Julien Kern
mbed library
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mbed official
Revision 89:552587b429a1, committed 2014-09-12
- Comitter:
- bogdanm
- Date:
- Fri Sep 12 16:41:52 2014 +0100
- Parent:
- 88:9327015d4013
- Child:
- 90:cb3d968589d8
- Commit message:
- Release 89 of the mbed library
Main changes:
- low power optimizations for Nordic targets
- code structure changes for Freescale K64F targets
- bug fixes in various backends
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_BLE/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_button.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,187 @@
+/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup app_button Button Handler
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Buttons handling module.
+ *
+ * @details The button handler uses the @ref app_gpiote to detect that a button has been
+ * pushed. To handle debouncing, it will start a timer in the GPIOTE event handler.
+ * The button will only be reported as pushed if the corresponding pin is still active when
+ * the timer expires. If there is a new GPIOTE event while the timer is running, the timer
+ * is restarted.
+ * Use the USE_SCHEDULER parameter of the APP_BUTTON_INIT() macro to select if the
+ * @ref app_scheduler is to be used or not.
+ *
+ * @note The app_button module uses the app_timer module. The user must ensure that the queue in
+ * app_timer is large enough to hold the app_timer_stop() / app_timer_start() operations
+ * which will be executed on each event from GPIOTE module (2 operations), as well as other
+ * app_timer operations queued simultaneously in the application.
+ *
+ * @note Even if the scheduler is not used, app_button.h will include app_scheduler.h, so when
+ * compiling, app_scheduler.h must be available in one of the compiler include paths.
+ */
+
+#ifndef APP_BUTTON_H__
+#define APP_BUTTON_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "app_error.h"
+#include "app_scheduler.h"
+#include "nrf_gpio.h"
+
+#define APP_BUTTON_SCHED_EVT_SIZE sizeof(app_button_event_t) /**< Size of button events being passed through the scheduler (is to be used for computing the maximum size of scheduler events). */
+#define APP_BUTTON_PUSH 1 /**< Indicates that a button is pushed. */
+#define APP_BUTTON_RELEASE 0 /**< Indicates that a button is released. */
+#define APP_BUTTON_ACTIVE_HIGH 1 /**< Indicates that a button is active high. */
+#define APP_BUTTON_ACTIVE_LOW 0 /**< Indicates that a button is active low. */
+
+/**@brief Button event handler type. */
+typedef void (*app_button_handler_t)(uint8_t pin_no, uint8_t button_action);
+
+/**@brief Type of function for passing events from the Button Handler module to the scheduler. */
+typedef uint32_t (*app_button_evt_schedule_func_t) (app_button_handler_t button_handler,
+ uint8_t pin_no,
+ uint8_t button_action);
+
+/**@brief Button configuration structure. */
+typedef struct
+{
+ uint8_t pin_no; /**< Pin to be used as a button. */
+ uint8_t active_state; /**< APP_BUTTON_ACTIVE_HIGH or APP_BUTTON_ACTIVE_LOW. */
+ nrf_gpio_pin_pull_t pull_cfg; /**< Pull-up or -down configuration. */
+ app_button_handler_t button_handler; /**< Handler to be called when button is pushed. */
+} app_button_cfg_t;
+
+/**@brief Pin transition direction struct. */
+typedef struct
+{
+ uint32_t high_to_low; /**Pin went from high to low */
+ uint32_t low_to_high; /**Pin went from low to high */
+} pin_transition_t;
+
+/**@brief Macro for initializing the Button Handler module.
+ *
+ * @details It will initialize the specified pins as buttons, and configure the Button Handler
+ * module as a GPIOTE user (but it will not enable button detection). It will also connect
+ * the Button Handler module to the scheduler (if specified).
+ *
+ * @param[in] BUTTONS Array of buttons to be used (type app_button_cfg_t, must be
+ * static!).
+ * @param[in] BUTTON_COUNT Number of buttons.
+ * @param[in] DETECTION_DELAY Delay from a GPIOTE event until a button is reported as pushed.
+ * @param[in] USE_SCHEDULER TRUE if the application is using the event scheduler,
+ * FALSE otherwise.
+ */
+/*lint -emacro(506, APP_BUTTON_INIT) */ /* Suppress "Constant value Boolean */
+#define APP_BUTTON_INIT(BUTTONS, BUTTON_COUNT, DETECTION_DELAY, USE_SCHEDULER) \
+ do \
+ { \
+ uint32_t ERR_CODE = app_button_init((BUTTONS), \
+ (BUTTON_COUNT), \
+ (DETECTION_DELAY), \
+ (USE_SCHEDULER) ? app_button_evt_schedule : NULL); \
+ APP_ERROR_CHECK(ERR_CODE); \
+ } while (0)
+
+/**@brief Function for initializing the Buttons.
+ *
+ * @details This function will initialize the specified pins as buttons, and configure the Button
+ * Handler module as a GPIOTE user (but it will not enable button detection).
+ *
+ * @note Normally initialization should be done using the APP_BUTTON_INIT() macro, as that will take
+ * care of connecting the Buttons module to the scheduler (if specified).
+ *
+ * @note app_button_enable() function must be called in order to enable the button detection.
+ *
+ * @param[in] p_buttons Array of buttons to be used (NOTE: Must be static!).
+ * @param[in] button_count Number of buttons.
+ * @param[in] detection_delay Delay from a GPIOTE event until a button is reported as pushed.
+ * @param[in] evt_schedule_func Function for passing button events to the scheduler. Point to
+ * app_button_evt_schedule() to connect to the scheduler. Set to
+ * NULL to make the Buttons module call the event handler directly
+ * from the delayed button push detection timeout handler.
+ *
+ * @return NRF_SUCCESS on success, otherwise an error code.
+ */
+uint32_t app_button_init(app_button_cfg_t * p_buttons,
+ uint8_t button_count,
+ uint32_t detection_delay,
+ app_button_evt_schedule_func_t evt_schedule_func);
+
+/**@brief Function for enabling button detection.
+ *
+ * @retval NRF_ERROR_INVALID_PARAM GPIOTE has to many users.
+ * @retval NRF_ERROR_INVALID_STATE Button or GPIOTE not initialized.
+ * @retval NRF_SUCCESS Button detection successfully enabled.
+ */
+uint32_t app_button_enable(void);
+
+/**@brief Function for disabling button detection.
+ *
+ * @retval NRF_ERROR_INVALID_PARAM GPIOTE has to many users.
+ * @retval NRF_ERROR_INVALID_STATE Button or GPIOTE not initialized.
+ * @retval NRF_SUCCESS Button detection successfully enabled.
+ */
+uint32_t app_button_disable(void);
+
+/**@brief Function for checking if a button is currently being pushed.
+ *
+ * @param[in] pin_no Button pin to be checked.
+ * @param[out] p_is_pushed Button state.
+ *
+ * @retval NRF_SUCCESS State successfully read.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid pin_no.
+ */
+uint32_t app_button_is_pushed(uint8_t pin_no, bool * p_is_pushed);
+
+
+// Type and functions for connecting the Buttons module to the scheduler:
+
+/**@cond NO_DOXYGEN */
+typedef struct
+{
+ app_button_handler_t button_handler;
+ uint8_t pin_no;
+ uint8_t button_action;
+} app_button_event_t;
+
+static __INLINE void app_button_evt_get(void * p_event_data, uint16_t event_size)
+{
+ app_button_event_t * p_buttons_event = (app_button_event_t *)p_event_data;
+
+ APP_ERROR_CHECK_BOOL(event_size == sizeof(app_button_event_t));
+ p_buttons_event->button_handler(p_buttons_event->pin_no, p_buttons_event->button_action);
+}
+
+static __INLINE uint32_t app_button_evt_schedule(app_button_handler_t button_handler,
+ uint8_t pin_no,
+ uint8_t button_action)
+{
+ app_button_event_t buttons_event;
+
+ buttons_event.button_handler = button_handler;
+ buttons_event.pin_no = pin_no;
+ buttons_event.button_action = button_action;
+
+ return app_sched_event_put(&buttons_event, sizeof(buttons_event), app_button_evt_get);
+}
+/**@endcond */
+
+#endif // APP_BUTTON_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_BLE/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_error.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,84 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup app_error Common application error handler
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Common application error handler and macros for utilizing a common error handler.
+ */
+
+#ifndef APP_ERROR_H__
+#define APP_ERROR_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "nrf_error.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@brief Function for error handling, which is called when an error has occurred.
+ *
+ * @param[in] error_code Error code supplied to the handler.
+ * @param[in] line_num Line number where the handler is called.
+ * @param[in] p_file_name Pointer to the file name.
+ */
+void app_error_handler(uint32_t error_code, uint32_t line_num, const uint8_t * p_file_name);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@brief Macro for calling error handler function.
+ *
+ * @param[in] ERR_CODE Error code supplied to the error handler.
+ */
+#define APP_ERROR_HANDLER(ERR_CODE) \
+ do \
+ { \
+ /* app_error_handler((ERR_CODE), __LINE__, (uint8_t*) __FILE__); */ \
+ } while (0)
+
+/**@brief Macro for calling error handler function if supplied error code any other than NRF_SUCCESS.
+ *
+ * @param[in] ERR_CODE Error code supplied to the error handler.
+ */
+#define APP_ERROR_CHECK(ERR_CODE) \
+ do \
+ { \
+ const uint32_t LOCAL_ERR_CODE = (ERR_CODE); \
+ if (LOCAL_ERR_CODE != NRF_SUCCESS) \
+ { \
+ APP_ERROR_HANDLER(LOCAL_ERR_CODE); \
+ } \
+ } while (0)
+
+/**@brief Macro for calling error handler function if supplied boolean value is false.
+ *
+ * @param[in] BOOLEAN_VALUE Boolean value to be evaluated.
+ */
+#define APP_ERROR_CHECK_BOOL(BOOLEAN_VALUE) \
+ do \
+ { \
+ const bool LOCAL_BOOLEAN_VALUE = (BOOLEAN_VALUE); \
+ if (!LOCAL_BOOLEAN_VALUE) \
+ { \
+ APP_ERROR_HANDLER(0); \
+ } \
+ } while (0)
+
+#endif // APP_ERROR_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_BLE/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_fifo.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,83 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/**@file
+ *
+ * @defgroup app_fifo FIFO implementation
+ * @{
+ * @ingroup app_common
+ *
+ * @brief FIFO implementation.
+ */
+
+#ifndef APP_FIFO_H__
+#define APP_FIFO_H__
+
+#include <stdint.h>
+#include <stdlib.h>
+#include "nrf_error.h"
+
+/**@brief A FIFO instance structure. Keeps track of which bytes to read and write next.
+ * Also it keeps the information about which memory is allocated for the buffer
+ * and its size. This needs to be initialized by app_fifo_init() before use.
+ */
+typedef struct
+{
+ uint8_t * p_buf; /**< Pointer to FIFO buffer memory. */
+ uint16_t buf_size_mask; /**< Read/write index mask. Also used for size checking. */
+ volatile uint32_t read_pos; /**< Next read position in the FIFO buffer. */
+ volatile uint32_t write_pos; /**< Next write position in the FIFO buffer. */
+} app_fifo_t;
+
+/**@brief Function for initializing the FIFO.
+ *
+ * @param[out] p_fifo FIFO object.
+ * @param[in] p_buf FIFO buffer for storing data. The buffer size has to be a power of two.
+ * @param[in] buf_size Size of the FIFO buffer provided, has to be a power of 2.
+ *
+ * @retval NRF_SUCCESS If initialization was successful.
+ * @retval NRF_ERROR_NULL If a NULL pointer is provided as buffer.
+ * @retval NRF_ERROR_INVALID_LENGTH If size of buffer provided is not a power of two.
+ */
+uint32_t app_fifo_init(app_fifo_t * p_fifo, uint8_t * p_buf, uint16_t buf_size);
+
+/**@brief Function for adding an element to the FIFO.
+ *
+ * @param[in] p_fifo Pointer to the FIFO.
+ * @param[in] byte Data byte to add to the FIFO.
+ *
+ * @retval NRF_SUCCESS If an element has been successfully added to the FIFO.
+ * @retval NRF_ERROR_NO_MEM If the FIFO is full.
+ */
+uint32_t app_fifo_put(app_fifo_t * p_fifo, uint8_t byte);
+
+/**@brief Function for getting the next element from the FIFO.
+ *
+ * @param[in] p_fifo Pointer to the FIFO.
+ * @param[out] p_byte Byte fetched from the FIFO.
+ *
+ * @retval NRF_SUCCESS If an element was returned.
+ * @retval NRF_ERROR_NOT_FOUND If there is no more elements in the queue.
+ */
+uint32_t app_fifo_get(app_fifo_t * p_fifo, uint8_t * p_byte);
+
+/**@brief Function for flushing the FIFO.
+ *
+ * @param[in] p_fifo Pointer to the FIFO.
+ *
+ * @retval NRF_SUCCESS If the FIFO flushed successfully.
+ */
+uint32_t app_fifo_flush(app_fifo_t * p_fifo);
+
+#endif // APP_FIFO_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_BLE/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_gpiote.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,226 @@
+/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup app_gpiote GPIOTE Handler
+ * @{
+ * @ingroup app_common
+ *
+ * @brief GPIOTE handler module.
+ *
+ * @details The GPIOTE handler allows several modules ("users") to share the GPIOTE interrupt,
+ * each user defining a set of pins able to generate events to the user.
+ * When a GPIOTE interrupt occurs, the GPIOTE interrupt handler will call the event handler
+ * of each user for which at least one of the pins generated an event.
+ *
+ * The GPIOTE users are responsible for configuring all their corresponding pins, except
+ * the SENSE field, which should be initialized to GPIO_PIN_CNF_SENSE_Disabled.
+ * The SENSE field will be updated by the GPIOTE module when it is enabled or disabled,
+ * and also while it is enabled.
+ *
+ * The module specifies on which pins events should be generated if the pin(s) goes
+ * from low->high or high->low or both directions.
+ *
+ * @note Even if the application is using the @ref app_scheduler, the GPIOTE event handlers will
+ * be called directly from the GPIOTE interrupt handler.
+ *
+ * @warning If multiple users registers for the same pins the behavior for those pins are undefined.
+ */
+
+#ifndef APP_GPIOTE_H__
+#define APP_GPIOTE_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+// #include "nrf.h"
+#include "app_error.h"
+#include "app_util.h"
+
+#ifdef __cpluplus
+extern "C" {
+#endif
+
+#define GPIOTE_USER_NODE_SIZE 20 /**< Size of app_gpiote.gpiote_user_t (only for use inside APP_GPIOTE_BUF_SIZE()). */
+#define NO_OF_PINS 32 /**< Number of GPIO pins on the nRF51 chip. */
+
+/**@brief Compute number of bytes required to hold the GPIOTE data structures.
+ *
+ * @param[in] MAX_USERS Maximum number of GPIOTE users.
+ *
+ * @return Required buffer size (in bytes).
+ */
+#define APP_GPIOTE_BUF_SIZE(MAX_USERS) ((MAX_USERS) * GPIOTE_USER_NODE_SIZE)
+
+typedef uint8_t app_gpiote_user_id_t;
+
+/**@brief GPIOTE event handler type. */
+typedef void (*app_gpiote_event_handler_t)(uint32_t event_pins_low_to_high,
+ uint32_t event_pins_high_to_low);
+
+/**@brief GPIOTE input event handler type. */
+typedef void (*app_gpiote_input_event_handler_t)(void);
+
+/**@brief Macro for initializing the GPIOTE module.
+ *
+ * @details It will handle dimensioning and allocation of the memory buffer required by the module,
+ * making sure that the buffer is correctly aligned.
+ *
+ * @param[in] MAX_USERS Maximum number of GPIOTE users.
+ *
+ * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it
+ * several times as long as it is from the same location, e.g. to do a reinitialization).
+ */
+/*lint -emacro(506, APP_GPIOTE_INIT) */ /* Suppress "Constant value Boolean */
+#define APP_GPIOTE_INIT(MAX_USERS) \
+ do \
+ { \
+ static uint32_t app_gpiote_buf[CEIL_DIV(APP_GPIOTE_BUF_SIZE(MAX_USERS), sizeof(uint32_t))];\
+ uint32_t ERR_CODE = app_gpiote_init((MAX_USERS), app_gpiote_buf); \
+ APP_ERROR_CHECK(ERR_CODE); \
+ } while (0)
+
+/**@brief Function for initializing the GPIOTE module.
+ *
+ * @note Normally initialization should be done using the APP_GPIOTE_INIT() macro, as that will
+ * allocate the buffer needed by the GPIOTE module (including aligning the buffer correctly).
+ *
+ * @param[in] max_users Maximum number of GPIOTE users.
+ * @param[in] p_buffer Pointer to memory buffer for internal use in the app_gpiote
+ * module. The size of the buffer can be computed using the
+ * APP_GPIOTE_BUF_SIZE() macro. The buffer must be aligned to
+ * a 4 byte boundary.
+ *
+ * @retval NRF_SUCCESS Successful initialization.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte
+ * boundary).
+ */
+uint32_t app_gpiote_init(uint8_t max_users, void * p_buffer);
+
+/**@brief Function for registering a GPIOTE user.
+ *
+ * @param[out] p_user_id Id for the new GPIOTE user.
+ * @param[in] pins_low_to_high_mask Mask defining which pins will generate events to this user
+ * when state is changed from low->high.
+ * @param[in] pins_high_to_low_mask Mask defining which pins will generate events to this user
+ * when state is changed from high->low.
+ * @param[in] event_handler Pointer to function to be executed when an event occurs.
+ *
+ * @retval NRF_SUCCESS Successful initialization.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte boundary).
+ * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE
+ * module.
+ * @retval NRF_ERROR_NO_MEM Returned if the application tries to register more users
+ * than defined when the GPIOTE module was initialized in
+ * @ref app_gpiote_init.
+ */
+uint32_t app_gpiote_user_register(app_gpiote_user_id_t * p_user_id,
+ uint32_t pins_low_to_high_mask,
+ uint32_t pins_high_to_low_mask,
+ app_gpiote_event_handler_t event_handler);
+
+/**@brief Function for informing the GPIOTE module that the specified user wants to use the GPIOTE module.
+ *
+ * @param[in] user_id Id of user to enable.
+ *
+ * @retval NRF_SUCCESS On success.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid user_id provided, No a valid user.
+ * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE
+ * module.
+ */
+uint32_t app_gpiote_user_enable(app_gpiote_user_id_t user_id);
+
+/**@brief Function for informing the GPIOTE module that the specified user is done using the GPIOTE module.
+ *
+ * @param[in] user_id Id of user to enable.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid user_id provided, No a valid user.
+ * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE
+ * module.
+ */
+uint32_t app_gpiote_user_disable(app_gpiote_user_id_t user_id);
+
+/**@brief Function for getting the state of the pins which are registered for the specified user.
+ *
+ * @param[in] user_id Id of user to check.
+ * @param[out] p_pins Bit mask corresponding to the pins configured to generate events to
+ * the specified user. All bits corresponding to pins in the state
+ * 'high' will have value '1', all others will have value '0'.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid user_id provided, No a valid user.
+ * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE
+ * module.
+ */
+uint32_t app_gpiote_pins_state_get(app_gpiote_user_id_t user_id, uint32_t * p_pins);
+
+/**@brief Function for registering event handlers for GPIOTE IN events.
+ *
+ * @param[in] channel GPIOTE channel [0..3].
+ * @param[in] pin Pins associated with GPIOTE channel. Changes on following pins will generate events.
+ * @param[in] polarity Specify operation on input that shall trigger IN event.
+ * @param[in] event_handler Event handler invoked on the IN event in the GPIOTE interrupt.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid channel or pin number.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events.
+ */
+uint32_t app_gpiote_input_event_handler_register(const uint8_t channel,
+ const uint32_t pin,
+ const uint32_t polarity,
+ app_gpiote_input_event_handler_t event_handler);
+
+/**@brief Function for unregistering event handlers for GPIOTE IN events.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events.
+ */
+uint32_t app_gpiote_input_event_handler_unregister(const uint8_t channel);
+
+/**@brief Function for registering event handler invoked at the end of a GPIOTE interrupt.
+ *
+ * @param[in] event_handler Event handler invoked at the end of the GPIOTE interrupt.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events.
+ */
+uint32_t app_gpiote_end_irq_event_handler_register(app_gpiote_input_event_handler_t event_handler);
+
+/**@brief Function for unregistering event handler invoked at the end of a GPIOTE interrupt.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events.
+ */
+uint32_t app_gpiote_end_irq_event_handler_unregister(void);
+
+/**@brief Function for enabling interrupts in the GPIOTE driver.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support.
+ */
+uint32_t app_gpiote_enable_interrupts(void);
+
+/**@brief Function for disabling interrupts in the GPIOTE driver.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support.
+ */
+uint32_t app_gpiote_disable_interrupts(void);
+
+#ifdef __cpluplus
+}
+#endif
+
+#endif // APP_GPIOTE_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_BLE/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_scheduler.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,134 @@
+/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup app_scheduler Scheduler
+ * @{
+ * @ingroup app_common
+ *
+ * @brief The scheduler is used for transferring execution from the interrupt context to the main
+ * context.
+ *
+ * @details See @ref ble_sdk_apps_seq_diagrams for sequence diagrams illustrating the flow of events
+ * when using the Scheduler.
+ *
+ * @section app_scheduler_req Requirements:
+ *
+ * @subsection main_context_logic Logic in main context:
+ *
+ * - Define an event handler for each type of event expected.
+ * - Initialize the scheduler by calling the APP_SCHED_INIT() macro before entering the
+ * application main loop.
+ * - Call app_sched_execute() from the main loop each time the application wakes up because of an
+ * event (typically when sd_app_evt_wait() returns).
+ *
+ * @subsection int_context_logic Logic in interrupt context:
+ *
+ * - In the interrupt handler, call app_sched_event_put()
+ * with the appropriate data and event handler. This will insert an event into the
+ * scheduler's queue. The app_sched_execute() function will pull this event and call its
+ * handler in the main context.
+ *
+ * For an example usage of the scheduler, please see the implementations of
+ * @ref ble_sdk_app_hids_mouse and @ref ble_sdk_app_hids_keyboard.
+ *
+ * @image html scheduler_working.jpg The high level design of the scheduler
+ */
+
+#ifndef APP_SCHEDULER_H__
+#define APP_SCHEDULER_H__
+
+#include <stdint.h>
+#include "app_error.h"
+
+#define APP_SCHED_EVENT_HEADER_SIZE 8 /**< Size of app_scheduler.event_header_t (only for use inside APP_SCHED_BUF_SIZE()). */
+
+/**@brief Compute number of bytes required to hold the scheduler buffer.
+ *
+ * @param[in] EVENT_SIZE Maximum size of events to be passed through the scheduler.
+ * @param[in] QUEUE_SIZE Number of entries in scheduler queue (i.e. the maximum number of events
+ * that can be scheduled for execution).
+ *
+ * @return Required scheduler buffer size (in bytes).
+ */
+#define APP_SCHED_BUF_SIZE(EVENT_SIZE, QUEUE_SIZE) \
+ (((EVENT_SIZE) + APP_SCHED_EVENT_HEADER_SIZE) * ((QUEUE_SIZE) + 1))
+
+/**@brief Scheduler event handler type. */
+typedef void (*app_sched_event_handler_t)(void * p_event_data, uint16_t event_size);
+
+/**@brief Macro for initializing the event scheduler.
+ *
+ * @details It will also handle dimensioning and allocation of the memory buffer required by the
+ * scheduler, making sure the buffer is correctly aligned.
+ *
+ * @param[in] EVENT_SIZE Maximum size of events to be passed through the scheduler.
+ * @param[in] QUEUE_SIZE Number of entries in scheduler queue (i.e. the maximum number of events
+ * that can be scheduled for execution).
+ *
+ * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it
+ * several times as long as it is from the same location, e.g. to do a reinitialization).
+ */
+#define APP_SCHED_INIT(EVENT_SIZE, QUEUE_SIZE) \
+ do \
+ { \
+ static uint32_t APP_SCHED_BUF[CEIL_DIV(APP_SCHED_BUF_SIZE((EVENT_SIZE), (QUEUE_SIZE)), \
+ sizeof(uint32_t))]; \
+ uint32_t ERR_CODE = app_sched_init((EVENT_SIZE), (QUEUE_SIZE), APP_SCHED_BUF); \
+ APP_ERROR_CHECK(ERR_CODE); \
+ } while (0)
+
+/**@brief Function for initializing the Scheduler.
+ *
+ * @details It must be called before entering the main loop.
+ *
+ * @param[in] max_event_size Maximum size of events to be passed through the scheduler.
+ * @param[in] queue_size Number of entries in scheduler queue (i.e. the maximum number of
+ * events that can be scheduled for execution).
+ * @param[in] p_event_buffer Pointer to memory buffer for holding the scheduler queue. It must
+ * be dimensioned using the APP_SCHED_BUFFER_SIZE() macro. The buffer
+ * must be aligned to a 4 byte boundary.
+ *
+ * @note Normally initialization should be done using the APP_SCHED_INIT() macro, as that will both
+ * allocate the scheduler buffer, and also align the buffer correctly.
+ *
+ * @retval NRF_SUCCESS Successful initialization.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte
+ * boundary).
+ */
+uint32_t app_sched_init(uint16_t max_event_size, uint16_t queue_size, void * p_evt_buffer);
+
+/**@brief Function for executing all scheduled events.
+ *
+ * @details This function must be called from within the main loop. It will execute all events
+ * scheduled since the last time it was called.
+ */
+void app_sched_execute(void);
+
+/**@brief Function for scheduling an event.
+ *
+ * @details Puts an event into the event queue.
+ *
+ * @param[in] p_event_data Pointer to event data to be scheduled.
+ * @param[in] p_event_size Size of event data to be scheduled.
+ * @param[in] handler Event handler to receive the event.
+ *
+ * @return NRF_SUCCESS on success, otherwise an error code.
+ */
+uint32_t app_sched_event_put(void * p_event_data,
+ uint16_t event_size,
+ app_sched_event_handler_t handler);
+
+#endif // APP_SCHEDULER_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_BLE/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_timer.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,313 @@
+/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup app_timer Application Timer
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Application timer functionality.
+ *
+ * @details It enables the application to create multiple timer instances based on the RTC1
+ * peripheral. Checking for timeouts and invokation of user timeout handlers is performed
+ * in the RTC1 interrupt handler. List handling is done using a software interrupt (SWI0).
+ * Both interrupt handlers are running in APP_LOW priority level.
+ *
+ * @note When calling app_timer_start() or app_timer_stop(), the timer operation is just queued,
+ * and the software interrupt is triggered. The actual timer start/stop operation is
+ * executed by the SWI0 interrupt handler. Since the SWI0 interrupt is running in APP_LOW,
+ * if the application code calling the timer function is running in APP_LOW or APP_HIGH,
+ * the timer operation will not be performed until the application handler has returned.
+ * This will be the case e.g. when stopping a timer from a timeout handler when not using
+ * the scheduler.
+ *
+ * @details Use the USE_SCHEDULER parameter of the APP_TIMER_INIT() macro to select if the
+ * @ref app_scheduler is to be used or not.
+ *
+ * @note Even if the scheduler is not used, app_timer.h will include app_scheduler.h, so when
+ * compiling, app_scheduler.h must be available in one of the compiler include paths.
+ */
+
+#ifndef APP_TIMER_H__
+#define APP_TIMER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include "app_error.h"
+#include "app_util.h"
+#include "app_scheduler.h"
+#include "compiler_abstraction.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif // #ifdef __cplusplus
+
+#define APP_TIMER_SCHED_EVT_SIZE sizeof(app_timer_event_t) /**< Size of button events being passed through the scheduler (is to be used for computing the maximum size of scheduler events). */
+#define APP_TIMER_CLOCK_FREQ 32768 /**< Clock frequency of the RTC timer used to implement the app timer module. */
+#define APP_TIMER_MIN_TIMEOUT_TICKS 5 /**< Minimum value of the timeout_ticks parameter of app_timer_start(). */
+
+#define APP_TIMER_NODE_SIZE 40 /**< Size of app_timer.timer_node_t (only for use inside APP_TIMER_BUF_SIZE()). */
+#define APP_TIMER_USER_OP_SIZE 24 /**< Size of app_timer.timer_user_op_t (only for use inside APP_TIMER_BUF_SIZE()). */
+#define APP_TIMER_USER_SIZE 8 /**< Size of app_timer.timer_user_t (only for use inside APP_TIMER_BUF_SIZE()). */
+#define APP_TIMER_INT_LEVELS 3 /**< Number of interrupt levels from where timer operations may be initiated (only for use inside APP_TIMER_BUF_SIZE()). */
+
+#define MAX_RTC_COUNTER_VAL 0x00FFFFFF /**< Maximum value of the RTC counter. */
+
+/**@brief Compute number of bytes required to hold the application timer data structures.
+ *
+ * @param[in] MAX_TIMERS Maximum number of timers that can be created at any given time.
+ * @param[in] OP_QUEUE_SIZE Size of queues holding timer operations that are pending execution.
+ * NOTE: Due to the queue implementation, this size must be one more
+ * than the size that is actually needed.
+ *
+ * @return Required application timer buffer size (in bytes).
+ */
+#define APP_TIMER_BUF_SIZE(MAX_TIMERS, OP_QUEUE_SIZE) \
+ ( \
+ ((MAX_TIMERS) * APP_TIMER_NODE_SIZE) \
+ + \
+ ( \
+ APP_TIMER_INT_LEVELS \
+ * \
+ (APP_TIMER_USER_SIZE + ((OP_QUEUE_SIZE) + 1) * APP_TIMER_USER_OP_SIZE) \
+ ) \
+ )
+
+/**@brief Convert milliseconds to timer ticks.
+ *
+ * @note This macro uses 64 bit integer arithmetic, but as long as the macro parameters are
+ * constants (i.e. defines), the computation will be done by the preprocessor.
+ *
+ * @param[in] MS Milliseconds.
+ * @param[in] PRESCALER Value of the RTC1 PRESCALER register (must be the same value that was
+ * passed to APP_TIMER_INIT()).
+ *
+ * @note When using this macro, it is the responsibility of the developer to ensure that the
+ * values provided as input result in an output value that is supported by the
+ * @ref app_timer_start function. For example, when the ticks for 1 ms is needed, the
+ * maximum possible value of PRESCALER must be 6, when @ref APP_TIMER_CLOCK_FREQ is 32768.
+ * This will result in a ticks value as 5. Any higher value for PRESCALER will result in a
+ * ticks value that is not supported by this module.
+ *
+ * @return Number of timer ticks.
+ */
+#define APP_TIMER_TICKS(MS, PRESCALER)\
+ ((uint32_t)ROUNDED_DIV((MS) * (uint64_t)APP_TIMER_CLOCK_FREQ, ((PRESCALER) + 1) * 1000))
+
+/**@brief Timer id type. */
+typedef uint32_t app_timer_id_t;
+
+#define TIMER_NULL ((app_timer_id_t)(0 - 1)) /**< Invalid timer id. */
+
+/**@brief Application timeout handler type. */
+typedef void (*app_timer_timeout_handler_t)(void * p_context);
+
+/**@brief Type of function for passing events from the timer module to the scheduler. */
+typedef uint32_t (*app_timer_evt_schedule_func_t) (app_timer_timeout_handler_t timeout_handler,
+ void * p_context);
+
+/**@brief Timer modes. */
+typedef enum
+{
+ APP_TIMER_MODE_SINGLE_SHOT, /**< The timer will expire only once. */
+ APP_TIMER_MODE_REPEATED /**< The timer will restart each time it expires. */
+} app_timer_mode_t;
+
+/**@brief Macro for initializing the application timer module.
+ *
+ * @details It will handle dimensioning and allocation of the memory buffer required by the timer,
+ * making sure that the buffer is correctly aligned. It will also connect the timer module
+ * to the scheduler (if specified).
+ *
+ * @note This module assumes that the LFCLK is already running. If it isn't, the module will
+ * be non-functional, since the RTC will not run. If you don't use a softdevice, you'll
+ * have to start the LFCLK manually. See the rtc_example's \ref lfclk_config() function
+ * for an example of how to do this. If you use a softdevice, the LFCLK is started on
+ * softdevice init.
+ *
+ *
+ * @param[in] PRESCALER Value of the RTC1 PRESCALER register. This will decide the
+ * timer tick rate. Set to 0 for no prescaling.
+ * @param[in] MAX_TIMERS Maximum number of timers that can be created at any given time.
+ * @param[in] OP_QUEUES_SIZE Size of queues holding timer operations that are pending execution.
+ * @param[in] USE_SCHEDULER TRUE if the application is using the event scheduler,
+ * FALSE otherwise.
+ *
+ * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it
+ * several times as long as it is from the same location, e.g. to do a reinitialization).
+ */
+/*lint -emacro(506, APP_TIMER_INIT) */ /* Suppress "Constant value Boolean */
+#define APP_TIMER_INIT(PRESCALER, MAX_TIMERS, OP_QUEUES_SIZE, USE_SCHEDULER) \
+ do \
+ { \
+ static uint32_t APP_TIMER_BUF[CEIL_DIV(APP_TIMER_BUF_SIZE((MAX_TIMERS), \
+ (OP_QUEUES_SIZE) + 1), \
+ sizeof(uint32_t))]; \
+ uint32_t ERR_CODE = app_timer_init((PRESCALER), \
+ (MAX_TIMERS), \
+ (OP_QUEUES_SIZE) + 1, \
+ APP_TIMER_BUF, \
+ (USE_SCHEDULER) ? app_timer_evt_schedule : NULL); \
+ APP_ERROR_CHECK(ERR_CODE); \
+ } while (0)
+
+/**@brief Function for initializing the timer module.
+ *
+ * @note Normally initialization should be done using the APP_TIMER_INIT() macro, as that will both
+ * allocate the buffers needed by the timer module (including aligning the buffers correctly,
+ * and also take care of connecting the timer module to the scheduler (if specified).
+ *
+ * @param[in] prescaler Value of the RTC1 PRESCALER register. Set to 0 for no prescaling.
+ * @param[in] max_timers Maximum number of timers that can be created at any given time.
+ * @param[in] op_queues_size Size of queues holding timer operations that are pending
+ * execution. NOTE: Due to the queue implementation, this size must
+ * be one more than the size that is actually needed.
+ * @param[in] p_buffer Pointer to memory buffer for internal use in the app_timer
+ * module. The size of the buffer can be computed using the
+ * APP_TIMER_BUF_SIZE() macro. The buffer must be aligned to a
+ * 4 byte boundary.
+ * @param[in] evt_schedule_func Function for passing timeout events to the scheduler. Point to
+ * app_timer_evt_schedule() to connect to the scheduler. Set to NULL
+ * to make the timer module call the timeout handler directly from
+ * the timer interrupt handler.
+ *
+ * @retval NRF_SUCCESS Successful initialization.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte
+ * boundary or NULL).
+ */
+uint32_t app_timer_init(uint32_t prescaler,
+ uint8_t max_timers,
+ uint8_t op_queues_size,
+ void * p_buffer,
+ app_timer_evt_schedule_func_t evt_schedule_func);
+
+/**@brief Function for creating a timer instance.
+ *
+ * @param[out] p_timer_id Id of the newly created timer.
+ * @param[in] mode Timer mode.
+ * @param[in] timeout_handler Function to be executed when the timer expires.
+ *
+ * @retval NRF_SUCCESS Timer was successfully created.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter.
+ * @retval NRF_ERROR_INVALID_STATE Application timer module has not been initialized.
+ * @retval NRF_ERROR_NO_MEM Maximum number of timers has already been reached.
+ *
+ * @note This function does the timer allocation in the caller's context. It is also not protected
+ * by a critical region. Therefore care must be taken not to call it from several interrupt
+ * levels simultaneously.
+ */
+uint32_t app_timer_create(app_timer_id_t * p_timer_id,
+ app_timer_mode_t mode,
+ app_timer_timeout_handler_t timeout_handler);
+
+/**@brief Function for starting a timer.
+ *
+ * @param[in] timer_id Id of timer to start.
+ * @param[in] timeout_ticks Number of ticks (of RTC1, including prescaling) to timeout event
+ * (minimum 5 ticks).
+ * @param[in] p_context General purpose pointer. Will be passed to the timeout handler when
+ * the timer expires.
+ *
+ * @retval NRF_SUCCESS Timer was successfully started.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter.
+ * @retval NRF_ERROR_INVALID_STATE Application timer module has not been initialized, or timer
+ * has not been created.
+ * @retval NRF_ERROR_NO_MEM Timer operations queue was full.
+ *
+ * @note The minimum timeout_ticks value is 5.
+ * @note For multiple active timers, timeouts occurring in close proximity to each other (in the
+ * range of 1 to 3 ticks) will have a positive jitter of maximum 3 ticks.
+ * @note When calling this method on a timer which is already running, the second start operation
+ * will be ignored.
+ */
+uint32_t app_timer_start(app_timer_id_t timer_id, uint32_t timeout_ticks, void * p_context);
+
+/**@brief Function for stopping the specified timer.
+ *
+ * @param[in] timer_id Id of timer to stop.
+ *
+ * @retval NRF_SUCCESS Timer was successfully stopped.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter.
+ * @retval NRF_ERROR_INVALID_STATE Application timer module has not been initialized, or timer
+ * has not been created.
+ * @retval NRF_ERROR_NO_MEM Timer operations queue was full.
+ */
+uint32_t app_timer_stop(app_timer_id_t timer_id);
+
+/**@brief Function for stopping all running timers.
+ *
+ * @retval NRF_SUCCESS All timers were successfully stopped.
+ * @retval NRF_ERROR_INVALID_STATE Application timer module has not been initialized.
+ * @retval NRF_ERROR_NO_MEM Timer operations queue was full.
+ */
+uint32_t app_timer_stop_all(void);
+
+/**@brief Function for returning the current value of the RTC1 counter. The
+ * value includes overflow bits to extend the range to 64-bits.
+ *
+ * @param[out] p_ticks Current value of the RTC1 counter.
+ *
+ * @retval NRF_SUCCESS Counter was successfully read.
+ */
+uint32_t app_timer_cnt_get(uint64_t * p_ticks);
+
+/**@brief Function for computing the difference between two RTC1 counter values.
+ *
+ * @param[in] ticks_to Value returned by app_timer_cnt_get().
+ * @param[in] ticks_from Value returned by app_timer_cnt_get().
+ * @param[out] p_ticks_diff Number of ticks from ticks_from to ticks_to.
+ *
+ * @retval NRF_SUCCESS Counter difference was successfully computed.
+ */
+uint32_t app_timer_cnt_diff_compute(uint32_t ticks_to,
+ uint32_t ticks_from,
+ uint32_t * p_ticks_diff);
+
+
+// Type and functions for connecting the timer to the scheduler:
+
+/**@cond NO_DOXYGEN */
+typedef struct
+{
+ app_timer_timeout_handler_t timeout_handler;
+ void * p_context;
+} app_timer_event_t;
+
+static __INLINE void app_timer_evt_get(void * p_event_data, uint16_t event_size)
+{
+ app_timer_event_t * p_timer_event = (app_timer_event_t *)p_event_data;
+
+ APP_ERROR_CHECK_BOOL(event_size == sizeof(app_timer_event_t));
+ p_timer_event->timeout_handler(p_timer_event->p_context);
+}
+
+static __INLINE uint32_t app_timer_evt_schedule(app_timer_timeout_handler_t timeout_handler,
+ void * p_context)
+{
+ app_timer_event_t timer_event;
+
+ timer_event.timeout_handler = timeout_handler;
+ timer_event.p_context = p_context;
+
+ return app_sched_event_put(&timer_event, sizeof(timer_event), app_timer_evt_get);
+}
+/**@endcond */
+
+#ifdef __cplusplus
+}
+#endif // #ifdef __cplusplus
+
+#endif // APP_TIMER_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_BLE/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_trace.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,55 @@
+#ifndef __DEBUG_H_
+#define __DEBUG_H_
+
+#include <stdint.h>
+#include <stdio.h>
+
+/**
+ * @defgroup app_trace Debug Logger
+ * @ingroup app_common
+ * @{
+ * @brief Enables debug logs/ trace over UART.
+ * @details Enables debug logs/ trace over UART. Tracing is enabled only if
+ * ENABLE_DEBUG_LOG_SUPPORT is defined in the project.
+ */
+#ifdef ENABLE_DEBUG_LOG_SUPPORT
+/**
+ * @brief Module Initialization.
+ *
+ * @details Initializes the module to use UART as trace output.
+ *
+ * @warning This function will configure UART using default board configuration (described in @ref nrf51_setups).
+ * Do not call this function if UART is configured from a higher level in the application.
+ */
+void app_trace_init(void);
+
+/**
+ * @brief Log debug messages.
+ *
+ * @details This API logs messages over UART. The module must be initialized before using this API.
+ *
+ * @note Though this is currently a macro, it should be used used and treated as function.
+ */
+#define app_trace_log printf
+
+/**
+ * @brief Dump auxiliary byte buffer to the debug trace.
+ *
+ * @details This API logs messages over UART. The module must be initialized before using this API.
+ *
+ * @param[in] p_buffer Buffer to be dumped on the debug trace.
+ * @param[in] len Size of the buffer.
+ */
+void app_trace_dump(uint8_t * p_buffer, uint32_t len);
+
+#else // ENABLE_DEBUG_LOG_SUPPORT
+
+#define app_trace_init(...)
+#define app_trace_log(...)
+#define app_trace_dump(...)
+
+#endif // ENABLE_DEBUG_LOG_SUPPORT
+
+/** @} */
+
+#endif //__DEBUG_H_
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_BLE/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_uart.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,286 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/**@file
+ *
+ * @defgroup app_uart UART module
+ * @{
+ * @ingroup app_common
+ *
+ * @brief UART module interface.
+ */
+
+#ifndef APP_UART_H__
+#define APP_UART_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "app_util_platform.h"
+
+#define UART_PIN_DISCONNECTED 0xFFFFFFFF /**< Value indicating that no pin is connected to this UART register. */
+
+/**@brief UART Flow Control modes for the peripheral.
+ */
+typedef enum
+{
+ APP_UART_FLOW_CONTROL_DISABLED, /**< UART Hw Flow Control is disabled. */
+ APP_UART_FLOW_CONTROL_ENABLED, /**< Standard UART Hw Flow Control is enabled. */
+ APP_UART_FLOW_CONTROL_LOW_POWER /**< Specialized UART Hw Flow Control is used. The Low Power setting allows the nRF51 to Power Off the UART module when CTS is in-active, and re-enabling the UART when the CTS signal becomes active. This allows the nRF51 to safe power by only using the UART module when it is needed by the remote site. */
+} app_uart_flow_control_t;
+
+/**@brief UART communication structure holding configuration settings for the peripheral.
+ */
+typedef struct
+{
+ uint8_t rx_pin_no; /**< RX pin number. */
+ uint8_t tx_pin_no; /**< TX pin number. */
+ uint8_t rts_pin_no; /**< RTS pin number, only used if flow control is enabled. */
+ uint8_t cts_pin_no; /**< CTS pin number, only used if flow control is enabled. */
+ app_uart_flow_control_t flow_control; /**< Flow control setting, if flow control is used, the system will use low power UART mode, based on CTS signal. */
+ bool use_parity; /**< Even parity if TRUE, no parity if FALSE. */
+ uint32_t baud_rate; /**< Baud rate configuration. */
+} app_uart_comm_params_t;
+
+/**@brief UART buffer for transmitting/receiving data.
+ */
+typedef struct
+{
+ uint8_t * rx_buf; /**< Pointer to the RX buffer. */
+ uint32_t rx_buf_size; /**< Size of the RX buffer. */
+ uint8_t * tx_buf; /**< Pointer to the TX buffer. */
+ uint32_t tx_buf_size; /**< Size of the TX buffer. */
+} app_uart_buffers_t;
+
+/**@brief Enumeration describing current state of the UART.
+ *
+ * @details The connection state can be fetched by the application using the function call
+ * @ref app_uart_get_connection_state.
+ * When hardware flow control is used
+ * - APP_UART_CONNECTED: Communication is ongoing.
+ * - APP_UART_DISCONNECTED: No communication is ongoing.
+ *
+ * When no hardware flow control is used
+ * - APP_UART_CONNECTED: Always returned as bytes can always be received/transmitted.
+ */
+typedef enum
+{
+ APP_UART_DISCONNECTED, /**< State indicating that the UART is disconnected and cannot receive or transmit bytes. */
+ APP_UART_CONNECTED /**< State indicating that the UART is connected and ready to receive or transmit bytes. If flow control is disabled, the state will always be connected. */
+} app_uart_connection_state_t;
+
+/**@brief Enumeration which defines events used by the UART module upon data reception or error.
+ *
+ * @details The event type is used to indicate the type of additional information in the event
+ * @ref app_uart_evt_t.
+ */
+typedef enum
+{
+ APP_UART_DATA_READY, /**< An event indicating that UART data has been received. The data is available in the FIFO and can be fetched using @ref app_uart_get. */
+ APP_UART_FIFO_ERROR, /**< An error in the FIFO module used by the app_uart module has occured. The FIFO error code is stored in app_uart_evt_t.data.error_code field. */
+ APP_UART_COMMUNICATION_ERROR, /**< An communication error has occured during reception. The error is stored in app_uart_evt_t.data.error_communication field. */
+ APP_UART_TX_EMPTY, /**< An event indicating that UART has completed transmission of all available data in the TX FIFO. */
+ APP_UART_DATA, /**< An event indicating that UART data has been received, and data is present in data field. This event is only used when no FIFO is configured. */
+} app_uart_evt_type_t;
+
+/**@brief Struct containing events from the UART module.
+ *
+ * @details The app_uart_evt_t is used to notify the application of asynchronous events when data
+ * are received on the UART peripheral or in case an error occured during data reception.
+ */
+typedef struct
+{
+ app_uart_evt_type_t evt_type; /**< Type of event. */
+ union
+ {
+ uint32_t error_communication; /**< Field used if evt_type is: APP_UART_COMMUNICATION_ERROR. This field contains the value in the ERRORSRC register for the UART peripheral. The UART_ERRORSRC_x defines from @ref nrf51_bitfields.h can be used to parse the error code. See also the nRF51 Series Reference Manual for specification. */
+ uint32_t error_code; /**< Field used if evt_type is: NRF_ERROR_x. Additional status/error code if the error event type is APP_UART_FIFO_ERROR. This error code refer to errors defined in nrf_error.h. */
+ uint8_t value; /**< Field used if evt_type is: NRF_ERROR_x. Additional status/error code if the error event type is APP_UART_FIFO_ERROR. This error code refer to errors defined in nrf_error.h. */
+ } data;
+} app_uart_evt_t;
+
+/**@brief Function for handling app_uart event callback.
+ *
+ * @details Upon an event in the app_uart module this callback function will be called to notify
+ * the applicatioon about the event.
+ *
+ * @param[in] p_app_uart_event Pointer to UART event.
+ */
+
+
+typedef void (* app_uart_event_handler_t) (app_uart_evt_t * p_app_uart_event);
+
+/**@brief Macro for safe initialization of the UART module in a single user instance when using
+ * a FIFO together with UART.
+ *
+ * @param[in] P_COMM_PARAMS Pointer to a UART communication structure: app_uart_comm_params_t
+ * @param[in] RX_BUF_SIZE Size of desired RX buffer, must be a power of 2 or ZERO (No FIFO).
+ * @param[in] TX_BUF_SIZE Size of desired TX buffer, must be a power of 2 or ZERO (No FIFO).
+ * @param[in] EVENT_HANDLER Event handler function to be called when an event occurs in the
+ * UART module.
+ * @param[in] IRQ_PRIO IRQ priority, app_irq_priority_t, for the UART module irq handler.
+ * @param[out] ERR_CODE The return value of the UART initialization function will be
+ * written to this parameter.
+ *
+ * @note Since this macro allocates a buffer and registers the module as a GPIOTE user when flow
+ * control is enabled, it must only be called once.
+ */
+#define APP_UART_FIFO_INIT(P_COMM_PARAMS, RX_BUF_SIZE, TX_BUF_SIZE, EVT_HANDLER, IRQ_PRIO, ERR_CODE) \
+ do \
+ { \
+ uint16_t APP_UART_UID = 0; \
+ app_uart_buffers_t buffers; \
+ static uint8_t rx_buf[RX_BUF_SIZE]; \
+ static uint8_t tx_buf[TX_BUF_SIZE]; \
+ \
+ buffers.rx_buf = rx_buf; \
+ buffers.rx_buf_size = sizeof (rx_buf); \
+ buffers.tx_buf = tx_buf; \
+ buffers.tx_buf_size = sizeof (tx_buf); \
+ ERR_CODE = app_uart_init(P_COMM_PARAMS, &buffers, EVT_HANDLER, IRQ_PRIO, &APP_UART_UID); \
+ } while (0)
+
+/**@brief Macro for safe initialization of the UART module in a single user instance.
+ *
+ * @param[in] P_COMM_PARAMS Pointer to a UART communication structure: app_uart_comm_params_t
+ * @param[in] EVENT_HANDLER Event handler function to be called when an event occurs in the
+ * UART module.
+ * @param[in] IRQ_PRIO IRQ priority, app_irq_priority_t, for the UART module irq handler.
+ * @param[out] ERR_CODE The return value of the UART initialization function will be
+ * written to this parameter.
+ *
+ * @note Since this macro allocates registers the module as a GPIOTE user when flow control is
+ * enabled, it must only be called once.
+ */
+#define APP_UART_INIT(P_COMM_PARAMS, EVT_HANDLER, IRQ_PRIO, ERR_CODE) \
+ do \
+ { \
+ uint16_t APP_UART_UID = 0; \
+ ERR_CODE = app_uart_init(P_COMM_PARAMS, NULL, EVT_HANDLER, IRQ_PRIO, &APP_UART_UID); \
+ } while (0)
+
+/**@brief Function for initializing the UART module. Use this initialization when several instances of the UART
+ * module are needed.
+ *
+ * @details This initialization will return a UART user id for the caller. The UART user id must be
+ * used upon re-initialization of the UART or closing of the module for the user.
+ * If single instance usage is needed, the APP_UART_INIT() macro should be used instead.
+ *
+ * @note Normally single instance initialization should be done using the APP_UART_INIT() or
+ * APP_UART_INIT_FIFO() macro depending on whether the FIFO should be used by the UART, as
+ * that will allocate the buffers needed by the UART module (including aligning the buffer
+ * correctly).
+
+ * @param[in] p_comm_params Pin and communication parameters.
+ * @param[in] p_buffers RX and TX buffers, NULL is FIFO is not used.
+ * @param[in] error_handler Function to be called in case of an error.
+ * @param[in] app_irq_priority Interrupt priority level.
+ * @param[in,out] p_uart_uid User id for the UART module. The p_uart_uid must be used if
+ * re-initialization and/or closing of the UART module is needed.
+ * If the value pointed to by p_uart_uid is zero, this is
+ * considdered a first time initialization. Otherwise this is
+ * considered a re-initialization for the user with id *p_uart_uid.
+ *
+ * @retval NRF_SUCCESS If successful initialization.
+ * @retval NRF_ERROR_INVALID_LENGTH If a provided buffer is not a power of two.
+ * @retval NRF_ERROR_NULL If one of the provided buffers is a NULL pointer.
+ *
+ * Those errors are propagated by the UART module to the caller upon registration when Hardware Flow
+ * Control is enabled. When Hardware Flow Control is not used, those errors cannot occur.
+ * @retval NRF_ERROR_INVALID_STATE The GPIOTE module is not in a valid state when registering
+ * the UART module as a user.
+ * @retval NRF_ERROR_INVALID_PARAM The UART module provides an invalid callback function when
+ * registering the UART module as a user.
+ * Or the value pointed to by *p_uart_uid is not a valid
+ * GPIOTE number.
+ * @retval NRF_ERROR_NO_MEM GPIOTE module has reached the maximum number of users.
+ */
+uint32_t app_uart_init(const app_uart_comm_params_t * p_comm_params,
+ app_uart_buffers_t * p_buffers,
+ app_uart_event_handler_t error_handler,
+ app_irq_priority_t irq_priority,
+ uint16_t * p_uart_uid);
+
+/**@brief Function for getting a byte from the UART.
+ *
+ * @details This function will get the next byte from the RX buffer. If the RX buffer is empty
+ * an error code will be returned and the app_uart module will generate an event upon
+ * reception of the first byte which is added to the RX buffer.
+ *
+ * @param[out] p_byte Pointer to an address where next byte received on the UART will be copied.
+ *
+ * @retval NRF_SUCCESS If a byte has been received and pushed to the pointer provided.
+ * @retval NRF_ERROR_NOT_FOUND If no byte is available in the RX buffer of the app_uart module.
+ */
+uint32_t app_uart_get(uint8_t * p_byte);
+
+/**@brief Function for putting a byte on the UART.
+ *
+ * @details This call is non-blocking.
+ *
+ * @param[in] byte Byte to be transmitted on the UART.
+ *
+ * @retval NRF_SUCCESS If the byte was succesfully put on the TX buffer for transmission.
+ * @retval NRF_ERROR_NO_MEM If no more space is available in the TX buffer.
+ * NRF_ERROR_NO_MEM may occur if flow control is enabled and CTS signal
+ * is high for a long period and the buffer fills up.
+ */
+uint32_t app_uart_put(uint8_t byte);
+
+/**@brief Function for getting the current state of the UART.
+ *
+ * @details If flow control is disabled, the state is assumed to always be APP_UART_CONNECTED.
+ *
+ * When using flow control the state will be controlled by the CTS. If CTS is set active
+ * by the remote side, or the app_uart module is in the process of transmitting a byte,
+ * app_uart is in APP_UART_CONNECTED state. If CTS is set inactive by remote side app_uart
+ * will not get into APP_UART_DISCONNECTED state until the last byte in the TXD register
+ * is fully transmitted.
+ *
+ * Internal states in the state machine are mapped to the general connected/disconnected
+ * states in the following ways:
+ *
+ * - UART_ON = CONNECTED
+ * - UART_READY = CONNECTED
+ * - UART_WAIT = CONNECTED
+ * - UART_OFF = DISCONNECTED.
+ *
+ * @param[out] p_connection_state Current connection state of the UART.
+ *
+ * @retval NRF_SUCCESS The connection state was succesfully retrieved.
+ */
+uint32_t app_uart_get_connection_state(app_uart_connection_state_t * p_connection_state);
+
+/**@brief Function for flushing the RX and TX buffers (Only valid if FIFO is used).
+ * This function does nothing if FIFO is not used.
+ *
+ * @retval NRF_SUCCESS Flushing completed (Current implementation will always succeed).
+ */
+uint32_t app_uart_flush(void);
+
+/**@brief Function for closing the UART module.
+ *
+ * @details This function will close any on-going UART transmissions and disable itself in the
+ * GPTIO module.
+ *
+ * @param[in] app_uart_uid User id for the UART module. The app_uart_uid must be identical to the
+ * UART id returned on initialization and which is currently in use.
+
+ * @retval NRF_SUCCESS If successfully closed.
+ * @retval NRF_ERROR_INVALID_PARAM If an invalid user id is provided or the user id differs from
+ * the current active user.
+ */
+uint32_t app_uart_close(uint16_t app_uart_id);
+
+
+#endif //APP_UART_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_BLE/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_util.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,232 @@
+/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup app_util Utility Functions and Definitions
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Various types and definitions available to all applications.
+ */
+
+#ifndef APP_UTIL_H__
+#define APP_UTIL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "compiler_abstraction.h"
+
+enum
+{
+ UNIT_0_625_MS = 625, /**< Number of microseconds in 0.625 milliseconds. */
+ UNIT_1_25_MS = 1250, /**< Number of microseconds in 1.25 milliseconds. */
+ UNIT_10_MS = 10000 /**< Number of microseconds in 10 milliseconds. */
+};
+
+/**@brief Macro for doing static (i.e. compile time) assertion.
+ *
+ * @note If the assertion fails when compiling using Keil, the compiler will report error message
+ * "error: #94: the size of an array must be greater than zero" (while gcc will list the
+ * symbol static_assert_failed, making the error message more readable).
+ * If the supplied expression can not be evaluated at compile time, Keil will report
+ * "error: #28: expression must have a constant value".
+ *
+ * @note The macro is intentionally implemented not using do while(0), allowing it to be used
+ * outside function blocks (e.g. close to global type- and variable declarations).
+ * If used in a code block, it must be used before any executable code in this block.
+ *
+ * @param[in] EXPR Constant expression to be verified.
+ */
+
+#if defined(__GNUC__)
+#define STATIC_ASSERT(EXPR) typedef char __attribute__((unused)) static_assert_failed[(EXPR) ? 1 : -1]
+#else
+#define STATIC_ASSERT(EXPR) typedef char static_assert_failed[(EXPR) ? 1 : -1]
+#endif
+
+
+/**@brief type for holding an encoded (i.e. little endian) 16 bit unsigned integer. */
+typedef uint8_t uint16_le_t[2];
+
+/**@brief type for holding an encoded (i.e. little endian) 32 bit unsigned integer. */
+typedef uint8_t uint32_le_t[4];
+
+/**@brief Byte array type. */
+typedef struct
+{
+ uint16_t size; /**< Number of array entries. */
+ uint8_t * p_data; /**< Pointer to array entries. */
+} uint8_array_t;
+
+/**@brief Perform rounded integer division (as opposed to truncating the result).
+ *
+ * @param[in] A Numerator.
+ * @param[in] B Denominator.
+ *
+ * @return Rounded (integer) result of dividing A by B.
+ */
+#define ROUNDED_DIV(A, B) (((A) + ((B) / 2)) / (B))
+
+/**@brief Check if the integer provided is a power of two.
+ *
+ * @param[in] A Number to be tested.
+ *
+ * @return true if value is power of two.
+ * @return false if value not power of two.
+ */
+#define IS_POWER_OF_TWO(A) ( ((A) != 0) && ((((A) - 1) & (A)) == 0) )
+
+/**@brief To convert ticks to millisecond
+ * @param[in] time Number of millseconds that needs to be converted.
+ * @param[in] resolution Units to be converted.
+ */
+#define MSEC_TO_UNITS(TIME, RESOLUTION) (((TIME) * 1000) / (RESOLUTION))
+
+
+/**@brief Perform integer division, making sure the result is rounded up.
+ *
+ * @details One typical use for this is to compute the number of objects with size B is needed to
+ * hold A number of bytes.
+ *
+ * @param[in] A Numerator.
+ * @param[in] B Denominator.
+ *
+ * @return Integer result of dividing A by B, rounded up.
+ */
+#define CEIL_DIV(A, B) \
+ /*lint -save -e573 */ \
+ ((((A) - 1) / (B)) + 1) \
+ /*lint -restore */
+
+/**@brief Function for encoding a uint16 value.
+ *
+ * @param[in] value Value to be encoded.
+ * @param[out] p_encoded_data Buffer where the encoded data is to be written.
+ *
+ * @return Number of bytes written.
+ */
+static __INLINE uint8_t uint16_encode(uint16_t value, uint8_t * p_encoded_data)
+{
+ p_encoded_data[0] = (uint8_t) ((value & 0x00FF) >> 0);
+ p_encoded_data[1] = (uint8_t) ((value & 0xFF00) >> 8);
+ return sizeof(uint16_t);
+}
+
+/**@brief Function for encoding a uint32 value.
+ *
+ * @param[in] value Value to be encoded.
+ * @param[out] p_encoded_data Buffer where the encoded data is to be written.
+ *
+ * @return Number of bytes written.
+ */
+static __INLINE uint8_t uint32_encode(uint32_t value, uint8_t * p_encoded_data)
+{
+ p_encoded_data[0] = (uint8_t) ((value & 0x000000FF) >> 0);
+ p_encoded_data[1] = (uint8_t) ((value & 0x0000FF00) >> 8);
+ p_encoded_data[2] = (uint8_t) ((value & 0x00FF0000) >> 16);
+ p_encoded_data[3] = (uint8_t) ((value & 0xFF000000) >> 24);
+ return sizeof(uint32_t);
+}
+
+/**@brief Function for decoding a uint16 value.
+ *
+ * @param[in] p_encoded_data Buffer where the encoded data is stored.
+ *
+ * @return Decoded value.
+ */
+static __INLINE uint16_t uint16_decode(const uint8_t * p_encoded_data)
+{
+ return ( (((uint16_t)((uint8_t *)p_encoded_data)[0])) |
+ (((uint16_t)((uint8_t *)p_encoded_data)[1]) << 8 ));
+}
+
+/**@brief Function for decoding a uint32 value.
+ *
+ * @param[in] p_encoded_data Buffer where the encoded data is stored.
+ *
+ * @return Decoded value.
+ */
+static __INLINE uint32_t uint32_decode(const uint8_t * p_encoded_data)
+{
+ return ( (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0) |
+ (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8) |
+ (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16) |
+ (((uint32_t)((uint8_t *)p_encoded_data)[3]) << 24 ));
+}
+
+/** @brief Function for converting the input voltage (in milli volts) into percentage of 3.0 Volts.
+ *
+ * @details The calculation is based on a linearized version of the battery's discharge
+ * curve. 3.0V returns 100% battery level. The limit for power failure is 2.1V and
+ * is considered to be the lower boundary.
+ *
+ * The discharge curve for CR2032 is non-linear. In this model it is split into
+ * 4 linear sections:
+ * - Section 1: 3.0V - 2.9V = 100% - 42% (58% drop on 100 mV)
+ * - Section 2: 2.9V - 2.74V = 42% - 18% (24% drop on 160 mV)
+ * - Section 3: 2.74V - 2.44V = 18% - 6% (12% drop on 300 mV)
+ * - Section 4: 2.44V - 2.1V = 6% - 0% (6% drop on 340 mV)
+ *
+ * These numbers are by no means accurate. Temperature and
+ * load in the actual application is not accounted for!
+ *
+ * @param[in] mvolts The voltage in mV
+ *
+ * @return Battery level in percent.
+*/
+static __INLINE uint8_t battery_level_in_percent(const uint16_t mvolts)
+{
+ uint8_t battery_level;
+
+ if (mvolts >= 3000)
+ {
+ battery_level = 100;
+ }
+ else if (mvolts > 2900)
+ {
+ battery_level = 100 - ((3000 - mvolts) * 58) / 100;
+ }
+ else if (mvolts > 2740)
+ {
+ battery_level = 42 - ((2900 - mvolts) * 24) / 160;
+ }
+ else if (mvolts > 2440)
+ {
+ battery_level = 18 - ((2740 - mvolts) * 12) / 300;
+ }
+ else if (mvolts > 2100)
+ {
+ battery_level = 6 - ((2440 - mvolts) * 6) / 340;
+ }
+ else
+ {
+ battery_level = 0;
+ }
+
+ return battery_level;
+}
+
+/**@brief Function for checking if a pointer value is aligned to a 4 byte boundary.
+ *
+ * @param[in] p Pointer value to be checked.
+ *
+ * @return TRUE if pointer is aligned to a 4 byte boundary, FALSE otherwise.
+ */
+static __INLINE bool is_word_aligned(void * p)
+{
+ return (((uintptr_t)p & 0x03) == 0);
+}
+
+#endif // APP_UTIL_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_BLE/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/crc16.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,52 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup crc_compute CRC compute
+ * @{
+ * @ingroup hci_transport
+ *
+ * @brief This module implements the CRC-16 calculation in the blocks.
+ */
+
+#ifndef CRC16_H__
+#define CRC16_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@brief Function for calculating CRC-16 in blocks.
+ *
+ * Feed each consecutive data block into this function, along with the current value of p_crc as
+ * returned by the previous call of this function. The first call of this function should pass NULL
+ * as the initial value of the crc in p_crc.
+ *
+ * @param[in] p_data The input data block for computation.
+ * @param[in] size The size of the input data block in bytes.
+ * @param[in] p_crc The previous calculated CRC-16 value or NULL if first call.
+ *
+ * @return The updated CRC-16 value, based on the input supplied.
+ */
+uint16_t crc16_compute(const uint8_t * p_data, uint32_t size, const uint16_t * p_crc);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif // CRC16_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_BLE/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hal_transport.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,227 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/**@file
+ *
+ * @defgroup hci_transport HCI Transport
+ * @{
+ * @ingroup app_common
+ *
+ * @brief HCI transport module implementation.
+ *
+ * This module implements certain specific features from the three-wire UART transport layer,
+ * defined by the Bluetooth specification version 4.0 [Vol 4] part D.
+ *
+ * \par Features supported
+ * - Transmission and reception of Vendor Specific HCI packet type application packets.
+ * - Transmission and reception of reliable packets: defined by chapter 6 of the specification.
+ *
+ * \par Features not supported
+ * - Link establishment procedure: defined by chapter 8 of the specification.
+ * - Low power: defined by chapter 9 of the specification.
+ *
+ * \par Implementation specific behaviour
+ * - As Link establishment procedure is not supported following static link configuration parameters
+ * are used:
+ * + TX window size is 1.
+ * + 16 bit CCITT-CRC must be used.
+ * + Out of frame software flow control not supported.
+ * + Parameters specific for resending reliable packets are compile time configurable (clarifed
+ * later in this document).
+ * + Acknowledgement packet transmissions are not timeout driven , meaning they are delivered for
+ * transmission within same context which the corresponding application packet was received.
+ *
+ * \par Implementation specific limitations
+ * Current implementation has the following limitations which will have impact to system wide
+ * behaviour:
+ * - Delayed acknowledgement scheduling not implemented:
+ * There exists a possibility that acknowledgement TX packet and application TX packet will collide
+ * in the TX pipeline having the end result that acknowledgement packet will be excluded from the TX
+ * pipeline which will trigger the retransmission algorithm within the peer protocol entity.
+ * - Delayed retransmission scheduling not implemented:
+ * There exists a possibility that retransmitted application TX packet and acknowledgement TX packet
+ * will collide in the TX pipeline having the end result that retransmitted application TX packet
+ * will be excluded from the TX pipeline.
+ * - Processing of the acknowledgement number from RX application packets:
+ * Acknowledgement number is not processed from the RX application packets having the end result
+ * that unnecessary application packet retransmissions can occur.
+ *
+ * The application TX packet processing flow is illustrated by the statemachine below.
+ *
+ * @image html hci_transport_tx_sm.png "TX - application packet statemachine"
+ *
+ * \par Component specific configuration options
+ *
+ * The following compile time configuration options are available, and used to configure the
+ * application TX packet retransmission interval, in order to suite various application specific
+ * implementations:
+ * - MAC_PACKET_SIZE_IN_BITS Maximum size of a single application packet in bits.
+ * - USED_BAUD_RATE Used uart baudrate.
+ *
+ * The following compile time configuration option is available to configure module specific
+ * behaviour:
+ * - MAX_RETRY_COUNT Max retransmission retry count for applicaton packets.
+ */
+
+#ifndef HCI_TRANSPORT_H__
+#define HCI_TRANSPORT_H__
+
+#include <stdint.h>
+#include "nrf_error.h"
+
+#define HCI_TRANSPORT_PKT_HEADER_SIZE (2) /**< Size of transport packet header */
+
+/**@brief Generic event callback function events. */
+typedef enum
+{
+ HCI_TRANSPORT_RX_RDY, /**< An event indicating that RX packet is ready for read. */
+ HCI_TRANSPORT_EVT_TYPE_MAX /**< Enumeration upper bound. */
+} hci_transport_evt_type_t;
+
+/**@brief Struct containing events from the Transport layer.
+ */
+typedef struct
+{
+ hci_transport_evt_type_t evt_type; /**< Type of event. */
+} hci_transport_evt_t;
+
+/**@brief Transport layer generic event callback function type.
+ *
+ * @param[in] event Transport layer event.
+ */
+typedef void (*hci_transport_event_handler_t)(hci_transport_evt_t event);
+
+/**@brief TX done event callback function result codes. */
+typedef enum
+{
+ HCI_TRANSPORT_TX_DONE_SUCCESS, /**< Transmission success, peer transport entity has acknowledged the transmission. */
+ HCI_TRANSPORT_TX_DONE_FAILURE /**< Transmission failure. */
+} hci_transport_tx_done_result_t;
+
+/**@brief Transport layer TX done event callback function type.
+ *
+ * @param[in] result TX done event result code.
+ */
+typedef void (*hci_transport_tx_done_handler_t)(hci_transport_tx_done_result_t result);
+
+/**@brief Function for registering a generic event handler.
+ *
+ * @note Multiple registration requests will overwrite any possible existing registration.
+ *
+ * @param[in] event_handler The function to be called by the transport layer upon an event.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_evt_handler_reg(hci_transport_event_handler_t event_handler);
+
+/**@brief Function for registering a handler for TX done event.
+ *
+ * @note Multiple registration requests will overwrite any possible existing registration.
+ *
+ * @param[in] event_handler The function to be called by the transport layer upon TX done
+ * event.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_tx_done_register(hci_transport_tx_done_handler_t event_handler);
+
+/**@brief Function for opening the transport channel and initializing the transport layer.
+ *
+ * @warning Must not be called for a channel which has been allready opened.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_INTERNAL Operation failure. Internal error ocurred.
+ */
+uint32_t hci_transport_open(void);
+
+/**@brief Function for closing the transport channel.
+ *
+ * @note Can be called multiple times and also for not opened channel.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_transport_close(void);
+
+/**@brief Function for allocating tx packet memory.
+ *
+ * @param[out] pp_memory Pointer to the packet data.
+ *
+ * @retval NRF_SUCCESS Operation success. Memory was allocated.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No memory available.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_tx_alloc(uint8_t ** pp_memory);
+
+/**@brief Function for freeing tx packet memory.
+ *
+ * @note Memory management works in FIFO principle meaning that free order must match the alloc
+ * order.
+ *
+ * @retval NRF_SUCCESS Operation success. Memory was freed.
+ */
+uint32_t hci_transport_tx_free(void);
+
+/**@brief Function for writing a packet.
+ *
+ * @note Completion of this method does not guarantee that actual peripheral transmission would
+ * have completed.
+ *
+ * @note In case of 0 byte packet length write request, message will consist of only transport
+ * module specific headers.
+ *
+ * @note The buffer provided to this function must be allocated through @ref hci_transport_tx_alloc
+ * function.
+ *
+ * @retval NRF_SUCCESS Operation success. Packet was added to the transmission queue
+ * and an event will be send upon transmission completion.
+ * @retval NRF_ERROR_NO_MEM Operation failure. Transmission queue is full and packet was not
+ * added to the transmission queue. User should wait for
+ * a appropriate event prior issuing this operation again.
+ * @retval NRF_ERROR_DATA_SIZE Operation failure. Packet size exceeds limit.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ * @retval NRF_ERROR_INVALID_STATE Operation failure. Channel is not open.
+ * @retval NRF_ERROR_INVALID_ADDR Operation failure. Buffer provided is not allocated through
+ * hci_transport_tx_alloc function.
+ */
+uint32_t hci_transport_pkt_write(const uint8_t * p_buffer, uint16_t length);
+
+/**@brief Function for extracting received packet.
+ *
+ * @note Extracted memory can't be reused by the underlying transport layer untill freed by call to
+ * hci_transport_rx_pkt_consume().
+ *
+ * @param[out] pp_buffer Pointer to the packet data.
+ * @param[out] p_length Length of packet data in bytes.
+ *
+ * @retval NRF_SUCCESS Operation success. Packet was extracted.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to extract.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_rx_pkt_extract(uint8_t ** pp_buffer, uint16_t * p_length);
+
+/**@brief Function for consuming extracted packet described by p_buffer.
+ *
+ * RX memory pointed to by p_buffer is freed and can be reused by the underlying transport layer.
+ *
+ * @param[in] p_buffer Pointer to the buffer that has been consumed.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to consume.
+ * @retval NRF_ERROR_INVALID_ADDR Operation failure. Not a valid pointer.
+ */
+uint32_t hci_transport_rx_pkt_consume(uint8_t * p_buffer);
+
+#endif // HCI_TRANSPORT_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_BLE/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_mem_pool.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,132 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup memory_pool Memory pool
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Memory pool implementation
+ *
+ * Memory pool implementation, based on circular buffer data structure, which supports asynchronous
+ * processing of RX data. The current default implementation supports 1 TX buffer and 4 RX buffers.
+ * The memory managed by the pool is allocated from static storage instead of heap. The internal
+ * design of the circular buffer implementing the RX memory layout is illustrated in the picture
+ * below.
+ *
+ * @image html memory_pool.png "Circular buffer design"
+ *
+ * The expected call order for the RX APIs is as follows:
+ * - hci_mem_pool_rx_produce
+ * - hci_mem_pool_rx_data_size_set
+ * - hci_mem_pool_rx_extract
+ * - hci_mem_pool_rx_consume
+ *
+ * @warning If the above mentioned expected call order is violated the end result can be undefined.
+ *
+ * \par Component specific configuration options
+ *
+ * The following compile time configuration options are available to suit various implementations:
+ * - TX_BUF_SIZE TX buffer size in bytes.
+ * - RX_BUF_SIZE RX buffer size in bytes.
+ * - RX_BUF_QUEUE_SIZE RX buffer element size.
+ */
+
+#ifndef HCI_MEM_POOL_H__
+#define HCI_MEM_POOL_H__
+
+#include <stdint.h>
+#include "nrf_error.h"
+
+/**@brief Function for opening the module.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_mem_pool_open(void);
+
+/**@brief Function for closing the module.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_mem_pool_close(void);
+
+/**@brief Function for allocating requested amount of TX memory.
+ *
+ * @param[out] pp_buffer Pointer to the allocated memory.
+ *
+ * @retval NRF_SUCCESS Operation success. Memory was allocated.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No memory available for allocation.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_mem_pool_tx_alloc(void ** pp_buffer);
+
+/**@brief Function for freeing previously allocated TX memory.
+ *
+ * @note Memory management follows the FIFO principle meaning that free() order must match the
+ * alloc(...) order, which is the reason for omitting exact memory block identifier as an
+ * input parameter.
+ *
+ * @retval NRF_SUCCESS Operation success. Memory was freed.
+ */
+uint32_t hci_mem_pool_tx_free(void);
+
+/**@brief Function for producing a free RX memory block for usage.
+ *
+ * @note Upon produce request amount being 0, NRF_SUCCESS is returned.
+ *
+ * @param[in] length Amount, in bytes, of free memory to be produced.
+ * @param[out] pp_buffer Pointer to the allocated memory.
+ *
+ * @retval NRF_SUCCESS Operation success. Free RX memory block produced.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No suitable memory available for allocation.
+ * @retval NRF_ERROR_DATA_SIZE Operation failure. Request size exceeds limit.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_mem_pool_rx_produce(uint32_t length, void ** pp_buffer);
+
+/**@brief Function for setting the length of the last produced RX memory block.
+ *
+ * @warning If call to this API is omitted the end result is that the following call to
+ * mem_pool_rx_extract will return incorrect data in the p_length output parameter.
+ *
+ * @param[in] length Amount, in bytes, of actual memory used.
+ *
+ * @retval NRF_SUCCESS Operation success. Length was set.
+ */
+uint32_t hci_mem_pool_rx_data_size_set(uint32_t length);
+
+/**@brief Function for extracting a packet, which has been filled with read data, for further
+ * processing.
+ *
+ * @param[out] pp_buffer Pointer to the packet data.
+ * @param[out] p_length Length of packet data in bytes.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to extract.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_mem_pool_rx_extract(uint8_t ** pp_buffer, uint32_t * p_length);
+
+/**@brief Function for freeing previously extracted packet, which has been filled with read data.
+ *
+ * @param[in] p_buffer Pointer to consumed buffer.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to free.
+ * @retval NRF_ERROR_INVALID_ADDR Operation failure. Not a valid pointer.
+ */
+uint32_t hci_mem_pool_rx_consume(uint8_t * p_buffer);
+
+#endif // HCI_MEM_POOL_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_BLE/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_mem_pool_internal.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,32 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup memory_pool_internal Memory Pool Internal
+ * @{
+ * @ingroup memory_pool
+ *
+ * @brief Memory pool internal definitions
+ */
+
+#ifndef MEM_POOL_INTERNAL_H__
+#define MEM_POOL_INTERNAL_H__
+
+#define TX_BUF_SIZE 600u /**< TX buffer size in bytes. */
+#define RX_BUF_SIZE TX_BUF_SIZE /**< RX buffer size in bytes. */
+
+#define RX_BUF_QUEUE_SIZE 4u /**< RX buffer element size. */
+
+#endif // MEM_POOL_INTERNAL_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_BLE/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_slip.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,129 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup hci_slip SLIP module
+ * @{
+ * @ingroup app_common
+ *
+ * @brief SLIP layer for supporting packet framing in HCI transport.
+ *
+ * @details This module implements SLIP packet framing as described in the Bluetooth Core
+ * Specification 4.0, Volume 4, Part D, Chapter 3 SLIP Layer.
+ *
+ * SLIP framing ensures that all packets sent on the UART are framed as:
+ * <0xC0> SLIP packet 1 <0xC0> <0xC0> SLIP packet 2 <0xC0>.
+ *
+ * The SLIP layer uses events to notify the upper layer when data transmission is complete
+ * and when a SLIP packet is received.
+ */
+
+#ifndef HCI_SLIP_H__
+#define HCI_SLIP_H__
+
+#include <stdint.h>
+
+/**@brief Event types from the SLIP Layer. */
+typedef enum
+{
+ HCI_SLIP_RX_RDY, /**< An event indicating that an RX packet is ready to be read. */
+ HCI_SLIP_TX_DONE, /**< An event indicating write completion of the TX packet provided in the function call \ref hci_slip_write . */
+ HCI_SLIP_RX_OVERFLOW, /**< An event indicating that RX data has been discarded due to lack of free RX memory. */
+ HCI_SLIP_ERROR, /**< An event indicating that an unrecoverable error has occurred. */
+ HCI_SLIP_EVT_TYPE_MAX /**< Enumeration upper bound. */
+} hci_slip_evt_type_t;
+
+/**@brief Structure containing an event from the SLIP layer.
+ */
+typedef struct
+{
+ hci_slip_evt_type_t evt_type; /**< Type of event. */
+ const uint8_t * packet; /**< This field contains a pointer to the packet for which the event relates, i.e. SLIP_TX_DONE: the packet transmitted, SLIP_RX_RDY: the packet received, SLIP_RX_OVERFLOW: The packet which overflow/or NULL if no receive buffer is available. */
+ uint32_t packet_length; /**< Packet length, i.e. SLIP_TX_DONE: Bytes transmitted, SLIP_RX_RDY: Bytes received, SLIP_RX_OVERFLOW: index at which the packet overflowed. */
+} hci_slip_evt_t;
+
+/**@brief Function for the SLIP layer event callback.
+ */
+typedef void (*hci_slip_event_handler_t)(hci_slip_evt_t event);
+
+/**@brief Function for registering the event handler provided as parameter and this event handler
+ * will be used by SLIP layer to send events described in \ref hci_slip_evt_type_t.
+ *
+ * @note Multiple registration requests will overwrite any existing registration.
+ *
+ * @param[in] event_handler This function is called by the SLIP layer upon an event.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_slip_evt_handler_register(hci_slip_event_handler_t event_handler);
+
+/**@brief Function for opening the SLIP layer. This function must be called before
+ * \ref hci_slip_write and before any data can be received.
+ *
+ * @note Can be called multiple times.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ *
+ * The SLIP layer module will propagate errors from underlying sub-modules.
+ * This implementation is using UART module as a physical transmission layer, and hci_slip_open
+ * executes \ref app_uart_init . For an extended error list, please refer to \ref app_uart_init .
+ */
+uint32_t hci_slip_open(void);
+
+/**@brief Function for closing the SLIP layer. After this function is called no data can be
+ * transmitted or received in this layer.
+ *
+ * @note This function can be called multiple times and also for an unopened channel.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_slip_close(void);
+
+/**@brief Function for writing a packet with SLIP encoding. Packet transmission is confirmed when
+ * the HCI_SLIP_TX_DONE event is received by the function caller.
+ *
+ * @param[in] p_buffer Pointer to the packet to transmit.
+ * @param[in] length Packet length, in bytes.
+ *
+ * @retval NRF_SUCCESS Operation success. Packet was encoded and added to the
+ * transmission queue and an event will be sent upon transmission
+ * completion.
+ * @retval NRF_ERROR_NO_MEM Operation failure. Transmission queue is full and packet was not
+ * added to the transmission queue. Application shall wait for
+ * the \ref HCI_SLIP_TX_DONE event. After HCI_SLIP_TX_DONE this
+ * function can be executed for transmission of next packet.
+ * @retval NRF_ERROR_INVALID_ADDR If a NULL pointer is provided.
+ * @retval NRF_ERROR_INVALID_STATE Operation failure. Module is not open.
+ */
+uint32_t hci_slip_write(const uint8_t * p_buffer, uint32_t length);
+
+/**@brief Function for registering a receive buffer. The receive buffer will be used for storage of
+ * received and SLIP decoded data.
+ * No data can be received by the SLIP layer until a receive buffer has been registered.
+ *
+ * @note The lifetime of the buffer must be valid during complete reception of data. A static
+ * buffer is recommended.
+ *
+ * @warning Multiple registration requests will overwrite any existing registration.
+ *
+ * @param[in] p_buffer Pointer to receive buffer. The received and SLIP decoded packet
+ * will be placed in this buffer.
+ * @param[in] length Buffer length, in bytes.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_slip_rx_buffer_register(uint8_t * p_buffer, uint32_t length);
+
+#endif // HCI_SLIP_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_BLE/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_transport.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,220 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/**@file
+ *
+ * @defgroup hci_transport HCI Transport
+ * @{
+ * @ingroup app_common
+ *
+ * @brief HCI transport module implementation.
+ *
+ * This module implements certain specific features from the three-wire UART transport layer,
+ * defined by the Bluetooth specification version 4.0 [Vol 4] part D.
+ *
+ * \par Features supported
+ * - Transmission and reception of Vendor Specific HCI packet type application packets.
+ * - Transmission and reception of reliable packets: defined by chapter 6 of the specification.
+ *
+ * \par Features not supported
+ * - Link establishment procedure: defined by chapter 8 of the specification.
+ * - Low power: defined by chapter 9 of the specification.
+ *
+ * \par Implementation specific behaviour
+ * - As Link establishment procedure is not supported following static link configuration parameters
+ * are used:
+ * + TX window size is 1.
+ * + 16 bit CCITT-CRC must be used.
+ * + Out of frame software flow control not supported.
+ * + Parameters specific for resending reliable packets are compile time configurable (clarifed
+ * later in this document).
+ * + Acknowledgement packet transmissions are not timeout driven , meaning they are delivered for
+ * transmission within same context which the corresponding application packet was received.
+ *
+ * \par Implementation specific limitations
+ * Current implementation has the following limitations which will have impact to system wide
+ * behaviour:
+ * - Delayed acknowledgement scheduling not implemented:
+ * There exists a possibility that acknowledgement TX packet and application TX packet will collide
+ * in the TX pipeline having the end result that acknowledgement packet will be excluded from the TX
+ * pipeline which will trigger the retransmission algorithm within the peer protocol entity.
+ * - Delayed retransmission scheduling not implemented:
+ * There exists a possibility that retransmitted application TX packet and acknowledgement TX packet
+ * will collide in the TX pipeline having the end result that retransmitted application TX packet
+ * will be excluded from the TX pipeline.
+ * - Processing of the acknowledgement number from RX application packets:
+ * Acknowledgement number is not processed from the RX application packets having the end result
+ * that unnecessary application packet retransmissions can occur.
+ *
+ * The application TX packet processing flow is illustrated by the statemachine below.
+ *
+ * @image html hci_transport_tx_sm.png "TX - application packet statemachine"
+ *
+ * \par Component specific configuration options
+ *
+ * The following compile time configuration options are available, and used to configure the
+ * application TX packet retransmission interval, in order to suite various application specific
+ * implementations:
+ * - MAC_PACKET_SIZE_IN_BITS Maximum size of a single application packet in bits.
+ * - USED_BAUD_RATE Used uart baudrate.
+ *
+ * The following compile time configuration option is available to configure module specific
+ * behaviour:
+ * - MAX_RETRY_COUNT Max retransmission retry count for applicaton packets.
+ */
+
+#ifndef HCI_TRANSPORT_H__
+#define HCI_TRANSPORT_H__
+
+#include <stdint.h>
+#include "nrf_error.h"
+
+/**@brief Generic event callback function events. */
+typedef enum
+{
+ HCI_TRANSPORT_RX_RDY, /**< An event indicating that RX packet is ready for read. */
+ HCI_TRANSPORT_EVT_TYPE_MAX /**< Enumeration upper bound. */
+} hci_transport_evt_type_t;
+
+/**@brief Struct containing events from the Transport layer.
+ */
+typedef struct
+{
+ hci_transport_evt_type_t evt_type; /**< Type of event. */
+} hci_transport_evt_t;
+
+/**@brief Transport layer generic event callback function type.
+ *
+ * @param[in] event Transport layer event.
+ */
+typedef void (*hci_transport_event_handler_t)(hci_transport_evt_t event);
+
+/**@brief TX done event callback function result codes. */
+typedef enum
+{
+ HCI_TRANSPORT_TX_DONE_SUCCESS, /**< Transmission success, peer transport entity has acknowledged the transmission. */
+ HCI_TRANSPORT_TX_DONE_FAILURE /**< Transmission failure. */
+} hci_transport_tx_done_result_t;
+
+/**@brief Transport layer TX done event callback function type.
+ *
+ * @param[in] result TX done event result code.
+ */
+typedef void (*hci_transport_tx_done_handler_t)(hci_transport_tx_done_result_t result);
+
+/**@brief Function for registering a generic event handler.
+ *
+ * @note Multiple registration requests will overwrite any possible existing registration.
+ *
+ * @param[in] event_handler The function to be called by the transport layer upon an event.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_evt_handler_reg(hci_transport_event_handler_t event_handler);
+
+/**@brief Function for registering a handler for TX done event.
+ *
+ * @note Multiple registration requests will overwrite any possible existing registration.
+ *
+ * @param[in] event_handler The function to be called by the transport layer upon TX done
+ * event.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_tx_done_register(hci_transport_tx_done_handler_t event_handler);
+
+/**@brief Function for opening the transport channel and initializing the transport layer.
+ *
+ * @warning Must not be called for a channel which has been allready opened.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_INTERNAL Operation failure. Internal error ocurred.
+ */
+uint32_t hci_transport_open(void);
+
+/**@brief Function for closing the transport channel.
+ *
+ * @note Can be called multiple times and also for not opened channel.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_transport_close(void);
+
+/**@brief Function for allocating tx packet memory.
+ *
+ * @param[out] pp_memory Pointer to the packet data.
+ *
+ * @retval NRF_SUCCESS Operation success. Memory was allocated.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No memory available.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_tx_alloc(uint8_t ** pp_memory);
+
+/**@brief Function for freeing tx packet memory.
+ *
+ * @note Memory management works in FIFO principle meaning that free order must match the alloc
+ * order.
+ *
+ * @retval NRF_SUCCESS Operation success. Memory was freed.
+ */
+uint32_t hci_transport_tx_free(void);
+
+/**@brief Function for writing a packet.
+ *
+ * @note Completion of this method does not guarantee that actual peripheral transmission would
+ * have completed.
+ *
+ * @note In case of 0 byte packet length write request, message will consist of only transport
+ * module specific headers.
+ *
+ * @retval NRF_SUCCESS Operation success. Packet was added to the transmission queue
+ * and an event will be send upon transmission completion.
+ * @retval NRF_ERROR_NO_MEM Operation failure. Transmission queue is full and packet was not
+ * added to the transmission queue. User should wait for
+ * a appropriate event prior issuing this operation again.
+ * @retval NRF_ERROR_DATA_SIZE Operation failure. Packet size exceeds limit.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ * @retval NRF_ERROR_INVALID_STATE Operation failure. Channel is not open.
+ */
+uint32_t hci_transport_pkt_write(const uint8_t * p_buffer, uint32_t length);
+
+/**@brief Function for extracting received packet.
+ *
+ * @note Extracted memory can't be reused by the underlying transport layer untill freed by call to
+ * hci_transport_rx_pkt_consume().
+ *
+ * @param[out] pp_buffer Pointer to the packet data.
+ * @param[out] p_length Length of packet data in bytes.
+ *
+ * @retval NRF_SUCCESS Operation success. Packet was extracted.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to extract.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_rx_pkt_extract(uint8_t ** pp_buffer, uint32_t * p_length);
+
+/**@brief Function for consuming extracted packet described by p_buffer.
+ *
+ * RX memory pointed to by p_buffer is freed and can be reused by the underlying transport layer.
+ *
+ * @param[in] p_buffer Pointer to the buffer that has been consumed.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to consume.
+ * @retval NRF_ERROR_INVALID_ADDR Operation failure. Not a valid pointer.
+ */
+uint32_t hci_transport_rx_pkt_consume(uint8_t * p_buffer);
+
+#endif // HCI_TRANSPORT_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_BLE/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/pstorage.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,381 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/**@file
+ *
+ * @defgroup persistent_storage Persistent Storage Interface
+ * @{
+ * @ingroup app_common
+ * @brief Abstracted flash interface.
+ *
+ * @details In order to ensure that the SDK and application be moved to alternate persistent storage
+ * options other than the default provided with NRF solution, an abstracted interface is provided
+ * by the module to ensure SDK modules and application can be ported to alternate option with ease.
+ */
+
+#ifndef PSTORAGE_H__
+#define PSTORAGE_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* #ifdef __cplusplus */
+
+#include "pstorage_platform.h"
+
+
+/**@defgroup ps_opcode Persistent Storage Access Operation Codes
+ * @{
+ * @brief Persistent Storage Access Operation Codes. These are used to report any error during
+ * a persistent storage access operation or any general error that may occur in the
+ * interface.
+ *
+ * @details Persistent Storage Access Operation Codes used in error notification callback
+ * registered with the interface to report any error during an persistent storage access
+ * operation or any general error that may occur in the interface.
+ */
+#define PSTORAGE_ERROR_OP_CODE 0x01 /**< General Error Code */
+#define PSTORAGE_STORE_OP_CODE 0x02 /**< Error when Store Operation was requested */
+#define PSTORAGE_LOAD_OP_CODE 0x03 /**< Error when Load Operation was requested */
+#define PSTORAGE_CLEAR_OP_CODE 0x04 /**< Error when Clear Operation was requested */
+#define PSTORAGE_UPDATE_OP_CODE 0x05 /**< Update an already touched storage block */
+
+/**@} */
+
+/**@defgroup pstorage_data_types Persistent Memory Interface Data Types
+ * @{
+ * @brief Data Types needed for interfacing with persistent memory.
+ *
+ * @details Data Types needed for interfacing with persistent memory.
+ */
+
+/**@brief Persistent Storage Error Reporting Callback
+ *
+ * @details Persistent Storage Error Reporting Callback that is used by the interface to report
+ * success or failure of a flash operation. Therefore, for any operations, application
+ * can know when the procedure was complete. For store operation, since no data copy
+ * is made, receiving a success or failure notification, indicated by the reason
+ * parameter of callback is an indication that the resident memory could now be reused
+ * or freed, as the case may be.
+ *
+ * @param[in] handle Identifies module and block for which callback is received.
+ * @param[in] op_code Identifies the operation for which the event is notified.
+ * @param[in] result Identifies the result of flash access operation.
+ * NRF_SUCCESS implies, operation succeeded.
+ * @param[in] p_data Identifies the application data pointer. In case of store operation, this
+ * points to the resident source of application memory that application can now
+ * free or reuse. In case of clear, this is NULL as no application pointer is
+ * needed for this operation.
+ * @param[in] data_len Length data application had provided for the operation.
+ *
+ */
+typedef void (*pstorage_ntf_cb_t)(pstorage_handle_t * p_handle,
+ uint8_t op_code,
+ uint32_t result,
+ uint8_t * p_data,
+ uint32_t data_len);
+
+
+typedef struct
+{
+ pstorage_ntf_cb_t cb; /**< Callback registered with the module to be notified of any error occurring in persistent memory management */
+ pstorage_size_t block_size; /**< Desired block size for persistent memory storage, for example, if a module has a table with 10 entries, each entry is size 64 bytes,
+ * it can request 10 blocks with block size 64 bytes. On the other hand, the module can also request one block of size 640 based on
+ * how it would like to access or alter memory in persistent memory.
+ * First option is preferred when single entries that need to be updated often when having no impact on the other entries.
+ * While second option is preferred when entries of table are not changed on individually but have common point of loading and storing
+ * data. */
+ pstorage_size_t block_count; /** Number of blocks requested by the module, minimum values is 1. */
+} pstorage_module_param_t;
+
+/**@} */
+
+/**@defgroup pstorage_routines Persistent Storage Access Routines
+ * @{
+ * @brief Functions/Interface SDK modules use to persistently store data.
+ *
+ * @details Interface for Application & SDK module to load/store information persistently.
+ * Note: that while implementation of each of the persistent storage access function
+ * depends on the system and can specific to system/solution, the signature of the
+ * interface routines should not be altered.
+ */
+
+/**@brief Module Initialization Routine.
+ *
+ * @details Initializes module. To be called once before any other APIs of the module are used.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ */
+uint32_t pstorage_init(void);
+
+
+/**@brief Register with persistent storage interface.
+ *
+ * @param[in] p_module_param Module registration param.
+ * @param[out] p_block_id Block identifier to identify persistent memory blocks in case
+ * registration succeeds. Application is expected to use the block ids
+ * for subsequent operations on requested persistent memory. Maximum
+ * registrations permitted is determined by configuration parameter
+ * PSTORAGE_MAX_APPLICATIONS.
+ * In case more than one memory blocks are requested, the identifier provided here is
+ * the base identifier for the first block and to identify subsequent block,
+ * application shall use \@ref pstorage_block_identifier_get with this base identifier
+ * and block number. Therefore if 10 blocks of size 64 are requested and application
+ * wishes to store memory in 6th block, it shall use
+ * \@ref pstorage_block_identifier_get with based id and provide a block number of 5.
+ * This way application is only expected to remember the base block identifier.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_NO_MEM in case no more registrations can be supported.
+ */
+uint32_t pstorage_register(pstorage_module_param_t * p_module_param,
+ pstorage_handle_t * p_block_id);
+
+
+/**
+ * @brief Function to get block id with reference to base block identifier provided at time of
+ * registration.
+ *
+ * @details Function to get block id with reference to base block identifier provided at time of
+ * registration.
+ * In case more than one memory blocks were requested when registering, the identifier
+ * provided here is the base identifier for the first block and to identify subsequent
+ * block, application shall use this routine to get block identifier providing input as
+ * base identifier and block number. Therefore if 10 blocks of size 64 are requested and
+ * application wishes to store memory in 6th block, it shall use
+ * \@ref pstorage_block_identifier_get with based id and provide a block number of 5.
+ * This way application is only expected to remember the base block identifier.
+ *
+ * @param[in] p_base_id Base block id received at the time of registration.
+ * @param[in] block_num Block Number, with first block numbered zero.
+ * @param[out] p_block_id Block identifier for the block number requested in case the API succeeds.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ */
+uint32_t pstorage_block_identifier_get(pstorage_handle_t * p_base_id,
+ pstorage_size_t block_num,
+ pstorage_handle_t * p_block_id);
+
+
+/**@brief Routine to persistently store data of length 'size' contained in 'p_src' address
+ * in storage module at 'p_dest' address; Equivalent to Storage Write.
+ *
+ * @param[in] p_dest Destination address where data is to be stored persistently.
+ * @param[in] p_src Source address containing data to be stored. API assumes this to be resident
+ * memory and no intermediate copy of data is made by the API.
+ * @param[in] size Size of data to be stored expressed in bytes. Should be word aligned.
+ * @param[in] offset Offset in bytes to be applied when writing to the block.
+ * For example, if within a block of 100 bytes, application wishes to
+ * write 20 bytes at offset of 12, then this field should be set to 12.
+ * Should be word aligned.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_src' is not aligned.
+ * @retval NRF_ERROR_NO_MEM in case request cannot be processed.
+ *
+ * @warning No copy of the data is made, and hence memory provided for data source to be written
+ * to flash cannot be freed or reused by the application until this procedure
+ * is complete. End of this procedure is notified to the application using the
+ * notification callback registered by the application.
+ */
+uint32_t pstorage_store(pstorage_handle_t * p_dest,
+ uint8_t * p_src,
+ pstorage_size_t size,
+ pstorage_size_t offset);
+
+/**@brief Routine to update persistently stored data of length 'size' contained in 'p_src' address
+ * in storage module at 'p_dest' address.
+ *
+ * @param[in] p_dest Destination address where data is to be updated.
+ * @param[in] p_src Source address containing data to be stored. API assumes this to be resident
+ * memory and no intermediate copy of data is made by the API.
+ * @param[in] size Size of data to be stored expressed in bytes. Should be word aligned.
+ * @param[in] offset Offset in bytes to be applied when writing to the block.
+ * For example, if within a block of 100 bytes, application wishes to
+ * write 20 bytes at offset of 12, then this field should be set to 12.
+ * Should be word aligned.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_src' is not aligned.
+ * @retval NRF_ERROR_NO_MEM in case request cannot be processed.
+ *
+ * @warning No copy of the data is made, and hence memory provided for data source to be written
+ * to flash cannot be freed or reused by the application until this procedure
+ * is complete. End of this procedure is notified to the application using the
+ * notification callback registered by the application.
+ */
+uint32_t pstorage_update(pstorage_handle_t * p_dest,
+ uint8_t * p_src,
+ pstorage_size_t size,
+ pstorage_size_t offset);
+
+/**@brief Routine to load persistently stored data of length 'size' from 'p_src' address
+ * to 'p_dest' address; Equivalent to Storage Read.
+ *
+ * @param[in] p_dest Destination address where persistently stored data is to be loaded.
+ * @param[in] p_src Source from where data is to be loaded from persistent memory.
+ * @param[in] size Size of data to be loaded from persistent memory expressed in bytes.
+ * Should be word aligned.
+ * @param[in] offset Offset in bytes to be applied when loading from the block.
+ * For example, if within a block of 100 bytes, application wishes to
+ * load 20 bytes from offset of 12, then this field should be set to 12.
+ * Should be word aligned.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_dst' is not aligned.
+ * @retval NRF_ERROR_NO_MEM in case request cannot be processed.
+ */
+uint32_t pstorage_load(uint8_t * p_dest,
+ pstorage_handle_t * p_src,
+ pstorage_size_t size,
+ pstorage_size_t offset);
+
+/**@brief Routine to clear data in persistent memory.
+ *
+ * @param[in] p_base_id Base block identifier in persistent memory that needs to cleared;
+ * Equivalent to an Erase Operation.
+ *
+ * @param[in] size Size of data to be cleared from persistent memory expressed in bytes.
+ * This parameter is to provision for clearing of certain blocks
+ * of memory, or all memory blocks in a registered module. If the total size
+ * of the application module is used (blocks * block size) in combination with
+ * the identifier for the first block in the module, all blocks in the
+ * module will be erased.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_dst' is not aligned.
+ * @retval NRF_ERROR_NO_MEM in case request cannot be processed.
+ *
+ * @note Clear operations may take time. This API however, does not block until the clear
+ * procedure is complete. Application is notified of procedure completion using
+ * notification callback registered by the application. 'result' parameter of the
+ * callback suggests if the procedure was successful or not.
+ */
+uint32_t pstorage_clear(pstorage_handle_t * p_base_id, pstorage_size_t size);
+
+/**
+ * @brief API to get status of number of pending operations with the module.
+ *
+ * @param[out] p_count Number of storage operations pending with the module, if 0,
+ * there are no outstanding requests.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ */
+uint32_t pstorage_access_status_get(uint32_t * p_count);
+
+#ifdef PSTORAGE_RAW_MODE_ENABLE
+
+/**@brief Function for registering with persistent storage interface.
+ *
+ * @param[in] p_module_param Module registration param.
+ * @param[out] p_block_id Block identifier to identify persistent memory blocks in case
+ * registration succeeds. Application is expected to use the block ids
+ * for subsequent operations on requested persistent memory.
+ * In case more than one memory blocks are requested, the identifier provided here is
+ * the base identifier for the first block and to identify subsequent block,
+ * application shall use \@ref pstorage_block_identifier_get with this base identifier
+ * and block number. Therefore if 10 blocks of size 64 are requested and application
+ * wishes to store memory in 6th block, it shall use
+ * \@ref pstorage_block_identifier_get with based id and provide a block number of 5.
+ * This way application is only expected to remember the base block identifier.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_NO_MEM in case no more registrations can be supported.
+ */
+uint32_t pstorage_raw_register(pstorage_module_param_t * p_module_param,
+ pstorage_handle_t * p_block_id);
+
+/**@brief Raw mode function for persistently storing data of length 'size' contained in 'p_src'
+ * address in storage module at 'p_dest' address; Equivalent to Storage Write.
+ *
+ * @param[in] p_dest Destination address where data is to be stored persistently.
+ * @param[in] p_src Source address containing data to be stored. API assumes this to be resident
+ * memory and no intermediate copy of data is made by the API.
+ * @param[in] size Size of data to be stored expressed in bytes. Should be word aligned.
+ * @param[in] offset Offset in bytes to be applied when writing to the block.
+ * For example, if within a block of 100 bytes, application wishes to
+ * write 20 bytes at offset of 12, then this field should be set to 12.
+ * Should be word aligned.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_src' is not aligned.
+ * @retval NRF_ERROR_NO_MEM in case request cannot be processed.
+ *
+ * @warning No copy of the data is made, and hence memory provided for data source to be written
+ * to flash cannot be freed or reused by the application until this procedure
+ * is complete. End of this procedure is notified to the application using the
+ * notification callback registered by the application.
+ */
+uint32_t pstorage_raw_store(pstorage_handle_t * p_dest,
+ uint8_t * p_src,
+ pstorage_size_t size,
+ pstorage_size_t offset);
+
+/**@brief Function for clearing data in persistent memory in raw mode.
+ *
+ * @param[in] p_dest Base block identifier in persistent memory that needs to cleared;
+ * Equivalent to an Erase Operation.
+ * @param[in] size Size of data to be cleared from persistent memory expressed in bytes.
+ * This is currently unused. And a clear would mean clearing all blocks,
+ * however, this parameter is to provision for clearing of certain blocks
+ * of memory only and not all if need be.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_NO_MEM in case request cannot be processed.
+ *
+ * @note Clear operations may take time. This API however, does not block until the clear
+ * procedure is complete. Application is notified of procedure completion using
+ * notification callback registered by the application. 'result' parameter of the
+ * callback suggests if the procedure was successful or not.
+ */
+uint32_t pstorage_raw_clear(pstorage_handle_t * p_dest, pstorage_size_t size);
+
+#endif // PSTORAGE_RAW_MODE_ENABLE
+
+#ifdef __cplusplus
+}
+#endif /* #ifdef __cplusplus */
+
+
+/**@} */
+/**@} */
+
+#endif // PSTORAGE_H__
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_BLE/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/nrf_delay.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,74 @@
+#ifndef _NRF_DELAY_H
+#define _NRF_DELAY_H
+
+// #include "nrf.h"
+
+/*lint --e{438, 522} "Variable not used" "Function lacks side-effects" */
+#if defined ( __CC_ARM )
+static __ASM void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
+{
+loop
+ SUBS R0, R0, #1
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ BNE loop
+ BX LR
+}
+#elif defined ( __ICCARM__ )
+static void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
+{
+__ASM (
+"loop:\n\t"
+ " SUBS R0, R0, #1\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " BNE loop\n\t");
+}
+#elif defined ( __GNUC__ )
+static void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
+{
+ do
+ {
+ __ASM volatile (
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ );
+ } while (--number_of_us);
+}
+#endif
+
+void nrf_delay_ms(uint32_t volatile number_of_ms);
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_BLE/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/sd_common/app_util_platform.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,110 @@
+/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/**@file
+ *
+ * @defgroup app_util_platform Utility Functions and Definitions (Platform)
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Various types and definitions available to all applications when using SoftDevice.
+ */
+
+#ifndef APP_UTIL_PLATFORM_H__
+#define APP_UTIL_PLATFORM_H__
+
+#include <stdint.h>
+#include "compiler_abstraction.h"
+#include "nrf51.h"
+#include "app_error.h"
+
+/**@brief The interrupt priorities available to the application while the SoftDevice is active. */
+typedef enum
+{
+ APP_IRQ_PRIORITY_HIGH = 1,
+ APP_IRQ_PRIORITY_LOW = 3
+} app_irq_priority_t;
+
+#define NRF_APP_PRIORITY_THREAD 4 /**< "Interrupt level" when running in Thread Mode. */
+
+/**@cond NO_DOXYGEN */
+#define EXTERNAL_INT_VECTOR_OFFSET 16
+/**@endcond */
+
+#define PACKED(TYPE) __packed TYPE
+
+/**@brief Macro for entering a critical region.
+ *
+ * @note Due to implementation details, there must exist one and only one call to
+ * CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located
+ * in the same scope.
+ */
+#define CRITICAL_REGION_ENTER() \
+ { \
+ uint8_t IS_NESTED_CRITICAL_REGION = 0; \
+ uint32_t CURRENT_INT_PRI = current_int_priority_get(); \
+ if (CURRENT_INT_PRI != APP_IRQ_PRIORITY_HIGH) \
+ { \
+ uint32_t ERR_CODE = sd_nvic_critical_region_enter(&IS_NESTED_CRITICAL_REGION); \
+ if (ERR_CODE == NRF_ERROR_SOFTDEVICE_NOT_ENABLED) \
+ { \
+ __disable_irq(); \
+ } \
+ else \
+ { \
+ APP_ERROR_CHECK(ERR_CODE); \
+ } \
+ }
+
+/**@brief Macro for leaving a critical region.
+ *
+ * @note Due to implementation details, there must exist one and only one call to
+ * CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located
+ * in the same scope.
+ */
+#define CRITICAL_REGION_EXIT() \
+ if (CURRENT_INT_PRI != APP_IRQ_PRIORITY_HIGH) \
+ { \
+ uint32_t ERR_CODE; \
+ __enable_irq(); \
+ ERR_CODE = sd_nvic_critical_region_exit(IS_NESTED_CRITICAL_REGION); \
+ if (ERR_CODE != NRF_ERROR_SOFTDEVICE_NOT_ENABLED) \
+ { \
+ APP_ERROR_CHECK(ERR_CODE); \
+ } \
+ } \
+ }
+
+/**@brief Function for finding the current interrupt level.
+ *
+ * @return Current interrupt level.
+ * @retval APP_IRQ_PRIORITY_HIGH We are running in Application High interrupt level.
+ * @retval APP_IRQ_PRIORITY_LOW We are running in Application Low interrupt level.
+ * @retval APP_IRQ_PRIORITY_THREAD We are running in Thread Mode.
+ */
+static __INLINE uint8_t current_int_priority_get(void)
+{
+ uint32_t isr_vector_num = (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk);
+ if (isr_vector_num > 0)
+ {
+ int32_t irq_type = ((int32_t)isr_vector_num - EXTERNAL_INT_VECTOR_OFFSET);
+ return (NVIC_GetPriority((IRQn_Type)irq_type) & 0xFF);
+ }
+ else
+ {
+ return NRF_APP_PRIORITY_THREAD;
+ }
+}
+
+#endif // APP_UTIL_PLATFORM_H__
+
+/** @} */
--- a/TARGET_ARCH_BLE/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_0_0/s110_nrf51822_7.0.0_API/include/nrf_svc.h Fri Aug 15 15:28:31 2014 +0100
+++ b/TARGET_ARCH_BLE/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_0_0/s110_nrf51822_7.0.0_API/include/nrf_svc.h Fri Sep 12 16:41:52 2014 +0100
@@ -16,7 +16,7 @@
{ \
__asm( \
"svc %0\n" \
- "bx r14" : : "I" (number) : "r0" \
+ "bx r14" : : "I" ((uint32_t)number) : "r0" \
); \
}
#elif defined (__ICCARM__)
--- a/TARGET_ARCH_BLE/TARGET_NORDIC/TARGET_MCU_NRF51822/objects.h Fri Aug 15 15:28:31 2014 +0100
+++ b/TARGET_ARCH_BLE/TARGET_NORDIC/TARGET_MCU_NRF51822/objects.h Fri Sep 12 16:41:52 2014 +0100
@@ -53,6 +53,7 @@
PinName sda;
PinName scl;
int freq;
+ uint8_t address_set;
};
struct analogin_s {
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/TARGET_STM/TARGET_STM32F407VG/PeripheralNames.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,85 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE
+} ADCName;
+
+typedef enum {
+ DAC_0 = 0,
+ DAC_1
+} DACName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_6 = (int)USART6_BASE
+} UARTName;
+
+#define STDIO_UART_TX PA_2
+#define STDIO_UART_RX PA_3
+#define STDIO_UART UART_2
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/TARGET_STM/TARGET_STM32F407VG/PortNames.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,52 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PortA = 0,
+ PortB = 1,
+ PortC = 2,
+ PortD = 3,
+ PortE = 4,
+ PortF = 5,
+ PortG = 6,
+ PortH = 7,
+ PortI = 8
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/TARGET_STM/TARGET_STM32F407VG/TARGET_ARCH_MAX/PinNames.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,280 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
+#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0)))
+#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
+#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
+#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
+#define STM_MODE_INPUT (0)
+#define STM_MODE_OUTPUT_PP (1)
+#define STM_MODE_OUTPUT_OD (2)
+#define STM_MODE_AF_PP (3)
+#define STM_MODE_AF_OD (4)
+#define STM_MODE_ANALOG (5)
+#define STM_MODE_IT_RISING (6)
+#define STM_MODE_IT_FALLING (7)
+#define STM_MODE_IT_RISING_FALLING (8)
+#define STM_MODE_EVT_RISING (9)
+#define STM_MODE_EVT_FALLING (10)
+#define STM_MODE_EVT_RISING_FALLING (11)
+
+// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
+// Low nibble = pin number
+#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
+#define STM_PIN(X) ((uint32_t)(X) & 0xF)
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_3 = 0x03,
+ PA_4 = 0x04,
+ PA_5 = 0x05,
+ PA_6 = 0x06,
+ PA_7 = 0x07,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+
+ PB_0 = 0x10,
+ PB_1 = 0x11,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_4 = 0x14,
+ PB_5 = 0x15,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_9 = 0x19,
+ PB_10 = 0x1A,
+ PB_11 = 0x1B,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_15 = 0x1F,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_7 = 0x27,
+ PC_8 = 0x28,
+ PC_9 = 0x29,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_0 = 0x30,
+ PD_1 = 0x31,
+ PD_2 = 0x32,
+ PD_3 = 0x33,
+ PD_4 = 0x34,
+ PD_5 = 0x35,
+ PD_6 = 0x36,
+ PD_7 = 0x37,
+ PD_8 = 0x38,
+ PD_9 = 0x39,
+ PD_10 = 0x3A,
+ PD_11 = 0x3B,
+ PD_12 = 0x3C,
+ PD_13 = 0x3D,
+ PD_14 = 0x3E,
+ PD_15 = 0x3F,
+
+ PE_0 = 0x40,
+ PE_1 = 0x41,
+ PE_2 = 0x42,
+ PE_3 = 0x43,
+ PE_4 = 0x44,
+ PE_5 = 0x45,
+ PE_6 = 0x46,
+ PE_7 = 0x47,
+ PE_8 = 0x48,
+ PE_9 = 0x49,
+ PE_10 = 0x4A,
+ PE_11 = 0x4B,
+ PE_12 = 0x4C,
+ PE_13 = 0x4D,
+ PE_14 = 0x4E,
+ PE_15 = 0x4F,
+
+ PF_0 = 0x50,
+ PF_1 = 0x51,
+ PF_2 = 0x52,
+ PF_3 = 0x53,
+ PF_4 = 0x54,
+ PF_5 = 0x55,
+ PF_6 = 0x56,
+ PF_7 = 0x57,
+ PF_8 = 0x58,
+ PF_9 = 0x59,
+ PF_10 = 0x5A,
+ PF_11 = 0x5B,
+ PF_12 = 0x5C,
+ PF_13 = 0x5D,
+ PF_14 = 0x5E,
+ PF_15 = 0x5F,
+
+ PG_0 = 0x60,
+ PG_1 = 0x61,
+ PG_2 = 0x62,
+ PG_3 = 0x63,
+ PG_4 = 0x64,
+ PG_5 = 0x65,
+ PG_6 = 0x66,
+ PG_7 = 0x67,
+ PG_8 = 0x68,
+ PG_9 = 0x69,
+ PG_10 = 0x6A,
+ PG_11 = 0x6B,
+ PG_12 = 0x6C,
+ PG_13 = 0x6D,
+ PG_14 = 0x6E,
+ PG_15 = 0x6F,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+ PH_2 = 0x72,
+ PH_3 = 0x73,
+ PH_4 = 0x74,
+ PH_5 = 0x75,
+ PH_6 = 0x76,
+ PH_7 = 0x77,
+ PH_8 = 0x78,
+ PH_9 = 0x79,
+ PH_10 = 0x7A,
+ PH_11 = 0x7B,
+ PH_12 = 0x7C,
+ PH_13 = 0x7D,
+ PH_14 = 0x7E,
+ PH_15 = 0x7F,
+
+ PI_0 = 0x80,
+ PI_1 = 0x81,
+ PI_2 = 0x82,
+ PI_3 = 0x83,
+ PI_4 = 0x84,
+ PI_5 = 0x85,
+ PI_6 = 0x86,
+ PI_7 = 0x87,
+ PI_8 = 0x88,
+ PI_9 = 0x89,
+ PI_10 = 0x8A,
+ PI_11 = 0x8B,
+ PI_12 = 0x8C,
+ PI_13 = 0x8D,
+ PI_14 = 0x8E,
+ PI_15 = 0x8F,
+
+
+ // Arduino connector namings
+ A0 = PA_0,
+ A1 = PA_3,
+ A2 = PA_4,
+ A3 = PA_5,
+ A4 = PA_6,
+ A5 = PB_0,
+ A6 = PB_1,
+ A7 = PC_0,
+ D0 = PD_3,
+ D1 = PD_6,
+ D2 = PD_11,
+ D3 = PD_12,
+ D4 = PD_13,
+ D5 = PA_8,
+ D6 = PB_6,
+ D7 = PB_7,
+ D8 = PB_15,
+ D9 = PB_14,
+ D10 = PA_15,
+ D11 = PB_5,
+ D12 = PB_4,
+ D13 = PB_3,
+
+ // Generic signals namings
+ LED1 = PB_3,
+ LED2 = PD_8,
+ LED3 = PD_9,
+ LED4 = PD_10,
+ USBTX = PC_6, /* USART2 */
+ USBRX = PC_7,
+ I2C_SCL = PB_8, /* I2C1 */
+ I2C_SDA = PB_9,
+ SPI_MOSI = PC_3,
+ SPI_MISO = PC_2,
+ SPI_SCK = PB_10,
+ SPI_CS = PE_3,
+ SD_MOSI = PC_3,
+ SD_MISO = PC_2,
+ SD_SCK = PB_10,
+ SD_CS = PE_2,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+ PullNone = 0,
+ PullUp = 1,
+ PullDown = 2,
+ OpenDrain = 3,
+ PullDefault = PullNone
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_ARCH_MAX/TARGET_STM/TARGET_STM32F407VG/TARGET_ARCH_MAX/device.h Fri Sep 12 16:41:52 2014 +0100 @@ -0,0 +1,70 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_RTC 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SLEEP 1 + +//======================================= + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 0 + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/TARGET_STM/TARGET_STM32F407VG/gpio_object.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,69 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "mbed_assert.h"
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ uint32_t mask;
+ __IO uint32_t *reg_in;
+ __IO uint16_t *reg_set;
+ __IO uint16_t *reg_clr;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ if (value) {
+ *obj->reg_set = obj->mask;
+ } else {
+ *obj->reg_clr = obj->mask;
+ }
+}
+
+static inline int gpio_read(gpio_t *obj) {
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/TARGET_STM/TARGET_STM32F407VG/objects.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,110 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ IRQn_Type irq_n;
+ uint32_t irq_index;
+ uint32_t event;
+ PinName pin;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ PinDirection direction;
+ __IO uint32_t *reg_in;
+ __IO uint32_t *reg_out;
+};
+
+struct analogin_s {
+ ADCName adc;
+ PinName pin;
+};
+
+struct dac_s {
+ DACName dac;
+ PinName channel;
+};
+
+struct serial_s {
+ UARTName uart;
+ int index; // Used by irq
+ uint32_t baudrate;
+ uint32_t databits;
+ uint32_t stopbits;
+ uint32_t parity;
+ PinName pin_tx;
+ PinName pin_rx;
+};
+
+struct spi_s {
+ SPIName spi;
+ uint32_t bits;
+ uint32_t cpol;
+ uint32_t cpha;
+ uint32_t mode;
+ uint32_t nss;
+ uint32_t br_presc;
+ PinName pin_miso;
+ PinName pin_mosi;
+ PinName pin_sclk;
+ PinName pin_ssel;
+};
+
+struct i2c_s {
+ I2CName i2c;
+ uint32_t slave;
+};
+
+struct pwmout_s {
+ PWMName pwm;
+ PinName pin;
+ uint32_t period;
+ uint32_t pulse;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/TOOLCHAIN_ARM_STD/STM32F407.sct Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,17 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00100000 { ; load region size_region
+ ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x10000000 0x00010000 { ; CCM
+ }
+ RW_IRAM2 0x20000188 0x0001FE78 {
+ .ANY (+RW +ZI)
+ }
+}
+
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/TOOLCHAIN_GCC_ARM/STM32F407.ld Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,157 @@
+/* Linker script for STM32F407 */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
+ CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
+ RAM (rwx) : ORIGIN = 0x20000188, LENGTH = 128k - 0x188
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+ /* KEEP(.ioview) */
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
+
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_ARCH_MAX/cmsis.h Fri Sep 12 16:41:52 2014 +0100 @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/cmsis_nvic.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,61 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// STM32F401RE
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 85 vectors = 340 bytes from 0x40 to ...
+// Total: 101 vectors = 404 bytes (0x194) to be reserved in RAM
+
+// STM32F407VG
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 82 vectors = 328 bytes from 0x40 to ...
+// Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
+
+#define NVIC_NUM_VECTORS 98
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/core_cm0.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,682 @@
+/**************************************************************************//**
+ * @file core_cm0.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+ @{
+ */
+
+/* CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+ __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0_REV
+ #define __CM0_REV 0x0000
+ #warning "__CM0_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
+ else {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/core_cm0plus.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,793 @@
+/**************************************************************************//**
+ * @file core_cm0plus.h
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+ @{
+ */
+
+/* CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+ __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0PLUS_REV
+ #define __CM0PLUS_REV 0x0000
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if (__VTOR_PRESENT == 1)
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
+ else {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/core_cm3.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,1627 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/core_cm4.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,1772 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+ @{
+ */
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x04) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+#include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/** \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1)
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
+ NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/core_cm4_simd.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,673 @@
+/**************************************************************************//**
+ * @file core_cm4_simd.h
+ * @brief CMSIS Cortex-M4 SIMD Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32) ) >> 32))
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_iar.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_ccs.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/core_cmFunc.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,636 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief Enable IRQ Interrupts
+
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief Disable IRQ Interrupts
+
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ uint32_t result;
+
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/core_cmInstr.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,688 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V3.20
+ * @date 05. March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/** \brief Breakpoint
+
+ This function causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __rbit
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX __clrex
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb");
+}
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb");
+}
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb");
+}
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (short)__builtin_bswap16(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32 - op2));
+}
+
+
+/** \brief Breakpoint
+
+ This function causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/hal_tick.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,60 @@
+/**
+ ******************************************************************************
+ * @file hal_tick.h
+ * @author MCD Application Team
+ * @brief Initialization of HAL tick
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HAL_TICK_H
+#define __HAL_TICK_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f4xx.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST TIM5
+#define TIM_MST_IRQ TIM5_IRQn
+#define TIM_MST_RCC __TIM5_CLK_ENABLE()
+
+#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
+
+#define HAL_TICK_DELAY (1000) // 1 ms
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HAL_TICK_H
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f407xx.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,7953 @@
+/**
+ ******************************************************************************
+ * @file stm32f407xx.h
+ * @author MCD Application Team
+ * @version V2.1.0
+ * @date 19-June-2014
+ * @brief CMSIS STM32F407xx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripherals registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f407xx
+ * @{
+ */
+
+#ifndef __STM32F407xx_H
+#define __STM32F407xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ FSMC_IRQn = 48, /*!< FSMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */
+ HASH_RNG_IRQn = 80, /*!< Hash and RNG global interrupt */
+ FPU_IRQn = 81 /*!< FPU global interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DCMI
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+
+/**
+ * @brief Ethernet MAC
+ */
+
+typedef struct
+{
+ __IO uint32_t MACCR;
+ __IO uint32_t MACFFR;
+ __IO uint32_t MACHTHR;
+ __IO uint32_t MACHTLR;
+ __IO uint32_t MACMIIAR;
+ __IO uint32_t MACMIIDR;
+ __IO uint32_t MACFCR;
+ __IO uint32_t MACVLANTR; /* 8 */
+ uint32_t RESERVED0[2];
+ __IO uint32_t MACRWUFFR; /* 11 */
+ __IO uint32_t MACPMTCSR;
+ uint32_t RESERVED1[2];
+ __IO uint32_t MACSR; /* 15 */
+ __IO uint32_t MACIMR;
+ __IO uint32_t MACA0HR;
+ __IO uint32_t MACA0LR;
+ __IO uint32_t MACA1HR;
+ __IO uint32_t MACA1LR;
+ __IO uint32_t MACA2HR;
+ __IO uint32_t MACA2LR;
+ __IO uint32_t MACA3HR;
+ __IO uint32_t MACA3LR; /* 24 */
+ uint32_t RESERVED2[40];
+ __IO uint32_t MMCCR; /* 65 */
+ __IO uint32_t MMCRIR;
+ __IO uint32_t MMCTIR;
+ __IO uint32_t MMCRIMR;
+ __IO uint32_t MMCTIMR; /* 69 */
+ uint32_t RESERVED3[14];
+ __IO uint32_t MMCTGFSCCR; /* 84 */
+ __IO uint32_t MMCTGFMSCCR;
+ uint32_t RESERVED4[5];
+ __IO uint32_t MMCTGFCR;
+ uint32_t RESERVED5[10];
+ __IO uint32_t MMCRFCECR;
+ __IO uint32_t MMCRFAECR;
+ uint32_t RESERVED6[10];
+ __IO uint32_t MMCRGUFCR;
+ uint32_t RESERVED7[334];
+ __IO uint32_t PTPTSCR;
+ __IO uint32_t PTPSSIR;
+ __IO uint32_t PTPTSHR;
+ __IO uint32_t PTPTSLR;
+ __IO uint32_t PTPTSHUR;
+ __IO uint32_t PTPTSLUR;
+ __IO uint32_t PTPTSAR;
+ __IO uint32_t PTPTTHR;
+ __IO uint32_t PTPTTLR;
+ __IO uint32_t RESERVED8;
+ __IO uint32_t PTPTSSR;
+ uint32_t RESERVED9[565];
+ __IO uint32_t DMABMR;
+ __IO uint32_t DMATPDR;
+ __IO uint32_t DMARPDR;
+ __IO uint32_t DMARDLAR;
+ __IO uint32_t DMATDLAR;
+ __IO uint32_t DMASR;
+ __IO uint32_t DMAOMR;
+ __IO uint32_t DMAIER;
+ __IO uint32_t DMAMFBOCR;
+ __IO uint32_t DMARSWTR;
+ uint32_t RESERVED10[8];
+ __IO uint32_t DMACHTDR;
+ __IO uint32_t DMACHRDR;
+ __IO uint32_t DMACHTBAR;
+ __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+
+/**
+ * @brief Flexible Static Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FSMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FSMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank2
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
+ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
+ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
+ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+ uint32_t RESERVED0; /*!< Reserved, 0x70 */
+ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
+ uint32_t RESERVED1; /*!< Reserved, 0x78 */
+ uint32_t RESERVED2; /*!< Reserved, 0x7C */
+ __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
+ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
+ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
+ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+ uint32_t RESERVED3; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
+} FSMC_Bank2_3_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank4
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
+ __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
+ __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
+ __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
+ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
+} FSMC_Bank4_TypeDef;
+
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
+ __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+
+
+/**
+ * @brief __USB_OTG_Core_register
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/
+ __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
+ uint32_t Reserved30[2]; /* Reserved 030h*/
+ __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
+ __IO uint32_t CID; /* User ID Register 03Ch*/
+ uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
+ __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
+ __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
+}
+USB_OTG_GlobalTypeDef;
+
+
+
+/**
+ * @brief __device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /* dev Configuration Register 800h*/
+ __IO uint32_t DCTL; /* dev Control Register 804h*/
+ __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
+ uint32_t Reserved0C; /* Reserved 80Ch*/
+ __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
+ __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
+ __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
+ __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
+ uint32_t Reserved20; /* Reserved 820h*/
+ uint32_t Reserved9; /* Reserved 824h*/
+ __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
+ __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
+ __IO uint32_t DTHRCTL; /* dev thr 830h*/
+ __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
+ __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
+ __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
+ uint32_t Reserved40; /* dedicated EP mask 840h*/
+ __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
+ uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
+ __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
+}
+USB_OTG_DeviceTypeDef;
+
+
+/**
+ * @brief __IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
+ __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
+ uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
+}
+USB_OTG_INEndpointTypeDef;
+
+
+/**
+ * @brief __OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
+ uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+}
+USB_OTG_OUTEndpointTypeDef;
+
+
+/**
+ * @brief __Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /* Host Configuration Register 400h*/
+ __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
+ __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
+ uint32_t Reserved40C; /* Reserved 40Ch*/
+ __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
+ __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
+ __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
+}
+USB_OTG_HostTypeDef;
+
+
+/**
+ * @brief __Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR;
+ __IO uint32_t HCSPLT;
+ __IO uint32_t HCINT;
+ __IO uint32_t HCINTMSK;
+ __IO uint32_t HCTSIZ;
+ __IO uint32_t HCDMA;
+ uint32_t Reserved[2];
+}
+USB_OTG_HostChannelTypeDef;
+
+
+/**
+ * @brief Peripheral_memory_map
+ */
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
+#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
+#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
+#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
+#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
+#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
+#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
+#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
+#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */
+#define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
+#define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
+#define ETH_MAC_BASE (ETH_BASE)
+#define ETH_MMC_BASE (ETH_BASE + 0x0100)
+#define ETH_PTP_BASE (ETH_BASE + 0x0700)
+#define ETH_DMA_BASE (ETH_BASE + 0x1000)
+
+/*!< AHB2 peripherals */
+#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
+
+/*!< FSMC Bankx registers base address */
+#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
+#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
+#define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060)
+#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE ((uint32_t )0xE0042000)
+
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
+#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
+
+#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
+#define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
+#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
+#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
+#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
+#define USB_OTG_HOST_BASE ((uint32_t )0x400)
+#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
+#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
+#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
+#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
+#define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
+#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define ETH ((ETH_TypeDef *) ETH_BASE)
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
+#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
+#define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
+#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
+#define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
+#define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
+#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
+#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
+#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
+#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
+#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
+#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
+#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
+#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
+#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
+#define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
+#define CAN_MCR_DBF ((uint32_t)0x00010000) /*!<bxCAN Debug freeze */
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK ((uint32_t)0x0001) /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK ((uint32_t)0x0002) /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI ((uint32_t)0x0004) /*!<Error Interrupt */
+#define CAN_MSR_WKUI ((uint32_t)0x0008) /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI ((uint32_t)0x0010) /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM ((uint32_t)0x0100) /*!<Transmit Mode */
+#define CAN_MSR_RXM ((uint32_t)0x0200) /*!<Receive Mode */
+#define CAN_MSR_SAMP ((uint32_t)0x0400) /*!<Last Sample Point */
+#define CAN_MSR_RX ((uint32_t)0x0800) /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
+
+#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
+#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 ((uint32_t)0x03) /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 ((uint32_t)0x08) /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0 ((uint32_t)0x10) /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 ((uint32_t)0x20) /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 ((uint32_t)0x03) /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 ((uint32_t)0x08) /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1 ((uint32_t)0x10) /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 ((uint32_t)0x20) /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error warning interrupt enable */
+#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error passive interrupt enable */
+#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-off interrupt enable */
+#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last error code interrupt enable */
+#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error interrupt enable */
+
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
+#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
+#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
+#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
+#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
+#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
+#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT ((uint32_t)0x01) /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM ((uint32_t)0x3FFF) /*!<Filter Mode */
+#define CAN_FM1R_FBM0 ((uint32_t)0x0001) /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 ((uint32_t)0x0002) /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 ((uint32_t)0x0004) /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 ((uint32_t)0x0008) /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 ((uint32_t)0x0010) /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 ((uint32_t)0x0020) /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 ((uint32_t)0x0040) /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 ((uint32_t)0x0080) /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 ((uint32_t)0x0100) /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 ((uint32_t)0x0200) /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 ((uint32_t)0x0400) /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 ((uint32_t)0x0800) /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 ((uint32_t)0x1000) /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 ((uint32_t)0x2000) /*!<Filter Init Mode bit 13 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC ((uint32_t)0x3FFF) /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 ((uint32_t)0x0001) /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 ((uint32_t)0x0002) /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 ((uint32_t)0x0004) /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 ((uint32_t)0x0008) /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 ((uint32_t)0x0010) /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 ((uint32_t)0x0020) /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 ((uint32_t)0x0040) /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 ((uint32_t)0x0080) /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 ((uint32_t)0x0100) /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 ((uint32_t)0x0200) /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 ((uint32_t)0x0400) /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 ((uint32_t)0x0800) /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 ((uint32_t)0x1000) /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 ((uint32_t)0x2000) /*!<Filter Scale Configuration bit 13 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA ((uint32_t)0x3FFF) /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 ((uint32_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
+#define CAN_FFA1R_FFA1 ((uint32_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
+#define CAN_FFA1R_FFA2 ((uint32_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
+#define CAN_FFA1R_FFA3 ((uint32_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
+#define CAN_FFA1R_FFA4 ((uint32_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
+#define CAN_FFA1R_FFA5 ((uint32_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
+#define CAN_FFA1R_FFA6 ((uint32_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
+#define CAN_FFA1R_FFA7 ((uint32_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
+#define CAN_FFA1R_FFA8 ((uint32_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
+#define CAN_FFA1R_FFA9 ((uint32_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
+#define CAN_FFA1R_FFA10 ((uint32_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
+#define CAN_FFA1R_FFA11 ((uint32_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
+#define CAN_FFA1R_FFA12 ((uint32_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
+#define CAN_FFA1R_FFA13 ((uint32_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT ((uint32_t)0x3FFF) /*!<Filter Active */
+#define CAN_FA1R_FACT0 ((uint32_t)0x0001) /*!<Filter 0 Active */
+#define CAN_FA1R_FACT1 ((uint32_t)0x0002) /*!<Filter 1 Active */
+#define CAN_FA1R_FACT2 ((uint32_t)0x0004) /*!<Filter 2 Active */
+#define CAN_FA1R_FACT3 ((uint32_t)0x0008) /*!<Filter 3 Active */
+#define CAN_FA1R_FACT4 ((uint32_t)0x0010) /*!<Filter 4 Active */
+#define CAN_FA1R_FACT5 ((uint32_t)0x0020) /*!<Filter 5 Active */
+#define CAN_FA1R_FACT6 ((uint32_t)0x0040) /*!<Filter 6 Active */
+#define CAN_FA1R_FACT7 ((uint32_t)0x0080) /*!<Filter 7 Active */
+#define CAN_FA1R_FACT8 ((uint32_t)0x0100) /*!<Filter 8 Active */
+#define CAN_FA1R_FACT9 ((uint32_t)0x0200) /*!<Filter 9 Active */
+#define CAN_FA1R_FACT10 ((uint32_t)0x0400) /*!<Filter 10 Active */
+#define CAN_FA1R_FACT11 ((uint32_t)0x0800) /*!<Filter 11 Active */
+#define CAN_FA1R_FACT12 ((uint32_t)0x1000) /*!<Filter 12 Active */
+#define CAN_FA1R_FACT13 ((uint32_t)0x2000) /*!<Filter 13 Active */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
+
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
+
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
+
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* DCMI */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DCMI_CR register ******************/
+#define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
+#define DCMI_CR_CM ((uint32_t)0x00000002)
+#define DCMI_CR_CROP ((uint32_t)0x00000004)
+#define DCMI_CR_JPEG ((uint32_t)0x00000008)
+#define DCMI_CR_ESS ((uint32_t)0x00000010)
+#define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
+#define DCMI_CR_HSPOL ((uint32_t)0x00000040)
+#define DCMI_CR_VSPOL ((uint32_t)0x00000080)
+#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
+#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
+#define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
+#define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
+#define DCMI_CR_CRE ((uint32_t)0x00001000)
+#define DCMI_CR_ENABLE ((uint32_t)0x00004000)
+
+/******************** Bits definition for DCMI_SR register ******************/
+#define DCMI_SR_HSYNC ((uint32_t)0x00000001)
+#define DCMI_SR_VSYNC ((uint32_t)0x00000002)
+#define DCMI_SR_FNE ((uint32_t)0x00000004)
+
+/******************** Bits definition for DCMI_RISR register ****************/
+#define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
+#define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
+#define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
+#define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
+#define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
+
+/******************** Bits definition for DCMI_IER register *****************/
+#define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
+#define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
+#define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
+#define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
+#define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
+
+/******************** Bits definition for DCMI_MISR register ****************/
+#define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
+#define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
+#define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
+#define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
+#define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
+
+/******************** Bits definition for DCMI_ICR register *****************/
+#define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
+#define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
+#define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
+#define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
+#define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
+#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
+#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
+#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
+#define DMA_SxCR_MBURST ((uint32_t)0x01800000)
+#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
+#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
+#define DMA_SxCR_PBURST ((uint32_t)0x00600000)
+#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
+#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
+#define DMA_SxCR_ACK ((uint32_t)0x00100000)
+#define DMA_SxCR_CT ((uint32_t)0x00080000)
+#define DMA_SxCR_DBM ((uint32_t)0x00040000)
+#define DMA_SxCR_PL ((uint32_t)0x00030000)
+#define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
+#define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
+#define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
+#define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
+#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
+#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
+#define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
+#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
+#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
+#define DMA_SxCR_MINC ((uint32_t)0x00000400)
+#define DMA_SxCR_PINC ((uint32_t)0x00000200)
+#define DMA_SxCR_CIRC ((uint32_t)0x00000100)
+#define DMA_SxCR_DIR ((uint32_t)0x000000C0)
+#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
+#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
+#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
+#define DMA_SxCR_TCIE ((uint32_t)0x00000010)
+#define DMA_SxCR_HTIE ((uint32_t)0x00000008)
+#define DMA_SxCR_TEIE ((uint32_t)0x00000004)
+#define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
+#define DMA_SxCR_EN ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT ((uint32_t)0x0000FFFF)
+#define DMA_SxNDT_0 ((uint32_t)0x00000001)
+#define DMA_SxNDT_1 ((uint32_t)0x00000002)
+#define DMA_SxNDT_2 ((uint32_t)0x00000004)
+#define DMA_SxNDT_3 ((uint32_t)0x00000008)
+#define DMA_SxNDT_4 ((uint32_t)0x00000010)
+#define DMA_SxNDT_5 ((uint32_t)0x00000020)
+#define DMA_SxNDT_6 ((uint32_t)0x00000040)
+#define DMA_SxNDT_7 ((uint32_t)0x00000080)
+#define DMA_SxNDT_8 ((uint32_t)0x00000100)
+#define DMA_SxNDT_9 ((uint32_t)0x00000200)
+#define DMA_SxNDT_10 ((uint32_t)0x00000400)
+#define DMA_SxNDT_11 ((uint32_t)0x00000800)
+#define DMA_SxNDT_12 ((uint32_t)0x00001000)
+#define DMA_SxNDT_13 ((uint32_t)0x00002000)
+#define DMA_SxNDT_14 ((uint32_t)0x00004000)
+#define DMA_SxNDT_15 ((uint32_t)0x00008000)
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
+#define DMA_SxFCR_FS ((uint32_t)0x00000038)
+#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
+#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
+#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
+#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
+#define DMA_SxFCR_FTH ((uint32_t)0x00000003)
+#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
+#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
+#define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
+#define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
+#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
+#define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
+#define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
+#define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
+#define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
+#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
+#define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
+#define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
+#define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
+#define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
+#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
+#define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
+#define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
+#define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
+#define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
+#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
+#define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
+#define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
+#define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
+#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
+#define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
+#define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
+#define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
+#define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
+#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
+#define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
+#define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
+#define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
+#define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
+#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
+#define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
+#define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
+#define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
+#define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
+#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
+#define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
+#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
+#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
+#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
+#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
+#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
+#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
+#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
+#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
+#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
+#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
+#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
+#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
+#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
+#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
+#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
+#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
+#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
+#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
+#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
+#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
+#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
+#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
+#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
+#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
+#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
+#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
+#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
+#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
+#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
+#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
+#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
+#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
+#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
+#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
+#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
+#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
+#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
+#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
+#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
+#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
+#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
+#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
+#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
+#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
+#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
+#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
+
+#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
+#define FLASH_ACR_ICEN ((uint32_t)0x00000200)
+#define FLASH_ACR_DCEN ((uint32_t)0x00000400)
+#define FLASH_ACR_ICRST ((uint32_t)0x00000800)
+#define FLASH_ACR_DCRST ((uint32_t)0x00001000)
+#define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
+#define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP ((uint32_t)0x00000001)
+#define FLASH_SR_SOP ((uint32_t)0x00000002)
+#define FLASH_SR_WRPERR ((uint32_t)0x00000010)
+#define FLASH_SR_PGAERR ((uint32_t)0x00000020)
+#define FLASH_SR_PGPERR ((uint32_t)0x00000040)
+#define FLASH_SR_PGSERR ((uint32_t)0x00000080)
+#define FLASH_SR_BSY ((uint32_t)0x00010000)
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG ((uint32_t)0x00000001)
+#define FLASH_CR_SER ((uint32_t)0x00000002)
+#define FLASH_CR_MER ((uint32_t)0x00000004)
+#define FLASH_CR_SNB ((uint32_t)0x000000F8)
+#define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
+#define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
+#define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
+#define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
+#define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
+#define FLASH_CR_PSIZE ((uint32_t)0x00000300)
+#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
+#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
+#define FLASH_CR_STRT ((uint32_t)0x00010000)
+#define FLASH_CR_EOPIE ((uint32_t)0x01000000)
+#define FLASH_CR_LOCK ((uint32_t)0x80000000)
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
+#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
+#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
+#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
+#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
+
+#define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
+#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
+#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
+#define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
+#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
+#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
+#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
+#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
+#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
+#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
+#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
+#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
+#define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
+#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
+#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
+#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
+#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
+#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
+#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
+#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
+#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
+#define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
+#define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
+#define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
+#define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
+#define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
+#define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
+#define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
+#define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
+#define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
+#define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
+#define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
+#define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
+#define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
+#define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
+#define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
+#define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
+
+/******************************************************************************/
+/* */
+/* Flexible Static Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FSMC_BCR1 register *******************/
+#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR2 register *******************/
+#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR3 register *******************/
+#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR4 register *******************/
+#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BTR1 register ******************/
+#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BTR2 register *******************/
+#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/******************* Bit definition for FSMC_BTR3 register *******************/
+#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BTR4 register *******************/
+#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR1 register ******************/
+#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR2 register ******************/
+#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
+#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR3 register ******************/
+#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR4 register ******************/
+#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_PCR2 register *******************/
+#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
+#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+
+#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+
+#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+
+#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
+#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+
+/****************** Bit definition for FSMC_PCR3 register *******************/
+#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
+#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+
+#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+
+#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+
+#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
+#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+
+/****************** Bit definition for FSMC_PCR4 register *******************/
+#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
+#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+
+#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+
+#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+
+#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
+#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+
+/******************* Bit definition for FSMC_SR2 register *******************/
+#define FSMC_SR2_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
+#define FSMC_SR2_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
+#define FSMC_SR2_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
+#define FSMC_SR2_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR2_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
+#define FSMC_SR2_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR2_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
+
+/******************* Bit definition for FSMC_SR3 register *******************/
+#define FSMC_SR3_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
+#define FSMC_SR3_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
+#define FSMC_SR3_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
+#define FSMC_SR3_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR3_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
+#define FSMC_SR3_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR3_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
+
+/******************* Bit definition for FSMC_SR4 register *******************/
+#define FSMC_SR4_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
+#define FSMC_SR4_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
+#define FSMC_SR4_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
+#define FSMC_SR4_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR4_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
+#define FSMC_SR4_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR4_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
+
+/****************** Bit definition for FSMC_PMEM2 register ******************/
+#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PMEM3 register ******************/
+#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PMEM4 register ******************/
+#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PATT2 register ******************/
+#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PATT3 register ******************/
+#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PATT4 register ******************/
+#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PIO4 register *******************/
+#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_ECCR2 register ******************/
+#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
+
+/****************** Bit definition for FSMC_ECCR3 register ******************/
+#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
+
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
+
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
+
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
+
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
+
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
+
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
+
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
+
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
+
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
+
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
+
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
+
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
+
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
+
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
+
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
+#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
+#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
+
+#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
+#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
+
+#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
+#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
+#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
+
+#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
+#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
+
+#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
+#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
+#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
+
+#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
+#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
+
+#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
+#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
+#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
+
+#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
+#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
+
+#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
+#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
+#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
+
+#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
+#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
+
+#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
+#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
+#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
+
+#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
+#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
+
+#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
+#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
+#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
+
+#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
+#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
+
+#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
+#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
+#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
+
+#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
+#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
+
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
+
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
+
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
+
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
+
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
+
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
+
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
+
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
+
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
+
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
+
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
+
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
+
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
+
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
+
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
+#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
+#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
+#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
+#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
+#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
+#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
+#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
+#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
+#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
+#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
+#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
+#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
+#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
+#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
+#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
+#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
+#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
+#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
+#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
+#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
+#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
+#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
+#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
+#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
+#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
+#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
+#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
+#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
+#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
+#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
+#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
+#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
+#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
+#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
+#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
+#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
+#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
+#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
+#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
+#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
+#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
+#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
+#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
+#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
+#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
+#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
+#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
+#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
+#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
+#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
+#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
+#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
+#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
+#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
+#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
+#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
+#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
+#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
+#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
+#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
+#define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
+#define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
+#define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
+#define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
+#define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
+#define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
+#define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
+#define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
+#define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
+#define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
+#define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
+#define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
+#define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
+#define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
+#define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
+#define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
+#define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
+
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
+#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
+#define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
+#define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
+#define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION ((uint32_t)0x00000001)
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
+
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
+#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
+
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
+#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
+
+#define RCC_CR_HSEON ((uint32_t)0x00010000)
+#define RCC_CR_HSERDY ((uint32_t)0x00020000)
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
+#define RCC_CR_CSSON ((uint32_t)0x00080000)
+#define RCC_CR_PLLON ((uint32_t)0x01000000)
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
+#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
+#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
+#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
+#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
+#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
+#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
+#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
+#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
+
+#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
+#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
+#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
+#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
+#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
+#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
+#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
+#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
+#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
+#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
+
+#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
+#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
+#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
+
+#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
+#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
+#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
+
+#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
+#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
+#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
+#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
+#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
+#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
+#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
+#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
+#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
+#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
+#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
+#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
+
+#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
+
+#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
+#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
+#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
+#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
+
+#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
+#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
+#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
+#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
+
+#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
+#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
+#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
+#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
+
+#define RCC_CIR_CSSF ((uint32_t)0x00000080)
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
+#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
+
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
+#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
+
+#define RCC_CIR_CSSC ((uint32_t)0x00800000)
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
+#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
+#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
+#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
+#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
+#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
+#define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
+#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
+#define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
+#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
+#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
+#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
+#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
+#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
+#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
+#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
+
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+
+#define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001)
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
+#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
+#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
+#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
+#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
+#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
+#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
+#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
+#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
+#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
+#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
+#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
+#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
+#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
+#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
+#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
+#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
+#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
+#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
+#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
+#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
+#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
+#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
+#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
+#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
+#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
+#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
+#define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
+#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
+#define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
+#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
+#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
+#define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
+#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
+#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
+
+#define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
+#define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
+#define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
+#define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
+#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
+#define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
+
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+#define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
+#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
+#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+
+#define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
+#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
+#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
+#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
+#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
+#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
+#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
+#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
+#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
+#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
+#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
+#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
+#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
+#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
+#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
+#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
+#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
+#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
+#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
+#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
+#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
+#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
+#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
+#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
+#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
+#define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
+#define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
+#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
+#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
+#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
+#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
+#define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
+#define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
+#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
+#define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
+#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
+#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
+#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
+#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
+#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
+#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
+#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
+#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
+#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
+#define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
+#define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
+#define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
+#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
+#define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
+#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
+#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+
+#define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
+#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
+#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
+#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
+#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
+#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
+#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
+#define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
+#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
+#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
+#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
+#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
+#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
+#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
+#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
+#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
+#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
+#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
+#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
+#define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
+#define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
+#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
+#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
+#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
+#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
+#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
+#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
+#define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200)
+#define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
+#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
+#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
+#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
+#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
+#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
+#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001)
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000)
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001)
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
+#define RCC_CSR_RMVF ((uint32_t)0x01000000)
+#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
+#define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
+#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
+#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
+#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
+#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
+#define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
+#define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
+#define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
+#define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
+#define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
+#define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
+#define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
+#define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
+#define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
+
+#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
+#define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
+#define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
+#define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN ((uint32_t)0x00000004)
+#define RNG_CR_IE ((uint32_t)0x00000008)
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY ((uint32_t)0x00000001)
+#define RNG_SR_CECS ((uint32_t)0x00000002)
+#define RNG_SR_SECS ((uint32_t)0x00000004)
+#define RNG_SR_CEIS ((uint32_t)0x00000020)
+#define RNG_SR_SEIS ((uint32_t)0x00000040)
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM ((uint32_t)0x00400000)
+#define RTC_TR_HT ((uint32_t)0x00300000)
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TR_HU ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TR_MNT ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TR_MNU ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TR_ST ((uint32_t)0x00000070)
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TR_SU ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)
+#define RTC_DR_YU ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)
+#define RTC_DR_WDU ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DR_MT ((uint32_t)0x00001000)
+#define RTC_DR_MU ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)
+#define RTC_DR_DT ((uint32_t)0x00000030)
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)
+#define RTC_DR_DU ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE ((uint32_t)0x00800000)
+#define RTC_CR_OSEL ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
+#define RTC_CR_POL ((uint32_t)0x00100000)
+#define RTC_CR_COSEL ((uint32_t)0x00080000)
+#define RTC_CR_BCK ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)
+#define RTC_CR_TSIE ((uint32_t)0x00008000)
+#define RTC_CR_WUTIE ((uint32_t)0x00004000)
+#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
+#define RTC_CR_TSE ((uint32_t)0x00000800)
+#define RTC_CR_WUTE ((uint32_t)0x00000400)
+#define RTC_CR_ALRBE ((uint32_t)0x00000200)
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)
+#define RTC_CR_DCE ((uint32_t)0x00000080)
+#define RTC_CR_FMT ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
+#define RTC_ISR_TSF ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF ((uint32_t)0x00000400)
+#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
+#define RTC_ISR_INIT ((uint32_t)0x00000080)
+#define RTC_ISR_INITF ((uint32_t)0x00000040)
+#define RTC_ISR_RSF ((uint32_t)0x00000020)
+#define RTC_ISR_INITS ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
+#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS ((uint32_t)0x00000080)
+#define RTC_CALIBR_DC ((uint32_t)0x0000001F)
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM ((uint32_t)0x00400000)
+#define RTC_TSTR_HT ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TSTR_ST ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSDR_MT ((uint32_t)0x00001000)
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
+#define RTC_TSDR_DT ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
+#define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
+#define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
+
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
+
+#define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
+#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
+#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
+#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
+#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
+#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
+
+#define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+
+#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
+#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
+#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
+#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
+#define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
+#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
+#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
+#define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
+#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
+#define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
+#define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
+#define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
+#define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
+#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
+#define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
+
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
+/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
+#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /*!<PI[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /*!<PI[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /*!<PI[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /*!<PI[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /*!<PI[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /*!<PI[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /*!<PI[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /*!<PI[7] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /*!<PI[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /*!<PI[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /*!<PI[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /*!<PI[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
+#define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
+#define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
+
+#define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
+#define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
+#define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
+#define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
+#define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
+#define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
+#define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
+#define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
+#define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
+#define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
+#define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
+#define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
+#define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
+#define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
+#define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
+#define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
+#define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
+#define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
+#define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
+#define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
+#define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
+#define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
+#define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
+#define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
+#define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
+#define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
+#define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
+#define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
+#define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
+#define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
+
+#define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
+
+#define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
+#define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
+#define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
+#define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
+#define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
+#define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
+#define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
+#define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
+
+#define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
+#define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
+#define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
+#define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
+#define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
+#define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
+#define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
+
+#define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
+
+#define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
+
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
+
+/******************************************************************************/
+/* */
+/* Ethernet MAC Registers bits definitions */
+/* */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
+#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
+#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
+ #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
+ #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
+ #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
+ #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
+ #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
+ #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
+ #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
+#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
+#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
+#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
+#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
+#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
+#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
+#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+ a transmission attempt during retries after a collision: 0 =< r <2^k */
+ #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
+ #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
+ #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
+ #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
+#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
+#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
+#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
+#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
+#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
+#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
+#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
+ #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
+ #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
+ #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
+#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
+#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
+#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
+#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
+#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
+#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
+#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
+ #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+ #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
+ #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+ #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+ #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
+#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
+#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
+
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
+#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
+ #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
+ #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
+ #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
+ #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
+#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
+#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
+#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+ Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+ Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+ Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+ Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+ Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
+ RSVD - Filter1 Command - RSVD - Filter0 Command
+ Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+ Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+ Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */
+#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
+#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
+#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
+#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
+#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
+#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
+#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+ #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
+#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
+#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
+ #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
+#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
+#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
+ #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
+
+/******************************************************************************/
+/* Ethernet MMC Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
+#define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
+#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
+#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
+#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/* Ethernet PTP Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
+#define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
+
+#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
+#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
+
+/* Bit definition for Ethernet PTP Time Stamp Status Register */
+#define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
+
+/******************************************************************************/
+/* Ethernet DMA Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
+#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
+#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
+#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
+ #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+ #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+ #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+ #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
+#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
+#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
+ #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+ #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+ #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+ #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
+#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
+#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
+#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
+#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
+ /* combination with EBS[2:0] for GetFlagStatus function */
+ #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
+ #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
+ #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
+ #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
+ #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
+ #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
+ #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
+ #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
+ #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
+ #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
+ #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
+ #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
+ #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
+ #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
+ #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
+#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
+#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
+#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
+#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
+#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
+#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
+#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
+#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
+#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
+#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
+#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
+#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
+ #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+ #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+ #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+ #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+ #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+ #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+ #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+ #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
+#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
+ #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
+ #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
+ #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
+ #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
+#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
+#define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) /*!< B-session valid */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
+
+/******************** Bit definition forUSB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
+
+/******************** Bit definition forUSB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
+
+/******************** Bit definition forUSB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
+
+/******************** Bit definition forUSB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
+
+/******************** Bit definition forUSB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
+
+/******************** Bit definition forUSB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
+
+/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
+
+/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
+
+#define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
+
+/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
+
+#define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/******************** Bit definition forUSB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
+
+/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition forUSB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition forUSB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
+#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
+
+#define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
+#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
+#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+
+#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
+#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
+#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
+
+#define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
+#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
+#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+
+#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
+#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
+
+/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
+
+/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+
+/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
+
+/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition forUSB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) /*!< Enable I2C bus connection for the external I2C PHY interface */
+#define USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) /*!< VBUS sensing disable option */
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition forUSB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
+
+/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
+#define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
+
+/******************** Bit definition forUSB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
+
+/******************** Bit definition forUSB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
+#define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
+
+/******************** Bit definition forUSB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
+/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space avail */
+
+/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
+
+/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2) || \
+ ((INSTANCE) == ADC3))
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2))
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH) || \
+ ((INSTANCE) == GPIOI))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32F4xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F4 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define FMC_IRQn FSMC_IRQn
+
+/* Aliases for __IRQHandler */
+#define FMC_IRQHandler FSMC_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F407xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,222 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx.h
+ * @author MCD Application Team
+ * @version V2.1.0RC2
+ * @date 14-May-2014
+ * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F4xx device used in the target application
+ * - To use or not the peripherals drivers in application code(i.e.
+ * code will be based on direct access to peripherals registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx
+ * @{
+ */
+
+#ifndef __STM32F4xx_H
+#define __STM32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+
+#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
+ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE)
+ /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
+ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
+ #define STM32F407xx /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
+ /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+ /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
+ /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
+ /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
+ STM32F439NI, STM32F429IG and STM32F429II Devices */
+ /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
+ STM32F439NI, STM32F439IG and STM32F439II Devices */
+ /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
+ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+ /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+#define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS Device version number V2.1.0RC2
+ */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x02) /*!< [7:0] release candidate */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
+ |(__CMSIS_DEVICE_HAL_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F405xx)
+ #include "stm32f405xx.h"
+#elif defined(STM32F415xx)
+ #include "stm32f415xx.h"
+#elif defined(STM32F407xx)
+ #include "stm32f407xx.h"
+#elif defined(STM32F417xx)
+ #include "stm32f417xx.h"
+#elif defined(STM32F427xx)
+ #include "stm32f427xx.h"
+#elif defined(STM32F437xx)
+ #include "stm32f437xx.h"
+#elif defined(STM32F429xx)
+ #include "stm32f429xx.h"
+#elif defined(STM32F439xx)
+ #include "stm32f439xx.h"
+#elif defined(STM32F401xC)
+ #include "stm32f401xc.h"
+#elif defined(STM32F401xE)
+ #include "stm32f401xe.h"
+#elif defined(STM32F411xE)
+ #include "stm32f411xe.h"
+#else
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,194 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief This file contains all the functions prototypes for the HAL
+ * module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_H
+#define __STM32F4xx_HAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_conf.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HAL
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Freeze/Unfreeze Peripherals in Debug mode
+ */
+#define __HAL_FREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
+#define __HAL_FREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
+#define __HAL_FREEZE_TIM4_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
+#define __HAL_FREEZE_TIM5_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
+#define __HAL_FREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
+#define __HAL_FREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
+#define __HAL_FREEZE_TIM12_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
+#define __HAL_FREEZE_TIM13_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
+#define __HAL_FREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
+#define __HAL_FREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
+#define __HAL_FREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
+#define __HAL_FREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
+#define __HAL_FREEZE_CAN1_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
+#define __HAL_FREEZE_CAN2_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
+#define __HAL_FREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
+#define __HAL_FREEZE_TIM8_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
+#define __HAL_FREEZE_TIM9_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
+#define __HAL_FREEZE_TIM10_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
+#define __HAL_FREEZE_TIM11_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
+
+#define __HAL_UNFREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
+#define __HAL_UNFREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
+#define __HAL_UNFREEZE_TIM4_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
+#define __HAL_UNFREEZE_TIM5_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
+#define __HAL_UNFREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
+#define __HAL_UNFREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
+#define __HAL_UNFREEZE_TIM12_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
+#define __HAL_UNFREEZE_TIM13_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
+#define __HAL_UNFREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
+#define __HAL_UNFREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
+#define __HAL_UNFREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
+#define __HAL_UNFREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
+#define __HAL_UNFREEZE_CAN1_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
+#define __HAL_UNFREEZE_CAN2_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
+#define __HAL_UNFREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
+#define __HAL_UNFREEZE_TIM8_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
+#define __HAL_UNFREEZE_TIM9_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
+#define __HAL_UNFREEZE_TIM10_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
+#define __HAL_UNFREEZE_TIM11_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
+
+/** @brief Main Flash memory mapped at 0x00000000
+ */
+#define __HAL_REMAPMEMORY_FLASH() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE))
+
+/** @brief System Flash memory mapped at 0x00000000
+ */
+#define __HAL_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+ SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\
+ }while(0);
+
+/** @brief Embedded SRAM mapped at 0x00000000
+ */
+#define __HAL_REMAPMEMORY_SRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+ SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\
+ }while(0);
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+/** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
+ */
+#define __HAL_REMAPMEMORY_FSMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+ SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
+ }while(0);
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+/** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
+ */
+#define __HAL_REMAPMEMORY_FMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+ SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
+ }while(0);
+
+/** @brief FMC/SDRAM Bank 1 and 2 mapped at 0x00000000
+ */
+#define __HAL_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+ SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2);\
+ }while(0);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions ******************************/
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void HAL_MspInit(void);
+void HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
+
+/* Peripheral Control functions ************************************************/
+void HAL_IncTick(void);
+void HAL_Delay(__IO uint32_t Delay);
+uint32_t HAL_GetTick(void);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+void HAL_EnableDBGSleepMode(void);
+void HAL_DisableDBGSleepMode(void);
+void HAL_EnableDBGStopMode(void);
+void HAL_DisableDBGStopMode(void);
+void HAL_EnableDBGStandbyMode(void);
+void HAL_DisableDBGStandbyMode(void);
+void HAL_EnableCompensationCell(void);
+void HAL_DisableCompensationCell(void);
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+void HAL_EnableMemorySwappingBank(void);
+void HAL_DisableMemorySwappingBank(void);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_adc.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,705 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_adc.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of ADC HAL extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_ADC_H
+#define __STM32F4xx_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */
+ HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */
+ HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
+ HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */
+ HAL_ADC_STATE_BUSY_INJ = 0x22, /*!< Injected conversion is ongoing */
+ HAL_ADC_STATE_BUSY_INJ_REG = 0x32, /*!< Injected and regular conversion are ongoing */
+ HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */
+ HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */
+ HAL_ADC_STATE_EOC_REG = 0x15, /*!< Regular conversion is completed */
+ HAL_ADC_STATE_EOC_INJ = 0x25, /*!< Injected conversion is completed */
+ HAL_ADC_STATE_EOC_INJ_REG = 0x35, /*!< Injected and regular conversion are completed */
+ HAL_ADC_STATE_AWD = 0x06 /*!< ADC state analog watchdog */
+
+}HAL_ADC_StateTypeDef;
+
+/**
+ * @brief ADC Init structure definition
+ */
+typedef struct
+{
+ uint32_t ClockPrescaler; /*!< Select the frequency of the clock to the ADC. The clock is common for
+ all the ADCs.
+ This parameter can be a value of @ref ADC_ClockPrescaler */
+ uint32_t Resolution; /*!< Configures the ADC resolution dual mode.
+ This parameter can be a value of @ref ADC_Resolution */
+ uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
+ This parameter can be a value of @ref ADC_data_align */
+ uint32_t ScanConvMode; /*!< Specifies whether the conversion is performed in Scan (multi channels) or
+ Single (one channel) mode.
+ This parameter can be set to ENABLE or DISABLE */
+ uint32_t EOCSelection; /*!< Specifies whether the EOC flag is set
+ at the end of single channel conversion or at the end of all conversions.
+ This parameter can be a value of @ref ADC_EOCSelection */
+ uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in Continuous or Single mode.
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests is performed in Continuous or in Single mode.
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done using the sequencer for
+ regular channel group.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
+ uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous or not
+ for regular channels.
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t NbrOfDiscConversion; /*!< Specifies the number of ADC discontinuous conversions that will be done
+ using the sequencer for regular channel group.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
+ uint32_t ExternalTrigConvEdge; /*!< Select the external trigger edge and enable the trigger of a regular group.
+ This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
+ uint32_t ExternalTrigConv; /*!< Select the external event used to trigger the start of conversion of a regular group.
+ This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
+}ADC_InitTypeDef;
+
+/**
+ * @brief ADC handle Structure definition
+ */
+typedef struct
+{
+ ADC_TypeDef *Instance; /*!< Register base address */
+
+ ADC_InitTypeDef Init; /*!< ADC required parameters */
+
+ __IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */
+
+ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
+
+ HAL_LockTypeDef Lock; /*!< ADC locking object */
+
+ __IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */
+
+ __IO uint32_t ErrorCode; /*!< ADC Error code */
+}ADC_HandleTypeDef;
+
+/**
+ * @brief ADC Configuration regular Channel structure definition
+ */
+typedef struct
+{
+ uint32_t Channel; /*!< The ADC channel to configure.
+ This parameter can be a value of @ref ADC_channels */
+ uint32_t Rank; /*!< The rank in the regular group sequencer.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
+ uint32_t SamplingTime; /*!< The sample time value to be set for the selected channel.
+ This parameter can be a value of @ref ADC_sampling_times */
+ uint32_t Offset; /*!< Reserved for future use, can be set to 0 */
+}ADC_ChannelConfTypeDef;
+
+/**
+ * @brief ADC Configuration multi-mode structure definition
+ */
+typedef struct
+{
+ uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode.
+ This parameter can be a value of @ref ADC_analog_watchdog_selection */
+ uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
+ This parameter must be a 12-bit value. */
+ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
+ This parameter must be a 12-bit value. */
+ uint32_t Channel; /*!< Configures ADC channel for the analog watchdog.
+ This parameter has an effect only if watchdog mode is configured on single channel
+ This parameter can be a value of @ref ADC_channels */
+ uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured
+ is interrupt mode or in polling mode.
+ This parameter can be set to ENABLE or DISABLE */
+ uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
+}ADC_AnalogWDGConfTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants
+ * @{
+ */
+
+
+/** @defgroup ADC_Error_Code
+ * @{
+ */
+
+#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
+#define HAL_ADC_ERROR_OVR ((uint32_t)0x01) /*!< OVR error */
+#define HAL_ADC_ERROR_DMA ((uint32_t)0x02) /*!< DMA transfer error */
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_ClockPrescaler
+ * @{
+ */
+#define ADC_CLOCKPRESCALER_PCLK_DIV2 ((uint32_t)0x00000000)
+#define ADC_CLOCKPRESCALER_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
+#define ADC_CLOCKPRESCALER_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
+#define ADC_CLOCKPRESCALER_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
+#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV2) || \
+ ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV4) || \
+ ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV6) || \
+ ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV8))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Resolution
+ * @{
+ */
+#define ADC_RESOLUTION12b ((uint32_t)0x00000000)
+#define ADC_RESOLUTION10b ((uint32_t)ADC_CR1_RES_0)
+#define ADC_RESOLUTION8b ((uint32_t)ADC_CR1_RES_1)
+#define ADC_RESOLUTION6b ((uint32_t)ADC_CR1_RES)
+
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION12b) || \
+ ((RESOLUTION) == ADC_RESOLUTION10b) || \
+ ((RESOLUTION) == ADC_RESOLUTION8b) || \
+ ((RESOLUTION) == ADC_RESOLUTION6b))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_External_trigger_edge_Regular
+ * @{
+ */
+#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
+#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
+#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
+
+#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_External_trigger_Source_Regular
+ * @{
+ */
+#define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
+#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
+#define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIGCONV_T2_CC3 ((uint32_t)ADC_CR2_EXTSEL_2)
+#define ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
+#define ADC_EXTERNALTRIGCONV_T3_CC1 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIGCONV_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_3)
+#define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIGCONV_T5_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
+#define ADC_EXTERNALTRIGCONV_T5_CC2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIGCONV_T5_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
+#define ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
+#define ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL)
+
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_data_align
+ * @{
+ */
+#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
+#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
+
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
+ ((ALIGN) == ADC_DATAALIGN_LEFT))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_channels
+ * @{
+ */
+#define ADC_CHANNEL_0 ((uint32_t)0x00000000)
+#define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
+#define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2)
+#define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
+#define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3)
+#define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
+#define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
+#define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
+#define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4)
+#define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
+#define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
+
+#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16)
+#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)
+#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
+ ((CHANNEL) == ADC_CHANNEL_1) || \
+ ((CHANNEL) == ADC_CHANNEL_2) || \
+ ((CHANNEL) == ADC_CHANNEL_3) || \
+ ((CHANNEL) == ADC_CHANNEL_4) || \
+ ((CHANNEL) == ADC_CHANNEL_5) || \
+ ((CHANNEL) == ADC_CHANNEL_6) || \
+ ((CHANNEL) == ADC_CHANNEL_7) || \
+ ((CHANNEL) == ADC_CHANNEL_8) || \
+ ((CHANNEL) == ADC_CHANNEL_9) || \
+ ((CHANNEL) == ADC_CHANNEL_10) || \
+ ((CHANNEL) == ADC_CHANNEL_11) || \
+ ((CHANNEL) == ADC_CHANNEL_12) || \
+ ((CHANNEL) == ADC_CHANNEL_13) || \
+ ((CHANNEL) == ADC_CHANNEL_14) || \
+ ((CHANNEL) == ADC_CHANNEL_15) || \
+ ((CHANNEL) == ADC_CHANNEL_16) || \
+ ((CHANNEL) == ADC_CHANNEL_17) || \
+ ((CHANNEL) == ADC_CHANNEL_18))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_sampling_times
+ * @{
+ */
+#define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000)
+#define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
+#define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
+#define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
+#define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2)
+#define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
+#define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
+#define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)
+
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_15CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_28CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_56CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_84CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_112CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_144CYCLES) || \
+ ((TIME) == ADC_SAMPLETIME_480CYCLES))
+/**
+ * @}
+ */
+
+ /** @defgroup ADC_EOCSelection
+ * @{
+ */
+#define EOC_SEQ_CONV ((uint32_t)0x00000000)
+#define EOC_SINGLE_CONV ((uint32_t)0x00000001)
+#define EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002) /*!< reserved for future use */
+
+#define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == EOC_SINGLE_CONV) || \
+ ((EOCSelection) == EOC_SEQ_CONV) || \
+ ((EOCSelection) == EOC_SINGLE_SEQ_CONV))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Event_type
+ * @{
+ */
+#define AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
+#define OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
+
+#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == AWD_EVENT) || \
+ ((EVENT) == OVR_EVENT))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_analog_watchdog_selection
+ * @{
+ */
+#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
+#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
+#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
+#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
+#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
+#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
+#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
+
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_interrupts_definition
+ * @{
+ */
+#define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)
+#define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)
+#define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)
+#define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)
+
+#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
+ ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_flags_definition
+ * @{
+ */
+#define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)
+#define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC)
+#define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC)
+#define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT)
+#define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT)
+#define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_channels_type
+ * @{
+ */
+#define ALL_CHANNELS ((uint32_t)0x00000001)
+#define REGULAR_CHANNELS ((uint32_t)0x00000002) /*!< reserved for future use */
+#define INJECTED_CHANNELS ((uint32_t)0x00000003) /*!< reserved for future use */
+
+#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ALL_CHANNELS) || \
+ ((CHANNEL_TYPE) == REGULAR_CHANNELS) || \
+ ((CHANNEL_TYPE) == INJECTED_CHANNELS))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_thresholds
+ * @{
+ */
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= ((uint32_t)0xFFF))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_length
+ * @{
+ */
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_rank
+ * @{
+ */
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)16)))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_discontinuous_mode_number
+ * @{
+ */
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_range_verification
+ * @{
+ */
+#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
+ ((((RESOLUTION) == ADC_RESOLUTION12b) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
+ (((RESOLUTION) == ADC_RESOLUTION10b) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
+ (((RESOLUTION) == ADC_RESOLUTION8b) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \
+ (((RESOLUTION) == ADC_RESOLUTION6b) && ((ADC_VALUE) <= ((uint32_t)0x003F))))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset ADC handle state
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+
+/**
+ * @brief Enable the ADC peripheral.
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON)
+
+/**
+ * @brief Disable the ADC peripheral.
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)
+
+/**
+ * @brief Set ADC Regular channel sequence length.
+ * @param _NbrOfConversion_: Regular channel sequence length.
+ * @retval None
+ */
+#define __HAL_ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)
+
+/**
+ * @brief Set the ADC's sample time for channel numbers between 10 and 18.
+ * @param _SAMPLETIME_: Sample time parameter.
+ * @param _CHANNELNB_: Channel number.
+ * @retval None
+ */
+#define __HAL_ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10)))
+
+/**
+ * @brief Set the ADC's sample time for channel numbers between 0 and 9.
+ * @param _SAMPLETIME_: Sample time parameter.
+ * @param _CHANNELNB_: Channel number.
+ * @retval None
+ */
+#define __HAL_ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (_CHANNELNB_)))
+
+/**
+ * @brief Set the selected regular channel rank for rank between 1 and 6.
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @retval None
+ */
+#define __HAL_ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 1)))
+
+/**
+ * @brief Set the selected regular channel rank for rank between 7 and 12.
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @retval None
+ */
+#define __HAL_ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 7)))
+
+/**
+ * @brief Set the selected regular channel rank for rank between 13 and 16.
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @retval None
+ */
+#define __HAL_ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 13)))
+
+/**
+ * @brief Enable ADC continuous conversion mode.
+ * @param _CONTINUOUS_MODE_: Continuous mode.
+ * @retval None
+ */
+#define __HAL_ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)
+
+/**
+ * @brief Configures the number of discontinuous conversions for the regular group channels.
+ * @param _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions.
+ * @retval None
+ */
+#define __HAL_ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << 13)
+
+/**
+ * @brief Enable ADC scan mode.
+ * @param _SCANCONV_MODE_: Scan conversion mode.
+ * @retval None
+ */
+#define __HAL_ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)
+
+/**
+ * @brief Enable the ADC end of conversion selection.
+ * @param _EOCSelection_MODE_: End of conversion selection mode.
+ * @retval None
+ */
+#define __HAL_ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)
+
+/**
+ * @brief Enable the ADC DMA continuous request.
+ * @param _DMAContReq_MODE_: DMA continuous request mode.
+ * @retval None
+ */
+#define __HAL_ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)
+
+/**
+ * @brief Enable the ADC end of conversion interrupt.
+ * @param __HANDLE__: specifies the ADC Handle.
+ * @param __INTERRUPT__: ADC Interrupt.
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the ADC end of conversion interrupt.
+ * @param __HANDLE__: specifies the ADC Handle.
+ * @param __INTERRUPT__: ADC interrupt.
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
+
+/** @brief Check if the specified ADC interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the ADC Handle.
+ * @param __INTERRUPT__: specifies the ADC interrupt source to check.
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @brief Clear the ADC's pending flags.
+ * @param __HANDLE__: specifies the ADC Handle.
+ * @param __FLAG__: ADC flag.
+ * @retval None
+ */
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) &= ~(__FLAG__))
+
+/**
+ * @brief Get the selected ADC's flag status.
+ * @param __HANDLE__: specifies the ADC Handle.
+ * @param __FLAG__: ADC flag.
+ * @retval None
+ */
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Return resolution bits in CR1 register.
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
+
+/* Include ADC HAL Extension module */
+#include "stm32f4xx_hal_adc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions ***********************************/
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
+void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
+
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
+
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
+
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
+
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
+
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
+
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
+
+void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
+void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
+void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
+void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
+
+/* Peripheral Control functions *************************************************/
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
+
+/* Peripheral State functions ***************************************************/
+HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_ADC_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_adc_ex.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,328 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_adc.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of ADC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_ADC_EX_H
+#define __STM32F4xx_ADC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ADCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief ADC Configuration injected Channel structure definition
+ */
+typedef struct
+{
+ uint32_t InjectedChannel; /*!< Configure the ADC injected channel.
+ This parameter can be a value of @ref ADC_channels */
+ uint32_t InjectedRank; /*!< The rank in the injected group sequencer
+ This parameter must be a number between Min_Data = 1 and Max_Data = 4. */
+ uint32_t InjectedSamplingTime; /*!< The sample time value to be set for the selected channel.
+ This parameter can be a value of @ref ADC_sampling_times */
+ uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data when convert injected channels.
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+ uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ADC conversions that will be done using the sequencer for
+ injected channel group.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 4. */
+ uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group
+ conversion after regular one */
+ uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous mode or not for injected channels.
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t ExternalTrigInjecConvEdge; /*!< Select the external trigger edge and enable the trigger of an injected channels.
+ This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected */
+ uint32_t ExternalTrigInjecConv; /*!< Select the external event used to trigger the start of conversion of a injected channels.
+ This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected */
+}ADC_InjectionConfTypeDef;
+
+/**
+ * @brief ADC Configuration multi-mode structure definition
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
+ This parameter can be a value of @ref ADCEx_Common_mode */
+ uint32_t DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode.
+ This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */
+ uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
+ This parameter can be a value of @ref ADCEx_delay_between_2_sampling_phases */
+}ADC_MultiModeTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Constants
+ * @{
+ */
+
+
+/** @defgroup ADCEx_Common_mode
+ * @{
+ */
+#define ADC_MODE_INDEPENDENT ((uint32_t)0x00000000)
+#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0)
+#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1)
+#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
+#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
+#define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
+#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
+#define ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0))
+#define ADC_TRIPLEMODE_REGSIMULT_AlterTrig ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1))
+#define ADC_TRIPLEMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
+#define ADC_TRIPLEMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
+#define ADC_TRIPLEMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
+#define ADC_TRIPLEMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
+
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \
+ ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
+ ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
+ ((MODE) == ADC_DUALMODE_INJECSIMULT) || \
+ ((MODE) == ADC_DUALMODE_REGSIMULT) || \
+ ((MODE) == ADC_DUALMODE_INTERL) || \
+ ((MODE) == ADC_DUALMODE_ALTERTRIG) || \
+ ((MODE) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \
+ ((MODE) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig) || \
+ ((MODE) == ADC_TRIPLEMODE_INJECSIMULT) || \
+ ((MODE) == ADC_TRIPLEMODE_REGSIMULT) || \
+ ((MODE) == ADC_TRIPLEMODE_INTERL) || \
+ ((MODE) == ADC_TRIPLEMODE_ALTERTRIG))
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode
+ * @{
+ */
+#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000) /*!< DMA mode disabled */
+#define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0) /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
+#define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1) /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
+#define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA) /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
+
+#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED) || \
+ ((MODE) == ADC_DMAACCESSMODE_1) || \
+ ((MODE) == ADC_DMAACCESSMODE_2) || \
+ ((MODE) == ADC_DMAACCESSMODE_3))
+/**
+ * @}
+ */
+
+ /** @defgroup ADCEx_delay_between_2_sampling_phases
+ * @{
+ */
+#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000)
+#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
+#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
+#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)
+#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
+#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)
+#define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
+#define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
+#define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
+#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
+
+#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES))
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_External_trigger_edge_Injected
+ * @{
+ */
+#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0)
+#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1)
+#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN)
+
+#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE) || \
+ ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING) || \
+ ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \
+ ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING))
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_External_trigger_Source_Injected
+ * @{
+ */
+#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)ADC_CR2_JEXTSEL_0)
+#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)ADC_CR2_JEXTSEL_1)
+#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC2 ((uint32_t)ADC_CR2_JEXTSEL_2)
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJECCONV_T4_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
+#define ADC_EXTERNALTRIGINJECCONV_T4_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ((uint32_t)ADC_CR2_JEXTSEL_3)
+#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJECCONV_T5_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1))
+#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2))
+#define ADC_EXTERNALTRIGINJECCONV_T8_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
+#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ((uint32_t)ADC_CR2_JEXTSEL)
+
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15))
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_injected_channel_selection
+ * @{
+ */
+#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)
+#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)
+#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)
+#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)
+
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_injected_length
+ * @{
+ */
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_injected_rank
+ * @{
+ */
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)4)))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/**
+ * @brief Set the selected injected Channel rank.
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @param _JSQR_JL_: Sequence length.
+ * @retval None
+ */
+#define __HAL_ADC_JSQR(_CHANNELNB_, _RANKNB_,_JSQR_JL_) \
+((_CHANNELNB_) << (5 * (uint8_t)(((_RANKNB_) + 3) - (_JSQR_JL_))))
+
+/* Exported functions --------------------------------------------------------*/
+
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
+uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc);
+uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc);
+void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
+
+/* Peripheral Control functions *************************************************/
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_ADC_EX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_can.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,781 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_can.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of CAN HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CAN_H
+#define __STM32F4xx_HAL_CAN_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CAN
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_CAN_STATE_RESET = 0x00, /*!< CAN not yet initialized or disabled */
+ HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */
+ HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX_RX = 0x32, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */
+
+}HAL_CAN_StateTypeDef;
+
+/**
+ * @brief CAN init structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Specifies the length of a time quantum.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
+
+ uint32_t Mode; /*!< Specifies the CAN operating mode.
+ This parameter can be a value of @ref CAN_operating_mode */
+
+ uint32_t SJW; /*!< Specifies the maximum number of time quanta
+ the CAN hardware is allowed to lengthen or
+ shorten a bit to perform resynchronization.
+ This parameter can be a value of @ref CAN_synchronisation_jump_width */
+
+ uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
+
+ uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+
+ uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
+ This parameter can be set to ENABLE or DISABLE */
+}CAN_InitTypeDef;
+
+/**
+ * @brief CAN filter configuration structure definition
+ */
+typedef struct
+{
+ uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
+ configuration, first one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
+ configuration, second one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
+ according to the mode (MSBs for a 32-bit configuration,
+ first one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
+ according to the mode (LSBs for a 32-bit configuration,
+ second one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+ This parameter can be a value of @ref CAN_filter_FIFO */
+
+ uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 27 */
+
+ uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
+ This parameter can be a value of @ref CAN_filter_mode */
+
+ uint32_t FilterScale; /*!< Specifies the filter scale.
+ This parameter can be a value of @ref CAN_filter_scale */
+
+ uint32_t FilterActivation; /*!< Enable or disable the filter.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t BankNumber; /*!< Select the start slave bank filter.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 28 */
+
+}CAN_FilterConfTypeDef;
+
+/**
+ * @brief CAN Tx message structure definition
+ */
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
+
+ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_identifier_type */
+
+ uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_remote_transmission_request */
+
+ uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
+
+ uint32_t Data[8]; /*!< Contains the data to be transmitted.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+
+}CanTxMsgTypeDef;
+
+/**
+ * @brief CAN Rx message structure definition
+ */
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
+
+ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
+ This parameter can be a value of @ref CAN_identifier_type */
+
+ uint32_t RTR; /*!< Specifies the type of frame for the received message.
+ This parameter can be a value of @ref CAN_remote_transmission_request */
+
+ uint32_t DLC; /*!< Specifies the length of the frame that will be received.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
+
+ uint32_t Data[8]; /*!< Contains the data to be received.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+
+ uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+
+ uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
+ This parameter can be CAN_FIFO0 or CAN_FIFO1 */
+
+}CanRxMsgTypeDef;
+
+/**
+ * @brief CAN handle Structure definition
+ */
+typedef struct
+{
+ CAN_TypeDef *Instance; /*!< Register base address */
+
+ CAN_InitTypeDef Init; /*!< CAN required parameters */
+
+ CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
+
+ CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */
+
+ __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
+
+ HAL_LockTypeDef Lock; /*!< CAN locking object */
+
+ __IO uint32_t ErrorCode; /*!< CAN Error code */
+
+}CAN_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CAN_Exported_Constants
+ * @{
+ */
+
+/** @defgroup HAL CAN Error Code
+ * @{
+ */
+#define HAL_CAN_ERROR_NONE 0x00 /*!< No error */
+#define HAL_CAN_ERROR_EWG 0x01 /*!< EWG error */
+#define HAL_CAN_ERROR_EPV 0x02 /*!< EPV error */
+#define HAL_CAN_ERROR_BOF 0x04 /*!< BOF error */
+#define HAL_CAN_ERROR_STF 0x08 /*!< Stuff error */
+#define HAL_CAN_ERROR_FOR 0x10 /*!< Form error */
+#define HAL_CAN_ERROR_ACK 0x20 /*!< Acknowledgment error */
+#define HAL_CAN_ERROR_BR 0x40 /*!< Bit recessive */
+#define HAL_CAN_ERROR_BD 0x80 /*!< LEC dominant */
+#define HAL_CAN_ERROR_CRC 0x100 /*!< LEC transfer error */
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_InitStatus
+ * @{
+ */
+#define CAN_INITSTATUS_FAILED ((uint8_t)0x00) /*!< CAN initialization failed */
+#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01) /*!< CAN initialization OK */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_operating_mode
+ * @{
+ */
+#define CAN_MODE_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
+#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
+#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
+#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
+
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
+ ((MODE) == CAN_MODE_LOOPBACK)|| \
+ ((MODE) == CAN_MODE_SILENT) || \
+ ((MODE) == CAN_MODE_SILENT_LOOPBACK))
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_synchronisation_jump_width
+ * @{
+ */
+#define CAN_SJW_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
+#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
+#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
+#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
+
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
+ ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_1
+ * @{
+ */
+#define CAN_BS1_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
+#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
+#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
+#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
+#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
+#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
+#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
+#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
+#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
+#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
+#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
+#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
+#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
+#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
+#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
+#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
+
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2
+ * @{
+ */
+#define CAN_BS2_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
+#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
+#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
+#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
+#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
+#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
+#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
+#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
+
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
+/**
+ * @}
+ */
+
+/** @defgroup CAN_clock_prescaler
+ * @{
+ */
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_number
+ * @{
+ */
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_mode
+ * @{
+ */
+#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
+#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
+
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
+ ((MODE) == CAN_FILTERMODE_IDLIST))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_scale
+ * @{
+ */
+#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
+#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
+
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
+ ((SCALE) == CAN_FILTERSCALE_32BIT))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_FIFO
+ * @{
+ */
+#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
+
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
+ ((FIFO) == CAN_FILTER_FIFO1))
+
+/* Legacy defines */
+#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
+#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Start_bank_filter_for_slave_CAN
+ * @{
+ */
+#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Tx
+ * @{
+ */
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_identifier_type
+ * @{
+ */
+#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */
+#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
+ ((IDTYPE) == CAN_ID_EXT))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_remote_transmission_request
+ * @{
+ */
+#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */
+#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_transmit_constants
+ * @{
+ */
+#define CAN_TXSTATUS_FAILED ((uint8_t)0x00) /*!< CAN transmission failed */
+#define CAN_TXSTATUS_OK ((uint8_t)0x01) /*!< CAN transmission succeeded */
+#define CAN_TXSTATUS_PENDING ((uint8_t)0x02) /*!< CAN transmission pending */
+#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_receive_FIFO_number_constants
+ * @{
+ */
+#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
+#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
+
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_flags
+ * @{
+ */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
+ and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with
+ CAN_GetFlagStatus() function. */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500) /*!< Request MailBox0 flag */
+#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508) /*!< Request MailBox1 flag */
+#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510) /*!< Request MailBox2 flag */
+#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501) /*!< Transmission OK MailBox0 flag */
+#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509) /*!< Transmission OK MailBox1 flag */
+#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511) /*!< Transmission OK MailBox2 flag */
+#define CAN_FLAG_TME0 ((uint32_t)0x0000051A) /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME1 ((uint32_t)0x0000051B) /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME2 ((uint32_t)0x0000051C) /*!< Transmit mailbox 0 empty flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FF0 ((uint32_t)0x00000203) /*!< FIFO 0 Full flag */
+#define CAN_FLAG_FOV0 ((uint32_t)0x00000204) /*!< FIFO 0 Overrun flag */
+
+#define CAN_FLAG_FF1 ((uint32_t)0x00000403) /*!< FIFO 1 Full flag */
+#define CAN_FLAG_FOV1 ((uint32_t)0x00000404) /*!< FIFO 1 Overrun flag */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WKU ((uint32_t)0x00000103) /*!< Wake up flag */
+#define CAN_FLAG_SLAK ((uint32_t)0x00000101) /*!< Sleep acknowledge flag */
+#define CAN_FLAG_SLAKI ((uint32_t)0x00000104) /*!< Sleep acknowledge flag */
+/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
+ In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_EWG ((uint32_t)0x00000300) /*!< Error warning flag */
+#define CAN_FLAG_EPV ((uint32_t)0x00000301) /*!< Error passive flag */
+#define CAN_FLAG_BOF ((uint32_t)0x00000302) /*!< Bus-Off flag */
+
+#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_RQCP2) || ((FLAG) == CAN_FLAG_BOF) || \
+ ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
+ ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
+ ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_SLAK) || \
+ ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
+ ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0))
+
+
+#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_SLAK) || ((FLAG) == CAN_FLAG_RQCP2) || \
+ ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
+ ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) || \
+ ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
+ ((FLAG) == CAN_FLAG_WKU))
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_interrupts
+ * @{
+ */
+#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
+
+/* Receive Interrupts */
+#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
+#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
+#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
+#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
+#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
+#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
+#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
+
+/* Error Interrupts */
+#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
+#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
+#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
+#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
+#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
+
+/* Flags named as Interrupts : kept only for FW compatibility */
+#define CAN_IT_RQCP0 CAN_IT_TME
+#define CAN_IT_RQCP1 CAN_IT_TME
+#define CAN_IT_RQCP2 CAN_IT_TME
+
+#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
+ ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
+ ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
+ ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
+ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+
+#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
+ ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
+ ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
+ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+/**
+ * @}
+ */
+
+/* Time out for INAK bit */
+#define INAK_TIMEOUT ((uint32_t)0x0000FFFF)
+/* Time out for SLAK bit */
+#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF)
+
+/* Mailboxes definition */
+#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
+#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
+#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset CAN handle state
+ * @param __HANDLE__: specifies the CAN Handle.
+ * @retval None
+ */
+#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
+
+/**
+ * @brief Enable the specified CAN interrupts.
+ * @param __HANDLE__: CAN handle
+ * @param __INTERRUPT__: CAN Interrupt
+ * @retval None
+ */
+#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified CAN interrupts.
+ * @param __HANDLE__: CAN handle
+ * @param __INTERRUPT__: CAN Interrupt
+ * @retval None
+ */
+#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/**
+ * @brief Return the number of pending received messages.
+ * @param __HANDLE__: CAN handle
+ * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @retval The number of pending message.
+ */
+#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
+((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03)))
+
+/** @brief Check whether the specified CAN flag is set or not.
+ * @param __HANDLE__: CAN Handle
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
+ * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
+ * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
+ * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
+ * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
+ * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
+ * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
+ * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
+ * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
+ * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
+ * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
+ * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
+ * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
+ * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
+ * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
+ * @arg CAN_FLAG_WKU: Wake up Flag
+ * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
+ * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
+ * @arg CAN_FLAG_EWG: Error Warning Flag
+ * @arg CAN_FLAG_EPV: Error Passive Flag
+ * @arg CAN_FLAG_BOF: Bus-Off Flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define CAN_FLAG_MASK ((uint32_t)0x000000FF)
+#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
+((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ ((((__HANDLE__)->Instance->ESR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))))
+
+/** @brief Clear the specified CAN pending flag.
+ * @param __HANDLE__: CAN Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
+ * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
+ * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
+ * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
+ * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
+ * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
+ * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
+ * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
+ * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
+ * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
+ * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
+ * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
+ * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
+ * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
+ * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
+ * @arg CAN_FLAG_WKU: Wake up Flag
+ * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
+ * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
+ * @arg CAN_FLAG_EWG: Error Warning Flag
+ * @arg CAN_FLAG_EPV: Error Passive Flag
+ * @arg CAN_FLAG_BOF: Bus-Off Flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+((((__FLAG__) >> 8) == 5)? (((__HANDLE__)->Instance->TSR) &= ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 2)? (((__HANDLE__)->Instance->RF0R) &= ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 4)? (((__HANDLE__)->Instance->RF1R) &= ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 1)? (((__HANDLE__)->Instance->MSR) &= ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__HANDLE__)->Instance->ESR) &= ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))))
+
+/** @brief Check if the specified CAN interrupt source is enabled or disabled.
+ * @param __HANDLE__: CAN Handle
+ * @param __INTERRUPT__: specifies the CAN interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
+ * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev
+ * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @brief Check the transmission status of a CAN Frame.
+ * @param __HANDLE__: CAN Handle
+ * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
+ * @retval The new status of transmission (TRUE or FALSE).
+ */
+#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
+ ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
+
+
+
+/**
+ * @brief Release the specified receive FIFO.
+ * @param __HANDLE__: CAN handle
+ * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @retval None
+ */
+#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
+((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
+
+/**
+ * @brief Cancel a transmit request.
+ * @param __HANDLE__: CAN Handle
+ * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
+ * @retval None
+ */
+#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
+ ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
+
+/**
+ * @brief Enable or disable the DBG Freeze for CAN.
+ * @param __HANDLE__: CAN Handle
+ * @param __NEWSTATE__: new state of the CAN peripheral.
+ * This parameter can be: ENABLE (CAN reception/transmission is frozen
+ * during debug. Reception FIFOs can still be accessed/controlled normally)
+ * or DISABLE (CAN is working during debug).
+ * @retval None
+ */
+#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
+((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions ***********************************/
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
+void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
+void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
+
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
+
+/* Peripheral State functions ***************************************************/
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
+
+void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
+void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
+void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_CAN_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_conf.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,400 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_conf_template.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief HAL configuration template file.
+ * This file should be copied to the application folder and renamed
+ * to stm32f4xx_hal_conf.h.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DCMI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_DMA2D_MODULE_ENABLED
+#define HAL_ETH_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_PCCARD_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+#define HAL_SDRAM_MODULE_ENABLED
+#define HAL_HASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_LTDC_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+//#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SAI_MODULE_ENABLED
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ * This value is used by the UART, RTC HAL module to compute the system frequency
+ */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+ * @brief External clock source for I2S peripheral
+ * This value is used by the I2S HAL module to compute the I2S clock source
+ * frequency, this source is inserted directly through I2S_CKIN pad.
+ */
+#if !defined (EXTERNAL_CLOCK_VALUE)
+ #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the external oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
+#define USE_RTOS 0
+#define PREFETCH_ENABLE 1
+#define INSTRUCTION_CACHE_ENABLE 1
+#define DATA_CACHE_ENABLE 1
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1 */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0 2
+#define MAC_ADDR1 0
+#define MAC_ADDR2 0
+#define MAC_ADDR3 0
+#define MAC_ADDR4 0
+#define MAC_ADDR5 0
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
+#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
+#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
+#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS 0x01
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
+
+#define PHY_READ_TO ((uint32_t)0x0000FFFF)
+#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
+#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
+
+#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
+#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
+#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
+#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
+#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
+#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
+#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
+
+#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
+#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
+#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
+
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
+#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
+#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
+
+#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
+#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
+#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
+
+#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
+#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
+
+#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
+#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+ #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+ #include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+ #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+ #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_cortex.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,163 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_cortex.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of CORTEX HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CORTEX_H
+#define __STM32F4xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CORTEX
+ * @{
+ */
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants
+ * @{
+ */
+
+
+/** @defgroup CORTEX_Preemption_Priority_Group
+ * @{
+ */
+
+#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
+ 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
+ 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
+ 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
+ 1 bits for subpriority */
+#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
+ 0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_1) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_2) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_3) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_SysTick_clock_source
+ * @{
+ */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
+#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+/**
+ * @}
+ */
+
+/* Exported Macros -----------------------------------------------------------*/
+
+/** @brief Configures the SysTick clock source.
+ * @param __CLKSRC__: specifies the SysTick clock source.
+ * This parameter can be one of the following values:
+ * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+ * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+ * @retval None
+ */
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG(__CLKSRC__) \
+ do { \
+ if ((__CLKSRC__) == SYSTICK_CLKSOURCE_HCLK) \
+ { \
+ SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; \
+ } \
+ else \
+ SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; \
+ } while(0)
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/* Initialization and de-initialization functions *******************************/
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+
+/* Peripheral Control functions *************************************************/
+uint32_t HAL_NVIC_GetPriorityGrouping(void);
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void HAL_SYSTICK_IRQHandler(void);
+void HAL_SYSTICK_Callback(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CORTEX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_crc.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,130 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_crc.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of CRC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CRC_H
+#define __STM32F4xx_HAL_CRC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CRC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief CRC HAL State Structure definition
+ */
+typedef enum
+{
+ HAL_CRC_STATE_RESET = 0x00, /*!< CRC not yet initialized or disabled */
+ HAL_CRC_STATE_READY = 0x01, /*!< CRC initialized and ready for use */
+ HAL_CRC_STATE_BUSY = 0x02, /*!< CRC internal process is ongoing */
+ HAL_CRC_STATE_TIMEOUT = 0x03, /*!< CRC timeout state */
+ HAL_CRC_STATE_ERROR = 0x04 /*!< CRC error state */
+
+}HAL_CRC_StateTypeDef;
+
+/**
+ * @brief CRC handle Structure definition
+ */
+typedef struct
+{
+ CRC_TypeDef *Instance; /*!< Register base address */
+
+ HAL_LockTypeDef Lock; /*!< CRC locking object */
+
+ __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
+
+}CRC_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset CRC handle state
+ * @param __HANDLE__: CRC handle
+ * @retval None
+ */
+#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
+
+/**
+ * @brief Resets CRC Data Register.
+ * @param __HANDLE__: CRC handle
+ * @retval None
+ */
+#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
+HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
+
+/* Peripheral Control functions ************************************************/
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+
+/* Peripheral State functions **************************************************/
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CRC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_cryp.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,403 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_cryp.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of CRYP HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CRYP_H
+#define __STM32F4xx_HAL_CRYP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CRYP
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief CRYP Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
+ This parameter can be a value of @ref CRYP_Data_Type */
+
+ uint32_t KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit key length.
+ This parameter can be a value of @ref CRYP_Key_Size */
+
+ uint8_t* pKey; /*!< The key used for encryption/decryption */
+
+ uint8_t* pInitVect; /*!< The initialization vector used also as initialization
+ counter in CTR mode */
+
+ uint8_t IVSize; /*!< The size of initialization vector.
+ This parameter (called nonce size in CCM) is used only
+ in AES-128/192/256 encryption/decryption CCM mode */
+
+ uint8_t TagSize; /*!< The size of returned authentication TAG.
+ This parameter is used only in AES-128/192/256
+ encryption/decryption CCM mode */
+
+ uint8_t* Header; /*!< The header used in GCM and CCM modes */
+
+ uint16_t HeaderSize; /*!< The size of header buffer in bytes */
+
+ uint8_t* pScratch; /*!< Scratch buffer used to append the header. It's size must be equal to header size + 21 bytes.
+ This parameter is used only in AES-128/192/256 encryption/decryption CCM mode */
+}CRYP_InitTypeDef;
+
+/**
+ * @brief HAL CRYP State structures definition
+ */
+typedef enum
+{
+ HAL_CRYP_STATE_RESET = 0x00, /*!< CRYP not yet initialized or disabled */
+ HAL_CRYP_STATE_READY = 0x01, /*!< CRYP initialized and ready for use */
+ HAL_CRYP_STATE_BUSY = 0x02, /*!< CRYP internal processing is ongoing */
+ HAL_CRYP_STATE_TIMEOUT = 0x03, /*!< CRYP timeout state */
+ HAL_CRYP_STATE_ERROR = 0x04 /*!< CRYP error state */
+}HAL_CRYP_STATETypeDef;
+
+/**
+ * @brief HAL CRYP phase structures definition
+ */
+typedef enum
+{
+ HAL_CRYP_PHASE_READY = 0x01, /*!< CRYP peripheral is ready for initialization. */
+ HAL_CRYP_PHASE_PROCESS = 0x02, /*!< CRYP peripheral is in processing phase */
+ HAL_CRYP_PHASE_FINAL = 0x03 /*!< CRYP peripheral is in final phase
+ This is relevant only with CCM and GCM modes */
+}HAL_PhaseTypeDef;
+
+/**
+ * @brief CRYP handle Structure definition
+ */
+typedef struct
+{
+ CRYP_InitTypeDef Init; /*!< CRYP required parameters */
+
+ uint8_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+
+ uint8_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+
+ __IO uint16_t CrypInCount; /*!< Counter of inputed data */
+
+ __IO uint16_t CrypOutCount; /*!< Counter of outputed data */
+
+ HAL_StatusTypeDef Status; /*!< CRYP peripheral status */
+
+ HAL_PhaseTypeDef Phase; /*!< CRYP peripheral phase */
+
+ DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< CRYP locking object */
+
+ __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
+}CRYP_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CRYP_Exported_Constants
+ * @{
+ */
+
+/** @defgroup CRYP_Key_Size
+ * @{
+ */
+#define CRYP_KEYSIZE_128B ((uint32_t)0x00000000)
+#define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0
+#define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1
+
+#define IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KEYSIZE_128B) || \
+ ((KEYSIZE) == CRYP_KEYSIZE_192B) || \
+ ((KEYSIZE) == CRYP_KEYSIZE_256B))
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Data_Type
+ * @{
+ */
+#define CRYP_DATATYPE_32B ((uint32_t)0x00000000)
+#define CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0
+#define CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1
+#define CRYP_DATATYPE_1B CRYP_CR_DATATYPE
+
+#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DATATYPE_32B) || \
+ ((DATATYPE) == CRYP_DATATYPE_16B) || \
+ ((DATATYPE) == CRYP_DATATYPE_8B) || \
+ ((DATATYPE) == CRYP_DATATYPE_1B))
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_AlgoModeDirection
+ * @{
+ */
+#define CRYP_CR_ALGOMODE_DIRECTION ((uint32_t)0x0008003C)
+#define CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT ((uint32_t)0x00000000)
+#define CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT ((uint32_t)0x00000004)
+#define CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT ((uint32_t)0x00000008)
+#define CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT ((uint32_t)0x0000000C)
+#define CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT ((uint32_t)0x00000010)
+#define CRYP_CR_ALGOMODE_DES_ECB_DECRYPT ((uint32_t)0x00000014)
+#define CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT ((uint32_t)0x00000018)
+#define CRYP_CR_ALGOMODE_DES_CBC_DECRYPT ((uint32_t)0x0000001C)
+#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT ((uint32_t)0x00000020)
+#define CRYP_CR_ALGOMODE_AES_ECB_DECRYPT ((uint32_t)0x00000024)
+#define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT ((uint32_t)0x00000028)
+#define CRYP_CR_ALGOMODE_AES_CBC_DECRYPT ((uint32_t)0x0000002C)
+#define CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT ((uint32_t)0x00000030)
+#define CRYP_CR_ALGOMODE_AES_CTR_DECRYPT ((uint32_t)0x00000034)
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Interrupt
+ * @{
+ */
+#define CRYP_IT_INI ((uint32_t)CRYP_IMSCR_INIM) /*!< Input FIFO Interrupt */
+#define CRYP_IT_OUTI ((uint32_t)CRYP_IMSCR_OUTIM) /*!< Output FIFO Interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup CRYP_Flags
+ * @{
+ */
+
+#define CRYP_FLAG_BUSY ((uint32_t)0x00000010) /*!< The CRYP core is currently
+ processing a block of data
+ or a key preparation (for
+ AES decryption). */
+#define CRYP_FLAG_IFEM ((uint32_t)0x00000001) /*!< Input FIFO is empty */
+#define CRYP_FLAG_IFNF ((uint32_t)0x00000002) /*!< Input FIFO is not Full */
+#define CRYP_FLAG_OFNE ((uint32_t)0x00000004) /*!< Output FIFO is not empty */
+#define CRYP_FLAG_OFFU ((uint32_t)0x00000008) /*!< Output FIFO is Full */
+#define CRYP_FLAG_OUTRIS ((uint32_t)0x01000002) /*!< Output FIFO service raw
+ interrupt status */
+#define CRYP_FLAG_INRIS ((uint32_t)0x01000001) /*!< Input FIFO service raw
+ interrupt status */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset CRYP handle state
+ * @param __HANDLE__: specifies the CRYP handle.
+ * @retval None
+ */
+#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
+
+/**
+ * @brief Enable/Disable the CRYP peripheral.
+ * @param None
+ * @retval None
+ */
+#define __HAL_CRYP_ENABLE() (CRYP->CR |= CRYP_CR_CRYPEN)
+#define __HAL_CRYP_DISABLE() (CRYP->CR &= ~CRYP_CR_CRYPEN)
+
+/**
+ * @brief Flush the data FIFO.
+ * @param None
+ * @retval None
+ */
+#define __HAL_CRYP_FIFO_FLUSH() (CRYP->CR |= CRYP_CR_FFLUSH)
+
+/**
+ * @brief Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC,
+ * @param MODE: The algorithm mode.
+ * @retval None
+ */
+#define __HAL_CRYP_SET_MODE(MODE) CRYP->CR |= (uint32_t)(MODE)
+
+/** @brief Check whether the specified CRYP flag is set or not.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
+ * or a key preparation (for AES decryption).
+ * @arg CRYP_FLAG_IFEM: Input FIFO is empty
+ * @arg CRYP_FLAG_IFNF: Input FIFO is not full
+ * @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
+ * @arg CRYP_FLAG_OFNE: Output FIFO is not empty
+ * @arg CRYP_FLAG_OFFU: Output FIFO is full
+ * @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define CRYP_FLAG_MASK ((uint32_t)0x0000001F)
+#define __HAL_CRYP_GET_FLAG(__FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01)?(((CRYP->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
+ (((CRYP->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
+
+/** @brief Check whether the specified CRYP interrupt is set or not.
+ * @param __INTERRUPT__: specifies the interrupt to check.
+ * This parameter can be one of the following values:
+ * @arg CRYP_IT_INRIS: Input FIFO service raw interrupt is pending
+ * @arg CRYP_IT_OUTRIS: Output FIFO service raw interrupt is pending
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_CRYP_GET_IT(__INTERRUPT__) ((CRYP->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @brief Enable the CRYP interrupt.
+ * @param __INTERRUPT__: CRYP Interrupt.
+ * @retval None
+ */
+#define __HAL_CRYP_ENABLE_IT(__INTERRUPT__) ((CRYP->IMSCR) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the CRYP interrupt.
+ * @param __INTERRUPT__: CRYP interrupt.
+ * @retval None
+ */
+#define __HAL_CRYP_DISABLE_IT(__INTERRUPT__) ((CRYP->IMSCR) &= ~(__INTERRUPT__))
+
+/* Include CRYP HAL Extension module */
+#include "stm32f4xx_hal_cryp_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
+
+/* AES encryption/decryption using polling ***********************************/
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+
+/* AES encryption/decryption using interrupt *********************************/
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* AES encryption/decryption using DMA ***************************************/
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* DES encryption/decryption using polling ***********************************/
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+
+/* DES encryption/decryption using interrupt *********************************/
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* DES encryption/decryption using DMA ***************************************/
+HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* TDES encryption/decryption using polling **********************************/
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+
+/* TDES encryption/decryption using interrupt ********************************/
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* TDES encryption/decryption using DMA **************************************/
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* Processing functions ******************************************************/
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
+
+/* Peripheral State functions ************************************************/
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
+
+/* MSP functions *************************************************************/
+void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
+
+/* CallBack functions ********************************************************/
+void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
+
+#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CRYP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_cryp_ex.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,146 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_cryp_ex.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of CRYP HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CRYP_EX_H
+#define __STM32F4xx_HAL_CRYP_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F437xx) || defined(STM32F439xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CRYPEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CRYPEx_Exported_Constants
+ * @{
+ */
+
+/** @defgroup CRYPEx_AlgoModeDirection
+ * @{
+ */
+#define CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT ((uint32_t)0x00080000)
+#define CRYP_CR_ALGOMODE_AES_GCM_DECRYPT ((uint32_t)0x00080004)
+#define CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT ((uint32_t)0x00080008)
+#define CRYP_CR_ALGOMODE_AES_CCM_DECRYPT ((uint32_t)0x0008000C)
+/**
+ * @}
+ */
+
+/** @defgroup CRYPEx_PhaseConfig
+ * The phases are relevant only to AES-GCM and AES-CCM
+ * @{
+ */
+#define CRYP_PHASE_INIT ((uint32_t)0x00000000)
+#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0
+#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1
+#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/**
+ * @brief Set the phase: Init, header, payload, final.
+ * This is relevant only for GCM and CCM modes.
+ * @param PHASE: The phase.
+ * @retval None
+ */
+#define __HAL_CRYP_SET_PHASE(PHASE) do{CRYP->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
+ CRYP->CR |= (uint32_t)(PHASE);\
+ }while(0)
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/* AES encryption/decryption using polling ***********************************/
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint16_t Size, uint8_t *AuthTag, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout);
+
+/* AES encryption/decryption using interrupt *********************************/
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* AES encryption/decryption using DMA ***************************************/
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+
+/* Processing functions ********************************************************/
+void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp);
+
+#endif /* STM32F437xx || STM32F439xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CRYP_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_dac.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,331 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dac.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of DAC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DAC_H
+#define __STM32F4xx_HAL_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */
+ HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */
+ HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */
+ HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */
+ HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */
+}HAL_DAC_StateTypeDef;
+
+/**
+ * @brief DAC handle Structure definition
+ */
+typedef struct
+{
+ DAC_TypeDef *Instance; /*!< Register base address */
+
+ __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
+
+ HAL_LockTypeDef Lock; /*!< DAC locking object */
+
+ DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
+
+ DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
+
+ __IO uint32_t ErrorCode; /*!< DAC Error code */
+
+}DAC_HandleTypeDef;
+
+/**
+ * @brief DAC Configuration regular Channel structure definition
+ */
+typedef struct
+{
+ uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
+ This parameter can be a value of @ref DAC_trigger_selection */
+
+ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+ This parameter can be a value of @ref DAC_output_buffer */
+}DAC_ChannelConfTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DAC_Error_Code
+ * @{
+ */
+#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */
+#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DAM underrun error */
+#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DAM underrun error */
+#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_trigger_selection
+ * @{
+ */
+
+#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+ has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
+
+#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_output_buffer
+ * @{
+ */
+#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)
+#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
+
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
+ ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Channel_selection
+ * @{
+ */
+#define DAC_CHANNEL_1 ((uint32_t)0x00000000)
+#define DAC_CHANNEL_2 ((uint32_t)0x00000010)
+
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
+ ((CHANNEL) == DAC_CHANNEL_2))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_data_alignement
+ * @{
+ */
+#define DAC_ALIGN_12B_R ((uint32_t)0x00000000)
+#define DAC_ALIGN_12B_L ((uint32_t)0x00000004)
+#define DAC_ALIGN_8B_R ((uint32_t)0x00000008)
+
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
+ ((ALIGN) == DAC_ALIGN_12B_L) || \
+ ((ALIGN) == DAC_ALIGN_8B_R))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_data
+ * @{
+ */
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+/**
+ * @}
+ */
+
+/** @defgroup DAC_flags_definition
+ * @{
+ */
+#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
+#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
+
+#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR1) || \
+ ((FLAG) == DAC_FLAG_DMAUDR2))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_IT_definition
+ * @{
+ */
+#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
+#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
+
+#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR1) || \
+ ((IT) == DAC_IT_DMAUDR2))
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset DAC handle state
+ * @param __HANDLE__: specifies the DAC handle.
+ * @retval None
+ */
+#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
+
+/** @brief Enable the DAC channel
+ * @param __HANDLE__: specifies the DAC handle.
+ * @param __DAC_Channel__: specifies the DAC channel
+ * @retval None
+ */
+#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
+((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
+
+/** @brief Disable the DAC channel
+ * @param __HANDLE__: specifies the DAC handle
+ * @param __DAC_Channel__: specifies the DAC channel.
+ * @retval None
+ */
+#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
+((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
+
+/** @brief Set DHR12R1 alignment
+ * @param __ALIGNEMENT__: specifies the DAC alignement
+ * @retval None
+ */
+#define __HAL_DHR12R1_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000008) + (__ALIGNEMENT__))
+
+/** @brief Set DHR12R2 alignment
+ * @param __ALIGNEMENT__: specifies the DAC alignement
+ * @retval None
+ */
+#define __HAL_DHR12R2_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000014) + (__ALIGNEMENT__))
+
+/** @brief Set DHR12RD alignment
+ * @param __ALIGNEMENT__: specifies the DAC alignement
+ * @retval None
+ */
+#define __HAL_DHR12RD_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000020) + (__ALIGNEMENT__))
+
+/** @brief Enable the DAC interrupt
+ * @param __HANDLE__: specifies the DAC handle
+ * @param __INTERRUPT__: specifies the DAC interrupt.
+ * @retval None
+ */
+#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
+
+/** @brief Disable the DAC interrupt
+ * @param __HANDLE__: specifies the DAC handle
+ * @param __INTERRUPT__: specifies the DAC interrupt.
+ * @retval None
+ */
+#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
+
+/** @brief Get the selected DAC's flag status.
+ * @param __HANDLE__: specifies the DAC handle.
+ * @retval None
+ */
+#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the DAC's flag.
+ * @param __HANDLE__: specifies the DAC handle.
+ * @retval None
+ */
+#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) |= (__FLAG__))
+
+/* Include DAC HAL Extension module */
+#include "stm32f4xx_hal_dac_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions *********************************/
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
+void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
+void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
+
+/* I/O operation functions ****************************************************/
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
+
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
+
+/* Peripheral State functions *************************************************/
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
+
+void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
+void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_HAL_DAC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_dac_ex.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,183 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dac.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of DAC HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DAC_EX_H
+#define __STM32F4xx_HAL_DAC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DACEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HAL State structures definition
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DACEx_wave_generation
+ * @{
+ */
+#define DAC_WAVEGENERATION_NONE ((uint32_t)0x00000000)
+#define DAC_WAVEGENERATION_NOISE ((uint32_t)DAC_CR_WAVE1_0)
+#define DAC_WAVEGENERATION_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
+
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WAVEGENERATION_NONE) || \
+ ((WAVE) == DAC_WAVEGENERATION_NOISE) || \
+ ((WAVE) == DAC_WAVEGENERATION_TRIANGLE))
+/**
+ * @}
+ */
+
+/** @defgroup DACEx_lfsrunmask_triangleamplitude
+ * @{
+ */
+#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
+#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
+#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
+#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
+#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
+#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
+#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
+#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
+#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
+/**
+ * @}
+ */
+
+/** @defgroup DACEx_wave_generation
+ * @{
+ */
+#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
+#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NOISE) || \
+ ((WAVE) == DAC_WAVE_TRIANGLE))
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Extension features functions ***********************************************/
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
+
+void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
+
+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_HAL_DAC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_dcmi.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,498 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dcmi.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of DCMI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DCMI_H
+#define __STM32F4xx_HAL_DCMI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DCMI
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief DCMI Error source
+ */
+typedef enum
+{
+ DCMI_ERROR_SYNC = 1, /*!< Synchronisation error */
+ DCMI_OVERRUN = 2, /*!< DCMI Overrun */
+}DCMI_ErrorTypeDef;
+
+/**
+ * @brief DCMI Embedded Synchronisation CODE Init structure definition
+ */
+typedef struct
+{
+ uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
+ uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */
+ uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */
+ uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
+}DCMI_CodesInitTypeDef;
+
+/**
+ * @brief DCMI Init structure definition
+ */
+typedef struct
+{
+ uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.
+ This parameter can be a value of @ref DCMI_Synchronization_Mode */
+
+ uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising.
+ This parameter can be a value of @ref DCMI_PIXCK_Polarity */
+
+ uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low.
+ This parameter can be a value of @ref DCMI_VSYNC_Polarity */
+
+ uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low.
+ This parameter can be a value of @ref DCMI_HSYNC_Polarity */
+
+ uint32_t CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
+ This parameter can be a value of @ref DCMI_Capture_Rate */
+
+ uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
+ This parameter can be a value of @ref DCMI_Extended_Data_Mode */
+
+ DCMI_CodesInitTypeDef SyncroCode; /*!< Specifies the code of the frame start delimiter. */
+
+ uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode.
+ This parameter can be a value of @ref DCMI_MODE_JPEG */
+
+}DCMI_InitTypeDef;
+
+/**
+ * @brief HAL DCMI State structures definition
+ */
+typedef enum
+{
+ HAL_DCMI_STATE_RESET = 0x00, /*!< DCMI not yet initialized or disabled */
+ HAL_DCMI_STATE_READY = 0x01, /*!< DCMI initialized and ready for use */
+ HAL_DCMI_STATE_BUSY = 0x02, /*!< DCMI internal processing is ongoing */
+ HAL_DCMI_STATE_TIMEOUT = 0x03, /*!< DCMI timeout state */
+ HAL_DCMI_STATE_ERROR = 0x04 /*!< DCMI error state */
+}HAL_DCMI_StateTypeDef;
+
+/**
+ * @brief DCMI handle Structure definition
+ */
+typedef struct
+{
+ DCMI_TypeDef *Instance; /*!< DCMI Register base address */
+
+ DCMI_InitTypeDef Init; /*!< DCMI parameters */
+
+ HAL_LockTypeDef Lock; /*!< DCMI locking object */
+
+ __IO HAL_DCMI_StateTypeDef State; /*!< DCMI state */
+
+ __IO uint32_t XferCount; /*!< DMA transfer counter */
+
+ __IO uint32_t XferSize; /*!< DMA transfer size */
+
+ uint32_t XferTransferNumber; /*!< DMA transfer number */
+
+ uint32_t pBuffPtr; /*!< Pointer to DMA output buffer */
+
+ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer to the DMA handler */
+
+ __IO uint32_t ErrorCode; /*!< DCMI Error code */
+
+}DCMI_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DCMI_Exported_Constants
+ * @{
+ */
+
+/** @defgroup DCMI_Error_Code
+ * @{
+ */
+#define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_DCMI_ERROR_OVF ((uint32_t)0x00000001) /*!< Overflow error */
+#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002) /*!< Synchronization error */
+#define HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Capture_Mode
+ * @{
+ */
+#define DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000) /*!< The received data are transferred continuously
+ into the destination memory through the DMA */
+#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of
+ frame and then transfers a single frame through the DMA */
+
+#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \
+ ((MODE) == DCMI_MODE_SNAPSHOT))
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Synchronization_Mode
+ * @{
+ */
+#define DCMI_SYNCHRO_HARDWARE ((uint32_t)0x00000000) /*!< Hardware synchronization data capture (frame/line start/stop)
+ is synchronized with the HSYNC/VSYNC signals */
+#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with
+ synchronization codes embedded in the data flow */
+
+#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
+ ((MODE) == DCMI_SYNCHRO_EMBEDDED))
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_PIXCK_Polarity
+ * @{
+ */
+#define DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000) /*!< Pixel clock active on Falling edge */
+#define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */
+
+#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
+ ((POLARITY) == DCMI_PCKPOLARITY_RISING))
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_VSYNC_Polarity
+ * @{
+ */
+#define DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Vertical synchronization active Low */
+#define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */
+
+#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
+ ((POLARITY) == DCMI_VSPOLARITY_HIGH))
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_HSYNC_Polarity
+ * @{
+ */
+#define DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Horizontal synchronization active Low */
+#define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */
+
+#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
+ ((POLARITY) == DCMI_HSPOLARITY_HIGH))
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_MODE_JPEG
+ * @{
+ */
+#define DCMI_JPEG_DISABLE ((uint32_t)0x00000000) /*!< Mode JPEG Disabled */
+#define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< Mode JPEG Enabled */
+
+#define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
+ ((JPEG_MODE) == DCMI_JPEG_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Capture_Rate
+ * @{
+ */
+#define DCMI_CR_ALL_FRAME ((uint32_t)0x00000000) /*!< All frames are captured */
+#define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */
+#define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */
+
+#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME) || \
+ ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
+ ((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Extended_Data_Mode
+ * @{
+ */
+#define DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000) /*!< Interface captures 8-bit data on every pixel clock */
+#define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */
+#define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */
+#define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */
+
+#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B) || \
+ ((DATA) == DCMI_EXTEND_DATA_10B) || \
+ ((DATA) == DCMI_EXTEND_DATA_12B) || \
+ ((DATA) == DCMI_EXTEND_DATA_14B))
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Window_Coordinate
+ * @{
+ */
+#define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFF) /*!< Window coordinate */
+
+#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Window_Height
+ * @{
+ */
+#define DCMI_WINDOW_HEIGHT ((uint32_t)0x1FFF) /*!< Window Height */
+
+#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_interrupt_sources
+ * @{
+ */
+#define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE)
+#define DCMI_IT_OVF ((uint32_t)DCMI_IER_OVF_IE)
+#define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE)
+#define DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE)
+#define DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE)
+
+#define IS_DCMI_CONFIG_IT(IT) ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000))
+
+#define IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) || \
+ ((IT) == DCMI_IT_OVF) || \
+ ((IT) == DCMI_IT_ERR) || \
+ ((IT) == DCMI_IT_VSYNC) || \
+ ((IT) == DCMI_IT_LINE))
+/**
+ * @}
+ */
+
+/** @defgroup DCMI_Flags
+ * @{
+ */
+
+/**
+ * @brief DCMI SR register
+ */
+#define DCMI_FLAG_HSYNC ((uint32_t)0x2001)
+#define DCMI_FLAG_VSYNC ((uint32_t)0x2002)
+#define DCMI_FLAG_FNE ((uint32_t)0x2004)
+/**
+ * @brief DCMI RISR register
+ */
+#define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RISR_FRAME_RIS)
+#define DCMI_FLAG_OVFRI ((uint32_t)DCMI_RISR_OVF_RIS)
+#define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RISR_ERR_RIS)
+#define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RISR_VSYNC_RIS)
+#define DCMI_FLAG_LINERI ((uint32_t)DCMI_RISR_LINE_RIS)
+/**
+ * @brief DCMI MISR register
+ */
+#define DCMI_FLAG_FRAMEMI ((uint32_t)0x1001)
+#define DCMI_FLAG_OVFMI ((uint32_t)0x1002)
+#define DCMI_FLAG_ERRMI ((uint32_t)0x1004)
+#define DCMI_FLAG_VSYNCMI ((uint32_t)0x1008)
+#define DCMI_FLAG_LINEMI ((uint32_t)0x1010)
+#define IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC) || \
+ ((FLAG) == DCMI_FLAG_VSYNC) || \
+ ((FLAG) == DCMI_FLAG_FNE) || \
+ ((FLAG) == DCMI_FLAG_FRAMERI) || \
+ ((FLAG) == DCMI_FLAG_OVFRI) || \
+ ((FLAG) == DCMI_FLAG_ERRRI) || \
+ ((FLAG) == DCMI_FLAG_VSYNCRI) || \
+ ((FLAG) == DCMI_FLAG_LINERI) || \
+ ((FLAG) == DCMI_FLAG_FRAMEMI) || \
+ ((FLAG) == DCMI_FLAG_OVFMI) || \
+ ((FLAG) == DCMI_FLAG_ERRMI) || \
+ ((FLAG) == DCMI_FLAG_VSYNCMI) || \
+ ((FLAG) == DCMI_FLAG_LINEMI))
+
+#define IS_DCMI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset DCMI handle state
+ * @param __HANDLE__: specifies the DCMI handle.
+ * @retval None
+ */
+#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
+
+/**
+ * @brief Enable the DCMI.
+ * @param __HANDLE__: DCMI handle
+ * @retval None
+ */
+#define __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
+
+/**
+ * @brief Disable the DCMI.
+ * @param __HANDLE__: DCMI handle
+ * @retval None
+ */
+#define __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
+
+/* Interrupt & Flag management */
+/**
+ * @brief Get the DCMI pending flags.
+ * @param __HANDLE__: DCMI handle
+ * @param __FLAG__: Get the specified flag.
+ * This parameter can be any combination of the following values:
+ * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
+ * @arg DCMI_FLAG_OVFRI: Overflow flag mask
+ * @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
+ * @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
+ * @arg DCMI_FLAG_LINERI: Line flag mask
+ * @retval The state of FLAG.
+ */
+#define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\
+((((__FLAG__) & 0x3000) == 0x0)? ((__HANDLE__)->Instance->RISR & (__FLAG__)) :\
+ (((__FLAG__) & 0x2000) == 0x0)? ((__HANDLE__)->Instance->MISR & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))
+
+/**
+ * @brief Clear the DCMI pending flags.
+ * @param __HANDLE__: DCMI handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
+ * @arg DCMI_FLAG_OVFRI: Overflow flag mask
+ * @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
+ * @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
+ * @arg DCMI_FLAG_LINERI: Line flag mask
+ * @retval None
+ */
+#define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR |= (__FLAG__))
+
+/**
+ * @brief Enable the specified DCMI interrupts.
+ * @param __HANDLE__: DCMI handle
+ * @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
+ * @arg DCMI_IT_OVF: Overflow interrupt mask
+ * @arg DCMI_IT_ERR: Synchronization error interrupt mask
+ * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
+ * @arg DCMI_IT_LINE: Line interrupt mask
+ * @retval None
+ */
+#define __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified DCMI interrupts.
+ * @param __HANDLE__: DCMI handle
+ * @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
+ * @arg DCMI_IT_OVF: Overflow interrupt mask
+ * @arg DCMI_IT_ERR: Synchronization error interrupt mask
+ * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
+ * @arg DCMI_IT_LINE: Line interrupt mask
+ * @retval None
+ */
+#define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified DCMI interrupt has occurred or not.
+ * @param __HANDLE__: DCMI handle
+ * @param __INTERRUPT__: specifies the DCMI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
+ * @arg DCMI_IT_OVF: Overflow interrupt mask
+ * @arg DCMI_IT_ERR: Synchronization error interrupt mask
+ * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
+ * @arg DCMI_IT_LINE: Line interrupt mask
+ * @retval The state of INTERRUPT.
+ */
+#define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
+void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);
+void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);
+void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
+void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
+void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
+void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);
+void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
+
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
+HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi);
+
+/* Peripheral State functions *************************************************/
+HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi);
+uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_DCMI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_def.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,148 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_def.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief This file contains HAL common defines, enumeration, macros and
+ * structures definitions.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DEF
+#define __STM32F4xx_HAL_DEF
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HAL Status structures definition
+ */
+typedef enum
+{
+ HAL_OK = 0x00,
+ HAL_ERROR = 0x01,
+ HAL_BUSY = 0x02,
+ HAL_TIMEOUT = 0x03
+} HAL_StatusTypeDef;
+
+/**
+ * @brief HAL Lock structures definition
+ */
+typedef enum
+{
+ HAL_UNLOCKED = 0x00,
+ HAL_LOCKED = 0x01
+} HAL_LockTypeDef;
+
+/* Exported macro ------------------------------------------------------------*/
+#ifndef NULL
+ #define NULL (void *) 0
+#endif
+
+#define HAL_MAX_DELAY 0xFFFFFFFF
+
+#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
+#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
+ do{ \
+ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
+ (__DMA_HANDLE__).Parent = (__HANDLE__); \
+ } while(0)
+
+#if (USE_RTOS == 1)
+ /* Reserved for future use */
+#else
+ #define __HAL_LOCK(__HANDLE__) \
+ do{ \
+ if((__HANDLE__)->Lock == HAL_LOCKED) \
+ { \
+ return HAL_BUSY; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Lock = HAL_LOCKED; \
+ } \
+ }while (0)
+
+ #define __HAL_UNLOCK(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->Lock = HAL_UNLOCKED; \
+ }while (0)
+#endif /* USE_RTOS */
+
+#if defined ( __GNUC__ )
+ #ifndef __weak
+ #define __weak __attribute__((weak))
+ #endif /* __weak */
+ #ifndef __packed
+ #define __packed __attribute__((__packed__))
+ #endif /* __packed */
+#endif /* __GNUC__ */
+
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+#if defined (__GNUC__) /* GNU Compiler */
+ #ifndef __ALIGN_END
+ #define __ALIGN_END __attribute__ ((aligned (4)))
+ #endif /* __ALIGN_END */
+ #ifndef __ALIGN_BEGIN
+ #define __ALIGN_BEGIN
+ #endif /* __ALIGN_BEGIN */
+#else
+ #ifndef __ALIGN_END
+ #define __ALIGN_END
+ #endif /* __ALIGN_END */
+ #ifndef __ALIGN_BEGIN
+ #if defined (__CC_ARM) /* ARM Compiler */
+ #define __ALIGN_BEGIN __align(4)
+ #elif defined (__ICCARM__) /* IAR Compiler */
+ #define __ALIGN_BEGIN
+ #elif defined (__TASKING__) /* TASKING Compiler */
+ #define __ALIGN_BEGIN __align(4)
+ #endif /* __CC_ARM */
+ #endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32F4xx_HAL_DEF */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_dma.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,697 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dma.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of DMA HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DMA_H
+#define __STM32F4xx_HAL_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief DMA Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Channel; /*!< Specifies the channel used for the specified stream.
+ This parameter can be a value of @ref DMA_Channel_selection */
+
+ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
+ from memory to memory or from peripheral to memory.
+ This parameter can be a value of @ref DMA_Data_transfer_direction */
+
+ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
+ This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
+
+ uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
+ This parameter can be a value of @ref DMA_Memory_incremented_mode */
+
+ uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
+ This parameter can be a value of @ref DMA_Peripheral_data_size */
+
+ uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
+ This parameter can be a value of @ref DMA_Memory_data_size */
+
+ uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
+ This parameter can be a value of @ref DMA_mode
+ @note The circular buffer mode cannot be used if the memory-to-memory
+ data transfer is configured on the selected Stream */
+
+ uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
+ This parameter can be a value of @ref DMA_Priority_level */
+
+ uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
+ This parameter can be a value of @ref DMA_FIFO_direct_mode
+ @note The Direct mode (FIFO mode disabled) cannot be used if the
+ memory-to-memory data transfer is configured on the selected stream */
+
+ uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
+ This parameter can be a value of @ref DMA_FIFO_threshold_level */
+
+ uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
+ It specifies the amount of data to be transferred in a single non interruptable
+ transaction.
+ This parameter can be a value of @ref DMA_Memory_burst
+ @note The burst mode is possible only if the address Increment mode is enabled. */
+
+ uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
+ It specifies the amount of data to be transferred in a single non interruptable
+ transaction.
+ This parameter can be a value of @ref DMA_Peripheral_burst
+ @note The burst mode is possible only if the address Increment mode is enabled. */
+}DMA_InitTypeDef;
+
+/**
+ * @brief HAL DMA State structures definition
+ */
+typedef enum
+{
+ HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
+ HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
+ HAL_DMA_STATE_READY_MEM0 = 0x11, /*!< DMA Mem0 process success */
+ HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */
+ HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, /*!< DMA Mem0 Half process success */
+ HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */
+ HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
+ HAL_DMA_STATE_BUSY_MEM0 = 0x12, /*!< DMA Mem0 process is ongoing */
+ HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */
+ HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
+ HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
+}HAL_DMA_StateTypeDef;
+
+/**
+ * @brief HAL DMA Error Code structure definition
+ */
+typedef enum
+{
+ HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
+ HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
+}HAL_DMA_LevelCompleteTypeDef;
+
+/**
+ * @brief DMA handle Structure definition
+ */
+typedef struct __DMA_HandleTypeDef
+{
+ DMA_Stream_TypeDef *Instance; /*!< Register base address */
+
+ DMA_InitTypeDef Init; /*!< DMA communication parameters */
+
+ HAL_LockTypeDef Lock; /*!< DMA locking object */
+
+ __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
+
+ void *Parent; /*!< Parent object state */
+
+ void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
+
+ void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
+
+ void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
+
+ void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
+
+ __IO uint32_t ErrorCode; /*!< DMA Error code */
+}DMA_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants
+ * @{
+ */
+
+/** @defgroup DMA_Error_Code
+ * @{
+ */
+#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
+#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */
+#define HAL_DMA_ERROR_DME ((uint32_t)0x00000004) /*!< Direct Mode error */
+#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Channel_selection
+ * @{
+ */
+#define DMA_CHANNEL_0 ((uint32_t)0x00000000) /*!< DMA Channel 0 */
+#define DMA_CHANNEL_1 ((uint32_t)0x02000000) /*!< DMA Channel 1 */
+#define DMA_CHANNEL_2 ((uint32_t)0x04000000) /*!< DMA Channel 2 */
+#define DMA_CHANNEL_3 ((uint32_t)0x06000000) /*!< DMA Channel 3 */
+#define DMA_CHANNEL_4 ((uint32_t)0x08000000) /*!< DMA Channel 4 */
+#define DMA_CHANNEL_5 ((uint32_t)0x0A000000) /*!< DMA Channel 5 */
+#define DMA_CHANNEL_6 ((uint32_t)0x0C000000) /*!< DMA Channel 6 */
+#define DMA_CHANNEL_7 ((uint32_t)0x0E000000) /*!< DMA Channel 7 */
+
+#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
+ ((CHANNEL) == DMA_CHANNEL_1) || \
+ ((CHANNEL) == DMA_CHANNEL_2) || \
+ ((CHANNEL) == DMA_CHANNEL_3) || \
+ ((CHANNEL) == DMA_CHANNEL_4) || \
+ ((CHANNEL) == DMA_CHANNEL_5) || \
+ ((CHANNEL) == DMA_CHANNEL_6) || \
+ ((CHANNEL) == DMA_CHANNEL_7))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Data_transfer_direction
+ * @{
+ */
+#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
+ ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Data_buffer_size
+ * @{
+ */
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_incremented_mode
+ * @{
+ */
+#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
+#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode disable */
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
+ ((STATE) == DMA_PINC_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Memory_incremented_mode
+ * @{
+ */
+#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
+#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode disable */
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
+ ((STATE) == DMA_MINC_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_data_size
+ * @{
+ */
+#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */
+#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
+#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
+ ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+ ((SIZE) == DMA_PDATAALIGN_WORD))
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_Memory_data_size
+ * @{
+ */
+#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */
+#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
+#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
+ ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+ ((SIZE) == DMA_MDATAALIGN_WORD ))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_mode
+ * @{
+ */
+#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
+#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
+#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
+ ((MODE) == DMA_CIRCULAR) || \
+ ((MODE) == DMA_PFCTRL))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Priority_level
+ * @{
+ */
+#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level: Low */
+#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
+#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
+#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
+ ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+ ((PRIORITY) == DMA_PRIORITY_HIGH) || \
+ ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_FIFO_direct_mode
+ * @{
+ */
+#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000) /*!< FIFO mode disable */
+#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
+
+#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
+ ((STATE) == DMA_FIFOMODE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_FIFO_threshold_level
+ * @{
+ */
+#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000) /*!< FIFO threshold 1 quart full configuration */
+#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
+#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
+#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
+
+#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Memory_burst
+ * @{
+ */
+#define DMA_MBURST_SINGLE ((uint32_t)0x00000000)
+#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
+#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
+#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
+
+#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
+ ((BURST) == DMA_MBURST_INC4) || \
+ ((BURST) == DMA_MBURST_INC8) || \
+ ((BURST) == DMA_MBURST_INC16))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_burst
+ * @{
+ */
+#define DMA_PBURST_SINGLE ((uint32_t)0x00000000)
+#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
+#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
+#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
+
+#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
+ ((BURST) == DMA_PBURST_INC4) || \
+ ((BURST) == DMA_PBURST_INC8) || \
+ ((BURST) == DMA_PBURST_INC16))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_interrupt_enable_definitions
+ * @{
+ */
+#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
+#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
+#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
+#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
+#define DMA_IT_FE ((uint32_t)0x00000080)
+/**
+ * @}
+ */
+
+/** @defgroup DMA_flag_definitions
+ * @{
+ */
+#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001)
+#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004)
+#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008)
+#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010)
+#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020)
+#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040)
+#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100)
+#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200)
+#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400)
+#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800)
+#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000)
+#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000)
+#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000)
+#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000)
+#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000)
+#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000)
+#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000)
+#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000)
+#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000)
+#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset DMA handle state
+ * @param __HANDLE__: specifies the DMA handle.
+ * @retval None
+ */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
+/**
+ * @brief Return the current DMA Stream FIFO filled level.
+ * @param __HANDLE__: DMA handle
+ * @retval The FIFO filling state.
+ * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
+ * and not empty.
+ * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
+ * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
+ * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
+ * - DMA_FIFOStatus_Empty: when FIFO is empty
+ * - DMA_FIFOStatus_Full: when FIFO is full
+ */
+#define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
+
+/**
+ * @brief Enable the specified DMA Stream.
+ * @param __HANDLE__: DMA handle
+ * @retval None
+ */
+#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
+
+/**
+ * @brief Disable the specified DMA Stream.
+ * @param __HANDLE__: DMA handle
+ * @retval None
+ */
+#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
+
+/* Interrupt & Flag management */
+
+/**
+ * @brief Return the current DMA Stream transfer complete flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified transfer complete flag index.
+ */
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
+ DMA_FLAG_TCIF3_7)
+
+/**
+ * @brief Return the current DMA Stream half transfer complete flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified half transfer complete flag index.
+ */
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
+ DMA_FLAG_HTIF3_7)
+
+/**
+ * @brief Return the current DMA Stream transfer error flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
+ DMA_FLAG_TEIF3_7)
+
+/**
+ * @brief Return the current DMA Stream FIFO error flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified FIFO error flag index.
+ */
+#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
+ DMA_FLAG_FEIF3_7)
+
+/**
+ * @brief Return the current DMA Stream direct mode error flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified direct mode error flag index.
+ */
+#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
+ DMA_FLAG_DMEIF3_7)
+
+/**
+ * @brief Get the DMA Stream pending flags.
+ * @param __HANDLE__: DMA handle
+ * @param __FLAG__: Get the specified flag.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCIFx: Transfer complete flag.
+ * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
+ * @arg DMA_FLAG_TEIFx: Transfer error flag.
+ * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
+ * @arg DMA_FLAG_FEIFx: FIFO error flag.
+ * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
+
+/**
+ * @brief Clear the DMA Stream pending flags.
+ * @param __HANDLE__: DMA handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCIFx: Transfer complete flag.
+ * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
+ * @arg DMA_FLAG_TEIFx: Transfer error flag.
+ * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
+ * @arg DMA_FLAG_FEIFx: FIFO error flag.
+ * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
+ * @retval None
+ */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR |= (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR |= (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR |= (__FLAG__)) : (DMA1->LIFCR |= (__FLAG__)))
+
+/**
+ * @brief Enable the specified DMA Stream interrupts.
+ * @param __HANDLE__: DMA handle
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask.
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask.
+ * @arg DMA_IT_TE: Transfer error interrupt mask.
+ * @arg DMA_IT_FE: FIFO error interrupt mask.
+ * @arg DMA_IT_DME: Direct mode error interrupt.
+ * @retval None
+ */
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
+((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
+
+/**
+ * @brief Disable the specified DMA Stream interrupts.
+ * @param __HANDLE__: DMA handle
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask.
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask.
+ * @arg DMA_IT_TE: Transfer error interrupt mask.
+ * @arg DMA_IT_FE: FIFO error interrupt mask.
+ * @arg DMA_IT_DME: Direct mode error interrupt.
+ * @retval None
+ */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
+((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
+
+/**
+ * @brief Check whether the specified DMA Stream interrupt has occurred or not.
+ * @param __HANDLE__: DMA handle
+ * @param __INTERRUPT__: specifies the DMA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask.
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask.
+ * @arg DMA_IT_TE: Transfer error interrupt mask.
+ * @arg DMA_IT_FE: FIFO error interrupt mask.
+ * @arg DMA_IT_DME: Direct mode error interrupt.
+ * @retval The state of DMA_IT.
+ */
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
+ ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
+ ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
+
+/**
+ * @brief Writes the number of data units to be transferred on the DMA Stream.
+ * @param __HANDLE__: DMA handle
+ * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535)
+ * Number of data items depends only on the Peripheral data format.
+ *
+ * @note If Peripheral data format is Bytes: number of data units is equal
+ * to total number of bytes to be transferred.
+ *
+ * @note If Peripheral data format is Half-Word: number of data units is
+ * equal to total number of bytes to be transferred / 2.
+ *
+ * @note If Peripheral data format is Word: number of data units is equal
+ * to total number of bytes to be transferred / 4.
+ *
+ * @retval The number of remaining data units in the current DMAy Streamx transfer.
+ */
+#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
+
+/**
+ * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
+ * @param __HANDLE__: DMA handle
+ *
+ * @retval The number of remaining data units in the current DMA Stream transfer.
+ */
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
+
+
+/* Include DMA HAL Extension module */
+#include "stm32f4xx_hal_dma_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+
+/* Peripheral State and Error functions ***************************************/
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_dma2d.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,503 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dma2d.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of DMA2D HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DMA2D_H
+#define __STM32F4xx_HAL_DMA2D_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DMA2D
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+#define MAX_DMA2D_LAYER 2
+
+/**
+ * @brief DMA2D color Structure definition
+ */
+typedef struct
+{
+ uint32_t Blue; /*!< Configures the blue value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+ uint32_t Green; /*!< Configures the green value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+ uint32_t Red; /*!< Configures the red value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+} DMA2D_ColorTypeDef;
+
+/**
+ * @brief DMA2D CLUT Structure definition
+ */
+typedef struct
+{
+ uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/
+
+ uint32_t CLUTColorMode; /*!< configures the DMA2D CLUT color mode.
+ This parameter can be one value of @ref DMA2D_CLUT_CM */
+
+ uint32_t Size; /*!< configures the DMA2D CLUT size.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
+} DMA2D_CLUTCfgTypeDef;
+
+/**
+ * @brief DMA2D Init structure definition
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< configures the DMA2D transfer mode.
+ This parameter can be one value of @ref DMA2D_Mode */
+
+ uint32_t ColorMode; /*!< configures the color format of the output image.
+ This parameter can be one value of @ref DMA2D_Color_Mode */
+
+ uint32_t OutputOffset; /*!< Specifies the Offset value.
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
+} DMA2D_InitTypeDef;
+
+/**
+ * @brief DMA2D Layer structure definition
+ */
+typedef struct
+{
+ uint32_t InputOffset; /*!< configures the DMA2D foreground offset.
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
+
+ uint32_t InputColorMode; /*!< configures the DMA2D foreground color mode .
+ This parameter can be one value of @ref DMA2D_Input_Color_Mode */
+
+ uint32_t AlphaMode; /*!< configures the DMA2D foreground alpha mode.
+ This parameter can be one value of @ref DMA2D_ALPHA_MODE */
+
+ uint32_t InputAlpha; /*!< Specifies the DMA2D foreground alpha value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+} DMA2D_LayerCfgTypeDef;
+
+/**
+ * @brief HAL DMA2D State structures definition
+ */
+typedef enum
+{
+ HAL_DMA2D_STATE_RESET = 0x00, /*!< DMA2D not yet initialized or disabled */
+ HAL_DMA2D_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_DMA2D_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_DMA2D_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_DMA2D_STATE_ERROR = 0x04, /*!< DMA2D state error */
+ HAL_DMA2D_STATE_SUSPEND = 0x05 /*!< DMA2D process is suspended */
+}HAL_DMA2D_StateTypeDef;
+
+/**
+ * @brief DMA2D handle Structure definition
+ */
+typedef struct __DMA2D_HandleTypeDef
+{
+ DMA2D_TypeDef *Instance; /*!< DMA2D Register base address */
+
+ DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters */
+
+ void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback */
+
+ void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback */
+
+ DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
+
+ HAL_LockTypeDef Lock; /*!< DMA2D Lock */
+
+ __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state */
+
+ __IO uint32_t ErrorCode; /*!< DMA2D Error code */
+} DMA2D_HandleTypeDef;
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA2D_Exported_Constants
+ * @{
+ */
+
+/** @defgroup DMA2D_Layer
+ * @{
+ */
+#define IS_DMA2D_LAYER(LAYER) ((LAYER) <= MAX_DMA2D_LAYER)
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Error_Code
+ * @{
+ */
+#define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
+#define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002) /*!< Configuration error */
+#define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Mode
+ * @{
+ */
+#define DMA2D_M2M ((uint32_t)0x00000000) /*!< DMA2D memory to memory transfer mode */
+#define DMA2D_M2M_PFC ((uint32_t)0x00010000) /*!< DMA2D memory to memory with pixel format conversion transfer mode */
+#define DMA2D_M2M_BLEND ((uint32_t)0x00020000) /*!< DMA2D memory to memory with blending transfer mode */
+#define DMA2D_R2M ((uint32_t)0x00030000) /*!< DMA2D register to memory transfer mode */
+
+#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
+ ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Color_Mode
+ * @{
+ */
+#define DMA2D_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 DMA2D color mode */
+#define DMA2D_RGB888 ((uint32_t)0x00000001) /*!< RGB888 DMA2D color mode */
+#define DMA2D_RGB565 ((uint32_t)0x00000002) /*!< RGB565 DMA2D color mode */
+#define DMA2D_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 DMA2D color mode */
+#define DMA2D_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 DMA2D color mode */
+
+#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888) || \
+ ((MODE_ARGB) == DMA2D_RGB565) || ((MODE_ARGB) == DMA2D_ARGB1555) || \
+ ((MODE_ARGB) == DMA2D_ARGB4444))
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_COLOR_VALUE
+ * @{
+ */
+
+#define COLOR_VALUE ((uint32_t)0x000000FF) /*!< color value mask */
+
+#define IS_DMA2D_ALPHA_VALUE(ALPHA_VALUE) ((ALPHA_VALUE) <= COLOR_VALUE)
+#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= COLOR_VALUE)
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_SIZE
+ * @{
+ */
+#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16) /*!< DMA2D pixel per line */
+#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of line */
+
+#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
+#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Offset
+ * @{
+ */
+#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */
+
+#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Input_Color_Mode
+ * @{
+ */
+#define CM_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 color mode */
+#define CM_RGB888 ((uint32_t)0x00000001) /*!< RGB888 color mode */
+#define CM_RGB565 ((uint32_t)0x00000002) /*!< RGB565 color mode */
+#define CM_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 color mode */
+#define CM_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 color mode */
+#define CM_L8 ((uint32_t)0x00000005) /*!< L8 color mode */
+#define CM_AL44 ((uint32_t)0x00000006) /*!< AL44 color mode */
+#define CM_AL88 ((uint32_t)0x00000007) /*!< AL88 color mode */
+#define CM_L4 ((uint32_t)0x00000008) /*!< L4 color mode */
+#define CM_A8 ((uint32_t)0x00000009) /*!< A8 color mode */
+#define CM_A4 ((uint32_t)0x0000000A) /*!< A4 color mode */
+
+#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == CM_ARGB8888) || ((INPUT_CM) == CM_RGB888) || \
+ ((INPUT_CM) == CM_RGB565) || ((INPUT_CM) == CM_ARGB1555) || \
+ ((INPUT_CM) == CM_ARGB4444) || ((INPUT_CM) == CM_L8) || \
+ ((INPUT_CM) == CM_AL44) || ((INPUT_CM) == CM_AL88) || \
+ ((INPUT_CM) == CM_L4) || ((INPUT_CM) == CM_A8) || \
+ ((INPUT_CM) == CM_A4))
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_ALPHA_MODE
+ * @{
+ */
+#define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000) /*!< No modification of the alpha channel value */
+#define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001) /*!< Replace original alpha channel value by programmed alpha value */
+#define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002) /*!< Replace original alpha channel value by programmed alpha value
+ with original alpha channel value */
+
+#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
+ ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
+ ((AlphaMode) == DMA2D_COMBINE_ALPHA))
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_CLUT_CM
+ * @{
+ */
+#define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 DMA2D C-LUT color mode */
+#define DMA2D_CCM_RGB888 ((uint32_t)0x00000001) /*!< RGB888 DMA2D C-LUT color mode */
+
+#define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Size_Clut
+ * @{
+ */
+#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D C-LUT size */
+
+#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_DeadTime
+ * @{
+ */
+#define LINE_WATERMARK DMA2D_LWR_LW
+
+#define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK)
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Interrupts
+ * @{
+ */
+#define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
+#define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< C-LUT Transfer Complete Interrupt */
+#define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< C-LUT Access Error Interrupt */
+#define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
+#define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
+#define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
+
+#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
+ ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
+ ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Flag
+ * @{
+ */
+#define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
+#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< C-LUT Transfer Complete Interrupt Flag */
+#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< C-LUT Access Error Interrupt Flag */
+#define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
+
+#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
+ ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
+ ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset DMA2D handle state
+ * @param __HANDLE__: specifies the DMA2D handle.
+ * @retval None
+ */
+#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
+
+/**
+ * @brief Enable the DMA2D.
+ * @param __HANDLE__: DMA2D handle
+ * @retval None.
+ */
+#define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
+
+/**
+ * @brief Disable the DMA2D.
+ * @param __HANDLE__: DMA2D handle
+ * @retval None.
+ */
+#define __HAL_DMA2D_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA2D_CR_START)
+
+/* Interrupt & Flag management */
+/**
+ * @brief Get the DMA2D pending flags.
+ * @param __HANDLE__: DMA2D handle
+ * @param __FLAG__: Get the specified flag.
+ * This parameter can be any combination of the following values:
+ * @arg DMA2D_FLAG_CE: Configuration error flag
+ * @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag
+ * @arg DMA2D_FLAG_CAE: C-LUT access error flag
+ * @arg DMA2D_FLAG_TW: Transfer Watermark flag
+ * @arg DMA2D_FLAG_TC: Transfer complete flag
+ * @arg DMA2D_FLAG_TE: Transfer error flag
+ * @retval The state of FLAG.
+ */
+#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
+
+/**
+ * @brief Clears the DMA2D pending flags.
+ * @param __HANDLE__: DMA2D handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DMA2D_FLAG_CE: Configuration error flag
+ * @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag
+ * @arg DMA2D_FLAG_CAE: C-LUT access error flag
+ * @arg DMA2D_FLAG_TW: Transfer Watermark flag
+ * @arg DMA2D_FLAG_TC: Transfer complete flag
+ * @arg DMA2D_FLAG_TE: Transfer error flag
+ * @retval None
+ */
+#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR |= (__FLAG__))
+
+/**
+ * @brief Enables the specified DMA2D interrupts.
+ * @param __HANDLE__: DMA2D handle
+ * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA2D_IT_CE: Configuration error interrupt mask
+ * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
+ * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
+ * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
+ * @arg DMA2D_IT_TC: Transfer complete interrupt mask
+ * @arg DMA2D_IT_TE: Transfer error interrupt mask
+ * @retval None
+ */
+#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified DMA2D interrupts.
+ * @param __HANDLE__: DMA2D handle
+ * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA2D_IT_CE: Configuration error interrupt mask
+ * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
+ * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
+ * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
+ * @arg DMA2D_IT_TC: Transfer complete interrupt mask
+ * @arg DMA2D_IT_TE: Transfer error interrupt mask
+ * @retval None
+ */
+#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Checks whether the specified DMA2D interrupt has occurred or not.
+ * @param __HANDLE__: DMA2D handle
+ * @param __INTERRUPT__: specifies the DMA2D interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DMA2D_IT_CE: Configuration error interrupt mask
+ * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
+ * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
+ * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
+ * @arg DMA2D_IT_TC: Transfer complete interrupt mask
+ * @arg DMA2D_IT_TE: Transfer error interrupt mask
+ * @retval The state of INTERRUPT.
+ */
+#define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions *******************************/
+HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
+void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
+void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
+HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
+HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
+void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
+
+/* Peripheral Control functions *************************************************/
+HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_DisableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
+
+/* Peripheral State functions ***************************************************/
+HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
+uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_DMA2D_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_dma_ex.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,92 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_dma_ex.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of DMA HAL extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DMA_EX_H
+#define __STM32F4xx_HAL_DMA_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DMAEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HAL DMA Memory definition
+ */
+typedef enum
+{
+ MEMORY0 = 0x00, /*!< Memory 0 */
+ MEMORY1 = 0x01, /*!< Memory 1 */
+
+}HAL_DMA_MemoryTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_eth.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,2192 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_eth.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of ETH HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_ETH_H
+#define __STM32F4xx_HAL_ETH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ETH
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_ETH_STATE_RESET = 0x00, /*!< Peripheral not yet Initialized or disabled */
+ HAL_ETH_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_ETH_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_ETH_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_ETH_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_ETH_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
+ HAL_ETH_STATE_BUSY_WR = 0x42, /*!< Write process is ongoing */
+ HAL_ETH_STATE_BUSY_RD = 0x82, /*!< Read process is ongoing */
+ HAL_ETH_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_ETH_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
+}HAL_ETH_StateTypeDef;
+
+/**
+ * @brief ETH Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
+ The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
+ and the mode (half/full-duplex).
+ This parameter can be a value of @ref ETH_AutoNegotiation */
+
+ uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
+ This parameter can be a value of @ref ETH_Speed */
+
+ uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
+ This parameter can be a value of @ref ETH_Duplex_Mode */
+
+ uint16_t PhyAddress; /*!< Ethernet PHY address.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
+
+ uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
+
+ uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
+ This parameter can be a value of @ref ETH_Rx_Mode */
+
+ uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
+ This parameter can be a value of @ref ETH_Checksum_Mode */
+
+ uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
+ This parameter can be a value of @ref ETH_Media_Interface */
+
+} ETH_InitTypeDef;
+
+
+ /**
+ * @brief ETH MAC Configuration Structure definition
+ */
+
+typedef struct
+{
+ uint32_t Watchdog; /*!< Selects or not the Watchdog timer
+ When enabled, the MAC allows no more then 2048 bytes to be received.
+ When disabled, the MAC can receive up to 16384 bytes.
+ This parameter can be a value of @ref ETH_watchdog */
+
+ uint32_t Jabber; /*!< Selects or not Jabber timer
+ When enabled, the MAC allows no more then 2048 bytes to be sent.
+ When disabled, the MAC can send up to 16384 bytes.
+ This parameter can be a value of @ref ETH_Jabber */
+
+ uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
+ This parameter can be a value of @ref ETH_Inter_Frame_Gap */
+
+ uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
+ This parameter can be a value of @ref ETH_Carrier_Sense */
+
+ uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
+ ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
+ in Half-Duplex mode.
+ This parameter can be a value of @ref ETH_Receive_Own */
+
+ uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
+ This parameter can be a value of @ref ETH_Loop_Back_Mode */
+
+ uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
+ This parameter can be a value of @ref ETH_Checksum_Offload */
+
+ uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
+ when a collision occurs (Half-Duplex mode).
+ This parameter can be a value of @ref ETH_Retry_Transmission */
+
+ uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
+ This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
+
+ uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
+ This parameter can be a value of @ref ETH_Back_Off_Limit */
+
+ uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
+ This parameter can be a value of @ref ETH_Deferral_Check */
+
+ uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
+ This parameter can be a value of @ref ETH_Receive_All */
+
+ uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
+ This parameter can be a value of @ref ETH_Source_Addr_Filter */
+
+ uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
+ This parameter can be a value of @ref ETH_Pass_Control_Frames */
+
+ uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
+ This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
+
+ uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
+ This parameter can be a value of @ref ETH_Destination_Addr_Filter */
+
+ uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
+ This parameter can be a value of @ref ETH_Promiscuous_Mode */
+
+ uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
+ This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
+
+ uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
+ This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
+
+ uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
+
+ uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
+
+ uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
+
+ uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
+ This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
+
+ uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
+ automatic retransmission of PAUSE Frame.
+ This parameter can be a value of @ref ETH_Pause_Low_Threshold */
+
+ uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
+ unicast address and unique multicast address).
+ This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
+
+ uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
+ disable its transmitter for a specified time (Pause Time)
+ This parameter can be a value of @ref ETH_Receive_Flow_Control */
+
+ uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
+ or the MAC back-pressure operation (Half-Duplex mode)
+ This parameter can be a value of @ref ETH_Transmit_Flow_Control */
+
+ uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
+ comparison and filtering.
+ This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
+
+ uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
+
+} ETH_MACInitTypeDef;
+
+
+/**
+ * @brief ETH DMA Configuration Structure definition
+ */
+
+typedef struct
+{
+ uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
+ This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
+
+ uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
+ This parameter can be a value of @ref ETH_Receive_Store_Forward */
+
+ uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
+ This parameter can be a value of @ref ETH_Flush_Received_Frame */
+
+ uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
+ This parameter can be a value of @ref ETH_Transmit_Store_Forward */
+
+ uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
+ This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
+
+ uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
+ This parameter can be a value of @ref ETH_Forward_Error_Frames */
+
+ uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
+ and length less than 64 bytes) including pad-bytes and CRC)
+ This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
+
+ uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
+ This parameter can be a value of @ref ETH_Receive_Threshold_Control */
+
+ uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
+ frame of Transmit data even before obtaining the status for the first frame.
+ This parameter can be a value of @ref ETH_Second_Frame_Operate */
+
+ uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
+ This parameter can be a value of @ref ETH_Address_Aligned_Beats */
+
+ uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
+ This parameter can be a value of @ref ETH_Fixed_Burst */
+
+ uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
+ This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
+
+ uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
+ This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
+
+ uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
+ This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
+
+ uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
+ This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
+
+ uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
+ This parameter can be a value of @ref ETH_DMA_Arbitration */
+} ETH_DMAInitTypeDef;
+
+
+/**
+ * @brief ETH DMA Descriptors data structure definition
+ */
+
+typedef struct
+{
+ __IO uint32_t Status; /*!< Status */
+
+ uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
+
+ uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
+
+ uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
+
+ /*!< Enhanced ETHERNET DMA PTP Descriptors */
+ uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */
+
+ uint32_t Reserved1; /*!< Reserved */
+
+ uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */
+
+ uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */
+
+} ETH_DMADescTypeDef;
+
+
+/**
+ * @brief Received Frame Informations structure definition
+ */
+typedef struct
+{
+ ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */
+
+ ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */
+
+ uint32_t SegCount; /*!< Segment count */
+
+ uint32_t length; /*!< Frame length */
+
+ uint32_t buffer; /*!< Frame buffer */
+
+} ETH_DMARxFrameInfos;
+
+
+/**
+ * @brief ETH Handle Structure definition
+ */
+
+typedef struct
+{
+ ETH_TypeDef *Instance; /*!< Register base address */
+
+ ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
+
+ uint32_t LinkStatus; /*!< Ethernet link status */
+
+ ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */
+
+ ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */
+
+ ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */
+
+ __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */
+
+ HAL_LockTypeDef Lock; /*!< ETH Lock */
+
+} ETH_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
+
+/* Delay to wait when writing to some Ethernet registers */
+#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
+
+
+/* ETHERNET Errors */
+#define ETH_SUCCESS ((uint32_t)0)
+#define ETH_ERROR ((uint32_t)1)
+
+/** @defgroup ETH_Buffers_setting
+ * @{
+ */
+#define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /*!< ETH_HEADER + ETH_EXTRA + VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
+#define ETH_HEADER ((uint32_t)14) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define ETH_CRC ((uint32_t)4) /*!< Ethernet CRC */
+#define ETH_EXTRA ((uint32_t)2) /*!< Extra bytes in some cases */
+#define VLAN_TAG ((uint32_t)4) /*!< optional 802.1q VLAN Tag */
+#define MIN_ETH_PAYLOAD ((uint32_t)46) /*!< Minimum Ethernet payload size */
+#define MAX_ETH_PAYLOAD ((uint32_t)1500) /*!< Maximum Ethernet payload size */
+#define JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /*!< Jumbo frame payload size */
+
+ /* Ethernet driver receive buffers are organized in a chained linked-list, when
+ an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
+ to the driver receive buffers memory.
+
+ Depending on the size of the received ethernet packet and the size of
+ each ethernet driver receive buffer, the received packet can take one or more
+ ethernet driver receive buffer.
+
+ In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
+ and the total count of the driver receive buffers ETH_RXBUFNB.
+
+ The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
+ example, they can be reconfigured in the application layer to fit the application
+ needs */
+
+/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
+ packet */
+#ifndef ETH_RX_BUF_SIZE
+ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
+#endif
+
+/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
+#ifndef ETH_RXBUFNB
+ #define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
+#endif
+
+
+ /* Ethernet driver transmit buffers are organized in a chained linked-list, when
+ an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
+ driver transmit buffers memory to the TxFIFO.
+
+ Depending on the size of the Ethernet packet to be transmitted and the size of
+ each ethernet driver transmit buffer, the packet to be transmitted can take
+ one or more ethernet driver transmit buffer.
+
+ In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
+ and the total count of the driver transmit buffers ETH_TXBUFNB.
+
+ The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
+ example, they can be reconfigured in the application layer to fit the application
+ needs */
+
+/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
+ packet */
+#ifndef ETH_TX_BUF_SIZE
+ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
+#endif
+
+/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
+#ifndef ETH_TXBUFNB
+ #define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
+#endif
+
+
+/*
+ DMA Tx Desciptor
+ -----------------------------------------------------------------------------------------------
+ TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
+ -----------------------------------------------------------------------------------------------
+ TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
+ -----------------------------------------------------------------------------------------------
+ TDES2 | Buffer1 Address [31:0] |
+ -----------------------------------------------------------------------------------------------
+ TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
+ -----------------------------------------------------------------------------------------------
+*/
+
+/**
+ * @brief Bit definition of TDES0 register: DMA Tx descriptor status register
+ */
+#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */
+#define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /*!< Last Segment */
+#define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /*!< First Segment */
+#define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /*!< Disable CRC */
+#define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /*!< Disable Padding */
+#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */
+#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */
+#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */
+#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
+#define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */
+#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */
+#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */
+#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /*!< IP Header Error */
+#define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
+#define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */
+#define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
+#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */
+#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during transmission */
+#define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the transceiver */
+#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */
+#define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */
+#define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /*!< VLAN Frame */
+#define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /*!< Collision Count */
+#define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */
+#define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */
+#define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /*!< Deferred Bit */
+
+/**
+ * @brief Bit definition of TDES1 register
+ */
+#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */
+#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */
+
+/**
+ * @brief Bit definition of TDES2 register
+ */
+#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
+
+/**
+ * @brief Bit definition of TDES3 register
+ */
+#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
+
+ /*---------------------------------------------------------------------------------------------
+ TDES6 | Transmit Time Stamp Low [31:0] |
+ -----------------------------------------------------------------------------------------------
+ TDES7 | Transmit Time Stamp High [31:0] |
+ ----------------------------------------------------------------------------------------------*/
+
+/* Bit definition of TDES6 register */
+ #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */
+
+/* Bit definition of TDES7 register */
+ #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup ETH_DMA_Rx_descriptor
+ * @{
+ */
+
+/*
+ DMA Rx Descriptor
+ --------------------------------------------------------------------------------------------------------------------
+ RDES0 | OWN(31) | Status [30:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES2 | Buffer1 Address [31:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+*/
+
+/**
+ * @brief Bit definition of RDES0 register: DMA Rx descriptor status register
+ */
+#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */
+#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */
+#define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
+#define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /*!< Descriptor error: no more descriptors for receive frame */
+#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */
+#define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */
+#define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */
+#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */
+#define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */
+#define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */
+#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
+#define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */
+#define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */
+#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
+#define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */
+#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */
+#define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /*!< CRC error */
+#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
+
+/**
+ * @brief Bit definition of RDES1 register
+ */
+#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */
+#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */
+#define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */
+#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */
+#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */
+
+/**
+ * @brief Bit definition of RDES2 register
+ */
+#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
+
+/**
+ * @brief Bit definition of RDES3 register
+ */
+#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
+
+/*---------------------------------------------------------------------------------------------------------------------
+ RDES4 | Reserved[31:15] | Extended Status [14:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES5 | Reserved[31:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES6 | Receive Time Stamp Low [31:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES7 | Receive Time Stamp High [31:0] |
+ --------------------------------------------------------------------------------------------------------------------*/
+
+/* Bit definition of RDES4 register */
+#define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */
+#define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */
+#define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */
+ #define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */
+ #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */
+ #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */
+ #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */
+ #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
+ #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
+ #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
+#define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */
+#define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */
+#define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */
+#define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */
+#define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */
+#define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */
+ #define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */
+ #define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */
+ #define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */
+
+/* Bit definition of RDES6 register */
+#define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */
+
+/* Bit definition of RDES7 register */
+#define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */
+
+
+ /** @defgroup ETH_AutoNegotiation
+ * @{
+ */
+#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
+#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
+ ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
+/**
+ * @}
+ */
+/** @defgroup ETH_Speed
+ * @{
+ */
+#define ETH_SPEED_10M ((uint32_t)0x00000000)
+#define ETH_SPEED_100M ((uint32_t)0x00004000)
+#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
+ ((SPEED) == ETH_SPEED_100M))
+/**
+ * @}
+ */
+/** @defgroup ETH_Duplex_Mode
+ * @{
+ */
+#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
+#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
+#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
+ ((MODE) == ETH_MODE_HALFDUPLEX))
+/**
+ * @}
+ */
+/** @defgroup ETH_Rx_Mode
+ * @{
+ */
+#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
+#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
+#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
+ ((MODE) == ETH_RXINTERRUPT_MODE))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Checksum_Mode
+ * @{
+ */
+#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
+#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
+#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
+ ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Media_Interface
+ * @{
+ */
+#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
+#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
+#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
+ ((MODE) == ETH_MEDIA_INTERFACE_RMII))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_watchdog
+ * @{
+ */
+#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
+#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
+#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
+ ((CMD) == ETH_WATCHDOG_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Jabber
+ * @{
+ */
+#define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
+#define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
+#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
+ ((CMD) == ETH_JABBER_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Inter_Frame_Gap
+ * @{
+ */
+#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */
+#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */
+#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */
+#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */
+#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */
+#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */
+#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */
+#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */
+#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_40BIT))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Carrier_Sense
+ * @{
+ */
+#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
+#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
+#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
+ ((CMD) == ETH_CARRIERSENCE_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_Own
+ * @{
+ */
+#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
+#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
+#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
+ ((CMD) == ETH_RECEIVEOWN_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Loop_Back_Mode
+ * @{
+ */
+#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
+#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
+ ((CMD) == ETH_LOOPBACKMODE_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Checksum_Offload
+ * @{
+ */
+#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
+#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
+ ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Retry_Transmission
+ * @{
+ */
+#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
+#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
+#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
+ ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Automatic_Pad_CRC_Strip
+ * @{
+ */
+#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
+#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
+ ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Back_Off_Limit
+ * @{
+ */
+#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
+#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
+#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
+#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
+#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
+ ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
+ ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
+ ((LIMIT) == ETH_BACKOFFLIMIT_1))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Deferral_Check
+ * @{
+ */
+#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
+#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
+ ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_All
+ * @{
+ */
+#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
+#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
+ ((CMD) == ETH_RECEIVEAll_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Source_Addr_Filter
+ * @{
+ */
+#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
+#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
+#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
+ ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
+ ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Pass_Control_Frames
+ * @{
+ */
+#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */
+#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */
+#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
+ ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
+ ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Broadcast_Frames_Reception
+ * @{
+ */
+#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
+#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
+#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
+ ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Destination_Addr_Filter
+ * @{
+ */
+#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
+#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
+#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
+ ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Promiscuous_Mode
+ * @{
+ */
+#define ETH_PROMISCIOUSMODE_ENABLE ((uint32_t)0x00000001)
+#define ETH_PROMISCIOUSMODE_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_PROMISCIOUS_MODE(CMD) (((CMD) == ETH_PROMISCIOUSMODE_ENABLE) || \
+ ((CMD) == ETH_PROMISCIOUSMODE_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Multicast_Frames_Filter
+ * @{
+ */
+#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
+#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
+#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
+#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
+#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Unicast_Frames_Filter
+ * @{
+ */
+#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
+#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
+#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
+#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
+ ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
+ ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Pause_Time
+ * @{
+ */
+#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Zero_Quanta_Pause
+ * @{
+ */
+#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
+#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
+#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
+ ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Pause_Low_Threshold
+ * @{
+ */
+#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */
+#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Unicast_Pause_Frame_Detect
+ * @{
+ */
+#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
+#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
+ ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_Flow_Control
+ * @{
+ */
+#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
+#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
+ ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Transmit_Flow_Control
+ * @{
+ */
+#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
+#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
+ ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_VLAN_Tag_Comparison
+ * @{
+ */
+#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
+#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
+#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
+ ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
+#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_addresses
+ * @{
+ */
+#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
+#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
+#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
+#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
+#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS1) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS2) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS3))
+#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS2) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS3))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_addresses_filter_SA_DA_filed_of_received_frames
+ * @{
+ */
+#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
+#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
+#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
+ ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_addresses_filter_Mask_bytes
+ * @{
+ */
+#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */
+#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */
+#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */
+#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */
+#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */
+#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */
+#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_Debug_flags
+ * @{
+ */
+#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
+
+#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
+
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
+
+#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
+
+#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
+
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
+
+#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
+
+#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
+#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
+
+#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */
+#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */
+#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
+
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
+
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
+
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_AVTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame
+ * @{
+ */
+#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
+#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
+#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
+ ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_Store_Forward
+ * @{
+ */
+#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
+#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
+ ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Flush_Received_Frame
+ * @{
+ */
+#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
+#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
+#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
+ ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Transmit_Store_Forward
+ * @{
+ */
+#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
+#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
+ ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Transmit_Threshold_Control
+ * @{
+ */
+#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Forward_Error_Frames
+ * @{
+ */
+#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
+#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
+ ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Forward_Undersized_Good_Frames
+ * @{
+ */
+#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
+#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
+ ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_Threshold_Control
+ * @{
+ */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
+#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Second_Frame_Operate
+ * @{
+ */
+#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
+#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
+ ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Address_Aligned_Beats
+ * @{
+ */
+#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
+#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
+ ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Fixed_Burst
+ * @{
+ */
+#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
+#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
+#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
+ ((CMD) == ETH_FIXEDBURST_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Rx_DMA_Burst_Length
+ * @{
+ */
+#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
+
+#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Tx_DMA_Burst_Length
+ * @{
+ */
+#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+
+#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
+
+/** @defgroup ETH_DMA_Enhanced_descriptor_format
+ * @{
+ */
+#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)
+#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)
+
+#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
+ ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
+
+/**
+ * @}
+ */
+
+/**
+ * @brief ETH DMA Descriptor SkipLength
+ */
+#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
+
+
+/** @defgroup ETH_DMA_Arbitration
+ * @{
+ */
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
+#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
+#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
+ ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Tx_descriptor_flags
+ * @{
+ */
+#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
+ ((FLAG) == ETH_DMATXDESC_IC) || \
+ ((FLAG) == ETH_DMATXDESC_LS) || \
+ ((FLAG) == ETH_DMATXDESC_FS) || \
+ ((FLAG) == ETH_DMATXDESC_DC) || \
+ ((FLAG) == ETH_DMATXDESC_DP) || \
+ ((FLAG) == ETH_DMATXDESC_TTSE) || \
+ ((FLAG) == ETH_DMATXDESC_TER) || \
+ ((FLAG) == ETH_DMATXDESC_TCH) || \
+ ((FLAG) == ETH_DMATXDESC_TTSS) || \
+ ((FLAG) == ETH_DMATXDESC_IHE) || \
+ ((FLAG) == ETH_DMATXDESC_ES) || \
+ ((FLAG) == ETH_DMATXDESC_JT) || \
+ ((FLAG) == ETH_DMATXDESC_FF) || \
+ ((FLAG) == ETH_DMATXDESC_PCE) || \
+ ((FLAG) == ETH_DMATXDESC_LCA) || \
+ ((FLAG) == ETH_DMATXDESC_NC) || \
+ ((FLAG) == ETH_DMATXDESC_LCO) || \
+ ((FLAG) == ETH_DMATXDESC_EC) || \
+ ((FLAG) == ETH_DMATXDESC_VF) || \
+ ((FLAG) == ETH_DMATXDESC_CC) || \
+ ((FLAG) == ETH_DMATXDESC_ED) || \
+ ((FLAG) == ETH_DMATXDESC_UF) || \
+ ((FLAG) == ETH_DMATXDESC_DB))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Tx_descriptor_segment
+ * @{
+ */
+#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /*!< Last Segment */
+#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /*!< First Segment */
+#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
+ ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control
+ * @{
+ */
+#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /*!< Checksum engine bypass */
+#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */
+#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
+#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
+#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
+/**
+ * @brief ETH DMA Tx Desciptor buffer size
+ */
+#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Rx_descriptor_flags
+ * @{
+ */
+#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
+ ((FLAG) == ETH_DMARXDESC_AFM) || \
+ ((FLAG) == ETH_DMARXDESC_ES) || \
+ ((FLAG) == ETH_DMARXDESC_DE) || \
+ ((FLAG) == ETH_DMARXDESC_SAF) || \
+ ((FLAG) == ETH_DMARXDESC_LE) || \
+ ((FLAG) == ETH_DMARXDESC_OE) || \
+ ((FLAG) == ETH_DMARXDESC_VLAN) || \
+ ((FLAG) == ETH_DMARXDESC_FS) || \
+ ((FLAG) == ETH_DMARXDESC_LS) || \
+ ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
+ ((FLAG) == ETH_DMARXDESC_LC) || \
+ ((FLAG) == ETH_DMARXDESC_FT) || \
+ ((FLAG) == ETH_DMARXDESC_RWT) || \
+ ((FLAG) == ETH_DMARXDESC_RE) || \
+ ((FLAG) == ETH_DMARXDESC_DBE) || \
+ ((FLAG) == ETH_DMARXDESC_CE) || \
+ ((FLAG) == ETH_DMARXDESC_MAMPCE))
+
+/* ETHERNET DMA PTP Rx descriptor extended flags --------------------------------*/
+#define IS_ETH_DMAPTPRXDESC_GET_EXTENDED_FLAG(FLAG) (((FLAG) == ETH_DMAPTPRXDESC_PTPV) || \
+ ((FLAG) == ETH_DMAPTPRXDESC_PTPFT) || \
+ ((FLAG) == ETH_DMAPTPRXDESC_PTPMT) || \
+ ((FLAG) == ETH_DMAPTPRXDESC_IPV6PR) || \
+ ((FLAG) == ETH_DMAPTPRXDESC_IPV4PR) || \
+ ((FLAG) == ETH_DMAPTPRXDESC_IPCB) || \
+ ((FLAG) == ETH_DMAPTPRXDESC_IPPE) || \
+ ((FLAG) == ETH_DMAPTPRXDESC_IPHE) || \
+ ((FLAG) == ETH_DMAPTPRXDESC_IPPT))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Rx_descriptor_buffers_
+ * @{
+ */
+#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */
+#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */
+#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
+ ((BUFFER) == ETH_DMARXDESC_BUFFER2))
+
+
+/* ETHERNET DMA Tx descriptors Collision Count Shift */
+#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
+
+/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
+#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
+
+/* ETHERNET DMA Rx descriptors Frame Length Shift */
+#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
+
+/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
+#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
+
+/* ETHERNET DMA Rx descriptors Frame length Shift */
+#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_PMT_Flags
+ * @{
+ */
+#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */
+#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */
+#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
+ ((FLAG) == ETH_PMT_FLAG_MPR))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MMC_Tx_Interrupts
+ * @{
+ */
+#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */
+#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */
+#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MMC_Rx_Interrupts
+ * @{
+ */
+#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */
+#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */
+#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
+ ((IT) != 0x00))
+#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
+ ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
+ ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MMC_Registers
+ * @{
+ */
+#define ETH_MMCCR ((uint32_t)0x00000100) /*!< MMC CR register */
+#define ETH_MMCRIR ((uint32_t)0x00000104) /*!< MMC RIR register */
+#define ETH_MMCTIR ((uint32_t)0x00000108) /*!< MMC TIR register */
+#define ETH_MMCRIMR ((uint32_t)0x0000010C) /*!< MMC RIMR register */
+#define ETH_MMCTIMR ((uint32_t)0x00000110) /*!< MMC TIMR register */
+#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /*!< MMC TGFSCCR register */
+#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /*!< MMC TGFMSCCR register */
+#define ETH_MMCTGFCR ((uint32_t)0x00000168) /*!< MMC TGFCR register */
+#define ETH_MMCRFCECR ((uint32_t)0x00000194) /*!< MMC RFCECR register */
+#define ETH_MMCRFAECR ((uint32_t)0x00000198) /*!< MMC RFAECR register */
+#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /*!< MMC RGUFCR register */
+
+/**
+ * @brief ETH MMC registers
+ */
+#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) || ((REG) == ETH_MMCRIR) || \
+ ((REG) == ETH_MMCTIR) || ((REG) == ETH_MMCRIMR) || \
+ ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \
+ ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \
+ ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \
+ ((REG) == ETH_MMCRGUFCR))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_Flags
+ * @{
+ */
+#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */
+#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */
+#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */
+#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */
+#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */
+#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
+ ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
+ ((FLAG) == ETH_MAC_FLAG_PMT))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Flags
+ * @{
+ */
+#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
+#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
+#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */
+#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */
+#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */
+#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */
+#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */
+#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */
+#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */
+#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */
+#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */
+#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */
+#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */
+#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */
+#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */
+#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */
+#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */
+#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */
+#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */
+
+#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
+#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
+ ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
+ ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
+ ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
+ ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
+ ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
+ ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
+ ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
+ ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
+ ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
+ ((FLAG) == ETH_DMA_FLAG_T))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_Interrupts
+ * @{
+ */
+#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */
+#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */
+#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */
+#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */
+#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */
+#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00))
+#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
+ ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
+ ((IT) == ETH_MAC_IT_PMT))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Interrupts
+ * @{
+ */
+#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
+#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
+#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */
+#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */
+#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */
+#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */
+#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */
+#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */
+#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */
+#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */
+#define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */
+#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */
+#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */
+#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */
+#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */
+#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */
+#define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */
+
+#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
+#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
+ ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
+ ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
+ ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
+ ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
+ ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
+ ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
+ ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
+ ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_transmit_process_state_
+ * @{
+ */
+#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */
+#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */
+#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /*!< Running - waiting for status */
+#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */
+#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /*!< Suspended - Tx Descriptor unavailable */
+#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup ETH_DMA_receive_process_state_
+ * @{
+ */
+#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */
+#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */
+#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /*!< Running - waiting for packet */
+#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /*!< Suspended - Rx Descriptor unavailable */
+#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /*!< Running - closing descriptor */
+#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /*!< Running - queuing the receive frame into host memory */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_overflow_
+ * @{
+ */
+#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */
+#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */
+#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
+ ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
+/**
+ * @}
+ */
+
+/* ETHERNET MAC address offsets */
+#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
+#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
+
+/* ETHERNET MACMIIAR register Mask */
+#define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
+
+/* ETHERNET MACCR register Mask */
+#define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
+
+/* ETHERNET MACFCR register Mask */
+#define MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
+
+
+/* ETHERNET DMAOMR register Mask */
+#define DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
+
+
+/* ETHERNET Remote Wake-up frame register length */
+#define ETH_WAKEUP_REGISTER_LENGTH 8
+
+/* ETHERNET Missed frames counter Shift */
+#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset ETH handle state
+ * @param __HANDLE__: specifies the ETH handle.
+ * @retval None
+ */
+#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
+ * @param __HANDLE__: ETH Handle
+ * @param __FLAG__: specifies the flag to check.
+ * @retval the ETH_DMATxDescFlag (SET or RESET).
+ */
+#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
+ * @param __HANDLE__: ETH Handle
+ * @param __FLAG__: specifies the flag to check.
+ * @retval the ETH_DMATxDescFlag (SET or RESET).
+ */
+#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
+
+/**
+ * @brief Enables the specified DMA Rx Desc receive interrupt.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
+
+/**
+ * @brief Disables the specified DMA Rx Desc receive interrupt.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
+
+/**
+ * @brief Set the specified DMA Rx Desc Own bit.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
+
+/**
+ * @brief Returns the specified ETHERNET DMA Tx Desc collision count.
+ * @param __HANDLE__: ETH Handle
+ * @retval The Transmit descriptor collision counter value.
+ */
+#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
+
+/**
+ * @brief Set the specified DMA Tx Desc Own bit.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
+
+/**
+ * @brief Enables the specified DMA Tx Desc Transmit interrupt.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
+
+/**
+ * @brief Disables the specified DMA Tx Desc Transmit interrupt.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
+
+/**
+ * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
+ * @param __HANDLE__: ETH Handle
+ * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
+ * This parameter can be one of the following values:
+ * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
+ * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
+ * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
+ * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
+
+/**
+ * @brief Enables the DMA Tx Desc CRC.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
+
+/**
+ * @brief Disables the DMA Tx Desc CRC.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
+
+/**
+ * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
+
+/**
+ * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
+
+/**
+ * @brief Enables the specified ETHERNET MAC interrupts.
+ * @param __HANDLE__ : ETH Handle
+ * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
+ * enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
+ * @arg ETH_MAC_IT_PMT : PMT interrupt
+ * @retval None
+ */
+#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified ETHERNET MAC interrupts.
+ * @param __HANDLE__ : ETH Handle
+ * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
+ * enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
+ * @arg ETH_MAC_IT_PMT : PMT interrupt
+ * @retval None
+ */
+#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Initiate a Pause Control Frame (Full-duplex only).
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
+
+/**
+ * @brief Checks whether the ETHERNET flow control busy bit is set or not.
+ * @param __HANDLE__: ETH Handle
+ * @retval The new state of flow control busy status bit (SET or RESET).
+ */
+#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
+
+/**
+ * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
+
+/**
+ * @brief Disables the MAC BackPressure operation activation (Half-duplex only).
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
+
+/**
+ * @brief Checks whether the specified ETHERNET MAC flag is set or not.
+ * @param __HANDLE__: ETH Handle
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
+ * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
+ * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
+ * @arg ETH_MAC_FLAG_MMC : MMC flag
+ * @arg ETH_MAC_FLAG_PMT : PMT flag
+ * @retval The state of ETHERNET MAC flag.
+ */
+#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
+
+/**
+ * @brief Clears the specified ETHERNET MAC flag.
+ * @param __HANDLE__: ETH Handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
+ * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
+ * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
+ * @arg ETH_MAC_FLAG_MMC : MMC flag
+ * @arg ETH_MAC_FLAG_PMT : PMT flag
+ * @retval None.
+ */
+#define __HAL_ETH_MAC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->MACSR &= ~(__FLAG__))
+
+/**
+ * @brief Enables the specified ETHERNET DMA interrupts.
+ * @param __HANDLE__ : ETH Handle
+ * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
+ * enabled @defgroup ETH_DMA_Interrupts
+ * @retval None
+ */
+#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified ETHERNET DMA interrupts.
+ * @param __HANDLE__ : ETH Handle
+ * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
+ * disabled. @defgroup ETH_DMA_Interrupts
+ * @retval None
+ */
+#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
+
+/**
+ * @brief Clears the ETHERNET DMA IT pending bit.
+ * @param __HANDLE__ : ETH Handle
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @defgroup ETH_DMA_Interrupts
+ * @retval None
+ */
+#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA flag is set or not.
+* @param __HANDLE__: ETH Handle
+ * @param __FLAG__: specifies the flag to check.
+ * @retval The new state of ETH_DMA_FLAG (SET or RESET).
+ */
+#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA flag is set or not.
+ * @param __HANDLE__: ETH Handle
+ * @param __FLAG__: specifies the flag to clear.
+ * @retval The new state of ETH_DMA_FLAG (SET or RESET).
+ */
+#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR &= ~(__FLAG__))
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
+ * @param __HANDLE__: ETH Handle
+ * @param __OVERFLOW__: specifies the DMA overflow flag to check.
+ * This parameter can be one of the following values:
+ * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
+ * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
+ * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
+ */
+#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
+
+/**
+ * @brief Set the DMA Receive status watchdog timer register value
+ * @param __HANDLE__: ETH Handle
+ * @param __VALUE__: DMA Receive status watchdog timer register value
+ * @retval None
+ */
+#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
+
+/**
+ * @brief Enables any unicast packet filtered by the MAC address
+ * recognition to be a wake-up frame.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
+
+/**
+ * @brief Disables any unicast packet filtered by the MAC address
+ * recognition to be a wake-up frame.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
+
+/**
+ * @brief Enables the MAC Wake-Up Frame Detection.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
+
+/**
+ * @brief Disables the MAC Wake-Up Frame Detection.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
+
+/**
+ * @brief Enables the MAC Magic Packet Detection.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
+
+/**
+ * @brief Disables the MAC Magic Packet Detection.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
+
+/**
+ * @brief Enables the MAC Power Down.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
+
+/**
+ * @brief Disables the MAC Power Down.
+ * @param __HANDLE__: ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
+
+/**
+ * @brief Checks whether the specified ETHERNET PMT flag is set or not.
+ * @param __HANDLE__: ETH Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
+ * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
+ * @arg ETH_PMT_FLAG_MPR : Magic Packet Received
+ * @retval The new state of ETHERNET PMT Flag (SET or RESET).
+ */
+#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
+
+/**
+ * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
+
+/**
+ * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
+ (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
+
+/**
+ * @brief Enables the MMC Counter Freeze.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
+
+/**
+ * @brief Disables the MMC Counter Freeze.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
+
+/**
+ * @brief Enables the MMC Reset On Read.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
+
+/**
+ * @brief Disables the MMC Reset On Read.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
+
+/**
+ * @brief Enables the MMC Counter Stop Rollover.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
+
+/**
+ * @brief Disables the MMC Counter Stop Rollover.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
+
+/**
+ * @brief Resets the MMC Counters.
+ * @param __HANDLE__: ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
+
+/**
+ * @brief Enables the specified ETHERNET MMC Rx interrupts.
+ * @param __HANDLE__: ETH Handle.
+ * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
+ * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
+ * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
+ * @retval None
+ */
+#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
+/**
+ * @brief Disables the specified ETHERNET MMC Rx interrupts.
+ * @param __HANDLE__: ETH Handle.
+ * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
+ * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
+ * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
+ * @retval None
+ */
+#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)
+/**
+ * @brief Enables the specified ETHERNET MMC Tx interrupts.
+ * @param __HANDLE__: ETH Handle.
+ * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
+ * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
+ * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
+ * @retval None
+ */
+#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified ETHERNET MMC Tx interrupts.
+ * @param __HANDLE__: ETH Handle.
+ * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
+ * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
+ * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
+ * @retval None
+ */
+#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
+
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
+void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
+void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
+HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
+
+/* IO operation functions ****************************************************/
+HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
+
+ /* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
+void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
+
+ /* Callback in non blocking modes (Interrupt) */
+void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
+void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
+void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
+
+/* Cmmunication with PHY functions*/
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
+
+/* Peripheral Control functions **********************************************/
+HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
+
+HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
+HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
+
+/* Peripheral State functions ************************************************/
+HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_ETH_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_flash.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,362 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_flash.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of FLASH HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_FLASH_H
+#define __STM32F4xx_HAL_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/**
+ * @brief FLASH Error structure definition
+ */
+typedef enum
+{
+ FLASH_ERROR_RD = 0x01,
+ FLASH_ERROR_PGS = 0x02,
+ FLASH_ERROR_PGP = 0x04,
+ FLASH_ERROR_PGA = 0x08,
+ FLASH_ERROR_WRP = 0x10,
+ FLASH_ERROR_OPERATION = 0x20
+}FLASH_ErrorTypeDef;
+
+/**
+ * @brief FLASH Procedure structure definition
+ */
+typedef enum
+{
+ FLASH_PROC_NONE = 0,
+ FLASH_PROC_SECTERASE,
+ FLASH_PROC_MASSERASE,
+ FLASH_PROC_PROGRAM
+} FLASH_ProcedureTypeDef;
+
+
+/**
+ * @brief FLASH handle Structure definition
+ */
+typedef struct
+{
+ __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*Internal variable to indicate which procedure is ongoing or not in IT context*/
+
+ __IO uint32_t NbSectorsToErase; /*Internal variable to save the remaining sectors to erase in IT context*/
+
+ __IO uint8_t VoltageForErase; /*Internal variable to provide voltange range selected by user in IT context*/
+
+ __IO uint32_t Sector; /*Internal variable to define the current sector which is erasing*/
+
+ __IO uint32_t Bank; /*Internal variable to save current bank selected during mass erase*/
+
+ __IO uint32_t Address; /*Internal variable to save address selected for program*/
+
+ HAL_LockTypeDef Lock; /* FLASH locking object */
+
+ __IO FLASH_ErrorTypeDef ErrorCode; /* FLASH error code */
+
+}FLASH_ProcessTypeDef;
+
+/**
+ * @brief FLASH Error source
+ */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
+ * @{
+ */
+
+
+
+/** @defgroup FLASH_Type_Program FLASH Type Program
+ * @{
+ */
+#define TYPEPROGRAM_BYTE ((uint32_t)0x00) /*!< Program byte (8-bit) at a specified address */
+#define TYPEPROGRAM_HALFWORD ((uint32_t)0x01) /*!< Program a half-word (16-bit) at a specified address */
+#define TYPEPROGRAM_WORD ((uint32_t)0x02) /*!< Program a word (32-bit) at a specified address */
+#define TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03) /*!< Program a double word (64-bit) at a specified address */
+
+#define IS_TYPEPROGRAM(VALUE)(((VALUE) == TYPEPROGRAM_BYTE) || \
+ ((VALUE) == TYPEPROGRAM_HALFWORD) || \
+ ((VALUE) == TYPEPROGRAM_WORD) || \
+ ((VALUE) == TYPEPROGRAM_DOUBLEWORD))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Flag_definition FLASH Flag definition
+ * @brief Flag definition
+ * @{
+ */
+#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */
+#define FLASH_FLAG_OPERR FLASH_SR_SOP /*!< FLASH operation Error flag */
+#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */
+#define FLASH_FLAG_PGPERR FLASH_SR_PGPERR /*!< FLASH Programming Parallelism error flag */
+#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming Sequence error flag */
+#define FLASH_FLAG_RDERR ((uint32_t)0x00000100) /*!< Read Protection error flag (PCROP) */
+#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
+ * @brief FLASH Interrupt definition
+ * @{
+ */
+#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
+#define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
+ * @{
+ */
+#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000)
+#define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100)
+#define FLASH_PSIZE_WORD ((uint32_t)0x00000200)
+#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300)
+#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF)
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Keys FLASH Keys
+ * @{
+ */
+#define RDP_KEY ((uint16_t)0x00A5)
+#define FLASH_KEY1 ((uint32_t)0x45670123)
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
+#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B)
+#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F)
+/**
+ * @}
+ */
+
+/**
+ * @brief ACR register byte 0 (Bits[7:0]) base address
+ */
+#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
+/**
+ * @brief OPTCR register byte 0 (Bits[7:0]) base address
+ */
+#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14)
+/**
+ * @brief OPTCR register byte 1 (Bits[15:8]) base address
+ */
+#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15)
+/**
+ * @brief OPTCR register byte 2 (Bits[23:16]) base address
+ */
+#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16)
+/**
+ * @brief OPTCR register byte 3 (Bits[31:24]) base address
+ */
+#define OPTCR_BYTE3_ADDRESS ((uint32_t)0x40023C17)
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/**
+ * @brief Set the FLASH Latency.
+ * @param __LATENCY__: FLASH Latency
+ * The value of this parameter depend on device used within the same series
+ * @retval none
+ */
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (*(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)(__LATENCY__))
+
+/**
+ * @brief Enable the FLASH prefetch buffer.
+ * @retval none
+ */
+#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN)
+
+/**
+ * @brief Disable the FLASH prefetch buffer.
+ * @retval none
+ */
+#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN))
+
+/**
+ * @brief Enable the FLASH instruction cache.
+ * @retval none
+ */
+#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_ICEN)
+
+/**
+ * @brief Disable the FLASH instruction cache.
+ * @retval none
+ */
+#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_ICEN))
+
+/**
+ * @brief Enable the FLASH data cache.
+ * @retval none
+ */
+#define __HAL_FLASH_DATA_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_DCEN)
+
+/**
+ * @brief Disable the FLASH data cache.
+ * @retval none
+ */
+#define __HAL_FLASH_DATA_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_DCEN))
+
+/**
+ * @brief Resets the FLASH instruction Cache.
+ * @note This function must be used only when the Instruction Cache is disabled.
+ * @retval None
+ */
+#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() (FLASH->ACR |= FLASH_ACR_ICRST)
+
+/**
+ * @brief Resets the FLASH data Cache.
+ * @note This function must be used only when the data Cache is disabled.
+ * @retval None
+ */
+#define __HAL_FLASH_DATA_CACHE_RESET() (FLASH->ACR |= FLASH_ACR_DCRST)
+
+/**
+ * @brief Enable the specified FLASH interrupt.
+ * @param __INTERRUPT__ : FLASH interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+ * @arg FLASH_IT_ERR: Error Interrupt
+ * @retval none
+ */
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified FLASH interrupt.
+ * @param __INTERRUPT__ : FLASH interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+ * @arg FLASH_IT_ERR: Error Interrupt
+ * @retval none
+ */
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))
+
+/**
+ * @brief Get the specified FLASH flag status.
+ * @param __FLAG__: specifies the FLASH flag to check.
+ * This parameter can be one of the following values:
+ * @arg FLASH_FLAG_EOP : FLASH End of Operation flag
+ * @arg FLASH_FLAG_OPERR : FLASH operation Error flag
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
+ * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
+ * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
+ * @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP)
+ * @arg FLASH_FLAG_BSY : FLASH Busy flag
+ * @retval The new state of __FLAG__ (SET or RESET).
+ */
+#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__)))
+
+/**
+ * @brief Clear the specified FLASH flag.
+ * @param __FLAG__: specifies the FLASH flags to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_FLAG_EOP : FLASH End of Operation flag
+ * @arg FLASH_FLAG_OPERR : FLASH operation Error flag
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
+ * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
+ * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
+ * @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP)
+ * @retval none
+ */
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__))
+
+/* Include FLASH HAL Extension module */
+#include "stm32f4xx_hal_flash_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/* Program operation functions ***********************************************/
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+/* FLASH IRQ handler method */
+void HAL_FLASH_IRQHandler(void);
+/* Callbacks in non blocking modes */
+void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
+void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
+
+/* Peripheral Control functions **********************************************/
+HAL_StatusTypeDef HAL_FLASH_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
+/* Option bytes control */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
+
+/* Peripheral State functions ************************************************/
+FLASH_ErrorTypeDef HAL_FLASH_GetError(void);
+
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_FLASH_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_flash_ex.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,735 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_flash_ex.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of FLASH HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_FLASH_EX_H
+#define __STM32F4xx_HAL_FLASH_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FLASHEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief FLASH Erase structure definition
+ */
+typedef struct
+{
+ uint32_t TypeErase; /*!< Mass erase or sector Erase.
+ This parameter can be a value of @ref FLASHEx_Type_Erase */
+
+ uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
+ This parameter must be a value of @ref FLASHEx_Banks */
+
+ uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled
+ This parameter must be a value of @ref FLASHEx_Sectors */
+
+ uint32_t NbSectors; /*!< Number of sectors to be erased.
+ This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
+
+ uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
+ This parameter must be a value of @ref FLASHEx_Voltage_Range */
+
+} FLASH_EraseInitTypeDef;
+
+/**
+ * @brief FLASH Option Bytes Program structure definition
+ */
+typedef struct
+{
+ uint32_t OptionType; /*!< Option byte to be configured.
+ This parameter can be a value of @ref FLASHEx_Option_Type */
+
+ uint32_t WRPState; /*!< Write protection activation or deactivation.
+ This parameter can be a value of @ref FLASHEx_WRP_State */
+
+ uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected.
+ The value of this parameter depend on device used within the same series */
+
+ uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors.
+ This parameter must be a value of @ref FLASHEx_Banks */
+
+ uint32_t RDPLevel; /*!< Set the read protection level.
+ This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
+
+ uint32_t BORLevel; /*!< Set the BOR Level.
+ This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
+
+ uint8_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. */
+
+} FLASH_OBProgramInitTypeDef;
+
+/**
+ * @brief FLASH Advanced Option Bytes Program structure definition
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE)
+typedef struct
+{
+ uint32_t OptionType; /*!< Option byte to be configured for extension.
+ This parameter can be a value of @ref FLASHEx_Advanced_Option_Type */
+
+ uint32_t PCROPState; /*!< PCROP activation or deactivation.
+ This parameter can be a value of @ref FLASHEx_PCROP_State */
+
+#if defined (STM32F401xC) || defined (STM32F401xE)
+ uint16_t Sectors; /*!< specifies the sector(s) set for PCROP.
+ This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
+#endif /* STM32F401xC || STM32F401xE */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ uint32_t Banks; /*!< Select banks for PCROP activation/deactivation of all sectors.
+ This parameter must be a value of @ref FLASHEx_Banks */
+
+ uint16_t SectorsBank1; /*!< Specifies the sector(s) set for PCROP for Bank1.
+ This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
+
+ uint16_t SectorsBank2; /*!< Specifies the sector(s) set for PCROP for Bank2.
+ This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
+
+ uint8_t BootConfig; /*!< Specifies Option bytes for boot config.
+ This parameter can be a value of @ref FLASHEx_Dual_Boot */
+
+#endif /*STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+} FLASH_AdvOBProgramInitTypeDef;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
+ * @{
+ */
+
+/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
+ * @{
+ */
+#define TYPEERASE_SECTORS ((uint32_t)0x00) /*!< Sectors erase only */
+#define TYPEERASE_MASSERASE ((uint32_t)0x01) /*!< Flash Mass erase activation */
+
+#define IS_TYPEERASE(VALUE)(((VALUE) == TYPEERASE_SECTORS) || \
+ ((VALUE) == TYPEERASE_MASSERASE))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
+ * @{
+ */
+#define VOLTAGE_RANGE_1 ((uint32_t)0x00) /*!< Device operating range: 1.8V to 2.1V */
+#define VOLTAGE_RANGE_2 ((uint32_t)0x01) /*!< Device operating range: 2.1V to 2.7V */
+#define VOLTAGE_RANGE_3 ((uint32_t)0x02) /*!< Device operating range: 2.7V to 3.6V */
+#define VOLTAGE_RANGE_4 ((uint32_t)0x03) /*!< Device operating range: 2.7V to 3.6V + External Vpp */
+
+#define IS_VOLTAGERANGE(RANGE)(((RANGE) == VOLTAGE_RANGE_1) || \
+ ((RANGE) == VOLTAGE_RANGE_2) || \
+ ((RANGE) == VOLTAGE_RANGE_3) || \
+ ((RANGE) == VOLTAGE_RANGE_4))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_WRP_State FLASH WRP State
+ * @{
+ */
+#define WRPSTATE_DISABLE ((uint32_t)0x00) /*!< Disable the write protection of the desired bank 1 sectors */
+#define WRPSTATE_ENABLE ((uint32_t)0x01) /*!< Enable the write protection of the desired bank 1 sectors */
+
+#define IS_WRPSTATE(VALUE)(((VALUE) == WRPSTATE_DISABLE) || \
+ ((VALUE) == WRPSTATE_ENABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Option_Type FLASH Option Type
+ * @{
+ */
+#define OPTIONBYTE_WRP ((uint32_t)0x01) /*!< WRP option byte configuration */
+#define OPTIONBYTE_RDP ((uint32_t)0x02) /*!< RDP option byte configuration */
+#define OPTIONBYTE_USER ((uint32_t)0x04) /*!< USER option byte configuration */
+#define OPTIONBYTE_BOR ((uint32_t)0x08) /*!< BOR option byte configuration */
+
+#define IS_OPTIONBYTE(VALUE)(((VALUE) < (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
+ * @{
+ */
+#define OB_RDP_LEVEL_0 ((uint8_t)0xAA)
+#define OB_RDP_LEVEL_1 ((uint8_t)0x55)
+/*#define OB_RDP_LEVEL_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2
+ it s no more possible to go back to level 1 or 0 */
+#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
+ ((LEVEL) == OB_RDP_LEVEL_1))/*||\
+ ((LEVEL) == OB_RDP_LEVEL_2))*/
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
+ * @{
+ */
+#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */
+#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
+ * @{
+ */
+#define OB_STOP_NO_RST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
+/**
+ * @}
+ */
+
+
+/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
+ * @{
+ */
+#define OB_STDBY_NO_RST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
+ * @{
+ */
+#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */
+#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */
+#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */
+#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */
+#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
+ ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
+/**
+ * @}
+ */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE)
+/** @defgroup FLASHEx_PCROP_State FLASH PCROP State
+ * @{
+ */
+#define PCROPSTATE_DISABLE ((uint32_t)0x00) /*!< Disable PCROP */
+#define PCROPSTATE_ENABLE ((uint32_t)0x01) /*!< Enable PCROP */
+
+#define IS_PCROPSTATE(VALUE)(((VALUE) == PCROPSTATE_DISABLE) || \
+ ((VALUE) == PCROPSTATE_ENABLE))
+
+/**
+ * @}
+ */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE */
+
+/** @defgroup FLASHEx_Advanced_Option_Type FLASH Advanced Option Type
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#define OBEX_PCROP ((uint32_t)0x01) /*!< PCROP option byte configuration */
+#define OBEX_BOOTCONFIG ((uint32_t)0x02) /*!< BOOTConfig option byte configuration */
+
+#define IS_OBEX(VALUE)(((VALUE) == OBEX_PCROP) || \
+ ((VALUE) == OBEX_BOOTCONFIG))
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F401xC) || defined(STM32F401xE)
+#define OBEX_PCROP ((uint32_t)0x01) /*!<PCROP option byte configuration */
+
+#define IS_OBEX(VALUE)(((VALUE) == OBEX_PCROP))
+
+#endif /* STM32F401xC || STM32F401xE */
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Latency FLASH Latency
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */
+#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */
+#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */
+#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */
+#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */
+#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */
+#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */
+#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */
+#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycles */
+#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycles */
+#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */
+#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */
+#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */
+#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */
+#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */
+#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */
+
+
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
+ ((LATENCY) == FLASH_LATENCY_1) || \
+ ((LATENCY) == FLASH_LATENCY_2) || \
+ ((LATENCY) == FLASH_LATENCY_3) || \
+ ((LATENCY) == FLASH_LATENCY_4) || \
+ ((LATENCY) == FLASH_LATENCY_5) || \
+ ((LATENCY) == FLASH_LATENCY_6) || \
+ ((LATENCY) == FLASH_LATENCY_7) || \
+ ((LATENCY) == FLASH_LATENCY_8) || \
+ ((LATENCY) == FLASH_LATENCY_9) || \
+ ((LATENCY) == FLASH_LATENCY_10) || \
+ ((LATENCY) == FLASH_LATENCY_11) || \
+ ((LATENCY) == FLASH_LATENCY_12) || \
+ ((LATENCY) == FLASH_LATENCY_13) || \
+ ((LATENCY) == FLASH_LATENCY_14) || \
+ ((LATENCY) == FLASH_LATENCY_15))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE)
+#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */
+#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */
+#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */
+#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */
+#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */
+#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */
+#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */
+#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */
+
+
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
+ ((LATENCY) == FLASH_LATENCY_1) || \
+ ((LATENCY) == FLASH_LATENCY_2) || \
+ ((LATENCY) == FLASH_LATENCY_3) || \
+ ((LATENCY) == FLASH_LATENCY_4) || \
+ ((LATENCY) == FLASH_LATENCY_5) || \
+ ((LATENCY) == FLASH_LATENCY_6) || \
+ ((LATENCY) == FLASH_LATENCY_7))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FLASHEx_Banks FLASH Banks
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define FLASH_BANK_1 ((uint32_t)1) /*!< Bank 1 */
+#define FLASH_BANK_2 ((uint32_t)2) /*!< Bank 2 */
+#define FLASH_BANK_BOTH ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */
+
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
+ ((BANK) == FLASH_BANK_2) || \
+ ((BANK) == FLASH_BANK_BOTH))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE)
+#define FLASH_BANK_1 ((uint32_t)1) /*!< Bank 1 */
+
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define FLASH_MER_BIT (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits here to clear */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE)
+#define FLASH_MER_BIT (FLASH_CR_MER) /*!< only 1 MER Bit */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Sectors FLASH Sectors
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */
+#define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */
+#define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */
+#define FLASH_SECTOR_3 ((uint32_t)3) /*!< Sector Number 3 */
+#define FLASH_SECTOR_4 ((uint32_t)4) /*!< Sector Number 4 */
+#define FLASH_SECTOR_5 ((uint32_t)5) /*!< Sector Number 5 */
+#define FLASH_SECTOR_6 ((uint32_t)6) /*!< Sector Number 6 */
+#define FLASH_SECTOR_7 ((uint32_t)7) /*!< Sector Number 7 */
+#define FLASH_SECTOR_8 ((uint32_t)8) /*!< Sector Number 8 */
+#define FLASH_SECTOR_9 ((uint32_t)9) /*!< Sector Number 9 */
+#define FLASH_SECTOR_10 ((uint32_t)10) /*!< Sector Number 10 */
+#define FLASH_SECTOR_11 ((uint32_t)11) /*!< Sector Number 11 */
+#define FLASH_SECTOR_12 ((uint32_t)12) /*!< Sector Number 12 */
+#define FLASH_SECTOR_13 ((uint32_t)13) /*!< Sector Number 13 */
+#define FLASH_SECTOR_14 ((uint32_t)14) /*!< Sector Number 14 */
+#define FLASH_SECTOR_15 ((uint32_t)15) /*!< Sector Number 15 */
+#define FLASH_SECTOR_16 ((uint32_t)16) /*!< Sector Number 16 */
+#define FLASH_SECTOR_17 ((uint32_t)17) /*!< Sector Number 17 */
+#define FLASH_SECTOR_18 ((uint32_t)18) /*!< Sector Number 18 */
+#define FLASH_SECTOR_19 ((uint32_t)19) /*!< Sector Number 19 */
+#define FLASH_SECTOR_20 ((uint32_t)20) /*!< Sector Number 20 */
+#define FLASH_SECTOR_21 ((uint32_t)21) /*!< Sector Number 21 */
+#define FLASH_SECTOR_22 ((uint32_t)22) /*!< Sector Number 22 */
+#define FLASH_SECTOR_23 ((uint32_t)23) /*!< Sector Number 23 */
+
+#define FLASH_SECTOR_TOTAL 24
+
+#define IS_FLASH_SECTOR(SECTOR) ( ((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
+ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
+ ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
+ ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\
+ ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\
+ ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11) ||\
+ ((SECTOR) == FLASH_SECTOR_12) || ((SECTOR) == FLASH_SECTOR_13) ||\
+ ((SECTOR) == FLASH_SECTOR_14) || ((SECTOR) == FLASH_SECTOR_15) ||\
+ ((SECTOR) == FLASH_SECTOR_16) || ((SECTOR) == FLASH_SECTOR_17) ||\
+ ((SECTOR) == FLASH_SECTOR_18) || ((SECTOR) == FLASH_SECTOR_19) ||\
+ ((SECTOR) == FLASH_SECTOR_20) || ((SECTOR) == FLASH_SECTOR_21) ||\
+ ((SECTOR) == FLASH_SECTOR_22) || ((SECTOR) == FLASH_SECTOR_23))
+
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x081FFFFF)) ||\
+ (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F)))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */
+#define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */
+#define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */
+#define FLASH_SECTOR_3 ((uint32_t)3) /*!< Sector Number 3 */
+#define FLASH_SECTOR_4 ((uint32_t)4) /*!< Sector Number 4 */
+#define FLASH_SECTOR_5 ((uint32_t)5) /*!< Sector Number 5 */
+#define FLASH_SECTOR_6 ((uint32_t)6) /*!< Sector Number 6 */
+#define FLASH_SECTOR_7 ((uint32_t)7) /*!< Sector Number 7 */
+#define FLASH_SECTOR_8 ((uint32_t)8) /*!< Sector Number 8 */
+#define FLASH_SECTOR_9 ((uint32_t)9) /*!< Sector Number 9 */
+#define FLASH_SECTOR_10 ((uint32_t)10) /*!< Sector Number 10 */
+#define FLASH_SECTOR_11 ((uint32_t)11) /*!< Sector Number 11 */
+
+#define FLASH_SECTOR_TOTAL 12
+
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
+ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
+ ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
+ ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\
+ ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\
+ ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11))
+
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\
+ (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F)))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F401xC)
+#define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */
+#define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */
+#define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */
+#define FLASH_SECTOR_3 ((uint32_t)3) /*!< Sector Number 3 */
+#define FLASH_SECTOR_4 ((uint32_t)4) /*!< Sector Number 4 */
+#define FLASH_SECTOR_5 ((uint32_t)5) /*!< Sector Number 5 */
+
+#define FLASH_SECTOR_TOTAL 6
+
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
+ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
+ ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5))
+
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0803FFFF)) ||\
+ (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F)))
+#endif /* STM32F401xC */
+
+#if defined(STM32F401xE)
+#define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */
+#define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */
+#define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */
+#define FLASH_SECTOR_3 ((uint32_t)3) /*!< Sector Number 3 */
+#define FLASH_SECTOR_4 ((uint32_t)4) /*!< Sector Number 4 */
+#define FLASH_SECTOR_5 ((uint32_t)5) /*!< Sector Number 5 */
+#define FLASH_SECTOR_6 ((uint32_t)6) /*!< Sector Number 6 */
+#define FLASH_SECTOR_7 ((uint32_t)7) /*!< Sector Number 7 */
+
+#define FLASH_SECTOR_TOTAL 8
+
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
+ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
+ ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
+ ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7))
+
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF)) ||\
+ (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F)))
+#endif /* STM32F401xE */
+
+#define IS_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define OB_WRP_SECTOR_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
+#define OB_WRP_SECTOR_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
+#define OB_WRP_SECTOR_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
+#define OB_WRP_SECTOR_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */
+#define OB_WRP_SECTOR_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */
+#define OB_WRP_SECTOR_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */
+#define OB_WRP_SECTOR_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */
+#define OB_WRP_SECTOR_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */
+#define OB_WRP_SECTOR_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */
+#define OB_WRP_SECTOR_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */
+#define OB_WRP_SECTOR_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */
+#define OB_WRP_SECTOR_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */
+#define OB_WRP_SECTOR_12 ((uint32_t)0x00000001 << 12) /*!< Write protection of Sector12 */
+#define OB_WRP_SECTOR_13 ((uint32_t)0x00000002 << 12) /*!< Write protection of Sector13 */
+#define OB_WRP_SECTOR_14 ((uint32_t)0x00000004 << 12) /*!< Write protection of Sector14 */
+#define OB_WRP_SECTOR_15 ((uint32_t)0x00000008 << 12) /*!< Write protection of Sector15 */
+#define OB_WRP_SECTOR_16 ((uint32_t)0x00000010 << 12) /*!< Write protection of Sector16 */
+#define OB_WRP_SECTOR_17 ((uint32_t)0x00000020 << 12) /*!< Write protection of Sector17 */
+#define OB_WRP_SECTOR_18 ((uint32_t)0x00000040 << 12) /*!< Write protection of Sector18 */
+#define OB_WRP_SECTOR_19 ((uint32_t)0x00000080 << 12) /*!< Write protection of Sector19 */
+#define OB_WRP_SECTOR_20 ((uint32_t)0x00000100 << 12) /*!< Write protection of Sector20 */
+#define OB_WRP_SECTOR_21 ((uint32_t)0x00000200 << 12) /*!< Write protection of Sector21 */
+#define OB_WRP_SECTOR_22 ((uint32_t)0x00000400 << 12) /*!< Write protection of Sector22 */
+#define OB_WRP_SECTOR_23 ((uint32_t)0x00000800 << 12) /*!< Write protection of Sector23 */
+#define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF << 12) /*!< Write protection of all Sectors */
+
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFF000000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#define OB_WRP_SECTOR_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
+#define OB_WRP_SECTOR_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
+#define OB_WRP_SECTOR_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
+#define OB_WRP_SECTOR_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */
+#define OB_WRP_SECTOR_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */
+#define OB_WRP_SECTOR_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */
+#define OB_WRP_SECTOR_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */
+#define OB_WRP_SECTOR_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */
+#define OB_WRP_SECTOR_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */
+#define OB_WRP_SECTOR_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */
+#define OB_WRP_SECTOR_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */
+#define OB_WRP_SECTOR_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */
+#define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
+
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F401xC)
+#define OB_WRP_SECTOR_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
+#define OB_WRP_SECTOR_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
+#define OB_WRP_SECTOR_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
+#define OB_WRP_SECTOR_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */
+#define OB_WRP_SECTOR_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */
+#define OB_WRP_SECTOR_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */
+#define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
+
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F401xC */
+
+#if defined(STM32F401xE)
+#define OB_WRP_SECTOR_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
+#define OB_WRP_SECTOR_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
+#define OB_WRP_SECTOR_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
+#define OB_WRP_SECTOR_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */
+#define OB_WRP_SECTOR_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */
+#define OB_WRP_SECTOR_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */
+#define OB_WRP_SECTOR_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */
+#define OB_WRP_SECTOR_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */
+#define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
+
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F401xE */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASH Option Bytes PC ReadWrite Protection
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */
+#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */
+#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */
+#define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3 */
+#define OB_PCROP_SECTOR_4 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4 */
+#define OB_PCROP_SECTOR_5 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5 */
+#define OB_PCROP_SECTOR_6 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector6 */
+#define OB_PCROP_SECTOR_7 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector7 */
+#define OB_PCROP_SECTOR_8 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector8 */
+#define OB_PCROP_SECTOR_9 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector9 */
+#define OB_PCROP_SECTOR_10 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector10 */
+#define OB_PCROP_SECTOR_11 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector11 */
+#define OB_PCROP_SECTOR_12 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector12 */
+#define OB_PCROP_SECTOR_13 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector13 */
+#define OB_PCROP_SECTOR_14 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector14 */
+#define OB_PCROP_SECTOR_15 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector15 */
+#define OB_PCROP_SECTOR_16 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector16 */
+#define OB_PCROP_SECTOR_17 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector17 */
+#define OB_PCROP_SECTOR_18 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector18 */
+#define OB_PCROP_SECTOR_19 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector19 */
+#define OB_PCROP_SECTOR_20 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector20 */
+#define OB_PCROP_SECTOR_21 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector21 */
+#define OB_PCROP_SECTOR_22 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector22 */
+#define OB_PCROP_SECTOR_23 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector23 */
+#define OB_PCROP_SECTOR_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */
+
+#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+#if defined(STM32F401xC)
+#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */
+#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */
+#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */
+#define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3 */
+#define OB_PCROP_SECTOR_4 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4 */
+#define OB_PCROP_SECTOR_5 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5 */
+#define OB_PCROP_SECTOR_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */
+
+#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F401xC */
+
+#if defined(STM32F401xE)
+#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */
+#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */
+#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */
+#define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3 */
+#define OB_PCROP_SECTOR_4 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4 */
+#define OB_PCROP_SECTOR_5 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5 */
+#define OB_PCROP_SECTOR_6 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector6 */
+#define OB_PCROP_SECTOR_7 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector7 */
+#define OB_PCROP_SECTOR_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */
+
+#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#endif /* STM32F401xE */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Dual_Boot FLASH Dual Boot
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define OB_DUAL_BOOT_ENABLE ((uint8_t)0x10) /*!< Dual Bank Boot Enable */
+#define OB_DUAL_BOOT_DISABLE ((uint8_t)0x00) /*!< Dual Bank Boot Disable, always boot on User Flash */
+#define IS_OB_BOOT(BOOT) (((BOOT) == OB_DUAL_BOOT_ENABLE) || ((BOOT) == OB_DUAL_BOOT_DISABLE))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Selection_Protection_Mode FLASH Selection Protection Mode
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE)
+#define OB_PCROP_DESELECTED ((uint8_t)0x00) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */
+#define OB_PCROP_SELECTED ((uint8_t)0x80) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i */
+#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PCROP_SELECTED) || ((PCROP) == OB_PCROP_DESELECTED))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE */
+/**
+ * @}
+ */
+
+/**
+ * @brief OPTCR1 register byte 2 (Bits[23:16]) base address
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define OPTCR1_BYTE2_ADDRESS ((uint32_t)0x40023C1A)
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Extension Program operation functions *************************************/
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE)
+HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
+void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
+HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void);
+HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+uint16_t HAL_FLASHEx_OB_GetBank2WRP(void);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_FLASH_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_gpio.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,277 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_gpio.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of GPIO HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_GPIO_H
+#define __STM32F4xx_HAL_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief GPIO Init structure definition
+ */
+typedef struct
+{
+ uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_pins_define */
+
+ uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIO_mode_define */
+
+ uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+ This parameter can be a value of @ref GPIO_pull_define */
+
+ uint32_t Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIO_speed_define */
+
+ uint32_t Alternate; /*!< Peripheral to be connected to the selected pins.
+ This parameter can be a value of @ref GPIO_Alternat_function_selection */
+}GPIO_InitTypeDef;
+
+/**
+ * @brief GPIO Bit SET and Bit RESET enumeration
+ */
+typedef enum
+{
+ GPIO_PIN_RESET = 0,
+ GPIO_PIN_SET
+}GPIO_PinState;
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants
+ * @{
+ */
+
+/** @defgroup GPIO_pins_define
+ * @{
+ */
+#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
+#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
+#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
+#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
+#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
+#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
+#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
+#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
+#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
+#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
+#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
+#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
+#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
+#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
+#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
+#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
+#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
+
+#define IS_GPIO_PIN(PIN) ((((PIN) & (uint32_t)0x00) == 0x00) && ((PIN) != (uint32_t)0x00))
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_PIN_0) || \
+ ((PIN) == GPIO_PIN_1) || \
+ ((PIN) == GPIO_PIN_2) || \
+ ((PIN) == GPIO_PIN_3) || \
+ ((PIN) == GPIO_PIN_4) || \
+ ((PIN) == GPIO_PIN_5) || \
+ ((PIN) == GPIO_PIN_6) || \
+ ((PIN) == GPIO_PIN_7) || \
+ ((PIN) == GPIO_PIN_8) || \
+ ((PIN) == GPIO_PIN_9) || \
+ ((PIN) == GPIO_PIN_10) || \
+ ((PIN) == GPIO_PIN_11) || \
+ ((PIN) == GPIO_PIN_12) || \
+ ((PIN) == GPIO_PIN_13) || \
+ ((PIN) == GPIO_PIN_14) || \
+ ((PIN) == GPIO_PIN_15))
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_mode_define
+ * @brief GPIO Configuration Mode
+ * Elements values convention: 0xX0yz00YZ
+ * - X : GPIO mode or EXTI Mode
+ * - y : External IT or Event trigger detection
+ * - z : IO configuration on External IT or Event
+ * - Y : Output type (Push Pull or Open Drain)
+ * - Z : IO Direction mode (Input, Output, Alternate or Analog)
+ * @{
+ */
+#define GPIO_MODE_INPUT ((uint32_t)0x00000000) /*!< Input Floating Mode */
+#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001) /*!< Output Push Pull Mode */
+#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011) /*!< Output Open Drain Mode */
+#define GPIO_MODE_AF_PP ((uint32_t)0x00000002) /*!< Alternate Function Push Pull Mode */
+#define GPIO_MODE_AF_OD ((uint32_t)0x00000012) /*!< Alternate Function Open Drain Mode */
+
+#define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */
+
+#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+
+#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */
+#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */
+#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */
+
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
+ ((MODE) == GPIO_MODE_OUTPUT_PP) ||\
+ ((MODE) == GPIO_MODE_OUTPUT_OD) ||\
+ ((MODE) == GPIO_MODE_AF_PP) ||\
+ ((MODE) == GPIO_MODE_AF_OD) ||\
+ ((MODE) == GPIO_MODE_IT_RISING) ||\
+ ((MODE) == GPIO_MODE_IT_FALLING) ||\
+ ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
+ ((MODE) == GPIO_MODE_EVT_RISING) ||\
+ ((MODE) == GPIO_MODE_EVT_FALLING) ||\
+ ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
+ ((MODE) == GPIO_MODE_ANALOG))
+
+/**
+ * @}
+ */
+/** @defgroup GPIO_speed_define
+ * @brief GPIO Output Maximum frequency
+ * @{
+ */
+#define GPIO_SPEED_LOW ((uint32_t)0x00000000) /*!< Low speed */
+#define GPIO_SPEED_MEDIUM ((uint32_t)0x00000001) /*!< Medium speed */
+#define GPIO_SPEED_FAST ((uint32_t)0x00000002) /*!< Fast speed */
+#define GPIO_SPEED_HIGH ((uint32_t)0x00000003) /*!< High speed */
+
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW) || ((SPEED) == GPIO_SPEED_MEDIUM) || \
+ ((SPEED) == GPIO_SPEED_FAST) || ((SPEED) == GPIO_SPEED_HIGH))
+/**
+ * @}
+ */
+
+ /** @defgroup GPIO_pull_define
+ * @brief GPIO Pull-Up or Pull-Down Activation
+ * @{
+ */
+#define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */
+#define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */
+#define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */
+
+#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
+ ((PULL) == GPIO_PULLDOWN))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/**
+ * @brief Checks whether the specified EXTI line flag is set or not.
+ * @param __EXTI_LINE__: specifies the EXTI line flag to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+ * @brief Clears the EXTI's line pending flags.
+ * @param __EXTI_LINE__: specifies the EXTI lines flags to clear.
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/**
+ * @brief Checks whether the specified EXTI line is asserted or not.
+ * @param __EXTI_LINE__: specifies the EXTI line to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+ * @brief Clears the EXTI's line pending bits.
+ * @param __EXTI_LINE__: specifies the EXTI lines to clear.
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/* Include GPIO HAL Extension module */
+#include "stm32f4xx_hal_gpio_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization and de-initialization functions *******************************/
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+
+/* IO operation functions *******************************************************/
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_GPIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_gpio_ex.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,716 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_gpio_ex.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of GPIO HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_GPIO_EX_H
+#define __STM32F4xx_HAL_GPIO_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants
+ * @{
+ */
+
+/** @defgroup GPIO_Alternat_function_selection
+ * @{
+ */
+
+/*------------------------- STM32F429xx/STM32F439xx---------------------------*/
+#if defined (STM32F429xx) || defined (STM32F439xx)
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
+#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
+#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
+#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
+#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */
+#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
+#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
+#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
+#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */
+#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
+#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
+#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
+#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LCD-TFT Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
+#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
+
+/**
+ * @brief AF 13 selection
+ */
+#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
+
+/**
+ * @brief AF 14 selection
+ */
+#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
+ ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
+ ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \
+ ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
+ ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \
+ ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+ ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \
+ ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \
+ ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \
+ ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
+ ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1) || \
+ ((AF) == GPIO_AF14_LTDC))
+
+#endif /* STM32F429xx || STM32F439xx */
+/*------------------------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F427xx/STM32F437xx--------------------------------*/
+#if defined (STM32F427xx) || defined (STM32F437xx)
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
+#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
+#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
+#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
+#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */
+#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
+#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
+#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
+#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */
+#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
+#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
+#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
+#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
+
+/**
+ * @brief AF 13 selection
+ */
+#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
+ ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
+ ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \
+ ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
+ ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \
+ ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+ ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \
+ ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \
+ ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \
+ ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
+ ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1))
+
+#endif /* STM32F427xx || STM32F437xx */
+/*------------------------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F407xx/STM32F417xx--------------------------------*/
+#if defined (STM32F407xx) || defined (STM32F417xx)
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
+#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
+#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
+#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
+#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
+#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */
+#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
+
+/**
+ * @brief AF 13 selection
+ */
+#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
+ ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
+ ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \
+ ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
+ ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \
+ ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+ ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \
+ ((AF) == GPIO_AF12_FSMC) || ((AF) == GPIO_AF15_EVENTOUT))
+
+#endif /* STM32F407xx || STM32F417xx */
+/*------------------------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F405xx/STM32F415xx--------------------------------*/
+#if defined (STM32F405xx) || defined (STM32F415xx)
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
+#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
+#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
+#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
+#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
+#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */
+#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
+ ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
+ ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \
+ ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
+ ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \
+ ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDIO) || \
+ ((AF) == GPIO_AF12_FSMC) || ((AF) == GPIO_AF15_EVENTOUT))
+
+#endif /* STM32F405xx || STM32F415xx */
+
+/*------------------------------------------------------------------------------------------*/
+
+/*---------------------------------------- STM32F401xx--------------------------------------*/
+#if defined(STM32F401xC) || defined(STM32F401xE)
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
+#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
+#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
+#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */
+#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */
+
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
+ ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF4_I2C1) || \
+ ((AF) == GPIO_AF4_I2C2) || ((AF) == GPIO_AF4_I2C3) || \
+ ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF5_SPI4) || \
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
+ ((AF) == GPIO_AF8_USART6) || ((AF) == GPIO_AF10_OTG_FS) || \
+ ((AF) == GPIO_AF9_I2C2) || ((AF) == GPIO_AF9_I2C3) || \
+ ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF15_EVENTOUT))
+
+#endif /* STM32F401xC || STM32F401xE */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_GPIO_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_hash.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,331 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_hash.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of HASH HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_HASH_H
+#define __STM32F4xx_HAL_HASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HASH
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HASH Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
+ This parameter can be a value of @ref HASH_Data_Type */
+
+ uint32_t KeySize; /*!< The key size is used only in HMAC operation */
+
+ uint8_t* pKey; /*!< The key is used only in HMAC operation */
+}HASH_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_HASH_STATE_RESET = 0x00, /*!< HASH not yet initialized or disabled */
+ HAL_HASH_STATE_READY = 0x01, /*!< HASH initialized and ready for use */
+ HAL_HASH_STATE_BUSY = 0x02, /*!< HASH internal process is ongoing */
+ HAL_HASH_STATE_TIMEOUT = 0x03, /*!< HASH timeout state */
+ HAL_HASH_STATE_ERROR = 0x04 /*!< HASH error state */
+}HAL_HASH_STATETypeDef;
+
+/**
+ * @brief HAL phase structures definition
+ */
+typedef enum
+{
+ HAL_HASH_PHASE_READY = 0x01, /*!< HASH peripheral is ready for initialization */
+ HAL_HASH_PHASE_PROCESS = 0x02, /*!< HASH peripheral is in processing phase */
+}HAL_HASHPhaseTypeDef;
+
+/**
+ * @brief HASH Handle Structure definition
+ */
+typedef struct
+{
+ HASH_InitTypeDef Init; /*!< HASH required parameters */
+
+ uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */
+
+ uint8_t *pHashOutBuffPtr; /*!< Pointer to input buffer */
+
+ __IO uint32_t HashBuffSize; /*!< Size of buffer to be processed */
+
+ __IO uint32_t HashInCount; /*!< Counter of inputed data */
+
+ __IO uint32_t HashITCounter; /*!< Counter of issued interrupts */
+
+ HAL_StatusTypeDef Status; /*!< HASH peripheral status */
+
+ HAL_HASHPhaseTypeDef Phase; /*!< HASH peripheral phase */
+
+ DMA_HandleTypeDef *hdmain; /*!< HASH In DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< HASH locking object */
+
+ __IO HAL_HASH_STATETypeDef State; /*!< HASH peripheral state */
+} HASH_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HASH_Exported_Constants
+ * @{
+ */
+
+/** @defgroup HASH_Algo_Selection
+ * @{
+ */
+#define HASH_AlgoSelection_SHA1 ((uint32_t)0x0000) /*!< HASH function is SHA1 */
+#define HASH_AlgoSelection_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */
+#define HASH_AlgoSelection_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */
+#define HASH_AlgoSelection_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */
+
+#define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \
+ ((ALGOSELECTION) == HASH_AlgoSelection_SHA224) || \
+ ((ALGOSELECTION) == HASH_AlgoSelection_SHA256) || \
+ ((ALGOSELECTION) == HASH_AlgoSelection_MD5))
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Algorithm_Mode
+ * @{
+ */
+#define HASH_AlgoMode_HASH ((uint32_t)0x00000000) /*!< Algorithm is HASH */
+#define HASH_AlgoMode_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */
+
+#define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \
+ ((ALGOMODE) == HASH_AlgoMode_HMAC))
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Data_Type
+ * @{
+ */
+#define HASH_DATATYPE_32B ((uint32_t)0x0000) /*!< 32-bit data. No swapping */
+#define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
+#define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
+#define HASH_DATATYPE_1B HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */
+
+#define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DATATYPE_32B)|| \
+ ((DATATYPE) == HASH_DATATYPE_16B)|| \
+ ((DATATYPE) == HASH_DATATYPE_8B) || \
+ ((DATATYPE) == HASH_DATATYPE_1B))
+/**
+ * @}
+ */
+
+/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode
+ * @{
+ */
+#define HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */
+#define HASH_HMACKeyType_LongKey HASH_CR_LKEY /*!< HMAC Key is > 64 bytes */
+
+#define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \
+ ((KEYTYPE) == HASH_HMACKeyType_LongKey))
+/**
+ * @}
+ */
+
+/** @defgroup HASH_flags_definition
+ * @{
+ */
+#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */
+#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
+#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
+#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy : processing a block of data */
+#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : The input buffer contains at least one word of data */
+/**
+ * @}
+ */
+
+/** @defgroup HASH_interrupts_definition
+ * @{
+ */
+#define HASH_IT_DINI HASH_IMR_DINIM /*!< A new block can be entered into the input buffer (DIN) */
+#define HASH_IT_DCI HASH_IMR_DCIM /*!< Digest calculation complete */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset HASH handle state
+ * @param __HANDLE__: specifies the HASH handle.
+ * @retval None
+ */
+#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
+
+/** @brief Check whether the specified HASH flag is set or not.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg HASH_FLAG_DINIS: A new block can be entered into the input buffer.
+ * @arg HASH_FLAG_DCIS: Digest calculation complete
+ * @arg HASH_FLAG_DMAS: DMA interface is enabled (DMAE=1) or a transfer is ongoing
+ * @arg HASH_FLAG_BUSY: The hash core is Busy : processing a block of data
+ * @arg HASH_FLAG_DINNE: DIN not empty : The input buffer contains at least one word of data
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_HASH_GET_FLAG(__FLAG__) ((HASH->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Macros for HMAC finish.
+ * @param None
+ * @retval None
+ */
+#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
+#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
+#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
+#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
+
+/**
+ * @brief Enable the multiple DMA mode.
+ * This feature is available only in STM32F429x and STM32F439x devices.
+ * @param None
+ * @retval None
+ */
+#define __HAL_HASH_SET_MDMAT() HASH->CR |= HASH_CR_MDMAT
+
+/**
+ * @brief Disable the multiple DMA mode.
+ * @param None
+ * @retval None
+ */
+#define __HAL_HASH_RESET_MDMAT() HASH->CR &= (uint32_t)(~HASH_CR_MDMAT)
+
+/**
+ * @brief Start the digest computation
+ * @param None
+ * @retval None
+ */
+#define __HAL_HASH_START_DIGEST() HASH->STR |= HASH_STR_DCAL
+
+/**
+ * @brief Set the number of valid bits in last word written in Data register
+ * @param SIZE: size in byte of last data written in Data register.
+ * @retval None
+*/
+#define __HAL_HASH_SET_NBVALIDBITS(SIZE) do{HASH->STR &= ~(HASH_STR_NBW);\
+ HASH->STR |= 8 * ((SIZE) % 4);\
+ }while(0)
+
+/* Include HASH HAL Extension module */
+#include "stm32f4xx_hal_hash_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
+HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
+
+/* HASH processing using polling *********************************************/
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+/* HASH-MAC processing using polling *****************************************/
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+
+/* HASH processing using interrupt *******************************************/
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+
+/* HASH processing using DMA *************************************************/
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+
+/* HASH-HMAC processing using DMA ********************************************/
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+/* Processing functions ******************************************************/
+void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
+
+/* Peripheral State functions ************************************************/
+HAL_HASH_STATETypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
+void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
+void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
+void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
+void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
+void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
+
+#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_HASH_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_hash_ex.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,105 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_hash_ex.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of HASH HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_HASH_EX_H
+#define __STM32F4xx_HAL_HASH_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F437xx) || defined(STM32F439xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HASHEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* HASH processing using polling *********************************************/
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+/* HASH-MAC processing using polling *****************************************/
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+
+/* HASH processing using interrupt *******************************************/
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+
+/* HASH processing using DMA *************************************************/
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+
+/* HASH-HMAC processing using DMA ********************************************/
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+/* Processing functions ******************************************************/
+void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash);
+
+#endif /* STM32F437xx || STM32F439xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_HASH_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_hcd.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,227 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_hcd.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of HCD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_HCD_H
+#define __STM32F4xx_HAL_HCD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_usb.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HCD
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+ /**
+ * @brief HCD Status structures structure definition
+ */
+typedef enum
+{
+ HCD_READY = 0x00,
+ HCD_ERROR = 0x01,
+ HCD_BUSY = 0x02,
+ HCD_TIMEOUT = 0x03
+} HCD_StateTypeDef;
+
+typedef USB_OTG_GlobalTypeDef HCD_TypeDef;
+typedef USB_OTG_CfgTypeDef HCD_InitTypeDef;
+typedef USB_OTG_HCTypeDef HCD_HCTypeDef ;
+typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef ;
+typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef ;
+
+/**
+ * @brief HCD Handle Structure definition
+ */
+typedef struct
+{
+ HCD_TypeDef *Instance; /*!< Register base address */
+ HCD_InitTypeDef Init; /*!< HCD required parameters */
+ HCD_HCTypeDef hc[15]; /*!< Host channels parameters */
+ HAL_LockTypeDef Lock; /*!< HCD peripheral status */
+ __IO HCD_StateTypeDef State; /*!< HCD communication state */
+ void *pData; /*!< Pointer Stack Handler */
+
+} HCD_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HCD_Exported_Constants
+ * @{
+ */
+
+/** @defgroup HCD_Instance_definition
+ * @{
+ */
+
+#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) |= (__INTERRUPT__))
+#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
+
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+#elif defined(STM32F401xC) || defined(STM32F401xE)
+ #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HCD_Speed
+ * @{
+ */
+#define HCD_SPEED_HIGH 0
+#define HCD_SPEED_LOW 2
+#define HCD_SPEED_FULL 3
+
+/**
+ * @}
+ */
+
+ /** @defgroup HCD_PHY_Module
+ * @{
+ */
+#define HCD_PHY_ULPI 1
+#define HCD_PHY_EMBEDDED 2
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup HCD_Interrupt_Clock
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+#define __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
+
+#define __HAL_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) |= (__INTERRUPT__))
+#define __HAL_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
+
+
+#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
+#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
+#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
+#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
+#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
+ uint8_t ch_num,
+ uint8_t epnum,
+ uint8_t dev_address,
+ uint8_t speed,
+ uint8_t ep_type,
+ uint16_t mps);
+
+HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd,
+ uint8_t ch_num);
+
+void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
+
+/* I/O operation functions *****************************************************/
+HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
+ uint8_t pipe,
+ uint8_t direction ,
+ uint8_t ep_type,
+ uint8_t token,
+ uint8_t* pbuff,
+ uint16_t length,
+ uint8_t do_ping);
+
+ /* Non-Blocking mode: Interrupt */
+void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
+ uint8_t chnum,
+ HCD_URBStateTypeDef urb_state);
+
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
+
+/* Peripheral State functions **************************************************/
+HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
+HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
+uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_HCD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_i2c.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,461 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_i2c.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of I2C HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_I2C_H
+#define __STM32F4xx_HAL_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief I2C Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t ClockSpeed; /*!< Specifies the clock frequency.
+ This parameter must be set to a value lower than 400kHz */
+
+ uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
+ This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+ uint32_t OwnAddress1; /*!< Specifies the first device own address.
+ This parameter can be a 7-bit or 10-bit address. */
+
+ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
+ This parameter can be a value of @ref I2C_addressing_mode */
+
+ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
+ This parameter can be a value of @ref I2C_dual_addressing_mode */
+
+ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
+ This parameter can be a 7-bit address. */
+
+ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
+ This parameter can be a value of @ref I2C_general_call_addressing_mode */
+
+ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
+ This parameter can be a value of @ref I2C_nostretch_mode */
+
+}I2C_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_I2C_STATE_RESET = 0x00, /*!< I2C not yet initialized or disabled */
+ HAL_I2C_STATE_READY = 0x01, /*!< I2C initialized and ready for use */
+ HAL_I2C_STATE_BUSY = 0x02, /*!< I2C internal process is ongoing */
+ HAL_I2C_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_I2C_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_I2C_STATE_MEM_BUSY_TX = 0x32, /*!< Memory Data Transmission process is ongoing */
+ HAL_I2C_STATE_MEM_BUSY_RX = 0x42, /*!< Memory Data Reception process is ongoing */
+ HAL_I2C_STATE_TIMEOUT = 0x03, /*!< I2C timeout state */
+ HAL_I2C_STATE_ERROR = 0x04 /*!< I2C error state */
+
+}HAL_I2C_StateTypeDef;
+
+/**
+ * @brief HAL I2C Error Code structure definition
+ */
+typedef enum
+{
+ HAL_I2C_ERROR_NONE = 0x00, /*!< No error */
+ HAL_I2C_ERROR_BERR = 0x01, /*!< BERR error */
+ HAL_I2C_ERROR_ARLO = 0x02, /*!< ARLO error */
+ HAL_I2C_ERROR_AF = 0x04, /*!< AF error */
+ HAL_I2C_ERROR_OVR = 0x08, /*!< OVR error */
+ HAL_I2C_ERROR_DMA = 0x10, /*!< DMA transfer error */
+ HAL_I2C_ERROR_TIMEOUT = 0x20 /*!< Timeout error */
+
+}HAL_I2C_ErrorTypeDef;
+
+/**
+ * @brief I2C handle Structure definition
+ */
+typedef struct
+{
+ I2C_TypeDef *Instance; /*!< I2C registers base address */
+
+ I2C_InitTypeDef Init; /*!< I2C communication parameters */
+
+ uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
+
+ uint16_t XferSize; /*!< I2C transfer size */
+
+ __IO uint16_t XferCount; /*!< I2C transfer counter */
+
+ DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< I2C locking object */
+
+ __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
+
+ __IO HAL_I2C_ErrorTypeDef ErrorCode; /* I2C Error code */
+
+}I2C_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Constants
+ * @{
+ */
+
+/** @defgroup I2C_duty_cycle_in_fast_mode
+ * @{
+ */
+#define I2C_DUTYCYCLE_2 ((uint32_t)0x00000000)
+#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
+
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
+ ((CYCLE) == I2C_DUTYCYCLE_16_9))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_addressing_mode
+ * @{
+ */
+#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00004000)
+#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000))
+
+#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
+ ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_dual_addressing_mode
+ * @{
+ */
+#define I2C_DUALADDRESS_DISABLED ((uint32_t)0x00000000)
+#define I2C_DUALADDRESS_ENABLED I2C_OAR2_ENDUAL
+
+#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLED) || \
+ ((ADDRESS) == I2C_DUALADDRESS_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_general_call_addressing_mode
+ * @{
+ */
+#define I2C_GENERALCALL_DISABLED ((uint32_t)0x00000000)
+#define I2C_GENERALCALL_ENABLED I2C_CR1_ENGC
+
+#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLED) || \
+ ((CALL) == I2C_GENERALCALL_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_nostretch_mode
+ * @{
+ */
+#define I2C_NOSTRETCH_DISABLED ((uint32_t)0x00000000)
+#define I2C_NOSTRETCH_ENABLED I2C_CR1_NOSTRETCH
+
+#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLED) || \
+ ((STRETCH) == I2C_NOSTRETCH_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Memory_Address_Size
+ * @{
+ */
+#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001)
+#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000010)
+
+#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
+ ((SIZE) == I2C_MEMADD_SIZE_16BIT))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Interrupt_configuration_definition
+ * @{
+ */
+#define I2C_IT_BUF I2C_CR2_ITBUFEN
+#define I2C_IT_EVT I2C_CR2_ITEVTEN
+#define I2C_IT_ERR I2C_CR2_ITERREN
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Flag_definition
+ * @{
+ */
+#define I2C_FLAG_SMBALERT ((uint32_t)0x00018000)
+#define I2C_FLAG_TIMEOUT ((uint32_t)0x00014000)
+#define I2C_FLAG_PECERR ((uint32_t)0x00011000)
+#define I2C_FLAG_OVR ((uint32_t)0x00010800)
+#define I2C_FLAG_AF ((uint32_t)0x00010400)
+#define I2C_FLAG_ARLO ((uint32_t)0x00010200)
+#define I2C_FLAG_BERR ((uint32_t)0x00010100)
+#define I2C_FLAG_TXE ((uint32_t)0x00010080)
+#define I2C_FLAG_RXNE ((uint32_t)0x00010040)
+#define I2C_FLAG_STOPF ((uint32_t)0x00010010)
+#define I2C_FLAG_ADD10 ((uint32_t)0x00010008)
+#define I2C_FLAG_BTF ((uint32_t)0x00010004)
+#define I2C_FLAG_ADDR ((uint32_t)0x00010002)
+#define I2C_FLAG_SB ((uint32_t)0x00010001)
+#define I2C_FLAG_DUALF ((uint32_t)0x00100080)
+#define I2C_FLAG_SMBHOST ((uint32_t)0x00100040)
+#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00100020)
+#define I2C_FLAG_GENCALL ((uint32_t)0x00100010)
+#define I2C_FLAG_TRA ((uint32_t)0x00100004)
+#define I2C_FLAG_BUSY ((uint32_t)0x00100002)
+#define I2C_FLAG_MSL ((uint32_t)0x00100001)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset I2C handle state
+ * @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @retval None
+ */
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
+
+/** @brief Enable or disable the specified I2C interrupts.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg I2C_IT_BUF: Buffer interrupt enable
+ * @arg I2C_IT_EVT: Event interrupt enable
+ * @arg I2C_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
+
+/** @brief Checks if the specified I2C interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @param __INTERRUPT__: specifies the I2C interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_IT_BUF: Buffer interrupt enable
+ * @arg I2C_IT_EVT: Event interrupt enable
+ * @arg I2C_IT_ERR: Error interrupt enable
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks whether the specified I2C flag is set or not.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+ * @arg I2C_FLAG_PECERR: PEC error in reception flag
+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag
+ * @arg I2C_FLAG_AF: Acknowledge failure flag
+ * @arg I2C_FLAG_ARLO: Arbitration lost flag
+ * @arg I2C_FLAG_BERR: Bus error flag
+ * @arg I2C_FLAG_TXE: Data register empty flag
+ * @arg I2C_FLAG_RXNE: Data register not empty flag
+ * @arg I2C_FLAG_STOPF: Stop detection flag
+ * @arg I2C_FLAG_ADD10: 10-bit header sent flag
+ * @arg I2C_FLAG_BTF: Byte transfer finished flag
+ * @arg I2C_FLAG_ADDR: Address sent flag
+ * Address matched flag
+ * @arg I2C_FLAG_SB: Start bit flag
+ * @arg I2C_FLAG_DUALF: Dual flag
+ * @arg I2C_FLAG_SMBHOST: SMBus host header
+ * @arg I2C_FLAG_SMBDEFAULT: SMBus default header
+ * @arg I2C_FLAG_GENCALL: General call header flag
+ * @arg I2C_FLAG_TRA: Transmitter/Receiver flag
+ * @arg I2C_FLAG_BUSY: Bus busy flag
+ * @arg I2C_FLAG_MSL: Master/Slave flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define I2C_FLAG_MASK ((uint32_t)0x0000FFFF)
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16)) == 0x01)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
+ ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
+
+/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+ * @arg I2C_FLAG_PECERR: PEC error in reception flag
+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+ * @arg I2C_FLAG_AF: Acknowledge failure flag
+ * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+ * @arg I2C_FLAG_BERR: Bus error flag
+ * @retval None
+ */
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 &= ~((__FLAG__) & I2C_FLAG_MASK))
+
+/** @brief Clears the I2C ADDR pending flag.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @retval None
+ */
+
+#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR1;\
+ (__HANDLE__)->Instance->SR2;}while(0)
+
+/** @brief Clears the I2C STOPF pending flag.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @retval None
+ */
+#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR1;\
+ (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE;}while(0)
+
+#define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
+#define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
+
+#define __HAL_I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000)
+#define __HAL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000) ? ((__FREQRANGE__) + 1) : ((((__FREQRANGE__) * 300) / 1000) + 1))
+#define __HAL_I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1)) & I2C_CCR_CCR) < 4)? 4:((__PCLK__) / ((__SPEED__) << 1)))
+#define __HAL_I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3)) : (((__PCLK__) / ((__SPEED__) * 25)) | I2C_DUTYCYCLE_16_9))
+#define __HAL_I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000)? (__HAL_I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
+ ((__HAL_I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0)? 1 : \
+ ((__HAL_I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
+
+#define __HAL_I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
+#define __HAL_I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
+
+#define __HAL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+#define __HAL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
+#define __HAL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
+
+#define __HAL_I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
+#define __HAL_I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000))
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00)) == 0)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01)) == 0)
+
+/* Include I2C HAL Extension module */
+#include "stm32f4xx_hal_i2c_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+
+/* I/O operation functions *****************************************************/
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+/******* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+
+/* Peripheral Control and State functions **************************************/
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_I2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_i2c_ex.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,111 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_i2c_ex.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of I2C HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_I2C_EX_H
+#define __STM32F4xx_HAL_I2C_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup I2CEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2CEx_Exported_Constants
+ * @{
+ */
+
+/** @defgroup I2CEx_Analog_Filter
+ * @{
+ */
+#define I2C_ANALOGFILTER_ENABLED ((uint32_t)0x00000000)
+#define I2C_ANALOGFILTER_DISABLED I2C_FLTR_ANOFF
+
+#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLED) || \
+ ((FILTER) == I2C_ANALOGFILTER_DISABLED))
+/**
+ * @}
+ */
+
+/** @defgroup I2CEx_Digital_Filter
+ * @{
+ */
+#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_I2CEx_AnalogFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_I2CEx_DigitalFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
+
+/**
+ * @}
+ */
+#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC || STM32F401xE */
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_I2C_EX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_i2s.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,445 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_i2s.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of I2S HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_I2S_H
+#define __STM32F4xx_HAL_I2S_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup I2S
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/**
+ * @brief I2S Init structure definition
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Specifies the I2S operating mode.
+ This parameter can be a value of @ref I2S_Mode */
+
+ uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
+ This parameter can be a value of @ref I2S_Standard */
+
+ uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
+ This parameter can be a value of @ref I2S_Data_Format */
+
+ uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
+ This parameter can be a value of @ref I2S_MCLK_Output */
+
+ uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
+ This parameter can be a value of @ref I2S_Audio_Frequency */
+
+ uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
+ This parameter can be a value of @ref I2S_Clock_Polarity */
+
+ uint32_t ClockSource; /*!< Specifies the I2S Clock Source.
+ This parameter can be a value of @ref I2S_Clock_Source */
+
+ uint32_t FullDuplexMode; /*!< Specifies the I2S FullDuplex mode.
+ This parameter can be a value of @ref I2S_FullDuplex_Mode */
+
+}I2S_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */
+ HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */
+ HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */
+ HAL_I2S_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_I2S_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_I2S_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
+ HAL_I2S_STATE_TIMEOUT = 0x03, /*!< I2S timeout state */
+ HAL_I2S_STATE_ERROR = 0x04 /*!< I2S error state */
+
+}HAL_I2S_StateTypeDef;
+
+/**
+ * @brief HAL I2S Error Code structure definition
+ */
+typedef enum
+{
+ HAL_I2S_ERROR_NONE = 0x00, /*!< No error */
+ HAL_I2S_ERROR_UDR = 0x01, /*!< I2S Underrun error */
+ HAL_I2S_ERROR_OVR = 0x02, /*!< I2S Overrun error */
+ HAL_I2SEX_ERROR_UDR = 0x04, /*!< I2S extended Underrun error */
+ HAL_I2SEX_ERROR_OVR = 0x08, /*!< I2S extended Overrun error */
+ HAL_I2S_ERROR_FRE = 0x10, /*!< I2S Frame format error */
+ HAL_I2S_ERROR_DMA = 0x20 /*!< DMA transfer error */
+}HAL_I2S_ErrorTypeDef;
+
+/**
+ * @brief I2S handle Structure definition
+ */
+typedef struct
+{
+ SPI_TypeDef *Instance; /* I2S registers base address */
+
+ I2S_InitTypeDef Init; /* I2S communication parameters */
+
+ uint16_t *pTxBuffPtr; /* Pointer to I2S Tx transfer buffer */
+
+ __IO uint16_t TxXferSize; /* I2S Tx transfer size */
+
+ __IO uint16_t TxXferCount; /* I2S Tx transfer Counter */
+
+ uint16_t *pRxBuffPtr; /* Pointer to I2S Rx transfer buffer */
+
+ __IO uint16_t RxXferSize; /* I2S Rx transfer size */
+
+ __IO uint16_t RxXferCount; /* I2S Rx transfer counter */
+
+ DMA_HandleTypeDef *hdmatx; /* I2S Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /* I2S Rx DMA handle parameters */
+
+ __IO HAL_LockTypeDef Lock; /* I2S locking object */
+
+ __IO HAL_I2S_StateTypeDef State; /* I2S communication state */
+
+ __IO HAL_I2S_ErrorTypeDef ErrorCode; /* I2S Error code */
+
+}I2S_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2S_Exported_Constants
+ * @{
+ */
+#define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE))
+
+/** @defgroup I2S_Clock_Source
+ * @{
+ */
+#define I2S_CLOCK_PLL ((uint32_t)0x00000000)
+#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001)
+
+#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
+ ((CLOCK) == I2S_CLOCK_PLL))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Mode
+ * @{
+ */
+#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000)
+#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100)
+#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200)
+#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300)
+
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
+ ((MODE) == I2S_MODE_SLAVE_RX) || \
+ ((MODE) == I2S_MODE_MASTER_TX) || \
+ ((MODE) == I2S_MODE_MASTER_RX))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Standard
+ * @{
+ */
+#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000)
+#define I2S_STANDARD_MSB ((uint32_t)0x00000010)
+#define I2S_STANDARD_LSB ((uint32_t)0x00000020)
+#define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030)
+#define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0)
+
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
+ ((STANDARD) == I2S_STANDARD_MSB) || \
+ ((STANDARD) == I2S_STANDARD_LSB) || \
+ ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
+ ((STANDARD) == I2S_STANDARD_PCM_LONG))
+/** @defgroup I2S_Legacy
+ * @{
+ */
+#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Data_Format
+ * @{
+ */
+#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000)
+#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001)
+#define I2S_DATAFORMAT_24B ((uint32_t)0x00000003)
+#define I2S_DATAFORMAT_32B ((uint32_t)0x00000005)
+
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
+ ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
+ ((FORMAT) == I2S_DATAFORMAT_24B) || \
+ ((FORMAT) == I2S_DATAFORMAT_32B))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_MCLK_Output
+ * @{
+ */
+#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
+#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000)
+
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
+ ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Audio_Frequency
+ * @{
+ */
+#define I2S_AUDIOFREQ_192K ((uint32_t)192000)
+#define I2S_AUDIOFREQ_96K ((uint32_t)96000)
+#define I2S_AUDIOFREQ_48K ((uint32_t)48000)
+#define I2S_AUDIOFREQ_44K ((uint32_t)44100)
+#define I2S_AUDIOFREQ_32K ((uint32_t)32000)
+#define I2S_AUDIOFREQ_22K ((uint32_t)22050)
+#define I2S_AUDIOFREQ_16K ((uint32_t)16000)
+#define I2S_AUDIOFREQ_11K ((uint32_t)11025)
+#define I2S_AUDIOFREQ_8K ((uint32_t)8000)
+#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2)
+
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
+ ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
+ ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_FullDuplex_Mode
+ * @{
+ */
+#define I2S_FULLDUPLEXMODE_DISABLE ((uint32_t)0x00000000)
+#define I2S_FULLDUPLEXMODE_ENABLE ((uint32_t)0x00000001)
+
+#define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \
+ ((MODE) == I2S_FULLDUPLEXMODE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Clock_Polarity
+ * @{
+ */
+#define I2S_CPOL_LOW ((uint32_t)0x00000000)
+#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
+
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
+ ((CPOL) == I2S_CPOL_HIGH))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Interrupt_configuration_definition
+ * @{
+ */
+#define I2S_IT_TXE SPI_CR2_TXEIE
+#define I2S_IT_RXNE SPI_CR2_RXNEIE
+#define I2S_IT_ERR SPI_CR2_ERRIE
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Flag_definition
+ * @{
+ */
+#define I2S_FLAG_TXE SPI_SR_TXE
+#define I2S_FLAG_RXNE SPI_SR_RXNE
+
+#define I2S_FLAG_UDR SPI_SR_UDR
+#define I2S_FLAG_OVR SPI_SR_OVR
+#define I2S_FLAG_FRE SPI_SR_FRE
+
+#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
+#define I2S_FLAG_BSY SPI_SR_BSY
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+
+/** @brief Reset I2S handle state
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
+
+/** @brief Enable or disable the specified SPI peripheral (in I2S mode).
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
+#define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
+
+/** @brief Enable or disable the specified I2S interrupts.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
+#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__))
+
+/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
+ * @param __INTERRUPT__: specifies the I2S interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks whether the specified I2S flag is set or not.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
+ * @arg I2S_FLAG_TXE: Transmit buffer empty flag
+ * @arg I2S_FLAG_UDR: Underrun flag
+ * @arg I2S_FLAG_OVR: Overrun flag
+ * @arg I2S_FLAG_FRE: Frame error flag
+ * @arg I2S_FLAG_CHSIDE: Channel Side flag
+ * @arg I2S_FLAG_BSY: Busy flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the I2S OVR pending flag.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\
+ (__HANDLE__)->Instance->SR;}while(0)
+/** @brief Clears the I2S UDR pending flag.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)((__HANDLE__)->Instance->SR)
+
+/* Include I2S Extension module */
+#include "stm32f4xx_hal_i2s_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
+void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
+
+/* I/O operation functions *****************************************************/
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+
+ /* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
+
+/* Peripheral Control and State functions **************************************/
+HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
+HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
+
+/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
+void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
+
+void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
+void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
+void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+void I2S_DMAError(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_I2S_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_i2s_ex.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,86 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_i2s_ex.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of I2S HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_I2S_EX_H
+#define __STM32F4xx_HAL_I2S_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup I2SEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Extended features functions **************************************************/
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout);
+ /* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
+
+HAL_StatusTypeDef I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_I2S_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_irda.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,395 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_irda.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of IRDA HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_IRDA_H
+#define __STM32F4xx_HAL_IRDA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup IRDA
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief IRDA Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
+ The baud rate is computed using the following formula:
+ - IntegerDivider = ((PCLKx) / (8 * (hirda->Init.BaudRate)))
+ - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref IRDA_Word_Length */
+
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref IRDA_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref IRDA_Mode */
+
+ uint8_t Prescaler; /*!< Specifies the Prescaler */
+
+ uint32_t IrDAMode; /*!< Specifies the IrDA mode
+ This parameter can be a value of @ref IrDA_Low_Power */
+}IRDA_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_IRDA_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */
+ HAL_IRDA_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_IRDA_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_IRDA_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_IRDA_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_IRDA_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
+ HAL_IRDA_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_IRDA_STATE_ERROR = 0x04 /*!< Error */
+}HAL_IRDA_StateTypeDef;
+
+/**
+ * @brief HAL IRDA Error Code structure definition
+ */
+typedef enum
+{
+ HAL_IRDA_ERROR_NONE = 0x00, /*!< No error */
+ HAL_IRDA_ERROR_PE = 0x01, /*!< Parity error */
+ HAL_IRDA_ERROR_NE = 0x02, /*!< Noise error */
+ HAL_IRDA_ERROR_FE = 0x04, /*!< frame error */
+ HAL_IRDA_ERROR_ORE = 0x08, /*!< Overrun error */
+ HAL_IRDA_ERROR_DMA = 0x10 /*!< DMA transfer error */
+}HAL_IRDA_ErrorTypeDef;
+
+/**
+ * @brief IRDA handle Structure definition
+ */
+typedef struct
+{
+ USART_TypeDef *Instance; /* USART registers base address */
+
+ IRDA_InitTypeDef Init; /* IRDA communication parameters */
+
+ uint8_t *pTxBuffPtr; /* Pointer to IRDA Tx transfer Buffer */
+
+ uint16_t TxXferSize; /* IRDA Tx Transfer size */
+
+ uint16_t TxXferCount; /* IRDA Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /* Pointer to IRDA Rx transfer Buffer */
+
+ uint16_t RxXferSize; /* IRDA Rx Transfer size */
+
+ uint16_t RxXferCount; /* IRDA Rx Transfer Counter */
+
+ DMA_HandleTypeDef *hdmatx; /* IRDA Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /* IRDA Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /* Locking object */
+
+ __IO HAL_IRDA_StateTypeDef State; /* IRDA communication state */
+
+ __IO HAL_IRDA_ErrorTypeDef ErrorCode; /* IRDA Error code */
+
+}IRDA_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Constants
+ * @{
+ */
+
+/** @defgroup IRDA_Word_Length
+ * @{
+ */
+#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000)
+#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
+#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \
+ ((LENGTH) == IRDA_WORDLENGTH_9B))
+/**
+ * @}
+ */
+
+
+/** @defgroup IRDA_Parity
+ * @{
+ */
+#define IRDA_PARITY_NONE ((uint32_t)0x00000000)
+#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
+#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
+ ((PARITY) == IRDA_PARITY_EVEN) || \
+ ((PARITY) == IRDA_PARITY_ODD))
+/**
+ * @}
+ */
+
+
+/** @defgroup IRDA_Mode
+ * @{
+ */
+#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
+#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
+#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+#define IS_IRDA_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
+/**
+ * @}
+ */
+
+/** @defgroup IrDA_Low_Power
+ * @{
+ */
+#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
+#define IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000)
+#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
+ ((MODE) == IRDA_POWERMODE_NORMAL))
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the SR register
+ * @{
+ */
+#define IRDA_FLAG_TXE ((uint32_t)0x00000080)
+#define IRDA_FLAG_TC ((uint32_t)0x00000040)
+#define IRDA_FLAG_RXNE ((uint32_t)0x00000020)
+#define IRDA_FLAG_IDLE ((uint32_t)0x00000010)
+#define IRDA_FLAG_ORE ((uint32_t)0x00000008)
+#define IRDA_FLAG_NE ((uint32_t)0x00000004)
+#define IRDA_FLAG_FE ((uint32_t)0x00000002)
+#define IRDA_FLAG_PE ((uint32_t)0x00000001)
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Interrupt_definition
+ * Elements values convention: 0xY000XXXX
+ * - XXXX : Interrupt mask in the XX register
+ * - Y : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ *
+ * @{
+ */
+
+#define IRDA_IT_PE ((uint32_t)0x10000100)
+#define IRDA_IT_TXE ((uint32_t)0x10000080)
+#define IRDA_IT_TC ((uint32_t)0x10000040)
+#define IRDA_IT_RXNE ((uint32_t)0x10000020)
+#define IRDA_IT_IDLE ((uint32_t)0x10000010)
+
+#define IRDA_IT_LBD ((uint32_t)0x20000040)
+
+#define IRDA_IT_CTS ((uint32_t)0x30000400)
+#define IRDA_IT_ERR ((uint32_t)0x30000001)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset IRDA handle state
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET)
+
+/** @brief Flushs the IRDA DR register
+ * @param __HANDLE__: specifies the IRDA Handle.
+ */
+#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
+
+/** @brief Checks whether the specified IRDA flag is set or not.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg IRDA_FLAG_TXE: Transmit data register empty flag
+ * @arg IRDA_FLAG_TC: Transmission Complete flag
+ * @arg IRDA_FLAG_RXNE: Receive data register not empty flag
+ * @arg IRDA_FLAG_IDLE: Idle Line detection flag
+ * @arg IRDA_FLAG_ORE: OverRun Error flag
+ * @arg IRDA_FLAG_NE: Noise Error flag
+ * @arg IRDA_FLAG_FE: Framing Error flag
+ * @arg IRDA_FLAG_PE: Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the specified IRDA pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg IRDA_FLAG_TC: Transmission Complete flag.
+ * @arg IRDA_FLAG_RXNE: Receive data register not empty flag.
+ *
+ * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * error) and IDLE (Idle line detected) flags are cleared by software
+ * sequence: a read operation to USART_SR register followed by a read
+ * operation to USART_DR register.
+ * @note RXNE flag can be also cleared by a read to the USART_DR register.
+ * @note TC flag can be also cleared by software sequence: a read operation to
+ * USART_SR register followed by a write operation to USART_DR register.
+ * @note TXE flag is cleared only by a write to the USART_DR register.
+ *
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
+
+
+/** @brief Enables or disables the specified IRDA interrupt.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __INTERRUPT__: specifies the IRDA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
+ * @arg IRDA_IT_TC: Transmission complete interrupt
+ * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
+ * @arg IRDA_IT_IDLE: Idle line detection interrupt
+ * @arg IRDA_IT_PE: Parity Error interrupt
+ * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @param NewState: new state of the specified IRDA interrupt.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+#define IRDA_IT_MASK ((uint32_t)0x0000FFFF)
+#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
+ (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK)))
+#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
+ (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK)))
+
+/** @brief Checks whether the specified IRDA interrupt has occurred or not.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __IT__: specifies the IRDA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
+ * @arg IRDA_IT_TC: Transmission complete interrupt
+ * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
+ * @arg IRDA_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_ERR: Error interrupt
+ * @arg IRDA_IT_PE: Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK))
+
+
+
+#define __IRDA_ENABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+#define __IRDA_DISABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+#define __DIV(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
+#define __DIVMANT(_PCLK_, _BAUD_) (__DIV((_PCLK_), (_BAUD_))/100)
+#define __DIVFRAQ(_PCLK_, _BAUD_) (((__DIV((_PCLK_), (_BAUD_)) - (__DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define __IRDA_BRR(_PCLK_, _BAUD_) ((__DIVMANT((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
+
+#define IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201)
+
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
+
+/* Peripheral State functions **************************************************/
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
+uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_IRDA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_iwdg.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,255 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_iwdg.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of IWDG HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_IWDG_H
+#define __STM32F4xx_HAL_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup IWDG
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief IWDG HAL State Structure definition
+ */
+typedef enum
+{
+ HAL_IWDG_STATE_RESET = 0x00, /*!< IWDG not yet initialized or disabled */
+ HAL_IWDG_STATE_READY = 0x01, /*!< IWDG initialized and ready for use */
+ HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */
+ HAL_IWDG_STATE_TIMEOUT = 0x03, /*!< IWDG timeout state */
+ HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */
+
+}HAL_IWDG_StateTypeDef;
+
+/**
+ * @brief IWDG Init structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
+ This parameter can be a value of @ref IWDG_Prescaler */
+
+ uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+
+}IWDG_InitTypeDef;
+
+/**
+ * @brief IWDG handle Structure definition
+ */
+typedef struct
+{
+ IWDG_TypeDef *Instance; /*!< Register base address */
+
+ IWDG_InitTypeDef Init; /*!< IWDG required parameters */
+
+ HAL_LockTypeDef Lock; /*!< IWDG locking object */
+
+ __IO HAL_IWDG_StateTypeDef State; /*!< IWDG communication state */
+
+}IWDG_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Constants
+ * @{
+ */
+
+/** @defgroup IWDG_Registers_BitMask
+ * @{
+ */
+/* --- KR Register ---*/
+/* KR register bit mask */
+#define KR_KEY_RELOAD ((uint32_t)0xAAAA) /*!< IWDG reload counter enable */
+#define KR_KEY_ENABLE ((uint32_t)0xCCCC) /*!< IWDG peripheral enable */
+#define KR_KEY_EWA ((uint32_t)0x5555) /*!< IWDG KR write Access enable */
+#define KR_KEY_DWA ((uint32_t)0x0000) /*!< IWDG KR write Access disable */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Flag_definition
+ * @{
+ */
+#define IWDG_FLAG_PVU ((uint32_t)0x0001) /*!< Watchdog counter prescaler value update flag */
+#define IWDG_FLAG_RVU ((uint32_t)0x0002) /*!< Watchdog counter reload value update flag */
+
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || \
+ ((FLAG) == IWDG_FLAG_RVU))
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Prescaler
+ * @{
+ */
+#define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */
+#define IWDG_PRESCALER_8 ((uint8_t)0x01) /*!< IWDG prescaler set to 8 */
+#define IWDG_PRESCALER_16 ((uint8_t)0x02) /*!< IWDG prescaler set to 16 */
+#define IWDG_PRESCALER_32 ((uint8_t)0x03) /*!< IWDG prescaler set to 32 */
+#define IWDG_PRESCALER_64 ((uint8_t)0x04) /*!< IWDG prescaler set to 64 */
+#define IWDG_PRESCALER_128 ((uint8_t)0x05) /*!< IWDG prescaler set to 128 */
+#define IWDG_PRESCALER_256 ((uint8_t)0x06) /*!< IWDG prescaler set to 256 */
+
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_PRESCALER_4) || \
+ ((PRESCALER) == IWDG_PRESCALER_8) || \
+ ((PRESCALER) == IWDG_PRESCALER_16) || \
+ ((PRESCALER) == IWDG_PRESCALER_32) || \
+ ((PRESCALER) == IWDG_PRESCALER_64) || \
+ ((PRESCALER) == IWDG_PRESCALER_128)|| \
+ ((PRESCALER) == IWDG_PRESCALER_256))
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Reload_Value
+ * @{
+ */
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset IWDG handle state
+ * @param __HANDLE__: IWDG handle
+ * @retval None
+ */
+#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
+
+/**
+ * @brief Enables the IWDG peripheral.
+ * @param __HANDLE__: IWDG handle
+ * @retval None
+ */
+#define __HAL_IWDG_START(__HANDLE__) ((__HANDLE__)->Instance->KR |= KR_KEY_ENABLE)
+
+/**
+ * @brief Reloads IWDG counter with value defined in the reload register
+ * (write access to IWDG_PR and IWDG_RLR registers disabled).
+ * @param __HANDLE__: IWDG handle
+ * @retval None
+ */
+#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) (((__HANDLE__)->Instance->KR) |= KR_KEY_RELOAD)
+
+/**
+ * @brief Enables write access to IWDG_PR and IWDG_RLR registers.
+ * @param __HANDLE__: IWDG handle
+ * @retval None
+ */
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) (((__HANDLE__)->Instance->KR) |= KR_KEY_EWA)
+
+/**
+ * @brief Disables write access to IWDG_PR and IWDG_RLR registers.
+ * @param __HANDLE__: IWDG handle
+ * @retval None
+ */
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) (((__HANDLE__)->Instance->KR) |= KR_KEY_DWA)
+
+/**
+ * @brief Gets the selected IWDG's flag status.
+ * @param __HANDLE__: IWDG handle
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag
+ * @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clears the IWDG's pending flags.
+ * @param __HANDLE__: IWDG handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag
+ * @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag
+ * @retval None
+ */
+#define __HAL_IWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
+void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
+
+/* I/O operation functions ****************************************************/
+HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg);
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
+
+/* Peripheral State functions ************************************************/
+HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_IWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_ltdc.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,582 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_ltdc.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of LTDC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_LTDC_H
+#define __STM32F4xx_HAL_LTDC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F429xx) || defined(STM32F439xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup LTDC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+#define MAX_LAYER 2
+
+/**
+ * @brief LTDC color structure definition
+ */
+typedef struct
+{
+ uint8_t Blue; /*!< Configures the blue value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+ uint8_t Green; /*!< Configures the green value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+ uint8_t Red; /*!< Configures the red value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+ uint8_t Reserved; /*!< Reserved 0xFF */
+} LTDC_ColorTypeDef;
+
+/**
+ * @brief LTDC Init structure definition
+ */
+typedef struct
+{
+ uint32_t HSPolarity; /*!< configures the horizontal synchronization polarity.
+ This parameter can be one value of @ref LTDC_HS_POLARITY */
+
+ uint32_t VSPolarity; /*!< configures the vertical synchronization polarity.
+ This parameter can be one value of @ref LTDC_VS_POLARITY */
+
+ uint32_t DEPolarity; /*!< configures the data enable polarity.
+ This parameter can be one of value of @ref LTDC_DE_POLARITY */
+
+ uint32_t PCPolarity; /*!< configures the pixel clock polarity.
+ This parameter can be one of value of @ref LTDC_PC_POLARITY */
+
+ uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width.
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+
+ uint32_t VerticalSync; /*!< configures the number of Vertical synchronization heigh.
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
+
+ uint32_t AccumulatedHBP; /*!< configures the accumulated horizontal back porch width.
+ This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */
+
+ uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch heigh.
+ This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */
+
+ uint32_t AccumulatedActiveW; /*!< configures the accumulated active width.
+ This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */
+
+ uint32_t AccumulatedActiveH; /*!< configures the accumulated active heigh.
+ This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */
+
+ uint32_t TotalWidth; /*!< configures the total width.
+ This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */
+
+ uint32_t TotalHeigh; /*!< configures the total heigh.
+ This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */
+
+ LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */
+} LTDC_InitTypeDef;
+
+
+/**
+ * @brief LTDC Layer structure definition
+ */
+typedef struct
+{
+ uint32_t WindowX0; /*!< Configures the Window Horizontal Start Position.
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+
+ uint32_t WindowX1; /*!< Configures the Window Horizontal Stop Position.
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+
+ uint32_t WindowY0; /*!< Configures the Window vertical Start Position.
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+
+ uint32_t WindowY1; /*!< Configures the Window vertical Stop Position.
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t PixelFormat; /*!< Specifies the pixel format.
+ This parameter can be one of value of @ref LTDC_Pixelformat */
+
+ uint32_t Alpha; /*!< Specifies the constant alpha used for blending.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+ uint32_t Alpha0; /*!< Configures the default alpha value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+ uint32_t BlendingFactor1; /*!< Select the blending factor 1.
+ This parameter can be one of value of @ref LTDC_BlendingFactor1 */
+
+ uint32_t BlendingFactor2; /*!< Select the blending factor 2.
+ This parameter can be one of value of @ref LTDC_BlendingFactor2 */
+
+ uint32_t FBStartAdress; /*!< Configures the color frame buffer address */
+
+ uint32_t ImageWidth; /*!< Configures the color frame buffer line length.
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */
+
+ uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer.
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
+
+ LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */
+} LTDC_LayerCfgTypeDef;
+
+/**
+ * @brief HAL LTDC State structures definition
+ */
+typedef enum
+{
+ HAL_LTDC_STATE_RESET = 0x00, /*!< LTDC not yet initialized or disabled */
+ HAL_LTDC_STATE_READY = 0x01, /*!< LTDC initialized and ready for use */
+ HAL_LTDC_STATE_BUSY = 0x02, /*!< LTDC internal process is ongoing */
+ HAL_LTDC_STATE_TIMEOUT = 0x03, /*!< LTDC Timeout state */
+ HAL_LTDC_STATE_ERROR = 0x04 /*!< LTDC state error */
+}HAL_LTDC_StateTypeDef;
+
+/**
+ * @brief LTDC handle Structure definition
+ */
+typedef struct
+{
+ LTDC_TypeDef *Instance; /*!< LTDC Register base address */
+
+ LTDC_InitTypeDef Init; /*!< LTDC parameters */
+
+ LTDC_LayerCfgTypeDef LayerCfg[MAX_LAYER]; /*!< LTDC Layers parameters */
+
+ HAL_LockTypeDef Lock; /*!< LTDC Lock */
+
+ __IO HAL_LTDC_StateTypeDef State; /*!< LTDC state */
+
+ __IO uint32_t ErrorCode; /*!< LTDC Error code */
+
+} LTDC_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LTDC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup LTDC_Layer
+ * @{
+ */
+#define IS_LTDC_LAYER(LAYER) ((LAYER) <= MAX_LAYER)
+/**
+ * @}
+ */
+
+/** @defgroup LTDC Error Code
+ * @{
+ */
+#define HAL_LTDC_ERROR_NONE ((uint32_t)0x00000000) /*!< LTDC No error */
+#define HAL_LTDC_ERROR_TE ((uint32_t)0x00000001) /*!< LTDC Transfer error */
+#define HAL_LTDC_ERROR_FU ((uint32_t)0x00000002) /*!< LTDC FIFO Underrun */
+#define HAL_LTDC_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< LTDC Timeout error */
+
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_HS_POLARITY
+ * @{
+ */
+#define LTDC_HSPOLARITY_AL ((uint32_t)0x00000000) /*!< Horizontal Synchronization is active low. */
+#define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */
+
+#define IS_LTDC_HSPOL(HSPOL) (((HSPOL) == LTDC_HSPOLARITY_AL) || \
+ ((HSPOL) == LTDC_HSPOLARITY_AH))
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_VS_POLARITY
+ * @{
+ */
+#define LTDC_VSPOLARITY_AL ((uint32_t)0x00000000) /*!< Vertical Synchronization is active low. */
+#define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */
+
+#define IS_LTDC_VSPOL(VSPOL) (((VSPOL) == LTDC_VSPOLARITY_AL) || \
+ ((VSPOL) == LTDC_VSPOLARITY_AH))
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_DE_POLARITY
+ * @{
+ */
+#define LTDC_DEPOLARITY_AL ((uint32_t)0x00000000) /*!< Data Enable, is active low. */
+#define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */
+
+#define IS_LTDC_DEPOL(DEPOL) (((DEPOL) == LTDC_DEPOLARITY_AL) || \
+ ((DEPOL) == LTDC_DEPOLARITY_AH))
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_PC_POLARITY
+ * @{
+ */
+#define LTDC_PCPOLARITY_IPC ((uint32_t)0x00000000) /*!< input pixel clock. */
+#define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */
+
+#define IS_LTDC_PCPOL(PCPOL) (((PCPOL) == LTDC_PCPOLARITY_IPC) || \
+ ((PCPOL) == LTDC_PCPOLARITY_IIPC))
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_SYNC
+ * @{
+ */
+#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16) /*!< Horizontal synchronization width. */
+#define LTDC_VERTICALSYNC LTDC_SSCR_VSH /*!< Vertical synchronization heigh. */
+
+#define IS_LTDC_HSYNC(HSYNC) ((HSYNC) <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_VSYNC(VSYNC) ((VSYNC) <= LTDC_VERTICALSYNC)
+#define IS_LTDC_AHBP(AHBP) ((AHBP) <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_AVBP(AVBP) ((AVBP) <= LTDC_VERTICALSYNC)
+#define IS_LTDC_AAW(AAW) ((AAW) <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_AAH(AAH) ((AAH) <= LTDC_VERTICALSYNC)
+#define IS_LTDC_TOTALW(TOTALW) ((TOTALW) <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_TOTALH(TOTALH) ((TOTALH) <= LTDC_VERTICALSYNC)
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_BACK_COLOR
+ * @{
+ */
+#define LTDC_COLOR ((uint32_t)0x000000FF) /*!< Color mask */
+
+#define IS_LTDC_BLUEVALUE(BBLUE) ((BBLUE) <= LTDC_COLOR)
+#define IS_LTDC_GREENVALUE(BGREEN) ((BGREEN) <= LTDC_COLOR)
+#define IS_LTDC_REDVALUE(BRED) ((BRED) <= LTDC_COLOR)
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_BlendingFactor1
+ * @{
+ */
+#define LTDC_BLENDING_FACTOR1_CA ((uint32_t)0x00000400) /*!< Blending factor : Cte Alpha */
+#define LTDC_BLENDING_FACTOR1_PAxCA ((uint32_t)0x00000600) /*!< Blending factor : Cte Alpha x Pixel Alpha*/
+
+#define IS_LTDC_BLENDING_FACTOR1(BlendingFactor1) (((BlendingFactor1) == LTDC_BLENDING_FACTOR1_CA) || \
+ ((BlendingFactor1) == LTDC_BLENDING_FACTOR1_PAxCA))
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_BlendingFactor2
+ * @{
+ */
+#define LTDC_BLENDING_FACTOR2_CA ((uint32_t)0x00000005) /*!< Blending factor : Cte Alpha */
+#define LTDC_BLENDING_FACTOR2_PAxCA ((uint32_t)0x00000007) /*!< Blending factor : Cte Alpha x Pixel Alpha*/
+
+#define IS_LTDC_BLENDING_FACTOR2(BlendingFactor2) (((BlendingFactor2) == LTDC_BLENDING_FACTOR2_CA) || \
+ ((BlendingFactor2) == LTDC_BLENDING_FACTOR2_PAxCA))
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_Pixelformat
+ * @{
+ */
+#define LTDC_PIXEL_FORMAT_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_RGB888 ((uint32_t)0x00000001) /*!< RGB888 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_RGB565 ((uint32_t)0x00000002) /*!< RGB565 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_L8 ((uint32_t)0x00000005) /*!< L8 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_AL44 ((uint32_t)0x00000006) /*!< AL44 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_AL88 ((uint32_t)0x00000007) /*!< AL88 LTDC pixel format */
+
+#define IS_LTDC_PIXEL_FORMAT(Pixelformat) (((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB8888) || ((Pixelformat) == LTDC_PIXEL_FORMAT_RGB888) || \
+ ((Pixelformat) == LTDC_PIXEL_FORMAT_RGB565) || ((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB1555) || \
+ ((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB4444) || ((Pixelformat) == LTDC_PIXEL_FORMAT_L8) || \
+ ((Pixelformat) == LTDC_PIXEL_FORMAT_AL44) || ((Pixelformat) == LTDC_PIXEL_FORMAT_AL88))
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_Alpha
+ * @{
+ */
+#define LTDC_ALPHA LTDC_LxCACR_CONSTA /*!< LTDC Cte Alpha mask */
+
+#define IS_LTDC_ALPHA(ALPHA) ((ALPHA) <= LTDC_ALPHA)
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_LAYER_Config
+ * @{
+ */
+#define LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16) /*!< LTDC Layer stop position */
+#define LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS /*!< LTDC Layer start position */
+
+#define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL /*!< LTDC Layer Line length */
+#define LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR /*!< LTDC Layer Line number */
+
+#define IS_LTDC_HCONFIGST(HCONFIGST) ((HCONFIGST) <= LTDC_STARTPOSITION)
+#define IS_LTDC_HCONFIGSP(HCONFIGSP) ((HCONFIGSP) <= LTDC_STOPPOSITION)
+#define IS_LTDC_VCONFIGST(VCONFIGST) ((VCONFIGST) <= LTDC_STARTPOSITION)
+#define IS_LTDC_VCONFIGSP(VCONFIGSP) ((VCONFIGSP) <= LTDC_STOPPOSITION)
+
+#define IS_LTDC_CFBP(CFBP) ((CFBP) <= LTDC_COLOR_FRAME_BUFFER)
+#define IS_LTDC_CFBLL(CFBLL) ((CFBLL) <= LTDC_COLOR_FRAME_BUFFER)
+
+#define IS_LTDC_CFBLNBR(CFBLNBR) ((CFBLNBR) <= LTDC_LINE_NUMBER)
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_LIPosition
+ * @{
+ */
+#define IS_LTDC_LIPOS(LIPOS) ((LIPOS) <= 0x7FF)
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_Interrupts
+ * @{
+ */
+#define LTDC_IT_LI LTDC_IER_LIE
+#define LTDC_IT_FU LTDC_IER_FUIE
+#define LTDC_IT_TE LTDC_IER_TERRIE
+#define LTDC_IT_RR LTDC_IER_RRIE
+
+#define IS_LTDC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFF0) == 0x00) && ((IT) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup LTDC_Flag
+ * @{
+ */
+#define LTDC_FLAG_LI LTDC_ISR_LIF
+#define LTDC_FLAG_FU LTDC_ISR_FUIF
+#define LTDC_FLAG_TE LTDC_ISR_TERRIF
+#define LTDC_FLAG_RR LTDC_ISR_RRIF
+
+#define IS_LTDC_FLAG(FLAG) (((FLAG) == LTDC_FLAG_LI) || ((FLAG) == LTDC_FLAG_FU) || \
+ ((FLAG) == LTDC_FLAG_TERR) || ((FLAG) == LTDC_FLAG_RR))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset LTDC handle state
+ * @param __HANDLE__: specifies the LTDC handle.
+ * @retval None
+ */
+#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET)
+
+/**
+ * @brief Enable the LTDC.
+ * @param __HANDLE__: LTDC handle
+ * @retval None.
+ */
+#define __HAL_LTDC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN)
+
+/**
+ * @brief Disable the LTDC.
+ * @param __HANDLE__: LTDC handle
+ * @retval None.
+ */
+#define __HAL_LTDC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN))
+
+/**
+ * @brief Enable the LTDC Layer.
+ * @param __HANDLE__: LTDC handle
+ * @param __LAYER__: Specify the layer to be enabled
+ This parameter can be 0 or 1
+ * @retval None.
+ */
+#define __HAL_LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)(((uint32_t)((__HANDLE__)->Instance)) + 0x84 + (0x80*(__LAYER__))))
+
+#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((__HAL_LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)
+
+/**
+ * @brief Disable the LTDC Layer.
+ * @param __HANDLE__: LTDC handle
+ * @param __LAYER__: Specify the layer to be disabled
+ This parameter can be 0 or 1
+ * @retval None.
+ */
+#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((__HAL_LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)
+
+/**
+ * @brief Reload Layer Configuration.
+ * @param __HANDLE__: LTDC handle
+ * @retval None.
+ */
+#define __HAL_LTDC_RELOAD_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR)
+
+/* Interrupt & Flag management */
+/**
+ * @brief Get the LTDC pending flags.
+ * @param __HANDLE__: LTDC handle
+ * @param __FLAG__: Get the specified flag.
+ * This parameter can be any combination of the following values:
+ * @arg LTDC_FLAG_LI: Line Interrupt flag
+ * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
+ * @arg LTDC_FLAG_TE: Transfer Error interrupt flag
+ * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
+
+/**
+ * @brief Clears the LTDC pending flags.
+ * @param __HANDLE__: LTDC handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg LTDC_FLAG_LI: Line Interrupt flag
+ * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
+ * @arg LTDC_FLAG_TE: Transfer Error interrupt flag
+ * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
+ * @retval None
+ */
+#define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR |= (__FLAG__))
+
+/**
+ * @brief Enables the specified LTDC interrupts.
+ * @param __HANDLE__: LTDC handle
+ * @param __INTERRUPT__: specifies the LTDC interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg LTDC_IT_LI: Line Interrupt flag
+ * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
+ * @arg LTDC_IT_TE: Transfer Error interrupt flag
+ * @arg LTDC_IT_RR: Register Reload Interrupt Flag
+ * @retval None
+ */
+#define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified LTDC interrupts.
+ * @param __HANDLE__: LTDC handle
+ * @param __INTERRUPT__: specifies the LTDC interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg LTDC_IT_LI: Line Interrupt flag
+ * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
+ * @arg LTDC_IT_TE: Transfer Error interrupt flag
+ * @arg LTDC_IT_RR: Register Reload Interrupt Flag
+ * @retval None
+ */
+#define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
+
+/**
+ * @brief Checks whether the specified LTDC interrupt has occurred or not.
+ * @param __HANDLE__: LTDC handle
+ * @param __INTERRUPT__: specifies the LTDC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg LTDC_IT_LI: Line Interrupt flag
+ * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
+ * @arg LTDC_IT_TE: Transfer Error interrupt flag
+ * @arg LTDC_IT_RR: Register Reload Interrupt Flag
+ * @retval The state of INTERRUPT (SET or RESET).
+ */
+#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->ISR & (__INTERRUPT__))
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc);
+HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc);
+void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc);
+void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc);
+void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc);
+void HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc);
+
+/* IO operation functions *****************************************************/
+void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc);
+
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line);
+HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc);
+HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc);
+
+/* Peripheral State functions *************************************************/
+HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc);
+uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
+
+#endif /* STM32F429xx || STM32F439xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_LTDC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_nand.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,239 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_nand.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of NAND HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_NAND_H
+#define __STM32F4xx_HAL_NAND_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+ #include "stm32f4xx_ll_fsmc.h"
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+ #include "stm32f4xx_ll_fmc.h"
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup NAND
+ * @{
+ */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Exported typedef ----------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HAL NAND State structures definition
+ */
+typedef enum
+{
+ HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */
+ HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */
+ HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */
+ HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */
+}HAL_NAND_StateTypeDef;
+
+/**
+ * @brief NAND Memory electronic signature Structure definition
+ */
+typedef struct
+{
+ /*<! NAND memory electronic signature maker and device IDs */
+
+ uint8_t Maker_Id;
+
+ uint8_t Device_Id;
+
+ uint8_t Third_Id;
+
+ uint8_t Fourth_Id;
+}NAND_IDTypeDef;
+
+/**
+ * @brief NAND Memory address Structure definition
+ */
+typedef struct
+{
+ uint16_t Page; /*!< NAND memory Page address */
+
+ uint16_t Zone; /*!< NAND memory Zone address */
+
+ uint16_t Block; /*!< NAND memory Block address */
+
+}NAND_AddressTypedef;
+
+/**
+ * @brief NAND Memory info Structure definition
+ */
+typedef struct
+{
+ uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in K. bytes */
+
+ uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in K. bytes */
+
+ uint32_t BlockSize; /*!< NAND memory block size number of pages */
+
+ uint32_t BlockNbr; /*!< NAND memory number of blocks */
+
+ uint32_t ZoneSize; /*!< NAND memory zone size measured in number of blocks */
+}NAND_InfoTypeDef;
+
+/**
+ * @brief NAND handle Structure definition
+ */
+typedef struct
+{
+ FMC_NAND_TypeDef *Instance; /*!< Register base address */
+
+ FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
+
+ HAL_LockTypeDef Lock; /*!< NAND locking object */
+
+ __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
+
+ NAND_InfoTypeDef Info; /*!< NAND characteristic information structure */
+}NAND_HandleTypeDef;
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup NAND_Exported_Constants
+ * @{
+ */
+#define NAND_DEVICE1 ((uint32_t)0x70000000)
+#define NAND_DEVICE2 ((uint32_t)0x80000000)
+#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000)
+
+#define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
+#define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
+
+#define NAND_CMD_AREA_A ((uint8_t)0x00)
+#define NAND_CMD_AREA_B ((uint8_t)0x01)
+#define NAND_CMD_AREA_C ((uint8_t)0x50)
+
+/* NAND memory status */
+#define NAND_VALID_ADDRESS ((uint32_t)0x00000100)
+#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200)
+#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)
+#define NAND_BUSY ((uint32_t)0x00000000)
+#define NAND_ERROR ((uint32_t)0x00000001)
+#define NAND_READY ((uint32_t)0x00000040)
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset NAND handle state
+ * @param __HANDLE__: specifies the NAND handle.
+ * @retval None
+ */
+#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
+
+/**
+ * @brief NAND memory address computation.
+ * @param __ADDRESS__: NAND memory address.
+ * @param __HANDLE__ : NAND handle.
+ * @retval NAND Raw address value
+ */
+#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.BlockSize)))* ((__HANDLE__)->Info.ZoneSize)))
+
+/**
+ * @brief NAND memory address cycling.
+ * @param __ADDRESS__: NAND memory address.
+ * @retval NAND address cycling value.
+ */
+#define ADDR_1st_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__)& 0xFF) /* 1st addressing cycle */
+#define ADDR_2nd_CYCLE(__ADDRESS__) (uint8_t)(((__ADDRESS__)& 0xFF00) >> 8) /* 2nd addressing cycle */
+#define ADDR_3rd_CYCLE(__ADDRESS__) (uint8_t)(((__ADDRESS__)& 0xFF0000) >> 16) /* 3rd addressing cycle */
+#define ADDR_4th_CYCLE(__ADDRESS__) (uint8_t)(((__ADDRESS__)& 0xFF000000) >> 24) /* 4th addressing cycle */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
+HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
+void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
+void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
+void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
+void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
+
+/* IO operation functions ****************************************************/
+HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
+HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress);
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress);
+
+/* NAND Control functions ****************************************************/
+HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
+
+/* NAND State functions *******************************************************/
+HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_NAND_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_nor.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,242 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_nor.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of NOR HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_NOR_H
+#define __STM32F4xx_HAL_NOR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+ #include "stm32f4xx_ll_fsmc.h"
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+ #include "stm32f4xx_ll_fmc.h"
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup NOR
+ * @{
+ */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Exported typedef ----------------------------------------------------------*/
+/**
+ * @brief HAL SRAM State structures definition
+ */
+typedef enum
+{
+ HAL_NOR_STATE_RESET = 0x00, /*!< NOR not yet initialized or disabled */
+ HAL_NOR_STATE_READY = 0x01, /*!< NOR initialized and ready for use */
+ HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */
+ HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */
+ HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */
+}HAL_NOR_StateTypeDef;
+
+/**
+ * @brief FMC NOR Status typedef
+ */
+typedef enum
+{
+ NOR_SUCCESS = 0,
+ NOR_ONGOING,
+ NOR_ERROR,
+ NOR_TIMEOUT
+}NOR_StatusTypedef;
+
+/**
+ * @brief FMC NOR ID typedef
+ */
+typedef struct
+{
+ uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
+
+ uint16_t Device_Code1;
+
+ uint16_t Device_Code2;
+
+ uint16_t Device_Code3; /*!< Defines the devices' codes used to identify the memory.
+ These codes can be accessed by performing read operations with specific
+ control signals and addresses set.They can also be accessed by issuing
+ an Auto Select command */
+}NOR_IDTypeDef;
+
+/**
+ * @brief FMC NOR CFI typedef
+ */
+typedef struct
+{
+ /*!< Defines the information stored in the memory's Common flash interface
+ which contains a description of various electrical and timing parameters,
+ density information and functions supported by the memory */
+
+ uint16_t CFI_1;
+
+ uint16_t CFI_2;
+
+ uint16_t CFI_3;
+
+ uint16_t CFI_4;
+}NOR_CFITypeDef;
+
+/**
+ * @brief NOR handle Structure definition
+ */
+typedef struct
+{
+ FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
+
+ FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
+
+ FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
+
+ HAL_LockTypeDef Lock; /*!< NOR locking object */
+
+ __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
+
+}NOR_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup NOR_Exported_Constants
+ * @{
+ */
+/* NOR device IDs addresses */
+#define MC_ADDRESS ((uint16_t)0x0000)
+#define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
+#define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
+#define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
+
+/* NOR CFI IDs addresses */
+#define CFI1_ADDRESS ((uint16_t)0x61)
+#define CFI2_ADDRESS ((uint16_t)0x62)
+#define CFI3_ADDRESS ((uint16_t)0x63)
+#define CFI4_ADDRESS ((uint16_t)0x64)
+
+/* NOR operation wait timeout */
+#define NOR_TMEOUT ((uint16_t)0xFFFF)
+
+/* #define NOR_MEMORY_16B */
+#define NOR_MEMORY_8B
+
+/* NOR memory device read/write start address */
+#define NOR_MEMORY_ADRESS ((uint32_t)0x60000000)
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset NOR handle state
+ * @param __HANDLE__: specifies the NOR handle.
+ * @retval None
+ */
+#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
+
+/**
+ * @brief NOR memory address shifting.
+ * @param __ADDRESS__: NOR memory address
+ * @retval NOR shifted address value
+ */
+#ifdef NOR_MEMORY_8B
+ #define __NOR_ADDR_SHIFT(__ADDRESS__) (uint32_t)(NOR_MEMORY_ADRESS + (2 * (__ADDRESS__)))
+#else /* NOR_MEMORY_16B */
+ #define __NOR_ADDR_SHIFT(__ADDRESS__) (uint32_t)(NOR_MEMORY_ADRESS + (__ADDRESS__))
+#endif /* NOR_MEMORY_8B */
+
+/**
+ * @brief NOR memory write data to specified address.
+ * @param __ADDRESS__: NOR memory address
+ * @param __DATA__: Data to write
+ * @retval None
+ */
+#define __NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
+
+/* I/O operation functions ***************************************************/
+HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
+HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
+HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
+
+HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
+HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
+HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
+
+/* NOR Control functions *****************************************************/
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
+
+/* NOR State functions ********************************************************/
+HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
+NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_NOR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_pccard.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,185 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_pccard.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of PCCARD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_PCCARD_H
+#define __STM32F4xx_HAL_PCCARD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+ #include "stm32f4xx_ll_fsmc.h"
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+ #include "stm32f4xx_ll_fmc.h"
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PCCARD
+ * @{
+ */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Exported typedef ----------------------------------------------------------*/
+
+/**
+ * @brief HAL SRAM State structures definition
+ */
+typedef enum
+{
+ HAL_PCCARD_STATE_RESET = 0x00, /*!< PCCARD peripheral not yet initialized or disabled */
+ HAL_PCCARD_STATE_READY = 0x01, /*!< PCCARD peripheral ready */
+ HAL_PCCARD_STATE_BUSY = 0x02, /*!< PCCARD peripheral busy */
+ HAL_PCCARD_STATE_ERROR = 0x04 /*!< PCCARD peripheral error */
+}HAL_PCCARD_StateTypeDef;
+
+typedef enum
+{
+ CF_SUCCESS = 0,
+ CF_ONGOING,
+ CF_ERROR,
+ CF_TIMEOUT
+}CF_StatusTypedef;
+
+/**
+ * @brief FMC_PCCARD handle Structure definition
+ */
+typedef struct
+{
+ FMC_PCCARD_TypeDef *Instance; /*!< Register base address for PCCARD device */
+
+ FMC_PCCARD_InitTypeDef Init; /*!< PCCARD device control configuration parameters */
+
+ __IO HAL_PCCARD_StateTypeDef State; /*!< PCCARD device access state */
+
+ HAL_LockTypeDef Lock; /*!< PCCARD Lock */
+
+}PCCARD_HandleTypeDef;
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PCCARD_Exported_Constants
+ * @{
+ */
+
+#define CF_DEVICE_ADDRESS ((uint32_t)0x90000000)
+#define CF_ATTRIBUTE_SPACE_ADDRESS ((uint32_t)0x98000000) /* Attribute space size to @0x9BFF FFFF */
+#define CF_COMMON_SPACE_ADDRESS CF_DEVICE_ADDRESS /* Common space size to @0x93FF FFFF */
+#define CF_IO_SPACE_ADDRESS ((uint32_t)0x9C000000) /* IO space size to @0x9FFF FFFF */
+#define CF_IO_SPACE_PRIMARY_ADDR ((uint32_t)0x9C0001F0) /* IO space size to @0x9FFF FFFF */
+
+/* Compact Flash-ATA registers description */
+#define CF_DATA ((uint8_t)0x00) /* Data register */
+#define CF_SECTOR_COUNT ((uint8_t)0x02) /* Sector Count register */
+#define CF_SECTOR_NUMBER ((uint8_t)0x03) /* Sector Number register */
+#define CF_CYLINDER_LOW ((uint8_t)0x04) /* Cylinder low register */
+#define CF_CYLINDER_HIGH ((uint8_t)0x05) /* Cylinder high register */
+#define CF_CARD_HEAD ((uint8_t)0x06) /* Card/Head register */
+#define CF_STATUS_CMD ((uint8_t)0x07) /* Status(read)/Command(write) register */
+#define CF_STATUS_CMD_ALTERNATE ((uint8_t)0x0E) /* Alternate Status(read)/Command(write) register */
+#define CF_COMMON_DATA_AREA ((uint16_t)0x0400) /* Start of data area (for Common access only!) */
+
+/* Compact Flash-ATA commands */
+#define CF_READ_SECTOR_CMD ((uint8_t)0x20)
+#define CF_WRITE_SECTOR_CMD ((uint8_t)0x30)
+#define CF_ERASE_SECTOR_CMD ((uint8_t)0xC0)
+#define CF_IDENTIFY_CMD ((uint8_t)0xEC)
+
+/* Compact Flash status */
+#define CF_TIMEOUT_ERROR ((uint8_t)0x60)
+#define CF_BUSY ((uint8_t)0x80)
+#define CF_PROGR ((uint8_t)0x01)
+#define CF_READY ((uint8_t)0x40)
+
+#define CF_SECTOR_SIZE ((uint32_t)255) /* In half words */
+
+/**
+ * @}
+ */
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset PCCARD handle state
+ * @param __HANDLE__: specifies the PCCARD handle.
+ * @retval None
+ */
+#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET)
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
+HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
+void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
+void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_CF_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus);
+HAL_StatusTypeDef HAL_CF_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
+HAL_StatusTypeDef HAL_CF_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
+HAL_StatusTypeDef HAL_CF_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus);
+HAL_StatusTypeDef HAL_CF_Reset(PCCARD_HandleTypeDef *hpccard);
+void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
+void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
+
+/* PCCARD State functions *******************************************************/
+HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard);
+CF_StatusTypedef HAL_CF_GetStatus(PCCARD_HandleTypeDef *hpccard);
+CF_StatusTypedef HAL_CF_ReadStatus(PCCARD_HandleTypeDef *hpccard);
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_PCCARD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_pcd.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,272 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_pcd.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of PCD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_PCD_H
+#define __STM32F4xx_HAL_PCD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_usb.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PCD
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+ /**
+ * @brief PCD State structures definition
+ */
+typedef enum
+{
+ PCD_READY = 0x00,
+ PCD_ERROR = 0x01,
+ PCD_BUSY = 0x02,
+ PCD_TIMEOUT = 0x03
+} PCD_StateTypeDef;
+
+
+typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
+typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;
+typedef USB_OTG_EPTypeDef PCD_EPTypeDef ;
+
+/**
+ * @brief PCD Handle Structure definition
+ */
+typedef struct
+{
+ PCD_TypeDef *Instance; /*!< Register base address */
+ PCD_InitTypeDef Init; /*!< PCD required parameters */
+ PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */
+ PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */
+ HAL_LockTypeDef Lock; /*!< PCD peripheral status */
+ __IO PCD_StateTypeDef State; /*!< PCD communication state */
+ uint32_t Setup[12]; /*!< Setup packet buffer */
+ void *pData; /*!< Pointer to upper stack Handler */
+
+} PCD_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Constants
+ * @{
+ */
+
+/** @defgroup PCD_Speed
+ * @{
+ */
+#define PCD_SPEED_HIGH 0
+#define PCD_SPEED_HIGH_IN_FULL 1
+#define PCD_SPEED_FULL 2
+/**
+ * @}
+ */
+
+ /** @defgroup PCD_PHY_Module
+ * @{
+ */
+#define PCD_PHY_ULPI 1
+#define PCD_PHY_EMBEDDED 2
+/**
+ * @}
+ */
+
+/** @defgroup PCD_Instance_definition
+ * @{
+ */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+#elif defined(STM32F401xC) || defined(STM32F401xE)
+ #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup PCD_Interrupt_Clock
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+#define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
+
+#define __HAL_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) |= (__INTERRUPT__))
+#define __HAL_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
+
+
+#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
+ ~(USB_OTG_PCGCCTL_STOPCLK)
+
+
+#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
+
+#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
+
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE ((uint32_t)0x08)
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE ((uint32_t)0x0C)
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE ((uint32_t)0x10)
+
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE ((uint32_t)0x08)
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE ((uint32_t)0x0C)
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE ((uint32_t)0x10)
+
+
+#define USB_HS_EXTI_LINE_WAKEUP ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB HS EXTI Line */
+#define USB_FS_EXTI_LINE_WAKEUP ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
+
+
+
+#define __HAL_USB_HS_EXTI_ENABLE_IT() EXTI->IMR |= (USB_HS_EXTI_LINE_WAKEUP)
+#define __HAL_USB_HS_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_HS_EXTI_LINE_WAKEUP)
+#define __HAL_USB_HS_EXTI_GET_FLAG() EXTI->PR & (USB_HS_EXTI_LINE_WAKEUP)
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG() EXTI->PR = (USB_HS_EXTI_LINE_WAKEUP)
+
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER() EXTI->FTSR &= ~(USB_HS_EXTI_LINE_WAKEUP);\
+ EXTI->RTSR |= USB_HS_EXTI_LINE_WAKEUP
+
+
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER() EXTI->FTSR |= (USB_HS_EXTI_LINE_WAKEUP);\
+ EXTI->RTSR &= ~(USB_HS_EXTI_LINE_WAKEUP)
+
+
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(USB_HS_EXTI_LINE_WAKEUP);\
+ EXTI->FTSR &= ~(USB_HS_EXTI_LINE_WAKEUP;)\
+ EXTI->RTSR |= USB_HS_EXTI_LINE_WAKEUP;\
+ EXTI->FTSR |= USB_HS_EXTI_LINE_WAKEUP
+
+
+#define __HAL_USB_FS_EXTI_ENABLE_IT() EXTI->IMR |= USB_FS_EXTI_LINE_WAKEUP
+#define __HAL_USB_FS_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_FS_EXTI_LINE_WAKEUP)
+#define __HAL_USB_FS_EXTI_GET_FLAG() EXTI->PR & (USB_FS_EXTI_LINE_WAKEUP)
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG() EXTI->PR = USB_FS_EXTI_LINE_WAKEUP
+
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER() EXTI->FTSR &= ~(USB_FS_EXTI_LINE_WAKEUP);\
+ EXTI->RTSR |= USB_FS_EXTI_LINE_WAKEUP
+
+
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER() EXTI->FTSR |= (USB_FS_EXTI_LINE_WAKEUP);\
+ EXTI->RTSR &= ~(USB_FS_EXTI_LINE_WAKEUP)
+
+
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(USB_FS_EXTI_LINE_WAKEUP);\
+ EXTI->FTSR &= ~(USB_FS_EXTI_LINE_WAKEUP);\
+ EXTI->RTSR |= USB_FS_EXTI_LINE_WAKEUP;\
+ EXTI->FTSR |= USB_FS_EXTI_LINE_WAKEUP
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
+
+/* I/O operation functions *****************************************************/
+ /* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
+
+
+
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
+HAL_StatusTypeDef HAL_PCD_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
+HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
+/* Peripheral State functions **************************************************/
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_PCD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_pwr.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,333 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_pwr.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of PWR HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_PWR_H
+#define __STM32F4xx_HAL_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PWR
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/**
+ * @brief PWR PVD configuration structure definition
+ */
+typedef struct
+{
+ uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
+ This parameter can be a value of @ref PWR_PVD_detection_level */
+
+ uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref PWR_PVD_Mode */
+}PWR_PVDTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* ------------- PWR registers bit address in the alias region ---------------*/
+#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+/* Alias word address of DBP bit */
+#define CR_OFFSET (PWR_OFFSET + 0x00)
+#define DBP_BitNumber 0x08
+#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
+
+/* Alias word address of PVDE bit */
+#define PVDE_BitNumber 0x04
+#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
+
+/* Alias word address of FPDS bit */
+#define FPDS_BitNumber 0x09
+#define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4))
+
+/* Alias word address of PMODE bit */
+#define PMODE_BitNumber 0x0E
+#define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4))
+
+/* --- CSR Register ---*/
+/* Alias word address of EWUP bit */
+#define CSR_OFFSET (PWR_OFFSET + 0x04)
+#define EWUP_BitNumber 0x08
+#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
+
+/* Alias word address of BRE bit */
+#define BRE_BitNumber 0x09
+#define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4))
+
+/** @defgroup PWR_Exported_Constants
+ * @{
+ */
+
+/** @defgroup PWR_WakeUp_Pins
+ * @{
+ */
+
+#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP
+#define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1)
+/**
+ * @}
+ */
+
+/** @defgroup PWR_PVD_detection_level
+ * @{
+ */
+#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
+#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
+#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
+#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
+#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
+#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
+#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
+#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
+ ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
+ ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
+ ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
+/**
+ * @}
+ */
+
+/** @defgroup PWR_PVD_Mode
+ * @{
+ */
+#define PWR_MODE_EVT ((uint32_t)0x00000000) /*!< No Interrupt */
+#define PWR_MODE_IT_RISING ((uint32_t)0x00000001) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_MODE_IT_FALLING ((uint32_t)0x00000002) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_MODE_IT_RISING_FALLING ((uint32_t)0x00000003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_MODE_EVT) || ((MODE) == PWR_MODE_IT_RISING)|| \
+ ((MODE) == PWR_MODE_IT_FALLING) || ((MODE) == PWR_MODE_IT_RISING_FALLING))
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Regulator_state_in_STOP_mode
+ * @{
+ */
+#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
+#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
+
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
+ ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
+/**
+ * @}
+ */
+
+/** @defgroup PWR_SLEEP_mode_entry
+ * @{
+ */
+#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
+#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
+/**
+ * @}
+ */
+
+/** @defgroup PWR_STOP_mode_entry
+ * @{
+ */
+#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
+#define PWR_STOPENTRY_WFE ((uint8_t)0x02)
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Regulator_Voltage_Scale
+ * @{
+ */
+#define PWR_REGULATOR_VOLTAGE_SCALE1 ((uint32_t)0x0000C000)
+#define PWR_REGULATOR_VOLTAGE_SCALE2 ((uint32_t)0x00008000)
+#define PWR_REGULATOR_VOLTAGE_SCALE3 ((uint32_t)0x00004000)
+#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
+ ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
+ ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Flag
+ * @{
+ */
+#define PWR_FLAG_WU PWR_CSR_WUF
+#define PWR_FLAG_SB PWR_CSR_SBF
+#define PWR_FLAG_PVDO PWR_CSR_PVDO
+#define PWR_FLAG_BRR PWR_CSR_BRR
+#define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief macros configure the main internal regulator output voltage.
+ * @param __REGULATOR__: specifies the regulator output voltage to achieve
+ * a tradeoff between performance and power consumption when the device does
+ * not operate at the maximum frequency (refer to the datasheets for more details).
+ * This parameter can be one of the following values:
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
+ * @retval None
+ */
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)))
+
+/** @brief Check PWR flag is set or not.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
+ * was received from the WKUP pin or from the RTC alarm (Alarm A
+ * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
+ * An additional wakeup event is detected if the WKUP pin is enabled
+ * (by setting the EWUP bit) when the WKUP pin level is already high.
+ * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
+ * resumed from StandBy mode.
+ * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
+ * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
+ * For this reason, this bit is equal to 0 after Standby or reset
+ * until the PVDE bit is set.
+ * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
+ * when the device wakes up from Standby mode or by a system reset
+ * or power reset.
+ * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
+ * scaling output selection is ready.
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the PWR's pending flags.
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg PWR_FLAG_WU: Wake Up flag
+ * @arg PWR_FLAG_SB: StandBy flag
+ */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2)
+
+#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
+/**
+ * @brief Enable the PVD Exti Line.
+ * @param __EXTILINE__: specifies the PVD Exti sources to be enabled.
+ * This parameter can be:
+ * @arg PWR_EXTI_LINE_PVD
+ * @retval None.
+ */
+#define __HAL_PVD_EXTI_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__))
+
+/**
+ * @brief Disable the PVD EXTI Line.
+ * @param __EXTILINE__: specifies the PVD EXTI sources to be disabled.
+ * This parameter can be:
+ * @arg PWR_EXTI_LINE_PVD
+ * @retval None.
+ */
+#define __HAL_PVD_EXTI_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__))
+
+/**
+ * @brief checks whether the specified PVD Exti interrupt flag is set or not.
+ * @param __EXTILINE__: specifies the PVD Exti sources to be cleared.
+ * This parameter can be:
+ * @arg PWR_EXTI_LINE_PVD
+ * @retval EXTI PVD Line Status.
+ */
+#define __HAL_PVD_EXTI_GET_FLAG(__EXTILINE__) (EXTI->PR & (__EXTILINE__))
+
+/**
+ * @brief Clear the PVD Exti flag.
+ * @param __EXTILINE__: specifies the PVD Exti sources to be cleared.
+ * This parameter can be:
+ * @arg PWR_EXTI_LINE_PVD
+ * @retval None.
+ */
+#define __HAL_PVD_EXTI_CLEAR_FLAG(__EXTILINE__) (EXTI->PR = (__EXTILINE__))
+
+
+/* Include PWR HAL Extension module */
+#include "stm32f4xx_hal_pwr_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions *******************************/
+void HAL_PWR_DeInit(void);
+void HAL_PWR_EnableBkUpAccess(void);
+void HAL_PWR_DisableBkUpAccess(void);
+
+/* Peripheral Control functions ************************************************/
+void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD);
+void HAL_PWR_EnablePVD(void);
+void HAL_PWR_DisablePVD(void);
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
+
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
+void HAL_PWR_EnterSTANDBYMode(void);
+
+void HAL_PWR_PVD_IRQHandler(void);
+void HAL_PWR_PVDCallback(void);
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_PWR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_pwr_ex.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,161 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_pwr_ex.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of PWR HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_PWR_EX_H
+#define __STM32F4xx_HAL_PWR_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PWREx
+ * @{
+ */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* ------------- PWR registers bit address in the alias region ---------------*/
+/* --- CR Register ---*/
+
+/* Alias word address of ODEN bit */
+#define ODEN_BitNumber 0x10
+#define CR_ODEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODEN_BitNumber * 4))
+
+/* Alias word address of ODSWEN bit */
+#define ODSWEN_BitNumber 0x11
+#define CR_ODSWEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODSWEN_BitNumber * 4))
+
+
+/** @defgroup PWREx_Over_Under_Drive_Flag
+ * @{
+ */
+#define PWR_FLAG_ODRDY PWR_CSR_ODRDY
+#define PWR_FLAG_ODSWRDY PWR_CSR_ODSWRDY
+#define PWR_FLAG_UDRDY PWR_CSR_UDSWRDY
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Macros to enable or disable the Over drive mode.
+ * @note These macros can be used only for STM32F42xx/STM3243xx devices.
+ */
+#define __HAL_PWR_OVERDRIVE_ENABLE() (*(__IO uint32_t *) CR_ODEN_BB = ENABLE)
+#define __HAL_PWR_OVERDRIVE_DISABLE() (*(__IO uint32_t *) CR_ODEN_BB = DISABLE)
+
+/** @brief Macros to enable or disable the Over drive switching.
+ * @note These macros can be used only for STM32F42xx/STM3243xx devices.
+ */
+#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = ENABLE)
+#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = DISABLE)
+
+/** @brief Macros to enable or disable the Under drive mode.
+ * @note This mode is enabled only with STOP low power mode.
+ * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
+ * mode is only available when the main regulator or the low power regulator
+ * is in low voltage mode.
+ * @note If the Under-drive mode was enabled, it is automatically disabled after
+ * exiting Stop mode.
+ * When the voltage regulator operates in Under-drive mode, an additional
+ * startup delay is induced when waking up from Stop mode.
+ */
+#define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR |= (uint32_t)PWR_CR_UDEN)
+#define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR &= (uint32_t)(~PWR_CR_UDEN))
+
+/** @brief Check PWR flag is set or not.
+ * @note These macros can be used only for STM32F42xx/STM3243xx devices.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode
+ * is ready
+ * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode
+ * switching is ready
+ * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode
+ * is enabled in Stop mode
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the Under-Drive Ready flag.
+ * @note These macros can be used only for STM32F42xx/STM3243xx devices.
+ */
+#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR |= PWR_FLAG_UDRDY)
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/* Exported functions --------------------------------------------------------*/
+void HAL_PWREx_EnableFlashPowerDown(void);
+void HAL_PWREx_DisableFlashPowerDown(void);
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+HAL_StatusTypeDef HAL_PWREx_ActivateOverDrive(void);
+HAL_StatusTypeDef HAL_PWREx_DeactivateOverDrive(void);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_PWR_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_rcc.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,1169 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_rcc.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of RCC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_RCC_H
+#define __STM32F4xx_HAL_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief RCC PLL configuration structure definition
+ */
+typedef struct
+{
+ uint32_t PLLState; /*!< The new state of the PLL.
+ This parameter can be a value of @ref RCC_PLL_Config */
+
+ uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
+ This parameter must be a value of @ref RCC_PLL_Clock_Source */
+
+ uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
+
+ uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
+ This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
+
+ uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
+ This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
+
+ uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
+
+}RCC_PLLInitTypeDef;
+
+/**
+ * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
+ */
+typedef struct
+{
+ uint32_t OscillatorType; /*!< The oscillators to be configured.
+ This parameter can be a value of @ref RCC_Oscillator_Type */
+
+ uint32_t HSEState; /*!< The new state of the HSE.
+ This parameter can be a value of @ref RCC_HSE_Config */
+
+ uint32_t LSEState; /*!< The new state of the LSE.
+ This parameter can be a value of @ref RCC_LSE_Config */
+
+ uint32_t HSIState; /*!< The new state of the HSI.
+ This parameter can be a value of @ref RCC_HSI_Config */
+
+ uint32_t HSICalibrationValue; /*!< The calibration trimming value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
+
+ uint32_t LSIState; /*!< The new state of the LSI.
+ This parameter can be a value of @ref RCC_LSI_Config */
+
+ RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
+
+}RCC_OscInitTypeDef;
+
+/**
+ * @brief RCC System, AHB and APB busses clock configuration structure definition
+ */
+typedef struct
+{
+ uint32_t ClockType; /*!< The clock to be configured.
+ This parameter can be a value of @ref RCC_System_Clock_Type */
+
+ uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
+ This parameter can be a value of @ref RCC_System_Clock_Source */
+
+ uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+ This parameter can be a value of @ref RCC_AHB_Clock_Source */
+
+ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
+
+ uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
+
+}RCC_ClkInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup RCC_BitAddress_AliasRegion
+ * @brief RCC registers bit address in the alias region
+ * @{
+ */
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
+/* --- CR Register ---*/
+/* Alias word address of HSION bit */
+#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
+#define HSION_BitNumber 0x00
+#define CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (HSION_BitNumber * 4))
+/* Alias word address of CSSON bit */
+#define CSSON_BitNumber 0x13
+#define CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (CSSON_BitNumber * 4))
+/* Alias word address of PLLON bit */
+#define PLLON_BitNumber 0x18
+#define CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLON_BitNumber * 4))
+/* Alias word address of PLLI2SON bit */
+#define PLLI2SON_BitNumber 0x1A
+#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
+
+/* --- CFGR Register ---*/
+/* Alias word address of I2SSRC bit */
+#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
+#define I2SSRC_BitNumber 0x17
+#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
+
+/* --- BDCR Register ---*/
+/* Alias word address of RTCEN bit */
+#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70)
+#define RTCEN_BitNumber 0x0F
+#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
+/* Alias word address of BDRST bit */
+#define BDRST_BitNumber 0x10
+#define BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
+
+/* --- CSR Register ---*/
+/* Alias word address of LSION bit */
+#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
+#define LSION_BitNumber 0x00
+#define CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (LSION_BitNumber * 4))
+
+/* CR register byte 3 (Bits[23:16]) base address */
+#define CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
+
+/* CIR register byte 2 (Bits[15:8]) base address */
+#define CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
+
+/* CIR register byte 3 (Bits[23:16]) base address */
+#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
+
+/* BDCR register base address */
+#define BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
+
+
+#define DBP_TIMEOUT_VALUE ((uint32_t)100)
+#define LSE_TIMEOUT_VALUE ((uint32_t)500)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Oscillator_Type
+ * @{
+ */
+#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
+#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
+#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
+#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
+#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
+
+#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSE_Config
+ * @{
+ */
+#define RCC_HSE_OFF ((uint8_t)0x00)
+#define RCC_HSE_ON ((uint8_t)0x01)
+#define RCC_HSE_BYPASS ((uint8_t)0x05)
+
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+ ((HSE) == RCC_HSE_BYPASS))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSE_Config
+ * @{
+ */
+#define RCC_LSE_OFF ((uint8_t)0x00)
+#define RCC_LSE_ON ((uint8_t)0x01)
+#define RCC_LSE_BYPASS ((uint8_t)0x05)
+
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+ ((LSE) == RCC_LSE_BYPASS))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSI_Config
+ * @{
+ */
+#define RCC_HSI_OFF ((uint8_t)0x00)
+#define RCC_HSI_ON ((uint8_t)0x01)
+
+#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSI_Config
+ * @{
+ */
+#define RCC_LSI_OFF ((uint8_t)0x00)
+#define RCC_LSI_ON ((uint8_t)0x01)
+
+#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Config
+ * @{
+ */
+#define RCC_PLL_NONE ((uint8_t)0x00)
+#define RCC_PLL_OFF ((uint8_t)0x01)
+#define RCC_PLL_ON ((uint8_t)0x02)
+
+#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLLP_Clock_Divider
+ * @{
+ */
+#define RCC_PLLP_DIV2 ((uint32_t)0x00000002)
+#define RCC_PLLP_DIV4 ((uint32_t)0x00000004)
+#define RCC_PLLP_DIV6 ((uint32_t)0x00000006)
+#define RCC_PLLP_DIV8 ((uint32_t)0x00000008)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Clock_Source
+ * @{
+ */
+#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
+#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
+
+#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
+ ((SOURCE) == RCC_PLLSOURCE_HSE))
+#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
+#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
+#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
+#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
+
+#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
+#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Type
+ * @{
+ */
+#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
+#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
+#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
+#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
+
+#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Source
+ * @{
+ */
+#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
+#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
+#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
+
+#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Clock_Source
+ * @{
+ */
+#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
+#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
+#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
+#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
+#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
+#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
+#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
+#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
+#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
+
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
+ ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
+ ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
+ ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
+ ((HCLK) == RCC_SYSCLK_DIV512))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_APB2_Clock_Source
+ * @{
+ */
+#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
+#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
+#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
+#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
+#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
+
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
+ ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
+ ((PCLK) == RCC_HCLK_DIV16))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_RTC_Clock_Source
+ * @{
+ */
+#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)
+#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200)
+#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300)
+#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300)
+#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300)
+#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300)
+#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300)
+#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300)
+#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300)
+#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300)
+#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300)
+#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300)
+#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300)
+#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300)
+#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300)
+#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300)
+#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300)
+#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300)
+#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300)
+#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300)
+#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300)
+#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_I2S_Clock_Source
+ * @{
+ */
+#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)
+#define RCC_I2SCLKSOURCE_EXT ((uint32_t)0x00000001)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCO_Index
+ * @{
+ */
+#define RCC_MCO1 ((uint32_t)0x00000000)
+#define RCC_MCO2 ((uint32_t)0x00000001)
+
+#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCO1_Clock_Source
+ * @{
+ */
+#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
+#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
+#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
+#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
+
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
+ ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCO2_Clock_Source
+ * @{
+ */
+#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
+#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
+#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
+#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
+
+#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
+ ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCOx_Clock_Prescaler
+ * @{
+ */
+#define RCC_MCODIV_1 ((uint32_t)0x00000000)
+#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
+#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
+#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
+#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
+
+#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
+ ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
+ ((DIV) == RCC_MCODIV_5))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Interrupt
+ * @{
+ */
+#define RCC_IT_LSIRDY ((uint8_t)0x01)
+#define RCC_IT_LSERDY ((uint8_t)0x02)
+#define RCC_IT_HSIRDY ((uint8_t)0x04)
+#define RCC_IT_HSERDY ((uint8_t)0x08)
+#define RCC_IT_PLLRDY ((uint8_t)0x10)
+#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
+#define RCC_IT_CSS ((uint8_t)0x80)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Flag
+ * Elements values convention: 0XXYYYYYb
+ * - YYYYY : Flag position in the register
+ * - 0XX : Register index
+ * - 01: CR register
+ * - 10: BDCR register
+ * - 11: CSR register
+ * @{
+ */
+/* Flags in the CR register */
+#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
+#define RCC_FLAG_HSERDY ((uint8_t)0x31)
+#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
+#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
+
+/* Flags in the BDCR register */
+#define RCC_FLAG_LSERDY ((uint8_t)0x41)
+
+/* Flags in the CSR register */
+#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
+#define RCC_FLAG_BORRST ((uint8_t)0x79)
+#define RCC_FLAG_PINRST ((uint8_t)0x7A)
+#define RCC_FLAG_PORRST ((uint8_t)0x7B)
+#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
+#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
+#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
+#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
+
+#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Enable or disable the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#define __GPIOA_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOAEN))
+#define __GPIOB_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOBEN))
+#define __GPIOC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOCEN))
+#define __GPIOD_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIODEN))
+#define __GPIOE_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOEEN))
+#define __GPIOH_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOHEN))
+#define __CRC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_CRCEN))
+#define __BKPSRAM_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_BKPSRAMEN))
+#define __CCMDATARAMEN_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_CCMDATARAMEN))
+#define __DMA1_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA1EN))
+#define __DMA2_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA2EN))
+
+#define __GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
+#define __GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
+#define __GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
+#define __GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#define __GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#define __GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
+#define __CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+#define __BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
+#define __CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
+#define __DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
+#define __DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
+
+/** @brief Enable or disable the AHB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#define __USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
+ __SYSCFG_CLK_ENABLE();\
+ }while(0)
+
+
+#define __USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
+ __SYSCFG_CLK_DISABLE();\
+ }while(0)
+
+#define __RNG_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_RNGEN))
+#define __RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
+/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
+#define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
+#define __TIM4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN))
+#define __TIM5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM5EN))
+#define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
+#define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
+#define __SPI3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI3EN))
+#define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
+#define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
+#define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
+#define __I2C3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C3EN))
+#define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN))
+
+#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
+#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
+#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
+#define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
+#define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
+#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
+#define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+#define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
+
+/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#define __TIM1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM1EN))
+#define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN))
+#define __USART6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART6EN))
+#define __ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN))
+#define __SDIO_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SDIOEN))
+#define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
+#define __SPI4_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI4EN))
+#define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN))
+#define __TIM9_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM9EN))
+#define __TIM10_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM10EN))
+#define __TIM11_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM11EN))
+
+#define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
+#define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
+#define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
+#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
+#define __SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
+#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
+#define __SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
+#define __TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
+#define __TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+#define __TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
+
+/** @brief Force or release AHB1 peripheral reset.
+ */
+#define __AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
+#define __GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
+#define __GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
+#define __GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
+#define __GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#define __GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
+#define __GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
+#define __CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+#define __DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
+#define __DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
+
+#define __AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
+#define __GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
+#define __GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
+#define __GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
+#define __GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#define __GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
+#define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
+#define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
+#define __GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
+#define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
+#define __CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+#define __DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
+#define __DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
+
+/** @brief Force or release AHB2 peripheral reset.
+ */
+#define __AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
+#define __OTGFS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+
+#define __AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
+#define __OTGFS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+
+#define __RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
+#define __RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
+
+/** @brief Force or release APB1 peripheral reset.
+ */
+#define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
+#define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
+#define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
+#define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
+#define __SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
+#define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
+#define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
+#define __I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+#define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
+
+#define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
+#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
+#define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
+#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
+#define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
+#define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
+#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
+#define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+#define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
+
+/** @brief Force or release APB2 peripheral reset.
+ */
+#define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
+#define __TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
+#define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
+#define __USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
+#define __ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
+#define __SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
+#define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
+#define __SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+#define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
+#define __TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
+#define __TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+#define __TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
+
+#define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
+#define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
+#define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
+#define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
+#define __ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
+#define __SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
+#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
+#define __SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
+#define __TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
+#define __TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+#define __TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
+
+/** @brief Force or release AHB3 peripheral reset.
+ */
+#define __AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
+#define __AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
+
+/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+#define __GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
+#define __GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
+#define __GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
+#define __GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
+#define __GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
+#define __CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+#define __BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
+#define __DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
+#define __DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
+
+#define __GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
+#define __GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
+#define __GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
+#define __GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
+#define __GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
+#define __GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
+#define __CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+#define __BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
+#define __DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
+#define __DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
+
+/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+#define __OTGFS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+
+#define __OTGFS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+
+#define __RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
+
+/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+#define __TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
+#define __TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
+#define __WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
+#define __SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
+#define __SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
+#define __USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
+#define __I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
+#define __I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
+#define __I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
+#define __PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
+
+#define __TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
+#define __WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
+#define __SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
+#define __SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
+#define __USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
+#define __I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
+#define __I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
+#define __I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
+#define __PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
+
+/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+#define __TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
+#define __USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
+#define __USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
+#define __ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
+#define __SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
+#define __SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
+#define __SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
+#define __SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
+#define __TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
+#define __TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
+#define __TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
+
+#define __TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
+#define __USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
+#define __USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
+#define __ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
+#define __SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
+#define __SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
+#define __SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
+#define __SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
+#define __TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
+#define __TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
+#define __TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
+
+/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
+ * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
+ * It is used (enabled by hardware) as system clock source after startup
+ * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
+ * of the HSE used directly or indirectly as system clock (if the Clock
+ * Security System CSS is enabled).
+ * @note HSI can not be stopped if it is used as system clock source. In this case,
+ * you have to select another source of the system clock then stop the HSI.
+ * @note After enabling the HSI, the application software should wait on HSIRDY
+ * flag to be set indicating that HSI clock is stable and can be used as
+ * system clock source.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+ * clock cycles.
+ */
+#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) CR_HSION_BB = ENABLE)
+#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) CR_HSION_BB = DISABLE)
+
+/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
+ * @note The calibration is used to compensate for the variations in voltage
+ * and temperature that influence the frequency of the internal HSI RC.
+ * @param __HSICalibrationValue__: specifies the calibration trimming value.
+ * This parameter must be a number between 0 and 0x1F.
+ */
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
+ RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
+
+/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
+ * @note After enabling the LSI, the application software should wait on
+ * LSIRDY flag to be set indicating that LSI clock is stable and can
+ * be used to clock the IWDG and/or the RTC.
+ * @note LSI can not be disabled if the IWDG is running.
+ * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+ * clock cycles.
+ */
+#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) CSR_LSION_BB = ENABLE)
+#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) CSR_LSION_BB = DISABLE)
+
+/**
+ * @brief Macro to configure the External High Speed oscillator (HSE).
+ * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
+ * software should wait on HSERDY flag to be set indicating that HSE clock
+ * is stable and can be used to clock the PLL and/or system clock.
+ * @note HSE state can not be changed if it is used directly or through the
+ * PLL as system clock. In this case, you have to select another source
+ * of the system clock then change the HSE state (ex. disable it).
+ * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
+ * @note This function reset the CSSON bit, so if the clock security system(CSS)
+ * was previously enabled you have to enable it again after calling this
+ * function.
+ * @param __STATE__: specifies the new state of the HSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
+ * 6 HSE oscillator clock cycles.
+ * @arg RCC_HSE_ON: turn ON the HSE oscillator.
+ * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
+ */
+#define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *) CR_BYTE2_ADDRESS = (__STATE__))
+
+/**
+ * @brief Macro to configure the External Low Speed oscillator (LSE).
+ * @note As the LSE is in the Backup domain and write access is denied to
+ * this domain after reset, you have to enable write access using
+ * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+ * (to be done once after reset).
+ * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
+ * software should wait on LSERDY flag to be set indicating that LSE clock
+ * is stable and can be used to clock the RTC.
+ * @param __STATE__: specifies the new state of the LSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
+ * 6 LSE oscillator clock cycles.
+ * @arg RCC_LSE_ON: turn ON the LSE oscillator.
+ * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
+ */
+#define __HAL_RCC_LSE_CONFIG(__STATE__) (*(__IO uint8_t *) BDCR_BYTE0_ADDRESS = (__STATE__))
+
+/** @brief Macros to enable or disable the the RTC clock.
+ * @note These macros must be used only after the RTC clock source was selected.
+ */
+#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) BDCR_RTCEN_BB = ENABLE)
+#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) BDCR_RTCEN_BB = DISABLE)
+
+/** @brief Macros to configure the RTC clock (RTCCLK).
+ * @note As the RTC clock configuration bits are in the Backup domain and write
+ * access is denied to this domain after reset, you have to enable write
+ * access using the Power Backup Access macro before to configure
+ * the RTC clock source (to be done once after reset).
+ * @note Once the RTC clock is configured it can't be changed unless the
+ * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
+ * a Power On Reset (POR).
+ * @param __RTCCLKSource__: specifies the RTC clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
+ * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
+ * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
+ * as RTC clock, where x:[2,31]
+ * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
+ * work in STOP and STANDBY modes, and can be used as wakeup source.
+ * However, when the HSE clock is used as RTC clock source, the RTC
+ * cannot be used in STOP and STANDBY modes.
+ * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
+ * RTC clock source).
+ */
+#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
+
+#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
+ RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \
+ } while (0)
+
+/** @brief Macros to force or release the Backup domain reset.
+ * @note This function resets the RTC peripheral (including the backup registers)
+ * and the RTC clock source selection in RCC_CSR register.
+ * @note The BKPSRAM is not affected by this reset.
+ */
+#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) BDCR_BDRST_BB = ENABLE)
+#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) BDCR_BDRST_BB = DISABLE)
+
+/** @brief Macros to enable or disable the main PLL.
+ * @note After enabling the main PLL, the application software should wait on
+ * PLLRDY flag to be set indicating that PLL clock is stable and can
+ * be used as system clock source.
+ * @note The main PLL can not be disabled if it is used as system clock source
+ * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) CR_PLLON_BB = ENABLE)
+#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) CR_PLLON_BB = DISABLE)
+
+/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
+ * @note This function must be used only when the main PLL is disabled.
+ * @param __RCC_PLLSource__: specifies the PLL entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+ * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
+ * @param __PLLM__: specifies the division factor for PLL VCO input clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+ * @note You have to set the PLLM parameter correctly to ensure that the VCO input
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+ * of 2 MHz to limit PLL jitter.
+ * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
+ * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+ * @note You have to set the PLLN parameter correctly to ensure that the VCO
+ * output frequency is between 192 and 432 MHz.
+ * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
+ * This parameter must be a number in the range {2, 4, 6, or 8}.
+ * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on
+ * the System clock frequency.
+ * @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ * @note If the USB OTG FS is used in your application, you have to set the
+ * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
+ * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
+ * correctly.
+ */
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)\
+ (RCC->PLLCFGR = (0x20000000 | (__PLLM__) | ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
+ ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | (__RCC_PLLSource__) | \
+ ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
+
+/** @brief Macro to configure the I2S clock source (I2SCLK).
+ * @note This function must be called before enabling the I2S APB clock.
+ * @param __SOURCE__: specifies the I2S clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
+ * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
+ * used as I2S clock source.
+ */
+#define __HAL_RCC_I2SCLK(__SOURCE__) (*(__IO uint32_t *) CFGR_I2SSRC_BB = (__SOURCE__))
+
+/** @brief Macros to enable or disable the PLLI2S.
+ * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) CR_PLLI2SON_BB = ENABLE)
+#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) CR_PLLI2SON_BB = DISABLE)
+
+/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
+ * @note This macro must be used only when the PLLI2S is disabled.
+ * @note PLLI2S clock source is common with the main PLL (configured in
+ * HAL_RCC_ClockConfig() API).
+ * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
+ * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+ * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
+ * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
+ * @param __PLLI2SR__: specifies the division factor for I2S clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+ * on the I2S clock frequency.
+ */
+#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) | ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
+
+/** @brief Macro to get the clock source used as system clock.
+ * @retval The clock source used as system clock. The returned value can be one
+ * of the following:
+ * - RCC_CFGR_SWS_HSI: HSI used as system clock.
+ * - RCC_CFGR_SWS_HSE: HSE used as system clock.
+ * - RCC_CFGR_SWS_PLL: PLL used as system clock.
+ */
+#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
+
+/** @brief Macro to get the oscillator used as PLL clock source.
+ * @retval The oscillator used as PLL clock source. The returned value can be one
+ * of the following:
+ * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
+ * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
+ */
+#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
+
+/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
+ * the selected interrupts).
+ * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
+ */
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
+
+/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
+ * the selected interrupts).
+ * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
+ */
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
+
+/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
+ * bits to clear the selected interrupt pending bits.
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ */
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE2_ADDRESS = (__INTERRUPT__))
+
+/** @brief Check the RCC's interrupt has occurred or not.
+ * @param __INTERRUPT__: specifies the RCC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
+ * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
+ */
+#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
+
+/** @brief Check RCC flag is set or not.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
+ * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
+ * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
+ * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
+ * @arg RCC_FLAG_PINRST: Pin reset.
+ * @arg RCC_FLAG_PORRST: POR/PDR reset.
+ * @arg RCC_FLAG_SFTRST: Software reset.
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
+ * @arg RCC_FLAG_LPWRRST: Low Power reset.
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define RCC_FLAG_MASK ((uint8_t)0x1F)
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
+
+#define __RCC_PLLSRC() ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC))
+
+
+/* Include RCC HAL Extension module */
+#include "stm32f4xx_hal_rcc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions ******************************/
+void HAL_RCC_DeInit(void);
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
+
+/* Peripheral Control functions ************************************************/
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
+void HAL_RCC_EnableCSS(void);
+void HAL_RCC_DisableCSS(void);
+uint32_t HAL_RCC_GetSysClockFreq(void);
+uint32_t HAL_RCC_GetHCLKFreq(void);
+uint32_t HAL_RCC_GetPCLK1Freq(void);
+uint32_t HAL_RCC_GetPCLK2Freq(void);
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
+
+/* CSS NMI IRQ handler */
+void HAL_RCC_NMI_IRQHandler(void);
+
+/* User Callbacks in non blocking mode (IT mode) */
+void HAL_RCC_CCSCallback(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_RCC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_rcc_ex.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,874 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_rcc_ex.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of RCC HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_RCC_EX_H
+#define __STM32F4xx_HAL_RCC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RCCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+/**
+ * @brief PLLI2S Clock structure definition
+ */
+typedef struct
+{
+ uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+ This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+ uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+ uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+}RCC_PLLI2SInitTypeDef;
+
+/**
+ * @brief PLLSAI Clock structure definition
+ */
+typedef struct
+{
+ uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+ This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+ This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
+
+ uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
+
+ uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
+ This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
+
+}RCC_PLLSAIInitTypeDef;
+/**
+ * @brief RCC extended clocks structure definition
+ */
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+ RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
+
+ uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 32
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+
+ uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 32
+ This parameter will be used only when PLLSAI is selected as Clock Source SAI */
+
+ uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
+ This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
+ This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE)
+/**
+ * @brief PLLI2S Clock structure definition
+ */
+typedef struct
+{
+ uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+ This parameter must be a number between Min_Data = 192 and Max_Data = 432
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+ uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+}RCC_PLLI2SInitTypeDef;
+
+
+/**
+ * @brief RCC extended clocks structure definition
+ */
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Constants
+ * @{
+ */
+
+/** @defgroup RCCEx_Periph_Clock_Selection
+ * @{
+ */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004)
+#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
+#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000002F))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE)
+#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000002)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000003))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_BitAddress_AliasRegion
+ * @brief RCC registers bit address in the alias region
+ * @{
+ */
+/* --- CR Register ---*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+/* Alias word address of PLLSAION bit */
+#define PLLSAION_BitNumber 0x1C
+#define CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))
+
+/* --- DCKCFGR Register ---*/
+/* Alias word address of TIMPRE bit */
+#define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
+#define TIMPRE_BitNumber 0x18
+#define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_PLLI2S_Clock_Source
+ * @{
+ */
+#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_PLLSAI_Clock_Source
+ * @{
+ */
+#define IS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
+#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
+#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_PLLSAI_DIVQ
+ * @{
+ */
+#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_PLLI2S_DIVQ
+ * @{
+ */
+#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_PLLSAI_DIVR
+ * @{
+ */
+#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
+#define RCC_PLLSAIDIVR_4 ((uint32_t)0x00010000)
+#define RCC_PLLSAIDIVR_8 ((uint32_t)0x00020000)
+#define RCC_PLLSAIDIVR_16 ((uint32_t)0x00030000)
+#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
+ ((VALUE) == RCC_PLLSAIDIVR_4) ||\
+ ((VALUE) == RCC_PLLSAIDIVR_8) ||\
+ ((VALUE) == RCC_PLLSAIDIVR_16))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SAI_BlockA_Clock_Source
+ * @{
+ */
+#define RCC_SAIACLKSOURCE_PLLSAI ((uint32_t)0x00000000)
+#define RCC_SAIACLKSOURCE_PLLI2S ((uint32_t)0x00100000)
+#define RCC_SAIACLKSOURCE_EXT ((uint32_t)0x00200000)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SAI_BlockB_Clock_Source
+ * @{
+ */
+#define RCC_SAIBCLKSOURCE_PLLSAI ((uint32_t)0x00000000)
+#define RCC_SAIBCLKSOURCE_PLLI2S ((uint32_t)0x00400000)
+#define RCC_SAIBCLKSOURCE_EXT ((uint32_t)0x00800000)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM_PRescaler_Selection
+ * @{
+ */
+#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
+#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
+/**
+ * @}
+ */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Enables or disables the AHB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+#define __GPIOI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOIEN))
+#define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN))
+#define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN))
+#define __ETHMAC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN))
+#define __ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN))
+#define __ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN))
+#define __ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN))
+#define __USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSEN))
+#define __USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSULPIEN))
+
+#define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
+#define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
+#define __GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
+#define __ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
+#define __ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
+#define __ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
+#define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
+#define __USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
+#define __USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
+#endif /* !(STM32F401xC && STM32F401xE) */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __GPIOJ_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOJEN))
+#define __GPIOK_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOKEN))
+#define __DMA2D_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA2DEN))
+
+#define __GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
+#define __GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
+#define __DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
+
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+/**
+ * @brief Enable ETHERNET clock.
+ */
+#define __ETH_CLK_ENABLE() do { \
+ __ETHMAC_CLK_ENABLE(); \
+ __ETHMACTX_CLK_ENABLE(); \
+ __ETHMACRX_CLK_ENABLE(); \
+ } while(0)
+
+/**
+ * @brief Disable ETHERNET clock.
+ */
+#define __ETH_CLK_DISABLE() do { \
+ __ETHMACTX_CLK_DISABLE(); \
+ __ETHMACRX_CLK_DISABLE(); \
+ __ETHMAC_CLK_DISABLE(); \
+ } while(0)
+#endif /* !(STM32F401xC && STM32F401xE) */
+
+/** @brief Enable or disable the AHB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+#define __DCMI_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_DCMIEN))
+#define __DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
+#endif /* !(STM32F401xC && STM32F401xE) */
+
+#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx)
+#define __CRYP_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_CRYPEN))
+#define __HASH_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_HASHEN))
+
+#define __CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
+#define __HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
+
+#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
+
+/** @brief Enables or disables the AHB3 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#define __FSMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FSMCEN))
+#define __FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __FMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN))
+#define __FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
+#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
+
+
+/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+#define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
+#define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
+#define __TIM12_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN))
+#define __TIM13_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN))
+#define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
+#define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
+#define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
+#define __UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN))
+#define __UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN))
+#define __CAN1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN1EN))
+#define __CAN2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN2EN))
+#define __DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
+
+#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
+#define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
+#define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
+#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
+#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
+#define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
+#define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
+#define __CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
+#define __CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
+#define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+#endif /* !(STM32F401xC && STM32F401xE) */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __UART7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART7EN))
+#define __UART8_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART8EN))
+
+#define __UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
+#define __UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
+#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
+
+/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+#define __TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN))
+#define __ADC2_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC2EN))
+#define __ADC3_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC3EN))
+
+#define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
+#define __ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
+#define __ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
+#endif /* !(STM32F401xC && STM32F401xE) */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __SPI5_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI5EN))
+#define __SPI6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI6EN))
+#define __SAI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SAI1EN))
+#define __LTDC_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_LTDCEN))
+
+#define __SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
+#define __SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
+#define __SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
+#define __LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @brief Force or release AHB1 peripheral reset.
+ */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+#define __GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
+#define __GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
+#define __GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
+#define __ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
+#define __OTGHS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
+
+#define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
+#define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
+#define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
+#define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
+#define __OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
+#endif /* !STM32F401xC && STM32F401xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
+#define __GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
+#define __DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
+
+#define __GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
+#define __GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
+#define __DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @brief Force or release AHB2 peripheral reset.
+ */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+#define __DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
+#define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
+#endif /* !STM32F401xC && STM32F401xE */
+
+#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx)
+#define __CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
+#define __HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
+
+#define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
+#define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
+
+#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
+
+/** @brief Force or release AHB3 peripheral reset
+ */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#define __FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
+#define __FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
+#define __FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @brief Force or release APB1 peripheral reset.
+ */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+#define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
+#define __TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
+#define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
+#define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
+#define __UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
+#define __UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
+#define __CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
+#define __CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
+#define __DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+
+#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
+#define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
+#define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
+#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
+#define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
+#define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
+#define __CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
+#define __CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
+#define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+#endif /* !STM32F401xC && STM32F401xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
+#define __UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
+
+#define __UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
+#define __UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @brief Force or release APB2 peripheral reset.
+ */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+#define __TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
+#define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
+#endif /* !STM32F401xC && STM32F401xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
+#define __SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
+#define __SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
+#define __LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
+
+#define __SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
+#define __SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
+#define __SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
+#define __LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+
+/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+#define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
+#define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
+#define __GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
+#define __SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
+#define __ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
+#define __ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
+#define __ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
+#define __ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
+#define __OTGHS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
+#define __OTGHSULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
+
+#define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
+#define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
+#define __GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
+#define __SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
+#define __ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
+#define __ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
+#define __ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
+#define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
+#define __OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
+#define __OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
+#endif /* !STM32F401xC && STM32F401xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
+#define __GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
+#define __SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN))
+#define __DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
+
+#define __GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
+#define __GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
+#define __DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+#define __DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
+#endif /* !STM32F401xC && STM32F401xE */
+
+#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx)
+#define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
+#define __HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
+
+#define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
+#define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
+
+#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
+
+/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+#define __FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
+#define __FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx)
+#define __FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
+#define __FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+#define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
+#define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
+#define __TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
+#define __TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
+#define __TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
+#define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
+#define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
+#define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
+#define __CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
+#define __CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
+#define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
+
+#define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
+#define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
+#define __TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
+#define __TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
+#define __TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
+#define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
+#define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
+#define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
+#define __CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
+#define __CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
+#define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
+#endif /* !STM32F401xC && STM32F401xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
+#define __UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
+
+#define __UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
+#define __UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ */
+#if !defined(STM32F401xC) && !defined(STM32F401xE)
+#define __TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
+#define __ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
+#define __ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
+
+#define __TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
+#define __ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
+#define __ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
+#endif /* !STM32F401xC && STM32F401xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define __SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
+#define __SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
+#define __SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
+#define __LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
+
+#define __SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
+#define __SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
+#define __SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
+#define __LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+
+/** @brief Macro to configure the Timers clocks prescalers
+ * @note This feature is only available with STM32F429x/439x Devices.
+ * @param __PRESC__ : specifies the Timers clocks prescalers selection
+ * This parameter can be one of the following values:
+ * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
+ * equal to HPRE if PPREx is corresponding to division by 1 or 2,
+ * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
+ * division by 4 or more.
+ * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
+ * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
+ * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
+ * to division by 8 or more.
+ */
+#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) DCKCFGR_TIMPRE_BB = (__PRESC__))
+
+/** @brief Macros to Enable or Disable the PLLISAI.
+ * @note The PLLSAI is only available with STM32F429x/439x Devices.
+ * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) CR_PLLSAION_BB = ENABLE)
+#define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) CR_PLLSAION_BB = DISABLE)
+
+/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
+ * @note The PLLSAI is only available with STM32F429x/439x Devices.
+ * @note This function must be used only when the PLLSAI is disabled.
+ * @note PLLSAI clock source is common with the main PLL (configured in
+ * RCC_PLLConfig function )
+ * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
+ * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+ * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
+ * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
+ * @param __PLLSAIQ__: specifies the division factor for SAI1 clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ * @param __PLLSAIR__: specifies the division factor for LTDC clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ */
+#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << 6) | ((__PLLSAIQ__) << 24) | ((__PLLSAIR__) << 28))
+
+/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
+ * @note This macro must be used only when the PLLI2S is disabled.
+ * @note PLLI2S clock source is common with the main PLL (configured in
+ * HAL_RCC_ClockConfig() API)
+ * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
+ * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+ * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
+ * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
+ * @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+ * @note the PLLI2SQ parameter is only available with STM32F429x/439x Devices
+ * and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
+ * @param __PLLI2SR__: specifies the division factor for I2S clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+ * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+ * on the I2S clock frequency.
+ */
+#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) | ((__PLLI2SQ__) << 24) | ((__PLLI2SR__) << 28))
+
+/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
+ * @note The SAI peripheral is only available with STM32F429x/439x Devices.
+ * @note This function must be called before enabling the PLLI2S.
+ * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
+ * This parameter must be a number between 1 and 32.
+ * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
+ */
+#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
+
+/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
+ * @note The SAI peripheral is only available with STM32F429x/439x Devices.
+ * @note This function must be called before enabling the PLLSAI.
+ * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
+ * This parameter must be a number between Min_Data = 1 and Max_Data = 32.
+ * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
+ */
+#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
+
+/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
+ *
+ * @note The LTDC peripheral is only available with STM32F429x/439x Devices.
+ * @note This function must be called before enabling the PLLSAI.
+ * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 16.
+ * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
+ */
+#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
+
+/** @brief Macro to configure SAI1BlockA clock source selection.
+ * @note The SAI peripheral is only available with STM32F429x/439x Devices.
+ * @note This function must be called before enabling PLLSAI, PLLI2S and
+ * the SAI clock.
+ * @param __SOURCE__: specifies the SAI Block A clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
+ * as SAI1 Block A clock.
+ * @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
+ * as SAI1 Block A clock.
+ * @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
+ * used as SAI1 Block A clock.
+ */
+#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
+
+/** @brief Macro to configure SAI1BlockB clock source selection.
+ * @note The SAI peripheral is only available with STM32F429x/439x Devices.
+ * @note This function must be called before enabling PLLSAI, PLLI2S and
+ * the SAI clock.
+ * @param __SOURCE__: specifies the SAI Block B clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
+ * as SAI1 Block B clock.
+ * @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
+ * as SAI1 Block B clock.
+ * @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
+ * used as SAI1 Block B clock.
+ */
+#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
+
+/** @brief Enable PLLSAI_RDY interrupt.
+ */
+#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
+
+/** @brief Disable PLLSAI_RDY interrupt.
+ */
+#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
+
+/** @brief Clear the PLLSAI RDY interrupt pending bits.
+ */
+#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
+
+/** @brief Check the PLLSAI RDY interrupt has occurred or not.
+ * @retval The new state (TRUE or FALSE).
+ */
+#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
+
+/** @brief Check PLLSAI RDY flag is set or not.
+ * @retval The new state (TRUE or FALSE).
+ */
+#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+/* Exported functions --------------------------------------------------------*/
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_RCC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_rng.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,218 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_rng.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of RNG HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_RNG_H
+#define __STM32F4xx_HAL_RNG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RNG
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief RNG HAL State Structure definition
+ */
+typedef enum
+{
+ HAL_RNG_STATE_RESET = 0x00, /*!< RNG not yet initialized or disabled */
+ HAL_RNG_STATE_READY = 0x01, /*!< RNG initialized and ready for use */
+ HAL_RNG_STATE_BUSY = 0x02, /*!< RNG internal process is ongoing */
+ HAL_RNG_STATE_TIMEOUT = 0x03, /*!< RNG timeout state */
+ HAL_RNG_STATE_ERROR = 0x04 /*!< RNG error state */
+
+}HAL_RNG_StateTypeDef;
+
+/**
+ * @brief RNG Handle Structure definition
+ */
+typedef struct
+{
+ RNG_TypeDef *Instance; /*!< Register base address */
+
+ HAL_LockTypeDef Lock; /*!< RNG locking object */
+
+ __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */
+
+}RNG_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RNG_Exported_Constants
+ * @{
+ */
+
+/** @defgroup RNG_Interrupt_definition
+ * @{
+ */
+#define RNG_IT_CEI ((uint32_t)0x20) /*!< Clock error interrupt */
+#define RNG_IT_SEI ((uint32_t)0x40) /*!< Seed error interrupt */
+
+#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
+ ((IT) == RNG_IT_SEI))
+/**
+ * @}
+ */
+
+
+/** @defgroup RNG_Flag_definition
+ * @{
+ */
+#define RNG_FLAG_DRDY ((uint32_t)0x0001) /*!< Data ready */
+#define RNG_FLAG_CECS ((uint32_t)0x0002) /*!< Clock error current status */
+#define RNG_FLAG_SECS ((uint32_t)0x0004) /*!< Seed error current status */
+
+#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
+ ((FLAG) == RNG_FLAG_CECS) || \
+ ((FLAG) == RNG_FLAG_SECS))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset RNG handle state
+ * @param __HANDLE__: RNG Handle
+ * @retval None
+ */
+#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
+
+/**
+ * @brief Enables the RNG peripheral.
+ * @param __HANDLE__: RNG Handle
+ * @retval None
+ */
+#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
+
+/**
+ * @brief Disables the RNG peripheral.
+ * @param __HANDLE__: RNG Handle
+ * @retval None
+ */
+#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
+
+/**
+ * @brief Gets the selected RNG's flag status.
+ * @param __HANDLE__: RNG Handle
+ * @param __FLAG__: RNG flag
+ * @retval The new state of RNG_FLAG (SET or RESET).
+ */
+#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clears the RNG's pending flags.
+ * @param __HANDLE__: RNG Handle
+ * @param __FLAG__: RNG flag
+ * @retval None
+ */
+#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) &= ~(__FLAG__))
+
+/**
+ * @brief Enables the RNG interrupts.
+ * @param __HANDLE__: RNG Handle
+ * @retval None
+ */
+#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
+
+/**
+ * @brief Disables the RNG interrupts.
+ * @param __HANDLE__: RNG Handle
+ * @retval None
+ */
+#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
+
+/**
+ * @brief Checks whether the specified RNG interrupt has occurred or not.
+ * @param __HANDLE__: RNG Handle
+ * @param __INTERRUPT__: specifies the RNG interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg RNG_FLAG_DRDY: Data ready interrupt
+ * @arg RNG_FLAG_CECS: Clock error interrupt
+ * @arg RNG_FLAG_SECS: Seed error interrupt
+ * @retval The new state of RNG_FLAG (SET or RESET).
+ */
+#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
+HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);
+void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
+void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
+
+/* Peripheral Control functions ************************************************/
+uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng);
+uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng);
+void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
+void HAL_RNG_ReadyCallback(RNG_HandleTypeDef* hrng);
+void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
+
+/* Peripheral State functions **************************************************/
+HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_RNG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_rtc.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,745 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_rtc.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of RTC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_RTC_H
+#define __STM32F4xx_HAL_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RTC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_RTC_STATE_RESET = 0x00, /*!< RTC not yet initialized or disabled */
+ HAL_RTC_STATE_READY = 0x01, /*!< RTC initialized and ready for use */
+ HAL_RTC_STATE_BUSY = 0x02, /*!< RTC process is ongoing */
+ HAL_RTC_STATE_TIMEOUT = 0x03, /*!< RTC timeout state */
+ HAL_RTC_STATE_ERROR = 0x04 /*!< RTC error state */
+
+}HAL_RTCStateTypeDef;
+
+/**
+ * @brief RTC Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t HourFormat; /*!< Specifies the RTC Hour Format.
+ This parameter can be a value of @ref RTC_Hour_Formats */
+
+ uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
+
+ uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
+
+ uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
+ This parameter can be a value of @ref RTC_Output_selection_Definitions */
+
+ uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
+ This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
+
+ uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
+ This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
+}RTC_InitTypeDef;
+
+/**
+ * @brief RTC Time structure definition
+ */
+typedef struct
+{
+ uint8_t Hours; /*!< Specifies the RTC Time Hour.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
+
+ uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+
+ uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+
+ uint32_t SubSeconds; /*!< Specifies the RTC Time SubSeconds.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+
+ uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
+ This parameter can be a value of @ref RTC_AM_PM_Definitions */
+
+ uint32_t DayLightSaving; /*!< Specifies DayLight Save Operation.
+ This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
+
+ uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
+ in CR register to store the operation.
+ This parameter can be a value of @ref RTC_StoreOperation_Definitions */
+}RTC_TimeTypeDef;
+
+/**
+ * @brief RTC Date structure definition
+ */
+typedef struct
+{
+ uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
+ This parameter can be a value of @ref RTC_WeekDay_Definitions */
+
+ uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
+ This parameter can be a value of @ref RTC_Month_Date_Definitions */
+
+ uint8_t Date; /*!< Specifies the RTC Date.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
+
+ uint8_t Year; /*!< Specifies the RTC Date Year.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
+
+}RTC_DateTypeDef;
+
+/**
+ * @brief RTC Alarm structure definition
+ */
+typedef struct
+{
+ RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */
+
+ uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
+ This parameter can be a value of @ref RTC_AlarmMask_Definitions */
+
+ uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks.
+ This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
+
+ uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
+ This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+
+ uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
+ If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
+ If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
+
+ uint32_t Alarm; /*!< Specifies the alarm .
+ This parameter can be a value of @ref RTC_Alarms_Definitions */
+}RTC_AlarmTypeDef;
+
+/**
+ * @brief Time Handle Structure definition
+ */
+typedef struct
+{
+ RTC_TypeDef *Instance; /*!< Register base address */
+
+ RTC_InitTypeDef Init; /*!< RTC required parameters */
+
+ HAL_LockTypeDef Lock; /*!< RTC locking object */
+
+ __IO HAL_RTCStateTypeDef State; /*!< Time communication state */
+
+}RTC_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTC_Exported_Constants
+ * @{
+ */
+
+/* Masks Definition */
+#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
+#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
+#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
+#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)
+#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
+ RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
+ RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
+ RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \
+ RTC_FLAG_RECALPF | RTC_FLAG_SHPF))
+
+#define RTC_TIMEOUT_VALUE 1000
+
+/** @defgroup RTC_Hour_Formats
+ * @{
+ */
+#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000)
+#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040)
+
+#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
+ ((FORMAT) == RTC_HOURFORMAT_24))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Output_selection_Definitions
+ * @{
+ */
+#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000)
+#define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000)
+#define RTC_OUTPUT_ALARMB ((uint32_t)0x00400000)
+#define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000)
+
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
+ ((OUTPUT) == RTC_OUTPUT_ALARMA) || \
+ ((OUTPUT) == RTC_OUTPUT_ALARMB) || \
+ ((OUTPUT) == RTC_OUTPUT_WAKEUP))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Output_Polarity_Definitions
+ * @{
+ */
+#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000)
+#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000)
+
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
+ ((POL) == RTC_OUTPUT_POLARITY_LOW))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Output_Type_ALARM_OUT
+ * @{
+ */
+#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000)
+#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)0x00040000)
+
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
+ ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Asynchronous_Predivider
+ * @{
+ */
+#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F)
+/**
+ * @}
+ */
+
+
+/** @defgroup RTC_Synchronous_Predivider
+ * @{
+ */
+#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Time_Definitions
+ * @{
+ */
+#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
+#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23)
+#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59)
+#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_AM_PM_Definitions
+ * @{
+ */
+#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
+#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)
+
+#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_DayLightSaving_Definitions
+ * @{
+ */
+#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000)
+#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000)
+#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000)
+
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
+ ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
+ ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_StoreOperation_Definitions
+ * @{
+ */
+#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000)
+#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000)
+
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
+ ((OPERATION) == RTC_STOREOPERATION_SET))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Input_parameter_format_definitions
+ * @{
+ */
+#define FORMAT_BIN ((uint32_t)0x000000000)
+#define FORMAT_BCD ((uint32_t)0x000000001)
+
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == FORMAT_BIN) || ((FORMAT) == FORMAT_BCD))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Year_Date_Definitions
+ * @{
+ */
+#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Month_Date_Definitions
+ * @{
+ */
+
+/* Coded in BCD format */
+#define RTC_MONTH_JANUARY ((uint8_t)0x01)
+#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
+#define RTC_MONTH_MARCH ((uint8_t)0x03)
+#define RTC_MONTH_APRIL ((uint8_t)0x04)
+#define RTC_MONTH_MAY ((uint8_t)0x05)
+#define RTC_MONTH_JUNE ((uint8_t)0x06)
+#define RTC_MONTH_JULY ((uint8_t)0x07)
+#define RTC_MONTH_AUGUST ((uint8_t)0x08)
+#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
+#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
+#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
+#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
+
+#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
+#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_WeekDay_Definitions
+ * @{
+ */
+#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
+#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
+#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
+#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
+#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
+#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
+#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
+
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Alarm_Definitions
+ * @{
+ */
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+/**
+ * @}
+ */
+
+
+/** @defgroup RTC_AlarmDateWeekDay_Definitions
+ * @{
+ */
+#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000)
+#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000)
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
+ ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
+/**
+ * @}
+ */
+
+
+/** @defgroup RTC_AlarmMask_Definitions
+ * @{
+ */
+#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000)
+#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
+#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
+#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
+#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
+#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080)
+
+#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Alarms_Definitions
+ * @{
+ */
+#define RTC_ALARM_A RTC_CR_ALRAE
+#define RTC_ALARM_B RTC_CR_ALRBE
+
+#define IS_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Alarm_Sub_Seconds_Value
+ * @{
+ */
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF)
+/**
+ * @}
+ */
+
+ /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions
+ * @{
+ */
+#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked.
+ There is no comparison on sub seconds
+ for Alarm */
+#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm
+ comparison. Only SS[0] is compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm
+ comparison. Only SS[1:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm
+ comparison. Only SS[2:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm
+ comparison. Only SS[3:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm
+ comparison. Only SS[4:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm
+ comparison. Only SS[5:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm
+ comparison. Only SS[6:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm
+ comparison. Only SS[7:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm
+ comparison. Only SS[8:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm
+ comparison. Only SS[9:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm
+ comparison. Only SS[10:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm
+ comparison.Only SS[11:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm
+ comparison. Only SS[12:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm
+ comparison.Only SS[13:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match
+ to activate alarm. */
+
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_None))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Interrupts_Definitions
+ * @{
+ */
+#define RTC_IT_TS ((uint32_t)0x00008000)
+#define RTC_IT_WUT ((uint32_t)0x00004000)
+#define RTC_IT_ALRB ((uint32_t)0x00002000)
+#define RTC_IT_ALRA ((uint32_t)0x00001000)
+#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
+#define RTC_IT_TAMP1 ((uint32_t)0x00020000)
+#define RTC_IT_TAMP2 ((uint32_t)0x00040000)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Flags_Definitions
+ * @{
+ */
+#define RTC_FLAG_RECALPF ((uint32_t)0x00010000)
+#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000)
+#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)
+#define RTC_FLAG_TSOVF ((uint32_t)0x00001000)
+#define RTC_FLAG_TSF ((uint32_t)0x00000800)
+#define RTC_FLAG_WUTF ((uint32_t)0x00000400)
+#define RTC_FLAG_ALRBF ((uint32_t)0x00000200)
+#define RTC_FLAG_ALRAF ((uint32_t)0x00000100)
+#define RTC_FLAG_INITF ((uint32_t)0x00000040)
+#define RTC_FLAG_RSF ((uint32_t)0x00000020)
+#define RTC_FLAG_INITS ((uint32_t)0x00000010)
+#define RTC_FLAG_SHPF ((uint32_t)0x00000008)
+#define RTC_FLAG_WUTWF ((uint32_t)0x00000004)
+#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002)
+#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset RTC handle state
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
+
+/**
+ * @brief Disable the write protection for RTC registers.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->Instance->WPR = 0xCA; \
+ (__HANDLE__)->Instance->WPR = 0x53; \
+ } while(0)
+
+/**
+ * @brief Enable the write protection for RTC registers.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->Instance->WPR = 0xFF; \
+ } while(0)
+
+/**
+ * @brief Enable the RTC ALARMA peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
+
+/**
+ * @brief Disable the RTC ALARMA peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
+
+/**
+ * @brief Enable the RTC ALARMB peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
+
+/**
+ * @brief Disable the RTC ALARMB peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
+
+/**
+ * @brief Enable the RTC Alarm interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @arg RTC_IT_ALRB: Alarm B interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC Alarm interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @arg RTC_IT_ALRB: Alarm B interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified RTC Alarm interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @arg RTC_IT_ALRB: Alarm B interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __FLAG__) ((((((__HANDLE__)->Instance->ISR)& ((__FLAG__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET)
+
+/**
+ * @brief Get the selected RTC Alarm's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_ALRAF
+ * @arg RTC_FLAG_ALRBF
+ * @arg RTC_FLAG_ALRAWF
+ * @arg RTC_FLAG_ALRBWF
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Clear the RTC Alarm's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_ALRAF
+ * @arg RTC_FLAG_ALRBF
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+
+#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00020000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
+#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wakeup event */
+
+/**
+ * @brief Enable the RTC Exti line.
+ * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_EXTI_LINE_ALARM_EVENT
+ * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
+ * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
+ * @retval None
+ */
+#define __HAL_RTC_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__))
+
+/**
+ * @brief Disable the RTC Exti line.
+ * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_EXTI_LINE_ALARM_EVENT
+ * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
+ * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
+ * @retval None
+ */
+#define __HAL_RTC_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__))
+
+/**
+ * @brief Clear the RTC Exti flags.
+ * @param __FLAG__: specifies the RTC Exti sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_EXTI_LINE_ALARM_EVENT
+ * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
+ * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
+ * @retval None
+ */
+#define __HAL_RTC_CLEAR_FLAG(__FLAG__) (EXTI->PR = (__FLAG__))
+
+/* Include RTC HAL Extension module */
+#include "stm32f4xx_hal_rtc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
+
+/* RTC Time and Date functions ************************************************/
+HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+
+/* RTC Alarm functions ********************************************************/
+HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
+HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
+void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
+
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
+
+/* Peripheral State functions *************************************************/
+HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
+
+HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
+uint8_t RTC_ByteToBcd2(uint8_t Value);
+uint8_t RTC_Bcd2ToByte(uint8_t Value);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_RTC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_rtc_ex.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,691 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_rtc_ex.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of RTC HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_RTC_EX_H
+#define __STM32F4xx_HAL_RTC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RTCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief RTC Tamper structure definition
+ */
+typedef struct
+{
+ uint32_t Tamper; /*!< Specifies the Tamper Pin.
+ This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */
+
+ uint32_t PinSelection; /*!< Specifies the Tamper Pin.
+ This parameter can be a value of @ref RTCEx_Tamper_Pins_Selection */
+
+ uint32_t Trigger; /*!< Specifies the Tamper Trigger.
+ This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */
+
+ uint32_t Filter; /*!< Specifies the RTC Filter Tamper.
+ This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */
+
+ uint32_t SamplingFrequency; /*!< Specifies the sampling frequency.
+ This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */
+
+ uint32_t PrechargeDuration; /*!< Specifies the Precharge Duration .
+ This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */
+
+ uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp .
+ This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */
+
+ uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection.
+ This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
+}RTC_TamperTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Constants
+ * @{
+ */
+
+/** @defgroup RTCEx_Backup_Registers_Definitions
+ * @{
+ */
+#define RTC_BKP_DR0 ((uint32_t)0x00000000)
+#define RTC_BKP_DR1 ((uint32_t)0x00000001)
+#define RTC_BKP_DR2 ((uint32_t)0x00000002)
+#define RTC_BKP_DR3 ((uint32_t)0x00000003)
+#define RTC_BKP_DR4 ((uint32_t)0x00000004)
+#define RTC_BKP_DR5 ((uint32_t)0x00000005)
+#define RTC_BKP_DR6 ((uint32_t)0x00000006)
+#define RTC_BKP_DR7 ((uint32_t)0x00000007)
+#define RTC_BKP_DR8 ((uint32_t)0x00000008)
+#define RTC_BKP_DR9 ((uint32_t)0x00000009)
+#define RTC_BKP_DR10 ((uint32_t)0x0000000A)
+#define RTC_BKP_DR11 ((uint32_t)0x0000000B)
+#define RTC_BKP_DR12 ((uint32_t)0x0000000C)
+#define RTC_BKP_DR13 ((uint32_t)0x0000000D)
+#define RTC_BKP_DR14 ((uint32_t)0x0000000E)
+#define RTC_BKP_DR15 ((uint32_t)0x0000000F)
+#define RTC_BKP_DR16 ((uint32_t)0x00000010)
+#define RTC_BKP_DR17 ((uint32_t)0x00000011)
+#define RTC_BKP_DR18 ((uint32_t)0x00000012)
+#define RTC_BKP_DR19 ((uint32_t)0x00000013)
+
+#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \
+ ((BKP) == RTC_BKP_DR1) || \
+ ((BKP) == RTC_BKP_DR2) || \
+ ((BKP) == RTC_BKP_DR3) || \
+ ((BKP) == RTC_BKP_DR4) || \
+ ((BKP) == RTC_BKP_DR5) || \
+ ((BKP) == RTC_BKP_DR6) || \
+ ((BKP) == RTC_BKP_DR7) || \
+ ((BKP) == RTC_BKP_DR8) || \
+ ((BKP) == RTC_BKP_DR9) || \
+ ((BKP) == RTC_BKP_DR10) || \
+ ((BKP) == RTC_BKP_DR11) || \
+ ((BKP) == RTC_BKP_DR12) || \
+ ((BKP) == RTC_BKP_DR13) || \
+ ((BKP) == RTC_BKP_DR14) || \
+ ((BKP) == RTC_BKP_DR15) || \
+ ((BKP) == RTC_BKP_DR16) || \
+ ((BKP) == RTC_BKP_DR17) || \
+ ((BKP) == RTC_BKP_DR18) || \
+ ((BKP) == RTC_BKP_DR19))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Time_Stamp_Edges_definitions
+ * @{
+ */
+#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000)
+#define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008)
+
+#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
+ ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Pins_Definitions
+ * @{
+ */
+#define RTC_TAMPER_1 RTC_TAFCR_TAMP1E
+#define RTC_TAMPER_2 RTC_TAFCR_TAMP2E
+
+#define IS_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFF6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Pins_Selection
+ * @{
+ */
+#define RTC_TAMPERPIN_PC13 ((uint32_t)0x00000000)
+#define RTC_TAMPERPIN_PI8 ((uint32_t)0x00010000)
+
+#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TAMPERPIN_PC13) || \
+ ((PIN) == RTC_TAMPERPIN_PI8))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_TimeStamp_Pin_Selection
+ * @{
+ */
+#define RTC_TIMESTAMPPIN_PC13 ((uint32_t)0x00000000)
+#define RTC_TIMESTAMPPIN_PI8 ((uint32_t)0x00020000)
+
+#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_PC13) || \
+ ((PIN) == RTC_TIMESTAMPPIN_PI8))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Trigger_Definitions
+ * @{
+ */
+#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000)
+#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002)
+#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
+#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE
+
+#define IS_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Filter_Definitions
+ * @{
+ */
+#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
+
+#define RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800) /*!< Tamper is activated after 2
+ consecutive samples at the active level */
+#define RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000) /*!< Tamper is activated after 4
+ consecutive samples at the active level */
+#define RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800) /*!< Tamper is activated after 8
+ consecutive samples at the active leve. */
+
+#define IS_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
+ ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
+ ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
+ ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions
+ * @{
+ */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 32768 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 16384 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 8192 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 4096 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 2048 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 1024 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 512 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 256 */
+
+#define IS_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions
+ * @{
+ */
+#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before
+ sampling during 1 RTCCLK cycle */
+#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before
+ sampling during 2 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before
+ sampling during 4 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before
+ sampling during 8 RTCCLK cycles */
+
+#define IS_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
+ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
+ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
+ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions
+ * @{
+ */
+#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */
+#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event is not saved */
+
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
+ ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Pull_UP_Definitions
+ * @{
+ */
+#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event saved */
+#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS) /*!< TimeStamp on Tamper Detection event is not saved */
+
+#define IS_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
+ ((STATE) == RTC_TAMPER_PULLUP_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Wakeup_Timer_Definitions
+ * @{
+ */
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000)
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001)
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002)
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003)
+#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004)
+#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006)
+
+#define IS_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
+
+#define IS_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Digital_Calibration_Definitions
+ * @{
+ */
+#define RTC_CALIBSIGN_POSITIVE ((uint32_t)0x00000000)
+#define RTC_CALIBSIGN_NEGATIVE ((uint32_t)0x00000080)
+
+#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CALIBSIGN_POSITIVE) || \
+ ((SIGN) == RTC_CALIBSIGN_NEGATIVE))
+
+#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Smooth_calib_period_Definitions
+ * @{
+ */
+#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000) /*!< If RTCCLK = 32768 Hz, Smooth calibation
+ period is 32s, else 2exp20 RTCCLK seconds */
+#define RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000) /*!< If RTCCLK = 32768 Hz, Smooth calibation
+ period is 16s, else 2exp19 RTCCLK seconds */
+#define RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000) /*!< If RTCCLK = 32768 Hz, Smooth calibation
+ period is 8s, else 2exp18 RTCCLK seconds */
+
+#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
+ ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
+ ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions
+ * @{
+ */
+#define RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added
+ during a X -second window = Y - CALM[8:0]
+ with Y = 512, 256, 128 when X = 32, 16, 8 */
+#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited
+ during a 32-second window = CALM[8:0] */
+
+#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
+ ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Smooth_calib_Minus_pulses_Definitions
+ * @{
+ */
+#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions
+ * @{
+ */
+#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000)
+#define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000)
+
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
+ ((SEL) == RTC_SHIFTADD1S_SET))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Substract_Fraction_Of_Second_Value
+ * @{
+ */
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
+/**
+ * @}
+ */
+
+ /** @defgroup RTCEx_Calib_Output_selection_Definitions
+ * @{
+ */
+#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000)
+#define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000)
+
+#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
+ ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/**
+ * @brief Enable the RTC WakeUp Timer peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
+
+/**
+ * @brief Enable the RTC TimeStamp peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
+
+/**
+ * @brief Disable the RTC WakeUp Timer peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
+
+/**
+ * @brief Disable the RTC TimeStamp peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
+
+/**
+ * @brief Enable the Coarse calibration process.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_COARSE_CALIB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_DCE))
+
+/**
+ * @brief Disable the Coarse calibration process.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_COARSE_CALIB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_DCE))
+
+/**
+ * @brief Enable the RTC calibration output.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
+
+/**
+ * @brief Disable the calibration output.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
+
+/**
+ * @brief Enable the clock reference detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
+
+/**
+ * @brief Disable the clock reference detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
+
+/**
+ * @brief Enable the RTC TimeStamp interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Enable the RTC WakeUpTimer interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC TimeStamp interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC WakeUpTimer interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified RTC Tamper interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_TAMP1
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
+
+/**
+ * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
+
+/**
+ * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
+
+/**
+ * @brief Get the selected RTC TimeStamp's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC TimeStamp Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_TSF
+ * @arg RTC_FLAG_TSOVF
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Get the selected RTC WakeUpTimer's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC WakeUpTimer Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_WUTF
+ * @arg RTC_FLAG_WUTWF
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Get the selected RTC Tamper's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_TAMP1F
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Get the selected RTC shift operation's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC shift operation Flag is pending or not.
+ * This parameter can be:
+ * @arg RTC_FLAG_SHPF
+ * @retval None
+ */
+#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Clear the RTC Time Stamp's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_TSF
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+/**
+ * @brief Clear the RTC Tamper's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_TAMP1F
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+/**
+ * @brief Clear the RTC Wake Up timer's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg RTC_FLAG_WUTF
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+/* Exported functions --------------------------------------------------------*/
+
+/* RTC TimeStamp and Tamper functions *****************************************/
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
+
+HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
+void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
+
+void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+
+/* RTC Wake-up functions ******************************************************/
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
+uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
+uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+
+/* Extension Control functions ************************************************/
+void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
+uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
+
+HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue);
+HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
+HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
+
+/* Extension RTC features functions *******************************************/
+void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_RTC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_sai.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,767 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_sai.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of SAI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SAI_H
+#define __STM32F4xx_HAL_SAI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SAI
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief SAI Init Structure definition
+ */
+typedef struct
+{
+ uint32_t Protocol; /*!< Specifies the SAI Block protocol.
+ This parameter can be a value of @ref SAI_Block_Protocol */
+
+ uint32_t AudioMode; /*!< Specifies the SAI Block audio Mode.
+ This parameter can be a value of @ref SAI_Block_Mode */
+
+ uint32_t DataSize; /*!< Specifies the SAI Block data size.
+ This parameter can be a value of @ref SAI_Block_Data_Size */
+
+ uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */
+
+ uint32_t ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity.
+ This parameter can be a value of @ref SAI_Block_Clock_Strobing */
+
+ uint32_t Synchro; /*!< Specifies SAI Block synchronization
+ This parameter can be a value of @ref SAI_Block_Synchronization */
+
+ uint32_t OutputDrive; /*!< Specifies when SAI Block outputs are driven.
+ This parameter can be a value of @ref SAI_Block_Output_Drive
+ @note this value has to be set before enabling the audio block
+ but after the audio block configuration. */
+
+ uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not.
+ This parameter can be a value of @ref SAI_Block_NoDivider
+ @note: If bit NODIV in the SAI_xCR1 register is cleared, the frame length
+ should be aligned to a number equal to a power of 2, from 8 to 256.
+ If bit NODIV in the SAI_xCR1 register is set, the frame length can
+ take any of the values without constraint since the input clock of
+ the audio block should be equal to the bit clock.
+ There is no MCLK_x clock which can be output. */
+
+ uint32_t FIFOThreshold; /*!< Specifies SAI Block FIFO threshold.
+ This parameter can be a value of @ref SAI_Block_Fifo_Threshold */
+
+ uint32_t ClockSource; /*!< Specifies the SAI Block x Clock source.
+ This parameter can be a value of @ref SAI_Clock_Source
+ @note: If ClockSource is equal to SAI_CLKSource_Ext, the PLLI2S
+ and PLLSAI divisions factors will be ignored. */
+
+ uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling.
+ This parameter can be a value of @ref SAI_Audio_Frequency */
+
+}SAI_InitTypeDef;
+
+/**
+ * @brief SAI Block Frame Init structure definition
+ */
+
+typedef struct
+{
+
+ uint32_t FrameLength; /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.
+ This parameter must be a number between Min_Data = 8 and Max_Data = 256.
+ @note: If master clock MCLK_x pin is declared as an output, the frame length
+ should be aligned to a number equal to power of 2 in order to keep
+ in an audio frame, an integer number of MCLK pulses by bit Clock. */
+
+ uint32_t ActiveFrameLength; /*!< Specifies the Frame synchronization active level length.
+ This Parameter specifies the length in number of bit clock (SCK + 1)
+ of the active level of FS signal in audio frame.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
+
+ uint32_t FSDefinition; /*!< Specifies the Frame synchronization definition.
+ This parameter can be a value of @ref SAI_Block_FS_Definition */
+
+ uint32_t FSPolarity; /*!< Specifies the Frame synchronization Polarity.
+ This parameter can be a value of @ref SAI_Block_FS_Polarity */
+
+ uint32_t FSOffset; /*!< Specifies the Frame synchronization Offset.
+ This parameter can be a value of @ref SAI_Block_FS_Offset */
+
+}SAI_FrameInitTypeDef;
+
+/**
+ * @brief SAI Block Slot Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t FirstBitOffset; /*!< Specifies the position of first data transfer bit in the slot.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 24 */
+
+ uint32_t SlotSize; /*!< Specifies the Slot Size.
+ This parameter can be a value of @ref SAI_Block_Slot_Size */
+
+ uint32_t SlotNumber; /*!< Specifies the number of slot in the audio frame.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
+
+ uint32_t SlotActive; /*!< Specifies the slots in audio frame that will be activated.
+ This parameter can be a value of @ref SAI_Block_Slot_Active */
+}SAI_SlotInitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_SAI_STATE_RESET = 0x00, /*!< SAI not yet initialized or disabled */
+ HAL_SAI_STATE_READY = 0x01, /*!< SAI initialized and ready for use */
+ HAL_SAI_STATE_BUSY = 0x02, /*!< SAI internal process is ongoing */
+ HAL_SAI_STATE_BUSY_TX = 0x12, /*!< Data transmission process is ongoing */
+ HAL_SAI_STATE_BUSY_RX = 0x22, /*!< Data reception process is ongoing */
+ HAL_SAI_STATE_TIMEOUT = 0x03, /*!< SAI timeout state */
+ HAL_SAI_STATE_ERROR = 0x04 /*!< SAI error state */
+
+}HAL_SAI_StateTypeDef;
+
+/**
+ * @brief SAI handle Structure definition
+ */
+typedef struct
+{
+ SAI_Block_TypeDef *Instance; /*!< SAI Blockx registers base address */
+
+ SAI_InitTypeDef Init; /*!< SAI communication parameters */
+
+ SAI_FrameInitTypeDef FrameInit; /*!< SAI Frame configuration parameters */
+
+ SAI_SlotInitTypeDef SlotInit; /*!< SAI Slot configuration parameters */
+
+ uint16_t *pTxBuffPtr; /*!< Pointer to SAI Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< SAI Tx transfer size */
+
+ uint16_t TxXferCount; /*!< SAI Tx transfer counter */
+
+ uint16_t *pRxBuffPtr; /*!< Pointer to SAI Rx transfer buffer */
+
+ uint16_t RxXferSize; /*!< SAI Rx transfer size */
+
+ uint16_t RxXferCount; /*!< SAI Rx transfer counter */
+
+ DMA_HandleTypeDef *hdmatx; /*!< SAI Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< SAI Rx DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< SAI locking object */
+
+ __IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */
+
+ __IO uint32_t ErrorCode; /*!< SAI Error code */
+}SAI_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SAI_Exported_Constants
+ * @{
+ */
+/** @defgroup SAI Error Code
+ * @{
+ */
+#define HAL_SAI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_SAI_ERROR_OVR ((uint32_t)0x00000001) /*!< Overrun Error */
+#define HAL_SAI_ERROR_UDR ((uint32_t)0x00000002) /*!< Underrun error */
+#define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Clock_Source
+ * @{
+ */
+#define SAI_CLKSOURCE_PLLSAI ((uint32_t)RCC_SAIACLKSOURCE_PLLSAI)
+#define SAI_CLKSOURCE_PLLI2S ((uint32_t)RCC_SAIACLKSOURCE_PLLI2S)
+#define SAI_CLKSOURCE_EXT ((uint32_t)RCC_SAIACLKSOURCE_EXT)
+
+#define IS_SAI_CLK_SOURCE(SOURCE) (((SOURCE) == SAI_CLKSOURCE_PLLSAI) ||\
+ ((SOURCE) == SAI_CLKSOURCE_PLLI2S) ||\
+ ((SOURCE) == SAI_CLKSOURCE_EXT))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Audio_Frequency
+ * @{
+ */
+#define SAI_AUDIO_FREQUENCY_192K ((uint32_t)192000)
+#define SAI_AUDIO_FREQUENCY_96K ((uint32_t)96000)
+#define SAI_AUDIO_FREQUENCY_48K ((uint32_t)48000)
+#define SAI_AUDIO_FREQUENCY_44K ((uint32_t)44100)
+#define SAI_AUDIO_FREQUENCY_32K ((uint32_t)32000)
+#define SAI_AUDIO_FREQUENCY_22K ((uint32_t)22050)
+#define SAI_AUDIO_FREQUENCY_16K ((uint32_t)16000)
+#define SAI_AUDIO_FREQUENCY_11K ((uint32_t)11025)
+#define SAI_AUDIO_FREQUENCY_8K ((uint32_t)8000)
+
+#define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_48K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_32K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_16K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
+ ((AUDIO) == SAI_AUDIO_FREQUENCY_8K))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Mode
+ * @{
+ */
+#define SAI_MODEMASTER_TX ((uint32_t)0x00000000)
+#define SAI_MODEMASTER_RX ((uint32_t)0x00000001)
+#define SAI_MODESLAVE_TX ((uint32_t)0x00000002)
+#define SAI_MODESLAVE_RX ((uint32_t)0x00000003)
+#define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_MODEMASTER_TX) || \
+ ((MODE) == SAI_MODEMASTER_RX) || \
+ ((MODE) == SAI_MODESLAVE_TX) || \
+ ((MODE) == SAI_MODESLAVE_RX))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Protocol
+ * @{
+ */
+
+#define SAI_FREE_PROTOCOL ((uint32_t)0x00000000)
+#define SAI_AC97_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_1)
+
+#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL) || \
+ ((PROTOCOL) == SAI_AC97_PROTOCOL))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Data_Size
+ * @{
+ */
+#define SAI_DATASIZE_8 ((uint32_t)0x00000040)
+#define SAI_DATASIZE_10 ((uint32_t)0x00000060)
+#define SAI_DATASIZE_16 ((uint32_t)0x00000080)
+#define SAI_DATASIZE_20 ((uint32_t)0x000000A0)
+#define SAI_DATASIZE_24 ((uint32_t)0x000000C0)
+#define SAI_DATASIZE_32 ((uint32_t)0x000000E0)
+
+#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8) || \
+ ((DATASIZE) == SAI_DATASIZE_10) || \
+ ((DATASIZE) == SAI_DATASIZE_16) || \
+ ((DATASIZE) == SAI_DATASIZE_20) || \
+ ((DATASIZE) == SAI_DATASIZE_24) || \
+ ((DATASIZE) == SAI_DATASIZE_32))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_MSB_LSB_transmission
+ * @{
+ */
+
+#define SAI_FIRSTBIT_MSB ((uint32_t)0x00000000)
+#define SAI_FIRSTBIT_LSB ((uint32_t)SAI_xCR1_LSBFIRST)
+
+#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \
+ ((BIT) == SAI_FIRSTBIT_LSB))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Clock_Strobing
+ * @{
+ */
+#define SAI_CLOCKSTROBING_FALLINGEDGE ((uint32_t)0x00000000)
+#define SAI_CLOCKSTROBING_RISINGEDGE ((uint32_t)SAI_xCR1_CKSTR)
+
+#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
+ ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Synchronization
+ * @{
+ */
+#define SAI_ASYNCHRONOUS ((uint32_t)0x00000000)
+#define SAI_SYNCHRONOUS ((uint32_t)SAI_xCR1_SYNCEN_0)
+
+#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \
+ ((SYNCHRO) == SAI_SYNCHRONOUS))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Output_Drive
+ * @{
+ */
+#define SAI_OUTPUTDRIVE_DISABLED ((uint32_t)0x00000000)
+#define SAI_OUTPUTDRIVE_ENABLED ((uint32_t)SAI_xCR1_OUTDRIV)
+
+#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLED) || \
+ ((DRIVE) == SAI_OUTPUTDRIVE_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_NoDivider
+ * @{
+ */
+#define SAI_MASTERDIVIDER_ENABLED ((uint32_t)0x00000000)
+#define SAI_MASTERDIVIDER_DISABLED ((uint32_t)SAI_xCR1_NODIV)
+
+#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLED) || \
+ ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLED))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Master_Divider
+ * @{
+ */
+#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15)
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Frame_Length
+ * @{
+ */
+#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Active_FrameLength
+ * @{
+ */
+#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_FS_Definition
+ * @{
+ */
+#define SAI_FS_STARTFRAME ((uint32_t)0x00000000)
+#define SAI_FS_CHANNEL_IDENTIFICATION ((uint32_t)SAI_xFRCR_FSDEF)
+
+#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
+ ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_FS_Polarity
+ * @{
+ */
+#define SAI_FS_ACTIVE_LOW ((uint32_t)0x00000000)
+#define SAI_FS_ACTIVE_HIGH ((uint32_t)SAI_xFRCR_FSPO)
+
+#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \
+ ((POLARITY) == SAI_FS_ACTIVE_HIGH))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_FS_Offset
+ * @{
+ */
+#define SAI_FS_FIRSTBIT ((uint32_t)0x00000000)
+#define SAI_FS_BEFOREFIRSTBIT ((uint32_t)SAI_xFRCR_FSOFF)
+
+#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \
+ ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Slot_FirstBit_Offset
+ * @{
+ */
+#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24)
+/**
+ * @}
+ */
+
+ /** @defgroup SAI_Block_Slot_Size
+ * @{
+ */
+#define SAI_SLOTSIZE_DATASIZE ((uint32_t)0x00000000)
+#define SAI_SLOTSIZE_16B ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
+#define SAI_SLOTSIZE_32B ((uint32_t)SAI_xSLOTR_SLOTSZ_1)
+
+#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
+ ((SIZE) == SAI_SLOTSIZE_16B) || \
+ ((SIZE) == SAI_SLOTSIZE_32B))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Slot_Number
+ * @{
+ */
+#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Slot_Active
+ * @{
+ */
+#define SAI_SLOT_NOTACTIVE ((uint32_t)0x00000000)
+#define SAI_SLOTACTIVE_0 ((uint32_t)0x00010000)
+#define SAI_SLOTACTIVE_1 ((uint32_t)0x00020000)
+#define SAI_SLOTACTIVE_2 ((uint32_t)0x00040000)
+#define SAI_SLOTACTIVE_3 ((uint32_t)0x00080000)
+#define SAI_SLOTACTIVE_4 ((uint32_t)0x00100000)
+#define SAI_SLOTACTIVE_5 ((uint32_t)0x00200000)
+#define SAI_SLOTACTIVE_6 ((uint32_t)0x00400000)
+#define SAI_SLOTACTIVE_7 ((uint32_t)0x00800000)
+#define SAI_SLOTACTIVE_8 ((uint32_t)0x01000000)
+#define SAI_SLOTACTIVE_9 ((uint32_t)0x02000000)
+#define SAI_SLOTACTIVE_10 ((uint32_t)0x04000000)
+#define SAI_SLOTACTIVE_11 ((uint32_t)0x08000000)
+#define SAI_SLOTACTIVE_12 ((uint32_t)0x10000000)
+#define SAI_SLOTACTIVE_13 ((uint32_t)0x20000000)
+#define SAI_SLOTACTIVE_14 ((uint32_t)0x40000000)
+#define SAI_SLOTACTIVE_15 ((uint32_t)0x80000000)
+#define SAI_SLOTACTIVE_ALL ((uint32_t)0xFFFF0000)
+
+#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) != 0)
+
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Mono_Stereo_Mode
+ * @{
+ */
+#define SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO)
+#define SAI_STREOMODE ((uint32_t)0x00000000)
+
+#define IS_SAI_BLOCK_MONO_STREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\
+ ((MODE) == SAI_STREOMODE))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_TRIState_Management
+ * @{
+ */
+#define SAI_OUTPUT_NOTRELEASED ((uint32_t)0x00000000)
+#define SAI_OUTPUT_RELEASED ((uint32_t)SAI_xCR2_TRIS)
+
+#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
+ ((STATE) == SAI_OUTPUT_RELEASED))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Fifo_Threshold
+ * @{
+ */
+#define SAI_FIFOTHRESHOLD_EMPTY ((uint32_t)0x00000000)
+#define SAI_FIFOTHRESHOLD_1QF ((uint32_t)0x00000001)
+#define SAI_FIFOTHRESHOLD_HF ((uint32_t)0x00000002)
+#define SAI_FIFOTHRESHOLD_3QF ((uint32_t)0x00000003)
+#define SAI_FIFOTHRESHOLD_FULL ((uint32_t)0x00000004)
+
+#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY) || \
+ ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF) || \
+ ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF) || \
+ ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF) || \
+ ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Companding_Mode
+ * @{
+ */
+#define SAI_NOCOMPANDING ((uint32_t)0x00000000)
+#define SAI_ULAW_1CPL_COMPANDING ((uint32_t)0x00008000)
+#define SAI_ALAW_1CPL_COMPANDING ((uint32_t)0x0000C000)
+#define SAI_ULAW_2CPL_COMPANDING ((uint32_t)0x0000A000)
+#define SAI_ALAW_2CPL_COMPANDING ((uint32_t)0x0000E000)
+
+#define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NOCOMPANDING) || \
+ ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
+ ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
+ ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
+ ((MODE) == SAI_ALAW_2CPL_COMPANDING))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Mute_Value
+ * @{
+ */
+#define SAI_ZERO_VALUE ((uint32_t)0x00000000)
+#define SAI_LAST_SENT_VALUE ((uint32_t)SAI_xCR2_MUTEVAL)
+
+#define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZERO_VALUE) || \
+ ((VALUE) == SAI_LAST_SENT_VALUE))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Mute_Frame_Counter
+ * @{
+ */
+#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63)
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Interrupts_Definition
+ * @{
+ */
+#define SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE)
+#define SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE)
+#define SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE)
+#define SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE)
+#define SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE)
+#define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE)
+#define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE)
+
+#define IS_SAI_BLOCK_CONFIG_IT(IT) (((IT) == SAI_IT_OVRUDR) || \
+ ((IT) == SAI_IT_MUTEDET) || \
+ ((IT) == SAI_IT_WCKCFG) || \
+ ((IT) == SAI_IT_FREQ) || \
+ ((IT) == SAI_IT_CNRDY) || \
+ ((IT) == SAI_IT_AFSDET) || \
+ ((IT) == SAI_IT_LFSDET))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Flags_Definition
+ * @{
+ */
+#define SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR)
+#define SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET)
+#define SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG)
+#define SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ)
+#define SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY)
+#define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET)
+#define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET)
+
+#define IS_SAI_BLOCK_GET_FLAG(FLAG) (((FLAG) == SAI_FLAG_OVRUDR) || \
+ ((FLAG) == SAI_FLAG_MUTEDET) || \
+ ((FLAG) == SAI_FLAG_WCKCFG) || \
+ ((FLAG) == SAI_FLAG_FREQ) || \
+ ((FLAG) == SAI_FLAG_CNRDY) || \
+ ((FLAG) == SAI_FLAG_AFSDET) || \
+ ((FLAG) == SAI_FLAG_LFSDET))
+
+#define IS_SAI_BLOCK_CLEAR_FLAG(FLAG) (((FLAG) == SAI_FLAG_OVRUDR) || \
+ ((FLAG) == SAI_FLAG_MUTEDET) || \
+ ((FLAG) == SAI_FLAG_WCKCFG) || \
+ ((FLAG) == SAI_FLAG_FREQ) || \
+ ((FLAG) == SAI_FLAG_CNRDY) || \
+ ((FLAG) == SAI_FLAG_AFSDET) || \
+ ((FLAG) == SAI_FLAG_LFSDET))
+/**
+ * @}
+ */
+
+/** @defgroup SAI_Block_Fifo_Status_Level
+ * @{
+ */
+#define SAI_FIFOStatus_Empty ((uint32_t)0x00000000)
+#define SAI_FIFOStatus_Less1QuarterFull ((uint32_t)0x00010000)
+#define SAI_FIFOStatus_1QuarterFull ((uint32_t)0x00020000)
+#define SAI_FIFOStatus_HalfFull ((uint32_t)0x00030000)
+#define SAI_FIFOStatus_3QuartersFull ((uint32_t)0x00040000)
+#define SAI_FIFOStatus_Full ((uint32_t)0x00050000)
+
+#define IS_SAI_BLOCK_FIFO_STATUS(STATUS) (((STATUS) == SAI_FIFOStatus_Less1QuarterFull ) || \
+ ((STATUS) == SAI_FIFOStatus_HalfFull) || \
+ ((STATUS) == SAI_FIFOStatus_1QuarterFull) || \
+ ((STATUS) == SAI_FIFOStatus_3QuartersFull) || \
+ ((STATUS) == SAI_FIFOStatus_Full) || \
+ ((STATUS) == SAI_FIFOStatus_Empty))
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @brief Reset SAI handle state
+ * @param __HANDLE__: specifies the SAI Handle.
+ * @retval None
+ */
+#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
+
+/** @brief Enable or disable the specified SAI interrupts.
+ * @param __HANDLE__: specifies the SAI Handle.
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
+ * @arg SAI_IT_MUTEDET: Mute detection interrupt enable
+ * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
+ * @arg SAI_IT_FREQ: FIFO request interrupt enable
+ * @arg SAI_IT_CNRDY: Codec not ready interrupt enable
+ * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
+ * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enabl
+ * @retval None
+ */
+
+#define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
+#define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
+
+/** @brief Check if the specified SAI interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the SAI Handle.
+ * This parameter can be SAI where x: 1, 2, or 3 to select the SAI peripheral.
+ * @param __INTERRUPT__: specifies the SAI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SAI_IT_TXE: Tx buffer empty interrupt enable.
+ * @arg SAI_IT_RXNE: Rx buffer not empty interrupt enable.
+ * @arg SAI_IT_ERR: Error interrupt enable.
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Check whether the specified SAI flag is set or not.
+ * @param __HANDLE__: specifies the SAI Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SAI_FLAG_OVRUDR: Overrun underrun flag.
+ * @arg SAI_FLAG_MUTEDET: Mute detection flag.
+ * @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.
+ * @arg SAI_FLAG_FREQ: FIFO request flag.
+ * @arg SAI_FLAG_CNRDY: Codec not ready flag.
+ * @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.
+ * @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag.
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the specified SAI pending flag.
+ * @param __HANDLE__: specifies the SAI Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg SAI_FLAG_OVRUDR: Clear Overrun underrun
+ * @arg SAI_FLAG_MUTEDET: Clear Mute detection
+ * @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration
+ * @arg SAI_FLAG_FREQ: Clear FIFO request
+ * @arg SAI_FLAG_CNRDY: Clear Codec not ready
+ * @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection
+ * @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection
+ *
+ * @retval None
+ */
+#define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR |= (__FLAG__))
+
+#define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)
+#define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_DeInit (SAI_HandleTypeDef *hsai);
+void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);
+void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);
+
+/* I/O operation functions *****************************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);
+
+/* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);
+void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);
+
+/* Peripheral State functions **************************************************/
+HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai);
+uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_SAI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_sd.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,665 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_sd.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of SD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SD_H
+#define __STM32F4xx_HAL_SD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_sdmmc.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SD
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+#define SD_InitTypeDef SDIO_InitTypeDef
+#define SD_TypeDef SDIO_TypeDef
+
+/**
+ * @brief SDIO Handle Structure definition
+ */
+typedef struct
+{
+ SD_TypeDef *Instance; /*!< SDIO register base address */
+
+ SD_InitTypeDef Init; /*!< SD required parameters */
+
+ HAL_LockTypeDef Lock; /*!< SD locking object */
+
+ uint32_t CardType; /*!< SD card type */
+
+ uint32_t RCA; /*!< SD relative card address */
+
+ uint32_t CSD[4]; /*!< SD card specific data table */
+
+ uint32_t CID[4]; /*!< SD card identification number table */
+
+ __IO uint32_t SdTransferCplt; /*!< SD transfer complete flag in non blocking mode */
+
+ __IO uint32_t SdTransferErr; /*!< SD transfer error flag in non blocking mode */
+
+ __IO uint32_t DmaTransferCplt; /*!< SD DMA transfer complete flag */
+
+ __IO uint32_t SdOperation; /*!< SD transfer operation (read/write) */
+
+ DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */
+
+}SD_HandleTypeDef;
+
+/**
+ * @brief Card Specific Data: CSD Register
+ */
+typedef struct
+{
+ __IO uint8_t CSDStruct; /*!< CSD structure */
+ __IO uint8_t SysSpecVersion; /*!< System specification version */
+ __IO uint8_t Reserved1; /*!< Reserved */
+ __IO uint8_t TAAC; /*!< Data read access time 1 */
+ __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
+ __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
+ __IO uint16_t CardComdClasses; /*!< Card command classes */
+ __IO uint8_t RdBlockLen; /*!< Max. read data block length */
+ __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
+ __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
+ __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
+ __IO uint8_t DSRImpl; /*!< DSR implemented */
+ __IO uint8_t Reserved2; /*!< Reserved */
+ __IO uint32_t DeviceSize; /*!< Device Size */
+ __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
+ __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
+ __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
+ __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
+ __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
+ __IO uint8_t EraseGrSize; /*!< Erase group size */
+ __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
+ __IO uint8_t WrProtectGrSize; /*!< Write protect group size */
+ __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
+ __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
+ __IO uint8_t WrSpeedFact; /*!< Write speed factor */
+ __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
+ __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
+ __IO uint8_t Reserved3; /*!< Reserved */
+ __IO uint8_t ContentProtectAppli; /*!< Content protection application */
+ __IO uint8_t FileFormatGrouop; /*!< File format group */
+ __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
+ __IO uint8_t PermWrProtect; /*!< Permanent write protection */
+ __IO uint8_t TempWrProtect; /*!< Temporary write protection */
+ __IO uint8_t FileFormat; /*!< File format */
+ __IO uint8_t ECC; /*!< ECC code */
+ __IO uint8_t CSD_CRC; /*!< CSD CRC */
+ __IO uint8_t Reserved4; /*!< Always 1 */
+
+}HAL_SD_CSDTypedef;
+
+/**
+ * @brief Card Identification Data: CID Register
+ */
+typedef struct
+{
+ __IO uint8_t ManufacturerID; /*!< Manufacturer ID */
+ __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
+ __IO uint32_t ProdName1; /*!< Product Name part1 */
+ __IO uint8_t ProdName2; /*!< Product Name part2 */
+ __IO uint8_t ProdRev; /*!< Product Revision */
+ __IO uint32_t ProdSN; /*!< Product Serial Number */
+ __IO uint8_t Reserved1; /*!< Reserved1 */
+ __IO uint16_t ManufactDate; /*!< Manufacturing Date */
+ __IO uint8_t CID_CRC; /*!< CID CRC */
+ __IO uint8_t Reserved2; /*!< Always 1 */
+
+}HAL_SD_CIDTypedef;
+
+/**
+ * @brief SD Card Status returned by ACMD13
+ */
+typedef struct
+{
+ __IO uint8_t DAT_BUS_WIDTH; /*!< Shows the currently defined data bus width */
+ __IO uint8_t SECURED_MODE; /*!< Card is in secured mode of operation */
+ __IO uint16_t SD_CARD_TYPE; /*!< Carries information about card type */
+ __IO uint32_t SIZE_OF_PROTECTED_AREA; /*!< Carries information about the capacity of protected area */
+ __IO uint8_t SPEED_CLASS; /*!< Carries information about the speed class of the card */
+ __IO uint8_t PERFORMANCE_MOVE; /*!< Carries information about the card's performance move */
+ __IO uint8_t AU_SIZE; /*!< Carries information about the card's allocation unit size */
+ __IO uint16_t ERASE_SIZE; /*!< Determines the number of AUs to be erased in one operation */
+ __IO uint8_t ERASE_TIMEOUT; /*!< Determines the timeout for any number of AU erase */
+ __IO uint8_t ERASE_OFFSET; /*!< Carries information about the erase offset */
+
+}HAL_SD_CardStatusTypedef;
+
+/**
+ * @brief SD Card information structure
+ */
+typedef struct
+{
+ HAL_SD_CSDTypedef SD_csd; /*!< SD card specific data register */
+ HAL_SD_CIDTypedef SD_cid; /*!< SD card identification number register */
+ uint64_t CardCapacity; /*!< Card capacity */
+ uint32_t CardBlockSize; /*!< Card block size */
+ uint16_t RCA; /*!< SD relative card address */
+ uint8_t CardType; /*!< SD card type */
+
+}HAL_SD_CardInfoTypedef;
+
+/**
+ * @brief SD Error status enumeration Structure definition
+ */
+typedef enum
+{
+/**
+ * @brief SD specific error defines
+ */
+ SD_CMD_CRC_FAIL = (1), /*!< Command response received (but CRC check failed) */
+ SD_DATA_CRC_FAIL = (2), /*!< Data block sent/received (CRC check failed) */
+ SD_CMD_RSP_TIMEOUT = (3), /*!< Command response timeout */
+ SD_DATA_TIMEOUT = (4), /*!< Data timeout */
+ SD_TX_UNDERRUN = (5), /*!< Transmit FIFO underrun */
+ SD_RX_OVERRUN = (6), /*!< Receive FIFO overrun */
+ SD_START_BIT_ERR = (7), /*!< Start bit not detected on all data signals in wide bus mode */
+ SD_CMD_OUT_OF_RANGE = (8), /*!< Command's argument was out of range. */
+ SD_ADDR_MISALIGNED = (9), /*!< Misaligned address */
+ SD_BLOCK_LEN_ERR = (10), /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
+ SD_ERASE_SEQ_ERR = (11), /*!< An error in the sequence of erase command occurs. */
+ SD_BAD_ERASE_PARAM = (12), /*!< An invalid selection for erase groups */
+ SD_WRITE_PROT_VIOLATION = (13), /*!< Attempt to program a write protect block */
+ SD_LOCK_UNLOCK_FAILED = (14), /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
+ SD_COM_CRC_FAILED = (15), /*!< CRC check of the previous command failed */
+ SD_ILLEGAL_CMD = (16), /*!< Command is not legal for the card state */
+ SD_CARD_ECC_FAILED = (17), /*!< Card internal ECC was applied but failed to correct the data */
+ SD_CC_ERROR = (18), /*!< Internal card controller error */
+ SD_GENERAL_UNKNOWN_ERROR = (19), /*!< General or unknown error */
+ SD_STREAM_READ_UNDERRUN = (20), /*!< The card could not sustain data transfer in stream read operation. */
+ SD_STREAM_WRITE_OVERRUN = (21), /*!< The card could not sustain data programming in stream mode */
+ SD_CID_CSD_OVERWRITE = (22), /*!< CID/CSD overwrite error */
+ SD_WP_ERASE_SKIP = (23), /*!< Only partial address space was erased */
+ SD_CARD_ECC_DISABLED = (24), /*!< Command has been executed without using internal ECC */
+ SD_ERASE_RESET = (25), /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
+ SD_AKE_SEQ_ERROR = (26), /*!< Error in sequence of authentication. */
+ SD_INVALID_VOLTRANGE = (27),
+ SD_ADDR_OUT_OF_RANGE = (28),
+ SD_SWITCH_ERROR = (29),
+ SD_SDIO_DISABLED = (30),
+ SD_SDIO_FUNCTION_BUSY = (31),
+ SD_SDIO_FUNCTION_FAILED = (32),
+ SD_SDIO_UNKNOWN_FUNCTION = (33),
+
+/**
+ * @brief Standard error defines
+ */
+ SD_INTERNAL_ERROR = (34),
+ SD_NOT_CONFIGURED = (35),
+ SD_REQUEST_PENDING = (36),
+ SD_REQUEST_NOT_APPLICABLE = (37),
+ SD_INVALID_PARAMETER = (38),
+ SD_UNSUPPORTED_FEATURE = (39),
+ SD_UNSUPPORTED_HW = (40),
+ SD_ERROR = (41),
+ SD_OK = (0)
+
+}HAL_SD_ErrorTypedef;
+
+/**
+ * @brief SD Transfer state enumeration structure
+ */
+typedef enum
+{
+ SD_TRANSFER_OK = 0, /*!< Transfer success */
+ SD_TRANSFER_BUSY = 1, /*!< Transfer is occurring */
+ SD_TRANSFER_ERROR = 2 /*!< Transfer failed */
+
+}HAL_SD_TransferStateTypedef;
+
+/**
+ * @brief SD Card State enumeration structure
+ */
+typedef enum
+{
+ SD_CARD_READY = ((uint32_t)0x00000001), /*!< Card state is ready */
+ SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002), /*!< Card is in identification state */
+ SD_CARD_STANDBY = ((uint32_t)0x00000003), /*!< Card is in standby state */
+ SD_CARD_TRANSFER = ((uint32_t)0x00000004), /*!< Card is in transfer state */
+ SD_CARD_SENDING = ((uint32_t)0x00000005), /*!< Card is sending an operation */
+ SD_CARD_RECEIVING = ((uint32_t)0x00000006), /*!< Card is receiving operation information */
+ SD_CARD_PROGRAMMING = ((uint32_t)0x00000007), /*!< Card is in programming state */
+ SD_CARD_DISCONNECTED = ((uint32_t)0x00000008), /*!< Card is disconnected */
+ SD_CARD_ERROR = ((uint32_t)0x000000FF) /*!< Card is in error state */
+
+}HAL_SD_CardStateTypedef;
+
+/**
+ * @brief SD Operation enumeration structure
+ */
+typedef enum
+{
+ SD_READ_SINGLE_BLOCK = 0, /*!< Read single block operation */
+ SD_READ_MULTIPLE_BLOCK = 1, /*!< Read multiple blocks operation */
+ SD_WRITE_SINGLE_BLOCK = 2, /*!< Write single block operation */
+ SD_WRITE_MULTIPLE_BLOCK = 3 /*!< Write multiple blocks operation */
+
+}HAL_SD_OperationTypedef;
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SD_Exported_Constants
+ * @{
+ */
+
+/**
+ * @brief SD Commands Index
+ */
+#define SD_CMD_GO_IDLE_STATE ((uint8_t)0) /*!< Resets the SD memory card. */
+#define SD_CMD_SEND_OP_COND ((uint8_t)1) /*!< Sends host capacity support information and activates the card's initialization process. */
+#define SD_CMD_ALL_SEND_CID ((uint8_t)2) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
+#define SD_CMD_SET_REL_ADDR ((uint8_t)3) /*!< Asks the card to publish a new relative address (RCA). */
+#define SD_CMD_SET_DSR ((uint8_t)4) /*!< Programs the DSR of all cards. */
+#define SD_CMD_SDIO_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
+ operating condition register (OCR) content in the response on the CMD line. */
+#define SD_CMD_HS_SWITCH ((uint8_t)6) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
+#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7) /*!< Selects the card by its own relative address and gets deselected by any other address */
+#define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
+ and asks the card whether card supports voltage. */
+#define SD_CMD_SEND_CSD ((uint8_t)9) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
+#define SD_CMD_SEND_CID ((uint8_t)10) /*!< Addressed card sends its card identification (CID) on the CMD line. */
+#define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD card doesn't support it. */
+#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12) /*!< Forces the card to stop transmission. */
+#define SD_CMD_SEND_STATUS ((uint8_t)13) /*!< Addressed card sends its status register. */
+#define SD_CMD_HS_BUSTEST_READ ((uint8_t)14)
+#define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15) /*!< Sends an addressed card into the inactive state. */
+#define SD_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands
+ (read, write, lock). Default block length is fixed to 512 Bytes. Not effective
+ for SDHS and SDXC. */
+#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
+ fixed 512 bytes in case of SDHC and SDXC. */
+#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by
+ STOP_TRANSMISSION command. */
+#define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
+#define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< Speed class control command. */
+#define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< Specify block count for CMD18 and CMD25. */
+#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
+ fixed 512 bytes in case of SDHC and SDXC. */
+#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
+#define SD_CMD_PROG_CID ((uint8_t)26) /*!< Reserved for manufacturers. */
+#define SD_CMD_PROG_CSD ((uint8_t)27) /*!< Programming of the programmable bits of the CSD. */
+#define SD_CMD_SET_WRITE_PROT ((uint8_t)28) /*!< Sets the write protection bit of the addressed group. */
+#define SD_CMD_CLR_WRITE_PROT ((uint8_t)29) /*!< Clears the write protection bit of the addressed group. */
+#define SD_CMD_SEND_WRITE_PROT ((uint8_t)30) /*!< Asks the card to send the status of the write protection bits. */
+#define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< Sets the address of the first write block to be erased. (For SD card only). */
+#define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< Sets the address of the last write block of the continuous range to be erased. */
+#define SD_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command
+ system set by switch function command (CMD6). */
+#define SD_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased.
+ Reserved for each command system set by switch function command (CMD6). */
+#define SD_CMD_ERASE ((uint8_t)38) /*!< Reserved for SD security applications. */
+#define SD_CMD_FAST_IO ((uint8_t)39) /*!< SD card doesn't support it (Reserved). */
+#define SD_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD card doesn't support it (Reserved). */
+#define SD_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
+ the SET_BLOCK_LEN command. */
+#define SD_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather
+ than a standard command. */
+#define SD_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card
+ for general purpose/application specific commands. */
+#define SD_CMD_NO_CMD ((uint8_t)64)
+
+/**
+ * @brief Following commands are SD Card Specific commands.
+ * SDIO_APP_CMD should be sent before sending these commands.
+ */
+#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
+ widths are given in SCR register. */
+#define SD_CMD_SD_APP_STAUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */
+#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
+ 32bit+CRC data block. */
+#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
+ send its operating condition register (OCR) content in the response on the CMD line. */
+#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */
+#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< Reads the SD Configuration Register (SCR). */
+#define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52) /*!< For SD I/O card only, reserved for security specification. */
+#define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O card only, reserved for security specification. */
+
+/**
+ * @brief Following commands are SD Card Specific security commands.
+ * SD_CMD_APP_CMD should be sent before sending these commands.
+ */
+#define SD_CMD_SD_APP_GET_MKB ((uint8_t)43) /*!< For SD card only */
+#define SD_CMD_SD_APP_GET_MID ((uint8_t)44) /*!< For SD card only */
+#define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45) /*!< For SD card only */
+#define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46) /*!< For SD card only */
+#define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47) /*!< For SD card only */
+#define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48) /*!< For SD card only */
+#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18) /*!< For SD card only */
+#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25) /*!< For SD card only */
+#define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38) /*!< For SD card only */
+#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49) /*!< For SD card only */
+#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48) /*!< For SD card only */
+
+/**
+ * @brief Supported SD Memory Cards
+ */
+#define STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000)
+#define STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001)
+#define HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002)
+#define MULTIMEDIA_CARD ((uint32_t)0x00000003)
+#define SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004)
+#define HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005)
+#define SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006)
+#define HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007)
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup SD_Interrupt_Clock
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+
+/**
+ * @brief Enable the SD device.
+ * @retval None
+ */
+#define __HAL_SD_SDIO_ENABLE() __SDIO_ENABLE()
+
+/**
+ * @brief Disable the SD device.
+ * @retval None
+ */
+#define __HAL_SD_SDIO_DISABLE() __SDIO_DISABLE()
+
+/**
+ * @brief Enable the SDIO DMA transfer.
+ * @retval None
+ */
+#define __HAL_SD_SDIO_DMA_ENABLE() __SDIO_DMA_ENABLE()
+
+/**
+ * @brief Disable the SDIO DMA transfer.
+ * @retval None
+ */
+#define __HAL_SD_SDIO_DMA_DISABLE() __SDIO_DMA_DISABLE()
+
+/**
+ * @brief Enable the SD device interrupt.
+ * @param __HANDLE__: SD Handle
+ * @param __INTERRUPT__: specifies the SDIO interrupt sources to be enabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+ * @retval None
+ */
+#define __HAL_SD_SDIO_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @brief Disable the SD device interrupt.
+ * @param __HANDLE__: SD Handle
+ * @param __INTERRUPT__: specifies the SDIO interrupt sources to be disabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+ * @retval None
+ */
+#define __HAL_SD_SDIO_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified SD flag is set or not.
+ * @param __HANDLE__: SD Handle
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDIO_FLAG_CMDACT: Command transfer in progress
+ * @arg SDIO_FLAG_TXACT: Data transmit in progress
+ * @arg SDIO_FLAG_RXACT: Data receive in progress
+ * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+ * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
+ * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
+ * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
+ * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
+ * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
+ * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
+ * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+ * @retval The new state of SD FLAG (SET or RESET).
+ */
+#define __HAL_SD_SDIO_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+ * @brief Clear the SD's pending flags.
+ * @param __HANDLE__: SD Handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+ * @retval None
+ */
+#define __HAL_SD_SDIO_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+ * @brief Check whether the specified SD interrupt has occurred or not.
+ * @param __HANDLE__: SD Handle
+ * @param __INTERRUPT__: specifies the SDIO interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+ * @retval The new state of SD IT (SET or RESET).
+ */
+#define __HAL_SD_SDIO_GET_IT (__HANDLE__, __INTERRUPT__) __SDIO_GET_IT ((__HANDLE__)->Instance, __INTERRUPT__)
+
+/**
+ * @brief Clear the SD's interrupt pending bits.
+ * @param __HANDLE__ : SD Handle
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
+ * @retval None
+ */
+#define __HAL_SD_SDIO_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions **********************************/
+HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo);
+HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
+void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
+void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
+
+/* I/O operation functions *****************************************************/
+/* Blocking mode: Polling */
+HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
+HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
+HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr);
+
+/* Non-Blocking mode: Interrupt */
+void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
+
+/* Callback in non blocking modes (DMA) */
+void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma);
+void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma);
+void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma);
+void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma);
+void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd);
+
+/* Non-Blocking mode: DMA */
+HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
+HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
+HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
+HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
+
+/* Peripheral Control functions ************************************************/
+HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo);
+HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode);
+HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd);
+HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd);
+
+/* Peripheral State functions **************************************************/
+HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
+HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus);
+HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_SD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_sdram.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,151 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_sdram.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of SDRAM HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SDRAM_H
+#define __STM32F4xx_HAL_SDRAM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_fmc.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SDRAM
+ * @{
+ */
+
+/* Exported typedef ----------------------------------------------------------*/
+
+/**
+ * @brief HAL SDRAM State structure definition
+ */
+typedef enum
+{
+ HAL_SDRAM_STATE_RESET = 0x00, /*!< SDRAM not yet initialized or disabled */
+ HAL_SDRAM_STATE_READY = 0x01, /*!< SDRAM initialized and ready for use */
+ HAL_SDRAM_STATE_BUSY = 0x02, /*!< SDRAM internal process is ongoing */
+ HAL_SDRAM_STATE_ERROR = 0x03, /*!< SDRAM error state */
+ HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04, /*!< SDRAM device write protected */
+ HAL_SDRAM_STATE_PRECHARGED = 0x05 /*!< SDRAM device precharged */
+
+}HAL_SDRAM_StateTypeDef;
+
+/**
+ * @brief SDRAM handle Structure definition
+ */
+typedef struct
+{
+ FMC_SDRAM_TypeDef *Instance; /*!< Register base address */
+
+ FMC_SDRAM_InitTypeDef Init; /*!< SDRAM device configuration parameters */
+
+ __IO HAL_SDRAM_StateTypeDef State; /*!< SDRAM access state */
+
+ HAL_LockTypeDef Lock; /*!< SDRAM locking object */
+
+ DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
+
+}SDRAM_HandleTypeDef;
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset SDRAM handle state
+ * @param __HANDLE__: specifies the SDRAM handle.
+ * @retval None
+ */
+#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);
+HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram);
+void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);
+void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram);
+
+void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram);
+void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);
+void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
+void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
+
+/* I/O operation functions *****************************************************/
+HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+
+HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t * pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+
+/* SDRAM Control functions *****************************************************/
+HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram);
+HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram);
+HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate);
+HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber);
+uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);
+
+/* SDRAM State functions ********************************************************/
+HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_SDRAM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_smartcard.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,452 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_smartcard.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of SMARTCARD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SMARTCARD_H
+#define __STM32F4xx_HAL_SMARTCARD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SMARTCARD
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/**
+ * @brief SMARTCARD Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the SmartCard communication baud rate.
+ The baud rate is computed using the following formula:
+ - IntegerDivider = ((PCLKx) / (8 * (hirda->Init.BaudRate)))
+ - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref SMARTCARD_Word_Length */
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref SMARTCARD_Stop_Bits */
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref SMARTCARD_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits).*/
+
+ uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref SMARTCARD_Mode */
+
+ uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
+ This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
+
+ uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref SMARTCARD_Clock_Phase */
+
+ uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref SMARTCARD_Last_Bit */
+
+ uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t NACKState; /*!< Specifies the SmartCard NACK Transmission state.
+ This parameter can be a value of @ref SmartCard_NACK_State */
+}SMARTCARD_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_SMARTCARD_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */
+ HAL_SMARTCARD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_SMARTCARD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_SMARTCARD_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_SMARTCARD_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
+ HAL_SMARTCARD_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_SMARTCARD_STATE_ERROR = 0x04 /*!< Error */
+}HAL_SMARTCARD_StateTypeDef;
+
+/**
+ * @brief HAL SMARTCARD Error Code structure definition
+ */
+typedef enum
+{
+ HAL_SMARTCARD_ERROR_NONE = 0x00, /*!< No error */
+ HAL_SMARTCARD_ERROR_PE = 0x01, /*!< Parity error */
+ HAL_SMARTCARD_ERROR_NE = 0x02, /*!< Noise error */
+ HAL_SMARTCARD_ERROR_FE = 0x04, /*!< frame error */
+ HAL_SMARTCARD_ERROR_ORE = 0x08, /*!< Overrun error */
+ HAL_SMARTCARD_ERROR_DMA = 0x10 /*!< DMA transfer error */
+}HAL_SMARTCARD_ErrorTypeDef;
+
+/**
+ * @brief SMARTCARD handle Structure definition
+ */
+typedef struct
+{
+ USART_TypeDef *Instance; /* USART registers base address */
+
+ SMARTCARD_InitTypeDef Init; /* SmartCard communication parameters */
+
+ uint8_t *pTxBuffPtr; /* Pointer to SmartCard Tx transfer Buffer */
+
+ uint16_t TxXferSize; /* SmartCard Tx Transfer size */
+
+ uint16_t TxXferCount; /* SmartCard Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /* Pointer to SmartCard Rx transfer Buffer */
+
+ uint16_t RxXferSize; /* SmartCard Rx Transfer size */
+
+ uint16_t RxXferCount; /* SmartCard Rx Transfer Counter */
+
+ DMA_HandleTypeDef *hdmatx; /* SmartCard Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /* SmartCard Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /* Locking object */
+
+ __IO HAL_SMARTCARD_StateTypeDef State; /* SmartCard communication state */
+
+ __IO HAL_SMARTCARD_ErrorTypeDef ErrorCode; /* SMARTCARD Error code */
+}SMARTCARD_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Constants
+ * @{
+ */
+
+/** @defgroup SMARTCARD_Word_Length
+ * @{
+ */
+#define SMARTCARD_WORDLENGTH_8B ((uint32_t)0x00000000)
+#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
+#define IS_SMARTCARD_WORD_LENGTH(LENGTH) (((LENGTH) == SMARTCARD_WORDLENGTH_8B) || \
+ ((LENGTH) == SMARTCARD_WORDLENGTH_9B))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Stop_Bits
+ * @{
+ */
+#define SMARTCARD_STOPBITS_1 ((uint32_t)0x00000000)
+#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
+#define SMARTCARD_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
+#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
+#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_1) || \
+ ((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
+ ((STOPBITS) == SMARTCARD_STOPBITS_1_5) || \
+ ((STOPBITS) == SMARTCARD_STOPBITS_2))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Parity
+ * @{
+ */
+#define SMARTCARD_PARITY_NONE ((uint32_t)0x00000000)
+#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
+#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_NONE) || \
+ ((PARITY) == SMARTCARD_PARITY_EVEN) || \
+ ((PARITY) == SMARTCARD_PARITY_ODD))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Mode
+ * @{
+ */
+#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
+#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
+#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+#define IS_SMARTCARD_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Clock_Polarity
+ * @{
+ */
+#define SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000)
+#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
+#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Clock_Phase
+ * @{
+ */
+#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000)
+#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
+#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Last_Bit
+ * @{
+ */
+#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000)
+#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
+#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
+ ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SmartCard_NACK_State
+ * @{
+ */
+#define SMARTCARD_NACK_ENABLED ((uint32_t)USART_CR3_NACK)
+#define SMARTCARD_NACK_DISABLED ((uint32_t)0x00000000)
+#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLED) || \
+ ((NACK) == SMARTCARD_NACK_DISABLED))
+/**
+ * @}
+ */
+
+/** @defgroup SmartCard_DMA_Requests
+ * @{
+ */
+
+#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)
+#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)
+
+/**
+ * @}
+ */
+
+/** @defgroup SmartCard_Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the SR register
+ * @{
+ */
+
+#define SMARTCARD_FLAG_TXE ((uint32_t)0x00000080)
+#define SMARTCARD_FLAG_TC ((uint32_t)0x00000040)
+#define SMARTCARD_FLAG_RXNE ((uint32_t)0x00000020)
+#define SMARTCARD_FLAG_IDLE ((uint32_t)0x00000010)
+#define SMARTCARD_FLAG_ORE ((uint32_t)0x00000008)
+#define SMARTCARD_FLAG_NE ((uint32_t)0x00000004)
+#define SMARTCARD_FLAG_FE ((uint32_t)0x00000002)
+#define SMARTCARD_FLAG_PE ((uint32_t)0x00000001)
+/**
+ * @}
+ */
+
+/** @defgroup SmartCard_Interrupt_definition
+ * Elements values convention: 0xY000XXXX
+ * - XXXX : Interrupt mask in the XX register
+ * - Y : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR3 register
+
+ *
+ * @{
+ */
+#define SMARTCARD_IT_PE ((uint32_t)0x10000100)
+#define SMARTCARD_IT_TXE ((uint32_t)0x10000080)
+#define SMARTCARD_IT_TC ((uint32_t)0x10000040)
+#define SMARTCARD_IT_RXNE ((uint32_t)0x10000020)
+#define SMARTCARD_IT_IDLE ((uint32_t)0x10000010)
+#define SMARTCARD_IT_ERR ((uint32_t)0x20000001)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset SMARTCARD handle state
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET)
+
+/** @brief Flushs the Smartcard DR register
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ */
+#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
+
+/** @brief Checks whether the specified Smartcard flag is set or not.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_FLAG_TXE: Transmit data register empty flag
+ * @arg SMARTCARD_FLAG_TC: Transmission Complete flag
+ * @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag
+ * @arg SMARTCARD_FLAG_IDLE: Idle Line detection flag
+ * @arg SMARTCARD_FLAG_ORE: OverRun Error flag
+ * @arg SMARTCARD_FLAG_NE: Noise Error flag
+ * @arg SMARTCARD_FLAG_FE: Framing Error flag
+ * @arg SMARTCARD_FLAG_PE: Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the specified Smartcard pending flags.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg SMARTCARD_FLAG_TC: Transmission Complete flag.
+ * @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag.
+ *
+ * @note PE (Parity error), FE (Framing error), NE (Noise error) and ORE (OverRun
+ * error) flags are cleared by software sequence: a read operation to
+ * USART_SR register followed by a read operation to USART_DR register.
+ * @note RXNE flag can be also cleared by a read to the USART_DR register.
+ * @note TC flag can be also cleared by software sequence: a read operation to
+ * USART_SR register followed by a write operation to USART_DR register.
+ * @note TXE flag is cleared only by a write to the USART_DR register.
+ */
+#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
+
+/** @brief Enables or disables the specified SmartCard interrupts.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __INTERRUPT__: specifies the SMARTCARD interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
+ * @arg SMARTCARD_IT_TC: Transmission complete interrupt
+ * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
+ * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
+ * @arg SMARTCARD_IT_PE: Parity Error interrupt
+ * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ */
+#define SMARTCARD_IT_MASK ((uint32_t)0x0000FFFF)
+#define __SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
+#define __SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
+
+/** @brief Checks whether the specified SmartCard interrupt has occurred or not.
+ * @param __HANDLE__: specifies the SmartCard Handle.
+ * @param __IT__: specifies the SMARTCARD interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
+ * @arg SMARTCARD_IT_TC: Transmission complete interrupt
+ * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
+ * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
+ * @arg SMARTCARD_IT_ERR: Error interrupt
+ * @arg SMARTCARD_IT_PE: Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
+
+/** @brief Macros to enable or disable the SmartCard interface.
+ * @param __HANDLE__: specifies the SmartCard Handle.
+ */
+#define __SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+#define __SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/** @brief Macros to enable or disable the SmartCard DMA request.
+ * @param __HANDLE__: specifies the SmartCard Handle.
+ * @param __REQUEST__: specifies the SmartCard DMA request.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
+ * @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
+ */
+#define __SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 |= (__REQUEST__))
+#define __SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__))
+
+#define __DIV(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
+#define __DIVMANT(_PCLK_, _BAUD_) (__DIV((_PCLK_), (_BAUD_))/100)
+#define __DIVFRAQ(_PCLK_, _BAUD_) (((__DIV((_PCLK_), (_BAUD_)) - (__DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define __SMARTCARD_BRR(_PCLK_, _BAUD_) ((__DIVMANT((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
+
+#define IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001)
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc);
+HAL_StatusTypeDef HAL_SMARTCARD_ReInit(SMARTCARD_HandleTypeDef *hsc);
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc);
+void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc);
+void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc);
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc);
+void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
+void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
+void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);
+
+/* Peripheral State functions **************************************************/
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc);
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_SMARTCARD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_spi.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,481 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_spi.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of SPI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SPI_H
+#define __STM32F4xx_HAL_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief SPI Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Specifies the SPI operating mode.
+ This parameter can be a value of @ref SPI_mode */
+
+ uint32_t Direction; /*!< Specifies the SPI Directional mode state.
+ This parameter can be a value of @ref SPI_Direction_mode */
+
+ uint32_t DataSize; /*!< Specifies the SPI data size.
+ This parameter can be a value of @ref SPI_data_size */
+
+ uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
+ This parameter can be a value of @ref SPI_Clock_Polarity */
+
+ uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be a value of @ref SPI_Clock_Phase */
+
+ uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
+ hardware (NSS pin) or by software using the SSI bit.
+ This parameter can be a value of @ref SPI_Slave_Select_management */
+
+ uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
+ used to configure the transmit and receive SCK clock.
+ This parameter can be a value of @ref SPI_BaudRate_Prescaler
+ @note The communication clock is derived from the master
+ clock. The slave clock does not need to be set */
+
+ uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+ uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
+ This parameter can be a value of @ref SPI_TI_mode */
+
+ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
+ This parameter can be a value of @ref SPI_CRC_Calculation */
+
+ uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
+
+}SPI_InitTypeDef;
+
+/**
+ * @brief HAL SPI State structure definition
+ */
+typedef enum
+{
+ HAL_SPI_STATE_RESET = 0x00, /*!< SPI not yet initialized or disabled */
+ HAL_SPI_STATE_READY = 0x01, /*!< SPI initialized and ready for use */
+ HAL_SPI_STATE_BUSY = 0x02, /*!< SPI process is ongoing */
+ HAL_SPI_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_SPI_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_SPI_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
+ HAL_SPI_STATE_ERROR = 0x03 /*!< SPI error state */
+
+}HAL_SPI_StateTypeDef;
+
+/**
+ * @brief HAL SPI Error Code structure definition
+ */
+typedef enum
+{
+ HAL_SPI_ERROR_NONE = 0x00, /*!< No error */
+ HAL_SPI_ERROR_MODF = 0x01, /*!< MODF error */
+ HAL_SPI_ERROR_CRC = 0x02, /*!< CRC error */
+ HAL_SPI_ERROR_OVR = 0x04, /*!< OVR error */
+ HAL_SPI_ERROR_FRE = 0x08, /*!< FRE error */
+ HAL_SPI_ERROR_DMA = 0x10, /*!< DMA transfer error */
+ HAL_SPI_ERROR_FLAG = 0x20 /*!< Flag: RXNE,TXE, BSY */
+
+}HAL_SPI_ErrorTypeDef;
+
+/**
+ * @brief SPI handle Structure definition
+ */
+typedef struct __SPI_HandleTypeDef
+{
+ SPI_TypeDef *Instance; /* SPI registers base address */
+
+ SPI_InitTypeDef Init; /* SPI communication parameters */
+
+ uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */
+
+ uint16_t TxXferSize; /* SPI Tx transfer size */
+
+ uint16_t TxXferCount; /* SPI Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */
+
+ uint16_t RxXferSize; /* SPI Rx transfer size */
+
+ uint16_t RxXferCount; /* SPI Rx Transfer Counter */
+
+ DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA handle parameters */
+
+ void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */
+
+ void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */
+
+ HAL_LockTypeDef Lock; /* SPI locking object */
+
+ __IO HAL_SPI_StateTypeDef State; /* SPI communication state */
+
+ __IO HAL_SPI_ErrorTypeDef ErrorCode; /* SPI Error code */
+
+}SPI_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SPI_Exported_Constants
+ * @{
+ */
+
+/** @defgroup SPI_mode
+ * @{
+ */
+#define SPI_MODE_SLAVE ((uint32_t)0x00000000)
+#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
+
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
+ ((MODE) == SPI_MODE_MASTER))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Direction_mode
+ * @{
+ */
+#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
+#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
+#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
+
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
+ ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
+ ((MODE) == SPI_DIRECTION_1LINE))
+
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
+ ((MODE) == SPI_DIRECTION_1LINE))
+
+#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_data_size
+ * @{
+ */
+#define SPI_DATASIZE_8BIT ((uint32_t)0x00000000)
+#define SPI_DATASIZE_16BIT SPI_CR1_DFF
+
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_8BIT))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Polarity
+ * @{
+ */
+#define SPI_POLARITY_LOW ((uint32_t)0x00000000)
+#define SPI_POLARITY_HIGH SPI_CR1_CPOL
+
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
+ ((CPOL) == SPI_POLARITY_HIGH))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Phase
+ * @{
+ */
+#define SPI_PHASE_1EDGE ((uint32_t)0x00000000)
+#define SPI_PHASE_2EDGE SPI_CR1_CPHA
+
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
+ ((CPHA) == SPI_PHASE_2EDGE))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Slave_Select_management
+ * @{
+ */
+#define SPI_NSS_SOFT SPI_CR1_SSM
+#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
+#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)
+
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
+ ((NSS) == SPI_NSS_HARD_INPUT) || \
+ ((NSS) == SPI_NSS_HARD_OUTPUT))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_BaudRate_Prescaler
+ * @{
+ */
+#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
+#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008)
+#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010)
+#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018)
+#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020)
+#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)
+#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)
+#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)
+
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_MSB_LSB_transmission
+ * @{
+ */
+#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
+#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
+
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
+ ((BIT) == SPI_FIRSTBIT_LSB))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_TI_mode
+ * @{
+ */
+#define SPI_TIMODE_DISABLED ((uint32_t)0x00000000)
+#define SPI_TIMODE_ENABLED SPI_CR2_FRF
+
+#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLED) || \
+ ((MODE) == SPI_TIMODE_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_Calculation
+ * @{
+ */
+#define SPI_CRCCALCULATION_DISABLED ((uint32_t)0x00000000)
+#define SPI_CRCCALCULATION_ENABLED SPI_CR1_CRCEN
+
+#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) || \
+ ((CALCULATION) == SPI_CRCCALCULATION_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Interrupt_configuration_definition
+ * @{
+ */
+#define SPI_IT_TXE SPI_CR2_TXEIE
+#define SPI_IT_RXNE SPI_CR2_RXNEIE
+#define SPI_IT_ERR SPI_CR2_ERRIE
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Flag_definition
+ * @{
+ */
+#define SPI_FLAG_RXNE SPI_SR_RXNE
+#define SPI_FLAG_TXE SPI_SR_TXE
+#define SPI_FLAG_CRCERR SPI_SR_CRCERR
+#define SPI_FLAG_MODF SPI_SR_MODF
+#define SPI_FLAG_OVR SPI_SR_OVR
+#define SPI_FLAG_BSY SPI_SR_BSY
+#define SPI_FLAG_FRE SPI_SR_FRE
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset SPI handle state
+ * @param __HANDLE__: specifies the SPI handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
+
+/** @brief Enable or disable the specified SPI interrupts.
+ * @param __HANDLE__: specifies the SPI handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg SPI_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
+#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
+
+/** @brief Check if the specified SPI interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the SPI handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @param __INTERRUPT__: specifies the SPI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg SPI_IT_ERR: Error interrupt enable
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Check whether the specified SPI flag is set or not.
+ * @param __HANDLE__: specifies the SPI handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
+ * @arg SPI_FLAG_TXE: Transmit buffer empty flag
+ * @arg SPI_FLAG_CRCERR: CRC error flag
+ * @arg SPI_FLAG_MODF: Mode fault flag
+ * @arg SPI_FLAG_OVR: Overrun flag
+ * @arg SPI_FLAG_BSY: Busy flag
+ * @arg SPI_FLAG_FRE: Frame format error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the SPI CRCERR pending flag.
+ * @param __HANDLE__: specifies the SPI handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR &= ~(SPI_FLAG_CRCERR))
+
+/** @brief Clear the SPI MODF pending flag.
+ * @param __HANDLE__: specifies the SPI handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
+ (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE);}while(0)
+
+/** @brief Clear the SPI OVR pending flag.
+ * @param __HANDLE__: specifies the SPI handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\
+ (__HANDLE__)->Instance->SR;}while(0)
+
+/** @brief Clear the SPI FRE pending flag.
+ * @param __HANDLE__: specifies the SPI handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR)
+
+#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
+#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_SPE)
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
+
+#define __HAL_SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
+
+#define __HAL_SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_BIDIOE)
+
+#define __HAL_SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_CRCEN);\
+ (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
+
+/* I/O operation functions *****************************************************/
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
+
+/* Peripheral State and Control functions **************************************/
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
+HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_SPI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_sram.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,152 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_sram.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of SRAM HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SRAM_H
+#define __STM32F4xx_HAL_SRAM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+ #include "stm32f4xx_ll_fsmc.h"
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+ #include "stm32f4xx_ll_fmc.h"
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SRAM
+ * @{
+ */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Exported typedef ----------------------------------------------------------*/
+
+/**
+ * @brief HAL SRAM State structures definition
+ */
+typedef enum
+{
+ HAL_SRAM_STATE_RESET = 0x00, /*!< SRAM not yet initialized or disabled */
+ HAL_SRAM_STATE_READY = 0x01, /*!< SRAM initialized and ready for use */
+ HAL_SRAM_STATE_BUSY = 0x02, /*!< SRAM internal process is ongoing */
+ HAL_SRAM_STATE_ERROR = 0x03, /*!< SRAM error state */
+ HAL_SRAM_STATE_PROTECTED = 0x04 /*!< SRAM peripheral NORSRAM device write protected */
+
+}HAL_SRAM_StateTypeDef;
+
+/**
+ * @brief SRAM handle Structure definition
+ */
+typedef struct
+{
+ FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
+
+ FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
+
+ FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
+
+ HAL_LockTypeDef Lock; /*!< SRAM locking object */
+
+ __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
+
+ DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
+
+}SRAM_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset SRAM handle state
+ * @param __HANDLE__: SRAM handle
+ * @retval None
+ */
+#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
+void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
+void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
+
+/* I/O operation functions *****************************************************/
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+
+void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
+void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
+
+/* SRAM Control functions ******************************************************/
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
+
+/* SRAM State functions *********************************************************/
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_SRAM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_tim.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,1377 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_tim.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of TIM HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_TIM_H
+#define __STM32F4xx_HAL_TIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL
+ * @{
+ */
+
+/** @addtogroup TIM
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief TIM Time base Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t CounterMode; /*!< Specifies the counter mode.
+ This parameter can be a value of @ref TIM_Counter_Mode */
+
+ uint32_t Period; /*!< Specifies the period value to be loaded into the active
+ Auto-Reload Register at the next update event.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t ClockDivision; /*!< Specifies the clock division.
+ This parameter can be a value of @ref TIM_ClockDivision */
+
+ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
+ reaches zero, an update event is generated and counting restarts
+ from the RCR value (N).
+ This means in PWM mode that (N+1) corresponds to:
+ - the number of PWM periods in edge-aligned mode
+ - the number of half PWM period in center-aligned mode
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+ @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_Base_InitTypeDef;
+
+/**
+ * @brief TIM Output Compare Configuration Structure definition
+ */
+
+typedef struct
+{
+ uint32_t OCMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t OCFastMode; /*!< Specifies the Fast mode state.
+ This parameter can be a value of @ref TIM_Output_Fast_State
+ @note This parameter is valid only in PWM1 and PWM2 mode. */
+
+
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_OC_InitTypeDef;
+
+/**
+ * @brief TIM One Pulse Mode Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t OCMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t ICSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_OnePulse_InitTypeDef;
+
+
+/**
+ * @brief TIM Input Capture Configuration Structure definition
+ */
+
+typedef struct
+{
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t ICSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_IC_InitTypeDef;
+
+/**
+ * @brief TIM Encoder Configuration Structure definition
+ */
+
+typedef struct
+{
+ uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Encoder_Mode */
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t IC1Selection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t IC1Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+ uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t IC2Selection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t IC2Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_Encoder_InitTypeDef;
+
+/**
+ * @brief Clock Configuration Handle Structure definition
+ */
+typedef struct
+{
+ uint32_t ClockSource; /*!< TIM clock sources.
+ This parameter can be a value of @ref TIM_Clock_Source */
+ uint32_t ClockPolarity; /*!< TIM clock polarity.
+ This parameter can be a value of @ref TIM_Clock_Polarity */
+ uint32_t ClockPrescaler; /*!< TIM clock prescaler.
+ This parameter can be a value of @ref TIM_Clock_Prescaler */
+ uint32_t ClockFilter; /*!< TIM clock filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+}TIM_ClockConfigTypeDef;
+
+/**
+ * @brief Clear Input Configuration Handle Structure definition
+ */
+typedef struct
+{
+ uint32_t ClearInputState; /*!< TIM clear Input state.
+ This parameter can be ENABLE or DISABLE */
+ uint32_t ClearInputSource; /*!< TIM clear Input sources.
+ This parameter can be a value of @ref TIM_ClearInput_Source */
+ uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
+ This parameter can be a value of @ref TIM_ClearInput_Polarity */
+ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
+ This parameter can be a value of @ref TIM_ClearInput_Prescaler */
+ uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+}TIM_ClearInputConfigTypeDef;
+
+/**
+ * @brief TIM Slave configuration Structure definition
+ */
+typedef struct {
+ uint32_t SlaveMode; /*!< Slave mode selection
+ This parameter can be a value of @ref TIM_Slave_Mode */
+ uint32_t InputTrigger; /*!< Input Trigger source
+ This parameter can be a value of @ref TIM_Trigger_Selection */
+ uint32_t TriggerPolarity; /*!< Input Trigger polarity
+ This parameter can be a value of @ref TIM_Trigger_Polarity */
+ uint32_t TriggerPrescaler; /*!< Input trigger prescaler
+ This parameter can be a value of @ref TIM_Trigger_Prescaler */
+ uint32_t TriggerFilter; /*!< Input trigger filter
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+}TIM_SlaveConfigTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
+ HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
+ HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
+}HAL_TIM_StateTypeDef;
+
+/**
+ * @brief HAL Active channel structures definition
+ */
+typedef enum
+{
+ HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */
+ HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */
+ HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
+ HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */
+ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
+}HAL_TIM_ActiveChannel;
+
+/**
+ * @brief TIM Time Base Handle Structure definition
+ */
+typedef struct
+{
+ TIM_TypeDef *Instance; /*!< Register base address */
+ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
+ HAL_TIM_ActiveChannel Channel; /*!< Active channel */
+ DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
+ This array is accessed by a @ref DMA_Handle_index */
+ HAL_LockTypeDef Lock; /*!< Locking object */
+ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
+}TIM_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_Exported_Constants
+ * @{
+ */
+
+/** @defgroup TIM_Input_Channel_Polarity
+ * @{
+ */
+#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */
+#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
+#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ETR_Polarity
+ * @{
+ */
+#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ETR_Prescaler
+ * @{
+ */
+#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
+#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
+#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Counter_Mode
+ * @{
+ */
+#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
+#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
+#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
+#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
+#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
+
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
+ ((MODE) == TIM_COUNTERMODE_DOWN) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClockDivision
+ * @{
+ */
+#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
+#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
+#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
+
+#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
+ ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
+ ((DIV) == TIM_CLOCKDIVISION_DIV4))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes
+ * @{
+ */
+#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
+#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
+#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
+#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
+#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
+#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
+#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
+#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
+
+#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
+ ((MODE) == TIM_OCMODE_PWM2))
+
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
+ ((MODE) == TIM_OCMODE_ACTIVE) || \
+ ((MODE) == TIM_OCMODE_INACTIVE) || \
+ ((MODE) == TIM_OCMODE_TOGGLE) || \
+ ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
+ ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_State
+ * @{
+ */
+#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
+#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
+
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
+ ((STATE) == TIM_OUTPUTSTATE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Fast_State
+ * @{
+ */
+#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
+#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
+
+#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
+ ((STATE) == TIM_OCFAST_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_State
+ * @{
+ */
+#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
+#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
+
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
+ ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Polarity
+ * @{
+ */
+#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
+#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
+
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
+ ((POLARITY) == TIM_OCPOLARITY_LOW))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Polarity
+ * @{
+ */
+#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
+#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
+
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
+ ((POLARITY) == TIM_OCNPOLARITY_LOW))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Idle_State
+ * @{
+ */
+#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
+#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
+ ((STATE) == TIM_OCIDLESTATE_RESET))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Idle_State
+ * @{
+ */
+#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
+#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
+ ((STATE) == TIM_OCNIDLESTATE_RESET))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Channel
+ * @{
+ */
+#define TIM_CHANNEL_1 ((uint32_t)0x0000)
+#define TIM_CHANNEL_2 ((uint32_t)0x0004)
+#define TIM_CHANNEL_3 ((uint32_t)0x0008)
+#define TIM_CHANNEL_4 ((uint32_t)0x000C)
+#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
+
+#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4) || \
+ ((CHANNEL) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))
+
+#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))
+
+#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Polarity
+ * @{
+ */
+#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
+#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
+#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
+
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
+ ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
+ ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Selection
+ * @{
+ */
+#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
+
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
+ ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
+ ((SELECTION) == TIM_ICSELECTION_TRC))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Prescaler
+ * @{
+ */
+#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */
+#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
+#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
+#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
+
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
+ ((PRESCALER) == TIM_ICPSC_DIV2) || \
+ ((PRESCALER) == TIM_ICPSC_DIV4) || \
+ ((PRESCALER) == TIM_ICPSC_DIV8))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_One_Pulse_Mode
+ * @{
+ */
+#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
+#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
+ ((MODE) == TIM_OPMODE_REPETITIVE))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Encoder_Mode
+ * @{
+ */
+#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
+#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
+#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
+ ((MODE) == TIM_ENCODERMODE_TI2) || \
+ ((MODE) == TIM_ENCODERMODE_TI12))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Interrupt_definition
+ * @{
+ */
+#define TIM_IT_UPDATE (TIM_DIER_UIE)
+#define TIM_IT_CC1 (TIM_DIER_CC1IE)
+#define TIM_IT_CC2 (TIM_DIER_CC2IE)
+#define TIM_IT_CC3 (TIM_DIER_CC3IE)
+#define TIM_IT_CC4 (TIM_DIER_CC4IE)
+#define TIM_IT_COM (TIM_DIER_COMIE)
+#define TIM_IT_TRIGGER (TIM_DIER_TIE)
+#define TIM_IT_BREAK (TIM_DIER_BIE)
+
+#define IS_TIM_IT(IT) ((((IT) & 0xFFFFFF00) == 0x00000000) && ((IT) != 0x00000000))
+
+#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_UPDATE) || \
+ ((IT) == TIM_IT_CC1) || \
+ ((IT) == TIM_IT_CC2) || \
+ ((IT) == TIM_IT_CC3) || \
+ ((IT) == TIM_IT_CC4) || \
+ ((IT) == TIM_IT_COM) || \
+ ((IT) == TIM_IT_TRIGGER) || \
+ ((IT) == TIM_IT_BREAK))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_sources
+ * @{
+ */
+#define TIM_DMA_UPDATE (TIM_DIER_UDE)
+#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
+#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
+#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
+#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
+#define TIM_DMA_COM (TIM_DIER_COMDE)
+#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Event_Source
+ * @{
+ */
+#define TIM_EventSource_Update TIM_EGR_UG
+#define TIM_EventSource_CC1 TIM_EGR_CC1G
+#define TIM_EventSource_CC2 TIM_EGR_CC2G
+#define TIM_EventSource_CC3 TIM_EGR_CC3G
+#define TIM_EventSource_CC4 TIM_EGR_CC4G
+#define TIM_EventSource_COM TIM_EGR_COMG
+#define TIM_EventSource_Trigger TIM_EGR_TG
+#define TIM_EventSource_Break TIM_EGR_BG
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Flag_definition
+ * @{
+ */
+#define TIM_FLAG_UPDATE (TIM_SR_UIF)
+#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
+#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
+#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
+#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
+#define TIM_FLAG_COM (TIM_SR_COMIF)
+#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
+#define TIM_FLAG_BREAK (TIM_SR_BIF)
+#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
+#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
+#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
+#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
+
+#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) || \
+ ((FLAG) == TIM_FLAG_CC1) || \
+ ((FLAG) == TIM_FLAG_CC2) || \
+ ((FLAG) == TIM_FLAG_CC3) || \
+ ((FLAG) == TIM_FLAG_CC4) || \
+ ((FLAG) == TIM_FLAG_COM) || \
+ ((FLAG) == TIM_FLAG_TRIGGER) || \
+ ((FLAG) == TIM_FLAG_BREAK) || \
+ ((FLAG) == TIM_FLAG_CC1OF) || \
+ ((FLAG) == TIM_FLAG_CC2OF) || \
+ ((FLAG) == TIM_FLAG_CC3OF) || \
+ ((FLAG) == TIM_FLAG_CC4OF))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Source
+ * @{
+ */
+#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
+#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
+#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
+#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
+#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
+#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
+#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
+#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
+#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
+#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
+
+#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Polarity
+ * @{
+ */
+#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
+
+#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Prescaler
+ * @{
+ */
+#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
+#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
+#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
+
+#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Filter
+ * @{
+ */
+#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClearInput_Source
+ * @{
+ */
+#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
+#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
+
+#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
+ ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClearInput_Polarity
+ * @{
+ */
+#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
+#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+ ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClearInput_Prescaler
+ * @{
+ */
+#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
+#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClearInput_Filter
+ * @{
+ */
+#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Slave_Mode
+ * @{
+ */
+#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
+#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
+#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
+#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
+#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
+
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
+ ((MODE) == TIM_SLAVEMODE_GATED) || \
+ ((MODE) == TIM_SLAVEMODE_RESET) || \
+ ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
+ ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Selection
+ * @{
+ */
+#define TIM_TS_ITR0 ((uint32_t)0x0000)
+#define TIM_TS_ITR1 ((uint32_t)0x0010)
+#define TIM_TS_ITR2 ((uint32_t)0x0020)
+#define TIM_TS_ITR3 ((uint32_t)0x0030)
+#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
+#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
+#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
+#define TIM_TS_ETRF ((uint32_t)0x0070)
+#define TIM_TS_NONE ((uint32_t)0xFFFF)
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3) || \
+ ((SELECTION) == TIM_TS_TI1F_ED) || \
+ ((SELECTION) == TIM_TS_TI1FP1) || \
+ ((SELECTION) == TIM_TS_TI2FP2) || \
+ ((SELECTION) == TIM_TS_ETRF))
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3))
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3) || \
+ ((SELECTION) == TIM_TS_NONE))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Polarity
+ * @{
+ */
+#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+
+#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Prescaler
+ * @{
+ */
+#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
+#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
+#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
+
+#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Filter
+ * @{
+ */
+#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+ /** @defgroup TIM_TI1_Selection
+ * @{
+ */
+#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
+#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
+
+#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
+ ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Base_address
+ * @{
+ */
+#define TIM_DMABase_CR1 (0x00000000)
+#define TIM_DMABase_CR2 (0x00000001)
+#define TIM_DMABase_SMCR (0x00000002)
+#define TIM_DMABase_DIER (0x00000003)
+#define TIM_DMABase_SR (0x00000004)
+#define TIM_DMABase_EGR (0x00000005)
+#define TIM_DMABase_CCMR1 (0x00000006)
+#define TIM_DMABase_CCMR2 (0x00000007)
+#define TIM_DMABase_CCER (0x00000008)
+#define TIM_DMABase_CNT (0x00000009)
+#define TIM_DMABase_PSC (0x0000000A)
+#define TIM_DMABase_ARR (0x0000000B)
+#define TIM_DMABase_RCR (0x0000000C)
+#define TIM_DMABase_CCR1 (0x0000000D)
+#define TIM_DMABase_CCR2 (0x0000000E)
+#define TIM_DMABase_CCR3 (0x0000000F)
+#define TIM_DMABase_CCR4 (0x00000010)
+#define TIM_DMABase_BDTR (0x00000011)
+#define TIM_DMABase_DCR (0x00000012)
+#define TIM_DMABase_OR (0x00000013)
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
+ ((BASE) == TIM_DMABase_CR2) || \
+ ((BASE) == TIM_DMABase_SMCR) || \
+ ((BASE) == TIM_DMABase_DIER) || \
+ ((BASE) == TIM_DMABase_SR) || \
+ ((BASE) == TIM_DMABase_EGR) || \
+ ((BASE) == TIM_DMABase_CCMR1) || \
+ ((BASE) == TIM_DMABase_CCMR2) || \
+ ((BASE) == TIM_DMABase_CCER) || \
+ ((BASE) == TIM_DMABase_CNT) || \
+ ((BASE) == TIM_DMABase_PSC) || \
+ ((BASE) == TIM_DMABase_ARR) || \
+ ((BASE) == TIM_DMABase_RCR) || \
+ ((BASE) == TIM_DMABase_CCR1) || \
+ ((BASE) == TIM_DMABase_CCR2) || \
+ ((BASE) == TIM_DMABase_CCR3) || \
+ ((BASE) == TIM_DMABase_CCR4) || \
+ ((BASE) == TIM_DMABase_BDTR) || \
+ ((BASE) == TIM_DMABase_DCR) || \
+ ((BASE) == TIM_DMABase_OR))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Burst_Length
+ * @{
+ */
+#define TIM_DMABurstLength_1Transfer (0x00000000)
+#define TIM_DMABurstLength_2Transfers (0x00000100)
+#define TIM_DMABurstLength_3Transfers (0x00000200)
+#define TIM_DMABurstLength_4Transfers (0x00000300)
+#define TIM_DMABurstLength_5Transfers (0x00000400)
+#define TIM_DMABurstLength_6Transfers (0x00000500)
+#define TIM_DMABurstLength_7Transfers (0x00000600)
+#define TIM_DMABurstLength_8Transfers (0x00000700)
+#define TIM_DMABurstLength_9Transfers (0x00000800)
+#define TIM_DMABurstLength_10Transfers (0x00000900)
+#define TIM_DMABurstLength_11Transfers (0x00000A00)
+#define TIM_DMABurstLength_12Transfers (0x00000B00)
+#define TIM_DMABurstLength_13Transfers (0x00000C00)
+#define TIM_DMABurstLength_14Transfers (0x00000D00)
+#define TIM_DMABurstLength_15Transfers (0x00000E00)
+#define TIM_DMABurstLength_16Transfers (0x00000F00)
+#define TIM_DMABurstLength_17Transfers (0x00001000)
+#define TIM_DMABurstLength_18Transfers (0x00001100)
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
+ ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_18Transfers))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Filer_Value
+ * @{
+ */
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Handle_index
+ * @{
+ */
+#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */
+#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
+#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
+#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
+#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
+#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */
+#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */
+/**
+ * @}
+ */
+
+/** @defgroup Channel_CC_State
+ * @{
+ */
+#define TIM_CCx_ENABLE ((uint32_t)0x0001)
+#define TIM_CCx_DISABLE ((uint32_t)0x0000)
+#define TIM_CCxN_ENABLE ((uint32_t)0x0004)
+#define TIM_CCxN_DISABLE ((uint32_t)0x0000)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset TIM handle state
+ * @param __HANDLE__: TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
+
+/**
+ * @brief Enable the TIM peripheral.
+ * @param __HANDLE__: TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
+
+/**
+ * @brief Enable the TIM main Output.
+ * @param __HANDLE__: TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
+
+
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+ channels have been disabled */
+#define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+#define CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
+
+/**
+ * @brief Disable the TIM peripheral.
+ * @param __HANDLE__: TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE(__HANDLE__) \
+ do { \
+ if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
+ { \
+ if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
+ { \
+ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
+ } \
+ } \
+ } while(0)
+
+/* The Main Output of a timer instance is disabled only if all the CCx and CCxN
+ channels have been disabled */
+/**
+ * @brief Disable the TIM main Output.
+ * @param __HANDLE__: TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
+ do { \
+ if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
+ { \
+ if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
+ { \
+ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
+ } \
+ } \
+ } while(0)
+
+#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
+#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
+#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
+#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
+
+#define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR &= ~(__INTERRUPT__))
+
+#define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
+#define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC |= (__PRESC__))
+
+#define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
+
+#define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
+ ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
+
+/**
+ * @brief Sets the TIM Capture Compare Register value on runtime without
+ * calling another time ConfigChannel function.
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__ : TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param __COMPARE__: specifies the Capture Compare register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
+(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
+
+/**
+ * @brief Gets the TIM Capture Compare Register value on runtime
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__ : TIM Channel associated with the capture compare register
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: get capture/compare 1 register value
+ * @arg TIM_CHANNEL_2: get capture/compare 2 register value
+ * @arg TIM_CHANNEL_3: get capture/compare 3 register value
+ * @arg TIM_CHANNEL_4: get capture/compare 4 register value
+ * @retval None
+ */
+#define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
+ (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
+
+/**
+ * @brief Sets the TIM Counter Register value on runtime.
+ * @param __HANDLE__: TIM handle.
+ * @param __COUNTER__: specifies the Counter register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+
+/**
+ * @brief Gets the TIM Counter Register value on runtime.
+ * @param __HANDLE__: TIM handle.
+ * @retval None
+ */
+#define __HAL_TIM_GetCounter(__HANDLE__) ((__HANDLE__)->Instance->CNT)
+
+/**
+ * @brief Sets the TIM Autoreload Register value on runtime without calling
+ * another time any Init function.
+ * @param __HANDLE__: TIM handle.
+ * @param __AUTORELOAD__: specifies the Counter register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \
+ do{ \
+ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
+ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
+ } while(0)
+/**
+ * @brief Gets the TIM Autoreload Register value on runtime
+ * @param __HANDLE__: TIM handle.
+ * @retval None
+ */
+#define __HAL_TIM_GetAutoreload(__HANDLE__) ((__HANDLE__)->Instance->ARR)
+
+/**
+ * @brief Sets the TIM Clock Division value on runtime without calling
+ * another time any Init function.
+ * @param __HANDLE__: TIM handle.
+ * @param __CKD__: specifies the clock division value.
+ * This parameter can be one of the following value:
+ * @arg TIM_CLOCKDIVISION_DIV1
+ * @arg TIM_CLOCKDIVISION_DIV2
+ * @arg TIM_CLOCKDIVISION_DIV4
+ * @retval None
+ */
+#define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \
+ do{ \
+ (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
+ (__HANDLE__)->Instance->CR1 |= (__CKD__); \
+ (__HANDLE__)->Init.ClockDivision = (__CKD__); \
+ } while(0)
+/**
+ * @brief Gets the TIM Clock Division value on runtime
+ * @param __HANDLE__: TIM handle.
+ * @retval None
+ */
+#define __HAL_TIM_GetClockDivision(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+
+/**
+ * @brief Sets the TIM Input Capture prescaler on runtime without calling
+ * another time HAL_TIM_IC_ConfigChannel() function.
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__ : TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+#define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \
+ do{ \
+ __HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \
+ __HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+ } while(0)
+
+/**
+ * @brief Gets the TIM Input Capture prescaler on runtime
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__ : TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
+ * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
+ * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
+ * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
+ * @retval None
+ */
+#define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
+ (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
+/**
+ * @}
+ */
+
+/* Include TIM HAL Extension module */
+#include "stm32f4xx_hal_tim_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Time Base functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
+
+/* Timer Output Compare functions **********************************************/
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Timer PWM functions *********************************************************/
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Timer Input Capture functions ***********************************************/
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Timer One Pulse functions ***************************************************/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+
+/* Timer Encoder functions *****************************************************/
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Interrupt Handler functions **********************************************/
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
+
+/* Control functions *********************************************************/
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
+ uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
+ uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Callback in non blocking modes (Interrupt and DMA) *************************/
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
+
+/* Peripheral State functions **************************************************/
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
+
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
+void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
+void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_TIM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_tim_ex.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,351 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_tim_ex.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of TIM HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_TIM_EX_H
+#define __STM32F4xx_HAL_TIM_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL
+ * @{
+ */
+
+/** @addtogroup TIMEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief TIM Hall sensor Configuration Structure definition
+ */
+
+typedef struct
+{
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t IC1Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+ uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+} TIM_HallSensor_InitTypeDef;
+
+/**
+ * @brief TIM Master configuration Structure definition
+ */
+typedef struct {
+ uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection.
+ This parameter can be a value of @ref TIMEx_Master_Mode_Selection */
+ uint32_t MasterSlaveMode; /*!< Master/slave mode selection.
+ This parameter can be a value of @ref TIMEx_Master_Slave_Mode */
+}TIM_MasterConfigTypeDef;
+
+/**
+ * @brief TIM Break and Dead time configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t OffStateRunMode; /*!< TIM off state in run mode.
+ This parameter can be a value of @ref TIMEx_OSSR_Off_State_Selection_for_Run_mode_state */
+ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode.
+ This parameter can be a value of @ref TIMEx_OSSI_Off_State_Selection_for_Idle_mode_state */
+ uint32_t LockLevel; /*!< TIM Lock level.
+ This parameter can be a value of @ref TIMEx_Lock_level */
+ uint32_t DeadTime; /*!< TIM dead Time.
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+ uint32_t BreakState; /*!< TIM Break State.
+ This parameter can be a value of @ref TIMEx_Break_Input_enable_disable */
+ uint32_t BreakPolarity; /*!< TIM Break input polarity.
+ This parameter can be a value of @ref TIMEx_Break_Polarity */
+ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state.
+ This parameter can be a value of @ref TIMEx_AOE_Bit_Set_Reset */
+}TIM_BreakDeadTimeConfigTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Constants
+ * @{
+ */
+/** @defgroup TIMEx_OSSR_Off_State_Selection_for_Run_mode_state
+ * @{
+ */
+#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
+#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
+
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
+ ((STATE) == TIM_OSSR_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_OSSI_Off_State_Selection_for_Idle_mode_state
+ * @{
+ */
+#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
+#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
+
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
+ ((STATE) == TIM_OSSI_DISABLE))
+/**
+ * @}
+ */
+/** @defgroup TIMEx_Lock_level
+ * @{
+ */
+#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
+#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
+#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
+#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
+
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
+ ((LEVEL) == TIM_LOCKLEVEL_1) || \
+ ((LEVEL) == TIM_LOCKLEVEL_2) || \
+ ((LEVEL) == TIM_LOCKLEVEL_3))
+/**
+ * @}
+ */
+/** @defgroup TIMEx_Break_Input_enable_disable
+ * @{
+ */
+#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
+#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
+
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
+ ((STATE) == TIM_BREAK_DISABLE))
+/**
+ * @}
+ */
+/** @defgroup TIMEx_Break_Polarity
+ * @{
+ */
+#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
+#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
+
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
+ ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
+/**
+ * @}
+ */
+/** @defgroup TIMEx_AOE_Bit_Set_Reset
+ * @{
+ */
+#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
+#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+ ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Master_Mode_Selection
+ * @{
+ */
+#define TIM_TRGO_RESET ((uint32_t)0x0000)
+#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
+#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
+#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
+#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
+#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
+#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
+#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
+
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
+ ((SOURCE) == TIM_TRGO_ENABLE) || \
+ ((SOURCE) == TIM_TRGO_UPDATE) || \
+ ((SOURCE) == TIM_TRGO_OC1) || \
+ ((SOURCE) == TIM_TRGO_OC1REF) || \
+ ((SOURCE) == TIM_TRGO_OC2REF) || \
+ ((SOURCE) == TIM_TRGO_OC3REF) || \
+ ((SOURCE) == TIM_TRGO_OC4REF))
+
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Master_Slave_Mode
+ * @{
+ */
+
+#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
+#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
+ ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Commutation_Mode
+ * @{
+ */
+#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
+#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Remap
+ * @{
+ */
+
+#define TIM_TIM2_TIM8_TRGO (0x00000000)
+#define TIM_TIM2_ETH_PTP (0x00000400)
+#define TIM_TIM2_USBFS_SOF (0x00000800)
+#define TIM_TIM2_USBHS_SOF (0x00000C00)
+#define TIM_TIM5_GPIO (0x00000000)
+#define TIM_TIM5_LSI (0x00000040)
+#define TIM_TIM5_LSE (0x00000080)
+#define TIM_TIM5_RTC (0x000000C0)
+#define TIM_TIM11_GPIO (0x00000000)
+#define TIM_TIM11_HSE (0x00000002)
+
+#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
+ ((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
+ ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
+ ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
+ ((TIM_REMAP) == TIM_TIM5_GPIO)||\
+ ((TIM_REMAP) == TIM_TIM5_LSI)||\
+ ((TIM_REMAP) == TIM_TIM5_LSE)||\
+ ((TIM_REMAP) == TIM_TIM5_RTC)||\
+ ((TIM_REMAP) == TIM_TIM11_GPIO)||\
+ ((TIM_REMAP) == TIM_TIM11_HSE))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Timer Hall Sensor functions **********************************************/
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef* htim, TIM_HallSensor_InitTypeDef* sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef* htim);
+
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef* htim);
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef* htim);
+
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef* htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef* htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef* htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef* htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef* htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef* htim);
+
+/* Timer Complementary Output Compare functions *****************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
+
+/* Timer Complementary PWM functions ****************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
+
+/* Timer Complementary One Pulse functions **********************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
+
+/* Extnsion Control functions ************************************************/
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef* htim, TIM_MasterConfigTypeDef * sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef* htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef* htim, uint32_t Remap);
+
+/* Extension Callback *********************************************************/
+void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef* htim);
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef* htim);
+void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+
+/* Extension Peripheral State functions **************************************/
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_TIM_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_uart.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,493 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_uart.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of UART HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_UART_H
+#define __STM32F4xx_HAL_UART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup UART
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief UART Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
+ The baud rate is computed using the following formula:
+ - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (huart->Init.BaudRate)))
+ - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5
+ Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref UART_Word_Length */
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref UART_Stop_Bits */
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref UART_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref UART_Mode */
+
+ uint32_t HwFlowCtl; /*!< Specifies wether the hardware flow control mode is enabled
+ or disabled.
+ This parameter can be a value of @ref UART_Hardware_Flow_Control */
+
+ uint32_t OverSampling; /*!< Specifies wether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
+ This parameter can be a value of @ref UART_Over_Sampling */
+}UART_InitTypeDef;
+
+/**
+ * @brief HAL UART State structures definition
+ */
+typedef enum
+{
+ HAL_UART_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */
+ HAL_UART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_UART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_UART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_UART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_UART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
+ HAL_UART_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_UART_STATE_ERROR = 0x04 /*!< Error */
+}HAL_UART_StateTypeDef;
+
+/**
+ * @brief HAL UART Error Code structure definition
+ */
+typedef enum
+{
+ HAL_UART_ERROR_NONE = 0x00, /*!< No error */
+ HAL_UART_ERROR_PE = 0x01, /*!< Parity error */
+ HAL_UART_ERROR_NE = 0x02, /*!< Noise error */
+ HAL_UART_ERROR_FE = 0x04, /*!< frame error */
+ HAL_UART_ERROR_ORE = 0x08, /*!< Overrun error */
+ HAL_UART_ERROR_DMA = 0x10 /*!< DMA transfer error */
+}HAL_UART_ErrorTypeDef;
+
+/**
+ * @brief UART handle Structure definition
+ */
+typedef struct
+{
+ USART_TypeDef *Instance; /* UART registers base address */
+
+ UART_InitTypeDef Init; /* UART communication parameters */
+
+ uint8_t *pTxBuffPtr; /* Pointer to UART Tx transfer Buffer */
+
+ uint16_t TxXferSize; /* UART Tx Transfer size */
+
+ uint16_t TxXferCount; /* UART Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /* Pointer to UART Rx transfer Buffer */
+
+ uint16_t RxXferSize; /* UART Rx Transfer size */
+
+ uint16_t RxXferCount; /* UART Rx Transfer Counter */
+
+ DMA_HandleTypeDef *hdmatx; /* UART Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /* UART Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /* Locking object */
+
+ __IO HAL_UART_StateTypeDef State; /* UART communication state */
+
+ __IO HAL_UART_ErrorTypeDef ErrorCode; /* UART Error code */
+
+}UART_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UART_Exported_Constants
+ * @{
+ */
+
+/** @defgroup UART_Word_Length
+ * @{
+ */
+#define UART_WORDLENGTH_8B ((uint32_t)0x00000000)
+#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
+#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
+ ((LENGTH) == UART_WORDLENGTH_9B))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Stop_Bits
+ * @{
+ */
+#define UART_STOPBITS_1 ((uint32_t)0x00000000)
+#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
+#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
+ ((STOPBITS) == UART_STOPBITS_2))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Parity
+ * @{
+ */
+#define UART_PARITY_NONE ((uint32_t)0x00000000)
+#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
+#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
+ ((PARITY) == UART_PARITY_EVEN) || \
+ ((PARITY) == UART_PARITY_ODD))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Hardware_Flow_Control
+ * @{
+ */
+#define UART_HWCONTROL_NONE ((uint32_t)0x00000000)
+#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
+#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
+#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
+#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
+ (((CONTROL) == UART_HWCONTROL_NONE) || \
+ ((CONTROL) == UART_HWCONTROL_RTS) || \
+ ((CONTROL) == UART_HWCONTROL_CTS) || \
+ ((CONTROL) == UART_HWCONTROL_RTS_CTS))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Mode
+ * @{
+ */
+#define UART_MODE_RX ((uint32_t)USART_CR1_RE)
+#define UART_MODE_TX ((uint32_t)USART_CR1_TE)
+#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+#define IS_UART_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
+/**
+ * @}
+ */
+
+ /** @defgroup UART_State
+ * @{
+ */
+#define UART_STATE_DISABLE ((uint32_t)0x00000000)
+#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)
+#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
+ ((STATE) == UART_STATE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Over_Sampling
+ * @{
+ */
+#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000)
+#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
+#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
+ ((SAMPLING) == UART_OVERSAMPLING_8))
+/**
+ * @}
+ */
+
+/** @defgroup UART_LIN_Break_Detection_Length
+ * @{
+ */
+#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000)
+#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)0x00000020)
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
+ ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
+/**
+ * @}
+ */
+
+/** @defgroup UART_WakeUp_functions
+ * @{
+ */
+#define UART_WAKEUPMETHODE_IDLELINE ((uint32_t)0x00000000)
+#define UART_WAKEUPMETHODE_ADDRESSMARK ((uint32_t)0x00000800)
+#define IS_UART_WAKEUPMETHODE(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHODE_IDLELINE) || \
+ ((WAKEUP) == UART_WAKEUPMETHODE_ADDRESSMARK))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the SR register
+ * @{
+ */
+#define UART_FLAG_CTS ((uint32_t)0x00000200)
+#define UART_FLAG_LBD ((uint32_t)0x00000100)
+#define UART_FLAG_TXE ((uint32_t)0x00000080)
+#define UART_FLAG_TC ((uint32_t)0x00000040)
+#define UART_FLAG_RXNE ((uint32_t)0x00000020)
+#define UART_FLAG_IDLE ((uint32_t)0x00000010)
+#define UART_FLAG_ORE ((uint32_t)0x00000008)
+#define UART_FLAG_NE ((uint32_t)0x00000004)
+#define UART_FLAG_FE ((uint32_t)0x00000002)
+#define UART_FLAG_PE ((uint32_t)0x00000001)
+/**
+ * @}
+ */
+
+/** @defgroup UART_Interrupt_definition
+ * Elements values convention: 0xY000XXXX
+ * - XXXX : Interrupt mask in the XX register
+ * - Y : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ *
+ * @{
+ */
+#define UART_IT_PE ((uint32_t)0x10000100)
+#define UART_IT_TXE ((uint32_t)0x10000080)
+#define UART_IT_TC ((uint32_t)0x10000040)
+#define UART_IT_RXNE ((uint32_t)0x10000020)
+#define UART_IT_IDLE ((uint32_t)0x10000010)
+
+#define UART_IT_LBD ((uint32_t)0x20000040)
+#define UART_IT_CTS ((uint32_t)0x30000400)
+
+#define UART_IT_ERR ((uint32_t)0x30000001)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset UART handle state
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @retval None
+ */
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET)
+
+/** @brief Flushs the UART DR register
+ * @param __HANDLE__: specifies the UART Handle.
+ */
+#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
+
+/** @brief Checks whether the specified UART flag is set or not.
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
+ * @arg UART_FLAG_LBD: LIN Break detection flag
+ * @arg UART_FLAG_TXE: Transmit data register empty flag
+ * @arg UART_FLAG_TC: Transmission Complete flag
+ * @arg UART_FLAG_RXNE: Receive data register not empty flag
+ * @arg UART_FLAG_IDLE: Idle Line detection flag
+ * @arg UART_FLAG_ORE: OverRun Error flag
+ * @arg UART_FLAG_NE: Noise Error flag
+ * @arg UART_FLAG_FE: Framing Error flag
+ * @arg UART_FLAG_PE: Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+
+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the specified UART pending flag.
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
+ * @arg UART_FLAG_LBD: LIN Break detection flag.
+ * @arg UART_FLAG_TC: Transmission Complete flag.
+ * @arg UART_FLAG_RXNE: Receive data register not empty flag.
+ *
+ * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * error) and IDLE (Idle line detected) flags are cleared by software
+ * sequence: a read operation to USART_SR register followed by a read
+ * operation to USART_DR register.
+ * @note RXNE flag can be also cleared by a read to the USART_DR register.
+ * @note TC flag can be also cleared by software sequence: a read operation to
+ * USART_SR register followed by a write operation to USART_DR register.
+ * @note TXE flag is cleared only by a write to the USART_DR register.
+ *
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
+
+/** @brief Enables or disables the specified UART interrupt.
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __INTERRUPT__: specifies the UART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg UART_IT_CTS: CTS change interrupt
+ * @arg UART_IT_LBD: LIN Break detection interrupt
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg UART_IT_TC: Transmission complete interrupt
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg UART_IT_IDLE: Idle line detection interrupt
+ * @arg UART_IT_PE: Parity Error interrupt
+ * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @param NewState: new state of the specified UART interrupt.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+#define UART_IT_MASK ((uint32_t)0x0000FFFF)
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
+
+/** @brief Checks whether the specified UART interrupt has occurred or not.
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
+ * UART peripheral.
+ * @param __IT__: specifies the UART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
+ * @arg UART_IT_LBD: LIN Break detection interrupt
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg UART_IT_TC: Transmission complete interrupt
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg UART_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_ERR: Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))
+
+/** @brief macros to enables or disables the UART's one bit sampling method
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_ONEBIT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+#define __HAL_UART_ONEBIT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
+
+#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+#define __DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
+#define __DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (__DIV_SAMPLING16((_PCLK_), (_BAUD_))/100)
+#define __DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((__DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (__DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define __UART_BRR_SAMPLING16(_PCLK_, _BAUD_) ((__DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0F))
+
+#define __DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25)/(2*(_BAUD_)))
+#define __DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (__DIV_SAMPLING8((_PCLK_), (_BAUD_))/100)
+#define __DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((__DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (__DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define __UART_BRR_SAMPLING8(_PCLK_, _BAUD_) ((__DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x0F))
+
+#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001)
+#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethode);
+HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
+void HAL_UART_MspInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
+
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
+
+/* Peripheral State functions **************************************************/
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_UART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_usart.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,456 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_usart.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of USART HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_USART_H
+#define __STM32F4xx_HAL_USART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup USART
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/**
+ * @brief USART Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
+ The baud rate is computed using the following formula:
+ - IntegerDivider = ((PCLKx) / (8 * (husart->Init.BaudRate)))
+ - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref USART_Word_Length */
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref USART_Stop_Bits */
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref USART_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref USART_Mode */
+
+ uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
+ This parameter can be a value of @ref USART_Clock_Polarity */
+
+ uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref USART_Clock_Phase */
+
+ uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref USART_Last_Bit */
+}USART_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_USART_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */
+ HAL_USART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_USART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_USART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_USART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_USART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission Reception process is ongoing */
+ HAL_USART_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_USART_STATE_ERROR = 0x04 /*!< Error */
+}HAL_USART_StateTypeDef;
+
+/**
+ * @brief HAL USART Error Code structure definition
+ */
+typedef enum
+{
+ HAL_USART_ERROR_NONE = 0x00, /*!< No error */
+ HAL_USART_ERROR_PE = 0x01, /*!< Parity error */
+ HAL_USART_ERROR_NE = 0x02, /*!< Noise error */
+ HAL_USART_ERROR_FE = 0x04, /*!< frame error */
+ HAL_USART_ERROR_ORE = 0x08, /*!< Overrun error */
+ HAL_USART_ERROR_DMA = 0x10 /*!< DMA transfer error */
+}HAL_USART_ErrorTypeDef;
+
+/**
+ * @brief USART handle Structure definition
+ */
+typedef struct
+{
+ USART_TypeDef *Instance; /* USART registers base address */
+
+ USART_InitTypeDef Init; /* Usart communication parameters */
+
+ uint8_t *pTxBuffPtr; /* Pointer to Usart Tx transfer Buffer */
+
+ uint16_t TxXferSize; /* Usart Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /* Usart Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /* Pointer to Usart Rx transfer Buffer */
+
+ uint16_t RxXferSize; /* Usart Rx Transfer size */
+
+ __IO uint16_t RxXferCount; /* Usart Rx Transfer Counter */
+
+ DMA_HandleTypeDef *hdmatx; /* Usart Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /* Usart Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /* Locking object */
+
+ __IO HAL_USART_StateTypeDef State; /* Usart communication state */
+
+ __IO HAL_USART_ErrorTypeDef ErrorCode; /* USART Error code */
+
+}USART_HandleTypeDef;
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_Exported_Constants
+ * @{
+ */
+
+/** @defgroup USART_Word_Length
+ * @{
+ */
+#define USART_WORDLENGTH_8B ((uint32_t)0x00000000)
+#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \
+ ((LENGTH) == USART_WORDLENGTH_9B))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Stop_Bits
+ * @{
+ */
+#define USART_STOPBITS_1 ((uint32_t)0x00000000)
+#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
+#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
+#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \
+ ((STOPBITS) == USART_STOPBITS_0_5) || \
+ ((STOPBITS) == USART_STOPBITS_1_5) || \
+ ((STOPBITS) == USART_STOPBITS_2))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Parity
+ * @{
+ */
+#define USART_PARITY_NONE ((uint32_t)0x00000000)
+#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
+#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
+ ((PARITY) == USART_PARITY_EVEN) || \
+ ((PARITY) == USART_PARITY_ODD))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Mode
+ * @{
+ */
+#define USART_MODE_RX ((uint32_t)USART_CR1_RE)
+#define USART_MODE_TX ((uint32_t)USART_CR1_TE)
+#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFF3) == 0x00) && ((MODE) != (uint32_t)0x00))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock
+ * @{
+ */
+#define USART_CLOCK_DISABLED ((uint32_t)0x00000000)
+#define USART_CLOCK_ENABLED ((uint32_t)USART_CR2_CLKEN)
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLED) || \
+ ((CLOCK) == USART_CLOCK_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock_Polarity
+ * @{
+ */
+#define USART_POLARITY_LOW ((uint32_t)0x00000000)
+#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
+#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock_Phase
+ * @{
+ */
+#define USART_PHASE_1EDGE ((uint32_t)0x00000000)
+#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
+#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Last_Bit
+ * @{
+ */
+#define USART_LASTBIT_DISABLE ((uint32_t)0x00000000)
+#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \
+ ((LASTBIT) == USART_LASTBIT_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup USART_NACK_State
+ * @{
+ */
+#define USARTNACK_ENABLED ((uint32_t)USART_CR3_NACK)
+#define USARTNACK_DISABLED ((uint32_t)0x00000000)
+#define IS_USART_NACK_STATE(NACK) (((NACK) == USARTNACK_ENABLED) || \
+ ((NACK) == USARTNACK_DISABLED))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the SR register
+ * @{
+ */
+
+#define USART_FLAG_TXE ((uint32_t)0x00000080)
+#define USART_FLAG_TC ((uint32_t)0x00000040)
+#define USART_FLAG_RXNE ((uint32_t)0x00000020)
+#define USART_FLAG_IDLE ((uint32_t)0x00000010)
+#define USART_FLAG_ORE ((uint32_t)0x00000008)
+#define USART_FLAG_NE ((uint32_t)0x00000004)
+#define USART_FLAG_FE ((uint32_t)0x00000002)
+#define USART_FLAG_PE ((uint32_t)0x00000001)
+/**
+ * @}
+ */
+
+/** @defgroup USART_Interrupt_definition
+ * Elements values convention: 0xY000XXXX
+ * - XXXX : Interrupt mask in the XX register
+ * - Y : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ *
+ * @{
+ */
+#define USART_IT_PE ((uint32_t)0x10000100)
+#define USART_IT_TXE ((uint32_t)0x10000080)
+#define USART_IT_TC ((uint32_t)0x10000040)
+#define USART_IT_RXNE ((uint32_t)0x10000020)
+#define USART_IT_IDLE ((uint32_t)0x10000010)
+
+#define USART_IT_LBD ((uint32_t)0x20000040)
+#define USART_IT_CTS ((uint32_t)0x30000400)
+
+#define USART_IT_ERR ((uint32_t)0x30000001)
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @brief Reset USART handle state
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * @retval None
+ */
+#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
+
+/** @brief Checks whether the specified Smartcard flag is set or not.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg USART_FLAG_TXE: Transmit data register empty flag
+ * @arg USART_FLAG_TC: Transmission Complete flag
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag
+ * @arg USART_FLAG_IDLE: Idle Line detection flag
+ * @arg USART_FLAG_ORE: OverRun Error flag
+ * @arg USART_FLAG_NE: Noise Error flag
+ * @arg USART_FLAG_FE: Framing Error flag
+ * @arg USART_FLAG_PE: Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+
+#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the specified Smartcard pending flags.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg USART_FLAG_TC: Transmission Complete flag.
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag.
+ *
+ * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * error) and IDLE (Idle line detected) flags are cleared by software
+ * sequence: a read operation to USART_SR register followed by a read
+ * operation to USART_DR register.
+ * @note RXNE flag can be also cleared by a read to the USART_DR register.
+ * @note TC flag can be also cleared by software sequence: a read operation to
+ * USART_SR register followed by a write operation to USART_DR register.
+ * @note TXE flag is cleared only by a write to the USART_DR register.
+ *
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
+
+
+/** @brief Enables or disables the specified Usart interrupts.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * @param __INTERRUPT__: specifies the USART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg USART_IT_TC: Transmission complete interrupt
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg USART_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_PE: Parity Error interrupt
+ * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @param NewState: new state of the specified Usart interrupt.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+#define USART_IT_MASK ((uint32_t)0x0000FFFF)
+#define __USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))
+#define __USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
+
+
+/** @brief Checks whether the specified Usart interrupt has occurred or not.
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * @param __IT__: specifies the USART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg USART_IT_TC: Transmission complete interrupt
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg USART_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_ERR: Error interrupt
+ * @arg USART_IT_PE: Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK))
+
+#define __USART_ENABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+#define __USART_DISABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+#define __DIV(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
+#define __DIVMANT(_PCLK_, _BAUD_) (__DIV((_PCLK_), (_BAUD_))/100)
+#define __DIVFRAQ(_PCLK_, _BAUD_) (((__DIV((_PCLK_), (_BAUD_)) - (__DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
+#define __USART_BRR(_PCLK_, _BAUD_) ((__DIVMANT((_PCLK_), (_BAUD_)) << 4)|(__DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
+
+#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001)
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
+void HAL_USART_MspInit(USART_HandleTypeDef *husart);
+void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
+void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
+
+/* Peripheral State functions **************************************************/
+HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
+uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_USART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_wwdg.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,249 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_wwdg.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of WWDG HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_WWDG_H
+#define __STM32F4xx_HAL_WWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup WWDG
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief WWDG HAL State Structure definition
+ */
+typedef enum
+{
+ HAL_WWDG_STATE_RESET = 0x00, /*!< WWDG not yet initialized or disabled */
+ HAL_WWDG_STATE_READY = 0x01, /*!< WWDG initialized and ready for use */
+ HAL_WWDG_STATE_BUSY = 0x02, /*!< WWDG internal process is ongoing */
+ HAL_WWDG_STATE_TIMEOUT = 0x03, /*!< WWDG timeout state */
+ HAL_WWDG_STATE_ERROR = 0x04 /*!< WWDG error state */
+
+}HAL_WWDG_StateTypeDef;
+
+/**
+ * @brief WWDG Init structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Specifies the prescaler.
+ This parameter can be a value of @ref WWDG_Prescaler */
+
+ uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter.
+ This parameter must be a number lower than Max_Data = 0x80 */
+
+ uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
+ This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
+
+}WWDG_InitTypeDef;
+
+/**
+ * @brief WWDG handle Structure definition
+ */
+typedef struct
+{
+ WWDG_TypeDef *Instance; /*!< Register base address */
+
+ WWDG_InitTypeDef Init; /*!< WWDG required parameters */
+
+ HAL_LockTypeDef Lock; /*!< WWDG locking object */
+
+ __IO HAL_WWDG_StateTypeDef State; /*!< WWDG communication state */
+
+}WWDG_HandleTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup WWDG_BitAddress_AliasRegion
+ * @{
+ */
+
+/* --- CFR Register ---*/
+/* Alias word address of EWI bit */
+#define CFR_BASE (uint32_t)(WWDG_BASE + 0x04)
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Interrupt_definition
+ * @{
+ */
+#define WWDG_IT_EWI ((uint32_t)WWDG_CFR_EWI)
+
+#define IS_WWDG_IT(IT) ((IT) == WWDG_IT_EWI)
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Flag_definition
+ * @brief WWDG Flag definition
+ * @{
+ */
+#define WWDG_FLAG_EWIF ((uint32_t)0x0001) /*!< Early wakeup interrupt flag */
+
+#define IS_WWDG_FLAG(FLAG) ((FLAG) == WWDG_FLAG_EWIF))
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Prescaler
+ * @{
+ */
+#define WWDG_PRESCALER_1 ((uint32_t)0x00000000) /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define WWDG_PRESCALER_2 ((uint32_t)0x00000080) /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define WWDG_PRESCALER_4 ((uint32_t)0x00000100) /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define WWDG_PRESCALER_8 ((uint32_t)0x00000180) /*!< WWDG counter clock = (PCLK1/4096)/8 */
+
+#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_PRESCALER_1) || \
+ ((PRESCALER) == WWDG_PRESCALER_2) || \
+ ((PRESCALER) == WWDG_PRESCALER_4) || \
+ ((PRESCALER) == WWDG_PRESCALER_8))
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Window
+ * @{
+ */
+#define IS_WWDG_WINDOW(WINDOW) ((WINDOW) <= 0x7F)
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Counter
+ * @{
+ */
+#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset WWDG handle state
+ * @param __HANDLE__: WWDG handle
+ * @retval None
+ */
+#define __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET)
+
+/**
+ * @brief Enables the WWDG peripheral.
+ * @param __HANDLE__: WWDG handle
+ * @retval None
+ */
+#define __HAL_WWDG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= WWDG_CR_WDGA)
+
+/**
+ * @brief Gets the selected WWDG's flag status.
+ * @param __HANDLE__: WWDG handle
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+ * @retval The new state of WWDG_FLAG (SET or RESET).
+ */
+#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clears the WWDG's pending flags.
+ * @param __HANDLE__: WWDG handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+ * @retval None
+ */
+#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) &= ~(__FLAG__))
+
+/**
+ * @brief Enables the WWDG early wakeup interrupt.
+ * @note Once enabled this interrupt cannot be disabled except by a system reset.
+ * @retval None
+ */
+#define __HAL_WWDG_ENABLE_IT(__INTERRUPT__) (*(__IO uint32_t *) CFR_BASE |= (__INTERRUPT__))
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
+HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg);
+void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
+void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg);
+void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg);
+
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg);
+HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg);
+HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter);
+void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
+
+/* Peripheral State functions **************************************************/
+HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_WWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_ll_fmc.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,1379 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_fmc.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of FMC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_FMC_H
+#define __STM32F4xx_LL_FMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FMC
+ * @{
+ */
+
+/* Exported typedef ----------------------------------------------------------*/
+#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
+#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
+#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
+#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
+#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
+
+#define FMC_NORSRAM_DEVICE FMC_Bank1
+#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
+#define FMC_NAND_DEVICE FMC_Bank2_3
+#define FMC_PCCARD_DEVICE FMC_Bank4
+#define FMC_SDRAM_DEVICE FMC_Bank5_6
+
+/**
+ * @brief FMC_NORSRAM Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
+ This parameter can be a value of @ref FMC_NORSRAM_Bank */
+
+ uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
+ multiplexed on the data bus or not.
+ This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
+
+ uint32_t MemoryType; /*!< Specifies the type of external memory attached to
+ the corresponding memory device.
+ This parameter can be a value of @ref FMC_Memory_Type */
+
+ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
+ This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
+
+ uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
+ valid only with synchronous burst Flash memories.
+ This parameter can be a value of @ref FMC_Burst_Access_Mode */
+
+ uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
+ the Flash memory in burst mode.
+ This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
+
+ uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
+ memory, valid only when accessing Flash memories in burst mode.
+ This parameter can be a value of @ref FMC_Wrap_Mode */
+
+ uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
+ clock cycle before the wait state or during the wait state,
+ valid only when accessing memories in burst mode.
+ This parameter can be a value of @ref FMC_Wait_Timing */
+
+ uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
+ This parameter can be a value of @ref FMC_Write_Operation */
+
+ uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
+ signal, valid for Flash memory access in burst mode.
+ This parameter can be a value of @ref FMC_Wait_Signal */
+
+ uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
+ This parameter can be a value of @ref FMC_Extended_Mode */
+
+ uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
+ valid only with asynchronous Flash memories.
+ This parameter can be a value of @ref FMC_AsynchronousWait */
+
+ uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
+ This parameter can be a value of @ref FMC_Write_Burst */
+
+ uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
+ This parameter is only enabled through the FMC_BCR1 register, and don't care
+ through FMC_BCR2..4 registers.
+ This parameter can be a value of @ref FMC_Continous_Clock */
+
+}FMC_NORSRAM_InitTypeDef;
+
+/**
+ * @brief FMC_NORSRAM Timing parameters structure definition
+ */
+typedef struct
+{
+ uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address setup time.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+ @note This parameter is not used with synchronous NOR Flash memories. */
+
+ uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address hold time.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 15.
+ @note This parameter is not used with synchronous NOR Flash memories. */
+
+ uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the data setup time.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 255.
+ @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
+ NOR Flash memories. */
+
+ uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
+ the duration of the bus turnaround.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+ @note This parameter is only used for multiplexed NOR Flash memories. */
+
+ uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
+ HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
+ @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
+ accesses. */
+
+ uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
+ to the memory before getting the first data.
+ The parameter value depends on the memory type as shown below:
+ - It must be set to 0 in case of a CRAM
+ - It is don't care in asynchronous NOR, SRAM or ROM accesses
+ - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
+ with synchronous burst mode enable */
+
+ uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
+ This parameter can be a value of @ref FMC_Access_Mode */
+}FMC_NORSRAM_TimingTypeDef;
+
+/**
+ * @brief FMC_NAND Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
+ This parameter can be a value of @ref FMC_NAND_Bank */
+
+ uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
+ This parameter can be any value of @ref FMC_Wait_feature */
+
+ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
+ This parameter can be any value of @ref FMC_NAND_Data_Width */
+
+ uint32_t EccComputation; /*!< Enables or disables the ECC computation.
+ This parameter can be any value of @ref FMC_ECC */
+
+ uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
+ This parameter can be any value of @ref FMC_ECC_Page_Size */
+
+ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between CLE low and RE low.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between ALE low and RE low.
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+}FMC_NAND_InitTypeDef;
+
+/**
+ * @brief FMC_NAND_PCCARD Timing parameters structure definition
+ */
+typedef struct
+{
+ uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
+ the command assertion for NAND-Flash read or write access
+ to common/Attribute or I/O memory space (depending on
+ the memory space timing to be configured).
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
+ command for NAND-Flash read or write access to
+ common/Attribute or I/O memory space (depending on the
+ memory space timing to be configured).
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
+ (and data for write access) after the command de-assertion
+ for NAND-Flash read or write access to common/Attribute
+ or I/O memory space (depending on the memory space timing
+ to be configured).
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
+ data bus is kept in HiZ after the start of a NAND-Flash
+ write access to common/Attribute or I/O memory space (depending
+ on the memory space timing to be configured).
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+}FMC_NAND_PCC_TimingTypeDef;
+
+/**
+ * @brief FMC_NAND Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
+ This parameter can be any value of @ref FMC_Wait_feature */
+
+ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between CLE low and RE low.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between ALE low and RE low.
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+}FMC_PCCARD_InitTypeDef;
+
+/**
+ * @brief FMC_SDRAM Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
+ This parameter can be a value of @ref FMC_SDRAM_Bank */
+
+ uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
+ This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
+
+ uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
+ This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
+
+ uint32_t MemoryDataWidth; /*!< Defines the memory device width.
+ This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
+
+ uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
+ This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
+
+ uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
+ This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
+
+ uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
+ This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
+
+ uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
+ to disable the clock before changing frequency.
+ This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
+
+ uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
+ commands during the CAS latency and stores data in the Read FIFO.
+ This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
+
+ uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
+ This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
+}FMC_SDRAM_InitTypeDef;
+
+/**
+ * @brief FMC_SDRAM Timing parameters structure definition
+ */
+typedef struct
+{
+ uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
+ an active or Refresh command in number of memory clock cycles.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
+
+ uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
+ issuing the Activate command in number of memory clock cycles.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
+
+ uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
+ cycles.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
+
+ uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
+ and the delay between two consecutive Refresh commands in number of
+ memory clock cycles.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
+
+ uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
+
+ uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
+ in number of memory clock cycles.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
+
+ uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
+ command in number of memory clock cycles.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
+}FMC_SDRAM_TimingTypeDef;
+
+/**
+ * @brief SDRAM command parameters structure definition
+ */
+typedef struct
+{
+ uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
+ This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
+
+ uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
+ This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
+
+ uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
+ in auto refresh mode.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
+ uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */
+}FMC_SDRAM_CommandTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FMC_NOR_SRAM_Controller
+ * @{
+ */
+
+/** @defgroup FMC_NORSRAM_Bank
+ * @{
+ */
+#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
+#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
+#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
+#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
+
+#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \
+ ((BANK) == FMC_NORSRAM_BANK2) || \
+ ((BANK) == FMC_NORSRAM_BANK3) || \
+ ((BANK) == FMC_NORSRAM_BANK4))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Data_Address_Bus_Multiplexing
+ * @{
+ */
+#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
+#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
+
+#define IS_FMC_MUX(MUX) (((MUX) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
+ ((MUX) == FMC_DATA_ADDRESS_MUX_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Memory_Type
+ * @{
+ */
+#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
+#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
+#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
+
+#define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MEMORY_TYPE_SRAM) || \
+ ((MEMORY) == FMC_MEMORY_TYPE_PSRAM)|| \
+ ((MEMORY) == FMC_MEMORY_TYPE_NOR))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NORSRAM_Data_Width
+ * @{
+ */
+#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
+
+#define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
+ ((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
+ ((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NORSRAM_Flash_Access
+ * @{
+ */
+#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
+#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Burst_Access_Mode
+ * @{
+ */
+#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
+#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
+
+#define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BURST_ACCESS_MODE_DISABLE) || \
+ ((STATE) == FMC_BURST_ACCESS_MODE_ENABLE))
+/**
+ * @}
+ */
+
+
+/** @defgroup FMC_Wait_Signal_Polarity
+ * @{
+ */
+#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
+#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
+
+#define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
+ ((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wrap_Mode
+ * @{
+ */
+#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
+#define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
+
+#define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WRAP_MODE_DISABLE) || \
+ ((MODE) == FMC_WRAP_MODE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wait_Timing
+ * @{
+ */
+#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
+#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
+
+#define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WAIT_TIMING_BEFORE_WS) || \
+ ((ACTIVE) == FMC_WAIT_TIMING_DURING_WS))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Write_Operation
+ * @{
+ */
+#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
+#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
+
+#define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WRITE_OPERATION_DISABLE) || \
+ ((OPERATION) == FMC_WRITE_OPERATION_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wait_Signal
+ * @{
+ */
+#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
+#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
+
+#define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WAIT_SIGNAL_DISABLE) || \
+ ((SIGNAL) == FMC_WAIT_SIGNAL_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Extended_Mode
+ * @{
+ */
+#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
+#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
+
+#define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_EXTENDED_MODE_DISABLE) || \
+ ((MODE) == FMC_EXTENDED_MODE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_AsynchronousWait
+ * @{
+ */
+#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
+#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
+
+#define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
+ ((STATE) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Write_Burst
+ * @{
+ */
+#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
+#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
+
+#define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WRITE_BURST_DISABLE) || \
+ ((BURST) == FMC_WRITE_BURST_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Continous_Clock
+ * @{
+ */
+#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
+#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
+
+#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
+ ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Address_Setup_Time
+ * @{
+ */
+#define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Address_Hold_Time
+ * @{
+ */
+#define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Data_Setup_Time
+ * @{
+ */
+#define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Bus_Turn_around_Duration
+ * @{
+ */
+#define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_CLK_Division
+ * @{
+ */
+#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Data_Latency
+ * @{
+ */
+#define IS_FMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Access_Mode
+ * @{
+ */
+#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
+#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
+#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
+#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
+
+#define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_ACCESS_MODE_A) || \
+ ((MODE) == FMC_ACCESS_MODE_B) || \
+ ((MODE) == FMC_ACCESS_MODE_C) || \
+ ((MODE) == FMC_ACCESS_MODE_D))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NAND_Controller
+ * @{
+ */
+
+/** @defgroup FMC_NAND_Bank
+ * @{
+ */
+#define FMC_NAND_BANK2 ((uint32_t)0x00000010)
+#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
+
+#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) || \
+ ((BANK) == FMC_NAND_BANK3))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wait_feature
+ * @{
+ */
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
+
+#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
+ ((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_PCR_Memory_Type
+ * @{
+ */
+#define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
+#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NAND_Data_Width
+ * @{
+ */
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
+
+#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
+ ((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_ECC
+ * @{
+ */
+#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
+#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
+
+#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \
+ ((STATE) == FMC_NAND_ECC_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_ECC_Page_Size
+ * @{
+ */
+#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
+#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
+#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
+#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
+#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
+#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
+
+#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
+ ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
+ ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
+ ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
+ ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
+ ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_TCLR_Setup_Time
+ * @{
+ */
+#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_TAR_Setup_Time
+ * @{
+ */
+#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Setup_Time
+ * @{
+ */
+#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wait_Setup_Time
+ * @{
+ */
+#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Hold_Setup_Time
+ * @{
+ */
+#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_HiZ_Setup_Time
+ * @{
+ */
+#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Controller
+ * @{
+ */
+
+/** @defgroup FMC_SDRAM_Bank
+ * @{
+ */
+#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
+#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
+
+#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \
+ ((BANK) == FMC_SDRAM_BANK2))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Column_Bits_number
+ * @{
+ */
+#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
+#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
+#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
+#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
+
+#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \
+ ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
+ ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
+ ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Row_Bits_number
+ * @{
+ */
+#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
+#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
+#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
+
+#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \
+ ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \
+ ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Memory_Bus_Width
+ * @{
+ */
+#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
+#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
+#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
+
+#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
+ ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
+ ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Internal_Banks_Number
+ * @{
+ */
+#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
+#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
+
+#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
+ ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_CAS_Latency
+ * @{
+ */
+#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
+#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
+#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
+
+#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \
+ ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \
+ ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Write_Protection
+ * @{
+ */
+#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
+#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
+
+#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
+ ((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Clock_Period
+ * @{
+ */
+#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
+#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
+#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
+
+#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) || \
+ ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) || \
+ ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Read_Burst
+ * @{
+ */
+#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
+#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
+
+#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) || \
+ ((RBURST) == FMC_SDRAM_RBURST_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Read_Pipe_Delay
+ * @{
+ */
+#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
+#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
+#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
+
+#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) || \
+ ((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) || \
+ ((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_LoadToActive_Delay
+ * @{
+ */
+#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay
+ * @{
+ */
+#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_SelfRefresh_Time
+ * @{
+ */
+#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_RowCycle_Delay
+ * @{
+ */
+#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Write_Recovery_Time
+ * @{
+ */
+#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_RP_Delay
+ * @{
+ */
+#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_RCD_Delay
+ * @{
+ */
+#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Command_Mode
+ * @{
+ */
+#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
+#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
+#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
+#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
+#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
+#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
+#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
+
+#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) || \
+ ((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) || \
+ ((COMMAND) == FMC_SDRAM_CMD_PALL) || \
+ ((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
+ ((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) || \
+ ((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
+ ((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Command_Target
+ * @{
+ */
+#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
+#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
+#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
+
+#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) || \
+ ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) || \
+ ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_AutoRefresh_Number
+ * @{
+ */
+#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_ModeRegister_Definition
+ * @{
+ */
+#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Refresh_rate
+ * @{
+ */
+#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Mode_Status
+ * @{
+ */
+#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
+#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
+#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NORSRAM_Device_Instance
+ * @{
+ */
+#define IS_FMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_DEVICE)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance
+ * @{
+ */
+#define IS_FMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_EXTENDED_DEVICE)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NAND_Device_Instance
+ * @{
+ */
+#define IS_FMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FMC_NAND_DEVICE)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_PCCARD_Device_Instance
+ * @{
+ */
+#define IS_FMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FMC_PCCARD_DEVICE)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_SDRAM_Device_Instance
+ * @{
+ */
+#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Interrupt_definition
+ * @brief FMC Interrupt definition
+ * @{
+ */
+#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
+#define FMC_IT_LEVEL ((uint32_t)0x00000010)
+#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
+#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
+
+#define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
+
+#define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RISING_EDGE) || \
+ ((IT) == FMC_IT_LEVEL) || \
+ ((IT) == FMC_IT_FALLING_EDGE) || \
+ ((IT) == FMC_IT_REFRESH_ERROR))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Flag_definition
+ * @brief FMC Flag definition
+ * @{
+ */
+#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
+#define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
+#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
+#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
+#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
+#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
+#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
+
+#define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RISING_EDGE) || \
+ ((FLAG) == FMC_FLAG_LEVEL) || \
+ ((FLAG) == FMC_FLAG_FALLING_EDGE) || \
+ ((FLAG) == FMC_FLAG_FEMPT) || \
+ ((FLAG) == FMC_SDRAM_FLAG_REFRESH_IT) || \
+ ((FLAG) == FMC_SDRAM_FLAG_BUSY))
+
+#define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup FMC_NOR_Macros
+ * @brief macros to handle NOR device enable/disable and read/write operations
+ * @{
+ */
+
+/**
+ * @brief Enable the NORSRAM device access.
+ * @param __INSTANCE__: FMC_NORSRAM Instance
+ * @param __BANK__: FMC_NORSRAM Bank
+ * @retval None
+ */
+#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)
+
+/**
+ * @brief Disable the NORSRAM device access.
+ * @param __INSTANCE__: FMC_NORSRAM Instance
+ * @param __BANK__: FMC_NORSRAM Bank
+ * @retval None
+ */
+#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NAND_Macros
+ * @brief macros to handle NAND device enable/disable
+ * @{
+ */
+
+/**
+ * @brief Enable the NAND device access.
+ * @param __INSTANCE__: FMC_NAND Instance
+ * @param __BANK__: FMC_NAND Bank
+ * @retval None
+ */
+#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \
+ ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN))
+
+/**
+ * @brief Disable the NAND device access.
+ * @param __INSTANCE__: FMC_NAND Instance
+ * @param __BANK__: FMC_NAND Bank
+ * @retval None
+ */
+#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
+ ((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_PCCARD_Macros
+ * @brief macros to handle SRAM read/write operations
+ * @{
+ */
+
+/**
+ * @brief Enable the PCCARD device access.
+ * @param __INSTANCE__: FMC_PCCARD Instance
+ * @retval None
+ */
+#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN)
+
+/**
+ * @brief Disable the PCCARD device access.
+ * @param __INSTANCE__: FMC_PCCARD Instance
+ * @retval None
+ */
+#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Interrupt
+ * @brief macros to handle FMC interrupts
+ * @{
+ */
+
+/**
+ * @brief Enable the NAND device interrupt.
+ * @param __INSTANCE__: FMC_NAND instance
+ * @param __BANK__: FMC_NAND Bank
+ * @param __INTERRUPT__: FMC_NAND interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FMC_IT_LEVEL: Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
+ ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
+
+/**
+ * @brief Disable the NAND device interrupt.
+ * @param __INSTANCE__: FMC_NAND handle
+ * @param __BANK__: FMC_NAND Bank
+ * @param __INTERRUPT__: FMC_NAND interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FMC_IT_LEVEL: Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
+ ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
+
+/**
+ * @brief Get flag status of the NAND device.
+ * @param __INSTANCE__: FMC_NAND handle
+ * @param __BANK__: FMC_NAND Bank
+ * @param __FLAG__: FMC_NAND flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
+ (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
+/**
+ * @brief Clear flag status of the NAND device.
+ * @param __INSTANCE__: FMC_NAND handle
+ * @param __BANK__: FMC_NAND Bank
+ * @param __FLAG__: FMC_NAND flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval None
+ */
+#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
+ ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
+/**
+ * @brief Enable the PCCARD device interrupt.
+ * @param __INSTANCE__: FMC_PCCARD instance
+ * @param __INTERRUPT__: FMC_PCCARD interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FMC_IT_LEVEL: Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the PCCARD device interrupt.
+ * @param __INSTANCE__: FMC_PCCARD instance
+ * @param __INTERRUPT__: FMC_PCCARD interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FMC_IT_LEVEL: Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
+
+/**
+ * @brief Get flag status of the PCCARD device.
+ * @param __INSTANCE__: FMC_PCCARD instance
+ * @param __FLAG__: FMC_PCCARD flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear flag status of the PCCARD device.
+ * @param __INSTANCE__: FMC_PCCARD instance
+ * @param __FLAG__: FMC_PCCARD flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval None
+ */
+#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
+
+/**
+ * @brief Enable the SDRAM device interrupt.
+ * @param __INSTANCE__: FMC_SDRAM instance
+ * @param __INTERRUPT__: FMC_SDRAM interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
+ * @retval None
+ */
+#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the SDRAM device interrupt.
+ * @param __INSTANCE__: FMC_SDRAM instance
+ * @param __INTERRUPT__: FMC_SDRAM interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
+ * @retval None
+ */
+#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Get flag status of the SDRAM device.
+ * @param __INSTANCE__: FMC_SDRAM instance
+ * @param __FLAG__: FMC_SDRAM flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
+ * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
+ * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear flag status of the SDRAM device.
+ * @param __INSTANCE__: FMC_SDRAM instance
+ * @param __FLAG__: FMC_SDRAM flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_SDRAM_FLAG_REFRESH_ERROR
+ * @retval None
+ */
+#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__))
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* FMC_NORSRAM Controller functions *******************************************/
+/* Initialization/de-initialization functions */
+HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
+HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
+HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
+
+/* FMC_NORSRAM Control functions */
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+
+/* FMC_NAND Controller functions **********************************************/
+/* Initialization/de-initialization functions */
+HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
+HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
+
+/* FMC_NAND Control functions */
+HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
+
+/* FMC_PCCARD Controller functions ********************************************/
+/* Initialization/de-initialization functions */
+HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
+HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
+
+/* FMC_SDRAM Controller functions *********************************************/
+/* Initialization/de-initialization functions */
+HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
+HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
+
+/* FMC_SDRAM Control functions */
+HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
+HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
+HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
+uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_FMC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_ll_fsmc.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,1044 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_fsmc.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of FSMC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_FSMC_H
+#define __STM32F4xx_LL_FSMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FSMC
+ * @{
+ */
+
+/* Exported typedef ----------------------------------------------------------*/
+#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
+#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
+#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
+
+#define FSMC_NORSRAM_DEVICE FSMC_Bank1
+#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
+#define FSMC_NAND_DEVICE FSMC_Bank2_3
+#define FSMC_PCCARD_DEVICE FSMC_Bank4
+
+/**
+ * @brief FSMC_NORSRAM Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
+ This parameter can be a value of @ref FSMC_NORSRAM_Bank */
+
+ uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
+ multiplexed on the data bus or not.
+ This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
+
+ uint32_t MemoryType; /*!< Specifies the type of external memory attached to
+ the corresponding memory device.
+ This parameter can be a value of @ref FSMC_Memory_Type */
+
+ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
+ This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
+
+ uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
+ valid only with synchronous burst Flash memories.
+ This parameter can be a value of @ref FSMC_Burst_Access_Mode */
+
+ uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
+ the Flash memory in burst mode.
+ This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
+
+ uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
+ memory, valid only when accessing Flash memories in burst mode.
+ This parameter can be a value of @ref FSMC_Wrap_Mode */
+
+ uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
+ clock cycle before the wait state or during the wait state,
+ valid only when accessing memories in burst mode.
+ This parameter can be a value of @ref FSMC_Wait_Timing */
+
+ uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
+ This parameter can be a value of @ref FSMC_Write_Operation */
+
+ uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
+ signal, valid for Flash memory access in burst mode.
+ This parameter can be a value of @ref FSMC_Wait_Signal */
+
+ uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
+ This parameter can be a value of @ref FSMC_Extended_Mode */
+
+ uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
+ valid only with asynchronous Flash memories.
+ This parameter can be a value of @ref FSMC_AsynchronousWait */
+
+ uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
+ This parameter can be a value of @ref FSMC_Write_Burst */
+
+}FSMC_NORSRAM_InitTypeDef;
+
+/**
+ * @brief FSMC_NORSRAM Timing parameters structure definition
+ */
+typedef struct
+{
+ uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address setup time.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+ @note This parameter is not used with synchronous NOR Flash memories. */
+
+ uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address hold time.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 15.
+ @note This parameter is not used with synchronous NOR Flash memories. */
+
+ uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the data setup time.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 255.
+ @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
+ NOR Flash memories. */
+
+ uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
+ the duration of the bus turnaround.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+ @note This parameter is only used for multiplexed NOR Flash memories. */
+
+ uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
+ HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
+ @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
+ accesses. */
+
+ uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
+ to the memory before getting the first data.
+ The parameter value depends on the memory type as shown below:
+ - It must be set to 0 in case of a CRAM
+ - It is don't care in asynchronous NOR, SRAM or ROM accesses
+ - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
+ with synchronous burst mode enable */
+
+ uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
+ This parameter can be a value of @ref FSMC_Access_Mode */
+
+}FSMC_NORSRAM_TimingTypeDef;
+
+/**
+ * @brief FSMC_NAND Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
+ This parameter can be a value of @ref FSMC_NAND_Bank */
+
+ uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
+ This parameter can be any value of @ref FSMC_Wait_feature */
+
+ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
+ This parameter can be any value of @ref FSMC_NAND_Data_Width */
+
+ uint32_t EccComputation; /*!< Enables or disables the ECC computation.
+ This parameter can be any value of @ref FSMC_ECC */
+
+ uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
+ This parameter can be any value of @ref FSMC_ECC_Page_Size */
+
+ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between CLE low and RE low.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between ALE low and RE low.
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+}FSMC_NAND_InitTypeDef;
+
+/**
+ * @brief FSMC_NAND_PCCARD Timing parameters structure definition
+ */
+typedef struct
+{
+ uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
+ the command assertion for NAND-Flash read or write access
+ to common/Attribute or I/O memory space (depending on
+ the memory space timing to be configured).
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
+ command for NAND-Flash read or write access to
+ common/Attribute or I/O memory space (depending on the
+ memory space timing to be configured).
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
+ (and data for write access) after the command de-assertion
+ for NAND-Flash read or write access to common/Attribute
+ or I/O memory space (depending on the memory space timing
+ to be configured).
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
+ data bus is kept in HiZ after the start of a NAND-Flash
+ write access to common/Attribute or I/O memory space (depending
+ on the memory space timing to be configured).
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+}FSMC_NAND_PCC_TimingTypeDef;
+
+/**
+ * @brief FSMC_NAND Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
+ This parameter can be any value of @ref FSMC_Wait_feature */
+
+ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between CLE low and RE low.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between ALE low and RE low.
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+}FSMC_PCCARD_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FSMC_NOR_SRAM_Controller
+ * @{
+ */
+
+/** @defgroup FSMC_NORSRAM_Bank
+ * @{
+ */
+#define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
+#define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
+#define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
+#define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
+
+#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_NORSRAM_BANK1) || \
+ ((BANK) == FSMC_NORSRAM_BANK2) || \
+ ((BANK) == FSMC_NORSRAM_BANK3) || \
+ ((BANK) == FSMC_NORSRAM_BANK4))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Data_Address_Bus_Multiplexing
+ * @{
+ */
+
+#define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
+#define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
+
+#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
+ ((MUX) == FSMC_DATA_ADDRESS_MUX_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Memory_Type
+ * @{
+ */
+
+#define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
+#define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
+#define FSMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
+
+
+#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MEMORY_TYPE_SRAM) || \
+ ((MEMORY) == FSMC_MEMORY_TYPE_PSRAM)|| \
+ ((MEMORY) == FSMC_MEMORY_TYPE_NOR))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_NORSRAM_Data_Width
+ * @{
+ */
+
+#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
+#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
+#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
+
+#define IS_FSMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
+ ((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
+ ((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_NORSRAM_Flash_Access
+ * @{
+ */
+#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
+#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Burst_Access_Mode
+ * @{
+ */
+
+#define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
+#define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
+
+#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
+ ((STATE) == FSMC_BURST_ACCESS_MODE_ENABLE))
+/**
+ * @}
+ */
+
+
+/** @defgroup FSMC_Wait_Signal_Polarity
+ * @{
+ */
+#define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
+#define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
+
+#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
+ ((POLARITY) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wrap_Mode
+ * @{
+ */
+#define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
+#define FSMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
+
+#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WRAP_MODE_DISABLE) || \
+ ((MODE) == FSMC_WRAP_MODE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_Timing
+ * @{
+ */
+#define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
+#define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
+
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WAIT_TIMING_BEFORE_WS) || \
+ ((ACTIVE) == FSMC_WAIT_TIMING_DURING_WS))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Write_Operation
+ * @{
+ */
+#define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
+#define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
+
+#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WRITE_OPERATION_DISABLE) || \
+ ((OPERATION) == FSMC_WRITE_OPERATION_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_Signal
+ * @{
+ */
+#define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
+#define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
+
+#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WAIT_SIGNAL_DISABLE) || \
+ ((SIGNAL) == FSMC_WAIT_SIGNAL_ENABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Extended_Mode
+ * @{
+ */
+#define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
+#define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
+
+#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_EXTENDED_MODE_DISABLE) || \
+ ((MODE) == FSMC_EXTENDED_MODE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_AsynchronousWait
+ * @{
+ */
+#define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
+#define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
+
+#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
+ ((STATE) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Write_Burst
+ * @{
+ */
+
+#define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
+#define FSMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
+
+#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WRITE_BURST_DISABLE) || \
+ ((BURST) == FSMC_WRITE_BURST_ENABLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Continous_Clock
+ * @{
+ */
+
+#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
+#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
+
+#define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
+ ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Address_Setup_Time
+ * @{
+ */
+#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Address_Hold_Time
+ * @{
+ */
+#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Data_Setup_Time
+ * @{
+ */
+#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Bus_Turn_around_Duration
+ * @{
+ */
+#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_CLK_Division
+ * @{
+ */
+#define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Data_Latency
+ * @{
+ */
+#define IS_FSMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Access_Mode
+ * @{
+ */
+#define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000)
+#define FSMC_ACCESS_MODE_B ((uint32_t)0x10000000)
+#define FSMC_ACCESS_MODE_C ((uint32_t)0x20000000)
+#define FSMC_ACCESS_MODE_D ((uint32_t)0x30000000)
+
+#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_ACCESS_MODE_A) || \
+ ((MODE) == FSMC_ACCESS_MODE_B) || \
+ ((MODE) == FSMC_ACCESS_MODE_C) || \
+ ((MODE) == FSMC_ACCESS_MODE_D))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_NAND_Controller
+ * @{
+ */
+
+/** @defgroup FSMC_NAND_Bank
+ * @{
+ */
+#define FSMC_NAND_BANK2 ((uint32_t)0x00000010)
+#define FSMC_NAND_BANK3 ((uint32_t)0x00000100)
+
+#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \
+ ((BANK) == FSMC_NAND_BANK3))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_feature
+ * @{
+ */
+#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
+#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
+
+#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
+ ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_PCR_Memory_Type
+ * @{
+ */
+#define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
+#define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_NAND_Data_Width
+ * @{
+ */
+#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
+#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
+
+#define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
+ ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_ECC
+ * @{
+ */
+#define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
+#define FSMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
+
+#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \
+ ((STATE) == FSMC_NAND_ECC_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_ECC_Page_Size
+ * @{
+ */
+#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
+#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
+#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
+#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
+#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
+#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
+
+#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
+ ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
+ ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
+ ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
+ ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
+ ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_TCLR_Setup_Time
+ * @{
+ */
+#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_TAR_Setup_Time
+ * @{
+ */
+#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Setup_Time
+ * @{
+ */
+#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_Setup_Time
+ * @{
+ */
+#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Hold_Setup_Time
+ * @{
+ */
+#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_HiZ_Setup_Time
+ * @{
+ */
+#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FSMC_NORSRAM_Device_Instance
+ * @{
+ */
+#define IS_FSMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NORSRAM_DEVICE)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance
+ * @{
+ */
+#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NORSRAM_EXTENDED_DEVICE)
+
+/**
+ * @}
+ */
+
+ /** @defgroup FSMC_NAND_Device_Instance
+ * @{
+ */
+#define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_PCCARD_Device_Instance
+ * @{
+ */
+#define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Interrupt_definition
+ * @brief FSMC Interrupt definition
+ * @{
+ */
+#define FSMC_IT_RISING_EDGE ((uint32_t)0x00000008)
+#define FSMC_IT_LEVEL ((uint32_t)0x00000010)
+#define FSMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
+#define FSMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
+
+#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
+#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RISING_EDGE) || \
+ ((IT) == FSMC_IT_LEVEL) || \
+ ((IT) == FSMC_IT_FALLING_EDGE) || \
+ ((IT) == FSMC_IT_REFRESH_ERROR))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Flag_definition
+ * @brief FSMC Flag definition
+ * @{
+ */
+#define FSMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
+#define FSMC_FLAG_LEVEL ((uint32_t)0x00000002)
+#define FSMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
+#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
+
+#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RISING_EDGE) || \
+ ((FLAG) == FSMC_FLAG_LEVEL) || \
+ ((FLAG) == FSMC_FLAG_FALLING_EDGE) || \
+ ((FLAG) == FSMC_FLAG_FEMPT))
+
+#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
+
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+
+
+/** @defgroup FSMC_NOR_Macros
+ * @brief macros to handle NOR device enable/disable and read/write operations
+ * @{
+ */
+
+/**
+ * @brief Enable the NORSRAM device access.
+ * @param __INSTANCE__: FSMC_NORSRAM Instance
+ * @param __BANK__: FSMC_NORSRAM Bank
+ * @retval none
+ */
+#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN)
+
+/**
+ * @brief Disable the NORSRAM device access.
+ * @param __INSTANCE__: FSMC_NORSRAM Instance
+ * @param __BANK__: FSMC_NORSRAM Bank
+ * @retval none
+ */
+#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FSMC_NAND_Macros
+ * @brief macros to handle NAND device enable/disable
+ * @{
+ */
+
+/**
+ * @brief Enable the NAND device access.
+ * @param __INSTANCE__: FSMC_NAND Instance
+ * @param __BANK__: FSMC_NAND Bank
+ * @retval none
+ */
+#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \
+ ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN))
+
+
+/**
+ * @brief Disable the NAND device access.
+ * @param __INSTANCE__: FSMC_NAND Instance
+ * @param __BANK__: FSMC_NAND Bank
+ * @retval none
+ */
+#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
+ ((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
+
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_PCCARD_Macros
+ * @brief macros to handle SRAM read/write operations
+ * @{
+ */
+
+/**
+ * @brief Enable the PCCARD device access.
+ * @param __INSTANCE__: FSMC_PCCARD Instance
+ * @retval none
+ */
+#define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN)
+
+/**
+ * @brief Disable the PCCARD device access.
+ * @param __INSTANCE__: FSMC_PCCARD Instance
+ * @retval none
+ */
+#define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Interrupt
+ * @brief macros to handle FSMC interrupts
+ * @{
+ */
+
+/**
+ * @brief Enable the NAND device interrupt.
+ * @param __INSTANCE__: FSMC_NAND Instance
+ * @param __BANK__: FSMC_NAND Bank
+ * @param __INTERRUPT__: FSMC_NAND interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FSMC_IT_LEVEL: Interrupt level.
+ * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
+ ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
+
+/**
+ * @brief Disable the NAND device interrupt.
+ * @param __INSTANCE__: FSMC_NAND Instance
+ * @param __BANK__: FSMC_NAND Bank
+ * @param __INTERRUPT__: FSMC_NAND interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FSMC_IT_LEVEL: Interrupt level.
+ * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
+ ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
+
+/**
+ * @brief Get flag status of the NAND device.
+ * @param __INSTANCE__: FSMC_NAND Instance
+ * @param __BANK__: FSMC_NAND Bank
+ * @param __FLAG__: FSMC_NAND flag
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
+ (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
+/**
+ * @brief Clear flag status of the NAND device.
+ * @param __INSTANCE__: FSMC_NAND Instance
+ * @param __BANK__: FSMC_NAND Bank
+ * @param __FLAG__: FSMC_NAND flag
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval None
+ */
+#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
+ ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
+/**
+ * @brief Enable the PCCARD device interrupt.
+ * @param __INSTANCE__: FSMC_PCCARD Instance
+ * @param __INTERRUPT__: FSMC_PCCARD interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FSMC_IT_LEVEL: Interrupt level.
+ * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the PCCARD device interrupt.
+ * @param __INSTANCE__: FSMC_PCCARD Instance
+ * @param __INTERRUPT__: FSMC_PCCARD interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FSMC_IT_LEVEL: Interrupt level.
+ * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
+
+/**
+ * @brief Get flag status of the PCCARD device.
+ * @param __INSTANCE__: FSMC_PCCARD Instance
+ * @param __FLAG__: FSMC_PCCARD flag
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear flag status of the PCCARD device.
+ * @param __INSTANCE__: FSMC_PCCARD Instance
+ * @param __FLAG__: FSMC_PCCARD flag
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval None
+ */
+#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* FSMC_NORSRAM Controller functions ******************************************/
+/* Initialization/de-initialization functions */
+HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
+HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
+HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
+
+/* FSMC_NORSRAM Control functions */
+HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+
+/* FSMC_NAND Controller functions *********************************************/
+/* Initialization/de-initialization functions */
+HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
+HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
+
+/* FSMC_NAND Control functions */
+HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
+
+/* FSMC_PCCARD Controller functions *******************************************/
+/* Initialization/de-initialization functions */
+HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
+HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
+
+/* FSMC APIs, macros and typedefs redefinition */
+#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
+#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
+#define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef
+#define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef
+
+#define FMC_NORSRAM_Init FSMC_NORSRAM_Init
+#define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init
+#define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init
+#define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit
+#define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable
+#define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable
+
+#define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE
+#define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE
+
+#define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef
+#define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef
+#define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef
+
+#define FMC_NAND_Init FSMC_NAND_Init
+#define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init
+#define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init
+#define FMC_NAND_DeInit FSMC_NAND_DeInit
+#define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable
+#define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable
+#define FMC_NAND_GetECC FSMC_NAND_GetECC
+#define FMC_PCCARD_Init FSMC_PCCARD_Init
+#define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init
+#define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init
+#define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init
+#define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit
+
+#define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE
+#define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE
+#define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE
+#define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE
+#define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT
+#define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT
+#define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG
+#define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG
+#define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT
+#define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT
+#define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG
+#define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG
+
+#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
+#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
+#define FMC_NAND_TypeDef FSMC_NAND_TypeDef
+#define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef
+
+#define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE
+#define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE
+#define FMC_NAND_DEVICE FSMC_NAND_DEVICE
+#define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE
+
+#define FMC_NAND_BANK2 FSMC_NAND_BANK2
+
+#define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE
+#define FMC_IT_LEVEL FSMC_IT_LEVEL
+#define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE
+#define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR
+
+#define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE
+#define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL
+#define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE
+#define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_FSMC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_ll_sdmmc.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,940 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_sdmmc.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of SDMMC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_SDMMC_H
+#define __STM32F4xx_LL_SDMMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_Driver
+ * @{
+ */
+
+/** @addtogroup SDMMC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief SDMMC Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref SDIO_Clock_Edge */
+
+ uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
+ enabled or disabled.
+ This parameter can be a value of @ref SDIO_Clock_Bypass */
+
+ uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
+ disabled when the bus is idle.
+ This parameter can be a value of @ref SDIO_Clock_Power_Save */
+
+ uint32_t BusWide; /*!< Specifies the SDIO bus width.
+ This parameter can be a value of @ref SDIO_Bus_Wide */
+
+ uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
+ This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
+
+ uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
+
+}SDIO_InitTypeDef;
+
+
+/**
+ * @brief SDIO Command Control structure
+ */
+typedef struct
+{
+ uint32_t Argument; /*!< Specifies the SDIO command argument which is sent
+ to a card as part of a command message. If a command
+ contains an argument, it must be loaded into this register
+ before writing the command to the command register. */
+
+ uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and
+ Max_Data = 64 */
+
+ uint32_t Response; /*!< Specifies the SDIO response type.
+ This parameter can be a value of @ref SDIO_Response_Type */
+
+ uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is
+ enabled or disabled.
+ This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
+
+ uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
+ is enabled or disabled.
+ This parameter can be a value of @ref SDIO_CPSM_State */
+}SDIO_CmdInitTypeDef;
+
+
+/**
+ * @brief SDIO Data Control structure
+ */
+typedef struct
+{
+ uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
+
+ uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
+
+ uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
+ This parameter can be a value of @ref SDIO_Data_Block_Size */
+
+ uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
+ is a read or write.
+ This parameter can be a value of @ref SDIO_Transfer_Direction */
+
+ uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
+ This parameter can be a value of @ref SDIO_Transfer_Type */
+
+ uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
+ is enabled or disabled.
+ This parameter can be a value of @ref SDIO_DPSM_State */
+}SDIO_DataInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SDIO_Exported_Constants
+ * @{
+ */
+
+/** @defgroup SDIO_Clock_Edge
+ * @{
+ */
+#define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000)
+#define SDIO_CLOCK_EDGE_FALLING ((uint32_t)0x00002000)
+
+#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
+ ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Clock_Bypass
+ * @{
+ */
+#define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000)
+#define SDIO_CLOCK_BYPASS_ENABLE ((uint32_t)0x00000400)
+
+#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
+ ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Clock_Power_Save
+ * @{
+ */
+#define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000)
+#define SDIO_CLOCK_POWER_SAVE_ENABLE ((uint32_t)0x00000200)
+
+#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
+ ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Bus_Wide
+ * @{
+ */
+#define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000)
+#define SDIO_BUS_WIDE_4B ((uint32_t)0x00000800)
+#define SDIO_BUS_WIDE_8B ((uint32_t)0x00001000)
+
+#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
+ ((WIDE) == SDIO_BUS_WIDE_4B) || \
+ ((WIDE) == SDIO_BUS_WIDE_8B))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Hardware_Flow_Control
+ * @{
+ */
+#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000)
+#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE ((uint32_t)0x00004000)
+
+#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
+ ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Clock_Division
+ * @{
+ */
+#define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Command_Index
+ * @{
+ */
+#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Response_Type
+ * @{
+ */
+#define SDIO_RESPONSE_NO ((uint32_t)0x00000000)
+#define SDIO_RESPONSE_SHORT ((uint32_t)0x00000040)
+#define SDIO_RESPONSE_LONG ((uint32_t)0x000000C0)
+
+#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \
+ ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
+ ((RESPONSE) == SDIO_RESPONSE_LONG))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Wait_Interrupt_State
+ * @{
+ */
+#define SDIO_WAIT_NO ((uint32_t)0x00000000)
+#define SDIO_WAIT_IT ((uint32_t)0x00000100)
+#define SDIO_WAIT_PEND ((uint32_t)0x00000200)
+
+#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
+ ((WAIT) == SDIO_WAIT_IT) || \
+ ((WAIT) == SDIO_WAIT_PEND))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_CPSM_State
+ * @{
+ */
+#define SDIO_CPSM_DISABLE ((uint32_t)0x00000000)
+#define SDIO_CPSM_ENABLE ((uint32_t)0x00000400)
+
+#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
+ ((CPSM) == SDIO_CPSM_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Response_Registers
+ * @{
+ */
+#define SDIO_RESP1 ((uint32_t)0x00000000)
+#define SDIO_RESP2 ((uint32_t)0x00000004)
+#define SDIO_RESP3 ((uint32_t)0x00000008)
+#define SDIO_RESP4 ((uint32_t)0x0000000C)
+
+#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
+ ((RESP) == SDIO_RESP2) || \
+ ((RESP) == SDIO_RESP3) || \
+ ((RESP) == SDIO_RESP4))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Data_Length
+ * @{
+ */
+#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Data_Block_Size
+ * @{
+ */
+#define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000)
+#define SDIO_DATABLOCK_SIZE_2B ((uint32_t)0x00000010)
+#define SDIO_DATABLOCK_SIZE_4B ((uint32_t)0x00000020)
+#define SDIO_DATABLOCK_SIZE_8B ((uint32_t)0x00000030)
+#define SDIO_DATABLOCK_SIZE_16B ((uint32_t)0x00000040)
+#define SDIO_DATABLOCK_SIZE_32B ((uint32_t)0x00000050)
+#define SDIO_DATABLOCK_SIZE_64B ((uint32_t)0x00000060)
+#define SDIO_DATABLOCK_SIZE_128B ((uint32_t)0x00000070)
+#define SDIO_DATABLOCK_SIZE_256B ((uint32_t)0x00000080)
+#define SDIO_DATABLOCK_SIZE_512B ((uint32_t)0x00000090)
+#define SDIO_DATABLOCK_SIZE_1024B ((uint32_t)0x000000A0)
+#define SDIO_DATABLOCK_SIZE_2048B ((uint32_t)0x000000B0)
+#define SDIO_DATABLOCK_SIZE_4096B ((uint32_t)0x000000C0)
+#define SDIO_DATABLOCK_SIZE_8192B ((uint32_t)0x000000D0)
+#define SDIO_DATABLOCK_SIZE_16384B ((uint32_t)0x000000E0)
+
+#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Transfer_Direction
+ * @{
+ */
+#define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000)
+#define SDIO_TRANSFER_DIR_TO_SDIO ((uint32_t)0x00000002)
+
+#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
+ ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Transfer_Type
+ * @{
+ */
+#define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000)
+#define SDIO_TRANSFER_MODE_STREAM ((uint32_t)0x00000004)
+
+#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
+ ((MODE) == SDIO_TRANSFER_MODE_STREAM))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_DPSM_State
+ * @{
+ */
+#define SDIO_DPSM_DISABLE ((uint32_t)0x00000000)
+#define SDIO_DPSM_ENABLE ((uint32_t)0x00000001)
+
+#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
+ ((DPSM) == SDIO_DPSM_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Read_Wait_Mode
+ * @{
+ */
+#define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000000)
+#define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000001)
+
+#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
+ ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Interrupt_sources
+ * @{
+ */
+#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
+#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
+#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
+#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
+#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
+#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
+#define SDIO_IT_CMDREND ((uint32_t)0x00000040)
+#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
+#define SDIO_IT_DATAEND ((uint32_t)0x00000100)
+#define SDIO_IT_STBITERR ((uint32_t)0x00000200)
+#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
+#define SDIO_IT_CMDACT ((uint32_t)0x00000800)
+#define SDIO_IT_TXACT ((uint32_t)0x00001000)
+#define SDIO_IT_RXACT ((uint32_t)0x00002000)
+#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
+#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
+#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
+#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
+#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
+#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
+#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
+#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
+#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
+#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
+
+#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Flags
+ * @{
+ */
+#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
+#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
+#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
+#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
+#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
+#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
+#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
+#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
+#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
+#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
+#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
+#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
+#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
+#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
+#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
+#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
+#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
+#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
+#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
+#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
+#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
+#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
+#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
+#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
+
+#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
+ ((FLAG) == SDIO_FLAG_DCRCFAIL) || \
+ ((FLAG) == SDIO_FLAG_CTIMEOUT) || \
+ ((FLAG) == SDIO_FLAG_DTIMEOUT) || \
+ ((FLAG) == SDIO_FLAG_TXUNDERR) || \
+ ((FLAG) == SDIO_FLAG_RXOVERR) || \
+ ((FLAG) == SDIO_FLAG_CMDREND) || \
+ ((FLAG) == SDIO_FLAG_CMDSENT) || \
+ ((FLAG) == SDIO_FLAG_DATAEND) || \
+ ((FLAG) == SDIO_FLAG_STBITERR) || \
+ ((FLAG) == SDIO_FLAG_DBCKEND) || \
+ ((FLAG) == SDIO_FLAG_CMDACT) || \
+ ((FLAG) == SDIO_FLAG_TXACT) || \
+ ((FLAG) == SDIO_FLAG_RXACT) || \
+ ((FLAG) == SDIO_FLAG_TXFIFOHE) || \
+ ((FLAG) == SDIO_FLAG_RXFIFOHF) || \
+ ((FLAG) == SDIO_FLAG_TXFIFOF) || \
+ ((FLAG) == SDIO_FLAG_RXFIFOF) || \
+ ((FLAG) == SDIO_FLAG_TXFIFOE) || \
+ ((FLAG) == SDIO_FLAG_RXFIFOE) || \
+ ((FLAG) == SDIO_FLAG_TXDAVL) || \
+ ((FLAG) == SDIO_FLAG_RXDAVL) || \
+ ((FLAG) == SDIO_FLAG_SDIOIT) || \
+ ((FLAG) == SDIO_FLAG_CEATAEND))
+
+#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
+
+#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
+ ((IT) == SDIO_IT_DCRCFAIL) || \
+ ((IT) == SDIO_IT_CTIMEOUT) || \
+ ((IT) == SDIO_IT_DTIMEOUT) || \
+ ((IT) == SDIO_IT_TXUNDERR) || \
+ ((IT) == SDIO_IT_RXOVERR) || \
+ ((IT) == SDIO_IT_CMDREND) || \
+ ((IT) == SDIO_IT_CMDSENT) || \
+ ((IT) == SDIO_IT_DATAEND) || \
+ ((IT) == SDIO_IT_STBITERR) || \
+ ((IT) == SDIO_IT_DBCKEND) || \
+ ((IT) == SDIO_IT_CMDACT) || \
+ ((IT) == SDIO_IT_TXACT) || \
+ ((IT) == SDIO_IT_RXACT) || \
+ ((IT) == SDIO_IT_TXFIFOHE) || \
+ ((IT) == SDIO_IT_RXFIFOHF) || \
+ ((IT) == SDIO_IT_TXFIFOF) || \
+ ((IT) == SDIO_IT_RXFIFOF) || \
+ ((IT) == SDIO_IT_TXFIFOE) || \
+ ((IT) == SDIO_IT_RXFIFOE) || \
+ ((IT) == SDIO_IT_TXDAVL) || \
+ ((IT) == SDIO_IT_RXDAVL) || \
+ ((IT) == SDIO_IT_SDIOIT) || \
+ ((IT) == SDIO_IT_CEATAEND))
+
+#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup SDIO_Instance_definition
+ * @{
+ */
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* ------------ SDIO registers bit address in the alias region -------------- */
+#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
+
+/* --- CLKCR Register ---*/
+/* Alias word address of CLKEN bit */
+#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
+#define CLKEN_BitNumber 0x08
+#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
+
+/* --- CMD Register ---*/
+/* Alias word address of SDIOSUSPEND bit */
+#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
+#define SDIOSUSPEND_BitNumber 0x0B
+#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
+
+/* Alias word address of ENCMDCOMPL bit */
+#define ENCMDCOMPL_BitNumber 0x0C
+#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
+
+/* Alias word address of NIEN bit */
+#define NIEN_BitNumber 0x0D
+#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
+
+/* Alias word address of ATACMD bit */
+#define ATACMD_BitNumber 0x0E
+#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
+
+/* --- DCTRL Register ---*/
+/* Alias word address of DMAEN bit */
+#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
+#define DMAEN_BitNumber 0x03
+#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
+
+/* Alias word address of RWSTART bit */
+#define RWSTART_BitNumber 0x08
+#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
+
+/* Alias word address of RWSTOP bit */
+#define RWSTOP_BitNumber 0x09
+#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
+
+/* Alias word address of RWMOD bit */
+#define RWMOD_BitNumber 0x0A
+#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
+
+/* Alias word address of SDIOEN bit */
+#define SDIOEN_BitNumber 0x0B
+#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
+
+/* ---------------------- SDIO registers bit mask --------------------------- */
+/* --- CLKCR Register ---*/
+/* CLKCR register clear mask */
+#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
+
+/* --- PWRCTRL Register ---*/
+/* SDIO PWRCTRL Mask */
+#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
+
+/* --- DCTRL Register ---*/
+/* SDIO DCTRL Clear Mask */
+#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
+
+/* --- CMD Register ---*/
+/* CMD Register clear mask */
+#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
+
+/* SDIO RESP Registers Address */
+#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
+
+/* SD FLASH SDIO Interface */
+#define SDIO_FIFO_ADDRESS ((uint32_t)0x40012C80)
+
+/* SDIO Intialization Frequency (400KHz max) */
+#define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
+
+/* SDIO Data Transfer Frequency (25MHz max) */
+#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
+
+/** @defgroup SDIO_Interrupt_Clock
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+
+/**
+ * @brief Enable the SDIO device.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_ENABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
+
+/**
+ * @brief Disable the SDIO device.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_DISABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
+
+/**
+ * @brief Enable the SDIO DMA transfer.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_DMA_ENABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
+
+/**
+ * @brief Disable the SDIO DMA transfer.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_DMA_DISABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
+
+/**
+ * @brief Enable the SDIO device interrupt.
+ * @param __INSTANCE__ : Pointer to SDIO register base
+ * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+ * @retval None
+ */
+#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the SDIO device interrupt.
+ * @param __INSTANCE__ : Pointer to SDIO register base
+ * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+ * @retval None
+ */
+#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
+
+/**
+ * @brief Checks whether the specified SDIO flag is set or not.
+ * @param __INSTANCE__ : Pointer to SDIO register base
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDIO_FLAG_CMDACT: Command transfer in progress
+ * @arg SDIO_FLAG_TXACT: Data transmit in progress
+ * @arg SDIO_FLAG_RXACT: Data receive in progress
+ * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+ * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
+ * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
+ * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
+ * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
+ * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
+ * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
+ * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+ * @retval The new state of SDIO_FLAG (SET or RESET).
+ */
+#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
+
+
+/**
+ * @brief Clears the SDIO's pending flags.
+ * @param __INSTANCE__ : Pointer to SDIO register base
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+ * @retval None
+ */
+#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
+
+/**
+ * @brief Checks whether the specified SDIO interrupt has occurred or not.
+ * @param __INSTANCE__ : Pointer to SDIO register base
+ * @param __INTERRUPT__: specifies the SDIO interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+ * @retval The new state of SDIO_IT (SET or RESET).
+ */
+#define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @brief Clears the SDIO's interrupt pending bits.
+ * @param __INSTANCE__ : Pointer to SDIO register base
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
+ * @retval None
+ */
+#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
+
+/**
+ * @brief Enable Start the SD I/O Read Wait operation.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_START_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
+
+/**
+ * @brief Disable Start the SD I/O Read Wait operations.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_START_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
+
+/**
+ * @brief Enable Start the SD I/O Read Wait operation.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_STOP_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
+
+/**
+ * @brief Disable Stop the SD I/O Read Wait operations.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_STOP_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
+
+/**
+ * @brief Enable the SD I/O Mode Operation.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_OPERATION_ENABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
+
+/**
+ * @brief Disable the SD I/O Mode Operation.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_OPERATION_DISABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
+
+/**
+ * @brief Enable the SD I/O Suspend command sending.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_SUSPEND_CMD_ENABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
+
+/**
+ * @brief Disable the SD I/O Suspend command sending.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_SUSPEND_CMD_DISABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
+
+/**
+ * @brief Enable the command completion signal.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
+
+/**
+ * @brief Disable the command completion signal.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
+
+/**
+ * @brief Enable the CE-ATA interrupt.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0)
+
+/**
+ * @brief Disable the CE-ATA interrupt.
+ * @param None
+ * @retval None
+ */
+#define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1)
+
+/**
+ * @brief Enable send CE-ATA command (CMD61).
+ * @param None
+ * @retval None
+ */
+#define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
+
+/**
+ * @brief Disable send CE-ATA command (CMD61).
+ * @param None
+ * @retval None
+ */
+#define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
+
+/* I/O operation functions *****************************************************/
+/* Blocking mode: Polling */
+uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
+HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
+
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
+HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
+uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
+
+/* Command path state machine (CPSM) management functions */
+HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
+uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
+
+/* Data path state machine (DPSM) management functions */
+HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
+uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
+
+/* SDIO IO Cards mode management functions */
+HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_SDMMC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_ll_usb.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,459 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_ll_usb.h
+ * @author MCD Application Team
+ * @version V1.1.0RC2
+ * @date 14-May-2014
+ * @brief Header file of USB Core HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_USB_H
+#define __STM32F4xx_LL_USB_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL
+ * @{
+ */
+
+/** @addtogroup USB_Core
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief USB Mode definition
+ */
+typedef enum
+{
+ USB_OTG_DEVICE_MODE = 0,
+ USB_OTG_HOST_MODE = 1,
+ USB_OTG_DRD_MODE = 2
+
+}USB_OTG_ModeTypeDef;
+
+/**
+ * @brief URB States definition
+ */
+typedef enum {
+ URB_IDLE = 0,
+ URB_DONE,
+ URB_NOTREADY,
+ URB_NYET,
+ URB_ERROR,
+ URB_STALL
+
+}USB_OTG_URBStateTypeDef;
+
+/**
+ * @brief Host channel States definition
+ */
+typedef enum {
+ HC_IDLE = 0,
+ HC_XFRC,
+ HC_HALTED,
+ HC_NAK,
+ HC_NYET,
+ HC_STALL,
+ HC_XACTERR,
+ HC_BBLERR,
+ HC_DATATGLERR
+
+}USB_OTG_HCStateTypeDef;
+
+/**
+ * @brief PCD Initialization Structure definition
+ */
+typedef struct
+{
+ uint32_t dev_endpoints; /*!< Device Endpoints number.
+ This parameter depends on the used USB core.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint32_t Host_channels; /*!< Host Channels number.
+ This parameter Depends on the used USB core.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint32_t speed; /*!< USB Core speed.
+ This parameter can be any value of @ref USB_Core_Speed_ */
+
+ uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA. */
+
+ uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size.
+ This parameter can be any value of @ref USB_EP0_MPS_ */
+
+ uint32_t phy_itface; /*!< Select the used PHY interface.
+ This parameter can be any value of @ref USB_Core_PHY_ */
+
+ uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
+
+ uint32_t low_power_enable; /*!< Enable or disable the low power mode. */
+
+ uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
+
+ uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
+
+ uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
+
+}USB_OTG_CfgTypeDef;
+
+typedef struct
+{
+ uint8_t num; /*!< Endpoint number
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint8_t is_in; /*!< Endpoint direction
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t is_stall; /*!< Endpoint stall condition
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t type; /*!< Endpoint type
+ This parameter can be any value of @ref USB_EP_Type_ */
+
+ uint8_t data_pid_start; /*!< Initial data PID
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t even_odd_frame; /*!< IFrame parity
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint16_t tx_fifo_num; /*!< Transmission FIFO number
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint32_t maxpacket; /*!< Endpoint Max packet size
+ This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
+
+ uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
+
+ uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */
+
+ uint32_t xfer_len; /*!< Current transfer length */
+
+ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
+
+}USB_OTG_EPTypeDef;
+
+typedef struct
+{
+ uint8_t dev_addr ; /*!< USB device address.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
+
+ uint8_t ch_num; /*!< Host channel number.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint8_t ep_num; /*!< Endpoint number.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint8_t ep_is_in; /*!< Endpoint direction
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t speed; /*!< USB Host speed.
+ This parameter can be any value of @ref USB_Core_Speed_ */
+
+ uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
+
+ uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */
+
+ uint8_t ep_type; /*!< Endpoint Type.
+ This parameter can be any value of @ref USB_EP_Type_ */
+
+ uint16_t max_packet; /*!< Endpoint Max packet size.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
+
+ uint8_t data_pid; /*!< Initial data PID.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
+
+ uint32_t xfer_len; /*!< Current transfer length. */
+
+ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
+
+ uint8_t toggle_in; /*!< IN transfer current toggle flag.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t toggle_out; /*!< OUT transfer current toggle flag
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
+
+ uint32_t ErrCnt; /*!< Host channel error count.*/
+
+ USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
+ This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
+
+ USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
+ This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
+
+}USB_OTG_HCTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PCD_Exported_Constants
+ * @{
+ */
+
+/** @defgroup USB_Core_Mode_
+ * @{
+ */
+#define USB_OTG_MODE_DEVICE 0
+#define USB_OTG_MODE_HOST 1
+#define USB_OTG_MODE_DRD 2
+/**
+ * @}
+ */
+
+/** @defgroup USB_Core_Speed_
+ * @{
+ */
+#define USB_OTG_SPEED_HIGH 0
+#define USB_OTG_SPEED_HIGH_IN_FULL 1
+#define USB_OTG_SPEED_LOW 2
+#define USB_OTG_SPEED_FULL 3
+/**
+ * @}
+ */
+
+/** @defgroup USB_Core_PHY_
+ * @{
+ */
+#define USB_OTG_ULPI_PHY 1
+#define USB_OTG_EMBEDDED_PHY 2
+/**
+ * @}
+ */
+
+/** @defgroup USB_Core_MPS_
+ * @{
+ */
+#define USB_OTG_HS_MAX_PACKET_SIZE 512
+#define USB_OTG_FS_MAX_PACKET_SIZE 64
+#define USB_OTG_MAX_EP0_SIZE 64
+/**
+ * @}
+ */
+
+/** @defgroup USB_Core_Phy_Frequency_
+ * @{
+ */
+#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0 << 1)
+#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1 << 1)
+#define DSTS_ENUMSPD_LS_PHY_6MHZ (2 << 1)
+#define DSTS_ENUMSPD_FS_PHY_48MHZ (3 << 1)
+/**
+ * @}
+ */
+
+/** @defgroup USB_CORE_Frame_Interval_
+ * @{
+ */
+#define DCFG_FRAME_INTERVAL_80 0
+#define DCFG_FRAME_INTERVAL_85 1
+#define DCFG_FRAME_INTERVAL_90 2
+#define DCFG_FRAME_INTERVAL_95 3
+/**
+ * @}
+ */
+
+/** @defgroup USB_EP0_MPS_
+ * @{
+ */
+#define DEP0CTL_MPS_64 0
+#define DEP0CTL_MPS_32 1
+#define DEP0CTL_MPS_16 2
+#define DEP0CTL_MPS_8 3
+/**
+ * @}
+ */
+
+/** @defgroup USB_EP_Speed_
+ * @{
+ */
+#define EP_SPEED_LOW 0
+#define EP_SPEED_FULL 1
+#define EP_SPEED_HIGH 2
+/**
+ * @}
+ */
+
+/** @defgroup USB_EP_Type_
+ * @{
+ */
+#define EP_TYPE_CTRL 0
+#define EP_TYPE_ISOC 1
+#define EP_TYPE_BULK 2
+#define EP_TYPE_INTR 3
+#define EP_TYPE_MSK 3
+/**
+ * @}
+ */
+
+/** @defgroup USB_STS_Defines_
+ * @{
+ */
+#define STS_GOUT_NAK 1
+#define STS_DATA_UPDT 2
+#define STS_XFER_COMP 3
+#define STS_SETUP_COMP 4
+#define STS_SETUP_UPDT 6
+/**
+ * @}
+ */
+
+/** @defgroup HCFG_SPEED_Defines_
+ * @{
+ */
+#define HCFG_30_60_MHZ 0
+#define HCFG_48_MHZ 1
+#define HCFG_6_MHZ 2
+/**
+ * @}
+ */
+
+/** @defgroup HPRT0_PRTSPD_SPEED_Defines_
+ * @{
+ */
+#define HPRT0_PRTSPD_HIGH_SPEED 0
+#define HPRT0_PRTSPD_FULL_SPEED 1
+#define HPRT0_PRTSPD_LOW_SPEED 2
+/**
+ * @}
+ */
+
+#define HCCHAR_CTRL 0
+#define HCCHAR_ISOC 1
+#define HCCHAR_BULK 2
+#define HCCHAR_INTR 3
+
+#define HC_PID_DATA0 0
+#define HC_PID_DATA2 1
+#define HC_PID_DATA1 2
+#define HC_PID_SETUP 3
+
+#define GRXSTS_PKTSTS_IN 2
+#define GRXSTS_PKTSTS_IN_XFER_COMP 3
+#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5
+#define GRXSTS_PKTSTS_CH_HALTED 7
+
+#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE)
+#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE)
+
+#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE))
+#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))
+#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))
+#define USBx_DFIFO(i) *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE)
+
+#define USBx_HOST ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE))
+#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE))
+
+/* Exported macro ------------------------------------------------------------*/
+#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
+#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
+
+#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
+#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
+
+/* Exported functions --------------------------------------------------------*/
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
+HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode);
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed);
+HAL_StatusTypeDef USB_FlushRxFifo (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num );
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
+HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma);
+void * USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address);
+HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
+uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
+uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
+void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
+
+HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq);
+HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state);
+uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
+ uint8_t ch_num,
+ uint8_t epnum,
+ uint8_t dev_address,
+ uint8_t speed,
+ uint8_t ep_type,
+ uint16_t mps);
+HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);
+uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num);
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num);
+HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_LL_USB_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_ARCH_MAX/system_stm32f4xx.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,124 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.h
+ * @author MCD Application Team
+ * @version V2.1.0RC2
+ * @date 14-May-2014
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F4xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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--- a/TARGET_GHI_MBUINO/LPC11Uxx.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,670 +0,0 @@
-
-/****************************************************************************************************//**
- * @file LPC11Uxx.h
- *
- *
- * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
- * default LPC11Uxx Device Series
- *
- * @version V0.1
- * @date 21. March 2011
- *
- * @note Generated with SFDGen V2.6 Build 3j (beta) on Thursday, 17.03.2011 13:19:45
- *
- * from CMSIS SVD File 'LPC11U1x_svd.xml' Version 0.1,
- * created on Wednesday, 16.03.2011 20:30:42, last modified on Thursday, 17.03.2011 20:19:40
- *
- *******************************************************************************************************/
-
-// ################################################################################
-// Minor fix 8 April 2011 - changed LPC_CT32B1_BASE from 0x40014000 to 0x40018000
-// ################################################################################
-
-/** @addtogroup NXP
- * @{
- */
-
-/** @addtogroup LPC11Uxx
- * @{
- */
-
-#ifndef __LPC11UXX_H__
-#define __LPC11UXX_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-#if defined ( __CC_ARM )
- #pragma anon_unions
-#endif
-
- /* Interrupt Number Definition */
-
-typedef enum {
-// ------------------------- Cortex-M0 Processor Exceptions Numbers -----------------------------
- Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
- SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
- PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
- SysTick_IRQn = -1, /*!< 15 System Tick Timer */
-// --------------------------- LPC11Uxx Specific Interrupt Numbers ------------------------------
-FLEX_INT0_IRQn = 0, /*!< All I/O pins can be routed to below 8 interrupts. */
- FLEX_INT1_IRQn = 1,
- FLEX_INT2_IRQn = 2,
- FLEX_INT3_IRQn = 3,
- FLEX_INT4_IRQn = 4,
- FLEX_INT5_IRQn = 5,
- FLEX_INT6_IRQn = 6,
- FLEX_INT7_IRQn = 7,
- GINT0_IRQn = 8, /*!< Grouped Interrupt 0 */
- GINT1_IRQn = 9, /*!< Grouped Interrupt 1 */
- Reserved0_IRQn = 10, /*!< Reserved Interrupt */
- Reserved1_IRQn = 11,
- Reserved2_IRQn = 12,
- Reserved3_IRQn = 13,
- SSP1_IRQn = 14, /*!< SSP1 Interrupt */
- I2C_IRQn = 15, /*!< I2C Interrupt */
- TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */
- TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */
- TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */
- TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */
- SSP0_IRQn = 20, /*!< SSP0 Interrupt */
- UART_IRQn = 21, /*!< UART Interrupt */
- USB_IRQn = 22, /*!< USB IRQ Interrupt */
- USB_FIQn = 23, /*!< USB FIQ Interrupt */
- ADC_IRQn = 24, /*!< A/D Converter Interrupt */
- WDT_IRQn = 25, /*!< Watchdog timer Interrupt */
- BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */
- FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */
- Reserved4_IRQn = 28, /*!< Reserved Interrupt */
- Reserved5_IRQn = 29, /*!< Reserved Interrupt */
- USBWakeup_IRQn = 30, /*!< USB wakeup Interrupt */
- Reserved6_IRQn = 31, /*!< Reserved Interrupt */
-} IRQn_Type;
-
-
-/** @addtogroup Configuration_of_CMSIS
- * @{
- */
-
-/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M0 Processor and Core Peripherals */
-
-#define __MPU_PRESENT 0 /*!< MPU present or not */
-#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-/** @} */ /* End of group Configuration_of_CMSIS */
-
-#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
-#include "system_LPC11Uxx.h" /*!< LPC11Uxx System */
-
-/** @addtogroup Device_Peripheral_Registers
- * @{
- */
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- I2C -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC11U1x I2C-bus controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (I2C)
- */
-
-typedef struct { /*!< (@ 0x40000000) I2C Structure */
- __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register */
- __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register */
- __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. */
- __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0 */
- __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word */
- __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word */
- __IO uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register*/
- __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register*/
- __IO uint32_t ADR1; /*!< (@ 0x40000020) I2C Slave Address Register 1*/
- __IO uint32_t ADR2; /*!< (@ 0x40000024) I2C Slave Address Register 2*/
- __IO uint32_t ADR3; /*!< (@ 0x40000028) I2C Slave Address Register 3*/
- __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register */
-union{
- __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register */
- struct{
- __IO uint32_t MASK0;
- __IO uint32_t MASK1;
- __IO uint32_t MASK2;
- __IO uint32_t MASK3;
- };
- };
-} LPC_I2C_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- WWDT -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC11U1x Windowed Watchdog Timer (WWDT) Modification date=3/16/2011 Major revision=0 Minor revision=3 (WWDT)
- */
-
-typedef struct { /*!< (@ 0x40004000) WWDT Structure */
- __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register*/
- __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register */
- __IO uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register */
- __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register */
- __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
- __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
- __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
-} LPC_WWDT_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- USART -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC11U1x USART Modification date=3/16/2011 Major revision=0 Minor revision=3 (USART)
- */
-
-typedef struct { /*!< (@ 0x40008000) USART Structure */
-
- union {
- __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
- __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
- __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
- };
-
- union {
- __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
- __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
- };
-
- union {
- __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
- __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
- };
- __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
- __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
- __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
- __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
- __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
- __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
- __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
- __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
- __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
- __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
- __I uint32_t RESERVED0[3];
- __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
- __I uint32_t RESERVED1;
- __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
- __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
- __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
- __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
- __IO uint32_t SYNCCTRL;
-} LPC_USART_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- Timer -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC11U1x 32-bitcounter/timers CT32B0/1 Modification date=3/16/2011 Major revision=0 Minor revision=3
- */
-
-typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
- __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register */
- __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register */
- __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter */
- __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register */
- __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter */
- __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register */
- union {
- __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register */
- struct{
- __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */
- __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */
- __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */
- __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */
- };
- };
- __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register */
- union{
- __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register */
- struct{
- __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */
- __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */
- __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */
- __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */
- };
- };
-__IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register */
- __I uint32_t RESERVED0[12];
- __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register */
- __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register */
-} LPC_CTxxBx_Type;
-
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- ADC -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC11U1x ADC Modification date=3/16/2011 Major revision=0 Minor revision=3 (ADC)
- */
-
-typedef struct { /*!< (@ 0x4001C000) ADC Structure */
- __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register */
- __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register */
- __I uint32_t RESERVED0[1];
- __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register */
- union{
- __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/
- struct{
- __IO uint32_t DR0; /*!< (@ 0x40020010) A/D Channel Data Register 0*/
- __IO uint32_t DR1; /*!< (@ 0x40020014) A/D Channel Data Register 1*/
- __IO uint32_t DR2; /*!< (@ 0x40020018) A/D Channel Data Register 2*/
- __IO uint32_t DR3; /*!< (@ 0x4002001C) A/D Channel Data Register 3*/
- __IO uint32_t DR4; /*!< (@ 0x40020020) A/D Channel Data Register 4*/
- __IO uint32_t DR5; /*!< (@ 0x40020024) A/D Channel Data Register 5*/
- __IO uint32_t DR6; /*!< (@ 0x40020028) A/D Channel Data Register 6*/
- __IO uint32_t DR7; /*!< (@ 0x4002002C) A/D Channel Data Register 7*/
- };
- };
- __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. */
-} LPC_ADC_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- PMU -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC11U1x Power Management Unit (PMU) Modification date=3/16/2011 Major revision=0 Minor revision=3 (PMU)
- */
-
-typedef struct { /*!< (@ 0x40038000) PMU Structure */
- __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */
- union{
- __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */
- struct{
- __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */
- __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */
- __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */
- __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */
- };
- };
-} LPC_PMU_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- FLASHCTRL -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC11U1x Flash programming firmware Modification date=3/17/2011 Major revision=0 Minor revision=3 (FLASHCTRL)
- */
-
-typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
- __I uint32_t RESERVED0[4];
- __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
- __I uint32_t RESERVED1[3];
- __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
- __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
- __I uint32_t RESERVED2[1];
- __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
- __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
- __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
- __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
- __I uint32_t RESERVED3[1001];
- __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
- __I uint32_t RESERVED4[1];
- __IO uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
-} LPC_FLASHCTRL_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- SSP0/1 -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC11U1x SSP/SPI Modification date=3/16/2011 Major revision=0 Minor revision=3 (SSP0)
- */
-
-typedef struct { /*!< (@ 0x40040000) SSP0 Structure */
- __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
- __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
- __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
- __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */
- __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */
- __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
- __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */
- __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */
- __IO uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
-} LPC_SSPx_Type;
-
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- IOCONFIG -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC11U1x I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG)
- */
-
-typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */
- __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
- __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
- __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
- __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
- __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
- __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
- __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
- __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
- __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 */
- __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 */
- __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
- __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
- __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
- __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
- __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
- __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
- __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
- __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
- __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
- __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
- __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
- __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
- __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
- __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
- __IO uint32_t PIO1_0; /*!< Offset: 0x060 */
- __IO uint32_t PIO1_1;
- __IO uint32_t PIO1_2;
- __IO uint32_t PIO1_3;
- __IO uint32_t PIO1_4; /*!< Offset: 0x070 */
- __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
- __IO uint32_t PIO1_6;
- __IO uint32_t PIO1_7;
- __IO uint32_t PIO1_8; /*!< Offset: 0x080 */
- __IO uint32_t PIO1_9;
- __IO uint32_t PIO1_10;
- __IO uint32_t PIO1_11;
- __IO uint32_t PIO1_12; /*!< Offset: 0x090 */
- __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for pin PIO1_13/DTR/CT16B0_MAT0/TXD */
- __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for pin PIO1_14/DSR/CT16B0_MAT1/RXD */
- __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
- __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
- __IO uint32_t PIO1_17;
- __IO uint32_t PIO1_18;
- __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
- __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
- __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
- __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
- __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
- __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
- __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
- __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
- __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
- __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
- __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
- __IO uint32_t PIO1_30;
- __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
-} LPC_IOCON_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- SYSCON -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC11U1x System control block Modification date=3/16/2011 Major revision=0 Minor revision=3 (SYSCON)
- */
-
-typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
- __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
- __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
- __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
- __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
- __IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */
- __I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */
- __I uint32_t RESERVED0[2];
- __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
- __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
- __I uint32_t RESERVED1[2];
- __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
- __I uint32_t RESERVED2[3];
- __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
- __IO uint32_t SYSPLLCLKUEN; /*!< (@ 0x40048044) System PLL clock source update enable */
- __IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */
- __IO uint32_t USBPLLCLKUEN; /*!< (@ 0x4004804C) USB PLL clock source update enable */
- __I uint32_t RESERVED3[8];
- __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
- __IO uint32_t MAINCLKUEN; /*!< (@ 0x40048074) Main clock source update enable */
- __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
- __I uint32_t RESERVED4[1];
- __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
- __I uint32_t RESERVED5[4];
- __IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */
- __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */
- __IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */
- __I uint32_t RESERVED6[8];
- __IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */
- __IO uint32_t USBCLKUEN; /*!< (@ 0x400480C4) USB clock source update enable */
- __IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */
- __I uint32_t RESERVED7[5];
- __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
- __IO uint32_t CLKOUTUEN; /*!< (@ 0x400480E4) CLKOUT clock source update enable */
- __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
- __I uint32_t RESERVED8[5];
- __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
- __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */
- __I uint32_t RESERVED9[18];
- __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
- __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
- __I uint32_t RESERVED10[6];
- __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay */
- __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
- __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
- __IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */
- __I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */
- __I uint32_t RESERVED11[25];
- __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
- __I uint32_t RESERVED12[3];
- __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
- __I uint32_t RESERVED13[6];
- __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
- __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
- __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
- __I uint32_t RESERVED14[110];
- __I uint32_t DEVICE_ID; /*!< (@ 0x400483F4) Device ID */
-} LPC_SYSCON_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- GPIO_PIN_INT -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PIN_INT)
- */
-
-typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
- __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */
- __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
- __IO uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
- __IO uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
- __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
- __IO uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
- __IO uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
- __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
- __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
- __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */
-} LPC_GPIO_PIN_INT_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- GPIO_GROUP_INT0/1 -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_GROUP_INT0)
- */
-
-typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
- __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
- __I uint32_t RESERVED0[7];
- __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
- __I uint32_t RESERVED1[6];
- __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
-} LPC_GPIO_GROUP_INTx_Type;
-
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- USB -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC11U1x USB2.0device controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (USB)
- */
-
-typedef struct { /*!< (@ 0x40080000) USB Structure */
- __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40080000) USB Device Command/Status register */
- __IO uint32_t INFO; /*!< (@ 0x40080004) USB Info register */
- __IO uint32_t EPLISTSTART; /*!< (@ 0x40080008) USB EP Command/Status List start address */
- __IO uint32_t DATABUFSTART; /*!< (@ 0x4008000C) USB Data buffer start address */
- __IO uint32_t LPM; /*!< (@ 0x40080010) Link Power Management register */
- __IO uint32_t EPSKIP; /*!< (@ 0x40080014) USB Endpoint skip */
- __IO uint32_t EPINUSE; /*!< (@ 0x40080018) USB Endpoint Buffer in use */
- __IO uint32_t EPBUFCFG; /*!< (@ 0x4008001C) USB Endpoint Buffer Configuration register */
- __IO uint32_t INTSTAT; /*!< (@ 0x40080020) USB interrupt status register */
- __IO uint32_t INTEN; /*!< (@ 0x40080024) USB interrupt enable register */
- __IO uint32_t INTSETSTAT; /*!< (@ 0x40080028) USB set interrupt status register */
- __IO uint32_t INTROUTING; /*!< (@ 0x4008002C) USB interrupt routing register */
- __I uint32_t RESERVED0[1];
- __I uint32_t EPTOGGLE; /*!< (@ 0x40080034) USB Endpoint toggle register */
-} LPC_USB_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- GPIO_PORT -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT)
- */
-
-typedef struct {
- union {
- struct {
- __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
- __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */
- };
- __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */
- };
- __I uint32_t RESERVED0[1008];
- union {
- struct {
- __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */
- __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */
- };
- __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */
- };
- uint32_t RESERVED1[960];
- __IO uint32_t DIR[2]; /* 0x2000 */
- uint32_t RESERVED2[30];
- __IO uint32_t MASK[2]; /* 0x2080 */
- uint32_t RESERVED3[30];
- __IO uint32_t PIN[2]; /* 0x2100 */
- uint32_t RESERVED4[30];
- __IO uint32_t MPIN[2]; /* 0x2180 */
- uint32_t RESERVED5[30];
- __IO uint32_t SET[2]; /* 0x2200 */
- uint32_t RESERVED6[30];
- __O uint32_t CLR[2]; /* 0x2280 */
- uint32_t RESERVED7[30];
- __O uint32_t NOT[2]; /* 0x2300 */
-} LPC_GPIO_Type;
-
-
-#if defined ( __CC_ARM )
- #pragma no_anon_unions
-#endif
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- Peripheral memory map -----
-// ------------------------------------------------------------------------------------------------
-
-#define LPC_I2C_BASE (0x40000000)
-#define LPC_WWDT_BASE (0x40004000)
-#define LPC_USART_BASE (0x40008000)
-#define LPC_CT16B0_BASE (0x4000C000)
-#define LPC_CT16B1_BASE (0x40010000)
-#define LPC_CT32B0_BASE (0x40014000)
-#define LPC_CT32B1_BASE (0x40018000)
-#define LPC_ADC_BASE (0x4001C000)
-#define LPC_PMU_BASE (0x40038000)
-#define LPC_FLASHCTRL_BASE (0x4003C000)
-#define LPC_SSP0_BASE (0x40040000)
-#define LPC_SSP1_BASE (0x40058000)
-#define LPC_IOCON_BASE (0x40044000)
-#define LPC_SYSCON_BASE (0x40048000)
-#define LPC_GPIO_PIN_INT_BASE (0x4004C000)
-#define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)
-#define LPC_GPIO_GROUP_INT1_BASE (0x40060000)
-#define LPC_USB_BASE (0x40080000)
-#define LPC_GPIO_BASE (0x50000000)
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- Peripheral declaration -----
-// ------------------------------------------------------------------------------------------------
-
-#define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)
-#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
-#define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)
-#define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE)
-#define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE)
-#define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE)
-#define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE)
-#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
-#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
-#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
-#define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE)
-#define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE)
-#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
-#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
-#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
-#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT0_BASE)
-#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT1_BASE)
-#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
-#define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)
-
-
-/** @} */ /* End of group Device_Peripheral_Registers */
-/** @} */ /* End of group (null) */
-/** @} */ /* End of group LPC11Uxx */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif // __LPC11UXX_H__
--- a/TARGET_GHI_MBUINO/TARGET_NXP/TARGET_LPC11UXX/PeripheralPins.h Fri Aug 15 15:28:31 2014 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,43 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - -/************ADC***************/ -extern const PinMap PinMap_ADC[]; - -/************I2C***************/ -extern const PinMap PinMap_I2C_SDA[]; -extern const PinMap PinMap_I2C_SCL[]; - -/************UART***************/ -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; - -/************SPI***************/ -extern const PinMap PinMap_SPI_SCLK[]; -extern const PinMap PinMap_SPI_MOSI[]; -extern const PinMap PinMap_SPI_MISO[]; -extern const PinMap PinMap_SPI_SSEL[]; - -/************PWM***************/ -extern const PinMap PinMap_PWM[]; - -#endif
--- a/TARGET_GHI_MBUINO/TARGET_NXP/TARGET_LPC11UXX/PortNames.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- Port0 = 0,
- Port1 = 1
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/TARGET_GHI_MBUINO/TARGET_NXP/TARGET_LPC11UXX/TARGET_GHI_MBUINO/PeripheralNames.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,91 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- UART_0 = (int)LPC_USART_BASE
-} UARTName;
-
-typedef enum {
- I2C_0 = (int)LPC_I2C_BASE
-} I2CName;
-
-typedef enum {
- ADC0_0 = 0,
- ADC0_1,
- ADC0_2,
- ADC0_3,
- ADC0_4,
- ADC0_5,
- ADC0_6,
- ADC0_7
-} ADCName;
-
-typedef enum {
- SPI_0 = (int)LPC_SSP0_BASE,
- SPI_1 = (int)LPC_SSP1_BASE
-} SPIName;
-
-typedef enum {
- PWM_1 = 0,
- PWM_2,
- PWM_3,
- PWM_4,
- PWM_5,
- PWM_6,
- PWM_7,
- PWM_8,
- PWM_9,
- PWM_10,
- PWM_11,
- PWM_12,
- PWM_13
-} PWMName;
-
-#define STDIO_UART_TX USBTX
-#define STDIO_UART_RX USBRX
-#define STDIO_UART UART_0
-
-// Default peripherals
-#define MBED_SPI0 P0_9, P0_8, P0_6, P0_2 // MOSI, MISO, CLK, SEL
-#define MBED_SPI1 P0_21, P0_22, P1_15, P01_19 // MOSI, MISO, CLK, SEL
-
-#define MBED_UART0 USBTX, USBRX
-#define MBED_UARTUSB USBTX, USBRX
-
-#define MBED_I2C0 P0_5, P0_4
-
-#define MBED_ANALOGIN0 P0_11
-#define MBED_ANALOGIN1 P0_12
-#define MBED_ANALOGIN2 P0_13
-#define MBED_ANALOGIN3 P0_14
-#define MBED_ANALOGIN4 P0_15
-#define MBED_ANALOGIN5 P0_16
-#define MBED_ANALOGIN6 P0_22
-#define MBED_ANALOGIN7 P0_23
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/TARGET_GHI_MBUINO/TARGET_NXP/TARGET_LPC11UXX/TARGET_GHI_MBUINO/PinNames.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,105 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
-#define PORT_SHIFT 5
-
-typedef enum {
- // LPC11U24 HVQFN33 Pin Names
- P0_0 = 0,
- P0_1 = 1,
- P0_2 = 2,
- P0_3 = 3,
- P0_4 = 4,
- P0_5 = 5,
- P0_6 = 6,
- P0_7 = 7,
- P0_8 = 8,
- P0_9 = 9,
- P0_10 = 10,
- P0_11 = 11,
- P0_12 = 12,
- P0_13 = 13,
- P0_14 = 14,
- P0_15 = 15,
- P0_16 = 16,
- P0_17 = 17,
- P0_18 = 18,
- P0_19 = 19,
- P0_20 = 20,
- P0_21 = 21,
- P0_22 = 22,
- P0_23 = 23,
-
- P1_15 = 47,
- P1_19 = 51,
-
- // Other mbed Pin Names
- LED1 = P0_7,
- LED2 = P0_8,
- LED3 = P0_2,
- LED4 = P0_20,
- LED5 = P1_19,
- LED6 = P0_17,
- LED7 = P0_23,
-
- USBTX = P0_19,
- USBRX = P0_18,
-
- I2C_SCL = P0_4,
- I2C_SDA = P0_5,
-
- // Not connected
- NC = (int)0xFFFFFFFF,
-} PinName;
-
-typedef enum {
- CHANNEL0 = FLEX_INT0_IRQn,
- CHANNEL1 = FLEX_INT1_IRQn,
- CHANNEL2 = FLEX_INT2_IRQn,
- CHANNEL3 = FLEX_INT3_IRQn,
- CHANNEL4 = FLEX_INT4_IRQn,
- CHANNEL5 = FLEX_INT5_IRQn,
- CHANNEL6 = FLEX_INT6_IRQn,
- CHANNEL7 = FLEX_INT7_IRQn
-} Channel;
-
-typedef enum {
- PullUp = 2,
- PullDown = 1,
- PullNone = 0,
- Repeater = 3,
- OpenDrain = 4,
- PullDefault = PullDown
-} PinMode;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/TARGET_GHI_MBUINO/TARGET_NXP/TARGET_LPC11UXX/TARGET_GHI_MBUINO/device.h Fri Aug 15 15:28:31 2014 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,59 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_PORTIN 1 -#define DEVICE_PORTOUT 1 -#define DEVICE_PORTINOUT 1 - -#define DEVICE_INTERRUPTIN 1 - -#define DEVICE_ANALOGIN 1 -#define DEVICE_ANALOGOUT 0 - -#define DEVICE_SERIAL 1 - -#define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 1 - -#define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 1 - -#define DEVICE_CAN 0 - -#define DEVICE_RTC 0 - -#define DEVICE_ETHERNET 0 - -#define DEVICE_PWMOUT 1 - -#define DEVICE_SEMIHOST 1 -#define DEVICE_LOCALFILESYSTEM 1 -#define DEVICE_ID_LENGTH 32 -#define DEVICE_MAC_OFFSET 20 - -#define DEVICE_SLEEP 1 - -#define DEVICE_DEBUG_AWARENESS 0 - -#define DEVICE_STDIO_MESSAGES 1 - -#define DEVICE_ERROR_PATTERN 1 - -#include "objects.h" - -#endif
--- a/TARGET_GHI_MBUINO/TARGET_NXP/TARGET_LPC11UXX/gpio_object.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,52 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#include "mbed_assert.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
- PinName pin;
- uint32_t mask;
-
- __IO uint32_t *reg_dir;
- __IO uint32_t *reg_set;
- __IO uint32_t *reg_clr;
- __I uint32_t *reg_in;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value) {
- MBED_ASSERT(obj->pin != (PinName)NC);
- if (value)
- *obj->reg_set = obj->mask;
- else
- *obj->reg_clr = obj->mask;
-}
-
-static inline int gpio_read(gpio_t *obj) {
- MBED_ASSERT(obj->pin != (PinName)NC);
- return ((*obj->reg_in & obj->mask) ? 1 : 0);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/TARGET_GHI_MBUINO/TARGET_NXP/TARGET_LPC11UXX/objects.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,66 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
- uint32_t ch;
-};
-
-struct port_s {
- __IO uint32_t *reg_dir;
- __IO uint32_t *reg_mpin;
- PortName port;
- uint32_t mask;
-};
-
-struct pwmout_s {
- PWMName pwm;
-};
-
-struct serial_s {
- LPC_USART_Type *uart;
- int index;
-};
-
-struct analogin_s {
- ADCName adc;
-};
-
-struct i2c_s {
- LPC_I2C_Type *i2c;
-};
-
-struct spi_s {
- LPC_SSPx_Type *spi;
-};
-
-#include "gpio_object.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/TARGET_GHI_MBUINO/TOOLCHAIN_ARM_MICRO/LPC11U24.sct Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,17 +0,0 @@
-
-LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
- ER_IROM1 0x00000000 0x8000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
- ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
- ; 6KB - 0xC0 = 0x1740
- RW_IRAM1 0x100000C0 0x1740 {
- .ANY (+RW +ZI)
- }
- RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
- .ANY (USBRAM)
- }
-}
-
Binary file TARGET_GHI_MBUINO/TOOLCHAIN_ARM_MICRO/board.o has changed
Binary file TARGET_GHI_MBUINO/TOOLCHAIN_ARM_MICRO/cmsis_nvic.o has changed
Binary file TARGET_GHI_MBUINO/TOOLCHAIN_ARM_MICRO/mbed.ar has changed
Binary file TARGET_GHI_MBUINO/TOOLCHAIN_ARM_MICRO/retarget.o has changed
Binary file TARGET_GHI_MBUINO/TOOLCHAIN_ARM_MICRO/startup_LPC11xx.o has changed
Binary file TARGET_GHI_MBUINO/TOOLCHAIN_ARM_MICRO/sys.o has changed
Binary file TARGET_GHI_MBUINO/TOOLCHAIN_ARM_MICRO/system_LPC11Uxx.o has changed
--- a/TARGET_GHI_MBUINO/TOOLCHAIN_ARM_STD/LPC11U24.sct Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,17 +0,0 @@
-
-LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
- ER_IROM1 0x00000000 0x8000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
- ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
- ; 6KB - 0xC0 = 0x1740
- RW_IRAM1 0x100000C0 0x1740 {
- .ANY (+RW +ZI)
- }
- RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
- .ANY (USBRAM)
- }
-}
-
Binary file TARGET_GHI_MBUINO/TOOLCHAIN_ARM_STD/board.o has changed
Binary file TARGET_GHI_MBUINO/TOOLCHAIN_ARM_STD/cmsis_nvic.o has changed
Binary file TARGET_GHI_MBUINO/TOOLCHAIN_ARM_STD/mbed.ar has changed
Binary file TARGET_GHI_MBUINO/TOOLCHAIN_ARM_STD/retarget.o has changed
Binary file TARGET_GHI_MBUINO/TOOLCHAIN_ARM_STD/startup_LPC11xx.o has changed
Binary file TARGET_GHI_MBUINO/TOOLCHAIN_ARM_STD/sys.o has changed
Binary file TARGET_GHI_MBUINO/TOOLCHAIN_ARM_STD/system_LPC11Uxx.o has changed
--- a/TARGET_GHI_MBUINO/TOOLCHAIN_GCC_ARM/LPC11U24.ld Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,154 +0,0 @@
-/* Linker script for mbed LPC1768 */
-
-/* Linker script to configure memory regions. */
-MEMORY
-{
- FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K
- RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1740
- USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800
-}
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- * Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- * __exidx_start
- * __exidx_end
- * __etext
- * __data_start__
- * __preinit_array_start
- * __preinit_array_end
- * __init_array_start
- * __init_array_end
- * __fini_array_start
- * __fini_array_end
- * __data_end__
- * __bss_start__
- * __bss_end__
- * __end__
- * end
- * __HeapLimit
- * __StackLimit
- * __StackTop
- * __stack
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
- .text :
- {
- KEEP(*(.isr_vector))
- *(.text.Reset_Handler)
- *(.text.SystemInit)
-
- /* Only vectors and code running at reset are safe to be in first 512
- bytes since RAM can be mapped into this area for RAM based interrupt
- vectors. */
- . = 0x00000200;
- *(.text*)
-
- KEEP(*(.init))
- KEEP(*(.fini))
-
- /* .ctors */
- *crtbegin.o(.ctors)
- *crtbegin?.o(.ctors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
- *(SORT(.ctors.*))
- *(.ctors)
-
- /* .dtors */
- *crtbegin.o(.dtors)
- *crtbegin?.o(.dtors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
- *(SORT(.dtors.*))
- *(.dtors)
-
- *(.rodata*)
-
- KEEP(*(.eh_frame*))
- } > FLASH
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > FLASH
-
- __exidx_start = .;
- .ARM.exidx :
- {
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- } > FLASH
- __exidx_end = .;
-
- __etext = .;
-
- .data : AT (__etext)
- {
- __data_start__ = .;
- *(vtable)
- *(.data*)
-
- . = ALIGN(4);
- /* preinit data */
- PROVIDE (__preinit_array_start = .);
- KEEP(*(.preinit_array))
- PROVIDE (__preinit_array_end = .);
-
- . = ALIGN(4);
- /* init data */
- PROVIDE (__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE (__init_array_end = .);
-
-
- . = ALIGN(4);
- /* finit data */
- PROVIDE (__fini_array_start = .);
- KEEP(*(SORT(.fini_array.*)))
- KEEP(*(.fini_array))
- PROVIDE (__fini_array_end = .);
-
- . = ALIGN(4);
- /* All data end */
- __data_end__ = .;
-
- } > RAM
-
- .bss :
- {
- __bss_start__ = .;
- *(.bss*)
- *(COMMON)
- __bss_end__ = .;
- } > RAM
-
- .heap :
- {
- __end__ = .;
- end = __end__;
- *(.heap*)
- __HeapLimit = .;
- } > RAM
-
- /* .stack_dummy section doesn't contains any symbols. It is only
- * used for linker to calculate size of stack sections, and assign
- * values to stack symbols later */
- .stack_dummy :
- {
- *(.stack)
- } > RAM
-
- /* Set stack top to end of RAM, and stack limit move down by
- * size of stack_dummy section */
- __StackTop = ORIGIN(RAM) + LENGTH(RAM);
- __StackLimit = __StackTop - SIZEOF(.stack_dummy);
- PROVIDE(__stack = __StackTop);
-
- /* Check if data + heap + stack exceeds RAM limit */
- ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}
Binary file TARGET_GHI_MBUINO/TOOLCHAIN_GCC_ARM/board.o has changed
Binary file TARGET_GHI_MBUINO/TOOLCHAIN_GCC_ARM/cmsis_nvic.o has changed
Binary file TARGET_GHI_MBUINO/TOOLCHAIN_GCC_ARM/libmbed.a has changed
Binary file TARGET_GHI_MBUINO/TOOLCHAIN_GCC_ARM/retarget.o has changed
Binary file TARGET_GHI_MBUINO/TOOLCHAIN_GCC_ARM/startup_LPC11xx.o has changed
Binary file TARGET_GHI_MBUINO/TOOLCHAIN_GCC_ARM/system_LPC11Uxx.o has changed
--- a/TARGET_GHI_MBUINO/cmsis.h Fri Aug 15 15:28:31 2014 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,13 +0,0 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in LPC11U24 specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "LPC11Uxx.h" -#include "cmsis_nvic.h" - -#endif
--- a/TARGET_GHI_MBUINO/cmsis_nvic.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,26 +0,0 @@
-/* mbed Microcontroller Library - cmsis_nvic
- * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
- *
- * CMSIS-style functionality to support dynamic vectors
- */
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-#include "cmsis.h"
-
-#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
-#define NVIC_USER_IRQ_OFFSET 16
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/TARGET_GHI_MBUINO/core_cm0.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,682 +0,0 @@
-/**************************************************************************//**
- * @file core_cm0.h
- * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version V3.20
- * @date 25. February 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM0_H_GENERIC
-#define __CORE_CM0_H_GENERIC
-
-/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M0
- @{
- */
-
-/* CMSIS CM0 definitions */
-#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
-#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
-#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
- __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x00) /*!< Cortex-M Core */
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
- #define __STATIC_INLINE static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
-*/
-#define __FPU_USED 0
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-#endif
-
-#include <stdint.h> /* standard types definitions */
-#include <core_cmInstr.h> /* Core Instruction Access */
-#include <core_cmFunc.h> /* Core Function Access */
-
-#endif /* __CORE_CM0_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0_H_DEPENDANT
-#define __CORE_CM0_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM0_REV
- #define __CM0_REV 0x0000
- #warning "__CM0_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 2
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/*@} end of group Cortex_M0 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/** \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
-#else
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
-#endif
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-
-/** \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-
-/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
-#else
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
-#endif
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-
-/** \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[31];
- __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[31];
- __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[31];
- __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[31];
- uint32_t RESERVED4[64];
- __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
-} NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/** \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- uint32_t RESERVED0;
- __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- uint32_t RESERVED1;
- __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
- __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/** \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
- are only accessible over DAP and not via processor. Therefore
- they are not covered by the Cortex-M0 header file.
- @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Cortex-M0 Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
-#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
-#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
-
-
-/** \brief Enable External Interrupt
-
- The function enables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief Disable External Interrupt
-
- The function disables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief Get Pending Interrupt
-
- The function reads the pending register in the NVIC and returns the pending bit
- for the specified interrupt.
-
- \param [in] IRQn Interrupt number.
-
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-
-/** \brief Set Pending Interrupt
-
- The function sets the pending bit of an external interrupt.
-
- \param [in] IRQn Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief Clear Pending Interrupt
-
- The function clears the pending bit of an external interrupt.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief Set Interrupt Priority
-
- The function sets the priority of an interrupt.
-
- \note The priority cannot be set for every core interrupt.
-
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if(IRQn < 0) {
- SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
- else {
- NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-}
-
-
-/** \brief Get Interrupt Priority
-
- The function reads the priority of an interrupt. The interrupt
- number can be positive to specify an external (device specific)
- interrupt, or negative to specify an internal (core) interrupt.
-
-
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority. Value is aligned automatically to the implemented
- priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if(IRQn < 0) {
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
- else {
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
-}
-
-
-/** \brief System Reset
-
- The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- SCB_AIRCR_SYSRESETREQ_Msk);
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief System Tick Configuration
-
- The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
-
- \param [in] ticks Number of ticks between two interrupts.
-
- \return 0 Function succeeded.
- \return 1 Function failed.
-
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
-
- SysTick->LOAD = ticks - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#endif /* __CORE_CM0_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif
--- a/TARGET_GHI_MBUINO/core_cm0plus.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,793 +0,0 @@
-/**************************************************************************//**
- * @file core_cm0plus.h
- * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
- * @version V3.20
- * @date 25. February 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM0PLUS_H_GENERIC
-#define __CORE_CM0PLUS_H_GENERIC
-
-/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex-M0+
- @{
- */
-
-/* CMSIS CM0P definitions */
-#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
-#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
-#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
- __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x00) /*!< Cortex-M Core */
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
- #define __STATIC_INLINE static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
-*/
-#define __FPU_USED 0
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-#endif
-
-#include <stdint.h> /* standard types definitions */
-#include <core_cmInstr.h> /* Core Instruction Access */
-#include <core_cmFunc.h> /* Core Function Access */
-
-#endif /* __CORE_CM0PLUS_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0PLUS_H_DEPENDANT
-#define __CORE_CM0PLUS_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM0PLUS_REV
- #define __CM0PLUS_REV 0x0000
- #warning "__CM0PLUS_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __VTOR_PRESENT
- #define __VTOR_PRESENT 0
- #warning "__VTOR_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 2
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/*@} end of group Cortex-M0+ */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core MPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/** \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
-#else
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
-#endif
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-
-/** \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-
-/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
-#else
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
-#endif
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-
-/** \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[31];
- __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[31];
- __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[31];
- __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[31];
- uint32_t RESERVED4[64];
- __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
-} NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/** \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
-#if (__VTOR_PRESENT == 1)
- __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
-#else
- uint32_t RESERVED0;
-#endif
- __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- uint32_t RESERVED1;
- __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
- __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if (__VTOR_PRESENT == 1)
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/** \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/** \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
- are only accessible over DAP and not via processor. Therefore
- they are not covered by the Cortex-M0 header file.
- @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Cortex-M0+ Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-
-#if (__MPU_PRESENT == 1)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
-#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
-#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
-
-
-/** \brief Enable External Interrupt
-
- The function enables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief Disable External Interrupt
-
- The function disables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief Get Pending Interrupt
-
- The function reads the pending register in the NVIC and returns the pending bit
- for the specified interrupt.
-
- \param [in] IRQn Interrupt number.
-
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-
-/** \brief Set Pending Interrupt
-
- The function sets the pending bit of an external interrupt.
-
- \param [in] IRQn Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief Clear Pending Interrupt
-
- The function clears the pending bit of an external interrupt.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief Set Interrupt Priority
-
- The function sets the priority of an interrupt.
-
- \note The priority cannot be set for every core interrupt.
-
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if(IRQn < 0) {
- SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
- else {
- NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-}
-
-
-/** \brief Get Interrupt Priority
-
- The function reads the priority of an interrupt. The interrupt
- number can be positive to specify an external (device specific)
- interrupt, or negative to specify an internal (core) interrupt.
-
-
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority. Value is aligned automatically to the implemented
- priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if(IRQn < 0) {
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
- else {
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
-}
-
-
-/** \brief System Reset
-
- The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- SCB_AIRCR_SYSRESETREQ_Msk);
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief System Tick Configuration
-
- The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
-
- \param [in] ticks Number of ticks between two interrupts.
-
- \return 0 Function succeeded.
- \return 1 Function failed.
-
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
-
- SysTick->LOAD = ticks - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#endif /* __CORE_CM0PLUS_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif
--- a/TARGET_GHI_MBUINO/core_cm3.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1627 +0,0 @@
-/**************************************************************************//**
- * @file core_cm3.h
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version V3.20
- * @date 25. February 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM3_H_GENERIC
-#define __CORE_CM3_H_GENERIC
-
-/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M3
- @{
- */
-
-/* CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
- __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x03) /*!< Cortex-M Core */
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TMS470__ )
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
- #define __STATIC_INLINE static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
-*/
-#define __FPU_USED 0
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TMS470__ )
- #if defined __TI__VFP_SUPPORT____
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-#endif
-
-#include <stdint.h> /* standard types definitions */
-#include <core_cmInstr.h> /* Core Instruction Access */
-#include <core_cmFunc.h> /* Core Function Access */
-
-#endif /* __CORE_CM3_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM3_H_DEPENDANT
-#define __CORE_CM3_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM3_REV
- #define __CM3_REV 0x0200
- #warning "__CM3_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 4
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/*@} end of group Cortex_M3 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/** \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
-#else
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
-#endif
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-
-/** \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-
-/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
-#else
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
-#endif
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-
-/** \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[24];
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[24];
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[24];
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[24];
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[56];
- __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644];
- __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/** \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- uint32_t RESERVED0[5];
- __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#if (__CM3_REV < 0x0201) /* core r2p1 */
-#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-#else
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/** \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1];
- __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
- __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
-#else
- uint32_t RESERVED1[1];
-#endif
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/** \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __O union
- {
- __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864];
- __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15];
- __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15];
- __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29];
- __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
- __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43];
- __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[6];
- __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
- __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED0[1];
- __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
- __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED1[1];
- __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
- __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED2[1];
- __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
- __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/** \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2];
- __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55];
- __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131];
- __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759];
- __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
- __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1];
- __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39];
- __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8];
- __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/** \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
- __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
- __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
- __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
- __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
- __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
- __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/** \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if (__MPU_PRESENT == 1)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-/** \brief Set Priority Grouping
-
- The function sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-
-/** \brief Get Priority Grouping
-
- The function reads the priority grouping field from the NVIC Interrupt Controller.
-
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
-}
-
-
-/** \brief Enable External Interrupt
-
- The function enables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
-}
-
-
-/** \brief Disable External Interrupt
-
- The function disables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-
-/** \brief Get Pending Interrupt
-
- The function reads the pending register in the NVIC and returns the pending bit
- for the specified interrupt.
-
- \param [in] IRQn Interrupt number.
-
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-
-/** \brief Set Pending Interrupt
-
- The function sets the pending bit of an external interrupt.
-
- \param [in] IRQn Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-
-/** \brief Clear Pending Interrupt
-
- The function clears the pending bit of an external interrupt.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief Get Active Interrupt
-
- The function reads the active register in NVIC and returns the active bit.
-
- \param [in] IRQn Interrupt number.
-
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
-}
-
-
-/** \brief Set Interrupt Priority
-
- The function sets the priority of an interrupt.
-
- \note The priority cannot be set for every core interrupt.
-
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if(IRQn < 0) {
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
- else {
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
-}
-
-
-/** \brief Get Interrupt Priority
-
- The function reads the priority of an interrupt. The interrupt
- number can be positive to specify an external (device specific)
- interrupt, or negative to specify an internal (core) interrupt.
-
-
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority. Value is aligned automatically to the implemented
- priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if(IRQn < 0) {
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
- else {
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
-}
-
-
-/** \brief Encode Priority
-
- The function encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
-
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
- return (
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
- );
-}
-
-
-/** \brief Decode Priority
-
- The function decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
-
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
-}
-
-
-/** \brief System Reset
-
- The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief System Tick Configuration
-
- The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
-
- \param [in] ticks Number of ticks between two interrupts.
-
- \return 0 Function succeeded.
- \return 1 Function failed.
-
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
-
- SysTick->LOAD = ticks - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions ITM Functions
- \brief Functions that access the ITM debug interface.
- @{
- */
-
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/** \brief ITM Send Character
-
- The function transmits a character via the ITM channel 0, and
- \li Just returns when no debugger is connected that has booked the output.
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-
- \param [in] ch Character to transmit.
-
- \returns Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
- (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0].u32 == 0);
- ITM->PORT[0].u8 = (uint8_t) ch;
- }
- return (ch);
-}
-
-
-/** \brief ITM Receive Character
-
- The function inputs a character via the external variable \ref ITM_RxBuffer.
-
- \return Received character.
- \return -1 No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
- int32_t ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/** \brief ITM Check Character
-
- The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
- \return 0 No character available.
- \return 1 Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
- return (0); /* no character available */
- } else {
- return (1); /* character available */
- }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-#endif /* __CORE_CM3_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif
--- a/TARGET_GHI_MBUINO/core_cm4.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1772 +0,0 @@
-/**************************************************************************//**
- * @file core_cm4.h
- * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version V3.20
- * @date 25. February 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM4_H_GENERIC
-#define __CORE_CM4_H_GENERIC
-
-/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M4
- @{
- */
-
-/* CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
-#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
-#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
- __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x04) /*!< Cortex-M Core */
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TMS470__ )
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
- #define __STATIC_INLINE static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __TMS470__ )
- #if defined __TI_VFP_SUPPORT__
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-#endif
-
-#include <stdint.h> /* standard types definitions */
-#include <core_cmInstr.h> /* Core Instruction Access */
-#include <core_cmFunc.h> /* Core Function Access */
-#include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
-
-#endif /* __CORE_CM4_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM4_H_DEPENDANT
-#define __CORE_CM4_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM4_REV
- #define __CM4_REV 0x0000
- #warning "__CM4_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __FPU_PRESENT
- #define __FPU_PRESENT 0
- #warning "__FPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 4
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/*@} end of group Cortex_M4 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- - Core FPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/** \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
-#else
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
-#endif
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-
-/** \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-
-/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
-#else
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
-#endif
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-
-/** \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[24];
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[24];
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[24];
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[24];
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[56];
- __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644];
- __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/** \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- uint32_t RESERVED0[5];
- __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/** \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1];
- __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
- __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
-#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
-
-#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
-#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/** \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __O union
- {
- __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864];
- __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15];
- __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15];
- __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29];
- __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
- __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43];
- __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[6];
- __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
- __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED0[1];
- __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
- __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED1[1];
- __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
- __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED2[1];
- __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
- __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/** \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2];
- __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55];
- __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131];
- __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759];
- __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
- __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1];
- __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39];
- __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8];
- __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/** \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
- __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
- __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
- __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
- __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
- __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
- __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if (__FPU_PRESENT == 1)
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_FPU Floating Point Unit (FPU)
- \brief Type definitions for the Floating Point Unit (FPU)
- @{
- */
-
-/** \brief Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
- uint32_t RESERVED0[1];
- __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
- __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
- __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
- __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
- __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register */
-#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register */
-#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register */
-#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 */
-#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 */
-#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-#endif
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/** \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Cortex-M4 Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if (__MPU_PRESENT == 1)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-#if (__FPU_PRESENT == 1)
- #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
- #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-/** \brief Set Priority Grouping
-
- The function sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-
-/** \brief Get Priority Grouping
-
- The function reads the priority grouping field from the NVIC Interrupt Controller.
-
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
-}
-
-
-/** \brief Enable External Interrupt
-
- The function enables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
- NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
-}
-
-
-/** \brief Disable External Interrupt
-
- The function disables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-
-/** \brief Get Pending Interrupt
-
- The function reads the pending register in the NVIC and returns the pending bit
- for the specified interrupt.
-
- \param [in] IRQn Interrupt number.
-
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-
-/** \brief Set Pending Interrupt
-
- The function sets the pending bit of an external interrupt.
-
- \param [in] IRQn Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-
-/** \brief Clear Pending Interrupt
-
- The function clears the pending bit of an external interrupt.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief Get Active Interrupt
-
- The function reads the active register in NVIC and returns the active bit.
-
- \param [in] IRQn Interrupt number.
-
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
-}
-
-
-/** \brief Set Interrupt Priority
-
- The function sets the priority of an interrupt.
-
- \note The priority cannot be set for every core interrupt.
-
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if(IRQn < 0) {
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
- else {
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
-}
-
-
-/** \brief Get Interrupt Priority
-
- The function reads the priority of an interrupt. The interrupt
- number can be positive to specify an external (device specific)
- interrupt, or negative to specify an internal (core) interrupt.
-
-
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority. Value is aligned automatically to the implemented
- priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if(IRQn < 0) {
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
- else {
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
-}
-
-
-/** \brief Encode Priority
-
- The function encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
-
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
- return (
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
- );
-}
-
-
-/** \brief Decode Priority
-
- The function decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
-
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
-}
-
-
-/** \brief System Reset
-
- The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief System Tick Configuration
-
- The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
-
- \param [in] ticks Number of ticks between two interrupts.
-
- \return 0 Function succeeded.
- \return 1 Function failed.
-
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
-
- SysTick->LOAD = ticks - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions ITM Functions
- \brief Functions that access the ITM debug interface.
- @{
- */
-
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/** \brief ITM Send Character
-
- The function transmits a character via the ITM channel 0, and
- \li Just returns when no debugger is connected that has booked the output.
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-
- \param [in] ch Character to transmit.
-
- \returns Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
- (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0].u32 == 0);
- ITM->PORT[0].u8 = (uint8_t) ch;
- }
- return (ch);
-}
-
-
-/** \brief ITM Receive Character
-
- The function inputs a character via the external variable \ref ITM_RxBuffer.
-
- \return Received character.
- \return -1 No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
- int32_t ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/** \brief ITM Check Character
-
- The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
- \return 0 No character available.
- \return 1 Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
- return (0); /* no character available */
- } else {
- return (1); /* character available */
- }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-#endif /* __CORE_CM4_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif
--- a/TARGET_GHI_MBUINO/core_cm4_simd.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,673 +0,0 @@
-/**************************************************************************//**
- * @file core_cm4_simd.h
- * @brief CMSIS Cortex-M4 SIMD Header File
- * @version V3.20
- * @date 25. February 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM4_SIMD_H
-#define __CORE_CM4_SIMD_H
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- ******************************************************************************/
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
- Access to dedicated SIMD instructions
- @{
-*/
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-#define __SADD8 __sadd8
-#define __QADD8 __qadd8
-#define __SHADD8 __shadd8
-#define __UADD8 __uadd8
-#define __UQADD8 __uqadd8
-#define __UHADD8 __uhadd8
-#define __SSUB8 __ssub8
-#define __QSUB8 __qsub8
-#define __SHSUB8 __shsub8
-#define __USUB8 __usub8
-#define __UQSUB8 __uqsub8
-#define __UHSUB8 __uhsub8
-#define __SADD16 __sadd16
-#define __QADD16 __qadd16
-#define __SHADD16 __shadd16
-#define __UADD16 __uadd16
-#define __UQADD16 __uqadd16
-#define __UHADD16 __uhadd16
-#define __SSUB16 __ssub16
-#define __QSUB16 __qsub16
-#define __SHSUB16 __shsub16
-#define __USUB16 __usub16
-#define __UQSUB16 __uqsub16
-#define __UHSUB16 __uhsub16
-#define __SASX __sasx
-#define __QASX __qasx
-#define __SHASX __shasx
-#define __UASX __uasx
-#define __UQASX __uqasx
-#define __UHASX __uhasx
-#define __SSAX __ssax
-#define __QSAX __qsax
-#define __SHSAX __shsax
-#define __USAX __usax
-#define __UQSAX __uqsax
-#define __UHSAX __uhsax
-#define __USAD8 __usad8
-#define __USADA8 __usada8
-#define __SSAT16 __ssat16
-#define __USAT16 __usat16
-#define __UXTB16 __uxtb16
-#define __UXTAB16 __uxtab16
-#define __SXTB16 __sxtb16
-#define __SXTAB16 __sxtab16
-#define __SMUAD __smuad
-#define __SMUADX __smuadx
-#define __SMLAD __smlad
-#define __SMLADX __smladx
-#define __SMLALD __smlald
-#define __SMLALDX __smlaldx
-#define __SMUSD __smusd
-#define __SMUSDX __smusdx
-#define __SMLSD __smlsd
-#define __SMLSDX __smlsdx
-#define __SMLSLD __smlsld
-#define __SMLSLDX __smlsldx
-#define __SEL __sel
-#define __QADD __qadd
-#define __QSUB __qsub
-
-#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
- ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
-
-#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
- ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
-
-#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
- ((int64_t)(ARG3) << 32) ) >> 32))
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-#include <cmsis_iar.h>
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-#include <cmsis_ccs.h>
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
-{
- uint32_t result;
-
- __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
-{
- uint32_t result;
-
- __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#define __SMLALD(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
- (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-#define __SMLALDX(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
- (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#define __SMLSLD(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
- (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-#define __SMLSLDX(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
- (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
- __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
- __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
- if (ARG3 == 0) \
- __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
- else \
- __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
- __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
- int32_t result;
-
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-/* not yet supported */
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-#endif
-
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CORE_CM4_SIMD_H */
-
-#ifdef __cplusplus
-}
-#endif
--- a/TARGET_GHI_MBUINO/core_cmFunc.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,636 +0,0 @@
-/**************************************************************************//**
- * @file core_cmFunc.h
- * @brief CMSIS Cortex-M Core Function Access Header File
- * @version V3.20
- * @date 25. February 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CMFUNC_H
-#define __CORE_CMFUNC_H
-
-
-/* ########################### Core Function Access ########################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
- @{
- */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* intrinsic void __enable_irq(); */
-/* intrinsic void __disable_irq(); */
-
-/** \brief Get Control Register
-
- This function returns the content of the Control Register.
-
- \return Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
- register uint32_t __regControl __ASM("control");
- return(__regControl);
-}
-
-
-/** \brief Set Control Register
-
- This function writes the given value to the Control Register.
-
- \param [in] control Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
- register uint32_t __regControl __ASM("control");
- __regControl = control;
-}
-
-
-/** \brief Get IPSR Register
-
- This function returns the content of the IPSR Register.
-
- \return IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
- register uint32_t __regIPSR __ASM("ipsr");
- return(__regIPSR);
-}
-
-
-/** \brief Get APSR Register
-
- This function returns the content of the APSR Register.
-
- \return APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
- register uint32_t __regAPSR __ASM("apsr");
- return(__regAPSR);
-}
-
-
-/** \brief Get xPSR Register
-
- This function returns the content of the xPSR Register.
-
- \return xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
- register uint32_t __regXPSR __ASM("xpsr");
- return(__regXPSR);
-}
-
-
-/** \brief Get Process Stack Pointer
-
- This function returns the current value of the Process Stack Pointer (PSP).
-
- \return PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
- register uint32_t __regProcessStackPointer __ASM("psp");
- return(__regProcessStackPointer);
-}
-
-
-/** \brief Set Process Stack Pointer
-
- This function assigns the given value to the Process Stack Pointer (PSP).
-
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- register uint32_t __regProcessStackPointer __ASM("psp");
- __regProcessStackPointer = topOfProcStack;
-}
-
-
-/** \brief Get Main Stack Pointer
-
- This function returns the current value of the Main Stack Pointer (MSP).
-
- \return MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
- register uint32_t __regMainStackPointer __ASM("msp");
- return(__regMainStackPointer);
-}
-
-
-/** \brief Set Main Stack Pointer
-
- This function assigns the given value to the Main Stack Pointer (MSP).
-
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
- register uint32_t __regMainStackPointer __ASM("msp");
- __regMainStackPointer = topOfMainStack;
-}
-
-
-/** \brief Get Priority Mask
-
- This function returns the current state of the priority mask bit from the Priority Mask Register.
-
- \return Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
- register uint32_t __regPriMask __ASM("primask");
- return(__regPriMask);
-}
-
-
-/** \brief Set Priority Mask
-
- This function assigns the given value to the Priority Mask Register.
-
- \param [in] priMask Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
- register uint32_t __regPriMask __ASM("primask");
- __regPriMask = (priMask);
-}
-
-
-#if (__CORTEX_M >= 0x03)
-
-/** \brief Enable FIQ
-
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq __enable_fiq
-
-
-/** \brief Disable FIQ
-
- This function disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq __disable_fiq
-
-
-/** \brief Get Base Priority
-
- This function returns the current value of the Base Priority register.
-
- \return Base Priority register value
- */
-__STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
- register uint32_t __regBasePri __ASM("basepri");
- return(__regBasePri);
-}
-
-
-/** \brief Set Base Priority
-
- This function assigns the given value to the Base Priority register.
-
- \param [in] basePri Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
- register uint32_t __regBasePri __ASM("basepri");
- __regBasePri = (basePri & 0xff);
-}
-
-
-/** \brief Get Fault Mask
-
- This function returns the current value of the Fault Mask register.
-
- \return Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- return(__regFaultMask);
-}
-
-
-/** \brief Set Fault Mask
-
- This function assigns the given value to the Fault Mask register.
-
- \param [in] faultMask Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- __regFaultMask = (faultMask & (uint32_t)1);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if (__CORTEX_M == 0x04)
-
-/** \brief Get FPSCR
-
- This function returns the current value of the Floating Point Status/Control register.
-
- \return Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- register uint32_t __regfpscr __ASM("fpscr");
- return(__regfpscr);
-#else
- return(0);
-#endif
-}
-
-
-/** \brief Set FPSCR
-
- This function assigns the given value to the Floating Point Status/Control register.
-
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- register uint32_t __regfpscr __ASM("fpscr");
- __regfpscr = (fpscr);
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief Enable IRQ Interrupts
-
- This function enables IRQ interrupts by clearing the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
-{
- __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/** \brief Disable IRQ Interrupts
-
- This function disables IRQ interrupts by setting the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
-{
- __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/** \brief Get Control Register
-
- This function returns the content of the Control Register.
-
- \return Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Control Register
-
- This function writes the given value to the Control Register.
-
- \param [in] control Control Register value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-/** \brief Get IPSR Register
-
- This function returns the content of the IPSR Register.
-
- \return IPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Get APSR Register
-
- This function returns the content of the APSR Register.
-
- \return APSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, apsr" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Get xPSR Register
-
- This function returns the content of the xPSR Register.
-
- \return xPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Get Process Stack Pointer
-
- This function returns the current value of the Process Stack Pointer (PSP).
-
- \return PSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Process Stack Pointer
-
- This function assigns the given value to the Process Stack Pointer (PSP).
-
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
-}
-
-
-/** \brief Get Main Stack Pointer
-
- This function returns the current value of the Main Stack Pointer (MSP).
-
- \return MSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Main Stack Pointer
-
- This function assigns the given value to the Main Stack Pointer (MSP).
-
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
-}
-
-
-/** \brief Get Priority Mask
-
- This function returns the current state of the priority mask bit from the Priority Mask Register.
-
- \return Priority Mask value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Priority Mask
-
- This function assigns the given value to the Priority Mask Register.
-
- \param [in] priMask Priority Mask
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (__CORTEX_M >= 0x03)
-
-/** \brief Enable FIQ
-
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
-{
- __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/** \brief Disable FIQ
-
- This function disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
-{
- __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/** \brief Get Base Priority
-
- This function returns the current value of the Base Priority register.
-
- \return Base Priority register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Base Priority
-
- This function assigns the given value to the Base Priority register.
-
- \param [in] basePri Base Priority value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
-{
- __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
-}
-
-
-/** \brief Get Fault Mask
-
- This function returns the current value of the Fault Mask register.
-
- \return Fault Mask register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Fault Mask
-
- This function assigns the given value to the Fault Mask register.
-
- \param [in] faultMask Fault Mask value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if (__CORTEX_M == 0x04)
-
-/** \brief Get FPSCR
-
- This function returns the current value of the Floating Point Status/Control register.
-
- \return Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- uint32_t result;
-
- /* Empty asm statement works as a scheduling barrier */
- __ASM volatile ("");
- __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
- __ASM volatile ("");
- return(result);
-#else
- return(0);
-#endif
-}
-
-
-/** \brief Set FPSCR
-
- This function assigns the given value to the Floating Point Status/Control register.
-
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- /* Empty asm statement works as a scheduling barrier */
- __ASM volatile ("");
- __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
- __ASM volatile ("");
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-#endif /* __CORE_CMFUNC_H */
--- a/TARGET_GHI_MBUINO/core_cmInstr.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,688 +0,0 @@
-/**************************************************************************//**
- * @file core_cmInstr.h
- * @brief CMSIS Cortex-M Core Instruction Access Header File
- * @version V3.20
- * @date 05. March 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CMINSTR_H
-#define __CORE_CMINSTR_H
-
-
-/* ########################## Core Instruction Access ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
- Access to dedicated instructions
- @{
-*/
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-
-/** \brief No Operation
-
- No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP __nop
-
-
-/** \brief Wait For Interrupt
-
- Wait For Interrupt is a hint instruction that suspends execution
- until one of a number of events occurs.
- */
-#define __WFI __wfi
-
-
-/** \brief Wait For Event
-
- Wait For Event is a hint instruction that permits the processor to enter
- a low-power state until one of a number of events occurs.
- */
-#define __WFE __wfe
-
-
-/** \brief Send Event
-
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV __sev
-
-
-/** \brief Instruction Synchronization Barrier
-
- Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or
- memory, after the instruction has been completed.
- */
-#define __ISB() __isb(0xF)
-
-
-/** \brief Data Synchronization Barrier
-
- This function acts as a special kind of Data Memory Barrier.
- It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB() __dsb(0xF)
-
-
-/** \brief Data Memory Barrier
-
- This function ensures the apparent order of the explicit memory operations before
- and after the instruction, without ensuring their completion.
- */
-#define __DMB() __dmb(0xF)
-
-
-/** \brief Reverse byte order (32 bit)
-
- This function reverses the byte order in integer value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#define __REV __rev
-
-
-/** \brief Reverse byte order (16 bit)
-
- This function reverses the byte order in two unsigned short values.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
- rev16 r0, r0
- bx lr
-}
-#endif
-
-/** \brief Reverse byte order in signed short value
-
- This function reverses the byte order in a signed short value with sign extension to integer.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
-{
- revsh r0, r0
- bx lr
-}
-#endif
-
-
-/** \brief Rotate Right in unsigned value (32 bit)
-
- This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
- \param [in] value Value to rotate
- \param [in] value Number of Bits to rotate
- \return Rotated value
- */
-#define __ROR __ror
-
-
-/** \brief Breakpoint
-
- This function causes the processor to enter Debug state.
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
- \param [in] value is ignored by the processor.
- If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value) __breakpoint(value)
-
-
-#if (__CORTEX_M >= 0x03)
-
-/** \brief Reverse bit order of value
-
- This function reverses the bit order of the given value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#define __RBIT __rbit
-
-
-/** \brief LDR Exclusive (8 bit)
-
- This function performs a exclusive LDR command for 8 bit value.
-
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
-
-
-/** \brief LDR Exclusive (16 bit)
-
- This function performs a exclusive LDR command for 16 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
-
-
-/** \brief LDR Exclusive (32 bit)
-
- This function performs a exclusive LDR command for 32 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
-
-
-/** \brief STR Exclusive (8 bit)
-
- This function performs a exclusive STR command for 8 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXB(value, ptr) __strex(value, ptr)
-
-
-/** \brief STR Exclusive (16 bit)
-
- This function performs a exclusive STR command for 16 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXH(value, ptr) __strex(value, ptr)
-
-
-/** \brief STR Exclusive (32 bit)
-
- This function performs a exclusive STR command for 32 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXW(value, ptr) __strex(value, ptr)
-
-
-/** \brief Remove the exclusive lock
-
- This function removes the exclusive lock which is created by LDREX.
-
- */
-#define __CLREX __clrex
-
-
-/** \brief Signed Saturate
-
- This function saturates a signed value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-#define __SSAT __ssat
-
-
-/** \brief Unsigned Saturate
-
- This function saturates an unsigned value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-#define __USAT __usat
-
-
-/** \brief Count leading zeros
-
- This function counts the number of leading zeros of a data value.
-
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-#define __CLZ __clz
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constrant "l"
- * Otherwise, use general registers, specified by constrant "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/** \brief No Operation
-
- No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
-{
- __ASM volatile ("nop");
-}
-
-
-/** \brief Wait For Interrupt
-
- Wait For Interrupt is a hint instruction that suspends execution
- until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
-{
- __ASM volatile ("wfi");
-}
-
-
-/** \brief Wait For Event
-
- Wait For Event is a hint instruction that permits the processor to enter
- a low-power state until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
-{
- __ASM volatile ("wfe");
-}
-
-
-/** \brief Send Event
-
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
-{
- __ASM volatile ("sev");
-}
-
-
-/** \brief Instruction Synchronization Barrier
-
- Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or
- memory, after the instruction has been completed.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
-{
- __ASM volatile ("isb");
-}
-
-
-/** \brief Data Synchronization Barrier
-
- This function acts as a special kind of Data Memory Barrier.
- It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
-{
- __ASM volatile ("dsb");
-}
-
-
-/** \brief Data Memory Barrier
-
- This function ensures the apparent order of the explicit memory operations before
- and after the instruction, without ensuring their completion.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
-{
- __ASM volatile ("dmb");
-}
-
-
-/** \brief Reverse byte order (32 bit)
-
- This function reverses the byte order in integer value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
- return __builtin_bswap32(value);
-#else
- uint32_t result;
-
- __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-#endif
-}
-
-
-/** \brief Reverse byte order (16 bit)
-
- This function reverses the byte order in two unsigned short values.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-}
-
-
-/** \brief Reverse byte order in signed short value
-
- This function reverses the byte order in a signed short value with sign extension to integer.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- return (short)__builtin_bswap16(value);
-#else
- uint32_t result;
-
- __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-#endif
-}
-
-
-/** \brief Rotate Right in unsigned value (32 bit)
-
- This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
- \param [in] value Value to rotate
- \param [in] value Number of Bits to rotate
- \return Rotated value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
- return (op1 >> op2) | (op1 << (32 - op2));
-}
-
-
-/** \brief Breakpoint
-
- This function causes the processor to enter Debug state.
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
- \param [in] value is ignored by the processor.
- If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value) __ASM volatile ("bkpt "#value)
-
-
-#if (__CORTEX_M >= 0x03)
-
-/** \brief Reverse bit order of value
-
- This function reverses the bit order of the given value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-
-/** \brief LDR Exclusive (8 bit)
-
- This function performs a exclusive LDR command for 8 bit value.
-
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return(result);
-}
-
-
-/** \brief LDR Exclusive (16 bit)
-
- This function performs a exclusive LDR command for 16 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return(result);
-}
-
-
-/** \brief LDR Exclusive (32 bit)
-
- This function performs a exclusive LDR command for 32 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
- return(result);
-}
-
-
-/** \brief STR Exclusive (8 bit)
-
- This function performs a exclusive STR command for 8 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- return(result);
-}
-
-
-/** \brief STR Exclusive (16 bit)
-
- This function performs a exclusive STR command for 16 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- return(result);
-}
-
-
-/** \brief STR Exclusive (32 bit)
-
- This function performs a exclusive STR command for 32 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- return(result);
-}
-
-
-/** \brief Remove the exclusive lock
-
- This function removes the exclusive lock which is created by LDREX.
-
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
-{
- __ASM volatile ("clrex" ::: "memory");
-}
-
-
-/** \brief Signed Saturate
-
- This function saturates a signed value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-
-/** \brief Unsigned Saturate
-
- This function saturates an unsigned value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-
-/** \brief Count leading zeros
-
- This function counts the number of leading zeros of a data value.
-
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-#endif /* __CORE_CMINSTR_H */
--- a/TARGET_GHI_MBUINO/power_api.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,82 +0,0 @@
-/****************************************************************************
- * $Id:: power_api.h 6249 2011-01-25 19:23:47Z usb01267 $
- * Project: NXP LPC11Uxx software example
- *
- * Description:
- * Power API Header File for NXP LPC11Uxx Device Series
- *
- ****************************************************************************
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * products. This software is supplied "AS IS" without any warranties.
- * NXP Semiconductors assumes no responsibility or liability for the
- * use of the software, conveys no license or title under any patent,
- * copyright, or mask work right to the product. NXP Semiconductors
- * reserves the right to make changes in the software without
- * notification. NXP Semiconductors also make no representation or
- * warranty that such application will be suitable for the specified
- * use without further testing or modification.
-****************************************************************************/
-#ifndef __LPC11UXX_POWER_API_H__
-#define __LPC11UXX_POWER_API_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define PWRROMD_PRESENT
-
-typedef struct _PWRD {
- void (*set_pll)(unsigned int cmd[], unsigned int resp[]);
- void (*set_power)(unsigned int cmd[], unsigned int resp[]);
-} PWRD;
-
-typedef struct _ROM {
-#ifdef USBROMD_PRESENT
- const USB * pUSBD;
-#else
- const unsigned p_usbd;
-#endif /* USBROMD_PRESENT */
- const unsigned p_clib;
- const unsigned p_cand;
-#ifdef PWRROMD_PRESENT
- const PWRD * pPWRD;
-#else
- const unsigned p_pwrd;
-#endif /* PWRROMD_PRESENT */
- const unsigned p_dev1;
- const unsigned p_dev2;
- const unsigned p_dev3;
- const unsigned p_dev4;
-} ROM;
-
-//PLL setup related definitions
-#define CPU_FREQ_EQU 0 //main PLL freq must be equal to the specified
-#define CPU_FREQ_LTE 1 //main PLL freq must be less than or equal the specified
-#define CPU_FREQ_GTE 2 //main PLL freq must be greater than or equal the specified
-#define CPU_FREQ_APPROX 3 //main PLL freq must be as close as possible the specified
-
-#define PLL_CMD_SUCCESS 0 //PLL setup successfully found
-#define PLL_INVALID_FREQ 1 //specified freq out of range (either input or output)
-#define PLL_INVALID_MODE 2 //invalid mode (see above for valid) specified
-#define PLL_FREQ_NOT_FOUND 3 //specified freq not found under specified conditions
-#define PLL_NOT_LOCKED 4 //PLL not locked => no changes to the PLL setup
-
-//power setup elated definitions
-#define PARAM_DEFAULT 0 //default power settings (voltage regulator, flash interface)
-#define PARAM_CPU_PERFORMANCE 1 //setup for maximum CPU performance (higher current, more computation)
-#define PARAM_EFFICIENCY 2 //balanced setting (power vs CPU performance)
-#define PARAM_LOW_CURRENT 3 //lowest active current, lowest CPU performance
-
-#define PARAM_CMD_SUCCESS 0 //power setting successfully found
-#define PARAM_INVALID_FREQ 1 //specified freq out of range (=0 or > 50 MHz)
-#define PARAM_INVALID_MODE 2 //specified mode not valid (see above for valid)
-
-#define MAX_CLOCK_KHZ_PARAM 50000
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __LPC11UXX_POWER_API_H__ */
-
--- a/TARGET_GHI_MBUINO/system_LPC11Uxx.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,64 +0,0 @@
-/**************************************************************************//**
- * @file system_LPC11Uxx.h
- * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File
- * for the NXP LPC11Uxx Device Series
- * @version V1.10
- * @date 24. November 2010
- *
- * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#ifndef __SYSTEM_LPC11Uxx_H
-#define __SYSTEM_LPC11Uxx_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-
-
-/**
- * Initialize the system
- *
- * @param none
- * @return none
- *
- * @brief Setup the microcontroller system.
- * Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param none
- * @return none
- *
- * @brief Updates the SystemCoreClock with current core Clock
- * retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_LPC11Uxx_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_HRM1017/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_button.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,187 @@
+/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup app_button Button Handler
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Buttons handling module.
+ *
+ * @details The button handler uses the @ref app_gpiote to detect that a button has been
+ * pushed. To handle debouncing, it will start a timer in the GPIOTE event handler.
+ * The button will only be reported as pushed if the corresponding pin is still active when
+ * the timer expires. If there is a new GPIOTE event while the timer is running, the timer
+ * is restarted.
+ * Use the USE_SCHEDULER parameter of the APP_BUTTON_INIT() macro to select if the
+ * @ref app_scheduler is to be used or not.
+ *
+ * @note The app_button module uses the app_timer module. The user must ensure that the queue in
+ * app_timer is large enough to hold the app_timer_stop() / app_timer_start() operations
+ * which will be executed on each event from GPIOTE module (2 operations), as well as other
+ * app_timer operations queued simultaneously in the application.
+ *
+ * @note Even if the scheduler is not used, app_button.h will include app_scheduler.h, so when
+ * compiling, app_scheduler.h must be available in one of the compiler include paths.
+ */
+
+#ifndef APP_BUTTON_H__
+#define APP_BUTTON_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "app_error.h"
+#include "app_scheduler.h"
+#include "nrf_gpio.h"
+
+#define APP_BUTTON_SCHED_EVT_SIZE sizeof(app_button_event_t) /**< Size of button events being passed through the scheduler (is to be used for computing the maximum size of scheduler events). */
+#define APP_BUTTON_PUSH 1 /**< Indicates that a button is pushed. */
+#define APP_BUTTON_RELEASE 0 /**< Indicates that a button is released. */
+#define APP_BUTTON_ACTIVE_HIGH 1 /**< Indicates that a button is active high. */
+#define APP_BUTTON_ACTIVE_LOW 0 /**< Indicates that a button is active low. */
+
+/**@brief Button event handler type. */
+typedef void (*app_button_handler_t)(uint8_t pin_no, uint8_t button_action);
+
+/**@brief Type of function for passing events from the Button Handler module to the scheduler. */
+typedef uint32_t (*app_button_evt_schedule_func_t) (app_button_handler_t button_handler,
+ uint8_t pin_no,
+ uint8_t button_action);
+
+/**@brief Button configuration structure. */
+typedef struct
+{
+ uint8_t pin_no; /**< Pin to be used as a button. */
+ uint8_t active_state; /**< APP_BUTTON_ACTIVE_HIGH or APP_BUTTON_ACTIVE_LOW. */
+ nrf_gpio_pin_pull_t pull_cfg; /**< Pull-up or -down configuration. */
+ app_button_handler_t button_handler; /**< Handler to be called when button is pushed. */
+} app_button_cfg_t;
+
+/**@brief Pin transition direction struct. */
+typedef struct
+{
+ uint32_t high_to_low; /**Pin went from high to low */
+ uint32_t low_to_high; /**Pin went from low to high */
+} pin_transition_t;
+
+/**@brief Macro for initializing the Button Handler module.
+ *
+ * @details It will initialize the specified pins as buttons, and configure the Button Handler
+ * module as a GPIOTE user (but it will not enable button detection). It will also connect
+ * the Button Handler module to the scheduler (if specified).
+ *
+ * @param[in] BUTTONS Array of buttons to be used (type app_button_cfg_t, must be
+ * static!).
+ * @param[in] BUTTON_COUNT Number of buttons.
+ * @param[in] DETECTION_DELAY Delay from a GPIOTE event until a button is reported as pushed.
+ * @param[in] USE_SCHEDULER TRUE if the application is using the event scheduler,
+ * FALSE otherwise.
+ */
+/*lint -emacro(506, APP_BUTTON_INIT) */ /* Suppress "Constant value Boolean */
+#define APP_BUTTON_INIT(BUTTONS, BUTTON_COUNT, DETECTION_DELAY, USE_SCHEDULER) \
+ do \
+ { \
+ uint32_t ERR_CODE = app_button_init((BUTTONS), \
+ (BUTTON_COUNT), \
+ (DETECTION_DELAY), \
+ (USE_SCHEDULER) ? app_button_evt_schedule : NULL); \
+ APP_ERROR_CHECK(ERR_CODE); \
+ } while (0)
+
+/**@brief Function for initializing the Buttons.
+ *
+ * @details This function will initialize the specified pins as buttons, and configure the Button
+ * Handler module as a GPIOTE user (but it will not enable button detection).
+ *
+ * @note Normally initialization should be done using the APP_BUTTON_INIT() macro, as that will take
+ * care of connecting the Buttons module to the scheduler (if specified).
+ *
+ * @note app_button_enable() function must be called in order to enable the button detection.
+ *
+ * @param[in] p_buttons Array of buttons to be used (NOTE: Must be static!).
+ * @param[in] button_count Number of buttons.
+ * @param[in] detection_delay Delay from a GPIOTE event until a button is reported as pushed.
+ * @param[in] evt_schedule_func Function for passing button events to the scheduler. Point to
+ * app_button_evt_schedule() to connect to the scheduler. Set to
+ * NULL to make the Buttons module call the event handler directly
+ * from the delayed button push detection timeout handler.
+ *
+ * @return NRF_SUCCESS on success, otherwise an error code.
+ */
+uint32_t app_button_init(app_button_cfg_t * p_buttons,
+ uint8_t button_count,
+ uint32_t detection_delay,
+ app_button_evt_schedule_func_t evt_schedule_func);
+
+/**@brief Function for enabling button detection.
+ *
+ * @retval NRF_ERROR_INVALID_PARAM GPIOTE has to many users.
+ * @retval NRF_ERROR_INVALID_STATE Button or GPIOTE not initialized.
+ * @retval NRF_SUCCESS Button detection successfully enabled.
+ */
+uint32_t app_button_enable(void);
+
+/**@brief Function for disabling button detection.
+ *
+ * @retval NRF_ERROR_INVALID_PARAM GPIOTE has to many users.
+ * @retval NRF_ERROR_INVALID_STATE Button or GPIOTE not initialized.
+ * @retval NRF_SUCCESS Button detection successfully enabled.
+ */
+uint32_t app_button_disable(void);
+
+/**@brief Function for checking if a button is currently being pushed.
+ *
+ * @param[in] pin_no Button pin to be checked.
+ * @param[out] p_is_pushed Button state.
+ *
+ * @retval NRF_SUCCESS State successfully read.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid pin_no.
+ */
+uint32_t app_button_is_pushed(uint8_t pin_no, bool * p_is_pushed);
+
+
+// Type and functions for connecting the Buttons module to the scheduler:
+
+/**@cond NO_DOXYGEN */
+typedef struct
+{
+ app_button_handler_t button_handler;
+ uint8_t pin_no;
+ uint8_t button_action;
+} app_button_event_t;
+
+static __INLINE void app_button_evt_get(void * p_event_data, uint16_t event_size)
+{
+ app_button_event_t * p_buttons_event = (app_button_event_t *)p_event_data;
+
+ APP_ERROR_CHECK_BOOL(event_size == sizeof(app_button_event_t));
+ p_buttons_event->button_handler(p_buttons_event->pin_no, p_buttons_event->button_action);
+}
+
+static __INLINE uint32_t app_button_evt_schedule(app_button_handler_t button_handler,
+ uint8_t pin_no,
+ uint8_t button_action)
+{
+ app_button_event_t buttons_event;
+
+ buttons_event.button_handler = button_handler;
+ buttons_event.pin_no = pin_no;
+ buttons_event.button_action = button_action;
+
+ return app_sched_event_put(&buttons_event, sizeof(buttons_event), app_button_evt_get);
+}
+/**@endcond */
+
+#endif // APP_BUTTON_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_HRM1017/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_error.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,84 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup app_error Common application error handler
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Common application error handler and macros for utilizing a common error handler.
+ */
+
+#ifndef APP_ERROR_H__
+#define APP_ERROR_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "nrf_error.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@brief Function for error handling, which is called when an error has occurred.
+ *
+ * @param[in] error_code Error code supplied to the handler.
+ * @param[in] line_num Line number where the handler is called.
+ * @param[in] p_file_name Pointer to the file name.
+ */
+void app_error_handler(uint32_t error_code, uint32_t line_num, const uint8_t * p_file_name);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@brief Macro for calling error handler function.
+ *
+ * @param[in] ERR_CODE Error code supplied to the error handler.
+ */
+#define APP_ERROR_HANDLER(ERR_CODE) \
+ do \
+ { \
+ /* app_error_handler((ERR_CODE), __LINE__, (uint8_t*) __FILE__); */ \
+ } while (0)
+
+/**@brief Macro for calling error handler function if supplied error code any other than NRF_SUCCESS.
+ *
+ * @param[in] ERR_CODE Error code supplied to the error handler.
+ */
+#define APP_ERROR_CHECK(ERR_CODE) \
+ do \
+ { \
+ const uint32_t LOCAL_ERR_CODE = (ERR_CODE); \
+ if (LOCAL_ERR_CODE != NRF_SUCCESS) \
+ { \
+ APP_ERROR_HANDLER(LOCAL_ERR_CODE); \
+ } \
+ } while (0)
+
+/**@brief Macro for calling error handler function if supplied boolean value is false.
+ *
+ * @param[in] BOOLEAN_VALUE Boolean value to be evaluated.
+ */
+#define APP_ERROR_CHECK_BOOL(BOOLEAN_VALUE) \
+ do \
+ { \
+ const bool LOCAL_BOOLEAN_VALUE = (BOOLEAN_VALUE); \
+ if (!LOCAL_BOOLEAN_VALUE) \
+ { \
+ APP_ERROR_HANDLER(0); \
+ } \
+ } while (0)
+
+#endif // APP_ERROR_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_HRM1017/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_fifo.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,83 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/**@file
+ *
+ * @defgroup app_fifo FIFO implementation
+ * @{
+ * @ingroup app_common
+ *
+ * @brief FIFO implementation.
+ */
+
+#ifndef APP_FIFO_H__
+#define APP_FIFO_H__
+
+#include <stdint.h>
+#include <stdlib.h>
+#include "nrf_error.h"
+
+/**@brief A FIFO instance structure. Keeps track of which bytes to read and write next.
+ * Also it keeps the information about which memory is allocated for the buffer
+ * and its size. This needs to be initialized by app_fifo_init() before use.
+ */
+typedef struct
+{
+ uint8_t * p_buf; /**< Pointer to FIFO buffer memory. */
+ uint16_t buf_size_mask; /**< Read/write index mask. Also used for size checking. */
+ volatile uint32_t read_pos; /**< Next read position in the FIFO buffer. */
+ volatile uint32_t write_pos; /**< Next write position in the FIFO buffer. */
+} app_fifo_t;
+
+/**@brief Function for initializing the FIFO.
+ *
+ * @param[out] p_fifo FIFO object.
+ * @param[in] p_buf FIFO buffer for storing data. The buffer size has to be a power of two.
+ * @param[in] buf_size Size of the FIFO buffer provided, has to be a power of 2.
+ *
+ * @retval NRF_SUCCESS If initialization was successful.
+ * @retval NRF_ERROR_NULL If a NULL pointer is provided as buffer.
+ * @retval NRF_ERROR_INVALID_LENGTH If size of buffer provided is not a power of two.
+ */
+uint32_t app_fifo_init(app_fifo_t * p_fifo, uint8_t * p_buf, uint16_t buf_size);
+
+/**@brief Function for adding an element to the FIFO.
+ *
+ * @param[in] p_fifo Pointer to the FIFO.
+ * @param[in] byte Data byte to add to the FIFO.
+ *
+ * @retval NRF_SUCCESS If an element has been successfully added to the FIFO.
+ * @retval NRF_ERROR_NO_MEM If the FIFO is full.
+ */
+uint32_t app_fifo_put(app_fifo_t * p_fifo, uint8_t byte);
+
+/**@brief Function for getting the next element from the FIFO.
+ *
+ * @param[in] p_fifo Pointer to the FIFO.
+ * @param[out] p_byte Byte fetched from the FIFO.
+ *
+ * @retval NRF_SUCCESS If an element was returned.
+ * @retval NRF_ERROR_NOT_FOUND If there is no more elements in the queue.
+ */
+uint32_t app_fifo_get(app_fifo_t * p_fifo, uint8_t * p_byte);
+
+/**@brief Function for flushing the FIFO.
+ *
+ * @param[in] p_fifo Pointer to the FIFO.
+ *
+ * @retval NRF_SUCCESS If the FIFO flushed successfully.
+ */
+uint32_t app_fifo_flush(app_fifo_t * p_fifo);
+
+#endif // APP_FIFO_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_HRM1017/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_gpiote.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,226 @@
+/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup app_gpiote GPIOTE Handler
+ * @{
+ * @ingroup app_common
+ *
+ * @brief GPIOTE handler module.
+ *
+ * @details The GPIOTE handler allows several modules ("users") to share the GPIOTE interrupt,
+ * each user defining a set of pins able to generate events to the user.
+ * When a GPIOTE interrupt occurs, the GPIOTE interrupt handler will call the event handler
+ * of each user for which at least one of the pins generated an event.
+ *
+ * The GPIOTE users are responsible for configuring all their corresponding pins, except
+ * the SENSE field, which should be initialized to GPIO_PIN_CNF_SENSE_Disabled.
+ * The SENSE field will be updated by the GPIOTE module when it is enabled or disabled,
+ * and also while it is enabled.
+ *
+ * The module specifies on which pins events should be generated if the pin(s) goes
+ * from low->high or high->low or both directions.
+ *
+ * @note Even if the application is using the @ref app_scheduler, the GPIOTE event handlers will
+ * be called directly from the GPIOTE interrupt handler.
+ *
+ * @warning If multiple users registers for the same pins the behavior for those pins are undefined.
+ */
+
+#ifndef APP_GPIOTE_H__
+#define APP_GPIOTE_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+// #include "nrf.h"
+#include "app_error.h"
+#include "app_util.h"
+
+#ifdef __cpluplus
+extern "C" {
+#endif
+
+#define GPIOTE_USER_NODE_SIZE 20 /**< Size of app_gpiote.gpiote_user_t (only for use inside APP_GPIOTE_BUF_SIZE()). */
+#define NO_OF_PINS 32 /**< Number of GPIO pins on the nRF51 chip. */
+
+/**@brief Compute number of bytes required to hold the GPIOTE data structures.
+ *
+ * @param[in] MAX_USERS Maximum number of GPIOTE users.
+ *
+ * @return Required buffer size (in bytes).
+ */
+#define APP_GPIOTE_BUF_SIZE(MAX_USERS) ((MAX_USERS) * GPIOTE_USER_NODE_SIZE)
+
+typedef uint8_t app_gpiote_user_id_t;
+
+/**@brief GPIOTE event handler type. */
+typedef void (*app_gpiote_event_handler_t)(uint32_t event_pins_low_to_high,
+ uint32_t event_pins_high_to_low);
+
+/**@brief GPIOTE input event handler type. */
+typedef void (*app_gpiote_input_event_handler_t)(void);
+
+/**@brief Macro for initializing the GPIOTE module.
+ *
+ * @details It will handle dimensioning and allocation of the memory buffer required by the module,
+ * making sure that the buffer is correctly aligned.
+ *
+ * @param[in] MAX_USERS Maximum number of GPIOTE users.
+ *
+ * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it
+ * several times as long as it is from the same location, e.g. to do a reinitialization).
+ */
+/*lint -emacro(506, APP_GPIOTE_INIT) */ /* Suppress "Constant value Boolean */
+#define APP_GPIOTE_INIT(MAX_USERS) \
+ do \
+ { \
+ static uint32_t app_gpiote_buf[CEIL_DIV(APP_GPIOTE_BUF_SIZE(MAX_USERS), sizeof(uint32_t))];\
+ uint32_t ERR_CODE = app_gpiote_init((MAX_USERS), app_gpiote_buf); \
+ APP_ERROR_CHECK(ERR_CODE); \
+ } while (0)
+
+/**@brief Function for initializing the GPIOTE module.
+ *
+ * @note Normally initialization should be done using the APP_GPIOTE_INIT() macro, as that will
+ * allocate the buffer needed by the GPIOTE module (including aligning the buffer correctly).
+ *
+ * @param[in] max_users Maximum number of GPIOTE users.
+ * @param[in] p_buffer Pointer to memory buffer for internal use in the app_gpiote
+ * module. The size of the buffer can be computed using the
+ * APP_GPIOTE_BUF_SIZE() macro. The buffer must be aligned to
+ * a 4 byte boundary.
+ *
+ * @retval NRF_SUCCESS Successful initialization.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte
+ * boundary).
+ */
+uint32_t app_gpiote_init(uint8_t max_users, void * p_buffer);
+
+/**@brief Function for registering a GPIOTE user.
+ *
+ * @param[out] p_user_id Id for the new GPIOTE user.
+ * @param[in] pins_low_to_high_mask Mask defining which pins will generate events to this user
+ * when state is changed from low->high.
+ * @param[in] pins_high_to_low_mask Mask defining which pins will generate events to this user
+ * when state is changed from high->low.
+ * @param[in] event_handler Pointer to function to be executed when an event occurs.
+ *
+ * @retval NRF_SUCCESS Successful initialization.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte boundary).
+ * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE
+ * module.
+ * @retval NRF_ERROR_NO_MEM Returned if the application tries to register more users
+ * than defined when the GPIOTE module was initialized in
+ * @ref app_gpiote_init.
+ */
+uint32_t app_gpiote_user_register(app_gpiote_user_id_t * p_user_id,
+ uint32_t pins_low_to_high_mask,
+ uint32_t pins_high_to_low_mask,
+ app_gpiote_event_handler_t event_handler);
+
+/**@brief Function for informing the GPIOTE module that the specified user wants to use the GPIOTE module.
+ *
+ * @param[in] user_id Id of user to enable.
+ *
+ * @retval NRF_SUCCESS On success.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid user_id provided, No a valid user.
+ * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE
+ * module.
+ */
+uint32_t app_gpiote_user_enable(app_gpiote_user_id_t user_id);
+
+/**@brief Function for informing the GPIOTE module that the specified user is done using the GPIOTE module.
+ *
+ * @param[in] user_id Id of user to enable.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid user_id provided, No a valid user.
+ * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE
+ * module.
+ */
+uint32_t app_gpiote_user_disable(app_gpiote_user_id_t user_id);
+
+/**@brief Function for getting the state of the pins which are registered for the specified user.
+ *
+ * @param[in] user_id Id of user to check.
+ * @param[out] p_pins Bit mask corresponding to the pins configured to generate events to
+ * the specified user. All bits corresponding to pins in the state
+ * 'high' will have value '1', all others will have value '0'.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid user_id provided, No a valid user.
+ * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE
+ * module.
+ */
+uint32_t app_gpiote_pins_state_get(app_gpiote_user_id_t user_id, uint32_t * p_pins);
+
+/**@brief Function for registering event handlers for GPIOTE IN events.
+ *
+ * @param[in] channel GPIOTE channel [0..3].
+ * @param[in] pin Pins associated with GPIOTE channel. Changes on following pins will generate events.
+ * @param[in] polarity Specify operation on input that shall trigger IN event.
+ * @param[in] event_handler Event handler invoked on the IN event in the GPIOTE interrupt.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid channel or pin number.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events.
+ */
+uint32_t app_gpiote_input_event_handler_register(const uint8_t channel,
+ const uint32_t pin,
+ const uint32_t polarity,
+ app_gpiote_input_event_handler_t event_handler);
+
+/**@brief Function for unregistering event handlers for GPIOTE IN events.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events.
+ */
+uint32_t app_gpiote_input_event_handler_unregister(const uint8_t channel);
+
+/**@brief Function for registering event handler invoked at the end of a GPIOTE interrupt.
+ *
+ * @param[in] event_handler Event handler invoked at the end of the GPIOTE interrupt.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events.
+ */
+uint32_t app_gpiote_end_irq_event_handler_register(app_gpiote_input_event_handler_t event_handler);
+
+/**@brief Function for unregistering event handler invoked at the end of a GPIOTE interrupt.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events.
+ */
+uint32_t app_gpiote_end_irq_event_handler_unregister(void);
+
+/**@brief Function for enabling interrupts in the GPIOTE driver.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support.
+ */
+uint32_t app_gpiote_enable_interrupts(void);
+
+/**@brief Function for disabling interrupts in the GPIOTE driver.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support.
+ */
+uint32_t app_gpiote_disable_interrupts(void);
+
+#ifdef __cpluplus
+}
+#endif
+
+#endif // APP_GPIOTE_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_HRM1017/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_scheduler.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,134 @@
+/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup app_scheduler Scheduler
+ * @{
+ * @ingroup app_common
+ *
+ * @brief The scheduler is used for transferring execution from the interrupt context to the main
+ * context.
+ *
+ * @details See @ref ble_sdk_apps_seq_diagrams for sequence diagrams illustrating the flow of events
+ * when using the Scheduler.
+ *
+ * @section app_scheduler_req Requirements:
+ *
+ * @subsection main_context_logic Logic in main context:
+ *
+ * - Define an event handler for each type of event expected.
+ * - Initialize the scheduler by calling the APP_SCHED_INIT() macro before entering the
+ * application main loop.
+ * - Call app_sched_execute() from the main loop each time the application wakes up because of an
+ * event (typically when sd_app_evt_wait() returns).
+ *
+ * @subsection int_context_logic Logic in interrupt context:
+ *
+ * - In the interrupt handler, call app_sched_event_put()
+ * with the appropriate data and event handler. This will insert an event into the
+ * scheduler's queue. The app_sched_execute() function will pull this event and call its
+ * handler in the main context.
+ *
+ * For an example usage of the scheduler, please see the implementations of
+ * @ref ble_sdk_app_hids_mouse and @ref ble_sdk_app_hids_keyboard.
+ *
+ * @image html scheduler_working.jpg The high level design of the scheduler
+ */
+
+#ifndef APP_SCHEDULER_H__
+#define APP_SCHEDULER_H__
+
+#include <stdint.h>
+#include "app_error.h"
+
+#define APP_SCHED_EVENT_HEADER_SIZE 8 /**< Size of app_scheduler.event_header_t (only for use inside APP_SCHED_BUF_SIZE()). */
+
+/**@brief Compute number of bytes required to hold the scheduler buffer.
+ *
+ * @param[in] EVENT_SIZE Maximum size of events to be passed through the scheduler.
+ * @param[in] QUEUE_SIZE Number of entries in scheduler queue (i.e. the maximum number of events
+ * that can be scheduled for execution).
+ *
+ * @return Required scheduler buffer size (in bytes).
+ */
+#define APP_SCHED_BUF_SIZE(EVENT_SIZE, QUEUE_SIZE) \
+ (((EVENT_SIZE) + APP_SCHED_EVENT_HEADER_SIZE) * ((QUEUE_SIZE) + 1))
+
+/**@brief Scheduler event handler type. */
+typedef void (*app_sched_event_handler_t)(void * p_event_data, uint16_t event_size);
+
+/**@brief Macro for initializing the event scheduler.
+ *
+ * @details It will also handle dimensioning and allocation of the memory buffer required by the
+ * scheduler, making sure the buffer is correctly aligned.
+ *
+ * @param[in] EVENT_SIZE Maximum size of events to be passed through the scheduler.
+ * @param[in] QUEUE_SIZE Number of entries in scheduler queue (i.e. the maximum number of events
+ * that can be scheduled for execution).
+ *
+ * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it
+ * several times as long as it is from the same location, e.g. to do a reinitialization).
+ */
+#define APP_SCHED_INIT(EVENT_SIZE, QUEUE_SIZE) \
+ do \
+ { \
+ static uint32_t APP_SCHED_BUF[CEIL_DIV(APP_SCHED_BUF_SIZE((EVENT_SIZE), (QUEUE_SIZE)), \
+ sizeof(uint32_t))]; \
+ uint32_t ERR_CODE = app_sched_init((EVENT_SIZE), (QUEUE_SIZE), APP_SCHED_BUF); \
+ APP_ERROR_CHECK(ERR_CODE); \
+ } while (0)
+
+/**@brief Function for initializing the Scheduler.
+ *
+ * @details It must be called before entering the main loop.
+ *
+ * @param[in] max_event_size Maximum size of events to be passed through the scheduler.
+ * @param[in] queue_size Number of entries in scheduler queue (i.e. the maximum number of
+ * events that can be scheduled for execution).
+ * @param[in] p_event_buffer Pointer to memory buffer for holding the scheduler queue. It must
+ * be dimensioned using the APP_SCHED_BUFFER_SIZE() macro. The buffer
+ * must be aligned to a 4 byte boundary.
+ *
+ * @note Normally initialization should be done using the APP_SCHED_INIT() macro, as that will both
+ * allocate the scheduler buffer, and also align the buffer correctly.
+ *
+ * @retval NRF_SUCCESS Successful initialization.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte
+ * boundary).
+ */
+uint32_t app_sched_init(uint16_t max_event_size, uint16_t queue_size, void * p_evt_buffer);
+
+/**@brief Function for executing all scheduled events.
+ *
+ * @details This function must be called from within the main loop. It will execute all events
+ * scheduled since the last time it was called.
+ */
+void app_sched_execute(void);
+
+/**@brief Function for scheduling an event.
+ *
+ * @details Puts an event into the event queue.
+ *
+ * @param[in] p_event_data Pointer to event data to be scheduled.
+ * @param[in] p_event_size Size of event data to be scheduled.
+ * @param[in] handler Event handler to receive the event.
+ *
+ * @return NRF_SUCCESS on success, otherwise an error code.
+ */
+uint32_t app_sched_event_put(void * p_event_data,
+ uint16_t event_size,
+ app_sched_event_handler_t handler);
+
+#endif // APP_SCHEDULER_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_HRM1017/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_timer.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,313 @@
+/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup app_timer Application Timer
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Application timer functionality.
+ *
+ * @details It enables the application to create multiple timer instances based on the RTC1
+ * peripheral. Checking for timeouts and invokation of user timeout handlers is performed
+ * in the RTC1 interrupt handler. List handling is done using a software interrupt (SWI0).
+ * Both interrupt handlers are running in APP_LOW priority level.
+ *
+ * @note When calling app_timer_start() or app_timer_stop(), the timer operation is just queued,
+ * and the software interrupt is triggered. The actual timer start/stop operation is
+ * executed by the SWI0 interrupt handler. Since the SWI0 interrupt is running in APP_LOW,
+ * if the application code calling the timer function is running in APP_LOW or APP_HIGH,
+ * the timer operation will not be performed until the application handler has returned.
+ * This will be the case e.g. when stopping a timer from a timeout handler when not using
+ * the scheduler.
+ *
+ * @details Use the USE_SCHEDULER parameter of the APP_TIMER_INIT() macro to select if the
+ * @ref app_scheduler is to be used or not.
+ *
+ * @note Even if the scheduler is not used, app_timer.h will include app_scheduler.h, so when
+ * compiling, app_scheduler.h must be available in one of the compiler include paths.
+ */
+
+#ifndef APP_TIMER_H__
+#define APP_TIMER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include "app_error.h"
+#include "app_util.h"
+#include "app_scheduler.h"
+#include "compiler_abstraction.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif // #ifdef __cplusplus
+
+#define APP_TIMER_SCHED_EVT_SIZE sizeof(app_timer_event_t) /**< Size of button events being passed through the scheduler (is to be used for computing the maximum size of scheduler events). */
+#define APP_TIMER_CLOCK_FREQ 32768 /**< Clock frequency of the RTC timer used to implement the app timer module. */
+#define APP_TIMER_MIN_TIMEOUT_TICKS 5 /**< Minimum value of the timeout_ticks parameter of app_timer_start(). */
+
+#define APP_TIMER_NODE_SIZE 40 /**< Size of app_timer.timer_node_t (only for use inside APP_TIMER_BUF_SIZE()). */
+#define APP_TIMER_USER_OP_SIZE 24 /**< Size of app_timer.timer_user_op_t (only for use inside APP_TIMER_BUF_SIZE()). */
+#define APP_TIMER_USER_SIZE 8 /**< Size of app_timer.timer_user_t (only for use inside APP_TIMER_BUF_SIZE()). */
+#define APP_TIMER_INT_LEVELS 3 /**< Number of interrupt levels from where timer operations may be initiated (only for use inside APP_TIMER_BUF_SIZE()). */
+
+#define MAX_RTC_COUNTER_VAL 0x00FFFFFF /**< Maximum value of the RTC counter. */
+
+/**@brief Compute number of bytes required to hold the application timer data structures.
+ *
+ * @param[in] MAX_TIMERS Maximum number of timers that can be created at any given time.
+ * @param[in] OP_QUEUE_SIZE Size of queues holding timer operations that are pending execution.
+ * NOTE: Due to the queue implementation, this size must be one more
+ * than the size that is actually needed.
+ *
+ * @return Required application timer buffer size (in bytes).
+ */
+#define APP_TIMER_BUF_SIZE(MAX_TIMERS, OP_QUEUE_SIZE) \
+ ( \
+ ((MAX_TIMERS) * APP_TIMER_NODE_SIZE) \
+ + \
+ ( \
+ APP_TIMER_INT_LEVELS \
+ * \
+ (APP_TIMER_USER_SIZE + ((OP_QUEUE_SIZE) + 1) * APP_TIMER_USER_OP_SIZE) \
+ ) \
+ )
+
+/**@brief Convert milliseconds to timer ticks.
+ *
+ * @note This macro uses 64 bit integer arithmetic, but as long as the macro parameters are
+ * constants (i.e. defines), the computation will be done by the preprocessor.
+ *
+ * @param[in] MS Milliseconds.
+ * @param[in] PRESCALER Value of the RTC1 PRESCALER register (must be the same value that was
+ * passed to APP_TIMER_INIT()).
+ *
+ * @note When using this macro, it is the responsibility of the developer to ensure that the
+ * values provided as input result in an output value that is supported by the
+ * @ref app_timer_start function. For example, when the ticks for 1 ms is needed, the
+ * maximum possible value of PRESCALER must be 6, when @ref APP_TIMER_CLOCK_FREQ is 32768.
+ * This will result in a ticks value as 5. Any higher value for PRESCALER will result in a
+ * ticks value that is not supported by this module.
+ *
+ * @return Number of timer ticks.
+ */
+#define APP_TIMER_TICKS(MS, PRESCALER)\
+ ((uint32_t)ROUNDED_DIV((MS) * (uint64_t)APP_TIMER_CLOCK_FREQ, ((PRESCALER) + 1) * 1000))
+
+/**@brief Timer id type. */
+typedef uint32_t app_timer_id_t;
+
+#define TIMER_NULL ((app_timer_id_t)(0 - 1)) /**< Invalid timer id. */
+
+/**@brief Application timeout handler type. */
+typedef void (*app_timer_timeout_handler_t)(void * p_context);
+
+/**@brief Type of function for passing events from the timer module to the scheduler. */
+typedef uint32_t (*app_timer_evt_schedule_func_t) (app_timer_timeout_handler_t timeout_handler,
+ void * p_context);
+
+/**@brief Timer modes. */
+typedef enum
+{
+ APP_TIMER_MODE_SINGLE_SHOT, /**< The timer will expire only once. */
+ APP_TIMER_MODE_REPEATED /**< The timer will restart each time it expires. */
+} app_timer_mode_t;
+
+/**@brief Macro for initializing the application timer module.
+ *
+ * @details It will handle dimensioning and allocation of the memory buffer required by the timer,
+ * making sure that the buffer is correctly aligned. It will also connect the timer module
+ * to the scheduler (if specified).
+ *
+ * @note This module assumes that the LFCLK is already running. If it isn't, the module will
+ * be non-functional, since the RTC will not run. If you don't use a softdevice, you'll
+ * have to start the LFCLK manually. See the rtc_example's \ref lfclk_config() function
+ * for an example of how to do this. If you use a softdevice, the LFCLK is started on
+ * softdevice init.
+ *
+ *
+ * @param[in] PRESCALER Value of the RTC1 PRESCALER register. This will decide the
+ * timer tick rate. Set to 0 for no prescaling.
+ * @param[in] MAX_TIMERS Maximum number of timers that can be created at any given time.
+ * @param[in] OP_QUEUES_SIZE Size of queues holding timer operations that are pending execution.
+ * @param[in] USE_SCHEDULER TRUE if the application is using the event scheduler,
+ * FALSE otherwise.
+ *
+ * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it
+ * several times as long as it is from the same location, e.g. to do a reinitialization).
+ */
+/*lint -emacro(506, APP_TIMER_INIT) */ /* Suppress "Constant value Boolean */
+#define APP_TIMER_INIT(PRESCALER, MAX_TIMERS, OP_QUEUES_SIZE, USE_SCHEDULER) \
+ do \
+ { \
+ static uint32_t APP_TIMER_BUF[CEIL_DIV(APP_TIMER_BUF_SIZE((MAX_TIMERS), \
+ (OP_QUEUES_SIZE) + 1), \
+ sizeof(uint32_t))]; \
+ uint32_t ERR_CODE = app_timer_init((PRESCALER), \
+ (MAX_TIMERS), \
+ (OP_QUEUES_SIZE) + 1, \
+ APP_TIMER_BUF, \
+ (USE_SCHEDULER) ? app_timer_evt_schedule : NULL); \
+ APP_ERROR_CHECK(ERR_CODE); \
+ } while (0)
+
+/**@brief Function for initializing the timer module.
+ *
+ * @note Normally initialization should be done using the APP_TIMER_INIT() macro, as that will both
+ * allocate the buffers needed by the timer module (including aligning the buffers correctly,
+ * and also take care of connecting the timer module to the scheduler (if specified).
+ *
+ * @param[in] prescaler Value of the RTC1 PRESCALER register. Set to 0 for no prescaling.
+ * @param[in] max_timers Maximum number of timers that can be created at any given time.
+ * @param[in] op_queues_size Size of queues holding timer operations that are pending
+ * execution. NOTE: Due to the queue implementation, this size must
+ * be one more than the size that is actually needed.
+ * @param[in] p_buffer Pointer to memory buffer for internal use in the app_timer
+ * module. The size of the buffer can be computed using the
+ * APP_TIMER_BUF_SIZE() macro. The buffer must be aligned to a
+ * 4 byte boundary.
+ * @param[in] evt_schedule_func Function for passing timeout events to the scheduler. Point to
+ * app_timer_evt_schedule() to connect to the scheduler. Set to NULL
+ * to make the timer module call the timeout handler directly from
+ * the timer interrupt handler.
+ *
+ * @retval NRF_SUCCESS Successful initialization.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte
+ * boundary or NULL).
+ */
+uint32_t app_timer_init(uint32_t prescaler,
+ uint8_t max_timers,
+ uint8_t op_queues_size,
+ void * p_buffer,
+ app_timer_evt_schedule_func_t evt_schedule_func);
+
+/**@brief Function for creating a timer instance.
+ *
+ * @param[out] p_timer_id Id of the newly created timer.
+ * @param[in] mode Timer mode.
+ * @param[in] timeout_handler Function to be executed when the timer expires.
+ *
+ * @retval NRF_SUCCESS Timer was successfully created.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter.
+ * @retval NRF_ERROR_INVALID_STATE Application timer module has not been initialized.
+ * @retval NRF_ERROR_NO_MEM Maximum number of timers has already been reached.
+ *
+ * @note This function does the timer allocation in the caller's context. It is also not protected
+ * by a critical region. Therefore care must be taken not to call it from several interrupt
+ * levels simultaneously.
+ */
+uint32_t app_timer_create(app_timer_id_t * p_timer_id,
+ app_timer_mode_t mode,
+ app_timer_timeout_handler_t timeout_handler);
+
+/**@brief Function for starting a timer.
+ *
+ * @param[in] timer_id Id of timer to start.
+ * @param[in] timeout_ticks Number of ticks (of RTC1, including prescaling) to timeout event
+ * (minimum 5 ticks).
+ * @param[in] p_context General purpose pointer. Will be passed to the timeout handler when
+ * the timer expires.
+ *
+ * @retval NRF_SUCCESS Timer was successfully started.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter.
+ * @retval NRF_ERROR_INVALID_STATE Application timer module has not been initialized, or timer
+ * has not been created.
+ * @retval NRF_ERROR_NO_MEM Timer operations queue was full.
+ *
+ * @note The minimum timeout_ticks value is 5.
+ * @note For multiple active timers, timeouts occurring in close proximity to each other (in the
+ * range of 1 to 3 ticks) will have a positive jitter of maximum 3 ticks.
+ * @note When calling this method on a timer which is already running, the second start operation
+ * will be ignored.
+ */
+uint32_t app_timer_start(app_timer_id_t timer_id, uint32_t timeout_ticks, void * p_context);
+
+/**@brief Function for stopping the specified timer.
+ *
+ * @param[in] timer_id Id of timer to stop.
+ *
+ * @retval NRF_SUCCESS Timer was successfully stopped.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter.
+ * @retval NRF_ERROR_INVALID_STATE Application timer module has not been initialized, or timer
+ * has not been created.
+ * @retval NRF_ERROR_NO_MEM Timer operations queue was full.
+ */
+uint32_t app_timer_stop(app_timer_id_t timer_id);
+
+/**@brief Function for stopping all running timers.
+ *
+ * @retval NRF_SUCCESS All timers were successfully stopped.
+ * @retval NRF_ERROR_INVALID_STATE Application timer module has not been initialized.
+ * @retval NRF_ERROR_NO_MEM Timer operations queue was full.
+ */
+uint32_t app_timer_stop_all(void);
+
+/**@brief Function for returning the current value of the RTC1 counter. The
+ * value includes overflow bits to extend the range to 64-bits.
+ *
+ * @param[out] p_ticks Current value of the RTC1 counter.
+ *
+ * @retval NRF_SUCCESS Counter was successfully read.
+ */
+uint32_t app_timer_cnt_get(uint64_t * p_ticks);
+
+/**@brief Function for computing the difference between two RTC1 counter values.
+ *
+ * @param[in] ticks_to Value returned by app_timer_cnt_get().
+ * @param[in] ticks_from Value returned by app_timer_cnt_get().
+ * @param[out] p_ticks_diff Number of ticks from ticks_from to ticks_to.
+ *
+ * @retval NRF_SUCCESS Counter difference was successfully computed.
+ */
+uint32_t app_timer_cnt_diff_compute(uint32_t ticks_to,
+ uint32_t ticks_from,
+ uint32_t * p_ticks_diff);
+
+
+// Type and functions for connecting the timer to the scheduler:
+
+/**@cond NO_DOXYGEN */
+typedef struct
+{
+ app_timer_timeout_handler_t timeout_handler;
+ void * p_context;
+} app_timer_event_t;
+
+static __INLINE void app_timer_evt_get(void * p_event_data, uint16_t event_size)
+{
+ app_timer_event_t * p_timer_event = (app_timer_event_t *)p_event_data;
+
+ APP_ERROR_CHECK_BOOL(event_size == sizeof(app_timer_event_t));
+ p_timer_event->timeout_handler(p_timer_event->p_context);
+}
+
+static __INLINE uint32_t app_timer_evt_schedule(app_timer_timeout_handler_t timeout_handler,
+ void * p_context)
+{
+ app_timer_event_t timer_event;
+
+ timer_event.timeout_handler = timeout_handler;
+ timer_event.p_context = p_context;
+
+ return app_sched_event_put(&timer_event, sizeof(timer_event), app_timer_evt_get);
+}
+/**@endcond */
+
+#ifdef __cplusplus
+}
+#endif // #ifdef __cplusplus
+
+#endif // APP_TIMER_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_HRM1017/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_trace.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,55 @@
+#ifndef __DEBUG_H_
+#define __DEBUG_H_
+
+#include <stdint.h>
+#include <stdio.h>
+
+/**
+ * @defgroup app_trace Debug Logger
+ * @ingroup app_common
+ * @{
+ * @brief Enables debug logs/ trace over UART.
+ * @details Enables debug logs/ trace over UART. Tracing is enabled only if
+ * ENABLE_DEBUG_LOG_SUPPORT is defined in the project.
+ */
+#ifdef ENABLE_DEBUG_LOG_SUPPORT
+/**
+ * @brief Module Initialization.
+ *
+ * @details Initializes the module to use UART as trace output.
+ *
+ * @warning This function will configure UART using default board configuration (described in @ref nrf51_setups).
+ * Do not call this function if UART is configured from a higher level in the application.
+ */
+void app_trace_init(void);
+
+/**
+ * @brief Log debug messages.
+ *
+ * @details This API logs messages over UART. The module must be initialized before using this API.
+ *
+ * @note Though this is currently a macro, it should be used used and treated as function.
+ */
+#define app_trace_log printf
+
+/**
+ * @brief Dump auxiliary byte buffer to the debug trace.
+ *
+ * @details This API logs messages over UART. The module must be initialized before using this API.
+ *
+ * @param[in] p_buffer Buffer to be dumped on the debug trace.
+ * @param[in] len Size of the buffer.
+ */
+void app_trace_dump(uint8_t * p_buffer, uint32_t len);
+
+#else // ENABLE_DEBUG_LOG_SUPPORT
+
+#define app_trace_init(...)
+#define app_trace_log(...)
+#define app_trace_dump(...)
+
+#endif // ENABLE_DEBUG_LOG_SUPPORT
+
+/** @} */
+
+#endif //__DEBUG_H_
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_HRM1017/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_uart.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,286 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/**@file
+ *
+ * @defgroup app_uart UART module
+ * @{
+ * @ingroup app_common
+ *
+ * @brief UART module interface.
+ */
+
+#ifndef APP_UART_H__
+#define APP_UART_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "app_util_platform.h"
+
+#define UART_PIN_DISCONNECTED 0xFFFFFFFF /**< Value indicating that no pin is connected to this UART register. */
+
+/**@brief UART Flow Control modes for the peripheral.
+ */
+typedef enum
+{
+ APP_UART_FLOW_CONTROL_DISABLED, /**< UART Hw Flow Control is disabled. */
+ APP_UART_FLOW_CONTROL_ENABLED, /**< Standard UART Hw Flow Control is enabled. */
+ APP_UART_FLOW_CONTROL_LOW_POWER /**< Specialized UART Hw Flow Control is used. The Low Power setting allows the nRF51 to Power Off the UART module when CTS is in-active, and re-enabling the UART when the CTS signal becomes active. This allows the nRF51 to safe power by only using the UART module when it is needed by the remote site. */
+} app_uart_flow_control_t;
+
+/**@brief UART communication structure holding configuration settings for the peripheral.
+ */
+typedef struct
+{
+ uint8_t rx_pin_no; /**< RX pin number. */
+ uint8_t tx_pin_no; /**< TX pin number. */
+ uint8_t rts_pin_no; /**< RTS pin number, only used if flow control is enabled. */
+ uint8_t cts_pin_no; /**< CTS pin number, only used if flow control is enabled. */
+ app_uart_flow_control_t flow_control; /**< Flow control setting, if flow control is used, the system will use low power UART mode, based on CTS signal. */
+ bool use_parity; /**< Even parity if TRUE, no parity if FALSE. */
+ uint32_t baud_rate; /**< Baud rate configuration. */
+} app_uart_comm_params_t;
+
+/**@brief UART buffer for transmitting/receiving data.
+ */
+typedef struct
+{
+ uint8_t * rx_buf; /**< Pointer to the RX buffer. */
+ uint32_t rx_buf_size; /**< Size of the RX buffer. */
+ uint8_t * tx_buf; /**< Pointer to the TX buffer. */
+ uint32_t tx_buf_size; /**< Size of the TX buffer. */
+} app_uart_buffers_t;
+
+/**@brief Enumeration describing current state of the UART.
+ *
+ * @details The connection state can be fetched by the application using the function call
+ * @ref app_uart_get_connection_state.
+ * When hardware flow control is used
+ * - APP_UART_CONNECTED: Communication is ongoing.
+ * - APP_UART_DISCONNECTED: No communication is ongoing.
+ *
+ * When no hardware flow control is used
+ * - APP_UART_CONNECTED: Always returned as bytes can always be received/transmitted.
+ */
+typedef enum
+{
+ APP_UART_DISCONNECTED, /**< State indicating that the UART is disconnected and cannot receive or transmit bytes. */
+ APP_UART_CONNECTED /**< State indicating that the UART is connected and ready to receive or transmit bytes. If flow control is disabled, the state will always be connected. */
+} app_uart_connection_state_t;
+
+/**@brief Enumeration which defines events used by the UART module upon data reception or error.
+ *
+ * @details The event type is used to indicate the type of additional information in the event
+ * @ref app_uart_evt_t.
+ */
+typedef enum
+{
+ APP_UART_DATA_READY, /**< An event indicating that UART data has been received. The data is available in the FIFO and can be fetched using @ref app_uart_get. */
+ APP_UART_FIFO_ERROR, /**< An error in the FIFO module used by the app_uart module has occured. The FIFO error code is stored in app_uart_evt_t.data.error_code field. */
+ APP_UART_COMMUNICATION_ERROR, /**< An communication error has occured during reception. The error is stored in app_uart_evt_t.data.error_communication field. */
+ APP_UART_TX_EMPTY, /**< An event indicating that UART has completed transmission of all available data in the TX FIFO. */
+ APP_UART_DATA, /**< An event indicating that UART data has been received, and data is present in data field. This event is only used when no FIFO is configured. */
+} app_uart_evt_type_t;
+
+/**@brief Struct containing events from the UART module.
+ *
+ * @details The app_uart_evt_t is used to notify the application of asynchronous events when data
+ * are received on the UART peripheral or in case an error occured during data reception.
+ */
+typedef struct
+{
+ app_uart_evt_type_t evt_type; /**< Type of event. */
+ union
+ {
+ uint32_t error_communication; /**< Field used if evt_type is: APP_UART_COMMUNICATION_ERROR. This field contains the value in the ERRORSRC register for the UART peripheral. The UART_ERRORSRC_x defines from @ref nrf51_bitfields.h can be used to parse the error code. See also the nRF51 Series Reference Manual for specification. */
+ uint32_t error_code; /**< Field used if evt_type is: NRF_ERROR_x. Additional status/error code if the error event type is APP_UART_FIFO_ERROR. This error code refer to errors defined in nrf_error.h. */
+ uint8_t value; /**< Field used if evt_type is: NRF_ERROR_x. Additional status/error code if the error event type is APP_UART_FIFO_ERROR. This error code refer to errors defined in nrf_error.h. */
+ } data;
+} app_uart_evt_t;
+
+/**@brief Function for handling app_uart event callback.
+ *
+ * @details Upon an event in the app_uart module this callback function will be called to notify
+ * the applicatioon about the event.
+ *
+ * @param[in] p_app_uart_event Pointer to UART event.
+ */
+
+
+typedef void (* app_uart_event_handler_t) (app_uart_evt_t * p_app_uart_event);
+
+/**@brief Macro for safe initialization of the UART module in a single user instance when using
+ * a FIFO together with UART.
+ *
+ * @param[in] P_COMM_PARAMS Pointer to a UART communication structure: app_uart_comm_params_t
+ * @param[in] RX_BUF_SIZE Size of desired RX buffer, must be a power of 2 or ZERO (No FIFO).
+ * @param[in] TX_BUF_SIZE Size of desired TX buffer, must be a power of 2 or ZERO (No FIFO).
+ * @param[in] EVENT_HANDLER Event handler function to be called when an event occurs in the
+ * UART module.
+ * @param[in] IRQ_PRIO IRQ priority, app_irq_priority_t, for the UART module irq handler.
+ * @param[out] ERR_CODE The return value of the UART initialization function will be
+ * written to this parameter.
+ *
+ * @note Since this macro allocates a buffer and registers the module as a GPIOTE user when flow
+ * control is enabled, it must only be called once.
+ */
+#define APP_UART_FIFO_INIT(P_COMM_PARAMS, RX_BUF_SIZE, TX_BUF_SIZE, EVT_HANDLER, IRQ_PRIO, ERR_CODE) \
+ do \
+ { \
+ uint16_t APP_UART_UID = 0; \
+ app_uart_buffers_t buffers; \
+ static uint8_t rx_buf[RX_BUF_SIZE]; \
+ static uint8_t tx_buf[TX_BUF_SIZE]; \
+ \
+ buffers.rx_buf = rx_buf; \
+ buffers.rx_buf_size = sizeof (rx_buf); \
+ buffers.tx_buf = tx_buf; \
+ buffers.tx_buf_size = sizeof (tx_buf); \
+ ERR_CODE = app_uart_init(P_COMM_PARAMS, &buffers, EVT_HANDLER, IRQ_PRIO, &APP_UART_UID); \
+ } while (0)
+
+/**@brief Macro for safe initialization of the UART module in a single user instance.
+ *
+ * @param[in] P_COMM_PARAMS Pointer to a UART communication structure: app_uart_comm_params_t
+ * @param[in] EVENT_HANDLER Event handler function to be called when an event occurs in the
+ * UART module.
+ * @param[in] IRQ_PRIO IRQ priority, app_irq_priority_t, for the UART module irq handler.
+ * @param[out] ERR_CODE The return value of the UART initialization function will be
+ * written to this parameter.
+ *
+ * @note Since this macro allocates registers the module as a GPIOTE user when flow control is
+ * enabled, it must only be called once.
+ */
+#define APP_UART_INIT(P_COMM_PARAMS, EVT_HANDLER, IRQ_PRIO, ERR_CODE) \
+ do \
+ { \
+ uint16_t APP_UART_UID = 0; \
+ ERR_CODE = app_uart_init(P_COMM_PARAMS, NULL, EVT_HANDLER, IRQ_PRIO, &APP_UART_UID); \
+ } while (0)
+
+/**@brief Function for initializing the UART module. Use this initialization when several instances of the UART
+ * module are needed.
+ *
+ * @details This initialization will return a UART user id for the caller. The UART user id must be
+ * used upon re-initialization of the UART or closing of the module for the user.
+ * If single instance usage is needed, the APP_UART_INIT() macro should be used instead.
+ *
+ * @note Normally single instance initialization should be done using the APP_UART_INIT() or
+ * APP_UART_INIT_FIFO() macro depending on whether the FIFO should be used by the UART, as
+ * that will allocate the buffers needed by the UART module (including aligning the buffer
+ * correctly).
+
+ * @param[in] p_comm_params Pin and communication parameters.
+ * @param[in] p_buffers RX and TX buffers, NULL is FIFO is not used.
+ * @param[in] error_handler Function to be called in case of an error.
+ * @param[in] app_irq_priority Interrupt priority level.
+ * @param[in,out] p_uart_uid User id for the UART module. The p_uart_uid must be used if
+ * re-initialization and/or closing of the UART module is needed.
+ * If the value pointed to by p_uart_uid is zero, this is
+ * considdered a first time initialization. Otherwise this is
+ * considered a re-initialization for the user with id *p_uart_uid.
+ *
+ * @retval NRF_SUCCESS If successful initialization.
+ * @retval NRF_ERROR_INVALID_LENGTH If a provided buffer is not a power of two.
+ * @retval NRF_ERROR_NULL If one of the provided buffers is a NULL pointer.
+ *
+ * Those errors are propagated by the UART module to the caller upon registration when Hardware Flow
+ * Control is enabled. When Hardware Flow Control is not used, those errors cannot occur.
+ * @retval NRF_ERROR_INVALID_STATE The GPIOTE module is not in a valid state when registering
+ * the UART module as a user.
+ * @retval NRF_ERROR_INVALID_PARAM The UART module provides an invalid callback function when
+ * registering the UART module as a user.
+ * Or the value pointed to by *p_uart_uid is not a valid
+ * GPIOTE number.
+ * @retval NRF_ERROR_NO_MEM GPIOTE module has reached the maximum number of users.
+ */
+uint32_t app_uart_init(const app_uart_comm_params_t * p_comm_params,
+ app_uart_buffers_t * p_buffers,
+ app_uart_event_handler_t error_handler,
+ app_irq_priority_t irq_priority,
+ uint16_t * p_uart_uid);
+
+/**@brief Function for getting a byte from the UART.
+ *
+ * @details This function will get the next byte from the RX buffer. If the RX buffer is empty
+ * an error code will be returned and the app_uart module will generate an event upon
+ * reception of the first byte which is added to the RX buffer.
+ *
+ * @param[out] p_byte Pointer to an address where next byte received on the UART will be copied.
+ *
+ * @retval NRF_SUCCESS If a byte has been received and pushed to the pointer provided.
+ * @retval NRF_ERROR_NOT_FOUND If no byte is available in the RX buffer of the app_uart module.
+ */
+uint32_t app_uart_get(uint8_t * p_byte);
+
+/**@brief Function for putting a byte on the UART.
+ *
+ * @details This call is non-blocking.
+ *
+ * @param[in] byte Byte to be transmitted on the UART.
+ *
+ * @retval NRF_SUCCESS If the byte was succesfully put on the TX buffer for transmission.
+ * @retval NRF_ERROR_NO_MEM If no more space is available in the TX buffer.
+ * NRF_ERROR_NO_MEM may occur if flow control is enabled and CTS signal
+ * is high for a long period and the buffer fills up.
+ */
+uint32_t app_uart_put(uint8_t byte);
+
+/**@brief Function for getting the current state of the UART.
+ *
+ * @details If flow control is disabled, the state is assumed to always be APP_UART_CONNECTED.
+ *
+ * When using flow control the state will be controlled by the CTS. If CTS is set active
+ * by the remote side, or the app_uart module is in the process of transmitting a byte,
+ * app_uart is in APP_UART_CONNECTED state. If CTS is set inactive by remote side app_uart
+ * will not get into APP_UART_DISCONNECTED state until the last byte in the TXD register
+ * is fully transmitted.
+ *
+ * Internal states in the state machine are mapped to the general connected/disconnected
+ * states in the following ways:
+ *
+ * - UART_ON = CONNECTED
+ * - UART_READY = CONNECTED
+ * - UART_WAIT = CONNECTED
+ * - UART_OFF = DISCONNECTED.
+ *
+ * @param[out] p_connection_state Current connection state of the UART.
+ *
+ * @retval NRF_SUCCESS The connection state was succesfully retrieved.
+ */
+uint32_t app_uart_get_connection_state(app_uart_connection_state_t * p_connection_state);
+
+/**@brief Function for flushing the RX and TX buffers (Only valid if FIFO is used).
+ * This function does nothing if FIFO is not used.
+ *
+ * @retval NRF_SUCCESS Flushing completed (Current implementation will always succeed).
+ */
+uint32_t app_uart_flush(void);
+
+/**@brief Function for closing the UART module.
+ *
+ * @details This function will close any on-going UART transmissions and disable itself in the
+ * GPTIO module.
+ *
+ * @param[in] app_uart_uid User id for the UART module. The app_uart_uid must be identical to the
+ * UART id returned on initialization and which is currently in use.
+
+ * @retval NRF_SUCCESS If successfully closed.
+ * @retval NRF_ERROR_INVALID_PARAM If an invalid user id is provided or the user id differs from
+ * the current active user.
+ */
+uint32_t app_uart_close(uint16_t app_uart_id);
+
+
+#endif //APP_UART_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_HRM1017/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_util.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,232 @@
+/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup app_util Utility Functions and Definitions
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Various types and definitions available to all applications.
+ */
+
+#ifndef APP_UTIL_H__
+#define APP_UTIL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "compiler_abstraction.h"
+
+enum
+{
+ UNIT_0_625_MS = 625, /**< Number of microseconds in 0.625 milliseconds. */
+ UNIT_1_25_MS = 1250, /**< Number of microseconds in 1.25 milliseconds. */
+ UNIT_10_MS = 10000 /**< Number of microseconds in 10 milliseconds. */
+};
+
+/**@brief Macro for doing static (i.e. compile time) assertion.
+ *
+ * @note If the assertion fails when compiling using Keil, the compiler will report error message
+ * "error: #94: the size of an array must be greater than zero" (while gcc will list the
+ * symbol static_assert_failed, making the error message more readable).
+ * If the supplied expression can not be evaluated at compile time, Keil will report
+ * "error: #28: expression must have a constant value".
+ *
+ * @note The macro is intentionally implemented not using do while(0), allowing it to be used
+ * outside function blocks (e.g. close to global type- and variable declarations).
+ * If used in a code block, it must be used before any executable code in this block.
+ *
+ * @param[in] EXPR Constant expression to be verified.
+ */
+
+#if defined(__GNUC__)
+#define STATIC_ASSERT(EXPR) typedef char __attribute__((unused)) static_assert_failed[(EXPR) ? 1 : -1]
+#else
+#define STATIC_ASSERT(EXPR) typedef char static_assert_failed[(EXPR) ? 1 : -1]
+#endif
+
+
+/**@brief type for holding an encoded (i.e. little endian) 16 bit unsigned integer. */
+typedef uint8_t uint16_le_t[2];
+
+/**@brief type for holding an encoded (i.e. little endian) 32 bit unsigned integer. */
+typedef uint8_t uint32_le_t[4];
+
+/**@brief Byte array type. */
+typedef struct
+{
+ uint16_t size; /**< Number of array entries. */
+ uint8_t * p_data; /**< Pointer to array entries. */
+} uint8_array_t;
+
+/**@brief Perform rounded integer division (as opposed to truncating the result).
+ *
+ * @param[in] A Numerator.
+ * @param[in] B Denominator.
+ *
+ * @return Rounded (integer) result of dividing A by B.
+ */
+#define ROUNDED_DIV(A, B) (((A) + ((B) / 2)) / (B))
+
+/**@brief Check if the integer provided is a power of two.
+ *
+ * @param[in] A Number to be tested.
+ *
+ * @return true if value is power of two.
+ * @return false if value not power of two.
+ */
+#define IS_POWER_OF_TWO(A) ( ((A) != 0) && ((((A) - 1) & (A)) == 0) )
+
+/**@brief To convert ticks to millisecond
+ * @param[in] time Number of millseconds that needs to be converted.
+ * @param[in] resolution Units to be converted.
+ */
+#define MSEC_TO_UNITS(TIME, RESOLUTION) (((TIME) * 1000) / (RESOLUTION))
+
+
+/**@brief Perform integer division, making sure the result is rounded up.
+ *
+ * @details One typical use for this is to compute the number of objects with size B is needed to
+ * hold A number of bytes.
+ *
+ * @param[in] A Numerator.
+ * @param[in] B Denominator.
+ *
+ * @return Integer result of dividing A by B, rounded up.
+ */
+#define CEIL_DIV(A, B) \
+ /*lint -save -e573 */ \
+ ((((A) - 1) / (B)) + 1) \
+ /*lint -restore */
+
+/**@brief Function for encoding a uint16 value.
+ *
+ * @param[in] value Value to be encoded.
+ * @param[out] p_encoded_data Buffer where the encoded data is to be written.
+ *
+ * @return Number of bytes written.
+ */
+static __INLINE uint8_t uint16_encode(uint16_t value, uint8_t * p_encoded_data)
+{
+ p_encoded_data[0] = (uint8_t) ((value & 0x00FF) >> 0);
+ p_encoded_data[1] = (uint8_t) ((value & 0xFF00) >> 8);
+ return sizeof(uint16_t);
+}
+
+/**@brief Function for encoding a uint32 value.
+ *
+ * @param[in] value Value to be encoded.
+ * @param[out] p_encoded_data Buffer where the encoded data is to be written.
+ *
+ * @return Number of bytes written.
+ */
+static __INLINE uint8_t uint32_encode(uint32_t value, uint8_t * p_encoded_data)
+{
+ p_encoded_data[0] = (uint8_t) ((value & 0x000000FF) >> 0);
+ p_encoded_data[1] = (uint8_t) ((value & 0x0000FF00) >> 8);
+ p_encoded_data[2] = (uint8_t) ((value & 0x00FF0000) >> 16);
+ p_encoded_data[3] = (uint8_t) ((value & 0xFF000000) >> 24);
+ return sizeof(uint32_t);
+}
+
+/**@brief Function for decoding a uint16 value.
+ *
+ * @param[in] p_encoded_data Buffer where the encoded data is stored.
+ *
+ * @return Decoded value.
+ */
+static __INLINE uint16_t uint16_decode(const uint8_t * p_encoded_data)
+{
+ return ( (((uint16_t)((uint8_t *)p_encoded_data)[0])) |
+ (((uint16_t)((uint8_t *)p_encoded_data)[1]) << 8 ));
+}
+
+/**@brief Function for decoding a uint32 value.
+ *
+ * @param[in] p_encoded_data Buffer where the encoded data is stored.
+ *
+ * @return Decoded value.
+ */
+static __INLINE uint32_t uint32_decode(const uint8_t * p_encoded_data)
+{
+ return ( (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0) |
+ (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8) |
+ (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16) |
+ (((uint32_t)((uint8_t *)p_encoded_data)[3]) << 24 ));
+}
+
+/** @brief Function for converting the input voltage (in milli volts) into percentage of 3.0 Volts.
+ *
+ * @details The calculation is based on a linearized version of the battery's discharge
+ * curve. 3.0V returns 100% battery level. The limit for power failure is 2.1V and
+ * is considered to be the lower boundary.
+ *
+ * The discharge curve for CR2032 is non-linear. In this model it is split into
+ * 4 linear sections:
+ * - Section 1: 3.0V - 2.9V = 100% - 42% (58% drop on 100 mV)
+ * - Section 2: 2.9V - 2.74V = 42% - 18% (24% drop on 160 mV)
+ * - Section 3: 2.74V - 2.44V = 18% - 6% (12% drop on 300 mV)
+ * - Section 4: 2.44V - 2.1V = 6% - 0% (6% drop on 340 mV)
+ *
+ * These numbers are by no means accurate. Temperature and
+ * load in the actual application is not accounted for!
+ *
+ * @param[in] mvolts The voltage in mV
+ *
+ * @return Battery level in percent.
+*/
+static __INLINE uint8_t battery_level_in_percent(const uint16_t mvolts)
+{
+ uint8_t battery_level;
+
+ if (mvolts >= 3000)
+ {
+ battery_level = 100;
+ }
+ else if (mvolts > 2900)
+ {
+ battery_level = 100 - ((3000 - mvolts) * 58) / 100;
+ }
+ else if (mvolts > 2740)
+ {
+ battery_level = 42 - ((2900 - mvolts) * 24) / 160;
+ }
+ else if (mvolts > 2440)
+ {
+ battery_level = 18 - ((2740 - mvolts) * 12) / 300;
+ }
+ else if (mvolts > 2100)
+ {
+ battery_level = 6 - ((2440 - mvolts) * 6) / 340;
+ }
+ else
+ {
+ battery_level = 0;
+ }
+
+ return battery_level;
+}
+
+/**@brief Function for checking if a pointer value is aligned to a 4 byte boundary.
+ *
+ * @param[in] p Pointer value to be checked.
+ *
+ * @return TRUE if pointer is aligned to a 4 byte boundary, FALSE otherwise.
+ */
+static __INLINE bool is_word_aligned(void * p)
+{
+ return (((uintptr_t)p & 0x03) == 0);
+}
+
+#endif // APP_UTIL_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_HRM1017/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/crc16.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,52 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup crc_compute CRC compute
+ * @{
+ * @ingroup hci_transport
+ *
+ * @brief This module implements the CRC-16 calculation in the blocks.
+ */
+
+#ifndef CRC16_H__
+#define CRC16_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@brief Function for calculating CRC-16 in blocks.
+ *
+ * Feed each consecutive data block into this function, along with the current value of p_crc as
+ * returned by the previous call of this function. The first call of this function should pass NULL
+ * as the initial value of the crc in p_crc.
+ *
+ * @param[in] p_data The input data block for computation.
+ * @param[in] size The size of the input data block in bytes.
+ * @param[in] p_crc The previous calculated CRC-16 value or NULL if first call.
+ *
+ * @return The updated CRC-16 value, based on the input supplied.
+ */
+uint16_t crc16_compute(const uint8_t * p_data, uint32_t size, const uint16_t * p_crc);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif // CRC16_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_HRM1017/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hal_transport.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,227 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/**@file
+ *
+ * @defgroup hci_transport HCI Transport
+ * @{
+ * @ingroup app_common
+ *
+ * @brief HCI transport module implementation.
+ *
+ * This module implements certain specific features from the three-wire UART transport layer,
+ * defined by the Bluetooth specification version 4.0 [Vol 4] part D.
+ *
+ * \par Features supported
+ * - Transmission and reception of Vendor Specific HCI packet type application packets.
+ * - Transmission and reception of reliable packets: defined by chapter 6 of the specification.
+ *
+ * \par Features not supported
+ * - Link establishment procedure: defined by chapter 8 of the specification.
+ * - Low power: defined by chapter 9 of the specification.
+ *
+ * \par Implementation specific behaviour
+ * - As Link establishment procedure is not supported following static link configuration parameters
+ * are used:
+ * + TX window size is 1.
+ * + 16 bit CCITT-CRC must be used.
+ * + Out of frame software flow control not supported.
+ * + Parameters specific for resending reliable packets are compile time configurable (clarifed
+ * later in this document).
+ * + Acknowledgement packet transmissions are not timeout driven , meaning they are delivered for
+ * transmission within same context which the corresponding application packet was received.
+ *
+ * \par Implementation specific limitations
+ * Current implementation has the following limitations which will have impact to system wide
+ * behaviour:
+ * - Delayed acknowledgement scheduling not implemented:
+ * There exists a possibility that acknowledgement TX packet and application TX packet will collide
+ * in the TX pipeline having the end result that acknowledgement packet will be excluded from the TX
+ * pipeline which will trigger the retransmission algorithm within the peer protocol entity.
+ * - Delayed retransmission scheduling not implemented:
+ * There exists a possibility that retransmitted application TX packet and acknowledgement TX packet
+ * will collide in the TX pipeline having the end result that retransmitted application TX packet
+ * will be excluded from the TX pipeline.
+ * - Processing of the acknowledgement number from RX application packets:
+ * Acknowledgement number is not processed from the RX application packets having the end result
+ * that unnecessary application packet retransmissions can occur.
+ *
+ * The application TX packet processing flow is illustrated by the statemachine below.
+ *
+ * @image html hci_transport_tx_sm.png "TX - application packet statemachine"
+ *
+ * \par Component specific configuration options
+ *
+ * The following compile time configuration options are available, and used to configure the
+ * application TX packet retransmission interval, in order to suite various application specific
+ * implementations:
+ * - MAC_PACKET_SIZE_IN_BITS Maximum size of a single application packet in bits.
+ * - USED_BAUD_RATE Used uart baudrate.
+ *
+ * The following compile time configuration option is available to configure module specific
+ * behaviour:
+ * - MAX_RETRY_COUNT Max retransmission retry count for applicaton packets.
+ */
+
+#ifndef HCI_TRANSPORT_H__
+#define HCI_TRANSPORT_H__
+
+#include <stdint.h>
+#include "nrf_error.h"
+
+#define HCI_TRANSPORT_PKT_HEADER_SIZE (2) /**< Size of transport packet header */
+
+/**@brief Generic event callback function events. */
+typedef enum
+{
+ HCI_TRANSPORT_RX_RDY, /**< An event indicating that RX packet is ready for read. */
+ HCI_TRANSPORT_EVT_TYPE_MAX /**< Enumeration upper bound. */
+} hci_transport_evt_type_t;
+
+/**@brief Struct containing events from the Transport layer.
+ */
+typedef struct
+{
+ hci_transport_evt_type_t evt_type; /**< Type of event. */
+} hci_transport_evt_t;
+
+/**@brief Transport layer generic event callback function type.
+ *
+ * @param[in] event Transport layer event.
+ */
+typedef void (*hci_transport_event_handler_t)(hci_transport_evt_t event);
+
+/**@brief TX done event callback function result codes. */
+typedef enum
+{
+ HCI_TRANSPORT_TX_DONE_SUCCESS, /**< Transmission success, peer transport entity has acknowledged the transmission. */
+ HCI_TRANSPORT_TX_DONE_FAILURE /**< Transmission failure. */
+} hci_transport_tx_done_result_t;
+
+/**@brief Transport layer TX done event callback function type.
+ *
+ * @param[in] result TX done event result code.
+ */
+typedef void (*hci_transport_tx_done_handler_t)(hci_transport_tx_done_result_t result);
+
+/**@brief Function for registering a generic event handler.
+ *
+ * @note Multiple registration requests will overwrite any possible existing registration.
+ *
+ * @param[in] event_handler The function to be called by the transport layer upon an event.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_evt_handler_reg(hci_transport_event_handler_t event_handler);
+
+/**@brief Function for registering a handler for TX done event.
+ *
+ * @note Multiple registration requests will overwrite any possible existing registration.
+ *
+ * @param[in] event_handler The function to be called by the transport layer upon TX done
+ * event.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_tx_done_register(hci_transport_tx_done_handler_t event_handler);
+
+/**@brief Function for opening the transport channel and initializing the transport layer.
+ *
+ * @warning Must not be called for a channel which has been allready opened.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_INTERNAL Operation failure. Internal error ocurred.
+ */
+uint32_t hci_transport_open(void);
+
+/**@brief Function for closing the transport channel.
+ *
+ * @note Can be called multiple times and also for not opened channel.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_transport_close(void);
+
+/**@brief Function for allocating tx packet memory.
+ *
+ * @param[out] pp_memory Pointer to the packet data.
+ *
+ * @retval NRF_SUCCESS Operation success. Memory was allocated.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No memory available.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_tx_alloc(uint8_t ** pp_memory);
+
+/**@brief Function for freeing tx packet memory.
+ *
+ * @note Memory management works in FIFO principle meaning that free order must match the alloc
+ * order.
+ *
+ * @retval NRF_SUCCESS Operation success. Memory was freed.
+ */
+uint32_t hci_transport_tx_free(void);
+
+/**@brief Function for writing a packet.
+ *
+ * @note Completion of this method does not guarantee that actual peripheral transmission would
+ * have completed.
+ *
+ * @note In case of 0 byte packet length write request, message will consist of only transport
+ * module specific headers.
+ *
+ * @note The buffer provided to this function must be allocated through @ref hci_transport_tx_alloc
+ * function.
+ *
+ * @retval NRF_SUCCESS Operation success. Packet was added to the transmission queue
+ * and an event will be send upon transmission completion.
+ * @retval NRF_ERROR_NO_MEM Operation failure. Transmission queue is full and packet was not
+ * added to the transmission queue. User should wait for
+ * a appropriate event prior issuing this operation again.
+ * @retval NRF_ERROR_DATA_SIZE Operation failure. Packet size exceeds limit.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ * @retval NRF_ERROR_INVALID_STATE Operation failure. Channel is not open.
+ * @retval NRF_ERROR_INVALID_ADDR Operation failure. Buffer provided is not allocated through
+ * hci_transport_tx_alloc function.
+ */
+uint32_t hci_transport_pkt_write(const uint8_t * p_buffer, uint16_t length);
+
+/**@brief Function for extracting received packet.
+ *
+ * @note Extracted memory can't be reused by the underlying transport layer untill freed by call to
+ * hci_transport_rx_pkt_consume().
+ *
+ * @param[out] pp_buffer Pointer to the packet data.
+ * @param[out] p_length Length of packet data in bytes.
+ *
+ * @retval NRF_SUCCESS Operation success. Packet was extracted.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to extract.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_rx_pkt_extract(uint8_t ** pp_buffer, uint16_t * p_length);
+
+/**@brief Function for consuming extracted packet described by p_buffer.
+ *
+ * RX memory pointed to by p_buffer is freed and can be reused by the underlying transport layer.
+ *
+ * @param[in] p_buffer Pointer to the buffer that has been consumed.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to consume.
+ * @retval NRF_ERROR_INVALID_ADDR Operation failure. Not a valid pointer.
+ */
+uint32_t hci_transport_rx_pkt_consume(uint8_t * p_buffer);
+
+#endif // HCI_TRANSPORT_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_HRM1017/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_mem_pool.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,132 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup memory_pool Memory pool
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Memory pool implementation
+ *
+ * Memory pool implementation, based on circular buffer data structure, which supports asynchronous
+ * processing of RX data. The current default implementation supports 1 TX buffer and 4 RX buffers.
+ * The memory managed by the pool is allocated from static storage instead of heap. The internal
+ * design of the circular buffer implementing the RX memory layout is illustrated in the picture
+ * below.
+ *
+ * @image html memory_pool.png "Circular buffer design"
+ *
+ * The expected call order for the RX APIs is as follows:
+ * - hci_mem_pool_rx_produce
+ * - hci_mem_pool_rx_data_size_set
+ * - hci_mem_pool_rx_extract
+ * - hci_mem_pool_rx_consume
+ *
+ * @warning If the above mentioned expected call order is violated the end result can be undefined.
+ *
+ * \par Component specific configuration options
+ *
+ * The following compile time configuration options are available to suit various implementations:
+ * - TX_BUF_SIZE TX buffer size in bytes.
+ * - RX_BUF_SIZE RX buffer size in bytes.
+ * - RX_BUF_QUEUE_SIZE RX buffer element size.
+ */
+
+#ifndef HCI_MEM_POOL_H__
+#define HCI_MEM_POOL_H__
+
+#include <stdint.h>
+#include "nrf_error.h"
+
+/**@brief Function for opening the module.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_mem_pool_open(void);
+
+/**@brief Function for closing the module.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_mem_pool_close(void);
+
+/**@brief Function for allocating requested amount of TX memory.
+ *
+ * @param[out] pp_buffer Pointer to the allocated memory.
+ *
+ * @retval NRF_SUCCESS Operation success. Memory was allocated.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No memory available for allocation.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_mem_pool_tx_alloc(void ** pp_buffer);
+
+/**@brief Function for freeing previously allocated TX memory.
+ *
+ * @note Memory management follows the FIFO principle meaning that free() order must match the
+ * alloc(...) order, which is the reason for omitting exact memory block identifier as an
+ * input parameter.
+ *
+ * @retval NRF_SUCCESS Operation success. Memory was freed.
+ */
+uint32_t hci_mem_pool_tx_free(void);
+
+/**@brief Function for producing a free RX memory block for usage.
+ *
+ * @note Upon produce request amount being 0, NRF_SUCCESS is returned.
+ *
+ * @param[in] length Amount, in bytes, of free memory to be produced.
+ * @param[out] pp_buffer Pointer to the allocated memory.
+ *
+ * @retval NRF_SUCCESS Operation success. Free RX memory block produced.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No suitable memory available for allocation.
+ * @retval NRF_ERROR_DATA_SIZE Operation failure. Request size exceeds limit.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_mem_pool_rx_produce(uint32_t length, void ** pp_buffer);
+
+/**@brief Function for setting the length of the last produced RX memory block.
+ *
+ * @warning If call to this API is omitted the end result is that the following call to
+ * mem_pool_rx_extract will return incorrect data in the p_length output parameter.
+ *
+ * @param[in] length Amount, in bytes, of actual memory used.
+ *
+ * @retval NRF_SUCCESS Operation success. Length was set.
+ */
+uint32_t hci_mem_pool_rx_data_size_set(uint32_t length);
+
+/**@brief Function for extracting a packet, which has been filled with read data, for further
+ * processing.
+ *
+ * @param[out] pp_buffer Pointer to the packet data.
+ * @param[out] p_length Length of packet data in bytes.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to extract.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_mem_pool_rx_extract(uint8_t ** pp_buffer, uint32_t * p_length);
+
+/**@brief Function for freeing previously extracted packet, which has been filled with read data.
+ *
+ * @param[in] p_buffer Pointer to consumed buffer.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to free.
+ * @retval NRF_ERROR_INVALID_ADDR Operation failure. Not a valid pointer.
+ */
+uint32_t hci_mem_pool_rx_consume(uint8_t * p_buffer);
+
+#endif // HCI_MEM_POOL_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_HRM1017/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_mem_pool_internal.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,32 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup memory_pool_internal Memory Pool Internal
+ * @{
+ * @ingroup memory_pool
+ *
+ * @brief Memory pool internal definitions
+ */
+
+#ifndef MEM_POOL_INTERNAL_H__
+#define MEM_POOL_INTERNAL_H__
+
+#define TX_BUF_SIZE 600u /**< TX buffer size in bytes. */
+#define RX_BUF_SIZE TX_BUF_SIZE /**< RX buffer size in bytes. */
+
+#define RX_BUF_QUEUE_SIZE 4u /**< RX buffer element size. */
+
+#endif // MEM_POOL_INTERNAL_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_HRM1017/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_slip.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,129 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup hci_slip SLIP module
+ * @{
+ * @ingroup app_common
+ *
+ * @brief SLIP layer for supporting packet framing in HCI transport.
+ *
+ * @details This module implements SLIP packet framing as described in the Bluetooth Core
+ * Specification 4.0, Volume 4, Part D, Chapter 3 SLIP Layer.
+ *
+ * SLIP framing ensures that all packets sent on the UART are framed as:
+ * <0xC0> SLIP packet 1 <0xC0> <0xC0> SLIP packet 2 <0xC0>.
+ *
+ * The SLIP layer uses events to notify the upper layer when data transmission is complete
+ * and when a SLIP packet is received.
+ */
+
+#ifndef HCI_SLIP_H__
+#define HCI_SLIP_H__
+
+#include <stdint.h>
+
+/**@brief Event types from the SLIP Layer. */
+typedef enum
+{
+ HCI_SLIP_RX_RDY, /**< An event indicating that an RX packet is ready to be read. */
+ HCI_SLIP_TX_DONE, /**< An event indicating write completion of the TX packet provided in the function call \ref hci_slip_write . */
+ HCI_SLIP_RX_OVERFLOW, /**< An event indicating that RX data has been discarded due to lack of free RX memory. */
+ HCI_SLIP_ERROR, /**< An event indicating that an unrecoverable error has occurred. */
+ HCI_SLIP_EVT_TYPE_MAX /**< Enumeration upper bound. */
+} hci_slip_evt_type_t;
+
+/**@brief Structure containing an event from the SLIP layer.
+ */
+typedef struct
+{
+ hci_slip_evt_type_t evt_type; /**< Type of event. */
+ const uint8_t * packet; /**< This field contains a pointer to the packet for which the event relates, i.e. SLIP_TX_DONE: the packet transmitted, SLIP_RX_RDY: the packet received, SLIP_RX_OVERFLOW: The packet which overflow/or NULL if no receive buffer is available. */
+ uint32_t packet_length; /**< Packet length, i.e. SLIP_TX_DONE: Bytes transmitted, SLIP_RX_RDY: Bytes received, SLIP_RX_OVERFLOW: index at which the packet overflowed. */
+} hci_slip_evt_t;
+
+/**@brief Function for the SLIP layer event callback.
+ */
+typedef void (*hci_slip_event_handler_t)(hci_slip_evt_t event);
+
+/**@brief Function for registering the event handler provided as parameter and this event handler
+ * will be used by SLIP layer to send events described in \ref hci_slip_evt_type_t.
+ *
+ * @note Multiple registration requests will overwrite any existing registration.
+ *
+ * @param[in] event_handler This function is called by the SLIP layer upon an event.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_slip_evt_handler_register(hci_slip_event_handler_t event_handler);
+
+/**@brief Function for opening the SLIP layer. This function must be called before
+ * \ref hci_slip_write and before any data can be received.
+ *
+ * @note Can be called multiple times.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ *
+ * The SLIP layer module will propagate errors from underlying sub-modules.
+ * This implementation is using UART module as a physical transmission layer, and hci_slip_open
+ * executes \ref app_uart_init . For an extended error list, please refer to \ref app_uart_init .
+ */
+uint32_t hci_slip_open(void);
+
+/**@brief Function for closing the SLIP layer. After this function is called no data can be
+ * transmitted or received in this layer.
+ *
+ * @note This function can be called multiple times and also for an unopened channel.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_slip_close(void);
+
+/**@brief Function for writing a packet with SLIP encoding. Packet transmission is confirmed when
+ * the HCI_SLIP_TX_DONE event is received by the function caller.
+ *
+ * @param[in] p_buffer Pointer to the packet to transmit.
+ * @param[in] length Packet length, in bytes.
+ *
+ * @retval NRF_SUCCESS Operation success. Packet was encoded and added to the
+ * transmission queue and an event will be sent upon transmission
+ * completion.
+ * @retval NRF_ERROR_NO_MEM Operation failure. Transmission queue is full and packet was not
+ * added to the transmission queue. Application shall wait for
+ * the \ref HCI_SLIP_TX_DONE event. After HCI_SLIP_TX_DONE this
+ * function can be executed for transmission of next packet.
+ * @retval NRF_ERROR_INVALID_ADDR If a NULL pointer is provided.
+ * @retval NRF_ERROR_INVALID_STATE Operation failure. Module is not open.
+ */
+uint32_t hci_slip_write(const uint8_t * p_buffer, uint32_t length);
+
+/**@brief Function for registering a receive buffer. The receive buffer will be used for storage of
+ * received and SLIP decoded data.
+ * No data can be received by the SLIP layer until a receive buffer has been registered.
+ *
+ * @note The lifetime of the buffer must be valid during complete reception of data. A static
+ * buffer is recommended.
+ *
+ * @warning Multiple registration requests will overwrite any existing registration.
+ *
+ * @param[in] p_buffer Pointer to receive buffer. The received and SLIP decoded packet
+ * will be placed in this buffer.
+ * @param[in] length Buffer length, in bytes.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_slip_rx_buffer_register(uint8_t * p_buffer, uint32_t length);
+
+#endif // HCI_SLIP_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_HRM1017/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_transport.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,220 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/**@file
+ *
+ * @defgroup hci_transport HCI Transport
+ * @{
+ * @ingroup app_common
+ *
+ * @brief HCI transport module implementation.
+ *
+ * This module implements certain specific features from the three-wire UART transport layer,
+ * defined by the Bluetooth specification version 4.0 [Vol 4] part D.
+ *
+ * \par Features supported
+ * - Transmission and reception of Vendor Specific HCI packet type application packets.
+ * - Transmission and reception of reliable packets: defined by chapter 6 of the specification.
+ *
+ * \par Features not supported
+ * - Link establishment procedure: defined by chapter 8 of the specification.
+ * - Low power: defined by chapter 9 of the specification.
+ *
+ * \par Implementation specific behaviour
+ * - As Link establishment procedure is not supported following static link configuration parameters
+ * are used:
+ * + TX window size is 1.
+ * + 16 bit CCITT-CRC must be used.
+ * + Out of frame software flow control not supported.
+ * + Parameters specific for resending reliable packets are compile time configurable (clarifed
+ * later in this document).
+ * + Acknowledgement packet transmissions are not timeout driven , meaning they are delivered for
+ * transmission within same context which the corresponding application packet was received.
+ *
+ * \par Implementation specific limitations
+ * Current implementation has the following limitations which will have impact to system wide
+ * behaviour:
+ * - Delayed acknowledgement scheduling not implemented:
+ * There exists a possibility that acknowledgement TX packet and application TX packet will collide
+ * in the TX pipeline having the end result that acknowledgement packet will be excluded from the TX
+ * pipeline which will trigger the retransmission algorithm within the peer protocol entity.
+ * - Delayed retransmission scheduling not implemented:
+ * There exists a possibility that retransmitted application TX packet and acknowledgement TX packet
+ * will collide in the TX pipeline having the end result that retransmitted application TX packet
+ * will be excluded from the TX pipeline.
+ * - Processing of the acknowledgement number from RX application packets:
+ * Acknowledgement number is not processed from the RX application packets having the end result
+ * that unnecessary application packet retransmissions can occur.
+ *
+ * The application TX packet processing flow is illustrated by the statemachine below.
+ *
+ * @image html hci_transport_tx_sm.png "TX - application packet statemachine"
+ *
+ * \par Component specific configuration options
+ *
+ * The following compile time configuration options are available, and used to configure the
+ * application TX packet retransmission interval, in order to suite various application specific
+ * implementations:
+ * - MAC_PACKET_SIZE_IN_BITS Maximum size of a single application packet in bits.
+ * - USED_BAUD_RATE Used uart baudrate.
+ *
+ * The following compile time configuration option is available to configure module specific
+ * behaviour:
+ * - MAX_RETRY_COUNT Max retransmission retry count for applicaton packets.
+ */
+
+#ifndef HCI_TRANSPORT_H__
+#define HCI_TRANSPORT_H__
+
+#include <stdint.h>
+#include "nrf_error.h"
+
+/**@brief Generic event callback function events. */
+typedef enum
+{
+ HCI_TRANSPORT_RX_RDY, /**< An event indicating that RX packet is ready for read. */
+ HCI_TRANSPORT_EVT_TYPE_MAX /**< Enumeration upper bound. */
+} hci_transport_evt_type_t;
+
+/**@brief Struct containing events from the Transport layer.
+ */
+typedef struct
+{
+ hci_transport_evt_type_t evt_type; /**< Type of event. */
+} hci_transport_evt_t;
+
+/**@brief Transport layer generic event callback function type.
+ *
+ * @param[in] event Transport layer event.
+ */
+typedef void (*hci_transport_event_handler_t)(hci_transport_evt_t event);
+
+/**@brief TX done event callback function result codes. */
+typedef enum
+{
+ HCI_TRANSPORT_TX_DONE_SUCCESS, /**< Transmission success, peer transport entity has acknowledged the transmission. */
+ HCI_TRANSPORT_TX_DONE_FAILURE /**< Transmission failure. */
+} hci_transport_tx_done_result_t;
+
+/**@brief Transport layer TX done event callback function type.
+ *
+ * @param[in] result TX done event result code.
+ */
+typedef void (*hci_transport_tx_done_handler_t)(hci_transport_tx_done_result_t result);
+
+/**@brief Function for registering a generic event handler.
+ *
+ * @note Multiple registration requests will overwrite any possible existing registration.
+ *
+ * @param[in] event_handler The function to be called by the transport layer upon an event.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_evt_handler_reg(hci_transport_event_handler_t event_handler);
+
+/**@brief Function for registering a handler for TX done event.
+ *
+ * @note Multiple registration requests will overwrite any possible existing registration.
+ *
+ * @param[in] event_handler The function to be called by the transport layer upon TX done
+ * event.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_tx_done_register(hci_transport_tx_done_handler_t event_handler);
+
+/**@brief Function for opening the transport channel and initializing the transport layer.
+ *
+ * @warning Must not be called for a channel which has been allready opened.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_INTERNAL Operation failure. Internal error ocurred.
+ */
+uint32_t hci_transport_open(void);
+
+/**@brief Function for closing the transport channel.
+ *
+ * @note Can be called multiple times and also for not opened channel.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_transport_close(void);
+
+/**@brief Function for allocating tx packet memory.
+ *
+ * @param[out] pp_memory Pointer to the packet data.
+ *
+ * @retval NRF_SUCCESS Operation success. Memory was allocated.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No memory available.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_tx_alloc(uint8_t ** pp_memory);
+
+/**@brief Function for freeing tx packet memory.
+ *
+ * @note Memory management works in FIFO principle meaning that free order must match the alloc
+ * order.
+ *
+ * @retval NRF_SUCCESS Operation success. Memory was freed.
+ */
+uint32_t hci_transport_tx_free(void);
+
+/**@brief Function for writing a packet.
+ *
+ * @note Completion of this method does not guarantee that actual peripheral transmission would
+ * have completed.
+ *
+ * @note In case of 0 byte packet length write request, message will consist of only transport
+ * module specific headers.
+ *
+ * @retval NRF_SUCCESS Operation success. Packet was added to the transmission queue
+ * and an event will be send upon transmission completion.
+ * @retval NRF_ERROR_NO_MEM Operation failure. Transmission queue is full and packet was not
+ * added to the transmission queue. User should wait for
+ * a appropriate event prior issuing this operation again.
+ * @retval NRF_ERROR_DATA_SIZE Operation failure. Packet size exceeds limit.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ * @retval NRF_ERROR_INVALID_STATE Operation failure. Channel is not open.
+ */
+uint32_t hci_transport_pkt_write(const uint8_t * p_buffer, uint32_t length);
+
+/**@brief Function for extracting received packet.
+ *
+ * @note Extracted memory can't be reused by the underlying transport layer untill freed by call to
+ * hci_transport_rx_pkt_consume().
+ *
+ * @param[out] pp_buffer Pointer to the packet data.
+ * @param[out] p_length Length of packet data in bytes.
+ *
+ * @retval NRF_SUCCESS Operation success. Packet was extracted.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to extract.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_rx_pkt_extract(uint8_t ** pp_buffer, uint32_t * p_length);
+
+/**@brief Function for consuming extracted packet described by p_buffer.
+ *
+ * RX memory pointed to by p_buffer is freed and can be reused by the underlying transport layer.
+ *
+ * @param[in] p_buffer Pointer to the buffer that has been consumed.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to consume.
+ * @retval NRF_ERROR_INVALID_ADDR Operation failure. Not a valid pointer.
+ */
+uint32_t hci_transport_rx_pkt_consume(uint8_t * p_buffer);
+
+#endif // HCI_TRANSPORT_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_HRM1017/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/pstorage.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,381 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/**@file
+ *
+ * @defgroup persistent_storage Persistent Storage Interface
+ * @{
+ * @ingroup app_common
+ * @brief Abstracted flash interface.
+ *
+ * @details In order to ensure that the SDK and application be moved to alternate persistent storage
+ * options other than the default provided with NRF solution, an abstracted interface is provided
+ * by the module to ensure SDK modules and application can be ported to alternate option with ease.
+ */
+
+#ifndef PSTORAGE_H__
+#define PSTORAGE_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* #ifdef __cplusplus */
+
+#include "pstorage_platform.h"
+
+
+/**@defgroup ps_opcode Persistent Storage Access Operation Codes
+ * @{
+ * @brief Persistent Storage Access Operation Codes. These are used to report any error during
+ * a persistent storage access operation or any general error that may occur in the
+ * interface.
+ *
+ * @details Persistent Storage Access Operation Codes used in error notification callback
+ * registered with the interface to report any error during an persistent storage access
+ * operation or any general error that may occur in the interface.
+ */
+#define PSTORAGE_ERROR_OP_CODE 0x01 /**< General Error Code */
+#define PSTORAGE_STORE_OP_CODE 0x02 /**< Error when Store Operation was requested */
+#define PSTORAGE_LOAD_OP_CODE 0x03 /**< Error when Load Operation was requested */
+#define PSTORAGE_CLEAR_OP_CODE 0x04 /**< Error when Clear Operation was requested */
+#define PSTORAGE_UPDATE_OP_CODE 0x05 /**< Update an already touched storage block */
+
+/**@} */
+
+/**@defgroup pstorage_data_types Persistent Memory Interface Data Types
+ * @{
+ * @brief Data Types needed for interfacing with persistent memory.
+ *
+ * @details Data Types needed for interfacing with persistent memory.
+ */
+
+/**@brief Persistent Storage Error Reporting Callback
+ *
+ * @details Persistent Storage Error Reporting Callback that is used by the interface to report
+ * success or failure of a flash operation. Therefore, for any operations, application
+ * can know when the procedure was complete. For store operation, since no data copy
+ * is made, receiving a success or failure notification, indicated by the reason
+ * parameter of callback is an indication that the resident memory could now be reused
+ * or freed, as the case may be.
+ *
+ * @param[in] handle Identifies module and block for which callback is received.
+ * @param[in] op_code Identifies the operation for which the event is notified.
+ * @param[in] result Identifies the result of flash access operation.
+ * NRF_SUCCESS implies, operation succeeded.
+ * @param[in] p_data Identifies the application data pointer. In case of store operation, this
+ * points to the resident source of application memory that application can now
+ * free or reuse. In case of clear, this is NULL as no application pointer is
+ * needed for this operation.
+ * @param[in] data_len Length data application had provided for the operation.
+ *
+ */
+typedef void (*pstorage_ntf_cb_t)(pstorage_handle_t * p_handle,
+ uint8_t op_code,
+ uint32_t result,
+ uint8_t * p_data,
+ uint32_t data_len);
+
+
+typedef struct
+{
+ pstorage_ntf_cb_t cb; /**< Callback registered with the module to be notified of any error occurring in persistent memory management */
+ pstorage_size_t block_size; /**< Desired block size for persistent memory storage, for example, if a module has a table with 10 entries, each entry is size 64 bytes,
+ * it can request 10 blocks with block size 64 bytes. On the other hand, the module can also request one block of size 640 based on
+ * how it would like to access or alter memory in persistent memory.
+ * First option is preferred when single entries that need to be updated often when having no impact on the other entries.
+ * While second option is preferred when entries of table are not changed on individually but have common point of loading and storing
+ * data. */
+ pstorage_size_t block_count; /** Number of blocks requested by the module, minimum values is 1. */
+} pstorage_module_param_t;
+
+/**@} */
+
+/**@defgroup pstorage_routines Persistent Storage Access Routines
+ * @{
+ * @brief Functions/Interface SDK modules use to persistently store data.
+ *
+ * @details Interface for Application & SDK module to load/store information persistently.
+ * Note: that while implementation of each of the persistent storage access function
+ * depends on the system and can specific to system/solution, the signature of the
+ * interface routines should not be altered.
+ */
+
+/**@brief Module Initialization Routine.
+ *
+ * @details Initializes module. To be called once before any other APIs of the module are used.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ */
+uint32_t pstorage_init(void);
+
+
+/**@brief Register with persistent storage interface.
+ *
+ * @param[in] p_module_param Module registration param.
+ * @param[out] p_block_id Block identifier to identify persistent memory blocks in case
+ * registration succeeds. Application is expected to use the block ids
+ * for subsequent operations on requested persistent memory. Maximum
+ * registrations permitted is determined by configuration parameter
+ * PSTORAGE_MAX_APPLICATIONS.
+ * In case more than one memory blocks are requested, the identifier provided here is
+ * the base identifier for the first block and to identify subsequent block,
+ * application shall use \@ref pstorage_block_identifier_get with this base identifier
+ * and block number. Therefore if 10 blocks of size 64 are requested and application
+ * wishes to store memory in 6th block, it shall use
+ * \@ref pstorage_block_identifier_get with based id and provide a block number of 5.
+ * This way application is only expected to remember the base block identifier.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_NO_MEM in case no more registrations can be supported.
+ */
+uint32_t pstorage_register(pstorage_module_param_t * p_module_param,
+ pstorage_handle_t * p_block_id);
+
+
+/**
+ * @brief Function to get block id with reference to base block identifier provided at time of
+ * registration.
+ *
+ * @details Function to get block id with reference to base block identifier provided at time of
+ * registration.
+ * In case more than one memory blocks were requested when registering, the identifier
+ * provided here is the base identifier for the first block and to identify subsequent
+ * block, application shall use this routine to get block identifier providing input as
+ * base identifier and block number. Therefore if 10 blocks of size 64 are requested and
+ * application wishes to store memory in 6th block, it shall use
+ * \@ref pstorage_block_identifier_get with based id and provide a block number of 5.
+ * This way application is only expected to remember the base block identifier.
+ *
+ * @param[in] p_base_id Base block id received at the time of registration.
+ * @param[in] block_num Block Number, with first block numbered zero.
+ * @param[out] p_block_id Block identifier for the block number requested in case the API succeeds.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ */
+uint32_t pstorage_block_identifier_get(pstorage_handle_t * p_base_id,
+ pstorage_size_t block_num,
+ pstorage_handle_t * p_block_id);
+
+
+/**@brief Routine to persistently store data of length 'size' contained in 'p_src' address
+ * in storage module at 'p_dest' address; Equivalent to Storage Write.
+ *
+ * @param[in] p_dest Destination address where data is to be stored persistently.
+ * @param[in] p_src Source address containing data to be stored. API assumes this to be resident
+ * memory and no intermediate copy of data is made by the API.
+ * @param[in] size Size of data to be stored expressed in bytes. Should be word aligned.
+ * @param[in] offset Offset in bytes to be applied when writing to the block.
+ * For example, if within a block of 100 bytes, application wishes to
+ * write 20 bytes at offset of 12, then this field should be set to 12.
+ * Should be word aligned.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_src' is not aligned.
+ * @retval NRF_ERROR_NO_MEM in case request cannot be processed.
+ *
+ * @warning No copy of the data is made, and hence memory provided for data source to be written
+ * to flash cannot be freed or reused by the application until this procedure
+ * is complete. End of this procedure is notified to the application using the
+ * notification callback registered by the application.
+ */
+uint32_t pstorage_store(pstorage_handle_t * p_dest,
+ uint8_t * p_src,
+ pstorage_size_t size,
+ pstorage_size_t offset);
+
+/**@brief Routine to update persistently stored data of length 'size' contained in 'p_src' address
+ * in storage module at 'p_dest' address.
+ *
+ * @param[in] p_dest Destination address where data is to be updated.
+ * @param[in] p_src Source address containing data to be stored. API assumes this to be resident
+ * memory and no intermediate copy of data is made by the API.
+ * @param[in] size Size of data to be stored expressed in bytes. Should be word aligned.
+ * @param[in] offset Offset in bytes to be applied when writing to the block.
+ * For example, if within a block of 100 bytes, application wishes to
+ * write 20 bytes at offset of 12, then this field should be set to 12.
+ * Should be word aligned.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_src' is not aligned.
+ * @retval NRF_ERROR_NO_MEM in case request cannot be processed.
+ *
+ * @warning No copy of the data is made, and hence memory provided for data source to be written
+ * to flash cannot be freed or reused by the application until this procedure
+ * is complete. End of this procedure is notified to the application using the
+ * notification callback registered by the application.
+ */
+uint32_t pstorage_update(pstorage_handle_t * p_dest,
+ uint8_t * p_src,
+ pstorage_size_t size,
+ pstorage_size_t offset);
+
+/**@brief Routine to load persistently stored data of length 'size' from 'p_src' address
+ * to 'p_dest' address; Equivalent to Storage Read.
+ *
+ * @param[in] p_dest Destination address where persistently stored data is to be loaded.
+ * @param[in] p_src Source from where data is to be loaded from persistent memory.
+ * @param[in] size Size of data to be loaded from persistent memory expressed in bytes.
+ * Should be word aligned.
+ * @param[in] offset Offset in bytes to be applied when loading from the block.
+ * For example, if within a block of 100 bytes, application wishes to
+ * load 20 bytes from offset of 12, then this field should be set to 12.
+ * Should be word aligned.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_dst' is not aligned.
+ * @retval NRF_ERROR_NO_MEM in case request cannot be processed.
+ */
+uint32_t pstorage_load(uint8_t * p_dest,
+ pstorage_handle_t * p_src,
+ pstorage_size_t size,
+ pstorage_size_t offset);
+
+/**@brief Routine to clear data in persistent memory.
+ *
+ * @param[in] p_base_id Base block identifier in persistent memory that needs to cleared;
+ * Equivalent to an Erase Operation.
+ *
+ * @param[in] size Size of data to be cleared from persistent memory expressed in bytes.
+ * This parameter is to provision for clearing of certain blocks
+ * of memory, or all memory blocks in a registered module. If the total size
+ * of the application module is used (blocks * block size) in combination with
+ * the identifier for the first block in the module, all blocks in the
+ * module will be erased.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_dst' is not aligned.
+ * @retval NRF_ERROR_NO_MEM in case request cannot be processed.
+ *
+ * @note Clear operations may take time. This API however, does not block until the clear
+ * procedure is complete. Application is notified of procedure completion using
+ * notification callback registered by the application. 'result' parameter of the
+ * callback suggests if the procedure was successful or not.
+ */
+uint32_t pstorage_clear(pstorage_handle_t * p_base_id, pstorage_size_t size);
+
+/**
+ * @brief API to get status of number of pending operations with the module.
+ *
+ * @param[out] p_count Number of storage operations pending with the module, if 0,
+ * there are no outstanding requests.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ */
+uint32_t pstorage_access_status_get(uint32_t * p_count);
+
+#ifdef PSTORAGE_RAW_MODE_ENABLE
+
+/**@brief Function for registering with persistent storage interface.
+ *
+ * @param[in] p_module_param Module registration param.
+ * @param[out] p_block_id Block identifier to identify persistent memory blocks in case
+ * registration succeeds. Application is expected to use the block ids
+ * for subsequent operations on requested persistent memory.
+ * In case more than one memory blocks are requested, the identifier provided here is
+ * the base identifier for the first block and to identify subsequent block,
+ * application shall use \@ref pstorage_block_identifier_get with this base identifier
+ * and block number. Therefore if 10 blocks of size 64 are requested and application
+ * wishes to store memory in 6th block, it shall use
+ * \@ref pstorage_block_identifier_get with based id and provide a block number of 5.
+ * This way application is only expected to remember the base block identifier.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_NO_MEM in case no more registrations can be supported.
+ */
+uint32_t pstorage_raw_register(pstorage_module_param_t * p_module_param,
+ pstorage_handle_t * p_block_id);
+
+/**@brief Raw mode function for persistently storing data of length 'size' contained in 'p_src'
+ * address in storage module at 'p_dest' address; Equivalent to Storage Write.
+ *
+ * @param[in] p_dest Destination address where data is to be stored persistently.
+ * @param[in] p_src Source address containing data to be stored. API assumes this to be resident
+ * memory and no intermediate copy of data is made by the API.
+ * @param[in] size Size of data to be stored expressed in bytes. Should be word aligned.
+ * @param[in] offset Offset in bytes to be applied when writing to the block.
+ * For example, if within a block of 100 bytes, application wishes to
+ * write 20 bytes at offset of 12, then this field should be set to 12.
+ * Should be word aligned.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_src' is not aligned.
+ * @retval NRF_ERROR_NO_MEM in case request cannot be processed.
+ *
+ * @warning No copy of the data is made, and hence memory provided for data source to be written
+ * to flash cannot be freed or reused by the application until this procedure
+ * is complete. End of this procedure is notified to the application using the
+ * notification callback registered by the application.
+ */
+uint32_t pstorage_raw_store(pstorage_handle_t * p_dest,
+ uint8_t * p_src,
+ pstorage_size_t size,
+ pstorage_size_t offset);
+
+/**@brief Function for clearing data in persistent memory in raw mode.
+ *
+ * @param[in] p_dest Base block identifier in persistent memory that needs to cleared;
+ * Equivalent to an Erase Operation.
+ * @param[in] size Size of data to be cleared from persistent memory expressed in bytes.
+ * This is currently unused. And a clear would mean clearing all blocks,
+ * however, this parameter is to provision for clearing of certain blocks
+ * of memory only and not all if need be.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_NO_MEM in case request cannot be processed.
+ *
+ * @note Clear operations may take time. This API however, does not block until the clear
+ * procedure is complete. Application is notified of procedure completion using
+ * notification callback registered by the application. 'result' parameter of the
+ * callback suggests if the procedure was successful or not.
+ */
+uint32_t pstorage_raw_clear(pstorage_handle_t * p_dest, pstorage_size_t size);
+
+#endif // PSTORAGE_RAW_MODE_ENABLE
+
+#ifdef __cplusplus
+}
+#endif /* #ifdef __cplusplus */
+
+
+/**@} */
+/**@} */
+
+#endif // PSTORAGE_H__
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_HRM1017/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/nrf_delay.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,74 @@
+#ifndef _NRF_DELAY_H
+#define _NRF_DELAY_H
+
+// #include "nrf.h"
+
+/*lint --e{438, 522} "Variable not used" "Function lacks side-effects" */
+#if defined ( __CC_ARM )
+static __ASM void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
+{
+loop
+ SUBS R0, R0, #1
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ BNE loop
+ BX LR
+}
+#elif defined ( __ICCARM__ )
+static void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
+{
+__ASM (
+"loop:\n\t"
+ " SUBS R0, R0, #1\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " BNE loop\n\t");
+}
+#elif defined ( __GNUC__ )
+static void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
+{
+ do
+ {
+ __ASM volatile (
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ );
+ } while (--number_of_us);
+}
+#endif
+
+void nrf_delay_ms(uint32_t volatile number_of_ms);
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_HRM1017/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/sd_common/app_util_platform.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,110 @@
+/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/**@file
+ *
+ * @defgroup app_util_platform Utility Functions and Definitions (Platform)
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Various types and definitions available to all applications when using SoftDevice.
+ */
+
+#ifndef APP_UTIL_PLATFORM_H__
+#define APP_UTIL_PLATFORM_H__
+
+#include <stdint.h>
+#include "compiler_abstraction.h"
+#include "nrf51.h"
+#include "app_error.h"
+
+/**@brief The interrupt priorities available to the application while the SoftDevice is active. */
+typedef enum
+{
+ APP_IRQ_PRIORITY_HIGH = 1,
+ APP_IRQ_PRIORITY_LOW = 3
+} app_irq_priority_t;
+
+#define NRF_APP_PRIORITY_THREAD 4 /**< "Interrupt level" when running in Thread Mode. */
+
+/**@cond NO_DOXYGEN */
+#define EXTERNAL_INT_VECTOR_OFFSET 16
+/**@endcond */
+
+#define PACKED(TYPE) __packed TYPE
+
+/**@brief Macro for entering a critical region.
+ *
+ * @note Due to implementation details, there must exist one and only one call to
+ * CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located
+ * in the same scope.
+ */
+#define CRITICAL_REGION_ENTER() \
+ { \
+ uint8_t IS_NESTED_CRITICAL_REGION = 0; \
+ uint32_t CURRENT_INT_PRI = current_int_priority_get(); \
+ if (CURRENT_INT_PRI != APP_IRQ_PRIORITY_HIGH) \
+ { \
+ uint32_t ERR_CODE = sd_nvic_critical_region_enter(&IS_NESTED_CRITICAL_REGION); \
+ if (ERR_CODE == NRF_ERROR_SOFTDEVICE_NOT_ENABLED) \
+ { \
+ __disable_irq(); \
+ } \
+ else \
+ { \
+ APP_ERROR_CHECK(ERR_CODE); \
+ } \
+ }
+
+/**@brief Macro for leaving a critical region.
+ *
+ * @note Due to implementation details, there must exist one and only one call to
+ * CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located
+ * in the same scope.
+ */
+#define CRITICAL_REGION_EXIT() \
+ if (CURRENT_INT_PRI != APP_IRQ_PRIORITY_HIGH) \
+ { \
+ uint32_t ERR_CODE; \
+ __enable_irq(); \
+ ERR_CODE = sd_nvic_critical_region_exit(IS_NESTED_CRITICAL_REGION); \
+ if (ERR_CODE != NRF_ERROR_SOFTDEVICE_NOT_ENABLED) \
+ { \
+ APP_ERROR_CHECK(ERR_CODE); \
+ } \
+ } \
+ }
+
+/**@brief Function for finding the current interrupt level.
+ *
+ * @return Current interrupt level.
+ * @retval APP_IRQ_PRIORITY_HIGH We are running in Application High interrupt level.
+ * @retval APP_IRQ_PRIORITY_LOW We are running in Application Low interrupt level.
+ * @retval APP_IRQ_PRIORITY_THREAD We are running in Thread Mode.
+ */
+static __INLINE uint8_t current_int_priority_get(void)
+{
+ uint32_t isr_vector_num = (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk);
+ if (isr_vector_num > 0)
+ {
+ int32_t irq_type = ((int32_t)isr_vector_num - EXTERNAL_INT_VECTOR_OFFSET);
+ return (NVIC_GetPriority((IRQn_Type)irq_type) & 0xFF);
+ }
+ else
+ {
+ return NRF_APP_PRIORITY_THREAD;
+ }
+}
+
+#endif // APP_UTIL_PLATFORM_H__
+
+/** @} */
--- a/TARGET_HRM1017/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_0_0/s110_nrf51822_7.0.0_API/include/nrf_svc.h Fri Aug 15 15:28:31 2014 +0100
+++ b/TARGET_HRM1017/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_0_0/s110_nrf51822_7.0.0_API/include/nrf_svc.h Fri Sep 12 16:41:52 2014 +0100
@@ -16,7 +16,7 @@
{ \
__asm( \
"svc %0\n" \
- "bx r14" : : "I" (number) : "r0" \
+ "bx r14" : : "I" ((uint32_t)number) : "r0" \
); \
}
#elif defined (__ICCARM__)
--- a/TARGET_HRM1017/TARGET_NORDIC/TARGET_MCU_NRF51822/objects.h Fri Aug 15 15:28:31 2014 +0100
+++ b/TARGET_HRM1017/TARGET_NORDIC/TARGET_MCU_NRF51822/objects.h Fri Sep 12 16:41:52 2014 +0100
@@ -53,6 +53,7 @@
PinName sda;
PinName scl;
int freq;
+ uint8_t address_set;
};
struct analogin_s {
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--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/PeripheralPins.h Fri Aug 15 15:28:31 2014 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,49 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - -/************RTC***************/ -extern const PinMap PinMap_RTC[]; - -/************ADC***************/ -extern const PinMap PinMap_ADC[]; - -/************DAC***************/ -extern const PinMap PinMap_DAC[]; - -/************I2C***************/ -extern const PinMap PinMap_I2C_SDA[]; -extern const PinMap PinMap_I2C_SCL[]; - -/************UART***************/ -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; - -/************SPI***************/ -extern const PinMap PinMap_SPI_SCLK[]; -extern const PinMap PinMap_SPI_MOSI[]; -extern const PinMap PinMap_SPI_MISO[]; -extern const PinMap PinMap_SPI_SSEL[]; - -/************PWM***************/ -extern const PinMap PinMap_PWM[]; - -#endif
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/PortNames.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,35 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/TARGET_FRDM/PeripheralNames.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,131 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- OSC32KCLK = 0,
-} RTCName;
-
-typedef enum {
- UART_0 = 0,
- UART_1 = 1,
- UART_2 = 2,
- UART_3 = 3,
- UART_4 = 4,
-} UARTName;
-
-#define STDIO_UART_TX USBTX
-#define STDIO_UART_RX USBRX
-#define STDIO_UART UART_0
-
-typedef enum {
- I2C_0 = 0,
- I2C_1 = 1,
- I2C_2 = 2,
-} I2CName;
-
-#define TPM_SHIFT 8
-typedef enum {
- PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0
- PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1
- PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2
- PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3
- PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4
- PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5
- PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6
- PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7
- PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0
- PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1
- PWM_11 = (1 << TPM_SHIFT) | (2), // FTM1 CH2
- PWM_12 = (1 << TPM_SHIFT) | (3), // FTM1 CH3
- PWM_13 = (1 << TPM_SHIFT) | (4), // FTM1 CH4
- PWM_14 = (1 << TPM_SHIFT) | (5), // FTM1 CH5
- PWM_15 = (1 << TPM_SHIFT) | (6), // FTM1 CH6
- PWM_16 = (1 << TPM_SHIFT) | (7), // FTM1 CH7
- PWM_17 = (2 << TPM_SHIFT) | (0), // FTM2 CH0
- PWM_18 = (2 << TPM_SHIFT) | (1), // FTM2 CH1
- PWM_19 = (2 << TPM_SHIFT) | (2), // FTM2 CH2
- PWM_20 = (2 << TPM_SHIFT) | (3), // FTM2 CH3
- PWM_21 = (2 << TPM_SHIFT) | (4), // FTM2 CH4
- PWM_22 = (2 << TPM_SHIFT) | (5), // FTM2 CH5
- PWM_23 = (2 << TPM_SHIFT) | (6), // FTM2 CH6
- PWM_24 = (2 << TPM_SHIFT) | (7), // FTM2 CH7
- // could be 4 or could be 3... not sure what register
- // this is for... too much abstraction
- PWM_25 = (3 << TPM_SHIFT) | (0), // FTM3 CH0
- PWM_26 = (3 << TPM_SHIFT) | (1), // FTM3 CH1
- PWM_27 = (3 << TPM_SHIFT) | (2), // FTM3 CH2
- PWM_28 = (3 << TPM_SHIFT) | (3), // FTM3 CH3
- PWM_29 = (3 << TPM_SHIFT) | (4), // FTM3 CH4
- PWM_30 = (3 << TPM_SHIFT) | (5), // FTM3 CH5
- PWM_31 = (3 << TPM_SHIFT) | (6), // FTM3 CH6
- PWM_32 = (3 << TPM_SHIFT) | (7), // FTM3 CH7
-} PWMName;
-
-#define ADC_INSTANCE_SHIFT 8
-#define ADC_B_CHANNEL_SHIFT 5
-typedef enum {
- ADC0_SE4b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4,
- ADC0_SE5b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5,
- ADC0_SE6b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6,
- ADC0_SE7b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7,
- ADC0_SE8 = (0 << ADC_INSTANCE_SHIFT) | 8,
- ADC0_SE9 = (0 << ADC_INSTANCE_SHIFT) | 9,
- ADC0_SE12 = (0 << ADC_INSTANCE_SHIFT) | 12,
- ADC0_SE13 = (0 << ADC_INSTANCE_SHIFT) | 13,
- ADC0_SE14 = (0 << ADC_INSTANCE_SHIFT) | 14,
- ADC0_SE15 = (0 << ADC_INSTANCE_SHIFT) | 15,
- ADC0_SE16 = (0 << ADC_INSTANCE_SHIFT) | 16,
- ADC0_SE17 = (0 << ADC_INSTANCE_SHIFT) | 17,
- ADC0_SE18 = (0 << ADC_INSTANCE_SHIFT) | 18,
- ADC1_SE4b = (1 << ADC_INSTANCE_SHIFT) | 4,
- ADC1_SE5b = (1 << ADC_INSTANCE_SHIFT) | 5,
- ADC1_SE6b = (1 << ADC_INSTANCE_SHIFT) | 6,
- ADC1_SE7b = (1 << ADC_INSTANCE_SHIFT) | 7,
- ADC1_SE8 = (1 << ADC_INSTANCE_SHIFT) | 8,
- ADC1_SE9 = (1 << ADC_INSTANCE_SHIFT) | 9,
- ADC1_SE12 = (1 << ADC_INSTANCE_SHIFT) | 12,
- ADC1_SE13 = (1 << ADC_INSTANCE_SHIFT) | 13,
- ADC1_SE14 = (1 << ADC_INSTANCE_SHIFT) | 14,
- ADC1_SE15 = (1 << ADC_INSTANCE_SHIFT) | 15,
- ADC1_SE16 = (1 << ADC_INSTANCE_SHIFT) | 16,
- ADC1_SE17 = (1 << ADC_INSTANCE_SHIFT) | 17,
- ADC1_SE18 = (1 << ADC_INSTANCE_SHIFT) | 18,
-} ADCName;
-
-typedef enum {
- DAC_0 = 0
-} DACName;
-
-
-typedef enum {
- SPI_0 = 0,
- SPI_1 = 1,
- SPI_2 = 2,
-} SPIName;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/TARGET_FRDM/PinNames.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,258 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
-#define GPIO_PORT_SHIFT 12
-
-typedef enum {
- PTA0 = (0 << GPIO_PORT_SHIFT | 0 ),
- PTA1 = (0 << GPIO_PORT_SHIFT | 1 ),
- PTA2 = (0 << GPIO_PORT_SHIFT | 2 ),
- PTA3 = (0 << GPIO_PORT_SHIFT | 3 ),
- PTA4 = (0 << GPIO_PORT_SHIFT | 4 ),
- PTA5 = (0 << GPIO_PORT_SHIFT | 5 ),
- PTA6 = (0 << GPIO_PORT_SHIFT | 6 ),
- PTA7 = (0 << GPIO_PORT_SHIFT | 7 ),
- PTA8 = (0 << GPIO_PORT_SHIFT | 8 ),
- PTA9 = (0 << GPIO_PORT_SHIFT | 9 ),
- PTA10 = (0 << GPIO_PORT_SHIFT | 10),
- PTA11 = (0 << GPIO_PORT_SHIFT | 11),
- PTA12 = (0 << GPIO_PORT_SHIFT | 12),
- PTA13 = (0 << GPIO_PORT_SHIFT | 13),
- PTA14 = (0 << GPIO_PORT_SHIFT | 14),
- PTA15 = (0 << GPIO_PORT_SHIFT | 15),
- PTA16 = (0 << GPIO_PORT_SHIFT | 16),
- PTA17 = (0 << GPIO_PORT_SHIFT | 17),
- PTA18 = (0 << GPIO_PORT_SHIFT | 18),
- PTA19 = (0 << GPIO_PORT_SHIFT | 19),
- PTA20 = (0 << GPIO_PORT_SHIFT | 20),
- PTA21 = (0 << GPIO_PORT_SHIFT | 21),
- PTA22 = (0 << GPIO_PORT_SHIFT | 22),
- PTA23 = (0 << GPIO_PORT_SHIFT | 23),
- PTA24 = (0 << GPIO_PORT_SHIFT | 24),
- PTA25 = (0 << GPIO_PORT_SHIFT | 25),
- PTA26 = (0 << GPIO_PORT_SHIFT | 26),
- PTA27 = (0 << GPIO_PORT_SHIFT | 27),
- PTA28 = (0 << GPIO_PORT_SHIFT | 28),
- PTA29 = (0 << GPIO_PORT_SHIFT | 29),
- PTA30 = (0 << GPIO_PORT_SHIFT | 30),
- PTA31 = (0 << GPIO_PORT_SHIFT | 31),
- PTB0 = (1 << GPIO_PORT_SHIFT | 0 ),
- PTB1 = (1 << GPIO_PORT_SHIFT | 1 ),
- PTB2 = (1 << GPIO_PORT_SHIFT | 2 ),
- PTB3 = (1 << GPIO_PORT_SHIFT | 3 ),
- PTB4 = (1 << GPIO_PORT_SHIFT | 4 ),
- PTB5 = (1 << GPIO_PORT_SHIFT | 5 ),
- PTB6 = (1 << GPIO_PORT_SHIFT | 6 ),
- PTB7 = (1 << GPIO_PORT_SHIFT | 7 ),
- PTB8 = (1 << GPIO_PORT_SHIFT | 8 ),
- PTB9 = (1 << GPIO_PORT_SHIFT | 9 ),
- PTB10 = (1 << GPIO_PORT_SHIFT | 10),
- PTB11 = (1 << GPIO_PORT_SHIFT | 11),
- PTB12 = (1 << GPIO_PORT_SHIFT | 12),
- PTB13 = (1 << GPIO_PORT_SHIFT | 13),
- PTB14 = (1 << GPIO_PORT_SHIFT | 14),
- PTB15 = (1 << GPIO_PORT_SHIFT | 15),
- PTB16 = (1 << GPIO_PORT_SHIFT | 16),
- PTB17 = (1 << GPIO_PORT_SHIFT | 17),
- PTB18 = (1 << GPIO_PORT_SHIFT | 18),
- PTB19 = (1 << GPIO_PORT_SHIFT | 19),
- PTB20 = (1 << GPIO_PORT_SHIFT | 20),
- PTB21 = (1 << GPIO_PORT_SHIFT | 21),
- PTB22 = (1 << GPIO_PORT_SHIFT | 22),
- PTB23 = (1 << GPIO_PORT_SHIFT | 23),
- PTB24 = (1 << GPIO_PORT_SHIFT | 24),
- PTB25 = (1 << GPIO_PORT_SHIFT | 25),
- PTB26 = (1 << GPIO_PORT_SHIFT | 26),
- PTB27 = (1 << GPIO_PORT_SHIFT | 27),
- PTB28 = (1 << GPIO_PORT_SHIFT | 28),
- PTB29 = (1 << GPIO_PORT_SHIFT | 29),
- PTB30 = (1 << GPIO_PORT_SHIFT | 30),
- PTB31 = (1 << GPIO_PORT_SHIFT | 31),
- PTC0 = (2 << GPIO_PORT_SHIFT | 0 ),
- PTC1 = (2 << GPIO_PORT_SHIFT | 1 ),
- PTC2 = (2 << GPIO_PORT_SHIFT | 2 ),
- PTC3 = (2 << GPIO_PORT_SHIFT | 3 ),
- PTC4 = (2 << GPIO_PORT_SHIFT | 4 ),
- PTC5 = (2 << GPIO_PORT_SHIFT | 5 ),
- PTC6 = (2 << GPIO_PORT_SHIFT | 6 ),
- PTC7 = (2 << GPIO_PORT_SHIFT | 7 ),
- PTC8 = (2 << GPIO_PORT_SHIFT | 8 ),
- PTC9 = (2 << GPIO_PORT_SHIFT | 9 ),
- PTC10 = (2 << GPIO_PORT_SHIFT | 10),
- PTC11 = (2 << GPIO_PORT_SHIFT | 11),
- PTC12 = (2 << GPIO_PORT_SHIFT | 12),
- PTC13 = (2 << GPIO_PORT_SHIFT | 13),
- PTC14 = (2 << GPIO_PORT_SHIFT | 14),
- PTC15 = (2 << GPIO_PORT_SHIFT | 15),
- PTC16 = (2 << GPIO_PORT_SHIFT | 16),
- PTC17 = (2 << GPIO_PORT_SHIFT | 17),
- PTC18 = (2 << GPIO_PORT_SHIFT | 18),
- PTC19 = (2 << GPIO_PORT_SHIFT | 19),
- PTC20 = (2 << GPIO_PORT_SHIFT | 20),
- PTC21 = (2 << GPIO_PORT_SHIFT | 21),
- PTC22 = (2 << GPIO_PORT_SHIFT | 22),
- PTC23 = (2 << GPIO_PORT_SHIFT | 23),
- PTC24 = (2 << GPIO_PORT_SHIFT | 24),
- PTC25 = (2 << GPIO_PORT_SHIFT | 25),
- PTC26 = (2 << GPIO_PORT_SHIFT | 26),
- PTC27 = (2 << GPIO_PORT_SHIFT | 27),
- PTC28 = (2 << GPIO_PORT_SHIFT | 28),
- PTC29 = (2 << GPIO_PORT_SHIFT | 29),
- PTC30 = (2 << GPIO_PORT_SHIFT | 30),
- PTC31 = (2 << GPIO_PORT_SHIFT | 31),
- PTD0 = (3 << GPIO_PORT_SHIFT | 0 ),
- PTD1 = (3 << GPIO_PORT_SHIFT | 1 ),
- PTD2 = (3 << GPIO_PORT_SHIFT | 2 ),
- PTD3 = (3 << GPIO_PORT_SHIFT | 3 ),
- PTD4 = (3 << GPIO_PORT_SHIFT | 4 ),
- PTD5 = (3 << GPIO_PORT_SHIFT | 5 ),
- PTD6 = (3 << GPIO_PORT_SHIFT | 6 ),
- PTD7 = (3 << GPIO_PORT_SHIFT | 7 ),
- PTD8 = (3 << GPIO_PORT_SHIFT | 8 ),
- PTD9 = (3 << GPIO_PORT_SHIFT | 9 ),
- PTD10 = (3 << GPIO_PORT_SHIFT | 10),
- PTD11 = (3 << GPIO_PORT_SHIFT | 11),
- PTD12 = (3 << GPIO_PORT_SHIFT | 12),
- PTD13 = (3 << GPIO_PORT_SHIFT | 13),
- PTD14 = (3 << GPIO_PORT_SHIFT | 14),
- PTD15 = (3 << GPIO_PORT_SHIFT | 15),
- PTD16 = (3 << GPIO_PORT_SHIFT | 16),
- PTD17 = (3 << GPIO_PORT_SHIFT | 17),
- PTD18 = (3 << GPIO_PORT_SHIFT | 18),
- PTD19 = (3 << GPIO_PORT_SHIFT | 19),
- PTD20 = (3 << GPIO_PORT_SHIFT | 20),
- PTD21 = (3 << GPIO_PORT_SHIFT | 21),
- PTD22 = (3 << GPIO_PORT_SHIFT | 22),
- PTD23 = (3 << GPIO_PORT_SHIFT | 23),
- PTD24 = (3 << GPIO_PORT_SHIFT | 24),
- PTD25 = (3 << GPIO_PORT_SHIFT | 25),
- PTD26 = (3 << GPIO_PORT_SHIFT | 26),
- PTD27 = (3 << GPIO_PORT_SHIFT | 27),
- PTD28 = (3 << GPIO_PORT_SHIFT | 28),
- PTD29 = (3 << GPIO_PORT_SHIFT | 29),
- PTD30 = (3 << GPIO_PORT_SHIFT | 30),
- PTD31 = (3 << GPIO_PORT_SHIFT | 31),
- PTE0 = (4 << GPIO_PORT_SHIFT | 0 ),
- PTE1 = (4 << GPIO_PORT_SHIFT | 1 ),
- PTE2 = (4 << GPIO_PORT_SHIFT | 2 ),
- PTE3 = (4 << GPIO_PORT_SHIFT | 3 ),
- PTE4 = (4 << GPIO_PORT_SHIFT | 4 ),
- PTE5 = (4 << GPIO_PORT_SHIFT | 5 ),
- PTE6 = (4 << GPIO_PORT_SHIFT | 6 ),
- PTE7 = (4 << GPIO_PORT_SHIFT | 7 ),
- PTE8 = (4 << GPIO_PORT_SHIFT | 8 ),
- PTE9 = (4 << GPIO_PORT_SHIFT | 9 ),
- PTE10 = (4 << GPIO_PORT_SHIFT | 10),
- PTE11 = (4 << GPIO_PORT_SHIFT | 11),
- PTE12 = (4 << GPIO_PORT_SHIFT | 12),
- PTE13 = (4 << GPIO_PORT_SHIFT | 13),
- PTE14 = (4 << GPIO_PORT_SHIFT | 14),
- PTE15 = (4 << GPIO_PORT_SHIFT | 15),
- PTE16 = (4 << GPIO_PORT_SHIFT | 16),
- PTE17 = (4 << GPIO_PORT_SHIFT | 17),
- PTE18 = (4 << GPIO_PORT_SHIFT | 18),
- PTE19 = (4 << GPIO_PORT_SHIFT | 19),
- PTE20 = (4 << GPIO_PORT_SHIFT | 20),
- PTE21 = (4 << GPIO_PORT_SHIFT | 21),
- PTE22 = (4 << GPIO_PORT_SHIFT | 22),
- PTE23 = (4 << GPIO_PORT_SHIFT | 23),
- PTE24 = (4 << GPIO_PORT_SHIFT | 24),
- PTE25 = (4 << GPIO_PORT_SHIFT | 25),
- PTE26 = (4 << GPIO_PORT_SHIFT | 26),
- PTE27 = (4 << GPIO_PORT_SHIFT | 27),
- PTE28 = (4 << GPIO_PORT_SHIFT | 28),
- PTE29 = (4 << GPIO_PORT_SHIFT | 29),
- PTE30 = (4 << GPIO_PORT_SHIFT | 30),
- PTE31 = (4 << GPIO_PORT_SHIFT | 31),
-
- LED_RED = PTB22,
- LED_GREEN = PTE26,
- LED_BLUE = PTB21,
-
- // mbed original LED naming
- LED1 = LED_RED,
- LED2 = LED_GREEN,
- LED3 = LED_BLUE,
- LED4 = LED_RED,
-
- //Push buttons
- SW2 = PTC6,
- SW3 = PTA4,
-
- // USB Pins
- USBTX = PTB17,
- USBRX = PTB16,
-
- // Arduino Headers
- D0 = PTC16,
- D1 = PTC17,
- D2 = PTB9,
- D3 = PTA1,
- D4 = PTB23,
- D5 = PTA2,
- D6 = PTC2,
- D7 = PTC3,
- D8 = PTA0,
- D9 = PTC4,
- D10 = PTD0,
- D11 = PTD2,
- D12 = PTD3,
- D13 = PTD1,
- D14 = PTE25,
- D15 = PTE24,
-
- I2C_SCL = D15,
- I2C_SDA = D14,
-
- A0 = PTB2,
- A1 = PTB3,
- A2 = PTB10,
- A3 = PTB11,
- A4 = PTC10,
- A5 = PTC11,
-
- DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */
-
- // Not connected
- NC = (int)0xFFFFFFFF
-} PinName;
-
-
-typedef enum {
- PullNone = 0,
- PullDown = 1,
- PullUp = 2,
- PullDefault = PullUp
-} PinMode;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/TARGET_FRDM/device.h Fri Aug 15 15:28:31 2014 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,58 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_PORTIN 1 -#define DEVICE_PORTOUT 1 -#define DEVICE_PORTINOUT 1 - -#define DEVICE_INTERRUPTIN 1 - -#define DEVICE_ANALOGIN 1 -#define DEVICE_ANALOGOUT 1 - -#define DEVICE_SERIAL 1 - -#define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 1 - -#define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 1 - -#define DEVICE_CAN 0 - -#define DEVICE_RTC 1 - -#define DEVICE_ETHERNET 0 - -#define DEVICE_PWMOUT 1 - -#define DEVICE_SEMIHOST 0 -#define DEVICE_LOCALFILESYSTEM 0 -#define DEVICE_ID_LENGTH 24 - -#define DEVICE_SLEEP 1 - -#define DEVICE_DEBUG_AWARENESS 0 - -#define DEVICE_STDIO_MESSAGES 1 - -#define DEVICE_ERROR_RED 1 - -#include "objects.h" - -#endif
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,13704 +0,0 @@
-/*
-** ###################################################################
-** Processor: MK64FN1M0VMD12
-** Compilers: ARM Compiler
-** Freescale C/C++ for Embedded ARM
-** GNU C Compiler
-** GNU C Compiler - CodeSourcery Sourcery G++
-** IAR ANSI C/C++ Compiler for ARM
-**
-** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
-** Version: rev. 2.3, 2014-01-24
-**
-** Abstract:
-** CMSIS Peripheral Access Layer for MK64F12
-**
-** Copyright: 1997 - 2014 Freescale, Inc. All Rights Reserved.
-**
-** http: www.freescale.com
-** mail: support@freescale.com
-**
-** Revisions:
-** - rev. 1.0 (2013-08-12)
-** Initial version.
-** - rev. 2.0 (2013-10-29)
-** Register accessor macros added to the memory map.
-** Symbols for Processor Expert memory map compatibility added to the memory map.
-** Startup file for gcc has been updated according to CMSIS 3.2.
-** System initialization updated.
-** MCG - registers updated.
-** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
-** - rev. 2.1 (2013-10-29)
-** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
-** - rev. 2.2 (2013-12-09)
-** DMA - EARS register removed.
-** AIPS0, AIPS1 - MPRA register updated.
-** - rev. 2.3 (2014-01-24)
-** Update according to reference manual rev. 2
-** ENET, MCG, MCM, SIM, USB - registers updated
-**
-** ###################################################################
-*/
-
-/*!
- * @file MK64F12.h
- * @version 2.3
- * @date 2014-01-24
- * @brief CMSIS Peripheral Access Layer for MK64F12
- *
- * CMSIS Peripheral Access Layer for MK64F12
- */
-
-#if !defined(MK64F12_H_)
-#define MK64F12_H_ /**< Symbol preventing repeated inclusion */
-
-
-/* ----------------------------------------------------------------------------
- -- MCU activation
- ---------------------------------------------------------------------------- */
-
-/* Prevention from multiple including the same memory map */
-#if !defined(MCU_MK64F12) /* Check if memory map has not been already included */
-#define MCU_MK64F12
-
-/* Check if another memory map has not been also included */
-#if (defined(MCU_ACTIVE))
- #error MK64F12 memory map: There is already included another memory map. Only one memory map can be included.
-#endif /* (defined(MCU_ACTIVE)) */
-#define MCU_ACTIVE
-
-#include <stdint.h>
-
-/** Memory map major version (memory maps with equal major version number are
- * compatible) */
-#define MCU_MEM_MAP_VERSION 0x0200u
-/** Memory map minor version */
-#define MCU_MEM_MAP_VERSION_MINOR 0x0003u
-
-/**
- * @brief Macro to calculate address of an aliased word in the peripheral
- * bitband area for a peripheral register and bit (bit band region 0x40000000 to
- * 0x400FFFFF).
- * @param Reg Register to access.
- * @param Bit Bit number to access.
- * @return Address of the aliased word in the peripheral bitband area.
- */
-#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
-/**
- * @brief Macro to access a single bit of a peripheral register (bit band region
- * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
- * be used for peripherals with 32bit access allowed.
- * @param Reg Register to access.
- * @param Bit Bit number to access.
- * @return Value of the targeted bit in the bit band region.
- */
-#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
-#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
-/**
- * @brief Macro to access a single bit of a peripheral register (bit band region
- * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
- * be used for peripherals with 16bit access allowed.
- * @param Reg Register to access.
- * @param Bit Bit number to access.
- * @return Value of the targeted bit in the bit band region.
- */
-#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
-/**
- * @brief Macro to access a single bit of a peripheral register (bit band region
- * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
- * be used for peripherals with 8bit access allowed.
- * @param Reg Register to access.
- * @param Bit Bit number to access.
- * @return Value of the targeted bit in the bit band region.
- */
-#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
-
-/* ----------------------------------------------------------------------------
- -- Interrupt vector numbers
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
- * @{
- */
-
-/** Interrupt Number Definitions */
-typedef enum IRQn {
- /* Core interrupts */
- NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
- HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
- MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
- BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
- SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
- SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
-
- /* Device specific interrupts */
- DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */
- DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */
- DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */
- DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */
- DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */
- DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */
- DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */
- DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */
- DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */
- DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */
- DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */
- DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */
- DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */
- DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */
- DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */
- DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */
- DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
- MCM_IRQn = 17, /**< Normal Interrupt */
- FTFE_IRQn = 18, /**< FTFE Command complete interrupt */
- Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
- LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
- LLW_IRQn = 21, /**< Low Leakage Wakeup */
- Watchdog_IRQn = 22, /**< WDOG Interrupt */
- RNG_IRQn = 23, /**< RNG Interrupt */
- I2C0_IRQn = 24, /**< I2C0 interrupt */
- I2C1_IRQn = 25, /**< I2C1 interrupt */
- SPI0_IRQn = 26, /**< SPI0 Interrupt */
- SPI1_IRQn = 27, /**< SPI1 Interrupt */
- I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */
- I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */
- UART0_LON_IRQn = 30, /**< UART0 LON interrupt */
- UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */
- UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */
- UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */
- UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */
- UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */
- UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */
- UART3_RX_TX_IRQn = 37, /**< UART3 Receive/Transmit interrupt */
- UART3_ERR_IRQn = 38, /**< UART3 Error interrupt */
- ADC0_IRQn = 39, /**< ADC0 interrupt */
- CMP0_IRQn = 40, /**< CMP0 interrupt */
- CMP1_IRQn = 41, /**< CMP1 interrupt */
- FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */
- FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */
- FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */
- CMT_IRQn = 45, /**< CMT interrupt */
- RTC_IRQn = 46, /**< RTC interrupt */
- RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */
- PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */
- PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */
- PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
- PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
- PDB0_IRQn = 52, /**< PDB0 Interrupt */
- USB0_IRQn = 53, /**< USB0 interrupt */
- USBDCD_IRQn = 54, /**< USBDCD Interrupt */
- Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
- DAC0_IRQn = 56, /**< DAC0 interrupt */
- MCG_IRQn = 57, /**< MCG Interrupt */
- LPTimer_IRQn = 58, /**< LPTimer interrupt */
- PORTA_IRQn = 59, /**< Port A interrupt */
- PORTB_IRQn = 60, /**< Port B interrupt */
- PORTC_IRQn = 61, /**< Port C interrupt */
- PORTD_IRQn = 62, /**< Port D interrupt */
- PORTE_IRQn = 63, /**< Port E interrupt */
- SWI_IRQn = 64, /**< Software interrupt */
- SPI2_IRQn = 65, /**< SPI2 Interrupt */
- UART4_RX_TX_IRQn = 66, /**< UART4 Receive/Transmit interrupt */
- UART4_ERR_IRQn = 67, /**< UART4 Error interrupt */
- UART5_RX_TX_IRQn = 68, /**< UART5 Receive/Transmit interrupt */
- UART5_ERR_IRQn = 69, /**< UART5 Error interrupt */
- CMP2_IRQn = 70, /**< CMP2 interrupt */
- FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */
- DAC1_IRQn = 72, /**< DAC1 interrupt */
- ADC1_IRQn = 73, /**< ADC1 interrupt */
- I2C2_IRQn = 74, /**< I2C2 interrupt */
- CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */
- CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */
- CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */
- CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */
- CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */
- CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */
- SDHC_IRQn = 81, /**< SDHC interrupt */
- ENET_1588_Timer_IRQn = 82, /**< Ethernet MAC IEEE 1588 Timer Interrupt */
- ENET_Transmit_IRQn = 83, /**< Ethernet MAC Transmit Interrupt */
- ENET_Receive_IRQn = 84, /**< Ethernet MAC Receive Interrupt */
- ENET_Error_IRQn = 85 /**< Ethernet MAC Error and miscelaneous Interrupt */
-} IRQn_Type;
-
-/*!
- * @}
- */ /* end of group Interrupt_vector_numbers */
-
-
-/* ----------------------------------------------------------------------------
- -- Cortex M4 Core Configuration
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
- * @{
- */
-
-#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
-#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
-#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
-#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
-
-#include "core_cm4.h" /* Core Peripheral Access Layer */
-#include "system_MK64F12.h" /* Device specific configuration file */
-
-/*!
- * @}
- */ /* end of group Cortex_Core_Configuration */
-
-
-/* ----------------------------------------------------------------------------
- -- Device Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
- * @{
- */
-
-
-/*
-** Start of section using anonymous unions
-*/
-
-#if defined(__ARMCC_VERSION)
- #pragma push
- #pragma anon_unions
-#elif defined(__CWCC__)
- #pragma push
- #pragma cpp_extensions on
-#elif defined(__GNUC__)
- /* anonymous unions are enabled by default */
-#elif defined(__IAR_SYSTEMS_ICC__)
- #pragma language=extended
-#else
- #error Not supported compiler type
-#endif
-
-/* ----------------------------------------------------------------------------
- -- ADC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
- * @{
- */
-
-/** ADC - Register Layout Typedef */
-typedef struct {
- __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
- __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
- __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
- __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
- __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
- __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
- __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
- __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
- __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
- __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
- __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
- __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
- __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
- __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
- __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
- __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
- __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
- __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
- uint8_t RESERVED_0[4];
- __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
- __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
- __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
- __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
- __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
- __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
- __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
-} ADC_Type, *ADC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- ADC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
- * @{
- */
-
-
-/* ADC - Register accessors */
-#define ADC_SC1_REG(base,index) ((base)->SC1[index])
-#define ADC_CFG1_REG(base) ((base)->CFG1)
-#define ADC_CFG2_REG(base) ((base)->CFG2)
-#define ADC_R_REG(base,index) ((base)->R[index])
-#define ADC_CV1_REG(base) ((base)->CV1)
-#define ADC_CV2_REG(base) ((base)->CV2)
-#define ADC_SC2_REG(base) ((base)->SC2)
-#define ADC_SC3_REG(base) ((base)->SC3)
-#define ADC_OFS_REG(base) ((base)->OFS)
-#define ADC_PG_REG(base) ((base)->PG)
-#define ADC_MG_REG(base) ((base)->MG)
-#define ADC_CLPD_REG(base) ((base)->CLPD)
-#define ADC_CLPS_REG(base) ((base)->CLPS)
-#define ADC_CLP4_REG(base) ((base)->CLP4)
-#define ADC_CLP3_REG(base) ((base)->CLP3)
-#define ADC_CLP2_REG(base) ((base)->CLP2)
-#define ADC_CLP1_REG(base) ((base)->CLP1)
-#define ADC_CLP0_REG(base) ((base)->CLP0)
-#define ADC_CLMD_REG(base) ((base)->CLMD)
-#define ADC_CLMS_REG(base) ((base)->CLMS)
-#define ADC_CLM4_REG(base) ((base)->CLM4)
-#define ADC_CLM3_REG(base) ((base)->CLM3)
-#define ADC_CLM2_REG(base) ((base)->CLM2)
-#define ADC_CLM1_REG(base) ((base)->CLM1)
-#define ADC_CLM0_REG(base) ((base)->CLM0)
-
-/*!
- * @}
- */ /* end of group ADC_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- ADC Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ADC_Register_Masks ADC Register Masks
- * @{
- */
-
-/* SC1 Bit Fields */
-#define ADC_SC1_ADCH_MASK 0x1Fu
-#define ADC_SC1_ADCH_SHIFT 0
-#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
-#define ADC_SC1_DIFF_MASK 0x20u
-#define ADC_SC1_DIFF_SHIFT 5
-#define ADC_SC1_AIEN_MASK 0x40u
-#define ADC_SC1_AIEN_SHIFT 6
-#define ADC_SC1_COCO_MASK 0x80u
-#define ADC_SC1_COCO_SHIFT 7
-/* CFG1 Bit Fields */
-#define ADC_CFG1_ADICLK_MASK 0x3u
-#define ADC_CFG1_ADICLK_SHIFT 0
-#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
-#define ADC_CFG1_MODE_MASK 0xCu
-#define ADC_CFG1_MODE_SHIFT 2
-#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
-#define ADC_CFG1_ADLSMP_MASK 0x10u
-#define ADC_CFG1_ADLSMP_SHIFT 4
-#define ADC_CFG1_ADIV_MASK 0x60u
-#define ADC_CFG1_ADIV_SHIFT 5
-#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
-#define ADC_CFG1_ADLPC_MASK 0x80u
-#define ADC_CFG1_ADLPC_SHIFT 7
-/* CFG2 Bit Fields */
-#define ADC_CFG2_ADLSTS_MASK 0x3u
-#define ADC_CFG2_ADLSTS_SHIFT 0
-#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
-#define ADC_CFG2_ADHSC_MASK 0x4u
-#define ADC_CFG2_ADHSC_SHIFT 2
-#define ADC_CFG2_ADACKEN_MASK 0x8u
-#define ADC_CFG2_ADACKEN_SHIFT 3
-#define ADC_CFG2_MUXSEL_MASK 0x10u
-#define ADC_CFG2_MUXSEL_SHIFT 4
-/* R Bit Fields */
-#define ADC_R_D_MASK 0xFFFFu
-#define ADC_R_D_SHIFT 0
-#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
-/* CV1 Bit Fields */
-#define ADC_CV1_CV_MASK 0xFFFFu
-#define ADC_CV1_CV_SHIFT 0
-#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
-/* CV2 Bit Fields */
-#define ADC_CV2_CV_MASK 0xFFFFu
-#define ADC_CV2_CV_SHIFT 0
-#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
-/* SC2 Bit Fields */
-#define ADC_SC2_REFSEL_MASK 0x3u
-#define ADC_SC2_REFSEL_SHIFT 0
-#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
-#define ADC_SC2_DMAEN_MASK 0x4u
-#define ADC_SC2_DMAEN_SHIFT 2
-#define ADC_SC2_ACREN_MASK 0x8u
-#define ADC_SC2_ACREN_SHIFT 3
-#define ADC_SC2_ACFGT_MASK 0x10u
-#define ADC_SC2_ACFGT_SHIFT 4
-#define ADC_SC2_ACFE_MASK 0x20u
-#define ADC_SC2_ACFE_SHIFT 5
-#define ADC_SC2_ADTRG_MASK 0x40u
-#define ADC_SC2_ADTRG_SHIFT 6
-#define ADC_SC2_ADACT_MASK 0x80u
-#define ADC_SC2_ADACT_SHIFT 7
-/* SC3 Bit Fields */
-#define ADC_SC3_AVGS_MASK 0x3u
-#define ADC_SC3_AVGS_SHIFT 0
-#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
-#define ADC_SC3_AVGE_MASK 0x4u
-#define ADC_SC3_AVGE_SHIFT 2
-#define ADC_SC3_ADCO_MASK 0x8u
-#define ADC_SC3_ADCO_SHIFT 3
-#define ADC_SC3_CALF_MASK 0x40u
-#define ADC_SC3_CALF_SHIFT 6
-#define ADC_SC3_CAL_MASK 0x80u
-#define ADC_SC3_CAL_SHIFT 7
-/* OFS Bit Fields */
-#define ADC_OFS_OFS_MASK 0xFFFFu
-#define ADC_OFS_OFS_SHIFT 0
-#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
-/* PG Bit Fields */
-#define ADC_PG_PG_MASK 0xFFFFu
-#define ADC_PG_PG_SHIFT 0
-#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
-/* MG Bit Fields */
-#define ADC_MG_MG_MASK 0xFFFFu
-#define ADC_MG_MG_SHIFT 0
-#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
-/* CLPD Bit Fields */
-#define ADC_CLPD_CLPD_MASK 0x3Fu
-#define ADC_CLPD_CLPD_SHIFT 0
-#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
-/* CLPS Bit Fields */
-#define ADC_CLPS_CLPS_MASK 0x3Fu
-#define ADC_CLPS_CLPS_SHIFT 0
-#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
-/* CLP4 Bit Fields */
-#define ADC_CLP4_CLP4_MASK 0x3FFu
-#define ADC_CLP4_CLP4_SHIFT 0
-#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
-/* CLP3 Bit Fields */
-#define ADC_CLP3_CLP3_MASK 0x1FFu
-#define ADC_CLP3_CLP3_SHIFT 0
-#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
-/* CLP2 Bit Fields */
-#define ADC_CLP2_CLP2_MASK 0xFFu
-#define ADC_CLP2_CLP2_SHIFT 0
-#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
-/* CLP1 Bit Fields */
-#define ADC_CLP1_CLP1_MASK 0x7Fu
-#define ADC_CLP1_CLP1_SHIFT 0
-#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
-/* CLP0 Bit Fields */
-#define ADC_CLP0_CLP0_MASK 0x3Fu
-#define ADC_CLP0_CLP0_SHIFT 0
-#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
-/* CLMD Bit Fields */
-#define ADC_CLMD_CLMD_MASK 0x3Fu
-#define ADC_CLMD_CLMD_SHIFT 0
-#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
-/* CLMS Bit Fields */
-#define ADC_CLMS_CLMS_MASK 0x3Fu
-#define ADC_CLMS_CLMS_SHIFT 0
-#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
-/* CLM4 Bit Fields */
-#define ADC_CLM4_CLM4_MASK 0x3FFu
-#define ADC_CLM4_CLM4_SHIFT 0
-#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
-/* CLM3 Bit Fields */
-#define ADC_CLM3_CLM3_MASK 0x1FFu
-#define ADC_CLM3_CLM3_SHIFT 0
-#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
-/* CLM2 Bit Fields */
-#define ADC_CLM2_CLM2_MASK 0xFFu
-#define ADC_CLM2_CLM2_SHIFT 0
-#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
-/* CLM1 Bit Fields */
-#define ADC_CLM1_CLM1_MASK 0x7Fu
-#define ADC_CLM1_CLM1_SHIFT 0
-#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
-/* CLM0 Bit Fields */
-#define ADC_CLM0_CLM0_MASK 0x3Fu
-#define ADC_CLM0_CLM0_SHIFT 0
-#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
-
-/*!
- * @}
- */ /* end of group ADC_Register_Masks */
-
-
-/* ADC - Peripheral instance base addresses */
-/** Peripheral ADC0 base address */
-#define ADC0_BASE (0x4003B000u)
-/** Peripheral ADC0 base pointer */
-#define ADC0 ((ADC_Type *)ADC0_BASE)
-#define ADC0_BASE_PTR (ADC0)
-/** Peripheral ADC1 base address */
-#define ADC1_BASE (0x400BB000u)
-/** Peripheral ADC1 base pointer */
-#define ADC1 ((ADC_Type *)ADC1_BASE)
-#define ADC1_BASE_PTR (ADC1)
-/** Array initializer of ADC peripheral base pointers */
-#define ADC_BASES { ADC0, ADC1 }
-
-/* ----------------------------------------------------------------------------
- -- ADC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
- * @{
- */
-
-
-/* ADC - Register instance definitions */
-/* ADC0 */
-#define ADC0_SC1A ADC_SC1_REG(ADC0,0)
-#define ADC0_SC1B ADC_SC1_REG(ADC0,1)
-#define ADC0_CFG1 ADC_CFG1_REG(ADC0)
-#define ADC0_CFG2 ADC_CFG2_REG(ADC0)
-#define ADC0_RA ADC_R_REG(ADC0,0)
-#define ADC0_RB ADC_R_REG(ADC0,1)
-#define ADC0_CV1 ADC_CV1_REG(ADC0)
-#define ADC0_CV2 ADC_CV2_REG(ADC0)
-#define ADC0_SC2 ADC_SC2_REG(ADC0)
-#define ADC0_SC3 ADC_SC3_REG(ADC0)
-#define ADC0_OFS ADC_OFS_REG(ADC0)
-#define ADC0_PG ADC_PG_REG(ADC0)
-#define ADC0_MG ADC_MG_REG(ADC0)
-#define ADC0_CLPD ADC_CLPD_REG(ADC0)
-#define ADC0_CLPS ADC_CLPS_REG(ADC0)
-#define ADC0_CLP4 ADC_CLP4_REG(ADC0)
-#define ADC0_CLP3 ADC_CLP3_REG(ADC0)
-#define ADC0_CLP2 ADC_CLP2_REG(ADC0)
-#define ADC0_CLP1 ADC_CLP1_REG(ADC0)
-#define ADC0_CLP0 ADC_CLP0_REG(ADC0)
-#define ADC0_CLMD ADC_CLMD_REG(ADC0)
-#define ADC0_CLMS ADC_CLMS_REG(ADC0)
-#define ADC0_CLM4 ADC_CLM4_REG(ADC0)
-#define ADC0_CLM3 ADC_CLM3_REG(ADC0)
-#define ADC0_CLM2 ADC_CLM2_REG(ADC0)
-#define ADC0_CLM1 ADC_CLM1_REG(ADC0)
-#define ADC0_CLM0 ADC_CLM0_REG(ADC0)
-/* ADC1 */
-#define ADC1_SC1A ADC_SC1_REG(ADC1,0)
-#define ADC1_SC1B ADC_SC1_REG(ADC1,1)
-#define ADC1_CFG1 ADC_CFG1_REG(ADC1)
-#define ADC1_CFG2 ADC_CFG2_REG(ADC1)
-#define ADC1_RA ADC_R_REG(ADC1,0)
-#define ADC1_RB ADC_R_REG(ADC1,1)
-#define ADC1_CV1 ADC_CV1_REG(ADC1)
-#define ADC1_CV2 ADC_CV2_REG(ADC1)
-#define ADC1_SC2 ADC_SC2_REG(ADC1)
-#define ADC1_SC3 ADC_SC3_REG(ADC1)
-#define ADC1_OFS ADC_OFS_REG(ADC1)
-#define ADC1_PG ADC_PG_REG(ADC1)
-#define ADC1_MG ADC_MG_REG(ADC1)
-#define ADC1_CLPD ADC_CLPD_REG(ADC1)
-#define ADC1_CLPS ADC_CLPS_REG(ADC1)
-#define ADC1_CLP4 ADC_CLP4_REG(ADC1)
-#define ADC1_CLP3 ADC_CLP3_REG(ADC1)
-#define ADC1_CLP2 ADC_CLP2_REG(ADC1)
-#define ADC1_CLP1 ADC_CLP1_REG(ADC1)
-#define ADC1_CLP0 ADC_CLP0_REG(ADC1)
-#define ADC1_CLMD ADC_CLMD_REG(ADC1)
-#define ADC1_CLMS ADC_CLMS_REG(ADC1)
-#define ADC1_CLM4 ADC_CLM4_REG(ADC1)
-#define ADC1_CLM3 ADC_CLM3_REG(ADC1)
-#define ADC1_CLM2 ADC_CLM2_REG(ADC1)
-#define ADC1_CLM1 ADC_CLM1_REG(ADC1)
-#define ADC1_CLM0 ADC_CLM0_REG(ADC1)
-
-/* ADC - Register array accessors */
-#define ADC0_SC1(index) ADC_SC1_REG(ADC0,index)
-#define ADC1_SC1(index) ADC_SC1_REG(ADC1,index)
-#define ADC0_R(index) ADC_R_REG(ADC0,index)
-#define ADC1_R(index) ADC_R_REG(ADC1,index)
-
-/*!
- * @}
- */ /* end of group ADC_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group ADC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- AIPS Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
- * @{
- */
-
-/** AIPS - Register Layout Typedef */
-typedef struct {
- __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
- uint8_t RESERVED_0[28];
- __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
- __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
- __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
- __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
- uint8_t RESERVED_1[16];
- __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
- __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
- __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
- __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
- __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
- __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
- __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
- __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
- __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
- __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
- __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
- __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
- uint8_t RESERVED_2[16];
- __IO uint32_t PACRU; /**< Peripheral Access Control Register, offset: 0x80 */
-} AIPS_Type, *AIPS_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- AIPS - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
- * @{
- */
-
-
-/* AIPS - Register accessors */
-#define AIPS_MPRA_REG(base) ((base)->MPRA)
-#define AIPS_PACRA_REG(base) ((base)->PACRA)
-#define AIPS_PACRB_REG(base) ((base)->PACRB)
-#define AIPS_PACRC_REG(base) ((base)->PACRC)
-#define AIPS_PACRD_REG(base) ((base)->PACRD)
-#define AIPS_PACRE_REG(base) ((base)->PACRE)
-#define AIPS_PACRF_REG(base) ((base)->PACRF)
-#define AIPS_PACRG_REG(base) ((base)->PACRG)
-#define AIPS_PACRH_REG(base) ((base)->PACRH)
-#define AIPS_PACRI_REG(base) ((base)->PACRI)
-#define AIPS_PACRJ_REG(base) ((base)->PACRJ)
-#define AIPS_PACRK_REG(base) ((base)->PACRK)
-#define AIPS_PACRL_REG(base) ((base)->PACRL)
-#define AIPS_PACRM_REG(base) ((base)->PACRM)
-#define AIPS_PACRN_REG(base) ((base)->PACRN)
-#define AIPS_PACRO_REG(base) ((base)->PACRO)
-#define AIPS_PACRP_REG(base) ((base)->PACRP)
-#define AIPS_PACRU_REG(base) ((base)->PACRU)
-
-/*!
- * @}
- */ /* end of group AIPS_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- AIPS Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup AIPS_Register_Masks AIPS Register Masks
- * @{
- */
-
-/* MPRA Bit Fields */
-#define AIPS_MPRA_MPL5_MASK 0x100u
-#define AIPS_MPRA_MPL5_SHIFT 8
-#define AIPS_MPRA_MTW5_MASK 0x200u
-#define AIPS_MPRA_MTW5_SHIFT 9
-#define AIPS_MPRA_MTR5_MASK 0x400u
-#define AIPS_MPRA_MTR5_SHIFT 10
-#define AIPS_MPRA_MPL4_MASK 0x1000u
-#define AIPS_MPRA_MPL4_SHIFT 12
-#define AIPS_MPRA_MTW4_MASK 0x2000u
-#define AIPS_MPRA_MTW4_SHIFT 13
-#define AIPS_MPRA_MTR4_MASK 0x4000u
-#define AIPS_MPRA_MTR4_SHIFT 14
-#define AIPS_MPRA_MPL3_MASK 0x10000u
-#define AIPS_MPRA_MPL3_SHIFT 16
-#define AIPS_MPRA_MTW3_MASK 0x20000u
-#define AIPS_MPRA_MTW3_SHIFT 17
-#define AIPS_MPRA_MTR3_MASK 0x40000u
-#define AIPS_MPRA_MTR3_SHIFT 18
-#define AIPS_MPRA_MPL2_MASK 0x100000u
-#define AIPS_MPRA_MPL2_SHIFT 20
-#define AIPS_MPRA_MTW2_MASK 0x200000u
-#define AIPS_MPRA_MTW2_SHIFT 21
-#define AIPS_MPRA_MTR2_MASK 0x400000u
-#define AIPS_MPRA_MTR2_SHIFT 22
-#define AIPS_MPRA_MPL1_MASK 0x1000000u
-#define AIPS_MPRA_MPL1_SHIFT 24
-#define AIPS_MPRA_MTW1_MASK 0x2000000u
-#define AIPS_MPRA_MTW1_SHIFT 25
-#define AIPS_MPRA_MTR1_MASK 0x4000000u
-#define AIPS_MPRA_MTR1_SHIFT 26
-#define AIPS_MPRA_MPL0_MASK 0x10000000u
-#define AIPS_MPRA_MPL0_SHIFT 28
-#define AIPS_MPRA_MTW0_MASK 0x20000000u
-#define AIPS_MPRA_MTW0_SHIFT 29
-#define AIPS_MPRA_MTR0_MASK 0x40000000u
-#define AIPS_MPRA_MTR0_SHIFT 30
-/* PACRA Bit Fields */
-#define AIPS_PACRA_TP7_MASK 0x1u
-#define AIPS_PACRA_TP7_SHIFT 0
-#define AIPS_PACRA_WP7_MASK 0x2u
-#define AIPS_PACRA_WP7_SHIFT 1
-#define AIPS_PACRA_SP7_MASK 0x4u
-#define AIPS_PACRA_SP7_SHIFT 2
-#define AIPS_PACRA_TP6_MASK 0x10u
-#define AIPS_PACRA_TP6_SHIFT 4
-#define AIPS_PACRA_WP6_MASK 0x20u
-#define AIPS_PACRA_WP6_SHIFT 5
-#define AIPS_PACRA_SP6_MASK 0x40u
-#define AIPS_PACRA_SP6_SHIFT 6
-#define AIPS_PACRA_TP5_MASK 0x100u
-#define AIPS_PACRA_TP5_SHIFT 8
-#define AIPS_PACRA_WP5_MASK 0x200u
-#define AIPS_PACRA_WP5_SHIFT 9
-#define AIPS_PACRA_SP5_MASK 0x400u
-#define AIPS_PACRA_SP5_SHIFT 10
-#define AIPS_PACRA_TP4_MASK 0x1000u
-#define AIPS_PACRA_TP4_SHIFT 12
-#define AIPS_PACRA_WP4_MASK 0x2000u
-#define AIPS_PACRA_WP4_SHIFT 13
-#define AIPS_PACRA_SP4_MASK 0x4000u
-#define AIPS_PACRA_SP4_SHIFT 14
-#define AIPS_PACRA_TP3_MASK 0x10000u
-#define AIPS_PACRA_TP3_SHIFT 16
-#define AIPS_PACRA_WP3_MASK 0x20000u
-#define AIPS_PACRA_WP3_SHIFT 17
-#define AIPS_PACRA_SP3_MASK 0x40000u
-#define AIPS_PACRA_SP3_SHIFT 18
-#define AIPS_PACRA_TP2_MASK 0x100000u
-#define AIPS_PACRA_TP2_SHIFT 20
-#define AIPS_PACRA_WP2_MASK 0x200000u
-#define AIPS_PACRA_WP2_SHIFT 21
-#define AIPS_PACRA_SP2_MASK 0x400000u
-#define AIPS_PACRA_SP2_SHIFT 22
-#define AIPS_PACRA_TP1_MASK 0x1000000u
-#define AIPS_PACRA_TP1_SHIFT 24
-#define AIPS_PACRA_WP1_MASK 0x2000000u
-#define AIPS_PACRA_WP1_SHIFT 25
-#define AIPS_PACRA_SP1_MASK 0x4000000u
-#define AIPS_PACRA_SP1_SHIFT 26
-#define AIPS_PACRA_TP0_MASK 0x10000000u
-#define AIPS_PACRA_TP0_SHIFT 28
-#define AIPS_PACRA_WP0_MASK 0x20000000u
-#define AIPS_PACRA_WP0_SHIFT 29
-#define AIPS_PACRA_SP0_MASK 0x40000000u
-#define AIPS_PACRA_SP0_SHIFT 30
-/* PACRB Bit Fields */
-#define AIPS_PACRB_TP7_MASK 0x1u
-#define AIPS_PACRB_TP7_SHIFT 0
-#define AIPS_PACRB_WP7_MASK 0x2u
-#define AIPS_PACRB_WP7_SHIFT 1
-#define AIPS_PACRB_SP7_MASK 0x4u
-#define AIPS_PACRB_SP7_SHIFT 2
-#define AIPS_PACRB_TP6_MASK 0x10u
-#define AIPS_PACRB_TP6_SHIFT 4
-#define AIPS_PACRB_WP6_MASK 0x20u
-#define AIPS_PACRB_WP6_SHIFT 5
-#define AIPS_PACRB_SP6_MASK 0x40u
-#define AIPS_PACRB_SP6_SHIFT 6
-#define AIPS_PACRB_TP5_MASK 0x100u
-#define AIPS_PACRB_TP5_SHIFT 8
-#define AIPS_PACRB_WP5_MASK 0x200u
-#define AIPS_PACRB_WP5_SHIFT 9
-#define AIPS_PACRB_SP5_MASK 0x400u
-#define AIPS_PACRB_SP5_SHIFT 10
-#define AIPS_PACRB_TP4_MASK 0x1000u
-#define AIPS_PACRB_TP4_SHIFT 12
-#define AIPS_PACRB_WP4_MASK 0x2000u
-#define AIPS_PACRB_WP4_SHIFT 13
-#define AIPS_PACRB_SP4_MASK 0x4000u
-#define AIPS_PACRB_SP4_SHIFT 14
-#define AIPS_PACRB_TP3_MASK 0x10000u
-#define AIPS_PACRB_TP3_SHIFT 16
-#define AIPS_PACRB_WP3_MASK 0x20000u
-#define AIPS_PACRB_WP3_SHIFT 17
-#define AIPS_PACRB_SP3_MASK 0x40000u
-#define AIPS_PACRB_SP3_SHIFT 18
-#define AIPS_PACRB_TP2_MASK 0x100000u
-#define AIPS_PACRB_TP2_SHIFT 20
-#define AIPS_PACRB_WP2_MASK 0x200000u
-#define AIPS_PACRB_WP2_SHIFT 21
-#define AIPS_PACRB_SP2_MASK 0x400000u
-#define AIPS_PACRB_SP2_SHIFT 22
-#define AIPS_PACRB_TP1_MASK 0x1000000u
-#define AIPS_PACRB_TP1_SHIFT 24
-#define AIPS_PACRB_WP1_MASK 0x2000000u
-#define AIPS_PACRB_WP1_SHIFT 25
-#define AIPS_PACRB_SP1_MASK 0x4000000u
-#define AIPS_PACRB_SP1_SHIFT 26
-#define AIPS_PACRB_TP0_MASK 0x10000000u
-#define AIPS_PACRB_TP0_SHIFT 28
-#define AIPS_PACRB_WP0_MASK 0x20000000u
-#define AIPS_PACRB_WP0_SHIFT 29
-#define AIPS_PACRB_SP0_MASK 0x40000000u
-#define AIPS_PACRB_SP0_SHIFT 30
-/* PACRC Bit Fields */
-#define AIPS_PACRC_TP7_MASK 0x1u
-#define AIPS_PACRC_TP7_SHIFT 0
-#define AIPS_PACRC_WP7_MASK 0x2u
-#define AIPS_PACRC_WP7_SHIFT 1
-#define AIPS_PACRC_SP7_MASK 0x4u
-#define AIPS_PACRC_SP7_SHIFT 2
-#define AIPS_PACRC_TP6_MASK 0x10u
-#define AIPS_PACRC_TP6_SHIFT 4
-#define AIPS_PACRC_WP6_MASK 0x20u
-#define AIPS_PACRC_WP6_SHIFT 5
-#define AIPS_PACRC_SP6_MASK 0x40u
-#define AIPS_PACRC_SP6_SHIFT 6
-#define AIPS_PACRC_TP5_MASK 0x100u
-#define AIPS_PACRC_TP5_SHIFT 8
-#define AIPS_PACRC_WP5_MASK 0x200u
-#define AIPS_PACRC_WP5_SHIFT 9
-#define AIPS_PACRC_SP5_MASK 0x400u
-#define AIPS_PACRC_SP5_SHIFT 10
-#define AIPS_PACRC_TP4_MASK 0x1000u
-#define AIPS_PACRC_TP4_SHIFT 12
-#define AIPS_PACRC_WP4_MASK 0x2000u
-#define AIPS_PACRC_WP4_SHIFT 13
-#define AIPS_PACRC_SP4_MASK 0x4000u
-#define AIPS_PACRC_SP4_SHIFT 14
-#define AIPS_PACRC_TP3_MASK 0x10000u
-#define AIPS_PACRC_TP3_SHIFT 16
-#define AIPS_PACRC_WP3_MASK 0x20000u
-#define AIPS_PACRC_WP3_SHIFT 17
-#define AIPS_PACRC_SP3_MASK 0x40000u
-#define AIPS_PACRC_SP3_SHIFT 18
-#define AIPS_PACRC_TP2_MASK 0x100000u
-#define AIPS_PACRC_TP2_SHIFT 20
-#define AIPS_PACRC_WP2_MASK 0x200000u
-#define AIPS_PACRC_WP2_SHIFT 21
-#define AIPS_PACRC_SP2_MASK 0x400000u
-#define AIPS_PACRC_SP2_SHIFT 22
-#define AIPS_PACRC_TP1_MASK 0x1000000u
-#define AIPS_PACRC_TP1_SHIFT 24
-#define AIPS_PACRC_WP1_MASK 0x2000000u
-#define AIPS_PACRC_WP1_SHIFT 25
-#define AIPS_PACRC_SP1_MASK 0x4000000u
-#define AIPS_PACRC_SP1_SHIFT 26
-#define AIPS_PACRC_TP0_MASK 0x10000000u
-#define AIPS_PACRC_TP0_SHIFT 28
-#define AIPS_PACRC_WP0_MASK 0x20000000u
-#define AIPS_PACRC_WP0_SHIFT 29
-#define AIPS_PACRC_SP0_MASK 0x40000000u
-#define AIPS_PACRC_SP0_SHIFT 30
-/* PACRD Bit Fields */
-#define AIPS_PACRD_TP7_MASK 0x1u
-#define AIPS_PACRD_TP7_SHIFT 0
-#define AIPS_PACRD_WP7_MASK 0x2u
-#define AIPS_PACRD_WP7_SHIFT 1
-#define AIPS_PACRD_SP7_MASK 0x4u
-#define AIPS_PACRD_SP7_SHIFT 2
-#define AIPS_PACRD_TP6_MASK 0x10u
-#define AIPS_PACRD_TP6_SHIFT 4
-#define AIPS_PACRD_WP6_MASK 0x20u
-#define AIPS_PACRD_WP6_SHIFT 5
-#define AIPS_PACRD_SP6_MASK 0x40u
-#define AIPS_PACRD_SP6_SHIFT 6
-#define AIPS_PACRD_TP5_MASK 0x100u
-#define AIPS_PACRD_TP5_SHIFT 8
-#define AIPS_PACRD_WP5_MASK 0x200u
-#define AIPS_PACRD_WP5_SHIFT 9
-#define AIPS_PACRD_SP5_MASK 0x400u
-#define AIPS_PACRD_SP5_SHIFT 10
-#define AIPS_PACRD_TP4_MASK 0x1000u
-#define AIPS_PACRD_TP4_SHIFT 12
-#define AIPS_PACRD_WP4_MASK 0x2000u
-#define AIPS_PACRD_WP4_SHIFT 13
-#define AIPS_PACRD_SP4_MASK 0x4000u
-#define AIPS_PACRD_SP4_SHIFT 14
-#define AIPS_PACRD_TP3_MASK 0x10000u
-#define AIPS_PACRD_TP3_SHIFT 16
-#define AIPS_PACRD_WP3_MASK 0x20000u
-#define AIPS_PACRD_WP3_SHIFT 17
-#define AIPS_PACRD_SP3_MASK 0x40000u
-#define AIPS_PACRD_SP3_SHIFT 18
-#define AIPS_PACRD_TP2_MASK 0x100000u
-#define AIPS_PACRD_TP2_SHIFT 20
-#define AIPS_PACRD_WP2_MASK 0x200000u
-#define AIPS_PACRD_WP2_SHIFT 21
-#define AIPS_PACRD_SP2_MASK 0x400000u
-#define AIPS_PACRD_SP2_SHIFT 22
-#define AIPS_PACRD_TP1_MASK 0x1000000u
-#define AIPS_PACRD_TP1_SHIFT 24
-#define AIPS_PACRD_WP1_MASK 0x2000000u
-#define AIPS_PACRD_WP1_SHIFT 25
-#define AIPS_PACRD_SP1_MASK 0x4000000u
-#define AIPS_PACRD_SP1_SHIFT 26
-#define AIPS_PACRD_TP0_MASK 0x10000000u
-#define AIPS_PACRD_TP0_SHIFT 28
-#define AIPS_PACRD_WP0_MASK 0x20000000u
-#define AIPS_PACRD_WP0_SHIFT 29
-#define AIPS_PACRD_SP0_MASK 0x40000000u
-#define AIPS_PACRD_SP0_SHIFT 30
-/* PACRE Bit Fields */
-#define AIPS_PACRE_TP7_MASK 0x1u
-#define AIPS_PACRE_TP7_SHIFT 0
-#define AIPS_PACRE_WP7_MASK 0x2u
-#define AIPS_PACRE_WP7_SHIFT 1
-#define AIPS_PACRE_SP7_MASK 0x4u
-#define AIPS_PACRE_SP7_SHIFT 2
-#define AIPS_PACRE_TP6_MASK 0x10u
-#define AIPS_PACRE_TP6_SHIFT 4
-#define AIPS_PACRE_WP6_MASK 0x20u
-#define AIPS_PACRE_WP6_SHIFT 5
-#define AIPS_PACRE_SP6_MASK 0x40u
-#define AIPS_PACRE_SP6_SHIFT 6
-#define AIPS_PACRE_TP5_MASK 0x100u
-#define AIPS_PACRE_TP5_SHIFT 8
-#define AIPS_PACRE_WP5_MASK 0x200u
-#define AIPS_PACRE_WP5_SHIFT 9
-#define AIPS_PACRE_SP5_MASK 0x400u
-#define AIPS_PACRE_SP5_SHIFT 10
-#define AIPS_PACRE_TP4_MASK 0x1000u
-#define AIPS_PACRE_TP4_SHIFT 12
-#define AIPS_PACRE_WP4_MASK 0x2000u
-#define AIPS_PACRE_WP4_SHIFT 13
-#define AIPS_PACRE_SP4_MASK 0x4000u
-#define AIPS_PACRE_SP4_SHIFT 14
-#define AIPS_PACRE_TP3_MASK 0x10000u
-#define AIPS_PACRE_TP3_SHIFT 16
-#define AIPS_PACRE_WP3_MASK 0x20000u
-#define AIPS_PACRE_WP3_SHIFT 17
-#define AIPS_PACRE_SP3_MASK 0x40000u
-#define AIPS_PACRE_SP3_SHIFT 18
-#define AIPS_PACRE_TP2_MASK 0x100000u
-#define AIPS_PACRE_TP2_SHIFT 20
-#define AIPS_PACRE_WP2_MASK 0x200000u
-#define AIPS_PACRE_WP2_SHIFT 21
-#define AIPS_PACRE_SP2_MASK 0x400000u
-#define AIPS_PACRE_SP2_SHIFT 22
-#define AIPS_PACRE_TP1_MASK 0x1000000u
-#define AIPS_PACRE_TP1_SHIFT 24
-#define AIPS_PACRE_WP1_MASK 0x2000000u
-#define AIPS_PACRE_WP1_SHIFT 25
-#define AIPS_PACRE_SP1_MASK 0x4000000u
-#define AIPS_PACRE_SP1_SHIFT 26
-#define AIPS_PACRE_TP0_MASK 0x10000000u
-#define AIPS_PACRE_TP0_SHIFT 28
-#define AIPS_PACRE_WP0_MASK 0x20000000u
-#define AIPS_PACRE_WP0_SHIFT 29
-#define AIPS_PACRE_SP0_MASK 0x40000000u
-#define AIPS_PACRE_SP0_SHIFT 30
-/* PACRF Bit Fields */
-#define AIPS_PACRF_TP7_MASK 0x1u
-#define AIPS_PACRF_TP7_SHIFT 0
-#define AIPS_PACRF_WP7_MASK 0x2u
-#define AIPS_PACRF_WP7_SHIFT 1
-#define AIPS_PACRF_SP7_MASK 0x4u
-#define AIPS_PACRF_SP7_SHIFT 2
-#define AIPS_PACRF_TP6_MASK 0x10u
-#define AIPS_PACRF_TP6_SHIFT 4
-#define AIPS_PACRF_WP6_MASK 0x20u
-#define AIPS_PACRF_WP6_SHIFT 5
-#define AIPS_PACRF_SP6_MASK 0x40u
-#define AIPS_PACRF_SP6_SHIFT 6
-#define AIPS_PACRF_TP5_MASK 0x100u
-#define AIPS_PACRF_TP5_SHIFT 8
-#define AIPS_PACRF_WP5_MASK 0x200u
-#define AIPS_PACRF_WP5_SHIFT 9
-#define AIPS_PACRF_SP5_MASK 0x400u
-#define AIPS_PACRF_SP5_SHIFT 10
-#define AIPS_PACRF_TP4_MASK 0x1000u
-#define AIPS_PACRF_TP4_SHIFT 12
-#define AIPS_PACRF_WP4_MASK 0x2000u
-#define AIPS_PACRF_WP4_SHIFT 13
-#define AIPS_PACRF_SP4_MASK 0x4000u
-#define AIPS_PACRF_SP4_SHIFT 14
-#define AIPS_PACRF_TP3_MASK 0x10000u
-#define AIPS_PACRF_TP3_SHIFT 16
-#define AIPS_PACRF_WP3_MASK 0x20000u
-#define AIPS_PACRF_WP3_SHIFT 17
-#define AIPS_PACRF_SP3_MASK 0x40000u
-#define AIPS_PACRF_SP3_SHIFT 18
-#define AIPS_PACRF_TP2_MASK 0x100000u
-#define AIPS_PACRF_TP2_SHIFT 20
-#define AIPS_PACRF_WP2_MASK 0x200000u
-#define AIPS_PACRF_WP2_SHIFT 21
-#define AIPS_PACRF_SP2_MASK 0x400000u
-#define AIPS_PACRF_SP2_SHIFT 22
-#define AIPS_PACRF_TP1_MASK 0x1000000u
-#define AIPS_PACRF_TP1_SHIFT 24
-#define AIPS_PACRF_WP1_MASK 0x2000000u
-#define AIPS_PACRF_WP1_SHIFT 25
-#define AIPS_PACRF_SP1_MASK 0x4000000u
-#define AIPS_PACRF_SP1_SHIFT 26
-#define AIPS_PACRF_TP0_MASK 0x10000000u
-#define AIPS_PACRF_TP0_SHIFT 28
-#define AIPS_PACRF_WP0_MASK 0x20000000u
-#define AIPS_PACRF_WP0_SHIFT 29
-#define AIPS_PACRF_SP0_MASK 0x40000000u
-#define AIPS_PACRF_SP0_SHIFT 30
-/* PACRG Bit Fields */
-#define AIPS_PACRG_TP7_MASK 0x1u
-#define AIPS_PACRG_TP7_SHIFT 0
-#define AIPS_PACRG_WP7_MASK 0x2u
-#define AIPS_PACRG_WP7_SHIFT 1
-#define AIPS_PACRG_SP7_MASK 0x4u
-#define AIPS_PACRG_SP7_SHIFT 2
-#define AIPS_PACRG_TP6_MASK 0x10u
-#define AIPS_PACRG_TP6_SHIFT 4
-#define AIPS_PACRG_WP6_MASK 0x20u
-#define AIPS_PACRG_WP6_SHIFT 5
-#define AIPS_PACRG_SP6_MASK 0x40u
-#define AIPS_PACRG_SP6_SHIFT 6
-#define AIPS_PACRG_TP5_MASK 0x100u
-#define AIPS_PACRG_TP5_SHIFT 8
-#define AIPS_PACRG_WP5_MASK 0x200u
-#define AIPS_PACRG_WP5_SHIFT 9
-#define AIPS_PACRG_SP5_MASK 0x400u
-#define AIPS_PACRG_SP5_SHIFT 10
-#define AIPS_PACRG_TP4_MASK 0x1000u
-#define AIPS_PACRG_TP4_SHIFT 12
-#define AIPS_PACRG_WP4_MASK 0x2000u
-#define AIPS_PACRG_WP4_SHIFT 13
-#define AIPS_PACRG_SP4_MASK 0x4000u
-#define AIPS_PACRG_SP4_SHIFT 14
-#define AIPS_PACRG_TP3_MASK 0x10000u
-#define AIPS_PACRG_TP3_SHIFT 16
-#define AIPS_PACRG_WP3_MASK 0x20000u
-#define AIPS_PACRG_WP3_SHIFT 17
-#define AIPS_PACRG_SP3_MASK 0x40000u
-#define AIPS_PACRG_SP3_SHIFT 18
-#define AIPS_PACRG_TP2_MASK 0x100000u
-#define AIPS_PACRG_TP2_SHIFT 20
-#define AIPS_PACRG_WP2_MASK 0x200000u
-#define AIPS_PACRG_WP2_SHIFT 21
-#define AIPS_PACRG_SP2_MASK 0x400000u
-#define AIPS_PACRG_SP2_SHIFT 22
-#define AIPS_PACRG_TP1_MASK 0x1000000u
-#define AIPS_PACRG_TP1_SHIFT 24
-#define AIPS_PACRG_WP1_MASK 0x2000000u
-#define AIPS_PACRG_WP1_SHIFT 25
-#define AIPS_PACRG_SP1_MASK 0x4000000u
-#define AIPS_PACRG_SP1_SHIFT 26
-#define AIPS_PACRG_TP0_MASK 0x10000000u
-#define AIPS_PACRG_TP0_SHIFT 28
-#define AIPS_PACRG_WP0_MASK 0x20000000u
-#define AIPS_PACRG_WP0_SHIFT 29
-#define AIPS_PACRG_SP0_MASK 0x40000000u
-#define AIPS_PACRG_SP0_SHIFT 30
-/* PACRH Bit Fields */
-#define AIPS_PACRH_TP7_MASK 0x1u
-#define AIPS_PACRH_TP7_SHIFT 0
-#define AIPS_PACRH_WP7_MASK 0x2u
-#define AIPS_PACRH_WP7_SHIFT 1
-#define AIPS_PACRH_SP7_MASK 0x4u
-#define AIPS_PACRH_SP7_SHIFT 2
-#define AIPS_PACRH_TP6_MASK 0x10u
-#define AIPS_PACRH_TP6_SHIFT 4
-#define AIPS_PACRH_WP6_MASK 0x20u
-#define AIPS_PACRH_WP6_SHIFT 5
-#define AIPS_PACRH_SP6_MASK 0x40u
-#define AIPS_PACRH_SP6_SHIFT 6
-#define AIPS_PACRH_TP5_MASK 0x100u
-#define AIPS_PACRH_TP5_SHIFT 8
-#define AIPS_PACRH_WP5_MASK 0x200u
-#define AIPS_PACRH_WP5_SHIFT 9
-#define AIPS_PACRH_SP5_MASK 0x400u
-#define AIPS_PACRH_SP5_SHIFT 10
-#define AIPS_PACRH_TP4_MASK 0x1000u
-#define AIPS_PACRH_TP4_SHIFT 12
-#define AIPS_PACRH_WP4_MASK 0x2000u
-#define AIPS_PACRH_WP4_SHIFT 13
-#define AIPS_PACRH_SP4_MASK 0x4000u
-#define AIPS_PACRH_SP4_SHIFT 14
-#define AIPS_PACRH_TP3_MASK 0x10000u
-#define AIPS_PACRH_TP3_SHIFT 16
-#define AIPS_PACRH_WP3_MASK 0x20000u
-#define AIPS_PACRH_WP3_SHIFT 17
-#define AIPS_PACRH_SP3_MASK 0x40000u
-#define AIPS_PACRH_SP3_SHIFT 18
-#define AIPS_PACRH_TP2_MASK 0x100000u
-#define AIPS_PACRH_TP2_SHIFT 20
-#define AIPS_PACRH_WP2_MASK 0x200000u
-#define AIPS_PACRH_WP2_SHIFT 21
-#define AIPS_PACRH_SP2_MASK 0x400000u
-#define AIPS_PACRH_SP2_SHIFT 22
-#define AIPS_PACRH_TP1_MASK 0x1000000u
-#define AIPS_PACRH_TP1_SHIFT 24
-#define AIPS_PACRH_WP1_MASK 0x2000000u
-#define AIPS_PACRH_WP1_SHIFT 25
-#define AIPS_PACRH_SP1_MASK 0x4000000u
-#define AIPS_PACRH_SP1_SHIFT 26
-#define AIPS_PACRH_TP0_MASK 0x10000000u
-#define AIPS_PACRH_TP0_SHIFT 28
-#define AIPS_PACRH_WP0_MASK 0x20000000u
-#define AIPS_PACRH_WP0_SHIFT 29
-#define AIPS_PACRH_SP0_MASK 0x40000000u
-#define AIPS_PACRH_SP0_SHIFT 30
-/* PACRI Bit Fields */
-#define AIPS_PACRI_TP7_MASK 0x1u
-#define AIPS_PACRI_TP7_SHIFT 0
-#define AIPS_PACRI_WP7_MASK 0x2u
-#define AIPS_PACRI_WP7_SHIFT 1
-#define AIPS_PACRI_SP7_MASK 0x4u
-#define AIPS_PACRI_SP7_SHIFT 2
-#define AIPS_PACRI_TP6_MASK 0x10u
-#define AIPS_PACRI_TP6_SHIFT 4
-#define AIPS_PACRI_WP6_MASK 0x20u
-#define AIPS_PACRI_WP6_SHIFT 5
-#define AIPS_PACRI_SP6_MASK 0x40u
-#define AIPS_PACRI_SP6_SHIFT 6
-#define AIPS_PACRI_TP5_MASK 0x100u
-#define AIPS_PACRI_TP5_SHIFT 8
-#define AIPS_PACRI_WP5_MASK 0x200u
-#define AIPS_PACRI_WP5_SHIFT 9
-#define AIPS_PACRI_SP5_MASK 0x400u
-#define AIPS_PACRI_SP5_SHIFT 10
-#define AIPS_PACRI_TP4_MASK 0x1000u
-#define AIPS_PACRI_TP4_SHIFT 12
-#define AIPS_PACRI_WP4_MASK 0x2000u
-#define AIPS_PACRI_WP4_SHIFT 13
-#define AIPS_PACRI_SP4_MASK 0x4000u
-#define AIPS_PACRI_SP4_SHIFT 14
-#define AIPS_PACRI_TP3_MASK 0x10000u
-#define AIPS_PACRI_TP3_SHIFT 16
-#define AIPS_PACRI_WP3_MASK 0x20000u
-#define AIPS_PACRI_WP3_SHIFT 17
-#define AIPS_PACRI_SP3_MASK 0x40000u
-#define AIPS_PACRI_SP3_SHIFT 18
-#define AIPS_PACRI_TP2_MASK 0x100000u
-#define AIPS_PACRI_TP2_SHIFT 20
-#define AIPS_PACRI_WP2_MASK 0x200000u
-#define AIPS_PACRI_WP2_SHIFT 21
-#define AIPS_PACRI_SP2_MASK 0x400000u
-#define AIPS_PACRI_SP2_SHIFT 22
-#define AIPS_PACRI_TP1_MASK 0x1000000u
-#define AIPS_PACRI_TP1_SHIFT 24
-#define AIPS_PACRI_WP1_MASK 0x2000000u
-#define AIPS_PACRI_WP1_SHIFT 25
-#define AIPS_PACRI_SP1_MASK 0x4000000u
-#define AIPS_PACRI_SP1_SHIFT 26
-#define AIPS_PACRI_TP0_MASK 0x10000000u
-#define AIPS_PACRI_TP0_SHIFT 28
-#define AIPS_PACRI_WP0_MASK 0x20000000u
-#define AIPS_PACRI_WP0_SHIFT 29
-#define AIPS_PACRI_SP0_MASK 0x40000000u
-#define AIPS_PACRI_SP0_SHIFT 30
-/* PACRJ Bit Fields */
-#define AIPS_PACRJ_TP7_MASK 0x1u
-#define AIPS_PACRJ_TP7_SHIFT 0
-#define AIPS_PACRJ_WP7_MASK 0x2u
-#define AIPS_PACRJ_WP7_SHIFT 1
-#define AIPS_PACRJ_SP7_MASK 0x4u
-#define AIPS_PACRJ_SP7_SHIFT 2
-#define AIPS_PACRJ_TP6_MASK 0x10u
-#define AIPS_PACRJ_TP6_SHIFT 4
-#define AIPS_PACRJ_WP6_MASK 0x20u
-#define AIPS_PACRJ_WP6_SHIFT 5
-#define AIPS_PACRJ_SP6_MASK 0x40u
-#define AIPS_PACRJ_SP6_SHIFT 6
-#define AIPS_PACRJ_TP5_MASK 0x100u
-#define AIPS_PACRJ_TP5_SHIFT 8
-#define AIPS_PACRJ_WP5_MASK 0x200u
-#define AIPS_PACRJ_WP5_SHIFT 9
-#define AIPS_PACRJ_SP5_MASK 0x400u
-#define AIPS_PACRJ_SP5_SHIFT 10
-#define AIPS_PACRJ_TP4_MASK 0x1000u
-#define AIPS_PACRJ_TP4_SHIFT 12
-#define AIPS_PACRJ_WP4_MASK 0x2000u
-#define AIPS_PACRJ_WP4_SHIFT 13
-#define AIPS_PACRJ_SP4_MASK 0x4000u
-#define AIPS_PACRJ_SP4_SHIFT 14
-#define AIPS_PACRJ_TP3_MASK 0x10000u
-#define AIPS_PACRJ_TP3_SHIFT 16
-#define AIPS_PACRJ_WP3_MASK 0x20000u
-#define AIPS_PACRJ_WP3_SHIFT 17
-#define AIPS_PACRJ_SP3_MASK 0x40000u
-#define AIPS_PACRJ_SP3_SHIFT 18
-#define AIPS_PACRJ_TP2_MASK 0x100000u
-#define AIPS_PACRJ_TP2_SHIFT 20
-#define AIPS_PACRJ_WP2_MASK 0x200000u
-#define AIPS_PACRJ_WP2_SHIFT 21
-#define AIPS_PACRJ_SP2_MASK 0x400000u
-#define AIPS_PACRJ_SP2_SHIFT 22
-#define AIPS_PACRJ_TP1_MASK 0x1000000u
-#define AIPS_PACRJ_TP1_SHIFT 24
-#define AIPS_PACRJ_WP1_MASK 0x2000000u
-#define AIPS_PACRJ_WP1_SHIFT 25
-#define AIPS_PACRJ_SP1_MASK 0x4000000u
-#define AIPS_PACRJ_SP1_SHIFT 26
-#define AIPS_PACRJ_TP0_MASK 0x10000000u
-#define AIPS_PACRJ_TP0_SHIFT 28
-#define AIPS_PACRJ_WP0_MASK 0x20000000u
-#define AIPS_PACRJ_WP0_SHIFT 29
-#define AIPS_PACRJ_SP0_MASK 0x40000000u
-#define AIPS_PACRJ_SP0_SHIFT 30
-/* PACRK Bit Fields */
-#define AIPS_PACRK_TP7_MASK 0x1u
-#define AIPS_PACRK_TP7_SHIFT 0
-#define AIPS_PACRK_WP7_MASK 0x2u
-#define AIPS_PACRK_WP7_SHIFT 1
-#define AIPS_PACRK_SP7_MASK 0x4u
-#define AIPS_PACRK_SP7_SHIFT 2
-#define AIPS_PACRK_TP6_MASK 0x10u
-#define AIPS_PACRK_TP6_SHIFT 4
-#define AIPS_PACRK_WP6_MASK 0x20u
-#define AIPS_PACRK_WP6_SHIFT 5
-#define AIPS_PACRK_SP6_MASK 0x40u
-#define AIPS_PACRK_SP6_SHIFT 6
-#define AIPS_PACRK_TP5_MASK 0x100u
-#define AIPS_PACRK_TP5_SHIFT 8
-#define AIPS_PACRK_WP5_MASK 0x200u
-#define AIPS_PACRK_WP5_SHIFT 9
-#define AIPS_PACRK_SP5_MASK 0x400u
-#define AIPS_PACRK_SP5_SHIFT 10
-#define AIPS_PACRK_TP4_MASK 0x1000u
-#define AIPS_PACRK_TP4_SHIFT 12
-#define AIPS_PACRK_WP4_MASK 0x2000u
-#define AIPS_PACRK_WP4_SHIFT 13
-#define AIPS_PACRK_SP4_MASK 0x4000u
-#define AIPS_PACRK_SP4_SHIFT 14
-#define AIPS_PACRK_TP3_MASK 0x10000u
-#define AIPS_PACRK_TP3_SHIFT 16
-#define AIPS_PACRK_WP3_MASK 0x20000u
-#define AIPS_PACRK_WP3_SHIFT 17
-#define AIPS_PACRK_SP3_MASK 0x40000u
-#define AIPS_PACRK_SP3_SHIFT 18
-#define AIPS_PACRK_TP2_MASK 0x100000u
-#define AIPS_PACRK_TP2_SHIFT 20
-#define AIPS_PACRK_WP2_MASK 0x200000u
-#define AIPS_PACRK_WP2_SHIFT 21
-#define AIPS_PACRK_SP2_MASK 0x400000u
-#define AIPS_PACRK_SP2_SHIFT 22
-#define AIPS_PACRK_TP1_MASK 0x1000000u
-#define AIPS_PACRK_TP1_SHIFT 24
-#define AIPS_PACRK_WP1_MASK 0x2000000u
-#define AIPS_PACRK_WP1_SHIFT 25
-#define AIPS_PACRK_SP1_MASK 0x4000000u
-#define AIPS_PACRK_SP1_SHIFT 26
-#define AIPS_PACRK_TP0_MASK 0x10000000u
-#define AIPS_PACRK_TP0_SHIFT 28
-#define AIPS_PACRK_WP0_MASK 0x20000000u
-#define AIPS_PACRK_WP0_SHIFT 29
-#define AIPS_PACRK_SP0_MASK 0x40000000u
-#define AIPS_PACRK_SP0_SHIFT 30
-/* PACRL Bit Fields */
-#define AIPS_PACRL_TP7_MASK 0x1u
-#define AIPS_PACRL_TP7_SHIFT 0
-#define AIPS_PACRL_WP7_MASK 0x2u
-#define AIPS_PACRL_WP7_SHIFT 1
-#define AIPS_PACRL_SP7_MASK 0x4u
-#define AIPS_PACRL_SP7_SHIFT 2
-#define AIPS_PACRL_TP6_MASK 0x10u
-#define AIPS_PACRL_TP6_SHIFT 4
-#define AIPS_PACRL_WP6_MASK 0x20u
-#define AIPS_PACRL_WP6_SHIFT 5
-#define AIPS_PACRL_SP6_MASK 0x40u
-#define AIPS_PACRL_SP6_SHIFT 6
-#define AIPS_PACRL_TP5_MASK 0x100u
-#define AIPS_PACRL_TP5_SHIFT 8
-#define AIPS_PACRL_WP5_MASK 0x200u
-#define AIPS_PACRL_WP5_SHIFT 9
-#define AIPS_PACRL_SP5_MASK 0x400u
-#define AIPS_PACRL_SP5_SHIFT 10
-#define AIPS_PACRL_TP4_MASK 0x1000u
-#define AIPS_PACRL_TP4_SHIFT 12
-#define AIPS_PACRL_WP4_MASK 0x2000u
-#define AIPS_PACRL_WP4_SHIFT 13
-#define AIPS_PACRL_SP4_MASK 0x4000u
-#define AIPS_PACRL_SP4_SHIFT 14
-#define AIPS_PACRL_TP3_MASK 0x10000u
-#define AIPS_PACRL_TP3_SHIFT 16
-#define AIPS_PACRL_WP3_MASK 0x20000u
-#define AIPS_PACRL_WP3_SHIFT 17
-#define AIPS_PACRL_SP3_MASK 0x40000u
-#define AIPS_PACRL_SP3_SHIFT 18
-#define AIPS_PACRL_TP2_MASK 0x100000u
-#define AIPS_PACRL_TP2_SHIFT 20
-#define AIPS_PACRL_WP2_MASK 0x200000u
-#define AIPS_PACRL_WP2_SHIFT 21
-#define AIPS_PACRL_SP2_MASK 0x400000u
-#define AIPS_PACRL_SP2_SHIFT 22
-#define AIPS_PACRL_TP1_MASK 0x1000000u
-#define AIPS_PACRL_TP1_SHIFT 24
-#define AIPS_PACRL_WP1_MASK 0x2000000u
-#define AIPS_PACRL_WP1_SHIFT 25
-#define AIPS_PACRL_SP1_MASK 0x4000000u
-#define AIPS_PACRL_SP1_SHIFT 26
-#define AIPS_PACRL_TP0_MASK 0x10000000u
-#define AIPS_PACRL_TP0_SHIFT 28
-#define AIPS_PACRL_WP0_MASK 0x20000000u
-#define AIPS_PACRL_WP0_SHIFT 29
-#define AIPS_PACRL_SP0_MASK 0x40000000u
-#define AIPS_PACRL_SP0_SHIFT 30
-/* PACRM Bit Fields */
-#define AIPS_PACRM_TP7_MASK 0x1u
-#define AIPS_PACRM_TP7_SHIFT 0
-#define AIPS_PACRM_WP7_MASK 0x2u
-#define AIPS_PACRM_WP7_SHIFT 1
-#define AIPS_PACRM_SP7_MASK 0x4u
-#define AIPS_PACRM_SP7_SHIFT 2
-#define AIPS_PACRM_TP6_MASK 0x10u
-#define AIPS_PACRM_TP6_SHIFT 4
-#define AIPS_PACRM_WP6_MASK 0x20u
-#define AIPS_PACRM_WP6_SHIFT 5
-#define AIPS_PACRM_SP6_MASK 0x40u
-#define AIPS_PACRM_SP6_SHIFT 6
-#define AIPS_PACRM_TP5_MASK 0x100u
-#define AIPS_PACRM_TP5_SHIFT 8
-#define AIPS_PACRM_WP5_MASK 0x200u
-#define AIPS_PACRM_WP5_SHIFT 9
-#define AIPS_PACRM_SP5_MASK 0x400u
-#define AIPS_PACRM_SP5_SHIFT 10
-#define AIPS_PACRM_TP4_MASK 0x1000u
-#define AIPS_PACRM_TP4_SHIFT 12
-#define AIPS_PACRM_WP4_MASK 0x2000u
-#define AIPS_PACRM_WP4_SHIFT 13
-#define AIPS_PACRM_SP4_MASK 0x4000u
-#define AIPS_PACRM_SP4_SHIFT 14
-#define AIPS_PACRM_TP3_MASK 0x10000u
-#define AIPS_PACRM_TP3_SHIFT 16
-#define AIPS_PACRM_WP3_MASK 0x20000u
-#define AIPS_PACRM_WP3_SHIFT 17
-#define AIPS_PACRM_SP3_MASK 0x40000u
-#define AIPS_PACRM_SP3_SHIFT 18
-#define AIPS_PACRM_TP2_MASK 0x100000u
-#define AIPS_PACRM_TP2_SHIFT 20
-#define AIPS_PACRM_WP2_MASK 0x200000u
-#define AIPS_PACRM_WP2_SHIFT 21
-#define AIPS_PACRM_SP2_MASK 0x400000u
-#define AIPS_PACRM_SP2_SHIFT 22
-#define AIPS_PACRM_TP1_MASK 0x1000000u
-#define AIPS_PACRM_TP1_SHIFT 24
-#define AIPS_PACRM_WP1_MASK 0x2000000u
-#define AIPS_PACRM_WP1_SHIFT 25
-#define AIPS_PACRM_SP1_MASK 0x4000000u
-#define AIPS_PACRM_SP1_SHIFT 26
-#define AIPS_PACRM_TP0_MASK 0x10000000u
-#define AIPS_PACRM_TP0_SHIFT 28
-#define AIPS_PACRM_WP0_MASK 0x20000000u
-#define AIPS_PACRM_WP0_SHIFT 29
-#define AIPS_PACRM_SP0_MASK 0x40000000u
-#define AIPS_PACRM_SP0_SHIFT 30
-/* PACRN Bit Fields */
-#define AIPS_PACRN_TP7_MASK 0x1u
-#define AIPS_PACRN_TP7_SHIFT 0
-#define AIPS_PACRN_WP7_MASK 0x2u
-#define AIPS_PACRN_WP7_SHIFT 1
-#define AIPS_PACRN_SP7_MASK 0x4u
-#define AIPS_PACRN_SP7_SHIFT 2
-#define AIPS_PACRN_TP6_MASK 0x10u
-#define AIPS_PACRN_TP6_SHIFT 4
-#define AIPS_PACRN_WP6_MASK 0x20u
-#define AIPS_PACRN_WP6_SHIFT 5
-#define AIPS_PACRN_SP6_MASK 0x40u
-#define AIPS_PACRN_SP6_SHIFT 6
-#define AIPS_PACRN_TP5_MASK 0x100u
-#define AIPS_PACRN_TP5_SHIFT 8
-#define AIPS_PACRN_WP5_MASK 0x200u
-#define AIPS_PACRN_WP5_SHIFT 9
-#define AIPS_PACRN_SP5_MASK 0x400u
-#define AIPS_PACRN_SP5_SHIFT 10
-#define AIPS_PACRN_TP4_MASK 0x1000u
-#define AIPS_PACRN_TP4_SHIFT 12
-#define AIPS_PACRN_WP4_MASK 0x2000u
-#define AIPS_PACRN_WP4_SHIFT 13
-#define AIPS_PACRN_SP4_MASK 0x4000u
-#define AIPS_PACRN_SP4_SHIFT 14
-#define AIPS_PACRN_TP3_MASK 0x10000u
-#define AIPS_PACRN_TP3_SHIFT 16
-#define AIPS_PACRN_WP3_MASK 0x20000u
-#define AIPS_PACRN_WP3_SHIFT 17
-#define AIPS_PACRN_SP3_MASK 0x40000u
-#define AIPS_PACRN_SP3_SHIFT 18
-#define AIPS_PACRN_TP2_MASK 0x100000u
-#define AIPS_PACRN_TP2_SHIFT 20
-#define AIPS_PACRN_WP2_MASK 0x200000u
-#define AIPS_PACRN_WP2_SHIFT 21
-#define AIPS_PACRN_SP2_MASK 0x400000u
-#define AIPS_PACRN_SP2_SHIFT 22
-#define AIPS_PACRN_TP1_MASK 0x1000000u
-#define AIPS_PACRN_TP1_SHIFT 24
-#define AIPS_PACRN_WP1_MASK 0x2000000u
-#define AIPS_PACRN_WP1_SHIFT 25
-#define AIPS_PACRN_SP1_MASK 0x4000000u
-#define AIPS_PACRN_SP1_SHIFT 26
-#define AIPS_PACRN_TP0_MASK 0x10000000u
-#define AIPS_PACRN_TP0_SHIFT 28
-#define AIPS_PACRN_WP0_MASK 0x20000000u
-#define AIPS_PACRN_WP0_SHIFT 29
-#define AIPS_PACRN_SP0_MASK 0x40000000u
-#define AIPS_PACRN_SP0_SHIFT 30
-/* PACRO Bit Fields */
-#define AIPS_PACRO_TP7_MASK 0x1u
-#define AIPS_PACRO_TP7_SHIFT 0
-#define AIPS_PACRO_WP7_MASK 0x2u
-#define AIPS_PACRO_WP7_SHIFT 1
-#define AIPS_PACRO_SP7_MASK 0x4u
-#define AIPS_PACRO_SP7_SHIFT 2
-#define AIPS_PACRO_TP6_MASK 0x10u
-#define AIPS_PACRO_TP6_SHIFT 4
-#define AIPS_PACRO_WP6_MASK 0x20u
-#define AIPS_PACRO_WP6_SHIFT 5
-#define AIPS_PACRO_SP6_MASK 0x40u
-#define AIPS_PACRO_SP6_SHIFT 6
-#define AIPS_PACRO_TP5_MASK 0x100u
-#define AIPS_PACRO_TP5_SHIFT 8
-#define AIPS_PACRO_WP5_MASK 0x200u
-#define AIPS_PACRO_WP5_SHIFT 9
-#define AIPS_PACRO_SP5_MASK 0x400u
-#define AIPS_PACRO_SP5_SHIFT 10
-#define AIPS_PACRO_TP4_MASK 0x1000u
-#define AIPS_PACRO_TP4_SHIFT 12
-#define AIPS_PACRO_WP4_MASK 0x2000u
-#define AIPS_PACRO_WP4_SHIFT 13
-#define AIPS_PACRO_SP4_MASK 0x4000u
-#define AIPS_PACRO_SP4_SHIFT 14
-#define AIPS_PACRO_TP3_MASK 0x10000u
-#define AIPS_PACRO_TP3_SHIFT 16
-#define AIPS_PACRO_WP3_MASK 0x20000u
-#define AIPS_PACRO_WP3_SHIFT 17
-#define AIPS_PACRO_SP3_MASK 0x40000u
-#define AIPS_PACRO_SP3_SHIFT 18
-#define AIPS_PACRO_TP2_MASK 0x100000u
-#define AIPS_PACRO_TP2_SHIFT 20
-#define AIPS_PACRO_WP2_MASK 0x200000u
-#define AIPS_PACRO_WP2_SHIFT 21
-#define AIPS_PACRO_SP2_MASK 0x400000u
-#define AIPS_PACRO_SP2_SHIFT 22
-#define AIPS_PACRO_TP1_MASK 0x1000000u
-#define AIPS_PACRO_TP1_SHIFT 24
-#define AIPS_PACRO_WP1_MASK 0x2000000u
-#define AIPS_PACRO_WP1_SHIFT 25
-#define AIPS_PACRO_SP1_MASK 0x4000000u
-#define AIPS_PACRO_SP1_SHIFT 26
-#define AIPS_PACRO_TP0_MASK 0x10000000u
-#define AIPS_PACRO_TP0_SHIFT 28
-#define AIPS_PACRO_WP0_MASK 0x20000000u
-#define AIPS_PACRO_WP0_SHIFT 29
-#define AIPS_PACRO_SP0_MASK 0x40000000u
-#define AIPS_PACRO_SP0_SHIFT 30
-/* PACRP Bit Fields */
-#define AIPS_PACRP_TP7_MASK 0x1u
-#define AIPS_PACRP_TP7_SHIFT 0
-#define AIPS_PACRP_WP7_MASK 0x2u
-#define AIPS_PACRP_WP7_SHIFT 1
-#define AIPS_PACRP_SP7_MASK 0x4u
-#define AIPS_PACRP_SP7_SHIFT 2
-#define AIPS_PACRP_TP6_MASK 0x10u
-#define AIPS_PACRP_TP6_SHIFT 4
-#define AIPS_PACRP_WP6_MASK 0x20u
-#define AIPS_PACRP_WP6_SHIFT 5
-#define AIPS_PACRP_SP6_MASK 0x40u
-#define AIPS_PACRP_SP6_SHIFT 6
-#define AIPS_PACRP_TP5_MASK 0x100u
-#define AIPS_PACRP_TP5_SHIFT 8
-#define AIPS_PACRP_WP5_MASK 0x200u
-#define AIPS_PACRP_WP5_SHIFT 9
-#define AIPS_PACRP_SP5_MASK 0x400u
-#define AIPS_PACRP_SP5_SHIFT 10
-#define AIPS_PACRP_TP4_MASK 0x1000u
-#define AIPS_PACRP_TP4_SHIFT 12
-#define AIPS_PACRP_WP4_MASK 0x2000u
-#define AIPS_PACRP_WP4_SHIFT 13
-#define AIPS_PACRP_SP4_MASK 0x4000u
-#define AIPS_PACRP_SP4_SHIFT 14
-#define AIPS_PACRP_TP3_MASK 0x10000u
-#define AIPS_PACRP_TP3_SHIFT 16
-#define AIPS_PACRP_WP3_MASK 0x20000u
-#define AIPS_PACRP_WP3_SHIFT 17
-#define AIPS_PACRP_SP3_MASK 0x40000u
-#define AIPS_PACRP_SP3_SHIFT 18
-#define AIPS_PACRP_TP2_MASK 0x100000u
-#define AIPS_PACRP_TP2_SHIFT 20
-#define AIPS_PACRP_WP2_MASK 0x200000u
-#define AIPS_PACRP_WP2_SHIFT 21
-#define AIPS_PACRP_SP2_MASK 0x400000u
-#define AIPS_PACRP_SP2_SHIFT 22
-#define AIPS_PACRP_TP1_MASK 0x1000000u
-#define AIPS_PACRP_TP1_SHIFT 24
-#define AIPS_PACRP_WP1_MASK 0x2000000u
-#define AIPS_PACRP_WP1_SHIFT 25
-#define AIPS_PACRP_SP1_MASK 0x4000000u
-#define AIPS_PACRP_SP1_SHIFT 26
-#define AIPS_PACRP_TP0_MASK 0x10000000u
-#define AIPS_PACRP_TP0_SHIFT 28
-#define AIPS_PACRP_WP0_MASK 0x20000000u
-#define AIPS_PACRP_WP0_SHIFT 29
-#define AIPS_PACRP_SP0_MASK 0x40000000u
-#define AIPS_PACRP_SP0_SHIFT 30
-/* PACRU Bit Fields */
-#define AIPS_PACRU_TP1_MASK 0x1000000u
-#define AIPS_PACRU_TP1_SHIFT 24
-#define AIPS_PACRU_WP1_MASK 0x2000000u
-#define AIPS_PACRU_WP1_SHIFT 25
-#define AIPS_PACRU_SP1_MASK 0x4000000u
-#define AIPS_PACRU_SP1_SHIFT 26
-#define AIPS_PACRU_TP0_MASK 0x10000000u
-#define AIPS_PACRU_TP0_SHIFT 28
-#define AIPS_PACRU_WP0_MASK 0x20000000u
-#define AIPS_PACRU_WP0_SHIFT 29
-#define AIPS_PACRU_SP0_MASK 0x40000000u
-#define AIPS_PACRU_SP0_SHIFT 30
-
-/*!
- * @}
- */ /* end of group AIPS_Register_Masks */
-
-
-/* AIPS - Peripheral instance base addresses */
-/** Peripheral AIPS0 base address */
-#define AIPS0_BASE (0x40000000u)
-/** Peripheral AIPS0 base pointer */
-#define AIPS0 ((AIPS_Type *)AIPS0_BASE)
-#define AIPS0_BASE_PTR (AIPS0)
-/** Peripheral AIPS1 base address */
-#define AIPS1_BASE (0x40080000u)
-/** Peripheral AIPS1 base pointer */
-#define AIPS1 ((AIPS_Type *)AIPS1_BASE)
-#define AIPS1_BASE_PTR (AIPS1)
-/** Array initializer of AIPS peripheral base pointers */
-#define AIPS_BASES { AIPS0, AIPS1 }
-
-/* ----------------------------------------------------------------------------
- -- AIPS - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
- * @{
- */
-
-
-/* AIPS - Register instance definitions */
-/* AIPS0 */
-#define AIPS0_MPRA AIPS_MPRA_REG(AIPS0)
-#define AIPS0_PACRA AIPS_PACRA_REG(AIPS0)
-#define AIPS0_PACRB AIPS_PACRB_REG(AIPS0)
-#define AIPS0_PACRC AIPS_PACRC_REG(AIPS0)
-#define AIPS0_PACRD AIPS_PACRD_REG(AIPS0)
-#define AIPS0_PACRE AIPS_PACRE_REG(AIPS0)
-#define AIPS0_PACRF AIPS_PACRF_REG(AIPS0)
-#define AIPS0_PACRG AIPS_PACRG_REG(AIPS0)
-#define AIPS0_PACRH AIPS_PACRH_REG(AIPS0)
-#define AIPS0_PACRI AIPS_PACRI_REG(AIPS0)
-#define AIPS0_PACRJ AIPS_PACRJ_REG(AIPS0)
-#define AIPS0_PACRK AIPS_PACRK_REG(AIPS0)
-#define AIPS0_PACRL AIPS_PACRL_REG(AIPS0)
-#define AIPS0_PACRM AIPS_PACRM_REG(AIPS0)
-#define AIPS0_PACRN AIPS_PACRN_REG(AIPS0)
-#define AIPS0_PACRO AIPS_PACRO_REG(AIPS0)
-#define AIPS0_PACRP AIPS_PACRP_REG(AIPS0)
-#define AIPS0_PACRU AIPS_PACRU_REG(AIPS0)
-/* AIPS1 */
-#define AIPS1_MPRA AIPS_MPRA_REG(AIPS1)
-#define AIPS1_PACRA AIPS_PACRA_REG(AIPS1)
-#define AIPS1_PACRB AIPS_PACRB_REG(AIPS1)
-#define AIPS1_PACRC AIPS_PACRC_REG(AIPS1)
-#define AIPS1_PACRD AIPS_PACRD_REG(AIPS1)
-#define AIPS1_PACRE AIPS_PACRE_REG(AIPS1)
-#define AIPS1_PACRF AIPS_PACRF_REG(AIPS1)
-#define AIPS1_PACRG AIPS_PACRG_REG(AIPS1)
-#define AIPS1_PACRH AIPS_PACRH_REG(AIPS1)
-#define AIPS1_PACRI AIPS_PACRI_REG(AIPS1)
-#define AIPS1_PACRJ AIPS_PACRJ_REG(AIPS1)
-#define AIPS1_PACRK AIPS_PACRK_REG(AIPS1)
-#define AIPS1_PACRL AIPS_PACRL_REG(AIPS1)
-#define AIPS1_PACRM AIPS_PACRM_REG(AIPS1)
-#define AIPS1_PACRN AIPS_PACRN_REG(AIPS1)
-#define AIPS1_PACRO AIPS_PACRO_REG(AIPS1)
-#define AIPS1_PACRP AIPS_PACRP_REG(AIPS1)
-#define AIPS1_PACRU AIPS_PACRU_REG(AIPS1)
-
-/*!
- * @}
- */ /* end of group AIPS_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group AIPS_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- AXBS Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
- * @{
- */
-
-/** AXBS - Register Layout Typedef */
-typedef struct {
- struct { /* offset: 0x0, array step: 0x100 */
- __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
- uint8_t RESERVED_0[12];
- __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
- uint8_t RESERVED_1[236];
- } SLAVE[5];
- uint8_t RESERVED_0[768];
- __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
- uint8_t RESERVED_1[252];
- __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
- uint8_t RESERVED_2[252];
- __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
- uint8_t RESERVED_3[252];
- __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */
- uint8_t RESERVED_4[252];
- __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
- uint8_t RESERVED_5[252];
- __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */
-} AXBS_Type, *AXBS_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- AXBS - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
- * @{
- */
-
-
-/* AXBS - Register accessors */
-#define AXBS_PRS_REG(base,index) ((base)->SLAVE[index].PRS)
-#define AXBS_CRS_REG(base,index) ((base)->SLAVE[index].CRS)
-#define AXBS_MGPCR0_REG(base) ((base)->MGPCR0)
-#define AXBS_MGPCR1_REG(base) ((base)->MGPCR1)
-#define AXBS_MGPCR2_REG(base) ((base)->MGPCR2)
-#define AXBS_MGPCR3_REG(base) ((base)->MGPCR3)
-#define AXBS_MGPCR4_REG(base) ((base)->MGPCR4)
-#define AXBS_MGPCR5_REG(base) ((base)->MGPCR5)
-
-/*!
- * @}
- */ /* end of group AXBS_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- AXBS Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup AXBS_Register_Masks AXBS Register Masks
- * @{
- */
-
-/* PRS Bit Fields */
-#define AXBS_PRS_M0_MASK 0x7u
-#define AXBS_PRS_M0_SHIFT 0
-#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK)
-#define AXBS_PRS_M1_MASK 0x70u
-#define AXBS_PRS_M1_SHIFT 4
-#define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK)
-#define AXBS_PRS_M2_MASK 0x700u
-#define AXBS_PRS_M2_SHIFT 8
-#define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK)
-#define AXBS_PRS_M3_MASK 0x7000u
-#define AXBS_PRS_M3_SHIFT 12
-#define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M3_SHIFT))&AXBS_PRS_M3_MASK)
-#define AXBS_PRS_M4_MASK 0x70000u
-#define AXBS_PRS_M4_SHIFT 16
-#define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK)
-#define AXBS_PRS_M5_MASK 0x700000u
-#define AXBS_PRS_M5_SHIFT 20
-#define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK)
-/* CRS Bit Fields */
-#define AXBS_CRS_PARK_MASK 0x7u
-#define AXBS_CRS_PARK_SHIFT 0
-#define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK)
-#define AXBS_CRS_PCTL_MASK 0x30u
-#define AXBS_CRS_PCTL_SHIFT 4
-#define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK)
-#define AXBS_CRS_ARB_MASK 0x300u
-#define AXBS_CRS_ARB_SHIFT 8
-#define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK)
-#define AXBS_CRS_HLP_MASK 0x40000000u
-#define AXBS_CRS_HLP_SHIFT 30
-#define AXBS_CRS_RO_MASK 0x80000000u
-#define AXBS_CRS_RO_SHIFT 31
-/* MGPCR0 Bit Fields */
-#define AXBS_MGPCR0_AULB_MASK 0x7u
-#define AXBS_MGPCR0_AULB_SHIFT 0
-#define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK)
-/* MGPCR1 Bit Fields */
-#define AXBS_MGPCR1_AULB_MASK 0x7u
-#define AXBS_MGPCR1_AULB_SHIFT 0
-#define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK)
-/* MGPCR2 Bit Fields */
-#define AXBS_MGPCR2_AULB_MASK 0x7u
-#define AXBS_MGPCR2_AULB_SHIFT 0
-#define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK)
-/* MGPCR3 Bit Fields */
-#define AXBS_MGPCR3_AULB_MASK 0x7u
-#define AXBS_MGPCR3_AULB_SHIFT 0
-#define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR3_AULB_SHIFT))&AXBS_MGPCR3_AULB_MASK)
-/* MGPCR4 Bit Fields */
-#define AXBS_MGPCR4_AULB_MASK 0x7u
-#define AXBS_MGPCR4_AULB_SHIFT 0
-#define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR4_AULB_SHIFT))&AXBS_MGPCR4_AULB_MASK)
-/* MGPCR5 Bit Fields */
-#define AXBS_MGPCR5_AULB_MASK 0x7u
-#define AXBS_MGPCR5_AULB_SHIFT 0
-#define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR5_AULB_SHIFT))&AXBS_MGPCR5_AULB_MASK)
-
-/*!
- * @}
- */ /* end of group AXBS_Register_Masks */
-
-
-/* AXBS - Peripheral instance base addresses */
-/** Peripheral AXBS base address */
-#define AXBS_BASE (0x40004000u)
-/** Peripheral AXBS base pointer */
-#define AXBS ((AXBS_Type *)AXBS_BASE)
-#define AXBS_BASE_PTR (AXBS)
-/** Array initializer of AXBS peripheral base pointers */
-#define AXBS_BASES { AXBS }
-
-/* ----------------------------------------------------------------------------
- -- AXBS - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
- * @{
- */
-
-
-/* AXBS - Register instance definitions */
-/* AXBS */
-#define AXBS_PRS0 AXBS_PRS_REG(AXBS,0)
-#define AXBS_CRS0 AXBS_CRS_REG(AXBS,0)
-#define AXBS_PRS1 AXBS_PRS_REG(AXBS,1)
-#define AXBS_CRS1 AXBS_CRS_REG(AXBS,1)
-#define AXBS_PRS2 AXBS_PRS_REG(AXBS,2)
-#define AXBS_CRS2 AXBS_CRS_REG(AXBS,2)
-#define AXBS_PRS3 AXBS_PRS_REG(AXBS,3)
-#define AXBS_CRS3 AXBS_CRS_REG(AXBS,3)
-#define AXBS_PRS4 AXBS_PRS_REG(AXBS,4)
-#define AXBS_CRS4 AXBS_CRS_REG(AXBS,4)
-#define AXBS_MGPCR0 AXBS_MGPCR0_REG(AXBS)
-#define AXBS_MGPCR1 AXBS_MGPCR1_REG(AXBS)
-#define AXBS_MGPCR2 AXBS_MGPCR2_REG(AXBS)
-#define AXBS_MGPCR3 AXBS_MGPCR3_REG(AXBS)
-#define AXBS_MGPCR4 AXBS_MGPCR4_REG(AXBS)
-#define AXBS_MGPCR5 AXBS_MGPCR5_REG(AXBS)
-
-/* AXBS - Register array accessors */
-#define AXBS_PRS(index) AXBS_PRS_REG(AXBS,index)
-#define AXBS_CRS(index) AXBS_CRS_REG(AXBS,index)
-
-/*!
- * @}
- */ /* end of group AXBS_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group AXBS_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- CAN Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
- * @{
- */
-
-/** CAN - Register Layout Typedef */
-typedef struct {
- __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
- __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */
- __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
- uint8_t RESERVED_0[4];
- __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
- __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */
- __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */
- __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
- __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */
- uint8_t RESERVED_1[4];
- __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */
- uint8_t RESERVED_2[4];
- __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */
- __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */
- __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */
- uint8_t RESERVED_3[8];
- __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
- __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */
- __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
- uint8_t RESERVED_4[48];
- struct { /* offset: 0x80, array step: 0x10 */
- __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
- __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
- __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
- __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
- } MB[16];
- uint8_t RESERVED_5[1792];
- __IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
-} CAN_Type, *CAN_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- CAN - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
- * @{
- */
-
-
-/* CAN - Register accessors */
-#define CAN_MCR_REG(base) ((base)->MCR)
-#define CAN_CTRL1_REG(base) ((base)->CTRL1)
-#define CAN_TIMER_REG(base) ((base)->TIMER)
-#define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK)
-#define CAN_RX14MASK_REG(base) ((base)->RX14MASK)
-#define CAN_RX15MASK_REG(base) ((base)->RX15MASK)
-#define CAN_ECR_REG(base) ((base)->ECR)
-#define CAN_ESR1_REG(base) ((base)->ESR1)
-#define CAN_IMASK1_REG(base) ((base)->IMASK1)
-#define CAN_IFLAG1_REG(base) ((base)->IFLAG1)
-#define CAN_CTRL2_REG(base) ((base)->CTRL2)
-#define CAN_ESR2_REG(base) ((base)->ESR2)
-#define CAN_CRCR_REG(base) ((base)->CRCR)
-#define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK)
-#define CAN_RXFIR_REG(base) ((base)->RXFIR)
-#define CAN_CS_REG(base,index) ((base)->MB[index].CS)
-#define CAN_ID_REG(base,index) ((base)->MB[index].ID)
-#define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0)
-#define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1)
-#define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index])
-
-/*!
- * @}
- */ /* end of group CAN_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- CAN Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CAN_Register_Masks CAN Register Masks
- * @{
- */
-
-/* MCR Bit Fields */
-#define CAN_MCR_MAXMB_MASK 0x7Fu
-#define CAN_MCR_MAXMB_SHIFT 0
-#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
-#define CAN_MCR_IDAM_MASK 0x300u
-#define CAN_MCR_IDAM_SHIFT 8
-#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
-#define CAN_MCR_AEN_MASK 0x1000u
-#define CAN_MCR_AEN_SHIFT 12
-#define CAN_MCR_LPRIOEN_MASK 0x2000u
-#define CAN_MCR_LPRIOEN_SHIFT 13
-#define CAN_MCR_IRMQ_MASK 0x10000u
-#define CAN_MCR_IRMQ_SHIFT 16
-#define CAN_MCR_SRXDIS_MASK 0x20000u
-#define CAN_MCR_SRXDIS_SHIFT 17
-#define CAN_MCR_WAKSRC_MASK 0x80000u
-#define CAN_MCR_WAKSRC_SHIFT 19
-#define CAN_MCR_LPMACK_MASK 0x100000u
-#define CAN_MCR_LPMACK_SHIFT 20
-#define CAN_MCR_WRNEN_MASK 0x200000u
-#define CAN_MCR_WRNEN_SHIFT 21
-#define CAN_MCR_SLFWAK_MASK 0x400000u
-#define CAN_MCR_SLFWAK_SHIFT 22
-#define CAN_MCR_SUPV_MASK 0x800000u
-#define CAN_MCR_SUPV_SHIFT 23
-#define CAN_MCR_FRZACK_MASK 0x1000000u
-#define CAN_MCR_FRZACK_SHIFT 24
-#define CAN_MCR_SOFTRST_MASK 0x2000000u
-#define CAN_MCR_SOFTRST_SHIFT 25
-#define CAN_MCR_WAKMSK_MASK 0x4000000u
-#define CAN_MCR_WAKMSK_SHIFT 26
-#define CAN_MCR_NOTRDY_MASK 0x8000000u
-#define CAN_MCR_NOTRDY_SHIFT 27
-#define CAN_MCR_HALT_MASK 0x10000000u
-#define CAN_MCR_HALT_SHIFT 28
-#define CAN_MCR_RFEN_MASK 0x20000000u
-#define CAN_MCR_RFEN_SHIFT 29
-#define CAN_MCR_FRZ_MASK 0x40000000u
-#define CAN_MCR_FRZ_SHIFT 30
-#define CAN_MCR_MDIS_MASK 0x80000000u
-#define CAN_MCR_MDIS_SHIFT 31
-/* CTRL1 Bit Fields */
-#define CAN_CTRL1_PROPSEG_MASK 0x7u
-#define CAN_CTRL1_PROPSEG_SHIFT 0
-#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
-#define CAN_CTRL1_LOM_MASK 0x8u
-#define CAN_CTRL1_LOM_SHIFT 3
-#define CAN_CTRL1_LBUF_MASK 0x10u
-#define CAN_CTRL1_LBUF_SHIFT 4
-#define CAN_CTRL1_TSYN_MASK 0x20u
-#define CAN_CTRL1_TSYN_SHIFT 5
-#define CAN_CTRL1_BOFFREC_MASK 0x40u
-#define CAN_CTRL1_BOFFREC_SHIFT 6
-#define CAN_CTRL1_SMP_MASK 0x80u
-#define CAN_CTRL1_SMP_SHIFT 7
-#define CAN_CTRL1_RWRNMSK_MASK 0x400u
-#define CAN_CTRL1_RWRNMSK_SHIFT 10
-#define CAN_CTRL1_TWRNMSK_MASK 0x800u
-#define CAN_CTRL1_TWRNMSK_SHIFT 11
-#define CAN_CTRL1_LPB_MASK 0x1000u
-#define CAN_CTRL1_LPB_SHIFT 12
-#define CAN_CTRL1_CLKSRC_MASK 0x2000u
-#define CAN_CTRL1_CLKSRC_SHIFT 13
-#define CAN_CTRL1_ERRMSK_MASK 0x4000u
-#define CAN_CTRL1_ERRMSK_SHIFT 14
-#define CAN_CTRL1_BOFFMSK_MASK 0x8000u
-#define CAN_CTRL1_BOFFMSK_SHIFT 15
-#define CAN_CTRL1_PSEG2_MASK 0x70000u
-#define CAN_CTRL1_PSEG2_SHIFT 16
-#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
-#define CAN_CTRL1_PSEG1_MASK 0x380000u
-#define CAN_CTRL1_PSEG1_SHIFT 19
-#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
-#define CAN_CTRL1_RJW_MASK 0xC00000u
-#define CAN_CTRL1_RJW_SHIFT 22
-#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
-#define CAN_CTRL1_PRESDIV_MASK 0xFF000000u
-#define CAN_CTRL1_PRESDIV_SHIFT 24
-#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
-/* TIMER Bit Fields */
-#define CAN_TIMER_TIMER_MASK 0xFFFFu
-#define CAN_TIMER_TIMER_SHIFT 0
-#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
-/* RXMGMASK Bit Fields */
-#define CAN_RXMGMASK_MG_MASK 0xFFFFFFFFu
-#define CAN_RXMGMASK_MG_SHIFT 0
-#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
-/* RX14MASK Bit Fields */
-#define CAN_RX14MASK_RX14M_MASK 0xFFFFFFFFu
-#define CAN_RX14MASK_RX14M_SHIFT 0
-#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
-/* RX15MASK Bit Fields */
-#define CAN_RX15MASK_RX15M_MASK 0xFFFFFFFFu
-#define CAN_RX15MASK_RX15M_SHIFT 0
-#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
-/* ECR Bit Fields */
-#define CAN_ECR_TXERRCNT_MASK 0xFFu
-#define CAN_ECR_TXERRCNT_SHIFT 0
-#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
-#define CAN_ECR_RXERRCNT_MASK 0xFF00u
-#define CAN_ECR_RXERRCNT_SHIFT 8
-#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
-/* ESR1 Bit Fields */
-#define CAN_ESR1_WAKINT_MASK 0x1u
-#define CAN_ESR1_WAKINT_SHIFT 0
-#define CAN_ESR1_ERRINT_MASK 0x2u
-#define CAN_ESR1_ERRINT_SHIFT 1
-#define CAN_ESR1_BOFFINT_MASK 0x4u
-#define CAN_ESR1_BOFFINT_SHIFT 2
-#define CAN_ESR1_RX_MASK 0x8u
-#define CAN_ESR1_RX_SHIFT 3
-#define CAN_ESR1_FLTCONF_MASK 0x30u
-#define CAN_ESR1_FLTCONF_SHIFT 4
-#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
-#define CAN_ESR1_TX_MASK 0x40u
-#define CAN_ESR1_TX_SHIFT 6
-#define CAN_ESR1_IDLE_MASK 0x80u
-#define CAN_ESR1_IDLE_SHIFT 7
-#define CAN_ESR1_RXWRN_MASK 0x100u
-#define CAN_ESR1_RXWRN_SHIFT 8
-#define CAN_ESR1_TXWRN_MASK 0x200u
-#define CAN_ESR1_TXWRN_SHIFT 9
-#define CAN_ESR1_STFERR_MASK 0x400u
-#define CAN_ESR1_STFERR_SHIFT 10
-#define CAN_ESR1_FRMERR_MASK 0x800u
-#define CAN_ESR1_FRMERR_SHIFT 11
-#define CAN_ESR1_CRCERR_MASK 0x1000u
-#define CAN_ESR1_CRCERR_SHIFT 12
-#define CAN_ESR1_ACKERR_MASK 0x2000u
-#define CAN_ESR1_ACKERR_SHIFT 13
-#define CAN_ESR1_BIT0ERR_MASK 0x4000u
-#define CAN_ESR1_BIT0ERR_SHIFT 14
-#define CAN_ESR1_BIT1ERR_MASK 0x8000u
-#define CAN_ESR1_BIT1ERR_SHIFT 15
-#define CAN_ESR1_RWRNINT_MASK 0x10000u
-#define CAN_ESR1_RWRNINT_SHIFT 16
-#define CAN_ESR1_TWRNINT_MASK 0x20000u
-#define CAN_ESR1_TWRNINT_SHIFT 17
-#define CAN_ESR1_SYNCH_MASK 0x40000u
-#define CAN_ESR1_SYNCH_SHIFT 18
-/* IMASK1 Bit Fields */
-#define CAN_IMASK1_BUFLM_MASK 0xFFFFFFFFu
-#define CAN_IMASK1_BUFLM_SHIFT 0
-#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)
-/* IFLAG1 Bit Fields */
-#define CAN_IFLAG1_BUF0I_MASK 0x1u
-#define CAN_IFLAG1_BUF0I_SHIFT 0
-#define CAN_IFLAG1_BUF4TO1I_MASK 0x1Eu
-#define CAN_IFLAG1_BUF4TO1I_SHIFT 1
-#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO1I_SHIFT))&CAN_IFLAG1_BUF4TO1I_MASK)
-#define CAN_IFLAG1_BUF5I_MASK 0x20u
-#define CAN_IFLAG1_BUF5I_SHIFT 5
-#define CAN_IFLAG1_BUF6I_MASK 0x40u
-#define CAN_IFLAG1_BUF6I_SHIFT 6
-#define CAN_IFLAG1_BUF7I_MASK 0x80u
-#define CAN_IFLAG1_BUF7I_SHIFT 7
-#define CAN_IFLAG1_BUF31TO8I_MASK 0xFFFFFF00u
-#define CAN_IFLAG1_BUF31TO8I_SHIFT 8
-#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
-/* CTRL2 Bit Fields */
-#define CAN_CTRL2_EACEN_MASK 0x10000u
-#define CAN_CTRL2_EACEN_SHIFT 16
-#define CAN_CTRL2_RRS_MASK 0x20000u
-#define CAN_CTRL2_RRS_SHIFT 17
-#define CAN_CTRL2_MRP_MASK 0x40000u
-#define CAN_CTRL2_MRP_SHIFT 18
-#define CAN_CTRL2_TASD_MASK 0xF80000u
-#define CAN_CTRL2_TASD_SHIFT 19
-#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
-#define CAN_CTRL2_RFFN_MASK 0xF000000u
-#define CAN_CTRL2_RFFN_SHIFT 24
-#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
-#define CAN_CTRL2_WRMFRZ_MASK 0x10000000u
-#define CAN_CTRL2_WRMFRZ_SHIFT 28
-/* ESR2 Bit Fields */
-#define CAN_ESR2_IMB_MASK 0x2000u
-#define CAN_ESR2_IMB_SHIFT 13
-#define CAN_ESR2_VPS_MASK 0x4000u
-#define CAN_ESR2_VPS_SHIFT 14
-#define CAN_ESR2_LPTM_MASK 0x7F0000u
-#define CAN_ESR2_LPTM_SHIFT 16
-#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
-/* CRCR Bit Fields */
-#define CAN_CRCR_TXCRC_MASK 0x7FFFu
-#define CAN_CRCR_TXCRC_SHIFT 0
-#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
-#define CAN_CRCR_MBCRC_MASK 0x7F0000u
-#define CAN_CRCR_MBCRC_SHIFT 16
-#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
-/* RXFGMASK Bit Fields */
-#define CAN_RXFGMASK_FGM_MASK 0xFFFFFFFFu
-#define CAN_RXFGMASK_FGM_SHIFT 0
-#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
-/* RXFIR Bit Fields */
-#define CAN_RXFIR_IDHIT_MASK 0x1FFu
-#define CAN_RXFIR_IDHIT_SHIFT 0
-#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
-/* CS Bit Fields */
-#define CAN_CS_TIME_STAMP_MASK 0xFFFFu
-#define CAN_CS_TIME_STAMP_SHIFT 0
-#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
-#define CAN_CS_DLC_MASK 0xF0000u
-#define CAN_CS_DLC_SHIFT 16
-#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
-#define CAN_CS_RTR_MASK 0x100000u
-#define CAN_CS_RTR_SHIFT 20
-#define CAN_CS_IDE_MASK 0x200000u
-#define CAN_CS_IDE_SHIFT 21
-#define CAN_CS_SRR_MASK 0x400000u
-#define CAN_CS_SRR_SHIFT 22
-#define CAN_CS_CODE_MASK 0xF000000u
-#define CAN_CS_CODE_SHIFT 24
-#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
-/* ID Bit Fields */
-#define CAN_ID_EXT_MASK 0x3FFFFu
-#define CAN_ID_EXT_SHIFT 0
-#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
-#define CAN_ID_STD_MASK 0x1FFC0000u
-#define CAN_ID_STD_SHIFT 18
-#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
-#define CAN_ID_PRIO_MASK 0xE0000000u
-#define CAN_ID_PRIO_SHIFT 29
-#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
-/* WORD0 Bit Fields */
-#define CAN_WORD0_DATA_BYTE_3_MASK 0xFFu
-#define CAN_WORD0_DATA_BYTE_3_SHIFT 0
-#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
-#define CAN_WORD0_DATA_BYTE_2_MASK 0xFF00u
-#define CAN_WORD0_DATA_BYTE_2_SHIFT 8
-#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
-#define CAN_WORD0_DATA_BYTE_1_MASK 0xFF0000u
-#define CAN_WORD0_DATA_BYTE_1_SHIFT 16
-#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
-#define CAN_WORD0_DATA_BYTE_0_MASK 0xFF000000u
-#define CAN_WORD0_DATA_BYTE_0_SHIFT 24
-#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
-/* WORD1 Bit Fields */
-#define CAN_WORD1_DATA_BYTE_7_MASK 0xFFu
-#define CAN_WORD1_DATA_BYTE_7_SHIFT 0
-#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
-#define CAN_WORD1_DATA_BYTE_6_MASK 0xFF00u
-#define CAN_WORD1_DATA_BYTE_6_SHIFT 8
-#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
-#define CAN_WORD1_DATA_BYTE_5_MASK 0xFF0000u
-#define CAN_WORD1_DATA_BYTE_5_SHIFT 16
-#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
-#define CAN_WORD1_DATA_BYTE_4_MASK 0xFF000000u
-#define CAN_WORD1_DATA_BYTE_4_SHIFT 24
-#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
-/* RXIMR Bit Fields */
-#define CAN_RXIMR_MI_MASK 0xFFFFFFFFu
-#define CAN_RXIMR_MI_SHIFT 0
-#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
-
-/*!
- * @}
- */ /* end of group CAN_Register_Masks */
-
-
-/* CAN - Peripheral instance base addresses */
-/** Peripheral CAN0 base address */
-#define CAN0_BASE (0x40024000u)
-/** Peripheral CAN0 base pointer */
-#define CAN0 ((CAN_Type *)CAN0_BASE)
-#define CAN0_BASE_PTR (CAN0)
-/** Array initializer of CAN peripheral base pointers */
-#define CAN_BASES { CAN0 }
-
-/* ----------------------------------------------------------------------------
- -- CAN - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
- * @{
- */
-
-
-/* CAN - Register instance definitions */
-/* CAN0 */
-#define CAN0_MCR CAN_MCR_REG(CAN0)
-#define CAN0_CTRL1 CAN_CTRL1_REG(CAN0)
-#define CAN0_TIMER CAN_TIMER_REG(CAN0)
-#define CAN0_RXMGMASK CAN_RXMGMASK_REG(CAN0)
-#define CAN0_RX14MASK CAN_RX14MASK_REG(CAN0)
-#define CAN0_RX15MASK CAN_RX15MASK_REG(CAN0)
-#define CAN0_ECR CAN_ECR_REG(CAN0)
-#define CAN0_ESR1 CAN_ESR1_REG(CAN0)
-#define CAN0_IMASK1 CAN_IMASK1_REG(CAN0)
-#define CAN0_IFLAG1 CAN_IFLAG1_REG(CAN0)
-#define CAN0_CTRL2 CAN_CTRL2_REG(CAN0)
-#define CAN0_ESR2 CAN_ESR2_REG(CAN0)
-#define CAN0_CRCR CAN_CRCR_REG(CAN0)
-#define CAN0_RXFGMASK CAN_RXFGMASK_REG(CAN0)
-#define CAN0_RXFIR CAN_RXFIR_REG(CAN0)
-#define CAN0_CS0 CAN_CS_REG(CAN0,0)
-#define CAN0_ID0 CAN_ID_REG(CAN0,0)
-#define CAN0_WORD00 CAN_WORD0_REG(CAN0,0)
-#define CAN0_WORD10 CAN_WORD1_REG(CAN0,0)
-#define CAN0_CS1 CAN_CS_REG(CAN0,1)
-#define CAN0_ID1 CAN_ID_REG(CAN0,1)
-#define CAN0_WORD01 CAN_WORD0_REG(CAN0,1)
-#define CAN0_WORD11 CAN_WORD1_REG(CAN0,1)
-#define CAN0_CS2 CAN_CS_REG(CAN0,2)
-#define CAN0_ID2 CAN_ID_REG(CAN0,2)
-#define CAN0_WORD02 CAN_WORD0_REG(CAN0,2)
-#define CAN0_WORD12 CAN_WORD1_REG(CAN0,2)
-#define CAN0_CS3 CAN_CS_REG(CAN0,3)
-#define CAN0_ID3 CAN_ID_REG(CAN0,3)
-#define CAN0_WORD03 CAN_WORD0_REG(CAN0,3)
-#define CAN0_WORD13 CAN_WORD1_REG(CAN0,3)
-#define CAN0_CS4 CAN_CS_REG(CAN0,4)
-#define CAN0_ID4 CAN_ID_REG(CAN0,4)
-#define CAN0_WORD04 CAN_WORD0_REG(CAN0,4)
-#define CAN0_WORD14 CAN_WORD1_REG(CAN0,4)
-#define CAN0_CS5 CAN_CS_REG(CAN0,5)
-#define CAN0_ID5 CAN_ID_REG(CAN0,5)
-#define CAN0_WORD05 CAN_WORD0_REG(CAN0,5)
-#define CAN0_WORD15 CAN_WORD1_REG(CAN0,5)
-#define CAN0_CS6 CAN_CS_REG(CAN0,6)
-#define CAN0_ID6 CAN_ID_REG(CAN0,6)
-#define CAN0_WORD06 CAN_WORD0_REG(CAN0,6)
-#define CAN0_WORD16 CAN_WORD1_REG(CAN0,6)
-#define CAN0_CS7 CAN_CS_REG(CAN0,7)
-#define CAN0_ID7 CAN_ID_REG(CAN0,7)
-#define CAN0_WORD07 CAN_WORD0_REG(CAN0,7)
-#define CAN0_WORD17 CAN_WORD1_REG(CAN0,7)
-#define CAN0_CS8 CAN_CS_REG(CAN0,8)
-#define CAN0_ID8 CAN_ID_REG(CAN0,8)
-#define CAN0_WORD08 CAN_WORD0_REG(CAN0,8)
-#define CAN0_WORD18 CAN_WORD1_REG(CAN0,8)
-#define CAN0_CS9 CAN_CS_REG(CAN0,9)
-#define CAN0_ID9 CAN_ID_REG(CAN0,9)
-#define CAN0_WORD09 CAN_WORD0_REG(CAN0,9)
-#define CAN0_WORD19 CAN_WORD1_REG(CAN0,9)
-#define CAN0_CS10 CAN_CS_REG(CAN0,10)
-#define CAN0_ID10 CAN_ID_REG(CAN0,10)
-#define CAN0_WORD010 CAN_WORD0_REG(CAN0,10)
-#define CAN0_WORD110 CAN_WORD1_REG(CAN0,10)
-#define CAN0_CS11 CAN_CS_REG(CAN0,11)
-#define CAN0_ID11 CAN_ID_REG(CAN0,11)
-#define CAN0_WORD011 CAN_WORD0_REG(CAN0,11)
-#define CAN0_WORD111 CAN_WORD1_REG(CAN0,11)
-#define CAN0_CS12 CAN_CS_REG(CAN0,12)
-#define CAN0_ID12 CAN_ID_REG(CAN0,12)
-#define CAN0_WORD012 CAN_WORD0_REG(CAN0,12)
-#define CAN0_WORD112 CAN_WORD1_REG(CAN0,12)
-#define CAN0_CS13 CAN_CS_REG(CAN0,13)
-#define CAN0_ID13 CAN_ID_REG(CAN0,13)
-#define CAN0_WORD013 CAN_WORD0_REG(CAN0,13)
-#define CAN0_WORD113 CAN_WORD1_REG(CAN0,13)
-#define CAN0_CS14 CAN_CS_REG(CAN0,14)
-#define CAN0_ID14 CAN_ID_REG(CAN0,14)
-#define CAN0_WORD014 CAN_WORD0_REG(CAN0,14)
-#define CAN0_WORD114 CAN_WORD1_REG(CAN0,14)
-#define CAN0_CS15 CAN_CS_REG(CAN0,15)
-#define CAN0_ID15 CAN_ID_REG(CAN0,15)
-#define CAN0_WORD015 CAN_WORD0_REG(CAN0,15)
-#define CAN0_WORD115 CAN_WORD1_REG(CAN0,15)
-#define CAN0_RXIMR0 CAN_RXIMR_REG(CAN0,0)
-#define CAN0_RXIMR1 CAN_RXIMR_REG(CAN0,1)
-#define CAN0_RXIMR2 CAN_RXIMR_REG(CAN0,2)
-#define CAN0_RXIMR3 CAN_RXIMR_REG(CAN0,3)
-#define CAN0_RXIMR4 CAN_RXIMR_REG(CAN0,4)
-#define CAN0_RXIMR5 CAN_RXIMR_REG(CAN0,5)
-#define CAN0_RXIMR6 CAN_RXIMR_REG(CAN0,6)
-#define CAN0_RXIMR7 CAN_RXIMR_REG(CAN0,7)
-#define CAN0_RXIMR8 CAN_RXIMR_REG(CAN0,8)
-#define CAN0_RXIMR9 CAN_RXIMR_REG(CAN0,9)
-#define CAN0_RXIMR10 CAN_RXIMR_REG(CAN0,10)
-#define CAN0_RXIMR11 CAN_RXIMR_REG(CAN0,11)
-#define CAN0_RXIMR12 CAN_RXIMR_REG(CAN0,12)
-#define CAN0_RXIMR13 CAN_RXIMR_REG(CAN0,13)
-#define CAN0_RXIMR14 CAN_RXIMR_REG(CAN0,14)
-#define CAN0_RXIMR15 CAN_RXIMR_REG(CAN0,15)
-
-/* CAN - Register array accessors */
-#define CAN0_CS(index) CAN_CS_REG(CAN0,index)
-#define CAN0_ID(index) CAN_ID_REG(CAN0,index)
-#define CAN0_WORD0(index) CAN_WORD0_REG(CAN0,index)
-#define CAN0_WORD1(index) CAN_WORD1_REG(CAN0,index)
-#define CAN0_RXIMR(index) CAN_RXIMR_REG(CAN0,index)
-
-/*!
- * @}
- */ /* end of group CAN_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group CAN_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- CAU Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
- * @{
- */
-
-/** CAU - Register Layout Typedef */
-typedef struct {
- __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
- uint8_t RESERVED_0[2048];
- __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
- __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
- __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
- uint8_t RESERVED_1[20];
- __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
- __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
- __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
- uint8_t RESERVED_2[20];
- __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
- __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
- __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
- uint8_t RESERVED_3[20];
- __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
- __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
- __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
- uint8_t RESERVED_4[84];
- __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
- __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
- __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
- uint8_t RESERVED_5[20];
- __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
- __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
- __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
- uint8_t RESERVED_6[276];
- __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
- __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
- __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
- uint8_t RESERVED_7[20];
- __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
- __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
- __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
-} CAU_Type, *CAU_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- CAU - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
- * @{
- */
-
-
-/* CAU - Register accessors */
-#define CAU_DIRECT_REG(base,index) ((base)->DIRECT[index])
-#define CAU_LDR_CASR_REG(base) ((base)->LDR_CASR)
-#define CAU_LDR_CAA_REG(base) ((base)->LDR_CAA)
-#define CAU_LDR_CA_REG(base,index) ((base)->LDR_CA[index])
-#define CAU_STR_CASR_REG(base) ((base)->STR_CASR)
-#define CAU_STR_CAA_REG(base) ((base)->STR_CAA)
-#define CAU_STR_CA_REG(base,index) ((base)->STR_CA[index])
-#define CAU_ADR_CASR_REG(base) ((base)->ADR_CASR)
-#define CAU_ADR_CAA_REG(base) ((base)->ADR_CAA)
-#define CAU_ADR_CA_REG(base,index) ((base)->ADR_CA[index])
-#define CAU_RADR_CASR_REG(base) ((base)->RADR_CASR)
-#define CAU_RADR_CAA_REG(base) ((base)->RADR_CAA)
-#define CAU_RADR_CA_REG(base,index) ((base)->RADR_CA[index])
-#define CAU_XOR_CASR_REG(base) ((base)->XOR_CASR)
-#define CAU_XOR_CAA_REG(base) ((base)->XOR_CAA)
-#define CAU_XOR_CA_REG(base,index) ((base)->XOR_CA[index])
-#define CAU_ROTL_CASR_REG(base) ((base)->ROTL_CASR)
-#define CAU_ROTL_CAA_REG(base) ((base)->ROTL_CAA)
-#define CAU_ROTL_CA_REG(base,index) ((base)->ROTL_CA[index])
-#define CAU_AESC_CASR_REG(base) ((base)->AESC_CASR)
-#define CAU_AESC_CAA_REG(base) ((base)->AESC_CAA)
-#define CAU_AESC_CA_REG(base,index) ((base)->AESC_CA[index])
-#define CAU_AESIC_CASR_REG(base) ((base)->AESIC_CASR)
-#define CAU_AESIC_CAA_REG(base) ((base)->AESIC_CAA)
-#define CAU_AESIC_CA_REG(base,index) ((base)->AESIC_CA[index])
-
-/*!
- * @}
- */ /* end of group CAU_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- CAU Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CAU_Register_Masks CAU Register Masks
- * @{
- */
-
-/* LDR_CASR Bit Fields */
-#define CAU_LDR_CASR_IC_MASK 0x1u
-#define CAU_LDR_CASR_IC_SHIFT 0
-#define CAU_LDR_CASR_DPE_MASK 0x2u
-#define CAU_LDR_CASR_DPE_SHIFT 1
-#define CAU_LDR_CASR_VER_MASK 0xF0000000u
-#define CAU_LDR_CASR_VER_SHIFT 28
-#define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_VER_SHIFT))&CAU_LDR_CASR_VER_MASK)
-/* STR_CASR Bit Fields */
-#define CAU_STR_CASR_IC_MASK 0x1u
-#define CAU_STR_CASR_IC_SHIFT 0
-#define CAU_STR_CASR_DPE_MASK 0x2u
-#define CAU_STR_CASR_DPE_SHIFT 1
-#define CAU_STR_CASR_VER_MASK 0xF0000000u
-#define CAU_STR_CASR_VER_SHIFT 28
-#define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_VER_SHIFT))&CAU_STR_CASR_VER_MASK)
-/* ADR_CASR Bit Fields */
-#define CAU_ADR_CASR_IC_MASK 0x1u
-#define CAU_ADR_CASR_IC_SHIFT 0
-#define CAU_ADR_CASR_DPE_MASK 0x2u
-#define CAU_ADR_CASR_DPE_SHIFT 1
-#define CAU_ADR_CASR_VER_MASK 0xF0000000u
-#define CAU_ADR_CASR_VER_SHIFT 28
-#define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_VER_SHIFT))&CAU_ADR_CASR_VER_MASK)
-/* RADR_CASR Bit Fields */
-#define CAU_RADR_CASR_IC_MASK 0x1u
-#define CAU_RADR_CASR_IC_SHIFT 0
-#define CAU_RADR_CASR_DPE_MASK 0x2u
-#define CAU_RADR_CASR_DPE_SHIFT 1
-#define CAU_RADR_CASR_VER_MASK 0xF0000000u
-#define CAU_RADR_CASR_VER_SHIFT 28
-#define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_VER_SHIFT))&CAU_RADR_CASR_VER_MASK)
-/* XOR_CASR Bit Fields */
-#define CAU_XOR_CASR_IC_MASK 0x1u
-#define CAU_XOR_CASR_IC_SHIFT 0
-#define CAU_XOR_CASR_DPE_MASK 0x2u
-#define CAU_XOR_CASR_DPE_SHIFT 1
-#define CAU_XOR_CASR_VER_MASK 0xF0000000u
-#define CAU_XOR_CASR_VER_SHIFT 28
-#define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_VER_SHIFT))&CAU_XOR_CASR_VER_MASK)
-/* ROTL_CASR Bit Fields */
-#define CAU_ROTL_CASR_IC_MASK 0x1u
-#define CAU_ROTL_CASR_IC_SHIFT 0
-#define CAU_ROTL_CASR_DPE_MASK 0x2u
-#define CAU_ROTL_CASR_DPE_SHIFT 1
-#define CAU_ROTL_CASR_VER_MASK 0xF0000000u
-#define CAU_ROTL_CASR_VER_SHIFT 28
-#define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_VER_SHIFT))&CAU_ROTL_CASR_VER_MASK)
-/* AESC_CASR Bit Fields */
-#define CAU_AESC_CASR_IC_MASK 0x1u
-#define CAU_AESC_CASR_IC_SHIFT 0
-#define CAU_AESC_CASR_DPE_MASK 0x2u
-#define CAU_AESC_CASR_DPE_SHIFT 1
-#define CAU_AESC_CASR_VER_MASK 0xF0000000u
-#define CAU_AESC_CASR_VER_SHIFT 28
-#define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_VER_SHIFT))&CAU_AESC_CASR_VER_MASK)
-/* AESIC_CASR Bit Fields */
-#define CAU_AESIC_CASR_IC_MASK 0x1u
-#define CAU_AESIC_CASR_IC_SHIFT 0
-#define CAU_AESIC_CASR_DPE_MASK 0x2u
-#define CAU_AESIC_CASR_DPE_SHIFT 1
-#define CAU_AESIC_CASR_VER_MASK 0xF0000000u
-#define CAU_AESIC_CASR_VER_SHIFT 28
-#define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_VER_SHIFT))&CAU_AESIC_CASR_VER_MASK)
-
-/*!
- * @}
- */ /* end of group CAU_Register_Masks */
-
-
-/* CAU - Peripheral instance base addresses */
-/** Peripheral CAU base address */
-#define CAU_BASE (0xE0081000u)
-/** Peripheral CAU base pointer */
-#define CAU ((CAU_Type *)CAU_BASE)
-#define CAU_BASE_PTR (CAU)
-/** Array initializer of CAU peripheral base pointers */
-#define CAU_BASES { CAU }
-
-/* ----------------------------------------------------------------------------
- -- CAU - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
- * @{
- */
-
-
-/* CAU - Register instance definitions */
-/* CAU */
-#define CAU_DIRECT0 CAU_DIRECT_REG(CAU,0)
-#define CAU_DIRECT1 CAU_DIRECT_REG(CAU,1)
-#define CAU_DIRECT2 CAU_DIRECT_REG(CAU,2)
-#define CAU_DIRECT3 CAU_DIRECT_REG(CAU,3)
-#define CAU_DIRECT4 CAU_DIRECT_REG(CAU,4)
-#define CAU_DIRECT5 CAU_DIRECT_REG(CAU,5)
-#define CAU_DIRECT6 CAU_DIRECT_REG(CAU,6)
-#define CAU_DIRECT7 CAU_DIRECT_REG(CAU,7)
-#define CAU_DIRECT8 CAU_DIRECT_REG(CAU,8)
-#define CAU_DIRECT9 CAU_DIRECT_REG(CAU,9)
-#define CAU_DIRECT10 CAU_DIRECT_REG(CAU,10)
-#define CAU_DIRECT11 CAU_DIRECT_REG(CAU,11)
-#define CAU_DIRECT12 CAU_DIRECT_REG(CAU,12)
-#define CAU_DIRECT13 CAU_DIRECT_REG(CAU,13)
-#define CAU_DIRECT14 CAU_DIRECT_REG(CAU,14)
-#define CAU_DIRECT15 CAU_DIRECT_REG(CAU,15)
-#define CAU_LDR_CASR CAU_LDR_CASR_REG(CAU)
-#define CAU_LDR_CAA CAU_LDR_CAA_REG(CAU)
-#define CAU_LDR_CA0 CAU_LDR_CA_REG(CAU,0)
-#define CAU_LDR_CA1 CAU_LDR_CA_REG(CAU,1)
-#define CAU_LDR_CA2 CAU_LDR_CA_REG(CAU,2)
-#define CAU_LDR_CA3 CAU_LDR_CA_REG(CAU,3)
-#define CAU_LDR_CA4 CAU_LDR_CA_REG(CAU,4)
-#define CAU_LDR_CA5 CAU_LDR_CA_REG(CAU,5)
-#define CAU_LDR_CA6 CAU_LDR_CA_REG(CAU,6)
-#define CAU_LDR_CA7 CAU_LDR_CA_REG(CAU,7)
-#define CAU_LDR_CA8 CAU_LDR_CA_REG(CAU,8)
-#define CAU_STR_CASR CAU_STR_CASR_REG(CAU)
-#define CAU_STR_CAA CAU_STR_CAA_REG(CAU)
-#define CAU_STR_CA0 CAU_STR_CA_REG(CAU,0)
-#define CAU_STR_CA1 CAU_STR_CA_REG(CAU,1)
-#define CAU_STR_CA2 CAU_STR_CA_REG(CAU,2)
-#define CAU_STR_CA3 CAU_STR_CA_REG(CAU,3)
-#define CAU_STR_CA4 CAU_STR_CA_REG(CAU,4)
-#define CAU_STR_CA5 CAU_STR_CA_REG(CAU,5)
-#define CAU_STR_CA6 CAU_STR_CA_REG(CAU,6)
-#define CAU_STR_CA7 CAU_STR_CA_REG(CAU,7)
-#define CAU_STR_CA8 CAU_STR_CA_REG(CAU,8)
-#define CAU_ADR_CASR CAU_ADR_CASR_REG(CAU)
-#define CAU_ADR_CAA CAU_ADR_CAA_REG(CAU)
-#define CAU_ADR_CA0 CAU_ADR_CA_REG(CAU,0)
-#define CAU_ADR_CA1 CAU_ADR_CA_REG(CAU,1)
-#define CAU_ADR_CA2 CAU_ADR_CA_REG(CAU,2)
-#define CAU_ADR_CA3 CAU_ADR_CA_REG(CAU,3)
-#define CAU_ADR_CA4 CAU_ADR_CA_REG(CAU,4)
-#define CAU_ADR_CA5 CAU_ADR_CA_REG(CAU,5)
-#define CAU_ADR_CA6 CAU_ADR_CA_REG(CAU,6)
-#define CAU_ADR_CA7 CAU_ADR_CA_REG(CAU,7)
-#define CAU_ADR_CA8 CAU_ADR_CA_REG(CAU,8)
-#define CAU_RADR_CASR CAU_RADR_CASR_REG(CAU)
-#define CAU_RADR_CAA CAU_RADR_CAA_REG(CAU)
-#define CAU_RADR_CA0 CAU_RADR_CA_REG(CAU,0)
-#define CAU_RADR_CA1 CAU_RADR_CA_REG(CAU,1)
-#define CAU_RADR_CA2 CAU_RADR_CA_REG(CAU,2)
-#define CAU_RADR_CA3 CAU_RADR_CA_REG(CAU,3)
-#define CAU_RADR_CA4 CAU_RADR_CA_REG(CAU,4)
-#define CAU_RADR_CA5 CAU_RADR_CA_REG(CAU,5)
-#define CAU_RADR_CA6 CAU_RADR_CA_REG(CAU,6)
-#define CAU_RADR_CA7 CAU_RADR_CA_REG(CAU,7)
-#define CAU_RADR_CA8 CAU_RADR_CA_REG(CAU,8)
-#define CAU_XOR_CASR CAU_XOR_CASR_REG(CAU)
-#define CAU_XOR_CAA CAU_XOR_CAA_REG(CAU)
-#define CAU_XOR_CA0 CAU_XOR_CA_REG(CAU,0)
-#define CAU_XOR_CA1 CAU_XOR_CA_REG(CAU,1)
-#define CAU_XOR_CA2 CAU_XOR_CA_REG(CAU,2)
-#define CAU_XOR_CA3 CAU_XOR_CA_REG(CAU,3)
-#define CAU_XOR_CA4 CAU_XOR_CA_REG(CAU,4)
-#define CAU_XOR_CA5 CAU_XOR_CA_REG(CAU,5)
-#define CAU_XOR_CA6 CAU_XOR_CA_REG(CAU,6)
-#define CAU_XOR_CA7 CAU_XOR_CA_REG(CAU,7)
-#define CAU_XOR_CA8 CAU_XOR_CA_REG(CAU,8)
-#define CAU_ROTL_CASR CAU_ROTL_CASR_REG(CAU)
-#define CAU_ROTL_CAA CAU_ROTL_CAA_REG(CAU)
-#define CAU_ROTL_CA0 CAU_ROTL_CA_REG(CAU,0)
-#define CAU_ROTL_CA1 CAU_ROTL_CA_REG(CAU,1)
-#define CAU_ROTL_CA2 CAU_ROTL_CA_REG(CAU,2)
-#define CAU_ROTL_CA3 CAU_ROTL_CA_REG(CAU,3)
-#define CAU_ROTL_CA4 CAU_ROTL_CA_REG(CAU,4)
-#define CAU_ROTL_CA5 CAU_ROTL_CA_REG(CAU,5)
-#define CAU_ROTL_CA6 CAU_ROTL_CA_REG(CAU,6)
-#define CAU_ROTL_CA7 CAU_ROTL_CA_REG(CAU,7)
-#define CAU_ROTL_CA8 CAU_ROTL_CA_REG(CAU,8)
-#define CAU_AESC_CASR CAU_AESC_CASR_REG(CAU)
-#define CAU_AESC_CAA CAU_AESC_CAA_REG(CAU)
-#define CAU_AESC_CA0 CAU_AESC_CA_REG(CAU,0)
-#define CAU_AESC_CA1 CAU_AESC_CA_REG(CAU,1)
-#define CAU_AESC_CA2 CAU_AESC_CA_REG(CAU,2)
-#define CAU_AESC_CA3 CAU_AESC_CA_REG(CAU,3)
-#define CAU_AESC_CA4 CAU_AESC_CA_REG(CAU,4)
-#define CAU_AESC_CA5 CAU_AESC_CA_REG(CAU,5)
-#define CAU_AESC_CA6 CAU_AESC_CA_REG(CAU,6)
-#define CAU_AESC_CA7 CAU_AESC_CA_REG(CAU,7)
-#define CAU_AESC_CA8 CAU_AESC_CA_REG(CAU,8)
-#define CAU_AESIC_CASR CAU_AESIC_CASR_REG(CAU)
-#define CAU_AESIC_CAA CAU_AESIC_CAA_REG(CAU)
-#define CAU_AESIC_CA0 CAU_AESIC_CA_REG(CAU,0)
-#define CAU_AESIC_CA1 CAU_AESIC_CA_REG(CAU,1)
-#define CAU_AESIC_CA2 CAU_AESIC_CA_REG(CAU,2)
-#define CAU_AESIC_CA3 CAU_AESIC_CA_REG(CAU,3)
-#define CAU_AESIC_CA4 CAU_AESIC_CA_REG(CAU,4)
-#define CAU_AESIC_CA5 CAU_AESIC_CA_REG(CAU,5)
-#define CAU_AESIC_CA6 CAU_AESIC_CA_REG(CAU,6)
-#define CAU_AESIC_CA7 CAU_AESIC_CA_REG(CAU,7)
-#define CAU_AESIC_CA8 CAU_AESIC_CA_REG(CAU,8)
-
-/* CAU - Register array accessors */
-#define CAU_DIRECT(index) CAU_DIRECT_REG(CAU,index)
-#define CAU_LDR_CA(index) CAU_LDR_CA_REG(CAU,index)
-#define CAU_STR_CA(index) CAU_STR_CA_REG(CAU,index)
-#define CAU_ADR_CA(index) CAU_ADR_CA_REG(CAU,index)
-#define CAU_RADR_CA(index) CAU_RADR_CA_REG(CAU,index)
-#define CAU_XOR_CA(index) CAU_XOR_CA_REG(CAU,index)
-#define CAU_ROTL_CA(index) CAU_ROTL_CA_REG(CAU,index)
-#define CAU_AESC_CA(index) CAU_AESC_CA_REG(CAU,index)
-#define CAU_AESIC_CA(index) CAU_AESIC_CA_REG(CAU,index)
-
-/*!
- * @}
- */ /* end of group CAU_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group CAU_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- CMP Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
- * @{
- */
-
-/** CMP - Register Layout Typedef */
-typedef struct {
- __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
- __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
- __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
- __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
- __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
- __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
-} CMP_Type, *CMP_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- CMP - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
- * @{
- */
-
-
-/* CMP - Register accessors */
-#define CMP_CR0_REG(base) ((base)->CR0)
-#define CMP_CR1_REG(base) ((base)->CR1)
-#define CMP_FPR_REG(base) ((base)->FPR)
-#define CMP_SCR_REG(base) ((base)->SCR)
-#define CMP_DACCR_REG(base) ((base)->DACCR)
-#define CMP_MUXCR_REG(base) ((base)->MUXCR)
-
-/*!
- * @}
- */ /* end of group CMP_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- CMP Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CMP_Register_Masks CMP Register Masks
- * @{
- */
-
-/* CR0 Bit Fields */
-#define CMP_CR0_HYSTCTR_MASK 0x3u
-#define CMP_CR0_HYSTCTR_SHIFT 0
-#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
-#define CMP_CR0_FILTER_CNT_MASK 0x70u
-#define CMP_CR0_FILTER_CNT_SHIFT 4
-#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
-/* CR1 Bit Fields */
-#define CMP_CR1_EN_MASK 0x1u
-#define CMP_CR1_EN_SHIFT 0
-#define CMP_CR1_OPE_MASK 0x2u
-#define CMP_CR1_OPE_SHIFT 1
-#define CMP_CR1_COS_MASK 0x4u
-#define CMP_CR1_COS_SHIFT 2
-#define CMP_CR1_INV_MASK 0x8u
-#define CMP_CR1_INV_SHIFT 3
-#define CMP_CR1_PMODE_MASK 0x10u
-#define CMP_CR1_PMODE_SHIFT 4
-#define CMP_CR1_WE_MASK 0x40u
-#define CMP_CR1_WE_SHIFT 6
-#define CMP_CR1_SE_MASK 0x80u
-#define CMP_CR1_SE_SHIFT 7
-/* FPR Bit Fields */
-#define CMP_FPR_FILT_PER_MASK 0xFFu
-#define CMP_FPR_FILT_PER_SHIFT 0
-#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
-/* SCR Bit Fields */
-#define CMP_SCR_COUT_MASK 0x1u
-#define CMP_SCR_COUT_SHIFT 0
-#define CMP_SCR_CFF_MASK 0x2u
-#define CMP_SCR_CFF_SHIFT 1
-#define CMP_SCR_CFR_MASK 0x4u
-#define CMP_SCR_CFR_SHIFT 2
-#define CMP_SCR_IEF_MASK 0x8u
-#define CMP_SCR_IEF_SHIFT 3
-#define CMP_SCR_IER_MASK 0x10u
-#define CMP_SCR_IER_SHIFT 4
-#define CMP_SCR_DMAEN_MASK 0x40u
-#define CMP_SCR_DMAEN_SHIFT 6
-/* DACCR Bit Fields */
-#define CMP_DACCR_VOSEL_MASK 0x3Fu
-#define CMP_DACCR_VOSEL_SHIFT 0
-#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
-#define CMP_DACCR_VRSEL_MASK 0x40u
-#define CMP_DACCR_VRSEL_SHIFT 6
-#define CMP_DACCR_DACEN_MASK 0x80u
-#define CMP_DACCR_DACEN_SHIFT 7
-/* MUXCR Bit Fields */
-#define CMP_MUXCR_MSEL_MASK 0x7u
-#define CMP_MUXCR_MSEL_SHIFT 0
-#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
-#define CMP_MUXCR_PSEL_MASK 0x38u
-#define CMP_MUXCR_PSEL_SHIFT 3
-#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
-#define CMP_MUXCR_PSTM_MASK 0x80u
-#define CMP_MUXCR_PSTM_SHIFT 7
-
-/*!
- * @}
- */ /* end of group CMP_Register_Masks */
-
-
-/* CMP - Peripheral instance base addresses */
-/** Peripheral CMP0 base address */
-#define CMP0_BASE (0x40073000u)
-/** Peripheral CMP0 base pointer */
-#define CMP0 ((CMP_Type *)CMP0_BASE)
-#define CMP0_BASE_PTR (CMP0)
-/** Peripheral CMP1 base address */
-#define CMP1_BASE (0x40073008u)
-/** Peripheral CMP1 base pointer */
-#define CMP1 ((CMP_Type *)CMP1_BASE)
-#define CMP1_BASE_PTR (CMP1)
-/** Peripheral CMP2 base address */
-#define CMP2_BASE (0x40073010u)
-/** Peripheral CMP2 base pointer */
-#define CMP2 ((CMP_Type *)CMP2_BASE)
-#define CMP2_BASE_PTR (CMP2)
-/** Array initializer of CMP peripheral base pointers */
-#define CMP_BASES { CMP0, CMP1, CMP2 }
-
-/* ----------------------------------------------------------------------------
- -- CMP - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
- * @{
- */
-
-
-/* CMP - Register instance definitions */
-/* CMP0 */
-#define CMP0_CR0 CMP_CR0_REG(CMP0)
-#define CMP0_CR1 CMP_CR1_REG(CMP0)
-#define CMP0_FPR CMP_FPR_REG(CMP0)
-#define CMP0_SCR CMP_SCR_REG(CMP0)
-#define CMP0_DACCR CMP_DACCR_REG(CMP0)
-#define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
-/* CMP1 */
-#define CMP1_CR0 CMP_CR0_REG(CMP1)
-#define CMP1_CR1 CMP_CR1_REG(CMP1)
-#define CMP1_FPR CMP_FPR_REG(CMP1)
-#define CMP1_SCR CMP_SCR_REG(CMP1)
-#define CMP1_DACCR CMP_DACCR_REG(CMP1)
-#define CMP1_MUXCR CMP_MUXCR_REG(CMP1)
-/* CMP2 */
-#define CMP2_CR0 CMP_CR0_REG(CMP2)
-#define CMP2_CR1 CMP_CR1_REG(CMP2)
-#define CMP2_FPR CMP_FPR_REG(CMP2)
-#define CMP2_SCR CMP_SCR_REG(CMP2)
-#define CMP2_DACCR CMP_DACCR_REG(CMP2)
-#define CMP2_MUXCR CMP_MUXCR_REG(CMP2)
-
-/*!
- * @}
- */ /* end of group CMP_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group CMP_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- CMT Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
- * @{
- */
-
-/** CMT - Register Layout Typedef */
-typedef struct {
- __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
- __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
- __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
- __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
- __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
- __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
- __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
- __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
- __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
- __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
- __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
- __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */
-} CMT_Type, *CMT_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- CMT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
- * @{
- */
-
-
-/* CMT - Register accessors */
-#define CMT_CGH1_REG(base) ((base)->CGH1)
-#define CMT_CGL1_REG(base) ((base)->CGL1)
-#define CMT_CGH2_REG(base) ((base)->CGH2)
-#define CMT_CGL2_REG(base) ((base)->CGL2)
-#define CMT_OC_REG(base) ((base)->OC)
-#define CMT_MSC_REG(base) ((base)->MSC)
-#define CMT_CMD1_REG(base) ((base)->CMD1)
-#define CMT_CMD2_REG(base) ((base)->CMD2)
-#define CMT_CMD3_REG(base) ((base)->CMD3)
-#define CMT_CMD4_REG(base) ((base)->CMD4)
-#define CMT_PPS_REG(base) ((base)->PPS)
-#define CMT_DMA_REG(base) ((base)->DMA)
-
-/*!
- * @}
- */ /* end of group CMT_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- CMT Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CMT_Register_Masks CMT Register Masks
- * @{
- */
-
-/* CGH1 Bit Fields */
-#define CMT_CGH1_PH_MASK 0xFFu
-#define CMT_CGH1_PH_SHIFT 0
-#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
-/* CGL1 Bit Fields */
-#define CMT_CGL1_PL_MASK 0xFFu
-#define CMT_CGL1_PL_SHIFT 0
-#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
-/* CGH2 Bit Fields */
-#define CMT_CGH2_SH_MASK 0xFFu
-#define CMT_CGH2_SH_SHIFT 0
-#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
-/* CGL2 Bit Fields */
-#define CMT_CGL2_SL_MASK 0xFFu
-#define CMT_CGL2_SL_SHIFT 0
-#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
-/* OC Bit Fields */
-#define CMT_OC_IROPEN_MASK 0x20u
-#define CMT_OC_IROPEN_SHIFT 5
-#define CMT_OC_CMTPOL_MASK 0x40u
-#define CMT_OC_CMTPOL_SHIFT 6
-#define CMT_OC_IROL_MASK 0x80u
-#define CMT_OC_IROL_SHIFT 7
-/* MSC Bit Fields */
-#define CMT_MSC_MCGEN_MASK 0x1u
-#define CMT_MSC_MCGEN_SHIFT 0
-#define CMT_MSC_EOCIE_MASK 0x2u
-#define CMT_MSC_EOCIE_SHIFT 1
-#define CMT_MSC_FSK_MASK 0x4u
-#define CMT_MSC_FSK_SHIFT 2
-#define CMT_MSC_BASE_MASK 0x8u
-#define CMT_MSC_BASE_SHIFT 3
-#define CMT_MSC_EXSPC_MASK 0x10u
-#define CMT_MSC_EXSPC_SHIFT 4
-#define CMT_MSC_CMTDIV_MASK 0x60u
-#define CMT_MSC_CMTDIV_SHIFT 5
-#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
-#define CMT_MSC_EOCF_MASK 0x80u
-#define CMT_MSC_EOCF_SHIFT 7
-/* CMD1 Bit Fields */
-#define CMT_CMD1_MB_MASK 0xFFu
-#define CMT_CMD1_MB_SHIFT 0
-#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
-/* CMD2 Bit Fields */
-#define CMT_CMD2_MB_MASK 0xFFu
-#define CMT_CMD2_MB_SHIFT 0
-#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
-/* CMD3 Bit Fields */
-#define CMT_CMD3_SB_MASK 0xFFu
-#define CMT_CMD3_SB_SHIFT 0
-#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
-/* CMD4 Bit Fields */
-#define CMT_CMD4_SB_MASK 0xFFu
-#define CMT_CMD4_SB_SHIFT 0
-#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
-/* PPS Bit Fields */
-#define CMT_PPS_PPSDIV_MASK 0xFu
-#define CMT_PPS_PPSDIV_SHIFT 0
-#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
-/* DMA Bit Fields */
-#define CMT_DMA_DMA_MASK 0x1u
-#define CMT_DMA_DMA_SHIFT 0
-
-/*!
- * @}
- */ /* end of group CMT_Register_Masks */
-
-
-/* CMT - Peripheral instance base addresses */
-/** Peripheral CMT base address */
-#define CMT_BASE (0x40062000u)
-/** Peripheral CMT base pointer */
-#define CMT ((CMT_Type *)CMT_BASE)
-#define CMT_BASE_PTR (CMT)
-/** Array initializer of CMT peripheral base pointers */
-#define CMT_BASES { CMT }
-
-/* ----------------------------------------------------------------------------
- -- CMT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
- * @{
- */
-
-
-/* CMT - Register instance definitions */
-/* CMT */
-#define CMT_CGH1 CMT_CGH1_REG(CMT)
-#define CMT_CGL1 CMT_CGL1_REG(CMT)
-#define CMT_CGH2 CMT_CGH2_REG(CMT)
-#define CMT_CGL2 CMT_CGL2_REG(CMT)
-#define CMT_OC CMT_OC_REG(CMT)
-#define CMT_MSC CMT_MSC_REG(CMT)
-#define CMT_CMD1 CMT_CMD1_REG(CMT)
-#define CMT_CMD2 CMT_CMD2_REG(CMT)
-#define CMT_CMD3 CMT_CMD3_REG(CMT)
-#define CMT_CMD4 CMT_CMD4_REG(CMT)
-#define CMT_PPS CMT_PPS_REG(CMT)
-#define CMT_DMA CMT_DMA_REG(CMT)
-
-/*!
- * @}
- */ /* end of group CMT_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group CMT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- CRC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
- * @{
- */
-
-/** CRC - Register Layout Typedef */
-typedef struct {
- union { /* offset: 0x0 */
- struct { /* offset: 0x0 */
- __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
- __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
- } ACCESS16BIT;
- __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
- struct { /* offset: 0x0 */
- __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
- __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
- __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
- __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
- } ACCESS8BIT;
- };
- union { /* offset: 0x4 */
- struct { /* offset: 0x4 */
- __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
- __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
- } GPOLY_ACCESS16BIT;
- __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
- struct { /* offset: 0x4 */
- __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
- __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
- __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
- __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
- } GPOLY_ACCESS8BIT;
- };
- union { /* offset: 0x8 */
- __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
- struct { /* offset: 0x8 */
- uint8_t RESERVED_0[3];
- __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
- } CTRL_ACCESS8BIT;
- };
-} CRC_Type, *CRC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- CRC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
- * @{
- */
-
-
-/* CRC - Register accessors */
-#define CRC_DATAL_REG(base) ((base)->ACCESS16BIT.DATAL)
-#define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH)
-#define CRC_DATA_REG(base) ((base)->DATA)
-#define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL)
-#define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU)
-#define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL)
-#define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU)
-#define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL)
-#define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH)
-#define CRC_GPOLY_REG(base) ((base)->GPOLY)
-#define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
-#define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
-#define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
-#define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
-#define CRC_CTRL_REG(base) ((base)->CTRL)
-#define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU)
-
-/*!
- * @}
- */ /* end of group CRC_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- CRC Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CRC_Register_Masks CRC Register Masks
- * @{
- */
-
-/* DATAL Bit Fields */
-#define CRC_DATAL_DATAL_MASK 0xFFFFu
-#define CRC_DATAL_DATAL_SHIFT 0
-#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
-/* DATAH Bit Fields */
-#define CRC_DATAH_DATAH_MASK 0xFFFFu
-#define CRC_DATAH_DATAH_SHIFT 0
-#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
-/* DATA Bit Fields */
-#define CRC_DATA_LL_MASK 0xFFu
-#define CRC_DATA_LL_SHIFT 0
-#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
-#define CRC_DATA_LU_MASK 0xFF00u
-#define CRC_DATA_LU_SHIFT 8
-#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
-#define CRC_DATA_HL_MASK 0xFF0000u
-#define CRC_DATA_HL_SHIFT 16
-#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
-#define CRC_DATA_HU_MASK 0xFF000000u
-#define CRC_DATA_HU_SHIFT 24
-#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
-/* DATALL Bit Fields */
-#define CRC_DATALL_DATALL_MASK 0xFFu
-#define CRC_DATALL_DATALL_SHIFT 0
-#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
-/* DATALU Bit Fields */
-#define CRC_DATALU_DATALU_MASK 0xFFu
-#define CRC_DATALU_DATALU_SHIFT 0
-#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
-/* DATAHL Bit Fields */
-#define CRC_DATAHL_DATAHL_MASK 0xFFu
-#define CRC_DATAHL_DATAHL_SHIFT 0
-#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
-/* DATAHU Bit Fields */
-#define CRC_DATAHU_DATAHU_MASK 0xFFu
-#define CRC_DATAHU_DATAHU_SHIFT 0
-#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
-/* GPOLYL Bit Fields */
-#define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
-#define CRC_GPOLYL_GPOLYL_SHIFT 0
-#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
-/* GPOLYH Bit Fields */
-#define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
-#define CRC_GPOLYH_GPOLYH_SHIFT 0
-#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
-/* GPOLY Bit Fields */
-#define CRC_GPOLY_LOW_MASK 0xFFFFu
-#define CRC_GPOLY_LOW_SHIFT 0
-#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
-#define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
-#define CRC_GPOLY_HIGH_SHIFT 16
-#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
-/* GPOLYLL Bit Fields */
-#define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
-#define CRC_GPOLYLL_GPOLYLL_SHIFT 0
-#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
-/* GPOLYLU Bit Fields */
-#define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
-#define CRC_GPOLYLU_GPOLYLU_SHIFT 0
-#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
-/* GPOLYHL Bit Fields */
-#define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
-#define CRC_GPOLYHL_GPOLYHL_SHIFT 0
-#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
-/* GPOLYHU Bit Fields */
-#define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
-#define CRC_GPOLYHU_GPOLYHU_SHIFT 0
-#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
-/* CTRL Bit Fields */
-#define CRC_CTRL_TCRC_MASK 0x1000000u
-#define CRC_CTRL_TCRC_SHIFT 24
-#define CRC_CTRL_WAS_MASK 0x2000000u
-#define CRC_CTRL_WAS_SHIFT 25
-#define CRC_CTRL_FXOR_MASK 0x4000000u
-#define CRC_CTRL_FXOR_SHIFT 26
-#define CRC_CTRL_TOTR_MASK 0x30000000u
-#define CRC_CTRL_TOTR_SHIFT 28
-#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
-#define CRC_CTRL_TOT_MASK 0xC0000000u
-#define CRC_CTRL_TOT_SHIFT 30
-#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
-/* CTRLHU Bit Fields */
-#define CRC_CTRLHU_TCRC_MASK 0x1u
-#define CRC_CTRLHU_TCRC_SHIFT 0
-#define CRC_CTRLHU_WAS_MASK 0x2u
-#define CRC_CTRLHU_WAS_SHIFT 1
-#define CRC_CTRLHU_FXOR_MASK 0x4u
-#define CRC_CTRLHU_FXOR_SHIFT 2
-#define CRC_CTRLHU_TOTR_MASK 0x30u
-#define CRC_CTRLHU_TOTR_SHIFT 4
-#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
-#define CRC_CTRLHU_TOT_MASK 0xC0u
-#define CRC_CTRLHU_TOT_SHIFT 6
-#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
-
-/*!
- * @}
- */ /* end of group CRC_Register_Masks */
-
-
-/* CRC - Peripheral instance base addresses */
-/** Peripheral CRC base address */
-#define CRC_BASE (0x40032000u)
-/** Peripheral CRC base pointer */
-#define CRC0 ((CRC_Type *)CRC_BASE)
-#define CRC_BASE_PTR (CRC0)
-/** Array initializer of CRC peripheral base pointers */
-#define CRC_BASES { CRC0 }
-
-/* ----------------------------------------------------------------------------
- -- CRC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
- * @{
- */
-
-
-/* CRC - Register instance definitions */
-/* CRC */
-#define CRC_DATA CRC_DATA_REG(CRC0)
-#define CRC_DATAL CRC_DATAL_REG(CRC0)
-#define CRC_DATALL CRC_DATALL_REG(CRC0)
-#define CRC_DATALU CRC_DATALU_REG(CRC0)
-#define CRC_DATAH CRC_DATAH_REG(CRC0)
-#define CRC_DATAHL CRC_DATAHL_REG(CRC0)
-#define CRC_DATAHU CRC_DATAHU_REG(CRC0)
-#define CRC_GPOLY CRC_GPOLY_REG(CRC0)
-#define CRC_GPOLYL CRC_GPOLYL_REG(CRC0)
-#define CRC_GPOLYLL CRC_GPOLYLL_REG(CRC0)
-#define CRC_GPOLYLU CRC_GPOLYLU_REG(CRC0)
-#define CRC_GPOLYH CRC_GPOLYH_REG(CRC0)
-#define CRC_GPOLYHL CRC_GPOLYHL_REG(CRC0)
-#define CRC_GPOLYHU CRC_GPOLYHU_REG(CRC0)
-#define CRC_CTRL CRC_CTRL_REG(CRC0)
-#define CRC_CTRLHU CRC_CTRLHU_REG(CRC0)
-
-/*!
- * @}
- */ /* end of group CRC_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group CRC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- DAC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
- * @{
- */
-
-/** DAC - Register Layout Typedef */
-typedef struct {
- struct { /* offset: 0x0, array step: 0x2 */
- __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
- __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
- } DAT[16];
- __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
- __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
- __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
- __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
-} DAC_Type, *DAC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- DAC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
- * @{
- */
-
-
-/* DAC - Register accessors */
-#define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
-#define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
-#define DAC_SR_REG(base) ((base)->SR)
-#define DAC_C0_REG(base) ((base)->C0)
-#define DAC_C1_REG(base) ((base)->C1)
-#define DAC_C2_REG(base) ((base)->C2)
-
-/*!
- * @}
- */ /* end of group DAC_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- DAC Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DAC_Register_Masks DAC Register Masks
- * @{
- */
-
-/* DATL Bit Fields */
-#define DAC_DATL_DATA0_MASK 0xFFu
-#define DAC_DATL_DATA0_SHIFT 0
-#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
-/* DATH Bit Fields */
-#define DAC_DATH_DATA1_MASK 0xFu
-#define DAC_DATH_DATA1_SHIFT 0
-#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
-/* SR Bit Fields */
-#define DAC_SR_DACBFRPBF_MASK 0x1u
-#define DAC_SR_DACBFRPBF_SHIFT 0
-#define DAC_SR_DACBFRPTF_MASK 0x2u
-#define DAC_SR_DACBFRPTF_SHIFT 1
-#define DAC_SR_DACBFWMF_MASK 0x4u
-#define DAC_SR_DACBFWMF_SHIFT 2
-/* C0 Bit Fields */
-#define DAC_C0_DACBBIEN_MASK 0x1u
-#define DAC_C0_DACBBIEN_SHIFT 0
-#define DAC_C0_DACBTIEN_MASK 0x2u
-#define DAC_C0_DACBTIEN_SHIFT 1
-#define DAC_C0_DACBWIEN_MASK 0x4u
-#define DAC_C0_DACBWIEN_SHIFT 2
-#define DAC_C0_LPEN_MASK 0x8u
-#define DAC_C0_LPEN_SHIFT 3
-#define DAC_C0_DACSWTRG_MASK 0x10u
-#define DAC_C0_DACSWTRG_SHIFT 4
-#define DAC_C0_DACTRGSEL_MASK 0x20u
-#define DAC_C0_DACTRGSEL_SHIFT 5
-#define DAC_C0_DACRFS_MASK 0x40u
-#define DAC_C0_DACRFS_SHIFT 6
-#define DAC_C0_DACEN_MASK 0x80u
-#define DAC_C0_DACEN_SHIFT 7
-/* C1 Bit Fields */
-#define DAC_C1_DACBFEN_MASK 0x1u
-#define DAC_C1_DACBFEN_SHIFT 0
-#define DAC_C1_DACBFMD_MASK 0x6u
-#define DAC_C1_DACBFMD_SHIFT 1
-#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
-#define DAC_C1_DACBFWM_MASK 0x18u
-#define DAC_C1_DACBFWM_SHIFT 3
-#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
-#define DAC_C1_DMAEN_MASK 0x80u
-#define DAC_C1_DMAEN_SHIFT 7
-/* C2 Bit Fields */
-#define DAC_C2_DACBFUP_MASK 0xFu
-#define DAC_C2_DACBFUP_SHIFT 0
-#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
-#define DAC_C2_DACBFRP_MASK 0xF0u
-#define DAC_C2_DACBFRP_SHIFT 4
-#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
-
-/*!
- * @}
- */ /* end of group DAC_Register_Masks */
-
-
-/* DAC - Peripheral instance base addresses */
-/** Peripheral DAC0 base address */
-#define DAC0_BASE (0x400CC000u)
-/** Peripheral DAC0 base pointer */
-#define DAC0 ((DAC_Type *)DAC0_BASE)
-#define DAC0_BASE_PTR (DAC0)
-/** Peripheral DAC1 base address */
-#define DAC1_BASE (0x400CD000u)
-/** Peripheral DAC1 base pointer */
-#define DAC1 ((DAC_Type *)DAC1_BASE)
-#define DAC1_BASE_PTR (DAC1)
-/** Array initializer of DAC peripheral base pointers */
-#define DAC_BASES { DAC0, DAC1 }
-
-/* ----------------------------------------------------------------------------
- -- DAC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
- * @{
- */
-
-
-/* DAC - Register instance definitions */
-/* DAC0 */
-#define DAC0_DAT0L DAC_DATL_REG(DAC0,0)
-#define DAC0_DAT0H DAC_DATH_REG(DAC0,0)
-#define DAC0_DAT1L DAC_DATL_REG(DAC0,1)
-#define DAC0_DAT1H DAC_DATH_REG(DAC0,1)
-#define DAC0_DAT2L DAC_DATL_REG(DAC0,2)
-#define DAC0_DAT2H DAC_DATH_REG(DAC0,2)
-#define DAC0_DAT3L DAC_DATL_REG(DAC0,3)
-#define DAC0_DAT3H DAC_DATH_REG(DAC0,3)
-#define DAC0_DAT4L DAC_DATL_REG(DAC0,4)
-#define DAC0_DAT4H DAC_DATH_REG(DAC0,4)
-#define DAC0_DAT5L DAC_DATL_REG(DAC0,5)
-#define DAC0_DAT5H DAC_DATH_REG(DAC0,5)
-#define DAC0_DAT6L DAC_DATL_REG(DAC0,6)
-#define DAC0_DAT6H DAC_DATH_REG(DAC0,6)
-#define DAC0_DAT7L DAC_DATL_REG(DAC0,7)
-#define DAC0_DAT7H DAC_DATH_REG(DAC0,7)
-#define DAC0_DAT8L DAC_DATL_REG(DAC0,8)
-#define DAC0_DAT8H DAC_DATH_REG(DAC0,8)
-#define DAC0_DAT9L DAC_DATL_REG(DAC0,9)
-#define DAC0_DAT9H DAC_DATH_REG(DAC0,9)
-#define DAC0_DAT10L DAC_DATL_REG(DAC0,10)
-#define DAC0_DAT10H DAC_DATH_REG(DAC0,10)
-#define DAC0_DAT11L DAC_DATL_REG(DAC0,11)
-#define DAC0_DAT11H DAC_DATH_REG(DAC0,11)
-#define DAC0_DAT12L DAC_DATL_REG(DAC0,12)
-#define DAC0_DAT12H DAC_DATH_REG(DAC0,12)
-#define DAC0_DAT13L DAC_DATL_REG(DAC0,13)
-#define DAC0_DAT13H DAC_DATH_REG(DAC0,13)
-#define DAC0_DAT14L DAC_DATL_REG(DAC0,14)
-#define DAC0_DAT14H DAC_DATH_REG(DAC0,14)
-#define DAC0_DAT15L DAC_DATL_REG(DAC0,15)
-#define DAC0_DAT15H DAC_DATH_REG(DAC0,15)
-#define DAC0_SR DAC_SR_REG(DAC0)
-#define DAC0_C0 DAC_C0_REG(DAC0)
-#define DAC0_C1 DAC_C1_REG(DAC0)
-#define DAC0_C2 DAC_C2_REG(DAC0)
-/* DAC1 */
-#define DAC1_DAT0L DAC_DATL_REG(DAC1,0)
-#define DAC1_DAT0H DAC_DATH_REG(DAC1,0)
-#define DAC1_DAT1L DAC_DATL_REG(DAC1,1)
-#define DAC1_DAT1H DAC_DATH_REG(DAC1,1)
-#define DAC1_DAT2L DAC_DATL_REG(DAC1,2)
-#define DAC1_DAT2H DAC_DATH_REG(DAC1,2)
-#define DAC1_DAT3L DAC_DATL_REG(DAC1,3)
-#define DAC1_DAT3H DAC_DATH_REG(DAC1,3)
-#define DAC1_DAT4L DAC_DATL_REG(DAC1,4)
-#define DAC1_DAT4H DAC_DATH_REG(DAC1,4)
-#define DAC1_DAT5L DAC_DATL_REG(DAC1,5)
-#define DAC1_DAT5H DAC_DATH_REG(DAC1,5)
-#define DAC1_DAT6L DAC_DATL_REG(DAC1,6)
-#define DAC1_DAT6H DAC_DATH_REG(DAC1,6)
-#define DAC1_DAT7L DAC_DATL_REG(DAC1,7)
-#define DAC1_DAT7H DAC_DATH_REG(DAC1,7)
-#define DAC1_DAT8L DAC_DATL_REG(DAC1,8)
-#define DAC1_DAT8H DAC_DATH_REG(DAC1,8)
-#define DAC1_DAT9L DAC_DATL_REG(DAC1,9)
-#define DAC1_DAT9H DAC_DATH_REG(DAC1,9)
-#define DAC1_DAT10L DAC_DATL_REG(DAC1,10)
-#define DAC1_DAT10H DAC_DATH_REG(DAC1,10)
-#define DAC1_DAT11L DAC_DATL_REG(DAC1,11)
-#define DAC1_DAT11H DAC_DATH_REG(DAC1,11)
-#define DAC1_DAT12L DAC_DATL_REG(DAC1,12)
-#define DAC1_DAT12H DAC_DATH_REG(DAC1,12)
-#define DAC1_DAT13L DAC_DATL_REG(DAC1,13)
-#define DAC1_DAT13H DAC_DATH_REG(DAC1,13)
-#define DAC1_DAT14L DAC_DATL_REG(DAC1,14)
-#define DAC1_DAT14H DAC_DATH_REG(DAC1,14)
-#define DAC1_DAT15L DAC_DATL_REG(DAC1,15)
-#define DAC1_DAT15H DAC_DATH_REG(DAC1,15)
-#define DAC1_SR DAC_SR_REG(DAC1)
-#define DAC1_C0 DAC_C0_REG(DAC1)
-#define DAC1_C1 DAC_C1_REG(DAC1)
-#define DAC1_C2 DAC_C2_REG(DAC1)
-
-/* DAC - Register array accessors */
-#define DAC0_DATL(index) DAC_DATL_REG(DAC0,index)
-#define DAC1_DATL(index) DAC_DATL_REG(DAC1,index)
-#define DAC0_DATH(index) DAC_DATH_REG(DAC0,index)
-#define DAC1_DATH(index) DAC_DATH_REG(DAC1,index)
-
-/*!
- * @}
- */ /* end of group DAC_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group DAC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- DMA Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
- * @{
- */
-
-/** DMA - Register Layout Typedef */
-typedef struct {
- __IO uint32_t CR; /**< Control Register, offset: 0x0 */
- __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
- uint8_t RESERVED_0[4];
- __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
- uint8_t RESERVED_1[4];
- __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
- __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
- __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
- __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
- __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
- __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
- __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
- __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
- __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
- uint8_t RESERVED_2[4];
- __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
- uint8_t RESERVED_3[4];
- __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
- uint8_t RESERVED_4[4];
- __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
- uint8_t RESERVED_5[200];
- __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
- __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
- __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
- __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
- __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
- __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
- __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
- __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
- __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
- __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
- __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
- __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
- __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
- __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
- __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
- __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
- uint8_t RESERVED_6[3824];
- struct { /* offset: 0x1000, array step: 0x20 */
- __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
- __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
- __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
- union { /* offset: 0x1008, array step: 0x20 */
- __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
- __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
- __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
- };
- __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
- __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
- __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
- union { /* offset: 0x1016, array step: 0x20 */
- __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
- __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
- };
- __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
- __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
- union { /* offset: 0x101E, array step: 0x20 */
- __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
- __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
- };
- } TCD[16];
-} DMA_Type, *DMA_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- DMA - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
- * @{
- */
-
-
-/* DMA - Register accessors */
-#define DMA_CR_REG(base) ((base)->CR)
-#define DMA_ES_REG(base) ((base)->ES)
-#define DMA_ERQ_REG(base) ((base)->ERQ)
-#define DMA_EEI_REG(base) ((base)->EEI)
-#define DMA_CEEI_REG(base) ((base)->CEEI)
-#define DMA_SEEI_REG(base) ((base)->SEEI)
-#define DMA_CERQ_REG(base) ((base)->CERQ)
-#define DMA_SERQ_REG(base) ((base)->SERQ)
-#define DMA_CDNE_REG(base) ((base)->CDNE)
-#define DMA_SSRT_REG(base) ((base)->SSRT)
-#define DMA_CERR_REG(base) ((base)->CERR)
-#define DMA_CINT_REG(base) ((base)->CINT)
-#define DMA_INT_REG(base) ((base)->INT)
-#define DMA_ERR_REG(base) ((base)->ERR)
-#define DMA_HRS_REG(base) ((base)->HRS)
-#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3)
-#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2)
-#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1)
-#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0)
-#define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7)
-#define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6)
-#define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5)
-#define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4)
-#define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11)
-#define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10)
-#define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9)
-#define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8)
-#define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15)
-#define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14)
-#define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13)
-#define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12)
-#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR)
-#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF)
-#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR)
-#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO)
-#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO)
-#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES)
-#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST)
-#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR)
-#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF)
-#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO)
-#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES)
-#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA)
-#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR)
-#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO)
-#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES)
-
-/*!
- * @}
- */ /* end of group DMA_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- DMA Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMA_Register_Masks DMA Register Masks
- * @{
- */
-
-/* CR Bit Fields */
-#define DMA_CR_EDBG_MASK 0x2u
-#define DMA_CR_EDBG_SHIFT 1
-#define DMA_CR_ERCA_MASK 0x4u
-#define DMA_CR_ERCA_SHIFT 2
-#define DMA_CR_HOE_MASK 0x10u
-#define DMA_CR_HOE_SHIFT 4
-#define DMA_CR_HALT_MASK 0x20u
-#define DMA_CR_HALT_SHIFT 5
-#define DMA_CR_CLM_MASK 0x40u
-#define DMA_CR_CLM_SHIFT 6
-#define DMA_CR_EMLM_MASK 0x80u
-#define DMA_CR_EMLM_SHIFT 7
-#define DMA_CR_ECX_MASK 0x10000u
-#define DMA_CR_ECX_SHIFT 16
-#define DMA_CR_CX_MASK 0x20000u
-#define DMA_CR_CX_SHIFT 17
-/* ES Bit Fields */
-#define DMA_ES_DBE_MASK 0x1u
-#define DMA_ES_DBE_SHIFT 0
-#define DMA_ES_SBE_MASK 0x2u
-#define DMA_ES_SBE_SHIFT 1
-#define DMA_ES_SGE_MASK 0x4u
-#define DMA_ES_SGE_SHIFT 2
-#define DMA_ES_NCE_MASK 0x8u
-#define DMA_ES_NCE_SHIFT 3
-#define DMA_ES_DOE_MASK 0x10u
-#define DMA_ES_DOE_SHIFT 4
-#define DMA_ES_DAE_MASK 0x20u
-#define DMA_ES_DAE_SHIFT 5
-#define DMA_ES_SOE_MASK 0x40u
-#define DMA_ES_SOE_SHIFT 6
-#define DMA_ES_SAE_MASK 0x80u
-#define DMA_ES_SAE_SHIFT 7
-#define DMA_ES_ERRCHN_MASK 0xF00u
-#define DMA_ES_ERRCHN_SHIFT 8
-#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
-#define DMA_ES_CPE_MASK 0x4000u
-#define DMA_ES_CPE_SHIFT 14
-#define DMA_ES_ECX_MASK 0x10000u
-#define DMA_ES_ECX_SHIFT 16
-#define DMA_ES_VLD_MASK 0x80000000u
-#define DMA_ES_VLD_SHIFT 31
-/* ERQ Bit Fields */
-#define DMA_ERQ_ERQ0_MASK 0x1u
-#define DMA_ERQ_ERQ0_SHIFT 0
-#define DMA_ERQ_ERQ1_MASK 0x2u
-#define DMA_ERQ_ERQ1_SHIFT 1
-#define DMA_ERQ_ERQ2_MASK 0x4u
-#define DMA_ERQ_ERQ2_SHIFT 2
-#define DMA_ERQ_ERQ3_MASK 0x8u
-#define DMA_ERQ_ERQ3_SHIFT 3
-#define DMA_ERQ_ERQ4_MASK 0x10u
-#define DMA_ERQ_ERQ4_SHIFT 4
-#define DMA_ERQ_ERQ5_MASK 0x20u
-#define DMA_ERQ_ERQ5_SHIFT 5
-#define DMA_ERQ_ERQ6_MASK 0x40u
-#define DMA_ERQ_ERQ6_SHIFT 6
-#define DMA_ERQ_ERQ7_MASK 0x80u
-#define DMA_ERQ_ERQ7_SHIFT 7
-#define DMA_ERQ_ERQ8_MASK 0x100u
-#define DMA_ERQ_ERQ8_SHIFT 8
-#define DMA_ERQ_ERQ9_MASK 0x200u
-#define DMA_ERQ_ERQ9_SHIFT 9
-#define DMA_ERQ_ERQ10_MASK 0x400u
-#define DMA_ERQ_ERQ10_SHIFT 10
-#define DMA_ERQ_ERQ11_MASK 0x800u
-#define DMA_ERQ_ERQ11_SHIFT 11
-#define DMA_ERQ_ERQ12_MASK 0x1000u
-#define DMA_ERQ_ERQ12_SHIFT 12
-#define DMA_ERQ_ERQ13_MASK 0x2000u
-#define DMA_ERQ_ERQ13_SHIFT 13
-#define DMA_ERQ_ERQ14_MASK 0x4000u
-#define DMA_ERQ_ERQ14_SHIFT 14
-#define DMA_ERQ_ERQ15_MASK 0x8000u
-#define DMA_ERQ_ERQ15_SHIFT 15
-/* EEI Bit Fields */
-#define DMA_EEI_EEI0_MASK 0x1u
-#define DMA_EEI_EEI0_SHIFT 0
-#define DMA_EEI_EEI1_MASK 0x2u
-#define DMA_EEI_EEI1_SHIFT 1
-#define DMA_EEI_EEI2_MASK 0x4u
-#define DMA_EEI_EEI2_SHIFT 2
-#define DMA_EEI_EEI3_MASK 0x8u
-#define DMA_EEI_EEI3_SHIFT 3
-#define DMA_EEI_EEI4_MASK 0x10u
-#define DMA_EEI_EEI4_SHIFT 4
-#define DMA_EEI_EEI5_MASK 0x20u
-#define DMA_EEI_EEI5_SHIFT 5
-#define DMA_EEI_EEI6_MASK 0x40u
-#define DMA_EEI_EEI6_SHIFT 6
-#define DMA_EEI_EEI7_MASK 0x80u
-#define DMA_EEI_EEI7_SHIFT 7
-#define DMA_EEI_EEI8_MASK 0x100u
-#define DMA_EEI_EEI8_SHIFT 8
-#define DMA_EEI_EEI9_MASK 0x200u
-#define DMA_EEI_EEI9_SHIFT 9
-#define DMA_EEI_EEI10_MASK 0x400u
-#define DMA_EEI_EEI10_SHIFT 10
-#define DMA_EEI_EEI11_MASK 0x800u
-#define DMA_EEI_EEI11_SHIFT 11
-#define DMA_EEI_EEI12_MASK 0x1000u
-#define DMA_EEI_EEI12_SHIFT 12
-#define DMA_EEI_EEI13_MASK 0x2000u
-#define DMA_EEI_EEI13_SHIFT 13
-#define DMA_EEI_EEI14_MASK 0x4000u
-#define DMA_EEI_EEI14_SHIFT 14
-#define DMA_EEI_EEI15_MASK 0x8000u
-#define DMA_EEI_EEI15_SHIFT 15
-/* CEEI Bit Fields */
-#define DMA_CEEI_CEEI_MASK 0xFu
-#define DMA_CEEI_CEEI_SHIFT 0
-#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
-#define DMA_CEEI_CAEE_MASK 0x40u
-#define DMA_CEEI_CAEE_SHIFT 6
-#define DMA_CEEI_NOP_MASK 0x80u
-#define DMA_CEEI_NOP_SHIFT 7
-/* SEEI Bit Fields */
-#define DMA_SEEI_SEEI_MASK 0xFu
-#define DMA_SEEI_SEEI_SHIFT 0
-#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
-#define DMA_SEEI_SAEE_MASK 0x40u
-#define DMA_SEEI_SAEE_SHIFT 6
-#define DMA_SEEI_NOP_MASK 0x80u
-#define DMA_SEEI_NOP_SHIFT 7
-/* CERQ Bit Fields */
-#define DMA_CERQ_CERQ_MASK 0xFu
-#define DMA_CERQ_CERQ_SHIFT 0
-#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
-#define DMA_CERQ_CAER_MASK 0x40u
-#define DMA_CERQ_CAER_SHIFT 6
-#define DMA_CERQ_NOP_MASK 0x80u
-#define DMA_CERQ_NOP_SHIFT 7
-/* SERQ Bit Fields */
-#define DMA_SERQ_SERQ_MASK 0xFu
-#define DMA_SERQ_SERQ_SHIFT 0
-#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
-#define DMA_SERQ_SAER_MASK 0x40u
-#define DMA_SERQ_SAER_SHIFT 6
-#define DMA_SERQ_NOP_MASK 0x80u
-#define DMA_SERQ_NOP_SHIFT 7
-/* CDNE Bit Fields */
-#define DMA_CDNE_CDNE_MASK 0xFu
-#define DMA_CDNE_CDNE_SHIFT 0
-#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
-#define DMA_CDNE_CADN_MASK 0x40u
-#define DMA_CDNE_CADN_SHIFT 6
-#define DMA_CDNE_NOP_MASK 0x80u
-#define DMA_CDNE_NOP_SHIFT 7
-/* SSRT Bit Fields */
-#define DMA_SSRT_SSRT_MASK 0xFu
-#define DMA_SSRT_SSRT_SHIFT 0
-#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
-#define DMA_SSRT_SAST_MASK 0x40u
-#define DMA_SSRT_SAST_SHIFT 6
-#define DMA_SSRT_NOP_MASK 0x80u
-#define DMA_SSRT_NOP_SHIFT 7
-/* CERR Bit Fields */
-#define DMA_CERR_CERR_MASK 0xFu
-#define DMA_CERR_CERR_SHIFT 0
-#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
-#define DMA_CERR_CAEI_MASK 0x40u
-#define DMA_CERR_CAEI_SHIFT 6
-#define DMA_CERR_NOP_MASK 0x80u
-#define DMA_CERR_NOP_SHIFT 7
-/* CINT Bit Fields */
-#define DMA_CINT_CINT_MASK 0xFu
-#define DMA_CINT_CINT_SHIFT 0
-#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
-#define DMA_CINT_CAIR_MASK 0x40u
-#define DMA_CINT_CAIR_SHIFT 6
-#define DMA_CINT_NOP_MASK 0x80u
-#define DMA_CINT_NOP_SHIFT 7
-/* INT Bit Fields */
-#define DMA_INT_INT0_MASK 0x1u
-#define DMA_INT_INT0_SHIFT 0
-#define DMA_INT_INT1_MASK 0x2u
-#define DMA_INT_INT1_SHIFT 1
-#define DMA_INT_INT2_MASK 0x4u
-#define DMA_INT_INT2_SHIFT 2
-#define DMA_INT_INT3_MASK 0x8u
-#define DMA_INT_INT3_SHIFT 3
-#define DMA_INT_INT4_MASK 0x10u
-#define DMA_INT_INT4_SHIFT 4
-#define DMA_INT_INT5_MASK 0x20u
-#define DMA_INT_INT5_SHIFT 5
-#define DMA_INT_INT6_MASK 0x40u
-#define DMA_INT_INT6_SHIFT 6
-#define DMA_INT_INT7_MASK 0x80u
-#define DMA_INT_INT7_SHIFT 7
-#define DMA_INT_INT8_MASK 0x100u
-#define DMA_INT_INT8_SHIFT 8
-#define DMA_INT_INT9_MASK 0x200u
-#define DMA_INT_INT9_SHIFT 9
-#define DMA_INT_INT10_MASK 0x400u
-#define DMA_INT_INT10_SHIFT 10
-#define DMA_INT_INT11_MASK 0x800u
-#define DMA_INT_INT11_SHIFT 11
-#define DMA_INT_INT12_MASK 0x1000u
-#define DMA_INT_INT12_SHIFT 12
-#define DMA_INT_INT13_MASK 0x2000u
-#define DMA_INT_INT13_SHIFT 13
-#define DMA_INT_INT14_MASK 0x4000u
-#define DMA_INT_INT14_SHIFT 14
-#define DMA_INT_INT15_MASK 0x8000u
-#define DMA_INT_INT15_SHIFT 15
-/* ERR Bit Fields */
-#define DMA_ERR_ERR0_MASK 0x1u
-#define DMA_ERR_ERR0_SHIFT 0
-#define DMA_ERR_ERR1_MASK 0x2u
-#define DMA_ERR_ERR1_SHIFT 1
-#define DMA_ERR_ERR2_MASK 0x4u
-#define DMA_ERR_ERR2_SHIFT 2
-#define DMA_ERR_ERR3_MASK 0x8u
-#define DMA_ERR_ERR3_SHIFT 3
-#define DMA_ERR_ERR4_MASK 0x10u
-#define DMA_ERR_ERR4_SHIFT 4
-#define DMA_ERR_ERR5_MASK 0x20u
-#define DMA_ERR_ERR5_SHIFT 5
-#define DMA_ERR_ERR6_MASK 0x40u
-#define DMA_ERR_ERR6_SHIFT 6
-#define DMA_ERR_ERR7_MASK 0x80u
-#define DMA_ERR_ERR7_SHIFT 7
-#define DMA_ERR_ERR8_MASK 0x100u
-#define DMA_ERR_ERR8_SHIFT 8
-#define DMA_ERR_ERR9_MASK 0x200u
-#define DMA_ERR_ERR9_SHIFT 9
-#define DMA_ERR_ERR10_MASK 0x400u
-#define DMA_ERR_ERR10_SHIFT 10
-#define DMA_ERR_ERR11_MASK 0x800u
-#define DMA_ERR_ERR11_SHIFT 11
-#define DMA_ERR_ERR12_MASK 0x1000u
-#define DMA_ERR_ERR12_SHIFT 12
-#define DMA_ERR_ERR13_MASK 0x2000u
-#define DMA_ERR_ERR13_SHIFT 13
-#define DMA_ERR_ERR14_MASK 0x4000u
-#define DMA_ERR_ERR14_SHIFT 14
-#define DMA_ERR_ERR15_MASK 0x8000u
-#define DMA_ERR_ERR15_SHIFT 15
-/* HRS Bit Fields */
-#define DMA_HRS_HRS0_MASK 0x1u
-#define DMA_HRS_HRS0_SHIFT 0
-#define DMA_HRS_HRS1_MASK 0x2u
-#define DMA_HRS_HRS1_SHIFT 1
-#define DMA_HRS_HRS2_MASK 0x4u
-#define DMA_HRS_HRS2_SHIFT 2
-#define DMA_HRS_HRS3_MASK 0x8u
-#define DMA_HRS_HRS3_SHIFT 3
-#define DMA_HRS_HRS4_MASK 0x10u
-#define DMA_HRS_HRS4_SHIFT 4
-#define DMA_HRS_HRS5_MASK 0x20u
-#define DMA_HRS_HRS5_SHIFT 5
-#define DMA_HRS_HRS6_MASK 0x40u
-#define DMA_HRS_HRS6_SHIFT 6
-#define DMA_HRS_HRS7_MASK 0x80u
-#define DMA_HRS_HRS7_SHIFT 7
-#define DMA_HRS_HRS8_MASK 0x100u
-#define DMA_HRS_HRS8_SHIFT 8
-#define DMA_HRS_HRS9_MASK 0x200u
-#define DMA_HRS_HRS9_SHIFT 9
-#define DMA_HRS_HRS10_MASK 0x400u
-#define DMA_HRS_HRS10_SHIFT 10
-#define DMA_HRS_HRS11_MASK 0x800u
-#define DMA_HRS_HRS11_SHIFT 11
-#define DMA_HRS_HRS12_MASK 0x1000u
-#define DMA_HRS_HRS12_SHIFT 12
-#define DMA_HRS_HRS13_MASK 0x2000u
-#define DMA_HRS_HRS13_SHIFT 13
-#define DMA_HRS_HRS14_MASK 0x4000u
-#define DMA_HRS_HRS14_SHIFT 14
-#define DMA_HRS_HRS15_MASK 0x8000u
-#define DMA_HRS_HRS15_SHIFT 15
-/* DCHPRI3 Bit Fields */
-#define DMA_DCHPRI3_CHPRI_MASK 0xFu
-#define DMA_DCHPRI3_CHPRI_SHIFT 0
-#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
-#define DMA_DCHPRI3_DPA_MASK 0x40u
-#define DMA_DCHPRI3_DPA_SHIFT 6
-#define DMA_DCHPRI3_ECP_MASK 0x80u
-#define DMA_DCHPRI3_ECP_SHIFT 7
-/* DCHPRI2 Bit Fields */
-#define DMA_DCHPRI2_CHPRI_MASK 0xFu
-#define DMA_DCHPRI2_CHPRI_SHIFT 0
-#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
-#define DMA_DCHPRI2_DPA_MASK 0x40u
-#define DMA_DCHPRI2_DPA_SHIFT 6
-#define DMA_DCHPRI2_ECP_MASK 0x80u
-#define DMA_DCHPRI2_ECP_SHIFT 7
-/* DCHPRI1 Bit Fields */
-#define DMA_DCHPRI1_CHPRI_MASK 0xFu
-#define DMA_DCHPRI1_CHPRI_SHIFT 0
-#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
-#define DMA_DCHPRI1_DPA_MASK 0x40u
-#define DMA_DCHPRI1_DPA_SHIFT 6
-#define DMA_DCHPRI1_ECP_MASK 0x80u
-#define DMA_DCHPRI1_ECP_SHIFT 7
-/* DCHPRI0 Bit Fields */
-#define DMA_DCHPRI0_CHPRI_MASK 0xFu
-#define DMA_DCHPRI0_CHPRI_SHIFT 0
-#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
-#define DMA_DCHPRI0_DPA_MASK 0x40u
-#define DMA_DCHPRI0_DPA_SHIFT 6
-#define DMA_DCHPRI0_ECP_MASK 0x80u
-#define DMA_DCHPRI0_ECP_SHIFT 7
-/* DCHPRI7 Bit Fields */
-#define DMA_DCHPRI7_CHPRI_MASK 0xFu
-#define DMA_DCHPRI7_CHPRI_SHIFT 0
-#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
-#define DMA_DCHPRI7_DPA_MASK 0x40u
-#define DMA_DCHPRI7_DPA_SHIFT 6
-#define DMA_DCHPRI7_ECP_MASK 0x80u
-#define DMA_DCHPRI7_ECP_SHIFT 7
-/* DCHPRI6 Bit Fields */
-#define DMA_DCHPRI6_CHPRI_MASK 0xFu
-#define DMA_DCHPRI6_CHPRI_SHIFT 0
-#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
-#define DMA_DCHPRI6_DPA_MASK 0x40u
-#define DMA_DCHPRI6_DPA_SHIFT 6
-#define DMA_DCHPRI6_ECP_MASK 0x80u
-#define DMA_DCHPRI6_ECP_SHIFT 7
-/* DCHPRI5 Bit Fields */
-#define DMA_DCHPRI5_CHPRI_MASK 0xFu
-#define DMA_DCHPRI5_CHPRI_SHIFT 0
-#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
-#define DMA_DCHPRI5_DPA_MASK 0x40u
-#define DMA_DCHPRI5_DPA_SHIFT 6
-#define DMA_DCHPRI5_ECP_MASK 0x80u
-#define DMA_DCHPRI5_ECP_SHIFT 7
-/* DCHPRI4 Bit Fields */
-#define DMA_DCHPRI4_CHPRI_MASK 0xFu
-#define DMA_DCHPRI4_CHPRI_SHIFT 0
-#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
-#define DMA_DCHPRI4_DPA_MASK 0x40u
-#define DMA_DCHPRI4_DPA_SHIFT 6
-#define DMA_DCHPRI4_ECP_MASK 0x80u
-#define DMA_DCHPRI4_ECP_SHIFT 7
-/* DCHPRI11 Bit Fields */
-#define DMA_DCHPRI11_CHPRI_MASK 0xFu
-#define DMA_DCHPRI11_CHPRI_SHIFT 0
-#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
-#define DMA_DCHPRI11_DPA_MASK 0x40u
-#define DMA_DCHPRI11_DPA_SHIFT 6
-#define DMA_DCHPRI11_ECP_MASK 0x80u
-#define DMA_DCHPRI11_ECP_SHIFT 7
-/* DCHPRI10 Bit Fields */
-#define DMA_DCHPRI10_CHPRI_MASK 0xFu
-#define DMA_DCHPRI10_CHPRI_SHIFT 0
-#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
-#define DMA_DCHPRI10_DPA_MASK 0x40u
-#define DMA_DCHPRI10_DPA_SHIFT 6
-#define DMA_DCHPRI10_ECP_MASK 0x80u
-#define DMA_DCHPRI10_ECP_SHIFT 7
-/* DCHPRI9 Bit Fields */
-#define DMA_DCHPRI9_CHPRI_MASK 0xFu
-#define DMA_DCHPRI9_CHPRI_SHIFT 0
-#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
-#define DMA_DCHPRI9_DPA_MASK 0x40u
-#define DMA_DCHPRI9_DPA_SHIFT 6
-#define DMA_DCHPRI9_ECP_MASK 0x80u
-#define DMA_DCHPRI9_ECP_SHIFT 7
-/* DCHPRI8 Bit Fields */
-#define DMA_DCHPRI8_CHPRI_MASK 0xFu
-#define DMA_DCHPRI8_CHPRI_SHIFT 0
-#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
-#define DMA_DCHPRI8_DPA_MASK 0x40u
-#define DMA_DCHPRI8_DPA_SHIFT 6
-#define DMA_DCHPRI8_ECP_MASK 0x80u
-#define DMA_DCHPRI8_ECP_SHIFT 7
-/* DCHPRI15 Bit Fields */
-#define DMA_DCHPRI15_CHPRI_MASK 0xFu
-#define DMA_DCHPRI15_CHPRI_SHIFT 0
-#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
-#define DMA_DCHPRI15_DPA_MASK 0x40u
-#define DMA_DCHPRI15_DPA_SHIFT 6
-#define DMA_DCHPRI15_ECP_MASK 0x80u
-#define DMA_DCHPRI15_ECP_SHIFT 7
-/* DCHPRI14 Bit Fields */
-#define DMA_DCHPRI14_CHPRI_MASK 0xFu
-#define DMA_DCHPRI14_CHPRI_SHIFT 0
-#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
-#define DMA_DCHPRI14_DPA_MASK 0x40u
-#define DMA_DCHPRI14_DPA_SHIFT 6
-#define DMA_DCHPRI14_ECP_MASK 0x80u
-#define DMA_DCHPRI14_ECP_SHIFT 7
-/* DCHPRI13 Bit Fields */
-#define DMA_DCHPRI13_CHPRI_MASK 0xFu
-#define DMA_DCHPRI13_CHPRI_SHIFT 0
-#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
-#define DMA_DCHPRI13_DPA_MASK 0x40u
-#define DMA_DCHPRI13_DPA_SHIFT 6
-#define DMA_DCHPRI13_ECP_MASK 0x80u
-#define DMA_DCHPRI13_ECP_SHIFT 7
-/* DCHPRI12 Bit Fields */
-#define DMA_DCHPRI12_CHPRI_MASK 0xFu
-#define DMA_DCHPRI12_CHPRI_SHIFT 0
-#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
-#define DMA_DCHPRI12_DPA_MASK 0x40u
-#define DMA_DCHPRI12_DPA_SHIFT 6
-#define DMA_DCHPRI12_ECP_MASK 0x80u
-#define DMA_DCHPRI12_ECP_SHIFT 7
-/* SADDR Bit Fields */
-#define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
-#define DMA_SADDR_SADDR_SHIFT 0
-#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
-/* SOFF Bit Fields */
-#define DMA_SOFF_SOFF_MASK 0xFFFFu
-#define DMA_SOFF_SOFF_SHIFT 0
-#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
-/* ATTR Bit Fields */
-#define DMA_ATTR_DSIZE_MASK 0x7u
-#define DMA_ATTR_DSIZE_SHIFT 0
-#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
-#define DMA_ATTR_DMOD_MASK 0xF8u
-#define DMA_ATTR_DMOD_SHIFT 3
-#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
-#define DMA_ATTR_SSIZE_MASK 0x700u
-#define DMA_ATTR_SSIZE_SHIFT 8
-#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
-#define DMA_ATTR_SMOD_MASK 0xF800u
-#define DMA_ATTR_SMOD_SHIFT 11
-#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
-/* NBYTES_MLNO Bit Fields */
-#define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
-#define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
-#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
-/* NBYTES_MLOFFNO Bit Fields */
-#define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
-#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
-#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
-#define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
-#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
-#define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
-#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
-/* NBYTES_MLOFFYES Bit Fields */
-#define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
-#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
-#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
-#define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
-#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
-#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
-#define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
-#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
-#define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
-#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
-/* SLAST Bit Fields */
-#define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
-#define DMA_SLAST_SLAST_SHIFT 0
-#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
-/* DADDR Bit Fields */
-#define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
-#define DMA_DADDR_DADDR_SHIFT 0
-#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
-/* DOFF Bit Fields */
-#define DMA_DOFF_DOFF_MASK 0xFFFFu
-#define DMA_DOFF_DOFF_SHIFT 0
-#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
-/* CITER_ELINKNO Bit Fields */
-#define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
-#define DMA_CITER_ELINKNO_CITER_SHIFT 0
-#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
-#define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
-#define DMA_CITER_ELINKNO_ELINK_SHIFT 15
-/* CITER_ELINKYES Bit Fields */
-#define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
-#define DMA_CITER_ELINKYES_CITER_SHIFT 0
-#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
-#define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
-#define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
-#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
-#define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
-#define DMA_CITER_ELINKYES_ELINK_SHIFT 15
-/* DLAST_SGA Bit Fields */
-#define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
-#define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
-#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
-/* CSR Bit Fields */
-#define DMA_CSR_START_MASK 0x1u
-#define DMA_CSR_START_SHIFT 0
-#define DMA_CSR_INTMAJOR_MASK 0x2u
-#define DMA_CSR_INTMAJOR_SHIFT 1
-#define DMA_CSR_INTHALF_MASK 0x4u
-#define DMA_CSR_INTHALF_SHIFT 2
-#define DMA_CSR_DREQ_MASK 0x8u
-#define DMA_CSR_DREQ_SHIFT 3
-#define DMA_CSR_ESG_MASK 0x10u
-#define DMA_CSR_ESG_SHIFT 4
-#define DMA_CSR_MAJORELINK_MASK 0x20u
-#define DMA_CSR_MAJORELINK_SHIFT 5
-#define DMA_CSR_ACTIVE_MASK 0x40u
-#define DMA_CSR_ACTIVE_SHIFT 6
-#define DMA_CSR_DONE_MASK 0x80u
-#define DMA_CSR_DONE_SHIFT 7
-#define DMA_CSR_MAJORLINKCH_MASK 0xF00u
-#define DMA_CSR_MAJORLINKCH_SHIFT 8
-#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
-#define DMA_CSR_BWC_MASK 0xC000u
-#define DMA_CSR_BWC_SHIFT 14
-#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
-/* BITER_ELINKNO Bit Fields */
-#define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
-#define DMA_BITER_ELINKNO_BITER_SHIFT 0
-#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
-#define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
-#define DMA_BITER_ELINKNO_ELINK_SHIFT 15
-/* BITER_ELINKYES Bit Fields */
-#define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
-#define DMA_BITER_ELINKYES_BITER_SHIFT 0
-#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
-#define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
-#define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
-#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
-#define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
-#define DMA_BITER_ELINKYES_ELINK_SHIFT 15
-
-/*!
- * @}
- */ /* end of group DMA_Register_Masks */
-
-
-/* DMA - Peripheral instance base addresses */
-/** Peripheral DMA base address */
-#define DMA_BASE (0x40008000u)
-/** Peripheral DMA base pointer */
-#define DMA0 ((DMA_Type *)DMA_BASE)
-#define DMA_BASE_PTR (DMA0)
-/** Array initializer of DMA peripheral base pointers */
-#define DMA_BASES { DMA0 }
-
-/* ----------------------------------------------------------------------------
- -- DMA - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
- * @{
- */
-
-
-/* DMA - Register instance definitions */
-/* DMA */
-#define DMA_CR DMA_CR_REG(DMA0)
-#define DMA_ES DMA_ES_REG(DMA0)
-#define DMA_ERQ DMA_ERQ_REG(DMA0)
-#define DMA_EEI DMA_EEI_REG(DMA0)
-#define DMA_CEEI DMA_CEEI_REG(DMA0)
-#define DMA_SEEI DMA_SEEI_REG(DMA0)
-#define DMA_CERQ DMA_CERQ_REG(DMA0)
-#define DMA_SERQ DMA_SERQ_REG(DMA0)
-#define DMA_CDNE DMA_CDNE_REG(DMA0)
-#define DMA_SSRT DMA_SSRT_REG(DMA0)
-#define DMA_CERR DMA_CERR_REG(DMA0)
-#define DMA_CINT DMA_CINT_REG(DMA0)
-#define DMA_INT DMA_INT_REG(DMA0)
-#define DMA_ERR DMA_ERR_REG(DMA0)
-#define DMA_HRS DMA_HRS_REG(DMA0)
-#define DMA_DCHPRI3 DMA_DCHPRI3_REG(DMA0)
-#define DMA_DCHPRI2 DMA_DCHPRI2_REG(DMA0)
-#define DMA_DCHPRI1 DMA_DCHPRI1_REG(DMA0)
-#define DMA_DCHPRI0 DMA_DCHPRI0_REG(DMA0)
-#define DMA_DCHPRI7 DMA_DCHPRI7_REG(DMA0)
-#define DMA_DCHPRI6 DMA_DCHPRI6_REG(DMA0)
-#define DMA_DCHPRI5 DMA_DCHPRI5_REG(DMA0)
-#define DMA_DCHPRI4 DMA_DCHPRI4_REG(DMA0)
-#define DMA_DCHPRI11 DMA_DCHPRI11_REG(DMA0)
-#define DMA_DCHPRI10 DMA_DCHPRI10_REG(DMA0)
-#define DMA_DCHPRI9 DMA_DCHPRI9_REG(DMA0)
-#define DMA_DCHPRI8 DMA_DCHPRI8_REG(DMA0)
-#define DMA_DCHPRI15 DMA_DCHPRI15_REG(DMA0)
-#define DMA_DCHPRI14 DMA_DCHPRI14_REG(DMA0)
-#define DMA_DCHPRI13 DMA_DCHPRI13_REG(DMA0)
-#define DMA_DCHPRI12 DMA_DCHPRI12_REG(DMA0)
-#define DMA_TCD0_SADDR DMA_SADDR_REG(DMA0,0)
-#define DMA_TCD0_SOFF DMA_SOFF_REG(DMA0,0)
-#define DMA_TCD0_ATTR DMA_ATTR_REG(DMA0,0)
-#define DMA_TCD0_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,0)
-#define DMA_TCD0_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,0)
-#define DMA_TCD0_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,0)
-#define DMA_TCD0_SLAST DMA_SLAST_REG(DMA0,0)
-#define DMA_TCD0_DADDR DMA_DADDR_REG(DMA0,0)
-#define DMA_TCD0_DOFF DMA_DOFF_REG(DMA0,0)
-#define DMA_TCD0_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,0)
-#define DMA_TCD0_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,0)
-#define DMA_TCD0_DLASTSGA DMA_DLAST_SGA_REG(DMA0,0)
-#define DMA_TCD0_CSR DMA_CSR_REG(DMA0,0)
-#define DMA_TCD0_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,0)
-#define DMA_TCD0_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,0)
-#define DMA_TCD1_SADDR DMA_SADDR_REG(DMA0,1)
-#define DMA_TCD1_SOFF DMA_SOFF_REG(DMA0,1)
-#define DMA_TCD1_ATTR DMA_ATTR_REG(DMA0,1)
-#define DMA_TCD1_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,1)
-#define DMA_TCD1_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,1)
-#define DMA_TCD1_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,1)
-#define DMA_TCD1_SLAST DMA_SLAST_REG(DMA0,1)
-#define DMA_TCD1_DADDR DMA_DADDR_REG(DMA0,1)
-#define DMA_TCD1_DOFF DMA_DOFF_REG(DMA0,1)
-#define DMA_TCD1_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,1)
-#define DMA_TCD1_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,1)
-#define DMA_TCD1_DLASTSGA DMA_DLAST_SGA_REG(DMA0,1)
-#define DMA_TCD1_CSR DMA_CSR_REG(DMA0,1)
-#define DMA_TCD1_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,1)
-#define DMA_TCD1_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,1)
-#define DMA_TCD2_SADDR DMA_SADDR_REG(DMA0,2)
-#define DMA_TCD2_SOFF DMA_SOFF_REG(DMA0,2)
-#define DMA_TCD2_ATTR DMA_ATTR_REG(DMA0,2)
-#define DMA_TCD2_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,2)
-#define DMA_TCD2_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,2)
-#define DMA_TCD2_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,2)
-#define DMA_TCD2_SLAST DMA_SLAST_REG(DMA0,2)
-#define DMA_TCD2_DADDR DMA_DADDR_REG(DMA0,2)
-#define DMA_TCD2_DOFF DMA_DOFF_REG(DMA0,2)
-#define DMA_TCD2_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,2)
-#define DMA_TCD2_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,2)
-#define DMA_TCD2_DLASTSGA DMA_DLAST_SGA_REG(DMA0,2)
-#define DMA_TCD2_CSR DMA_CSR_REG(DMA0,2)
-#define DMA_TCD2_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,2)
-#define DMA_TCD2_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,2)
-#define DMA_TCD3_SADDR DMA_SADDR_REG(DMA0,3)
-#define DMA_TCD3_SOFF DMA_SOFF_REG(DMA0,3)
-#define DMA_TCD3_ATTR DMA_ATTR_REG(DMA0,3)
-#define DMA_TCD3_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,3)
-#define DMA_TCD3_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,3)
-#define DMA_TCD3_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,3)
-#define DMA_TCD3_SLAST DMA_SLAST_REG(DMA0,3)
-#define DMA_TCD3_DADDR DMA_DADDR_REG(DMA0,3)
-#define DMA_TCD3_DOFF DMA_DOFF_REG(DMA0,3)
-#define DMA_TCD3_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,3)
-#define DMA_TCD3_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,3)
-#define DMA_TCD3_DLASTSGA DMA_DLAST_SGA_REG(DMA0,3)
-#define DMA_TCD3_CSR DMA_CSR_REG(DMA0,3)
-#define DMA_TCD3_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,3)
-#define DMA_TCD3_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,3)
-#define DMA_TCD4_SADDR DMA_SADDR_REG(DMA0,4)
-#define DMA_TCD4_SOFF DMA_SOFF_REG(DMA0,4)
-#define DMA_TCD4_ATTR DMA_ATTR_REG(DMA0,4)
-#define DMA_TCD4_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,4)
-#define DMA_TCD4_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,4)
-#define DMA_TCD4_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,4)
-#define DMA_TCD4_SLAST DMA_SLAST_REG(DMA0,4)
-#define DMA_TCD4_DADDR DMA_DADDR_REG(DMA0,4)
-#define DMA_TCD4_DOFF DMA_DOFF_REG(DMA0,4)
-#define DMA_TCD4_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,4)
-#define DMA_TCD4_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,4)
-#define DMA_TCD4_DLASTSGA DMA_DLAST_SGA_REG(DMA0,4)
-#define DMA_TCD4_CSR DMA_CSR_REG(DMA0,4)
-#define DMA_TCD4_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,4)
-#define DMA_TCD4_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,4)
-#define DMA_TCD5_SADDR DMA_SADDR_REG(DMA0,5)
-#define DMA_TCD5_SOFF DMA_SOFF_REG(DMA0,5)
-#define DMA_TCD5_ATTR DMA_ATTR_REG(DMA0,5)
-#define DMA_TCD5_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,5)
-#define DMA_TCD5_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,5)
-#define DMA_TCD5_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,5)
-#define DMA_TCD5_SLAST DMA_SLAST_REG(DMA0,5)
-#define DMA_TCD5_DADDR DMA_DADDR_REG(DMA0,5)
-#define DMA_TCD5_DOFF DMA_DOFF_REG(DMA0,5)
-#define DMA_TCD5_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,5)
-#define DMA_TCD5_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,5)
-#define DMA_TCD5_DLASTSGA DMA_DLAST_SGA_REG(DMA0,5)
-#define DMA_TCD5_CSR DMA_CSR_REG(DMA0,5)
-#define DMA_TCD5_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,5)
-#define DMA_TCD5_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,5)
-#define DMA_TCD6_SADDR DMA_SADDR_REG(DMA0,6)
-#define DMA_TCD6_SOFF DMA_SOFF_REG(DMA0,6)
-#define DMA_TCD6_ATTR DMA_ATTR_REG(DMA0,6)
-#define DMA_TCD6_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,6)
-#define DMA_TCD6_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,6)
-#define DMA_TCD6_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,6)
-#define DMA_TCD6_SLAST DMA_SLAST_REG(DMA0,6)
-#define DMA_TCD6_DADDR DMA_DADDR_REG(DMA0,6)
-#define DMA_TCD6_DOFF DMA_DOFF_REG(DMA0,6)
-#define DMA_TCD6_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,6)
-#define DMA_TCD6_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,6)
-#define DMA_TCD6_DLASTSGA DMA_DLAST_SGA_REG(DMA0,6)
-#define DMA_TCD6_CSR DMA_CSR_REG(DMA0,6)
-#define DMA_TCD6_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,6)
-#define DMA_TCD6_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,6)
-#define DMA_TCD7_SADDR DMA_SADDR_REG(DMA0,7)
-#define DMA_TCD7_SOFF DMA_SOFF_REG(DMA0,7)
-#define DMA_TCD7_ATTR DMA_ATTR_REG(DMA0,7)
-#define DMA_TCD7_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,7)
-#define DMA_TCD7_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,7)
-#define DMA_TCD7_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,7)
-#define DMA_TCD7_SLAST DMA_SLAST_REG(DMA0,7)
-#define DMA_TCD7_DADDR DMA_DADDR_REG(DMA0,7)
-#define DMA_TCD7_DOFF DMA_DOFF_REG(DMA0,7)
-#define DMA_TCD7_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,7)
-#define DMA_TCD7_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,7)
-#define DMA_TCD7_DLASTSGA DMA_DLAST_SGA_REG(DMA0,7)
-#define DMA_TCD7_CSR DMA_CSR_REG(DMA0,7)
-#define DMA_TCD7_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,7)
-#define DMA_TCD7_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,7)
-#define DMA_TCD8_SADDR DMA_SADDR_REG(DMA0,8)
-#define DMA_TCD8_SOFF DMA_SOFF_REG(DMA0,8)
-#define DMA_TCD8_ATTR DMA_ATTR_REG(DMA0,8)
-#define DMA_TCD8_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,8)
-#define DMA_TCD8_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,8)
-#define DMA_TCD8_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,8)
-#define DMA_TCD8_SLAST DMA_SLAST_REG(DMA0,8)
-#define DMA_TCD8_DADDR DMA_DADDR_REG(DMA0,8)
-#define DMA_TCD8_DOFF DMA_DOFF_REG(DMA0,8)
-#define DMA_TCD8_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,8)
-#define DMA_TCD8_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,8)
-#define DMA_TCD8_DLASTSGA DMA_DLAST_SGA_REG(DMA0,8)
-#define DMA_TCD8_CSR DMA_CSR_REG(DMA0,8)
-#define DMA_TCD8_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,8)
-#define DMA_TCD8_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,8)
-#define DMA_TCD9_SADDR DMA_SADDR_REG(DMA0,9)
-#define DMA_TCD9_SOFF DMA_SOFF_REG(DMA0,9)
-#define DMA_TCD9_ATTR DMA_ATTR_REG(DMA0,9)
-#define DMA_TCD9_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,9)
-#define DMA_TCD9_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,9)
-#define DMA_TCD9_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,9)
-#define DMA_TCD9_SLAST DMA_SLAST_REG(DMA0,9)
-#define DMA_TCD9_DADDR DMA_DADDR_REG(DMA0,9)
-#define DMA_TCD9_DOFF DMA_DOFF_REG(DMA0,9)
-#define DMA_TCD9_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,9)
-#define DMA_TCD9_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,9)
-#define DMA_TCD9_DLASTSGA DMA_DLAST_SGA_REG(DMA0,9)
-#define DMA_TCD9_CSR DMA_CSR_REG(DMA0,9)
-#define DMA_TCD9_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,9)
-#define DMA_TCD9_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,9)
-#define DMA_TCD10_SADDR DMA_SADDR_REG(DMA0,10)
-#define DMA_TCD10_SOFF DMA_SOFF_REG(DMA0,10)
-#define DMA_TCD10_ATTR DMA_ATTR_REG(DMA0,10)
-#define DMA_TCD10_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,10)
-#define DMA_TCD10_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,10)
-#define DMA_TCD10_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,10)
-#define DMA_TCD10_SLAST DMA_SLAST_REG(DMA0,10)
-#define DMA_TCD10_DADDR DMA_DADDR_REG(DMA0,10)
-#define DMA_TCD10_DOFF DMA_DOFF_REG(DMA0,10)
-#define DMA_TCD10_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,10)
-#define DMA_TCD10_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,10)
-#define DMA_TCD10_DLASTSGA DMA_DLAST_SGA_REG(DMA0,10)
-#define DMA_TCD10_CSR DMA_CSR_REG(DMA0,10)
-#define DMA_TCD10_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,10)
-#define DMA_TCD10_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,10)
-#define DMA_TCD11_SADDR DMA_SADDR_REG(DMA0,11)
-#define DMA_TCD11_SOFF DMA_SOFF_REG(DMA0,11)
-#define DMA_TCD11_ATTR DMA_ATTR_REG(DMA0,11)
-#define DMA_TCD11_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,11)
-#define DMA_TCD11_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,11)
-#define DMA_TCD11_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,11)
-#define DMA_TCD11_SLAST DMA_SLAST_REG(DMA0,11)
-#define DMA_TCD11_DADDR DMA_DADDR_REG(DMA0,11)
-#define DMA_TCD11_DOFF DMA_DOFF_REG(DMA0,11)
-#define DMA_TCD11_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,11)
-#define DMA_TCD11_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,11)
-#define DMA_TCD11_DLASTSGA DMA_DLAST_SGA_REG(DMA0,11)
-#define DMA_TCD11_CSR DMA_CSR_REG(DMA0,11)
-#define DMA_TCD11_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,11)
-#define DMA_TCD11_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,11)
-#define DMA_TCD12_SADDR DMA_SADDR_REG(DMA0,12)
-#define DMA_TCD12_SOFF DMA_SOFF_REG(DMA0,12)
-#define DMA_TCD12_ATTR DMA_ATTR_REG(DMA0,12)
-#define DMA_TCD12_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,12)
-#define DMA_TCD12_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,12)
-#define DMA_TCD12_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,12)
-#define DMA_TCD12_SLAST DMA_SLAST_REG(DMA0,12)
-#define DMA_TCD12_DADDR DMA_DADDR_REG(DMA0,12)
-#define DMA_TCD12_DOFF DMA_DOFF_REG(DMA0,12)
-#define DMA_TCD12_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,12)
-#define DMA_TCD12_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,12)
-#define DMA_TCD12_DLASTSGA DMA_DLAST_SGA_REG(DMA0,12)
-#define DMA_TCD12_CSR DMA_CSR_REG(DMA0,12)
-#define DMA_TCD12_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,12)
-#define DMA_TCD12_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,12)
-#define DMA_TCD13_SADDR DMA_SADDR_REG(DMA0,13)
-#define DMA_TCD13_SOFF DMA_SOFF_REG(DMA0,13)
-#define DMA_TCD13_ATTR DMA_ATTR_REG(DMA0,13)
-#define DMA_TCD13_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,13)
-#define DMA_TCD13_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,13)
-#define DMA_TCD13_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,13)
-#define DMA_TCD13_SLAST DMA_SLAST_REG(DMA0,13)
-#define DMA_TCD13_DADDR DMA_DADDR_REG(DMA0,13)
-#define DMA_TCD13_DOFF DMA_DOFF_REG(DMA0,13)
-#define DMA_TCD13_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,13)
-#define DMA_TCD13_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,13)
-#define DMA_TCD13_DLASTSGA DMA_DLAST_SGA_REG(DMA0,13)
-#define DMA_TCD13_CSR DMA_CSR_REG(DMA0,13)
-#define DMA_TCD13_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,13)
-#define DMA_TCD13_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,13)
-#define DMA_TCD14_SADDR DMA_SADDR_REG(DMA0,14)
-#define DMA_TCD14_SOFF DMA_SOFF_REG(DMA0,14)
-#define DMA_TCD14_ATTR DMA_ATTR_REG(DMA0,14)
-#define DMA_TCD14_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,14)
-#define DMA_TCD14_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,14)
-#define DMA_TCD14_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,14)
-#define DMA_TCD14_SLAST DMA_SLAST_REG(DMA0,14)
-#define DMA_TCD14_DADDR DMA_DADDR_REG(DMA0,14)
-#define DMA_TCD14_DOFF DMA_DOFF_REG(DMA0,14)
-#define DMA_TCD14_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,14)
-#define DMA_TCD14_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,14)
-#define DMA_TCD14_DLASTSGA DMA_DLAST_SGA_REG(DMA0,14)
-#define DMA_TCD14_CSR DMA_CSR_REG(DMA0,14)
-#define DMA_TCD14_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,14)
-#define DMA_TCD14_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,14)
-#define DMA_TCD15_SADDR DMA_SADDR_REG(DMA0,15)
-#define DMA_TCD15_SOFF DMA_SOFF_REG(DMA0,15)
-#define DMA_TCD15_ATTR DMA_ATTR_REG(DMA0,15)
-#define DMA_TCD15_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,15)
-#define DMA_TCD15_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,15)
-#define DMA_TCD15_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,15)
-#define DMA_TCD15_SLAST DMA_SLAST_REG(DMA0,15)
-#define DMA_TCD15_DADDR DMA_DADDR_REG(DMA0,15)
-#define DMA_TCD15_DOFF DMA_DOFF_REG(DMA0,15)
-#define DMA_TCD15_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,15)
-#define DMA_TCD15_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,15)
-#define DMA_TCD15_DLASTSGA DMA_DLAST_SGA_REG(DMA0,15)
-#define DMA_TCD15_CSR DMA_CSR_REG(DMA0,15)
-#define DMA_TCD15_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,15)
-#define DMA_TCD15_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,15)
-
-/* DMA - Register array accessors */
-#define DMA_SADDR(index) DMA_SADDR_REG(DMA0,index)
-#define DMA_SOFF(index) DMA_SOFF_REG(DMA0,index)
-#define DMA_ATTR(index) DMA_ATTR_REG(DMA0,index)
-#define DMA_NBYTES_MLNO(index) DMA_NBYTES_MLNO_REG(DMA0,index)
-#define DMA_NBYTES_MLOFFNO(index) DMA_NBYTES_MLOFFNO_REG(DMA0,index)
-#define DMA_NBYTES_MLOFFYES(index) DMA_NBYTES_MLOFFYES_REG(DMA0,index)
-#define DMA_SLAST(index) DMA_SLAST_REG(DMA0,index)
-#define DMA_DADDR(index) DMA_DADDR_REG(DMA0,index)
-#define DMA_DOFF(index) DMA_DOFF_REG(DMA0,index)
-#define DMA_CITER_ELINKNO(index) DMA_CITER_ELINKNO_REG(DMA0,index)
-#define DMA_CITER_ELINKYES(index) DMA_CITER_ELINKYES_REG(DMA0,index)
-#define DMA_DLAST_SGA(index) DMA_DLAST_SGA_REG(DMA0,index)
-#define DMA_CSR(index) DMA_CSR_REG(DMA0,index)
-#define DMA_BITER_ELINKNO(index) DMA_BITER_ELINKNO_REG(DMA0,index)
-#define DMA_BITER_ELINKYES(index) DMA_BITER_ELINKYES_REG(DMA0,index)
-
-/*!
- * @}
- */ /* end of group DMA_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group DMA_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- DMAMUX Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
- * @{
- */
-
-/** DMAMUX - Register Layout Typedef */
-typedef struct {
- __IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
-} DMAMUX_Type, *DMAMUX_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- DMAMUX - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
- * @{
- */
-
-
-/* DMAMUX - Register accessors */
-#define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index])
-
-/*!
- * @}
- */ /* end of group DMAMUX_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- DMAMUX Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
- * @{
- */
-
-/* CHCFG Bit Fields */
-#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
-#define DMAMUX_CHCFG_SOURCE_SHIFT 0
-#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
-#define DMAMUX_CHCFG_TRIG_MASK 0x40u
-#define DMAMUX_CHCFG_TRIG_SHIFT 6
-#define DMAMUX_CHCFG_ENBL_MASK 0x80u
-#define DMAMUX_CHCFG_ENBL_SHIFT 7
-
-/*!
- * @}
- */ /* end of group DMAMUX_Register_Masks */
-
-
-/* DMAMUX - Peripheral instance base addresses */
-/** Peripheral DMAMUX base address */
-#define DMAMUX_BASE (0x40021000u)
-/** Peripheral DMAMUX base pointer */
-#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
-#define DMAMUX_BASE_PTR (DMAMUX)
-/** Array initializer of DMAMUX peripheral base pointers */
-#define DMAMUX_BASES { DMAMUX }
-
-/* ----------------------------------------------------------------------------
- -- DMAMUX - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
- * @{
- */
-
-
-/* DMAMUX - Register instance definitions */
-/* DMAMUX */
-#define DMAMUX_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX,0)
-#define DMAMUX_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX,1)
-#define DMAMUX_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX,2)
-#define DMAMUX_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX,3)
-#define DMAMUX_CHCFG4 DMAMUX_CHCFG_REG(DMAMUX,4)
-#define DMAMUX_CHCFG5 DMAMUX_CHCFG_REG(DMAMUX,5)
-#define DMAMUX_CHCFG6 DMAMUX_CHCFG_REG(DMAMUX,6)
-#define DMAMUX_CHCFG7 DMAMUX_CHCFG_REG(DMAMUX,7)
-#define DMAMUX_CHCFG8 DMAMUX_CHCFG_REG(DMAMUX,8)
-#define DMAMUX_CHCFG9 DMAMUX_CHCFG_REG(DMAMUX,9)
-#define DMAMUX_CHCFG10 DMAMUX_CHCFG_REG(DMAMUX,10)
-#define DMAMUX_CHCFG11 DMAMUX_CHCFG_REG(DMAMUX,11)
-#define DMAMUX_CHCFG12 DMAMUX_CHCFG_REG(DMAMUX,12)
-#define DMAMUX_CHCFG13 DMAMUX_CHCFG_REG(DMAMUX,13)
-#define DMAMUX_CHCFG14 DMAMUX_CHCFG_REG(DMAMUX,14)
-#define DMAMUX_CHCFG15 DMAMUX_CHCFG_REG(DMAMUX,15)
-
-/* DMAMUX - Register array accessors */
-#define DMAMUX_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX,index)
-
-/*!
- * @}
- */ /* end of group DMAMUX_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group DMAMUX_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- ENET Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
- * @{
- */
-
-/** ENET - Register Layout Typedef */
-typedef struct {
- uint8_t RESERVED_0[4];
- __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */
- __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */
- uint8_t RESERVED_1[4];
- __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */
- __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */
- uint8_t RESERVED_2[12];
- __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */
- uint8_t RESERVED_3[24];
- __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */
- __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */
- uint8_t RESERVED_4[28];
- __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */
- uint8_t RESERVED_5[28];
- __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */
- uint8_t RESERVED_6[60];
- __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */
- uint8_t RESERVED_7[28];
- __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */
- __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */
- __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */
- uint8_t RESERVED_8[40];
- __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */
- __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */
- __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */
- __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */
- uint8_t RESERVED_9[28];
- __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */
- uint8_t RESERVED_10[56];
- __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */
- __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
- __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */
- uint8_t RESERVED_11[4];
- __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */
- __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
- __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
- __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
- __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
- __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
- __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
- __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */
- __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */
- uint8_t RESERVED_12[12];
- __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
- __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
- uint8_t RESERVED_13[60];
- __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */
- __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
- __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
- __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
- __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
- __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
- __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
- __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
- __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */
- __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
- __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
- __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
- __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
- __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
- __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
- __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
- __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */
- uint8_t RESERVED_14[4];
- __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
- __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
- __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
- __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
- __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
- __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
- __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
- __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
- uint8_t RESERVED_15[4];
- __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
- __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
- uint8_t RESERVED_16[12];
- __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */
- __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
- __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
- __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
- __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
- __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
- __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
- __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
- uint8_t RESERVED_17[4];
- __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
- __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
- __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
- __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
- __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
- __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
- __I uint32_t RMON_R_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
- __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */
- __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
- __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */
- __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
- __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
- __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
- __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
- __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
- uint8_t RESERVED_18[284];
- __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */
- __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */
- __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */
- __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */
- __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */
- __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */
- __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
- uint8_t RESERVED_19[488];
- __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */
- struct { /* offset: 0x608, array step: 0x8 */
- __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
- __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
- } CHANNEL[4];
-} ENET_Type, *ENET_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- ENET - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
- * @{
- */
-
-
-/* ENET - Register accessors */
-#define ENET_EIR_REG(base) ((base)->EIR)
-#define ENET_EIMR_REG(base) ((base)->EIMR)
-#define ENET_RDAR_REG(base) ((base)->RDAR)
-#define ENET_TDAR_REG(base) ((base)->TDAR)
-#define ENET_ECR_REG(base) ((base)->ECR)
-#define ENET_MMFR_REG(base) ((base)->MMFR)
-#define ENET_MSCR_REG(base) ((base)->MSCR)
-#define ENET_MIBC_REG(base) ((base)->MIBC)
-#define ENET_RCR_REG(base) ((base)->RCR)
-#define ENET_TCR_REG(base) ((base)->TCR)
-#define ENET_PALR_REG(base) ((base)->PALR)
-#define ENET_PAUR_REG(base) ((base)->PAUR)
-#define ENET_OPD_REG(base) ((base)->OPD)
-#define ENET_IAUR_REG(base) ((base)->IAUR)
-#define ENET_IALR_REG(base) ((base)->IALR)
-#define ENET_GAUR_REG(base) ((base)->GAUR)
-#define ENET_GALR_REG(base) ((base)->GALR)
-#define ENET_TFWR_REG(base) ((base)->TFWR)
-#define ENET_RDSR_REG(base) ((base)->RDSR)
-#define ENET_TDSR_REG(base) ((base)->TDSR)
-#define ENET_MRBR_REG(base) ((base)->MRBR)
-#define ENET_RSFL_REG(base) ((base)->RSFL)
-#define ENET_RSEM_REG(base) ((base)->RSEM)
-#define ENET_RAEM_REG(base) ((base)->RAEM)
-#define ENET_RAFL_REG(base) ((base)->RAFL)
-#define ENET_TSEM_REG(base) ((base)->TSEM)
-#define ENET_TAEM_REG(base) ((base)->TAEM)
-#define ENET_TAFL_REG(base) ((base)->TAFL)
-#define ENET_TIPG_REG(base) ((base)->TIPG)
-#define ENET_FTRL_REG(base) ((base)->FTRL)
-#define ENET_TACC_REG(base) ((base)->TACC)
-#define ENET_RACC_REG(base) ((base)->RACC)
-#define ENET_RMON_T_PACKETS_REG(base) ((base)->RMON_T_PACKETS)
-#define ENET_RMON_T_BC_PKT_REG(base) ((base)->RMON_T_BC_PKT)
-#define ENET_RMON_T_MC_PKT_REG(base) ((base)->RMON_T_MC_PKT)
-#define ENET_RMON_T_CRC_ALIGN_REG(base) ((base)->RMON_T_CRC_ALIGN)
-#define ENET_RMON_T_UNDERSIZE_REG(base) ((base)->RMON_T_UNDERSIZE)
-#define ENET_RMON_T_OVERSIZE_REG(base) ((base)->RMON_T_OVERSIZE)
-#define ENET_RMON_T_FRAG_REG(base) ((base)->RMON_T_FRAG)
-#define ENET_RMON_T_JAB_REG(base) ((base)->RMON_T_JAB)
-#define ENET_RMON_T_COL_REG(base) ((base)->RMON_T_COL)
-#define ENET_RMON_T_P64_REG(base) ((base)->RMON_T_P64)
-#define ENET_RMON_T_P65TO127_REG(base) ((base)->RMON_T_P65TO127)
-#define ENET_RMON_T_P128TO255_REG(base) ((base)->RMON_T_P128TO255)
-#define ENET_RMON_T_P256TO511_REG(base) ((base)->RMON_T_P256TO511)
-#define ENET_RMON_T_P512TO1023_REG(base) ((base)->RMON_T_P512TO1023)
-#define ENET_RMON_T_P1024TO2047_REG(base) ((base)->RMON_T_P1024TO2047)
-#define ENET_RMON_T_P_GTE2048_REG(base) ((base)->RMON_T_P_GTE2048)
-#define ENET_RMON_T_OCTETS_REG(base) ((base)->RMON_T_OCTETS)
-#define ENET_IEEE_T_FRAME_OK_REG(base) ((base)->IEEE_T_FRAME_OK)
-#define ENET_IEEE_T_1COL_REG(base) ((base)->IEEE_T_1COL)
-#define ENET_IEEE_T_MCOL_REG(base) ((base)->IEEE_T_MCOL)
-#define ENET_IEEE_T_DEF_REG(base) ((base)->IEEE_T_DEF)
-#define ENET_IEEE_T_LCOL_REG(base) ((base)->IEEE_T_LCOL)
-#define ENET_IEEE_T_EXCOL_REG(base) ((base)->IEEE_T_EXCOL)
-#define ENET_IEEE_T_MACERR_REG(base) ((base)->IEEE_T_MACERR)
-#define ENET_IEEE_T_CSERR_REG(base) ((base)->IEEE_T_CSERR)
-#define ENET_IEEE_T_FDXFC_REG(base) ((base)->IEEE_T_FDXFC)
-#define ENET_IEEE_T_OCTETS_OK_REG(base) ((base)->IEEE_T_OCTETS_OK)
-#define ENET_RMON_R_PACKETS_REG(base) ((base)->RMON_R_PACKETS)
-#define ENET_RMON_R_BC_PKT_REG(base) ((base)->RMON_R_BC_PKT)
-#define ENET_RMON_R_MC_PKT_REG(base) ((base)->RMON_R_MC_PKT)
-#define ENET_RMON_R_CRC_ALIGN_REG(base) ((base)->RMON_R_CRC_ALIGN)
-#define ENET_RMON_R_UNDERSIZE_REG(base) ((base)->RMON_R_UNDERSIZE)
-#define ENET_RMON_R_OVERSIZE_REG(base) ((base)->RMON_R_OVERSIZE)
-#define ENET_RMON_R_FRAG_REG(base) ((base)->RMON_R_FRAG)
-#define ENET_RMON_R_JAB_REG(base) ((base)->RMON_R_JAB)
-#define ENET_RMON_R_P64_REG(base) ((base)->RMON_R_P64)
-#define ENET_RMON_R_P65TO127_REG(base) ((base)->RMON_R_P65TO127)
-#define ENET_RMON_R_P128TO255_REG(base) ((base)->RMON_R_P128TO255)
-#define ENET_RMON_R_P256TO511_REG(base) ((base)->RMON_R_P256TO511)
-#define ENET_RMON_R_P512TO1023_REG(base) ((base)->RMON_R_P512TO1023)
-#define ENET_RMON_R_P1024TO2047_REG(base) ((base)->RMON_R_P1024TO2047)
-#define ENET_RMON_R_GTE2048_REG(base) ((base)->RMON_R_GTE2048)
-#define ENET_RMON_R_OCTETS_REG(base) ((base)->RMON_R_OCTETS)
-#define ENET_IEEE_R_DROP_REG(base) ((base)->IEEE_R_DROP)
-#define ENET_IEEE_R_FRAME_OK_REG(base) ((base)->IEEE_R_FRAME_OK)
-#define ENET_IEEE_R_CRC_REG(base) ((base)->IEEE_R_CRC)
-#define ENET_IEEE_R_ALIGN_REG(base) ((base)->IEEE_R_ALIGN)
-#define ENET_IEEE_R_MACERR_REG(base) ((base)->IEEE_R_MACERR)
-#define ENET_IEEE_R_FDXFC_REG(base) ((base)->IEEE_R_FDXFC)
-#define ENET_IEEE_R_OCTETS_OK_REG(base) ((base)->IEEE_R_OCTETS_OK)
-#define ENET_ATCR_REG(base) ((base)->ATCR)
-#define ENET_ATVR_REG(base) ((base)->ATVR)
-#define ENET_ATOFF_REG(base) ((base)->ATOFF)
-#define ENET_ATPER_REG(base) ((base)->ATPER)
-#define ENET_ATCOR_REG(base) ((base)->ATCOR)
-#define ENET_ATINC_REG(base) ((base)->ATINC)
-#define ENET_ATSTMP_REG(base) ((base)->ATSTMP)
-#define ENET_TGSR_REG(base) ((base)->TGSR)
-#define ENET_TCSR_REG(base,index) ((base)->CHANNEL[index].TCSR)
-#define ENET_TCCR_REG(base,index) ((base)->CHANNEL[index].TCCR)
-
-/*!
- * @}
- */ /* end of group ENET_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- ENET Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ENET_Register_Masks ENET Register Masks
- * @{
- */
-
-/* EIR Bit Fields */
-#define ENET_EIR_TS_TIMER_MASK 0x8000u
-#define ENET_EIR_TS_TIMER_SHIFT 15
-#define ENET_EIR_TS_AVAIL_MASK 0x10000u
-#define ENET_EIR_TS_AVAIL_SHIFT 16
-#define ENET_EIR_WAKEUP_MASK 0x20000u
-#define ENET_EIR_WAKEUP_SHIFT 17
-#define ENET_EIR_PLR_MASK 0x40000u
-#define ENET_EIR_PLR_SHIFT 18
-#define ENET_EIR_UN_MASK 0x80000u
-#define ENET_EIR_UN_SHIFT 19
-#define ENET_EIR_RL_MASK 0x100000u
-#define ENET_EIR_RL_SHIFT 20
-#define ENET_EIR_LC_MASK 0x200000u
-#define ENET_EIR_LC_SHIFT 21
-#define ENET_EIR_EBERR_MASK 0x400000u
-#define ENET_EIR_EBERR_SHIFT 22
-#define ENET_EIR_MII_MASK 0x800000u
-#define ENET_EIR_MII_SHIFT 23
-#define ENET_EIR_RXB_MASK 0x1000000u
-#define ENET_EIR_RXB_SHIFT 24
-#define ENET_EIR_RXF_MASK 0x2000000u
-#define ENET_EIR_RXF_SHIFT 25
-#define ENET_EIR_TXB_MASK 0x4000000u
-#define ENET_EIR_TXB_SHIFT 26
-#define ENET_EIR_TXF_MASK 0x8000000u
-#define ENET_EIR_TXF_SHIFT 27
-#define ENET_EIR_GRA_MASK 0x10000000u
-#define ENET_EIR_GRA_SHIFT 28
-#define ENET_EIR_BABT_MASK 0x20000000u
-#define ENET_EIR_BABT_SHIFT 29
-#define ENET_EIR_BABR_MASK 0x40000000u
-#define ENET_EIR_BABR_SHIFT 30
-/* EIMR Bit Fields */
-#define ENET_EIMR_TS_TIMER_MASK 0x8000u
-#define ENET_EIMR_TS_TIMER_SHIFT 15
-#define ENET_EIMR_TS_AVAIL_MASK 0x10000u
-#define ENET_EIMR_TS_AVAIL_SHIFT 16
-#define ENET_EIMR_WAKEUP_MASK 0x20000u
-#define ENET_EIMR_WAKEUP_SHIFT 17
-#define ENET_EIMR_PLR_MASK 0x40000u
-#define ENET_EIMR_PLR_SHIFT 18
-#define ENET_EIMR_UN_MASK 0x80000u
-#define ENET_EIMR_UN_SHIFT 19
-#define ENET_EIMR_RL_MASK 0x100000u
-#define ENET_EIMR_RL_SHIFT 20
-#define ENET_EIMR_LC_MASK 0x200000u
-#define ENET_EIMR_LC_SHIFT 21
-#define ENET_EIMR_EBERR_MASK 0x400000u
-#define ENET_EIMR_EBERR_SHIFT 22
-#define ENET_EIMR_MII_MASK 0x800000u
-#define ENET_EIMR_MII_SHIFT 23
-#define ENET_EIMR_RXB_MASK 0x1000000u
-#define ENET_EIMR_RXB_SHIFT 24
-#define ENET_EIMR_RXF_MASK 0x2000000u
-#define ENET_EIMR_RXF_SHIFT 25
-#define ENET_EIMR_TXB_MASK 0x4000000u
-#define ENET_EIMR_TXB_SHIFT 26
-#define ENET_EIMR_TXF_MASK 0x8000000u
-#define ENET_EIMR_TXF_SHIFT 27
-#define ENET_EIMR_GRA_MASK 0x10000000u
-#define ENET_EIMR_GRA_SHIFT 28
-#define ENET_EIMR_BABT_MASK 0x20000000u
-#define ENET_EIMR_BABT_SHIFT 29
-#define ENET_EIMR_BABR_MASK 0x40000000u
-#define ENET_EIMR_BABR_SHIFT 30
-/* RDAR Bit Fields */
-#define ENET_RDAR_RDAR_MASK 0x1000000u
-#define ENET_RDAR_RDAR_SHIFT 24
-/* TDAR Bit Fields */
-#define ENET_TDAR_TDAR_MASK 0x1000000u
-#define ENET_TDAR_TDAR_SHIFT 24
-/* ECR Bit Fields */
-#define ENET_ECR_RESET_MASK 0x1u
-#define ENET_ECR_RESET_SHIFT 0
-#define ENET_ECR_ETHEREN_MASK 0x2u
-#define ENET_ECR_ETHEREN_SHIFT 1
-#define ENET_ECR_MAGICEN_MASK 0x4u
-#define ENET_ECR_MAGICEN_SHIFT 2
-#define ENET_ECR_SLEEP_MASK 0x8u
-#define ENET_ECR_SLEEP_SHIFT 3
-#define ENET_ECR_EN1588_MASK 0x10u
-#define ENET_ECR_EN1588_SHIFT 4
-#define ENET_ECR_DBGEN_MASK 0x40u
-#define ENET_ECR_DBGEN_SHIFT 6
-#define ENET_ECR_STOPEN_MASK 0x80u
-#define ENET_ECR_STOPEN_SHIFT 7
-#define ENET_ECR_DBSWP_MASK 0x100u
-#define ENET_ECR_DBSWP_SHIFT 8
-/* MMFR Bit Fields */
-#define ENET_MMFR_DATA_MASK 0xFFFFu
-#define ENET_MMFR_DATA_SHIFT 0
-#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK)
-#define ENET_MMFR_TA_MASK 0x30000u
-#define ENET_MMFR_TA_SHIFT 16
-#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK)
-#define ENET_MMFR_RA_MASK 0x7C0000u
-#define ENET_MMFR_RA_SHIFT 18
-#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK)
-#define ENET_MMFR_PA_MASK 0xF800000u
-#define ENET_MMFR_PA_SHIFT 23
-#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK)
-#define ENET_MMFR_OP_MASK 0x30000000u
-#define ENET_MMFR_OP_SHIFT 28
-#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK)
-#define ENET_MMFR_ST_MASK 0xC0000000u
-#define ENET_MMFR_ST_SHIFT 30
-#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK)
-/* MSCR Bit Fields */
-#define ENET_MSCR_MII_SPEED_MASK 0x7Eu
-#define ENET_MSCR_MII_SPEED_SHIFT 1
-#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK)
-#define ENET_MSCR_DIS_PRE_MASK 0x80u
-#define ENET_MSCR_DIS_PRE_SHIFT 7
-#define ENET_MSCR_HOLDTIME_MASK 0x700u
-#define ENET_MSCR_HOLDTIME_SHIFT 8
-#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK)
-/* MIBC Bit Fields */
-#define ENET_MIBC_MIB_CLEAR_MASK 0x20000000u
-#define ENET_MIBC_MIB_CLEAR_SHIFT 29
-#define ENET_MIBC_MIB_IDLE_MASK 0x40000000u
-#define ENET_MIBC_MIB_IDLE_SHIFT 30
-#define ENET_MIBC_MIB_DIS_MASK 0x80000000u
-#define ENET_MIBC_MIB_DIS_SHIFT 31
-/* RCR Bit Fields */
-#define ENET_RCR_LOOP_MASK 0x1u
-#define ENET_RCR_LOOP_SHIFT 0
-#define ENET_RCR_DRT_MASK 0x2u
-#define ENET_RCR_DRT_SHIFT 1
-#define ENET_RCR_MII_MODE_MASK 0x4u
-#define ENET_RCR_MII_MODE_SHIFT 2
-#define ENET_RCR_PROM_MASK 0x8u
-#define ENET_RCR_PROM_SHIFT 3
-#define ENET_RCR_BC_REJ_MASK 0x10u
-#define ENET_RCR_BC_REJ_SHIFT 4
-#define ENET_RCR_FCE_MASK 0x20u
-#define ENET_RCR_FCE_SHIFT 5
-#define ENET_RCR_RMII_MODE_MASK 0x100u
-#define ENET_RCR_RMII_MODE_SHIFT 8
-#define ENET_RCR_RMII_10T_MASK 0x200u
-#define ENET_RCR_RMII_10T_SHIFT 9
-#define ENET_RCR_PADEN_MASK 0x1000u
-#define ENET_RCR_PADEN_SHIFT 12
-#define ENET_RCR_PAUFWD_MASK 0x2000u
-#define ENET_RCR_PAUFWD_SHIFT 13
-#define ENET_RCR_CRCFWD_MASK 0x4000u
-#define ENET_RCR_CRCFWD_SHIFT 14
-#define ENET_RCR_CFEN_MASK 0x8000u
-#define ENET_RCR_CFEN_SHIFT 15
-#define ENET_RCR_MAX_FL_MASK 0x3FFF0000u
-#define ENET_RCR_MAX_FL_SHIFT 16
-#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK)
-#define ENET_RCR_NLC_MASK 0x40000000u
-#define ENET_RCR_NLC_SHIFT 30
-#define ENET_RCR_GRS_MASK 0x80000000u
-#define ENET_RCR_GRS_SHIFT 31
-/* TCR Bit Fields */
-#define ENET_TCR_GTS_MASK 0x1u
-#define ENET_TCR_GTS_SHIFT 0
-#define ENET_TCR_FDEN_MASK 0x4u
-#define ENET_TCR_FDEN_SHIFT 2
-#define ENET_TCR_TFC_PAUSE_MASK 0x8u
-#define ENET_TCR_TFC_PAUSE_SHIFT 3
-#define ENET_TCR_RFC_PAUSE_MASK 0x10u
-#define ENET_TCR_RFC_PAUSE_SHIFT 4
-#define ENET_TCR_ADDSEL_MASK 0xE0u
-#define ENET_TCR_ADDSEL_SHIFT 5
-#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK)
-#define ENET_TCR_ADDINS_MASK 0x100u
-#define ENET_TCR_ADDINS_SHIFT 8
-#define ENET_TCR_CRCFWD_MASK 0x200u
-#define ENET_TCR_CRCFWD_SHIFT 9
-/* PALR Bit Fields */
-#define ENET_PALR_PADDR1_MASK 0xFFFFFFFFu
-#define ENET_PALR_PADDR1_SHIFT 0
-#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK)
-/* PAUR Bit Fields */
-#define ENET_PAUR_TYPE_MASK 0xFFFFu
-#define ENET_PAUR_TYPE_SHIFT 0
-#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK)
-#define ENET_PAUR_PADDR2_MASK 0xFFFF0000u
-#define ENET_PAUR_PADDR2_SHIFT 16
-#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK)
-/* OPD Bit Fields */
-#define ENET_OPD_PAUSE_DUR_MASK 0xFFFFu
-#define ENET_OPD_PAUSE_DUR_SHIFT 0
-#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK)
-#define ENET_OPD_OPCODE_MASK 0xFFFF0000u
-#define ENET_OPD_OPCODE_SHIFT 16
-#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK)
-/* IAUR Bit Fields */
-#define ENET_IAUR_IADDR1_MASK 0xFFFFFFFFu
-#define ENET_IAUR_IADDR1_SHIFT 0
-#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK)
-/* IALR Bit Fields */
-#define ENET_IALR_IADDR2_MASK 0xFFFFFFFFu
-#define ENET_IALR_IADDR2_SHIFT 0
-#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK)
-/* GAUR Bit Fields */
-#define ENET_GAUR_GADDR1_MASK 0xFFFFFFFFu
-#define ENET_GAUR_GADDR1_SHIFT 0
-#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK)
-/* GALR Bit Fields */
-#define ENET_GALR_GADDR2_MASK 0xFFFFFFFFu
-#define ENET_GALR_GADDR2_SHIFT 0
-#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK)
-/* TFWR Bit Fields */
-#define ENET_TFWR_TFWR_MASK 0x3Fu
-#define ENET_TFWR_TFWR_SHIFT 0
-#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK)
-#define ENET_TFWR_STRFWD_MASK 0x100u
-#define ENET_TFWR_STRFWD_SHIFT 8
-/* RDSR Bit Fields */
-#define ENET_RDSR_R_DES_START_MASK 0xFFFFFFF8u
-#define ENET_RDSR_R_DES_START_SHIFT 3
-#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK)
-/* TDSR Bit Fields */
-#define ENET_TDSR_X_DES_START_MASK 0xFFFFFFF8u
-#define ENET_TDSR_X_DES_START_SHIFT 3
-#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK)
-/* MRBR Bit Fields */
-#define ENET_MRBR_R_BUF_SIZE_MASK 0x3FF0u
-#define ENET_MRBR_R_BUF_SIZE_SHIFT 4
-#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK)
-/* RSFL Bit Fields */
-#define ENET_RSFL_RX_SECTION_FULL_MASK 0xFFu
-#define ENET_RSFL_RX_SECTION_FULL_SHIFT 0
-#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK)
-/* RSEM Bit Fields */
-#define ENET_RSEM_RX_SECTION_EMPTY_MASK 0xFFu
-#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT 0
-#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK)
-#define ENET_RSEM_STAT_SECTION_EMPTY_MASK 0x1F0000u
-#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT 16
-#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_STAT_SECTION_EMPTY_SHIFT))&ENET_RSEM_STAT_SECTION_EMPTY_MASK)
-/* RAEM Bit Fields */
-#define ENET_RAEM_RX_ALMOST_EMPTY_MASK 0xFFu
-#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT 0
-#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK)
-/* RAFL Bit Fields */
-#define ENET_RAFL_RX_ALMOST_FULL_MASK 0xFFu
-#define ENET_RAFL_RX_ALMOST_FULL_SHIFT 0
-#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK)
-/* TSEM Bit Fields */
-#define ENET_TSEM_TX_SECTION_EMPTY_MASK 0xFFu
-#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT 0
-#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK)
-/* TAEM Bit Fields */
-#define ENET_TAEM_TX_ALMOST_EMPTY_MASK 0xFFu
-#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT 0
-#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK)
-/* TAFL Bit Fields */
-#define ENET_TAFL_TX_ALMOST_FULL_MASK 0xFFu
-#define ENET_TAFL_TX_ALMOST_FULL_SHIFT 0
-#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK)
-/* TIPG Bit Fields */
-#define ENET_TIPG_IPG_MASK 0x1Fu
-#define ENET_TIPG_IPG_SHIFT 0
-#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK)
-/* FTRL Bit Fields */
-#define ENET_FTRL_TRUNC_FL_MASK 0x3FFFu
-#define ENET_FTRL_TRUNC_FL_SHIFT 0
-#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK)
-/* TACC Bit Fields */
-#define ENET_TACC_SHIFT16_MASK 0x1u
-#define ENET_TACC_SHIFT16_SHIFT 0
-#define ENET_TACC_IPCHK_MASK 0x8u
-#define ENET_TACC_IPCHK_SHIFT 3
-#define ENET_TACC_PROCHK_MASK 0x10u
-#define ENET_TACC_PROCHK_SHIFT 4
-/* RACC Bit Fields */
-#define ENET_RACC_PADREM_MASK 0x1u
-#define ENET_RACC_PADREM_SHIFT 0
-#define ENET_RACC_IPDIS_MASK 0x2u
-#define ENET_RACC_IPDIS_SHIFT 1
-#define ENET_RACC_PRODIS_MASK 0x4u
-#define ENET_RACC_PRODIS_SHIFT 2
-#define ENET_RACC_LINEDIS_MASK 0x40u
-#define ENET_RACC_LINEDIS_SHIFT 6
-#define ENET_RACC_SHIFT16_MASK 0x80u
-#define ENET_RACC_SHIFT16_SHIFT 7
-/* RMON_T_PACKETS Bit Fields */
-#define ENET_RMON_T_PACKETS_TXPKTS_MASK 0xFFFFu
-#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT 0
-#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_PACKETS_TXPKTS_SHIFT))&ENET_RMON_T_PACKETS_TXPKTS_MASK)
-/* RMON_T_BC_PKT Bit Fields */
-#define ENET_RMON_T_BC_PKT_TXPKTS_MASK 0xFFFFu
-#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT 0
-#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_BC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_BC_PKT_TXPKTS_MASK)
-/* RMON_T_MC_PKT Bit Fields */
-#define ENET_RMON_T_MC_PKT_TXPKTS_MASK 0xFFFFu
-#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT 0
-#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_MC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_MC_PKT_TXPKTS_MASK)
-/* RMON_T_CRC_ALIGN Bit Fields */
-#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK 0xFFFFu
-#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT 0
-#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT))&ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
-/* RMON_T_UNDERSIZE Bit Fields */
-#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK 0xFFFFu
-#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT 0
-#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
-/* RMON_T_OVERSIZE Bit Fields */
-#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK 0xFFFFu
-#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT 0
-#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
-/* RMON_T_FRAG Bit Fields */
-#define ENET_RMON_T_FRAG_TXPKTS_MASK 0xFFFFu
-#define ENET_RMON_T_FRAG_TXPKTS_SHIFT 0
-#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_FRAG_TXPKTS_SHIFT))&ENET_RMON_T_FRAG_TXPKTS_MASK)
-/* RMON_T_JAB Bit Fields */
-#define ENET_RMON_T_JAB_TXPKTS_MASK 0xFFFFu
-#define ENET_RMON_T_JAB_TXPKTS_SHIFT 0
-#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_JAB_TXPKTS_SHIFT))&ENET_RMON_T_JAB_TXPKTS_MASK)
-/* RMON_T_COL Bit Fields */
-#define ENET_RMON_T_COL_TXPKTS_MASK 0xFFFFu
-#define ENET_RMON_T_COL_TXPKTS_SHIFT 0
-#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_COL_TXPKTS_SHIFT))&ENET_RMON_T_COL_TXPKTS_MASK)
-/* RMON_T_P64 Bit Fields */
-#define ENET_RMON_T_P64_TXPKTS_MASK 0xFFFFu
-#define ENET_RMON_T_P64_TXPKTS_SHIFT 0
-#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P64_TXPKTS_SHIFT))&ENET_RMON_T_P64_TXPKTS_MASK)
-/* RMON_T_P65TO127 Bit Fields */
-#define ENET_RMON_T_P65TO127_TXPKTS_MASK 0xFFFFu
-#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT 0
-#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P65TO127_TXPKTS_SHIFT))&ENET_RMON_T_P65TO127_TXPKTS_MASK)
-/* RMON_T_P128TO255 Bit Fields */
-#define ENET_RMON_T_P128TO255_TXPKTS_MASK 0xFFFFu
-#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT 0
-#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P128TO255_TXPKTS_SHIFT))&ENET_RMON_T_P128TO255_TXPKTS_MASK)
-/* RMON_T_P256TO511 Bit Fields */
-#define ENET_RMON_T_P256TO511_TXPKTS_MASK 0xFFFFu
-#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT 0
-#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P256TO511_TXPKTS_SHIFT))&ENET_RMON_T_P256TO511_TXPKTS_MASK)
-/* RMON_T_P512TO1023 Bit Fields */
-#define ENET_RMON_T_P512TO1023_TXPKTS_MASK 0xFFFFu
-#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT 0
-#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P512TO1023_TXPKTS_SHIFT))&ENET_RMON_T_P512TO1023_TXPKTS_MASK)
-/* RMON_T_P1024TO2047 Bit Fields */
-#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK 0xFFFFu
-#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT 0
-#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT))&ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
-/* RMON_T_P_GTE2048 Bit Fields */
-#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK 0xFFFFu
-#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT 0
-#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT))&ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
-/* RMON_T_OCTETS Bit Fields */
-#define ENET_RMON_T_OCTETS_TXOCTS_MASK 0xFFFFFFFFu
-#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT 0
-#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OCTETS_TXOCTS_SHIFT))&ENET_RMON_T_OCTETS_TXOCTS_MASK)
-/* IEEE_T_FRAME_OK Bit Fields */
-#define ENET_IEEE_T_FRAME_OK_COUNT_MASK 0xFFFFu
-#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT 0
-#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_T_FRAME_OK_COUNT_MASK)
-/* IEEE_T_1COL Bit Fields */
-#define ENET_IEEE_T_1COL_COUNT_MASK 0xFFFFu
-#define ENET_IEEE_T_1COL_COUNT_SHIFT 0
-#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_1COL_COUNT_SHIFT))&ENET_IEEE_T_1COL_COUNT_MASK)
-/* IEEE_T_MCOL Bit Fields */
-#define ENET_IEEE_T_MCOL_COUNT_MASK 0xFFFFu
-#define ENET_IEEE_T_MCOL_COUNT_SHIFT 0
-#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MCOL_COUNT_SHIFT))&ENET_IEEE_T_MCOL_COUNT_MASK)
-/* IEEE_T_DEF Bit Fields */
-#define ENET_IEEE_T_DEF_COUNT_MASK 0xFFFFu
-#define ENET_IEEE_T_DEF_COUNT_SHIFT 0
-#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_DEF_COUNT_SHIFT))&ENET_IEEE_T_DEF_COUNT_MASK)
-/* IEEE_T_LCOL Bit Fields */
-#define ENET_IEEE_T_LCOL_COUNT_MASK 0xFFFFu
-#define ENET_IEEE_T_LCOL_COUNT_SHIFT 0
-#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_LCOL_COUNT_SHIFT))&ENET_IEEE_T_LCOL_COUNT_MASK)
-/* IEEE_T_EXCOL Bit Fields */
-#define ENET_IEEE_T_EXCOL_COUNT_MASK 0xFFFFu
-#define ENET_IEEE_T_EXCOL_COUNT_SHIFT 0
-#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_EXCOL_COUNT_SHIFT))&ENET_IEEE_T_EXCOL_COUNT_MASK)
-/* IEEE_T_MACERR Bit Fields */
-#define ENET_IEEE_T_MACERR_COUNT_MASK 0xFFFFu
-#define ENET_IEEE_T_MACERR_COUNT_SHIFT 0
-#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MACERR_COUNT_SHIFT))&ENET_IEEE_T_MACERR_COUNT_MASK)
-/* IEEE_T_CSERR Bit Fields */
-#define ENET_IEEE_T_CSERR_COUNT_MASK 0xFFFFu
-#define ENET_IEEE_T_CSERR_COUNT_SHIFT 0
-#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_CSERR_COUNT_SHIFT))&ENET_IEEE_T_CSERR_COUNT_MASK)
-/* IEEE_T_FDXFC Bit Fields */
-#define ENET_IEEE_T_FDXFC_COUNT_MASK 0xFFFFu
-#define ENET_IEEE_T_FDXFC_COUNT_SHIFT 0
-#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FDXFC_COUNT_SHIFT))&ENET_IEEE_T_FDXFC_COUNT_MASK)
-/* IEEE_T_OCTETS_OK Bit Fields */
-#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu
-#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT 0
-#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
-/* RMON_R_PACKETS Bit Fields */
-#define ENET_RMON_R_PACKETS_COUNT_MASK 0xFFFFu
-#define ENET_RMON_R_PACKETS_COUNT_SHIFT 0
-#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_PACKETS_COUNT_SHIFT))&ENET_RMON_R_PACKETS_COUNT_MASK)
-/* RMON_R_BC_PKT Bit Fields */
-#define ENET_RMON_R_BC_PKT_COUNT_MASK 0xFFFFu
-#define ENET_RMON_R_BC_PKT_COUNT_SHIFT 0
-#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_BC_PKT_COUNT_SHIFT))&ENET_RMON_R_BC_PKT_COUNT_MASK)
-/* RMON_R_MC_PKT Bit Fields */
-#define ENET_RMON_R_MC_PKT_COUNT_MASK 0xFFFFu
-#define ENET_RMON_R_MC_PKT_COUNT_SHIFT 0
-#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_MC_PKT_COUNT_SHIFT))&ENET_RMON_R_MC_PKT_COUNT_MASK)
-/* RMON_R_CRC_ALIGN Bit Fields */
-#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK 0xFFFFu
-#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT 0
-#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT))&ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
-/* RMON_R_UNDERSIZE Bit Fields */
-#define ENET_RMON_R_UNDERSIZE_COUNT_MASK 0xFFFFu
-#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT 0
-#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_UNDERSIZE_COUNT_SHIFT))&ENET_RMON_R_UNDERSIZE_COUNT_MASK)
-/* RMON_R_OVERSIZE Bit Fields */
-#define ENET_RMON_R_OVERSIZE_COUNT_MASK 0xFFFFu
-#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT 0
-#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OVERSIZE_COUNT_SHIFT))&ENET_RMON_R_OVERSIZE_COUNT_MASK)
-/* RMON_R_FRAG Bit Fields */
-#define ENET_RMON_R_FRAG_COUNT_MASK 0xFFFFu
-#define ENET_RMON_R_FRAG_COUNT_SHIFT 0
-#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_FRAG_COUNT_SHIFT))&ENET_RMON_R_FRAG_COUNT_MASK)
-/* RMON_R_JAB Bit Fields */
-#define ENET_RMON_R_JAB_COUNT_MASK 0xFFFFu
-#define ENET_RMON_R_JAB_COUNT_SHIFT 0
-#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_JAB_COUNT_SHIFT))&ENET_RMON_R_JAB_COUNT_MASK)
-/* RMON_R_P64 Bit Fields */
-#define ENET_RMON_R_P64_COUNT_MASK 0xFFFFu
-#define ENET_RMON_R_P64_COUNT_SHIFT 0
-#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P64_COUNT_SHIFT))&ENET_RMON_R_P64_COUNT_MASK)
-/* RMON_R_P65TO127 Bit Fields */
-#define ENET_RMON_R_P65TO127_COUNT_MASK 0xFFFFu
-#define ENET_RMON_R_P65TO127_COUNT_SHIFT 0
-#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P65TO127_COUNT_SHIFT))&ENET_RMON_R_P65TO127_COUNT_MASK)
-/* RMON_R_P128TO255 Bit Fields */
-#define ENET_RMON_R_P128TO255_COUNT_MASK 0xFFFFu
-#define ENET_RMON_R_P128TO255_COUNT_SHIFT 0
-#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P128TO255_COUNT_SHIFT))&ENET_RMON_R_P128TO255_COUNT_MASK)
-/* RMON_R_P256TO511 Bit Fields */
-#define ENET_RMON_R_P256TO511_COUNT_MASK 0xFFFFu
-#define ENET_RMON_R_P256TO511_COUNT_SHIFT 0
-#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P256TO511_COUNT_SHIFT))&ENET_RMON_R_P256TO511_COUNT_MASK)
-/* RMON_R_P512TO1023 Bit Fields */
-#define ENET_RMON_R_P512TO1023_COUNT_MASK 0xFFFFu
-#define ENET_RMON_R_P512TO1023_COUNT_SHIFT 0
-#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P512TO1023_COUNT_SHIFT))&ENET_RMON_R_P512TO1023_COUNT_MASK)
-/* RMON_R_P1024TO2047 Bit Fields */
-#define ENET_RMON_R_P1024TO2047_COUNT_MASK 0xFFFFu
-#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT 0
-#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P1024TO2047_COUNT_SHIFT))&ENET_RMON_R_P1024TO2047_COUNT_MASK)
-/* RMON_R_GTE2048 Bit Fields */
-#define ENET_RMON_R_GTE2048_COUNT_MASK 0xFFFFu
-#define ENET_RMON_R_GTE2048_COUNT_SHIFT 0
-#define ENET_RMON_R_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_GTE2048_COUNT_SHIFT))&ENET_RMON_R_GTE2048_COUNT_MASK)
-/* RMON_R_OCTETS Bit Fields */
-#define ENET_RMON_R_OCTETS_COUNT_MASK 0xFFFFFFFFu
-#define ENET_RMON_R_OCTETS_COUNT_SHIFT 0
-#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OCTETS_COUNT_SHIFT))&ENET_RMON_R_OCTETS_COUNT_MASK)
-/* IEEE_R_DROP Bit Fields */
-#define ENET_IEEE_R_DROP_COUNT_MASK 0xFFFFu
-#define ENET_IEEE_R_DROP_COUNT_SHIFT 0
-#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_DROP_COUNT_SHIFT))&ENET_IEEE_R_DROP_COUNT_MASK)
-/* IEEE_R_FRAME_OK Bit Fields */
-#define ENET_IEEE_R_FRAME_OK_COUNT_MASK 0xFFFFu
-#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT 0
-#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_R_FRAME_OK_COUNT_MASK)
-/* IEEE_R_CRC Bit Fields */
-#define ENET_IEEE_R_CRC_COUNT_MASK 0xFFFFu
-#define ENET_IEEE_R_CRC_COUNT_SHIFT 0
-#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_CRC_COUNT_SHIFT))&ENET_IEEE_R_CRC_COUNT_MASK)
-/* IEEE_R_ALIGN Bit Fields */
-#define ENET_IEEE_R_ALIGN_COUNT_MASK 0xFFFFu
-#define ENET_IEEE_R_ALIGN_COUNT_SHIFT 0
-#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_ALIGN_COUNT_SHIFT))&ENET_IEEE_R_ALIGN_COUNT_MASK)
-/* IEEE_R_MACERR Bit Fields */
-#define ENET_IEEE_R_MACERR_COUNT_MASK 0xFFFFu
-#define ENET_IEEE_R_MACERR_COUNT_SHIFT 0
-#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_MACERR_COUNT_SHIFT))&ENET_IEEE_R_MACERR_COUNT_MASK)
-/* IEEE_R_FDXFC Bit Fields */
-#define ENET_IEEE_R_FDXFC_COUNT_MASK 0xFFFFu
-#define ENET_IEEE_R_FDXFC_COUNT_SHIFT 0
-#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FDXFC_COUNT_SHIFT))&ENET_IEEE_R_FDXFC_COUNT_MASK)
-/* IEEE_R_OCTETS_OK Bit Fields */
-#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu
-#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT 0
-#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
-/* ATCR Bit Fields */
-#define ENET_ATCR_EN_MASK 0x1u
-#define ENET_ATCR_EN_SHIFT 0
-#define ENET_ATCR_OFFEN_MASK 0x4u
-#define ENET_ATCR_OFFEN_SHIFT 2
-#define ENET_ATCR_OFFRST_MASK 0x8u
-#define ENET_ATCR_OFFRST_SHIFT 3
-#define ENET_ATCR_PEREN_MASK 0x10u
-#define ENET_ATCR_PEREN_SHIFT 4
-#define ENET_ATCR_PINPER_MASK 0x80u
-#define ENET_ATCR_PINPER_SHIFT 7
-#define ENET_ATCR_RESTART_MASK 0x200u
-#define ENET_ATCR_RESTART_SHIFT 9
-#define ENET_ATCR_CAPTURE_MASK 0x800u
-#define ENET_ATCR_CAPTURE_SHIFT 11
-#define ENET_ATCR_SLAVE_MASK 0x2000u
-#define ENET_ATCR_SLAVE_SHIFT 13
-/* ATVR Bit Fields */
-#define ENET_ATVR_ATIME_MASK 0xFFFFFFFFu
-#define ENET_ATVR_ATIME_SHIFT 0
-#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK)
-/* ATOFF Bit Fields */
-#define ENET_ATOFF_OFFSET_MASK 0xFFFFFFFFu
-#define ENET_ATOFF_OFFSET_SHIFT 0
-#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK)
-/* ATPER Bit Fields */
-#define ENET_ATPER_PERIOD_MASK 0xFFFFFFFFu
-#define ENET_ATPER_PERIOD_SHIFT 0
-#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK)
-/* ATCOR Bit Fields */
-#define ENET_ATCOR_COR_MASK 0x7FFFFFFFu
-#define ENET_ATCOR_COR_SHIFT 0
-#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK)
-/* ATINC Bit Fields */
-#define ENET_ATINC_INC_MASK 0x7Fu
-#define ENET_ATINC_INC_SHIFT 0
-#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK)
-#define ENET_ATINC_INC_CORR_MASK 0x7F00u
-#define ENET_ATINC_INC_CORR_SHIFT 8
-#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK)
-/* ATSTMP Bit Fields */
-#define ENET_ATSTMP_TIMESTAMP_MASK 0xFFFFFFFFu
-#define ENET_ATSTMP_TIMESTAMP_SHIFT 0
-#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK)
-/* TGSR Bit Fields */
-#define ENET_TGSR_TF0_MASK 0x1u
-#define ENET_TGSR_TF0_SHIFT 0
-#define ENET_TGSR_TF1_MASK 0x2u
-#define ENET_TGSR_TF1_SHIFT 1
-#define ENET_TGSR_TF2_MASK 0x4u
-#define ENET_TGSR_TF2_SHIFT 2
-#define ENET_TGSR_TF3_MASK 0x8u
-#define ENET_TGSR_TF3_SHIFT 3
-/* TCSR Bit Fields */
-#define ENET_TCSR_TDRE_MASK 0x1u
-#define ENET_TCSR_TDRE_SHIFT 0
-#define ENET_TCSR_TMODE_MASK 0x3Cu
-#define ENET_TCSR_TMODE_SHIFT 2
-#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK)
-#define ENET_TCSR_TIE_MASK 0x40u
-#define ENET_TCSR_TIE_SHIFT 6
-#define ENET_TCSR_TF_MASK 0x80u
-#define ENET_TCSR_TF_SHIFT 7
-/* TCCR Bit Fields */
-#define ENET_TCCR_TCC_MASK 0xFFFFFFFFu
-#define ENET_TCCR_TCC_SHIFT 0
-#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK)
-
-/*!
- * @}
- */ /* end of group ENET_Register_Masks */
-
-
-/* ENET - Peripheral instance base addresses */
-/** Peripheral ENET base address */
-#define ENET_BASE (0x400C0000u)
-/** Peripheral ENET base pointer */
-#define ENET ((ENET_Type *)ENET_BASE)
-#define ENET_BASE_PTR (ENET)
-/** Array initializer of ENET peripheral base pointers */
-#define ENET_BASES { ENET }
-
-/* ----------------------------------------------------------------------------
- -- ENET - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
- * @{
- */
-
-
-/* ENET - Register instance definitions */
-/* ENET */
-#define ENET_EIR ENET_EIR_REG(ENET)
-#define ENET_EIMR ENET_EIMR_REG(ENET)
-#define ENET_RDAR ENET_RDAR_REG(ENET)
-#define ENET_TDAR ENET_TDAR_REG(ENET)
-#define ENET_ECR ENET_ECR_REG(ENET)
-#define ENET_MMFR ENET_MMFR_REG(ENET)
-#define ENET_MSCR ENET_MSCR_REG(ENET)
-#define ENET_MIBC ENET_MIBC_REG(ENET)
-#define ENET_RCR ENET_RCR_REG(ENET)
-#define ENET_TCR ENET_TCR_REG(ENET)
-#define ENET_PALR ENET_PALR_REG(ENET)
-#define ENET_PAUR ENET_PAUR_REG(ENET)
-#define ENET_OPD ENET_OPD_REG(ENET)
-#define ENET_IAUR ENET_IAUR_REG(ENET)
-#define ENET_IALR ENET_IALR_REG(ENET)
-#define ENET_GAUR ENET_GAUR_REG(ENET)
-#define ENET_GALR ENET_GALR_REG(ENET)
-#define ENET_TFWR ENET_TFWR_REG(ENET)
-#define ENET_RDSR ENET_RDSR_REG(ENET)
-#define ENET_TDSR ENET_TDSR_REG(ENET)
-#define ENET_MRBR ENET_MRBR_REG(ENET)
-#define ENET_RSFL ENET_RSFL_REG(ENET)
-#define ENET_RSEM ENET_RSEM_REG(ENET)
-#define ENET_RAEM ENET_RAEM_REG(ENET)
-#define ENET_RAFL ENET_RAFL_REG(ENET)
-#define ENET_TSEM ENET_TSEM_REG(ENET)
-#define ENET_TAEM ENET_TAEM_REG(ENET)
-#define ENET_TAFL ENET_TAFL_REG(ENET)
-#define ENET_TIPG ENET_TIPG_REG(ENET)
-#define ENET_FTRL ENET_FTRL_REG(ENET)
-#define ENET_TACC ENET_TACC_REG(ENET)
-#define ENET_RACC ENET_RACC_REG(ENET)
-#define ENET_RMON_T_PACKETS ENET_RMON_T_PACKETS_REG(ENET)
-#define ENET_RMON_T_BC_PKT ENET_RMON_T_BC_PKT_REG(ENET)
-#define ENET_RMON_T_MC_PKT ENET_RMON_T_MC_PKT_REG(ENET)
-#define ENET_RMON_T_CRC_ALIGN ENET_RMON_T_CRC_ALIGN_REG(ENET)
-#define ENET_RMON_T_UNDERSIZE ENET_RMON_T_UNDERSIZE_REG(ENET)
-#define ENET_RMON_T_OVERSIZE ENET_RMON_T_OVERSIZE_REG(ENET)
-#define ENET_RMON_T_FRAG ENET_RMON_T_FRAG_REG(ENET)
-#define ENET_RMON_T_JAB ENET_RMON_T_JAB_REG(ENET)
-#define ENET_RMON_T_COL ENET_RMON_T_COL_REG(ENET)
-#define ENET_RMON_T_P64 ENET_RMON_T_P64_REG(ENET)
-#define ENET_RMON_T_P65TO127 ENET_RMON_T_P65TO127_REG(ENET)
-#define ENET_RMON_T_P128TO255 ENET_RMON_T_P128TO255_REG(ENET)
-#define ENET_RMON_T_P256TO511 ENET_RMON_T_P256TO511_REG(ENET)
-#define ENET_RMON_T_P512TO1023 ENET_RMON_T_P512TO1023_REG(ENET)
-#define ENET_RMON_T_P1024TO2047 ENET_RMON_T_P1024TO2047_REG(ENET)
-#define ENET_RMON_T_P_GTE2048 ENET_RMON_T_P_GTE2048_REG(ENET)
-#define ENET_RMON_T_OCTETS ENET_RMON_T_OCTETS_REG(ENET)
-#define ENET_IEEE_T_FRAME_OK ENET_IEEE_T_FRAME_OK_REG(ENET)
-#define ENET_IEEE_T_1COL ENET_IEEE_T_1COL_REG(ENET)
-#define ENET_IEEE_T_MCOL ENET_IEEE_T_MCOL_REG(ENET)
-#define ENET_IEEE_T_DEF ENET_IEEE_T_DEF_REG(ENET)
-#define ENET_IEEE_T_LCOL ENET_IEEE_T_LCOL_REG(ENET)
-#define ENET_IEEE_T_EXCOL ENET_IEEE_T_EXCOL_REG(ENET)
-#define ENET_IEEE_T_MACERR ENET_IEEE_T_MACERR_REG(ENET)
-#define ENET_IEEE_T_CSERR ENET_IEEE_T_CSERR_REG(ENET)
-#define ENET_IEEE_T_FDXFC ENET_IEEE_T_FDXFC_REG(ENET)
-#define ENET_IEEE_T_OCTETS_OK ENET_IEEE_T_OCTETS_OK_REG(ENET)
-#define ENET_RMON_R_PACKETS ENET_RMON_R_PACKETS_REG(ENET)
-#define ENET_RMON_R_BC_PKT ENET_RMON_R_BC_PKT_REG(ENET)
-#define ENET_RMON_R_MC_PKT ENET_RMON_R_MC_PKT_REG(ENET)
-#define ENET_RMON_R_CRC_ALIGN ENET_RMON_R_CRC_ALIGN_REG(ENET)
-#define ENET_RMON_R_UNDERSIZE ENET_RMON_R_UNDERSIZE_REG(ENET)
-#define ENET_RMON_R_OVERSIZE ENET_RMON_R_OVERSIZE_REG(ENET)
-#define ENET_RMON_R_FRAG ENET_RMON_R_FRAG_REG(ENET)
-#define ENET_RMON_R_JAB ENET_RMON_R_JAB_REG(ENET)
-#define ENET_RMON_R_P64 ENET_RMON_R_P64_REG(ENET)
-#define ENET_RMON_R_P65TO127 ENET_RMON_R_P65TO127_REG(ENET)
-#define ENET_RMON_R_P128TO255 ENET_RMON_R_P128TO255_REG(ENET)
-#define ENET_RMON_R_P256TO511 ENET_RMON_R_P256TO511_REG(ENET)
-#define ENET_RMON_R_P512TO1023 ENET_RMON_R_P512TO1023_REG(ENET)
-#define ENET_RMON_R_P1024TO2047 ENET_RMON_R_P1024TO2047_REG(ENET)
-#define ENET_RMON_R_GTE2048 ENET_RMON_R_GTE2048_REG(ENET)
-#define ENET_RMON_R_OCTETS ENET_RMON_R_OCTETS_REG(ENET)
-#define ENET_IEEE_R_DROP ENET_IEEE_R_DROP_REG(ENET)
-#define ENET_IEEE_R_FRAME_OK ENET_IEEE_R_FRAME_OK_REG(ENET)
-#define ENET_IEEE_R_CRC ENET_IEEE_R_CRC_REG(ENET)
-#define ENET_IEEE_R_ALIGN ENET_IEEE_R_ALIGN_REG(ENET)
-#define ENET_IEEE_R_MACERR ENET_IEEE_R_MACERR_REG(ENET)
-#define ENET_IEEE_R_FDXFC ENET_IEEE_R_FDXFC_REG(ENET)
-#define ENET_IEEE_R_OCTETS_OK ENET_IEEE_R_OCTETS_OK_REG(ENET)
-#define ENET_ATCR ENET_ATCR_REG(ENET)
-#define ENET_ATVR ENET_ATVR_REG(ENET)
-#define ENET_ATOFF ENET_ATOFF_REG(ENET)
-#define ENET_ATPER ENET_ATPER_REG(ENET)
-#define ENET_ATCOR ENET_ATCOR_REG(ENET)
-#define ENET_ATINC ENET_ATINC_REG(ENET)
-#define ENET_ATSTMP ENET_ATSTMP_REG(ENET)
-#define ENET_TGSR ENET_TGSR_REG(ENET)
-#define ENET_TCSR0 ENET_TCSR_REG(ENET,0)
-#define ENET_TCCR0 ENET_TCCR_REG(ENET,0)
-#define ENET_TCSR1 ENET_TCSR_REG(ENET,1)
-#define ENET_TCCR1 ENET_TCCR_REG(ENET,1)
-#define ENET_TCSR2 ENET_TCSR_REG(ENET,2)
-#define ENET_TCCR2 ENET_TCCR_REG(ENET,2)
-#define ENET_TCSR3 ENET_TCSR_REG(ENET,3)
-#define ENET_TCCR3 ENET_TCCR_REG(ENET,3)
-
-/* ENET - Register array accessors */
-#define ENET_TCSR(index) ENET_TCSR_REG(ENET,index)
-#define ENET_TCCR(index) ENET_TCCR_REG(ENET,index)
-
-/*!
- * @}
- */ /* end of group ENET_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group ENET_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- EWM Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
- * @{
- */
-
-/** EWM - Register Layout Typedef */
-typedef struct {
- __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
- __O uint8_t SERV; /**< Service Register, offset: 0x1 */
- __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
- __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
-} EWM_Type, *EWM_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- EWM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
- * @{
- */
-
-
-/* EWM - Register accessors */
-#define EWM_CTRL_REG(base) ((base)->CTRL)
-#define EWM_SERV_REG(base) ((base)->SERV)
-#define EWM_CMPL_REG(base) ((base)->CMPL)
-#define EWM_CMPH_REG(base) ((base)->CMPH)
-
-/*!
- * @}
- */ /* end of group EWM_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- EWM Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup EWM_Register_Masks EWM Register Masks
- * @{
- */
-
-/* CTRL Bit Fields */
-#define EWM_CTRL_EWMEN_MASK 0x1u
-#define EWM_CTRL_EWMEN_SHIFT 0
-#define EWM_CTRL_ASSIN_MASK 0x2u
-#define EWM_CTRL_ASSIN_SHIFT 1
-#define EWM_CTRL_INEN_MASK 0x4u
-#define EWM_CTRL_INEN_SHIFT 2
-#define EWM_CTRL_INTEN_MASK 0x8u
-#define EWM_CTRL_INTEN_SHIFT 3
-/* SERV Bit Fields */
-#define EWM_SERV_SERVICE_MASK 0xFFu
-#define EWM_SERV_SERVICE_SHIFT 0
-#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
-/* CMPL Bit Fields */
-#define EWM_CMPL_COMPAREL_MASK 0xFFu
-#define EWM_CMPL_COMPAREL_SHIFT 0
-#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
-/* CMPH Bit Fields */
-#define EWM_CMPH_COMPAREH_MASK 0xFFu
-#define EWM_CMPH_COMPAREH_SHIFT 0
-#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
-
-/*!
- * @}
- */ /* end of group EWM_Register_Masks */
-
-
-/* EWM - Peripheral instance base addresses */
-/** Peripheral EWM base address */
-#define EWM_BASE (0x40061000u)
-/** Peripheral EWM base pointer */
-#define EWM ((EWM_Type *)EWM_BASE)
-#define EWM_BASE_PTR (EWM)
-/** Array initializer of EWM peripheral base pointers */
-#define EWM_BASES { EWM }
-
-/* ----------------------------------------------------------------------------
- -- EWM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
- * @{
- */
-
-
-/* EWM - Register instance definitions */
-/* EWM */
-#define EWM_CTRL EWM_CTRL_REG(EWM)
-#define EWM_SERV EWM_SERV_REG(EWM)
-#define EWM_CMPL EWM_CMPL_REG(EWM)
-#define EWM_CMPH EWM_CMPH_REG(EWM)
-
-/*!
- * @}
- */ /* end of group EWM_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group EWM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- FB Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
- * @{
- */
-
-/** FB - Register Layout Typedef */
-typedef struct {
- struct { /* offset: 0x0, array step: 0xC */
- __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
- __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
- __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
- } CS[6];
- uint8_t RESERVED_0[24];
- __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
-} FB_Type, *FB_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- FB - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
- * @{
- */
-
-
-/* FB - Register accessors */
-#define FB_CSAR_REG(base,index) ((base)->CS[index].CSAR)
-#define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR)
-#define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR)
-#define FB_CSPMCR_REG(base) ((base)->CSPMCR)
-
-/*!
- * @}
- */ /* end of group FB_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- FB Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FB_Register_Masks FB Register Masks
- * @{
- */
-
-/* CSAR Bit Fields */
-#define FB_CSAR_BA_MASK 0xFFFF0000u
-#define FB_CSAR_BA_SHIFT 16
-#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
-/* CSMR Bit Fields */
-#define FB_CSMR_V_MASK 0x1u
-#define FB_CSMR_V_SHIFT 0
-#define FB_CSMR_WP_MASK 0x100u
-#define FB_CSMR_WP_SHIFT 8
-#define FB_CSMR_BAM_MASK 0xFFFF0000u
-#define FB_CSMR_BAM_SHIFT 16
-#define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
-/* CSCR Bit Fields */
-#define FB_CSCR_BSTW_MASK 0x8u
-#define FB_CSCR_BSTW_SHIFT 3
-#define FB_CSCR_BSTR_MASK 0x10u
-#define FB_CSCR_BSTR_SHIFT 4
-#define FB_CSCR_BEM_MASK 0x20u
-#define FB_CSCR_BEM_SHIFT 5
-#define FB_CSCR_PS_MASK 0xC0u
-#define FB_CSCR_PS_SHIFT 6
-#define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
-#define FB_CSCR_AA_MASK 0x100u
-#define FB_CSCR_AA_SHIFT 8
-#define FB_CSCR_BLS_MASK 0x200u
-#define FB_CSCR_BLS_SHIFT 9
-#define FB_CSCR_WS_MASK 0xFC00u
-#define FB_CSCR_WS_SHIFT 10
-#define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
-#define FB_CSCR_WRAH_MASK 0x30000u
-#define FB_CSCR_WRAH_SHIFT 16
-#define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
-#define FB_CSCR_RDAH_MASK 0xC0000u
-#define FB_CSCR_RDAH_SHIFT 18
-#define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
-#define FB_CSCR_ASET_MASK 0x300000u
-#define FB_CSCR_ASET_SHIFT 20
-#define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
-#define FB_CSCR_EXTS_MASK 0x400000u
-#define FB_CSCR_EXTS_SHIFT 22
-#define FB_CSCR_SWSEN_MASK 0x800000u
-#define FB_CSCR_SWSEN_SHIFT 23
-#define FB_CSCR_SWS_MASK 0xFC000000u
-#define FB_CSCR_SWS_SHIFT 26
-#define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
-/* CSPMCR Bit Fields */
-#define FB_CSPMCR_GROUP5_MASK 0xF000u
-#define FB_CSPMCR_GROUP5_SHIFT 12
-#define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
-#define FB_CSPMCR_GROUP4_MASK 0xF0000u
-#define FB_CSPMCR_GROUP4_SHIFT 16
-#define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
-#define FB_CSPMCR_GROUP3_MASK 0xF00000u
-#define FB_CSPMCR_GROUP3_SHIFT 20
-#define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
-#define FB_CSPMCR_GROUP2_MASK 0xF000000u
-#define FB_CSPMCR_GROUP2_SHIFT 24
-#define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
-#define FB_CSPMCR_GROUP1_MASK 0xF0000000u
-#define FB_CSPMCR_GROUP1_SHIFT 28
-#define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)
-
-/*!
- * @}
- */ /* end of group FB_Register_Masks */
-
-
-/* FB - Peripheral instance base addresses */
-/** Peripheral FB base address */
-#define FB_BASE (0x4000C000u)
-/** Peripheral FB base pointer */
-#define FB ((FB_Type *)FB_BASE)
-#define FB_BASE_PTR (FB)
-/** Array initializer of FB peripheral base pointers */
-#define FB_BASES { FB }
-
-/* ----------------------------------------------------------------------------
- -- FB - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
- * @{
- */
-
-
-/* FB - Register instance definitions */
-/* FB */
-#define FB_CSAR0 FB_CSAR_REG(FB,0)
-#define FB_CSMR0 FB_CSMR_REG(FB,0)
-#define FB_CSCR0 FB_CSCR_REG(FB,0)
-#define FB_CSAR1 FB_CSAR_REG(FB,1)
-#define FB_CSMR1 FB_CSMR_REG(FB,1)
-#define FB_CSCR1 FB_CSCR_REG(FB,1)
-#define FB_CSAR2 FB_CSAR_REG(FB,2)
-#define FB_CSMR2 FB_CSMR_REG(FB,2)
-#define FB_CSCR2 FB_CSCR_REG(FB,2)
-#define FB_CSAR3 FB_CSAR_REG(FB,3)
-#define FB_CSMR3 FB_CSMR_REG(FB,3)
-#define FB_CSCR3 FB_CSCR_REG(FB,3)
-#define FB_CSAR4 FB_CSAR_REG(FB,4)
-#define FB_CSMR4 FB_CSMR_REG(FB,4)
-#define FB_CSCR4 FB_CSCR_REG(FB,4)
-#define FB_CSAR5 FB_CSAR_REG(FB,5)
-#define FB_CSMR5 FB_CSMR_REG(FB,5)
-#define FB_CSCR5 FB_CSCR_REG(FB,5)
-#define FB_CSPMCR FB_CSPMCR_REG(FB)
-
-/* FB - Register array accessors */
-#define FB_CSAR(index) FB_CSAR_REG(FB,index)
-#define FB_CSMR(index) FB_CSMR_REG(FB,index)
-#define FB_CSCR(index) FB_CSCR_REG(FB,index)
-
-/*!
- * @}
- */ /* end of group FB_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group FB_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- FMC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
- * @{
- */
-
-/** FMC - Register Layout Typedef */
-typedef struct {
- __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
- __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */
- __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */
- uint8_t RESERVED_0[244];
- __IO uint32_t TAGVDW0S[4]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
- __IO uint32_t TAGVDW1S[4]; /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */
- __IO uint32_t TAGVDW2S[4]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
- __IO uint32_t TAGVDW3S[4]; /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */
- uint8_t RESERVED_1[192];
- struct { /* offset: 0x200, array step: index*0x20, index2*0x8 */
- __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8 */
- __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8 */
- } SET[4][4];
-} FMC_Type, *FMC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- FMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
- * @{
- */
-
-
-/* FMC - Register accessors */
-#define FMC_PFAPR_REG(base) ((base)->PFAPR)
-#define FMC_PFB0CR_REG(base) ((base)->PFB0CR)
-#define FMC_PFB1CR_REG(base) ((base)->PFB1CR)
-#define FMC_TAGVDW0S_REG(base,index) ((base)->TAGVDW0S[index])
-#define FMC_TAGVDW1S_REG(base,index) ((base)->TAGVDW1S[index])
-#define FMC_TAGVDW2S_REG(base,index) ((base)->TAGVDW2S[index])
-#define FMC_TAGVDW3S_REG(base,index) ((base)->TAGVDW3S[index])
-#define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U)
-#define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L)
-
-/*!
- * @}
- */ /* end of group FMC_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- FMC Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FMC_Register_Masks FMC Register Masks
- * @{
- */
-
-/* PFAPR Bit Fields */
-#define FMC_PFAPR_M0AP_MASK 0x3u
-#define FMC_PFAPR_M0AP_SHIFT 0
-#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
-#define FMC_PFAPR_M1AP_MASK 0xCu
-#define FMC_PFAPR_M1AP_SHIFT 2
-#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
-#define FMC_PFAPR_M2AP_MASK 0x30u
-#define FMC_PFAPR_M2AP_SHIFT 4
-#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
-#define FMC_PFAPR_M3AP_MASK 0xC0u
-#define FMC_PFAPR_M3AP_SHIFT 6
-#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
-#define FMC_PFAPR_M4AP_MASK 0x300u
-#define FMC_PFAPR_M4AP_SHIFT 8
-#define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
-#define FMC_PFAPR_M5AP_MASK 0xC00u
-#define FMC_PFAPR_M5AP_SHIFT 10
-#define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
-#define FMC_PFAPR_M6AP_MASK 0x3000u
-#define FMC_PFAPR_M6AP_SHIFT 12
-#define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
-#define FMC_PFAPR_M7AP_MASK 0xC000u
-#define FMC_PFAPR_M7AP_SHIFT 14
-#define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
-#define FMC_PFAPR_M0PFD_MASK 0x10000u
-#define FMC_PFAPR_M0PFD_SHIFT 16
-#define FMC_PFAPR_M1PFD_MASK 0x20000u
-#define FMC_PFAPR_M1PFD_SHIFT 17
-#define FMC_PFAPR_M2PFD_MASK 0x40000u
-#define FMC_PFAPR_M2PFD_SHIFT 18
-#define FMC_PFAPR_M3PFD_MASK 0x80000u
-#define FMC_PFAPR_M3PFD_SHIFT 19
-#define FMC_PFAPR_M4PFD_MASK 0x100000u
-#define FMC_PFAPR_M4PFD_SHIFT 20
-#define FMC_PFAPR_M5PFD_MASK 0x200000u
-#define FMC_PFAPR_M5PFD_SHIFT 21
-#define FMC_PFAPR_M6PFD_MASK 0x400000u
-#define FMC_PFAPR_M6PFD_SHIFT 22
-#define FMC_PFAPR_M7PFD_MASK 0x800000u
-#define FMC_PFAPR_M7PFD_SHIFT 23
-/* PFB0CR Bit Fields */
-#define FMC_PFB0CR_B0SEBE_MASK 0x1u
-#define FMC_PFB0CR_B0SEBE_SHIFT 0
-#define FMC_PFB0CR_B0IPE_MASK 0x2u
-#define FMC_PFB0CR_B0IPE_SHIFT 1
-#define FMC_PFB0CR_B0DPE_MASK 0x4u
-#define FMC_PFB0CR_B0DPE_SHIFT 2
-#define FMC_PFB0CR_B0ICE_MASK 0x8u
-#define FMC_PFB0CR_B0ICE_SHIFT 3
-#define FMC_PFB0CR_B0DCE_MASK 0x10u
-#define FMC_PFB0CR_B0DCE_SHIFT 4
-#define FMC_PFB0CR_CRC_MASK 0xE0u
-#define FMC_PFB0CR_CRC_SHIFT 5
-#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
-#define FMC_PFB0CR_B0MW_MASK 0x60000u
-#define FMC_PFB0CR_B0MW_SHIFT 17
-#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
-#define FMC_PFB0CR_S_B_INV_MASK 0x80000u
-#define FMC_PFB0CR_S_B_INV_SHIFT 19
-#define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
-#define FMC_PFB0CR_CINV_WAY_SHIFT 20
-#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
-#define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
-#define FMC_PFB0CR_CLCK_WAY_SHIFT 24
-#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
-#define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
-#define FMC_PFB0CR_B0RWSC_SHIFT 28
-#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
-/* PFB1CR Bit Fields */
-#define FMC_PFB1CR_B1SEBE_MASK 0x1u
-#define FMC_PFB1CR_B1SEBE_SHIFT 0
-#define FMC_PFB1CR_B1IPE_MASK 0x2u
-#define FMC_PFB1CR_B1IPE_SHIFT 1
-#define FMC_PFB1CR_B1DPE_MASK 0x4u
-#define FMC_PFB1CR_B1DPE_SHIFT 2
-#define FMC_PFB1CR_B1ICE_MASK 0x8u
-#define FMC_PFB1CR_B1ICE_SHIFT 3
-#define FMC_PFB1CR_B1DCE_MASK 0x10u
-#define FMC_PFB1CR_B1DCE_SHIFT 4
-#define FMC_PFB1CR_B1MW_MASK 0x60000u
-#define FMC_PFB1CR_B1MW_SHIFT 17
-#define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
-#define FMC_PFB1CR_B1RWSC_MASK 0xF0000000u
-#define FMC_PFB1CR_B1RWSC_SHIFT 28
-#define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
-/* TAGVDW0S Bit Fields */
-#define FMC_TAGVDW0S_valid_MASK 0x1u
-#define FMC_TAGVDW0S_valid_SHIFT 0
-#define FMC_TAGVDW0S_tag_MASK 0x7FFE0u
-#define FMC_TAGVDW0S_tag_SHIFT 5
-#define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_tag_SHIFT))&FMC_TAGVDW0S_tag_MASK)
-/* TAGVDW1S Bit Fields */
-#define FMC_TAGVDW1S_valid_MASK 0x1u
-#define FMC_TAGVDW1S_valid_SHIFT 0
-#define FMC_TAGVDW1S_tag_MASK 0x7FFE0u
-#define FMC_TAGVDW1S_tag_SHIFT 5
-#define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_tag_SHIFT))&FMC_TAGVDW1S_tag_MASK)
-/* TAGVDW2S Bit Fields */
-#define FMC_TAGVDW2S_valid_MASK 0x1u
-#define FMC_TAGVDW2S_valid_SHIFT 0
-#define FMC_TAGVDW2S_tag_MASK 0x7FFE0u
-#define FMC_TAGVDW2S_tag_SHIFT 5
-#define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_tag_SHIFT))&FMC_TAGVDW2S_tag_MASK)
-/* TAGVDW3S Bit Fields */
-#define FMC_TAGVDW3S_valid_MASK 0x1u
-#define FMC_TAGVDW3S_valid_SHIFT 0
-#define FMC_TAGVDW3S_tag_MASK 0x7FFE0u
-#define FMC_TAGVDW3S_tag_SHIFT 5
-#define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_tag_SHIFT))&FMC_TAGVDW3S_tag_MASK)
-/* DATA_U Bit Fields */
-#define FMC_DATA_U_data_MASK 0xFFFFFFFFu
-#define FMC_DATA_U_data_SHIFT 0
-#define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
-/* DATA_L Bit Fields */
-#define FMC_DATA_L_data_MASK 0xFFFFFFFFu
-#define FMC_DATA_L_data_SHIFT 0
-#define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
-
-/*!
- * @}
- */ /* end of group FMC_Register_Masks */
-
-
-/* FMC - Peripheral instance base addresses */
-/** Peripheral FMC base address */
-#define FMC_BASE (0x4001F000u)
-/** Peripheral FMC base pointer */
-#define FMC ((FMC_Type *)FMC_BASE)
-#define FMC_BASE_PTR (FMC)
-/** Array initializer of FMC peripheral base pointers */
-#define FMC_BASES { FMC }
-
-/* ----------------------------------------------------------------------------
- -- FMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
- * @{
- */
-
-
-/* FMC - Register instance definitions */
-/* FMC */
-#define FMC_PFAPR FMC_PFAPR_REG(FMC)
-#define FMC_PFB0CR FMC_PFB0CR_REG(FMC)
-#define FMC_PFB1CR FMC_PFB1CR_REG(FMC)
-#define FMC_TAGVDW0S0 FMC_TAGVDW0S_REG(FMC,0)
-#define FMC_TAGVDW0S1 FMC_TAGVDW0S_REG(FMC,1)
-#define FMC_TAGVDW0S2 FMC_TAGVDW0S_REG(FMC,2)
-#define FMC_TAGVDW0S3 FMC_TAGVDW0S_REG(FMC,3)
-#define FMC_TAGVDW1S0 FMC_TAGVDW1S_REG(FMC,0)
-#define FMC_TAGVDW1S1 FMC_TAGVDW1S_REG(FMC,1)
-#define FMC_TAGVDW1S2 FMC_TAGVDW1S_REG(FMC,2)
-#define FMC_TAGVDW1S3 FMC_TAGVDW1S_REG(FMC,3)
-#define FMC_TAGVDW2S0 FMC_TAGVDW2S_REG(FMC,0)
-#define FMC_TAGVDW2S1 FMC_TAGVDW2S_REG(FMC,1)
-#define FMC_TAGVDW2S2 FMC_TAGVDW2S_REG(FMC,2)
-#define FMC_TAGVDW2S3 FMC_TAGVDW2S_REG(FMC,3)
-#define FMC_TAGVDW3S0 FMC_TAGVDW3S_REG(FMC,0)
-#define FMC_TAGVDW3S1 FMC_TAGVDW3S_REG(FMC,1)
-#define FMC_TAGVDW3S2 FMC_TAGVDW3S_REG(FMC,2)
-#define FMC_TAGVDW3S3 FMC_TAGVDW3S_REG(FMC,3)
-#define FMC_DATAW0S0U FMC_DATA_U_REG(FMC,0,0)
-#define FMC_DATAW0S0L FMC_DATA_L_REG(FMC,0,0)
-#define FMC_DATAW0S1U FMC_DATA_U_REG(FMC,0,1)
-#define FMC_DATAW0S1L FMC_DATA_L_REG(FMC,0,1)
-#define FMC_DATAW0S2U FMC_DATA_U_REG(FMC,0,2)
-#define FMC_DATAW0S2L FMC_DATA_L_REG(FMC,0,2)
-#define FMC_DATAW0S3U FMC_DATA_U_REG(FMC,0,3)
-#define FMC_DATAW0S3L FMC_DATA_L_REG(FMC,0,3)
-#define FMC_DATAW1S0U FMC_DATA_U_REG(FMC,1,0)
-#define FMC_DATAW1S0L FMC_DATA_L_REG(FMC,1,0)
-#define FMC_DATAW1S1U FMC_DATA_U_REG(FMC,1,1)
-#define FMC_DATAW1S1L FMC_DATA_L_REG(FMC,1,1)
-#define FMC_DATAW1S2U FMC_DATA_U_REG(FMC,1,2)
-#define FMC_DATAW1S2L FMC_DATA_L_REG(FMC,1,2)
-#define FMC_DATAW1S3U FMC_DATA_U_REG(FMC,1,3)
-#define FMC_DATAW1S3L FMC_DATA_L_REG(FMC,1,3)
-#define FMC_DATAW2S0U FMC_DATA_U_REG(FMC,2,0)
-#define FMC_DATAW2S0L FMC_DATA_L_REG(FMC,2,0)
-#define FMC_DATAW2S1U FMC_DATA_U_REG(FMC,2,1)
-#define FMC_DATAW2S1L FMC_DATA_L_REG(FMC,2,1)
-#define FMC_DATAW2S2U FMC_DATA_U_REG(FMC,2,2)
-#define FMC_DATAW2S2L FMC_DATA_L_REG(FMC,2,2)
-#define FMC_DATAW2S3U FMC_DATA_U_REG(FMC,2,3)
-#define FMC_DATAW2S3L FMC_DATA_L_REG(FMC,2,3)
-#define FMC_DATAW3S0U FMC_DATA_U_REG(FMC,3,0)
-#define FMC_DATAW3S0L FMC_DATA_L_REG(FMC,3,0)
-#define FMC_DATAW3S1U FMC_DATA_U_REG(FMC,3,1)
-#define FMC_DATAW3S1L FMC_DATA_L_REG(FMC,3,1)
-#define FMC_DATAW3S2U FMC_DATA_U_REG(FMC,3,2)
-#define FMC_DATAW3S2L FMC_DATA_L_REG(FMC,3,2)
-#define FMC_DATAW3S3U FMC_DATA_U_REG(FMC,3,3)
-#define FMC_DATAW3S3L FMC_DATA_L_REG(FMC,3,3)
-
-/* FMC - Register array accessors */
-#define FMC_TAGVDW0S(index) FMC_TAGVDW0S_REG(FMC,index)
-#define FMC_TAGVDW1S(index) FMC_TAGVDW1S_REG(FMC,index)
-#define FMC_TAGVDW2S(index) FMC_TAGVDW2S_REG(FMC,index)
-#define FMC_TAGVDW3S(index) FMC_TAGVDW3S_REG(FMC,index)
-#define FMC_DATA_U(index,index2) FMC_DATA_U_REG(FMC,index,index2)
-#define FMC_DATA_L(index,index2) FMC_DATA_L_REG(FMC,index,index2)
-
-/*!
- * @}
- */ /* end of group FMC_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group FMC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- FTFE Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
- * @{
- */
-
-/** FTFE - Register Layout Typedef */
-typedef struct {
- __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
- __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
- __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
- __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
- __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
- __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
- __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
- __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
- __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
- __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
- __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
- __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
- __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
- __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
- __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
- __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
- __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
- __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
- __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
- __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
- uint8_t RESERVED_0[2];
- __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
- __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
-} FTFE_Type, *FTFE_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- FTFE - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
- * @{
- */
-
-
-/* FTFE - Register accessors */
-#define FTFE_FSTAT_REG(base) ((base)->FSTAT)
-#define FTFE_FCNFG_REG(base) ((base)->FCNFG)
-#define FTFE_FSEC_REG(base) ((base)->FSEC)
-#define FTFE_FOPT_REG(base) ((base)->FOPT)
-#define FTFE_FCCOB3_REG(base) ((base)->FCCOB3)
-#define FTFE_FCCOB2_REG(base) ((base)->FCCOB2)
-#define FTFE_FCCOB1_REG(base) ((base)->FCCOB1)
-#define FTFE_FCCOB0_REG(base) ((base)->FCCOB0)
-#define FTFE_FCCOB7_REG(base) ((base)->FCCOB7)
-#define FTFE_FCCOB6_REG(base) ((base)->FCCOB6)
-#define FTFE_FCCOB5_REG(base) ((base)->FCCOB5)
-#define FTFE_FCCOB4_REG(base) ((base)->FCCOB4)
-#define FTFE_FCCOBB_REG(base) ((base)->FCCOBB)
-#define FTFE_FCCOBA_REG(base) ((base)->FCCOBA)
-#define FTFE_FCCOB9_REG(base) ((base)->FCCOB9)
-#define FTFE_FCCOB8_REG(base) ((base)->FCCOB8)
-#define FTFE_FPROT3_REG(base) ((base)->FPROT3)
-#define FTFE_FPROT2_REG(base) ((base)->FPROT2)
-#define FTFE_FPROT1_REG(base) ((base)->FPROT1)
-#define FTFE_FPROT0_REG(base) ((base)->FPROT0)
-#define FTFE_FEPROT_REG(base) ((base)->FEPROT)
-#define FTFE_FDPROT_REG(base) ((base)->FDPROT)
-
-/*!
- * @}
- */ /* end of group FTFE_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- FTFE Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTFE_Register_Masks FTFE Register Masks
- * @{
- */
-
-/* FSTAT Bit Fields */
-#define FTFE_FSTAT_MGSTAT0_MASK 0x1u
-#define FTFE_FSTAT_MGSTAT0_SHIFT 0
-#define FTFE_FSTAT_FPVIOL_MASK 0x10u
-#define FTFE_FSTAT_FPVIOL_SHIFT 4
-#define FTFE_FSTAT_ACCERR_MASK 0x20u
-#define FTFE_FSTAT_ACCERR_SHIFT 5
-#define FTFE_FSTAT_RDCOLERR_MASK 0x40u
-#define FTFE_FSTAT_RDCOLERR_SHIFT 6
-#define FTFE_FSTAT_CCIF_MASK 0x80u
-#define FTFE_FSTAT_CCIF_SHIFT 7
-/* FCNFG Bit Fields */
-#define FTFE_FCNFG_EEERDY_MASK 0x1u
-#define FTFE_FCNFG_EEERDY_SHIFT 0
-#define FTFE_FCNFG_RAMRDY_MASK 0x2u
-#define FTFE_FCNFG_RAMRDY_SHIFT 1
-#define FTFE_FCNFG_PFLSH_MASK 0x4u
-#define FTFE_FCNFG_PFLSH_SHIFT 2
-#define FTFE_FCNFG_SWAP_MASK 0x8u
-#define FTFE_FCNFG_SWAP_SHIFT 3
-#define FTFE_FCNFG_ERSSUSP_MASK 0x10u
-#define FTFE_FCNFG_ERSSUSP_SHIFT 4
-#define FTFE_FCNFG_ERSAREQ_MASK 0x20u
-#define FTFE_FCNFG_ERSAREQ_SHIFT 5
-#define FTFE_FCNFG_RDCOLLIE_MASK 0x40u
-#define FTFE_FCNFG_RDCOLLIE_SHIFT 6
-#define FTFE_FCNFG_CCIE_MASK 0x80u
-#define FTFE_FCNFG_CCIE_SHIFT 7
-/* FSEC Bit Fields */
-#define FTFE_FSEC_SEC_MASK 0x3u
-#define FTFE_FSEC_SEC_SHIFT 0
-#define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_SEC_SHIFT))&FTFE_FSEC_SEC_MASK)
-#define FTFE_FSEC_FSLACC_MASK 0xCu
-#define FTFE_FSEC_FSLACC_SHIFT 2
-#define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_FSLACC_SHIFT))&FTFE_FSEC_FSLACC_MASK)
-#define FTFE_FSEC_MEEN_MASK 0x30u
-#define FTFE_FSEC_MEEN_SHIFT 4
-#define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_MEEN_SHIFT))&FTFE_FSEC_MEEN_MASK)
-#define FTFE_FSEC_KEYEN_MASK 0xC0u
-#define FTFE_FSEC_KEYEN_SHIFT 6
-#define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_KEYEN_SHIFT))&FTFE_FSEC_KEYEN_MASK)
-/* FOPT Bit Fields */
-#define FTFE_FOPT_OPT_MASK 0xFFu
-#define FTFE_FOPT_OPT_SHIFT 0
-#define FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FOPT_OPT_SHIFT))&FTFE_FOPT_OPT_MASK)
-/* FCCOB3 Bit Fields */
-#define FTFE_FCCOB3_CCOBn_MASK 0xFFu
-#define FTFE_FCCOB3_CCOBn_SHIFT 0
-#define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB3_CCOBn_SHIFT))&FTFE_FCCOB3_CCOBn_MASK)
-/* FCCOB2 Bit Fields */
-#define FTFE_FCCOB2_CCOBn_MASK 0xFFu
-#define FTFE_FCCOB2_CCOBn_SHIFT 0
-#define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB2_CCOBn_SHIFT))&FTFE_FCCOB2_CCOBn_MASK)
-/* FCCOB1 Bit Fields */
-#define FTFE_FCCOB1_CCOBn_MASK 0xFFu
-#define FTFE_FCCOB1_CCOBn_SHIFT 0
-#define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB1_CCOBn_SHIFT))&FTFE_FCCOB1_CCOBn_MASK)
-/* FCCOB0 Bit Fields */
-#define FTFE_FCCOB0_CCOBn_MASK 0xFFu
-#define FTFE_FCCOB0_CCOBn_SHIFT 0
-#define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB0_CCOBn_SHIFT))&FTFE_FCCOB0_CCOBn_MASK)
-/* FCCOB7 Bit Fields */
-#define FTFE_FCCOB7_CCOBn_MASK 0xFFu
-#define FTFE_FCCOB7_CCOBn_SHIFT 0
-#define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB7_CCOBn_SHIFT))&FTFE_FCCOB7_CCOBn_MASK)
-/* FCCOB6 Bit Fields */
-#define FTFE_FCCOB6_CCOBn_MASK 0xFFu
-#define FTFE_FCCOB6_CCOBn_SHIFT 0
-#define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB6_CCOBn_SHIFT))&FTFE_FCCOB6_CCOBn_MASK)
-/* FCCOB5 Bit Fields */
-#define FTFE_FCCOB5_CCOBn_MASK 0xFFu
-#define FTFE_FCCOB5_CCOBn_SHIFT 0
-#define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB5_CCOBn_SHIFT))&FTFE_FCCOB5_CCOBn_MASK)
-/* FCCOB4 Bit Fields */
-#define FTFE_FCCOB4_CCOBn_MASK 0xFFu
-#define FTFE_FCCOB4_CCOBn_SHIFT 0
-#define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB4_CCOBn_SHIFT))&FTFE_FCCOB4_CCOBn_MASK)
-/* FCCOBB Bit Fields */
-#define FTFE_FCCOBB_CCOBn_MASK 0xFFu
-#define FTFE_FCCOBB_CCOBn_SHIFT 0
-#define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBB_CCOBn_SHIFT))&FTFE_FCCOBB_CCOBn_MASK)
-/* FCCOBA Bit Fields */
-#define FTFE_FCCOBA_CCOBn_MASK 0xFFu
-#define FTFE_FCCOBA_CCOBn_SHIFT 0
-#define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBA_CCOBn_SHIFT))&FTFE_FCCOBA_CCOBn_MASK)
-/* FCCOB9 Bit Fields */
-#define FTFE_FCCOB9_CCOBn_MASK 0xFFu
-#define FTFE_FCCOB9_CCOBn_SHIFT 0
-#define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB9_CCOBn_SHIFT))&FTFE_FCCOB9_CCOBn_MASK)
-/* FCCOB8 Bit Fields */
-#define FTFE_FCCOB8_CCOBn_MASK 0xFFu
-#define FTFE_FCCOB8_CCOBn_SHIFT 0
-#define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB8_CCOBn_SHIFT))&FTFE_FCCOB8_CCOBn_MASK)
-/* FPROT3 Bit Fields */
-#define FTFE_FPROT3_PROT_MASK 0xFFu
-#define FTFE_FPROT3_PROT_SHIFT 0
-#define FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT3_PROT_SHIFT))&FTFE_FPROT3_PROT_MASK)
-/* FPROT2 Bit Fields */
-#define FTFE_FPROT2_PROT_MASK 0xFFu
-#define FTFE_FPROT2_PROT_SHIFT 0
-#define FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT2_PROT_SHIFT))&FTFE_FPROT2_PROT_MASK)
-/* FPROT1 Bit Fields */
-#define FTFE_FPROT1_PROT_MASK 0xFFu
-#define FTFE_FPROT1_PROT_SHIFT 0
-#define FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT1_PROT_SHIFT))&FTFE_FPROT1_PROT_MASK)
-/* FPROT0 Bit Fields */
-#define FTFE_FPROT0_PROT_MASK 0xFFu
-#define FTFE_FPROT0_PROT_SHIFT 0
-#define FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT0_PROT_SHIFT))&FTFE_FPROT0_PROT_MASK)
-/* FEPROT Bit Fields */
-#define FTFE_FEPROT_EPROT_MASK 0xFFu
-#define FTFE_FEPROT_EPROT_SHIFT 0
-#define FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FEPROT_EPROT_SHIFT))&FTFE_FEPROT_EPROT_MASK)
-/* FDPROT Bit Fields */
-#define FTFE_FDPROT_DPROT_MASK 0xFFu
-#define FTFE_FDPROT_DPROT_SHIFT 0
-#define FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FDPROT_DPROT_SHIFT))&FTFE_FDPROT_DPROT_MASK)
-
-/*!
- * @}
- */ /* end of group FTFE_Register_Masks */
-
-
-/* FTFE - Peripheral instance base addresses */
-/** Peripheral FTFE base address */
-#define FTFE_BASE (0x40020000u)
-/** Peripheral FTFE base pointer */
-#define FTFE ((FTFE_Type *)FTFE_BASE)
-#define FTFE_BASE_PTR (FTFE)
-/** Array initializer of FTFE peripheral base pointers */
-#define FTFE_BASES { FTFE }
-
-/* ----------------------------------------------------------------------------
- -- FTFE - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
- * @{
- */
-
-
-/* FTFE - Register instance definitions */
-/* FTFE */
-#define FTFE_FSTAT FTFE_FSTAT_REG(FTFE)
-#define FTFE_FCNFG FTFE_FCNFG_REG(FTFE)
-#define FTFE_FSEC FTFE_FSEC_REG(FTFE)
-#define FTFE_FOPT FTFE_FOPT_REG(FTFE)
-#define FTFE_FCCOB3 FTFE_FCCOB3_REG(FTFE)
-#define FTFE_FCCOB2 FTFE_FCCOB2_REG(FTFE)
-#define FTFE_FCCOB1 FTFE_FCCOB1_REG(FTFE)
-#define FTFE_FCCOB0 FTFE_FCCOB0_REG(FTFE)
-#define FTFE_FCCOB7 FTFE_FCCOB7_REG(FTFE)
-#define FTFE_FCCOB6 FTFE_FCCOB6_REG(FTFE)
-#define FTFE_FCCOB5 FTFE_FCCOB5_REG(FTFE)
-#define FTFE_FCCOB4 FTFE_FCCOB4_REG(FTFE)
-#define FTFE_FCCOBB FTFE_FCCOBB_REG(FTFE)
-#define FTFE_FCCOBA FTFE_FCCOBA_REG(FTFE)
-#define FTFE_FCCOB9 FTFE_FCCOB9_REG(FTFE)
-#define FTFE_FCCOB8 FTFE_FCCOB8_REG(FTFE)
-#define FTFE_FPROT3 FTFE_FPROT3_REG(FTFE)
-#define FTFE_FPROT2 FTFE_FPROT2_REG(FTFE)
-#define FTFE_FPROT1 FTFE_FPROT1_REG(FTFE)
-#define FTFE_FPROT0 FTFE_FPROT0_REG(FTFE)
-#define FTFE_FEPROT FTFE_FEPROT_REG(FTFE)
-#define FTFE_FDPROT FTFE_FDPROT_REG(FTFE)
-
-/*!
- * @}
- */ /* end of group FTFE_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group FTFE_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- FTM Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
- * @{
- */
-
-/** FTM - Register Layout Typedef */
-typedef struct {
- __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
- __IO uint32_t CNT; /**< Counter, offset: 0x4 */
- __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
- struct { /* offset: 0xC, array step: 0x8 */
- __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
- __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
- } CONTROLS[8];
- __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
- __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
- __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
- __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
- __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
- __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
- __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
- __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
- __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
- __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
- __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
- __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
- __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
- __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
- __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
- __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
- __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
- __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
- __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
- __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
-} FTM_Type, *FTM_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- FTM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
- * @{
- */
-
-
-/* FTM - Register accessors */
-#define FTM_SC_REG(base) ((base)->SC)
-#define FTM_CNT_REG(base) ((base)->CNT)
-#define FTM_MOD_REG(base) ((base)->MOD)
-#define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
-#define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
-#define FTM_CNTIN_REG(base) ((base)->CNTIN)
-#define FTM_STATUS_REG(base) ((base)->STATUS)
-#define FTM_MODE_REG(base) ((base)->MODE)
-#define FTM_SYNC_REG(base) ((base)->SYNC)
-#define FTM_OUTINIT_REG(base) ((base)->OUTINIT)
-#define FTM_OUTMASK_REG(base) ((base)->OUTMASK)
-#define FTM_COMBINE_REG(base) ((base)->COMBINE)
-#define FTM_DEADTIME_REG(base) ((base)->DEADTIME)
-#define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG)
-#define FTM_POL_REG(base) ((base)->POL)
-#define FTM_FMS_REG(base) ((base)->FMS)
-#define FTM_FILTER_REG(base) ((base)->FILTER)
-#define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL)
-#define FTM_QDCTRL_REG(base) ((base)->QDCTRL)
-#define FTM_CONF_REG(base) ((base)->CONF)
-#define FTM_FLTPOL_REG(base) ((base)->FLTPOL)
-#define FTM_SYNCONF_REG(base) ((base)->SYNCONF)
-#define FTM_INVCTRL_REG(base) ((base)->INVCTRL)
-#define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL)
-#define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD)
-
-/*!
- * @}
- */ /* end of group FTM_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- FTM Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTM_Register_Masks FTM Register Masks
- * @{
- */
-
-/* SC Bit Fields */
-#define FTM_SC_PS_MASK 0x7u
-#define FTM_SC_PS_SHIFT 0
-#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
-#define FTM_SC_CLKS_MASK 0x18u
-#define FTM_SC_CLKS_SHIFT 3
-#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
-#define FTM_SC_CPWMS_MASK 0x20u
-#define FTM_SC_CPWMS_SHIFT 5
-#define FTM_SC_TOIE_MASK 0x40u
-#define FTM_SC_TOIE_SHIFT 6
-#define FTM_SC_TOF_MASK 0x80u
-#define FTM_SC_TOF_SHIFT 7
-/* CNT Bit Fields */
-#define FTM_CNT_COUNT_MASK 0xFFFFu
-#define FTM_CNT_COUNT_SHIFT 0
-#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
-/* MOD Bit Fields */
-#define FTM_MOD_MOD_MASK 0xFFFFu
-#define FTM_MOD_MOD_SHIFT 0
-#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
-/* CnSC Bit Fields */
-#define FTM_CnSC_DMA_MASK 0x1u
-#define FTM_CnSC_DMA_SHIFT 0
-#define FTM_CnSC_ELSA_MASK 0x4u
-#define FTM_CnSC_ELSA_SHIFT 2
-#define FTM_CnSC_ELSB_MASK 0x8u
-#define FTM_CnSC_ELSB_SHIFT 3
-#define FTM_CnSC_MSA_MASK 0x10u
-#define FTM_CnSC_MSA_SHIFT 4
-#define FTM_CnSC_MSB_MASK 0x20u
-#define FTM_CnSC_MSB_SHIFT 5
-#define FTM_CnSC_CHIE_MASK 0x40u
-#define FTM_CnSC_CHIE_SHIFT 6
-#define FTM_CnSC_CHF_MASK 0x80u
-#define FTM_CnSC_CHF_SHIFT 7
-/* CnV Bit Fields */
-#define FTM_CnV_VAL_MASK 0xFFFFu
-#define FTM_CnV_VAL_SHIFT 0
-#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
-/* CNTIN Bit Fields */
-#define FTM_CNTIN_INIT_MASK 0xFFFFu
-#define FTM_CNTIN_INIT_SHIFT 0
-#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
-/* STATUS Bit Fields */
-#define FTM_STATUS_CH0F_MASK 0x1u
-#define FTM_STATUS_CH0F_SHIFT 0
-#define FTM_STATUS_CH1F_MASK 0x2u
-#define FTM_STATUS_CH1F_SHIFT 1
-#define FTM_STATUS_CH2F_MASK 0x4u
-#define FTM_STATUS_CH2F_SHIFT 2
-#define FTM_STATUS_CH3F_MASK 0x8u
-#define FTM_STATUS_CH3F_SHIFT 3
-#define FTM_STATUS_CH4F_MASK 0x10u
-#define FTM_STATUS_CH4F_SHIFT 4
-#define FTM_STATUS_CH5F_MASK 0x20u
-#define FTM_STATUS_CH5F_SHIFT 5
-#define FTM_STATUS_CH6F_MASK 0x40u
-#define FTM_STATUS_CH6F_SHIFT 6
-#define FTM_STATUS_CH7F_MASK 0x80u
-#define FTM_STATUS_CH7F_SHIFT 7
-/* MODE Bit Fields */
-#define FTM_MODE_FTMEN_MASK 0x1u
-#define FTM_MODE_FTMEN_SHIFT 0
-#define FTM_MODE_INIT_MASK 0x2u
-#define FTM_MODE_INIT_SHIFT 1
-#define FTM_MODE_WPDIS_MASK 0x4u
-#define FTM_MODE_WPDIS_SHIFT 2
-#define FTM_MODE_PWMSYNC_MASK 0x8u
-#define FTM_MODE_PWMSYNC_SHIFT 3
-#define FTM_MODE_CAPTEST_MASK 0x10u
-#define FTM_MODE_CAPTEST_SHIFT 4
-#define FTM_MODE_FAULTM_MASK 0x60u
-#define FTM_MODE_FAULTM_SHIFT 5
-#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
-#define FTM_MODE_FAULTIE_MASK 0x80u
-#define FTM_MODE_FAULTIE_SHIFT 7
-/* SYNC Bit Fields */
-#define FTM_SYNC_CNTMIN_MASK 0x1u
-#define FTM_SYNC_CNTMIN_SHIFT 0
-#define FTM_SYNC_CNTMAX_MASK 0x2u
-#define FTM_SYNC_CNTMAX_SHIFT 1
-#define FTM_SYNC_REINIT_MASK 0x4u
-#define FTM_SYNC_REINIT_SHIFT 2
-#define FTM_SYNC_SYNCHOM_MASK 0x8u
-#define FTM_SYNC_SYNCHOM_SHIFT 3
-#define FTM_SYNC_TRIG0_MASK 0x10u
-#define FTM_SYNC_TRIG0_SHIFT 4
-#define FTM_SYNC_TRIG1_MASK 0x20u
-#define FTM_SYNC_TRIG1_SHIFT 5
-#define FTM_SYNC_TRIG2_MASK 0x40u
-#define FTM_SYNC_TRIG2_SHIFT 6
-#define FTM_SYNC_SWSYNC_MASK 0x80u
-#define FTM_SYNC_SWSYNC_SHIFT 7
-/* OUTINIT Bit Fields */
-#define FTM_OUTINIT_CH0OI_MASK 0x1u
-#define FTM_OUTINIT_CH0OI_SHIFT 0
-#define FTM_OUTINIT_CH1OI_MASK 0x2u
-#define FTM_OUTINIT_CH1OI_SHIFT 1
-#define FTM_OUTINIT_CH2OI_MASK 0x4u
-#define FTM_OUTINIT_CH2OI_SHIFT 2
-#define FTM_OUTINIT_CH3OI_MASK 0x8u
-#define FTM_OUTINIT_CH3OI_SHIFT 3
-#define FTM_OUTINIT_CH4OI_MASK 0x10u
-#define FTM_OUTINIT_CH4OI_SHIFT 4
-#define FTM_OUTINIT_CH5OI_MASK 0x20u
-#define FTM_OUTINIT_CH5OI_SHIFT 5
-#define FTM_OUTINIT_CH6OI_MASK 0x40u
-#define FTM_OUTINIT_CH6OI_SHIFT 6
-#define FTM_OUTINIT_CH7OI_MASK 0x80u
-#define FTM_OUTINIT_CH7OI_SHIFT 7
-/* OUTMASK Bit Fields */
-#define FTM_OUTMASK_CH0OM_MASK 0x1u
-#define FTM_OUTMASK_CH0OM_SHIFT 0
-#define FTM_OUTMASK_CH1OM_MASK 0x2u
-#define FTM_OUTMASK_CH1OM_SHIFT 1
-#define FTM_OUTMASK_CH2OM_MASK 0x4u
-#define FTM_OUTMASK_CH2OM_SHIFT 2
-#define FTM_OUTMASK_CH3OM_MASK 0x8u
-#define FTM_OUTMASK_CH3OM_SHIFT 3
-#define FTM_OUTMASK_CH4OM_MASK 0x10u
-#define FTM_OUTMASK_CH4OM_SHIFT 4
-#define FTM_OUTMASK_CH5OM_MASK 0x20u
-#define FTM_OUTMASK_CH5OM_SHIFT 5
-#define FTM_OUTMASK_CH6OM_MASK 0x40u
-#define FTM_OUTMASK_CH6OM_SHIFT 6
-#define FTM_OUTMASK_CH7OM_MASK 0x80u
-#define FTM_OUTMASK_CH7OM_SHIFT 7
-/* COMBINE Bit Fields */
-#define FTM_COMBINE_COMBINE0_MASK 0x1u
-#define FTM_COMBINE_COMBINE0_SHIFT 0
-#define FTM_COMBINE_COMP0_MASK 0x2u
-#define FTM_COMBINE_COMP0_SHIFT 1
-#define FTM_COMBINE_DECAPEN0_MASK 0x4u
-#define FTM_COMBINE_DECAPEN0_SHIFT 2
-#define FTM_COMBINE_DECAP0_MASK 0x8u
-#define FTM_COMBINE_DECAP0_SHIFT 3
-#define FTM_COMBINE_DTEN0_MASK 0x10u
-#define FTM_COMBINE_DTEN0_SHIFT 4
-#define FTM_COMBINE_SYNCEN0_MASK 0x20u
-#define FTM_COMBINE_SYNCEN0_SHIFT 5
-#define FTM_COMBINE_FAULTEN0_MASK 0x40u
-#define FTM_COMBINE_FAULTEN0_SHIFT 6
-#define FTM_COMBINE_COMBINE1_MASK 0x100u
-#define FTM_COMBINE_COMBINE1_SHIFT 8
-#define FTM_COMBINE_COMP1_MASK 0x200u
-#define FTM_COMBINE_COMP1_SHIFT 9
-#define FTM_COMBINE_DECAPEN1_MASK 0x400u
-#define FTM_COMBINE_DECAPEN1_SHIFT 10
-#define FTM_COMBINE_DECAP1_MASK 0x800u
-#define FTM_COMBINE_DECAP1_SHIFT 11
-#define FTM_COMBINE_DTEN1_MASK 0x1000u
-#define FTM_COMBINE_DTEN1_SHIFT 12
-#define FTM_COMBINE_SYNCEN1_MASK 0x2000u
-#define FTM_COMBINE_SYNCEN1_SHIFT 13
-#define FTM_COMBINE_FAULTEN1_MASK 0x4000u
-#define FTM_COMBINE_FAULTEN1_SHIFT 14
-#define FTM_COMBINE_COMBINE2_MASK 0x10000u
-#define FTM_COMBINE_COMBINE2_SHIFT 16
-#define FTM_COMBINE_COMP2_MASK 0x20000u
-#define FTM_COMBINE_COMP2_SHIFT 17
-#define FTM_COMBINE_DECAPEN2_MASK 0x40000u
-#define FTM_COMBINE_DECAPEN2_SHIFT 18
-#define FTM_COMBINE_DECAP2_MASK 0x80000u
-#define FTM_COMBINE_DECAP2_SHIFT 19
-#define FTM_COMBINE_DTEN2_MASK 0x100000u
-#define FTM_COMBINE_DTEN2_SHIFT 20
-#define FTM_COMBINE_SYNCEN2_MASK 0x200000u
-#define FTM_COMBINE_SYNCEN2_SHIFT 21
-#define FTM_COMBINE_FAULTEN2_MASK 0x400000u
-#define FTM_COMBINE_FAULTEN2_SHIFT 22
-#define FTM_COMBINE_COMBINE3_MASK 0x1000000u
-#define FTM_COMBINE_COMBINE3_SHIFT 24
-#define FTM_COMBINE_COMP3_MASK 0x2000000u
-#define FTM_COMBINE_COMP3_SHIFT 25
-#define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
-#define FTM_COMBINE_DECAPEN3_SHIFT 26
-#define FTM_COMBINE_DECAP3_MASK 0x8000000u
-#define FTM_COMBINE_DECAP3_SHIFT 27
-#define FTM_COMBINE_DTEN3_MASK 0x10000000u
-#define FTM_COMBINE_DTEN3_SHIFT 28
-#define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
-#define FTM_COMBINE_SYNCEN3_SHIFT 29
-#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
-#define FTM_COMBINE_FAULTEN3_SHIFT 30
-/* DEADTIME Bit Fields */
-#define FTM_DEADTIME_DTVAL_MASK 0x3Fu
-#define FTM_DEADTIME_DTVAL_SHIFT 0
-#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
-#define FTM_DEADTIME_DTPS_MASK 0xC0u
-#define FTM_DEADTIME_DTPS_SHIFT 6
-#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
-/* EXTTRIG Bit Fields */
-#define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
-#define FTM_EXTTRIG_CH2TRIG_SHIFT 0
-#define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
-#define FTM_EXTTRIG_CH3TRIG_SHIFT 1
-#define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
-#define FTM_EXTTRIG_CH4TRIG_SHIFT 2
-#define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
-#define FTM_EXTTRIG_CH5TRIG_SHIFT 3
-#define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
-#define FTM_EXTTRIG_CH0TRIG_SHIFT 4
-#define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
-#define FTM_EXTTRIG_CH1TRIG_SHIFT 5
-#define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
-#define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
-#define FTM_EXTTRIG_TRIGF_MASK 0x80u
-#define FTM_EXTTRIG_TRIGF_SHIFT 7
-/* POL Bit Fields */
-#define FTM_POL_POL0_MASK 0x1u
-#define FTM_POL_POL0_SHIFT 0
-#define FTM_POL_POL1_MASK 0x2u
-#define FTM_POL_POL1_SHIFT 1
-#define FTM_POL_POL2_MASK 0x4u
-#define FTM_POL_POL2_SHIFT 2
-#define FTM_POL_POL3_MASK 0x8u
-#define FTM_POL_POL3_SHIFT 3
-#define FTM_POL_POL4_MASK 0x10u
-#define FTM_POL_POL4_SHIFT 4
-#define FTM_POL_POL5_MASK 0x20u
-#define FTM_POL_POL5_SHIFT 5
-#define FTM_POL_POL6_MASK 0x40u
-#define FTM_POL_POL6_SHIFT 6
-#define FTM_POL_POL7_MASK 0x80u
-#define FTM_POL_POL7_SHIFT 7
-/* FMS Bit Fields */
-#define FTM_FMS_FAULTF0_MASK 0x1u
-#define FTM_FMS_FAULTF0_SHIFT 0
-#define FTM_FMS_FAULTF1_MASK 0x2u
-#define FTM_FMS_FAULTF1_SHIFT 1
-#define FTM_FMS_FAULTF2_MASK 0x4u
-#define FTM_FMS_FAULTF2_SHIFT 2
-#define FTM_FMS_FAULTF3_MASK 0x8u
-#define FTM_FMS_FAULTF3_SHIFT 3
-#define FTM_FMS_FAULTIN_MASK 0x20u
-#define FTM_FMS_FAULTIN_SHIFT 5
-#define FTM_FMS_WPEN_MASK 0x40u
-#define FTM_FMS_WPEN_SHIFT 6
-#define FTM_FMS_FAULTF_MASK 0x80u
-#define FTM_FMS_FAULTF_SHIFT 7
-/* FILTER Bit Fields */
-#define FTM_FILTER_CH0FVAL_MASK 0xFu
-#define FTM_FILTER_CH0FVAL_SHIFT 0
-#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
-#define FTM_FILTER_CH1FVAL_MASK 0xF0u
-#define FTM_FILTER_CH1FVAL_SHIFT 4
-#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
-#define FTM_FILTER_CH2FVAL_MASK 0xF00u
-#define FTM_FILTER_CH2FVAL_SHIFT 8
-#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
-#define FTM_FILTER_CH3FVAL_MASK 0xF000u
-#define FTM_FILTER_CH3FVAL_SHIFT 12
-#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
-/* FLTCTRL Bit Fields */
-#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
-#define FTM_FLTCTRL_FAULT0EN_SHIFT 0
-#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
-#define FTM_FLTCTRL_FAULT1EN_SHIFT 1
-#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
-#define FTM_FLTCTRL_FAULT2EN_SHIFT 2
-#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
-#define FTM_FLTCTRL_FAULT3EN_SHIFT 3
-#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
-#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
-#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
-#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
-#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
-#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
-#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
-#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
-#define FTM_FLTCTRL_FFVAL_MASK 0xF00u
-#define FTM_FLTCTRL_FFVAL_SHIFT 8
-#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
-/* QDCTRL Bit Fields */
-#define FTM_QDCTRL_QUADEN_MASK 0x1u
-#define FTM_QDCTRL_QUADEN_SHIFT 0
-#define FTM_QDCTRL_TOFDIR_MASK 0x2u
-#define FTM_QDCTRL_TOFDIR_SHIFT 1
-#define FTM_QDCTRL_QUADIR_MASK 0x4u
-#define FTM_QDCTRL_QUADIR_SHIFT 2
-#define FTM_QDCTRL_QUADMODE_MASK 0x8u
-#define FTM_QDCTRL_QUADMODE_SHIFT 3
-#define FTM_QDCTRL_PHBPOL_MASK 0x10u
-#define FTM_QDCTRL_PHBPOL_SHIFT 4
-#define FTM_QDCTRL_PHAPOL_MASK 0x20u
-#define FTM_QDCTRL_PHAPOL_SHIFT 5
-#define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
-#define FTM_QDCTRL_PHBFLTREN_SHIFT 6
-#define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
-#define FTM_QDCTRL_PHAFLTREN_SHIFT 7
-/* CONF Bit Fields */
-#define FTM_CONF_NUMTOF_MASK 0x1Fu
-#define FTM_CONF_NUMTOF_SHIFT 0
-#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
-#define FTM_CONF_BDMMODE_MASK 0xC0u
-#define FTM_CONF_BDMMODE_SHIFT 6
-#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
-#define FTM_CONF_GTBEEN_MASK 0x200u
-#define FTM_CONF_GTBEEN_SHIFT 9
-#define FTM_CONF_GTBEOUT_MASK 0x400u
-#define FTM_CONF_GTBEOUT_SHIFT 10
-/* FLTPOL Bit Fields */
-#define FTM_FLTPOL_FLT0POL_MASK 0x1u
-#define FTM_FLTPOL_FLT0POL_SHIFT 0
-#define FTM_FLTPOL_FLT1POL_MASK 0x2u
-#define FTM_FLTPOL_FLT1POL_SHIFT 1
-#define FTM_FLTPOL_FLT2POL_MASK 0x4u
-#define FTM_FLTPOL_FLT2POL_SHIFT 2
-#define FTM_FLTPOL_FLT3POL_MASK 0x8u
-#define FTM_FLTPOL_FLT3POL_SHIFT 3
-/* SYNCONF Bit Fields */
-#define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
-#define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
-#define FTM_SYNCONF_CNTINC_MASK 0x4u
-#define FTM_SYNCONF_CNTINC_SHIFT 2
-#define FTM_SYNCONF_INVC_MASK 0x10u
-#define FTM_SYNCONF_INVC_SHIFT 4
-#define FTM_SYNCONF_SWOC_MASK 0x20u
-#define FTM_SYNCONF_SWOC_SHIFT 5
-#define FTM_SYNCONF_SYNCMODE_MASK 0x80u
-#define FTM_SYNCONF_SYNCMODE_SHIFT 7
-#define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
-#define FTM_SYNCONF_SWRSTCNT_SHIFT 8
-#define FTM_SYNCONF_SWWRBUF_MASK 0x200u
-#define FTM_SYNCONF_SWWRBUF_SHIFT 9
-#define FTM_SYNCONF_SWOM_MASK 0x400u
-#define FTM_SYNCONF_SWOM_SHIFT 10
-#define FTM_SYNCONF_SWINVC_MASK 0x800u
-#define FTM_SYNCONF_SWINVC_SHIFT 11
-#define FTM_SYNCONF_SWSOC_MASK 0x1000u
-#define FTM_SYNCONF_SWSOC_SHIFT 12
-#define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
-#define FTM_SYNCONF_HWRSTCNT_SHIFT 16
-#define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
-#define FTM_SYNCONF_HWWRBUF_SHIFT 17
-#define FTM_SYNCONF_HWOM_MASK 0x40000u
-#define FTM_SYNCONF_HWOM_SHIFT 18
-#define FTM_SYNCONF_HWINVC_MASK 0x80000u
-#define FTM_SYNCONF_HWINVC_SHIFT 19
-#define FTM_SYNCONF_HWSOC_MASK 0x100000u
-#define FTM_SYNCONF_HWSOC_SHIFT 20
-/* INVCTRL Bit Fields */
-#define FTM_INVCTRL_INV0EN_MASK 0x1u
-#define FTM_INVCTRL_INV0EN_SHIFT 0
-#define FTM_INVCTRL_INV1EN_MASK 0x2u
-#define FTM_INVCTRL_INV1EN_SHIFT 1
-#define FTM_INVCTRL_INV2EN_MASK 0x4u
-#define FTM_INVCTRL_INV2EN_SHIFT 2
-#define FTM_INVCTRL_INV3EN_MASK 0x8u
-#define FTM_INVCTRL_INV3EN_SHIFT 3
-/* SWOCTRL Bit Fields */
-#define FTM_SWOCTRL_CH0OC_MASK 0x1u
-#define FTM_SWOCTRL_CH0OC_SHIFT 0
-#define FTM_SWOCTRL_CH1OC_MASK 0x2u
-#define FTM_SWOCTRL_CH1OC_SHIFT 1
-#define FTM_SWOCTRL_CH2OC_MASK 0x4u
-#define FTM_SWOCTRL_CH2OC_SHIFT 2
-#define FTM_SWOCTRL_CH3OC_MASK 0x8u
-#define FTM_SWOCTRL_CH3OC_SHIFT 3
-#define FTM_SWOCTRL_CH4OC_MASK 0x10u
-#define FTM_SWOCTRL_CH4OC_SHIFT 4
-#define FTM_SWOCTRL_CH5OC_MASK 0x20u
-#define FTM_SWOCTRL_CH5OC_SHIFT 5
-#define FTM_SWOCTRL_CH6OC_MASK 0x40u
-#define FTM_SWOCTRL_CH6OC_SHIFT 6
-#define FTM_SWOCTRL_CH7OC_MASK 0x80u
-#define FTM_SWOCTRL_CH7OC_SHIFT 7
-#define FTM_SWOCTRL_CH0OCV_MASK 0x100u
-#define FTM_SWOCTRL_CH0OCV_SHIFT 8
-#define FTM_SWOCTRL_CH1OCV_MASK 0x200u
-#define FTM_SWOCTRL_CH1OCV_SHIFT 9
-#define FTM_SWOCTRL_CH2OCV_MASK 0x400u
-#define FTM_SWOCTRL_CH2OCV_SHIFT 10
-#define FTM_SWOCTRL_CH3OCV_MASK 0x800u
-#define FTM_SWOCTRL_CH3OCV_SHIFT 11
-#define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
-#define FTM_SWOCTRL_CH4OCV_SHIFT 12
-#define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
-#define FTM_SWOCTRL_CH5OCV_SHIFT 13
-#define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
-#define FTM_SWOCTRL_CH6OCV_SHIFT 14
-#define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
-#define FTM_SWOCTRL_CH7OCV_SHIFT 15
-/* PWMLOAD Bit Fields */
-#define FTM_PWMLOAD_CH0SEL_MASK 0x1u
-#define FTM_PWMLOAD_CH0SEL_SHIFT 0
-#define FTM_PWMLOAD_CH1SEL_MASK 0x2u
-#define FTM_PWMLOAD_CH1SEL_SHIFT 1
-#define FTM_PWMLOAD_CH2SEL_MASK 0x4u
-#define FTM_PWMLOAD_CH2SEL_SHIFT 2
-#define FTM_PWMLOAD_CH3SEL_MASK 0x8u
-#define FTM_PWMLOAD_CH3SEL_SHIFT 3
-#define FTM_PWMLOAD_CH4SEL_MASK 0x10u
-#define FTM_PWMLOAD_CH4SEL_SHIFT 4
-#define FTM_PWMLOAD_CH5SEL_MASK 0x20u
-#define FTM_PWMLOAD_CH5SEL_SHIFT 5
-#define FTM_PWMLOAD_CH6SEL_MASK 0x40u
-#define FTM_PWMLOAD_CH6SEL_SHIFT 6
-#define FTM_PWMLOAD_CH7SEL_MASK 0x80u
-#define FTM_PWMLOAD_CH7SEL_SHIFT 7
-#define FTM_PWMLOAD_LDOK_MASK 0x200u
-#define FTM_PWMLOAD_LDOK_SHIFT 9
-
-/*!
- * @}
- */ /* end of group FTM_Register_Masks */
-
-
-/* FTM - Peripheral instance base addresses */
-/** Peripheral FTM0 base address */
-#define FTM0_BASE (0x40038000u)
-/** Peripheral FTM0 base pointer */
-#define FTM0 ((FTM_Type *)FTM0_BASE)
-#define FTM0_BASE_PTR (FTM0)
-/** Peripheral FTM1 base address */
-#define FTM1_BASE (0x40039000u)
-/** Peripheral FTM1 base pointer */
-#define FTM1 ((FTM_Type *)FTM1_BASE)
-#define FTM1_BASE_PTR (FTM1)
-/** Peripheral FTM2 base address */
-#define FTM2_BASE (0x4003A000u)
-/** Peripheral FTM2 base pointer */
-#define FTM2 ((FTM_Type *)FTM2_BASE)
-#define FTM2_BASE_PTR (FTM2)
-/** Peripheral FTM3 base address */
-#define FTM3_BASE (0x400B9000u)
-/** Peripheral FTM3 base pointer */
-#define FTM3 ((FTM_Type *)FTM3_BASE)
-#define FTM3_BASE_PTR (FTM3)
-/** Array initializer of FTM peripheral base pointers */
-#define FTM_BASES { FTM0, FTM1, FTM2, FTM3 }
-
-/* ----------------------------------------------------------------------------
- -- FTM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
- * @{
- */
-
-
-/* FTM - Register instance definitions */
-/* FTM0 */
-#define FTM0_SC FTM_SC_REG(FTM0)
-#define FTM0_CNT FTM_CNT_REG(FTM0)
-#define FTM0_MOD FTM_MOD_REG(FTM0)
-#define FTM0_C0SC FTM_CnSC_REG(FTM0,0)
-#define FTM0_C0V FTM_CnV_REG(FTM0,0)
-#define FTM0_C1SC FTM_CnSC_REG(FTM0,1)
-#define FTM0_C1V FTM_CnV_REG(FTM0,1)
-#define FTM0_C2SC FTM_CnSC_REG(FTM0,2)
-#define FTM0_C2V FTM_CnV_REG(FTM0,2)
-#define FTM0_C3SC FTM_CnSC_REG(FTM0,3)
-#define FTM0_C3V FTM_CnV_REG(FTM0,3)
-#define FTM0_C4SC FTM_CnSC_REG(FTM0,4)
-#define FTM0_C4V FTM_CnV_REG(FTM0,4)
-#define FTM0_C5SC FTM_CnSC_REG(FTM0,5)
-#define FTM0_C5V FTM_CnV_REG(FTM0,5)
-#define FTM0_C6SC FTM_CnSC_REG(FTM0,6)
-#define FTM0_C6V FTM_CnV_REG(FTM0,6)
-#define FTM0_C7SC FTM_CnSC_REG(FTM0,7)
-#define FTM0_C7V FTM_CnV_REG(FTM0,7)
-#define FTM0_CNTIN FTM_CNTIN_REG(FTM0)
-#define FTM0_STATUS FTM_STATUS_REG(FTM0)
-#define FTM0_MODE FTM_MODE_REG(FTM0)
-#define FTM0_SYNC FTM_SYNC_REG(FTM0)
-#define FTM0_OUTINIT FTM_OUTINIT_REG(FTM0)
-#define FTM0_OUTMASK FTM_OUTMASK_REG(FTM0)
-#define FTM0_COMBINE FTM_COMBINE_REG(FTM0)
-#define FTM0_DEADTIME FTM_DEADTIME_REG(FTM0)
-#define FTM0_EXTTRIG FTM_EXTTRIG_REG(FTM0)
-#define FTM0_POL FTM_POL_REG(FTM0)
-#define FTM0_FMS FTM_FMS_REG(FTM0)
-#define FTM0_FILTER FTM_FILTER_REG(FTM0)
-#define FTM0_FLTCTRL FTM_FLTCTRL_REG(FTM0)
-#define FTM0_QDCTRL FTM_QDCTRL_REG(FTM0)
-#define FTM0_CONF FTM_CONF_REG(FTM0)
-#define FTM0_FLTPOL FTM_FLTPOL_REG(FTM0)
-#define FTM0_SYNCONF FTM_SYNCONF_REG(FTM0)
-#define FTM0_INVCTRL FTM_INVCTRL_REG(FTM0)
-#define FTM0_SWOCTRL FTM_SWOCTRL_REG(FTM0)
-#define FTM0_PWMLOAD FTM_PWMLOAD_REG(FTM0)
-/* FTM1 */
-#define FTM1_SC FTM_SC_REG(FTM1)
-#define FTM1_CNT FTM_CNT_REG(FTM1)
-#define FTM1_MOD FTM_MOD_REG(FTM1)
-#define FTM1_C0SC FTM_CnSC_REG(FTM1,0)
-#define FTM1_C0V FTM_CnV_REG(FTM1,0)
-#define FTM1_C1SC FTM_CnSC_REG(FTM1,1)
-#define FTM1_C1V FTM_CnV_REG(FTM1,1)
-#define FTM1_CNTIN FTM_CNTIN_REG(FTM1)
-#define FTM1_STATUS FTM_STATUS_REG(FTM1)
-#define FTM1_MODE FTM_MODE_REG(FTM1)
-#define FTM1_SYNC FTM_SYNC_REG(FTM1)
-#define FTM1_OUTINIT FTM_OUTINIT_REG(FTM1)
-#define FTM1_OUTMASK FTM_OUTMASK_REG(FTM1)
-#define FTM1_COMBINE FTM_COMBINE_REG(FTM1)
-#define FTM1_DEADTIME FTM_DEADTIME_REG(FTM1)
-#define FTM1_EXTTRIG FTM_EXTTRIG_REG(FTM1)
-#define FTM1_POL FTM_POL_REG(FTM1)
-#define FTM1_FMS FTM_FMS_REG(FTM1)
-#define FTM1_FILTER FTM_FILTER_REG(FTM1)
-#define FTM1_FLTCTRL FTM_FLTCTRL_REG(FTM1)
-#define FTM1_QDCTRL FTM_QDCTRL_REG(FTM1)
-#define FTM1_CONF FTM_CONF_REG(FTM1)
-#define FTM1_FLTPOL FTM_FLTPOL_REG(FTM1)
-#define FTM1_SYNCONF FTM_SYNCONF_REG(FTM1)
-#define FTM1_INVCTRL FTM_INVCTRL_REG(FTM1)
-#define FTM1_SWOCTRL FTM_SWOCTRL_REG(FTM1)
-#define FTM1_PWMLOAD FTM_PWMLOAD_REG(FTM1)
-/* FTM2 */
-#define FTM2_SC FTM_SC_REG(FTM2)
-#define FTM2_CNT FTM_CNT_REG(FTM2)
-#define FTM2_MOD FTM_MOD_REG(FTM2)
-#define FTM2_C0SC FTM_CnSC_REG(FTM2,0)
-#define FTM2_C0V FTM_CnV_REG(FTM2,0)
-#define FTM2_C1SC FTM_CnSC_REG(FTM2,1)
-#define FTM2_C1V FTM_CnV_REG(FTM2,1)
-#define FTM2_CNTIN FTM_CNTIN_REG(FTM2)
-#define FTM2_STATUS FTM_STATUS_REG(FTM2)
-#define FTM2_MODE FTM_MODE_REG(FTM2)
-#define FTM2_SYNC FTM_SYNC_REG(FTM2)
-#define FTM2_OUTINIT FTM_OUTINIT_REG(FTM2)
-#define FTM2_OUTMASK FTM_OUTMASK_REG(FTM2)
-#define FTM2_COMBINE FTM_COMBINE_REG(FTM2)
-#define FTM2_DEADTIME FTM_DEADTIME_REG(FTM2)
-#define FTM2_EXTTRIG FTM_EXTTRIG_REG(FTM2)
-#define FTM2_POL FTM_POL_REG(FTM2)
-#define FTM2_FMS FTM_FMS_REG(FTM2)
-#define FTM2_FILTER FTM_FILTER_REG(FTM2)
-#define FTM2_FLTCTRL FTM_FLTCTRL_REG(FTM2)
-#define FTM2_QDCTRL FTM_QDCTRL_REG(FTM2)
-#define FTM2_CONF FTM_CONF_REG(FTM2)
-#define FTM2_FLTPOL FTM_FLTPOL_REG(FTM2)
-#define FTM2_SYNCONF FTM_SYNCONF_REG(FTM2)
-#define FTM2_INVCTRL FTM_INVCTRL_REG(FTM2)
-#define FTM2_SWOCTRL FTM_SWOCTRL_REG(FTM2)
-#define FTM2_PWMLOAD FTM_PWMLOAD_REG(FTM2)
-/* FTM3 */
-#define FTM3_SC FTM_SC_REG(FTM3)
-#define FTM3_CNT FTM_CNT_REG(FTM3)
-#define FTM3_MOD FTM_MOD_REG(FTM3)
-#define FTM3_C0SC FTM_CnSC_REG(FTM3,0)
-#define FTM3_C0V FTM_CnV_REG(FTM3,0)
-#define FTM3_C1SC FTM_CnSC_REG(FTM3,1)
-#define FTM3_C1V FTM_CnV_REG(FTM3,1)
-#define FTM3_C2SC FTM_CnSC_REG(FTM3,2)
-#define FTM3_C2V FTM_CnV_REG(FTM3,2)
-#define FTM3_C3SC FTM_CnSC_REG(FTM3,3)
-#define FTM3_C3V FTM_CnV_REG(FTM3,3)
-#define FTM3_C4SC FTM_CnSC_REG(FTM3,4)
-#define FTM3_C4V FTM_CnV_REG(FTM3,4)
-#define FTM3_C5SC FTM_CnSC_REG(FTM3,5)
-#define FTM3_C5V FTM_CnV_REG(FTM3,5)
-#define FTM3_C6SC FTM_CnSC_REG(FTM3,6)
-#define FTM3_C6V FTM_CnV_REG(FTM3,6)
-#define FTM3_C7SC FTM_CnSC_REG(FTM3,7)
-#define FTM3_C7V FTM_CnV_REG(FTM3,7)
-#define FTM3_CNTIN FTM_CNTIN_REG(FTM3)
-#define FTM3_STATUS FTM_STATUS_REG(FTM3)
-#define FTM3_MODE FTM_MODE_REG(FTM3)
-#define FTM3_SYNC FTM_SYNC_REG(FTM3)
-#define FTM3_OUTINIT FTM_OUTINIT_REG(FTM3)
-#define FTM3_OUTMASK FTM_OUTMASK_REG(FTM3)
-#define FTM3_COMBINE FTM_COMBINE_REG(FTM3)
-#define FTM3_DEADTIME FTM_DEADTIME_REG(FTM3)
-#define FTM3_EXTTRIG FTM_EXTTRIG_REG(FTM3)
-#define FTM3_POL FTM_POL_REG(FTM3)
-#define FTM3_FMS FTM_FMS_REG(FTM3)
-#define FTM3_FILTER FTM_FILTER_REG(FTM3)
-#define FTM3_FLTCTRL FTM_FLTCTRL_REG(FTM3)
-#define FTM3_QDCTRL FTM_QDCTRL_REG(FTM3)
-#define FTM3_CONF FTM_CONF_REG(FTM3)
-#define FTM3_FLTPOL FTM_FLTPOL_REG(FTM3)
-#define FTM3_SYNCONF FTM_SYNCONF_REG(FTM3)
-#define FTM3_INVCTRL FTM_INVCTRL_REG(FTM3)
-#define FTM3_SWOCTRL FTM_SWOCTRL_REG(FTM3)
-#define FTM3_PWMLOAD FTM_PWMLOAD_REG(FTM3)
-
-/* FTM - Register array accessors */
-#define FTM0_CnSC(index) FTM_CnSC_REG(FTM0,index)
-#define FTM1_CnSC(index) FTM_CnSC_REG(FTM1,index)
-#define FTM2_CnSC(index) FTM_CnSC_REG(FTM2,index)
-#define FTM3_CnSC(index) FTM_CnSC_REG(FTM3,index)
-#define FTM0_CnV(index) FTM_CnV_REG(FTM0,index)
-#define FTM1_CnV(index) FTM_CnV_REG(FTM1,index)
-#define FTM2_CnV(index) FTM_CnV_REG(FTM2,index)
-#define FTM3_CnV(index) FTM_CnV_REG(FTM3,index)
-
-/*!
- * @}
- */ /* end of group FTM_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group FTM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- GPIO Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
- * @{
- */
-
-/** GPIO - Register Layout Typedef */
-typedef struct {
- __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
- __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
- __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
- __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
- __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
- __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
-} GPIO_Type, *GPIO_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- GPIO - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
- * @{
- */
-
-
-/* GPIO - Register accessors */
-#define GPIO_PDOR_REG(base) ((base)->PDOR)
-#define GPIO_PSOR_REG(base) ((base)->PSOR)
-#define GPIO_PCOR_REG(base) ((base)->PCOR)
-#define GPIO_PTOR_REG(base) ((base)->PTOR)
-#define GPIO_PDIR_REG(base) ((base)->PDIR)
-#define GPIO_PDDR_REG(base) ((base)->PDDR)
-
-/*!
- * @}
- */ /* end of group GPIO_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- GPIO Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup GPIO_Register_Masks GPIO Register Masks
- * @{
- */
-
-/* PDOR Bit Fields */
-#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
-#define GPIO_PDOR_PDO_SHIFT 0
-#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
-/* PSOR Bit Fields */
-#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
-#define GPIO_PSOR_PTSO_SHIFT 0
-#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
-/* PCOR Bit Fields */
-#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
-#define GPIO_PCOR_PTCO_SHIFT 0
-#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
-/* PTOR Bit Fields */
-#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
-#define GPIO_PTOR_PTTO_SHIFT 0
-#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
-/* PDIR Bit Fields */
-#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
-#define GPIO_PDIR_PDI_SHIFT 0
-#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
-/* PDDR Bit Fields */
-#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
-#define GPIO_PDDR_PDD_SHIFT 0
-#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
-
-/*!
- * @}
- */ /* end of group GPIO_Register_Masks */
-
-
-/* GPIO - Peripheral instance base addresses */
-/** Peripheral PTA base address */
-#define PTA_BASE (0x400FF000u)
-/** Peripheral PTA base pointer */
-#define PTA ((GPIO_Type *)PTA_BASE)
-#define PTA_BASE_PTR (PTA)
-/** Peripheral PTB base address */
-#define PTB_BASE (0x400FF040u)
-/** Peripheral PTB base pointer */
-#define PTB ((GPIO_Type *)PTB_BASE)
-#define PTB_BASE_PTR (PTB)
-/** Peripheral PTC base address */
-#define PTC_BASE (0x400FF080u)
-/** Peripheral PTC base pointer */
-#define PTC ((GPIO_Type *)PTC_BASE)
-#define PTC_BASE_PTR (PTC)
-/** Peripheral PTD base address */
-#define PTD_BASE (0x400FF0C0u)
-/** Peripheral PTD base pointer */
-#define PTD ((GPIO_Type *)PTD_BASE)
-#define PTD_BASE_PTR (PTD)
-/** Peripheral PTE base address */
-#define PTE_BASE (0x400FF100u)
-/** Peripheral PTE base pointer */
-#define PTE ((GPIO_Type *)PTE_BASE)
-#define PTE_BASE_PTR (PTE)
-/** Array initializer of GPIO peripheral base pointers */
-#define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
-
-/* ----------------------------------------------------------------------------
- -- GPIO - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
- * @{
- */
-
-
-/* GPIO - Register instance definitions */
-/* PTA */
-#define GPIOA_PDOR GPIO_PDOR_REG(PTA)
-#define GPIOA_PSOR GPIO_PSOR_REG(PTA)
-#define GPIOA_PCOR GPIO_PCOR_REG(PTA)
-#define GPIOA_PTOR GPIO_PTOR_REG(PTA)
-#define GPIOA_PDIR GPIO_PDIR_REG(PTA)
-#define GPIOA_PDDR GPIO_PDDR_REG(PTA)
-/* PTB */
-#define GPIOB_PDOR GPIO_PDOR_REG(PTB)
-#define GPIOB_PSOR GPIO_PSOR_REG(PTB)
-#define GPIOB_PCOR GPIO_PCOR_REG(PTB)
-#define GPIOB_PTOR GPIO_PTOR_REG(PTB)
-#define GPIOB_PDIR GPIO_PDIR_REG(PTB)
-#define GPIOB_PDDR GPIO_PDDR_REG(PTB)
-/* PTC */
-#define GPIOC_PDOR GPIO_PDOR_REG(PTC)
-#define GPIOC_PSOR GPIO_PSOR_REG(PTC)
-#define GPIOC_PCOR GPIO_PCOR_REG(PTC)
-#define GPIOC_PTOR GPIO_PTOR_REG(PTC)
-#define GPIOC_PDIR GPIO_PDIR_REG(PTC)
-#define GPIOC_PDDR GPIO_PDDR_REG(PTC)
-/* PTD */
-#define GPIOD_PDOR GPIO_PDOR_REG(PTD)
-#define GPIOD_PSOR GPIO_PSOR_REG(PTD)
-#define GPIOD_PCOR GPIO_PCOR_REG(PTD)
-#define GPIOD_PTOR GPIO_PTOR_REG(PTD)
-#define GPIOD_PDIR GPIO_PDIR_REG(PTD)
-#define GPIOD_PDDR GPIO_PDDR_REG(PTD)
-/* PTE */
-#define GPIOE_PDOR GPIO_PDOR_REG(PTE)
-#define GPIOE_PSOR GPIO_PSOR_REG(PTE)
-#define GPIOE_PCOR GPIO_PCOR_REG(PTE)
-#define GPIOE_PTOR GPIO_PTOR_REG(PTE)
-#define GPIOE_PDIR GPIO_PDIR_REG(PTE)
-#define GPIOE_PDDR GPIO_PDDR_REG(PTE)
-
-/*!
- * @}
- */ /* end of group GPIO_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group GPIO_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- I2C Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
- * @{
- */
-
-/** I2C - Register Layout Typedef */
-typedef struct {
- __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
- __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
- __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
- __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
- __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
- __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
- __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
- __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
- __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
- __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
- __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
- __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
-} I2C_Type, *I2C_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- I2C - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
- * @{
- */
-
-
-/* I2C - Register accessors */
-#define I2C_A1_REG(base) ((base)->A1)
-#define I2C_F_REG(base) ((base)->F)
-#define I2C_C1_REG(base) ((base)->C1)
-#define I2C_S_REG(base) ((base)->S)
-#define I2C_D_REG(base) ((base)->D)
-#define I2C_C2_REG(base) ((base)->C2)
-#define I2C_FLT_REG(base) ((base)->FLT)
-#define I2C_RA_REG(base) ((base)->RA)
-#define I2C_SMB_REG(base) ((base)->SMB)
-#define I2C_A2_REG(base) ((base)->A2)
-#define I2C_SLTH_REG(base) ((base)->SLTH)
-#define I2C_SLTL_REG(base) ((base)->SLTL)
-
-/*!
- * @}
- */ /* end of group I2C_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- I2C Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2C_Register_Masks I2C Register Masks
- * @{
- */
-
-/* A1 Bit Fields */
-#define I2C_A1_AD_MASK 0xFEu
-#define I2C_A1_AD_SHIFT 1
-#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
-/* F Bit Fields */
-#define I2C_F_ICR_MASK 0x3Fu
-#define I2C_F_ICR_SHIFT 0
-#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
-#define I2C_F_MULT_MASK 0xC0u
-#define I2C_F_MULT_SHIFT 6
-#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
-/* C1 Bit Fields */
-#define I2C_C1_DMAEN_MASK 0x1u
-#define I2C_C1_DMAEN_SHIFT 0
-#define I2C_C1_WUEN_MASK 0x2u
-#define I2C_C1_WUEN_SHIFT 1
-#define I2C_C1_RSTA_MASK 0x4u
-#define I2C_C1_RSTA_SHIFT 2
-#define I2C_C1_TXAK_MASK 0x8u
-#define I2C_C1_TXAK_SHIFT 3
-#define I2C_C1_TX_MASK 0x10u
-#define I2C_C1_TX_SHIFT 4
-#define I2C_C1_MST_MASK 0x20u
-#define I2C_C1_MST_SHIFT 5
-#define I2C_C1_IICIE_MASK 0x40u
-#define I2C_C1_IICIE_SHIFT 6
-#define I2C_C1_IICEN_MASK 0x80u
-#define I2C_C1_IICEN_SHIFT 7
-/* S Bit Fields */
-#define I2C_S_RXAK_MASK 0x1u
-#define I2C_S_RXAK_SHIFT 0
-#define I2C_S_IICIF_MASK 0x2u
-#define I2C_S_IICIF_SHIFT 1
-#define I2C_S_SRW_MASK 0x4u
-#define I2C_S_SRW_SHIFT 2
-#define I2C_S_RAM_MASK 0x8u
-#define I2C_S_RAM_SHIFT 3
-#define I2C_S_ARBL_MASK 0x10u
-#define I2C_S_ARBL_SHIFT 4
-#define I2C_S_BUSY_MASK 0x20u
-#define I2C_S_BUSY_SHIFT 5
-#define I2C_S_IAAS_MASK 0x40u
-#define I2C_S_IAAS_SHIFT 6
-#define I2C_S_TCF_MASK 0x80u
-#define I2C_S_TCF_SHIFT 7
-/* D Bit Fields */
-#define I2C_D_DATA_MASK 0xFFu
-#define I2C_D_DATA_SHIFT 0
-#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
-/* C2 Bit Fields */
-#define I2C_C2_AD_MASK 0x7u
-#define I2C_C2_AD_SHIFT 0
-#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
-#define I2C_C2_RMEN_MASK 0x8u
-#define I2C_C2_RMEN_SHIFT 3
-#define I2C_C2_SBRC_MASK 0x10u
-#define I2C_C2_SBRC_SHIFT 4
-#define I2C_C2_HDRS_MASK 0x20u
-#define I2C_C2_HDRS_SHIFT 5
-#define I2C_C2_ADEXT_MASK 0x40u
-#define I2C_C2_ADEXT_SHIFT 6
-#define I2C_C2_GCAEN_MASK 0x80u
-#define I2C_C2_GCAEN_SHIFT 7
-/* FLT Bit Fields */
-#define I2C_FLT_FLT_MASK 0xFu
-#define I2C_FLT_FLT_SHIFT 0
-#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
-#define I2C_FLT_STARTF_MASK 0x10u
-#define I2C_FLT_STARTF_SHIFT 4
-#define I2C_FLT_SSIE_MASK 0x20u
-#define I2C_FLT_SSIE_SHIFT 5
-#define I2C_FLT_STOPF_MASK 0x40u
-#define I2C_FLT_STOPF_SHIFT 6
-#define I2C_FLT_SHEN_MASK 0x80u
-#define I2C_FLT_SHEN_SHIFT 7
-/* RA Bit Fields */
-#define I2C_RA_RAD_MASK 0xFEu
-#define I2C_RA_RAD_SHIFT 1
-#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
-/* SMB Bit Fields */
-#define I2C_SMB_SHTF2IE_MASK 0x1u
-#define I2C_SMB_SHTF2IE_SHIFT 0
-#define I2C_SMB_SHTF2_MASK 0x2u
-#define I2C_SMB_SHTF2_SHIFT 1
-#define I2C_SMB_SHTF1_MASK 0x4u
-#define I2C_SMB_SHTF1_SHIFT 2
-#define I2C_SMB_SLTF_MASK 0x8u
-#define I2C_SMB_SLTF_SHIFT 3
-#define I2C_SMB_TCKSEL_MASK 0x10u
-#define I2C_SMB_TCKSEL_SHIFT 4
-#define I2C_SMB_SIICAEN_MASK 0x20u
-#define I2C_SMB_SIICAEN_SHIFT 5
-#define I2C_SMB_ALERTEN_MASK 0x40u
-#define I2C_SMB_ALERTEN_SHIFT 6
-#define I2C_SMB_FACK_MASK 0x80u
-#define I2C_SMB_FACK_SHIFT 7
-/* A2 Bit Fields */
-#define I2C_A2_SAD_MASK 0xFEu
-#define I2C_A2_SAD_SHIFT 1
-#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
-/* SLTH Bit Fields */
-#define I2C_SLTH_SSLT_MASK 0xFFu
-#define I2C_SLTH_SSLT_SHIFT 0
-#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
-/* SLTL Bit Fields */
-#define I2C_SLTL_SSLT_MASK 0xFFu
-#define I2C_SLTL_SSLT_SHIFT 0
-#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
-
-/*!
- * @}
- */ /* end of group I2C_Register_Masks */
-
-
-/* I2C - Peripheral instance base addresses */
-/** Peripheral I2C0 base address */
-#define I2C0_BASE (0x40066000u)
-/** Peripheral I2C0 base pointer */
-#define I2C0 ((I2C_Type *)I2C0_BASE)
-#define I2C0_BASE_PTR (I2C0)
-/** Peripheral I2C1 base address */
-#define I2C1_BASE (0x40067000u)
-/** Peripheral I2C1 base pointer */
-#define I2C1 ((I2C_Type *)I2C1_BASE)
-#define I2C1_BASE_PTR (I2C1)
-/** Peripheral I2C2 base address */
-#define I2C2_BASE (0x400E6000u)
-/** Peripheral I2C2 base pointer */
-#define I2C2 ((I2C_Type *)I2C2_BASE)
-#define I2C2_BASE_PTR (I2C2)
-/** Array initializer of I2C peripheral base pointers */
-#define I2C_BASES { I2C0, I2C1, I2C2 }
-
-/* ----------------------------------------------------------------------------
- -- I2C - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
- * @{
- */
-
-
-/* I2C - Register instance definitions */
-/* I2C0 */
-#define I2C0_A1 I2C_A1_REG(I2C0)
-#define I2C0_F I2C_F_REG(I2C0)
-#define I2C0_C1 I2C_C1_REG(I2C0)
-#define I2C0_S I2C_S_REG(I2C0)
-#define I2C0_D I2C_D_REG(I2C0)
-#define I2C0_C2 I2C_C2_REG(I2C0)
-#define I2C0_FLT I2C_FLT_REG(I2C0)
-#define I2C0_RA I2C_RA_REG(I2C0)
-#define I2C0_SMB I2C_SMB_REG(I2C0)
-#define I2C0_A2 I2C_A2_REG(I2C0)
-#define I2C0_SLTH I2C_SLTH_REG(I2C0)
-#define I2C0_SLTL I2C_SLTL_REG(I2C0)
-/* I2C1 */
-#define I2C1_A1 I2C_A1_REG(I2C1)
-#define I2C1_F I2C_F_REG(I2C1)
-#define I2C1_C1 I2C_C1_REG(I2C1)
-#define I2C1_S I2C_S_REG(I2C1)
-#define I2C1_D I2C_D_REG(I2C1)
-#define I2C1_C2 I2C_C2_REG(I2C1)
-#define I2C1_FLT I2C_FLT_REG(I2C1)
-#define I2C1_RA I2C_RA_REG(I2C1)
-#define I2C1_SMB I2C_SMB_REG(I2C1)
-#define I2C1_A2 I2C_A2_REG(I2C1)
-#define I2C1_SLTH I2C_SLTH_REG(I2C1)
-#define I2C1_SLTL I2C_SLTL_REG(I2C1)
-/* I2C2 */
-#define I2C2_A1 I2C_A1_REG(I2C2)
-#define I2C2_F I2C_F_REG(I2C2)
-#define I2C2_C1 I2C_C1_REG(I2C2)
-#define I2C2_S I2C_S_REG(I2C2)
-#define I2C2_D I2C_D_REG(I2C2)
-#define I2C2_C2 I2C_C2_REG(I2C2)
-#define I2C2_FLT I2C_FLT_REG(I2C2)
-#define I2C2_RA I2C_RA_REG(I2C2)
-#define I2C2_SMB I2C_SMB_REG(I2C2)
-#define I2C2_A2 I2C_A2_REG(I2C2)
-#define I2C2_SLTH I2C_SLTH_REG(I2C2)
-#define I2C2_SLTL I2C_SLTL_REG(I2C2)
-
-/*!
- * @}
- */ /* end of group I2C_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group I2C_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- I2S Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
- * @{
- */
-
-/** I2S - Register Layout Typedef */
-typedef struct {
- __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
- __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
- __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
- __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
- __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
- __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
- uint8_t RESERVED_0[8];
- __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
- uint8_t RESERVED_1[24];
- __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
- uint8_t RESERVED_2[24];
- __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
- uint8_t RESERVED_3[28];
- __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
- __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
- __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
- __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
- __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
- __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
- uint8_t RESERVED_4[8];
- __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
- uint8_t RESERVED_5[24];
- __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
- uint8_t RESERVED_6[24];
- __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
- uint8_t RESERVED_7[28];
- __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
- __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
-} I2S_Type, *I2S_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- I2S - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
- * @{
- */
-
-
-/* I2S - Register accessors */
-#define I2S_TCSR_REG(base) ((base)->TCSR)
-#define I2S_TCR1_REG(base) ((base)->TCR1)
-#define I2S_TCR2_REG(base) ((base)->TCR2)
-#define I2S_TCR3_REG(base) ((base)->TCR3)
-#define I2S_TCR4_REG(base) ((base)->TCR4)
-#define I2S_TCR5_REG(base) ((base)->TCR5)
-#define I2S_TDR_REG(base,index) ((base)->TDR[index])
-#define I2S_TFR_REG(base,index) ((base)->TFR[index])
-#define I2S_TMR_REG(base) ((base)->TMR)
-#define I2S_RCSR_REG(base) ((base)->RCSR)
-#define I2S_RCR1_REG(base) ((base)->RCR1)
-#define I2S_RCR2_REG(base) ((base)->RCR2)
-#define I2S_RCR3_REG(base) ((base)->RCR3)
-#define I2S_RCR4_REG(base) ((base)->RCR4)
-#define I2S_RCR5_REG(base) ((base)->RCR5)
-#define I2S_RDR_REG(base,index) ((base)->RDR[index])
-#define I2S_RFR_REG(base,index) ((base)->RFR[index])
-#define I2S_RMR_REG(base) ((base)->RMR)
-#define I2S_MCR_REG(base) ((base)->MCR)
-#define I2S_MDR_REG(base) ((base)->MDR)
-
-/*!
- * @}
- */ /* end of group I2S_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- I2S Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2S_Register_Masks I2S Register Masks
- * @{
- */
-
-/* TCSR Bit Fields */
-#define I2S_TCSR_FRDE_MASK 0x1u
-#define I2S_TCSR_FRDE_SHIFT 0
-#define I2S_TCSR_FWDE_MASK 0x2u
-#define I2S_TCSR_FWDE_SHIFT 1
-#define I2S_TCSR_FRIE_MASK 0x100u
-#define I2S_TCSR_FRIE_SHIFT 8
-#define I2S_TCSR_FWIE_MASK 0x200u
-#define I2S_TCSR_FWIE_SHIFT 9
-#define I2S_TCSR_FEIE_MASK 0x400u
-#define I2S_TCSR_FEIE_SHIFT 10
-#define I2S_TCSR_SEIE_MASK 0x800u
-#define I2S_TCSR_SEIE_SHIFT 11
-#define I2S_TCSR_WSIE_MASK 0x1000u
-#define I2S_TCSR_WSIE_SHIFT 12
-#define I2S_TCSR_FRF_MASK 0x10000u
-#define I2S_TCSR_FRF_SHIFT 16
-#define I2S_TCSR_FWF_MASK 0x20000u
-#define I2S_TCSR_FWF_SHIFT 17
-#define I2S_TCSR_FEF_MASK 0x40000u
-#define I2S_TCSR_FEF_SHIFT 18
-#define I2S_TCSR_SEF_MASK 0x80000u
-#define I2S_TCSR_SEF_SHIFT 19
-#define I2S_TCSR_WSF_MASK 0x100000u
-#define I2S_TCSR_WSF_SHIFT 20
-#define I2S_TCSR_SR_MASK 0x1000000u
-#define I2S_TCSR_SR_SHIFT 24
-#define I2S_TCSR_FR_MASK 0x2000000u
-#define I2S_TCSR_FR_SHIFT 25
-#define I2S_TCSR_BCE_MASK 0x10000000u
-#define I2S_TCSR_BCE_SHIFT 28
-#define I2S_TCSR_DBGE_MASK 0x20000000u
-#define I2S_TCSR_DBGE_SHIFT 29
-#define I2S_TCSR_STOPE_MASK 0x40000000u
-#define I2S_TCSR_STOPE_SHIFT 30
-#define I2S_TCSR_TE_MASK 0x80000000u
-#define I2S_TCSR_TE_SHIFT 31
-/* TCR1 Bit Fields */
-#define I2S_TCR1_TFW_MASK 0x7u
-#define I2S_TCR1_TFW_SHIFT 0
-#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
-/* TCR2 Bit Fields */
-#define I2S_TCR2_DIV_MASK 0xFFu
-#define I2S_TCR2_DIV_SHIFT 0
-#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
-#define I2S_TCR2_BCD_MASK 0x1000000u
-#define I2S_TCR2_BCD_SHIFT 24
-#define I2S_TCR2_BCP_MASK 0x2000000u
-#define I2S_TCR2_BCP_SHIFT 25
-#define I2S_TCR2_MSEL_MASK 0xC000000u
-#define I2S_TCR2_MSEL_SHIFT 26
-#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
-#define I2S_TCR2_BCI_MASK 0x10000000u
-#define I2S_TCR2_BCI_SHIFT 28
-#define I2S_TCR2_BCS_MASK 0x20000000u
-#define I2S_TCR2_BCS_SHIFT 29
-#define I2S_TCR2_SYNC_MASK 0xC0000000u
-#define I2S_TCR2_SYNC_SHIFT 30
-#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
-/* TCR3 Bit Fields */
-#define I2S_TCR3_WDFL_MASK 0x1Fu
-#define I2S_TCR3_WDFL_SHIFT 0
-#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
-#define I2S_TCR3_TCE_MASK 0x30000u
-#define I2S_TCR3_TCE_SHIFT 16
-#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
-/* TCR4 Bit Fields */
-#define I2S_TCR4_FSD_MASK 0x1u
-#define I2S_TCR4_FSD_SHIFT 0
-#define I2S_TCR4_FSP_MASK 0x2u
-#define I2S_TCR4_FSP_SHIFT 1
-#define I2S_TCR4_FSE_MASK 0x8u
-#define I2S_TCR4_FSE_SHIFT 3
-#define I2S_TCR4_MF_MASK 0x10u
-#define I2S_TCR4_MF_SHIFT 4
-#define I2S_TCR4_SYWD_MASK 0x1F00u
-#define I2S_TCR4_SYWD_SHIFT 8
-#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
-#define I2S_TCR4_FRSZ_MASK 0x1F0000u
-#define I2S_TCR4_FRSZ_SHIFT 16
-#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
-/* TCR5 Bit Fields */
-#define I2S_TCR5_FBT_MASK 0x1F00u
-#define I2S_TCR5_FBT_SHIFT 8
-#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
-#define I2S_TCR5_W0W_MASK 0x1F0000u
-#define I2S_TCR5_W0W_SHIFT 16
-#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
-#define I2S_TCR5_WNW_MASK 0x1F000000u
-#define I2S_TCR5_WNW_SHIFT 24
-#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
-/* TDR Bit Fields */
-#define I2S_TDR_TDR_MASK 0xFFFFFFFFu
-#define I2S_TDR_TDR_SHIFT 0
-#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
-/* TFR Bit Fields */
-#define I2S_TFR_RFP_MASK 0xFu
-#define I2S_TFR_RFP_SHIFT 0
-#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
-#define I2S_TFR_WFP_MASK 0xF0000u
-#define I2S_TFR_WFP_SHIFT 16
-#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
-/* TMR Bit Fields */
-#define I2S_TMR_TWM_MASK 0xFFFFFFFFu
-#define I2S_TMR_TWM_SHIFT 0
-#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
-/* RCSR Bit Fields */
-#define I2S_RCSR_FRDE_MASK 0x1u
-#define I2S_RCSR_FRDE_SHIFT 0
-#define I2S_RCSR_FWDE_MASK 0x2u
-#define I2S_RCSR_FWDE_SHIFT 1
-#define I2S_RCSR_FRIE_MASK 0x100u
-#define I2S_RCSR_FRIE_SHIFT 8
-#define I2S_RCSR_FWIE_MASK 0x200u
-#define I2S_RCSR_FWIE_SHIFT 9
-#define I2S_RCSR_FEIE_MASK 0x400u
-#define I2S_RCSR_FEIE_SHIFT 10
-#define I2S_RCSR_SEIE_MASK 0x800u
-#define I2S_RCSR_SEIE_SHIFT 11
-#define I2S_RCSR_WSIE_MASK 0x1000u
-#define I2S_RCSR_WSIE_SHIFT 12
-#define I2S_RCSR_FRF_MASK 0x10000u
-#define I2S_RCSR_FRF_SHIFT 16
-#define I2S_RCSR_FWF_MASK 0x20000u
-#define I2S_RCSR_FWF_SHIFT 17
-#define I2S_RCSR_FEF_MASK 0x40000u
-#define I2S_RCSR_FEF_SHIFT 18
-#define I2S_RCSR_SEF_MASK 0x80000u
-#define I2S_RCSR_SEF_SHIFT 19
-#define I2S_RCSR_WSF_MASK 0x100000u
-#define I2S_RCSR_WSF_SHIFT 20
-#define I2S_RCSR_SR_MASK 0x1000000u
-#define I2S_RCSR_SR_SHIFT 24
-#define I2S_RCSR_FR_MASK 0x2000000u
-#define I2S_RCSR_FR_SHIFT 25
-#define I2S_RCSR_BCE_MASK 0x10000000u
-#define I2S_RCSR_BCE_SHIFT 28
-#define I2S_RCSR_DBGE_MASK 0x20000000u
-#define I2S_RCSR_DBGE_SHIFT 29
-#define I2S_RCSR_STOPE_MASK 0x40000000u
-#define I2S_RCSR_STOPE_SHIFT 30
-#define I2S_RCSR_RE_MASK 0x80000000u
-#define I2S_RCSR_RE_SHIFT 31
-/* RCR1 Bit Fields */
-#define I2S_RCR1_RFW_MASK 0x7u
-#define I2S_RCR1_RFW_SHIFT 0
-#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
-/* RCR2 Bit Fields */
-#define I2S_RCR2_DIV_MASK 0xFFu
-#define I2S_RCR2_DIV_SHIFT 0
-#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
-#define I2S_RCR2_BCD_MASK 0x1000000u
-#define I2S_RCR2_BCD_SHIFT 24
-#define I2S_RCR2_BCP_MASK 0x2000000u
-#define I2S_RCR2_BCP_SHIFT 25
-#define I2S_RCR2_MSEL_MASK 0xC000000u
-#define I2S_RCR2_MSEL_SHIFT 26
-#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
-#define I2S_RCR2_BCI_MASK 0x10000000u
-#define I2S_RCR2_BCI_SHIFT 28
-#define I2S_RCR2_BCS_MASK 0x20000000u
-#define I2S_RCR2_BCS_SHIFT 29
-#define I2S_RCR2_SYNC_MASK 0xC0000000u
-#define I2S_RCR2_SYNC_SHIFT 30
-#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
-/* RCR3 Bit Fields */
-#define I2S_RCR3_WDFL_MASK 0x1Fu
-#define I2S_RCR3_WDFL_SHIFT 0
-#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
-#define I2S_RCR3_RCE_MASK 0x30000u
-#define I2S_RCR3_RCE_SHIFT 16
-#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
-/* RCR4 Bit Fields */
-#define I2S_RCR4_FSD_MASK 0x1u
-#define I2S_RCR4_FSD_SHIFT 0
-#define I2S_RCR4_FSP_MASK 0x2u
-#define I2S_RCR4_FSP_SHIFT 1
-#define I2S_RCR4_FSE_MASK 0x8u
-#define I2S_RCR4_FSE_SHIFT 3
-#define I2S_RCR4_MF_MASK 0x10u
-#define I2S_RCR4_MF_SHIFT 4
-#define I2S_RCR4_SYWD_MASK 0x1F00u
-#define I2S_RCR4_SYWD_SHIFT 8
-#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
-#define I2S_RCR4_FRSZ_MASK 0x1F0000u
-#define I2S_RCR4_FRSZ_SHIFT 16
-#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
-/* RCR5 Bit Fields */
-#define I2S_RCR5_FBT_MASK 0x1F00u
-#define I2S_RCR5_FBT_SHIFT 8
-#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
-#define I2S_RCR5_W0W_MASK 0x1F0000u
-#define I2S_RCR5_W0W_SHIFT 16
-#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
-#define I2S_RCR5_WNW_MASK 0x1F000000u
-#define I2S_RCR5_WNW_SHIFT 24
-#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
-/* RDR Bit Fields */
-#define I2S_RDR_RDR_MASK 0xFFFFFFFFu
-#define I2S_RDR_RDR_SHIFT 0
-#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
-/* RFR Bit Fields */
-#define I2S_RFR_RFP_MASK 0xFu
-#define I2S_RFR_RFP_SHIFT 0
-#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
-#define I2S_RFR_WFP_MASK 0xF0000u
-#define I2S_RFR_WFP_SHIFT 16
-#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
-/* RMR Bit Fields */
-#define I2S_RMR_RWM_MASK 0xFFFFFFFFu
-#define I2S_RMR_RWM_SHIFT 0
-#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
-/* MCR Bit Fields */
-#define I2S_MCR_MICS_MASK 0x3000000u
-#define I2S_MCR_MICS_SHIFT 24
-#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
-#define I2S_MCR_MOE_MASK 0x40000000u
-#define I2S_MCR_MOE_SHIFT 30
-#define I2S_MCR_DUF_MASK 0x80000000u
-#define I2S_MCR_DUF_SHIFT 31
-/* MDR Bit Fields */
-#define I2S_MDR_DIVIDE_MASK 0xFFFu
-#define I2S_MDR_DIVIDE_SHIFT 0
-#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
-#define I2S_MDR_FRACT_MASK 0xFF000u
-#define I2S_MDR_FRACT_SHIFT 12
-#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
-
-/*!
- * @}
- */ /* end of group I2S_Register_Masks */
-
-
-/* I2S - Peripheral instance base addresses */
-/** Peripheral I2S0 base address */
-#define I2S0_BASE (0x4002F000u)
-/** Peripheral I2S0 base pointer */
-#define I2S0 ((I2S_Type *)I2S0_BASE)
-#define I2S0_BASE_PTR (I2S0)
-/** Array initializer of I2S peripheral base pointers */
-#define I2S_BASES { I2S0 }
-
-/* ----------------------------------------------------------------------------
- -- I2S - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
- * @{
- */
-
-
-/* I2S - Register instance definitions */
-/* I2S0 */
-#define I2S0_TCSR I2S_TCSR_REG(I2S0)
-#define I2S0_TCR1 I2S_TCR1_REG(I2S0)
-#define I2S0_TCR2 I2S_TCR2_REG(I2S0)
-#define I2S0_TCR3 I2S_TCR3_REG(I2S0)
-#define I2S0_TCR4 I2S_TCR4_REG(I2S0)
-#define I2S0_TCR5 I2S_TCR5_REG(I2S0)
-#define I2S0_TDR0 I2S_TDR_REG(I2S0,0)
-#define I2S0_TDR1 I2S_TDR_REG(I2S0,1)
-#define I2S0_TFR0 I2S_TFR_REG(I2S0,0)
-#define I2S0_TFR1 I2S_TFR_REG(I2S0,1)
-#define I2S0_TMR I2S_TMR_REG(I2S0)
-#define I2S0_RCSR I2S_RCSR_REG(I2S0)
-#define I2S0_RCR1 I2S_RCR1_REG(I2S0)
-#define I2S0_RCR2 I2S_RCR2_REG(I2S0)
-#define I2S0_RCR3 I2S_RCR3_REG(I2S0)
-#define I2S0_RCR4 I2S_RCR4_REG(I2S0)
-#define I2S0_RCR5 I2S_RCR5_REG(I2S0)
-#define I2S0_RDR0 I2S_RDR_REG(I2S0,0)
-#define I2S0_RDR1 I2S_RDR_REG(I2S0,1)
-#define I2S0_RFR0 I2S_RFR_REG(I2S0,0)
-#define I2S0_RFR1 I2S_RFR_REG(I2S0,1)
-#define I2S0_RMR I2S_RMR_REG(I2S0)
-#define I2S0_MCR I2S_MCR_REG(I2S0)
-#define I2S0_MDR I2S_MDR_REG(I2S0)
-
-/* I2S - Register array accessors */
-#define I2S0_TDR(index) I2S_TDR_REG(I2S0,index)
-#define I2S0_TFR(index) I2S_TFR_REG(I2S0,index)
-#define I2S0_RDR(index) I2S_RDR_REG(I2S0,index)
-#define I2S0_RFR(index) I2S_RFR_REG(I2S0,index)
-
-/*!
- * @}
- */ /* end of group I2S_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group I2S_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- LLWU Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
- * @{
- */
-
-/** LLWU - Register Layout Typedef */
-typedef struct {
- __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
- __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
- __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
- __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
- __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
- __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
- __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
- __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
- __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
- __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
- __IO uint8_t RST; /**< LLWU Reset Enable register, offset: 0xA */
-} LLWU_Type, *LLWU_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- LLWU - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
- * @{
- */
-
-
-/* LLWU - Register accessors */
-#define LLWU_PE1_REG(base) ((base)->PE1)
-#define LLWU_PE2_REG(base) ((base)->PE2)
-#define LLWU_PE3_REG(base) ((base)->PE3)
-#define LLWU_PE4_REG(base) ((base)->PE4)
-#define LLWU_ME_REG(base) ((base)->ME)
-#define LLWU_F1_REG(base) ((base)->F1)
-#define LLWU_F2_REG(base) ((base)->F2)
-#define LLWU_F3_REG(base) ((base)->F3)
-#define LLWU_FILT1_REG(base) ((base)->FILT1)
-#define LLWU_FILT2_REG(base) ((base)->FILT2)
-#define LLWU_RST_REG(base) ((base)->RST)
-
-/*!
- * @}
- */ /* end of group LLWU_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- LLWU Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LLWU_Register_Masks LLWU Register Masks
- * @{
- */
-
-/* PE1 Bit Fields */
-#define LLWU_PE1_WUPE0_MASK 0x3u
-#define LLWU_PE1_WUPE0_SHIFT 0
-#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
-#define LLWU_PE1_WUPE1_MASK 0xCu
-#define LLWU_PE1_WUPE1_SHIFT 2
-#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
-#define LLWU_PE1_WUPE2_MASK 0x30u
-#define LLWU_PE1_WUPE2_SHIFT 4
-#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
-#define LLWU_PE1_WUPE3_MASK 0xC0u
-#define LLWU_PE1_WUPE3_SHIFT 6
-#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
-/* PE2 Bit Fields */
-#define LLWU_PE2_WUPE4_MASK 0x3u
-#define LLWU_PE2_WUPE4_SHIFT 0
-#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
-#define LLWU_PE2_WUPE5_MASK 0xCu
-#define LLWU_PE2_WUPE5_SHIFT 2
-#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
-#define LLWU_PE2_WUPE6_MASK 0x30u
-#define LLWU_PE2_WUPE6_SHIFT 4
-#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
-#define LLWU_PE2_WUPE7_MASK 0xC0u
-#define LLWU_PE2_WUPE7_SHIFT 6
-#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
-/* PE3 Bit Fields */
-#define LLWU_PE3_WUPE8_MASK 0x3u
-#define LLWU_PE3_WUPE8_SHIFT 0
-#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
-#define LLWU_PE3_WUPE9_MASK 0xCu
-#define LLWU_PE3_WUPE9_SHIFT 2
-#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
-#define LLWU_PE3_WUPE10_MASK 0x30u
-#define LLWU_PE3_WUPE10_SHIFT 4
-#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
-#define LLWU_PE3_WUPE11_MASK 0xC0u
-#define LLWU_PE3_WUPE11_SHIFT 6
-#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
-/* PE4 Bit Fields */
-#define LLWU_PE4_WUPE12_MASK 0x3u
-#define LLWU_PE4_WUPE12_SHIFT 0
-#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
-#define LLWU_PE4_WUPE13_MASK 0xCu
-#define LLWU_PE4_WUPE13_SHIFT 2
-#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
-#define LLWU_PE4_WUPE14_MASK 0x30u
-#define LLWU_PE4_WUPE14_SHIFT 4
-#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
-#define LLWU_PE4_WUPE15_MASK 0xC0u
-#define LLWU_PE4_WUPE15_SHIFT 6
-#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
-/* ME Bit Fields */
-#define LLWU_ME_WUME0_MASK 0x1u
-#define LLWU_ME_WUME0_SHIFT 0
-#define LLWU_ME_WUME1_MASK 0x2u
-#define LLWU_ME_WUME1_SHIFT 1
-#define LLWU_ME_WUME2_MASK 0x4u
-#define LLWU_ME_WUME2_SHIFT 2
-#define LLWU_ME_WUME3_MASK 0x8u
-#define LLWU_ME_WUME3_SHIFT 3
-#define LLWU_ME_WUME4_MASK 0x10u
-#define LLWU_ME_WUME4_SHIFT 4
-#define LLWU_ME_WUME5_MASK 0x20u
-#define LLWU_ME_WUME5_SHIFT 5
-#define LLWU_ME_WUME6_MASK 0x40u
-#define LLWU_ME_WUME6_SHIFT 6
-#define LLWU_ME_WUME7_MASK 0x80u
-#define LLWU_ME_WUME7_SHIFT 7
-/* F1 Bit Fields */
-#define LLWU_F1_WUF0_MASK 0x1u
-#define LLWU_F1_WUF0_SHIFT 0
-#define LLWU_F1_WUF1_MASK 0x2u
-#define LLWU_F1_WUF1_SHIFT 1
-#define LLWU_F1_WUF2_MASK 0x4u
-#define LLWU_F1_WUF2_SHIFT 2
-#define LLWU_F1_WUF3_MASK 0x8u
-#define LLWU_F1_WUF3_SHIFT 3
-#define LLWU_F1_WUF4_MASK 0x10u
-#define LLWU_F1_WUF4_SHIFT 4
-#define LLWU_F1_WUF5_MASK 0x20u
-#define LLWU_F1_WUF5_SHIFT 5
-#define LLWU_F1_WUF6_MASK 0x40u
-#define LLWU_F1_WUF6_SHIFT 6
-#define LLWU_F1_WUF7_MASK 0x80u
-#define LLWU_F1_WUF7_SHIFT 7
-/* F2 Bit Fields */
-#define LLWU_F2_WUF8_MASK 0x1u
-#define LLWU_F2_WUF8_SHIFT 0
-#define LLWU_F2_WUF9_MASK 0x2u
-#define LLWU_F2_WUF9_SHIFT 1
-#define LLWU_F2_WUF10_MASK 0x4u
-#define LLWU_F2_WUF10_SHIFT 2
-#define LLWU_F2_WUF11_MASK 0x8u
-#define LLWU_F2_WUF11_SHIFT 3
-#define LLWU_F2_WUF12_MASK 0x10u
-#define LLWU_F2_WUF12_SHIFT 4
-#define LLWU_F2_WUF13_MASK 0x20u
-#define LLWU_F2_WUF13_SHIFT 5
-#define LLWU_F2_WUF14_MASK 0x40u
-#define LLWU_F2_WUF14_SHIFT 6
-#define LLWU_F2_WUF15_MASK 0x80u
-#define LLWU_F2_WUF15_SHIFT 7
-/* F3 Bit Fields */
-#define LLWU_F3_MWUF0_MASK 0x1u
-#define LLWU_F3_MWUF0_SHIFT 0
-#define LLWU_F3_MWUF1_MASK 0x2u
-#define LLWU_F3_MWUF1_SHIFT 1
-#define LLWU_F3_MWUF2_MASK 0x4u
-#define LLWU_F3_MWUF2_SHIFT 2
-#define LLWU_F3_MWUF3_MASK 0x8u
-#define LLWU_F3_MWUF3_SHIFT 3
-#define LLWU_F3_MWUF4_MASK 0x10u
-#define LLWU_F3_MWUF4_SHIFT 4
-#define LLWU_F3_MWUF5_MASK 0x20u
-#define LLWU_F3_MWUF5_SHIFT 5
-#define LLWU_F3_MWUF6_MASK 0x40u
-#define LLWU_F3_MWUF6_SHIFT 6
-#define LLWU_F3_MWUF7_MASK 0x80u
-#define LLWU_F3_MWUF7_SHIFT 7
-/* FILT1 Bit Fields */
-#define LLWU_FILT1_FILTSEL_MASK 0xFu
-#define LLWU_FILT1_FILTSEL_SHIFT 0
-#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
-#define LLWU_FILT1_FILTE_MASK 0x60u
-#define LLWU_FILT1_FILTE_SHIFT 5
-#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
-#define LLWU_FILT1_FILTF_MASK 0x80u
-#define LLWU_FILT1_FILTF_SHIFT 7
-/* FILT2 Bit Fields */
-#define LLWU_FILT2_FILTSEL_MASK 0xFu
-#define LLWU_FILT2_FILTSEL_SHIFT 0
-#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
-#define LLWU_FILT2_FILTE_MASK 0x60u
-#define LLWU_FILT2_FILTE_SHIFT 5
-#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
-#define LLWU_FILT2_FILTF_MASK 0x80u
-#define LLWU_FILT2_FILTF_SHIFT 7
-/* RST Bit Fields */
-#define LLWU_RST_RSTFILT_MASK 0x1u
-#define LLWU_RST_RSTFILT_SHIFT 0
-#define LLWU_RST_LLRSTE_MASK 0x2u
-#define LLWU_RST_LLRSTE_SHIFT 1
-
-/*!
- * @}
- */ /* end of group LLWU_Register_Masks */
-
-
-/* LLWU - Peripheral instance base addresses */
-/** Peripheral LLWU base address */
-#define LLWU_BASE (0x4007C000u)
-/** Peripheral LLWU base pointer */
-#define LLWU ((LLWU_Type *)LLWU_BASE)
-#define LLWU_BASE_PTR (LLWU)
-/** Array initializer of LLWU peripheral base pointers */
-#define LLWU_BASES { LLWU }
-
-/* ----------------------------------------------------------------------------
- -- LLWU - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
- * @{
- */
-
-
-/* LLWU - Register instance definitions */
-/* LLWU */
-#define LLWU_PE1 LLWU_PE1_REG(LLWU)
-#define LLWU_PE2 LLWU_PE2_REG(LLWU)
-#define LLWU_PE3 LLWU_PE3_REG(LLWU)
-#define LLWU_PE4 LLWU_PE4_REG(LLWU)
-#define LLWU_ME LLWU_ME_REG(LLWU)
-#define LLWU_F1 LLWU_F1_REG(LLWU)
-#define LLWU_F2 LLWU_F2_REG(LLWU)
-#define LLWU_F3 LLWU_F3_REG(LLWU)
-#define LLWU_FILT1 LLWU_FILT1_REG(LLWU)
-#define LLWU_FILT2 LLWU_FILT2_REG(LLWU)
-#define LLWU_RST LLWU_RST_REG(LLWU)
-
-/*!
- * @}
- */ /* end of group LLWU_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group LLWU_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- LPTMR Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
- * @{
- */
-
-/** LPTMR - Register Layout Typedef */
-typedef struct {
- __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
- __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
- __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
- __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
-} LPTMR_Type, *LPTMR_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- LPTMR - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
- * @{
- */
-
-
-/* LPTMR - Register accessors */
-#define LPTMR_CSR_REG(base) ((base)->CSR)
-#define LPTMR_PSR_REG(base) ((base)->PSR)
-#define LPTMR_CMR_REG(base) ((base)->CMR)
-#define LPTMR_CNR_REG(base) ((base)->CNR)
-
-/*!
- * @}
- */ /* end of group LPTMR_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- LPTMR Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
- * @{
- */
-
-/* CSR Bit Fields */
-#define LPTMR_CSR_TEN_MASK 0x1u
-#define LPTMR_CSR_TEN_SHIFT 0
-#define LPTMR_CSR_TMS_MASK 0x2u
-#define LPTMR_CSR_TMS_SHIFT 1
-#define LPTMR_CSR_TFC_MASK 0x4u
-#define LPTMR_CSR_TFC_SHIFT 2
-#define LPTMR_CSR_TPP_MASK 0x8u
-#define LPTMR_CSR_TPP_SHIFT 3
-#define LPTMR_CSR_TPS_MASK 0x30u
-#define LPTMR_CSR_TPS_SHIFT 4
-#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
-#define LPTMR_CSR_TIE_MASK 0x40u
-#define LPTMR_CSR_TIE_SHIFT 6
-#define LPTMR_CSR_TCF_MASK 0x80u
-#define LPTMR_CSR_TCF_SHIFT 7
-/* PSR Bit Fields */
-#define LPTMR_PSR_PCS_MASK 0x3u
-#define LPTMR_PSR_PCS_SHIFT 0
-#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
-#define LPTMR_PSR_PBYP_MASK 0x4u
-#define LPTMR_PSR_PBYP_SHIFT 2
-#define LPTMR_PSR_PRESCALE_MASK 0x78u
-#define LPTMR_PSR_PRESCALE_SHIFT 3
-#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
-/* CMR Bit Fields */
-#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
-#define LPTMR_CMR_COMPARE_SHIFT 0
-#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
-/* CNR Bit Fields */
-#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
-#define LPTMR_CNR_COUNTER_SHIFT 0
-#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
-
-/*!
- * @}
- */ /* end of group LPTMR_Register_Masks */
-
-
-/* LPTMR - Peripheral instance base addresses */
-/** Peripheral LPTMR0 base address */
-#define LPTMR0_BASE (0x40040000u)
-/** Peripheral LPTMR0 base pointer */
-#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
-#define LPTMR0_BASE_PTR (LPTMR0)
-/** Array initializer of LPTMR peripheral base pointers */
-#define LPTMR_BASES { LPTMR0 }
-
-/* ----------------------------------------------------------------------------
- -- LPTMR - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
- * @{
- */
-
-
-/* LPTMR - Register instance definitions */
-/* LPTMR0 */
-#define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0)
-#define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0)
-#define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0)
-#define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0)
-
-/*!
- * @}
- */ /* end of group LPTMR_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group LPTMR_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- MCG Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
- * @{
- */
-
-/** MCG - Register Layout Typedef */
-typedef struct {
- __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
- __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
- __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
- __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
- __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
- __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
- __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
- uint8_t RESERVED_0[1];
- __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
- uint8_t RESERVED_1[1];
- __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
- __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
- __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
- __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
-} MCG_Type, *MCG_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- MCG - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
- * @{
- */
-
-
-/* MCG - Register accessors */
-#define MCG_C1_REG(base) ((base)->C1)
-#define MCG_C2_REG(base) ((base)->C2)
-#define MCG_C3_REG(base) ((base)->C3)
-#define MCG_C4_REG(base) ((base)->C4)
-#define MCG_C5_REG(base) ((base)->C5)
-#define MCG_C6_REG(base) ((base)->C6)
-#define MCG_S_REG(base) ((base)->S)
-#define MCG_SC_REG(base) ((base)->SC)
-#define MCG_ATCVH_REG(base) ((base)->ATCVH)
-#define MCG_ATCVL_REG(base) ((base)->ATCVL)
-#define MCG_C7_REG(base) ((base)->C7)
-#define MCG_C8_REG(base) ((base)->C8)
-
-/*!
- * @}
- */ /* end of group MCG_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- MCG Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCG_Register_Masks MCG Register Masks
- * @{
- */
-
-/* C1 Bit Fields */
-#define MCG_C1_IREFSTEN_MASK 0x1u
-#define MCG_C1_IREFSTEN_SHIFT 0
-#define MCG_C1_IRCLKEN_MASK 0x2u
-#define MCG_C1_IRCLKEN_SHIFT 1
-#define MCG_C1_IREFS_MASK 0x4u
-#define MCG_C1_IREFS_SHIFT 2
-#define MCG_C1_FRDIV_MASK 0x38u
-#define MCG_C1_FRDIV_SHIFT 3
-#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
-#define MCG_C1_CLKS_MASK 0xC0u
-#define MCG_C1_CLKS_SHIFT 6
-#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
-/* C2 Bit Fields */
-#define MCG_C2_IRCS_MASK 0x1u
-#define MCG_C2_IRCS_SHIFT 0
-#define MCG_C2_LP_MASK 0x2u
-#define MCG_C2_LP_SHIFT 1
-#define MCG_C2_EREFS_MASK 0x4u
-#define MCG_C2_EREFS_SHIFT 2
-#define MCG_C2_HGO_MASK 0x8u
-#define MCG_C2_HGO_SHIFT 3
-#define MCG_C2_RANGE_MASK 0x30u
-#define MCG_C2_RANGE_SHIFT 4
-#define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)
-#define MCG_C2_FCFTRIM_MASK 0x40u
-#define MCG_C2_FCFTRIM_SHIFT 6
-#define MCG_C2_LOCRE0_MASK 0x80u
-#define MCG_C2_LOCRE0_SHIFT 7
-/* C3 Bit Fields */
-#define MCG_C3_SCTRIM_MASK 0xFFu
-#define MCG_C3_SCTRIM_SHIFT 0
-#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
-/* C4 Bit Fields */
-#define MCG_C4_SCFTRIM_MASK 0x1u
-#define MCG_C4_SCFTRIM_SHIFT 0
-#define MCG_C4_FCTRIM_MASK 0x1Eu
-#define MCG_C4_FCTRIM_SHIFT 1
-#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
-#define MCG_C4_DRST_DRS_MASK 0x60u
-#define MCG_C4_DRST_DRS_SHIFT 5
-#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
-#define MCG_C4_DMX32_MASK 0x80u
-#define MCG_C4_DMX32_SHIFT 7
-/* C5 Bit Fields */
-#define MCG_C5_PRDIV0_MASK 0x1Fu
-#define MCG_C5_PRDIV0_SHIFT 0
-#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
-#define MCG_C5_PLLSTEN0_MASK 0x20u
-#define MCG_C5_PLLSTEN0_SHIFT 5
-#define MCG_C5_PLLCLKEN0_MASK 0x40u
-#define MCG_C5_PLLCLKEN0_SHIFT 6
-/* C6 Bit Fields */
-#define MCG_C6_VDIV0_MASK 0x1Fu
-#define MCG_C6_VDIV0_SHIFT 0
-#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
-#define MCG_C6_CME0_MASK 0x20u
-#define MCG_C6_CME0_SHIFT 5
-#define MCG_C6_PLLS_MASK 0x40u
-#define MCG_C6_PLLS_SHIFT 6
-#define MCG_C6_LOLIE0_MASK 0x80u
-#define MCG_C6_LOLIE0_SHIFT 7
-/* S Bit Fields */
-#define MCG_S_IRCST_MASK 0x1u
-#define MCG_S_IRCST_SHIFT 0
-#define MCG_S_OSCINIT0_MASK 0x2u
-#define MCG_S_OSCINIT0_SHIFT 1
-#define MCG_S_CLKST_MASK 0xCu
-#define MCG_S_CLKST_SHIFT 2
-#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
-#define MCG_S_IREFST_MASK 0x10u
-#define MCG_S_IREFST_SHIFT 4
-#define MCG_S_PLLST_MASK 0x20u
-#define MCG_S_PLLST_SHIFT 5
-#define MCG_S_LOCK0_MASK 0x40u
-#define MCG_S_LOCK0_SHIFT 6
-#define MCG_S_LOLS0_MASK 0x80u
-#define MCG_S_LOLS0_SHIFT 7
-/* SC Bit Fields */
-#define MCG_SC_LOCS0_MASK 0x1u
-#define MCG_SC_LOCS0_SHIFT 0
-#define MCG_SC_FCRDIV_MASK 0xEu
-#define MCG_SC_FCRDIV_SHIFT 1
-#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
-#define MCG_SC_FLTPRSRV_MASK 0x10u
-#define MCG_SC_FLTPRSRV_SHIFT 4
-#define MCG_SC_ATMF_MASK 0x20u
-#define MCG_SC_ATMF_SHIFT 5
-#define MCG_SC_ATMS_MASK 0x40u
-#define MCG_SC_ATMS_SHIFT 6
-#define MCG_SC_ATME_MASK 0x80u
-#define MCG_SC_ATME_SHIFT 7
-/* ATCVH Bit Fields */
-#define MCG_ATCVH_ATCVH_MASK 0xFFu
-#define MCG_ATCVH_ATCVH_SHIFT 0
-#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
-/* ATCVL Bit Fields */
-#define MCG_ATCVL_ATCVL_MASK 0xFFu
-#define MCG_ATCVL_ATCVL_SHIFT 0
-#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
-/* C7 Bit Fields */
-#define MCG_C7_OSCSEL_MASK 0x3u
-#define MCG_C7_OSCSEL_SHIFT 0
-#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x))<<MCG_C7_OSCSEL_SHIFT))&MCG_C7_OSCSEL_MASK)
-/* C8 Bit Fields */
-#define MCG_C8_LOCS1_MASK 0x1u
-#define MCG_C8_LOCS1_SHIFT 0
-#define MCG_C8_CME1_MASK 0x20u
-#define MCG_C8_CME1_SHIFT 5
-#define MCG_C8_LOLRE_MASK 0x40u
-#define MCG_C8_LOLRE_SHIFT 6
-#define MCG_C8_LOCRE1_MASK 0x80u
-#define MCG_C8_LOCRE1_SHIFT 7
-
-/*!
- * @}
- */ /* end of group MCG_Register_Masks */
-
-
-/* MCG - Peripheral instance base addresses */
-/** Peripheral MCG base address */
-#define MCG_BASE (0x40064000u)
-/** Peripheral MCG base pointer */
-#define MCG ((MCG_Type *)MCG_BASE)
-#define MCG_BASE_PTR (MCG)
-/** Array initializer of MCG peripheral base pointers */
-#define MCG_BASES { MCG }
-
-/* ----------------------------------------------------------------------------
- -- MCG - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
- * @{
- */
-
-
-/* MCG - Register instance definitions */
-/* MCG */
-#define MCG_C1 MCG_C1_REG(MCG)
-#define MCG_C2 MCG_C2_REG(MCG)
-#define MCG_C3 MCG_C3_REG(MCG)
-#define MCG_C4 MCG_C4_REG(MCG)
-#define MCG_C5 MCG_C5_REG(MCG)
-#define MCG_C6 MCG_C6_REG(MCG)
-#define MCG_S MCG_S_REG(MCG)
-#define MCG_SC MCG_SC_REG(MCG)
-#define MCG_ATCVH MCG_ATCVH_REG(MCG)
-#define MCG_ATCVL MCG_ATCVL_REG(MCG)
-#define MCG_C7 MCG_C7_REG(MCG)
-#define MCG_C8 MCG_C8_REG(MCG)
-
-/*!
- * @}
- */ /* end of group MCG_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group MCG_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- MCM Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
- * @{
- */
-
-/** MCM - Register Layout Typedef */
-typedef struct {
- uint8_t RESERVED_0[8];
- __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
- __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
- __IO uint32_t CR; /**< Control Register, offset: 0xC */
- __IO uint32_t ISR; /**< Interrupt Status Register, offset: 0x10 */
- __IO uint32_t ETBCC; /**< ETB Counter Control register, offset: 0x14 */
- __IO uint32_t ETBRL; /**< ETB Reload register, offset: 0x18 */
- __I uint32_t ETBCNT; /**< ETB Counter Value register, offset: 0x1C */
- uint8_t RESERVED_1[16];
- __IO uint32_t PID; /**< Process ID register, offset: 0x30 */
-} MCM_Type, *MCM_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- MCM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
- * @{
- */
-
-
-/* MCM - Register accessors */
-#define MCM_PLASC_REG(base) ((base)->PLASC)
-#define MCM_PLAMC_REG(base) ((base)->PLAMC)
-#define MCM_CR_REG(base) ((base)->CR)
-#define MCM_ISR_REG(base) ((base)->ISR)
-#define MCM_ETBCC_REG(base) ((base)->ETBCC)
-#define MCM_ETBRL_REG(base) ((base)->ETBRL)
-#define MCM_ETBCNT_REG(base) ((base)->ETBCNT)
-#define MCM_PID_REG(base) ((base)->PID)
-
-/*!
- * @}
- */ /* end of group MCM_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- MCM Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCM_Register_Masks MCM Register Masks
- * @{
- */
-
-/* PLASC Bit Fields */
-#define MCM_PLASC_ASC_MASK 0xFFu
-#define MCM_PLASC_ASC_SHIFT 0
-#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
-/* PLAMC Bit Fields */
-#define MCM_PLAMC_AMC_MASK 0xFFu
-#define MCM_PLAMC_AMC_SHIFT 0
-#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
-/* CR Bit Fields */
-#define MCM_CR_SRAMUAP_MASK 0x3000000u
-#define MCM_CR_SRAMUAP_SHIFT 24
-#define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMUAP_SHIFT))&MCM_CR_SRAMUAP_MASK)
-#define MCM_CR_SRAMUWP_MASK 0x4000000u
-#define MCM_CR_SRAMUWP_SHIFT 26
-#define MCM_CR_SRAMLAP_MASK 0x30000000u
-#define MCM_CR_SRAMLAP_SHIFT 28
-#define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMLAP_SHIFT))&MCM_CR_SRAMLAP_MASK)
-#define MCM_CR_SRAMLWP_MASK 0x40000000u
-#define MCM_CR_SRAMLWP_SHIFT 30
-/* ISR Bit Fields */
-#define MCM_ISR_IRQ_MASK 0x2u
-#define MCM_ISR_IRQ_SHIFT 1
-#define MCM_ISR_NMI_MASK 0x4u
-#define MCM_ISR_NMI_SHIFT 2
-#define MCM_ISR_DHREQ_MASK 0x8u
-#define MCM_ISR_DHREQ_SHIFT 3
-#define MCM_ISR_FIOC_MASK 0x100u
-#define MCM_ISR_FIOC_SHIFT 8
-#define MCM_ISR_FDZC_MASK 0x200u
-#define MCM_ISR_FDZC_SHIFT 9
-#define MCM_ISR_FOFC_MASK 0x400u
-#define MCM_ISR_FOFC_SHIFT 10
-#define MCM_ISR_FUFC_MASK 0x800u
-#define MCM_ISR_FUFC_SHIFT 11
-#define MCM_ISR_FIXC_MASK 0x1000u
-#define MCM_ISR_FIXC_SHIFT 12
-#define MCM_ISR_FIDC_MASK 0x8000u
-#define MCM_ISR_FIDC_SHIFT 15
-#define MCM_ISR_FIOCE_MASK 0x1000000u
-#define MCM_ISR_FIOCE_SHIFT 24
-#define MCM_ISR_FDZCE_MASK 0x2000000u
-#define MCM_ISR_FDZCE_SHIFT 25
-#define MCM_ISR_FOFCE_MASK 0x4000000u
-#define MCM_ISR_FOFCE_SHIFT 26
-#define MCM_ISR_FUFCE_MASK 0x8000000u
-#define MCM_ISR_FUFCE_SHIFT 27
-#define MCM_ISR_FIXCE_MASK 0x10000000u
-#define MCM_ISR_FIXCE_SHIFT 28
-#define MCM_ISR_FIDCE_MASK 0x80000000u
-#define MCM_ISR_FIDCE_SHIFT 31
-/* ETBCC Bit Fields */
-#define MCM_ETBCC_CNTEN_MASK 0x1u
-#define MCM_ETBCC_CNTEN_SHIFT 0
-#define MCM_ETBCC_RSPT_MASK 0x6u
-#define MCM_ETBCC_RSPT_SHIFT 1
-#define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RSPT_SHIFT))&MCM_ETBCC_RSPT_MASK)
-#define MCM_ETBCC_RLRQ_MASK 0x8u
-#define MCM_ETBCC_RLRQ_SHIFT 3
-#define MCM_ETBCC_ETDIS_MASK 0x10u
-#define MCM_ETBCC_ETDIS_SHIFT 4
-#define MCM_ETBCC_ITDIS_MASK 0x20u
-#define MCM_ETBCC_ITDIS_SHIFT 5
-/* ETBRL Bit Fields */
-#define MCM_ETBRL_RELOAD_MASK 0x7FFu
-#define MCM_ETBRL_RELOAD_SHIFT 0
-#define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBRL_RELOAD_SHIFT))&MCM_ETBRL_RELOAD_MASK)
-/* ETBCNT Bit Fields */
-#define MCM_ETBCNT_COUNTER_MASK 0x7FFu
-#define MCM_ETBCNT_COUNTER_SHIFT 0
-#define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCNT_COUNTER_SHIFT))&MCM_ETBCNT_COUNTER_MASK)
-/* PID Bit Fields */
-#define MCM_PID_PID_MASK 0xFFu
-#define MCM_PID_PID_SHIFT 0
-#define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x))<<MCM_PID_PID_SHIFT))&MCM_PID_PID_MASK)
-
-/*!
- * @}
- */ /* end of group MCM_Register_Masks */
-
-
-/* MCM - Peripheral instance base addresses */
-/** Peripheral MCM base address */
-#define MCM_BASE (0xE0080000u)
-/** Peripheral MCM base pointer */
-#define MCM ((MCM_Type *)MCM_BASE)
-#define MCM_BASE_PTR (MCM)
-/** Array initializer of MCM peripheral base pointers */
-#define MCM_BASES { MCM }
-
-/* ----------------------------------------------------------------------------
- -- MCM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
- * @{
- */
-
-
-/* MCM - Register instance definitions */
-/* MCM */
-#define MCM_PLASC MCM_PLASC_REG(MCM)
-#define MCM_PLAMC MCM_PLAMC_REG(MCM)
-#define MCM_CR MCM_CR_REG(MCM)
-#define MCM_ISCR MCM_ISR_REG(MCM)
-#define MCM_ETBCC MCM_ETBCC_REG(MCM)
-#define MCM_ETBRL MCM_ETBRL_REG(MCM)
-#define MCM_ETBCNT MCM_ETBCNT_REG(MCM)
-#define MCM_PID MCM_PID_REG(MCM)
-
-/*!
- * @}
- */ /* end of group MCM_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group MCM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- MPU Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
- * @{
- */
-
-/** MPU - Register Layout Typedef */
-typedef struct {
- __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */
- uint8_t RESERVED_0[12];
- struct { /* offset: 0x10, array step: 0x8 */
- __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
- __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
- } SP[5];
- uint8_t RESERVED_1[968];
- __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
- uint8_t RESERVED_2[832];
- __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
-} MPU_Type, *MPU_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- MPU - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
- * @{
- */
-
-
-/* MPU - Register accessors */
-#define MPU_CESR_REG(base) ((base)->CESR)
-#define MPU_EAR_REG(base,index) ((base)->SP[index].EAR)
-#define MPU_EDR_REG(base,index) ((base)->SP[index].EDR)
-#define MPU_WORD_REG(base,index,index2) ((base)->WORD[index][index2])
-#define MPU_RGDAAC_REG(base,index) ((base)->RGDAAC[index])
-
-/*!
- * @}
- */ /* end of group MPU_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- MPU Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MPU_Register_Masks MPU Register Masks
- * @{
- */
-
-/* CESR Bit Fields */
-#define MPU_CESR_VLD_MASK 0x1u
-#define MPU_CESR_VLD_SHIFT 0
-#define MPU_CESR_NRGD_MASK 0xF00u
-#define MPU_CESR_NRGD_SHIFT 8
-#define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK)
-#define MPU_CESR_NSP_MASK 0xF000u
-#define MPU_CESR_NSP_SHIFT 12
-#define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK)
-#define MPU_CESR_HRL_MASK 0xF0000u
-#define MPU_CESR_HRL_SHIFT 16
-#define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK)
-#define MPU_CESR_SPERR_MASK 0xF8000000u
-#define MPU_CESR_SPERR_SHIFT 27
-#define MPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR_SHIFT))&MPU_CESR_SPERR_MASK)
-/* EAR Bit Fields */
-#define MPU_EAR_EADDR_MASK 0xFFFFFFFFu
-#define MPU_EAR_EADDR_SHIFT 0
-#define MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK)
-/* EDR Bit Fields */
-#define MPU_EDR_ERW_MASK 0x1u
-#define MPU_EDR_ERW_SHIFT 0
-#define MPU_EDR_EATTR_MASK 0xEu
-#define MPU_EDR_EATTR_SHIFT 1
-#define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK)
-#define MPU_EDR_EMN_MASK 0xF0u
-#define MPU_EDR_EMN_SHIFT 4
-#define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK)
-#define MPU_EDR_EPID_MASK 0xFF00u
-#define MPU_EDR_EPID_SHIFT 8
-#define MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EPID_SHIFT))&MPU_EDR_EPID_MASK)
-#define MPU_EDR_EACD_MASK 0xFFFF0000u
-#define MPU_EDR_EACD_SHIFT 16
-#define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK)
-/* WORD Bit Fields */
-#define MPU_WORD_VLD_MASK 0x1u
-#define MPU_WORD_VLD_SHIFT 0
-#define MPU_WORD_M0UM_MASK 0x7u
-#define MPU_WORD_M0UM_SHIFT 0
-#define MPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0UM_SHIFT))&MPU_WORD_M0UM_MASK)
-#define MPU_WORD_M0SM_MASK 0x18u
-#define MPU_WORD_M0SM_SHIFT 3
-#define MPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0SM_SHIFT))&MPU_WORD_M0SM_MASK)
-#define MPU_WORD_M0PE_MASK 0x20u
-#define MPU_WORD_M0PE_SHIFT 5
-#define MPU_WORD_ENDADDR_MASK 0xFFFFFFE0u
-#define MPU_WORD_ENDADDR_SHIFT 5
-#define MPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_ENDADDR_SHIFT))&MPU_WORD_ENDADDR_MASK)
-#define MPU_WORD_SRTADDR_MASK 0xFFFFFFE0u
-#define MPU_WORD_SRTADDR_SHIFT 5
-#define MPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_SRTADDR_SHIFT))&MPU_WORD_SRTADDR_MASK)
-#define MPU_WORD_M1UM_MASK 0x1C0u
-#define MPU_WORD_M1UM_SHIFT 6
-#define MPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1UM_SHIFT))&MPU_WORD_M1UM_MASK)
-#define MPU_WORD_M1SM_MASK 0x600u
-#define MPU_WORD_M1SM_SHIFT 9
-#define MPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1SM_SHIFT))&MPU_WORD_M1SM_MASK)
-#define MPU_WORD_M1PE_MASK 0x800u
-#define MPU_WORD_M1PE_SHIFT 11
-#define MPU_WORD_M2UM_MASK 0x7000u
-#define MPU_WORD_M2UM_SHIFT 12
-#define MPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2UM_SHIFT))&MPU_WORD_M2UM_MASK)
-#define MPU_WORD_M2SM_MASK 0x18000u
-#define MPU_WORD_M2SM_SHIFT 15
-#define MPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2SM_SHIFT))&MPU_WORD_M2SM_MASK)
-#define MPU_WORD_PIDMASK_MASK 0xFF0000u
-#define MPU_WORD_PIDMASK_SHIFT 16
-#define MPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PIDMASK_SHIFT))&MPU_WORD_PIDMASK_MASK)
-#define MPU_WORD_M2PE_MASK 0x20000u
-#define MPU_WORD_M2PE_SHIFT 17
-#define MPU_WORD_M3UM_MASK 0x1C0000u
-#define MPU_WORD_M3UM_SHIFT 18
-#define MPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3UM_SHIFT))&MPU_WORD_M3UM_MASK)
-#define MPU_WORD_M3SM_MASK 0x600000u
-#define MPU_WORD_M3SM_SHIFT 21
-#define MPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3SM_SHIFT))&MPU_WORD_M3SM_MASK)
-#define MPU_WORD_M3PE_MASK 0x800000u
-#define MPU_WORD_M3PE_SHIFT 23
-#define MPU_WORD_PID_MASK 0xFF000000u
-#define MPU_WORD_PID_SHIFT 24
-#define MPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PID_SHIFT))&MPU_WORD_PID_MASK)
-#define MPU_WORD_M4WE_MASK 0x1000000u
-#define MPU_WORD_M4WE_SHIFT 24
-#define MPU_WORD_M4RE_MASK 0x2000000u
-#define MPU_WORD_M4RE_SHIFT 25
-#define MPU_WORD_M5WE_MASK 0x4000000u
-#define MPU_WORD_M5WE_SHIFT 26
-#define MPU_WORD_M5RE_MASK 0x8000000u
-#define MPU_WORD_M5RE_SHIFT 27
-#define MPU_WORD_M6WE_MASK 0x10000000u
-#define MPU_WORD_M6WE_SHIFT 28
-#define MPU_WORD_M6RE_MASK 0x20000000u
-#define MPU_WORD_M6RE_SHIFT 29
-#define MPU_WORD_M7WE_MASK 0x40000000u
-#define MPU_WORD_M7WE_SHIFT 30
-#define MPU_WORD_M7RE_MASK 0x80000000u
-#define MPU_WORD_M7RE_SHIFT 31
-/* RGDAAC Bit Fields */
-#define MPU_RGDAAC_M0UM_MASK 0x7u
-#define MPU_RGDAAC_M0UM_SHIFT 0
-#define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK)
-#define MPU_RGDAAC_M0SM_MASK 0x18u
-#define MPU_RGDAAC_M0SM_SHIFT 3
-#define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK)
-#define MPU_RGDAAC_M0PE_MASK 0x20u
-#define MPU_RGDAAC_M0PE_SHIFT 5
-#define MPU_RGDAAC_M1UM_MASK 0x1C0u
-#define MPU_RGDAAC_M1UM_SHIFT 6
-#define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK)
-#define MPU_RGDAAC_M1SM_MASK 0x600u
-#define MPU_RGDAAC_M1SM_SHIFT 9
-#define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK)
-#define MPU_RGDAAC_M1PE_MASK 0x800u
-#define MPU_RGDAAC_M1PE_SHIFT 11
-#define MPU_RGDAAC_M2UM_MASK 0x7000u
-#define MPU_RGDAAC_M2UM_SHIFT 12
-#define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK)
-#define MPU_RGDAAC_M2SM_MASK 0x18000u
-#define MPU_RGDAAC_M2SM_SHIFT 15
-#define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK)
-#define MPU_RGDAAC_M2PE_MASK 0x20000u
-#define MPU_RGDAAC_M2PE_SHIFT 17
-#define MPU_RGDAAC_M3UM_MASK 0x1C0000u
-#define MPU_RGDAAC_M3UM_SHIFT 18
-#define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK)
-#define MPU_RGDAAC_M3SM_MASK 0x600000u
-#define MPU_RGDAAC_M3SM_SHIFT 21
-#define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK)
-#define MPU_RGDAAC_M3PE_MASK 0x800000u
-#define MPU_RGDAAC_M3PE_SHIFT 23
-#define MPU_RGDAAC_M4WE_MASK 0x1000000u
-#define MPU_RGDAAC_M4WE_SHIFT 24
-#define MPU_RGDAAC_M4RE_MASK 0x2000000u
-#define MPU_RGDAAC_M4RE_SHIFT 25
-#define MPU_RGDAAC_M5WE_MASK 0x4000000u
-#define MPU_RGDAAC_M5WE_SHIFT 26
-#define MPU_RGDAAC_M5RE_MASK 0x8000000u
-#define MPU_RGDAAC_M5RE_SHIFT 27
-#define MPU_RGDAAC_M6WE_MASK 0x10000000u
-#define MPU_RGDAAC_M6WE_SHIFT 28
-#define MPU_RGDAAC_M6RE_MASK 0x20000000u
-#define MPU_RGDAAC_M6RE_SHIFT 29
-#define MPU_RGDAAC_M7WE_MASK 0x40000000u
-#define MPU_RGDAAC_M7WE_SHIFT 30
-#define MPU_RGDAAC_M7RE_MASK 0x80000000u
-#define MPU_RGDAAC_M7RE_SHIFT 31
-
-/*!
- * @}
- */ /* end of group MPU_Register_Masks */
-
-
-/* MPU - Peripheral instance base addresses */
-/** Peripheral MPU base address */
-#define MPU_BASE (0x4000D000u)
-/** Peripheral MPU base pointer */
-#define MPU ((MPU_Type *)MPU_BASE)
-#define MPU_BASE_PTR (MPU)
-/** Array initializer of MPU peripheral base pointers */
-#define MPU_BASES { MPU }
-
-/* ----------------------------------------------------------------------------
- -- MPU - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
- * @{
- */
-
-
-/* MPU - Register instance definitions */
-/* MPU */
-#define MPU_CESR MPU_CESR_REG(MPU)
-#define MPU_EAR0 MPU_EAR_REG(MPU,0)
-#define MPU_EDR0 MPU_EDR_REG(MPU,0)
-#define MPU_EAR1 MPU_EAR_REG(MPU,1)
-#define MPU_EDR1 MPU_EDR_REG(MPU,1)
-#define MPU_EAR2 MPU_EAR_REG(MPU,2)
-#define MPU_EDR2 MPU_EDR_REG(MPU,2)
-#define MPU_EAR3 MPU_EAR_REG(MPU,3)
-#define MPU_EDR3 MPU_EDR_REG(MPU,3)
-#define MPU_EAR4 MPU_EAR_REG(MPU,4)
-#define MPU_EDR4 MPU_EDR_REG(MPU,4)
-#define MPU_RGD0_WORD0 MPU_WORD_REG(MPU,0,0)
-#define MPU_RGD0_WORD1 MPU_WORD_REG(MPU,0,1)
-#define MPU_RGD0_WORD2 MPU_WORD_REG(MPU,0,2)
-#define MPU_RGD0_WORD3 MPU_WORD_REG(MPU,0,3)
-#define MPU_RGD1_WORD0 MPU_WORD_REG(MPU,1,0)
-#define MPU_RGD1_WORD1 MPU_WORD_REG(MPU,1,1)
-#define MPU_RGD1_WORD2 MPU_WORD_REG(MPU,1,2)
-#define MPU_RGD1_WORD3 MPU_WORD_REG(MPU,1,3)
-#define MPU_RGD2_WORD0 MPU_WORD_REG(MPU,2,0)
-#define MPU_RGD2_WORD1 MPU_WORD_REG(MPU,2,1)
-#define MPU_RGD2_WORD2 MPU_WORD_REG(MPU,2,2)
-#define MPU_RGD2_WORD3 MPU_WORD_REG(MPU,2,3)
-#define MPU_RGD3_WORD0 MPU_WORD_REG(MPU,3,0)
-#define MPU_RGD3_WORD1 MPU_WORD_REG(MPU,3,1)
-#define MPU_RGD3_WORD2 MPU_WORD_REG(MPU,3,2)
-#define MPU_RGD3_WORD3 MPU_WORD_REG(MPU,3,3)
-#define MPU_RGD4_WORD0 MPU_WORD_REG(MPU,4,0)
-#define MPU_RGD4_WORD1 MPU_WORD_REG(MPU,4,1)
-#define MPU_RGD4_WORD2 MPU_WORD_REG(MPU,4,2)
-#define MPU_RGD4_WORD3 MPU_WORD_REG(MPU,4,3)
-#define MPU_RGD5_WORD0 MPU_WORD_REG(MPU,5,0)
-#define MPU_RGD5_WORD1 MPU_WORD_REG(MPU,5,1)
-#define MPU_RGD5_WORD2 MPU_WORD_REG(MPU,5,2)
-#define MPU_RGD5_WORD3 MPU_WORD_REG(MPU,5,3)
-#define MPU_RGD6_WORD0 MPU_WORD_REG(MPU,6,0)
-#define MPU_RGD6_WORD1 MPU_WORD_REG(MPU,6,1)
-#define MPU_RGD6_WORD2 MPU_WORD_REG(MPU,6,2)
-#define MPU_RGD6_WORD3 MPU_WORD_REG(MPU,6,3)
-#define MPU_RGD7_WORD0 MPU_WORD_REG(MPU,7,0)
-#define MPU_RGD7_WORD1 MPU_WORD_REG(MPU,7,1)
-#define MPU_RGD7_WORD2 MPU_WORD_REG(MPU,7,2)
-#define MPU_RGD7_WORD3 MPU_WORD_REG(MPU,7,3)
-#define MPU_RGD8_WORD0 MPU_WORD_REG(MPU,8,0)
-#define MPU_RGD8_WORD1 MPU_WORD_REG(MPU,8,1)
-#define MPU_RGD8_WORD2 MPU_WORD_REG(MPU,8,2)
-#define MPU_RGD8_WORD3 MPU_WORD_REG(MPU,8,3)
-#define MPU_RGD9_WORD0 MPU_WORD_REG(MPU,9,0)
-#define MPU_RGD9_WORD1 MPU_WORD_REG(MPU,9,1)
-#define MPU_RGD9_WORD2 MPU_WORD_REG(MPU,9,2)
-#define MPU_RGD9_WORD3 MPU_WORD_REG(MPU,9,3)
-#define MPU_RGD10_WORD0 MPU_WORD_REG(MPU,10,0)
-#define MPU_RGD10_WORD1 MPU_WORD_REG(MPU,10,1)
-#define MPU_RGD10_WORD2 MPU_WORD_REG(MPU,10,2)
-#define MPU_RGD10_WORD3 MPU_WORD_REG(MPU,10,3)
-#define MPU_RGD11_WORD0 MPU_WORD_REG(MPU,11,0)
-#define MPU_RGD11_WORD1 MPU_WORD_REG(MPU,11,1)
-#define MPU_RGD11_WORD2 MPU_WORD_REG(MPU,11,2)
-#define MPU_RGD11_WORD3 MPU_WORD_REG(MPU,11,3)
-#define MPU_RGDAAC0 MPU_RGDAAC_REG(MPU,0)
-#define MPU_RGDAAC1 MPU_RGDAAC_REG(MPU,1)
-#define MPU_RGDAAC2 MPU_RGDAAC_REG(MPU,2)
-#define MPU_RGDAAC3 MPU_RGDAAC_REG(MPU,3)
-#define MPU_RGDAAC4 MPU_RGDAAC_REG(MPU,4)
-#define MPU_RGDAAC5 MPU_RGDAAC_REG(MPU,5)
-#define MPU_RGDAAC6 MPU_RGDAAC_REG(MPU,6)
-#define MPU_RGDAAC7 MPU_RGDAAC_REG(MPU,7)
-#define MPU_RGDAAC8 MPU_RGDAAC_REG(MPU,8)
-#define MPU_RGDAAC9 MPU_RGDAAC_REG(MPU,9)
-#define MPU_RGDAAC10 MPU_RGDAAC_REG(MPU,10)
-#define MPU_RGDAAC11 MPU_RGDAAC_REG(MPU,11)
-
-/* MPU - Register array accessors */
-#define MPU_EAR(index) MPU_EAR_REG(MPU,index)
-#define MPU_EDR(index) MPU_EDR_REG(MPU,index)
-#define MPU_WORD(index,index2) MPU_WORD_REG(MPU,index,index2)
-#define MPU_RGDAAC(index) MPU_RGDAAC_REG(MPU,index)
-
-/*!
- * @}
- */ /* end of group MPU_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group MPU_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- NV Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
- * @{
- */
-
-/** NV - Register Layout Typedef */
-typedef struct {
- __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
- __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
- __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
- __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
- __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
- __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
- __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
- __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
- __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
- __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
- __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
- __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
- __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
- __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
- __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
- __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
-} NV_Type, *NV_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- NV - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
- * @{
- */
-
-
-/* NV - Register accessors */
-#define NV_BACKKEY3_REG(base) ((base)->BACKKEY3)
-#define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
-#define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
-#define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
-#define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
-#define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
-#define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
-#define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
-#define NV_FPROT3_REG(base) ((base)->FPROT3)
-#define NV_FPROT2_REG(base) ((base)->FPROT2)
-#define NV_FPROT1_REG(base) ((base)->FPROT1)
-#define NV_FPROT0_REG(base) ((base)->FPROT0)
-#define NV_FSEC_REG(base) ((base)->FSEC)
-#define NV_FOPT_REG(base) ((base)->FOPT)
-#define NV_FEPROT_REG(base) ((base)->FEPROT)
-#define NV_FDPROT_REG(base) ((base)->FDPROT)
-
-/*!
- * @}
- */ /* end of group NV_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- NV Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup NV_Register_Masks NV Register Masks
- * @{
- */
-
-/* BACKKEY3 Bit Fields */
-#define NV_BACKKEY3_KEY_MASK 0xFFu
-#define NV_BACKKEY3_KEY_SHIFT 0
-#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
-/* BACKKEY2 Bit Fields */
-#define NV_BACKKEY2_KEY_MASK 0xFFu
-#define NV_BACKKEY2_KEY_SHIFT 0
-#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
-/* BACKKEY1 Bit Fields */
-#define NV_BACKKEY1_KEY_MASK 0xFFu
-#define NV_BACKKEY1_KEY_SHIFT 0
-#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
-/* BACKKEY0 Bit Fields */
-#define NV_BACKKEY0_KEY_MASK 0xFFu
-#define NV_BACKKEY0_KEY_SHIFT 0
-#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
-/* BACKKEY7 Bit Fields */
-#define NV_BACKKEY7_KEY_MASK 0xFFu
-#define NV_BACKKEY7_KEY_SHIFT 0
-#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
-/* BACKKEY6 Bit Fields */
-#define NV_BACKKEY6_KEY_MASK 0xFFu
-#define NV_BACKKEY6_KEY_SHIFT 0
-#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
-/* BACKKEY5 Bit Fields */
-#define NV_BACKKEY5_KEY_MASK 0xFFu
-#define NV_BACKKEY5_KEY_SHIFT 0
-#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
-/* BACKKEY4 Bit Fields */
-#define NV_BACKKEY4_KEY_MASK 0xFFu
-#define NV_BACKKEY4_KEY_SHIFT 0
-#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
-/* FPROT3 Bit Fields */
-#define NV_FPROT3_PROT_MASK 0xFFu
-#define NV_FPROT3_PROT_SHIFT 0
-#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
-/* FPROT2 Bit Fields */
-#define NV_FPROT2_PROT_MASK 0xFFu
-#define NV_FPROT2_PROT_SHIFT 0
-#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
-/* FPROT1 Bit Fields */
-#define NV_FPROT1_PROT_MASK 0xFFu
-#define NV_FPROT1_PROT_SHIFT 0
-#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
-/* FPROT0 Bit Fields */
-#define NV_FPROT0_PROT_MASK 0xFFu
-#define NV_FPROT0_PROT_SHIFT 0
-#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
-/* FSEC Bit Fields */
-#define NV_FSEC_SEC_MASK 0x3u
-#define NV_FSEC_SEC_SHIFT 0
-#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
-#define NV_FSEC_FSLACC_MASK 0xCu
-#define NV_FSEC_FSLACC_SHIFT 2
-#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
-#define NV_FSEC_MEEN_MASK 0x30u
-#define NV_FSEC_MEEN_SHIFT 4
-#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
-#define NV_FSEC_KEYEN_MASK 0xC0u
-#define NV_FSEC_KEYEN_SHIFT 6
-#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
-/* FOPT Bit Fields */
-#define NV_FOPT_LPBOOT_MASK 0x1u
-#define NV_FOPT_LPBOOT_SHIFT 0
-#define NV_FOPT_EZPORT_DIS_MASK 0x2u
-#define NV_FOPT_EZPORT_DIS_SHIFT 1
-/* FEPROT Bit Fields */
-#define NV_FEPROT_EPROT_MASK 0xFFu
-#define NV_FEPROT_EPROT_SHIFT 0
-#define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
-/* FDPROT Bit Fields */
-#define NV_FDPROT_DPROT_MASK 0xFFu
-#define NV_FDPROT_DPROT_SHIFT 0
-#define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
-
-/*!
- * @}
- */ /* end of group NV_Register_Masks */
-
-
-/* NV - Peripheral instance base addresses */
-/** Peripheral FTFE_FlashConfig base address */
-#define FTFE_FlashConfig_BASE (0x400u)
-/** Peripheral FTFE_FlashConfig base pointer */
-#define FTFE_FlashConfig ((NV_Type *)FTFE_FlashConfig_BASE)
-#define FTFE_FlashConfig_BASE_PTR (FTFE_FlashConfig)
-/** Array initializer of NV peripheral base pointers */
-#define NV_BASES { FTFE_FlashConfig }
-
-/* ----------------------------------------------------------------------------
- -- NV - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
- * @{
- */
-
-
-/* NV - Register instance definitions */
-/* FTFE_FlashConfig */
-#define NV_BACKKEY3 NV_BACKKEY3_REG(FTFE_FlashConfig)
-#define NV_BACKKEY2 NV_BACKKEY2_REG(FTFE_FlashConfig)
-#define NV_BACKKEY1 NV_BACKKEY1_REG(FTFE_FlashConfig)
-#define NV_BACKKEY0 NV_BACKKEY0_REG(FTFE_FlashConfig)
-#define NV_BACKKEY7 NV_BACKKEY7_REG(FTFE_FlashConfig)
-#define NV_BACKKEY6 NV_BACKKEY6_REG(FTFE_FlashConfig)
-#define NV_BACKKEY5 NV_BACKKEY5_REG(FTFE_FlashConfig)
-#define NV_BACKKEY4 NV_BACKKEY4_REG(FTFE_FlashConfig)
-#define NV_FPROT3 NV_FPROT3_REG(FTFE_FlashConfig)
-#define NV_FPROT2 NV_FPROT2_REG(FTFE_FlashConfig)
-#define NV_FPROT1 NV_FPROT1_REG(FTFE_FlashConfig)
-#define NV_FPROT0 NV_FPROT0_REG(FTFE_FlashConfig)
-#define NV_FSEC NV_FSEC_REG(FTFE_FlashConfig)
-#define NV_FOPT NV_FOPT_REG(FTFE_FlashConfig)
-#define NV_FEPROT NV_FEPROT_REG(FTFE_FlashConfig)
-#define NV_FDPROT NV_FDPROT_REG(FTFE_FlashConfig)
-
-/*!
- * @}
- */ /* end of group NV_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group NV_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- OSC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
- * @{
- */
-
-/** OSC - Register Layout Typedef */
-typedef struct {
- __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
-} OSC_Type, *OSC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- OSC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
- * @{
- */
-
-
-/* OSC - Register accessors */
-#define OSC_CR_REG(base) ((base)->CR)
-
-/*!
- * @}
- */ /* end of group OSC_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- OSC Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup OSC_Register_Masks OSC Register Masks
- * @{
- */
-
-/* CR Bit Fields */
-#define OSC_CR_SC16P_MASK 0x1u
-#define OSC_CR_SC16P_SHIFT 0
-#define OSC_CR_SC8P_MASK 0x2u
-#define OSC_CR_SC8P_SHIFT 1
-#define OSC_CR_SC4P_MASK 0x4u
-#define OSC_CR_SC4P_SHIFT 2
-#define OSC_CR_SC2P_MASK 0x8u
-#define OSC_CR_SC2P_SHIFT 3
-#define OSC_CR_EREFSTEN_MASK 0x20u
-#define OSC_CR_EREFSTEN_SHIFT 5
-#define OSC_CR_ERCLKEN_MASK 0x80u
-#define OSC_CR_ERCLKEN_SHIFT 7
-
-/*!
- * @}
- */ /* end of group OSC_Register_Masks */
-
-
-/* OSC - Peripheral instance base addresses */
-/** Peripheral OSC base address */
-#define OSC_BASE (0x40065000u)
-/** Peripheral OSC base pointer */
-#define OSC ((OSC_Type *)OSC_BASE)
-#define OSC_BASE_PTR (OSC)
-/** Array initializer of OSC peripheral base pointers */
-#define OSC_BASES { OSC }
-
-/* ----------------------------------------------------------------------------
- -- OSC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
- * @{
- */
-
-
-/* OSC - Register instance definitions */
-/* OSC */
-#define OSC_CR OSC_CR_REG(OSC)
-
-/*!
- * @}
- */ /* end of group OSC_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group OSC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- PDB Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
- * @{
- */
-
-/** PDB - Register Layout Typedef */
-typedef struct {
- __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
- __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
- __I uint32_t CNT; /**< Counter register, offset: 0x8 */
- __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
- struct { /* offset: 0x10, array step: 0x28 */
- __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
- __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
- __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
- uint8_t RESERVED_0[24];
- } CH[2];
- uint8_t RESERVED_0[240];
- struct { /* offset: 0x150, array step: 0x8 */
- __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
- __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
- } DAC[2];
- uint8_t RESERVED_1[48];
- __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
- __IO uint32_t PODLY[3]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
-} PDB_Type, *PDB_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- PDB - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
- * @{
- */
-
-
-/* PDB - Register accessors */
-#define PDB_SC_REG(base) ((base)->SC)
-#define PDB_MOD_REG(base) ((base)->MOD)
-#define PDB_CNT_REG(base) ((base)->CNT)
-#define PDB_IDLY_REG(base) ((base)->IDLY)
-#define PDB_C1_REG(base,index) ((base)->CH[index].C1)
-#define PDB_S_REG(base,index) ((base)->CH[index].S)
-#define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2])
-#define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC)
-#define PDB_INT_REG(base,index) ((base)->DAC[index].INT)
-#define PDB_POEN_REG(base) ((base)->POEN)
-#define PDB_PODLY_REG(base,index) ((base)->PODLY[index])
-
-/*!
- * @}
- */ /* end of group PDB_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- PDB Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PDB_Register_Masks PDB Register Masks
- * @{
- */
-
-/* SC Bit Fields */
-#define PDB_SC_LDOK_MASK 0x1u
-#define PDB_SC_LDOK_SHIFT 0
-#define PDB_SC_CONT_MASK 0x2u
-#define PDB_SC_CONT_SHIFT 1
-#define PDB_SC_MULT_MASK 0xCu
-#define PDB_SC_MULT_SHIFT 2
-#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
-#define PDB_SC_PDBIE_MASK 0x20u
-#define PDB_SC_PDBIE_SHIFT 5
-#define PDB_SC_PDBIF_MASK 0x40u
-#define PDB_SC_PDBIF_SHIFT 6
-#define PDB_SC_PDBEN_MASK 0x80u
-#define PDB_SC_PDBEN_SHIFT 7
-#define PDB_SC_TRGSEL_MASK 0xF00u
-#define PDB_SC_TRGSEL_SHIFT 8
-#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
-#define PDB_SC_PRESCALER_MASK 0x7000u
-#define PDB_SC_PRESCALER_SHIFT 12
-#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
-#define PDB_SC_DMAEN_MASK 0x8000u
-#define PDB_SC_DMAEN_SHIFT 15
-#define PDB_SC_SWTRIG_MASK 0x10000u
-#define PDB_SC_SWTRIG_SHIFT 16
-#define PDB_SC_PDBEIE_MASK 0x20000u
-#define PDB_SC_PDBEIE_SHIFT 17
-#define PDB_SC_LDMOD_MASK 0xC0000u
-#define PDB_SC_LDMOD_SHIFT 18
-#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
-/* MOD Bit Fields */
-#define PDB_MOD_MOD_MASK 0xFFFFu
-#define PDB_MOD_MOD_SHIFT 0
-#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
-/* CNT Bit Fields */
-#define PDB_CNT_CNT_MASK 0xFFFFu
-#define PDB_CNT_CNT_SHIFT 0
-#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
-/* IDLY Bit Fields */
-#define PDB_IDLY_IDLY_MASK 0xFFFFu
-#define PDB_IDLY_IDLY_SHIFT 0
-#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
-/* C1 Bit Fields */
-#define PDB_C1_EN_MASK 0xFFu
-#define PDB_C1_EN_SHIFT 0
-#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
-#define PDB_C1_TOS_MASK 0xFF00u
-#define PDB_C1_TOS_SHIFT 8
-#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
-#define PDB_C1_BB_MASK 0xFF0000u
-#define PDB_C1_BB_SHIFT 16
-#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
-/* S Bit Fields */
-#define PDB_S_ERR_MASK 0xFFu
-#define PDB_S_ERR_SHIFT 0
-#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
-#define PDB_S_CF_MASK 0xFF0000u
-#define PDB_S_CF_SHIFT 16
-#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
-/* DLY Bit Fields */
-#define PDB_DLY_DLY_MASK 0xFFFFu
-#define PDB_DLY_DLY_SHIFT 0
-#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
-/* INTC Bit Fields */
-#define PDB_INTC_TOE_MASK 0x1u
-#define PDB_INTC_TOE_SHIFT 0
-#define PDB_INTC_EXT_MASK 0x2u
-#define PDB_INTC_EXT_SHIFT 1
-/* INT Bit Fields */
-#define PDB_INT_INT_MASK 0xFFFFu
-#define PDB_INT_INT_SHIFT 0
-#define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
-/* POEN Bit Fields */
-#define PDB_POEN_POEN_MASK 0xFFu
-#define PDB_POEN_POEN_SHIFT 0
-#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
-/* PODLY Bit Fields */
-#define PDB_PODLY_DLY2_MASK 0xFFFFu
-#define PDB_PODLY_DLY2_SHIFT 0
-#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
-#define PDB_PODLY_DLY1_MASK 0xFFFF0000u
-#define PDB_PODLY_DLY1_SHIFT 16
-#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
-
-/*!
- * @}
- */ /* end of group PDB_Register_Masks */
-
-
-/* PDB - Peripheral instance base addresses */
-/** Peripheral PDB0 base address */
-#define PDB0_BASE (0x40036000u)
-/** Peripheral PDB0 base pointer */
-#define PDB0 ((PDB_Type *)PDB0_BASE)
-#define PDB0_BASE_PTR (PDB0)
-/** Array initializer of PDB peripheral base pointers */
-#define PDB_BASES { PDB0 }
-
-/* ----------------------------------------------------------------------------
- -- PDB - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
- * @{
- */
-
-
-/* PDB - Register instance definitions */
-/* PDB0 */
-#define PDB0_SC PDB_SC_REG(PDB0)
-#define PDB0_MOD PDB_MOD_REG(PDB0)
-#define PDB0_CNT PDB_CNT_REG(PDB0)
-#define PDB0_IDLY PDB_IDLY_REG(PDB0)
-#define PDB0_CH0C1 PDB_C1_REG(PDB0,0)
-#define PDB0_CH0S PDB_S_REG(PDB0,0)
-#define PDB0_CH0DLY0 PDB_DLY_REG(PDB0,0,0)
-#define PDB0_CH0DLY1 PDB_DLY_REG(PDB0,0,1)
-#define PDB0_CH1C1 PDB_C1_REG(PDB0,1)
-#define PDB0_CH1S PDB_S_REG(PDB0,1)
-#define PDB0_CH1DLY0 PDB_DLY_REG(PDB0,1,0)
-#define PDB0_CH1DLY1 PDB_DLY_REG(PDB0,1,1)
-#define PDB0_DACINTC0 PDB_INTC_REG(PDB0,0)
-#define PDB0_DACINT0 PDB_INT_REG(PDB0,0)
-#define PDB0_DACINTC1 PDB_INTC_REG(PDB0,1)
-#define PDB0_DACINT1 PDB_INT_REG(PDB0,1)
-#define PDB0_POEN PDB_POEN_REG(PDB0)
-#define PDB0_PO0DLY PDB_PODLY_REG(PDB0,0)
-#define PDB0_PO1DLY PDB_PODLY_REG(PDB0,1)
-#define PDB0_PO2DLY PDB_PODLY_REG(PDB0,2)
-
-/* PDB - Register array accessors */
-#define PDB0_C1(index) PDB_C1_REG(PDB0,index)
-#define PDB0_S(index) PDB_S_REG(PDB0,index)
-#define PDB0_DLY(index,index2) PDB_DLY_REG(PDB0,index,index2)
-#define PDB0_INTC(index) PDB_INTC_REG(PDB0,index)
-#define PDB0_INT(index) PDB_INT_REG(PDB0,index)
-#define PDB0_PODLY(index) PDB_PODLY_REG(PDB0,index)
-
-/*!
- * @}
- */ /* end of group PDB_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group PDB_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- PIT Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
- * @{
- */
-
-/** PIT - Register Layout Typedef */
-typedef struct {
- __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
- uint8_t RESERVED_0[252];
- struct { /* offset: 0x100, array step: 0x10 */
- __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
- __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
- __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
- __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
- } CHANNEL[4];
-} PIT_Type, *PIT_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- PIT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
- * @{
- */
-
-
-/* PIT - Register accessors */
-#define PIT_MCR_REG(base) ((base)->MCR)
-#define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL)
-#define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
-#define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
-#define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
-
-/*!
- * @}
- */ /* end of group PIT_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- PIT Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PIT_Register_Masks PIT Register Masks
- * @{
- */
-
-/* MCR Bit Fields */
-#define PIT_MCR_FRZ_MASK 0x1u
-#define PIT_MCR_FRZ_SHIFT 0
-#define PIT_MCR_MDIS_MASK 0x2u
-#define PIT_MCR_MDIS_SHIFT 1
-/* LDVAL Bit Fields */
-#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
-#define PIT_LDVAL_TSV_SHIFT 0
-#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
-/* CVAL Bit Fields */
-#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
-#define PIT_CVAL_TVL_SHIFT 0
-#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
-/* TCTRL Bit Fields */
-#define PIT_TCTRL_TEN_MASK 0x1u
-#define PIT_TCTRL_TEN_SHIFT 0
-#define PIT_TCTRL_TIE_MASK 0x2u
-#define PIT_TCTRL_TIE_SHIFT 1
-#define PIT_TCTRL_CHN_MASK 0x4u
-#define PIT_TCTRL_CHN_SHIFT 2
-/* TFLG Bit Fields */
-#define PIT_TFLG_TIF_MASK 0x1u
-#define PIT_TFLG_TIF_SHIFT 0
-
-/*!
- * @}
- */ /* end of group PIT_Register_Masks */
-
-
-/* PIT - Peripheral instance base addresses */
-/** Peripheral PIT base address */
-#define PIT_BASE (0x40037000u)
-/** Peripheral PIT base pointer */
-#define PIT ((PIT_Type *)PIT_BASE)
-#define PIT_BASE_PTR (PIT)
-/** Array initializer of PIT peripheral base pointers */
-#define PIT_BASES { PIT }
-
-/* ----------------------------------------------------------------------------
- -- PIT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
- * @{
- */
-
-
-/* PIT - Register instance definitions */
-/* PIT */
-#define PIT_MCR PIT_MCR_REG(PIT)
-#define PIT_LDVAL0 PIT_LDVAL_REG(PIT,0)
-#define PIT_CVAL0 PIT_CVAL_REG(PIT,0)
-#define PIT_TCTRL0 PIT_TCTRL_REG(PIT,0)
-#define PIT_TFLG0 PIT_TFLG_REG(PIT,0)
-#define PIT_LDVAL1 PIT_LDVAL_REG(PIT,1)
-#define PIT_CVAL1 PIT_CVAL_REG(PIT,1)
-#define PIT_TCTRL1 PIT_TCTRL_REG(PIT,1)
-#define PIT_TFLG1 PIT_TFLG_REG(PIT,1)
-#define PIT_LDVAL2 PIT_LDVAL_REG(PIT,2)
-#define PIT_CVAL2 PIT_CVAL_REG(PIT,2)
-#define PIT_TCTRL2 PIT_TCTRL_REG(PIT,2)
-#define PIT_TFLG2 PIT_TFLG_REG(PIT,2)
-#define PIT_LDVAL3 PIT_LDVAL_REG(PIT,3)
-#define PIT_CVAL3 PIT_CVAL_REG(PIT,3)
-#define PIT_TCTRL3 PIT_TCTRL_REG(PIT,3)
-#define PIT_TFLG3 PIT_TFLG_REG(PIT,3)
-
-/* PIT - Register array accessors */
-#define PIT_LDVAL(index) PIT_LDVAL_REG(PIT,index)
-#define PIT_CVAL(index) PIT_CVAL_REG(PIT,index)
-#define PIT_TCTRL(index) PIT_TCTRL_REG(PIT,index)
-#define PIT_TFLG(index) PIT_TFLG_REG(PIT,index)
-
-/*!
- * @}
- */ /* end of group PIT_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group PIT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- PMC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
- * @{
- */
-
-/** PMC - Register Layout Typedef */
-typedef struct {
- __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
- __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
- __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
-} PMC_Type, *PMC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- PMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
- * @{
- */
-
-
-/* PMC - Register accessors */
-#define PMC_LVDSC1_REG(base) ((base)->LVDSC1)
-#define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
-#define PMC_REGSC_REG(base) ((base)->REGSC)
-
-/*!
- * @}
- */ /* end of group PMC_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- PMC Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PMC_Register_Masks PMC Register Masks
- * @{
- */
-
-/* LVDSC1 Bit Fields */
-#define PMC_LVDSC1_LVDV_MASK 0x3u
-#define PMC_LVDSC1_LVDV_SHIFT 0
-#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
-#define PMC_LVDSC1_LVDRE_MASK 0x10u
-#define PMC_LVDSC1_LVDRE_SHIFT 4
-#define PMC_LVDSC1_LVDIE_MASK 0x20u
-#define PMC_LVDSC1_LVDIE_SHIFT 5
-#define PMC_LVDSC1_LVDACK_MASK 0x40u
-#define PMC_LVDSC1_LVDACK_SHIFT 6
-#define PMC_LVDSC1_LVDF_MASK 0x80u
-#define PMC_LVDSC1_LVDF_SHIFT 7
-/* LVDSC2 Bit Fields */
-#define PMC_LVDSC2_LVWV_MASK 0x3u
-#define PMC_LVDSC2_LVWV_SHIFT 0
-#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
-#define PMC_LVDSC2_LVWIE_MASK 0x20u
-#define PMC_LVDSC2_LVWIE_SHIFT 5
-#define PMC_LVDSC2_LVWACK_MASK 0x40u
-#define PMC_LVDSC2_LVWACK_SHIFT 6
-#define PMC_LVDSC2_LVWF_MASK 0x80u
-#define PMC_LVDSC2_LVWF_SHIFT 7
-/* REGSC Bit Fields */
-#define PMC_REGSC_BGBE_MASK 0x1u
-#define PMC_REGSC_BGBE_SHIFT 0
-#define PMC_REGSC_REGONS_MASK 0x4u
-#define PMC_REGSC_REGONS_SHIFT 2
-#define PMC_REGSC_ACKISO_MASK 0x8u
-#define PMC_REGSC_ACKISO_SHIFT 3
-#define PMC_REGSC_BGEN_MASK 0x10u
-#define PMC_REGSC_BGEN_SHIFT 4
-
-/*!
- * @}
- */ /* end of group PMC_Register_Masks */
-
-
-/* PMC - Peripheral instance base addresses */
-/** Peripheral PMC base address */
-#define PMC_BASE (0x4007D000u)
-/** Peripheral PMC base pointer */
-#define PMC ((PMC_Type *)PMC_BASE)
-#define PMC_BASE_PTR (PMC)
-/** Array initializer of PMC peripheral base pointers */
-#define PMC_BASES { PMC }
-
-/* ----------------------------------------------------------------------------
- -- PMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
- * @{
- */
-
-
-/* PMC - Register instance definitions */
-/* PMC */
-#define PMC_LVDSC1 PMC_LVDSC1_REG(PMC)
-#define PMC_LVDSC2 PMC_LVDSC2_REG(PMC)
-#define PMC_REGSC PMC_REGSC_REG(PMC)
-
-/*!
- * @}
- */ /* end of group PMC_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group PMC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- PORT Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
- * @{
- */
-
-/** PORT - Register Layout Typedef */
-typedef struct {
- __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
- __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
- __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
- uint8_t RESERVED_0[24];
- __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
- uint8_t RESERVED_1[28];
- __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
- __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
- __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
-} PORT_Type, *PORT_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- PORT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
- * @{
- */
-
-
-/* PORT - Register accessors */
-#define PORT_PCR_REG(base,index) ((base)->PCR[index])
-#define PORT_GPCLR_REG(base) ((base)->GPCLR)
-#define PORT_GPCHR_REG(base) ((base)->GPCHR)
-#define PORT_ISFR_REG(base) ((base)->ISFR)
-#define PORT_DFER_REG(base) ((base)->DFER)
-#define PORT_DFCR_REG(base) ((base)->DFCR)
-#define PORT_DFWR_REG(base) ((base)->DFWR)
-
-/*!
- * @}
- */ /* end of group PORT_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- PORT Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PORT_Register_Masks PORT Register Masks
- * @{
- */
-
-/* PCR Bit Fields */
-#define PORT_PCR_PS_MASK 0x1u
-#define PORT_PCR_PS_SHIFT 0
-#define PORT_PCR_PE_MASK 0x2u
-#define PORT_PCR_PE_SHIFT 1
-#define PORT_PCR_SRE_MASK 0x4u
-#define PORT_PCR_SRE_SHIFT 2
-#define PORT_PCR_PFE_MASK 0x10u
-#define PORT_PCR_PFE_SHIFT 4
-#define PORT_PCR_ODE_MASK 0x20u
-#define PORT_PCR_ODE_SHIFT 5
-#define PORT_PCR_DSE_MASK 0x40u
-#define PORT_PCR_DSE_SHIFT 6
-#define PORT_PCR_MUX_MASK 0x700u
-#define PORT_PCR_MUX_SHIFT 8
-#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
-#define PORT_PCR_LK_MASK 0x8000u
-#define PORT_PCR_LK_SHIFT 15
-#define PORT_PCR_IRQC_MASK 0xF0000u
-#define PORT_PCR_IRQC_SHIFT 16
-#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
-#define PORT_PCR_ISF_MASK 0x1000000u
-#define PORT_PCR_ISF_SHIFT 24
-/* GPCLR Bit Fields */
-#define PORT_GPCLR_GPWD_MASK 0xFFFFu
-#define PORT_GPCLR_GPWD_SHIFT 0
-#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
-#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
-#define PORT_GPCLR_GPWE_SHIFT 16
-#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
-/* GPCHR Bit Fields */
-#define PORT_GPCHR_GPWD_MASK 0xFFFFu
-#define PORT_GPCHR_GPWD_SHIFT 0
-#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
-#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
-#define PORT_GPCHR_GPWE_SHIFT 16
-#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
-/* ISFR Bit Fields */
-#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
-#define PORT_ISFR_ISF_SHIFT 0
-#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
-/* DFER Bit Fields */
-#define PORT_DFER_DFE_MASK 0xFFFFFFFFu
-#define PORT_DFER_DFE_SHIFT 0
-#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
-/* DFCR Bit Fields */
-#define PORT_DFCR_CS_MASK 0x1u
-#define PORT_DFCR_CS_SHIFT 0
-/* DFWR Bit Fields */
-#define PORT_DFWR_FILT_MASK 0x1Fu
-#define PORT_DFWR_FILT_SHIFT 0
-#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
-
-/*!
- * @}
- */ /* end of group PORT_Register_Masks */
-
-
-/* PORT - Peripheral instance base addresses */
-/** Peripheral PORTA base address */
-#define PORTA_BASE (0x40049000u)
-/** Peripheral PORTA base pointer */
-#define PORTA ((PORT_Type *)PORTA_BASE)
-#define PORTA_BASE_PTR (PORTA)
-/** Peripheral PORTB base address */
-#define PORTB_BASE (0x4004A000u)
-/** Peripheral PORTB base pointer */
-#define PORTB ((PORT_Type *)PORTB_BASE)
-#define PORTB_BASE_PTR (PORTB)
-/** Peripheral PORTC base address */
-#define PORTC_BASE (0x4004B000u)
-/** Peripheral PORTC base pointer */
-#define PORTC ((PORT_Type *)PORTC_BASE)
-#define PORTC_BASE_PTR (PORTC)
-/** Peripheral PORTD base address */
-#define PORTD_BASE (0x4004C000u)
-/** Peripheral PORTD base pointer */
-#define PORTD ((PORT_Type *)PORTD_BASE)
-#define PORTD_BASE_PTR (PORTD)
-/** Peripheral PORTE base address */
-#define PORTE_BASE (0x4004D000u)
-/** Peripheral PORTE base pointer */
-#define PORTE ((PORT_Type *)PORTE_BASE)
-#define PORTE_BASE_PTR (PORTE)
-/** Array initializer of PORT peripheral base pointers */
-#define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
-
-/* ----------------------------------------------------------------------------
- -- PORT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
- * @{
- */
-
-
-/* PORT - Register instance definitions */
-/* PORTA */
-#define PORTA_PCR0 PORT_PCR_REG(PORTA,0)
-#define PORTA_PCR1 PORT_PCR_REG(PORTA,1)
-#define PORTA_PCR2 PORT_PCR_REG(PORTA,2)
-#define PORTA_PCR3 PORT_PCR_REG(PORTA,3)
-#define PORTA_PCR4 PORT_PCR_REG(PORTA,4)
-#define PORTA_PCR5 PORT_PCR_REG(PORTA,5)
-#define PORTA_PCR6 PORT_PCR_REG(PORTA,6)
-#define PORTA_PCR7 PORT_PCR_REG(PORTA,7)
-#define PORTA_PCR8 PORT_PCR_REG(PORTA,8)
-#define PORTA_PCR9 PORT_PCR_REG(PORTA,9)
-#define PORTA_PCR10 PORT_PCR_REG(PORTA,10)
-#define PORTA_PCR11 PORT_PCR_REG(PORTA,11)
-#define PORTA_PCR12 PORT_PCR_REG(PORTA,12)
-#define PORTA_PCR13 PORT_PCR_REG(PORTA,13)
-#define PORTA_PCR14 PORT_PCR_REG(PORTA,14)
-#define PORTA_PCR15 PORT_PCR_REG(PORTA,15)
-#define PORTA_PCR16 PORT_PCR_REG(PORTA,16)
-#define PORTA_PCR17 PORT_PCR_REG(PORTA,17)
-#define PORTA_PCR18 PORT_PCR_REG(PORTA,18)
-#define PORTA_PCR19 PORT_PCR_REG(PORTA,19)
-#define PORTA_PCR20 PORT_PCR_REG(PORTA,20)
-#define PORTA_PCR21 PORT_PCR_REG(PORTA,21)
-#define PORTA_PCR22 PORT_PCR_REG(PORTA,22)
-#define PORTA_PCR23 PORT_PCR_REG(PORTA,23)
-#define PORTA_PCR24 PORT_PCR_REG(PORTA,24)
-#define PORTA_PCR25 PORT_PCR_REG(PORTA,25)
-#define PORTA_PCR26 PORT_PCR_REG(PORTA,26)
-#define PORTA_PCR27 PORT_PCR_REG(PORTA,27)
-#define PORTA_PCR28 PORT_PCR_REG(PORTA,28)
-#define PORTA_PCR29 PORT_PCR_REG(PORTA,29)
-#define PORTA_PCR30 PORT_PCR_REG(PORTA,30)
-#define PORTA_PCR31 PORT_PCR_REG(PORTA,31)
-#define PORTA_GPCLR PORT_GPCLR_REG(PORTA)
-#define PORTA_GPCHR PORT_GPCHR_REG(PORTA)
-#define PORTA_ISFR PORT_ISFR_REG(PORTA)
-/* PORTB */
-#define PORTB_PCR0 PORT_PCR_REG(PORTB,0)
-#define PORTB_PCR1 PORT_PCR_REG(PORTB,1)
-#define PORTB_PCR2 PORT_PCR_REG(PORTB,2)
-#define PORTB_PCR3 PORT_PCR_REG(PORTB,3)
-#define PORTB_PCR4 PORT_PCR_REG(PORTB,4)
-#define PORTB_PCR5 PORT_PCR_REG(PORTB,5)
-#define PORTB_PCR6 PORT_PCR_REG(PORTB,6)
-#define PORTB_PCR7 PORT_PCR_REG(PORTB,7)
-#define PORTB_PCR8 PORT_PCR_REG(PORTB,8)
-#define PORTB_PCR9 PORT_PCR_REG(PORTB,9)
-#define PORTB_PCR10 PORT_PCR_REG(PORTB,10)
-#define PORTB_PCR11 PORT_PCR_REG(PORTB,11)
-#define PORTB_PCR12 PORT_PCR_REG(PORTB,12)
-#define PORTB_PCR13 PORT_PCR_REG(PORTB,13)
-#define PORTB_PCR14 PORT_PCR_REG(PORTB,14)
-#define PORTB_PCR15 PORT_PCR_REG(PORTB,15)
-#define PORTB_PCR16 PORT_PCR_REG(PORTB,16)
-#define PORTB_PCR17 PORT_PCR_REG(PORTB,17)
-#define PORTB_PCR18 PORT_PCR_REG(PORTB,18)
-#define PORTB_PCR19 PORT_PCR_REG(PORTB,19)
-#define PORTB_PCR20 PORT_PCR_REG(PORTB,20)
-#define PORTB_PCR21 PORT_PCR_REG(PORTB,21)
-#define PORTB_PCR22 PORT_PCR_REG(PORTB,22)
-#define PORTB_PCR23 PORT_PCR_REG(PORTB,23)
-#define PORTB_PCR24 PORT_PCR_REG(PORTB,24)
-#define PORTB_PCR25 PORT_PCR_REG(PORTB,25)
-#define PORTB_PCR26 PORT_PCR_REG(PORTB,26)
-#define PORTB_PCR27 PORT_PCR_REG(PORTB,27)
-#define PORTB_PCR28 PORT_PCR_REG(PORTB,28)
-#define PORTB_PCR29 PORT_PCR_REG(PORTB,29)
-#define PORTB_PCR30 PORT_PCR_REG(PORTB,30)
-#define PORTB_PCR31 PORT_PCR_REG(PORTB,31)
-#define PORTB_GPCLR PORT_GPCLR_REG(PORTB)
-#define PORTB_GPCHR PORT_GPCHR_REG(PORTB)
-#define PORTB_ISFR PORT_ISFR_REG(PORTB)
-/* PORTC */
-#define PORTC_PCR0 PORT_PCR_REG(PORTC,0)
-#define PORTC_PCR1 PORT_PCR_REG(PORTC,1)
-#define PORTC_PCR2 PORT_PCR_REG(PORTC,2)
-#define PORTC_PCR3 PORT_PCR_REG(PORTC,3)
-#define PORTC_PCR4 PORT_PCR_REG(PORTC,4)
-#define PORTC_PCR5 PORT_PCR_REG(PORTC,5)
-#define PORTC_PCR6 PORT_PCR_REG(PORTC,6)
-#define PORTC_PCR7 PORT_PCR_REG(PORTC,7)
-#define PORTC_PCR8 PORT_PCR_REG(PORTC,8)
-#define PORTC_PCR9 PORT_PCR_REG(PORTC,9)
-#define PORTC_PCR10 PORT_PCR_REG(PORTC,10)
-#define PORTC_PCR11 PORT_PCR_REG(PORTC,11)
-#define PORTC_PCR12 PORT_PCR_REG(PORTC,12)
-#define PORTC_PCR13 PORT_PCR_REG(PORTC,13)
-#define PORTC_PCR14 PORT_PCR_REG(PORTC,14)
-#define PORTC_PCR15 PORT_PCR_REG(PORTC,15)
-#define PORTC_PCR16 PORT_PCR_REG(PORTC,16)
-#define PORTC_PCR17 PORT_PCR_REG(PORTC,17)
-#define PORTC_PCR18 PORT_PCR_REG(PORTC,18)
-#define PORTC_PCR19 PORT_PCR_REG(PORTC,19)
-#define PORTC_PCR20 PORT_PCR_REG(PORTC,20)
-#define PORTC_PCR21 PORT_PCR_REG(PORTC,21)
-#define PORTC_PCR22 PORT_PCR_REG(PORTC,22)
-#define PORTC_PCR23 PORT_PCR_REG(PORTC,23)
-#define PORTC_PCR24 PORT_PCR_REG(PORTC,24)
-#define PORTC_PCR25 PORT_PCR_REG(PORTC,25)
-#define PORTC_PCR26 PORT_PCR_REG(PORTC,26)
-#define PORTC_PCR27 PORT_PCR_REG(PORTC,27)
-#define PORTC_PCR28 PORT_PCR_REG(PORTC,28)
-#define PORTC_PCR29 PORT_PCR_REG(PORTC,29)
-#define PORTC_PCR30 PORT_PCR_REG(PORTC,30)
-#define PORTC_PCR31 PORT_PCR_REG(PORTC,31)
-#define PORTC_GPCLR PORT_GPCLR_REG(PORTC)
-#define PORTC_GPCHR PORT_GPCHR_REG(PORTC)
-#define PORTC_ISFR PORT_ISFR_REG(PORTC)
-/* PORTD */
-#define PORTD_PCR0 PORT_PCR_REG(PORTD,0)
-#define PORTD_PCR1 PORT_PCR_REG(PORTD,1)
-#define PORTD_PCR2 PORT_PCR_REG(PORTD,2)
-#define PORTD_PCR3 PORT_PCR_REG(PORTD,3)
-#define PORTD_PCR4 PORT_PCR_REG(PORTD,4)
-#define PORTD_PCR5 PORT_PCR_REG(PORTD,5)
-#define PORTD_PCR6 PORT_PCR_REG(PORTD,6)
-#define PORTD_PCR7 PORT_PCR_REG(PORTD,7)
-#define PORTD_PCR8 PORT_PCR_REG(PORTD,8)
-#define PORTD_PCR9 PORT_PCR_REG(PORTD,9)
-#define PORTD_PCR10 PORT_PCR_REG(PORTD,10)
-#define PORTD_PCR11 PORT_PCR_REG(PORTD,11)
-#define PORTD_PCR12 PORT_PCR_REG(PORTD,12)
-#define PORTD_PCR13 PORT_PCR_REG(PORTD,13)
-#define PORTD_PCR14 PORT_PCR_REG(PORTD,14)
-#define PORTD_PCR15 PORT_PCR_REG(PORTD,15)
-#define PORTD_PCR16 PORT_PCR_REG(PORTD,16)
-#define PORTD_PCR17 PORT_PCR_REG(PORTD,17)
-#define PORTD_PCR18 PORT_PCR_REG(PORTD,18)
-#define PORTD_PCR19 PORT_PCR_REG(PORTD,19)
-#define PORTD_PCR20 PORT_PCR_REG(PORTD,20)
-#define PORTD_PCR21 PORT_PCR_REG(PORTD,21)
-#define PORTD_PCR22 PORT_PCR_REG(PORTD,22)
-#define PORTD_PCR23 PORT_PCR_REG(PORTD,23)
-#define PORTD_PCR24 PORT_PCR_REG(PORTD,24)
-#define PORTD_PCR25 PORT_PCR_REG(PORTD,25)
-#define PORTD_PCR26 PORT_PCR_REG(PORTD,26)
-#define PORTD_PCR27 PORT_PCR_REG(PORTD,27)
-#define PORTD_PCR28 PORT_PCR_REG(PORTD,28)
-#define PORTD_PCR29 PORT_PCR_REG(PORTD,29)
-#define PORTD_PCR30 PORT_PCR_REG(PORTD,30)
-#define PORTD_PCR31 PORT_PCR_REG(PORTD,31)
-#define PORTD_GPCLR PORT_GPCLR_REG(PORTD)
-#define PORTD_GPCHR PORT_GPCHR_REG(PORTD)
-#define PORTD_ISFR PORT_ISFR_REG(PORTD)
-#define PORTD_DFER PORT_DFER_REG(PORTD)
-#define PORTD_DFCR PORT_DFCR_REG(PORTD)
-#define PORTD_DFWR PORT_DFWR_REG(PORTD)
-/* PORTE */
-#define PORTE_PCR0 PORT_PCR_REG(PORTE,0)
-#define PORTE_PCR1 PORT_PCR_REG(PORTE,1)
-#define PORTE_PCR2 PORT_PCR_REG(PORTE,2)
-#define PORTE_PCR3 PORT_PCR_REG(PORTE,3)
-#define PORTE_PCR4 PORT_PCR_REG(PORTE,4)
-#define PORTE_PCR5 PORT_PCR_REG(PORTE,5)
-#define PORTE_PCR6 PORT_PCR_REG(PORTE,6)
-#define PORTE_PCR7 PORT_PCR_REG(PORTE,7)
-#define PORTE_PCR8 PORT_PCR_REG(PORTE,8)
-#define PORTE_PCR9 PORT_PCR_REG(PORTE,9)
-#define PORTE_PCR10 PORT_PCR_REG(PORTE,10)
-#define PORTE_PCR11 PORT_PCR_REG(PORTE,11)
-#define PORTE_PCR12 PORT_PCR_REG(PORTE,12)
-#define PORTE_PCR13 PORT_PCR_REG(PORTE,13)
-#define PORTE_PCR14 PORT_PCR_REG(PORTE,14)
-#define PORTE_PCR15 PORT_PCR_REG(PORTE,15)
-#define PORTE_PCR16 PORT_PCR_REG(PORTE,16)
-#define PORTE_PCR17 PORT_PCR_REG(PORTE,17)
-#define PORTE_PCR18 PORT_PCR_REG(PORTE,18)
-#define PORTE_PCR19 PORT_PCR_REG(PORTE,19)
-#define PORTE_PCR20 PORT_PCR_REG(PORTE,20)
-#define PORTE_PCR21 PORT_PCR_REG(PORTE,21)
-#define PORTE_PCR22 PORT_PCR_REG(PORTE,22)
-#define PORTE_PCR23 PORT_PCR_REG(PORTE,23)
-#define PORTE_PCR24 PORT_PCR_REG(PORTE,24)
-#define PORTE_PCR25 PORT_PCR_REG(PORTE,25)
-#define PORTE_PCR26 PORT_PCR_REG(PORTE,26)
-#define PORTE_PCR27 PORT_PCR_REG(PORTE,27)
-#define PORTE_PCR28 PORT_PCR_REG(PORTE,28)
-#define PORTE_PCR29 PORT_PCR_REG(PORTE,29)
-#define PORTE_PCR30 PORT_PCR_REG(PORTE,30)
-#define PORTE_PCR31 PORT_PCR_REG(PORTE,31)
-#define PORTE_GPCLR PORT_GPCLR_REG(PORTE)
-#define PORTE_GPCHR PORT_GPCHR_REG(PORTE)
-#define PORTE_ISFR PORT_ISFR_REG(PORTE)
-
-/* PORT - Register array accessors */
-#define PORTA_PCR(index) PORT_PCR_REG(PORTA,index)
-#define PORTB_PCR(index) PORT_PCR_REG(PORTB,index)
-#define PORTC_PCR(index) PORT_PCR_REG(PORTC,index)
-#define PORTD_PCR(index) PORT_PCR_REG(PORTD,index)
-#define PORTE_PCR(index) PORT_PCR_REG(PORTE,index)
-
-/*!
- * @}
- */ /* end of group PORT_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group PORT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- RCM Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
- * @{
- */
-
-/** RCM - Register Layout Typedef */
-typedef struct {
- __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
- __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
- uint8_t RESERVED_0[2];
- __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
- __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
- uint8_t RESERVED_1[1];
- __I uint8_t MR; /**< Mode Register, offset: 0x7 */
-} RCM_Type, *RCM_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- RCM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
- * @{
- */
-
-
-/* RCM - Register accessors */
-#define RCM_SRS0_REG(base) ((base)->SRS0)
-#define RCM_SRS1_REG(base) ((base)->SRS1)
-#define RCM_RPFC_REG(base) ((base)->RPFC)
-#define RCM_RPFW_REG(base) ((base)->RPFW)
-#define RCM_MR_REG(base) ((base)->MR)
-
-/*!
- * @}
- */ /* end of group RCM_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- RCM Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RCM_Register_Masks RCM Register Masks
- * @{
- */
-
-/* SRS0 Bit Fields */
-#define RCM_SRS0_WAKEUP_MASK 0x1u
-#define RCM_SRS0_WAKEUP_SHIFT 0
-#define RCM_SRS0_LVD_MASK 0x2u
-#define RCM_SRS0_LVD_SHIFT 1
-#define RCM_SRS0_LOC_MASK 0x4u
-#define RCM_SRS0_LOC_SHIFT 2
-#define RCM_SRS0_LOL_MASK 0x8u
-#define RCM_SRS0_LOL_SHIFT 3
-#define RCM_SRS0_WDOG_MASK 0x20u
-#define RCM_SRS0_WDOG_SHIFT 5
-#define RCM_SRS0_PIN_MASK 0x40u
-#define RCM_SRS0_PIN_SHIFT 6
-#define RCM_SRS0_POR_MASK 0x80u
-#define RCM_SRS0_POR_SHIFT 7
-/* SRS1 Bit Fields */
-#define RCM_SRS1_JTAG_MASK 0x1u
-#define RCM_SRS1_JTAG_SHIFT 0
-#define RCM_SRS1_LOCKUP_MASK 0x2u
-#define RCM_SRS1_LOCKUP_SHIFT 1
-#define RCM_SRS1_SW_MASK 0x4u
-#define RCM_SRS1_SW_SHIFT 2
-#define RCM_SRS1_MDM_AP_MASK 0x8u
-#define RCM_SRS1_MDM_AP_SHIFT 3
-#define RCM_SRS1_EZPT_MASK 0x10u
-#define RCM_SRS1_EZPT_SHIFT 4
-#define RCM_SRS1_SACKERR_MASK 0x20u
-#define RCM_SRS1_SACKERR_SHIFT 5
-/* RPFC Bit Fields */
-#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
-#define RCM_RPFC_RSTFLTSRW_SHIFT 0
-#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
-#define RCM_RPFC_RSTFLTSS_MASK 0x4u
-#define RCM_RPFC_RSTFLTSS_SHIFT 2
-/* RPFW Bit Fields */
-#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
-#define RCM_RPFW_RSTFLTSEL_SHIFT 0
-#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
-/* MR Bit Fields */
-#define RCM_MR_EZP_MS_MASK 0x2u
-#define RCM_MR_EZP_MS_SHIFT 1
-
-/*!
- * @}
- */ /* end of group RCM_Register_Masks */
-
-
-/* RCM - Peripheral instance base addresses */
-/** Peripheral RCM base address */
-#define RCM_BASE (0x4007F000u)
-/** Peripheral RCM base pointer */
-#define RCM ((RCM_Type *)RCM_BASE)
-#define RCM_BASE_PTR (RCM)
-/** Array initializer of RCM peripheral base pointers */
-#define RCM_BASES { RCM }
-
-/* ----------------------------------------------------------------------------
- -- RCM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
- * @{
- */
-
-
-/* RCM - Register instance definitions */
-/* RCM */
-#define RCM_SRS0 RCM_SRS0_REG(RCM)
-#define RCM_SRS1 RCM_SRS1_REG(RCM)
-#define RCM_RPFC RCM_RPFC_REG(RCM)
-#define RCM_RPFW RCM_RPFW_REG(RCM)
-#define RCM_MR RCM_MR_REG(RCM)
-
-/*!
- * @}
- */ /* end of group RCM_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group RCM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- RFSYS Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
- * @{
- */
-
-/** RFSYS - Register Layout Typedef */
-typedef struct {
- __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
-} RFSYS_Type, *RFSYS_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- RFSYS - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
- * @{
- */
-
-
-/* RFSYS - Register accessors */
-#define RFSYS_REG_REG(base,index) ((base)->REG[index])
-
-/*!
- * @}
- */ /* end of group RFSYS_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- RFSYS Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
- * @{
- */
-
-/* REG Bit Fields */
-#define RFSYS_REG_LL_MASK 0xFFu
-#define RFSYS_REG_LL_SHIFT 0
-#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
-#define RFSYS_REG_LH_MASK 0xFF00u
-#define RFSYS_REG_LH_SHIFT 8
-#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
-#define RFSYS_REG_HL_MASK 0xFF0000u
-#define RFSYS_REG_HL_SHIFT 16
-#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
-#define RFSYS_REG_HH_MASK 0xFF000000u
-#define RFSYS_REG_HH_SHIFT 24
-#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
-
-/*!
- * @}
- */ /* end of group RFSYS_Register_Masks */
-
-
-/* RFSYS - Peripheral instance base addresses */
-/** Peripheral RFSYS base address */
-#define RFSYS_BASE (0x40041000u)
-/** Peripheral RFSYS base pointer */
-#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
-#define RFSYS_BASE_PTR (RFSYS)
-/** Array initializer of RFSYS peripheral base pointers */
-#define RFSYS_BASES { RFSYS }
-
-/* ----------------------------------------------------------------------------
- -- RFSYS - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
- * @{
- */
-
-
-/* RFSYS - Register instance definitions */
-/* RFSYS */
-#define RFSYS_REG0 RFSYS_REG_REG(RFSYS,0)
-#define RFSYS_REG1 RFSYS_REG_REG(RFSYS,1)
-#define RFSYS_REG2 RFSYS_REG_REG(RFSYS,2)
-#define RFSYS_REG3 RFSYS_REG_REG(RFSYS,3)
-#define RFSYS_REG4 RFSYS_REG_REG(RFSYS,4)
-#define RFSYS_REG5 RFSYS_REG_REG(RFSYS,5)
-#define RFSYS_REG6 RFSYS_REG_REG(RFSYS,6)
-#define RFSYS_REG7 RFSYS_REG_REG(RFSYS,7)
-
-/* RFSYS - Register array accessors */
-#define RFSYS_REG(index) RFSYS_REG_REG(RFSYS,index)
-
-/*!
- * @}
- */ /* end of group RFSYS_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group RFSYS_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- RFVBAT Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
- * @{
- */
-
-/** RFVBAT - Register Layout Typedef */
-typedef struct {
- __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
-} RFVBAT_Type, *RFVBAT_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- RFVBAT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
- * @{
- */
-
-
-/* RFVBAT - Register accessors */
-#define RFVBAT_REG_REG(base,index) ((base)->REG[index])
-
-/*!
- * @}
- */ /* end of group RFVBAT_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- RFVBAT Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
- * @{
- */
-
-/* REG Bit Fields */
-#define RFVBAT_REG_LL_MASK 0xFFu
-#define RFVBAT_REG_LL_SHIFT 0
-#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
-#define RFVBAT_REG_LH_MASK 0xFF00u
-#define RFVBAT_REG_LH_SHIFT 8
-#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
-#define RFVBAT_REG_HL_MASK 0xFF0000u
-#define RFVBAT_REG_HL_SHIFT 16
-#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
-#define RFVBAT_REG_HH_MASK 0xFF000000u
-#define RFVBAT_REG_HH_SHIFT 24
-#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
-
-/*!
- * @}
- */ /* end of group RFVBAT_Register_Masks */
-
-
-/* RFVBAT - Peripheral instance base addresses */
-/** Peripheral RFVBAT base address */
-#define RFVBAT_BASE (0x4003E000u)
-/** Peripheral RFVBAT base pointer */
-#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
-#define RFVBAT_BASE_PTR (RFVBAT)
-/** Array initializer of RFVBAT peripheral base pointers */
-#define RFVBAT_BASES { RFVBAT }
-
-/* ----------------------------------------------------------------------------
- -- RFVBAT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
- * @{
- */
-
-
-/* RFVBAT - Register instance definitions */
-/* RFVBAT */
-#define RFVBAT_REG0 RFVBAT_REG_REG(RFVBAT,0)
-#define RFVBAT_REG1 RFVBAT_REG_REG(RFVBAT,1)
-#define RFVBAT_REG2 RFVBAT_REG_REG(RFVBAT,2)
-#define RFVBAT_REG3 RFVBAT_REG_REG(RFVBAT,3)
-#define RFVBAT_REG4 RFVBAT_REG_REG(RFVBAT,4)
-#define RFVBAT_REG5 RFVBAT_REG_REG(RFVBAT,5)
-#define RFVBAT_REG6 RFVBAT_REG_REG(RFVBAT,6)
-#define RFVBAT_REG7 RFVBAT_REG_REG(RFVBAT,7)
-
-/* RFVBAT - Register array accessors */
-#define RFVBAT_REG(index) RFVBAT_REG_REG(RFVBAT,index)
-
-/*!
- * @}
- */ /* end of group RFVBAT_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group RFVBAT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- RNG Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
- * @{
- */
-
-/** RNG - Register Layout Typedef */
-typedef struct {
- __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */
- __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */
- __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */
- __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */
-} RNG_Type, *RNG_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- RNG - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
- * @{
- */
-
-
-/* RNG - Register accessors */
-#define RNG_CR_REG(base) ((base)->CR)
-#define RNG_SR_REG(base) ((base)->SR)
-#define RNG_ER_REG(base) ((base)->ER)
-#define RNG_OR_REG(base) ((base)->OR)
-
-/*!
- * @}
- */ /* end of group RNG_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- RNG Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RNG_Register_Masks RNG Register Masks
- * @{
- */
-
-/* CR Bit Fields */
-#define RNG_CR_GO_MASK 0x1u
-#define RNG_CR_GO_SHIFT 0
-#define RNG_CR_HA_MASK 0x2u
-#define RNG_CR_HA_SHIFT 1
-#define RNG_CR_INTM_MASK 0x4u
-#define RNG_CR_INTM_SHIFT 2
-#define RNG_CR_CLRI_MASK 0x8u
-#define RNG_CR_CLRI_SHIFT 3
-#define RNG_CR_SLP_MASK 0x10u
-#define RNG_CR_SLP_SHIFT 4
-/* SR Bit Fields */
-#define RNG_SR_SECV_MASK 0x1u
-#define RNG_SR_SECV_SHIFT 0
-#define RNG_SR_LRS_MASK 0x2u
-#define RNG_SR_LRS_SHIFT 1
-#define RNG_SR_ORU_MASK 0x4u
-#define RNG_SR_ORU_SHIFT 2
-#define RNG_SR_ERRI_MASK 0x8u
-#define RNG_SR_ERRI_SHIFT 3
-#define RNG_SR_SLP_MASK 0x10u
-#define RNG_SR_SLP_SHIFT 4
-#define RNG_SR_OREG_LVL_MASK 0xFF00u
-#define RNG_SR_OREG_LVL_SHIFT 8
-#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_LVL_SHIFT))&RNG_SR_OREG_LVL_MASK)
-#define RNG_SR_OREG_SIZE_MASK 0xFF0000u
-#define RNG_SR_OREG_SIZE_SHIFT 16
-#define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_SIZE_SHIFT))&RNG_SR_OREG_SIZE_MASK)
-/* ER Bit Fields */
-#define RNG_ER_EXT_ENT_MASK 0xFFFFFFFFu
-#define RNG_ER_EXT_ENT_SHIFT 0
-#define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x))<<RNG_ER_EXT_ENT_SHIFT))&RNG_ER_EXT_ENT_MASK)
-/* OR Bit Fields */
-#define RNG_OR_RANDOUT_MASK 0xFFFFFFFFu
-#define RNG_OR_RANDOUT_SHIFT 0
-#define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x))<<RNG_OR_RANDOUT_SHIFT))&RNG_OR_RANDOUT_MASK)
-
-/*!
- * @}
- */ /* end of group RNG_Register_Masks */
-
-
-/* RNG - Peripheral instance base addresses */
-/** Peripheral RNG base address */
-#define RNG_BASE (0x40029000u)
-/** Peripheral RNG base pointer */
-#define RNG ((RNG_Type *)RNG_BASE)
-#define RNG_BASE_PTR (RNG)
-/** Array initializer of RNG peripheral base pointers */
-#define RNG_BASES { RNG }
-
-/* ----------------------------------------------------------------------------
- -- RNG - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
- * @{
- */
-
-
-/* RNG - Register instance definitions */
-/* RNG */
-#define RNG_CR RNG_CR_REG(RNG)
-#define RNG_SR RNG_SR_REG(RNG)
-#define RNG_ER RNG_ER_REG(RNG)
-#define RNG_OR RNG_OR_REG(RNG)
-
-/*!
- * @}
- */ /* end of group RNG_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group RNG_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- RTC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
- * @{
- */
-
-/** RTC - Register Layout Typedef */
-typedef struct {
- __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
- __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
- __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
- __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
- __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
- __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
- __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
- __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
- uint8_t RESERVED_0[2016];
- __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
- __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
-} RTC_Type, *RTC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- RTC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
- * @{
- */
-
-
-/* RTC - Register accessors */
-#define RTC_TSR_REG(base) ((base)->TSR)
-#define RTC_TPR_REG(base) ((base)->TPR)
-#define RTC_TAR_REG(base) ((base)->TAR)
-#define RTC_TCR_REG(base) ((base)->TCR)
-#define RTC_CR_REG(base) ((base)->CR)
-#define RTC_SR_REG(base) ((base)->SR)
-#define RTC_LR_REG(base) ((base)->LR)
-#define RTC_IER_REG(base) ((base)->IER)
-#define RTC_WAR_REG(base) ((base)->WAR)
-#define RTC_RAR_REG(base) ((base)->RAR)
-
-/*!
- * @}
- */ /* end of group RTC_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- RTC Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RTC_Register_Masks RTC Register Masks
- * @{
- */
-
-/* TSR Bit Fields */
-#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
-#define RTC_TSR_TSR_SHIFT 0
-#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
-/* TPR Bit Fields */
-#define RTC_TPR_TPR_MASK 0xFFFFu
-#define RTC_TPR_TPR_SHIFT 0
-#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
-/* TAR Bit Fields */
-#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
-#define RTC_TAR_TAR_SHIFT 0
-#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
-/* TCR Bit Fields */
-#define RTC_TCR_TCR_MASK 0xFFu
-#define RTC_TCR_TCR_SHIFT 0
-#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
-#define RTC_TCR_CIR_MASK 0xFF00u
-#define RTC_TCR_CIR_SHIFT 8
-#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
-#define RTC_TCR_TCV_MASK 0xFF0000u
-#define RTC_TCR_TCV_SHIFT 16
-#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
-#define RTC_TCR_CIC_MASK 0xFF000000u
-#define RTC_TCR_CIC_SHIFT 24
-#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
-/* CR Bit Fields */
-#define RTC_CR_SWR_MASK 0x1u
-#define RTC_CR_SWR_SHIFT 0
-#define RTC_CR_WPE_MASK 0x2u
-#define RTC_CR_WPE_SHIFT 1
-#define RTC_CR_SUP_MASK 0x4u
-#define RTC_CR_SUP_SHIFT 2
-#define RTC_CR_UM_MASK 0x8u
-#define RTC_CR_UM_SHIFT 3
-#define RTC_CR_WPS_MASK 0x10u
-#define RTC_CR_WPS_SHIFT 4
-#define RTC_CR_OSCE_MASK 0x100u
-#define RTC_CR_OSCE_SHIFT 8
-#define RTC_CR_CLKO_MASK 0x200u
-#define RTC_CR_CLKO_SHIFT 9
-#define RTC_CR_SC16P_MASK 0x400u
-#define RTC_CR_SC16P_SHIFT 10
-#define RTC_CR_SC8P_MASK 0x800u
-#define RTC_CR_SC8P_SHIFT 11
-#define RTC_CR_SC4P_MASK 0x1000u
-#define RTC_CR_SC4P_SHIFT 12
-#define RTC_CR_SC2P_MASK 0x2000u
-#define RTC_CR_SC2P_SHIFT 13
-/* SR Bit Fields */
-#define RTC_SR_TIF_MASK 0x1u
-#define RTC_SR_TIF_SHIFT 0
-#define RTC_SR_TOF_MASK 0x2u
-#define RTC_SR_TOF_SHIFT 1
-#define RTC_SR_TAF_MASK 0x4u
-#define RTC_SR_TAF_SHIFT 2
-#define RTC_SR_TCE_MASK 0x10u
-#define RTC_SR_TCE_SHIFT 4
-/* LR Bit Fields */
-#define RTC_LR_TCL_MASK 0x8u
-#define RTC_LR_TCL_SHIFT 3
-#define RTC_LR_CRL_MASK 0x10u
-#define RTC_LR_CRL_SHIFT 4
-#define RTC_LR_SRL_MASK 0x20u
-#define RTC_LR_SRL_SHIFT 5
-#define RTC_LR_LRL_MASK 0x40u
-#define RTC_LR_LRL_SHIFT 6
-/* IER Bit Fields */
-#define RTC_IER_TIIE_MASK 0x1u
-#define RTC_IER_TIIE_SHIFT 0
-#define RTC_IER_TOIE_MASK 0x2u
-#define RTC_IER_TOIE_SHIFT 1
-#define RTC_IER_TAIE_MASK 0x4u
-#define RTC_IER_TAIE_SHIFT 2
-#define RTC_IER_TSIE_MASK 0x10u
-#define RTC_IER_TSIE_SHIFT 4
-#define RTC_IER_WPON_MASK 0x80u
-#define RTC_IER_WPON_SHIFT 7
-/* WAR Bit Fields */
-#define RTC_WAR_TSRW_MASK 0x1u
-#define RTC_WAR_TSRW_SHIFT 0
-#define RTC_WAR_TPRW_MASK 0x2u
-#define RTC_WAR_TPRW_SHIFT 1
-#define RTC_WAR_TARW_MASK 0x4u
-#define RTC_WAR_TARW_SHIFT 2
-#define RTC_WAR_TCRW_MASK 0x8u
-#define RTC_WAR_TCRW_SHIFT 3
-#define RTC_WAR_CRW_MASK 0x10u
-#define RTC_WAR_CRW_SHIFT 4
-#define RTC_WAR_SRW_MASK 0x20u
-#define RTC_WAR_SRW_SHIFT 5
-#define RTC_WAR_LRW_MASK 0x40u
-#define RTC_WAR_LRW_SHIFT 6
-#define RTC_WAR_IERW_MASK 0x80u
-#define RTC_WAR_IERW_SHIFT 7
-/* RAR Bit Fields */
-#define RTC_RAR_TSRR_MASK 0x1u
-#define RTC_RAR_TSRR_SHIFT 0
-#define RTC_RAR_TPRR_MASK 0x2u
-#define RTC_RAR_TPRR_SHIFT 1
-#define RTC_RAR_TARR_MASK 0x4u
-#define RTC_RAR_TARR_SHIFT 2
-#define RTC_RAR_TCRR_MASK 0x8u
-#define RTC_RAR_TCRR_SHIFT 3
-#define RTC_RAR_CRR_MASK 0x10u
-#define RTC_RAR_CRR_SHIFT 4
-#define RTC_RAR_SRR_MASK 0x20u
-#define RTC_RAR_SRR_SHIFT 5
-#define RTC_RAR_LRR_MASK 0x40u
-#define RTC_RAR_LRR_SHIFT 6
-#define RTC_RAR_IERR_MASK 0x80u
-#define RTC_RAR_IERR_SHIFT 7
-
-/*!
- * @}
- */ /* end of group RTC_Register_Masks */
-
-
-/* RTC - Peripheral instance base addresses */
-/** Peripheral RTC base address */
-#define RTC_BASE (0x4003D000u)
-/** Peripheral RTC base pointer */
-#define RTC ((RTC_Type *)RTC_BASE)
-#define RTC_BASE_PTR (RTC)
-/** Array initializer of RTC peripheral base pointers */
-#define RTC_BASES { RTC }
-
-/* ----------------------------------------------------------------------------
- -- RTC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
- * @{
- */
-
-
-/* RTC - Register instance definitions */
-/* RTC */
-#define RTC_TSR RTC_TSR_REG(RTC)
-#define RTC_TPR RTC_TPR_REG(RTC)
-#define RTC_TAR RTC_TAR_REG(RTC)
-#define RTC_TCR RTC_TCR_REG(RTC)
-#define RTC_CR RTC_CR_REG(RTC)
-#define RTC_SR RTC_SR_REG(RTC)
-#define RTC_LR RTC_LR_REG(RTC)
-#define RTC_IER RTC_IER_REG(RTC)
-#define RTC_WAR RTC_WAR_REG(RTC)
-#define RTC_RAR RTC_RAR_REG(RTC)
-
-/*!
- * @}
- */ /* end of group RTC_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group RTC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- SDHC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
- * @{
- */
-
-/** SDHC - Register Layout Typedef */
-typedef struct {
- __IO uint32_t DSADDR; /**< DMA System Address register, offset: 0x0 */
- __IO uint32_t BLKATTR; /**< Block Attributes register, offset: 0x4 */
- __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x8 */
- __IO uint32_t XFERTYP; /**< Transfer Type register, offset: 0xC */
- __I uint32_t CMDRSP[4]; /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
- __IO uint32_t DATPORT; /**< Buffer Data Port register, offset: 0x20 */
- __I uint32_t PRSSTAT; /**< Present State register, offset: 0x24 */
- __IO uint32_t PROCTL; /**< Protocol Control register, offset: 0x28 */
- __IO uint32_t SYSCTL; /**< System Control register, offset: 0x2C */
- __IO uint32_t IRQSTAT; /**< Interrupt Status register, offset: 0x30 */
- __IO uint32_t IRQSTATEN; /**< Interrupt Status Enable register, offset: 0x34 */
- __IO uint32_t IRQSIGEN; /**< Interrupt Signal Enable register, offset: 0x38 */
- __I uint32_t AC12ERR; /**< Auto CMD12 Error Status Register, offset: 0x3C */
- __I uint32_t HTCAPBLT; /**< Host Controller Capabilities, offset: 0x40 */
- __IO uint32_t WML; /**< Watermark Level Register, offset: 0x44 */
- uint8_t RESERVED_0[8];
- __O uint32_t FEVT; /**< Force Event register, offset: 0x50 */
- __I uint32_t ADMAES; /**< ADMA Error Status register, offset: 0x54 */
- __IO uint32_t ADSADDR; /**< ADMA System Addressregister, offset: 0x58 */
- uint8_t RESERVED_1[100];
- __IO uint32_t VENDOR; /**< Vendor Specific register, offset: 0xC0 */
- __IO uint32_t MMCBOOT; /**< MMC Boot register, offset: 0xC4 */
- uint8_t RESERVED_2[52];
- __I uint32_t HOSTVER; /**< Host Controller Version, offset: 0xFC */
-} SDHC_Type, *SDHC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- SDHC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
- * @{
- */
-
-
-/* SDHC - Register accessors */
-#define SDHC_DSADDR_REG(base) ((base)->DSADDR)
-#define SDHC_BLKATTR_REG(base) ((base)->BLKATTR)
-#define SDHC_CMDARG_REG(base) ((base)->CMDARG)
-#define SDHC_XFERTYP_REG(base) ((base)->XFERTYP)
-#define SDHC_CMDRSP_REG(base,index) ((base)->CMDRSP[index])
-#define SDHC_DATPORT_REG(base) ((base)->DATPORT)
-#define SDHC_PRSSTAT_REG(base) ((base)->PRSSTAT)
-#define SDHC_PROCTL_REG(base) ((base)->PROCTL)
-#define SDHC_SYSCTL_REG(base) ((base)->SYSCTL)
-#define SDHC_IRQSTAT_REG(base) ((base)->IRQSTAT)
-#define SDHC_IRQSTATEN_REG(base) ((base)->IRQSTATEN)
-#define SDHC_IRQSIGEN_REG(base) ((base)->IRQSIGEN)
-#define SDHC_AC12ERR_REG(base) ((base)->AC12ERR)
-#define SDHC_HTCAPBLT_REG(base) ((base)->HTCAPBLT)
-#define SDHC_WML_REG(base) ((base)->WML)
-#define SDHC_FEVT_REG(base) ((base)->FEVT)
-#define SDHC_ADMAES_REG(base) ((base)->ADMAES)
-#define SDHC_ADSADDR_REG(base) ((base)->ADSADDR)
-#define SDHC_VENDOR_REG(base) ((base)->VENDOR)
-#define SDHC_MMCBOOT_REG(base) ((base)->MMCBOOT)
-#define SDHC_HOSTVER_REG(base) ((base)->HOSTVER)
-
-/*!
- * @}
- */ /* end of group SDHC_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- SDHC Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SDHC_Register_Masks SDHC Register Masks
- * @{
- */
-
-/* DSADDR Bit Fields */
-#define SDHC_DSADDR_DSADDR_MASK 0xFFFFFFFCu
-#define SDHC_DSADDR_DSADDR_SHIFT 2
-#define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DSADDR_DSADDR_SHIFT))&SDHC_DSADDR_DSADDR_MASK)
-/* BLKATTR Bit Fields */
-#define SDHC_BLKATTR_BLKSIZE_MASK 0x1FFFu
-#define SDHC_BLKATTR_BLKSIZE_SHIFT 0
-#define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKSIZE_SHIFT))&SDHC_BLKATTR_BLKSIZE_MASK)
-#define SDHC_BLKATTR_BLKCNT_MASK 0xFFFF0000u
-#define SDHC_BLKATTR_BLKCNT_SHIFT 16
-#define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKCNT_SHIFT))&SDHC_BLKATTR_BLKCNT_MASK)
-/* CMDARG Bit Fields */
-#define SDHC_CMDARG_CMDARG_MASK 0xFFFFFFFFu
-#define SDHC_CMDARG_CMDARG_SHIFT 0
-#define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDARG_CMDARG_SHIFT))&SDHC_CMDARG_CMDARG_MASK)
-/* XFERTYP Bit Fields */
-#define SDHC_XFERTYP_DMAEN_MASK 0x1u
-#define SDHC_XFERTYP_DMAEN_SHIFT 0
-#define SDHC_XFERTYP_BCEN_MASK 0x2u
-#define SDHC_XFERTYP_BCEN_SHIFT 1
-#define SDHC_XFERTYP_AC12EN_MASK 0x4u
-#define SDHC_XFERTYP_AC12EN_SHIFT 2
-#define SDHC_XFERTYP_DTDSEL_MASK 0x10u
-#define SDHC_XFERTYP_DTDSEL_SHIFT 4
-#define SDHC_XFERTYP_MSBSEL_MASK 0x20u
-#define SDHC_XFERTYP_MSBSEL_SHIFT 5
-#define SDHC_XFERTYP_RSPTYP_MASK 0x30000u
-#define SDHC_XFERTYP_RSPTYP_SHIFT 16
-#define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_RSPTYP_SHIFT))&SDHC_XFERTYP_RSPTYP_MASK)
-#define SDHC_XFERTYP_CCCEN_MASK 0x80000u
-#define SDHC_XFERTYP_CCCEN_SHIFT 19
-#define SDHC_XFERTYP_CICEN_MASK 0x100000u
-#define SDHC_XFERTYP_CICEN_SHIFT 20
-#define SDHC_XFERTYP_DPSEL_MASK 0x200000u
-#define SDHC_XFERTYP_DPSEL_SHIFT 21
-#define SDHC_XFERTYP_CMDTYP_MASK 0xC00000u
-#define SDHC_XFERTYP_CMDTYP_SHIFT 22
-#define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDTYP_SHIFT))&SDHC_XFERTYP_CMDTYP_MASK)
-#define SDHC_XFERTYP_CMDINX_MASK 0x3F000000u
-#define SDHC_XFERTYP_CMDINX_SHIFT 24
-#define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDINX_SHIFT))&SDHC_XFERTYP_CMDINX_MASK)
-/* CMDRSP Bit Fields */
-#define SDHC_CMDRSP_CMDRSP0_MASK 0xFFFFFFFFu
-#define SDHC_CMDRSP_CMDRSP0_SHIFT 0
-#define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP0_SHIFT))&SDHC_CMDRSP_CMDRSP0_MASK)
-#define SDHC_CMDRSP_CMDRSP1_MASK 0xFFFFFFFFu
-#define SDHC_CMDRSP_CMDRSP1_SHIFT 0
-#define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP1_SHIFT))&SDHC_CMDRSP_CMDRSP1_MASK)
-#define SDHC_CMDRSP_CMDRSP2_MASK 0xFFFFFFFFu
-#define SDHC_CMDRSP_CMDRSP2_SHIFT 0
-#define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP2_SHIFT))&SDHC_CMDRSP_CMDRSP2_MASK)
-#define SDHC_CMDRSP_CMDRSP3_MASK 0xFFFFFFFFu
-#define SDHC_CMDRSP_CMDRSP3_SHIFT 0
-#define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP3_SHIFT))&SDHC_CMDRSP_CMDRSP3_MASK)
-/* DATPORT Bit Fields */
-#define SDHC_DATPORT_DATCONT_MASK 0xFFFFFFFFu
-#define SDHC_DATPORT_DATCONT_SHIFT 0
-#define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DATPORT_DATCONT_SHIFT))&SDHC_DATPORT_DATCONT_MASK)
-/* PRSSTAT Bit Fields */
-#define SDHC_PRSSTAT_CIHB_MASK 0x1u
-#define SDHC_PRSSTAT_CIHB_SHIFT 0
-#define SDHC_PRSSTAT_CDIHB_MASK 0x2u
-#define SDHC_PRSSTAT_CDIHB_SHIFT 1
-#define SDHC_PRSSTAT_DLA_MASK 0x4u
-#define SDHC_PRSSTAT_DLA_SHIFT 2
-#define SDHC_PRSSTAT_SDSTB_MASK 0x8u
-#define SDHC_PRSSTAT_SDSTB_SHIFT 3
-#define SDHC_PRSSTAT_IPGOFF_MASK 0x10u
-#define SDHC_PRSSTAT_IPGOFF_SHIFT 4
-#define SDHC_PRSSTAT_HCKOFF_MASK 0x20u
-#define SDHC_PRSSTAT_HCKOFF_SHIFT 5
-#define SDHC_PRSSTAT_PEROFF_MASK 0x40u
-#define SDHC_PRSSTAT_PEROFF_SHIFT 6
-#define SDHC_PRSSTAT_SDOFF_MASK 0x80u
-#define SDHC_PRSSTAT_SDOFF_SHIFT 7
-#define SDHC_PRSSTAT_WTA_MASK 0x100u
-#define SDHC_PRSSTAT_WTA_SHIFT 8
-#define SDHC_PRSSTAT_RTA_MASK 0x200u
-#define SDHC_PRSSTAT_RTA_SHIFT 9
-#define SDHC_PRSSTAT_BWEN_MASK 0x400u
-#define SDHC_PRSSTAT_BWEN_SHIFT 10
-#define SDHC_PRSSTAT_BREN_MASK 0x800u
-#define SDHC_PRSSTAT_BREN_SHIFT 11
-#define SDHC_PRSSTAT_CINS_MASK 0x10000u
-#define SDHC_PRSSTAT_CINS_SHIFT 16
-#define SDHC_PRSSTAT_CLSL_MASK 0x800000u
-#define SDHC_PRSSTAT_CLSL_SHIFT 23
-#define SDHC_PRSSTAT_DLSL_MASK 0xFF000000u
-#define SDHC_PRSSTAT_DLSL_SHIFT 24
-#define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLSL_SHIFT))&SDHC_PRSSTAT_DLSL_MASK)
-/* PROCTL Bit Fields */
-#define SDHC_PROCTL_LCTL_MASK 0x1u
-#define SDHC_PROCTL_LCTL_SHIFT 0
-#define SDHC_PROCTL_DTW_MASK 0x6u
-#define SDHC_PROCTL_DTW_SHIFT 1
-#define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DTW_SHIFT))&SDHC_PROCTL_DTW_MASK)
-#define SDHC_PROCTL_D3CD_MASK 0x8u
-#define SDHC_PROCTL_D3CD_SHIFT 3
-#define SDHC_PROCTL_EMODE_MASK 0x30u
-#define SDHC_PROCTL_EMODE_SHIFT 4
-#define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_EMODE_SHIFT))&SDHC_PROCTL_EMODE_MASK)
-#define SDHC_PROCTL_CDTL_MASK 0x40u
-#define SDHC_PROCTL_CDTL_SHIFT 6
-#define SDHC_PROCTL_CDSS_MASK 0x80u
-#define SDHC_PROCTL_CDSS_SHIFT 7
-#define SDHC_PROCTL_DMAS_MASK 0x300u
-#define SDHC_PROCTL_DMAS_SHIFT 8
-#define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DMAS_SHIFT))&SDHC_PROCTL_DMAS_MASK)
-#define SDHC_PROCTL_SABGREQ_MASK 0x10000u
-#define SDHC_PROCTL_SABGREQ_SHIFT 16
-#define SDHC_PROCTL_CREQ_MASK 0x20000u
-#define SDHC_PROCTL_CREQ_SHIFT 17
-#define SDHC_PROCTL_RWCTL_MASK 0x40000u
-#define SDHC_PROCTL_RWCTL_SHIFT 18
-#define SDHC_PROCTL_IABG_MASK 0x80000u
-#define SDHC_PROCTL_IABG_SHIFT 19
-#define SDHC_PROCTL_WECINT_MASK 0x1000000u
-#define SDHC_PROCTL_WECINT_SHIFT 24
-#define SDHC_PROCTL_WECINS_MASK 0x2000000u
-#define SDHC_PROCTL_WECINS_SHIFT 25
-#define SDHC_PROCTL_WECRM_MASK 0x4000000u
-#define SDHC_PROCTL_WECRM_SHIFT 26
-/* SYSCTL Bit Fields */
-#define SDHC_SYSCTL_IPGEN_MASK 0x1u
-#define SDHC_SYSCTL_IPGEN_SHIFT 0
-#define SDHC_SYSCTL_HCKEN_MASK 0x2u
-#define SDHC_SYSCTL_HCKEN_SHIFT 1
-#define SDHC_SYSCTL_PEREN_MASK 0x4u
-#define SDHC_SYSCTL_PEREN_SHIFT 2
-#define SDHC_SYSCTL_SDCLKEN_MASK 0x8u
-#define SDHC_SYSCTL_SDCLKEN_SHIFT 3
-#define SDHC_SYSCTL_DVS_MASK 0xF0u
-#define SDHC_SYSCTL_DVS_SHIFT 4
-#define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DVS_SHIFT))&SDHC_SYSCTL_DVS_MASK)
-#define SDHC_SYSCTL_SDCLKFS_MASK 0xFF00u
-#define SDHC_SYSCTL_SDCLKFS_SHIFT 8
-#define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKFS_SHIFT))&SDHC_SYSCTL_SDCLKFS_MASK)
-#define SDHC_SYSCTL_DTOCV_MASK 0xF0000u
-#define SDHC_SYSCTL_DTOCV_SHIFT 16
-#define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DTOCV_SHIFT))&SDHC_SYSCTL_DTOCV_MASK)
-#define SDHC_SYSCTL_RSTA_MASK 0x1000000u
-#define SDHC_SYSCTL_RSTA_SHIFT 24
-#define SDHC_SYSCTL_RSTC_MASK 0x2000000u
-#define SDHC_SYSCTL_RSTC_SHIFT 25
-#define SDHC_SYSCTL_RSTD_MASK 0x4000000u
-#define SDHC_SYSCTL_RSTD_SHIFT 26
-#define SDHC_SYSCTL_INITA_MASK 0x8000000u
-#define SDHC_SYSCTL_INITA_SHIFT 27
-/* IRQSTAT Bit Fields */
-#define SDHC_IRQSTAT_CC_MASK 0x1u
-#define SDHC_IRQSTAT_CC_SHIFT 0
-#define SDHC_IRQSTAT_TC_MASK 0x2u
-#define SDHC_IRQSTAT_TC_SHIFT 1
-#define SDHC_IRQSTAT_BGE_MASK 0x4u
-#define SDHC_IRQSTAT_BGE_SHIFT 2
-#define SDHC_IRQSTAT_DINT_MASK 0x8u
-#define SDHC_IRQSTAT_DINT_SHIFT 3
-#define SDHC_IRQSTAT_BWR_MASK 0x10u
-#define SDHC_IRQSTAT_BWR_SHIFT 4
-#define SDHC_IRQSTAT_BRR_MASK 0x20u
-#define SDHC_IRQSTAT_BRR_SHIFT 5
-#define SDHC_IRQSTAT_CINS_MASK 0x40u
-#define SDHC_IRQSTAT_CINS_SHIFT 6
-#define SDHC_IRQSTAT_CRM_MASK 0x80u
-#define SDHC_IRQSTAT_CRM_SHIFT 7
-#define SDHC_IRQSTAT_CINT_MASK 0x100u
-#define SDHC_IRQSTAT_CINT_SHIFT 8
-#define SDHC_IRQSTAT_CTOE_MASK 0x10000u
-#define SDHC_IRQSTAT_CTOE_SHIFT 16
-#define SDHC_IRQSTAT_CCE_MASK 0x20000u
-#define SDHC_IRQSTAT_CCE_SHIFT 17
-#define SDHC_IRQSTAT_CEBE_MASK 0x40000u
-#define SDHC_IRQSTAT_CEBE_SHIFT 18
-#define SDHC_IRQSTAT_CIE_MASK 0x80000u
-#define SDHC_IRQSTAT_CIE_SHIFT 19
-#define SDHC_IRQSTAT_DTOE_MASK 0x100000u
-#define SDHC_IRQSTAT_DTOE_SHIFT 20
-#define SDHC_IRQSTAT_DCE_MASK 0x200000u
-#define SDHC_IRQSTAT_DCE_SHIFT 21
-#define SDHC_IRQSTAT_DEBE_MASK 0x400000u
-#define SDHC_IRQSTAT_DEBE_SHIFT 22
-#define SDHC_IRQSTAT_AC12E_MASK 0x1000000u
-#define SDHC_IRQSTAT_AC12E_SHIFT 24
-#define SDHC_IRQSTAT_DMAE_MASK 0x10000000u
-#define SDHC_IRQSTAT_DMAE_SHIFT 28
-/* IRQSTATEN Bit Fields */
-#define SDHC_IRQSTATEN_CCSEN_MASK 0x1u
-#define SDHC_IRQSTATEN_CCSEN_SHIFT 0
-#define SDHC_IRQSTATEN_TCSEN_MASK 0x2u
-#define SDHC_IRQSTATEN_TCSEN_SHIFT 1
-#define SDHC_IRQSTATEN_BGESEN_MASK 0x4u
-#define SDHC_IRQSTATEN_BGESEN_SHIFT 2
-#define SDHC_IRQSTATEN_DINTSEN_MASK 0x8u
-#define SDHC_IRQSTATEN_DINTSEN_SHIFT 3
-#define SDHC_IRQSTATEN_BWRSEN_MASK 0x10u
-#define SDHC_IRQSTATEN_BWRSEN_SHIFT 4
-#define SDHC_IRQSTATEN_BRRSEN_MASK 0x20u
-#define SDHC_IRQSTATEN_BRRSEN_SHIFT 5
-#define SDHC_IRQSTATEN_CINSEN_MASK 0x40u
-#define SDHC_IRQSTATEN_CINSEN_SHIFT 6
-#define SDHC_IRQSTATEN_CRMSEN_MASK 0x80u
-#define SDHC_IRQSTATEN_CRMSEN_SHIFT 7
-#define SDHC_IRQSTATEN_CINTSEN_MASK 0x100u
-#define SDHC_IRQSTATEN_CINTSEN_SHIFT 8
-#define SDHC_IRQSTATEN_CTOESEN_MASK 0x10000u
-#define SDHC_IRQSTATEN_CTOESEN_SHIFT 16
-#define SDHC_IRQSTATEN_CCESEN_MASK 0x20000u
-#define SDHC_IRQSTATEN_CCESEN_SHIFT 17
-#define SDHC_IRQSTATEN_CEBESEN_MASK 0x40000u
-#define SDHC_IRQSTATEN_CEBESEN_SHIFT 18
-#define SDHC_IRQSTATEN_CIESEN_MASK 0x80000u
-#define SDHC_IRQSTATEN_CIESEN_SHIFT 19
-#define SDHC_IRQSTATEN_DTOESEN_MASK 0x100000u
-#define SDHC_IRQSTATEN_DTOESEN_SHIFT 20
-#define SDHC_IRQSTATEN_DCESEN_MASK 0x200000u
-#define SDHC_IRQSTATEN_DCESEN_SHIFT 21
-#define SDHC_IRQSTATEN_DEBESEN_MASK 0x400000u
-#define SDHC_IRQSTATEN_DEBESEN_SHIFT 22
-#define SDHC_IRQSTATEN_AC12ESEN_MASK 0x1000000u
-#define SDHC_IRQSTATEN_AC12ESEN_SHIFT 24
-#define SDHC_IRQSTATEN_DMAESEN_MASK 0x10000000u
-#define SDHC_IRQSTATEN_DMAESEN_SHIFT 28
-/* IRQSIGEN Bit Fields */
-#define SDHC_IRQSIGEN_CCIEN_MASK 0x1u
-#define SDHC_IRQSIGEN_CCIEN_SHIFT 0
-#define SDHC_IRQSIGEN_TCIEN_MASK 0x2u
-#define SDHC_IRQSIGEN_TCIEN_SHIFT 1
-#define SDHC_IRQSIGEN_BGEIEN_MASK 0x4u
-#define SDHC_IRQSIGEN_BGEIEN_SHIFT 2
-#define SDHC_IRQSIGEN_DINTIEN_MASK 0x8u
-#define SDHC_IRQSIGEN_DINTIEN_SHIFT 3
-#define SDHC_IRQSIGEN_BWRIEN_MASK 0x10u
-#define SDHC_IRQSIGEN_BWRIEN_SHIFT 4
-#define SDHC_IRQSIGEN_BRRIEN_MASK 0x20u
-#define SDHC_IRQSIGEN_BRRIEN_SHIFT 5
-#define SDHC_IRQSIGEN_CINSIEN_MASK 0x40u
-#define SDHC_IRQSIGEN_CINSIEN_SHIFT 6
-#define SDHC_IRQSIGEN_CRMIEN_MASK 0x80u
-#define SDHC_IRQSIGEN_CRMIEN_SHIFT 7
-#define SDHC_IRQSIGEN_CINTIEN_MASK 0x100u
-#define SDHC_IRQSIGEN_CINTIEN_SHIFT 8
-#define SDHC_IRQSIGEN_CTOEIEN_MASK 0x10000u
-#define SDHC_IRQSIGEN_CTOEIEN_SHIFT 16
-#define SDHC_IRQSIGEN_CCEIEN_MASK 0x20000u
-#define SDHC_IRQSIGEN_CCEIEN_SHIFT 17
-#define SDHC_IRQSIGEN_CEBEIEN_MASK 0x40000u
-#define SDHC_IRQSIGEN_CEBEIEN_SHIFT 18
-#define SDHC_IRQSIGEN_CIEIEN_MASK 0x80000u
-#define SDHC_IRQSIGEN_CIEIEN_SHIFT 19
-#define SDHC_IRQSIGEN_DTOEIEN_MASK 0x100000u
-#define SDHC_IRQSIGEN_DTOEIEN_SHIFT 20
-#define SDHC_IRQSIGEN_DCEIEN_MASK 0x200000u
-#define SDHC_IRQSIGEN_DCEIEN_SHIFT 21
-#define SDHC_IRQSIGEN_DEBEIEN_MASK 0x400000u
-#define SDHC_IRQSIGEN_DEBEIEN_SHIFT 22
-#define SDHC_IRQSIGEN_AC12EIEN_MASK 0x1000000u
-#define SDHC_IRQSIGEN_AC12EIEN_SHIFT 24
-#define SDHC_IRQSIGEN_DMAEIEN_MASK 0x10000000u
-#define SDHC_IRQSIGEN_DMAEIEN_SHIFT 28
-/* AC12ERR Bit Fields */
-#define SDHC_AC12ERR_AC12NE_MASK 0x1u
-#define SDHC_AC12ERR_AC12NE_SHIFT 0
-#define SDHC_AC12ERR_AC12TOE_MASK 0x2u
-#define SDHC_AC12ERR_AC12TOE_SHIFT 1
-#define SDHC_AC12ERR_AC12EBE_MASK 0x4u
-#define SDHC_AC12ERR_AC12EBE_SHIFT 2
-#define SDHC_AC12ERR_AC12CE_MASK 0x8u
-#define SDHC_AC12ERR_AC12CE_SHIFT 3
-#define SDHC_AC12ERR_AC12IE_MASK 0x10u
-#define SDHC_AC12ERR_AC12IE_SHIFT 4
-#define SDHC_AC12ERR_CNIBAC12E_MASK 0x80u
-#define SDHC_AC12ERR_CNIBAC12E_SHIFT 7
-/* HTCAPBLT Bit Fields */
-#define SDHC_HTCAPBLT_MBL_MASK 0x70000u
-#define SDHC_HTCAPBLT_MBL_SHIFT 16
-#define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_MBL_SHIFT))&SDHC_HTCAPBLT_MBL_MASK)
-#define SDHC_HTCAPBLT_ADMAS_MASK 0x100000u
-#define SDHC_HTCAPBLT_ADMAS_SHIFT 20
-#define SDHC_HTCAPBLT_HSS_MASK 0x200000u
-#define SDHC_HTCAPBLT_HSS_SHIFT 21
-#define SDHC_HTCAPBLT_DMAS_MASK 0x400000u
-#define SDHC_HTCAPBLT_DMAS_SHIFT 22
-#define SDHC_HTCAPBLT_SRS_MASK 0x800000u
-#define SDHC_HTCAPBLT_SRS_SHIFT 23
-#define SDHC_HTCAPBLT_VS33_MASK 0x1000000u
-#define SDHC_HTCAPBLT_VS33_SHIFT 24
-/* WML Bit Fields */
-#define SDHC_WML_RDWML_MASK 0xFFu
-#define SDHC_WML_RDWML_SHIFT 0
-#define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_RDWML_SHIFT))&SDHC_WML_RDWML_MASK)
-#define SDHC_WML_WRWML_MASK 0xFF0000u
-#define SDHC_WML_WRWML_SHIFT 16
-#define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRWML_SHIFT))&SDHC_WML_WRWML_MASK)
-/* FEVT Bit Fields */
-#define SDHC_FEVT_AC12NE_MASK 0x1u
-#define SDHC_FEVT_AC12NE_SHIFT 0
-#define SDHC_FEVT_AC12TOE_MASK 0x2u
-#define SDHC_FEVT_AC12TOE_SHIFT 1
-#define SDHC_FEVT_AC12CE_MASK 0x4u
-#define SDHC_FEVT_AC12CE_SHIFT 2
-#define SDHC_FEVT_AC12EBE_MASK 0x8u
-#define SDHC_FEVT_AC12EBE_SHIFT 3
-#define SDHC_FEVT_AC12IE_MASK 0x10u
-#define SDHC_FEVT_AC12IE_SHIFT 4
-#define SDHC_FEVT_CNIBAC12E_MASK 0x80u
-#define SDHC_FEVT_CNIBAC12E_SHIFT 7
-#define SDHC_FEVT_CTOE_MASK 0x10000u
-#define SDHC_FEVT_CTOE_SHIFT 16
-#define SDHC_FEVT_CCE_MASK 0x20000u
-#define SDHC_FEVT_CCE_SHIFT 17
-#define SDHC_FEVT_CEBE_MASK 0x40000u
-#define SDHC_FEVT_CEBE_SHIFT 18
-#define SDHC_FEVT_CIE_MASK 0x80000u
-#define SDHC_FEVT_CIE_SHIFT 19
-#define SDHC_FEVT_DTOE_MASK 0x100000u
-#define SDHC_FEVT_DTOE_SHIFT 20
-#define SDHC_FEVT_DCE_MASK 0x200000u
-#define SDHC_FEVT_DCE_SHIFT 21
-#define SDHC_FEVT_DEBE_MASK 0x400000u
-#define SDHC_FEVT_DEBE_SHIFT 22
-#define SDHC_FEVT_AC12E_MASK 0x1000000u
-#define SDHC_FEVT_AC12E_SHIFT 24
-#define SDHC_FEVT_DMAE_MASK 0x10000000u
-#define SDHC_FEVT_DMAE_SHIFT 28
-#define SDHC_FEVT_CINT_MASK 0x80000000u
-#define SDHC_FEVT_CINT_SHIFT 31
-/* ADMAES Bit Fields */
-#define SDHC_ADMAES_ADMAES_MASK 0x3u
-#define SDHC_ADMAES_ADMAES_SHIFT 0
-#define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMAES_SHIFT))&SDHC_ADMAES_ADMAES_MASK)
-#define SDHC_ADMAES_ADMALME_MASK 0x4u
-#define SDHC_ADMAES_ADMALME_SHIFT 2
-#define SDHC_ADMAES_ADMADCE_MASK 0x8u
-#define SDHC_ADMAES_ADMADCE_SHIFT 3
-/* ADSADDR Bit Fields */
-#define SDHC_ADSADDR_ADSADDR_MASK 0xFFFFFFFCu
-#define SDHC_ADSADDR_ADSADDR_SHIFT 2
-#define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADSADDR_ADSADDR_SHIFT))&SDHC_ADSADDR_ADSADDR_MASK)
-/* VENDOR Bit Fields */
-#define SDHC_VENDOR_EXTDMAEN_MASK 0x1u
-#define SDHC_VENDOR_EXTDMAEN_SHIFT 0
-#define SDHC_VENDOR_EXBLKNU_MASK 0x2u
-#define SDHC_VENDOR_EXBLKNU_SHIFT 1
-#define SDHC_VENDOR_INTSTVAL_MASK 0xFF0000u
-#define SDHC_VENDOR_INTSTVAL_SHIFT 16
-#define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_INTSTVAL_SHIFT))&SDHC_VENDOR_INTSTVAL_MASK)
-/* MMCBOOT Bit Fields */
-#define SDHC_MMCBOOT_DTOCVACK_MASK 0xFu
-#define SDHC_MMCBOOT_DTOCVACK_SHIFT 0
-#define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_DTOCVACK_SHIFT))&SDHC_MMCBOOT_DTOCVACK_MASK)
-#define SDHC_MMCBOOT_BOOTACK_MASK 0x10u
-#define SDHC_MMCBOOT_BOOTACK_SHIFT 4
-#define SDHC_MMCBOOT_BOOTMODE_MASK 0x20u
-#define SDHC_MMCBOOT_BOOTMODE_SHIFT 5
-#define SDHC_MMCBOOT_BOOTEN_MASK 0x40u
-#define SDHC_MMCBOOT_BOOTEN_SHIFT 6
-#define SDHC_MMCBOOT_AUTOSABGEN_MASK 0x80u
-#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT 7
-#define SDHC_MMCBOOT_BOOTBLKCNT_MASK 0xFFFF0000u
-#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT 16
-#define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTBLKCNT_SHIFT))&SDHC_MMCBOOT_BOOTBLKCNT_MASK)
-/* HOSTVER Bit Fields */
-#define SDHC_HOSTVER_SVN_MASK 0xFFu
-#define SDHC_HOSTVER_SVN_SHIFT 0
-#define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_SVN_SHIFT))&SDHC_HOSTVER_SVN_MASK)
-#define SDHC_HOSTVER_VVN_MASK 0xFF00u
-#define SDHC_HOSTVER_VVN_SHIFT 8
-#define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_VVN_SHIFT))&SDHC_HOSTVER_VVN_MASK)
-
-/*!
- * @}
- */ /* end of group SDHC_Register_Masks */
-
-
-/* SDHC - Peripheral instance base addresses */
-/** Peripheral SDHC base address */
-#define SDHC_BASE (0x400B1000u)
-/** Peripheral SDHC base pointer */
-#define SDHC ((SDHC_Type *)SDHC_BASE)
-#define SDHC_BASE_PTR (SDHC)
-/** Array initializer of SDHC peripheral base pointers */
-#define SDHC_BASES { SDHC }
-
-/* ----------------------------------------------------------------------------
- -- SDHC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
- * @{
- */
-
-
-/* SDHC - Register instance definitions */
-/* SDHC */
-#define SDHC_DSADDR SDHC_DSADDR_REG(SDHC)
-#define SDHC_BLKATTR SDHC_BLKATTR_REG(SDHC)
-#define SDHC_CMDARG SDHC_CMDARG_REG(SDHC)
-#define SDHC_XFERTYP SDHC_XFERTYP_REG(SDHC)
-#define SDHC_CMDRSP0 SDHC_CMDRSP_REG(SDHC,0)
-#define SDHC_CMDRSP1 SDHC_CMDRSP_REG(SDHC,1)
-#define SDHC_CMDRSP2 SDHC_CMDRSP_REG(SDHC,2)
-#define SDHC_CMDRSP3 SDHC_CMDRSP_REG(SDHC,3)
-#define SDHC_DATPORT SDHC_DATPORT_REG(SDHC)
-#define SDHC_PRSSTAT SDHC_PRSSTAT_REG(SDHC)
-#define SDHC_PROCTL SDHC_PROCTL_REG(SDHC)
-#define SDHC_SYSCTL SDHC_SYSCTL_REG(SDHC)
-#define SDHC_IRQSTAT SDHC_IRQSTAT_REG(SDHC)
-#define SDHC_IRQSTATEN SDHC_IRQSTATEN_REG(SDHC)
-#define SDHC_IRQSIGEN SDHC_IRQSIGEN_REG(SDHC)
-#define SDHC_AC12ERR SDHC_AC12ERR_REG(SDHC)
-#define SDHC_HTCAPBLT SDHC_HTCAPBLT_REG(SDHC)
-#define SDHC_WML SDHC_WML_REG(SDHC)
-#define SDHC_FEVT SDHC_FEVT_REG(SDHC)
-#define SDHC_ADMAES SDHC_ADMAES_REG(SDHC)
-#define SDHC_ADSADDR SDHC_ADSADDR_REG(SDHC)
-#define SDHC_VENDOR SDHC_VENDOR_REG(SDHC)
-#define SDHC_MMCBOOT SDHC_MMCBOOT_REG(SDHC)
-#define SDHC_HOSTVER SDHC_HOSTVER_REG(SDHC)
-
-/* SDHC - Register array accessors */
-#define SDHC_CMDRSP(index) SDHC_CMDRSP_REG(SDHC,index)
-
-/*!
- * @}
- */ /* end of group SDHC_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group SDHC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- SIM Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
- * @{
- */
-
-/** SIM - Register Layout Typedef */
-typedef struct {
- __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
- __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
- uint8_t RESERVED_0[4092];
- __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
- uint8_t RESERVED_1[4];
- __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
- __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
- uint8_t RESERVED_2[4];
- __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
- uint8_t RESERVED_3[8];
- __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
- __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */
- __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */
- __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */
- __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
- __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
- __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
- __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
- __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
- __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
- __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
- __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
- __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
- __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
- __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
- __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
-} SIM_Type, *SIM_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- SIM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
- * @{
- */
-
-
-/* SIM - Register accessors */
-#define SIM_SOPT1_REG(base) ((base)->SOPT1)
-#define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG)
-#define SIM_SOPT2_REG(base) ((base)->SOPT2)
-#define SIM_SOPT4_REG(base) ((base)->SOPT4)
-#define SIM_SOPT5_REG(base) ((base)->SOPT5)
-#define SIM_SOPT7_REG(base) ((base)->SOPT7)
-#define SIM_SDID_REG(base) ((base)->SDID)
-#define SIM_SCGC1_REG(base) ((base)->SCGC1)
-#define SIM_SCGC2_REG(base) ((base)->SCGC2)
-#define SIM_SCGC3_REG(base) ((base)->SCGC3)
-#define SIM_SCGC4_REG(base) ((base)->SCGC4)
-#define SIM_SCGC5_REG(base) ((base)->SCGC5)
-#define SIM_SCGC6_REG(base) ((base)->SCGC6)
-#define SIM_SCGC7_REG(base) ((base)->SCGC7)
-#define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)
-#define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2)
-#define SIM_FCFG1_REG(base) ((base)->FCFG1)
-#define SIM_FCFG2_REG(base) ((base)->FCFG2)
-#define SIM_UIDH_REG(base) ((base)->UIDH)
-#define SIM_UIDMH_REG(base) ((base)->UIDMH)
-#define SIM_UIDML_REG(base) ((base)->UIDML)
-#define SIM_UIDL_REG(base) ((base)->UIDL)
-
-/*!
- * @}
- */ /* end of group SIM_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- SIM Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SIM_Register_Masks SIM Register Masks
- * @{
- */
-
-/* SOPT1 Bit Fields */
-#define SIM_SOPT1_RAMSIZE_MASK 0xF000u
-#define SIM_SOPT1_RAMSIZE_SHIFT 12
-#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
-#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
-#define SIM_SOPT1_OSC32KSEL_SHIFT 18
-#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
-#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
-#define SIM_SOPT1_USBVSTBY_SHIFT 29
-#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
-#define SIM_SOPT1_USBSSTBY_SHIFT 30
-#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
-#define SIM_SOPT1_USBREGEN_SHIFT 31
-/* SOPT1CFG Bit Fields */
-#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
-#define SIM_SOPT1CFG_URWE_SHIFT 24
-#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
-#define SIM_SOPT1CFG_UVSWE_SHIFT 25
-#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
-#define SIM_SOPT1CFG_USSWE_SHIFT 26
-/* SOPT2 Bit Fields */
-#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
-#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
-#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
-#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
-#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
-#define SIM_SOPT2_FBSL_MASK 0x300u
-#define SIM_SOPT2_FBSL_SHIFT 8
-#define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
-#define SIM_SOPT2_PTD7PAD_MASK 0x800u
-#define SIM_SOPT2_PTD7PAD_SHIFT 11
-#define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
-#define SIM_SOPT2_TRACECLKSEL_SHIFT 12
-#define SIM_SOPT2_PLLFLLSEL_MASK 0x30000u
-#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
-#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PLLFLLSEL_SHIFT))&SIM_SOPT2_PLLFLLSEL_MASK)
-#define SIM_SOPT2_USBSRC_MASK 0x40000u
-#define SIM_SOPT2_USBSRC_SHIFT 18
-#define SIM_SOPT2_RMIISRC_MASK 0x80000u
-#define SIM_SOPT2_RMIISRC_SHIFT 19
-#define SIM_SOPT2_TIMESRC_MASK 0x300000u
-#define SIM_SOPT2_TIMESRC_SHIFT 20
-#define SIM_SOPT2_TIMESRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TIMESRC_SHIFT))&SIM_SOPT2_TIMESRC_MASK)
-#define SIM_SOPT2_SDHCSRC_MASK 0x30000000u
-#define SIM_SOPT2_SDHCSRC_SHIFT 28
-#define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_SDHCSRC_SHIFT))&SIM_SOPT2_SDHCSRC_MASK)
-/* SOPT4 Bit Fields */
-#define SIM_SOPT4_FTM0FLT0_MASK 0x1u
-#define SIM_SOPT4_FTM0FLT0_SHIFT 0
-#define SIM_SOPT4_FTM0FLT1_MASK 0x2u
-#define SIM_SOPT4_FTM0FLT1_SHIFT 1
-#define SIM_SOPT4_FTM0FLT2_MASK 0x4u
-#define SIM_SOPT4_FTM0FLT2_SHIFT 2
-#define SIM_SOPT4_FTM1FLT0_MASK 0x10u
-#define SIM_SOPT4_FTM1FLT0_SHIFT 4
-#define SIM_SOPT4_FTM2FLT0_MASK 0x100u
-#define SIM_SOPT4_FTM2FLT0_SHIFT 8
-#define SIM_SOPT4_FTM3FLT0_MASK 0x1000u
-#define SIM_SOPT4_FTM3FLT0_SHIFT 12
-#define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
-#define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
-#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
-#define SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u
-#define SIM_SOPT4_FTM2CH0SRC_SHIFT 20
-#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
-#define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
-#define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
-#define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
-#define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
-#define SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u
-#define SIM_SOPT4_FTM2CLKSEL_SHIFT 26
-#define SIM_SOPT4_FTM3CLKSEL_MASK 0x8000000u
-#define SIM_SOPT4_FTM3CLKSEL_SHIFT 27
-#define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
-#define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
-#define SIM_SOPT4_FTM0TRG1SRC_MASK 0x20000000u
-#define SIM_SOPT4_FTM0TRG1SRC_SHIFT 29
-#define SIM_SOPT4_FTM3TRG0SRC_MASK 0x40000000u
-#define SIM_SOPT4_FTM3TRG0SRC_SHIFT 30
-#define SIM_SOPT4_FTM3TRG1SRC_MASK 0x80000000u
-#define SIM_SOPT4_FTM3TRG1SRC_SHIFT 31
-/* SOPT5 Bit Fields */
-#define SIM_SOPT5_UART0TXSRC_MASK 0x3u
-#define SIM_SOPT5_UART0TXSRC_SHIFT 0
-#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
-#define SIM_SOPT5_UART0RXSRC_MASK 0xCu
-#define SIM_SOPT5_UART0RXSRC_SHIFT 2
-#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
-#define SIM_SOPT5_UART1TXSRC_MASK 0x30u
-#define SIM_SOPT5_UART1TXSRC_SHIFT 4
-#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
-#define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
-#define SIM_SOPT5_UART1RXSRC_SHIFT 6
-#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
-/* SOPT7 Bit Fields */
-#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
-#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
-#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
-#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
-#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
-#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
-#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
-#define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u
-#define SIM_SOPT7_ADC1TRGSEL_SHIFT 8
-#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
-#define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u
-#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12
-#define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u
-#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15
-/* SDID Bit Fields */
-#define SIM_SDID_PINID_MASK 0xFu
-#define SIM_SDID_PINID_SHIFT 0
-#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
-#define SIM_SDID_FAMID_MASK 0x70u
-#define SIM_SDID_FAMID_SHIFT 4
-#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
-#define SIM_SDID_DIEID_MASK 0xF80u
-#define SIM_SDID_DIEID_SHIFT 7
-#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
-#define SIM_SDID_REVID_MASK 0xF000u
-#define SIM_SDID_REVID_SHIFT 12
-#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
-#define SIM_SDID_SERIESID_MASK 0xF00000u
-#define SIM_SDID_SERIESID_SHIFT 20
-#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
-#define SIM_SDID_SUBFAMID_MASK 0xF000000u
-#define SIM_SDID_SUBFAMID_SHIFT 24
-#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
-#define SIM_SDID_FAMILYID_MASK 0xF0000000u
-#define SIM_SDID_FAMILYID_SHIFT 28
-#define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMILYID_SHIFT))&SIM_SDID_FAMILYID_MASK)
-/* SCGC1 Bit Fields */
-#define SIM_SCGC1_I2C2_MASK 0x40u
-#define SIM_SCGC1_I2C2_SHIFT 6
-#define SIM_SCGC1_UART4_MASK 0x400u
-#define SIM_SCGC1_UART4_SHIFT 10
-#define SIM_SCGC1_UART5_MASK 0x800u
-#define SIM_SCGC1_UART5_SHIFT 11
-/* SCGC2 Bit Fields */
-#define SIM_SCGC2_ENET_MASK 0x1u
-#define SIM_SCGC2_ENET_SHIFT 0
-#define SIM_SCGC2_DAC0_MASK 0x1000u
-#define SIM_SCGC2_DAC0_SHIFT 12
-#define SIM_SCGC2_DAC1_MASK 0x2000u
-#define SIM_SCGC2_DAC1_SHIFT 13
-/* SCGC3 Bit Fields */
-#define SIM_SCGC3_RNGA_MASK 0x1u
-#define SIM_SCGC3_RNGA_SHIFT 0
-#define SIM_SCGC3_SPI2_MASK 0x1000u
-#define SIM_SCGC3_SPI2_SHIFT 12
-#define SIM_SCGC3_SDHC_MASK 0x20000u
-#define SIM_SCGC3_SDHC_SHIFT 17
-#define SIM_SCGC3_FTM2_MASK 0x1000000u
-#define SIM_SCGC3_FTM2_SHIFT 24
-#define SIM_SCGC3_FTM3_MASK 0x2000000u
-#define SIM_SCGC3_FTM3_SHIFT 25
-#define SIM_SCGC3_ADC1_MASK 0x8000000u
-#define SIM_SCGC3_ADC1_SHIFT 27
-/* SCGC4 Bit Fields */
-#define SIM_SCGC4_EWM_MASK 0x2u
-#define SIM_SCGC4_EWM_SHIFT 1
-#define SIM_SCGC4_CMT_MASK 0x4u
-#define SIM_SCGC4_CMT_SHIFT 2
-#define SIM_SCGC4_I2C0_MASK 0x40u
-#define SIM_SCGC4_I2C0_SHIFT 6
-#define SIM_SCGC4_I2C1_MASK 0x80u
-#define SIM_SCGC4_I2C1_SHIFT 7
-#define SIM_SCGC4_UART0_MASK 0x400u
-#define SIM_SCGC4_UART0_SHIFT 10
-#define SIM_SCGC4_UART1_MASK 0x800u
-#define SIM_SCGC4_UART1_SHIFT 11
-#define SIM_SCGC4_UART2_MASK 0x1000u
-#define SIM_SCGC4_UART2_SHIFT 12
-#define SIM_SCGC4_UART3_MASK 0x2000u
-#define SIM_SCGC4_UART3_SHIFT 13
-#define SIM_SCGC4_USBOTG_MASK 0x40000u
-#define SIM_SCGC4_USBOTG_SHIFT 18
-#define SIM_SCGC4_CMP_MASK 0x80000u
-#define SIM_SCGC4_CMP_SHIFT 19
-#define SIM_SCGC4_VREF_MASK 0x100000u
-#define SIM_SCGC4_VREF_SHIFT 20
-/* SCGC5 Bit Fields */
-#define SIM_SCGC5_LPTMR_MASK 0x1u
-#define SIM_SCGC5_LPTMR_SHIFT 0
-#define SIM_SCGC5_PORTA_MASK 0x200u
-#define SIM_SCGC5_PORTA_SHIFT 9
-#define SIM_SCGC5_PORTB_MASK 0x400u
-#define SIM_SCGC5_PORTB_SHIFT 10
-#define SIM_SCGC5_PORTC_MASK 0x800u
-#define SIM_SCGC5_PORTC_SHIFT 11
-#define SIM_SCGC5_PORTD_MASK 0x1000u
-#define SIM_SCGC5_PORTD_SHIFT 12
-#define SIM_SCGC5_PORTE_MASK 0x2000u
-#define SIM_SCGC5_PORTE_SHIFT 13
-/* SCGC6 Bit Fields */
-#define SIM_SCGC6_FTF_MASK 0x1u
-#define SIM_SCGC6_FTF_SHIFT 0
-#define SIM_SCGC6_DMAMUX_MASK 0x2u
-#define SIM_SCGC6_DMAMUX_SHIFT 1
-#define SIM_SCGC6_FLEXCAN0_MASK 0x10u
-#define SIM_SCGC6_FLEXCAN0_SHIFT 4
-#define SIM_SCGC6_RNGA_MASK 0x200u
-#define SIM_SCGC6_RNGA_SHIFT 9
-#define SIM_SCGC6_SPI0_MASK 0x1000u
-#define SIM_SCGC6_SPI0_SHIFT 12
-#define SIM_SCGC6_SPI1_MASK 0x2000u
-#define SIM_SCGC6_SPI1_SHIFT 13
-#define SIM_SCGC6_I2S_MASK 0x8000u
-#define SIM_SCGC6_I2S_SHIFT 15
-#define SIM_SCGC6_CRC_MASK 0x40000u
-#define SIM_SCGC6_CRC_SHIFT 18
-#define SIM_SCGC6_USBDCD_MASK 0x200000u
-#define SIM_SCGC6_USBDCD_SHIFT 21
-#define SIM_SCGC6_PDB_MASK 0x400000u
-#define SIM_SCGC6_PDB_SHIFT 22
-#define SIM_SCGC6_PIT_MASK 0x800000u
-#define SIM_SCGC6_PIT_SHIFT 23
-#define SIM_SCGC6_FTM0_MASK 0x1000000u
-#define SIM_SCGC6_FTM0_SHIFT 24
-#define SIM_SCGC6_FTM1_MASK 0x2000000u
-#define SIM_SCGC6_FTM1_SHIFT 25
-#define SIM_SCGC6_FTM2_MASK 0x4000000u
-#define SIM_SCGC6_FTM2_SHIFT 26
-#define SIM_SCGC6_ADC0_MASK 0x8000000u
-#define SIM_SCGC6_ADC0_SHIFT 27
-#define SIM_SCGC6_RTC_MASK 0x20000000u
-#define SIM_SCGC6_RTC_SHIFT 29
-#define SIM_SCGC6_DAC0_MASK 0x80000000u
-#define SIM_SCGC6_DAC0_SHIFT 31
-/* SCGC7 Bit Fields */
-#define SIM_SCGC7_FLEXBUS_MASK 0x1u
-#define SIM_SCGC7_FLEXBUS_SHIFT 0
-#define SIM_SCGC7_DMA_MASK 0x2u
-#define SIM_SCGC7_DMA_SHIFT 1
-#define SIM_SCGC7_MPU_MASK 0x4u
-#define SIM_SCGC7_MPU_SHIFT 2
-/* CLKDIV1 Bit Fields */
-#define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
-#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
-#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
-#define SIM_CLKDIV1_OUTDIV3_MASK 0xF00000u
-#define SIM_CLKDIV1_OUTDIV3_SHIFT 20
-#define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
-#define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
-#define SIM_CLKDIV1_OUTDIV2_SHIFT 24
-#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
-#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
-#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
-#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
-/* CLKDIV2 Bit Fields */
-#define SIM_CLKDIV2_USBFRAC_MASK 0x1u
-#define SIM_CLKDIV2_USBFRAC_SHIFT 0
-#define SIM_CLKDIV2_USBDIV_MASK 0xEu
-#define SIM_CLKDIV2_USBDIV_SHIFT 1
-#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
-/* FCFG1 Bit Fields */
-#define SIM_FCFG1_FLASHDIS_MASK 0x1u
-#define SIM_FCFG1_FLASHDIS_SHIFT 0
-#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
-#define SIM_FCFG1_FLASHDOZE_SHIFT 1
-#define SIM_FCFG1_DEPART_MASK 0xF00u
-#define SIM_FCFG1_DEPART_SHIFT 8
-#define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
-#define SIM_FCFG1_EESIZE_MASK 0xF0000u
-#define SIM_FCFG1_EESIZE_SHIFT 16
-#define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
-#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
-#define SIM_FCFG1_PFSIZE_SHIFT 24
-#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
-#define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u
-#define SIM_FCFG1_NVMSIZE_SHIFT 28
-#define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
-/* FCFG2 Bit Fields */
-#define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
-#define SIM_FCFG2_MAXADDR1_SHIFT 16
-#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
-#define SIM_FCFG2_PFLSH_MASK 0x800000u
-#define SIM_FCFG2_PFLSH_SHIFT 23
-#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
-#define SIM_FCFG2_MAXADDR0_SHIFT 24
-#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
-/* UIDH Bit Fields */
-#define SIM_UIDH_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDH_UID_SHIFT 0
-#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
-/* UIDMH Bit Fields */
-#define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDMH_UID_SHIFT 0
-#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
-/* UIDML Bit Fields */
-#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDML_UID_SHIFT 0
-#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
-/* UIDL Bit Fields */
-#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDL_UID_SHIFT 0
-#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
-
-/*!
- * @}
- */ /* end of group SIM_Register_Masks */
-
-
-/* SIM - Peripheral instance base addresses */
-/** Peripheral SIM base address */
-#define SIM_BASE (0x40047000u)
-/** Peripheral SIM base pointer */
-#define SIM ((SIM_Type *)SIM_BASE)
-#define SIM_BASE_PTR (SIM)
-/** Array initializer of SIM peripheral base pointers */
-#define SIM_BASES { SIM }
-
-/* ----------------------------------------------------------------------------
- -- SIM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
- * @{
- */
-
-
-/* SIM - Register instance definitions */
-/* SIM */
-#define SIM_SOPT1 SIM_SOPT1_REG(SIM)
-#define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM)
-#define SIM_SOPT2 SIM_SOPT2_REG(SIM)
-#define SIM_SOPT4 SIM_SOPT4_REG(SIM)
-#define SIM_SOPT5 SIM_SOPT5_REG(SIM)
-#define SIM_SOPT7 SIM_SOPT7_REG(SIM)
-#define SIM_SDID SIM_SDID_REG(SIM)
-#define SIM_SCGC1 SIM_SCGC1_REG(SIM)
-#define SIM_SCGC2 SIM_SCGC2_REG(SIM)
-#define SIM_SCGC3 SIM_SCGC3_REG(SIM)
-#define SIM_SCGC4 SIM_SCGC4_REG(SIM)
-#define SIM_SCGC5 SIM_SCGC5_REG(SIM)
-#define SIM_SCGC6 SIM_SCGC6_REG(SIM)
-#define SIM_SCGC7 SIM_SCGC7_REG(SIM)
-#define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM)
-#define SIM_CLKDIV2 SIM_CLKDIV2_REG(SIM)
-#define SIM_FCFG1 SIM_FCFG1_REG(SIM)
-#define SIM_FCFG2 SIM_FCFG2_REG(SIM)
-#define SIM_UIDH SIM_UIDH_REG(SIM)
-#define SIM_UIDMH SIM_UIDMH_REG(SIM)
-#define SIM_UIDML SIM_UIDML_REG(SIM)
-#define SIM_UIDL SIM_UIDL_REG(SIM)
-
-/*!
- * @}
- */ /* end of group SIM_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group SIM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- SMC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
- * @{
- */
-
-/** SMC - Register Layout Typedef */
-typedef struct {
- __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
- __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
- __IO uint8_t VLLSCTRL; /**< VLLS Control register, offset: 0x2 */
- __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
-} SMC_Type, *SMC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- SMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
- * @{
- */
-
-
-/* SMC - Register accessors */
-#define SMC_PMPROT_REG(base) ((base)->PMPROT)
-#define SMC_PMCTRL_REG(base) ((base)->PMCTRL)
-#define SMC_VLLSCTRL_REG(base) ((base)->VLLSCTRL)
-#define SMC_PMSTAT_REG(base) ((base)->PMSTAT)
-
-/*!
- * @}
- */ /* end of group SMC_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- SMC Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SMC_Register_Masks SMC Register Masks
- * @{
- */
-
-/* PMPROT Bit Fields */
-#define SMC_PMPROT_AVLLS_MASK 0x2u
-#define SMC_PMPROT_AVLLS_SHIFT 1
-#define SMC_PMPROT_ALLS_MASK 0x8u
-#define SMC_PMPROT_ALLS_SHIFT 3
-#define SMC_PMPROT_AVLP_MASK 0x20u
-#define SMC_PMPROT_AVLP_SHIFT 5
-/* PMCTRL Bit Fields */
-#define SMC_PMCTRL_STOPM_MASK 0x7u
-#define SMC_PMCTRL_STOPM_SHIFT 0
-#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
-#define SMC_PMCTRL_STOPA_MASK 0x8u
-#define SMC_PMCTRL_STOPA_SHIFT 3
-#define SMC_PMCTRL_RUNM_MASK 0x60u
-#define SMC_PMCTRL_RUNM_SHIFT 5
-#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
-#define SMC_PMCTRL_LPWUI_MASK 0x80u
-#define SMC_PMCTRL_LPWUI_SHIFT 7
-/* VLLSCTRL Bit Fields */
-#define SMC_VLLSCTRL_VLLSM_MASK 0x7u
-#define SMC_VLLSCTRL_VLLSM_SHIFT 0
-#define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
-#define SMC_VLLSCTRL_PORPO_MASK 0x20u
-#define SMC_VLLSCTRL_PORPO_SHIFT 5
-/* PMSTAT Bit Fields */
-#define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
-#define SMC_PMSTAT_PMSTAT_SHIFT 0
-#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
-
-/*!
- * @}
- */ /* end of group SMC_Register_Masks */
-
-
-/* SMC - Peripheral instance base addresses */
-/** Peripheral SMC base address */
-#define SMC_BASE (0x4007E000u)
-/** Peripheral SMC base pointer */
-#define SMC ((SMC_Type *)SMC_BASE)
-#define SMC_BASE_PTR (SMC)
-/** Array initializer of SMC peripheral base pointers */
-#define SMC_BASES { SMC }
-
-/* ----------------------------------------------------------------------------
- -- SMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
- * @{
- */
-
-
-/* SMC - Register instance definitions */
-/* SMC */
-#define SMC_PMPROT SMC_PMPROT_REG(SMC)
-#define SMC_PMCTRL SMC_PMCTRL_REG(SMC)
-#define SMC_VLLSCTRL SMC_VLLSCTRL_REG(SMC)
-#define SMC_PMSTAT SMC_PMSTAT_REG(SMC)
-
-/*!
- * @}
- */ /* end of group SMC_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group SMC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- SPI Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
- * @{
- */
-
-/** SPI - Register Layout Typedef */
-typedef struct {
- __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
- uint8_t RESERVED_0[4];
- __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
- union { /* offset: 0xC */
- __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
- __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
- };
- uint8_t RESERVED_1[24];
- __IO uint32_t SR; /**< Status Register, offset: 0x2C */
- __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
- union { /* offset: 0x34 */
- __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
- __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
- };
- __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
- __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */
- __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */
- __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */
- __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */
- uint8_t RESERVED_2[48];
- __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */
- __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
- __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
- __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
-} SPI_Type, *SPI_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- SPI - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
- * @{
- */
-
-
-/* SPI - Register accessors */
-#define SPI_MCR_REG(base) ((base)->MCR)
-#define SPI_TCR_REG(base) ((base)->TCR)
-#define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2])
-#define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2])
-#define SPI_SR_REG(base) ((base)->SR)
-#define SPI_RSER_REG(base) ((base)->RSER)
-#define SPI_PUSHR_REG(base) ((base)->PUSHR)
-#define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE)
-#define SPI_POPR_REG(base) ((base)->POPR)
-#define SPI_TXFR0_REG(base) ((base)->TXFR0)
-#define SPI_TXFR1_REG(base) ((base)->TXFR1)
-#define SPI_TXFR2_REG(base) ((base)->TXFR2)
-#define SPI_TXFR3_REG(base) ((base)->TXFR3)
-#define SPI_RXFR0_REG(base) ((base)->RXFR0)
-#define SPI_RXFR1_REG(base) ((base)->RXFR1)
-#define SPI_RXFR2_REG(base) ((base)->RXFR2)
-#define SPI_RXFR3_REG(base) ((base)->RXFR3)
-
-/*!
- * @}
- */ /* end of group SPI_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- SPI Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SPI_Register_Masks SPI Register Masks
- * @{
- */
-
-/* MCR Bit Fields */
-#define SPI_MCR_HALT_MASK 0x1u
-#define SPI_MCR_HALT_SHIFT 0
-#define SPI_MCR_SMPL_PT_MASK 0x300u
-#define SPI_MCR_SMPL_PT_SHIFT 8
-#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
-#define SPI_MCR_CLR_RXF_MASK 0x400u
-#define SPI_MCR_CLR_RXF_SHIFT 10
-#define SPI_MCR_CLR_TXF_MASK 0x800u
-#define SPI_MCR_CLR_TXF_SHIFT 11
-#define SPI_MCR_DIS_RXF_MASK 0x1000u
-#define SPI_MCR_DIS_RXF_SHIFT 12
-#define SPI_MCR_DIS_TXF_MASK 0x2000u
-#define SPI_MCR_DIS_TXF_SHIFT 13
-#define SPI_MCR_MDIS_MASK 0x4000u
-#define SPI_MCR_MDIS_SHIFT 14
-#define SPI_MCR_DOZE_MASK 0x8000u
-#define SPI_MCR_DOZE_SHIFT 15
-#define SPI_MCR_PCSIS_MASK 0x3F0000u
-#define SPI_MCR_PCSIS_SHIFT 16
-#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
-#define SPI_MCR_ROOE_MASK 0x1000000u
-#define SPI_MCR_ROOE_SHIFT 24
-#define SPI_MCR_PCSSE_MASK 0x2000000u
-#define SPI_MCR_PCSSE_SHIFT 25
-#define SPI_MCR_MTFE_MASK 0x4000000u
-#define SPI_MCR_MTFE_SHIFT 26
-#define SPI_MCR_FRZ_MASK 0x8000000u
-#define SPI_MCR_FRZ_SHIFT 27
-#define SPI_MCR_DCONF_MASK 0x30000000u
-#define SPI_MCR_DCONF_SHIFT 28
-#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
-#define SPI_MCR_CONT_SCKE_MASK 0x40000000u
-#define SPI_MCR_CONT_SCKE_SHIFT 30
-#define SPI_MCR_MSTR_MASK 0x80000000u
-#define SPI_MCR_MSTR_SHIFT 31
-/* TCR Bit Fields */
-#define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
-#define SPI_TCR_SPI_TCNT_SHIFT 16
-#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
-/* CTAR Bit Fields */
-#define SPI_CTAR_BR_MASK 0xFu
-#define SPI_CTAR_BR_SHIFT 0
-#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
-#define SPI_CTAR_DT_MASK 0xF0u
-#define SPI_CTAR_DT_SHIFT 4
-#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
-#define SPI_CTAR_ASC_MASK 0xF00u
-#define SPI_CTAR_ASC_SHIFT 8
-#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
-#define SPI_CTAR_CSSCK_MASK 0xF000u
-#define SPI_CTAR_CSSCK_SHIFT 12
-#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
-#define SPI_CTAR_PBR_MASK 0x30000u
-#define SPI_CTAR_PBR_SHIFT 16
-#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
-#define SPI_CTAR_PDT_MASK 0xC0000u
-#define SPI_CTAR_PDT_SHIFT 18
-#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
-#define SPI_CTAR_PASC_MASK 0x300000u
-#define SPI_CTAR_PASC_SHIFT 20
-#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
-#define SPI_CTAR_PCSSCK_MASK 0xC00000u
-#define SPI_CTAR_PCSSCK_SHIFT 22
-#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
-#define SPI_CTAR_LSBFE_MASK 0x1000000u
-#define SPI_CTAR_LSBFE_SHIFT 24
-#define SPI_CTAR_CPHA_MASK 0x2000000u
-#define SPI_CTAR_CPHA_SHIFT 25
-#define SPI_CTAR_CPOL_MASK 0x4000000u
-#define SPI_CTAR_CPOL_SHIFT 26
-#define SPI_CTAR_FMSZ_MASK 0x78000000u
-#define SPI_CTAR_FMSZ_SHIFT 27
-#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
-#define SPI_CTAR_DBR_MASK 0x80000000u
-#define SPI_CTAR_DBR_SHIFT 31
-/* CTAR_SLAVE Bit Fields */
-#define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
-#define SPI_CTAR_SLAVE_CPHA_SHIFT 25
-#define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
-#define SPI_CTAR_SLAVE_CPOL_SHIFT 26
-#define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
-#define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
-#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
-/* SR Bit Fields */
-#define SPI_SR_POPNXTPTR_MASK 0xFu
-#define SPI_SR_POPNXTPTR_SHIFT 0
-#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
-#define SPI_SR_RXCTR_MASK 0xF0u
-#define SPI_SR_RXCTR_SHIFT 4
-#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
-#define SPI_SR_TXNXTPTR_MASK 0xF00u
-#define SPI_SR_TXNXTPTR_SHIFT 8
-#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
-#define SPI_SR_TXCTR_MASK 0xF000u
-#define SPI_SR_TXCTR_SHIFT 12
-#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
-#define SPI_SR_RFDF_MASK 0x20000u
-#define SPI_SR_RFDF_SHIFT 17
-#define SPI_SR_RFOF_MASK 0x80000u
-#define SPI_SR_RFOF_SHIFT 19
-#define SPI_SR_TFFF_MASK 0x2000000u
-#define SPI_SR_TFFF_SHIFT 25
-#define SPI_SR_TFUF_MASK 0x8000000u
-#define SPI_SR_TFUF_SHIFT 27
-#define SPI_SR_EOQF_MASK 0x10000000u
-#define SPI_SR_EOQF_SHIFT 28
-#define SPI_SR_TXRXS_MASK 0x40000000u
-#define SPI_SR_TXRXS_SHIFT 30
-#define SPI_SR_TCF_MASK 0x80000000u
-#define SPI_SR_TCF_SHIFT 31
-/* RSER Bit Fields */
-#define SPI_RSER_RFDF_DIRS_MASK 0x10000u
-#define SPI_RSER_RFDF_DIRS_SHIFT 16
-#define SPI_RSER_RFDF_RE_MASK 0x20000u
-#define SPI_RSER_RFDF_RE_SHIFT 17
-#define SPI_RSER_RFOF_RE_MASK 0x80000u
-#define SPI_RSER_RFOF_RE_SHIFT 19
-#define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
-#define SPI_RSER_TFFF_DIRS_SHIFT 24
-#define SPI_RSER_TFFF_RE_MASK 0x2000000u
-#define SPI_RSER_TFFF_RE_SHIFT 25
-#define SPI_RSER_TFUF_RE_MASK 0x8000000u
-#define SPI_RSER_TFUF_RE_SHIFT 27
-#define SPI_RSER_EOQF_RE_MASK 0x10000000u
-#define SPI_RSER_EOQF_RE_SHIFT 28
-#define SPI_RSER_TCF_RE_MASK 0x80000000u
-#define SPI_RSER_TCF_RE_SHIFT 31
-/* PUSHR Bit Fields */
-#define SPI_PUSHR_TXDATA_MASK 0xFFFFu
-#define SPI_PUSHR_TXDATA_SHIFT 0
-#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
-#define SPI_PUSHR_PCS_MASK 0x3F0000u
-#define SPI_PUSHR_PCS_SHIFT 16
-#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
-#define SPI_PUSHR_CTCNT_MASK 0x4000000u
-#define SPI_PUSHR_CTCNT_SHIFT 26
-#define SPI_PUSHR_EOQ_MASK 0x8000000u
-#define SPI_PUSHR_EOQ_SHIFT 27
-#define SPI_PUSHR_CTAS_MASK 0x70000000u
-#define SPI_PUSHR_CTAS_SHIFT 28
-#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
-#define SPI_PUSHR_CONT_MASK 0x80000000u
-#define SPI_PUSHR_CONT_SHIFT 31
-/* PUSHR_SLAVE Bit Fields */
-#define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
-#define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
-#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
-/* POPR Bit Fields */
-#define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_POPR_RXDATA_SHIFT 0
-#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
-/* TXFR0 Bit Fields */
-#define SPI_TXFR0_TXDATA_MASK 0xFFFFu
-#define SPI_TXFR0_TXDATA_SHIFT 0
-#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
-#define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
-#define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
-#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
-/* TXFR1 Bit Fields */
-#define SPI_TXFR1_TXDATA_MASK 0xFFFFu
-#define SPI_TXFR1_TXDATA_SHIFT 0
-#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
-#define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
-#define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
-#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
-/* TXFR2 Bit Fields */
-#define SPI_TXFR2_TXDATA_MASK 0xFFFFu
-#define SPI_TXFR2_TXDATA_SHIFT 0
-#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
-#define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
-#define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
-#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
-/* TXFR3 Bit Fields */
-#define SPI_TXFR3_TXDATA_MASK 0xFFFFu
-#define SPI_TXFR3_TXDATA_SHIFT 0
-#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
-#define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
-#define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
-#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
-/* RXFR0 Bit Fields */
-#define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_RXFR0_RXDATA_SHIFT 0
-#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
-/* RXFR1 Bit Fields */
-#define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_RXFR1_RXDATA_SHIFT 0
-#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
-/* RXFR2 Bit Fields */
-#define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_RXFR2_RXDATA_SHIFT 0
-#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
-/* RXFR3 Bit Fields */
-#define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_RXFR3_RXDATA_SHIFT 0
-#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
-
-/*!
- * @}
- */ /* end of group SPI_Register_Masks */
-
-
-/* SPI - Peripheral instance base addresses */
-/** Peripheral SPI0 base address */
-#define SPI0_BASE (0x4002C000u)
-/** Peripheral SPI0 base pointer */
-#define SPI0 ((SPI_Type *)SPI0_BASE)
-#define SPI0_BASE_PTR (SPI0)
-/** Peripheral SPI1 base address */
-#define SPI1_BASE (0x4002D000u)
-/** Peripheral SPI1 base pointer */
-#define SPI1 ((SPI_Type *)SPI1_BASE)
-#define SPI1_BASE_PTR (SPI1)
-/** Peripheral SPI2 base address */
-#define SPI2_BASE (0x400AC000u)
-/** Peripheral SPI2 base pointer */
-#define SPI2 ((SPI_Type *)SPI2_BASE)
-#define SPI2_BASE_PTR (SPI2)
-/** Array initializer of SPI peripheral base pointers */
-#define SPI_BASES { SPI0, SPI1, SPI2 }
-
-/* ----------------------------------------------------------------------------
- -- SPI - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
- * @{
- */
-
-
-/* SPI - Register instance definitions */
-/* SPI0 */
-#define SPI0_MCR SPI_MCR_REG(SPI0)
-#define SPI0_TCR SPI_TCR_REG(SPI0)
-#define SPI0_CTAR0 SPI_CTAR_REG(SPI0,0)
-#define SPI0_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI0,0)
-#define SPI0_CTAR1 SPI_CTAR_REG(SPI0,1)
-#define SPI0_SR SPI_SR_REG(SPI0)
-#define SPI0_RSER SPI_RSER_REG(SPI0)
-#define SPI0_PUSHR SPI_PUSHR_REG(SPI0)
-#define SPI0_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI0)
-#define SPI0_POPR SPI_POPR_REG(SPI0)
-#define SPI0_TXFR0 SPI_TXFR0_REG(SPI0)
-#define SPI0_TXFR1 SPI_TXFR1_REG(SPI0)
-#define SPI0_TXFR2 SPI_TXFR2_REG(SPI0)
-#define SPI0_TXFR3 SPI_TXFR3_REG(SPI0)
-#define SPI0_RXFR0 SPI_RXFR0_REG(SPI0)
-#define SPI0_RXFR1 SPI_RXFR1_REG(SPI0)
-#define SPI0_RXFR2 SPI_RXFR2_REG(SPI0)
-#define SPI0_RXFR3 SPI_RXFR3_REG(SPI0)
-/* SPI1 */
-#define SPI1_MCR SPI_MCR_REG(SPI1)
-#define SPI1_TCR SPI_TCR_REG(SPI1)
-#define SPI1_CTAR0 SPI_CTAR_REG(SPI1,0)
-#define SPI1_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI1,0)
-#define SPI1_CTAR1 SPI_CTAR_REG(SPI1,1)
-#define SPI1_SR SPI_SR_REG(SPI1)
-#define SPI1_RSER SPI_RSER_REG(SPI1)
-#define SPI1_PUSHR SPI_PUSHR_REG(SPI1)
-#define SPI1_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI1)
-#define SPI1_POPR SPI_POPR_REG(SPI1)
-#define SPI1_TXFR0 SPI_TXFR0_REG(SPI1)
-#define SPI1_TXFR1 SPI_TXFR1_REG(SPI1)
-#define SPI1_TXFR2 SPI_TXFR2_REG(SPI1)
-#define SPI1_TXFR3 SPI_TXFR3_REG(SPI1)
-#define SPI1_RXFR0 SPI_RXFR0_REG(SPI1)
-#define SPI1_RXFR1 SPI_RXFR1_REG(SPI1)
-#define SPI1_RXFR2 SPI_RXFR2_REG(SPI1)
-#define SPI1_RXFR3 SPI_RXFR3_REG(SPI1)
-/* SPI2 */
-#define SPI2_MCR SPI_MCR_REG(SPI2)
-#define SPI2_TCR SPI_TCR_REG(SPI2)
-#define SPI2_CTAR0 SPI_CTAR_REG(SPI2,0)
-#define SPI2_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI2,0)
-#define SPI2_CTAR1 SPI_CTAR_REG(SPI2,1)
-#define SPI2_SR SPI_SR_REG(SPI2)
-#define SPI2_RSER SPI_RSER_REG(SPI2)
-#define SPI2_PUSHR SPI_PUSHR_REG(SPI2)
-#define SPI2_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI2)
-#define SPI2_POPR SPI_POPR_REG(SPI2)
-#define SPI2_TXFR0 SPI_TXFR0_REG(SPI2)
-#define SPI2_TXFR1 SPI_TXFR1_REG(SPI2)
-#define SPI2_TXFR2 SPI_TXFR2_REG(SPI2)
-#define SPI2_TXFR3 SPI_TXFR3_REG(SPI2)
-#define SPI2_RXFR0 SPI_RXFR0_REG(SPI2)
-#define SPI2_RXFR1 SPI_RXFR1_REG(SPI2)
-#define SPI2_RXFR2 SPI_RXFR2_REG(SPI2)
-#define SPI2_RXFR3 SPI_RXFR3_REG(SPI2)
-
-/* SPI - Register array accessors */
-#define SPI0_CTAR(index2) SPI_CTAR_REG(SPI0,index2)
-#define SPI1_CTAR(index2) SPI_CTAR_REG(SPI1,index2)
-#define SPI2_CTAR(index2) SPI_CTAR_REG(SPI2,index2)
-#define SPI0_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI0,index2)
-#define SPI1_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI1,index2)
-#define SPI2_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI2,index2)
-
-/*!
- * @}
- */ /* end of group SPI_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group SPI_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- UART Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
- * @{
- */
-
-/** UART - Register Layout Typedef */
-typedef struct {
- __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
- __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
- __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
- __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
- __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
- __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
- __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
- __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
- __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
- __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
- __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
- __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
- __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
- __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
- __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
- uint8_t RESERVED_0[1];
- __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
- __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
- __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
- __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
- __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
- __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
- __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
- uint8_t RESERVED_1[1];
- __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
- __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
- __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
- union { /* offset: 0x1B */
- __IO uint8_t WP7816_T_TYPE0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
- __IO uint8_t WP7816_T_TYPE1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
- };
- __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
- __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
- __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
- __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
-} UART_Type, *UART_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- UART - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
- * @{
- */
-
-
-/* UART - Register accessors */
-#define UART_BDH_REG(base) ((base)->BDH)
-#define UART_BDL_REG(base) ((base)->BDL)
-#define UART_C1_REG(base) ((base)->C1)
-#define UART_C2_REG(base) ((base)->C2)
-#define UART_S1_REG(base) ((base)->S1)
-#define UART_S2_REG(base) ((base)->S2)
-#define UART_C3_REG(base) ((base)->C3)
-#define UART_D_REG(base) ((base)->D)
-#define UART_MA1_REG(base) ((base)->MA1)
-#define UART_MA2_REG(base) ((base)->MA2)
-#define UART_C4_REG(base) ((base)->C4)
-#define UART_C5_REG(base) ((base)->C5)
-#define UART_ED_REG(base) ((base)->ED)
-#define UART_MODEM_REG(base) ((base)->MODEM)
-#define UART_IR_REG(base) ((base)->IR)
-#define UART_PFIFO_REG(base) ((base)->PFIFO)
-#define UART_CFIFO_REG(base) ((base)->CFIFO)
-#define UART_SFIFO_REG(base) ((base)->SFIFO)
-#define UART_TWFIFO_REG(base) ((base)->TWFIFO)
-#define UART_TCFIFO_REG(base) ((base)->TCFIFO)
-#define UART_RWFIFO_REG(base) ((base)->RWFIFO)
-#define UART_RCFIFO_REG(base) ((base)->RCFIFO)
-#define UART_C7816_REG(base) ((base)->C7816)
-#define UART_IE7816_REG(base) ((base)->IE7816)
-#define UART_IS7816_REG(base) ((base)->IS7816)
-#define UART_WP7816_T_TYPE0_REG(base) ((base)->WP7816_T_TYPE0)
-#define UART_WP7816_T_TYPE1_REG(base) ((base)->WP7816_T_TYPE1)
-#define UART_WN7816_REG(base) ((base)->WN7816)
-#define UART_WF7816_REG(base) ((base)->WF7816)
-#define UART_ET7816_REG(base) ((base)->ET7816)
-#define UART_TL7816_REG(base) ((base)->TL7816)
-
-/*!
- * @}
- */ /* end of group UART_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- UART Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup UART_Register_Masks UART Register Masks
- * @{
- */
-
-/* BDH Bit Fields */
-#define UART_BDH_SBR_MASK 0x1Fu
-#define UART_BDH_SBR_SHIFT 0
-#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
-#define UART_BDH_SBNS_MASK 0x20u
-#define UART_BDH_SBNS_SHIFT 5
-#define UART_BDH_RXEDGIE_MASK 0x40u
-#define UART_BDH_RXEDGIE_SHIFT 6
-#define UART_BDH_LBKDIE_MASK 0x80u
-#define UART_BDH_LBKDIE_SHIFT 7
-/* BDL Bit Fields */
-#define UART_BDL_SBR_MASK 0xFFu
-#define UART_BDL_SBR_SHIFT 0
-#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
-/* C1 Bit Fields */
-#define UART_C1_PT_MASK 0x1u
-#define UART_C1_PT_SHIFT 0
-#define UART_C1_PE_MASK 0x2u
-#define UART_C1_PE_SHIFT 1
-#define UART_C1_ILT_MASK 0x4u
-#define UART_C1_ILT_SHIFT 2
-#define UART_C1_WAKE_MASK 0x8u
-#define UART_C1_WAKE_SHIFT 3
-#define UART_C1_M_MASK 0x10u
-#define UART_C1_M_SHIFT 4
-#define UART_C1_RSRC_MASK 0x20u
-#define UART_C1_RSRC_SHIFT 5
-#define UART_C1_UARTSWAI_MASK 0x40u
-#define UART_C1_UARTSWAI_SHIFT 6
-#define UART_C1_LOOPS_MASK 0x80u
-#define UART_C1_LOOPS_SHIFT 7
-/* C2 Bit Fields */
-#define UART_C2_SBK_MASK 0x1u
-#define UART_C2_SBK_SHIFT 0
-#define UART_C2_RWU_MASK 0x2u
-#define UART_C2_RWU_SHIFT 1
-#define UART_C2_RE_MASK 0x4u
-#define UART_C2_RE_SHIFT 2
-#define UART_C2_TE_MASK 0x8u
-#define UART_C2_TE_SHIFT 3
-#define UART_C2_ILIE_MASK 0x10u
-#define UART_C2_ILIE_SHIFT 4
-#define UART_C2_RIE_MASK 0x20u
-#define UART_C2_RIE_SHIFT 5
-#define UART_C2_TCIE_MASK 0x40u
-#define UART_C2_TCIE_SHIFT 6
-#define UART_C2_TIE_MASK 0x80u
-#define UART_C2_TIE_SHIFT 7
-/* S1 Bit Fields */
-#define UART_S1_PF_MASK 0x1u
-#define UART_S1_PF_SHIFT 0
-#define UART_S1_FE_MASK 0x2u
-#define UART_S1_FE_SHIFT 1
-#define UART_S1_NF_MASK 0x4u
-#define UART_S1_NF_SHIFT 2
-#define UART_S1_OR_MASK 0x8u
-#define UART_S1_OR_SHIFT 3
-#define UART_S1_IDLE_MASK 0x10u
-#define UART_S1_IDLE_SHIFT 4
-#define UART_S1_RDRF_MASK 0x20u
-#define UART_S1_RDRF_SHIFT 5
-#define UART_S1_TC_MASK 0x40u
-#define UART_S1_TC_SHIFT 6
-#define UART_S1_TDRE_MASK 0x80u
-#define UART_S1_TDRE_SHIFT 7
-/* S2 Bit Fields */
-#define UART_S2_RAF_MASK 0x1u
-#define UART_S2_RAF_SHIFT 0
-#define UART_S2_LBKDE_MASK 0x2u
-#define UART_S2_LBKDE_SHIFT 1
-#define UART_S2_BRK13_MASK 0x4u
-#define UART_S2_BRK13_SHIFT 2
-#define UART_S2_RWUID_MASK 0x8u
-#define UART_S2_RWUID_SHIFT 3
-#define UART_S2_RXINV_MASK 0x10u
-#define UART_S2_RXINV_SHIFT 4
-#define UART_S2_MSBF_MASK 0x20u
-#define UART_S2_MSBF_SHIFT 5
-#define UART_S2_RXEDGIF_MASK 0x40u
-#define UART_S2_RXEDGIF_SHIFT 6
-#define UART_S2_LBKDIF_MASK 0x80u
-#define UART_S2_LBKDIF_SHIFT 7
-/* C3 Bit Fields */
-#define UART_C3_PEIE_MASK 0x1u
-#define UART_C3_PEIE_SHIFT 0
-#define UART_C3_FEIE_MASK 0x2u
-#define UART_C3_FEIE_SHIFT 1
-#define UART_C3_NEIE_MASK 0x4u
-#define UART_C3_NEIE_SHIFT 2
-#define UART_C3_ORIE_MASK 0x8u
-#define UART_C3_ORIE_SHIFT 3
-#define UART_C3_TXINV_MASK 0x10u
-#define UART_C3_TXINV_SHIFT 4
-#define UART_C3_TXDIR_MASK 0x20u
-#define UART_C3_TXDIR_SHIFT 5
-#define UART_C3_T8_MASK 0x40u
-#define UART_C3_T8_SHIFT 6
-#define UART_C3_R8_MASK 0x80u
-#define UART_C3_R8_SHIFT 7
-/* D Bit Fields */
-#define UART_D_RT_MASK 0xFFu
-#define UART_D_RT_SHIFT 0
-#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
-/* MA1 Bit Fields */
-#define UART_MA1_MA_MASK 0xFFu
-#define UART_MA1_MA_SHIFT 0
-#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
-/* MA2 Bit Fields */
-#define UART_MA2_MA_MASK 0xFFu
-#define UART_MA2_MA_SHIFT 0
-#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
-/* C4 Bit Fields */
-#define UART_C4_BRFA_MASK 0x1Fu
-#define UART_C4_BRFA_SHIFT 0
-#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
-#define UART_C4_M10_MASK 0x20u
-#define UART_C4_M10_SHIFT 5
-#define UART_C4_MAEN2_MASK 0x40u
-#define UART_C4_MAEN2_SHIFT 6
-#define UART_C4_MAEN1_MASK 0x80u
-#define UART_C4_MAEN1_SHIFT 7
-/* C5 Bit Fields */
-#define UART_C5_LBKDDMAS_MASK 0x8u
-#define UART_C5_LBKDDMAS_SHIFT 3
-#define UART_C5_ILDMAS_MASK 0x10u
-#define UART_C5_ILDMAS_SHIFT 4
-#define UART_C5_RDMAS_MASK 0x20u
-#define UART_C5_RDMAS_SHIFT 5
-#define UART_C5_TCDMAS_MASK 0x40u
-#define UART_C5_TCDMAS_SHIFT 6
-#define UART_C5_TDMAS_MASK 0x80u
-#define UART_C5_TDMAS_SHIFT 7
-/* ED Bit Fields */
-#define UART_ED_PARITYE_MASK 0x40u
-#define UART_ED_PARITYE_SHIFT 6
-#define UART_ED_NOISY_MASK 0x80u
-#define UART_ED_NOISY_SHIFT 7
-/* MODEM Bit Fields */
-#define UART_MODEM_TXCTSE_MASK 0x1u
-#define UART_MODEM_TXCTSE_SHIFT 0
-#define UART_MODEM_TXRTSE_MASK 0x2u
-#define UART_MODEM_TXRTSE_SHIFT 1
-#define UART_MODEM_TXRTSPOL_MASK 0x4u
-#define UART_MODEM_TXRTSPOL_SHIFT 2
-#define UART_MODEM_RXRTSE_MASK 0x8u
-#define UART_MODEM_RXRTSE_SHIFT 3
-/* IR Bit Fields */
-#define UART_IR_TNP_MASK 0x3u
-#define UART_IR_TNP_SHIFT 0
-#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
-#define UART_IR_IREN_MASK 0x4u
-#define UART_IR_IREN_SHIFT 2
-/* PFIFO Bit Fields */
-#define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
-#define UART_PFIFO_RXFIFOSIZE_SHIFT 0
-#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
-#define UART_PFIFO_RXFE_MASK 0x8u
-#define UART_PFIFO_RXFE_SHIFT 3
-#define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
-#define UART_PFIFO_TXFIFOSIZE_SHIFT 4
-#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
-#define UART_PFIFO_TXFE_MASK 0x80u
-#define UART_PFIFO_TXFE_SHIFT 7
-/* CFIFO Bit Fields */
-#define UART_CFIFO_RXUFE_MASK 0x1u
-#define UART_CFIFO_RXUFE_SHIFT 0
-#define UART_CFIFO_TXOFE_MASK 0x2u
-#define UART_CFIFO_TXOFE_SHIFT 1
-#define UART_CFIFO_RXOFE_MASK 0x4u
-#define UART_CFIFO_RXOFE_SHIFT 2
-#define UART_CFIFO_RXFLUSH_MASK 0x40u
-#define UART_CFIFO_RXFLUSH_SHIFT 6
-#define UART_CFIFO_TXFLUSH_MASK 0x80u
-#define UART_CFIFO_TXFLUSH_SHIFT 7
-/* SFIFO Bit Fields */
-#define UART_SFIFO_RXUF_MASK 0x1u
-#define UART_SFIFO_RXUF_SHIFT 0
-#define UART_SFIFO_TXOF_MASK 0x2u
-#define UART_SFIFO_TXOF_SHIFT 1
-#define UART_SFIFO_RXOF_MASK 0x4u
-#define UART_SFIFO_RXOF_SHIFT 2
-#define UART_SFIFO_RXEMPT_MASK 0x40u
-#define UART_SFIFO_RXEMPT_SHIFT 6
-#define UART_SFIFO_TXEMPT_MASK 0x80u
-#define UART_SFIFO_TXEMPT_SHIFT 7
-/* TWFIFO Bit Fields */
-#define UART_TWFIFO_TXWATER_MASK 0xFFu
-#define UART_TWFIFO_TXWATER_SHIFT 0
-#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
-/* TCFIFO Bit Fields */
-#define UART_TCFIFO_TXCOUNT_MASK 0xFFu
-#define UART_TCFIFO_TXCOUNT_SHIFT 0
-#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
-/* RWFIFO Bit Fields */
-#define UART_RWFIFO_RXWATER_MASK 0xFFu
-#define UART_RWFIFO_RXWATER_SHIFT 0
-#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
-/* RCFIFO Bit Fields */
-#define UART_RCFIFO_RXCOUNT_MASK 0xFFu
-#define UART_RCFIFO_RXCOUNT_SHIFT 0
-#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
-/* C7816 Bit Fields */
-#define UART_C7816_ISO_7816E_MASK 0x1u
-#define UART_C7816_ISO_7816E_SHIFT 0
-#define UART_C7816_TTYPE_MASK 0x2u
-#define UART_C7816_TTYPE_SHIFT 1
-#define UART_C7816_INIT_MASK 0x4u
-#define UART_C7816_INIT_SHIFT 2
-#define UART_C7816_ANACK_MASK 0x8u
-#define UART_C7816_ANACK_SHIFT 3
-#define UART_C7816_ONACK_MASK 0x10u
-#define UART_C7816_ONACK_SHIFT 4
-/* IE7816 Bit Fields */
-#define UART_IE7816_RXTE_MASK 0x1u
-#define UART_IE7816_RXTE_SHIFT 0
-#define UART_IE7816_TXTE_MASK 0x2u
-#define UART_IE7816_TXTE_SHIFT 1
-#define UART_IE7816_GTVE_MASK 0x4u
-#define UART_IE7816_GTVE_SHIFT 2
-#define UART_IE7816_INITDE_MASK 0x10u
-#define UART_IE7816_INITDE_SHIFT 4
-#define UART_IE7816_BWTE_MASK 0x20u
-#define UART_IE7816_BWTE_SHIFT 5
-#define UART_IE7816_CWTE_MASK 0x40u
-#define UART_IE7816_CWTE_SHIFT 6
-#define UART_IE7816_WTE_MASK 0x80u
-#define UART_IE7816_WTE_SHIFT 7
-/* IS7816 Bit Fields */
-#define UART_IS7816_RXT_MASK 0x1u
-#define UART_IS7816_RXT_SHIFT 0
-#define UART_IS7816_TXT_MASK 0x2u
-#define UART_IS7816_TXT_SHIFT 1
-#define UART_IS7816_GTV_MASK 0x4u
-#define UART_IS7816_GTV_SHIFT 2
-#define UART_IS7816_INITD_MASK 0x10u
-#define UART_IS7816_INITD_SHIFT 4
-#define UART_IS7816_BWT_MASK 0x20u
-#define UART_IS7816_BWT_SHIFT 5
-#define UART_IS7816_CWT_MASK 0x40u
-#define UART_IS7816_CWT_SHIFT 6
-#define UART_IS7816_WT_MASK 0x80u
-#define UART_IS7816_WT_SHIFT 7
-/* WP7816_T_TYPE0 Bit Fields */
-#define UART_WP7816_T_TYPE0_WI_MASK 0xFFu
-#define UART_WP7816_T_TYPE0_WI_SHIFT 0
-#define UART_WP7816_T_TYPE0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE0_WI_SHIFT))&UART_WP7816_T_TYPE0_WI_MASK)
-/* WP7816_T_TYPE1 Bit Fields */
-#define UART_WP7816_T_TYPE1_BWI_MASK 0xFu
-#define UART_WP7816_T_TYPE1_BWI_SHIFT 0
-#define UART_WP7816_T_TYPE1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_BWI_SHIFT))&UART_WP7816_T_TYPE1_BWI_MASK)
-#define UART_WP7816_T_TYPE1_CWI_MASK 0xF0u
-#define UART_WP7816_T_TYPE1_CWI_SHIFT 4
-#define UART_WP7816_T_TYPE1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_CWI_SHIFT))&UART_WP7816_T_TYPE1_CWI_MASK)
-/* WN7816 Bit Fields */
-#define UART_WN7816_GTN_MASK 0xFFu
-#define UART_WN7816_GTN_SHIFT 0
-#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
-/* WF7816 Bit Fields */
-#define UART_WF7816_GTFD_MASK 0xFFu
-#define UART_WF7816_GTFD_SHIFT 0
-#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
-/* ET7816 Bit Fields */
-#define UART_ET7816_RXTHRESHOLD_MASK 0xFu
-#define UART_ET7816_RXTHRESHOLD_SHIFT 0
-#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
-#define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
-#define UART_ET7816_TXTHRESHOLD_SHIFT 4
-#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
-/* TL7816 Bit Fields */
-#define UART_TL7816_TLEN_MASK 0xFFu
-#define UART_TL7816_TLEN_SHIFT 0
-#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
-
-/*!
- * @}
- */ /* end of group UART_Register_Masks */
-
-
-/* UART - Peripheral instance base addresses */
-/** Peripheral UART0 base address */
-#define UART0_BASE (0x4006A000u)
-/** Peripheral UART0 base pointer */
-#define UART0 ((UART_Type *)UART0_BASE)
-#define UART0_BASE_PTR (UART0)
-/** Peripheral UART1 base address */
-#define UART1_BASE (0x4006B000u)
-/** Peripheral UART1 base pointer */
-#define UART1 ((UART_Type *)UART1_BASE)
-#define UART1_BASE_PTR (UART1)
-/** Peripheral UART2 base address */
-#define UART2_BASE (0x4006C000u)
-/** Peripheral UART2 base pointer */
-#define UART2 ((UART_Type *)UART2_BASE)
-#define UART2_BASE_PTR (UART2)
-/** Peripheral UART3 base address */
-#define UART3_BASE (0x4006D000u)
-/** Peripheral UART3 base pointer */
-#define UART3 ((UART_Type *)UART3_BASE)
-#define UART3_BASE_PTR (UART3)
-/** Peripheral UART4 base address */
-#define UART4_BASE (0x400EA000u)
-/** Peripheral UART4 base pointer */
-#define UART4 ((UART_Type *)UART4_BASE)
-#define UART4_BASE_PTR (UART4)
-/** Peripheral UART5 base address */
-#define UART5_BASE (0x400EB000u)
-/** Peripheral UART5 base pointer */
-#define UART5 ((UART_Type *)UART5_BASE)
-#define UART5_BASE_PTR (UART5)
-/** Array initializer of UART peripheral base pointers */
-#define UART_BASES { UART0, UART1, UART2, UART3, UART4, UART5 }
-
-/* ----------------------------------------------------------------------------
- -- UART - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
- * @{
- */
-
-
-/* UART - Register instance definitions */
-/* UART0 */
-#define UART0_BDH UART_BDH_REG(UART0)
-#define UART0_BDL UART_BDL_REG(UART0)
-#define UART0_C1 UART_C1_REG(UART0)
-#define UART0_C2 UART_C2_REG(UART0)
-#define UART0_S1 UART_S1_REG(UART0)
-#define UART0_S2 UART_S2_REG(UART0)
-#define UART0_C3 UART_C3_REG(UART0)
-#define UART0_D UART_D_REG(UART0)
-#define UART0_MA1 UART_MA1_REG(UART0)
-#define UART0_MA2 UART_MA2_REG(UART0)
-#define UART0_C4 UART_C4_REG(UART0)
-#define UART0_C5 UART_C5_REG(UART0)
-#define UART0_ED UART_ED_REG(UART0)
-#define UART0_MODEM UART_MODEM_REG(UART0)
-#define UART0_IR UART_IR_REG(UART0)
-#define UART0_PFIFO UART_PFIFO_REG(UART0)
-#define UART0_CFIFO UART_CFIFO_REG(UART0)
-#define UART0_SFIFO UART_SFIFO_REG(UART0)
-#define UART0_TWFIFO UART_TWFIFO_REG(UART0)
-#define UART0_TCFIFO UART_TCFIFO_REG(UART0)
-#define UART0_RWFIFO UART_RWFIFO_REG(UART0)
-#define UART0_RCFIFO UART_RCFIFO_REG(UART0)
-#define UART0_C7816 UART_C7816_REG(UART0)
-#define UART0_IE7816 UART_IE7816_REG(UART0)
-#define UART0_IS7816 UART_IS7816_REG(UART0)
-#define UART0_WP7816T0 UART_WP7816_T_TYPE0_REG(UART0)
-#define UART0_WP7816T1 UART_WP7816_T_TYPE1_REG(UART0)
-#define UART0_WN7816 UART_WN7816_REG(UART0)
-#define UART0_WF7816 UART_WF7816_REG(UART0)
-#define UART0_ET7816 UART_ET7816_REG(UART0)
-#define UART0_TL7816 UART_TL7816_REG(UART0)
-/* UART1 */
-#define UART1_BDH UART_BDH_REG(UART1)
-#define UART1_BDL UART_BDL_REG(UART1)
-#define UART1_C1 UART_C1_REG(UART1)
-#define UART1_C2 UART_C2_REG(UART1)
-#define UART1_S1 UART_S1_REG(UART1)
-#define UART1_S2 UART_S2_REG(UART1)
-#define UART1_C3 UART_C3_REG(UART1)
-#define UART1_D UART_D_REG(UART1)
-#define UART1_MA1 UART_MA1_REG(UART1)
-#define UART1_MA2 UART_MA2_REG(UART1)
-#define UART1_C4 UART_C4_REG(UART1)
-#define UART1_C5 UART_C5_REG(UART1)
-#define UART1_ED UART_ED_REG(UART1)
-#define UART1_MODEM UART_MODEM_REG(UART1)
-#define UART1_IR UART_IR_REG(UART1)
-#define UART1_PFIFO UART_PFIFO_REG(UART1)
-#define UART1_CFIFO UART_CFIFO_REG(UART1)
-#define UART1_SFIFO UART_SFIFO_REG(UART1)
-#define UART1_TWFIFO UART_TWFIFO_REG(UART1)
-#define UART1_TCFIFO UART_TCFIFO_REG(UART1)
-#define UART1_RWFIFO UART_RWFIFO_REG(UART1)
-#define UART1_RCFIFO UART_RCFIFO_REG(UART1)
-/* UART2 */
-#define UART2_BDH UART_BDH_REG(UART2)
-#define UART2_BDL UART_BDL_REG(UART2)
-#define UART2_C1 UART_C1_REG(UART2)
-#define UART2_C2 UART_C2_REG(UART2)
-#define UART2_S1 UART_S1_REG(UART2)
-#define UART2_S2 UART_S2_REG(UART2)
-#define UART2_C3 UART_C3_REG(UART2)
-#define UART2_D UART_D_REG(UART2)
-#define UART2_MA1 UART_MA1_REG(UART2)
-#define UART2_MA2 UART_MA2_REG(UART2)
-#define UART2_C4 UART_C4_REG(UART2)
-#define UART2_C5 UART_C5_REG(UART2)
-#define UART2_ED UART_ED_REG(UART2)
-#define UART2_MODEM UART_MODEM_REG(UART2)
-#define UART2_IR UART_IR_REG(UART2)
-#define UART2_PFIFO UART_PFIFO_REG(UART2)
-#define UART2_CFIFO UART_CFIFO_REG(UART2)
-#define UART2_SFIFO UART_SFIFO_REG(UART2)
-#define UART2_TWFIFO UART_TWFIFO_REG(UART2)
-#define UART2_TCFIFO UART_TCFIFO_REG(UART2)
-#define UART2_RWFIFO UART_RWFIFO_REG(UART2)
-#define UART2_RCFIFO UART_RCFIFO_REG(UART2)
-/* UART3 */
-#define UART3_BDH UART_BDH_REG(UART3)
-#define UART3_BDL UART_BDL_REG(UART3)
-#define UART3_C1 UART_C1_REG(UART3)
-#define UART3_C2 UART_C2_REG(UART3)
-#define UART3_S1 UART_S1_REG(UART3)
-#define UART3_S2 UART_S2_REG(UART3)
-#define UART3_C3 UART_C3_REG(UART3)
-#define UART3_D UART_D_REG(UART3)
-#define UART3_MA1 UART_MA1_REG(UART3)
-#define UART3_MA2 UART_MA2_REG(UART3)
-#define UART3_C4 UART_C4_REG(UART3)
-#define UART3_C5 UART_C5_REG(UART3)
-#define UART3_ED UART_ED_REG(UART3)
-#define UART3_MODEM UART_MODEM_REG(UART3)
-#define UART3_IR UART_IR_REG(UART3)
-#define UART3_PFIFO UART_PFIFO_REG(UART3)
-#define UART3_CFIFO UART_CFIFO_REG(UART3)
-#define UART3_SFIFO UART_SFIFO_REG(UART3)
-#define UART3_TWFIFO UART_TWFIFO_REG(UART3)
-#define UART3_TCFIFO UART_TCFIFO_REG(UART3)
-#define UART3_RWFIFO UART_RWFIFO_REG(UART3)
-#define UART3_RCFIFO UART_RCFIFO_REG(UART3)
-/* UART4 */
-#define UART4_BDH UART_BDH_REG(UART4)
-#define UART4_BDL UART_BDL_REG(UART4)
-#define UART4_C1 UART_C1_REG(UART4)
-#define UART4_C2 UART_C2_REG(UART4)
-#define UART4_S1 UART_S1_REG(UART4)
-#define UART4_S2 UART_S2_REG(UART4)
-#define UART4_C3 UART_C3_REG(UART4)
-#define UART4_D UART_D_REG(UART4)
-#define UART4_MA1 UART_MA1_REG(UART4)
-#define UART4_MA2 UART_MA2_REG(UART4)
-#define UART4_C4 UART_C4_REG(UART4)
-#define UART4_C5 UART_C5_REG(UART4)
-#define UART4_ED UART_ED_REG(UART4)
-#define UART4_MODEM UART_MODEM_REG(UART4)
-#define UART4_IR UART_IR_REG(UART4)
-#define UART4_PFIFO UART_PFIFO_REG(UART4)
-#define UART4_CFIFO UART_CFIFO_REG(UART4)
-#define UART4_SFIFO UART_SFIFO_REG(UART4)
-#define UART4_TWFIFO UART_TWFIFO_REG(UART4)
-#define UART4_TCFIFO UART_TCFIFO_REG(UART4)
-#define UART4_RWFIFO UART_RWFIFO_REG(UART4)
-#define UART4_RCFIFO UART_RCFIFO_REG(UART4)
-/* UART5 */
-#define UART5_BDH UART_BDH_REG(UART5)
-#define UART5_BDL UART_BDL_REG(UART5)
-#define UART5_C1 UART_C1_REG(UART5)
-#define UART5_C2 UART_C2_REG(UART5)
-#define UART5_S1 UART_S1_REG(UART5)
-#define UART5_S2 UART_S2_REG(UART5)
-#define UART5_C3 UART_C3_REG(UART5)
-#define UART5_D UART_D_REG(UART5)
-#define UART5_MA1 UART_MA1_REG(UART5)
-#define UART5_MA2 UART_MA2_REG(UART5)
-#define UART5_C4 UART_C4_REG(UART5)
-#define UART5_C5 UART_C5_REG(UART5)
-#define UART5_ED UART_ED_REG(UART5)
-#define UART5_MODEM UART_MODEM_REG(UART5)
-#define UART5_IR UART_IR_REG(UART5)
-#define UART5_PFIFO UART_PFIFO_REG(UART5)
-#define UART5_CFIFO UART_CFIFO_REG(UART5)
-#define UART5_SFIFO UART_SFIFO_REG(UART5)
-#define UART5_TWFIFO UART_TWFIFO_REG(UART5)
-#define UART5_TCFIFO UART_TCFIFO_REG(UART5)
-#define UART5_RWFIFO UART_RWFIFO_REG(UART5)
-#define UART5_RCFIFO UART_RCFIFO_REG(UART5)
-
-/*!
- * @}
- */ /* end of group UART_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group UART_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- USB Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
- * @{
- */
-
-/** USB - Register Layout Typedef */
-typedef struct {
- __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
- uint8_t RESERVED_0[3];
- __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
- uint8_t RESERVED_1[3];
- __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
- uint8_t RESERVED_2[3];
- __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
- uint8_t RESERVED_3[3];
- __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
- uint8_t RESERVED_4[3];
- __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
- uint8_t RESERVED_5[3];
- __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
- uint8_t RESERVED_6[3];
- __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
- uint8_t RESERVED_7[99];
- __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
- uint8_t RESERVED_8[3];
- __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
- uint8_t RESERVED_9[3];
- __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
- uint8_t RESERVED_10[3];
- __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
- uint8_t RESERVED_11[3];
- __I uint8_t STAT; /**< Status register, offset: 0x90 */
- uint8_t RESERVED_12[3];
- __IO uint8_t CTL; /**< Control register, offset: 0x94 */
- uint8_t RESERVED_13[3];
- __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
- uint8_t RESERVED_14[3];
- __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
- uint8_t RESERVED_15[3];
- __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
- uint8_t RESERVED_16[3];
- __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
- uint8_t RESERVED_17[3];
- __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
- uint8_t RESERVED_18[3];
- __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
- uint8_t RESERVED_19[3];
- __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
- uint8_t RESERVED_20[3];
- __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
- uint8_t RESERVED_21[11];
- struct { /* offset: 0xC0, array step: 0x4 */
- __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
- uint8_t RESERVED_0[3];
- } ENDPOINT[16];
- __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
- uint8_t RESERVED_22[3];
- __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
- uint8_t RESERVED_23[3];
- __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
- uint8_t RESERVED_24[3];
- __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
- uint8_t RESERVED_25[7];
- __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
- uint8_t RESERVED_26[43];
- __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
- uint8_t RESERVED_27[3];
- __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
- uint8_t RESERVED_28[23];
- __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
-} USB_Type, *USB_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- USB - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
- * @{
- */
-
-
-/* USB - Register accessors */
-#define USB_PERID_REG(base) ((base)->PERID)
-#define USB_IDCOMP_REG(base) ((base)->IDCOMP)
-#define USB_REV_REG(base) ((base)->REV)
-#define USB_ADDINFO_REG(base) ((base)->ADDINFO)
-#define USB_OTGISTAT_REG(base) ((base)->OTGISTAT)
-#define USB_OTGICR_REG(base) ((base)->OTGICR)
-#define USB_OTGSTAT_REG(base) ((base)->OTGSTAT)
-#define USB_OTGCTL_REG(base) ((base)->OTGCTL)
-#define USB_ISTAT_REG(base) ((base)->ISTAT)
-#define USB_INTEN_REG(base) ((base)->INTEN)
-#define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
-#define USB_ERREN_REG(base) ((base)->ERREN)
-#define USB_STAT_REG(base) ((base)->STAT)
-#define USB_CTL_REG(base) ((base)->CTL)
-#define USB_ADDR_REG(base) ((base)->ADDR)
-#define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
-#define USB_FRMNUML_REG(base) ((base)->FRMNUML)
-#define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
-#define USB_TOKEN_REG(base) ((base)->TOKEN)
-#define USB_SOFTHLD_REG(base) ((base)->SOFTHLD)
-#define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
-#define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
-#define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
-#define USB_USBCTRL_REG(base) ((base)->USBCTRL)
-#define USB_OBSERVE_REG(base) ((base)->OBSERVE)
-#define USB_CONTROL_REG(base) ((base)->CONTROL)
-#define USB_USBTRC0_REG(base) ((base)->USBTRC0)
-#define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)
-#define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL)
-#define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN)
-#define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS)
-
-/*!
- * @}
- */ /* end of group USB_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- USB Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USB_Register_Masks USB Register Masks
- * @{
- */
-
-/* PERID Bit Fields */
-#define USB_PERID_ID_MASK 0x3Fu
-#define USB_PERID_ID_SHIFT 0
-#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
-/* IDCOMP Bit Fields */
-#define USB_IDCOMP_NID_MASK 0x3Fu
-#define USB_IDCOMP_NID_SHIFT 0
-#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
-/* REV Bit Fields */
-#define USB_REV_REV_MASK 0xFFu
-#define USB_REV_REV_SHIFT 0
-#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
-/* ADDINFO Bit Fields */
-#define USB_ADDINFO_IEHOST_MASK 0x1u
-#define USB_ADDINFO_IEHOST_SHIFT 0
-#define USB_ADDINFO_IRQNUM_MASK 0xF8u
-#define USB_ADDINFO_IRQNUM_SHIFT 3
-#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
-/* OTGISTAT Bit Fields */
-#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
-#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
-#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
-#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
-#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
-#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
-#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
-#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
-#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
-#define USB_OTGISTAT_ONEMSEC_SHIFT 6
-#define USB_OTGISTAT_IDCHG_MASK 0x80u
-#define USB_OTGISTAT_IDCHG_SHIFT 7
-/* OTGICR Bit Fields */
-#define USB_OTGICR_AVBUSEN_MASK 0x1u
-#define USB_OTGICR_AVBUSEN_SHIFT 0
-#define USB_OTGICR_BSESSEN_MASK 0x4u
-#define USB_OTGICR_BSESSEN_SHIFT 2
-#define USB_OTGICR_SESSVLDEN_MASK 0x8u
-#define USB_OTGICR_SESSVLDEN_SHIFT 3
-#define USB_OTGICR_LINESTATEEN_MASK 0x20u
-#define USB_OTGICR_LINESTATEEN_SHIFT 5
-#define USB_OTGICR_ONEMSECEN_MASK 0x40u
-#define USB_OTGICR_ONEMSECEN_SHIFT 6
-#define USB_OTGICR_IDEN_MASK 0x80u
-#define USB_OTGICR_IDEN_SHIFT 7
-/* OTGSTAT Bit Fields */
-#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
-#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
-#define USB_OTGSTAT_BSESSEND_MASK 0x4u
-#define USB_OTGSTAT_BSESSEND_SHIFT 2
-#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
-#define USB_OTGSTAT_SESS_VLD_SHIFT 3
-#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
-#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
-#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
-#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
-#define USB_OTGSTAT_ID_MASK 0x80u
-#define USB_OTGSTAT_ID_SHIFT 7
-/* OTGCTL Bit Fields */
-#define USB_OTGCTL_OTGEN_MASK 0x4u
-#define USB_OTGCTL_OTGEN_SHIFT 2
-#define USB_OTGCTL_DMLOW_MASK 0x10u
-#define USB_OTGCTL_DMLOW_SHIFT 4
-#define USB_OTGCTL_DPLOW_MASK 0x20u
-#define USB_OTGCTL_DPLOW_SHIFT 5
-#define USB_OTGCTL_DPHIGH_MASK 0x80u
-#define USB_OTGCTL_DPHIGH_SHIFT 7
-/* ISTAT Bit Fields */
-#define USB_ISTAT_USBRST_MASK 0x1u
-#define USB_ISTAT_USBRST_SHIFT 0
-#define USB_ISTAT_ERROR_MASK 0x2u
-#define USB_ISTAT_ERROR_SHIFT 1
-#define USB_ISTAT_SOFTOK_MASK 0x4u
-#define USB_ISTAT_SOFTOK_SHIFT 2
-#define USB_ISTAT_TOKDNE_MASK 0x8u
-#define USB_ISTAT_TOKDNE_SHIFT 3
-#define USB_ISTAT_SLEEP_MASK 0x10u
-#define USB_ISTAT_SLEEP_SHIFT 4
-#define USB_ISTAT_RESUME_MASK 0x20u
-#define USB_ISTAT_RESUME_SHIFT 5
-#define USB_ISTAT_ATTACH_MASK 0x40u
-#define USB_ISTAT_ATTACH_SHIFT 6
-#define USB_ISTAT_STALL_MASK 0x80u
-#define USB_ISTAT_STALL_SHIFT 7
-/* INTEN Bit Fields */
-#define USB_INTEN_USBRSTEN_MASK 0x1u
-#define USB_INTEN_USBRSTEN_SHIFT 0
-#define USB_INTEN_ERROREN_MASK 0x2u
-#define USB_INTEN_ERROREN_SHIFT 1
-#define USB_INTEN_SOFTOKEN_MASK 0x4u
-#define USB_INTEN_SOFTOKEN_SHIFT 2
-#define USB_INTEN_TOKDNEEN_MASK 0x8u
-#define USB_INTEN_TOKDNEEN_SHIFT 3
-#define USB_INTEN_SLEEPEN_MASK 0x10u
-#define USB_INTEN_SLEEPEN_SHIFT 4
-#define USB_INTEN_RESUMEEN_MASK 0x20u
-#define USB_INTEN_RESUMEEN_SHIFT 5
-#define USB_INTEN_ATTACHEN_MASK 0x40u
-#define USB_INTEN_ATTACHEN_SHIFT 6
-#define USB_INTEN_STALLEN_MASK 0x80u
-#define USB_INTEN_STALLEN_SHIFT 7
-/* ERRSTAT Bit Fields */
-#define USB_ERRSTAT_PIDERR_MASK 0x1u
-#define USB_ERRSTAT_PIDERR_SHIFT 0
-#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
-#define USB_ERRSTAT_CRC5EOF_SHIFT 1
-#define USB_ERRSTAT_CRC16_MASK 0x4u
-#define USB_ERRSTAT_CRC16_SHIFT 2
-#define USB_ERRSTAT_DFN8_MASK 0x8u
-#define USB_ERRSTAT_DFN8_SHIFT 3
-#define USB_ERRSTAT_BTOERR_MASK 0x10u
-#define USB_ERRSTAT_BTOERR_SHIFT 4
-#define USB_ERRSTAT_DMAERR_MASK 0x20u
-#define USB_ERRSTAT_DMAERR_SHIFT 5
-#define USB_ERRSTAT_BTSERR_MASK 0x80u
-#define USB_ERRSTAT_BTSERR_SHIFT 7
-/* ERREN Bit Fields */
-#define USB_ERREN_PIDERREN_MASK 0x1u
-#define USB_ERREN_PIDERREN_SHIFT 0
-#define USB_ERREN_CRC5EOFEN_MASK 0x2u
-#define USB_ERREN_CRC5EOFEN_SHIFT 1
-#define USB_ERREN_CRC16EN_MASK 0x4u
-#define USB_ERREN_CRC16EN_SHIFT 2
-#define USB_ERREN_DFN8EN_MASK 0x8u
-#define USB_ERREN_DFN8EN_SHIFT 3
-#define USB_ERREN_BTOERREN_MASK 0x10u
-#define USB_ERREN_BTOERREN_SHIFT 4
-#define USB_ERREN_DMAERREN_MASK 0x20u
-#define USB_ERREN_DMAERREN_SHIFT 5
-#define USB_ERREN_BTSERREN_MASK 0x80u
-#define USB_ERREN_BTSERREN_SHIFT 7
-/* STAT Bit Fields */
-#define USB_STAT_ODD_MASK 0x4u
-#define USB_STAT_ODD_SHIFT 2
-#define USB_STAT_TX_MASK 0x8u
-#define USB_STAT_TX_SHIFT 3
-#define USB_STAT_ENDP_MASK 0xF0u
-#define USB_STAT_ENDP_SHIFT 4
-#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
-/* CTL Bit Fields */
-#define USB_CTL_USBENSOFEN_MASK 0x1u
-#define USB_CTL_USBENSOFEN_SHIFT 0
-#define USB_CTL_ODDRST_MASK 0x2u
-#define USB_CTL_ODDRST_SHIFT 1
-#define USB_CTL_RESUME_MASK 0x4u
-#define USB_CTL_RESUME_SHIFT 2
-#define USB_CTL_HOSTMODEEN_MASK 0x8u
-#define USB_CTL_HOSTMODEEN_SHIFT 3
-#define USB_CTL_RESET_MASK 0x10u
-#define USB_CTL_RESET_SHIFT 4
-#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
-#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
-#define USB_CTL_SE0_MASK 0x40u
-#define USB_CTL_SE0_SHIFT 6
-#define USB_CTL_JSTATE_MASK 0x80u
-#define USB_CTL_JSTATE_SHIFT 7
-/* ADDR Bit Fields */
-#define USB_ADDR_ADDR_MASK 0x7Fu
-#define USB_ADDR_ADDR_SHIFT 0
-#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
-#define USB_ADDR_LSEN_MASK 0x80u
-#define USB_ADDR_LSEN_SHIFT 7
-/* BDTPAGE1 Bit Fields */
-#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
-#define USB_BDTPAGE1_BDTBA_SHIFT 1
-#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
-/* FRMNUML Bit Fields */
-#define USB_FRMNUML_FRM_MASK 0xFFu
-#define USB_FRMNUML_FRM_SHIFT 0
-#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
-/* FRMNUMH Bit Fields */
-#define USB_FRMNUMH_FRM_MASK 0x7u
-#define USB_FRMNUMH_FRM_SHIFT 0
-#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
-/* TOKEN Bit Fields */
-#define USB_TOKEN_TOKENENDPT_MASK 0xFu
-#define USB_TOKEN_TOKENENDPT_SHIFT 0
-#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
-#define USB_TOKEN_TOKENPID_MASK 0xF0u
-#define USB_TOKEN_TOKENPID_SHIFT 4
-#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
-/* SOFTHLD Bit Fields */
-#define USB_SOFTHLD_CNT_MASK 0xFFu
-#define USB_SOFTHLD_CNT_SHIFT 0
-#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
-/* BDTPAGE2 Bit Fields */
-#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
-#define USB_BDTPAGE2_BDTBA_SHIFT 0
-#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
-/* BDTPAGE3 Bit Fields */
-#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
-#define USB_BDTPAGE3_BDTBA_SHIFT 0
-#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
-/* ENDPT Bit Fields */
-#define USB_ENDPT_EPHSHK_MASK 0x1u
-#define USB_ENDPT_EPHSHK_SHIFT 0
-#define USB_ENDPT_EPSTALL_MASK 0x2u
-#define USB_ENDPT_EPSTALL_SHIFT 1
-#define USB_ENDPT_EPTXEN_MASK 0x4u
-#define USB_ENDPT_EPTXEN_SHIFT 2
-#define USB_ENDPT_EPRXEN_MASK 0x8u
-#define USB_ENDPT_EPRXEN_SHIFT 3
-#define USB_ENDPT_EPCTLDIS_MASK 0x10u
-#define USB_ENDPT_EPCTLDIS_SHIFT 4
-#define USB_ENDPT_RETRYDIS_MASK 0x40u
-#define USB_ENDPT_RETRYDIS_SHIFT 6
-#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
-#define USB_ENDPT_HOSTWOHUB_SHIFT 7
-/* USBCTRL Bit Fields */
-#define USB_USBCTRL_PDE_MASK 0x40u
-#define USB_USBCTRL_PDE_SHIFT 6
-#define USB_USBCTRL_SUSP_MASK 0x80u
-#define USB_USBCTRL_SUSP_SHIFT 7
-/* OBSERVE Bit Fields */
-#define USB_OBSERVE_DMPD_MASK 0x10u
-#define USB_OBSERVE_DMPD_SHIFT 4
-#define USB_OBSERVE_DPPD_MASK 0x40u
-#define USB_OBSERVE_DPPD_SHIFT 6
-#define USB_OBSERVE_DPPU_MASK 0x80u
-#define USB_OBSERVE_DPPU_SHIFT 7
-/* CONTROL Bit Fields */
-#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
-#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
-/* USBTRC0 Bit Fields */
-#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
-#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
-#define USB_USBTRC0_SYNC_DET_MASK 0x2u
-#define USB_USBTRC0_SYNC_DET_SHIFT 1
-#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK 0x4u
-#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT 2
-#define USB_USBTRC0_USBRESMEN_MASK 0x20u
-#define USB_USBTRC0_USBRESMEN_SHIFT 5
-#define USB_USBTRC0_USBRESET_MASK 0x80u
-#define USB_USBTRC0_USBRESET_SHIFT 7
-/* USBFRMADJUST Bit Fields */
-#define USB_USBFRMADJUST_ADJ_MASK 0xFFu
-#define USB_USBFRMADJUST_ADJ_SHIFT 0
-#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
-/* CLK_RECOVER_CTRL Bit Fields */
-#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
-#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
-#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
-#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
-#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
-#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
-/* CLK_RECOVER_IRC_EN Bit Fields */
-#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK 0x1u
-#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT 0
-#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK 0x2u
-#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT 1
-/* CLK_RECOVER_INT_STATUS Bit Fields */
-#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
-#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
-
-/*!
- * @}
- */ /* end of group USB_Register_Masks */
-
-
-/* USB - Peripheral instance base addresses */
-/** Peripheral USB0 base address */
-#define USB0_BASE (0x40072000u)
-/** Peripheral USB0 base pointer */
-#define USB0 ((USB_Type *)USB0_BASE)
-#define USB0_BASE_PTR (USB0)
-/** Array initializer of USB peripheral base pointers */
-#define USB_BASES { USB0 }
-
-/* ----------------------------------------------------------------------------
- -- USB - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
- * @{
- */
-
-
-/* USB - Register instance definitions */
-/* USB0 */
-#define USB0_PERID USB_PERID_REG(USB0)
-#define USB0_IDCOMP USB_IDCOMP_REG(USB0)
-#define USB0_REV USB_REV_REG(USB0)
-#define USB0_ADDINFO USB_ADDINFO_REG(USB0)
-#define USB0_OTGISTAT USB_OTGISTAT_REG(USB0)
-#define USB0_OTGICR USB_OTGICR_REG(USB0)
-#define USB0_OTGSTAT USB_OTGSTAT_REG(USB0)
-#define USB0_OTGCTL USB_OTGCTL_REG(USB0)
-#define USB0_ISTAT USB_ISTAT_REG(USB0)
-#define USB0_INTEN USB_INTEN_REG(USB0)
-#define USB0_ERRSTAT USB_ERRSTAT_REG(USB0)
-#define USB0_ERREN USB_ERREN_REG(USB0)
-#define USB0_STAT USB_STAT_REG(USB0)
-#define USB0_CTL USB_CTL_REG(USB0)
-#define USB0_ADDR USB_ADDR_REG(USB0)
-#define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0)
-#define USB0_FRMNUML USB_FRMNUML_REG(USB0)
-#define USB0_FRMNUMH USB_FRMNUMH_REG(USB0)
-#define USB0_TOKEN USB_TOKEN_REG(USB0)
-#define USB0_SOFTHLD USB_SOFTHLD_REG(USB0)
-#define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0)
-#define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0)
-#define USB0_ENDPT0 USB_ENDPT_REG(USB0,0)
-#define USB0_ENDPT1 USB_ENDPT_REG(USB0,1)
-#define USB0_ENDPT2 USB_ENDPT_REG(USB0,2)
-#define USB0_ENDPT3 USB_ENDPT_REG(USB0,3)
-#define USB0_ENDPT4 USB_ENDPT_REG(USB0,4)
-#define USB0_ENDPT5 USB_ENDPT_REG(USB0,5)
-#define USB0_ENDPT6 USB_ENDPT_REG(USB0,6)
-#define USB0_ENDPT7 USB_ENDPT_REG(USB0,7)
-#define USB0_ENDPT8 USB_ENDPT_REG(USB0,8)
-#define USB0_ENDPT9 USB_ENDPT_REG(USB0,9)
-#define USB0_ENDPT10 USB_ENDPT_REG(USB0,10)
-#define USB0_ENDPT11 USB_ENDPT_REG(USB0,11)
-#define USB0_ENDPT12 USB_ENDPT_REG(USB0,12)
-#define USB0_ENDPT13 USB_ENDPT_REG(USB0,13)
-#define USB0_ENDPT14 USB_ENDPT_REG(USB0,14)
-#define USB0_ENDPT15 USB_ENDPT_REG(USB0,15)
-#define USB0_USBCTRL USB_USBCTRL_REG(USB0)
-#define USB0_OBSERVE USB_OBSERVE_REG(USB0)
-#define USB0_CONTROL USB_CONTROL_REG(USB0)
-#define USB0_USBTRC0 USB_USBTRC0_REG(USB0)
-#define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0)
-#define USB0_CLK_RECOVER_CTRL USB_CLK_RECOVER_CTRL_REG(USB0)
-#define USB0_CLK_RECOVER_IRC_EN USB_CLK_RECOVER_IRC_EN_REG(USB0)
-#define USB0_CLK_RECOVER_INT_STATUS USB_CLK_RECOVER_INT_STATUS_REG(USB0)
-
-/* USB - Register array accessors */
-#define USB0_ENDPT(index) USB_ENDPT_REG(USB0,index)
-
-/*!
- * @}
- */ /* end of group USB_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group USB_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- USBDCD Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
- * @{
- */
-
-/** USBDCD - Register Layout Typedef */
-typedef struct {
- __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */
- __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */
- __I uint32_t STATUS; /**< Status register, offset: 0x8 */
- uint8_t RESERVED_0[4];
- __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */
- __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */
- union { /* offset: 0x18 */
- __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */
- __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */
- };
-} USBDCD_Type, *USBDCD_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- USBDCD - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
- * @{
- */
-
-
-/* USBDCD - Register accessors */
-#define USBDCD_CONTROL_REG(base) ((base)->CONTROL)
-#define USBDCD_CLOCK_REG(base) ((base)->CLOCK)
-#define USBDCD_STATUS_REG(base) ((base)->STATUS)
-#define USBDCD_TIMER0_REG(base) ((base)->TIMER0)
-#define USBDCD_TIMER1_REG(base) ((base)->TIMER1)
-#define USBDCD_TIMER2_BC11_REG(base) ((base)->TIMER2_BC11)
-#define USBDCD_TIMER2_BC12_REG(base) ((base)->TIMER2_BC12)
-
-/*!
- * @}
- */ /* end of group USBDCD_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- USBDCD Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
- * @{
- */
-
-/* CONTROL Bit Fields */
-#define USBDCD_CONTROL_IACK_MASK 0x1u
-#define USBDCD_CONTROL_IACK_SHIFT 0
-#define USBDCD_CONTROL_IF_MASK 0x100u
-#define USBDCD_CONTROL_IF_SHIFT 8
-#define USBDCD_CONTROL_IE_MASK 0x10000u
-#define USBDCD_CONTROL_IE_SHIFT 16
-#define USBDCD_CONTROL_BC12_MASK 0x20000u
-#define USBDCD_CONTROL_BC12_SHIFT 17
-#define USBDCD_CONTROL_START_MASK 0x1000000u
-#define USBDCD_CONTROL_START_SHIFT 24
-#define USBDCD_CONTROL_SR_MASK 0x2000000u
-#define USBDCD_CONTROL_SR_SHIFT 25
-/* CLOCK Bit Fields */
-#define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u
-#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0
-#define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu
-#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2
-#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
-/* STATUS Bit Fields */
-#define USBDCD_STATUS_SEQ_RES_MASK 0x30000u
-#define USBDCD_STATUS_SEQ_RES_SHIFT 16
-#define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
-#define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u
-#define USBDCD_STATUS_SEQ_STAT_SHIFT 18
-#define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
-#define USBDCD_STATUS_ERR_MASK 0x100000u
-#define USBDCD_STATUS_ERR_SHIFT 20
-#define USBDCD_STATUS_TO_MASK 0x200000u
-#define USBDCD_STATUS_TO_SHIFT 21
-#define USBDCD_STATUS_ACTIVE_MASK 0x400000u
-#define USBDCD_STATUS_ACTIVE_SHIFT 22
-/* TIMER0 Bit Fields */
-#define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu
-#define USBDCD_TIMER0_TUNITCON_SHIFT 0
-#define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
-#define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u
-#define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16
-#define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
-/* TIMER1 Bit Fields */
-#define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu
-#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0
-#define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
-#define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u
-#define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16
-#define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
-/* TIMER2_BC11 Bit Fields */
-#define USBDCD_TIMER2_BC11_CHECK_DM_MASK 0xFu
-#define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT 0
-#define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_CHECK_DM_SHIFT))&USBDCD_TIMER2_BC11_CHECK_DM_MASK)
-#define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK 0x3FF0000u
-#define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT 16
-#define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
-/* TIMER2_BC12 Bit Fields */
-#define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK 0x3FFu
-#define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT 0
-#define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT))&USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
-#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK 0x3FF0000u
-#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT 16
-#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT))&USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
-
-/*!
- * @}
- */ /* end of group USBDCD_Register_Masks */
-
-
-/* USBDCD - Peripheral instance base addresses */
-/** Peripheral USBDCD base address */
-#define USBDCD_BASE (0x40035000u)
-/** Peripheral USBDCD base pointer */
-#define USBDCD ((USBDCD_Type *)USBDCD_BASE)
-#define USBDCD_BASE_PTR (USBDCD)
-/** Array initializer of USBDCD peripheral base pointers */
-#define USBDCD_BASES { USBDCD }
-
-/* ----------------------------------------------------------------------------
- -- USBDCD - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
- * @{
- */
-
-
-/* USBDCD - Register instance definitions */
-/* USBDCD */
-#define USBDCD_CONTROL USBDCD_CONTROL_REG(USBDCD)
-#define USBDCD_CLOCK USBDCD_CLOCK_REG(USBDCD)
-#define USBDCD_STATUS USBDCD_STATUS_REG(USBDCD)
-#define USBDCD_TIMER0 USBDCD_TIMER0_REG(USBDCD)
-#define USBDCD_TIMER1 USBDCD_TIMER1_REG(USBDCD)
-#define USBDCD_TIMER2_BC11 USBDCD_TIMER2_BC11_REG(USBDCD)
-#define USBDCD_TIMER2_BC12 USBDCD_TIMER2_BC12_REG(USBDCD)
-
-/*!
- * @}
- */ /* end of group USBDCD_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group USBDCD_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- VREF Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
- * @{
- */
-
-/** VREF - Register Layout Typedef */
-typedef struct {
- __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
- __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
-} VREF_Type, *VREF_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- VREF - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
- * @{
- */
-
-
-/* VREF - Register accessors */
-#define VREF_TRM_REG(base) ((base)->TRM)
-#define VREF_SC_REG(base) ((base)->SC)
-
-/*!
- * @}
- */ /* end of group VREF_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- VREF Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup VREF_Register_Masks VREF Register Masks
- * @{
- */
-
-/* TRM Bit Fields */
-#define VREF_TRM_TRIM_MASK 0x3Fu
-#define VREF_TRM_TRIM_SHIFT 0
-#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
-#define VREF_TRM_CHOPEN_MASK 0x40u
-#define VREF_TRM_CHOPEN_SHIFT 6
-/* SC Bit Fields */
-#define VREF_SC_MODE_LV_MASK 0x3u
-#define VREF_SC_MODE_LV_SHIFT 0
-#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
-#define VREF_SC_VREFST_MASK 0x4u
-#define VREF_SC_VREFST_SHIFT 2
-#define VREF_SC_ICOMPEN_MASK 0x20u
-#define VREF_SC_ICOMPEN_SHIFT 5
-#define VREF_SC_REGEN_MASK 0x40u
-#define VREF_SC_REGEN_SHIFT 6
-#define VREF_SC_VREFEN_MASK 0x80u
-#define VREF_SC_VREFEN_SHIFT 7
-
-/*!
- * @}
- */ /* end of group VREF_Register_Masks */
-
-
-/* VREF - Peripheral instance base addresses */
-/** Peripheral VREF base address */
-#define VREF_BASE (0x40074000u)
-/** Peripheral VREF base pointer */
-#define VREF ((VREF_Type *)VREF_BASE)
-#define VREF_BASE_PTR (VREF)
-/** Array initializer of VREF peripheral base pointers */
-#define VREF_BASES { VREF }
-
-/* ----------------------------------------------------------------------------
- -- VREF - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
- * @{
- */
-
-
-/* VREF - Register instance definitions */
-/* VREF */
-#define VREF_TRM VREF_TRM_REG(VREF)
-#define VREF_SC VREF_SC_REG(VREF)
-
-/*!
- * @}
- */ /* end of group VREF_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group VREF_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- WDOG Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
- * @{
- */
-
-/** WDOG - Register Layout Typedef */
-typedef struct {
- __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
- __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
- __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
- __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
- __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
- __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
- __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
- __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
- __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
- __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
- __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
- __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
-} WDOG_Type, *WDOG_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- WDOG - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
- * @{
- */
-
-
-/* WDOG - Register accessors */
-#define WDOG_STCTRLH_REG(base) ((base)->STCTRLH)
-#define WDOG_STCTRLL_REG(base) ((base)->STCTRLL)
-#define WDOG_TOVALH_REG(base) ((base)->TOVALH)
-#define WDOG_TOVALL_REG(base) ((base)->TOVALL)
-#define WDOG_WINH_REG(base) ((base)->WINH)
-#define WDOG_WINL_REG(base) ((base)->WINL)
-#define WDOG_REFRESH_REG(base) ((base)->REFRESH)
-#define WDOG_UNLOCK_REG(base) ((base)->UNLOCK)
-#define WDOG_TMROUTH_REG(base) ((base)->TMROUTH)
-#define WDOG_TMROUTL_REG(base) ((base)->TMROUTL)
-#define WDOG_RSTCNT_REG(base) ((base)->RSTCNT)
-#define WDOG_PRESC_REG(base) ((base)->PRESC)
-
-/*!
- * @}
- */ /* end of group WDOG_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- WDOG Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup WDOG_Register_Masks WDOG Register Masks
- * @{
- */
-
-/* STCTRLH Bit Fields */
-#define WDOG_STCTRLH_WDOGEN_MASK 0x1u
-#define WDOG_STCTRLH_WDOGEN_SHIFT 0
-#define WDOG_STCTRLH_CLKSRC_MASK 0x2u
-#define WDOG_STCTRLH_CLKSRC_SHIFT 1
-#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
-#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
-#define WDOG_STCTRLH_WINEN_MASK 0x8u
-#define WDOG_STCTRLH_WINEN_SHIFT 3
-#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
-#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
-#define WDOG_STCTRLH_DBGEN_MASK 0x20u
-#define WDOG_STCTRLH_DBGEN_SHIFT 5
-#define WDOG_STCTRLH_STOPEN_MASK 0x40u
-#define WDOG_STCTRLH_STOPEN_SHIFT 6
-#define WDOG_STCTRLH_WAITEN_MASK 0x80u
-#define WDOG_STCTRLH_WAITEN_SHIFT 7
-#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
-#define WDOG_STCTRLH_TESTWDOG_SHIFT 10
-#define WDOG_STCTRLH_TESTSEL_MASK 0x800u
-#define WDOG_STCTRLH_TESTSEL_SHIFT 11
-#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
-#define WDOG_STCTRLH_BYTESEL_SHIFT 12
-#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
-#define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
-#define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
-/* STCTRLL Bit Fields */
-#define WDOG_STCTRLL_INTFLG_MASK 0x8000u
-#define WDOG_STCTRLL_INTFLG_SHIFT 15
-/* TOVALH Bit Fields */
-#define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
-#define WDOG_TOVALH_TOVALHIGH_SHIFT 0
-#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
-/* TOVALL Bit Fields */
-#define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
-#define WDOG_TOVALL_TOVALLOW_SHIFT 0
-#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
-/* WINH Bit Fields */
-#define WDOG_WINH_WINHIGH_MASK 0xFFFFu
-#define WDOG_WINH_WINHIGH_SHIFT 0
-#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
-/* WINL Bit Fields */
-#define WDOG_WINL_WINLOW_MASK 0xFFFFu
-#define WDOG_WINL_WINLOW_SHIFT 0
-#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
-/* REFRESH Bit Fields */
-#define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
-#define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
-#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
-/* UNLOCK Bit Fields */
-#define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
-#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
-#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
-/* TMROUTH Bit Fields */
-#define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
-#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
-#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
-/* TMROUTL Bit Fields */
-#define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
-#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
-#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
-/* RSTCNT Bit Fields */
-#define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
-#define WDOG_RSTCNT_RSTCNT_SHIFT 0
-#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
-/* PRESC Bit Fields */
-#define WDOG_PRESC_PRESCVAL_MASK 0x700u
-#define WDOG_PRESC_PRESCVAL_SHIFT 8
-#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
-
-/*!
- * @}
- */ /* end of group WDOG_Register_Masks */
-
-
-/* WDOG - Peripheral instance base addresses */
-/** Peripheral WDOG base address */
-#define WDOG_BASE (0x40052000u)
-/** Peripheral WDOG base pointer */
-#define WDOG ((WDOG_Type *)WDOG_BASE)
-#define WDOG_BASE_PTR (WDOG)
-/** Array initializer of WDOG peripheral base pointers */
-#define WDOG_BASES { WDOG }
-
-/* ----------------------------------------------------------------------------
- -- WDOG - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
- * @{
- */
-
-
-/* WDOG - Register instance definitions */
-/* WDOG */
-#define WDOG_STCTRLH WDOG_STCTRLH_REG(WDOG)
-#define WDOG_STCTRLL WDOG_STCTRLL_REG(WDOG)
-#define WDOG_TOVALH WDOG_TOVALH_REG(WDOG)
-#define WDOG_TOVALL WDOG_TOVALL_REG(WDOG)
-#define WDOG_WINH WDOG_WINH_REG(WDOG)
-#define WDOG_WINL WDOG_WINL_REG(WDOG)
-#define WDOG_REFRESH WDOG_REFRESH_REG(WDOG)
-#define WDOG_UNLOCK WDOG_UNLOCK_REG(WDOG)
-#define WDOG_TMROUTH WDOG_TMROUTH_REG(WDOG)
-#define WDOG_TMROUTL WDOG_TMROUTL_REG(WDOG)
-#define WDOG_RSTCNT WDOG_RSTCNT_REG(WDOG)
-#define WDOG_PRESC WDOG_PRESC_REG(WDOG)
-
-/*!
- * @}
- */ /* end of group WDOG_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group WDOG_Peripheral_Access_Layer */
-
-
-/*
-** End of section using anonymous unions
-*/
-
-#if defined(__ARMCC_VERSION)
- #pragma pop
-#elif defined(__CWCC__)
- #pragma pop
-#elif defined(__GNUC__)
- /* leave anonymous unions enabled */
-#elif defined(__IAR_SYSTEMS_ICC__)
- #pragma language=default
-#else
- #error Not supported compiler type
-#endif
-
-/*!
- * @}
- */ /* end of group Peripheral_access_layer */
-
-
-/* ----------------------------------------------------------------------------
- -- Backward Compatibility
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
- * @{
- */
-
-#define DMA_EARS_REG(base) This_symbol_has_been_deprecated
-#define DMA_EARS This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_0_MASK This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_0_SHIFT This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_1_MASK This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_1_SHIFT This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_2_MASK This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_2_SHIFT This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_3_MASK This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_3_SHIFT This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_4_MASK This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_4_SHIFT This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_5_MASK This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_5_SHIFT This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_6_MASK This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_6_SHIFT This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_7_MASK This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_7_SHIFT This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_8_MASK This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_8_SHIFT This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_9_MASK This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_9_SHIFT This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_10_MASK This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_10_SHIFT This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_11_MASK This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_11_SHIFT This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_12_MASK This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_12_SHIFT This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_13_MASK This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_13_SHIFT This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_14_MASK This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_14_SHIFT This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_15_MASK This_symbol_has_been_deprecated
-#define DMA_EARS_EDREQ_15_SHIFT This_symbol_has_been_deprecated
-#define ENET_RMON_T_DROP_REG(base) This_symbol_has_been_deprecated
-#define ENET_IEEE_T_DROP_REG(base) This_symbol_has_been_deprecated
-#define ENET_IEEE_T_SQE_REG(base) This_symbol_has_been_deprecated
-#define ENET_RMON_R_RESVD_0_REG(base) This_symbol_has_been_deprecated
-#define ENET_RMON_R_DROP_REG(base) ENET_IEEE_R_DROP_REG(base)
-#define ENET_RMON_R_FRAME_OK_REG(base) ENET_IEEE_R_FRAME_OK_REG(base)
-#define ENET_RMON_T_DROP This_symbol_has_been_deprecated
-#define ENET_IEEE_T_DROP This_symbol_has_been_deprecated
-#define ENET_IEEE_T_SQE This_symbol_has_been_deprecated
-#define ENET_RMON_R_RESVD_0 This_symbol_has_been_deprecated
-#define MCG_C9_REG(base) This_symbol_has_been_deprecated
-#define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
-#define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
-#define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
-#define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
-#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
-#define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
-#define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
-#define MCG_C9 This_symbol_has_been_deprecated
-#define MCM_PLACR_REG(base) This_symbol_has_been_deprecated
-#define MCM_PLACR_ARB_MASK This_symbol_has_been_deprecated
-#define MCM_PLACR_ARB_SHIFT This_symbol_has_been_deprecated
-#define MCM_PLACR This_symbol_has_been_deprecated
-
-/*!
- * @}
- */ /* end of group Backward_Compatibility_Symbols */
-
-
-#else /* #if !defined(MCU_MK64F12) */
- /* There is already included the same memory map. Check if it is compatible (has the same major version) */
- #if (MCU_MEM_MAP_VERSION != 0x0200u)
- #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
- #warning There are included two not compatible versions of memory maps. Please check possible differences.
- #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
- #endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */
-#endif /* #if !defined(MCU_MK64F12) */
-
-#endif /* #if !defined(MK64F12_H_) */
-
-/* MK64F12.h, eof. */
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_adc.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,2578 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_ADC_REGISTERS_H__
-#define __HW_ADC_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 ADC
- *
- * Analog-to-Digital Converter
- *
- * Registers defined in this header file:
- * - HW_ADC_SC1n - ADC Status and Control Registers 1
- * - HW_ADC_CFG1 - ADC Configuration Register 1
- * - HW_ADC_CFG2 - ADC Configuration Register 2
- * - HW_ADC_Rn - ADC Data Result Register
- * - HW_ADC_CV1 - Compare Value Registers
- * - HW_ADC_CV2 - Compare Value Registers
- * - HW_ADC_SC2 - Status and Control Register 2
- * - HW_ADC_SC3 - Status and Control Register 3
- * - HW_ADC_OFS - ADC Offset Correction Register
- * - HW_ADC_PG - ADC Plus-Side Gain Register
- * - HW_ADC_MG - ADC Minus-Side Gain Register
- * - HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register
- * - HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register
- * - HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register
- * - HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register
- * - HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register
- * - HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register
- * - HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register
- * - HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register
- * - HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register
- * - HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register
- * - HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register
- * - HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register
- * - HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register
- * - HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register
- *
- * - hw_adc_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_ADC_BASE
-#define HW_ADC_INSTANCE_COUNT (2U) //!< Number of instances of the ADC module.
-#define HW_ADC0 (0U) //!< Instance number for ADC0.
-#define HW_ADC1 (1U) //!< Instance number for ADC1.
-#define REGS_ADC0_BASE (0x4003B000U) //!< Base address for ADC0.
-#define REGS_ADC1_BASE (0x400BB000U) //!< Base address for ADC1.
-
-//! @brief Table of base addresses for ADC instances.
-static const uint32_t __g_regs_ADC_base_addresses[] = {
- REGS_ADC0_BASE,
- REGS_ADC1_BASE,
- };
-
-//! @brief Get the base address of ADC by instance number.
-//! @param x ADC instance number, from 0 through 1.
-#define REGS_ADC_BASE(x) (__g_regs_ADC_base_addresses[(x)])
-
-//! @brief Get the instance number given a base address.
-//! @param b Base address for an instance of ADC.
-#define REGS_ADC_INSTANCE(b) ((b) == REGS_ADC0_BASE ? HW_ADC0 : (b) == REGS_ADC1_BASE ? HW_ADC1 : 0)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ADC_SC1n - ADC Status and Control Registers 1
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ADC_SC1n - ADC Status and Control Registers 1 (RW)
- *
- * Reset value: 0x0000001FU
- *
- * SC1A is used for both software and hardware trigger modes of operation. To
- * allow sequential conversions of the ADC to be triggered by internal peripherals,
- * the ADC can have more than one status and control register: one for each
- * conversion. The SC1B-SC1n registers indicate potentially multiple SC1 registers
- * for use only in hardware trigger mode. See the chip configuration information
- * about the number of SC1n registers specific to this device. The SC1n registers
- * have identical fields, and are used in a "ping-pong" approach to control ADC
- * operation. At any one point in time, only one of the SC1n registers is actively
- * controlling ADC conversions. Updating SC1A while SC1n is actively controlling
- * a conversion is allowed, and vice-versa for any of the SC1n registers specific
- * to this MCU. Writing SC1A while SC1A is actively controlling a conversion
- * aborts the current conversion. In Software Trigger mode, when SC2[ADTRG]=0,
- * writes to SC1A subsequently initiate a new conversion, if SC1[ADCH] contains a
- * value other than all 1s. Writing any of the SC1n registers while that specific
- * SC1n register is actively controlling a conversion aborts the current conversion.
- * None of the SC1B-SC1n registers are used for software trigger operation and
- * therefore writes to the SC1B-SC1n registers do not initiate a new conversion.
- */
-typedef union _hw_adc_sc1n
-{
- uint32_t U;
- struct _hw_adc_sc1n_bitfields
- {
- uint32_t ADCH : 5; //!< [4:0] Input channel select
- uint32_t DIFF : 1; //!< [5] Differential Mode Enable
- uint32_t AIEN : 1; //!< [6] Interrupt Enable
- uint32_t COCO : 1; //!< [7] Conversion Complete Flag
- uint32_t RESERVED0 : 24; //!< [31:8]
- } B;
-} hw_adc_sc1n_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ADC_SC1n register
- */
-//@{
-#define HW_ADC_SC1n_COUNT (2U)
-
-#define HW_ADC_SC1n_ADDR(x, n) (REGS_ADC_BASE(x) + 0x0U + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ADC_SC1n(x, n) (*(__IO hw_adc_sc1n_t *) HW_ADC_SC1n_ADDR(x, n))
-#define HW_ADC_SC1n_RD(x, n) (HW_ADC_SC1n(x, n).U)
-#define HW_ADC_SC1n_WR(x, n, v) (HW_ADC_SC1n(x, n).U = (v))
-#define HW_ADC_SC1n_SET(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) | (v)))
-#define HW_ADC_SC1n_CLR(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) & ~(v)))
-#define HW_ADC_SC1n_TOG(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ADC_SC1n bitfields
- */
-
-/*!
- * @name Register ADC_SC1n, field ADCH[4:0] (RW)
- *
- * Selects one of the input channels. The input channel decode depends on the
- * value of DIFF. DAD0-DAD3 are associated with the input pin pairs DADPx and
- * DADMx. Some of the input channel options in the bitfield-setting descriptions might
- * not be available for your device. For the actual ADC channel assignments for
- * your device, see the Chip Configuration details. The successive approximation
- * converter subsystem is turned off when the channel select bits are all set,
- * that is, ADCH = 11111. This feature allows explicit disabling of the ADC and
- * isolation of the input channel from all sources. Terminating continuous
- * conversions this way prevents an additional single conversion from being performed. It
- * is not necessary to set ADCH to all 1s to place the ADC in a low-power state
- * when continuous conversions are not enabled because the module automatically
- * enters a low-power state when a conversion completes.
- *
- * Values:
- * - 00000 - When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is
- * selected as input.
- * - 00001 - When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is
- * selected as input.
- * - 00010 - When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is
- * selected as input.
- * - 00011 - When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is
- * selected as input.
- * - 00100 - When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
- * - 00101 - When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
- * - 00110 - When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
- * - 00111 - When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
- * - 01000 - When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
- * - 01001 - When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
- * - 01010 - When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
- * - 01011 - When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
- * - 01100 - When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
- * - 01101 - When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
- * - 01110 - When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
- * - 01111 - When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
- * - 10000 - When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
- * - 10001 - When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
- * - 10010 - When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
- * - 10011 - When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
- * - 10100 - When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
- * - 10101 - When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
- * - 10110 - When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
- * - 10111 - When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
- * - 11000 - Reserved.
- * - 11001 - Reserved.
- * - 11010 - When DIFF=0, Temp Sensor (single-ended) is selected as input; when
- * DIFF=1, Temp Sensor (differential) is selected as input.
- * - 11011 - When DIFF=0, Bandgap (single-ended) is selected as input; when
- * DIFF=1, Bandgap (differential) is selected as input.
- * - 11100 - Reserved.
- * - 11101 - When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH
- * (differential) is selected as input. Voltage reference selected is determined
- * by SC2[REFSEL].
- * - 11110 - When DIFF=0,VREFSL is selected as input; when DIFF=1, it is
- * reserved. Voltage reference selected is determined by SC2[REFSEL].
- * - 11111 - Module is disabled.
- */
-//@{
-#define BP_ADC_SC1n_ADCH (0U) //!< Bit position for ADC_SC1n_ADCH.
-#define BM_ADC_SC1n_ADCH (0x0000001FU) //!< Bit mask for ADC_SC1n_ADCH.
-#define BS_ADC_SC1n_ADCH (5U) //!< Bit field size in bits for ADC_SC1n_ADCH.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_SC1n_ADCH field.
-#define BR_ADC_SC1n_ADCH(x, n) (HW_ADC_SC1n(x, n).B.ADCH)
-#endif
-
-//! @brief Format value for bitfield ADC_SC1n_ADCH.
-#define BF_ADC_SC1n_ADCH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC1n_ADCH), uint32_t) & BM_ADC_SC1n_ADCH)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ADCH field to a new value.
-#define BW_ADC_SC1n_ADCH(x, n, v) (HW_ADC_SC1n_WR(x, n, (HW_ADC_SC1n_RD(x, n) & ~BM_ADC_SC1n_ADCH) | BF_ADC_SC1n_ADCH(v)))
-#endif
-//@}
-
-/*!
- * @name Register ADC_SC1n, field DIFF[5] (RW)
- *
- * Configures the ADC to operate in differential mode. When enabled, this mode
- * automatically selects from the differential channels, and changes the
- * conversion algorithm and the number of cycles to complete a conversion.
- *
- * Values:
- * - 0 - Single-ended conversions and input channels are selected.
- * - 1 - Differential conversions and input channels are selected.
- */
-//@{
-#define BP_ADC_SC1n_DIFF (5U) //!< Bit position for ADC_SC1n_DIFF.
-#define BM_ADC_SC1n_DIFF (0x00000020U) //!< Bit mask for ADC_SC1n_DIFF.
-#define BS_ADC_SC1n_DIFF (1U) //!< Bit field size in bits for ADC_SC1n_DIFF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_SC1n_DIFF field.
-#define BR_ADC_SC1n_DIFF(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_DIFF))
-#endif
-
-//! @brief Format value for bitfield ADC_SC1n_DIFF.
-#define BF_ADC_SC1n_DIFF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC1n_DIFF), uint32_t) & BM_ADC_SC1n_DIFF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DIFF field to a new value.
-#define BW_ADC_SC1n_DIFF(x, n, v) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_DIFF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ADC_SC1n, field AIEN[6] (RW)
- *
- * Enables conversion complete interrupts. When COCO becomes set while the
- * respective AIEN is high, an interrupt is asserted.
- *
- * Values:
- * - 0 - Conversion complete interrupt is disabled.
- * - 1 - Conversion complete interrupt is enabled.
- */
-//@{
-#define BP_ADC_SC1n_AIEN (6U) //!< Bit position for ADC_SC1n_AIEN.
-#define BM_ADC_SC1n_AIEN (0x00000040U) //!< Bit mask for ADC_SC1n_AIEN.
-#define BS_ADC_SC1n_AIEN (1U) //!< Bit field size in bits for ADC_SC1n_AIEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_SC1n_AIEN field.
-#define BR_ADC_SC1n_AIEN(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_AIEN))
-#endif
-
-//! @brief Format value for bitfield ADC_SC1n_AIEN.
-#define BF_ADC_SC1n_AIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC1n_AIEN), uint32_t) & BM_ADC_SC1n_AIEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the AIEN field to a new value.
-#define BW_ADC_SC1n_AIEN(x, n, v) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_AIEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ADC_SC1n, field COCO[7] (RO)
- *
- * This is a read-only field that is set each time a conversion is completed
- * when the compare function is disabled, or SC2[ACFE]=0 and the hardware average
- * function is disabled, or SC3[AVGE]=0. When the compare function is enabled, or
- * SC2[ACFE]=1, COCO is set upon completion of a conversion only if the compare
- * result is true. When the hardware average function is enabled, or SC3[AVGE]=1,
- * COCO is set upon completion of the selected number of conversions (determined
- * by AVGS). COCO in SC1A is also set at the completion of a calibration sequence.
- * COCO is cleared when the respective SC1n register is written or when the
- * respective Rn register is read.
- *
- * Values:
- * - 0 - Conversion is not completed.
- * - 1 - Conversion is completed.
- */
-//@{
-#define BP_ADC_SC1n_COCO (7U) //!< Bit position for ADC_SC1n_COCO.
-#define BM_ADC_SC1n_COCO (0x00000080U) //!< Bit mask for ADC_SC1n_COCO.
-#define BS_ADC_SC1n_COCO (1U) //!< Bit field size in bits for ADC_SC1n_COCO.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_SC1n_COCO field.
-#define BR_ADC_SC1n_COCO(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_COCO))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ADC_CFG1 - ADC Configuration Register 1
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ADC_CFG1 - ADC Configuration Register 1 (RW)
- *
- * Reset value: 0x00000000U
- *
- * The configuration Register 1 (CFG1) selects the mode of operation, clock
- * source, clock divide, and configuration for low power or long sample time.
- */
-typedef union _hw_adc_cfg1
-{
- uint32_t U;
- struct _hw_adc_cfg1_bitfields
- {
- uint32_t ADICLK : 2; //!< [1:0] Input Clock Select
- uint32_t MODE : 2; //!< [3:2] Conversion mode selection
- uint32_t ADLSMP : 1; //!< [4] Sample Time Configuration
- uint32_t ADIV : 2; //!< [6:5] Clock Divide Select
- uint32_t ADLPC : 1; //!< [7] Low-Power Configuration
- uint32_t RESERVED0 : 24; //!< [31:8]
- } B;
-} hw_adc_cfg1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ADC_CFG1 register
- */
-//@{
-#define HW_ADC_CFG1_ADDR(x) (REGS_ADC_BASE(x) + 0x8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ADC_CFG1(x) (*(__IO hw_adc_cfg1_t *) HW_ADC_CFG1_ADDR(x))
-#define HW_ADC_CFG1_RD(x) (HW_ADC_CFG1(x).U)
-#define HW_ADC_CFG1_WR(x, v) (HW_ADC_CFG1(x).U = (v))
-#define HW_ADC_CFG1_SET(x, v) (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) | (v)))
-#define HW_ADC_CFG1_CLR(x, v) (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) & ~(v)))
-#define HW_ADC_CFG1_TOG(x, v) (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ADC_CFG1 bitfields
- */
-
-/*!
- * @name Register ADC_CFG1, field ADICLK[1:0] (RW)
- *
- * Selects the input clock source to generate the internal clock, ADCK. Note
- * that when the ADACK clock source is selected, it is not required to be active
- * prior to conversion start. When it is selected and it is not active prior to a
- * conversion start, when CFG2[ADACKEN]=0, the asynchronous clock is activated at
- * the start of a conversion and deactivated when conversions are terminated. In
- * this case, there is an associated clock startup delay each time the clock
- * source is re-activated.
- *
- * Values:
- * - 00 - Bus clock
- * - 01 - Alternate clock 2 (ALTCLK2)
- * - 10 - Alternate clock (ALTCLK)
- * - 11 - Asynchronous clock (ADACK)
- */
-//@{
-#define BP_ADC_CFG1_ADICLK (0U) //!< Bit position for ADC_CFG1_ADICLK.
-#define BM_ADC_CFG1_ADICLK (0x00000003U) //!< Bit mask for ADC_CFG1_ADICLK.
-#define BS_ADC_CFG1_ADICLK (2U) //!< Bit field size in bits for ADC_CFG1_ADICLK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_CFG1_ADICLK field.
-#define BR_ADC_CFG1_ADICLK(x) (HW_ADC_CFG1(x).B.ADICLK)
-#endif
-
-//! @brief Format value for bitfield ADC_CFG1_ADICLK.
-#define BF_ADC_CFG1_ADICLK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG1_ADICLK), uint32_t) & BM_ADC_CFG1_ADICLK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ADICLK field to a new value.
-#define BW_ADC_CFG1_ADICLK(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_ADICLK) | BF_ADC_CFG1_ADICLK(v)))
-#endif
-//@}
-
-/*!
- * @name Register ADC_CFG1, field MODE[3:2] (RW)
- *
- * Selects the ADC resolution mode.
- *
- * Values:
- * - 00 - When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is
- * differential 9-bit conversion with 2's complement output.
- * - 01 - When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is
- * differential 13-bit conversion with 2's complement output.
- * - 10 - When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is
- * differential 11-bit conversion with 2's complement output
- * - 11 - When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is
- * differential 16-bit conversion with 2's complement output
- */
-//@{
-#define BP_ADC_CFG1_MODE (2U) //!< Bit position for ADC_CFG1_MODE.
-#define BM_ADC_CFG1_MODE (0x0000000CU) //!< Bit mask for ADC_CFG1_MODE.
-#define BS_ADC_CFG1_MODE (2U) //!< Bit field size in bits for ADC_CFG1_MODE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_CFG1_MODE field.
-#define BR_ADC_CFG1_MODE(x) (HW_ADC_CFG1(x).B.MODE)
-#endif
-
-//! @brief Format value for bitfield ADC_CFG1_MODE.
-#define BF_ADC_CFG1_MODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG1_MODE), uint32_t) & BM_ADC_CFG1_MODE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MODE field to a new value.
-#define BW_ADC_CFG1_MODE(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_MODE) | BF_ADC_CFG1_MODE(v)))
-#endif
-//@}
-
-/*!
- * @name Register ADC_CFG1, field ADLSMP[4] (RW)
- *
- * Selects between different sample times based on the conversion mode selected.
- * This field adjusts the sample period to allow higher impedance inputs to be
- * accurately sampled or to maximize conversion speed for lower impedance inputs.
- * Longer sample times can also be used to lower overall power consumption if
- * continuous conversions are enabled and high conversion rates are not required.
- * When ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the
- * extent of the long sample time.
- *
- * Values:
- * - 0 - Short sample time.
- * - 1 - Long sample time.
- */
-//@{
-#define BP_ADC_CFG1_ADLSMP (4U) //!< Bit position for ADC_CFG1_ADLSMP.
-#define BM_ADC_CFG1_ADLSMP (0x00000010U) //!< Bit mask for ADC_CFG1_ADLSMP.
-#define BS_ADC_CFG1_ADLSMP (1U) //!< Bit field size in bits for ADC_CFG1_ADLSMP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_CFG1_ADLSMP field.
-#define BR_ADC_CFG1_ADLSMP(x) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLSMP))
-#endif
-
-//! @brief Format value for bitfield ADC_CFG1_ADLSMP.
-#define BF_ADC_CFG1_ADLSMP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG1_ADLSMP), uint32_t) & BM_ADC_CFG1_ADLSMP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ADLSMP field to a new value.
-#define BW_ADC_CFG1_ADLSMP(x, v) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLSMP) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ADC_CFG1, field ADIV[6:5] (RW)
- *
- * Selects the divide ratio used by the ADC to generate the internal clock ADCK.
- *
- * Values:
- * - 00 - The divide ratio is 1 and the clock rate is input clock.
- * - 01 - The divide ratio is 2 and the clock rate is (input clock)/2.
- * - 10 - The divide ratio is 4 and the clock rate is (input clock)/4.
- * - 11 - The divide ratio is 8 and the clock rate is (input clock)/8.
- */
-//@{
-#define BP_ADC_CFG1_ADIV (5U) //!< Bit position for ADC_CFG1_ADIV.
-#define BM_ADC_CFG1_ADIV (0x00000060U) //!< Bit mask for ADC_CFG1_ADIV.
-#define BS_ADC_CFG1_ADIV (2U) //!< Bit field size in bits for ADC_CFG1_ADIV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_CFG1_ADIV field.
-#define BR_ADC_CFG1_ADIV(x) (HW_ADC_CFG1(x).B.ADIV)
-#endif
-
-//! @brief Format value for bitfield ADC_CFG1_ADIV.
-#define BF_ADC_CFG1_ADIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG1_ADIV), uint32_t) & BM_ADC_CFG1_ADIV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ADIV field to a new value.
-#define BW_ADC_CFG1_ADIV(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_ADIV) | BF_ADC_CFG1_ADIV(v)))
-#endif
-//@}
-
-/*!
- * @name Register ADC_CFG1, field ADLPC[7] (RW)
- *
- * Controls the power configuration of the successive approximation converter.
- * This optimizes power consumption when higher sample rates are not required.
- *
- * Values:
- * - 0 - Normal power configuration.
- * - 1 - Low-power configuration. The power is reduced at the expense of maximum
- * clock speed.
- */
-//@{
-#define BP_ADC_CFG1_ADLPC (7U) //!< Bit position for ADC_CFG1_ADLPC.
-#define BM_ADC_CFG1_ADLPC (0x00000080U) //!< Bit mask for ADC_CFG1_ADLPC.
-#define BS_ADC_CFG1_ADLPC (1U) //!< Bit field size in bits for ADC_CFG1_ADLPC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_CFG1_ADLPC field.
-#define BR_ADC_CFG1_ADLPC(x) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLPC))
-#endif
-
-//! @brief Format value for bitfield ADC_CFG1_ADLPC.
-#define BF_ADC_CFG1_ADLPC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG1_ADLPC), uint32_t) & BM_ADC_CFG1_ADLPC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ADLPC field to a new value.
-#define BW_ADC_CFG1_ADLPC(x, v) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLPC) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ADC_CFG2 - ADC Configuration Register 2
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ADC_CFG2 - ADC Configuration Register 2 (RW)
- *
- * Reset value: 0x00000000U
- *
- * Configuration Register 2 (CFG2) selects the special high-speed configuration
- * for very high speed conversions and selects the long sample time duration
- * during long sample mode.
- */
-typedef union _hw_adc_cfg2
-{
- uint32_t U;
- struct _hw_adc_cfg2_bitfields
- {
- uint32_t ADLSTS : 2; //!< [1:0] Long Sample Time Select
- uint32_t ADHSC : 1; //!< [2] High-Speed Configuration
- uint32_t ADACKEN : 1; //!< [3] Asynchronous Clock Output Enable
- uint32_t MUXSEL : 1; //!< [4] ADC Mux Select
- uint32_t RESERVED0 : 27; //!< [31:5]
- } B;
-} hw_adc_cfg2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ADC_CFG2 register
- */
-//@{
-#define HW_ADC_CFG2_ADDR(x) (REGS_ADC_BASE(x) + 0xCU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ADC_CFG2(x) (*(__IO hw_adc_cfg2_t *) HW_ADC_CFG2_ADDR(x))
-#define HW_ADC_CFG2_RD(x) (HW_ADC_CFG2(x).U)
-#define HW_ADC_CFG2_WR(x, v) (HW_ADC_CFG2(x).U = (v))
-#define HW_ADC_CFG2_SET(x, v) (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) | (v)))
-#define HW_ADC_CFG2_CLR(x, v) (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) & ~(v)))
-#define HW_ADC_CFG2_TOG(x, v) (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ADC_CFG2 bitfields
- */
-
-/*!
- * @name Register ADC_CFG2, field ADLSTS[1:0] (RW)
- *
- * Selects between the extended sample times when long sample time is selected,
- * that is, when CFG1[ADLSMP]=1. This allows higher impedance inputs to be
- * accurately sampled or to maximize conversion speed for lower impedance inputs.
- * Longer sample times can also be used to lower overall power consumption when
- * continuous conversions are enabled if high conversion rates are not required.
- *
- * Values:
- * - 00 - Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles
- * total.
- * - 01 - 12 extra ADCK cycles; 16 ADCK cycles total sample time.
- * - 10 - 6 extra ADCK cycles; 10 ADCK cycles total sample time.
- * - 11 - 2 extra ADCK cycles; 6 ADCK cycles total sample time.
- */
-//@{
-#define BP_ADC_CFG2_ADLSTS (0U) //!< Bit position for ADC_CFG2_ADLSTS.
-#define BM_ADC_CFG2_ADLSTS (0x00000003U) //!< Bit mask for ADC_CFG2_ADLSTS.
-#define BS_ADC_CFG2_ADLSTS (2U) //!< Bit field size in bits for ADC_CFG2_ADLSTS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_CFG2_ADLSTS field.
-#define BR_ADC_CFG2_ADLSTS(x) (HW_ADC_CFG2(x).B.ADLSTS)
-#endif
-
-//! @brief Format value for bitfield ADC_CFG2_ADLSTS.
-#define BF_ADC_CFG2_ADLSTS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG2_ADLSTS), uint32_t) & BM_ADC_CFG2_ADLSTS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ADLSTS field to a new value.
-#define BW_ADC_CFG2_ADLSTS(x, v) (HW_ADC_CFG2_WR(x, (HW_ADC_CFG2_RD(x) & ~BM_ADC_CFG2_ADLSTS) | BF_ADC_CFG2_ADLSTS(v)))
-#endif
-//@}
-
-/*!
- * @name Register ADC_CFG2, field ADHSC[2] (RW)
- *
- * Configures the ADC for very high-speed operation. The conversion sequence is
- * altered with 2 ADCK cycles added to the conversion time to allow higher speed
- * conversion clocks.
- *
- * Values:
- * - 0 - Normal conversion sequence selected.
- * - 1 - High-speed conversion sequence selected with 2 additional ADCK cycles
- * to total conversion time.
- */
-//@{
-#define BP_ADC_CFG2_ADHSC (2U) //!< Bit position for ADC_CFG2_ADHSC.
-#define BM_ADC_CFG2_ADHSC (0x00000004U) //!< Bit mask for ADC_CFG2_ADHSC.
-#define BS_ADC_CFG2_ADHSC (1U) //!< Bit field size in bits for ADC_CFG2_ADHSC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_CFG2_ADHSC field.
-#define BR_ADC_CFG2_ADHSC(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADHSC))
-#endif
-
-//! @brief Format value for bitfield ADC_CFG2_ADHSC.
-#define BF_ADC_CFG2_ADHSC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG2_ADHSC), uint32_t) & BM_ADC_CFG2_ADHSC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ADHSC field to a new value.
-#define BW_ADC_CFG2_ADHSC(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADHSC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ADC_CFG2, field ADACKEN[3] (RW)
- *
- * Enables the asynchronous clock source and the clock source output regardless
- * of the conversion and status of CFG1[ADICLK]. Based on MCU configuration, the
- * asynchronous clock may be used by other modules. See chip configuration
- * information. Setting this field allows the clock to be used even while the ADC is
- * idle or operating from a different clock source. Also, latency of initiating a
- * single or first-continuous conversion with the asynchronous clock selected is
- * reduced because the ADACK clock is already operational.
- *
- * Values:
- * - 0 - Asynchronous clock output disabled; Asynchronous clock is enabled only
- * if selected by ADICLK and a conversion is active.
- * - 1 - Asynchronous clock and clock output is enabled regardless of the state
- * of the ADC.
- */
-//@{
-#define BP_ADC_CFG2_ADACKEN (3U) //!< Bit position for ADC_CFG2_ADACKEN.
-#define BM_ADC_CFG2_ADACKEN (0x00000008U) //!< Bit mask for ADC_CFG2_ADACKEN.
-#define BS_ADC_CFG2_ADACKEN (1U) //!< Bit field size in bits for ADC_CFG2_ADACKEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_CFG2_ADACKEN field.
-#define BR_ADC_CFG2_ADACKEN(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADACKEN))
-#endif
-
-//! @brief Format value for bitfield ADC_CFG2_ADACKEN.
-#define BF_ADC_CFG2_ADACKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG2_ADACKEN), uint32_t) & BM_ADC_CFG2_ADACKEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ADACKEN field to a new value.
-#define BW_ADC_CFG2_ADACKEN(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADACKEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ADC_CFG2, field MUXSEL[4] (RW)
- *
- * Changes the ADC mux setting to select between alternate sets of ADC channels.
- *
- * Values:
- * - 0 - ADxxa channels are selected.
- * - 1 - ADxxb channels are selected.
- */
-//@{
-#define BP_ADC_CFG2_MUXSEL (4U) //!< Bit position for ADC_CFG2_MUXSEL.
-#define BM_ADC_CFG2_MUXSEL (0x00000010U) //!< Bit mask for ADC_CFG2_MUXSEL.
-#define BS_ADC_CFG2_MUXSEL (1U) //!< Bit field size in bits for ADC_CFG2_MUXSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_CFG2_MUXSEL field.
-#define BR_ADC_CFG2_MUXSEL(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_MUXSEL))
-#endif
-
-//! @brief Format value for bitfield ADC_CFG2_MUXSEL.
-#define BF_ADC_CFG2_MUXSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG2_MUXSEL), uint32_t) & BM_ADC_CFG2_MUXSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MUXSEL field to a new value.
-#define BW_ADC_CFG2_MUXSEL(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_MUXSEL) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ADC_Rn - ADC Data Result Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ADC_Rn - ADC Data Result Register (RO)
- *
- * Reset value: 0x00000000U
- *
- * The data result registers (Rn) contain the result of an ADC conversion of the
- * channel selected by the corresponding status and channel control register
- * (SC1A:SC1n). For every status and channel control register, there is a
- * corresponding data result register. Unused bits in R n are cleared in unsigned
- * right-aligned modes and carry the sign bit (MSB) in sign-extended 2's complement modes.
- * For example, when configured for 10-bit single-ended mode, D[15:10] are
- * cleared. When configured for 11-bit differential mode, D[15:10] carry the sign bit,
- * that is, bit 10 extended through bit 15. The following table describes the
- * behavior of the data result registers in the different modes of operation. Data
- * result register description Conversion mode D15 D14 D13 D12 D11 D10 D9 D8 D7
- * D6 D5 D4 D3 D2 D1 D0 Format 16-bit differential S D D D D D D D D D D D D D D D
- * Signed 2's complement 16-bit single-ended D D D D D D D D D D D D D D D D
- * Unsigned right justified 13-bit differential S S S S D D D D D D D D D D D D
- * Sign-extended 2's complement 12-bit single-ended 0 0 0 0 D D D D D D D D D D D D
- * Unsigned right-justified 11-bit differential S S S S S S D D D D D D D D D D
- * Sign-extended 2's complement 10-bit single-ended 0 0 0 0 0 0 D D D D D D D D D D
- * Unsigned right-justified 9-bit differential S S S S S S S S D D D D D D D D
- * Sign-extended 2's complement 8-bit single-ended 0 0 0 0 0 0 0 0 D D D D D D D D
- * Unsigned right-justified S: Sign bit or sign bit extension; D: Data, which is
- * 2's complement data if indicated
- */
-typedef union _hw_adc_rn
-{
- uint32_t U;
- struct _hw_adc_rn_bitfields
- {
- uint32_t D : 16; //!< [15:0] Data result
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_adc_rn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ADC_Rn register
- */
-//@{
-#define HW_ADC_Rn_COUNT (2U)
-
-#define HW_ADC_Rn_ADDR(x, n) (REGS_ADC_BASE(x) + 0x10U + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ADC_Rn(x, n) (*(__I hw_adc_rn_t *) HW_ADC_Rn_ADDR(x, n))
-#define HW_ADC_Rn_RD(x, n) (HW_ADC_Rn(x, n).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ADC_Rn bitfields
- */
-
-/*!
- * @name Register ADC_Rn, field D[15:0] (RO)
- */
-//@{
-#define BP_ADC_Rn_D (0U) //!< Bit position for ADC_Rn_D.
-#define BM_ADC_Rn_D (0x0000FFFFU) //!< Bit mask for ADC_Rn_D.
-#define BS_ADC_Rn_D (16U) //!< Bit field size in bits for ADC_Rn_D.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_Rn_D field.
-#define BR_ADC_Rn_D(x, n) (HW_ADC_Rn(x, n).B.D)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ADC_CV1 - Compare Value Registers
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ADC_CV1 - Compare Value Registers (RW)
- *
- * Reset value: 0x00000000U
- *
- * The Compare Value Registers (CV1 and CV2) contain a compare value used to
- * compare the conversion result when the compare function is enabled, that is,
- * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
- * different modes of operation for both bit position definition and value format
- * using unsigned or sign-extended 2's complement. Therefore, the compare function
- * uses only the CVn fields that are related to the ADC mode of operation. The
- * compare value 2 register (CV2) is used only when the compare range function is
- * enabled, that is, SC2[ACREN]=1.
- */
-typedef union _hw_adc_cv1
-{
- uint32_t U;
- struct _hw_adc_cv1_bitfields
- {
- uint32_t CV : 16; //!< [15:0] Compare Value.
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_adc_cv1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ADC_CV1 register
- */
-//@{
-#define HW_ADC_CV1_ADDR(x) (REGS_ADC_BASE(x) + 0x18U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ADC_CV1(x) (*(__IO hw_adc_cv1_t *) HW_ADC_CV1_ADDR(x))
-#define HW_ADC_CV1_RD(x) (HW_ADC_CV1(x).U)
-#define HW_ADC_CV1_WR(x, v) (HW_ADC_CV1(x).U = (v))
-#define HW_ADC_CV1_SET(x, v) (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) | (v)))
-#define HW_ADC_CV1_CLR(x, v) (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) & ~(v)))
-#define HW_ADC_CV1_TOG(x, v) (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ADC_CV1 bitfields
- */
-
-/*!
- * @name Register ADC_CV1, field CV[15:0] (RW)
- */
-//@{
-#define BP_ADC_CV1_CV (0U) //!< Bit position for ADC_CV1_CV.
-#define BM_ADC_CV1_CV (0x0000FFFFU) //!< Bit mask for ADC_CV1_CV.
-#define BS_ADC_CV1_CV (16U) //!< Bit field size in bits for ADC_CV1_CV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_CV1_CV field.
-#define BR_ADC_CV1_CV(x) (HW_ADC_CV1(x).B.CV)
-#endif
-
-//! @brief Format value for bitfield ADC_CV1_CV.
-#define BF_ADC_CV1_CV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CV1_CV), uint32_t) & BM_ADC_CV1_CV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CV field to a new value.
-#define BW_ADC_CV1_CV(x, v) (HW_ADC_CV1_WR(x, (HW_ADC_CV1_RD(x) & ~BM_ADC_CV1_CV) | BF_ADC_CV1_CV(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ADC_CV2 - Compare Value Registers
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ADC_CV2 - Compare Value Registers (RW)
- *
- * Reset value: 0x00000000U
- *
- * The Compare Value Registers (CV1 and CV2) contain a compare value used to
- * compare the conversion result when the compare function is enabled, that is,
- * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
- * different modes of operation for both bit position definition and value format
- * using unsigned or sign-extended 2's complement. Therefore, the compare function
- * uses only the CVn fields that are related to the ADC mode of operation. The
- * compare value 2 register (CV2) is used only when the compare range function is
- * enabled, that is, SC2[ACREN]=1.
- */
-typedef union _hw_adc_cv2
-{
- uint32_t U;
- struct _hw_adc_cv2_bitfields
- {
- uint32_t CV : 16; //!< [15:0] Compare Value.
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_adc_cv2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ADC_CV2 register
- */
-//@{
-#define HW_ADC_CV2_ADDR(x) (REGS_ADC_BASE(x) + 0x1CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ADC_CV2(x) (*(__IO hw_adc_cv2_t *) HW_ADC_CV2_ADDR(x))
-#define HW_ADC_CV2_RD(x) (HW_ADC_CV2(x).U)
-#define HW_ADC_CV2_WR(x, v) (HW_ADC_CV2(x).U = (v))
-#define HW_ADC_CV2_SET(x, v) (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) | (v)))
-#define HW_ADC_CV2_CLR(x, v) (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) & ~(v)))
-#define HW_ADC_CV2_TOG(x, v) (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ADC_CV2 bitfields
- */
-
-/*!
- * @name Register ADC_CV2, field CV[15:0] (RW)
- */
-//@{
-#define BP_ADC_CV2_CV (0U) //!< Bit position for ADC_CV2_CV.
-#define BM_ADC_CV2_CV (0x0000FFFFU) //!< Bit mask for ADC_CV2_CV.
-#define BS_ADC_CV2_CV (16U) //!< Bit field size in bits for ADC_CV2_CV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_CV2_CV field.
-#define BR_ADC_CV2_CV(x) (HW_ADC_CV2(x).B.CV)
-#endif
-
-//! @brief Format value for bitfield ADC_CV2_CV.
-#define BF_ADC_CV2_CV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CV2_CV), uint32_t) & BM_ADC_CV2_CV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CV field to a new value.
-#define BW_ADC_CV2_CV(x, v) (HW_ADC_CV2_WR(x, (HW_ADC_CV2_RD(x) & ~BM_ADC_CV2_CV) | BF_ADC_CV2_CV(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ADC_SC2 - Status and Control Register 2
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ADC_SC2 - Status and Control Register 2 (RW)
- *
- * Reset value: 0x00000000U
- *
- * The status and control register 2 (SC2) contains the conversion active,
- * hardware/software trigger select, compare function, and voltage reference select of
- * the ADC module.
- */
-typedef union _hw_adc_sc2
-{
- uint32_t U;
- struct _hw_adc_sc2_bitfields
- {
- uint32_t REFSEL : 2; //!< [1:0] Voltage Reference Selection
- uint32_t DMAEN : 1; //!< [2] DMA Enable
- uint32_t ACREN : 1; //!< [3] Compare Function Range Enable
- uint32_t ACFGT : 1; //!< [4] Compare Function Greater Than Enable
- uint32_t ACFE : 1; //!< [5] Compare Function Enable
- uint32_t ADTRG : 1; //!< [6] Conversion Trigger Select
- uint32_t ADACT : 1; //!< [7] Conversion Active
- uint32_t RESERVED0 : 24; //!< [31:8]
- } B;
-} hw_adc_sc2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ADC_SC2 register
- */
-//@{
-#define HW_ADC_SC2_ADDR(x) (REGS_ADC_BASE(x) + 0x20U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ADC_SC2(x) (*(__IO hw_adc_sc2_t *) HW_ADC_SC2_ADDR(x))
-#define HW_ADC_SC2_RD(x) (HW_ADC_SC2(x).U)
-#define HW_ADC_SC2_WR(x, v) (HW_ADC_SC2(x).U = (v))
-#define HW_ADC_SC2_SET(x, v) (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) | (v)))
-#define HW_ADC_SC2_CLR(x, v) (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) & ~(v)))
-#define HW_ADC_SC2_TOG(x, v) (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ADC_SC2 bitfields
- */
-
-/*!
- * @name Register ADC_SC2, field REFSEL[1:0] (RW)
- *
- * Selects the voltage reference source used for conversions.
- *
- * Values:
- * - 00 - Default voltage reference pin pair, that is, external pins VREFH and
- * VREFL
- * - 01 - Alternate reference pair, that is, VALTH and VALTL . This pair may be
- * additional external pins or internal sources depending on the MCU
- * configuration. See the chip configuration information for details specific to this
- * MCU
- * - 10 - Reserved
- * - 11 - Reserved
- */
-//@{
-#define BP_ADC_SC2_REFSEL (0U) //!< Bit position for ADC_SC2_REFSEL.
-#define BM_ADC_SC2_REFSEL (0x00000003U) //!< Bit mask for ADC_SC2_REFSEL.
-#define BS_ADC_SC2_REFSEL (2U) //!< Bit field size in bits for ADC_SC2_REFSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_SC2_REFSEL field.
-#define BR_ADC_SC2_REFSEL(x) (HW_ADC_SC2(x).B.REFSEL)
-#endif
-
-//! @brief Format value for bitfield ADC_SC2_REFSEL.
-#define BF_ADC_SC2_REFSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_REFSEL), uint32_t) & BM_ADC_SC2_REFSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the REFSEL field to a new value.
-#define BW_ADC_SC2_REFSEL(x, v) (HW_ADC_SC2_WR(x, (HW_ADC_SC2_RD(x) & ~BM_ADC_SC2_REFSEL) | BF_ADC_SC2_REFSEL(v)))
-#endif
-//@}
-
-/*!
- * @name Register ADC_SC2, field DMAEN[2] (RW)
- *
- * Values:
- * - 0 - DMA is disabled.
- * - 1 - DMA is enabled and will assert the ADC DMA request during an ADC
- * conversion complete event noted when any of the SC1n[COCO] flags is asserted.
- */
-//@{
-#define BP_ADC_SC2_DMAEN (2U) //!< Bit position for ADC_SC2_DMAEN.
-#define BM_ADC_SC2_DMAEN (0x00000004U) //!< Bit mask for ADC_SC2_DMAEN.
-#define BS_ADC_SC2_DMAEN (1U) //!< Bit field size in bits for ADC_SC2_DMAEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_SC2_DMAEN field.
-#define BR_ADC_SC2_DMAEN(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_DMAEN))
-#endif
-
-//! @brief Format value for bitfield ADC_SC2_DMAEN.
-#define BF_ADC_SC2_DMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_DMAEN), uint32_t) & BM_ADC_SC2_DMAEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DMAEN field to a new value.
-#define BW_ADC_SC2_DMAEN(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_DMAEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ADC_SC2, field ACREN[3] (RW)
- *
- * Configures the compare function to check if the conversion result of the
- * input being monitored is either between or outside the range formed by CV1 and CV2
- * determined by the value of ACFGT. ACFE must be set for ACFGT to have any
- * effect.
- *
- * Values:
- * - 0 - Range function disabled. Only CV1 is compared.
- * - 1 - Range function enabled. Both CV1 and CV2 are compared.
- */
-//@{
-#define BP_ADC_SC2_ACREN (3U) //!< Bit position for ADC_SC2_ACREN.
-#define BM_ADC_SC2_ACREN (0x00000008U) //!< Bit mask for ADC_SC2_ACREN.
-#define BS_ADC_SC2_ACREN (1U) //!< Bit field size in bits for ADC_SC2_ACREN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_SC2_ACREN field.
-#define BR_ADC_SC2_ACREN(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACREN))
-#endif
-
-//! @brief Format value for bitfield ADC_SC2_ACREN.
-#define BF_ADC_SC2_ACREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_ACREN), uint32_t) & BM_ADC_SC2_ACREN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ACREN field to a new value.
-#define BW_ADC_SC2_ACREN(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACREN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ADC_SC2, field ACFGT[4] (RW)
- *
- * Configures the compare function to check the conversion result relative to
- * the CV1 and CV2 based upon the value of ACREN. ACFE must be set for ACFGT to
- * have any effect.
- *
- * Values:
- * - 0 - Configures less than threshold, outside range not inclusive and inside
- * range not inclusive; functionality based on the values placed in CV1 and
- * CV2.
- * - 1 - Configures greater than or equal to threshold, outside and inside
- * ranges inclusive; functionality based on the values placed in CV1 and CV2.
- */
-//@{
-#define BP_ADC_SC2_ACFGT (4U) //!< Bit position for ADC_SC2_ACFGT.
-#define BM_ADC_SC2_ACFGT (0x00000010U) //!< Bit mask for ADC_SC2_ACFGT.
-#define BS_ADC_SC2_ACFGT (1U) //!< Bit field size in bits for ADC_SC2_ACFGT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_SC2_ACFGT field.
-#define BR_ADC_SC2_ACFGT(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFGT))
-#endif
-
-//! @brief Format value for bitfield ADC_SC2_ACFGT.
-#define BF_ADC_SC2_ACFGT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_ACFGT), uint32_t) & BM_ADC_SC2_ACFGT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ACFGT field to a new value.
-#define BW_ADC_SC2_ACFGT(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFGT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ADC_SC2, field ACFE[5] (RW)
- *
- * Enables the compare function.
- *
- * Values:
- * - 0 - Compare function disabled.
- * - 1 - Compare function enabled.
- */
-//@{
-#define BP_ADC_SC2_ACFE (5U) //!< Bit position for ADC_SC2_ACFE.
-#define BM_ADC_SC2_ACFE (0x00000020U) //!< Bit mask for ADC_SC2_ACFE.
-#define BS_ADC_SC2_ACFE (1U) //!< Bit field size in bits for ADC_SC2_ACFE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_SC2_ACFE field.
-#define BR_ADC_SC2_ACFE(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFE))
-#endif
-
-//! @brief Format value for bitfield ADC_SC2_ACFE.
-#define BF_ADC_SC2_ACFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_ACFE), uint32_t) & BM_ADC_SC2_ACFE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ACFE field to a new value.
-#define BW_ADC_SC2_ACFE(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ADC_SC2, field ADTRG[6] (RW)
- *
- * Selects the type of trigger used for initiating a conversion. Two types of
- * trigger are selectable: Software trigger: When software trigger is selected, a
- * conversion is initiated following a write to SC1A. Hardware trigger: When
- * hardware trigger is selected, a conversion is initiated following the assertion of
- * the ADHWT input after a pulse of the ADHWTSn input.
- *
- * Values:
- * - 0 - Software trigger selected.
- * - 1 - Hardware trigger selected.
- */
-//@{
-#define BP_ADC_SC2_ADTRG (6U) //!< Bit position for ADC_SC2_ADTRG.
-#define BM_ADC_SC2_ADTRG (0x00000040U) //!< Bit mask for ADC_SC2_ADTRG.
-#define BS_ADC_SC2_ADTRG (1U) //!< Bit field size in bits for ADC_SC2_ADTRG.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_SC2_ADTRG field.
-#define BR_ADC_SC2_ADTRG(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADTRG))
-#endif
-
-//! @brief Format value for bitfield ADC_SC2_ADTRG.
-#define BF_ADC_SC2_ADTRG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_ADTRG), uint32_t) & BM_ADC_SC2_ADTRG)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ADTRG field to a new value.
-#define BW_ADC_SC2_ADTRG(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADTRG) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ADC_SC2, field ADACT[7] (RO)
- *
- * Indicates that a conversion or hardware averaging is in progress. ADACT is
- * set when a conversion is initiated and cleared when a conversion is completed or
- * aborted.
- *
- * Values:
- * - 0 - Conversion not in progress.
- * - 1 - Conversion in progress.
- */
-//@{
-#define BP_ADC_SC2_ADACT (7U) //!< Bit position for ADC_SC2_ADACT.
-#define BM_ADC_SC2_ADACT (0x00000080U) //!< Bit mask for ADC_SC2_ADACT.
-#define BS_ADC_SC2_ADACT (1U) //!< Bit field size in bits for ADC_SC2_ADACT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_SC2_ADACT field.
-#define BR_ADC_SC2_ADACT(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADACT))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ADC_SC3 - Status and Control Register 3
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ADC_SC3 - Status and Control Register 3 (RW)
- *
- * Reset value: 0x00000000U
- *
- * The Status and Control Register 3 (SC3) controls the calibration, continuous
- * convert, and hardware averaging functions of the ADC module.
- */
-typedef union _hw_adc_sc3
-{
- uint32_t U;
- struct _hw_adc_sc3_bitfields
- {
- uint32_t AVGS : 2; //!< [1:0] Hardware Average Select
- uint32_t AVGE : 1; //!< [2] Hardware Average Enable
- uint32_t ADCO : 1; //!< [3] Continuous Conversion Enable
- uint32_t RESERVED0 : 2; //!< [5:4]
- uint32_t CALF : 1; //!< [6] Calibration Failed Flag
- uint32_t CAL : 1; //!< [7] Calibration
- uint32_t RESERVED1 : 24; //!< [31:8]
- } B;
-} hw_adc_sc3_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ADC_SC3 register
- */
-//@{
-#define HW_ADC_SC3_ADDR(x) (REGS_ADC_BASE(x) + 0x24U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ADC_SC3(x) (*(__IO hw_adc_sc3_t *) HW_ADC_SC3_ADDR(x))
-#define HW_ADC_SC3_RD(x) (HW_ADC_SC3(x).U)
-#define HW_ADC_SC3_WR(x, v) (HW_ADC_SC3(x).U = (v))
-#define HW_ADC_SC3_SET(x, v) (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) | (v)))
-#define HW_ADC_SC3_CLR(x, v) (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) & ~(v)))
-#define HW_ADC_SC3_TOG(x, v) (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ADC_SC3 bitfields
- */
-
-/*!
- * @name Register ADC_SC3, field AVGS[1:0] (RW)
- *
- * Determines how many ADC conversions will be averaged to create the ADC
- * average result.
- *
- * Values:
- * - 00 - 4 samples averaged.
- * - 01 - 8 samples averaged.
- * - 10 - 16 samples averaged.
- * - 11 - 32 samples averaged.
- */
-//@{
-#define BP_ADC_SC3_AVGS (0U) //!< Bit position for ADC_SC3_AVGS.
-#define BM_ADC_SC3_AVGS (0x00000003U) //!< Bit mask for ADC_SC3_AVGS.
-#define BS_ADC_SC3_AVGS (2U) //!< Bit field size in bits for ADC_SC3_AVGS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_SC3_AVGS field.
-#define BR_ADC_SC3_AVGS(x) (HW_ADC_SC3(x).B.AVGS)
-#endif
-
-//! @brief Format value for bitfield ADC_SC3_AVGS.
-#define BF_ADC_SC3_AVGS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC3_AVGS), uint32_t) & BM_ADC_SC3_AVGS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the AVGS field to a new value.
-#define BW_ADC_SC3_AVGS(x, v) (HW_ADC_SC3_WR(x, (HW_ADC_SC3_RD(x) & ~BM_ADC_SC3_AVGS) | BF_ADC_SC3_AVGS(v)))
-#endif
-//@}
-
-/*!
- * @name Register ADC_SC3, field AVGE[2] (RW)
- *
- * Enables the hardware average function of the ADC.
- *
- * Values:
- * - 0 - Hardware average function disabled.
- * - 1 - Hardware average function enabled.
- */
-//@{
-#define BP_ADC_SC3_AVGE (2U) //!< Bit position for ADC_SC3_AVGE.
-#define BM_ADC_SC3_AVGE (0x00000004U) //!< Bit mask for ADC_SC3_AVGE.
-#define BS_ADC_SC3_AVGE (1U) //!< Bit field size in bits for ADC_SC3_AVGE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_SC3_AVGE field.
-#define BR_ADC_SC3_AVGE(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_AVGE))
-#endif
-
-//! @brief Format value for bitfield ADC_SC3_AVGE.
-#define BF_ADC_SC3_AVGE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC3_AVGE), uint32_t) & BM_ADC_SC3_AVGE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the AVGE field to a new value.
-#define BW_ADC_SC3_AVGE(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_AVGE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ADC_SC3, field ADCO[3] (RW)
- *
- * Enables continuous conversions.
- *
- * Values:
- * - 0 - One conversion or one set of conversions if the hardware average
- * function is enabled, that is, AVGE=1, after initiating a conversion.
- * - 1 - Continuous conversions or sets of conversions if the hardware average
- * function is enabled, that is, AVGE=1, after initiating a conversion.
- */
-//@{
-#define BP_ADC_SC3_ADCO (3U) //!< Bit position for ADC_SC3_ADCO.
-#define BM_ADC_SC3_ADCO (0x00000008U) //!< Bit mask for ADC_SC3_ADCO.
-#define BS_ADC_SC3_ADCO (1U) //!< Bit field size in bits for ADC_SC3_ADCO.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_SC3_ADCO field.
-#define BR_ADC_SC3_ADCO(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_ADCO))
-#endif
-
-//! @brief Format value for bitfield ADC_SC3_ADCO.
-#define BF_ADC_SC3_ADCO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC3_ADCO), uint32_t) & BM_ADC_SC3_ADCO)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ADCO field to a new value.
-#define BW_ADC_SC3_ADCO(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_ADCO) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ADC_SC3, field CALF[6] (RO)
- *
- * Displays the result of the calibration sequence. The calibration sequence
- * will fail if SC2[ADTRG] = 1, any ADC register is written, or any stop mode is
- * entered before the calibration sequence completes. Writing 1 to CALF clears it.
- *
- * Values:
- * - 0 - Calibration completed normally.
- * - 1 - Calibration failed. ADC accuracy specifications are not guaranteed.
- */
-//@{
-#define BP_ADC_SC3_CALF (6U) //!< Bit position for ADC_SC3_CALF.
-#define BM_ADC_SC3_CALF (0x00000040U) //!< Bit mask for ADC_SC3_CALF.
-#define BS_ADC_SC3_CALF (1U) //!< Bit field size in bits for ADC_SC3_CALF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_SC3_CALF field.
-#define BR_ADC_SC3_CALF(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CALF))
-#endif
-//@}
-
-/*!
- * @name Register ADC_SC3, field CAL[7] (RW)
- *
- * Begins the calibration sequence when set. This field stays set while the
- * calibration is in progress and is cleared when the calibration sequence is
- * completed. CALF must be checked to determine the result of the calibration sequence.
- * Once started, the calibration routine cannot be interrupted by writes to the
- * ADC registers or the results will be invalid and CALF will set. Setting CAL
- * will abort any current conversion.
- */
-//@{
-#define BP_ADC_SC3_CAL (7U) //!< Bit position for ADC_SC3_CAL.
-#define BM_ADC_SC3_CAL (0x00000080U) //!< Bit mask for ADC_SC3_CAL.
-#define BS_ADC_SC3_CAL (1U) //!< Bit field size in bits for ADC_SC3_CAL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_SC3_CAL field.
-#define BR_ADC_SC3_CAL(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CAL))
-#endif
-
-//! @brief Format value for bitfield ADC_SC3_CAL.
-#define BF_ADC_SC3_CAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC3_CAL), uint32_t) & BM_ADC_SC3_CAL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CAL field to a new value.
-#define BW_ADC_SC3_CAL(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CAL) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ADC_OFS - ADC Offset Correction Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ADC_OFS - ADC Offset Correction Register (RW)
- *
- * Reset value: 0x00000004U
- *
- * The ADC Offset Correction Register (OFS) contains the user-selected or
- * calibration-generated offset error correction value. This register is a 2's
- * complement, left-justified, 16-bit value . The value in OFS is subtracted from the
- * conversion and the result is transferred into the result registers, Rn. If the
- * result is greater than the maximum or less than the minimum result value, it is
- * forced to the appropriate limit for the current mode of operation.
- */
-typedef union _hw_adc_ofs
-{
- uint32_t U;
- struct _hw_adc_ofs_bitfields
- {
- uint32_t OFS : 16; //!< [15:0] Offset Error Correction Value
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_adc_ofs_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ADC_OFS register
- */
-//@{
-#define HW_ADC_OFS_ADDR(x) (REGS_ADC_BASE(x) + 0x28U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ADC_OFS(x) (*(__IO hw_adc_ofs_t *) HW_ADC_OFS_ADDR(x))
-#define HW_ADC_OFS_RD(x) (HW_ADC_OFS(x).U)
-#define HW_ADC_OFS_WR(x, v) (HW_ADC_OFS(x).U = (v))
-#define HW_ADC_OFS_SET(x, v) (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) | (v)))
-#define HW_ADC_OFS_CLR(x, v) (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) & ~(v)))
-#define HW_ADC_OFS_TOG(x, v) (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ADC_OFS bitfields
- */
-
-/*!
- * @name Register ADC_OFS, field OFS[15:0] (RW)
- */
-//@{
-#define BP_ADC_OFS_OFS (0U) //!< Bit position for ADC_OFS_OFS.
-#define BM_ADC_OFS_OFS (0x0000FFFFU) //!< Bit mask for ADC_OFS_OFS.
-#define BS_ADC_OFS_OFS (16U) //!< Bit field size in bits for ADC_OFS_OFS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_OFS_OFS field.
-#define BR_ADC_OFS_OFS(x) (HW_ADC_OFS(x).B.OFS)
-#endif
-
-//! @brief Format value for bitfield ADC_OFS_OFS.
-#define BF_ADC_OFS_OFS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_OFS_OFS), uint32_t) & BM_ADC_OFS_OFS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the OFS field to a new value.
-#define BW_ADC_OFS_OFS(x, v) (HW_ADC_OFS_WR(x, (HW_ADC_OFS_RD(x) & ~BM_ADC_OFS_OFS) | BF_ADC_OFS_OFS(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ADC_PG - ADC Plus-Side Gain Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ADC_PG - ADC Plus-Side Gain Register (RW)
- *
- * Reset value: 0x00008200U
- *
- * The Plus-Side Gain Register (PG) contains the gain error correction for the
- * plus-side input in differential mode or the overall conversion in single-ended
- * mode. PG, a 16-bit real number in binary format, is the gain adjustment
- * factor, with the radix point fixed between ADPG15 and ADPG14. This register must be
- * written by the user with the value described in the calibration procedure.
- * Otherwise, the gain error specifications may not be met.
- */
-typedef union _hw_adc_pg
-{
- uint32_t U;
- struct _hw_adc_pg_bitfields
- {
- uint32_t PG : 16; //!< [15:0] Plus-Side Gain
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_adc_pg_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ADC_PG register
- */
-//@{
-#define HW_ADC_PG_ADDR(x) (REGS_ADC_BASE(x) + 0x2CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ADC_PG(x) (*(__IO hw_adc_pg_t *) HW_ADC_PG_ADDR(x))
-#define HW_ADC_PG_RD(x) (HW_ADC_PG(x).U)
-#define HW_ADC_PG_WR(x, v) (HW_ADC_PG(x).U = (v))
-#define HW_ADC_PG_SET(x, v) (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) | (v)))
-#define HW_ADC_PG_CLR(x, v) (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) & ~(v)))
-#define HW_ADC_PG_TOG(x, v) (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ADC_PG bitfields
- */
-
-/*!
- * @name Register ADC_PG, field PG[15:0] (RW)
- */
-//@{
-#define BP_ADC_PG_PG (0U) //!< Bit position for ADC_PG_PG.
-#define BM_ADC_PG_PG (0x0000FFFFU) //!< Bit mask for ADC_PG_PG.
-#define BS_ADC_PG_PG (16U) //!< Bit field size in bits for ADC_PG_PG.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_PG_PG field.
-#define BR_ADC_PG_PG(x) (HW_ADC_PG(x).B.PG)
-#endif
-
-//! @brief Format value for bitfield ADC_PG_PG.
-#define BF_ADC_PG_PG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_PG_PG), uint32_t) & BM_ADC_PG_PG)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PG field to a new value.
-#define BW_ADC_PG_PG(x, v) (HW_ADC_PG_WR(x, (HW_ADC_PG_RD(x) & ~BM_ADC_PG_PG) | BF_ADC_PG_PG(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ADC_MG - ADC Minus-Side Gain Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ADC_MG - ADC Minus-Side Gain Register (RW)
- *
- * Reset value: 0x00008200U
- *
- * The Minus-Side Gain Register (MG) contains the gain error correction for the
- * minus-side input in differential mode. This register is ignored in
- * single-ended mode. MG, a 16-bit real number in binary format, is the gain adjustment
- * factor, with the radix point fixed between ADMG15 and ADMG14. This register must
- * be written by the user with the value described in the calibration procedure.
- * Otherwise, the gain error specifications may not be met.
- */
-typedef union _hw_adc_mg
-{
- uint32_t U;
- struct _hw_adc_mg_bitfields
- {
- uint32_t MG : 16; //!< [15:0] Minus-Side Gain
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_adc_mg_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ADC_MG register
- */
-//@{
-#define HW_ADC_MG_ADDR(x) (REGS_ADC_BASE(x) + 0x30U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ADC_MG(x) (*(__IO hw_adc_mg_t *) HW_ADC_MG_ADDR(x))
-#define HW_ADC_MG_RD(x) (HW_ADC_MG(x).U)
-#define HW_ADC_MG_WR(x, v) (HW_ADC_MG(x).U = (v))
-#define HW_ADC_MG_SET(x, v) (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) | (v)))
-#define HW_ADC_MG_CLR(x, v) (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) & ~(v)))
-#define HW_ADC_MG_TOG(x, v) (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ADC_MG bitfields
- */
-
-/*!
- * @name Register ADC_MG, field MG[15:0] (RW)
- */
-//@{
-#define BP_ADC_MG_MG (0U) //!< Bit position for ADC_MG_MG.
-#define BM_ADC_MG_MG (0x0000FFFFU) //!< Bit mask for ADC_MG_MG.
-#define BS_ADC_MG_MG (16U) //!< Bit field size in bits for ADC_MG_MG.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_MG_MG field.
-#define BR_ADC_MG_MG(x) (HW_ADC_MG(x).B.MG)
-#endif
-
-//! @brief Format value for bitfield ADC_MG_MG.
-#define BF_ADC_MG_MG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_MG_MG), uint32_t) & BM_ADC_MG_MG)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MG field to a new value.
-#define BW_ADC_MG_MG(x, v) (HW_ADC_MG_WR(x, (HW_ADC_MG_RD(x) & ~BM_ADC_MG_MG) | BF_ADC_MG_MG(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register (RW)
- *
- * Reset value: 0x0000000AU
- *
- * The Plus-Side General Calibration Value Registers (CLPx) contain calibration
- * information that is generated by the calibration function. These registers
- * contain seven calibration values of varying widths: CLP0[5:0], CLP1[6:0],
- * CLP2[7:0], CLP3[8:0], CLP4[9:0], CLPS[5:0], and CLPD[5:0]. CLPx are automatically set
- * when the self-calibration sequence is done, that is, CAL is cleared. If these
- * registers are written by the user after calibration, the linearity error
- * specifications may not be met.
- */
-typedef union _hw_adc_clpd
-{
- uint32_t U;
- struct _hw_adc_clpd_bitfields
- {
- uint32_t CLPD : 6; //!< [5:0]
- uint32_t RESERVED0 : 26; //!< [31:6]
- } B;
-} hw_adc_clpd_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ADC_CLPD register
- */
-//@{
-#define HW_ADC_CLPD_ADDR(x) (REGS_ADC_BASE(x) + 0x34U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ADC_CLPD(x) (*(__IO hw_adc_clpd_t *) HW_ADC_CLPD_ADDR(x))
-#define HW_ADC_CLPD_RD(x) (HW_ADC_CLPD(x).U)
-#define HW_ADC_CLPD_WR(x, v) (HW_ADC_CLPD(x).U = (v))
-#define HW_ADC_CLPD_SET(x, v) (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) | (v)))
-#define HW_ADC_CLPD_CLR(x, v) (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) & ~(v)))
-#define HW_ADC_CLPD_TOG(x, v) (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ADC_CLPD bitfields
- */
-
-/*!
- * @name Register ADC_CLPD, field CLPD[5:0] (RW)
- *
- * Calibration Value
- */
-//@{
-#define BP_ADC_CLPD_CLPD (0U) //!< Bit position for ADC_CLPD_CLPD.
-#define BM_ADC_CLPD_CLPD (0x0000003FU) //!< Bit mask for ADC_CLPD_CLPD.
-#define BS_ADC_CLPD_CLPD (6U) //!< Bit field size in bits for ADC_CLPD_CLPD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_CLPD_CLPD field.
-#define BR_ADC_CLPD_CLPD(x) (HW_ADC_CLPD(x).B.CLPD)
-#endif
-
-//! @brief Format value for bitfield ADC_CLPD_CLPD.
-#define BF_ADC_CLPD_CLPD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLPD_CLPD), uint32_t) & BM_ADC_CLPD_CLPD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CLPD field to a new value.
-#define BW_ADC_CLPD_CLPD(x, v) (HW_ADC_CLPD_WR(x, (HW_ADC_CLPD_RD(x) & ~BM_ADC_CLPD_CLPD) | BF_ADC_CLPD_CLPD(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register (RW)
- *
- * Reset value: 0x00000020U
- *
- * For more information, see CLPD register description.
- */
-typedef union _hw_adc_clps
-{
- uint32_t U;
- struct _hw_adc_clps_bitfields
- {
- uint32_t CLPS : 6; //!< [5:0]
- uint32_t RESERVED0 : 26; //!< [31:6]
- } B;
-} hw_adc_clps_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ADC_CLPS register
- */
-//@{
-#define HW_ADC_CLPS_ADDR(x) (REGS_ADC_BASE(x) + 0x38U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ADC_CLPS(x) (*(__IO hw_adc_clps_t *) HW_ADC_CLPS_ADDR(x))
-#define HW_ADC_CLPS_RD(x) (HW_ADC_CLPS(x).U)
-#define HW_ADC_CLPS_WR(x, v) (HW_ADC_CLPS(x).U = (v))
-#define HW_ADC_CLPS_SET(x, v) (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) | (v)))
-#define HW_ADC_CLPS_CLR(x, v) (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) & ~(v)))
-#define HW_ADC_CLPS_TOG(x, v) (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ADC_CLPS bitfields
- */
-
-/*!
- * @name Register ADC_CLPS, field CLPS[5:0] (RW)
- *
- * Calibration Value
- */
-//@{
-#define BP_ADC_CLPS_CLPS (0U) //!< Bit position for ADC_CLPS_CLPS.
-#define BM_ADC_CLPS_CLPS (0x0000003FU) //!< Bit mask for ADC_CLPS_CLPS.
-#define BS_ADC_CLPS_CLPS (6U) //!< Bit field size in bits for ADC_CLPS_CLPS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_CLPS_CLPS field.
-#define BR_ADC_CLPS_CLPS(x) (HW_ADC_CLPS(x).B.CLPS)
-#endif
-
-//! @brief Format value for bitfield ADC_CLPS_CLPS.
-#define BF_ADC_CLPS_CLPS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLPS_CLPS), uint32_t) & BM_ADC_CLPS_CLPS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CLPS field to a new value.
-#define BW_ADC_CLPS_CLPS(x, v) (HW_ADC_CLPS_WR(x, (HW_ADC_CLPS_RD(x) & ~BM_ADC_CLPS_CLPS) | BF_ADC_CLPS_CLPS(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register (RW)
- *
- * Reset value: 0x00000200U
- *
- * For more information, see CLPD register description.
- */
-typedef union _hw_adc_clp4
-{
- uint32_t U;
- struct _hw_adc_clp4_bitfields
- {
- uint32_t CLP4 : 10; //!< [9:0]
- uint32_t RESERVED0 : 22; //!< [31:10]
- } B;
-} hw_adc_clp4_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ADC_CLP4 register
- */
-//@{
-#define HW_ADC_CLP4_ADDR(x) (REGS_ADC_BASE(x) + 0x3CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ADC_CLP4(x) (*(__IO hw_adc_clp4_t *) HW_ADC_CLP4_ADDR(x))
-#define HW_ADC_CLP4_RD(x) (HW_ADC_CLP4(x).U)
-#define HW_ADC_CLP4_WR(x, v) (HW_ADC_CLP4(x).U = (v))
-#define HW_ADC_CLP4_SET(x, v) (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) | (v)))
-#define HW_ADC_CLP4_CLR(x, v) (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) & ~(v)))
-#define HW_ADC_CLP4_TOG(x, v) (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ADC_CLP4 bitfields
- */
-
-/*!
- * @name Register ADC_CLP4, field CLP4[9:0] (RW)
- *
- * Calibration Value
- */
-//@{
-#define BP_ADC_CLP4_CLP4 (0U) //!< Bit position for ADC_CLP4_CLP4.
-#define BM_ADC_CLP4_CLP4 (0x000003FFU) //!< Bit mask for ADC_CLP4_CLP4.
-#define BS_ADC_CLP4_CLP4 (10U) //!< Bit field size in bits for ADC_CLP4_CLP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_CLP4_CLP4 field.
-#define BR_ADC_CLP4_CLP4(x) (HW_ADC_CLP4(x).B.CLP4)
-#endif
-
-//! @brief Format value for bitfield ADC_CLP4_CLP4.
-#define BF_ADC_CLP4_CLP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLP4_CLP4), uint32_t) & BM_ADC_CLP4_CLP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CLP4 field to a new value.
-#define BW_ADC_CLP4_CLP4(x, v) (HW_ADC_CLP4_WR(x, (HW_ADC_CLP4_RD(x) & ~BM_ADC_CLP4_CLP4) | BF_ADC_CLP4_CLP4(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register (RW)
- *
- * Reset value: 0x00000100U
- *
- * For more information, see CLPD register description.
- */
-typedef union _hw_adc_clp3
-{
- uint32_t U;
- struct _hw_adc_clp3_bitfields
- {
- uint32_t CLP3 : 9; //!< [8:0]
- uint32_t RESERVED0 : 23; //!< [31:9]
- } B;
-} hw_adc_clp3_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ADC_CLP3 register
- */
-//@{
-#define HW_ADC_CLP3_ADDR(x) (REGS_ADC_BASE(x) + 0x40U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ADC_CLP3(x) (*(__IO hw_adc_clp3_t *) HW_ADC_CLP3_ADDR(x))
-#define HW_ADC_CLP3_RD(x) (HW_ADC_CLP3(x).U)
-#define HW_ADC_CLP3_WR(x, v) (HW_ADC_CLP3(x).U = (v))
-#define HW_ADC_CLP3_SET(x, v) (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) | (v)))
-#define HW_ADC_CLP3_CLR(x, v) (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) & ~(v)))
-#define HW_ADC_CLP3_TOG(x, v) (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ADC_CLP3 bitfields
- */
-
-/*!
- * @name Register ADC_CLP3, field CLP3[8:0] (RW)
- *
- * Calibration Value
- */
-//@{
-#define BP_ADC_CLP3_CLP3 (0U) //!< Bit position for ADC_CLP3_CLP3.
-#define BM_ADC_CLP3_CLP3 (0x000001FFU) //!< Bit mask for ADC_CLP3_CLP3.
-#define BS_ADC_CLP3_CLP3 (9U) //!< Bit field size in bits for ADC_CLP3_CLP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_CLP3_CLP3 field.
-#define BR_ADC_CLP3_CLP3(x) (HW_ADC_CLP3(x).B.CLP3)
-#endif
-
-//! @brief Format value for bitfield ADC_CLP3_CLP3.
-#define BF_ADC_CLP3_CLP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLP3_CLP3), uint32_t) & BM_ADC_CLP3_CLP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CLP3 field to a new value.
-#define BW_ADC_CLP3_CLP3(x, v) (HW_ADC_CLP3_WR(x, (HW_ADC_CLP3_RD(x) & ~BM_ADC_CLP3_CLP3) | BF_ADC_CLP3_CLP3(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register (RW)
- *
- * Reset value: 0x00000080U
- *
- * For more information, see CLPD register description.
- */
-typedef union _hw_adc_clp2
-{
- uint32_t U;
- struct _hw_adc_clp2_bitfields
- {
- uint32_t CLP2 : 8; //!< [7:0]
- uint32_t RESERVED0 : 24; //!< [31:8]
- } B;
-} hw_adc_clp2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ADC_CLP2 register
- */
-//@{
-#define HW_ADC_CLP2_ADDR(x) (REGS_ADC_BASE(x) + 0x44U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ADC_CLP2(x) (*(__IO hw_adc_clp2_t *) HW_ADC_CLP2_ADDR(x))
-#define HW_ADC_CLP2_RD(x) (HW_ADC_CLP2(x).U)
-#define HW_ADC_CLP2_WR(x, v) (HW_ADC_CLP2(x).U = (v))
-#define HW_ADC_CLP2_SET(x, v) (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) | (v)))
-#define HW_ADC_CLP2_CLR(x, v) (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) & ~(v)))
-#define HW_ADC_CLP2_TOG(x, v) (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ADC_CLP2 bitfields
- */
-
-/*!
- * @name Register ADC_CLP2, field CLP2[7:0] (RW)
- *
- * Calibration Value
- */
-//@{
-#define BP_ADC_CLP2_CLP2 (0U) //!< Bit position for ADC_CLP2_CLP2.
-#define BM_ADC_CLP2_CLP2 (0x000000FFU) //!< Bit mask for ADC_CLP2_CLP2.
-#define BS_ADC_CLP2_CLP2 (8U) //!< Bit field size in bits for ADC_CLP2_CLP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_CLP2_CLP2 field.
-#define BR_ADC_CLP2_CLP2(x) (HW_ADC_CLP2(x).B.CLP2)
-#endif
-
-//! @brief Format value for bitfield ADC_CLP2_CLP2.
-#define BF_ADC_CLP2_CLP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLP2_CLP2), uint32_t) & BM_ADC_CLP2_CLP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CLP2 field to a new value.
-#define BW_ADC_CLP2_CLP2(x, v) (HW_ADC_CLP2_WR(x, (HW_ADC_CLP2_RD(x) & ~BM_ADC_CLP2_CLP2) | BF_ADC_CLP2_CLP2(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register (RW)
- *
- * Reset value: 0x00000040U
- *
- * For more information, see CLPD register description.
- */
-typedef union _hw_adc_clp1
-{
- uint32_t U;
- struct _hw_adc_clp1_bitfields
- {
- uint32_t CLP1 : 7; //!< [6:0]
- uint32_t RESERVED0 : 25; //!< [31:7]
- } B;
-} hw_adc_clp1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ADC_CLP1 register
- */
-//@{
-#define HW_ADC_CLP1_ADDR(x) (REGS_ADC_BASE(x) + 0x48U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ADC_CLP1(x) (*(__IO hw_adc_clp1_t *) HW_ADC_CLP1_ADDR(x))
-#define HW_ADC_CLP1_RD(x) (HW_ADC_CLP1(x).U)
-#define HW_ADC_CLP1_WR(x, v) (HW_ADC_CLP1(x).U = (v))
-#define HW_ADC_CLP1_SET(x, v) (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) | (v)))
-#define HW_ADC_CLP1_CLR(x, v) (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) & ~(v)))
-#define HW_ADC_CLP1_TOG(x, v) (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ADC_CLP1 bitfields
- */
-
-/*!
- * @name Register ADC_CLP1, field CLP1[6:0] (RW)
- *
- * Calibration Value
- */
-//@{
-#define BP_ADC_CLP1_CLP1 (0U) //!< Bit position for ADC_CLP1_CLP1.
-#define BM_ADC_CLP1_CLP1 (0x0000007FU) //!< Bit mask for ADC_CLP1_CLP1.
-#define BS_ADC_CLP1_CLP1 (7U) //!< Bit field size in bits for ADC_CLP1_CLP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_CLP1_CLP1 field.
-#define BR_ADC_CLP1_CLP1(x) (HW_ADC_CLP1(x).B.CLP1)
-#endif
-
-//! @brief Format value for bitfield ADC_CLP1_CLP1.
-#define BF_ADC_CLP1_CLP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLP1_CLP1), uint32_t) & BM_ADC_CLP1_CLP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CLP1 field to a new value.
-#define BW_ADC_CLP1_CLP1(x, v) (HW_ADC_CLP1_WR(x, (HW_ADC_CLP1_RD(x) & ~BM_ADC_CLP1_CLP1) | BF_ADC_CLP1_CLP1(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register (RW)
- *
- * Reset value: 0x00000020U
- *
- * For more information, see CLPD register description.
- */
-typedef union _hw_adc_clp0
-{
- uint32_t U;
- struct _hw_adc_clp0_bitfields
- {
- uint32_t CLP0 : 6; //!< [5:0]
- uint32_t RESERVED0 : 26; //!< [31:6]
- } B;
-} hw_adc_clp0_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ADC_CLP0 register
- */
-//@{
-#define HW_ADC_CLP0_ADDR(x) (REGS_ADC_BASE(x) + 0x4CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ADC_CLP0(x) (*(__IO hw_adc_clp0_t *) HW_ADC_CLP0_ADDR(x))
-#define HW_ADC_CLP0_RD(x) (HW_ADC_CLP0(x).U)
-#define HW_ADC_CLP0_WR(x, v) (HW_ADC_CLP0(x).U = (v))
-#define HW_ADC_CLP0_SET(x, v) (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) | (v)))
-#define HW_ADC_CLP0_CLR(x, v) (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) & ~(v)))
-#define HW_ADC_CLP0_TOG(x, v) (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ADC_CLP0 bitfields
- */
-
-/*!
- * @name Register ADC_CLP0, field CLP0[5:0] (RW)
- *
- * Calibration Value
- */
-//@{
-#define BP_ADC_CLP0_CLP0 (0U) //!< Bit position for ADC_CLP0_CLP0.
-#define BM_ADC_CLP0_CLP0 (0x0000003FU) //!< Bit mask for ADC_CLP0_CLP0.
-#define BS_ADC_CLP0_CLP0 (6U) //!< Bit field size in bits for ADC_CLP0_CLP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_CLP0_CLP0 field.
-#define BR_ADC_CLP0_CLP0(x) (HW_ADC_CLP0(x).B.CLP0)
-#endif
-
-//! @brief Format value for bitfield ADC_CLP0_CLP0.
-#define BF_ADC_CLP0_CLP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLP0_CLP0), uint32_t) & BM_ADC_CLP0_CLP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CLP0 field to a new value.
-#define BW_ADC_CLP0_CLP0(x, v) (HW_ADC_CLP0_WR(x, (HW_ADC_CLP0_RD(x) & ~BM_ADC_CLP0_CLP0) | BF_ADC_CLP0_CLP0(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register (RW)
- *
- * Reset value: 0x0000000AU
- *
- * The Minus-Side General Calibration Value (CLMx) registers contain calibration
- * information that is generated by the calibration function. These registers
- * contain seven calibration values of varying widths: CLM0[5:0], CLM1[6:0],
- * CLM2[7:0], CLM3[8:0], CLM4[9:0], CLMS[5:0], and CLMD[5:0]. CLMx are automatically
- * set when the self-calibration sequence is done, that is, CAL is cleared. If
- * these registers are written by the user after calibration, the linearity error
- * specifications may not be met.
- */
-typedef union _hw_adc_clmd
-{
- uint32_t U;
- struct _hw_adc_clmd_bitfields
- {
- uint32_t CLMD : 6; //!< [5:0]
- uint32_t RESERVED0 : 26; //!< [31:6]
- } B;
-} hw_adc_clmd_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ADC_CLMD register
- */
-//@{
-#define HW_ADC_CLMD_ADDR(x) (REGS_ADC_BASE(x) + 0x54U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ADC_CLMD(x) (*(__IO hw_adc_clmd_t *) HW_ADC_CLMD_ADDR(x))
-#define HW_ADC_CLMD_RD(x) (HW_ADC_CLMD(x).U)
-#define HW_ADC_CLMD_WR(x, v) (HW_ADC_CLMD(x).U = (v))
-#define HW_ADC_CLMD_SET(x, v) (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) | (v)))
-#define HW_ADC_CLMD_CLR(x, v) (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) & ~(v)))
-#define HW_ADC_CLMD_TOG(x, v) (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ADC_CLMD bitfields
- */
-
-/*!
- * @name Register ADC_CLMD, field CLMD[5:0] (RW)
- *
- * Calibration Value
- */
-//@{
-#define BP_ADC_CLMD_CLMD (0U) //!< Bit position for ADC_CLMD_CLMD.
-#define BM_ADC_CLMD_CLMD (0x0000003FU) //!< Bit mask for ADC_CLMD_CLMD.
-#define BS_ADC_CLMD_CLMD (6U) //!< Bit field size in bits for ADC_CLMD_CLMD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_CLMD_CLMD field.
-#define BR_ADC_CLMD_CLMD(x) (HW_ADC_CLMD(x).B.CLMD)
-#endif
-
-//! @brief Format value for bitfield ADC_CLMD_CLMD.
-#define BF_ADC_CLMD_CLMD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLMD_CLMD), uint32_t) & BM_ADC_CLMD_CLMD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CLMD field to a new value.
-#define BW_ADC_CLMD_CLMD(x, v) (HW_ADC_CLMD_WR(x, (HW_ADC_CLMD_RD(x) & ~BM_ADC_CLMD_CLMD) | BF_ADC_CLMD_CLMD(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register (RW)
- *
- * Reset value: 0x00000020U
- *
- * For more information, see CLMD register description.
- */
-typedef union _hw_adc_clms
-{
- uint32_t U;
- struct _hw_adc_clms_bitfields
- {
- uint32_t CLMS : 6; //!< [5:0]
- uint32_t RESERVED0 : 26; //!< [31:6]
- } B;
-} hw_adc_clms_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ADC_CLMS register
- */
-//@{
-#define HW_ADC_CLMS_ADDR(x) (REGS_ADC_BASE(x) + 0x58U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ADC_CLMS(x) (*(__IO hw_adc_clms_t *) HW_ADC_CLMS_ADDR(x))
-#define HW_ADC_CLMS_RD(x) (HW_ADC_CLMS(x).U)
-#define HW_ADC_CLMS_WR(x, v) (HW_ADC_CLMS(x).U = (v))
-#define HW_ADC_CLMS_SET(x, v) (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) | (v)))
-#define HW_ADC_CLMS_CLR(x, v) (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) & ~(v)))
-#define HW_ADC_CLMS_TOG(x, v) (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ADC_CLMS bitfields
- */
-
-/*!
- * @name Register ADC_CLMS, field CLMS[5:0] (RW)
- *
- * Calibration Value
- */
-//@{
-#define BP_ADC_CLMS_CLMS (0U) //!< Bit position for ADC_CLMS_CLMS.
-#define BM_ADC_CLMS_CLMS (0x0000003FU) //!< Bit mask for ADC_CLMS_CLMS.
-#define BS_ADC_CLMS_CLMS (6U) //!< Bit field size in bits for ADC_CLMS_CLMS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_CLMS_CLMS field.
-#define BR_ADC_CLMS_CLMS(x) (HW_ADC_CLMS(x).B.CLMS)
-#endif
-
-//! @brief Format value for bitfield ADC_CLMS_CLMS.
-#define BF_ADC_CLMS_CLMS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLMS_CLMS), uint32_t) & BM_ADC_CLMS_CLMS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CLMS field to a new value.
-#define BW_ADC_CLMS_CLMS(x, v) (HW_ADC_CLMS_WR(x, (HW_ADC_CLMS_RD(x) & ~BM_ADC_CLMS_CLMS) | BF_ADC_CLMS_CLMS(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register (RW)
- *
- * Reset value: 0x00000200U
- *
- * For more information, see CLMD register description.
- */
-typedef union _hw_adc_clm4
-{
- uint32_t U;
- struct _hw_adc_clm4_bitfields
- {
- uint32_t CLM4 : 10; //!< [9:0]
- uint32_t RESERVED0 : 22; //!< [31:10]
- } B;
-} hw_adc_clm4_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ADC_CLM4 register
- */
-//@{
-#define HW_ADC_CLM4_ADDR(x) (REGS_ADC_BASE(x) + 0x5CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ADC_CLM4(x) (*(__IO hw_adc_clm4_t *) HW_ADC_CLM4_ADDR(x))
-#define HW_ADC_CLM4_RD(x) (HW_ADC_CLM4(x).U)
-#define HW_ADC_CLM4_WR(x, v) (HW_ADC_CLM4(x).U = (v))
-#define HW_ADC_CLM4_SET(x, v) (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) | (v)))
-#define HW_ADC_CLM4_CLR(x, v) (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) & ~(v)))
-#define HW_ADC_CLM4_TOG(x, v) (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ADC_CLM4 bitfields
- */
-
-/*!
- * @name Register ADC_CLM4, field CLM4[9:0] (RW)
- *
- * Calibration Value
- */
-//@{
-#define BP_ADC_CLM4_CLM4 (0U) //!< Bit position for ADC_CLM4_CLM4.
-#define BM_ADC_CLM4_CLM4 (0x000003FFU) //!< Bit mask for ADC_CLM4_CLM4.
-#define BS_ADC_CLM4_CLM4 (10U) //!< Bit field size in bits for ADC_CLM4_CLM4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_CLM4_CLM4 field.
-#define BR_ADC_CLM4_CLM4(x) (HW_ADC_CLM4(x).B.CLM4)
-#endif
-
-//! @brief Format value for bitfield ADC_CLM4_CLM4.
-#define BF_ADC_CLM4_CLM4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLM4_CLM4), uint32_t) & BM_ADC_CLM4_CLM4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CLM4 field to a new value.
-#define BW_ADC_CLM4_CLM4(x, v) (HW_ADC_CLM4_WR(x, (HW_ADC_CLM4_RD(x) & ~BM_ADC_CLM4_CLM4) | BF_ADC_CLM4_CLM4(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register (RW)
- *
- * Reset value: 0x00000100U
- *
- * For more information, see CLMD register description.
- */
-typedef union _hw_adc_clm3
-{
- uint32_t U;
- struct _hw_adc_clm3_bitfields
- {
- uint32_t CLM3 : 9; //!< [8:0]
- uint32_t RESERVED0 : 23; //!< [31:9]
- } B;
-} hw_adc_clm3_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ADC_CLM3 register
- */
-//@{
-#define HW_ADC_CLM3_ADDR(x) (REGS_ADC_BASE(x) + 0x60U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ADC_CLM3(x) (*(__IO hw_adc_clm3_t *) HW_ADC_CLM3_ADDR(x))
-#define HW_ADC_CLM3_RD(x) (HW_ADC_CLM3(x).U)
-#define HW_ADC_CLM3_WR(x, v) (HW_ADC_CLM3(x).U = (v))
-#define HW_ADC_CLM3_SET(x, v) (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) | (v)))
-#define HW_ADC_CLM3_CLR(x, v) (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) & ~(v)))
-#define HW_ADC_CLM3_TOG(x, v) (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ADC_CLM3 bitfields
- */
-
-/*!
- * @name Register ADC_CLM3, field CLM3[8:0] (RW)
- *
- * Calibration Value
- */
-//@{
-#define BP_ADC_CLM3_CLM3 (0U) //!< Bit position for ADC_CLM3_CLM3.
-#define BM_ADC_CLM3_CLM3 (0x000001FFU) //!< Bit mask for ADC_CLM3_CLM3.
-#define BS_ADC_CLM3_CLM3 (9U) //!< Bit field size in bits for ADC_CLM3_CLM3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_CLM3_CLM3 field.
-#define BR_ADC_CLM3_CLM3(x) (HW_ADC_CLM3(x).B.CLM3)
-#endif
-
-//! @brief Format value for bitfield ADC_CLM3_CLM3.
-#define BF_ADC_CLM3_CLM3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLM3_CLM3), uint32_t) & BM_ADC_CLM3_CLM3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CLM3 field to a new value.
-#define BW_ADC_CLM3_CLM3(x, v) (HW_ADC_CLM3_WR(x, (HW_ADC_CLM3_RD(x) & ~BM_ADC_CLM3_CLM3) | BF_ADC_CLM3_CLM3(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register (RW)
- *
- * Reset value: 0x00000080U
- *
- * For more information, see CLMD register description.
- */
-typedef union _hw_adc_clm2
-{
- uint32_t U;
- struct _hw_adc_clm2_bitfields
- {
- uint32_t CLM2 : 8; //!< [7:0]
- uint32_t RESERVED0 : 24; //!< [31:8]
- } B;
-} hw_adc_clm2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ADC_CLM2 register
- */
-//@{
-#define HW_ADC_CLM2_ADDR(x) (REGS_ADC_BASE(x) + 0x64U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ADC_CLM2(x) (*(__IO hw_adc_clm2_t *) HW_ADC_CLM2_ADDR(x))
-#define HW_ADC_CLM2_RD(x) (HW_ADC_CLM2(x).U)
-#define HW_ADC_CLM2_WR(x, v) (HW_ADC_CLM2(x).U = (v))
-#define HW_ADC_CLM2_SET(x, v) (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) | (v)))
-#define HW_ADC_CLM2_CLR(x, v) (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) & ~(v)))
-#define HW_ADC_CLM2_TOG(x, v) (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ADC_CLM2 bitfields
- */
-
-/*!
- * @name Register ADC_CLM2, field CLM2[7:0] (RW)
- *
- * Calibration Value
- */
-//@{
-#define BP_ADC_CLM2_CLM2 (0U) //!< Bit position for ADC_CLM2_CLM2.
-#define BM_ADC_CLM2_CLM2 (0x000000FFU) //!< Bit mask for ADC_CLM2_CLM2.
-#define BS_ADC_CLM2_CLM2 (8U) //!< Bit field size in bits for ADC_CLM2_CLM2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_CLM2_CLM2 field.
-#define BR_ADC_CLM2_CLM2(x) (HW_ADC_CLM2(x).B.CLM2)
-#endif
-
-//! @brief Format value for bitfield ADC_CLM2_CLM2.
-#define BF_ADC_CLM2_CLM2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLM2_CLM2), uint32_t) & BM_ADC_CLM2_CLM2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CLM2 field to a new value.
-#define BW_ADC_CLM2_CLM2(x, v) (HW_ADC_CLM2_WR(x, (HW_ADC_CLM2_RD(x) & ~BM_ADC_CLM2_CLM2) | BF_ADC_CLM2_CLM2(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register (RW)
- *
- * Reset value: 0x00000040U
- *
- * For more information, see CLMD register description.
- */
-typedef union _hw_adc_clm1
-{
- uint32_t U;
- struct _hw_adc_clm1_bitfields
- {
- uint32_t CLM1 : 7; //!< [6:0]
- uint32_t RESERVED0 : 25; //!< [31:7]
- } B;
-} hw_adc_clm1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ADC_CLM1 register
- */
-//@{
-#define HW_ADC_CLM1_ADDR(x) (REGS_ADC_BASE(x) + 0x68U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ADC_CLM1(x) (*(__IO hw_adc_clm1_t *) HW_ADC_CLM1_ADDR(x))
-#define HW_ADC_CLM1_RD(x) (HW_ADC_CLM1(x).U)
-#define HW_ADC_CLM1_WR(x, v) (HW_ADC_CLM1(x).U = (v))
-#define HW_ADC_CLM1_SET(x, v) (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) | (v)))
-#define HW_ADC_CLM1_CLR(x, v) (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) & ~(v)))
-#define HW_ADC_CLM1_TOG(x, v) (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ADC_CLM1 bitfields
- */
-
-/*!
- * @name Register ADC_CLM1, field CLM1[6:0] (RW)
- *
- * Calibration Value
- */
-//@{
-#define BP_ADC_CLM1_CLM1 (0U) //!< Bit position for ADC_CLM1_CLM1.
-#define BM_ADC_CLM1_CLM1 (0x0000007FU) //!< Bit mask for ADC_CLM1_CLM1.
-#define BS_ADC_CLM1_CLM1 (7U) //!< Bit field size in bits for ADC_CLM1_CLM1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_CLM1_CLM1 field.
-#define BR_ADC_CLM1_CLM1(x) (HW_ADC_CLM1(x).B.CLM1)
-#endif
-
-//! @brief Format value for bitfield ADC_CLM1_CLM1.
-#define BF_ADC_CLM1_CLM1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLM1_CLM1), uint32_t) & BM_ADC_CLM1_CLM1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CLM1 field to a new value.
-#define BW_ADC_CLM1_CLM1(x, v) (HW_ADC_CLM1_WR(x, (HW_ADC_CLM1_RD(x) & ~BM_ADC_CLM1_CLM1) | BF_ADC_CLM1_CLM1(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register (RW)
- *
- * Reset value: 0x00000020U
- *
- * For more information, see CLMD register description.
- */
-typedef union _hw_adc_clm0
-{
- uint32_t U;
- struct _hw_adc_clm0_bitfields
- {
- uint32_t CLM0 : 6; //!< [5:0]
- uint32_t RESERVED0 : 26; //!< [31:6]
- } B;
-} hw_adc_clm0_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ADC_CLM0 register
- */
-//@{
-#define HW_ADC_CLM0_ADDR(x) (REGS_ADC_BASE(x) + 0x6CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ADC_CLM0(x) (*(__IO hw_adc_clm0_t *) HW_ADC_CLM0_ADDR(x))
-#define HW_ADC_CLM0_RD(x) (HW_ADC_CLM0(x).U)
-#define HW_ADC_CLM0_WR(x, v) (HW_ADC_CLM0(x).U = (v))
-#define HW_ADC_CLM0_SET(x, v) (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) | (v)))
-#define HW_ADC_CLM0_CLR(x, v) (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) & ~(v)))
-#define HW_ADC_CLM0_TOG(x, v) (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ADC_CLM0 bitfields
- */
-
-/*!
- * @name Register ADC_CLM0, field CLM0[5:0] (RW)
- *
- * Calibration Value
- */
-//@{
-#define BP_ADC_CLM0_CLM0 (0U) //!< Bit position for ADC_CLM0_CLM0.
-#define BM_ADC_CLM0_CLM0 (0x0000003FU) //!< Bit mask for ADC_CLM0_CLM0.
-#define BS_ADC_CLM0_CLM0 (6U) //!< Bit field size in bits for ADC_CLM0_CLM0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ADC_CLM0_CLM0 field.
-#define BR_ADC_CLM0_CLM0(x) (HW_ADC_CLM0(x).B.CLM0)
-#endif
-
-//! @brief Format value for bitfield ADC_CLM0_CLM0.
-#define BF_ADC_CLM0_CLM0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLM0_CLM0), uint32_t) & BM_ADC_CLM0_CLM0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CLM0 field to a new value.
-#define BW_ADC_CLM0_CLM0(x, v) (HW_ADC_CLM0_WR(x, (HW_ADC_CLM0_RD(x) & ~BM_ADC_CLM0_CLM0) | BF_ADC_CLM0_CLM0(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_adc_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All ADC module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_adc
-{
- __IO hw_adc_sc1n_t SC1n[2]; //!< [0x0] ADC Status and Control Registers 1
- __IO hw_adc_cfg1_t CFG1; //!< [0x8] ADC Configuration Register 1
- __IO hw_adc_cfg2_t CFG2; //!< [0xC] ADC Configuration Register 2
- __I hw_adc_rn_t Rn[2]; //!< [0x10] ADC Data Result Register
- __IO hw_adc_cv1_t CV1; //!< [0x18] Compare Value Registers
- __IO hw_adc_cv2_t CV2; //!< [0x1C] Compare Value Registers
- __IO hw_adc_sc2_t SC2; //!< [0x20] Status and Control Register 2
- __IO hw_adc_sc3_t SC3; //!< [0x24] Status and Control Register 3
- __IO hw_adc_ofs_t OFS; //!< [0x28] ADC Offset Correction Register
- __IO hw_adc_pg_t PG; //!< [0x2C] ADC Plus-Side Gain Register
- __IO hw_adc_mg_t MG; //!< [0x30] ADC Minus-Side Gain Register
- __IO hw_adc_clpd_t CLPD; //!< [0x34] ADC Plus-Side General Calibration Value Register
- __IO hw_adc_clps_t CLPS; //!< [0x38] ADC Plus-Side General Calibration Value Register
- __IO hw_adc_clp4_t CLP4; //!< [0x3C] ADC Plus-Side General Calibration Value Register
- __IO hw_adc_clp3_t CLP3; //!< [0x40] ADC Plus-Side General Calibration Value Register
- __IO hw_adc_clp2_t CLP2; //!< [0x44] ADC Plus-Side General Calibration Value Register
- __IO hw_adc_clp1_t CLP1; //!< [0x48] ADC Plus-Side General Calibration Value Register
- __IO hw_adc_clp0_t CLP0; //!< [0x4C] ADC Plus-Side General Calibration Value Register
- uint8_t _reserved0[4];
- __IO hw_adc_clmd_t CLMD; //!< [0x54] ADC Minus-Side General Calibration Value Register
- __IO hw_adc_clms_t CLMS; //!< [0x58] ADC Minus-Side General Calibration Value Register
- __IO hw_adc_clm4_t CLM4; //!< [0x5C] ADC Minus-Side General Calibration Value Register
- __IO hw_adc_clm3_t CLM3; //!< [0x60] ADC Minus-Side General Calibration Value Register
- __IO hw_adc_clm2_t CLM2; //!< [0x64] ADC Minus-Side General Calibration Value Register
- __IO hw_adc_clm1_t CLM1; //!< [0x68] ADC Minus-Side General Calibration Value Register
- __IO hw_adc_clm0_t CLM0; //!< [0x6C] ADC Minus-Side General Calibration Value Register
-} hw_adc_t;
-#pragma pack()
-
-//! @brief Macro to access all ADC registers.
-//! @param x ADC instance number.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_ADC(0)</code>.
-#define HW_ADC(x) (*(hw_adc_t *) REGS_ADC_BASE(x))
-#endif
-
-#endif // __HW_ADC_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_aips.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,14135 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_AIPS_REGISTERS_H__
-#define __HW_AIPS_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 AIPS
- *
- * AIPS-Lite Bridge
- *
- * Registers defined in this header file:
- * - HW_AIPS_MPRA - Master Privilege Register A
- * - HW_AIPS_PACRA - Peripheral Access Control Register
- * - HW_AIPS_PACRB - Peripheral Access Control Register
- * - HW_AIPS_PACRC - Peripheral Access Control Register
- * - HW_AIPS_PACRD - Peripheral Access Control Register
- * - HW_AIPS_PACRE - Peripheral Access Control Register
- * - HW_AIPS_PACRF - Peripheral Access Control Register
- * - HW_AIPS_PACRG - Peripheral Access Control Register
- * - HW_AIPS_PACRH - Peripheral Access Control Register
- * - HW_AIPS_PACRI - Peripheral Access Control Register
- * - HW_AIPS_PACRJ - Peripheral Access Control Register
- * - HW_AIPS_PACRK - Peripheral Access Control Register
- * - HW_AIPS_PACRL - Peripheral Access Control Register
- * - HW_AIPS_PACRM - Peripheral Access Control Register
- * - HW_AIPS_PACRN - Peripheral Access Control Register
- * - HW_AIPS_PACRO - Peripheral Access Control Register
- * - HW_AIPS_PACRP - Peripheral Access Control Register
- * - HW_AIPS_PACRU - Peripheral Access Control Register
- *
- * - hw_aips_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_AIPS_BASE
-#define HW_AIPS_INSTANCE_COUNT (2U) //!< Number of instances of the AIPS module.
-#define HW_AIPS0 (0U) //!< Instance number for AIPS0.
-#define HW_AIPS1 (1U) //!< Instance number for AIPS1.
-#define REGS_AIPS0_BASE (0x40000000U) //!< Base address for AIPS0.
-#define REGS_AIPS1_BASE (0x40080000U) //!< Base address for AIPS1.
-
-//! @brief Table of base addresses for AIPS instances.
-static const uint32_t __g_regs_AIPS_base_addresses[] = {
- REGS_AIPS0_BASE,
- REGS_AIPS1_BASE,
- };
-
-//! @brief Get the base address of AIPS by instance number.
-//! @param x AIPS instance number, from 0 through 1.
-#define REGS_AIPS_BASE(x) (__g_regs_AIPS_base_addresses[(x)])
-
-//! @brief Get the instance number given a base address.
-//! @param b Base address for an instance of AIPS.
-#define REGS_AIPS_INSTANCE(b) ((b) == REGS_AIPS0_BASE ? HW_AIPS0 : (b) == REGS_AIPS1_BASE ? HW_AIPS1 : 0)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_AIPS_MPRA - Master Privilege Register A
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_AIPS_MPRA - Master Privilege Register A (RW)
- *
- * Reset value: 0x77700000U
- *
- * The MPRA specifies identical 4-bit fields defining the access-privilege level
- * associated with a bus master to various peripherals on the chip. The register
- * provides one field per bus master. At reset, the default value loaded into
- * the MPRA fields is chip-specific. See the chip configuration details for the
- * value of a particular device. A register field that maps to an unimplemented
- * master or peripheral behaves as read-only-zero. Each master is assigned a logical
- * ID from 0 to 15. See the master logical ID assignment table in the
- * chip-specific AIPS information.
- */
-typedef union _hw_aips_mpra
-{
- uint32_t U;
- struct _hw_aips_mpra_bitfields
- {
- uint32_t RESERVED0 : 8; //!< [7:0]
- uint32_t MPL5 : 1; //!< [8] Master 5 Privilege Level
- uint32_t MTW5 : 1; //!< [9] Master 5 Trusted For Writes
- uint32_t MTR5 : 1; //!< [10] Master 5 Trusted For Read
- uint32_t RESERVED1 : 1; //!< [11]
- uint32_t MPL4 : 1; //!< [12] Master 4 Privilege Level
- uint32_t MTW4 : 1; //!< [13] Master 4 Trusted For Writes
- uint32_t MTR4 : 1; //!< [14] Master 4 Trusted For Read
- uint32_t RESERVED2 : 1; //!< [15]
- uint32_t MPL3 : 1; //!< [16] Master 3 Privilege Level
- uint32_t MTW3 : 1; //!< [17] Master 3 Trusted For Writes
- uint32_t MTR3 : 1; //!< [18] Master 3 Trusted For Read
- uint32_t RESERVED3 : 1; //!< [19]
- uint32_t MPL2 : 1; //!< [20] Master 2 Privilege Level
- uint32_t MTW2 : 1; //!< [21] Master 2 Trusted For Writes
- uint32_t MTR2 : 1; //!< [22] Master 2 Trusted For Read
- uint32_t RESERVED4 : 1; //!< [23]
- uint32_t MPL1 : 1; //!< [24] Master 1 Privilege Level
- uint32_t MTW1 : 1; //!< [25] Master 1 Trusted for Writes
- uint32_t MTR1 : 1; //!< [26] Master 1 Trusted for Read
- uint32_t RESERVED5 : 1; //!< [27]
- uint32_t MPL0 : 1; //!< [28] Master 0 Privilege Level
- uint32_t MTW0 : 1; //!< [29] Master 0 Trusted For Writes
- uint32_t MTR0 : 1; //!< [30] Master 0 Trusted For Read
- uint32_t RESERVED6 : 1; //!< [31]
- } B;
-} hw_aips_mpra_t;
-#endif
-
-/*!
- * @name Constants and macros for entire AIPS_MPRA register
- */
-//@{
-#define HW_AIPS_MPRA_ADDR(x) (REGS_AIPS_BASE(x) + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_AIPS_MPRA(x) (*(__IO hw_aips_mpra_t *) HW_AIPS_MPRA_ADDR(x))
-#define HW_AIPS_MPRA_RD(x) (HW_AIPS_MPRA(x).U)
-#define HW_AIPS_MPRA_WR(x, v) (HW_AIPS_MPRA(x).U = (v))
-#define HW_AIPS_MPRA_SET(x, v) (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) | (v)))
-#define HW_AIPS_MPRA_CLR(x, v) (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) & ~(v)))
-#define HW_AIPS_MPRA_TOG(x, v) (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual AIPS_MPRA bitfields
- */
-
-/*!
- * @name Register AIPS_MPRA, field MPL5[8] (RW)
- *
- * Specifies how the privilege level of the master is determined.
- *
- * Values:
- * - 0 - Accesses from this master are forced to user-mode.
- * - 1 - Accesses from this master are not forced to user-mode.
- */
-//@{
-#define BP_AIPS_MPRA_MPL5 (8U) //!< Bit position for AIPS_MPRA_MPL5.
-#define BM_AIPS_MPRA_MPL5 (0x00000100U) //!< Bit mask for AIPS_MPRA_MPL5.
-#define BS_AIPS_MPRA_MPL5 (1U) //!< Bit field size in bits for AIPS_MPRA_MPL5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_MPRA_MPL5 field.
-#define BR_AIPS_MPRA_MPL5(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL5))
-#endif
-
-//! @brief Format value for bitfield AIPS_MPRA_MPL5.
-#define BF_AIPS_MPRA_MPL5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MPL5), uint32_t) & BM_AIPS_MPRA_MPL5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MPL5 field to a new value.
-#define BW_AIPS_MPRA_MPL5(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_MPRA, field MTW5[9] (RW)
- *
- * Determines whether the master is trusted for write accesses.
- *
- * Values:
- * - 0 - This master is not trusted for write accesses.
- * - 1 - This master is trusted for write accesses.
- */
-//@{
-#define BP_AIPS_MPRA_MTW5 (9U) //!< Bit position for AIPS_MPRA_MTW5.
-#define BM_AIPS_MPRA_MTW5 (0x00000200U) //!< Bit mask for AIPS_MPRA_MTW5.
-#define BS_AIPS_MPRA_MTW5 (1U) //!< Bit field size in bits for AIPS_MPRA_MTW5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_MPRA_MTW5 field.
-#define BR_AIPS_MPRA_MTW5(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW5))
-#endif
-
-//! @brief Format value for bitfield AIPS_MPRA_MTW5.
-#define BF_AIPS_MPRA_MTW5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTW5), uint32_t) & BM_AIPS_MPRA_MTW5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MTW5 field to a new value.
-#define BW_AIPS_MPRA_MTW5(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_MPRA, field MTR5[10] (RW)
- *
- * Determines whether the master is trusted for read accesses.
- *
- * Values:
- * - 0 - This master is not trusted for read accesses.
- * - 1 - This master is trusted for read accesses.
- */
-//@{
-#define BP_AIPS_MPRA_MTR5 (10U) //!< Bit position for AIPS_MPRA_MTR5.
-#define BM_AIPS_MPRA_MTR5 (0x00000400U) //!< Bit mask for AIPS_MPRA_MTR5.
-#define BS_AIPS_MPRA_MTR5 (1U) //!< Bit field size in bits for AIPS_MPRA_MTR5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_MPRA_MTR5 field.
-#define BR_AIPS_MPRA_MTR5(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR5))
-#endif
-
-//! @brief Format value for bitfield AIPS_MPRA_MTR5.
-#define BF_AIPS_MPRA_MTR5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTR5), uint32_t) & BM_AIPS_MPRA_MTR5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MTR5 field to a new value.
-#define BW_AIPS_MPRA_MTR5(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_MPRA, field MPL4[12] (RW)
- *
- * Specifies how the privilege level of the master is determined.
- *
- * Values:
- * - 0 - Accesses from this master are forced to user-mode.
- * - 1 - Accesses from this master are not forced to user-mode.
- */
-//@{
-#define BP_AIPS_MPRA_MPL4 (12U) //!< Bit position for AIPS_MPRA_MPL4.
-#define BM_AIPS_MPRA_MPL4 (0x00001000U) //!< Bit mask for AIPS_MPRA_MPL4.
-#define BS_AIPS_MPRA_MPL4 (1U) //!< Bit field size in bits for AIPS_MPRA_MPL4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_MPRA_MPL4 field.
-#define BR_AIPS_MPRA_MPL4(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL4))
-#endif
-
-//! @brief Format value for bitfield AIPS_MPRA_MPL4.
-#define BF_AIPS_MPRA_MPL4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MPL4), uint32_t) & BM_AIPS_MPRA_MPL4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MPL4 field to a new value.
-#define BW_AIPS_MPRA_MPL4(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_MPRA, field MTW4[13] (RW)
- *
- * Determines whether the master is trusted for write accesses.
- *
- * Values:
- * - 0 - This master is not trusted for write accesses.
- * - 1 - This master is trusted for write accesses.
- */
-//@{
-#define BP_AIPS_MPRA_MTW4 (13U) //!< Bit position for AIPS_MPRA_MTW4.
-#define BM_AIPS_MPRA_MTW4 (0x00002000U) //!< Bit mask for AIPS_MPRA_MTW4.
-#define BS_AIPS_MPRA_MTW4 (1U) //!< Bit field size in bits for AIPS_MPRA_MTW4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_MPRA_MTW4 field.
-#define BR_AIPS_MPRA_MTW4(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW4))
-#endif
-
-//! @brief Format value for bitfield AIPS_MPRA_MTW4.
-#define BF_AIPS_MPRA_MTW4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTW4), uint32_t) & BM_AIPS_MPRA_MTW4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MTW4 field to a new value.
-#define BW_AIPS_MPRA_MTW4(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_MPRA, field MTR4[14] (RW)
- *
- * Determines whether the master is trusted for read accesses.
- *
- * Values:
- * - 0 - This master is not trusted for read accesses.
- * - 1 - This master is trusted for read accesses.
- */
-//@{
-#define BP_AIPS_MPRA_MTR4 (14U) //!< Bit position for AIPS_MPRA_MTR4.
-#define BM_AIPS_MPRA_MTR4 (0x00004000U) //!< Bit mask for AIPS_MPRA_MTR4.
-#define BS_AIPS_MPRA_MTR4 (1U) //!< Bit field size in bits for AIPS_MPRA_MTR4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_MPRA_MTR4 field.
-#define BR_AIPS_MPRA_MTR4(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR4))
-#endif
-
-//! @brief Format value for bitfield AIPS_MPRA_MTR4.
-#define BF_AIPS_MPRA_MTR4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTR4), uint32_t) & BM_AIPS_MPRA_MTR4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MTR4 field to a new value.
-#define BW_AIPS_MPRA_MTR4(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_MPRA, field MPL3[16] (RW)
- *
- * Specifies how the privilege level of the master is determined.
- *
- * Values:
- * - 0 - Accesses from this master are forced to user-mode.
- * - 1 - Accesses from this master are not forced to user-mode.
- */
-//@{
-#define BP_AIPS_MPRA_MPL3 (16U) //!< Bit position for AIPS_MPRA_MPL3.
-#define BM_AIPS_MPRA_MPL3 (0x00010000U) //!< Bit mask for AIPS_MPRA_MPL3.
-#define BS_AIPS_MPRA_MPL3 (1U) //!< Bit field size in bits for AIPS_MPRA_MPL3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_MPRA_MPL3 field.
-#define BR_AIPS_MPRA_MPL3(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL3))
-#endif
-
-//! @brief Format value for bitfield AIPS_MPRA_MPL3.
-#define BF_AIPS_MPRA_MPL3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MPL3), uint32_t) & BM_AIPS_MPRA_MPL3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MPL3 field to a new value.
-#define BW_AIPS_MPRA_MPL3(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_MPRA, field MTW3[17] (RW)
- *
- * Determines whether the master is trusted for write accesses.
- *
- * Values:
- * - 0 - This master is not trusted for write accesses.
- * - 1 - This master is trusted for write accesses.
- */
-//@{
-#define BP_AIPS_MPRA_MTW3 (17U) //!< Bit position for AIPS_MPRA_MTW3.
-#define BM_AIPS_MPRA_MTW3 (0x00020000U) //!< Bit mask for AIPS_MPRA_MTW3.
-#define BS_AIPS_MPRA_MTW3 (1U) //!< Bit field size in bits for AIPS_MPRA_MTW3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_MPRA_MTW3 field.
-#define BR_AIPS_MPRA_MTW3(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW3))
-#endif
-
-//! @brief Format value for bitfield AIPS_MPRA_MTW3.
-#define BF_AIPS_MPRA_MTW3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTW3), uint32_t) & BM_AIPS_MPRA_MTW3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MTW3 field to a new value.
-#define BW_AIPS_MPRA_MTW3(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_MPRA, field MTR3[18] (RW)
- *
- * Determines whether the master is trusted for read accesses.
- *
- * Values:
- * - 0 - This master is not trusted for read accesses.
- * - 1 - This master is trusted for read accesses.
- */
-//@{
-#define BP_AIPS_MPRA_MTR3 (18U) //!< Bit position for AIPS_MPRA_MTR3.
-#define BM_AIPS_MPRA_MTR3 (0x00040000U) //!< Bit mask for AIPS_MPRA_MTR3.
-#define BS_AIPS_MPRA_MTR3 (1U) //!< Bit field size in bits for AIPS_MPRA_MTR3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_MPRA_MTR3 field.
-#define BR_AIPS_MPRA_MTR3(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR3))
-#endif
-
-//! @brief Format value for bitfield AIPS_MPRA_MTR3.
-#define BF_AIPS_MPRA_MTR3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTR3), uint32_t) & BM_AIPS_MPRA_MTR3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MTR3 field to a new value.
-#define BW_AIPS_MPRA_MTR3(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_MPRA, field MPL2[20] (RW)
- *
- * Specifies how the privilege level of the master is determined.
- *
- * Values:
- * - 0 - Accesses from this master are forced to user-mode.
- * - 1 - Accesses from this master are not forced to user-mode.
- */
-//@{
-#define BP_AIPS_MPRA_MPL2 (20U) //!< Bit position for AIPS_MPRA_MPL2.
-#define BM_AIPS_MPRA_MPL2 (0x00100000U) //!< Bit mask for AIPS_MPRA_MPL2.
-#define BS_AIPS_MPRA_MPL2 (1U) //!< Bit field size in bits for AIPS_MPRA_MPL2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_MPRA_MPL2 field.
-#define BR_AIPS_MPRA_MPL2(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL2))
-#endif
-
-//! @brief Format value for bitfield AIPS_MPRA_MPL2.
-#define BF_AIPS_MPRA_MPL2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MPL2), uint32_t) & BM_AIPS_MPRA_MPL2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MPL2 field to a new value.
-#define BW_AIPS_MPRA_MPL2(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_MPRA, field MTW2[21] (RW)
- *
- * Determines whether the master is trusted for write accesses.
- *
- * Values:
- * - 0 - This master is not trusted for write accesses.
- * - 1 - This master is trusted for write accesses.
- */
-//@{
-#define BP_AIPS_MPRA_MTW2 (21U) //!< Bit position for AIPS_MPRA_MTW2.
-#define BM_AIPS_MPRA_MTW2 (0x00200000U) //!< Bit mask for AIPS_MPRA_MTW2.
-#define BS_AIPS_MPRA_MTW2 (1U) //!< Bit field size in bits for AIPS_MPRA_MTW2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_MPRA_MTW2 field.
-#define BR_AIPS_MPRA_MTW2(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW2))
-#endif
-
-//! @brief Format value for bitfield AIPS_MPRA_MTW2.
-#define BF_AIPS_MPRA_MTW2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTW2), uint32_t) & BM_AIPS_MPRA_MTW2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MTW2 field to a new value.
-#define BW_AIPS_MPRA_MTW2(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_MPRA, field MTR2[22] (RW)
- *
- * Determines whether the master is trusted for read accesses.
- *
- * Values:
- * - 0 - This master is not trusted for read accesses.
- * - 1 - This master is trusted for read accesses.
- */
-//@{
-#define BP_AIPS_MPRA_MTR2 (22U) //!< Bit position for AIPS_MPRA_MTR2.
-#define BM_AIPS_MPRA_MTR2 (0x00400000U) //!< Bit mask for AIPS_MPRA_MTR2.
-#define BS_AIPS_MPRA_MTR2 (1U) //!< Bit field size in bits for AIPS_MPRA_MTR2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_MPRA_MTR2 field.
-#define BR_AIPS_MPRA_MTR2(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR2))
-#endif
-
-//! @brief Format value for bitfield AIPS_MPRA_MTR2.
-#define BF_AIPS_MPRA_MTR2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTR2), uint32_t) & BM_AIPS_MPRA_MTR2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MTR2 field to a new value.
-#define BW_AIPS_MPRA_MTR2(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_MPRA, field MPL1[24] (RW)
- *
- * Specifies how the privilege level of the master is determined.
- *
- * Values:
- * - 0 - Accesses from this master are forced to user-mode.
- * - 1 - Accesses from this master are not forced to user-mode.
- */
-//@{
-#define BP_AIPS_MPRA_MPL1 (24U) //!< Bit position for AIPS_MPRA_MPL1.
-#define BM_AIPS_MPRA_MPL1 (0x01000000U) //!< Bit mask for AIPS_MPRA_MPL1.
-#define BS_AIPS_MPRA_MPL1 (1U) //!< Bit field size in bits for AIPS_MPRA_MPL1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_MPRA_MPL1 field.
-#define BR_AIPS_MPRA_MPL1(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL1))
-#endif
-
-//! @brief Format value for bitfield AIPS_MPRA_MPL1.
-#define BF_AIPS_MPRA_MPL1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MPL1), uint32_t) & BM_AIPS_MPRA_MPL1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MPL1 field to a new value.
-#define BW_AIPS_MPRA_MPL1(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_MPRA, field MTW1[25] (RW)
- *
- * Determines whether the master is trusted for write accesses.
- *
- * Values:
- * - 0 - This master is not trusted for write accesses.
- * - 1 - This master is trusted for write accesses.
- */
-//@{
-#define BP_AIPS_MPRA_MTW1 (25U) //!< Bit position for AIPS_MPRA_MTW1.
-#define BM_AIPS_MPRA_MTW1 (0x02000000U) //!< Bit mask for AIPS_MPRA_MTW1.
-#define BS_AIPS_MPRA_MTW1 (1U) //!< Bit field size in bits for AIPS_MPRA_MTW1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_MPRA_MTW1 field.
-#define BR_AIPS_MPRA_MTW1(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW1))
-#endif
-
-//! @brief Format value for bitfield AIPS_MPRA_MTW1.
-#define BF_AIPS_MPRA_MTW1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTW1), uint32_t) & BM_AIPS_MPRA_MTW1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MTW1 field to a new value.
-#define BW_AIPS_MPRA_MTW1(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_MPRA, field MTR1[26] (RW)
- *
- * Determines whether the master is trusted for read accesses.
- *
- * Values:
- * - 0 - This master is not trusted for read accesses.
- * - 1 - This master is trusted for read accesses.
- */
-//@{
-#define BP_AIPS_MPRA_MTR1 (26U) //!< Bit position for AIPS_MPRA_MTR1.
-#define BM_AIPS_MPRA_MTR1 (0x04000000U) //!< Bit mask for AIPS_MPRA_MTR1.
-#define BS_AIPS_MPRA_MTR1 (1U) //!< Bit field size in bits for AIPS_MPRA_MTR1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_MPRA_MTR1 field.
-#define BR_AIPS_MPRA_MTR1(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR1))
-#endif
-
-//! @brief Format value for bitfield AIPS_MPRA_MTR1.
-#define BF_AIPS_MPRA_MTR1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTR1), uint32_t) & BM_AIPS_MPRA_MTR1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MTR1 field to a new value.
-#define BW_AIPS_MPRA_MTR1(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_MPRA, field MPL0[28] (RW)
- *
- * Specifies how the privilege level of the master is determined.
- *
- * Values:
- * - 0 - Accesses from this master are forced to user-mode.
- * - 1 - Accesses from this master are not forced to user-mode.
- */
-//@{
-#define BP_AIPS_MPRA_MPL0 (28U) //!< Bit position for AIPS_MPRA_MPL0.
-#define BM_AIPS_MPRA_MPL0 (0x10000000U) //!< Bit mask for AIPS_MPRA_MPL0.
-#define BS_AIPS_MPRA_MPL0 (1U) //!< Bit field size in bits for AIPS_MPRA_MPL0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_MPRA_MPL0 field.
-#define BR_AIPS_MPRA_MPL0(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL0))
-#endif
-
-//! @brief Format value for bitfield AIPS_MPRA_MPL0.
-#define BF_AIPS_MPRA_MPL0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MPL0), uint32_t) & BM_AIPS_MPRA_MPL0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MPL0 field to a new value.
-#define BW_AIPS_MPRA_MPL0(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_MPRA, field MTW0[29] (RW)
- *
- * Determines whether the master is trusted for write accesses.
- *
- * Values:
- * - 0 - This master is not trusted for write accesses.
- * - 1 - This master is trusted for write accesses.
- */
-//@{
-#define BP_AIPS_MPRA_MTW0 (29U) //!< Bit position for AIPS_MPRA_MTW0.
-#define BM_AIPS_MPRA_MTW0 (0x20000000U) //!< Bit mask for AIPS_MPRA_MTW0.
-#define BS_AIPS_MPRA_MTW0 (1U) //!< Bit field size in bits for AIPS_MPRA_MTW0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_MPRA_MTW0 field.
-#define BR_AIPS_MPRA_MTW0(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW0))
-#endif
-
-//! @brief Format value for bitfield AIPS_MPRA_MTW0.
-#define BF_AIPS_MPRA_MTW0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTW0), uint32_t) & BM_AIPS_MPRA_MTW0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MTW0 field to a new value.
-#define BW_AIPS_MPRA_MTW0(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_MPRA, field MTR0[30] (RW)
- *
- * Determines whether the master is trusted for read accesses.
- *
- * Values:
- * - 0 - This master is not trusted for read accesses.
- * - 1 - This master is trusted for read accesses.
- */
-//@{
-#define BP_AIPS_MPRA_MTR0 (30U) //!< Bit position for AIPS_MPRA_MTR0.
-#define BM_AIPS_MPRA_MTR0 (0x40000000U) //!< Bit mask for AIPS_MPRA_MTR0.
-#define BS_AIPS_MPRA_MTR0 (1U) //!< Bit field size in bits for AIPS_MPRA_MTR0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_MPRA_MTR0 field.
-#define BR_AIPS_MPRA_MTR0(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR0))
-#endif
-
-//! @brief Format value for bitfield AIPS_MPRA_MTR0.
-#define BF_AIPS_MPRA_MTR0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTR0), uint32_t) & BM_AIPS_MPRA_MTR0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MTR0 field to a new value.
-#define BW_AIPS_MPRA_MTR0(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR0) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_AIPS_PACRA - Peripheral Access Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_AIPS_PACRA - Peripheral Access Control Register (RW)
- *
- * Reset value: 0x50004000U
- *
- * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
- * defines the access levels for a particular peripheral. The mapping between a
- * peripheral and its PACR field is shown in the table below. The peripheral assignment
- * to each PACR is defined by the memory map slot that the peripheral is
- * assigned to. See this chip's memory map for the assignment of a particular
- * peripheral. The following table shows the location of each peripheral slot's PACR field
- * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
- * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
- * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
- * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
- * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
- * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
- * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
- * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
- * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
- * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
- * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
- * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
- * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
- * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
- * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
- * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
- * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
- * A-D, which control peripheral slots 0-31, are shown below. The following
- * section, PACRPeripheral Access Control Register , shows the register field
- * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
- * sections because they occupy two non-contiguous address spaces.
- */
-typedef union _hw_aips_pacra
-{
- uint32_t U;
- struct _hw_aips_pacra_bitfields
- {
- uint32_t TP7 : 1; //!< [0] Trusted Protect
- uint32_t WP7 : 1; //!< [1] Write Protect
- uint32_t SP7 : 1; //!< [2] Supervisor Protect
- uint32_t RESERVED0 : 1; //!< [3]
- uint32_t TP6 : 1; //!< [4] Trusted Protect
- uint32_t WP6 : 1; //!< [5] Write Protect
- uint32_t SP6 : 1; //!< [6] Supervisor Protect
- uint32_t RESERVED1 : 1; //!< [7]
- uint32_t TP5 : 1; //!< [8] Trusted Protect
- uint32_t WP5 : 1; //!< [9] Write Protect
- uint32_t SP5 : 1; //!< [10] Supervisor Protect
- uint32_t RESERVED2 : 1; //!< [11]
- uint32_t TP4 : 1; //!< [12] Trusted Protect
- uint32_t WP4 : 1; //!< [13] Write Protect
- uint32_t SP4 : 1; //!< [14] Supervisor Protect
- uint32_t RESERVED3 : 1; //!< [15]
- uint32_t TP3 : 1; //!< [16] Trusted Protect
- uint32_t WP3 : 1; //!< [17] Write Protect
- uint32_t SP3 : 1; //!< [18] Supervisor Protect
- uint32_t RESERVED4 : 1; //!< [19]
- uint32_t TP2 : 1; //!< [20] Trusted Protect
- uint32_t WP2 : 1; //!< [21] Write Protect
- uint32_t SP2 : 1; //!< [22] Supervisor Protect
- uint32_t RESERVED5 : 1; //!< [23]
- uint32_t TP1 : 1; //!< [24] Trusted Protect
- uint32_t WP1 : 1; //!< [25] Write Protect
- uint32_t SP1 : 1; //!< [26] Supervisor Protect
- uint32_t RESERVED6 : 1; //!< [27]
- uint32_t TP0 : 1; //!< [28] Trusted Protect
- uint32_t WP0 : 1; //!< [29] Write Protect
- uint32_t SP0 : 1; //!< [30] Supervisor Protect
- uint32_t RESERVED7 : 1; //!< [31]
- } B;
-} hw_aips_pacra_t;
-#endif
-
-/*!
- * @name Constants and macros for entire AIPS_PACRA register
- */
-//@{
-#define HW_AIPS_PACRA_ADDR(x) (REGS_AIPS_BASE(x) + 0x20U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_AIPS_PACRA(x) (*(__IO hw_aips_pacra_t *) HW_AIPS_PACRA_ADDR(x))
-#define HW_AIPS_PACRA_RD(x) (HW_AIPS_PACRA(x).U)
-#define HW_AIPS_PACRA_WR(x, v) (HW_AIPS_PACRA(x).U = (v))
-#define HW_AIPS_PACRA_SET(x, v) (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) | (v)))
-#define HW_AIPS_PACRA_CLR(x, v) (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) & ~(v)))
-#define HW_AIPS_PACRA_TOG(x, v) (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual AIPS_PACRA bitfields
- */
-
-/*!
- * @name Register AIPS_PACRA, field TP7[0] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRA_TP7 (0U) //!< Bit position for AIPS_PACRA_TP7.
-#define BM_AIPS_PACRA_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRA_TP7.
-#define BS_AIPS_PACRA_TP7 (1U) //!< Bit field size in bits for AIPS_PACRA_TP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRA_TP7 field.
-#define BR_AIPS_PACRA_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRA_TP7.
-#define BF_AIPS_PACRA_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP7), uint32_t) & BM_AIPS_PACRA_TP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP7 field to a new value.
-#define BW_AIPS_PACRA_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRA, field WP7[1] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRA_WP7 (1U) //!< Bit position for AIPS_PACRA_WP7.
-#define BM_AIPS_PACRA_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRA_WP7.
-#define BS_AIPS_PACRA_WP7 (1U) //!< Bit field size in bits for AIPS_PACRA_WP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRA_WP7 field.
-#define BR_AIPS_PACRA_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRA_WP7.
-#define BF_AIPS_PACRA_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP7), uint32_t) & BM_AIPS_PACRA_WP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP7 field to a new value.
-#define BW_AIPS_PACRA_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRA, field SP7[2] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRA_SP7 (2U) //!< Bit position for AIPS_PACRA_SP7.
-#define BM_AIPS_PACRA_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRA_SP7.
-#define BS_AIPS_PACRA_SP7 (1U) //!< Bit field size in bits for AIPS_PACRA_SP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRA_SP7 field.
-#define BR_AIPS_PACRA_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRA_SP7.
-#define BF_AIPS_PACRA_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP7), uint32_t) & BM_AIPS_PACRA_SP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP7 field to a new value.
-#define BW_AIPS_PACRA_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRA, field TP6[4] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRA_TP6 (4U) //!< Bit position for AIPS_PACRA_TP6.
-#define BM_AIPS_PACRA_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRA_TP6.
-#define BS_AIPS_PACRA_TP6 (1U) //!< Bit field size in bits for AIPS_PACRA_TP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRA_TP6 field.
-#define BR_AIPS_PACRA_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRA_TP6.
-#define BF_AIPS_PACRA_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP6), uint32_t) & BM_AIPS_PACRA_TP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP6 field to a new value.
-#define BW_AIPS_PACRA_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRA, field WP6[5] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRA_WP6 (5U) //!< Bit position for AIPS_PACRA_WP6.
-#define BM_AIPS_PACRA_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRA_WP6.
-#define BS_AIPS_PACRA_WP6 (1U) //!< Bit field size in bits for AIPS_PACRA_WP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRA_WP6 field.
-#define BR_AIPS_PACRA_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRA_WP6.
-#define BF_AIPS_PACRA_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP6), uint32_t) & BM_AIPS_PACRA_WP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP6 field to a new value.
-#define BW_AIPS_PACRA_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRA, field SP6[6] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRA_SP6 (6U) //!< Bit position for AIPS_PACRA_SP6.
-#define BM_AIPS_PACRA_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRA_SP6.
-#define BS_AIPS_PACRA_SP6 (1U) //!< Bit field size in bits for AIPS_PACRA_SP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRA_SP6 field.
-#define BR_AIPS_PACRA_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRA_SP6.
-#define BF_AIPS_PACRA_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP6), uint32_t) & BM_AIPS_PACRA_SP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP6 field to a new value.
-#define BW_AIPS_PACRA_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRA, field TP5[8] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRA_TP5 (8U) //!< Bit position for AIPS_PACRA_TP5.
-#define BM_AIPS_PACRA_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRA_TP5.
-#define BS_AIPS_PACRA_TP5 (1U) //!< Bit field size in bits for AIPS_PACRA_TP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRA_TP5 field.
-#define BR_AIPS_PACRA_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRA_TP5.
-#define BF_AIPS_PACRA_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP5), uint32_t) & BM_AIPS_PACRA_TP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP5 field to a new value.
-#define BW_AIPS_PACRA_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRA, field WP5[9] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRA_WP5 (9U) //!< Bit position for AIPS_PACRA_WP5.
-#define BM_AIPS_PACRA_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRA_WP5.
-#define BS_AIPS_PACRA_WP5 (1U) //!< Bit field size in bits for AIPS_PACRA_WP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRA_WP5 field.
-#define BR_AIPS_PACRA_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRA_WP5.
-#define BF_AIPS_PACRA_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP5), uint32_t) & BM_AIPS_PACRA_WP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP5 field to a new value.
-#define BW_AIPS_PACRA_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRA, field SP5[10] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRA_SP5 (10U) //!< Bit position for AIPS_PACRA_SP5.
-#define BM_AIPS_PACRA_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRA_SP5.
-#define BS_AIPS_PACRA_SP5 (1U) //!< Bit field size in bits for AIPS_PACRA_SP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRA_SP5 field.
-#define BR_AIPS_PACRA_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRA_SP5.
-#define BF_AIPS_PACRA_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP5), uint32_t) & BM_AIPS_PACRA_SP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP5 field to a new value.
-#define BW_AIPS_PACRA_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRA, field TP4[12] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRA_TP4 (12U) //!< Bit position for AIPS_PACRA_TP4.
-#define BM_AIPS_PACRA_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRA_TP4.
-#define BS_AIPS_PACRA_TP4 (1U) //!< Bit field size in bits for AIPS_PACRA_TP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRA_TP4 field.
-#define BR_AIPS_PACRA_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRA_TP4.
-#define BF_AIPS_PACRA_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP4), uint32_t) & BM_AIPS_PACRA_TP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP4 field to a new value.
-#define BW_AIPS_PACRA_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRA, field WP4[13] (RW)
- *
- * Determines whether the peripheral allows write accesss. When this bit is set
- * and a write access is attempted, access terminates with an error response and
- * no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRA_WP4 (13U) //!< Bit position for AIPS_PACRA_WP4.
-#define BM_AIPS_PACRA_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRA_WP4.
-#define BS_AIPS_PACRA_WP4 (1U) //!< Bit field size in bits for AIPS_PACRA_WP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRA_WP4 field.
-#define BR_AIPS_PACRA_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRA_WP4.
-#define BF_AIPS_PACRA_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP4), uint32_t) & BM_AIPS_PACRA_WP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP4 field to a new value.
-#define BW_AIPS_PACRA_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRA, field SP4[14] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRA_SP4 (14U) //!< Bit position for AIPS_PACRA_SP4.
-#define BM_AIPS_PACRA_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRA_SP4.
-#define BS_AIPS_PACRA_SP4 (1U) //!< Bit field size in bits for AIPS_PACRA_SP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRA_SP4 field.
-#define BR_AIPS_PACRA_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRA_SP4.
-#define BF_AIPS_PACRA_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP4), uint32_t) & BM_AIPS_PACRA_SP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP4 field to a new value.
-#define BW_AIPS_PACRA_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRA, field TP3[16] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRA_TP3 (16U) //!< Bit position for AIPS_PACRA_TP3.
-#define BM_AIPS_PACRA_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRA_TP3.
-#define BS_AIPS_PACRA_TP3 (1U) //!< Bit field size in bits for AIPS_PACRA_TP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRA_TP3 field.
-#define BR_AIPS_PACRA_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRA_TP3.
-#define BF_AIPS_PACRA_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP3), uint32_t) & BM_AIPS_PACRA_TP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP3 field to a new value.
-#define BW_AIPS_PACRA_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRA, field WP3[17] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRA_WP3 (17U) //!< Bit position for AIPS_PACRA_WP3.
-#define BM_AIPS_PACRA_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRA_WP3.
-#define BS_AIPS_PACRA_WP3 (1U) //!< Bit field size in bits for AIPS_PACRA_WP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRA_WP3 field.
-#define BR_AIPS_PACRA_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRA_WP3.
-#define BF_AIPS_PACRA_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP3), uint32_t) & BM_AIPS_PACRA_WP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP3 field to a new value.
-#define BW_AIPS_PACRA_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRA, field SP3[18] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this bit is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
- * set. If not, access terminates with an error response and no peripheral access
- * initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRA_SP3 (18U) //!< Bit position for AIPS_PACRA_SP3.
-#define BM_AIPS_PACRA_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRA_SP3.
-#define BS_AIPS_PACRA_SP3 (1U) //!< Bit field size in bits for AIPS_PACRA_SP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRA_SP3 field.
-#define BR_AIPS_PACRA_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRA_SP3.
-#define BF_AIPS_PACRA_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP3), uint32_t) & BM_AIPS_PACRA_SP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP3 field to a new value.
-#define BW_AIPS_PACRA_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRA, field TP2[20] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRA_TP2 (20U) //!< Bit position for AIPS_PACRA_TP2.
-#define BM_AIPS_PACRA_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRA_TP2.
-#define BS_AIPS_PACRA_TP2 (1U) //!< Bit field size in bits for AIPS_PACRA_TP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRA_TP2 field.
-#define BR_AIPS_PACRA_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRA_TP2.
-#define BF_AIPS_PACRA_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP2), uint32_t) & BM_AIPS_PACRA_TP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP2 field to a new value.
-#define BW_AIPS_PACRA_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRA, field WP2[21] (RW)
- *
- * Determines whether the peripheral allows write accesss. When this bit is set
- * and a write access is attempted, access terminates with an error response and
- * no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRA_WP2 (21U) //!< Bit position for AIPS_PACRA_WP2.
-#define BM_AIPS_PACRA_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRA_WP2.
-#define BS_AIPS_PACRA_WP2 (1U) //!< Bit field size in bits for AIPS_PACRA_WP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRA_WP2 field.
-#define BR_AIPS_PACRA_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRA_WP2.
-#define BF_AIPS_PACRA_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP2), uint32_t) & BM_AIPS_PACRA_WP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP2 field to a new value.
-#define BW_AIPS_PACRA_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRA, field SP2[22] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRA_SP2 (22U) //!< Bit position for AIPS_PACRA_SP2.
-#define BM_AIPS_PACRA_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRA_SP2.
-#define BS_AIPS_PACRA_SP2 (1U) //!< Bit field size in bits for AIPS_PACRA_SP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRA_SP2 field.
-#define BR_AIPS_PACRA_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRA_SP2.
-#define BF_AIPS_PACRA_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP2), uint32_t) & BM_AIPS_PACRA_SP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP2 field to a new value.
-#define BW_AIPS_PACRA_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRA, field TP1[24] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRA_TP1 (24U) //!< Bit position for AIPS_PACRA_TP1.
-#define BM_AIPS_PACRA_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRA_TP1.
-#define BS_AIPS_PACRA_TP1 (1U) //!< Bit field size in bits for AIPS_PACRA_TP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRA_TP1 field.
-#define BR_AIPS_PACRA_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRA_TP1.
-#define BF_AIPS_PACRA_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP1), uint32_t) & BM_AIPS_PACRA_TP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP1 field to a new value.
-#define BW_AIPS_PACRA_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRA, field WP1[25] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRA_WP1 (25U) //!< Bit position for AIPS_PACRA_WP1.
-#define BM_AIPS_PACRA_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRA_WP1.
-#define BS_AIPS_PACRA_WP1 (1U) //!< Bit field size in bits for AIPS_PACRA_WP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRA_WP1 field.
-#define BR_AIPS_PACRA_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRA_WP1.
-#define BF_AIPS_PACRA_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP1), uint32_t) & BM_AIPS_PACRA_WP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP1 field to a new value.
-#define BW_AIPS_PACRA_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRA, field SP1[26] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRA_SP1 (26U) //!< Bit position for AIPS_PACRA_SP1.
-#define BM_AIPS_PACRA_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRA_SP1.
-#define BS_AIPS_PACRA_SP1 (1U) //!< Bit field size in bits for AIPS_PACRA_SP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRA_SP1 field.
-#define BR_AIPS_PACRA_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRA_SP1.
-#define BF_AIPS_PACRA_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP1), uint32_t) & BM_AIPS_PACRA_SP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP1 field to a new value.
-#define BW_AIPS_PACRA_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRA, field TP0[28] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRA_TP0 (28U) //!< Bit position for AIPS_PACRA_TP0.
-#define BM_AIPS_PACRA_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRA_TP0.
-#define BS_AIPS_PACRA_TP0 (1U) //!< Bit field size in bits for AIPS_PACRA_TP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRA_TP0 field.
-#define BR_AIPS_PACRA_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRA_TP0.
-#define BF_AIPS_PACRA_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP0), uint32_t) & BM_AIPS_PACRA_TP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP0 field to a new value.
-#define BW_AIPS_PACRA_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRA, field WP0[29] (RW)
- *
- * Determines whether the peripheral allows write accesss. When this bit is set
- * and a write access is attempted, access terminates with an error response and
- * no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRA_WP0 (29U) //!< Bit position for AIPS_PACRA_WP0.
-#define BM_AIPS_PACRA_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRA_WP0.
-#define BS_AIPS_PACRA_WP0 (1U) //!< Bit field size in bits for AIPS_PACRA_WP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRA_WP0 field.
-#define BR_AIPS_PACRA_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRA_WP0.
-#define BF_AIPS_PACRA_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP0), uint32_t) & BM_AIPS_PACRA_WP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP0 field to a new value.
-#define BW_AIPS_PACRA_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRA, field SP0[30] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRA_SP0 (30U) //!< Bit position for AIPS_PACRA_SP0.
-#define BM_AIPS_PACRA_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRA_SP0.
-#define BS_AIPS_PACRA_SP0 (1U) //!< Bit field size in bits for AIPS_PACRA_SP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRA_SP0 field.
-#define BR_AIPS_PACRA_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRA_SP0.
-#define BF_AIPS_PACRA_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP0), uint32_t) & BM_AIPS_PACRA_SP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP0 field to a new value.
-#define BW_AIPS_PACRA_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP0) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_AIPS_PACRB - Peripheral Access Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_AIPS_PACRB - Peripheral Access Control Register (RW)
- *
- * Reset value: 0x44004400U
- *
- * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
- * defines the access levels for a particular peripheral. The mapping between a
- * peripheral and its PACR field is shown in the table below. The peripheral assignment
- * to each PACR is defined by the memory map slot that the peripheral is
- * assigned to. See this chip's memory map for the assignment of a particular
- * peripheral. The following table shows the location of each peripheral slot's PACR field
- * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
- * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
- * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
- * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
- * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
- * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
- * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
- * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
- * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
- * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
- * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
- * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
- * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
- * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
- * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
- * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
- * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
- * A-D, which control peripheral slots 0-31, are shown below. The following
- * section, PACRPeripheral Access Control Register , shows the register field
- * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
- * sections because they occupy two non-contiguous address spaces.
- */
-typedef union _hw_aips_pacrb
-{
- uint32_t U;
- struct _hw_aips_pacrb_bitfields
- {
- uint32_t TP7 : 1; //!< [0] Trusted Protect
- uint32_t WP7 : 1; //!< [1] Write Protect
- uint32_t SP7 : 1; //!< [2] Supervisor Protect
- uint32_t RESERVED0 : 1; //!< [3]
- uint32_t TP6 : 1; //!< [4] Trusted Protect
- uint32_t WP6 : 1; //!< [5] Write Protect
- uint32_t SP6 : 1; //!< [6] Supervisor Protect
- uint32_t RESERVED1 : 1; //!< [7]
- uint32_t TP5 : 1; //!< [8] Trusted Protect
- uint32_t WP5 : 1; //!< [9] Write Protect
- uint32_t SP5 : 1; //!< [10] Supervisor Protect
- uint32_t RESERVED2 : 1; //!< [11]
- uint32_t TP4 : 1; //!< [12] Trusted Protect
- uint32_t WP4 : 1; //!< [13] Write Protect
- uint32_t SP4 : 1; //!< [14] Supervisor Protect
- uint32_t RESERVED3 : 1; //!< [15]
- uint32_t TP3 : 1; //!< [16] Trusted Protect
- uint32_t WP3 : 1; //!< [17] Write Protect
- uint32_t SP3 : 1; //!< [18] Supervisor Protect
- uint32_t RESERVED4 : 1; //!< [19]
- uint32_t TP2 : 1; //!< [20] Trusted Protect
- uint32_t WP2 : 1; //!< [21] Write Protect
- uint32_t SP2 : 1; //!< [22] Supervisor Protect
- uint32_t RESERVED5 : 1; //!< [23]
- uint32_t TP1 : 1; //!< [24] Trusted Protect
- uint32_t WP1 : 1; //!< [25] Write Protect
- uint32_t SP1 : 1; //!< [26] Supervisor Protect
- uint32_t RESERVED6 : 1; //!< [27]
- uint32_t TP0 : 1; //!< [28] Trusted Protect
- uint32_t WP0 : 1; //!< [29] Write Protect
- uint32_t SP0 : 1; //!< [30] Supervisor Protect
- uint32_t RESERVED7 : 1; //!< [31]
- } B;
-} hw_aips_pacrb_t;
-#endif
-
-/*!
- * @name Constants and macros for entire AIPS_PACRB register
- */
-//@{
-#define HW_AIPS_PACRB_ADDR(x) (REGS_AIPS_BASE(x) + 0x24U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_AIPS_PACRB(x) (*(__IO hw_aips_pacrb_t *) HW_AIPS_PACRB_ADDR(x))
-#define HW_AIPS_PACRB_RD(x) (HW_AIPS_PACRB(x).U)
-#define HW_AIPS_PACRB_WR(x, v) (HW_AIPS_PACRB(x).U = (v))
-#define HW_AIPS_PACRB_SET(x, v) (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) | (v)))
-#define HW_AIPS_PACRB_CLR(x, v) (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) & ~(v)))
-#define HW_AIPS_PACRB_TOG(x, v) (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual AIPS_PACRB bitfields
- */
-
-/*!
- * @name Register AIPS_PACRB, field TP7[0] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRB_TP7 (0U) //!< Bit position for AIPS_PACRB_TP7.
-#define BM_AIPS_PACRB_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRB_TP7.
-#define BS_AIPS_PACRB_TP7 (1U) //!< Bit field size in bits for AIPS_PACRB_TP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRB_TP7 field.
-#define BR_AIPS_PACRB_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRB_TP7.
-#define BF_AIPS_PACRB_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP7), uint32_t) & BM_AIPS_PACRB_TP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP7 field to a new value.
-#define BW_AIPS_PACRB_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRB, field WP7[1] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRB_WP7 (1U) //!< Bit position for AIPS_PACRB_WP7.
-#define BM_AIPS_PACRB_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRB_WP7.
-#define BS_AIPS_PACRB_WP7 (1U) //!< Bit field size in bits for AIPS_PACRB_WP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRB_WP7 field.
-#define BR_AIPS_PACRB_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRB_WP7.
-#define BF_AIPS_PACRB_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP7), uint32_t) & BM_AIPS_PACRB_WP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP7 field to a new value.
-#define BW_AIPS_PACRB_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRB, field SP7[2] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRB_SP7 (2U) //!< Bit position for AIPS_PACRB_SP7.
-#define BM_AIPS_PACRB_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRB_SP7.
-#define BS_AIPS_PACRB_SP7 (1U) //!< Bit field size in bits for AIPS_PACRB_SP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRB_SP7 field.
-#define BR_AIPS_PACRB_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRB_SP7.
-#define BF_AIPS_PACRB_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP7), uint32_t) & BM_AIPS_PACRB_SP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP7 field to a new value.
-#define BW_AIPS_PACRB_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRB, field TP6[4] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRB_TP6 (4U) //!< Bit position for AIPS_PACRB_TP6.
-#define BM_AIPS_PACRB_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRB_TP6.
-#define BS_AIPS_PACRB_TP6 (1U) //!< Bit field size in bits for AIPS_PACRB_TP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRB_TP6 field.
-#define BR_AIPS_PACRB_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRB_TP6.
-#define BF_AIPS_PACRB_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP6), uint32_t) & BM_AIPS_PACRB_TP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP6 field to a new value.
-#define BW_AIPS_PACRB_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRB, field WP6[5] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRB_WP6 (5U) //!< Bit position for AIPS_PACRB_WP6.
-#define BM_AIPS_PACRB_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRB_WP6.
-#define BS_AIPS_PACRB_WP6 (1U) //!< Bit field size in bits for AIPS_PACRB_WP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRB_WP6 field.
-#define BR_AIPS_PACRB_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRB_WP6.
-#define BF_AIPS_PACRB_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP6), uint32_t) & BM_AIPS_PACRB_WP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP6 field to a new value.
-#define BW_AIPS_PACRB_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRB, field SP6[6] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRB_SP6 (6U) //!< Bit position for AIPS_PACRB_SP6.
-#define BM_AIPS_PACRB_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRB_SP6.
-#define BS_AIPS_PACRB_SP6 (1U) //!< Bit field size in bits for AIPS_PACRB_SP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRB_SP6 field.
-#define BR_AIPS_PACRB_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRB_SP6.
-#define BF_AIPS_PACRB_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP6), uint32_t) & BM_AIPS_PACRB_SP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP6 field to a new value.
-#define BW_AIPS_PACRB_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRB, field TP5[8] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRB_TP5 (8U) //!< Bit position for AIPS_PACRB_TP5.
-#define BM_AIPS_PACRB_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRB_TP5.
-#define BS_AIPS_PACRB_TP5 (1U) //!< Bit field size in bits for AIPS_PACRB_TP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRB_TP5 field.
-#define BR_AIPS_PACRB_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRB_TP5.
-#define BF_AIPS_PACRB_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP5), uint32_t) & BM_AIPS_PACRB_TP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP5 field to a new value.
-#define BW_AIPS_PACRB_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRB, field WP5[9] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRB_WP5 (9U) //!< Bit position for AIPS_PACRB_WP5.
-#define BM_AIPS_PACRB_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRB_WP5.
-#define BS_AIPS_PACRB_WP5 (1U) //!< Bit field size in bits for AIPS_PACRB_WP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRB_WP5 field.
-#define BR_AIPS_PACRB_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRB_WP5.
-#define BF_AIPS_PACRB_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP5), uint32_t) & BM_AIPS_PACRB_WP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP5 field to a new value.
-#define BW_AIPS_PACRB_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRB, field SP5[10] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRB_SP5 (10U) //!< Bit position for AIPS_PACRB_SP5.
-#define BM_AIPS_PACRB_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRB_SP5.
-#define BS_AIPS_PACRB_SP5 (1U) //!< Bit field size in bits for AIPS_PACRB_SP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRB_SP5 field.
-#define BR_AIPS_PACRB_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRB_SP5.
-#define BF_AIPS_PACRB_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP5), uint32_t) & BM_AIPS_PACRB_SP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP5 field to a new value.
-#define BW_AIPS_PACRB_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRB, field TP4[12] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRB_TP4 (12U) //!< Bit position for AIPS_PACRB_TP4.
-#define BM_AIPS_PACRB_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRB_TP4.
-#define BS_AIPS_PACRB_TP4 (1U) //!< Bit field size in bits for AIPS_PACRB_TP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRB_TP4 field.
-#define BR_AIPS_PACRB_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRB_TP4.
-#define BF_AIPS_PACRB_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP4), uint32_t) & BM_AIPS_PACRB_TP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP4 field to a new value.
-#define BW_AIPS_PACRB_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRB, field WP4[13] (RW)
- *
- * Determines whether the peripheral allows write accesss. When this bit is set
- * and a write access is attempted, access terminates with an error response and
- * no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRB_WP4 (13U) //!< Bit position for AIPS_PACRB_WP4.
-#define BM_AIPS_PACRB_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRB_WP4.
-#define BS_AIPS_PACRB_WP4 (1U) //!< Bit field size in bits for AIPS_PACRB_WP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRB_WP4 field.
-#define BR_AIPS_PACRB_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRB_WP4.
-#define BF_AIPS_PACRB_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP4), uint32_t) & BM_AIPS_PACRB_WP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP4 field to a new value.
-#define BW_AIPS_PACRB_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRB, field SP4[14] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRB_SP4 (14U) //!< Bit position for AIPS_PACRB_SP4.
-#define BM_AIPS_PACRB_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRB_SP4.
-#define BS_AIPS_PACRB_SP4 (1U) //!< Bit field size in bits for AIPS_PACRB_SP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRB_SP4 field.
-#define BR_AIPS_PACRB_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRB_SP4.
-#define BF_AIPS_PACRB_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP4), uint32_t) & BM_AIPS_PACRB_SP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP4 field to a new value.
-#define BW_AIPS_PACRB_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRB, field TP3[16] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRB_TP3 (16U) //!< Bit position for AIPS_PACRB_TP3.
-#define BM_AIPS_PACRB_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRB_TP3.
-#define BS_AIPS_PACRB_TP3 (1U) //!< Bit field size in bits for AIPS_PACRB_TP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRB_TP3 field.
-#define BR_AIPS_PACRB_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRB_TP3.
-#define BF_AIPS_PACRB_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP3), uint32_t) & BM_AIPS_PACRB_TP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP3 field to a new value.
-#define BW_AIPS_PACRB_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRB, field WP3[17] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRB_WP3 (17U) //!< Bit position for AIPS_PACRB_WP3.
-#define BM_AIPS_PACRB_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRB_WP3.
-#define BS_AIPS_PACRB_WP3 (1U) //!< Bit field size in bits for AIPS_PACRB_WP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRB_WP3 field.
-#define BR_AIPS_PACRB_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRB_WP3.
-#define BF_AIPS_PACRB_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP3), uint32_t) & BM_AIPS_PACRB_WP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP3 field to a new value.
-#define BW_AIPS_PACRB_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRB, field SP3[18] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this bit is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
- * set. If not, access terminates with an error response and no peripheral access
- * initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRB_SP3 (18U) //!< Bit position for AIPS_PACRB_SP3.
-#define BM_AIPS_PACRB_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRB_SP3.
-#define BS_AIPS_PACRB_SP3 (1U) //!< Bit field size in bits for AIPS_PACRB_SP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRB_SP3 field.
-#define BR_AIPS_PACRB_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRB_SP3.
-#define BF_AIPS_PACRB_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP3), uint32_t) & BM_AIPS_PACRB_SP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP3 field to a new value.
-#define BW_AIPS_PACRB_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRB, field TP2[20] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRB_TP2 (20U) //!< Bit position for AIPS_PACRB_TP2.
-#define BM_AIPS_PACRB_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRB_TP2.
-#define BS_AIPS_PACRB_TP2 (1U) //!< Bit field size in bits for AIPS_PACRB_TP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRB_TP2 field.
-#define BR_AIPS_PACRB_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRB_TP2.
-#define BF_AIPS_PACRB_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP2), uint32_t) & BM_AIPS_PACRB_TP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP2 field to a new value.
-#define BW_AIPS_PACRB_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRB, field WP2[21] (RW)
- *
- * Determines whether the peripheral allows write accesss. When this bit is set
- * and a write access is attempted, access terminates with an error response and
- * no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRB_WP2 (21U) //!< Bit position for AIPS_PACRB_WP2.
-#define BM_AIPS_PACRB_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRB_WP2.
-#define BS_AIPS_PACRB_WP2 (1U) //!< Bit field size in bits for AIPS_PACRB_WP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRB_WP2 field.
-#define BR_AIPS_PACRB_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRB_WP2.
-#define BF_AIPS_PACRB_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP2), uint32_t) & BM_AIPS_PACRB_WP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP2 field to a new value.
-#define BW_AIPS_PACRB_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRB, field SP2[22] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRB_SP2 (22U) //!< Bit position for AIPS_PACRB_SP2.
-#define BM_AIPS_PACRB_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRB_SP2.
-#define BS_AIPS_PACRB_SP2 (1U) //!< Bit field size in bits for AIPS_PACRB_SP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRB_SP2 field.
-#define BR_AIPS_PACRB_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRB_SP2.
-#define BF_AIPS_PACRB_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP2), uint32_t) & BM_AIPS_PACRB_SP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP2 field to a new value.
-#define BW_AIPS_PACRB_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRB, field TP1[24] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRB_TP1 (24U) //!< Bit position for AIPS_PACRB_TP1.
-#define BM_AIPS_PACRB_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRB_TP1.
-#define BS_AIPS_PACRB_TP1 (1U) //!< Bit field size in bits for AIPS_PACRB_TP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRB_TP1 field.
-#define BR_AIPS_PACRB_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRB_TP1.
-#define BF_AIPS_PACRB_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP1), uint32_t) & BM_AIPS_PACRB_TP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP1 field to a new value.
-#define BW_AIPS_PACRB_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRB, field WP1[25] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRB_WP1 (25U) //!< Bit position for AIPS_PACRB_WP1.
-#define BM_AIPS_PACRB_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRB_WP1.
-#define BS_AIPS_PACRB_WP1 (1U) //!< Bit field size in bits for AIPS_PACRB_WP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRB_WP1 field.
-#define BR_AIPS_PACRB_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRB_WP1.
-#define BF_AIPS_PACRB_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP1), uint32_t) & BM_AIPS_PACRB_WP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP1 field to a new value.
-#define BW_AIPS_PACRB_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRB, field SP1[26] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRB_SP1 (26U) //!< Bit position for AIPS_PACRB_SP1.
-#define BM_AIPS_PACRB_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRB_SP1.
-#define BS_AIPS_PACRB_SP1 (1U) //!< Bit field size in bits for AIPS_PACRB_SP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRB_SP1 field.
-#define BR_AIPS_PACRB_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRB_SP1.
-#define BF_AIPS_PACRB_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP1), uint32_t) & BM_AIPS_PACRB_SP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP1 field to a new value.
-#define BW_AIPS_PACRB_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRB, field TP0[28] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRB_TP0 (28U) //!< Bit position for AIPS_PACRB_TP0.
-#define BM_AIPS_PACRB_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRB_TP0.
-#define BS_AIPS_PACRB_TP0 (1U) //!< Bit field size in bits for AIPS_PACRB_TP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRB_TP0 field.
-#define BR_AIPS_PACRB_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRB_TP0.
-#define BF_AIPS_PACRB_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP0), uint32_t) & BM_AIPS_PACRB_TP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP0 field to a new value.
-#define BW_AIPS_PACRB_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRB, field WP0[29] (RW)
- *
- * Determines whether the peripheral allows write accesss. When this bit is set
- * and a write access is attempted, access terminates with an error response and
- * no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRB_WP0 (29U) //!< Bit position for AIPS_PACRB_WP0.
-#define BM_AIPS_PACRB_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRB_WP0.
-#define BS_AIPS_PACRB_WP0 (1U) //!< Bit field size in bits for AIPS_PACRB_WP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRB_WP0 field.
-#define BR_AIPS_PACRB_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRB_WP0.
-#define BF_AIPS_PACRB_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP0), uint32_t) & BM_AIPS_PACRB_WP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP0 field to a new value.
-#define BW_AIPS_PACRB_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRB, field SP0[30] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRB_SP0 (30U) //!< Bit position for AIPS_PACRB_SP0.
-#define BM_AIPS_PACRB_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRB_SP0.
-#define BS_AIPS_PACRB_SP0 (1U) //!< Bit field size in bits for AIPS_PACRB_SP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRB_SP0 field.
-#define BR_AIPS_PACRB_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRB_SP0.
-#define BF_AIPS_PACRB_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP0), uint32_t) & BM_AIPS_PACRB_SP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP0 field to a new value.
-#define BW_AIPS_PACRB_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP0) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_AIPS_PACRC - Peripheral Access Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_AIPS_PACRC - Peripheral Access Control Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
- * defines the access levels for a particular peripheral. The mapping between a
- * peripheral and its PACR field is shown in the table below. The peripheral assignment
- * to each PACR is defined by the memory map slot that the peripheral is
- * assigned to. See this chip's memory map for the assignment of a particular
- * peripheral. The following table shows the location of each peripheral slot's PACR field
- * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
- * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
- * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
- * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
- * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
- * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
- * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
- * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
- * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
- * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
- * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
- * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
- * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
- * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
- * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
- * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
- * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
- * A-D, which control peripheral slots 0-31, are shown below. The following
- * section, PACRPeripheral Access Control Register , shows the register field
- * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
- * sections because they occupy two non-contiguous address spaces.
- */
-typedef union _hw_aips_pacrc
-{
- uint32_t U;
- struct _hw_aips_pacrc_bitfields
- {
- uint32_t TP7 : 1; //!< [0] Trusted Protect
- uint32_t WP7 : 1; //!< [1] Write Protect
- uint32_t SP7 : 1; //!< [2] Supervisor Protect
- uint32_t RESERVED0 : 1; //!< [3]
- uint32_t TP6 : 1; //!< [4] Trusted Protect
- uint32_t WP6 : 1; //!< [5] Write Protect
- uint32_t SP6 : 1; //!< [6] Supervisor Protect
- uint32_t RESERVED1 : 1; //!< [7]
- uint32_t TP5 : 1; //!< [8] Trusted Protect
- uint32_t WP5 : 1; //!< [9] Write Protect
- uint32_t SP5 : 1; //!< [10] Supervisor Protect
- uint32_t RESERVED2 : 1; //!< [11]
- uint32_t TP4 : 1; //!< [12] Trusted Protect
- uint32_t WP4 : 1; //!< [13] Write Protect
- uint32_t SP4 : 1; //!< [14] Supervisor Protect
- uint32_t RESERVED3 : 1; //!< [15]
- uint32_t TP3 : 1; //!< [16] Trusted Protect
- uint32_t WP3 : 1; //!< [17] Write Protect
- uint32_t SP3 : 1; //!< [18] Supervisor Protect
- uint32_t RESERVED4 : 1; //!< [19]
- uint32_t TP2 : 1; //!< [20] Trusted Protect
- uint32_t WP2 : 1; //!< [21] Write Protect
- uint32_t SP2 : 1; //!< [22] Supervisor Protect
- uint32_t RESERVED5 : 1; //!< [23]
- uint32_t TP1 : 1; //!< [24] Trusted Protect
- uint32_t WP1 : 1; //!< [25] Write Protect
- uint32_t SP1 : 1; //!< [26] Supervisor Protect
- uint32_t RESERVED6 : 1; //!< [27]
- uint32_t TP0 : 1; //!< [28] Trusted Protect
- uint32_t WP0 : 1; //!< [29] Write Protect
- uint32_t SP0 : 1; //!< [30] Supervisor Protect
- uint32_t RESERVED7 : 1; //!< [31]
- } B;
-} hw_aips_pacrc_t;
-#endif
-
-/*!
- * @name Constants and macros for entire AIPS_PACRC register
- */
-//@{
-#define HW_AIPS_PACRC_ADDR(x) (REGS_AIPS_BASE(x) + 0x28U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_AIPS_PACRC(x) (*(__IO hw_aips_pacrc_t *) HW_AIPS_PACRC_ADDR(x))
-#define HW_AIPS_PACRC_RD(x) (HW_AIPS_PACRC(x).U)
-#define HW_AIPS_PACRC_WR(x, v) (HW_AIPS_PACRC(x).U = (v))
-#define HW_AIPS_PACRC_SET(x, v) (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) | (v)))
-#define HW_AIPS_PACRC_CLR(x, v) (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) & ~(v)))
-#define HW_AIPS_PACRC_TOG(x, v) (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual AIPS_PACRC bitfields
- */
-
-/*!
- * @name Register AIPS_PACRC, field TP7[0] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRC_TP7 (0U) //!< Bit position for AIPS_PACRC_TP7.
-#define BM_AIPS_PACRC_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRC_TP7.
-#define BS_AIPS_PACRC_TP7 (1U) //!< Bit field size in bits for AIPS_PACRC_TP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRC_TP7 field.
-#define BR_AIPS_PACRC_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRC_TP7.
-#define BF_AIPS_PACRC_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP7), uint32_t) & BM_AIPS_PACRC_TP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP7 field to a new value.
-#define BW_AIPS_PACRC_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRC, field WP7[1] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRC_WP7 (1U) //!< Bit position for AIPS_PACRC_WP7.
-#define BM_AIPS_PACRC_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRC_WP7.
-#define BS_AIPS_PACRC_WP7 (1U) //!< Bit field size in bits for AIPS_PACRC_WP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRC_WP7 field.
-#define BR_AIPS_PACRC_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRC_WP7.
-#define BF_AIPS_PACRC_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP7), uint32_t) & BM_AIPS_PACRC_WP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP7 field to a new value.
-#define BW_AIPS_PACRC_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRC, field SP7[2] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRC_SP7 (2U) //!< Bit position for AIPS_PACRC_SP7.
-#define BM_AIPS_PACRC_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRC_SP7.
-#define BS_AIPS_PACRC_SP7 (1U) //!< Bit field size in bits for AIPS_PACRC_SP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRC_SP7 field.
-#define BR_AIPS_PACRC_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRC_SP7.
-#define BF_AIPS_PACRC_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP7), uint32_t) & BM_AIPS_PACRC_SP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP7 field to a new value.
-#define BW_AIPS_PACRC_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRC, field TP6[4] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRC_TP6 (4U) //!< Bit position for AIPS_PACRC_TP6.
-#define BM_AIPS_PACRC_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRC_TP6.
-#define BS_AIPS_PACRC_TP6 (1U) //!< Bit field size in bits for AIPS_PACRC_TP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRC_TP6 field.
-#define BR_AIPS_PACRC_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRC_TP6.
-#define BF_AIPS_PACRC_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP6), uint32_t) & BM_AIPS_PACRC_TP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP6 field to a new value.
-#define BW_AIPS_PACRC_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRC, field WP6[5] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRC_WP6 (5U) //!< Bit position for AIPS_PACRC_WP6.
-#define BM_AIPS_PACRC_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRC_WP6.
-#define BS_AIPS_PACRC_WP6 (1U) //!< Bit field size in bits for AIPS_PACRC_WP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRC_WP6 field.
-#define BR_AIPS_PACRC_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRC_WP6.
-#define BF_AIPS_PACRC_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP6), uint32_t) & BM_AIPS_PACRC_WP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP6 field to a new value.
-#define BW_AIPS_PACRC_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRC, field SP6[6] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRC_SP6 (6U) //!< Bit position for AIPS_PACRC_SP6.
-#define BM_AIPS_PACRC_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRC_SP6.
-#define BS_AIPS_PACRC_SP6 (1U) //!< Bit field size in bits for AIPS_PACRC_SP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRC_SP6 field.
-#define BR_AIPS_PACRC_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRC_SP6.
-#define BF_AIPS_PACRC_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP6), uint32_t) & BM_AIPS_PACRC_SP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP6 field to a new value.
-#define BW_AIPS_PACRC_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRC, field TP5[8] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRC_TP5 (8U) //!< Bit position for AIPS_PACRC_TP5.
-#define BM_AIPS_PACRC_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRC_TP5.
-#define BS_AIPS_PACRC_TP5 (1U) //!< Bit field size in bits for AIPS_PACRC_TP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRC_TP5 field.
-#define BR_AIPS_PACRC_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRC_TP5.
-#define BF_AIPS_PACRC_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP5), uint32_t) & BM_AIPS_PACRC_TP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP5 field to a new value.
-#define BW_AIPS_PACRC_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRC, field WP5[9] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRC_WP5 (9U) //!< Bit position for AIPS_PACRC_WP5.
-#define BM_AIPS_PACRC_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRC_WP5.
-#define BS_AIPS_PACRC_WP5 (1U) //!< Bit field size in bits for AIPS_PACRC_WP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRC_WP5 field.
-#define BR_AIPS_PACRC_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRC_WP5.
-#define BF_AIPS_PACRC_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP5), uint32_t) & BM_AIPS_PACRC_WP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP5 field to a new value.
-#define BW_AIPS_PACRC_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRC, field SP5[10] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRC_SP5 (10U) //!< Bit position for AIPS_PACRC_SP5.
-#define BM_AIPS_PACRC_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRC_SP5.
-#define BS_AIPS_PACRC_SP5 (1U) //!< Bit field size in bits for AIPS_PACRC_SP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRC_SP5 field.
-#define BR_AIPS_PACRC_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRC_SP5.
-#define BF_AIPS_PACRC_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP5), uint32_t) & BM_AIPS_PACRC_SP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP5 field to a new value.
-#define BW_AIPS_PACRC_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRC, field TP4[12] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRC_TP4 (12U) //!< Bit position for AIPS_PACRC_TP4.
-#define BM_AIPS_PACRC_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRC_TP4.
-#define BS_AIPS_PACRC_TP4 (1U) //!< Bit field size in bits for AIPS_PACRC_TP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRC_TP4 field.
-#define BR_AIPS_PACRC_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRC_TP4.
-#define BF_AIPS_PACRC_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP4), uint32_t) & BM_AIPS_PACRC_TP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP4 field to a new value.
-#define BW_AIPS_PACRC_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRC, field WP4[13] (RW)
- *
- * Determines whether the peripheral allows write accesss. When this bit is set
- * and a write access is attempted, access terminates with an error response and
- * no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRC_WP4 (13U) //!< Bit position for AIPS_PACRC_WP4.
-#define BM_AIPS_PACRC_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRC_WP4.
-#define BS_AIPS_PACRC_WP4 (1U) //!< Bit field size in bits for AIPS_PACRC_WP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRC_WP4 field.
-#define BR_AIPS_PACRC_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRC_WP4.
-#define BF_AIPS_PACRC_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP4), uint32_t) & BM_AIPS_PACRC_WP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP4 field to a new value.
-#define BW_AIPS_PACRC_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRC, field SP4[14] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRC_SP4 (14U) //!< Bit position for AIPS_PACRC_SP4.
-#define BM_AIPS_PACRC_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRC_SP4.
-#define BS_AIPS_PACRC_SP4 (1U) //!< Bit field size in bits for AIPS_PACRC_SP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRC_SP4 field.
-#define BR_AIPS_PACRC_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRC_SP4.
-#define BF_AIPS_PACRC_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP4), uint32_t) & BM_AIPS_PACRC_SP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP4 field to a new value.
-#define BW_AIPS_PACRC_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRC, field TP3[16] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRC_TP3 (16U) //!< Bit position for AIPS_PACRC_TP3.
-#define BM_AIPS_PACRC_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRC_TP3.
-#define BS_AIPS_PACRC_TP3 (1U) //!< Bit field size in bits for AIPS_PACRC_TP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRC_TP3 field.
-#define BR_AIPS_PACRC_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRC_TP3.
-#define BF_AIPS_PACRC_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP3), uint32_t) & BM_AIPS_PACRC_TP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP3 field to a new value.
-#define BW_AIPS_PACRC_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRC, field WP3[17] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRC_WP3 (17U) //!< Bit position for AIPS_PACRC_WP3.
-#define BM_AIPS_PACRC_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRC_WP3.
-#define BS_AIPS_PACRC_WP3 (1U) //!< Bit field size in bits for AIPS_PACRC_WP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRC_WP3 field.
-#define BR_AIPS_PACRC_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRC_WP3.
-#define BF_AIPS_PACRC_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP3), uint32_t) & BM_AIPS_PACRC_WP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP3 field to a new value.
-#define BW_AIPS_PACRC_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRC, field SP3[18] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this bit is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
- * set. If not, access terminates with an error response and no peripheral access
- * initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRC_SP3 (18U) //!< Bit position for AIPS_PACRC_SP3.
-#define BM_AIPS_PACRC_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRC_SP3.
-#define BS_AIPS_PACRC_SP3 (1U) //!< Bit field size in bits for AIPS_PACRC_SP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRC_SP3 field.
-#define BR_AIPS_PACRC_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRC_SP3.
-#define BF_AIPS_PACRC_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP3), uint32_t) & BM_AIPS_PACRC_SP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP3 field to a new value.
-#define BW_AIPS_PACRC_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRC, field TP2[20] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRC_TP2 (20U) //!< Bit position for AIPS_PACRC_TP2.
-#define BM_AIPS_PACRC_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRC_TP2.
-#define BS_AIPS_PACRC_TP2 (1U) //!< Bit field size in bits for AIPS_PACRC_TP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRC_TP2 field.
-#define BR_AIPS_PACRC_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRC_TP2.
-#define BF_AIPS_PACRC_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP2), uint32_t) & BM_AIPS_PACRC_TP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP2 field to a new value.
-#define BW_AIPS_PACRC_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRC, field WP2[21] (RW)
- *
- * Determines whether the peripheral allows write accesss. When this bit is set
- * and a write access is attempted, access terminates with an error response and
- * no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRC_WP2 (21U) //!< Bit position for AIPS_PACRC_WP2.
-#define BM_AIPS_PACRC_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRC_WP2.
-#define BS_AIPS_PACRC_WP2 (1U) //!< Bit field size in bits for AIPS_PACRC_WP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRC_WP2 field.
-#define BR_AIPS_PACRC_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRC_WP2.
-#define BF_AIPS_PACRC_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP2), uint32_t) & BM_AIPS_PACRC_WP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP2 field to a new value.
-#define BW_AIPS_PACRC_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRC, field SP2[22] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRC_SP2 (22U) //!< Bit position for AIPS_PACRC_SP2.
-#define BM_AIPS_PACRC_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRC_SP2.
-#define BS_AIPS_PACRC_SP2 (1U) //!< Bit field size in bits for AIPS_PACRC_SP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRC_SP2 field.
-#define BR_AIPS_PACRC_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRC_SP2.
-#define BF_AIPS_PACRC_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP2), uint32_t) & BM_AIPS_PACRC_SP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP2 field to a new value.
-#define BW_AIPS_PACRC_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRC, field TP1[24] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRC_TP1 (24U) //!< Bit position for AIPS_PACRC_TP1.
-#define BM_AIPS_PACRC_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRC_TP1.
-#define BS_AIPS_PACRC_TP1 (1U) //!< Bit field size in bits for AIPS_PACRC_TP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRC_TP1 field.
-#define BR_AIPS_PACRC_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRC_TP1.
-#define BF_AIPS_PACRC_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP1), uint32_t) & BM_AIPS_PACRC_TP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP1 field to a new value.
-#define BW_AIPS_PACRC_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRC, field WP1[25] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRC_WP1 (25U) //!< Bit position for AIPS_PACRC_WP1.
-#define BM_AIPS_PACRC_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRC_WP1.
-#define BS_AIPS_PACRC_WP1 (1U) //!< Bit field size in bits for AIPS_PACRC_WP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRC_WP1 field.
-#define BR_AIPS_PACRC_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRC_WP1.
-#define BF_AIPS_PACRC_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP1), uint32_t) & BM_AIPS_PACRC_WP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP1 field to a new value.
-#define BW_AIPS_PACRC_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRC, field SP1[26] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRC_SP1 (26U) //!< Bit position for AIPS_PACRC_SP1.
-#define BM_AIPS_PACRC_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRC_SP1.
-#define BS_AIPS_PACRC_SP1 (1U) //!< Bit field size in bits for AIPS_PACRC_SP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRC_SP1 field.
-#define BR_AIPS_PACRC_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRC_SP1.
-#define BF_AIPS_PACRC_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP1), uint32_t) & BM_AIPS_PACRC_SP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP1 field to a new value.
-#define BW_AIPS_PACRC_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRC, field TP0[28] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRC_TP0 (28U) //!< Bit position for AIPS_PACRC_TP0.
-#define BM_AIPS_PACRC_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRC_TP0.
-#define BS_AIPS_PACRC_TP0 (1U) //!< Bit field size in bits for AIPS_PACRC_TP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRC_TP0 field.
-#define BR_AIPS_PACRC_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRC_TP0.
-#define BF_AIPS_PACRC_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP0), uint32_t) & BM_AIPS_PACRC_TP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP0 field to a new value.
-#define BW_AIPS_PACRC_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRC, field WP0[29] (RW)
- *
- * Determines whether the peripheral allows write accesss. When this bit is set
- * and a write access is attempted, access terminates with an error response and
- * no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRC_WP0 (29U) //!< Bit position for AIPS_PACRC_WP0.
-#define BM_AIPS_PACRC_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRC_WP0.
-#define BS_AIPS_PACRC_WP0 (1U) //!< Bit field size in bits for AIPS_PACRC_WP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRC_WP0 field.
-#define BR_AIPS_PACRC_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRC_WP0.
-#define BF_AIPS_PACRC_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP0), uint32_t) & BM_AIPS_PACRC_WP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP0 field to a new value.
-#define BW_AIPS_PACRC_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRC, field SP0[30] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRC_SP0 (30U) //!< Bit position for AIPS_PACRC_SP0.
-#define BM_AIPS_PACRC_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRC_SP0.
-#define BS_AIPS_PACRC_SP0 (1U) //!< Bit field size in bits for AIPS_PACRC_SP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRC_SP0 field.
-#define BR_AIPS_PACRC_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRC_SP0.
-#define BF_AIPS_PACRC_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP0), uint32_t) & BM_AIPS_PACRC_SP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP0 field to a new value.
-#define BW_AIPS_PACRC_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP0) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_AIPS_PACRD - Peripheral Access Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_AIPS_PACRD - Peripheral Access Control Register (RW)
- *
- * Reset value: 0x00000004U
- *
- * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
- * defines the access levels for a particular peripheral. The mapping between a
- * peripheral and its PACR field is shown in the table below. The peripheral assignment
- * to each PACR is defined by the memory map slot that the peripheral is
- * assigned to. See this chip's memory map for the assignment of a particular
- * peripheral. The following table shows the location of each peripheral slot's PACR field
- * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
- * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
- * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
- * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
- * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
- * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
- * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
- * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
- * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
- * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
- * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
- * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
- * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
- * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
- * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
- * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
- * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
- * A-D, which control peripheral slots 0-31, are shown below. The following
- * section, PACRPeripheral Access Control Register , shows the register field
- * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
- * sections because they occupy two non-contiguous address spaces.
- */
-typedef union _hw_aips_pacrd
-{
- uint32_t U;
- struct _hw_aips_pacrd_bitfields
- {
- uint32_t TP7 : 1; //!< [0] Trusted Protect
- uint32_t WP7 : 1; //!< [1] Write Protect
- uint32_t SP7 : 1; //!< [2] Supervisor Protect
- uint32_t RESERVED0 : 1; //!< [3]
- uint32_t TP6 : 1; //!< [4] Trusted Protect
- uint32_t WP6 : 1; //!< [5] Write Protect
- uint32_t SP6 : 1; //!< [6] Supervisor Protect
- uint32_t RESERVED1 : 1; //!< [7]
- uint32_t TP5 : 1; //!< [8] Trusted Protect
- uint32_t WP5 : 1; //!< [9] Write Protect
- uint32_t SP5 : 1; //!< [10] Supervisor Protect
- uint32_t RESERVED2 : 1; //!< [11]
- uint32_t TP4 : 1; //!< [12] Trusted Protect
- uint32_t WP4 : 1; //!< [13] Write Protect
- uint32_t SP4 : 1; //!< [14] Supervisor Protect
- uint32_t RESERVED3 : 1; //!< [15]
- uint32_t TP3 : 1; //!< [16] Trusted Protect
- uint32_t WP3 : 1; //!< [17] Write Protect
- uint32_t SP3 : 1; //!< [18] Supervisor Protect
- uint32_t RESERVED4 : 1; //!< [19]
- uint32_t TP2 : 1; //!< [20] Trusted Protect
- uint32_t WP2 : 1; //!< [21] Write Protect
- uint32_t SP2 : 1; //!< [22] Supervisor Protect
- uint32_t RESERVED5 : 1; //!< [23]
- uint32_t TP1 : 1; //!< [24] Trusted Protect
- uint32_t WP1 : 1; //!< [25] Write Protect
- uint32_t SP1 : 1; //!< [26] Supervisor Protect
- uint32_t RESERVED6 : 1; //!< [27]
- uint32_t TP0 : 1; //!< [28] Trusted Protect
- uint32_t WP0 : 1; //!< [29] Write Protect
- uint32_t SP0 : 1; //!< [30] Supervisor Protect
- uint32_t RESERVED7 : 1; //!< [31]
- } B;
-} hw_aips_pacrd_t;
-#endif
-
-/*!
- * @name Constants and macros for entire AIPS_PACRD register
- */
-//@{
-#define HW_AIPS_PACRD_ADDR(x) (REGS_AIPS_BASE(x) + 0x2CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_AIPS_PACRD(x) (*(__IO hw_aips_pacrd_t *) HW_AIPS_PACRD_ADDR(x))
-#define HW_AIPS_PACRD_RD(x) (HW_AIPS_PACRD(x).U)
-#define HW_AIPS_PACRD_WR(x, v) (HW_AIPS_PACRD(x).U = (v))
-#define HW_AIPS_PACRD_SET(x, v) (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) | (v)))
-#define HW_AIPS_PACRD_CLR(x, v) (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) & ~(v)))
-#define HW_AIPS_PACRD_TOG(x, v) (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual AIPS_PACRD bitfields
- */
-
-/*!
- * @name Register AIPS_PACRD, field TP7[0] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRD_TP7 (0U) //!< Bit position for AIPS_PACRD_TP7.
-#define BM_AIPS_PACRD_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRD_TP7.
-#define BS_AIPS_PACRD_TP7 (1U) //!< Bit field size in bits for AIPS_PACRD_TP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRD_TP7 field.
-#define BR_AIPS_PACRD_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRD_TP7.
-#define BF_AIPS_PACRD_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP7), uint32_t) & BM_AIPS_PACRD_TP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP7 field to a new value.
-#define BW_AIPS_PACRD_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRD, field WP7[1] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRD_WP7 (1U) //!< Bit position for AIPS_PACRD_WP7.
-#define BM_AIPS_PACRD_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRD_WP7.
-#define BS_AIPS_PACRD_WP7 (1U) //!< Bit field size in bits for AIPS_PACRD_WP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRD_WP7 field.
-#define BR_AIPS_PACRD_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRD_WP7.
-#define BF_AIPS_PACRD_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP7), uint32_t) & BM_AIPS_PACRD_WP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP7 field to a new value.
-#define BW_AIPS_PACRD_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRD, field SP7[2] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRD_SP7 (2U) //!< Bit position for AIPS_PACRD_SP7.
-#define BM_AIPS_PACRD_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRD_SP7.
-#define BS_AIPS_PACRD_SP7 (1U) //!< Bit field size in bits for AIPS_PACRD_SP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRD_SP7 field.
-#define BR_AIPS_PACRD_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRD_SP7.
-#define BF_AIPS_PACRD_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP7), uint32_t) & BM_AIPS_PACRD_SP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP7 field to a new value.
-#define BW_AIPS_PACRD_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRD, field TP6[4] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRD_TP6 (4U) //!< Bit position for AIPS_PACRD_TP6.
-#define BM_AIPS_PACRD_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRD_TP6.
-#define BS_AIPS_PACRD_TP6 (1U) //!< Bit field size in bits for AIPS_PACRD_TP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRD_TP6 field.
-#define BR_AIPS_PACRD_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRD_TP6.
-#define BF_AIPS_PACRD_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP6), uint32_t) & BM_AIPS_PACRD_TP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP6 field to a new value.
-#define BW_AIPS_PACRD_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRD, field WP6[5] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRD_WP6 (5U) //!< Bit position for AIPS_PACRD_WP6.
-#define BM_AIPS_PACRD_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRD_WP6.
-#define BS_AIPS_PACRD_WP6 (1U) //!< Bit field size in bits for AIPS_PACRD_WP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRD_WP6 field.
-#define BR_AIPS_PACRD_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRD_WP6.
-#define BF_AIPS_PACRD_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP6), uint32_t) & BM_AIPS_PACRD_WP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP6 field to a new value.
-#define BW_AIPS_PACRD_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRD, field SP6[6] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRD_SP6 (6U) //!< Bit position for AIPS_PACRD_SP6.
-#define BM_AIPS_PACRD_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRD_SP6.
-#define BS_AIPS_PACRD_SP6 (1U) //!< Bit field size in bits for AIPS_PACRD_SP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRD_SP6 field.
-#define BR_AIPS_PACRD_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRD_SP6.
-#define BF_AIPS_PACRD_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP6), uint32_t) & BM_AIPS_PACRD_SP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP6 field to a new value.
-#define BW_AIPS_PACRD_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRD, field TP5[8] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRD_TP5 (8U) //!< Bit position for AIPS_PACRD_TP5.
-#define BM_AIPS_PACRD_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRD_TP5.
-#define BS_AIPS_PACRD_TP5 (1U) //!< Bit field size in bits for AIPS_PACRD_TP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRD_TP5 field.
-#define BR_AIPS_PACRD_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRD_TP5.
-#define BF_AIPS_PACRD_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP5), uint32_t) & BM_AIPS_PACRD_TP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP5 field to a new value.
-#define BW_AIPS_PACRD_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRD, field WP5[9] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRD_WP5 (9U) //!< Bit position for AIPS_PACRD_WP5.
-#define BM_AIPS_PACRD_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRD_WP5.
-#define BS_AIPS_PACRD_WP5 (1U) //!< Bit field size in bits for AIPS_PACRD_WP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRD_WP5 field.
-#define BR_AIPS_PACRD_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRD_WP5.
-#define BF_AIPS_PACRD_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP5), uint32_t) & BM_AIPS_PACRD_WP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP5 field to a new value.
-#define BW_AIPS_PACRD_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRD, field SP5[10] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRD_SP5 (10U) //!< Bit position for AIPS_PACRD_SP5.
-#define BM_AIPS_PACRD_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRD_SP5.
-#define BS_AIPS_PACRD_SP5 (1U) //!< Bit field size in bits for AIPS_PACRD_SP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRD_SP5 field.
-#define BR_AIPS_PACRD_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRD_SP5.
-#define BF_AIPS_PACRD_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP5), uint32_t) & BM_AIPS_PACRD_SP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP5 field to a new value.
-#define BW_AIPS_PACRD_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRD, field TP4[12] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRD_TP4 (12U) //!< Bit position for AIPS_PACRD_TP4.
-#define BM_AIPS_PACRD_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRD_TP4.
-#define BS_AIPS_PACRD_TP4 (1U) //!< Bit field size in bits for AIPS_PACRD_TP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRD_TP4 field.
-#define BR_AIPS_PACRD_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRD_TP4.
-#define BF_AIPS_PACRD_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP4), uint32_t) & BM_AIPS_PACRD_TP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP4 field to a new value.
-#define BW_AIPS_PACRD_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRD, field WP4[13] (RW)
- *
- * Determines whether the peripheral allows write accesss. When this bit is set
- * and a write access is attempted, access terminates with an error response and
- * no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRD_WP4 (13U) //!< Bit position for AIPS_PACRD_WP4.
-#define BM_AIPS_PACRD_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRD_WP4.
-#define BS_AIPS_PACRD_WP4 (1U) //!< Bit field size in bits for AIPS_PACRD_WP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRD_WP4 field.
-#define BR_AIPS_PACRD_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRD_WP4.
-#define BF_AIPS_PACRD_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP4), uint32_t) & BM_AIPS_PACRD_WP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP4 field to a new value.
-#define BW_AIPS_PACRD_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRD, field SP4[14] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRD_SP4 (14U) //!< Bit position for AIPS_PACRD_SP4.
-#define BM_AIPS_PACRD_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRD_SP4.
-#define BS_AIPS_PACRD_SP4 (1U) //!< Bit field size in bits for AIPS_PACRD_SP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRD_SP4 field.
-#define BR_AIPS_PACRD_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRD_SP4.
-#define BF_AIPS_PACRD_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP4), uint32_t) & BM_AIPS_PACRD_SP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP4 field to a new value.
-#define BW_AIPS_PACRD_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRD, field TP3[16] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRD_TP3 (16U) //!< Bit position for AIPS_PACRD_TP3.
-#define BM_AIPS_PACRD_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRD_TP3.
-#define BS_AIPS_PACRD_TP3 (1U) //!< Bit field size in bits for AIPS_PACRD_TP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRD_TP3 field.
-#define BR_AIPS_PACRD_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRD_TP3.
-#define BF_AIPS_PACRD_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP3), uint32_t) & BM_AIPS_PACRD_TP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP3 field to a new value.
-#define BW_AIPS_PACRD_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRD, field WP3[17] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRD_WP3 (17U) //!< Bit position for AIPS_PACRD_WP3.
-#define BM_AIPS_PACRD_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRD_WP3.
-#define BS_AIPS_PACRD_WP3 (1U) //!< Bit field size in bits for AIPS_PACRD_WP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRD_WP3 field.
-#define BR_AIPS_PACRD_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRD_WP3.
-#define BF_AIPS_PACRD_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP3), uint32_t) & BM_AIPS_PACRD_WP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP3 field to a new value.
-#define BW_AIPS_PACRD_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRD, field SP3[18] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this bit is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
- * set. If not, access terminates with an error response and no peripheral access
- * initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRD_SP3 (18U) //!< Bit position for AIPS_PACRD_SP3.
-#define BM_AIPS_PACRD_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRD_SP3.
-#define BS_AIPS_PACRD_SP3 (1U) //!< Bit field size in bits for AIPS_PACRD_SP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRD_SP3 field.
-#define BR_AIPS_PACRD_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRD_SP3.
-#define BF_AIPS_PACRD_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP3), uint32_t) & BM_AIPS_PACRD_SP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP3 field to a new value.
-#define BW_AIPS_PACRD_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRD, field TP2[20] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRD_TP2 (20U) //!< Bit position for AIPS_PACRD_TP2.
-#define BM_AIPS_PACRD_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRD_TP2.
-#define BS_AIPS_PACRD_TP2 (1U) //!< Bit field size in bits for AIPS_PACRD_TP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRD_TP2 field.
-#define BR_AIPS_PACRD_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRD_TP2.
-#define BF_AIPS_PACRD_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP2), uint32_t) & BM_AIPS_PACRD_TP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP2 field to a new value.
-#define BW_AIPS_PACRD_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRD, field WP2[21] (RW)
- *
- * Determines whether the peripheral allows write accesss. When this bit is set
- * and a write access is attempted, access terminates with an error response and
- * no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRD_WP2 (21U) //!< Bit position for AIPS_PACRD_WP2.
-#define BM_AIPS_PACRD_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRD_WP2.
-#define BS_AIPS_PACRD_WP2 (1U) //!< Bit field size in bits for AIPS_PACRD_WP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRD_WP2 field.
-#define BR_AIPS_PACRD_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRD_WP2.
-#define BF_AIPS_PACRD_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP2), uint32_t) & BM_AIPS_PACRD_WP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP2 field to a new value.
-#define BW_AIPS_PACRD_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRD, field SP2[22] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRD_SP2 (22U) //!< Bit position for AIPS_PACRD_SP2.
-#define BM_AIPS_PACRD_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRD_SP2.
-#define BS_AIPS_PACRD_SP2 (1U) //!< Bit field size in bits for AIPS_PACRD_SP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRD_SP2 field.
-#define BR_AIPS_PACRD_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRD_SP2.
-#define BF_AIPS_PACRD_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP2), uint32_t) & BM_AIPS_PACRD_SP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP2 field to a new value.
-#define BW_AIPS_PACRD_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRD, field TP1[24] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRD_TP1 (24U) //!< Bit position for AIPS_PACRD_TP1.
-#define BM_AIPS_PACRD_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRD_TP1.
-#define BS_AIPS_PACRD_TP1 (1U) //!< Bit field size in bits for AIPS_PACRD_TP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRD_TP1 field.
-#define BR_AIPS_PACRD_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRD_TP1.
-#define BF_AIPS_PACRD_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP1), uint32_t) & BM_AIPS_PACRD_TP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP1 field to a new value.
-#define BW_AIPS_PACRD_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRD, field WP1[25] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRD_WP1 (25U) //!< Bit position for AIPS_PACRD_WP1.
-#define BM_AIPS_PACRD_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRD_WP1.
-#define BS_AIPS_PACRD_WP1 (1U) //!< Bit field size in bits for AIPS_PACRD_WP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRD_WP1 field.
-#define BR_AIPS_PACRD_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRD_WP1.
-#define BF_AIPS_PACRD_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP1), uint32_t) & BM_AIPS_PACRD_WP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP1 field to a new value.
-#define BW_AIPS_PACRD_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRD, field SP1[26] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRD_SP1 (26U) //!< Bit position for AIPS_PACRD_SP1.
-#define BM_AIPS_PACRD_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRD_SP1.
-#define BS_AIPS_PACRD_SP1 (1U) //!< Bit field size in bits for AIPS_PACRD_SP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRD_SP1 field.
-#define BR_AIPS_PACRD_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRD_SP1.
-#define BF_AIPS_PACRD_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP1), uint32_t) & BM_AIPS_PACRD_SP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP1 field to a new value.
-#define BW_AIPS_PACRD_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRD, field TP0[28] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRD_TP0 (28U) //!< Bit position for AIPS_PACRD_TP0.
-#define BM_AIPS_PACRD_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRD_TP0.
-#define BS_AIPS_PACRD_TP0 (1U) //!< Bit field size in bits for AIPS_PACRD_TP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRD_TP0 field.
-#define BR_AIPS_PACRD_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRD_TP0.
-#define BF_AIPS_PACRD_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP0), uint32_t) & BM_AIPS_PACRD_TP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP0 field to a new value.
-#define BW_AIPS_PACRD_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRD, field WP0[29] (RW)
- *
- * Determines whether the peripheral allows write accesss. When this bit is set
- * and a write access is attempted, access terminates with an error response and
- * no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRD_WP0 (29U) //!< Bit position for AIPS_PACRD_WP0.
-#define BM_AIPS_PACRD_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRD_WP0.
-#define BS_AIPS_PACRD_WP0 (1U) //!< Bit field size in bits for AIPS_PACRD_WP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRD_WP0 field.
-#define BR_AIPS_PACRD_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRD_WP0.
-#define BF_AIPS_PACRD_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP0), uint32_t) & BM_AIPS_PACRD_WP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP0 field to a new value.
-#define BW_AIPS_PACRD_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRD, field SP0[30] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRD_SP0 (30U) //!< Bit position for AIPS_PACRD_SP0.
-#define BM_AIPS_PACRD_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRD_SP0.
-#define BS_AIPS_PACRD_SP0 (1U) //!< Bit field size in bits for AIPS_PACRD_SP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRD_SP0 field.
-#define BR_AIPS_PACRD_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRD_SP0.
-#define BF_AIPS_PACRD_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP0), uint32_t) & BM_AIPS_PACRD_SP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP0 field to a new value.
-#define BW_AIPS_PACRD_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP0) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_AIPS_PACRE - Peripheral Access Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_AIPS_PACRE - Peripheral Access Control Register (RW)
- *
- * Reset value: 0x44444444U
- *
- * This section describes PACR registers E-P, which control peripheral slots
- * 32-127. See PACRPeripheral Access Control Register for the description of these
- * registers.
- */
-typedef union _hw_aips_pacre
-{
- uint32_t U;
- struct _hw_aips_pacre_bitfields
- {
- uint32_t TP7 : 1; //!< [0] Trusted Protect
- uint32_t WP7 : 1; //!< [1] Write Protect
- uint32_t SP7 : 1; //!< [2] Supervisor Protect
- uint32_t RESERVED0 : 1; //!< [3]
- uint32_t TP6 : 1; //!< [4] Trusted Protect
- uint32_t WP6 : 1; //!< [5] Write Protect
- uint32_t SP6 : 1; //!< [6] Supervisor Protect
- uint32_t RESERVED1 : 1; //!< [7]
- uint32_t TP5 : 1; //!< [8] Trusted Protect
- uint32_t WP5 : 1; //!< [9] Write Protect
- uint32_t SP5 : 1; //!< [10] Supervisor Protect
- uint32_t RESERVED2 : 1; //!< [11]
- uint32_t TP4 : 1; //!< [12] Trusted Protect
- uint32_t WP4 : 1; //!< [13] Write Protect
- uint32_t SP4 : 1; //!< [14] Supervisor Protect
- uint32_t RESERVED3 : 1; //!< [15]
- uint32_t TP3 : 1; //!< [16] Trusted Protect
- uint32_t WP3 : 1; //!< [17] Write Protect
- uint32_t SP3 : 1; //!< [18] Supervisor Protect
- uint32_t RESERVED4 : 1; //!< [19]
- uint32_t TP2 : 1; //!< [20] Trusted Protect
- uint32_t WP2 : 1; //!< [21] Write Protect
- uint32_t SP2 : 1; //!< [22] Supervisor Protect
- uint32_t RESERVED5 : 1; //!< [23]
- uint32_t TP1 : 1; //!< [24] Trusted Protect
- uint32_t WP1 : 1; //!< [25] Write Protect
- uint32_t SP1 : 1; //!< [26] Supervisor Protect
- uint32_t RESERVED6 : 1; //!< [27]
- uint32_t TP0 : 1; //!< [28] Trusted Protect
- uint32_t WP0 : 1; //!< [29] Write Protect
- uint32_t SP0 : 1; //!< [30] Supervisor Protect
- uint32_t RESERVED7 : 1; //!< [31]
- } B;
-} hw_aips_pacre_t;
-#endif
-
-/*!
- * @name Constants and macros for entire AIPS_PACRE register
- */
-//@{
-#define HW_AIPS_PACRE_ADDR(x) (REGS_AIPS_BASE(x) + 0x40U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_AIPS_PACRE(x) (*(__IO hw_aips_pacre_t *) HW_AIPS_PACRE_ADDR(x))
-#define HW_AIPS_PACRE_RD(x) (HW_AIPS_PACRE(x).U)
-#define HW_AIPS_PACRE_WR(x, v) (HW_AIPS_PACRE(x).U = (v))
-#define HW_AIPS_PACRE_SET(x, v) (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) | (v)))
-#define HW_AIPS_PACRE_CLR(x, v) (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) & ~(v)))
-#define HW_AIPS_PACRE_TOG(x, v) (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual AIPS_PACRE bitfields
- */
-
-/*!
- * @name Register AIPS_PACRE, field TP7[0] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRE_TP7 (0U) //!< Bit position for AIPS_PACRE_TP7.
-#define BM_AIPS_PACRE_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRE_TP7.
-#define BS_AIPS_PACRE_TP7 (1U) //!< Bit field size in bits for AIPS_PACRE_TP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRE_TP7 field.
-#define BR_AIPS_PACRE_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRE_TP7.
-#define BF_AIPS_PACRE_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP7), uint32_t) & BM_AIPS_PACRE_TP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP7 field to a new value.
-#define BW_AIPS_PACRE_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRE, field WP7[1] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRE_WP7 (1U) //!< Bit position for AIPS_PACRE_WP7.
-#define BM_AIPS_PACRE_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRE_WP7.
-#define BS_AIPS_PACRE_WP7 (1U) //!< Bit field size in bits for AIPS_PACRE_WP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRE_WP7 field.
-#define BR_AIPS_PACRE_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRE_WP7.
-#define BF_AIPS_PACRE_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP7), uint32_t) & BM_AIPS_PACRE_WP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP7 field to a new value.
-#define BW_AIPS_PACRE_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRE, field SP7[2] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRE_SP7 (2U) //!< Bit position for AIPS_PACRE_SP7.
-#define BM_AIPS_PACRE_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRE_SP7.
-#define BS_AIPS_PACRE_SP7 (1U) //!< Bit field size in bits for AIPS_PACRE_SP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRE_SP7 field.
-#define BR_AIPS_PACRE_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRE_SP7.
-#define BF_AIPS_PACRE_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP7), uint32_t) & BM_AIPS_PACRE_SP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP7 field to a new value.
-#define BW_AIPS_PACRE_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRE, field TP6[4] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRE_TP6 (4U) //!< Bit position for AIPS_PACRE_TP6.
-#define BM_AIPS_PACRE_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRE_TP6.
-#define BS_AIPS_PACRE_TP6 (1U) //!< Bit field size in bits for AIPS_PACRE_TP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRE_TP6 field.
-#define BR_AIPS_PACRE_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRE_TP6.
-#define BF_AIPS_PACRE_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP6), uint32_t) & BM_AIPS_PACRE_TP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP6 field to a new value.
-#define BW_AIPS_PACRE_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRE, field WP6[5] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRE_WP6 (5U) //!< Bit position for AIPS_PACRE_WP6.
-#define BM_AIPS_PACRE_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRE_WP6.
-#define BS_AIPS_PACRE_WP6 (1U) //!< Bit field size in bits for AIPS_PACRE_WP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRE_WP6 field.
-#define BR_AIPS_PACRE_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRE_WP6.
-#define BF_AIPS_PACRE_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP6), uint32_t) & BM_AIPS_PACRE_WP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP6 field to a new value.
-#define BW_AIPS_PACRE_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRE, field SP6[6] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRE_SP6 (6U) //!< Bit position for AIPS_PACRE_SP6.
-#define BM_AIPS_PACRE_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRE_SP6.
-#define BS_AIPS_PACRE_SP6 (1U) //!< Bit field size in bits for AIPS_PACRE_SP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRE_SP6 field.
-#define BR_AIPS_PACRE_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRE_SP6.
-#define BF_AIPS_PACRE_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP6), uint32_t) & BM_AIPS_PACRE_SP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP6 field to a new value.
-#define BW_AIPS_PACRE_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRE, field TP5[8] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRE_TP5 (8U) //!< Bit position for AIPS_PACRE_TP5.
-#define BM_AIPS_PACRE_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRE_TP5.
-#define BS_AIPS_PACRE_TP5 (1U) //!< Bit field size in bits for AIPS_PACRE_TP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRE_TP5 field.
-#define BR_AIPS_PACRE_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRE_TP5.
-#define BF_AIPS_PACRE_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP5), uint32_t) & BM_AIPS_PACRE_TP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP5 field to a new value.
-#define BW_AIPS_PACRE_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRE, field WP5[9] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRE_WP5 (9U) //!< Bit position for AIPS_PACRE_WP5.
-#define BM_AIPS_PACRE_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRE_WP5.
-#define BS_AIPS_PACRE_WP5 (1U) //!< Bit field size in bits for AIPS_PACRE_WP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRE_WP5 field.
-#define BR_AIPS_PACRE_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRE_WP5.
-#define BF_AIPS_PACRE_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP5), uint32_t) & BM_AIPS_PACRE_WP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP5 field to a new value.
-#define BW_AIPS_PACRE_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRE, field SP5[10] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRE_SP5 (10U) //!< Bit position for AIPS_PACRE_SP5.
-#define BM_AIPS_PACRE_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRE_SP5.
-#define BS_AIPS_PACRE_SP5 (1U) //!< Bit field size in bits for AIPS_PACRE_SP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRE_SP5 field.
-#define BR_AIPS_PACRE_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRE_SP5.
-#define BF_AIPS_PACRE_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP5), uint32_t) & BM_AIPS_PACRE_SP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP5 field to a new value.
-#define BW_AIPS_PACRE_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRE, field TP4[12] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRE_TP4 (12U) //!< Bit position for AIPS_PACRE_TP4.
-#define BM_AIPS_PACRE_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRE_TP4.
-#define BS_AIPS_PACRE_TP4 (1U) //!< Bit field size in bits for AIPS_PACRE_TP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRE_TP4 field.
-#define BR_AIPS_PACRE_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRE_TP4.
-#define BF_AIPS_PACRE_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP4), uint32_t) & BM_AIPS_PACRE_TP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP4 field to a new value.
-#define BW_AIPS_PACRE_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRE, field WP4[13] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRE_WP4 (13U) //!< Bit position for AIPS_PACRE_WP4.
-#define BM_AIPS_PACRE_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRE_WP4.
-#define BS_AIPS_PACRE_WP4 (1U) //!< Bit field size in bits for AIPS_PACRE_WP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRE_WP4 field.
-#define BR_AIPS_PACRE_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRE_WP4.
-#define BF_AIPS_PACRE_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP4), uint32_t) & BM_AIPS_PACRE_WP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP4 field to a new value.
-#define BW_AIPS_PACRE_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRE, field SP4[14] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this bit is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
- * set. If not, access terminates with an error response and no peripheral access
- * initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRE_SP4 (14U) //!< Bit position for AIPS_PACRE_SP4.
-#define BM_AIPS_PACRE_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRE_SP4.
-#define BS_AIPS_PACRE_SP4 (1U) //!< Bit field size in bits for AIPS_PACRE_SP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRE_SP4 field.
-#define BR_AIPS_PACRE_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRE_SP4.
-#define BF_AIPS_PACRE_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP4), uint32_t) & BM_AIPS_PACRE_SP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP4 field to a new value.
-#define BW_AIPS_PACRE_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRE, field TP3[16] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRE_TP3 (16U) //!< Bit position for AIPS_PACRE_TP3.
-#define BM_AIPS_PACRE_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRE_TP3.
-#define BS_AIPS_PACRE_TP3 (1U) //!< Bit field size in bits for AIPS_PACRE_TP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRE_TP3 field.
-#define BR_AIPS_PACRE_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRE_TP3.
-#define BF_AIPS_PACRE_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP3), uint32_t) & BM_AIPS_PACRE_TP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP3 field to a new value.
-#define BW_AIPS_PACRE_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRE, field WP3[17] (RW)
- *
- * Determines whether the peripheral allows write accesss. When this bit is set
- * and a write access is attempted, access terminates with an error response and
- * no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRE_WP3 (17U) //!< Bit position for AIPS_PACRE_WP3.
-#define BM_AIPS_PACRE_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRE_WP3.
-#define BS_AIPS_PACRE_WP3 (1U) //!< Bit field size in bits for AIPS_PACRE_WP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRE_WP3 field.
-#define BR_AIPS_PACRE_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRE_WP3.
-#define BF_AIPS_PACRE_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP3), uint32_t) & BM_AIPS_PACRE_WP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP3 field to a new value.
-#define BW_AIPS_PACRE_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRE, field SP3[18] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRE_SP3 (18U) //!< Bit position for AIPS_PACRE_SP3.
-#define BM_AIPS_PACRE_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRE_SP3.
-#define BS_AIPS_PACRE_SP3 (1U) //!< Bit field size in bits for AIPS_PACRE_SP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRE_SP3 field.
-#define BR_AIPS_PACRE_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRE_SP3.
-#define BF_AIPS_PACRE_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP3), uint32_t) & BM_AIPS_PACRE_SP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP3 field to a new value.
-#define BW_AIPS_PACRE_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRE, field TP2[20] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRE_TP2 (20U) //!< Bit position for AIPS_PACRE_TP2.
-#define BM_AIPS_PACRE_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRE_TP2.
-#define BS_AIPS_PACRE_TP2 (1U) //!< Bit field size in bits for AIPS_PACRE_TP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRE_TP2 field.
-#define BR_AIPS_PACRE_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRE_TP2.
-#define BF_AIPS_PACRE_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP2), uint32_t) & BM_AIPS_PACRE_TP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP2 field to a new value.
-#define BW_AIPS_PACRE_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRE, field WP2[21] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRE_WP2 (21U) //!< Bit position for AIPS_PACRE_WP2.
-#define BM_AIPS_PACRE_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRE_WP2.
-#define BS_AIPS_PACRE_WP2 (1U) //!< Bit field size in bits for AIPS_PACRE_WP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRE_WP2 field.
-#define BR_AIPS_PACRE_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRE_WP2.
-#define BF_AIPS_PACRE_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP2), uint32_t) & BM_AIPS_PACRE_WP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP2 field to a new value.
-#define BW_AIPS_PACRE_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRE, field SP2[22] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this bit is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
- * set. If not, access terminates with an error response and no peripheral access
- * initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRE_SP2 (22U) //!< Bit position for AIPS_PACRE_SP2.
-#define BM_AIPS_PACRE_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRE_SP2.
-#define BS_AIPS_PACRE_SP2 (1U) //!< Bit field size in bits for AIPS_PACRE_SP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRE_SP2 field.
-#define BR_AIPS_PACRE_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRE_SP2.
-#define BF_AIPS_PACRE_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP2), uint32_t) & BM_AIPS_PACRE_SP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP2 field to a new value.
-#define BW_AIPS_PACRE_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRE, field TP1[24] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRE_TP1 (24U) //!< Bit position for AIPS_PACRE_TP1.
-#define BM_AIPS_PACRE_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRE_TP1.
-#define BS_AIPS_PACRE_TP1 (1U) //!< Bit field size in bits for AIPS_PACRE_TP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRE_TP1 field.
-#define BR_AIPS_PACRE_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRE_TP1.
-#define BF_AIPS_PACRE_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP1), uint32_t) & BM_AIPS_PACRE_TP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP1 field to a new value.
-#define BW_AIPS_PACRE_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRE, field WP1[25] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRE_WP1 (25U) //!< Bit position for AIPS_PACRE_WP1.
-#define BM_AIPS_PACRE_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRE_WP1.
-#define BS_AIPS_PACRE_WP1 (1U) //!< Bit field size in bits for AIPS_PACRE_WP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRE_WP1 field.
-#define BR_AIPS_PACRE_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRE_WP1.
-#define BF_AIPS_PACRE_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP1), uint32_t) & BM_AIPS_PACRE_WP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP1 field to a new value.
-#define BW_AIPS_PACRE_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRE, field SP1[26] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master must
- * be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRE_SP1 (26U) //!< Bit position for AIPS_PACRE_SP1.
-#define BM_AIPS_PACRE_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRE_SP1.
-#define BS_AIPS_PACRE_SP1 (1U) //!< Bit field size in bits for AIPS_PACRE_SP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRE_SP1 field.
-#define BR_AIPS_PACRE_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRE_SP1.
-#define BF_AIPS_PACRE_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP1), uint32_t) & BM_AIPS_PACRE_SP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP1 field to a new value.
-#define BW_AIPS_PACRE_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRE, field TP0[28] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRE_TP0 (28U) //!< Bit position for AIPS_PACRE_TP0.
-#define BM_AIPS_PACRE_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRE_TP0.
-#define BS_AIPS_PACRE_TP0 (1U) //!< Bit field size in bits for AIPS_PACRE_TP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRE_TP0 field.
-#define BR_AIPS_PACRE_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRE_TP0.
-#define BF_AIPS_PACRE_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP0), uint32_t) & BM_AIPS_PACRE_TP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP0 field to a new value.
-#define BW_AIPS_PACRE_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRE, field WP0[29] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRE_WP0 (29U) //!< Bit position for AIPS_PACRE_WP0.
-#define BM_AIPS_PACRE_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRE_WP0.
-#define BS_AIPS_PACRE_WP0 (1U) //!< Bit field size in bits for AIPS_PACRE_WP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRE_WP0 field.
-#define BR_AIPS_PACRE_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRE_WP0.
-#define BF_AIPS_PACRE_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP0), uint32_t) & BM_AIPS_PACRE_WP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP0 field to a new value.
-#define BW_AIPS_PACRE_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRE, field SP0[30] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRE_SP0 (30U) //!< Bit position for AIPS_PACRE_SP0.
-#define BM_AIPS_PACRE_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRE_SP0.
-#define BS_AIPS_PACRE_SP0 (1U) //!< Bit field size in bits for AIPS_PACRE_SP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRE_SP0 field.
-#define BR_AIPS_PACRE_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRE_SP0.
-#define BF_AIPS_PACRE_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP0), uint32_t) & BM_AIPS_PACRE_SP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP0 field to a new value.
-#define BW_AIPS_PACRE_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP0) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_AIPS_PACRF - Peripheral Access Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_AIPS_PACRF - Peripheral Access Control Register (RW)
- *
- * Reset value: 0x44444444U
- *
- * This section describes PACR registers E-P, which control peripheral slots
- * 32-127. See PACRPeripheral Access Control Register for the description of these
- * registers.
- */
-typedef union _hw_aips_pacrf
-{
- uint32_t U;
- struct _hw_aips_pacrf_bitfields
- {
- uint32_t TP7 : 1; //!< [0] Trusted Protect
- uint32_t WP7 : 1; //!< [1] Write Protect
- uint32_t SP7 : 1; //!< [2] Supervisor Protect
- uint32_t RESERVED0 : 1; //!< [3]
- uint32_t TP6 : 1; //!< [4] Trusted Protect
- uint32_t WP6 : 1; //!< [5] Write Protect
- uint32_t SP6 : 1; //!< [6] Supervisor Protect
- uint32_t RESERVED1 : 1; //!< [7]
- uint32_t TP5 : 1; //!< [8] Trusted Protect
- uint32_t WP5 : 1; //!< [9] Write Protect
- uint32_t SP5 : 1; //!< [10] Supervisor Protect
- uint32_t RESERVED2 : 1; //!< [11]
- uint32_t TP4 : 1; //!< [12] Trusted Protect
- uint32_t WP4 : 1; //!< [13] Write Protect
- uint32_t SP4 : 1; //!< [14] Supervisor Protect
- uint32_t RESERVED3 : 1; //!< [15]
- uint32_t TP3 : 1; //!< [16] Trusted Protect
- uint32_t WP3 : 1; //!< [17] Write Protect
- uint32_t SP3 : 1; //!< [18] Supervisor Protect
- uint32_t RESERVED4 : 1; //!< [19]
- uint32_t TP2 : 1; //!< [20] Trusted Protect
- uint32_t WP2 : 1; //!< [21] Write Protect
- uint32_t SP2 : 1; //!< [22] Supervisor Protect
- uint32_t RESERVED5 : 1; //!< [23]
- uint32_t TP1 : 1; //!< [24] Trusted Protect
- uint32_t WP1 : 1; //!< [25] Write Protect
- uint32_t SP1 : 1; //!< [26] Supervisor Protect
- uint32_t RESERVED6 : 1; //!< [27]
- uint32_t TP0 : 1; //!< [28] Trusted Protect
- uint32_t WP0 : 1; //!< [29] Write Protect
- uint32_t SP0 : 1; //!< [30] Supervisor Protect
- uint32_t RESERVED7 : 1; //!< [31]
- } B;
-} hw_aips_pacrf_t;
-#endif
-
-/*!
- * @name Constants and macros for entire AIPS_PACRF register
- */
-//@{
-#define HW_AIPS_PACRF_ADDR(x) (REGS_AIPS_BASE(x) + 0x44U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_AIPS_PACRF(x) (*(__IO hw_aips_pacrf_t *) HW_AIPS_PACRF_ADDR(x))
-#define HW_AIPS_PACRF_RD(x) (HW_AIPS_PACRF(x).U)
-#define HW_AIPS_PACRF_WR(x, v) (HW_AIPS_PACRF(x).U = (v))
-#define HW_AIPS_PACRF_SET(x, v) (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) | (v)))
-#define HW_AIPS_PACRF_CLR(x, v) (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) & ~(v)))
-#define HW_AIPS_PACRF_TOG(x, v) (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual AIPS_PACRF bitfields
- */
-
-/*!
- * @name Register AIPS_PACRF, field TP7[0] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRF_TP7 (0U) //!< Bit position for AIPS_PACRF_TP7.
-#define BM_AIPS_PACRF_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRF_TP7.
-#define BS_AIPS_PACRF_TP7 (1U) //!< Bit field size in bits for AIPS_PACRF_TP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRF_TP7 field.
-#define BR_AIPS_PACRF_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRF_TP7.
-#define BF_AIPS_PACRF_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP7), uint32_t) & BM_AIPS_PACRF_TP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP7 field to a new value.
-#define BW_AIPS_PACRF_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRF, field WP7[1] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRF_WP7 (1U) //!< Bit position for AIPS_PACRF_WP7.
-#define BM_AIPS_PACRF_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRF_WP7.
-#define BS_AIPS_PACRF_WP7 (1U) //!< Bit field size in bits for AIPS_PACRF_WP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRF_WP7 field.
-#define BR_AIPS_PACRF_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRF_WP7.
-#define BF_AIPS_PACRF_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP7), uint32_t) & BM_AIPS_PACRF_WP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP7 field to a new value.
-#define BW_AIPS_PACRF_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRF, field SP7[2] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRF_SP7 (2U) //!< Bit position for AIPS_PACRF_SP7.
-#define BM_AIPS_PACRF_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRF_SP7.
-#define BS_AIPS_PACRF_SP7 (1U) //!< Bit field size in bits for AIPS_PACRF_SP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRF_SP7 field.
-#define BR_AIPS_PACRF_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRF_SP7.
-#define BF_AIPS_PACRF_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP7), uint32_t) & BM_AIPS_PACRF_SP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP7 field to a new value.
-#define BW_AIPS_PACRF_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRF, field TP6[4] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRF_TP6 (4U) //!< Bit position for AIPS_PACRF_TP6.
-#define BM_AIPS_PACRF_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRF_TP6.
-#define BS_AIPS_PACRF_TP6 (1U) //!< Bit field size in bits for AIPS_PACRF_TP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRF_TP6 field.
-#define BR_AIPS_PACRF_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRF_TP6.
-#define BF_AIPS_PACRF_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP6), uint32_t) & BM_AIPS_PACRF_TP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP6 field to a new value.
-#define BW_AIPS_PACRF_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRF, field WP6[5] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRF_WP6 (5U) //!< Bit position for AIPS_PACRF_WP6.
-#define BM_AIPS_PACRF_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRF_WP6.
-#define BS_AIPS_PACRF_WP6 (1U) //!< Bit field size in bits for AIPS_PACRF_WP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRF_WP6 field.
-#define BR_AIPS_PACRF_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRF_WP6.
-#define BF_AIPS_PACRF_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP6), uint32_t) & BM_AIPS_PACRF_WP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP6 field to a new value.
-#define BW_AIPS_PACRF_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRF, field SP6[6] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRF_SP6 (6U) //!< Bit position for AIPS_PACRF_SP6.
-#define BM_AIPS_PACRF_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRF_SP6.
-#define BS_AIPS_PACRF_SP6 (1U) //!< Bit field size in bits for AIPS_PACRF_SP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRF_SP6 field.
-#define BR_AIPS_PACRF_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRF_SP6.
-#define BF_AIPS_PACRF_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP6), uint32_t) & BM_AIPS_PACRF_SP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP6 field to a new value.
-#define BW_AIPS_PACRF_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRF, field TP5[8] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRF_TP5 (8U) //!< Bit position for AIPS_PACRF_TP5.
-#define BM_AIPS_PACRF_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRF_TP5.
-#define BS_AIPS_PACRF_TP5 (1U) //!< Bit field size in bits for AIPS_PACRF_TP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRF_TP5 field.
-#define BR_AIPS_PACRF_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRF_TP5.
-#define BF_AIPS_PACRF_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP5), uint32_t) & BM_AIPS_PACRF_TP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP5 field to a new value.
-#define BW_AIPS_PACRF_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRF, field WP5[9] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRF_WP5 (9U) //!< Bit position for AIPS_PACRF_WP5.
-#define BM_AIPS_PACRF_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRF_WP5.
-#define BS_AIPS_PACRF_WP5 (1U) //!< Bit field size in bits for AIPS_PACRF_WP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRF_WP5 field.
-#define BR_AIPS_PACRF_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRF_WP5.
-#define BF_AIPS_PACRF_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP5), uint32_t) & BM_AIPS_PACRF_WP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP5 field to a new value.
-#define BW_AIPS_PACRF_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRF, field SP5[10] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRF_SP5 (10U) //!< Bit position for AIPS_PACRF_SP5.
-#define BM_AIPS_PACRF_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRF_SP5.
-#define BS_AIPS_PACRF_SP5 (1U) //!< Bit field size in bits for AIPS_PACRF_SP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRF_SP5 field.
-#define BR_AIPS_PACRF_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRF_SP5.
-#define BF_AIPS_PACRF_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP5), uint32_t) & BM_AIPS_PACRF_SP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP5 field to a new value.
-#define BW_AIPS_PACRF_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRF, field TP4[12] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRF_TP4 (12U) //!< Bit position for AIPS_PACRF_TP4.
-#define BM_AIPS_PACRF_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRF_TP4.
-#define BS_AIPS_PACRF_TP4 (1U) //!< Bit field size in bits for AIPS_PACRF_TP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRF_TP4 field.
-#define BR_AIPS_PACRF_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRF_TP4.
-#define BF_AIPS_PACRF_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP4), uint32_t) & BM_AIPS_PACRF_TP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP4 field to a new value.
-#define BW_AIPS_PACRF_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRF, field WP4[13] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRF_WP4 (13U) //!< Bit position for AIPS_PACRF_WP4.
-#define BM_AIPS_PACRF_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRF_WP4.
-#define BS_AIPS_PACRF_WP4 (1U) //!< Bit field size in bits for AIPS_PACRF_WP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRF_WP4 field.
-#define BR_AIPS_PACRF_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRF_WP4.
-#define BF_AIPS_PACRF_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP4), uint32_t) & BM_AIPS_PACRF_WP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP4 field to a new value.
-#define BW_AIPS_PACRF_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRF, field SP4[14] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this bit is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
- * set. If not, access terminates with an error response and no peripheral access
- * initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRF_SP4 (14U) //!< Bit position for AIPS_PACRF_SP4.
-#define BM_AIPS_PACRF_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRF_SP4.
-#define BS_AIPS_PACRF_SP4 (1U) //!< Bit field size in bits for AIPS_PACRF_SP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRF_SP4 field.
-#define BR_AIPS_PACRF_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRF_SP4.
-#define BF_AIPS_PACRF_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP4), uint32_t) & BM_AIPS_PACRF_SP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP4 field to a new value.
-#define BW_AIPS_PACRF_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRF, field TP3[16] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRF_TP3 (16U) //!< Bit position for AIPS_PACRF_TP3.
-#define BM_AIPS_PACRF_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRF_TP3.
-#define BS_AIPS_PACRF_TP3 (1U) //!< Bit field size in bits for AIPS_PACRF_TP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRF_TP3 field.
-#define BR_AIPS_PACRF_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRF_TP3.
-#define BF_AIPS_PACRF_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP3), uint32_t) & BM_AIPS_PACRF_TP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP3 field to a new value.
-#define BW_AIPS_PACRF_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRF, field WP3[17] (RW)
- *
- * Determines whether the peripheral allows write accesss. When this bit is set
- * and a write access is attempted, access terminates with an error response and
- * no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRF_WP3 (17U) //!< Bit position for AIPS_PACRF_WP3.
-#define BM_AIPS_PACRF_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRF_WP3.
-#define BS_AIPS_PACRF_WP3 (1U) //!< Bit field size in bits for AIPS_PACRF_WP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRF_WP3 field.
-#define BR_AIPS_PACRF_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRF_WP3.
-#define BF_AIPS_PACRF_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP3), uint32_t) & BM_AIPS_PACRF_WP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP3 field to a new value.
-#define BW_AIPS_PACRF_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRF, field SP3[18] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRF_SP3 (18U) //!< Bit position for AIPS_PACRF_SP3.
-#define BM_AIPS_PACRF_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRF_SP3.
-#define BS_AIPS_PACRF_SP3 (1U) //!< Bit field size in bits for AIPS_PACRF_SP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRF_SP3 field.
-#define BR_AIPS_PACRF_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRF_SP3.
-#define BF_AIPS_PACRF_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP3), uint32_t) & BM_AIPS_PACRF_SP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP3 field to a new value.
-#define BW_AIPS_PACRF_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRF, field TP2[20] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRF_TP2 (20U) //!< Bit position for AIPS_PACRF_TP2.
-#define BM_AIPS_PACRF_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRF_TP2.
-#define BS_AIPS_PACRF_TP2 (1U) //!< Bit field size in bits for AIPS_PACRF_TP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRF_TP2 field.
-#define BR_AIPS_PACRF_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRF_TP2.
-#define BF_AIPS_PACRF_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP2), uint32_t) & BM_AIPS_PACRF_TP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP2 field to a new value.
-#define BW_AIPS_PACRF_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRF, field WP2[21] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRF_WP2 (21U) //!< Bit position for AIPS_PACRF_WP2.
-#define BM_AIPS_PACRF_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRF_WP2.
-#define BS_AIPS_PACRF_WP2 (1U) //!< Bit field size in bits for AIPS_PACRF_WP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRF_WP2 field.
-#define BR_AIPS_PACRF_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRF_WP2.
-#define BF_AIPS_PACRF_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP2), uint32_t) & BM_AIPS_PACRF_WP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP2 field to a new value.
-#define BW_AIPS_PACRF_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRF, field SP2[22] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this bit is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
- * set. If not, access terminates with an error response and no peripheral access
- * initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRF_SP2 (22U) //!< Bit position for AIPS_PACRF_SP2.
-#define BM_AIPS_PACRF_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRF_SP2.
-#define BS_AIPS_PACRF_SP2 (1U) //!< Bit field size in bits for AIPS_PACRF_SP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRF_SP2 field.
-#define BR_AIPS_PACRF_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRF_SP2.
-#define BF_AIPS_PACRF_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP2), uint32_t) & BM_AIPS_PACRF_SP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP2 field to a new value.
-#define BW_AIPS_PACRF_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRF, field TP1[24] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRF_TP1 (24U) //!< Bit position for AIPS_PACRF_TP1.
-#define BM_AIPS_PACRF_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRF_TP1.
-#define BS_AIPS_PACRF_TP1 (1U) //!< Bit field size in bits for AIPS_PACRF_TP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRF_TP1 field.
-#define BR_AIPS_PACRF_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRF_TP1.
-#define BF_AIPS_PACRF_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP1), uint32_t) & BM_AIPS_PACRF_TP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP1 field to a new value.
-#define BW_AIPS_PACRF_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRF, field WP1[25] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRF_WP1 (25U) //!< Bit position for AIPS_PACRF_WP1.
-#define BM_AIPS_PACRF_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRF_WP1.
-#define BS_AIPS_PACRF_WP1 (1U) //!< Bit field size in bits for AIPS_PACRF_WP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRF_WP1 field.
-#define BR_AIPS_PACRF_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRF_WP1.
-#define BF_AIPS_PACRF_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP1), uint32_t) & BM_AIPS_PACRF_WP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP1 field to a new value.
-#define BW_AIPS_PACRF_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRF, field SP1[26] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master must
- * be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRF_SP1 (26U) //!< Bit position for AIPS_PACRF_SP1.
-#define BM_AIPS_PACRF_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRF_SP1.
-#define BS_AIPS_PACRF_SP1 (1U) //!< Bit field size in bits for AIPS_PACRF_SP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRF_SP1 field.
-#define BR_AIPS_PACRF_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRF_SP1.
-#define BF_AIPS_PACRF_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP1), uint32_t) & BM_AIPS_PACRF_SP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP1 field to a new value.
-#define BW_AIPS_PACRF_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRF, field TP0[28] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRF_TP0 (28U) //!< Bit position for AIPS_PACRF_TP0.
-#define BM_AIPS_PACRF_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRF_TP0.
-#define BS_AIPS_PACRF_TP0 (1U) //!< Bit field size in bits for AIPS_PACRF_TP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRF_TP0 field.
-#define BR_AIPS_PACRF_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRF_TP0.
-#define BF_AIPS_PACRF_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP0), uint32_t) & BM_AIPS_PACRF_TP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP0 field to a new value.
-#define BW_AIPS_PACRF_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRF, field WP0[29] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRF_WP0 (29U) //!< Bit position for AIPS_PACRF_WP0.
-#define BM_AIPS_PACRF_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRF_WP0.
-#define BS_AIPS_PACRF_WP0 (1U) //!< Bit field size in bits for AIPS_PACRF_WP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRF_WP0 field.
-#define BR_AIPS_PACRF_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRF_WP0.
-#define BF_AIPS_PACRF_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP0), uint32_t) & BM_AIPS_PACRF_WP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP0 field to a new value.
-#define BW_AIPS_PACRF_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRF, field SP0[30] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRF_SP0 (30U) //!< Bit position for AIPS_PACRF_SP0.
-#define BM_AIPS_PACRF_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRF_SP0.
-#define BS_AIPS_PACRF_SP0 (1U) //!< Bit field size in bits for AIPS_PACRF_SP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRF_SP0 field.
-#define BR_AIPS_PACRF_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRF_SP0.
-#define BF_AIPS_PACRF_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP0), uint32_t) & BM_AIPS_PACRF_SP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP0 field to a new value.
-#define BW_AIPS_PACRF_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP0) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_AIPS_PACRG - Peripheral Access Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_AIPS_PACRG - Peripheral Access Control Register (RW)
- *
- * Reset value: 0x44444444U
- *
- * This section describes PACR registers E-P, which control peripheral slots
- * 32-127. See PACRPeripheral Access Control Register for the description of these
- * registers.
- */
-typedef union _hw_aips_pacrg
-{
- uint32_t U;
- struct _hw_aips_pacrg_bitfields
- {
- uint32_t TP7 : 1; //!< [0] Trusted Protect
- uint32_t WP7 : 1; //!< [1] Write Protect
- uint32_t SP7 : 1; //!< [2] Supervisor Protect
- uint32_t RESERVED0 : 1; //!< [3]
- uint32_t TP6 : 1; //!< [4] Trusted Protect
- uint32_t WP6 : 1; //!< [5] Write Protect
- uint32_t SP6 : 1; //!< [6] Supervisor Protect
- uint32_t RESERVED1 : 1; //!< [7]
- uint32_t TP5 : 1; //!< [8] Trusted Protect
- uint32_t WP5 : 1; //!< [9] Write Protect
- uint32_t SP5 : 1; //!< [10] Supervisor Protect
- uint32_t RESERVED2 : 1; //!< [11]
- uint32_t TP4 : 1; //!< [12] Trusted Protect
- uint32_t WP4 : 1; //!< [13] Write Protect
- uint32_t SP4 : 1; //!< [14] Supervisor Protect
- uint32_t RESERVED3 : 1; //!< [15]
- uint32_t TP3 : 1; //!< [16] Trusted Protect
- uint32_t WP3 : 1; //!< [17] Write Protect
- uint32_t SP3 : 1; //!< [18] Supervisor Protect
- uint32_t RESERVED4 : 1; //!< [19]
- uint32_t TP2 : 1; //!< [20] Trusted Protect
- uint32_t WP2 : 1; //!< [21] Write Protect
- uint32_t SP2 : 1; //!< [22] Supervisor Protect
- uint32_t RESERVED5 : 1; //!< [23]
- uint32_t TP1 : 1; //!< [24] Trusted Protect
- uint32_t WP1 : 1; //!< [25] Write Protect
- uint32_t SP1 : 1; //!< [26] Supervisor Protect
- uint32_t RESERVED6 : 1; //!< [27]
- uint32_t TP0 : 1; //!< [28] Trusted Protect
- uint32_t WP0 : 1; //!< [29] Write Protect
- uint32_t SP0 : 1; //!< [30] Supervisor Protect
- uint32_t RESERVED7 : 1; //!< [31]
- } B;
-} hw_aips_pacrg_t;
-#endif
-
-/*!
- * @name Constants and macros for entire AIPS_PACRG register
- */
-//@{
-#define HW_AIPS_PACRG_ADDR(x) (REGS_AIPS_BASE(x) + 0x48U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_AIPS_PACRG(x) (*(__IO hw_aips_pacrg_t *) HW_AIPS_PACRG_ADDR(x))
-#define HW_AIPS_PACRG_RD(x) (HW_AIPS_PACRG(x).U)
-#define HW_AIPS_PACRG_WR(x, v) (HW_AIPS_PACRG(x).U = (v))
-#define HW_AIPS_PACRG_SET(x, v) (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) | (v)))
-#define HW_AIPS_PACRG_CLR(x, v) (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) & ~(v)))
-#define HW_AIPS_PACRG_TOG(x, v) (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual AIPS_PACRG bitfields
- */
-
-/*!
- * @name Register AIPS_PACRG, field TP7[0] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRG_TP7 (0U) //!< Bit position for AIPS_PACRG_TP7.
-#define BM_AIPS_PACRG_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRG_TP7.
-#define BS_AIPS_PACRG_TP7 (1U) //!< Bit field size in bits for AIPS_PACRG_TP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRG_TP7 field.
-#define BR_AIPS_PACRG_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRG_TP7.
-#define BF_AIPS_PACRG_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP7), uint32_t) & BM_AIPS_PACRG_TP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP7 field to a new value.
-#define BW_AIPS_PACRG_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRG, field WP7[1] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRG_WP7 (1U) //!< Bit position for AIPS_PACRG_WP7.
-#define BM_AIPS_PACRG_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRG_WP7.
-#define BS_AIPS_PACRG_WP7 (1U) //!< Bit field size in bits for AIPS_PACRG_WP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRG_WP7 field.
-#define BR_AIPS_PACRG_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRG_WP7.
-#define BF_AIPS_PACRG_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP7), uint32_t) & BM_AIPS_PACRG_WP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP7 field to a new value.
-#define BW_AIPS_PACRG_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRG, field SP7[2] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRG_SP7 (2U) //!< Bit position for AIPS_PACRG_SP7.
-#define BM_AIPS_PACRG_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRG_SP7.
-#define BS_AIPS_PACRG_SP7 (1U) //!< Bit field size in bits for AIPS_PACRG_SP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRG_SP7 field.
-#define BR_AIPS_PACRG_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRG_SP7.
-#define BF_AIPS_PACRG_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP7), uint32_t) & BM_AIPS_PACRG_SP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP7 field to a new value.
-#define BW_AIPS_PACRG_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRG, field TP6[4] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRG_TP6 (4U) //!< Bit position for AIPS_PACRG_TP6.
-#define BM_AIPS_PACRG_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRG_TP6.
-#define BS_AIPS_PACRG_TP6 (1U) //!< Bit field size in bits for AIPS_PACRG_TP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRG_TP6 field.
-#define BR_AIPS_PACRG_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRG_TP6.
-#define BF_AIPS_PACRG_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP6), uint32_t) & BM_AIPS_PACRG_TP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP6 field to a new value.
-#define BW_AIPS_PACRG_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRG, field WP6[5] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRG_WP6 (5U) //!< Bit position for AIPS_PACRG_WP6.
-#define BM_AIPS_PACRG_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRG_WP6.
-#define BS_AIPS_PACRG_WP6 (1U) //!< Bit field size in bits for AIPS_PACRG_WP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRG_WP6 field.
-#define BR_AIPS_PACRG_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRG_WP6.
-#define BF_AIPS_PACRG_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP6), uint32_t) & BM_AIPS_PACRG_WP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP6 field to a new value.
-#define BW_AIPS_PACRG_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRG, field SP6[6] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRG_SP6 (6U) //!< Bit position for AIPS_PACRG_SP6.
-#define BM_AIPS_PACRG_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRG_SP6.
-#define BS_AIPS_PACRG_SP6 (1U) //!< Bit field size in bits for AIPS_PACRG_SP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRG_SP6 field.
-#define BR_AIPS_PACRG_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRG_SP6.
-#define BF_AIPS_PACRG_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP6), uint32_t) & BM_AIPS_PACRG_SP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP6 field to a new value.
-#define BW_AIPS_PACRG_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRG, field TP5[8] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRG_TP5 (8U) //!< Bit position for AIPS_PACRG_TP5.
-#define BM_AIPS_PACRG_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRG_TP5.
-#define BS_AIPS_PACRG_TP5 (1U) //!< Bit field size in bits for AIPS_PACRG_TP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRG_TP5 field.
-#define BR_AIPS_PACRG_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRG_TP5.
-#define BF_AIPS_PACRG_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP5), uint32_t) & BM_AIPS_PACRG_TP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP5 field to a new value.
-#define BW_AIPS_PACRG_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRG, field WP5[9] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRG_WP5 (9U) //!< Bit position for AIPS_PACRG_WP5.
-#define BM_AIPS_PACRG_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRG_WP5.
-#define BS_AIPS_PACRG_WP5 (1U) //!< Bit field size in bits for AIPS_PACRG_WP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRG_WP5 field.
-#define BR_AIPS_PACRG_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRG_WP5.
-#define BF_AIPS_PACRG_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP5), uint32_t) & BM_AIPS_PACRG_WP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP5 field to a new value.
-#define BW_AIPS_PACRG_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRG, field SP5[10] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRG_SP5 (10U) //!< Bit position for AIPS_PACRG_SP5.
-#define BM_AIPS_PACRG_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRG_SP5.
-#define BS_AIPS_PACRG_SP5 (1U) //!< Bit field size in bits for AIPS_PACRG_SP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRG_SP5 field.
-#define BR_AIPS_PACRG_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRG_SP5.
-#define BF_AIPS_PACRG_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP5), uint32_t) & BM_AIPS_PACRG_SP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP5 field to a new value.
-#define BW_AIPS_PACRG_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRG, field TP4[12] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRG_TP4 (12U) //!< Bit position for AIPS_PACRG_TP4.
-#define BM_AIPS_PACRG_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRG_TP4.
-#define BS_AIPS_PACRG_TP4 (1U) //!< Bit field size in bits for AIPS_PACRG_TP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRG_TP4 field.
-#define BR_AIPS_PACRG_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRG_TP4.
-#define BF_AIPS_PACRG_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP4), uint32_t) & BM_AIPS_PACRG_TP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP4 field to a new value.
-#define BW_AIPS_PACRG_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRG, field WP4[13] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRG_WP4 (13U) //!< Bit position for AIPS_PACRG_WP4.
-#define BM_AIPS_PACRG_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRG_WP4.
-#define BS_AIPS_PACRG_WP4 (1U) //!< Bit field size in bits for AIPS_PACRG_WP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRG_WP4 field.
-#define BR_AIPS_PACRG_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRG_WP4.
-#define BF_AIPS_PACRG_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP4), uint32_t) & BM_AIPS_PACRG_WP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP4 field to a new value.
-#define BW_AIPS_PACRG_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRG, field SP4[14] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this bit is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
- * set. If not, access terminates with an error response and no peripheral access
- * initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRG_SP4 (14U) //!< Bit position for AIPS_PACRG_SP4.
-#define BM_AIPS_PACRG_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRG_SP4.
-#define BS_AIPS_PACRG_SP4 (1U) //!< Bit field size in bits for AIPS_PACRG_SP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRG_SP4 field.
-#define BR_AIPS_PACRG_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRG_SP4.
-#define BF_AIPS_PACRG_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP4), uint32_t) & BM_AIPS_PACRG_SP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP4 field to a new value.
-#define BW_AIPS_PACRG_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRG, field TP3[16] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRG_TP3 (16U) //!< Bit position for AIPS_PACRG_TP3.
-#define BM_AIPS_PACRG_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRG_TP3.
-#define BS_AIPS_PACRG_TP3 (1U) //!< Bit field size in bits for AIPS_PACRG_TP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRG_TP3 field.
-#define BR_AIPS_PACRG_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRG_TP3.
-#define BF_AIPS_PACRG_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP3), uint32_t) & BM_AIPS_PACRG_TP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP3 field to a new value.
-#define BW_AIPS_PACRG_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRG, field WP3[17] (RW)
- *
- * Determines whether the peripheral allows write accesss. When this bit is set
- * and a write access is attempted, access terminates with an error response and
- * no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRG_WP3 (17U) //!< Bit position for AIPS_PACRG_WP3.
-#define BM_AIPS_PACRG_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRG_WP3.
-#define BS_AIPS_PACRG_WP3 (1U) //!< Bit field size in bits for AIPS_PACRG_WP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRG_WP3 field.
-#define BR_AIPS_PACRG_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRG_WP3.
-#define BF_AIPS_PACRG_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP3), uint32_t) & BM_AIPS_PACRG_WP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP3 field to a new value.
-#define BW_AIPS_PACRG_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRG, field SP3[18] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRG_SP3 (18U) //!< Bit position for AIPS_PACRG_SP3.
-#define BM_AIPS_PACRG_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRG_SP3.
-#define BS_AIPS_PACRG_SP3 (1U) //!< Bit field size in bits for AIPS_PACRG_SP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRG_SP3 field.
-#define BR_AIPS_PACRG_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRG_SP3.
-#define BF_AIPS_PACRG_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP3), uint32_t) & BM_AIPS_PACRG_SP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP3 field to a new value.
-#define BW_AIPS_PACRG_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRG, field TP2[20] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRG_TP2 (20U) //!< Bit position for AIPS_PACRG_TP2.
-#define BM_AIPS_PACRG_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRG_TP2.
-#define BS_AIPS_PACRG_TP2 (1U) //!< Bit field size in bits for AIPS_PACRG_TP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRG_TP2 field.
-#define BR_AIPS_PACRG_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRG_TP2.
-#define BF_AIPS_PACRG_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP2), uint32_t) & BM_AIPS_PACRG_TP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP2 field to a new value.
-#define BW_AIPS_PACRG_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRG, field WP2[21] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRG_WP2 (21U) //!< Bit position for AIPS_PACRG_WP2.
-#define BM_AIPS_PACRG_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRG_WP2.
-#define BS_AIPS_PACRG_WP2 (1U) //!< Bit field size in bits for AIPS_PACRG_WP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRG_WP2 field.
-#define BR_AIPS_PACRG_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRG_WP2.
-#define BF_AIPS_PACRG_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP2), uint32_t) & BM_AIPS_PACRG_WP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP2 field to a new value.
-#define BW_AIPS_PACRG_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRG, field SP2[22] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this bit is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
- * set. If not, access terminates with an error response and no peripheral access
- * initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRG_SP2 (22U) //!< Bit position for AIPS_PACRG_SP2.
-#define BM_AIPS_PACRG_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRG_SP2.
-#define BS_AIPS_PACRG_SP2 (1U) //!< Bit field size in bits for AIPS_PACRG_SP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRG_SP2 field.
-#define BR_AIPS_PACRG_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRG_SP2.
-#define BF_AIPS_PACRG_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP2), uint32_t) & BM_AIPS_PACRG_SP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP2 field to a new value.
-#define BW_AIPS_PACRG_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRG, field TP1[24] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRG_TP1 (24U) //!< Bit position for AIPS_PACRG_TP1.
-#define BM_AIPS_PACRG_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRG_TP1.
-#define BS_AIPS_PACRG_TP1 (1U) //!< Bit field size in bits for AIPS_PACRG_TP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRG_TP1 field.
-#define BR_AIPS_PACRG_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRG_TP1.
-#define BF_AIPS_PACRG_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP1), uint32_t) & BM_AIPS_PACRG_TP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP1 field to a new value.
-#define BW_AIPS_PACRG_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRG, field WP1[25] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRG_WP1 (25U) //!< Bit position for AIPS_PACRG_WP1.
-#define BM_AIPS_PACRG_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRG_WP1.
-#define BS_AIPS_PACRG_WP1 (1U) //!< Bit field size in bits for AIPS_PACRG_WP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRG_WP1 field.
-#define BR_AIPS_PACRG_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRG_WP1.
-#define BF_AIPS_PACRG_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP1), uint32_t) & BM_AIPS_PACRG_WP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP1 field to a new value.
-#define BW_AIPS_PACRG_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRG, field SP1[26] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master must
- * be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRG_SP1 (26U) //!< Bit position for AIPS_PACRG_SP1.
-#define BM_AIPS_PACRG_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRG_SP1.
-#define BS_AIPS_PACRG_SP1 (1U) //!< Bit field size in bits for AIPS_PACRG_SP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRG_SP1 field.
-#define BR_AIPS_PACRG_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRG_SP1.
-#define BF_AIPS_PACRG_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP1), uint32_t) & BM_AIPS_PACRG_SP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP1 field to a new value.
-#define BW_AIPS_PACRG_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRG, field TP0[28] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRG_TP0 (28U) //!< Bit position for AIPS_PACRG_TP0.
-#define BM_AIPS_PACRG_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRG_TP0.
-#define BS_AIPS_PACRG_TP0 (1U) //!< Bit field size in bits for AIPS_PACRG_TP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRG_TP0 field.
-#define BR_AIPS_PACRG_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRG_TP0.
-#define BF_AIPS_PACRG_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP0), uint32_t) & BM_AIPS_PACRG_TP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP0 field to a new value.
-#define BW_AIPS_PACRG_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRG, field WP0[29] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRG_WP0 (29U) //!< Bit position for AIPS_PACRG_WP0.
-#define BM_AIPS_PACRG_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRG_WP0.
-#define BS_AIPS_PACRG_WP0 (1U) //!< Bit field size in bits for AIPS_PACRG_WP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRG_WP0 field.
-#define BR_AIPS_PACRG_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRG_WP0.
-#define BF_AIPS_PACRG_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP0), uint32_t) & BM_AIPS_PACRG_WP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP0 field to a new value.
-#define BW_AIPS_PACRG_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRG, field SP0[30] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRG_SP0 (30U) //!< Bit position for AIPS_PACRG_SP0.
-#define BM_AIPS_PACRG_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRG_SP0.
-#define BS_AIPS_PACRG_SP0 (1U) //!< Bit field size in bits for AIPS_PACRG_SP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRG_SP0 field.
-#define BR_AIPS_PACRG_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRG_SP0.
-#define BF_AIPS_PACRG_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP0), uint32_t) & BM_AIPS_PACRG_SP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP0 field to a new value.
-#define BW_AIPS_PACRG_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP0) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_AIPS_PACRH - Peripheral Access Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_AIPS_PACRH - Peripheral Access Control Register (RW)
- *
- * Reset value: 0x44444444U
- *
- * This section describes PACR registers E-P, which control peripheral slots
- * 32-127. See PACRPeripheral Access Control Register for the description of these
- * registers.
- */
-typedef union _hw_aips_pacrh
-{
- uint32_t U;
- struct _hw_aips_pacrh_bitfields
- {
- uint32_t TP7 : 1; //!< [0] Trusted Protect
- uint32_t WP7 : 1; //!< [1] Write Protect
- uint32_t SP7 : 1; //!< [2] Supervisor Protect
- uint32_t RESERVED0 : 1; //!< [3]
- uint32_t TP6 : 1; //!< [4] Trusted Protect
- uint32_t WP6 : 1; //!< [5] Write Protect
- uint32_t SP6 : 1; //!< [6] Supervisor Protect
- uint32_t RESERVED1 : 1; //!< [7]
- uint32_t TP5 : 1; //!< [8] Trusted Protect
- uint32_t WP5 : 1; //!< [9] Write Protect
- uint32_t SP5 : 1; //!< [10] Supervisor Protect
- uint32_t RESERVED2 : 1; //!< [11]
- uint32_t TP4 : 1; //!< [12] Trusted Protect
- uint32_t WP4 : 1; //!< [13] Write Protect
- uint32_t SP4 : 1; //!< [14] Supervisor Protect
- uint32_t RESERVED3 : 1; //!< [15]
- uint32_t TP3 : 1; //!< [16] Trusted Protect
- uint32_t WP3 : 1; //!< [17] Write Protect
- uint32_t SP3 : 1; //!< [18] Supervisor Protect
- uint32_t RESERVED4 : 1; //!< [19]
- uint32_t TP2 : 1; //!< [20] Trusted Protect
- uint32_t WP2 : 1; //!< [21] Write Protect
- uint32_t SP2 : 1; //!< [22] Supervisor Protect
- uint32_t RESERVED5 : 1; //!< [23]
- uint32_t TP1 : 1; //!< [24] Trusted Protect
- uint32_t WP1 : 1; //!< [25] Write Protect
- uint32_t SP1 : 1; //!< [26] Supervisor Protect
- uint32_t RESERVED6 : 1; //!< [27]
- uint32_t TP0 : 1; //!< [28] Trusted Protect
- uint32_t WP0 : 1; //!< [29] Write Protect
- uint32_t SP0 : 1; //!< [30] Supervisor Protect
- uint32_t RESERVED7 : 1; //!< [31]
- } B;
-} hw_aips_pacrh_t;
-#endif
-
-/*!
- * @name Constants and macros for entire AIPS_PACRH register
- */
-//@{
-#define HW_AIPS_PACRH_ADDR(x) (REGS_AIPS_BASE(x) + 0x4CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_AIPS_PACRH(x) (*(__IO hw_aips_pacrh_t *) HW_AIPS_PACRH_ADDR(x))
-#define HW_AIPS_PACRH_RD(x) (HW_AIPS_PACRH(x).U)
-#define HW_AIPS_PACRH_WR(x, v) (HW_AIPS_PACRH(x).U = (v))
-#define HW_AIPS_PACRH_SET(x, v) (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) | (v)))
-#define HW_AIPS_PACRH_CLR(x, v) (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) & ~(v)))
-#define HW_AIPS_PACRH_TOG(x, v) (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual AIPS_PACRH bitfields
- */
-
-/*!
- * @name Register AIPS_PACRH, field TP7[0] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRH_TP7 (0U) //!< Bit position for AIPS_PACRH_TP7.
-#define BM_AIPS_PACRH_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRH_TP7.
-#define BS_AIPS_PACRH_TP7 (1U) //!< Bit field size in bits for AIPS_PACRH_TP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRH_TP7 field.
-#define BR_AIPS_PACRH_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRH_TP7.
-#define BF_AIPS_PACRH_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP7), uint32_t) & BM_AIPS_PACRH_TP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP7 field to a new value.
-#define BW_AIPS_PACRH_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRH, field WP7[1] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRH_WP7 (1U) //!< Bit position for AIPS_PACRH_WP7.
-#define BM_AIPS_PACRH_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRH_WP7.
-#define BS_AIPS_PACRH_WP7 (1U) //!< Bit field size in bits for AIPS_PACRH_WP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRH_WP7 field.
-#define BR_AIPS_PACRH_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRH_WP7.
-#define BF_AIPS_PACRH_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP7), uint32_t) & BM_AIPS_PACRH_WP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP7 field to a new value.
-#define BW_AIPS_PACRH_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRH, field SP7[2] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRH_SP7 (2U) //!< Bit position for AIPS_PACRH_SP7.
-#define BM_AIPS_PACRH_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRH_SP7.
-#define BS_AIPS_PACRH_SP7 (1U) //!< Bit field size in bits for AIPS_PACRH_SP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRH_SP7 field.
-#define BR_AIPS_PACRH_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRH_SP7.
-#define BF_AIPS_PACRH_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP7), uint32_t) & BM_AIPS_PACRH_SP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP7 field to a new value.
-#define BW_AIPS_PACRH_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRH, field TP6[4] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRH_TP6 (4U) //!< Bit position for AIPS_PACRH_TP6.
-#define BM_AIPS_PACRH_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRH_TP6.
-#define BS_AIPS_PACRH_TP6 (1U) //!< Bit field size in bits for AIPS_PACRH_TP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRH_TP6 field.
-#define BR_AIPS_PACRH_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRH_TP6.
-#define BF_AIPS_PACRH_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP6), uint32_t) & BM_AIPS_PACRH_TP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP6 field to a new value.
-#define BW_AIPS_PACRH_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRH, field WP6[5] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRH_WP6 (5U) //!< Bit position for AIPS_PACRH_WP6.
-#define BM_AIPS_PACRH_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRH_WP6.
-#define BS_AIPS_PACRH_WP6 (1U) //!< Bit field size in bits for AIPS_PACRH_WP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRH_WP6 field.
-#define BR_AIPS_PACRH_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRH_WP6.
-#define BF_AIPS_PACRH_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP6), uint32_t) & BM_AIPS_PACRH_WP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP6 field to a new value.
-#define BW_AIPS_PACRH_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRH, field SP6[6] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRH_SP6 (6U) //!< Bit position for AIPS_PACRH_SP6.
-#define BM_AIPS_PACRH_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRH_SP6.
-#define BS_AIPS_PACRH_SP6 (1U) //!< Bit field size in bits for AIPS_PACRH_SP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRH_SP6 field.
-#define BR_AIPS_PACRH_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRH_SP6.
-#define BF_AIPS_PACRH_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP6), uint32_t) & BM_AIPS_PACRH_SP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP6 field to a new value.
-#define BW_AIPS_PACRH_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRH, field TP5[8] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRH_TP5 (8U) //!< Bit position for AIPS_PACRH_TP5.
-#define BM_AIPS_PACRH_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRH_TP5.
-#define BS_AIPS_PACRH_TP5 (1U) //!< Bit field size in bits for AIPS_PACRH_TP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRH_TP5 field.
-#define BR_AIPS_PACRH_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRH_TP5.
-#define BF_AIPS_PACRH_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP5), uint32_t) & BM_AIPS_PACRH_TP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP5 field to a new value.
-#define BW_AIPS_PACRH_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRH, field WP5[9] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRH_WP5 (9U) //!< Bit position for AIPS_PACRH_WP5.
-#define BM_AIPS_PACRH_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRH_WP5.
-#define BS_AIPS_PACRH_WP5 (1U) //!< Bit field size in bits for AIPS_PACRH_WP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRH_WP5 field.
-#define BR_AIPS_PACRH_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRH_WP5.
-#define BF_AIPS_PACRH_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP5), uint32_t) & BM_AIPS_PACRH_WP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP5 field to a new value.
-#define BW_AIPS_PACRH_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRH, field SP5[10] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRH_SP5 (10U) //!< Bit position for AIPS_PACRH_SP5.
-#define BM_AIPS_PACRH_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRH_SP5.
-#define BS_AIPS_PACRH_SP5 (1U) //!< Bit field size in bits for AIPS_PACRH_SP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRH_SP5 field.
-#define BR_AIPS_PACRH_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRH_SP5.
-#define BF_AIPS_PACRH_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP5), uint32_t) & BM_AIPS_PACRH_SP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP5 field to a new value.
-#define BW_AIPS_PACRH_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRH, field TP4[12] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRH_TP4 (12U) //!< Bit position for AIPS_PACRH_TP4.
-#define BM_AIPS_PACRH_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRH_TP4.
-#define BS_AIPS_PACRH_TP4 (1U) //!< Bit field size in bits for AIPS_PACRH_TP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRH_TP4 field.
-#define BR_AIPS_PACRH_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRH_TP4.
-#define BF_AIPS_PACRH_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP4), uint32_t) & BM_AIPS_PACRH_TP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP4 field to a new value.
-#define BW_AIPS_PACRH_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRH, field WP4[13] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRH_WP4 (13U) //!< Bit position for AIPS_PACRH_WP4.
-#define BM_AIPS_PACRH_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRH_WP4.
-#define BS_AIPS_PACRH_WP4 (1U) //!< Bit field size in bits for AIPS_PACRH_WP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRH_WP4 field.
-#define BR_AIPS_PACRH_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRH_WP4.
-#define BF_AIPS_PACRH_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP4), uint32_t) & BM_AIPS_PACRH_WP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP4 field to a new value.
-#define BW_AIPS_PACRH_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRH, field SP4[14] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this bit is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
- * set. If not, access terminates with an error response and no peripheral access
- * initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRH_SP4 (14U) //!< Bit position for AIPS_PACRH_SP4.
-#define BM_AIPS_PACRH_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRH_SP4.
-#define BS_AIPS_PACRH_SP4 (1U) //!< Bit field size in bits for AIPS_PACRH_SP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRH_SP4 field.
-#define BR_AIPS_PACRH_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRH_SP4.
-#define BF_AIPS_PACRH_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP4), uint32_t) & BM_AIPS_PACRH_SP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP4 field to a new value.
-#define BW_AIPS_PACRH_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRH, field TP3[16] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRH_TP3 (16U) //!< Bit position for AIPS_PACRH_TP3.
-#define BM_AIPS_PACRH_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRH_TP3.
-#define BS_AIPS_PACRH_TP3 (1U) //!< Bit field size in bits for AIPS_PACRH_TP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRH_TP3 field.
-#define BR_AIPS_PACRH_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRH_TP3.
-#define BF_AIPS_PACRH_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP3), uint32_t) & BM_AIPS_PACRH_TP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP3 field to a new value.
-#define BW_AIPS_PACRH_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRH, field WP3[17] (RW)
- *
- * Determines whether the peripheral allows write accesss. When this bit is set
- * and a write access is attempted, access terminates with an error response and
- * no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRH_WP3 (17U) //!< Bit position for AIPS_PACRH_WP3.
-#define BM_AIPS_PACRH_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRH_WP3.
-#define BS_AIPS_PACRH_WP3 (1U) //!< Bit field size in bits for AIPS_PACRH_WP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRH_WP3 field.
-#define BR_AIPS_PACRH_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRH_WP3.
-#define BF_AIPS_PACRH_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP3), uint32_t) & BM_AIPS_PACRH_WP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP3 field to a new value.
-#define BW_AIPS_PACRH_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRH, field SP3[18] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRH_SP3 (18U) //!< Bit position for AIPS_PACRH_SP3.
-#define BM_AIPS_PACRH_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRH_SP3.
-#define BS_AIPS_PACRH_SP3 (1U) //!< Bit field size in bits for AIPS_PACRH_SP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRH_SP3 field.
-#define BR_AIPS_PACRH_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRH_SP3.
-#define BF_AIPS_PACRH_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP3), uint32_t) & BM_AIPS_PACRH_SP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP3 field to a new value.
-#define BW_AIPS_PACRH_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRH, field TP2[20] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRH_TP2 (20U) //!< Bit position for AIPS_PACRH_TP2.
-#define BM_AIPS_PACRH_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRH_TP2.
-#define BS_AIPS_PACRH_TP2 (1U) //!< Bit field size in bits for AIPS_PACRH_TP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRH_TP2 field.
-#define BR_AIPS_PACRH_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRH_TP2.
-#define BF_AIPS_PACRH_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP2), uint32_t) & BM_AIPS_PACRH_TP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP2 field to a new value.
-#define BW_AIPS_PACRH_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRH, field WP2[21] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRH_WP2 (21U) //!< Bit position for AIPS_PACRH_WP2.
-#define BM_AIPS_PACRH_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRH_WP2.
-#define BS_AIPS_PACRH_WP2 (1U) //!< Bit field size in bits for AIPS_PACRH_WP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRH_WP2 field.
-#define BR_AIPS_PACRH_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRH_WP2.
-#define BF_AIPS_PACRH_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP2), uint32_t) & BM_AIPS_PACRH_WP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP2 field to a new value.
-#define BW_AIPS_PACRH_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRH, field SP2[22] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this bit is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
- * set. If not, access terminates with an error response and no peripheral access
- * initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRH_SP2 (22U) //!< Bit position for AIPS_PACRH_SP2.
-#define BM_AIPS_PACRH_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRH_SP2.
-#define BS_AIPS_PACRH_SP2 (1U) //!< Bit field size in bits for AIPS_PACRH_SP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRH_SP2 field.
-#define BR_AIPS_PACRH_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRH_SP2.
-#define BF_AIPS_PACRH_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP2), uint32_t) & BM_AIPS_PACRH_SP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP2 field to a new value.
-#define BW_AIPS_PACRH_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRH, field TP1[24] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRH_TP1 (24U) //!< Bit position for AIPS_PACRH_TP1.
-#define BM_AIPS_PACRH_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRH_TP1.
-#define BS_AIPS_PACRH_TP1 (1U) //!< Bit field size in bits for AIPS_PACRH_TP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRH_TP1 field.
-#define BR_AIPS_PACRH_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRH_TP1.
-#define BF_AIPS_PACRH_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP1), uint32_t) & BM_AIPS_PACRH_TP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP1 field to a new value.
-#define BW_AIPS_PACRH_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRH, field WP1[25] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRH_WP1 (25U) //!< Bit position for AIPS_PACRH_WP1.
-#define BM_AIPS_PACRH_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRH_WP1.
-#define BS_AIPS_PACRH_WP1 (1U) //!< Bit field size in bits for AIPS_PACRH_WP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRH_WP1 field.
-#define BR_AIPS_PACRH_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRH_WP1.
-#define BF_AIPS_PACRH_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP1), uint32_t) & BM_AIPS_PACRH_WP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP1 field to a new value.
-#define BW_AIPS_PACRH_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRH, field SP1[26] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master must
- * be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRH_SP1 (26U) //!< Bit position for AIPS_PACRH_SP1.
-#define BM_AIPS_PACRH_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRH_SP1.
-#define BS_AIPS_PACRH_SP1 (1U) //!< Bit field size in bits for AIPS_PACRH_SP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRH_SP1 field.
-#define BR_AIPS_PACRH_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRH_SP1.
-#define BF_AIPS_PACRH_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP1), uint32_t) & BM_AIPS_PACRH_SP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP1 field to a new value.
-#define BW_AIPS_PACRH_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRH, field TP0[28] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRH_TP0 (28U) //!< Bit position for AIPS_PACRH_TP0.
-#define BM_AIPS_PACRH_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRH_TP0.
-#define BS_AIPS_PACRH_TP0 (1U) //!< Bit field size in bits for AIPS_PACRH_TP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRH_TP0 field.
-#define BR_AIPS_PACRH_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRH_TP0.
-#define BF_AIPS_PACRH_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP0), uint32_t) & BM_AIPS_PACRH_TP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP0 field to a new value.
-#define BW_AIPS_PACRH_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRH, field WP0[29] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRH_WP0 (29U) //!< Bit position for AIPS_PACRH_WP0.
-#define BM_AIPS_PACRH_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRH_WP0.
-#define BS_AIPS_PACRH_WP0 (1U) //!< Bit field size in bits for AIPS_PACRH_WP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRH_WP0 field.
-#define BR_AIPS_PACRH_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRH_WP0.
-#define BF_AIPS_PACRH_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP0), uint32_t) & BM_AIPS_PACRH_WP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP0 field to a new value.
-#define BW_AIPS_PACRH_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRH, field SP0[30] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRH_SP0 (30U) //!< Bit position for AIPS_PACRH_SP0.
-#define BM_AIPS_PACRH_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRH_SP0.
-#define BS_AIPS_PACRH_SP0 (1U) //!< Bit field size in bits for AIPS_PACRH_SP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRH_SP0 field.
-#define BR_AIPS_PACRH_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRH_SP0.
-#define BF_AIPS_PACRH_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP0), uint32_t) & BM_AIPS_PACRH_SP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP0 field to a new value.
-#define BW_AIPS_PACRH_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP0) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_AIPS_PACRI - Peripheral Access Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_AIPS_PACRI - Peripheral Access Control Register (RW)
- *
- * Reset value: 0x44444444U
- *
- * This section describes PACR registers E-P, which control peripheral slots
- * 32-127. See PACRPeripheral Access Control Register for the description of these
- * registers.
- */
-typedef union _hw_aips_pacri
-{
- uint32_t U;
- struct _hw_aips_pacri_bitfields
- {
- uint32_t TP7 : 1; //!< [0] Trusted Protect
- uint32_t WP7 : 1; //!< [1] Write Protect
- uint32_t SP7 : 1; //!< [2] Supervisor Protect
- uint32_t RESERVED0 : 1; //!< [3]
- uint32_t TP6 : 1; //!< [4] Trusted Protect
- uint32_t WP6 : 1; //!< [5] Write Protect
- uint32_t SP6 : 1; //!< [6] Supervisor Protect
- uint32_t RESERVED1 : 1; //!< [7]
- uint32_t TP5 : 1; //!< [8] Trusted Protect
- uint32_t WP5 : 1; //!< [9] Write Protect
- uint32_t SP5 : 1; //!< [10] Supervisor Protect
- uint32_t RESERVED2 : 1; //!< [11]
- uint32_t TP4 : 1; //!< [12] Trusted Protect
- uint32_t WP4 : 1; //!< [13] Write Protect
- uint32_t SP4 : 1; //!< [14] Supervisor Protect
- uint32_t RESERVED3 : 1; //!< [15]
- uint32_t TP3 : 1; //!< [16] Trusted Protect
- uint32_t WP3 : 1; //!< [17] Write Protect
- uint32_t SP3 : 1; //!< [18] Supervisor Protect
- uint32_t RESERVED4 : 1; //!< [19]
- uint32_t TP2 : 1; //!< [20] Trusted Protect
- uint32_t WP2 : 1; //!< [21] Write Protect
- uint32_t SP2 : 1; //!< [22] Supervisor Protect
- uint32_t RESERVED5 : 1; //!< [23]
- uint32_t TP1 : 1; //!< [24] Trusted Protect
- uint32_t WP1 : 1; //!< [25] Write Protect
- uint32_t SP1 : 1; //!< [26] Supervisor Protect
- uint32_t RESERVED6 : 1; //!< [27]
- uint32_t TP0 : 1; //!< [28] Trusted Protect
- uint32_t WP0 : 1; //!< [29] Write Protect
- uint32_t SP0 : 1; //!< [30] Supervisor Protect
- uint32_t RESERVED7 : 1; //!< [31]
- } B;
-} hw_aips_pacri_t;
-#endif
-
-/*!
- * @name Constants and macros for entire AIPS_PACRI register
- */
-//@{
-#define HW_AIPS_PACRI_ADDR(x) (REGS_AIPS_BASE(x) + 0x50U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_AIPS_PACRI(x) (*(__IO hw_aips_pacri_t *) HW_AIPS_PACRI_ADDR(x))
-#define HW_AIPS_PACRI_RD(x) (HW_AIPS_PACRI(x).U)
-#define HW_AIPS_PACRI_WR(x, v) (HW_AIPS_PACRI(x).U = (v))
-#define HW_AIPS_PACRI_SET(x, v) (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) | (v)))
-#define HW_AIPS_PACRI_CLR(x, v) (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) & ~(v)))
-#define HW_AIPS_PACRI_TOG(x, v) (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual AIPS_PACRI bitfields
- */
-
-/*!
- * @name Register AIPS_PACRI, field TP7[0] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRI_TP7 (0U) //!< Bit position for AIPS_PACRI_TP7.
-#define BM_AIPS_PACRI_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRI_TP7.
-#define BS_AIPS_PACRI_TP7 (1U) //!< Bit field size in bits for AIPS_PACRI_TP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRI_TP7 field.
-#define BR_AIPS_PACRI_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRI_TP7.
-#define BF_AIPS_PACRI_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP7), uint32_t) & BM_AIPS_PACRI_TP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP7 field to a new value.
-#define BW_AIPS_PACRI_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRI, field WP7[1] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRI_WP7 (1U) //!< Bit position for AIPS_PACRI_WP7.
-#define BM_AIPS_PACRI_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRI_WP7.
-#define BS_AIPS_PACRI_WP7 (1U) //!< Bit field size in bits for AIPS_PACRI_WP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRI_WP7 field.
-#define BR_AIPS_PACRI_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRI_WP7.
-#define BF_AIPS_PACRI_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP7), uint32_t) & BM_AIPS_PACRI_WP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP7 field to a new value.
-#define BW_AIPS_PACRI_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRI, field SP7[2] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRI_SP7 (2U) //!< Bit position for AIPS_PACRI_SP7.
-#define BM_AIPS_PACRI_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRI_SP7.
-#define BS_AIPS_PACRI_SP7 (1U) //!< Bit field size in bits for AIPS_PACRI_SP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRI_SP7 field.
-#define BR_AIPS_PACRI_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRI_SP7.
-#define BF_AIPS_PACRI_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP7), uint32_t) & BM_AIPS_PACRI_SP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP7 field to a new value.
-#define BW_AIPS_PACRI_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRI, field TP6[4] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRI_TP6 (4U) //!< Bit position for AIPS_PACRI_TP6.
-#define BM_AIPS_PACRI_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRI_TP6.
-#define BS_AIPS_PACRI_TP6 (1U) //!< Bit field size in bits for AIPS_PACRI_TP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRI_TP6 field.
-#define BR_AIPS_PACRI_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRI_TP6.
-#define BF_AIPS_PACRI_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP6), uint32_t) & BM_AIPS_PACRI_TP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP6 field to a new value.
-#define BW_AIPS_PACRI_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRI, field WP6[5] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRI_WP6 (5U) //!< Bit position for AIPS_PACRI_WP6.
-#define BM_AIPS_PACRI_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRI_WP6.
-#define BS_AIPS_PACRI_WP6 (1U) //!< Bit field size in bits for AIPS_PACRI_WP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRI_WP6 field.
-#define BR_AIPS_PACRI_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRI_WP6.
-#define BF_AIPS_PACRI_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP6), uint32_t) & BM_AIPS_PACRI_WP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP6 field to a new value.
-#define BW_AIPS_PACRI_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRI, field SP6[6] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRI_SP6 (6U) //!< Bit position for AIPS_PACRI_SP6.
-#define BM_AIPS_PACRI_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRI_SP6.
-#define BS_AIPS_PACRI_SP6 (1U) //!< Bit field size in bits for AIPS_PACRI_SP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRI_SP6 field.
-#define BR_AIPS_PACRI_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRI_SP6.
-#define BF_AIPS_PACRI_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP6), uint32_t) & BM_AIPS_PACRI_SP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP6 field to a new value.
-#define BW_AIPS_PACRI_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRI, field TP5[8] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRI_TP5 (8U) //!< Bit position for AIPS_PACRI_TP5.
-#define BM_AIPS_PACRI_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRI_TP5.
-#define BS_AIPS_PACRI_TP5 (1U) //!< Bit field size in bits for AIPS_PACRI_TP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRI_TP5 field.
-#define BR_AIPS_PACRI_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRI_TP5.
-#define BF_AIPS_PACRI_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP5), uint32_t) & BM_AIPS_PACRI_TP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP5 field to a new value.
-#define BW_AIPS_PACRI_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRI, field WP5[9] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRI_WP5 (9U) //!< Bit position for AIPS_PACRI_WP5.
-#define BM_AIPS_PACRI_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRI_WP5.
-#define BS_AIPS_PACRI_WP5 (1U) //!< Bit field size in bits for AIPS_PACRI_WP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRI_WP5 field.
-#define BR_AIPS_PACRI_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRI_WP5.
-#define BF_AIPS_PACRI_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP5), uint32_t) & BM_AIPS_PACRI_WP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP5 field to a new value.
-#define BW_AIPS_PACRI_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRI, field SP5[10] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRI_SP5 (10U) //!< Bit position for AIPS_PACRI_SP5.
-#define BM_AIPS_PACRI_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRI_SP5.
-#define BS_AIPS_PACRI_SP5 (1U) //!< Bit field size in bits for AIPS_PACRI_SP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRI_SP5 field.
-#define BR_AIPS_PACRI_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRI_SP5.
-#define BF_AIPS_PACRI_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP5), uint32_t) & BM_AIPS_PACRI_SP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP5 field to a new value.
-#define BW_AIPS_PACRI_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRI, field TP4[12] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRI_TP4 (12U) //!< Bit position for AIPS_PACRI_TP4.
-#define BM_AIPS_PACRI_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRI_TP4.
-#define BS_AIPS_PACRI_TP4 (1U) //!< Bit field size in bits for AIPS_PACRI_TP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRI_TP4 field.
-#define BR_AIPS_PACRI_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRI_TP4.
-#define BF_AIPS_PACRI_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP4), uint32_t) & BM_AIPS_PACRI_TP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP4 field to a new value.
-#define BW_AIPS_PACRI_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRI, field WP4[13] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRI_WP4 (13U) //!< Bit position for AIPS_PACRI_WP4.
-#define BM_AIPS_PACRI_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRI_WP4.
-#define BS_AIPS_PACRI_WP4 (1U) //!< Bit field size in bits for AIPS_PACRI_WP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRI_WP4 field.
-#define BR_AIPS_PACRI_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRI_WP4.
-#define BF_AIPS_PACRI_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP4), uint32_t) & BM_AIPS_PACRI_WP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP4 field to a new value.
-#define BW_AIPS_PACRI_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRI, field SP4[14] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this bit is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
- * set. If not, access terminates with an error response and no peripheral access
- * initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRI_SP4 (14U) //!< Bit position for AIPS_PACRI_SP4.
-#define BM_AIPS_PACRI_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRI_SP4.
-#define BS_AIPS_PACRI_SP4 (1U) //!< Bit field size in bits for AIPS_PACRI_SP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRI_SP4 field.
-#define BR_AIPS_PACRI_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRI_SP4.
-#define BF_AIPS_PACRI_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP4), uint32_t) & BM_AIPS_PACRI_SP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP4 field to a new value.
-#define BW_AIPS_PACRI_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRI, field TP3[16] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRI_TP3 (16U) //!< Bit position for AIPS_PACRI_TP3.
-#define BM_AIPS_PACRI_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRI_TP3.
-#define BS_AIPS_PACRI_TP3 (1U) //!< Bit field size in bits for AIPS_PACRI_TP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRI_TP3 field.
-#define BR_AIPS_PACRI_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRI_TP3.
-#define BF_AIPS_PACRI_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP3), uint32_t) & BM_AIPS_PACRI_TP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP3 field to a new value.
-#define BW_AIPS_PACRI_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRI, field WP3[17] (RW)
- *
- * Determines whether the peripheral allows write accesss. When this bit is set
- * and a write access is attempted, access terminates with an error response and
- * no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRI_WP3 (17U) //!< Bit position for AIPS_PACRI_WP3.
-#define BM_AIPS_PACRI_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRI_WP3.
-#define BS_AIPS_PACRI_WP3 (1U) //!< Bit field size in bits for AIPS_PACRI_WP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRI_WP3 field.
-#define BR_AIPS_PACRI_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRI_WP3.
-#define BF_AIPS_PACRI_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP3), uint32_t) & BM_AIPS_PACRI_WP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP3 field to a new value.
-#define BW_AIPS_PACRI_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRI, field SP3[18] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRI_SP3 (18U) //!< Bit position for AIPS_PACRI_SP3.
-#define BM_AIPS_PACRI_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRI_SP3.
-#define BS_AIPS_PACRI_SP3 (1U) //!< Bit field size in bits for AIPS_PACRI_SP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRI_SP3 field.
-#define BR_AIPS_PACRI_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRI_SP3.
-#define BF_AIPS_PACRI_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP3), uint32_t) & BM_AIPS_PACRI_SP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP3 field to a new value.
-#define BW_AIPS_PACRI_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRI, field TP2[20] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRI_TP2 (20U) //!< Bit position for AIPS_PACRI_TP2.
-#define BM_AIPS_PACRI_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRI_TP2.
-#define BS_AIPS_PACRI_TP2 (1U) //!< Bit field size in bits for AIPS_PACRI_TP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRI_TP2 field.
-#define BR_AIPS_PACRI_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRI_TP2.
-#define BF_AIPS_PACRI_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP2), uint32_t) & BM_AIPS_PACRI_TP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP2 field to a new value.
-#define BW_AIPS_PACRI_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRI, field WP2[21] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRI_WP2 (21U) //!< Bit position for AIPS_PACRI_WP2.
-#define BM_AIPS_PACRI_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRI_WP2.
-#define BS_AIPS_PACRI_WP2 (1U) //!< Bit field size in bits for AIPS_PACRI_WP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRI_WP2 field.
-#define BR_AIPS_PACRI_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRI_WP2.
-#define BF_AIPS_PACRI_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP2), uint32_t) & BM_AIPS_PACRI_WP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP2 field to a new value.
-#define BW_AIPS_PACRI_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRI, field SP2[22] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this bit is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
- * set. If not, access terminates with an error response and no peripheral access
- * initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRI_SP2 (22U) //!< Bit position for AIPS_PACRI_SP2.
-#define BM_AIPS_PACRI_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRI_SP2.
-#define BS_AIPS_PACRI_SP2 (1U) //!< Bit field size in bits for AIPS_PACRI_SP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRI_SP2 field.
-#define BR_AIPS_PACRI_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRI_SP2.
-#define BF_AIPS_PACRI_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP2), uint32_t) & BM_AIPS_PACRI_SP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP2 field to a new value.
-#define BW_AIPS_PACRI_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRI, field TP1[24] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRI_TP1 (24U) //!< Bit position for AIPS_PACRI_TP1.
-#define BM_AIPS_PACRI_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRI_TP1.
-#define BS_AIPS_PACRI_TP1 (1U) //!< Bit field size in bits for AIPS_PACRI_TP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRI_TP1 field.
-#define BR_AIPS_PACRI_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRI_TP1.
-#define BF_AIPS_PACRI_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP1), uint32_t) & BM_AIPS_PACRI_TP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP1 field to a new value.
-#define BW_AIPS_PACRI_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRI, field WP1[25] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRI_WP1 (25U) //!< Bit position for AIPS_PACRI_WP1.
-#define BM_AIPS_PACRI_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRI_WP1.
-#define BS_AIPS_PACRI_WP1 (1U) //!< Bit field size in bits for AIPS_PACRI_WP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRI_WP1 field.
-#define BR_AIPS_PACRI_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRI_WP1.
-#define BF_AIPS_PACRI_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP1), uint32_t) & BM_AIPS_PACRI_WP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP1 field to a new value.
-#define BW_AIPS_PACRI_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRI, field SP1[26] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master must
- * be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRI_SP1 (26U) //!< Bit position for AIPS_PACRI_SP1.
-#define BM_AIPS_PACRI_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRI_SP1.
-#define BS_AIPS_PACRI_SP1 (1U) //!< Bit field size in bits for AIPS_PACRI_SP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRI_SP1 field.
-#define BR_AIPS_PACRI_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRI_SP1.
-#define BF_AIPS_PACRI_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP1), uint32_t) & BM_AIPS_PACRI_SP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP1 field to a new value.
-#define BW_AIPS_PACRI_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRI, field TP0[28] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRI_TP0 (28U) //!< Bit position for AIPS_PACRI_TP0.
-#define BM_AIPS_PACRI_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRI_TP0.
-#define BS_AIPS_PACRI_TP0 (1U) //!< Bit field size in bits for AIPS_PACRI_TP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRI_TP0 field.
-#define BR_AIPS_PACRI_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRI_TP0.
-#define BF_AIPS_PACRI_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP0), uint32_t) & BM_AIPS_PACRI_TP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP0 field to a new value.
-#define BW_AIPS_PACRI_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRI, field WP0[29] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRI_WP0 (29U) //!< Bit position for AIPS_PACRI_WP0.
-#define BM_AIPS_PACRI_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRI_WP0.
-#define BS_AIPS_PACRI_WP0 (1U) //!< Bit field size in bits for AIPS_PACRI_WP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRI_WP0 field.
-#define BR_AIPS_PACRI_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRI_WP0.
-#define BF_AIPS_PACRI_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP0), uint32_t) & BM_AIPS_PACRI_WP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP0 field to a new value.
-#define BW_AIPS_PACRI_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRI, field SP0[30] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRI_SP0 (30U) //!< Bit position for AIPS_PACRI_SP0.
-#define BM_AIPS_PACRI_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRI_SP0.
-#define BS_AIPS_PACRI_SP0 (1U) //!< Bit field size in bits for AIPS_PACRI_SP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRI_SP0 field.
-#define BR_AIPS_PACRI_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRI_SP0.
-#define BF_AIPS_PACRI_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP0), uint32_t) & BM_AIPS_PACRI_SP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP0 field to a new value.
-#define BW_AIPS_PACRI_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP0) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_AIPS_PACRJ - Peripheral Access Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_AIPS_PACRJ - Peripheral Access Control Register (RW)
- *
- * Reset value: 0x44444444U
- *
- * This section describes PACR registers E-P, which control peripheral slots
- * 32-127. See PACRPeripheral Access Control Register for the description of these
- * registers.
- */
-typedef union _hw_aips_pacrj
-{
- uint32_t U;
- struct _hw_aips_pacrj_bitfields
- {
- uint32_t TP7 : 1; //!< [0] Trusted Protect
- uint32_t WP7 : 1; //!< [1] Write Protect
- uint32_t SP7 : 1; //!< [2] Supervisor Protect
- uint32_t RESERVED0 : 1; //!< [3]
- uint32_t TP6 : 1; //!< [4] Trusted Protect
- uint32_t WP6 : 1; //!< [5] Write Protect
- uint32_t SP6 : 1; //!< [6] Supervisor Protect
- uint32_t RESERVED1 : 1; //!< [7]
- uint32_t TP5 : 1; //!< [8] Trusted Protect
- uint32_t WP5 : 1; //!< [9] Write Protect
- uint32_t SP5 : 1; //!< [10] Supervisor Protect
- uint32_t RESERVED2 : 1; //!< [11]
- uint32_t TP4 : 1; //!< [12] Trusted Protect
- uint32_t WP4 : 1; //!< [13] Write Protect
- uint32_t SP4 : 1; //!< [14] Supervisor Protect
- uint32_t RESERVED3 : 1; //!< [15]
- uint32_t TP3 : 1; //!< [16] Trusted Protect
- uint32_t WP3 : 1; //!< [17] Write Protect
- uint32_t SP3 : 1; //!< [18] Supervisor Protect
- uint32_t RESERVED4 : 1; //!< [19]
- uint32_t TP2 : 1; //!< [20] Trusted Protect
- uint32_t WP2 : 1; //!< [21] Write Protect
- uint32_t SP2 : 1; //!< [22] Supervisor Protect
- uint32_t RESERVED5 : 1; //!< [23]
- uint32_t TP1 : 1; //!< [24] Trusted Protect
- uint32_t WP1 : 1; //!< [25] Write Protect
- uint32_t SP1 : 1; //!< [26] Supervisor Protect
- uint32_t RESERVED6 : 1; //!< [27]
- uint32_t TP0 : 1; //!< [28] Trusted Protect
- uint32_t WP0 : 1; //!< [29] Write Protect
- uint32_t SP0 : 1; //!< [30] Supervisor Protect
- uint32_t RESERVED7 : 1; //!< [31]
- } B;
-} hw_aips_pacrj_t;
-#endif
-
-/*!
- * @name Constants and macros for entire AIPS_PACRJ register
- */
-//@{
-#define HW_AIPS_PACRJ_ADDR(x) (REGS_AIPS_BASE(x) + 0x54U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_AIPS_PACRJ(x) (*(__IO hw_aips_pacrj_t *) HW_AIPS_PACRJ_ADDR(x))
-#define HW_AIPS_PACRJ_RD(x) (HW_AIPS_PACRJ(x).U)
-#define HW_AIPS_PACRJ_WR(x, v) (HW_AIPS_PACRJ(x).U = (v))
-#define HW_AIPS_PACRJ_SET(x, v) (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) | (v)))
-#define HW_AIPS_PACRJ_CLR(x, v) (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) & ~(v)))
-#define HW_AIPS_PACRJ_TOG(x, v) (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual AIPS_PACRJ bitfields
- */
-
-/*!
- * @name Register AIPS_PACRJ, field TP7[0] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRJ_TP7 (0U) //!< Bit position for AIPS_PACRJ_TP7.
-#define BM_AIPS_PACRJ_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRJ_TP7.
-#define BS_AIPS_PACRJ_TP7 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRJ_TP7 field.
-#define BR_AIPS_PACRJ_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRJ_TP7.
-#define BF_AIPS_PACRJ_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP7), uint32_t) & BM_AIPS_PACRJ_TP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP7 field to a new value.
-#define BW_AIPS_PACRJ_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRJ, field WP7[1] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRJ_WP7 (1U) //!< Bit position for AIPS_PACRJ_WP7.
-#define BM_AIPS_PACRJ_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRJ_WP7.
-#define BS_AIPS_PACRJ_WP7 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRJ_WP7 field.
-#define BR_AIPS_PACRJ_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRJ_WP7.
-#define BF_AIPS_PACRJ_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP7), uint32_t) & BM_AIPS_PACRJ_WP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP7 field to a new value.
-#define BW_AIPS_PACRJ_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRJ, field SP7[2] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRJ_SP7 (2U) //!< Bit position for AIPS_PACRJ_SP7.
-#define BM_AIPS_PACRJ_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRJ_SP7.
-#define BS_AIPS_PACRJ_SP7 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRJ_SP7 field.
-#define BR_AIPS_PACRJ_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRJ_SP7.
-#define BF_AIPS_PACRJ_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP7), uint32_t) & BM_AIPS_PACRJ_SP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP7 field to a new value.
-#define BW_AIPS_PACRJ_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRJ, field TP6[4] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRJ_TP6 (4U) //!< Bit position for AIPS_PACRJ_TP6.
-#define BM_AIPS_PACRJ_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRJ_TP6.
-#define BS_AIPS_PACRJ_TP6 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRJ_TP6 field.
-#define BR_AIPS_PACRJ_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRJ_TP6.
-#define BF_AIPS_PACRJ_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP6), uint32_t) & BM_AIPS_PACRJ_TP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP6 field to a new value.
-#define BW_AIPS_PACRJ_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRJ, field WP6[5] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRJ_WP6 (5U) //!< Bit position for AIPS_PACRJ_WP6.
-#define BM_AIPS_PACRJ_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRJ_WP6.
-#define BS_AIPS_PACRJ_WP6 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRJ_WP6 field.
-#define BR_AIPS_PACRJ_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRJ_WP6.
-#define BF_AIPS_PACRJ_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP6), uint32_t) & BM_AIPS_PACRJ_WP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP6 field to a new value.
-#define BW_AIPS_PACRJ_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRJ, field SP6[6] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRJ_SP6 (6U) //!< Bit position for AIPS_PACRJ_SP6.
-#define BM_AIPS_PACRJ_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRJ_SP6.
-#define BS_AIPS_PACRJ_SP6 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRJ_SP6 field.
-#define BR_AIPS_PACRJ_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRJ_SP6.
-#define BF_AIPS_PACRJ_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP6), uint32_t) & BM_AIPS_PACRJ_SP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP6 field to a new value.
-#define BW_AIPS_PACRJ_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRJ, field TP5[8] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRJ_TP5 (8U) //!< Bit position for AIPS_PACRJ_TP5.
-#define BM_AIPS_PACRJ_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRJ_TP5.
-#define BS_AIPS_PACRJ_TP5 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRJ_TP5 field.
-#define BR_AIPS_PACRJ_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRJ_TP5.
-#define BF_AIPS_PACRJ_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP5), uint32_t) & BM_AIPS_PACRJ_TP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP5 field to a new value.
-#define BW_AIPS_PACRJ_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRJ, field WP5[9] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRJ_WP5 (9U) //!< Bit position for AIPS_PACRJ_WP5.
-#define BM_AIPS_PACRJ_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRJ_WP5.
-#define BS_AIPS_PACRJ_WP5 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRJ_WP5 field.
-#define BR_AIPS_PACRJ_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRJ_WP5.
-#define BF_AIPS_PACRJ_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP5), uint32_t) & BM_AIPS_PACRJ_WP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP5 field to a new value.
-#define BW_AIPS_PACRJ_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRJ, field SP5[10] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRJ_SP5 (10U) //!< Bit position for AIPS_PACRJ_SP5.
-#define BM_AIPS_PACRJ_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRJ_SP5.
-#define BS_AIPS_PACRJ_SP5 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRJ_SP5 field.
-#define BR_AIPS_PACRJ_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRJ_SP5.
-#define BF_AIPS_PACRJ_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP5), uint32_t) & BM_AIPS_PACRJ_SP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP5 field to a new value.
-#define BW_AIPS_PACRJ_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRJ, field TP4[12] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRJ_TP4 (12U) //!< Bit position for AIPS_PACRJ_TP4.
-#define BM_AIPS_PACRJ_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRJ_TP4.
-#define BS_AIPS_PACRJ_TP4 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRJ_TP4 field.
-#define BR_AIPS_PACRJ_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRJ_TP4.
-#define BF_AIPS_PACRJ_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP4), uint32_t) & BM_AIPS_PACRJ_TP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP4 field to a new value.
-#define BW_AIPS_PACRJ_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRJ, field WP4[13] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRJ_WP4 (13U) //!< Bit position for AIPS_PACRJ_WP4.
-#define BM_AIPS_PACRJ_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRJ_WP4.
-#define BS_AIPS_PACRJ_WP4 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRJ_WP4 field.
-#define BR_AIPS_PACRJ_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRJ_WP4.
-#define BF_AIPS_PACRJ_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP4), uint32_t) & BM_AIPS_PACRJ_WP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP4 field to a new value.
-#define BW_AIPS_PACRJ_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRJ, field SP4[14] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this bit is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
- * set. If not, access terminates with an error response and no peripheral access
- * initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRJ_SP4 (14U) //!< Bit position for AIPS_PACRJ_SP4.
-#define BM_AIPS_PACRJ_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRJ_SP4.
-#define BS_AIPS_PACRJ_SP4 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRJ_SP4 field.
-#define BR_AIPS_PACRJ_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRJ_SP4.
-#define BF_AIPS_PACRJ_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP4), uint32_t) & BM_AIPS_PACRJ_SP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP4 field to a new value.
-#define BW_AIPS_PACRJ_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRJ, field TP3[16] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRJ_TP3 (16U) //!< Bit position for AIPS_PACRJ_TP3.
-#define BM_AIPS_PACRJ_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRJ_TP3.
-#define BS_AIPS_PACRJ_TP3 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRJ_TP3 field.
-#define BR_AIPS_PACRJ_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRJ_TP3.
-#define BF_AIPS_PACRJ_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP3), uint32_t) & BM_AIPS_PACRJ_TP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP3 field to a new value.
-#define BW_AIPS_PACRJ_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRJ, field WP3[17] (RW)
- *
- * Determines whether the peripheral allows write accesss. When this bit is set
- * and a write access is attempted, access terminates with an error response and
- * no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRJ_WP3 (17U) //!< Bit position for AIPS_PACRJ_WP3.
-#define BM_AIPS_PACRJ_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRJ_WP3.
-#define BS_AIPS_PACRJ_WP3 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRJ_WP3 field.
-#define BR_AIPS_PACRJ_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRJ_WP3.
-#define BF_AIPS_PACRJ_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP3), uint32_t) & BM_AIPS_PACRJ_WP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP3 field to a new value.
-#define BW_AIPS_PACRJ_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRJ, field SP3[18] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRJ_SP3 (18U) //!< Bit position for AIPS_PACRJ_SP3.
-#define BM_AIPS_PACRJ_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRJ_SP3.
-#define BS_AIPS_PACRJ_SP3 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRJ_SP3 field.
-#define BR_AIPS_PACRJ_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRJ_SP3.
-#define BF_AIPS_PACRJ_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP3), uint32_t) & BM_AIPS_PACRJ_SP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP3 field to a new value.
-#define BW_AIPS_PACRJ_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRJ, field TP2[20] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRJ_TP2 (20U) //!< Bit position for AIPS_PACRJ_TP2.
-#define BM_AIPS_PACRJ_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRJ_TP2.
-#define BS_AIPS_PACRJ_TP2 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRJ_TP2 field.
-#define BR_AIPS_PACRJ_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRJ_TP2.
-#define BF_AIPS_PACRJ_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP2), uint32_t) & BM_AIPS_PACRJ_TP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP2 field to a new value.
-#define BW_AIPS_PACRJ_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRJ, field WP2[21] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRJ_WP2 (21U) //!< Bit position for AIPS_PACRJ_WP2.
-#define BM_AIPS_PACRJ_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRJ_WP2.
-#define BS_AIPS_PACRJ_WP2 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRJ_WP2 field.
-#define BR_AIPS_PACRJ_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRJ_WP2.
-#define BF_AIPS_PACRJ_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP2), uint32_t) & BM_AIPS_PACRJ_WP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP2 field to a new value.
-#define BW_AIPS_PACRJ_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRJ, field SP2[22] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this bit is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
- * set. If not, access terminates with an error response and no peripheral access
- * initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRJ_SP2 (22U) //!< Bit position for AIPS_PACRJ_SP2.
-#define BM_AIPS_PACRJ_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRJ_SP2.
-#define BS_AIPS_PACRJ_SP2 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRJ_SP2 field.
-#define BR_AIPS_PACRJ_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRJ_SP2.
-#define BF_AIPS_PACRJ_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP2), uint32_t) & BM_AIPS_PACRJ_SP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP2 field to a new value.
-#define BW_AIPS_PACRJ_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRJ, field TP1[24] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRJ_TP1 (24U) //!< Bit position for AIPS_PACRJ_TP1.
-#define BM_AIPS_PACRJ_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRJ_TP1.
-#define BS_AIPS_PACRJ_TP1 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRJ_TP1 field.
-#define BR_AIPS_PACRJ_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRJ_TP1.
-#define BF_AIPS_PACRJ_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP1), uint32_t) & BM_AIPS_PACRJ_TP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP1 field to a new value.
-#define BW_AIPS_PACRJ_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRJ, field WP1[25] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRJ_WP1 (25U) //!< Bit position for AIPS_PACRJ_WP1.
-#define BM_AIPS_PACRJ_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRJ_WP1.
-#define BS_AIPS_PACRJ_WP1 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRJ_WP1 field.
-#define BR_AIPS_PACRJ_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRJ_WP1.
-#define BF_AIPS_PACRJ_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP1), uint32_t) & BM_AIPS_PACRJ_WP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP1 field to a new value.
-#define BW_AIPS_PACRJ_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRJ, field SP1[26] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master must
- * be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRJ_SP1 (26U) //!< Bit position for AIPS_PACRJ_SP1.
-#define BM_AIPS_PACRJ_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRJ_SP1.
-#define BS_AIPS_PACRJ_SP1 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRJ_SP1 field.
-#define BR_AIPS_PACRJ_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRJ_SP1.
-#define BF_AIPS_PACRJ_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP1), uint32_t) & BM_AIPS_PACRJ_SP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP1 field to a new value.
-#define BW_AIPS_PACRJ_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRJ, field TP0[28] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRJ_TP0 (28U) //!< Bit position for AIPS_PACRJ_TP0.
-#define BM_AIPS_PACRJ_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRJ_TP0.
-#define BS_AIPS_PACRJ_TP0 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRJ_TP0 field.
-#define BR_AIPS_PACRJ_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRJ_TP0.
-#define BF_AIPS_PACRJ_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP0), uint32_t) & BM_AIPS_PACRJ_TP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP0 field to a new value.
-#define BW_AIPS_PACRJ_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRJ, field WP0[29] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRJ_WP0 (29U) //!< Bit position for AIPS_PACRJ_WP0.
-#define BM_AIPS_PACRJ_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRJ_WP0.
-#define BS_AIPS_PACRJ_WP0 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRJ_WP0 field.
-#define BR_AIPS_PACRJ_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRJ_WP0.
-#define BF_AIPS_PACRJ_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP0), uint32_t) & BM_AIPS_PACRJ_WP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP0 field to a new value.
-#define BW_AIPS_PACRJ_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRJ, field SP0[30] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRJ_SP0 (30U) //!< Bit position for AIPS_PACRJ_SP0.
-#define BM_AIPS_PACRJ_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRJ_SP0.
-#define BS_AIPS_PACRJ_SP0 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRJ_SP0 field.
-#define BR_AIPS_PACRJ_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRJ_SP0.
-#define BF_AIPS_PACRJ_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP0), uint32_t) & BM_AIPS_PACRJ_SP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP0 field to a new value.
-#define BW_AIPS_PACRJ_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP0) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_AIPS_PACRK - Peripheral Access Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_AIPS_PACRK - Peripheral Access Control Register (RW)
- *
- * Reset value: 0x44444444U
- *
- * This section describes PACR registers E-P, which control peripheral slots
- * 32-127. See PACRPeripheral Access Control Register for the description of these
- * registers.
- */
-typedef union _hw_aips_pacrk
-{
- uint32_t U;
- struct _hw_aips_pacrk_bitfields
- {
- uint32_t TP7 : 1; //!< [0] Trusted Protect
- uint32_t WP7 : 1; //!< [1] Write Protect
- uint32_t SP7 : 1; //!< [2] Supervisor Protect
- uint32_t RESERVED0 : 1; //!< [3]
- uint32_t TP6 : 1; //!< [4] Trusted Protect
- uint32_t WP6 : 1; //!< [5] Write Protect
- uint32_t SP6 : 1; //!< [6] Supervisor Protect
- uint32_t RESERVED1 : 1; //!< [7]
- uint32_t TP5 : 1; //!< [8] Trusted Protect
- uint32_t WP5 : 1; //!< [9] Write Protect
- uint32_t SP5 : 1; //!< [10] Supervisor Protect
- uint32_t RESERVED2 : 1; //!< [11]
- uint32_t TP4 : 1; //!< [12] Trusted Protect
- uint32_t WP4 : 1; //!< [13] Write Protect
- uint32_t SP4 : 1; //!< [14] Supervisor Protect
- uint32_t RESERVED3 : 1; //!< [15]
- uint32_t TP3 : 1; //!< [16] Trusted Protect
- uint32_t WP3 : 1; //!< [17] Write Protect
- uint32_t SP3 : 1; //!< [18] Supervisor Protect
- uint32_t RESERVED4 : 1; //!< [19]
- uint32_t TP2 : 1; //!< [20] Trusted Protect
- uint32_t WP2 : 1; //!< [21] Write Protect
- uint32_t SP2 : 1; //!< [22] Supervisor Protect
- uint32_t RESERVED5 : 1; //!< [23]
- uint32_t TP1 : 1; //!< [24] Trusted Protect
- uint32_t WP1 : 1; //!< [25] Write Protect
- uint32_t SP1 : 1; //!< [26] Supervisor Protect
- uint32_t RESERVED6 : 1; //!< [27]
- uint32_t TP0 : 1; //!< [28] Trusted Protect
- uint32_t WP0 : 1; //!< [29] Write Protect
- uint32_t SP0 : 1; //!< [30] Supervisor Protect
- uint32_t RESERVED7 : 1; //!< [31]
- } B;
-} hw_aips_pacrk_t;
-#endif
-
-/*!
- * @name Constants and macros for entire AIPS_PACRK register
- */
-//@{
-#define HW_AIPS_PACRK_ADDR(x) (REGS_AIPS_BASE(x) + 0x58U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_AIPS_PACRK(x) (*(__IO hw_aips_pacrk_t *) HW_AIPS_PACRK_ADDR(x))
-#define HW_AIPS_PACRK_RD(x) (HW_AIPS_PACRK(x).U)
-#define HW_AIPS_PACRK_WR(x, v) (HW_AIPS_PACRK(x).U = (v))
-#define HW_AIPS_PACRK_SET(x, v) (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) | (v)))
-#define HW_AIPS_PACRK_CLR(x, v) (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) & ~(v)))
-#define HW_AIPS_PACRK_TOG(x, v) (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual AIPS_PACRK bitfields
- */
-
-/*!
- * @name Register AIPS_PACRK, field TP7[0] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRK_TP7 (0U) //!< Bit position for AIPS_PACRK_TP7.
-#define BM_AIPS_PACRK_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRK_TP7.
-#define BS_AIPS_PACRK_TP7 (1U) //!< Bit field size in bits for AIPS_PACRK_TP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRK_TP7 field.
-#define BR_AIPS_PACRK_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRK_TP7.
-#define BF_AIPS_PACRK_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP7), uint32_t) & BM_AIPS_PACRK_TP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP7 field to a new value.
-#define BW_AIPS_PACRK_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRK, field WP7[1] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRK_WP7 (1U) //!< Bit position for AIPS_PACRK_WP7.
-#define BM_AIPS_PACRK_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRK_WP7.
-#define BS_AIPS_PACRK_WP7 (1U) //!< Bit field size in bits for AIPS_PACRK_WP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRK_WP7 field.
-#define BR_AIPS_PACRK_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRK_WP7.
-#define BF_AIPS_PACRK_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP7), uint32_t) & BM_AIPS_PACRK_WP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP7 field to a new value.
-#define BW_AIPS_PACRK_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRK, field SP7[2] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRK_SP7 (2U) //!< Bit position for AIPS_PACRK_SP7.
-#define BM_AIPS_PACRK_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRK_SP7.
-#define BS_AIPS_PACRK_SP7 (1U) //!< Bit field size in bits for AIPS_PACRK_SP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRK_SP7 field.
-#define BR_AIPS_PACRK_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRK_SP7.
-#define BF_AIPS_PACRK_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP7), uint32_t) & BM_AIPS_PACRK_SP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP7 field to a new value.
-#define BW_AIPS_PACRK_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRK, field TP6[4] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRK_TP6 (4U) //!< Bit position for AIPS_PACRK_TP6.
-#define BM_AIPS_PACRK_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRK_TP6.
-#define BS_AIPS_PACRK_TP6 (1U) //!< Bit field size in bits for AIPS_PACRK_TP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRK_TP6 field.
-#define BR_AIPS_PACRK_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRK_TP6.
-#define BF_AIPS_PACRK_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP6), uint32_t) & BM_AIPS_PACRK_TP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP6 field to a new value.
-#define BW_AIPS_PACRK_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRK, field WP6[5] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRK_WP6 (5U) //!< Bit position for AIPS_PACRK_WP6.
-#define BM_AIPS_PACRK_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRK_WP6.
-#define BS_AIPS_PACRK_WP6 (1U) //!< Bit field size in bits for AIPS_PACRK_WP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRK_WP6 field.
-#define BR_AIPS_PACRK_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRK_WP6.
-#define BF_AIPS_PACRK_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP6), uint32_t) & BM_AIPS_PACRK_WP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP6 field to a new value.
-#define BW_AIPS_PACRK_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRK, field SP6[6] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRK_SP6 (6U) //!< Bit position for AIPS_PACRK_SP6.
-#define BM_AIPS_PACRK_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRK_SP6.
-#define BS_AIPS_PACRK_SP6 (1U) //!< Bit field size in bits for AIPS_PACRK_SP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRK_SP6 field.
-#define BR_AIPS_PACRK_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRK_SP6.
-#define BF_AIPS_PACRK_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP6), uint32_t) & BM_AIPS_PACRK_SP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP6 field to a new value.
-#define BW_AIPS_PACRK_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRK, field TP5[8] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRK_TP5 (8U) //!< Bit position for AIPS_PACRK_TP5.
-#define BM_AIPS_PACRK_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRK_TP5.
-#define BS_AIPS_PACRK_TP5 (1U) //!< Bit field size in bits for AIPS_PACRK_TP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRK_TP5 field.
-#define BR_AIPS_PACRK_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRK_TP5.
-#define BF_AIPS_PACRK_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP5), uint32_t) & BM_AIPS_PACRK_TP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP5 field to a new value.
-#define BW_AIPS_PACRK_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRK, field WP5[9] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRK_WP5 (9U) //!< Bit position for AIPS_PACRK_WP5.
-#define BM_AIPS_PACRK_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRK_WP5.
-#define BS_AIPS_PACRK_WP5 (1U) //!< Bit field size in bits for AIPS_PACRK_WP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRK_WP5 field.
-#define BR_AIPS_PACRK_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRK_WP5.
-#define BF_AIPS_PACRK_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP5), uint32_t) & BM_AIPS_PACRK_WP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP5 field to a new value.
-#define BW_AIPS_PACRK_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRK, field SP5[10] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRK_SP5 (10U) //!< Bit position for AIPS_PACRK_SP5.
-#define BM_AIPS_PACRK_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRK_SP5.
-#define BS_AIPS_PACRK_SP5 (1U) //!< Bit field size in bits for AIPS_PACRK_SP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRK_SP5 field.
-#define BR_AIPS_PACRK_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRK_SP5.
-#define BF_AIPS_PACRK_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP5), uint32_t) & BM_AIPS_PACRK_SP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP5 field to a new value.
-#define BW_AIPS_PACRK_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRK, field TP4[12] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRK_TP4 (12U) //!< Bit position for AIPS_PACRK_TP4.
-#define BM_AIPS_PACRK_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRK_TP4.
-#define BS_AIPS_PACRK_TP4 (1U) //!< Bit field size in bits for AIPS_PACRK_TP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRK_TP4 field.
-#define BR_AIPS_PACRK_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRK_TP4.
-#define BF_AIPS_PACRK_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP4), uint32_t) & BM_AIPS_PACRK_TP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP4 field to a new value.
-#define BW_AIPS_PACRK_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRK, field WP4[13] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRK_WP4 (13U) //!< Bit position for AIPS_PACRK_WP4.
-#define BM_AIPS_PACRK_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRK_WP4.
-#define BS_AIPS_PACRK_WP4 (1U) //!< Bit field size in bits for AIPS_PACRK_WP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRK_WP4 field.
-#define BR_AIPS_PACRK_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRK_WP4.
-#define BF_AIPS_PACRK_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP4), uint32_t) & BM_AIPS_PACRK_WP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP4 field to a new value.
-#define BW_AIPS_PACRK_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRK, field SP4[14] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this bit is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
- * set. If not, access terminates with an error response and no peripheral access
- * initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRK_SP4 (14U) //!< Bit position for AIPS_PACRK_SP4.
-#define BM_AIPS_PACRK_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRK_SP4.
-#define BS_AIPS_PACRK_SP4 (1U) //!< Bit field size in bits for AIPS_PACRK_SP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRK_SP4 field.
-#define BR_AIPS_PACRK_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRK_SP4.
-#define BF_AIPS_PACRK_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP4), uint32_t) & BM_AIPS_PACRK_SP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP4 field to a new value.
-#define BW_AIPS_PACRK_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRK, field TP3[16] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRK_TP3 (16U) //!< Bit position for AIPS_PACRK_TP3.
-#define BM_AIPS_PACRK_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRK_TP3.
-#define BS_AIPS_PACRK_TP3 (1U) //!< Bit field size in bits for AIPS_PACRK_TP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRK_TP3 field.
-#define BR_AIPS_PACRK_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRK_TP3.
-#define BF_AIPS_PACRK_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP3), uint32_t) & BM_AIPS_PACRK_TP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP3 field to a new value.
-#define BW_AIPS_PACRK_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRK, field WP3[17] (RW)
- *
- * Determines whether the peripheral allows write accesss. When this bit is set
- * and a write access is attempted, access terminates with an error response and
- * no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRK_WP3 (17U) //!< Bit position for AIPS_PACRK_WP3.
-#define BM_AIPS_PACRK_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRK_WP3.
-#define BS_AIPS_PACRK_WP3 (1U) //!< Bit field size in bits for AIPS_PACRK_WP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRK_WP3 field.
-#define BR_AIPS_PACRK_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRK_WP3.
-#define BF_AIPS_PACRK_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP3), uint32_t) & BM_AIPS_PACRK_WP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP3 field to a new value.
-#define BW_AIPS_PACRK_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRK, field SP3[18] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRK_SP3 (18U) //!< Bit position for AIPS_PACRK_SP3.
-#define BM_AIPS_PACRK_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRK_SP3.
-#define BS_AIPS_PACRK_SP3 (1U) //!< Bit field size in bits for AIPS_PACRK_SP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRK_SP3 field.
-#define BR_AIPS_PACRK_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRK_SP3.
-#define BF_AIPS_PACRK_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP3), uint32_t) & BM_AIPS_PACRK_SP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP3 field to a new value.
-#define BW_AIPS_PACRK_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRK, field TP2[20] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRK_TP2 (20U) //!< Bit position for AIPS_PACRK_TP2.
-#define BM_AIPS_PACRK_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRK_TP2.
-#define BS_AIPS_PACRK_TP2 (1U) //!< Bit field size in bits for AIPS_PACRK_TP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRK_TP2 field.
-#define BR_AIPS_PACRK_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRK_TP2.
-#define BF_AIPS_PACRK_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP2), uint32_t) & BM_AIPS_PACRK_TP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP2 field to a new value.
-#define BW_AIPS_PACRK_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRK, field WP2[21] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRK_WP2 (21U) //!< Bit position for AIPS_PACRK_WP2.
-#define BM_AIPS_PACRK_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRK_WP2.
-#define BS_AIPS_PACRK_WP2 (1U) //!< Bit field size in bits for AIPS_PACRK_WP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRK_WP2 field.
-#define BR_AIPS_PACRK_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRK_WP2.
-#define BF_AIPS_PACRK_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP2), uint32_t) & BM_AIPS_PACRK_WP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP2 field to a new value.
-#define BW_AIPS_PACRK_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRK, field SP2[22] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this bit is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
- * set. If not, access terminates with an error response and no peripheral access
- * initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRK_SP2 (22U) //!< Bit position for AIPS_PACRK_SP2.
-#define BM_AIPS_PACRK_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRK_SP2.
-#define BS_AIPS_PACRK_SP2 (1U) //!< Bit field size in bits for AIPS_PACRK_SP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRK_SP2 field.
-#define BR_AIPS_PACRK_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRK_SP2.
-#define BF_AIPS_PACRK_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP2), uint32_t) & BM_AIPS_PACRK_SP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP2 field to a new value.
-#define BW_AIPS_PACRK_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRK, field TP1[24] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRK_TP1 (24U) //!< Bit position for AIPS_PACRK_TP1.
-#define BM_AIPS_PACRK_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRK_TP1.
-#define BS_AIPS_PACRK_TP1 (1U) //!< Bit field size in bits for AIPS_PACRK_TP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRK_TP1 field.
-#define BR_AIPS_PACRK_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRK_TP1.
-#define BF_AIPS_PACRK_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP1), uint32_t) & BM_AIPS_PACRK_TP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP1 field to a new value.
-#define BW_AIPS_PACRK_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRK, field WP1[25] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRK_WP1 (25U) //!< Bit position for AIPS_PACRK_WP1.
-#define BM_AIPS_PACRK_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRK_WP1.
-#define BS_AIPS_PACRK_WP1 (1U) //!< Bit field size in bits for AIPS_PACRK_WP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRK_WP1 field.
-#define BR_AIPS_PACRK_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRK_WP1.
-#define BF_AIPS_PACRK_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP1), uint32_t) & BM_AIPS_PACRK_WP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP1 field to a new value.
-#define BW_AIPS_PACRK_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRK, field SP1[26] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master must
- * be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRK_SP1 (26U) //!< Bit position for AIPS_PACRK_SP1.
-#define BM_AIPS_PACRK_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRK_SP1.
-#define BS_AIPS_PACRK_SP1 (1U) //!< Bit field size in bits for AIPS_PACRK_SP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRK_SP1 field.
-#define BR_AIPS_PACRK_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRK_SP1.
-#define BF_AIPS_PACRK_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP1), uint32_t) & BM_AIPS_PACRK_SP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP1 field to a new value.
-#define BW_AIPS_PACRK_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRK, field TP0[28] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRK_TP0 (28U) //!< Bit position for AIPS_PACRK_TP0.
-#define BM_AIPS_PACRK_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRK_TP0.
-#define BS_AIPS_PACRK_TP0 (1U) //!< Bit field size in bits for AIPS_PACRK_TP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRK_TP0 field.
-#define BR_AIPS_PACRK_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRK_TP0.
-#define BF_AIPS_PACRK_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP0), uint32_t) & BM_AIPS_PACRK_TP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP0 field to a new value.
-#define BW_AIPS_PACRK_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRK, field WP0[29] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRK_WP0 (29U) //!< Bit position for AIPS_PACRK_WP0.
-#define BM_AIPS_PACRK_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRK_WP0.
-#define BS_AIPS_PACRK_WP0 (1U) //!< Bit field size in bits for AIPS_PACRK_WP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRK_WP0 field.
-#define BR_AIPS_PACRK_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRK_WP0.
-#define BF_AIPS_PACRK_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP0), uint32_t) & BM_AIPS_PACRK_WP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP0 field to a new value.
-#define BW_AIPS_PACRK_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRK, field SP0[30] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRK_SP0 (30U) //!< Bit position for AIPS_PACRK_SP0.
-#define BM_AIPS_PACRK_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRK_SP0.
-#define BS_AIPS_PACRK_SP0 (1U) //!< Bit field size in bits for AIPS_PACRK_SP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRK_SP0 field.
-#define BR_AIPS_PACRK_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRK_SP0.
-#define BF_AIPS_PACRK_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP0), uint32_t) & BM_AIPS_PACRK_SP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP0 field to a new value.
-#define BW_AIPS_PACRK_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP0) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_AIPS_PACRL - Peripheral Access Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_AIPS_PACRL - Peripheral Access Control Register (RW)
- *
- * Reset value: 0x44444444U
- *
- * This section describes PACR registers E-P, which control peripheral slots
- * 32-127. See PACRPeripheral Access Control Register for the description of these
- * registers.
- */
-typedef union _hw_aips_pacrl
-{
- uint32_t U;
- struct _hw_aips_pacrl_bitfields
- {
- uint32_t TP7 : 1; //!< [0] Trusted Protect
- uint32_t WP7 : 1; //!< [1] Write Protect
- uint32_t SP7 : 1; //!< [2] Supervisor Protect
- uint32_t RESERVED0 : 1; //!< [3]
- uint32_t TP6 : 1; //!< [4] Trusted Protect
- uint32_t WP6 : 1; //!< [5] Write Protect
- uint32_t SP6 : 1; //!< [6] Supervisor Protect
- uint32_t RESERVED1 : 1; //!< [7]
- uint32_t TP5 : 1; //!< [8] Trusted Protect
- uint32_t WP5 : 1; //!< [9] Write Protect
- uint32_t SP5 : 1; //!< [10] Supervisor Protect
- uint32_t RESERVED2 : 1; //!< [11]
- uint32_t TP4 : 1; //!< [12] Trusted Protect
- uint32_t WP4 : 1; //!< [13] Write Protect
- uint32_t SP4 : 1; //!< [14] Supervisor Protect
- uint32_t RESERVED3 : 1; //!< [15]
- uint32_t TP3 : 1; //!< [16] Trusted Protect
- uint32_t WP3 : 1; //!< [17] Write Protect
- uint32_t SP3 : 1; //!< [18] Supervisor Protect
- uint32_t RESERVED4 : 1; //!< [19]
- uint32_t TP2 : 1; //!< [20] Trusted Protect
- uint32_t WP2 : 1; //!< [21] Write Protect
- uint32_t SP2 : 1; //!< [22] Supervisor Protect
- uint32_t RESERVED5 : 1; //!< [23]
- uint32_t TP1 : 1; //!< [24] Trusted Protect
- uint32_t WP1 : 1; //!< [25] Write Protect
- uint32_t SP1 : 1; //!< [26] Supervisor Protect
- uint32_t RESERVED6 : 1; //!< [27]
- uint32_t TP0 : 1; //!< [28] Trusted Protect
- uint32_t WP0 : 1; //!< [29] Write Protect
- uint32_t SP0 : 1; //!< [30] Supervisor Protect
- uint32_t RESERVED7 : 1; //!< [31]
- } B;
-} hw_aips_pacrl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire AIPS_PACRL register
- */
-//@{
-#define HW_AIPS_PACRL_ADDR(x) (REGS_AIPS_BASE(x) + 0x5CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_AIPS_PACRL(x) (*(__IO hw_aips_pacrl_t *) HW_AIPS_PACRL_ADDR(x))
-#define HW_AIPS_PACRL_RD(x) (HW_AIPS_PACRL(x).U)
-#define HW_AIPS_PACRL_WR(x, v) (HW_AIPS_PACRL(x).U = (v))
-#define HW_AIPS_PACRL_SET(x, v) (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) | (v)))
-#define HW_AIPS_PACRL_CLR(x, v) (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) & ~(v)))
-#define HW_AIPS_PACRL_TOG(x, v) (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual AIPS_PACRL bitfields
- */
-
-/*!
- * @name Register AIPS_PACRL, field TP7[0] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRL_TP7 (0U) //!< Bit position for AIPS_PACRL_TP7.
-#define BM_AIPS_PACRL_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRL_TP7.
-#define BS_AIPS_PACRL_TP7 (1U) //!< Bit field size in bits for AIPS_PACRL_TP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRL_TP7 field.
-#define BR_AIPS_PACRL_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRL_TP7.
-#define BF_AIPS_PACRL_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP7), uint32_t) & BM_AIPS_PACRL_TP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP7 field to a new value.
-#define BW_AIPS_PACRL_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRL, field WP7[1] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRL_WP7 (1U) //!< Bit position for AIPS_PACRL_WP7.
-#define BM_AIPS_PACRL_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRL_WP7.
-#define BS_AIPS_PACRL_WP7 (1U) //!< Bit field size in bits for AIPS_PACRL_WP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRL_WP7 field.
-#define BR_AIPS_PACRL_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRL_WP7.
-#define BF_AIPS_PACRL_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP7), uint32_t) & BM_AIPS_PACRL_WP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP7 field to a new value.
-#define BW_AIPS_PACRL_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRL, field SP7[2] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRL_SP7 (2U) //!< Bit position for AIPS_PACRL_SP7.
-#define BM_AIPS_PACRL_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRL_SP7.
-#define BS_AIPS_PACRL_SP7 (1U) //!< Bit field size in bits for AIPS_PACRL_SP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRL_SP7 field.
-#define BR_AIPS_PACRL_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRL_SP7.
-#define BF_AIPS_PACRL_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP7), uint32_t) & BM_AIPS_PACRL_SP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP7 field to a new value.
-#define BW_AIPS_PACRL_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRL, field TP6[4] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRL_TP6 (4U) //!< Bit position for AIPS_PACRL_TP6.
-#define BM_AIPS_PACRL_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRL_TP6.
-#define BS_AIPS_PACRL_TP6 (1U) //!< Bit field size in bits for AIPS_PACRL_TP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRL_TP6 field.
-#define BR_AIPS_PACRL_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRL_TP6.
-#define BF_AIPS_PACRL_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP6), uint32_t) & BM_AIPS_PACRL_TP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP6 field to a new value.
-#define BW_AIPS_PACRL_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRL, field WP6[5] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRL_WP6 (5U) //!< Bit position for AIPS_PACRL_WP6.
-#define BM_AIPS_PACRL_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRL_WP6.
-#define BS_AIPS_PACRL_WP6 (1U) //!< Bit field size in bits for AIPS_PACRL_WP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRL_WP6 field.
-#define BR_AIPS_PACRL_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRL_WP6.
-#define BF_AIPS_PACRL_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP6), uint32_t) & BM_AIPS_PACRL_WP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP6 field to a new value.
-#define BW_AIPS_PACRL_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRL, field SP6[6] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRL_SP6 (6U) //!< Bit position for AIPS_PACRL_SP6.
-#define BM_AIPS_PACRL_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRL_SP6.
-#define BS_AIPS_PACRL_SP6 (1U) //!< Bit field size in bits for AIPS_PACRL_SP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRL_SP6 field.
-#define BR_AIPS_PACRL_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRL_SP6.
-#define BF_AIPS_PACRL_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP6), uint32_t) & BM_AIPS_PACRL_SP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP6 field to a new value.
-#define BW_AIPS_PACRL_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRL, field TP5[8] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRL_TP5 (8U) //!< Bit position for AIPS_PACRL_TP5.
-#define BM_AIPS_PACRL_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRL_TP5.
-#define BS_AIPS_PACRL_TP5 (1U) //!< Bit field size in bits for AIPS_PACRL_TP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRL_TP5 field.
-#define BR_AIPS_PACRL_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRL_TP5.
-#define BF_AIPS_PACRL_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP5), uint32_t) & BM_AIPS_PACRL_TP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP5 field to a new value.
-#define BW_AIPS_PACRL_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRL, field WP5[9] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRL_WP5 (9U) //!< Bit position for AIPS_PACRL_WP5.
-#define BM_AIPS_PACRL_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRL_WP5.
-#define BS_AIPS_PACRL_WP5 (1U) //!< Bit field size in bits for AIPS_PACRL_WP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRL_WP5 field.
-#define BR_AIPS_PACRL_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRL_WP5.
-#define BF_AIPS_PACRL_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP5), uint32_t) & BM_AIPS_PACRL_WP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP5 field to a new value.
-#define BW_AIPS_PACRL_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRL, field SP5[10] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRL_SP5 (10U) //!< Bit position for AIPS_PACRL_SP5.
-#define BM_AIPS_PACRL_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRL_SP5.
-#define BS_AIPS_PACRL_SP5 (1U) //!< Bit field size in bits for AIPS_PACRL_SP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRL_SP5 field.
-#define BR_AIPS_PACRL_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRL_SP5.
-#define BF_AIPS_PACRL_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP5), uint32_t) & BM_AIPS_PACRL_SP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP5 field to a new value.
-#define BW_AIPS_PACRL_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRL, field TP4[12] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRL_TP4 (12U) //!< Bit position for AIPS_PACRL_TP4.
-#define BM_AIPS_PACRL_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRL_TP4.
-#define BS_AIPS_PACRL_TP4 (1U) //!< Bit field size in bits for AIPS_PACRL_TP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRL_TP4 field.
-#define BR_AIPS_PACRL_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRL_TP4.
-#define BF_AIPS_PACRL_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP4), uint32_t) & BM_AIPS_PACRL_TP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP4 field to a new value.
-#define BW_AIPS_PACRL_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRL, field WP4[13] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRL_WP4 (13U) //!< Bit position for AIPS_PACRL_WP4.
-#define BM_AIPS_PACRL_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRL_WP4.
-#define BS_AIPS_PACRL_WP4 (1U) //!< Bit field size in bits for AIPS_PACRL_WP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRL_WP4 field.
-#define BR_AIPS_PACRL_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRL_WP4.
-#define BF_AIPS_PACRL_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP4), uint32_t) & BM_AIPS_PACRL_WP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP4 field to a new value.
-#define BW_AIPS_PACRL_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRL, field SP4[14] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this bit is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
- * set. If not, access terminates with an error response and no peripheral access
- * initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRL_SP4 (14U) //!< Bit position for AIPS_PACRL_SP4.
-#define BM_AIPS_PACRL_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRL_SP4.
-#define BS_AIPS_PACRL_SP4 (1U) //!< Bit field size in bits for AIPS_PACRL_SP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRL_SP4 field.
-#define BR_AIPS_PACRL_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRL_SP4.
-#define BF_AIPS_PACRL_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP4), uint32_t) & BM_AIPS_PACRL_SP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP4 field to a new value.
-#define BW_AIPS_PACRL_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRL, field TP3[16] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRL_TP3 (16U) //!< Bit position for AIPS_PACRL_TP3.
-#define BM_AIPS_PACRL_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRL_TP3.
-#define BS_AIPS_PACRL_TP3 (1U) //!< Bit field size in bits for AIPS_PACRL_TP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRL_TP3 field.
-#define BR_AIPS_PACRL_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRL_TP3.
-#define BF_AIPS_PACRL_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP3), uint32_t) & BM_AIPS_PACRL_TP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP3 field to a new value.
-#define BW_AIPS_PACRL_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRL, field WP3[17] (RW)
- *
- * Determines whether the peripheral allows write accesss. When this bit is set
- * and a write access is attempted, access terminates with an error response and
- * no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRL_WP3 (17U) //!< Bit position for AIPS_PACRL_WP3.
-#define BM_AIPS_PACRL_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRL_WP3.
-#define BS_AIPS_PACRL_WP3 (1U) //!< Bit field size in bits for AIPS_PACRL_WP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRL_WP3 field.
-#define BR_AIPS_PACRL_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRL_WP3.
-#define BF_AIPS_PACRL_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP3), uint32_t) & BM_AIPS_PACRL_WP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP3 field to a new value.
-#define BW_AIPS_PACRL_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRL, field SP3[18] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRL_SP3 (18U) //!< Bit position for AIPS_PACRL_SP3.
-#define BM_AIPS_PACRL_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRL_SP3.
-#define BS_AIPS_PACRL_SP3 (1U) //!< Bit field size in bits for AIPS_PACRL_SP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRL_SP3 field.
-#define BR_AIPS_PACRL_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRL_SP3.
-#define BF_AIPS_PACRL_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP3), uint32_t) & BM_AIPS_PACRL_SP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP3 field to a new value.
-#define BW_AIPS_PACRL_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRL, field TP2[20] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRL_TP2 (20U) //!< Bit position for AIPS_PACRL_TP2.
-#define BM_AIPS_PACRL_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRL_TP2.
-#define BS_AIPS_PACRL_TP2 (1U) //!< Bit field size in bits for AIPS_PACRL_TP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRL_TP2 field.
-#define BR_AIPS_PACRL_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRL_TP2.
-#define BF_AIPS_PACRL_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP2), uint32_t) & BM_AIPS_PACRL_TP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP2 field to a new value.
-#define BW_AIPS_PACRL_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRL, field WP2[21] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRL_WP2 (21U) //!< Bit position for AIPS_PACRL_WP2.
-#define BM_AIPS_PACRL_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRL_WP2.
-#define BS_AIPS_PACRL_WP2 (1U) //!< Bit field size in bits for AIPS_PACRL_WP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRL_WP2 field.
-#define BR_AIPS_PACRL_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRL_WP2.
-#define BF_AIPS_PACRL_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP2), uint32_t) & BM_AIPS_PACRL_WP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP2 field to a new value.
-#define BW_AIPS_PACRL_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRL, field SP2[22] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this bit is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
- * set. If not, access terminates with an error response and no peripheral access
- * initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRL_SP2 (22U) //!< Bit position for AIPS_PACRL_SP2.
-#define BM_AIPS_PACRL_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRL_SP2.
-#define BS_AIPS_PACRL_SP2 (1U) //!< Bit field size in bits for AIPS_PACRL_SP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRL_SP2 field.
-#define BR_AIPS_PACRL_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRL_SP2.
-#define BF_AIPS_PACRL_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP2), uint32_t) & BM_AIPS_PACRL_SP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP2 field to a new value.
-#define BW_AIPS_PACRL_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRL, field TP1[24] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRL_TP1 (24U) //!< Bit position for AIPS_PACRL_TP1.
-#define BM_AIPS_PACRL_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRL_TP1.
-#define BS_AIPS_PACRL_TP1 (1U) //!< Bit field size in bits for AIPS_PACRL_TP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRL_TP1 field.
-#define BR_AIPS_PACRL_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRL_TP1.
-#define BF_AIPS_PACRL_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP1), uint32_t) & BM_AIPS_PACRL_TP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP1 field to a new value.
-#define BW_AIPS_PACRL_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRL, field WP1[25] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRL_WP1 (25U) //!< Bit position for AIPS_PACRL_WP1.
-#define BM_AIPS_PACRL_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRL_WP1.
-#define BS_AIPS_PACRL_WP1 (1U) //!< Bit field size in bits for AIPS_PACRL_WP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRL_WP1 field.
-#define BR_AIPS_PACRL_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRL_WP1.
-#define BF_AIPS_PACRL_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP1), uint32_t) & BM_AIPS_PACRL_WP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP1 field to a new value.
-#define BW_AIPS_PACRL_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRL, field SP1[26] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master must
- * be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRL_SP1 (26U) //!< Bit position for AIPS_PACRL_SP1.
-#define BM_AIPS_PACRL_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRL_SP1.
-#define BS_AIPS_PACRL_SP1 (1U) //!< Bit field size in bits for AIPS_PACRL_SP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRL_SP1 field.
-#define BR_AIPS_PACRL_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRL_SP1.
-#define BF_AIPS_PACRL_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP1), uint32_t) & BM_AIPS_PACRL_SP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP1 field to a new value.
-#define BW_AIPS_PACRL_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRL, field TP0[28] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRL_TP0 (28U) //!< Bit position for AIPS_PACRL_TP0.
-#define BM_AIPS_PACRL_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRL_TP0.
-#define BS_AIPS_PACRL_TP0 (1U) //!< Bit field size in bits for AIPS_PACRL_TP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRL_TP0 field.
-#define BR_AIPS_PACRL_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRL_TP0.
-#define BF_AIPS_PACRL_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP0), uint32_t) & BM_AIPS_PACRL_TP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP0 field to a new value.
-#define BW_AIPS_PACRL_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRL, field WP0[29] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRL_WP0 (29U) //!< Bit position for AIPS_PACRL_WP0.
-#define BM_AIPS_PACRL_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRL_WP0.
-#define BS_AIPS_PACRL_WP0 (1U) //!< Bit field size in bits for AIPS_PACRL_WP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRL_WP0 field.
-#define BR_AIPS_PACRL_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRL_WP0.
-#define BF_AIPS_PACRL_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP0), uint32_t) & BM_AIPS_PACRL_WP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP0 field to a new value.
-#define BW_AIPS_PACRL_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRL, field SP0[30] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRL_SP0 (30U) //!< Bit position for AIPS_PACRL_SP0.
-#define BM_AIPS_PACRL_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRL_SP0.
-#define BS_AIPS_PACRL_SP0 (1U) //!< Bit field size in bits for AIPS_PACRL_SP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRL_SP0 field.
-#define BR_AIPS_PACRL_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRL_SP0.
-#define BF_AIPS_PACRL_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP0), uint32_t) & BM_AIPS_PACRL_SP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP0 field to a new value.
-#define BW_AIPS_PACRL_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP0) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_AIPS_PACRM - Peripheral Access Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_AIPS_PACRM - Peripheral Access Control Register (RW)
- *
- * Reset value: 0x44444444U
- *
- * This section describes PACR registers E-P, which control peripheral slots
- * 32-127. See PACRPeripheral Access Control Register for the description of these
- * registers.
- */
-typedef union _hw_aips_pacrm
-{
- uint32_t U;
- struct _hw_aips_pacrm_bitfields
- {
- uint32_t TP7 : 1; //!< [0] Trusted Protect
- uint32_t WP7 : 1; //!< [1] Write Protect
- uint32_t SP7 : 1; //!< [2] Supervisor Protect
- uint32_t RESERVED0 : 1; //!< [3]
- uint32_t TP6 : 1; //!< [4] Trusted Protect
- uint32_t WP6 : 1; //!< [5] Write Protect
- uint32_t SP6 : 1; //!< [6] Supervisor Protect
- uint32_t RESERVED1 : 1; //!< [7]
- uint32_t TP5 : 1; //!< [8] Trusted Protect
- uint32_t WP5 : 1; //!< [9] Write Protect
- uint32_t SP5 : 1; //!< [10] Supervisor Protect
- uint32_t RESERVED2 : 1; //!< [11]
- uint32_t TP4 : 1; //!< [12] Trusted Protect
- uint32_t WP4 : 1; //!< [13] Write Protect
- uint32_t SP4 : 1; //!< [14] Supervisor Protect
- uint32_t RESERVED3 : 1; //!< [15]
- uint32_t TP3 : 1; //!< [16] Trusted Protect
- uint32_t WP3 : 1; //!< [17] Write Protect
- uint32_t SP3 : 1; //!< [18] Supervisor Protect
- uint32_t RESERVED4 : 1; //!< [19]
- uint32_t TP2 : 1; //!< [20] Trusted Protect
- uint32_t WP2 : 1; //!< [21] Write Protect
- uint32_t SP2 : 1; //!< [22] Supervisor Protect
- uint32_t RESERVED5 : 1; //!< [23]
- uint32_t TP1 : 1; //!< [24] Trusted Protect
- uint32_t WP1 : 1; //!< [25] Write Protect
- uint32_t SP1 : 1; //!< [26] Supervisor Protect
- uint32_t RESERVED6 : 1; //!< [27]
- uint32_t TP0 : 1; //!< [28] Trusted Protect
- uint32_t WP0 : 1; //!< [29] Write Protect
- uint32_t SP0 : 1; //!< [30] Supervisor Protect
- uint32_t RESERVED7 : 1; //!< [31]
- } B;
-} hw_aips_pacrm_t;
-#endif
-
-/*!
- * @name Constants and macros for entire AIPS_PACRM register
- */
-//@{
-#define HW_AIPS_PACRM_ADDR(x) (REGS_AIPS_BASE(x) + 0x60U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_AIPS_PACRM(x) (*(__IO hw_aips_pacrm_t *) HW_AIPS_PACRM_ADDR(x))
-#define HW_AIPS_PACRM_RD(x) (HW_AIPS_PACRM(x).U)
-#define HW_AIPS_PACRM_WR(x, v) (HW_AIPS_PACRM(x).U = (v))
-#define HW_AIPS_PACRM_SET(x, v) (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) | (v)))
-#define HW_AIPS_PACRM_CLR(x, v) (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) & ~(v)))
-#define HW_AIPS_PACRM_TOG(x, v) (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual AIPS_PACRM bitfields
- */
-
-/*!
- * @name Register AIPS_PACRM, field TP7[0] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRM_TP7 (0U) //!< Bit position for AIPS_PACRM_TP7.
-#define BM_AIPS_PACRM_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRM_TP7.
-#define BS_AIPS_PACRM_TP7 (1U) //!< Bit field size in bits for AIPS_PACRM_TP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRM_TP7 field.
-#define BR_AIPS_PACRM_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRM_TP7.
-#define BF_AIPS_PACRM_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP7), uint32_t) & BM_AIPS_PACRM_TP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP7 field to a new value.
-#define BW_AIPS_PACRM_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRM, field WP7[1] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRM_WP7 (1U) //!< Bit position for AIPS_PACRM_WP7.
-#define BM_AIPS_PACRM_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRM_WP7.
-#define BS_AIPS_PACRM_WP7 (1U) //!< Bit field size in bits for AIPS_PACRM_WP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRM_WP7 field.
-#define BR_AIPS_PACRM_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRM_WP7.
-#define BF_AIPS_PACRM_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP7), uint32_t) & BM_AIPS_PACRM_WP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP7 field to a new value.
-#define BW_AIPS_PACRM_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRM, field SP7[2] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRM_SP7 (2U) //!< Bit position for AIPS_PACRM_SP7.
-#define BM_AIPS_PACRM_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRM_SP7.
-#define BS_AIPS_PACRM_SP7 (1U) //!< Bit field size in bits for AIPS_PACRM_SP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRM_SP7 field.
-#define BR_AIPS_PACRM_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRM_SP7.
-#define BF_AIPS_PACRM_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP7), uint32_t) & BM_AIPS_PACRM_SP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP7 field to a new value.
-#define BW_AIPS_PACRM_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRM, field TP6[4] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRM_TP6 (4U) //!< Bit position for AIPS_PACRM_TP6.
-#define BM_AIPS_PACRM_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRM_TP6.
-#define BS_AIPS_PACRM_TP6 (1U) //!< Bit field size in bits for AIPS_PACRM_TP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRM_TP6 field.
-#define BR_AIPS_PACRM_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRM_TP6.
-#define BF_AIPS_PACRM_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP6), uint32_t) & BM_AIPS_PACRM_TP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP6 field to a new value.
-#define BW_AIPS_PACRM_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRM, field WP6[5] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRM_WP6 (5U) //!< Bit position for AIPS_PACRM_WP6.
-#define BM_AIPS_PACRM_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRM_WP6.
-#define BS_AIPS_PACRM_WP6 (1U) //!< Bit field size in bits for AIPS_PACRM_WP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRM_WP6 field.
-#define BR_AIPS_PACRM_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRM_WP6.
-#define BF_AIPS_PACRM_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP6), uint32_t) & BM_AIPS_PACRM_WP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP6 field to a new value.
-#define BW_AIPS_PACRM_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRM, field SP6[6] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRM_SP6 (6U) //!< Bit position for AIPS_PACRM_SP6.
-#define BM_AIPS_PACRM_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRM_SP6.
-#define BS_AIPS_PACRM_SP6 (1U) //!< Bit field size in bits for AIPS_PACRM_SP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRM_SP6 field.
-#define BR_AIPS_PACRM_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRM_SP6.
-#define BF_AIPS_PACRM_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP6), uint32_t) & BM_AIPS_PACRM_SP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP6 field to a new value.
-#define BW_AIPS_PACRM_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRM, field TP5[8] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRM_TP5 (8U) //!< Bit position for AIPS_PACRM_TP5.
-#define BM_AIPS_PACRM_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRM_TP5.
-#define BS_AIPS_PACRM_TP5 (1U) //!< Bit field size in bits for AIPS_PACRM_TP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRM_TP5 field.
-#define BR_AIPS_PACRM_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRM_TP5.
-#define BF_AIPS_PACRM_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP5), uint32_t) & BM_AIPS_PACRM_TP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP5 field to a new value.
-#define BW_AIPS_PACRM_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRM, field WP5[9] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRM_WP5 (9U) //!< Bit position for AIPS_PACRM_WP5.
-#define BM_AIPS_PACRM_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRM_WP5.
-#define BS_AIPS_PACRM_WP5 (1U) //!< Bit field size in bits for AIPS_PACRM_WP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRM_WP5 field.
-#define BR_AIPS_PACRM_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRM_WP5.
-#define BF_AIPS_PACRM_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP5), uint32_t) & BM_AIPS_PACRM_WP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP5 field to a new value.
-#define BW_AIPS_PACRM_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRM, field SP5[10] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRM_SP5 (10U) //!< Bit position for AIPS_PACRM_SP5.
-#define BM_AIPS_PACRM_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRM_SP5.
-#define BS_AIPS_PACRM_SP5 (1U) //!< Bit field size in bits for AIPS_PACRM_SP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRM_SP5 field.
-#define BR_AIPS_PACRM_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRM_SP5.
-#define BF_AIPS_PACRM_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP5), uint32_t) & BM_AIPS_PACRM_SP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP5 field to a new value.
-#define BW_AIPS_PACRM_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRM, field TP4[12] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRM_TP4 (12U) //!< Bit position for AIPS_PACRM_TP4.
-#define BM_AIPS_PACRM_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRM_TP4.
-#define BS_AIPS_PACRM_TP4 (1U) //!< Bit field size in bits for AIPS_PACRM_TP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRM_TP4 field.
-#define BR_AIPS_PACRM_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRM_TP4.
-#define BF_AIPS_PACRM_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP4), uint32_t) & BM_AIPS_PACRM_TP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP4 field to a new value.
-#define BW_AIPS_PACRM_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRM, field WP4[13] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRM_WP4 (13U) //!< Bit position for AIPS_PACRM_WP4.
-#define BM_AIPS_PACRM_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRM_WP4.
-#define BS_AIPS_PACRM_WP4 (1U) //!< Bit field size in bits for AIPS_PACRM_WP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRM_WP4 field.
-#define BR_AIPS_PACRM_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRM_WP4.
-#define BF_AIPS_PACRM_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP4), uint32_t) & BM_AIPS_PACRM_WP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP4 field to a new value.
-#define BW_AIPS_PACRM_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRM, field SP4[14] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this bit is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
- * set. If not, access terminates with an error response and no peripheral access
- * initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRM_SP4 (14U) //!< Bit position for AIPS_PACRM_SP4.
-#define BM_AIPS_PACRM_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRM_SP4.
-#define BS_AIPS_PACRM_SP4 (1U) //!< Bit field size in bits for AIPS_PACRM_SP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRM_SP4 field.
-#define BR_AIPS_PACRM_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRM_SP4.
-#define BF_AIPS_PACRM_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP4), uint32_t) & BM_AIPS_PACRM_SP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP4 field to a new value.
-#define BW_AIPS_PACRM_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRM, field TP3[16] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRM_TP3 (16U) //!< Bit position for AIPS_PACRM_TP3.
-#define BM_AIPS_PACRM_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRM_TP3.
-#define BS_AIPS_PACRM_TP3 (1U) //!< Bit field size in bits for AIPS_PACRM_TP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRM_TP3 field.
-#define BR_AIPS_PACRM_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRM_TP3.
-#define BF_AIPS_PACRM_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP3), uint32_t) & BM_AIPS_PACRM_TP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP3 field to a new value.
-#define BW_AIPS_PACRM_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRM, field WP3[17] (RW)
- *
- * Determines whether the peripheral allows write accesss. When this bit is set
- * and a write access is attempted, access terminates with an error response and
- * no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRM_WP3 (17U) //!< Bit position for AIPS_PACRM_WP3.
-#define BM_AIPS_PACRM_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRM_WP3.
-#define BS_AIPS_PACRM_WP3 (1U) //!< Bit field size in bits for AIPS_PACRM_WP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRM_WP3 field.
-#define BR_AIPS_PACRM_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRM_WP3.
-#define BF_AIPS_PACRM_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP3), uint32_t) & BM_AIPS_PACRM_WP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP3 field to a new value.
-#define BW_AIPS_PACRM_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRM, field SP3[18] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRM_SP3 (18U) //!< Bit position for AIPS_PACRM_SP3.
-#define BM_AIPS_PACRM_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRM_SP3.
-#define BS_AIPS_PACRM_SP3 (1U) //!< Bit field size in bits for AIPS_PACRM_SP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRM_SP3 field.
-#define BR_AIPS_PACRM_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRM_SP3.
-#define BF_AIPS_PACRM_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP3), uint32_t) & BM_AIPS_PACRM_SP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP3 field to a new value.
-#define BW_AIPS_PACRM_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRM, field TP2[20] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRM_TP2 (20U) //!< Bit position for AIPS_PACRM_TP2.
-#define BM_AIPS_PACRM_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRM_TP2.
-#define BS_AIPS_PACRM_TP2 (1U) //!< Bit field size in bits for AIPS_PACRM_TP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRM_TP2 field.
-#define BR_AIPS_PACRM_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRM_TP2.
-#define BF_AIPS_PACRM_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP2), uint32_t) & BM_AIPS_PACRM_TP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP2 field to a new value.
-#define BW_AIPS_PACRM_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRM, field WP2[21] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRM_WP2 (21U) //!< Bit position for AIPS_PACRM_WP2.
-#define BM_AIPS_PACRM_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRM_WP2.
-#define BS_AIPS_PACRM_WP2 (1U) //!< Bit field size in bits for AIPS_PACRM_WP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRM_WP2 field.
-#define BR_AIPS_PACRM_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRM_WP2.
-#define BF_AIPS_PACRM_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP2), uint32_t) & BM_AIPS_PACRM_WP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP2 field to a new value.
-#define BW_AIPS_PACRM_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRM, field SP2[22] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this bit is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
- * set. If not, access terminates with an error response and no peripheral access
- * initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRM_SP2 (22U) //!< Bit position for AIPS_PACRM_SP2.
-#define BM_AIPS_PACRM_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRM_SP2.
-#define BS_AIPS_PACRM_SP2 (1U) //!< Bit field size in bits for AIPS_PACRM_SP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRM_SP2 field.
-#define BR_AIPS_PACRM_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRM_SP2.
-#define BF_AIPS_PACRM_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP2), uint32_t) & BM_AIPS_PACRM_SP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP2 field to a new value.
-#define BW_AIPS_PACRM_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRM, field TP1[24] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRM_TP1 (24U) //!< Bit position for AIPS_PACRM_TP1.
-#define BM_AIPS_PACRM_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRM_TP1.
-#define BS_AIPS_PACRM_TP1 (1U) //!< Bit field size in bits for AIPS_PACRM_TP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRM_TP1 field.
-#define BR_AIPS_PACRM_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRM_TP1.
-#define BF_AIPS_PACRM_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP1), uint32_t) & BM_AIPS_PACRM_TP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP1 field to a new value.
-#define BW_AIPS_PACRM_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRM, field WP1[25] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRM_WP1 (25U) //!< Bit position for AIPS_PACRM_WP1.
-#define BM_AIPS_PACRM_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRM_WP1.
-#define BS_AIPS_PACRM_WP1 (1U) //!< Bit field size in bits for AIPS_PACRM_WP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRM_WP1 field.
-#define BR_AIPS_PACRM_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRM_WP1.
-#define BF_AIPS_PACRM_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP1), uint32_t) & BM_AIPS_PACRM_WP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP1 field to a new value.
-#define BW_AIPS_PACRM_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRM, field SP1[26] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master must
- * be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRM_SP1 (26U) //!< Bit position for AIPS_PACRM_SP1.
-#define BM_AIPS_PACRM_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRM_SP1.
-#define BS_AIPS_PACRM_SP1 (1U) //!< Bit field size in bits for AIPS_PACRM_SP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRM_SP1 field.
-#define BR_AIPS_PACRM_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRM_SP1.
-#define BF_AIPS_PACRM_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP1), uint32_t) & BM_AIPS_PACRM_SP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP1 field to a new value.
-#define BW_AIPS_PACRM_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRM, field TP0[28] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRM_TP0 (28U) //!< Bit position for AIPS_PACRM_TP0.
-#define BM_AIPS_PACRM_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRM_TP0.
-#define BS_AIPS_PACRM_TP0 (1U) //!< Bit field size in bits for AIPS_PACRM_TP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRM_TP0 field.
-#define BR_AIPS_PACRM_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRM_TP0.
-#define BF_AIPS_PACRM_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP0), uint32_t) & BM_AIPS_PACRM_TP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP0 field to a new value.
-#define BW_AIPS_PACRM_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRM, field WP0[29] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRM_WP0 (29U) //!< Bit position for AIPS_PACRM_WP0.
-#define BM_AIPS_PACRM_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRM_WP0.
-#define BS_AIPS_PACRM_WP0 (1U) //!< Bit field size in bits for AIPS_PACRM_WP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRM_WP0 field.
-#define BR_AIPS_PACRM_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRM_WP0.
-#define BF_AIPS_PACRM_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP0), uint32_t) & BM_AIPS_PACRM_WP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP0 field to a new value.
-#define BW_AIPS_PACRM_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRM, field SP0[30] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRM_SP0 (30U) //!< Bit position for AIPS_PACRM_SP0.
-#define BM_AIPS_PACRM_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRM_SP0.
-#define BS_AIPS_PACRM_SP0 (1U) //!< Bit field size in bits for AIPS_PACRM_SP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRM_SP0 field.
-#define BR_AIPS_PACRM_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRM_SP0.
-#define BF_AIPS_PACRM_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP0), uint32_t) & BM_AIPS_PACRM_SP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP0 field to a new value.
-#define BW_AIPS_PACRM_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP0) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_AIPS_PACRN - Peripheral Access Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_AIPS_PACRN - Peripheral Access Control Register (RW)
- *
- * Reset value: 0x44444444U
- *
- * This section describes PACR registers E-P, which control peripheral slots
- * 32-127. See PACRPeripheral Access Control Register for the description of these
- * registers.
- */
-typedef union _hw_aips_pacrn
-{
- uint32_t U;
- struct _hw_aips_pacrn_bitfields
- {
- uint32_t TP7 : 1; //!< [0] Trusted Protect
- uint32_t WP7 : 1; //!< [1] Write Protect
- uint32_t SP7 : 1; //!< [2] Supervisor Protect
- uint32_t RESERVED0 : 1; //!< [3]
- uint32_t TP6 : 1; //!< [4] Trusted Protect
- uint32_t WP6 : 1; //!< [5] Write Protect
- uint32_t SP6 : 1; //!< [6] Supervisor Protect
- uint32_t RESERVED1 : 1; //!< [7]
- uint32_t TP5 : 1; //!< [8] Trusted Protect
- uint32_t WP5 : 1; //!< [9] Write Protect
- uint32_t SP5 : 1; //!< [10] Supervisor Protect
- uint32_t RESERVED2 : 1; //!< [11]
- uint32_t TP4 : 1; //!< [12] Trusted Protect
- uint32_t WP4 : 1; //!< [13] Write Protect
- uint32_t SP4 : 1; //!< [14] Supervisor Protect
- uint32_t RESERVED3 : 1; //!< [15]
- uint32_t TP3 : 1; //!< [16] Trusted Protect
- uint32_t WP3 : 1; //!< [17] Write Protect
- uint32_t SP3 : 1; //!< [18] Supervisor Protect
- uint32_t RESERVED4 : 1; //!< [19]
- uint32_t TP2 : 1; //!< [20] Trusted Protect
- uint32_t WP2 : 1; //!< [21] Write Protect
- uint32_t SP2 : 1; //!< [22] Supervisor Protect
- uint32_t RESERVED5 : 1; //!< [23]
- uint32_t TP1 : 1; //!< [24] Trusted Protect
- uint32_t WP1 : 1; //!< [25] Write Protect
- uint32_t SP1 : 1; //!< [26] Supervisor Protect
- uint32_t RESERVED6 : 1; //!< [27]
- uint32_t TP0 : 1; //!< [28] Trusted Protect
- uint32_t WP0 : 1; //!< [29] Write Protect
- uint32_t SP0 : 1; //!< [30] Supervisor Protect
- uint32_t RESERVED7 : 1; //!< [31]
- } B;
-} hw_aips_pacrn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire AIPS_PACRN register
- */
-//@{
-#define HW_AIPS_PACRN_ADDR(x) (REGS_AIPS_BASE(x) + 0x64U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_AIPS_PACRN(x) (*(__IO hw_aips_pacrn_t *) HW_AIPS_PACRN_ADDR(x))
-#define HW_AIPS_PACRN_RD(x) (HW_AIPS_PACRN(x).U)
-#define HW_AIPS_PACRN_WR(x, v) (HW_AIPS_PACRN(x).U = (v))
-#define HW_AIPS_PACRN_SET(x, v) (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) | (v)))
-#define HW_AIPS_PACRN_CLR(x, v) (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) & ~(v)))
-#define HW_AIPS_PACRN_TOG(x, v) (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual AIPS_PACRN bitfields
- */
-
-/*!
- * @name Register AIPS_PACRN, field TP7[0] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRN_TP7 (0U) //!< Bit position for AIPS_PACRN_TP7.
-#define BM_AIPS_PACRN_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRN_TP7.
-#define BS_AIPS_PACRN_TP7 (1U) //!< Bit field size in bits for AIPS_PACRN_TP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRN_TP7 field.
-#define BR_AIPS_PACRN_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRN_TP7.
-#define BF_AIPS_PACRN_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP7), uint32_t) & BM_AIPS_PACRN_TP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP7 field to a new value.
-#define BW_AIPS_PACRN_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRN, field WP7[1] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRN_WP7 (1U) //!< Bit position for AIPS_PACRN_WP7.
-#define BM_AIPS_PACRN_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRN_WP7.
-#define BS_AIPS_PACRN_WP7 (1U) //!< Bit field size in bits for AIPS_PACRN_WP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRN_WP7 field.
-#define BR_AIPS_PACRN_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRN_WP7.
-#define BF_AIPS_PACRN_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP7), uint32_t) & BM_AIPS_PACRN_WP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP7 field to a new value.
-#define BW_AIPS_PACRN_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRN, field SP7[2] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRN_SP7 (2U) //!< Bit position for AIPS_PACRN_SP7.
-#define BM_AIPS_PACRN_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRN_SP7.
-#define BS_AIPS_PACRN_SP7 (1U) //!< Bit field size in bits for AIPS_PACRN_SP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRN_SP7 field.
-#define BR_AIPS_PACRN_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRN_SP7.
-#define BF_AIPS_PACRN_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP7), uint32_t) & BM_AIPS_PACRN_SP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP7 field to a new value.
-#define BW_AIPS_PACRN_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRN, field TP6[4] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRN_TP6 (4U) //!< Bit position for AIPS_PACRN_TP6.
-#define BM_AIPS_PACRN_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRN_TP6.
-#define BS_AIPS_PACRN_TP6 (1U) //!< Bit field size in bits for AIPS_PACRN_TP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRN_TP6 field.
-#define BR_AIPS_PACRN_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRN_TP6.
-#define BF_AIPS_PACRN_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP6), uint32_t) & BM_AIPS_PACRN_TP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP6 field to a new value.
-#define BW_AIPS_PACRN_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRN, field WP6[5] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRN_WP6 (5U) //!< Bit position for AIPS_PACRN_WP6.
-#define BM_AIPS_PACRN_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRN_WP6.
-#define BS_AIPS_PACRN_WP6 (1U) //!< Bit field size in bits for AIPS_PACRN_WP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRN_WP6 field.
-#define BR_AIPS_PACRN_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRN_WP6.
-#define BF_AIPS_PACRN_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP6), uint32_t) & BM_AIPS_PACRN_WP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP6 field to a new value.
-#define BW_AIPS_PACRN_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRN, field SP6[6] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRN_SP6 (6U) //!< Bit position for AIPS_PACRN_SP6.
-#define BM_AIPS_PACRN_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRN_SP6.
-#define BS_AIPS_PACRN_SP6 (1U) //!< Bit field size in bits for AIPS_PACRN_SP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRN_SP6 field.
-#define BR_AIPS_PACRN_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRN_SP6.
-#define BF_AIPS_PACRN_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP6), uint32_t) & BM_AIPS_PACRN_SP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP6 field to a new value.
-#define BW_AIPS_PACRN_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRN, field TP5[8] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRN_TP5 (8U) //!< Bit position for AIPS_PACRN_TP5.
-#define BM_AIPS_PACRN_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRN_TP5.
-#define BS_AIPS_PACRN_TP5 (1U) //!< Bit field size in bits for AIPS_PACRN_TP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRN_TP5 field.
-#define BR_AIPS_PACRN_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRN_TP5.
-#define BF_AIPS_PACRN_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP5), uint32_t) & BM_AIPS_PACRN_TP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP5 field to a new value.
-#define BW_AIPS_PACRN_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRN, field WP5[9] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRN_WP5 (9U) //!< Bit position for AIPS_PACRN_WP5.
-#define BM_AIPS_PACRN_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRN_WP5.
-#define BS_AIPS_PACRN_WP5 (1U) //!< Bit field size in bits for AIPS_PACRN_WP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRN_WP5 field.
-#define BR_AIPS_PACRN_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRN_WP5.
-#define BF_AIPS_PACRN_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP5), uint32_t) & BM_AIPS_PACRN_WP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP5 field to a new value.
-#define BW_AIPS_PACRN_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRN, field SP5[10] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRN_SP5 (10U) //!< Bit position for AIPS_PACRN_SP5.
-#define BM_AIPS_PACRN_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRN_SP5.
-#define BS_AIPS_PACRN_SP5 (1U) //!< Bit field size in bits for AIPS_PACRN_SP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRN_SP5 field.
-#define BR_AIPS_PACRN_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRN_SP5.
-#define BF_AIPS_PACRN_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP5), uint32_t) & BM_AIPS_PACRN_SP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP5 field to a new value.
-#define BW_AIPS_PACRN_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRN, field TP4[12] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRN_TP4 (12U) //!< Bit position for AIPS_PACRN_TP4.
-#define BM_AIPS_PACRN_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRN_TP4.
-#define BS_AIPS_PACRN_TP4 (1U) //!< Bit field size in bits for AIPS_PACRN_TP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRN_TP4 field.
-#define BR_AIPS_PACRN_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRN_TP4.
-#define BF_AIPS_PACRN_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP4), uint32_t) & BM_AIPS_PACRN_TP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP4 field to a new value.
-#define BW_AIPS_PACRN_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRN, field WP4[13] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRN_WP4 (13U) //!< Bit position for AIPS_PACRN_WP4.
-#define BM_AIPS_PACRN_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRN_WP4.
-#define BS_AIPS_PACRN_WP4 (1U) //!< Bit field size in bits for AIPS_PACRN_WP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRN_WP4 field.
-#define BR_AIPS_PACRN_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRN_WP4.
-#define BF_AIPS_PACRN_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP4), uint32_t) & BM_AIPS_PACRN_WP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP4 field to a new value.
-#define BW_AIPS_PACRN_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRN, field SP4[14] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this bit is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
- * set. If not, access terminates with an error response and no peripheral access
- * initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRN_SP4 (14U) //!< Bit position for AIPS_PACRN_SP4.
-#define BM_AIPS_PACRN_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRN_SP4.
-#define BS_AIPS_PACRN_SP4 (1U) //!< Bit field size in bits for AIPS_PACRN_SP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRN_SP4 field.
-#define BR_AIPS_PACRN_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRN_SP4.
-#define BF_AIPS_PACRN_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP4), uint32_t) & BM_AIPS_PACRN_SP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP4 field to a new value.
-#define BW_AIPS_PACRN_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRN, field TP3[16] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRN_TP3 (16U) //!< Bit position for AIPS_PACRN_TP3.
-#define BM_AIPS_PACRN_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRN_TP3.
-#define BS_AIPS_PACRN_TP3 (1U) //!< Bit field size in bits for AIPS_PACRN_TP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRN_TP3 field.
-#define BR_AIPS_PACRN_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRN_TP3.
-#define BF_AIPS_PACRN_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP3), uint32_t) & BM_AIPS_PACRN_TP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP3 field to a new value.
-#define BW_AIPS_PACRN_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRN, field WP3[17] (RW)
- *
- * Determines whether the peripheral allows write accesss. When this bit is set
- * and a write access is attempted, access terminates with an error response and
- * no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRN_WP3 (17U) //!< Bit position for AIPS_PACRN_WP3.
-#define BM_AIPS_PACRN_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRN_WP3.
-#define BS_AIPS_PACRN_WP3 (1U) //!< Bit field size in bits for AIPS_PACRN_WP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRN_WP3 field.
-#define BR_AIPS_PACRN_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRN_WP3.
-#define BF_AIPS_PACRN_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP3), uint32_t) & BM_AIPS_PACRN_WP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP3 field to a new value.
-#define BW_AIPS_PACRN_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRN, field SP3[18] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRN_SP3 (18U) //!< Bit position for AIPS_PACRN_SP3.
-#define BM_AIPS_PACRN_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRN_SP3.
-#define BS_AIPS_PACRN_SP3 (1U) //!< Bit field size in bits for AIPS_PACRN_SP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRN_SP3 field.
-#define BR_AIPS_PACRN_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRN_SP3.
-#define BF_AIPS_PACRN_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP3), uint32_t) & BM_AIPS_PACRN_SP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP3 field to a new value.
-#define BW_AIPS_PACRN_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRN, field TP2[20] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRN_TP2 (20U) //!< Bit position for AIPS_PACRN_TP2.
-#define BM_AIPS_PACRN_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRN_TP2.
-#define BS_AIPS_PACRN_TP2 (1U) //!< Bit field size in bits for AIPS_PACRN_TP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRN_TP2 field.
-#define BR_AIPS_PACRN_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRN_TP2.
-#define BF_AIPS_PACRN_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP2), uint32_t) & BM_AIPS_PACRN_TP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP2 field to a new value.
-#define BW_AIPS_PACRN_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRN, field WP2[21] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRN_WP2 (21U) //!< Bit position for AIPS_PACRN_WP2.
-#define BM_AIPS_PACRN_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRN_WP2.
-#define BS_AIPS_PACRN_WP2 (1U) //!< Bit field size in bits for AIPS_PACRN_WP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRN_WP2 field.
-#define BR_AIPS_PACRN_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRN_WP2.
-#define BF_AIPS_PACRN_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP2), uint32_t) & BM_AIPS_PACRN_WP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP2 field to a new value.
-#define BW_AIPS_PACRN_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRN, field SP2[22] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this bit is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
- * set. If not, access terminates with an error response and no peripheral access
- * initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRN_SP2 (22U) //!< Bit position for AIPS_PACRN_SP2.
-#define BM_AIPS_PACRN_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRN_SP2.
-#define BS_AIPS_PACRN_SP2 (1U) //!< Bit field size in bits for AIPS_PACRN_SP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRN_SP2 field.
-#define BR_AIPS_PACRN_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRN_SP2.
-#define BF_AIPS_PACRN_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP2), uint32_t) & BM_AIPS_PACRN_SP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP2 field to a new value.
-#define BW_AIPS_PACRN_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRN, field TP1[24] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRN_TP1 (24U) //!< Bit position for AIPS_PACRN_TP1.
-#define BM_AIPS_PACRN_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRN_TP1.
-#define BS_AIPS_PACRN_TP1 (1U) //!< Bit field size in bits for AIPS_PACRN_TP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRN_TP1 field.
-#define BR_AIPS_PACRN_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRN_TP1.
-#define BF_AIPS_PACRN_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP1), uint32_t) & BM_AIPS_PACRN_TP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP1 field to a new value.
-#define BW_AIPS_PACRN_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRN, field WP1[25] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRN_WP1 (25U) //!< Bit position for AIPS_PACRN_WP1.
-#define BM_AIPS_PACRN_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRN_WP1.
-#define BS_AIPS_PACRN_WP1 (1U) //!< Bit field size in bits for AIPS_PACRN_WP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRN_WP1 field.
-#define BR_AIPS_PACRN_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRN_WP1.
-#define BF_AIPS_PACRN_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP1), uint32_t) & BM_AIPS_PACRN_WP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP1 field to a new value.
-#define BW_AIPS_PACRN_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRN, field SP1[26] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master must
- * be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRN_SP1 (26U) //!< Bit position for AIPS_PACRN_SP1.
-#define BM_AIPS_PACRN_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRN_SP1.
-#define BS_AIPS_PACRN_SP1 (1U) //!< Bit field size in bits for AIPS_PACRN_SP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRN_SP1 field.
-#define BR_AIPS_PACRN_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRN_SP1.
-#define BF_AIPS_PACRN_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP1), uint32_t) & BM_AIPS_PACRN_SP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP1 field to a new value.
-#define BW_AIPS_PACRN_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRN, field TP0[28] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRN_TP0 (28U) //!< Bit position for AIPS_PACRN_TP0.
-#define BM_AIPS_PACRN_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRN_TP0.
-#define BS_AIPS_PACRN_TP0 (1U) //!< Bit field size in bits for AIPS_PACRN_TP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRN_TP0 field.
-#define BR_AIPS_PACRN_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRN_TP0.
-#define BF_AIPS_PACRN_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP0), uint32_t) & BM_AIPS_PACRN_TP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP0 field to a new value.
-#define BW_AIPS_PACRN_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRN, field WP0[29] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRN_WP0 (29U) //!< Bit position for AIPS_PACRN_WP0.
-#define BM_AIPS_PACRN_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRN_WP0.
-#define BS_AIPS_PACRN_WP0 (1U) //!< Bit field size in bits for AIPS_PACRN_WP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRN_WP0 field.
-#define BR_AIPS_PACRN_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRN_WP0.
-#define BF_AIPS_PACRN_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP0), uint32_t) & BM_AIPS_PACRN_WP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP0 field to a new value.
-#define BW_AIPS_PACRN_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRN, field SP0[30] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRN_SP0 (30U) //!< Bit position for AIPS_PACRN_SP0.
-#define BM_AIPS_PACRN_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRN_SP0.
-#define BS_AIPS_PACRN_SP0 (1U) //!< Bit field size in bits for AIPS_PACRN_SP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRN_SP0 field.
-#define BR_AIPS_PACRN_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRN_SP0.
-#define BF_AIPS_PACRN_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP0), uint32_t) & BM_AIPS_PACRN_SP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP0 field to a new value.
-#define BW_AIPS_PACRN_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP0) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_AIPS_PACRO - Peripheral Access Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_AIPS_PACRO - Peripheral Access Control Register (RW)
- *
- * Reset value: 0x44444444U
- *
- * This section describes PACR registers E-P, which control peripheral slots
- * 32-127. See PACRPeripheral Access Control Register for the description of these
- * registers.
- */
-typedef union _hw_aips_pacro
-{
- uint32_t U;
- struct _hw_aips_pacro_bitfields
- {
- uint32_t TP7 : 1; //!< [0] Trusted Protect
- uint32_t WP7 : 1; //!< [1] Write Protect
- uint32_t SP7 : 1; //!< [2] Supervisor Protect
- uint32_t RESERVED0 : 1; //!< [3]
- uint32_t TP6 : 1; //!< [4] Trusted Protect
- uint32_t WP6 : 1; //!< [5] Write Protect
- uint32_t SP6 : 1; //!< [6] Supervisor Protect
- uint32_t RESERVED1 : 1; //!< [7]
- uint32_t TP5 : 1; //!< [8] Trusted Protect
- uint32_t WP5 : 1; //!< [9] Write Protect
- uint32_t SP5 : 1; //!< [10] Supervisor Protect
- uint32_t RESERVED2 : 1; //!< [11]
- uint32_t TP4 : 1; //!< [12] Trusted Protect
- uint32_t WP4 : 1; //!< [13] Write Protect
- uint32_t SP4 : 1; //!< [14] Supervisor Protect
- uint32_t RESERVED3 : 1; //!< [15]
- uint32_t TP3 : 1; //!< [16] Trusted Protect
- uint32_t WP3 : 1; //!< [17] Write Protect
- uint32_t SP3 : 1; //!< [18] Supervisor Protect
- uint32_t RESERVED4 : 1; //!< [19]
- uint32_t TP2 : 1; //!< [20] Trusted Protect
- uint32_t WP2 : 1; //!< [21] Write Protect
- uint32_t SP2 : 1; //!< [22] Supervisor Protect
- uint32_t RESERVED5 : 1; //!< [23]
- uint32_t TP1 : 1; //!< [24] Trusted Protect
- uint32_t WP1 : 1; //!< [25] Write Protect
- uint32_t SP1 : 1; //!< [26] Supervisor Protect
- uint32_t RESERVED6 : 1; //!< [27]
- uint32_t TP0 : 1; //!< [28] Trusted Protect
- uint32_t WP0 : 1; //!< [29] Write Protect
- uint32_t SP0 : 1; //!< [30] Supervisor Protect
- uint32_t RESERVED7 : 1; //!< [31]
- } B;
-} hw_aips_pacro_t;
-#endif
-
-/*!
- * @name Constants and macros for entire AIPS_PACRO register
- */
-//@{
-#define HW_AIPS_PACRO_ADDR(x) (REGS_AIPS_BASE(x) + 0x68U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_AIPS_PACRO(x) (*(__IO hw_aips_pacro_t *) HW_AIPS_PACRO_ADDR(x))
-#define HW_AIPS_PACRO_RD(x) (HW_AIPS_PACRO(x).U)
-#define HW_AIPS_PACRO_WR(x, v) (HW_AIPS_PACRO(x).U = (v))
-#define HW_AIPS_PACRO_SET(x, v) (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) | (v)))
-#define HW_AIPS_PACRO_CLR(x, v) (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) & ~(v)))
-#define HW_AIPS_PACRO_TOG(x, v) (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual AIPS_PACRO bitfields
- */
-
-/*!
- * @name Register AIPS_PACRO, field TP7[0] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRO_TP7 (0U) //!< Bit position for AIPS_PACRO_TP7.
-#define BM_AIPS_PACRO_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRO_TP7.
-#define BS_AIPS_PACRO_TP7 (1U) //!< Bit field size in bits for AIPS_PACRO_TP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRO_TP7 field.
-#define BR_AIPS_PACRO_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRO_TP7.
-#define BF_AIPS_PACRO_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP7), uint32_t) & BM_AIPS_PACRO_TP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP7 field to a new value.
-#define BW_AIPS_PACRO_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRO, field WP7[1] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRO_WP7 (1U) //!< Bit position for AIPS_PACRO_WP7.
-#define BM_AIPS_PACRO_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRO_WP7.
-#define BS_AIPS_PACRO_WP7 (1U) //!< Bit field size in bits for AIPS_PACRO_WP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRO_WP7 field.
-#define BR_AIPS_PACRO_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRO_WP7.
-#define BF_AIPS_PACRO_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP7), uint32_t) & BM_AIPS_PACRO_WP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP7 field to a new value.
-#define BW_AIPS_PACRO_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRO, field SP7[2] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRO_SP7 (2U) //!< Bit position for AIPS_PACRO_SP7.
-#define BM_AIPS_PACRO_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRO_SP7.
-#define BS_AIPS_PACRO_SP7 (1U) //!< Bit field size in bits for AIPS_PACRO_SP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRO_SP7 field.
-#define BR_AIPS_PACRO_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRO_SP7.
-#define BF_AIPS_PACRO_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP7), uint32_t) & BM_AIPS_PACRO_SP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP7 field to a new value.
-#define BW_AIPS_PACRO_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRO, field TP6[4] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRO_TP6 (4U) //!< Bit position for AIPS_PACRO_TP6.
-#define BM_AIPS_PACRO_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRO_TP6.
-#define BS_AIPS_PACRO_TP6 (1U) //!< Bit field size in bits for AIPS_PACRO_TP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRO_TP6 field.
-#define BR_AIPS_PACRO_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRO_TP6.
-#define BF_AIPS_PACRO_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP6), uint32_t) & BM_AIPS_PACRO_TP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP6 field to a new value.
-#define BW_AIPS_PACRO_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRO, field WP6[5] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRO_WP6 (5U) //!< Bit position for AIPS_PACRO_WP6.
-#define BM_AIPS_PACRO_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRO_WP6.
-#define BS_AIPS_PACRO_WP6 (1U) //!< Bit field size in bits for AIPS_PACRO_WP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRO_WP6 field.
-#define BR_AIPS_PACRO_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRO_WP6.
-#define BF_AIPS_PACRO_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP6), uint32_t) & BM_AIPS_PACRO_WP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP6 field to a new value.
-#define BW_AIPS_PACRO_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRO, field SP6[6] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRO_SP6 (6U) //!< Bit position for AIPS_PACRO_SP6.
-#define BM_AIPS_PACRO_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRO_SP6.
-#define BS_AIPS_PACRO_SP6 (1U) //!< Bit field size in bits for AIPS_PACRO_SP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRO_SP6 field.
-#define BR_AIPS_PACRO_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRO_SP6.
-#define BF_AIPS_PACRO_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP6), uint32_t) & BM_AIPS_PACRO_SP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP6 field to a new value.
-#define BW_AIPS_PACRO_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRO, field TP5[8] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRO_TP5 (8U) //!< Bit position for AIPS_PACRO_TP5.
-#define BM_AIPS_PACRO_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRO_TP5.
-#define BS_AIPS_PACRO_TP5 (1U) //!< Bit field size in bits for AIPS_PACRO_TP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRO_TP5 field.
-#define BR_AIPS_PACRO_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRO_TP5.
-#define BF_AIPS_PACRO_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP5), uint32_t) & BM_AIPS_PACRO_TP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP5 field to a new value.
-#define BW_AIPS_PACRO_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRO, field WP5[9] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRO_WP5 (9U) //!< Bit position for AIPS_PACRO_WP5.
-#define BM_AIPS_PACRO_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRO_WP5.
-#define BS_AIPS_PACRO_WP5 (1U) //!< Bit field size in bits for AIPS_PACRO_WP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRO_WP5 field.
-#define BR_AIPS_PACRO_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRO_WP5.
-#define BF_AIPS_PACRO_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP5), uint32_t) & BM_AIPS_PACRO_WP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP5 field to a new value.
-#define BW_AIPS_PACRO_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRO, field SP5[10] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRO_SP5 (10U) //!< Bit position for AIPS_PACRO_SP5.
-#define BM_AIPS_PACRO_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRO_SP5.
-#define BS_AIPS_PACRO_SP5 (1U) //!< Bit field size in bits for AIPS_PACRO_SP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRO_SP5 field.
-#define BR_AIPS_PACRO_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRO_SP5.
-#define BF_AIPS_PACRO_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP5), uint32_t) & BM_AIPS_PACRO_SP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP5 field to a new value.
-#define BW_AIPS_PACRO_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRO, field TP4[12] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRO_TP4 (12U) //!< Bit position for AIPS_PACRO_TP4.
-#define BM_AIPS_PACRO_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRO_TP4.
-#define BS_AIPS_PACRO_TP4 (1U) //!< Bit field size in bits for AIPS_PACRO_TP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRO_TP4 field.
-#define BR_AIPS_PACRO_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRO_TP4.
-#define BF_AIPS_PACRO_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP4), uint32_t) & BM_AIPS_PACRO_TP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP4 field to a new value.
-#define BW_AIPS_PACRO_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRO, field WP4[13] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRO_WP4 (13U) //!< Bit position for AIPS_PACRO_WP4.
-#define BM_AIPS_PACRO_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRO_WP4.
-#define BS_AIPS_PACRO_WP4 (1U) //!< Bit field size in bits for AIPS_PACRO_WP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRO_WP4 field.
-#define BR_AIPS_PACRO_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRO_WP4.
-#define BF_AIPS_PACRO_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP4), uint32_t) & BM_AIPS_PACRO_WP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP4 field to a new value.
-#define BW_AIPS_PACRO_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRO, field SP4[14] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this bit is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
- * set. If not, access terminates with an error response and no peripheral access
- * initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRO_SP4 (14U) //!< Bit position for AIPS_PACRO_SP4.
-#define BM_AIPS_PACRO_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRO_SP4.
-#define BS_AIPS_PACRO_SP4 (1U) //!< Bit field size in bits for AIPS_PACRO_SP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRO_SP4 field.
-#define BR_AIPS_PACRO_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRO_SP4.
-#define BF_AIPS_PACRO_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP4), uint32_t) & BM_AIPS_PACRO_SP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP4 field to a new value.
-#define BW_AIPS_PACRO_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRO, field TP3[16] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRO_TP3 (16U) //!< Bit position for AIPS_PACRO_TP3.
-#define BM_AIPS_PACRO_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRO_TP3.
-#define BS_AIPS_PACRO_TP3 (1U) //!< Bit field size in bits for AIPS_PACRO_TP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRO_TP3 field.
-#define BR_AIPS_PACRO_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRO_TP3.
-#define BF_AIPS_PACRO_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP3), uint32_t) & BM_AIPS_PACRO_TP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP3 field to a new value.
-#define BW_AIPS_PACRO_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRO, field WP3[17] (RW)
- *
- * Determines whether the peripheral allows write accesss. When this bit is set
- * and a write access is attempted, access terminates with an error response and
- * no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRO_WP3 (17U) //!< Bit position for AIPS_PACRO_WP3.
-#define BM_AIPS_PACRO_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRO_WP3.
-#define BS_AIPS_PACRO_WP3 (1U) //!< Bit field size in bits for AIPS_PACRO_WP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRO_WP3 field.
-#define BR_AIPS_PACRO_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRO_WP3.
-#define BF_AIPS_PACRO_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP3), uint32_t) & BM_AIPS_PACRO_WP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP3 field to a new value.
-#define BW_AIPS_PACRO_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRO, field SP3[18] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRO_SP3 (18U) //!< Bit position for AIPS_PACRO_SP3.
-#define BM_AIPS_PACRO_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRO_SP3.
-#define BS_AIPS_PACRO_SP3 (1U) //!< Bit field size in bits for AIPS_PACRO_SP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRO_SP3 field.
-#define BR_AIPS_PACRO_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRO_SP3.
-#define BF_AIPS_PACRO_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP3), uint32_t) & BM_AIPS_PACRO_SP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP3 field to a new value.
-#define BW_AIPS_PACRO_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRO, field TP2[20] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRO_TP2 (20U) //!< Bit position for AIPS_PACRO_TP2.
-#define BM_AIPS_PACRO_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRO_TP2.
-#define BS_AIPS_PACRO_TP2 (1U) //!< Bit field size in bits for AIPS_PACRO_TP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRO_TP2 field.
-#define BR_AIPS_PACRO_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRO_TP2.
-#define BF_AIPS_PACRO_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP2), uint32_t) & BM_AIPS_PACRO_TP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP2 field to a new value.
-#define BW_AIPS_PACRO_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRO, field WP2[21] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRO_WP2 (21U) //!< Bit position for AIPS_PACRO_WP2.
-#define BM_AIPS_PACRO_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRO_WP2.
-#define BS_AIPS_PACRO_WP2 (1U) //!< Bit field size in bits for AIPS_PACRO_WP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRO_WP2 field.
-#define BR_AIPS_PACRO_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRO_WP2.
-#define BF_AIPS_PACRO_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP2), uint32_t) & BM_AIPS_PACRO_WP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP2 field to a new value.
-#define BW_AIPS_PACRO_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRO, field SP2[22] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this bit is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
- * set. If not, access terminates with an error response and no peripheral access
- * initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRO_SP2 (22U) //!< Bit position for AIPS_PACRO_SP2.
-#define BM_AIPS_PACRO_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRO_SP2.
-#define BS_AIPS_PACRO_SP2 (1U) //!< Bit field size in bits for AIPS_PACRO_SP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRO_SP2 field.
-#define BR_AIPS_PACRO_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRO_SP2.
-#define BF_AIPS_PACRO_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP2), uint32_t) & BM_AIPS_PACRO_SP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP2 field to a new value.
-#define BW_AIPS_PACRO_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRO, field TP1[24] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRO_TP1 (24U) //!< Bit position for AIPS_PACRO_TP1.
-#define BM_AIPS_PACRO_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRO_TP1.
-#define BS_AIPS_PACRO_TP1 (1U) //!< Bit field size in bits for AIPS_PACRO_TP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRO_TP1 field.
-#define BR_AIPS_PACRO_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRO_TP1.
-#define BF_AIPS_PACRO_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP1), uint32_t) & BM_AIPS_PACRO_TP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP1 field to a new value.
-#define BW_AIPS_PACRO_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRO, field WP1[25] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRO_WP1 (25U) //!< Bit position for AIPS_PACRO_WP1.
-#define BM_AIPS_PACRO_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRO_WP1.
-#define BS_AIPS_PACRO_WP1 (1U) //!< Bit field size in bits for AIPS_PACRO_WP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRO_WP1 field.
-#define BR_AIPS_PACRO_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRO_WP1.
-#define BF_AIPS_PACRO_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP1), uint32_t) & BM_AIPS_PACRO_WP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP1 field to a new value.
-#define BW_AIPS_PACRO_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRO, field SP1[26] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master must
- * be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRO_SP1 (26U) //!< Bit position for AIPS_PACRO_SP1.
-#define BM_AIPS_PACRO_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRO_SP1.
-#define BS_AIPS_PACRO_SP1 (1U) //!< Bit field size in bits for AIPS_PACRO_SP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRO_SP1 field.
-#define BR_AIPS_PACRO_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRO_SP1.
-#define BF_AIPS_PACRO_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP1), uint32_t) & BM_AIPS_PACRO_SP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP1 field to a new value.
-#define BW_AIPS_PACRO_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRO, field TP0[28] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRO_TP0 (28U) //!< Bit position for AIPS_PACRO_TP0.
-#define BM_AIPS_PACRO_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRO_TP0.
-#define BS_AIPS_PACRO_TP0 (1U) //!< Bit field size in bits for AIPS_PACRO_TP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRO_TP0 field.
-#define BR_AIPS_PACRO_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRO_TP0.
-#define BF_AIPS_PACRO_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP0), uint32_t) & BM_AIPS_PACRO_TP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP0 field to a new value.
-#define BW_AIPS_PACRO_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRO, field WP0[29] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRO_WP0 (29U) //!< Bit position for AIPS_PACRO_WP0.
-#define BM_AIPS_PACRO_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRO_WP0.
-#define BS_AIPS_PACRO_WP0 (1U) //!< Bit field size in bits for AIPS_PACRO_WP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRO_WP0 field.
-#define BR_AIPS_PACRO_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRO_WP0.
-#define BF_AIPS_PACRO_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP0), uint32_t) & BM_AIPS_PACRO_WP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP0 field to a new value.
-#define BW_AIPS_PACRO_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRO, field SP0[30] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRO_SP0 (30U) //!< Bit position for AIPS_PACRO_SP0.
-#define BM_AIPS_PACRO_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRO_SP0.
-#define BS_AIPS_PACRO_SP0 (1U) //!< Bit field size in bits for AIPS_PACRO_SP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRO_SP0 field.
-#define BR_AIPS_PACRO_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRO_SP0.
-#define BF_AIPS_PACRO_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP0), uint32_t) & BM_AIPS_PACRO_SP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP0 field to a new value.
-#define BW_AIPS_PACRO_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP0) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_AIPS_PACRP - Peripheral Access Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_AIPS_PACRP - Peripheral Access Control Register (RW)
- *
- * Reset value: 0x44444444U
- *
- * This section describes PACR registers E-P, which control peripheral slots
- * 32-127. See PACRPeripheral Access Control Register for the description of these
- * registers.
- */
-typedef union _hw_aips_pacrp
-{
- uint32_t U;
- struct _hw_aips_pacrp_bitfields
- {
- uint32_t TP7 : 1; //!< [0] Trusted Protect
- uint32_t WP7 : 1; //!< [1] Write Protect
- uint32_t SP7 : 1; //!< [2] Supervisor Protect
- uint32_t RESERVED0 : 1; //!< [3]
- uint32_t TP6 : 1; //!< [4] Trusted Protect
- uint32_t WP6 : 1; //!< [5] Write Protect
- uint32_t SP6 : 1; //!< [6] Supervisor Protect
- uint32_t RESERVED1 : 1; //!< [7]
- uint32_t TP5 : 1; //!< [8] Trusted Protect
- uint32_t WP5 : 1; //!< [9] Write Protect
- uint32_t SP5 : 1; //!< [10] Supervisor Protect
- uint32_t RESERVED2 : 1; //!< [11]
- uint32_t TP4 : 1; //!< [12] Trusted Protect
- uint32_t WP4 : 1; //!< [13] Write Protect
- uint32_t SP4 : 1; //!< [14] Supervisor Protect
- uint32_t RESERVED3 : 1; //!< [15]
- uint32_t TP3 : 1; //!< [16] Trusted Protect
- uint32_t WP3 : 1; //!< [17] Write Protect
- uint32_t SP3 : 1; //!< [18] Supervisor Protect
- uint32_t RESERVED4 : 1; //!< [19]
- uint32_t TP2 : 1; //!< [20] Trusted Protect
- uint32_t WP2 : 1; //!< [21] Write Protect
- uint32_t SP2 : 1; //!< [22] Supervisor Protect
- uint32_t RESERVED5 : 1; //!< [23]
- uint32_t TP1 : 1; //!< [24] Trusted Protect
- uint32_t WP1 : 1; //!< [25] Write Protect
- uint32_t SP1 : 1; //!< [26] Supervisor Protect
- uint32_t RESERVED6 : 1; //!< [27]
- uint32_t TP0 : 1; //!< [28] Trusted Protect
- uint32_t WP0 : 1; //!< [29] Write Protect
- uint32_t SP0 : 1; //!< [30] Supervisor Protect
- uint32_t RESERVED7 : 1; //!< [31]
- } B;
-} hw_aips_pacrp_t;
-#endif
-
-/*!
- * @name Constants and macros for entire AIPS_PACRP register
- */
-//@{
-#define HW_AIPS_PACRP_ADDR(x) (REGS_AIPS_BASE(x) + 0x6CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_AIPS_PACRP(x) (*(__IO hw_aips_pacrp_t *) HW_AIPS_PACRP_ADDR(x))
-#define HW_AIPS_PACRP_RD(x) (HW_AIPS_PACRP(x).U)
-#define HW_AIPS_PACRP_WR(x, v) (HW_AIPS_PACRP(x).U = (v))
-#define HW_AIPS_PACRP_SET(x, v) (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) | (v)))
-#define HW_AIPS_PACRP_CLR(x, v) (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) & ~(v)))
-#define HW_AIPS_PACRP_TOG(x, v) (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual AIPS_PACRP bitfields
- */
-
-/*!
- * @name Register AIPS_PACRP, field TP7[0] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRP_TP7 (0U) //!< Bit position for AIPS_PACRP_TP7.
-#define BM_AIPS_PACRP_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRP_TP7.
-#define BS_AIPS_PACRP_TP7 (1U) //!< Bit field size in bits for AIPS_PACRP_TP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRP_TP7 field.
-#define BR_AIPS_PACRP_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRP_TP7.
-#define BF_AIPS_PACRP_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP7), uint32_t) & BM_AIPS_PACRP_TP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP7 field to a new value.
-#define BW_AIPS_PACRP_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRP, field WP7[1] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRP_WP7 (1U) //!< Bit position for AIPS_PACRP_WP7.
-#define BM_AIPS_PACRP_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRP_WP7.
-#define BS_AIPS_PACRP_WP7 (1U) //!< Bit field size in bits for AIPS_PACRP_WP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRP_WP7 field.
-#define BR_AIPS_PACRP_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRP_WP7.
-#define BF_AIPS_PACRP_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP7), uint32_t) & BM_AIPS_PACRP_WP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP7 field to a new value.
-#define BW_AIPS_PACRP_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRP, field SP7[2] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRP_SP7 (2U) //!< Bit position for AIPS_PACRP_SP7.
-#define BM_AIPS_PACRP_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRP_SP7.
-#define BS_AIPS_PACRP_SP7 (1U) //!< Bit field size in bits for AIPS_PACRP_SP7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRP_SP7 field.
-#define BR_AIPS_PACRP_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP7))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRP_SP7.
-#define BF_AIPS_PACRP_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP7), uint32_t) & BM_AIPS_PACRP_SP7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP7 field to a new value.
-#define BW_AIPS_PACRP_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRP, field TP6[4] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRP_TP6 (4U) //!< Bit position for AIPS_PACRP_TP6.
-#define BM_AIPS_PACRP_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRP_TP6.
-#define BS_AIPS_PACRP_TP6 (1U) //!< Bit field size in bits for AIPS_PACRP_TP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRP_TP6 field.
-#define BR_AIPS_PACRP_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRP_TP6.
-#define BF_AIPS_PACRP_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP6), uint32_t) & BM_AIPS_PACRP_TP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP6 field to a new value.
-#define BW_AIPS_PACRP_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRP, field WP6[5] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRP_WP6 (5U) //!< Bit position for AIPS_PACRP_WP6.
-#define BM_AIPS_PACRP_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRP_WP6.
-#define BS_AIPS_PACRP_WP6 (1U) //!< Bit field size in bits for AIPS_PACRP_WP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRP_WP6 field.
-#define BR_AIPS_PACRP_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRP_WP6.
-#define BF_AIPS_PACRP_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP6), uint32_t) & BM_AIPS_PACRP_WP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP6 field to a new value.
-#define BW_AIPS_PACRP_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRP, field SP6[6] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRP_SP6 (6U) //!< Bit position for AIPS_PACRP_SP6.
-#define BM_AIPS_PACRP_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRP_SP6.
-#define BS_AIPS_PACRP_SP6 (1U) //!< Bit field size in bits for AIPS_PACRP_SP6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRP_SP6 field.
-#define BR_AIPS_PACRP_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP6))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRP_SP6.
-#define BF_AIPS_PACRP_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP6), uint32_t) & BM_AIPS_PACRP_SP6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP6 field to a new value.
-#define BW_AIPS_PACRP_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRP, field TP5[8] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRP_TP5 (8U) //!< Bit position for AIPS_PACRP_TP5.
-#define BM_AIPS_PACRP_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRP_TP5.
-#define BS_AIPS_PACRP_TP5 (1U) //!< Bit field size in bits for AIPS_PACRP_TP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRP_TP5 field.
-#define BR_AIPS_PACRP_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRP_TP5.
-#define BF_AIPS_PACRP_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP5), uint32_t) & BM_AIPS_PACRP_TP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP5 field to a new value.
-#define BW_AIPS_PACRP_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRP, field WP5[9] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRP_WP5 (9U) //!< Bit position for AIPS_PACRP_WP5.
-#define BM_AIPS_PACRP_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRP_WP5.
-#define BS_AIPS_PACRP_WP5 (1U) //!< Bit field size in bits for AIPS_PACRP_WP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRP_WP5 field.
-#define BR_AIPS_PACRP_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRP_WP5.
-#define BF_AIPS_PACRP_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP5), uint32_t) & BM_AIPS_PACRP_WP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP5 field to a new value.
-#define BW_AIPS_PACRP_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRP, field SP5[10] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRP_SP5 (10U) //!< Bit position for AIPS_PACRP_SP5.
-#define BM_AIPS_PACRP_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRP_SP5.
-#define BS_AIPS_PACRP_SP5 (1U) //!< Bit field size in bits for AIPS_PACRP_SP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRP_SP5 field.
-#define BR_AIPS_PACRP_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP5))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRP_SP5.
-#define BF_AIPS_PACRP_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP5), uint32_t) & BM_AIPS_PACRP_SP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP5 field to a new value.
-#define BW_AIPS_PACRP_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRP, field TP4[12] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRP_TP4 (12U) //!< Bit position for AIPS_PACRP_TP4.
-#define BM_AIPS_PACRP_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRP_TP4.
-#define BS_AIPS_PACRP_TP4 (1U) //!< Bit field size in bits for AIPS_PACRP_TP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRP_TP4 field.
-#define BR_AIPS_PACRP_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRP_TP4.
-#define BF_AIPS_PACRP_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP4), uint32_t) & BM_AIPS_PACRP_TP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP4 field to a new value.
-#define BW_AIPS_PACRP_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRP, field WP4[13] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRP_WP4 (13U) //!< Bit position for AIPS_PACRP_WP4.
-#define BM_AIPS_PACRP_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRP_WP4.
-#define BS_AIPS_PACRP_WP4 (1U) //!< Bit field size in bits for AIPS_PACRP_WP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRP_WP4 field.
-#define BR_AIPS_PACRP_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRP_WP4.
-#define BF_AIPS_PACRP_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP4), uint32_t) & BM_AIPS_PACRP_WP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP4 field to a new value.
-#define BW_AIPS_PACRP_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRP, field SP4[14] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this bit is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
- * set. If not, access terminates with an error response and no peripheral access
- * initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRP_SP4 (14U) //!< Bit position for AIPS_PACRP_SP4.
-#define BM_AIPS_PACRP_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRP_SP4.
-#define BS_AIPS_PACRP_SP4 (1U) //!< Bit field size in bits for AIPS_PACRP_SP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRP_SP4 field.
-#define BR_AIPS_PACRP_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP4))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRP_SP4.
-#define BF_AIPS_PACRP_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP4), uint32_t) & BM_AIPS_PACRP_SP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP4 field to a new value.
-#define BW_AIPS_PACRP_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRP, field TP3[16] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRP_TP3 (16U) //!< Bit position for AIPS_PACRP_TP3.
-#define BM_AIPS_PACRP_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRP_TP3.
-#define BS_AIPS_PACRP_TP3 (1U) //!< Bit field size in bits for AIPS_PACRP_TP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRP_TP3 field.
-#define BR_AIPS_PACRP_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRP_TP3.
-#define BF_AIPS_PACRP_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP3), uint32_t) & BM_AIPS_PACRP_TP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP3 field to a new value.
-#define BW_AIPS_PACRP_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRP, field WP3[17] (RW)
- *
- * Determines whether the peripheral allows write accesss. When this bit is set
- * and a write access is attempted, access terminates with an error response and
- * no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRP_WP3 (17U) //!< Bit position for AIPS_PACRP_WP3.
-#define BM_AIPS_PACRP_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRP_WP3.
-#define BS_AIPS_PACRP_WP3 (1U) //!< Bit field size in bits for AIPS_PACRP_WP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRP_WP3 field.
-#define BR_AIPS_PACRP_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRP_WP3.
-#define BF_AIPS_PACRP_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP3), uint32_t) & BM_AIPS_PACRP_WP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP3 field to a new value.
-#define BW_AIPS_PACRP_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRP, field SP3[18] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRP_SP3 (18U) //!< Bit position for AIPS_PACRP_SP3.
-#define BM_AIPS_PACRP_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRP_SP3.
-#define BS_AIPS_PACRP_SP3 (1U) //!< Bit field size in bits for AIPS_PACRP_SP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRP_SP3 field.
-#define BR_AIPS_PACRP_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP3))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRP_SP3.
-#define BF_AIPS_PACRP_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP3), uint32_t) & BM_AIPS_PACRP_SP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP3 field to a new value.
-#define BW_AIPS_PACRP_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRP, field TP2[20] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRP_TP2 (20U) //!< Bit position for AIPS_PACRP_TP2.
-#define BM_AIPS_PACRP_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRP_TP2.
-#define BS_AIPS_PACRP_TP2 (1U) //!< Bit field size in bits for AIPS_PACRP_TP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRP_TP2 field.
-#define BR_AIPS_PACRP_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRP_TP2.
-#define BF_AIPS_PACRP_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP2), uint32_t) & BM_AIPS_PACRP_TP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP2 field to a new value.
-#define BW_AIPS_PACRP_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRP, field WP2[21] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRP_WP2 (21U) //!< Bit position for AIPS_PACRP_WP2.
-#define BM_AIPS_PACRP_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRP_WP2.
-#define BS_AIPS_PACRP_WP2 (1U) //!< Bit field size in bits for AIPS_PACRP_WP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRP_WP2 field.
-#define BR_AIPS_PACRP_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRP_WP2.
-#define BF_AIPS_PACRP_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP2), uint32_t) & BM_AIPS_PACRP_WP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP2 field to a new value.
-#define BW_AIPS_PACRP_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRP, field SP2[22] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this bit is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
- * set. If not, access terminates with an error response and no peripheral access
- * initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRP_SP2 (22U) //!< Bit position for AIPS_PACRP_SP2.
-#define BM_AIPS_PACRP_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRP_SP2.
-#define BS_AIPS_PACRP_SP2 (1U) //!< Bit field size in bits for AIPS_PACRP_SP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRP_SP2 field.
-#define BR_AIPS_PACRP_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP2))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRP_SP2.
-#define BF_AIPS_PACRP_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP2), uint32_t) & BM_AIPS_PACRP_SP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP2 field to a new value.
-#define BW_AIPS_PACRP_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRP, field TP1[24] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRP_TP1 (24U) //!< Bit position for AIPS_PACRP_TP1.
-#define BM_AIPS_PACRP_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRP_TP1.
-#define BS_AIPS_PACRP_TP1 (1U) //!< Bit field size in bits for AIPS_PACRP_TP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRP_TP1 field.
-#define BR_AIPS_PACRP_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRP_TP1.
-#define BF_AIPS_PACRP_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP1), uint32_t) & BM_AIPS_PACRP_TP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP1 field to a new value.
-#define BW_AIPS_PACRP_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRP, field WP1[25] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRP_WP1 (25U) //!< Bit position for AIPS_PACRP_WP1.
-#define BM_AIPS_PACRP_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRP_WP1.
-#define BS_AIPS_PACRP_WP1 (1U) //!< Bit field size in bits for AIPS_PACRP_WP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRP_WP1 field.
-#define BR_AIPS_PACRP_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRP_WP1.
-#define BF_AIPS_PACRP_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP1), uint32_t) & BM_AIPS_PACRP_WP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP1 field to a new value.
-#define BW_AIPS_PACRP_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRP, field SP1[26] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master must
- * be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRP_SP1 (26U) //!< Bit position for AIPS_PACRP_SP1.
-#define BM_AIPS_PACRP_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRP_SP1.
-#define BS_AIPS_PACRP_SP1 (1U) //!< Bit field size in bits for AIPS_PACRP_SP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRP_SP1 field.
-#define BR_AIPS_PACRP_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRP_SP1.
-#define BF_AIPS_PACRP_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP1), uint32_t) & BM_AIPS_PACRP_SP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP1 field to a new value.
-#define BW_AIPS_PACRP_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRP, field TP0[28] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this bit is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRP_TP0 (28U) //!< Bit position for AIPS_PACRP_TP0.
-#define BM_AIPS_PACRP_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRP_TP0.
-#define BS_AIPS_PACRP_TP0 (1U) //!< Bit field size in bits for AIPS_PACRP_TP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRP_TP0 field.
-#define BR_AIPS_PACRP_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRP_TP0.
-#define BF_AIPS_PACRP_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP0), uint32_t) & BM_AIPS_PACRP_TP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP0 field to a new value.
-#define BW_AIPS_PACRP_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRP, field WP0[29] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRP_WP0 (29U) //!< Bit position for AIPS_PACRP_WP0.
-#define BM_AIPS_PACRP_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRP_WP0.
-#define BS_AIPS_PACRP_WP0 (1U) //!< Bit field size in bits for AIPS_PACRP_WP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRP_WP0 field.
-#define BR_AIPS_PACRP_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRP_WP0.
-#define BF_AIPS_PACRP_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP0), uint32_t) & BM_AIPS_PACRP_WP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP0 field to a new value.
-#define BW_AIPS_PACRP_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRP, field SP0[30] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRP_SP0 (30U) //!< Bit position for AIPS_PACRP_SP0.
-#define BM_AIPS_PACRP_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRP_SP0.
-#define BS_AIPS_PACRP_SP0 (1U) //!< Bit field size in bits for AIPS_PACRP_SP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRP_SP0 field.
-#define BR_AIPS_PACRP_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRP_SP0.
-#define BF_AIPS_PACRP_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP0), uint32_t) & BM_AIPS_PACRP_SP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP0 field to a new value.
-#define BW_AIPS_PACRP_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP0) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_AIPS_PACRU - Peripheral Access Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_AIPS_PACRU - Peripheral Access Control Register (RW)
- *
- * Reset value: 0x44000000U
- *
- * PACRU defines the access levels for the two global spaces.
- */
-typedef union _hw_aips_pacru
-{
- uint32_t U;
- struct _hw_aips_pacru_bitfields
- {
- uint32_t RESERVED0 : 24; //!< [23:0]
- uint32_t TP1 : 1; //!< [24] Trusted Protect
- uint32_t WP1 : 1; //!< [25] Write Protect
- uint32_t SP1 : 1; //!< [26] Supervisor Protect
- uint32_t RESERVED1 : 1; //!< [27]
- uint32_t TP0 : 1; //!< [28] Trusted Protect
- uint32_t WP0 : 1; //!< [29] Write Protect
- uint32_t SP0 : 1; //!< [30] Supervisor Protect
- uint32_t RESERVED2 : 1; //!< [31]
- } B;
-} hw_aips_pacru_t;
-#endif
-
-/*!
- * @name Constants and macros for entire AIPS_PACRU register
- */
-//@{
-#define HW_AIPS_PACRU_ADDR(x) (REGS_AIPS_BASE(x) + 0x80U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_AIPS_PACRU(x) (*(__IO hw_aips_pacru_t *) HW_AIPS_PACRU_ADDR(x))
-#define HW_AIPS_PACRU_RD(x) (HW_AIPS_PACRU(x).U)
-#define HW_AIPS_PACRU_WR(x, v) (HW_AIPS_PACRU(x).U = (v))
-#define HW_AIPS_PACRU_SET(x, v) (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) | (v)))
-#define HW_AIPS_PACRU_CLR(x, v) (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) & ~(v)))
-#define HW_AIPS_PACRU_TOG(x, v) (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual AIPS_PACRU bitfields
- */
-
-/*!
- * @name Register AIPS_PACRU, field TP1[24] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRU_TP1 (24U) //!< Bit position for AIPS_PACRU_TP1.
-#define BM_AIPS_PACRU_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRU_TP1.
-#define BS_AIPS_PACRU_TP1 (1U) //!< Bit field size in bits for AIPS_PACRU_TP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRU_TP1 field.
-#define BR_AIPS_PACRU_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRU_TP1.
-#define BF_AIPS_PACRU_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_TP1), uint32_t) & BM_AIPS_PACRU_TP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP1 field to a new value.
-#define BW_AIPS_PACRU_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRU, field WP1[25] (RW)
- *
- * Determines whether the peripheral allows write accesss. When this bit is set
- * and a write access is attempted, access terminates with an error response and
- * no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRU_WP1 (25U) //!< Bit position for AIPS_PACRU_WP1.
-#define BM_AIPS_PACRU_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRU_WP1.
-#define BS_AIPS_PACRU_WP1 (1U) //!< Bit field size in bits for AIPS_PACRU_WP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRU_WP1 field.
-#define BR_AIPS_PACRU_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRU_WP1.
-#define BF_AIPS_PACRU_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_WP1), uint32_t) & BM_AIPS_PACRU_WP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP1 field to a new value.
-#define BW_AIPS_PACRU_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRU, field SP1[26] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * accesses. When this field is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control field for the master
- * must be set. If not, access terminates with an error response and no peripheral
- * access initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRU_SP1 (26U) //!< Bit position for AIPS_PACRU_SP1.
-#define BM_AIPS_PACRU_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRU_SP1.
-#define BS_AIPS_PACRU_SP1 (1U) //!< Bit field size in bits for AIPS_PACRU_SP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRU_SP1 field.
-#define BR_AIPS_PACRU_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP1))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRU_SP1.
-#define BF_AIPS_PACRU_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_SP1), uint32_t) & BM_AIPS_PACRU_SP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP1 field to a new value.
-#define BW_AIPS_PACRU_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRU, field TP0[28] (RW)
- *
- * Determines whether the peripheral allows accesses from an untrusted master.
- * When this field is set and an access is attempted by an untrusted master, the
- * access terminates with an error response and no peripheral access initiates.
- *
- * Values:
- * - 0 - Accesses from an untrusted master are allowed.
- * - 1 - Accesses from an untrusted master are not allowed.
- */
-//@{
-#define BP_AIPS_PACRU_TP0 (28U) //!< Bit position for AIPS_PACRU_TP0.
-#define BM_AIPS_PACRU_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRU_TP0.
-#define BS_AIPS_PACRU_TP0 (1U) //!< Bit field size in bits for AIPS_PACRU_TP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRU_TP0 field.
-#define BR_AIPS_PACRU_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRU_TP0.
-#define BF_AIPS_PACRU_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_TP0), uint32_t) & BM_AIPS_PACRU_TP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TP0 field to a new value.
-#define BW_AIPS_PACRU_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRU, field WP0[29] (RW)
- *
- * Determines whether the peripheral allows write accesses. When this field is
- * set and a write access is attempted, access terminates with an error response
- * and no peripheral access initiates.
- *
- * Values:
- * - 0 - This peripheral allows write accesses.
- * - 1 - This peripheral is write protected.
- */
-//@{
-#define BP_AIPS_PACRU_WP0 (29U) //!< Bit position for AIPS_PACRU_WP0.
-#define BM_AIPS_PACRU_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRU_WP0.
-#define BS_AIPS_PACRU_WP0 (1U) //!< Bit field size in bits for AIPS_PACRU_WP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRU_WP0 field.
-#define BR_AIPS_PACRU_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRU_WP0.
-#define BF_AIPS_PACRU_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_WP0), uint32_t) & BM_AIPS_PACRU_WP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP0 field to a new value.
-#define BW_AIPS_PACRU_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AIPS_PACRU, field SP0[30] (RW)
- *
- * Determines whether the peripheral requires supervisor privilege level for
- * access. When this bit is set, the master privilege level must indicate the
- * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
- * set. If not, access terminates with an error response and no peripheral access
- * initiates.
- *
- * Values:
- * - 0 - This peripheral does not require supervisor privilege level for
- * accesses.
- * - 1 - This peripheral requires supervisor privilege level for accesses.
- */
-//@{
-#define BP_AIPS_PACRU_SP0 (30U) //!< Bit position for AIPS_PACRU_SP0.
-#define BM_AIPS_PACRU_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRU_SP0.
-#define BS_AIPS_PACRU_SP0 (1U) //!< Bit field size in bits for AIPS_PACRU_SP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AIPS_PACRU_SP0 field.
-#define BR_AIPS_PACRU_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP0))
-#endif
-
-//! @brief Format value for bitfield AIPS_PACRU_SP0.
-#define BF_AIPS_PACRU_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_SP0), uint32_t) & BM_AIPS_PACRU_SP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SP0 field to a new value.
-#define BW_AIPS_PACRU_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP0) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_aips_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All AIPS module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_aips
-{
- __IO hw_aips_mpra_t MPRA; //!< [0x0] Master Privilege Register A
- uint8_t _reserved0[28];
- __IO hw_aips_pacra_t PACRA; //!< [0x20] Peripheral Access Control Register
- __IO hw_aips_pacrb_t PACRB; //!< [0x24] Peripheral Access Control Register
- __IO hw_aips_pacrc_t PACRC; //!< [0x28] Peripheral Access Control Register
- __IO hw_aips_pacrd_t PACRD; //!< [0x2C] Peripheral Access Control Register
- uint8_t _reserved1[16];
- __IO hw_aips_pacre_t PACRE; //!< [0x40] Peripheral Access Control Register
- __IO hw_aips_pacrf_t PACRF; //!< [0x44] Peripheral Access Control Register
- __IO hw_aips_pacrg_t PACRG; //!< [0x48] Peripheral Access Control Register
- __IO hw_aips_pacrh_t PACRH; //!< [0x4C] Peripheral Access Control Register
- __IO hw_aips_pacri_t PACRI; //!< [0x50] Peripheral Access Control Register
- __IO hw_aips_pacrj_t PACRJ; //!< [0x54] Peripheral Access Control Register
- __IO hw_aips_pacrk_t PACRK; //!< [0x58] Peripheral Access Control Register
- __IO hw_aips_pacrl_t PACRL; //!< [0x5C] Peripheral Access Control Register
- __IO hw_aips_pacrm_t PACRM; //!< [0x60] Peripheral Access Control Register
- __IO hw_aips_pacrn_t PACRN; //!< [0x64] Peripheral Access Control Register
- __IO hw_aips_pacro_t PACRO; //!< [0x68] Peripheral Access Control Register
- __IO hw_aips_pacrp_t PACRP; //!< [0x6C] Peripheral Access Control Register
- uint8_t _reserved2[16];
- __IO hw_aips_pacru_t PACRU; //!< [0x80] Peripheral Access Control Register
-} hw_aips_t;
-#pragma pack()
-
-//! @brief Macro to access all AIPS registers.
-//! @param x AIPS instance number.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_AIPS(0)</code>.
-#define HW_AIPS(x) (*(hw_aips_t *) REGS_AIPS_BASE(x))
-#endif
-
-#endif // __HW_AIPS_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_axbs.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1078 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_AXBS_REGISTERS_H__
-#define __HW_AXBS_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 AXBS
- *
- * Crossbar switch
- *
- * Registers defined in this header file:
- * - HW_AXBS_PRSn - Priority Registers Slave
- * - HW_AXBS_CRSn - Control Register
- * - HW_AXBS_MGPCR0 - Master General Purpose Control Register
- * - HW_AXBS_MGPCR1 - Master General Purpose Control Register
- * - HW_AXBS_MGPCR2 - Master General Purpose Control Register
- * - HW_AXBS_MGPCR3 - Master General Purpose Control Register
- * - HW_AXBS_MGPCR4 - Master General Purpose Control Register
- * - HW_AXBS_MGPCR5 - Master General Purpose Control Register
- *
- * - hw_axbs_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_AXBS_BASE
-#define HW_AXBS_INSTANCE_COUNT (1U) //!< Number of instances of the AXBS module.
-#define REGS_AXBS_BASE (0x40004000U) //!< Base address for AXBS.
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_AXBS_PRSn - Priority Registers Slave
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_AXBS_PRSn - Priority Registers Slave (RW)
- *
- * Reset value: 0x00543210U
- *
- * The priority registers (PRSn) set the priority of each master port on a per
- * slave port basis and reside in each slave port. The priority register can be
- * accessed only with 32-bit accesses. After the CRSn[RO] bit is set, the PRSn
- * register can only be read; attempts to write to it have no effect on PRSn and
- * result in a bus-error response to the master initiating the write. Two available
- * masters must not be programmed with the same priority level. Attempts to
- * program two or more masters with the same priority level result in a bus-error
- * response and the PRSn is not updated. Valid values for the Mn priority fields
- * depend on which masters are available on the chip. This information can be found in
- * the chip-specific information for the crossbar. If the chip contains less
- * than five masters, values 0 to 3 are valid. Writing other values will result in
- * an error. If the chip contains five or more masters, valid values are 0 to n-1,
- * where n is the number of masters attached to the AXBS module. Other values
- * will result in an error.
- */
-typedef union _hw_axbs_prsn
-{
- uint32_t U;
- struct _hw_axbs_prsn_bitfields
- {
- uint32_t M0 : 3; //!< [2:0] Master 0 Priority. Sets the arbitration
- //! priority for this port on the associated slave port.
- uint32_t RESERVED0 : 1; //!< [3]
- uint32_t M1 : 3; //!< [6:4] Master 1 Priority. Sets the arbitration
- //! priority for this port on the associated slave port.
- uint32_t RESERVED1 : 1; //!< [7]
- uint32_t M2 : 3; //!< [10:8] Master 2 Priority. Sets the arbitration
- //! priority for this port on the associated slave port.
- uint32_t RESERVED2 : 1; //!< [11]
- uint32_t M3 : 3; //!< [14:12] Master 3 Priority. Sets the arbitration
- //! priority for this port on the associated slave port.
- uint32_t RESERVED3 : 1; //!< [15]
- uint32_t M4 : 3; //!< [18:16] Master 4 Priority. Sets the arbitration
- //! priority for this port on the associated slave port.
- uint32_t RESERVED4 : 1; //!< [19]
- uint32_t M5 : 3; //!< [22:20] Master 5 Priority. Sets the arbitration
- //! priority for this port on the associated slave port.
- uint32_t RESERVED5 : 9; //!< [31:23]
- } B;
-} hw_axbs_prsn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire AXBS_PRSn register
- */
-//@{
-#define HW_AXBS_PRSn_COUNT (5U)
-
-#define HW_AXBS_PRSn_ADDR(n) (REGS_AXBS_BASE + 0x0U + (0x100U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_AXBS_PRSn(n) (*(__IO hw_axbs_prsn_t *) HW_AXBS_PRSn_ADDR(n))
-#define HW_AXBS_PRSn_RD(n) (HW_AXBS_PRSn(n).U)
-#define HW_AXBS_PRSn_WR(n, v) (HW_AXBS_PRSn(n).U = (v))
-#define HW_AXBS_PRSn_SET(n, v) (HW_AXBS_PRSn_WR(n, HW_AXBS_PRSn_RD(n) | (v)))
-#define HW_AXBS_PRSn_CLR(n, v) (HW_AXBS_PRSn_WR(n, HW_AXBS_PRSn_RD(n) & ~(v)))
-#define HW_AXBS_PRSn_TOG(n, v) (HW_AXBS_PRSn_WR(n, HW_AXBS_PRSn_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual AXBS_PRSn bitfields
- */
-
-/*!
- * @name Register AXBS_PRSn, field M0[2:0] (RW)
- *
- * Values:
- * - 000 - This master has level 1, or highest, priority when accessing the
- * slave port.
- * - 001 - This master has level 2 priority when accessing the slave port.
- * - 010 - This master has level 3 priority when accessing the slave port.
- * - 011 - This master has level 4 priority when accessing the slave port.
- * - 100 - This master has level 5 priority when accessing the slave port.
- * - 101 - This master has level 6 priority when accessing the slave port.
- * - 110 - This master has level 7 priority when accessing the slave port.
- * - 111 - This master has level 8, or lowest, priority when accessing the slave
- * port.
- */
-//@{
-#define BP_AXBS_PRSn_M0 (0U) //!< Bit position for AXBS_PRSn_M0.
-#define BM_AXBS_PRSn_M0 (0x00000007U) //!< Bit mask for AXBS_PRSn_M0.
-#define BS_AXBS_PRSn_M0 (3U) //!< Bit field size in bits for AXBS_PRSn_M0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AXBS_PRSn_M0 field.
-#define BR_AXBS_PRSn_M0(n) (HW_AXBS_PRSn(n).B.M0)
-#endif
-
-//! @brief Format value for bitfield AXBS_PRSn_M0.
-#define BF_AXBS_PRSn_M0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M0), uint32_t) & BM_AXBS_PRSn_M0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M0 field to a new value.
-#define BW_AXBS_PRSn_M0(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M0) | BF_AXBS_PRSn_M0(v)))
-#endif
-//@}
-
-/*!
- * @name Register AXBS_PRSn, field M1[6:4] (RW)
- *
- * Values:
- * - 000 - This master has level 1, or highest, priority when accessing the
- * slave port.
- * - 001 - This master has level 2 priority when accessing the slave port.
- * - 010 - This master has level 3 priority when accessing the slave port.
- * - 011 - This master has level 4 priority when accessing the slave port.
- * - 100 - This master has level 5 priority when accessing the slave port.
- * - 101 - This master has level 6 priority when accessing the slave port.
- * - 110 - This master has level 7 priority when accessing the slave port.
- * - 111 - This master has level 8, or lowest, priority when accessing the slave
- * port.
- */
-//@{
-#define BP_AXBS_PRSn_M1 (4U) //!< Bit position for AXBS_PRSn_M1.
-#define BM_AXBS_PRSn_M1 (0x00000070U) //!< Bit mask for AXBS_PRSn_M1.
-#define BS_AXBS_PRSn_M1 (3U) //!< Bit field size in bits for AXBS_PRSn_M1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AXBS_PRSn_M1 field.
-#define BR_AXBS_PRSn_M1(n) (HW_AXBS_PRSn(n).B.M1)
-#endif
-
-//! @brief Format value for bitfield AXBS_PRSn_M1.
-#define BF_AXBS_PRSn_M1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M1), uint32_t) & BM_AXBS_PRSn_M1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M1 field to a new value.
-#define BW_AXBS_PRSn_M1(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M1) | BF_AXBS_PRSn_M1(v)))
-#endif
-//@}
-
-/*!
- * @name Register AXBS_PRSn, field M2[10:8] (RW)
- *
- * Values:
- * - 000 - This master has level 1, or highest, priority when accessing the
- * slave port.
- * - 001 - This master has level 2 priority when accessing the slave port.
- * - 010 - This master has level 3 priority when accessing the slave port.
- * - 011 - This master has level 4 priority when accessing the slave port.
- * - 100 - This master has level 5 priority when accessing the slave port.
- * - 101 - This master has level 6 priority when accessing the slave port.
- * - 110 - This master has level 7 priority when accessing the slave port.
- * - 111 - This master has level 8, or lowest, priority when accessing the slave
- * port.
- */
-//@{
-#define BP_AXBS_PRSn_M2 (8U) //!< Bit position for AXBS_PRSn_M2.
-#define BM_AXBS_PRSn_M2 (0x00000700U) //!< Bit mask for AXBS_PRSn_M2.
-#define BS_AXBS_PRSn_M2 (3U) //!< Bit field size in bits for AXBS_PRSn_M2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AXBS_PRSn_M2 field.
-#define BR_AXBS_PRSn_M2(n) (HW_AXBS_PRSn(n).B.M2)
-#endif
-
-//! @brief Format value for bitfield AXBS_PRSn_M2.
-#define BF_AXBS_PRSn_M2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M2), uint32_t) & BM_AXBS_PRSn_M2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M2 field to a new value.
-#define BW_AXBS_PRSn_M2(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M2) | BF_AXBS_PRSn_M2(v)))
-#endif
-//@}
-
-/*!
- * @name Register AXBS_PRSn, field M3[14:12] (RW)
- *
- * Values:
- * - 000 - This master has level 1, or highest, priority when accessing the
- * slave port.
- * - 001 - This master has level 2 priority when accessing the slave port.
- * - 010 - This master has level 3 priority when accessing the slave port.
- * - 011 - This master has level 4 priority when accessing the slave port.
- * - 100 - This master has level 5 priority when accessing the slave port.
- * - 101 - This master has level 6 priority when accessing the slave port.
- * - 110 - This master has level 7 priority when accessing the slave port.
- * - 111 - This master has level 8, or lowest, priority when accessing the slave
- * port.
- */
-//@{
-#define BP_AXBS_PRSn_M3 (12U) //!< Bit position for AXBS_PRSn_M3.
-#define BM_AXBS_PRSn_M3 (0x00007000U) //!< Bit mask for AXBS_PRSn_M3.
-#define BS_AXBS_PRSn_M3 (3U) //!< Bit field size in bits for AXBS_PRSn_M3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AXBS_PRSn_M3 field.
-#define BR_AXBS_PRSn_M3(n) (HW_AXBS_PRSn(n).B.M3)
-#endif
-
-//! @brief Format value for bitfield AXBS_PRSn_M3.
-#define BF_AXBS_PRSn_M3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M3), uint32_t) & BM_AXBS_PRSn_M3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M3 field to a new value.
-#define BW_AXBS_PRSn_M3(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M3) | BF_AXBS_PRSn_M3(v)))
-#endif
-//@}
-
-/*!
- * @name Register AXBS_PRSn, field M4[18:16] (RW)
- *
- * Values:
- * - 000 - This master has level 1, or highest, priority when accessing the
- * slave port.
- * - 001 - This master has level 2 priority when accessing the slave port.
- * - 010 - This master has level 3 priority when accessing the slave port.
- * - 011 - This master has level 4 priority when accessing the slave port.
- * - 100 - This master has level 5 priority when accessing the slave port.
- * - 101 - This master has level 6 priority when accessing the slave port.
- * - 110 - This master has level 7 priority when accessing the slave port.
- * - 111 - This master has level 8, or lowest, priority when accessing the slave
- * port.
- */
-//@{
-#define BP_AXBS_PRSn_M4 (16U) //!< Bit position for AXBS_PRSn_M4.
-#define BM_AXBS_PRSn_M4 (0x00070000U) //!< Bit mask for AXBS_PRSn_M4.
-#define BS_AXBS_PRSn_M4 (3U) //!< Bit field size in bits for AXBS_PRSn_M4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AXBS_PRSn_M4 field.
-#define BR_AXBS_PRSn_M4(n) (HW_AXBS_PRSn(n).B.M4)
-#endif
-
-//! @brief Format value for bitfield AXBS_PRSn_M4.
-#define BF_AXBS_PRSn_M4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M4), uint32_t) & BM_AXBS_PRSn_M4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M4 field to a new value.
-#define BW_AXBS_PRSn_M4(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M4) | BF_AXBS_PRSn_M4(v)))
-#endif
-//@}
-
-/*!
- * @name Register AXBS_PRSn, field M5[22:20] (RW)
- *
- * Values:
- * - 000 - This master has level 1, or highest, priority when accessing the
- * slave port.
- * - 001 - This master has level 2 priority when accessing the slave port.
- * - 010 - This master has level 3 priority when accessing the slave port.
- * - 011 - This master has level 4 priority when accessing the slave port.
- * - 100 - This master has level 5 priority when accessing the slave port.
- * - 101 - This master has level 6 priority when accessing the slave port.
- * - 110 - This master has level 7 priority when accessing the slave port.
- * - 111 - This master has level 8, or lowest, priority when accessing the slave
- * port.
- */
-//@{
-#define BP_AXBS_PRSn_M5 (20U) //!< Bit position for AXBS_PRSn_M5.
-#define BM_AXBS_PRSn_M5 (0x00700000U) //!< Bit mask for AXBS_PRSn_M5.
-#define BS_AXBS_PRSn_M5 (3U) //!< Bit field size in bits for AXBS_PRSn_M5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AXBS_PRSn_M5 field.
-#define BR_AXBS_PRSn_M5(n) (HW_AXBS_PRSn(n).B.M5)
-#endif
-
-//! @brief Format value for bitfield AXBS_PRSn_M5.
-#define BF_AXBS_PRSn_M5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M5), uint32_t) & BM_AXBS_PRSn_M5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M5 field to a new value.
-#define BW_AXBS_PRSn_M5(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M5) | BF_AXBS_PRSn_M5(v)))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_AXBS_CRSn - Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_AXBS_CRSn - Control Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * These registers control several features of each slave port and must be
- * accessed using 32-bit accesses. After CRSn[RO] is set, the PRSn can only be read;
- * attempts to write to it have no effect and result in an error response.
- */
-typedef union _hw_axbs_crsn
-{
- uint32_t U;
- struct _hw_axbs_crsn_bitfields
- {
- uint32_t PARK : 3; //!< [2:0] Park
- uint32_t RESERVED0 : 1; //!< [3]
- uint32_t PCTL : 2; //!< [5:4] Parking Control
- uint32_t RESERVED1 : 2; //!< [7:6]
- uint32_t ARB : 2; //!< [9:8] Arbitration Mode
- uint32_t RESERVED2 : 20; //!< [29:10]
- uint32_t HLP : 1; //!< [30] Halt Low Priority
- uint32_t RO : 1; //!< [31] Read Only
- } B;
-} hw_axbs_crsn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire AXBS_CRSn register
- */
-//@{
-#define HW_AXBS_CRSn_COUNT (5U)
-
-#define HW_AXBS_CRSn_ADDR(n) (REGS_AXBS_BASE + 0x10U + (0x100U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_AXBS_CRSn(n) (*(__IO hw_axbs_crsn_t *) HW_AXBS_CRSn_ADDR(n))
-#define HW_AXBS_CRSn_RD(n) (HW_AXBS_CRSn(n).U)
-#define HW_AXBS_CRSn_WR(n, v) (HW_AXBS_CRSn(n).U = (v))
-#define HW_AXBS_CRSn_SET(n, v) (HW_AXBS_CRSn_WR(n, HW_AXBS_CRSn_RD(n) | (v)))
-#define HW_AXBS_CRSn_CLR(n, v) (HW_AXBS_CRSn_WR(n, HW_AXBS_CRSn_RD(n) & ~(v)))
-#define HW_AXBS_CRSn_TOG(n, v) (HW_AXBS_CRSn_WR(n, HW_AXBS_CRSn_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual AXBS_CRSn bitfields
- */
-
-/*!
- * @name Register AXBS_CRSn, field PARK[2:0] (RW)
- *
- * Determines which master port the current slave port parks on when no masters
- * are actively making requests and the PCTL bits are cleared. Select only master
- * ports that are present on the chip. Otherwise, undefined behavior might occur.
- *
- * Values:
- * - 000 - Park on master port M0
- * - 001 - Park on master port M1
- * - 010 - Park on master port M2
- * - 011 - Park on master port M3
- * - 100 - Park on master port M4
- * - 101 - Park on master port M5
- * - 110 - Park on master port M6
- * - 111 - Park on master port M7
- */
-//@{
-#define BP_AXBS_CRSn_PARK (0U) //!< Bit position for AXBS_CRSn_PARK.
-#define BM_AXBS_CRSn_PARK (0x00000007U) //!< Bit mask for AXBS_CRSn_PARK.
-#define BS_AXBS_CRSn_PARK (3U) //!< Bit field size in bits for AXBS_CRSn_PARK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AXBS_CRSn_PARK field.
-#define BR_AXBS_CRSn_PARK(n) (HW_AXBS_CRSn(n).B.PARK)
-#endif
-
-//! @brief Format value for bitfield AXBS_CRSn_PARK.
-#define BF_AXBS_CRSn_PARK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_CRSn_PARK), uint32_t) & BM_AXBS_CRSn_PARK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PARK field to a new value.
-#define BW_AXBS_CRSn_PARK(n, v) (HW_AXBS_CRSn_WR(n, (HW_AXBS_CRSn_RD(n) & ~BM_AXBS_CRSn_PARK) | BF_AXBS_CRSn_PARK(v)))
-#endif
-//@}
-
-/*!
- * @name Register AXBS_CRSn, field PCTL[5:4] (RW)
- *
- * Determines the slave port's parking control. The low-power park feature
- * results in an overall power savings if the slave port is not saturated. However,
- * this forces an extra latency clock when any master tries to access the slave
- * port while not in use because it is not parked on any master.
- *
- * Values:
- * - 00 - When no master makes a request, the arbiter parks the slave port on
- * the master port defined by the PARK field
- * - 01 - When no master makes a request, the arbiter parks the slave port on
- * the last master to be in control of the slave port
- * - 10 - When no master makes a request, the slave port is not parked on a
- * master and the arbiter drives all outputs to a constant safe state
- * - 11 - Reserved
- */
-//@{
-#define BP_AXBS_CRSn_PCTL (4U) //!< Bit position for AXBS_CRSn_PCTL.
-#define BM_AXBS_CRSn_PCTL (0x00000030U) //!< Bit mask for AXBS_CRSn_PCTL.
-#define BS_AXBS_CRSn_PCTL (2U) //!< Bit field size in bits for AXBS_CRSn_PCTL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AXBS_CRSn_PCTL field.
-#define BR_AXBS_CRSn_PCTL(n) (HW_AXBS_CRSn(n).B.PCTL)
-#endif
-
-//! @brief Format value for bitfield AXBS_CRSn_PCTL.
-#define BF_AXBS_CRSn_PCTL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_CRSn_PCTL), uint32_t) & BM_AXBS_CRSn_PCTL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PCTL field to a new value.
-#define BW_AXBS_CRSn_PCTL(n, v) (HW_AXBS_CRSn_WR(n, (HW_AXBS_CRSn_RD(n) & ~BM_AXBS_CRSn_PCTL) | BF_AXBS_CRSn_PCTL(v)))
-#endif
-//@}
-
-/*!
- * @name Register AXBS_CRSn, field ARB[9:8] (RW)
- *
- * Selects the arbitration policy for the slave port.
- *
- * Values:
- * - 00 - Fixed priority
- * - 01 - Round-robin, or rotating, priority
- * - 10 - Reserved
- * - 11 - Reserved
- */
-//@{
-#define BP_AXBS_CRSn_ARB (8U) //!< Bit position for AXBS_CRSn_ARB.
-#define BM_AXBS_CRSn_ARB (0x00000300U) //!< Bit mask for AXBS_CRSn_ARB.
-#define BS_AXBS_CRSn_ARB (2U) //!< Bit field size in bits for AXBS_CRSn_ARB.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AXBS_CRSn_ARB field.
-#define BR_AXBS_CRSn_ARB(n) (HW_AXBS_CRSn(n).B.ARB)
-#endif
-
-//! @brief Format value for bitfield AXBS_CRSn_ARB.
-#define BF_AXBS_CRSn_ARB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_CRSn_ARB), uint32_t) & BM_AXBS_CRSn_ARB)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ARB field to a new value.
-#define BW_AXBS_CRSn_ARB(n, v) (HW_AXBS_CRSn_WR(n, (HW_AXBS_CRSn_RD(n) & ~BM_AXBS_CRSn_ARB) | BF_AXBS_CRSn_ARB(v)))
-#endif
-//@}
-
-/*!
- * @name Register AXBS_CRSn, field HLP[30] (RW)
- *
- * Sets the initial arbitration priority for low power mode requests . Setting
- * this bit will not affect the request for low power mode from attaining highest
- * priority once it has control of the slave ports.
- *
- * Values:
- * - 0 - The low power mode request has the highest priority for arbitration on
- * this slave port
- * - 1 - The low power mode request has the lowest initial priority for
- * arbitration on this slave port
- */
-//@{
-#define BP_AXBS_CRSn_HLP (30U) //!< Bit position for AXBS_CRSn_HLP.
-#define BM_AXBS_CRSn_HLP (0x40000000U) //!< Bit mask for AXBS_CRSn_HLP.
-#define BS_AXBS_CRSn_HLP (1U) //!< Bit field size in bits for AXBS_CRSn_HLP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AXBS_CRSn_HLP field.
-#define BR_AXBS_CRSn_HLP(n) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(n), BP_AXBS_CRSn_HLP))
-#endif
-
-//! @brief Format value for bitfield AXBS_CRSn_HLP.
-#define BF_AXBS_CRSn_HLP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_CRSn_HLP), uint32_t) & BM_AXBS_CRSn_HLP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the HLP field to a new value.
-#define BW_AXBS_CRSn_HLP(n, v) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(n), BP_AXBS_CRSn_HLP) = (v))
-#endif
-//@}
-
-/*!
- * @name Register AXBS_CRSn, field RO[31] (RW)
- *
- * Forces the slave port's CSRn and PRSn registers to be read-only. After set,
- * only a hardware reset clears it.
- *
- * Values:
- * - 0 - The slave port's registers are writeable
- * - 1 - The slave port's registers are read-only and cannot be written.
- * Attempted writes have no effect on the registers and result in a bus error
- * response.
- */
-//@{
-#define BP_AXBS_CRSn_RO (31U) //!< Bit position for AXBS_CRSn_RO.
-#define BM_AXBS_CRSn_RO (0x80000000U) //!< Bit mask for AXBS_CRSn_RO.
-#define BS_AXBS_CRSn_RO (1U) //!< Bit field size in bits for AXBS_CRSn_RO.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AXBS_CRSn_RO field.
-#define BR_AXBS_CRSn_RO(n) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(n), BP_AXBS_CRSn_RO))
-#endif
-
-//! @brief Format value for bitfield AXBS_CRSn_RO.
-#define BF_AXBS_CRSn_RO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_CRSn_RO), uint32_t) & BM_AXBS_CRSn_RO)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RO field to a new value.
-#define BW_AXBS_CRSn_RO(n, v) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(n), BP_AXBS_CRSn_RO) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_AXBS_MGPCR0 - Master General Purpose Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_AXBS_MGPCR0 - Master General Purpose Control Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * The MGPCR controls only whether the master's undefined length burst accesses
- * are allowed to complete uninterrupted or whether they can be broken by
- * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
- * mode with 32-bit accesses.
- */
-typedef union _hw_axbs_mgpcr0
-{
- uint32_t U;
- struct _hw_axbs_mgpcr0_bitfields
- {
- uint32_t AULB : 3; //!< [2:0] Arbitrates On Undefined Length Bursts
- uint32_t RESERVED0 : 29; //!< [31:3]
- } B;
-} hw_axbs_mgpcr0_t;
-#endif
-
-/*!
- * @name Constants and macros for entire AXBS_MGPCR0 register
- */
-//@{
-#define HW_AXBS_MGPCR0_ADDR (REGS_AXBS_BASE + 0x800U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_AXBS_MGPCR0 (*(__IO hw_axbs_mgpcr0_t *) HW_AXBS_MGPCR0_ADDR)
-#define HW_AXBS_MGPCR0_RD() (HW_AXBS_MGPCR0.U)
-#define HW_AXBS_MGPCR0_WR(v) (HW_AXBS_MGPCR0.U = (v))
-#define HW_AXBS_MGPCR0_SET(v) (HW_AXBS_MGPCR0_WR(HW_AXBS_MGPCR0_RD() | (v)))
-#define HW_AXBS_MGPCR0_CLR(v) (HW_AXBS_MGPCR0_WR(HW_AXBS_MGPCR0_RD() & ~(v)))
-#define HW_AXBS_MGPCR0_TOG(v) (HW_AXBS_MGPCR0_WR(HW_AXBS_MGPCR0_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual AXBS_MGPCR0 bitfields
- */
-
-/*!
- * @name Register AXBS_MGPCR0, field AULB[2:0] (RW)
- *
- * Determines whether, and when, the crossbar switch arbitrates away the slave
- * port the master owns when the master is performing undefined length burst
- * accesses.
- *
- * Values:
- * - 000 - No arbitration is allowed during an undefined length burst
- * - 001 - Arbitration is allowed at any time during an undefined length burst
- * - 010 - Arbitration is allowed after four beats of an undefined length burst
- * - 011 - Arbitration is allowed after eight beats of an undefined length burst
- * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
- * - 101 - Reserved
- * - 110 - Reserved
- * - 111 - Reserved
- */
-//@{
-#define BP_AXBS_MGPCR0_AULB (0U) //!< Bit position for AXBS_MGPCR0_AULB.
-#define BM_AXBS_MGPCR0_AULB (0x00000007U) //!< Bit mask for AXBS_MGPCR0_AULB.
-#define BS_AXBS_MGPCR0_AULB (3U) //!< Bit field size in bits for AXBS_MGPCR0_AULB.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AXBS_MGPCR0_AULB field.
-#define BR_AXBS_MGPCR0_AULB (HW_AXBS_MGPCR0.B.AULB)
-#endif
-
-//! @brief Format value for bitfield AXBS_MGPCR0_AULB.
-#define BF_AXBS_MGPCR0_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR0_AULB), uint32_t) & BM_AXBS_MGPCR0_AULB)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the AULB field to a new value.
-#define BW_AXBS_MGPCR0_AULB(v) (HW_AXBS_MGPCR0_WR((HW_AXBS_MGPCR0_RD() & ~BM_AXBS_MGPCR0_AULB) | BF_AXBS_MGPCR0_AULB(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_AXBS_MGPCR1 - Master General Purpose Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_AXBS_MGPCR1 - Master General Purpose Control Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * The MGPCR controls only whether the master's undefined length burst accesses
- * are allowed to complete uninterrupted or whether they can be broken by
- * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
- * mode with 32-bit accesses.
- */
-typedef union _hw_axbs_mgpcr1
-{
- uint32_t U;
- struct _hw_axbs_mgpcr1_bitfields
- {
- uint32_t AULB : 3; //!< [2:0] Arbitrates On Undefined Length Bursts
- uint32_t RESERVED0 : 29; //!< [31:3]
- } B;
-} hw_axbs_mgpcr1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire AXBS_MGPCR1 register
- */
-//@{
-#define HW_AXBS_MGPCR1_ADDR (REGS_AXBS_BASE + 0x900U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_AXBS_MGPCR1 (*(__IO hw_axbs_mgpcr1_t *) HW_AXBS_MGPCR1_ADDR)
-#define HW_AXBS_MGPCR1_RD() (HW_AXBS_MGPCR1.U)
-#define HW_AXBS_MGPCR1_WR(v) (HW_AXBS_MGPCR1.U = (v))
-#define HW_AXBS_MGPCR1_SET(v) (HW_AXBS_MGPCR1_WR(HW_AXBS_MGPCR1_RD() | (v)))
-#define HW_AXBS_MGPCR1_CLR(v) (HW_AXBS_MGPCR1_WR(HW_AXBS_MGPCR1_RD() & ~(v)))
-#define HW_AXBS_MGPCR1_TOG(v) (HW_AXBS_MGPCR1_WR(HW_AXBS_MGPCR1_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual AXBS_MGPCR1 bitfields
- */
-
-/*!
- * @name Register AXBS_MGPCR1, field AULB[2:0] (RW)
- *
- * Determines whether, and when, the crossbar switch arbitrates away the slave
- * port the master owns when the master is performing undefined length burst
- * accesses.
- *
- * Values:
- * - 000 - No arbitration is allowed during an undefined length burst
- * - 001 - Arbitration is allowed at any time during an undefined length burst
- * - 010 - Arbitration is allowed after four beats of an undefined length burst
- * - 011 - Arbitration is allowed after eight beats of an undefined length burst
- * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
- * - 101 - Reserved
- * - 110 - Reserved
- * - 111 - Reserved
- */
-//@{
-#define BP_AXBS_MGPCR1_AULB (0U) //!< Bit position for AXBS_MGPCR1_AULB.
-#define BM_AXBS_MGPCR1_AULB (0x00000007U) //!< Bit mask for AXBS_MGPCR1_AULB.
-#define BS_AXBS_MGPCR1_AULB (3U) //!< Bit field size in bits for AXBS_MGPCR1_AULB.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AXBS_MGPCR1_AULB field.
-#define BR_AXBS_MGPCR1_AULB (HW_AXBS_MGPCR1.B.AULB)
-#endif
-
-//! @brief Format value for bitfield AXBS_MGPCR1_AULB.
-#define BF_AXBS_MGPCR1_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR1_AULB), uint32_t) & BM_AXBS_MGPCR1_AULB)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the AULB field to a new value.
-#define BW_AXBS_MGPCR1_AULB(v) (HW_AXBS_MGPCR1_WR((HW_AXBS_MGPCR1_RD() & ~BM_AXBS_MGPCR1_AULB) | BF_AXBS_MGPCR1_AULB(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_AXBS_MGPCR2 - Master General Purpose Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_AXBS_MGPCR2 - Master General Purpose Control Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * The MGPCR controls only whether the master's undefined length burst accesses
- * are allowed to complete uninterrupted or whether they can be broken by
- * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
- * mode with 32-bit accesses.
- */
-typedef union _hw_axbs_mgpcr2
-{
- uint32_t U;
- struct _hw_axbs_mgpcr2_bitfields
- {
- uint32_t AULB : 3; //!< [2:0] Arbitrates On Undefined Length Bursts
- uint32_t RESERVED0 : 29; //!< [31:3]
- } B;
-} hw_axbs_mgpcr2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire AXBS_MGPCR2 register
- */
-//@{
-#define HW_AXBS_MGPCR2_ADDR (REGS_AXBS_BASE + 0xA00U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_AXBS_MGPCR2 (*(__IO hw_axbs_mgpcr2_t *) HW_AXBS_MGPCR2_ADDR)
-#define HW_AXBS_MGPCR2_RD() (HW_AXBS_MGPCR2.U)
-#define HW_AXBS_MGPCR2_WR(v) (HW_AXBS_MGPCR2.U = (v))
-#define HW_AXBS_MGPCR2_SET(v) (HW_AXBS_MGPCR2_WR(HW_AXBS_MGPCR2_RD() | (v)))
-#define HW_AXBS_MGPCR2_CLR(v) (HW_AXBS_MGPCR2_WR(HW_AXBS_MGPCR2_RD() & ~(v)))
-#define HW_AXBS_MGPCR2_TOG(v) (HW_AXBS_MGPCR2_WR(HW_AXBS_MGPCR2_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual AXBS_MGPCR2 bitfields
- */
-
-/*!
- * @name Register AXBS_MGPCR2, field AULB[2:0] (RW)
- *
- * Determines whether, and when, the crossbar switch arbitrates away the slave
- * port the master owns when the master is performing undefined length burst
- * accesses.
- *
- * Values:
- * - 000 - No arbitration is allowed during an undefined length burst
- * - 001 - Arbitration is allowed at any time during an undefined length burst
- * - 010 - Arbitration is allowed after four beats of an undefined length burst
- * - 011 - Arbitration is allowed after eight beats of an undefined length burst
- * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
- * - 101 - Reserved
- * - 110 - Reserved
- * - 111 - Reserved
- */
-//@{
-#define BP_AXBS_MGPCR2_AULB (0U) //!< Bit position for AXBS_MGPCR2_AULB.
-#define BM_AXBS_MGPCR2_AULB (0x00000007U) //!< Bit mask for AXBS_MGPCR2_AULB.
-#define BS_AXBS_MGPCR2_AULB (3U) //!< Bit field size in bits for AXBS_MGPCR2_AULB.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AXBS_MGPCR2_AULB field.
-#define BR_AXBS_MGPCR2_AULB (HW_AXBS_MGPCR2.B.AULB)
-#endif
-
-//! @brief Format value for bitfield AXBS_MGPCR2_AULB.
-#define BF_AXBS_MGPCR2_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR2_AULB), uint32_t) & BM_AXBS_MGPCR2_AULB)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the AULB field to a new value.
-#define BW_AXBS_MGPCR2_AULB(v) (HW_AXBS_MGPCR2_WR((HW_AXBS_MGPCR2_RD() & ~BM_AXBS_MGPCR2_AULB) | BF_AXBS_MGPCR2_AULB(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_AXBS_MGPCR3 - Master General Purpose Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_AXBS_MGPCR3 - Master General Purpose Control Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * The MGPCR controls only whether the master's undefined length burst accesses
- * are allowed to complete uninterrupted or whether they can be broken by
- * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
- * mode with 32-bit accesses.
- */
-typedef union _hw_axbs_mgpcr3
-{
- uint32_t U;
- struct _hw_axbs_mgpcr3_bitfields
- {
- uint32_t AULB : 3; //!< [2:0] Arbitrates On Undefined Length Bursts
- uint32_t RESERVED0 : 29; //!< [31:3]
- } B;
-} hw_axbs_mgpcr3_t;
-#endif
-
-/*!
- * @name Constants and macros for entire AXBS_MGPCR3 register
- */
-//@{
-#define HW_AXBS_MGPCR3_ADDR (REGS_AXBS_BASE + 0xB00U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_AXBS_MGPCR3 (*(__IO hw_axbs_mgpcr3_t *) HW_AXBS_MGPCR3_ADDR)
-#define HW_AXBS_MGPCR3_RD() (HW_AXBS_MGPCR3.U)
-#define HW_AXBS_MGPCR3_WR(v) (HW_AXBS_MGPCR3.U = (v))
-#define HW_AXBS_MGPCR3_SET(v) (HW_AXBS_MGPCR3_WR(HW_AXBS_MGPCR3_RD() | (v)))
-#define HW_AXBS_MGPCR3_CLR(v) (HW_AXBS_MGPCR3_WR(HW_AXBS_MGPCR3_RD() & ~(v)))
-#define HW_AXBS_MGPCR3_TOG(v) (HW_AXBS_MGPCR3_WR(HW_AXBS_MGPCR3_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual AXBS_MGPCR3 bitfields
- */
-
-/*!
- * @name Register AXBS_MGPCR3, field AULB[2:0] (RW)
- *
- * Determines whether, and when, the crossbar switch arbitrates away the slave
- * port the master owns when the master is performing undefined length burst
- * accesses.
- *
- * Values:
- * - 000 - No arbitration is allowed during an undefined length burst
- * - 001 - Arbitration is allowed at any time during an undefined length burst
- * - 010 - Arbitration is allowed after four beats of an undefined length burst
- * - 011 - Arbitration is allowed after eight beats of an undefined length burst
- * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
- * - 101 - Reserved
- * - 110 - Reserved
- * - 111 - Reserved
- */
-//@{
-#define BP_AXBS_MGPCR3_AULB (0U) //!< Bit position for AXBS_MGPCR3_AULB.
-#define BM_AXBS_MGPCR3_AULB (0x00000007U) //!< Bit mask for AXBS_MGPCR3_AULB.
-#define BS_AXBS_MGPCR3_AULB (3U) //!< Bit field size in bits for AXBS_MGPCR3_AULB.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AXBS_MGPCR3_AULB field.
-#define BR_AXBS_MGPCR3_AULB (HW_AXBS_MGPCR3.B.AULB)
-#endif
-
-//! @brief Format value for bitfield AXBS_MGPCR3_AULB.
-#define BF_AXBS_MGPCR3_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR3_AULB), uint32_t) & BM_AXBS_MGPCR3_AULB)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the AULB field to a new value.
-#define BW_AXBS_MGPCR3_AULB(v) (HW_AXBS_MGPCR3_WR((HW_AXBS_MGPCR3_RD() & ~BM_AXBS_MGPCR3_AULB) | BF_AXBS_MGPCR3_AULB(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_AXBS_MGPCR4 - Master General Purpose Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_AXBS_MGPCR4 - Master General Purpose Control Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * The MGPCR controls only whether the master's undefined length burst accesses
- * are allowed to complete uninterrupted or whether they can be broken by
- * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
- * mode with 32-bit accesses.
- */
-typedef union _hw_axbs_mgpcr4
-{
- uint32_t U;
- struct _hw_axbs_mgpcr4_bitfields
- {
- uint32_t AULB : 3; //!< [2:0] Arbitrates On Undefined Length Bursts
- uint32_t RESERVED0 : 29; //!< [31:3]
- } B;
-} hw_axbs_mgpcr4_t;
-#endif
-
-/*!
- * @name Constants and macros for entire AXBS_MGPCR4 register
- */
-//@{
-#define HW_AXBS_MGPCR4_ADDR (REGS_AXBS_BASE + 0xC00U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_AXBS_MGPCR4 (*(__IO hw_axbs_mgpcr4_t *) HW_AXBS_MGPCR4_ADDR)
-#define HW_AXBS_MGPCR4_RD() (HW_AXBS_MGPCR4.U)
-#define HW_AXBS_MGPCR4_WR(v) (HW_AXBS_MGPCR4.U = (v))
-#define HW_AXBS_MGPCR4_SET(v) (HW_AXBS_MGPCR4_WR(HW_AXBS_MGPCR4_RD() | (v)))
-#define HW_AXBS_MGPCR4_CLR(v) (HW_AXBS_MGPCR4_WR(HW_AXBS_MGPCR4_RD() & ~(v)))
-#define HW_AXBS_MGPCR4_TOG(v) (HW_AXBS_MGPCR4_WR(HW_AXBS_MGPCR4_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual AXBS_MGPCR4 bitfields
- */
-
-/*!
- * @name Register AXBS_MGPCR4, field AULB[2:0] (RW)
- *
- * Determines whether, and when, the crossbar switch arbitrates away the slave
- * port the master owns when the master is performing undefined length burst
- * accesses.
- *
- * Values:
- * - 000 - No arbitration is allowed during an undefined length burst
- * - 001 - Arbitration is allowed at any time during an undefined length burst
- * - 010 - Arbitration is allowed after four beats of an undefined length burst
- * - 011 - Arbitration is allowed after eight beats of an undefined length burst
- * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
- * - 101 - Reserved
- * - 110 - Reserved
- * - 111 - Reserved
- */
-//@{
-#define BP_AXBS_MGPCR4_AULB (0U) //!< Bit position for AXBS_MGPCR4_AULB.
-#define BM_AXBS_MGPCR4_AULB (0x00000007U) //!< Bit mask for AXBS_MGPCR4_AULB.
-#define BS_AXBS_MGPCR4_AULB (3U) //!< Bit field size in bits for AXBS_MGPCR4_AULB.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AXBS_MGPCR4_AULB field.
-#define BR_AXBS_MGPCR4_AULB (HW_AXBS_MGPCR4.B.AULB)
-#endif
-
-//! @brief Format value for bitfield AXBS_MGPCR4_AULB.
-#define BF_AXBS_MGPCR4_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR4_AULB), uint32_t) & BM_AXBS_MGPCR4_AULB)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the AULB field to a new value.
-#define BW_AXBS_MGPCR4_AULB(v) (HW_AXBS_MGPCR4_WR((HW_AXBS_MGPCR4_RD() & ~BM_AXBS_MGPCR4_AULB) | BF_AXBS_MGPCR4_AULB(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_AXBS_MGPCR5 - Master General Purpose Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_AXBS_MGPCR5 - Master General Purpose Control Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * The MGPCR controls only whether the master's undefined length burst accesses
- * are allowed to complete uninterrupted or whether they can be broken by
- * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
- * mode with 32-bit accesses.
- */
-typedef union _hw_axbs_mgpcr5
-{
- uint32_t U;
- struct _hw_axbs_mgpcr5_bitfields
- {
- uint32_t AULB : 3; //!< [2:0] Arbitrates On Undefined Length Bursts
- uint32_t RESERVED0 : 29; //!< [31:3]
- } B;
-} hw_axbs_mgpcr5_t;
-#endif
-
-/*!
- * @name Constants and macros for entire AXBS_MGPCR5 register
- */
-//@{
-#define HW_AXBS_MGPCR5_ADDR (REGS_AXBS_BASE + 0xD00U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_AXBS_MGPCR5 (*(__IO hw_axbs_mgpcr5_t *) HW_AXBS_MGPCR5_ADDR)
-#define HW_AXBS_MGPCR5_RD() (HW_AXBS_MGPCR5.U)
-#define HW_AXBS_MGPCR5_WR(v) (HW_AXBS_MGPCR5.U = (v))
-#define HW_AXBS_MGPCR5_SET(v) (HW_AXBS_MGPCR5_WR(HW_AXBS_MGPCR5_RD() | (v)))
-#define HW_AXBS_MGPCR5_CLR(v) (HW_AXBS_MGPCR5_WR(HW_AXBS_MGPCR5_RD() & ~(v)))
-#define HW_AXBS_MGPCR5_TOG(v) (HW_AXBS_MGPCR5_WR(HW_AXBS_MGPCR5_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual AXBS_MGPCR5 bitfields
- */
-
-/*!
- * @name Register AXBS_MGPCR5, field AULB[2:0] (RW)
- *
- * Determines whether, and when, the crossbar switch arbitrates away the slave
- * port the master owns when the master is performing undefined length burst
- * accesses.
- *
- * Values:
- * - 000 - No arbitration is allowed during an undefined length burst
- * - 001 - Arbitration is allowed at any time during an undefined length burst
- * - 010 - Arbitration is allowed after four beats of an undefined length burst
- * - 011 - Arbitration is allowed after eight beats of an undefined length burst
- * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
- * - 101 - Reserved
- * - 110 - Reserved
- * - 111 - Reserved
- */
-//@{
-#define BP_AXBS_MGPCR5_AULB (0U) //!< Bit position for AXBS_MGPCR5_AULB.
-#define BM_AXBS_MGPCR5_AULB (0x00000007U) //!< Bit mask for AXBS_MGPCR5_AULB.
-#define BS_AXBS_MGPCR5_AULB (3U) //!< Bit field size in bits for AXBS_MGPCR5_AULB.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the AXBS_MGPCR5_AULB field.
-#define BR_AXBS_MGPCR5_AULB (HW_AXBS_MGPCR5.B.AULB)
-#endif
-
-//! @brief Format value for bitfield AXBS_MGPCR5_AULB.
-#define BF_AXBS_MGPCR5_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR5_AULB), uint32_t) & BM_AXBS_MGPCR5_AULB)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the AULB field to a new value.
-#define BW_AXBS_MGPCR5_AULB(v) (HW_AXBS_MGPCR5_WR((HW_AXBS_MGPCR5_RD() & ~BM_AXBS_MGPCR5_AULB) | BF_AXBS_MGPCR5_AULB(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_axbs_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All AXBS module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_axbs
-{
- struct {
- __IO hw_axbs_prsn_t PRSn; //!< [0x0] Priority Registers Slave
- uint8_t _reserved0[12];
- __IO hw_axbs_crsn_t CRSn; //!< [0x10] Control Register
- uint8_t _reserved1[236];
- } SLAVE[5];
- uint8_t _reserved0[768];
- __IO hw_axbs_mgpcr0_t MGPCR0; //!< [0x800] Master General Purpose Control Register
- uint8_t _reserved1[252];
- __IO hw_axbs_mgpcr1_t MGPCR1; //!< [0x900] Master General Purpose Control Register
- uint8_t _reserved2[252];
- __IO hw_axbs_mgpcr2_t MGPCR2; //!< [0xA00] Master General Purpose Control Register
- uint8_t _reserved3[252];
- __IO hw_axbs_mgpcr3_t MGPCR3; //!< [0xB00] Master General Purpose Control Register
- uint8_t _reserved4[252];
- __IO hw_axbs_mgpcr4_t MGPCR4; //!< [0xC00] Master General Purpose Control Register
- uint8_t _reserved5[252];
- __IO hw_axbs_mgpcr5_t MGPCR5; //!< [0xD00] Master General Purpose Control Register
-} hw_axbs_t;
-#pragma pack()
-
-//! @brief Macro to access all AXBS registers.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_AXBS</code>.
-#define HW_AXBS (*(hw_axbs_t *) REGS_AXBS_BASE)
-#endif
-
-#endif // __HW_AXBS_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_can.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,3963 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_CAN_REGISTERS_H__
-#define __HW_CAN_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 CAN
- *
- * Flex Controller Area Network module
- *
- * Registers defined in this header file:
- * - HW_CAN_MCR - Module Configuration Register
- * - HW_CAN_CTRL1 - Control 1 register
- * - HW_CAN_TIMER - Free Running Timer
- * - HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register
- * - HW_CAN_RX14MASK - Rx 14 Mask register
- * - HW_CAN_RX15MASK - Rx 15 Mask register
- * - HW_CAN_ECR - Error Counter
- * - HW_CAN_ESR1 - Error and Status 1 register
- * - HW_CAN_IMASK1 - Interrupt Masks 1 register
- * - HW_CAN_IFLAG1 - Interrupt Flags 1 register
- * - HW_CAN_CTRL2 - Control 2 register
- * - HW_CAN_ESR2 - Error and Status 2 register
- * - HW_CAN_CRCR - CRC Register
- * - HW_CAN_RXFGMASK - Rx FIFO Global Mask register
- * - HW_CAN_RXFIR - Rx FIFO Information Register
- * - HW_CAN_CS - Message Buffer 0 CS Register
- * - HW_CAN_ID - Message Buffer 0 ID Register
- * - HW_CAN_WORD0 - Message Buffer 0 WORD0 Register
- * - HW_CAN_WORD1 - Message Buffer 0 WORD1 Register
- * - HW_CAN_RXIMRn - Rx Individual Mask Registers
- *
- * - hw_can_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_CAN_BASE
-#define HW_CAN_INSTANCE_COUNT (1U) //!< Number of instances of the CAN module.
-#define HW_CAN0 (0U) //!< Instance number for CAN0.
-#define REGS_CAN0_BASE (0x40024000U) //!< Base address for CAN0.
-
-//! @brief Table of base addresses for CAN instances.
-static const uint32_t __g_regs_CAN_base_addresses[] = {
- REGS_CAN0_BASE,
- };
-
-//! @brief Get the base address of CAN by instance number.
-//! @param x CAN instance number, from 0 through 0.
-#define REGS_CAN_BASE(x) (__g_regs_CAN_base_addresses[(x)])
-
-//! @brief Get the instance number given a base address.
-//! @param b Base address for an instance of CAN.
-#define REGS_CAN_INSTANCE(b) ((b) == REGS_CAN0_BASE ? HW_CAN0 : 0)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CAN_MCR - Module Configuration Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAN_MCR - Module Configuration Register (RW)
- *
- * Reset value: 0xD890000FU
- *
- * This register defines global system configurations, such as the module
- * operation modes and the maximum message buffer configuration.
- */
-typedef union _hw_can_mcr
-{
- uint32_t U;
- struct _hw_can_mcr_bitfields
- {
- uint32_t MAXMB : 7; //!< [6:0] Number Of The Last Message Buffer
- uint32_t RESERVED0 : 1; //!< [7]
- uint32_t IDAM : 2; //!< [9:8] ID Acceptance Mode
- uint32_t RESERVED1 : 2; //!< [11:10]
- uint32_t AEN : 1; //!< [12] Abort Enable
- uint32_t LPRIOEN : 1; //!< [13] Local Priority Enable
- uint32_t RESERVED2 : 2; //!< [15:14]
- uint32_t IRMQ : 1; //!< [16] Individual Rx Masking And Queue Enable
- uint32_t SRXDIS : 1; //!< [17] Self Reception Disable
- uint32_t RESERVED3 : 1; //!< [18]
- uint32_t WAKSRC : 1; //!< [19] Wake Up Source
- uint32_t LPMACK : 1; //!< [20] Low-Power Mode Acknowledge
- uint32_t WRNEN : 1; //!< [21] Warning Interrupt Enable
- uint32_t SLFWAK : 1; //!< [22] Self Wake Up
- uint32_t SUPV : 1; //!< [23] Supervisor Mode
- uint32_t FRZACK : 1; //!< [24] Freeze Mode Acknowledge
- uint32_t SOFTRST : 1; //!< [25] Soft Reset
- uint32_t WAKMSK : 1; //!< [26] Wake Up Interrupt Mask
- uint32_t NOTRDY : 1; //!< [27] FlexCAN Not Ready
- uint32_t HALT : 1; //!< [28] Halt FlexCAN
- uint32_t RFEN : 1; //!< [29] Rx FIFO Enable
- uint32_t FRZ : 1; //!< [30] Freeze Enable
- uint32_t MDIS : 1; //!< [31] Module Disable
- } B;
-} hw_can_mcr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAN_MCR register
- */
-//@{
-#define HW_CAN_MCR_ADDR(x) (REGS_CAN_BASE(x) + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAN_MCR(x) (*(__IO hw_can_mcr_t *) HW_CAN_MCR_ADDR(x))
-#define HW_CAN_MCR_RD(x) (HW_CAN_MCR(x).U)
-#define HW_CAN_MCR_WR(x, v) (HW_CAN_MCR(x).U = (v))
-#define HW_CAN_MCR_SET(x, v) (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) | (v)))
-#define HW_CAN_MCR_CLR(x, v) (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) & ~(v)))
-#define HW_CAN_MCR_TOG(x, v) (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAN_MCR bitfields
- */
-
-/*!
- * @name Register CAN_MCR, field MAXMB[6:0] (RW)
- *
- * This 7-bit field defines the number of the last Message Buffers that will
- * take part in the matching and arbitration processes. The reset value (0x0F) is
- * equivalent to a 16 MB configuration. This field can be written only in Freeze
- * mode because it is blocked by hardware in other modes. Number of the last MB =
- * MAXMB MAXMB must be programmed with a value smaller than the parameter
- * NUMBER_OF_MB, otherwise the number of the last effective Message Buffer will be:
- * (NUMBER_OF_MB - 1) Additionally, the value of MAXMB must encompass the FIFO size
- * defined by CTRL2[RFFN]. MAXMB also impacts the definition of the minimum number
- * of peripheral clocks per CAN bit as described in Table "Minimum Ratio Between
- * Peripheral Clock Frequency and CAN Bit Rate" (in Section "Arbitration and
- * Matching Timing").
- */
-//@{
-#define BP_CAN_MCR_MAXMB (0U) //!< Bit position for CAN_MCR_MAXMB.
-#define BM_CAN_MCR_MAXMB (0x0000007FU) //!< Bit mask for CAN_MCR_MAXMB.
-#define BS_CAN_MCR_MAXMB (7U) //!< Bit field size in bits for CAN_MCR_MAXMB.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_MCR_MAXMB field.
-#define BR_CAN_MCR_MAXMB(x) (HW_CAN_MCR(x).B.MAXMB)
-#endif
-
-//! @brief Format value for bitfield CAN_MCR_MAXMB.
-#define BF_CAN_MCR_MAXMB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_MAXMB), uint32_t) & BM_CAN_MCR_MAXMB)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MAXMB field to a new value.
-#define BW_CAN_MCR_MAXMB(x, v) (HW_CAN_MCR_WR(x, (HW_CAN_MCR_RD(x) & ~BM_CAN_MCR_MAXMB) | BF_CAN_MCR_MAXMB(v)))
-#endif
-//@}
-
-/*!
- * @name Register CAN_MCR, field IDAM[9:8] (RW)
- *
- * This 2-bit field identifies the format of the Rx FIFO ID Filter Table
- * elements. Note that all elements of the table are configured at the same time by this
- * field (they are all the same format). See Section "Rx FIFO Structure". This
- * field can be written only in Freeze mode because it is blocked by hardware in
- * other modes.
- *
- * Values:
- * - 00 - Format A: One full ID (standard and extended) per ID Filter Table
- * element.
- * - 01 - Format B: Two full standard IDs or two partial 14-bit (standard and
- * extended) IDs per ID Filter Table element.
- * - 10 - Format C: Four partial 8-bit Standard IDs per ID Filter Table element.
- * - 11 - Format D: All frames rejected.
- */
-//@{
-#define BP_CAN_MCR_IDAM (8U) //!< Bit position for CAN_MCR_IDAM.
-#define BM_CAN_MCR_IDAM (0x00000300U) //!< Bit mask for CAN_MCR_IDAM.
-#define BS_CAN_MCR_IDAM (2U) //!< Bit field size in bits for CAN_MCR_IDAM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_MCR_IDAM field.
-#define BR_CAN_MCR_IDAM(x) (HW_CAN_MCR(x).B.IDAM)
-#endif
-
-//! @brief Format value for bitfield CAN_MCR_IDAM.
-#define BF_CAN_MCR_IDAM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_IDAM), uint32_t) & BM_CAN_MCR_IDAM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IDAM field to a new value.
-#define BW_CAN_MCR_IDAM(x, v) (HW_CAN_MCR_WR(x, (HW_CAN_MCR_RD(x) & ~BM_CAN_MCR_IDAM) | BF_CAN_MCR_IDAM(v)))
-#endif
-//@}
-
-/*!
- * @name Register CAN_MCR, field AEN[12] (RW)
- *
- * This bit is supplied for backwards compatibility with legacy applications.
- * When asserted, it enables the Tx abort mechanism. This mechanism guarantees a
- * safe procedure for aborting a pending transmission, so that no frame is sent in
- * the CAN bus without notification. This bit can be written only in Freeze mode
- * because it is blocked by hardware in other modes. When MCR[AEN] is asserted,
- * only the abort mechanism (see Section "Transmission Abort Mechanism") must be
- * used for updating Mailboxes configured for transmission. Writing the Abort code
- * into Rx Mailboxes can cause unpredictable results when the MCR[AEN] is
- * asserted.
- *
- * Values:
- * - 0 - Abort disabled.
- * - 1 - Abort enabled.
- */
-//@{
-#define BP_CAN_MCR_AEN (12U) //!< Bit position for CAN_MCR_AEN.
-#define BM_CAN_MCR_AEN (0x00001000U) //!< Bit mask for CAN_MCR_AEN.
-#define BS_CAN_MCR_AEN (1U) //!< Bit field size in bits for CAN_MCR_AEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_MCR_AEN field.
-#define BR_CAN_MCR_AEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_AEN))
-#endif
-
-//! @brief Format value for bitfield CAN_MCR_AEN.
-#define BF_CAN_MCR_AEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_AEN), uint32_t) & BM_CAN_MCR_AEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the AEN field to a new value.
-#define BW_CAN_MCR_AEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_AEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_MCR, field LPRIOEN[13] (RW)
- *
- * This bit is provided for backwards compatibility with legacy applications. It
- * controls whether the local priority feature is enabled or not. It is used to
- * expand the ID used during the arbitration process. With this expanded ID
- * concept, the arbitration process is done based on the full 32-bit word, but the
- * actual transmitted ID still has 11-bit for standard frames and 29-bit for
- * extended frames. This bit can be written only in Freeze mode because it is blocked by
- * hardware in other modes.
- *
- * Values:
- * - 0 - Local Priority disabled.
- * - 1 - Local Priority enabled.
- */
-//@{
-#define BP_CAN_MCR_LPRIOEN (13U) //!< Bit position for CAN_MCR_LPRIOEN.
-#define BM_CAN_MCR_LPRIOEN (0x00002000U) //!< Bit mask for CAN_MCR_LPRIOEN.
-#define BS_CAN_MCR_LPRIOEN (1U) //!< Bit field size in bits for CAN_MCR_LPRIOEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_MCR_LPRIOEN field.
-#define BR_CAN_MCR_LPRIOEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPRIOEN))
-#endif
-
-//! @brief Format value for bitfield CAN_MCR_LPRIOEN.
-#define BF_CAN_MCR_LPRIOEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_LPRIOEN), uint32_t) & BM_CAN_MCR_LPRIOEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LPRIOEN field to a new value.
-#define BW_CAN_MCR_LPRIOEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPRIOEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_MCR, field IRMQ[16] (RW)
- *
- * This bit indicates whether Rx matching process will be based either on
- * individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and
- * RX15MASK, RXFGMASK. This bit can be written only in Freeze mode because it is
- * blocked by hardware in other modes.
- *
- * Values:
- * - 0 - Individual Rx masking and queue feature are disabled. For backward
- * compatibility with legacy applications, the reading of C/S word locks the MB
- * even if it is EMPTY.
- * - 1 - Individual Rx masking and queue feature are enabled.
- */
-//@{
-#define BP_CAN_MCR_IRMQ (16U) //!< Bit position for CAN_MCR_IRMQ.
-#define BM_CAN_MCR_IRMQ (0x00010000U) //!< Bit mask for CAN_MCR_IRMQ.
-#define BS_CAN_MCR_IRMQ (1U) //!< Bit field size in bits for CAN_MCR_IRMQ.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_MCR_IRMQ field.
-#define BR_CAN_MCR_IRMQ(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_IRMQ))
-#endif
-
-//! @brief Format value for bitfield CAN_MCR_IRMQ.
-#define BF_CAN_MCR_IRMQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_IRMQ), uint32_t) & BM_CAN_MCR_IRMQ)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IRMQ field to a new value.
-#define BW_CAN_MCR_IRMQ(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_IRMQ) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_MCR, field SRXDIS[17] (RW)
- *
- * This bit defines whether FlexCAN is allowed to receive frames transmitted by
- * itself. If this bit is asserted, frames transmitted by the module will not be
- * stored in any MB, regardless if the MB is programmed with an ID that matches
- * the transmitted frame, and no interrupt flag or interrupt signal will be
- * generated due to the frame reception. This bit can be written only in Freeze mode
- * because it is blocked by hardware in other modes.
- *
- * Values:
- * - 0 - Self reception enabled.
- * - 1 - Self reception disabled.
- */
-//@{
-#define BP_CAN_MCR_SRXDIS (17U) //!< Bit position for CAN_MCR_SRXDIS.
-#define BM_CAN_MCR_SRXDIS (0x00020000U) //!< Bit mask for CAN_MCR_SRXDIS.
-#define BS_CAN_MCR_SRXDIS (1U) //!< Bit field size in bits for CAN_MCR_SRXDIS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_MCR_SRXDIS field.
-#define BR_CAN_MCR_SRXDIS(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SRXDIS))
-#endif
-
-//! @brief Format value for bitfield CAN_MCR_SRXDIS.
-#define BF_CAN_MCR_SRXDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_SRXDIS), uint32_t) & BM_CAN_MCR_SRXDIS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SRXDIS field to a new value.
-#define BW_CAN_MCR_SRXDIS(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SRXDIS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_MCR, field WAKSRC[19] (RW)
- *
- * This bit defines whether the integrated low-pass filter is applied to protect
- * the Rx CAN input from spurious wake up. This bit can be written only in
- * Freeze mode because it is blocked by hardware in other modes.
- *
- * Values:
- * - 0 - FlexCAN uses the unfiltered Rx input to detect recessive to dominant
- * edges on the CAN bus.
- * - 1 - FlexCAN uses the filtered Rx input to detect recessive to dominant
- * edges on the CAN bus.
- */
-//@{
-#define BP_CAN_MCR_WAKSRC (19U) //!< Bit position for CAN_MCR_WAKSRC.
-#define BM_CAN_MCR_WAKSRC (0x00080000U) //!< Bit mask for CAN_MCR_WAKSRC.
-#define BS_CAN_MCR_WAKSRC (1U) //!< Bit field size in bits for CAN_MCR_WAKSRC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_MCR_WAKSRC field.
-#define BR_CAN_MCR_WAKSRC(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKSRC))
-#endif
-
-//! @brief Format value for bitfield CAN_MCR_WAKSRC.
-#define BF_CAN_MCR_WAKSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_WAKSRC), uint32_t) & BM_CAN_MCR_WAKSRC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WAKSRC field to a new value.
-#define BW_CAN_MCR_WAKSRC(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKSRC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_MCR, field LPMACK[20] (RO)
- *
- * This read-only bit indicates that FlexCAN is in a low-power mode (Disable
- * mode , Stop mode ). A low-power mode cannot be entered until all current
- * transmission or reception processes have finished, so the CPU can poll the LPMACK bit
- * to know when FlexCAN has actually entered low power mode. LPMACK will be
- * asserted within 180 CAN bits from the low-power mode request by the CPU, and
- * negated within 2 CAN bits after the low-power mode request removal (see Section
- * "Protocol Timing").
- *
- * Values:
- * - 0 - FlexCAN is not in a low-power mode.
- * - 1 - FlexCAN is in a low-power mode.
- */
-//@{
-#define BP_CAN_MCR_LPMACK (20U) //!< Bit position for CAN_MCR_LPMACK.
-#define BM_CAN_MCR_LPMACK (0x00100000U) //!< Bit mask for CAN_MCR_LPMACK.
-#define BS_CAN_MCR_LPMACK (1U) //!< Bit field size in bits for CAN_MCR_LPMACK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_MCR_LPMACK field.
-#define BR_CAN_MCR_LPMACK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPMACK))
-#endif
-//@}
-
-/*!
- * @name Register CAN_MCR, field WRNEN[21] (RW)
- *
- * When asserted, this bit enables the generation of the TWRNINT and RWRNINT
- * flags in the Error and Status Register. If WRNEN is negated, the TWRNINT and
- * RWRNINT flags will always be zero, independent of the values of the error
- * counters, and no warning interrupt will ever be generated. This bit can be written
- * only in Freeze mode because it is blocked by hardware in other modes.
- *
- * Values:
- * - 0 - TWRNINT and RWRNINT bits are zero, independent of the values in the
- * error counters.
- * - 1 - TWRNINT and RWRNINT bits are set when the respective error counter
- * transitions from less than 96 to greater than or equal to 96.
- */
-//@{
-#define BP_CAN_MCR_WRNEN (21U) //!< Bit position for CAN_MCR_WRNEN.
-#define BM_CAN_MCR_WRNEN (0x00200000U) //!< Bit mask for CAN_MCR_WRNEN.
-#define BS_CAN_MCR_WRNEN (1U) //!< Bit field size in bits for CAN_MCR_WRNEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_MCR_WRNEN field.
-#define BR_CAN_MCR_WRNEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WRNEN))
-#endif
-
-//! @brief Format value for bitfield CAN_MCR_WRNEN.
-#define BF_CAN_MCR_WRNEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_WRNEN), uint32_t) & BM_CAN_MCR_WRNEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WRNEN field to a new value.
-#define BW_CAN_MCR_WRNEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WRNEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_MCR, field SLFWAK[22] (RW)
- *
- * This bit enables the Self Wake Up feature when FlexCAN is in a low-power mode
- * other than Disable mode. When this feature is enabled, the FlexCAN module
- * monitors the bus for wake up event, that is, a recessive-to-dominant transition.
- * If a wake up event is detected during Stop mode, then FlexCAN generates, if
- * enabled to do so, a Wake Up interrupt to the CPU so that it can exit Stop mode
- * globally and FlexCAN can request to resume the clocks. When FlexCAN is in a
- * low-power mode other than Disable mode, this bit cannot be written as it is
- * blocked by hardware.
- *
- * Values:
- * - 0 - FlexCAN Self Wake Up feature is disabled.
- * - 1 - FlexCAN Self Wake Up feature is enabled.
- */
-//@{
-#define BP_CAN_MCR_SLFWAK (22U) //!< Bit position for CAN_MCR_SLFWAK.
-#define BM_CAN_MCR_SLFWAK (0x00400000U) //!< Bit mask for CAN_MCR_SLFWAK.
-#define BS_CAN_MCR_SLFWAK (1U) //!< Bit field size in bits for CAN_MCR_SLFWAK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_MCR_SLFWAK field.
-#define BR_CAN_MCR_SLFWAK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SLFWAK))
-#endif
-
-//! @brief Format value for bitfield CAN_MCR_SLFWAK.
-#define BF_CAN_MCR_SLFWAK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_SLFWAK), uint32_t) & BM_CAN_MCR_SLFWAK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SLFWAK field to a new value.
-#define BW_CAN_MCR_SLFWAK(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SLFWAK) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_MCR, field SUPV[23] (RW)
- *
- * This bit configures the FlexCAN to be either in Supervisor or User mode. The
- * registers affected by this bit are marked as S/U in the Access Type column of
- * the module memory map. Reset value of this bit is 1, so the affected registers
- * start with Supervisor access allowance only . This bit can be written only in
- * Freeze mode because it is blocked by hardware in other modes.
- *
- * Values:
- * - 0 - FlexCAN is in User mode. Affected registers allow both Supervisor and
- * Unrestricted accesses .
- * - 1 - FlexCAN is in Supervisor mode. Affected registers allow only Supervisor
- * access. Unrestricted access behaves as though the access was done to an
- * unimplemented register location .
- */
-//@{
-#define BP_CAN_MCR_SUPV (23U) //!< Bit position for CAN_MCR_SUPV.
-#define BM_CAN_MCR_SUPV (0x00800000U) //!< Bit mask for CAN_MCR_SUPV.
-#define BS_CAN_MCR_SUPV (1U) //!< Bit field size in bits for CAN_MCR_SUPV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_MCR_SUPV field.
-#define BR_CAN_MCR_SUPV(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SUPV))
-#endif
-
-//! @brief Format value for bitfield CAN_MCR_SUPV.
-#define BF_CAN_MCR_SUPV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_SUPV), uint32_t) & BM_CAN_MCR_SUPV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SUPV field to a new value.
-#define BW_CAN_MCR_SUPV(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SUPV) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_MCR, field FRZACK[24] (RO)
- *
- * This read-only bit indicates that FlexCAN is in Freeze mode and its prescaler
- * is stopped. The Freeze mode request cannot be granted until current
- * transmission or reception processes have finished. Therefore the software can poll the
- * FRZACK bit to know when FlexCAN has actually entered Freeze mode. If Freeze
- * Mode request is negated, then this bit is negated after the FlexCAN prescaler is
- * running again. If Freeze mode is requested while FlexCAN is in a low power
- * mode, then the FRZACK bit will be set only when the low-power mode is exited.
- * See Section "Freeze Mode". FRZACK will be asserted within 178 CAN bits from the
- * freeze mode request by the CPU, and negated within 2 CAN bits after the freeze
- * mode request removal (see Section "Protocol Timing").
- *
- * Values:
- * - 0 - FlexCAN not in Freeze mode, prescaler running.
- * - 1 - FlexCAN in Freeze mode, prescaler stopped.
- */
-//@{
-#define BP_CAN_MCR_FRZACK (24U) //!< Bit position for CAN_MCR_FRZACK.
-#define BM_CAN_MCR_FRZACK (0x01000000U) //!< Bit mask for CAN_MCR_FRZACK.
-#define BS_CAN_MCR_FRZACK (1U) //!< Bit field size in bits for CAN_MCR_FRZACK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_MCR_FRZACK field.
-#define BR_CAN_MCR_FRZACK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZACK))
-#endif
-//@}
-
-/*!
- * @name Register CAN_MCR, field SOFTRST[25] (RW)
- *
- * When this bit is asserted, FlexCAN resets its internal state machines and
- * some of the memory mapped registers. The following registers are reset: MCR
- * (except the MDIS bit), TIMER , ECR, ESR1, ESR2, IMASK1, IMASK2, IFLAG1, IFLAG2 and
- * CRCR. Configuration registers that control the interface to the CAN bus are
- * not affected by soft reset. The following registers are unaffected: CTRL1,
- * CTRL2, all RXIMR registers, RXMGMASK, RX14MASK, RX15MASK, RXFGMASK, RXFIR, all
- * Message Buffers . The SOFTRST bit can be asserted directly by the CPU when it
- * writes to the MCR Register, but it is also asserted when global soft reset is
- * requested at MCU level . Because soft reset is synchronous and has to follow a
- * request/acknowledge procedure across clock domains, it may take some time to
- * fully propagate its effect. The SOFTRST bit remains asserted while reset is
- * pending, and is automatically negated when reset completes. Therefore, software can
- * poll this bit to know when the soft reset has completed. Soft reset cannot be
- * applied while clocks are shut down in a low power mode. The module should be
- * first removed from low power mode, and then soft reset can be applied.
- *
- * Values:
- * - 0 - No reset request.
- * - 1 - Resets the registers affected by soft reset.
- */
-//@{
-#define BP_CAN_MCR_SOFTRST (25U) //!< Bit position for CAN_MCR_SOFTRST.
-#define BM_CAN_MCR_SOFTRST (0x02000000U) //!< Bit mask for CAN_MCR_SOFTRST.
-#define BS_CAN_MCR_SOFTRST (1U) //!< Bit field size in bits for CAN_MCR_SOFTRST.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_MCR_SOFTRST field.
-#define BR_CAN_MCR_SOFTRST(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SOFTRST))
-#endif
-
-//! @brief Format value for bitfield CAN_MCR_SOFTRST.
-#define BF_CAN_MCR_SOFTRST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_SOFTRST), uint32_t) & BM_CAN_MCR_SOFTRST)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SOFTRST field to a new value.
-#define BW_CAN_MCR_SOFTRST(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SOFTRST) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_MCR, field WAKMSK[26] (RW)
- *
- * This bit enables the Wake Up Interrupt generation under Self Wake Up
- * mechanism.
- *
- * Values:
- * - 0 - Wake Up Interrupt is disabled.
- * - 1 - Wake Up Interrupt is enabled.
- */
-//@{
-#define BP_CAN_MCR_WAKMSK (26U) //!< Bit position for CAN_MCR_WAKMSK.
-#define BM_CAN_MCR_WAKMSK (0x04000000U) //!< Bit mask for CAN_MCR_WAKMSK.
-#define BS_CAN_MCR_WAKMSK (1U) //!< Bit field size in bits for CAN_MCR_WAKMSK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_MCR_WAKMSK field.
-#define BR_CAN_MCR_WAKMSK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKMSK))
-#endif
-
-//! @brief Format value for bitfield CAN_MCR_WAKMSK.
-#define BF_CAN_MCR_WAKMSK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_WAKMSK), uint32_t) & BM_CAN_MCR_WAKMSK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WAKMSK field to a new value.
-#define BW_CAN_MCR_WAKMSK(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKMSK) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_MCR, field NOTRDY[27] (RO)
- *
- * This read-only bit indicates that FlexCAN is either in Disable mode , Stop
- * mode or Freeze mode. It is negated once FlexCAN has exited these modes.
- *
- * Values:
- * - 0 - FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back
- * mode.
- * - 1 - FlexCAN module is either in Disable mode , Stop mode or Freeze mode.
- */
-//@{
-#define BP_CAN_MCR_NOTRDY (27U) //!< Bit position for CAN_MCR_NOTRDY.
-#define BM_CAN_MCR_NOTRDY (0x08000000U) //!< Bit mask for CAN_MCR_NOTRDY.
-#define BS_CAN_MCR_NOTRDY (1U) //!< Bit field size in bits for CAN_MCR_NOTRDY.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_MCR_NOTRDY field.
-#define BR_CAN_MCR_NOTRDY(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_NOTRDY))
-#endif
-//@}
-
-/*!
- * @name Register CAN_MCR, field HALT[28] (RW)
- *
- * Assertion of this bit puts the FlexCAN module into Freeze mode. The CPU
- * should clear it after initializing the Message Buffers and Control Register. No
- * reception or transmission is performed by FlexCAN before this bit is cleared.
- * Freeze mode cannot be entered while FlexCAN is in a low power mode.
- *
- * Values:
- * - 0 - No Freeze mode request.
- * - 1 - Enters Freeze mode if the FRZ bit is asserted.
- */
-//@{
-#define BP_CAN_MCR_HALT (28U) //!< Bit position for CAN_MCR_HALT.
-#define BM_CAN_MCR_HALT (0x10000000U) //!< Bit mask for CAN_MCR_HALT.
-#define BS_CAN_MCR_HALT (1U) //!< Bit field size in bits for CAN_MCR_HALT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_MCR_HALT field.
-#define BR_CAN_MCR_HALT(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_HALT))
-#endif
-
-//! @brief Format value for bitfield CAN_MCR_HALT.
-#define BF_CAN_MCR_HALT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_HALT), uint32_t) & BM_CAN_MCR_HALT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the HALT field to a new value.
-#define BW_CAN_MCR_HALT(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_HALT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_MCR, field RFEN[29] (RW)
- *
- * This bit controls whether the Rx FIFO feature is enabled or not. When RFEN is
- * set, MBs 0 to 5 cannot be used for normal reception and transmission because
- * the corresponding memory region (0x80-0xDC) is used by the FIFO engine as well
- * as additional MBs (up to 32, depending on CTRL2[RFFN] setting) which are used
- * as Rx FIFO ID Filter Table elements. RFEN also impacts the definition of the
- * minimum number of peripheral clocks per CAN bit as described in the table
- * "Minimum Ratio Between Peripheral Clock Frequency and CAN Bit Rate" (in section
- * "Arbitration and Matching Timing"). This bit can be written only in Freeze mode
- * because it is blocked by hardware in other modes.
- *
- * Values:
- * - 0 - Rx FIFO not enabled.
- * - 1 - Rx FIFO enabled.
- */
-//@{
-#define BP_CAN_MCR_RFEN (29U) //!< Bit position for CAN_MCR_RFEN.
-#define BM_CAN_MCR_RFEN (0x20000000U) //!< Bit mask for CAN_MCR_RFEN.
-#define BS_CAN_MCR_RFEN (1U) //!< Bit field size in bits for CAN_MCR_RFEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_MCR_RFEN field.
-#define BR_CAN_MCR_RFEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_RFEN))
-#endif
-
-//! @brief Format value for bitfield CAN_MCR_RFEN.
-#define BF_CAN_MCR_RFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_RFEN), uint32_t) & BM_CAN_MCR_RFEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RFEN field to a new value.
-#define BW_CAN_MCR_RFEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_RFEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_MCR, field FRZ[30] (RW)
- *
- * The FRZ bit specifies the FlexCAN behavior when the HALT bit in the MCR
- * Register is set or when Debug mode is requested at MCU level . When FRZ is
- * asserted, FlexCAN is enabled to enter Freeze mode. Negation of this bit field causes
- * FlexCAN to exit from Freeze mode.
- *
- * Values:
- * - 0 - Not enabled to enter Freeze mode.
- * - 1 - Enabled to enter Freeze mode.
- */
-//@{
-#define BP_CAN_MCR_FRZ (30U) //!< Bit position for CAN_MCR_FRZ.
-#define BM_CAN_MCR_FRZ (0x40000000U) //!< Bit mask for CAN_MCR_FRZ.
-#define BS_CAN_MCR_FRZ (1U) //!< Bit field size in bits for CAN_MCR_FRZ.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_MCR_FRZ field.
-#define BR_CAN_MCR_FRZ(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZ))
-#endif
-
-//! @brief Format value for bitfield CAN_MCR_FRZ.
-#define BF_CAN_MCR_FRZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_FRZ), uint32_t) & BM_CAN_MCR_FRZ)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FRZ field to a new value.
-#define BW_CAN_MCR_FRZ(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZ) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_MCR, field MDIS[31] (RW)
- *
- * This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN
- * disables the clocks to the CAN Protocol Engine and Controller Host Interface
- * sub-modules. This is the only bit within this register not affected by soft
- * reset.
- *
- * Values:
- * - 0 - Enable the FlexCAN module.
- * - 1 - Disable the FlexCAN module.
- */
-//@{
-#define BP_CAN_MCR_MDIS (31U) //!< Bit position for CAN_MCR_MDIS.
-#define BM_CAN_MCR_MDIS (0x80000000U) //!< Bit mask for CAN_MCR_MDIS.
-#define BS_CAN_MCR_MDIS (1U) //!< Bit field size in bits for CAN_MCR_MDIS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_MCR_MDIS field.
-#define BR_CAN_MCR_MDIS(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_MDIS))
-#endif
-
-//! @brief Format value for bitfield CAN_MCR_MDIS.
-#define BF_CAN_MCR_MDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_MDIS), uint32_t) & BM_CAN_MCR_MDIS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MDIS field to a new value.
-#define BW_CAN_MCR_MDIS(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_MDIS) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CAN_CTRL1 - Control 1 register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAN_CTRL1 - Control 1 register (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register is defined for specific FlexCAN control features related to the
- * CAN bus, such as bit-rate, programmable sampling point within an Rx bit, Loop
- * Back mode, Listen-Only mode, Bus Off recovery behavior and interrupt enabling
- * (Bus-Off, Error, Warning). It also determines the Division Factor for the
- * clock prescaler.
- */
-typedef union _hw_can_ctrl1
-{
- uint32_t U;
- struct _hw_can_ctrl1_bitfields
- {
- uint32_t PROPSEG : 3; //!< [2:0] Propagation Segment
- uint32_t LOM : 1; //!< [3] Listen-Only Mode
- uint32_t LBUF : 1; //!< [4] Lowest Buffer Transmitted First
- uint32_t TSYN : 1; //!< [5] Timer Sync
- uint32_t BOFFREC : 1; //!< [6] Bus Off Recovery
- uint32_t SMP : 1; //!< [7] CAN Bit Sampling
- uint32_t RESERVED0 : 2; //!< [9:8]
- uint32_t RWRNMSK : 1; //!< [10] Rx Warning Interrupt Mask
- uint32_t TWRNMSK : 1; //!< [11] Tx Warning Interrupt Mask
- uint32_t LPB : 1; //!< [12] Loop Back Mode
- uint32_t CLKSRC : 1; //!< [13] CAN Engine Clock Source
- uint32_t ERRMSK : 1; //!< [14] Error Mask
- uint32_t BOFFMSK : 1; //!< [15] Bus Off Mask
- uint32_t PSEG2 : 3; //!< [18:16] Phase Segment 2
- uint32_t PSEG1 : 3; //!< [21:19] Phase Segment 1
- uint32_t RJW : 2; //!< [23:22] Resync Jump Width
- uint32_t PRESDIV : 8; //!< [31:24] Prescaler Division Factor
- } B;
-} hw_can_ctrl1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAN_CTRL1 register
- */
-//@{
-#define HW_CAN_CTRL1_ADDR(x) (REGS_CAN_BASE(x) + 0x4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAN_CTRL1(x) (*(__IO hw_can_ctrl1_t *) HW_CAN_CTRL1_ADDR(x))
-#define HW_CAN_CTRL1_RD(x) (HW_CAN_CTRL1(x).U)
-#define HW_CAN_CTRL1_WR(x, v) (HW_CAN_CTRL1(x).U = (v))
-#define HW_CAN_CTRL1_SET(x, v) (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) | (v)))
-#define HW_CAN_CTRL1_CLR(x, v) (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) & ~(v)))
-#define HW_CAN_CTRL1_TOG(x, v) (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAN_CTRL1 bitfields
- */
-
-/*!
- * @name Register CAN_CTRL1, field PROPSEG[2:0] (RW)
- *
- * This 3-bit field defines the length of the Propagation Segment in the bit
- * time. The valid programmable values are 0-7. This field can be written only in
- * Freeze mode because it is blocked by hardware in other modes. Propagation
- * Segment Time = (PROPSEG + 1) * Time-Quanta. Time-Quantum = one Sclock period.
- */
-//@{
-#define BP_CAN_CTRL1_PROPSEG (0U) //!< Bit position for CAN_CTRL1_PROPSEG.
-#define BM_CAN_CTRL1_PROPSEG (0x00000007U) //!< Bit mask for CAN_CTRL1_PROPSEG.
-#define BS_CAN_CTRL1_PROPSEG (3U) //!< Bit field size in bits for CAN_CTRL1_PROPSEG.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CTRL1_PROPSEG field.
-#define BR_CAN_CTRL1_PROPSEG(x) (HW_CAN_CTRL1(x).B.PROPSEG)
-#endif
-
-//! @brief Format value for bitfield CAN_CTRL1_PROPSEG.
-#define BF_CAN_CTRL1_PROPSEG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_PROPSEG), uint32_t) & BM_CAN_CTRL1_PROPSEG)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PROPSEG field to a new value.
-#define BW_CAN_CTRL1_PROPSEG(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PROPSEG) | BF_CAN_CTRL1_PROPSEG(v)))
-#endif
-//@}
-
-/*!
- * @name Register CAN_CTRL1, field LOM[3] (RW)
- *
- * This bit configures FlexCAN to operate in Listen-Only mode. In this mode,
- * transmission is disabled, all error counters are frozen and the module operates
- * in a CAN Error Passive mode. Only messages acknowledged by another CAN station
- * will be received. If FlexCAN detects a message that has not been acknowledged,
- * it will flag a BIT0 error without changing the REC, as if it was trying to
- * acknowledge the message. Listen-Only mode acknowledgement can be obtained by the
- * state of ESR1[FLTCONF] field which is Passive Error when Listen-Only mode is
- * entered. There can be some delay between the Listen-Only mode request and
- * acknowledge. This bit can be written only in Freeze mode because it is blocked by
- * hardware in other modes.
- *
- * Values:
- * - 0 - Listen-Only mode is deactivated.
- * - 1 - FlexCAN module operates in Listen-Only mode.
- */
-//@{
-#define BP_CAN_CTRL1_LOM (3U) //!< Bit position for CAN_CTRL1_LOM.
-#define BM_CAN_CTRL1_LOM (0x00000008U) //!< Bit mask for CAN_CTRL1_LOM.
-#define BS_CAN_CTRL1_LOM (1U) //!< Bit field size in bits for CAN_CTRL1_LOM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CTRL1_LOM field.
-#define BR_CAN_CTRL1_LOM(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LOM))
-#endif
-
-//! @brief Format value for bitfield CAN_CTRL1_LOM.
-#define BF_CAN_CTRL1_LOM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_LOM), uint32_t) & BM_CAN_CTRL1_LOM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LOM field to a new value.
-#define BW_CAN_CTRL1_LOM(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LOM) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_CTRL1, field LBUF[4] (RW)
- *
- * This bit defines the ordering mechanism for Message Buffer transmission. When
- * asserted, the LPRIOEN bit does not affect the priority arbitration. This bit
- * can be written only in Freeze mode because it is blocked by hardware in other
- * modes.
- *
- * Values:
- * - 0 - Buffer with highest priority is transmitted first.
- * - 1 - Lowest number buffer is transmitted first.
- */
-//@{
-#define BP_CAN_CTRL1_LBUF (4U) //!< Bit position for CAN_CTRL1_LBUF.
-#define BM_CAN_CTRL1_LBUF (0x00000010U) //!< Bit mask for CAN_CTRL1_LBUF.
-#define BS_CAN_CTRL1_LBUF (1U) //!< Bit field size in bits for CAN_CTRL1_LBUF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CTRL1_LBUF field.
-#define BR_CAN_CTRL1_LBUF(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LBUF))
-#endif
-
-//! @brief Format value for bitfield CAN_CTRL1_LBUF.
-#define BF_CAN_CTRL1_LBUF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_LBUF), uint32_t) & BM_CAN_CTRL1_LBUF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LBUF field to a new value.
-#define BW_CAN_CTRL1_LBUF(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LBUF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_CTRL1, field TSYN[5] (RW)
- *
- * This bit enables a mechanism that resets the free-running timer each time a
- * message is received in Message Buffer 0. This feature provides means to
- * synchronize multiple FlexCAN stations with a special "SYNC" message, that is, global
- * network time. If the RFEN bit in MCR is set (Rx FIFO enabled), the first
- * available Mailbox, according to CTRL2[RFFN] setting, is used for timer
- * synchronization instead of MB0. This bit can be written only in Freeze mode because it is
- * blocked by hardware in other modes.
- *
- * Values:
- * - 0 - Timer Sync feature disabled
- * - 1 - Timer Sync feature enabled
- */
-//@{
-#define BP_CAN_CTRL1_TSYN (5U) //!< Bit position for CAN_CTRL1_TSYN.
-#define BM_CAN_CTRL1_TSYN (0x00000020U) //!< Bit mask for CAN_CTRL1_TSYN.
-#define BS_CAN_CTRL1_TSYN (1U) //!< Bit field size in bits for CAN_CTRL1_TSYN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CTRL1_TSYN field.
-#define BR_CAN_CTRL1_TSYN(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TSYN))
-#endif
-
-//! @brief Format value for bitfield CAN_CTRL1_TSYN.
-#define BF_CAN_CTRL1_TSYN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_TSYN), uint32_t) & BM_CAN_CTRL1_TSYN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TSYN field to a new value.
-#define BW_CAN_CTRL1_TSYN(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TSYN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_CTRL1, field BOFFREC[6] (RW)
- *
- * This bit defines how FlexCAN recovers from Bus Off state. If this bit is
- * negated, automatic recovering from Bus Off state occurs according to the CAN
- * Specification 2.0B. If the bit is asserted, automatic recovering from Bus Off is
- * disabled and the module remains in Bus Off state until the bit is negated by the
- * user. If the negation occurs before 128 sequences of 11 recessive bits are
- * detected on the CAN bus, then Bus Off recovery happens as if the BOFFREC bit had
- * never been asserted. If the negation occurs after 128 sequences of 11
- * recessive bits occurred, then FlexCAN will re-synchronize to the bus by waiting for
- * 11 recessive bits before joining the bus. After negation, the BOFFREC bit can
- * be re-asserted again during Bus Off, but it will be effective only the next
- * time the module enters Bus Off. If BOFFREC was negated when the module entered
- * Bus Off, asserting it during Bus Off will not be effective for the current Bus
- * Off recovery.
- *
- * Values:
- * - 0 - Automatic recovering from Bus Off state enabled, according to CAN Spec
- * 2.0 part B.
- * - 1 - Automatic recovering from Bus Off state disabled.
- */
-//@{
-#define BP_CAN_CTRL1_BOFFREC (6U) //!< Bit position for CAN_CTRL1_BOFFREC.
-#define BM_CAN_CTRL1_BOFFREC (0x00000040U) //!< Bit mask for CAN_CTRL1_BOFFREC.
-#define BS_CAN_CTRL1_BOFFREC (1U) //!< Bit field size in bits for CAN_CTRL1_BOFFREC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CTRL1_BOFFREC field.
-#define BR_CAN_CTRL1_BOFFREC(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFREC))
-#endif
-
-//! @brief Format value for bitfield CAN_CTRL1_BOFFREC.
-#define BF_CAN_CTRL1_BOFFREC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_BOFFREC), uint32_t) & BM_CAN_CTRL1_BOFFREC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BOFFREC field to a new value.
-#define BW_CAN_CTRL1_BOFFREC(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFREC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_CTRL1, field SMP[7] (RW)
- *
- * This bit defines the sampling mode of CAN bits at the Rx input. This bit can
- * be written only in Freeze mode because it is blocked by hardware in other
- * modes.
- *
- * Values:
- * - 0 - Just one sample is used to determine the bit value.
- * - 1 - Three samples are used to determine the value of the received bit: the
- * regular one (sample point) and 2 preceding samples; a majority rule is
- * used.
- */
-//@{
-#define BP_CAN_CTRL1_SMP (7U) //!< Bit position for CAN_CTRL1_SMP.
-#define BM_CAN_CTRL1_SMP (0x00000080U) //!< Bit mask for CAN_CTRL1_SMP.
-#define BS_CAN_CTRL1_SMP (1U) //!< Bit field size in bits for CAN_CTRL1_SMP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CTRL1_SMP field.
-#define BR_CAN_CTRL1_SMP(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_SMP))
-#endif
-
-//! @brief Format value for bitfield CAN_CTRL1_SMP.
-#define BF_CAN_CTRL1_SMP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_SMP), uint32_t) & BM_CAN_CTRL1_SMP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SMP field to a new value.
-#define BW_CAN_CTRL1_SMP(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_SMP) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_CTRL1, field RWRNMSK[10] (RW)
- *
- * This bit provides a mask for the Rx Warning Interrupt associated with the
- * RWRNINT flag in the Error and Status Register. This bit is read as zero when
- * MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
- * asserted.
- *
- * Values:
- * - 0 - Rx Warning Interrupt disabled.
- * - 1 - Rx Warning Interrupt enabled.
- */
-//@{
-#define BP_CAN_CTRL1_RWRNMSK (10U) //!< Bit position for CAN_CTRL1_RWRNMSK.
-#define BM_CAN_CTRL1_RWRNMSK (0x00000400U) //!< Bit mask for CAN_CTRL1_RWRNMSK.
-#define BS_CAN_CTRL1_RWRNMSK (1U) //!< Bit field size in bits for CAN_CTRL1_RWRNMSK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CTRL1_RWRNMSK field.
-#define BR_CAN_CTRL1_RWRNMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_RWRNMSK))
-#endif
-
-//! @brief Format value for bitfield CAN_CTRL1_RWRNMSK.
-#define BF_CAN_CTRL1_RWRNMSK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_RWRNMSK), uint32_t) & BM_CAN_CTRL1_RWRNMSK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RWRNMSK field to a new value.
-#define BW_CAN_CTRL1_RWRNMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_RWRNMSK) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_CTRL1, field TWRNMSK[11] (RW)
- *
- * This bit provides a mask for the Tx Warning Interrupt associated with the
- * TWRNINT flag in the Error and Status Register. This bit is read as zero when
- * MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
- * asserted.
- *
- * Values:
- * - 0 - Tx Warning Interrupt disabled.
- * - 1 - Tx Warning Interrupt enabled.
- */
-//@{
-#define BP_CAN_CTRL1_TWRNMSK (11U) //!< Bit position for CAN_CTRL1_TWRNMSK.
-#define BM_CAN_CTRL1_TWRNMSK (0x00000800U) //!< Bit mask for CAN_CTRL1_TWRNMSK.
-#define BS_CAN_CTRL1_TWRNMSK (1U) //!< Bit field size in bits for CAN_CTRL1_TWRNMSK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CTRL1_TWRNMSK field.
-#define BR_CAN_CTRL1_TWRNMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TWRNMSK))
-#endif
-
-//! @brief Format value for bitfield CAN_CTRL1_TWRNMSK.
-#define BF_CAN_CTRL1_TWRNMSK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_TWRNMSK), uint32_t) & BM_CAN_CTRL1_TWRNMSK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TWRNMSK field to a new value.
-#define BW_CAN_CTRL1_TWRNMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TWRNMSK) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_CTRL1, field LPB[12] (RW)
- *
- * This bit configures FlexCAN to operate in Loop-Back mode. In this mode,
- * FlexCAN performs an internal loop back that can be used for self test operation.
- * The bit stream output of the transmitter is fed back internally to the receiver
- * input. The Rx CAN input pin is ignored and the Tx CAN output goes to the
- * recessive state (logic 1). FlexCAN behaves as it normally does when transmitting,
- * and treats its own transmitted message as a message received from a remote
- * node. In this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN
- * frame acknowledge field, generating an internal acknowledge bit to ensure proper
- * reception of its own message. Both transmit and receive interrupts are
- * generated. This bit can be written only in Freeze mode because it is blocked by
- * hardware in other modes. In this mode, the MCR[SRXDIS] cannot be asserted because
- * this will impede the self reception of a transmitted message.
- *
- * Values:
- * - 0 - Loop Back disabled.
- * - 1 - Loop Back enabled.
- */
-//@{
-#define BP_CAN_CTRL1_LPB (12U) //!< Bit position for CAN_CTRL1_LPB.
-#define BM_CAN_CTRL1_LPB (0x00001000U) //!< Bit mask for CAN_CTRL1_LPB.
-#define BS_CAN_CTRL1_LPB (1U) //!< Bit field size in bits for CAN_CTRL1_LPB.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CTRL1_LPB field.
-#define BR_CAN_CTRL1_LPB(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LPB))
-#endif
-
-//! @brief Format value for bitfield CAN_CTRL1_LPB.
-#define BF_CAN_CTRL1_LPB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_LPB), uint32_t) & BM_CAN_CTRL1_LPB)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LPB field to a new value.
-#define BW_CAN_CTRL1_LPB(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LPB) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_CTRL1, field CLKSRC[13] (RW)
- *
- * This bit selects the clock source to the CAN Protocol Engine (PE) to be
- * either the peripheral clock (driven by the PLL) or the crystal oscillator clock.
- * The selected clock is the one fed to the prescaler to generate the Serial Clock
- * (Sclock). In order to guarantee reliable operation, this bit can be written
- * only in Disable mode because it is blocked by hardware in other modes. See
- * Section "Protocol Timing".
- *
- * Values:
- * - 0 - The CAN engine clock source is the oscillator clock. Under this
- * condition, the oscillator clock frequency must be lower than the bus clock.
- * - 1 - The CAN engine clock source is the peripheral clock.
- */
-//@{
-#define BP_CAN_CTRL1_CLKSRC (13U) //!< Bit position for CAN_CTRL1_CLKSRC.
-#define BM_CAN_CTRL1_CLKSRC (0x00002000U) //!< Bit mask for CAN_CTRL1_CLKSRC.
-#define BS_CAN_CTRL1_CLKSRC (1U) //!< Bit field size in bits for CAN_CTRL1_CLKSRC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CTRL1_CLKSRC field.
-#define BR_CAN_CTRL1_CLKSRC(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_CLKSRC))
-#endif
-
-//! @brief Format value for bitfield CAN_CTRL1_CLKSRC.
-#define BF_CAN_CTRL1_CLKSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_CLKSRC), uint32_t) & BM_CAN_CTRL1_CLKSRC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CLKSRC field to a new value.
-#define BW_CAN_CTRL1_CLKSRC(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_CLKSRC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_CTRL1, field ERRMSK[14] (RW)
- *
- * This bit provides a mask for the Error Interrupt.
- *
- * Values:
- * - 0 - Error interrupt disabled.
- * - 1 - Error interrupt enabled.
- */
-//@{
-#define BP_CAN_CTRL1_ERRMSK (14U) //!< Bit position for CAN_CTRL1_ERRMSK.
-#define BM_CAN_CTRL1_ERRMSK (0x00004000U) //!< Bit mask for CAN_CTRL1_ERRMSK.
-#define BS_CAN_CTRL1_ERRMSK (1U) //!< Bit field size in bits for CAN_CTRL1_ERRMSK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CTRL1_ERRMSK field.
-#define BR_CAN_CTRL1_ERRMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_ERRMSK))
-#endif
-
-//! @brief Format value for bitfield CAN_CTRL1_ERRMSK.
-#define BF_CAN_CTRL1_ERRMSK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_ERRMSK), uint32_t) & BM_CAN_CTRL1_ERRMSK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERRMSK field to a new value.
-#define BW_CAN_CTRL1_ERRMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_ERRMSK) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_CTRL1, field BOFFMSK[15] (RW)
- *
- * This bit provides a mask for the Bus Off Interrupt.
- *
- * Values:
- * - 0 - Bus Off interrupt disabled.
- * - 1 - Bus Off interrupt enabled.
- */
-//@{
-#define BP_CAN_CTRL1_BOFFMSK (15U) //!< Bit position for CAN_CTRL1_BOFFMSK.
-#define BM_CAN_CTRL1_BOFFMSK (0x00008000U) //!< Bit mask for CAN_CTRL1_BOFFMSK.
-#define BS_CAN_CTRL1_BOFFMSK (1U) //!< Bit field size in bits for CAN_CTRL1_BOFFMSK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CTRL1_BOFFMSK field.
-#define BR_CAN_CTRL1_BOFFMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFMSK))
-#endif
-
-//! @brief Format value for bitfield CAN_CTRL1_BOFFMSK.
-#define BF_CAN_CTRL1_BOFFMSK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_BOFFMSK), uint32_t) & BM_CAN_CTRL1_BOFFMSK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BOFFMSK field to a new value.
-#define BW_CAN_CTRL1_BOFFMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFMSK) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_CTRL1, field PSEG2[18:16] (RW)
- *
- * This 3-bit field defines the length of Phase Buffer Segment 2 in the bit
- * time. The valid programmable values are 1-7. This field can be written only in
- * Freeze mode because it is blocked by hardware in other modes. Phase Buffer
- * Segment 2 = (PSEG2 + 1) * Time-Quanta.
- */
-//@{
-#define BP_CAN_CTRL1_PSEG2 (16U) //!< Bit position for CAN_CTRL1_PSEG2.
-#define BM_CAN_CTRL1_PSEG2 (0x00070000U) //!< Bit mask for CAN_CTRL1_PSEG2.
-#define BS_CAN_CTRL1_PSEG2 (3U) //!< Bit field size in bits for CAN_CTRL1_PSEG2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CTRL1_PSEG2 field.
-#define BR_CAN_CTRL1_PSEG2(x) (HW_CAN_CTRL1(x).B.PSEG2)
-#endif
-
-//! @brief Format value for bitfield CAN_CTRL1_PSEG2.
-#define BF_CAN_CTRL1_PSEG2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_PSEG2), uint32_t) & BM_CAN_CTRL1_PSEG2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PSEG2 field to a new value.
-#define BW_CAN_CTRL1_PSEG2(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PSEG2) | BF_CAN_CTRL1_PSEG2(v)))
-#endif
-//@}
-
-/*!
- * @name Register CAN_CTRL1, field PSEG1[21:19] (RW)
- *
- * This 3-bit field defines the length of Phase Buffer Segment 1 in the bit
- * time. The valid programmable values are 0-7. This field can be written only in
- * Freeze mode because it is blocked by hardware in other modes. Phase Buffer
- * Segment 1 = (PSEG1 + 1) * Time-Quanta.
- */
-//@{
-#define BP_CAN_CTRL1_PSEG1 (19U) //!< Bit position for CAN_CTRL1_PSEG1.
-#define BM_CAN_CTRL1_PSEG1 (0x00380000U) //!< Bit mask for CAN_CTRL1_PSEG1.
-#define BS_CAN_CTRL1_PSEG1 (3U) //!< Bit field size in bits for CAN_CTRL1_PSEG1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CTRL1_PSEG1 field.
-#define BR_CAN_CTRL1_PSEG1(x) (HW_CAN_CTRL1(x).B.PSEG1)
-#endif
-
-//! @brief Format value for bitfield CAN_CTRL1_PSEG1.
-#define BF_CAN_CTRL1_PSEG1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_PSEG1), uint32_t) & BM_CAN_CTRL1_PSEG1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PSEG1 field to a new value.
-#define BW_CAN_CTRL1_PSEG1(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PSEG1) | BF_CAN_CTRL1_PSEG1(v)))
-#endif
-//@}
-
-/*!
- * @name Register CAN_CTRL1, field RJW[23:22] (RW)
- *
- * This 2-bit field defines the maximum number of time quanta that a bit time
- * can be changed by one re-synchronization. One time quantum is equal to the
- * Sclock period. The valid programmable values are 0-3. This field can be written
- * only in Freeze mode because it is blocked by hardware in other modes. Resync Jump
- * Width = RJW + 1.
- */
-//@{
-#define BP_CAN_CTRL1_RJW (22U) //!< Bit position for CAN_CTRL1_RJW.
-#define BM_CAN_CTRL1_RJW (0x00C00000U) //!< Bit mask for CAN_CTRL1_RJW.
-#define BS_CAN_CTRL1_RJW (2U) //!< Bit field size in bits for CAN_CTRL1_RJW.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CTRL1_RJW field.
-#define BR_CAN_CTRL1_RJW(x) (HW_CAN_CTRL1(x).B.RJW)
-#endif
-
-//! @brief Format value for bitfield CAN_CTRL1_RJW.
-#define BF_CAN_CTRL1_RJW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_RJW), uint32_t) & BM_CAN_CTRL1_RJW)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RJW field to a new value.
-#define BW_CAN_CTRL1_RJW(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_RJW) | BF_CAN_CTRL1_RJW(v)))
-#endif
-//@}
-
-/*!
- * @name Register CAN_CTRL1, field PRESDIV[31:24] (RW)
- *
- * This 8-bit field defines the ratio between the PE clock frequency and the
- * Serial Clock (Sclock) frequency. The Sclock period defines the time quantum of
- * the CAN protocol. For the reset value, the Sclock frequency is equal to the PE
- * clock frequency. The Maximum value of this field is 0xFF, that gives a minimum
- * Sclock frequency equal to the PE clock frequency divided by 256. See Section
- * "Protocol Timing". This field can be written only in Freeze mode because it is
- * blocked by hardware in other modes. Sclock frequency = PE clock frequency /
- * (PRESDIV + 1)
- */
-//@{
-#define BP_CAN_CTRL1_PRESDIV (24U) //!< Bit position for CAN_CTRL1_PRESDIV.
-#define BM_CAN_CTRL1_PRESDIV (0xFF000000U) //!< Bit mask for CAN_CTRL1_PRESDIV.
-#define BS_CAN_CTRL1_PRESDIV (8U) //!< Bit field size in bits for CAN_CTRL1_PRESDIV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CTRL1_PRESDIV field.
-#define BR_CAN_CTRL1_PRESDIV(x) (HW_CAN_CTRL1(x).B.PRESDIV)
-#endif
-
-//! @brief Format value for bitfield CAN_CTRL1_PRESDIV.
-#define BF_CAN_CTRL1_PRESDIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_PRESDIV), uint32_t) & BM_CAN_CTRL1_PRESDIV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PRESDIV field to a new value.
-#define BW_CAN_CTRL1_PRESDIV(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PRESDIV) | BF_CAN_CTRL1_PRESDIV(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CAN_TIMER - Free Running Timer
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAN_TIMER - Free Running Timer (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register represents a 16-bit free running counter that can be read and
- * written by the CPU. The timer starts from 0x0 after Reset, counts linearly to
- * 0xFFFF, and wraps around. The timer is clocked by the FlexCAN bit-clock, which
- * defines the baud rate on the CAN bus. During a message transmission/reception,
- * it increments by one for each bit that is received or transmitted. When there
- * is no message on the bus, it counts using the previously programmed baud
- * rate. The timer is not incremented during Disable , Stop, and Freeze modes. The
- * timer value is captured when the second bit of the identifier field of any frame
- * is on the CAN bus. This captured value is written into the Time Stamp entry
- * in a message buffer after a successful reception or transmission of a message.
- * If bit CTRL1[TSYN] is asserted, the Timer is reset whenever a message is
- * received in the first available Mailbox, according to CTRL2[RFFN] setting. The CPU
- * can write to this register anytime. However, if the write occurs at the same
- * time that the Timer is being reset by a reception in the first Mailbox, then
- * the write value is discarded. Reading this register affects the Mailbox
- * Unlocking procedure; see Section "Mailbox Lock Mechanism".
- */
-typedef union _hw_can_timer
-{
- uint32_t U;
- struct _hw_can_timer_bitfields
- {
- uint32_t TIMER : 16; //!< [15:0] Timer Value
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_can_timer_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAN_TIMER register
- */
-//@{
-#define HW_CAN_TIMER_ADDR(x) (REGS_CAN_BASE(x) + 0x8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAN_TIMER(x) (*(__IO hw_can_timer_t *) HW_CAN_TIMER_ADDR(x))
-#define HW_CAN_TIMER_RD(x) (HW_CAN_TIMER(x).U)
-#define HW_CAN_TIMER_WR(x, v) (HW_CAN_TIMER(x).U = (v))
-#define HW_CAN_TIMER_SET(x, v) (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) | (v)))
-#define HW_CAN_TIMER_CLR(x, v) (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) & ~(v)))
-#define HW_CAN_TIMER_TOG(x, v) (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAN_TIMER bitfields
- */
-
-/*!
- * @name Register CAN_TIMER, field TIMER[15:0] (RW)
- *
- * Contains the free-running counter value.
- */
-//@{
-#define BP_CAN_TIMER_TIMER (0U) //!< Bit position for CAN_TIMER_TIMER.
-#define BM_CAN_TIMER_TIMER (0x0000FFFFU) //!< Bit mask for CAN_TIMER_TIMER.
-#define BS_CAN_TIMER_TIMER (16U) //!< Bit field size in bits for CAN_TIMER_TIMER.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_TIMER_TIMER field.
-#define BR_CAN_TIMER_TIMER(x) (HW_CAN_TIMER(x).B.TIMER)
-#endif
-
-//! @brief Format value for bitfield CAN_TIMER_TIMER.
-#define BF_CAN_TIMER_TIMER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_TIMER_TIMER), uint32_t) & BM_CAN_TIMER_TIMER)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TIMER field to a new value.
-#define BW_CAN_TIMER_TIMER(x, v) (HW_CAN_TIMER_WR(x, (HW_CAN_TIMER_RD(x) & ~BM_CAN_TIMER_TIMER) | BF_CAN_TIMER_TIMER(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register (RW)
- *
- * Reset value: 0xFFFFFFFFU
- *
- * This register is located in RAM. RXMGMASK is provided for legacy application
- * support. When the MCR[IRMQ] bit is negated, RXMGMASK is always in effect. When
- * the MCR[IRMQ] bit is asserted, RXMGMASK has no effect. RXMGMASK is used to
- * mask the filter fields of all Rx MBs, excluding MBs 14-15, which have individual
- * mask registers. This register can only be written in Freeze mode as it is
- * blocked by hardware in other modes.
- */
-typedef union _hw_can_rxmgmask
-{
- uint32_t U;
- struct _hw_can_rxmgmask_bitfields
- {
- uint32_t MG : 32; //!< [31:0] Rx Mailboxes Global Mask Bits
- } B;
-} hw_can_rxmgmask_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAN_RXMGMASK register
- */
-//@{
-#define HW_CAN_RXMGMASK_ADDR(x) (REGS_CAN_BASE(x) + 0x10U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAN_RXMGMASK(x) (*(__IO hw_can_rxmgmask_t *) HW_CAN_RXMGMASK_ADDR(x))
-#define HW_CAN_RXMGMASK_RD(x) (HW_CAN_RXMGMASK(x).U)
-#define HW_CAN_RXMGMASK_WR(x, v) (HW_CAN_RXMGMASK(x).U = (v))
-#define HW_CAN_RXMGMASK_SET(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) | (v)))
-#define HW_CAN_RXMGMASK_CLR(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) & ~(v)))
-#define HW_CAN_RXMGMASK_TOG(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAN_RXMGMASK bitfields
- */
-
-/*!
- * @name Register CAN_RXMGMASK, field MG[31:0] (RW)
- *
- * These bits mask the Mailbox filter bits. Note that the alignment with the ID
- * word of the Mailbox is not perfect as the two most significant MG bits affect
- * the fields RTR and IDE, which are located in the Control and Status word of
- * the Mailbox. The following table shows in detail which MG bits mask each Mailbox
- * filter field. SMB[RTR] RTR bit of the Incoming Frame. It is saved into an
- * auxiliary MB called Rx Serial Message Buffer (Rx SMB). CTRL2[RRS] CTRL2[EACEN]
- * Mailbox filter fields MB[RTR] MB[IDE] MB[ID] Reserved 0 - 0 note If the
- * CTRL2[EACEN] bit is negated, the RTR bit of Mailbox is never compared with the RTR bit
- * of the incoming frame. note If the CTRL2[EACEN] bit is negated, the IDE bit
- * of Mailbox is always compared with the IDE bit of the incoming frame. MG[28:0]
- * MG[31:29] 0 - 1 MG[31] MG[30] MG[28:0] MG[29] 1 0 - - - - MG[31:0] 1 1 0 - -
- * MG[28:0] MG[31:29] 1 1 1 MG[31] MG[30] MG[28:0] MG[29]
- *
- * Values:
- * - 0 - The corresponding bit in the filter is "don't care."
- * - 1 - The corresponding bit in the filter is checked.
- */
-//@{
-#define BP_CAN_RXMGMASK_MG (0U) //!< Bit position for CAN_RXMGMASK_MG.
-#define BM_CAN_RXMGMASK_MG (0xFFFFFFFFU) //!< Bit mask for CAN_RXMGMASK_MG.
-#define BS_CAN_RXMGMASK_MG (32U) //!< Bit field size in bits for CAN_RXMGMASK_MG.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_RXMGMASK_MG field.
-#define BR_CAN_RXMGMASK_MG(x) (HW_CAN_RXMGMASK(x).U)
-#endif
-
-//! @brief Format value for bitfield CAN_RXMGMASK_MG.
-#define BF_CAN_RXMGMASK_MG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_RXMGMASK_MG), uint32_t) & BM_CAN_RXMGMASK_MG)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MG field to a new value.
-#define BW_CAN_RXMGMASK_MG(x, v) (HW_CAN_RXMGMASK_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CAN_RX14MASK - Rx 14 Mask register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAN_RX14MASK - Rx 14 Mask register (RW)
- *
- * Reset value: 0xFFFFFFFFU
- *
- * This register is located in RAM. RX14MASK is provided for legacy application
- * support. When the MCR[IRMQ] bit is asserted, RX14MASK has no effect. RX14MASK
- * is used to mask the filter fields of Message Buffer 14. This register can only
- * be programmed while the module is in Freeze mode as it is blocked by hardware
- * in other modes.
- */
-typedef union _hw_can_rx14mask
-{
- uint32_t U;
- struct _hw_can_rx14mask_bitfields
- {
- uint32_t RX14M : 32; //!< [31:0] Rx Buffer 14 Mask Bits
- } B;
-} hw_can_rx14mask_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAN_RX14MASK register
- */
-//@{
-#define HW_CAN_RX14MASK_ADDR(x) (REGS_CAN_BASE(x) + 0x14U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAN_RX14MASK(x) (*(__IO hw_can_rx14mask_t *) HW_CAN_RX14MASK_ADDR(x))
-#define HW_CAN_RX14MASK_RD(x) (HW_CAN_RX14MASK(x).U)
-#define HW_CAN_RX14MASK_WR(x, v) (HW_CAN_RX14MASK(x).U = (v))
-#define HW_CAN_RX14MASK_SET(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) | (v)))
-#define HW_CAN_RX14MASK_CLR(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) & ~(v)))
-#define HW_CAN_RX14MASK_TOG(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAN_RX14MASK bitfields
- */
-
-/*!
- * @name Register CAN_RX14MASK, field RX14M[31:0] (RW)
- *
- * Each mask bit masks the corresponding Mailbox 14 filter field in the same way
- * that RXMGMASK masks other Mailboxes' filters. See the description of the
- * CAN_RXMGMASK register.
- *
- * Values:
- * - 0 - The corresponding bit in the filter is "don't care."
- * - 1 - The corresponding bit in the filter is checked.
- */
-//@{
-#define BP_CAN_RX14MASK_RX14M (0U) //!< Bit position for CAN_RX14MASK_RX14M.
-#define BM_CAN_RX14MASK_RX14M (0xFFFFFFFFU) //!< Bit mask for CAN_RX14MASK_RX14M.
-#define BS_CAN_RX14MASK_RX14M (32U) //!< Bit field size in bits for CAN_RX14MASK_RX14M.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_RX14MASK_RX14M field.
-#define BR_CAN_RX14MASK_RX14M(x) (HW_CAN_RX14MASK(x).U)
-#endif
-
-//! @brief Format value for bitfield CAN_RX14MASK_RX14M.
-#define BF_CAN_RX14MASK_RX14M(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_RX14MASK_RX14M), uint32_t) & BM_CAN_RX14MASK_RX14M)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RX14M field to a new value.
-#define BW_CAN_RX14MASK_RX14M(x, v) (HW_CAN_RX14MASK_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CAN_RX15MASK - Rx 15 Mask register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAN_RX15MASK - Rx 15 Mask register (RW)
- *
- * Reset value: 0xFFFFFFFFU
- *
- * This register is located in RAM. RX15MASK is provided for legacy application
- * support. When the MCR[IRMQ] bit is asserted, RX15MASK has no effect. RX15MASK
- * is used to mask the filter fields of Message Buffer 15. This register can be
- * programmed only while the module is in Freeze mode because it is blocked by
- * hardware in other modes.
- */
-typedef union _hw_can_rx15mask
-{
- uint32_t U;
- struct _hw_can_rx15mask_bitfields
- {
- uint32_t RX15M : 32; //!< [31:0] Rx Buffer 15 Mask Bits
- } B;
-} hw_can_rx15mask_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAN_RX15MASK register
- */
-//@{
-#define HW_CAN_RX15MASK_ADDR(x) (REGS_CAN_BASE(x) + 0x18U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAN_RX15MASK(x) (*(__IO hw_can_rx15mask_t *) HW_CAN_RX15MASK_ADDR(x))
-#define HW_CAN_RX15MASK_RD(x) (HW_CAN_RX15MASK(x).U)
-#define HW_CAN_RX15MASK_WR(x, v) (HW_CAN_RX15MASK(x).U = (v))
-#define HW_CAN_RX15MASK_SET(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) | (v)))
-#define HW_CAN_RX15MASK_CLR(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) & ~(v)))
-#define HW_CAN_RX15MASK_TOG(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAN_RX15MASK bitfields
- */
-
-/*!
- * @name Register CAN_RX15MASK, field RX15M[31:0] (RW)
- *
- * Each mask bit masks the corresponding Mailbox 15 filter field in the same way
- * that RXMGMASK masks other Mailboxes' filters. See the description of the
- * CAN_RXMGMASK register.
- *
- * Values:
- * - 0 - The corresponding bit in the filter is "don't care."
- * - 1 - The corresponding bit in the filter is checked.
- */
-//@{
-#define BP_CAN_RX15MASK_RX15M (0U) //!< Bit position for CAN_RX15MASK_RX15M.
-#define BM_CAN_RX15MASK_RX15M (0xFFFFFFFFU) //!< Bit mask for CAN_RX15MASK_RX15M.
-#define BS_CAN_RX15MASK_RX15M (32U) //!< Bit field size in bits for CAN_RX15MASK_RX15M.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_RX15MASK_RX15M field.
-#define BR_CAN_RX15MASK_RX15M(x) (HW_CAN_RX15MASK(x).U)
-#endif
-
-//! @brief Format value for bitfield CAN_RX15MASK_RX15M.
-#define BF_CAN_RX15MASK_RX15M(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_RX15MASK_RX15M), uint32_t) & BM_CAN_RX15MASK_RX15M)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RX15M field to a new value.
-#define BW_CAN_RX15MASK_RX15M(x, v) (HW_CAN_RX15MASK_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CAN_ECR - Error Counter
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAN_ECR - Error Counter (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register has two 8-bit fields reflecting the value of two FlexCAN error
- * counters: Transmit Error Counter (TXERRCNT field) and Receive Error Counter
- * (RXERRCNT field). The rules for increasing and decreasing these counters are
- * described in the CAN protocol and are completely implemented in the FlexCAN
- * module. Both counters are read-only except in Freeze mode, where they can be
- * written by the CPU. FlexCAN responds to any bus state as described in the protocol,
- * for example, transmit Error Active or Error Passive flag, delay its
- * transmission start time (Error Passive) and avoid any influence on the bus when in Bus
- * Off state. The following are the basic rules for FlexCAN bus state transitions:
- * If the value of TXERRCNT or RXERRCNT increases to be greater than or equal to
- * 128, the FLTCONF field in the Error and Status Register is updated to reflect
- * 'Error Passive' state. If the FlexCAN state is 'Error Passive', and either
- * TXERRCNT or RXERRCNT decrements to a value less than or equal to 127 while the
- * other already satisfies this condition, the FLTCONF field in the Error and
- * Status Register is updated to reflect 'Error Active' state. If the value of
- * TXERRCNT increases to be greater than 255, the FLTCONF field in the Error and Status
- * Register is updated to reflect 'Bus Off' state, and an interrupt may be
- * issued. The value of TXERRCNT is then reset to zero. If FlexCAN is in 'Bus Off'
- * state, then TXERRCNT is cascaded together with another internal counter to count
- * the 128th occurrences of 11 consecutive recessive bits on the bus. Hence,
- * TXERRCNT is reset to zero and counts in a manner where the internal counter counts
- * 11 such bits and then wraps around while incrementing the TXERRCNT. When
- * TXERRCNT reaches the value of 128, the FLTCONF field in the Error and Status
- * Register is updated to be 'Error Active' and both error counters are reset to zero.
- * At any instance of dominant bit following a stream of less than 11
- * consecutive recessive bits, the internal counter resets itself to zero without affecting
- * the TXERRCNT value. If during system start-up, only one node is operating,
- * then its TXERRCNT increases in each message it is trying to transmit, as a
- * result of acknowledge errors (indicated by the ACKERR bit in the Error and Status
- * Register). After the transition to 'Error Passive' state, the TXERRCNT does not
- * increment anymore by acknowledge errors. Therefore the device never goes to
- * the 'Bus Off' state. If the RXERRCNT increases to a value greater than 127, it
- * is not incremented further, even if more errors are detected while being a
- * receiver. At the next successful message reception, the counter is set to a value
- * between 119 and 127 to resume to 'Error Active' state.
- */
-typedef union _hw_can_ecr
-{
- uint32_t U;
- struct _hw_can_ecr_bitfields
- {
- uint32_t TXERRCNT : 8; //!< [7:0] Transmit Error Counter
- uint32_t RXERRCNT : 8; //!< [15:8] Receive Error Counter
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_can_ecr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAN_ECR register
- */
-//@{
-#define HW_CAN_ECR_ADDR(x) (REGS_CAN_BASE(x) + 0x1CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAN_ECR(x) (*(__IO hw_can_ecr_t *) HW_CAN_ECR_ADDR(x))
-#define HW_CAN_ECR_RD(x) (HW_CAN_ECR(x).U)
-#define HW_CAN_ECR_WR(x, v) (HW_CAN_ECR(x).U = (v))
-#define HW_CAN_ECR_SET(x, v) (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) | (v)))
-#define HW_CAN_ECR_CLR(x, v) (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) & ~(v)))
-#define HW_CAN_ECR_TOG(x, v) (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAN_ECR bitfields
- */
-
-/*!
- * @name Register CAN_ECR, field TXERRCNT[7:0] (RW)
- */
-//@{
-#define BP_CAN_ECR_TXERRCNT (0U) //!< Bit position for CAN_ECR_TXERRCNT.
-#define BM_CAN_ECR_TXERRCNT (0x000000FFU) //!< Bit mask for CAN_ECR_TXERRCNT.
-#define BS_CAN_ECR_TXERRCNT (8U) //!< Bit field size in bits for CAN_ECR_TXERRCNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_ECR_TXERRCNT field.
-#define BR_CAN_ECR_TXERRCNT(x) (HW_CAN_ECR(x).B.TXERRCNT)
-#endif
-
-//! @brief Format value for bitfield CAN_ECR_TXERRCNT.
-#define BF_CAN_ECR_TXERRCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ECR_TXERRCNT), uint32_t) & BM_CAN_ECR_TXERRCNT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TXERRCNT field to a new value.
-#define BW_CAN_ECR_TXERRCNT(x, v) (HW_CAN_ECR_WR(x, (HW_CAN_ECR_RD(x) & ~BM_CAN_ECR_TXERRCNT) | BF_CAN_ECR_TXERRCNT(v)))
-#endif
-//@}
-
-/*!
- * @name Register CAN_ECR, field RXERRCNT[15:8] (RW)
- */
-//@{
-#define BP_CAN_ECR_RXERRCNT (8U) //!< Bit position for CAN_ECR_RXERRCNT.
-#define BM_CAN_ECR_RXERRCNT (0x0000FF00U) //!< Bit mask for CAN_ECR_RXERRCNT.
-#define BS_CAN_ECR_RXERRCNT (8U) //!< Bit field size in bits for CAN_ECR_RXERRCNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_ECR_RXERRCNT field.
-#define BR_CAN_ECR_RXERRCNT(x) (HW_CAN_ECR(x).B.RXERRCNT)
-#endif
-
-//! @brief Format value for bitfield CAN_ECR_RXERRCNT.
-#define BF_CAN_ECR_RXERRCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ECR_RXERRCNT), uint32_t) & BM_CAN_ECR_RXERRCNT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RXERRCNT field to a new value.
-#define BW_CAN_ECR_RXERRCNT(x, v) (HW_CAN_ECR_WR(x, (HW_CAN_ECR_RD(x) & ~BM_CAN_ECR_RXERRCNT) | BF_CAN_ECR_RXERRCNT(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CAN_ESR1 - Error and Status 1 register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAN_ESR1 - Error and Status 1 register (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register reflects various error conditions, some general status of the
- * device and it is the source of interrupts to the CPU. The CPU read action
- * clears bits 15-10. Therefore the reported error conditions (bits 15-10) are those
- * that occurred since the last time the CPU read this register. Bits 9-3 are
- * status bits. The following table shows the FlexCAN state variables and their
- * meanings. Other combinations not shown in the table are reserved. SYNCH IDLE TX RX
- * FlexCAN State 0 0 0 0 Not synchronized to CAN bus 1 1 x x Idle 1 0 1 0
- * Transmitting 1 0 0 1 Receiving
- */
-typedef union _hw_can_esr1
-{
- uint32_t U;
- struct _hw_can_esr1_bitfields
- {
- uint32_t WAKINT : 1; //!< [0] Wake-Up Interrupt
- uint32_t ERRINT : 1; //!< [1] Error Interrupt
- uint32_t BOFFINT : 1; //!< [2] Bus Off Interrupt
- uint32_t RX : 1; //!< [3] FlexCAN In Reception
- uint32_t FLTCONF : 2; //!< [5:4] Fault Confinement State
- uint32_t TX : 1; //!< [6] FlexCAN In Transmission
- uint32_t IDLE : 1; //!< [7]
- uint32_t RXWRN : 1; //!< [8] Rx Error Warning
- uint32_t TXWRN : 1; //!< [9] TX Error Warning
- uint32_t STFERR : 1; //!< [10] Stuffing Error
- uint32_t FRMERR : 1; //!< [11] Form Error
- uint32_t CRCERR : 1; //!< [12] Cyclic Redundancy Check Error
- uint32_t ACKERR : 1; //!< [13] Acknowledge Error
- uint32_t BIT0ERR : 1; //!< [14] Bit0 Error
- uint32_t BIT1ERR : 1; //!< [15] Bit1 Error
- uint32_t RWRNINT : 1; //!< [16] Rx Warning Interrupt Flag
- uint32_t TWRNINT : 1; //!< [17] Tx Warning Interrupt Flag
- uint32_t SYNCH : 1; //!< [18] CAN Synchronization Status
- uint32_t RESERVED0 : 13; //!< [31:19]
- } B;
-} hw_can_esr1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAN_ESR1 register
- */
-//@{
-#define HW_CAN_ESR1_ADDR(x) (REGS_CAN_BASE(x) + 0x20U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAN_ESR1(x) (*(__IO hw_can_esr1_t *) HW_CAN_ESR1_ADDR(x))
-#define HW_CAN_ESR1_RD(x) (HW_CAN_ESR1(x).U)
-#define HW_CAN_ESR1_WR(x, v) (HW_CAN_ESR1(x).U = (v))
-#define HW_CAN_ESR1_SET(x, v) (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) | (v)))
-#define HW_CAN_ESR1_CLR(x, v) (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) & ~(v)))
-#define HW_CAN_ESR1_TOG(x, v) (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAN_ESR1 bitfields
- */
-
-/*!
- * @name Register CAN_ESR1, field WAKINT[0] (W1C)
- *
- * This field applies when FlexCAN is in low-power mode under Self Wake Up
- * mechanism: Stop mode When a recessive-to-dominant transition is detected on the CAN
- * bus and if the MCR[WAKMSK] bit is set, an interrupt is generated to the CPU.
- * This bit is cleared by writing it to 1. When MCR[SLFWAK] is negated, this flag
- * is masked. The CPU must clear this flag before disabling the bit. Otherwise
- * it will be set when the SLFWAK is set again. Writing 0 has no effect.
- *
- * Values:
- * - 0 - No such occurrence.
- * - 1 - Indicates a recessive to dominant transition was received on the CAN
- * bus.
- */
-//@{
-#define BP_CAN_ESR1_WAKINT (0U) //!< Bit position for CAN_ESR1_WAKINT.
-#define BM_CAN_ESR1_WAKINT (0x00000001U) //!< Bit mask for CAN_ESR1_WAKINT.
-#define BS_CAN_ESR1_WAKINT (1U) //!< Bit field size in bits for CAN_ESR1_WAKINT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_ESR1_WAKINT field.
-#define BR_CAN_ESR1_WAKINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_WAKINT))
-#endif
-
-//! @brief Format value for bitfield CAN_ESR1_WAKINT.
-#define BF_CAN_ESR1_WAKINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ESR1_WAKINT), uint32_t) & BM_CAN_ESR1_WAKINT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WAKINT field to a new value.
-#define BW_CAN_ESR1_WAKINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_WAKINT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_ESR1, field ERRINT[1] (W1C)
- *
- * This bit indicates that at least one of the Error Bits (bits 15-10) is set.
- * If the corresponding mask bit CTRL1[ERRMSK] is set, an interrupt is generated
- * to the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
- *
- * Values:
- * - 0 - No such occurrence.
- * - 1 - Indicates setting of any Error Bit in the Error and Status Register.
- */
-//@{
-#define BP_CAN_ESR1_ERRINT (1U) //!< Bit position for CAN_ESR1_ERRINT.
-#define BM_CAN_ESR1_ERRINT (0x00000002U) //!< Bit mask for CAN_ESR1_ERRINT.
-#define BS_CAN_ESR1_ERRINT (1U) //!< Bit field size in bits for CAN_ESR1_ERRINT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_ESR1_ERRINT field.
-#define BR_CAN_ESR1_ERRINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ERRINT))
-#endif
-
-//! @brief Format value for bitfield CAN_ESR1_ERRINT.
-#define BF_CAN_ESR1_ERRINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ESR1_ERRINT), uint32_t) & BM_CAN_ESR1_ERRINT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERRINT field to a new value.
-#define BW_CAN_ESR1_ERRINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ERRINT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_ESR1, field BOFFINT[2] (W1C)
- *
- * This bit is set when FlexCAN enters 'Bus Off' state. If the corresponding
- * mask bit in the Control Register (BOFFMSK) is set, an interrupt is generated to
- * the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
- *
- * Values:
- * - 0 - No such occurrence.
- * - 1 - FlexCAN module entered Bus Off state.
- */
-//@{
-#define BP_CAN_ESR1_BOFFINT (2U) //!< Bit position for CAN_ESR1_BOFFINT.
-#define BM_CAN_ESR1_BOFFINT (0x00000004U) //!< Bit mask for CAN_ESR1_BOFFINT.
-#define BS_CAN_ESR1_BOFFINT (1U) //!< Bit field size in bits for CAN_ESR1_BOFFINT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_ESR1_BOFFINT field.
-#define BR_CAN_ESR1_BOFFINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BOFFINT))
-#endif
-
-//! @brief Format value for bitfield CAN_ESR1_BOFFINT.
-#define BF_CAN_ESR1_BOFFINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ESR1_BOFFINT), uint32_t) & BM_CAN_ESR1_BOFFINT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BOFFINT field to a new value.
-#define BW_CAN_ESR1_BOFFINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BOFFINT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_ESR1, field RX[3] (RO)
- *
- * This bit indicates if FlexCAN is receiving a message. See the table in the
- * overall CAN_ESR1 register description.
- *
- * Values:
- * - 0 - FlexCAN is not receiving a message.
- * - 1 - FlexCAN is receiving a message.
- */
-//@{
-#define BP_CAN_ESR1_RX (3U) //!< Bit position for CAN_ESR1_RX.
-#define BM_CAN_ESR1_RX (0x00000008U) //!< Bit mask for CAN_ESR1_RX.
-#define BS_CAN_ESR1_RX (1U) //!< Bit field size in bits for CAN_ESR1_RX.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_ESR1_RX field.
-#define BR_CAN_ESR1_RX(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RX))
-#endif
-//@}
-
-/*!
- * @name Register CAN_ESR1, field FLTCONF[5:4] (RO)
- *
- * This 2-bit field indicates the Confinement State of the FlexCAN module. If
- * the LOM bit in the Control Register is asserted, after some delay that depends
- * on the CAN bit timing the FLTCONF field will indicate "Error Passive". The very
- * same delay affects the way how FLTCONF reflects an update to ECR register by
- * the CPU. It may be necessary up to one CAN bit time to get them coherent
- * again. Because the Control Register is not affected by soft reset, the FLTCONF
- * field will not be affected by soft reset if the LOM bit is asserted.
- *
- * Values:
- * - 00 - Error Active
- * - 01 - Error Passive
- * - 1x - Bus Off
- */
-//@{
-#define BP_CAN_ESR1_FLTCONF (4U) //!< Bit position for CAN_ESR1_FLTCONF.
-#define BM_CAN_ESR1_FLTCONF (0x00000030U) //!< Bit mask for CAN_ESR1_FLTCONF.
-#define BS_CAN_ESR1_FLTCONF (2U) //!< Bit field size in bits for CAN_ESR1_FLTCONF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_ESR1_FLTCONF field.
-#define BR_CAN_ESR1_FLTCONF(x) (HW_CAN_ESR1(x).B.FLTCONF)
-#endif
-//@}
-
-/*!
- * @name Register CAN_ESR1, field TX[6] (RO)
- *
- * This bit indicates if FlexCAN is transmitting a message. See the table in the
- * overall CAN_ESR1 register description.
- *
- * Values:
- * - 0 - FlexCAN is not transmitting a message.
- * - 1 - FlexCAN is transmitting a message.
- */
-//@{
-#define BP_CAN_ESR1_TX (6U) //!< Bit position for CAN_ESR1_TX.
-#define BM_CAN_ESR1_TX (0x00000040U) //!< Bit mask for CAN_ESR1_TX.
-#define BS_CAN_ESR1_TX (1U) //!< Bit field size in bits for CAN_ESR1_TX.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_ESR1_TX field.
-#define BR_CAN_ESR1_TX(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TX))
-#endif
-//@}
-
-/*!
- * @name Register CAN_ESR1, field IDLE[7] (RO)
- *
- * This bit indicates when CAN bus is in IDLE state. See the table in the
- * overall CAN_ESR1 register description.
- *
- * Values:
- * - 0 - No such occurrence.
- * - 1 - CAN bus is now IDLE.
- */
-//@{
-#define BP_CAN_ESR1_IDLE (7U) //!< Bit position for CAN_ESR1_IDLE.
-#define BM_CAN_ESR1_IDLE (0x00000080U) //!< Bit mask for CAN_ESR1_IDLE.
-#define BS_CAN_ESR1_IDLE (1U) //!< Bit field size in bits for CAN_ESR1_IDLE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_ESR1_IDLE field.
-#define BR_CAN_ESR1_IDLE(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_IDLE))
-#endif
-//@}
-
-/*!
- * @name Register CAN_ESR1, field RXWRN[8] (RO)
- *
- * This bit indicates when repetitive errors are occurring during message
- * reception. This bit is not updated during Freeze mode.
- *
- * Values:
- * - 0 - No such occurrence.
- * - 1 - RXERRCNT is greater than or equal to 96.
- */
-//@{
-#define BP_CAN_ESR1_RXWRN (8U) //!< Bit position for CAN_ESR1_RXWRN.
-#define BM_CAN_ESR1_RXWRN (0x00000100U) //!< Bit mask for CAN_ESR1_RXWRN.
-#define BS_CAN_ESR1_RXWRN (1U) //!< Bit field size in bits for CAN_ESR1_RXWRN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_ESR1_RXWRN field.
-#define BR_CAN_ESR1_RXWRN(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RXWRN))
-#endif
-//@}
-
-/*!
- * @name Register CAN_ESR1, field TXWRN[9] (RO)
- *
- * This bit indicates when repetitive errors are occurring during message
- * transmission. This bit is not updated during Freeze mode.
- *
- * Values:
- * - 0 - No such occurrence.
- * - 1 - TXERRCNT is greater than or equal to 96.
- */
-//@{
-#define BP_CAN_ESR1_TXWRN (9U) //!< Bit position for CAN_ESR1_TXWRN.
-#define BM_CAN_ESR1_TXWRN (0x00000200U) //!< Bit mask for CAN_ESR1_TXWRN.
-#define BS_CAN_ESR1_TXWRN (1U) //!< Bit field size in bits for CAN_ESR1_TXWRN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_ESR1_TXWRN field.
-#define BR_CAN_ESR1_TXWRN(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TXWRN))
-#endif
-//@}
-
-/*!
- * @name Register CAN_ESR1, field STFERR[10] (RO)
- *
- * This bit indicates that a Stuffing Error has been etected.
- *
- * Values:
- * - 0 - No such occurrence.
- * - 1 - A Stuffing Error occurred since last read of this register.
- */
-//@{
-#define BP_CAN_ESR1_STFERR (10U) //!< Bit position for CAN_ESR1_STFERR.
-#define BM_CAN_ESR1_STFERR (0x00000400U) //!< Bit mask for CAN_ESR1_STFERR.
-#define BS_CAN_ESR1_STFERR (1U) //!< Bit field size in bits for CAN_ESR1_STFERR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_ESR1_STFERR field.
-#define BR_CAN_ESR1_STFERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_STFERR))
-#endif
-//@}
-
-/*!
- * @name Register CAN_ESR1, field FRMERR[11] (RO)
- *
- * This bit indicates that a Form Error has been detected by the receiver node,
- * that is, a fixed-form bit field contains at least one illegal bit.
- *
- * Values:
- * - 0 - No such occurrence.
- * - 1 - A Form Error occurred since last read of this register.
- */
-//@{
-#define BP_CAN_ESR1_FRMERR (11U) //!< Bit position for CAN_ESR1_FRMERR.
-#define BM_CAN_ESR1_FRMERR (0x00000800U) //!< Bit mask for CAN_ESR1_FRMERR.
-#define BS_CAN_ESR1_FRMERR (1U) //!< Bit field size in bits for CAN_ESR1_FRMERR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_ESR1_FRMERR field.
-#define BR_CAN_ESR1_FRMERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_FRMERR))
-#endif
-//@}
-
-/*!
- * @name Register CAN_ESR1, field CRCERR[12] (RO)
- *
- * This bit indicates that a CRC Error has been detected by the receiver node,
- * that is, the calculated CRC is different from the received.
- *
- * Values:
- * - 0 - No such occurrence.
- * - 1 - A CRC error occurred since last read of this register.
- */
-//@{
-#define BP_CAN_ESR1_CRCERR (12U) //!< Bit position for CAN_ESR1_CRCERR.
-#define BM_CAN_ESR1_CRCERR (0x00001000U) //!< Bit mask for CAN_ESR1_CRCERR.
-#define BS_CAN_ESR1_CRCERR (1U) //!< Bit field size in bits for CAN_ESR1_CRCERR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_ESR1_CRCERR field.
-#define BR_CAN_ESR1_CRCERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_CRCERR))
-#endif
-//@}
-
-/*!
- * @name Register CAN_ESR1, field ACKERR[13] (RO)
- *
- * This bit indicates that an Acknowledge Error has been detected by the
- * transmitter node, that is, a dominant bit has not been detected during the ACK SLOT.
- *
- * Values:
- * - 0 - No such occurrence.
- * - 1 - An ACK error occurred since last read of this register.
- */
-//@{
-#define BP_CAN_ESR1_ACKERR (13U) //!< Bit position for CAN_ESR1_ACKERR.
-#define BM_CAN_ESR1_ACKERR (0x00002000U) //!< Bit mask for CAN_ESR1_ACKERR.
-#define BS_CAN_ESR1_ACKERR (1U) //!< Bit field size in bits for CAN_ESR1_ACKERR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_ESR1_ACKERR field.
-#define BR_CAN_ESR1_ACKERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ACKERR))
-#endif
-//@}
-
-/*!
- * @name Register CAN_ESR1, field BIT0ERR[14] (RO)
- *
- * This bit indicates when an inconsistency occurs between the transmitted and
- * the received bit in a message.
- *
- * Values:
- * - 0 - No such occurrence.
- * - 1 - At least one bit sent as dominant is received as recessive.
- */
-//@{
-#define BP_CAN_ESR1_BIT0ERR (14U) //!< Bit position for CAN_ESR1_BIT0ERR.
-#define BM_CAN_ESR1_BIT0ERR (0x00004000U) //!< Bit mask for CAN_ESR1_BIT0ERR.
-#define BS_CAN_ESR1_BIT0ERR (1U) //!< Bit field size in bits for CAN_ESR1_BIT0ERR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_ESR1_BIT0ERR field.
-#define BR_CAN_ESR1_BIT0ERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BIT0ERR))
-#endif
-//@}
-
-/*!
- * @name Register CAN_ESR1, field BIT1ERR[15] (RO)
- *
- * This bit indicates when an inconsistency occurs between the transmitted and
- * the received bit in a message. This bit is not set by a transmitter in case of
- * arbitration field or ACK slot, or in case of a node sending a passive error
- * flag that detects dominant bits.
- *
- * Values:
- * - 0 - No such occurrence.
- * - 1 - At least one bit sent as recessive is received as dominant.
- */
-//@{
-#define BP_CAN_ESR1_BIT1ERR (15U) //!< Bit position for CAN_ESR1_BIT1ERR.
-#define BM_CAN_ESR1_BIT1ERR (0x00008000U) //!< Bit mask for CAN_ESR1_BIT1ERR.
-#define BS_CAN_ESR1_BIT1ERR (1U) //!< Bit field size in bits for CAN_ESR1_BIT1ERR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_ESR1_BIT1ERR field.
-#define BR_CAN_ESR1_BIT1ERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BIT1ERR))
-#endif
-//@}
-
-/*!
- * @name Register CAN_ESR1, field RWRNINT[16] (W1C)
- *
- * If the WRNEN bit in MCR is asserted, the RWRNINT bit is set when the RXWRN
- * flag transitions from 0 to 1, meaning that the Rx error counters reached 96. If
- * the corresponding mask bit in the Control Register (RWRNMSK) is set, an
- * interrupt is generated to the CPU. This bit is cleared by writing it to 1. When
- * WRNEN is negated, this flag is masked. CPU must clear this flag before disabling
- * the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
- * effect. This bit is not updated during Freeze mode.
- *
- * Values:
- * - 0 - No such occurrence.
- * - 1 - The Rx error counter transitioned from less than 96 to greater than or
- * equal to 96.
- */
-//@{
-#define BP_CAN_ESR1_RWRNINT (16U) //!< Bit position for CAN_ESR1_RWRNINT.
-#define BM_CAN_ESR1_RWRNINT (0x00010000U) //!< Bit mask for CAN_ESR1_RWRNINT.
-#define BS_CAN_ESR1_RWRNINT (1U) //!< Bit field size in bits for CAN_ESR1_RWRNINT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_ESR1_RWRNINT field.
-#define BR_CAN_ESR1_RWRNINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RWRNINT))
-#endif
-
-//! @brief Format value for bitfield CAN_ESR1_RWRNINT.
-#define BF_CAN_ESR1_RWRNINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ESR1_RWRNINT), uint32_t) & BM_CAN_ESR1_RWRNINT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RWRNINT field to a new value.
-#define BW_CAN_ESR1_RWRNINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RWRNINT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_ESR1, field TWRNINT[17] (W1C)
- *
- * If the WRNEN bit in MCR is asserted, the TWRNINT bit is set when the TXWRN
- * flag transitions from 0 to 1, meaning that the Tx error counter reached 96. If
- * the corresponding mask bit in the Control Register (TWRNMSK) is set, an
- * interrupt is generated to the CPU. This bit is cleared by writing it to 1. When WRNEN
- * is negated, this flag is masked. CPU must clear this flag before disabling
- * the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
- * effect. This flag is not generated during Bus Off state. This bit is not
- * updated during Freeze mode.
- *
- * Values:
- * - 0 - No such occurrence.
- * - 1 - The Tx error counter transitioned from less than 96 to greater than or
- * equal to 96.
- */
-//@{
-#define BP_CAN_ESR1_TWRNINT (17U) //!< Bit position for CAN_ESR1_TWRNINT.
-#define BM_CAN_ESR1_TWRNINT (0x00020000U) //!< Bit mask for CAN_ESR1_TWRNINT.
-#define BS_CAN_ESR1_TWRNINT (1U) //!< Bit field size in bits for CAN_ESR1_TWRNINT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_ESR1_TWRNINT field.
-#define BR_CAN_ESR1_TWRNINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TWRNINT))
-#endif
-
-//! @brief Format value for bitfield CAN_ESR1_TWRNINT.
-#define BF_CAN_ESR1_TWRNINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ESR1_TWRNINT), uint32_t) & BM_CAN_ESR1_TWRNINT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TWRNINT field to a new value.
-#define BW_CAN_ESR1_TWRNINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TWRNINT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_ESR1, field SYNCH[18] (RO)
- *
- * This read-only flag indicates whether the FlexCAN is synchronized to the CAN
- * bus and able to participate in the communication process. It is set and
- * cleared by the FlexCAN. See the table in the overall CAN_ESR1 register description.
- *
- * Values:
- * - 0 - FlexCAN is not synchronized to the CAN bus.
- * - 1 - FlexCAN is synchronized to the CAN bus.
- */
-//@{
-#define BP_CAN_ESR1_SYNCH (18U) //!< Bit position for CAN_ESR1_SYNCH.
-#define BM_CAN_ESR1_SYNCH (0x00040000U) //!< Bit mask for CAN_ESR1_SYNCH.
-#define BS_CAN_ESR1_SYNCH (1U) //!< Bit field size in bits for CAN_ESR1_SYNCH.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_ESR1_SYNCH field.
-#define BR_CAN_ESR1_SYNCH(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_SYNCH))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CAN_IMASK1 - Interrupt Masks 1 register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAN_IMASK1 - Interrupt Masks 1 register (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register allows any number of a range of the 32 Message Buffer
- * Interrupts to be enabled or disabled for MB31 to MB0. It contains one interrupt mask
- * bit per buffer, enabling the CPU to determine which buffer generates an
- * interrupt after a successful transmission or reception, that is, when the
- * corresponding IFLAG1 bit is set.
- */
-typedef union _hw_can_imask1
-{
- uint32_t U;
- struct _hw_can_imask1_bitfields
- {
- uint32_t BUFLM : 32; //!< [31:0] Buffer MB i Mask
- } B;
-} hw_can_imask1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAN_IMASK1 register
- */
-//@{
-#define HW_CAN_IMASK1_ADDR(x) (REGS_CAN_BASE(x) + 0x28U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAN_IMASK1(x) (*(__IO hw_can_imask1_t *) HW_CAN_IMASK1_ADDR(x))
-#define HW_CAN_IMASK1_RD(x) (HW_CAN_IMASK1(x).U)
-#define HW_CAN_IMASK1_WR(x, v) (HW_CAN_IMASK1(x).U = (v))
-#define HW_CAN_IMASK1_SET(x, v) (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) | (v)))
-#define HW_CAN_IMASK1_CLR(x, v) (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) & ~(v)))
-#define HW_CAN_IMASK1_TOG(x, v) (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAN_IMASK1 bitfields
- */
-
-/*!
- * @name Register CAN_IMASK1, field BUFLM[31:0] (RW)
- *
- * Each bit enables or disables the corresponding FlexCAN Message Buffer
- * Interrupt for MB31 to MB0. Setting or clearing a bit in the IMASK1 Register can
- * assert or negate an interrupt request, if the corresponding IFLAG1 bit is set.
- *
- * Values:
- * - 0 - The corresponding buffer Interrupt is disabled.
- * - 1 - The corresponding buffer Interrupt is enabled.
- */
-//@{
-#define BP_CAN_IMASK1_BUFLM (0U) //!< Bit position for CAN_IMASK1_BUFLM.
-#define BM_CAN_IMASK1_BUFLM (0xFFFFFFFFU) //!< Bit mask for CAN_IMASK1_BUFLM.
-#define BS_CAN_IMASK1_BUFLM (32U) //!< Bit field size in bits for CAN_IMASK1_BUFLM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_IMASK1_BUFLM field.
-#define BR_CAN_IMASK1_BUFLM(x) (HW_CAN_IMASK1(x).U)
-#endif
-
-//! @brief Format value for bitfield CAN_IMASK1_BUFLM.
-#define BF_CAN_IMASK1_BUFLM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IMASK1_BUFLM), uint32_t) & BM_CAN_IMASK1_BUFLM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BUFLM field to a new value.
-#define BW_CAN_IMASK1_BUFLM(x, v) (HW_CAN_IMASK1_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CAN_IFLAG1 - Interrupt Flags 1 register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAN_IFLAG1 - Interrupt Flags 1 register (W1C)
- *
- * Reset value: 0x00000000U
- *
- * This register defines the flags for the 32 Message Buffer interrupts for MB31
- * to MB0. It contains one interrupt flag bit per buffer. Each successful
- * transmission or reception sets the corresponding IFLAG1 bit. If the corresponding
- * IMASK1 bit is set, an interrupt will be generated. The interrupt flag must be
- * cleared by writing 1 to it. Writing 0 has no effect. The BUF7I to BUF5I flags
- * are also used to represent FIFO interrupts when the Rx FIFO is enabled. When the
- * bit MCR[RFEN] is set, the function of the 8 least significant interrupt flags
- * BUF[7:0]I changes: BUF7I, BUF6I and BUF5I indicate operating conditions of
- * the FIFO, and the BUF4TO0I field is reserved. Before enabling the RFEN, the CPU
- * must service the IFLAG bits asserted in the Rx FIFO region; see Section "Rx
- * FIFO". Otherwise, these IFLAG bits will mistakenly show the related MBs now
- * belonging to FIFO as having contents to be serviced. When the RFEN bit is negated,
- * the FIFO flags must be cleared. The same care must be taken when an RFFN
- * value is selected extending Rx FIFO filters beyond MB7. For example, when RFFN is
- * 0x8, the MB0-23 range is occupied by Rx FIFO filters and related IFLAG bits
- * must be cleared. Before updating MCR[MAXMB] field, CPU must service the IFLAG1
- * bits whose MB value is greater than the MCR[MAXMB] to be updated; otherwise,
- * they will remain set and be inconsistent with the number of MBs available.
- */
-typedef union _hw_can_iflag1
-{
- uint32_t U;
- struct _hw_can_iflag1_bitfields
- {
- uint32_t BUF0I : 1; //!< [0] Buffer MB0 Interrupt Or "reserved"
- uint32_t BUF4TO1I : 4; //!< [4:1] Buffer MB i Interrupt Or "reserved"
- uint32_t BUF5I : 1; //!< [5] Buffer MB5 Interrupt Or "Frames
- //! available in Rx FIFO"
- uint32_t BUF6I : 1; //!< [6] Buffer MB6 Interrupt Or "Rx FIFO Warning"
- uint32_t BUF7I : 1; //!< [7] Buffer MB7 Interrupt Or "Rx FIFO
- //! Overflow"
- uint32_t BUF31TO8I : 24; //!< [31:8] Buffer MBi Interrupt
- } B;
-} hw_can_iflag1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAN_IFLAG1 register
- */
-//@{
-#define HW_CAN_IFLAG1_ADDR(x) (REGS_CAN_BASE(x) + 0x30U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAN_IFLAG1(x) (*(__IO hw_can_iflag1_t *) HW_CAN_IFLAG1_ADDR(x))
-#define HW_CAN_IFLAG1_RD(x) (HW_CAN_IFLAG1(x).U)
-#define HW_CAN_IFLAG1_WR(x, v) (HW_CAN_IFLAG1(x).U = (v))
-#define HW_CAN_IFLAG1_SET(x, v) (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) | (v)))
-#define HW_CAN_IFLAG1_CLR(x, v) (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) & ~(v)))
-#define HW_CAN_IFLAG1_TOG(x, v) (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAN_IFLAG1 bitfields
- */
-
-/*!
- * @name Register CAN_IFLAG1, field BUF0I[0] (W1C)
- *
- * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
- * the interrupt for MB0. This flag is cleared by the FlexCAN whenever the bit
- * MCR[RFEN] is changed by CPU writes. The BUF0I flag is reserved when MCR[RFEN] is
- * set.
- *
- * Values:
- * - 0 - The corresponding buffer has no occurrence of successfully completed
- * transmission or reception when MCR[RFEN]=0.
- * - 1 - The corresponding buffer has successfully completed transmission or
- * reception when MCR[RFEN]=0.
- */
-//@{
-#define BP_CAN_IFLAG1_BUF0I (0U) //!< Bit position for CAN_IFLAG1_BUF0I.
-#define BM_CAN_IFLAG1_BUF0I (0x00000001U) //!< Bit mask for CAN_IFLAG1_BUF0I.
-#define BS_CAN_IFLAG1_BUF0I (1U) //!< Bit field size in bits for CAN_IFLAG1_BUF0I.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_IFLAG1_BUF0I field.
-#define BR_CAN_IFLAG1_BUF0I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF0I))
-#endif
-
-//! @brief Format value for bitfield CAN_IFLAG1_BUF0I.
-#define BF_CAN_IFLAG1_BUF0I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF0I), uint32_t) & BM_CAN_IFLAG1_BUF0I)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BUF0I field to a new value.
-#define BW_CAN_IFLAG1_BUF0I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF0I) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_IFLAG1, field BUF4TO1I[4:1] (W1C)
- *
- * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), these bits flag
- * the interrupts for MB4 to MB1. These flags are cleared by the FlexCAN whenever
- * the bit MCR[RFEN] is changed by CPU writes. The BUF4TO1I flags are reserved
- * when MCR[RFEN] is set.
- *
- * Values:
- * - 0 - The corresponding buffer has no occurrence of successfully completed
- * transmission or reception when MCR[RFEN]=0.
- * - 1 - The corresponding buffer has successfully completed transmission or
- * reception when MCR[RFEN]=0.
- */
-//@{
-#define BP_CAN_IFLAG1_BUF4TO1I (1U) //!< Bit position for CAN_IFLAG1_BUF4TO1I.
-#define BM_CAN_IFLAG1_BUF4TO1I (0x0000001EU) //!< Bit mask for CAN_IFLAG1_BUF4TO1I.
-#define BS_CAN_IFLAG1_BUF4TO1I (4U) //!< Bit field size in bits for CAN_IFLAG1_BUF4TO1I.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_IFLAG1_BUF4TO1I field.
-#define BR_CAN_IFLAG1_BUF4TO1I(x) (HW_CAN_IFLAG1(x).B.BUF4TO1I)
-#endif
-
-//! @brief Format value for bitfield CAN_IFLAG1_BUF4TO1I.
-#define BF_CAN_IFLAG1_BUF4TO1I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF4TO1I), uint32_t) & BM_CAN_IFLAG1_BUF4TO1I)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BUF4TO1I field to a new value.
-#define BW_CAN_IFLAG1_BUF4TO1I(x, v) (HW_CAN_IFLAG1_WR(x, (HW_CAN_IFLAG1_RD(x) & ~BM_CAN_IFLAG1_BUF4TO1I) | BF_CAN_IFLAG1_BUF4TO1I(v)))
-#endif
-//@}
-
-/*!
- * @name Register CAN_IFLAG1, field BUF5I[5] (W1C)
- *
- * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
- * the interrupt for MB5. This flag is cleared by the FlexCAN whenever the bit
- * MCR[RFEN] is changed by CPU writes. The BUF5I flag represents "Frames available in
- * Rx FIFO" when MCR[RFEN] is set. In this case, the flag indicates that at
- * least one frame is available to be read from the Rx FIFO.
- *
- * Values:
- * - 0 - No occurrence of MB5 completing transmission/reception when
- * MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
- * - 1 - MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s)
- * available in the Rx FIFO when MCR[RFEN]=1
- */
-//@{
-#define BP_CAN_IFLAG1_BUF5I (5U) //!< Bit position for CAN_IFLAG1_BUF5I.
-#define BM_CAN_IFLAG1_BUF5I (0x00000020U) //!< Bit mask for CAN_IFLAG1_BUF5I.
-#define BS_CAN_IFLAG1_BUF5I (1U) //!< Bit field size in bits for CAN_IFLAG1_BUF5I.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_IFLAG1_BUF5I field.
-#define BR_CAN_IFLAG1_BUF5I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF5I))
-#endif
-
-//! @brief Format value for bitfield CAN_IFLAG1_BUF5I.
-#define BF_CAN_IFLAG1_BUF5I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF5I), uint32_t) & BM_CAN_IFLAG1_BUF5I)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BUF5I field to a new value.
-#define BW_CAN_IFLAG1_BUF5I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF5I) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_IFLAG1, field BUF6I[6] (W1C)
- *
- * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
- * the interrupt for MB6. This flag is cleared by the FlexCAN whenever the bit
- * MCR[RFEN] is changed by CPU writes. The BUF6I flag represents "Rx FIFO Warning"
- * when MCR[RFEN] is set. In this case, the flag indicates when the number of
- * unread messages within the Rx FIFO is increased to 5 from 4 due to the reception of
- * a new one, meaning that the Rx FIFO is almost full. Note that if the flag is
- * cleared while the number of unread messages is greater than 4, it does not
- * assert again until the number of unread messages within the Rx FIFO is decreased
- * to be equal to or less than 4.
- *
- * Values:
- * - 0 - No occurrence of MB6 completing transmission/reception when
- * MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
- * - 1 - MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
- * almost full when MCR[RFEN]=1
- */
-//@{
-#define BP_CAN_IFLAG1_BUF6I (6U) //!< Bit position for CAN_IFLAG1_BUF6I.
-#define BM_CAN_IFLAG1_BUF6I (0x00000040U) //!< Bit mask for CAN_IFLAG1_BUF6I.
-#define BS_CAN_IFLAG1_BUF6I (1U) //!< Bit field size in bits for CAN_IFLAG1_BUF6I.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_IFLAG1_BUF6I field.
-#define BR_CAN_IFLAG1_BUF6I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF6I))
-#endif
-
-//! @brief Format value for bitfield CAN_IFLAG1_BUF6I.
-#define BF_CAN_IFLAG1_BUF6I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF6I), uint32_t) & BM_CAN_IFLAG1_BUF6I)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BUF6I field to a new value.
-#define BW_CAN_IFLAG1_BUF6I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF6I) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_IFLAG1, field BUF7I[7] (W1C)
- *
- * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
- * the interrupt for MB7. This flag is cleared by the FlexCAN whenever the bit
- * MCR[RFEN] is changed by CPU writes. The BUF7I flag represents "Rx FIFO Overflow"
- * when MCR[RFEN] is set. In this case, the flag indicates that a message was lost
- * because the Rx FIFO is full. Note that the flag will not be asserted when the
- * Rx FIFO is full and the message was captured by a Mailbox.
- *
- * Values:
- * - 0 - No occurrence of MB7 completing transmission/reception when
- * MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
- * - 1 - MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
- * overflow when MCR[RFEN]=1
- */
-//@{
-#define BP_CAN_IFLAG1_BUF7I (7U) //!< Bit position for CAN_IFLAG1_BUF7I.
-#define BM_CAN_IFLAG1_BUF7I (0x00000080U) //!< Bit mask for CAN_IFLAG1_BUF7I.
-#define BS_CAN_IFLAG1_BUF7I (1U) //!< Bit field size in bits for CAN_IFLAG1_BUF7I.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_IFLAG1_BUF7I field.
-#define BR_CAN_IFLAG1_BUF7I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF7I))
-#endif
-
-//! @brief Format value for bitfield CAN_IFLAG1_BUF7I.
-#define BF_CAN_IFLAG1_BUF7I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF7I), uint32_t) & BM_CAN_IFLAG1_BUF7I)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BUF7I field to a new value.
-#define BW_CAN_IFLAG1_BUF7I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF7I) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_IFLAG1, field BUF31TO8I[31:8] (W1C)
- *
- * Each bit flags the corresponding FlexCAN Message Buffer interrupt for MB31 to
- * MB8.
- *
- * Values:
- * - 0 - The corresponding buffer has no occurrence of successfully completed
- * transmission or reception.
- * - 1 - The corresponding buffer has successfully completed transmission or
- * reception.
- */
-//@{
-#define BP_CAN_IFLAG1_BUF31TO8I (8U) //!< Bit position for CAN_IFLAG1_BUF31TO8I.
-#define BM_CAN_IFLAG1_BUF31TO8I (0xFFFFFF00U) //!< Bit mask for CAN_IFLAG1_BUF31TO8I.
-#define BS_CAN_IFLAG1_BUF31TO8I (24U) //!< Bit field size in bits for CAN_IFLAG1_BUF31TO8I.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_IFLAG1_BUF31TO8I field.
-#define BR_CAN_IFLAG1_BUF31TO8I(x) (HW_CAN_IFLAG1(x).B.BUF31TO8I)
-#endif
-
-//! @brief Format value for bitfield CAN_IFLAG1_BUF31TO8I.
-#define BF_CAN_IFLAG1_BUF31TO8I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF31TO8I), uint32_t) & BM_CAN_IFLAG1_BUF31TO8I)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BUF31TO8I field to a new value.
-#define BW_CAN_IFLAG1_BUF31TO8I(x, v) (HW_CAN_IFLAG1_WR(x, (HW_CAN_IFLAG1_RD(x) & ~BM_CAN_IFLAG1_BUF31TO8I) | BF_CAN_IFLAG1_BUF31TO8I(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CAN_CTRL2 - Control 2 register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAN_CTRL2 - Control 2 register (RW)
- *
- * Reset value: 0x00B00000U
- *
- * This register contains control bits for CAN errors, FIFO features, and mode
- * selection.
- */
-typedef union _hw_can_ctrl2
-{
- uint32_t U;
- struct _hw_can_ctrl2_bitfields
- {
- uint32_t RESERVED0 : 16; //!< [15:0]
- uint32_t EACEN : 1; //!< [16] Entire Frame Arbitration Field
- //! Comparison Enable For Rx Mailboxes
- uint32_t RRS : 1; //!< [17] Remote Request Storing
- uint32_t MRP : 1; //!< [18] Mailboxes Reception Priority
- uint32_t TASD : 5; //!< [23:19] Tx Arbitration Start Delay
- uint32_t RFFN : 4; //!< [27:24] Number Of Rx FIFO Filters
- uint32_t WRMFRZ : 1; //!< [28] Write-Access To Memory In Freeze Mode
- uint32_t RESERVED1 : 3; //!< [31:29]
- } B;
-} hw_can_ctrl2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAN_CTRL2 register
- */
-//@{
-#define HW_CAN_CTRL2_ADDR(x) (REGS_CAN_BASE(x) + 0x34U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAN_CTRL2(x) (*(__IO hw_can_ctrl2_t *) HW_CAN_CTRL2_ADDR(x))
-#define HW_CAN_CTRL2_RD(x) (HW_CAN_CTRL2(x).U)
-#define HW_CAN_CTRL2_WR(x, v) (HW_CAN_CTRL2(x).U = (v))
-#define HW_CAN_CTRL2_SET(x, v) (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) | (v)))
-#define HW_CAN_CTRL2_CLR(x, v) (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) & ~(v)))
-#define HW_CAN_CTRL2_TOG(x, v) (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAN_CTRL2 bitfields
- */
-
-/*!
- * @name Register CAN_CTRL2, field EACEN[16] (RW)
- *
- * This bit controls the comparison of IDE and RTR bits whithin Rx Mailboxes
- * filters with their corresponding bits in the incoming frame by the matching
- * process. This bit does not affect matching for Rx FIFO. This bit can be written
- * only in Freeze mode because it is blocked by hardware in other modes.
- *
- * Values:
- * - 0 - Rx Mailbox filter's IDE bit is always compared and RTR is never
- * compared despite mask bits.
- * - 1 - Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with
- * their corresponding bits within the incoming frame. Mask bits do apply.
- */
-//@{
-#define BP_CAN_CTRL2_EACEN (16U) //!< Bit position for CAN_CTRL2_EACEN.
-#define BM_CAN_CTRL2_EACEN (0x00010000U) //!< Bit mask for CAN_CTRL2_EACEN.
-#define BS_CAN_CTRL2_EACEN (1U) //!< Bit field size in bits for CAN_CTRL2_EACEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CTRL2_EACEN field.
-#define BR_CAN_CTRL2_EACEN(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_EACEN))
-#endif
-
-//! @brief Format value for bitfield CAN_CTRL2_EACEN.
-#define BF_CAN_CTRL2_EACEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_EACEN), uint32_t) & BM_CAN_CTRL2_EACEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EACEN field to a new value.
-#define BW_CAN_CTRL2_EACEN(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_EACEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_CTRL2, field RRS[17] (RW)
- *
- * If this bit is asserted Remote Request Frame is submitted to a matching
- * process and stored in the corresponding Message Buffer in the same fashion of a
- * Data Frame. No automatic Remote Response Frame will be generated. If this bit is
- * negated the Remote Request Frame is submitted to a matching process and an
- * automatic Remote Response Frame is generated if a Message Buffer with CODE=0b1010
- * is found with the same ID. This bit can be written only in Freeze mode
- * because it is blocked by hardware in other modes.
- *
- * Values:
- * - 0 - Remote Response Frame is generated.
- * - 1 - Remote Request Frame is stored.
- */
-//@{
-#define BP_CAN_CTRL2_RRS (17U) //!< Bit position for CAN_CTRL2_RRS.
-#define BM_CAN_CTRL2_RRS (0x00020000U) //!< Bit mask for CAN_CTRL2_RRS.
-#define BS_CAN_CTRL2_RRS (1U) //!< Bit field size in bits for CAN_CTRL2_RRS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CTRL2_RRS field.
-#define BR_CAN_CTRL2_RRS(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_RRS))
-#endif
-
-//! @brief Format value for bitfield CAN_CTRL2_RRS.
-#define BF_CAN_CTRL2_RRS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_RRS), uint32_t) & BM_CAN_CTRL2_RRS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RRS field to a new value.
-#define BW_CAN_CTRL2_RRS(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_RRS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_CTRL2, field MRP[18] (RW)
- *
- * If this bit is set the matching process starts from the Mailboxes and if no
- * match occurs the matching continues on the Rx FIFO. This bit can be written
- * only in Freeze mode because it is blocked by hardware in other modes.
- *
- * Values:
- * - 0 - Matching starts from Rx FIFO and continues on Mailboxes.
- * - 1 - Matching starts from Mailboxes and continues on Rx FIFO.
- */
-//@{
-#define BP_CAN_CTRL2_MRP (18U) //!< Bit position for CAN_CTRL2_MRP.
-#define BM_CAN_CTRL2_MRP (0x00040000U) //!< Bit mask for CAN_CTRL2_MRP.
-#define BS_CAN_CTRL2_MRP (1U) //!< Bit field size in bits for CAN_CTRL2_MRP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CTRL2_MRP field.
-#define BR_CAN_CTRL2_MRP(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_MRP))
-#endif
-
-//! @brief Format value for bitfield CAN_CTRL2_MRP.
-#define BF_CAN_CTRL2_MRP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_MRP), uint32_t) & BM_CAN_CTRL2_MRP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MRP field to a new value.
-#define BW_CAN_CTRL2_MRP(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_MRP) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_CTRL2, field TASD[23:19] (RW)
- *
- * This 5-bit field indicates how many CAN bits the Tx arbitration process start
- * point can be delayed from the first bit of CRC field on CAN bus. This field
- * can be written only in Freeze mode because it is blocked by hardware in other
- * modes. This field is useful to optimize the transmit performance based on
- * factors such as: peripheral/serial clock ratio, CAN bit timing and number of MBs.
- * The duration of an arbitration process, in terms of CAN bits, is directly
- * proportional to the number of available MBs and CAN baud rate and inversely
- * proportional to the peripheral clock frequency. The optimal arbitration timing is
- * that in which the last MB is scanned right before the first bit of the
- * Intermission field of a CAN frame. Therefore, if there are few MBs and the system/serial
- * clock ratio is high and the CAN baud rate is low then the arbitration can be
- * delayed and vice-versa. If TASD is 0 then the arbitration start is not
- * delayed, thus the CPU has less time to configure a Tx MB for the next arbitration,
- * but more time is reserved for arbitration. On the other hand, if TASD is 24 then
- * the CPU can configure a Tx MB later and less time is reserved for
- * arbitration. If too little time is reserved for arbitration the FlexCAN may be not able
- * to find winner MBs in time to compete with other nodes for the CAN bus. If the
- * arbitration ends too much time before the first bit of Intermission field then
- * there is a chance that the CPU reconfigures some Tx MBs and the winner MB is
- * not the best to be transmitted. The optimal configuration for TASD can be
- * calculated as: TASD = 25 - {f CANCLK * [MAXMB + 3 - (RFEN * 8) - (RFEN * RFFN *
- * 2)] * 2} / {f SYS * [1+(PSEG1+1)+(PSEG2+1)+(PROPSEG+1)] * (PRESDIV+1)} where: f
- * CANCLK is the Protocol Engine (PE) Clock (see section "Protocol Timing"), in
- * Hz f SYS is the peripheral clock, in Hz MAXMB is the value in CTRL1[MAXMB]
- * field RFEN is the value in CTRL1[RFEN] bit RFFN is the value in CTRL2[RFFN] field
- * PSEG1 is the value in CTRL1[PSEG1] field PSEG2 is the value in CTRL1[PSEG2]
- * field PROPSEG is the value in CTRL1[PROPSEG] field PRESDIV is the value in
- * CTRL1[PRESDIV] field See Section "Arbitration process" and Section "Protocol
- * Timing" for more details.
- */
-//@{
-#define BP_CAN_CTRL2_TASD (19U) //!< Bit position for CAN_CTRL2_TASD.
-#define BM_CAN_CTRL2_TASD (0x00F80000U) //!< Bit mask for CAN_CTRL2_TASD.
-#define BS_CAN_CTRL2_TASD (5U) //!< Bit field size in bits for CAN_CTRL2_TASD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CTRL2_TASD field.
-#define BR_CAN_CTRL2_TASD(x) (HW_CAN_CTRL2(x).B.TASD)
-#endif
-
-//! @brief Format value for bitfield CAN_CTRL2_TASD.
-#define BF_CAN_CTRL2_TASD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_TASD), uint32_t) & BM_CAN_CTRL2_TASD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TASD field to a new value.
-#define BW_CAN_CTRL2_TASD(x, v) (HW_CAN_CTRL2_WR(x, (HW_CAN_CTRL2_RD(x) & ~BM_CAN_CTRL2_TASD) | BF_CAN_CTRL2_TASD(v)))
-#endif
-//@}
-
-/*!
- * @name Register CAN_CTRL2, field RFFN[27:24] (RW)
- *
- * This 4-bit field defines the number of Rx FIFO filters, as shown in the
- * following table. The maximum selectable number of filters is determined by the MCU.
- * This field can only be written in Freeze mode as it is blocked by hardware in
- * other modes. This field must not be programmed with values that make the
- * number of Message Buffers occupied by Rx FIFO and ID Filter exceed the number of
- * Mailboxes present, defined by MCR[MAXMB]. Each group of eight filters occupies
- * a memory space equivalent to two Message Buffers which means that the more
- * filters are implemented the less Mailboxes will be available. Considering that
- * the Rx FIFO occupies the memory space originally reserved for MB0-5, RFFN should
- * be programmed with a value correponding to a number of filters not greater
- * than the number of available memory words which can be calculated as follows:
- * (SETUP_MB - 6) * 4 where SETUP_MB is the least between NUMBER_OF_MB and MAXMB.
- * The number of remaining Mailboxes available will be: (SETUP_MB - 8) - (RFFN *
- * 2) If the Number of Rx FIFO Filters programmed through RFFN exceeds the
- * SETUP_MB value (memory space available) the exceeding ones will not be functional.
- * RFFN[3:0] Number of Rx FIFO filters Message Buffers occupied by Rx FIFO and ID
- * Filter Table Remaining Available MailboxesThe number of the last remaining
- * available mailboxes is defined by the least value between the parameter
- * NUMBER_OF_MB minus 1 and the MCR[MAXMB] field. Rx FIFO ID Filter Table Elements Affected
- * by Rx Individual MasksIf Rx Individual Mask Registers are not enabled then
- * all Rx FIFO filters are affected by the Rx FIFO Global Mask. Rx FIFO ID Filter
- * Table Elements Affected by Rx FIFO Global Mask #rxfgmask-note 0x0 8 MB 0-7 MB
- * 8-63 Elements 0-7 none 0x1 16 MB 0-9 MB 10-63 Elements 0-9 Elements 10-15 0x2
- * 24 MB 0-11 MB 12-63 Elements 0-11 Elements 12-23 0x3 32 MB 0-13 MB 14-63
- * Elements 0-13 Elements 14-31 0x4 40 MB 0-15 MB 16-63 Elements 0-15 Elements 16-39
- * 0x5 48 MB 0-17 MB 18-63 Elements 0-17 Elements 18-47 0x6 56 MB 0-19 MB 20-63
- * Elements 0-19 Elements 20-55 0x7 64 MB 0-21 MB 22-63 Elements 0-21 Elements 22-63
- * 0x8 72 MB 0-23 MB 24-63 Elements 0-23 Elements 24-71 0x9 80 MB 0-25 MB 26-63
- * Elements 0-25 Elements 26-79 0xA 88 MB 0-27 MB 28-63 Elements 0-27 Elements
- * 28-87 0xB 96 MB 0-29 MB 30-63 Elements 0-29 Elements 30-95 0xC 104 MB 0-31 MB
- * 32-63 Elements 0-31 Elements 32-103 0xD 112 MB 0-33 MB 34-63 Elements 0-31
- * Elements 32-111 0xE 120 MB 0-35 MB 36-63 Elements 0-31 Elements 32-119 0xF 128 MB
- * 0-37 MB 38-63 Elements 0-31 Elements 32-127
- */
-//@{
-#define BP_CAN_CTRL2_RFFN (24U) //!< Bit position for CAN_CTRL2_RFFN.
-#define BM_CAN_CTRL2_RFFN (0x0F000000U) //!< Bit mask for CAN_CTRL2_RFFN.
-#define BS_CAN_CTRL2_RFFN (4U) //!< Bit field size in bits for CAN_CTRL2_RFFN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CTRL2_RFFN field.
-#define BR_CAN_CTRL2_RFFN(x) (HW_CAN_CTRL2(x).B.RFFN)
-#endif
-
-//! @brief Format value for bitfield CAN_CTRL2_RFFN.
-#define BF_CAN_CTRL2_RFFN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_RFFN), uint32_t) & BM_CAN_CTRL2_RFFN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RFFN field to a new value.
-#define BW_CAN_CTRL2_RFFN(x, v) (HW_CAN_CTRL2_WR(x, (HW_CAN_CTRL2_RD(x) & ~BM_CAN_CTRL2_RFFN) | BF_CAN_CTRL2_RFFN(v)))
-#endif
-//@}
-
-/*!
- * @name Register CAN_CTRL2, field WRMFRZ[28] (RW)
- *
- * Enable unrestricted write access to FlexCAN memory in Freeze mode. This bit
- * can only be written in Freeze mode and has no effect out of Freeze mode.
- *
- * Values:
- * - 0 - Maintain the write access restrictions.
- * - 1 - Enable unrestricted write access to FlexCAN memory.
- */
-//@{
-#define BP_CAN_CTRL2_WRMFRZ (28U) //!< Bit position for CAN_CTRL2_WRMFRZ.
-#define BM_CAN_CTRL2_WRMFRZ (0x10000000U) //!< Bit mask for CAN_CTRL2_WRMFRZ.
-#define BS_CAN_CTRL2_WRMFRZ (1U) //!< Bit field size in bits for CAN_CTRL2_WRMFRZ.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CTRL2_WRMFRZ field.
-#define BR_CAN_CTRL2_WRMFRZ(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_WRMFRZ))
-#endif
-
-//! @brief Format value for bitfield CAN_CTRL2_WRMFRZ.
-#define BF_CAN_CTRL2_WRMFRZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_WRMFRZ), uint32_t) & BM_CAN_CTRL2_WRMFRZ)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WRMFRZ field to a new value.
-#define BW_CAN_CTRL2_WRMFRZ(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_WRMFRZ) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CAN_ESR2 - Error and Status 2 register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAN_ESR2 - Error and Status 2 register (RO)
- *
- * Reset value: 0x00000000U
- *
- * This register reflects various interrupt flags and some general status.
- */
-typedef union _hw_can_esr2
-{
- uint32_t U;
- struct _hw_can_esr2_bitfields
- {
- uint32_t RESERVED0 : 13; //!< [12:0]
- uint32_t IMB : 1; //!< [13] Inactive Mailbox
- uint32_t VPS : 1; //!< [14] Valid Priority Status
- uint32_t RESERVED1 : 1; //!< [15]
- uint32_t LPTM : 7; //!< [22:16] Lowest Priority Tx Mailbox
- uint32_t RESERVED2 : 9; //!< [31:23]
- } B;
-} hw_can_esr2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAN_ESR2 register
- */
-//@{
-#define HW_CAN_ESR2_ADDR(x) (REGS_CAN_BASE(x) + 0x38U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAN_ESR2(x) (*(__I hw_can_esr2_t *) HW_CAN_ESR2_ADDR(x))
-#define HW_CAN_ESR2_RD(x) (HW_CAN_ESR2(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAN_ESR2 bitfields
- */
-
-/*!
- * @name Register CAN_ESR2, field IMB[13] (RO)
- *
- * If ESR2[VPS] is asserted, this bit indicates whether there is any inactive
- * Mailbox (CODE field is either 0b1000 or 0b0000). This bit is asserted in the
- * following cases: During arbitration, if an LPTM is found and it is inactive. If
- * IMB is not asserted and a frame is transmitted successfully. This bit is
- * cleared in all start of arbitration (see Section "Arbitration process"). LPTM
- * mechanism have the following behavior: if an MB is successfully transmitted and
- * ESR2[IMB]=0 (no inactive Mailbox), then ESR2[VPS] and ESR2[IMB] are asserted and
- * the index related to the MB just transmitted is loaded into ESR2[LPTM].
- *
- * Values:
- * - 0 - If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
- * - 1 - If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM
- * content is the number of the first one.
- */
-//@{
-#define BP_CAN_ESR2_IMB (13U) //!< Bit position for CAN_ESR2_IMB.
-#define BM_CAN_ESR2_IMB (0x00002000U) //!< Bit mask for CAN_ESR2_IMB.
-#define BS_CAN_ESR2_IMB (1U) //!< Bit field size in bits for CAN_ESR2_IMB.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_ESR2_IMB field.
-#define BR_CAN_ESR2_IMB(x) (BITBAND_ACCESS32(HW_CAN_ESR2_ADDR(x), BP_CAN_ESR2_IMB))
-#endif
-//@}
-
-/*!
- * @name Register CAN_ESR2, field VPS[14] (RO)
- *
- * This bit indicates whether IMB and LPTM contents are currently valid or not.
- * VPS is asserted upon every complete Tx arbitration process unless the CPU
- * writes to Control and Status word of a Mailbox that has already been scanned, that
- * is, it is behind Tx Arbitration Pointer, during the Tx arbitration process.
- * If there is no inactive Mailbox and only one Tx Mailbox that is being
- * transmitted then VPS is not asserted. VPS is negated upon the start of every Tx
- * arbitration process or upon a write to Control and Status word of any Mailbox.
- * ESR2[VPS] is not affected by any CPU write into Control Status (C/S) of a MB that is
- * blocked by abort mechanism. When MCR[AEN] is asserted, the abort code write
- * in C/S of a MB that is being transmitted (pending abort), or any write attempt
- * into a Tx MB with IFLAG set is blocked.
- *
- * Values:
- * - 0 - Contents of IMB and LPTM are invalid.
- * - 1 - Contents of IMB and LPTM are valid.
- */
-//@{
-#define BP_CAN_ESR2_VPS (14U) //!< Bit position for CAN_ESR2_VPS.
-#define BM_CAN_ESR2_VPS (0x00004000U) //!< Bit mask for CAN_ESR2_VPS.
-#define BS_CAN_ESR2_VPS (1U) //!< Bit field size in bits for CAN_ESR2_VPS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_ESR2_VPS field.
-#define BR_CAN_ESR2_VPS(x) (BITBAND_ACCESS32(HW_CAN_ESR2_ADDR(x), BP_CAN_ESR2_VPS))
-#endif
-//@}
-
-/*!
- * @name Register CAN_ESR2, field LPTM[22:16] (RO)
- *
- * If ESR2[VPS] is asserted, this field indicates the lowest number inactive
- * Mailbox (see the IMB bit description). If there is no inactive Mailbox then the
- * Mailbox indicated depends on CTRL1[LBUF] bit value. If CTRL1[LBUF] bit is
- * negated then the Mailbox indicated is the one that has the greatest arbitration
- * value (see the "Highest priority Mailbox first" section). If CTRL1[LBUF] bit is
- * asserted then the Mailbox indicated is the highest number active Tx Mailbox. If
- * a Tx Mailbox is being transmitted it is not considered in LPTM calculation.
- * If ESR2[IMB] is not asserted and a frame is transmitted successfully, LPTM is
- * updated with its Mailbox number.
- */
-//@{
-#define BP_CAN_ESR2_LPTM (16U) //!< Bit position for CAN_ESR2_LPTM.
-#define BM_CAN_ESR2_LPTM (0x007F0000U) //!< Bit mask for CAN_ESR2_LPTM.
-#define BS_CAN_ESR2_LPTM (7U) //!< Bit field size in bits for CAN_ESR2_LPTM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_ESR2_LPTM field.
-#define BR_CAN_ESR2_LPTM(x) (HW_CAN_ESR2(x).B.LPTM)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CAN_CRCR - CRC Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAN_CRCR - CRC Register (RO)
- *
- * Reset value: 0x00000000U
- *
- * This register provides information about the CRC of transmitted messages.
- */
-typedef union _hw_can_crcr
-{
- uint32_t U;
- struct _hw_can_crcr_bitfields
- {
- uint32_t TXCRC : 15; //!< [14:0] CRC Transmitted
- uint32_t RESERVED0 : 1; //!< [15]
- uint32_t MBCRC : 7; //!< [22:16] CRC Mailbox
- uint32_t RESERVED1 : 9; //!< [31:23]
- } B;
-} hw_can_crcr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAN_CRCR register
- */
-//@{
-#define HW_CAN_CRCR_ADDR(x) (REGS_CAN_BASE(x) + 0x44U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAN_CRCR(x) (*(__I hw_can_crcr_t *) HW_CAN_CRCR_ADDR(x))
-#define HW_CAN_CRCR_RD(x) (HW_CAN_CRCR(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAN_CRCR bitfields
- */
-
-/*!
- * @name Register CAN_CRCR, field TXCRC[14:0] (RO)
- *
- * This field indicates the CRC value of the last message transmitted. This
- * field is updated at the same time the Tx Interrupt Flag is asserted.
- */
-//@{
-#define BP_CAN_CRCR_TXCRC (0U) //!< Bit position for CAN_CRCR_TXCRC.
-#define BM_CAN_CRCR_TXCRC (0x00007FFFU) //!< Bit mask for CAN_CRCR_TXCRC.
-#define BS_CAN_CRCR_TXCRC (15U) //!< Bit field size in bits for CAN_CRCR_TXCRC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CRCR_TXCRC field.
-#define BR_CAN_CRCR_TXCRC(x) (HW_CAN_CRCR(x).B.TXCRC)
-#endif
-//@}
-
-/*!
- * @name Register CAN_CRCR, field MBCRC[22:16] (RO)
- *
- * This field indicates the number of the Mailbox corresponding to the value in
- * TXCRC field.
- */
-//@{
-#define BP_CAN_CRCR_MBCRC (16U) //!< Bit position for CAN_CRCR_MBCRC.
-#define BM_CAN_CRCR_MBCRC (0x007F0000U) //!< Bit mask for CAN_CRCR_MBCRC.
-#define BS_CAN_CRCR_MBCRC (7U) //!< Bit field size in bits for CAN_CRCR_MBCRC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CRCR_MBCRC field.
-#define BR_CAN_CRCR_MBCRC(x) (HW_CAN_CRCR(x).B.MBCRC)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CAN_RXFGMASK - Rx FIFO Global Mask register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAN_RXFGMASK - Rx FIFO Global Mask register (RW)
- *
- * Reset value: 0xFFFFFFFFU
- *
- * This register is located in RAM. If Rx FIFO is enabled RXFGMASK is used to
- * mask the Rx FIFO ID Filter Table elements that do not have a corresponding RXIMR
- * according to CTRL2[RFFN] field setting. This register can only be written in
- * Freeze mode as it is blocked by hardware in other modes.
- */
-typedef union _hw_can_rxfgmask
-{
- uint32_t U;
- struct _hw_can_rxfgmask_bitfields
- {
- uint32_t FGM : 32; //!< [31:0] Rx FIFO Global Mask Bits
- } B;
-} hw_can_rxfgmask_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAN_RXFGMASK register
- */
-//@{
-#define HW_CAN_RXFGMASK_ADDR(x) (REGS_CAN_BASE(x) + 0x48U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAN_RXFGMASK(x) (*(__IO hw_can_rxfgmask_t *) HW_CAN_RXFGMASK_ADDR(x))
-#define HW_CAN_RXFGMASK_RD(x) (HW_CAN_RXFGMASK(x).U)
-#define HW_CAN_RXFGMASK_WR(x, v) (HW_CAN_RXFGMASK(x).U = (v))
-#define HW_CAN_RXFGMASK_SET(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) | (v)))
-#define HW_CAN_RXFGMASK_CLR(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) & ~(v)))
-#define HW_CAN_RXFGMASK_TOG(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAN_RXFGMASK bitfields
- */
-
-/*!
- * @name Register CAN_RXFGMASK, field FGM[31:0] (RW)
- *
- * These bits mask the ID Filter Table elements bits in a perfect alignment. The
- * following table shows how the FGM bits correspond to each IDAF field. Rx FIFO
- * ID Filter Table Elements Format (MCR[IDAM]) Identifier Acceptance Filter
- * Fields RTR IDE RXIDA RXIDB If MCR[IDAM] field is equivalent to the format B only
- * the fourteen most significant bits of the Identifier of the incoming frame are
- * compared with the Rx FIFO filter. RXIDC If MCR[IDAM] field is equivalent to
- * the format C only the eight most significant bits of the Identifier of the
- * incoming frame are compared with the Rx FIFO filter. Reserved A FGM[31] FGM[30]
- * FGM[29:1] - - FGM[0] B FGM[31], FGM[15] FGM[30], FGM[14] - FGM[29:16], FGM[13:0]
- * - C - - - FGM[31:24], FGM[23:16], FGM[15:8], FGM[7:0]
- *
- * Values:
- * - 0 - The corresponding bit in the filter is "don't care."
- * - 1 - The corresponding bit in the filter is checked.
- */
-//@{
-#define BP_CAN_RXFGMASK_FGM (0U) //!< Bit position for CAN_RXFGMASK_FGM.
-#define BM_CAN_RXFGMASK_FGM (0xFFFFFFFFU) //!< Bit mask for CAN_RXFGMASK_FGM.
-#define BS_CAN_RXFGMASK_FGM (32U) //!< Bit field size in bits for CAN_RXFGMASK_FGM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_RXFGMASK_FGM field.
-#define BR_CAN_RXFGMASK_FGM(x) (HW_CAN_RXFGMASK(x).U)
-#endif
-
-//! @brief Format value for bitfield CAN_RXFGMASK_FGM.
-#define BF_CAN_RXFGMASK_FGM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_RXFGMASK_FGM), uint32_t) & BM_CAN_RXFGMASK_FGM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FGM field to a new value.
-#define BW_CAN_RXFGMASK_FGM(x, v) (HW_CAN_RXFGMASK_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CAN_RXFIR - Rx FIFO Information Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAN_RXFIR - Rx FIFO Information Register (RO)
- *
- * Reset value: 0x00000000U
- *
- * RXFIR provides information on Rx FIFO. This register is the port through
- * which the CPU accesses the output of the RXFIR FIFO located in RAM. The RXFIR FIFO
- * is written by the FlexCAN whenever a new message is moved into the Rx FIFO as
- * well as its output is updated whenever the output of the Rx FIFO is updated
- * with the next message. See Section "Rx FIFO" for instructions on reading this
- * register.
- */
-typedef union _hw_can_rxfir
-{
- uint32_t U;
- struct _hw_can_rxfir_bitfields
- {
- uint32_t IDHIT : 9; //!< [8:0] Identifier Acceptance Filter Hit
- //! Indicator
- uint32_t RESERVED0 : 23; //!< [31:9]
- } B;
-} hw_can_rxfir_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAN_RXFIR register
- */
-//@{
-#define HW_CAN_RXFIR_ADDR(x) (REGS_CAN_BASE(x) + 0x4CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAN_RXFIR(x) (*(__I hw_can_rxfir_t *) HW_CAN_RXFIR_ADDR(x))
-#define HW_CAN_RXFIR_RD(x) (HW_CAN_RXFIR(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAN_RXFIR bitfields
- */
-
-/*!
- * @name Register CAN_RXFIR, field IDHIT[8:0] (RO)
- *
- * This field indicates which Identifier Acceptance Filter was hit by the
- * received message that is in the output of the Rx FIFO. If multiple filters match the
- * incoming message ID then the first matching IDAF found (lowest number) by the
- * matching process is indicated. This field is valid only while the
- * IFLAG[BUF5I] is asserted.
- */
-//@{
-#define BP_CAN_RXFIR_IDHIT (0U) //!< Bit position for CAN_RXFIR_IDHIT.
-#define BM_CAN_RXFIR_IDHIT (0x000001FFU) //!< Bit mask for CAN_RXFIR_IDHIT.
-#define BS_CAN_RXFIR_IDHIT (9U) //!< Bit field size in bits for CAN_RXFIR_IDHIT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_RXFIR_IDHIT field.
-#define BR_CAN_RXFIR_IDHIT(x) (HW_CAN_RXFIR(x).B.IDHIT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CAN_CS - Message Buffer 0 CS Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAN_CS - Message Buffer 0 CS Register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_can_cs
-{
- uint32_t U;
- struct _hw_can_cs_bitfields
- {
- uint32_t TIME_STAMP : 16; //!< [15:0] Free-Running Counter Time
- //! stamp. This 16-bit field is a copy of the Free-Running Timer, captured for
- //! Tx and Rx frames at the time when the beginning of the Identifier
- //! field appears on the CAN bus.
- uint32_t DLC : 4; //!< [19:16] Length of the data to be
- //! stored/transmitted.
- uint32_t RTR : 1; //!< [20] Remote Transmission Request. One/zero for
- //! remote/data frame.
- uint32_t IDE : 1; //!< [21] ID Extended. One/zero for
- //! extended/standard format frame.
- uint32_t SRR : 1; //!< [22] Substitute Remote Request. Contains a
- //! fixed recessive bit.
- uint32_t RESERVED0 : 1; //!< [23] Reserved
- uint32_t CODE : 4; //!< [27:24] Reserved
- uint32_t RESERVED1 : 4; //!< [31:28] Reserved
- } B;
-} hw_can_cs_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAN_CS register
- */
-//@{
-#define HW_CAN_CS_COUNT (16U)
-
-#define HW_CAN_CS_ADDR(x, n) (REGS_CAN_BASE(x) + 0x80U + (0x10U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAN_CS(x, n) (*(__IO hw_can_cs_t *) HW_CAN_CS_ADDR(x, n))
-#define HW_CAN_CS_RD(x, n) (HW_CAN_CS(x, n).U)
-#define HW_CAN_CS_WR(x, n, v) (HW_CAN_CS(x, n).U = (v))
-#define HW_CAN_CS_SET(x, n, v) (HW_CAN_CS_WR(x, n, HW_CAN_CS_RD(x, n) | (v)))
-#define HW_CAN_CS_CLR(x, n, v) (HW_CAN_CS_WR(x, n, HW_CAN_CS_RD(x, n) & ~(v)))
-#define HW_CAN_CS_TOG(x, n, v) (HW_CAN_CS_WR(x, n, HW_CAN_CS_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAN_CS bitfields
- */
-
-/*!
- * @name Register CAN_CS, field TIME_STAMP[15:0] (RW)
- */
-//@{
-#define BP_CAN_CS_TIME_STAMP (0U) //!< Bit position for CAN_CS_TIME_STAMP.
-#define BM_CAN_CS_TIME_STAMP (0x0000FFFFU) //!< Bit mask for CAN_CS_TIME_STAMP.
-#define BS_CAN_CS_TIME_STAMP (16U) //!< Bit field size in bits for CAN_CS_TIME_STAMP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CS_TIME_STAMP field.
-#define BR_CAN_CS_TIME_STAMP(x, n) (HW_CAN_CS(x, n).B.TIME_STAMP)
-#endif
-
-//! @brief Format value for bitfield CAN_CS_TIME_STAMP.
-#define BF_CAN_CS_TIME_STAMP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_TIME_STAMP), uint32_t) & BM_CAN_CS_TIME_STAMP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TIME_STAMP field to a new value.
-#define BW_CAN_CS_TIME_STAMP(x, n, v) (HW_CAN_CS_WR(x, n, (HW_CAN_CS_RD(x, n) & ~BM_CAN_CS_TIME_STAMP) | BF_CAN_CS_TIME_STAMP(v)))
-#endif
-//@}
-
-/*!
- * @name Register CAN_CS, field DLC[19:16] (RW)
- */
-//@{
-#define BP_CAN_CS_DLC (16U) //!< Bit position for CAN_CS_DLC.
-#define BM_CAN_CS_DLC (0x000F0000U) //!< Bit mask for CAN_CS_DLC.
-#define BS_CAN_CS_DLC (4U) //!< Bit field size in bits for CAN_CS_DLC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CS_DLC field.
-#define BR_CAN_CS_DLC(x, n) (HW_CAN_CS(x, n).B.DLC)
-#endif
-
-//! @brief Format value for bitfield CAN_CS_DLC.
-#define BF_CAN_CS_DLC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_DLC), uint32_t) & BM_CAN_CS_DLC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DLC field to a new value.
-#define BW_CAN_CS_DLC(x, n, v) (HW_CAN_CS_WR(x, n, (HW_CAN_CS_RD(x, n) & ~BM_CAN_CS_DLC) | BF_CAN_CS_DLC(v)))
-#endif
-//@}
-
-/*!
- * @name Register CAN_CS, field RTR[20] (RW)
- */
-//@{
-#define BP_CAN_CS_RTR (20U) //!< Bit position for CAN_CS_RTR.
-#define BM_CAN_CS_RTR (0x00100000U) //!< Bit mask for CAN_CS_RTR.
-#define BS_CAN_CS_RTR (1U) //!< Bit field size in bits for CAN_CS_RTR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CS_RTR field.
-#define BR_CAN_CS_RTR(x, n) (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_RTR))
-#endif
-
-//! @brief Format value for bitfield CAN_CS_RTR.
-#define BF_CAN_CS_RTR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_RTR), uint32_t) & BM_CAN_CS_RTR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RTR field to a new value.
-#define BW_CAN_CS_RTR(x, n, v) (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_RTR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_CS, field IDE[21] (RW)
- */
-//@{
-#define BP_CAN_CS_IDE (21U) //!< Bit position for CAN_CS_IDE.
-#define BM_CAN_CS_IDE (0x00200000U) //!< Bit mask for CAN_CS_IDE.
-#define BS_CAN_CS_IDE (1U) //!< Bit field size in bits for CAN_CS_IDE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CS_IDE field.
-#define BR_CAN_CS_IDE(x, n) (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_IDE))
-#endif
-
-//! @brief Format value for bitfield CAN_CS_IDE.
-#define BF_CAN_CS_IDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_IDE), uint32_t) & BM_CAN_CS_IDE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IDE field to a new value.
-#define BW_CAN_CS_IDE(x, n, v) (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_IDE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_CS, field SRR[22] (RW)
- */
-//@{
-#define BP_CAN_CS_SRR (22U) //!< Bit position for CAN_CS_SRR.
-#define BM_CAN_CS_SRR (0x00400000U) //!< Bit mask for CAN_CS_SRR.
-#define BS_CAN_CS_SRR (1U) //!< Bit field size in bits for CAN_CS_SRR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CS_SRR field.
-#define BR_CAN_CS_SRR(x, n) (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_SRR))
-#endif
-
-//! @brief Format value for bitfield CAN_CS_SRR.
-#define BF_CAN_CS_SRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_SRR), uint32_t) & BM_CAN_CS_SRR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SRR field to a new value.
-#define BW_CAN_CS_SRR(x, n, v) (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_SRR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CAN_CS, field CODE[27:24] (RW)
- */
-//@{
-#define BP_CAN_CS_CODE (24U) //!< Bit position for CAN_CS_CODE.
-#define BM_CAN_CS_CODE (0x0F000000U) //!< Bit mask for CAN_CS_CODE.
-#define BS_CAN_CS_CODE (4U) //!< Bit field size in bits for CAN_CS_CODE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_CS_CODE field.
-#define BR_CAN_CS_CODE(x, n) (HW_CAN_CS(x, n).B.CODE)
-#endif
-
-//! @brief Format value for bitfield CAN_CS_CODE.
-#define BF_CAN_CS_CODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_CODE), uint32_t) & BM_CAN_CS_CODE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CODE field to a new value.
-#define BW_CAN_CS_CODE(x, n, v) (HW_CAN_CS_WR(x, n, (HW_CAN_CS_RD(x, n) & ~BM_CAN_CS_CODE) | BF_CAN_CS_CODE(v)))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_CAN_ID - Message Buffer 0 ID Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAN_ID - Message Buffer 0 ID Register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_can_id
-{
- uint32_t U;
- struct _hw_can_id_bitfields
- {
- uint32_t EXT : 18; //!< [17:0] Contains extended (LOW word)
- //! identifier of message buffer.
- uint32_t STD : 11; //!< [28:18] Contains standard/extended (HIGH
- //! word) identifier of message buffer.
- uint32_t PRIO : 3; //!< [31:29] Local priority. This 3-bit fieldis
- //! only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx
- //! buffers. These bits are not transmitted. They are appended to the
- //! regular ID to define the transmission priority.
- } B;
-} hw_can_id_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAN_ID register
- */
-//@{
-#define HW_CAN_ID_COUNT (16U)
-
-#define HW_CAN_ID_ADDR(x, n) (REGS_CAN_BASE(x) + 0x84U + (0x10U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAN_ID(x, n) (*(__IO hw_can_id_t *) HW_CAN_ID_ADDR(x, n))
-#define HW_CAN_ID_RD(x, n) (HW_CAN_ID(x, n).U)
-#define HW_CAN_ID_WR(x, n, v) (HW_CAN_ID(x, n).U = (v))
-#define HW_CAN_ID_SET(x, n, v) (HW_CAN_ID_WR(x, n, HW_CAN_ID_RD(x, n) | (v)))
-#define HW_CAN_ID_CLR(x, n, v) (HW_CAN_ID_WR(x, n, HW_CAN_ID_RD(x, n) & ~(v)))
-#define HW_CAN_ID_TOG(x, n, v) (HW_CAN_ID_WR(x, n, HW_CAN_ID_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAN_ID bitfields
- */
-
-/*!
- * @name Register CAN_ID, field EXT[17:0] (RW)
- */
-//@{
-#define BP_CAN_ID_EXT (0U) //!< Bit position for CAN_ID_EXT.
-#define BM_CAN_ID_EXT (0x0003FFFFU) //!< Bit mask for CAN_ID_EXT.
-#define BS_CAN_ID_EXT (18U) //!< Bit field size in bits for CAN_ID_EXT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_ID_EXT field.
-#define BR_CAN_ID_EXT(x, n) (HW_CAN_ID(x, n).B.EXT)
-#endif
-
-//! @brief Format value for bitfield CAN_ID_EXT.
-#define BF_CAN_ID_EXT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ID_EXT), uint32_t) & BM_CAN_ID_EXT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EXT field to a new value.
-#define BW_CAN_ID_EXT(x, n, v) (HW_CAN_ID_WR(x, n, (HW_CAN_ID_RD(x, n) & ~BM_CAN_ID_EXT) | BF_CAN_ID_EXT(v)))
-#endif
-//@}
-
-/*!
- * @name Register CAN_ID, field STD[28:18] (RW)
- */
-//@{
-#define BP_CAN_ID_STD (18U) //!< Bit position for CAN_ID_STD.
-#define BM_CAN_ID_STD (0x1FFC0000U) //!< Bit mask for CAN_ID_STD.
-#define BS_CAN_ID_STD (11U) //!< Bit field size in bits for CAN_ID_STD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_ID_STD field.
-#define BR_CAN_ID_STD(x, n) (HW_CAN_ID(x, n).B.STD)
-#endif
-
-//! @brief Format value for bitfield CAN_ID_STD.
-#define BF_CAN_ID_STD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ID_STD), uint32_t) & BM_CAN_ID_STD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the STD field to a new value.
-#define BW_CAN_ID_STD(x, n, v) (HW_CAN_ID_WR(x, n, (HW_CAN_ID_RD(x, n) & ~BM_CAN_ID_STD) | BF_CAN_ID_STD(v)))
-#endif
-//@}
-
-/*!
- * @name Register CAN_ID, field PRIO[31:29] (RW)
- */
-//@{
-#define BP_CAN_ID_PRIO (29U) //!< Bit position for CAN_ID_PRIO.
-#define BM_CAN_ID_PRIO (0xE0000000U) //!< Bit mask for CAN_ID_PRIO.
-#define BS_CAN_ID_PRIO (3U) //!< Bit field size in bits for CAN_ID_PRIO.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_ID_PRIO field.
-#define BR_CAN_ID_PRIO(x, n) (HW_CAN_ID(x, n).B.PRIO)
-#endif
-
-//! @brief Format value for bitfield CAN_ID_PRIO.
-#define BF_CAN_ID_PRIO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ID_PRIO), uint32_t) & BM_CAN_ID_PRIO)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PRIO field to a new value.
-#define BW_CAN_ID_PRIO(x, n, v) (HW_CAN_ID_WR(x, n, (HW_CAN_ID_RD(x, n) & ~BM_CAN_ID_PRIO) | BF_CAN_ID_PRIO(v)))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_CAN_WORD0 - Message Buffer 0 WORD0 Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAN_WORD0 - Message Buffer 0 WORD0 Register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_can_word0
-{
- uint32_t U;
- struct _hw_can_word0_bitfields
- {
- uint32_t DATA_BYTE_3 : 8; //!< [7:0] Data byte 3 of Rx/Tx frame.
- uint32_t DATA_BYTE_2 : 8; //!< [15:8] Data byte 2 of Rx/Tx frame.
- uint32_t DATA_BYTE_1 : 8; //!< [23:16] Data byte 1 of Rx/Tx frame.
- uint32_t DATA_BYTE_0 : 8; //!< [31:24] Data byte 0 of Rx/Tx frame.
- } B;
-} hw_can_word0_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAN_WORD0 register
- */
-//@{
-#define HW_CAN_WORD0_COUNT (16U)
-
-#define HW_CAN_WORD0_ADDR(x, n) (REGS_CAN_BASE(x) + 0x88U + (0x10U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAN_WORD0(x, n) (*(__IO hw_can_word0_t *) HW_CAN_WORD0_ADDR(x, n))
-#define HW_CAN_WORD0_RD(x, n) (HW_CAN_WORD0(x, n).U)
-#define HW_CAN_WORD0_WR(x, n, v) (HW_CAN_WORD0(x, n).U = (v))
-#define HW_CAN_WORD0_SET(x, n, v) (HW_CAN_WORD0_WR(x, n, HW_CAN_WORD0_RD(x, n) | (v)))
-#define HW_CAN_WORD0_CLR(x, n, v) (HW_CAN_WORD0_WR(x, n, HW_CAN_WORD0_RD(x, n) & ~(v)))
-#define HW_CAN_WORD0_TOG(x, n, v) (HW_CAN_WORD0_WR(x, n, HW_CAN_WORD0_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAN_WORD0 bitfields
- */
-
-/*!
- * @name Register CAN_WORD0, field DATA_BYTE_3[7:0] (RW)
- */
-//@{
-#define BP_CAN_WORD0_DATA_BYTE_3 (0U) //!< Bit position for CAN_WORD0_DATA_BYTE_3.
-#define BM_CAN_WORD0_DATA_BYTE_3 (0x000000FFU) //!< Bit mask for CAN_WORD0_DATA_BYTE_3.
-#define BS_CAN_WORD0_DATA_BYTE_3 (8U) //!< Bit field size in bits for CAN_WORD0_DATA_BYTE_3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_WORD0_DATA_BYTE_3 field.
-#define BR_CAN_WORD0_DATA_BYTE_3(x, n) (HW_CAN_WORD0(x, n).B.DATA_BYTE_3)
-#endif
-
-//! @brief Format value for bitfield CAN_WORD0_DATA_BYTE_3.
-#define BF_CAN_WORD0_DATA_BYTE_3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD0_DATA_BYTE_3), uint32_t) & BM_CAN_WORD0_DATA_BYTE_3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DATA_BYTE_3 field to a new value.
-#define BW_CAN_WORD0_DATA_BYTE_3(x, n, v) (HW_CAN_WORD0_WR(x, n, (HW_CAN_WORD0_RD(x, n) & ~BM_CAN_WORD0_DATA_BYTE_3) | BF_CAN_WORD0_DATA_BYTE_3(v)))
-#endif
-//@}
-
-/*!
- * @name Register CAN_WORD0, field DATA_BYTE_2[15:8] (RW)
- */
-//@{
-#define BP_CAN_WORD0_DATA_BYTE_2 (8U) //!< Bit position for CAN_WORD0_DATA_BYTE_2.
-#define BM_CAN_WORD0_DATA_BYTE_2 (0x0000FF00U) //!< Bit mask for CAN_WORD0_DATA_BYTE_2.
-#define BS_CAN_WORD0_DATA_BYTE_2 (8U) //!< Bit field size in bits for CAN_WORD0_DATA_BYTE_2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_WORD0_DATA_BYTE_2 field.
-#define BR_CAN_WORD0_DATA_BYTE_2(x, n) (HW_CAN_WORD0(x, n).B.DATA_BYTE_2)
-#endif
-
-//! @brief Format value for bitfield CAN_WORD0_DATA_BYTE_2.
-#define BF_CAN_WORD0_DATA_BYTE_2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD0_DATA_BYTE_2), uint32_t) & BM_CAN_WORD0_DATA_BYTE_2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DATA_BYTE_2 field to a new value.
-#define BW_CAN_WORD0_DATA_BYTE_2(x, n, v) (HW_CAN_WORD0_WR(x, n, (HW_CAN_WORD0_RD(x, n) & ~BM_CAN_WORD0_DATA_BYTE_2) | BF_CAN_WORD0_DATA_BYTE_2(v)))
-#endif
-//@}
-
-/*!
- * @name Register CAN_WORD0, field DATA_BYTE_1[23:16] (RW)
- */
-//@{
-#define BP_CAN_WORD0_DATA_BYTE_1 (16U) //!< Bit position for CAN_WORD0_DATA_BYTE_1.
-#define BM_CAN_WORD0_DATA_BYTE_1 (0x00FF0000U) //!< Bit mask for CAN_WORD0_DATA_BYTE_1.
-#define BS_CAN_WORD0_DATA_BYTE_1 (8U) //!< Bit field size in bits for CAN_WORD0_DATA_BYTE_1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_WORD0_DATA_BYTE_1 field.
-#define BR_CAN_WORD0_DATA_BYTE_1(x, n) (HW_CAN_WORD0(x, n).B.DATA_BYTE_1)
-#endif
-
-//! @brief Format value for bitfield CAN_WORD0_DATA_BYTE_1.
-#define BF_CAN_WORD0_DATA_BYTE_1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD0_DATA_BYTE_1), uint32_t) & BM_CAN_WORD0_DATA_BYTE_1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DATA_BYTE_1 field to a new value.
-#define BW_CAN_WORD0_DATA_BYTE_1(x, n, v) (HW_CAN_WORD0_WR(x, n, (HW_CAN_WORD0_RD(x, n) & ~BM_CAN_WORD0_DATA_BYTE_1) | BF_CAN_WORD0_DATA_BYTE_1(v)))
-#endif
-//@}
-
-/*!
- * @name Register CAN_WORD0, field DATA_BYTE_0[31:24] (RW)
- */
-//@{
-#define BP_CAN_WORD0_DATA_BYTE_0 (24U) //!< Bit position for CAN_WORD0_DATA_BYTE_0.
-#define BM_CAN_WORD0_DATA_BYTE_0 (0xFF000000U) //!< Bit mask for CAN_WORD0_DATA_BYTE_0.
-#define BS_CAN_WORD0_DATA_BYTE_0 (8U) //!< Bit field size in bits for CAN_WORD0_DATA_BYTE_0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_WORD0_DATA_BYTE_0 field.
-#define BR_CAN_WORD0_DATA_BYTE_0(x, n) (HW_CAN_WORD0(x, n).B.DATA_BYTE_0)
-#endif
-
-//! @brief Format value for bitfield CAN_WORD0_DATA_BYTE_0.
-#define BF_CAN_WORD0_DATA_BYTE_0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD0_DATA_BYTE_0), uint32_t) & BM_CAN_WORD0_DATA_BYTE_0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DATA_BYTE_0 field to a new value.
-#define BW_CAN_WORD0_DATA_BYTE_0(x, n, v) (HW_CAN_WORD0_WR(x, n, (HW_CAN_WORD0_RD(x, n) & ~BM_CAN_WORD0_DATA_BYTE_0) | BF_CAN_WORD0_DATA_BYTE_0(v)))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_CAN_WORD1 - Message Buffer 0 WORD1 Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAN_WORD1 - Message Buffer 0 WORD1 Register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_can_word1
-{
- uint32_t U;
- struct _hw_can_word1_bitfields
- {
- uint32_t DATA_BYTE_7 : 8; //!< [7:0] Data byte 7 of Rx/Tx frame.
- uint32_t DATA_BYTE_6 : 8; //!< [15:8] Data byte 6 of Rx/Tx frame.
- uint32_t DATA_BYTE_5 : 8; //!< [23:16] Data byte 5 of Rx/Tx frame.
- uint32_t DATA_BYTE_4 : 8; //!< [31:24] Data byte 4 of Rx/Tx frame.
- } B;
-} hw_can_word1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAN_WORD1 register
- */
-//@{
-#define HW_CAN_WORD1_COUNT (16U)
-
-#define HW_CAN_WORD1_ADDR(x, n) (REGS_CAN_BASE(x) + 0x8CU + (0x10U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAN_WORD1(x, n) (*(__IO hw_can_word1_t *) HW_CAN_WORD1_ADDR(x, n))
-#define HW_CAN_WORD1_RD(x, n) (HW_CAN_WORD1(x, n).U)
-#define HW_CAN_WORD1_WR(x, n, v) (HW_CAN_WORD1(x, n).U = (v))
-#define HW_CAN_WORD1_SET(x, n, v) (HW_CAN_WORD1_WR(x, n, HW_CAN_WORD1_RD(x, n) | (v)))
-#define HW_CAN_WORD1_CLR(x, n, v) (HW_CAN_WORD1_WR(x, n, HW_CAN_WORD1_RD(x, n) & ~(v)))
-#define HW_CAN_WORD1_TOG(x, n, v) (HW_CAN_WORD1_WR(x, n, HW_CAN_WORD1_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAN_WORD1 bitfields
- */
-
-/*!
- * @name Register CAN_WORD1, field DATA_BYTE_7[7:0] (RW)
- */
-//@{
-#define BP_CAN_WORD1_DATA_BYTE_7 (0U) //!< Bit position for CAN_WORD1_DATA_BYTE_7.
-#define BM_CAN_WORD1_DATA_BYTE_7 (0x000000FFU) //!< Bit mask for CAN_WORD1_DATA_BYTE_7.
-#define BS_CAN_WORD1_DATA_BYTE_7 (8U) //!< Bit field size in bits for CAN_WORD1_DATA_BYTE_7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_WORD1_DATA_BYTE_7 field.
-#define BR_CAN_WORD1_DATA_BYTE_7(x, n) (HW_CAN_WORD1(x, n).B.DATA_BYTE_7)
-#endif
-
-//! @brief Format value for bitfield CAN_WORD1_DATA_BYTE_7.
-#define BF_CAN_WORD1_DATA_BYTE_7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD1_DATA_BYTE_7), uint32_t) & BM_CAN_WORD1_DATA_BYTE_7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DATA_BYTE_7 field to a new value.
-#define BW_CAN_WORD1_DATA_BYTE_7(x, n, v) (HW_CAN_WORD1_WR(x, n, (HW_CAN_WORD1_RD(x, n) & ~BM_CAN_WORD1_DATA_BYTE_7) | BF_CAN_WORD1_DATA_BYTE_7(v)))
-#endif
-//@}
-
-/*!
- * @name Register CAN_WORD1, field DATA_BYTE_6[15:8] (RW)
- */
-//@{
-#define BP_CAN_WORD1_DATA_BYTE_6 (8U) //!< Bit position for CAN_WORD1_DATA_BYTE_6.
-#define BM_CAN_WORD1_DATA_BYTE_6 (0x0000FF00U) //!< Bit mask for CAN_WORD1_DATA_BYTE_6.
-#define BS_CAN_WORD1_DATA_BYTE_6 (8U) //!< Bit field size in bits for CAN_WORD1_DATA_BYTE_6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_WORD1_DATA_BYTE_6 field.
-#define BR_CAN_WORD1_DATA_BYTE_6(x, n) (HW_CAN_WORD1(x, n).B.DATA_BYTE_6)
-#endif
-
-//! @brief Format value for bitfield CAN_WORD1_DATA_BYTE_6.
-#define BF_CAN_WORD1_DATA_BYTE_6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD1_DATA_BYTE_6), uint32_t) & BM_CAN_WORD1_DATA_BYTE_6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DATA_BYTE_6 field to a new value.
-#define BW_CAN_WORD1_DATA_BYTE_6(x, n, v) (HW_CAN_WORD1_WR(x, n, (HW_CAN_WORD1_RD(x, n) & ~BM_CAN_WORD1_DATA_BYTE_6) | BF_CAN_WORD1_DATA_BYTE_6(v)))
-#endif
-//@}
-
-/*!
- * @name Register CAN_WORD1, field DATA_BYTE_5[23:16] (RW)
- */
-//@{
-#define BP_CAN_WORD1_DATA_BYTE_5 (16U) //!< Bit position for CAN_WORD1_DATA_BYTE_5.
-#define BM_CAN_WORD1_DATA_BYTE_5 (0x00FF0000U) //!< Bit mask for CAN_WORD1_DATA_BYTE_5.
-#define BS_CAN_WORD1_DATA_BYTE_5 (8U) //!< Bit field size in bits for CAN_WORD1_DATA_BYTE_5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_WORD1_DATA_BYTE_5 field.
-#define BR_CAN_WORD1_DATA_BYTE_5(x, n) (HW_CAN_WORD1(x, n).B.DATA_BYTE_5)
-#endif
-
-//! @brief Format value for bitfield CAN_WORD1_DATA_BYTE_5.
-#define BF_CAN_WORD1_DATA_BYTE_5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD1_DATA_BYTE_5), uint32_t) & BM_CAN_WORD1_DATA_BYTE_5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DATA_BYTE_5 field to a new value.
-#define BW_CAN_WORD1_DATA_BYTE_5(x, n, v) (HW_CAN_WORD1_WR(x, n, (HW_CAN_WORD1_RD(x, n) & ~BM_CAN_WORD1_DATA_BYTE_5) | BF_CAN_WORD1_DATA_BYTE_5(v)))
-#endif
-//@}
-
-/*!
- * @name Register CAN_WORD1, field DATA_BYTE_4[31:24] (RW)
- */
-//@{
-#define BP_CAN_WORD1_DATA_BYTE_4 (24U) //!< Bit position for CAN_WORD1_DATA_BYTE_4.
-#define BM_CAN_WORD1_DATA_BYTE_4 (0xFF000000U) //!< Bit mask for CAN_WORD1_DATA_BYTE_4.
-#define BS_CAN_WORD1_DATA_BYTE_4 (8U) //!< Bit field size in bits for CAN_WORD1_DATA_BYTE_4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_WORD1_DATA_BYTE_4 field.
-#define BR_CAN_WORD1_DATA_BYTE_4(x, n) (HW_CAN_WORD1(x, n).B.DATA_BYTE_4)
-#endif
-
-//! @brief Format value for bitfield CAN_WORD1_DATA_BYTE_4.
-#define BF_CAN_WORD1_DATA_BYTE_4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD1_DATA_BYTE_4), uint32_t) & BM_CAN_WORD1_DATA_BYTE_4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DATA_BYTE_4 field to a new value.
-#define BW_CAN_WORD1_DATA_BYTE_4(x, n, v) (HW_CAN_WORD1_WR(x, n, (HW_CAN_WORD1_RD(x, n) & ~BM_CAN_WORD1_DATA_BYTE_4) | BF_CAN_WORD1_DATA_BYTE_4(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CAN_RXIMRn - Rx Individual Mask Registers
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAN_RXIMRn - Rx Individual Mask Registers (RW)
- *
- * Reset value: 0x00000000U
- *
- * These registers are located in RAM. RXIMR are used as acceptance masks for ID
- * filtering in Rx MBs and the Rx FIFO. If the Rx FIFO is not enabled, one mask
- * register is provided for each available Mailbox, providing ID masking
- * capability on a per Mailbox basis. When the Rx FIFO is enabled (MCR[RFEN] bit is
- * asserted), up to 32 Rx Individual Mask Registers can apply to the Rx FIFO ID Filter
- * Table elements on a one-to-one correspondence depending on the setting of
- * CTRL2[RFFN]. RXIMR can only be written by the CPU while the module is in Freeze
- * mode; otherwise, they are blocked by hardware. The Individual Rx Mask Registers
- * are not affected by reset and must be explicitly initialized prior to any
- * reception.
- */
-typedef union _hw_can_rximrn
-{
- uint32_t U;
- struct _hw_can_rximrn_bitfields
- {
- uint32_t MI : 32; //!< [31:0] Individual Mask Bits
- } B;
-} hw_can_rximrn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAN_RXIMRn register
- */
-//@{
-#define HW_CAN_RXIMRn_COUNT (16U)
-
-#define HW_CAN_RXIMRn_ADDR(x, n) (REGS_CAN_BASE(x) + 0x880U + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAN_RXIMRn(x, n) (*(__IO hw_can_rximrn_t *) HW_CAN_RXIMRn_ADDR(x, n))
-#define HW_CAN_RXIMRn_RD(x, n) (HW_CAN_RXIMRn(x, n).U)
-#define HW_CAN_RXIMRn_WR(x, n, v) (HW_CAN_RXIMRn(x, n).U = (v))
-#define HW_CAN_RXIMRn_SET(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) | (v)))
-#define HW_CAN_RXIMRn_CLR(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) & ~(v)))
-#define HW_CAN_RXIMRn_TOG(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAN_RXIMRn bitfields
- */
-
-/*!
- * @name Register CAN_RXIMRn, field MI[31:0] (RW)
- *
- * Each Individual Mask Bit masks the corresponding bit in both the Mailbox
- * filter and Rx FIFO ID Filter Table element in distinct ways. For Mailbox filters,
- * see the RXMGMASK register description. For Rx FIFO ID Filter Table elements,
- * see the RXFGMASK register description.
- *
- * Values:
- * - 0 - The corresponding bit in the filter is "don't care."
- * - 1 - The corresponding bit in the filter is checked.
- */
-//@{
-#define BP_CAN_RXIMRn_MI (0U) //!< Bit position for CAN_RXIMRn_MI.
-#define BM_CAN_RXIMRn_MI (0xFFFFFFFFU) //!< Bit mask for CAN_RXIMRn_MI.
-#define BS_CAN_RXIMRn_MI (32U) //!< Bit field size in bits for CAN_RXIMRn_MI.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAN_RXIMRn_MI field.
-#define BR_CAN_RXIMRn_MI(x, n) (HW_CAN_RXIMRn(x, n).U)
-#endif
-
-//! @brief Format value for bitfield CAN_RXIMRn_MI.
-#define BF_CAN_RXIMRn_MI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_RXIMRn_MI), uint32_t) & BM_CAN_RXIMRn_MI)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MI field to a new value.
-#define BW_CAN_RXIMRn_MI(x, n, v) (HW_CAN_RXIMRn_WR(x, n, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_can_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All CAN module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_can
-{
- __IO hw_can_mcr_t MCR; //!< [0x0] Module Configuration Register
- __IO hw_can_ctrl1_t CTRL1; //!< [0x4] Control 1 register
- __IO hw_can_timer_t TIMER; //!< [0x8] Free Running Timer
- uint8_t _reserved0[4];
- __IO hw_can_rxmgmask_t RXMGMASK; //!< [0x10] Rx Mailboxes Global Mask Register
- __IO hw_can_rx14mask_t RX14MASK; //!< [0x14] Rx 14 Mask register
- __IO hw_can_rx15mask_t RX15MASK; //!< [0x18] Rx 15 Mask register
- __IO hw_can_ecr_t ECR; //!< [0x1C] Error Counter
- __IO hw_can_esr1_t ESR1; //!< [0x20] Error and Status 1 register
- uint8_t _reserved1[4];
- __IO hw_can_imask1_t IMASK1; //!< [0x28] Interrupt Masks 1 register
- uint8_t _reserved2[4];
- __IO hw_can_iflag1_t IFLAG1; //!< [0x30] Interrupt Flags 1 register
- __IO hw_can_ctrl2_t CTRL2; //!< [0x34] Control 2 register
- __I hw_can_esr2_t ESR2; //!< [0x38] Error and Status 2 register
- uint8_t _reserved3[8];
- __I hw_can_crcr_t CRCR; //!< [0x44] CRC Register
- __IO hw_can_rxfgmask_t RXFGMASK; //!< [0x48] Rx FIFO Global Mask register
- __I hw_can_rxfir_t RXFIR; //!< [0x4C] Rx FIFO Information Register
- uint8_t _reserved4[48];
- struct {
- __IO hw_can_cs_t CS; //!< [0x80] Message Buffer 0 CS Register
- __IO hw_can_id_t ID; //!< [0x84] Message Buffer 0 ID Register
- __IO hw_can_word0_t WORD0; //!< [0x88] Message Buffer 0 WORD0 Register
- __IO hw_can_word1_t WORD1; //!< [0x8C] Message Buffer 0 WORD1 Register
- } MB[16];
- uint8_t _reserved5[1792];
- __IO hw_can_rximrn_t RXIMRn[16]; //!< [0x880] Rx Individual Mask Registers
-} hw_can_t;
-#pragma pack()
-
-//! @brief Macro to access all CAN registers.
-//! @param x CAN instance number.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_CAN(0)</code>.
-#define HW_CAN(x) (*(hw_can_t *) REGS_CAN_BASE(x))
-#endif
-
-#endif // __HW_CAN_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_cau.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1463 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_CAU_REGISTERS_H__
-#define __HW_CAU_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 CAU
- *
- * Memory Mapped Cryptographic Acceleration Unit (MMCAU)
- *
- * Registers defined in this header file:
- * - HW_CAU_DIRECT - Direct access register 0
- * - HW_CAU_LDR_CASR - Status register - Load Register command
- * - HW_CAU_LDR_CAA - Accumulator register - Load Register command
- * - HW_CAU_LDR_CA - General Purpose Register 0 - Load Register command
- * - HW_CAU_STR_CASR - Status register - Store Register command
- * - HW_CAU_STR_CAA - Accumulator register - Store Register command
- * - HW_CAU_STR_CA - General Purpose Register 0 - Store Register command
- * - HW_CAU_ADR_CASR - Status register - Add Register command
- * - HW_CAU_ADR_CAA - Accumulator register - Add to register command
- * - HW_CAU_ADR_CA - General Purpose Register 0 - Add to register command
- * - HW_CAU_RADR_CASR - Status register - Reverse and Add to Register command
- * - HW_CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command
- * - HW_CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command
- * - HW_CAU_XOR_CASR - Status register - Exclusive Or command
- * - HW_CAU_XOR_CAA - Accumulator register - Exclusive Or command
- * - HW_CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command
- * - HW_CAU_ROTL_CASR - Status register - Rotate Left command
- * - HW_CAU_ROTL_CAA - Accumulator register - Rotate Left command
- * - HW_CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command
- * - HW_CAU_AESC_CASR - Status register - AES Column Operation command
- * - HW_CAU_AESC_CAA - Accumulator register - AES Column Operation command
- * - HW_CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command
- * - HW_CAU_AESIC_CASR - Status register - AES Inverse Column Operation command
- * - HW_CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command
- * - HW_CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command
- *
- * - hw_cau_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_CAU_BASE
-#define HW_CAU_INSTANCE_COUNT (1U) //!< Number of instances of the CAU module.
-#define REGS_CAU_BASE (0xE0081000U) //!< Base address for CAU.
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CAU_DIRECT - Direct access register 0
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAU_DIRECT - Direct access register 0 (WO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_cau_direct
-{
- uint32_t U;
- struct _hw_cau_direct_bitfields
- {
- uint32_t RESERVED0 : 32; //!< [31:0]
- } B;
-} hw_cau_direct_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAU_DIRECT register
- */
-//@{
-#define HW_CAU_DIRECT_COUNT (16U)
-
-#define HW_CAU_DIRECT_ADDR(n) (REGS_CAU_BASE + 0x0U + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAU_DIRECT(n) (*(__O hw_cau_direct_t *) HW_CAU_DIRECT_ADDR(n))
-#define HW_CAU_DIRECT_WR(n, v) (HW_CAU_DIRECT(n).U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAU_DIRECT bitfields
- */
-
-//-------------------------------------------------------------------------------------------
-// HW_CAU_LDR_CASR - Status register - Load Register command
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAU_LDR_CASR - Status register - Load Register command (WO)
- *
- * Reset value: 0x20000000U
- */
-typedef union _hw_cau_ldr_casr
-{
- uint32_t U;
- struct _hw_cau_ldr_casr_bitfields
- {
- uint32_t IC : 1; //!< [0]
- uint32_t DPE : 1; //!< [1]
- uint32_t RESERVED0 : 26; //!< [27:2]
- uint32_t VER : 4; //!< [31:28] CAU version
- } B;
-} hw_cau_ldr_casr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAU_LDR_CASR register
- */
-//@{
-#define HW_CAU_LDR_CASR_ADDR (REGS_CAU_BASE + 0x840U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAU_LDR_CASR (*(__O hw_cau_ldr_casr_t *) HW_CAU_LDR_CASR_ADDR)
-#define HW_CAU_LDR_CASR_WR(v) (HW_CAU_LDR_CASR.U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAU_LDR_CASR bitfields
- */
-
-/*!
- * @name Register CAU_LDR_CASR, field IC[0] (WO)
- *
- * Values:
- * - 0 - No illegal commands issued
- * - 1 - Illegal command issued
- */
-//@{
-#define BP_CAU_LDR_CASR_IC (0U) //!< Bit position for CAU_LDR_CASR_IC.
-#define BM_CAU_LDR_CASR_IC (0x00000001U) //!< Bit mask for CAU_LDR_CASR_IC.
-#define BS_CAU_LDR_CASR_IC (1U) //!< Bit field size in bits for CAU_LDR_CASR_IC.
-
-//! @brief Format value for bitfield CAU_LDR_CASR_IC.
-#define BF_CAU_LDR_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_LDR_CASR_IC), uint32_t) & BM_CAU_LDR_CASR_IC)
-//@}
-
-/*!
- * @name Register CAU_LDR_CASR, field DPE[1] (WO)
- *
- * Values:
- * - 0 - No error detected
- * - 1 - DES key parity error detected
- */
-//@{
-#define BP_CAU_LDR_CASR_DPE (1U) //!< Bit position for CAU_LDR_CASR_DPE.
-#define BM_CAU_LDR_CASR_DPE (0x00000002U) //!< Bit mask for CAU_LDR_CASR_DPE.
-#define BS_CAU_LDR_CASR_DPE (1U) //!< Bit field size in bits for CAU_LDR_CASR_DPE.
-
-//! @brief Format value for bitfield CAU_LDR_CASR_DPE.
-#define BF_CAU_LDR_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_LDR_CASR_DPE), uint32_t) & BM_CAU_LDR_CASR_DPE)
-//@}
-
-/*!
- * @name Register CAU_LDR_CASR, field VER[31:28] (WO)
- *
- * Values:
- * - 0001 - Initial CAU version
- * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
- * value on this device)
- */
-//@{
-#define BP_CAU_LDR_CASR_VER (28U) //!< Bit position for CAU_LDR_CASR_VER.
-#define BM_CAU_LDR_CASR_VER (0xF0000000U) //!< Bit mask for CAU_LDR_CASR_VER.
-#define BS_CAU_LDR_CASR_VER (4U) //!< Bit field size in bits for CAU_LDR_CASR_VER.
-
-//! @brief Format value for bitfield CAU_LDR_CASR_VER.
-#define BF_CAU_LDR_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_LDR_CASR_VER), uint32_t) & BM_CAU_LDR_CASR_VER)
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CAU_LDR_CAA - Accumulator register - Load Register command
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAU_LDR_CAA - Accumulator register - Load Register command (WO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_cau_ldr_caa
-{
- uint32_t U;
- struct _hw_cau_ldr_caa_bitfields
- {
- uint32_t RESERVED0 : 32; //!< [31:0]
- } B;
-} hw_cau_ldr_caa_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAU_LDR_CAA register
- */
-//@{
-#define HW_CAU_LDR_CAA_ADDR (REGS_CAU_BASE + 0x844U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAU_LDR_CAA (*(__O hw_cau_ldr_caa_t *) HW_CAU_LDR_CAA_ADDR)
-#define HW_CAU_LDR_CAA_WR(v) (HW_CAU_LDR_CAA.U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAU_LDR_CAA bitfields
- */
-
-//-------------------------------------------------------------------------------------------
-// HW_CAU_LDR_CA - General Purpose Register 0 - Load Register command
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAU_LDR_CA - General Purpose Register 0 - Load Register command (WO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_cau_ldr_ca
-{
- uint32_t U;
- struct _hw_cau_ldr_ca_bitfields
- {
- uint32_t RESERVED0 : 32; //!< [31:0]
- } B;
-} hw_cau_ldr_ca_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAU_LDR_CA register
- */
-//@{
-#define HW_CAU_LDR_CA_COUNT (9U)
-
-#define HW_CAU_LDR_CA_ADDR(n) (REGS_CAU_BASE + 0x848U + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAU_LDR_CA(n) (*(__O hw_cau_ldr_ca_t *) HW_CAU_LDR_CA_ADDR(n))
-#define HW_CAU_LDR_CA_WR(n, v) (HW_CAU_LDR_CA(n).U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAU_LDR_CA bitfields
- */
-
-//-------------------------------------------------------------------------------------------
-// HW_CAU_STR_CASR - Status register - Store Register command
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAU_STR_CASR - Status register - Store Register command (RO)
- *
- * Reset value: 0x20000000U
- */
-typedef union _hw_cau_str_casr
-{
- uint32_t U;
- struct _hw_cau_str_casr_bitfields
- {
- uint32_t IC : 1; //!< [0]
- uint32_t DPE : 1; //!< [1]
- uint32_t RESERVED0 : 26; //!< [27:2]
- uint32_t VER : 4; //!< [31:28] CAU version
- } B;
-} hw_cau_str_casr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAU_STR_CASR register
- */
-//@{
-#define HW_CAU_STR_CASR_ADDR (REGS_CAU_BASE + 0x880U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAU_STR_CASR (*(__I hw_cau_str_casr_t *) HW_CAU_STR_CASR_ADDR)
-#define HW_CAU_STR_CASR_RD() (HW_CAU_STR_CASR.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAU_STR_CASR bitfields
- */
-
-/*!
- * @name Register CAU_STR_CASR, field IC[0] (RO)
- *
- * Values:
- * - 0 - No illegal commands issued
- * - 1 - Illegal command issued
- */
-//@{
-#define BP_CAU_STR_CASR_IC (0U) //!< Bit position for CAU_STR_CASR_IC.
-#define BM_CAU_STR_CASR_IC (0x00000001U) //!< Bit mask for CAU_STR_CASR_IC.
-#define BS_CAU_STR_CASR_IC (1U) //!< Bit field size in bits for CAU_STR_CASR_IC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAU_STR_CASR_IC field.
-#define BR_CAU_STR_CASR_IC (BITBAND_ACCESS32(HW_CAU_STR_CASR_ADDR, BP_CAU_STR_CASR_IC))
-#endif
-//@}
-
-/*!
- * @name Register CAU_STR_CASR, field DPE[1] (RO)
- *
- * Values:
- * - 0 - No error detected
- * - 1 - DES key parity error detected
- */
-//@{
-#define BP_CAU_STR_CASR_DPE (1U) //!< Bit position for CAU_STR_CASR_DPE.
-#define BM_CAU_STR_CASR_DPE (0x00000002U) //!< Bit mask for CAU_STR_CASR_DPE.
-#define BS_CAU_STR_CASR_DPE (1U) //!< Bit field size in bits for CAU_STR_CASR_DPE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAU_STR_CASR_DPE field.
-#define BR_CAU_STR_CASR_DPE (BITBAND_ACCESS32(HW_CAU_STR_CASR_ADDR, BP_CAU_STR_CASR_DPE))
-#endif
-//@}
-
-/*!
- * @name Register CAU_STR_CASR, field VER[31:28] (RO)
- *
- * Values:
- * - 0001 - Initial CAU version
- * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
- * value on this device)
- */
-//@{
-#define BP_CAU_STR_CASR_VER (28U) //!< Bit position for CAU_STR_CASR_VER.
-#define BM_CAU_STR_CASR_VER (0xF0000000U) //!< Bit mask for CAU_STR_CASR_VER.
-#define BS_CAU_STR_CASR_VER (4U) //!< Bit field size in bits for CAU_STR_CASR_VER.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CAU_STR_CASR_VER field.
-#define BR_CAU_STR_CASR_VER (HW_CAU_STR_CASR.B.VER)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CAU_STR_CAA - Accumulator register - Store Register command
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAU_STR_CAA - Accumulator register - Store Register command (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_cau_str_caa
-{
- uint32_t U;
- struct _hw_cau_str_caa_bitfields
- {
- uint32_t RESERVED0 : 32; //!< [31:0]
- } B;
-} hw_cau_str_caa_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAU_STR_CAA register
- */
-//@{
-#define HW_CAU_STR_CAA_ADDR (REGS_CAU_BASE + 0x884U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAU_STR_CAA (*(__I hw_cau_str_caa_t *) HW_CAU_STR_CAA_ADDR)
-#define HW_CAU_STR_CAA_RD() (HW_CAU_STR_CAA.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAU_STR_CAA bitfields
- */
-
-//-------------------------------------------------------------------------------------------
-// HW_CAU_STR_CA - General Purpose Register 0 - Store Register command
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAU_STR_CA - General Purpose Register 0 - Store Register command (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_cau_str_ca
-{
- uint32_t U;
- struct _hw_cau_str_ca_bitfields
- {
- uint32_t RESERVED0 : 32; //!< [31:0]
- } B;
-} hw_cau_str_ca_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAU_STR_CA register
- */
-//@{
-#define HW_CAU_STR_CA_COUNT (9U)
-
-#define HW_CAU_STR_CA_ADDR(n) (REGS_CAU_BASE + 0x888U + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAU_STR_CA(n) (*(__I hw_cau_str_ca_t *) HW_CAU_STR_CA_ADDR(n))
-#define HW_CAU_STR_CA_RD(n) (HW_CAU_STR_CA(n).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAU_STR_CA bitfields
- */
-
-//-------------------------------------------------------------------------------------------
-// HW_CAU_ADR_CASR - Status register - Add Register command
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAU_ADR_CASR - Status register - Add Register command (WO)
- *
- * Reset value: 0x20000000U
- */
-typedef union _hw_cau_adr_casr
-{
- uint32_t U;
- struct _hw_cau_adr_casr_bitfields
- {
- uint32_t IC : 1; //!< [0]
- uint32_t DPE : 1; //!< [1]
- uint32_t RESERVED0 : 26; //!< [27:2]
- uint32_t VER : 4; //!< [31:28] CAU version
- } B;
-} hw_cau_adr_casr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAU_ADR_CASR register
- */
-//@{
-#define HW_CAU_ADR_CASR_ADDR (REGS_CAU_BASE + 0x8C0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAU_ADR_CASR (*(__O hw_cau_adr_casr_t *) HW_CAU_ADR_CASR_ADDR)
-#define HW_CAU_ADR_CASR_WR(v) (HW_CAU_ADR_CASR.U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAU_ADR_CASR bitfields
- */
-
-/*!
- * @name Register CAU_ADR_CASR, field IC[0] (WO)
- *
- * Values:
- * - 0 - No illegal commands issued
- * - 1 - Illegal command issued
- */
-//@{
-#define BP_CAU_ADR_CASR_IC (0U) //!< Bit position for CAU_ADR_CASR_IC.
-#define BM_CAU_ADR_CASR_IC (0x00000001U) //!< Bit mask for CAU_ADR_CASR_IC.
-#define BS_CAU_ADR_CASR_IC (1U) //!< Bit field size in bits for CAU_ADR_CASR_IC.
-
-//! @brief Format value for bitfield CAU_ADR_CASR_IC.
-#define BF_CAU_ADR_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ADR_CASR_IC), uint32_t) & BM_CAU_ADR_CASR_IC)
-//@}
-
-/*!
- * @name Register CAU_ADR_CASR, field DPE[1] (WO)
- *
- * Values:
- * - 0 - No error detected
- * - 1 - DES key parity error detected
- */
-//@{
-#define BP_CAU_ADR_CASR_DPE (1U) //!< Bit position for CAU_ADR_CASR_DPE.
-#define BM_CAU_ADR_CASR_DPE (0x00000002U) //!< Bit mask for CAU_ADR_CASR_DPE.
-#define BS_CAU_ADR_CASR_DPE (1U) //!< Bit field size in bits for CAU_ADR_CASR_DPE.
-
-//! @brief Format value for bitfield CAU_ADR_CASR_DPE.
-#define BF_CAU_ADR_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ADR_CASR_DPE), uint32_t) & BM_CAU_ADR_CASR_DPE)
-//@}
-
-/*!
- * @name Register CAU_ADR_CASR, field VER[31:28] (WO)
- *
- * Values:
- * - 0001 - Initial CAU version
- * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
- * value on this device)
- */
-//@{
-#define BP_CAU_ADR_CASR_VER (28U) //!< Bit position for CAU_ADR_CASR_VER.
-#define BM_CAU_ADR_CASR_VER (0xF0000000U) //!< Bit mask for CAU_ADR_CASR_VER.
-#define BS_CAU_ADR_CASR_VER (4U) //!< Bit field size in bits for CAU_ADR_CASR_VER.
-
-//! @brief Format value for bitfield CAU_ADR_CASR_VER.
-#define BF_CAU_ADR_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ADR_CASR_VER), uint32_t) & BM_CAU_ADR_CASR_VER)
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CAU_ADR_CAA - Accumulator register - Add to register command
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAU_ADR_CAA - Accumulator register - Add to register command (WO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_cau_adr_caa
-{
- uint32_t U;
- struct _hw_cau_adr_caa_bitfields
- {
- uint32_t RESERVED0 : 32; //!< [31:0]
- } B;
-} hw_cau_adr_caa_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAU_ADR_CAA register
- */
-//@{
-#define HW_CAU_ADR_CAA_ADDR (REGS_CAU_BASE + 0x8C4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAU_ADR_CAA (*(__O hw_cau_adr_caa_t *) HW_CAU_ADR_CAA_ADDR)
-#define HW_CAU_ADR_CAA_WR(v) (HW_CAU_ADR_CAA.U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAU_ADR_CAA bitfields
- */
-
-//-------------------------------------------------------------------------------------------
-// HW_CAU_ADR_CA - General Purpose Register 0 - Add to register command
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAU_ADR_CA - General Purpose Register 0 - Add to register command (WO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_cau_adr_ca
-{
- uint32_t U;
- struct _hw_cau_adr_ca_bitfields
- {
- uint32_t RESERVED0 : 32; //!< [31:0]
- } B;
-} hw_cau_adr_ca_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAU_ADR_CA register
- */
-//@{
-#define HW_CAU_ADR_CA_COUNT (9U)
-
-#define HW_CAU_ADR_CA_ADDR(n) (REGS_CAU_BASE + 0x8C8U + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAU_ADR_CA(n) (*(__O hw_cau_adr_ca_t *) HW_CAU_ADR_CA_ADDR(n))
-#define HW_CAU_ADR_CA_WR(n, v) (HW_CAU_ADR_CA(n).U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAU_ADR_CA bitfields
- */
-
-//-------------------------------------------------------------------------------------------
-// HW_CAU_RADR_CASR - Status register - Reverse and Add to Register command
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAU_RADR_CASR - Status register - Reverse and Add to Register command (WO)
- *
- * Reset value: 0x20000000U
- */
-typedef union _hw_cau_radr_casr
-{
- uint32_t U;
- struct _hw_cau_radr_casr_bitfields
- {
- uint32_t IC : 1; //!< [0]
- uint32_t DPE : 1; //!< [1]
- uint32_t RESERVED0 : 26; //!< [27:2]
- uint32_t VER : 4; //!< [31:28] CAU version
- } B;
-} hw_cau_radr_casr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAU_RADR_CASR register
- */
-//@{
-#define HW_CAU_RADR_CASR_ADDR (REGS_CAU_BASE + 0x900U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAU_RADR_CASR (*(__O hw_cau_radr_casr_t *) HW_CAU_RADR_CASR_ADDR)
-#define HW_CAU_RADR_CASR_WR(v) (HW_CAU_RADR_CASR.U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAU_RADR_CASR bitfields
- */
-
-/*!
- * @name Register CAU_RADR_CASR, field IC[0] (WO)
- *
- * Values:
- * - 0 - No illegal commands issued
- * - 1 - Illegal command issued
- */
-//@{
-#define BP_CAU_RADR_CASR_IC (0U) //!< Bit position for CAU_RADR_CASR_IC.
-#define BM_CAU_RADR_CASR_IC (0x00000001U) //!< Bit mask for CAU_RADR_CASR_IC.
-#define BS_CAU_RADR_CASR_IC (1U) //!< Bit field size in bits for CAU_RADR_CASR_IC.
-
-//! @brief Format value for bitfield CAU_RADR_CASR_IC.
-#define BF_CAU_RADR_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_RADR_CASR_IC), uint32_t) & BM_CAU_RADR_CASR_IC)
-//@}
-
-/*!
- * @name Register CAU_RADR_CASR, field DPE[1] (WO)
- *
- * Values:
- * - 0 - No error detected
- * - 1 - DES key parity error detected
- */
-//@{
-#define BP_CAU_RADR_CASR_DPE (1U) //!< Bit position for CAU_RADR_CASR_DPE.
-#define BM_CAU_RADR_CASR_DPE (0x00000002U) //!< Bit mask for CAU_RADR_CASR_DPE.
-#define BS_CAU_RADR_CASR_DPE (1U) //!< Bit field size in bits for CAU_RADR_CASR_DPE.
-
-//! @brief Format value for bitfield CAU_RADR_CASR_DPE.
-#define BF_CAU_RADR_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_RADR_CASR_DPE), uint32_t) & BM_CAU_RADR_CASR_DPE)
-//@}
-
-/*!
- * @name Register CAU_RADR_CASR, field VER[31:28] (WO)
- *
- * Values:
- * - 0001 - Initial CAU version
- * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
- * value on this device)
- */
-//@{
-#define BP_CAU_RADR_CASR_VER (28U) //!< Bit position for CAU_RADR_CASR_VER.
-#define BM_CAU_RADR_CASR_VER (0xF0000000U) //!< Bit mask for CAU_RADR_CASR_VER.
-#define BS_CAU_RADR_CASR_VER (4U) //!< Bit field size in bits for CAU_RADR_CASR_VER.
-
-//! @brief Format value for bitfield CAU_RADR_CASR_VER.
-#define BF_CAU_RADR_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_RADR_CASR_VER), uint32_t) & BM_CAU_RADR_CASR_VER)
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command (WO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_cau_radr_caa
-{
- uint32_t U;
- struct _hw_cau_radr_caa_bitfields
- {
- uint32_t RESERVED0 : 32; //!< [31:0]
- } B;
-} hw_cau_radr_caa_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAU_RADR_CAA register
- */
-//@{
-#define HW_CAU_RADR_CAA_ADDR (REGS_CAU_BASE + 0x904U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAU_RADR_CAA (*(__O hw_cau_radr_caa_t *) HW_CAU_RADR_CAA_ADDR)
-#define HW_CAU_RADR_CAA_WR(v) (HW_CAU_RADR_CAA.U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAU_RADR_CAA bitfields
- */
-
-//-------------------------------------------------------------------------------------------
-// HW_CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command (WO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_cau_radr_ca
-{
- uint32_t U;
- struct _hw_cau_radr_ca_bitfields
- {
- uint32_t RESERVED0 : 32; //!< [31:0]
- } B;
-} hw_cau_radr_ca_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAU_RADR_CA register
- */
-//@{
-#define HW_CAU_RADR_CA_COUNT (9U)
-
-#define HW_CAU_RADR_CA_ADDR(n) (REGS_CAU_BASE + 0x908U + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAU_RADR_CA(n) (*(__O hw_cau_radr_ca_t *) HW_CAU_RADR_CA_ADDR(n))
-#define HW_CAU_RADR_CA_WR(n, v) (HW_CAU_RADR_CA(n).U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAU_RADR_CA bitfields
- */
-
-//-------------------------------------------------------------------------------------------
-// HW_CAU_XOR_CASR - Status register - Exclusive Or command
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAU_XOR_CASR - Status register - Exclusive Or command (WO)
- *
- * Reset value: 0x20000000U
- */
-typedef union _hw_cau_xor_casr
-{
- uint32_t U;
- struct _hw_cau_xor_casr_bitfields
- {
- uint32_t IC : 1; //!< [0]
- uint32_t DPE : 1; //!< [1]
- uint32_t RESERVED0 : 26; //!< [27:2]
- uint32_t VER : 4; //!< [31:28] CAU version
- } B;
-} hw_cau_xor_casr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAU_XOR_CASR register
- */
-//@{
-#define HW_CAU_XOR_CASR_ADDR (REGS_CAU_BASE + 0x980U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAU_XOR_CASR (*(__O hw_cau_xor_casr_t *) HW_CAU_XOR_CASR_ADDR)
-#define HW_CAU_XOR_CASR_WR(v) (HW_CAU_XOR_CASR.U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAU_XOR_CASR bitfields
- */
-
-/*!
- * @name Register CAU_XOR_CASR, field IC[0] (WO)
- *
- * Values:
- * - 0 - No illegal commands issued
- * - 1 - Illegal command issued
- */
-//@{
-#define BP_CAU_XOR_CASR_IC (0U) //!< Bit position for CAU_XOR_CASR_IC.
-#define BM_CAU_XOR_CASR_IC (0x00000001U) //!< Bit mask for CAU_XOR_CASR_IC.
-#define BS_CAU_XOR_CASR_IC (1U) //!< Bit field size in bits for CAU_XOR_CASR_IC.
-
-//! @brief Format value for bitfield CAU_XOR_CASR_IC.
-#define BF_CAU_XOR_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_XOR_CASR_IC), uint32_t) & BM_CAU_XOR_CASR_IC)
-//@}
-
-/*!
- * @name Register CAU_XOR_CASR, field DPE[1] (WO)
- *
- * Values:
- * - 0 - No error detected
- * - 1 - DES key parity error detected
- */
-//@{
-#define BP_CAU_XOR_CASR_DPE (1U) //!< Bit position for CAU_XOR_CASR_DPE.
-#define BM_CAU_XOR_CASR_DPE (0x00000002U) //!< Bit mask for CAU_XOR_CASR_DPE.
-#define BS_CAU_XOR_CASR_DPE (1U) //!< Bit field size in bits for CAU_XOR_CASR_DPE.
-
-//! @brief Format value for bitfield CAU_XOR_CASR_DPE.
-#define BF_CAU_XOR_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_XOR_CASR_DPE), uint32_t) & BM_CAU_XOR_CASR_DPE)
-//@}
-
-/*!
- * @name Register CAU_XOR_CASR, field VER[31:28] (WO)
- *
- * Values:
- * - 0001 - Initial CAU version
- * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
- * value on this device)
- */
-//@{
-#define BP_CAU_XOR_CASR_VER (28U) //!< Bit position for CAU_XOR_CASR_VER.
-#define BM_CAU_XOR_CASR_VER (0xF0000000U) //!< Bit mask for CAU_XOR_CASR_VER.
-#define BS_CAU_XOR_CASR_VER (4U) //!< Bit field size in bits for CAU_XOR_CASR_VER.
-
-//! @brief Format value for bitfield CAU_XOR_CASR_VER.
-#define BF_CAU_XOR_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_XOR_CASR_VER), uint32_t) & BM_CAU_XOR_CASR_VER)
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CAU_XOR_CAA - Accumulator register - Exclusive Or command
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAU_XOR_CAA - Accumulator register - Exclusive Or command (WO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_cau_xor_caa
-{
- uint32_t U;
- struct _hw_cau_xor_caa_bitfields
- {
- uint32_t RESERVED0 : 32; //!< [31:0]
- } B;
-} hw_cau_xor_caa_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAU_XOR_CAA register
- */
-//@{
-#define HW_CAU_XOR_CAA_ADDR (REGS_CAU_BASE + 0x984U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAU_XOR_CAA (*(__O hw_cau_xor_caa_t *) HW_CAU_XOR_CAA_ADDR)
-#define HW_CAU_XOR_CAA_WR(v) (HW_CAU_XOR_CAA.U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAU_XOR_CAA bitfields
- */
-
-//-------------------------------------------------------------------------------------------
-// HW_CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command (WO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_cau_xor_ca
-{
- uint32_t U;
- struct _hw_cau_xor_ca_bitfields
- {
- uint32_t RESERVED0 : 32; //!< [31:0]
- } B;
-} hw_cau_xor_ca_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAU_XOR_CA register
- */
-//@{
-#define HW_CAU_XOR_CA_COUNT (9U)
-
-#define HW_CAU_XOR_CA_ADDR(n) (REGS_CAU_BASE + 0x988U + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAU_XOR_CA(n) (*(__O hw_cau_xor_ca_t *) HW_CAU_XOR_CA_ADDR(n))
-#define HW_CAU_XOR_CA_WR(n, v) (HW_CAU_XOR_CA(n).U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAU_XOR_CA bitfields
- */
-
-//-------------------------------------------------------------------------------------------
-// HW_CAU_ROTL_CASR - Status register - Rotate Left command
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAU_ROTL_CASR - Status register - Rotate Left command (WO)
- *
- * Reset value: 0x20000000U
- */
-typedef union _hw_cau_rotl_casr
-{
- uint32_t U;
- struct _hw_cau_rotl_casr_bitfields
- {
- uint32_t IC : 1; //!< [0]
- uint32_t DPE : 1; //!< [1]
- uint32_t RESERVED0 : 26; //!< [27:2]
- uint32_t VER : 4; //!< [31:28] CAU version
- } B;
-} hw_cau_rotl_casr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAU_ROTL_CASR register
- */
-//@{
-#define HW_CAU_ROTL_CASR_ADDR (REGS_CAU_BASE + 0x9C0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAU_ROTL_CASR (*(__O hw_cau_rotl_casr_t *) HW_CAU_ROTL_CASR_ADDR)
-#define HW_CAU_ROTL_CASR_WR(v) (HW_CAU_ROTL_CASR.U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAU_ROTL_CASR bitfields
- */
-
-/*!
- * @name Register CAU_ROTL_CASR, field IC[0] (WO)
- *
- * Values:
- * - 0 - No illegal commands issued
- * - 1 - Illegal command issued
- */
-//@{
-#define BP_CAU_ROTL_CASR_IC (0U) //!< Bit position for CAU_ROTL_CASR_IC.
-#define BM_CAU_ROTL_CASR_IC (0x00000001U) //!< Bit mask for CAU_ROTL_CASR_IC.
-#define BS_CAU_ROTL_CASR_IC (1U) //!< Bit field size in bits for CAU_ROTL_CASR_IC.
-
-//! @brief Format value for bitfield CAU_ROTL_CASR_IC.
-#define BF_CAU_ROTL_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ROTL_CASR_IC), uint32_t) & BM_CAU_ROTL_CASR_IC)
-//@}
-
-/*!
- * @name Register CAU_ROTL_CASR, field DPE[1] (WO)
- *
- * Values:
- * - 0 - No error detected
- * - 1 - DES key parity error detected
- */
-//@{
-#define BP_CAU_ROTL_CASR_DPE (1U) //!< Bit position for CAU_ROTL_CASR_DPE.
-#define BM_CAU_ROTL_CASR_DPE (0x00000002U) //!< Bit mask for CAU_ROTL_CASR_DPE.
-#define BS_CAU_ROTL_CASR_DPE (1U) //!< Bit field size in bits for CAU_ROTL_CASR_DPE.
-
-//! @brief Format value for bitfield CAU_ROTL_CASR_DPE.
-#define BF_CAU_ROTL_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ROTL_CASR_DPE), uint32_t) & BM_CAU_ROTL_CASR_DPE)
-//@}
-
-/*!
- * @name Register CAU_ROTL_CASR, field VER[31:28] (WO)
- *
- * Values:
- * - 0001 - Initial CAU version
- * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
- * value on this device)
- */
-//@{
-#define BP_CAU_ROTL_CASR_VER (28U) //!< Bit position for CAU_ROTL_CASR_VER.
-#define BM_CAU_ROTL_CASR_VER (0xF0000000U) //!< Bit mask for CAU_ROTL_CASR_VER.
-#define BS_CAU_ROTL_CASR_VER (4U) //!< Bit field size in bits for CAU_ROTL_CASR_VER.
-
-//! @brief Format value for bitfield CAU_ROTL_CASR_VER.
-#define BF_CAU_ROTL_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ROTL_CASR_VER), uint32_t) & BM_CAU_ROTL_CASR_VER)
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CAU_ROTL_CAA - Accumulator register - Rotate Left command
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAU_ROTL_CAA - Accumulator register - Rotate Left command (WO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_cau_rotl_caa
-{
- uint32_t U;
- struct _hw_cau_rotl_caa_bitfields
- {
- uint32_t RESERVED0 : 32; //!< [31:0]
- } B;
-} hw_cau_rotl_caa_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAU_ROTL_CAA register
- */
-//@{
-#define HW_CAU_ROTL_CAA_ADDR (REGS_CAU_BASE + 0x9C4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAU_ROTL_CAA (*(__O hw_cau_rotl_caa_t *) HW_CAU_ROTL_CAA_ADDR)
-#define HW_CAU_ROTL_CAA_WR(v) (HW_CAU_ROTL_CAA.U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAU_ROTL_CAA bitfields
- */
-
-//-------------------------------------------------------------------------------------------
-// HW_CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command (WO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_cau_rotl_ca
-{
- uint32_t U;
- struct _hw_cau_rotl_ca_bitfields
- {
- uint32_t RESERVED0 : 32; //!< [31:0]
- } B;
-} hw_cau_rotl_ca_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAU_ROTL_CA register
- */
-//@{
-#define HW_CAU_ROTL_CA_COUNT (9U)
-
-#define HW_CAU_ROTL_CA_ADDR(n) (REGS_CAU_BASE + 0x9C8U + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAU_ROTL_CA(n) (*(__O hw_cau_rotl_ca_t *) HW_CAU_ROTL_CA_ADDR(n))
-#define HW_CAU_ROTL_CA_WR(n, v) (HW_CAU_ROTL_CA(n).U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAU_ROTL_CA bitfields
- */
-
-//-------------------------------------------------------------------------------------------
-// HW_CAU_AESC_CASR - Status register - AES Column Operation command
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAU_AESC_CASR - Status register - AES Column Operation command (WO)
- *
- * Reset value: 0x20000000U
- */
-typedef union _hw_cau_aesc_casr
-{
- uint32_t U;
- struct _hw_cau_aesc_casr_bitfields
- {
- uint32_t IC : 1; //!< [0]
- uint32_t DPE : 1; //!< [1]
- uint32_t RESERVED0 : 26; //!< [27:2]
- uint32_t VER : 4; //!< [31:28] CAU version
- } B;
-} hw_cau_aesc_casr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAU_AESC_CASR register
- */
-//@{
-#define HW_CAU_AESC_CASR_ADDR (REGS_CAU_BASE + 0xB00U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAU_AESC_CASR (*(__O hw_cau_aesc_casr_t *) HW_CAU_AESC_CASR_ADDR)
-#define HW_CAU_AESC_CASR_WR(v) (HW_CAU_AESC_CASR.U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAU_AESC_CASR bitfields
- */
-
-/*!
- * @name Register CAU_AESC_CASR, field IC[0] (WO)
- *
- * Values:
- * - 0 - No illegal commands issued
- * - 1 - Illegal command issued
- */
-//@{
-#define BP_CAU_AESC_CASR_IC (0U) //!< Bit position for CAU_AESC_CASR_IC.
-#define BM_CAU_AESC_CASR_IC (0x00000001U) //!< Bit mask for CAU_AESC_CASR_IC.
-#define BS_CAU_AESC_CASR_IC (1U) //!< Bit field size in bits for CAU_AESC_CASR_IC.
-
-//! @brief Format value for bitfield CAU_AESC_CASR_IC.
-#define BF_CAU_AESC_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESC_CASR_IC), uint32_t) & BM_CAU_AESC_CASR_IC)
-//@}
-
-/*!
- * @name Register CAU_AESC_CASR, field DPE[1] (WO)
- *
- * Values:
- * - 0 - No error detected
- * - 1 - DES key parity error detected
- */
-//@{
-#define BP_CAU_AESC_CASR_DPE (1U) //!< Bit position for CAU_AESC_CASR_DPE.
-#define BM_CAU_AESC_CASR_DPE (0x00000002U) //!< Bit mask for CAU_AESC_CASR_DPE.
-#define BS_CAU_AESC_CASR_DPE (1U) //!< Bit field size in bits for CAU_AESC_CASR_DPE.
-
-//! @brief Format value for bitfield CAU_AESC_CASR_DPE.
-#define BF_CAU_AESC_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESC_CASR_DPE), uint32_t) & BM_CAU_AESC_CASR_DPE)
-//@}
-
-/*!
- * @name Register CAU_AESC_CASR, field VER[31:28] (WO)
- *
- * Values:
- * - 0001 - Initial CAU version
- * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
- * value on this device)
- */
-//@{
-#define BP_CAU_AESC_CASR_VER (28U) //!< Bit position for CAU_AESC_CASR_VER.
-#define BM_CAU_AESC_CASR_VER (0xF0000000U) //!< Bit mask for CAU_AESC_CASR_VER.
-#define BS_CAU_AESC_CASR_VER (4U) //!< Bit field size in bits for CAU_AESC_CASR_VER.
-
-//! @brief Format value for bitfield CAU_AESC_CASR_VER.
-#define BF_CAU_AESC_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESC_CASR_VER), uint32_t) & BM_CAU_AESC_CASR_VER)
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CAU_AESC_CAA - Accumulator register - AES Column Operation command
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAU_AESC_CAA - Accumulator register - AES Column Operation command (WO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_cau_aesc_caa
-{
- uint32_t U;
- struct _hw_cau_aesc_caa_bitfields
- {
- uint32_t RESERVED0 : 32; //!< [31:0]
- } B;
-} hw_cau_aesc_caa_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAU_AESC_CAA register
- */
-//@{
-#define HW_CAU_AESC_CAA_ADDR (REGS_CAU_BASE + 0xB04U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAU_AESC_CAA (*(__O hw_cau_aesc_caa_t *) HW_CAU_AESC_CAA_ADDR)
-#define HW_CAU_AESC_CAA_WR(v) (HW_CAU_AESC_CAA.U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAU_AESC_CAA bitfields
- */
-
-//-------------------------------------------------------------------------------------------
-// HW_CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command (WO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_cau_aesc_ca
-{
- uint32_t U;
- struct _hw_cau_aesc_ca_bitfields
- {
- uint32_t RESERVED0 : 32; //!< [31:0]
- } B;
-} hw_cau_aesc_ca_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAU_AESC_CA register
- */
-//@{
-#define HW_CAU_AESC_CA_COUNT (9U)
-
-#define HW_CAU_AESC_CA_ADDR(n) (REGS_CAU_BASE + 0xB08U + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAU_AESC_CA(n) (*(__O hw_cau_aesc_ca_t *) HW_CAU_AESC_CA_ADDR(n))
-#define HW_CAU_AESC_CA_WR(n, v) (HW_CAU_AESC_CA(n).U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAU_AESC_CA bitfields
- */
-
-//-------------------------------------------------------------------------------------------
-// HW_CAU_AESIC_CASR - Status register - AES Inverse Column Operation command
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAU_AESIC_CASR - Status register - AES Inverse Column Operation command (WO)
- *
- * Reset value: 0x20000000U
- */
-typedef union _hw_cau_aesic_casr
-{
- uint32_t U;
- struct _hw_cau_aesic_casr_bitfields
- {
- uint32_t IC : 1; //!< [0]
- uint32_t DPE : 1; //!< [1]
- uint32_t RESERVED0 : 26; //!< [27:2]
- uint32_t VER : 4; //!< [31:28] CAU version
- } B;
-} hw_cau_aesic_casr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAU_AESIC_CASR register
- */
-//@{
-#define HW_CAU_AESIC_CASR_ADDR (REGS_CAU_BASE + 0xB40U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAU_AESIC_CASR (*(__O hw_cau_aesic_casr_t *) HW_CAU_AESIC_CASR_ADDR)
-#define HW_CAU_AESIC_CASR_WR(v) (HW_CAU_AESIC_CASR.U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAU_AESIC_CASR bitfields
- */
-
-/*!
- * @name Register CAU_AESIC_CASR, field IC[0] (WO)
- *
- * Values:
- * - 0 - No illegal commands issued
- * - 1 - Illegal command issued
- */
-//@{
-#define BP_CAU_AESIC_CASR_IC (0U) //!< Bit position for CAU_AESIC_CASR_IC.
-#define BM_CAU_AESIC_CASR_IC (0x00000001U) //!< Bit mask for CAU_AESIC_CASR_IC.
-#define BS_CAU_AESIC_CASR_IC (1U) //!< Bit field size in bits for CAU_AESIC_CASR_IC.
-
-//! @brief Format value for bitfield CAU_AESIC_CASR_IC.
-#define BF_CAU_AESIC_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESIC_CASR_IC), uint32_t) & BM_CAU_AESIC_CASR_IC)
-//@}
-
-/*!
- * @name Register CAU_AESIC_CASR, field DPE[1] (WO)
- *
- * Values:
- * - 0 - No error detected
- * - 1 - DES key parity error detected
- */
-//@{
-#define BP_CAU_AESIC_CASR_DPE (1U) //!< Bit position for CAU_AESIC_CASR_DPE.
-#define BM_CAU_AESIC_CASR_DPE (0x00000002U) //!< Bit mask for CAU_AESIC_CASR_DPE.
-#define BS_CAU_AESIC_CASR_DPE (1U) //!< Bit field size in bits for CAU_AESIC_CASR_DPE.
-
-//! @brief Format value for bitfield CAU_AESIC_CASR_DPE.
-#define BF_CAU_AESIC_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESIC_CASR_DPE), uint32_t) & BM_CAU_AESIC_CASR_DPE)
-//@}
-
-/*!
- * @name Register CAU_AESIC_CASR, field VER[31:28] (WO)
- *
- * Values:
- * - 0001 - Initial CAU version
- * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
- * value on this device)
- */
-//@{
-#define BP_CAU_AESIC_CASR_VER (28U) //!< Bit position for CAU_AESIC_CASR_VER.
-#define BM_CAU_AESIC_CASR_VER (0xF0000000U) //!< Bit mask for CAU_AESIC_CASR_VER.
-#define BS_CAU_AESIC_CASR_VER (4U) //!< Bit field size in bits for CAU_AESIC_CASR_VER.
-
-//! @brief Format value for bitfield CAU_AESIC_CASR_VER.
-#define BF_CAU_AESIC_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESIC_CASR_VER), uint32_t) & BM_CAU_AESIC_CASR_VER)
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command (WO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_cau_aesic_caa
-{
- uint32_t U;
- struct _hw_cau_aesic_caa_bitfields
- {
- uint32_t RESERVED0 : 32; //!< [31:0]
- } B;
-} hw_cau_aesic_caa_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAU_AESIC_CAA register
- */
-//@{
-#define HW_CAU_AESIC_CAA_ADDR (REGS_CAU_BASE + 0xB44U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAU_AESIC_CAA (*(__O hw_cau_aesic_caa_t *) HW_CAU_AESIC_CAA_ADDR)
-#define HW_CAU_AESIC_CAA_WR(v) (HW_CAU_AESIC_CAA.U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAU_AESIC_CAA bitfields
- */
-
-//-------------------------------------------------------------------------------------------
-// HW_CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command (WO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_cau_aesic_ca
-{
- uint32_t U;
- struct _hw_cau_aesic_ca_bitfields
- {
- uint32_t RESERVED0 : 32; //!< [31:0]
- } B;
-} hw_cau_aesic_ca_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CAU_AESIC_CA register
- */
-//@{
-#define HW_CAU_AESIC_CA_COUNT (9U)
-
-#define HW_CAU_AESIC_CA_ADDR(n) (REGS_CAU_BASE + 0xB48U + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CAU_AESIC_CA(n) (*(__O hw_cau_aesic_ca_t *) HW_CAU_AESIC_CA_ADDR(n))
-#define HW_CAU_AESIC_CA_WR(n, v) (HW_CAU_AESIC_CA(n).U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CAU_AESIC_CA bitfields
- */
-
-//-------------------------------------------------------------------------------------------
-// hw_cau_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All CAU module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_cau
-{
- __O hw_cau_direct_t DIRECT[16]; //!< [0x0] Direct access register 0
- uint8_t _reserved0[2048];
- __O hw_cau_ldr_casr_t LDR_CASR; //!< [0x840] Status register - Load Register command
- __O hw_cau_ldr_caa_t LDR_CAA; //!< [0x844] Accumulator register - Load Register command
- __O hw_cau_ldr_ca_t LDR_CA[9]; //!< [0x848] General Purpose Register 0 - Load Register command
- uint8_t _reserved1[20];
- __I hw_cau_str_casr_t STR_CASR; //!< [0x880] Status register - Store Register command
- __I hw_cau_str_caa_t STR_CAA; //!< [0x884] Accumulator register - Store Register command
- __I hw_cau_str_ca_t STR_CA[9]; //!< [0x888] General Purpose Register 0 - Store Register command
- uint8_t _reserved2[20];
- __O hw_cau_adr_casr_t ADR_CASR; //!< [0x8C0] Status register - Add Register command
- __O hw_cau_adr_caa_t ADR_CAA; //!< [0x8C4] Accumulator register - Add to register command
- __O hw_cau_adr_ca_t ADR_CA[9]; //!< [0x8C8] General Purpose Register 0 - Add to register command
- uint8_t _reserved3[20];
- __O hw_cau_radr_casr_t RADR_CASR; //!< [0x900] Status register - Reverse and Add to Register command
- __O hw_cau_radr_caa_t RADR_CAA; //!< [0x904] Accumulator register - Reverse and Add to Register command
- __O hw_cau_radr_ca_t RADR_CA[9]; //!< [0x908] General Purpose Register 0 - Reverse and Add to Register command
- uint8_t _reserved4[84];
- __O hw_cau_xor_casr_t XOR_CASR; //!< [0x980] Status register - Exclusive Or command
- __O hw_cau_xor_caa_t XOR_CAA; //!< [0x984] Accumulator register - Exclusive Or command
- __O hw_cau_xor_ca_t XOR_CA[9]; //!< [0x988] General Purpose Register 0 - Exclusive Or command
- uint8_t _reserved5[20];
- __O hw_cau_rotl_casr_t ROTL_CASR; //!< [0x9C0] Status register - Rotate Left command
- __O hw_cau_rotl_caa_t ROTL_CAA; //!< [0x9C4] Accumulator register - Rotate Left command
- __O hw_cau_rotl_ca_t ROTL_CA[9]; //!< [0x9C8] General Purpose Register 0 - Rotate Left command
- uint8_t _reserved6[276];
- __O hw_cau_aesc_casr_t AESC_CASR; //!< [0xB00] Status register - AES Column Operation command
- __O hw_cau_aesc_caa_t AESC_CAA; //!< [0xB04] Accumulator register - AES Column Operation command
- __O hw_cau_aesc_ca_t AESC_CA[9]; //!< [0xB08] General Purpose Register 0 - AES Column Operation command
- uint8_t _reserved7[20];
- __O hw_cau_aesic_casr_t AESIC_CASR; //!< [0xB40] Status register - AES Inverse Column Operation command
- __O hw_cau_aesic_caa_t AESIC_CAA; //!< [0xB44] Accumulator register - AES Inverse Column Operation command
- __O hw_cau_aesic_ca_t AESIC_CA[9]; //!< [0xB48] General Purpose Register 0 - AES Inverse Column Operation command
-} hw_cau_t;
-#pragma pack()
-
-//! @brief Macro to access all CAU registers.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_CAU</code>.
-#define HW_CAU (*(hw_cau_t *) REGS_CAU_BASE)
-#endif
-
-#endif // __HW_CAU_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_cmp.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1018 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_CMP_REGISTERS_H__
-#define __HW_CMP_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 CMP
- *
- * High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
- *
- * Registers defined in this header file:
- * - HW_CMP_CR0 - CMP Control Register 0
- * - HW_CMP_CR1 - CMP Control Register 1
- * - HW_CMP_FPR - CMP Filter Period Register
- * - HW_CMP_SCR - CMP Status and Control Register
- * - HW_CMP_DACCR - DAC Control Register
- * - HW_CMP_MUXCR - MUX Control Register
- *
- * - hw_cmp_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_CMP_BASE
-#define HW_CMP_INSTANCE_COUNT (3U) //!< Number of instances of the CMP module.
-#define HW_CMP0 (0U) //!< Instance number for CMP0.
-#define HW_CMP1 (1U) //!< Instance number for CMP1.
-#define HW_CMP2 (2U) //!< Instance number for CMP2.
-#define REGS_CMP0_BASE (0x40073000U) //!< Base address for CMP0.
-#define REGS_CMP1_BASE (0x40073008U) //!< Base address for CMP1.
-#define REGS_CMP2_BASE (0x40073010U) //!< Base address for CMP2.
-
-//! @brief Table of base addresses for CMP instances.
-static const uint32_t __g_regs_CMP_base_addresses[] = {
- REGS_CMP0_BASE,
- REGS_CMP1_BASE,
- REGS_CMP2_BASE,
- };
-
-//! @brief Get the base address of CMP by instance number.
-//! @param x CMP instance number, from 0 through 2.
-#define REGS_CMP_BASE(x) (__g_regs_CMP_base_addresses[(x)])
-
-//! @brief Get the instance number given a base address.
-//! @param b Base address for an instance of CMP.
-#define REGS_CMP_INSTANCE(b) ((b) == REGS_CMP0_BASE ? HW_CMP0 : (b) == REGS_CMP1_BASE ? HW_CMP1 : (b) == REGS_CMP2_BASE ? HW_CMP2 : 0)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CMP_CR0 - CMP Control Register 0
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CMP_CR0 - CMP Control Register 0 (RW)
- *
- * Reset value: 0x00U
- */
-typedef union _hw_cmp_cr0
-{
- uint8_t U;
- struct _hw_cmp_cr0_bitfields
- {
- uint8_t HYSTCTR : 2; //!< [1:0] Comparator hard block hysteresis
- //! control
- uint8_t RESERVED0 : 2; //!< [3:2]
- uint8_t FILTER_CNT : 3; //!< [6:4] Filter Sample Count
- uint8_t RESERVED1 : 1; //!< [7]
- } B;
-} hw_cmp_cr0_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CMP_CR0 register
- */
-//@{
-#define HW_CMP_CR0_ADDR(x) (REGS_CMP_BASE(x) + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CMP_CR0(x) (*(__IO hw_cmp_cr0_t *) HW_CMP_CR0_ADDR(x))
-#define HW_CMP_CR0_RD(x) (HW_CMP_CR0(x).U)
-#define HW_CMP_CR0_WR(x, v) (HW_CMP_CR0(x).U = (v))
-#define HW_CMP_CR0_SET(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) | (v)))
-#define HW_CMP_CR0_CLR(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) & ~(v)))
-#define HW_CMP_CR0_TOG(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CMP_CR0 bitfields
- */
-
-/*!
- * @name Register CMP_CR0, field HYSTCTR[1:0] (RW)
- *
- * Defines the programmable hysteresis level. The hysteresis values associated
- * with each level are device-specific. See the Data Sheet of the device for the
- * exact values.
- *
- * Values:
- * - 00 - Level 0
- * - 01 - Level 1
- * - 10 - Level 2
- * - 11 - Level 3
- */
-//@{
-#define BP_CMP_CR0_HYSTCTR (0U) //!< Bit position for CMP_CR0_HYSTCTR.
-#define BM_CMP_CR0_HYSTCTR (0x03U) //!< Bit mask for CMP_CR0_HYSTCTR.
-#define BS_CMP_CR0_HYSTCTR (2U) //!< Bit field size in bits for CMP_CR0_HYSTCTR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMP_CR0_HYSTCTR field.
-#define BR_CMP_CR0_HYSTCTR(x) (HW_CMP_CR0(x).B.HYSTCTR)
-#endif
-
-//! @brief Format value for bitfield CMP_CR0_HYSTCTR.
-#define BF_CMP_CR0_HYSTCTR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR0_HYSTCTR), uint8_t) & BM_CMP_CR0_HYSTCTR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the HYSTCTR field to a new value.
-#define BW_CMP_CR0_HYSTCTR(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_HYSTCTR) | BF_CMP_CR0_HYSTCTR(v)))
-#endif
-//@}
-
-/*!
- * @name Register CMP_CR0, field FILTER_CNT[6:4] (RW)
- *
- * Represents the number of consecutive samples that must agree prior to the
- * comparator ouput filter accepting a new output state. For information regarding
- * filter programming and latency, see the Functional descriptionThe CMP module
- * can be used to compare two analog input voltages applied to INP and INM. .
- *
- * Values:
- * - 000 - Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a
- * legal state, and is not recommended. If SE = 0, COUT = COUTA.
- * - 001 - One sample must agree. The comparator output is simply sampled.
- * - 010 - 2 consecutive samples must agree.
- * - 011 - 3 consecutive samples must agree.
- * - 100 - 4 consecutive samples must agree.
- * - 101 - 5 consecutive samples must agree.
- * - 110 - 6 consecutive samples must agree.
- * - 111 - 7 consecutive samples must agree.
- */
-//@{
-#define BP_CMP_CR0_FILTER_CNT (4U) //!< Bit position for CMP_CR0_FILTER_CNT.
-#define BM_CMP_CR0_FILTER_CNT (0x70U) //!< Bit mask for CMP_CR0_FILTER_CNT.
-#define BS_CMP_CR0_FILTER_CNT (3U) //!< Bit field size in bits for CMP_CR0_FILTER_CNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMP_CR0_FILTER_CNT field.
-#define BR_CMP_CR0_FILTER_CNT(x) (HW_CMP_CR0(x).B.FILTER_CNT)
-#endif
-
-//! @brief Format value for bitfield CMP_CR0_FILTER_CNT.
-#define BF_CMP_CR0_FILTER_CNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR0_FILTER_CNT), uint8_t) & BM_CMP_CR0_FILTER_CNT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FILTER_CNT field to a new value.
-#define BW_CMP_CR0_FILTER_CNT(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_FILTER_CNT) | BF_CMP_CR0_FILTER_CNT(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CMP_CR1 - CMP Control Register 1
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CMP_CR1 - CMP Control Register 1 (RW)
- *
- * Reset value: 0x00U
- */
-typedef union _hw_cmp_cr1
-{
- uint8_t U;
- struct _hw_cmp_cr1_bitfields
- {
- uint8_t EN : 1; //!< [0] Comparator Module Enable
- uint8_t OPE : 1; //!< [1] Comparator Output Pin Enable
- uint8_t COS : 1; //!< [2] Comparator Output Select
- uint8_t INV : 1; //!< [3] Comparator INVERT
- uint8_t PMODE : 1; //!< [4] Power Mode Select
- uint8_t RESERVED0 : 1; //!< [5]
- uint8_t WE : 1; //!< [6] Windowing Enable
- uint8_t SE : 1; //!< [7] Sample Enable
- } B;
-} hw_cmp_cr1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CMP_CR1 register
- */
-//@{
-#define HW_CMP_CR1_ADDR(x) (REGS_CMP_BASE(x) + 0x1U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CMP_CR1(x) (*(__IO hw_cmp_cr1_t *) HW_CMP_CR1_ADDR(x))
-#define HW_CMP_CR1_RD(x) (HW_CMP_CR1(x).U)
-#define HW_CMP_CR1_WR(x, v) (HW_CMP_CR1(x).U = (v))
-#define HW_CMP_CR1_SET(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) | (v)))
-#define HW_CMP_CR1_CLR(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) & ~(v)))
-#define HW_CMP_CR1_TOG(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CMP_CR1 bitfields
- */
-
-/*!
- * @name Register CMP_CR1, field EN[0] (RW)
- *
- * Enables the Analog Comparator module. When the module is not enabled, it
- * remains in the off state, and consumes no power. When the user selects the same
- * input from analog mux to the positive and negative port, the comparator is
- * disabled automatically.
- *
- * Values:
- * - 0 - Analog Comparator is disabled.
- * - 1 - Analog Comparator is enabled.
- */
-//@{
-#define BP_CMP_CR1_EN (0U) //!< Bit position for CMP_CR1_EN.
-#define BM_CMP_CR1_EN (0x01U) //!< Bit mask for CMP_CR1_EN.
-#define BS_CMP_CR1_EN (1U) //!< Bit field size in bits for CMP_CR1_EN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMP_CR1_EN field.
-#define BR_CMP_CR1_EN(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN))
-#endif
-
-//! @brief Format value for bitfield CMP_CR1_EN.
-#define BF_CMP_CR1_EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_EN), uint8_t) & BM_CMP_CR1_EN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EN field to a new value.
-#define BW_CMP_CR1_EN(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CMP_CR1, field OPE[1] (RW)
- *
- * Values:
- * - 0 - CMPO is not available on the associated CMPO output pin. If the
- * comparator does not own the pin, this field has no effect.
- * - 1 - CMPO is available on the associated CMPO output pin. The comparator
- * output (CMPO) is driven out on the associated CMPO output pin if the
- * comparator owns the pin. If the comparator does not own the field, this bit has no
- * effect.
- */
-//@{
-#define BP_CMP_CR1_OPE (1U) //!< Bit position for CMP_CR1_OPE.
-#define BM_CMP_CR1_OPE (0x02U) //!< Bit mask for CMP_CR1_OPE.
-#define BS_CMP_CR1_OPE (1U) //!< Bit field size in bits for CMP_CR1_OPE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMP_CR1_OPE field.
-#define BR_CMP_CR1_OPE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE))
-#endif
-
-//! @brief Format value for bitfield CMP_CR1_OPE.
-#define BF_CMP_CR1_OPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_OPE), uint8_t) & BM_CMP_CR1_OPE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the OPE field to a new value.
-#define BW_CMP_CR1_OPE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CMP_CR1, field COS[2] (RW)
- *
- * Values:
- * - 0 - Set the filtered comparator output (CMPO) to equal COUT.
- * - 1 - Set the unfiltered comparator output (CMPO) to equal COUTA.
- */
-//@{
-#define BP_CMP_CR1_COS (2U) //!< Bit position for CMP_CR1_COS.
-#define BM_CMP_CR1_COS (0x04U) //!< Bit mask for CMP_CR1_COS.
-#define BS_CMP_CR1_COS (1U) //!< Bit field size in bits for CMP_CR1_COS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMP_CR1_COS field.
-#define BR_CMP_CR1_COS(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS))
-#endif
-
-//! @brief Format value for bitfield CMP_CR1_COS.
-#define BF_CMP_CR1_COS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_COS), uint8_t) & BM_CMP_CR1_COS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the COS field to a new value.
-#define BW_CMP_CR1_COS(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CMP_CR1, field INV[3] (RW)
- *
- * Allows selection of the polarity of the analog comparator function. It is
- * also driven to the COUT output, on both the device pin and as SCR[COUT], when
- * OPE=0.
- *
- * Values:
- * - 0 - Does not invert the comparator output.
- * - 1 - Inverts the comparator output.
- */
-//@{
-#define BP_CMP_CR1_INV (3U) //!< Bit position for CMP_CR1_INV.
-#define BM_CMP_CR1_INV (0x08U) //!< Bit mask for CMP_CR1_INV.
-#define BS_CMP_CR1_INV (1U) //!< Bit field size in bits for CMP_CR1_INV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMP_CR1_INV field.
-#define BR_CMP_CR1_INV(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV))
-#endif
-
-//! @brief Format value for bitfield CMP_CR1_INV.
-#define BF_CMP_CR1_INV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_INV), uint8_t) & BM_CMP_CR1_INV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INV field to a new value.
-#define BW_CMP_CR1_INV(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CMP_CR1, field PMODE[4] (RW)
- *
- * See the electrical specifications table in the device Data Sheet for details.
- *
- * Values:
- * - 0 - Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower
- * output propagation delay and lower current consumption.
- * - 1 - High-Speed (HS) Comparison mode selected. In this mode, CMP has faster
- * output propagation delay and higher current consumption.
- */
-//@{
-#define BP_CMP_CR1_PMODE (4U) //!< Bit position for CMP_CR1_PMODE.
-#define BM_CMP_CR1_PMODE (0x10U) //!< Bit mask for CMP_CR1_PMODE.
-#define BS_CMP_CR1_PMODE (1U) //!< Bit field size in bits for CMP_CR1_PMODE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMP_CR1_PMODE field.
-#define BR_CMP_CR1_PMODE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE))
-#endif
-
-//! @brief Format value for bitfield CMP_CR1_PMODE.
-#define BF_CMP_CR1_PMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_PMODE), uint8_t) & BM_CMP_CR1_PMODE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PMODE field to a new value.
-#define BW_CMP_CR1_PMODE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CMP_CR1, field WE[6] (RW)
- *
- * At any given time, either SE or WE can be set. If a write to this register
- * attempts to set both, then SE is set and WE is cleared. However, avoid writing
- * 1s to both field locations because this "11" case is reserved and may change in
- * future implementations.
- *
- * Values:
- * - 0 - Windowing mode is not selected.
- * - 1 - Windowing mode is selected.
- */
-//@{
-#define BP_CMP_CR1_WE (6U) //!< Bit position for CMP_CR1_WE.
-#define BM_CMP_CR1_WE (0x40U) //!< Bit mask for CMP_CR1_WE.
-#define BS_CMP_CR1_WE (1U) //!< Bit field size in bits for CMP_CR1_WE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMP_CR1_WE field.
-#define BR_CMP_CR1_WE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE))
-#endif
-
-//! @brief Format value for bitfield CMP_CR1_WE.
-#define BF_CMP_CR1_WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_WE), uint8_t) & BM_CMP_CR1_WE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WE field to a new value.
-#define BW_CMP_CR1_WE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CMP_CR1, field SE[7] (RW)
- *
- * At any given time, either SE or WE can be set. If a write to this register
- * attempts to set both, then SE is set and WE is cleared. However, avoid writing
- * 1s to both field locations because this "11" case is reserved and may change in
- * future implementations.
- *
- * Values:
- * - 0 - Sampling mode is not selected.
- * - 1 - Sampling mode is selected.
- */
-//@{
-#define BP_CMP_CR1_SE (7U) //!< Bit position for CMP_CR1_SE.
-#define BM_CMP_CR1_SE (0x80U) //!< Bit mask for CMP_CR1_SE.
-#define BS_CMP_CR1_SE (1U) //!< Bit field size in bits for CMP_CR1_SE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMP_CR1_SE field.
-#define BR_CMP_CR1_SE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE))
-#endif
-
-//! @brief Format value for bitfield CMP_CR1_SE.
-#define BF_CMP_CR1_SE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_SE), uint8_t) & BM_CMP_CR1_SE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SE field to a new value.
-#define BW_CMP_CR1_SE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CMP_FPR - CMP Filter Period Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CMP_FPR - CMP Filter Period Register (RW)
- *
- * Reset value: 0x00U
- */
-typedef union _hw_cmp_fpr
-{
- uint8_t U;
- struct _hw_cmp_fpr_bitfields
- {
- uint8_t FILT_PER : 8; //!< [7:0] Filter Sample Period
- } B;
-} hw_cmp_fpr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CMP_FPR register
- */
-//@{
-#define HW_CMP_FPR_ADDR(x) (REGS_CMP_BASE(x) + 0x2U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CMP_FPR(x) (*(__IO hw_cmp_fpr_t *) HW_CMP_FPR_ADDR(x))
-#define HW_CMP_FPR_RD(x) (HW_CMP_FPR(x).U)
-#define HW_CMP_FPR_WR(x, v) (HW_CMP_FPR(x).U = (v))
-#define HW_CMP_FPR_SET(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) | (v)))
-#define HW_CMP_FPR_CLR(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) & ~(v)))
-#define HW_CMP_FPR_TOG(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CMP_FPR bitfields
- */
-
-/*!
- * @name Register CMP_FPR, field FILT_PER[7:0] (RW)
- *
- * Specifies the sampling period, in bus clock cycles, of the comparator output
- * filter, when CR1[SE]=0. Setting FILT_PER to 0x0 disables the filter. Filter
- * programming and latency details appear in the Functional descriptionThe CMP
- * module can be used to compare two analog input voltages applied to INP and INM. .
- * This field has no effect when CR1[SE]=1. In that case, the external SAMPLE
- * signal is used to determine the sampling period.
- */
-//@{
-#define BP_CMP_FPR_FILT_PER (0U) //!< Bit position for CMP_FPR_FILT_PER.
-#define BM_CMP_FPR_FILT_PER (0xFFU) //!< Bit mask for CMP_FPR_FILT_PER.
-#define BS_CMP_FPR_FILT_PER (8U) //!< Bit field size in bits for CMP_FPR_FILT_PER.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMP_FPR_FILT_PER field.
-#define BR_CMP_FPR_FILT_PER(x) (HW_CMP_FPR(x).U)
-#endif
-
-//! @brief Format value for bitfield CMP_FPR_FILT_PER.
-#define BF_CMP_FPR_FILT_PER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_FPR_FILT_PER), uint8_t) & BM_CMP_FPR_FILT_PER)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FILT_PER field to a new value.
-#define BW_CMP_FPR_FILT_PER(x, v) (HW_CMP_FPR_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CMP_SCR - CMP Status and Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CMP_SCR - CMP Status and Control Register (RW)
- *
- * Reset value: 0x00U
- */
-typedef union _hw_cmp_scr
-{
- uint8_t U;
- struct _hw_cmp_scr_bitfields
- {
- uint8_t COUT : 1; //!< [0] Analog Comparator Output
- uint8_t CFF : 1; //!< [1] Analog Comparator Flag Falling
- uint8_t CFR : 1; //!< [2] Analog Comparator Flag Rising
- uint8_t IEF : 1; //!< [3] Comparator Interrupt Enable Falling
- uint8_t IER : 1; //!< [4] Comparator Interrupt Enable Rising
- uint8_t RESERVED0 : 1; //!< [5]
- uint8_t DMAEN : 1; //!< [6] DMA Enable Control
- uint8_t RESERVED1 : 1; //!< [7]
- } B;
-} hw_cmp_scr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CMP_SCR register
- */
-//@{
-#define HW_CMP_SCR_ADDR(x) (REGS_CMP_BASE(x) + 0x3U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CMP_SCR(x) (*(__IO hw_cmp_scr_t *) HW_CMP_SCR_ADDR(x))
-#define HW_CMP_SCR_RD(x) (HW_CMP_SCR(x).U)
-#define HW_CMP_SCR_WR(x, v) (HW_CMP_SCR(x).U = (v))
-#define HW_CMP_SCR_SET(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) | (v)))
-#define HW_CMP_SCR_CLR(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) & ~(v)))
-#define HW_CMP_SCR_TOG(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CMP_SCR bitfields
- */
-
-/*!
- * @name Register CMP_SCR, field COUT[0] (RO)
- *
- * Returns the current value of the Analog Comparator output, when read. The
- * field is reset to 0 and will read as CR1[INV] when the Analog Comparator module
- * is disabled, that is, when CR1[EN] = 0. Writes to this field are ignored.
- */
-//@{
-#define BP_CMP_SCR_COUT (0U) //!< Bit position for CMP_SCR_COUT.
-#define BM_CMP_SCR_COUT (0x01U) //!< Bit mask for CMP_SCR_COUT.
-#define BS_CMP_SCR_COUT (1U) //!< Bit field size in bits for CMP_SCR_COUT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMP_SCR_COUT field.
-#define BR_CMP_SCR_COUT(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_COUT))
-#endif
-//@}
-
-/*!
- * @name Register CMP_SCR, field CFF[1] (W1C)
- *
- * Detects a falling-edge on COUT, when set, during normal operation. CFF is
- * cleared by writing 1 to it. During Stop modes, CFF is level sensitive is edge
- * sensitive .
- *
- * Values:
- * - 0 - Falling-edge on COUT has not been detected.
- * - 1 - Falling-edge on COUT has occurred.
- */
-//@{
-#define BP_CMP_SCR_CFF (1U) //!< Bit position for CMP_SCR_CFF.
-#define BM_CMP_SCR_CFF (0x02U) //!< Bit mask for CMP_SCR_CFF.
-#define BS_CMP_SCR_CFF (1U) //!< Bit field size in bits for CMP_SCR_CFF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMP_SCR_CFF field.
-#define BR_CMP_SCR_CFF(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF))
-#endif
-
-//! @brief Format value for bitfield CMP_SCR_CFF.
-#define BF_CMP_SCR_CFF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_SCR_CFF), uint8_t) & BM_CMP_SCR_CFF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CFF field to a new value.
-#define BW_CMP_SCR_CFF(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CMP_SCR, field CFR[2] (W1C)
- *
- * Detects a rising-edge on COUT, when set, during normal operation. CFR is
- * cleared by writing 1 to it. During Stop modes, CFR is level sensitive is edge
- * sensitive .
- *
- * Values:
- * - 0 - Rising-edge on COUT has not been detected.
- * - 1 - Rising-edge on COUT has occurred.
- */
-//@{
-#define BP_CMP_SCR_CFR (2U) //!< Bit position for CMP_SCR_CFR.
-#define BM_CMP_SCR_CFR (0x04U) //!< Bit mask for CMP_SCR_CFR.
-#define BS_CMP_SCR_CFR (1U) //!< Bit field size in bits for CMP_SCR_CFR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMP_SCR_CFR field.
-#define BR_CMP_SCR_CFR(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR))
-#endif
-
-//! @brief Format value for bitfield CMP_SCR_CFR.
-#define BF_CMP_SCR_CFR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_SCR_CFR), uint8_t) & BM_CMP_SCR_CFR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CFR field to a new value.
-#define BW_CMP_SCR_CFR(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CMP_SCR, field IEF[3] (RW)
- *
- * Enables the CFF interrupt from the CMP. When this field is set, an interrupt
- * will be asserted when CFF is set.
- *
- * Values:
- * - 0 - Interrupt is disabled.
- * - 1 - Interrupt is enabled.
- */
-//@{
-#define BP_CMP_SCR_IEF (3U) //!< Bit position for CMP_SCR_IEF.
-#define BM_CMP_SCR_IEF (0x08U) //!< Bit mask for CMP_SCR_IEF.
-#define BS_CMP_SCR_IEF (1U) //!< Bit field size in bits for CMP_SCR_IEF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMP_SCR_IEF field.
-#define BR_CMP_SCR_IEF(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF))
-#endif
-
-//! @brief Format value for bitfield CMP_SCR_IEF.
-#define BF_CMP_SCR_IEF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_SCR_IEF), uint8_t) & BM_CMP_SCR_IEF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IEF field to a new value.
-#define BW_CMP_SCR_IEF(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CMP_SCR, field IER[4] (RW)
- *
- * Enables the CFR interrupt from the CMP. When this field is set, an interrupt
- * will be asserted when CFR is set.
- *
- * Values:
- * - 0 - Interrupt is disabled.
- * - 1 - Interrupt is enabled.
- */
-//@{
-#define BP_CMP_SCR_IER (4U) //!< Bit position for CMP_SCR_IER.
-#define BM_CMP_SCR_IER (0x10U) //!< Bit mask for CMP_SCR_IER.
-#define BS_CMP_SCR_IER (1U) //!< Bit field size in bits for CMP_SCR_IER.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMP_SCR_IER field.
-#define BR_CMP_SCR_IER(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER))
-#endif
-
-//! @brief Format value for bitfield CMP_SCR_IER.
-#define BF_CMP_SCR_IER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_SCR_IER), uint8_t) & BM_CMP_SCR_IER)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IER field to a new value.
-#define BW_CMP_SCR_IER(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CMP_SCR, field DMAEN[6] (RW)
- *
- * Enables the DMA transfer triggered from the CMP module. When this field is
- * set, a DMA request is asserted when CFR or CFF is set.
- *
- * Values:
- * - 0 - DMA is disabled.
- * - 1 - DMA is enabled.
- */
-//@{
-#define BP_CMP_SCR_DMAEN (6U) //!< Bit position for CMP_SCR_DMAEN.
-#define BM_CMP_SCR_DMAEN (0x40U) //!< Bit mask for CMP_SCR_DMAEN.
-#define BS_CMP_SCR_DMAEN (1U) //!< Bit field size in bits for CMP_SCR_DMAEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMP_SCR_DMAEN field.
-#define BR_CMP_SCR_DMAEN(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN))
-#endif
-
-//! @brief Format value for bitfield CMP_SCR_DMAEN.
-#define BF_CMP_SCR_DMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_SCR_DMAEN), uint8_t) & BM_CMP_SCR_DMAEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DMAEN field to a new value.
-#define BW_CMP_SCR_DMAEN(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CMP_DACCR - DAC Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CMP_DACCR - DAC Control Register (RW)
- *
- * Reset value: 0x00U
- */
-typedef union _hw_cmp_daccr
-{
- uint8_t U;
- struct _hw_cmp_daccr_bitfields
- {
- uint8_t VOSEL : 6; //!< [5:0] DAC Output Voltage Select
- uint8_t VRSEL : 1; //!< [6] Supply Voltage Reference Source Select
- uint8_t DACEN : 1; //!< [7] DAC Enable
- } B;
-} hw_cmp_daccr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CMP_DACCR register
- */
-//@{
-#define HW_CMP_DACCR_ADDR(x) (REGS_CMP_BASE(x) + 0x4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CMP_DACCR(x) (*(__IO hw_cmp_daccr_t *) HW_CMP_DACCR_ADDR(x))
-#define HW_CMP_DACCR_RD(x) (HW_CMP_DACCR(x).U)
-#define HW_CMP_DACCR_WR(x, v) (HW_CMP_DACCR(x).U = (v))
-#define HW_CMP_DACCR_SET(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) | (v)))
-#define HW_CMP_DACCR_CLR(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) & ~(v)))
-#define HW_CMP_DACCR_TOG(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CMP_DACCR bitfields
- */
-
-/*!
- * @name Register CMP_DACCR, field VOSEL[5:0] (RW)
- *
- * Selects an output voltage from one of 64 distinct levels. DACO = (V in /64) *
- * (VOSEL[5:0] + 1) , so the DACO range is from V in /64 to V in .
- */
-//@{
-#define BP_CMP_DACCR_VOSEL (0U) //!< Bit position for CMP_DACCR_VOSEL.
-#define BM_CMP_DACCR_VOSEL (0x3FU) //!< Bit mask for CMP_DACCR_VOSEL.
-#define BS_CMP_DACCR_VOSEL (6U) //!< Bit field size in bits for CMP_DACCR_VOSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMP_DACCR_VOSEL field.
-#define BR_CMP_DACCR_VOSEL(x) (HW_CMP_DACCR(x).B.VOSEL)
-#endif
-
-//! @brief Format value for bitfield CMP_DACCR_VOSEL.
-#define BF_CMP_DACCR_VOSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_DACCR_VOSEL), uint8_t) & BM_CMP_DACCR_VOSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the VOSEL field to a new value.
-#define BW_CMP_DACCR_VOSEL(x, v) (HW_CMP_DACCR_WR(x, (HW_CMP_DACCR_RD(x) & ~BM_CMP_DACCR_VOSEL) | BF_CMP_DACCR_VOSEL(v)))
-#endif
-//@}
-
-/*!
- * @name Register CMP_DACCR, field VRSEL[6] (RW)
- *
- * Values:
- * - 0 - V is selected as resistor ladder network supply reference V. in1 in
- * - 1 - V is selected as resistor ladder network supply reference V. in2 in
- */
-//@{
-#define BP_CMP_DACCR_VRSEL (6U) //!< Bit position for CMP_DACCR_VRSEL.
-#define BM_CMP_DACCR_VRSEL (0x40U) //!< Bit mask for CMP_DACCR_VRSEL.
-#define BS_CMP_DACCR_VRSEL (1U) //!< Bit field size in bits for CMP_DACCR_VRSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMP_DACCR_VRSEL field.
-#define BR_CMP_DACCR_VRSEL(x) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL))
-#endif
-
-//! @brief Format value for bitfield CMP_DACCR_VRSEL.
-#define BF_CMP_DACCR_VRSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_DACCR_VRSEL), uint8_t) & BM_CMP_DACCR_VRSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the VRSEL field to a new value.
-#define BW_CMP_DACCR_VRSEL(x, v) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CMP_DACCR, field DACEN[7] (RW)
- *
- * Enables the DAC. When the DAC is disabled, it is powered down to conserve
- * power.
- *
- * Values:
- * - 0 - DAC is disabled.
- * - 1 - DAC is enabled.
- */
-//@{
-#define BP_CMP_DACCR_DACEN (7U) //!< Bit position for CMP_DACCR_DACEN.
-#define BM_CMP_DACCR_DACEN (0x80U) //!< Bit mask for CMP_DACCR_DACEN.
-#define BS_CMP_DACCR_DACEN (1U) //!< Bit field size in bits for CMP_DACCR_DACEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMP_DACCR_DACEN field.
-#define BR_CMP_DACCR_DACEN(x) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN))
-#endif
-
-//! @brief Format value for bitfield CMP_DACCR_DACEN.
-#define BF_CMP_DACCR_DACEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_DACCR_DACEN), uint8_t) & BM_CMP_DACCR_DACEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DACEN field to a new value.
-#define BW_CMP_DACCR_DACEN(x, v) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CMP_MUXCR - MUX Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CMP_MUXCR - MUX Control Register (RW)
- *
- * Reset value: 0x00U
- */
-typedef union _hw_cmp_muxcr
-{
- uint8_t U;
- struct _hw_cmp_muxcr_bitfields
- {
- uint8_t MSEL : 3; //!< [2:0] Minus Input Mux Control
- uint8_t PSEL : 3; //!< [5:3] Plus Input Mux Control
- uint8_t RESERVED0 : 1; //!< [6]
- uint8_t PSTM : 1; //!< [7] Pass Through Mode Enable
- } B;
-} hw_cmp_muxcr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CMP_MUXCR register
- */
-//@{
-#define HW_CMP_MUXCR_ADDR(x) (REGS_CMP_BASE(x) + 0x5U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CMP_MUXCR(x) (*(__IO hw_cmp_muxcr_t *) HW_CMP_MUXCR_ADDR(x))
-#define HW_CMP_MUXCR_RD(x) (HW_CMP_MUXCR(x).U)
-#define HW_CMP_MUXCR_WR(x, v) (HW_CMP_MUXCR(x).U = (v))
-#define HW_CMP_MUXCR_SET(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) | (v)))
-#define HW_CMP_MUXCR_CLR(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) & ~(v)))
-#define HW_CMP_MUXCR_TOG(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CMP_MUXCR bitfields
- */
-
-/*!
- * @name Register CMP_MUXCR, field MSEL[2:0] (RW)
- *
- * Determines which input is selected for the minus input of the comparator. For
- * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
- * operation selects the same input for both muxes, the comparator automatically
- * shuts down to prevent itself from becoming a noise generator.
- *
- * Values:
- * - 000 - IN0
- * - 001 - IN1
- * - 010 - IN2
- * - 011 - IN3
- * - 100 - IN4
- * - 101 - IN5
- * - 110 - IN6
- * - 111 - IN7
- */
-//@{
-#define BP_CMP_MUXCR_MSEL (0U) //!< Bit position for CMP_MUXCR_MSEL.
-#define BM_CMP_MUXCR_MSEL (0x07U) //!< Bit mask for CMP_MUXCR_MSEL.
-#define BS_CMP_MUXCR_MSEL (3U) //!< Bit field size in bits for CMP_MUXCR_MSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMP_MUXCR_MSEL field.
-#define BR_CMP_MUXCR_MSEL(x) (HW_CMP_MUXCR(x).B.MSEL)
-#endif
-
-//! @brief Format value for bitfield CMP_MUXCR_MSEL.
-#define BF_CMP_MUXCR_MSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_MUXCR_MSEL), uint8_t) & BM_CMP_MUXCR_MSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MSEL field to a new value.
-#define BW_CMP_MUXCR_MSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_MSEL) | BF_CMP_MUXCR_MSEL(v)))
-#endif
-//@}
-
-/*!
- * @name Register CMP_MUXCR, field PSEL[5:3] (RW)
- *
- * Determines which input is selected for the plus input of the comparator. For
- * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
- * operation selects the same input for both muxes, the comparator automatically
- * shuts down to prevent itself from becoming a noise generator.
- *
- * Values:
- * - 000 - IN0
- * - 001 - IN1
- * - 010 - IN2
- * - 011 - IN3
- * - 100 - IN4
- * - 101 - IN5
- * - 110 - IN6
- * - 111 - IN7
- */
-//@{
-#define BP_CMP_MUXCR_PSEL (3U) //!< Bit position for CMP_MUXCR_PSEL.
-#define BM_CMP_MUXCR_PSEL (0x38U) //!< Bit mask for CMP_MUXCR_PSEL.
-#define BS_CMP_MUXCR_PSEL (3U) //!< Bit field size in bits for CMP_MUXCR_PSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMP_MUXCR_PSEL field.
-#define BR_CMP_MUXCR_PSEL(x) (HW_CMP_MUXCR(x).B.PSEL)
-#endif
-
-//! @brief Format value for bitfield CMP_MUXCR_PSEL.
-#define BF_CMP_MUXCR_PSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_MUXCR_PSEL), uint8_t) & BM_CMP_MUXCR_PSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PSEL field to a new value.
-#define BW_CMP_MUXCR_PSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_PSEL) | BF_CMP_MUXCR_PSEL(v)))
-#endif
-//@}
-
-/*!
- * @name Register CMP_MUXCR, field PSTM[7] (RW)
- *
- * This bit is used to enable to MUX pass through mode. Pass through mode is
- * always available but for some devices this feature must be always disabled due to
- * the lack of package pins.
- *
- * Values:
- * - 0 - Pass Through Mode is disabled.
- * - 1 - Pass Through Mode is enabled.
- */
-//@{
-#define BP_CMP_MUXCR_PSTM (7U) //!< Bit position for CMP_MUXCR_PSTM.
-#define BM_CMP_MUXCR_PSTM (0x80U) //!< Bit mask for CMP_MUXCR_PSTM.
-#define BS_CMP_MUXCR_PSTM (1U) //!< Bit field size in bits for CMP_MUXCR_PSTM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMP_MUXCR_PSTM field.
-#define BR_CMP_MUXCR_PSTM(x) (BITBAND_ACCESS8(HW_CMP_MUXCR_ADDR(x), BP_CMP_MUXCR_PSTM))
-#endif
-
-//! @brief Format value for bitfield CMP_MUXCR_PSTM.
-#define BF_CMP_MUXCR_PSTM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_MUXCR_PSTM), uint8_t) & BM_CMP_MUXCR_PSTM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PSTM field to a new value.
-#define BW_CMP_MUXCR_PSTM(x, v) (BITBAND_ACCESS8(HW_CMP_MUXCR_ADDR(x), BP_CMP_MUXCR_PSTM) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_cmp_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All CMP module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_cmp
-{
- __IO hw_cmp_cr0_t CR0; //!< [0x0] CMP Control Register 0
- __IO hw_cmp_cr1_t CR1; //!< [0x1] CMP Control Register 1
- __IO hw_cmp_fpr_t FPR; //!< [0x2] CMP Filter Period Register
- __IO hw_cmp_scr_t SCR; //!< [0x3] CMP Status and Control Register
- __IO hw_cmp_daccr_t DACCR; //!< [0x4] DAC Control Register
- __IO hw_cmp_muxcr_t MUXCR; //!< [0x5] MUX Control Register
-} hw_cmp_t;
-#pragma pack()
-
-//! @brief Macro to access all CMP registers.
-//! @param x CMP instance number.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_CMP(0)</code>.
-#define HW_CMP(x) (*(hw_cmp_t *) REGS_CMP_BASE(x))
-#endif
-
-#endif // __HW_CMP_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_cmt.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1194 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_CMT_REGISTERS_H__
-#define __HW_CMT_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 CMT
- *
- * Carrier Modulator Transmitter
- *
- * Registers defined in this header file:
- * - HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1
- * - HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1
- * - HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2
- * - HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2
- * - HW_CMT_OC - CMT Output Control Register
- * - HW_CMT_MSC - CMT Modulator Status and Control Register
- * - HW_CMT_CMD1 - CMT Modulator Data Register Mark High
- * - HW_CMT_CMD2 - CMT Modulator Data Register Mark Low
- * - HW_CMT_CMD3 - CMT Modulator Data Register Space High
- * - HW_CMT_CMD4 - CMT Modulator Data Register Space Low
- * - HW_CMT_PPS - CMT Primary Prescaler Register
- * - HW_CMT_DMA - CMT Direct Memory Access Register
- *
- * - hw_cmt_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_CMT_BASE
-#define HW_CMT_INSTANCE_COUNT (1U) //!< Number of instances of the CMT module.
-#define REGS_CMT_BASE (0x40062000U) //!< Base address for CMT.
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1 (RW)
- *
- * Reset value: 0x00U
- *
- * This data register contains the primary high value for generating the carrier
- * output.
- */
-typedef union _hw_cmt_cgh1
-{
- uint8_t U;
- struct _hw_cmt_cgh1_bitfields
- {
- uint8_t PH : 8; //!< [7:0] Primary Carrier High Time Data Value
- } B;
-} hw_cmt_cgh1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CMT_CGH1 register
- */
-//@{
-#define HW_CMT_CGH1_ADDR (REGS_CMT_BASE + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CMT_CGH1 (*(__IO hw_cmt_cgh1_t *) HW_CMT_CGH1_ADDR)
-#define HW_CMT_CGH1_RD() (HW_CMT_CGH1.U)
-#define HW_CMT_CGH1_WR(v) (HW_CMT_CGH1.U = (v))
-#define HW_CMT_CGH1_SET(v) (HW_CMT_CGH1_WR(HW_CMT_CGH1_RD() | (v)))
-#define HW_CMT_CGH1_CLR(v) (HW_CMT_CGH1_WR(HW_CMT_CGH1_RD() & ~(v)))
-#define HW_CMT_CGH1_TOG(v) (HW_CMT_CGH1_WR(HW_CMT_CGH1_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CMT_CGH1 bitfields
- */
-
-/*!
- * @name Register CMT_CGH1, field PH[7:0] (RW)
- *
- * Contains the number of input clocks required to generate the carrier high
- * time period. When operating in Time mode, this register is always selected. When
- * operating in FSK mode, this register and the secondary register pair are
- * alternately selected under the control of the modulator. The primary carrier high
- * time value is undefined out of reset. This register must be written to nonzero
- * values before the carrier generator is enabled to avoid spurious results.
- */
-//@{
-#define BP_CMT_CGH1_PH (0U) //!< Bit position for CMT_CGH1_PH.
-#define BM_CMT_CGH1_PH (0xFFU) //!< Bit mask for CMT_CGH1_PH.
-#define BS_CMT_CGH1_PH (8U) //!< Bit field size in bits for CMT_CGH1_PH.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMT_CGH1_PH field.
-#define BR_CMT_CGH1_PH (HW_CMT_CGH1.U)
-#endif
-
-//! @brief Format value for bitfield CMT_CGH1_PH.
-#define BF_CMT_CGH1_PH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CGH1_PH), uint8_t) & BM_CMT_CGH1_PH)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PH field to a new value.
-#define BW_CMT_CGH1_PH(v) (HW_CMT_CGH1_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1 (RW)
- *
- * Reset value: 0x00U
- *
- * This data register contains the primary low value for generating the carrier
- * output.
- */
-typedef union _hw_cmt_cgl1
-{
- uint8_t U;
- struct _hw_cmt_cgl1_bitfields
- {
- uint8_t PL : 8; //!< [7:0] Primary Carrier Low Time Data Value
- } B;
-} hw_cmt_cgl1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CMT_CGL1 register
- */
-//@{
-#define HW_CMT_CGL1_ADDR (REGS_CMT_BASE + 0x1U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CMT_CGL1 (*(__IO hw_cmt_cgl1_t *) HW_CMT_CGL1_ADDR)
-#define HW_CMT_CGL1_RD() (HW_CMT_CGL1.U)
-#define HW_CMT_CGL1_WR(v) (HW_CMT_CGL1.U = (v))
-#define HW_CMT_CGL1_SET(v) (HW_CMT_CGL1_WR(HW_CMT_CGL1_RD() | (v)))
-#define HW_CMT_CGL1_CLR(v) (HW_CMT_CGL1_WR(HW_CMT_CGL1_RD() & ~(v)))
-#define HW_CMT_CGL1_TOG(v) (HW_CMT_CGL1_WR(HW_CMT_CGL1_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CMT_CGL1 bitfields
- */
-
-/*!
- * @name Register CMT_CGL1, field PL[7:0] (RW)
- *
- * Contains the number of input clocks required to generate the carrier low time
- * period. When operating in Time mode, this register is always selected. When
- * operating in FSK mode, this register and the secondary register pair are
- * alternately selected under the control of the modulator. The primary carrier low
- * time value is undefined out of reset. This register must be written to nonzero
- * values before the carrier generator is enabled to avoid spurious results.
- */
-//@{
-#define BP_CMT_CGL1_PL (0U) //!< Bit position for CMT_CGL1_PL.
-#define BM_CMT_CGL1_PL (0xFFU) //!< Bit mask for CMT_CGL1_PL.
-#define BS_CMT_CGL1_PL (8U) //!< Bit field size in bits for CMT_CGL1_PL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMT_CGL1_PL field.
-#define BR_CMT_CGL1_PL (HW_CMT_CGL1.U)
-#endif
-
-//! @brief Format value for bitfield CMT_CGL1_PL.
-#define BF_CMT_CGL1_PL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CGL1_PL), uint8_t) & BM_CMT_CGL1_PL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PL field to a new value.
-#define BW_CMT_CGL1_PL(v) (HW_CMT_CGL1_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2 (RW)
- *
- * Reset value: 0x00U
- *
- * This data register contains the secondary high value for generating the
- * carrier output.
- */
-typedef union _hw_cmt_cgh2
-{
- uint8_t U;
- struct _hw_cmt_cgh2_bitfields
- {
- uint8_t SH : 8; //!< [7:0] Secondary Carrier High Time Data Value
- } B;
-} hw_cmt_cgh2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CMT_CGH2 register
- */
-//@{
-#define HW_CMT_CGH2_ADDR (REGS_CMT_BASE + 0x2U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CMT_CGH2 (*(__IO hw_cmt_cgh2_t *) HW_CMT_CGH2_ADDR)
-#define HW_CMT_CGH2_RD() (HW_CMT_CGH2.U)
-#define HW_CMT_CGH2_WR(v) (HW_CMT_CGH2.U = (v))
-#define HW_CMT_CGH2_SET(v) (HW_CMT_CGH2_WR(HW_CMT_CGH2_RD() | (v)))
-#define HW_CMT_CGH2_CLR(v) (HW_CMT_CGH2_WR(HW_CMT_CGH2_RD() & ~(v)))
-#define HW_CMT_CGH2_TOG(v) (HW_CMT_CGH2_WR(HW_CMT_CGH2_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CMT_CGH2 bitfields
- */
-
-/*!
- * @name Register CMT_CGH2, field SH[7:0] (RW)
- *
- * Contains the number of input clocks required to generate the carrier high
- * time period. When operating in Time mode, this register is never selected. When
- * operating in FSK mode, this register and the primary register pair are
- * alternately selected under control of the modulator. The secondary carrier high time
- * value is undefined out of reset. This register must be written to nonzero
- * values before the carrier generator is enabled when operating in FSK mode.
- */
-//@{
-#define BP_CMT_CGH2_SH (0U) //!< Bit position for CMT_CGH2_SH.
-#define BM_CMT_CGH2_SH (0xFFU) //!< Bit mask for CMT_CGH2_SH.
-#define BS_CMT_CGH2_SH (8U) //!< Bit field size in bits for CMT_CGH2_SH.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMT_CGH2_SH field.
-#define BR_CMT_CGH2_SH (HW_CMT_CGH2.U)
-#endif
-
-//! @brief Format value for bitfield CMT_CGH2_SH.
-#define BF_CMT_CGH2_SH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CGH2_SH), uint8_t) & BM_CMT_CGH2_SH)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SH field to a new value.
-#define BW_CMT_CGH2_SH(v) (HW_CMT_CGH2_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2 (RW)
- *
- * Reset value: 0x00U
- *
- * This data register contains the secondary low value for generating the
- * carrier output.
- */
-typedef union _hw_cmt_cgl2
-{
- uint8_t U;
- struct _hw_cmt_cgl2_bitfields
- {
- uint8_t SL : 8; //!< [7:0] Secondary Carrier Low Time Data Value
- } B;
-} hw_cmt_cgl2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CMT_CGL2 register
- */
-//@{
-#define HW_CMT_CGL2_ADDR (REGS_CMT_BASE + 0x3U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CMT_CGL2 (*(__IO hw_cmt_cgl2_t *) HW_CMT_CGL2_ADDR)
-#define HW_CMT_CGL2_RD() (HW_CMT_CGL2.U)
-#define HW_CMT_CGL2_WR(v) (HW_CMT_CGL2.U = (v))
-#define HW_CMT_CGL2_SET(v) (HW_CMT_CGL2_WR(HW_CMT_CGL2_RD() | (v)))
-#define HW_CMT_CGL2_CLR(v) (HW_CMT_CGL2_WR(HW_CMT_CGL2_RD() & ~(v)))
-#define HW_CMT_CGL2_TOG(v) (HW_CMT_CGL2_WR(HW_CMT_CGL2_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CMT_CGL2 bitfields
- */
-
-/*!
- * @name Register CMT_CGL2, field SL[7:0] (RW)
- *
- * Contains the number of input clocks required to generate the carrier low time
- * period. When operating in Time mode, this register is never selected. When
- * operating in FSK mode, this register and the primary register pair are
- * alternately selected under the control of the modulator. The secondary carrier low time
- * value is undefined out of reset. This register must be written to nonzero
- * values before the carrier generator is enabled when operating in FSK mode.
- */
-//@{
-#define BP_CMT_CGL2_SL (0U) //!< Bit position for CMT_CGL2_SL.
-#define BM_CMT_CGL2_SL (0xFFU) //!< Bit mask for CMT_CGL2_SL.
-#define BS_CMT_CGL2_SL (8U) //!< Bit field size in bits for CMT_CGL2_SL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMT_CGL2_SL field.
-#define BR_CMT_CGL2_SL (HW_CMT_CGL2.U)
-#endif
-
-//! @brief Format value for bitfield CMT_CGL2_SL.
-#define BF_CMT_CGL2_SL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CGL2_SL), uint8_t) & BM_CMT_CGL2_SL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SL field to a new value.
-#define BW_CMT_CGL2_SL(v) (HW_CMT_CGL2_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CMT_OC - CMT Output Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CMT_OC - CMT Output Control Register (RW)
- *
- * Reset value: 0x00U
- *
- * This register is used to control the IRO signal of the CMT module.
- */
-typedef union _hw_cmt_oc
-{
- uint8_t U;
- struct _hw_cmt_oc_bitfields
- {
- uint8_t RESERVED0 : 5; //!< [4:0]
- uint8_t IROPEN : 1; //!< [5] IRO Pin Enable
- uint8_t CMTPOL : 1; //!< [6] CMT Output Polarity
- uint8_t IROL : 1; //!< [7] IRO Latch Control
- } B;
-} hw_cmt_oc_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CMT_OC register
- */
-//@{
-#define HW_CMT_OC_ADDR (REGS_CMT_BASE + 0x4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CMT_OC (*(__IO hw_cmt_oc_t *) HW_CMT_OC_ADDR)
-#define HW_CMT_OC_RD() (HW_CMT_OC.U)
-#define HW_CMT_OC_WR(v) (HW_CMT_OC.U = (v))
-#define HW_CMT_OC_SET(v) (HW_CMT_OC_WR(HW_CMT_OC_RD() | (v)))
-#define HW_CMT_OC_CLR(v) (HW_CMT_OC_WR(HW_CMT_OC_RD() & ~(v)))
-#define HW_CMT_OC_TOG(v) (HW_CMT_OC_WR(HW_CMT_OC_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CMT_OC bitfields
- */
-
-/*!
- * @name Register CMT_OC, field IROPEN[5] (RW)
- *
- * Enables and disables the IRO signal. When the IRO signal is enabled, it is an
- * output that drives out either the CMT transmitter output or the state of IROL
- * depending on whether MSC[MCGEN] is set or not. Also, the state of output is
- * either inverted or non-inverted, depending on the state of CMTPOL. When the IRO
- * signal is disabled, it is in a high-impedance state and is unable to draw any
- * current. This signal is disabled during reset.
- *
- * Values:
- * - 0 - The IRO signal is disabled.
- * - 1 - The IRO signal is enabled as output.
- */
-//@{
-#define BP_CMT_OC_IROPEN (5U) //!< Bit position for CMT_OC_IROPEN.
-#define BM_CMT_OC_IROPEN (0x20U) //!< Bit mask for CMT_OC_IROPEN.
-#define BS_CMT_OC_IROPEN (1U) //!< Bit field size in bits for CMT_OC_IROPEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMT_OC_IROPEN field.
-#define BR_CMT_OC_IROPEN (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_IROPEN))
-#endif
-
-//! @brief Format value for bitfield CMT_OC_IROPEN.
-#define BF_CMT_OC_IROPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_OC_IROPEN), uint8_t) & BM_CMT_OC_IROPEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IROPEN field to a new value.
-#define BW_CMT_OC_IROPEN(v) (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_IROPEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CMT_OC, field CMTPOL[6] (RW)
- *
- * Controls the polarity of the IRO signal.
- *
- * Values:
- * - 0 - The IRO signal is active-low.
- * - 1 - The IRO signal is active-high.
- */
-//@{
-#define BP_CMT_OC_CMTPOL (6U) //!< Bit position for CMT_OC_CMTPOL.
-#define BM_CMT_OC_CMTPOL (0x40U) //!< Bit mask for CMT_OC_CMTPOL.
-#define BS_CMT_OC_CMTPOL (1U) //!< Bit field size in bits for CMT_OC_CMTPOL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMT_OC_CMTPOL field.
-#define BR_CMT_OC_CMTPOL (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_CMTPOL))
-#endif
-
-//! @brief Format value for bitfield CMT_OC_CMTPOL.
-#define BF_CMT_OC_CMTPOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_OC_CMTPOL), uint8_t) & BM_CMT_OC_CMTPOL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CMTPOL field to a new value.
-#define BW_CMT_OC_CMTPOL(v) (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_CMTPOL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CMT_OC, field IROL[7] (RW)
- *
- * Reads the state of the IRO latch. Writing to IROL changes the state of the
- * IRO signal when MSC[MCGEN] is cleared and IROPEN is set.
- */
-//@{
-#define BP_CMT_OC_IROL (7U) //!< Bit position for CMT_OC_IROL.
-#define BM_CMT_OC_IROL (0x80U) //!< Bit mask for CMT_OC_IROL.
-#define BS_CMT_OC_IROL (1U) //!< Bit field size in bits for CMT_OC_IROL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMT_OC_IROL field.
-#define BR_CMT_OC_IROL (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_IROL))
-#endif
-
-//! @brief Format value for bitfield CMT_OC_IROL.
-#define BF_CMT_OC_IROL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_OC_IROL), uint8_t) & BM_CMT_OC_IROL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IROL field to a new value.
-#define BW_CMT_OC_IROL(v) (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_IROL) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CMT_MSC - CMT Modulator Status and Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CMT_MSC - CMT Modulator Status and Control Register (RW)
- *
- * Reset value: 0x00U
- *
- * This register contains the modulator and carrier generator enable (MCGEN),
- * end of cycle interrupt enable (EOCIE), FSK mode select (FSK), baseband enable
- * (BASE), extended space (EXSPC), prescaler (CMTDIV) bits, and the end of cycle
- * (EOCF) status bit.
- */
-typedef union _hw_cmt_msc
-{
- uint8_t U;
- struct _hw_cmt_msc_bitfields
- {
- uint8_t MCGEN : 1; //!< [0] Modulator and Carrier Generator Enable
- uint8_t EOCIE : 1; //!< [1] End of Cycle Interrupt Enable
- uint8_t FSK : 1; //!< [2] FSK Mode Select
- uint8_t BASE : 1; //!< [3] Baseband Enable
- uint8_t EXSPC : 1; //!< [4] Extended Space Enable
- uint8_t CMTDIV : 2; //!< [6:5] CMT Clock Divide Prescaler
- uint8_t EOCF : 1; //!< [7] End Of Cycle Status Flag
- } B;
-} hw_cmt_msc_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CMT_MSC register
- */
-//@{
-#define HW_CMT_MSC_ADDR (REGS_CMT_BASE + 0x5U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CMT_MSC (*(__IO hw_cmt_msc_t *) HW_CMT_MSC_ADDR)
-#define HW_CMT_MSC_RD() (HW_CMT_MSC.U)
-#define HW_CMT_MSC_WR(v) (HW_CMT_MSC.U = (v))
-#define HW_CMT_MSC_SET(v) (HW_CMT_MSC_WR(HW_CMT_MSC_RD() | (v)))
-#define HW_CMT_MSC_CLR(v) (HW_CMT_MSC_WR(HW_CMT_MSC_RD() & ~(v)))
-#define HW_CMT_MSC_TOG(v) (HW_CMT_MSC_WR(HW_CMT_MSC_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CMT_MSC bitfields
- */
-
-/*!
- * @name Register CMT_MSC, field MCGEN[0] (RW)
- *
- * Setting MCGEN will initialize the carrier generator and modulator and will
- * enable all clocks. When enabled, the carrier generator and modulator will
- * function continuously. When MCGEN is cleared, the current modulator cycle will be
- * allowed to expire before all carrier and modulator clocks are disabled to save
- * power and the modulator output is forced low. To prevent spurious operation,
- * the user should initialize all data and control registers before enabling the
- * system.
- *
- * Values:
- * - 0 - Modulator and carrier generator disabled
- * - 1 - Modulator and carrier generator enabled
- */
-//@{
-#define BP_CMT_MSC_MCGEN (0U) //!< Bit position for CMT_MSC_MCGEN.
-#define BM_CMT_MSC_MCGEN (0x01U) //!< Bit mask for CMT_MSC_MCGEN.
-#define BS_CMT_MSC_MCGEN (1U) //!< Bit field size in bits for CMT_MSC_MCGEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMT_MSC_MCGEN field.
-#define BR_CMT_MSC_MCGEN (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_MCGEN))
-#endif
-
-//! @brief Format value for bitfield CMT_MSC_MCGEN.
-#define BF_CMT_MSC_MCGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_MCGEN), uint8_t) & BM_CMT_MSC_MCGEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MCGEN field to a new value.
-#define BW_CMT_MSC_MCGEN(v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_MCGEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CMT_MSC, field EOCIE[1] (RW)
- *
- * Requests to enable a CPU interrupt when EOCF is set if EOCIE is high.
- *
- * Values:
- * - 0 - CPU interrupt is disabled.
- * - 1 - CPU interrupt is enabled.
- */
-//@{
-#define BP_CMT_MSC_EOCIE (1U) //!< Bit position for CMT_MSC_EOCIE.
-#define BM_CMT_MSC_EOCIE (0x02U) //!< Bit mask for CMT_MSC_EOCIE.
-#define BS_CMT_MSC_EOCIE (1U) //!< Bit field size in bits for CMT_MSC_EOCIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMT_MSC_EOCIE field.
-#define BR_CMT_MSC_EOCIE (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_EOCIE))
-#endif
-
-//! @brief Format value for bitfield CMT_MSC_EOCIE.
-#define BF_CMT_MSC_EOCIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_EOCIE), uint8_t) & BM_CMT_MSC_EOCIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EOCIE field to a new value.
-#define BW_CMT_MSC_EOCIE(v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_EOCIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CMT_MSC, field FSK[2] (RW)
- *
- * Enables FSK operation.
- *
- * Values:
- * - 0 - The CMT operates in Time or Baseband mode.
- * - 1 - The CMT operates in FSK mode.
- */
-//@{
-#define BP_CMT_MSC_FSK (2U) //!< Bit position for CMT_MSC_FSK.
-#define BM_CMT_MSC_FSK (0x04U) //!< Bit mask for CMT_MSC_FSK.
-#define BS_CMT_MSC_FSK (1U) //!< Bit field size in bits for CMT_MSC_FSK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMT_MSC_FSK field.
-#define BR_CMT_MSC_FSK (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_FSK))
-#endif
-
-//! @brief Format value for bitfield CMT_MSC_FSK.
-#define BF_CMT_MSC_FSK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_FSK), uint8_t) & BM_CMT_MSC_FSK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FSK field to a new value.
-#define BW_CMT_MSC_FSK(v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_FSK) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CMT_MSC, field BASE[3] (RW)
- *
- * When set, BASE disables the carrier generator and forces the carrier output
- * high for generation of baseband protocols. When BASE is cleared, the carrier
- * generator is enabled and the carrier output toggles at the frequency determined
- * by values stored in the carrier data registers. This field is cleared by
- * reset. This field is not double-buffered and must not be written to during a
- * transmission.
- *
- * Values:
- * - 0 - Baseband mode is disabled.
- * - 1 - Baseband mode is enabled.
- */
-//@{
-#define BP_CMT_MSC_BASE (3U) //!< Bit position for CMT_MSC_BASE.
-#define BM_CMT_MSC_BASE (0x08U) //!< Bit mask for CMT_MSC_BASE.
-#define BS_CMT_MSC_BASE (1U) //!< Bit field size in bits for CMT_MSC_BASE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMT_MSC_BASE field.
-#define BR_CMT_MSC_BASE (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_BASE))
-#endif
-
-//! @brief Format value for bitfield CMT_MSC_BASE.
-#define BF_CMT_MSC_BASE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_BASE), uint8_t) & BM_CMT_MSC_BASE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BASE field to a new value.
-#define BW_CMT_MSC_BASE(v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_BASE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CMT_MSC, field EXSPC[4] (RW)
- *
- * Enables the extended space operation.
- *
- * Values:
- * - 0 - Extended space is disabled.
- * - 1 - Extended space is enabled.
- */
-//@{
-#define BP_CMT_MSC_EXSPC (4U) //!< Bit position for CMT_MSC_EXSPC.
-#define BM_CMT_MSC_EXSPC (0x10U) //!< Bit mask for CMT_MSC_EXSPC.
-#define BS_CMT_MSC_EXSPC (1U) //!< Bit field size in bits for CMT_MSC_EXSPC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMT_MSC_EXSPC field.
-#define BR_CMT_MSC_EXSPC (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_EXSPC))
-#endif
-
-//! @brief Format value for bitfield CMT_MSC_EXSPC.
-#define BF_CMT_MSC_EXSPC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_EXSPC), uint8_t) & BM_CMT_MSC_EXSPC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EXSPC field to a new value.
-#define BW_CMT_MSC_EXSPC(v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_EXSPC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CMT_MSC, field CMTDIV[6:5] (RW)
- *
- * Causes the CMT to be clocked at the IF signal frequency, or the IF frequency
- * divided by 2 ,4, or 8 . This field must not be changed during a transmission
- * because it is not double-buffered.
- *
- * Values:
- * - 00 - IF * 1
- * - 01 - IF * 2
- * - 10 - IF * 4
- * - 11 - IF * 8
- */
-//@{
-#define BP_CMT_MSC_CMTDIV (5U) //!< Bit position for CMT_MSC_CMTDIV.
-#define BM_CMT_MSC_CMTDIV (0x60U) //!< Bit mask for CMT_MSC_CMTDIV.
-#define BS_CMT_MSC_CMTDIV (2U) //!< Bit field size in bits for CMT_MSC_CMTDIV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMT_MSC_CMTDIV field.
-#define BR_CMT_MSC_CMTDIV (HW_CMT_MSC.B.CMTDIV)
-#endif
-
-//! @brief Format value for bitfield CMT_MSC_CMTDIV.
-#define BF_CMT_MSC_CMTDIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_CMTDIV), uint8_t) & BM_CMT_MSC_CMTDIV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CMTDIV field to a new value.
-#define BW_CMT_MSC_CMTDIV(v) (HW_CMT_MSC_WR((HW_CMT_MSC_RD() & ~BM_CMT_MSC_CMTDIV) | BF_CMT_MSC_CMTDIV(v)))
-#endif
-//@}
-
-/*!
- * @name Register CMT_MSC, field EOCF[7] (RO)
- *
- * Sets when: The modulator is not currently active and MCGEN is set to begin
- * the initial CMT transmission. At the end of each modulation cycle while MCGEN is
- * set. This is recognized when a match occurs between the contents of the space
- * period register and the down counter. At this time, the counter is
- * initialized with, possibly new contents of the mark period buffer, CMD1 and CMD2, and
- * the space period register is loaded with, possibly new contents of the space
- * period buffer, CMD3 and CMD4. This flag is cleared by reading MSC followed by an
- * access of CMD2 or CMD4, or by the DMA transfer.
- *
- * Values:
- * - 0 - End of modulation cycle has not occured since the flag last cleared.
- * - 1 - End of modulator cycle has occurred.
- */
-//@{
-#define BP_CMT_MSC_EOCF (7U) //!< Bit position for CMT_MSC_EOCF.
-#define BM_CMT_MSC_EOCF (0x80U) //!< Bit mask for CMT_MSC_EOCF.
-#define BS_CMT_MSC_EOCF (1U) //!< Bit field size in bits for CMT_MSC_EOCF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMT_MSC_EOCF field.
-#define BR_CMT_MSC_EOCF (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_EOCF))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CMT_CMD1 - CMT Modulator Data Register Mark High
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CMT_CMD1 - CMT Modulator Data Register Mark High (RW)
- *
- * Reset value: 0x00U
- *
- * The contents of this register are transferred to the modulator down counter
- * upon the completion of a modulation period.
- */
-typedef union _hw_cmt_cmd1
-{
- uint8_t U;
- struct _hw_cmt_cmd1_bitfields
- {
- uint8_t MB : 8; //!< [7:0]
- } B;
-} hw_cmt_cmd1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CMT_CMD1 register
- */
-//@{
-#define HW_CMT_CMD1_ADDR (REGS_CMT_BASE + 0x6U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CMT_CMD1 (*(__IO hw_cmt_cmd1_t *) HW_CMT_CMD1_ADDR)
-#define HW_CMT_CMD1_RD() (HW_CMT_CMD1.U)
-#define HW_CMT_CMD1_WR(v) (HW_CMT_CMD1.U = (v))
-#define HW_CMT_CMD1_SET(v) (HW_CMT_CMD1_WR(HW_CMT_CMD1_RD() | (v)))
-#define HW_CMT_CMD1_CLR(v) (HW_CMT_CMD1_WR(HW_CMT_CMD1_RD() & ~(v)))
-#define HW_CMT_CMD1_TOG(v) (HW_CMT_CMD1_WR(HW_CMT_CMD1_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CMT_CMD1 bitfields
- */
-
-/*!
- * @name Register CMT_CMD1, field MB[7:0] (RW)
- *
- * Controls the upper mark periods of the modulator for all modes.
- */
-//@{
-#define BP_CMT_CMD1_MB (0U) //!< Bit position for CMT_CMD1_MB.
-#define BM_CMT_CMD1_MB (0xFFU) //!< Bit mask for CMT_CMD1_MB.
-#define BS_CMT_CMD1_MB (8U) //!< Bit field size in bits for CMT_CMD1_MB.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMT_CMD1_MB field.
-#define BR_CMT_CMD1_MB (HW_CMT_CMD1.U)
-#endif
-
-//! @brief Format value for bitfield CMT_CMD1_MB.
-#define BF_CMT_CMD1_MB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CMD1_MB), uint8_t) & BM_CMT_CMD1_MB)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MB field to a new value.
-#define BW_CMT_CMD1_MB(v) (HW_CMT_CMD1_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CMT_CMD2 - CMT Modulator Data Register Mark Low
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CMT_CMD2 - CMT Modulator Data Register Mark Low (RW)
- *
- * Reset value: 0x00U
- *
- * The contents of this register are transferred to the modulator down counter
- * upon the completion of a modulation period.
- */
-typedef union _hw_cmt_cmd2
-{
- uint8_t U;
- struct _hw_cmt_cmd2_bitfields
- {
- uint8_t MB : 8; //!< [7:0]
- } B;
-} hw_cmt_cmd2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CMT_CMD2 register
- */
-//@{
-#define HW_CMT_CMD2_ADDR (REGS_CMT_BASE + 0x7U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CMT_CMD2 (*(__IO hw_cmt_cmd2_t *) HW_CMT_CMD2_ADDR)
-#define HW_CMT_CMD2_RD() (HW_CMT_CMD2.U)
-#define HW_CMT_CMD2_WR(v) (HW_CMT_CMD2.U = (v))
-#define HW_CMT_CMD2_SET(v) (HW_CMT_CMD2_WR(HW_CMT_CMD2_RD() | (v)))
-#define HW_CMT_CMD2_CLR(v) (HW_CMT_CMD2_WR(HW_CMT_CMD2_RD() & ~(v)))
-#define HW_CMT_CMD2_TOG(v) (HW_CMT_CMD2_WR(HW_CMT_CMD2_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CMT_CMD2 bitfields
- */
-
-/*!
- * @name Register CMT_CMD2, field MB[7:0] (RW)
- *
- * Controls the lower mark periods of the modulator for all modes.
- */
-//@{
-#define BP_CMT_CMD2_MB (0U) //!< Bit position for CMT_CMD2_MB.
-#define BM_CMT_CMD2_MB (0xFFU) //!< Bit mask for CMT_CMD2_MB.
-#define BS_CMT_CMD2_MB (8U) //!< Bit field size in bits for CMT_CMD2_MB.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMT_CMD2_MB field.
-#define BR_CMT_CMD2_MB (HW_CMT_CMD2.U)
-#endif
-
-//! @brief Format value for bitfield CMT_CMD2_MB.
-#define BF_CMT_CMD2_MB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CMD2_MB), uint8_t) & BM_CMT_CMD2_MB)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MB field to a new value.
-#define BW_CMT_CMD2_MB(v) (HW_CMT_CMD2_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CMT_CMD3 - CMT Modulator Data Register Space High
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CMT_CMD3 - CMT Modulator Data Register Space High (RW)
- *
- * Reset value: 0x00U
- *
- * The contents of this register are transferred to the space period register
- * upon the completion of a modulation period.
- */
-typedef union _hw_cmt_cmd3
-{
- uint8_t U;
- struct _hw_cmt_cmd3_bitfields
- {
- uint8_t SB : 8; //!< [7:0]
- } B;
-} hw_cmt_cmd3_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CMT_CMD3 register
- */
-//@{
-#define HW_CMT_CMD3_ADDR (REGS_CMT_BASE + 0x8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CMT_CMD3 (*(__IO hw_cmt_cmd3_t *) HW_CMT_CMD3_ADDR)
-#define HW_CMT_CMD3_RD() (HW_CMT_CMD3.U)
-#define HW_CMT_CMD3_WR(v) (HW_CMT_CMD3.U = (v))
-#define HW_CMT_CMD3_SET(v) (HW_CMT_CMD3_WR(HW_CMT_CMD3_RD() | (v)))
-#define HW_CMT_CMD3_CLR(v) (HW_CMT_CMD3_WR(HW_CMT_CMD3_RD() & ~(v)))
-#define HW_CMT_CMD3_TOG(v) (HW_CMT_CMD3_WR(HW_CMT_CMD3_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CMT_CMD3 bitfields
- */
-
-/*!
- * @name Register CMT_CMD3, field SB[7:0] (RW)
- *
- * Controls the upper space periods of the modulator for all modes.
- */
-//@{
-#define BP_CMT_CMD3_SB (0U) //!< Bit position for CMT_CMD3_SB.
-#define BM_CMT_CMD3_SB (0xFFU) //!< Bit mask for CMT_CMD3_SB.
-#define BS_CMT_CMD3_SB (8U) //!< Bit field size in bits for CMT_CMD3_SB.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMT_CMD3_SB field.
-#define BR_CMT_CMD3_SB (HW_CMT_CMD3.U)
-#endif
-
-//! @brief Format value for bitfield CMT_CMD3_SB.
-#define BF_CMT_CMD3_SB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CMD3_SB), uint8_t) & BM_CMT_CMD3_SB)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SB field to a new value.
-#define BW_CMT_CMD3_SB(v) (HW_CMT_CMD3_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CMT_CMD4 - CMT Modulator Data Register Space Low
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CMT_CMD4 - CMT Modulator Data Register Space Low (RW)
- *
- * Reset value: 0x00U
- *
- * The contents of this register are transferred to the space period register
- * upon the completion of a modulation period.
- */
-typedef union _hw_cmt_cmd4
-{
- uint8_t U;
- struct _hw_cmt_cmd4_bitfields
- {
- uint8_t SB : 8; //!< [7:0]
- } B;
-} hw_cmt_cmd4_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CMT_CMD4 register
- */
-//@{
-#define HW_CMT_CMD4_ADDR (REGS_CMT_BASE + 0x9U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CMT_CMD4 (*(__IO hw_cmt_cmd4_t *) HW_CMT_CMD4_ADDR)
-#define HW_CMT_CMD4_RD() (HW_CMT_CMD4.U)
-#define HW_CMT_CMD4_WR(v) (HW_CMT_CMD4.U = (v))
-#define HW_CMT_CMD4_SET(v) (HW_CMT_CMD4_WR(HW_CMT_CMD4_RD() | (v)))
-#define HW_CMT_CMD4_CLR(v) (HW_CMT_CMD4_WR(HW_CMT_CMD4_RD() & ~(v)))
-#define HW_CMT_CMD4_TOG(v) (HW_CMT_CMD4_WR(HW_CMT_CMD4_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CMT_CMD4 bitfields
- */
-
-/*!
- * @name Register CMT_CMD4, field SB[7:0] (RW)
- *
- * Controls the lower space periods of the modulator for all modes.
- */
-//@{
-#define BP_CMT_CMD4_SB (0U) //!< Bit position for CMT_CMD4_SB.
-#define BM_CMT_CMD4_SB (0xFFU) //!< Bit mask for CMT_CMD4_SB.
-#define BS_CMT_CMD4_SB (8U) //!< Bit field size in bits for CMT_CMD4_SB.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMT_CMD4_SB field.
-#define BR_CMT_CMD4_SB (HW_CMT_CMD4.U)
-#endif
-
-//! @brief Format value for bitfield CMT_CMD4_SB.
-#define BF_CMT_CMD4_SB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CMD4_SB), uint8_t) & BM_CMT_CMD4_SB)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SB field to a new value.
-#define BW_CMT_CMD4_SB(v) (HW_CMT_CMD4_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CMT_PPS - CMT Primary Prescaler Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CMT_PPS - CMT Primary Prescaler Register (RW)
- *
- * Reset value: 0x00U
- *
- * This register is used to set the Primary Prescaler Divider field (PPSDIV).
- */
-typedef union _hw_cmt_pps
-{
- uint8_t U;
- struct _hw_cmt_pps_bitfields
- {
- uint8_t PPSDIV : 4; //!< [3:0] Primary Prescaler Divider
- uint8_t RESERVED0 : 4; //!< [7:4]
- } B;
-} hw_cmt_pps_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CMT_PPS register
- */
-//@{
-#define HW_CMT_PPS_ADDR (REGS_CMT_BASE + 0xAU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CMT_PPS (*(__IO hw_cmt_pps_t *) HW_CMT_PPS_ADDR)
-#define HW_CMT_PPS_RD() (HW_CMT_PPS.U)
-#define HW_CMT_PPS_WR(v) (HW_CMT_PPS.U = (v))
-#define HW_CMT_PPS_SET(v) (HW_CMT_PPS_WR(HW_CMT_PPS_RD() | (v)))
-#define HW_CMT_PPS_CLR(v) (HW_CMT_PPS_WR(HW_CMT_PPS_RD() & ~(v)))
-#define HW_CMT_PPS_TOG(v) (HW_CMT_PPS_WR(HW_CMT_PPS_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CMT_PPS bitfields
- */
-
-/*!
- * @name Register CMT_PPS, field PPSDIV[3:0] (RW)
- *
- * Divides the CMT clock to generate the Intermediate Frequency clock enable to
- * the secondary prescaler.
- *
- * Values:
- * - 0000 - Bus clock * 1
- * - 0001 - Bus clock * 2
- * - 0010 - Bus clock * 3
- * - 0011 - Bus clock * 4
- * - 0100 - Bus clock * 5
- * - 0101 - Bus clock * 6
- * - 0110 - Bus clock * 7
- * - 0111 - Bus clock * 8
- * - 1000 - Bus clock * 9
- * - 1001 - Bus clock * 10
- * - 1010 - Bus clock * 11
- * - 1011 - Bus clock * 12
- * - 1100 - Bus clock * 13
- * - 1101 - Bus clock * 14
- * - 1110 - Bus clock * 15
- * - 1111 - Bus clock * 16
- */
-//@{
-#define BP_CMT_PPS_PPSDIV (0U) //!< Bit position for CMT_PPS_PPSDIV.
-#define BM_CMT_PPS_PPSDIV (0x0FU) //!< Bit mask for CMT_PPS_PPSDIV.
-#define BS_CMT_PPS_PPSDIV (4U) //!< Bit field size in bits for CMT_PPS_PPSDIV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMT_PPS_PPSDIV field.
-#define BR_CMT_PPS_PPSDIV (HW_CMT_PPS.B.PPSDIV)
-#endif
-
-//! @brief Format value for bitfield CMT_PPS_PPSDIV.
-#define BF_CMT_PPS_PPSDIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_PPS_PPSDIV), uint8_t) & BM_CMT_PPS_PPSDIV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PPSDIV field to a new value.
-#define BW_CMT_PPS_PPSDIV(v) (HW_CMT_PPS_WR((HW_CMT_PPS_RD() & ~BM_CMT_PPS_PPSDIV) | BF_CMT_PPS_PPSDIV(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CMT_DMA - CMT Direct Memory Access Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CMT_DMA - CMT Direct Memory Access Register (RW)
- *
- * Reset value: 0x00U
- *
- * This register is used to enable/disable direct memory access (DMA).
- */
-typedef union _hw_cmt_dma
-{
- uint8_t U;
- struct _hw_cmt_dma_bitfields
- {
- uint8_t DMAb : 1; //!< [0] DMA Enable
- uint8_t RESERVED0 : 7; //!< [7:1]
- } B;
-} hw_cmt_dma_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CMT_DMA register
- */
-//@{
-#define HW_CMT_DMA_ADDR (REGS_CMT_BASE + 0xBU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CMT_DMA (*(__IO hw_cmt_dma_t *) HW_CMT_DMA_ADDR)
-#define HW_CMT_DMA_RD() (HW_CMT_DMA.U)
-#define HW_CMT_DMA_WR(v) (HW_CMT_DMA.U = (v))
-#define HW_CMT_DMA_SET(v) (HW_CMT_DMA_WR(HW_CMT_DMA_RD() | (v)))
-#define HW_CMT_DMA_CLR(v) (HW_CMT_DMA_WR(HW_CMT_DMA_RD() & ~(v)))
-#define HW_CMT_DMA_TOG(v) (HW_CMT_DMA_WR(HW_CMT_DMA_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CMT_DMA bitfields
- */
-
-/*!
- * @name Register CMT_DMA, field DMA[0] (RW)
- *
- * Enables the DMA protocol.
- *
- * Values:
- * - 0 - DMA transfer request and done are disabled.
- * - 1 - DMA transfer request and done are enabled.
- */
-//@{
-#define BP_CMT_DMA_DMA (0U) //!< Bit position for CMT_DMA_DMA.
-#define BM_CMT_DMA_DMA (0x01U) //!< Bit mask for CMT_DMA_DMA.
-#define BS_CMT_DMA_DMA (1U) //!< Bit field size in bits for CMT_DMA_DMA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CMT_DMA_DMA field.
-#define BR_CMT_DMA_DMA (BITBAND_ACCESS8(HW_CMT_DMA_ADDR, BP_CMT_DMA_DMA))
-#endif
-
-//! @brief Format value for bitfield CMT_DMA_DMA.
-#define BF_CMT_DMA_DMA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_DMA_DMA), uint8_t) & BM_CMT_DMA_DMA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DMA field to a new value.
-#define BW_CMT_DMA_DMA(v) (BITBAND_ACCESS8(HW_CMT_DMA_ADDR, BP_CMT_DMA_DMA) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_cmt_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All CMT module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_cmt
-{
- __IO hw_cmt_cgh1_t CGH1; //!< [0x0] CMT Carrier Generator High Data Register 1
- __IO hw_cmt_cgl1_t CGL1; //!< [0x1] CMT Carrier Generator Low Data Register 1
- __IO hw_cmt_cgh2_t CGH2; //!< [0x2] CMT Carrier Generator High Data Register 2
- __IO hw_cmt_cgl2_t CGL2; //!< [0x3] CMT Carrier Generator Low Data Register 2
- __IO hw_cmt_oc_t OC; //!< [0x4] CMT Output Control Register
- __IO hw_cmt_msc_t MSC; //!< [0x5] CMT Modulator Status and Control Register
- __IO hw_cmt_cmd1_t CMD1; //!< [0x6] CMT Modulator Data Register Mark High
- __IO hw_cmt_cmd2_t CMD2; //!< [0x7] CMT Modulator Data Register Mark Low
- __IO hw_cmt_cmd3_t CMD3; //!< [0x8] CMT Modulator Data Register Space High
- __IO hw_cmt_cmd4_t CMD4; //!< [0x9] CMT Modulator Data Register Space Low
- __IO hw_cmt_pps_t PPS; //!< [0xA] CMT Primary Prescaler Register
- __IO hw_cmt_dma_t DMA; //!< [0xB] CMT Direct Memory Access Register
-} hw_cmt_t;
-#pragma pack()
-
-//! @brief Macro to access all CMT registers.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_CMT</code>.
-#define HW_CMT (*(hw_cmt_t *) REGS_CMT_BASE)
-#endif
-
-#endif // __HW_CMT_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_crc.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1499 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_CRC_REGISTERS_H__
-#define __HW_CRC_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 CRC
- *
- * Cyclic Redundancy Check
- *
- * Registers defined in this header file:
- * - HW_CRC_DATAL - CRC_DATAL register.
- * - HW_CRC_DATAH - CRC_DATAH register.
- * - HW_CRC_DATALL - CRC_DATALL register.
- * - HW_CRC_DATALU - CRC_DATALU register.
- * - HW_CRC_DATAHL - CRC_DATAHL register.
- * - HW_CRC_DATAHU - CRC_DATAHU register.
- * - HW_CRC_DATA - CRC Data register
- * - HW_CRC_GPOLY - CRC Polynomial register
- * - HW_CRC_GPOLYL - CRC_GPOLYL register.
- * - HW_CRC_GPOLYH - CRC_GPOLYH register.
- * - HW_CRC_GPOLYLL - CRC_GPOLYLL register.
- * - HW_CRC_GPOLYLU - CRC_GPOLYLU register.
- * - HW_CRC_GPOLYHL - CRC_GPOLYHL register.
- * - HW_CRC_GPOLYHU - CRC_GPOLYHU register.
- * - HW_CRC_CTRL - CRC Control register
- * - HW_CRC_CTRLHU - CRC_CTRLHU register.
- *
- * - hw_crc_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_CRC_BASE
-#define HW_CRC_INSTANCE_COUNT (1U) //!< Number of instances of the CRC module.
-#define REGS_CRC_BASE (0x40032000U) //!< Base address for CRC.
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CRC_DATAL - CRC_DATAL register.
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CRC_DATAL - CRC_DATAL register. (RW)
- *
- * Reset value: 0xFFFFU
- */
-typedef union _hw_crc_datal
-{
- uint16_t U;
- struct _hw_crc_datal_bitfields
- {
- uint16_t DATAL : 16; //!< [15:0] DATAL stores the lower 16 bits of
- //! the 16/32 bit CRC
- } B;
-} hw_crc_datal_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CRC_DATAL register
- */
-//@{
-#define HW_CRC_DATAL_ADDR (REGS_CRC_BASE + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CRC_DATAL (*(__IO hw_crc_datal_t *) HW_CRC_DATAL_ADDR)
-#define HW_CRC_DATAL_RD() (HW_CRC_DATAL.U)
-#define HW_CRC_DATAL_WR(v) (HW_CRC_DATAL.U = (v))
-#define HW_CRC_DATAL_SET(v) (HW_CRC_DATAL_WR(HW_CRC_DATAL_RD() | (v)))
-#define HW_CRC_DATAL_CLR(v) (HW_CRC_DATAL_WR(HW_CRC_DATAL_RD() & ~(v)))
-#define HW_CRC_DATAL_TOG(v) (HW_CRC_DATAL_WR(HW_CRC_DATAL_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CRC_DATAL bitfields
- */
-
-/*!
- * @name Register CRC_DATAL, field DATAL[15:0] (RW)
- */
-//@{
-#define BP_CRC_DATAL_DATAL (0U) //!< Bit position for CRC_DATAL_DATAL.
-#define BM_CRC_DATAL_DATAL (0xFFFFU) //!< Bit mask for CRC_DATAL_DATAL.
-#define BS_CRC_DATAL_DATAL (16U) //!< Bit field size in bits for CRC_DATAL_DATAL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CRC_DATAL_DATAL field.
-#define BR_CRC_DATAL_DATAL (HW_CRC_DATAL.U)
-#endif
-
-//! @brief Format value for bitfield CRC_DATAL_DATAL.
-#define BF_CRC_DATAL_DATAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_CRC_DATAL_DATAL), uint16_t) & BM_CRC_DATAL_DATAL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DATAL field to a new value.
-#define BW_CRC_DATAL_DATAL(v) (HW_CRC_DATAL_WR(v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_CRC_DATAH - CRC_DATAH register.
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CRC_DATAH - CRC_DATAH register. (RW)
- *
- * Reset value: 0xFFFFU
- */
-typedef union _hw_crc_datah
-{
- uint16_t U;
- struct _hw_crc_datah_bitfields
- {
- uint16_t DATAH : 16; //!< [15:0] DATAH stores the high 16 bits of the
- //! 16/32 bit CRC
- } B;
-} hw_crc_datah_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CRC_DATAH register
- */
-//@{
-#define HW_CRC_DATAH_ADDR (REGS_CRC_BASE + 0x2U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CRC_DATAH (*(__IO hw_crc_datah_t *) HW_CRC_DATAH_ADDR)
-#define HW_CRC_DATAH_RD() (HW_CRC_DATAH.U)
-#define HW_CRC_DATAH_WR(v) (HW_CRC_DATAH.U = (v))
-#define HW_CRC_DATAH_SET(v) (HW_CRC_DATAH_WR(HW_CRC_DATAH_RD() | (v)))
-#define HW_CRC_DATAH_CLR(v) (HW_CRC_DATAH_WR(HW_CRC_DATAH_RD() & ~(v)))
-#define HW_CRC_DATAH_TOG(v) (HW_CRC_DATAH_WR(HW_CRC_DATAH_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CRC_DATAH bitfields
- */
-
-/*!
- * @name Register CRC_DATAH, field DATAH[15:0] (RW)
- */
-//@{
-#define BP_CRC_DATAH_DATAH (0U) //!< Bit position for CRC_DATAH_DATAH.
-#define BM_CRC_DATAH_DATAH (0xFFFFU) //!< Bit mask for CRC_DATAH_DATAH.
-#define BS_CRC_DATAH_DATAH (16U) //!< Bit field size in bits for CRC_DATAH_DATAH.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CRC_DATAH_DATAH field.
-#define BR_CRC_DATAH_DATAH (HW_CRC_DATAH.U)
-#endif
-
-//! @brief Format value for bitfield CRC_DATAH_DATAH.
-#define BF_CRC_DATAH_DATAH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_CRC_DATAH_DATAH), uint16_t) & BM_CRC_DATAH_DATAH)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DATAH field to a new value.
-#define BW_CRC_DATAH_DATAH(v) (HW_CRC_DATAH_WR(v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_CRC_DATALL - CRC_DATALL register.
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CRC_DATALL - CRC_DATALL register. (RW)
- *
- * Reset value: 0xFFU
- */
-typedef union _hw_crc_datall
-{
- uint8_t U;
- struct _hw_crc_datall_bitfields
- {
- uint8_t DATALL : 8; //!< [7:0] CRCLL stores the first 8 bits of the
- //! 32 bit DATA
- } B;
-} hw_crc_datall_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CRC_DATALL register
- */
-//@{
-#define HW_CRC_DATALL_ADDR (REGS_CRC_BASE + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CRC_DATALL (*(__IO hw_crc_datall_t *) HW_CRC_DATALL_ADDR)
-#define HW_CRC_DATALL_RD() (HW_CRC_DATALL.U)
-#define HW_CRC_DATALL_WR(v) (HW_CRC_DATALL.U = (v))
-#define HW_CRC_DATALL_SET(v) (HW_CRC_DATALL_WR(HW_CRC_DATALL_RD() | (v)))
-#define HW_CRC_DATALL_CLR(v) (HW_CRC_DATALL_WR(HW_CRC_DATALL_RD() & ~(v)))
-#define HW_CRC_DATALL_TOG(v) (HW_CRC_DATALL_WR(HW_CRC_DATALL_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CRC_DATALL bitfields
- */
-
-/*!
- * @name Register CRC_DATALL, field DATALL[7:0] (RW)
- */
-//@{
-#define BP_CRC_DATALL_DATALL (0U) //!< Bit position for CRC_DATALL_DATALL.
-#define BM_CRC_DATALL_DATALL (0xFFU) //!< Bit mask for CRC_DATALL_DATALL.
-#define BS_CRC_DATALL_DATALL (8U) //!< Bit field size in bits for CRC_DATALL_DATALL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CRC_DATALL_DATALL field.
-#define BR_CRC_DATALL_DATALL (HW_CRC_DATALL.U)
-#endif
-
-//! @brief Format value for bitfield CRC_DATALL_DATALL.
-#define BF_CRC_DATALL_DATALL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_DATALL_DATALL), uint8_t) & BM_CRC_DATALL_DATALL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DATALL field to a new value.
-#define BW_CRC_DATALL_DATALL(v) (HW_CRC_DATALL_WR(v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_CRC_DATALU - CRC_DATALU register.
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CRC_DATALU - CRC_DATALU register. (RW)
- *
- * Reset value: 0xFFU
- */
-typedef union _hw_crc_datalu
-{
- uint8_t U;
- struct _hw_crc_datalu_bitfields
- {
- uint8_t DATALU : 8; //!< [7:0] DATALL stores the second 8 bits of the
- //! 32 bit CRC
- } B;
-} hw_crc_datalu_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CRC_DATALU register
- */
-//@{
-#define HW_CRC_DATALU_ADDR (REGS_CRC_BASE + 0x1U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CRC_DATALU (*(__IO hw_crc_datalu_t *) HW_CRC_DATALU_ADDR)
-#define HW_CRC_DATALU_RD() (HW_CRC_DATALU.U)
-#define HW_CRC_DATALU_WR(v) (HW_CRC_DATALU.U = (v))
-#define HW_CRC_DATALU_SET(v) (HW_CRC_DATALU_WR(HW_CRC_DATALU_RD() | (v)))
-#define HW_CRC_DATALU_CLR(v) (HW_CRC_DATALU_WR(HW_CRC_DATALU_RD() & ~(v)))
-#define HW_CRC_DATALU_TOG(v) (HW_CRC_DATALU_WR(HW_CRC_DATALU_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CRC_DATALU bitfields
- */
-
-/*!
- * @name Register CRC_DATALU, field DATALU[7:0] (RW)
- */
-//@{
-#define BP_CRC_DATALU_DATALU (0U) //!< Bit position for CRC_DATALU_DATALU.
-#define BM_CRC_DATALU_DATALU (0xFFU) //!< Bit mask for CRC_DATALU_DATALU.
-#define BS_CRC_DATALU_DATALU (8U) //!< Bit field size in bits for CRC_DATALU_DATALU.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CRC_DATALU_DATALU field.
-#define BR_CRC_DATALU_DATALU (HW_CRC_DATALU.U)
-#endif
-
-//! @brief Format value for bitfield CRC_DATALU_DATALU.
-#define BF_CRC_DATALU_DATALU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_DATALU_DATALU), uint8_t) & BM_CRC_DATALU_DATALU)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DATALU field to a new value.
-#define BW_CRC_DATALU_DATALU(v) (HW_CRC_DATALU_WR(v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_CRC_DATAHL - CRC_DATAHL register.
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CRC_DATAHL - CRC_DATAHL register. (RW)
- *
- * Reset value: 0xFFU
- */
-typedef union _hw_crc_datahl
-{
- uint8_t U;
- struct _hw_crc_datahl_bitfields
- {
- uint8_t DATAHL : 8; //!< [7:0] DATAHL stores the third 8 bits of the
- //! 32 bit CRC
- } B;
-} hw_crc_datahl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CRC_DATAHL register
- */
-//@{
-#define HW_CRC_DATAHL_ADDR (REGS_CRC_BASE + 0x2U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CRC_DATAHL (*(__IO hw_crc_datahl_t *) HW_CRC_DATAHL_ADDR)
-#define HW_CRC_DATAHL_RD() (HW_CRC_DATAHL.U)
-#define HW_CRC_DATAHL_WR(v) (HW_CRC_DATAHL.U = (v))
-#define HW_CRC_DATAHL_SET(v) (HW_CRC_DATAHL_WR(HW_CRC_DATAHL_RD() | (v)))
-#define HW_CRC_DATAHL_CLR(v) (HW_CRC_DATAHL_WR(HW_CRC_DATAHL_RD() & ~(v)))
-#define HW_CRC_DATAHL_TOG(v) (HW_CRC_DATAHL_WR(HW_CRC_DATAHL_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CRC_DATAHL bitfields
- */
-
-/*!
- * @name Register CRC_DATAHL, field DATAHL[7:0] (RW)
- */
-//@{
-#define BP_CRC_DATAHL_DATAHL (0U) //!< Bit position for CRC_DATAHL_DATAHL.
-#define BM_CRC_DATAHL_DATAHL (0xFFU) //!< Bit mask for CRC_DATAHL_DATAHL.
-#define BS_CRC_DATAHL_DATAHL (8U) //!< Bit field size in bits for CRC_DATAHL_DATAHL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CRC_DATAHL_DATAHL field.
-#define BR_CRC_DATAHL_DATAHL (HW_CRC_DATAHL.U)
-#endif
-
-//! @brief Format value for bitfield CRC_DATAHL_DATAHL.
-#define BF_CRC_DATAHL_DATAHL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_DATAHL_DATAHL), uint8_t) & BM_CRC_DATAHL_DATAHL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DATAHL field to a new value.
-#define BW_CRC_DATAHL_DATAHL(v) (HW_CRC_DATAHL_WR(v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_CRC_DATAHU - CRC_DATAHU register.
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CRC_DATAHU - CRC_DATAHU register. (RW)
- *
- * Reset value: 0xFFU
- */
-typedef union _hw_crc_datahu
-{
- uint8_t U;
- struct _hw_crc_datahu_bitfields
- {
- uint8_t DATAHU : 8; //!< [7:0] DATAHU stores the fourth 8 bits of the
- //! 32 bit CRC
- } B;
-} hw_crc_datahu_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CRC_DATAHU register
- */
-//@{
-#define HW_CRC_DATAHU_ADDR (REGS_CRC_BASE + 0x3U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CRC_DATAHU (*(__IO hw_crc_datahu_t *) HW_CRC_DATAHU_ADDR)
-#define HW_CRC_DATAHU_RD() (HW_CRC_DATAHU.U)
-#define HW_CRC_DATAHU_WR(v) (HW_CRC_DATAHU.U = (v))
-#define HW_CRC_DATAHU_SET(v) (HW_CRC_DATAHU_WR(HW_CRC_DATAHU_RD() | (v)))
-#define HW_CRC_DATAHU_CLR(v) (HW_CRC_DATAHU_WR(HW_CRC_DATAHU_RD() & ~(v)))
-#define HW_CRC_DATAHU_TOG(v) (HW_CRC_DATAHU_WR(HW_CRC_DATAHU_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CRC_DATAHU bitfields
- */
-
-/*!
- * @name Register CRC_DATAHU, field DATAHU[7:0] (RW)
- */
-//@{
-#define BP_CRC_DATAHU_DATAHU (0U) //!< Bit position for CRC_DATAHU_DATAHU.
-#define BM_CRC_DATAHU_DATAHU (0xFFU) //!< Bit mask for CRC_DATAHU_DATAHU.
-#define BS_CRC_DATAHU_DATAHU (8U) //!< Bit field size in bits for CRC_DATAHU_DATAHU.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CRC_DATAHU_DATAHU field.
-#define BR_CRC_DATAHU_DATAHU (HW_CRC_DATAHU.U)
-#endif
-
-//! @brief Format value for bitfield CRC_DATAHU_DATAHU.
-#define BF_CRC_DATAHU_DATAHU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_DATAHU_DATAHU), uint8_t) & BM_CRC_DATAHU_DATAHU)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DATAHU field to a new value.
-#define BW_CRC_DATAHU_DATAHU(v) (HW_CRC_DATAHU_WR(v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_CRC_DATA - CRC Data register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CRC_DATA - CRC Data register (RW)
- *
- * Reset value: 0xFFFFFFFFU
- *
- * The CRC Data register contains the value of the seed, data, and checksum.
- * When CTRL[WAS] is set, any write to the data register is regarded as the seed
- * value. When CTRL[WAS] is cleared, any write to the data register is regarded as
- * data for general CRC computation. In 16-bit CRC mode, the HU and HL fields are
- * not used for programming the seed value, and reads of these fields return an
- * indeterminate value. In 32-bit CRC mode, all fields are used for programming
- * the seed value. When programming data values, the values can be written 8 bits,
- * 16 bits, or 32 bits at a time, provided all bytes are contiguous; with MSB of
- * data value written first. After all data values are written, the CRC result
- * can be read from this data register. In 16-bit CRC mode, the CRC result is
- * available in the LU and LL fields. In 32-bit CRC mode, all fields contain the
- * result. Reads of this register at any time return the intermediate CRC value,
- * provided the CRC module is configured.
- */
-typedef union _hw_crc_data
-{
- uint32_t U;
- struct _hw_crc_data_bitfields
- {
- uint32_t LL : 8; //!< [7:0] CRC Low Lower Byte
- uint32_t LU : 8; //!< [15:8] CRC Low Upper Byte
- uint32_t HL : 8; //!< [23:16] CRC High Lower Byte
- uint32_t HU : 8; //!< [31:24] CRC High Upper Byte
- } B;
-} hw_crc_data_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CRC_DATA register
- */
-//@{
-#define HW_CRC_DATA_ADDR (REGS_CRC_BASE + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CRC_DATA (*(__IO hw_crc_data_t *) HW_CRC_DATA_ADDR)
-#define HW_CRC_DATA_RD() (HW_CRC_DATA.U)
-#define HW_CRC_DATA_WR(v) (HW_CRC_DATA.U = (v))
-#define HW_CRC_DATA_SET(v) (HW_CRC_DATA_WR(HW_CRC_DATA_RD() | (v)))
-#define HW_CRC_DATA_CLR(v) (HW_CRC_DATA_WR(HW_CRC_DATA_RD() & ~(v)))
-#define HW_CRC_DATA_TOG(v) (HW_CRC_DATA_WR(HW_CRC_DATA_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CRC_DATA bitfields
- */
-
-/*!
- * @name Register CRC_DATA, field LL[7:0] (RW)
- *
- * When CTRL[WAS] is 1, values written to this field are part of the seed value.
- * When CTRL[WAS] is 0, data written to this field is used for CRC checksum
- * generation.
- */
-//@{
-#define BP_CRC_DATA_LL (0U) //!< Bit position for CRC_DATA_LL.
-#define BM_CRC_DATA_LL (0x000000FFU) //!< Bit mask for CRC_DATA_LL.
-#define BS_CRC_DATA_LL (8U) //!< Bit field size in bits for CRC_DATA_LL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CRC_DATA_LL field.
-#define BR_CRC_DATA_LL (HW_CRC_DATA.B.LL)
-#endif
-
-//! @brief Format value for bitfield CRC_DATA_LL.
-#define BF_CRC_DATA_LL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_DATA_LL), uint32_t) & BM_CRC_DATA_LL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LL field to a new value.
-#define BW_CRC_DATA_LL(v) (HW_CRC_DATA_WR((HW_CRC_DATA_RD() & ~BM_CRC_DATA_LL) | BF_CRC_DATA_LL(v)))
-#endif
-//@}
-
-/*!
- * @name Register CRC_DATA, field LU[15:8] (RW)
- *
- * When CTRL[WAS] is 1, values written to this field are part of the seed value.
- * When CTRL[WAS] is 0, data written to this field is used for CRC checksum
- * generation.
- */
-//@{
-#define BP_CRC_DATA_LU (8U) //!< Bit position for CRC_DATA_LU.
-#define BM_CRC_DATA_LU (0x0000FF00U) //!< Bit mask for CRC_DATA_LU.
-#define BS_CRC_DATA_LU (8U) //!< Bit field size in bits for CRC_DATA_LU.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CRC_DATA_LU field.
-#define BR_CRC_DATA_LU (HW_CRC_DATA.B.LU)
-#endif
-
-//! @brief Format value for bitfield CRC_DATA_LU.
-#define BF_CRC_DATA_LU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_DATA_LU), uint32_t) & BM_CRC_DATA_LU)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LU field to a new value.
-#define BW_CRC_DATA_LU(v) (HW_CRC_DATA_WR((HW_CRC_DATA_RD() & ~BM_CRC_DATA_LU) | BF_CRC_DATA_LU(v)))
-#endif
-//@}
-
-/*!
- * @name Register CRC_DATA, field HL[23:16] (RW)
- *
- * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming
- * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this
- * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data
- * written to this field is used for CRC checksum generation in both 16-bit and
- * 32-bit CRC modes.
- */
-//@{
-#define BP_CRC_DATA_HL (16U) //!< Bit position for CRC_DATA_HL.
-#define BM_CRC_DATA_HL (0x00FF0000U) //!< Bit mask for CRC_DATA_HL.
-#define BS_CRC_DATA_HL (8U) //!< Bit field size in bits for CRC_DATA_HL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CRC_DATA_HL field.
-#define BR_CRC_DATA_HL (HW_CRC_DATA.B.HL)
-#endif
-
-//! @brief Format value for bitfield CRC_DATA_HL.
-#define BF_CRC_DATA_HL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_DATA_HL), uint32_t) & BM_CRC_DATA_HL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the HL field to a new value.
-#define BW_CRC_DATA_HL(v) (HW_CRC_DATA_WR((HW_CRC_DATA_RD() & ~BM_CRC_DATA_HL) | BF_CRC_DATA_HL(v)))
-#endif
-//@}
-
-/*!
- * @name Register CRC_DATA, field HU[31:24] (RW)
- *
- * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming
- * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this
- * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data
- * written to this field is used for CRC checksum generation in both 16-bit and
- * 32-bit CRC modes.
- */
-//@{
-#define BP_CRC_DATA_HU (24U) //!< Bit position for CRC_DATA_HU.
-#define BM_CRC_DATA_HU (0xFF000000U) //!< Bit mask for CRC_DATA_HU.
-#define BS_CRC_DATA_HU (8U) //!< Bit field size in bits for CRC_DATA_HU.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CRC_DATA_HU field.
-#define BR_CRC_DATA_HU (HW_CRC_DATA.B.HU)
-#endif
-
-//! @brief Format value for bitfield CRC_DATA_HU.
-#define BF_CRC_DATA_HU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_DATA_HU), uint32_t) & BM_CRC_DATA_HU)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the HU field to a new value.
-#define BW_CRC_DATA_HU(v) (HW_CRC_DATA_WR((HW_CRC_DATA_RD() & ~BM_CRC_DATA_HU) | BF_CRC_DATA_HU(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CRC_GPOLY - CRC Polynomial register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CRC_GPOLY - CRC Polynomial register (RW)
- *
- * Reset value: 0x00001021U
- *
- * This register contains the value of the polynomial for the CRC calculation.
- * The HIGH field contains the upper 16 bits of the CRC polynomial, which are used
- * only in 32-bit CRC mode. Writes to the HIGH field are ignored in 16-bit CRC
- * mode. The LOW field contains the lower 16 bits of the CRC polynomial, which are
- * used in both 16- and 32-bit CRC modes.
- */
-typedef union _hw_crc_gpoly
-{
- uint32_t U;
- struct _hw_crc_gpoly_bitfields
- {
- uint32_t LOW : 16; //!< [15:0] Low Polynominal Half-word
- uint32_t HIGH : 16; //!< [31:16] High Polynominal Half-word
- } B;
-} hw_crc_gpoly_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CRC_GPOLY register
- */
-//@{
-#define HW_CRC_GPOLY_ADDR (REGS_CRC_BASE + 0x4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CRC_GPOLY (*(__IO hw_crc_gpoly_t *) HW_CRC_GPOLY_ADDR)
-#define HW_CRC_GPOLY_RD() (HW_CRC_GPOLY.U)
-#define HW_CRC_GPOLY_WR(v) (HW_CRC_GPOLY.U = (v))
-#define HW_CRC_GPOLY_SET(v) (HW_CRC_GPOLY_WR(HW_CRC_GPOLY_RD() | (v)))
-#define HW_CRC_GPOLY_CLR(v) (HW_CRC_GPOLY_WR(HW_CRC_GPOLY_RD() & ~(v)))
-#define HW_CRC_GPOLY_TOG(v) (HW_CRC_GPOLY_WR(HW_CRC_GPOLY_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CRC_GPOLY bitfields
- */
-
-/*!
- * @name Register CRC_GPOLY, field LOW[15:0] (RW)
- *
- * Writable and readable in both 32-bit and 16-bit CRC modes.
- */
-//@{
-#define BP_CRC_GPOLY_LOW (0U) //!< Bit position for CRC_GPOLY_LOW.
-#define BM_CRC_GPOLY_LOW (0x0000FFFFU) //!< Bit mask for CRC_GPOLY_LOW.
-#define BS_CRC_GPOLY_LOW (16U) //!< Bit field size in bits for CRC_GPOLY_LOW.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CRC_GPOLY_LOW field.
-#define BR_CRC_GPOLY_LOW (HW_CRC_GPOLY.B.LOW)
-#endif
-
-//! @brief Format value for bitfield CRC_GPOLY_LOW.
-#define BF_CRC_GPOLY_LOW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_GPOLY_LOW), uint32_t) & BM_CRC_GPOLY_LOW)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LOW field to a new value.
-#define BW_CRC_GPOLY_LOW(v) (HW_CRC_GPOLY_WR((HW_CRC_GPOLY_RD() & ~BM_CRC_GPOLY_LOW) | BF_CRC_GPOLY_LOW(v)))
-#endif
-//@}
-
-/*!
- * @name Register CRC_GPOLY, field HIGH[31:16] (RW)
- *
- * Writable and readable in 32-bit CRC mode (CTRL[TCRC] is 1). This field is not
- * writable in 16-bit CRC mode (CTRL[TCRC] is 0).
- */
-//@{
-#define BP_CRC_GPOLY_HIGH (16U) //!< Bit position for CRC_GPOLY_HIGH.
-#define BM_CRC_GPOLY_HIGH (0xFFFF0000U) //!< Bit mask for CRC_GPOLY_HIGH.
-#define BS_CRC_GPOLY_HIGH (16U) //!< Bit field size in bits for CRC_GPOLY_HIGH.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CRC_GPOLY_HIGH field.
-#define BR_CRC_GPOLY_HIGH (HW_CRC_GPOLY.B.HIGH)
-#endif
-
-//! @brief Format value for bitfield CRC_GPOLY_HIGH.
-#define BF_CRC_GPOLY_HIGH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_GPOLY_HIGH), uint32_t) & BM_CRC_GPOLY_HIGH)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the HIGH field to a new value.
-#define BW_CRC_GPOLY_HIGH(v) (HW_CRC_GPOLY_WR((HW_CRC_GPOLY_RD() & ~BM_CRC_GPOLY_HIGH) | BF_CRC_GPOLY_HIGH(v)))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_CRC_GPOLYL - CRC_GPOLYL register.
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CRC_GPOLYL - CRC_GPOLYL register. (RW)
- *
- * Reset value: 0xFFFFU
- */
-typedef union _hw_crc_gpolyl
-{
- uint16_t U;
- struct _hw_crc_gpolyl_bitfields
- {
- uint16_t GPOLYL : 16; //!< [15:0] POLYL stores the lower 16 bits of
- //! the 16/32 bit CRC polynomial value
- } B;
-} hw_crc_gpolyl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CRC_GPOLYL register
- */
-//@{
-#define HW_CRC_GPOLYL_ADDR (REGS_CRC_BASE + 0x4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CRC_GPOLYL (*(__IO hw_crc_gpolyl_t *) HW_CRC_GPOLYL_ADDR)
-#define HW_CRC_GPOLYL_RD() (HW_CRC_GPOLYL.U)
-#define HW_CRC_GPOLYL_WR(v) (HW_CRC_GPOLYL.U = (v))
-#define HW_CRC_GPOLYL_SET(v) (HW_CRC_GPOLYL_WR(HW_CRC_GPOLYL_RD() | (v)))
-#define HW_CRC_GPOLYL_CLR(v) (HW_CRC_GPOLYL_WR(HW_CRC_GPOLYL_RD() & ~(v)))
-#define HW_CRC_GPOLYL_TOG(v) (HW_CRC_GPOLYL_WR(HW_CRC_GPOLYL_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CRC_GPOLYL bitfields
- */
-
-/*!
- * @name Register CRC_GPOLYL, field GPOLYL[15:0] (RW)
- */
-//@{
-#define BP_CRC_GPOLYL_GPOLYL (0U) //!< Bit position for CRC_GPOLYL_GPOLYL.
-#define BM_CRC_GPOLYL_GPOLYL (0xFFFFU) //!< Bit mask for CRC_GPOLYL_GPOLYL.
-#define BS_CRC_GPOLYL_GPOLYL (16U) //!< Bit field size in bits for CRC_GPOLYL_GPOLYL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CRC_GPOLYL_GPOLYL field.
-#define BR_CRC_GPOLYL_GPOLYL (HW_CRC_GPOLYL.U)
-#endif
-
-//! @brief Format value for bitfield CRC_GPOLYL_GPOLYL.
-#define BF_CRC_GPOLYL_GPOLYL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_CRC_GPOLYL_GPOLYL), uint16_t) & BM_CRC_GPOLYL_GPOLYL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the GPOLYL field to a new value.
-#define BW_CRC_GPOLYL_GPOLYL(v) (HW_CRC_GPOLYL_WR(v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_CRC_GPOLYH - CRC_GPOLYH register.
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CRC_GPOLYH - CRC_GPOLYH register. (RW)
- *
- * Reset value: 0xFFFFU
- */
-typedef union _hw_crc_gpolyh
-{
- uint16_t U;
- struct _hw_crc_gpolyh_bitfields
- {
- uint16_t GPOLYH : 16; //!< [15:0] POLYH stores the high 16 bits of
- //! the 16/32 bit CRC polynomial value
- } B;
-} hw_crc_gpolyh_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CRC_GPOLYH register
- */
-//@{
-#define HW_CRC_GPOLYH_ADDR (REGS_CRC_BASE + 0x6U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CRC_GPOLYH (*(__IO hw_crc_gpolyh_t *) HW_CRC_GPOLYH_ADDR)
-#define HW_CRC_GPOLYH_RD() (HW_CRC_GPOLYH.U)
-#define HW_CRC_GPOLYH_WR(v) (HW_CRC_GPOLYH.U = (v))
-#define HW_CRC_GPOLYH_SET(v) (HW_CRC_GPOLYH_WR(HW_CRC_GPOLYH_RD() | (v)))
-#define HW_CRC_GPOLYH_CLR(v) (HW_CRC_GPOLYH_WR(HW_CRC_GPOLYH_RD() & ~(v)))
-#define HW_CRC_GPOLYH_TOG(v) (HW_CRC_GPOLYH_WR(HW_CRC_GPOLYH_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CRC_GPOLYH bitfields
- */
-
-/*!
- * @name Register CRC_GPOLYH, field GPOLYH[15:0] (RW)
- */
-//@{
-#define BP_CRC_GPOLYH_GPOLYH (0U) //!< Bit position for CRC_GPOLYH_GPOLYH.
-#define BM_CRC_GPOLYH_GPOLYH (0xFFFFU) //!< Bit mask for CRC_GPOLYH_GPOLYH.
-#define BS_CRC_GPOLYH_GPOLYH (16U) //!< Bit field size in bits for CRC_GPOLYH_GPOLYH.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CRC_GPOLYH_GPOLYH field.
-#define BR_CRC_GPOLYH_GPOLYH (HW_CRC_GPOLYH.U)
-#endif
-
-//! @brief Format value for bitfield CRC_GPOLYH_GPOLYH.
-#define BF_CRC_GPOLYH_GPOLYH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_CRC_GPOLYH_GPOLYH), uint16_t) & BM_CRC_GPOLYH_GPOLYH)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the GPOLYH field to a new value.
-#define BW_CRC_GPOLYH_GPOLYH(v) (HW_CRC_GPOLYH_WR(v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_CRC_GPOLYLL - CRC_GPOLYLL register.
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CRC_GPOLYLL - CRC_GPOLYLL register. (RW)
- *
- * Reset value: 0xFFU
- */
-typedef union _hw_crc_gpolyll
-{
- uint8_t U;
- struct _hw_crc_gpolyll_bitfields
- {
- uint8_t GPOLYLL : 8; //!< [7:0] POLYLL stores the first 8 bits of the
- //! 32 bit CRC
- } B;
-} hw_crc_gpolyll_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CRC_GPOLYLL register
- */
-//@{
-#define HW_CRC_GPOLYLL_ADDR (REGS_CRC_BASE + 0x4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CRC_GPOLYLL (*(__IO hw_crc_gpolyll_t *) HW_CRC_GPOLYLL_ADDR)
-#define HW_CRC_GPOLYLL_RD() (HW_CRC_GPOLYLL.U)
-#define HW_CRC_GPOLYLL_WR(v) (HW_CRC_GPOLYLL.U = (v))
-#define HW_CRC_GPOLYLL_SET(v) (HW_CRC_GPOLYLL_WR(HW_CRC_GPOLYLL_RD() | (v)))
-#define HW_CRC_GPOLYLL_CLR(v) (HW_CRC_GPOLYLL_WR(HW_CRC_GPOLYLL_RD() & ~(v)))
-#define HW_CRC_GPOLYLL_TOG(v) (HW_CRC_GPOLYLL_WR(HW_CRC_GPOLYLL_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CRC_GPOLYLL bitfields
- */
-
-/*!
- * @name Register CRC_GPOLYLL, field GPOLYLL[7:0] (RW)
- */
-//@{
-#define BP_CRC_GPOLYLL_GPOLYLL (0U) //!< Bit position for CRC_GPOLYLL_GPOLYLL.
-#define BM_CRC_GPOLYLL_GPOLYLL (0xFFU) //!< Bit mask for CRC_GPOLYLL_GPOLYLL.
-#define BS_CRC_GPOLYLL_GPOLYLL (8U) //!< Bit field size in bits for CRC_GPOLYLL_GPOLYLL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CRC_GPOLYLL_GPOLYLL field.
-#define BR_CRC_GPOLYLL_GPOLYLL (HW_CRC_GPOLYLL.U)
-#endif
-
-//! @brief Format value for bitfield CRC_GPOLYLL_GPOLYLL.
-#define BF_CRC_GPOLYLL_GPOLYLL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_GPOLYLL_GPOLYLL), uint8_t) & BM_CRC_GPOLYLL_GPOLYLL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the GPOLYLL field to a new value.
-#define BW_CRC_GPOLYLL_GPOLYLL(v) (HW_CRC_GPOLYLL_WR(v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_CRC_GPOLYLU - CRC_GPOLYLU register.
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CRC_GPOLYLU - CRC_GPOLYLU register. (RW)
- *
- * Reset value: 0xFFU
- */
-typedef union _hw_crc_gpolylu
-{
- uint8_t U;
- struct _hw_crc_gpolylu_bitfields
- {
- uint8_t GPOLYLU : 8; //!< [7:0] POLYLL stores the second 8 bits of
- //! the 32 bit CRC
- } B;
-} hw_crc_gpolylu_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CRC_GPOLYLU register
- */
-//@{
-#define HW_CRC_GPOLYLU_ADDR (REGS_CRC_BASE + 0x5U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CRC_GPOLYLU (*(__IO hw_crc_gpolylu_t *) HW_CRC_GPOLYLU_ADDR)
-#define HW_CRC_GPOLYLU_RD() (HW_CRC_GPOLYLU.U)
-#define HW_CRC_GPOLYLU_WR(v) (HW_CRC_GPOLYLU.U = (v))
-#define HW_CRC_GPOLYLU_SET(v) (HW_CRC_GPOLYLU_WR(HW_CRC_GPOLYLU_RD() | (v)))
-#define HW_CRC_GPOLYLU_CLR(v) (HW_CRC_GPOLYLU_WR(HW_CRC_GPOLYLU_RD() & ~(v)))
-#define HW_CRC_GPOLYLU_TOG(v) (HW_CRC_GPOLYLU_WR(HW_CRC_GPOLYLU_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CRC_GPOLYLU bitfields
- */
-
-/*!
- * @name Register CRC_GPOLYLU, field GPOLYLU[7:0] (RW)
- */
-//@{
-#define BP_CRC_GPOLYLU_GPOLYLU (0U) //!< Bit position for CRC_GPOLYLU_GPOLYLU.
-#define BM_CRC_GPOLYLU_GPOLYLU (0xFFU) //!< Bit mask for CRC_GPOLYLU_GPOLYLU.
-#define BS_CRC_GPOLYLU_GPOLYLU (8U) //!< Bit field size in bits for CRC_GPOLYLU_GPOLYLU.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CRC_GPOLYLU_GPOLYLU field.
-#define BR_CRC_GPOLYLU_GPOLYLU (HW_CRC_GPOLYLU.U)
-#endif
-
-//! @brief Format value for bitfield CRC_GPOLYLU_GPOLYLU.
-#define BF_CRC_GPOLYLU_GPOLYLU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_GPOLYLU_GPOLYLU), uint8_t) & BM_CRC_GPOLYLU_GPOLYLU)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the GPOLYLU field to a new value.
-#define BW_CRC_GPOLYLU_GPOLYLU(v) (HW_CRC_GPOLYLU_WR(v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_CRC_GPOLYHL - CRC_GPOLYHL register.
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CRC_GPOLYHL - CRC_GPOLYHL register. (RW)
- *
- * Reset value: 0xFFU
- */
-typedef union _hw_crc_gpolyhl
-{
- uint8_t U;
- struct _hw_crc_gpolyhl_bitfields
- {
- uint8_t GPOLYHL : 8; //!< [7:0] POLYHL stores the third 8 bits of the
- //! 32 bit CRC
- } B;
-} hw_crc_gpolyhl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CRC_GPOLYHL register
- */
-//@{
-#define HW_CRC_GPOLYHL_ADDR (REGS_CRC_BASE + 0x6U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CRC_GPOLYHL (*(__IO hw_crc_gpolyhl_t *) HW_CRC_GPOLYHL_ADDR)
-#define HW_CRC_GPOLYHL_RD() (HW_CRC_GPOLYHL.U)
-#define HW_CRC_GPOLYHL_WR(v) (HW_CRC_GPOLYHL.U = (v))
-#define HW_CRC_GPOLYHL_SET(v) (HW_CRC_GPOLYHL_WR(HW_CRC_GPOLYHL_RD() | (v)))
-#define HW_CRC_GPOLYHL_CLR(v) (HW_CRC_GPOLYHL_WR(HW_CRC_GPOLYHL_RD() & ~(v)))
-#define HW_CRC_GPOLYHL_TOG(v) (HW_CRC_GPOLYHL_WR(HW_CRC_GPOLYHL_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CRC_GPOLYHL bitfields
- */
-
-/*!
- * @name Register CRC_GPOLYHL, field GPOLYHL[7:0] (RW)
- */
-//@{
-#define BP_CRC_GPOLYHL_GPOLYHL (0U) //!< Bit position for CRC_GPOLYHL_GPOLYHL.
-#define BM_CRC_GPOLYHL_GPOLYHL (0xFFU) //!< Bit mask for CRC_GPOLYHL_GPOLYHL.
-#define BS_CRC_GPOLYHL_GPOLYHL (8U) //!< Bit field size in bits for CRC_GPOLYHL_GPOLYHL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CRC_GPOLYHL_GPOLYHL field.
-#define BR_CRC_GPOLYHL_GPOLYHL (HW_CRC_GPOLYHL.U)
-#endif
-
-//! @brief Format value for bitfield CRC_GPOLYHL_GPOLYHL.
-#define BF_CRC_GPOLYHL_GPOLYHL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_GPOLYHL_GPOLYHL), uint8_t) & BM_CRC_GPOLYHL_GPOLYHL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the GPOLYHL field to a new value.
-#define BW_CRC_GPOLYHL_GPOLYHL(v) (HW_CRC_GPOLYHL_WR(v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_CRC_GPOLYHU - CRC_GPOLYHU register.
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CRC_GPOLYHU - CRC_GPOLYHU register. (RW)
- *
- * Reset value: 0xFFU
- */
-typedef union _hw_crc_gpolyhu
-{
- uint8_t U;
- struct _hw_crc_gpolyhu_bitfields
- {
- uint8_t GPOLYHU : 8; //!< [7:0] POLYHU stores the fourth 8 bits of
- //! the 32 bit CRC
- } B;
-} hw_crc_gpolyhu_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CRC_GPOLYHU register
- */
-//@{
-#define HW_CRC_GPOLYHU_ADDR (REGS_CRC_BASE + 0x7U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CRC_GPOLYHU (*(__IO hw_crc_gpolyhu_t *) HW_CRC_GPOLYHU_ADDR)
-#define HW_CRC_GPOLYHU_RD() (HW_CRC_GPOLYHU.U)
-#define HW_CRC_GPOLYHU_WR(v) (HW_CRC_GPOLYHU.U = (v))
-#define HW_CRC_GPOLYHU_SET(v) (HW_CRC_GPOLYHU_WR(HW_CRC_GPOLYHU_RD() | (v)))
-#define HW_CRC_GPOLYHU_CLR(v) (HW_CRC_GPOLYHU_WR(HW_CRC_GPOLYHU_RD() & ~(v)))
-#define HW_CRC_GPOLYHU_TOG(v) (HW_CRC_GPOLYHU_WR(HW_CRC_GPOLYHU_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CRC_GPOLYHU bitfields
- */
-
-/*!
- * @name Register CRC_GPOLYHU, field GPOLYHU[7:0] (RW)
- */
-//@{
-#define BP_CRC_GPOLYHU_GPOLYHU (0U) //!< Bit position for CRC_GPOLYHU_GPOLYHU.
-#define BM_CRC_GPOLYHU_GPOLYHU (0xFFU) //!< Bit mask for CRC_GPOLYHU_GPOLYHU.
-#define BS_CRC_GPOLYHU_GPOLYHU (8U) //!< Bit field size in bits for CRC_GPOLYHU_GPOLYHU.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CRC_GPOLYHU_GPOLYHU field.
-#define BR_CRC_GPOLYHU_GPOLYHU (HW_CRC_GPOLYHU.U)
-#endif
-
-//! @brief Format value for bitfield CRC_GPOLYHU_GPOLYHU.
-#define BF_CRC_GPOLYHU_GPOLYHU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_GPOLYHU_GPOLYHU), uint8_t) & BM_CRC_GPOLYHU_GPOLYHU)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the GPOLYHU field to a new value.
-#define BW_CRC_GPOLYHU_GPOLYHU(v) (HW_CRC_GPOLYHU_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_CRC_CTRL - CRC Control register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CRC_CTRL - CRC Control register (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register controls the configuration and working of the CRC module.
- * Appropriate bits must be set before starting a new CRC calculation. A new CRC
- * calculation is initialized by asserting CTRL[WAS] and then writing the seed into
- * the CRC data register.
- */
-typedef union _hw_crc_ctrl
-{
- uint32_t U;
- struct _hw_crc_ctrl_bitfields
- {
- uint32_t RESERVED0 : 24; //!< [23:0]
- uint32_t TCRC : 1; //!< [24]
- uint32_t WAS : 1; //!< [25] Write CRC Data Register As Seed
- uint32_t FXOR : 1; //!< [26] Complement Read Of CRC Data Register
- uint32_t RESERVED1 : 1; //!< [27]
- uint32_t TOTR : 2; //!< [29:28] Type Of Transpose For Read
- uint32_t TOT : 2; //!< [31:30] Type Of Transpose For Writes
- } B;
-} hw_crc_ctrl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CRC_CTRL register
- */
-//@{
-#define HW_CRC_CTRL_ADDR (REGS_CRC_BASE + 0x8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CRC_CTRL (*(__IO hw_crc_ctrl_t *) HW_CRC_CTRL_ADDR)
-#define HW_CRC_CTRL_RD() (HW_CRC_CTRL.U)
-#define HW_CRC_CTRL_WR(v) (HW_CRC_CTRL.U = (v))
-#define HW_CRC_CTRL_SET(v) (HW_CRC_CTRL_WR(HW_CRC_CTRL_RD() | (v)))
-#define HW_CRC_CTRL_CLR(v) (HW_CRC_CTRL_WR(HW_CRC_CTRL_RD() & ~(v)))
-#define HW_CRC_CTRL_TOG(v) (HW_CRC_CTRL_WR(HW_CRC_CTRL_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CRC_CTRL bitfields
- */
-
-/*!
- * @name Register CRC_CTRL, field TCRC[24] (RW)
- *
- * Width of CRC protocol.
- *
- * Values:
- * - 0 - 16-bit CRC protocol.
- * - 1 - 32-bit CRC protocol.
- */
-//@{
-#define BP_CRC_CTRL_TCRC (24U) //!< Bit position for CRC_CTRL_TCRC.
-#define BM_CRC_CTRL_TCRC (0x01000000U) //!< Bit mask for CRC_CTRL_TCRC.
-#define BS_CRC_CTRL_TCRC (1U) //!< Bit field size in bits for CRC_CTRL_TCRC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CRC_CTRL_TCRC field.
-#define BR_CRC_CTRL_TCRC (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR, BP_CRC_CTRL_TCRC))
-#endif
-
-//! @brief Format value for bitfield CRC_CTRL_TCRC.
-#define BF_CRC_CTRL_TCRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_CTRL_TCRC), uint32_t) & BM_CRC_CTRL_TCRC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TCRC field to a new value.
-#define BW_CRC_CTRL_TCRC(v) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR, BP_CRC_CTRL_TCRC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CRC_CTRL, field WAS[25] (RW)
- *
- * When asserted, a value written to the CRC data register is considered a seed
- * value. When deasserted, a value written to the CRC data register is taken as
- * data for CRC computation.
- *
- * Values:
- * - 0 - Writes to the CRC data register are data values.
- * - 1 - Writes to the CRC data register are seed values.
- */
-//@{
-#define BP_CRC_CTRL_WAS (25U) //!< Bit position for CRC_CTRL_WAS.
-#define BM_CRC_CTRL_WAS (0x02000000U) //!< Bit mask for CRC_CTRL_WAS.
-#define BS_CRC_CTRL_WAS (1U) //!< Bit field size in bits for CRC_CTRL_WAS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CRC_CTRL_WAS field.
-#define BR_CRC_CTRL_WAS (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR, BP_CRC_CTRL_WAS))
-#endif
-
-//! @brief Format value for bitfield CRC_CTRL_WAS.
-#define BF_CRC_CTRL_WAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_CTRL_WAS), uint32_t) & BM_CRC_CTRL_WAS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WAS field to a new value.
-#define BW_CRC_CTRL_WAS(v) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR, BP_CRC_CTRL_WAS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CRC_CTRL, field FXOR[26] (RW)
- *
- * Some CRC protocols require the final checksum to be XORed with 0xFFFFFFFF or
- * 0xFFFF. Asserting this bit enables on the fly complementing of read data.
- *
- * Values:
- * - 0 - No XOR on reading.
- * - 1 - Invert or complement the read value of the CRC Data register.
- */
-//@{
-#define BP_CRC_CTRL_FXOR (26U) //!< Bit position for CRC_CTRL_FXOR.
-#define BM_CRC_CTRL_FXOR (0x04000000U) //!< Bit mask for CRC_CTRL_FXOR.
-#define BS_CRC_CTRL_FXOR (1U) //!< Bit field size in bits for CRC_CTRL_FXOR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CRC_CTRL_FXOR field.
-#define BR_CRC_CTRL_FXOR (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR, BP_CRC_CTRL_FXOR))
-#endif
-
-//! @brief Format value for bitfield CRC_CTRL_FXOR.
-#define BF_CRC_CTRL_FXOR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_CTRL_FXOR), uint32_t) & BM_CRC_CTRL_FXOR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FXOR field to a new value.
-#define BW_CRC_CTRL_FXOR(v) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR, BP_CRC_CTRL_FXOR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CRC_CTRL, field TOTR[29:28] (RW)
- *
- * Identifies the transpose configuration of the value read from the CRC Data
- * register. See the description of the transpose feature for the available
- * transpose options.
- *
- * Values:
- * - 00 - No transposition.
- * - 01 - Bits in bytes are transposed; bytes are not transposed.
- * - 10 - Both bits in bytes and bytes are transposed.
- * - 11 - Only bytes are transposed; no bits in a byte are transposed.
- */
-//@{
-#define BP_CRC_CTRL_TOTR (28U) //!< Bit position for CRC_CTRL_TOTR.
-#define BM_CRC_CTRL_TOTR (0x30000000U) //!< Bit mask for CRC_CTRL_TOTR.
-#define BS_CRC_CTRL_TOTR (2U) //!< Bit field size in bits for CRC_CTRL_TOTR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CRC_CTRL_TOTR field.
-#define BR_CRC_CTRL_TOTR (HW_CRC_CTRL.B.TOTR)
-#endif
-
-//! @brief Format value for bitfield CRC_CTRL_TOTR.
-#define BF_CRC_CTRL_TOTR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_CTRL_TOTR), uint32_t) & BM_CRC_CTRL_TOTR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TOTR field to a new value.
-#define BW_CRC_CTRL_TOTR(v) (HW_CRC_CTRL_WR((HW_CRC_CTRL_RD() & ~BM_CRC_CTRL_TOTR) | BF_CRC_CTRL_TOTR(v)))
-#endif
-//@}
-
-/*!
- * @name Register CRC_CTRL, field TOT[31:30] (RW)
- *
- * Defines the transpose configuration of the data written to the CRC data
- * register. See the description of the transpose feature for the available transpose
- * options.
- *
- * Values:
- * - 00 - No transposition.
- * - 01 - Bits in bytes are transposed; bytes are not transposed.
- * - 10 - Both bits in bytes and bytes are transposed.
- * - 11 - Only bytes are transposed; no bits in a byte are transposed.
- */
-//@{
-#define BP_CRC_CTRL_TOT (30U) //!< Bit position for CRC_CTRL_TOT.
-#define BM_CRC_CTRL_TOT (0xC0000000U) //!< Bit mask for CRC_CTRL_TOT.
-#define BS_CRC_CTRL_TOT (2U) //!< Bit field size in bits for CRC_CTRL_TOT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CRC_CTRL_TOT field.
-#define BR_CRC_CTRL_TOT (HW_CRC_CTRL.B.TOT)
-#endif
-
-//! @brief Format value for bitfield CRC_CTRL_TOT.
-#define BF_CRC_CTRL_TOT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_CTRL_TOT), uint32_t) & BM_CRC_CTRL_TOT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TOT field to a new value.
-#define BW_CRC_CTRL_TOT(v) (HW_CRC_CTRL_WR((HW_CRC_CTRL_RD() & ~BM_CRC_CTRL_TOT) | BF_CRC_CTRL_TOT(v)))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_CRC_CTRLHU - CRC_CTRLHU register.
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_CRC_CTRLHU - CRC_CTRLHU register. (RW)
- *
- * Reset value: 0x00U
- */
-typedef union _hw_crc_ctrlhu
-{
- uint8_t U;
- struct _hw_crc_ctrlhu_bitfields
- {
- uint8_t TCRC : 1; //!< [0]
- uint8_t WAS : 1; //!< [1]
- uint8_t FXOR : 1; //!< [2]
- uint8_t RESERVED0 : 1; //!< [3]
- uint8_t TOTR : 2; //!< [5:4]
- uint8_t TOT : 2; //!< [7:6]
- } B;
-} hw_crc_ctrlhu_t;
-#endif
-
-/*!
- * @name Constants and macros for entire CRC_CTRLHU register
- */
-//@{
-#define HW_CRC_CTRLHU_ADDR (REGS_CRC_BASE + 0xBU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_CRC_CTRLHU (*(__IO hw_crc_ctrlhu_t *) HW_CRC_CTRLHU_ADDR)
-#define HW_CRC_CTRLHU_RD() (HW_CRC_CTRLHU.U)
-#define HW_CRC_CTRLHU_WR(v) (HW_CRC_CTRLHU.U = (v))
-#define HW_CRC_CTRLHU_SET(v) (HW_CRC_CTRLHU_WR(HW_CRC_CTRLHU_RD() | (v)))
-#define HW_CRC_CTRLHU_CLR(v) (HW_CRC_CTRLHU_WR(HW_CRC_CTRLHU_RD() & ~(v)))
-#define HW_CRC_CTRLHU_TOG(v) (HW_CRC_CTRLHU_WR(HW_CRC_CTRLHU_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual CRC_CTRLHU bitfields
- */
-
-/*!
- * @name Register CRC_CTRLHU, field TCRC[0] (RW)
- *
- * Values:
- * - 0 - 16-bit CRC protocol.
- * - 1 - 32-bit CRC protocol.
- */
-//@{
-#define BP_CRC_CTRLHU_TCRC (0U) //!< Bit position for CRC_CTRLHU_TCRC.
-#define BM_CRC_CTRLHU_TCRC (0x01U) //!< Bit mask for CRC_CTRLHU_TCRC.
-#define BS_CRC_CTRLHU_TCRC (1U) //!< Bit field size in bits for CRC_CTRLHU_TCRC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CRC_CTRLHU_TCRC field.
-#define BR_CRC_CTRLHU_TCRC (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR, BP_CRC_CTRLHU_TCRC))
-#endif
-
-//! @brief Format value for bitfield CRC_CTRLHU_TCRC.
-#define BF_CRC_CTRLHU_TCRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_CTRLHU_TCRC), uint8_t) & BM_CRC_CTRLHU_TCRC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TCRC field to a new value.
-#define BW_CRC_CTRLHU_TCRC(v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR, BP_CRC_CTRLHU_TCRC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CRC_CTRLHU, field WAS[1] (RW)
- *
- * Values:
- * - 0 - Writes to CRC data register are data values.
- * - 1 - Writes to CRC data reguster are seed values.
- */
-//@{
-#define BP_CRC_CTRLHU_WAS (1U) //!< Bit position for CRC_CTRLHU_WAS.
-#define BM_CRC_CTRLHU_WAS (0x02U) //!< Bit mask for CRC_CTRLHU_WAS.
-#define BS_CRC_CTRLHU_WAS (1U) //!< Bit field size in bits for CRC_CTRLHU_WAS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CRC_CTRLHU_WAS field.
-#define BR_CRC_CTRLHU_WAS (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR, BP_CRC_CTRLHU_WAS))
-#endif
-
-//! @brief Format value for bitfield CRC_CTRLHU_WAS.
-#define BF_CRC_CTRLHU_WAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_CTRLHU_WAS), uint8_t) & BM_CRC_CTRLHU_WAS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WAS field to a new value.
-#define BW_CRC_CTRLHU_WAS(v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR, BP_CRC_CTRLHU_WAS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CRC_CTRLHU, field FXOR[2] (RW)
- *
- * Values:
- * - 0 - No XOR on reading.
- * - 1 - Invert or complement the read value of CRC data register.
- */
-//@{
-#define BP_CRC_CTRLHU_FXOR (2U) //!< Bit position for CRC_CTRLHU_FXOR.
-#define BM_CRC_CTRLHU_FXOR (0x04U) //!< Bit mask for CRC_CTRLHU_FXOR.
-#define BS_CRC_CTRLHU_FXOR (1U) //!< Bit field size in bits for CRC_CTRLHU_FXOR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CRC_CTRLHU_FXOR field.
-#define BR_CRC_CTRLHU_FXOR (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR, BP_CRC_CTRLHU_FXOR))
-#endif
-
-//! @brief Format value for bitfield CRC_CTRLHU_FXOR.
-#define BF_CRC_CTRLHU_FXOR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_CTRLHU_FXOR), uint8_t) & BM_CRC_CTRLHU_FXOR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FXOR field to a new value.
-#define BW_CRC_CTRLHU_FXOR(v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR, BP_CRC_CTRLHU_FXOR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register CRC_CTRLHU, field TOTR[5:4] (RW)
- *
- * Values:
- * - 00 - No Transposition.
- * - 01 - Bits in bytes are transposed, bytes are not transposed.
- * - 10 - Both bits in bytes and bytes are transposed.
- * - 11 - Only bytes are transposed; no bits in a byte are transposed.
- */
-//@{
-#define BP_CRC_CTRLHU_TOTR (4U) //!< Bit position for CRC_CTRLHU_TOTR.
-#define BM_CRC_CTRLHU_TOTR (0x30U) //!< Bit mask for CRC_CTRLHU_TOTR.
-#define BS_CRC_CTRLHU_TOTR (2U) //!< Bit field size in bits for CRC_CTRLHU_TOTR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CRC_CTRLHU_TOTR field.
-#define BR_CRC_CTRLHU_TOTR (HW_CRC_CTRLHU.B.TOTR)
-#endif
-
-//! @brief Format value for bitfield CRC_CTRLHU_TOTR.
-#define BF_CRC_CTRLHU_TOTR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_CTRLHU_TOTR), uint8_t) & BM_CRC_CTRLHU_TOTR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TOTR field to a new value.
-#define BW_CRC_CTRLHU_TOTR(v) (HW_CRC_CTRLHU_WR((HW_CRC_CTRLHU_RD() & ~BM_CRC_CTRLHU_TOTR) | BF_CRC_CTRLHU_TOTR(v)))
-#endif
-//@}
-
-/*!
- * @name Register CRC_CTRLHU, field TOT[7:6] (RW)
- *
- * Values:
- * - 00 - No Transposition.
- * - 01 - Bits in bytes are transposed, bytes are not transposed.
- * - 10 - Both bits in bytes and bytes are transposed.
- * - 11 - Only bytes are transposed; no bits in a byte are transposed.
- */
-//@{
-#define BP_CRC_CTRLHU_TOT (6U) //!< Bit position for CRC_CTRLHU_TOT.
-#define BM_CRC_CTRLHU_TOT (0xC0U) //!< Bit mask for CRC_CTRLHU_TOT.
-#define BS_CRC_CTRLHU_TOT (2U) //!< Bit field size in bits for CRC_CTRLHU_TOT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the CRC_CTRLHU_TOT field.
-#define BR_CRC_CTRLHU_TOT (HW_CRC_CTRLHU.B.TOT)
-#endif
-
-//! @brief Format value for bitfield CRC_CTRLHU_TOT.
-#define BF_CRC_CTRLHU_TOT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_CTRLHU_TOT), uint8_t) & BM_CRC_CTRLHU_TOT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TOT field to a new value.
-#define BW_CRC_CTRLHU_TOT(v) (HW_CRC_CTRLHU_WR((HW_CRC_CTRLHU_RD() & ~BM_CRC_CTRLHU_TOT) | BF_CRC_CTRLHU_TOT(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_crc_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All CRC module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_crc
-{
- union {
- struct {
- __IO hw_crc_datal_t DATAL; //!< [0x0] CRC_DATAL register.
- __IO hw_crc_datah_t DATAH; //!< [0x2] CRC_DATAH register.
- } ACCESS16BIT;
- struct {
- __IO hw_crc_datall_t DATALL; //!< [0x0] CRC_DATALL register.
- __IO hw_crc_datalu_t DATALU; //!< [0x1] CRC_DATALU register.
- __IO hw_crc_datahl_t DATAHL; //!< [0x2] CRC_DATAHL register.
- __IO hw_crc_datahu_t DATAHU; //!< [0x3] CRC_DATAHU register.
- } ACCESS8BIT;
- __IO hw_crc_data_t DATA; //!< [0x0] CRC Data register
- };
- union {
- __IO hw_crc_gpoly_t GPOLY; //!< [0x4] CRC Polynomial register
- struct {
- __IO hw_crc_gpolyl_t GPOLYL; //!< [0x4] CRC_GPOLYL register.
- __IO hw_crc_gpolyh_t GPOLYH; //!< [0x6] CRC_GPOLYH register.
- } GPOLY_ACCESS16BIT;
- struct {
- __IO hw_crc_gpolyll_t GPOLYLL; //!< [0x4] CRC_GPOLYLL register.
- __IO hw_crc_gpolylu_t GPOLYLU; //!< [0x5] CRC_GPOLYLU register.
- __IO hw_crc_gpolyhl_t GPOLYHL; //!< [0x6] CRC_GPOLYHL register.
- __IO hw_crc_gpolyhu_t GPOLYHU; //!< [0x7] CRC_GPOLYHU register.
- } GPOLY_ACCESS8BIT;
- };
- union {
- __IO hw_crc_ctrl_t CTRL; //!< [0x8] CRC Control register
- struct {
- uint8_t _reserved0[3];
- __IO hw_crc_ctrlhu_t CTRLHU; //!< [0xB] CRC_CTRLHU register.
- } CTRL_ACCESS8BIT;
- };
-} hw_crc_t;
-#pragma pack()
-
-//! @brief Macro to access all CRC registers.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_CRC</code>.
-#define HW_CRC (*(hw_crc_t *) REGS_CRC_BASE)
-#endif
-
-#endif // __HW_CRC_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_dac.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,879 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_DAC_REGISTERS_H__
-#define __HW_DAC_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 DAC
- *
- * 12-Bit Digital-to-Analog Converter
- *
- * Registers defined in this header file:
- * - HW_DAC_DATnL - DAC Data Low Register
- * - HW_DAC_DATnH - DAC Data High Register
- * - HW_DAC_SR - DAC Status Register
- * - HW_DAC_C0 - DAC Control Register
- * - HW_DAC_C1 - DAC Control Register 1
- * - HW_DAC_C2 - DAC Control Register 2
- *
- * - hw_dac_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_DAC_BASE
-#define HW_DAC_INSTANCE_COUNT (2U) //!< Number of instances of the DAC module.
-#define HW_DAC0 (0U) //!< Instance number for DAC0.
-#define HW_DAC1 (1U) //!< Instance number for DAC1.
-#define REGS_DAC0_BASE (0x400CC000U) //!< Base address for DAC0.
-#define REGS_DAC1_BASE (0x400CD000U) //!< Base address for DAC1.
-
-//! @brief Table of base addresses for DAC instances.
-static const uint32_t __g_regs_DAC_base_addresses[] = {
- REGS_DAC0_BASE,
- REGS_DAC1_BASE,
- };
-
-//! @brief Get the base address of DAC by instance number.
-//! @param x DAC instance number, from 0 through 1.
-#define REGS_DAC_BASE(x) (__g_regs_DAC_base_addresses[(x)])
-
-//! @brief Get the instance number given a base address.
-//! @param b Base address for an instance of DAC.
-#define REGS_DAC_INSTANCE(b) ((b) == REGS_DAC0_BASE ? HW_DAC0 : (b) == REGS_DAC1_BASE ? HW_DAC1 : 0)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_DAC_DATnL - DAC Data Low Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DAC_DATnL - DAC Data Low Register (RW)
- *
- * Reset value: 0x00U
- */
-typedef union _hw_dac_datnl
-{
- uint8_t U;
- struct _hw_dac_datnl_bitfields
- {
- uint8_t DATA0 : 8; //!< [7:0]
- } B;
-} hw_dac_datnl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DAC_DATnL register
- */
-//@{
-#define HW_DAC_DATnL_COUNT (16U)
-
-#define HW_DAC_DATnL_ADDR(x, n) (REGS_DAC_BASE(x) + 0x0U + (0x2U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DAC_DATnL(x, n) (*(__IO hw_dac_datnl_t *) HW_DAC_DATnL_ADDR(x, n))
-#define HW_DAC_DATnL_RD(x, n) (HW_DAC_DATnL(x, n).U)
-#define HW_DAC_DATnL_WR(x, n, v) (HW_DAC_DATnL(x, n).U = (v))
-#define HW_DAC_DATnL_SET(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) | (v)))
-#define HW_DAC_DATnL_CLR(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) & ~(v)))
-#define HW_DAC_DATnL_TOG(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DAC_DATnL bitfields
- */
-
-/*!
- * @name Register DAC_DATnL, field DATA0[7:0] (RW)
- *
- * When the DAC buffer is not enabled, DATA[11:0] controls the output voltage
- * based on the following formula: V out = V in * (1 + DACDAT0[11:0])/4096 When the
- * DAC buffer is enabled, DATA is mapped to the 16-word buffer.
- */
-//@{
-#define BP_DAC_DATnL_DATA0 (0U) //!< Bit position for DAC_DATnL_DATA0.
-#define BM_DAC_DATnL_DATA0 (0xFFU) //!< Bit mask for DAC_DATnL_DATA0.
-#define BS_DAC_DATnL_DATA0 (8U) //!< Bit field size in bits for DAC_DATnL_DATA0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DAC_DATnL_DATA0 field.
-#define BR_DAC_DATnL_DATA0(x, n) (HW_DAC_DATnL(x, n).U)
-#endif
-
-//! @brief Format value for bitfield DAC_DATnL_DATA0.
-#define BF_DAC_DATnL_DATA0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_DATnL_DATA0), uint8_t) & BM_DAC_DATnL_DATA0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DATA0 field to a new value.
-#define BW_DAC_DATnL_DATA0(x, n, v) (HW_DAC_DATnL_WR(x, n, v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_DAC_DATnH - DAC Data High Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DAC_DATnH - DAC Data High Register (RW)
- *
- * Reset value: 0x00U
- */
-typedef union _hw_dac_datnh
-{
- uint8_t U;
- struct _hw_dac_datnh_bitfields
- {
- uint8_t DATA1 : 4; //!< [3:0]
- uint8_t RESERVED0 : 4; //!< [7:4]
- } B;
-} hw_dac_datnh_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DAC_DATnH register
- */
-//@{
-#define HW_DAC_DATnH_COUNT (16U)
-
-#define HW_DAC_DATnH_ADDR(x, n) (REGS_DAC_BASE(x) + 0x1U + (0x2U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DAC_DATnH(x, n) (*(__IO hw_dac_datnh_t *) HW_DAC_DATnH_ADDR(x, n))
-#define HW_DAC_DATnH_RD(x, n) (HW_DAC_DATnH(x, n).U)
-#define HW_DAC_DATnH_WR(x, n, v) (HW_DAC_DATnH(x, n).U = (v))
-#define HW_DAC_DATnH_SET(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) | (v)))
-#define HW_DAC_DATnH_CLR(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) & ~(v)))
-#define HW_DAC_DATnH_TOG(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DAC_DATnH bitfields
- */
-
-/*!
- * @name Register DAC_DATnH, field DATA1[3:0] (RW)
- *
- * When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage
- * based on the following formula. V out = V in * (1 + DACDAT0[11:0])/4096 When the
- * DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer.
- */
-//@{
-#define BP_DAC_DATnH_DATA1 (0U) //!< Bit position for DAC_DATnH_DATA1.
-#define BM_DAC_DATnH_DATA1 (0x0FU) //!< Bit mask for DAC_DATnH_DATA1.
-#define BS_DAC_DATnH_DATA1 (4U) //!< Bit field size in bits for DAC_DATnH_DATA1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DAC_DATnH_DATA1 field.
-#define BR_DAC_DATnH_DATA1(x, n) (HW_DAC_DATnH(x, n).B.DATA1)
-#endif
-
-//! @brief Format value for bitfield DAC_DATnH_DATA1.
-#define BF_DAC_DATnH_DATA1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_DATnH_DATA1), uint8_t) & BM_DAC_DATnH_DATA1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DATA1 field to a new value.
-#define BW_DAC_DATnH_DATA1(x, n, v) (HW_DAC_DATnH_WR(x, n, (HW_DAC_DATnH_RD(x, n) & ~BM_DAC_DATnH_DATA1) | BF_DAC_DATnH_DATA1(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_DAC_SR - DAC Status Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DAC_SR - DAC Status Register (RW)
- *
- * Reset value: 0x02U
- *
- * If DMA is enabled, the flags can be cleared automatically by DMA when the DMA
- * request is done. Writing 0 to a field clears it whereas writing 1 has no
- * effect. After reset, DACBFRPTF is set and can be cleared by software, if needed.
- * The flags are set only when the data buffer status is changed. Do not use
- * 32/16-bit accesses to this register.
- */
-typedef union _hw_dac_sr
-{
- uint8_t U;
- struct _hw_dac_sr_bitfields
- {
- uint8_t DACBFRPBF : 1; //!< [0] DAC Buffer Read Pointer Bottom
- //! Position Flag
- uint8_t DACBFRPTF : 1; //!< [1] DAC Buffer Read Pointer Top Position
- //! Flag
- uint8_t DACBFWMF : 1; //!< [2] DAC Buffer Watermark Flag
- uint8_t RESERVED0 : 5; //!< [7:3]
- } B;
-} hw_dac_sr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DAC_SR register
- */
-//@{
-#define HW_DAC_SR_ADDR(x) (REGS_DAC_BASE(x) + 0x20U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DAC_SR(x) (*(__IO hw_dac_sr_t *) HW_DAC_SR_ADDR(x))
-#define HW_DAC_SR_RD(x) (HW_DAC_SR(x).U)
-#define HW_DAC_SR_WR(x, v) (HW_DAC_SR(x).U = (v))
-#define HW_DAC_SR_SET(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) | (v)))
-#define HW_DAC_SR_CLR(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) & ~(v)))
-#define HW_DAC_SR_TOG(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DAC_SR bitfields
- */
-
-/*!
- * @name Register DAC_SR, field DACBFRPBF[0] (RW)
- *
- * Values:
- * - 0 - The DAC buffer read pointer is not equal to C2[DACBFUP].
- * - 1 - The DAC buffer read pointer is equal to C2[DACBFUP].
- */
-//@{
-#define BP_DAC_SR_DACBFRPBF (0U) //!< Bit position for DAC_SR_DACBFRPBF.
-#define BM_DAC_SR_DACBFRPBF (0x01U) //!< Bit mask for DAC_SR_DACBFRPBF.
-#define BS_DAC_SR_DACBFRPBF (1U) //!< Bit field size in bits for DAC_SR_DACBFRPBF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DAC_SR_DACBFRPBF field.
-#define BR_DAC_SR_DACBFRPBF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF))
-#endif
-
-//! @brief Format value for bitfield DAC_SR_DACBFRPBF.
-#define BF_DAC_SR_DACBFRPBF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_SR_DACBFRPBF), uint8_t) & BM_DAC_SR_DACBFRPBF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DACBFRPBF field to a new value.
-#define BW_DAC_SR_DACBFRPBF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DAC_SR, field DACBFRPTF[1] (RW)
- *
- * Values:
- * - 0 - The DAC buffer read pointer is not zero.
- * - 1 - The DAC buffer read pointer is zero.
- */
-//@{
-#define BP_DAC_SR_DACBFRPTF (1U) //!< Bit position for DAC_SR_DACBFRPTF.
-#define BM_DAC_SR_DACBFRPTF (0x02U) //!< Bit mask for DAC_SR_DACBFRPTF.
-#define BS_DAC_SR_DACBFRPTF (1U) //!< Bit field size in bits for DAC_SR_DACBFRPTF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DAC_SR_DACBFRPTF field.
-#define BR_DAC_SR_DACBFRPTF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF))
-#endif
-
-//! @brief Format value for bitfield DAC_SR_DACBFRPTF.
-#define BF_DAC_SR_DACBFRPTF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_SR_DACBFRPTF), uint8_t) & BM_DAC_SR_DACBFRPTF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DACBFRPTF field to a new value.
-#define BW_DAC_SR_DACBFRPTF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DAC_SR, field DACBFWMF[2] (RW)
- *
- * Values:
- * - 0 - The DAC buffer read pointer has not reached the watermark level.
- * - 1 - The DAC buffer read pointer has reached the watermark level.
- */
-//@{
-#define BP_DAC_SR_DACBFWMF (2U) //!< Bit position for DAC_SR_DACBFWMF.
-#define BM_DAC_SR_DACBFWMF (0x04U) //!< Bit mask for DAC_SR_DACBFWMF.
-#define BS_DAC_SR_DACBFWMF (1U) //!< Bit field size in bits for DAC_SR_DACBFWMF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DAC_SR_DACBFWMF field.
-#define BR_DAC_SR_DACBFWMF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF))
-#endif
-
-//! @brief Format value for bitfield DAC_SR_DACBFWMF.
-#define BF_DAC_SR_DACBFWMF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_SR_DACBFWMF), uint8_t) & BM_DAC_SR_DACBFWMF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DACBFWMF field to a new value.
-#define BW_DAC_SR_DACBFWMF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_DAC_C0 - DAC Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DAC_C0 - DAC Control Register (RW)
- *
- * Reset value: 0x00U
- *
- * Do not use 32- or 16-bit accesses to this register.
- */
-typedef union _hw_dac_c0
-{
- uint8_t U;
- struct _hw_dac_c0_bitfields
- {
- uint8_t DACBBIEN : 1; //!< [0] DAC Buffer Read Pointer Bottom Flag
- //! Interrupt Enable
- uint8_t DACBTIEN : 1; //!< [1] DAC Buffer Read Pointer Top Flag
- //! Interrupt Enable
- uint8_t DACBWIEN : 1; //!< [2] DAC Buffer Watermark Interrupt Enable
- uint8_t LPEN : 1; //!< [3] DAC Low Power Control
- uint8_t DACSWTRG : 1; //!< [4] DAC Software Trigger
- uint8_t DACTRGSEL : 1; //!< [5] DAC Trigger Select
- uint8_t DACRFS : 1; //!< [6] DAC Reference Select
- uint8_t DACEN : 1; //!< [7] DAC Enable
- } B;
-} hw_dac_c0_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DAC_C0 register
- */
-//@{
-#define HW_DAC_C0_ADDR(x) (REGS_DAC_BASE(x) + 0x21U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DAC_C0(x) (*(__IO hw_dac_c0_t *) HW_DAC_C0_ADDR(x))
-#define HW_DAC_C0_RD(x) (HW_DAC_C0(x).U)
-#define HW_DAC_C0_WR(x, v) (HW_DAC_C0(x).U = (v))
-#define HW_DAC_C0_SET(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) | (v)))
-#define HW_DAC_C0_CLR(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) & ~(v)))
-#define HW_DAC_C0_TOG(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DAC_C0 bitfields
- */
-
-/*!
- * @name Register DAC_C0, field DACBBIEN[0] (RW)
- *
- * Values:
- * - 0 - The DAC buffer read pointer bottom flag interrupt is disabled.
- * - 1 - The DAC buffer read pointer bottom flag interrupt is enabled.
- */
-//@{
-#define BP_DAC_C0_DACBBIEN (0U) //!< Bit position for DAC_C0_DACBBIEN.
-#define BM_DAC_C0_DACBBIEN (0x01U) //!< Bit mask for DAC_C0_DACBBIEN.
-#define BS_DAC_C0_DACBBIEN (1U) //!< Bit field size in bits for DAC_C0_DACBBIEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DAC_C0_DACBBIEN field.
-#define BR_DAC_C0_DACBBIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN))
-#endif
-
-//! @brief Format value for bitfield DAC_C0_DACBBIEN.
-#define BF_DAC_C0_DACBBIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACBBIEN), uint8_t) & BM_DAC_C0_DACBBIEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DACBBIEN field to a new value.
-#define BW_DAC_C0_DACBBIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DAC_C0, field DACBTIEN[1] (RW)
- *
- * Values:
- * - 0 - The DAC buffer read pointer top flag interrupt is disabled.
- * - 1 - The DAC buffer read pointer top flag interrupt is enabled.
- */
-//@{
-#define BP_DAC_C0_DACBTIEN (1U) //!< Bit position for DAC_C0_DACBTIEN.
-#define BM_DAC_C0_DACBTIEN (0x02U) //!< Bit mask for DAC_C0_DACBTIEN.
-#define BS_DAC_C0_DACBTIEN (1U) //!< Bit field size in bits for DAC_C0_DACBTIEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DAC_C0_DACBTIEN field.
-#define BR_DAC_C0_DACBTIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN))
-#endif
-
-//! @brief Format value for bitfield DAC_C0_DACBTIEN.
-#define BF_DAC_C0_DACBTIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACBTIEN), uint8_t) & BM_DAC_C0_DACBTIEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DACBTIEN field to a new value.
-#define BW_DAC_C0_DACBTIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DAC_C0, field DACBWIEN[2] (RW)
- *
- * Values:
- * - 0 - The DAC buffer watermark interrupt is disabled.
- * - 1 - The DAC buffer watermark interrupt is enabled.
- */
-//@{
-#define BP_DAC_C0_DACBWIEN (2U) //!< Bit position for DAC_C0_DACBWIEN.
-#define BM_DAC_C0_DACBWIEN (0x04U) //!< Bit mask for DAC_C0_DACBWIEN.
-#define BS_DAC_C0_DACBWIEN (1U) //!< Bit field size in bits for DAC_C0_DACBWIEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DAC_C0_DACBWIEN field.
-#define BR_DAC_C0_DACBWIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN))
-#endif
-
-//! @brief Format value for bitfield DAC_C0_DACBWIEN.
-#define BF_DAC_C0_DACBWIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACBWIEN), uint8_t) & BM_DAC_C0_DACBWIEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DACBWIEN field to a new value.
-#define BW_DAC_C0_DACBWIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DAC_C0, field LPEN[3] (RW)
- *
- * See the 12-bit DAC electrical characteristics of the device data sheet for
- * details on the impact of the modes below.
- *
- * Values:
- * - 0 - High-Power mode
- * - 1 - Low-Power mode
- */
-//@{
-#define BP_DAC_C0_LPEN (3U) //!< Bit position for DAC_C0_LPEN.
-#define BM_DAC_C0_LPEN (0x08U) //!< Bit mask for DAC_C0_LPEN.
-#define BS_DAC_C0_LPEN (1U) //!< Bit field size in bits for DAC_C0_LPEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DAC_C0_LPEN field.
-#define BR_DAC_C0_LPEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN))
-#endif
-
-//! @brief Format value for bitfield DAC_C0_LPEN.
-#define BF_DAC_C0_LPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_LPEN), uint8_t) & BM_DAC_C0_LPEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LPEN field to a new value.
-#define BW_DAC_C0_LPEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DAC_C0, field DACSWTRG[4] (WORZ)
- *
- * Active high. This is a write-only field, which always reads 0. If DAC
- * software trigger is selected and buffer is enabled, writing 1 to this field will
- * advance the buffer read pointer once.
- *
- * Values:
- * - 0 - The DAC soft trigger is not valid.
- * - 1 - The DAC soft trigger is valid.
- */
-//@{
-#define BP_DAC_C0_DACSWTRG (4U) //!< Bit position for DAC_C0_DACSWTRG.
-#define BM_DAC_C0_DACSWTRG (0x10U) //!< Bit mask for DAC_C0_DACSWTRG.
-#define BS_DAC_C0_DACSWTRG (1U) //!< Bit field size in bits for DAC_C0_DACSWTRG.
-
-//! @brief Format value for bitfield DAC_C0_DACSWTRG.
-#define BF_DAC_C0_DACSWTRG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACSWTRG), uint8_t) & BM_DAC_C0_DACSWTRG)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DACSWTRG field to a new value.
-#define BW_DAC_C0_DACSWTRG(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACSWTRG) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DAC_C0, field DACTRGSEL[5] (RW)
- *
- * Values:
- * - 0 - The DAC hardware trigger is selected.
- * - 1 - The DAC software trigger is selected.
- */
-//@{
-#define BP_DAC_C0_DACTRGSEL (5U) //!< Bit position for DAC_C0_DACTRGSEL.
-#define BM_DAC_C0_DACTRGSEL (0x20U) //!< Bit mask for DAC_C0_DACTRGSEL.
-#define BS_DAC_C0_DACTRGSEL (1U) //!< Bit field size in bits for DAC_C0_DACTRGSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DAC_C0_DACTRGSEL field.
-#define BR_DAC_C0_DACTRGSEL(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL))
-#endif
-
-//! @brief Format value for bitfield DAC_C0_DACTRGSEL.
-#define BF_DAC_C0_DACTRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACTRGSEL), uint8_t) & BM_DAC_C0_DACTRGSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DACTRGSEL field to a new value.
-#define BW_DAC_C0_DACTRGSEL(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DAC_C0, field DACRFS[6] (RW)
- *
- * Values:
- * - 0 - The DAC selects DACREF_1 as the reference voltage.
- * - 1 - The DAC selects DACREF_2 as the reference voltage.
- */
-//@{
-#define BP_DAC_C0_DACRFS (6U) //!< Bit position for DAC_C0_DACRFS.
-#define BM_DAC_C0_DACRFS (0x40U) //!< Bit mask for DAC_C0_DACRFS.
-#define BS_DAC_C0_DACRFS (1U) //!< Bit field size in bits for DAC_C0_DACRFS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DAC_C0_DACRFS field.
-#define BR_DAC_C0_DACRFS(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS))
-#endif
-
-//! @brief Format value for bitfield DAC_C0_DACRFS.
-#define BF_DAC_C0_DACRFS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACRFS), uint8_t) & BM_DAC_C0_DACRFS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DACRFS field to a new value.
-#define BW_DAC_C0_DACRFS(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DAC_C0, field DACEN[7] (RW)
- *
- * Starts the Programmable Reference Generator operation.
- *
- * Values:
- * - 0 - The DAC system is disabled.
- * - 1 - The DAC system is enabled.
- */
-//@{
-#define BP_DAC_C0_DACEN (7U) //!< Bit position for DAC_C0_DACEN.
-#define BM_DAC_C0_DACEN (0x80U) //!< Bit mask for DAC_C0_DACEN.
-#define BS_DAC_C0_DACEN (1U) //!< Bit field size in bits for DAC_C0_DACEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DAC_C0_DACEN field.
-#define BR_DAC_C0_DACEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN))
-#endif
-
-//! @brief Format value for bitfield DAC_C0_DACEN.
-#define BF_DAC_C0_DACEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACEN), uint8_t) & BM_DAC_C0_DACEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DACEN field to a new value.
-#define BW_DAC_C0_DACEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_DAC_C1 - DAC Control Register 1
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DAC_C1 - DAC Control Register 1 (RW)
- *
- * Reset value: 0x00U
- *
- * Do not use 32- or 16-bit accesses to this register.
- */
-typedef union _hw_dac_c1
-{
- uint8_t U;
- struct _hw_dac_c1_bitfields
- {
- uint8_t DACBFEN : 1; //!< [0] DAC Buffer Enable
- uint8_t DACBFMD : 2; //!< [2:1] DAC Buffer Work Mode Select
- uint8_t DACBFWM : 2; //!< [4:3] DAC Buffer Watermark Select
- uint8_t RESERVED0 : 2; //!< [6:5]
- uint8_t DMAEN : 1; //!< [7] DMA Enable Select
- } B;
-} hw_dac_c1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DAC_C1 register
- */
-//@{
-#define HW_DAC_C1_ADDR(x) (REGS_DAC_BASE(x) + 0x22U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DAC_C1(x) (*(__IO hw_dac_c1_t *) HW_DAC_C1_ADDR(x))
-#define HW_DAC_C1_RD(x) (HW_DAC_C1(x).U)
-#define HW_DAC_C1_WR(x, v) (HW_DAC_C1(x).U = (v))
-#define HW_DAC_C1_SET(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) | (v)))
-#define HW_DAC_C1_CLR(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) & ~(v)))
-#define HW_DAC_C1_TOG(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DAC_C1 bitfields
- */
-
-/*!
- * @name Register DAC_C1, field DACBFEN[0] (RW)
- *
- * Values:
- * - 0 - Buffer read pointer is disabled. The converted data is always the first
- * word of the buffer.
- * - 1 - Buffer read pointer is enabled. The converted data is the word that the
- * read pointer points to. It means converted data can be from any word of
- * the buffer.
- */
-//@{
-#define BP_DAC_C1_DACBFEN (0U) //!< Bit position for DAC_C1_DACBFEN.
-#define BM_DAC_C1_DACBFEN (0x01U) //!< Bit mask for DAC_C1_DACBFEN.
-#define BS_DAC_C1_DACBFEN (1U) //!< Bit field size in bits for DAC_C1_DACBFEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DAC_C1_DACBFEN field.
-#define BR_DAC_C1_DACBFEN(x) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN))
-#endif
-
-//! @brief Format value for bitfield DAC_C1_DACBFEN.
-#define BF_DAC_C1_DACBFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C1_DACBFEN), uint8_t) & BM_DAC_C1_DACBFEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DACBFEN field to a new value.
-#define BW_DAC_C1_DACBFEN(x, v) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DAC_C1, field DACBFMD[2:1] (RW)
- *
- * Values:
- * - 00 - Normal mode
- * - 01 - Swing mode
- * - 10 - One-Time Scan mode
- * - 11 - Reserved
- */
-//@{
-#define BP_DAC_C1_DACBFMD (1U) //!< Bit position for DAC_C1_DACBFMD.
-#define BM_DAC_C1_DACBFMD (0x06U) //!< Bit mask for DAC_C1_DACBFMD.
-#define BS_DAC_C1_DACBFMD (2U) //!< Bit field size in bits for DAC_C1_DACBFMD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DAC_C1_DACBFMD field.
-#define BR_DAC_C1_DACBFMD(x) (HW_DAC_C1(x).B.DACBFMD)
-#endif
-
-//! @brief Format value for bitfield DAC_C1_DACBFMD.
-#define BF_DAC_C1_DACBFMD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C1_DACBFMD), uint8_t) & BM_DAC_C1_DACBFMD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DACBFMD field to a new value.
-#define BW_DAC_C1_DACBFMD(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFMD) | BF_DAC_C1_DACBFMD(v)))
-#endif
-//@}
-
-/*!
- * @name Register DAC_C1, field DACBFWM[4:3] (RW)
- *
- * Controls when SR[DACBFWMF] is set. When the DAC buffer read pointer reaches
- * the word defined by this field, which is 1-4 words away from the upper limit
- * (DACBUP), SR[DACBFWMF] will be set. This allows user configuration of the
- * watermark interrupt.
- *
- * Values:
- * - 00 - 1 word
- * - 01 - 2 words
- * - 10 - 3 words
- * - 11 - 4 words
- */
-//@{
-#define BP_DAC_C1_DACBFWM (3U) //!< Bit position for DAC_C1_DACBFWM.
-#define BM_DAC_C1_DACBFWM (0x18U) //!< Bit mask for DAC_C1_DACBFWM.
-#define BS_DAC_C1_DACBFWM (2U) //!< Bit field size in bits for DAC_C1_DACBFWM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DAC_C1_DACBFWM field.
-#define BR_DAC_C1_DACBFWM(x) (HW_DAC_C1(x).B.DACBFWM)
-#endif
-
-//! @brief Format value for bitfield DAC_C1_DACBFWM.
-#define BF_DAC_C1_DACBFWM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C1_DACBFWM), uint8_t) & BM_DAC_C1_DACBFWM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DACBFWM field to a new value.
-#define BW_DAC_C1_DACBFWM(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFWM) | BF_DAC_C1_DACBFWM(v)))
-#endif
-//@}
-
-/*!
- * @name Register DAC_C1, field DMAEN[7] (RW)
- *
- * Values:
- * - 0 - DMA is disabled.
- * - 1 - DMA is enabled. When DMA is enabled, the DMA request will be generated
- * by original interrupts. The interrupts will not be presented on this
- * module at the same time.
- */
-//@{
-#define BP_DAC_C1_DMAEN (7U) //!< Bit position for DAC_C1_DMAEN.
-#define BM_DAC_C1_DMAEN (0x80U) //!< Bit mask for DAC_C1_DMAEN.
-#define BS_DAC_C1_DMAEN (1U) //!< Bit field size in bits for DAC_C1_DMAEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DAC_C1_DMAEN field.
-#define BR_DAC_C1_DMAEN(x) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN))
-#endif
-
-//! @brief Format value for bitfield DAC_C1_DMAEN.
-#define BF_DAC_C1_DMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C1_DMAEN), uint8_t) & BM_DAC_C1_DMAEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DMAEN field to a new value.
-#define BW_DAC_C1_DMAEN(x, v) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_DAC_C2 - DAC Control Register 2
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DAC_C2 - DAC Control Register 2 (RW)
- *
- * Reset value: 0x0FU
- */
-typedef union _hw_dac_c2
-{
- uint8_t U;
- struct _hw_dac_c2_bitfields
- {
- uint8_t DACBFUP : 4; //!< [3:0] DAC Buffer Upper Limit
- uint8_t DACBFRP : 4; //!< [7:4] DAC Buffer Read Pointer
- } B;
-} hw_dac_c2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DAC_C2 register
- */
-//@{
-#define HW_DAC_C2_ADDR(x) (REGS_DAC_BASE(x) + 0x23U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DAC_C2(x) (*(__IO hw_dac_c2_t *) HW_DAC_C2_ADDR(x))
-#define HW_DAC_C2_RD(x) (HW_DAC_C2(x).U)
-#define HW_DAC_C2_WR(x, v) (HW_DAC_C2(x).U = (v))
-#define HW_DAC_C2_SET(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) | (v)))
-#define HW_DAC_C2_CLR(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) & ~(v)))
-#define HW_DAC_C2_TOG(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DAC_C2 bitfields
- */
-
-/*!
- * @name Register DAC_C2, field DACBFUP[3:0] (RW)
- *
- * Selects the upper limit of the DAC buffer. The buffer read pointer cannot
- * exceed it.
- */
-//@{
-#define BP_DAC_C2_DACBFUP (0U) //!< Bit position for DAC_C2_DACBFUP.
-#define BM_DAC_C2_DACBFUP (0x0FU) //!< Bit mask for DAC_C2_DACBFUP.
-#define BS_DAC_C2_DACBFUP (4U) //!< Bit field size in bits for DAC_C2_DACBFUP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DAC_C2_DACBFUP field.
-#define BR_DAC_C2_DACBFUP(x) (HW_DAC_C2(x).B.DACBFUP)
-#endif
-
-//! @brief Format value for bitfield DAC_C2_DACBFUP.
-#define BF_DAC_C2_DACBFUP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C2_DACBFUP), uint8_t) & BM_DAC_C2_DACBFUP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DACBFUP field to a new value.
-#define BW_DAC_C2_DACBFUP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFUP) | BF_DAC_C2_DACBFUP(v)))
-#endif
-//@}
-
-/*!
- * @name Register DAC_C2, field DACBFRP[7:4] (RW)
- *
- * Keeps the current value of the buffer read pointer.
- */
-//@{
-#define BP_DAC_C2_DACBFRP (4U) //!< Bit position for DAC_C2_DACBFRP.
-#define BM_DAC_C2_DACBFRP (0xF0U) //!< Bit mask for DAC_C2_DACBFRP.
-#define BS_DAC_C2_DACBFRP (4U) //!< Bit field size in bits for DAC_C2_DACBFRP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DAC_C2_DACBFRP field.
-#define BR_DAC_C2_DACBFRP(x) (HW_DAC_C2(x).B.DACBFRP)
-#endif
-
-//! @brief Format value for bitfield DAC_C2_DACBFRP.
-#define BF_DAC_C2_DACBFRP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C2_DACBFRP), uint8_t) & BM_DAC_C2_DACBFRP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DACBFRP field to a new value.
-#define BW_DAC_C2_DACBFRP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFRP) | BF_DAC_C2_DACBFRP(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_dac_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All DAC module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_dac
-{
- struct {
- __IO hw_dac_datnl_t DATnL; //!< [0x0] DAC Data Low Register
- __IO hw_dac_datnh_t DATnH; //!< [0x1] DAC Data High Register
- } DAT[16];
- __IO hw_dac_sr_t SR; //!< [0x20] DAC Status Register
- __IO hw_dac_c0_t C0; //!< [0x21] DAC Control Register
- __IO hw_dac_c1_t C1; //!< [0x22] DAC Control Register 1
- __IO hw_dac_c2_t C2; //!< [0x23] DAC Control Register 2
-} hw_dac_t;
-#pragma pack()
-
-//! @brief Macro to access all DAC registers.
-//! @param x DAC instance number.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_DAC(0)</code>.
-#define HW_DAC(x) (*(hw_dac_t *) REGS_DAC_BASE(x))
-#endif
-
-#endif // __HW_DAC_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_dma.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,5973 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_DMA_REGISTERS_H__
-#define __HW_DMA_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 DMA
- *
- * Enhanced direct memory access controller
- *
- * Registers defined in this header file:
- * - HW_DMA_CR - Control Register
- * - HW_DMA_ES - Error Status Register
- * - HW_DMA_ERQ - Enable Request Register
- * - HW_DMA_EEI - Enable Error Interrupt Register
- * - HW_DMA_CEEI - Clear Enable Error Interrupt Register
- * - HW_DMA_SEEI - Set Enable Error Interrupt Register
- * - HW_DMA_CERQ - Clear Enable Request Register
- * - HW_DMA_SERQ - Set Enable Request Register
- * - HW_DMA_CDNE - Clear DONE Status Bit Register
- * - HW_DMA_SSRT - Set START Bit Register
- * - HW_DMA_CERR - Clear Error Register
- * - HW_DMA_CINT - Clear Interrupt Request Register
- * - HW_DMA_INT - Interrupt Request Register
- * - HW_DMA_ERR - Error Register
- * - HW_DMA_HRS - Hardware Request Status Register
- * - HW_DMA_DCHPRIn - Channel n Priority Register
- * - HW_DMA_TCDn_SADDR - TCD Source Address
- * - HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset
- * - HW_DMA_TCDn_ATTR - TCD Transfer Attributes
- * - HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
- * - HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
- * - HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
- * - HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment
- * - HW_DMA_TCDn_DADDR - TCD Destination Address
- * - HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset
- * - HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
- * - HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
- * - HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address
- * - HW_DMA_TCDn_CSR - TCD Control and Status
- * - HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
- * - HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
- *
- * - hw_dma_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_DMA_BASE
-#define HW_DMA_INSTANCE_COUNT (1U) //!< Number of instances of the DMA module.
-#define HW_DMA0 (0U) //!< Instance number for DMA.
-#define REGS_DMA0_BASE (0x40008000U) //!< Base address for DMA.
-
-//! @brief Table of base addresses for DMA instances.
-static const uint32_t __g_regs_DMA_base_addresses[] = {
- REGS_DMA0_BASE,
- };
-
-//! @brief Get the base address of DMA by instance number.
-//! @param x DMA instance number, from 0 through 0.
-#define REGS_DMA_BASE(x) (__g_regs_DMA_base_addresses[(x)])
-
-//! @brief Get the instance number given a base address.
-//! @param b Base address for an instance of DMA.
-#define REGS_DMA_INSTANCE(b) ((b) == REGS_DMA0_BASE ? HW_DMA0 : 0)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_DMA_CR - Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_CR - Control Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * The CR defines the basic operating configuration of the DMA. Arbitration can
- * be configured to use either a fixed-priority or a round-robin scheme. For
- * fixed-priority arbitration, the highest priority channel requesting service is
- * selected to execute. The channel priority registers assign the priorities; see
- * the DCHPRIn registers. For round-robin arbitration, the channel priorities are
- * ignored and channels are cycled through (from high to low channel number)
- * without regard to priority. For correct operation, writes to the CR register must
- * be performed only when the DMA channels are inactive; that is, when
- * TCDn_CSR[ACTIVE] bits are cleared. Minor loop offsets are address offset values added to
- * the final source address (TCDn_SADDR) or destination address (TCDn_DADDR) upon
- * minor loop completion. When minor loop offsets are enabled, the minor loop
- * offset (MLOFF) is added to the final source address (TCDn_SADDR), to the final
- * destination address (TCDn_DADDR), or to both prior to the addresses being
- * written back into the TCD. If the major loop is complete, the minor loop offset is
- * ignored and the major loop address offsets (TCDn_SLAST and TCDn_DLAST_SGA) are
- * used to compute the next TCDn_SADDR and TCDn_DADDR values. When minor loop
- * mapping is enabled (EMLM is 1), TCDn word2 is redefined. A portion of TCDn word2
- * is used to specify multiple fields: a source enable bit (SMLOE) to specify
- * the minor loop offset should be applied to the source address (TCDn_SADDR) upon
- * minor loop completion, a destination enable bit (DMLOE) to specify the minor
- * loop offset should be applied to the destination address (TCDn_DADDR) upon
- * minor loop completion, and the sign extended minor loop offset value (MLOFF). The
- * same offset value (MLOFF) is used for both source and destination minor loop
- * offsets. When either minor loop offset is enabled (SMLOE set or DMLOE set), the
- * NBYTES field is reduced to 10 bits. When both minor loop offsets are disabled
- * (SMLOE cleared and DMLOE cleared), the NBYTES field is a 30-bit vector. When
- * minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are
- * assigned to the NBYTES field.
- */
-typedef union _hw_dma_cr
-{
- uint32_t U;
- struct _hw_dma_cr_bitfields
- {
- uint32_t RESERVED0 : 1; //!< [0] Reserved.
- uint32_t EDBG : 1; //!< [1] Enable Debug
- uint32_t ERCA : 1; //!< [2] Enable Round Robin Channel Arbitration
- uint32_t RESERVED1 : 1; //!< [3] Reserved.
- uint32_t HOE : 1; //!< [4] Halt On Error
- uint32_t HALT : 1; //!< [5] Halt DMA Operations
- uint32_t CLM : 1; //!< [6] Continuous Link Mode
- uint32_t EMLM : 1; //!< [7] Enable Minor Loop Mapping
- uint32_t RESERVED2 : 8; //!< [15:8]
- uint32_t ECX : 1; //!< [16] Error Cancel Transfer
- uint32_t CX : 1; //!< [17] Cancel Transfer
- uint32_t RESERVED3 : 14; //!< [31:18]
- } B;
-} hw_dma_cr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_CR register
- */
-//@{
-#define HW_DMA_CR_ADDR(x) (REGS_DMA_BASE(x) + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_CR(x) (*(__IO hw_dma_cr_t *) HW_DMA_CR_ADDR(x))
-#define HW_DMA_CR_RD(x) (HW_DMA_CR(x).U)
-#define HW_DMA_CR_WR(x, v) (HW_DMA_CR(x).U = (v))
-#define HW_DMA_CR_SET(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) | (v)))
-#define HW_DMA_CR_CLR(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) & ~(v)))
-#define HW_DMA_CR_TOG(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_CR bitfields
- */
-
-/*!
- * @name Register DMA_CR, field EDBG[1] (RW)
- *
- * Values:
- * - 0 - When in debug mode, the DMA continues to operate.
- * - 1 - When in debug mode, the DMA stalls the start of a new channel.
- * Executing channels are allowed to complete. Channel execution resumes when the
- * system exits debug mode or the EDBG bit is cleared.
- */
-//@{
-#define BP_DMA_CR_EDBG (1U) //!< Bit position for DMA_CR_EDBG.
-#define BM_DMA_CR_EDBG (0x00000002U) //!< Bit mask for DMA_CR_EDBG.
-#define BS_DMA_CR_EDBG (1U) //!< Bit field size in bits for DMA_CR_EDBG.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_CR_EDBG field.
-#define BR_DMA_CR_EDBG(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EDBG))
-#endif
-
-//! @brief Format value for bitfield DMA_CR_EDBG.
-#define BF_DMA_CR_EDBG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_EDBG), uint32_t) & BM_DMA_CR_EDBG)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EDBG field to a new value.
-#define BW_DMA_CR_EDBG(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EDBG) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_CR, field ERCA[2] (RW)
- *
- * Values:
- * - 0 - Fixed priority arbitration is used for channel selection .
- * - 1 - Round robin arbitration is used for channel selection .
- */
-//@{
-#define BP_DMA_CR_ERCA (2U) //!< Bit position for DMA_CR_ERCA.
-#define BM_DMA_CR_ERCA (0x00000004U) //!< Bit mask for DMA_CR_ERCA.
-#define BS_DMA_CR_ERCA (1U) //!< Bit field size in bits for DMA_CR_ERCA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_CR_ERCA field.
-#define BR_DMA_CR_ERCA(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ERCA))
-#endif
-
-//! @brief Format value for bitfield DMA_CR_ERCA.
-#define BF_DMA_CR_ERCA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_ERCA), uint32_t) & BM_DMA_CR_ERCA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERCA field to a new value.
-#define BW_DMA_CR_ERCA(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ERCA) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_CR, field HOE[4] (RW)
- *
- * Values:
- * - 0 - Normal operation
- * - 1 - Any error causes the HALT bit to set. Subsequently, all service
- * requests are ignored until the HALT bit is cleared.
- */
-//@{
-#define BP_DMA_CR_HOE (4U) //!< Bit position for DMA_CR_HOE.
-#define BM_DMA_CR_HOE (0x00000010U) //!< Bit mask for DMA_CR_HOE.
-#define BS_DMA_CR_HOE (1U) //!< Bit field size in bits for DMA_CR_HOE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_CR_HOE field.
-#define BR_DMA_CR_HOE(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HOE))
-#endif
-
-//! @brief Format value for bitfield DMA_CR_HOE.
-#define BF_DMA_CR_HOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_HOE), uint32_t) & BM_DMA_CR_HOE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the HOE field to a new value.
-#define BW_DMA_CR_HOE(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HOE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_CR, field HALT[5] (RW)
- *
- * Values:
- * - 0 - Normal operation
- * - 1 - Stall the start of any new channels. Executing channels are allowed to
- * complete. Channel execution resumes when this bit is cleared.
- */
-//@{
-#define BP_DMA_CR_HALT (5U) //!< Bit position for DMA_CR_HALT.
-#define BM_DMA_CR_HALT (0x00000020U) //!< Bit mask for DMA_CR_HALT.
-#define BS_DMA_CR_HALT (1U) //!< Bit field size in bits for DMA_CR_HALT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_CR_HALT field.
-#define BR_DMA_CR_HALT(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HALT))
-#endif
-
-//! @brief Format value for bitfield DMA_CR_HALT.
-#define BF_DMA_CR_HALT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_HALT), uint32_t) & BM_DMA_CR_HALT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the HALT field to a new value.
-#define BW_DMA_CR_HALT(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HALT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_CR, field CLM[6] (RW)
- *
- * Values:
- * - 0 - A minor loop channel link made to itself goes through channel
- * arbitration before being activated again.
- * - 1 - A minor loop channel link made to itself does not go through channel
- * arbitration before being activated again. Upon minor loop completion, the
- * channel activates again if that channel has a minor loop channel link
- * enabled and the link channel is itself. This effectively applies the minor loop
- * offsets and restarts the next minor loop.
- */
-//@{
-#define BP_DMA_CR_CLM (6U) //!< Bit position for DMA_CR_CLM.
-#define BM_DMA_CR_CLM (0x00000040U) //!< Bit mask for DMA_CR_CLM.
-#define BS_DMA_CR_CLM (1U) //!< Bit field size in bits for DMA_CR_CLM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_CR_CLM field.
-#define BR_DMA_CR_CLM(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CLM))
-#endif
-
-//! @brief Format value for bitfield DMA_CR_CLM.
-#define BF_DMA_CR_CLM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_CLM), uint32_t) & BM_DMA_CR_CLM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CLM field to a new value.
-#define BW_DMA_CR_CLM(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CLM) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_CR, field EMLM[7] (RW)
- *
- * Values:
- * - 0 - Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
- * - 1 - Enabled. TCDn.word2 is redefined to include individual enable fields,
- * an offset field, and the NBYTES field. The individual enable fields allow
- * the minor loop offset to be applied to the source address, the destination
- * address, or both. The NBYTES field is reduced when either offset is
- * enabled.
- */
-//@{
-#define BP_DMA_CR_EMLM (7U) //!< Bit position for DMA_CR_EMLM.
-#define BM_DMA_CR_EMLM (0x00000080U) //!< Bit mask for DMA_CR_EMLM.
-#define BS_DMA_CR_EMLM (1U) //!< Bit field size in bits for DMA_CR_EMLM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_CR_EMLM field.
-#define BR_DMA_CR_EMLM(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EMLM))
-#endif
-
-//! @brief Format value for bitfield DMA_CR_EMLM.
-#define BF_DMA_CR_EMLM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_EMLM), uint32_t) & BM_DMA_CR_EMLM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EMLM field to a new value.
-#define BW_DMA_CR_EMLM(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EMLM) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_CR, field ECX[16] (RW)
- *
- * Values:
- * - 0 - Normal operation
- * - 1 - Cancel the remaining data transfer in the same fashion as the CX bit.
- * Stop the executing channel and force the minor loop to finish. The cancel
- * takes effect after the last write of the current read/write sequence. The
- * ECX bit clears itself after the cancel is honored. In addition to
- * cancelling the transfer, ECX treats the cancel as an error condition, thus updating
- * the Error Status register (DMAx_ES) and generating an optional error
- * interrupt.
- */
-//@{
-#define BP_DMA_CR_ECX (16U) //!< Bit position for DMA_CR_ECX.
-#define BM_DMA_CR_ECX (0x00010000U) //!< Bit mask for DMA_CR_ECX.
-#define BS_DMA_CR_ECX (1U) //!< Bit field size in bits for DMA_CR_ECX.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_CR_ECX field.
-#define BR_DMA_CR_ECX(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ECX))
-#endif
-
-//! @brief Format value for bitfield DMA_CR_ECX.
-#define BF_DMA_CR_ECX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_ECX), uint32_t) & BM_DMA_CR_ECX)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ECX field to a new value.
-#define BW_DMA_CR_ECX(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ECX) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_CR, field CX[17] (RW)
- *
- * Values:
- * - 0 - Normal operation
- * - 1 - Cancel the remaining data transfer. Stop the executing channel and
- * force the minor loop to finish. The cancel takes effect after the last write
- * of the current read/write sequence. The CX bit clears itself after the
- * cancel has been honored. This cancel retires the channel normally as if the
- * minor loop was completed.
- */
-//@{
-#define BP_DMA_CR_CX (17U) //!< Bit position for DMA_CR_CX.
-#define BM_DMA_CR_CX (0x00020000U) //!< Bit mask for DMA_CR_CX.
-#define BS_DMA_CR_CX (1U) //!< Bit field size in bits for DMA_CR_CX.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_CR_CX field.
-#define BR_DMA_CR_CX(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CX))
-#endif
-
-//! @brief Format value for bitfield DMA_CR_CX.
-#define BF_DMA_CR_CX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_CX), uint32_t) & BM_DMA_CR_CX)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CX field to a new value.
-#define BW_DMA_CR_CX(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CX) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_DMA_ES - Error Status Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_ES - Error Status Register (RO)
- *
- * Reset value: 0x00000000U
- *
- * The ES provides information concerning the last recorded channel error.
- * Channel errors can be caused by: A configuration error, that is: An illegal setting
- * in the transfer-control descriptor, or An illegal priority register setting
- * in fixed-arbitration An error termination to a bus master read or write cycle
- * See the Error Reporting and Handling section for more details.
- */
-typedef union _hw_dma_es
-{
- uint32_t U;
- struct _hw_dma_es_bitfields
- {
- uint32_t DBE : 1; //!< [0] Destination Bus Error
- uint32_t SBE : 1; //!< [1] Source Bus Error
- uint32_t SGE : 1; //!< [2] Scatter/Gather Configuration Error
- uint32_t NCE : 1; //!< [3] NBYTES/CITER Configuration Error
- uint32_t DOE : 1; //!< [4] Destination Offset Error
- uint32_t DAE : 1; //!< [5] Destination Address Error
- uint32_t SOE : 1; //!< [6] Source Offset Error
- uint32_t SAE : 1; //!< [7] Source Address Error
- uint32_t ERRCHN : 4; //!< [11:8] Error Channel Number or Canceled
- //! Channel Number
- uint32_t RESERVED0 : 2; //!< [13:12]
- uint32_t CPE : 1; //!< [14] Channel Priority Error
- uint32_t RESERVED1 : 1; //!< [15]
- uint32_t ECX : 1; //!< [16] Transfer Canceled
- uint32_t RESERVED2 : 14; //!< [30:17]
- uint32_t VLD : 1; //!< [31]
- } B;
-} hw_dma_es_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_ES register
- */
-//@{
-#define HW_DMA_ES_ADDR(x) (REGS_DMA_BASE(x) + 0x4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_ES(x) (*(__I hw_dma_es_t *) HW_DMA_ES_ADDR(x))
-#define HW_DMA_ES_RD(x) (HW_DMA_ES(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_ES bitfields
- */
-
-/*!
- * @name Register DMA_ES, field DBE[0] (RO)
- *
- * Values:
- * - 0 - No destination bus error
- * - 1 - The last recorded error was a bus error on a destination write
- */
-//@{
-#define BP_DMA_ES_DBE (0U) //!< Bit position for DMA_ES_DBE.
-#define BM_DMA_ES_DBE (0x00000001U) //!< Bit mask for DMA_ES_DBE.
-#define BS_DMA_ES_DBE (1U) //!< Bit field size in bits for DMA_ES_DBE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ES_DBE field.
-#define BR_DMA_ES_DBE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DBE))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ES, field SBE[1] (RO)
- *
- * Values:
- * - 0 - No source bus error
- * - 1 - The last recorded error was a bus error on a source read
- */
-//@{
-#define BP_DMA_ES_SBE (1U) //!< Bit position for DMA_ES_SBE.
-#define BM_DMA_ES_SBE (0x00000002U) //!< Bit mask for DMA_ES_SBE.
-#define BS_DMA_ES_SBE (1U) //!< Bit field size in bits for DMA_ES_SBE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ES_SBE field.
-#define BR_DMA_ES_SBE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SBE))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ES, field SGE[2] (RO)
- *
- * Values:
- * - 0 - No scatter/gather configuration error
- * - 1 - The last recorded error was a configuration error detected in the
- * TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather
- * operation after major loop completion if TCDn_CSR[ESG] is enabled.
- * TCDn_DLASTSGA is not on a 32 byte boundary.
- */
-//@{
-#define BP_DMA_ES_SGE (2U) //!< Bit position for DMA_ES_SGE.
-#define BM_DMA_ES_SGE (0x00000004U) //!< Bit mask for DMA_ES_SGE.
-#define BS_DMA_ES_SGE (1U) //!< Bit field size in bits for DMA_ES_SGE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ES_SGE field.
-#define BR_DMA_ES_SGE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SGE))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ES, field NCE[3] (RO)
- *
- * Values:
- * - 0 - No NBYTES/CITER configuration error
- * - 1 - The last recorded error was a configuration error detected in the
- * TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of
- * TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or
- * TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
- */
-//@{
-#define BP_DMA_ES_NCE (3U) //!< Bit position for DMA_ES_NCE.
-#define BM_DMA_ES_NCE (0x00000008U) //!< Bit mask for DMA_ES_NCE.
-#define BS_DMA_ES_NCE (1U) //!< Bit field size in bits for DMA_ES_NCE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ES_NCE field.
-#define BR_DMA_ES_NCE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_NCE))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ES, field DOE[4] (RO)
- *
- * Values:
- * - 0 - No destination offset configuration error
- * - 1 - The last recorded error was a configuration error detected in the
- * TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
- */
-//@{
-#define BP_DMA_ES_DOE (4U) //!< Bit position for DMA_ES_DOE.
-#define BM_DMA_ES_DOE (0x00000010U) //!< Bit mask for DMA_ES_DOE.
-#define BS_DMA_ES_DOE (1U) //!< Bit field size in bits for DMA_ES_DOE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ES_DOE field.
-#define BR_DMA_ES_DOE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DOE))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ES, field DAE[5] (RO)
- *
- * Values:
- * - 0 - No destination address configuration error
- * - 1 - The last recorded error was a configuration error detected in the
- * TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
- */
-//@{
-#define BP_DMA_ES_DAE (5U) //!< Bit position for DMA_ES_DAE.
-#define BM_DMA_ES_DAE (0x00000020U) //!< Bit mask for DMA_ES_DAE.
-#define BS_DMA_ES_DAE (1U) //!< Bit field size in bits for DMA_ES_DAE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ES_DAE field.
-#define BR_DMA_ES_DAE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DAE))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ES, field SOE[6] (RO)
- *
- * Values:
- * - 0 - No source offset configuration error
- * - 1 - The last recorded error was a configuration error detected in the
- * TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
- */
-//@{
-#define BP_DMA_ES_SOE (6U) //!< Bit position for DMA_ES_SOE.
-#define BM_DMA_ES_SOE (0x00000040U) //!< Bit mask for DMA_ES_SOE.
-#define BS_DMA_ES_SOE (1U) //!< Bit field size in bits for DMA_ES_SOE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ES_SOE field.
-#define BR_DMA_ES_SOE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SOE))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ES, field SAE[7] (RO)
- *
- * Values:
- * - 0 - No source address configuration error.
- * - 1 - The last recorded error was a configuration error detected in the
- * TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
- */
-//@{
-#define BP_DMA_ES_SAE (7U) //!< Bit position for DMA_ES_SAE.
-#define BM_DMA_ES_SAE (0x00000080U) //!< Bit mask for DMA_ES_SAE.
-#define BS_DMA_ES_SAE (1U) //!< Bit field size in bits for DMA_ES_SAE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ES_SAE field.
-#define BR_DMA_ES_SAE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SAE))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ES, field ERRCHN[11:8] (RO)
- *
- * The channel number of the last recorded error (excluding CPE errors) or last
- * recorded error canceled transfer.
- */
-//@{
-#define BP_DMA_ES_ERRCHN (8U) //!< Bit position for DMA_ES_ERRCHN.
-#define BM_DMA_ES_ERRCHN (0x00000F00U) //!< Bit mask for DMA_ES_ERRCHN.
-#define BS_DMA_ES_ERRCHN (4U) //!< Bit field size in bits for DMA_ES_ERRCHN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ES_ERRCHN field.
-#define BR_DMA_ES_ERRCHN(x) (HW_DMA_ES(x).B.ERRCHN)
-#endif
-//@}
-
-/*!
- * @name Register DMA_ES, field CPE[14] (RO)
- *
- * Values:
- * - 0 - No channel priority error
- * - 1 - The last recorded error was a configuration error in the channel
- * priorities . Channel priorities are not unique.
- */
-//@{
-#define BP_DMA_ES_CPE (14U) //!< Bit position for DMA_ES_CPE.
-#define BM_DMA_ES_CPE (0x00004000U) //!< Bit mask for DMA_ES_CPE.
-#define BS_DMA_ES_CPE (1U) //!< Bit field size in bits for DMA_ES_CPE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ES_CPE field.
-#define BR_DMA_ES_CPE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_CPE))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ES, field ECX[16] (RO)
- *
- * Values:
- * - 0 - No canceled transfers
- * - 1 - The last recorded entry was a canceled transfer by the error cancel
- * transfer input
- */
-//@{
-#define BP_DMA_ES_ECX (16U) //!< Bit position for DMA_ES_ECX.
-#define BM_DMA_ES_ECX (0x00010000U) //!< Bit mask for DMA_ES_ECX.
-#define BS_DMA_ES_ECX (1U) //!< Bit field size in bits for DMA_ES_ECX.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ES_ECX field.
-#define BR_DMA_ES_ECX(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_ECX))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ES, field VLD[31] (RO)
- *
- * Logical OR of all ERR status bits
- *
- * Values:
- * - 0 - No ERR bits are set
- * - 1 - At least one ERR bit is set indicating a valid error exists that has
- * not been cleared
- */
-//@{
-#define BP_DMA_ES_VLD (31U) //!< Bit position for DMA_ES_VLD.
-#define BM_DMA_ES_VLD (0x80000000U) //!< Bit mask for DMA_ES_VLD.
-#define BS_DMA_ES_VLD (1U) //!< Bit field size in bits for DMA_ES_VLD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ES_VLD field.
-#define BR_DMA_ES_VLD(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_VLD))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_DMA_ERQ - Enable Request Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_ERQ - Enable Request Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * The ERQ register provides a bit map for the 16 implemented channels to enable
- * the request signal for each channel. The state of any given channel enable is
- * directly affected by writes to this register; it is also affected by writes
- * to the SERQ and CERQ. The {S,C}ERQ registers are provided so the request enable
- * for a single channel can easily be modified without needing to perform a
- * read-modify-write sequence to the ERQ. DMA request input signals and this enable
- * request flag must be asserted before a channel's hardware service request is
- * accepted. The state of the DMA enable request flag does not affect a channel
- * service request made explicitly through software or a linked channel request.
- */
-typedef union _hw_dma_erq
-{
- uint32_t U;
- struct _hw_dma_erq_bitfields
- {
- uint32_t ERQ0 : 1; //!< [0] Enable DMA Request 0
- uint32_t ERQ1 : 1; //!< [1] Enable DMA Request 1
- uint32_t ERQ2 : 1; //!< [2] Enable DMA Request 2
- uint32_t ERQ3 : 1; //!< [3] Enable DMA Request 3
- uint32_t ERQ4 : 1; //!< [4] Enable DMA Request 4
- uint32_t ERQ5 : 1; //!< [5] Enable DMA Request 5
- uint32_t ERQ6 : 1; //!< [6] Enable DMA Request 6
- uint32_t ERQ7 : 1; //!< [7] Enable DMA Request 7
- uint32_t ERQ8 : 1; //!< [8] Enable DMA Request 8
- uint32_t ERQ9 : 1; //!< [9] Enable DMA Request 9
- uint32_t ERQ10 : 1; //!< [10] Enable DMA Request 10
- uint32_t ERQ11 : 1; //!< [11] Enable DMA Request 11
- uint32_t ERQ12 : 1; //!< [12] Enable DMA Request 12
- uint32_t ERQ13 : 1; //!< [13] Enable DMA Request 13
- uint32_t ERQ14 : 1; //!< [14] Enable DMA Request 14
- uint32_t ERQ15 : 1; //!< [15] Enable DMA Request 15
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_dma_erq_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_ERQ register
- */
-//@{
-#define HW_DMA_ERQ_ADDR(x) (REGS_DMA_BASE(x) + 0xCU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_ERQ(x) (*(__IO hw_dma_erq_t *) HW_DMA_ERQ_ADDR(x))
-#define HW_DMA_ERQ_RD(x) (HW_DMA_ERQ(x).U)
-#define HW_DMA_ERQ_WR(x, v) (HW_DMA_ERQ(x).U = (v))
-#define HW_DMA_ERQ_SET(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) | (v)))
-#define HW_DMA_ERQ_CLR(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) & ~(v)))
-#define HW_DMA_ERQ_TOG(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_ERQ bitfields
- */
-
-/*!
- * @name Register DMA_ERQ, field ERQ0[0] (RW)
- *
- * Values:
- * - 0 - The DMA request signal for the corresponding channel is disabled
- * - 1 - The DMA request signal for the corresponding channel is enabled
- */
-//@{
-#define BP_DMA_ERQ_ERQ0 (0U) //!< Bit position for DMA_ERQ_ERQ0.
-#define BM_DMA_ERQ_ERQ0 (0x00000001U) //!< Bit mask for DMA_ERQ_ERQ0.
-#define BS_DMA_ERQ_ERQ0 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERQ_ERQ0 field.
-#define BR_DMA_ERQ_ERQ0(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ0))
-#endif
-
-//! @brief Format value for bitfield DMA_ERQ_ERQ0.
-#define BF_DMA_ERQ_ERQ0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ0), uint32_t) & BM_DMA_ERQ_ERQ0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERQ0 field to a new value.
-#define BW_DMA_ERQ_ERQ0(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERQ, field ERQ1[1] (RW)
- *
- * Values:
- * - 0 - The DMA request signal for the corresponding channel is disabled
- * - 1 - The DMA request signal for the corresponding channel is enabled
- */
-//@{
-#define BP_DMA_ERQ_ERQ1 (1U) //!< Bit position for DMA_ERQ_ERQ1.
-#define BM_DMA_ERQ_ERQ1 (0x00000002U) //!< Bit mask for DMA_ERQ_ERQ1.
-#define BS_DMA_ERQ_ERQ1 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERQ_ERQ1 field.
-#define BR_DMA_ERQ_ERQ1(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ1))
-#endif
-
-//! @brief Format value for bitfield DMA_ERQ_ERQ1.
-#define BF_DMA_ERQ_ERQ1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ1), uint32_t) & BM_DMA_ERQ_ERQ1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERQ1 field to a new value.
-#define BW_DMA_ERQ_ERQ1(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERQ, field ERQ2[2] (RW)
- *
- * Values:
- * - 0 - The DMA request signal for the corresponding channel is disabled
- * - 1 - The DMA request signal for the corresponding channel is enabled
- */
-//@{
-#define BP_DMA_ERQ_ERQ2 (2U) //!< Bit position for DMA_ERQ_ERQ2.
-#define BM_DMA_ERQ_ERQ2 (0x00000004U) //!< Bit mask for DMA_ERQ_ERQ2.
-#define BS_DMA_ERQ_ERQ2 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERQ_ERQ2 field.
-#define BR_DMA_ERQ_ERQ2(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ2))
-#endif
-
-//! @brief Format value for bitfield DMA_ERQ_ERQ2.
-#define BF_DMA_ERQ_ERQ2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ2), uint32_t) & BM_DMA_ERQ_ERQ2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERQ2 field to a new value.
-#define BW_DMA_ERQ_ERQ2(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERQ, field ERQ3[3] (RW)
- *
- * Values:
- * - 0 - The DMA request signal for the corresponding channel is disabled
- * - 1 - The DMA request signal for the corresponding channel is enabled
- */
-//@{
-#define BP_DMA_ERQ_ERQ3 (3U) //!< Bit position for DMA_ERQ_ERQ3.
-#define BM_DMA_ERQ_ERQ3 (0x00000008U) //!< Bit mask for DMA_ERQ_ERQ3.
-#define BS_DMA_ERQ_ERQ3 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERQ_ERQ3 field.
-#define BR_DMA_ERQ_ERQ3(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ3))
-#endif
-
-//! @brief Format value for bitfield DMA_ERQ_ERQ3.
-#define BF_DMA_ERQ_ERQ3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ3), uint32_t) & BM_DMA_ERQ_ERQ3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERQ3 field to a new value.
-#define BW_DMA_ERQ_ERQ3(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERQ, field ERQ4[4] (RW)
- *
- * Values:
- * - 0 - The DMA request signal for the corresponding channel is disabled
- * - 1 - The DMA request signal for the corresponding channel is enabled
- */
-//@{
-#define BP_DMA_ERQ_ERQ4 (4U) //!< Bit position for DMA_ERQ_ERQ4.
-#define BM_DMA_ERQ_ERQ4 (0x00000010U) //!< Bit mask for DMA_ERQ_ERQ4.
-#define BS_DMA_ERQ_ERQ4 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERQ_ERQ4 field.
-#define BR_DMA_ERQ_ERQ4(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ4))
-#endif
-
-//! @brief Format value for bitfield DMA_ERQ_ERQ4.
-#define BF_DMA_ERQ_ERQ4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ4), uint32_t) & BM_DMA_ERQ_ERQ4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERQ4 field to a new value.
-#define BW_DMA_ERQ_ERQ4(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERQ, field ERQ5[5] (RW)
- *
- * Values:
- * - 0 - The DMA request signal for the corresponding channel is disabled
- * - 1 - The DMA request signal for the corresponding channel is enabled
- */
-//@{
-#define BP_DMA_ERQ_ERQ5 (5U) //!< Bit position for DMA_ERQ_ERQ5.
-#define BM_DMA_ERQ_ERQ5 (0x00000020U) //!< Bit mask for DMA_ERQ_ERQ5.
-#define BS_DMA_ERQ_ERQ5 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERQ_ERQ5 field.
-#define BR_DMA_ERQ_ERQ5(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ5))
-#endif
-
-//! @brief Format value for bitfield DMA_ERQ_ERQ5.
-#define BF_DMA_ERQ_ERQ5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ5), uint32_t) & BM_DMA_ERQ_ERQ5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERQ5 field to a new value.
-#define BW_DMA_ERQ_ERQ5(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERQ, field ERQ6[6] (RW)
- *
- * Values:
- * - 0 - The DMA request signal for the corresponding channel is disabled
- * - 1 - The DMA request signal for the corresponding channel is enabled
- */
-//@{
-#define BP_DMA_ERQ_ERQ6 (6U) //!< Bit position for DMA_ERQ_ERQ6.
-#define BM_DMA_ERQ_ERQ6 (0x00000040U) //!< Bit mask for DMA_ERQ_ERQ6.
-#define BS_DMA_ERQ_ERQ6 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERQ_ERQ6 field.
-#define BR_DMA_ERQ_ERQ6(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ6))
-#endif
-
-//! @brief Format value for bitfield DMA_ERQ_ERQ6.
-#define BF_DMA_ERQ_ERQ6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ6), uint32_t) & BM_DMA_ERQ_ERQ6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERQ6 field to a new value.
-#define BW_DMA_ERQ_ERQ6(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERQ, field ERQ7[7] (RW)
- *
- * Values:
- * - 0 - The DMA request signal for the corresponding channel is disabled
- * - 1 - The DMA request signal for the corresponding channel is enabled
- */
-//@{
-#define BP_DMA_ERQ_ERQ7 (7U) //!< Bit position for DMA_ERQ_ERQ7.
-#define BM_DMA_ERQ_ERQ7 (0x00000080U) //!< Bit mask for DMA_ERQ_ERQ7.
-#define BS_DMA_ERQ_ERQ7 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERQ_ERQ7 field.
-#define BR_DMA_ERQ_ERQ7(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ7))
-#endif
-
-//! @brief Format value for bitfield DMA_ERQ_ERQ7.
-#define BF_DMA_ERQ_ERQ7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ7), uint32_t) & BM_DMA_ERQ_ERQ7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERQ7 field to a new value.
-#define BW_DMA_ERQ_ERQ7(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERQ, field ERQ8[8] (RW)
- *
- * Values:
- * - 0 - The DMA request signal for the corresponding channel is disabled
- * - 1 - The DMA request signal for the corresponding channel is enabled
- */
-//@{
-#define BP_DMA_ERQ_ERQ8 (8U) //!< Bit position for DMA_ERQ_ERQ8.
-#define BM_DMA_ERQ_ERQ8 (0x00000100U) //!< Bit mask for DMA_ERQ_ERQ8.
-#define BS_DMA_ERQ_ERQ8 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ8.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERQ_ERQ8 field.
-#define BR_DMA_ERQ_ERQ8(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ8))
-#endif
-
-//! @brief Format value for bitfield DMA_ERQ_ERQ8.
-#define BF_DMA_ERQ_ERQ8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ8), uint32_t) & BM_DMA_ERQ_ERQ8)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERQ8 field to a new value.
-#define BW_DMA_ERQ_ERQ8(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ8) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERQ, field ERQ9[9] (RW)
- *
- * Values:
- * - 0 - The DMA request signal for the corresponding channel is disabled
- * - 1 - The DMA request signal for the corresponding channel is enabled
- */
-//@{
-#define BP_DMA_ERQ_ERQ9 (9U) //!< Bit position for DMA_ERQ_ERQ9.
-#define BM_DMA_ERQ_ERQ9 (0x00000200U) //!< Bit mask for DMA_ERQ_ERQ9.
-#define BS_DMA_ERQ_ERQ9 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ9.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERQ_ERQ9 field.
-#define BR_DMA_ERQ_ERQ9(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ9))
-#endif
-
-//! @brief Format value for bitfield DMA_ERQ_ERQ9.
-#define BF_DMA_ERQ_ERQ9(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ9), uint32_t) & BM_DMA_ERQ_ERQ9)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERQ9 field to a new value.
-#define BW_DMA_ERQ_ERQ9(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ9) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERQ, field ERQ10[10] (RW)
- *
- * Values:
- * - 0 - The DMA request signal for the corresponding channel is disabled
- * - 1 - The DMA request signal for the corresponding channel is enabled
- */
-//@{
-#define BP_DMA_ERQ_ERQ10 (10U) //!< Bit position for DMA_ERQ_ERQ10.
-#define BM_DMA_ERQ_ERQ10 (0x00000400U) //!< Bit mask for DMA_ERQ_ERQ10.
-#define BS_DMA_ERQ_ERQ10 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ10.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERQ_ERQ10 field.
-#define BR_DMA_ERQ_ERQ10(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ10))
-#endif
-
-//! @brief Format value for bitfield DMA_ERQ_ERQ10.
-#define BF_DMA_ERQ_ERQ10(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ10), uint32_t) & BM_DMA_ERQ_ERQ10)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERQ10 field to a new value.
-#define BW_DMA_ERQ_ERQ10(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ10) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERQ, field ERQ11[11] (RW)
- *
- * Values:
- * - 0 - The DMA request signal for the corresponding channel is disabled
- * - 1 - The DMA request signal for the corresponding channel is enabled
- */
-//@{
-#define BP_DMA_ERQ_ERQ11 (11U) //!< Bit position for DMA_ERQ_ERQ11.
-#define BM_DMA_ERQ_ERQ11 (0x00000800U) //!< Bit mask for DMA_ERQ_ERQ11.
-#define BS_DMA_ERQ_ERQ11 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ11.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERQ_ERQ11 field.
-#define BR_DMA_ERQ_ERQ11(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ11))
-#endif
-
-//! @brief Format value for bitfield DMA_ERQ_ERQ11.
-#define BF_DMA_ERQ_ERQ11(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ11), uint32_t) & BM_DMA_ERQ_ERQ11)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERQ11 field to a new value.
-#define BW_DMA_ERQ_ERQ11(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ11) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERQ, field ERQ12[12] (RW)
- *
- * Values:
- * - 0 - The DMA request signal for the corresponding channel is disabled
- * - 1 - The DMA request signal for the corresponding channel is enabled
- */
-//@{
-#define BP_DMA_ERQ_ERQ12 (12U) //!< Bit position for DMA_ERQ_ERQ12.
-#define BM_DMA_ERQ_ERQ12 (0x00001000U) //!< Bit mask for DMA_ERQ_ERQ12.
-#define BS_DMA_ERQ_ERQ12 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ12.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERQ_ERQ12 field.
-#define BR_DMA_ERQ_ERQ12(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ12))
-#endif
-
-//! @brief Format value for bitfield DMA_ERQ_ERQ12.
-#define BF_DMA_ERQ_ERQ12(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ12), uint32_t) & BM_DMA_ERQ_ERQ12)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERQ12 field to a new value.
-#define BW_DMA_ERQ_ERQ12(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ12) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERQ, field ERQ13[13] (RW)
- *
- * Values:
- * - 0 - The DMA request signal for the corresponding channel is disabled
- * - 1 - The DMA request signal for the corresponding channel is enabled
- */
-//@{
-#define BP_DMA_ERQ_ERQ13 (13U) //!< Bit position for DMA_ERQ_ERQ13.
-#define BM_DMA_ERQ_ERQ13 (0x00002000U) //!< Bit mask for DMA_ERQ_ERQ13.
-#define BS_DMA_ERQ_ERQ13 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ13.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERQ_ERQ13 field.
-#define BR_DMA_ERQ_ERQ13(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ13))
-#endif
-
-//! @brief Format value for bitfield DMA_ERQ_ERQ13.
-#define BF_DMA_ERQ_ERQ13(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ13), uint32_t) & BM_DMA_ERQ_ERQ13)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERQ13 field to a new value.
-#define BW_DMA_ERQ_ERQ13(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ13) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERQ, field ERQ14[14] (RW)
- *
- * Values:
- * - 0 - The DMA request signal for the corresponding channel is disabled
- * - 1 - The DMA request signal for the corresponding channel is enabled
- */
-//@{
-#define BP_DMA_ERQ_ERQ14 (14U) //!< Bit position for DMA_ERQ_ERQ14.
-#define BM_DMA_ERQ_ERQ14 (0x00004000U) //!< Bit mask for DMA_ERQ_ERQ14.
-#define BS_DMA_ERQ_ERQ14 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ14.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERQ_ERQ14 field.
-#define BR_DMA_ERQ_ERQ14(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ14))
-#endif
-
-//! @brief Format value for bitfield DMA_ERQ_ERQ14.
-#define BF_DMA_ERQ_ERQ14(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ14), uint32_t) & BM_DMA_ERQ_ERQ14)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERQ14 field to a new value.
-#define BW_DMA_ERQ_ERQ14(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ14) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERQ, field ERQ15[15] (RW)
- *
- * Values:
- * - 0 - The DMA request signal for the corresponding channel is disabled
- * - 1 - The DMA request signal for the corresponding channel is enabled
- */
-//@{
-#define BP_DMA_ERQ_ERQ15 (15U) //!< Bit position for DMA_ERQ_ERQ15.
-#define BM_DMA_ERQ_ERQ15 (0x00008000U) //!< Bit mask for DMA_ERQ_ERQ15.
-#define BS_DMA_ERQ_ERQ15 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ15.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERQ_ERQ15 field.
-#define BR_DMA_ERQ_ERQ15(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ15))
-#endif
-
-//! @brief Format value for bitfield DMA_ERQ_ERQ15.
-#define BF_DMA_ERQ_ERQ15(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ15), uint32_t) & BM_DMA_ERQ_ERQ15)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERQ15 field to a new value.
-#define BW_DMA_ERQ_ERQ15(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ15) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_DMA_EEI - Enable Error Interrupt Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_EEI - Enable Error Interrupt Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * The EEI register provides a bit map for the 16 channels to enable the error
- * interrupt signal for each channel. The state of any given channel's error
- * interrupt enable is directly affected by writes to this register; it is also
- * affected by writes to the SEEI and CEEI. The {S,C}EEI are provided so the error
- * interrupt enable for a single channel can easily be modified without the need to
- * perform a read-modify-write sequence to the EEI register. The DMA error
- * indicator and the error interrupt enable flag must be asserted before an error
- * interrupt request for a given channel is asserted to the interrupt controller.
- */
-typedef union _hw_dma_eei
-{
- uint32_t U;
- struct _hw_dma_eei_bitfields
- {
- uint32_t EEI0 : 1; //!< [0] Enable Error Interrupt 0
- uint32_t EEI1 : 1; //!< [1] Enable Error Interrupt 1
- uint32_t EEI2 : 1; //!< [2] Enable Error Interrupt 2
- uint32_t EEI3 : 1; //!< [3] Enable Error Interrupt 3
- uint32_t EEI4 : 1; //!< [4] Enable Error Interrupt 4
- uint32_t EEI5 : 1; //!< [5] Enable Error Interrupt 5
- uint32_t EEI6 : 1; //!< [6] Enable Error Interrupt 6
- uint32_t EEI7 : 1; //!< [7] Enable Error Interrupt 7
- uint32_t EEI8 : 1; //!< [8] Enable Error Interrupt 8
- uint32_t EEI9 : 1; //!< [9] Enable Error Interrupt 9
- uint32_t EEI10 : 1; //!< [10] Enable Error Interrupt 10
- uint32_t EEI11 : 1; //!< [11] Enable Error Interrupt 11
- uint32_t EEI12 : 1; //!< [12] Enable Error Interrupt 12
- uint32_t EEI13 : 1; //!< [13] Enable Error Interrupt 13
- uint32_t EEI14 : 1; //!< [14] Enable Error Interrupt 14
- uint32_t EEI15 : 1; //!< [15] Enable Error Interrupt 15
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_dma_eei_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_EEI register
- */
-//@{
-#define HW_DMA_EEI_ADDR(x) (REGS_DMA_BASE(x) + 0x14U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_EEI(x) (*(__IO hw_dma_eei_t *) HW_DMA_EEI_ADDR(x))
-#define HW_DMA_EEI_RD(x) (HW_DMA_EEI(x).U)
-#define HW_DMA_EEI_WR(x, v) (HW_DMA_EEI(x).U = (v))
-#define HW_DMA_EEI_SET(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) | (v)))
-#define HW_DMA_EEI_CLR(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) & ~(v)))
-#define HW_DMA_EEI_TOG(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_EEI bitfields
- */
-
-/*!
- * @name Register DMA_EEI, field EEI0[0] (RW)
- *
- * Values:
- * - 0 - The error signal for corresponding channel does not generate an error
- * interrupt
- * - 1 - The assertion of the error signal for corresponding channel generates
- * an error interrupt request
- */
-//@{
-#define BP_DMA_EEI_EEI0 (0U) //!< Bit position for DMA_EEI_EEI0.
-#define BM_DMA_EEI_EEI0 (0x00000001U) //!< Bit mask for DMA_EEI_EEI0.
-#define BS_DMA_EEI_EEI0 (1U) //!< Bit field size in bits for DMA_EEI_EEI0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_EEI_EEI0 field.
-#define BR_DMA_EEI_EEI0(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI0))
-#endif
-
-//! @brief Format value for bitfield DMA_EEI_EEI0.
-#define BF_DMA_EEI_EEI0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI0), uint32_t) & BM_DMA_EEI_EEI0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EEI0 field to a new value.
-#define BW_DMA_EEI_EEI0(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_EEI, field EEI1[1] (RW)
- *
- * Values:
- * - 0 - The error signal for corresponding channel does not generate an error
- * interrupt
- * - 1 - The assertion of the error signal for corresponding channel generates
- * an error interrupt request
- */
-//@{
-#define BP_DMA_EEI_EEI1 (1U) //!< Bit position for DMA_EEI_EEI1.
-#define BM_DMA_EEI_EEI1 (0x00000002U) //!< Bit mask for DMA_EEI_EEI1.
-#define BS_DMA_EEI_EEI1 (1U) //!< Bit field size in bits for DMA_EEI_EEI1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_EEI_EEI1 field.
-#define BR_DMA_EEI_EEI1(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI1))
-#endif
-
-//! @brief Format value for bitfield DMA_EEI_EEI1.
-#define BF_DMA_EEI_EEI1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI1), uint32_t) & BM_DMA_EEI_EEI1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EEI1 field to a new value.
-#define BW_DMA_EEI_EEI1(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_EEI, field EEI2[2] (RW)
- *
- * Values:
- * - 0 - The error signal for corresponding channel does not generate an error
- * interrupt
- * - 1 - The assertion of the error signal for corresponding channel generates
- * an error interrupt request
- */
-//@{
-#define BP_DMA_EEI_EEI2 (2U) //!< Bit position for DMA_EEI_EEI2.
-#define BM_DMA_EEI_EEI2 (0x00000004U) //!< Bit mask for DMA_EEI_EEI2.
-#define BS_DMA_EEI_EEI2 (1U) //!< Bit field size in bits for DMA_EEI_EEI2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_EEI_EEI2 field.
-#define BR_DMA_EEI_EEI2(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI2))
-#endif
-
-//! @brief Format value for bitfield DMA_EEI_EEI2.
-#define BF_DMA_EEI_EEI2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI2), uint32_t) & BM_DMA_EEI_EEI2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EEI2 field to a new value.
-#define BW_DMA_EEI_EEI2(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_EEI, field EEI3[3] (RW)
- *
- * Values:
- * - 0 - The error signal for corresponding channel does not generate an error
- * interrupt
- * - 1 - The assertion of the error signal for corresponding channel generates
- * an error interrupt request
- */
-//@{
-#define BP_DMA_EEI_EEI3 (3U) //!< Bit position for DMA_EEI_EEI3.
-#define BM_DMA_EEI_EEI3 (0x00000008U) //!< Bit mask for DMA_EEI_EEI3.
-#define BS_DMA_EEI_EEI3 (1U) //!< Bit field size in bits for DMA_EEI_EEI3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_EEI_EEI3 field.
-#define BR_DMA_EEI_EEI3(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI3))
-#endif
-
-//! @brief Format value for bitfield DMA_EEI_EEI3.
-#define BF_DMA_EEI_EEI3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI3), uint32_t) & BM_DMA_EEI_EEI3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EEI3 field to a new value.
-#define BW_DMA_EEI_EEI3(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_EEI, field EEI4[4] (RW)
- *
- * Values:
- * - 0 - The error signal for corresponding channel does not generate an error
- * interrupt
- * - 1 - The assertion of the error signal for corresponding channel generates
- * an error interrupt request
- */
-//@{
-#define BP_DMA_EEI_EEI4 (4U) //!< Bit position for DMA_EEI_EEI4.
-#define BM_DMA_EEI_EEI4 (0x00000010U) //!< Bit mask for DMA_EEI_EEI4.
-#define BS_DMA_EEI_EEI4 (1U) //!< Bit field size in bits for DMA_EEI_EEI4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_EEI_EEI4 field.
-#define BR_DMA_EEI_EEI4(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI4))
-#endif
-
-//! @brief Format value for bitfield DMA_EEI_EEI4.
-#define BF_DMA_EEI_EEI4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI4), uint32_t) & BM_DMA_EEI_EEI4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EEI4 field to a new value.
-#define BW_DMA_EEI_EEI4(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_EEI, field EEI5[5] (RW)
- *
- * Values:
- * - 0 - The error signal for corresponding channel does not generate an error
- * interrupt
- * - 1 - The assertion of the error signal for corresponding channel generates
- * an error interrupt request
- */
-//@{
-#define BP_DMA_EEI_EEI5 (5U) //!< Bit position for DMA_EEI_EEI5.
-#define BM_DMA_EEI_EEI5 (0x00000020U) //!< Bit mask for DMA_EEI_EEI5.
-#define BS_DMA_EEI_EEI5 (1U) //!< Bit field size in bits for DMA_EEI_EEI5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_EEI_EEI5 field.
-#define BR_DMA_EEI_EEI5(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI5))
-#endif
-
-//! @brief Format value for bitfield DMA_EEI_EEI5.
-#define BF_DMA_EEI_EEI5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI5), uint32_t) & BM_DMA_EEI_EEI5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EEI5 field to a new value.
-#define BW_DMA_EEI_EEI5(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_EEI, field EEI6[6] (RW)
- *
- * Values:
- * - 0 - The error signal for corresponding channel does not generate an error
- * interrupt
- * - 1 - The assertion of the error signal for corresponding channel generates
- * an error interrupt request
- */
-//@{
-#define BP_DMA_EEI_EEI6 (6U) //!< Bit position for DMA_EEI_EEI6.
-#define BM_DMA_EEI_EEI6 (0x00000040U) //!< Bit mask for DMA_EEI_EEI6.
-#define BS_DMA_EEI_EEI6 (1U) //!< Bit field size in bits for DMA_EEI_EEI6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_EEI_EEI6 field.
-#define BR_DMA_EEI_EEI6(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI6))
-#endif
-
-//! @brief Format value for bitfield DMA_EEI_EEI6.
-#define BF_DMA_EEI_EEI6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI6), uint32_t) & BM_DMA_EEI_EEI6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EEI6 field to a new value.
-#define BW_DMA_EEI_EEI6(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_EEI, field EEI7[7] (RW)
- *
- * Values:
- * - 0 - The error signal for corresponding channel does not generate an error
- * interrupt
- * - 1 - The assertion of the error signal for corresponding channel generates
- * an error interrupt request
- */
-//@{
-#define BP_DMA_EEI_EEI7 (7U) //!< Bit position for DMA_EEI_EEI7.
-#define BM_DMA_EEI_EEI7 (0x00000080U) //!< Bit mask for DMA_EEI_EEI7.
-#define BS_DMA_EEI_EEI7 (1U) //!< Bit field size in bits for DMA_EEI_EEI7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_EEI_EEI7 field.
-#define BR_DMA_EEI_EEI7(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI7))
-#endif
-
-//! @brief Format value for bitfield DMA_EEI_EEI7.
-#define BF_DMA_EEI_EEI7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI7), uint32_t) & BM_DMA_EEI_EEI7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EEI7 field to a new value.
-#define BW_DMA_EEI_EEI7(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_EEI, field EEI8[8] (RW)
- *
- * Values:
- * - 0 - The error signal for corresponding channel does not generate an error
- * interrupt
- * - 1 - The assertion of the error signal for corresponding channel generates
- * an error interrupt request
- */
-//@{
-#define BP_DMA_EEI_EEI8 (8U) //!< Bit position for DMA_EEI_EEI8.
-#define BM_DMA_EEI_EEI8 (0x00000100U) //!< Bit mask for DMA_EEI_EEI8.
-#define BS_DMA_EEI_EEI8 (1U) //!< Bit field size in bits for DMA_EEI_EEI8.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_EEI_EEI8 field.
-#define BR_DMA_EEI_EEI8(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI8))
-#endif
-
-//! @brief Format value for bitfield DMA_EEI_EEI8.
-#define BF_DMA_EEI_EEI8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI8), uint32_t) & BM_DMA_EEI_EEI8)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EEI8 field to a new value.
-#define BW_DMA_EEI_EEI8(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI8) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_EEI, field EEI9[9] (RW)
- *
- * Values:
- * - 0 - The error signal for corresponding channel does not generate an error
- * interrupt
- * - 1 - The assertion of the error signal for corresponding channel generates
- * an error interrupt request
- */
-//@{
-#define BP_DMA_EEI_EEI9 (9U) //!< Bit position for DMA_EEI_EEI9.
-#define BM_DMA_EEI_EEI9 (0x00000200U) //!< Bit mask for DMA_EEI_EEI9.
-#define BS_DMA_EEI_EEI9 (1U) //!< Bit field size in bits for DMA_EEI_EEI9.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_EEI_EEI9 field.
-#define BR_DMA_EEI_EEI9(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI9))
-#endif
-
-//! @brief Format value for bitfield DMA_EEI_EEI9.
-#define BF_DMA_EEI_EEI9(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI9), uint32_t) & BM_DMA_EEI_EEI9)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EEI9 field to a new value.
-#define BW_DMA_EEI_EEI9(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI9) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_EEI, field EEI10[10] (RW)
- *
- * Values:
- * - 0 - The error signal for corresponding channel does not generate an error
- * interrupt
- * - 1 - The assertion of the error signal for corresponding channel generates
- * an error interrupt request
- */
-//@{
-#define BP_DMA_EEI_EEI10 (10U) //!< Bit position for DMA_EEI_EEI10.
-#define BM_DMA_EEI_EEI10 (0x00000400U) //!< Bit mask for DMA_EEI_EEI10.
-#define BS_DMA_EEI_EEI10 (1U) //!< Bit field size in bits for DMA_EEI_EEI10.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_EEI_EEI10 field.
-#define BR_DMA_EEI_EEI10(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI10))
-#endif
-
-//! @brief Format value for bitfield DMA_EEI_EEI10.
-#define BF_DMA_EEI_EEI10(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI10), uint32_t) & BM_DMA_EEI_EEI10)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EEI10 field to a new value.
-#define BW_DMA_EEI_EEI10(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI10) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_EEI, field EEI11[11] (RW)
- *
- * Values:
- * - 0 - The error signal for corresponding channel does not generate an error
- * interrupt
- * - 1 - The assertion of the error signal for corresponding channel generates
- * an error interrupt request
- */
-//@{
-#define BP_DMA_EEI_EEI11 (11U) //!< Bit position for DMA_EEI_EEI11.
-#define BM_DMA_EEI_EEI11 (0x00000800U) //!< Bit mask for DMA_EEI_EEI11.
-#define BS_DMA_EEI_EEI11 (1U) //!< Bit field size in bits for DMA_EEI_EEI11.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_EEI_EEI11 field.
-#define BR_DMA_EEI_EEI11(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI11))
-#endif
-
-//! @brief Format value for bitfield DMA_EEI_EEI11.
-#define BF_DMA_EEI_EEI11(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI11), uint32_t) & BM_DMA_EEI_EEI11)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EEI11 field to a new value.
-#define BW_DMA_EEI_EEI11(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI11) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_EEI, field EEI12[12] (RW)
- *
- * Values:
- * - 0 - The error signal for corresponding channel does not generate an error
- * interrupt
- * - 1 - The assertion of the error signal for corresponding channel generates
- * an error interrupt request
- */
-//@{
-#define BP_DMA_EEI_EEI12 (12U) //!< Bit position for DMA_EEI_EEI12.
-#define BM_DMA_EEI_EEI12 (0x00001000U) //!< Bit mask for DMA_EEI_EEI12.
-#define BS_DMA_EEI_EEI12 (1U) //!< Bit field size in bits for DMA_EEI_EEI12.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_EEI_EEI12 field.
-#define BR_DMA_EEI_EEI12(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI12))
-#endif
-
-//! @brief Format value for bitfield DMA_EEI_EEI12.
-#define BF_DMA_EEI_EEI12(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI12), uint32_t) & BM_DMA_EEI_EEI12)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EEI12 field to a new value.
-#define BW_DMA_EEI_EEI12(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI12) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_EEI, field EEI13[13] (RW)
- *
- * Values:
- * - 0 - The error signal for corresponding channel does not generate an error
- * interrupt
- * - 1 - The assertion of the error signal for corresponding channel generates
- * an error interrupt request
- */
-//@{
-#define BP_DMA_EEI_EEI13 (13U) //!< Bit position for DMA_EEI_EEI13.
-#define BM_DMA_EEI_EEI13 (0x00002000U) //!< Bit mask for DMA_EEI_EEI13.
-#define BS_DMA_EEI_EEI13 (1U) //!< Bit field size in bits for DMA_EEI_EEI13.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_EEI_EEI13 field.
-#define BR_DMA_EEI_EEI13(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI13))
-#endif
-
-//! @brief Format value for bitfield DMA_EEI_EEI13.
-#define BF_DMA_EEI_EEI13(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI13), uint32_t) & BM_DMA_EEI_EEI13)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EEI13 field to a new value.
-#define BW_DMA_EEI_EEI13(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI13) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_EEI, field EEI14[14] (RW)
- *
- * Values:
- * - 0 - The error signal for corresponding channel does not generate an error
- * interrupt
- * - 1 - The assertion of the error signal for corresponding channel generates
- * an error interrupt request
- */
-//@{
-#define BP_DMA_EEI_EEI14 (14U) //!< Bit position for DMA_EEI_EEI14.
-#define BM_DMA_EEI_EEI14 (0x00004000U) //!< Bit mask for DMA_EEI_EEI14.
-#define BS_DMA_EEI_EEI14 (1U) //!< Bit field size in bits for DMA_EEI_EEI14.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_EEI_EEI14 field.
-#define BR_DMA_EEI_EEI14(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI14))
-#endif
-
-//! @brief Format value for bitfield DMA_EEI_EEI14.
-#define BF_DMA_EEI_EEI14(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI14), uint32_t) & BM_DMA_EEI_EEI14)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EEI14 field to a new value.
-#define BW_DMA_EEI_EEI14(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI14) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_EEI, field EEI15[15] (RW)
- *
- * Values:
- * - 0 - The error signal for corresponding channel does not generate an error
- * interrupt
- * - 1 - The assertion of the error signal for corresponding channel generates
- * an error interrupt request
- */
-//@{
-#define BP_DMA_EEI_EEI15 (15U) //!< Bit position for DMA_EEI_EEI15.
-#define BM_DMA_EEI_EEI15 (0x00008000U) //!< Bit mask for DMA_EEI_EEI15.
-#define BS_DMA_EEI_EEI15 (1U) //!< Bit field size in bits for DMA_EEI_EEI15.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_EEI_EEI15 field.
-#define BR_DMA_EEI_EEI15(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI15))
-#endif
-
-//! @brief Format value for bitfield DMA_EEI_EEI15.
-#define BF_DMA_EEI_EEI15(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI15), uint32_t) & BM_DMA_EEI_EEI15)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EEI15 field to a new value.
-#define BW_DMA_EEI_EEI15(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI15) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_DMA_CEEI - Clear Enable Error Interrupt Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_CEEI - Clear Enable Error Interrupt Register (WO)
- *
- * Reset value: 0x00U
- *
- * The CEEI provides a simple memory-mapped mechanism to clear a given bit in
- * the EEI to disable the error interrupt for a given channel. The data value on a
- * register write causes the corresponding bit in the EEI to be cleared. Setting
- * the CAEE bit provides a global clear function, forcing the EEI contents to be
- * cleared, disabling all DMA request inputs. If the NOP bit is set, the command
- * is ignored. This allows you to write multiple-byte registers as a 32-bit word.
- * Reads of this register return all zeroes.
- */
-typedef union _hw_dma_ceei
-{
- uint8_t U;
- struct _hw_dma_ceei_bitfields
- {
- uint8_t CEEI : 4; //!< [3:0] Clear Enable Error Interrupt
- uint8_t RESERVED0 : 2; //!< [5:4]
- uint8_t CAEE : 1; //!< [6] Clear All Enable Error Interrupts
- uint8_t NOP : 1; //!< [7] No Op enable
- } B;
-} hw_dma_ceei_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_CEEI register
- */
-//@{
-#define HW_DMA_CEEI_ADDR(x) (REGS_DMA_BASE(x) + 0x18U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_CEEI(x) (*(__O hw_dma_ceei_t *) HW_DMA_CEEI_ADDR(x))
-#define HW_DMA_CEEI_RD(x) (HW_DMA_CEEI(x).U)
-#define HW_DMA_CEEI_WR(x, v) (HW_DMA_CEEI(x).U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_CEEI bitfields
- */
-
-/*!
- * @name Register DMA_CEEI, field CEEI[3:0] (WORZ)
- *
- * Clears the corresponding bit in EEI
- */
-//@{
-#define BP_DMA_CEEI_CEEI (0U) //!< Bit position for DMA_CEEI_CEEI.
-#define BM_DMA_CEEI_CEEI (0x0FU) //!< Bit mask for DMA_CEEI_CEEI.
-#define BS_DMA_CEEI_CEEI (4U) //!< Bit field size in bits for DMA_CEEI_CEEI.
-
-//! @brief Format value for bitfield DMA_CEEI_CEEI.
-#define BF_DMA_CEEI_CEEI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CEEI_CEEI), uint8_t) & BM_DMA_CEEI_CEEI)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CEEI field to a new value.
-#define BW_DMA_CEEI_CEEI(x, v) (HW_DMA_CEEI_WR(x, (HW_DMA_CEEI_RD(x) & ~BM_DMA_CEEI_CEEI) | BF_DMA_CEEI_CEEI(v)))
-#endif
-//@}
-
-/*!
- * @name Register DMA_CEEI, field CAEE[6] (WORZ)
- *
- * Values:
- * - 0 - Clear only the EEI bit specified in the CEEI field
- * - 1 - Clear all bits in EEI
- */
-//@{
-#define BP_DMA_CEEI_CAEE (6U) //!< Bit position for DMA_CEEI_CAEE.
-#define BM_DMA_CEEI_CAEE (0x40U) //!< Bit mask for DMA_CEEI_CAEE.
-#define BS_DMA_CEEI_CAEE (1U) //!< Bit field size in bits for DMA_CEEI_CAEE.
-
-//! @brief Format value for bitfield DMA_CEEI_CAEE.
-#define BF_DMA_CEEI_CAEE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CEEI_CAEE), uint8_t) & BM_DMA_CEEI_CAEE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CAEE field to a new value.
-#define BW_DMA_CEEI_CAEE(x, v) (BITBAND_ACCESS8(HW_DMA_CEEI_ADDR(x), BP_DMA_CEEI_CAEE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_CEEI, field NOP[7] (WORZ)
- *
- * Values:
- * - 0 - Normal operation
- * - 1 - No operation, ignore the other bits in this register
- */
-//@{
-#define BP_DMA_CEEI_NOP (7U) //!< Bit position for DMA_CEEI_NOP.
-#define BM_DMA_CEEI_NOP (0x80U) //!< Bit mask for DMA_CEEI_NOP.
-#define BS_DMA_CEEI_NOP (1U) //!< Bit field size in bits for DMA_CEEI_NOP.
-
-//! @brief Format value for bitfield DMA_CEEI_NOP.
-#define BF_DMA_CEEI_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CEEI_NOP), uint8_t) & BM_DMA_CEEI_NOP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the NOP field to a new value.
-#define BW_DMA_CEEI_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CEEI_ADDR(x), BP_DMA_CEEI_NOP) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_DMA_SEEI - Set Enable Error Interrupt Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_SEEI - Set Enable Error Interrupt Register (WO)
- *
- * Reset value: 0x00U
- *
- * The SEEI provides a simple memory-mapped mechanism to set a given bit in the
- * EEI to enable the error interrupt for a given channel. The data value on a
- * register write causes the corresponding bit in the EEI to be set. Setting the
- * SAEE bit provides a global set function, forcing the entire EEI contents to be
- * set. If the NOP bit is set, the command is ignored. This allows you to write
- * multiple-byte registers as a 32-bit word. Reads of this register return all
- * zeroes.
- */
-typedef union _hw_dma_seei
-{
- uint8_t U;
- struct _hw_dma_seei_bitfields
- {
- uint8_t SEEI : 4; //!< [3:0] Set Enable Error Interrupt
- uint8_t RESERVED0 : 2; //!< [5:4]
- uint8_t SAEE : 1; //!< [6] Sets All Enable Error Interrupts
- uint8_t NOP : 1; //!< [7] No Op enable
- } B;
-} hw_dma_seei_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_SEEI register
- */
-//@{
-#define HW_DMA_SEEI_ADDR(x) (REGS_DMA_BASE(x) + 0x19U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_SEEI(x) (*(__O hw_dma_seei_t *) HW_DMA_SEEI_ADDR(x))
-#define HW_DMA_SEEI_RD(x) (HW_DMA_SEEI(x).U)
-#define HW_DMA_SEEI_WR(x, v) (HW_DMA_SEEI(x).U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_SEEI bitfields
- */
-
-/*!
- * @name Register DMA_SEEI, field SEEI[3:0] (WORZ)
- *
- * Sets the corresponding bit in EEI
- */
-//@{
-#define BP_DMA_SEEI_SEEI (0U) //!< Bit position for DMA_SEEI_SEEI.
-#define BM_DMA_SEEI_SEEI (0x0FU) //!< Bit mask for DMA_SEEI_SEEI.
-#define BS_DMA_SEEI_SEEI (4U) //!< Bit field size in bits for DMA_SEEI_SEEI.
-
-//! @brief Format value for bitfield DMA_SEEI_SEEI.
-#define BF_DMA_SEEI_SEEI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SEEI_SEEI), uint8_t) & BM_DMA_SEEI_SEEI)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SEEI field to a new value.
-#define BW_DMA_SEEI_SEEI(x, v) (HW_DMA_SEEI_WR(x, (HW_DMA_SEEI_RD(x) & ~BM_DMA_SEEI_SEEI) | BF_DMA_SEEI_SEEI(v)))
-#endif
-//@}
-
-/*!
- * @name Register DMA_SEEI, field SAEE[6] (WORZ)
- *
- * Values:
- * - 0 - Set only the EEI bit specified in the SEEI field.
- * - 1 - Sets all bits in EEI
- */
-//@{
-#define BP_DMA_SEEI_SAEE (6U) //!< Bit position for DMA_SEEI_SAEE.
-#define BM_DMA_SEEI_SAEE (0x40U) //!< Bit mask for DMA_SEEI_SAEE.
-#define BS_DMA_SEEI_SAEE (1U) //!< Bit field size in bits for DMA_SEEI_SAEE.
-
-//! @brief Format value for bitfield DMA_SEEI_SAEE.
-#define BF_DMA_SEEI_SAEE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SEEI_SAEE), uint8_t) & BM_DMA_SEEI_SAEE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SAEE field to a new value.
-#define BW_DMA_SEEI_SAEE(x, v) (BITBAND_ACCESS8(HW_DMA_SEEI_ADDR(x), BP_DMA_SEEI_SAEE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_SEEI, field NOP[7] (WORZ)
- *
- * Values:
- * - 0 - Normal operation
- * - 1 - No operation, ignore the other bits in this register
- */
-//@{
-#define BP_DMA_SEEI_NOP (7U) //!< Bit position for DMA_SEEI_NOP.
-#define BM_DMA_SEEI_NOP (0x80U) //!< Bit mask for DMA_SEEI_NOP.
-#define BS_DMA_SEEI_NOP (1U) //!< Bit field size in bits for DMA_SEEI_NOP.
-
-//! @brief Format value for bitfield DMA_SEEI_NOP.
-#define BF_DMA_SEEI_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SEEI_NOP), uint8_t) & BM_DMA_SEEI_NOP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the NOP field to a new value.
-#define BW_DMA_SEEI_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SEEI_ADDR(x), BP_DMA_SEEI_NOP) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_DMA_CERQ - Clear Enable Request Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_CERQ - Clear Enable Request Register (WO)
- *
- * Reset value: 0x00U
- *
- * The CERQ provides a simple memory-mapped mechanism to clear a given bit in
- * the ERQ to disable the DMA request for a given channel. The data value on a
- * register write causes the corresponding bit in the ERQ to be cleared. Setting the
- * CAER bit provides a global clear function, forcing the entire contents of the
- * ERQ to be cleared, disabling all DMA request inputs. If NOP is set, the
- * command is ignored. This allows you to write multiple-byte registers as a 32-bit
- * word. Reads of this register return all zeroes.
- */
-typedef union _hw_dma_cerq
-{
- uint8_t U;
- struct _hw_dma_cerq_bitfields
- {
- uint8_t CERQ : 4; //!< [3:0] Clear Enable Request
- uint8_t RESERVED0 : 2; //!< [5:4]
- uint8_t CAER : 1; //!< [6] Clear All Enable Requests
- uint8_t NOP : 1; //!< [7] No Op enable
- } B;
-} hw_dma_cerq_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_CERQ register
- */
-//@{
-#define HW_DMA_CERQ_ADDR(x) (REGS_DMA_BASE(x) + 0x1AU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_CERQ(x) (*(__O hw_dma_cerq_t *) HW_DMA_CERQ_ADDR(x))
-#define HW_DMA_CERQ_RD(x) (HW_DMA_CERQ(x).U)
-#define HW_DMA_CERQ_WR(x, v) (HW_DMA_CERQ(x).U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_CERQ bitfields
- */
-
-/*!
- * @name Register DMA_CERQ, field CERQ[3:0] (WORZ)
- *
- * Clears the corresponding bit in ERQ
- */
-//@{
-#define BP_DMA_CERQ_CERQ (0U) //!< Bit position for DMA_CERQ_CERQ.
-#define BM_DMA_CERQ_CERQ (0x0FU) //!< Bit mask for DMA_CERQ_CERQ.
-#define BS_DMA_CERQ_CERQ (4U) //!< Bit field size in bits for DMA_CERQ_CERQ.
-
-//! @brief Format value for bitfield DMA_CERQ_CERQ.
-#define BF_DMA_CERQ_CERQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERQ_CERQ), uint8_t) & BM_DMA_CERQ_CERQ)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CERQ field to a new value.
-#define BW_DMA_CERQ_CERQ(x, v) (HW_DMA_CERQ_WR(x, (HW_DMA_CERQ_RD(x) & ~BM_DMA_CERQ_CERQ) | BF_DMA_CERQ_CERQ(v)))
-#endif
-//@}
-
-/*!
- * @name Register DMA_CERQ, field CAER[6] (WORZ)
- *
- * Values:
- * - 0 - Clear only the ERQ bit specified in the CERQ field
- * - 1 - Clear all bits in ERQ
- */
-//@{
-#define BP_DMA_CERQ_CAER (6U) //!< Bit position for DMA_CERQ_CAER.
-#define BM_DMA_CERQ_CAER (0x40U) //!< Bit mask for DMA_CERQ_CAER.
-#define BS_DMA_CERQ_CAER (1U) //!< Bit field size in bits for DMA_CERQ_CAER.
-
-//! @brief Format value for bitfield DMA_CERQ_CAER.
-#define BF_DMA_CERQ_CAER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERQ_CAER), uint8_t) & BM_DMA_CERQ_CAER)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CAER field to a new value.
-#define BW_DMA_CERQ_CAER(x, v) (BITBAND_ACCESS8(HW_DMA_CERQ_ADDR(x), BP_DMA_CERQ_CAER) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_CERQ, field NOP[7] (WORZ)
- *
- * Values:
- * - 0 - Normal operation
- * - 1 - No operation, ignore the other bits in this register
- */
-//@{
-#define BP_DMA_CERQ_NOP (7U) //!< Bit position for DMA_CERQ_NOP.
-#define BM_DMA_CERQ_NOP (0x80U) //!< Bit mask for DMA_CERQ_NOP.
-#define BS_DMA_CERQ_NOP (1U) //!< Bit field size in bits for DMA_CERQ_NOP.
-
-//! @brief Format value for bitfield DMA_CERQ_NOP.
-#define BF_DMA_CERQ_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERQ_NOP), uint8_t) & BM_DMA_CERQ_NOP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the NOP field to a new value.
-#define BW_DMA_CERQ_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CERQ_ADDR(x), BP_DMA_CERQ_NOP) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_DMA_SERQ - Set Enable Request Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_SERQ - Set Enable Request Register (WO)
- *
- * Reset value: 0x00U
- *
- * The SERQ provides a simple memory-mapped mechanism to set a given bit in the
- * ERQ to enable the DMA request for a given channel. The data value on a
- * register write causes the corresponding bit in the ERQ to be set. Setting the SAER
- * bit provides a global set function, forcing the entire contents of ERQ to be
- * set. If the NOP bit is set, the command is ignored. This allows you to write
- * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
- */
-typedef union _hw_dma_serq
-{
- uint8_t U;
- struct _hw_dma_serq_bitfields
- {
- uint8_t SERQ : 4; //!< [3:0] Set enable request
- uint8_t RESERVED0 : 2; //!< [5:4]
- uint8_t SAER : 1; //!< [6] Set All Enable Requests
- uint8_t NOP : 1; //!< [7] No Op enable
- } B;
-} hw_dma_serq_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_SERQ register
- */
-//@{
-#define HW_DMA_SERQ_ADDR(x) (REGS_DMA_BASE(x) + 0x1BU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_SERQ(x) (*(__O hw_dma_serq_t *) HW_DMA_SERQ_ADDR(x))
-#define HW_DMA_SERQ_RD(x) (HW_DMA_SERQ(x).U)
-#define HW_DMA_SERQ_WR(x, v) (HW_DMA_SERQ(x).U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_SERQ bitfields
- */
-
-/*!
- * @name Register DMA_SERQ, field SERQ[3:0] (WORZ)
- *
- * Sets the corresponding bit in ERQ
- */
-//@{
-#define BP_DMA_SERQ_SERQ (0U) //!< Bit position for DMA_SERQ_SERQ.
-#define BM_DMA_SERQ_SERQ (0x0FU) //!< Bit mask for DMA_SERQ_SERQ.
-#define BS_DMA_SERQ_SERQ (4U) //!< Bit field size in bits for DMA_SERQ_SERQ.
-
-//! @brief Format value for bitfield DMA_SERQ_SERQ.
-#define BF_DMA_SERQ_SERQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SERQ_SERQ), uint8_t) & BM_DMA_SERQ_SERQ)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SERQ field to a new value.
-#define BW_DMA_SERQ_SERQ(x, v) (HW_DMA_SERQ_WR(x, (HW_DMA_SERQ_RD(x) & ~BM_DMA_SERQ_SERQ) | BF_DMA_SERQ_SERQ(v)))
-#endif
-//@}
-
-/*!
- * @name Register DMA_SERQ, field SAER[6] (WORZ)
- *
- * Values:
- * - 0 - Set only the ERQ bit specified in the SERQ field
- * - 1 - Set all bits in ERQ
- */
-//@{
-#define BP_DMA_SERQ_SAER (6U) //!< Bit position for DMA_SERQ_SAER.
-#define BM_DMA_SERQ_SAER (0x40U) //!< Bit mask for DMA_SERQ_SAER.
-#define BS_DMA_SERQ_SAER (1U) //!< Bit field size in bits for DMA_SERQ_SAER.
-
-//! @brief Format value for bitfield DMA_SERQ_SAER.
-#define BF_DMA_SERQ_SAER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SERQ_SAER), uint8_t) & BM_DMA_SERQ_SAER)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SAER field to a new value.
-#define BW_DMA_SERQ_SAER(x, v) (BITBAND_ACCESS8(HW_DMA_SERQ_ADDR(x), BP_DMA_SERQ_SAER) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_SERQ, field NOP[7] (WORZ)
- *
- * Values:
- * - 0 - Normal operation
- * - 1 - No operation, ignore the other bits in this register
- */
-//@{
-#define BP_DMA_SERQ_NOP (7U) //!< Bit position for DMA_SERQ_NOP.
-#define BM_DMA_SERQ_NOP (0x80U) //!< Bit mask for DMA_SERQ_NOP.
-#define BS_DMA_SERQ_NOP (1U) //!< Bit field size in bits for DMA_SERQ_NOP.
-
-//! @brief Format value for bitfield DMA_SERQ_NOP.
-#define BF_DMA_SERQ_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SERQ_NOP), uint8_t) & BM_DMA_SERQ_NOP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the NOP field to a new value.
-#define BW_DMA_SERQ_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SERQ_ADDR(x), BP_DMA_SERQ_NOP) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_DMA_CDNE - Clear DONE Status Bit Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_CDNE - Clear DONE Status Bit Register (WO)
- *
- * Reset value: 0x00U
- *
- * The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in
- * the TCD of the given channel. The data value on a register write causes the
- * DONE bit in the corresponding transfer control descriptor to be cleared. Setting
- * the CADN bit provides a global clear function, forcing all DONE bits to be
- * cleared. If the NOP bit is set, the command is ignored. This allows you to write
- * multiple-byte registers as a 32-bit word. Reads of this register return all
- * zeroes.
- */
-typedef union _hw_dma_cdne
-{
- uint8_t U;
- struct _hw_dma_cdne_bitfields
- {
- uint8_t CDNE : 4; //!< [3:0] Clear DONE Bit
- uint8_t RESERVED0 : 2; //!< [5:4]
- uint8_t CADN : 1; //!< [6] Clears All DONE Bits
- uint8_t NOP : 1; //!< [7] No Op enable
- } B;
-} hw_dma_cdne_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_CDNE register
- */
-//@{
-#define HW_DMA_CDNE_ADDR(x) (REGS_DMA_BASE(x) + 0x1CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_CDNE(x) (*(__O hw_dma_cdne_t *) HW_DMA_CDNE_ADDR(x))
-#define HW_DMA_CDNE_RD(x) (HW_DMA_CDNE(x).U)
-#define HW_DMA_CDNE_WR(x, v) (HW_DMA_CDNE(x).U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_CDNE bitfields
- */
-
-/*!
- * @name Register DMA_CDNE, field CDNE[3:0] (WORZ)
- *
- * Clears the corresponding bit in TCDn_CSR[DONE]
- */
-//@{
-#define BP_DMA_CDNE_CDNE (0U) //!< Bit position for DMA_CDNE_CDNE.
-#define BM_DMA_CDNE_CDNE (0x0FU) //!< Bit mask for DMA_CDNE_CDNE.
-#define BS_DMA_CDNE_CDNE (4U) //!< Bit field size in bits for DMA_CDNE_CDNE.
-
-//! @brief Format value for bitfield DMA_CDNE_CDNE.
-#define BF_DMA_CDNE_CDNE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CDNE_CDNE), uint8_t) & BM_DMA_CDNE_CDNE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CDNE field to a new value.
-#define BW_DMA_CDNE_CDNE(x, v) (HW_DMA_CDNE_WR(x, (HW_DMA_CDNE_RD(x) & ~BM_DMA_CDNE_CDNE) | BF_DMA_CDNE_CDNE(v)))
-#endif
-//@}
-
-/*!
- * @name Register DMA_CDNE, field CADN[6] (WORZ)
- *
- * Values:
- * - 0 - Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
- * - 1 - Clears all bits in TCDn_CSR[DONE]
- */
-//@{
-#define BP_DMA_CDNE_CADN (6U) //!< Bit position for DMA_CDNE_CADN.
-#define BM_DMA_CDNE_CADN (0x40U) //!< Bit mask for DMA_CDNE_CADN.
-#define BS_DMA_CDNE_CADN (1U) //!< Bit field size in bits for DMA_CDNE_CADN.
-
-//! @brief Format value for bitfield DMA_CDNE_CADN.
-#define BF_DMA_CDNE_CADN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CDNE_CADN), uint8_t) & BM_DMA_CDNE_CADN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CADN field to a new value.
-#define BW_DMA_CDNE_CADN(x, v) (BITBAND_ACCESS8(HW_DMA_CDNE_ADDR(x), BP_DMA_CDNE_CADN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_CDNE, field NOP[7] (WORZ)
- *
- * Values:
- * - 0 - Normal operation
- * - 1 - No operation, ignore the other bits in this register
- */
-//@{
-#define BP_DMA_CDNE_NOP (7U) //!< Bit position for DMA_CDNE_NOP.
-#define BM_DMA_CDNE_NOP (0x80U) //!< Bit mask for DMA_CDNE_NOP.
-#define BS_DMA_CDNE_NOP (1U) //!< Bit field size in bits for DMA_CDNE_NOP.
-
-//! @brief Format value for bitfield DMA_CDNE_NOP.
-#define BF_DMA_CDNE_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CDNE_NOP), uint8_t) & BM_DMA_CDNE_NOP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the NOP field to a new value.
-#define BW_DMA_CDNE_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CDNE_ADDR(x), BP_DMA_CDNE_NOP) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_DMA_SSRT - Set START Bit Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_SSRT - Set START Bit Register (WO)
- *
- * Reset value: 0x00U
- *
- * The SSRT provides a simple memory-mapped mechanism to set the START bit in
- * the TCD of the given channel. The data value on a register write causes the
- * START bit in the corresponding transfer control descriptor to be set. Setting the
- * SAST bit provides a global set function, forcing all START bits to be set. If
- * the NOP bit is set, the command is ignored. This allows you to write
- * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
- */
-typedef union _hw_dma_ssrt
-{
- uint8_t U;
- struct _hw_dma_ssrt_bitfields
- {
- uint8_t SSRT : 4; //!< [3:0] Set START Bit
- uint8_t RESERVED0 : 2; //!< [5:4]
- uint8_t SAST : 1; //!< [6] Set All START Bits (activates all channels)
- uint8_t NOP : 1; //!< [7] No Op enable
- } B;
-} hw_dma_ssrt_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_SSRT register
- */
-//@{
-#define HW_DMA_SSRT_ADDR(x) (REGS_DMA_BASE(x) + 0x1DU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_SSRT(x) (*(__O hw_dma_ssrt_t *) HW_DMA_SSRT_ADDR(x))
-#define HW_DMA_SSRT_RD(x) (HW_DMA_SSRT(x).U)
-#define HW_DMA_SSRT_WR(x, v) (HW_DMA_SSRT(x).U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_SSRT bitfields
- */
-
-/*!
- * @name Register DMA_SSRT, field SSRT[3:0] (WORZ)
- *
- * Sets the corresponding bit in TCDn_CSR[START]
- */
-//@{
-#define BP_DMA_SSRT_SSRT (0U) //!< Bit position for DMA_SSRT_SSRT.
-#define BM_DMA_SSRT_SSRT (0x0FU) //!< Bit mask for DMA_SSRT_SSRT.
-#define BS_DMA_SSRT_SSRT (4U) //!< Bit field size in bits for DMA_SSRT_SSRT.
-
-//! @brief Format value for bitfield DMA_SSRT_SSRT.
-#define BF_DMA_SSRT_SSRT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SSRT_SSRT), uint8_t) & BM_DMA_SSRT_SSRT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SSRT field to a new value.
-#define BW_DMA_SSRT_SSRT(x, v) (HW_DMA_SSRT_WR(x, (HW_DMA_SSRT_RD(x) & ~BM_DMA_SSRT_SSRT) | BF_DMA_SSRT_SSRT(v)))
-#endif
-//@}
-
-/*!
- * @name Register DMA_SSRT, field SAST[6] (WORZ)
- *
- * Values:
- * - 0 - Set only the TCDn_CSR[START] bit specified in the SSRT field
- * - 1 - Set all bits in TCDn_CSR[START]
- */
-//@{
-#define BP_DMA_SSRT_SAST (6U) //!< Bit position for DMA_SSRT_SAST.
-#define BM_DMA_SSRT_SAST (0x40U) //!< Bit mask for DMA_SSRT_SAST.
-#define BS_DMA_SSRT_SAST (1U) //!< Bit field size in bits for DMA_SSRT_SAST.
-
-//! @brief Format value for bitfield DMA_SSRT_SAST.
-#define BF_DMA_SSRT_SAST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SSRT_SAST), uint8_t) & BM_DMA_SSRT_SAST)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SAST field to a new value.
-#define BW_DMA_SSRT_SAST(x, v) (BITBAND_ACCESS8(HW_DMA_SSRT_ADDR(x), BP_DMA_SSRT_SAST) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_SSRT, field NOP[7] (WORZ)
- *
- * Values:
- * - 0 - Normal operation
- * - 1 - No operation, ignore the other bits in this register
- */
-//@{
-#define BP_DMA_SSRT_NOP (7U) //!< Bit position for DMA_SSRT_NOP.
-#define BM_DMA_SSRT_NOP (0x80U) //!< Bit mask for DMA_SSRT_NOP.
-#define BS_DMA_SSRT_NOP (1U) //!< Bit field size in bits for DMA_SSRT_NOP.
-
-//! @brief Format value for bitfield DMA_SSRT_NOP.
-#define BF_DMA_SSRT_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SSRT_NOP), uint8_t) & BM_DMA_SSRT_NOP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the NOP field to a new value.
-#define BW_DMA_SSRT_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SSRT_ADDR(x), BP_DMA_SSRT_NOP) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_DMA_CERR - Clear Error Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_CERR - Clear Error Register (WO)
- *
- * Reset value: 0x00U
- *
- * The CERR provides a simple memory-mapped mechanism to clear a given bit in
- * the ERR to disable the error condition flag for a given channel. The given value
- * on a register write causes the corresponding bit in the ERR to be cleared.
- * Setting the CAEI bit provides a global clear function, forcing the ERR contents
- * to be cleared, clearing all channel error indicators. If the NOP bit is set,
- * the command is ignored. This allows you to write multiple-byte registers as a
- * 32-bit word. Reads of this register return all zeroes.
- */
-typedef union _hw_dma_cerr
-{
- uint8_t U;
- struct _hw_dma_cerr_bitfields
- {
- uint8_t CERR : 4; //!< [3:0] Clear Error Indicator
- uint8_t RESERVED0 : 2; //!< [5:4]
- uint8_t CAEI : 1; //!< [6] Clear All Error Indicators
- uint8_t NOP : 1; //!< [7] No Op enable
- } B;
-} hw_dma_cerr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_CERR register
- */
-//@{
-#define HW_DMA_CERR_ADDR(x) (REGS_DMA_BASE(x) + 0x1EU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_CERR(x) (*(__O hw_dma_cerr_t *) HW_DMA_CERR_ADDR(x))
-#define HW_DMA_CERR_RD(x) (HW_DMA_CERR(x).U)
-#define HW_DMA_CERR_WR(x, v) (HW_DMA_CERR(x).U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_CERR bitfields
- */
-
-/*!
- * @name Register DMA_CERR, field CERR[3:0] (WORZ)
- *
- * Clears the corresponding bit in ERR
- */
-//@{
-#define BP_DMA_CERR_CERR (0U) //!< Bit position for DMA_CERR_CERR.
-#define BM_DMA_CERR_CERR (0x0FU) //!< Bit mask for DMA_CERR_CERR.
-#define BS_DMA_CERR_CERR (4U) //!< Bit field size in bits for DMA_CERR_CERR.
-
-//! @brief Format value for bitfield DMA_CERR_CERR.
-#define BF_DMA_CERR_CERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERR_CERR), uint8_t) & BM_DMA_CERR_CERR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CERR field to a new value.
-#define BW_DMA_CERR_CERR(x, v) (HW_DMA_CERR_WR(x, (HW_DMA_CERR_RD(x) & ~BM_DMA_CERR_CERR) | BF_DMA_CERR_CERR(v)))
-#endif
-//@}
-
-/*!
- * @name Register DMA_CERR, field CAEI[6] (WORZ)
- *
- * Values:
- * - 0 - Clear only the ERR bit specified in the CERR field
- * - 1 - Clear all bits in ERR
- */
-//@{
-#define BP_DMA_CERR_CAEI (6U) //!< Bit position for DMA_CERR_CAEI.
-#define BM_DMA_CERR_CAEI (0x40U) //!< Bit mask for DMA_CERR_CAEI.
-#define BS_DMA_CERR_CAEI (1U) //!< Bit field size in bits for DMA_CERR_CAEI.
-
-//! @brief Format value for bitfield DMA_CERR_CAEI.
-#define BF_DMA_CERR_CAEI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERR_CAEI), uint8_t) & BM_DMA_CERR_CAEI)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CAEI field to a new value.
-#define BW_DMA_CERR_CAEI(x, v) (BITBAND_ACCESS8(HW_DMA_CERR_ADDR(x), BP_DMA_CERR_CAEI) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_CERR, field NOP[7] (WORZ)
- *
- * Values:
- * - 0 - Normal operation
- * - 1 - No operation, ignore the other bits in this register
- */
-//@{
-#define BP_DMA_CERR_NOP (7U) //!< Bit position for DMA_CERR_NOP.
-#define BM_DMA_CERR_NOP (0x80U) //!< Bit mask for DMA_CERR_NOP.
-#define BS_DMA_CERR_NOP (1U) //!< Bit field size in bits for DMA_CERR_NOP.
-
-//! @brief Format value for bitfield DMA_CERR_NOP.
-#define BF_DMA_CERR_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERR_NOP), uint8_t) & BM_DMA_CERR_NOP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the NOP field to a new value.
-#define BW_DMA_CERR_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CERR_ADDR(x), BP_DMA_CERR_NOP) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_DMA_CINT - Clear Interrupt Request Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_CINT - Clear Interrupt Request Register (WO)
- *
- * Reset value: 0x00U
- *
- * The CINT provides a simple, memory-mapped mechanism to clear a given bit in
- * the INT to disable the interrupt request for a given channel. The given value
- * on a register write causes the corresponding bit in the INT to be cleared.
- * Setting the CAIR bit provides a global clear function, forcing the entire contents
- * of the INT to be cleared, disabling all DMA interrupt requests. If the NOP
- * bit is set, the command is ignored. This allows you to write multiple-byte
- * registers as a 32-bit word. Reads of this register return all zeroes.
- */
-typedef union _hw_dma_cint
-{
- uint8_t U;
- struct _hw_dma_cint_bitfields
- {
- uint8_t CINT : 4; //!< [3:0] Clear Interrupt Request
- uint8_t RESERVED0 : 2; //!< [5:4]
- uint8_t CAIR : 1; //!< [6] Clear All Interrupt Requests
- uint8_t NOP : 1; //!< [7] No Op enable
- } B;
-} hw_dma_cint_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_CINT register
- */
-//@{
-#define HW_DMA_CINT_ADDR(x) (REGS_DMA_BASE(x) + 0x1FU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_CINT(x) (*(__O hw_dma_cint_t *) HW_DMA_CINT_ADDR(x))
-#define HW_DMA_CINT_RD(x) (HW_DMA_CINT(x).U)
-#define HW_DMA_CINT_WR(x, v) (HW_DMA_CINT(x).U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_CINT bitfields
- */
-
-/*!
- * @name Register DMA_CINT, field CINT[3:0] (WORZ)
- *
- * Clears the corresponding bit in INT
- */
-//@{
-#define BP_DMA_CINT_CINT (0U) //!< Bit position for DMA_CINT_CINT.
-#define BM_DMA_CINT_CINT (0x0FU) //!< Bit mask for DMA_CINT_CINT.
-#define BS_DMA_CINT_CINT (4U) //!< Bit field size in bits for DMA_CINT_CINT.
-
-//! @brief Format value for bitfield DMA_CINT_CINT.
-#define BF_DMA_CINT_CINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CINT_CINT), uint8_t) & BM_DMA_CINT_CINT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CINT field to a new value.
-#define BW_DMA_CINT_CINT(x, v) (HW_DMA_CINT_WR(x, (HW_DMA_CINT_RD(x) & ~BM_DMA_CINT_CINT) | BF_DMA_CINT_CINT(v)))
-#endif
-//@}
-
-/*!
- * @name Register DMA_CINT, field CAIR[6] (WORZ)
- *
- * Values:
- * - 0 - Clear only the INT bit specified in the CINT field
- * - 1 - Clear all bits in INT
- */
-//@{
-#define BP_DMA_CINT_CAIR (6U) //!< Bit position for DMA_CINT_CAIR.
-#define BM_DMA_CINT_CAIR (0x40U) //!< Bit mask for DMA_CINT_CAIR.
-#define BS_DMA_CINT_CAIR (1U) //!< Bit field size in bits for DMA_CINT_CAIR.
-
-//! @brief Format value for bitfield DMA_CINT_CAIR.
-#define BF_DMA_CINT_CAIR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CINT_CAIR), uint8_t) & BM_DMA_CINT_CAIR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CAIR field to a new value.
-#define BW_DMA_CINT_CAIR(x, v) (BITBAND_ACCESS8(HW_DMA_CINT_ADDR(x), BP_DMA_CINT_CAIR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_CINT, field NOP[7] (WORZ)
- *
- * Values:
- * - 0 - Normal operation
- * - 1 - No operation, ignore the other bits in this register
- */
-//@{
-#define BP_DMA_CINT_NOP (7U) //!< Bit position for DMA_CINT_NOP.
-#define BM_DMA_CINT_NOP (0x80U) //!< Bit mask for DMA_CINT_NOP.
-#define BS_DMA_CINT_NOP (1U) //!< Bit field size in bits for DMA_CINT_NOP.
-
-//! @brief Format value for bitfield DMA_CINT_NOP.
-#define BF_DMA_CINT_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CINT_NOP), uint8_t) & BM_DMA_CINT_NOP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the NOP field to a new value.
-#define BW_DMA_CINT_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CINT_ADDR(x), BP_DMA_CINT_NOP) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_DMA_INT - Interrupt Request Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_INT - Interrupt Request Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * The INT register provides a bit map for the 16 channels signaling the
- * presence of an interrupt request for each channel. Depending on the appropriate bit
- * setting in the transfer-control descriptors, the eDMA engine generates an
- * interrupt on data transfer completion. The outputs of this register are directly
- * routed to the interrupt controller (INTC). During the interrupt-service routine
- * associated with any given channel, it is the software's responsibility to
- * clear the appropriate bit, negating the interrupt request. Typically, a write to
- * the CINT register in the interrupt service routine is used for this purpose.
- * The state of any given channel's interrupt request is directly affected by
- * writes to this register; it is also affected by writes to the CINT register. On
- * writes to INT, a 1 in any bit position clears the corresponding channel's
- * interrupt request. A zero in any bit position has no affect on the corresponding
- * channel's current interrupt status. The CINT register is provided so the interrupt
- * request for a single channel can easily be cleared without the need to
- * perform a read-modify-write sequence to the INT register.
- */
-typedef union _hw_dma_int
-{
- uint32_t U;
- struct _hw_dma_int_bitfields
- {
- uint32_t INT0 : 1; //!< [0] Interrupt Request 0
- uint32_t INT1 : 1; //!< [1] Interrupt Request 1
- uint32_t INT2 : 1; //!< [2] Interrupt Request 2
- uint32_t INT3 : 1; //!< [3] Interrupt Request 3
- uint32_t INT4 : 1; //!< [4] Interrupt Request 4
- uint32_t INT5 : 1; //!< [5] Interrupt Request 5
- uint32_t INT6 : 1; //!< [6] Interrupt Request 6
- uint32_t INT7 : 1; //!< [7] Interrupt Request 7
- uint32_t INT8 : 1; //!< [8] Interrupt Request 8
- uint32_t INT9 : 1; //!< [9] Interrupt Request 9
- uint32_t INT10 : 1; //!< [10] Interrupt Request 10
- uint32_t INT11 : 1; //!< [11] Interrupt Request 11
- uint32_t INT12 : 1; //!< [12] Interrupt Request 12
- uint32_t INT13 : 1; //!< [13] Interrupt Request 13
- uint32_t INT14 : 1; //!< [14] Interrupt Request 14
- uint32_t INT15 : 1; //!< [15] Interrupt Request 15
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_dma_int_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_INT register
- */
-//@{
-#define HW_DMA_INT_ADDR(x) (REGS_DMA_BASE(x) + 0x24U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_INT(x) (*(__IO hw_dma_int_t *) HW_DMA_INT_ADDR(x))
-#define HW_DMA_INT_RD(x) (HW_DMA_INT(x).U)
-#define HW_DMA_INT_WR(x, v) (HW_DMA_INT(x).U = (v))
-#define HW_DMA_INT_SET(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) | (v)))
-#define HW_DMA_INT_CLR(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) & ~(v)))
-#define HW_DMA_INT_TOG(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_INT bitfields
- */
-
-/*!
- * @name Register DMA_INT, field INT0[0] (W1C)
- *
- * Values:
- * - 0 - The interrupt request for corresponding channel is cleared
- * - 1 - The interrupt request for corresponding channel is active
- */
-//@{
-#define BP_DMA_INT_INT0 (0U) //!< Bit position for DMA_INT_INT0.
-#define BM_DMA_INT_INT0 (0x00000001U) //!< Bit mask for DMA_INT_INT0.
-#define BS_DMA_INT_INT0 (1U) //!< Bit field size in bits for DMA_INT_INT0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_INT_INT0 field.
-#define BR_DMA_INT_INT0(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT0))
-#endif
-
-//! @brief Format value for bitfield DMA_INT_INT0.
-#define BF_DMA_INT_INT0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT0), uint32_t) & BM_DMA_INT_INT0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INT0 field to a new value.
-#define BW_DMA_INT_INT0(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_INT, field INT1[1] (W1C)
- *
- * Values:
- * - 0 - The interrupt request for corresponding channel is cleared
- * - 1 - The interrupt request for corresponding channel is active
- */
-//@{
-#define BP_DMA_INT_INT1 (1U) //!< Bit position for DMA_INT_INT1.
-#define BM_DMA_INT_INT1 (0x00000002U) //!< Bit mask for DMA_INT_INT1.
-#define BS_DMA_INT_INT1 (1U) //!< Bit field size in bits for DMA_INT_INT1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_INT_INT1 field.
-#define BR_DMA_INT_INT1(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT1))
-#endif
-
-//! @brief Format value for bitfield DMA_INT_INT1.
-#define BF_DMA_INT_INT1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT1), uint32_t) & BM_DMA_INT_INT1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INT1 field to a new value.
-#define BW_DMA_INT_INT1(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_INT, field INT2[2] (W1C)
- *
- * Values:
- * - 0 - The interrupt request for corresponding channel is cleared
- * - 1 - The interrupt request for corresponding channel is active
- */
-//@{
-#define BP_DMA_INT_INT2 (2U) //!< Bit position for DMA_INT_INT2.
-#define BM_DMA_INT_INT2 (0x00000004U) //!< Bit mask for DMA_INT_INT2.
-#define BS_DMA_INT_INT2 (1U) //!< Bit field size in bits for DMA_INT_INT2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_INT_INT2 field.
-#define BR_DMA_INT_INT2(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT2))
-#endif
-
-//! @brief Format value for bitfield DMA_INT_INT2.
-#define BF_DMA_INT_INT2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT2), uint32_t) & BM_DMA_INT_INT2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INT2 field to a new value.
-#define BW_DMA_INT_INT2(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_INT, field INT3[3] (W1C)
- *
- * Values:
- * - 0 - The interrupt request for corresponding channel is cleared
- * - 1 - The interrupt request for corresponding channel is active
- */
-//@{
-#define BP_DMA_INT_INT3 (3U) //!< Bit position for DMA_INT_INT3.
-#define BM_DMA_INT_INT3 (0x00000008U) //!< Bit mask for DMA_INT_INT3.
-#define BS_DMA_INT_INT3 (1U) //!< Bit field size in bits for DMA_INT_INT3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_INT_INT3 field.
-#define BR_DMA_INT_INT3(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT3))
-#endif
-
-//! @brief Format value for bitfield DMA_INT_INT3.
-#define BF_DMA_INT_INT3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT3), uint32_t) & BM_DMA_INT_INT3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INT3 field to a new value.
-#define BW_DMA_INT_INT3(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_INT, field INT4[4] (W1C)
- *
- * Values:
- * - 0 - The interrupt request for corresponding channel is cleared
- * - 1 - The interrupt request for corresponding channel is active
- */
-//@{
-#define BP_DMA_INT_INT4 (4U) //!< Bit position for DMA_INT_INT4.
-#define BM_DMA_INT_INT4 (0x00000010U) //!< Bit mask for DMA_INT_INT4.
-#define BS_DMA_INT_INT4 (1U) //!< Bit field size in bits for DMA_INT_INT4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_INT_INT4 field.
-#define BR_DMA_INT_INT4(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT4))
-#endif
-
-//! @brief Format value for bitfield DMA_INT_INT4.
-#define BF_DMA_INT_INT4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT4), uint32_t) & BM_DMA_INT_INT4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INT4 field to a new value.
-#define BW_DMA_INT_INT4(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_INT, field INT5[5] (W1C)
- *
- * Values:
- * - 0 - The interrupt request for corresponding channel is cleared
- * - 1 - The interrupt request for corresponding channel is active
- */
-//@{
-#define BP_DMA_INT_INT5 (5U) //!< Bit position for DMA_INT_INT5.
-#define BM_DMA_INT_INT5 (0x00000020U) //!< Bit mask for DMA_INT_INT5.
-#define BS_DMA_INT_INT5 (1U) //!< Bit field size in bits for DMA_INT_INT5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_INT_INT5 field.
-#define BR_DMA_INT_INT5(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT5))
-#endif
-
-//! @brief Format value for bitfield DMA_INT_INT5.
-#define BF_DMA_INT_INT5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT5), uint32_t) & BM_DMA_INT_INT5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INT5 field to a new value.
-#define BW_DMA_INT_INT5(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_INT, field INT6[6] (W1C)
- *
- * Values:
- * - 0 - The interrupt request for corresponding channel is cleared
- * - 1 - The interrupt request for corresponding channel is active
- */
-//@{
-#define BP_DMA_INT_INT6 (6U) //!< Bit position for DMA_INT_INT6.
-#define BM_DMA_INT_INT6 (0x00000040U) //!< Bit mask for DMA_INT_INT6.
-#define BS_DMA_INT_INT6 (1U) //!< Bit field size in bits for DMA_INT_INT6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_INT_INT6 field.
-#define BR_DMA_INT_INT6(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT6))
-#endif
-
-//! @brief Format value for bitfield DMA_INT_INT6.
-#define BF_DMA_INT_INT6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT6), uint32_t) & BM_DMA_INT_INT6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INT6 field to a new value.
-#define BW_DMA_INT_INT6(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_INT, field INT7[7] (W1C)
- *
- * Values:
- * - 0 - The interrupt request for corresponding channel is cleared
- * - 1 - The interrupt request for corresponding channel is active
- */
-//@{
-#define BP_DMA_INT_INT7 (7U) //!< Bit position for DMA_INT_INT7.
-#define BM_DMA_INT_INT7 (0x00000080U) //!< Bit mask for DMA_INT_INT7.
-#define BS_DMA_INT_INT7 (1U) //!< Bit field size in bits for DMA_INT_INT7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_INT_INT7 field.
-#define BR_DMA_INT_INT7(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT7))
-#endif
-
-//! @brief Format value for bitfield DMA_INT_INT7.
-#define BF_DMA_INT_INT7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT7), uint32_t) & BM_DMA_INT_INT7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INT7 field to a new value.
-#define BW_DMA_INT_INT7(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_INT, field INT8[8] (W1C)
- *
- * Values:
- * - 0 - The interrupt request for corresponding channel is cleared
- * - 1 - The interrupt request for corresponding channel is active
- */
-//@{
-#define BP_DMA_INT_INT8 (8U) //!< Bit position for DMA_INT_INT8.
-#define BM_DMA_INT_INT8 (0x00000100U) //!< Bit mask for DMA_INT_INT8.
-#define BS_DMA_INT_INT8 (1U) //!< Bit field size in bits for DMA_INT_INT8.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_INT_INT8 field.
-#define BR_DMA_INT_INT8(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT8))
-#endif
-
-//! @brief Format value for bitfield DMA_INT_INT8.
-#define BF_DMA_INT_INT8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT8), uint32_t) & BM_DMA_INT_INT8)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INT8 field to a new value.
-#define BW_DMA_INT_INT8(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT8) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_INT, field INT9[9] (W1C)
- *
- * Values:
- * - 0 - The interrupt request for corresponding channel is cleared
- * - 1 - The interrupt request for corresponding channel is active
- */
-//@{
-#define BP_DMA_INT_INT9 (9U) //!< Bit position for DMA_INT_INT9.
-#define BM_DMA_INT_INT9 (0x00000200U) //!< Bit mask for DMA_INT_INT9.
-#define BS_DMA_INT_INT9 (1U) //!< Bit field size in bits for DMA_INT_INT9.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_INT_INT9 field.
-#define BR_DMA_INT_INT9(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT9))
-#endif
-
-//! @brief Format value for bitfield DMA_INT_INT9.
-#define BF_DMA_INT_INT9(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT9), uint32_t) & BM_DMA_INT_INT9)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INT9 field to a new value.
-#define BW_DMA_INT_INT9(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT9) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_INT, field INT10[10] (W1C)
- *
- * Values:
- * - 0 - The interrupt request for corresponding channel is cleared
- * - 1 - The interrupt request for corresponding channel is active
- */
-//@{
-#define BP_DMA_INT_INT10 (10U) //!< Bit position for DMA_INT_INT10.
-#define BM_DMA_INT_INT10 (0x00000400U) //!< Bit mask for DMA_INT_INT10.
-#define BS_DMA_INT_INT10 (1U) //!< Bit field size in bits for DMA_INT_INT10.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_INT_INT10 field.
-#define BR_DMA_INT_INT10(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT10))
-#endif
-
-//! @brief Format value for bitfield DMA_INT_INT10.
-#define BF_DMA_INT_INT10(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT10), uint32_t) & BM_DMA_INT_INT10)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INT10 field to a new value.
-#define BW_DMA_INT_INT10(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT10) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_INT, field INT11[11] (W1C)
- *
- * Values:
- * - 0 - The interrupt request for corresponding channel is cleared
- * - 1 - The interrupt request for corresponding channel is active
- */
-//@{
-#define BP_DMA_INT_INT11 (11U) //!< Bit position for DMA_INT_INT11.
-#define BM_DMA_INT_INT11 (0x00000800U) //!< Bit mask for DMA_INT_INT11.
-#define BS_DMA_INT_INT11 (1U) //!< Bit field size in bits for DMA_INT_INT11.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_INT_INT11 field.
-#define BR_DMA_INT_INT11(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT11))
-#endif
-
-//! @brief Format value for bitfield DMA_INT_INT11.
-#define BF_DMA_INT_INT11(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT11), uint32_t) & BM_DMA_INT_INT11)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INT11 field to a new value.
-#define BW_DMA_INT_INT11(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT11) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_INT, field INT12[12] (W1C)
- *
- * Values:
- * - 0 - The interrupt request for corresponding channel is cleared
- * - 1 - The interrupt request for corresponding channel is active
- */
-//@{
-#define BP_DMA_INT_INT12 (12U) //!< Bit position for DMA_INT_INT12.
-#define BM_DMA_INT_INT12 (0x00001000U) //!< Bit mask for DMA_INT_INT12.
-#define BS_DMA_INT_INT12 (1U) //!< Bit field size in bits for DMA_INT_INT12.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_INT_INT12 field.
-#define BR_DMA_INT_INT12(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT12))
-#endif
-
-//! @brief Format value for bitfield DMA_INT_INT12.
-#define BF_DMA_INT_INT12(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT12), uint32_t) & BM_DMA_INT_INT12)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INT12 field to a new value.
-#define BW_DMA_INT_INT12(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT12) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_INT, field INT13[13] (W1C)
- *
- * Values:
- * - 0 - The interrupt request for corresponding channel is cleared
- * - 1 - The interrupt request for corresponding channel is active
- */
-//@{
-#define BP_DMA_INT_INT13 (13U) //!< Bit position for DMA_INT_INT13.
-#define BM_DMA_INT_INT13 (0x00002000U) //!< Bit mask for DMA_INT_INT13.
-#define BS_DMA_INT_INT13 (1U) //!< Bit field size in bits for DMA_INT_INT13.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_INT_INT13 field.
-#define BR_DMA_INT_INT13(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT13))
-#endif
-
-//! @brief Format value for bitfield DMA_INT_INT13.
-#define BF_DMA_INT_INT13(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT13), uint32_t) & BM_DMA_INT_INT13)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INT13 field to a new value.
-#define BW_DMA_INT_INT13(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT13) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_INT, field INT14[14] (W1C)
- *
- * Values:
- * - 0 - The interrupt request for corresponding channel is cleared
- * - 1 - The interrupt request for corresponding channel is active
- */
-//@{
-#define BP_DMA_INT_INT14 (14U) //!< Bit position for DMA_INT_INT14.
-#define BM_DMA_INT_INT14 (0x00004000U) //!< Bit mask for DMA_INT_INT14.
-#define BS_DMA_INT_INT14 (1U) //!< Bit field size in bits for DMA_INT_INT14.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_INT_INT14 field.
-#define BR_DMA_INT_INT14(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT14))
-#endif
-
-//! @brief Format value for bitfield DMA_INT_INT14.
-#define BF_DMA_INT_INT14(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT14), uint32_t) & BM_DMA_INT_INT14)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INT14 field to a new value.
-#define BW_DMA_INT_INT14(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT14) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_INT, field INT15[15] (W1C)
- *
- * Values:
- * - 0 - The interrupt request for corresponding channel is cleared
- * - 1 - The interrupt request for corresponding channel is active
- */
-//@{
-#define BP_DMA_INT_INT15 (15U) //!< Bit position for DMA_INT_INT15.
-#define BM_DMA_INT_INT15 (0x00008000U) //!< Bit mask for DMA_INT_INT15.
-#define BS_DMA_INT_INT15 (1U) //!< Bit field size in bits for DMA_INT_INT15.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_INT_INT15 field.
-#define BR_DMA_INT_INT15(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT15))
-#endif
-
-//! @brief Format value for bitfield DMA_INT_INT15.
-#define BF_DMA_INT_INT15(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT15), uint32_t) & BM_DMA_INT_INT15)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INT15 field to a new value.
-#define BW_DMA_INT_INT15(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT15) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_DMA_ERR - Error Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_ERR - Error Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * The ERR provides a bit map for the 16 channels, signaling the presence of an
- * error for each channel. The eDMA engine signals the occurrence of an error
- * condition by setting the appropriate bit in this register. The outputs of this
- * register are enabled by the contents of the EEI, and then routed to the
- * interrupt controller. During the execution of the interrupt-service routine associated
- * with any DMA errors, it is software's responsibility to clear the appropriate
- * bit, negating the error-interrupt request. Typically, a write to the CERR in
- * the interrupt-service routine is used for this purpose. The normal DMA channel
- * completion indicators (setting the transfer control descriptor DONE flag and
- * the possible assertion of an interrupt request) are not affected when an error
- * is detected. The contents of this register can also be polled because a
- * non-zero value indicates the presence of a channel error regardless of the state of
- * the EEI. The state of any given channel's error indicators is affected by
- * writes to this register; it is also affected by writes to the CERR. On writes to
- * the ERR, a one in any bit position clears the corresponding channel's error
- * status. A zero in any bit position has no affect on the corresponding channel's
- * current error status. The CERR is provided so the error indicator for a single
- * channel can easily be cleared.
- */
-typedef union _hw_dma_err
-{
- uint32_t U;
- struct _hw_dma_err_bitfields
- {
- uint32_t ERR0 : 1; //!< [0] Error In Channel 0
- uint32_t ERR1 : 1; //!< [1] Error In Channel 1
- uint32_t ERR2 : 1; //!< [2] Error In Channel 2
- uint32_t ERR3 : 1; //!< [3] Error In Channel 3
- uint32_t ERR4 : 1; //!< [4] Error In Channel 4
- uint32_t ERR5 : 1; //!< [5] Error In Channel 5
- uint32_t ERR6 : 1; //!< [6] Error In Channel 6
- uint32_t ERR7 : 1; //!< [7] Error In Channel 7
- uint32_t ERR8 : 1; //!< [8] Error In Channel 8
- uint32_t ERR9 : 1; //!< [9] Error In Channel 9
- uint32_t ERR10 : 1; //!< [10] Error In Channel 10
- uint32_t ERR11 : 1; //!< [11] Error In Channel 11
- uint32_t ERR12 : 1; //!< [12] Error In Channel 12
- uint32_t ERR13 : 1; //!< [13] Error In Channel 13
- uint32_t ERR14 : 1; //!< [14] Error In Channel 14
- uint32_t ERR15 : 1; //!< [15] Error In Channel 15
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_dma_err_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_ERR register
- */
-//@{
-#define HW_DMA_ERR_ADDR(x) (REGS_DMA_BASE(x) + 0x2CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_ERR(x) (*(__IO hw_dma_err_t *) HW_DMA_ERR_ADDR(x))
-#define HW_DMA_ERR_RD(x) (HW_DMA_ERR(x).U)
-#define HW_DMA_ERR_WR(x, v) (HW_DMA_ERR(x).U = (v))
-#define HW_DMA_ERR_SET(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) | (v)))
-#define HW_DMA_ERR_CLR(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) & ~(v)))
-#define HW_DMA_ERR_TOG(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_ERR bitfields
- */
-
-/*!
- * @name Register DMA_ERR, field ERR0[0] (W1C)
- *
- * Values:
- * - 0 - An error in the corresponding channel has not occurred
- * - 1 - An error in the corresponding channel has occurred
- */
-//@{
-#define BP_DMA_ERR_ERR0 (0U) //!< Bit position for DMA_ERR_ERR0.
-#define BM_DMA_ERR_ERR0 (0x00000001U) //!< Bit mask for DMA_ERR_ERR0.
-#define BS_DMA_ERR_ERR0 (1U) //!< Bit field size in bits for DMA_ERR_ERR0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERR_ERR0 field.
-#define BR_DMA_ERR_ERR0(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR0))
-#endif
-
-//! @brief Format value for bitfield DMA_ERR_ERR0.
-#define BF_DMA_ERR_ERR0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR0), uint32_t) & BM_DMA_ERR_ERR0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERR0 field to a new value.
-#define BW_DMA_ERR_ERR0(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERR, field ERR1[1] (W1C)
- *
- * Values:
- * - 0 - An error in the corresponding channel has not occurred
- * - 1 - An error in the corresponding channel has occurred
- */
-//@{
-#define BP_DMA_ERR_ERR1 (1U) //!< Bit position for DMA_ERR_ERR1.
-#define BM_DMA_ERR_ERR1 (0x00000002U) //!< Bit mask for DMA_ERR_ERR1.
-#define BS_DMA_ERR_ERR1 (1U) //!< Bit field size in bits for DMA_ERR_ERR1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERR_ERR1 field.
-#define BR_DMA_ERR_ERR1(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR1))
-#endif
-
-//! @brief Format value for bitfield DMA_ERR_ERR1.
-#define BF_DMA_ERR_ERR1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR1), uint32_t) & BM_DMA_ERR_ERR1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERR1 field to a new value.
-#define BW_DMA_ERR_ERR1(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERR, field ERR2[2] (W1C)
- *
- * Values:
- * - 0 - An error in the corresponding channel has not occurred
- * - 1 - An error in the corresponding channel has occurred
- */
-//@{
-#define BP_DMA_ERR_ERR2 (2U) //!< Bit position for DMA_ERR_ERR2.
-#define BM_DMA_ERR_ERR2 (0x00000004U) //!< Bit mask for DMA_ERR_ERR2.
-#define BS_DMA_ERR_ERR2 (1U) //!< Bit field size in bits for DMA_ERR_ERR2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERR_ERR2 field.
-#define BR_DMA_ERR_ERR2(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR2))
-#endif
-
-//! @brief Format value for bitfield DMA_ERR_ERR2.
-#define BF_DMA_ERR_ERR2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR2), uint32_t) & BM_DMA_ERR_ERR2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERR2 field to a new value.
-#define BW_DMA_ERR_ERR2(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERR, field ERR3[3] (W1C)
- *
- * Values:
- * - 0 - An error in the corresponding channel has not occurred
- * - 1 - An error in the corresponding channel has occurred
- */
-//@{
-#define BP_DMA_ERR_ERR3 (3U) //!< Bit position for DMA_ERR_ERR3.
-#define BM_DMA_ERR_ERR3 (0x00000008U) //!< Bit mask for DMA_ERR_ERR3.
-#define BS_DMA_ERR_ERR3 (1U) //!< Bit field size in bits for DMA_ERR_ERR3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERR_ERR3 field.
-#define BR_DMA_ERR_ERR3(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR3))
-#endif
-
-//! @brief Format value for bitfield DMA_ERR_ERR3.
-#define BF_DMA_ERR_ERR3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR3), uint32_t) & BM_DMA_ERR_ERR3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERR3 field to a new value.
-#define BW_DMA_ERR_ERR3(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERR, field ERR4[4] (W1C)
- *
- * Values:
- * - 0 - An error in the corresponding channel has not occurred
- * - 1 - An error in the corresponding channel has occurred
- */
-//@{
-#define BP_DMA_ERR_ERR4 (4U) //!< Bit position for DMA_ERR_ERR4.
-#define BM_DMA_ERR_ERR4 (0x00000010U) //!< Bit mask for DMA_ERR_ERR4.
-#define BS_DMA_ERR_ERR4 (1U) //!< Bit field size in bits for DMA_ERR_ERR4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERR_ERR4 field.
-#define BR_DMA_ERR_ERR4(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR4))
-#endif
-
-//! @brief Format value for bitfield DMA_ERR_ERR4.
-#define BF_DMA_ERR_ERR4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR4), uint32_t) & BM_DMA_ERR_ERR4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERR4 field to a new value.
-#define BW_DMA_ERR_ERR4(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERR, field ERR5[5] (W1C)
- *
- * Values:
- * - 0 - An error in the corresponding channel has not occurred
- * - 1 - An error in the corresponding channel has occurred
- */
-//@{
-#define BP_DMA_ERR_ERR5 (5U) //!< Bit position for DMA_ERR_ERR5.
-#define BM_DMA_ERR_ERR5 (0x00000020U) //!< Bit mask for DMA_ERR_ERR5.
-#define BS_DMA_ERR_ERR5 (1U) //!< Bit field size in bits for DMA_ERR_ERR5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERR_ERR5 field.
-#define BR_DMA_ERR_ERR5(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR5))
-#endif
-
-//! @brief Format value for bitfield DMA_ERR_ERR5.
-#define BF_DMA_ERR_ERR5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR5), uint32_t) & BM_DMA_ERR_ERR5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERR5 field to a new value.
-#define BW_DMA_ERR_ERR5(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERR, field ERR6[6] (W1C)
- *
- * Values:
- * - 0 - An error in the corresponding channel has not occurred
- * - 1 - An error in the corresponding channel has occurred
- */
-//@{
-#define BP_DMA_ERR_ERR6 (6U) //!< Bit position for DMA_ERR_ERR6.
-#define BM_DMA_ERR_ERR6 (0x00000040U) //!< Bit mask for DMA_ERR_ERR6.
-#define BS_DMA_ERR_ERR6 (1U) //!< Bit field size in bits for DMA_ERR_ERR6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERR_ERR6 field.
-#define BR_DMA_ERR_ERR6(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR6))
-#endif
-
-//! @brief Format value for bitfield DMA_ERR_ERR6.
-#define BF_DMA_ERR_ERR6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR6), uint32_t) & BM_DMA_ERR_ERR6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERR6 field to a new value.
-#define BW_DMA_ERR_ERR6(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERR, field ERR7[7] (W1C)
- *
- * Values:
- * - 0 - An error in the corresponding channel has not occurred
- * - 1 - An error in the corresponding channel has occurred
- */
-//@{
-#define BP_DMA_ERR_ERR7 (7U) //!< Bit position for DMA_ERR_ERR7.
-#define BM_DMA_ERR_ERR7 (0x00000080U) //!< Bit mask for DMA_ERR_ERR7.
-#define BS_DMA_ERR_ERR7 (1U) //!< Bit field size in bits for DMA_ERR_ERR7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERR_ERR7 field.
-#define BR_DMA_ERR_ERR7(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR7))
-#endif
-
-//! @brief Format value for bitfield DMA_ERR_ERR7.
-#define BF_DMA_ERR_ERR7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR7), uint32_t) & BM_DMA_ERR_ERR7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERR7 field to a new value.
-#define BW_DMA_ERR_ERR7(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR7) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERR, field ERR8[8] (W1C)
- *
- * Values:
- * - 0 - An error in the corresponding channel has not occurred
- * - 1 - An error in the corresponding channel has occurred
- */
-//@{
-#define BP_DMA_ERR_ERR8 (8U) //!< Bit position for DMA_ERR_ERR8.
-#define BM_DMA_ERR_ERR8 (0x00000100U) //!< Bit mask for DMA_ERR_ERR8.
-#define BS_DMA_ERR_ERR8 (1U) //!< Bit field size in bits for DMA_ERR_ERR8.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERR_ERR8 field.
-#define BR_DMA_ERR_ERR8(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR8))
-#endif
-
-//! @brief Format value for bitfield DMA_ERR_ERR8.
-#define BF_DMA_ERR_ERR8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR8), uint32_t) & BM_DMA_ERR_ERR8)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERR8 field to a new value.
-#define BW_DMA_ERR_ERR8(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR8) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERR, field ERR9[9] (W1C)
- *
- * Values:
- * - 0 - An error in the corresponding channel has not occurred
- * - 1 - An error in the corresponding channel has occurred
- */
-//@{
-#define BP_DMA_ERR_ERR9 (9U) //!< Bit position for DMA_ERR_ERR9.
-#define BM_DMA_ERR_ERR9 (0x00000200U) //!< Bit mask for DMA_ERR_ERR9.
-#define BS_DMA_ERR_ERR9 (1U) //!< Bit field size in bits for DMA_ERR_ERR9.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERR_ERR9 field.
-#define BR_DMA_ERR_ERR9(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR9))
-#endif
-
-//! @brief Format value for bitfield DMA_ERR_ERR9.
-#define BF_DMA_ERR_ERR9(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR9), uint32_t) & BM_DMA_ERR_ERR9)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERR9 field to a new value.
-#define BW_DMA_ERR_ERR9(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR9) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERR, field ERR10[10] (W1C)
- *
- * Values:
- * - 0 - An error in the corresponding channel has not occurred
- * - 1 - An error in the corresponding channel has occurred
- */
-//@{
-#define BP_DMA_ERR_ERR10 (10U) //!< Bit position for DMA_ERR_ERR10.
-#define BM_DMA_ERR_ERR10 (0x00000400U) //!< Bit mask for DMA_ERR_ERR10.
-#define BS_DMA_ERR_ERR10 (1U) //!< Bit field size in bits for DMA_ERR_ERR10.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERR_ERR10 field.
-#define BR_DMA_ERR_ERR10(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR10))
-#endif
-
-//! @brief Format value for bitfield DMA_ERR_ERR10.
-#define BF_DMA_ERR_ERR10(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR10), uint32_t) & BM_DMA_ERR_ERR10)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERR10 field to a new value.
-#define BW_DMA_ERR_ERR10(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR10) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERR, field ERR11[11] (W1C)
- *
- * Values:
- * - 0 - An error in the corresponding channel has not occurred
- * - 1 - An error in the corresponding channel has occurred
- */
-//@{
-#define BP_DMA_ERR_ERR11 (11U) //!< Bit position for DMA_ERR_ERR11.
-#define BM_DMA_ERR_ERR11 (0x00000800U) //!< Bit mask for DMA_ERR_ERR11.
-#define BS_DMA_ERR_ERR11 (1U) //!< Bit field size in bits for DMA_ERR_ERR11.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERR_ERR11 field.
-#define BR_DMA_ERR_ERR11(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR11))
-#endif
-
-//! @brief Format value for bitfield DMA_ERR_ERR11.
-#define BF_DMA_ERR_ERR11(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR11), uint32_t) & BM_DMA_ERR_ERR11)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERR11 field to a new value.
-#define BW_DMA_ERR_ERR11(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR11) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERR, field ERR12[12] (W1C)
- *
- * Values:
- * - 0 - An error in the corresponding channel has not occurred
- * - 1 - An error in the corresponding channel has occurred
- */
-//@{
-#define BP_DMA_ERR_ERR12 (12U) //!< Bit position for DMA_ERR_ERR12.
-#define BM_DMA_ERR_ERR12 (0x00001000U) //!< Bit mask for DMA_ERR_ERR12.
-#define BS_DMA_ERR_ERR12 (1U) //!< Bit field size in bits for DMA_ERR_ERR12.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERR_ERR12 field.
-#define BR_DMA_ERR_ERR12(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR12))
-#endif
-
-//! @brief Format value for bitfield DMA_ERR_ERR12.
-#define BF_DMA_ERR_ERR12(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR12), uint32_t) & BM_DMA_ERR_ERR12)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERR12 field to a new value.
-#define BW_DMA_ERR_ERR12(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR12) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERR, field ERR13[13] (W1C)
- *
- * Values:
- * - 0 - An error in the corresponding channel has not occurred
- * - 1 - An error in the corresponding channel has occurred
- */
-//@{
-#define BP_DMA_ERR_ERR13 (13U) //!< Bit position for DMA_ERR_ERR13.
-#define BM_DMA_ERR_ERR13 (0x00002000U) //!< Bit mask for DMA_ERR_ERR13.
-#define BS_DMA_ERR_ERR13 (1U) //!< Bit field size in bits for DMA_ERR_ERR13.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERR_ERR13 field.
-#define BR_DMA_ERR_ERR13(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR13))
-#endif
-
-//! @brief Format value for bitfield DMA_ERR_ERR13.
-#define BF_DMA_ERR_ERR13(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR13), uint32_t) & BM_DMA_ERR_ERR13)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERR13 field to a new value.
-#define BW_DMA_ERR_ERR13(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR13) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERR, field ERR14[14] (W1C)
- *
- * Values:
- * - 0 - An error in the corresponding channel has not occurred
- * - 1 - An error in the corresponding channel has occurred
- */
-//@{
-#define BP_DMA_ERR_ERR14 (14U) //!< Bit position for DMA_ERR_ERR14.
-#define BM_DMA_ERR_ERR14 (0x00004000U) //!< Bit mask for DMA_ERR_ERR14.
-#define BS_DMA_ERR_ERR14 (1U) //!< Bit field size in bits for DMA_ERR_ERR14.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERR_ERR14 field.
-#define BR_DMA_ERR_ERR14(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR14))
-#endif
-
-//! @brief Format value for bitfield DMA_ERR_ERR14.
-#define BF_DMA_ERR_ERR14(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR14), uint32_t) & BM_DMA_ERR_ERR14)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERR14 field to a new value.
-#define BW_DMA_ERR_ERR14(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR14) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_ERR, field ERR15[15] (W1C)
- *
- * Values:
- * - 0 - An error in the corresponding channel has not occurred
- * - 1 - An error in the corresponding channel has occurred
- */
-//@{
-#define BP_DMA_ERR_ERR15 (15U) //!< Bit position for DMA_ERR_ERR15.
-#define BM_DMA_ERR_ERR15 (0x00008000U) //!< Bit mask for DMA_ERR_ERR15.
-#define BS_DMA_ERR_ERR15 (1U) //!< Bit field size in bits for DMA_ERR_ERR15.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_ERR_ERR15 field.
-#define BR_DMA_ERR_ERR15(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR15))
-#endif
-
-//! @brief Format value for bitfield DMA_ERR_ERR15.
-#define BF_DMA_ERR_ERR15(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR15), uint32_t) & BM_DMA_ERR_ERR15)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERR15 field to a new value.
-#define BW_DMA_ERR_ERR15(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR15) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_DMA_HRS - Hardware Request Status Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_HRS - Hardware Request Status Register (RO)
- *
- * Reset value: 0x00000000U
- *
- * The HRS register provides a bit map for the DMA channels, signaling the
- * presence of a hardware request for each channel. The hardware request status bits
- * reflect the current state of the register and qualified (via the ERQ fields)
- * DMA request signals as seen by the DMA's arbitration logic. This view into the
- * hardware request signals may be used for debug purposes. These bits reflect the
- * state of the request as seen by the arbitration logic. Therefore, this status
- * is affected by the ERQ bits.
- */
-typedef union _hw_dma_hrs
-{
- uint32_t U;
- struct _hw_dma_hrs_bitfields
- {
- uint32_t HRS0 : 1; //!< [0] Hardware Request Status Channel 0
- uint32_t HRS1 : 1; //!< [1] Hardware Request Status Channel 1
- uint32_t HRS2 : 1; //!< [2] Hardware Request Status Channel 2
- uint32_t HRS3 : 1; //!< [3] Hardware Request Status Channel 3
- uint32_t HRS4 : 1; //!< [4] Hardware Request Status Channel 4
- uint32_t HRS5 : 1; //!< [5] Hardware Request Status Channel 5
- uint32_t HRS6 : 1; //!< [6] Hardware Request Status Channel 6
- uint32_t HRS7 : 1; //!< [7] Hardware Request Status Channel 7
- uint32_t HRS8 : 1; //!< [8] Hardware Request Status Channel 8
- uint32_t HRS9 : 1; //!< [9] Hardware Request Status Channel 9
- uint32_t HRS10 : 1; //!< [10] Hardware Request Status Channel 10
- uint32_t HRS11 : 1; //!< [11] Hardware Request Status Channel 11
- uint32_t HRS12 : 1; //!< [12] Hardware Request Status Channel 12
- uint32_t HRS13 : 1; //!< [13] Hardware Request Status Channel 13
- uint32_t HRS14 : 1; //!< [14] Hardware Request Status Channel 14
- uint32_t HRS15 : 1; //!< [15] Hardware Request Status Channel 15
- uint32_t RESERVED0 : 16; //!< [31:16] Reserved
- } B;
-} hw_dma_hrs_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_HRS register
- */
-//@{
-#define HW_DMA_HRS_ADDR(x) (REGS_DMA_BASE(x) + 0x34U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_HRS(x) (*(__I hw_dma_hrs_t *) HW_DMA_HRS_ADDR(x))
-#define HW_DMA_HRS_RD(x) (HW_DMA_HRS(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_HRS bitfields
- */
-
-/*!
- * @name Register DMA_HRS, field HRS0[0] (RO)
- *
- * The HRS bit for its respective channel remains asserted for the period when a
- * Hardware Request is Present on the Channel. After the Request is completed
- * and Channel is free , the HRS bit is automatically cleared by hardware.
- *
- * Values:
- * - 0 - A hardware service request for channel 0 is not present
- * - 1 - A hardware service request for channel 0 is present
- */
-//@{
-#define BP_DMA_HRS_HRS0 (0U) //!< Bit position for DMA_HRS_HRS0.
-#define BM_DMA_HRS_HRS0 (0x00000001U) //!< Bit mask for DMA_HRS_HRS0.
-#define BS_DMA_HRS_HRS0 (1U) //!< Bit field size in bits for DMA_HRS_HRS0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_HRS_HRS0 field.
-#define BR_DMA_HRS_HRS0(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS0))
-#endif
-//@}
-
-/*!
- * @name Register DMA_HRS, field HRS1[1] (RO)
- *
- * The HRS bit for its respective channel remains asserted for the period when a
- * Hardware Request is Present on the Channel. After the Request is completed
- * and Channel is free , the HRS bit is automatically cleared by hardware.
- *
- * Values:
- * - 0 - A hardware service request for channel 1 is not present
- * - 1 - A hardware service request for channel 1 is present
- */
-//@{
-#define BP_DMA_HRS_HRS1 (1U) //!< Bit position for DMA_HRS_HRS1.
-#define BM_DMA_HRS_HRS1 (0x00000002U) //!< Bit mask for DMA_HRS_HRS1.
-#define BS_DMA_HRS_HRS1 (1U) //!< Bit field size in bits for DMA_HRS_HRS1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_HRS_HRS1 field.
-#define BR_DMA_HRS_HRS1(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS1))
-#endif
-//@}
-
-/*!
- * @name Register DMA_HRS, field HRS2[2] (RO)
- *
- * The HRS bit for its respective channel remains asserted for the period when a
- * Hardware Request is Present on the Channel. After the Request is completed
- * and Channel is free , the HRS bit is automatically cleared by hardware.
- *
- * Values:
- * - 0 - A hardware service request for channel 2 is not present
- * - 1 - A hardware service request for channel 2 is present
- */
-//@{
-#define BP_DMA_HRS_HRS2 (2U) //!< Bit position for DMA_HRS_HRS2.
-#define BM_DMA_HRS_HRS2 (0x00000004U) //!< Bit mask for DMA_HRS_HRS2.
-#define BS_DMA_HRS_HRS2 (1U) //!< Bit field size in bits for DMA_HRS_HRS2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_HRS_HRS2 field.
-#define BR_DMA_HRS_HRS2(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS2))
-#endif
-//@}
-
-/*!
- * @name Register DMA_HRS, field HRS3[3] (RO)
- *
- * The HRS bit for its respective channel remains asserted for the period when a
- * Hardware Request is Present on the Channel. After the Request is completed
- * and Channel is free , the HRS bit is automatically cleared by hardware.
- *
- * Values:
- * - 0 - A hardware service request for channel 3 is not present
- * - 1 - A hardware service request for channel 3 is present
- */
-//@{
-#define BP_DMA_HRS_HRS3 (3U) //!< Bit position for DMA_HRS_HRS3.
-#define BM_DMA_HRS_HRS3 (0x00000008U) //!< Bit mask for DMA_HRS_HRS3.
-#define BS_DMA_HRS_HRS3 (1U) //!< Bit field size in bits for DMA_HRS_HRS3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_HRS_HRS3 field.
-#define BR_DMA_HRS_HRS3(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS3))
-#endif
-//@}
-
-/*!
- * @name Register DMA_HRS, field HRS4[4] (RO)
- *
- * The HRS bit for its respective channel remains asserted for the period when a
- * Hardware Request is Present on the Channel. After the Request is completed
- * and Channel is free , the HRS bit is automatically cleared by hardware.
- *
- * Values:
- * - 0 - A hardware service request for channel 4 is not present
- * - 1 - A hardware service request for channel 4 is present
- */
-//@{
-#define BP_DMA_HRS_HRS4 (4U) //!< Bit position for DMA_HRS_HRS4.
-#define BM_DMA_HRS_HRS4 (0x00000010U) //!< Bit mask for DMA_HRS_HRS4.
-#define BS_DMA_HRS_HRS4 (1U) //!< Bit field size in bits for DMA_HRS_HRS4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_HRS_HRS4 field.
-#define BR_DMA_HRS_HRS4(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS4))
-#endif
-//@}
-
-/*!
- * @name Register DMA_HRS, field HRS5[5] (RO)
- *
- * The HRS bit for its respective channel remains asserted for the period when a
- * Hardware Request is Present on the Channel. After the Request is completed
- * and Channel is free , the HRS bit is automatically cleared by hardware.
- *
- * Values:
- * - 0 - A hardware service request for channel 5 is not present
- * - 1 - A hardware service request for channel 5 is present
- */
-//@{
-#define BP_DMA_HRS_HRS5 (5U) //!< Bit position for DMA_HRS_HRS5.
-#define BM_DMA_HRS_HRS5 (0x00000020U) //!< Bit mask for DMA_HRS_HRS5.
-#define BS_DMA_HRS_HRS5 (1U) //!< Bit field size in bits for DMA_HRS_HRS5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_HRS_HRS5 field.
-#define BR_DMA_HRS_HRS5(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS5))
-#endif
-//@}
-
-/*!
- * @name Register DMA_HRS, field HRS6[6] (RO)
- *
- * The HRS bit for its respective channel remains asserted for the period when a
- * Hardware Request is Present on the Channel. After the Request is completed
- * and Channel is free , the HRS bit is automatically cleared by hardware.
- *
- * Values:
- * - 0 - A hardware service request for channel 6 is not present
- * - 1 - A hardware service request for channel 6 is present
- */
-//@{
-#define BP_DMA_HRS_HRS6 (6U) //!< Bit position for DMA_HRS_HRS6.
-#define BM_DMA_HRS_HRS6 (0x00000040U) //!< Bit mask for DMA_HRS_HRS6.
-#define BS_DMA_HRS_HRS6 (1U) //!< Bit field size in bits for DMA_HRS_HRS6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_HRS_HRS6 field.
-#define BR_DMA_HRS_HRS6(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS6))
-#endif
-//@}
-
-/*!
- * @name Register DMA_HRS, field HRS7[7] (RO)
- *
- * The HRS bit for its respective channel remains asserted for the period when a
- * Hardware Request is Present on the Channel. After the Request is completed
- * and Channel is free , the HRS bit is automatically cleared by hardware.
- *
- * Values:
- * - 0 - A hardware service request for channel 7 is not present
- * - 1 - A hardware service request for channel 7 is present
- */
-//@{
-#define BP_DMA_HRS_HRS7 (7U) //!< Bit position for DMA_HRS_HRS7.
-#define BM_DMA_HRS_HRS7 (0x00000080U) //!< Bit mask for DMA_HRS_HRS7.
-#define BS_DMA_HRS_HRS7 (1U) //!< Bit field size in bits for DMA_HRS_HRS7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_HRS_HRS7 field.
-#define BR_DMA_HRS_HRS7(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS7))
-#endif
-//@}
-
-/*!
- * @name Register DMA_HRS, field HRS8[8] (RO)
- *
- * The HRS bit for its respective channel remains asserted for the period when a
- * Hardware Request is Present on the Channel. After the Request is completed
- * and Channel is free , the HRS bit is automatically cleared by hardware.
- *
- * Values:
- * - 0 - A hardware service request for channel 8 is not present
- * - 1 - A hardware service request for channel 8 is present
- */
-//@{
-#define BP_DMA_HRS_HRS8 (8U) //!< Bit position for DMA_HRS_HRS8.
-#define BM_DMA_HRS_HRS8 (0x00000100U) //!< Bit mask for DMA_HRS_HRS8.
-#define BS_DMA_HRS_HRS8 (1U) //!< Bit field size in bits for DMA_HRS_HRS8.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_HRS_HRS8 field.
-#define BR_DMA_HRS_HRS8(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS8))
-#endif
-//@}
-
-/*!
- * @name Register DMA_HRS, field HRS9[9] (RO)
- *
- * The HRS bit for its respective channel remains asserted for the period when a
- * Hardware Request is Present on the Channel. After the Request is completed
- * and Channel is free , the HRS bit is automatically cleared by hardware.
- *
- * Values:
- * - 0 - A hardware service request for channel 9 is not present
- * - 1 - A hardware service request for channel 9 is present
- */
-//@{
-#define BP_DMA_HRS_HRS9 (9U) //!< Bit position for DMA_HRS_HRS9.
-#define BM_DMA_HRS_HRS9 (0x00000200U) //!< Bit mask for DMA_HRS_HRS9.
-#define BS_DMA_HRS_HRS9 (1U) //!< Bit field size in bits for DMA_HRS_HRS9.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_HRS_HRS9 field.
-#define BR_DMA_HRS_HRS9(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS9))
-#endif
-//@}
-
-/*!
- * @name Register DMA_HRS, field HRS10[10] (RO)
- *
- * The HRS bit for its respective channel remains asserted for the period when a
- * Hardware Request is Present on the Channel. After the Request is completed
- * and Channel is free , the HRS bit is automatically cleared by hardware.
- *
- * Values:
- * - 0 - A hardware service request for channel 10 is not present
- * - 1 - A hardware service request for channel 10 is present
- */
-//@{
-#define BP_DMA_HRS_HRS10 (10U) //!< Bit position for DMA_HRS_HRS10.
-#define BM_DMA_HRS_HRS10 (0x00000400U) //!< Bit mask for DMA_HRS_HRS10.
-#define BS_DMA_HRS_HRS10 (1U) //!< Bit field size in bits for DMA_HRS_HRS10.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_HRS_HRS10 field.
-#define BR_DMA_HRS_HRS10(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS10))
-#endif
-//@}
-
-/*!
- * @name Register DMA_HRS, field HRS11[11] (RO)
- *
- * The HRS bit for its respective channel remains asserted for the period when a
- * Hardware Request is Present on the Channel. After the Request is completed
- * and Channel is free , the HRS bit is automatically cleared by hardware.
- *
- * Values:
- * - 0 - A hardware service request for channel 11 is not present
- * - 1 - A hardware service request for channel 11 is present
- */
-//@{
-#define BP_DMA_HRS_HRS11 (11U) //!< Bit position for DMA_HRS_HRS11.
-#define BM_DMA_HRS_HRS11 (0x00000800U) //!< Bit mask for DMA_HRS_HRS11.
-#define BS_DMA_HRS_HRS11 (1U) //!< Bit field size in bits for DMA_HRS_HRS11.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_HRS_HRS11 field.
-#define BR_DMA_HRS_HRS11(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS11))
-#endif
-//@}
-
-/*!
- * @name Register DMA_HRS, field HRS12[12] (RO)
- *
- * The HRS bit for its respective channel remains asserted for the period when a
- * Hardware Request is Present on the Channel. After the Request is completed
- * and Channel is free , the HRS bit is automatically cleared by hardware.
- *
- * Values:
- * - 0 - A hardware service request for channel 12 is not present
- * - 1 - A hardware service request for channel 12 is present
- */
-//@{
-#define BP_DMA_HRS_HRS12 (12U) //!< Bit position for DMA_HRS_HRS12.
-#define BM_DMA_HRS_HRS12 (0x00001000U) //!< Bit mask for DMA_HRS_HRS12.
-#define BS_DMA_HRS_HRS12 (1U) //!< Bit field size in bits for DMA_HRS_HRS12.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_HRS_HRS12 field.
-#define BR_DMA_HRS_HRS12(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS12))
-#endif
-//@}
-
-/*!
- * @name Register DMA_HRS, field HRS13[13] (RO)
- *
- * The HRS bit for its respective channel remains asserted for the period when a
- * Hardware Request is Present on the Channel. After the Request is completed
- * and Channel is free , the HRS bit is automatically cleared by hardware.
- *
- * Values:
- * - 0 - A hardware service request for channel 13 is not present
- * - 1 - A hardware service request for channel 13 is present
- */
-//@{
-#define BP_DMA_HRS_HRS13 (13U) //!< Bit position for DMA_HRS_HRS13.
-#define BM_DMA_HRS_HRS13 (0x00002000U) //!< Bit mask for DMA_HRS_HRS13.
-#define BS_DMA_HRS_HRS13 (1U) //!< Bit field size in bits for DMA_HRS_HRS13.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_HRS_HRS13 field.
-#define BR_DMA_HRS_HRS13(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS13))
-#endif
-//@}
-
-/*!
- * @name Register DMA_HRS, field HRS14[14] (RO)
- *
- * The HRS bit for its respective channel remains asserted for the period when a
- * Hardware Request is Present on the Channel. After the Request is completed
- * and Channel is free , the HRS bit is automatically cleared by hardware.
- *
- * Values:
- * - 0 - A hardware service request for channel 14 is not present
- * - 1 - A hardware service request for channel 14 is present
- */
-//@{
-#define BP_DMA_HRS_HRS14 (14U) //!< Bit position for DMA_HRS_HRS14.
-#define BM_DMA_HRS_HRS14 (0x00004000U) //!< Bit mask for DMA_HRS_HRS14.
-#define BS_DMA_HRS_HRS14 (1U) //!< Bit field size in bits for DMA_HRS_HRS14.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_HRS_HRS14 field.
-#define BR_DMA_HRS_HRS14(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS14))
-#endif
-//@}
-
-/*!
- * @name Register DMA_HRS, field HRS15[15] (RO)
- *
- * The HRS bit for its respective channel remains asserted for the period when a
- * Hardware Request is Present on the Channel. After the Request is completed
- * and Channel is free , the HRS bit is automatically cleared by hardware.
- *
- * Values:
- * - 0 - A hardware service request for channel 15 is not present
- * - 1 - A hardware service request for channel 15 is present
- */
-//@{
-#define BP_DMA_HRS_HRS15 (15U) //!< Bit position for DMA_HRS_HRS15.
-#define BM_DMA_HRS_HRS15 (0x00008000U) //!< Bit mask for DMA_HRS_HRS15.
-#define BS_DMA_HRS_HRS15 (1U) //!< Bit field size in bits for DMA_HRS_HRS15.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_HRS_HRS15 field.
-#define BR_DMA_HRS_HRS15(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS15))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_DMA_DCHPRIn - Channel n Priority Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_DCHPRIn - Channel n Priority Register (RW)
- *
- * Reset value: 0x00U
- *
- * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
- * contents of these registers define the unique priorities associated with each
- * channel . The channel priorities are evaluated by numeric value; for example, 0 is
- * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
- * program the channel priorities with unique values; otherwise, a configuration
- * error is reported. The range of the priority value is limited to the values of 0
- * through 15.
- */
-typedef union _hw_dma_dchprin
-{
- uint8_t U;
- struct _hw_dma_dchprin_bitfields
- {
- uint8_t CHPRI : 4; //!< [3:0] Channel n Arbitration Priority
- uint8_t RESERVED0 : 2; //!< [5:4]
- uint8_t DPA : 1; //!< [6] Disable Preempt Ability
- uint8_t ECP : 1; //!< [7] Enable Channel Preemption
- } B;
-} hw_dma_dchprin_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_DCHPRIn register
- */
-//@{
-#define HW_DMA_DCHPRIn_COUNT (16U)
-
-#define HW_DMA_DCHPRIn_ADDR(x, n) (REGS_DMA_BASE(x) + 0x100U + (0x1U * n))
-
-/* DMA channel index to DMA channel priority register array index conversion macro */
-#define HW_DMA_DCHPRIn_CHANNEL(n) (((n) & ~0x03U) | (3 - ((n) & 0x03U)))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_DCHPRIn(x, n) (*(__IO hw_dma_dchprin_t *) HW_DMA_DCHPRIn_ADDR(x, n))
-#define HW_DMA_DCHPRIn_RD(x, n) (HW_DMA_DCHPRIn(x, n).U)
-#define HW_DMA_DCHPRIn_WR(x, n, v) (HW_DMA_DCHPRIn(x, n).U = (v))
-#define HW_DMA_DCHPRIn_SET(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) | (v)))
-#define HW_DMA_DCHPRIn_CLR(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) & ~(v)))
-#define HW_DMA_DCHPRIn_TOG(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_DCHPRIn bitfields
- */
-
-/*!
- * @name Register DMA_DCHPRIn, field CHPRI[3:0] (RW)
- *
- * Channel priority when fixed-priority arbitration is enabled Reset value for
- * the channel priority fields, CHPRI, is equal to the corresponding channel
- * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
- */
-//@{
-#define BP_DMA_DCHPRIn_CHPRI (0U) //!< Bit position for DMA_DCHPRIn_CHPRI.
-#define BM_DMA_DCHPRIn_CHPRI (0x0FU) //!< Bit mask for DMA_DCHPRIn_CHPRI.
-#define BS_DMA_DCHPRIn_CHPRI (4U) //!< Bit field size in bits for DMA_DCHPRIn_CHPRI.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_DCHPRIn_CHPRI field.
-#define BR_DMA_DCHPRIn_CHPRI(x, n) (HW_DMA_DCHPRIn(x, n).B.CHPRI)
-#endif
-
-//! @brief Format value for bitfield DMA_DCHPRIn_CHPRI.
-#define BF_DMA_DCHPRIn_CHPRI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_DCHPRIn_CHPRI), uint8_t) & BM_DMA_DCHPRIn_CHPRI)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CHPRI field to a new value.
-#define BW_DMA_DCHPRIn_CHPRI(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, (HW_DMA_DCHPRIn_RD(x, n) & ~BM_DMA_DCHPRIn_CHPRI) | BF_DMA_DCHPRIn_CHPRI(v)))
-#endif
-//@}
-
-/*!
- * @name Register DMA_DCHPRIn, field DPA[6] (RW)
- *
- * Values:
- * - 0 - Channel n can suspend a lower priority channel
- * - 1 - Channel n cannot suspend any channel, regardless of channel priority
- */
-//@{
-#define BP_DMA_DCHPRIn_DPA (6U) //!< Bit position for DMA_DCHPRIn_DPA.
-#define BM_DMA_DCHPRIn_DPA (0x40U) //!< Bit mask for DMA_DCHPRIn_DPA.
-#define BS_DMA_DCHPRIn_DPA (1U) //!< Bit field size in bits for DMA_DCHPRIn_DPA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_DCHPRIn_DPA field.
-#define BR_DMA_DCHPRIn_DPA(x, n) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_DPA))
-#endif
-
-//! @brief Format value for bitfield DMA_DCHPRIn_DPA.
-#define BF_DMA_DCHPRIn_DPA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_DCHPRIn_DPA), uint8_t) & BM_DMA_DCHPRIn_DPA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DPA field to a new value.
-#define BW_DMA_DCHPRIn_DPA(x, n, v) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_DPA) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_DCHPRIn, field ECP[7] (RW)
- *
- * Values:
- * - 0 - Channel n cannot be suspended by a higher priority channel's service
- * request
- * - 1 - Channel n can be temporarily suspended by the service request of a
- * higher priority channel
- */
-//@{
-#define BP_DMA_DCHPRIn_ECP (7U) //!< Bit position for DMA_DCHPRIn_ECP.
-#define BM_DMA_DCHPRIn_ECP (0x80U) //!< Bit mask for DMA_DCHPRIn_ECP.
-#define BS_DMA_DCHPRIn_ECP (1U) //!< Bit field size in bits for DMA_DCHPRIn_ECP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_DCHPRIn_ECP field.
-#define BR_DMA_DCHPRIn_ECP(x, n) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_ECP))
-#endif
-
-//! @brief Format value for bitfield DMA_DCHPRIn_ECP.
-#define BF_DMA_DCHPRIn_ECP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_DCHPRIn_ECP), uint8_t) & BM_DMA_DCHPRIn_ECP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ECP field to a new value.
-#define BW_DMA_DCHPRIn_ECP(x, n, v) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_ECP) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_DMA_TCDn_SADDR - TCD Source Address
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_TCDn_SADDR - TCD Source Address (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_dma_tcdn_saddr
-{
- uint32_t U;
- struct _hw_dma_tcdn_saddr_bitfields
- {
- uint32_t SADDR : 32; //!< [31:0] Source Address
- } B;
-} hw_dma_tcdn_saddr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_TCDn_SADDR register
- */
-//@{
-#define HW_DMA_TCDn_SADDR_COUNT (16U)
-
-#define HW_DMA_TCDn_SADDR_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1000U + (0x20U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_TCDn_SADDR(x, n) (*(__IO hw_dma_tcdn_saddr_t *) HW_DMA_TCDn_SADDR_ADDR(x, n))
-#define HW_DMA_TCDn_SADDR_RD(x, n) (HW_DMA_TCDn_SADDR(x, n).U)
-#define HW_DMA_TCDn_SADDR_WR(x, n, v) (HW_DMA_TCDn_SADDR(x, n).U = (v))
-#define HW_DMA_TCDn_SADDR_SET(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) | (v)))
-#define HW_DMA_TCDn_SADDR_CLR(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) & ~(v)))
-#define HW_DMA_TCDn_SADDR_TOG(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_TCDn_SADDR bitfields
- */
-
-/*!
- * @name Register DMA_TCDn_SADDR, field SADDR[31:0] (RW)
- *
- * Memory address pointing to the source data.
- */
-//@{
-#define BP_DMA_TCDn_SADDR_SADDR (0U) //!< Bit position for DMA_TCDn_SADDR_SADDR.
-#define BM_DMA_TCDn_SADDR_SADDR (0xFFFFFFFFU) //!< Bit mask for DMA_TCDn_SADDR_SADDR.
-#define BS_DMA_TCDn_SADDR_SADDR (32U) //!< Bit field size in bits for DMA_TCDn_SADDR_SADDR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_SADDR_SADDR field.
-#define BR_DMA_TCDn_SADDR_SADDR(x, n) (HW_DMA_TCDn_SADDR(x, n).U)
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_SADDR_SADDR.
-#define BF_DMA_TCDn_SADDR_SADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_SADDR_SADDR), uint32_t) & BM_DMA_TCDn_SADDR_SADDR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SADDR field to a new value.
-#define BW_DMA_TCDn_SADDR_SADDR(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset (RW)
- *
- * Reset value: 0x0000U
- */
-typedef union _hw_dma_tcdn_soff
-{
- uint16_t U;
- struct _hw_dma_tcdn_soff_bitfields
- {
- uint16_t SOFF : 16; //!< [15:0] Source address signed offset
- } B;
-} hw_dma_tcdn_soff_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_TCDn_SOFF register
- */
-//@{
-#define HW_DMA_TCDn_SOFF_COUNT (16U)
-
-#define HW_DMA_TCDn_SOFF_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1004U + (0x20U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_TCDn_SOFF(x, n) (*(__IO hw_dma_tcdn_soff_t *) HW_DMA_TCDn_SOFF_ADDR(x, n))
-#define HW_DMA_TCDn_SOFF_RD(x, n) (HW_DMA_TCDn_SOFF(x, n).U)
-#define HW_DMA_TCDn_SOFF_WR(x, n, v) (HW_DMA_TCDn_SOFF(x, n).U = (v))
-#define HW_DMA_TCDn_SOFF_SET(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) | (v)))
-#define HW_DMA_TCDn_SOFF_CLR(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) & ~(v)))
-#define HW_DMA_TCDn_SOFF_TOG(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_TCDn_SOFF bitfields
- */
-
-/*!
- * @name Register DMA_TCDn_SOFF, field SOFF[15:0] (RW)
- *
- * Sign-extended offset applied to the current source address to form the
- * next-state value as each source read is completed.
- */
-//@{
-#define BP_DMA_TCDn_SOFF_SOFF (0U) //!< Bit position for DMA_TCDn_SOFF_SOFF.
-#define BM_DMA_TCDn_SOFF_SOFF (0xFFFFU) //!< Bit mask for DMA_TCDn_SOFF_SOFF.
-#define BS_DMA_TCDn_SOFF_SOFF (16U) //!< Bit field size in bits for DMA_TCDn_SOFF_SOFF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_SOFF_SOFF field.
-#define BR_DMA_TCDn_SOFF_SOFF(x, n) (HW_DMA_TCDn_SOFF(x, n).U)
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_SOFF_SOFF.
-#define BF_DMA_TCDn_SOFF_SOFF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_SOFF_SOFF), uint16_t) & BM_DMA_TCDn_SOFF_SOFF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SOFF field to a new value.
-#define BW_DMA_TCDn_SOFF_SOFF(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_DMA_TCDn_ATTR - TCD Transfer Attributes
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_TCDn_ATTR - TCD Transfer Attributes (RW)
- *
- * Reset value: 0x0000U
- */
-typedef union _hw_dma_tcdn_attr
-{
- uint16_t U;
- struct _hw_dma_tcdn_attr_bitfields
- {
- uint16_t DSIZE : 3; //!< [2:0] Destination Data Transfer Size
- uint16_t DMOD : 5; //!< [7:3] Destination Address Modulo
- uint16_t SSIZE : 3; //!< [10:8] Source data transfer size
- uint16_t SMOD : 5; //!< [15:11] Source Address Modulo.
- } B;
-} hw_dma_tcdn_attr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_TCDn_ATTR register
- */
-//@{
-#define HW_DMA_TCDn_ATTR_COUNT (16U)
-
-#define HW_DMA_TCDn_ATTR_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1006U + (0x20U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_TCDn_ATTR(x, n) (*(__IO hw_dma_tcdn_attr_t *) HW_DMA_TCDn_ATTR_ADDR(x, n))
-#define HW_DMA_TCDn_ATTR_RD(x, n) (HW_DMA_TCDn_ATTR(x, n).U)
-#define HW_DMA_TCDn_ATTR_WR(x, n, v) (HW_DMA_TCDn_ATTR(x, n).U = (v))
-#define HW_DMA_TCDn_ATTR_SET(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) | (v)))
-#define HW_DMA_TCDn_ATTR_CLR(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) & ~(v)))
-#define HW_DMA_TCDn_ATTR_TOG(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_TCDn_ATTR bitfields
- */
-
-/*!
- * @name Register DMA_TCDn_ATTR, field DSIZE[2:0] (RW)
- *
- * See the SSIZE definition
- */
-//@{
-#define BP_DMA_TCDn_ATTR_DSIZE (0U) //!< Bit position for DMA_TCDn_ATTR_DSIZE.
-#define BM_DMA_TCDn_ATTR_DSIZE (0x0007U) //!< Bit mask for DMA_TCDn_ATTR_DSIZE.
-#define BS_DMA_TCDn_ATTR_DSIZE (3U) //!< Bit field size in bits for DMA_TCDn_ATTR_DSIZE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_ATTR_DSIZE field.
-#define BR_DMA_TCDn_ATTR_DSIZE(x, n) (HW_DMA_TCDn_ATTR(x, n).B.DSIZE)
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_ATTR_DSIZE.
-#define BF_DMA_TCDn_ATTR_DSIZE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_ATTR_DSIZE), uint16_t) & BM_DMA_TCDn_ATTR_DSIZE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DSIZE field to a new value.
-#define BW_DMA_TCDn_ATTR_DSIZE(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_DSIZE) | BF_DMA_TCDn_ATTR_DSIZE(v)))
-#endif
-//@}
-
-/*!
- * @name Register DMA_TCDn_ATTR, field DMOD[7:3] (RW)
- *
- * See the SMOD definition
- */
-//@{
-#define BP_DMA_TCDn_ATTR_DMOD (3U) //!< Bit position for DMA_TCDn_ATTR_DMOD.
-#define BM_DMA_TCDn_ATTR_DMOD (0x00F8U) //!< Bit mask for DMA_TCDn_ATTR_DMOD.
-#define BS_DMA_TCDn_ATTR_DMOD (5U) //!< Bit field size in bits for DMA_TCDn_ATTR_DMOD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_ATTR_DMOD field.
-#define BR_DMA_TCDn_ATTR_DMOD(x, n) (HW_DMA_TCDn_ATTR(x, n).B.DMOD)
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_ATTR_DMOD.
-#define BF_DMA_TCDn_ATTR_DMOD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_ATTR_DMOD), uint16_t) & BM_DMA_TCDn_ATTR_DMOD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DMOD field to a new value.
-#define BW_DMA_TCDn_ATTR_DMOD(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_DMOD) | BF_DMA_TCDn_ATTR_DMOD(v)))
-#endif
-//@}
-
-/*!
- * @name Register DMA_TCDn_ATTR, field SSIZE[10:8] (RW)
- *
- * The attempted use of a Reserved encoding causes a configuration error.
- *
- * Values:
- * - 000 - 8-bit
- * - 001 - 16-bit
- * - 010 - 32-bit
- * - 011 - Reserved
- * - 100 - 16-byte
- * - 101 - 32-byte
- * - 110 - Reserved
- * - 111 - Reserved
- */
-//@{
-#define BP_DMA_TCDn_ATTR_SSIZE (8U) //!< Bit position for DMA_TCDn_ATTR_SSIZE.
-#define BM_DMA_TCDn_ATTR_SSIZE (0x0700U) //!< Bit mask for DMA_TCDn_ATTR_SSIZE.
-#define BS_DMA_TCDn_ATTR_SSIZE (3U) //!< Bit field size in bits for DMA_TCDn_ATTR_SSIZE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_ATTR_SSIZE field.
-#define BR_DMA_TCDn_ATTR_SSIZE(x, n) (HW_DMA_TCDn_ATTR(x, n).B.SSIZE)
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_ATTR_SSIZE.
-#define BF_DMA_TCDn_ATTR_SSIZE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_ATTR_SSIZE), uint16_t) & BM_DMA_TCDn_ATTR_SSIZE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SSIZE field to a new value.
-#define BW_DMA_TCDn_ATTR_SSIZE(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_SSIZE) | BF_DMA_TCDn_ATTR_SSIZE(v)))
-#endif
-//@}
-
-/*!
- * @name Register DMA_TCDn_ATTR, field SMOD[15:11] (RW)
- *
- * Values:
- * - 0 - Source address modulo feature is disabled
- */
-//@{
-#define BP_DMA_TCDn_ATTR_SMOD (11U) //!< Bit position for DMA_TCDn_ATTR_SMOD.
-#define BM_DMA_TCDn_ATTR_SMOD (0xF800U) //!< Bit mask for DMA_TCDn_ATTR_SMOD.
-#define BS_DMA_TCDn_ATTR_SMOD (5U) //!< Bit field size in bits for DMA_TCDn_ATTR_SMOD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_ATTR_SMOD field.
-#define BR_DMA_TCDn_ATTR_SMOD(x, n) (HW_DMA_TCDn_ATTR(x, n).B.SMOD)
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_ATTR_SMOD.
-#define BF_DMA_TCDn_ATTR_SMOD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_ATTR_SMOD), uint16_t) & BM_DMA_TCDn_ATTR_SMOD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SMOD field to a new value.
-#define BW_DMA_TCDn_ATTR_SMOD(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_SMOD) | BF_DMA_TCDn_ATTR_SMOD(v)))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register, or one of the next two registers (TCD_NBYTES_MLOFFNO,
- * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which
- * register to use depends on whether minor loop mapping is disabled, enabled but not
- * used for this channel, or enabled and used. TCD word 2 is defined as follows
- * if: Minor loop mapping is disabled (CR[EMLM] = 0) If minor loop mapping is
- * enabled, see the TCD_NBYTES_MLOFFNO and TCD_NBYTES_MLOFFYES register descriptions
- * for TCD word 2's definition.
- */
-typedef union _hw_dma_tcdn_nbytes_mlno
-{
- uint32_t U;
- struct _hw_dma_tcdn_nbytes_mlno_bitfields
- {
- uint32_t NBYTES : 32; //!< [31:0] Minor Byte Transfer Count
- } B;
-} hw_dma_tcdn_nbytes_mlno_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_TCDn_NBYTES_MLNO register
- */
-//@{
-#define HW_DMA_TCDn_NBYTES_MLNO_COUNT (16U)
-
-#define HW_DMA_TCDn_NBYTES_MLNO_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1008U + (0x20U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_TCDn_NBYTES_MLNO(x, n) (*(__IO hw_dma_tcdn_nbytes_mlno_t *) HW_DMA_TCDn_NBYTES_MLNO_ADDR(x, n))
-#define HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U)
-#define HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U = (v))
-#define HW_DMA_TCDn_NBYTES_MLNO_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) | (v)))
-#define HW_DMA_TCDn_NBYTES_MLNO_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) & ~(v)))
-#define HW_DMA_TCDn_NBYTES_MLNO_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_TCDn_NBYTES_MLNO bitfields
- */
-
-/*!
- * @name Register DMA_TCDn_NBYTES_MLNO, field NBYTES[31:0] (RW)
- *
- * Number of bytes to be transferred in each service request of the channel. As
- * a channel activates, the appropriate TCD contents load into the eDMA engine,
- * and the appropriate reads and writes perform until the minor byte transfer
- * count has transferred. This is an indivisible operation and cannot be halted.
- * (Although, it may be stalled by using the bandwidth control field, or via
- * preemption.) After the minor count is exhausted, the SADDR and DADDR values are
- * written back into the TCD memory, the major iteration count is decremented and
- * restored to the TCD memory. If the major iteration count is completed, additional
- * processing is performed. An NBYTES value of 0x0000_0000 is interpreted as a 4
- * GB transfer.
- */
-//@{
-#define BP_DMA_TCDn_NBYTES_MLNO_NBYTES (0U) //!< Bit position for DMA_TCDn_NBYTES_MLNO_NBYTES.
-#define BM_DMA_TCDn_NBYTES_MLNO_NBYTES (0xFFFFFFFFU) //!< Bit mask for DMA_TCDn_NBYTES_MLNO_NBYTES.
-#define BS_DMA_TCDn_NBYTES_MLNO_NBYTES (32U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLNO_NBYTES.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_NBYTES_MLNO_NBYTES field.
-#define BR_DMA_TCDn_NBYTES_MLNO_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U)
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLNO_NBYTES.
-#define BF_DMA_TCDn_NBYTES_MLNO_NBYTES(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLNO_NBYTES), uint32_t) & BM_DMA_TCDn_NBYTES_MLNO_NBYTES)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the NBYTES field to a new value.
-#define BW_DMA_TCDn_NBYTES_MLNO_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (RW)
- *
- * Reset value: 0x00000000U
- *
- * One of three registers (this register, TCD_NBYTES_MLNO, or
- * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which register to use
- * depends on whether minor loop mapping is disabled, enabled but not used for
- * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
- * loop mapping is enabled (CR[EMLM] = 1) and SMLOE = 0 and DMLOE = 0 If minor
- * loop mapping is enabled and SMLOE or DMLOE is set, then refer to the
- * TCD_NBYTES_MLOFFYES register description. If minor loop mapping is disabled, then refer to
- * the TCD_NBYTES_MLNO register description.
- */
-typedef union _hw_dma_tcdn_nbytes_mloffno
-{
- uint32_t U;
- struct _hw_dma_tcdn_nbytes_mloffno_bitfields
- {
- uint32_t NBYTES : 30; //!< [29:0] Minor Byte Transfer Count
- uint32_t DMLOE : 1; //!< [30] Destination Minor Loop Offset enable
- uint32_t SMLOE : 1; //!< [31] Source Minor Loop Offset Enable
- } B;
-} hw_dma_tcdn_nbytes_mloffno_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_TCDn_NBYTES_MLOFFNO register
- */
-//@{
-#define HW_DMA_TCDn_NBYTES_MLOFFNO_COUNT (16U)
-
-#define HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1008U + (0x20U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_TCDn_NBYTES_MLOFFNO(x, n) (*(__IO hw_dma_tcdn_nbytes_mloffno_t *) HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n))
-#define HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).U)
-#define HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).U = (v))
-#define HW_DMA_TCDn_NBYTES_MLOFFNO_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) | (v)))
-#define HW_DMA_TCDn_NBYTES_MLOFFNO_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) & ~(v)))
-#define HW_DMA_TCDn_NBYTES_MLOFFNO_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_TCDn_NBYTES_MLOFFNO bitfields
- */
-
-/*!
- * @name Register DMA_TCDn_NBYTES_MLOFFNO, field NBYTES[29:0] (RW)
- *
- * Number of bytes to be transferred in each service request of the channel. As
- * a channel activates, the appropriate TCD contents load into the eDMA engine,
- * and the appropriate reads and writes perform until the minor byte transfer
- * count has transferred. This is an indivisible operation and cannot be halted;
- * although, it may be stalled by using the bandwidth control field, or via
- * preemption. After the minor count is exhausted, the SADDR and DADDR values are written
- * back into the TCD memory, the major iteration count is decremented and
- * restored to the TCD memory. If the major iteration count is completed, additional
- * processing is performed.
- */
-//@{
-#define BP_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (0U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_NBYTES.
-#define BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (0x3FFFFFFFU) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_NBYTES.
-#define BS_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (30U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_NBYTES.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_NBYTES field.
-#define BR_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).B.NBYTES)
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_NBYTES.
-#define BF_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFNO_NBYTES), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the NBYTES field to a new value.
-#define BW_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES) | BF_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(v)))
-#endif
-//@}
-
-/*!
- * @name Register DMA_TCDn_NBYTES_MLOFFNO, field DMLOE[30] (RW)
- *
- * Selects whether the minor loop offset is applied to the destination address
- * upon minor loop completion.
- *
- * Values:
- * - 0 - The minor loop offset is not applied to the DADDR
- * - 1 - The minor loop offset is applied to the DADDR
- */
-//@{
-#define BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (30U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_DMLOE.
-#define BM_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (0x40000000U) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_DMLOE.
-#define BS_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (1U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_DMLOE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_DMLOE field.
-#define BR_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE))
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_DMLOE.
-#define BF_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFNO_DMLOE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DMLOE field to a new value.
-#define BW_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_TCDn_NBYTES_MLOFFNO, field SMLOE[31] (RW)
- *
- * Selects whether the minor loop offset is applied to the source address upon
- * minor loop completion.
- *
- * Values:
- * - 0 - The minor loop offset is not applied to the SADDR
- * - 1 - The minor loop offset is applied to the SADDR
- */
-//@{
-#define BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (31U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_SMLOE.
-#define BM_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (0x80000000U) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_SMLOE.
-#define BS_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (1U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_SMLOE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_SMLOE field.
-#define BR_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE))
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_SMLOE.
-#define BF_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFNO_SMLOE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SMLOE field to a new value.
-#define BW_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE) = (v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (RW)
- *
- * Reset value: 0x00000000U
- *
- * One of three registers (this register, TCD_NBYTES_MLNO, or
- * TCD_NBYTES_MLOFFNO), defines the number of bytes to transfer per request. Which register to use
- * depends on whether minor loop mapping is disabled, enabled but not used for
- * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
- * loop mapping is enabled (CR[EMLM] = 1) and Minor loop offset is enabled (SMLOE
- * or DMLOE = 1) If minor loop mapping is enabled and SMLOE and DMLOE are cleared,
- * then refer to the TCD_NBYTES_MLOFFNO register description. If minor loop
- * mapping is disabled, then refer to the TCD_NBYTES_MLNO register description.
- */
-typedef union _hw_dma_tcdn_nbytes_mloffyes
-{
- uint32_t U;
- struct _hw_dma_tcdn_nbytes_mloffyes_bitfields
- {
- uint32_t NBYTES : 10; //!< [9:0] Minor Byte Transfer Count
- uint32_t MLOFF : 20; //!< [29:10] If SMLOE or DMLOE is set, this
- //! field represents a sign-extended offset applied to the source or
- //! destination address to form the next-state value after the minor loop completes.
- uint32_t DMLOE : 1; //!< [30] Destination Minor Loop Offset enable
- uint32_t SMLOE : 1; //!< [31] Source Minor Loop Offset Enable
- } B;
-} hw_dma_tcdn_nbytes_mloffyes_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_TCDn_NBYTES_MLOFFYES register
- */
-//@{
-#define HW_DMA_TCDn_NBYTES_MLOFFYES_COUNT (16U)
-
-#define HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1008U + (0x20U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_TCDn_NBYTES_MLOFFYES(x, n) (*(__IO hw_dma_tcdn_nbytes_mloffyes_t *) HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n))
-#define HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).U)
-#define HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).U = (v))
-#define HW_DMA_TCDn_NBYTES_MLOFFYES_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) | (v)))
-#define HW_DMA_TCDn_NBYTES_MLOFFYES_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~(v)))
-#define HW_DMA_TCDn_NBYTES_MLOFFYES_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_TCDn_NBYTES_MLOFFYES bitfields
- */
-
-/*!
- * @name Register DMA_TCDn_NBYTES_MLOFFYES, field NBYTES[9:0] (RW)
- *
- * Number of bytes to be transferred in each service request of the channel. As
- * a channel activates, the appropriate TCD contents load into the eDMA engine,
- * and the appropriate reads and writes perform until the minor byte transfer
- * count has transferred. This is an indivisible operation and cannot be halted.
- * (Although, it may be stalled by using the bandwidth control field, or via
- * preemption.) After the minor count is exhausted, the SADDR and DADDR values are
- * written back into the TCD memory, the major iteration count is decremented and
- * restored to the TCD memory. If the major iteration count is completed, additional
- * processing is performed.
- */
-//@{
-#define BP_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (0U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_NBYTES.
-#define BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (0x000003FFU) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_NBYTES.
-#define BS_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (10U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_NBYTES.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_NBYTES field.
-#define BR_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).B.NBYTES)
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_NBYTES.
-#define BF_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFYES_NBYTES), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the NBYTES field to a new value.
-#define BW_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES) | BF_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(v)))
-#endif
-//@}
-
-/*!
- * @name Register DMA_TCDn_NBYTES_MLOFFYES, field MLOFF[29:10] (RW)
- */
-//@{
-#define BP_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (10U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_MLOFF.
-#define BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (0x3FFFFC00U) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_MLOFF.
-#define BS_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (20U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_MLOFF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_MLOFF field.
-#define BR_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).B.MLOFF)
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_MLOFF.
-#define BF_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFYES_MLOFF), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MLOFF field to a new value.
-#define BW_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF) | BF_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(v)))
-#endif
-//@}
-
-/*!
- * @name Register DMA_TCDn_NBYTES_MLOFFYES, field DMLOE[30] (RW)
- *
- * Selects whether the minor loop offset is applied to the destination address
- * upon minor loop completion.
- *
- * Values:
- * - 0 - The minor loop offset is not applied to the DADDR
- * - 1 - The minor loop offset is applied to the DADDR
- */
-//@{
-#define BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (30U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_DMLOE.
-#define BM_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (0x40000000U) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_DMLOE.
-#define BS_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (1U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_DMLOE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_DMLOE field.
-#define BR_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE))
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_DMLOE.
-#define BF_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFYES_DMLOE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DMLOE field to a new value.
-#define BW_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_TCDn_NBYTES_MLOFFYES, field SMLOE[31] (RW)
- *
- * Selects whether the minor loop offset is applied to the source address upon
- * minor loop completion.
- *
- * Values:
- * - 0 - The minor loop offset is not applied to the SADDR
- * - 1 - The minor loop offset is applied to the SADDR
- */
-//@{
-#define BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (31U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_SMLOE.
-#define BM_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (0x80000000U) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_SMLOE.
-#define BS_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (1U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_SMLOE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_SMLOE field.
-#define BR_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE))
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_SMLOE.
-#define BF_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFYES_SMLOE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SMLOE field to a new value.
-#define BW_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE) = (v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_dma_tcdn_slast
-{
- uint32_t U;
- struct _hw_dma_tcdn_slast_bitfields
- {
- uint32_t SLAST : 32; //!< [31:0] Last source Address Adjustment
- } B;
-} hw_dma_tcdn_slast_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_TCDn_SLAST register
- */
-//@{
-#define HW_DMA_TCDn_SLAST_COUNT (16U)
-
-#define HW_DMA_TCDn_SLAST_ADDR(x, n) (REGS_DMA_BASE(x) + 0x100CU + (0x20U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_TCDn_SLAST(x, n) (*(__IO hw_dma_tcdn_slast_t *) HW_DMA_TCDn_SLAST_ADDR(x, n))
-#define HW_DMA_TCDn_SLAST_RD(x, n) (HW_DMA_TCDn_SLAST(x, n).U)
-#define HW_DMA_TCDn_SLAST_WR(x, n, v) (HW_DMA_TCDn_SLAST(x, n).U = (v))
-#define HW_DMA_TCDn_SLAST_SET(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) | (v)))
-#define HW_DMA_TCDn_SLAST_CLR(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) & ~(v)))
-#define HW_DMA_TCDn_SLAST_TOG(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_TCDn_SLAST bitfields
- */
-
-/*!
- * @name Register DMA_TCDn_SLAST, field SLAST[31:0] (RW)
- *
- * Adjustment value added to the source address at the completion of the major
- * iteration count. This value can be applied to restore the source address to the
- * initial value, or adjust the address to reference the next data structure.
- * This register uses two's complement notation; the overflow bit is discarded.
- */
-//@{
-#define BP_DMA_TCDn_SLAST_SLAST (0U) //!< Bit position for DMA_TCDn_SLAST_SLAST.
-#define BM_DMA_TCDn_SLAST_SLAST (0xFFFFFFFFU) //!< Bit mask for DMA_TCDn_SLAST_SLAST.
-#define BS_DMA_TCDn_SLAST_SLAST (32U) //!< Bit field size in bits for DMA_TCDn_SLAST_SLAST.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_SLAST_SLAST field.
-#define BR_DMA_TCDn_SLAST_SLAST(x, n) (HW_DMA_TCDn_SLAST(x, n).U)
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_SLAST_SLAST.
-#define BF_DMA_TCDn_SLAST_SLAST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_SLAST_SLAST), uint32_t) & BM_DMA_TCDn_SLAST_SLAST)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SLAST field to a new value.
-#define BW_DMA_TCDn_SLAST_SLAST(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_DMA_TCDn_DADDR - TCD Destination Address
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_TCDn_DADDR - TCD Destination Address (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_dma_tcdn_daddr
-{
- uint32_t U;
- struct _hw_dma_tcdn_daddr_bitfields
- {
- uint32_t DADDR : 32; //!< [31:0] Destination Address
- } B;
-} hw_dma_tcdn_daddr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_TCDn_DADDR register
- */
-//@{
-#define HW_DMA_TCDn_DADDR_COUNT (16U)
-
-#define HW_DMA_TCDn_DADDR_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1010U + (0x20U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_TCDn_DADDR(x, n) (*(__IO hw_dma_tcdn_daddr_t *) HW_DMA_TCDn_DADDR_ADDR(x, n))
-#define HW_DMA_TCDn_DADDR_RD(x, n) (HW_DMA_TCDn_DADDR(x, n).U)
-#define HW_DMA_TCDn_DADDR_WR(x, n, v) (HW_DMA_TCDn_DADDR(x, n).U = (v))
-#define HW_DMA_TCDn_DADDR_SET(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) | (v)))
-#define HW_DMA_TCDn_DADDR_CLR(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) & ~(v)))
-#define HW_DMA_TCDn_DADDR_TOG(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_TCDn_DADDR bitfields
- */
-
-/*!
- * @name Register DMA_TCDn_DADDR, field DADDR[31:0] (RW)
- *
- * Memory address pointing to the destination data.
- */
-//@{
-#define BP_DMA_TCDn_DADDR_DADDR (0U) //!< Bit position for DMA_TCDn_DADDR_DADDR.
-#define BM_DMA_TCDn_DADDR_DADDR (0xFFFFFFFFU) //!< Bit mask for DMA_TCDn_DADDR_DADDR.
-#define BS_DMA_TCDn_DADDR_DADDR (32U) //!< Bit field size in bits for DMA_TCDn_DADDR_DADDR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_DADDR_DADDR field.
-#define BR_DMA_TCDn_DADDR_DADDR(x, n) (HW_DMA_TCDn_DADDR(x, n).U)
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_DADDR_DADDR.
-#define BF_DMA_TCDn_DADDR_DADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_DADDR_DADDR), uint32_t) & BM_DMA_TCDn_DADDR_DADDR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DADDR field to a new value.
-#define BW_DMA_TCDn_DADDR_DADDR(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset (RW)
- *
- * Reset value: 0x0000U
- */
-typedef union _hw_dma_tcdn_doff
-{
- uint16_t U;
- struct _hw_dma_tcdn_doff_bitfields
- {
- uint16_t DOFF : 16; //!< [15:0] Destination Address Signed offset
- } B;
-} hw_dma_tcdn_doff_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_TCDn_DOFF register
- */
-//@{
-#define HW_DMA_TCDn_DOFF_COUNT (16U)
-
-#define HW_DMA_TCDn_DOFF_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1014U + (0x20U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_TCDn_DOFF(x, n) (*(__IO hw_dma_tcdn_doff_t *) HW_DMA_TCDn_DOFF_ADDR(x, n))
-#define HW_DMA_TCDn_DOFF_RD(x, n) (HW_DMA_TCDn_DOFF(x, n).U)
-#define HW_DMA_TCDn_DOFF_WR(x, n, v) (HW_DMA_TCDn_DOFF(x, n).U = (v))
-#define HW_DMA_TCDn_DOFF_SET(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) | (v)))
-#define HW_DMA_TCDn_DOFF_CLR(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) & ~(v)))
-#define HW_DMA_TCDn_DOFF_TOG(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_TCDn_DOFF bitfields
- */
-
-/*!
- * @name Register DMA_TCDn_DOFF, field DOFF[15:0] (RW)
- *
- * Sign-extended offset applied to the current destination address to form the
- * next-state value as each destination write is completed.
- */
-//@{
-#define BP_DMA_TCDn_DOFF_DOFF (0U) //!< Bit position for DMA_TCDn_DOFF_DOFF.
-#define BM_DMA_TCDn_DOFF_DOFF (0xFFFFU) //!< Bit mask for DMA_TCDn_DOFF_DOFF.
-#define BS_DMA_TCDn_DOFF_DOFF (16U) //!< Bit field size in bits for DMA_TCDn_DOFF_DOFF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_DOFF_DOFF field.
-#define BR_DMA_TCDn_DOFF_DOFF(x, n) (HW_DMA_TCDn_DOFF(x, n).U)
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_DOFF_DOFF.
-#define BF_DMA_TCDn_DOFF_DOFF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_DOFF_DOFF), uint16_t) & BM_DMA_TCDn_DOFF_DOFF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DOFF field to a new value.
-#define BW_DMA_TCDn_DOFF_DOFF(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
- *
- * Reset value: 0x0000U
- *
- * If TCDn_CITER[ELINK] is cleared, the TCDn_CITER register is defined as
- * follows.
- */
-typedef union _hw_dma_tcdn_citer_elinkno
-{
- uint16_t U;
- struct _hw_dma_tcdn_citer_elinkno_bitfields
- {
- uint16_t CITER : 15; //!< [14:0] Current Major Iteration Count
- uint16_t ELINK : 1; //!< [15] Enable channel-to-channel linking on
- //! minor-loop complete
- } B;
-} hw_dma_tcdn_citer_elinkno_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_TCDn_CITER_ELINKNO register
- */
-//@{
-#define HW_DMA_TCDn_CITER_ELINKNO_COUNT (16U)
-
-#define HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1016U + (0x20U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_TCDn_CITER_ELINKNO(x, n) (*(__IO hw_dma_tcdn_citer_elinkno_t *) HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n))
-#define HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) (HW_DMA_TCDn_CITER_ELINKNO(x, n).U)
-#define HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO(x, n).U = (v))
-#define HW_DMA_TCDn_CITER_ELINKNO_SET(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) | (v)))
-#define HW_DMA_TCDn_CITER_ELINKNO_CLR(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) & ~(v)))
-#define HW_DMA_TCDn_CITER_ELINKNO_TOG(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_TCDn_CITER_ELINKNO bitfields
- */
-
-/*!
- * @name Register DMA_TCDn_CITER_ELINKNO, field CITER[14:0] (RW)
- *
- * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
- * major loop count for the channel. It is decremented each time the minor loop is
- * completed and updated in the transfer control descriptor memory. After the
- * major iteration count is exhausted, the channel performs a number of operations
- * (e.g., final source and destination address calculations), optionally generating
- * an interrupt to signal channel completion before reloading the CITER field
- * from the beginning iteration count (BITER) field. When the CITER field is
- * initially loaded by software, it must be set to the same value as that contained in
- * the BITER field. If the channel is configured to execute a single service
- * request, the initial values of BITER and CITER should be 0x0001.
- */
-//@{
-#define BP_DMA_TCDn_CITER_ELINKNO_CITER (0U) //!< Bit position for DMA_TCDn_CITER_ELINKNO_CITER.
-#define BM_DMA_TCDn_CITER_ELINKNO_CITER (0x7FFFU) //!< Bit mask for DMA_TCDn_CITER_ELINKNO_CITER.
-#define BS_DMA_TCDn_CITER_ELINKNO_CITER (15U) //!< Bit field size in bits for DMA_TCDn_CITER_ELINKNO_CITER.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_CITER_ELINKNO_CITER field.
-#define BR_DMA_TCDn_CITER_ELINKNO_CITER(x, n) (HW_DMA_TCDn_CITER_ELINKNO(x, n).B.CITER)
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_CITER_ELINKNO_CITER.
-#define BF_DMA_TCDn_CITER_ELINKNO_CITER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CITER_ELINKNO_CITER), uint16_t) & BM_DMA_TCDn_CITER_ELINKNO_CITER)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CITER field to a new value.
-#define BW_DMA_TCDn_CITER_ELINKNO_CITER(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, (HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKNO_CITER) | BF_DMA_TCDn_CITER_ELINKNO_CITER(v)))
-#endif
-//@}
-
-/*!
- * @name Register DMA_TCDn_CITER_ELINKNO, field ELINK[15] (RW)
- *
- * As the channel completes the minor loop, this flag enables linking to another
- * channel, defined by the LINKCH field. The link target channel initiates a
- * channel service request via an internal mechanism that sets the TCDn_CSR[START]
- * bit of the specified channel. If channel linking is disabled, the CITER value
- * is extended to 15 bits in place of a link channel number. If the major loop is
- * exhausted, this link mechanism is suppressed in favor of the MAJORELINK
- * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
- * configuration error is reported.
- *
- * Values:
- * - 0 - The channel-to-channel linking is disabled
- * - 1 - The channel-to-channel linking is enabled
- */
-//@{
-#define BP_DMA_TCDn_CITER_ELINKNO_ELINK (15U) //!< Bit position for DMA_TCDn_CITER_ELINKNO_ELINK.
-#define BM_DMA_TCDn_CITER_ELINKNO_ELINK (0x8000U) //!< Bit mask for DMA_TCDn_CITER_ELINKNO_ELINK.
-#define BS_DMA_TCDn_CITER_ELINKNO_ELINK (1U) //!< Bit field size in bits for DMA_TCDn_CITER_ELINKNO_ELINK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_CITER_ELINKNO_ELINK field.
-#define BR_DMA_TCDn_CITER_ELINKNO_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKNO_ELINK))
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_CITER_ELINKNO_ELINK.
-#define BF_DMA_TCDn_CITER_ELINKNO_ELINK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CITER_ELINKNO_ELINK), uint16_t) & BM_DMA_TCDn_CITER_ELINKNO_ELINK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ELINK field to a new value.
-#define BW_DMA_TCDn_CITER_ELINKNO_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKNO_ELINK) = (v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
- *
- * Reset value: 0x0000U
- *
- * If TCDn_CITER[ELINK] is set, the TCDn_CITER register is defined as follows.
- */
-typedef union _hw_dma_tcdn_citer_elinkyes
-{
- uint16_t U;
- struct _hw_dma_tcdn_citer_elinkyes_bitfields
- {
- uint16_t CITER : 9; //!< [8:0] Current Major Iteration Count
- uint16_t LINKCH : 4; //!< [12:9] Link Channel Number
- uint16_t RESERVED0 : 2; //!< [14:13]
- uint16_t ELINK : 1; //!< [15] Enable channel-to-channel linking on
- //! minor-loop complete
- } B;
-} hw_dma_tcdn_citer_elinkyes_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_TCDn_CITER_ELINKYES register
- */
-//@{
-#define HW_DMA_TCDn_CITER_ELINKYES_COUNT (16U)
-
-#define HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1016U + (0x20U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_TCDn_CITER_ELINKYES(x, n) (*(__IO hw_dma_tcdn_citer_elinkyes_t *) HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n))
-#define HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).U)
-#define HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES(x, n).U = (v))
-#define HW_DMA_TCDn_CITER_ELINKYES_SET(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) | (v)))
-#define HW_DMA_TCDn_CITER_ELINKYES_CLR(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~(v)))
-#define HW_DMA_TCDn_CITER_ELINKYES_TOG(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_TCDn_CITER_ELINKYES bitfields
- */
-
-/*!
- * @name Register DMA_TCDn_CITER_ELINKYES, field CITER[8:0] (RW)
- *
- * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
- * major loop count for the channel. It is decremented each time the minor loop is
- * completed and updated in the transfer control descriptor memory. After the
- * major iteration count is exhausted, the channel performs a number of operations
- * (e.g., final source and destination address calculations), optionally generating
- * an interrupt to signal channel completion before reloading the CITER field
- * from the beginning iteration count (BITER) field. When the CITER field is
- * initially loaded by software, it must be set to the same value as that contained in
- * the BITER field. If the channel is configured to execute a single service
- * request, the initial values of BITER and CITER should be 0x0001.
- */
-//@{
-#define BP_DMA_TCDn_CITER_ELINKYES_CITER (0U) //!< Bit position for DMA_TCDn_CITER_ELINKYES_CITER.
-#define BM_DMA_TCDn_CITER_ELINKYES_CITER (0x01FFU) //!< Bit mask for DMA_TCDn_CITER_ELINKYES_CITER.
-#define BS_DMA_TCDn_CITER_ELINKYES_CITER (9U) //!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_CITER.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_CITER field.
-#define BR_DMA_TCDn_CITER_ELINKYES_CITER(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).B.CITER)
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_CITER.
-#define BF_DMA_TCDn_CITER_ELINKYES_CITER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CITER_ELINKYES_CITER), uint16_t) & BM_DMA_TCDn_CITER_ELINKYES_CITER)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CITER field to a new value.
-#define BW_DMA_TCDn_CITER_ELINKYES_CITER(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKYES_CITER) | BF_DMA_TCDn_CITER_ELINKYES_CITER(v)))
-#endif
-//@}
-
-/*!
- * @name Register DMA_TCDn_CITER_ELINKYES, field LINKCH[12:9] (RW)
- *
- * If channel-to-channel linking is enabled (ELINK = 1), then after the minor
- * loop is exhausted, the eDMA engine initiates a channel service request to the
- * channel defined by these four bits by setting that channel's TCDn_CSR[START] bit.
- */
-//@{
-#define BP_DMA_TCDn_CITER_ELINKYES_LINKCH (9U) //!< Bit position for DMA_TCDn_CITER_ELINKYES_LINKCH.
-#define BM_DMA_TCDn_CITER_ELINKYES_LINKCH (0x1E00U) //!< Bit mask for DMA_TCDn_CITER_ELINKYES_LINKCH.
-#define BS_DMA_TCDn_CITER_ELINKYES_LINKCH (4U) //!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_LINKCH.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_LINKCH field.
-#define BR_DMA_TCDn_CITER_ELINKYES_LINKCH(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).B.LINKCH)
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_LINKCH.
-#define BF_DMA_TCDn_CITER_ELINKYES_LINKCH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CITER_ELINKYES_LINKCH), uint16_t) & BM_DMA_TCDn_CITER_ELINKYES_LINKCH)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LINKCH field to a new value.
-#define BW_DMA_TCDn_CITER_ELINKYES_LINKCH(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKYES_LINKCH) | BF_DMA_TCDn_CITER_ELINKYES_LINKCH(v)))
-#endif
-//@}
-
-/*!
- * @name Register DMA_TCDn_CITER_ELINKYES, field ELINK[15] (RW)
- *
- * As the channel completes the minor loop, this flag enables linking to another
- * channel, defined by the LINKCH field. The link target channel initiates a
- * channel service request via an internal mechanism that sets the TCDn_CSR[START]
- * bit of the specified channel. If channel linking is disabled, the CITER value
- * is extended to 15 bits in place of a link channel number. If the major loop is
- * exhausted, this link mechanism is suppressed in favor of the MAJORELINK
- * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
- * configuration error is reported.
- *
- * Values:
- * - 0 - The channel-to-channel linking is disabled
- * - 1 - The channel-to-channel linking is enabled
- */
-//@{
-#define BP_DMA_TCDn_CITER_ELINKYES_ELINK (15U) //!< Bit position for DMA_TCDn_CITER_ELINKYES_ELINK.
-#define BM_DMA_TCDn_CITER_ELINKYES_ELINK (0x8000U) //!< Bit mask for DMA_TCDn_CITER_ELINKYES_ELINK.
-#define BS_DMA_TCDn_CITER_ELINKYES_ELINK (1U) //!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_ELINK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_ELINK field.
-#define BR_DMA_TCDn_CITER_ELINKYES_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKYES_ELINK))
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_ELINK.
-#define BF_DMA_TCDn_CITER_ELINKYES_ELINK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CITER_ELINKYES_ELINK), uint16_t) & BM_DMA_TCDn_CITER_ELINKYES_ELINK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ELINK field to a new value.
-#define BW_DMA_TCDn_CITER_ELINKYES_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKYES_ELINK) = (v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_dma_tcdn_dlastsga
-{
- uint32_t U;
- struct _hw_dma_tcdn_dlastsga_bitfields
- {
- uint32_t DLASTSGA : 32; //!< [31:0]
- } B;
-} hw_dma_tcdn_dlastsga_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_TCDn_DLASTSGA register
- */
-//@{
-#define HW_DMA_TCDn_DLASTSGA_COUNT (16U)
-
-#define HW_DMA_TCDn_DLASTSGA_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1018U + (0x20U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_TCDn_DLASTSGA(x, n) (*(__IO hw_dma_tcdn_dlastsga_t *) HW_DMA_TCDn_DLASTSGA_ADDR(x, n))
-#define HW_DMA_TCDn_DLASTSGA_RD(x, n) (HW_DMA_TCDn_DLASTSGA(x, n).U)
-#define HW_DMA_TCDn_DLASTSGA_WR(x, n, v) (HW_DMA_TCDn_DLASTSGA(x, n).U = (v))
-#define HW_DMA_TCDn_DLASTSGA_SET(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) | (v)))
-#define HW_DMA_TCDn_DLASTSGA_CLR(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) & ~(v)))
-#define HW_DMA_TCDn_DLASTSGA_TOG(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_TCDn_DLASTSGA bitfields
- */
-
-/*!
- * @name Register DMA_TCDn_DLASTSGA, field DLASTSGA[31:0] (RW)
- *
- * Destination last address adjustment or the memory address for the next
- * transfer control descriptor to be loaded into this channel (scatter/gather). If
- * (TCDn_CSR[ESG] = 0), then: Adjustment value added to the destination address at
- * the completion of the major iteration count. This value can apply to restore the
- * destination address to the initial value or adjust the address to reference
- * the next data structure. This field uses two's complement notation for the
- * final destination address adjustment. Otherwise: This address points to the
- * beginning of a 0-modulo-32-byte region containing the next transfer control
- * descriptor to be loaded into this channel. This channel reload is performed as the
- * major iteration count completes. The scatter/gather address must be
- * 0-modulo-32-byte, else a configuration error is reported.
- */
-//@{
-#define BP_DMA_TCDn_DLASTSGA_DLASTSGA (0U) //!< Bit position for DMA_TCDn_DLASTSGA_DLASTSGA.
-#define BM_DMA_TCDn_DLASTSGA_DLASTSGA (0xFFFFFFFFU) //!< Bit mask for DMA_TCDn_DLASTSGA_DLASTSGA.
-#define BS_DMA_TCDn_DLASTSGA_DLASTSGA (32U) //!< Bit field size in bits for DMA_TCDn_DLASTSGA_DLASTSGA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_DLASTSGA_DLASTSGA field.
-#define BR_DMA_TCDn_DLASTSGA_DLASTSGA(x, n) (HW_DMA_TCDn_DLASTSGA(x, n).U)
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_DLASTSGA_DLASTSGA.
-#define BF_DMA_TCDn_DLASTSGA_DLASTSGA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_DLASTSGA_DLASTSGA), uint32_t) & BM_DMA_TCDn_DLASTSGA_DLASTSGA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DLASTSGA field to a new value.
-#define BW_DMA_TCDn_DLASTSGA_DLASTSGA(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_DMA_TCDn_CSR - TCD Control and Status
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_TCDn_CSR - TCD Control and Status (RW)
- *
- * Reset value: 0x0000U
- */
-typedef union _hw_dma_tcdn_csr
-{
- uint16_t U;
- struct _hw_dma_tcdn_csr_bitfields
- {
- uint16_t START : 1; //!< [0] Channel Start
- uint16_t INTMAJOR : 1; //!< [1] Enable an interrupt when major
- //! iteration count completes
- uint16_t INTHALF : 1; //!< [2] Enable an interrupt when major counter
- //! is half complete.
- uint16_t DREQ : 1; //!< [3] Disable Request
- uint16_t ESG : 1; //!< [4] Enable Scatter/Gather Processing
- uint16_t MAJORELINK : 1; //!< [5] Enable channel-to-channel linking
- //! on major loop complete
- uint16_t ACTIVE : 1; //!< [6] Channel Active
- uint16_t DONE : 1; //!< [7] Channel Done
- uint16_t MAJORLINKCH : 4; //!< [11:8] Link Channel Number
- uint16_t RESERVED0 : 2; //!< [13:12]
- uint16_t BWC : 2; //!< [15:14] Bandwidth Control
- } B;
-} hw_dma_tcdn_csr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_TCDn_CSR register
- */
-//@{
-#define HW_DMA_TCDn_CSR_COUNT (16U)
-
-#define HW_DMA_TCDn_CSR_ADDR(x, n) (REGS_DMA_BASE(x) + 0x101CU + (0x20U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_TCDn_CSR(x, n) (*(__IO hw_dma_tcdn_csr_t *) HW_DMA_TCDn_CSR_ADDR(x, n))
-#define HW_DMA_TCDn_CSR_RD(x, n) (HW_DMA_TCDn_CSR(x, n).U)
-#define HW_DMA_TCDn_CSR_WR(x, n, v) (HW_DMA_TCDn_CSR(x, n).U = (v))
-#define HW_DMA_TCDn_CSR_SET(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) | (v)))
-#define HW_DMA_TCDn_CSR_CLR(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) & ~(v)))
-#define HW_DMA_TCDn_CSR_TOG(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_TCDn_CSR bitfields
- */
-
-/*!
- * @name Register DMA_TCDn_CSR, field START[0] (RW)
- *
- * If this flag is set, the channel is requesting service. The eDMA hardware
- * automatically clears this flag after the channel begins execution.
- *
- * Values:
- * - 0 - The channel is not explicitly started
- * - 1 - The channel is explicitly started via a software initiated service
- * request
- */
-//@{
-#define BP_DMA_TCDn_CSR_START (0U) //!< Bit position for DMA_TCDn_CSR_START.
-#define BM_DMA_TCDn_CSR_START (0x0001U) //!< Bit mask for DMA_TCDn_CSR_START.
-#define BS_DMA_TCDn_CSR_START (1U) //!< Bit field size in bits for DMA_TCDn_CSR_START.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_CSR_START field.
-#define BR_DMA_TCDn_CSR_START(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_START))
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_CSR_START.
-#define BF_DMA_TCDn_CSR_START(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_START), uint16_t) & BM_DMA_TCDn_CSR_START)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the START field to a new value.
-#define BW_DMA_TCDn_CSR_START(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_START) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_TCDn_CSR, field INTMAJOR[1] (RW)
- *
- * If this flag is set, the channel generates an interrupt request by setting
- * the appropriate bit in the INT when the current major iteration count reaches
- * zero.
- *
- * Values:
- * - 0 - The end-of-major loop interrupt is disabled
- * - 1 - The end-of-major loop interrupt is enabled
- */
-//@{
-#define BP_DMA_TCDn_CSR_INTMAJOR (1U) //!< Bit position for DMA_TCDn_CSR_INTMAJOR.
-#define BM_DMA_TCDn_CSR_INTMAJOR (0x0002U) //!< Bit mask for DMA_TCDn_CSR_INTMAJOR.
-#define BS_DMA_TCDn_CSR_INTMAJOR (1U) //!< Bit field size in bits for DMA_TCDn_CSR_INTMAJOR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_CSR_INTMAJOR field.
-#define BR_DMA_TCDn_CSR_INTMAJOR(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTMAJOR))
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_CSR_INTMAJOR.
-#define BF_DMA_TCDn_CSR_INTMAJOR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_INTMAJOR), uint16_t) & BM_DMA_TCDn_CSR_INTMAJOR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INTMAJOR field to a new value.
-#define BW_DMA_TCDn_CSR_INTMAJOR(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTMAJOR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_TCDn_CSR, field INTHALF[2] (RW)
- *
- * If this flag is set, the channel generates an interrupt request by setting
- * the appropriate bit in the INT register when the current major iteration count
- * reaches the halfway point. Specifically, the comparison performed by the eDMA
- * engine is (CITER == (BITER >> 1)). This halfway point interrupt request is
- * provided to support double-buffered (aka ping-pong) schemes or other types of data
- * movement where the processor needs an early indication of the transfer's
- * progress. If BITER is set, do not use INTHALF. Use INTMAJOR instead.
- *
- * Values:
- * - 0 - The half-point interrupt is disabled
- * - 1 - The half-point interrupt is enabled
- */
-//@{
-#define BP_DMA_TCDn_CSR_INTHALF (2U) //!< Bit position for DMA_TCDn_CSR_INTHALF.
-#define BM_DMA_TCDn_CSR_INTHALF (0x0004U) //!< Bit mask for DMA_TCDn_CSR_INTHALF.
-#define BS_DMA_TCDn_CSR_INTHALF (1U) //!< Bit field size in bits for DMA_TCDn_CSR_INTHALF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_CSR_INTHALF field.
-#define BR_DMA_TCDn_CSR_INTHALF(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTHALF))
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_CSR_INTHALF.
-#define BF_DMA_TCDn_CSR_INTHALF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_INTHALF), uint16_t) & BM_DMA_TCDn_CSR_INTHALF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INTHALF field to a new value.
-#define BW_DMA_TCDn_CSR_INTHALF(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTHALF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_TCDn_CSR, field DREQ[3] (RW)
- *
- * If this flag is set, the eDMA hardware automatically clears the corresponding
- * ERQ bit when the current major iteration count reaches zero.
- *
- * Values:
- * - 0 - The channel's ERQ bit is not affected
- * - 1 - The channel's ERQ bit is cleared when the major loop is complete
- */
-//@{
-#define BP_DMA_TCDn_CSR_DREQ (3U) //!< Bit position for DMA_TCDn_CSR_DREQ.
-#define BM_DMA_TCDn_CSR_DREQ (0x0008U) //!< Bit mask for DMA_TCDn_CSR_DREQ.
-#define BS_DMA_TCDn_CSR_DREQ (1U) //!< Bit field size in bits for DMA_TCDn_CSR_DREQ.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_CSR_DREQ field.
-#define BR_DMA_TCDn_CSR_DREQ(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DREQ))
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_CSR_DREQ.
-#define BF_DMA_TCDn_CSR_DREQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_DREQ), uint16_t) & BM_DMA_TCDn_CSR_DREQ)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DREQ field to a new value.
-#define BW_DMA_TCDn_CSR_DREQ(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DREQ) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_TCDn_CSR, field ESG[4] (RW)
- *
- * As the channel completes the major loop, this flag enables scatter/gather
- * processing in the current channel. If enabled, the eDMA engine uses DLASTSGA as a
- * memory pointer to a 0-modulo-32 address containing a 32-byte data structure
- * loaded as the transfer control descriptor into the local memory. To support the
- * dynamic scatter/gather coherency model, this field is forced to zero when
- * written to while the TCDn_CSR[DONE] bit is set.
- *
- * Values:
- * - 0 - The current channel's TCD is normal format.
- * - 1 - The current channel's TCD specifies a scatter gather format. The
- * DLASTSGA field provides a memory pointer to the next TCD to be loaded into this
- * channel after the major loop completes its execution.
- */
-//@{
-#define BP_DMA_TCDn_CSR_ESG (4U) //!< Bit position for DMA_TCDn_CSR_ESG.
-#define BM_DMA_TCDn_CSR_ESG (0x0010U) //!< Bit mask for DMA_TCDn_CSR_ESG.
-#define BS_DMA_TCDn_CSR_ESG (1U) //!< Bit field size in bits for DMA_TCDn_CSR_ESG.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_CSR_ESG field.
-#define BR_DMA_TCDn_CSR_ESG(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ESG))
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_CSR_ESG.
-#define BF_DMA_TCDn_CSR_ESG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_ESG), uint16_t) & BM_DMA_TCDn_CSR_ESG)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ESG field to a new value.
-#define BW_DMA_TCDn_CSR_ESG(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ESG) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_TCDn_CSR, field MAJORELINK[5] (RW)
- *
- * As the channel completes the major loop, this flag enables the linking to
- * another channel, defined by MAJORLINKCH. The link target channel initiates a
- * channel service request via an internal mechanism that sets the TCDn_CSR[START]
- * bit of the specified channel. To support the dynamic linking coherency model,
- * this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set.
- *
- * Values:
- * - 0 - The channel-to-channel linking is disabled
- * - 1 - The channel-to-channel linking is enabled
- */
-//@{
-#define BP_DMA_TCDn_CSR_MAJORELINK (5U) //!< Bit position for DMA_TCDn_CSR_MAJORELINK.
-#define BM_DMA_TCDn_CSR_MAJORELINK (0x0020U) //!< Bit mask for DMA_TCDn_CSR_MAJORELINK.
-#define BS_DMA_TCDn_CSR_MAJORELINK (1U) //!< Bit field size in bits for DMA_TCDn_CSR_MAJORELINK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_CSR_MAJORELINK field.
-#define BR_DMA_TCDn_CSR_MAJORELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_MAJORELINK))
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_CSR_MAJORELINK.
-#define BF_DMA_TCDn_CSR_MAJORELINK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_MAJORELINK), uint16_t) & BM_DMA_TCDn_CSR_MAJORELINK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MAJORELINK field to a new value.
-#define BW_DMA_TCDn_CSR_MAJORELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_MAJORELINK) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_TCDn_CSR, field ACTIVE[6] (RW)
- *
- * This flag signals the channel is currently in execution. It is set when
- * channel service begins, and the eDMA clears it as the minor loop completes or if
- * any error condition is detected. This bit resets to zero.
- */
-//@{
-#define BP_DMA_TCDn_CSR_ACTIVE (6U) //!< Bit position for DMA_TCDn_CSR_ACTIVE.
-#define BM_DMA_TCDn_CSR_ACTIVE (0x0040U) //!< Bit mask for DMA_TCDn_CSR_ACTIVE.
-#define BS_DMA_TCDn_CSR_ACTIVE (1U) //!< Bit field size in bits for DMA_TCDn_CSR_ACTIVE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_CSR_ACTIVE field.
-#define BR_DMA_TCDn_CSR_ACTIVE(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ACTIVE))
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_CSR_ACTIVE.
-#define BF_DMA_TCDn_CSR_ACTIVE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_ACTIVE), uint16_t) & BM_DMA_TCDn_CSR_ACTIVE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ACTIVE field to a new value.
-#define BW_DMA_TCDn_CSR_ACTIVE(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ACTIVE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_TCDn_CSR, field DONE[7] (RW)
- *
- * This flag indicates the eDMA has completed the major loop. The eDMA engine
- * sets it as the CITER count reaches zero; The software clears it, or the hardware
- * when the channel is activated. This bit must be cleared to write the
- * MAJORELINK or ESG bits.
- */
-//@{
-#define BP_DMA_TCDn_CSR_DONE (7U) //!< Bit position for DMA_TCDn_CSR_DONE.
-#define BM_DMA_TCDn_CSR_DONE (0x0080U) //!< Bit mask for DMA_TCDn_CSR_DONE.
-#define BS_DMA_TCDn_CSR_DONE (1U) //!< Bit field size in bits for DMA_TCDn_CSR_DONE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_CSR_DONE field.
-#define BR_DMA_TCDn_CSR_DONE(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DONE))
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_CSR_DONE.
-#define BF_DMA_TCDn_CSR_DONE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_DONE), uint16_t) & BM_DMA_TCDn_CSR_DONE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DONE field to a new value.
-#define BW_DMA_TCDn_CSR_DONE(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DONE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMA_TCDn_CSR, field MAJORLINKCH[11:8] (RW)
- *
- * If (MAJORELINK = 0) then No channel-to-channel linking (or chaining) is
- * performed after the major loop counter is exhausted. else After the major loop
- * counter is exhausted, the eDMA engine initiates a channel service request at the
- * channel defined by these six bits by setting that channel's TCDn_CSR[START] bit.
- */
-//@{
-#define BP_DMA_TCDn_CSR_MAJORLINKCH (8U) //!< Bit position for DMA_TCDn_CSR_MAJORLINKCH.
-#define BM_DMA_TCDn_CSR_MAJORLINKCH (0x0F00U) //!< Bit mask for DMA_TCDn_CSR_MAJORLINKCH.
-#define BS_DMA_TCDn_CSR_MAJORLINKCH (4U) //!< Bit field size in bits for DMA_TCDn_CSR_MAJORLINKCH.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_CSR_MAJORLINKCH field.
-#define BR_DMA_TCDn_CSR_MAJORLINKCH(x, n) (HW_DMA_TCDn_CSR(x, n).B.MAJORLINKCH)
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_CSR_MAJORLINKCH.
-#define BF_DMA_TCDn_CSR_MAJORLINKCH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_MAJORLINKCH), uint16_t) & BM_DMA_TCDn_CSR_MAJORLINKCH)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MAJORLINKCH field to a new value.
-#define BW_DMA_TCDn_CSR_MAJORLINKCH(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, (HW_DMA_TCDn_CSR_RD(x, n) & ~BM_DMA_TCDn_CSR_MAJORLINKCH) | BF_DMA_TCDn_CSR_MAJORLINKCH(v)))
-#endif
-//@}
-
-/*!
- * @name Register DMA_TCDn_CSR, field BWC[15:14] (RW)
- *
- * Throttles the amount of bus bandwidth consumed by the eDMA. In general, as
- * the eDMA processes the minor loop, it continuously generates read/write
- * sequences until the minor count is exhausted. This field forces the eDMA to stall
- * after the completion of each read/write access to control the bus request
- * bandwidth seen by the crossbar switch. If the source and destination sizes are equal,
- * this field is ignored between the first and second transfers and after the
- * last write of each minor loop. This behavior is a side effect of reducing
- * start-up latency.
- *
- * Values:
- * - 00 - No eDMA engine stalls
- * - 01 - Reserved
- * - 10 - eDMA engine stalls for 4 cycles after each r/w
- * - 11 - eDMA engine stalls for 8 cycles after each r/w
- */
-//@{
-#define BP_DMA_TCDn_CSR_BWC (14U) //!< Bit position for DMA_TCDn_CSR_BWC.
-#define BM_DMA_TCDn_CSR_BWC (0xC000U) //!< Bit mask for DMA_TCDn_CSR_BWC.
-#define BS_DMA_TCDn_CSR_BWC (2U) //!< Bit field size in bits for DMA_TCDn_CSR_BWC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_CSR_BWC field.
-#define BR_DMA_TCDn_CSR_BWC(x, n) (HW_DMA_TCDn_CSR(x, n).B.BWC)
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_CSR_BWC.
-#define BF_DMA_TCDn_CSR_BWC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_BWC), uint16_t) & BM_DMA_TCDn_CSR_BWC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BWC field to a new value.
-#define BW_DMA_TCDn_CSR_BWC(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, (HW_DMA_TCDn_CSR_RD(x, n) & ~BM_DMA_TCDn_CSR_BWC) | BF_DMA_TCDn_CSR_BWC(v)))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
- *
- * Reset value: 0x0000U
- *
- * If the TCDn_BITER[ELINK] bit is cleared, the TCDn_BITER register is defined
- * as follows.
- */
-typedef union _hw_dma_tcdn_biter_elinkno
-{
- uint16_t U;
- struct _hw_dma_tcdn_biter_elinkno_bitfields
- {
- uint16_t BITER : 15; //!< [14:0] Starting Major Iteration Count
- uint16_t ELINK : 1; //!< [15] Enables channel-to-channel linking on
- //! minor loop complete
- } B;
-} hw_dma_tcdn_biter_elinkno_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_TCDn_BITER_ELINKNO register
- */
-//@{
-#define HW_DMA_TCDn_BITER_ELINKNO_COUNT (16U)
-
-#define HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n) (REGS_DMA_BASE(x) + 0x101EU + (0x20U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_TCDn_BITER_ELINKNO(x, n) (*(__IO hw_dma_tcdn_biter_elinkno_t *) HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n))
-#define HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) (HW_DMA_TCDn_BITER_ELINKNO(x, n).U)
-#define HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO(x, n).U = (v))
-#define HW_DMA_TCDn_BITER_ELINKNO_SET(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) | (v)))
-#define HW_DMA_TCDn_BITER_ELINKNO_CLR(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) & ~(v)))
-#define HW_DMA_TCDn_BITER_ELINKNO_TOG(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_TCDn_BITER_ELINKNO bitfields
- */
-
-/*!
- * @name Register DMA_TCDn_BITER_ELINKNO, field BITER[14:0] (RW)
- *
- * As the transfer control descriptor is first loaded by software, this 9-bit
- * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
- * field. As the major iteration count is exhausted, the contents of this field
- * are reloaded into the CITER field. When the software loads the TCD, this field
- * must be set equal to the corresponding CITER field; otherwise, a configuration
- * error is reported. As the major iteration count is exhausted, the contents of
- * this field is reloaded into the CITER field. If the channel is configured to
- * execute a single service request, the initial values of BITER and CITER should
- * be 0x0001.
- */
-//@{
-#define BP_DMA_TCDn_BITER_ELINKNO_BITER (0U) //!< Bit position for DMA_TCDn_BITER_ELINKNO_BITER.
-#define BM_DMA_TCDn_BITER_ELINKNO_BITER (0x7FFFU) //!< Bit mask for DMA_TCDn_BITER_ELINKNO_BITER.
-#define BS_DMA_TCDn_BITER_ELINKNO_BITER (15U) //!< Bit field size in bits for DMA_TCDn_BITER_ELINKNO_BITER.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_BITER_ELINKNO_BITER field.
-#define BR_DMA_TCDn_BITER_ELINKNO_BITER(x, n) (HW_DMA_TCDn_BITER_ELINKNO(x, n).B.BITER)
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_BITER_ELINKNO_BITER.
-#define BF_DMA_TCDn_BITER_ELINKNO_BITER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_BITER_ELINKNO_BITER), uint16_t) & BM_DMA_TCDn_BITER_ELINKNO_BITER)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BITER field to a new value.
-#define BW_DMA_TCDn_BITER_ELINKNO_BITER(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, (HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKNO_BITER) | BF_DMA_TCDn_BITER_ELINKNO_BITER(v)))
-#endif
-//@}
-
-/*!
- * @name Register DMA_TCDn_BITER_ELINKNO, field ELINK[15] (RW)
- *
- * As the channel completes the minor loop, this flag enables the linking to
- * another channel, defined by BITER[LINKCH]. The link target channel initiates a
- * channel service request via an internal mechanism that sets the TCDn_CSR[START]
- * bit of the specified channel. If channel linking is disabled, the BITER value
- * extends to 15 bits in place of a link channel number. If the major loop is
- * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
- * linking. When the software loads the TCD, this field must be set equal to the
- * corresponding CITER field; otherwise, a configuration error is reported. As the
- * major iteration count is exhausted, the contents of this field is reloaded
- * into the CITER field.
- *
- * Values:
- * - 0 - The channel-to-channel linking is disabled
- * - 1 - The channel-to-channel linking is enabled
- */
-//@{
-#define BP_DMA_TCDn_BITER_ELINKNO_ELINK (15U) //!< Bit position for DMA_TCDn_BITER_ELINKNO_ELINK.
-#define BM_DMA_TCDn_BITER_ELINKNO_ELINK (0x8000U) //!< Bit mask for DMA_TCDn_BITER_ELINKNO_ELINK.
-#define BS_DMA_TCDn_BITER_ELINKNO_ELINK (1U) //!< Bit field size in bits for DMA_TCDn_BITER_ELINKNO_ELINK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_BITER_ELINKNO_ELINK field.
-#define BR_DMA_TCDn_BITER_ELINKNO_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKNO_ELINK))
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_BITER_ELINKNO_ELINK.
-#define BF_DMA_TCDn_BITER_ELINKNO_ELINK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_BITER_ELINKNO_ELINK), uint16_t) & BM_DMA_TCDn_BITER_ELINKNO_ELINK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ELINK field to a new value.
-#define BW_DMA_TCDn_BITER_ELINKNO_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKNO_ELINK) = (v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
- *
- * Reset value: 0x0000U
- *
- * If the TCDn_BITER[ELINK] bit is set, the TCDn_BITER register is defined as
- * follows.
- */
-typedef union _hw_dma_tcdn_biter_elinkyes
-{
- uint16_t U;
- struct _hw_dma_tcdn_biter_elinkyes_bitfields
- {
- uint16_t BITER : 9; //!< [8:0] Starting Major Iteration Count
- uint16_t LINKCH : 4; //!< [12:9] Link Channel Number
- uint16_t RESERVED0 : 2; //!< [14:13]
- uint16_t ELINK : 1; //!< [15] Enables channel-to-channel linking on
- //! minor loop complete
- } B;
-} hw_dma_tcdn_biter_elinkyes_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMA_TCDn_BITER_ELINKYES register
- */
-//@{
-#define HW_DMA_TCDn_BITER_ELINKYES_COUNT (16U)
-
-#define HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n) (REGS_DMA_BASE(x) + 0x101EU + (0x20U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMA_TCDn_BITER_ELINKYES(x, n) (*(__IO hw_dma_tcdn_biter_elinkyes_t *) HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n))
-#define HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).U)
-#define HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES(x, n).U = (v))
-#define HW_DMA_TCDn_BITER_ELINKYES_SET(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) | (v)))
-#define HW_DMA_TCDn_BITER_ELINKYES_CLR(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~(v)))
-#define HW_DMA_TCDn_BITER_ELINKYES_TOG(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMA_TCDn_BITER_ELINKYES bitfields
- */
-
-/*!
- * @name Register DMA_TCDn_BITER_ELINKYES, field BITER[8:0] (RW)
- *
- * As the transfer control descriptor is first loaded by software, this 9-bit
- * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
- * field. As the major iteration count is exhausted, the contents of this field
- * are reloaded into the CITER field. When the software loads the TCD, this field
- * must be set equal to the corresponding CITER field; otherwise, a configuration
- * error is reported. As the major iteration count is exhausted, the contents of
- * this field is reloaded into the CITER field. If the channel is configured to
- * execute a single service request, the initial values of BITER and CITER should
- * be 0x0001.
- */
-//@{
-#define BP_DMA_TCDn_BITER_ELINKYES_BITER (0U) //!< Bit position for DMA_TCDn_BITER_ELINKYES_BITER.
-#define BM_DMA_TCDn_BITER_ELINKYES_BITER (0x01FFU) //!< Bit mask for DMA_TCDn_BITER_ELINKYES_BITER.
-#define BS_DMA_TCDn_BITER_ELINKYES_BITER (9U) //!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_BITER.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_BITER field.
-#define BR_DMA_TCDn_BITER_ELINKYES_BITER(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).B.BITER)
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_BITER.
-#define BF_DMA_TCDn_BITER_ELINKYES_BITER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_BITER_ELINKYES_BITER), uint16_t) & BM_DMA_TCDn_BITER_ELINKYES_BITER)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BITER field to a new value.
-#define BW_DMA_TCDn_BITER_ELINKYES_BITER(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKYES_BITER) | BF_DMA_TCDn_BITER_ELINKYES_BITER(v)))
-#endif
-//@}
-
-/*!
- * @name Register DMA_TCDn_BITER_ELINKYES, field LINKCH[12:9] (RW)
- *
- * If channel-to-channel linking is enabled (ELINK = 1), then after the minor
- * loop is exhausted, the eDMA engine initiates a channel service request at the
- * channel defined by these four bits by setting that channel's TCDn_CSR[START]
- * bit. When the software loads the TCD, this field must be set equal to the
- * corresponding CITER field; otherwise, a configuration error is reported. As the major
- * iteration count is exhausted, the contents of this field is reloaded into the
- * CITER field.
- */
-//@{
-#define BP_DMA_TCDn_BITER_ELINKYES_LINKCH (9U) //!< Bit position for DMA_TCDn_BITER_ELINKYES_LINKCH.
-#define BM_DMA_TCDn_BITER_ELINKYES_LINKCH (0x1E00U) //!< Bit mask for DMA_TCDn_BITER_ELINKYES_LINKCH.
-#define BS_DMA_TCDn_BITER_ELINKYES_LINKCH (4U) //!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_LINKCH.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_LINKCH field.
-#define BR_DMA_TCDn_BITER_ELINKYES_LINKCH(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).B.LINKCH)
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_LINKCH.
-#define BF_DMA_TCDn_BITER_ELINKYES_LINKCH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_BITER_ELINKYES_LINKCH), uint16_t) & BM_DMA_TCDn_BITER_ELINKYES_LINKCH)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LINKCH field to a new value.
-#define BW_DMA_TCDn_BITER_ELINKYES_LINKCH(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKYES_LINKCH) | BF_DMA_TCDn_BITER_ELINKYES_LINKCH(v)))
-#endif
-//@}
-
-/*!
- * @name Register DMA_TCDn_BITER_ELINKYES, field ELINK[15] (RW)
- *
- * As the channel completes the minor loop, this flag enables the linking to
- * another channel, defined by BITER[LINKCH]. The link target channel initiates a
- * channel service request via an internal mechanism that sets the TCDn_CSR[START]
- * bit of the specified channel. If channel linking disables, the BITER value
- * extends to 15 bits in place of a link channel number. If the major loop is
- * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
- * linking. When the software loads the TCD, this field must be set equal to the
- * corresponding CITER field; otherwise, a configuration error is reported. As the
- * major iteration count is exhausted, the contents of this field is reloaded into
- * the CITER field.
- *
- * Values:
- * - 0 - The channel-to-channel linking is disabled
- * - 1 - The channel-to-channel linking is enabled
- */
-//@{
-#define BP_DMA_TCDn_BITER_ELINKYES_ELINK (15U) //!< Bit position for DMA_TCDn_BITER_ELINKYES_ELINK.
-#define BM_DMA_TCDn_BITER_ELINKYES_ELINK (0x8000U) //!< Bit mask for DMA_TCDn_BITER_ELINKYES_ELINK.
-#define BS_DMA_TCDn_BITER_ELINKYES_ELINK (1U) //!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_ELINK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_ELINK field.
-#define BR_DMA_TCDn_BITER_ELINKYES_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKYES_ELINK))
-#endif
-
-//! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_ELINK.
-#define BF_DMA_TCDn_BITER_ELINKYES_ELINK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_BITER_ELINKYES_ELINK), uint16_t) & BM_DMA_TCDn_BITER_ELINKYES_ELINK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ELINK field to a new value.
-#define BW_DMA_TCDn_BITER_ELINKYES_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKYES_ELINK) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_dma_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All DMA module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_dma
-{
- __IO hw_dma_cr_t CR; //!< [0x0] Control Register
- __I hw_dma_es_t ES; //!< [0x4] Error Status Register
- uint8_t _reserved0[4];
- __IO hw_dma_erq_t ERQ; //!< [0xC] Enable Request Register
- uint8_t _reserved1[4];
- __IO hw_dma_eei_t EEI; //!< [0x14] Enable Error Interrupt Register
- __O hw_dma_ceei_t CEEI; //!< [0x18] Clear Enable Error Interrupt Register
- __O hw_dma_seei_t SEEI; //!< [0x19] Set Enable Error Interrupt Register
- __O hw_dma_cerq_t CERQ; //!< [0x1A] Clear Enable Request Register
- __O hw_dma_serq_t SERQ; //!< [0x1B] Set Enable Request Register
- __O hw_dma_cdne_t CDNE; //!< [0x1C] Clear DONE Status Bit Register
- __O hw_dma_ssrt_t SSRT; //!< [0x1D] Set START Bit Register
- __O hw_dma_cerr_t CERR; //!< [0x1E] Clear Error Register
- __O hw_dma_cint_t CINT; //!< [0x1F] Clear Interrupt Request Register
- uint8_t _reserved2[4];
- __IO hw_dma_int_t INT; //!< [0x24] Interrupt Request Register
- uint8_t _reserved3[4];
- __IO hw_dma_err_t ERR; //!< [0x2C] Error Register
- uint8_t _reserved4[4];
- __I hw_dma_hrs_t HRS; //!< [0x34] Hardware Request Status Register
- uint8_t _reserved5[200];
- __IO hw_dma_dchprin_t DCHPRIn[16]; //!< [0x100] Channel n Priority Register
- uint8_t _reserved6[3824];
- struct {
- __IO hw_dma_tcdn_saddr_t TCDn_SADDR; //!< [0x1000] TCD Source Address
- __IO hw_dma_tcdn_soff_t TCDn_SOFF; //!< [0x1004] TCD Signed Source Address Offset
- __IO hw_dma_tcdn_attr_t TCDn_ATTR; //!< [0x1006] TCD Transfer Attributes
- union {
- __IO hw_dma_tcdn_nbytes_mlno_t TCDn_NBYTES_MLNO; //!< [0x1008] TCD Minor Byte Count (Minor Loop Disabled)
- __IO hw_dma_tcdn_nbytes_mloffno_t TCDn_NBYTES_MLOFFNO; //!< [0x1008] TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
- __IO hw_dma_tcdn_nbytes_mloffyes_t TCDn_NBYTES_MLOFFYES; //!< [0x1008] TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
- };
- __IO hw_dma_tcdn_slast_t TCDn_SLAST; //!< [0x100C] TCD Last Source Address Adjustment
- __IO hw_dma_tcdn_daddr_t TCDn_DADDR; //!< [0x1010] TCD Destination Address
- __IO hw_dma_tcdn_doff_t TCDn_DOFF; //!< [0x1014] TCD Signed Destination Address Offset
- union {
- __IO hw_dma_tcdn_citer_elinkno_t TCDn_CITER_ELINKNO; //!< [0x1016] TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
- __IO hw_dma_tcdn_citer_elinkyes_t TCDn_CITER_ELINKYES; //!< [0x1016] TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
- };
- __IO hw_dma_tcdn_dlastsga_t TCDn_DLASTSGA; //!< [0x1018] TCD Last Destination Address Adjustment/Scatter Gather Address
- __IO hw_dma_tcdn_csr_t TCDn_CSR; //!< [0x101C] TCD Control and Status
- union {
- __IO hw_dma_tcdn_biter_elinkno_t TCDn_BITER_ELINKNO; //!< [0x101E] TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
- __IO hw_dma_tcdn_biter_elinkyes_t TCDn_BITER_ELINKYES; //!< [0x101E] TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
- };
- } TCD[16];
-} hw_dma_t;
-#pragma pack()
-
-//! @brief Macro to access all DMA registers.
-//! @param x DMA instance number.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_DMA(0)</code>.
-#define HW_DMA(x) (*(hw_dma_t *) REGS_DMA_BASE(x))
-#endif
-
-#endif // __HW_DMA_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_dmamux.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,220 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_DMAMUX_REGISTERS_H__
-#define __HW_DMAMUX_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 DMAMUX
- *
- * DMA channel multiplexor
- *
- * Registers defined in this header file:
- * - HW_DMAMUX_CHCFGn - Channel Configuration register
- *
- * - hw_dmamux_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_DMAMUX_BASE
-#define HW_DMAMUX_INSTANCE_COUNT (1U) //!< Number of instances of the DMAMUX module.
-#define HW_DMAMUX0 (0U) //!< Instance number for DMAMUX.
-#define REGS_DMAMUX0_BASE (0x40021000U) //!< Base address for DMAMUX.
-
-//! @brief Table of base addresses for DMAMUX instances.
-static const uint32_t __g_regs_DMAMUX_base_addresses[] = {
- REGS_DMAMUX0_BASE,
- };
-
-//! @brief Get the base address of DMAMUX by instance number.
-//! @param x DMAMUX instance number, from 0 through 0.
-#define REGS_DMAMUX_BASE(x) (__g_regs_DMAMUX_base_addresses[(x)])
-
-//! @brief Get the instance number given a base address.
-//! @param b Base address for an instance of DMAMUX.
-#define REGS_DMAMUX_INSTANCE(b) ((b) == REGS_DMAMUX0_BASE ? HW_DMAMUX0 : 0)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_DMAMUX_CHCFGn - Channel Configuration register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_DMAMUX_CHCFGn - Channel Configuration register (RW)
- *
- * Reset value: 0x00U
- *
- * Each of the DMA channels can be independently enabled/disabled and associated
- * with one of the DMA slots (peripheral slots or always-on slots) in the
- * system. Setting multiple CHCFG registers with the same source value will result in
- * unpredictable behavior. This is true, even if a channel is disabled (ENBL==0).
- * Before changing the trigger or source settings, a DMA channel must be disabled
- * via CHCFGn[ENBL].
- */
-typedef union _hw_dmamux_chcfgn
-{
- uint8_t U;
- struct _hw_dmamux_chcfgn_bitfields
- {
- uint8_t SOURCE : 6; //!< [5:0] DMA Channel Source (Slot)
- uint8_t TRIG : 1; //!< [6] DMA Channel Trigger Enable
- uint8_t ENBL : 1; //!< [7] DMA Channel Enable
- } B;
-} hw_dmamux_chcfgn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire DMAMUX_CHCFGn register
- */
-//@{
-#define HW_DMAMUX_CHCFGn_COUNT (16U)
-
-#define HW_DMAMUX_CHCFGn_ADDR(x, n) (REGS_DMAMUX_BASE(x) + 0x0U + (0x1U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_DMAMUX_CHCFGn(x, n) (*(__IO hw_dmamux_chcfgn_t *) HW_DMAMUX_CHCFGn_ADDR(x, n))
-#define HW_DMAMUX_CHCFGn_RD(x, n) (HW_DMAMUX_CHCFGn(x, n).U)
-#define HW_DMAMUX_CHCFGn_WR(x, n, v) (HW_DMAMUX_CHCFGn(x, n).U = (v))
-#define HW_DMAMUX_CHCFGn_SET(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) | (v)))
-#define HW_DMAMUX_CHCFGn_CLR(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) & ~(v)))
-#define HW_DMAMUX_CHCFGn_TOG(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual DMAMUX_CHCFGn bitfields
- */
-
-/*!
- * @name Register DMAMUX_CHCFGn, field SOURCE[5:0] (RW)
- *
- * Specifies which DMA source, if any, is routed to a particular DMA channel.
- * See your device's chip configuration details for information about the
- * peripherals and their slot numbers.
- */
-//@{
-#define BP_DMAMUX_CHCFGn_SOURCE (0U) //!< Bit position for DMAMUX_CHCFGn_SOURCE.
-#define BM_DMAMUX_CHCFGn_SOURCE (0x3FU) //!< Bit mask for DMAMUX_CHCFGn_SOURCE.
-#define BS_DMAMUX_CHCFGn_SOURCE (6U) //!< Bit field size in bits for DMAMUX_CHCFGn_SOURCE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMAMUX_CHCFGn_SOURCE field.
-#define BR_DMAMUX_CHCFGn_SOURCE(x, n) (HW_DMAMUX_CHCFGn(x, n).B.SOURCE)
-#endif
-
-//! @brief Format value for bitfield DMAMUX_CHCFGn_SOURCE.
-#define BF_DMAMUX_CHCFGn_SOURCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMAMUX_CHCFGn_SOURCE), uint8_t) & BM_DMAMUX_CHCFGn_SOURCE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SOURCE field to a new value.
-#define BW_DMAMUX_CHCFGn_SOURCE(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, (HW_DMAMUX_CHCFGn_RD(x, n) & ~BM_DMAMUX_CHCFGn_SOURCE) | BF_DMAMUX_CHCFGn_SOURCE(v)))
-#endif
-//@}
-
-/*!
- * @name Register DMAMUX_CHCFGn, field TRIG[6] (RW)
- *
- * Enables the periodic trigger capability for the triggered DMA channel.
- *
- * Values:
- * - 0 - Triggering is disabled. If triggering is disabled and ENBL is set, the
- * DMA Channel will simply route the specified source to the DMA channel.
- * (Normal mode)
- * - 1 - Triggering is enabled. If triggering is enabled and ENBL is set, the
- * DMAMUX is in Periodic Trigger mode.
- */
-//@{
-#define BP_DMAMUX_CHCFGn_TRIG (6U) //!< Bit position for DMAMUX_CHCFGn_TRIG.
-#define BM_DMAMUX_CHCFGn_TRIG (0x40U) //!< Bit mask for DMAMUX_CHCFGn_TRIG.
-#define BS_DMAMUX_CHCFGn_TRIG (1U) //!< Bit field size in bits for DMAMUX_CHCFGn_TRIG.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMAMUX_CHCFGn_TRIG field.
-#define BR_DMAMUX_CHCFGn_TRIG(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG))
-#endif
-
-//! @brief Format value for bitfield DMAMUX_CHCFGn_TRIG.
-#define BF_DMAMUX_CHCFGn_TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMAMUX_CHCFGn_TRIG), uint8_t) & BM_DMAMUX_CHCFGn_TRIG)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TRIG field to a new value.
-#define BW_DMAMUX_CHCFGn_TRIG(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG) = (v))
-#endif
-//@}
-
-/*!
- * @name Register DMAMUX_CHCFGn, field ENBL[7] (RW)
- *
- * Enables the DMA channel.
- *
- * Values:
- * - 0 - DMA channel is disabled. This mode is primarily used during
- * configuration of the DMAMux. The DMA has separate channel enables/disables, which
- * should be used to disable or reconfigure a DMA channel.
- * - 1 - DMA channel is enabled
- */
-//@{
-#define BP_DMAMUX_CHCFGn_ENBL (7U) //!< Bit position for DMAMUX_CHCFGn_ENBL.
-#define BM_DMAMUX_CHCFGn_ENBL (0x80U) //!< Bit mask for DMAMUX_CHCFGn_ENBL.
-#define BS_DMAMUX_CHCFGn_ENBL (1U) //!< Bit field size in bits for DMAMUX_CHCFGn_ENBL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the DMAMUX_CHCFGn_ENBL field.
-#define BR_DMAMUX_CHCFGn_ENBL(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL))
-#endif
-
-//! @brief Format value for bitfield DMAMUX_CHCFGn_ENBL.
-#define BF_DMAMUX_CHCFGn_ENBL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMAMUX_CHCFGn_ENBL), uint8_t) & BM_DMAMUX_CHCFGn_ENBL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ENBL field to a new value.
-#define BW_DMAMUX_CHCFGn_ENBL(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_dmamux_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All DMAMUX module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_dmamux
-{
- __IO hw_dmamux_chcfgn_t CHCFGn[16]; //!< [0x0] Channel Configuration register
-} hw_dmamux_t;
-#pragma pack()
-
-//! @brief Macro to access all DMAMUX registers.
-//! @param x DMAMUX instance number.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_DMAMUX(0)</code>.
-#define HW_DMAMUX(x) (*(hw_dmamux_t *) REGS_DMAMUX_BASE(x))
-#endif
-
-#endif // __HW_DMAMUX_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_enet.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,8441 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_ENET_REGISTERS_H__
-#define __HW_ENET_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 ENET
- *
- * Ethernet MAC-NET Core
- *
- * Registers defined in this header file:
- * - HW_ENET_EIR - Interrupt Event Register
- * - HW_ENET_EIMR - Interrupt Mask Register
- * - HW_ENET_RDAR - Receive Descriptor Active Register
- * - HW_ENET_TDAR - Transmit Descriptor Active Register
- * - HW_ENET_ECR - Ethernet Control Register
- * - HW_ENET_MMFR - MII Management Frame Register
- * - HW_ENET_MSCR - MII Speed Control Register
- * - HW_ENET_MIBC - MIB Control Register
- * - HW_ENET_RCR - Receive Control Register
- * - HW_ENET_TCR - Transmit Control Register
- * - HW_ENET_PALR - Physical Address Lower Register
- * - HW_ENET_PAUR - Physical Address Upper Register
- * - HW_ENET_OPD - Opcode/Pause Duration Register
- * - HW_ENET_IAUR - Descriptor Individual Upper Address Register
- * - HW_ENET_IALR - Descriptor Individual Lower Address Register
- * - HW_ENET_GAUR - Descriptor Group Upper Address Register
- * - HW_ENET_GALR - Descriptor Group Lower Address Register
- * - HW_ENET_TFWR - Transmit FIFO Watermark Register
- * - HW_ENET_RDSR - Receive Descriptor Ring Start Register
- * - HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
- * - HW_ENET_MRBR - Maximum Receive Buffer Size Register
- * - HW_ENET_RSFL - Receive FIFO Section Full Threshold
- * - HW_ENET_RSEM - Receive FIFO Section Empty Threshold
- * - HW_ENET_RAEM - Receive FIFO Almost Empty Threshold
- * - HW_ENET_RAFL - Receive FIFO Almost Full Threshold
- * - HW_ENET_TSEM - Transmit FIFO Section Empty Threshold
- * - HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold
- * - HW_ENET_TAFL - Transmit FIFO Almost Full Threshold
- * - HW_ENET_TIPG - Transmit Inter-Packet Gap
- * - HW_ENET_FTRL - Frame Truncation Length
- * - HW_ENET_TACC - Transmit Accelerator Function Configuration
- * - HW_ENET_RACC - Receive Accelerator Function Configuration
- * - HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
- * - HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
- * - HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
- * - HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
- * - HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
- * - HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
- * - HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
- * - HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
- * - HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register
- * - HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
- * - HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
- * - HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
- * - HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
- * - HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
- * - HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
- * - HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
- * - HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register
- * - HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
- * - HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
- * - HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
- * - HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
- * - HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
- * - HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
- * - HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
- * - HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
- * - HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
- * - HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
- * - HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
- * - HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
- * - HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
- * - HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
- * - HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
- * - HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
- * - HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
- * - HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
- * - HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
- * - HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
- * - HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
- * - HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
- * - HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
- * - HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
- * - HW_ENET_RMON_R_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
- * - HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register
- * - HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
- * - HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
- * - HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
- * - HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
- * - HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
- * - HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
- * - HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
- * - HW_ENET_ATCR - Adjustable Timer Control Register
- * - HW_ENET_ATVR - Timer Value Register
- * - HW_ENET_ATOFF - Timer Offset Register
- * - HW_ENET_ATPER - Timer Period Register
- * - HW_ENET_ATCOR - Timer Correction Register
- * - HW_ENET_ATINC - Time-Stamping Clock Period Register
- * - HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame
- * - HW_ENET_TGSR - Timer Global Status Register
- * - HW_ENET_TCSRn - Timer Control Status Register
- * - HW_ENET_TCCRn - Timer Compare Capture Register
- *
- * - hw_enet_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_ENET_BASE
-#define HW_ENET_INSTANCE_COUNT (1U) //!< Number of instances of the ENET module.
-#define HW_ENET0 (0U) //!< Instance number for ENET.
-#define REGS_ENET0_BASE (0x400C0000U) //!< Base address for ENET.
-
-//! @brief Table of base addresses for ENET instances.
-static const uint32_t __g_regs_ENET_base_addresses[] = {
- REGS_ENET0_BASE,
- };
-
-//! @brief Get the base address of ENET by instance number.
-//! @param x ENET instance number, from 0 through 0.
-#define REGS_ENET_BASE(x) (__g_regs_ENET_base_addresses[(x)])
-
-//! @brief Get the instance number given a base address.
-//! @param b Base address for an instance of ENET.
-#define REGS_ENET_INSTANCE(b) ((b) == REGS_ENET0_BASE ? HW_ENET0 : 0)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_EIR - Interrupt Event Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_EIR - Interrupt Event Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * When an event occurs that sets a bit in EIR, an interrupt occurs if the
- * corresponding bit in the interrupt mask register (EIMR) is also set. Writing a 1 to
- * an EIR bit clears it; writing 0 has no effect. This register is cleared upon
- * hardware reset. TxBD[INT] and RxBD[INT] must be set to 1 to allow setting the
- * corresponding EIR register flags in enhanced mode, ENET_ECR[EN1588] = 1.
- * Legacy mode does not require these flags to be enabled.
- */
-typedef union _hw_enet_eir
-{
- uint32_t U;
- struct _hw_enet_eir_bitfields
- {
- uint32_t RESERVED0 : 15; //!< [14:0]
- uint32_t TS_TIMER : 1; //!< [15] Timestamp Timer
- uint32_t TS_AVAIL : 1; //!< [16] Transmit Timestamp Available
- uint32_t WAKEUP : 1; //!< [17] Node Wakeup Request Indication
- uint32_t PLR : 1; //!< [18] Payload Receive Error
- uint32_t UN : 1; //!< [19] Transmit FIFO Underrun
- uint32_t RL : 1; //!< [20] Collision Retry Limit
- uint32_t LC : 1; //!< [21] Late Collision
- uint32_t EBERR : 1; //!< [22] Ethernet Bus Error
- uint32_t MII : 1; //!< [23] MII Interrupt.
- uint32_t RXB : 1; //!< [24] Receive Buffer Interrupt
- uint32_t RXF : 1; //!< [25] Receive Frame Interrupt
- uint32_t TXB : 1; //!< [26] Transmit Buffer Interrupt
- uint32_t TXF : 1; //!< [27] Transmit Frame Interrupt
- uint32_t GRA : 1; //!< [28] Graceful Stop Complete
- uint32_t BABT : 1; //!< [29] Babbling Transmit Error
- uint32_t BABR : 1; //!< [30] Babbling Receive Error
- uint32_t RESERVED1 : 1; //!< [31]
- } B;
-} hw_enet_eir_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_EIR register
- */
-//@{
-#define HW_ENET_EIR_ADDR(x) (REGS_ENET_BASE(x) + 0x4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_EIR(x) (*(__IO hw_enet_eir_t *) HW_ENET_EIR_ADDR(x))
-#define HW_ENET_EIR_RD(x) (HW_ENET_EIR(x).U)
-#define HW_ENET_EIR_WR(x, v) (HW_ENET_EIR(x).U = (v))
-#define HW_ENET_EIR_SET(x, v) (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) | (v)))
-#define HW_ENET_EIR_CLR(x, v) (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) & ~(v)))
-#define HW_ENET_EIR_TOG(x, v) (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_EIR bitfields
- */
-
-/*!
- * @name Register ENET_EIR, field TS_TIMER[15] (W1C)
- *
- * The adjustable timer reached the period event. A period event interrupt can
- * be generated if ATCR[PEREN] is set and the timer wraps according to the
- * periodic setting in the ATPER register. Set the timer period value before setting
- * ATCR[PEREN].
- */
-//@{
-#define BP_ENET_EIR_TS_TIMER (15U) //!< Bit position for ENET_EIR_TS_TIMER.
-#define BM_ENET_EIR_TS_TIMER (0x00008000U) //!< Bit mask for ENET_EIR_TS_TIMER.
-#define BS_ENET_EIR_TS_TIMER (1U) //!< Bit field size in bits for ENET_EIR_TS_TIMER.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIR_TS_TIMER field.
-#define BR_ENET_EIR_TS_TIMER(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_TIMER))
-#endif
-
-//! @brief Format value for bitfield ENET_EIR_TS_TIMER.
-#define BF_ENET_EIR_TS_TIMER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_TS_TIMER), uint32_t) & BM_ENET_EIR_TS_TIMER)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TS_TIMER field to a new value.
-#define BW_ENET_EIR_TS_TIMER(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_TIMER) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIR, field TS_AVAIL[16] (W1C)
- *
- * Indicates that the timestamp of the last transmitted timing frame is
- * available in the ATSTMP register.
- */
-//@{
-#define BP_ENET_EIR_TS_AVAIL (16U) //!< Bit position for ENET_EIR_TS_AVAIL.
-#define BM_ENET_EIR_TS_AVAIL (0x00010000U) //!< Bit mask for ENET_EIR_TS_AVAIL.
-#define BS_ENET_EIR_TS_AVAIL (1U) //!< Bit field size in bits for ENET_EIR_TS_AVAIL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIR_TS_AVAIL field.
-#define BR_ENET_EIR_TS_AVAIL(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_AVAIL))
-#endif
-
-//! @brief Format value for bitfield ENET_EIR_TS_AVAIL.
-#define BF_ENET_EIR_TS_AVAIL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_TS_AVAIL), uint32_t) & BM_ENET_EIR_TS_AVAIL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TS_AVAIL field to a new value.
-#define BW_ENET_EIR_TS_AVAIL(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_AVAIL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIR, field WAKEUP[17] (W1C)
- *
- * Read-only status bit to indicate that a magic packet has been detected. Will
- * act only if ECR[MAGICEN] is set.
- */
-//@{
-#define BP_ENET_EIR_WAKEUP (17U) //!< Bit position for ENET_EIR_WAKEUP.
-#define BM_ENET_EIR_WAKEUP (0x00020000U) //!< Bit mask for ENET_EIR_WAKEUP.
-#define BS_ENET_EIR_WAKEUP (1U) //!< Bit field size in bits for ENET_EIR_WAKEUP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIR_WAKEUP field.
-#define BR_ENET_EIR_WAKEUP(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_WAKEUP))
-#endif
-
-//! @brief Format value for bitfield ENET_EIR_WAKEUP.
-#define BF_ENET_EIR_WAKEUP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_WAKEUP), uint32_t) & BM_ENET_EIR_WAKEUP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WAKEUP field to a new value.
-#define BW_ENET_EIR_WAKEUP(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_WAKEUP) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIR, field PLR[18] (W1C)
- *
- * Indicates a frame was received with a payload length error. See Frame
- * Length/Type Verification: Payload Length Check for more information.
- */
-//@{
-#define BP_ENET_EIR_PLR (18U) //!< Bit position for ENET_EIR_PLR.
-#define BM_ENET_EIR_PLR (0x00040000U) //!< Bit mask for ENET_EIR_PLR.
-#define BS_ENET_EIR_PLR (1U) //!< Bit field size in bits for ENET_EIR_PLR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIR_PLR field.
-#define BR_ENET_EIR_PLR(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_PLR))
-#endif
-
-//! @brief Format value for bitfield ENET_EIR_PLR.
-#define BF_ENET_EIR_PLR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_PLR), uint32_t) & BM_ENET_EIR_PLR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PLR field to a new value.
-#define BW_ENET_EIR_PLR(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_PLR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIR, field UN[19] (W1C)
- *
- * Indicates the transmit FIFO became empty before the complete frame was
- * transmitted. A bad CRC is appended to the frame fragment and the remainder of the
- * frame is discarded.
- */
-//@{
-#define BP_ENET_EIR_UN (19U) //!< Bit position for ENET_EIR_UN.
-#define BM_ENET_EIR_UN (0x00080000U) //!< Bit mask for ENET_EIR_UN.
-#define BS_ENET_EIR_UN (1U) //!< Bit field size in bits for ENET_EIR_UN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIR_UN field.
-#define BR_ENET_EIR_UN(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_UN))
-#endif
-
-//! @brief Format value for bitfield ENET_EIR_UN.
-#define BF_ENET_EIR_UN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_UN), uint32_t) & BM_ENET_EIR_UN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the UN field to a new value.
-#define BW_ENET_EIR_UN(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_UN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIR, field RL[20] (W1C)
- *
- * Indicates a collision occurred on each of 16 successive attempts to transmit
- * the frame. The frame is discarded without being transmitted and transmission
- * of the next frame commences. This error can only occur in half-duplex mode.
- */
-//@{
-#define BP_ENET_EIR_RL (20U) //!< Bit position for ENET_EIR_RL.
-#define BM_ENET_EIR_RL (0x00100000U) //!< Bit mask for ENET_EIR_RL.
-#define BS_ENET_EIR_RL (1U) //!< Bit field size in bits for ENET_EIR_RL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIR_RL field.
-#define BR_ENET_EIR_RL(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RL))
-#endif
-
-//! @brief Format value for bitfield ENET_EIR_RL.
-#define BF_ENET_EIR_RL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_RL), uint32_t) & BM_ENET_EIR_RL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RL field to a new value.
-#define BW_ENET_EIR_RL(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIR, field LC[21] (W1C)
- *
- * Indicates a collision occurred beyond the collision window (slot time) in
- * half-duplex mode. The frame truncates with a bad CRC and the remainder of the
- * frame is discarded.
- */
-//@{
-#define BP_ENET_EIR_LC (21U) //!< Bit position for ENET_EIR_LC.
-#define BM_ENET_EIR_LC (0x00200000U) //!< Bit mask for ENET_EIR_LC.
-#define BS_ENET_EIR_LC (1U) //!< Bit field size in bits for ENET_EIR_LC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIR_LC field.
-#define BR_ENET_EIR_LC(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_LC))
-#endif
-
-//! @brief Format value for bitfield ENET_EIR_LC.
-#define BF_ENET_EIR_LC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_LC), uint32_t) & BM_ENET_EIR_LC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LC field to a new value.
-#define BW_ENET_EIR_LC(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_LC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIR, field EBERR[22] (W1C)
- *
- * Indicates a system bus error occurred when a uDMA transaction is underway.
- * When this bit is set, ECR[ETHEREN] is cleared, halting frame processing by the
- * MAC. When this occurs, software must ensure proper actions, possibly resetting
- * the system, to resume normal operation.
- */
-//@{
-#define BP_ENET_EIR_EBERR (22U) //!< Bit position for ENET_EIR_EBERR.
-#define BM_ENET_EIR_EBERR (0x00400000U) //!< Bit mask for ENET_EIR_EBERR.
-#define BS_ENET_EIR_EBERR (1U) //!< Bit field size in bits for ENET_EIR_EBERR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIR_EBERR field.
-#define BR_ENET_EIR_EBERR(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_EBERR))
-#endif
-
-//! @brief Format value for bitfield ENET_EIR_EBERR.
-#define BF_ENET_EIR_EBERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_EBERR), uint32_t) & BM_ENET_EIR_EBERR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EBERR field to a new value.
-#define BW_ENET_EIR_EBERR(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_EBERR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIR, field MII[23] (W1C)
- *
- * Indicates that the MII has completed the data transfer requested.
- */
-//@{
-#define BP_ENET_EIR_MII (23U) //!< Bit position for ENET_EIR_MII.
-#define BM_ENET_EIR_MII (0x00800000U) //!< Bit mask for ENET_EIR_MII.
-#define BS_ENET_EIR_MII (1U) //!< Bit field size in bits for ENET_EIR_MII.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIR_MII field.
-#define BR_ENET_EIR_MII(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_MII))
-#endif
-
-//! @brief Format value for bitfield ENET_EIR_MII.
-#define BF_ENET_EIR_MII(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_MII), uint32_t) & BM_ENET_EIR_MII)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MII field to a new value.
-#define BW_ENET_EIR_MII(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_MII) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIR, field RXB[24] (W1C)
- *
- * Indicates a receive buffer descriptor is not the last in the frame has been
- * updated.
- */
-//@{
-#define BP_ENET_EIR_RXB (24U) //!< Bit position for ENET_EIR_RXB.
-#define BM_ENET_EIR_RXB (0x01000000U) //!< Bit mask for ENET_EIR_RXB.
-#define BS_ENET_EIR_RXB (1U) //!< Bit field size in bits for ENET_EIR_RXB.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIR_RXB field.
-#define BR_ENET_EIR_RXB(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXB))
-#endif
-
-//! @brief Format value for bitfield ENET_EIR_RXB.
-#define BF_ENET_EIR_RXB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_RXB), uint32_t) & BM_ENET_EIR_RXB)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RXB field to a new value.
-#define BW_ENET_EIR_RXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXB) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIR, field RXF[25] (W1C)
- *
- * Indicates a frame has been received and the last corresponding buffer
- * descriptor has been updated.
- */
-//@{
-#define BP_ENET_EIR_RXF (25U) //!< Bit position for ENET_EIR_RXF.
-#define BM_ENET_EIR_RXF (0x02000000U) //!< Bit mask for ENET_EIR_RXF.
-#define BS_ENET_EIR_RXF (1U) //!< Bit field size in bits for ENET_EIR_RXF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIR_RXF field.
-#define BR_ENET_EIR_RXF(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXF))
-#endif
-
-//! @brief Format value for bitfield ENET_EIR_RXF.
-#define BF_ENET_EIR_RXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_RXF), uint32_t) & BM_ENET_EIR_RXF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RXF field to a new value.
-#define BW_ENET_EIR_RXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIR, field TXB[26] (W1C)
- *
- * Indicates a transmit buffer descriptor has been updated.
- */
-//@{
-#define BP_ENET_EIR_TXB (26U) //!< Bit position for ENET_EIR_TXB.
-#define BM_ENET_EIR_TXB (0x04000000U) //!< Bit mask for ENET_EIR_TXB.
-#define BS_ENET_EIR_TXB (1U) //!< Bit field size in bits for ENET_EIR_TXB.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIR_TXB field.
-#define BR_ENET_EIR_TXB(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXB))
-#endif
-
-//! @brief Format value for bitfield ENET_EIR_TXB.
-#define BF_ENET_EIR_TXB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_TXB), uint32_t) & BM_ENET_EIR_TXB)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TXB field to a new value.
-#define BW_ENET_EIR_TXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXB) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIR, field TXF[27] (W1C)
- *
- * Indicates a frame has been transmitted and the last corresponding buffer
- * descriptor has been updated.
- */
-//@{
-#define BP_ENET_EIR_TXF (27U) //!< Bit position for ENET_EIR_TXF.
-#define BM_ENET_EIR_TXF (0x08000000U) //!< Bit mask for ENET_EIR_TXF.
-#define BS_ENET_EIR_TXF (1U) //!< Bit field size in bits for ENET_EIR_TXF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIR_TXF field.
-#define BR_ENET_EIR_TXF(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXF))
-#endif
-
-//! @brief Format value for bitfield ENET_EIR_TXF.
-#define BF_ENET_EIR_TXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_TXF), uint32_t) & BM_ENET_EIR_TXF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TXF field to a new value.
-#define BW_ENET_EIR_TXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIR, field GRA[28] (W1C)
- *
- * This interrupt is asserted after the transmitter is put into a pause state
- * after completion of the frame currently being transmitted. See Graceful Transmit
- * Stop (GTS) for conditions that lead to graceful stop. The GRA interrupt is
- * asserted only when the TX transitions into the stopped state. If this bit is
- * cleared by writing 1 and the TX is still stopped, the bit is not set again.
- */
-//@{
-#define BP_ENET_EIR_GRA (28U) //!< Bit position for ENET_EIR_GRA.
-#define BM_ENET_EIR_GRA (0x10000000U) //!< Bit mask for ENET_EIR_GRA.
-#define BS_ENET_EIR_GRA (1U) //!< Bit field size in bits for ENET_EIR_GRA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIR_GRA field.
-#define BR_ENET_EIR_GRA(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_GRA))
-#endif
-
-//! @brief Format value for bitfield ENET_EIR_GRA.
-#define BF_ENET_EIR_GRA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_GRA), uint32_t) & BM_ENET_EIR_GRA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the GRA field to a new value.
-#define BW_ENET_EIR_GRA(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_GRA) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIR, field BABT[29] (W1C)
- *
- * Indicates the transmitted frame length exceeds RCR[MAX_FL] bytes. Usually
- * this condition is caused when a frame that is too long is placed into the
- * transmit data buffer(s). Truncation does not occur.
- */
-//@{
-#define BP_ENET_EIR_BABT (29U) //!< Bit position for ENET_EIR_BABT.
-#define BM_ENET_EIR_BABT (0x20000000U) //!< Bit mask for ENET_EIR_BABT.
-#define BS_ENET_EIR_BABT (1U) //!< Bit field size in bits for ENET_EIR_BABT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIR_BABT field.
-#define BR_ENET_EIR_BABT(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABT))
-#endif
-
-//! @brief Format value for bitfield ENET_EIR_BABT.
-#define BF_ENET_EIR_BABT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_BABT), uint32_t) & BM_ENET_EIR_BABT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BABT field to a new value.
-#define BW_ENET_EIR_BABT(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIR, field BABR[30] (W1C)
- *
- * Indicates a frame was received with length in excess of RCR[MAX_FL] bytes.
- */
-//@{
-#define BP_ENET_EIR_BABR (30U) //!< Bit position for ENET_EIR_BABR.
-#define BM_ENET_EIR_BABR (0x40000000U) //!< Bit mask for ENET_EIR_BABR.
-#define BS_ENET_EIR_BABR (1U) //!< Bit field size in bits for ENET_EIR_BABR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIR_BABR field.
-#define BR_ENET_EIR_BABR(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABR))
-#endif
-
-//! @brief Format value for bitfield ENET_EIR_BABR.
-#define BF_ENET_EIR_BABR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_BABR), uint32_t) & BM_ENET_EIR_BABR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BABR field to a new value.
-#define BW_ENET_EIR_BABR(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABR) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_EIMR - Interrupt Mask Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_EIMR - Interrupt Mask Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * EIMR controls which interrupt events are allowed to generate actual
- * interrupts. A hardware reset clears this register. If the corresponding bits in the EIR
- * and EIMR registers are set, an interrupt is generated. The interrupt signal
- * remains asserted until a 1 is written to the EIR field (write 1 to clear) or a
- * 0 is written to the EIMR field.
- */
-typedef union _hw_enet_eimr
-{
- uint32_t U;
- struct _hw_enet_eimr_bitfields
- {
- uint32_t RESERVED0 : 15; //!< [14:0]
- uint32_t TS_TIMER : 1; //!< [15] TS_TIMER Interrupt Mask
- uint32_t TS_AVAIL : 1; //!< [16] TS_AVAIL Interrupt Mask
- uint32_t WAKEUP : 1; //!< [17] WAKEUP Interrupt Mask
- uint32_t PLR : 1; //!< [18] PLR Interrupt Mask
- uint32_t UN : 1; //!< [19] UN Interrupt Mask
- uint32_t RL : 1; //!< [20] RL Interrupt Mask
- uint32_t LC : 1; //!< [21] LC Interrupt Mask
- uint32_t EBERR : 1; //!< [22] EBERR Interrupt Mask
- uint32_t MII : 1; //!< [23] MII Interrupt Mask
- uint32_t RXB : 1; //!< [24] RXB Interrupt Mask
- uint32_t RXF : 1; //!< [25] RXF Interrupt Mask
- uint32_t TXB : 1; //!< [26] TXB Interrupt Mask
- uint32_t TXF : 1; //!< [27] TXF Interrupt Mask
- uint32_t GRA : 1; //!< [28] GRA Interrupt Mask
- uint32_t BABT : 1; //!< [29] BABT Interrupt Mask
- uint32_t BABR : 1; //!< [30] BABR Interrupt Mask
- uint32_t RESERVED1 : 1; //!< [31]
- } B;
-} hw_enet_eimr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_EIMR register
- */
-//@{
-#define HW_ENET_EIMR_ADDR(x) (REGS_ENET_BASE(x) + 0x8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_EIMR(x) (*(__IO hw_enet_eimr_t *) HW_ENET_EIMR_ADDR(x))
-#define HW_ENET_EIMR_RD(x) (HW_ENET_EIMR(x).U)
-#define HW_ENET_EIMR_WR(x, v) (HW_ENET_EIMR(x).U = (v))
-#define HW_ENET_EIMR_SET(x, v) (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) | (v)))
-#define HW_ENET_EIMR_CLR(x, v) (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) & ~(v)))
-#define HW_ENET_EIMR_TOG(x, v) (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_EIMR bitfields
- */
-
-/*!
- * @name Register ENET_EIMR, field TS_TIMER[15] (RW)
- *
- * Corresponds to interrupt source EIR[TS_TIMER] register and determines whether
- * an interrupt condition can generate an interrupt. At every module clock, the
- * EIR samples the signal generated by the interrupting source. The corresponding
- * EIR TS_TIMER field reflects the state of the interrupt signal even if the
- * corresponding EIMR field is cleared.
- */
-//@{
-#define BP_ENET_EIMR_TS_TIMER (15U) //!< Bit position for ENET_EIMR_TS_TIMER.
-#define BM_ENET_EIMR_TS_TIMER (0x00008000U) //!< Bit mask for ENET_EIMR_TS_TIMER.
-#define BS_ENET_EIMR_TS_TIMER (1U) //!< Bit field size in bits for ENET_EIMR_TS_TIMER.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIMR_TS_TIMER field.
-#define BR_ENET_EIMR_TS_TIMER(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_TIMER))
-#endif
-
-//! @brief Format value for bitfield ENET_EIMR_TS_TIMER.
-#define BF_ENET_EIMR_TS_TIMER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_TS_TIMER), uint32_t) & BM_ENET_EIMR_TS_TIMER)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TS_TIMER field to a new value.
-#define BW_ENET_EIMR_TS_TIMER(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_TIMER) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIMR, field TS_AVAIL[16] (RW)
- *
- * Corresponds to interrupt source EIR[TS_AVAIL] register and determines whether
- * an interrupt condition can generate an interrupt. At every module clock, the
- * EIR samples the signal generated by the interrupting source. The corresponding
- * EIR TS_AVAIL field reflects the state of the interrupt signal even if the
- * corresponding EIMR field is cleared.
- */
-//@{
-#define BP_ENET_EIMR_TS_AVAIL (16U) //!< Bit position for ENET_EIMR_TS_AVAIL.
-#define BM_ENET_EIMR_TS_AVAIL (0x00010000U) //!< Bit mask for ENET_EIMR_TS_AVAIL.
-#define BS_ENET_EIMR_TS_AVAIL (1U) //!< Bit field size in bits for ENET_EIMR_TS_AVAIL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIMR_TS_AVAIL field.
-#define BR_ENET_EIMR_TS_AVAIL(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_AVAIL))
-#endif
-
-//! @brief Format value for bitfield ENET_EIMR_TS_AVAIL.
-#define BF_ENET_EIMR_TS_AVAIL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_TS_AVAIL), uint32_t) & BM_ENET_EIMR_TS_AVAIL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TS_AVAIL field to a new value.
-#define BW_ENET_EIMR_TS_AVAIL(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_AVAIL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIMR, field WAKEUP[17] (RW)
- *
- * Corresponds to interrupt source EIR[WAKEUP] register and determines whether
- * an interrupt condition can generate an interrupt. At every module clock, the
- * EIR samples the signal generated by the interrupting source. The corresponding
- * EIR WAKEUP field reflects the state of the interrupt signal even if the
- * corresponding EIMR field is cleared.
- */
-//@{
-#define BP_ENET_EIMR_WAKEUP (17U) //!< Bit position for ENET_EIMR_WAKEUP.
-#define BM_ENET_EIMR_WAKEUP (0x00020000U) //!< Bit mask for ENET_EIMR_WAKEUP.
-#define BS_ENET_EIMR_WAKEUP (1U) //!< Bit field size in bits for ENET_EIMR_WAKEUP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIMR_WAKEUP field.
-#define BR_ENET_EIMR_WAKEUP(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_WAKEUP))
-#endif
-
-//! @brief Format value for bitfield ENET_EIMR_WAKEUP.
-#define BF_ENET_EIMR_WAKEUP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_WAKEUP), uint32_t) & BM_ENET_EIMR_WAKEUP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WAKEUP field to a new value.
-#define BW_ENET_EIMR_WAKEUP(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_WAKEUP) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIMR, field PLR[18] (RW)
- *
- * Corresponds to interrupt source EIR[PLR] and determines whether an interrupt
- * condition can generate an interrupt. At every module clock, the EIR samples
- * the signal generated by the interrupting source. The corresponding EIR PLR field
- * reflects the state of the interrupt signal even if the corresponding EIMR
- * field is cleared.
- */
-//@{
-#define BP_ENET_EIMR_PLR (18U) //!< Bit position for ENET_EIMR_PLR.
-#define BM_ENET_EIMR_PLR (0x00040000U) //!< Bit mask for ENET_EIMR_PLR.
-#define BS_ENET_EIMR_PLR (1U) //!< Bit field size in bits for ENET_EIMR_PLR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIMR_PLR field.
-#define BR_ENET_EIMR_PLR(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_PLR))
-#endif
-
-//! @brief Format value for bitfield ENET_EIMR_PLR.
-#define BF_ENET_EIMR_PLR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_PLR), uint32_t) & BM_ENET_EIMR_PLR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PLR field to a new value.
-#define BW_ENET_EIMR_PLR(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_PLR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIMR, field UN[19] (RW)
- *
- * Corresponds to interrupt source EIR[UN] and determines whether an interrupt
- * condition can generate an interrupt. At every module clock, the EIR samples the
- * signal generated by the interrupting source. The corresponding EIR UN field
- * reflects the state of the interrupt signal even if the corresponding EIMR field
- * is cleared.
- */
-//@{
-#define BP_ENET_EIMR_UN (19U) //!< Bit position for ENET_EIMR_UN.
-#define BM_ENET_EIMR_UN (0x00080000U) //!< Bit mask for ENET_EIMR_UN.
-#define BS_ENET_EIMR_UN (1U) //!< Bit field size in bits for ENET_EIMR_UN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIMR_UN field.
-#define BR_ENET_EIMR_UN(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_UN))
-#endif
-
-//! @brief Format value for bitfield ENET_EIMR_UN.
-#define BF_ENET_EIMR_UN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_UN), uint32_t) & BM_ENET_EIMR_UN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the UN field to a new value.
-#define BW_ENET_EIMR_UN(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_UN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIMR, field RL[20] (RW)
- *
- * Corresponds to interrupt source EIR[RL] and determines whether an interrupt
- * condition can generate an interrupt. At every module clock, the EIR samples the
- * signal generated by the interrupting source. The corresponding EIR RL field
- * reflects the state of the interrupt signal even if the corresponding EIMR field
- * is cleared.
- */
-//@{
-#define BP_ENET_EIMR_RL (20U) //!< Bit position for ENET_EIMR_RL.
-#define BM_ENET_EIMR_RL (0x00100000U) //!< Bit mask for ENET_EIMR_RL.
-#define BS_ENET_EIMR_RL (1U) //!< Bit field size in bits for ENET_EIMR_RL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIMR_RL field.
-#define BR_ENET_EIMR_RL(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RL))
-#endif
-
-//! @brief Format value for bitfield ENET_EIMR_RL.
-#define BF_ENET_EIMR_RL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_RL), uint32_t) & BM_ENET_EIMR_RL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RL field to a new value.
-#define BW_ENET_EIMR_RL(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIMR, field LC[21] (RW)
- *
- * Corresponds to interrupt source EIR[LC] and determines whether an interrupt
- * condition can generate an interrupt. At every module clock, the EIR samples the
- * signal generated by the interrupting source. The corresponding EIR LC field
- * reflects the state of the interrupt signal even if the corresponding EIMR field
- * is cleared.
- */
-//@{
-#define BP_ENET_EIMR_LC (21U) //!< Bit position for ENET_EIMR_LC.
-#define BM_ENET_EIMR_LC (0x00200000U) //!< Bit mask for ENET_EIMR_LC.
-#define BS_ENET_EIMR_LC (1U) //!< Bit field size in bits for ENET_EIMR_LC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIMR_LC field.
-#define BR_ENET_EIMR_LC(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_LC))
-#endif
-
-//! @brief Format value for bitfield ENET_EIMR_LC.
-#define BF_ENET_EIMR_LC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_LC), uint32_t) & BM_ENET_EIMR_LC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LC field to a new value.
-#define BW_ENET_EIMR_LC(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_LC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIMR, field EBERR[22] (RW)
- *
- * Corresponds to interrupt source EIR[EBERR] and determines whether an
- * interrupt condition can generate an interrupt. At every module clock, the EIR samples
- * the signal generated by the interrupting source. The corresponding EIR EBERR
- * field reflects the state of the interrupt signal even if the corresponding EIMR
- * field is cleared.
- */
-//@{
-#define BP_ENET_EIMR_EBERR (22U) //!< Bit position for ENET_EIMR_EBERR.
-#define BM_ENET_EIMR_EBERR (0x00400000U) //!< Bit mask for ENET_EIMR_EBERR.
-#define BS_ENET_EIMR_EBERR (1U) //!< Bit field size in bits for ENET_EIMR_EBERR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIMR_EBERR field.
-#define BR_ENET_EIMR_EBERR(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_EBERR))
-#endif
-
-//! @brief Format value for bitfield ENET_EIMR_EBERR.
-#define BF_ENET_EIMR_EBERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_EBERR), uint32_t) & BM_ENET_EIMR_EBERR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EBERR field to a new value.
-#define BW_ENET_EIMR_EBERR(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_EBERR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIMR, field MII[23] (RW)
- *
- * Corresponds to interrupt source EIR[MII] and determines whether an interrupt
- * condition can generate an interrupt. At every module clock, the EIR samples
- * the signal generated by the interrupting source. The corresponding EIR MII field
- * reflects the state of the interrupt signal even if the corresponding EIMR
- * field is cleared.
- */
-//@{
-#define BP_ENET_EIMR_MII (23U) //!< Bit position for ENET_EIMR_MII.
-#define BM_ENET_EIMR_MII (0x00800000U) //!< Bit mask for ENET_EIMR_MII.
-#define BS_ENET_EIMR_MII (1U) //!< Bit field size in bits for ENET_EIMR_MII.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIMR_MII field.
-#define BR_ENET_EIMR_MII(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_MII))
-#endif
-
-//! @brief Format value for bitfield ENET_EIMR_MII.
-#define BF_ENET_EIMR_MII(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_MII), uint32_t) & BM_ENET_EIMR_MII)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MII field to a new value.
-#define BW_ENET_EIMR_MII(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_MII) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIMR, field RXB[24] (RW)
- *
- * Corresponds to interrupt source EIR[RXB] and determines whether an interrupt
- * condition can generate an interrupt. At every module clock, the EIR samples
- * the signal generated by the interrupting source. The corresponding EIR RXB field
- * reflects the state of the interrupt signal even if the corresponding EIMR
- * field is cleared.
- */
-//@{
-#define BP_ENET_EIMR_RXB (24U) //!< Bit position for ENET_EIMR_RXB.
-#define BM_ENET_EIMR_RXB (0x01000000U) //!< Bit mask for ENET_EIMR_RXB.
-#define BS_ENET_EIMR_RXB (1U) //!< Bit field size in bits for ENET_EIMR_RXB.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIMR_RXB field.
-#define BR_ENET_EIMR_RXB(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXB))
-#endif
-
-//! @brief Format value for bitfield ENET_EIMR_RXB.
-#define BF_ENET_EIMR_RXB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_RXB), uint32_t) & BM_ENET_EIMR_RXB)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RXB field to a new value.
-#define BW_ENET_EIMR_RXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXB) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIMR, field RXF[25] (RW)
- *
- * Corresponds to interrupt source EIR[RXF] and determines whether an interrupt
- * condition can generate an interrupt. At every module clock, the EIR samples
- * the signal generated by the interrupting source. The corresponding EIR RXF field
- * reflects the state of the interrupt signal even if the corresponding EIMR
- * field is cleared.
- */
-//@{
-#define BP_ENET_EIMR_RXF (25U) //!< Bit position for ENET_EIMR_RXF.
-#define BM_ENET_EIMR_RXF (0x02000000U) //!< Bit mask for ENET_EIMR_RXF.
-#define BS_ENET_EIMR_RXF (1U) //!< Bit field size in bits for ENET_EIMR_RXF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIMR_RXF field.
-#define BR_ENET_EIMR_RXF(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXF))
-#endif
-
-//! @brief Format value for bitfield ENET_EIMR_RXF.
-#define BF_ENET_EIMR_RXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_RXF), uint32_t) & BM_ENET_EIMR_RXF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RXF field to a new value.
-#define BW_ENET_EIMR_RXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIMR, field TXB[26] (RW)
- *
- * Corresponds to interrupt source EIR[TXB] and determines whether an interrupt
- * condition can generate an interrupt. At every module clock, the EIR samples
- * the signal generated by the interrupting source. The corresponding EIR TXF field
- * reflects the state of the interrupt signal even if the corresponding EIMR
- * field is cleared.
- *
- * Values:
- * - 0 - The corresponding interrupt source is masked.
- * - 1 - The corresponding interrupt source is not masked.
- */
-//@{
-#define BP_ENET_EIMR_TXB (26U) //!< Bit position for ENET_EIMR_TXB.
-#define BM_ENET_EIMR_TXB (0x04000000U) //!< Bit mask for ENET_EIMR_TXB.
-#define BS_ENET_EIMR_TXB (1U) //!< Bit field size in bits for ENET_EIMR_TXB.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIMR_TXB field.
-#define BR_ENET_EIMR_TXB(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXB))
-#endif
-
-//! @brief Format value for bitfield ENET_EIMR_TXB.
-#define BF_ENET_EIMR_TXB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_TXB), uint32_t) & BM_ENET_EIMR_TXB)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TXB field to a new value.
-#define BW_ENET_EIMR_TXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXB) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIMR, field TXF[27] (RW)
- *
- * Corresponds to interrupt source EIR[TXF] and determines whether an interrupt
- * condition can generate an interrupt. At every module clock, the EIR samples
- * the signal generated by the interrupting source. The corresponding EIR TXF field
- * reflects the state of the interrupt signal even if the corresponding EIMR
- * field is cleared.
- *
- * Values:
- * - 0 - The corresponding interrupt source is masked.
- * - 1 - The corresponding interrupt source is not masked.
- */
-//@{
-#define BP_ENET_EIMR_TXF (27U) //!< Bit position for ENET_EIMR_TXF.
-#define BM_ENET_EIMR_TXF (0x08000000U) //!< Bit mask for ENET_EIMR_TXF.
-#define BS_ENET_EIMR_TXF (1U) //!< Bit field size in bits for ENET_EIMR_TXF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIMR_TXF field.
-#define BR_ENET_EIMR_TXF(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXF))
-#endif
-
-//! @brief Format value for bitfield ENET_EIMR_TXF.
-#define BF_ENET_EIMR_TXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_TXF), uint32_t) & BM_ENET_EIMR_TXF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TXF field to a new value.
-#define BW_ENET_EIMR_TXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIMR, field GRA[28] (RW)
- *
- * Corresponds to interrupt source EIR[GRA] and determines whether an interrupt
- * condition can generate an interrupt. At every module clock, the EIR samples
- * the signal generated by the interrupting source. The corresponding EIR GRA field
- * reflects the state of the interrupt signal even if the corresponding EIMR
- * field is cleared.
- *
- * Values:
- * - 0 - The corresponding interrupt source is masked.
- * - 1 - The corresponding interrupt source is not masked.
- */
-//@{
-#define BP_ENET_EIMR_GRA (28U) //!< Bit position for ENET_EIMR_GRA.
-#define BM_ENET_EIMR_GRA (0x10000000U) //!< Bit mask for ENET_EIMR_GRA.
-#define BS_ENET_EIMR_GRA (1U) //!< Bit field size in bits for ENET_EIMR_GRA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIMR_GRA field.
-#define BR_ENET_EIMR_GRA(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_GRA))
-#endif
-
-//! @brief Format value for bitfield ENET_EIMR_GRA.
-#define BF_ENET_EIMR_GRA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_GRA), uint32_t) & BM_ENET_EIMR_GRA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the GRA field to a new value.
-#define BW_ENET_EIMR_GRA(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_GRA) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIMR, field BABT[29] (RW)
- *
- * Corresponds to interrupt source EIR[BABT] and determines whether an interrupt
- * condition can generate an interrupt. At every module clock, the EIR samples
- * the signal generated by the interrupting source. The corresponding EIR BABT
- * field reflects the state of the interrupt signal even if the corresponding EIMR
- * field is cleared.
- *
- * Values:
- * - 0 - The corresponding interrupt source is masked.
- * - 1 - The corresponding interrupt source is not masked.
- */
-//@{
-#define BP_ENET_EIMR_BABT (29U) //!< Bit position for ENET_EIMR_BABT.
-#define BM_ENET_EIMR_BABT (0x20000000U) //!< Bit mask for ENET_EIMR_BABT.
-#define BS_ENET_EIMR_BABT (1U) //!< Bit field size in bits for ENET_EIMR_BABT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIMR_BABT field.
-#define BR_ENET_EIMR_BABT(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABT))
-#endif
-
-//! @brief Format value for bitfield ENET_EIMR_BABT.
-#define BF_ENET_EIMR_BABT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_BABT), uint32_t) & BM_ENET_EIMR_BABT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BABT field to a new value.
-#define BW_ENET_EIMR_BABT(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_EIMR, field BABR[30] (RW)
- *
- * Corresponds to interrupt source EIR[BABR] and determines whether an interrupt
- * condition can generate an interrupt. At every module clock, the EIR samples
- * the signal generated by the interrupting source. The corresponding EIR BABR
- * field reflects the state of the interrupt signal even if the corresponding EIMR
- * field is cleared.
- *
- * Values:
- * - 0 - The corresponding interrupt source is masked.
- * - 1 - The corresponding interrupt source is not masked.
- */
-//@{
-#define BP_ENET_EIMR_BABR (30U) //!< Bit position for ENET_EIMR_BABR.
-#define BM_ENET_EIMR_BABR (0x40000000U) //!< Bit mask for ENET_EIMR_BABR.
-#define BS_ENET_EIMR_BABR (1U) //!< Bit field size in bits for ENET_EIMR_BABR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_EIMR_BABR field.
-#define BR_ENET_EIMR_BABR(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABR))
-#endif
-
-//! @brief Format value for bitfield ENET_EIMR_BABR.
-#define BF_ENET_EIMR_BABR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_BABR), uint32_t) & BM_ENET_EIMR_BABR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BABR field to a new value.
-#define BW_ENET_EIMR_BABR(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABR) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RDAR - Receive Descriptor Active Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RDAR - Receive Descriptor Active Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * RDAR is a command register, written by the user, to indicate that the receive
- * descriptor ring has been updated, that is, that the driver produced empty
- * receive buffers with the empty bit set.
- */
-typedef union _hw_enet_rdar
-{
- uint32_t U;
- struct _hw_enet_rdar_bitfields
- {
- uint32_t RESERVED0 : 24; //!< [23:0]
- uint32_t RDAR : 1; //!< [24] Receive Descriptor Active
- uint32_t RESERVED1 : 7; //!< [31:25]
- } B;
-} hw_enet_rdar_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RDAR register
- */
-//@{
-#define HW_ENET_RDAR_ADDR(x) (REGS_ENET_BASE(x) + 0x10U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RDAR(x) (*(__IO hw_enet_rdar_t *) HW_ENET_RDAR_ADDR(x))
-#define HW_ENET_RDAR_RD(x) (HW_ENET_RDAR(x).U)
-#define HW_ENET_RDAR_WR(x, v) (HW_ENET_RDAR(x).U = (v))
-#define HW_ENET_RDAR_SET(x, v) (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) | (v)))
-#define HW_ENET_RDAR_CLR(x, v) (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) & ~(v)))
-#define HW_ENET_RDAR_TOG(x, v) (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RDAR bitfields
- */
-
-/*!
- * @name Register ENET_RDAR, field RDAR[24] (RW)
- *
- * Always set to 1 when this register is written, regardless of the value
- * written. This field is cleared by the MAC device when no additional empty
- * descriptors remain in the receive ring. It is also cleared when ECR[ETHEREN] transitions
- * from set to cleared or when ECR[RESET] is set.
- */
-//@{
-#define BP_ENET_RDAR_RDAR (24U) //!< Bit position for ENET_RDAR_RDAR.
-#define BM_ENET_RDAR_RDAR (0x01000000U) //!< Bit mask for ENET_RDAR_RDAR.
-#define BS_ENET_RDAR_RDAR (1U) //!< Bit field size in bits for ENET_RDAR_RDAR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RDAR_RDAR field.
-#define BR_ENET_RDAR_RDAR(x) (BITBAND_ACCESS32(HW_ENET_RDAR_ADDR(x), BP_ENET_RDAR_RDAR))
-#endif
-
-//! @brief Format value for bitfield ENET_RDAR_RDAR.
-#define BF_ENET_RDAR_RDAR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RDAR_RDAR), uint32_t) & BM_ENET_RDAR_RDAR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RDAR field to a new value.
-#define BW_ENET_RDAR_RDAR(x, v) (BITBAND_ACCESS32(HW_ENET_RDAR_ADDR(x), BP_ENET_RDAR_RDAR) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_TDAR - Transmit Descriptor Active Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_TDAR - Transmit Descriptor Active Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * The TDAR is a command register that the user writes to indicate that the
- * transmit descriptor ring has been updated, that is, that transmit buffers have
- * been produced by the driver with the ready bit set in the buffer descriptor. The
- * TDAR register is cleared at reset, when ECR[ETHEREN] transitions from set to
- * cleared, or when ECR[RESET] is set.
- */
-typedef union _hw_enet_tdar
-{
- uint32_t U;
- struct _hw_enet_tdar_bitfields
- {
- uint32_t RESERVED0 : 24; //!< [23:0]
- uint32_t TDAR : 1; //!< [24] Transmit Descriptor Active
- uint32_t RESERVED1 : 7; //!< [31:25]
- } B;
-} hw_enet_tdar_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_TDAR register
- */
-//@{
-#define HW_ENET_TDAR_ADDR(x) (REGS_ENET_BASE(x) + 0x14U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_TDAR(x) (*(__IO hw_enet_tdar_t *) HW_ENET_TDAR_ADDR(x))
-#define HW_ENET_TDAR_RD(x) (HW_ENET_TDAR(x).U)
-#define HW_ENET_TDAR_WR(x, v) (HW_ENET_TDAR(x).U = (v))
-#define HW_ENET_TDAR_SET(x, v) (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) | (v)))
-#define HW_ENET_TDAR_CLR(x, v) (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) & ~(v)))
-#define HW_ENET_TDAR_TOG(x, v) (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_TDAR bitfields
- */
-
-/*!
- * @name Register ENET_TDAR, field TDAR[24] (RW)
- *
- * Always set to 1 when this register is written, regardless of the value
- * written. This bit is cleared by the MAC device when no additional ready descriptors
- * remain in the transmit ring. Also cleared when ECR[ETHEREN] transitions from
- * set to cleared or when ECR[RESET] is set.
- */
-//@{
-#define BP_ENET_TDAR_TDAR (24U) //!< Bit position for ENET_TDAR_TDAR.
-#define BM_ENET_TDAR_TDAR (0x01000000U) //!< Bit mask for ENET_TDAR_TDAR.
-#define BS_ENET_TDAR_TDAR (1U) //!< Bit field size in bits for ENET_TDAR_TDAR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_TDAR_TDAR field.
-#define BR_ENET_TDAR_TDAR(x) (BITBAND_ACCESS32(HW_ENET_TDAR_ADDR(x), BP_ENET_TDAR_TDAR))
-#endif
-
-//! @brief Format value for bitfield ENET_TDAR_TDAR.
-#define BF_ENET_TDAR_TDAR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TDAR_TDAR), uint32_t) & BM_ENET_TDAR_TDAR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TDAR field to a new value.
-#define BW_ENET_TDAR_TDAR(x, v) (BITBAND_ACCESS32(HW_ENET_TDAR_ADDR(x), BP_ENET_TDAR_TDAR) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_ECR - Ethernet Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_ECR - Ethernet Control Register (RW)
- *
- * Reset value: 0xF0000000U
- *
- * ECR is a read/write user register, though hardware may also alter fields in
- * this register. It controls many of the high level features of the Ethernet MAC,
- * including legacy FEC support through the EN1588 field.
- */
-typedef union _hw_enet_ecr
-{
- uint32_t U;
- struct _hw_enet_ecr_bitfields
- {
- uint32_t RESET : 1; //!< [0] Ethernet MAC Reset
- uint32_t ETHEREN : 1; //!< [1] Ethernet Enable
- uint32_t MAGICEN : 1; //!< [2] Magic Packet Detection Enable
- uint32_t SLEEP : 1; //!< [3] Sleep Mode Enable
- uint32_t EN1588 : 1; //!< [4] EN1588 Enable
- uint32_t RESERVED0 : 1; //!< [5]
- uint32_t DBGEN : 1; //!< [6] Debug Enable
- uint32_t STOPEN : 1; //!< [7] STOPEN Signal Control
- uint32_t DBSWP : 1; //!< [8] Descriptor Byte Swapping Enable
- uint32_t RESERVED1 : 23; //!< [31:9]
- } B;
-} hw_enet_ecr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_ECR register
- */
-//@{
-#define HW_ENET_ECR_ADDR(x) (REGS_ENET_BASE(x) + 0x24U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_ECR(x) (*(__IO hw_enet_ecr_t *) HW_ENET_ECR_ADDR(x))
-#define HW_ENET_ECR_RD(x) (HW_ENET_ECR(x).U)
-#define HW_ENET_ECR_WR(x, v) (HW_ENET_ECR(x).U = (v))
-#define HW_ENET_ECR_SET(x, v) (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) | (v)))
-#define HW_ENET_ECR_CLR(x, v) (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) & ~(v)))
-#define HW_ENET_ECR_TOG(x, v) (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_ECR bitfields
- */
-
-/*!
- * @name Register ENET_ECR, field RESET[0] (RW)
- *
- * When this field is set, it clears the ETHEREN field.
- */
-//@{
-#define BP_ENET_ECR_RESET (0U) //!< Bit position for ENET_ECR_RESET.
-#define BM_ENET_ECR_RESET (0x00000001U) //!< Bit mask for ENET_ECR_RESET.
-#define BS_ENET_ECR_RESET (1U) //!< Bit field size in bits for ENET_ECR_RESET.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_ECR_RESET field.
-#define BR_ENET_ECR_RESET(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_RESET))
-#endif
-
-//! @brief Format value for bitfield ENET_ECR_RESET.
-#define BF_ENET_ECR_RESET(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_RESET), uint32_t) & BM_ENET_ECR_RESET)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RESET field to a new value.
-#define BW_ENET_ECR_RESET(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_RESET) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_ECR, field ETHEREN[1] (RW)
- *
- * Enables/disables the Ethernet MAC. When the MAC is disabled, the buffer
- * descriptors for an aborted transmit frame are not updated. The uDMA, buffer
- * descriptor, and FIFO control logic are reset, including the buffer descriptor and
- * FIFO pointers. Hardware clears this field under the following conditions: RESET
- * is set by software An error condition causes the EBERR field to set. ETHEREN
- * must be set at the very last step during ENET
- * configuration/setup/initialization, only after all other ENET-related registers have been configured. If ETHEREN
- * is cleared to 0 by software then then next time ETHEREN is set, the EIR
- * interrupts must cleared to 0 due to previous pending interrupts.
- *
- * Values:
- * - 0 - Reception immediately stops and transmission stops after a bad CRC is
- * appended to any currently transmitted frame.
- * - 1 - MAC is enabled, and reception and transmission are possible.
- */
-//@{
-#define BP_ENET_ECR_ETHEREN (1U) //!< Bit position for ENET_ECR_ETHEREN.
-#define BM_ENET_ECR_ETHEREN (0x00000002U) //!< Bit mask for ENET_ECR_ETHEREN.
-#define BS_ENET_ECR_ETHEREN (1U) //!< Bit field size in bits for ENET_ECR_ETHEREN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_ECR_ETHEREN field.
-#define BR_ENET_ECR_ETHEREN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_ETHEREN))
-#endif
-
-//! @brief Format value for bitfield ENET_ECR_ETHEREN.
-#define BF_ENET_ECR_ETHEREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_ETHEREN), uint32_t) & BM_ENET_ECR_ETHEREN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ETHEREN field to a new value.
-#define BW_ENET_ECR_ETHEREN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_ETHEREN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_ECR, field MAGICEN[2] (RW)
- *
- * Enables/disables magic packet detection. MAGICEN is relevant only if the
- * SLEEP field is set. If MAGICEN is set, changing the SLEEP field enables/disables
- * sleep mode and magic packet detection.
- *
- * Values:
- * - 0 - Magic detection logic disabled.
- * - 1 - The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame
- * is detected.
- */
-//@{
-#define BP_ENET_ECR_MAGICEN (2U) //!< Bit position for ENET_ECR_MAGICEN.
-#define BM_ENET_ECR_MAGICEN (0x00000004U) //!< Bit mask for ENET_ECR_MAGICEN.
-#define BS_ENET_ECR_MAGICEN (1U) //!< Bit field size in bits for ENET_ECR_MAGICEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_ECR_MAGICEN field.
-#define BR_ENET_ECR_MAGICEN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_MAGICEN))
-#endif
-
-//! @brief Format value for bitfield ENET_ECR_MAGICEN.
-#define BF_ENET_ECR_MAGICEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_MAGICEN), uint32_t) & BM_ENET_ECR_MAGICEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MAGICEN field to a new value.
-#define BW_ENET_ECR_MAGICEN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_MAGICEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_ECR, field SLEEP[3] (RW)
- *
- * Values:
- * - 0 - Normal operating mode.
- * - 1 - Sleep mode.
- */
-//@{
-#define BP_ENET_ECR_SLEEP (3U) //!< Bit position for ENET_ECR_SLEEP.
-#define BM_ENET_ECR_SLEEP (0x00000008U) //!< Bit mask for ENET_ECR_SLEEP.
-#define BS_ENET_ECR_SLEEP (1U) //!< Bit field size in bits for ENET_ECR_SLEEP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_ECR_SLEEP field.
-#define BR_ENET_ECR_SLEEP(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_SLEEP))
-#endif
-
-//! @brief Format value for bitfield ENET_ECR_SLEEP.
-#define BF_ENET_ECR_SLEEP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_SLEEP), uint32_t) & BM_ENET_ECR_SLEEP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SLEEP field to a new value.
-#define BW_ENET_ECR_SLEEP(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_SLEEP) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_ECR, field EN1588[4] (RW)
- *
- * Enables enhanced functionality of the MAC.
- *
- * Values:
- * - 0 - Legacy FEC buffer descriptors and functions enabled.
- * - 1 - Enhanced frame time-stamping functions enabled.
- */
-//@{
-#define BP_ENET_ECR_EN1588 (4U) //!< Bit position for ENET_ECR_EN1588.
-#define BM_ENET_ECR_EN1588 (0x00000010U) //!< Bit mask for ENET_ECR_EN1588.
-#define BS_ENET_ECR_EN1588 (1U) //!< Bit field size in bits for ENET_ECR_EN1588.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_ECR_EN1588 field.
-#define BR_ENET_ECR_EN1588(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_EN1588))
-#endif
-
-//! @brief Format value for bitfield ENET_ECR_EN1588.
-#define BF_ENET_ECR_EN1588(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_EN1588), uint32_t) & BM_ENET_ECR_EN1588)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EN1588 field to a new value.
-#define BW_ENET_ECR_EN1588(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_EN1588) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_ECR, field DBGEN[6] (RW)
- *
- * Enables the MAC to enter hardware freeze mode when the device enters debug
- * mode.
- *
- * Values:
- * - 0 - MAC continues operation in debug mode.
- * - 1 - MAC enters hardware freeze mode when the processor is in debug mode.
- */
-//@{
-#define BP_ENET_ECR_DBGEN (6U) //!< Bit position for ENET_ECR_DBGEN.
-#define BM_ENET_ECR_DBGEN (0x00000040U) //!< Bit mask for ENET_ECR_DBGEN.
-#define BS_ENET_ECR_DBGEN (1U) //!< Bit field size in bits for ENET_ECR_DBGEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_ECR_DBGEN field.
-#define BR_ENET_ECR_DBGEN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBGEN))
-#endif
-
-//! @brief Format value for bitfield ENET_ECR_DBGEN.
-#define BF_ENET_ECR_DBGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_DBGEN), uint32_t) & BM_ENET_ECR_DBGEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DBGEN field to a new value.
-#define BW_ENET_ECR_DBGEN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBGEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_ECR, field STOPEN[7] (RW)
- *
- * Controls device behavior in doze mode. In doze mode, if this field is set
- * then all the clocks of the ENET assembly are disabled, except the RMII /MII
- * clock. Doze mode is similar to a conditional stop mode entry for the ENET assembly
- * depending on ECR[STOPEN]. If module clocks are gated in this mode, the module
- * can still wake the system after receiving a magic packet in stop mode. MAGICEN
- * must be set prior to entering sleep/stop mode.
- */
-//@{
-#define BP_ENET_ECR_STOPEN (7U) //!< Bit position for ENET_ECR_STOPEN.
-#define BM_ENET_ECR_STOPEN (0x00000080U) //!< Bit mask for ENET_ECR_STOPEN.
-#define BS_ENET_ECR_STOPEN (1U) //!< Bit field size in bits for ENET_ECR_STOPEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_ECR_STOPEN field.
-#define BR_ENET_ECR_STOPEN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_STOPEN))
-#endif
-
-//! @brief Format value for bitfield ENET_ECR_STOPEN.
-#define BF_ENET_ECR_STOPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_STOPEN), uint32_t) & BM_ENET_ECR_STOPEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the STOPEN field to a new value.
-#define BW_ENET_ECR_STOPEN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_STOPEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_ECR, field DBSWP[8] (RW)
- *
- * Swaps the byte locations of the buffer descriptors. This field must be
- * written to 1 after reset.
- *
- * Values:
- * - 0 - The buffer descriptor bytes are not swapped to support big-endian
- * devices.
- * - 1 - The buffer descriptor bytes are swapped to support little-endian
- * devices.
- */
-//@{
-#define BP_ENET_ECR_DBSWP (8U) //!< Bit position for ENET_ECR_DBSWP.
-#define BM_ENET_ECR_DBSWP (0x00000100U) //!< Bit mask for ENET_ECR_DBSWP.
-#define BS_ENET_ECR_DBSWP (1U) //!< Bit field size in bits for ENET_ECR_DBSWP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_ECR_DBSWP field.
-#define BR_ENET_ECR_DBSWP(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBSWP))
-#endif
-
-//! @brief Format value for bitfield ENET_ECR_DBSWP.
-#define BF_ENET_ECR_DBSWP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_DBSWP), uint32_t) & BM_ENET_ECR_DBSWP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DBSWP field to a new value.
-#define BW_ENET_ECR_DBSWP(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBSWP) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_MMFR - MII Management Frame Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_MMFR - MII Management Frame Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * Writing to MMFR triggers a management frame transaction to the PHY device
- * unless MSCR is programmed to zero. If MSCR is changed from zero to non-zero
- * during a write to MMFR, an MII frame is generated with the data previously written
- * to the MMFR. This allows MMFR and MSCR to be programmed in either order if
- * MSCR is currently zero. If the MMFR register is written while frame generation is
- * in progress, the frame contents are altered. Software must use the EIR[MII]
- * interrupt indication to avoid writing to the MMFR register while frame
- * generation is in progress.
- */
-typedef union _hw_enet_mmfr
-{
- uint32_t U;
- struct _hw_enet_mmfr_bitfields
- {
- uint32_t DATA : 16; //!< [15:0] Management Frame Data
- uint32_t TA : 2; //!< [17:16] Turn Around
- uint32_t RA : 5; //!< [22:18] Register Address
- uint32_t PA : 5; //!< [27:23] PHY Address
- uint32_t OP : 2; //!< [29:28] Operation Code
- uint32_t ST : 2; //!< [31:30] Start Of Frame Delimiter
- } B;
-} hw_enet_mmfr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_MMFR register
- */
-//@{
-#define HW_ENET_MMFR_ADDR(x) (REGS_ENET_BASE(x) + 0x40U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_MMFR(x) (*(__IO hw_enet_mmfr_t *) HW_ENET_MMFR_ADDR(x))
-#define HW_ENET_MMFR_RD(x) (HW_ENET_MMFR(x).U)
-#define HW_ENET_MMFR_WR(x, v) (HW_ENET_MMFR(x).U = (v))
-#define HW_ENET_MMFR_SET(x, v) (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) | (v)))
-#define HW_ENET_MMFR_CLR(x, v) (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) & ~(v)))
-#define HW_ENET_MMFR_TOG(x, v) (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_MMFR bitfields
- */
-
-/*!
- * @name Register ENET_MMFR, field DATA[15:0] (RW)
- *
- * This is the field for data to be written to or read from the PHY register.
- */
-//@{
-#define BP_ENET_MMFR_DATA (0U) //!< Bit position for ENET_MMFR_DATA.
-#define BM_ENET_MMFR_DATA (0x0000FFFFU) //!< Bit mask for ENET_MMFR_DATA.
-#define BS_ENET_MMFR_DATA (16U) //!< Bit field size in bits for ENET_MMFR_DATA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_MMFR_DATA field.
-#define BR_ENET_MMFR_DATA(x) (HW_ENET_MMFR(x).B.DATA)
-#endif
-
-//! @brief Format value for bitfield ENET_MMFR_DATA.
-#define BF_ENET_MMFR_DATA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_DATA), uint32_t) & BM_ENET_MMFR_DATA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DATA field to a new value.
-#define BW_ENET_MMFR_DATA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_DATA) | BF_ENET_MMFR_DATA(v)))
-#endif
-//@}
-
-/*!
- * @name Register ENET_MMFR, field TA[17:16] (RW)
- *
- * This field must be programmed to 10 to generate a valid MII management frame.
- */
-//@{
-#define BP_ENET_MMFR_TA (16U) //!< Bit position for ENET_MMFR_TA.
-#define BM_ENET_MMFR_TA (0x00030000U) //!< Bit mask for ENET_MMFR_TA.
-#define BS_ENET_MMFR_TA (2U) //!< Bit field size in bits for ENET_MMFR_TA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_MMFR_TA field.
-#define BR_ENET_MMFR_TA(x) (HW_ENET_MMFR(x).B.TA)
-#endif
-
-//! @brief Format value for bitfield ENET_MMFR_TA.
-#define BF_ENET_MMFR_TA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_TA), uint32_t) & BM_ENET_MMFR_TA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TA field to a new value.
-#define BW_ENET_MMFR_TA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_TA) | BF_ENET_MMFR_TA(v)))
-#endif
-//@}
-
-/*!
- * @name Register ENET_MMFR, field RA[22:18] (RW)
- *
- * Specifies one of up to 32 registers within the specified PHY device.
- */
-//@{
-#define BP_ENET_MMFR_RA (18U) //!< Bit position for ENET_MMFR_RA.
-#define BM_ENET_MMFR_RA (0x007C0000U) //!< Bit mask for ENET_MMFR_RA.
-#define BS_ENET_MMFR_RA (5U) //!< Bit field size in bits for ENET_MMFR_RA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_MMFR_RA field.
-#define BR_ENET_MMFR_RA(x) (HW_ENET_MMFR(x).B.RA)
-#endif
-
-//! @brief Format value for bitfield ENET_MMFR_RA.
-#define BF_ENET_MMFR_RA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_RA), uint32_t) & BM_ENET_MMFR_RA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RA field to a new value.
-#define BW_ENET_MMFR_RA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_RA) | BF_ENET_MMFR_RA(v)))
-#endif
-//@}
-
-/*!
- * @name Register ENET_MMFR, field PA[27:23] (RW)
- *
- * Specifies one of up to 32 attached PHY devices.
- */
-//@{
-#define BP_ENET_MMFR_PA (23U) //!< Bit position for ENET_MMFR_PA.
-#define BM_ENET_MMFR_PA (0x0F800000U) //!< Bit mask for ENET_MMFR_PA.
-#define BS_ENET_MMFR_PA (5U) //!< Bit field size in bits for ENET_MMFR_PA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_MMFR_PA field.
-#define BR_ENET_MMFR_PA(x) (HW_ENET_MMFR(x).B.PA)
-#endif
-
-//! @brief Format value for bitfield ENET_MMFR_PA.
-#define BF_ENET_MMFR_PA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_PA), uint32_t) & BM_ENET_MMFR_PA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PA field to a new value.
-#define BW_ENET_MMFR_PA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_PA) | BF_ENET_MMFR_PA(v)))
-#endif
-//@}
-
-/*!
- * @name Register ENET_MMFR, field OP[29:28] (RW)
- *
- * Determines the frame operation.
- *
- * Values:
- * - 00 - Write frame operation, but not MII compliant.
- * - 01 - Write frame operation for a valid MII management frame.
- * - 10 - Read frame operation for a valid MII management frame.
- * - 11 - Read frame operation, but not MII compliant.
- */
-//@{
-#define BP_ENET_MMFR_OP (28U) //!< Bit position for ENET_MMFR_OP.
-#define BM_ENET_MMFR_OP (0x30000000U) //!< Bit mask for ENET_MMFR_OP.
-#define BS_ENET_MMFR_OP (2U) //!< Bit field size in bits for ENET_MMFR_OP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_MMFR_OP field.
-#define BR_ENET_MMFR_OP(x) (HW_ENET_MMFR(x).B.OP)
-#endif
-
-//! @brief Format value for bitfield ENET_MMFR_OP.
-#define BF_ENET_MMFR_OP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_OP), uint32_t) & BM_ENET_MMFR_OP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the OP field to a new value.
-#define BW_ENET_MMFR_OP(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_OP) | BF_ENET_MMFR_OP(v)))
-#endif
-//@}
-
-/*!
- * @name Register ENET_MMFR, field ST[31:30] (RW)
- *
- * These fields must be programmed to 01 for a valid MII management frame.
- */
-//@{
-#define BP_ENET_MMFR_ST (30U) //!< Bit position for ENET_MMFR_ST.
-#define BM_ENET_MMFR_ST (0xC0000000U) //!< Bit mask for ENET_MMFR_ST.
-#define BS_ENET_MMFR_ST (2U) //!< Bit field size in bits for ENET_MMFR_ST.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_MMFR_ST field.
-#define BR_ENET_MMFR_ST(x) (HW_ENET_MMFR(x).B.ST)
-#endif
-
-//! @brief Format value for bitfield ENET_MMFR_ST.
-#define BF_ENET_MMFR_ST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_ST), uint32_t) & BM_ENET_MMFR_ST)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ST field to a new value.
-#define BW_ENET_MMFR_ST(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_ST) | BF_ENET_MMFR_ST(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_MSCR - MII Speed Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_MSCR - MII Speed Control Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * MSCR provides control of the MII clock (MDC pin) frequency and allows a
- * preamble drop on the MII management frame. The MII_SPEED field must be programmed
- * with a value to provide an MDC frequency of less than or equal to 2.5 MHz to be
- * compliant with the IEEE 802.3 MII specification. The MII_SPEED must be set to
- * a non-zero value to source a read or write management frame. After the
- * management frame is complete, the MSCR register may optionally be cleared to turn
- * off MDC. The MDC signal generated has a 50% duty cycle except when MII_SPEED
- * changes during operation. This change takes effect following a rising or falling
- * edge of MDC. If the internal module clock is 25 MHz, programming this register
- * to 0x0000_0004 results in an MDC as stated in the following equation: 25 MHz
- * / ((4 + 1) x 2) = 2.5 MHz The following table shows the optimum values for
- * MII_SPEED as a function of internal module clock frequency. Programming Examples
- * for MSCR Internal MAC clock frequency MSCR [MII_SPEED] MDC frequency 25 MHz
- * 0x4 2.50 MHz 33 MHz 0x6 2.36 MHz 40 MHz 0x7 2.50 MHz 50 MHz 0x9 2.50 MHz 66 MHz
- * 0xD 2.36 MHz
- */
-typedef union _hw_enet_mscr
-{
- uint32_t U;
- struct _hw_enet_mscr_bitfields
- {
- uint32_t RESERVED0 : 1; //!< [0]
- uint32_t MII_SPEED : 6; //!< [6:1] MII Speed
- uint32_t DIS_PRE : 1; //!< [7] Disable Preamble
- uint32_t HOLDTIME : 3; //!< [10:8] Hold time On MDIO Output
- uint32_t RESERVED1 : 21; //!< [31:11]
- } B;
-} hw_enet_mscr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_MSCR register
- */
-//@{
-#define HW_ENET_MSCR_ADDR(x) (REGS_ENET_BASE(x) + 0x44U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_MSCR(x) (*(__IO hw_enet_mscr_t *) HW_ENET_MSCR_ADDR(x))
-#define HW_ENET_MSCR_RD(x) (HW_ENET_MSCR(x).U)
-#define HW_ENET_MSCR_WR(x, v) (HW_ENET_MSCR(x).U = (v))
-#define HW_ENET_MSCR_SET(x, v) (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) | (v)))
-#define HW_ENET_MSCR_CLR(x, v) (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) & ~(v)))
-#define HW_ENET_MSCR_TOG(x, v) (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_MSCR bitfields
- */
-
-/*!
- * @name Register ENET_MSCR, field MII_SPEED[6:1] (RW)
- *
- * Controls the frequency of the MII management interface clock (MDC) relative
- * to the internal module clock. A value of 0 in this field turns off MDC and
- * leaves it in low voltage state. Any non-zero value results in the MDC frequency
- * of: 1/((MII_SPEED + 1) x 2) of the internal module clock frequency
- */
-//@{
-#define BP_ENET_MSCR_MII_SPEED (1U) //!< Bit position for ENET_MSCR_MII_SPEED.
-#define BM_ENET_MSCR_MII_SPEED (0x0000007EU) //!< Bit mask for ENET_MSCR_MII_SPEED.
-#define BS_ENET_MSCR_MII_SPEED (6U) //!< Bit field size in bits for ENET_MSCR_MII_SPEED.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_MSCR_MII_SPEED field.
-#define BR_ENET_MSCR_MII_SPEED(x) (HW_ENET_MSCR(x).B.MII_SPEED)
-#endif
-
-//! @brief Format value for bitfield ENET_MSCR_MII_SPEED.
-#define BF_ENET_MSCR_MII_SPEED(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MSCR_MII_SPEED), uint32_t) & BM_ENET_MSCR_MII_SPEED)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MII_SPEED field to a new value.
-#define BW_ENET_MSCR_MII_SPEED(x, v) (HW_ENET_MSCR_WR(x, (HW_ENET_MSCR_RD(x) & ~BM_ENET_MSCR_MII_SPEED) | BF_ENET_MSCR_MII_SPEED(v)))
-#endif
-//@}
-
-/*!
- * @name Register ENET_MSCR, field DIS_PRE[7] (RW)
- *
- * Enables/disables prepending a preamble to the MII management frame. The MII
- * standard allows the preamble to be dropped if the attached PHY devices do not
- * require it.
- *
- * Values:
- * - 0 - Preamble enabled.
- * - 1 - Preamble (32 ones) is not prepended to the MII management frame.
- */
-//@{
-#define BP_ENET_MSCR_DIS_PRE (7U) //!< Bit position for ENET_MSCR_DIS_PRE.
-#define BM_ENET_MSCR_DIS_PRE (0x00000080U) //!< Bit mask for ENET_MSCR_DIS_PRE.
-#define BS_ENET_MSCR_DIS_PRE (1U) //!< Bit field size in bits for ENET_MSCR_DIS_PRE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_MSCR_DIS_PRE field.
-#define BR_ENET_MSCR_DIS_PRE(x) (BITBAND_ACCESS32(HW_ENET_MSCR_ADDR(x), BP_ENET_MSCR_DIS_PRE))
-#endif
-
-//! @brief Format value for bitfield ENET_MSCR_DIS_PRE.
-#define BF_ENET_MSCR_DIS_PRE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MSCR_DIS_PRE), uint32_t) & BM_ENET_MSCR_DIS_PRE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DIS_PRE field to a new value.
-#define BW_ENET_MSCR_DIS_PRE(x, v) (BITBAND_ACCESS32(HW_ENET_MSCR_ADDR(x), BP_ENET_MSCR_DIS_PRE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_MSCR, field HOLDTIME[10:8] (RW)
- *
- * IEEE802.3 clause 22 defines a minimum of 10 ns for the hold time on the MDIO
- * output. Depending on the host bus frequency, the setting may need to be
- * increased.
- *
- * Values:
- * - 000 - 1 internal module clock cycle
- * - 001 - 2 internal module clock cycles
- * - 010 - 3 internal module clock cycles
- * - 111 - 8 internal module clock cycles
- */
-//@{
-#define BP_ENET_MSCR_HOLDTIME (8U) //!< Bit position for ENET_MSCR_HOLDTIME.
-#define BM_ENET_MSCR_HOLDTIME (0x00000700U) //!< Bit mask for ENET_MSCR_HOLDTIME.
-#define BS_ENET_MSCR_HOLDTIME (3U) //!< Bit field size in bits for ENET_MSCR_HOLDTIME.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_MSCR_HOLDTIME field.
-#define BR_ENET_MSCR_HOLDTIME(x) (HW_ENET_MSCR(x).B.HOLDTIME)
-#endif
-
-//! @brief Format value for bitfield ENET_MSCR_HOLDTIME.
-#define BF_ENET_MSCR_HOLDTIME(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MSCR_HOLDTIME), uint32_t) & BM_ENET_MSCR_HOLDTIME)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the HOLDTIME field to a new value.
-#define BW_ENET_MSCR_HOLDTIME(x, v) (HW_ENET_MSCR_WR(x, (HW_ENET_MSCR_RD(x) & ~BM_ENET_MSCR_HOLDTIME) | BF_ENET_MSCR_HOLDTIME(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_MIBC - MIB Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_MIBC - MIB Control Register (RW)
- *
- * Reset value: 0xC0000000U
- *
- * MIBC is a read/write register controlling and observing the state of the MIB
- * block. Access this register to disable the MIB block operation or clear the
- * MIB counters. The MIB_DIS field resets to 1.
- */
-typedef union _hw_enet_mibc
-{
- uint32_t U;
- struct _hw_enet_mibc_bitfields
- {
- uint32_t RESERVED0 : 29; //!< [28:0]
- uint32_t MIB_CLEAR : 1; //!< [29] MIB Clear
- uint32_t MIB_IDLE : 1; //!< [30] MIB Idle
- uint32_t MIB_DIS : 1; //!< [31] Disable MIB Logic
- } B;
-} hw_enet_mibc_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_MIBC register
- */
-//@{
-#define HW_ENET_MIBC_ADDR(x) (REGS_ENET_BASE(x) + 0x64U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_MIBC(x) (*(__IO hw_enet_mibc_t *) HW_ENET_MIBC_ADDR(x))
-#define HW_ENET_MIBC_RD(x) (HW_ENET_MIBC(x).U)
-#define HW_ENET_MIBC_WR(x, v) (HW_ENET_MIBC(x).U = (v))
-#define HW_ENET_MIBC_SET(x, v) (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) | (v)))
-#define HW_ENET_MIBC_CLR(x, v) (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) & ~(v)))
-#define HW_ENET_MIBC_TOG(x, v) (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_MIBC bitfields
- */
-
-/*!
- * @name Register ENET_MIBC, field MIB_CLEAR[29] (RW)
- *
- * If set, all statistics counters are reset to 0. This field is not
- * self-clearing. To clear the MIB counters set and then clear the field.
- */
-//@{
-#define BP_ENET_MIBC_MIB_CLEAR (29U) //!< Bit position for ENET_MIBC_MIB_CLEAR.
-#define BM_ENET_MIBC_MIB_CLEAR (0x20000000U) //!< Bit mask for ENET_MIBC_MIB_CLEAR.
-#define BS_ENET_MIBC_MIB_CLEAR (1U) //!< Bit field size in bits for ENET_MIBC_MIB_CLEAR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_MIBC_MIB_CLEAR field.
-#define BR_ENET_MIBC_MIB_CLEAR(x) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_CLEAR))
-#endif
-
-//! @brief Format value for bitfield ENET_MIBC_MIB_CLEAR.
-#define BF_ENET_MIBC_MIB_CLEAR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MIBC_MIB_CLEAR), uint32_t) & BM_ENET_MIBC_MIB_CLEAR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MIB_CLEAR field to a new value.
-#define BW_ENET_MIBC_MIB_CLEAR(x, v) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_CLEAR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_MIBC, field MIB_IDLE[30] (RO)
- *
- * If this status field is set, the MIB block is not currently updating any MIB
- * counters.
- */
-//@{
-#define BP_ENET_MIBC_MIB_IDLE (30U) //!< Bit position for ENET_MIBC_MIB_IDLE.
-#define BM_ENET_MIBC_MIB_IDLE (0x40000000U) //!< Bit mask for ENET_MIBC_MIB_IDLE.
-#define BS_ENET_MIBC_MIB_IDLE (1U) //!< Bit field size in bits for ENET_MIBC_MIB_IDLE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_MIBC_MIB_IDLE field.
-#define BR_ENET_MIBC_MIB_IDLE(x) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_IDLE))
-#endif
-//@}
-
-/*!
- * @name Register ENET_MIBC, field MIB_DIS[31] (RW)
- *
- * If this control field is set, the MIB logic halts and does not update any MIB
- * counters.
- */
-//@{
-#define BP_ENET_MIBC_MIB_DIS (31U) //!< Bit position for ENET_MIBC_MIB_DIS.
-#define BM_ENET_MIBC_MIB_DIS (0x80000000U) //!< Bit mask for ENET_MIBC_MIB_DIS.
-#define BS_ENET_MIBC_MIB_DIS (1U) //!< Bit field size in bits for ENET_MIBC_MIB_DIS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_MIBC_MIB_DIS field.
-#define BR_ENET_MIBC_MIB_DIS(x) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_DIS))
-#endif
-
-//! @brief Format value for bitfield ENET_MIBC_MIB_DIS.
-#define BF_ENET_MIBC_MIB_DIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MIBC_MIB_DIS), uint32_t) & BM_ENET_MIBC_MIB_DIS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MIB_DIS field to a new value.
-#define BW_ENET_MIBC_MIB_DIS(x, v) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_DIS) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RCR - Receive Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RCR - Receive Control Register (RW)
- *
- * Reset value: 0x05EE0001U
- */
-typedef union _hw_enet_rcr
-{
- uint32_t U;
- struct _hw_enet_rcr_bitfields
- {
- uint32_t LOOP : 1; //!< [0] Internal Loopback
- uint32_t DRT : 1; //!< [1] Disable Receive On Transmit
- uint32_t MII_MODE : 1; //!< [2] Media Independent Interface Mode
- uint32_t PROM : 1; //!< [3] Promiscuous Mode
- uint32_t BC_REJ : 1; //!< [4] Broadcast Frame Reject
- uint32_t FCE : 1; //!< [5] Flow Control Enable
- uint32_t RESERVED0 : 2; //!< [7:6]
- uint32_t RMII_MODE : 1; //!< [8] RMII Mode Enable
- uint32_t RMII_10T : 1; //!< [9]
- uint32_t RESERVED1 : 2; //!< [11:10]
- uint32_t PADEN : 1; //!< [12] Enable Frame Padding Remove On Receive
- uint32_t PAUFWD : 1; //!< [13] Terminate/Forward Pause Frames
- uint32_t CRCFWD : 1; //!< [14] Terminate/Forward Received CRC
- uint32_t CFEN : 1; //!< [15] MAC Control Frame Enable
- uint32_t MAX_FL : 14; //!< [29:16] Maximum Frame Length
- uint32_t NLC : 1; //!< [30] Payload Length Check Disable
- uint32_t GRS : 1; //!< [31] Graceful Receive Stopped
- } B;
-} hw_enet_rcr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RCR register
- */
-//@{
-#define HW_ENET_RCR_ADDR(x) (REGS_ENET_BASE(x) + 0x84U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RCR(x) (*(__IO hw_enet_rcr_t *) HW_ENET_RCR_ADDR(x))
-#define HW_ENET_RCR_RD(x) (HW_ENET_RCR(x).U)
-#define HW_ENET_RCR_WR(x, v) (HW_ENET_RCR(x).U = (v))
-#define HW_ENET_RCR_SET(x, v) (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) | (v)))
-#define HW_ENET_RCR_CLR(x, v) (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) & ~(v)))
-#define HW_ENET_RCR_TOG(x, v) (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RCR bitfields
- */
-
-/*!
- * @name Register ENET_RCR, field LOOP[0] (RW)
- *
- * This is an MII internal loopback, therefore MII_MODE must be written to 1 and
- * RMII_MODE must be written to 0.
- *
- * Values:
- * - 0 - Loopback disabled.
- * - 1 - Transmitted frames are looped back internal to the device and transmit
- * MII output signals are not asserted. DRT must be cleared.
- */
-//@{
-#define BP_ENET_RCR_LOOP (0U) //!< Bit position for ENET_RCR_LOOP.
-#define BM_ENET_RCR_LOOP (0x00000001U) //!< Bit mask for ENET_RCR_LOOP.
-#define BS_ENET_RCR_LOOP (1U) //!< Bit field size in bits for ENET_RCR_LOOP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RCR_LOOP field.
-#define BR_ENET_RCR_LOOP(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_LOOP))
-#endif
-
-//! @brief Format value for bitfield ENET_RCR_LOOP.
-#define BF_ENET_RCR_LOOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_LOOP), uint32_t) & BM_ENET_RCR_LOOP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LOOP field to a new value.
-#define BW_ENET_RCR_LOOP(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_LOOP) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_RCR, field DRT[1] (RW)
- *
- * Values:
- * - 0 - Receive path operates independently of transmit. Used for full-duplex
- * or to monitor transmit activity in half-duplex mode.
- * - 1 - Disable reception of frames while transmitting. Normally used for
- * half-duplex mode.
- */
-//@{
-#define BP_ENET_RCR_DRT (1U) //!< Bit position for ENET_RCR_DRT.
-#define BM_ENET_RCR_DRT (0x00000002U) //!< Bit mask for ENET_RCR_DRT.
-#define BS_ENET_RCR_DRT (1U) //!< Bit field size in bits for ENET_RCR_DRT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RCR_DRT field.
-#define BR_ENET_RCR_DRT(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_DRT))
-#endif
-
-//! @brief Format value for bitfield ENET_RCR_DRT.
-#define BF_ENET_RCR_DRT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_DRT), uint32_t) & BM_ENET_RCR_DRT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DRT field to a new value.
-#define BW_ENET_RCR_DRT(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_DRT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_RCR, field MII_MODE[2] (RW)
- *
- * This field must always be set.
- *
- * Values:
- * - 0 - Reserved.
- * - 1 - MII or RMII mode, as indicated by the RMII_MODE field.
- */
-//@{
-#define BP_ENET_RCR_MII_MODE (2U) //!< Bit position for ENET_RCR_MII_MODE.
-#define BM_ENET_RCR_MII_MODE (0x00000004U) //!< Bit mask for ENET_RCR_MII_MODE.
-#define BS_ENET_RCR_MII_MODE (1U) //!< Bit field size in bits for ENET_RCR_MII_MODE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RCR_MII_MODE field.
-#define BR_ENET_RCR_MII_MODE(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_MII_MODE))
-#endif
-
-//! @brief Format value for bitfield ENET_RCR_MII_MODE.
-#define BF_ENET_RCR_MII_MODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_MII_MODE), uint32_t) & BM_ENET_RCR_MII_MODE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MII_MODE field to a new value.
-#define BW_ENET_RCR_MII_MODE(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_MII_MODE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_RCR, field PROM[3] (RW)
- *
- * All frames are accepted regardless of address matching.
- *
- * Values:
- * - 0 - Disabled.
- * - 1 - Enabled.
- */
-//@{
-#define BP_ENET_RCR_PROM (3U) //!< Bit position for ENET_RCR_PROM.
-#define BM_ENET_RCR_PROM (0x00000008U) //!< Bit mask for ENET_RCR_PROM.
-#define BS_ENET_RCR_PROM (1U) //!< Bit field size in bits for ENET_RCR_PROM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RCR_PROM field.
-#define BR_ENET_RCR_PROM(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PROM))
-#endif
-
-//! @brief Format value for bitfield ENET_RCR_PROM.
-#define BF_ENET_RCR_PROM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_PROM), uint32_t) & BM_ENET_RCR_PROM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PROM field to a new value.
-#define BW_ENET_RCR_PROM(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PROM) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_RCR, field BC_REJ[4] (RW)
- *
- * If set, frames with destination address (DA) equal to 0xFFFF_FFFF_FFFF are
- * rejected unless the PROM field is set. If BC_REJ and PROM are set, frames with
- * broadcast DA are accepted and the MISS (M) is set in the receive buffer
- * descriptor.
- */
-//@{
-#define BP_ENET_RCR_BC_REJ (4U) //!< Bit position for ENET_RCR_BC_REJ.
-#define BM_ENET_RCR_BC_REJ (0x00000010U) //!< Bit mask for ENET_RCR_BC_REJ.
-#define BS_ENET_RCR_BC_REJ (1U) //!< Bit field size in bits for ENET_RCR_BC_REJ.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RCR_BC_REJ field.
-#define BR_ENET_RCR_BC_REJ(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_BC_REJ))
-#endif
-
-//! @brief Format value for bitfield ENET_RCR_BC_REJ.
-#define BF_ENET_RCR_BC_REJ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_BC_REJ), uint32_t) & BM_ENET_RCR_BC_REJ)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BC_REJ field to a new value.
-#define BW_ENET_RCR_BC_REJ(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_BC_REJ) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_RCR, field FCE[5] (RW)
- *
- * If set, the receiver detects PAUSE frames. Upon PAUSE frame detection, the
- * transmitter stops transmitting data frames for a given duration.
- */
-//@{
-#define BP_ENET_RCR_FCE (5U) //!< Bit position for ENET_RCR_FCE.
-#define BM_ENET_RCR_FCE (0x00000020U) //!< Bit mask for ENET_RCR_FCE.
-#define BS_ENET_RCR_FCE (1U) //!< Bit field size in bits for ENET_RCR_FCE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RCR_FCE field.
-#define BR_ENET_RCR_FCE(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_FCE))
-#endif
-
-//! @brief Format value for bitfield ENET_RCR_FCE.
-#define BF_ENET_RCR_FCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_FCE), uint32_t) & BM_ENET_RCR_FCE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FCE field to a new value.
-#define BW_ENET_RCR_FCE(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_FCE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_RCR, field RMII_MODE[8] (RW)
- *
- * Specifies whether the MAC is configured for MII mode or RMII operation .
- *
- * Values:
- * - 0 - MAC configured for MII mode.
- * - 1 - MAC configured for RMII operation.
- */
-//@{
-#define BP_ENET_RCR_RMII_MODE (8U) //!< Bit position for ENET_RCR_RMII_MODE.
-#define BM_ENET_RCR_RMII_MODE (0x00000100U) //!< Bit mask for ENET_RCR_RMII_MODE.
-#define BS_ENET_RCR_RMII_MODE (1U) //!< Bit field size in bits for ENET_RCR_RMII_MODE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RCR_RMII_MODE field.
-#define BR_ENET_RCR_RMII_MODE(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_MODE))
-#endif
-
-//! @brief Format value for bitfield ENET_RCR_RMII_MODE.
-#define BF_ENET_RCR_RMII_MODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_RMII_MODE), uint32_t) & BM_ENET_RCR_RMII_MODE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RMII_MODE field to a new value.
-#define BW_ENET_RCR_RMII_MODE(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_MODE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_RCR, field RMII_10T[9] (RW)
- *
- * Enables 10-Mbps mode of the RMII .
- *
- * Values:
- * - 0 - 100 Mbps operation.
- * - 1 - 10 Mbps operation.
- */
-//@{
-#define BP_ENET_RCR_RMII_10T (9U) //!< Bit position for ENET_RCR_RMII_10T.
-#define BM_ENET_RCR_RMII_10T (0x00000200U) //!< Bit mask for ENET_RCR_RMII_10T.
-#define BS_ENET_RCR_RMII_10T (1U) //!< Bit field size in bits for ENET_RCR_RMII_10T.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RCR_RMII_10T field.
-#define BR_ENET_RCR_RMII_10T(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_10T))
-#endif
-
-//! @brief Format value for bitfield ENET_RCR_RMII_10T.
-#define BF_ENET_RCR_RMII_10T(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_RMII_10T), uint32_t) & BM_ENET_RCR_RMII_10T)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RMII_10T field to a new value.
-#define BW_ENET_RCR_RMII_10T(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_10T) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_RCR, field PADEN[12] (RW)
- *
- * Specifies whether the MAC removes padding from received frames.
- *
- * Values:
- * - 0 - No padding is removed on receive by the MAC.
- * - 1 - Padding is removed from received frames.
- */
-//@{
-#define BP_ENET_RCR_PADEN (12U) //!< Bit position for ENET_RCR_PADEN.
-#define BM_ENET_RCR_PADEN (0x00001000U) //!< Bit mask for ENET_RCR_PADEN.
-#define BS_ENET_RCR_PADEN (1U) //!< Bit field size in bits for ENET_RCR_PADEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RCR_PADEN field.
-#define BR_ENET_RCR_PADEN(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PADEN))
-#endif
-
-//! @brief Format value for bitfield ENET_RCR_PADEN.
-#define BF_ENET_RCR_PADEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_PADEN), uint32_t) & BM_ENET_RCR_PADEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PADEN field to a new value.
-#define BW_ENET_RCR_PADEN(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PADEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_RCR, field PAUFWD[13] (RW)
- *
- * Specifies whether pause frames are terminated or forwarded.
- *
- * Values:
- * - 0 - Pause frames are terminated and discarded in the MAC.
- * - 1 - Pause frames are forwarded to the user application.
- */
-//@{
-#define BP_ENET_RCR_PAUFWD (13U) //!< Bit position for ENET_RCR_PAUFWD.
-#define BM_ENET_RCR_PAUFWD (0x00002000U) //!< Bit mask for ENET_RCR_PAUFWD.
-#define BS_ENET_RCR_PAUFWD (1U) //!< Bit field size in bits for ENET_RCR_PAUFWD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RCR_PAUFWD field.
-#define BR_ENET_RCR_PAUFWD(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PAUFWD))
-#endif
-
-//! @brief Format value for bitfield ENET_RCR_PAUFWD.
-#define BF_ENET_RCR_PAUFWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_PAUFWD), uint32_t) & BM_ENET_RCR_PAUFWD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PAUFWD field to a new value.
-#define BW_ENET_RCR_PAUFWD(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PAUFWD) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_RCR, field CRCFWD[14] (RW)
- *
- * Specifies whether the CRC field of received frames is transmitted or
- * stripped. If padding function is enabled (PADEN = 1), CRCFWD is ignored and the CRC
- * field is checked and always terminated and removed.
- *
- * Values:
- * - 0 - The CRC field of received frames is transmitted to the user application.
- * - 1 - The CRC field is stripped from the frame.
- */
-//@{
-#define BP_ENET_RCR_CRCFWD (14U) //!< Bit position for ENET_RCR_CRCFWD.
-#define BM_ENET_RCR_CRCFWD (0x00004000U) //!< Bit mask for ENET_RCR_CRCFWD.
-#define BS_ENET_RCR_CRCFWD (1U) //!< Bit field size in bits for ENET_RCR_CRCFWD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RCR_CRCFWD field.
-#define BR_ENET_RCR_CRCFWD(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CRCFWD))
-#endif
-
-//! @brief Format value for bitfield ENET_RCR_CRCFWD.
-#define BF_ENET_RCR_CRCFWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_CRCFWD), uint32_t) & BM_ENET_RCR_CRCFWD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CRCFWD field to a new value.
-#define BW_ENET_RCR_CRCFWD(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CRCFWD) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_RCR, field CFEN[15] (RW)
- *
- * Enables/disables the MAC control frame.
- *
- * Values:
- * - 0 - MAC control frames with any opcode other than 0x0001 (pause frame) are
- * accepted and forwarded to the client interface.
- * - 1 - MAC control frames with any opcode other than 0x0001 (pause frame) are
- * silently discarded.
- */
-//@{
-#define BP_ENET_RCR_CFEN (15U) //!< Bit position for ENET_RCR_CFEN.
-#define BM_ENET_RCR_CFEN (0x00008000U) //!< Bit mask for ENET_RCR_CFEN.
-#define BS_ENET_RCR_CFEN (1U) //!< Bit field size in bits for ENET_RCR_CFEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RCR_CFEN field.
-#define BR_ENET_RCR_CFEN(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CFEN))
-#endif
-
-//! @brief Format value for bitfield ENET_RCR_CFEN.
-#define BF_ENET_RCR_CFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_CFEN), uint32_t) & BM_ENET_RCR_CFEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CFEN field to a new value.
-#define BW_ENET_RCR_CFEN(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CFEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_RCR, field MAX_FL[29:16] (RW)
- *
- * Resets to decimal 1518. Length is measured starting at DA and includes the
- * CRC at the end of the frame. Transmit frames longer than MAX_FL cause the BABT
- * interrupt to occur. Receive frames longer than MAX_FL cause the BABR interrupt
- * to occur and set the LG field in the end of frame receive buffer descriptor.
- * The recommended default value to be programmed is 1518 or 1522 if VLAN tags are
- * supported.
- */
-//@{
-#define BP_ENET_RCR_MAX_FL (16U) //!< Bit position for ENET_RCR_MAX_FL.
-#define BM_ENET_RCR_MAX_FL (0x3FFF0000U) //!< Bit mask for ENET_RCR_MAX_FL.
-#define BS_ENET_RCR_MAX_FL (14U) //!< Bit field size in bits for ENET_RCR_MAX_FL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RCR_MAX_FL field.
-#define BR_ENET_RCR_MAX_FL(x) (HW_ENET_RCR(x).B.MAX_FL)
-#endif
-
-//! @brief Format value for bitfield ENET_RCR_MAX_FL.
-#define BF_ENET_RCR_MAX_FL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_MAX_FL), uint32_t) & BM_ENET_RCR_MAX_FL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MAX_FL field to a new value.
-#define BW_ENET_RCR_MAX_FL(x, v) (HW_ENET_RCR_WR(x, (HW_ENET_RCR_RD(x) & ~BM_ENET_RCR_MAX_FL) | BF_ENET_RCR_MAX_FL(v)))
-#endif
-//@}
-
-/*!
- * @name Register ENET_RCR, field NLC[30] (RW)
- *
- * Enables/disables a payload length check.
- *
- * Values:
- * - 0 - The payload length check is disabled.
- * - 1 - The core checks the frame's payload length with the frame length/type
- * field. Errors are indicated in the EIR[PLC] field.
- */
-//@{
-#define BP_ENET_RCR_NLC (30U) //!< Bit position for ENET_RCR_NLC.
-#define BM_ENET_RCR_NLC (0x40000000U) //!< Bit mask for ENET_RCR_NLC.
-#define BS_ENET_RCR_NLC (1U) //!< Bit field size in bits for ENET_RCR_NLC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RCR_NLC field.
-#define BR_ENET_RCR_NLC(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_NLC))
-#endif
-
-//! @brief Format value for bitfield ENET_RCR_NLC.
-#define BF_ENET_RCR_NLC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_NLC), uint32_t) & BM_ENET_RCR_NLC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the NLC field to a new value.
-#define BW_ENET_RCR_NLC(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_NLC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_RCR, field GRS[31] (RO)
- *
- * Read-only status indicating that the MAC receive datapath is stopped.
- */
-//@{
-#define BP_ENET_RCR_GRS (31U) //!< Bit position for ENET_RCR_GRS.
-#define BM_ENET_RCR_GRS (0x80000000U) //!< Bit mask for ENET_RCR_GRS.
-#define BS_ENET_RCR_GRS (1U) //!< Bit field size in bits for ENET_RCR_GRS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RCR_GRS field.
-#define BR_ENET_RCR_GRS(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_GRS))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_TCR - Transmit Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_TCR - Transmit Control Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * TCR is read/write and configures the transmit block. This register is cleared
- * at system reset. FDEN can only be modified when ECR[ETHEREN] is cleared.
- */
-typedef union _hw_enet_tcr
-{
- uint32_t U;
- struct _hw_enet_tcr_bitfields
- {
- uint32_t GTS : 1; //!< [0] Graceful Transmit Stop
- uint32_t RESERVED0 : 1; //!< [1]
- uint32_t FDEN : 1; //!< [2] Full-Duplex Enable
- uint32_t TFC_PAUSE : 1; //!< [3] Transmit Frame Control Pause
- uint32_t RFC_PAUSE : 1; //!< [4] Receive Frame Control Pause
- uint32_t ADDSEL : 3; //!< [7:5] Source MAC Address Select On Transmit
- uint32_t ADDINS : 1; //!< [8] Set MAC Address On Transmit
- uint32_t CRCFWD : 1; //!< [9] Forward Frame From Application With CRC
- uint32_t RESERVED1 : 22; //!< [31:10]
- } B;
-} hw_enet_tcr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_TCR register
- */
-//@{
-#define HW_ENET_TCR_ADDR(x) (REGS_ENET_BASE(x) + 0xC4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_TCR(x) (*(__IO hw_enet_tcr_t *) HW_ENET_TCR_ADDR(x))
-#define HW_ENET_TCR_RD(x) (HW_ENET_TCR(x).U)
-#define HW_ENET_TCR_WR(x, v) (HW_ENET_TCR(x).U = (v))
-#define HW_ENET_TCR_SET(x, v) (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) | (v)))
-#define HW_ENET_TCR_CLR(x, v) (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) & ~(v)))
-#define HW_ENET_TCR_TOG(x, v) (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_TCR bitfields
- */
-
-/*!
- * @name Register ENET_TCR, field GTS[0] (RW)
- *
- * When this field is set, MAC stops transmission after any frame currently
- * transmitted is complete and EIR[GRA] is set. If frame transmission is not
- * currently underway, the GRA interrupt is asserted immediately. After transmission
- * finishes, clear GTS to restart. The next frame in the transmit FIFO is then
- * transmitted. If an early collision occurs during transmission when GTS is set,
- * transmission stops after the collision. The frame is transmitted again after GTS is
- * cleared. There may be old frames in the transmit FIFO that transmit when GTS
- * is reasserted. To avoid this, clear ECR[ETHEREN] following the GRA interrupt.
- */
-//@{
-#define BP_ENET_TCR_GTS (0U) //!< Bit position for ENET_TCR_GTS.
-#define BM_ENET_TCR_GTS (0x00000001U) //!< Bit mask for ENET_TCR_GTS.
-#define BS_ENET_TCR_GTS (1U) //!< Bit field size in bits for ENET_TCR_GTS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_TCR_GTS field.
-#define BR_ENET_TCR_GTS(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_GTS))
-#endif
-
-//! @brief Format value for bitfield ENET_TCR_GTS.
-#define BF_ENET_TCR_GTS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_GTS), uint32_t) & BM_ENET_TCR_GTS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the GTS field to a new value.
-#define BW_ENET_TCR_GTS(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_GTS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_TCR, field FDEN[2] (RW)
- *
- * If this field is set, frames transmit independent of carrier sense and
- * collision inputs. Only modify this bit when ECR[ETHEREN] is cleared.
- */
-//@{
-#define BP_ENET_TCR_FDEN (2U) //!< Bit position for ENET_TCR_FDEN.
-#define BM_ENET_TCR_FDEN (0x00000004U) //!< Bit mask for ENET_TCR_FDEN.
-#define BS_ENET_TCR_FDEN (1U) //!< Bit field size in bits for ENET_TCR_FDEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_TCR_FDEN field.
-#define BR_ENET_TCR_FDEN(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_FDEN))
-#endif
-
-//! @brief Format value for bitfield ENET_TCR_FDEN.
-#define BF_ENET_TCR_FDEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_FDEN), uint32_t) & BM_ENET_TCR_FDEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FDEN field to a new value.
-#define BW_ENET_TCR_FDEN(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_FDEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_TCR, field TFC_PAUSE[3] (RW)
- *
- * Pauses frame transmission. When this field is set, EIR[GRA] is set. With
- * transmission of data frames stopped, the MAC transmits a MAC control PAUSE frame.
- * Next, the MAC clears TFC_PAUSE and resumes transmitting data frames. If the
- * transmitter pauses due to user assertion of GTS or reception of a PAUSE frame,
- * the MAC may continue transmitting a MAC control PAUSE frame.
- *
- * Values:
- * - 0 - No PAUSE frame transmitted.
- * - 1 - The MAC stops transmission of data frames after the current
- * transmission is complete.
- */
-//@{
-#define BP_ENET_TCR_TFC_PAUSE (3U) //!< Bit position for ENET_TCR_TFC_PAUSE.
-#define BM_ENET_TCR_TFC_PAUSE (0x00000008U) //!< Bit mask for ENET_TCR_TFC_PAUSE.
-#define BS_ENET_TCR_TFC_PAUSE (1U) //!< Bit field size in bits for ENET_TCR_TFC_PAUSE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_TCR_TFC_PAUSE field.
-#define BR_ENET_TCR_TFC_PAUSE(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_TFC_PAUSE))
-#endif
-
-//! @brief Format value for bitfield ENET_TCR_TFC_PAUSE.
-#define BF_ENET_TCR_TFC_PAUSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_TFC_PAUSE), uint32_t) & BM_ENET_TCR_TFC_PAUSE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TFC_PAUSE field to a new value.
-#define BW_ENET_TCR_TFC_PAUSE(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_TFC_PAUSE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_TCR, field RFC_PAUSE[4] (RO)
- *
- * This status field is set when a full-duplex flow control pause frame is
- * received and the transmitter pauses for the duration defined in this pause frame.
- * This field automatically clears when the pause duration is complete.
- */
-//@{
-#define BP_ENET_TCR_RFC_PAUSE (4U) //!< Bit position for ENET_TCR_RFC_PAUSE.
-#define BM_ENET_TCR_RFC_PAUSE (0x00000010U) //!< Bit mask for ENET_TCR_RFC_PAUSE.
-#define BS_ENET_TCR_RFC_PAUSE (1U) //!< Bit field size in bits for ENET_TCR_RFC_PAUSE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_TCR_RFC_PAUSE field.
-#define BR_ENET_TCR_RFC_PAUSE(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_RFC_PAUSE))
-#endif
-//@}
-
-/*!
- * @name Register ENET_TCR, field ADDSEL[7:5] (RW)
- *
- * If ADDINS is set, indicates the MAC address that overwrites the source MAC
- * address.
- *
- * Values:
- * - 000 - Node MAC address programmed on PADDR1/2 registers.
- * - 100 - Reserved.
- * - 101 - Reserved.
- * - 110 - Reserved.
- */
-//@{
-#define BP_ENET_TCR_ADDSEL (5U) //!< Bit position for ENET_TCR_ADDSEL.
-#define BM_ENET_TCR_ADDSEL (0x000000E0U) //!< Bit mask for ENET_TCR_ADDSEL.
-#define BS_ENET_TCR_ADDSEL (3U) //!< Bit field size in bits for ENET_TCR_ADDSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_TCR_ADDSEL field.
-#define BR_ENET_TCR_ADDSEL(x) (HW_ENET_TCR(x).B.ADDSEL)
-#endif
-
-//! @brief Format value for bitfield ENET_TCR_ADDSEL.
-#define BF_ENET_TCR_ADDSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_ADDSEL), uint32_t) & BM_ENET_TCR_ADDSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ADDSEL field to a new value.
-#define BW_ENET_TCR_ADDSEL(x, v) (HW_ENET_TCR_WR(x, (HW_ENET_TCR_RD(x) & ~BM_ENET_TCR_ADDSEL) | BF_ENET_TCR_ADDSEL(v)))
-#endif
-//@}
-
-/*!
- * @name Register ENET_TCR, field ADDINS[8] (RW)
- *
- * Values:
- * - 0 - The source MAC address is not modified by the MAC.
- * - 1 - The MAC overwrites the source MAC address with the programmed MAC
- * address according to ADDSEL.
- */
-//@{
-#define BP_ENET_TCR_ADDINS (8U) //!< Bit position for ENET_TCR_ADDINS.
-#define BM_ENET_TCR_ADDINS (0x00000100U) //!< Bit mask for ENET_TCR_ADDINS.
-#define BS_ENET_TCR_ADDINS (1U) //!< Bit field size in bits for ENET_TCR_ADDINS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_TCR_ADDINS field.
-#define BR_ENET_TCR_ADDINS(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_ADDINS))
-#endif
-
-//! @brief Format value for bitfield ENET_TCR_ADDINS.
-#define BF_ENET_TCR_ADDINS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_ADDINS), uint32_t) & BM_ENET_TCR_ADDINS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ADDINS field to a new value.
-#define BW_ENET_TCR_ADDINS(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_ADDINS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_TCR, field CRCFWD[9] (RW)
- *
- * Values:
- * - 0 - TxBD[TC] controls whether the frame has a CRC from the application.
- * - 1 - The transmitter does not append any CRC to transmitted frames, as it is
- * expecting a frame with CRC from the application.
- */
-//@{
-#define BP_ENET_TCR_CRCFWD (9U) //!< Bit position for ENET_TCR_CRCFWD.
-#define BM_ENET_TCR_CRCFWD (0x00000200U) //!< Bit mask for ENET_TCR_CRCFWD.
-#define BS_ENET_TCR_CRCFWD (1U) //!< Bit field size in bits for ENET_TCR_CRCFWD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_TCR_CRCFWD field.
-#define BR_ENET_TCR_CRCFWD(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_CRCFWD))
-#endif
-
-//! @brief Format value for bitfield ENET_TCR_CRCFWD.
-#define BF_ENET_TCR_CRCFWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_CRCFWD), uint32_t) & BM_ENET_TCR_CRCFWD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CRCFWD field to a new value.
-#define BW_ENET_TCR_CRCFWD(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_CRCFWD) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_PALR - Physical Address Lower Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_PALR - Physical Address Lower Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * PALR contains the lower 32 bits (bytes 0, 1, 2, 3) of the 48-bit address used
- * in the address recognition process to compare with the destination address
- * (DA) field of receive frames with an individual DA. In addition, this register
- * is used in bytes 0 through 3 of the six-byte source address field when
- * transmitting PAUSE frames. This register is not reset and you must initialize it.
- */
-typedef union _hw_enet_palr
-{
- uint32_t U;
- struct _hw_enet_palr_bitfields
- {
- uint32_t PADDR1 : 32; //!< [31:0] Pause Address
- } B;
-} hw_enet_palr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_PALR register
- */
-//@{
-#define HW_ENET_PALR_ADDR(x) (REGS_ENET_BASE(x) + 0xE4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_PALR(x) (*(__IO hw_enet_palr_t *) HW_ENET_PALR_ADDR(x))
-#define HW_ENET_PALR_RD(x) (HW_ENET_PALR(x).U)
-#define HW_ENET_PALR_WR(x, v) (HW_ENET_PALR(x).U = (v))
-#define HW_ENET_PALR_SET(x, v) (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) | (v)))
-#define HW_ENET_PALR_CLR(x, v) (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) & ~(v)))
-#define HW_ENET_PALR_TOG(x, v) (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_PALR bitfields
- */
-
-/*!
- * @name Register ENET_PALR, field PADDR1[31:0] (RW)
- *
- * Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the
- * 6-byte individual address are used for exact match and the source address
- * field in PAUSE frames.
- */
-//@{
-#define BP_ENET_PALR_PADDR1 (0U) //!< Bit position for ENET_PALR_PADDR1.
-#define BM_ENET_PALR_PADDR1 (0xFFFFFFFFU) //!< Bit mask for ENET_PALR_PADDR1.
-#define BS_ENET_PALR_PADDR1 (32U) //!< Bit field size in bits for ENET_PALR_PADDR1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_PALR_PADDR1 field.
-#define BR_ENET_PALR_PADDR1(x) (HW_ENET_PALR(x).U)
-#endif
-
-//! @brief Format value for bitfield ENET_PALR_PADDR1.
-#define BF_ENET_PALR_PADDR1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_PALR_PADDR1), uint32_t) & BM_ENET_PALR_PADDR1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PADDR1 field to a new value.
-#define BW_ENET_PALR_PADDR1(x, v) (HW_ENET_PALR_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_PAUR - Physical Address Upper Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_PAUR - Physical Address Upper Register (RW)
- *
- * Reset value: 0x00008808U
- *
- * PAUR contains the upper 16 bits (bytes 4 and 5) of the 48-bit address used in
- * the address recognition process to compare with the destination address (DA)
- * field of receive frames with an individual DA. In addition, this register is
- * used in bytes 4 and 5 of the six-byte source address field when transmitting
- * PAUSE frames. Bits 15:0 of PAUR contain a constant type field (0x8808) for
- * transmission of PAUSE frames. The upper 16 bits of this register are not reset and
- * you must initialize it.
- */
-typedef union _hw_enet_paur
-{
- uint32_t U;
- struct _hw_enet_paur_bitfields
- {
- uint32_t TYPE : 16; //!< [15:0] Type Field In PAUSE Frames
- uint32_t PADDR2 : 16; //!< [31:16]
- } B;
-} hw_enet_paur_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_PAUR register
- */
-//@{
-#define HW_ENET_PAUR_ADDR(x) (REGS_ENET_BASE(x) + 0xE8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_PAUR(x) (*(__IO hw_enet_paur_t *) HW_ENET_PAUR_ADDR(x))
-#define HW_ENET_PAUR_RD(x) (HW_ENET_PAUR(x).U)
-#define HW_ENET_PAUR_WR(x, v) (HW_ENET_PAUR(x).U = (v))
-#define HW_ENET_PAUR_SET(x, v) (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) | (v)))
-#define HW_ENET_PAUR_CLR(x, v) (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) & ~(v)))
-#define HW_ENET_PAUR_TOG(x, v) (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_PAUR bitfields
- */
-
-/*!
- * @name Register ENET_PAUR, field TYPE[15:0] (RO)
- *
- * These fields have a constant value of 0x8808.
- */
-//@{
-#define BP_ENET_PAUR_TYPE (0U) //!< Bit position for ENET_PAUR_TYPE.
-#define BM_ENET_PAUR_TYPE (0x0000FFFFU) //!< Bit mask for ENET_PAUR_TYPE.
-#define BS_ENET_PAUR_TYPE (16U) //!< Bit field size in bits for ENET_PAUR_TYPE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_PAUR_TYPE field.
-#define BR_ENET_PAUR_TYPE(x) (HW_ENET_PAUR(x).B.TYPE)
-#endif
-//@}
-
-/*!
- * @name Register ENET_PAUR, field PADDR2[31:16] (RW)
- *
- * Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used
- * for exact match, and the source address field in PAUSE frames.
- */
-//@{
-#define BP_ENET_PAUR_PADDR2 (16U) //!< Bit position for ENET_PAUR_PADDR2.
-#define BM_ENET_PAUR_PADDR2 (0xFFFF0000U) //!< Bit mask for ENET_PAUR_PADDR2.
-#define BS_ENET_PAUR_PADDR2 (16U) //!< Bit field size in bits for ENET_PAUR_PADDR2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_PAUR_PADDR2 field.
-#define BR_ENET_PAUR_PADDR2(x) (HW_ENET_PAUR(x).B.PADDR2)
-#endif
-
-//! @brief Format value for bitfield ENET_PAUR_PADDR2.
-#define BF_ENET_PAUR_PADDR2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_PAUR_PADDR2), uint32_t) & BM_ENET_PAUR_PADDR2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PADDR2 field to a new value.
-#define BW_ENET_PAUR_PADDR2(x, v) (HW_ENET_PAUR_WR(x, (HW_ENET_PAUR_RD(x) & ~BM_ENET_PAUR_PADDR2) | BF_ENET_PAUR_PADDR2(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_OPD - Opcode/Pause Duration Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_OPD - Opcode/Pause Duration Register (RW)
- *
- * Reset value: 0x00010000U
- *
- * OPD is read/write accessible. This register contains the 16-bit opcode and
- * 16-bit pause duration fields used in transmission of a PAUSE frame. The opcode
- * field is a constant value, 0x0001. When another node detects a PAUSE frame,
- * that node pauses transmission for the duration specified in the pause duration
- * field. The lower 16 bits of this register are not reset and you must initialize
- * it.
- */
-typedef union _hw_enet_opd
-{
- uint32_t U;
- struct _hw_enet_opd_bitfields
- {
- uint32_t PAUSE_DUR : 16; //!< [15:0] Pause Duration
- uint32_t OPCODE : 16; //!< [31:16] Opcode Field In PAUSE Frames
- } B;
-} hw_enet_opd_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_OPD register
- */
-//@{
-#define HW_ENET_OPD_ADDR(x) (REGS_ENET_BASE(x) + 0xECU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_OPD(x) (*(__IO hw_enet_opd_t *) HW_ENET_OPD_ADDR(x))
-#define HW_ENET_OPD_RD(x) (HW_ENET_OPD(x).U)
-#define HW_ENET_OPD_WR(x, v) (HW_ENET_OPD(x).U = (v))
-#define HW_ENET_OPD_SET(x, v) (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) | (v)))
-#define HW_ENET_OPD_CLR(x, v) (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) & ~(v)))
-#define HW_ENET_OPD_TOG(x, v) (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_OPD bitfields
- */
-
-/*!
- * @name Register ENET_OPD, field PAUSE_DUR[15:0] (RW)
- *
- * Pause duration field used in PAUSE frames.
- */
-//@{
-#define BP_ENET_OPD_PAUSE_DUR (0U) //!< Bit position for ENET_OPD_PAUSE_DUR.
-#define BM_ENET_OPD_PAUSE_DUR (0x0000FFFFU) //!< Bit mask for ENET_OPD_PAUSE_DUR.
-#define BS_ENET_OPD_PAUSE_DUR (16U) //!< Bit field size in bits for ENET_OPD_PAUSE_DUR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_OPD_PAUSE_DUR field.
-#define BR_ENET_OPD_PAUSE_DUR(x) (HW_ENET_OPD(x).B.PAUSE_DUR)
-#endif
-
-//! @brief Format value for bitfield ENET_OPD_PAUSE_DUR.
-#define BF_ENET_OPD_PAUSE_DUR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_OPD_PAUSE_DUR), uint32_t) & BM_ENET_OPD_PAUSE_DUR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PAUSE_DUR field to a new value.
-#define BW_ENET_OPD_PAUSE_DUR(x, v) (HW_ENET_OPD_WR(x, (HW_ENET_OPD_RD(x) & ~BM_ENET_OPD_PAUSE_DUR) | BF_ENET_OPD_PAUSE_DUR(v)))
-#endif
-//@}
-
-/*!
- * @name Register ENET_OPD, field OPCODE[31:16] (RO)
- *
- * These fields have a constant value of 0x0001.
- */
-//@{
-#define BP_ENET_OPD_OPCODE (16U) //!< Bit position for ENET_OPD_OPCODE.
-#define BM_ENET_OPD_OPCODE (0xFFFF0000U) //!< Bit mask for ENET_OPD_OPCODE.
-#define BS_ENET_OPD_OPCODE (16U) //!< Bit field size in bits for ENET_OPD_OPCODE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_OPD_OPCODE field.
-#define BR_ENET_OPD_OPCODE(x) (HW_ENET_OPD(x).B.OPCODE)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_IAUR - Descriptor Individual Upper Address Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_IAUR - Descriptor Individual Upper Address Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * IAUR contains the upper 32 bits of the 64-bit individual address hash table.
- * The address recognition process uses this table to check for a possible match
- * with the destination address (DA) field of receive frames with an individual
- * DA. This register is not reset and you must initialize it.
- */
-typedef union _hw_enet_iaur
-{
- uint32_t U;
- struct _hw_enet_iaur_bitfields
- {
- uint32_t IADDR1 : 32; //!< [31:0]
- } B;
-} hw_enet_iaur_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_IAUR register
- */
-//@{
-#define HW_ENET_IAUR_ADDR(x) (REGS_ENET_BASE(x) + 0x118U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_IAUR(x) (*(__IO hw_enet_iaur_t *) HW_ENET_IAUR_ADDR(x))
-#define HW_ENET_IAUR_RD(x) (HW_ENET_IAUR(x).U)
-#define HW_ENET_IAUR_WR(x, v) (HW_ENET_IAUR(x).U = (v))
-#define HW_ENET_IAUR_SET(x, v) (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) | (v)))
-#define HW_ENET_IAUR_CLR(x, v) (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) & ~(v)))
-#define HW_ENET_IAUR_TOG(x, v) (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_IAUR bitfields
- */
-
-/*!
- * @name Register ENET_IAUR, field IADDR1[31:0] (RW)
- *
- * Contains the upper 32 bits of the 64-bit hash table used in the address
- * recognition process for receive frames with a unicast address. Bit 31 of IADDR1
- * contains hash index bit 63. Bit 0 of IADDR1 contains hash index bit 32.
- */
-//@{
-#define BP_ENET_IAUR_IADDR1 (0U) //!< Bit position for ENET_IAUR_IADDR1.
-#define BM_ENET_IAUR_IADDR1 (0xFFFFFFFFU) //!< Bit mask for ENET_IAUR_IADDR1.
-#define BS_ENET_IAUR_IADDR1 (32U) //!< Bit field size in bits for ENET_IAUR_IADDR1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_IAUR_IADDR1 field.
-#define BR_ENET_IAUR_IADDR1(x) (HW_ENET_IAUR(x).U)
-#endif
-
-//! @brief Format value for bitfield ENET_IAUR_IADDR1.
-#define BF_ENET_IAUR_IADDR1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_IAUR_IADDR1), uint32_t) & BM_ENET_IAUR_IADDR1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IADDR1 field to a new value.
-#define BW_ENET_IAUR_IADDR1(x, v) (HW_ENET_IAUR_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_IALR - Descriptor Individual Lower Address Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_IALR - Descriptor Individual Lower Address Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * IALR contains the lower 32 bits of the 64-bit individual address hash table.
- * The address recognition process uses this table to check for a possible match
- * with the DA field of receive frames with an individual DA. This register is
- * not reset and you must initialize it.
- */
-typedef union _hw_enet_ialr
-{
- uint32_t U;
- struct _hw_enet_ialr_bitfields
- {
- uint32_t IADDR2 : 32; //!< [31:0]
- } B;
-} hw_enet_ialr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_IALR register
- */
-//@{
-#define HW_ENET_IALR_ADDR(x) (REGS_ENET_BASE(x) + 0x11CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_IALR(x) (*(__IO hw_enet_ialr_t *) HW_ENET_IALR_ADDR(x))
-#define HW_ENET_IALR_RD(x) (HW_ENET_IALR(x).U)
-#define HW_ENET_IALR_WR(x, v) (HW_ENET_IALR(x).U = (v))
-#define HW_ENET_IALR_SET(x, v) (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) | (v)))
-#define HW_ENET_IALR_CLR(x, v) (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) & ~(v)))
-#define HW_ENET_IALR_TOG(x, v) (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_IALR bitfields
- */
-
-/*!
- * @name Register ENET_IALR, field IADDR2[31:0] (RW)
- *
- * Contains the lower 32 bits of the 64-bit hash table used in the address
- * recognition process for receive frames with a unicast address. Bit 31 of IADDR2
- * contains hash index bit 31. Bit 0 of IADDR2 contains hash index bit 0.
- */
-//@{
-#define BP_ENET_IALR_IADDR2 (0U) //!< Bit position for ENET_IALR_IADDR2.
-#define BM_ENET_IALR_IADDR2 (0xFFFFFFFFU) //!< Bit mask for ENET_IALR_IADDR2.
-#define BS_ENET_IALR_IADDR2 (32U) //!< Bit field size in bits for ENET_IALR_IADDR2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_IALR_IADDR2 field.
-#define BR_ENET_IALR_IADDR2(x) (HW_ENET_IALR(x).U)
-#endif
-
-//! @brief Format value for bitfield ENET_IALR_IADDR2.
-#define BF_ENET_IALR_IADDR2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_IALR_IADDR2), uint32_t) & BM_ENET_IALR_IADDR2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IADDR2 field to a new value.
-#define BW_ENET_IALR_IADDR2(x, v) (HW_ENET_IALR_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_GAUR - Descriptor Group Upper Address Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_GAUR - Descriptor Group Upper Address Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * GAUR contains the upper 32 bits of the 64-bit hash table used in the address
- * recognition process for receive frames with a multicast address. You must
- * initialize this register.
- */
-typedef union _hw_enet_gaur
-{
- uint32_t U;
- struct _hw_enet_gaur_bitfields
- {
- uint32_t GADDR1 : 32; //!< [31:0]
- } B;
-} hw_enet_gaur_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_GAUR register
- */
-//@{
-#define HW_ENET_GAUR_ADDR(x) (REGS_ENET_BASE(x) + 0x120U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_GAUR(x) (*(__IO hw_enet_gaur_t *) HW_ENET_GAUR_ADDR(x))
-#define HW_ENET_GAUR_RD(x) (HW_ENET_GAUR(x).U)
-#define HW_ENET_GAUR_WR(x, v) (HW_ENET_GAUR(x).U = (v))
-#define HW_ENET_GAUR_SET(x, v) (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) | (v)))
-#define HW_ENET_GAUR_CLR(x, v) (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) & ~(v)))
-#define HW_ENET_GAUR_TOG(x, v) (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_GAUR bitfields
- */
-
-/*!
- * @name Register ENET_GAUR, field GADDR1[31:0] (RW)
- *
- * Contains the upper 32 bits of the 64-bit hash table used in the address
- * recognition process for receive frames with a multicast address. Bit 31 of GADDR1
- * contains hash index bit 63. Bit 0 of GADDR1 contains hash index bit 32.
- */
-//@{
-#define BP_ENET_GAUR_GADDR1 (0U) //!< Bit position for ENET_GAUR_GADDR1.
-#define BM_ENET_GAUR_GADDR1 (0xFFFFFFFFU) //!< Bit mask for ENET_GAUR_GADDR1.
-#define BS_ENET_GAUR_GADDR1 (32U) //!< Bit field size in bits for ENET_GAUR_GADDR1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_GAUR_GADDR1 field.
-#define BR_ENET_GAUR_GADDR1(x) (HW_ENET_GAUR(x).U)
-#endif
-
-//! @brief Format value for bitfield ENET_GAUR_GADDR1.
-#define BF_ENET_GAUR_GADDR1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_GAUR_GADDR1), uint32_t) & BM_ENET_GAUR_GADDR1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the GADDR1 field to a new value.
-#define BW_ENET_GAUR_GADDR1(x, v) (HW_ENET_GAUR_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_GALR - Descriptor Group Lower Address Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_GALR - Descriptor Group Lower Address Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * GALR contains the lower 32 bits of the 64-bit hash table used in the address
- * recognition process for receive frames with a multicast address. You must
- * initialize this register.
- */
-typedef union _hw_enet_galr
-{
- uint32_t U;
- struct _hw_enet_galr_bitfields
- {
- uint32_t GADDR2 : 32; //!< [31:0]
- } B;
-} hw_enet_galr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_GALR register
- */
-//@{
-#define HW_ENET_GALR_ADDR(x) (REGS_ENET_BASE(x) + 0x124U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_GALR(x) (*(__IO hw_enet_galr_t *) HW_ENET_GALR_ADDR(x))
-#define HW_ENET_GALR_RD(x) (HW_ENET_GALR(x).U)
-#define HW_ENET_GALR_WR(x, v) (HW_ENET_GALR(x).U = (v))
-#define HW_ENET_GALR_SET(x, v) (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) | (v)))
-#define HW_ENET_GALR_CLR(x, v) (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) & ~(v)))
-#define HW_ENET_GALR_TOG(x, v) (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_GALR bitfields
- */
-
-/*!
- * @name Register ENET_GALR, field GADDR2[31:0] (RW)
- *
- * Contains the lower 32 bits of the 64-bit hash table used in the address
- * recognition process for receive frames with a multicast address. Bit 31 of GADDR2
- * contains hash index bit 31. Bit 0 of GADDR2 contains hash index bit 0.
- */
-//@{
-#define BP_ENET_GALR_GADDR2 (0U) //!< Bit position for ENET_GALR_GADDR2.
-#define BM_ENET_GALR_GADDR2 (0xFFFFFFFFU) //!< Bit mask for ENET_GALR_GADDR2.
-#define BS_ENET_GALR_GADDR2 (32U) //!< Bit field size in bits for ENET_GALR_GADDR2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_GALR_GADDR2 field.
-#define BR_ENET_GALR_GADDR2(x) (HW_ENET_GALR(x).U)
-#endif
-
-//! @brief Format value for bitfield ENET_GALR_GADDR2.
-#define BF_ENET_GALR_GADDR2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_GALR_GADDR2), uint32_t) & BM_ENET_GALR_GADDR2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the GADDR2 field to a new value.
-#define BW_ENET_GALR_GADDR2(x, v) (HW_ENET_GALR_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_TFWR - Transmit FIFO Watermark Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_TFWR - Transmit FIFO Watermark Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * If TFWR[STRFWD] is cleared, TFWR[TFWR] controls the amount of data required
- * in the transmit FIFO before transmission of a frame can begin. This allows you
- * to minimize transmit latency (TFWR = 00 or 01) or allow for larger bus access
- * latency (TFWR = 11) due to contention for the system bus. Setting the
- * watermark to a high value minimizes the risk of transmit FIFO underrun due to
- * contention for the system bus. The byte counts associated with the TFWR field may need
- * to be modified to match a given system requirement. For example, worst case
- * bus access latency by the transmit data DMA channel. When the FIFO level
- * reaches the value the TFWR field and when the STR_FWD is set to '0', the MAC
- * transmit control logic starts frame transmission even before the end-of-frame is
- * available in the FIFO (cut-through operation). If a complete frame has a size
- * smaller than the threshold programmed with TFWR, the MAC also transmits the Frame
- * to the line. To enable store and forward on the Transmit path, set STR_FWD to
- * '1'. In this case, the MAC starts to transmit data only when a complete frame
- * is stored in the Transmit FIFO.
- */
-typedef union _hw_enet_tfwr
-{
- uint32_t U;
- struct _hw_enet_tfwr_bitfields
- {
- uint32_t TFWR : 6; //!< [5:0] Transmit FIFO Write
- uint32_t RESERVED0 : 2; //!< [7:6]
- uint32_t STRFWD : 1; //!< [8] Store And Forward Enable
- uint32_t RESERVED1 : 23; //!< [31:9]
- } B;
-} hw_enet_tfwr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_TFWR register
- */
-//@{
-#define HW_ENET_TFWR_ADDR(x) (REGS_ENET_BASE(x) + 0x144U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_TFWR(x) (*(__IO hw_enet_tfwr_t *) HW_ENET_TFWR_ADDR(x))
-#define HW_ENET_TFWR_RD(x) (HW_ENET_TFWR(x).U)
-#define HW_ENET_TFWR_WR(x, v) (HW_ENET_TFWR(x).U = (v))
-#define HW_ENET_TFWR_SET(x, v) (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) | (v)))
-#define HW_ENET_TFWR_CLR(x, v) (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) & ~(v)))
-#define HW_ENET_TFWR_TOG(x, v) (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_TFWR bitfields
- */
-
-/*!
- * @name Register ENET_TFWR, field TFWR[5:0] (RW)
- *
- * If TFWR[STRFWD] is cleared, this field indicates the number of bytes, in
- * steps of 64 bytes, written to the transmit FIFO before transmission of a frame
- * begins. If a frame with less than the threshold is written, it is still sent
- * independently of this threshold setting. The threshold is relevant only if the
- * frame is larger than the threshold given. This chip may not support the maximum
- * number of bytes written shown below. See the chip-specific information for the
- * ENET module for this value.
- *
- * Values:
- * - 000000 - 64 bytes written.
- * - 000001 - 64 bytes written.
- * - 000010 - 128 bytes written.
- * - 000011 - 192 bytes written.
- * - 111110 - 3968 bytes written.
- * - 111111 - 4032 bytes written.
- */
-//@{
-#define BP_ENET_TFWR_TFWR (0U) //!< Bit position for ENET_TFWR_TFWR.
-#define BM_ENET_TFWR_TFWR (0x0000003FU) //!< Bit mask for ENET_TFWR_TFWR.
-#define BS_ENET_TFWR_TFWR (6U) //!< Bit field size in bits for ENET_TFWR_TFWR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_TFWR_TFWR field.
-#define BR_ENET_TFWR_TFWR(x) (HW_ENET_TFWR(x).B.TFWR)
-#endif
-
-//! @brief Format value for bitfield ENET_TFWR_TFWR.
-#define BF_ENET_TFWR_TFWR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TFWR_TFWR), uint32_t) & BM_ENET_TFWR_TFWR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TFWR field to a new value.
-#define BW_ENET_TFWR_TFWR(x, v) (HW_ENET_TFWR_WR(x, (HW_ENET_TFWR_RD(x) & ~BM_ENET_TFWR_TFWR) | BF_ENET_TFWR_TFWR(v)))
-#endif
-//@}
-
-/*!
- * @name Register ENET_TFWR, field STRFWD[8] (RW)
- *
- * Values:
- * - 0 - Reset. The transmission start threshold is programmed in TFWR[TFWR].
- * - 1 - Enabled.
- */
-//@{
-#define BP_ENET_TFWR_STRFWD (8U) //!< Bit position for ENET_TFWR_STRFWD.
-#define BM_ENET_TFWR_STRFWD (0x00000100U) //!< Bit mask for ENET_TFWR_STRFWD.
-#define BS_ENET_TFWR_STRFWD (1U) //!< Bit field size in bits for ENET_TFWR_STRFWD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_TFWR_STRFWD field.
-#define BR_ENET_TFWR_STRFWD(x) (BITBAND_ACCESS32(HW_ENET_TFWR_ADDR(x), BP_ENET_TFWR_STRFWD))
-#endif
-
-//! @brief Format value for bitfield ENET_TFWR_STRFWD.
-#define BF_ENET_TFWR_STRFWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TFWR_STRFWD), uint32_t) & BM_ENET_TFWR_STRFWD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the STRFWD field to a new value.
-#define BW_ENET_TFWR_STRFWD(x, v) (BITBAND_ACCESS32(HW_ENET_TFWR_ADDR(x), BP_ENET_TFWR_STRFWD) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RDSR - Receive Descriptor Ring Start Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RDSR - Receive Descriptor Ring Start Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * RDSR points to the beginning of the circular receive buffer descriptor queue
- * in external memory. This pointer must be 64-bit aligned (bits 2-0 must be
- * zero); however, it is recommended to be 128-bit aligned, that is, evenly divisible
- * by 16. This register must be initialized prior to operation
- */
-typedef union _hw_enet_rdsr
-{
- uint32_t U;
- struct _hw_enet_rdsr_bitfields
- {
- uint32_t RESERVED0 : 3; //!< [2:0]
- uint32_t R_DES_START : 29; //!< [31:3]
- } B;
-} hw_enet_rdsr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RDSR register
- */
-//@{
-#define HW_ENET_RDSR_ADDR(x) (REGS_ENET_BASE(x) + 0x180U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RDSR(x) (*(__IO hw_enet_rdsr_t *) HW_ENET_RDSR_ADDR(x))
-#define HW_ENET_RDSR_RD(x) (HW_ENET_RDSR(x).U)
-#define HW_ENET_RDSR_WR(x, v) (HW_ENET_RDSR(x).U = (v))
-#define HW_ENET_RDSR_SET(x, v) (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) | (v)))
-#define HW_ENET_RDSR_CLR(x, v) (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) & ~(v)))
-#define HW_ENET_RDSR_TOG(x, v) (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RDSR bitfields
- */
-
-/*!
- * @name Register ENET_RDSR, field R_DES_START[31:3] (RW)
- *
- * Pointer to the beginning of the receive buffer descriptor queue.
- */
-//@{
-#define BP_ENET_RDSR_R_DES_START (3U) //!< Bit position for ENET_RDSR_R_DES_START.
-#define BM_ENET_RDSR_R_DES_START (0xFFFFFFF8U) //!< Bit mask for ENET_RDSR_R_DES_START.
-#define BS_ENET_RDSR_R_DES_START (29U) //!< Bit field size in bits for ENET_RDSR_R_DES_START.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RDSR_R_DES_START field.
-#define BR_ENET_RDSR_R_DES_START(x) (HW_ENET_RDSR(x).B.R_DES_START)
-#endif
-
-//! @brief Format value for bitfield ENET_RDSR_R_DES_START.
-#define BF_ENET_RDSR_R_DES_START(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RDSR_R_DES_START), uint32_t) & BM_ENET_RDSR_R_DES_START)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the R_DES_START field to a new value.
-#define BW_ENET_RDSR_R_DES_START(x, v) (HW_ENET_RDSR_WR(x, (HW_ENET_RDSR_RD(x) & ~BM_ENET_RDSR_R_DES_START) | BF_ENET_RDSR_R_DES_START(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * TDSR provides a pointer to the beginning of the circular transmit buffer
- * descriptor queue in external memory. This pointer must be 64-bit aligned (bits 2-0
- * must be zero); however, it is recommended to be 128-bit aligned, that is,
- * evenly divisible by 16. This register must be initialized prior to operation.
- */
-typedef union _hw_enet_tdsr
-{
- uint32_t U;
- struct _hw_enet_tdsr_bitfields
- {
- uint32_t RESERVED0 : 3; //!< [2:0]
- uint32_t X_DES_START : 29; //!< [31:3]
- } B;
-} hw_enet_tdsr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_TDSR register
- */
-//@{
-#define HW_ENET_TDSR_ADDR(x) (REGS_ENET_BASE(x) + 0x184U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_TDSR(x) (*(__IO hw_enet_tdsr_t *) HW_ENET_TDSR_ADDR(x))
-#define HW_ENET_TDSR_RD(x) (HW_ENET_TDSR(x).U)
-#define HW_ENET_TDSR_WR(x, v) (HW_ENET_TDSR(x).U = (v))
-#define HW_ENET_TDSR_SET(x, v) (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) | (v)))
-#define HW_ENET_TDSR_CLR(x, v) (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) & ~(v)))
-#define HW_ENET_TDSR_TOG(x, v) (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_TDSR bitfields
- */
-
-/*!
- * @name Register ENET_TDSR, field X_DES_START[31:3] (RW)
- *
- * Pointer to the beginning of the transmit buffer descriptor queue.
- */
-//@{
-#define BP_ENET_TDSR_X_DES_START (3U) //!< Bit position for ENET_TDSR_X_DES_START.
-#define BM_ENET_TDSR_X_DES_START (0xFFFFFFF8U) //!< Bit mask for ENET_TDSR_X_DES_START.
-#define BS_ENET_TDSR_X_DES_START (29U) //!< Bit field size in bits for ENET_TDSR_X_DES_START.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_TDSR_X_DES_START field.
-#define BR_ENET_TDSR_X_DES_START(x) (HW_ENET_TDSR(x).B.X_DES_START)
-#endif
-
-//! @brief Format value for bitfield ENET_TDSR_X_DES_START.
-#define BF_ENET_TDSR_X_DES_START(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TDSR_X_DES_START), uint32_t) & BM_ENET_TDSR_X_DES_START)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the X_DES_START field to a new value.
-#define BW_ENET_TDSR_X_DES_START(x, v) (HW_ENET_TDSR_WR(x, (HW_ENET_TDSR_RD(x) & ~BM_ENET_TDSR_X_DES_START) | BF_ENET_TDSR_X_DES_START(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_MRBR - Maximum Receive Buffer Size Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_MRBR - Maximum Receive Buffer Size Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * The MRBR is a user-programmable register that dictates the maximum size of
- * all receive buffers. This value should take into consideration that the receive
- * CRC is always written into the last receive buffer. To allow one maximum size
- * frame per buffer, MRBR must be set to RCR[MAX_FL] or larger. To properly align
- * the buffer, MRBR must be evenly divisible by 16. To ensure this, bits 3-0 are
- * set to zero by the device. To minimize bus usage (descriptor fetches), set
- * MRBR greater than or equal to 256 bytes. This register must be initialized
- * before operation.
- */
-typedef union _hw_enet_mrbr
-{
- uint32_t U;
- struct _hw_enet_mrbr_bitfields
- {
- uint32_t RESERVED0 : 4; //!< [3:0]
- uint32_t R_BUF_SIZE : 10; //!< [13:4]
- uint32_t RESERVED1 : 18; //!< [31:14]
- } B;
-} hw_enet_mrbr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_MRBR register
- */
-//@{
-#define HW_ENET_MRBR_ADDR(x) (REGS_ENET_BASE(x) + 0x188U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_MRBR(x) (*(__IO hw_enet_mrbr_t *) HW_ENET_MRBR_ADDR(x))
-#define HW_ENET_MRBR_RD(x) (HW_ENET_MRBR(x).U)
-#define HW_ENET_MRBR_WR(x, v) (HW_ENET_MRBR(x).U = (v))
-#define HW_ENET_MRBR_SET(x, v) (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) | (v)))
-#define HW_ENET_MRBR_CLR(x, v) (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) & ~(v)))
-#define HW_ENET_MRBR_TOG(x, v) (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_MRBR bitfields
- */
-
-/*!
- * @name Register ENET_MRBR, field R_BUF_SIZE[13:4] (RW)
- *
- * Receive buffer size in bytes.
- */
-//@{
-#define BP_ENET_MRBR_R_BUF_SIZE (4U) //!< Bit position for ENET_MRBR_R_BUF_SIZE.
-#define BM_ENET_MRBR_R_BUF_SIZE (0x00003FF0U) //!< Bit mask for ENET_MRBR_R_BUF_SIZE.
-#define BS_ENET_MRBR_R_BUF_SIZE (10U) //!< Bit field size in bits for ENET_MRBR_R_BUF_SIZE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_MRBR_R_BUF_SIZE field.
-#define BR_ENET_MRBR_R_BUF_SIZE(x) (HW_ENET_MRBR(x).B.R_BUF_SIZE)
-#endif
-
-//! @brief Format value for bitfield ENET_MRBR_R_BUF_SIZE.
-#define BF_ENET_MRBR_R_BUF_SIZE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MRBR_R_BUF_SIZE), uint32_t) & BM_ENET_MRBR_R_BUF_SIZE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the R_BUF_SIZE field to a new value.
-#define BW_ENET_MRBR_R_BUF_SIZE(x, v) (HW_ENET_MRBR_WR(x, (HW_ENET_MRBR_RD(x) & ~BM_ENET_MRBR_R_BUF_SIZE) | BF_ENET_MRBR_R_BUF_SIZE(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RSFL - Receive FIFO Section Full Threshold
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RSFL - Receive FIFO Section Full Threshold (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rsfl
-{
- uint32_t U;
- struct _hw_enet_rsfl_bitfields
- {
- uint32_t RX_SECTION_FULL : 8; //!< [7:0] Value Of Receive FIFO
- //! Section Full Threshold
- uint32_t RESERVED0 : 24; //!< [31:8]
- } B;
-} hw_enet_rsfl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RSFL register
- */
-//@{
-#define HW_ENET_RSFL_ADDR(x) (REGS_ENET_BASE(x) + 0x190U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RSFL(x) (*(__IO hw_enet_rsfl_t *) HW_ENET_RSFL_ADDR(x))
-#define HW_ENET_RSFL_RD(x) (HW_ENET_RSFL(x).U)
-#define HW_ENET_RSFL_WR(x, v) (HW_ENET_RSFL(x).U = (v))
-#define HW_ENET_RSFL_SET(x, v) (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) | (v)))
-#define HW_ENET_RSFL_CLR(x, v) (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) & ~(v)))
-#define HW_ENET_RSFL_TOG(x, v) (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RSFL bitfields
- */
-
-/*!
- * @name Register ENET_RSFL, field RX_SECTION_FULL[7:0] (RW)
- *
- * Value, in 64-bit words, of the receive FIFO section full threshold. Clear
- * this field to enable store and forward on the RX FIFO. When programming a value
- * greater than 0 (cut-through operation), it must be greater than
- * RAEM[RX_ALMOST_EMPTY]. When the FIFO level reaches the value in this field, data is available
- * in the Receive FIFO (cut-through operation).
- */
-//@{
-#define BP_ENET_RSFL_RX_SECTION_FULL (0U) //!< Bit position for ENET_RSFL_RX_SECTION_FULL.
-#define BM_ENET_RSFL_RX_SECTION_FULL (0x000000FFU) //!< Bit mask for ENET_RSFL_RX_SECTION_FULL.
-#define BS_ENET_RSFL_RX_SECTION_FULL (8U) //!< Bit field size in bits for ENET_RSFL_RX_SECTION_FULL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RSFL_RX_SECTION_FULL field.
-#define BR_ENET_RSFL_RX_SECTION_FULL(x) (HW_ENET_RSFL(x).B.RX_SECTION_FULL)
-#endif
-
-//! @brief Format value for bitfield ENET_RSFL_RX_SECTION_FULL.
-#define BF_ENET_RSFL_RX_SECTION_FULL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RSFL_RX_SECTION_FULL), uint32_t) & BM_ENET_RSFL_RX_SECTION_FULL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RX_SECTION_FULL field to a new value.
-#define BW_ENET_RSFL_RX_SECTION_FULL(x, v) (HW_ENET_RSFL_WR(x, (HW_ENET_RSFL_RD(x) & ~BM_ENET_RSFL_RX_SECTION_FULL) | BF_ENET_RSFL_RX_SECTION_FULL(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RSEM - Receive FIFO Section Empty Threshold
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RSEM - Receive FIFO Section Empty Threshold (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rsem
-{
- uint32_t U;
- struct _hw_enet_rsem_bitfields
- {
- uint32_t RX_SECTION_EMPTY : 8; //!< [7:0] Value Of The Receive FIFO
- //! Section Empty Threshold
- uint32_t RESERVED0 : 8; //!< [15:8]
- uint32_t STAT_SECTION_EMPTY : 5; //!< [20:16] RX Status FIFO Section
- //! Empty Threshold
- uint32_t RESERVED1 : 11; //!< [31:21]
- } B;
-} hw_enet_rsem_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RSEM register
- */
-//@{
-#define HW_ENET_RSEM_ADDR(x) (REGS_ENET_BASE(x) + 0x194U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RSEM(x) (*(__IO hw_enet_rsem_t *) HW_ENET_RSEM_ADDR(x))
-#define HW_ENET_RSEM_RD(x) (HW_ENET_RSEM(x).U)
-#define HW_ENET_RSEM_WR(x, v) (HW_ENET_RSEM(x).U = (v))
-#define HW_ENET_RSEM_SET(x, v) (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) | (v)))
-#define HW_ENET_RSEM_CLR(x, v) (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) & ~(v)))
-#define HW_ENET_RSEM_TOG(x, v) (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RSEM bitfields
- */
-
-/*!
- * @name Register ENET_RSEM, field RX_SECTION_EMPTY[7:0] (RW)
- *
- * Value, in 64-bit words, of the receive FIFO section empty threshold. When the
- * FIFO has reached this level, a pause frame will be issued. A value of 0
- * disables automatic pause frame generation. When the FIFO level goes below the value
- * programmed in this field, an XON pause frame is issued to indicate the FIFO
- * congestion is cleared to the remote Ethernet client. The section-empty
- * threshold indications from both FIFOs are OR'ed to cause XOFF pause frame generation.
- */
-//@{
-#define BP_ENET_RSEM_RX_SECTION_EMPTY (0U) //!< Bit position for ENET_RSEM_RX_SECTION_EMPTY.
-#define BM_ENET_RSEM_RX_SECTION_EMPTY (0x000000FFU) //!< Bit mask for ENET_RSEM_RX_SECTION_EMPTY.
-#define BS_ENET_RSEM_RX_SECTION_EMPTY (8U) //!< Bit field size in bits for ENET_RSEM_RX_SECTION_EMPTY.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RSEM_RX_SECTION_EMPTY field.
-#define BR_ENET_RSEM_RX_SECTION_EMPTY(x) (HW_ENET_RSEM(x).B.RX_SECTION_EMPTY)
-#endif
-
-//! @brief Format value for bitfield ENET_RSEM_RX_SECTION_EMPTY.
-#define BF_ENET_RSEM_RX_SECTION_EMPTY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RSEM_RX_SECTION_EMPTY), uint32_t) & BM_ENET_RSEM_RX_SECTION_EMPTY)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RX_SECTION_EMPTY field to a new value.
-#define BW_ENET_RSEM_RX_SECTION_EMPTY(x, v) (HW_ENET_RSEM_WR(x, (HW_ENET_RSEM_RD(x) & ~BM_ENET_RSEM_RX_SECTION_EMPTY) | BF_ENET_RSEM_RX_SECTION_EMPTY(v)))
-#endif
-//@}
-
-/*!
- * @name Register ENET_RSEM, field STAT_SECTION_EMPTY[20:16] (RW)
- *
- * Defines number of frames in the receive FIFO, independent of its size, that
- * can be accepted. If the limit is reached, reception will continue normally,
- * however a pause frame will be triggered to indicate a possible congestion to the
- * remote device to avoid FIFO overflow. A value of 0 disables automatic pause
- * frame generation
- */
-//@{
-#define BP_ENET_RSEM_STAT_SECTION_EMPTY (16U) //!< Bit position for ENET_RSEM_STAT_SECTION_EMPTY.
-#define BM_ENET_RSEM_STAT_SECTION_EMPTY (0x001F0000U) //!< Bit mask for ENET_RSEM_STAT_SECTION_EMPTY.
-#define BS_ENET_RSEM_STAT_SECTION_EMPTY (5U) //!< Bit field size in bits for ENET_RSEM_STAT_SECTION_EMPTY.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RSEM_STAT_SECTION_EMPTY field.
-#define BR_ENET_RSEM_STAT_SECTION_EMPTY(x) (HW_ENET_RSEM(x).B.STAT_SECTION_EMPTY)
-#endif
-
-//! @brief Format value for bitfield ENET_RSEM_STAT_SECTION_EMPTY.
-#define BF_ENET_RSEM_STAT_SECTION_EMPTY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RSEM_STAT_SECTION_EMPTY), uint32_t) & BM_ENET_RSEM_STAT_SECTION_EMPTY)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the STAT_SECTION_EMPTY field to a new value.
-#define BW_ENET_RSEM_STAT_SECTION_EMPTY(x, v) (HW_ENET_RSEM_WR(x, (HW_ENET_RSEM_RD(x) & ~BM_ENET_RSEM_STAT_SECTION_EMPTY) | BF_ENET_RSEM_STAT_SECTION_EMPTY(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RAEM - Receive FIFO Almost Empty Threshold
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RAEM - Receive FIFO Almost Empty Threshold (RW)
- *
- * Reset value: 0x00000004U
- */
-typedef union _hw_enet_raem
-{
- uint32_t U;
- struct _hw_enet_raem_bitfields
- {
- uint32_t RX_ALMOST_EMPTY : 8; //!< [7:0] Value Of The Receive FIFO
- //! Almost Empty Threshold
- uint32_t RESERVED0 : 24; //!< [31:8]
- } B;
-} hw_enet_raem_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RAEM register
- */
-//@{
-#define HW_ENET_RAEM_ADDR(x) (REGS_ENET_BASE(x) + 0x198U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RAEM(x) (*(__IO hw_enet_raem_t *) HW_ENET_RAEM_ADDR(x))
-#define HW_ENET_RAEM_RD(x) (HW_ENET_RAEM(x).U)
-#define HW_ENET_RAEM_WR(x, v) (HW_ENET_RAEM(x).U = (v))
-#define HW_ENET_RAEM_SET(x, v) (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) | (v)))
-#define HW_ENET_RAEM_CLR(x, v) (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) & ~(v)))
-#define HW_ENET_RAEM_TOG(x, v) (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RAEM bitfields
- */
-
-/*!
- * @name Register ENET_RAEM, field RX_ALMOST_EMPTY[7:0] (RW)
- *
- * Value, in 64-bit words, of the receive FIFO almost empty threshold. When the
- * FIFO level reaches the value programmed in this field and the end-of-frame has
- * not been received for the frame yet, the core receive read control stops FIFO
- * read (and subsequently stops transferring data to the MAC client
- * application). It continues to deliver the frame, if again more data than the threshold or
- * the end-of-frame is available in the FIFO. A minimum value of 4 should be set.
- */
-//@{
-#define BP_ENET_RAEM_RX_ALMOST_EMPTY (0U) //!< Bit position for ENET_RAEM_RX_ALMOST_EMPTY.
-#define BM_ENET_RAEM_RX_ALMOST_EMPTY (0x000000FFU) //!< Bit mask for ENET_RAEM_RX_ALMOST_EMPTY.
-#define BS_ENET_RAEM_RX_ALMOST_EMPTY (8U) //!< Bit field size in bits for ENET_RAEM_RX_ALMOST_EMPTY.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RAEM_RX_ALMOST_EMPTY field.
-#define BR_ENET_RAEM_RX_ALMOST_EMPTY(x) (HW_ENET_RAEM(x).B.RX_ALMOST_EMPTY)
-#endif
-
-//! @brief Format value for bitfield ENET_RAEM_RX_ALMOST_EMPTY.
-#define BF_ENET_RAEM_RX_ALMOST_EMPTY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RAEM_RX_ALMOST_EMPTY), uint32_t) & BM_ENET_RAEM_RX_ALMOST_EMPTY)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RX_ALMOST_EMPTY field to a new value.
-#define BW_ENET_RAEM_RX_ALMOST_EMPTY(x, v) (HW_ENET_RAEM_WR(x, (HW_ENET_RAEM_RD(x) & ~BM_ENET_RAEM_RX_ALMOST_EMPTY) | BF_ENET_RAEM_RX_ALMOST_EMPTY(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RAFL - Receive FIFO Almost Full Threshold
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RAFL - Receive FIFO Almost Full Threshold (RW)
- *
- * Reset value: 0x00000004U
- */
-typedef union _hw_enet_rafl
-{
- uint32_t U;
- struct _hw_enet_rafl_bitfields
- {
- uint32_t RX_ALMOST_FULL : 8; //!< [7:0] Value Of The Receive FIFO
- //! Almost Full Threshold
- uint32_t RESERVED0 : 24; //!< [31:8]
- } B;
-} hw_enet_rafl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RAFL register
- */
-//@{
-#define HW_ENET_RAFL_ADDR(x) (REGS_ENET_BASE(x) + 0x19CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RAFL(x) (*(__IO hw_enet_rafl_t *) HW_ENET_RAFL_ADDR(x))
-#define HW_ENET_RAFL_RD(x) (HW_ENET_RAFL(x).U)
-#define HW_ENET_RAFL_WR(x, v) (HW_ENET_RAFL(x).U = (v))
-#define HW_ENET_RAFL_SET(x, v) (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) | (v)))
-#define HW_ENET_RAFL_CLR(x, v) (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) & ~(v)))
-#define HW_ENET_RAFL_TOG(x, v) (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RAFL bitfields
- */
-
-/*!
- * @name Register ENET_RAFL, field RX_ALMOST_FULL[7:0] (RW)
- *
- * Value, in 64-bit words, of the receive FIFO almost full threshold. When the
- * FIFO level comes close to the maximum, so that there is no more space for at
- * least RX_ALMOST_FULL number of words, the MAC stops writing data in the FIFO and
- * truncates the received frame to avoid FIFO overflow. The corresponding error
- * status will be set when the frame is delivered to the application. A minimum
- * value of 4 should be set.
- */
-//@{
-#define BP_ENET_RAFL_RX_ALMOST_FULL (0U) //!< Bit position for ENET_RAFL_RX_ALMOST_FULL.
-#define BM_ENET_RAFL_RX_ALMOST_FULL (0x000000FFU) //!< Bit mask for ENET_RAFL_RX_ALMOST_FULL.
-#define BS_ENET_RAFL_RX_ALMOST_FULL (8U) //!< Bit field size in bits for ENET_RAFL_RX_ALMOST_FULL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RAFL_RX_ALMOST_FULL field.
-#define BR_ENET_RAFL_RX_ALMOST_FULL(x) (HW_ENET_RAFL(x).B.RX_ALMOST_FULL)
-#endif
-
-//! @brief Format value for bitfield ENET_RAFL_RX_ALMOST_FULL.
-#define BF_ENET_RAFL_RX_ALMOST_FULL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RAFL_RX_ALMOST_FULL), uint32_t) & BM_ENET_RAFL_RX_ALMOST_FULL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RX_ALMOST_FULL field to a new value.
-#define BW_ENET_RAFL_RX_ALMOST_FULL(x, v) (HW_ENET_RAFL_WR(x, (HW_ENET_RAFL_RD(x) & ~BM_ENET_RAFL_RX_ALMOST_FULL) | BF_ENET_RAFL_RX_ALMOST_FULL(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_TSEM - Transmit FIFO Section Empty Threshold
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_TSEM - Transmit FIFO Section Empty Threshold (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_tsem
-{
- uint32_t U;
- struct _hw_enet_tsem_bitfields
- {
- uint32_t TX_SECTION_EMPTY : 8; //!< [7:0] Value Of The Transmit FIFO
- //! Section Empty Threshold
- uint32_t RESERVED0 : 24; //!< [31:8]
- } B;
-} hw_enet_tsem_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_TSEM register
- */
-//@{
-#define HW_ENET_TSEM_ADDR(x) (REGS_ENET_BASE(x) + 0x1A0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_TSEM(x) (*(__IO hw_enet_tsem_t *) HW_ENET_TSEM_ADDR(x))
-#define HW_ENET_TSEM_RD(x) (HW_ENET_TSEM(x).U)
-#define HW_ENET_TSEM_WR(x, v) (HW_ENET_TSEM(x).U = (v))
-#define HW_ENET_TSEM_SET(x, v) (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) | (v)))
-#define HW_ENET_TSEM_CLR(x, v) (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) & ~(v)))
-#define HW_ENET_TSEM_TOG(x, v) (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_TSEM bitfields
- */
-
-/*!
- * @name Register ENET_TSEM, field TX_SECTION_EMPTY[7:0] (RW)
- *
- * Value, in 64-bit words, of the transmit FIFO section empty threshold. See
- * Transmit FIFOFour programmable thresholds are available which control the core
- * operation. for more information.
- */
-//@{
-#define BP_ENET_TSEM_TX_SECTION_EMPTY (0U) //!< Bit position for ENET_TSEM_TX_SECTION_EMPTY.
-#define BM_ENET_TSEM_TX_SECTION_EMPTY (0x000000FFU) //!< Bit mask for ENET_TSEM_TX_SECTION_EMPTY.
-#define BS_ENET_TSEM_TX_SECTION_EMPTY (8U) //!< Bit field size in bits for ENET_TSEM_TX_SECTION_EMPTY.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_TSEM_TX_SECTION_EMPTY field.
-#define BR_ENET_TSEM_TX_SECTION_EMPTY(x) (HW_ENET_TSEM(x).B.TX_SECTION_EMPTY)
-#endif
-
-//! @brief Format value for bitfield ENET_TSEM_TX_SECTION_EMPTY.
-#define BF_ENET_TSEM_TX_SECTION_EMPTY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TSEM_TX_SECTION_EMPTY), uint32_t) & BM_ENET_TSEM_TX_SECTION_EMPTY)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TX_SECTION_EMPTY field to a new value.
-#define BW_ENET_TSEM_TX_SECTION_EMPTY(x, v) (HW_ENET_TSEM_WR(x, (HW_ENET_TSEM_RD(x) & ~BM_ENET_TSEM_TX_SECTION_EMPTY) | BF_ENET_TSEM_TX_SECTION_EMPTY(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold (RW)
- *
- * Reset value: 0x00000004U
- */
-typedef union _hw_enet_taem
-{
- uint32_t U;
- struct _hw_enet_taem_bitfields
- {
- uint32_t TX_ALMOST_EMPTY : 8; //!< [7:0] Value of Transmit FIFO
- //! Almost Empty Threshold
- uint32_t RESERVED0 : 24; //!< [31:8]
- } B;
-} hw_enet_taem_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_TAEM register
- */
-//@{
-#define HW_ENET_TAEM_ADDR(x) (REGS_ENET_BASE(x) + 0x1A4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_TAEM(x) (*(__IO hw_enet_taem_t *) HW_ENET_TAEM_ADDR(x))
-#define HW_ENET_TAEM_RD(x) (HW_ENET_TAEM(x).U)
-#define HW_ENET_TAEM_WR(x, v) (HW_ENET_TAEM(x).U = (v))
-#define HW_ENET_TAEM_SET(x, v) (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) | (v)))
-#define HW_ENET_TAEM_CLR(x, v) (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) & ~(v)))
-#define HW_ENET_TAEM_TOG(x, v) (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_TAEM bitfields
- */
-
-/*!
- * @name Register ENET_TAEM, field TX_ALMOST_EMPTY[7:0] (RW)
- *
- * Value, in 64-bit words, of the transmit FIFO almost empty threshold. When the
- * FIFO level reaches the value programmed in this field, and no end-of-frame is
- * available for the frame, the MAC transmit logic, to avoid FIFO underflow,
- * stops reading the FIFO and transmits a frame with an MII error indication. See
- * Transmit FIFOFour programmable thresholds are available which control the core
- * operation. for more information. A minimum value of 4 should be set.
- */
-//@{
-#define BP_ENET_TAEM_TX_ALMOST_EMPTY (0U) //!< Bit position for ENET_TAEM_TX_ALMOST_EMPTY.
-#define BM_ENET_TAEM_TX_ALMOST_EMPTY (0x000000FFU) //!< Bit mask for ENET_TAEM_TX_ALMOST_EMPTY.
-#define BS_ENET_TAEM_TX_ALMOST_EMPTY (8U) //!< Bit field size in bits for ENET_TAEM_TX_ALMOST_EMPTY.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_TAEM_TX_ALMOST_EMPTY field.
-#define BR_ENET_TAEM_TX_ALMOST_EMPTY(x) (HW_ENET_TAEM(x).B.TX_ALMOST_EMPTY)
-#endif
-
-//! @brief Format value for bitfield ENET_TAEM_TX_ALMOST_EMPTY.
-#define BF_ENET_TAEM_TX_ALMOST_EMPTY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TAEM_TX_ALMOST_EMPTY), uint32_t) & BM_ENET_TAEM_TX_ALMOST_EMPTY)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TX_ALMOST_EMPTY field to a new value.
-#define BW_ENET_TAEM_TX_ALMOST_EMPTY(x, v) (HW_ENET_TAEM_WR(x, (HW_ENET_TAEM_RD(x) & ~BM_ENET_TAEM_TX_ALMOST_EMPTY) | BF_ENET_TAEM_TX_ALMOST_EMPTY(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_TAFL - Transmit FIFO Almost Full Threshold
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_TAFL - Transmit FIFO Almost Full Threshold (RW)
- *
- * Reset value: 0x00000008U
- */
-typedef union _hw_enet_tafl
-{
- uint32_t U;
- struct _hw_enet_tafl_bitfields
- {
- uint32_t TX_ALMOST_FULL : 8; //!< [7:0] Value Of The Transmit FIFO
- //! Almost Full Threshold
- uint32_t RESERVED0 : 24; //!< [31:8]
- } B;
-} hw_enet_tafl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_TAFL register
- */
-//@{
-#define HW_ENET_TAFL_ADDR(x) (REGS_ENET_BASE(x) + 0x1A8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_TAFL(x) (*(__IO hw_enet_tafl_t *) HW_ENET_TAFL_ADDR(x))
-#define HW_ENET_TAFL_RD(x) (HW_ENET_TAFL(x).U)
-#define HW_ENET_TAFL_WR(x, v) (HW_ENET_TAFL(x).U = (v))
-#define HW_ENET_TAFL_SET(x, v) (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) | (v)))
-#define HW_ENET_TAFL_CLR(x, v) (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) & ~(v)))
-#define HW_ENET_TAFL_TOG(x, v) (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_TAFL bitfields
- */
-
-/*!
- * @name Register ENET_TAFL, field TX_ALMOST_FULL[7:0] (RW)
- *
- * Value, in 64-bit words, of the transmit FIFO almost full threshold. A minimum
- * value of six is required . A recommended value of at least 8 should be set
- * allowing a latency of two clock cycles to the application. If more latency is
- * required the value can be increased as necessary (latency = TAFL - 5). When the
- * FIFO level comes close to the maximum, so that there is no more space for at
- * least TX_ALMOST_FULL number of words, the pin ff_tx_rdy is deasserted. If the
- * application does not react on this signal, the FIFO write control logic, to
- * avoid FIFO overflow, truncates the current frame and sets the error status. As a
- * result, the frame will be transmitted with an GMII/MII error indication. See
- * Transmit FIFOFour programmable thresholds are available which control the core
- * operation. for more information. A FIFO overflow is a fatal error and requires
- * a global reset on the transmit datapath or at least deassertion of ETHEREN.
- */
-//@{
-#define BP_ENET_TAFL_TX_ALMOST_FULL (0U) //!< Bit position for ENET_TAFL_TX_ALMOST_FULL.
-#define BM_ENET_TAFL_TX_ALMOST_FULL (0x000000FFU) //!< Bit mask for ENET_TAFL_TX_ALMOST_FULL.
-#define BS_ENET_TAFL_TX_ALMOST_FULL (8U) //!< Bit field size in bits for ENET_TAFL_TX_ALMOST_FULL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_TAFL_TX_ALMOST_FULL field.
-#define BR_ENET_TAFL_TX_ALMOST_FULL(x) (HW_ENET_TAFL(x).B.TX_ALMOST_FULL)
-#endif
-
-//! @brief Format value for bitfield ENET_TAFL_TX_ALMOST_FULL.
-#define BF_ENET_TAFL_TX_ALMOST_FULL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TAFL_TX_ALMOST_FULL), uint32_t) & BM_ENET_TAFL_TX_ALMOST_FULL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TX_ALMOST_FULL field to a new value.
-#define BW_ENET_TAFL_TX_ALMOST_FULL(x, v) (HW_ENET_TAFL_WR(x, (HW_ENET_TAFL_RD(x) & ~BM_ENET_TAFL_TX_ALMOST_FULL) | BF_ENET_TAFL_TX_ALMOST_FULL(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_TIPG - Transmit Inter-Packet Gap
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_TIPG - Transmit Inter-Packet Gap (RW)
- *
- * Reset value: 0x0000000CU
- */
-typedef union _hw_enet_tipg
-{
- uint32_t U;
- struct _hw_enet_tipg_bitfields
- {
- uint32_t IPG : 5; //!< [4:0] Transmit Inter-Packet Gap
- uint32_t RESERVED0 : 27; //!< [31:5]
- } B;
-} hw_enet_tipg_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_TIPG register
- */
-//@{
-#define HW_ENET_TIPG_ADDR(x) (REGS_ENET_BASE(x) + 0x1ACU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_TIPG(x) (*(__IO hw_enet_tipg_t *) HW_ENET_TIPG_ADDR(x))
-#define HW_ENET_TIPG_RD(x) (HW_ENET_TIPG(x).U)
-#define HW_ENET_TIPG_WR(x, v) (HW_ENET_TIPG(x).U = (v))
-#define HW_ENET_TIPG_SET(x, v) (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) | (v)))
-#define HW_ENET_TIPG_CLR(x, v) (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) & ~(v)))
-#define HW_ENET_TIPG_TOG(x, v) (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_TIPG bitfields
- */
-
-/*!
- * @name Register ENET_TIPG, field IPG[4:0] (RW)
- *
- * Indicates the IPG, in bytes, between transmitted frames. Valid values range
- * from 8 to 27. If value is less than 8, the IPG is 8. If value is greater than
- * 27, the IPG is 27.
- */
-//@{
-#define BP_ENET_TIPG_IPG (0U) //!< Bit position for ENET_TIPG_IPG.
-#define BM_ENET_TIPG_IPG (0x0000001FU) //!< Bit mask for ENET_TIPG_IPG.
-#define BS_ENET_TIPG_IPG (5U) //!< Bit field size in bits for ENET_TIPG_IPG.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_TIPG_IPG field.
-#define BR_ENET_TIPG_IPG(x) (HW_ENET_TIPG(x).B.IPG)
-#endif
-
-//! @brief Format value for bitfield ENET_TIPG_IPG.
-#define BF_ENET_TIPG_IPG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TIPG_IPG), uint32_t) & BM_ENET_TIPG_IPG)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IPG field to a new value.
-#define BW_ENET_TIPG_IPG(x, v) (HW_ENET_TIPG_WR(x, (HW_ENET_TIPG_RD(x) & ~BM_ENET_TIPG_IPG) | BF_ENET_TIPG_IPG(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_FTRL - Frame Truncation Length
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_FTRL - Frame Truncation Length (RW)
- *
- * Reset value: 0x000007FFU
- */
-typedef union _hw_enet_ftrl
-{
- uint32_t U;
- struct _hw_enet_ftrl_bitfields
- {
- uint32_t TRUNC_FL : 14; //!< [13:0] Frame Truncation Length
- uint32_t RESERVED0 : 18; //!< [31:14]
- } B;
-} hw_enet_ftrl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_FTRL register
- */
-//@{
-#define HW_ENET_FTRL_ADDR(x) (REGS_ENET_BASE(x) + 0x1B0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_FTRL(x) (*(__IO hw_enet_ftrl_t *) HW_ENET_FTRL_ADDR(x))
-#define HW_ENET_FTRL_RD(x) (HW_ENET_FTRL(x).U)
-#define HW_ENET_FTRL_WR(x, v) (HW_ENET_FTRL(x).U = (v))
-#define HW_ENET_FTRL_SET(x, v) (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) | (v)))
-#define HW_ENET_FTRL_CLR(x, v) (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) & ~(v)))
-#define HW_ENET_FTRL_TOG(x, v) (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_FTRL bitfields
- */
-
-/*!
- * @name Register ENET_FTRL, field TRUNC_FL[13:0] (RW)
- *
- * Indicates the value a receive frame is truncated, if it is greater than this
- * value. Must be greater than or equal to RCR[MAX_FL]. Truncation happens at
- * TRUNC_FL. However, when truncation occurs, the application (FIFO) may receive
- * less data, guaranteeing that it never receives more than the set limit.
- */
-//@{
-#define BP_ENET_FTRL_TRUNC_FL (0U) //!< Bit position for ENET_FTRL_TRUNC_FL.
-#define BM_ENET_FTRL_TRUNC_FL (0x00003FFFU) //!< Bit mask for ENET_FTRL_TRUNC_FL.
-#define BS_ENET_FTRL_TRUNC_FL (14U) //!< Bit field size in bits for ENET_FTRL_TRUNC_FL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_FTRL_TRUNC_FL field.
-#define BR_ENET_FTRL_TRUNC_FL(x) (HW_ENET_FTRL(x).B.TRUNC_FL)
-#endif
-
-//! @brief Format value for bitfield ENET_FTRL_TRUNC_FL.
-#define BF_ENET_FTRL_TRUNC_FL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_FTRL_TRUNC_FL), uint32_t) & BM_ENET_FTRL_TRUNC_FL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TRUNC_FL field to a new value.
-#define BW_ENET_FTRL_TRUNC_FL(x, v) (HW_ENET_FTRL_WR(x, (HW_ENET_FTRL_RD(x) & ~BM_ENET_FTRL_TRUNC_FL) | BF_ENET_FTRL_TRUNC_FL(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_TACC - Transmit Accelerator Function Configuration
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_TACC - Transmit Accelerator Function Configuration (RW)
- *
- * Reset value: 0x00000000U
- *
- * TACC controls accelerator actions when sending frames. The register can be
- * changed before or after each frame, but it must remain unmodified during frame
- * writes into the transmit FIFO. The TFWR[STRFWD] field must be set to use the
- * checksum feature.
- */
-typedef union _hw_enet_tacc
-{
- uint32_t U;
- struct _hw_enet_tacc_bitfields
- {
- uint32_t SHIFT16 : 1; //!< [0] TX FIFO Shift-16
- uint32_t RESERVED0 : 2; //!< [2:1]
- uint32_t IPCHK : 1; //!< [3]
- uint32_t PROCHK : 1; //!< [4]
- uint32_t RESERVED1 : 27; //!< [31:5]
- } B;
-} hw_enet_tacc_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_TACC register
- */
-//@{
-#define HW_ENET_TACC_ADDR(x) (REGS_ENET_BASE(x) + 0x1C0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_TACC(x) (*(__IO hw_enet_tacc_t *) HW_ENET_TACC_ADDR(x))
-#define HW_ENET_TACC_RD(x) (HW_ENET_TACC(x).U)
-#define HW_ENET_TACC_WR(x, v) (HW_ENET_TACC(x).U = (v))
-#define HW_ENET_TACC_SET(x, v) (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) | (v)))
-#define HW_ENET_TACC_CLR(x, v) (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) & ~(v)))
-#define HW_ENET_TACC_TOG(x, v) (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_TACC bitfields
- */
-
-/*!
- * @name Register ENET_TACC, field SHIFT16[0] (RW)
- *
- * Values:
- * - 0 - Disabled.
- * - 1 - Indicates to the transmit data FIFO that the written frames contain two
- * additional octets before the frame data. This means the actual frame
- * begins at bit 16 of the first word written into the FIFO. This function allows
- * putting the frame payload on a 32-bit boundary in memory, as the 14-byte
- * Ethernet header is extended to a 16-byte header.
- */
-//@{
-#define BP_ENET_TACC_SHIFT16 (0U) //!< Bit position for ENET_TACC_SHIFT16.
-#define BM_ENET_TACC_SHIFT16 (0x00000001U) //!< Bit mask for ENET_TACC_SHIFT16.
-#define BS_ENET_TACC_SHIFT16 (1U) //!< Bit field size in bits for ENET_TACC_SHIFT16.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_TACC_SHIFT16 field.
-#define BR_ENET_TACC_SHIFT16(x) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_SHIFT16))
-#endif
-
-//! @brief Format value for bitfield ENET_TACC_SHIFT16.
-#define BF_ENET_TACC_SHIFT16(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TACC_SHIFT16), uint32_t) & BM_ENET_TACC_SHIFT16)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SHIFT16 field to a new value.
-#define BW_ENET_TACC_SHIFT16(x, v) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_SHIFT16) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_TACC, field IPCHK[3] (RW)
- *
- * Enables insertion of IP header checksum.
- *
- * Values:
- * - 0 - Checksum is not inserted.
- * - 1 - If an IP frame is transmitted, the checksum is inserted automatically.
- * The IP header checksum field must be cleared. If a non-IP frame is
- * transmitted the frame is not modified.
- */
-//@{
-#define BP_ENET_TACC_IPCHK (3U) //!< Bit position for ENET_TACC_IPCHK.
-#define BM_ENET_TACC_IPCHK (0x00000008U) //!< Bit mask for ENET_TACC_IPCHK.
-#define BS_ENET_TACC_IPCHK (1U) //!< Bit field size in bits for ENET_TACC_IPCHK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_TACC_IPCHK field.
-#define BR_ENET_TACC_IPCHK(x) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_IPCHK))
-#endif
-
-//! @brief Format value for bitfield ENET_TACC_IPCHK.
-#define BF_ENET_TACC_IPCHK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TACC_IPCHK), uint32_t) & BM_ENET_TACC_IPCHK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IPCHK field to a new value.
-#define BW_ENET_TACC_IPCHK(x, v) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_IPCHK) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_TACC, field PROCHK[4] (RW)
- *
- * Enables insertion of protocol checksum.
- *
- * Values:
- * - 0 - Checksum not inserted.
- * - 1 - If an IP frame with a known protocol is transmitted, the checksum is
- * inserted automatically into the frame. The checksum field must be cleared.
- * The other frames are not modified.
- */
-//@{
-#define BP_ENET_TACC_PROCHK (4U) //!< Bit position for ENET_TACC_PROCHK.
-#define BM_ENET_TACC_PROCHK (0x00000010U) //!< Bit mask for ENET_TACC_PROCHK.
-#define BS_ENET_TACC_PROCHK (1U) //!< Bit field size in bits for ENET_TACC_PROCHK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_TACC_PROCHK field.
-#define BR_ENET_TACC_PROCHK(x) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_PROCHK))
-#endif
-
-//! @brief Format value for bitfield ENET_TACC_PROCHK.
-#define BF_ENET_TACC_PROCHK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TACC_PROCHK), uint32_t) & BM_ENET_TACC_PROCHK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PROCHK field to a new value.
-#define BW_ENET_TACC_PROCHK(x, v) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_PROCHK) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RACC - Receive Accelerator Function Configuration
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RACC - Receive Accelerator Function Configuration (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_racc
-{
- uint32_t U;
- struct _hw_enet_racc_bitfields
- {
- uint32_t PADREM : 1; //!< [0] Enable Padding Removal For Short IP
- //! Frames
- uint32_t IPDIS : 1; //!< [1] Enable Discard Of Frames With Wrong IPv4
- //! Header Checksum
- uint32_t PRODIS : 1; //!< [2] Enable Discard Of Frames With Wrong
- //! Protocol Checksum
- uint32_t RESERVED0 : 3; //!< [5:3]
- uint32_t LINEDIS : 1; //!< [6] Enable Discard Of Frames With MAC
- //! Layer Errors
- uint32_t SHIFT16 : 1; //!< [7] RX FIFO Shift-16
- uint32_t RESERVED1 : 24; //!< [31:8]
- } B;
-} hw_enet_racc_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RACC register
- */
-//@{
-#define HW_ENET_RACC_ADDR(x) (REGS_ENET_BASE(x) + 0x1C4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RACC(x) (*(__IO hw_enet_racc_t *) HW_ENET_RACC_ADDR(x))
-#define HW_ENET_RACC_RD(x) (HW_ENET_RACC(x).U)
-#define HW_ENET_RACC_WR(x, v) (HW_ENET_RACC(x).U = (v))
-#define HW_ENET_RACC_SET(x, v) (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) | (v)))
-#define HW_ENET_RACC_CLR(x, v) (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) & ~(v)))
-#define HW_ENET_RACC_TOG(x, v) (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RACC bitfields
- */
-
-/*!
- * @name Register ENET_RACC, field PADREM[0] (RW)
- *
- * Values:
- * - 0 - Padding not removed.
- * - 1 - Any bytes following the IP payload section of the frame are removed
- * from the frame.
- */
-//@{
-#define BP_ENET_RACC_PADREM (0U) //!< Bit position for ENET_RACC_PADREM.
-#define BM_ENET_RACC_PADREM (0x00000001U) //!< Bit mask for ENET_RACC_PADREM.
-#define BS_ENET_RACC_PADREM (1U) //!< Bit field size in bits for ENET_RACC_PADREM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RACC_PADREM field.
-#define BR_ENET_RACC_PADREM(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PADREM))
-#endif
-
-//! @brief Format value for bitfield ENET_RACC_PADREM.
-#define BF_ENET_RACC_PADREM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RACC_PADREM), uint32_t) & BM_ENET_RACC_PADREM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PADREM field to a new value.
-#define BW_ENET_RACC_PADREM(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PADREM) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_RACC, field IPDIS[1] (RW)
- *
- * Values:
- * - 0 - Frames with wrong IPv4 header checksum are not discarded.
- * - 1 - If an IPv4 frame is received with a mismatching header checksum, the
- * frame is discarded. IPv6 has no header checksum and is not affected by this
- * setting. Discarding is only available when the RX FIFO operates in store
- * and forward mode (RSFL cleared).
- */
-//@{
-#define BP_ENET_RACC_IPDIS (1U) //!< Bit position for ENET_RACC_IPDIS.
-#define BM_ENET_RACC_IPDIS (0x00000002U) //!< Bit mask for ENET_RACC_IPDIS.
-#define BS_ENET_RACC_IPDIS (1U) //!< Bit field size in bits for ENET_RACC_IPDIS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RACC_IPDIS field.
-#define BR_ENET_RACC_IPDIS(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_IPDIS))
-#endif
-
-//! @brief Format value for bitfield ENET_RACC_IPDIS.
-#define BF_ENET_RACC_IPDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RACC_IPDIS), uint32_t) & BM_ENET_RACC_IPDIS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IPDIS field to a new value.
-#define BW_ENET_RACC_IPDIS(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_IPDIS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_RACC, field PRODIS[2] (RW)
- *
- * Values:
- * - 0 - Frames with wrong checksum are not discarded.
- * - 1 - If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP,
- * UDP, or ICMP checksum, the frame is discarded. Discarding is only
- * available when the RX FIFO operates in store and forward mode (RSFL cleared).
- */
-//@{
-#define BP_ENET_RACC_PRODIS (2U) //!< Bit position for ENET_RACC_PRODIS.
-#define BM_ENET_RACC_PRODIS (0x00000004U) //!< Bit mask for ENET_RACC_PRODIS.
-#define BS_ENET_RACC_PRODIS (1U) //!< Bit field size in bits for ENET_RACC_PRODIS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RACC_PRODIS field.
-#define BR_ENET_RACC_PRODIS(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PRODIS))
-#endif
-
-//! @brief Format value for bitfield ENET_RACC_PRODIS.
-#define BF_ENET_RACC_PRODIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RACC_PRODIS), uint32_t) & BM_ENET_RACC_PRODIS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PRODIS field to a new value.
-#define BW_ENET_RACC_PRODIS(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PRODIS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_RACC, field LINEDIS[6] (RW)
- *
- * Values:
- * - 0 - Frames with errors are not discarded.
- * - 1 - Any frame received with a CRC, length, or PHY error is automatically
- * discarded and not forwarded to the user application interface.
- */
-//@{
-#define BP_ENET_RACC_LINEDIS (6U) //!< Bit position for ENET_RACC_LINEDIS.
-#define BM_ENET_RACC_LINEDIS (0x00000040U) //!< Bit mask for ENET_RACC_LINEDIS.
-#define BS_ENET_RACC_LINEDIS (1U) //!< Bit field size in bits for ENET_RACC_LINEDIS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RACC_LINEDIS field.
-#define BR_ENET_RACC_LINEDIS(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_LINEDIS))
-#endif
-
-//! @brief Format value for bitfield ENET_RACC_LINEDIS.
-#define BF_ENET_RACC_LINEDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RACC_LINEDIS), uint32_t) & BM_ENET_RACC_LINEDIS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LINEDIS field to a new value.
-#define BW_ENET_RACC_LINEDIS(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_LINEDIS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_RACC, field SHIFT16[7] (RW)
- *
- * When this field is set, the actual frame data starts at bit 16 of the first
- * word read from the RX FIFO aligning the Ethernet payload on a 32-bit boundary.
- * This function only affects the FIFO storage and has no influence on the
- * statistics, which use the actual length of the frame received.
- *
- * Values:
- * - 0 - Disabled.
- * - 1 - Instructs the MAC to write two additional bytes in front of each frame
- * received into the RX FIFO.
- */
-//@{
-#define BP_ENET_RACC_SHIFT16 (7U) //!< Bit position for ENET_RACC_SHIFT16.
-#define BM_ENET_RACC_SHIFT16 (0x00000080U) //!< Bit mask for ENET_RACC_SHIFT16.
-#define BS_ENET_RACC_SHIFT16 (1U) //!< Bit field size in bits for ENET_RACC_SHIFT16.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RACC_SHIFT16 field.
-#define BR_ENET_RACC_SHIFT16(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_SHIFT16))
-#endif
-
-//! @brief Format value for bitfield ENET_RACC_SHIFT16.
-#define BF_ENET_RACC_SHIFT16(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RACC_SHIFT16), uint32_t) & BM_ENET_RACC_SHIFT16)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SHIFT16 field to a new value.
-#define BW_ENET_RACC_SHIFT16(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_SHIFT16) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rmon_t_packets
-{
- uint32_t U;
- struct _hw_enet_rmon_t_packets_bitfields
- {
- uint32_t TXPKTS : 16; //!< [15:0] Packet count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_t_packets_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_T_PACKETS register
- */
-//@{
-#define HW_ENET_RMON_T_PACKETS_ADDR(x) (REGS_ENET_BASE(x) + 0x204U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_T_PACKETS(x) (*(__I hw_enet_rmon_t_packets_t *) HW_ENET_RMON_T_PACKETS_ADDR(x))
-#define HW_ENET_RMON_T_PACKETS_RD(x) (HW_ENET_RMON_T_PACKETS(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_T_PACKETS bitfields
- */
-
-/*!
- * @name Register ENET_RMON_T_PACKETS, field TXPKTS[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_T_PACKETS_TXPKTS (0U) //!< Bit position for ENET_RMON_T_PACKETS_TXPKTS.
-#define BM_ENET_RMON_T_PACKETS_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_PACKETS_TXPKTS.
-#define BS_ENET_RMON_T_PACKETS_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_PACKETS_TXPKTS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_T_PACKETS_TXPKTS field.
-#define BR_ENET_RMON_T_PACKETS_TXPKTS(x) (HW_ENET_RMON_T_PACKETS(x).B.TXPKTS)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- *
- * RMON Tx Broadcast Packets
- */
-typedef union _hw_enet_rmon_t_bc_pkt
-{
- uint32_t U;
- struct _hw_enet_rmon_t_bc_pkt_bitfields
- {
- uint32_t TXPKTS : 16; //!< [15:0] Broadcast packets
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_t_bc_pkt_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_T_BC_PKT register
- */
-//@{
-#define HW_ENET_RMON_T_BC_PKT_ADDR(x) (REGS_ENET_BASE(x) + 0x208U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_T_BC_PKT(x) (*(__I hw_enet_rmon_t_bc_pkt_t *) HW_ENET_RMON_T_BC_PKT_ADDR(x))
-#define HW_ENET_RMON_T_BC_PKT_RD(x) (HW_ENET_RMON_T_BC_PKT(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_T_BC_PKT bitfields
- */
-
-/*!
- * @name Register ENET_RMON_T_BC_PKT, field TXPKTS[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_T_BC_PKT_TXPKTS (0U) //!< Bit position for ENET_RMON_T_BC_PKT_TXPKTS.
-#define BM_ENET_RMON_T_BC_PKT_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_BC_PKT_TXPKTS.
-#define BS_ENET_RMON_T_BC_PKT_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_BC_PKT_TXPKTS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_T_BC_PKT_TXPKTS field.
-#define BR_ENET_RMON_T_BC_PKT_TXPKTS(x) (HW_ENET_RMON_T_BC_PKT(x).B.TXPKTS)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rmon_t_mc_pkt
-{
- uint32_t U;
- struct _hw_enet_rmon_t_mc_pkt_bitfields
- {
- uint32_t TXPKTS : 16; //!< [15:0] Multicast packets
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_t_mc_pkt_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_T_MC_PKT register
- */
-//@{
-#define HW_ENET_RMON_T_MC_PKT_ADDR(x) (REGS_ENET_BASE(x) + 0x20CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_T_MC_PKT(x) (*(__I hw_enet_rmon_t_mc_pkt_t *) HW_ENET_RMON_T_MC_PKT_ADDR(x))
-#define HW_ENET_RMON_T_MC_PKT_RD(x) (HW_ENET_RMON_T_MC_PKT(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_T_MC_PKT bitfields
- */
-
-/*!
- * @name Register ENET_RMON_T_MC_PKT, field TXPKTS[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_T_MC_PKT_TXPKTS (0U) //!< Bit position for ENET_RMON_T_MC_PKT_TXPKTS.
-#define BM_ENET_RMON_T_MC_PKT_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_MC_PKT_TXPKTS.
-#define BS_ENET_RMON_T_MC_PKT_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_MC_PKT_TXPKTS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_T_MC_PKT_TXPKTS field.
-#define BR_ENET_RMON_T_MC_PKT_TXPKTS(x) (HW_ENET_RMON_T_MC_PKT(x).B.TXPKTS)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rmon_t_crc_align
-{
- uint32_t U;
- struct _hw_enet_rmon_t_crc_align_bitfields
- {
- uint32_t TXPKTS : 16; //!< [15:0] Packets with CRC/align error
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_t_crc_align_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_T_CRC_ALIGN register
- */
-//@{
-#define HW_ENET_RMON_T_CRC_ALIGN_ADDR(x) (REGS_ENET_BASE(x) + 0x210U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_T_CRC_ALIGN(x) (*(__I hw_enet_rmon_t_crc_align_t *) HW_ENET_RMON_T_CRC_ALIGN_ADDR(x))
-#define HW_ENET_RMON_T_CRC_ALIGN_RD(x) (HW_ENET_RMON_T_CRC_ALIGN(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_T_CRC_ALIGN bitfields
- */
-
-/*!
- * @name Register ENET_RMON_T_CRC_ALIGN, field TXPKTS[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_T_CRC_ALIGN_TXPKTS (0U) //!< Bit position for ENET_RMON_T_CRC_ALIGN_TXPKTS.
-#define BM_ENET_RMON_T_CRC_ALIGN_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_CRC_ALIGN_TXPKTS.
-#define BS_ENET_RMON_T_CRC_ALIGN_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_CRC_ALIGN_TXPKTS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_T_CRC_ALIGN_TXPKTS field.
-#define BR_ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (HW_ENET_RMON_T_CRC_ALIGN(x).B.TXPKTS)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rmon_t_undersize
-{
- uint32_t U;
- struct _hw_enet_rmon_t_undersize_bitfields
- {
- uint32_t TXPKTS : 16; //!< [15:0] Packet count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_t_undersize_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_T_UNDERSIZE register
- */
-//@{
-#define HW_ENET_RMON_T_UNDERSIZE_ADDR(x) (REGS_ENET_BASE(x) + 0x214U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_T_UNDERSIZE(x) (*(__I hw_enet_rmon_t_undersize_t *) HW_ENET_RMON_T_UNDERSIZE_ADDR(x))
-#define HW_ENET_RMON_T_UNDERSIZE_RD(x) (HW_ENET_RMON_T_UNDERSIZE(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_T_UNDERSIZE bitfields
- */
-
-/*!
- * @name Register ENET_RMON_T_UNDERSIZE, field TXPKTS[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_T_UNDERSIZE_TXPKTS (0U) //!< Bit position for ENET_RMON_T_UNDERSIZE_TXPKTS.
-#define BM_ENET_RMON_T_UNDERSIZE_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_UNDERSIZE_TXPKTS.
-#define BS_ENET_RMON_T_UNDERSIZE_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_UNDERSIZE_TXPKTS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_T_UNDERSIZE_TXPKTS field.
-#define BR_ENET_RMON_T_UNDERSIZE_TXPKTS(x) (HW_ENET_RMON_T_UNDERSIZE(x).B.TXPKTS)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rmon_t_oversize
-{
- uint32_t U;
- struct _hw_enet_rmon_t_oversize_bitfields
- {
- uint32_t TXPKTS : 16; //!< [15:0] Packet count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_t_oversize_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_T_OVERSIZE register
- */
-//@{
-#define HW_ENET_RMON_T_OVERSIZE_ADDR(x) (REGS_ENET_BASE(x) + 0x218U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_T_OVERSIZE(x) (*(__I hw_enet_rmon_t_oversize_t *) HW_ENET_RMON_T_OVERSIZE_ADDR(x))
-#define HW_ENET_RMON_T_OVERSIZE_RD(x) (HW_ENET_RMON_T_OVERSIZE(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_T_OVERSIZE bitfields
- */
-
-/*!
- * @name Register ENET_RMON_T_OVERSIZE, field TXPKTS[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_T_OVERSIZE_TXPKTS (0U) //!< Bit position for ENET_RMON_T_OVERSIZE_TXPKTS.
-#define BM_ENET_RMON_T_OVERSIZE_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_OVERSIZE_TXPKTS.
-#define BS_ENET_RMON_T_OVERSIZE_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_OVERSIZE_TXPKTS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_T_OVERSIZE_TXPKTS field.
-#define BR_ENET_RMON_T_OVERSIZE_TXPKTS(x) (HW_ENET_RMON_T_OVERSIZE(x).B.TXPKTS)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- *
- * .
- */
-typedef union _hw_enet_rmon_t_frag
-{
- uint32_t U;
- struct _hw_enet_rmon_t_frag_bitfields
- {
- uint32_t TXPKTS : 16; //!< [15:0] Packet count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_t_frag_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_T_FRAG register
- */
-//@{
-#define HW_ENET_RMON_T_FRAG_ADDR(x) (REGS_ENET_BASE(x) + 0x21CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_T_FRAG(x) (*(__I hw_enet_rmon_t_frag_t *) HW_ENET_RMON_T_FRAG_ADDR(x))
-#define HW_ENET_RMON_T_FRAG_RD(x) (HW_ENET_RMON_T_FRAG(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_T_FRAG bitfields
- */
-
-/*!
- * @name Register ENET_RMON_T_FRAG, field TXPKTS[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_T_FRAG_TXPKTS (0U) //!< Bit position for ENET_RMON_T_FRAG_TXPKTS.
-#define BM_ENET_RMON_T_FRAG_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_FRAG_TXPKTS.
-#define BS_ENET_RMON_T_FRAG_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_FRAG_TXPKTS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_T_FRAG_TXPKTS field.
-#define BR_ENET_RMON_T_FRAG_TXPKTS(x) (HW_ENET_RMON_T_FRAG(x).B.TXPKTS)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rmon_t_jab
-{
- uint32_t U;
- struct _hw_enet_rmon_t_jab_bitfields
- {
- uint32_t TXPKTS : 16; //!< [15:0] Packet count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_t_jab_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_T_JAB register
- */
-//@{
-#define HW_ENET_RMON_T_JAB_ADDR(x) (REGS_ENET_BASE(x) + 0x220U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_T_JAB(x) (*(__I hw_enet_rmon_t_jab_t *) HW_ENET_RMON_T_JAB_ADDR(x))
-#define HW_ENET_RMON_T_JAB_RD(x) (HW_ENET_RMON_T_JAB(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_T_JAB bitfields
- */
-
-/*!
- * @name Register ENET_RMON_T_JAB, field TXPKTS[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_T_JAB_TXPKTS (0U) //!< Bit position for ENET_RMON_T_JAB_TXPKTS.
-#define BM_ENET_RMON_T_JAB_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_JAB_TXPKTS.
-#define BS_ENET_RMON_T_JAB_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_JAB_TXPKTS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_T_JAB_TXPKTS field.
-#define BR_ENET_RMON_T_JAB_TXPKTS(x) (HW_ENET_RMON_T_JAB(x).B.TXPKTS)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rmon_t_col
-{
- uint32_t U;
- struct _hw_enet_rmon_t_col_bitfields
- {
- uint32_t TXPKTS : 16; //!< [15:0] Packet count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_t_col_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_T_COL register
- */
-//@{
-#define HW_ENET_RMON_T_COL_ADDR(x) (REGS_ENET_BASE(x) + 0x224U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_T_COL(x) (*(__I hw_enet_rmon_t_col_t *) HW_ENET_RMON_T_COL_ADDR(x))
-#define HW_ENET_RMON_T_COL_RD(x) (HW_ENET_RMON_T_COL(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_T_COL bitfields
- */
-
-/*!
- * @name Register ENET_RMON_T_COL, field TXPKTS[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_T_COL_TXPKTS (0U) //!< Bit position for ENET_RMON_T_COL_TXPKTS.
-#define BM_ENET_RMON_T_COL_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_COL_TXPKTS.
-#define BS_ENET_RMON_T_COL_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_COL_TXPKTS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_T_COL_TXPKTS field.
-#define BR_ENET_RMON_T_COL_TXPKTS(x) (HW_ENET_RMON_T_COL(x).B.TXPKTS)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- *
- * .
- */
-typedef union _hw_enet_rmon_t_p64
-{
- uint32_t U;
- struct _hw_enet_rmon_t_p64_bitfields
- {
- uint32_t TXPKTS : 16; //!< [15:0] Packet count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_t_p64_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_T_P64 register
- */
-//@{
-#define HW_ENET_RMON_T_P64_ADDR(x) (REGS_ENET_BASE(x) + 0x228U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_T_P64(x) (*(__I hw_enet_rmon_t_p64_t *) HW_ENET_RMON_T_P64_ADDR(x))
-#define HW_ENET_RMON_T_P64_RD(x) (HW_ENET_RMON_T_P64(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_T_P64 bitfields
- */
-
-/*!
- * @name Register ENET_RMON_T_P64, field TXPKTS[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_T_P64_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P64_TXPKTS.
-#define BM_ENET_RMON_T_P64_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P64_TXPKTS.
-#define BS_ENET_RMON_T_P64_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P64_TXPKTS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_T_P64_TXPKTS field.
-#define BR_ENET_RMON_T_P64_TXPKTS(x) (HW_ENET_RMON_T_P64(x).B.TXPKTS)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rmon_t_p65to127
-{
- uint32_t U;
- struct _hw_enet_rmon_t_p65to127_bitfields
- {
- uint32_t TXPKTS : 16; //!< [15:0] Packet count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_t_p65to127_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_T_P65TO127 register
- */
-//@{
-#define HW_ENET_RMON_T_P65TO127_ADDR(x) (REGS_ENET_BASE(x) + 0x22CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_T_P65TO127(x) (*(__I hw_enet_rmon_t_p65to127_t *) HW_ENET_RMON_T_P65TO127_ADDR(x))
-#define HW_ENET_RMON_T_P65TO127_RD(x) (HW_ENET_RMON_T_P65TO127(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_T_P65TO127 bitfields
- */
-
-/*!
- * @name Register ENET_RMON_T_P65TO127, field TXPKTS[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_T_P65TO127_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P65TO127_TXPKTS.
-#define BM_ENET_RMON_T_P65TO127_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P65TO127_TXPKTS.
-#define BS_ENET_RMON_T_P65TO127_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P65TO127_TXPKTS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_T_P65TO127_TXPKTS field.
-#define BR_ENET_RMON_T_P65TO127_TXPKTS(x) (HW_ENET_RMON_T_P65TO127(x).B.TXPKTS)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rmon_t_p128to255
-{
- uint32_t U;
- struct _hw_enet_rmon_t_p128to255_bitfields
- {
- uint32_t TXPKTS : 16; //!< [15:0] Packet count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_t_p128to255_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_T_P128TO255 register
- */
-//@{
-#define HW_ENET_RMON_T_P128TO255_ADDR(x) (REGS_ENET_BASE(x) + 0x230U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_T_P128TO255(x) (*(__I hw_enet_rmon_t_p128to255_t *) HW_ENET_RMON_T_P128TO255_ADDR(x))
-#define HW_ENET_RMON_T_P128TO255_RD(x) (HW_ENET_RMON_T_P128TO255(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_T_P128TO255 bitfields
- */
-
-/*!
- * @name Register ENET_RMON_T_P128TO255, field TXPKTS[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_T_P128TO255_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P128TO255_TXPKTS.
-#define BM_ENET_RMON_T_P128TO255_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P128TO255_TXPKTS.
-#define BS_ENET_RMON_T_P128TO255_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P128TO255_TXPKTS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_T_P128TO255_TXPKTS field.
-#define BR_ENET_RMON_T_P128TO255_TXPKTS(x) (HW_ENET_RMON_T_P128TO255(x).B.TXPKTS)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rmon_t_p256to511
-{
- uint32_t U;
- struct _hw_enet_rmon_t_p256to511_bitfields
- {
- uint32_t TXPKTS : 16; //!< [15:0] Packet count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_t_p256to511_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_T_P256TO511 register
- */
-//@{
-#define HW_ENET_RMON_T_P256TO511_ADDR(x) (REGS_ENET_BASE(x) + 0x234U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_T_P256TO511(x) (*(__I hw_enet_rmon_t_p256to511_t *) HW_ENET_RMON_T_P256TO511_ADDR(x))
-#define HW_ENET_RMON_T_P256TO511_RD(x) (HW_ENET_RMON_T_P256TO511(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_T_P256TO511 bitfields
- */
-
-/*!
- * @name Register ENET_RMON_T_P256TO511, field TXPKTS[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_T_P256TO511_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P256TO511_TXPKTS.
-#define BM_ENET_RMON_T_P256TO511_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P256TO511_TXPKTS.
-#define BS_ENET_RMON_T_P256TO511_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P256TO511_TXPKTS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_T_P256TO511_TXPKTS field.
-#define BR_ENET_RMON_T_P256TO511_TXPKTS(x) (HW_ENET_RMON_T_P256TO511(x).B.TXPKTS)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- *
- * .
- */
-typedef union _hw_enet_rmon_t_p512to1023
-{
- uint32_t U;
- struct _hw_enet_rmon_t_p512to1023_bitfields
- {
- uint32_t TXPKTS : 16; //!< [15:0] Packet count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_t_p512to1023_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_T_P512TO1023 register
- */
-//@{
-#define HW_ENET_RMON_T_P512TO1023_ADDR(x) (REGS_ENET_BASE(x) + 0x238U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_T_P512TO1023(x) (*(__I hw_enet_rmon_t_p512to1023_t *) HW_ENET_RMON_T_P512TO1023_ADDR(x))
-#define HW_ENET_RMON_T_P512TO1023_RD(x) (HW_ENET_RMON_T_P512TO1023(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_T_P512TO1023 bitfields
- */
-
-/*!
- * @name Register ENET_RMON_T_P512TO1023, field TXPKTS[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_T_P512TO1023_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P512TO1023_TXPKTS.
-#define BM_ENET_RMON_T_P512TO1023_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P512TO1023_TXPKTS.
-#define BS_ENET_RMON_T_P512TO1023_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P512TO1023_TXPKTS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_T_P512TO1023_TXPKTS field.
-#define BR_ENET_RMON_T_P512TO1023_TXPKTS(x) (HW_ENET_RMON_T_P512TO1023(x).B.TXPKTS)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rmon_t_p1024to2047
-{
- uint32_t U;
- struct _hw_enet_rmon_t_p1024to2047_bitfields
- {
- uint32_t TXPKTS : 16; //!< [15:0] Packet count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_t_p1024to2047_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_T_P1024TO2047 register
- */
-//@{
-#define HW_ENET_RMON_T_P1024TO2047_ADDR(x) (REGS_ENET_BASE(x) + 0x23CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_T_P1024TO2047(x) (*(__I hw_enet_rmon_t_p1024to2047_t *) HW_ENET_RMON_T_P1024TO2047_ADDR(x))
-#define HW_ENET_RMON_T_P1024TO2047_RD(x) (HW_ENET_RMON_T_P1024TO2047(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_T_P1024TO2047 bitfields
- */
-
-/*!
- * @name Register ENET_RMON_T_P1024TO2047, field TXPKTS[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_T_P1024TO2047_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P1024TO2047_TXPKTS.
-#define BM_ENET_RMON_T_P1024TO2047_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P1024TO2047_TXPKTS.
-#define BS_ENET_RMON_T_P1024TO2047_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P1024TO2047_TXPKTS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_T_P1024TO2047_TXPKTS field.
-#define BR_ENET_RMON_T_P1024TO2047_TXPKTS(x) (HW_ENET_RMON_T_P1024TO2047(x).B.TXPKTS)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rmon_t_p_gte2048
-{
- uint32_t U;
- struct _hw_enet_rmon_t_p_gte2048_bitfields
- {
- uint32_t TXPKTS : 16; //!< [15:0] Packet count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_t_p_gte2048_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_T_P_GTE2048 register
- */
-//@{
-#define HW_ENET_RMON_T_P_GTE2048_ADDR(x) (REGS_ENET_BASE(x) + 0x240U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_T_P_GTE2048(x) (*(__I hw_enet_rmon_t_p_gte2048_t *) HW_ENET_RMON_T_P_GTE2048_ADDR(x))
-#define HW_ENET_RMON_T_P_GTE2048_RD(x) (HW_ENET_RMON_T_P_GTE2048(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_T_P_GTE2048 bitfields
- */
-
-/*!
- * @name Register ENET_RMON_T_P_GTE2048, field TXPKTS[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_T_P_GTE2048_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P_GTE2048_TXPKTS.
-#define BM_ENET_RMON_T_P_GTE2048_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P_GTE2048_TXPKTS.
-#define BS_ENET_RMON_T_P_GTE2048_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P_GTE2048_TXPKTS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_T_P_GTE2048_TXPKTS field.
-#define BR_ENET_RMON_T_P_GTE2048_TXPKTS(x) (HW_ENET_RMON_T_P_GTE2048(x).B.TXPKTS)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rmon_t_octets
-{
- uint32_t U;
- struct _hw_enet_rmon_t_octets_bitfields
- {
- uint32_t TXOCTS : 32; //!< [31:0] Octet count
- } B;
-} hw_enet_rmon_t_octets_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_T_OCTETS register
- */
-//@{
-#define HW_ENET_RMON_T_OCTETS_ADDR(x) (REGS_ENET_BASE(x) + 0x244U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_T_OCTETS(x) (*(__I hw_enet_rmon_t_octets_t *) HW_ENET_RMON_T_OCTETS_ADDR(x))
-#define HW_ENET_RMON_T_OCTETS_RD(x) (HW_ENET_RMON_T_OCTETS(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_T_OCTETS bitfields
- */
-
-/*!
- * @name Register ENET_RMON_T_OCTETS, field TXOCTS[31:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_T_OCTETS_TXOCTS (0U) //!< Bit position for ENET_RMON_T_OCTETS_TXOCTS.
-#define BM_ENET_RMON_T_OCTETS_TXOCTS (0xFFFFFFFFU) //!< Bit mask for ENET_RMON_T_OCTETS_TXOCTS.
-#define BS_ENET_RMON_T_OCTETS_TXOCTS (32U) //!< Bit field size in bits for ENET_RMON_T_OCTETS_TXOCTS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_T_OCTETS_TXOCTS field.
-#define BR_ENET_RMON_T_OCTETS_TXOCTS(x) (HW_ENET_RMON_T_OCTETS(x).U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_ieee_t_frame_ok
-{
- uint32_t U;
- struct _hw_enet_ieee_t_frame_ok_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Frame count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_ieee_t_frame_ok_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_IEEE_T_FRAME_OK register
- */
-//@{
-#define HW_ENET_IEEE_T_FRAME_OK_ADDR(x) (REGS_ENET_BASE(x) + 0x24CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_IEEE_T_FRAME_OK(x) (*(__I hw_enet_ieee_t_frame_ok_t *) HW_ENET_IEEE_T_FRAME_OK_ADDR(x))
-#define HW_ENET_IEEE_T_FRAME_OK_RD(x) (HW_ENET_IEEE_T_FRAME_OK(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_IEEE_T_FRAME_OK bitfields
- */
-
-/*!
- * @name Register ENET_IEEE_T_FRAME_OK, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_IEEE_T_FRAME_OK_COUNT (0U) //!< Bit position for ENET_IEEE_T_FRAME_OK_COUNT.
-#define BM_ENET_IEEE_T_FRAME_OK_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_FRAME_OK_COUNT.
-#define BS_ENET_IEEE_T_FRAME_OK_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_FRAME_OK_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_IEEE_T_FRAME_OK_COUNT field.
-#define BR_ENET_IEEE_T_FRAME_OK_COUNT(x) (HW_ENET_IEEE_T_FRAME_OK(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_ieee_t_1col
-{
- uint32_t U;
- struct _hw_enet_ieee_t_1col_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Frame count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_ieee_t_1col_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_IEEE_T_1COL register
- */
-//@{
-#define HW_ENET_IEEE_T_1COL_ADDR(x) (REGS_ENET_BASE(x) + 0x250U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_IEEE_T_1COL(x) (*(__I hw_enet_ieee_t_1col_t *) HW_ENET_IEEE_T_1COL_ADDR(x))
-#define HW_ENET_IEEE_T_1COL_RD(x) (HW_ENET_IEEE_T_1COL(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_IEEE_T_1COL bitfields
- */
-
-/*!
- * @name Register ENET_IEEE_T_1COL, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_IEEE_T_1COL_COUNT (0U) //!< Bit position for ENET_IEEE_T_1COL_COUNT.
-#define BM_ENET_IEEE_T_1COL_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_1COL_COUNT.
-#define BS_ENET_IEEE_T_1COL_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_1COL_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_IEEE_T_1COL_COUNT field.
-#define BR_ENET_IEEE_T_1COL_COUNT(x) (HW_ENET_IEEE_T_1COL(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_ieee_t_mcol
-{
- uint32_t U;
- struct _hw_enet_ieee_t_mcol_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Frame count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_ieee_t_mcol_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_IEEE_T_MCOL register
- */
-//@{
-#define HW_ENET_IEEE_T_MCOL_ADDR(x) (REGS_ENET_BASE(x) + 0x254U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_IEEE_T_MCOL(x) (*(__I hw_enet_ieee_t_mcol_t *) HW_ENET_IEEE_T_MCOL_ADDR(x))
-#define HW_ENET_IEEE_T_MCOL_RD(x) (HW_ENET_IEEE_T_MCOL(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_IEEE_T_MCOL bitfields
- */
-
-/*!
- * @name Register ENET_IEEE_T_MCOL, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_IEEE_T_MCOL_COUNT (0U) //!< Bit position for ENET_IEEE_T_MCOL_COUNT.
-#define BM_ENET_IEEE_T_MCOL_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_MCOL_COUNT.
-#define BS_ENET_IEEE_T_MCOL_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_MCOL_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_IEEE_T_MCOL_COUNT field.
-#define BR_ENET_IEEE_T_MCOL_COUNT(x) (HW_ENET_IEEE_T_MCOL(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_ieee_t_def
-{
- uint32_t U;
- struct _hw_enet_ieee_t_def_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Frame count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_ieee_t_def_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_IEEE_T_DEF register
- */
-//@{
-#define HW_ENET_IEEE_T_DEF_ADDR(x) (REGS_ENET_BASE(x) + 0x258U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_IEEE_T_DEF(x) (*(__I hw_enet_ieee_t_def_t *) HW_ENET_IEEE_T_DEF_ADDR(x))
-#define HW_ENET_IEEE_T_DEF_RD(x) (HW_ENET_IEEE_T_DEF(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_IEEE_T_DEF bitfields
- */
-
-/*!
- * @name Register ENET_IEEE_T_DEF, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_IEEE_T_DEF_COUNT (0U) //!< Bit position for ENET_IEEE_T_DEF_COUNT.
-#define BM_ENET_IEEE_T_DEF_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_DEF_COUNT.
-#define BS_ENET_IEEE_T_DEF_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_DEF_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_IEEE_T_DEF_COUNT field.
-#define BR_ENET_IEEE_T_DEF_COUNT(x) (HW_ENET_IEEE_T_DEF(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_ieee_t_lcol
-{
- uint32_t U;
- struct _hw_enet_ieee_t_lcol_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Frame count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_ieee_t_lcol_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_IEEE_T_LCOL register
- */
-//@{
-#define HW_ENET_IEEE_T_LCOL_ADDR(x) (REGS_ENET_BASE(x) + 0x25CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_IEEE_T_LCOL(x) (*(__I hw_enet_ieee_t_lcol_t *) HW_ENET_IEEE_T_LCOL_ADDR(x))
-#define HW_ENET_IEEE_T_LCOL_RD(x) (HW_ENET_IEEE_T_LCOL(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_IEEE_T_LCOL bitfields
- */
-
-/*!
- * @name Register ENET_IEEE_T_LCOL, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_IEEE_T_LCOL_COUNT (0U) //!< Bit position for ENET_IEEE_T_LCOL_COUNT.
-#define BM_ENET_IEEE_T_LCOL_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_LCOL_COUNT.
-#define BS_ENET_IEEE_T_LCOL_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_LCOL_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_IEEE_T_LCOL_COUNT field.
-#define BR_ENET_IEEE_T_LCOL_COUNT(x) (HW_ENET_IEEE_T_LCOL(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_ieee_t_excol
-{
- uint32_t U;
- struct _hw_enet_ieee_t_excol_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Frame count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_ieee_t_excol_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_IEEE_T_EXCOL register
- */
-//@{
-#define HW_ENET_IEEE_T_EXCOL_ADDR(x) (REGS_ENET_BASE(x) + 0x260U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_IEEE_T_EXCOL(x) (*(__I hw_enet_ieee_t_excol_t *) HW_ENET_IEEE_T_EXCOL_ADDR(x))
-#define HW_ENET_IEEE_T_EXCOL_RD(x) (HW_ENET_IEEE_T_EXCOL(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_IEEE_T_EXCOL bitfields
- */
-
-/*!
- * @name Register ENET_IEEE_T_EXCOL, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_IEEE_T_EXCOL_COUNT (0U) //!< Bit position for ENET_IEEE_T_EXCOL_COUNT.
-#define BM_ENET_IEEE_T_EXCOL_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_EXCOL_COUNT.
-#define BS_ENET_IEEE_T_EXCOL_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_EXCOL_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_IEEE_T_EXCOL_COUNT field.
-#define BR_ENET_IEEE_T_EXCOL_COUNT(x) (HW_ENET_IEEE_T_EXCOL(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_ieee_t_macerr
-{
- uint32_t U;
- struct _hw_enet_ieee_t_macerr_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Frame count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_ieee_t_macerr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_IEEE_T_MACERR register
- */
-//@{
-#define HW_ENET_IEEE_T_MACERR_ADDR(x) (REGS_ENET_BASE(x) + 0x264U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_IEEE_T_MACERR(x) (*(__I hw_enet_ieee_t_macerr_t *) HW_ENET_IEEE_T_MACERR_ADDR(x))
-#define HW_ENET_IEEE_T_MACERR_RD(x) (HW_ENET_IEEE_T_MACERR(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_IEEE_T_MACERR bitfields
- */
-
-/*!
- * @name Register ENET_IEEE_T_MACERR, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_IEEE_T_MACERR_COUNT (0U) //!< Bit position for ENET_IEEE_T_MACERR_COUNT.
-#define BM_ENET_IEEE_T_MACERR_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_MACERR_COUNT.
-#define BS_ENET_IEEE_T_MACERR_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_MACERR_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_IEEE_T_MACERR_COUNT field.
-#define BR_ENET_IEEE_T_MACERR_COUNT(x) (HW_ENET_IEEE_T_MACERR(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_ieee_t_cserr
-{
- uint32_t U;
- struct _hw_enet_ieee_t_cserr_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Frame count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_ieee_t_cserr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_IEEE_T_CSERR register
- */
-//@{
-#define HW_ENET_IEEE_T_CSERR_ADDR(x) (REGS_ENET_BASE(x) + 0x268U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_IEEE_T_CSERR(x) (*(__I hw_enet_ieee_t_cserr_t *) HW_ENET_IEEE_T_CSERR_ADDR(x))
-#define HW_ENET_IEEE_T_CSERR_RD(x) (HW_ENET_IEEE_T_CSERR(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_IEEE_T_CSERR bitfields
- */
-
-/*!
- * @name Register ENET_IEEE_T_CSERR, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_IEEE_T_CSERR_COUNT (0U) //!< Bit position for ENET_IEEE_T_CSERR_COUNT.
-#define BM_ENET_IEEE_T_CSERR_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_CSERR_COUNT.
-#define BS_ENET_IEEE_T_CSERR_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_CSERR_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_IEEE_T_CSERR_COUNT field.
-#define BR_ENET_IEEE_T_CSERR_COUNT(x) (HW_ENET_IEEE_T_CSERR(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_ieee_t_fdxfc
-{
- uint32_t U;
- struct _hw_enet_ieee_t_fdxfc_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Frame count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_ieee_t_fdxfc_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_IEEE_T_FDXFC register
- */
-//@{
-#define HW_ENET_IEEE_T_FDXFC_ADDR(x) (REGS_ENET_BASE(x) + 0x270U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_IEEE_T_FDXFC(x) (*(__I hw_enet_ieee_t_fdxfc_t *) HW_ENET_IEEE_T_FDXFC_ADDR(x))
-#define HW_ENET_IEEE_T_FDXFC_RD(x) (HW_ENET_IEEE_T_FDXFC(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_IEEE_T_FDXFC bitfields
- */
-
-/*!
- * @name Register ENET_IEEE_T_FDXFC, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_IEEE_T_FDXFC_COUNT (0U) //!< Bit position for ENET_IEEE_T_FDXFC_COUNT.
-#define BM_ENET_IEEE_T_FDXFC_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_FDXFC_COUNT.
-#define BS_ENET_IEEE_T_FDXFC_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_FDXFC_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_IEEE_T_FDXFC_COUNT field.
-#define BR_ENET_IEEE_T_FDXFC_COUNT(x) (HW_ENET_IEEE_T_FDXFC(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- *
- * Counts total octets (includes header and FCS fields).
- */
-typedef union _hw_enet_ieee_t_octets_ok
-{
- uint32_t U;
- struct _hw_enet_ieee_t_octets_ok_bitfields
- {
- uint32_t COUNT : 32; //!< [31:0] Octet count
- } B;
-} hw_enet_ieee_t_octets_ok_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_IEEE_T_OCTETS_OK register
- */
-//@{
-#define HW_ENET_IEEE_T_OCTETS_OK_ADDR(x) (REGS_ENET_BASE(x) + 0x274U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_IEEE_T_OCTETS_OK(x) (*(__I hw_enet_ieee_t_octets_ok_t *) HW_ENET_IEEE_T_OCTETS_OK_ADDR(x))
-#define HW_ENET_IEEE_T_OCTETS_OK_RD(x) (HW_ENET_IEEE_T_OCTETS_OK(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_IEEE_T_OCTETS_OK bitfields
- */
-
-/*!
- * @name Register ENET_IEEE_T_OCTETS_OK, field COUNT[31:0] (RO)
- */
-//@{
-#define BP_ENET_IEEE_T_OCTETS_OK_COUNT (0U) //!< Bit position for ENET_IEEE_T_OCTETS_OK_COUNT.
-#define BM_ENET_IEEE_T_OCTETS_OK_COUNT (0xFFFFFFFFU) //!< Bit mask for ENET_IEEE_T_OCTETS_OK_COUNT.
-#define BS_ENET_IEEE_T_OCTETS_OK_COUNT (32U) //!< Bit field size in bits for ENET_IEEE_T_OCTETS_OK_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_IEEE_T_OCTETS_OK_COUNT field.
-#define BR_ENET_IEEE_T_OCTETS_OK_COUNT(x) (HW_ENET_IEEE_T_OCTETS_OK(x).U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rmon_r_packets
-{
- uint32_t U;
- struct _hw_enet_rmon_r_packets_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Packet count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_r_packets_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_R_PACKETS register
- */
-//@{
-#define HW_ENET_RMON_R_PACKETS_ADDR(x) (REGS_ENET_BASE(x) + 0x284U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_R_PACKETS(x) (*(__I hw_enet_rmon_r_packets_t *) HW_ENET_RMON_R_PACKETS_ADDR(x))
-#define HW_ENET_RMON_R_PACKETS_RD(x) (HW_ENET_RMON_R_PACKETS(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_R_PACKETS bitfields
- */
-
-/*!
- * @name Register ENET_RMON_R_PACKETS, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_R_PACKETS_COUNT (0U) //!< Bit position for ENET_RMON_R_PACKETS_COUNT.
-#define BM_ENET_RMON_R_PACKETS_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_PACKETS_COUNT.
-#define BS_ENET_RMON_R_PACKETS_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_PACKETS_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_R_PACKETS_COUNT field.
-#define BR_ENET_RMON_R_PACKETS_COUNT(x) (HW_ENET_RMON_R_PACKETS(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rmon_r_bc_pkt
-{
- uint32_t U;
- struct _hw_enet_rmon_r_bc_pkt_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Packet count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_r_bc_pkt_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_R_BC_PKT register
- */
-//@{
-#define HW_ENET_RMON_R_BC_PKT_ADDR(x) (REGS_ENET_BASE(x) + 0x288U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_R_BC_PKT(x) (*(__I hw_enet_rmon_r_bc_pkt_t *) HW_ENET_RMON_R_BC_PKT_ADDR(x))
-#define HW_ENET_RMON_R_BC_PKT_RD(x) (HW_ENET_RMON_R_BC_PKT(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_R_BC_PKT bitfields
- */
-
-/*!
- * @name Register ENET_RMON_R_BC_PKT, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_R_BC_PKT_COUNT (0U) //!< Bit position for ENET_RMON_R_BC_PKT_COUNT.
-#define BM_ENET_RMON_R_BC_PKT_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_BC_PKT_COUNT.
-#define BS_ENET_RMON_R_BC_PKT_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_BC_PKT_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_R_BC_PKT_COUNT field.
-#define BR_ENET_RMON_R_BC_PKT_COUNT(x) (HW_ENET_RMON_R_BC_PKT(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rmon_r_mc_pkt
-{
- uint32_t U;
- struct _hw_enet_rmon_r_mc_pkt_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Packet count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_r_mc_pkt_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_R_MC_PKT register
- */
-//@{
-#define HW_ENET_RMON_R_MC_PKT_ADDR(x) (REGS_ENET_BASE(x) + 0x28CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_R_MC_PKT(x) (*(__I hw_enet_rmon_r_mc_pkt_t *) HW_ENET_RMON_R_MC_PKT_ADDR(x))
-#define HW_ENET_RMON_R_MC_PKT_RD(x) (HW_ENET_RMON_R_MC_PKT(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_R_MC_PKT bitfields
- */
-
-/*!
- * @name Register ENET_RMON_R_MC_PKT, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_R_MC_PKT_COUNT (0U) //!< Bit position for ENET_RMON_R_MC_PKT_COUNT.
-#define BM_ENET_RMON_R_MC_PKT_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_MC_PKT_COUNT.
-#define BS_ENET_RMON_R_MC_PKT_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_MC_PKT_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_R_MC_PKT_COUNT field.
-#define BR_ENET_RMON_R_MC_PKT_COUNT(x) (HW_ENET_RMON_R_MC_PKT(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rmon_r_crc_align
-{
- uint32_t U;
- struct _hw_enet_rmon_r_crc_align_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Packet count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_r_crc_align_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_R_CRC_ALIGN register
- */
-//@{
-#define HW_ENET_RMON_R_CRC_ALIGN_ADDR(x) (REGS_ENET_BASE(x) + 0x290U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_R_CRC_ALIGN(x) (*(__I hw_enet_rmon_r_crc_align_t *) HW_ENET_RMON_R_CRC_ALIGN_ADDR(x))
-#define HW_ENET_RMON_R_CRC_ALIGN_RD(x) (HW_ENET_RMON_R_CRC_ALIGN(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_R_CRC_ALIGN bitfields
- */
-
-/*!
- * @name Register ENET_RMON_R_CRC_ALIGN, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_R_CRC_ALIGN_COUNT (0U) //!< Bit position for ENET_RMON_R_CRC_ALIGN_COUNT.
-#define BM_ENET_RMON_R_CRC_ALIGN_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_CRC_ALIGN_COUNT.
-#define BS_ENET_RMON_R_CRC_ALIGN_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_CRC_ALIGN_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_R_CRC_ALIGN_COUNT field.
-#define BR_ENET_RMON_R_CRC_ALIGN_COUNT(x) (HW_ENET_RMON_R_CRC_ALIGN(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rmon_r_undersize
-{
- uint32_t U;
- struct _hw_enet_rmon_r_undersize_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Packet count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_r_undersize_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_R_UNDERSIZE register
- */
-//@{
-#define HW_ENET_RMON_R_UNDERSIZE_ADDR(x) (REGS_ENET_BASE(x) + 0x294U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_R_UNDERSIZE(x) (*(__I hw_enet_rmon_r_undersize_t *) HW_ENET_RMON_R_UNDERSIZE_ADDR(x))
-#define HW_ENET_RMON_R_UNDERSIZE_RD(x) (HW_ENET_RMON_R_UNDERSIZE(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_R_UNDERSIZE bitfields
- */
-
-/*!
- * @name Register ENET_RMON_R_UNDERSIZE, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_R_UNDERSIZE_COUNT (0U) //!< Bit position for ENET_RMON_R_UNDERSIZE_COUNT.
-#define BM_ENET_RMON_R_UNDERSIZE_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_UNDERSIZE_COUNT.
-#define BS_ENET_RMON_R_UNDERSIZE_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_UNDERSIZE_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_R_UNDERSIZE_COUNT field.
-#define BR_ENET_RMON_R_UNDERSIZE_COUNT(x) (HW_ENET_RMON_R_UNDERSIZE(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rmon_r_oversize
-{
- uint32_t U;
- struct _hw_enet_rmon_r_oversize_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Packet count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_r_oversize_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_R_OVERSIZE register
- */
-//@{
-#define HW_ENET_RMON_R_OVERSIZE_ADDR(x) (REGS_ENET_BASE(x) + 0x298U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_R_OVERSIZE(x) (*(__I hw_enet_rmon_r_oversize_t *) HW_ENET_RMON_R_OVERSIZE_ADDR(x))
-#define HW_ENET_RMON_R_OVERSIZE_RD(x) (HW_ENET_RMON_R_OVERSIZE(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_R_OVERSIZE bitfields
- */
-
-/*!
- * @name Register ENET_RMON_R_OVERSIZE, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_R_OVERSIZE_COUNT (0U) //!< Bit position for ENET_RMON_R_OVERSIZE_COUNT.
-#define BM_ENET_RMON_R_OVERSIZE_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_OVERSIZE_COUNT.
-#define BS_ENET_RMON_R_OVERSIZE_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_OVERSIZE_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_R_OVERSIZE_COUNT field.
-#define BR_ENET_RMON_R_OVERSIZE_COUNT(x) (HW_ENET_RMON_R_OVERSIZE(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rmon_r_frag
-{
- uint32_t U;
- struct _hw_enet_rmon_r_frag_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Packet count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_r_frag_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_R_FRAG register
- */
-//@{
-#define HW_ENET_RMON_R_FRAG_ADDR(x) (REGS_ENET_BASE(x) + 0x29CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_R_FRAG(x) (*(__I hw_enet_rmon_r_frag_t *) HW_ENET_RMON_R_FRAG_ADDR(x))
-#define HW_ENET_RMON_R_FRAG_RD(x) (HW_ENET_RMON_R_FRAG(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_R_FRAG bitfields
- */
-
-/*!
- * @name Register ENET_RMON_R_FRAG, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_R_FRAG_COUNT (0U) //!< Bit position for ENET_RMON_R_FRAG_COUNT.
-#define BM_ENET_RMON_R_FRAG_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_FRAG_COUNT.
-#define BS_ENET_RMON_R_FRAG_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_FRAG_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_R_FRAG_COUNT field.
-#define BR_ENET_RMON_R_FRAG_COUNT(x) (HW_ENET_RMON_R_FRAG(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rmon_r_jab
-{
- uint32_t U;
- struct _hw_enet_rmon_r_jab_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Packet count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_r_jab_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_R_JAB register
- */
-//@{
-#define HW_ENET_RMON_R_JAB_ADDR(x) (REGS_ENET_BASE(x) + 0x2A0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_R_JAB(x) (*(__I hw_enet_rmon_r_jab_t *) HW_ENET_RMON_R_JAB_ADDR(x))
-#define HW_ENET_RMON_R_JAB_RD(x) (HW_ENET_RMON_R_JAB(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_R_JAB bitfields
- */
-
-/*!
- * @name Register ENET_RMON_R_JAB, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_R_JAB_COUNT (0U) //!< Bit position for ENET_RMON_R_JAB_COUNT.
-#define BM_ENET_RMON_R_JAB_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_JAB_COUNT.
-#define BS_ENET_RMON_R_JAB_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_JAB_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_R_JAB_COUNT field.
-#define BR_ENET_RMON_R_JAB_COUNT(x) (HW_ENET_RMON_R_JAB(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rmon_r_p64
-{
- uint32_t U;
- struct _hw_enet_rmon_r_p64_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Packet count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_r_p64_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_R_P64 register
- */
-//@{
-#define HW_ENET_RMON_R_P64_ADDR(x) (REGS_ENET_BASE(x) + 0x2A8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_R_P64(x) (*(__I hw_enet_rmon_r_p64_t *) HW_ENET_RMON_R_P64_ADDR(x))
-#define HW_ENET_RMON_R_P64_RD(x) (HW_ENET_RMON_R_P64(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_R_P64 bitfields
- */
-
-/*!
- * @name Register ENET_RMON_R_P64, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_R_P64_COUNT (0U) //!< Bit position for ENET_RMON_R_P64_COUNT.
-#define BM_ENET_RMON_R_P64_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P64_COUNT.
-#define BS_ENET_RMON_R_P64_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_P64_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_R_P64_COUNT field.
-#define BR_ENET_RMON_R_P64_COUNT(x) (HW_ENET_RMON_R_P64(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rmon_r_p65to127
-{
- uint32_t U;
- struct _hw_enet_rmon_r_p65to127_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Packet count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_r_p65to127_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_R_P65TO127 register
- */
-//@{
-#define HW_ENET_RMON_R_P65TO127_ADDR(x) (REGS_ENET_BASE(x) + 0x2ACU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_R_P65TO127(x) (*(__I hw_enet_rmon_r_p65to127_t *) HW_ENET_RMON_R_P65TO127_ADDR(x))
-#define HW_ENET_RMON_R_P65TO127_RD(x) (HW_ENET_RMON_R_P65TO127(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_R_P65TO127 bitfields
- */
-
-/*!
- * @name Register ENET_RMON_R_P65TO127, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_R_P65TO127_COUNT (0U) //!< Bit position for ENET_RMON_R_P65TO127_COUNT.
-#define BM_ENET_RMON_R_P65TO127_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P65TO127_COUNT.
-#define BS_ENET_RMON_R_P65TO127_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_P65TO127_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_R_P65TO127_COUNT field.
-#define BR_ENET_RMON_R_P65TO127_COUNT(x) (HW_ENET_RMON_R_P65TO127(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rmon_r_p128to255
-{
- uint32_t U;
- struct _hw_enet_rmon_r_p128to255_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Packet count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_r_p128to255_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_R_P128TO255 register
- */
-//@{
-#define HW_ENET_RMON_R_P128TO255_ADDR(x) (REGS_ENET_BASE(x) + 0x2B0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_R_P128TO255(x) (*(__I hw_enet_rmon_r_p128to255_t *) HW_ENET_RMON_R_P128TO255_ADDR(x))
-#define HW_ENET_RMON_R_P128TO255_RD(x) (HW_ENET_RMON_R_P128TO255(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_R_P128TO255 bitfields
- */
-
-/*!
- * @name Register ENET_RMON_R_P128TO255, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_R_P128TO255_COUNT (0U) //!< Bit position for ENET_RMON_R_P128TO255_COUNT.
-#define BM_ENET_RMON_R_P128TO255_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P128TO255_COUNT.
-#define BS_ENET_RMON_R_P128TO255_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_P128TO255_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_R_P128TO255_COUNT field.
-#define BR_ENET_RMON_R_P128TO255_COUNT(x) (HW_ENET_RMON_R_P128TO255(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rmon_r_p256to511
-{
- uint32_t U;
- struct _hw_enet_rmon_r_p256to511_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Packet count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_r_p256to511_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_R_P256TO511 register
- */
-//@{
-#define HW_ENET_RMON_R_P256TO511_ADDR(x) (REGS_ENET_BASE(x) + 0x2B4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_R_P256TO511(x) (*(__I hw_enet_rmon_r_p256to511_t *) HW_ENET_RMON_R_P256TO511_ADDR(x))
-#define HW_ENET_RMON_R_P256TO511_RD(x) (HW_ENET_RMON_R_P256TO511(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_R_P256TO511 bitfields
- */
-
-/*!
- * @name Register ENET_RMON_R_P256TO511, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_R_P256TO511_COUNT (0U) //!< Bit position for ENET_RMON_R_P256TO511_COUNT.
-#define BM_ENET_RMON_R_P256TO511_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P256TO511_COUNT.
-#define BS_ENET_RMON_R_P256TO511_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_P256TO511_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_R_P256TO511_COUNT field.
-#define BR_ENET_RMON_R_P256TO511_COUNT(x) (HW_ENET_RMON_R_P256TO511(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rmon_r_p512to1023
-{
- uint32_t U;
- struct _hw_enet_rmon_r_p512to1023_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Packet count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_r_p512to1023_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_R_P512TO1023 register
- */
-//@{
-#define HW_ENET_RMON_R_P512TO1023_ADDR(x) (REGS_ENET_BASE(x) + 0x2B8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_R_P512TO1023(x) (*(__I hw_enet_rmon_r_p512to1023_t *) HW_ENET_RMON_R_P512TO1023_ADDR(x))
-#define HW_ENET_RMON_R_P512TO1023_RD(x) (HW_ENET_RMON_R_P512TO1023(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_R_P512TO1023 bitfields
- */
-
-/*!
- * @name Register ENET_RMON_R_P512TO1023, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_R_P512TO1023_COUNT (0U) //!< Bit position for ENET_RMON_R_P512TO1023_COUNT.
-#define BM_ENET_RMON_R_P512TO1023_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P512TO1023_COUNT.
-#define BS_ENET_RMON_R_P512TO1023_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_P512TO1023_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_R_P512TO1023_COUNT field.
-#define BR_ENET_RMON_R_P512TO1023_COUNT(x) (HW_ENET_RMON_R_P512TO1023(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rmon_r_p1024to2047
-{
- uint32_t U;
- struct _hw_enet_rmon_r_p1024to2047_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Packet count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_r_p1024to2047_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_R_P1024TO2047 register
- */
-//@{
-#define HW_ENET_RMON_R_P1024TO2047_ADDR(x) (REGS_ENET_BASE(x) + 0x2BCU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_R_P1024TO2047(x) (*(__I hw_enet_rmon_r_p1024to2047_t *) HW_ENET_RMON_R_P1024TO2047_ADDR(x))
-#define HW_ENET_RMON_R_P1024TO2047_RD(x) (HW_ENET_RMON_R_P1024TO2047(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_R_P1024TO2047 bitfields
- */
-
-/*!
- * @name Register ENET_RMON_R_P1024TO2047, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_R_P1024TO2047_COUNT (0U) //!< Bit position for ENET_RMON_R_P1024TO2047_COUNT.
-#define BM_ENET_RMON_R_P1024TO2047_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P1024TO2047_COUNT.
-#define BS_ENET_RMON_R_P1024TO2047_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_P1024TO2047_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_R_P1024TO2047_COUNT field.
-#define BR_ENET_RMON_R_P1024TO2047_COUNT(x) (HW_ENET_RMON_R_P1024TO2047(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_R_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_R_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rmon_r_gte2048
-{
- uint32_t U;
- struct _hw_enet_rmon_r_gte2048_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Packet count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_rmon_r_gte2048_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_R_GTE2048 register
- */
-//@{
-#define HW_ENET_RMON_R_GTE2048_ADDR(x) (REGS_ENET_BASE(x) + 0x2C0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_R_GTE2048(x) (*(__I hw_enet_rmon_r_gte2048_t *) HW_ENET_RMON_R_GTE2048_ADDR(x))
-#define HW_ENET_RMON_R_GTE2048_RD(x) (HW_ENET_RMON_R_GTE2048(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_R_GTE2048 bitfields
- */
-
-/*!
- * @name Register ENET_RMON_R_GTE2048, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_R_GTE2048_COUNT (0U) //!< Bit position for ENET_RMON_R_GTE2048_COUNT.
-#define BM_ENET_RMON_R_GTE2048_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_GTE2048_COUNT.
-#define BS_ENET_RMON_R_GTE2048_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_GTE2048_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_R_GTE2048_COUNT field.
-#define BR_ENET_RMON_R_GTE2048_COUNT(x) (HW_ENET_RMON_R_GTE2048(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_rmon_r_octets
-{
- uint32_t U;
- struct _hw_enet_rmon_r_octets_bitfields
- {
- uint32_t COUNT : 32; //!< [31:0] Octet count
- } B;
-} hw_enet_rmon_r_octets_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_RMON_R_OCTETS register
- */
-//@{
-#define HW_ENET_RMON_R_OCTETS_ADDR(x) (REGS_ENET_BASE(x) + 0x2C4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_RMON_R_OCTETS(x) (*(__I hw_enet_rmon_r_octets_t *) HW_ENET_RMON_R_OCTETS_ADDR(x))
-#define HW_ENET_RMON_R_OCTETS_RD(x) (HW_ENET_RMON_R_OCTETS(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_RMON_R_OCTETS bitfields
- */
-
-/*!
- * @name Register ENET_RMON_R_OCTETS, field COUNT[31:0] (RO)
- */
-//@{
-#define BP_ENET_RMON_R_OCTETS_COUNT (0U) //!< Bit position for ENET_RMON_R_OCTETS_COUNT.
-#define BM_ENET_RMON_R_OCTETS_COUNT (0xFFFFFFFFU) //!< Bit mask for ENET_RMON_R_OCTETS_COUNT.
-#define BS_ENET_RMON_R_OCTETS_COUNT (32U) //!< Bit field size in bits for ENET_RMON_R_OCTETS_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_RMON_R_OCTETS_COUNT field.
-#define BR_ENET_RMON_R_OCTETS_COUNT(x) (HW_ENET_RMON_R_OCTETS(x).U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- *
- * Counter increments if a frame with invalid or missing SFD character is
- * detected and has been dropped. None of the other counters increments if this counter
- * increments.
- */
-typedef union _hw_enet_ieee_r_drop
-{
- uint32_t U;
- struct _hw_enet_ieee_r_drop_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Frame count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_ieee_r_drop_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_IEEE_R_DROP register
- */
-//@{
-#define HW_ENET_IEEE_R_DROP_ADDR(x) (REGS_ENET_BASE(x) + 0x2C8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_IEEE_R_DROP(x) (*(__I hw_enet_ieee_r_drop_t *) HW_ENET_IEEE_R_DROP_ADDR(x))
-#define HW_ENET_IEEE_R_DROP_RD(x) (HW_ENET_IEEE_R_DROP(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_IEEE_R_DROP bitfields
- */
-
-/*!
- * @name Register ENET_IEEE_R_DROP, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_IEEE_R_DROP_COUNT (0U) //!< Bit position for ENET_IEEE_R_DROP_COUNT.
-#define BM_ENET_IEEE_R_DROP_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_DROP_COUNT.
-#define BS_ENET_IEEE_R_DROP_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_R_DROP_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_IEEE_R_DROP_COUNT field.
-#define BR_ENET_IEEE_R_DROP_COUNT(x) (HW_ENET_IEEE_R_DROP(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_ieee_r_frame_ok
-{
- uint32_t U;
- struct _hw_enet_ieee_r_frame_ok_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Frame count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_ieee_r_frame_ok_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_IEEE_R_FRAME_OK register
- */
-//@{
-#define HW_ENET_IEEE_R_FRAME_OK_ADDR(x) (REGS_ENET_BASE(x) + 0x2CCU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_IEEE_R_FRAME_OK(x) (*(__I hw_enet_ieee_r_frame_ok_t *) HW_ENET_IEEE_R_FRAME_OK_ADDR(x))
-#define HW_ENET_IEEE_R_FRAME_OK_RD(x) (HW_ENET_IEEE_R_FRAME_OK(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_IEEE_R_FRAME_OK bitfields
- */
-
-/*!
- * @name Register ENET_IEEE_R_FRAME_OK, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_IEEE_R_FRAME_OK_COUNT (0U) //!< Bit position for ENET_IEEE_R_FRAME_OK_COUNT.
-#define BM_ENET_IEEE_R_FRAME_OK_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_FRAME_OK_COUNT.
-#define BS_ENET_IEEE_R_FRAME_OK_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_R_FRAME_OK_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_IEEE_R_FRAME_OK_COUNT field.
-#define BR_ENET_IEEE_R_FRAME_OK_COUNT(x) (HW_ENET_IEEE_R_FRAME_OK(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_ieee_r_crc
-{
- uint32_t U;
- struct _hw_enet_ieee_r_crc_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Frame count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_ieee_r_crc_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_IEEE_R_CRC register
- */
-//@{
-#define HW_ENET_IEEE_R_CRC_ADDR(x) (REGS_ENET_BASE(x) + 0x2D0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_IEEE_R_CRC(x) (*(__I hw_enet_ieee_r_crc_t *) HW_ENET_IEEE_R_CRC_ADDR(x))
-#define HW_ENET_IEEE_R_CRC_RD(x) (HW_ENET_IEEE_R_CRC(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_IEEE_R_CRC bitfields
- */
-
-/*!
- * @name Register ENET_IEEE_R_CRC, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_IEEE_R_CRC_COUNT (0U) //!< Bit position for ENET_IEEE_R_CRC_COUNT.
-#define BM_ENET_IEEE_R_CRC_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_CRC_COUNT.
-#define BS_ENET_IEEE_R_CRC_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_R_CRC_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_IEEE_R_CRC_COUNT field.
-#define BR_ENET_IEEE_R_CRC_COUNT(x) (HW_ENET_IEEE_R_CRC(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_ieee_r_align
-{
- uint32_t U;
- struct _hw_enet_ieee_r_align_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Frame count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_ieee_r_align_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_IEEE_R_ALIGN register
- */
-//@{
-#define HW_ENET_IEEE_R_ALIGN_ADDR(x) (REGS_ENET_BASE(x) + 0x2D4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_IEEE_R_ALIGN(x) (*(__I hw_enet_ieee_r_align_t *) HW_ENET_IEEE_R_ALIGN_ADDR(x))
-#define HW_ENET_IEEE_R_ALIGN_RD(x) (HW_ENET_IEEE_R_ALIGN(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_IEEE_R_ALIGN bitfields
- */
-
-/*!
- * @name Register ENET_IEEE_R_ALIGN, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_IEEE_R_ALIGN_COUNT (0U) //!< Bit position for ENET_IEEE_R_ALIGN_COUNT.
-#define BM_ENET_IEEE_R_ALIGN_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_ALIGN_COUNT.
-#define BS_ENET_IEEE_R_ALIGN_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_R_ALIGN_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_IEEE_R_ALIGN_COUNT field.
-#define BR_ENET_IEEE_R_ALIGN_COUNT(x) (HW_ENET_IEEE_R_ALIGN(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_ieee_r_macerr
-{
- uint32_t U;
- struct _hw_enet_ieee_r_macerr_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_ieee_r_macerr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_IEEE_R_MACERR register
- */
-//@{
-#define HW_ENET_IEEE_R_MACERR_ADDR(x) (REGS_ENET_BASE(x) + 0x2D8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_IEEE_R_MACERR(x) (*(__I hw_enet_ieee_r_macerr_t *) HW_ENET_IEEE_R_MACERR_ADDR(x))
-#define HW_ENET_IEEE_R_MACERR_RD(x) (HW_ENET_IEEE_R_MACERR(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_IEEE_R_MACERR bitfields
- */
-
-/*!
- * @name Register ENET_IEEE_R_MACERR, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_IEEE_R_MACERR_COUNT (0U) //!< Bit position for ENET_IEEE_R_MACERR_COUNT.
-#define BM_ENET_IEEE_R_MACERR_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_MACERR_COUNT.
-#define BS_ENET_IEEE_R_MACERR_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_R_MACERR_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_IEEE_R_MACERR_COUNT field.
-#define BR_ENET_IEEE_R_MACERR_COUNT(x) (HW_ENET_IEEE_R_MACERR(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_ieee_r_fdxfc
-{
- uint32_t U;
- struct _hw_enet_ieee_r_fdxfc_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Pause frame count
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_enet_ieee_r_fdxfc_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_IEEE_R_FDXFC register
- */
-//@{
-#define HW_ENET_IEEE_R_FDXFC_ADDR(x) (REGS_ENET_BASE(x) + 0x2DCU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_IEEE_R_FDXFC(x) (*(__I hw_enet_ieee_r_fdxfc_t *) HW_ENET_IEEE_R_FDXFC_ADDR(x))
-#define HW_ENET_IEEE_R_FDXFC_RD(x) (HW_ENET_IEEE_R_FDXFC(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_IEEE_R_FDXFC bitfields
- */
-
-/*!
- * @name Register ENET_IEEE_R_FDXFC, field COUNT[15:0] (RO)
- */
-//@{
-#define BP_ENET_IEEE_R_FDXFC_COUNT (0U) //!< Bit position for ENET_IEEE_R_FDXFC_COUNT.
-#define BM_ENET_IEEE_R_FDXFC_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_FDXFC_COUNT.
-#define BS_ENET_IEEE_R_FDXFC_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_R_FDXFC_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_IEEE_R_FDXFC_COUNT field.
-#define BR_ENET_IEEE_R_FDXFC_COUNT(x) (HW_ENET_IEEE_R_FDXFC(x).B.COUNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_ieee_r_octets_ok
-{
- uint32_t U;
- struct _hw_enet_ieee_r_octets_ok_bitfields
- {
- uint32_t COUNT : 32; //!< [31:0] Octet count
- } B;
-} hw_enet_ieee_r_octets_ok_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_IEEE_R_OCTETS_OK register
- */
-//@{
-#define HW_ENET_IEEE_R_OCTETS_OK_ADDR(x) (REGS_ENET_BASE(x) + 0x2E0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_IEEE_R_OCTETS_OK(x) (*(__I hw_enet_ieee_r_octets_ok_t *) HW_ENET_IEEE_R_OCTETS_OK_ADDR(x))
-#define HW_ENET_IEEE_R_OCTETS_OK_RD(x) (HW_ENET_IEEE_R_OCTETS_OK(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_IEEE_R_OCTETS_OK bitfields
- */
-
-/*!
- * @name Register ENET_IEEE_R_OCTETS_OK, field COUNT[31:0] (RO)
- */
-//@{
-#define BP_ENET_IEEE_R_OCTETS_OK_COUNT (0U) //!< Bit position for ENET_IEEE_R_OCTETS_OK_COUNT.
-#define BM_ENET_IEEE_R_OCTETS_OK_COUNT (0xFFFFFFFFU) //!< Bit mask for ENET_IEEE_R_OCTETS_OK_COUNT.
-#define BS_ENET_IEEE_R_OCTETS_OK_COUNT (32U) //!< Bit field size in bits for ENET_IEEE_R_OCTETS_OK_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_IEEE_R_OCTETS_OK_COUNT field.
-#define BR_ENET_IEEE_R_OCTETS_OK_COUNT(x) (HW_ENET_IEEE_R_OCTETS_OK(x).U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_ATCR - Adjustable Timer Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_ATCR - Adjustable Timer Control Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * ATCR command fields can trigger the corresponding events directly. It is not
- * necessary to preserve any of the configuration fields when a command field is
- * set in the register, that is, no read-modify-write is required. The fields are
- * automatically cleared after the command completes.
- */
-typedef union _hw_enet_atcr
-{
- uint32_t U;
- struct _hw_enet_atcr_bitfields
- {
- uint32_t EN : 1; //!< [0] Enable Timer
- uint32_t RESERVED0 : 1; //!< [1]
- uint32_t OFFEN : 1; //!< [2] Enable One-Shot Offset Event
- uint32_t OFFRST : 1; //!< [3] Reset Timer On Offset Event
- uint32_t PEREN : 1; //!< [4] Enable Periodical Event
- uint32_t RESERVED1 : 2; //!< [6:5]
- uint32_t PINPER : 1; //!< [7]
- uint32_t RESERVED2 : 1; //!< [8]
- uint32_t RESTART : 1; //!< [9] Reset Timer
- uint32_t RESERVED3 : 1; //!< [10]
- uint32_t CAPTURE : 1; //!< [11] Capture Timer Value
- uint32_t RESERVED4 : 1; //!< [12]
- uint32_t SLAVE : 1; //!< [13] Enable Timer Slave Mode
- uint32_t RESERVED5 : 18; //!< [31:14]
- } B;
-} hw_enet_atcr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_ATCR register
- */
-//@{
-#define HW_ENET_ATCR_ADDR(x) (REGS_ENET_BASE(x) + 0x400U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_ATCR(x) (*(__IO hw_enet_atcr_t *) HW_ENET_ATCR_ADDR(x))
-#define HW_ENET_ATCR_RD(x) (HW_ENET_ATCR(x).U)
-#define HW_ENET_ATCR_WR(x, v) (HW_ENET_ATCR(x).U = (v))
-#define HW_ENET_ATCR_SET(x, v) (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) | (v)))
-#define HW_ENET_ATCR_CLR(x, v) (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) & ~(v)))
-#define HW_ENET_ATCR_TOG(x, v) (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_ATCR bitfields
- */
-
-/*!
- * @name Register ENET_ATCR, field EN[0] (RW)
- *
- * Values:
- * - 0 - The timer stops at the current value.
- * - 1 - The timer starts incrementing.
- */
-//@{
-#define BP_ENET_ATCR_EN (0U) //!< Bit position for ENET_ATCR_EN.
-#define BM_ENET_ATCR_EN (0x00000001U) //!< Bit mask for ENET_ATCR_EN.
-#define BS_ENET_ATCR_EN (1U) //!< Bit field size in bits for ENET_ATCR_EN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_ATCR_EN field.
-#define BR_ENET_ATCR_EN(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_EN))
-#endif
-
-//! @brief Format value for bitfield ENET_ATCR_EN.
-#define BF_ENET_ATCR_EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_EN), uint32_t) & BM_ENET_ATCR_EN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EN field to a new value.
-#define BW_ENET_ATCR_EN(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_EN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_ATCR, field OFFEN[2] (RW)
- *
- * Values:
- * - 0 - Disable.
- * - 1 - The timer can be reset to zero when the given offset time is reached
- * (offset event). The field is cleared when the offset event is reached, so no
- * further event occurs until the field is set again. The timer offset value
- * must be set before setting this field.
- */
-//@{
-#define BP_ENET_ATCR_OFFEN (2U) //!< Bit position for ENET_ATCR_OFFEN.
-#define BM_ENET_ATCR_OFFEN (0x00000004U) //!< Bit mask for ENET_ATCR_OFFEN.
-#define BS_ENET_ATCR_OFFEN (1U) //!< Bit field size in bits for ENET_ATCR_OFFEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_ATCR_OFFEN field.
-#define BR_ENET_ATCR_OFFEN(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFEN))
-#endif
-
-//! @brief Format value for bitfield ENET_ATCR_OFFEN.
-#define BF_ENET_ATCR_OFFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_OFFEN), uint32_t) & BM_ENET_ATCR_OFFEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the OFFEN field to a new value.
-#define BW_ENET_ATCR_OFFEN(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_ATCR, field OFFRST[3] (RW)
- *
- * Values:
- * - 0 - The timer is not affected and no action occurs, besides clearing OFFEN,
- * when the offset is reached.
- * - 1 - If OFFEN is set, the timer resets to zero when the offset setting is
- * reached. The offset event does not cause a timer interrupt.
- */
-//@{
-#define BP_ENET_ATCR_OFFRST (3U) //!< Bit position for ENET_ATCR_OFFRST.
-#define BM_ENET_ATCR_OFFRST (0x00000008U) //!< Bit mask for ENET_ATCR_OFFRST.
-#define BS_ENET_ATCR_OFFRST (1U) //!< Bit field size in bits for ENET_ATCR_OFFRST.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_ATCR_OFFRST field.
-#define BR_ENET_ATCR_OFFRST(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFRST))
-#endif
-
-//! @brief Format value for bitfield ENET_ATCR_OFFRST.
-#define BF_ENET_ATCR_OFFRST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_OFFRST), uint32_t) & BM_ENET_ATCR_OFFRST)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the OFFRST field to a new value.
-#define BW_ENET_ATCR_OFFRST(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFRST) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_ATCR, field PEREN[4] (RW)
- *
- * Values:
- * - 0 - Disable.
- * - 1 - A period event interrupt can be generated (EIR[TS_TIMER]) and the event
- * signal output is asserted when the timer wraps around according to the
- * periodic setting ATPER. The timer period value must be set before setting
- * this bit. Not all devices contain the event signal output. See the chip
- * configuration details.
- */
-//@{
-#define BP_ENET_ATCR_PEREN (4U) //!< Bit position for ENET_ATCR_PEREN.
-#define BM_ENET_ATCR_PEREN (0x00000010U) //!< Bit mask for ENET_ATCR_PEREN.
-#define BS_ENET_ATCR_PEREN (1U) //!< Bit field size in bits for ENET_ATCR_PEREN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_ATCR_PEREN field.
-#define BR_ENET_ATCR_PEREN(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PEREN))
-#endif
-
-//! @brief Format value for bitfield ENET_ATCR_PEREN.
-#define BF_ENET_ATCR_PEREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_PEREN), uint32_t) & BM_ENET_ATCR_PEREN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PEREN field to a new value.
-#define BW_ENET_ATCR_PEREN(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PEREN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_ATCR, field PINPER[7] (RW)
- *
- * Enables event signal output assertion on period event. Not all devices
- * contain the event signal output. See the chip configuration details.
- *
- * Values:
- * - 0 - Disable.
- * - 1 - Enable.
- */
-//@{
-#define BP_ENET_ATCR_PINPER (7U) //!< Bit position for ENET_ATCR_PINPER.
-#define BM_ENET_ATCR_PINPER (0x00000080U) //!< Bit mask for ENET_ATCR_PINPER.
-#define BS_ENET_ATCR_PINPER (1U) //!< Bit field size in bits for ENET_ATCR_PINPER.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_ATCR_PINPER field.
-#define BR_ENET_ATCR_PINPER(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PINPER))
-#endif
-
-//! @brief Format value for bitfield ENET_ATCR_PINPER.
-#define BF_ENET_ATCR_PINPER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_PINPER), uint32_t) & BM_ENET_ATCR_PINPER)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PINPER field to a new value.
-#define BW_ENET_ATCR_PINPER(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PINPER) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_ATCR, field RESTART[9] (RW)
- *
- * Resets the timer to zero. This has no effect on the counter enable. If the
- * counter is enabled when this field is set, the timer is reset to zero and starts
- * counting from there. When set, all other fields are ignored during a write.
- */
-//@{
-#define BP_ENET_ATCR_RESTART (9U) //!< Bit position for ENET_ATCR_RESTART.
-#define BM_ENET_ATCR_RESTART (0x00000200U) //!< Bit mask for ENET_ATCR_RESTART.
-#define BS_ENET_ATCR_RESTART (1U) //!< Bit field size in bits for ENET_ATCR_RESTART.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_ATCR_RESTART field.
-#define BR_ENET_ATCR_RESTART(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_RESTART))
-#endif
-
-//! @brief Format value for bitfield ENET_ATCR_RESTART.
-#define BF_ENET_ATCR_RESTART(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_RESTART), uint32_t) & BM_ENET_ATCR_RESTART)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RESTART field to a new value.
-#define BW_ENET_ATCR_RESTART(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_RESTART) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_ATCR, field CAPTURE[11] (RW)
- *
- * Values:
- * - 0 - No effect.
- * - 1 - The current time is captured and can be read from the ATVR register.
- */
-//@{
-#define BP_ENET_ATCR_CAPTURE (11U) //!< Bit position for ENET_ATCR_CAPTURE.
-#define BM_ENET_ATCR_CAPTURE (0x00000800U) //!< Bit mask for ENET_ATCR_CAPTURE.
-#define BS_ENET_ATCR_CAPTURE (1U) //!< Bit field size in bits for ENET_ATCR_CAPTURE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_ATCR_CAPTURE field.
-#define BR_ENET_ATCR_CAPTURE(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_CAPTURE))
-#endif
-
-//! @brief Format value for bitfield ENET_ATCR_CAPTURE.
-#define BF_ENET_ATCR_CAPTURE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_CAPTURE), uint32_t) & BM_ENET_ATCR_CAPTURE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CAPTURE field to a new value.
-#define BW_ENET_ATCR_CAPTURE(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_CAPTURE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_ATCR, field SLAVE[13] (RW)
- *
- * Values:
- * - 0 - The timer is active and all configuration fields in this register are
- * relevant.
- * - 1 - The internal timer is disabled and the externally provided timer value
- * is used. All other fields, except CAPTURE, in this register have no
- * effect. CAPTURE can still be used to capture the current timer value.
- */
-//@{
-#define BP_ENET_ATCR_SLAVE (13U) //!< Bit position for ENET_ATCR_SLAVE.
-#define BM_ENET_ATCR_SLAVE (0x00002000U) //!< Bit mask for ENET_ATCR_SLAVE.
-#define BS_ENET_ATCR_SLAVE (1U) //!< Bit field size in bits for ENET_ATCR_SLAVE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_ATCR_SLAVE field.
-#define BR_ENET_ATCR_SLAVE(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_SLAVE))
-#endif
-
-//! @brief Format value for bitfield ENET_ATCR_SLAVE.
-#define BF_ENET_ATCR_SLAVE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_SLAVE), uint32_t) & BM_ENET_ATCR_SLAVE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SLAVE field to a new value.
-#define BW_ENET_ATCR_SLAVE(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_SLAVE) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_ATVR - Timer Value Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_ATVR - Timer Value Register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_atvr
-{
- uint32_t U;
- struct _hw_enet_atvr_bitfields
- {
- uint32_t ATIME : 32; //!< [31:0]
- } B;
-} hw_enet_atvr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_ATVR register
- */
-//@{
-#define HW_ENET_ATVR_ADDR(x) (REGS_ENET_BASE(x) + 0x404U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_ATVR(x) (*(__IO hw_enet_atvr_t *) HW_ENET_ATVR_ADDR(x))
-#define HW_ENET_ATVR_RD(x) (HW_ENET_ATVR(x).U)
-#define HW_ENET_ATVR_WR(x, v) (HW_ENET_ATVR(x).U = (v))
-#define HW_ENET_ATVR_SET(x, v) (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) | (v)))
-#define HW_ENET_ATVR_CLR(x, v) (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) & ~(v)))
-#define HW_ENET_ATVR_TOG(x, v) (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_ATVR bitfields
- */
-
-/*!
- * @name Register ENET_ATVR, field ATIME[31:0] (RW)
- *
- * A write sets the timer. A read returns the last captured value. To read the
- * current value, issue a capture command (set ATCR[CAPTURE]) prior to reading
- * this register.
- */
-//@{
-#define BP_ENET_ATVR_ATIME (0U) //!< Bit position for ENET_ATVR_ATIME.
-#define BM_ENET_ATVR_ATIME (0xFFFFFFFFU) //!< Bit mask for ENET_ATVR_ATIME.
-#define BS_ENET_ATVR_ATIME (32U) //!< Bit field size in bits for ENET_ATVR_ATIME.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_ATVR_ATIME field.
-#define BR_ENET_ATVR_ATIME(x) (HW_ENET_ATVR(x).U)
-#endif
-
-//! @brief Format value for bitfield ENET_ATVR_ATIME.
-#define BF_ENET_ATVR_ATIME(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATVR_ATIME), uint32_t) & BM_ENET_ATVR_ATIME)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ATIME field to a new value.
-#define BW_ENET_ATVR_ATIME(x, v) (HW_ENET_ATVR_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_ATOFF - Timer Offset Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_ATOFF - Timer Offset Register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_atoff
-{
- uint32_t U;
- struct _hw_enet_atoff_bitfields
- {
- uint32_t OFFSET : 32; //!< [31:0]
- } B;
-} hw_enet_atoff_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_ATOFF register
- */
-//@{
-#define HW_ENET_ATOFF_ADDR(x) (REGS_ENET_BASE(x) + 0x408U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_ATOFF(x) (*(__IO hw_enet_atoff_t *) HW_ENET_ATOFF_ADDR(x))
-#define HW_ENET_ATOFF_RD(x) (HW_ENET_ATOFF(x).U)
-#define HW_ENET_ATOFF_WR(x, v) (HW_ENET_ATOFF(x).U = (v))
-#define HW_ENET_ATOFF_SET(x, v) (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) | (v)))
-#define HW_ENET_ATOFF_CLR(x, v) (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) & ~(v)))
-#define HW_ENET_ATOFF_TOG(x, v) (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_ATOFF bitfields
- */
-
-/*!
- * @name Register ENET_ATOFF, field OFFSET[31:0] (RW)
- *
- * Offset value for one-shot event generation. When the timer reaches the value,
- * an event can be generated to reset the counter. If the increment value in
- * ATINC is given in true nanoseconds, this value is also given in true nanoseconds.
- */
-//@{
-#define BP_ENET_ATOFF_OFFSET (0U) //!< Bit position for ENET_ATOFF_OFFSET.
-#define BM_ENET_ATOFF_OFFSET (0xFFFFFFFFU) //!< Bit mask for ENET_ATOFF_OFFSET.
-#define BS_ENET_ATOFF_OFFSET (32U) //!< Bit field size in bits for ENET_ATOFF_OFFSET.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_ATOFF_OFFSET field.
-#define BR_ENET_ATOFF_OFFSET(x) (HW_ENET_ATOFF(x).U)
-#endif
-
-//! @brief Format value for bitfield ENET_ATOFF_OFFSET.
-#define BF_ENET_ATOFF_OFFSET(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATOFF_OFFSET), uint32_t) & BM_ENET_ATOFF_OFFSET)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the OFFSET field to a new value.
-#define BW_ENET_ATOFF_OFFSET(x, v) (HW_ENET_ATOFF_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_ATPER - Timer Period Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_ATPER - Timer Period Register (RW)
- *
- * Reset value: 0x3B9ACA00U
- */
-typedef union _hw_enet_atper
-{
- uint32_t U;
- struct _hw_enet_atper_bitfields
- {
- uint32_t PERIOD : 32; //!< [31:0]
- } B;
-} hw_enet_atper_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_ATPER register
- */
-//@{
-#define HW_ENET_ATPER_ADDR(x) (REGS_ENET_BASE(x) + 0x40CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_ATPER(x) (*(__IO hw_enet_atper_t *) HW_ENET_ATPER_ADDR(x))
-#define HW_ENET_ATPER_RD(x) (HW_ENET_ATPER(x).U)
-#define HW_ENET_ATPER_WR(x, v) (HW_ENET_ATPER(x).U = (v))
-#define HW_ENET_ATPER_SET(x, v) (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) | (v)))
-#define HW_ENET_ATPER_CLR(x, v) (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) & ~(v)))
-#define HW_ENET_ATPER_TOG(x, v) (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_ATPER bitfields
- */
-
-/*!
- * @name Register ENET_ATPER, field PERIOD[31:0] (RW)
- *
- * Value for generating periodic events. Each instance the timer reaches this
- * value, the period event occurs and the timer restarts. If the increment value in
- * ATINC is given in true nanoseconds, this value is also given in true
- * nanoseconds. The value should be initialized to 1,000,000,000 (1 x 10 9 ) to represent
- * a timer wrap around of one second. The increment value set in ATINC should be
- * set to the true nanoseconds of the period of clock ts_clk, hence implementing
- * a true 1 second counter.
- */
-//@{
-#define BP_ENET_ATPER_PERIOD (0U) //!< Bit position for ENET_ATPER_PERIOD.
-#define BM_ENET_ATPER_PERIOD (0xFFFFFFFFU) //!< Bit mask for ENET_ATPER_PERIOD.
-#define BS_ENET_ATPER_PERIOD (32U) //!< Bit field size in bits for ENET_ATPER_PERIOD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_ATPER_PERIOD field.
-#define BR_ENET_ATPER_PERIOD(x) (HW_ENET_ATPER(x).U)
-#endif
-
-//! @brief Format value for bitfield ENET_ATPER_PERIOD.
-#define BF_ENET_ATPER_PERIOD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATPER_PERIOD), uint32_t) & BM_ENET_ATPER_PERIOD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PERIOD field to a new value.
-#define BW_ENET_ATPER_PERIOD(x, v) (HW_ENET_ATPER_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_ATCOR - Timer Correction Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_ATCOR - Timer Correction Register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_atcor
-{
- uint32_t U;
- struct _hw_enet_atcor_bitfields
- {
- uint32_t COR : 31; //!< [30:0] Correction Counter Wrap-Around Value
- uint32_t RESERVED0 : 1; //!< [31]
- } B;
-} hw_enet_atcor_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_ATCOR register
- */
-//@{
-#define HW_ENET_ATCOR_ADDR(x) (REGS_ENET_BASE(x) + 0x410U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_ATCOR(x) (*(__IO hw_enet_atcor_t *) HW_ENET_ATCOR_ADDR(x))
-#define HW_ENET_ATCOR_RD(x) (HW_ENET_ATCOR(x).U)
-#define HW_ENET_ATCOR_WR(x, v) (HW_ENET_ATCOR(x).U = (v))
-#define HW_ENET_ATCOR_SET(x, v) (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) | (v)))
-#define HW_ENET_ATCOR_CLR(x, v) (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) & ~(v)))
-#define HW_ENET_ATCOR_TOG(x, v) (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_ATCOR bitfields
- */
-
-/*!
- * @name Register ENET_ATCOR, field COR[30:0] (RW)
- *
- * Defines after how many timer clock cycles (ts_clk) the correction counter
- * should be reset and trigger a correction increment on the timer. The amount of
- * correction is defined in ATINC[INC_CORR]. A value of 0 disables the correction
- * counter and no corrections occur. This value is given in clock cycles, not in
- * nanoseconds as all other values.
- */
-//@{
-#define BP_ENET_ATCOR_COR (0U) //!< Bit position for ENET_ATCOR_COR.
-#define BM_ENET_ATCOR_COR (0x7FFFFFFFU) //!< Bit mask for ENET_ATCOR_COR.
-#define BS_ENET_ATCOR_COR (31U) //!< Bit field size in bits for ENET_ATCOR_COR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_ATCOR_COR field.
-#define BR_ENET_ATCOR_COR(x) (HW_ENET_ATCOR(x).B.COR)
-#endif
-
-//! @brief Format value for bitfield ENET_ATCOR_COR.
-#define BF_ENET_ATCOR_COR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCOR_COR), uint32_t) & BM_ENET_ATCOR_COR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the COR field to a new value.
-#define BW_ENET_ATCOR_COR(x, v) (HW_ENET_ATCOR_WR(x, (HW_ENET_ATCOR_RD(x) & ~BM_ENET_ATCOR_COR) | BF_ENET_ATCOR_COR(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_ATINC - Time-Stamping Clock Period Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_ATINC - Time-Stamping Clock Period Register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_atinc
-{
- uint32_t U;
- struct _hw_enet_atinc_bitfields
- {
- uint32_t INC : 7; //!< [6:0] Clock Period Of The Timestamping Clock
- //! (ts_clk) In Nanoseconds
- uint32_t RESERVED0 : 1; //!< [7]
- uint32_t INC_CORR : 7; //!< [14:8] Correction Increment Value
- uint32_t RESERVED1 : 17; //!< [31:15]
- } B;
-} hw_enet_atinc_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_ATINC register
- */
-//@{
-#define HW_ENET_ATINC_ADDR(x) (REGS_ENET_BASE(x) + 0x414U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_ATINC(x) (*(__IO hw_enet_atinc_t *) HW_ENET_ATINC_ADDR(x))
-#define HW_ENET_ATINC_RD(x) (HW_ENET_ATINC(x).U)
-#define HW_ENET_ATINC_WR(x, v) (HW_ENET_ATINC(x).U = (v))
-#define HW_ENET_ATINC_SET(x, v) (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) | (v)))
-#define HW_ENET_ATINC_CLR(x, v) (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) & ~(v)))
-#define HW_ENET_ATINC_TOG(x, v) (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_ATINC bitfields
- */
-
-/*!
- * @name Register ENET_ATINC, field INC[6:0] (RW)
- *
- * The timer increments by this amount each clock cycle. For example, set to 10
- * for 100 MHz, 8 for 125 MHz, 5 for 200 MHz. For highest precision, use a value
- * that is an integer fraction of the period set in ATPER.
- */
-//@{
-#define BP_ENET_ATINC_INC (0U) //!< Bit position for ENET_ATINC_INC.
-#define BM_ENET_ATINC_INC (0x0000007FU) //!< Bit mask for ENET_ATINC_INC.
-#define BS_ENET_ATINC_INC (7U) //!< Bit field size in bits for ENET_ATINC_INC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_ATINC_INC field.
-#define BR_ENET_ATINC_INC(x) (HW_ENET_ATINC(x).B.INC)
-#endif
-
-//! @brief Format value for bitfield ENET_ATINC_INC.
-#define BF_ENET_ATINC_INC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATINC_INC), uint32_t) & BM_ENET_ATINC_INC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INC field to a new value.
-#define BW_ENET_ATINC_INC(x, v) (HW_ENET_ATINC_WR(x, (HW_ENET_ATINC_RD(x) & ~BM_ENET_ATINC_INC) | BF_ENET_ATINC_INC(v)))
-#endif
-//@}
-
-/*!
- * @name Register ENET_ATINC, field INC_CORR[14:8] (RW)
- *
- * This value is added every time the correction timer expires (every clock
- * cycle given in ATCOR). A value less than INC slows down the timer. A value greater
- * than INC speeds up the timer.
- */
-//@{
-#define BP_ENET_ATINC_INC_CORR (8U) //!< Bit position for ENET_ATINC_INC_CORR.
-#define BM_ENET_ATINC_INC_CORR (0x00007F00U) //!< Bit mask for ENET_ATINC_INC_CORR.
-#define BS_ENET_ATINC_INC_CORR (7U) //!< Bit field size in bits for ENET_ATINC_INC_CORR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_ATINC_INC_CORR field.
-#define BR_ENET_ATINC_INC_CORR(x) (HW_ENET_ATINC(x).B.INC_CORR)
-#endif
-
-//! @brief Format value for bitfield ENET_ATINC_INC_CORR.
-#define BF_ENET_ATINC_INC_CORR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATINC_INC_CORR), uint32_t) & BM_ENET_ATINC_INC_CORR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INC_CORR field to a new value.
-#define BW_ENET_ATINC_INC_CORR(x, v) (HW_ENET_ATINC_WR(x, (HW_ENET_ATINC_RD(x) & ~BM_ENET_ATINC_INC_CORR) | BF_ENET_ATINC_INC_CORR(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_atstmp
-{
- uint32_t U;
- struct _hw_enet_atstmp_bitfields
- {
- uint32_t TIMESTAMP : 32; //!< [31:0]
- } B;
-} hw_enet_atstmp_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_ATSTMP register
- */
-//@{
-#define HW_ENET_ATSTMP_ADDR(x) (REGS_ENET_BASE(x) + 0x418U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_ATSTMP(x) (*(__I hw_enet_atstmp_t *) HW_ENET_ATSTMP_ADDR(x))
-#define HW_ENET_ATSTMP_RD(x) (HW_ENET_ATSTMP(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_ATSTMP bitfields
- */
-
-/*!
- * @name Register ENET_ATSTMP, field TIMESTAMP[31:0] (RO)
- *
- * Timestamp of the last frame transmitted by the core that had TxBD[TS] set .
- * This register is only valid when EIR[TS_AVAIL] is set.
- */
-//@{
-#define BP_ENET_ATSTMP_TIMESTAMP (0U) //!< Bit position for ENET_ATSTMP_TIMESTAMP.
-#define BM_ENET_ATSTMP_TIMESTAMP (0xFFFFFFFFU) //!< Bit mask for ENET_ATSTMP_TIMESTAMP.
-#define BS_ENET_ATSTMP_TIMESTAMP (32U) //!< Bit field size in bits for ENET_ATSTMP_TIMESTAMP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_ATSTMP_TIMESTAMP field.
-#define BR_ENET_ATSTMP_TIMESTAMP(x) (HW_ENET_ATSTMP(x).U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_TGSR - Timer Global Status Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_TGSR - Timer Global Status Register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_tgsr
-{
- uint32_t U;
- struct _hw_enet_tgsr_bitfields
- {
- uint32_t TF0 : 1; //!< [0] Copy Of Timer Flag For Channel 0
- uint32_t TF1 : 1; //!< [1] Copy Of Timer Flag For Channel 1
- uint32_t TF2 : 1; //!< [2] Copy Of Timer Flag For Channel 2
- uint32_t TF3 : 1; //!< [3] Copy Of Timer Flag For Channel 3
- uint32_t RESERVED0 : 28; //!< [31:4]
- } B;
-} hw_enet_tgsr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_TGSR register
- */
-//@{
-#define HW_ENET_TGSR_ADDR(x) (REGS_ENET_BASE(x) + 0x604U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_TGSR(x) (*(__IO hw_enet_tgsr_t *) HW_ENET_TGSR_ADDR(x))
-#define HW_ENET_TGSR_RD(x) (HW_ENET_TGSR(x).U)
-#define HW_ENET_TGSR_WR(x, v) (HW_ENET_TGSR(x).U = (v))
-#define HW_ENET_TGSR_SET(x, v) (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) | (v)))
-#define HW_ENET_TGSR_CLR(x, v) (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) & ~(v)))
-#define HW_ENET_TGSR_TOG(x, v) (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_TGSR bitfields
- */
-
-/*!
- * @name Register ENET_TGSR, field TF0[0] (W1C)
- *
- * Values:
- * - 0 - Timer Flag for Channel 0 is clear
- * - 1 - Timer Flag for Channel 0 is set
- */
-//@{
-#define BP_ENET_TGSR_TF0 (0U) //!< Bit position for ENET_TGSR_TF0.
-#define BM_ENET_TGSR_TF0 (0x00000001U) //!< Bit mask for ENET_TGSR_TF0.
-#define BS_ENET_TGSR_TF0 (1U) //!< Bit field size in bits for ENET_TGSR_TF0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_TGSR_TF0 field.
-#define BR_ENET_TGSR_TF0(x) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF0))
-#endif
-
-//! @brief Format value for bitfield ENET_TGSR_TF0.
-#define BF_ENET_TGSR_TF0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TGSR_TF0), uint32_t) & BM_ENET_TGSR_TF0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TF0 field to a new value.
-#define BW_ENET_TGSR_TF0(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_TGSR, field TF1[1] (W1C)
- *
- * Values:
- * - 0 - Timer Flag for Channel 1 is clear
- * - 1 - Timer Flag for Channel 1 is set
- */
-//@{
-#define BP_ENET_TGSR_TF1 (1U) //!< Bit position for ENET_TGSR_TF1.
-#define BM_ENET_TGSR_TF1 (0x00000002U) //!< Bit mask for ENET_TGSR_TF1.
-#define BS_ENET_TGSR_TF1 (1U) //!< Bit field size in bits for ENET_TGSR_TF1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_TGSR_TF1 field.
-#define BR_ENET_TGSR_TF1(x) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF1))
-#endif
-
-//! @brief Format value for bitfield ENET_TGSR_TF1.
-#define BF_ENET_TGSR_TF1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TGSR_TF1), uint32_t) & BM_ENET_TGSR_TF1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TF1 field to a new value.
-#define BW_ENET_TGSR_TF1(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_TGSR, field TF2[2] (W1C)
- *
- * Values:
- * - 0 - Timer Flag for Channel 2 is clear
- * - 1 - Timer Flag for Channel 2 is set
- */
-//@{
-#define BP_ENET_TGSR_TF2 (2U) //!< Bit position for ENET_TGSR_TF2.
-#define BM_ENET_TGSR_TF2 (0x00000004U) //!< Bit mask for ENET_TGSR_TF2.
-#define BS_ENET_TGSR_TF2 (1U) //!< Bit field size in bits for ENET_TGSR_TF2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_TGSR_TF2 field.
-#define BR_ENET_TGSR_TF2(x) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF2))
-#endif
-
-//! @brief Format value for bitfield ENET_TGSR_TF2.
-#define BF_ENET_TGSR_TF2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TGSR_TF2), uint32_t) & BM_ENET_TGSR_TF2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TF2 field to a new value.
-#define BW_ENET_TGSR_TF2(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_TGSR, field TF3[3] (W1C)
- *
- * Values:
- * - 0 - Timer Flag for Channel 3 is clear
- * - 1 - Timer Flag for Channel 3 is set
- */
-//@{
-#define BP_ENET_TGSR_TF3 (3U) //!< Bit position for ENET_TGSR_TF3.
-#define BM_ENET_TGSR_TF3 (0x00000008U) //!< Bit mask for ENET_TGSR_TF3.
-#define BS_ENET_TGSR_TF3 (1U) //!< Bit field size in bits for ENET_TGSR_TF3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_TGSR_TF3 field.
-#define BR_ENET_TGSR_TF3(x) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF3))
-#endif
-
-//! @brief Format value for bitfield ENET_TGSR_TF3.
-#define BF_ENET_TGSR_TF3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TGSR_TF3), uint32_t) & BM_ENET_TGSR_TF3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TF3 field to a new value.
-#define BW_ENET_TGSR_TF3(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF3) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_ENET_TCSRn - Timer Control Status Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_TCSRn - Timer Control Status Register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_tcsrn
-{
- uint32_t U;
- struct _hw_enet_tcsrn_bitfields
- {
- uint32_t TDRE : 1; //!< [0] Timer DMA Request Enable
- uint32_t RESERVED0 : 1; //!< [1]
- uint32_t TMODE : 4; //!< [5:2] Timer Mode
- uint32_t TIE : 1; //!< [6] Timer Interrupt Enable
- uint32_t TF : 1; //!< [7] Timer Flag
- uint32_t RESERVED1 : 24; //!< [31:8]
- } B;
-} hw_enet_tcsrn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_TCSRn register
- */
-//@{
-#define HW_ENET_TCSRn_COUNT (4U)
-
-#define HW_ENET_TCSRn_ADDR(x, n) (REGS_ENET_BASE(x) + 0x608U + (0x8U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_TCSRn(x, n) (*(__IO hw_enet_tcsrn_t *) HW_ENET_TCSRn_ADDR(x, n))
-#define HW_ENET_TCSRn_RD(x, n) (HW_ENET_TCSRn(x, n).U)
-#define HW_ENET_TCSRn_WR(x, n, v) (HW_ENET_TCSRn(x, n).U = (v))
-#define HW_ENET_TCSRn_SET(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) | (v)))
-#define HW_ENET_TCSRn_CLR(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) & ~(v)))
-#define HW_ENET_TCSRn_TOG(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_TCSRn bitfields
- */
-
-/*!
- * @name Register ENET_TCSRn, field TDRE[0] (RW)
- *
- * Values:
- * - 0 - DMA request is disabled
- * - 1 - DMA request is enabled
- */
-//@{
-#define BP_ENET_TCSRn_TDRE (0U) //!< Bit position for ENET_TCSRn_TDRE.
-#define BM_ENET_TCSRn_TDRE (0x00000001U) //!< Bit mask for ENET_TCSRn_TDRE.
-#define BS_ENET_TCSRn_TDRE (1U) //!< Bit field size in bits for ENET_TCSRn_TDRE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_TCSRn_TDRE field.
-#define BR_ENET_TCSRn_TDRE(x, n) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TDRE))
-#endif
-
-//! @brief Format value for bitfield ENET_TCSRn_TDRE.
-#define BF_ENET_TCSRn_TDRE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCSRn_TDRE), uint32_t) & BM_ENET_TCSRn_TDRE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TDRE field to a new value.
-#define BW_ENET_TCSRn_TDRE(x, n, v) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TDRE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_TCSRn, field TMODE[5:2] (RW)
- *
- * Updating the Timer Mode field takes a few cycles to register because it is
- * synchronized to the 1588 clock. The version of Timer Mode returned on a read is
- * from the 1588 clock domain. When changing Timer Mode, always disable the
- * channel and read this register to verify the channel is disabled first.
- *
- * Values:
- * - 0000 - Timer Channel is disabled.
- * - 0001 - Timer Channel is configured for Input Capture on rising edge
- * - 0010 - Timer Channel is configured for Input Capture on falling edge
- * - 0011 - Timer Channel is configured for Input Capture on both edges
- * - 0100 - Timer Channel is configured for Output Compare - software only
- * - 0101 - Timer Channel is configured for Output Compare - toggle output on
- * compare
- * - 0110 - Timer Channel is configured for Output Compare - clear output on
- * compare
- * - 0111 - Timer Channel is configured for Output Compare - set output on
- * compare
- * - 1000 - Reserved
- * - 1010 - Timer Channel is configured for Output Compare - clear output on
- * compare, set output on overflow
- * - 10x1 - Timer Channel is configured for Output Compare - set output on
- * compare, clear output on overflow
- * - 1100 - Reserved
- * - 1110 - Timer Channel is configured for Output Compare - pulse output low on
- * compare for one 1588 clock cycle
- * - 1111 - Timer Channel is configured for Output Compare - pulse output high
- * on compare for one 1588 clock cycle
- */
-//@{
-#define BP_ENET_TCSRn_TMODE (2U) //!< Bit position for ENET_TCSRn_TMODE.
-#define BM_ENET_TCSRn_TMODE (0x0000003CU) //!< Bit mask for ENET_TCSRn_TMODE.
-#define BS_ENET_TCSRn_TMODE (4U) //!< Bit field size in bits for ENET_TCSRn_TMODE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_TCSRn_TMODE field.
-#define BR_ENET_TCSRn_TMODE(x, n) (HW_ENET_TCSRn(x, n).B.TMODE)
-#endif
-
-//! @brief Format value for bitfield ENET_TCSRn_TMODE.
-#define BF_ENET_TCSRn_TMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCSRn_TMODE), uint32_t) & BM_ENET_TCSRn_TMODE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TMODE field to a new value.
-#define BW_ENET_TCSRn_TMODE(x, n, v) (HW_ENET_TCSRn_WR(x, n, (HW_ENET_TCSRn_RD(x, n) & ~BM_ENET_TCSRn_TMODE) | BF_ENET_TCSRn_TMODE(v)))
-#endif
-//@}
-
-/*!
- * @name Register ENET_TCSRn, field TIE[6] (RW)
- *
- * Values:
- * - 0 - Interrupt is disabled
- * - 1 - Interrupt is enabled
- */
-//@{
-#define BP_ENET_TCSRn_TIE (6U) //!< Bit position for ENET_TCSRn_TIE.
-#define BM_ENET_TCSRn_TIE (0x00000040U) //!< Bit mask for ENET_TCSRn_TIE.
-#define BS_ENET_TCSRn_TIE (1U) //!< Bit field size in bits for ENET_TCSRn_TIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_TCSRn_TIE field.
-#define BR_ENET_TCSRn_TIE(x, n) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TIE))
-#endif
-
-//! @brief Format value for bitfield ENET_TCSRn_TIE.
-#define BF_ENET_TCSRn_TIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCSRn_TIE), uint32_t) & BM_ENET_TCSRn_TIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TIE field to a new value.
-#define BW_ENET_TCSRn_TIE(x, n, v) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register ENET_TCSRn, field TF[7] (W1C)
- *
- * Sets when input capture or output compare occurs. This flag is double
- * buffered between the module clock and 1588 clock domains. When this field is 1, it
- * can be cleared to 0 by writing 1 to it.
- *
- * Values:
- * - 0 - Input Capture or Output Compare has not occurred
- * - 1 - Input Capture or Output Compare has occurred
- */
-//@{
-#define BP_ENET_TCSRn_TF (7U) //!< Bit position for ENET_TCSRn_TF.
-#define BM_ENET_TCSRn_TF (0x00000080U) //!< Bit mask for ENET_TCSRn_TF.
-#define BS_ENET_TCSRn_TF (1U) //!< Bit field size in bits for ENET_TCSRn_TF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_TCSRn_TF field.
-#define BR_ENET_TCSRn_TF(x, n) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TF))
-#endif
-
-//! @brief Format value for bitfield ENET_TCSRn_TF.
-#define BF_ENET_TCSRn_TF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCSRn_TF), uint32_t) & BM_ENET_TCSRn_TF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TF field to a new value.
-#define BW_ENET_TCSRn_TF(x, n, v) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TF) = (v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_ENET_TCCRn - Timer Compare Capture Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_ENET_TCCRn - Timer Compare Capture Register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_enet_tccrn
-{
- uint32_t U;
- struct _hw_enet_tccrn_bitfields
- {
- uint32_t TCC : 32; //!< [31:0] Timer Capture Compare
- } B;
-} hw_enet_tccrn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire ENET_TCCRn register
- */
-//@{
-#define HW_ENET_TCCRn_COUNT (4U)
-
-#define HW_ENET_TCCRn_ADDR(x, n) (REGS_ENET_BASE(x) + 0x60CU + (0x8U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_ENET_TCCRn(x, n) (*(__IO hw_enet_tccrn_t *) HW_ENET_TCCRn_ADDR(x, n))
-#define HW_ENET_TCCRn_RD(x, n) (HW_ENET_TCCRn(x, n).U)
-#define HW_ENET_TCCRn_WR(x, n, v) (HW_ENET_TCCRn(x, n).U = (v))
-#define HW_ENET_TCCRn_SET(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) | (v)))
-#define HW_ENET_TCCRn_CLR(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) & ~(v)))
-#define HW_ENET_TCCRn_TOG(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual ENET_TCCRn bitfields
- */
-
-/*!
- * @name Register ENET_TCCRn, field TCC[31:0] (RW)
- *
- * This register is double buffered between the module clock and 1588 clock
- * domains. When configured for compare, the 1588 clock domain updates with the value
- * in the module clock domain whenever the Timer Channel is first enabled and on
- * each subsequent compare. Write to this register with the first compare value
- * before enabling the Timer Channel. When the Timer Channel is enabled, write
- * the second compare value either immediately, or at least before the first
- * compare occurs. After each compare, write the next compare value before the previous
- * compare occurs and before clearing the Timer Flag. The compare occurs one
- * 1588 clock cycle after the IEEE 1588 Counter increments past the compare value in
- * the 1588 clock domain. If the compare value is less than the value of the
- * 1588 Counter when the Timer Channel is first enabled, then the compare does not
- * occur until following the next overflow of the 1588 Counter. If the compare
- * value is greater than the IEEE 1588 Counter when the 1588 Counter overflows, or
- * the compare value is less than the value of the IEEE 1588 Counter after the
- * overflow, then the compare occurs one 1588 clock cycle following the overflow.
- * When configured for Capture, the value of the IEEE 1588 Counter is captured into
- * the 1588 clock domain and then updated into the module clock domain, provided
- * the Timer Flag is clear. Always read the capture value before clearing the
- * Timer Flag.
- */
-//@{
-#define BP_ENET_TCCRn_TCC (0U) //!< Bit position for ENET_TCCRn_TCC.
-#define BM_ENET_TCCRn_TCC (0xFFFFFFFFU) //!< Bit mask for ENET_TCCRn_TCC.
-#define BS_ENET_TCCRn_TCC (32U) //!< Bit field size in bits for ENET_TCCRn_TCC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the ENET_TCCRn_TCC field.
-#define BR_ENET_TCCRn_TCC(x, n) (HW_ENET_TCCRn(x, n).U)
-#endif
-
-//! @brief Format value for bitfield ENET_TCCRn_TCC.
-#define BF_ENET_TCCRn_TCC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCCRn_TCC), uint32_t) & BM_ENET_TCCRn_TCC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TCC field to a new value.
-#define BW_ENET_TCCRn_TCC(x, n, v) (HW_ENET_TCCRn_WR(x, n, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_enet_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All ENET module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_enet
-{
- uint8_t _reserved0[4];
- __IO hw_enet_eir_t EIR; //!< [0x4] Interrupt Event Register
- __IO hw_enet_eimr_t EIMR; //!< [0x8] Interrupt Mask Register
- uint8_t _reserved1[4];
- __IO hw_enet_rdar_t RDAR; //!< [0x10] Receive Descriptor Active Register
- __IO hw_enet_tdar_t TDAR; //!< [0x14] Transmit Descriptor Active Register
- uint8_t _reserved2[12];
- __IO hw_enet_ecr_t ECR; //!< [0x24] Ethernet Control Register
- uint8_t _reserved3[24];
- __IO hw_enet_mmfr_t MMFR; //!< [0x40] MII Management Frame Register
- __IO hw_enet_mscr_t MSCR; //!< [0x44] MII Speed Control Register
- uint8_t _reserved4[28];
- __IO hw_enet_mibc_t MIBC; //!< [0x64] MIB Control Register
- uint8_t _reserved5[28];
- __IO hw_enet_rcr_t RCR; //!< [0x84] Receive Control Register
- uint8_t _reserved6[60];
- __IO hw_enet_tcr_t TCR; //!< [0xC4] Transmit Control Register
- uint8_t _reserved7[28];
- __IO hw_enet_palr_t PALR; //!< [0xE4] Physical Address Lower Register
- __IO hw_enet_paur_t PAUR; //!< [0xE8] Physical Address Upper Register
- __IO hw_enet_opd_t OPD; //!< [0xEC] Opcode/Pause Duration Register
- uint8_t _reserved8[40];
- __IO hw_enet_iaur_t IAUR; //!< [0x118] Descriptor Individual Upper Address Register
- __IO hw_enet_ialr_t IALR; //!< [0x11C] Descriptor Individual Lower Address Register
- __IO hw_enet_gaur_t GAUR; //!< [0x120] Descriptor Group Upper Address Register
- __IO hw_enet_galr_t GALR; //!< [0x124] Descriptor Group Lower Address Register
- uint8_t _reserved9[28];
- __IO hw_enet_tfwr_t TFWR; //!< [0x144] Transmit FIFO Watermark Register
- uint8_t _reserved10[56];
- __IO hw_enet_rdsr_t RDSR; //!< [0x180] Receive Descriptor Ring Start Register
- __IO hw_enet_tdsr_t TDSR; //!< [0x184] Transmit Buffer Descriptor Ring Start Register
- __IO hw_enet_mrbr_t MRBR; //!< [0x188] Maximum Receive Buffer Size Register
- uint8_t _reserved11[4];
- __IO hw_enet_rsfl_t RSFL; //!< [0x190] Receive FIFO Section Full Threshold
- __IO hw_enet_rsem_t RSEM; //!< [0x194] Receive FIFO Section Empty Threshold
- __IO hw_enet_raem_t RAEM; //!< [0x198] Receive FIFO Almost Empty Threshold
- __IO hw_enet_rafl_t RAFL; //!< [0x19C] Receive FIFO Almost Full Threshold
- __IO hw_enet_tsem_t TSEM; //!< [0x1A0] Transmit FIFO Section Empty Threshold
- __IO hw_enet_taem_t TAEM; //!< [0x1A4] Transmit FIFO Almost Empty Threshold
- __IO hw_enet_tafl_t TAFL; //!< [0x1A8] Transmit FIFO Almost Full Threshold
- __IO hw_enet_tipg_t TIPG; //!< [0x1AC] Transmit Inter-Packet Gap
- __IO hw_enet_ftrl_t FTRL; //!< [0x1B0] Frame Truncation Length
- uint8_t _reserved12[12];
- __IO hw_enet_tacc_t TACC; //!< [0x1C0] Transmit Accelerator Function Configuration
- __IO hw_enet_racc_t RACC; //!< [0x1C4] Receive Accelerator Function Configuration
- uint8_t _reserved13[60];
- __I hw_enet_rmon_t_packets_t RMON_T_PACKETS; //!< [0x204] Tx Packet Count Statistic Register
- __I hw_enet_rmon_t_bc_pkt_t RMON_T_BC_PKT; //!< [0x208] Tx Broadcast Packets Statistic Register
- __I hw_enet_rmon_t_mc_pkt_t RMON_T_MC_PKT; //!< [0x20C] Tx Multicast Packets Statistic Register
- __I hw_enet_rmon_t_crc_align_t RMON_T_CRC_ALIGN; //!< [0x210] Tx Packets with CRC/Align Error Statistic Register
- __I hw_enet_rmon_t_undersize_t RMON_T_UNDERSIZE; //!< [0x214] Tx Packets Less Than Bytes and Good CRC Statistic Register
- __I hw_enet_rmon_t_oversize_t RMON_T_OVERSIZE; //!< [0x218] Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
- __I hw_enet_rmon_t_frag_t RMON_T_FRAG; //!< [0x21C] Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
- __I hw_enet_rmon_t_jab_t RMON_T_JAB; //!< [0x220] Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
- __I hw_enet_rmon_t_col_t RMON_T_COL; //!< [0x224] Tx Collision Count Statistic Register
- __I hw_enet_rmon_t_p64_t RMON_T_P64; //!< [0x228] Tx 64-Byte Packets Statistic Register
- __I hw_enet_rmon_t_p65to127_t RMON_T_P65TO127; //!< [0x22C] Tx 65- to 127-byte Packets Statistic Register
- __I hw_enet_rmon_t_p128to255_t RMON_T_P128TO255; //!< [0x230] Tx 128- to 255-byte Packets Statistic Register
- __I hw_enet_rmon_t_p256to511_t RMON_T_P256TO511; //!< [0x234] Tx 256- to 511-byte Packets Statistic Register
- __I hw_enet_rmon_t_p512to1023_t RMON_T_P512TO1023; //!< [0x238] Tx 512- to 1023-byte Packets Statistic Register
- __I hw_enet_rmon_t_p1024to2047_t RMON_T_P1024TO2047; //!< [0x23C] Tx 1024- to 2047-byte Packets Statistic Register
- __I hw_enet_rmon_t_p_gte2048_t RMON_T_P_GTE2048; //!< [0x240] Tx Packets Greater Than 2048 Bytes Statistic Register
- __I hw_enet_rmon_t_octets_t RMON_T_OCTETS; //!< [0x244] Tx Octets Statistic Register
- uint8_t _reserved14[4];
- __I hw_enet_ieee_t_frame_ok_t IEEE_T_FRAME_OK; //!< [0x24C] Frames Transmitted OK Statistic Register
- __I hw_enet_ieee_t_1col_t IEEE_T_1COL; //!< [0x250] Frames Transmitted with Single Collision Statistic Register
- __I hw_enet_ieee_t_mcol_t IEEE_T_MCOL; //!< [0x254] Frames Transmitted with Multiple Collisions Statistic Register
- __I hw_enet_ieee_t_def_t IEEE_T_DEF; //!< [0x258] Frames Transmitted after Deferral Delay Statistic Register
- __I hw_enet_ieee_t_lcol_t IEEE_T_LCOL; //!< [0x25C] Frames Transmitted with Late Collision Statistic Register
- __I hw_enet_ieee_t_excol_t IEEE_T_EXCOL; //!< [0x260] Frames Transmitted with Excessive Collisions Statistic Register
- __I hw_enet_ieee_t_macerr_t IEEE_T_MACERR; //!< [0x264] Frames Transmitted with Tx FIFO Underrun Statistic Register
- __I hw_enet_ieee_t_cserr_t IEEE_T_CSERR; //!< [0x268] Frames Transmitted with Carrier Sense Error Statistic Register
- uint8_t _reserved15[4];
- __I hw_enet_ieee_t_fdxfc_t IEEE_T_FDXFC; //!< [0x270] Flow Control Pause Frames Transmitted Statistic Register
- __I hw_enet_ieee_t_octets_ok_t IEEE_T_OCTETS_OK; //!< [0x274] Octet Count for Frames Transmitted w/o Error Statistic Register
- uint8_t _reserved16[12];
- __I hw_enet_rmon_r_packets_t RMON_R_PACKETS; //!< [0x284] Rx Packet Count Statistic Register
- __I hw_enet_rmon_r_bc_pkt_t RMON_R_BC_PKT; //!< [0x288] Rx Broadcast Packets Statistic Register
- __I hw_enet_rmon_r_mc_pkt_t RMON_R_MC_PKT; //!< [0x28C] Rx Multicast Packets Statistic Register
- __I hw_enet_rmon_r_crc_align_t RMON_R_CRC_ALIGN; //!< [0x290] Rx Packets with CRC/Align Error Statistic Register
- __I hw_enet_rmon_r_undersize_t RMON_R_UNDERSIZE; //!< [0x294] Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
- __I hw_enet_rmon_r_oversize_t RMON_R_OVERSIZE; //!< [0x298] Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
- __I hw_enet_rmon_r_frag_t RMON_R_FRAG; //!< [0x29C] Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
- __I hw_enet_rmon_r_jab_t RMON_R_JAB; //!< [0x2A0] Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
- uint8_t _reserved17[4];
- __I hw_enet_rmon_r_p64_t RMON_R_P64; //!< [0x2A8] Rx 64-Byte Packets Statistic Register
- __I hw_enet_rmon_r_p65to127_t RMON_R_P65TO127; //!< [0x2AC] Rx 65- to 127-Byte Packets Statistic Register
- __I hw_enet_rmon_r_p128to255_t RMON_R_P128TO255; //!< [0x2B0] Rx 128- to 255-Byte Packets Statistic Register
- __I hw_enet_rmon_r_p256to511_t RMON_R_P256TO511; //!< [0x2B4] Rx 256- to 511-Byte Packets Statistic Register
- __I hw_enet_rmon_r_p512to1023_t RMON_R_P512TO1023; //!< [0x2B8] Rx 512- to 1023-Byte Packets Statistic Register
- __I hw_enet_rmon_r_p1024to2047_t RMON_R_P1024TO2047; //!< [0x2BC] Rx 1024- to 2047-Byte Packets Statistic Register
- __I hw_enet_rmon_r_gte2048_t RMON_R_GTE2048; //!< [0x2C0] Rx Packets Greater than 2048 Bytes Statistic Register
- __I hw_enet_rmon_r_octets_t RMON_R_OCTETS; //!< [0x2C4] Rx Octets Statistic Register
- __I hw_enet_ieee_r_drop_t IEEE_R_DROP; //!< [0x2C8] Frames not Counted Correctly Statistic Register
- __I hw_enet_ieee_r_frame_ok_t IEEE_R_FRAME_OK; //!< [0x2CC] Frames Received OK Statistic Register
- __I hw_enet_ieee_r_crc_t IEEE_R_CRC; //!< [0x2D0] Frames Received with CRC Error Statistic Register
- __I hw_enet_ieee_r_align_t IEEE_R_ALIGN; //!< [0x2D4] Frames Received with Alignment Error Statistic Register
- __I hw_enet_ieee_r_macerr_t IEEE_R_MACERR; //!< [0x2D8] Receive FIFO Overflow Count Statistic Register
- __I hw_enet_ieee_r_fdxfc_t IEEE_R_FDXFC; //!< [0x2DC] Flow Control Pause Frames Received Statistic Register
- __I hw_enet_ieee_r_octets_ok_t IEEE_R_OCTETS_OK; //!< [0x2E0] Octet Count for Frames Received without Error Statistic Register
- uint8_t _reserved18[284];
- __IO hw_enet_atcr_t ATCR; //!< [0x400] Adjustable Timer Control Register
- __IO hw_enet_atvr_t ATVR; //!< [0x404] Timer Value Register
- __IO hw_enet_atoff_t ATOFF; //!< [0x408] Timer Offset Register
- __IO hw_enet_atper_t ATPER; //!< [0x40C] Timer Period Register
- __IO hw_enet_atcor_t ATCOR; //!< [0x410] Timer Correction Register
- __IO hw_enet_atinc_t ATINC; //!< [0x414] Time-Stamping Clock Period Register
- __I hw_enet_atstmp_t ATSTMP; //!< [0x418] Timestamp of Last Transmitted Frame
- uint8_t _reserved19[488];
- __IO hw_enet_tgsr_t TGSR; //!< [0x604] Timer Global Status Register
- struct {
- __IO hw_enet_tcsrn_t TCSRn; //!< [0x608] Timer Control Status Register
- __IO hw_enet_tccrn_t TCCRn; //!< [0x60C] Timer Compare Capture Register
- } CHANNEL[4];
-} hw_enet_t;
-#pragma pack()
-
-//! @brief Macro to access all ENET registers.
-//! @param x ENET instance number.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_ENET(0)</code>.
-#define HW_ENET(x) (*(hw_enet_t *) REGS_ENET_BASE(x))
-#endif
-
-#endif // __HW_ENET_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_ewm.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,430 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_EWM_REGISTERS_H__
-#define __HW_EWM_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 EWM
- *
- * External Watchdog Monitor
- *
- * Registers defined in this header file:
- * - HW_EWM_CTRL - Control Register
- * - HW_EWM_SERV - Service Register
- * - HW_EWM_CMPL - Compare Low Register
- * - HW_EWM_CMPH - Compare High Register
- *
- * - hw_ewm_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_EWM_BASE
-#define HW_EWM_INSTANCE_COUNT (1U) //!< Number of instances of the EWM module.
-#define REGS_EWM_BASE (0x40061000U) //!< Base address for EWM.
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_EWM_CTRL - Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_EWM_CTRL - Control Register (RW)
- *
- * Reset value: 0x00U
- *
- * The CTRL register is cleared by any reset. INEN, ASSIN and EWMEN bits can be
- * written once after a CPU reset. Modifying these bits more than once, generates
- * a bus transfer error.
- */
-typedef union _hw_ewm_ctrl
-{
- uint8_t U;
- struct _hw_ewm_ctrl_bitfields
- {
- uint8_t EWMEN : 1; //!< [0] EWM enable.
- uint8_t ASSIN : 1; //!< [1] EWM_in's Assertion State Select.
- uint8_t INEN : 1; //!< [2] Input Enable.
- uint8_t INTEN : 1; //!< [3] Interrupt Enable.
- uint8_t RESERVED0 : 4; //!< [7:4]
- } B;
-} hw_ewm_ctrl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire EWM_CTRL register
- */
-//@{
-#define HW_EWM_CTRL_ADDR (REGS_EWM_BASE + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_EWM_CTRL (*(__IO hw_ewm_ctrl_t *) HW_EWM_CTRL_ADDR)
-#define HW_EWM_CTRL_RD() (HW_EWM_CTRL.U)
-#define HW_EWM_CTRL_WR(v) (HW_EWM_CTRL.U = (v))
-#define HW_EWM_CTRL_SET(v) (HW_EWM_CTRL_WR(HW_EWM_CTRL_RD() | (v)))
-#define HW_EWM_CTRL_CLR(v) (HW_EWM_CTRL_WR(HW_EWM_CTRL_RD() & ~(v)))
-#define HW_EWM_CTRL_TOG(v) (HW_EWM_CTRL_WR(HW_EWM_CTRL_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual EWM_CTRL bitfields
- */
-
-/*!
- * @name Register EWM_CTRL, field EWMEN[0] (RW)
- *
- * This bit when set, enables the EWM module. This resets the EWM counter to
- * zero and deasserts the EWM_out signal. Clearing EWMEN bit disables the EWM, and
- * therefore it cannot be enabled until a reset occurs, due to the write-once
- * nature of this bit.
- */
-//@{
-#define BP_EWM_CTRL_EWMEN (0U) //!< Bit position for EWM_CTRL_EWMEN.
-#define BM_EWM_CTRL_EWMEN (0x01U) //!< Bit mask for EWM_CTRL_EWMEN.
-#define BS_EWM_CTRL_EWMEN (1U) //!< Bit field size in bits for EWM_CTRL_EWMEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the EWM_CTRL_EWMEN field.
-#define BR_EWM_CTRL_EWMEN (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_EWMEN))
-#endif
-
-//! @brief Format value for bitfield EWM_CTRL_EWMEN.
-#define BF_EWM_CTRL_EWMEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CTRL_EWMEN), uint8_t) & BM_EWM_CTRL_EWMEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EWMEN field to a new value.
-#define BW_EWM_CTRL_EWMEN(v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_EWMEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register EWM_CTRL, field ASSIN[1] (RW)
- *
- * Default assert state of the EWM_in signal is logic zero. Setting ASSIN bit
- * inverts the assert state to a logic one.
- */
-//@{
-#define BP_EWM_CTRL_ASSIN (1U) //!< Bit position for EWM_CTRL_ASSIN.
-#define BM_EWM_CTRL_ASSIN (0x02U) //!< Bit mask for EWM_CTRL_ASSIN.
-#define BS_EWM_CTRL_ASSIN (1U) //!< Bit field size in bits for EWM_CTRL_ASSIN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the EWM_CTRL_ASSIN field.
-#define BR_EWM_CTRL_ASSIN (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_ASSIN))
-#endif
-
-//! @brief Format value for bitfield EWM_CTRL_ASSIN.
-#define BF_EWM_CTRL_ASSIN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CTRL_ASSIN), uint8_t) & BM_EWM_CTRL_ASSIN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ASSIN field to a new value.
-#define BW_EWM_CTRL_ASSIN(v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_ASSIN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register EWM_CTRL, field INEN[2] (RW)
- *
- * This bit when set, enables the EWM_in port.
- */
-//@{
-#define BP_EWM_CTRL_INEN (2U) //!< Bit position for EWM_CTRL_INEN.
-#define BM_EWM_CTRL_INEN (0x04U) //!< Bit mask for EWM_CTRL_INEN.
-#define BS_EWM_CTRL_INEN (1U) //!< Bit field size in bits for EWM_CTRL_INEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the EWM_CTRL_INEN field.
-#define BR_EWM_CTRL_INEN (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_INEN))
-#endif
-
-//! @brief Format value for bitfield EWM_CTRL_INEN.
-#define BF_EWM_CTRL_INEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CTRL_INEN), uint8_t) & BM_EWM_CTRL_INEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INEN field to a new value.
-#define BW_EWM_CTRL_INEN(v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_INEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register EWM_CTRL, field INTEN[3] (RW)
- *
- * This bit when set and EWM_out is asserted, an interrupt request is generated.
- * To de-assert interrupt request, user should clear this bit by writing 0.
- */
-//@{
-#define BP_EWM_CTRL_INTEN (3U) //!< Bit position for EWM_CTRL_INTEN.
-#define BM_EWM_CTRL_INTEN (0x08U) //!< Bit mask for EWM_CTRL_INTEN.
-#define BS_EWM_CTRL_INTEN (1U) //!< Bit field size in bits for EWM_CTRL_INTEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the EWM_CTRL_INTEN field.
-#define BR_EWM_CTRL_INTEN (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_INTEN))
-#endif
-
-//! @brief Format value for bitfield EWM_CTRL_INTEN.
-#define BF_EWM_CTRL_INTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CTRL_INTEN), uint8_t) & BM_EWM_CTRL_INTEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INTEN field to a new value.
-#define BW_EWM_CTRL_INTEN(v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_INTEN) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_EWM_SERV - Service Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_EWM_SERV - Service Register (WORZ)
- *
- * Reset value: 0x00U
- *
- * The SERV register provides the interface from the CPU to the EWM module. It
- * is write-only and reads of this register return zero.
- */
-typedef union _hw_ewm_serv
-{
- uint8_t U;
- struct _hw_ewm_serv_bitfields
- {
- uint8_t SERVICE : 8; //!< [7:0]
- } B;
-} hw_ewm_serv_t;
-#endif
-
-/*!
- * @name Constants and macros for entire EWM_SERV register
- */
-//@{
-#define HW_EWM_SERV_ADDR (REGS_EWM_BASE + 0x1U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_EWM_SERV (*(__O hw_ewm_serv_t *) HW_EWM_SERV_ADDR)
-#define HW_EWM_SERV_RD() (HW_EWM_SERV.U)
-#define HW_EWM_SERV_WR(v) (HW_EWM_SERV.U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual EWM_SERV bitfields
- */
-
-/*!
- * @name Register EWM_SERV, field SERVICE[7:0] (WORZ)
- *
- * The EWM service mechanism requires the CPU to write two values to the SERV
- * register: a first data byte of 0xB4, followed by a second data byte of 0x2C. The
- * EWM service is illegal if either of the following conditions is true. The
- * first or second data byte is not written correctly. The second data byte is not
- * written within a fixed number of peripheral bus cycles of the first data byte.
- * This fixed number of cycles is called EWM_service_time.
- */
-//@{
-#define BP_EWM_SERV_SERVICE (0U) //!< Bit position for EWM_SERV_SERVICE.
-#define BM_EWM_SERV_SERVICE (0xFFU) //!< Bit mask for EWM_SERV_SERVICE.
-#define BS_EWM_SERV_SERVICE (8U) //!< Bit field size in bits for EWM_SERV_SERVICE.
-
-//! @brief Format value for bitfield EWM_SERV_SERVICE.
-#define BF_EWM_SERV_SERVICE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_SERV_SERVICE), uint8_t) & BM_EWM_SERV_SERVICE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SERVICE field to a new value.
-#define BW_EWM_SERV_SERVICE(v) (HW_EWM_SERV_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_EWM_CMPL - Compare Low Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_EWM_CMPL - Compare Low Register (RW)
- *
- * Reset value: 0x00U
- *
- * The CMPL register is reset to zero after a CPU reset. This provides no
- * minimum time for the CPU to service the EWM counter. This register can be written
- * only once after a CPU reset. Writing this register more than once generates a
- * bus transfer error.
- */
-typedef union _hw_ewm_cmpl
-{
- uint8_t U;
- struct _hw_ewm_cmpl_bitfields
- {
- uint8_t COMPAREL : 8; //!< [7:0]
- } B;
-} hw_ewm_cmpl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire EWM_CMPL register
- */
-//@{
-#define HW_EWM_CMPL_ADDR (REGS_EWM_BASE + 0x2U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_EWM_CMPL (*(__IO hw_ewm_cmpl_t *) HW_EWM_CMPL_ADDR)
-#define HW_EWM_CMPL_RD() (HW_EWM_CMPL.U)
-#define HW_EWM_CMPL_WR(v) (HW_EWM_CMPL.U = (v))
-#define HW_EWM_CMPL_SET(v) (HW_EWM_CMPL_WR(HW_EWM_CMPL_RD() | (v)))
-#define HW_EWM_CMPL_CLR(v) (HW_EWM_CMPL_WR(HW_EWM_CMPL_RD() & ~(v)))
-#define HW_EWM_CMPL_TOG(v) (HW_EWM_CMPL_WR(HW_EWM_CMPL_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual EWM_CMPL bitfields
- */
-
-/*!
- * @name Register EWM_CMPL, field COMPAREL[7:0] (RW)
- *
- * To prevent runaway code from changing this field, software should write to
- * this field after a CPU reset even if the (default) minimum service time is
- * required.
- */
-//@{
-#define BP_EWM_CMPL_COMPAREL (0U) //!< Bit position for EWM_CMPL_COMPAREL.
-#define BM_EWM_CMPL_COMPAREL (0xFFU) //!< Bit mask for EWM_CMPL_COMPAREL.
-#define BS_EWM_CMPL_COMPAREL (8U) //!< Bit field size in bits for EWM_CMPL_COMPAREL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the EWM_CMPL_COMPAREL field.
-#define BR_EWM_CMPL_COMPAREL (HW_EWM_CMPL.U)
-#endif
-
-//! @brief Format value for bitfield EWM_CMPL_COMPAREL.
-#define BF_EWM_CMPL_COMPAREL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CMPL_COMPAREL), uint8_t) & BM_EWM_CMPL_COMPAREL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the COMPAREL field to a new value.
-#define BW_EWM_CMPL_COMPAREL(v) (HW_EWM_CMPL_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_EWM_CMPH - Compare High Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_EWM_CMPH - Compare High Register (RW)
- *
- * Reset value: 0xFFU
- *
- * The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum
- * of 256 clocks time, for the CPU to service the EWM counter. This register can
- * be written only once after a CPU reset. Writing this register more than once
- * generates a bus transfer error. The valid values for CMPH are up to 0xFE
- * because the EWM counter never expires when CMPH = 0xFF. The expiration happens only
- * if EWM counter is greater than CMPH.
- */
-typedef union _hw_ewm_cmph
-{
- uint8_t U;
- struct _hw_ewm_cmph_bitfields
- {
- uint8_t COMPAREH : 8; //!< [7:0]
- } B;
-} hw_ewm_cmph_t;
-#endif
-
-/*!
- * @name Constants and macros for entire EWM_CMPH register
- */
-//@{
-#define HW_EWM_CMPH_ADDR (REGS_EWM_BASE + 0x3U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_EWM_CMPH (*(__IO hw_ewm_cmph_t *) HW_EWM_CMPH_ADDR)
-#define HW_EWM_CMPH_RD() (HW_EWM_CMPH.U)
-#define HW_EWM_CMPH_WR(v) (HW_EWM_CMPH.U = (v))
-#define HW_EWM_CMPH_SET(v) (HW_EWM_CMPH_WR(HW_EWM_CMPH_RD() | (v)))
-#define HW_EWM_CMPH_CLR(v) (HW_EWM_CMPH_WR(HW_EWM_CMPH_RD() & ~(v)))
-#define HW_EWM_CMPH_TOG(v) (HW_EWM_CMPH_WR(HW_EWM_CMPH_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual EWM_CMPH bitfields
- */
-
-/*!
- * @name Register EWM_CMPH, field COMPAREH[7:0] (RW)
- *
- * To prevent runaway code from changing this field, software should write to
- * this field after a CPU reset even if the (default) maximum service time is
- * required.
- */
-//@{
-#define BP_EWM_CMPH_COMPAREH (0U) //!< Bit position for EWM_CMPH_COMPAREH.
-#define BM_EWM_CMPH_COMPAREH (0xFFU) //!< Bit mask for EWM_CMPH_COMPAREH.
-#define BS_EWM_CMPH_COMPAREH (8U) //!< Bit field size in bits for EWM_CMPH_COMPAREH.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the EWM_CMPH_COMPAREH field.
-#define BR_EWM_CMPH_COMPAREH (HW_EWM_CMPH.U)
-#endif
-
-//! @brief Format value for bitfield EWM_CMPH_COMPAREH.
-#define BF_EWM_CMPH_COMPAREH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CMPH_COMPAREH), uint8_t) & BM_EWM_CMPH_COMPAREH)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the COMPAREH field to a new value.
-#define BW_EWM_CMPH_COMPAREH(v) (HW_EWM_CMPH_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_ewm_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All EWM module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_ewm
-{
- __IO hw_ewm_ctrl_t CTRL; //!< [0x0] Control Register
- __O hw_ewm_serv_t SERV; //!< [0x1] Service Register
- __IO hw_ewm_cmpl_t CMPL; //!< [0x2] Compare Low Register
- __IO hw_ewm_cmph_t CMPH; //!< [0x3] Compare High Register
-} hw_ewm_t;
-#pragma pack()
-
-//! @brief Macro to access all EWM registers.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_EWM</code>.
-#define HW_EWM (*(hw_ewm_t *) REGS_EWM_BASE)
-#endif
-
-#endif // __HW_EWM_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_fb.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,959 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_FB_REGISTERS_H__
-#define __HW_FB_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 FB
- *
- * FlexBus external bus interface
- *
- * Registers defined in this header file:
- * - HW_FB_CSARn - Chip Select Address Register
- * - HW_FB_CSMRn - Chip Select Mask Register
- * - HW_FB_CSCRn - Chip Select Control Register
- * - HW_FB_CSPMCR - Chip Select port Multiplexing Control Register
- *
- * - hw_fb_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_FB_BASE
-#define HW_FB_INSTANCE_COUNT (1U) //!< Number of instances of the FB module.
-#define REGS_FB_BASE (0x4000C000U) //!< Base address for FB.
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FB_CSARn - Chip Select Address Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FB_CSARn - Chip Select Address Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * Specifies the associated chip-select's base address.
- */
-typedef union _hw_fb_csarn
-{
- uint32_t U;
- struct _hw_fb_csarn_bitfields
- {
- uint32_t RESERVED0 : 16; //!< [15:0]
- uint32_t BA : 16; //!< [31:16] Base Address
- } B;
-} hw_fb_csarn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FB_CSARn register
- */
-//@{
-#define HW_FB_CSARn_COUNT (6U)
-
-#define HW_FB_CSARn_ADDR(n) (REGS_FB_BASE + 0x0U + (0xCU * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FB_CSARn(n) (*(__IO hw_fb_csarn_t *) HW_FB_CSARn_ADDR(n))
-#define HW_FB_CSARn_RD(n) (HW_FB_CSARn(n).U)
-#define HW_FB_CSARn_WR(n, v) (HW_FB_CSARn(n).U = (v))
-#define HW_FB_CSARn_SET(n, v) (HW_FB_CSARn_WR(n, HW_FB_CSARn_RD(n) | (v)))
-#define HW_FB_CSARn_CLR(n, v) (HW_FB_CSARn_WR(n, HW_FB_CSARn_RD(n) & ~(v)))
-#define HW_FB_CSARn_TOG(n, v) (HW_FB_CSARn_WR(n, HW_FB_CSARn_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FB_CSARn bitfields
- */
-
-/*!
- * @name Register FB_CSARn, field BA[31:16] (RW)
- *
- * Defines the base address for memory dedicated to the associated chip-select.
- * BA is compared to bits 31-16 on the internal address bus to determine if the
- * associated chip-select's memory is being accessed. Because the FlexBus module
- * is one of the slaves connected to the crossbar switch, it is only accessible
- * within a certain memory range. See the chip memory map for the applicable
- * FlexBus "expansion" address range for which the chip-selects can be active. Set the
- * CSARn and CSMRn registers appropriately before accessing this region.
- */
-//@{
-#define BP_FB_CSARn_BA (16U) //!< Bit position for FB_CSARn_BA.
-#define BM_FB_CSARn_BA (0xFFFF0000U) //!< Bit mask for FB_CSARn_BA.
-#define BS_FB_CSARn_BA (16U) //!< Bit field size in bits for FB_CSARn_BA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FB_CSARn_BA field.
-#define BR_FB_CSARn_BA(n) (HW_FB_CSARn(n).B.BA)
-#endif
-
-//! @brief Format value for bitfield FB_CSARn_BA.
-#define BF_FB_CSARn_BA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSARn_BA), uint32_t) & BM_FB_CSARn_BA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BA field to a new value.
-#define BW_FB_CSARn_BA(n, v) (HW_FB_CSARn_WR(n, (HW_FB_CSARn_RD(n) & ~BM_FB_CSARn_BA) | BF_FB_CSARn_BA(v)))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_FB_CSMRn - Chip Select Mask Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FB_CSMRn - Chip Select Mask Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * Specifies the address mask and allowable access types for the associated
- * chip-select.
- */
-typedef union _hw_fb_csmrn
-{
- uint32_t U;
- struct _hw_fb_csmrn_bitfields
- {
- uint32_t V : 1; //!< [0] Valid
- uint32_t RESERVED0 : 7; //!< [7:1]
- uint32_t WP : 1; //!< [8] Write Protect
- uint32_t RESERVED1 : 7; //!< [15:9]
- uint32_t BAM : 16; //!< [31:16] Base Address Mask
- } B;
-} hw_fb_csmrn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FB_CSMRn register
- */
-//@{
-#define HW_FB_CSMRn_COUNT (6U)
-
-#define HW_FB_CSMRn_ADDR(n) (REGS_FB_BASE + 0x4U + (0xCU * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FB_CSMRn(n) (*(__IO hw_fb_csmrn_t *) HW_FB_CSMRn_ADDR(n))
-#define HW_FB_CSMRn_RD(n) (HW_FB_CSMRn(n).U)
-#define HW_FB_CSMRn_WR(n, v) (HW_FB_CSMRn(n).U = (v))
-#define HW_FB_CSMRn_SET(n, v) (HW_FB_CSMRn_WR(n, HW_FB_CSMRn_RD(n) | (v)))
-#define HW_FB_CSMRn_CLR(n, v) (HW_FB_CSMRn_WR(n, HW_FB_CSMRn_RD(n) & ~(v)))
-#define HW_FB_CSMRn_TOG(n, v) (HW_FB_CSMRn_WR(n, HW_FB_CSMRn_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FB_CSMRn bitfields
- */
-
-/*!
- * @name Register FB_CSMRn, field V[0] (RW)
- *
- * Specifies whether the corresponding CSAR, CSMR, and CSCR contents are valid.
- * Programmed chip-selects do not assert until the V bit is 1b (except for
- * FB_CS0, which acts as the global chip-select). At reset, FB_CS0 will fire for any
- * access to the FlexBus memory region. CSMR0[V] must be set as part of the chip
- * select initialization sequence to allow other chip selects to function as
- * programmed.
- *
- * Values:
- * - 0 - Chip-select is invalid.
- * - 1 - Chip-select is valid.
- */
-//@{
-#define BP_FB_CSMRn_V (0U) //!< Bit position for FB_CSMRn_V.
-#define BM_FB_CSMRn_V (0x00000001U) //!< Bit mask for FB_CSMRn_V.
-#define BS_FB_CSMRn_V (1U) //!< Bit field size in bits for FB_CSMRn_V.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FB_CSMRn_V field.
-#define BR_FB_CSMRn_V(n) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(n), BP_FB_CSMRn_V))
-#endif
-
-//! @brief Format value for bitfield FB_CSMRn_V.
-#define BF_FB_CSMRn_V(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSMRn_V), uint32_t) & BM_FB_CSMRn_V)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the V field to a new value.
-#define BW_FB_CSMRn_V(n, v) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(n), BP_FB_CSMRn_V) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FB_CSMRn, field WP[8] (RW)
- *
- * Controls write accesses to the address range in the corresponding CSAR.
- *
- * Values:
- * - 0 - Write accesses are allowed.
- * - 1 - Write accesses are not allowed. Attempting to write to the range of
- * addresses for which the WP bit is set results in a bus error termination of
- * the internal cycle and no external cycle.
- */
-//@{
-#define BP_FB_CSMRn_WP (8U) //!< Bit position for FB_CSMRn_WP.
-#define BM_FB_CSMRn_WP (0x00000100U) //!< Bit mask for FB_CSMRn_WP.
-#define BS_FB_CSMRn_WP (1U) //!< Bit field size in bits for FB_CSMRn_WP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FB_CSMRn_WP field.
-#define BR_FB_CSMRn_WP(n) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(n), BP_FB_CSMRn_WP))
-#endif
-
-//! @brief Format value for bitfield FB_CSMRn_WP.
-#define BF_FB_CSMRn_WP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSMRn_WP), uint32_t) & BM_FB_CSMRn_WP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WP field to a new value.
-#define BW_FB_CSMRn_WP(n, v) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(n), BP_FB_CSMRn_WP) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FB_CSMRn, field BAM[31:16] (RW)
- *
- * Defines the associated chip-select's block size by masking address bits.
- *
- * Values:
- * - 0 - The corresponding address bit in CSAR is used in the chip-select decode.
- * - 1 - The corresponding address bit in CSAR is a don't care in the
- * chip-select decode.
- */
-//@{
-#define BP_FB_CSMRn_BAM (16U) //!< Bit position for FB_CSMRn_BAM.
-#define BM_FB_CSMRn_BAM (0xFFFF0000U) //!< Bit mask for FB_CSMRn_BAM.
-#define BS_FB_CSMRn_BAM (16U) //!< Bit field size in bits for FB_CSMRn_BAM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FB_CSMRn_BAM field.
-#define BR_FB_CSMRn_BAM(n) (HW_FB_CSMRn(n).B.BAM)
-#endif
-
-//! @brief Format value for bitfield FB_CSMRn_BAM.
-#define BF_FB_CSMRn_BAM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSMRn_BAM), uint32_t) & BM_FB_CSMRn_BAM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BAM field to a new value.
-#define BW_FB_CSMRn_BAM(n, v) (HW_FB_CSMRn_WR(n, (HW_FB_CSMRn_RD(n) & ~BM_FB_CSMRn_BAM) | BF_FB_CSMRn_BAM(v)))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_FB_CSCRn - Chip Select Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FB_CSCRn - Chip Select Control Register (RW)
- *
- * Reset value: 0x003FFC00U
- *
- * Controls the auto-acknowledge, address setup and hold times, port size, burst
- * capability, and number of wait states for the associated chip select. To
- * support the global chip-select (FB_CS0), the CSCR0 reset values differ from the
- * other CSCRs. The reset value of CSCR0 is as follows: Bits 31-24 are 0b Bit 23-3
- * are chip-dependent Bits 3-0 are 0b See the chip configuration details for your
- * particular chip for information on the exact CSCR0 reset value.
- */
-typedef union _hw_fb_cscrn
-{
- uint32_t U;
- struct _hw_fb_cscrn_bitfields
- {
- uint32_t RESERVED0 : 3; //!< [2:0]
- uint32_t BSTW : 1; //!< [3] Burst-Write Enable
- uint32_t BSTR : 1; //!< [4] Burst-Read Enable
- uint32_t BEM : 1; //!< [5] Byte-Enable Mode
- uint32_t PS : 2; //!< [7:6] Port Size
- uint32_t AA : 1; //!< [8] Auto-Acknowledge Enable
- uint32_t BLS : 1; //!< [9] Byte-Lane Shift
- uint32_t WS : 6; //!< [15:10] Wait States
- uint32_t WRAH : 2; //!< [17:16] Write Address Hold or Deselect
- uint32_t RDAH : 2; //!< [19:18] Read Address Hold or Deselect
- uint32_t ASET : 2; //!< [21:20] Address Setup
- uint32_t EXTS : 1; //!< [22]
- uint32_t SWSEN : 1; //!< [23] Secondary Wait State Enable
- uint32_t RESERVED1 : 2; //!< [25:24]
- uint32_t SWS : 6; //!< [31:26] Secondary Wait States
- } B;
-} hw_fb_cscrn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FB_CSCRn register
- */
-//@{
-#define HW_FB_CSCRn_COUNT (6U)
-
-#define HW_FB_CSCRn_ADDR(n) (REGS_FB_BASE + 0x8U + (0xCU * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FB_CSCRn(n) (*(__IO hw_fb_cscrn_t *) HW_FB_CSCRn_ADDR(n))
-#define HW_FB_CSCRn_RD(n) (HW_FB_CSCRn(n).U)
-#define HW_FB_CSCRn_WR(n, v) (HW_FB_CSCRn(n).U = (v))
-#define HW_FB_CSCRn_SET(n, v) (HW_FB_CSCRn_WR(n, HW_FB_CSCRn_RD(n) | (v)))
-#define HW_FB_CSCRn_CLR(n, v) (HW_FB_CSCRn_WR(n, HW_FB_CSCRn_RD(n) & ~(v)))
-#define HW_FB_CSCRn_TOG(n, v) (HW_FB_CSCRn_WR(n, HW_FB_CSCRn_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FB_CSCRn bitfields
- */
-
-/*!
- * @name Register FB_CSCRn, field BSTW[3] (RW)
- *
- * Specifies whether burst writes are enabled for memory associated with each
- * chip select.
- *
- * Values:
- * - 0 - Disabled. Data exceeding the specified port size is broken into
- * individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit
- * port takes four byte writes.
- * - 1 - Enabled. Enables burst write of data larger than the specified port
- * size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit
- * ports, and line writes to 8-, 16-, and 32-bit ports.
- */
-//@{
-#define BP_FB_CSCRn_BSTW (3U) //!< Bit position for FB_CSCRn_BSTW.
-#define BM_FB_CSCRn_BSTW (0x00000008U) //!< Bit mask for FB_CSCRn_BSTW.
-#define BS_FB_CSCRn_BSTW (1U) //!< Bit field size in bits for FB_CSCRn_BSTW.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FB_CSCRn_BSTW field.
-#define BR_FB_CSCRn_BSTW(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BSTW))
-#endif
-
-//! @brief Format value for bitfield FB_CSCRn_BSTW.
-#define BF_FB_CSCRn_BSTW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_BSTW), uint32_t) & BM_FB_CSCRn_BSTW)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BSTW field to a new value.
-#define BW_FB_CSCRn_BSTW(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BSTW) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FB_CSCRn, field BSTR[4] (RW)
- *
- * Specifies whether burst reads are enabled for memory associated with each
- * chip select.
- *
- * Values:
- * - 0 - Disabled. Data exceeding the specified port size is broken into
- * individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit
- * port is broken into four 8-bit reads.
- * - 1 - Enabled. Enables data burst reads larger than the specified port size,
- * including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit
- * ports, and line reads from 8-, 16-, and 32-bit ports.
- */
-//@{
-#define BP_FB_CSCRn_BSTR (4U) //!< Bit position for FB_CSCRn_BSTR.
-#define BM_FB_CSCRn_BSTR (0x00000010U) //!< Bit mask for FB_CSCRn_BSTR.
-#define BS_FB_CSCRn_BSTR (1U) //!< Bit field size in bits for FB_CSCRn_BSTR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FB_CSCRn_BSTR field.
-#define BR_FB_CSCRn_BSTR(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BSTR))
-#endif
-
-//! @brief Format value for bitfield FB_CSCRn_BSTR.
-#define BF_FB_CSCRn_BSTR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_BSTR), uint32_t) & BM_FB_CSCRn_BSTR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BSTR field to a new value.
-#define BW_FB_CSCRn_BSTR(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BSTR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FB_CSCRn, field BEM[5] (RW)
- *
- * Specifies whether the corresponding FB_BE is asserted for read accesses.
- * Certain memories have byte enables that must be asserted during reads and writes.
- * Write 1b to the BEM bit in the relevant CSCR to provide the appropriate mode
- * of byte enable support for these SRAMs.
- *
- * Values:
- * - 0 - FB_BE is asserted for data write only.
- * - 1 - FB_BE is asserted for data read and write accesses.
- */
-//@{
-#define BP_FB_CSCRn_BEM (5U) //!< Bit position for FB_CSCRn_BEM.
-#define BM_FB_CSCRn_BEM (0x00000020U) //!< Bit mask for FB_CSCRn_BEM.
-#define BS_FB_CSCRn_BEM (1U) //!< Bit field size in bits for FB_CSCRn_BEM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FB_CSCRn_BEM field.
-#define BR_FB_CSCRn_BEM(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BEM))
-#endif
-
-//! @brief Format value for bitfield FB_CSCRn_BEM.
-#define BF_FB_CSCRn_BEM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_BEM), uint32_t) & BM_FB_CSCRn_BEM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BEM field to a new value.
-#define BW_FB_CSCRn_BEM(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BEM) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FB_CSCRn, field PS[7:6] (RW)
- *
- * Specifies the data port width of the associated chip-select, and determines
- * where data is driven during write cycles and where data is sampled during read
- * cycles.
- *
- * Values:
- * - 00 - 32-bit port size. Valid data is sampled and driven on FB_D[31:0].
- * - 01 - 8-bit port size. Valid data is sampled and driven on FB_D[31:24] when
- * BLS is 0b, or FB_D[7:0] when BLS is 1b.
- */
-//@{
-#define BP_FB_CSCRn_PS (6U) //!< Bit position for FB_CSCRn_PS.
-#define BM_FB_CSCRn_PS (0x000000C0U) //!< Bit mask for FB_CSCRn_PS.
-#define BS_FB_CSCRn_PS (2U) //!< Bit field size in bits for FB_CSCRn_PS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FB_CSCRn_PS field.
-#define BR_FB_CSCRn_PS(n) (HW_FB_CSCRn(n).B.PS)
-#endif
-
-//! @brief Format value for bitfield FB_CSCRn_PS.
-#define BF_FB_CSCRn_PS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_PS), uint32_t) & BM_FB_CSCRn_PS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PS field to a new value.
-#define BW_FB_CSCRn_PS(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_PS) | BF_FB_CSCRn_PS(v)))
-#endif
-//@}
-
-/*!
- * @name Register FB_CSCRn, field AA[8] (RW)
- *
- * Asserts the internal transfer acknowledge for accesses specified by the
- * chip-select address. If AA is 1b for a corresponding FB_CSn and the external system
- * asserts an external FB_TA before the wait-state countdown asserts the
- * internal FB_TA, the cycle is terminated. Burst cycles increment the address bus
- * between each internal termination. This field must be 1b if CSPMCR disables FB_TA.
- *
- * Values:
- * - 0 - Disabled. No internal transfer acknowledge is asserted and the cycle is
- * terminated externally.
- * - 1 - Enabled. Internal transfer acknowledge is asserted as specified by WS.
- */
-//@{
-#define BP_FB_CSCRn_AA (8U) //!< Bit position for FB_CSCRn_AA.
-#define BM_FB_CSCRn_AA (0x00000100U) //!< Bit mask for FB_CSCRn_AA.
-#define BS_FB_CSCRn_AA (1U) //!< Bit field size in bits for FB_CSCRn_AA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FB_CSCRn_AA field.
-#define BR_FB_CSCRn_AA(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_AA))
-#endif
-
-//! @brief Format value for bitfield FB_CSCRn_AA.
-#define BF_FB_CSCRn_AA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_AA), uint32_t) & BM_FB_CSCRn_AA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the AA field to a new value.
-#define BW_FB_CSCRn_AA(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_AA) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FB_CSCRn, field BLS[9] (RW)
- *
- * Specifies if data on FB_AD appears left-aligned or right-aligned during the
- * data phase of a FlexBus access.
- *
- * Values:
- * - 0 - Not shifted. Data is left-aligned on FB_AD.
- * - 1 - Shifted. Data is right-aligned on FB_AD.
- */
-//@{
-#define BP_FB_CSCRn_BLS (9U) //!< Bit position for FB_CSCRn_BLS.
-#define BM_FB_CSCRn_BLS (0x00000200U) //!< Bit mask for FB_CSCRn_BLS.
-#define BS_FB_CSCRn_BLS (1U) //!< Bit field size in bits for FB_CSCRn_BLS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FB_CSCRn_BLS field.
-#define BR_FB_CSCRn_BLS(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BLS))
-#endif
-
-//! @brief Format value for bitfield FB_CSCRn_BLS.
-#define BF_FB_CSCRn_BLS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_BLS), uint32_t) & BM_FB_CSCRn_BLS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BLS field to a new value.
-#define BW_FB_CSCRn_BLS(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BLS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FB_CSCRn, field WS[15:10] (RW)
- *
- * Specifies the number of wait states inserted after FlexBus asserts the
- * associated chip-select and before an internal transfer acknowledge is generated (WS
- * = 00h inserts 0 wait states, ..., WS = 3Fh inserts 63 wait states).
- */
-//@{
-#define BP_FB_CSCRn_WS (10U) //!< Bit position for FB_CSCRn_WS.
-#define BM_FB_CSCRn_WS (0x0000FC00U) //!< Bit mask for FB_CSCRn_WS.
-#define BS_FB_CSCRn_WS (6U) //!< Bit field size in bits for FB_CSCRn_WS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FB_CSCRn_WS field.
-#define BR_FB_CSCRn_WS(n) (HW_FB_CSCRn(n).B.WS)
-#endif
-
-//! @brief Format value for bitfield FB_CSCRn_WS.
-#define BF_FB_CSCRn_WS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_WS), uint32_t) & BM_FB_CSCRn_WS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WS field to a new value.
-#define BW_FB_CSCRn_WS(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_WS) | BF_FB_CSCRn_WS(v)))
-#endif
-//@}
-
-/*!
- * @name Register FB_CSCRn, field WRAH[17:16] (RW)
- *
- * Controls the address, data, and attribute hold time after the termination of
- * a write cycle that hits in the associated chip-select's address space. The
- * hold time applies only at the end of a transfer. Therefore, during a burst
- * transfer or a transfer to a port size smaller than the transfer size, the hold time
- * is only added after the last bus cycle.
- *
- * Values:
- * - 00 - 1 cycle (default for all but FB_CS0 )
- * - 01 - 2 cycles
- * - 10 - 3 cycles
- * - 11 - 4 cycles (default for FB_CS0 )
- */
-//@{
-#define BP_FB_CSCRn_WRAH (16U) //!< Bit position for FB_CSCRn_WRAH.
-#define BM_FB_CSCRn_WRAH (0x00030000U) //!< Bit mask for FB_CSCRn_WRAH.
-#define BS_FB_CSCRn_WRAH (2U) //!< Bit field size in bits for FB_CSCRn_WRAH.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FB_CSCRn_WRAH field.
-#define BR_FB_CSCRn_WRAH(n) (HW_FB_CSCRn(n).B.WRAH)
-#endif
-
-//! @brief Format value for bitfield FB_CSCRn_WRAH.
-#define BF_FB_CSCRn_WRAH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_WRAH), uint32_t) & BM_FB_CSCRn_WRAH)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WRAH field to a new value.
-#define BW_FB_CSCRn_WRAH(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_WRAH) | BF_FB_CSCRn_WRAH(v)))
-#endif
-//@}
-
-/*!
- * @name Register FB_CSCRn, field RDAH[19:18] (RW)
- *
- * Controls the address and attribute hold time after the termination during a
- * read cycle that hits in the associated chip-select's address space. The hold
- * time applies only at the end of a transfer. Therefore, during a burst transfer
- * or a transfer to a port size smaller than the transfer size, the hold time is
- * only added after the last bus cycle. The number of cycles the address and
- * attributes are held after FB_CSn deassertion depends on the value of the AA bit.
- *
- * Values:
- * - 00 - When AA is 0b, 1 cycle. When AA is 1b, 0 cycles.
- * - 01 - When AA is 0b, 2 cycles. When AA is 1b, 1 cycle.
- * - 10 - When AA is 0b, 3 cycles. When AA is 1b, 2 cycles.
- * - 11 - When AA is 0b, 4 cycles. When AA is 1b, 3 cycles.
- */
-//@{
-#define BP_FB_CSCRn_RDAH (18U) //!< Bit position for FB_CSCRn_RDAH.
-#define BM_FB_CSCRn_RDAH (0x000C0000U) //!< Bit mask for FB_CSCRn_RDAH.
-#define BS_FB_CSCRn_RDAH (2U) //!< Bit field size in bits for FB_CSCRn_RDAH.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FB_CSCRn_RDAH field.
-#define BR_FB_CSCRn_RDAH(n) (HW_FB_CSCRn(n).B.RDAH)
-#endif
-
-//! @brief Format value for bitfield FB_CSCRn_RDAH.
-#define BF_FB_CSCRn_RDAH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_RDAH), uint32_t) & BM_FB_CSCRn_RDAH)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RDAH field to a new value.
-#define BW_FB_CSCRn_RDAH(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_RDAH) | BF_FB_CSCRn_RDAH(v)))
-#endif
-//@}
-
-/*!
- * @name Register FB_CSCRn, field ASET[21:20] (RW)
- *
- * Controls when the chip-select is asserted with respect to assertion of a
- * valid address and attributes.
- *
- * Values:
- * - 00 - Assert FB_CSn on the first rising clock edge after the address is
- * asserted (default for all but FB_CS0 ).
- * - 01 - Assert FB_CSn on the second rising clock edge after the address is
- * asserted.
- * - 10 - Assert FB_CSn on the third rising clock edge after the address is
- * asserted.
- * - 11 - Assert FB_CSn on the fourth rising clock edge after the address is
- * asserted (default for FB_CS0 ).
- */
-//@{
-#define BP_FB_CSCRn_ASET (20U) //!< Bit position for FB_CSCRn_ASET.
-#define BM_FB_CSCRn_ASET (0x00300000U) //!< Bit mask for FB_CSCRn_ASET.
-#define BS_FB_CSCRn_ASET (2U) //!< Bit field size in bits for FB_CSCRn_ASET.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FB_CSCRn_ASET field.
-#define BR_FB_CSCRn_ASET(n) (HW_FB_CSCRn(n).B.ASET)
-#endif
-
-//! @brief Format value for bitfield FB_CSCRn_ASET.
-#define BF_FB_CSCRn_ASET(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_ASET), uint32_t) & BM_FB_CSCRn_ASET)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ASET field to a new value.
-#define BW_FB_CSCRn_ASET(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_ASET) | BF_FB_CSCRn_ASET(v)))
-#endif
-//@}
-
-/*!
- * @name Register FB_CSCRn, field EXTS[22] (RW)
- *
- * Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS
- * /FB_ALE is asserted.
- *
- * Values:
- * - 0 - Disabled. FB_TS /FB_ALE asserts for one bus clock cycle.
- * - 1 - Enabled. FB_TS /FB_ALE remains asserted until the first positive clock
- * edge after FB_CSn asserts.
- */
-//@{
-#define BP_FB_CSCRn_EXTS (22U) //!< Bit position for FB_CSCRn_EXTS.
-#define BM_FB_CSCRn_EXTS (0x00400000U) //!< Bit mask for FB_CSCRn_EXTS.
-#define BS_FB_CSCRn_EXTS (1U) //!< Bit field size in bits for FB_CSCRn_EXTS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FB_CSCRn_EXTS field.
-#define BR_FB_CSCRn_EXTS(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_EXTS))
-#endif
-
-//! @brief Format value for bitfield FB_CSCRn_EXTS.
-#define BF_FB_CSCRn_EXTS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_EXTS), uint32_t) & BM_FB_CSCRn_EXTS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EXTS field to a new value.
-#define BW_FB_CSCRn_EXTS(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_EXTS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FB_CSCRn, field SWSEN[23] (RW)
- *
- * Values:
- * - 0 - Disabled. A number of wait states (specified by WS) are inserted before
- * an internal transfer acknowledge is generated for all transfers.
- * - 1 - Enabled. A number of wait states (specified by SWS) are inserted before
- * an internal transfer acknowledge is generated for burst transfer
- * secondary terminations.
- */
-//@{
-#define BP_FB_CSCRn_SWSEN (23U) //!< Bit position for FB_CSCRn_SWSEN.
-#define BM_FB_CSCRn_SWSEN (0x00800000U) //!< Bit mask for FB_CSCRn_SWSEN.
-#define BS_FB_CSCRn_SWSEN (1U) //!< Bit field size in bits for FB_CSCRn_SWSEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FB_CSCRn_SWSEN field.
-#define BR_FB_CSCRn_SWSEN(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_SWSEN))
-#endif
-
-//! @brief Format value for bitfield FB_CSCRn_SWSEN.
-#define BF_FB_CSCRn_SWSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_SWSEN), uint32_t) & BM_FB_CSCRn_SWSEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SWSEN field to a new value.
-#define BW_FB_CSCRn_SWSEN(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_SWSEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FB_CSCRn, field SWS[31:26] (RW)
- *
- * Used only when the SWSEN bit is 1b. Specifies the number of wait states
- * inserted before an internal transfer acknowledge is generated for a burst transfer
- * (except for the first termination, which is controlled by WS).
- */
-//@{
-#define BP_FB_CSCRn_SWS (26U) //!< Bit position for FB_CSCRn_SWS.
-#define BM_FB_CSCRn_SWS (0xFC000000U) //!< Bit mask for FB_CSCRn_SWS.
-#define BS_FB_CSCRn_SWS (6U) //!< Bit field size in bits for FB_CSCRn_SWS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FB_CSCRn_SWS field.
-#define BR_FB_CSCRn_SWS(n) (HW_FB_CSCRn(n).B.SWS)
-#endif
-
-//! @brief Format value for bitfield FB_CSCRn_SWS.
-#define BF_FB_CSCRn_SWS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_SWS), uint32_t) & BM_FB_CSCRn_SWS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SWS field to a new value.
-#define BW_FB_CSCRn_SWS(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_SWS) | BF_FB_CSCRn_SWS(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FB_CSPMCR - Chip Select port Multiplexing Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FB_CSPMCR - Chip Select port Multiplexing Control Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * Controls the multiplexing of the FlexBus signals. A bus error occurs when you
- * do any of the following: Write to a reserved address Write to a reserved
- * field in this register, or Access this register using a size other than 32 bits.
- */
-typedef union _hw_fb_cspmcr
-{
- uint32_t U;
- struct _hw_fb_cspmcr_bitfields
- {
- uint32_t RESERVED0 : 12; //!< [11:0]
- uint32_t GROUP5 : 4; //!< [15:12] FlexBus Signal Group 5 Multiplex
- //! control
- uint32_t GROUP4 : 4; //!< [19:16] FlexBus Signal Group 4 Multiplex
- //! control
- uint32_t GROUP3 : 4; //!< [23:20] FlexBus Signal Group 3 Multiplex
- //! control
- uint32_t GROUP2 : 4; //!< [27:24] FlexBus Signal Group 2 Multiplex
- //! control
- uint32_t GROUP1 : 4; //!< [31:28] FlexBus Signal Group 1 Multiplex
- //! control
- } B;
-} hw_fb_cspmcr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FB_CSPMCR register
- */
-//@{
-#define HW_FB_CSPMCR_ADDR (REGS_FB_BASE + 0x60U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FB_CSPMCR (*(__IO hw_fb_cspmcr_t *) HW_FB_CSPMCR_ADDR)
-#define HW_FB_CSPMCR_RD() (HW_FB_CSPMCR.U)
-#define HW_FB_CSPMCR_WR(v) (HW_FB_CSPMCR.U = (v))
-#define HW_FB_CSPMCR_SET(v) (HW_FB_CSPMCR_WR(HW_FB_CSPMCR_RD() | (v)))
-#define HW_FB_CSPMCR_CLR(v) (HW_FB_CSPMCR_WR(HW_FB_CSPMCR_RD() & ~(v)))
-#define HW_FB_CSPMCR_TOG(v) (HW_FB_CSPMCR_WR(HW_FB_CSPMCR_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FB_CSPMCR bitfields
- */
-
-/*!
- * @name Register FB_CSPMCR, field GROUP5[15:12] (RW)
- *
- * Controls the multiplexing of the FB_TA , FB_CS3 , and FB_BE_7_0 signals. When
- * GROUP5 is not 0000b, you must write 1b to the CSCR[AA] bit. Otherwise, the
- * bus hangs during a transfer.
- *
- * Values:
- * - 0000 - FB_TA
- * - 0001 - FB_CS3 . You must also write 1b to CSCR[AA].
- * - 0010 - FB_BE_7_0 . You must also write 1b to CSCR[AA].
- */
-//@{
-#define BP_FB_CSPMCR_GROUP5 (12U) //!< Bit position for FB_CSPMCR_GROUP5.
-#define BM_FB_CSPMCR_GROUP5 (0x0000F000U) //!< Bit mask for FB_CSPMCR_GROUP5.
-#define BS_FB_CSPMCR_GROUP5 (4U) //!< Bit field size in bits for FB_CSPMCR_GROUP5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FB_CSPMCR_GROUP5 field.
-#define BR_FB_CSPMCR_GROUP5 (HW_FB_CSPMCR.B.GROUP5)
-#endif
-
-//! @brief Format value for bitfield FB_CSPMCR_GROUP5.
-#define BF_FB_CSPMCR_GROUP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP5), uint32_t) & BM_FB_CSPMCR_GROUP5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the GROUP5 field to a new value.
-#define BW_FB_CSPMCR_GROUP5(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP5) | BF_FB_CSPMCR_GROUP5(v)))
-#endif
-//@}
-
-/*!
- * @name Register FB_CSPMCR, field GROUP4[19:16] (RW)
- *
- * Controls the multiplexing of the FB_TBST , FB_CS2 , and FB_BE_15_8 signals.
- *
- * Values:
- * - 0000 - FB_TBST
- * - 0001 - FB_CS2
- * - 0010 - FB_BE_15_8
- */
-//@{
-#define BP_FB_CSPMCR_GROUP4 (16U) //!< Bit position for FB_CSPMCR_GROUP4.
-#define BM_FB_CSPMCR_GROUP4 (0x000F0000U) //!< Bit mask for FB_CSPMCR_GROUP4.
-#define BS_FB_CSPMCR_GROUP4 (4U) //!< Bit field size in bits for FB_CSPMCR_GROUP4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FB_CSPMCR_GROUP4 field.
-#define BR_FB_CSPMCR_GROUP4 (HW_FB_CSPMCR.B.GROUP4)
-#endif
-
-//! @brief Format value for bitfield FB_CSPMCR_GROUP4.
-#define BF_FB_CSPMCR_GROUP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP4), uint32_t) & BM_FB_CSPMCR_GROUP4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the GROUP4 field to a new value.
-#define BW_FB_CSPMCR_GROUP4(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP4) | BF_FB_CSPMCR_GROUP4(v)))
-#endif
-//@}
-
-/*!
- * @name Register FB_CSPMCR, field GROUP3[23:20] (RW)
- *
- * Controls the multiplexing of the FB_CS5 , FB_TSIZ1, and FB_BE_23_16 signals.
- *
- * Values:
- * - 0000 - FB_CS5
- * - 0001 - FB_TSIZ1
- * - 0010 - FB_BE_23_16
- */
-//@{
-#define BP_FB_CSPMCR_GROUP3 (20U) //!< Bit position for FB_CSPMCR_GROUP3.
-#define BM_FB_CSPMCR_GROUP3 (0x00F00000U) //!< Bit mask for FB_CSPMCR_GROUP3.
-#define BS_FB_CSPMCR_GROUP3 (4U) //!< Bit field size in bits for FB_CSPMCR_GROUP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FB_CSPMCR_GROUP3 field.
-#define BR_FB_CSPMCR_GROUP3 (HW_FB_CSPMCR.B.GROUP3)
-#endif
-
-//! @brief Format value for bitfield FB_CSPMCR_GROUP3.
-#define BF_FB_CSPMCR_GROUP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP3), uint32_t) & BM_FB_CSPMCR_GROUP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the GROUP3 field to a new value.
-#define BW_FB_CSPMCR_GROUP3(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP3) | BF_FB_CSPMCR_GROUP3(v)))
-#endif
-//@}
-
-/*!
- * @name Register FB_CSPMCR, field GROUP2[27:24] (RW)
- *
- * Controls the multiplexing of the FB_CS4 , FB_TSIZ0, and FB_BE_31_24 signals.
- *
- * Values:
- * - 0000 - FB_CS4
- * - 0001 - FB_TSIZ0
- * - 0010 - FB_BE_31_24
- */
-//@{
-#define BP_FB_CSPMCR_GROUP2 (24U) //!< Bit position for FB_CSPMCR_GROUP2.
-#define BM_FB_CSPMCR_GROUP2 (0x0F000000U) //!< Bit mask for FB_CSPMCR_GROUP2.
-#define BS_FB_CSPMCR_GROUP2 (4U) //!< Bit field size in bits for FB_CSPMCR_GROUP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FB_CSPMCR_GROUP2 field.
-#define BR_FB_CSPMCR_GROUP2 (HW_FB_CSPMCR.B.GROUP2)
-#endif
-
-//! @brief Format value for bitfield FB_CSPMCR_GROUP2.
-#define BF_FB_CSPMCR_GROUP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP2), uint32_t) & BM_FB_CSPMCR_GROUP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the GROUP2 field to a new value.
-#define BW_FB_CSPMCR_GROUP2(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP2) | BF_FB_CSPMCR_GROUP2(v)))
-#endif
-//@}
-
-/*!
- * @name Register FB_CSPMCR, field GROUP1[31:28] (RW)
- *
- * Controls the multiplexing of the FB_ALE, FB_CS1 , and FB_TS signals.
- *
- * Values:
- * - 0000 - FB_ALE
- * - 0001 - FB_CS1
- * - 0010 - FB_TS
- */
-//@{
-#define BP_FB_CSPMCR_GROUP1 (28U) //!< Bit position for FB_CSPMCR_GROUP1.
-#define BM_FB_CSPMCR_GROUP1 (0xF0000000U) //!< Bit mask for FB_CSPMCR_GROUP1.
-#define BS_FB_CSPMCR_GROUP1 (4U) //!< Bit field size in bits for FB_CSPMCR_GROUP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FB_CSPMCR_GROUP1 field.
-#define BR_FB_CSPMCR_GROUP1 (HW_FB_CSPMCR.B.GROUP1)
-#endif
-
-//! @brief Format value for bitfield FB_CSPMCR_GROUP1.
-#define BF_FB_CSPMCR_GROUP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP1), uint32_t) & BM_FB_CSPMCR_GROUP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the GROUP1 field to a new value.
-#define BW_FB_CSPMCR_GROUP1(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP1) | BF_FB_CSPMCR_GROUP1(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_fb_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All FB module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_fb
-{
- struct {
- __IO hw_fb_csarn_t CSARn; //!< [0x0] Chip Select Address Register
- __IO hw_fb_csmrn_t CSMRn; //!< [0x4] Chip Select Mask Register
- __IO hw_fb_cscrn_t CSCRn; //!< [0x8] Chip Select Control Register
- } CS[6];
- uint8_t _reserved0[24];
- __IO hw_fb_cspmcr_t CSPMCR; //!< [0x60] Chip Select port Multiplexing Control Register
-} hw_fb_t;
-#pragma pack()
-
-//! @brief Macro to access all FB registers.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_FB</code>.
-#define HW_FB (*(hw_fb_t *) REGS_FB_BASE)
-#endif
-
-#endif // __HW_FB_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_fmc.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,2177 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_FMC_REGISTERS_H__
-#define __HW_FMC_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 FMC
- *
- * Flash Memory Controller
- *
- * Registers defined in this header file:
- * - HW_FMC_PFAPR - Flash Access Protection Register
- * - HW_FMC_PFB0CR - Flash Bank 0 Control Register
- * - HW_FMC_PFB1CR - Flash Bank 1 Control Register
- * - HW_FMC_TAGVDW0Sn - Cache Tag Storage
- * - HW_FMC_TAGVDW1Sn - Cache Tag Storage
- * - HW_FMC_TAGVDW2Sn - Cache Tag Storage
- * - HW_FMC_TAGVDW3Sn - Cache Tag Storage
- * - HW_FMC_DATAW0SnU - Cache Data Storage (upper word)
- * - HW_FMC_DATAW0SnL - Cache Data Storage (lower word)
- * - HW_FMC_DATAW1SnU - Cache Data Storage (upper word)
- * - HW_FMC_DATAW1SnL - Cache Data Storage (lower word)
- * - HW_FMC_DATAW2SnU - Cache Data Storage (upper word)
- * - HW_FMC_DATAW2SnL - Cache Data Storage (lower word)
- * - HW_FMC_DATAW3SnU - Cache Data Storage (upper word)
- * - HW_FMC_DATAW3SnL - Cache Data Storage (lower word)
- *
- * - hw_fmc_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_FMC_BASE
-#define HW_FMC_INSTANCE_COUNT (1U) //!< Number of instances of the FMC module.
-#define REGS_FMC_BASE (0x4001F000U) //!< Base address for FMC.
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FMC_PFAPR - Flash Access Protection Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FMC_PFAPR - Flash Access Protection Register (RW)
- *
- * Reset value: 0x00F8003FU
- */
-typedef union _hw_fmc_pfapr
-{
- uint32_t U;
- struct _hw_fmc_pfapr_bitfields
- {
- uint32_t M0AP : 2; //!< [1:0] Master 0 Access Protection
- uint32_t M1AP : 2; //!< [3:2] Master 1 Access Protection
- uint32_t M2AP : 2; //!< [5:4] Master 2 Access Protection
- uint32_t M3AP : 2; //!< [7:6] Master 3 Access Protection
- uint32_t M4AP : 2; //!< [9:8] Master 4 Access Protection
- uint32_t M5AP : 2; //!< [11:10] Master 5 Access Protection
- uint32_t M6AP : 2; //!< [13:12] Master 6 Access Protection
- uint32_t M7AP : 2; //!< [15:14] Master 7 Access Protection
- uint32_t M0PFD : 1; //!< [16] Master 0 Prefetch Disable
- uint32_t M1PFD : 1; //!< [17] Master 1 Prefetch Disable
- uint32_t M2PFD : 1; //!< [18] Master 2 Prefetch Disable
- uint32_t M3PFD : 1; //!< [19] Master 3 Prefetch Disable
- uint32_t M4PFD : 1; //!< [20] Master 4 Prefetch Disable
- uint32_t M5PFD : 1; //!< [21] Master 5 Prefetch Disable
- uint32_t M6PFD : 1; //!< [22] Master 6 Prefetch Disable
- uint32_t M7PFD : 1; //!< [23] Master 7 Prefetch Disable
- uint32_t RESERVED0 : 8; //!< [31:24]
- } B;
-} hw_fmc_pfapr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FMC_PFAPR register
- */
-//@{
-#define HW_FMC_PFAPR_ADDR (REGS_FMC_BASE + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FMC_PFAPR (*(__IO hw_fmc_pfapr_t *) HW_FMC_PFAPR_ADDR)
-#define HW_FMC_PFAPR_RD() (HW_FMC_PFAPR.U)
-#define HW_FMC_PFAPR_WR(v) (HW_FMC_PFAPR.U = (v))
-#define HW_FMC_PFAPR_SET(v) (HW_FMC_PFAPR_WR(HW_FMC_PFAPR_RD() | (v)))
-#define HW_FMC_PFAPR_CLR(v) (HW_FMC_PFAPR_WR(HW_FMC_PFAPR_RD() & ~(v)))
-#define HW_FMC_PFAPR_TOG(v) (HW_FMC_PFAPR_WR(HW_FMC_PFAPR_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FMC_PFAPR bitfields
- */
-
-/*!
- * @name Register FMC_PFAPR, field M0AP[1:0] (RW)
- *
- * This field controls whether read and write access to the flash are allowed
- * based on the logical master number of the requesting crossbar switch master.
- *
- * Values:
- * - 00 - No access may be performed by this master
- * - 01 - Only read accesses may be performed by this master
- * - 10 - Only write accesses may be performed by this master
- * - 11 - Both read and write accesses may be performed by this master
- */
-//@{
-#define BP_FMC_PFAPR_M0AP (0U) //!< Bit position for FMC_PFAPR_M0AP.
-#define BM_FMC_PFAPR_M0AP (0x00000003U) //!< Bit mask for FMC_PFAPR_M0AP.
-#define BS_FMC_PFAPR_M0AP (2U) //!< Bit field size in bits for FMC_PFAPR_M0AP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFAPR_M0AP field.
-#define BR_FMC_PFAPR_M0AP (HW_FMC_PFAPR.B.M0AP)
-#endif
-
-//! @brief Format value for bitfield FMC_PFAPR_M0AP.
-#define BF_FMC_PFAPR_M0AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M0AP), uint32_t) & BM_FMC_PFAPR_M0AP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M0AP field to a new value.
-#define BW_FMC_PFAPR_M0AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M0AP) | BF_FMC_PFAPR_M0AP(v)))
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFAPR, field M1AP[3:2] (RW)
- *
- * This field controls whether read and write access to the flash are allowed
- * based on the logical master number of the requesting crossbar switch master.
- *
- * Values:
- * - 00 - No access may be performed by this master
- * - 01 - Only read accesses may be performed by this master
- * - 10 - Only write accesses may be performed by this master
- * - 11 - Both read and write accesses may be performed by this master
- */
-//@{
-#define BP_FMC_PFAPR_M1AP (2U) //!< Bit position for FMC_PFAPR_M1AP.
-#define BM_FMC_PFAPR_M1AP (0x0000000CU) //!< Bit mask for FMC_PFAPR_M1AP.
-#define BS_FMC_PFAPR_M1AP (2U) //!< Bit field size in bits for FMC_PFAPR_M1AP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFAPR_M1AP field.
-#define BR_FMC_PFAPR_M1AP (HW_FMC_PFAPR.B.M1AP)
-#endif
-
-//! @brief Format value for bitfield FMC_PFAPR_M1AP.
-#define BF_FMC_PFAPR_M1AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M1AP), uint32_t) & BM_FMC_PFAPR_M1AP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M1AP field to a new value.
-#define BW_FMC_PFAPR_M1AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M1AP) | BF_FMC_PFAPR_M1AP(v)))
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFAPR, field M2AP[5:4] (RW)
- *
- * This field controls whether read and write access to the flash are allowed
- * based on the logical master number of the requesting crossbar switch master.
- *
- * Values:
- * - 00 - No access may be performed by this master
- * - 01 - Only read accesses may be performed by this master
- * - 10 - Only write accesses may be performed by this master
- * - 11 - Both read and write accesses may be performed by this master
- */
-//@{
-#define BP_FMC_PFAPR_M2AP (4U) //!< Bit position for FMC_PFAPR_M2AP.
-#define BM_FMC_PFAPR_M2AP (0x00000030U) //!< Bit mask for FMC_PFAPR_M2AP.
-#define BS_FMC_PFAPR_M2AP (2U) //!< Bit field size in bits for FMC_PFAPR_M2AP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFAPR_M2AP field.
-#define BR_FMC_PFAPR_M2AP (HW_FMC_PFAPR.B.M2AP)
-#endif
-
-//! @brief Format value for bitfield FMC_PFAPR_M2AP.
-#define BF_FMC_PFAPR_M2AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M2AP), uint32_t) & BM_FMC_PFAPR_M2AP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M2AP field to a new value.
-#define BW_FMC_PFAPR_M2AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M2AP) | BF_FMC_PFAPR_M2AP(v)))
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFAPR, field M3AP[7:6] (RW)
- *
- * This field controls whether read and write access to the flash are allowed
- * based on the logical master number of the requesting crossbar switch master.
- *
- * Values:
- * - 00 - No access may be performed by this master
- * - 01 - Only read accesses may be performed by this master
- * - 10 - Only write accesses may be performed by this master
- * - 11 - Both read and write accesses may be performed by this master
- */
-//@{
-#define BP_FMC_PFAPR_M3AP (6U) //!< Bit position for FMC_PFAPR_M3AP.
-#define BM_FMC_PFAPR_M3AP (0x000000C0U) //!< Bit mask for FMC_PFAPR_M3AP.
-#define BS_FMC_PFAPR_M3AP (2U) //!< Bit field size in bits for FMC_PFAPR_M3AP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFAPR_M3AP field.
-#define BR_FMC_PFAPR_M3AP (HW_FMC_PFAPR.B.M3AP)
-#endif
-
-//! @brief Format value for bitfield FMC_PFAPR_M3AP.
-#define BF_FMC_PFAPR_M3AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M3AP), uint32_t) & BM_FMC_PFAPR_M3AP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M3AP field to a new value.
-#define BW_FMC_PFAPR_M3AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M3AP) | BF_FMC_PFAPR_M3AP(v)))
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFAPR, field M4AP[9:8] (RW)
- *
- * This field controls whether read and write access to the flash are allowed
- * based on the logical master number of the requesting crossbar switch master.
- *
- * Values:
- * - 00 - No access may be performed by this master
- * - 01 - Only read accesses may be performed by this master
- * - 10 - Only write accesses may be performed by this master
- * - 11 - Both read and write accesses may be performed by this master
- */
-//@{
-#define BP_FMC_PFAPR_M4AP (8U) //!< Bit position for FMC_PFAPR_M4AP.
-#define BM_FMC_PFAPR_M4AP (0x00000300U) //!< Bit mask for FMC_PFAPR_M4AP.
-#define BS_FMC_PFAPR_M4AP (2U) //!< Bit field size in bits for FMC_PFAPR_M4AP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFAPR_M4AP field.
-#define BR_FMC_PFAPR_M4AP (HW_FMC_PFAPR.B.M4AP)
-#endif
-
-//! @brief Format value for bitfield FMC_PFAPR_M4AP.
-#define BF_FMC_PFAPR_M4AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M4AP), uint32_t) & BM_FMC_PFAPR_M4AP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M4AP field to a new value.
-#define BW_FMC_PFAPR_M4AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M4AP) | BF_FMC_PFAPR_M4AP(v)))
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFAPR, field M5AP[11:10] (RW)
- *
- * This field controls whether read and write access to the flash are allowed
- * based on the logical master number of the requesting crossbar switch master.
- *
- * Values:
- * - 00 - No access may be performed by this master
- * - 01 - Only read accesses may be performed by this master
- * - 10 - Only write accesses may be performed by this master
- * - 11 - Both read and write accesses may be performed by this master
- */
-//@{
-#define BP_FMC_PFAPR_M5AP (10U) //!< Bit position for FMC_PFAPR_M5AP.
-#define BM_FMC_PFAPR_M5AP (0x00000C00U) //!< Bit mask for FMC_PFAPR_M5AP.
-#define BS_FMC_PFAPR_M5AP (2U) //!< Bit field size in bits for FMC_PFAPR_M5AP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFAPR_M5AP field.
-#define BR_FMC_PFAPR_M5AP (HW_FMC_PFAPR.B.M5AP)
-#endif
-
-//! @brief Format value for bitfield FMC_PFAPR_M5AP.
-#define BF_FMC_PFAPR_M5AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M5AP), uint32_t) & BM_FMC_PFAPR_M5AP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M5AP field to a new value.
-#define BW_FMC_PFAPR_M5AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M5AP) | BF_FMC_PFAPR_M5AP(v)))
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFAPR, field M6AP[13:12] (RW)
- *
- * This field controls whether read and write access to the flash are allowed
- * based on the logical master number of the requesting crossbar switch master.
- *
- * Values:
- * - 00 - No access may be performed by this master
- * - 01 - Only read accesses may be performed by this master
- * - 10 - Only write accesses may be performed by this master
- * - 11 - Both read and write accesses may be performed by this master
- */
-//@{
-#define BP_FMC_PFAPR_M6AP (12U) //!< Bit position for FMC_PFAPR_M6AP.
-#define BM_FMC_PFAPR_M6AP (0x00003000U) //!< Bit mask for FMC_PFAPR_M6AP.
-#define BS_FMC_PFAPR_M6AP (2U) //!< Bit field size in bits for FMC_PFAPR_M6AP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFAPR_M6AP field.
-#define BR_FMC_PFAPR_M6AP (HW_FMC_PFAPR.B.M6AP)
-#endif
-
-//! @brief Format value for bitfield FMC_PFAPR_M6AP.
-#define BF_FMC_PFAPR_M6AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M6AP), uint32_t) & BM_FMC_PFAPR_M6AP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M6AP field to a new value.
-#define BW_FMC_PFAPR_M6AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M6AP) | BF_FMC_PFAPR_M6AP(v)))
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFAPR, field M7AP[15:14] (RW)
- *
- * This field controls whether read and write access to the flash are allowed
- * based on the logical master number of the requesting crossbar switch master.
- *
- * Values:
- * - 00 - No access may be performed by this master.
- * - 01 - Only read accesses may be performed by this master.
- * - 10 - Only write accesses may be performed by this master.
- * - 11 - Both read and write accesses may be performed by this master.
- */
-//@{
-#define BP_FMC_PFAPR_M7AP (14U) //!< Bit position for FMC_PFAPR_M7AP.
-#define BM_FMC_PFAPR_M7AP (0x0000C000U) //!< Bit mask for FMC_PFAPR_M7AP.
-#define BS_FMC_PFAPR_M7AP (2U) //!< Bit field size in bits for FMC_PFAPR_M7AP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFAPR_M7AP field.
-#define BR_FMC_PFAPR_M7AP (HW_FMC_PFAPR.B.M7AP)
-#endif
-
-//! @brief Format value for bitfield FMC_PFAPR_M7AP.
-#define BF_FMC_PFAPR_M7AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M7AP), uint32_t) & BM_FMC_PFAPR_M7AP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M7AP field to a new value.
-#define BW_FMC_PFAPR_M7AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M7AP) | BF_FMC_PFAPR_M7AP(v)))
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFAPR, field M0PFD[16] (RW)
- *
- * These bits control whether prefetching is enabled based on the logical number
- * of the requesting crossbar switch master. This field is further qualified by
- * the PFBnCR[BxDPE,BxIPE] bits.
- *
- * Values:
- * - 0 - Prefetching for this master is enabled.
- * - 1 - Prefetching for this master is disabled.
- */
-//@{
-#define BP_FMC_PFAPR_M0PFD (16U) //!< Bit position for FMC_PFAPR_M0PFD.
-#define BM_FMC_PFAPR_M0PFD (0x00010000U) //!< Bit mask for FMC_PFAPR_M0PFD.
-#define BS_FMC_PFAPR_M0PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M0PFD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFAPR_M0PFD field.
-#define BR_FMC_PFAPR_M0PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M0PFD))
-#endif
-
-//! @brief Format value for bitfield FMC_PFAPR_M0PFD.
-#define BF_FMC_PFAPR_M0PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M0PFD), uint32_t) & BM_FMC_PFAPR_M0PFD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M0PFD field to a new value.
-#define BW_FMC_PFAPR_M0PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M0PFD) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFAPR, field M1PFD[17] (RW)
- *
- * These bits control whether prefetching is enabled based on the logical number
- * of the requesting crossbar switch master. This field is further qualified by
- * the PFBnCR[BxDPE,BxIPE] bits.
- *
- * Values:
- * - 0 - Prefetching for this master is enabled.
- * - 1 - Prefetching for this master is disabled.
- */
-//@{
-#define BP_FMC_PFAPR_M1PFD (17U) //!< Bit position for FMC_PFAPR_M1PFD.
-#define BM_FMC_PFAPR_M1PFD (0x00020000U) //!< Bit mask for FMC_PFAPR_M1PFD.
-#define BS_FMC_PFAPR_M1PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M1PFD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFAPR_M1PFD field.
-#define BR_FMC_PFAPR_M1PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M1PFD))
-#endif
-
-//! @brief Format value for bitfield FMC_PFAPR_M1PFD.
-#define BF_FMC_PFAPR_M1PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M1PFD), uint32_t) & BM_FMC_PFAPR_M1PFD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M1PFD field to a new value.
-#define BW_FMC_PFAPR_M1PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M1PFD) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFAPR, field M2PFD[18] (RW)
- *
- * These bits control whether prefetching is enabled based on the logical number
- * of the requesting crossbar switch master. This field is further qualified by
- * the PFBnCR[BxDPE,BxIPE] bits.
- *
- * Values:
- * - 0 - Prefetching for this master is enabled.
- * - 1 - Prefetching for this master is disabled.
- */
-//@{
-#define BP_FMC_PFAPR_M2PFD (18U) //!< Bit position for FMC_PFAPR_M2PFD.
-#define BM_FMC_PFAPR_M2PFD (0x00040000U) //!< Bit mask for FMC_PFAPR_M2PFD.
-#define BS_FMC_PFAPR_M2PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M2PFD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFAPR_M2PFD field.
-#define BR_FMC_PFAPR_M2PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M2PFD))
-#endif
-
-//! @brief Format value for bitfield FMC_PFAPR_M2PFD.
-#define BF_FMC_PFAPR_M2PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M2PFD), uint32_t) & BM_FMC_PFAPR_M2PFD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M2PFD field to a new value.
-#define BW_FMC_PFAPR_M2PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M2PFD) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFAPR, field M3PFD[19] (RW)
- *
- * These bits control whether prefetching is enabled based on the logical number
- * of the requesting crossbar switch master. This field is further qualified by
- * the PFBnCR[BxDPE,BxIPE] bits.
- *
- * Values:
- * - 0 - Prefetching for this master is enabled.
- * - 1 - Prefetching for this master is disabled.
- */
-//@{
-#define BP_FMC_PFAPR_M3PFD (19U) //!< Bit position for FMC_PFAPR_M3PFD.
-#define BM_FMC_PFAPR_M3PFD (0x00080000U) //!< Bit mask for FMC_PFAPR_M3PFD.
-#define BS_FMC_PFAPR_M3PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M3PFD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFAPR_M3PFD field.
-#define BR_FMC_PFAPR_M3PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M3PFD))
-#endif
-
-//! @brief Format value for bitfield FMC_PFAPR_M3PFD.
-#define BF_FMC_PFAPR_M3PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M3PFD), uint32_t) & BM_FMC_PFAPR_M3PFD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M3PFD field to a new value.
-#define BW_FMC_PFAPR_M3PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M3PFD) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFAPR, field M4PFD[20] (RW)
- *
- * These bits control whether prefetching is enabled based on the logical number
- * of the requesting crossbar switch master. This field is further qualified by
- * the PFBnCR[BxDPE,BxIPE] bits.
- *
- * Values:
- * - 0 - Prefetching for this master is enabled.
- * - 1 - Prefetching for this master is disabled.
- */
-//@{
-#define BP_FMC_PFAPR_M4PFD (20U) //!< Bit position for FMC_PFAPR_M4PFD.
-#define BM_FMC_PFAPR_M4PFD (0x00100000U) //!< Bit mask for FMC_PFAPR_M4PFD.
-#define BS_FMC_PFAPR_M4PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M4PFD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFAPR_M4PFD field.
-#define BR_FMC_PFAPR_M4PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M4PFD))
-#endif
-
-//! @brief Format value for bitfield FMC_PFAPR_M4PFD.
-#define BF_FMC_PFAPR_M4PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M4PFD), uint32_t) & BM_FMC_PFAPR_M4PFD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M4PFD field to a new value.
-#define BW_FMC_PFAPR_M4PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M4PFD) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFAPR, field M5PFD[21] (RW)
- *
- * These bits control whether prefetching is enabled based on the logical number
- * of the requesting crossbar switch master. This field is further qualified by
- * the PFBnCR[BxDPE,BxIPE] bits.
- *
- * Values:
- * - 0 - Prefetching for this master is enabled.
- * - 1 - Prefetching for this master is disabled.
- */
-//@{
-#define BP_FMC_PFAPR_M5PFD (21U) //!< Bit position for FMC_PFAPR_M5PFD.
-#define BM_FMC_PFAPR_M5PFD (0x00200000U) //!< Bit mask for FMC_PFAPR_M5PFD.
-#define BS_FMC_PFAPR_M5PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M5PFD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFAPR_M5PFD field.
-#define BR_FMC_PFAPR_M5PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M5PFD))
-#endif
-
-//! @brief Format value for bitfield FMC_PFAPR_M5PFD.
-#define BF_FMC_PFAPR_M5PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M5PFD), uint32_t) & BM_FMC_PFAPR_M5PFD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M5PFD field to a new value.
-#define BW_FMC_PFAPR_M5PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M5PFD) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFAPR, field M6PFD[22] (RW)
- *
- * These bits control whether prefetching is enabled based on the logical number
- * of the requesting crossbar switch master. This field is further qualified by
- * the PFBnCR[BxDPE,BxIPE] bits.
- *
- * Values:
- * - 0 - Prefetching for this master is enabled.
- * - 1 - Prefetching for this master is disabled.
- */
-//@{
-#define BP_FMC_PFAPR_M6PFD (22U) //!< Bit position for FMC_PFAPR_M6PFD.
-#define BM_FMC_PFAPR_M6PFD (0x00400000U) //!< Bit mask for FMC_PFAPR_M6PFD.
-#define BS_FMC_PFAPR_M6PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M6PFD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFAPR_M6PFD field.
-#define BR_FMC_PFAPR_M6PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M6PFD))
-#endif
-
-//! @brief Format value for bitfield FMC_PFAPR_M6PFD.
-#define BF_FMC_PFAPR_M6PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M6PFD), uint32_t) & BM_FMC_PFAPR_M6PFD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M6PFD field to a new value.
-#define BW_FMC_PFAPR_M6PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M6PFD) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFAPR, field M7PFD[23] (RW)
- *
- * These bits control whether prefetching is enabled based on the logical number
- * of the requesting crossbar switch master. This field is further qualified by
- * the PFBnCR[BxDPE,BxIPE] bits.
- *
- * Values:
- * - 0 - Prefetching for this master is enabled.
- * - 1 - Prefetching for this master is disabled.
- */
-//@{
-#define BP_FMC_PFAPR_M7PFD (23U) //!< Bit position for FMC_PFAPR_M7PFD.
-#define BM_FMC_PFAPR_M7PFD (0x00800000U) //!< Bit mask for FMC_PFAPR_M7PFD.
-#define BS_FMC_PFAPR_M7PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M7PFD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFAPR_M7PFD field.
-#define BR_FMC_PFAPR_M7PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M7PFD))
-#endif
-
-//! @brief Format value for bitfield FMC_PFAPR_M7PFD.
-#define BF_FMC_PFAPR_M7PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M7PFD), uint32_t) & BM_FMC_PFAPR_M7PFD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M7PFD field to a new value.
-#define BW_FMC_PFAPR_M7PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M7PFD) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FMC_PFB0CR - Flash Bank 0 Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FMC_PFB0CR - Flash Bank 0 Control Register (RW)
- *
- * Reset value: 0x3004001FU
- */
-typedef union _hw_fmc_pfb0cr
-{
- uint32_t U;
- struct _hw_fmc_pfb0cr_bitfields
- {
- uint32_t B0SEBE : 1; //!< [0] Bank 0 Single Entry Buffer Enable
- uint32_t B0IPE : 1; //!< [1] Bank 0 Instruction Prefetch Enable
- uint32_t B0DPE : 1; //!< [2] Bank 0 Data Prefetch Enable
- uint32_t B0ICE : 1; //!< [3] Bank 0 Instruction Cache Enable
- uint32_t B0DCE : 1; //!< [4] Bank 0 Data Cache Enable
- uint32_t CRCb : 3; //!< [7:5] Cache Replacement Control
- uint32_t RESERVED0 : 9; //!< [16:8]
- uint32_t B0MW : 2; //!< [18:17] Bank 0 Memory Width
- uint32_t S_B_INV : 1; //!< [19] Invalidate Prefetch Speculation Buffer
- uint32_t CINV_WAY : 4; //!< [23:20] Cache Invalidate Way x
- uint32_t CLCK_WAY : 4; //!< [27:24] Cache Lock Way x
- uint32_t B0RWSC : 4; //!< [31:28] Bank 0 Read Wait State Control
- } B;
-} hw_fmc_pfb0cr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FMC_PFB0CR register
- */
-//@{
-#define HW_FMC_PFB0CR_ADDR (REGS_FMC_BASE + 0x4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FMC_PFB0CR (*(__IO hw_fmc_pfb0cr_t *) HW_FMC_PFB0CR_ADDR)
-#define HW_FMC_PFB0CR_RD() (HW_FMC_PFB0CR.U)
-#define HW_FMC_PFB0CR_WR(v) (HW_FMC_PFB0CR.U = (v))
-#define HW_FMC_PFB0CR_SET(v) (HW_FMC_PFB0CR_WR(HW_FMC_PFB0CR_RD() | (v)))
-#define HW_FMC_PFB0CR_CLR(v) (HW_FMC_PFB0CR_WR(HW_FMC_PFB0CR_RD() & ~(v)))
-#define HW_FMC_PFB0CR_TOG(v) (HW_FMC_PFB0CR_WR(HW_FMC_PFB0CR_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FMC_PFB0CR bitfields
- */
-
-/*!
- * @name Register FMC_PFB0CR, field B0SEBE[0] (RW)
- *
- * This bit controls whether the single entry page buffer is enabled in response
- * to flash read accesses. Its operation is independent from bank 1's cache. A
- * high-to-low transition of this enable forces the page buffer to be invalidated.
- *
- * Values:
- * - 0 - Single entry buffer is disabled.
- * - 1 - Single entry buffer is enabled.
- */
-//@{
-#define BP_FMC_PFB0CR_B0SEBE (0U) //!< Bit position for FMC_PFB0CR_B0SEBE.
-#define BM_FMC_PFB0CR_B0SEBE (0x00000001U) //!< Bit mask for FMC_PFB0CR_B0SEBE.
-#define BS_FMC_PFB0CR_B0SEBE (1U) //!< Bit field size in bits for FMC_PFB0CR_B0SEBE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFB0CR_B0SEBE field.
-#define BR_FMC_PFB0CR_B0SEBE (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0SEBE))
-#endif
-
-//! @brief Format value for bitfield FMC_PFB0CR_B0SEBE.
-#define BF_FMC_PFB0CR_B0SEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_B0SEBE), uint32_t) & BM_FMC_PFB0CR_B0SEBE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the B0SEBE field to a new value.
-#define BW_FMC_PFB0CR_B0SEBE(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0SEBE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFB0CR, field B0IPE[1] (RW)
- *
- * This bit controls whether prefetches (or speculative accesses) are initiated
- * in response to instruction fetches.
- *
- * Values:
- * - 0 - Do not prefetch in response to instruction fetches.
- * - 1 - Enable prefetches in response to instruction fetches.
- */
-//@{
-#define BP_FMC_PFB0CR_B0IPE (1U) //!< Bit position for FMC_PFB0CR_B0IPE.
-#define BM_FMC_PFB0CR_B0IPE (0x00000002U) //!< Bit mask for FMC_PFB0CR_B0IPE.
-#define BS_FMC_PFB0CR_B0IPE (1U) //!< Bit field size in bits for FMC_PFB0CR_B0IPE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFB0CR_B0IPE field.
-#define BR_FMC_PFB0CR_B0IPE (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0IPE))
-#endif
-
-//! @brief Format value for bitfield FMC_PFB0CR_B0IPE.
-#define BF_FMC_PFB0CR_B0IPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_B0IPE), uint32_t) & BM_FMC_PFB0CR_B0IPE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the B0IPE field to a new value.
-#define BW_FMC_PFB0CR_B0IPE(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0IPE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFB0CR, field B0DPE[2] (RW)
- *
- * This bit controls whether prefetches (or speculative accesses) are initiated
- * in response to data references.
- *
- * Values:
- * - 0 - Do not prefetch in response to data references.
- * - 1 - Enable prefetches in response to data references.
- */
-//@{
-#define BP_FMC_PFB0CR_B0DPE (2U) //!< Bit position for FMC_PFB0CR_B0DPE.
-#define BM_FMC_PFB0CR_B0DPE (0x00000004U) //!< Bit mask for FMC_PFB0CR_B0DPE.
-#define BS_FMC_PFB0CR_B0DPE (1U) //!< Bit field size in bits for FMC_PFB0CR_B0DPE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFB0CR_B0DPE field.
-#define BR_FMC_PFB0CR_B0DPE (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0DPE))
-#endif
-
-//! @brief Format value for bitfield FMC_PFB0CR_B0DPE.
-#define BF_FMC_PFB0CR_B0DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_B0DPE), uint32_t) & BM_FMC_PFB0CR_B0DPE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the B0DPE field to a new value.
-#define BW_FMC_PFB0CR_B0DPE(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0DPE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFB0CR, field B0ICE[3] (RW)
- *
- * This bit controls whether instruction fetches are loaded into the cache.
- *
- * Values:
- * - 0 - Do not cache instruction fetches.
- * - 1 - Cache instruction fetches.
- */
-//@{
-#define BP_FMC_PFB0CR_B0ICE (3U) //!< Bit position for FMC_PFB0CR_B0ICE.
-#define BM_FMC_PFB0CR_B0ICE (0x00000008U) //!< Bit mask for FMC_PFB0CR_B0ICE.
-#define BS_FMC_PFB0CR_B0ICE (1U) //!< Bit field size in bits for FMC_PFB0CR_B0ICE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFB0CR_B0ICE field.
-#define BR_FMC_PFB0CR_B0ICE (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0ICE))
-#endif
-
-//! @brief Format value for bitfield FMC_PFB0CR_B0ICE.
-#define BF_FMC_PFB0CR_B0ICE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_B0ICE), uint32_t) & BM_FMC_PFB0CR_B0ICE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the B0ICE field to a new value.
-#define BW_FMC_PFB0CR_B0ICE(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0ICE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFB0CR, field B0DCE[4] (RW)
- *
- * This bit controls whether data references are loaded into the cache.
- *
- * Values:
- * - 0 - Do not cache data references.
- * - 1 - Cache data references.
- */
-//@{
-#define BP_FMC_PFB0CR_B0DCE (4U) //!< Bit position for FMC_PFB0CR_B0DCE.
-#define BM_FMC_PFB0CR_B0DCE (0x00000010U) //!< Bit mask for FMC_PFB0CR_B0DCE.
-#define BS_FMC_PFB0CR_B0DCE (1U) //!< Bit field size in bits for FMC_PFB0CR_B0DCE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFB0CR_B0DCE field.
-#define BR_FMC_PFB0CR_B0DCE (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0DCE))
-#endif
-
-//! @brief Format value for bitfield FMC_PFB0CR_B0DCE.
-#define BF_FMC_PFB0CR_B0DCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_B0DCE), uint32_t) & BM_FMC_PFB0CR_B0DCE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the B0DCE field to a new value.
-#define BW_FMC_PFB0CR_B0DCE(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0DCE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFB0CR, field CRC[7:5] (RW)
- *
- * This 3-bit field defines the replacement algorithm for accesses that are
- * cached.
- *
- * Values:
- * - 000 - LRU replacement algorithm per set across all four ways
- * - 001 - Reserved
- * - 010 - Independent LRU with ways [0-1] for ifetches, [2-3] for data
- * - 011 - Independent LRU with ways [0-2] for ifetches, [3] for data
- * - 1xx - Reserved
- */
-//@{
-#define BP_FMC_PFB0CR_CRC (5U) //!< Bit position for FMC_PFB0CR_CRC.
-#define BM_FMC_PFB0CR_CRC (0x000000E0U) //!< Bit mask for FMC_PFB0CR_CRC.
-#define BS_FMC_PFB0CR_CRC (3U) //!< Bit field size in bits for FMC_PFB0CR_CRC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFB0CR_CRC field.
-#define BR_FMC_PFB0CR_CRC (HW_FMC_PFB0CR.B.CRC)
-#endif
-
-//! @brief Format value for bitfield FMC_PFB0CR_CRC.
-#define BF_FMC_PFB0CR_CRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_CRC), uint32_t) & BM_FMC_PFB0CR_CRC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CRC field to a new value.
-#define BW_FMC_PFB0CR_CRC(v) (HW_FMC_PFB0CR_WR((HW_FMC_PFB0CR_RD() & ~BM_FMC_PFB0CR_CRC) | BF_FMC_PFB0CR_CRC(v)))
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFB0CR, field B0MW[18:17] (RO)
- *
- * This read-only field defines the width of the bank 0 memory.
- *
- * Values:
- * - 00 - 32 bits
- * - 01 - 64 bits
- * - 10 - 128 bits
- * - 11 - Reserved
- */
-//@{
-#define BP_FMC_PFB0CR_B0MW (17U) //!< Bit position for FMC_PFB0CR_B0MW.
-#define BM_FMC_PFB0CR_B0MW (0x00060000U) //!< Bit mask for FMC_PFB0CR_B0MW.
-#define BS_FMC_PFB0CR_B0MW (2U) //!< Bit field size in bits for FMC_PFB0CR_B0MW.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFB0CR_B0MW field.
-#define BR_FMC_PFB0CR_B0MW (HW_FMC_PFB0CR.B.B0MW)
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFB0CR, field S_B_INV[19] (WORZ)
- *
- * This bit determines if the FMC's prefetch speculation buffer and the single
- * entry page buffer are to be invalidated (cleared). When this bit is written,
- * the speculation buffer and single entry buffer are immediately cleared. This bit
- * always reads as zero.
- *
- * Values:
- * - 0 - Speculation buffer and single entry buffer are not affected.
- * - 1 - Invalidate (clear) speculation buffer and single entry buffer.
- */
-//@{
-#define BP_FMC_PFB0CR_S_B_INV (19U) //!< Bit position for FMC_PFB0CR_S_B_INV.
-#define BM_FMC_PFB0CR_S_B_INV (0x00080000U) //!< Bit mask for FMC_PFB0CR_S_B_INV.
-#define BS_FMC_PFB0CR_S_B_INV (1U) //!< Bit field size in bits for FMC_PFB0CR_S_B_INV.
-
-//! @brief Format value for bitfield FMC_PFB0CR_S_B_INV.
-#define BF_FMC_PFB0CR_S_B_INV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_S_B_INV), uint32_t) & BM_FMC_PFB0CR_S_B_INV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the S_B_INV field to a new value.
-#define BW_FMC_PFB0CR_S_B_INV(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_S_B_INV) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFB0CR, field CINV_WAY[23:20] (WORZ)
- *
- * These bits determine if the given cache way is to be invalidated (cleared).
- * When a bit within this field is written, the corresponding cache way is
- * immediately invalidated: the way's tag, data, and valid contents are cleared. This
- * field always reads as zero. Cache invalidation takes precedence over locking.
- * The cache is invalidated by system reset. System software is required to
- * maintain memory coherency when any segment of the flash memory is programmed or
- * erased. Accordingly, cache invalidations must occur after a programming or erase
- * event is completed and before the new memory image is accessed. The bit setting
- * definitions are for each bit in the field.
- *
- * Values:
- * - 0 - No cache way invalidation for the corresponding cache
- * - 1 - Invalidate cache way for the corresponding cache: clear the tag, data,
- * and vld bits of ways selected
- */
-//@{
-#define BP_FMC_PFB0CR_CINV_WAY (20U) //!< Bit position for FMC_PFB0CR_CINV_WAY.
-#define BM_FMC_PFB0CR_CINV_WAY (0x00F00000U) //!< Bit mask for FMC_PFB0CR_CINV_WAY.
-#define BS_FMC_PFB0CR_CINV_WAY (4U) //!< Bit field size in bits for FMC_PFB0CR_CINV_WAY.
-
-//! @brief Format value for bitfield FMC_PFB0CR_CINV_WAY.
-#define BF_FMC_PFB0CR_CINV_WAY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_CINV_WAY), uint32_t) & BM_FMC_PFB0CR_CINV_WAY)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CINV_WAY field to a new value.
-#define BW_FMC_PFB0CR_CINV_WAY(v) (HW_FMC_PFB0CR_WR((HW_FMC_PFB0CR_RD() & ~BM_FMC_PFB0CR_CINV_WAY) | BF_FMC_PFB0CR_CINV_WAY(v)))
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFB0CR, field CLCK_WAY[27:24] (RW)
- *
- * These bits determine if the given cache way is locked such that its contents
- * will not be displaced by future misses. The bit setting definitions are for
- * each bit in the field.
- *
- * Values:
- * - 0 - Cache way is unlocked and may be displaced
- * - 1 - Cache way is locked and its contents are not displaced
- */
-//@{
-#define BP_FMC_PFB0CR_CLCK_WAY (24U) //!< Bit position for FMC_PFB0CR_CLCK_WAY.
-#define BM_FMC_PFB0CR_CLCK_WAY (0x0F000000U) //!< Bit mask for FMC_PFB0CR_CLCK_WAY.
-#define BS_FMC_PFB0CR_CLCK_WAY (4U) //!< Bit field size in bits for FMC_PFB0CR_CLCK_WAY.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFB0CR_CLCK_WAY field.
-#define BR_FMC_PFB0CR_CLCK_WAY (HW_FMC_PFB0CR.B.CLCK_WAY)
-#endif
-
-//! @brief Format value for bitfield FMC_PFB0CR_CLCK_WAY.
-#define BF_FMC_PFB0CR_CLCK_WAY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_CLCK_WAY), uint32_t) & BM_FMC_PFB0CR_CLCK_WAY)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CLCK_WAY field to a new value.
-#define BW_FMC_PFB0CR_CLCK_WAY(v) (HW_FMC_PFB0CR_WR((HW_FMC_PFB0CR_RD() & ~BM_FMC_PFB0CR_CLCK_WAY) | BF_FMC_PFB0CR_CLCK_WAY(v)))
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFB0CR, field B0RWSC[31:28] (RO)
- *
- * This read-only field defines the number of wait states required to access the
- * bank 0 flash memory. The relationship between the read access time of the
- * flash array (expressed in system clock cycles) and RWSC is defined as: Access
- * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
- * this value based on the ratio of the system clock speed to the flash clock
- * speed. For example, when this ratio is 4:1, the field's value is 3h.
- */
-//@{
-#define BP_FMC_PFB0CR_B0RWSC (28U) //!< Bit position for FMC_PFB0CR_B0RWSC.
-#define BM_FMC_PFB0CR_B0RWSC (0xF0000000U) //!< Bit mask for FMC_PFB0CR_B0RWSC.
-#define BS_FMC_PFB0CR_B0RWSC (4U) //!< Bit field size in bits for FMC_PFB0CR_B0RWSC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFB0CR_B0RWSC field.
-#define BR_FMC_PFB0CR_B0RWSC (HW_FMC_PFB0CR.B.B0RWSC)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FMC_PFB1CR - Flash Bank 1 Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FMC_PFB1CR - Flash Bank 1 Control Register (RW)
- *
- * Reset value: 0x3004001FU
- *
- * This register has a format similar to that for PFB0CR, except it controls the
- * operation of flash bank 1, and the "global" cache control fields are empty.
- */
-typedef union _hw_fmc_pfb1cr
-{
- uint32_t U;
- struct _hw_fmc_pfb1cr_bitfields
- {
- uint32_t B1SEBE : 1; //!< [0] Bank 1 Single Entry Buffer Enable
- uint32_t B1IPE : 1; //!< [1] Bank 1 Instruction Prefetch Enable
- uint32_t B1DPE : 1; //!< [2] Bank 1 Data Prefetch Enable
- uint32_t B1ICE : 1; //!< [3] Bank 1 Instruction Cache Enable
- uint32_t B1DCE : 1; //!< [4] Bank 1 Data Cache Enable
- uint32_t RESERVED0 : 12; //!< [16:5]
- uint32_t B1MW : 2; //!< [18:17] Bank 1 Memory Width
- uint32_t RESERVED1 : 9; //!< [27:19]
- uint32_t B1RWSC : 4; //!< [31:28] Bank 1 Read Wait State Control
- } B;
-} hw_fmc_pfb1cr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FMC_PFB1CR register
- */
-//@{
-#define HW_FMC_PFB1CR_ADDR (REGS_FMC_BASE + 0x8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FMC_PFB1CR (*(__IO hw_fmc_pfb1cr_t *) HW_FMC_PFB1CR_ADDR)
-#define HW_FMC_PFB1CR_RD() (HW_FMC_PFB1CR.U)
-#define HW_FMC_PFB1CR_WR(v) (HW_FMC_PFB1CR.U = (v))
-#define HW_FMC_PFB1CR_SET(v) (HW_FMC_PFB1CR_WR(HW_FMC_PFB1CR_RD() | (v)))
-#define HW_FMC_PFB1CR_CLR(v) (HW_FMC_PFB1CR_WR(HW_FMC_PFB1CR_RD() & ~(v)))
-#define HW_FMC_PFB1CR_TOG(v) (HW_FMC_PFB1CR_WR(HW_FMC_PFB1CR_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FMC_PFB1CR bitfields
- */
-
-/*!
- * @name Register FMC_PFB1CR, field B1SEBE[0] (RW)
- *
- * This bit controls whether the single entry buffer is enabled in response to
- * flash read accesses. Its operation is independent from bank 0's cache. A
- * high-to-low transition of this enable forces the page buffer to be invalidated.
- *
- * Values:
- * - 0 - Single entry buffer is disabled.
- * - 1 - Single entry buffer is enabled.
- */
-//@{
-#define BP_FMC_PFB1CR_B1SEBE (0U) //!< Bit position for FMC_PFB1CR_B1SEBE.
-#define BM_FMC_PFB1CR_B1SEBE (0x00000001U) //!< Bit mask for FMC_PFB1CR_B1SEBE.
-#define BS_FMC_PFB1CR_B1SEBE (1U) //!< Bit field size in bits for FMC_PFB1CR_B1SEBE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFB1CR_B1SEBE field.
-#define BR_FMC_PFB1CR_B1SEBE (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1SEBE))
-#endif
-
-//! @brief Format value for bitfield FMC_PFB1CR_B1SEBE.
-#define BF_FMC_PFB1CR_B1SEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB1CR_B1SEBE), uint32_t) & BM_FMC_PFB1CR_B1SEBE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the B1SEBE field to a new value.
-#define BW_FMC_PFB1CR_B1SEBE(v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1SEBE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFB1CR, field B1IPE[1] (RW)
- *
- * This bit controls whether prefetches (or speculative accesses) are initiated
- * in response to instruction fetches.
- *
- * Values:
- * - 0 - Do not prefetch in response to instruction fetches.
- * - 1 - Enable prefetches in response to instruction fetches.
- */
-//@{
-#define BP_FMC_PFB1CR_B1IPE (1U) //!< Bit position for FMC_PFB1CR_B1IPE.
-#define BM_FMC_PFB1CR_B1IPE (0x00000002U) //!< Bit mask for FMC_PFB1CR_B1IPE.
-#define BS_FMC_PFB1CR_B1IPE (1U) //!< Bit field size in bits for FMC_PFB1CR_B1IPE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFB1CR_B1IPE field.
-#define BR_FMC_PFB1CR_B1IPE (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1IPE))
-#endif
-
-//! @brief Format value for bitfield FMC_PFB1CR_B1IPE.
-#define BF_FMC_PFB1CR_B1IPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB1CR_B1IPE), uint32_t) & BM_FMC_PFB1CR_B1IPE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the B1IPE field to a new value.
-#define BW_FMC_PFB1CR_B1IPE(v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1IPE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFB1CR, field B1DPE[2] (RW)
- *
- * This bit controls whether prefetches (or speculative accesses) are initiated
- * in response to data references.
- *
- * Values:
- * - 0 - Do not prefetch in response to data references.
- * - 1 - Enable prefetches in response to data references.
- */
-//@{
-#define BP_FMC_PFB1CR_B1DPE (2U) //!< Bit position for FMC_PFB1CR_B1DPE.
-#define BM_FMC_PFB1CR_B1DPE (0x00000004U) //!< Bit mask for FMC_PFB1CR_B1DPE.
-#define BS_FMC_PFB1CR_B1DPE (1U) //!< Bit field size in bits for FMC_PFB1CR_B1DPE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFB1CR_B1DPE field.
-#define BR_FMC_PFB1CR_B1DPE (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1DPE))
-#endif
-
-//! @brief Format value for bitfield FMC_PFB1CR_B1DPE.
-#define BF_FMC_PFB1CR_B1DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB1CR_B1DPE), uint32_t) & BM_FMC_PFB1CR_B1DPE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the B1DPE field to a new value.
-#define BW_FMC_PFB1CR_B1DPE(v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1DPE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFB1CR, field B1ICE[3] (RW)
- *
- * This bit controls whether instruction fetches are loaded into the cache.
- *
- * Values:
- * - 0 - Do not cache instruction fetches.
- * - 1 - Cache instruction fetches.
- */
-//@{
-#define BP_FMC_PFB1CR_B1ICE (3U) //!< Bit position for FMC_PFB1CR_B1ICE.
-#define BM_FMC_PFB1CR_B1ICE (0x00000008U) //!< Bit mask for FMC_PFB1CR_B1ICE.
-#define BS_FMC_PFB1CR_B1ICE (1U) //!< Bit field size in bits for FMC_PFB1CR_B1ICE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFB1CR_B1ICE field.
-#define BR_FMC_PFB1CR_B1ICE (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1ICE))
-#endif
-
-//! @brief Format value for bitfield FMC_PFB1CR_B1ICE.
-#define BF_FMC_PFB1CR_B1ICE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB1CR_B1ICE), uint32_t) & BM_FMC_PFB1CR_B1ICE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the B1ICE field to a new value.
-#define BW_FMC_PFB1CR_B1ICE(v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1ICE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFB1CR, field B1DCE[4] (RW)
- *
- * This bit controls whether data references are loaded into the cache.
- *
- * Values:
- * - 0 - Do not cache data references.
- * - 1 - Cache data references.
- */
-//@{
-#define BP_FMC_PFB1CR_B1DCE (4U) //!< Bit position for FMC_PFB1CR_B1DCE.
-#define BM_FMC_PFB1CR_B1DCE (0x00000010U) //!< Bit mask for FMC_PFB1CR_B1DCE.
-#define BS_FMC_PFB1CR_B1DCE (1U) //!< Bit field size in bits for FMC_PFB1CR_B1DCE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFB1CR_B1DCE field.
-#define BR_FMC_PFB1CR_B1DCE (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1DCE))
-#endif
-
-//! @brief Format value for bitfield FMC_PFB1CR_B1DCE.
-#define BF_FMC_PFB1CR_B1DCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB1CR_B1DCE), uint32_t) & BM_FMC_PFB1CR_B1DCE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the B1DCE field to a new value.
-#define BW_FMC_PFB1CR_B1DCE(v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1DCE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFB1CR, field B1MW[18:17] (RO)
- *
- * This read-only field defines the width of the bank 1 memory.
- *
- * Values:
- * - 00 - 32 bits
- * - 01 - 64 bits
- * - 10 - 128 bits
- * - 11 - Reserved
- */
-//@{
-#define BP_FMC_PFB1CR_B1MW (17U) //!< Bit position for FMC_PFB1CR_B1MW.
-#define BM_FMC_PFB1CR_B1MW (0x00060000U) //!< Bit mask for FMC_PFB1CR_B1MW.
-#define BS_FMC_PFB1CR_B1MW (2U) //!< Bit field size in bits for FMC_PFB1CR_B1MW.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFB1CR_B1MW field.
-#define BR_FMC_PFB1CR_B1MW (HW_FMC_PFB1CR.B.B1MW)
-#endif
-//@}
-
-/*!
- * @name Register FMC_PFB1CR, field B1RWSC[31:28] (RO)
- *
- * This read-only field defines the number of wait states required to access the
- * bank 1 flash memory. The relationship between the read access time of the
- * flash array (expressed in system clock cycles) and RWSC is defined as: Access
- * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
- * this value based on the ratio of the system clock speed to the flash clock
- * speed. For example, when this ratio is 4:1, the field's value is 3h.
- */
-//@{
-#define BP_FMC_PFB1CR_B1RWSC (28U) //!< Bit position for FMC_PFB1CR_B1RWSC.
-#define BM_FMC_PFB1CR_B1RWSC (0xF0000000U) //!< Bit mask for FMC_PFB1CR_B1RWSC.
-#define BS_FMC_PFB1CR_B1RWSC (4U) //!< Bit field size in bits for FMC_PFB1CR_B1RWSC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_PFB1CR_B1RWSC field.
-#define BR_FMC_PFB1CR_B1RWSC (HW_FMC_PFB1CR.B.B1RWSC)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FMC_TAGVDW0Sn - Cache Tag Storage
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FMC_TAGVDW0Sn - Cache Tag Storage (RW)
- *
- * Reset value: 0x00000000U
- *
- * The cache is a 4-way, set-associative cache with 4 sets. The ways are
- * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
- * denotes the set. This section represents tag/vld information for all sets in the
- * indicated way.
- */
-typedef union _hw_fmc_tagvdw0sn
-{
- uint32_t U;
- struct _hw_fmc_tagvdw0sn_bitfields
- {
- uint32_t valid : 1; //!< [0] 1-bit valid for cache entry
- uint32_t RESERVED0 : 4; //!< [4:1]
- uint32_t tag : 14; //!< [18:5] 14-bit tag for cache entry
- uint32_t RESERVED1 : 13; //!< [31:19]
- } B;
-} hw_fmc_tagvdw0sn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FMC_TAGVDW0Sn register
- */
-//@{
-#define HW_FMC_TAGVDW0Sn_COUNT (4U)
-
-#define HW_FMC_TAGVDW0Sn_ADDR(n) (REGS_FMC_BASE + 0x100U + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FMC_TAGVDW0Sn(n) (*(__IO hw_fmc_tagvdw0sn_t *) HW_FMC_TAGVDW0Sn_ADDR(n))
-#define HW_FMC_TAGVDW0Sn_RD(n) (HW_FMC_TAGVDW0Sn(n).U)
-#define HW_FMC_TAGVDW0Sn_WR(n, v) (HW_FMC_TAGVDW0Sn(n).U = (v))
-#define HW_FMC_TAGVDW0Sn_SET(n, v) (HW_FMC_TAGVDW0Sn_WR(n, HW_FMC_TAGVDW0Sn_RD(n) | (v)))
-#define HW_FMC_TAGVDW0Sn_CLR(n, v) (HW_FMC_TAGVDW0Sn_WR(n, HW_FMC_TAGVDW0Sn_RD(n) & ~(v)))
-#define HW_FMC_TAGVDW0Sn_TOG(n, v) (HW_FMC_TAGVDW0Sn_WR(n, HW_FMC_TAGVDW0Sn_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FMC_TAGVDW0Sn bitfields
- */
-
-/*!
- * @name Register FMC_TAGVDW0Sn, field valid[0] (RW)
- */
-//@{
-#define BP_FMC_TAGVDW0Sn_valid (0U) //!< Bit position for FMC_TAGVDW0Sn_valid.
-#define BM_FMC_TAGVDW0Sn_valid (0x00000001U) //!< Bit mask for FMC_TAGVDW0Sn_valid.
-#define BS_FMC_TAGVDW0Sn_valid (1U) //!< Bit field size in bits for FMC_TAGVDW0Sn_valid.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_TAGVDW0Sn_valid field.
-#define BR_FMC_TAGVDW0Sn_valid(n) (BITBAND_ACCESS32(HW_FMC_TAGVDW0Sn_ADDR(n), BP_FMC_TAGVDW0Sn_valid))
-#endif
-
-//! @brief Format value for bitfield FMC_TAGVDW0Sn_valid.
-#define BF_FMC_TAGVDW0Sn_valid(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW0Sn_valid), uint32_t) & BM_FMC_TAGVDW0Sn_valid)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the valid field to a new value.
-#define BW_FMC_TAGVDW0Sn_valid(n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW0Sn_ADDR(n), BP_FMC_TAGVDW0Sn_valid) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FMC_TAGVDW0Sn, field tag[18:5] (RW)
- */
-//@{
-#define BP_FMC_TAGVDW0Sn_tag (5U) //!< Bit position for FMC_TAGVDW0Sn_tag.
-#define BM_FMC_TAGVDW0Sn_tag (0x0007FFE0U) //!< Bit mask for FMC_TAGVDW0Sn_tag.
-#define BS_FMC_TAGVDW0Sn_tag (14U) //!< Bit field size in bits for FMC_TAGVDW0Sn_tag.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_TAGVDW0Sn_tag field.
-#define BR_FMC_TAGVDW0Sn_tag(n) (HW_FMC_TAGVDW0Sn(n).B.tag)
-#endif
-
-//! @brief Format value for bitfield FMC_TAGVDW0Sn_tag.
-#define BF_FMC_TAGVDW0Sn_tag(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW0Sn_tag), uint32_t) & BM_FMC_TAGVDW0Sn_tag)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the tag field to a new value.
-#define BW_FMC_TAGVDW0Sn_tag(n, v) (HW_FMC_TAGVDW0Sn_WR(n, (HW_FMC_TAGVDW0Sn_RD(n) & ~BM_FMC_TAGVDW0Sn_tag) | BF_FMC_TAGVDW0Sn_tag(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FMC_TAGVDW1Sn - Cache Tag Storage
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FMC_TAGVDW1Sn - Cache Tag Storage (RW)
- *
- * Reset value: 0x00000000U
- *
- * The cache is a 4-way, set-associative cache with 4 sets. The ways are
- * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
- * denotes the set. This section represents tag/vld information for all sets in the
- * indicated way.
- */
-typedef union _hw_fmc_tagvdw1sn
-{
- uint32_t U;
- struct _hw_fmc_tagvdw1sn_bitfields
- {
- uint32_t valid : 1; //!< [0] 1-bit valid for cache entry
- uint32_t RESERVED0 : 4; //!< [4:1]
- uint32_t tag : 14; //!< [18:5] 14-bit tag for cache entry
- uint32_t RESERVED1 : 13; //!< [31:19]
- } B;
-} hw_fmc_tagvdw1sn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FMC_TAGVDW1Sn register
- */
-//@{
-#define HW_FMC_TAGVDW1Sn_COUNT (4U)
-
-#define HW_FMC_TAGVDW1Sn_ADDR(n) (REGS_FMC_BASE + 0x110U + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FMC_TAGVDW1Sn(n) (*(__IO hw_fmc_tagvdw1sn_t *) HW_FMC_TAGVDW1Sn_ADDR(n))
-#define HW_FMC_TAGVDW1Sn_RD(n) (HW_FMC_TAGVDW1Sn(n).U)
-#define HW_FMC_TAGVDW1Sn_WR(n, v) (HW_FMC_TAGVDW1Sn(n).U = (v))
-#define HW_FMC_TAGVDW1Sn_SET(n, v) (HW_FMC_TAGVDW1Sn_WR(n, HW_FMC_TAGVDW1Sn_RD(n) | (v)))
-#define HW_FMC_TAGVDW1Sn_CLR(n, v) (HW_FMC_TAGVDW1Sn_WR(n, HW_FMC_TAGVDW1Sn_RD(n) & ~(v)))
-#define HW_FMC_TAGVDW1Sn_TOG(n, v) (HW_FMC_TAGVDW1Sn_WR(n, HW_FMC_TAGVDW1Sn_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FMC_TAGVDW1Sn bitfields
- */
-
-/*!
- * @name Register FMC_TAGVDW1Sn, field valid[0] (RW)
- */
-//@{
-#define BP_FMC_TAGVDW1Sn_valid (0U) //!< Bit position for FMC_TAGVDW1Sn_valid.
-#define BM_FMC_TAGVDW1Sn_valid (0x00000001U) //!< Bit mask for FMC_TAGVDW1Sn_valid.
-#define BS_FMC_TAGVDW1Sn_valid (1U) //!< Bit field size in bits for FMC_TAGVDW1Sn_valid.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_TAGVDW1Sn_valid field.
-#define BR_FMC_TAGVDW1Sn_valid(n) (BITBAND_ACCESS32(HW_FMC_TAGVDW1Sn_ADDR(n), BP_FMC_TAGVDW1Sn_valid))
-#endif
-
-//! @brief Format value for bitfield FMC_TAGVDW1Sn_valid.
-#define BF_FMC_TAGVDW1Sn_valid(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW1Sn_valid), uint32_t) & BM_FMC_TAGVDW1Sn_valid)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the valid field to a new value.
-#define BW_FMC_TAGVDW1Sn_valid(n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW1Sn_ADDR(n), BP_FMC_TAGVDW1Sn_valid) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FMC_TAGVDW1Sn, field tag[18:5] (RW)
- */
-//@{
-#define BP_FMC_TAGVDW1Sn_tag (5U) //!< Bit position for FMC_TAGVDW1Sn_tag.
-#define BM_FMC_TAGVDW1Sn_tag (0x0007FFE0U) //!< Bit mask for FMC_TAGVDW1Sn_tag.
-#define BS_FMC_TAGVDW1Sn_tag (14U) //!< Bit field size in bits for FMC_TAGVDW1Sn_tag.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_TAGVDW1Sn_tag field.
-#define BR_FMC_TAGVDW1Sn_tag(n) (HW_FMC_TAGVDW1Sn(n).B.tag)
-#endif
-
-//! @brief Format value for bitfield FMC_TAGVDW1Sn_tag.
-#define BF_FMC_TAGVDW1Sn_tag(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW1Sn_tag), uint32_t) & BM_FMC_TAGVDW1Sn_tag)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the tag field to a new value.
-#define BW_FMC_TAGVDW1Sn_tag(n, v) (HW_FMC_TAGVDW1Sn_WR(n, (HW_FMC_TAGVDW1Sn_RD(n) & ~BM_FMC_TAGVDW1Sn_tag) | BF_FMC_TAGVDW1Sn_tag(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FMC_TAGVDW2Sn - Cache Tag Storage
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FMC_TAGVDW2Sn - Cache Tag Storage (RW)
- *
- * Reset value: 0x00000000U
- *
- * The cache is a 4-way, set-associative cache with 4 sets. The ways are
- * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
- * denotes the set. This section represents tag/vld information for all sets in the
- * indicated way.
- */
-typedef union _hw_fmc_tagvdw2sn
-{
- uint32_t U;
- struct _hw_fmc_tagvdw2sn_bitfields
- {
- uint32_t valid : 1; //!< [0] 1-bit valid for cache entry
- uint32_t RESERVED0 : 4; //!< [4:1]
- uint32_t tag : 14; //!< [18:5] 14-bit tag for cache entry
- uint32_t RESERVED1 : 13; //!< [31:19]
- } B;
-} hw_fmc_tagvdw2sn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FMC_TAGVDW2Sn register
- */
-//@{
-#define HW_FMC_TAGVDW2Sn_COUNT (4U)
-
-#define HW_FMC_TAGVDW2Sn_ADDR(n) (REGS_FMC_BASE + 0x120U + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FMC_TAGVDW2Sn(n) (*(__IO hw_fmc_tagvdw2sn_t *) HW_FMC_TAGVDW2Sn_ADDR(n))
-#define HW_FMC_TAGVDW2Sn_RD(n) (HW_FMC_TAGVDW2Sn(n).U)
-#define HW_FMC_TAGVDW2Sn_WR(n, v) (HW_FMC_TAGVDW2Sn(n).U = (v))
-#define HW_FMC_TAGVDW2Sn_SET(n, v) (HW_FMC_TAGVDW2Sn_WR(n, HW_FMC_TAGVDW2Sn_RD(n) | (v)))
-#define HW_FMC_TAGVDW2Sn_CLR(n, v) (HW_FMC_TAGVDW2Sn_WR(n, HW_FMC_TAGVDW2Sn_RD(n) & ~(v)))
-#define HW_FMC_TAGVDW2Sn_TOG(n, v) (HW_FMC_TAGVDW2Sn_WR(n, HW_FMC_TAGVDW2Sn_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FMC_TAGVDW2Sn bitfields
- */
-
-/*!
- * @name Register FMC_TAGVDW2Sn, field valid[0] (RW)
- */
-//@{
-#define BP_FMC_TAGVDW2Sn_valid (0U) //!< Bit position for FMC_TAGVDW2Sn_valid.
-#define BM_FMC_TAGVDW2Sn_valid (0x00000001U) //!< Bit mask for FMC_TAGVDW2Sn_valid.
-#define BS_FMC_TAGVDW2Sn_valid (1U) //!< Bit field size in bits for FMC_TAGVDW2Sn_valid.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_TAGVDW2Sn_valid field.
-#define BR_FMC_TAGVDW2Sn_valid(n) (BITBAND_ACCESS32(HW_FMC_TAGVDW2Sn_ADDR(n), BP_FMC_TAGVDW2Sn_valid))
-#endif
-
-//! @brief Format value for bitfield FMC_TAGVDW2Sn_valid.
-#define BF_FMC_TAGVDW2Sn_valid(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW2Sn_valid), uint32_t) & BM_FMC_TAGVDW2Sn_valid)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the valid field to a new value.
-#define BW_FMC_TAGVDW2Sn_valid(n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW2Sn_ADDR(n), BP_FMC_TAGVDW2Sn_valid) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FMC_TAGVDW2Sn, field tag[18:5] (RW)
- */
-//@{
-#define BP_FMC_TAGVDW2Sn_tag (5U) //!< Bit position for FMC_TAGVDW2Sn_tag.
-#define BM_FMC_TAGVDW2Sn_tag (0x0007FFE0U) //!< Bit mask for FMC_TAGVDW2Sn_tag.
-#define BS_FMC_TAGVDW2Sn_tag (14U) //!< Bit field size in bits for FMC_TAGVDW2Sn_tag.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_TAGVDW2Sn_tag field.
-#define BR_FMC_TAGVDW2Sn_tag(n) (HW_FMC_TAGVDW2Sn(n).B.tag)
-#endif
-
-//! @brief Format value for bitfield FMC_TAGVDW2Sn_tag.
-#define BF_FMC_TAGVDW2Sn_tag(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW2Sn_tag), uint32_t) & BM_FMC_TAGVDW2Sn_tag)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the tag field to a new value.
-#define BW_FMC_TAGVDW2Sn_tag(n, v) (HW_FMC_TAGVDW2Sn_WR(n, (HW_FMC_TAGVDW2Sn_RD(n) & ~BM_FMC_TAGVDW2Sn_tag) | BF_FMC_TAGVDW2Sn_tag(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FMC_TAGVDW3Sn - Cache Tag Storage
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FMC_TAGVDW3Sn - Cache Tag Storage (RW)
- *
- * Reset value: 0x00000000U
- *
- * The cache is a 4-way, set-associative cache with 4 sets. The ways are
- * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
- * denotes the set. This section represents tag/vld information for all sets in the
- * indicated way.
- */
-typedef union _hw_fmc_tagvdw3sn
-{
- uint32_t U;
- struct _hw_fmc_tagvdw3sn_bitfields
- {
- uint32_t valid : 1; //!< [0] 1-bit valid for cache entry
- uint32_t RESERVED0 : 4; //!< [4:1]
- uint32_t tag : 14; //!< [18:5] 14-bit tag for cache entry
- uint32_t RESERVED1 : 13; //!< [31:19]
- } B;
-} hw_fmc_tagvdw3sn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FMC_TAGVDW3Sn register
- */
-//@{
-#define HW_FMC_TAGVDW3Sn_COUNT (4U)
-
-#define HW_FMC_TAGVDW3Sn_ADDR(n) (REGS_FMC_BASE + 0x130U + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FMC_TAGVDW3Sn(n) (*(__IO hw_fmc_tagvdw3sn_t *) HW_FMC_TAGVDW3Sn_ADDR(n))
-#define HW_FMC_TAGVDW3Sn_RD(n) (HW_FMC_TAGVDW3Sn(n).U)
-#define HW_FMC_TAGVDW3Sn_WR(n, v) (HW_FMC_TAGVDW3Sn(n).U = (v))
-#define HW_FMC_TAGVDW3Sn_SET(n, v) (HW_FMC_TAGVDW3Sn_WR(n, HW_FMC_TAGVDW3Sn_RD(n) | (v)))
-#define HW_FMC_TAGVDW3Sn_CLR(n, v) (HW_FMC_TAGVDW3Sn_WR(n, HW_FMC_TAGVDW3Sn_RD(n) & ~(v)))
-#define HW_FMC_TAGVDW3Sn_TOG(n, v) (HW_FMC_TAGVDW3Sn_WR(n, HW_FMC_TAGVDW3Sn_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FMC_TAGVDW3Sn bitfields
- */
-
-/*!
- * @name Register FMC_TAGVDW3Sn, field valid[0] (RW)
- */
-//@{
-#define BP_FMC_TAGVDW3Sn_valid (0U) //!< Bit position for FMC_TAGVDW3Sn_valid.
-#define BM_FMC_TAGVDW3Sn_valid (0x00000001U) //!< Bit mask for FMC_TAGVDW3Sn_valid.
-#define BS_FMC_TAGVDW3Sn_valid (1U) //!< Bit field size in bits for FMC_TAGVDW3Sn_valid.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_TAGVDW3Sn_valid field.
-#define BR_FMC_TAGVDW3Sn_valid(n) (BITBAND_ACCESS32(HW_FMC_TAGVDW3Sn_ADDR(n), BP_FMC_TAGVDW3Sn_valid))
-#endif
-
-//! @brief Format value for bitfield FMC_TAGVDW3Sn_valid.
-#define BF_FMC_TAGVDW3Sn_valid(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW3Sn_valid), uint32_t) & BM_FMC_TAGVDW3Sn_valid)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the valid field to a new value.
-#define BW_FMC_TAGVDW3Sn_valid(n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW3Sn_ADDR(n), BP_FMC_TAGVDW3Sn_valid) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FMC_TAGVDW3Sn, field tag[18:5] (RW)
- */
-//@{
-#define BP_FMC_TAGVDW3Sn_tag (5U) //!< Bit position for FMC_TAGVDW3Sn_tag.
-#define BM_FMC_TAGVDW3Sn_tag (0x0007FFE0U) //!< Bit mask for FMC_TAGVDW3Sn_tag.
-#define BS_FMC_TAGVDW3Sn_tag (14U) //!< Bit field size in bits for FMC_TAGVDW3Sn_tag.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_TAGVDW3Sn_tag field.
-#define BR_FMC_TAGVDW3Sn_tag(n) (HW_FMC_TAGVDW3Sn(n).B.tag)
-#endif
-
-//! @brief Format value for bitfield FMC_TAGVDW3Sn_tag.
-#define BF_FMC_TAGVDW3Sn_tag(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW3Sn_tag), uint32_t) & BM_FMC_TAGVDW3Sn_tag)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the tag field to a new value.
-#define BW_FMC_TAGVDW3Sn_tag(n, v) (HW_FMC_TAGVDW3Sn_WR(n, (HW_FMC_TAGVDW3Sn_RD(n) & ~BM_FMC_TAGVDW3Sn_tag) | BF_FMC_TAGVDW3Sn_tag(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FMC_DATAW0SnU - Cache Data Storage (upper word)
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FMC_DATAW0SnU - Cache Data Storage (upper word) (RW)
- *
- * Reset value: 0x00000000U
- *
- * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
- * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
- * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
- * lower word, respectively. This section represents data for the upper word (bits
- * [63:32]) of all sets in the indicated way.
- */
-typedef union _hw_fmc_dataw0snu
-{
- uint32_t U;
- struct _hw_fmc_dataw0snu_bitfields
- {
- uint32_t data : 32; //!< [31:0] Bits [63:32] of data entry
- } B;
-} hw_fmc_dataw0snu_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FMC_DATAW0SnU register
- */
-//@{
-#define HW_FMC_DATAW0SnU_COUNT (4U)
-
-#define HW_FMC_DATAW0SnU_ADDR(n) (REGS_FMC_BASE + 0x200U + (0x8U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FMC_DATAW0SnU(n) (*(__IO hw_fmc_dataw0snu_t *) HW_FMC_DATAW0SnU_ADDR(n))
-#define HW_FMC_DATAW0SnU_RD(n) (HW_FMC_DATAW0SnU(n).U)
-#define HW_FMC_DATAW0SnU_WR(n, v) (HW_FMC_DATAW0SnU(n).U = (v))
-#define HW_FMC_DATAW0SnU_SET(n, v) (HW_FMC_DATAW0SnU_WR(n, HW_FMC_DATAW0SnU_RD(n) | (v)))
-#define HW_FMC_DATAW0SnU_CLR(n, v) (HW_FMC_DATAW0SnU_WR(n, HW_FMC_DATAW0SnU_RD(n) & ~(v)))
-#define HW_FMC_DATAW0SnU_TOG(n, v) (HW_FMC_DATAW0SnU_WR(n, HW_FMC_DATAW0SnU_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FMC_DATAW0SnU bitfields
- */
-
-/*!
- * @name Register FMC_DATAW0SnU, field data[31:0] (RW)
- */
-//@{
-#define BP_FMC_DATAW0SnU_data (0U) //!< Bit position for FMC_DATAW0SnU_data.
-#define BM_FMC_DATAW0SnU_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW0SnU_data.
-#define BS_FMC_DATAW0SnU_data (32U) //!< Bit field size in bits for FMC_DATAW0SnU_data.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_DATAW0SnU_data field.
-#define BR_FMC_DATAW0SnU_data(n) (HW_FMC_DATAW0SnU(n).U)
-#endif
-
-//! @brief Format value for bitfield FMC_DATAW0SnU_data.
-#define BF_FMC_DATAW0SnU_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW0SnU_data), uint32_t) & BM_FMC_DATAW0SnU_data)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the data field to a new value.
-#define BW_FMC_DATAW0SnU_data(n, v) (HW_FMC_DATAW0SnU_WR(n, v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_FMC_DATAW0SnL - Cache Data Storage (lower word)
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FMC_DATAW0SnL - Cache Data Storage (lower word) (RW)
- *
- * Reset value: 0x00000000U
- *
- * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
- * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
- * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
- * lower word, respectively. This section represents data for the lower word (bits
- * [31:0]) of all sets in the indicated way.
- */
-typedef union _hw_fmc_dataw0snl
-{
- uint32_t U;
- struct _hw_fmc_dataw0snl_bitfields
- {
- uint32_t data : 32; //!< [31:0] Bits [31:0] of data entry
- } B;
-} hw_fmc_dataw0snl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FMC_DATAW0SnL register
- */
-//@{
-#define HW_FMC_DATAW0SnL_COUNT (4U)
-
-#define HW_FMC_DATAW0SnL_ADDR(n) (REGS_FMC_BASE + 0x204U + (0x8U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FMC_DATAW0SnL(n) (*(__IO hw_fmc_dataw0snl_t *) HW_FMC_DATAW0SnL_ADDR(n))
-#define HW_FMC_DATAW0SnL_RD(n) (HW_FMC_DATAW0SnL(n).U)
-#define HW_FMC_DATAW0SnL_WR(n, v) (HW_FMC_DATAW0SnL(n).U = (v))
-#define HW_FMC_DATAW0SnL_SET(n, v) (HW_FMC_DATAW0SnL_WR(n, HW_FMC_DATAW0SnL_RD(n) | (v)))
-#define HW_FMC_DATAW0SnL_CLR(n, v) (HW_FMC_DATAW0SnL_WR(n, HW_FMC_DATAW0SnL_RD(n) & ~(v)))
-#define HW_FMC_DATAW0SnL_TOG(n, v) (HW_FMC_DATAW0SnL_WR(n, HW_FMC_DATAW0SnL_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FMC_DATAW0SnL bitfields
- */
-
-/*!
- * @name Register FMC_DATAW0SnL, field data[31:0] (RW)
- */
-//@{
-#define BP_FMC_DATAW0SnL_data (0U) //!< Bit position for FMC_DATAW0SnL_data.
-#define BM_FMC_DATAW0SnL_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW0SnL_data.
-#define BS_FMC_DATAW0SnL_data (32U) //!< Bit field size in bits for FMC_DATAW0SnL_data.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_DATAW0SnL_data field.
-#define BR_FMC_DATAW0SnL_data(n) (HW_FMC_DATAW0SnL(n).U)
-#endif
-
-//! @brief Format value for bitfield FMC_DATAW0SnL_data.
-#define BF_FMC_DATAW0SnL_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW0SnL_data), uint32_t) & BM_FMC_DATAW0SnL_data)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the data field to a new value.
-#define BW_FMC_DATAW0SnL_data(n, v) (HW_FMC_DATAW0SnL_WR(n, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FMC_DATAW1SnU - Cache Data Storage (upper word)
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FMC_DATAW1SnU - Cache Data Storage (upper word) (RW)
- *
- * Reset value: 0x00000000U
- *
- * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
- * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
- * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
- * lower word, respectively. This section represents data for the upper word (bits
- * [63:32]) of all sets in the indicated way.
- */
-typedef union _hw_fmc_dataw1snu
-{
- uint32_t U;
- struct _hw_fmc_dataw1snu_bitfields
- {
- uint32_t data : 32; //!< [31:0] Bits [63:32] of data entry
- } B;
-} hw_fmc_dataw1snu_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FMC_DATAW1SnU register
- */
-//@{
-#define HW_FMC_DATAW1SnU_COUNT (4U)
-
-#define HW_FMC_DATAW1SnU_ADDR(n) (REGS_FMC_BASE + 0x220U + (0x8U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FMC_DATAW1SnU(n) (*(__IO hw_fmc_dataw1snu_t *) HW_FMC_DATAW1SnU_ADDR(n))
-#define HW_FMC_DATAW1SnU_RD(n) (HW_FMC_DATAW1SnU(n).U)
-#define HW_FMC_DATAW1SnU_WR(n, v) (HW_FMC_DATAW1SnU(n).U = (v))
-#define HW_FMC_DATAW1SnU_SET(n, v) (HW_FMC_DATAW1SnU_WR(n, HW_FMC_DATAW1SnU_RD(n) | (v)))
-#define HW_FMC_DATAW1SnU_CLR(n, v) (HW_FMC_DATAW1SnU_WR(n, HW_FMC_DATAW1SnU_RD(n) & ~(v)))
-#define HW_FMC_DATAW1SnU_TOG(n, v) (HW_FMC_DATAW1SnU_WR(n, HW_FMC_DATAW1SnU_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FMC_DATAW1SnU bitfields
- */
-
-/*!
- * @name Register FMC_DATAW1SnU, field data[31:0] (RW)
- */
-//@{
-#define BP_FMC_DATAW1SnU_data (0U) //!< Bit position for FMC_DATAW1SnU_data.
-#define BM_FMC_DATAW1SnU_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW1SnU_data.
-#define BS_FMC_DATAW1SnU_data (32U) //!< Bit field size in bits for FMC_DATAW1SnU_data.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_DATAW1SnU_data field.
-#define BR_FMC_DATAW1SnU_data(n) (HW_FMC_DATAW1SnU(n).U)
-#endif
-
-//! @brief Format value for bitfield FMC_DATAW1SnU_data.
-#define BF_FMC_DATAW1SnU_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW1SnU_data), uint32_t) & BM_FMC_DATAW1SnU_data)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the data field to a new value.
-#define BW_FMC_DATAW1SnU_data(n, v) (HW_FMC_DATAW1SnU_WR(n, v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_FMC_DATAW1SnL - Cache Data Storage (lower word)
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FMC_DATAW1SnL - Cache Data Storage (lower word) (RW)
- *
- * Reset value: 0x00000000U
- *
- * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
- * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
- * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
- * lower word, respectively. This section represents data for the lower word (bits
- * [31:0]) of all sets in the indicated way.
- */
-typedef union _hw_fmc_dataw1snl
-{
- uint32_t U;
- struct _hw_fmc_dataw1snl_bitfields
- {
- uint32_t data : 32; //!< [31:0] Bits [31:0] of data entry
- } B;
-} hw_fmc_dataw1snl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FMC_DATAW1SnL register
- */
-//@{
-#define HW_FMC_DATAW1SnL_COUNT (4U)
-
-#define HW_FMC_DATAW1SnL_ADDR(n) (REGS_FMC_BASE + 0x224U + (0x8U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FMC_DATAW1SnL(n) (*(__IO hw_fmc_dataw1snl_t *) HW_FMC_DATAW1SnL_ADDR(n))
-#define HW_FMC_DATAW1SnL_RD(n) (HW_FMC_DATAW1SnL(n).U)
-#define HW_FMC_DATAW1SnL_WR(n, v) (HW_FMC_DATAW1SnL(n).U = (v))
-#define HW_FMC_DATAW1SnL_SET(n, v) (HW_FMC_DATAW1SnL_WR(n, HW_FMC_DATAW1SnL_RD(n) | (v)))
-#define HW_FMC_DATAW1SnL_CLR(n, v) (HW_FMC_DATAW1SnL_WR(n, HW_FMC_DATAW1SnL_RD(n) & ~(v)))
-#define HW_FMC_DATAW1SnL_TOG(n, v) (HW_FMC_DATAW1SnL_WR(n, HW_FMC_DATAW1SnL_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FMC_DATAW1SnL bitfields
- */
-
-/*!
- * @name Register FMC_DATAW1SnL, field data[31:0] (RW)
- */
-//@{
-#define BP_FMC_DATAW1SnL_data (0U) //!< Bit position for FMC_DATAW1SnL_data.
-#define BM_FMC_DATAW1SnL_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW1SnL_data.
-#define BS_FMC_DATAW1SnL_data (32U) //!< Bit field size in bits for FMC_DATAW1SnL_data.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_DATAW1SnL_data field.
-#define BR_FMC_DATAW1SnL_data(n) (HW_FMC_DATAW1SnL(n).U)
-#endif
-
-//! @brief Format value for bitfield FMC_DATAW1SnL_data.
-#define BF_FMC_DATAW1SnL_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW1SnL_data), uint32_t) & BM_FMC_DATAW1SnL_data)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the data field to a new value.
-#define BW_FMC_DATAW1SnL_data(n, v) (HW_FMC_DATAW1SnL_WR(n, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FMC_DATAW2SnU - Cache Data Storage (upper word)
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FMC_DATAW2SnU - Cache Data Storage (upper word) (RW)
- *
- * Reset value: 0x00000000U
- *
- * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
- * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
- * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
- * lower word, respectively. This section represents data for the upper word (bits
- * [63:32]) of all sets in the indicated way.
- */
-typedef union _hw_fmc_dataw2snu
-{
- uint32_t U;
- struct _hw_fmc_dataw2snu_bitfields
- {
- uint32_t data : 32; //!< [31:0] Bits [63:32] of data entry
- } B;
-} hw_fmc_dataw2snu_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FMC_DATAW2SnU register
- */
-//@{
-#define HW_FMC_DATAW2SnU_COUNT (4U)
-
-#define HW_FMC_DATAW2SnU_ADDR(n) (REGS_FMC_BASE + 0x240U + (0x8U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FMC_DATAW2SnU(n) (*(__IO hw_fmc_dataw2snu_t *) HW_FMC_DATAW2SnU_ADDR(n))
-#define HW_FMC_DATAW2SnU_RD(n) (HW_FMC_DATAW2SnU(n).U)
-#define HW_FMC_DATAW2SnU_WR(n, v) (HW_FMC_DATAW2SnU(n).U = (v))
-#define HW_FMC_DATAW2SnU_SET(n, v) (HW_FMC_DATAW2SnU_WR(n, HW_FMC_DATAW2SnU_RD(n) | (v)))
-#define HW_FMC_DATAW2SnU_CLR(n, v) (HW_FMC_DATAW2SnU_WR(n, HW_FMC_DATAW2SnU_RD(n) & ~(v)))
-#define HW_FMC_DATAW2SnU_TOG(n, v) (HW_FMC_DATAW2SnU_WR(n, HW_FMC_DATAW2SnU_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FMC_DATAW2SnU bitfields
- */
-
-/*!
- * @name Register FMC_DATAW2SnU, field data[31:0] (RW)
- */
-//@{
-#define BP_FMC_DATAW2SnU_data (0U) //!< Bit position for FMC_DATAW2SnU_data.
-#define BM_FMC_DATAW2SnU_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW2SnU_data.
-#define BS_FMC_DATAW2SnU_data (32U) //!< Bit field size in bits for FMC_DATAW2SnU_data.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_DATAW2SnU_data field.
-#define BR_FMC_DATAW2SnU_data(n) (HW_FMC_DATAW2SnU(n).U)
-#endif
-
-//! @brief Format value for bitfield FMC_DATAW2SnU_data.
-#define BF_FMC_DATAW2SnU_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW2SnU_data), uint32_t) & BM_FMC_DATAW2SnU_data)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the data field to a new value.
-#define BW_FMC_DATAW2SnU_data(n, v) (HW_FMC_DATAW2SnU_WR(n, v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_FMC_DATAW2SnL - Cache Data Storage (lower word)
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FMC_DATAW2SnL - Cache Data Storage (lower word) (RW)
- *
- * Reset value: 0x00000000U
- *
- * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
- * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
- * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
- * lower word, respectively. This section represents data for the lower word (bits
- * [31:0]) of all sets in the indicated way.
- */
-typedef union _hw_fmc_dataw2snl
-{
- uint32_t U;
- struct _hw_fmc_dataw2snl_bitfields
- {
- uint32_t data : 32; //!< [31:0] Bits [31:0] of data entry
- } B;
-} hw_fmc_dataw2snl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FMC_DATAW2SnL register
- */
-//@{
-#define HW_FMC_DATAW2SnL_COUNT (4U)
-
-#define HW_FMC_DATAW2SnL_ADDR(n) (REGS_FMC_BASE + 0x244U + (0x8U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FMC_DATAW2SnL(n) (*(__IO hw_fmc_dataw2snl_t *) HW_FMC_DATAW2SnL_ADDR(n))
-#define HW_FMC_DATAW2SnL_RD(n) (HW_FMC_DATAW2SnL(n).U)
-#define HW_FMC_DATAW2SnL_WR(n, v) (HW_FMC_DATAW2SnL(n).U = (v))
-#define HW_FMC_DATAW2SnL_SET(n, v) (HW_FMC_DATAW2SnL_WR(n, HW_FMC_DATAW2SnL_RD(n) | (v)))
-#define HW_FMC_DATAW2SnL_CLR(n, v) (HW_FMC_DATAW2SnL_WR(n, HW_FMC_DATAW2SnL_RD(n) & ~(v)))
-#define HW_FMC_DATAW2SnL_TOG(n, v) (HW_FMC_DATAW2SnL_WR(n, HW_FMC_DATAW2SnL_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FMC_DATAW2SnL bitfields
- */
-
-/*!
- * @name Register FMC_DATAW2SnL, field data[31:0] (RW)
- */
-//@{
-#define BP_FMC_DATAW2SnL_data (0U) //!< Bit position for FMC_DATAW2SnL_data.
-#define BM_FMC_DATAW2SnL_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW2SnL_data.
-#define BS_FMC_DATAW2SnL_data (32U) //!< Bit field size in bits for FMC_DATAW2SnL_data.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_DATAW2SnL_data field.
-#define BR_FMC_DATAW2SnL_data(n) (HW_FMC_DATAW2SnL(n).U)
-#endif
-
-//! @brief Format value for bitfield FMC_DATAW2SnL_data.
-#define BF_FMC_DATAW2SnL_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW2SnL_data), uint32_t) & BM_FMC_DATAW2SnL_data)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the data field to a new value.
-#define BW_FMC_DATAW2SnL_data(n, v) (HW_FMC_DATAW2SnL_WR(n, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FMC_DATAW3SnU - Cache Data Storage (upper word)
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FMC_DATAW3SnU - Cache Data Storage (upper word) (RW)
- *
- * Reset value: 0x00000000U
- *
- * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
- * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
- * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
- * lower word, respectively. This section represents data for the upper word (bits
- * [63:32]) of all sets in the indicated way.
- */
-typedef union _hw_fmc_dataw3snu
-{
- uint32_t U;
- struct _hw_fmc_dataw3snu_bitfields
- {
- uint32_t data : 32; //!< [31:0] Bits [63:32] of data entry
- } B;
-} hw_fmc_dataw3snu_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FMC_DATAW3SnU register
- */
-//@{
-#define HW_FMC_DATAW3SnU_COUNT (4U)
-
-#define HW_FMC_DATAW3SnU_ADDR(n) (REGS_FMC_BASE + 0x260U + (0x8U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FMC_DATAW3SnU(n) (*(__IO hw_fmc_dataw3snu_t *) HW_FMC_DATAW3SnU_ADDR(n))
-#define HW_FMC_DATAW3SnU_RD(n) (HW_FMC_DATAW3SnU(n).U)
-#define HW_FMC_DATAW3SnU_WR(n, v) (HW_FMC_DATAW3SnU(n).U = (v))
-#define HW_FMC_DATAW3SnU_SET(n, v) (HW_FMC_DATAW3SnU_WR(n, HW_FMC_DATAW3SnU_RD(n) | (v)))
-#define HW_FMC_DATAW3SnU_CLR(n, v) (HW_FMC_DATAW3SnU_WR(n, HW_FMC_DATAW3SnU_RD(n) & ~(v)))
-#define HW_FMC_DATAW3SnU_TOG(n, v) (HW_FMC_DATAW3SnU_WR(n, HW_FMC_DATAW3SnU_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FMC_DATAW3SnU bitfields
- */
-
-/*!
- * @name Register FMC_DATAW3SnU, field data[31:0] (RW)
- */
-//@{
-#define BP_FMC_DATAW3SnU_data (0U) //!< Bit position for FMC_DATAW3SnU_data.
-#define BM_FMC_DATAW3SnU_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW3SnU_data.
-#define BS_FMC_DATAW3SnU_data (32U) //!< Bit field size in bits for FMC_DATAW3SnU_data.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_DATAW3SnU_data field.
-#define BR_FMC_DATAW3SnU_data(n) (HW_FMC_DATAW3SnU(n).U)
-#endif
-
-//! @brief Format value for bitfield FMC_DATAW3SnU_data.
-#define BF_FMC_DATAW3SnU_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW3SnU_data), uint32_t) & BM_FMC_DATAW3SnU_data)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the data field to a new value.
-#define BW_FMC_DATAW3SnU_data(n, v) (HW_FMC_DATAW3SnU_WR(n, v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_FMC_DATAW3SnL - Cache Data Storage (lower word)
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FMC_DATAW3SnL - Cache Data Storage (lower word) (RW)
- *
- * Reset value: 0x00000000U
- *
- * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
- * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
- * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
- * lower word, respectively. This section represents data for the lower word (bits
- * [31:0]) of all sets in the indicated way.
- */
-typedef union _hw_fmc_dataw3snl
-{
- uint32_t U;
- struct _hw_fmc_dataw3snl_bitfields
- {
- uint32_t data : 32; //!< [31:0] Bits [31:0] of data entry
- } B;
-} hw_fmc_dataw3snl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FMC_DATAW3SnL register
- */
-//@{
-#define HW_FMC_DATAW3SnL_COUNT (4U)
-
-#define HW_FMC_DATAW3SnL_ADDR(n) (REGS_FMC_BASE + 0x264U + (0x8U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FMC_DATAW3SnL(n) (*(__IO hw_fmc_dataw3snl_t *) HW_FMC_DATAW3SnL_ADDR(n))
-#define HW_FMC_DATAW3SnL_RD(n) (HW_FMC_DATAW3SnL(n).U)
-#define HW_FMC_DATAW3SnL_WR(n, v) (HW_FMC_DATAW3SnL(n).U = (v))
-#define HW_FMC_DATAW3SnL_SET(n, v) (HW_FMC_DATAW3SnL_WR(n, HW_FMC_DATAW3SnL_RD(n) | (v)))
-#define HW_FMC_DATAW3SnL_CLR(n, v) (HW_FMC_DATAW3SnL_WR(n, HW_FMC_DATAW3SnL_RD(n) & ~(v)))
-#define HW_FMC_DATAW3SnL_TOG(n, v) (HW_FMC_DATAW3SnL_WR(n, HW_FMC_DATAW3SnL_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FMC_DATAW3SnL bitfields
- */
-
-/*!
- * @name Register FMC_DATAW3SnL, field data[31:0] (RW)
- */
-//@{
-#define BP_FMC_DATAW3SnL_data (0U) //!< Bit position for FMC_DATAW3SnL_data.
-#define BM_FMC_DATAW3SnL_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW3SnL_data.
-#define BS_FMC_DATAW3SnL_data (32U) //!< Bit field size in bits for FMC_DATAW3SnL_data.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FMC_DATAW3SnL_data field.
-#define BR_FMC_DATAW3SnL_data(n) (HW_FMC_DATAW3SnL(n).U)
-#endif
-
-//! @brief Format value for bitfield FMC_DATAW3SnL_data.
-#define BF_FMC_DATAW3SnL_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW3SnL_data), uint32_t) & BM_FMC_DATAW3SnL_data)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the data field to a new value.
-#define BW_FMC_DATAW3SnL_data(n, v) (HW_FMC_DATAW3SnL_WR(n, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_fmc_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All FMC module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_fmc
-{
- __IO hw_fmc_pfapr_t PFAPR; //!< [0x0] Flash Access Protection Register
- __IO hw_fmc_pfb0cr_t PFB0CR; //!< [0x4] Flash Bank 0 Control Register
- __IO hw_fmc_pfb1cr_t PFB1CR; //!< [0x8] Flash Bank 1 Control Register
- uint8_t _reserved0[244];
- __IO hw_fmc_tagvdw0sn_t TAGVDW0Sn[4]; //!< [0x100] Cache Tag Storage
- __IO hw_fmc_tagvdw1sn_t TAGVDW1Sn[4]; //!< [0x110] Cache Tag Storage
- __IO hw_fmc_tagvdw2sn_t TAGVDW2Sn[4]; //!< [0x120] Cache Tag Storage
- __IO hw_fmc_tagvdw3sn_t TAGVDW3Sn[4]; //!< [0x130] Cache Tag Storage
- uint8_t _reserved1[192];
- struct {
- __IO hw_fmc_dataw0snu_t DATAW0SnU; //!< [0x200] Cache Data Storage (upper word)
- __IO hw_fmc_dataw0snl_t DATAW0SnL; //!< [0x204] Cache Data Storage (lower word)
- } DATAW0Sn[4];
- struct {
- __IO hw_fmc_dataw1snu_t DATAW1SnU; //!< [0x220] Cache Data Storage (upper word)
- __IO hw_fmc_dataw1snl_t DATAW1SnL; //!< [0x224] Cache Data Storage (lower word)
- } DATAW1Sn[4];
- struct {
- __IO hw_fmc_dataw2snu_t DATAW2SnU; //!< [0x240] Cache Data Storage (upper word)
- __IO hw_fmc_dataw2snl_t DATAW2SnL; //!< [0x244] Cache Data Storage (lower word)
- } DATAW2Sn[4];
- struct {
- __IO hw_fmc_dataw3snu_t DATAW3SnU; //!< [0x260] Cache Data Storage (upper word)
- __IO hw_fmc_dataw3snl_t DATAW3SnL; //!< [0x264] Cache Data Storage (lower word)
- } DATAW3Sn[4];
-} hw_fmc_t;
-#pragma pack()
-
-//! @brief Macro to access all FMC registers.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_FMC</code>.
-#define HW_FMC (*(hw_fmc_t *) REGS_FMC_BASE)
-#endif
-
-#endif // __HW_FMC_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_ftfe.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,2500 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_FTFE_REGISTERS_H__
-#define __HW_FTFE_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 FTFE
- *
- * Flash Memory Interface
- *
- * Registers defined in this header file:
- * - HW_FTFE_FSTAT - Flash Status Register
- * - HW_FTFE_FCNFG - Flash Configuration Register
- * - HW_FTFE_FSEC - Flash Security Register
- * - HW_FTFE_FOPT - Flash Option Register
- * - HW_FTFE_FCCOB3 - Flash Common Command Object Registers
- * - HW_FTFE_FCCOB2 - Flash Common Command Object Registers
- * - HW_FTFE_FCCOB1 - Flash Common Command Object Registers
- * - HW_FTFE_FCCOB0 - Flash Common Command Object Registers
- * - HW_FTFE_FCCOB7 - Flash Common Command Object Registers
- * - HW_FTFE_FCCOB6 - Flash Common Command Object Registers
- * - HW_FTFE_FCCOB5 - Flash Common Command Object Registers
- * - HW_FTFE_FCCOB4 - Flash Common Command Object Registers
- * - HW_FTFE_FCCOBB - Flash Common Command Object Registers
- * - HW_FTFE_FCCOBA - Flash Common Command Object Registers
- * - HW_FTFE_FCCOB9 - Flash Common Command Object Registers
- * - HW_FTFE_FCCOB8 - Flash Common Command Object Registers
- * - HW_FTFE_FPROT3 - Program Flash Protection Registers
- * - HW_FTFE_FPROT2 - Program Flash Protection Registers
- * - HW_FTFE_FPROT1 - Program Flash Protection Registers
- * - HW_FTFE_FPROT0 - Program Flash Protection Registers
- * - HW_FTFE_FEPROT - EEPROM Protection Register
- * - HW_FTFE_FDPROT - Data Flash Protection Register
- *
- * - hw_ftfe_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_FTFE_BASE
-#define HW_FTFE_INSTANCE_COUNT (1U) //!< Number of instances of the FTFE module.
-#define REGS_FTFE_BASE (0x40020000U) //!< Base address for FTFE.
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTFE_FSTAT - Flash Status Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTFE_FSTAT - Flash Status Register (RW)
- *
- * Reset value: 0x00U
- *
- * The FSTAT register reports the operational status of the FTFE module. The
- * CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The MGSTAT0
- * bit is read only. The unassigned bits read 0 and are not writable. When set, the
- * Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in this
- * register prevent the launch of any more commands or writes to the FlexRAM (when
- * EEERDY is set) until the flag is cleared (by writing a one to it).
- */
-typedef union _hw_ftfe_fstat
-{
- uint8_t U;
- struct _hw_ftfe_fstat_bitfields
- {
- uint8_t MGSTAT0 : 1; //!< [0] Memory Controller Command Completion
- //! Status Flag
- uint8_t RESERVED0 : 3; //!< [3:1]
- uint8_t FPVIOL : 1; //!< [4] Flash Protection Violation Flag
- uint8_t ACCERR : 1; //!< [5] Flash Access Error Flag
- uint8_t RDCOLERR : 1; //!< [6] FTFE Read Collision Error Flag
- uint8_t CCIF : 1; //!< [7] Command Complete Interrupt Flag
- } B;
-} hw_ftfe_fstat_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTFE_FSTAT register
- */
-//@{
-#define HW_FTFE_FSTAT_ADDR (REGS_FTFE_BASE + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTFE_FSTAT (*(__IO hw_ftfe_fstat_t *) HW_FTFE_FSTAT_ADDR)
-#define HW_FTFE_FSTAT_RD() (HW_FTFE_FSTAT.U)
-#define HW_FTFE_FSTAT_WR(v) (HW_FTFE_FSTAT.U = (v))
-#define HW_FTFE_FSTAT_SET(v) (HW_FTFE_FSTAT_WR(HW_FTFE_FSTAT_RD() | (v)))
-#define HW_FTFE_FSTAT_CLR(v) (HW_FTFE_FSTAT_WR(HW_FTFE_FSTAT_RD() & ~(v)))
-#define HW_FTFE_FSTAT_TOG(v) (HW_FTFE_FSTAT_WR(HW_FTFE_FSTAT_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTFE_FSTAT bitfields
- */
-
-/*!
- * @name Register FTFE_FSTAT, field MGSTAT0[0] (RO)
- *
- * The MGSTAT0 status flag is set if an error is detected during execution of an
- * FTFE command or during the flash reset sequence. As a status flag, this bit
- * cannot (and need not) be cleared by the user like the other error flags in this
- * register. The value of the MGSTAT0 bit for "command-N" is valid only at the
- * end of the "command-N" execution when CCIF=1 and before the next command has
- * been launched. At some point during the execution of "command-N+1," the previous
- * result is discarded and any previous error is cleared.
- */
-//@{
-#define BP_FTFE_FSTAT_MGSTAT0 (0U) //!< Bit position for FTFE_FSTAT_MGSTAT0.
-#define BM_FTFE_FSTAT_MGSTAT0 (0x01U) //!< Bit mask for FTFE_FSTAT_MGSTAT0.
-#define BS_FTFE_FSTAT_MGSTAT0 (1U) //!< Bit field size in bits for FTFE_FSTAT_MGSTAT0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FSTAT_MGSTAT0 field.
-#define BR_FTFE_FSTAT_MGSTAT0 (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_MGSTAT0))
-#endif
-//@}
-
-/*!
- * @name Register FTFE_FSTAT, field FPVIOL[4] (W1C)
- *
- * The FPVIOL error bit indicates an attempt was made to program or erase an
- * address in a protected area of program flash or data flash memory during a
- * command write sequence or a write was attempted to a protected area of the FlexRAM
- * while enabled for EEPROM. While FPVIOL is set, the CCIF flag cannot be cleared
- * to launch a command. The FPVIOL bit is cleared by writing a 1 to it. Writing a
- * 0 to the FPVIOL bit has no effect.
- *
- * Values:
- * - 0 - No protection violation detected
- * - 1 - Protection violation detected
- */
-//@{
-#define BP_FTFE_FSTAT_FPVIOL (4U) //!< Bit position for FTFE_FSTAT_FPVIOL.
-#define BM_FTFE_FSTAT_FPVIOL (0x10U) //!< Bit mask for FTFE_FSTAT_FPVIOL.
-#define BS_FTFE_FSTAT_FPVIOL (1U) //!< Bit field size in bits for FTFE_FSTAT_FPVIOL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FSTAT_FPVIOL field.
-#define BR_FTFE_FSTAT_FPVIOL (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_FPVIOL))
-#endif
-
-//! @brief Format value for bitfield FTFE_FSTAT_FPVIOL.
-#define BF_FTFE_FSTAT_FPVIOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FSTAT_FPVIOL), uint8_t) & BM_FTFE_FSTAT_FPVIOL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FPVIOL field to a new value.
-#define BW_FTFE_FSTAT_FPVIOL(v) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_FPVIOL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTFE_FSTAT, field ACCERR[5] (W1C)
- *
- * The ACCERR error bit indicates an illegal access has occurred to an FTFE
- * resource caused by a violation of the command write sequence or issuing an illegal
- * FTFE command. While ACCERR is set, the CCIF flag cannot be cleared to launch
- * a command. The ACCERR bit is cleared by writing a 1 to it. Writing a 0 to the
- * ACCERR bit has no effect.
- *
- * Values:
- * - 0 - No access error detected
- * - 1 - Access error detected
- */
-//@{
-#define BP_FTFE_FSTAT_ACCERR (5U) //!< Bit position for FTFE_FSTAT_ACCERR.
-#define BM_FTFE_FSTAT_ACCERR (0x20U) //!< Bit mask for FTFE_FSTAT_ACCERR.
-#define BS_FTFE_FSTAT_ACCERR (1U) //!< Bit field size in bits for FTFE_FSTAT_ACCERR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FSTAT_ACCERR field.
-#define BR_FTFE_FSTAT_ACCERR (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_ACCERR))
-#endif
-
-//! @brief Format value for bitfield FTFE_FSTAT_ACCERR.
-#define BF_FTFE_FSTAT_ACCERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FSTAT_ACCERR), uint8_t) & BM_FTFE_FSTAT_ACCERR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ACCERR field to a new value.
-#define BW_FTFE_FSTAT_ACCERR(v) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_ACCERR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTFE_FSTAT, field RDCOLERR[6] (W1C)
- *
- * The RDCOLERR error bit indicates that the MCU attempted a read from an FTFE
- * resource that was being manipulated by an FTFE command (CCIF=0). Any
- * simultaneous access is detected as a collision error by the block arbitration logic. The
- * read data in this case cannot be guaranteed. The RDCOLERR bit is cleared by
- * writing a 1 to it. Writing a 0 to RDCOLERR has no effect.
- *
- * Values:
- * - 0 - No collision error detected
- * - 1 - Collision error detected
- */
-//@{
-#define BP_FTFE_FSTAT_RDCOLERR (6U) //!< Bit position for FTFE_FSTAT_RDCOLERR.
-#define BM_FTFE_FSTAT_RDCOLERR (0x40U) //!< Bit mask for FTFE_FSTAT_RDCOLERR.
-#define BS_FTFE_FSTAT_RDCOLERR (1U) //!< Bit field size in bits for FTFE_FSTAT_RDCOLERR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FSTAT_RDCOLERR field.
-#define BR_FTFE_FSTAT_RDCOLERR (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_RDCOLERR))
-#endif
-
-//! @brief Format value for bitfield FTFE_FSTAT_RDCOLERR.
-#define BF_FTFE_FSTAT_RDCOLERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FSTAT_RDCOLERR), uint8_t) & BM_FTFE_FSTAT_RDCOLERR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RDCOLERR field to a new value.
-#define BW_FTFE_FSTAT_RDCOLERR(v) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_RDCOLERR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTFE_FSTAT, field CCIF[7] (W1C)
- *
- * The CCIF flag indicates that a FTFE command or EEPROM file system operation
- * has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a
- * command, and CCIF stays low until command completion or command violation. The
- * CCIF flag is also cleared by a successful write to FlexRAM while enabled for EEE,
- * and CCIF stays low until the EEPROM file system has created the associated
- * EEPROM data record. The CCIF bit is reset to 0 but is set to 1 by the memory
- * controller at the end of the reset initialization sequence. Depending on how
- * quickly the read occurs after reset release, the user may or may not see the 0
- * hardware reset value.
- *
- * Values:
- * - 0 - FTFE command or EEPROM file system operation in progress
- * - 1 - FTFE command or EEPROM file system operation has completed
- */
-//@{
-#define BP_FTFE_FSTAT_CCIF (7U) //!< Bit position for FTFE_FSTAT_CCIF.
-#define BM_FTFE_FSTAT_CCIF (0x80U) //!< Bit mask for FTFE_FSTAT_CCIF.
-#define BS_FTFE_FSTAT_CCIF (1U) //!< Bit field size in bits for FTFE_FSTAT_CCIF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FSTAT_CCIF field.
-#define BR_FTFE_FSTAT_CCIF (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_CCIF))
-#endif
-
-//! @brief Format value for bitfield FTFE_FSTAT_CCIF.
-#define BF_FTFE_FSTAT_CCIF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FSTAT_CCIF), uint8_t) & BM_FTFE_FSTAT_CCIF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CCIF field to a new value.
-#define BW_FTFE_FSTAT_CCIF(v) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_CCIF) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTFE_FCNFG - Flash Configuration Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTFE_FCNFG - Flash Configuration Register (RW)
- *
- * Reset value: 0x00U
- *
- * This register provides information on the current functional state of the
- * FTFE module. The erase control bits (ERSAREQ and ERSSUSP) have write
- * restrictions. SWAP, PFLSH, RAMRDY, and EEERDY are read-only status bits. The unassigned
- * bits read as noted and are not writable. The reset values for the SWAP, PFLSH,
- * RAMRDY, and EEERDY bits are determined during the reset sequence.
- */
-typedef union _hw_ftfe_fcnfg
-{
- uint8_t U;
- struct _hw_ftfe_fcnfg_bitfields
- {
- uint8_t EEERDY : 1; //!< [0]
- uint8_t RAMRDY : 1; //!< [1] RAM Ready
- uint8_t PFLSH : 1; //!< [2] FTFE configuration
- uint8_t SWAP : 1; //!< [3] Swap
- uint8_t ERSSUSP : 1; //!< [4] Erase Suspend
- uint8_t ERSAREQ : 1; //!< [5] Erase All Request
- uint8_t RDCOLLIE : 1; //!< [6] Read Collision Error Interrupt Enable
- uint8_t CCIE : 1; //!< [7] Command Complete Interrupt Enable
- } B;
-} hw_ftfe_fcnfg_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTFE_FCNFG register
- */
-//@{
-#define HW_FTFE_FCNFG_ADDR (REGS_FTFE_BASE + 0x1U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTFE_FCNFG (*(__IO hw_ftfe_fcnfg_t *) HW_FTFE_FCNFG_ADDR)
-#define HW_FTFE_FCNFG_RD() (HW_FTFE_FCNFG.U)
-#define HW_FTFE_FCNFG_WR(v) (HW_FTFE_FCNFG.U = (v))
-#define HW_FTFE_FCNFG_SET(v) (HW_FTFE_FCNFG_WR(HW_FTFE_FCNFG_RD() | (v)))
-#define HW_FTFE_FCNFG_CLR(v) (HW_FTFE_FCNFG_WR(HW_FTFE_FCNFG_RD() & ~(v)))
-#define HW_FTFE_FCNFG_TOG(v) (HW_FTFE_FCNFG_WR(HW_FTFE_FCNFG_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTFE_FCNFG bitfields
- */
-
-/*!
- * @name Register FTFE_FCNFG, field EEERDY[0] (RO)
- *
- * For devices with FlexNVM: This flag indicates if the EEPROM backup data has
- * been copied to the FlexRAM and is therefore available for read access. During
- * the reset sequence, the EEERDY flag remains clear while CCIF=0 and only sets if
- * the FlexNVM block is partitioned for EEPROM. For devices without FlexNVM:
- * This bit is reserved.
- *
- * Values:
- * - 0 - For devices with FlexNVM: FlexRAM is not available for EEPROM operation.
- * - 1 - For devices with FlexNVM: FlexRAM is available for EEPROM operations
- * where: reads from the FlexRAM return data previously written to the FlexRAM
- * in EEPROM mode and writes launch an EEPROM operation to store the written
- * data in the FlexRAM and EEPROM backup.
- */
-//@{
-#define BP_FTFE_FCNFG_EEERDY (0U) //!< Bit position for FTFE_FCNFG_EEERDY.
-#define BM_FTFE_FCNFG_EEERDY (0x01U) //!< Bit mask for FTFE_FCNFG_EEERDY.
-#define BS_FTFE_FCNFG_EEERDY (1U) //!< Bit field size in bits for FTFE_FCNFG_EEERDY.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FCNFG_EEERDY field.
-#define BR_FTFE_FCNFG_EEERDY (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_EEERDY))
-#endif
-//@}
-
-/*!
- * @name Register FTFE_FCNFG, field RAMRDY[1] (RO)
- *
- * This flag indicates the current status of the FlexRAM/ programming
- * acceleration RAM. For devices with FlexNVM: The state of the RAMRDY flag is normally
- * controlled by the Set FlexRAM Function command. During the reset sequence, the
- * RAMRDY flag is cleared if the FlexNVM block is partitioned for EEPROM and will
- * be set if the FlexNVM block is not partitioned for EEPROM . The RAMRDY flag is
- * cleared if the Program Partition command is run to partition the FlexNVM block
- * for EEPROM. The RAMRDY flag sets after completion of the Erase All Blocks
- * command or execution of the erase-all operation triggered external to the FTFE.
- * For devices without FlexNVM: This bit should always be set.
- *
- * Values:
- * - 0 - For devices with FlexNVM: FlexRAM is not available for traditional RAM
- * access. For devices without FlexNVM: Programming acceleration RAM is not
- * available.
- * - 1 - For devices with FlexNVM: FlexRAM is available as traditional RAM only;
- * writes to the FlexRAM do not trigger EEPROM operations. For devices
- * without FlexNVM: Programming acceleration RAM is available.
- */
-//@{
-#define BP_FTFE_FCNFG_RAMRDY (1U) //!< Bit position for FTFE_FCNFG_RAMRDY.
-#define BM_FTFE_FCNFG_RAMRDY (0x02U) //!< Bit mask for FTFE_FCNFG_RAMRDY.
-#define BS_FTFE_FCNFG_RAMRDY (1U) //!< Bit field size in bits for FTFE_FCNFG_RAMRDY.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FCNFG_RAMRDY field.
-#define BR_FTFE_FCNFG_RAMRDY (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_RAMRDY))
-#endif
-//@}
-
-/*!
- * @name Register FTFE_FCNFG, field PFLSH[2] (RO)
- *
- * Values:
- * - 0 - For devices with FlexNVM: FTFE configuration supports two program flash
- * blocks and two FlexNVM blocks For devices with program flash only:
- * Reserved
- * - 1 - For devices with FlexNVM: Reserved For devices with program flash only:
- * FTFE configuration supports four program flash blocks
- */
-//@{
-#define BP_FTFE_FCNFG_PFLSH (2U) //!< Bit position for FTFE_FCNFG_PFLSH.
-#define BM_FTFE_FCNFG_PFLSH (0x04U) //!< Bit mask for FTFE_FCNFG_PFLSH.
-#define BS_FTFE_FCNFG_PFLSH (1U) //!< Bit field size in bits for FTFE_FCNFG_PFLSH.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FCNFG_PFLSH field.
-#define BR_FTFE_FCNFG_PFLSH (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_PFLSH))
-#endif
-//@}
-
-/*!
- * @name Register FTFE_FCNFG, field SWAP[3] (RO)
- *
- * The SWAP flag indicates which half of the program flash space is located at
- * relative address 0x0000. The state of the SWAP flag is set by the FTFE during
- * the reset sequence. See for information on swap management.
- *
- * Values:
- * - 0 - For devices with FlexNVM: Program flash 0 block is located at relative
- * address 0x0000 For devices with program flash only: Program flash 0 block
- * is located at relative address 0x0000
- * - 1 - For devices with FlexNVM: Reserved For devices with program flash only:
- * Program flash 1 block is located at relative address 0x0000
- */
-//@{
-#define BP_FTFE_FCNFG_SWAP (3U) //!< Bit position for FTFE_FCNFG_SWAP.
-#define BM_FTFE_FCNFG_SWAP (0x08U) //!< Bit mask for FTFE_FCNFG_SWAP.
-#define BS_FTFE_FCNFG_SWAP (1U) //!< Bit field size in bits for FTFE_FCNFG_SWAP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FCNFG_SWAP field.
-#define BR_FTFE_FCNFG_SWAP (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_SWAP))
-#endif
-//@}
-
-/*!
- * @name Register FTFE_FCNFG, field ERSSUSP[4] (RW)
- *
- * The ERSSUSP bit allows the user to suspend (interrupt) the Erase Flash Sector
- * command while it is executing.
- *
- * Values:
- * - 0 - No suspend requested
- * - 1 - Suspend the current Erase Flash Sector command execution.
- */
-//@{
-#define BP_FTFE_FCNFG_ERSSUSP (4U) //!< Bit position for FTFE_FCNFG_ERSSUSP.
-#define BM_FTFE_FCNFG_ERSSUSP (0x10U) //!< Bit mask for FTFE_FCNFG_ERSSUSP.
-#define BS_FTFE_FCNFG_ERSSUSP (1U) //!< Bit field size in bits for FTFE_FCNFG_ERSSUSP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FCNFG_ERSSUSP field.
-#define BR_FTFE_FCNFG_ERSSUSP (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_ERSSUSP))
-#endif
-
-//! @brief Format value for bitfield FTFE_FCNFG_ERSSUSP.
-#define BF_FTFE_FCNFG_ERSSUSP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCNFG_ERSSUSP), uint8_t) & BM_FTFE_FCNFG_ERSSUSP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERSSUSP field to a new value.
-#define BW_FTFE_FCNFG_ERSSUSP(v) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_ERSSUSP) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTFE_FCNFG, field ERSAREQ[5] (RO)
- *
- * This bit issues a request to the memory controller to execute the Erase All
- * Blocks command and release security. ERSAREQ is not directly writable but is
- * under indirect user control. Refer to the device's Chip Configuration details on
- * how to request this command. The ERSAREQ bit sets when an erase all request
- * is triggered external to the FTFE and CCIF is set (no command is currently
- * being executed). ERSAREQ is cleared by the FTFE when the operation completes.
- *
- * Values:
- * - 0 - No request or request complete
- * - 1 - Request to: run the Erase All Blocks command, verify the erased state,
- * program the security byte in the Flash Configuration Field to the unsecure
- * state, and release MCU security by setting the FSEC[SEC] field to the
- * unsecure state.
- */
-//@{
-#define BP_FTFE_FCNFG_ERSAREQ (5U) //!< Bit position for FTFE_FCNFG_ERSAREQ.
-#define BM_FTFE_FCNFG_ERSAREQ (0x20U) //!< Bit mask for FTFE_FCNFG_ERSAREQ.
-#define BS_FTFE_FCNFG_ERSAREQ (1U) //!< Bit field size in bits for FTFE_FCNFG_ERSAREQ.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FCNFG_ERSAREQ field.
-#define BR_FTFE_FCNFG_ERSAREQ (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_ERSAREQ))
-#endif
-//@}
-
-/*!
- * @name Register FTFE_FCNFG, field RDCOLLIE[6] (RW)
- *
- * The RDCOLLIE bit controls interrupt generation when an FTFE read collision
- * error occurs.
- *
- * Values:
- * - 0 - Read collision error interrupt disabled
- * - 1 - Read collision error interrupt enabled. An interrupt request is
- * generated whenever an FTFE read collision error is detected (see the description
- * of FSTAT[RDCOLERR]).
- */
-//@{
-#define BP_FTFE_FCNFG_RDCOLLIE (6U) //!< Bit position for FTFE_FCNFG_RDCOLLIE.
-#define BM_FTFE_FCNFG_RDCOLLIE (0x40U) //!< Bit mask for FTFE_FCNFG_RDCOLLIE.
-#define BS_FTFE_FCNFG_RDCOLLIE (1U) //!< Bit field size in bits for FTFE_FCNFG_RDCOLLIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FCNFG_RDCOLLIE field.
-#define BR_FTFE_FCNFG_RDCOLLIE (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_RDCOLLIE))
-#endif
-
-//! @brief Format value for bitfield FTFE_FCNFG_RDCOLLIE.
-#define BF_FTFE_FCNFG_RDCOLLIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCNFG_RDCOLLIE), uint8_t) & BM_FTFE_FCNFG_RDCOLLIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RDCOLLIE field to a new value.
-#define BW_FTFE_FCNFG_RDCOLLIE(v) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_RDCOLLIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTFE_FCNFG, field CCIE[7] (RW)
- *
- * The CCIE bit controls interrupt generation when an FTFE command completes.
- *
- * Values:
- * - 0 - Command complete interrupt disabled
- * - 1 - Command complete interrupt enabled. An interrupt request is generated
- * whenever the FSTAT[CCIF] flag is set.
- */
-//@{
-#define BP_FTFE_FCNFG_CCIE (7U) //!< Bit position for FTFE_FCNFG_CCIE.
-#define BM_FTFE_FCNFG_CCIE (0x80U) //!< Bit mask for FTFE_FCNFG_CCIE.
-#define BS_FTFE_FCNFG_CCIE (1U) //!< Bit field size in bits for FTFE_FCNFG_CCIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FCNFG_CCIE field.
-#define BR_FTFE_FCNFG_CCIE (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_CCIE))
-#endif
-
-//! @brief Format value for bitfield FTFE_FCNFG_CCIE.
-#define BF_FTFE_FCNFG_CCIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCNFG_CCIE), uint8_t) & BM_FTFE_FCNFG_CCIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CCIE field to a new value.
-#define BW_FTFE_FCNFG_CCIE(v) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_CCIE) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTFE_FSEC - Flash Security Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTFE_FSEC - Flash Security Register (RO)
- *
- * Reset value: 0x00U
- *
- * This read-only register holds all bits associated with the security of the
- * MCU and FTFE module. During the reset sequence, the register is loaded with the
- * contents of the flash security byte in the Flash Configuration Field located
- * in program flash memory. The Flash basis for the values is signified by X in
- * the reset value.
- */
-typedef union _hw_ftfe_fsec
-{
- uint8_t U;
- struct _hw_ftfe_fsec_bitfields
- {
- uint8_t SEC : 2; //!< [1:0] Flash Security
- uint8_t FSLACC : 2; //!< [3:2] Freescale Failure Analysis Access Code
- uint8_t MEEN : 2; //!< [5:4] Mass Erase Enable Bits
- uint8_t KEYEN : 2; //!< [7:6] Backdoor Key Security Enable
- } B;
-} hw_ftfe_fsec_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTFE_FSEC register
- */
-//@{
-#define HW_FTFE_FSEC_ADDR (REGS_FTFE_BASE + 0x2U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTFE_FSEC (*(__I hw_ftfe_fsec_t *) HW_FTFE_FSEC_ADDR)
-#define HW_FTFE_FSEC_RD() (HW_FTFE_FSEC.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTFE_FSEC bitfields
- */
-
-/*!
- * @name Register FTFE_FSEC, field SEC[1:0] (RO)
- *
- * These bits define the security state of the MCU. In the secure state, the MCU
- * limits access to FTFE module resources. The limitations are defined per
- * device and are detailed in the Chip Configuration details. If the FTFE module is
- * unsecured using backdoor key access, the SEC bits are forced to 10b.
- *
- * Values:
- * - 00 - MCU security status is secure
- * - 01 - MCU security status is secure
- * - 10 - MCU security status is unsecure (The standard shipping condition of
- * the FTFE is unsecure.)
- * - 11 - MCU security status is secure
- */
-//@{
-#define BP_FTFE_FSEC_SEC (0U) //!< Bit position for FTFE_FSEC_SEC.
-#define BM_FTFE_FSEC_SEC (0x03U) //!< Bit mask for FTFE_FSEC_SEC.
-#define BS_FTFE_FSEC_SEC (2U) //!< Bit field size in bits for FTFE_FSEC_SEC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FSEC_SEC field.
-#define BR_FTFE_FSEC_SEC (HW_FTFE_FSEC.B.SEC)
-#endif
-//@}
-
-/*!
- * @name Register FTFE_FSEC, field FSLACC[3:2] (RO)
- *
- * These bits enable or disable access to the flash memory contents during
- * returned part failure analysis at Freescale. When SEC is secure and FSLACC is
- * denied, access to the program flash contents is denied and any failure analysis
- * performed by Freescale factory test must begin with a full erase to unsecure the
- * part. When access is granted (SEC is unsecure, or SEC is secure and FSLACC is
- * granted), Freescale factory testing has visibility of the current flash
- * contents. The state of the FSLACC bits is only relevant when the SEC bits are set to
- * secure. When the SEC field is set to unsecure, the FSLACC setting does not
- * matter.
- *
- * Values:
- * - 00 - Freescale factory access granted
- * - 01 - Freescale factory access denied
- * - 10 - Freescale factory access denied
- * - 11 - Freescale factory access granted
- */
-//@{
-#define BP_FTFE_FSEC_FSLACC (2U) //!< Bit position for FTFE_FSEC_FSLACC.
-#define BM_FTFE_FSEC_FSLACC (0x0CU) //!< Bit mask for FTFE_FSEC_FSLACC.
-#define BS_FTFE_FSEC_FSLACC (2U) //!< Bit field size in bits for FTFE_FSEC_FSLACC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FSEC_FSLACC field.
-#define BR_FTFE_FSEC_FSLACC (HW_FTFE_FSEC.B.FSLACC)
-#endif
-//@}
-
-/*!
- * @name Register FTFE_FSEC, field MEEN[5:4] (RO)
- *
- * Enables and disables mass erase capability of the FTFE module. The state of
- * the MEEN bits is only relevant when the SEC bits are set to secure outside of
- * NVM Normal Mode. When the SEC field is set to unsecure, the MEEN setting does
- * not matter.
- *
- * Values:
- * - 00 - Mass erase is enabled
- * - 01 - Mass erase is enabled
- * - 10 - Mass erase is disabled
- * - 11 - Mass erase is enabled
- */
-//@{
-#define BP_FTFE_FSEC_MEEN (4U) //!< Bit position for FTFE_FSEC_MEEN.
-#define BM_FTFE_FSEC_MEEN (0x30U) //!< Bit mask for FTFE_FSEC_MEEN.
-#define BS_FTFE_FSEC_MEEN (2U) //!< Bit field size in bits for FTFE_FSEC_MEEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FSEC_MEEN field.
-#define BR_FTFE_FSEC_MEEN (HW_FTFE_FSEC.B.MEEN)
-#endif
-//@}
-
-/*!
- * @name Register FTFE_FSEC, field KEYEN[7:6] (RO)
- *
- * These bits enable and disable backdoor key access to the FTFE module.
- *
- * Values:
- * - 00 - Backdoor key access disabled
- * - 01 - Backdoor key access disabled (preferred KEYEN state to disable
- * backdoor key access)
- * - 10 - Backdoor key access enabled
- * - 11 - Backdoor key access disabled
- */
-//@{
-#define BP_FTFE_FSEC_KEYEN (6U) //!< Bit position for FTFE_FSEC_KEYEN.
-#define BM_FTFE_FSEC_KEYEN (0xC0U) //!< Bit mask for FTFE_FSEC_KEYEN.
-#define BS_FTFE_FSEC_KEYEN (2U) //!< Bit field size in bits for FTFE_FSEC_KEYEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FSEC_KEYEN field.
-#define BR_FTFE_FSEC_KEYEN (HW_FTFE_FSEC.B.KEYEN)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTFE_FOPT - Flash Option Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTFE_FOPT - Flash Option Register (RO)
- *
- * Reset value: 0x00U
- *
- * The flash option register allows the MCU to customize its operations by
- * examining the state of these read-only bits, which are loaded from NVM at reset.
- * The function of the bits is defined in the device's Chip Configuration details.
- * All bits in the register are read-only. During the reset sequence, the
- * register is loaded from the flash nonvolatile option byte in the Flash Configuration
- * Field located in program flash memory. The flash basis for the values is
- * signified by X in the reset value.
- */
-typedef union _hw_ftfe_fopt
-{
- uint8_t U;
- struct _hw_ftfe_fopt_bitfields
- {
- uint8_t OPT : 8; //!< [7:0] Nonvolatile Option
- } B;
-} hw_ftfe_fopt_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTFE_FOPT register
- */
-//@{
-#define HW_FTFE_FOPT_ADDR (REGS_FTFE_BASE + 0x3U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTFE_FOPT (*(__I hw_ftfe_fopt_t *) HW_FTFE_FOPT_ADDR)
-#define HW_FTFE_FOPT_RD() (HW_FTFE_FOPT.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTFE_FOPT bitfields
- */
-
-/*!
- * @name Register FTFE_FOPT, field OPT[7:0] (RO)
- *
- * These bits are loaded from flash to this register at reset. Refer to the
- * device's Chip Configuration details for the definition and use of these bits.
- */
-//@{
-#define BP_FTFE_FOPT_OPT (0U) //!< Bit position for FTFE_FOPT_OPT.
-#define BM_FTFE_FOPT_OPT (0xFFU) //!< Bit mask for FTFE_FOPT_OPT.
-#define BS_FTFE_FOPT_OPT (8U) //!< Bit field size in bits for FTFE_FOPT_OPT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FOPT_OPT field.
-#define BR_FTFE_FOPT_OPT (HW_FTFE_FOPT.U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTFE_FCCOB3 - Flash Common Command Object Registers
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTFE_FCCOB3 - Flash Common Command Object Registers (RW)
- *
- * Reset value: 0x00U
- *
- * The FCCOB register group provides 12 bytes for command codes and parameters.
- * The individual bytes within the set append a 0-B hex identifier to the FCCOB
- * register name: FCCOB0, FCCOB1, ..., FCCOBB.
- */
-typedef union _hw_ftfe_fccob3
-{
- uint8_t U;
- struct _hw_ftfe_fccob3_bitfields
- {
- uint8_t CCOBn : 8; //!< [7:0]
- } B;
-} hw_ftfe_fccob3_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTFE_FCCOB3 register
- */
-//@{
-#define HW_FTFE_FCCOB3_ADDR (REGS_FTFE_BASE + 0x4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTFE_FCCOB3 (*(__IO hw_ftfe_fccob3_t *) HW_FTFE_FCCOB3_ADDR)
-#define HW_FTFE_FCCOB3_RD() (HW_FTFE_FCCOB3.U)
-#define HW_FTFE_FCCOB3_WR(v) (HW_FTFE_FCCOB3.U = (v))
-#define HW_FTFE_FCCOB3_SET(v) (HW_FTFE_FCCOB3_WR(HW_FTFE_FCCOB3_RD() | (v)))
-#define HW_FTFE_FCCOB3_CLR(v) (HW_FTFE_FCCOB3_WR(HW_FTFE_FCCOB3_RD() & ~(v)))
-#define HW_FTFE_FCCOB3_TOG(v) (HW_FTFE_FCCOB3_WR(HW_FTFE_FCCOB3_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTFE_FCCOB3 bitfields
- */
-
-/*!
- * @name Register FTFE_FCCOB3, field CCOBn[7:0] (RW)
- *
- * The FCCOB register provides a command code and relevant parameters to the
- * memory controller. The individual registers that compose the FCCOB data set can
- * be written in any order, but you must provide all needed values, which vary
- * from command to command. First, set up all required FCCOB fields and then
- * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
- * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
- * by the user until the command completes (CCIF returns to 1). No command
- * buffering or queueing is provided; the next command can be loaded only after the
- * current command completes. Some commands return information to the FCCOB
- * registers. Any values returned to FCCOB are available for reading after the
- * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
- * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
- * the command code. This 8-bit value defines the command to be executed. The
- * command code is followed by the parameters required for this specific FTFE command,
- * typically an address and/or data values. The command parameter table is
- * written in terms of FCCOB Number (which is equivalent to the byte number). This
- * number is a reference to the FCCOB register name and is not the register address.
- * FCCOB NumberRefers to FCCOB register name, not register address Typical
- * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
- * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
- * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
- * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
- * register group uses a big endian addressing convention. For all command parameter
- * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
- * register number. The FCCOB register group may be read and written as
- * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
- */
-//@{
-#define BP_FTFE_FCCOB3_CCOBn (0U) //!< Bit position for FTFE_FCCOB3_CCOBn.
-#define BM_FTFE_FCCOB3_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB3_CCOBn.
-#define BS_FTFE_FCCOB3_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB3_CCOBn.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FCCOB3_CCOBn field.
-#define BR_FTFE_FCCOB3_CCOBn (HW_FTFE_FCCOB3.U)
-#endif
-
-//! @brief Format value for bitfield FTFE_FCCOB3_CCOBn.
-#define BF_FTFE_FCCOB3_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB3_CCOBn), uint8_t) & BM_FTFE_FCCOB3_CCOBn)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CCOBn field to a new value.
-#define BW_FTFE_FCCOB3_CCOBn(v) (HW_FTFE_FCCOB3_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTFE_FCCOB2 - Flash Common Command Object Registers
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTFE_FCCOB2 - Flash Common Command Object Registers (RW)
- *
- * Reset value: 0x00U
- *
- * The FCCOB register group provides 12 bytes for command codes and parameters.
- * The individual bytes within the set append a 0-B hex identifier to the FCCOB
- * register name: FCCOB0, FCCOB1, ..., FCCOBB.
- */
-typedef union _hw_ftfe_fccob2
-{
- uint8_t U;
- struct _hw_ftfe_fccob2_bitfields
- {
- uint8_t CCOBn : 8; //!< [7:0]
- } B;
-} hw_ftfe_fccob2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTFE_FCCOB2 register
- */
-//@{
-#define HW_FTFE_FCCOB2_ADDR (REGS_FTFE_BASE + 0x5U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTFE_FCCOB2 (*(__IO hw_ftfe_fccob2_t *) HW_FTFE_FCCOB2_ADDR)
-#define HW_FTFE_FCCOB2_RD() (HW_FTFE_FCCOB2.U)
-#define HW_FTFE_FCCOB2_WR(v) (HW_FTFE_FCCOB2.U = (v))
-#define HW_FTFE_FCCOB2_SET(v) (HW_FTFE_FCCOB2_WR(HW_FTFE_FCCOB2_RD() | (v)))
-#define HW_FTFE_FCCOB2_CLR(v) (HW_FTFE_FCCOB2_WR(HW_FTFE_FCCOB2_RD() & ~(v)))
-#define HW_FTFE_FCCOB2_TOG(v) (HW_FTFE_FCCOB2_WR(HW_FTFE_FCCOB2_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTFE_FCCOB2 bitfields
- */
-
-/*!
- * @name Register FTFE_FCCOB2, field CCOBn[7:0] (RW)
- *
- * The FCCOB register provides a command code and relevant parameters to the
- * memory controller. The individual registers that compose the FCCOB data set can
- * be written in any order, but you must provide all needed values, which vary
- * from command to command. First, set up all required FCCOB fields and then
- * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
- * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
- * by the user until the command completes (CCIF returns to 1). No command
- * buffering or queueing is provided; the next command can be loaded only after the
- * current command completes. Some commands return information to the FCCOB
- * registers. Any values returned to FCCOB are available for reading after the
- * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
- * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
- * the command code. This 8-bit value defines the command to be executed. The
- * command code is followed by the parameters required for this specific FTFE command,
- * typically an address and/or data values. The command parameter table is
- * written in terms of FCCOB Number (which is equivalent to the byte number). This
- * number is a reference to the FCCOB register name and is not the register address.
- * FCCOB NumberRefers to FCCOB register name, not register address Typical
- * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
- * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
- * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
- * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
- * register group uses a big endian addressing convention. For all command parameter
- * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
- * register number. The FCCOB register group may be read and written as
- * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
- */
-//@{
-#define BP_FTFE_FCCOB2_CCOBn (0U) //!< Bit position for FTFE_FCCOB2_CCOBn.
-#define BM_FTFE_FCCOB2_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB2_CCOBn.
-#define BS_FTFE_FCCOB2_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB2_CCOBn.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FCCOB2_CCOBn field.
-#define BR_FTFE_FCCOB2_CCOBn (HW_FTFE_FCCOB2.U)
-#endif
-
-//! @brief Format value for bitfield FTFE_FCCOB2_CCOBn.
-#define BF_FTFE_FCCOB2_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB2_CCOBn), uint8_t) & BM_FTFE_FCCOB2_CCOBn)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CCOBn field to a new value.
-#define BW_FTFE_FCCOB2_CCOBn(v) (HW_FTFE_FCCOB2_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTFE_FCCOB1 - Flash Common Command Object Registers
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTFE_FCCOB1 - Flash Common Command Object Registers (RW)
- *
- * Reset value: 0x00U
- *
- * The FCCOB register group provides 12 bytes for command codes and parameters.
- * The individual bytes within the set append a 0-B hex identifier to the FCCOB
- * register name: FCCOB0, FCCOB1, ..., FCCOBB.
- */
-typedef union _hw_ftfe_fccob1
-{
- uint8_t U;
- struct _hw_ftfe_fccob1_bitfields
- {
- uint8_t CCOBn : 8; //!< [7:0]
- } B;
-} hw_ftfe_fccob1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTFE_FCCOB1 register
- */
-//@{
-#define HW_FTFE_FCCOB1_ADDR (REGS_FTFE_BASE + 0x6U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTFE_FCCOB1 (*(__IO hw_ftfe_fccob1_t *) HW_FTFE_FCCOB1_ADDR)
-#define HW_FTFE_FCCOB1_RD() (HW_FTFE_FCCOB1.U)
-#define HW_FTFE_FCCOB1_WR(v) (HW_FTFE_FCCOB1.U = (v))
-#define HW_FTFE_FCCOB1_SET(v) (HW_FTFE_FCCOB1_WR(HW_FTFE_FCCOB1_RD() | (v)))
-#define HW_FTFE_FCCOB1_CLR(v) (HW_FTFE_FCCOB1_WR(HW_FTFE_FCCOB1_RD() & ~(v)))
-#define HW_FTFE_FCCOB1_TOG(v) (HW_FTFE_FCCOB1_WR(HW_FTFE_FCCOB1_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTFE_FCCOB1 bitfields
- */
-
-/*!
- * @name Register FTFE_FCCOB1, field CCOBn[7:0] (RW)
- *
- * The FCCOB register provides a command code and relevant parameters to the
- * memory controller. The individual registers that compose the FCCOB data set can
- * be written in any order, but you must provide all needed values, which vary
- * from command to command. First, set up all required FCCOB fields and then
- * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
- * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
- * by the user until the command completes (CCIF returns to 1). No command
- * buffering or queueing is provided; the next command can be loaded only after the
- * current command completes. Some commands return information to the FCCOB
- * registers. Any values returned to FCCOB are available for reading after the
- * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
- * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
- * the command code. This 8-bit value defines the command to be executed. The
- * command code is followed by the parameters required for this specific FTFE command,
- * typically an address and/or data values. The command parameter table is
- * written in terms of FCCOB Number (which is equivalent to the byte number). This
- * number is a reference to the FCCOB register name and is not the register address.
- * FCCOB NumberRefers to FCCOB register name, not register address Typical
- * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
- * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
- * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
- * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
- * register group uses a big endian addressing convention. For all command parameter
- * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
- * register number. The FCCOB register group may be read and written as
- * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
- */
-//@{
-#define BP_FTFE_FCCOB1_CCOBn (0U) //!< Bit position for FTFE_FCCOB1_CCOBn.
-#define BM_FTFE_FCCOB1_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB1_CCOBn.
-#define BS_FTFE_FCCOB1_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB1_CCOBn.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FCCOB1_CCOBn field.
-#define BR_FTFE_FCCOB1_CCOBn (HW_FTFE_FCCOB1.U)
-#endif
-
-//! @brief Format value for bitfield FTFE_FCCOB1_CCOBn.
-#define BF_FTFE_FCCOB1_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB1_CCOBn), uint8_t) & BM_FTFE_FCCOB1_CCOBn)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CCOBn field to a new value.
-#define BW_FTFE_FCCOB1_CCOBn(v) (HW_FTFE_FCCOB1_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTFE_FCCOB0 - Flash Common Command Object Registers
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTFE_FCCOB0 - Flash Common Command Object Registers (RW)
- *
- * Reset value: 0x00U
- *
- * The FCCOB register group provides 12 bytes for command codes and parameters.
- * The individual bytes within the set append a 0-B hex identifier to the FCCOB
- * register name: FCCOB0, FCCOB1, ..., FCCOBB.
- */
-typedef union _hw_ftfe_fccob0
-{
- uint8_t U;
- struct _hw_ftfe_fccob0_bitfields
- {
- uint8_t CCOBn : 8; //!< [7:0]
- } B;
-} hw_ftfe_fccob0_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTFE_FCCOB0 register
- */
-//@{
-#define HW_FTFE_FCCOB0_ADDR (REGS_FTFE_BASE + 0x7U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTFE_FCCOB0 (*(__IO hw_ftfe_fccob0_t *) HW_FTFE_FCCOB0_ADDR)
-#define HW_FTFE_FCCOB0_RD() (HW_FTFE_FCCOB0.U)
-#define HW_FTFE_FCCOB0_WR(v) (HW_FTFE_FCCOB0.U = (v))
-#define HW_FTFE_FCCOB0_SET(v) (HW_FTFE_FCCOB0_WR(HW_FTFE_FCCOB0_RD() | (v)))
-#define HW_FTFE_FCCOB0_CLR(v) (HW_FTFE_FCCOB0_WR(HW_FTFE_FCCOB0_RD() & ~(v)))
-#define HW_FTFE_FCCOB0_TOG(v) (HW_FTFE_FCCOB0_WR(HW_FTFE_FCCOB0_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTFE_FCCOB0 bitfields
- */
-
-/*!
- * @name Register FTFE_FCCOB0, field CCOBn[7:0] (RW)
- *
- * The FCCOB register provides a command code and relevant parameters to the
- * memory controller. The individual registers that compose the FCCOB data set can
- * be written in any order, but you must provide all needed values, which vary
- * from command to command. First, set up all required FCCOB fields and then
- * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
- * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
- * by the user until the command completes (CCIF returns to 1). No command
- * buffering or queueing is provided; the next command can be loaded only after the
- * current command completes. Some commands return information to the FCCOB
- * registers. Any values returned to FCCOB are available for reading after the
- * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
- * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
- * the command code. This 8-bit value defines the command to be executed. The
- * command code is followed by the parameters required for this specific FTFE command,
- * typically an address and/or data values. The command parameter table is
- * written in terms of FCCOB Number (which is equivalent to the byte number). This
- * number is a reference to the FCCOB register name and is not the register address.
- * FCCOB NumberRefers to FCCOB register name, not register address Typical
- * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
- * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
- * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
- * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
- * register group uses a big endian addressing convention. For all command parameter
- * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
- * register number. The FCCOB register group may be read and written as
- * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
- */
-//@{
-#define BP_FTFE_FCCOB0_CCOBn (0U) //!< Bit position for FTFE_FCCOB0_CCOBn.
-#define BM_FTFE_FCCOB0_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB0_CCOBn.
-#define BS_FTFE_FCCOB0_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB0_CCOBn.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FCCOB0_CCOBn field.
-#define BR_FTFE_FCCOB0_CCOBn (HW_FTFE_FCCOB0.U)
-#endif
-
-//! @brief Format value for bitfield FTFE_FCCOB0_CCOBn.
-#define BF_FTFE_FCCOB0_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB0_CCOBn), uint8_t) & BM_FTFE_FCCOB0_CCOBn)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CCOBn field to a new value.
-#define BW_FTFE_FCCOB0_CCOBn(v) (HW_FTFE_FCCOB0_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTFE_FCCOB7 - Flash Common Command Object Registers
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTFE_FCCOB7 - Flash Common Command Object Registers (RW)
- *
- * Reset value: 0x00U
- *
- * The FCCOB register group provides 12 bytes for command codes and parameters.
- * The individual bytes within the set append a 0-B hex identifier to the FCCOB
- * register name: FCCOB0, FCCOB1, ..., FCCOBB.
- */
-typedef union _hw_ftfe_fccob7
-{
- uint8_t U;
- struct _hw_ftfe_fccob7_bitfields
- {
- uint8_t CCOBn : 8; //!< [7:0]
- } B;
-} hw_ftfe_fccob7_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTFE_FCCOB7 register
- */
-//@{
-#define HW_FTFE_FCCOB7_ADDR (REGS_FTFE_BASE + 0x8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTFE_FCCOB7 (*(__IO hw_ftfe_fccob7_t *) HW_FTFE_FCCOB7_ADDR)
-#define HW_FTFE_FCCOB7_RD() (HW_FTFE_FCCOB7.U)
-#define HW_FTFE_FCCOB7_WR(v) (HW_FTFE_FCCOB7.U = (v))
-#define HW_FTFE_FCCOB7_SET(v) (HW_FTFE_FCCOB7_WR(HW_FTFE_FCCOB7_RD() | (v)))
-#define HW_FTFE_FCCOB7_CLR(v) (HW_FTFE_FCCOB7_WR(HW_FTFE_FCCOB7_RD() & ~(v)))
-#define HW_FTFE_FCCOB7_TOG(v) (HW_FTFE_FCCOB7_WR(HW_FTFE_FCCOB7_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTFE_FCCOB7 bitfields
- */
-
-/*!
- * @name Register FTFE_FCCOB7, field CCOBn[7:0] (RW)
- *
- * The FCCOB register provides a command code and relevant parameters to the
- * memory controller. The individual registers that compose the FCCOB data set can
- * be written in any order, but you must provide all needed values, which vary
- * from command to command. First, set up all required FCCOB fields and then
- * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
- * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
- * by the user until the command completes (CCIF returns to 1). No command
- * buffering or queueing is provided; the next command can be loaded only after the
- * current command completes. Some commands return information to the FCCOB
- * registers. Any values returned to FCCOB are available for reading after the
- * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
- * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
- * the command code. This 8-bit value defines the command to be executed. The
- * command code is followed by the parameters required for this specific FTFE command,
- * typically an address and/or data values. The command parameter table is
- * written in terms of FCCOB Number (which is equivalent to the byte number). This
- * number is a reference to the FCCOB register name and is not the register address.
- * FCCOB NumberRefers to FCCOB register name, not register address Typical
- * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
- * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
- * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
- * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
- * register group uses a big endian addressing convention. For all command parameter
- * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
- * register number. The FCCOB register group may be read and written as
- * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
- */
-//@{
-#define BP_FTFE_FCCOB7_CCOBn (0U) //!< Bit position for FTFE_FCCOB7_CCOBn.
-#define BM_FTFE_FCCOB7_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB7_CCOBn.
-#define BS_FTFE_FCCOB7_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB7_CCOBn.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FCCOB7_CCOBn field.
-#define BR_FTFE_FCCOB7_CCOBn (HW_FTFE_FCCOB7.U)
-#endif
-
-//! @brief Format value for bitfield FTFE_FCCOB7_CCOBn.
-#define BF_FTFE_FCCOB7_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB7_CCOBn), uint8_t) & BM_FTFE_FCCOB7_CCOBn)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CCOBn field to a new value.
-#define BW_FTFE_FCCOB7_CCOBn(v) (HW_FTFE_FCCOB7_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTFE_FCCOB6 - Flash Common Command Object Registers
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTFE_FCCOB6 - Flash Common Command Object Registers (RW)
- *
- * Reset value: 0x00U
- *
- * The FCCOB register group provides 12 bytes for command codes and parameters.
- * The individual bytes within the set append a 0-B hex identifier to the FCCOB
- * register name: FCCOB0, FCCOB1, ..., FCCOBB.
- */
-typedef union _hw_ftfe_fccob6
-{
- uint8_t U;
- struct _hw_ftfe_fccob6_bitfields
- {
- uint8_t CCOBn : 8; //!< [7:0]
- } B;
-} hw_ftfe_fccob6_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTFE_FCCOB6 register
- */
-//@{
-#define HW_FTFE_FCCOB6_ADDR (REGS_FTFE_BASE + 0x9U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTFE_FCCOB6 (*(__IO hw_ftfe_fccob6_t *) HW_FTFE_FCCOB6_ADDR)
-#define HW_FTFE_FCCOB6_RD() (HW_FTFE_FCCOB6.U)
-#define HW_FTFE_FCCOB6_WR(v) (HW_FTFE_FCCOB6.U = (v))
-#define HW_FTFE_FCCOB6_SET(v) (HW_FTFE_FCCOB6_WR(HW_FTFE_FCCOB6_RD() | (v)))
-#define HW_FTFE_FCCOB6_CLR(v) (HW_FTFE_FCCOB6_WR(HW_FTFE_FCCOB6_RD() & ~(v)))
-#define HW_FTFE_FCCOB6_TOG(v) (HW_FTFE_FCCOB6_WR(HW_FTFE_FCCOB6_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTFE_FCCOB6 bitfields
- */
-
-/*!
- * @name Register FTFE_FCCOB6, field CCOBn[7:0] (RW)
- *
- * The FCCOB register provides a command code and relevant parameters to the
- * memory controller. The individual registers that compose the FCCOB data set can
- * be written in any order, but you must provide all needed values, which vary
- * from command to command. First, set up all required FCCOB fields and then
- * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
- * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
- * by the user until the command completes (CCIF returns to 1). No command
- * buffering or queueing is provided; the next command can be loaded only after the
- * current command completes. Some commands return information to the FCCOB
- * registers. Any values returned to FCCOB are available for reading after the
- * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
- * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
- * the command code. This 8-bit value defines the command to be executed. The
- * command code is followed by the parameters required for this specific FTFE command,
- * typically an address and/or data values. The command parameter table is
- * written in terms of FCCOB Number (which is equivalent to the byte number). This
- * number is a reference to the FCCOB register name and is not the register address.
- * FCCOB NumberRefers to FCCOB register name, not register address Typical
- * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
- * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
- * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
- * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
- * register group uses a big endian addressing convention. For all command parameter
- * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
- * register number. The FCCOB register group may be read and written as
- * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
- */
-//@{
-#define BP_FTFE_FCCOB6_CCOBn (0U) //!< Bit position for FTFE_FCCOB6_CCOBn.
-#define BM_FTFE_FCCOB6_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB6_CCOBn.
-#define BS_FTFE_FCCOB6_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB6_CCOBn.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FCCOB6_CCOBn field.
-#define BR_FTFE_FCCOB6_CCOBn (HW_FTFE_FCCOB6.U)
-#endif
-
-//! @brief Format value for bitfield FTFE_FCCOB6_CCOBn.
-#define BF_FTFE_FCCOB6_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB6_CCOBn), uint8_t) & BM_FTFE_FCCOB6_CCOBn)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CCOBn field to a new value.
-#define BW_FTFE_FCCOB6_CCOBn(v) (HW_FTFE_FCCOB6_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTFE_FCCOB5 - Flash Common Command Object Registers
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTFE_FCCOB5 - Flash Common Command Object Registers (RW)
- *
- * Reset value: 0x00U
- *
- * The FCCOB register group provides 12 bytes for command codes and parameters.
- * The individual bytes within the set append a 0-B hex identifier to the FCCOB
- * register name: FCCOB0, FCCOB1, ..., FCCOBB.
- */
-typedef union _hw_ftfe_fccob5
-{
- uint8_t U;
- struct _hw_ftfe_fccob5_bitfields
- {
- uint8_t CCOBn : 8; //!< [7:0]
- } B;
-} hw_ftfe_fccob5_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTFE_FCCOB5 register
- */
-//@{
-#define HW_FTFE_FCCOB5_ADDR (REGS_FTFE_BASE + 0xAU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTFE_FCCOB5 (*(__IO hw_ftfe_fccob5_t *) HW_FTFE_FCCOB5_ADDR)
-#define HW_FTFE_FCCOB5_RD() (HW_FTFE_FCCOB5.U)
-#define HW_FTFE_FCCOB5_WR(v) (HW_FTFE_FCCOB5.U = (v))
-#define HW_FTFE_FCCOB5_SET(v) (HW_FTFE_FCCOB5_WR(HW_FTFE_FCCOB5_RD() | (v)))
-#define HW_FTFE_FCCOB5_CLR(v) (HW_FTFE_FCCOB5_WR(HW_FTFE_FCCOB5_RD() & ~(v)))
-#define HW_FTFE_FCCOB5_TOG(v) (HW_FTFE_FCCOB5_WR(HW_FTFE_FCCOB5_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTFE_FCCOB5 bitfields
- */
-
-/*!
- * @name Register FTFE_FCCOB5, field CCOBn[7:0] (RW)
- *
- * The FCCOB register provides a command code and relevant parameters to the
- * memory controller. The individual registers that compose the FCCOB data set can
- * be written in any order, but you must provide all needed values, which vary
- * from command to command. First, set up all required FCCOB fields and then
- * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
- * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
- * by the user until the command completes (CCIF returns to 1). No command
- * buffering or queueing is provided; the next command can be loaded only after the
- * current command completes. Some commands return information to the FCCOB
- * registers. Any values returned to FCCOB are available for reading after the
- * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
- * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
- * the command code. This 8-bit value defines the command to be executed. The
- * command code is followed by the parameters required for this specific FTFE command,
- * typically an address and/or data values. The command parameter table is
- * written in terms of FCCOB Number (which is equivalent to the byte number). This
- * number is a reference to the FCCOB register name and is not the register address.
- * FCCOB NumberRefers to FCCOB register name, not register address Typical
- * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
- * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
- * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
- * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
- * register group uses a big endian addressing convention. For all command parameter
- * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
- * register number. The FCCOB register group may be read and written as
- * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
- */
-//@{
-#define BP_FTFE_FCCOB5_CCOBn (0U) //!< Bit position for FTFE_FCCOB5_CCOBn.
-#define BM_FTFE_FCCOB5_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB5_CCOBn.
-#define BS_FTFE_FCCOB5_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB5_CCOBn.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FCCOB5_CCOBn field.
-#define BR_FTFE_FCCOB5_CCOBn (HW_FTFE_FCCOB5.U)
-#endif
-
-//! @brief Format value for bitfield FTFE_FCCOB5_CCOBn.
-#define BF_FTFE_FCCOB5_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB5_CCOBn), uint8_t) & BM_FTFE_FCCOB5_CCOBn)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CCOBn field to a new value.
-#define BW_FTFE_FCCOB5_CCOBn(v) (HW_FTFE_FCCOB5_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTFE_FCCOB4 - Flash Common Command Object Registers
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTFE_FCCOB4 - Flash Common Command Object Registers (RW)
- *
- * Reset value: 0x00U
- *
- * The FCCOB register group provides 12 bytes for command codes and parameters.
- * The individual bytes within the set append a 0-B hex identifier to the FCCOB
- * register name: FCCOB0, FCCOB1, ..., FCCOBB.
- */
-typedef union _hw_ftfe_fccob4
-{
- uint8_t U;
- struct _hw_ftfe_fccob4_bitfields
- {
- uint8_t CCOBn : 8; //!< [7:0]
- } B;
-} hw_ftfe_fccob4_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTFE_FCCOB4 register
- */
-//@{
-#define HW_FTFE_FCCOB4_ADDR (REGS_FTFE_BASE + 0xBU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTFE_FCCOB4 (*(__IO hw_ftfe_fccob4_t *) HW_FTFE_FCCOB4_ADDR)
-#define HW_FTFE_FCCOB4_RD() (HW_FTFE_FCCOB4.U)
-#define HW_FTFE_FCCOB4_WR(v) (HW_FTFE_FCCOB4.U = (v))
-#define HW_FTFE_FCCOB4_SET(v) (HW_FTFE_FCCOB4_WR(HW_FTFE_FCCOB4_RD() | (v)))
-#define HW_FTFE_FCCOB4_CLR(v) (HW_FTFE_FCCOB4_WR(HW_FTFE_FCCOB4_RD() & ~(v)))
-#define HW_FTFE_FCCOB4_TOG(v) (HW_FTFE_FCCOB4_WR(HW_FTFE_FCCOB4_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTFE_FCCOB4 bitfields
- */
-
-/*!
- * @name Register FTFE_FCCOB4, field CCOBn[7:0] (RW)
- *
- * The FCCOB register provides a command code and relevant parameters to the
- * memory controller. The individual registers that compose the FCCOB data set can
- * be written in any order, but you must provide all needed values, which vary
- * from command to command. First, set up all required FCCOB fields and then
- * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
- * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
- * by the user until the command completes (CCIF returns to 1). No command
- * buffering or queueing is provided; the next command can be loaded only after the
- * current command completes. Some commands return information to the FCCOB
- * registers. Any values returned to FCCOB are available for reading after the
- * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
- * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
- * the command code. This 8-bit value defines the command to be executed. The
- * command code is followed by the parameters required for this specific FTFE command,
- * typically an address and/or data values. The command parameter table is
- * written in terms of FCCOB Number (which is equivalent to the byte number). This
- * number is a reference to the FCCOB register name and is not the register address.
- * FCCOB NumberRefers to FCCOB register name, not register address Typical
- * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
- * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
- * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
- * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
- * register group uses a big endian addressing convention. For all command parameter
- * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
- * register number. The FCCOB register group may be read and written as
- * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
- */
-//@{
-#define BP_FTFE_FCCOB4_CCOBn (0U) //!< Bit position for FTFE_FCCOB4_CCOBn.
-#define BM_FTFE_FCCOB4_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB4_CCOBn.
-#define BS_FTFE_FCCOB4_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB4_CCOBn.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FCCOB4_CCOBn field.
-#define BR_FTFE_FCCOB4_CCOBn (HW_FTFE_FCCOB4.U)
-#endif
-
-//! @brief Format value for bitfield FTFE_FCCOB4_CCOBn.
-#define BF_FTFE_FCCOB4_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB4_CCOBn), uint8_t) & BM_FTFE_FCCOB4_CCOBn)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CCOBn field to a new value.
-#define BW_FTFE_FCCOB4_CCOBn(v) (HW_FTFE_FCCOB4_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTFE_FCCOBB - Flash Common Command Object Registers
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTFE_FCCOBB - Flash Common Command Object Registers (RW)
- *
- * Reset value: 0x00U
- *
- * The FCCOB register group provides 12 bytes for command codes and parameters.
- * The individual bytes within the set append a 0-B hex identifier to the FCCOB
- * register name: FCCOB0, FCCOB1, ..., FCCOBB.
- */
-typedef union _hw_ftfe_fccobb
-{
- uint8_t U;
- struct _hw_ftfe_fccobb_bitfields
- {
- uint8_t CCOBn : 8; //!< [7:0]
- } B;
-} hw_ftfe_fccobb_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTFE_FCCOBB register
- */
-//@{
-#define HW_FTFE_FCCOBB_ADDR (REGS_FTFE_BASE + 0xCU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTFE_FCCOBB (*(__IO hw_ftfe_fccobb_t *) HW_FTFE_FCCOBB_ADDR)
-#define HW_FTFE_FCCOBB_RD() (HW_FTFE_FCCOBB.U)
-#define HW_FTFE_FCCOBB_WR(v) (HW_FTFE_FCCOBB.U = (v))
-#define HW_FTFE_FCCOBB_SET(v) (HW_FTFE_FCCOBB_WR(HW_FTFE_FCCOBB_RD() | (v)))
-#define HW_FTFE_FCCOBB_CLR(v) (HW_FTFE_FCCOBB_WR(HW_FTFE_FCCOBB_RD() & ~(v)))
-#define HW_FTFE_FCCOBB_TOG(v) (HW_FTFE_FCCOBB_WR(HW_FTFE_FCCOBB_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTFE_FCCOBB bitfields
- */
-
-/*!
- * @name Register FTFE_FCCOBB, field CCOBn[7:0] (RW)
- *
- * The FCCOB register provides a command code and relevant parameters to the
- * memory controller. The individual registers that compose the FCCOB data set can
- * be written in any order, but you must provide all needed values, which vary
- * from command to command. First, set up all required FCCOB fields and then
- * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
- * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
- * by the user until the command completes (CCIF returns to 1). No command
- * buffering or queueing is provided; the next command can be loaded only after the
- * current command completes. Some commands return information to the FCCOB
- * registers. Any values returned to FCCOB are available for reading after the
- * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
- * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
- * the command code. This 8-bit value defines the command to be executed. The
- * command code is followed by the parameters required for this specific FTFE command,
- * typically an address and/or data values. The command parameter table is
- * written in terms of FCCOB Number (which is equivalent to the byte number). This
- * number is a reference to the FCCOB register name and is not the register address.
- * FCCOB NumberRefers to FCCOB register name, not register address Typical
- * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
- * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
- * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
- * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
- * register group uses a big endian addressing convention. For all command parameter
- * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
- * register number. The FCCOB register group may be read and written as
- * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
- */
-//@{
-#define BP_FTFE_FCCOBB_CCOBn (0U) //!< Bit position for FTFE_FCCOBB_CCOBn.
-#define BM_FTFE_FCCOBB_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOBB_CCOBn.
-#define BS_FTFE_FCCOBB_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOBB_CCOBn.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FCCOBB_CCOBn field.
-#define BR_FTFE_FCCOBB_CCOBn (HW_FTFE_FCCOBB.U)
-#endif
-
-//! @brief Format value for bitfield FTFE_FCCOBB_CCOBn.
-#define BF_FTFE_FCCOBB_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOBB_CCOBn), uint8_t) & BM_FTFE_FCCOBB_CCOBn)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CCOBn field to a new value.
-#define BW_FTFE_FCCOBB_CCOBn(v) (HW_FTFE_FCCOBB_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTFE_FCCOBA - Flash Common Command Object Registers
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTFE_FCCOBA - Flash Common Command Object Registers (RW)
- *
- * Reset value: 0x00U
- *
- * The FCCOB register group provides 12 bytes for command codes and parameters.
- * The individual bytes within the set append a 0-B hex identifier to the FCCOB
- * register name: FCCOB0, FCCOB1, ..., FCCOBB.
- */
-typedef union _hw_ftfe_fccoba
-{
- uint8_t U;
- struct _hw_ftfe_fccoba_bitfields
- {
- uint8_t CCOBn : 8; //!< [7:0]
- } B;
-} hw_ftfe_fccoba_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTFE_FCCOBA register
- */
-//@{
-#define HW_FTFE_FCCOBA_ADDR (REGS_FTFE_BASE + 0xDU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTFE_FCCOBA (*(__IO hw_ftfe_fccoba_t *) HW_FTFE_FCCOBA_ADDR)
-#define HW_FTFE_FCCOBA_RD() (HW_FTFE_FCCOBA.U)
-#define HW_FTFE_FCCOBA_WR(v) (HW_FTFE_FCCOBA.U = (v))
-#define HW_FTFE_FCCOBA_SET(v) (HW_FTFE_FCCOBA_WR(HW_FTFE_FCCOBA_RD() | (v)))
-#define HW_FTFE_FCCOBA_CLR(v) (HW_FTFE_FCCOBA_WR(HW_FTFE_FCCOBA_RD() & ~(v)))
-#define HW_FTFE_FCCOBA_TOG(v) (HW_FTFE_FCCOBA_WR(HW_FTFE_FCCOBA_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTFE_FCCOBA bitfields
- */
-
-/*!
- * @name Register FTFE_FCCOBA, field CCOBn[7:0] (RW)
- *
- * The FCCOB register provides a command code and relevant parameters to the
- * memory controller. The individual registers that compose the FCCOB data set can
- * be written in any order, but you must provide all needed values, which vary
- * from command to command. First, set up all required FCCOB fields and then
- * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
- * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
- * by the user until the command completes (CCIF returns to 1). No command
- * buffering or queueing is provided; the next command can be loaded only after the
- * current command completes. Some commands return information to the FCCOB
- * registers. Any values returned to FCCOB are available for reading after the
- * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
- * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
- * the command code. This 8-bit value defines the command to be executed. The
- * command code is followed by the parameters required for this specific FTFE command,
- * typically an address and/or data values. The command parameter table is
- * written in terms of FCCOB Number (which is equivalent to the byte number). This
- * number is a reference to the FCCOB register name and is not the register address.
- * FCCOB NumberRefers to FCCOB register name, not register address Typical
- * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
- * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
- * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
- * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
- * register group uses a big endian addressing convention. For all command parameter
- * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
- * register number. The FCCOB register group may be read and written as
- * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
- */
-//@{
-#define BP_FTFE_FCCOBA_CCOBn (0U) //!< Bit position for FTFE_FCCOBA_CCOBn.
-#define BM_FTFE_FCCOBA_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOBA_CCOBn.
-#define BS_FTFE_FCCOBA_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOBA_CCOBn.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FCCOBA_CCOBn field.
-#define BR_FTFE_FCCOBA_CCOBn (HW_FTFE_FCCOBA.U)
-#endif
-
-//! @brief Format value for bitfield FTFE_FCCOBA_CCOBn.
-#define BF_FTFE_FCCOBA_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOBA_CCOBn), uint8_t) & BM_FTFE_FCCOBA_CCOBn)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CCOBn field to a new value.
-#define BW_FTFE_FCCOBA_CCOBn(v) (HW_FTFE_FCCOBA_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTFE_FCCOB9 - Flash Common Command Object Registers
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTFE_FCCOB9 - Flash Common Command Object Registers (RW)
- *
- * Reset value: 0x00U
- *
- * The FCCOB register group provides 12 bytes for command codes and parameters.
- * The individual bytes within the set append a 0-B hex identifier to the FCCOB
- * register name: FCCOB0, FCCOB1, ..., FCCOBB.
- */
-typedef union _hw_ftfe_fccob9
-{
- uint8_t U;
- struct _hw_ftfe_fccob9_bitfields
- {
- uint8_t CCOBn : 8; //!< [7:0]
- } B;
-} hw_ftfe_fccob9_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTFE_FCCOB9 register
- */
-//@{
-#define HW_FTFE_FCCOB9_ADDR (REGS_FTFE_BASE + 0xEU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTFE_FCCOB9 (*(__IO hw_ftfe_fccob9_t *) HW_FTFE_FCCOB9_ADDR)
-#define HW_FTFE_FCCOB9_RD() (HW_FTFE_FCCOB9.U)
-#define HW_FTFE_FCCOB9_WR(v) (HW_FTFE_FCCOB9.U = (v))
-#define HW_FTFE_FCCOB9_SET(v) (HW_FTFE_FCCOB9_WR(HW_FTFE_FCCOB9_RD() | (v)))
-#define HW_FTFE_FCCOB9_CLR(v) (HW_FTFE_FCCOB9_WR(HW_FTFE_FCCOB9_RD() & ~(v)))
-#define HW_FTFE_FCCOB9_TOG(v) (HW_FTFE_FCCOB9_WR(HW_FTFE_FCCOB9_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTFE_FCCOB9 bitfields
- */
-
-/*!
- * @name Register FTFE_FCCOB9, field CCOBn[7:0] (RW)
- *
- * The FCCOB register provides a command code and relevant parameters to the
- * memory controller. The individual registers that compose the FCCOB data set can
- * be written in any order, but you must provide all needed values, which vary
- * from command to command. First, set up all required FCCOB fields and then
- * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
- * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
- * by the user until the command completes (CCIF returns to 1). No command
- * buffering or queueing is provided; the next command can be loaded only after the
- * current command completes. Some commands return information to the FCCOB
- * registers. Any values returned to FCCOB are available for reading after the
- * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
- * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
- * the command code. This 8-bit value defines the command to be executed. The
- * command code is followed by the parameters required for this specific FTFE command,
- * typically an address and/or data values. The command parameter table is
- * written in terms of FCCOB Number (which is equivalent to the byte number). This
- * number is a reference to the FCCOB register name and is not the register address.
- * FCCOB NumberRefers to FCCOB register name, not register address Typical
- * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
- * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
- * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
- * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
- * register group uses a big endian addressing convention. For all command parameter
- * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
- * register number. The FCCOB register group may be read and written as
- * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
- */
-//@{
-#define BP_FTFE_FCCOB9_CCOBn (0U) //!< Bit position for FTFE_FCCOB9_CCOBn.
-#define BM_FTFE_FCCOB9_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB9_CCOBn.
-#define BS_FTFE_FCCOB9_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB9_CCOBn.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FCCOB9_CCOBn field.
-#define BR_FTFE_FCCOB9_CCOBn (HW_FTFE_FCCOB9.U)
-#endif
-
-//! @brief Format value for bitfield FTFE_FCCOB9_CCOBn.
-#define BF_FTFE_FCCOB9_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB9_CCOBn), uint8_t) & BM_FTFE_FCCOB9_CCOBn)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CCOBn field to a new value.
-#define BW_FTFE_FCCOB9_CCOBn(v) (HW_FTFE_FCCOB9_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTFE_FCCOB8 - Flash Common Command Object Registers
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTFE_FCCOB8 - Flash Common Command Object Registers (RW)
- *
- * Reset value: 0x00U
- *
- * The FCCOB register group provides 12 bytes for command codes and parameters.
- * The individual bytes within the set append a 0-B hex identifier to the FCCOB
- * register name: FCCOB0, FCCOB1, ..., FCCOBB.
- */
-typedef union _hw_ftfe_fccob8
-{
- uint8_t U;
- struct _hw_ftfe_fccob8_bitfields
- {
- uint8_t CCOBn : 8; //!< [7:0]
- } B;
-} hw_ftfe_fccob8_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTFE_FCCOB8 register
- */
-//@{
-#define HW_FTFE_FCCOB8_ADDR (REGS_FTFE_BASE + 0xFU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTFE_FCCOB8 (*(__IO hw_ftfe_fccob8_t *) HW_FTFE_FCCOB8_ADDR)
-#define HW_FTFE_FCCOB8_RD() (HW_FTFE_FCCOB8.U)
-#define HW_FTFE_FCCOB8_WR(v) (HW_FTFE_FCCOB8.U = (v))
-#define HW_FTFE_FCCOB8_SET(v) (HW_FTFE_FCCOB8_WR(HW_FTFE_FCCOB8_RD() | (v)))
-#define HW_FTFE_FCCOB8_CLR(v) (HW_FTFE_FCCOB8_WR(HW_FTFE_FCCOB8_RD() & ~(v)))
-#define HW_FTFE_FCCOB8_TOG(v) (HW_FTFE_FCCOB8_WR(HW_FTFE_FCCOB8_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTFE_FCCOB8 bitfields
- */
-
-/*!
- * @name Register FTFE_FCCOB8, field CCOBn[7:0] (RW)
- *
- * The FCCOB register provides a command code and relevant parameters to the
- * memory controller. The individual registers that compose the FCCOB data set can
- * be written in any order, but you must provide all needed values, which vary
- * from command to command. First, set up all required FCCOB fields and then
- * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
- * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
- * by the user until the command completes (CCIF returns to 1). No command
- * buffering or queueing is provided; the next command can be loaded only after the
- * current command completes. Some commands return information to the FCCOB
- * registers. Any values returned to FCCOB are available for reading after the
- * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
- * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
- * the command code. This 8-bit value defines the command to be executed. The
- * command code is followed by the parameters required for this specific FTFE command,
- * typically an address and/or data values. The command parameter table is
- * written in terms of FCCOB Number (which is equivalent to the byte number). This
- * number is a reference to the FCCOB register name and is not the register address.
- * FCCOB NumberRefers to FCCOB register name, not register address Typical
- * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
- * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
- * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
- * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
- * register group uses a big endian addressing convention. For all command parameter
- * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
- * register number. The FCCOB register group may be read and written as
- * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
- */
-//@{
-#define BP_FTFE_FCCOB8_CCOBn (0U) //!< Bit position for FTFE_FCCOB8_CCOBn.
-#define BM_FTFE_FCCOB8_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB8_CCOBn.
-#define BS_FTFE_FCCOB8_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB8_CCOBn.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FCCOB8_CCOBn field.
-#define BR_FTFE_FCCOB8_CCOBn (HW_FTFE_FCCOB8.U)
-#endif
-
-//! @brief Format value for bitfield FTFE_FCCOB8_CCOBn.
-#define BF_FTFE_FCCOB8_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB8_CCOBn), uint8_t) & BM_FTFE_FCCOB8_CCOBn)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CCOBn field to a new value.
-#define BW_FTFE_FCCOB8_CCOBn(v) (HW_FTFE_FCCOB8_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTFE_FPROT3 - Program Flash Protection Registers
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTFE_FPROT3 - Program Flash Protection Registers (RW)
- *
- * Reset value: 0x00U
- *
- * The FPROT registers define which program flash regions are protected from
- * program and erase operations. Protected flash regions cannot have their content
- * changed; that is, these regions cannot be programmed and cannot be erased by
- * any FTFE command. Unprotected regions can be changed by program and erase
- * operations. The four FPROT registers allow up to 32 protectable regions of equal
- * memory size. Program flash protection register Program flash protection bits
- * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
- * the reset sequence, the FPROT registers are loaded with the contents of the
- * program flash protection bytes in the Flash Configuration Field as indicated in
- * the following table. Program flash protection register Flash Configuration Field
- * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
- * change the program flash protection that is loaded during the reset sequence,
- * unprotect the sector of program flash memory that contains the Flash
- * Configuration Field. Then, reprogram the program flash protection byte.
- */
-typedef union _hw_ftfe_fprot3
-{
- uint8_t U;
- struct _hw_ftfe_fprot3_bitfields
- {
- uint8_t PROT : 8; //!< [7:0] Program Flash Region Protect
- } B;
-} hw_ftfe_fprot3_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTFE_FPROT3 register
- */
-//@{
-#define HW_FTFE_FPROT3_ADDR (REGS_FTFE_BASE + 0x10U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTFE_FPROT3 (*(__IO hw_ftfe_fprot3_t *) HW_FTFE_FPROT3_ADDR)
-#define HW_FTFE_FPROT3_RD() (HW_FTFE_FPROT3.U)
-#define HW_FTFE_FPROT3_WR(v) (HW_FTFE_FPROT3.U = (v))
-#define HW_FTFE_FPROT3_SET(v) (HW_FTFE_FPROT3_WR(HW_FTFE_FPROT3_RD() | (v)))
-#define HW_FTFE_FPROT3_CLR(v) (HW_FTFE_FPROT3_WR(HW_FTFE_FPROT3_RD() & ~(v)))
-#define HW_FTFE_FPROT3_TOG(v) (HW_FTFE_FPROT3_WR(HW_FTFE_FPROT3_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTFE_FPROT3 bitfields
- */
-
-/*!
- * @name Register FTFE_FPROT3, field PROT[7:0] (RW)
- *
- * Each program flash region can be protected from program and erase operations
- * by setting the associated PROT bit. In NVM Normal mode: The protection can
- * only be increased, meaning that currently unprotected memory can be protected,
- * but currently protected memory cannot be unprotected. Since unprotected regions
- * are marked with a 1 and protected regions use a 0, only writes changing 1s to
- * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
- * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
- * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
- * writable without restriction. Unprotected areas can be protected and protected
- * areas can be unprotected. The user must never write to any FPROT register while
- * a command is running (CCIF=0). Trying to alter data in any protected area in
- * the program flash memory results in a protection violation error and sets the
- * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
- * if it contains any protected region.
- *
- * Values:
- * - 0 - Program flash region is protected.
- * - 1 - Program flash region is not protected
- */
-//@{
-#define BP_FTFE_FPROT3_PROT (0U) //!< Bit position for FTFE_FPROT3_PROT.
-#define BM_FTFE_FPROT3_PROT (0xFFU) //!< Bit mask for FTFE_FPROT3_PROT.
-#define BS_FTFE_FPROT3_PROT (8U) //!< Bit field size in bits for FTFE_FPROT3_PROT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FPROT3_PROT field.
-#define BR_FTFE_FPROT3_PROT (HW_FTFE_FPROT3.U)
-#endif
-
-//! @brief Format value for bitfield FTFE_FPROT3_PROT.
-#define BF_FTFE_FPROT3_PROT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FPROT3_PROT), uint8_t) & BM_FTFE_FPROT3_PROT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PROT field to a new value.
-#define BW_FTFE_FPROT3_PROT(v) (HW_FTFE_FPROT3_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTFE_FPROT2 - Program Flash Protection Registers
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTFE_FPROT2 - Program Flash Protection Registers (RW)
- *
- * Reset value: 0x00U
- *
- * The FPROT registers define which program flash regions are protected from
- * program and erase operations. Protected flash regions cannot have their content
- * changed; that is, these regions cannot be programmed and cannot be erased by
- * any FTFE command. Unprotected regions can be changed by program and erase
- * operations. The four FPROT registers allow up to 32 protectable regions of equal
- * memory size. Program flash protection register Program flash protection bits
- * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
- * the reset sequence, the FPROT registers are loaded with the contents of the
- * program flash protection bytes in the Flash Configuration Field as indicated in
- * the following table. Program flash protection register Flash Configuration Field
- * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
- * change the program flash protection that is loaded during the reset sequence,
- * unprotect the sector of program flash memory that contains the Flash
- * Configuration Field. Then, reprogram the program flash protection byte.
- */
-typedef union _hw_ftfe_fprot2
-{
- uint8_t U;
- struct _hw_ftfe_fprot2_bitfields
- {
- uint8_t PROT : 8; //!< [7:0] Program Flash Region Protect
- } B;
-} hw_ftfe_fprot2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTFE_FPROT2 register
- */
-//@{
-#define HW_FTFE_FPROT2_ADDR (REGS_FTFE_BASE + 0x11U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTFE_FPROT2 (*(__IO hw_ftfe_fprot2_t *) HW_FTFE_FPROT2_ADDR)
-#define HW_FTFE_FPROT2_RD() (HW_FTFE_FPROT2.U)
-#define HW_FTFE_FPROT2_WR(v) (HW_FTFE_FPROT2.U = (v))
-#define HW_FTFE_FPROT2_SET(v) (HW_FTFE_FPROT2_WR(HW_FTFE_FPROT2_RD() | (v)))
-#define HW_FTFE_FPROT2_CLR(v) (HW_FTFE_FPROT2_WR(HW_FTFE_FPROT2_RD() & ~(v)))
-#define HW_FTFE_FPROT2_TOG(v) (HW_FTFE_FPROT2_WR(HW_FTFE_FPROT2_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTFE_FPROT2 bitfields
- */
-
-/*!
- * @name Register FTFE_FPROT2, field PROT[7:0] (RW)
- *
- * Each program flash region can be protected from program and erase operations
- * by setting the associated PROT bit. In NVM Normal mode: The protection can
- * only be increased, meaning that currently unprotected memory can be protected,
- * but currently protected memory cannot be unprotected. Since unprotected regions
- * are marked with a 1 and protected regions use a 0, only writes changing 1s to
- * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
- * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
- * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
- * writable without restriction. Unprotected areas can be protected and protected
- * areas can be unprotected. The user must never write to any FPROT register while
- * a command is running (CCIF=0). Trying to alter data in any protected area in
- * the program flash memory results in a protection violation error and sets the
- * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
- * if it contains any protected region.
- *
- * Values:
- * - 0 - Program flash region is protected.
- * - 1 - Program flash region is not protected
- */
-//@{
-#define BP_FTFE_FPROT2_PROT (0U) //!< Bit position for FTFE_FPROT2_PROT.
-#define BM_FTFE_FPROT2_PROT (0xFFU) //!< Bit mask for FTFE_FPROT2_PROT.
-#define BS_FTFE_FPROT2_PROT (8U) //!< Bit field size in bits for FTFE_FPROT2_PROT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FPROT2_PROT field.
-#define BR_FTFE_FPROT2_PROT (HW_FTFE_FPROT2.U)
-#endif
-
-//! @brief Format value for bitfield FTFE_FPROT2_PROT.
-#define BF_FTFE_FPROT2_PROT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FPROT2_PROT), uint8_t) & BM_FTFE_FPROT2_PROT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PROT field to a new value.
-#define BW_FTFE_FPROT2_PROT(v) (HW_FTFE_FPROT2_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTFE_FPROT1 - Program Flash Protection Registers
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTFE_FPROT1 - Program Flash Protection Registers (RW)
- *
- * Reset value: 0x00U
- *
- * The FPROT registers define which program flash regions are protected from
- * program and erase operations. Protected flash regions cannot have their content
- * changed; that is, these regions cannot be programmed and cannot be erased by
- * any FTFE command. Unprotected regions can be changed by program and erase
- * operations. The four FPROT registers allow up to 32 protectable regions of equal
- * memory size. Program flash protection register Program flash protection bits
- * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
- * the reset sequence, the FPROT registers are loaded with the contents of the
- * program flash protection bytes in the Flash Configuration Field as indicated in
- * the following table. Program flash protection register Flash Configuration Field
- * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
- * change the program flash protection that is loaded during the reset sequence,
- * unprotect the sector of program flash memory that contains the Flash
- * Configuration Field. Then, reprogram the program flash protection byte.
- */
-typedef union _hw_ftfe_fprot1
-{
- uint8_t U;
- struct _hw_ftfe_fprot1_bitfields
- {
- uint8_t PROT : 8; //!< [7:0] Program Flash Region Protect
- } B;
-} hw_ftfe_fprot1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTFE_FPROT1 register
- */
-//@{
-#define HW_FTFE_FPROT1_ADDR (REGS_FTFE_BASE + 0x12U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTFE_FPROT1 (*(__IO hw_ftfe_fprot1_t *) HW_FTFE_FPROT1_ADDR)
-#define HW_FTFE_FPROT1_RD() (HW_FTFE_FPROT1.U)
-#define HW_FTFE_FPROT1_WR(v) (HW_FTFE_FPROT1.U = (v))
-#define HW_FTFE_FPROT1_SET(v) (HW_FTFE_FPROT1_WR(HW_FTFE_FPROT1_RD() | (v)))
-#define HW_FTFE_FPROT1_CLR(v) (HW_FTFE_FPROT1_WR(HW_FTFE_FPROT1_RD() & ~(v)))
-#define HW_FTFE_FPROT1_TOG(v) (HW_FTFE_FPROT1_WR(HW_FTFE_FPROT1_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTFE_FPROT1 bitfields
- */
-
-/*!
- * @name Register FTFE_FPROT1, field PROT[7:0] (RW)
- *
- * Each program flash region can be protected from program and erase operations
- * by setting the associated PROT bit. In NVM Normal mode: The protection can
- * only be increased, meaning that currently unprotected memory can be protected,
- * but currently protected memory cannot be unprotected. Since unprotected regions
- * are marked with a 1 and protected regions use a 0, only writes changing 1s to
- * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
- * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
- * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
- * writable without restriction. Unprotected areas can be protected and protected
- * areas can be unprotected. The user must never write to any FPROT register while
- * a command is running (CCIF=0). Trying to alter data in any protected area in
- * the program flash memory results in a protection violation error and sets the
- * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
- * if it contains any protected region.
- *
- * Values:
- * - 0 - Program flash region is protected.
- * - 1 - Program flash region is not protected
- */
-//@{
-#define BP_FTFE_FPROT1_PROT (0U) //!< Bit position for FTFE_FPROT1_PROT.
-#define BM_FTFE_FPROT1_PROT (0xFFU) //!< Bit mask for FTFE_FPROT1_PROT.
-#define BS_FTFE_FPROT1_PROT (8U) //!< Bit field size in bits for FTFE_FPROT1_PROT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FPROT1_PROT field.
-#define BR_FTFE_FPROT1_PROT (HW_FTFE_FPROT1.U)
-#endif
-
-//! @brief Format value for bitfield FTFE_FPROT1_PROT.
-#define BF_FTFE_FPROT1_PROT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FPROT1_PROT), uint8_t) & BM_FTFE_FPROT1_PROT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PROT field to a new value.
-#define BW_FTFE_FPROT1_PROT(v) (HW_FTFE_FPROT1_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTFE_FPROT0 - Program Flash Protection Registers
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTFE_FPROT0 - Program Flash Protection Registers (RW)
- *
- * Reset value: 0x00U
- *
- * The FPROT registers define which program flash regions are protected from
- * program and erase operations. Protected flash regions cannot have their content
- * changed; that is, these regions cannot be programmed and cannot be erased by
- * any FTFE command. Unprotected regions can be changed by program and erase
- * operations. The four FPROT registers allow up to 32 protectable regions of equal
- * memory size. Program flash protection register Program flash protection bits
- * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
- * the reset sequence, the FPROT registers are loaded with the contents of the
- * program flash protection bytes in the Flash Configuration Field as indicated in
- * the following table. Program flash protection register Flash Configuration Field
- * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
- * change the program flash protection that is loaded during the reset sequence,
- * unprotect the sector of program flash memory that contains the Flash
- * Configuration Field. Then, reprogram the program flash protection byte.
- */
-typedef union _hw_ftfe_fprot0
-{
- uint8_t U;
- struct _hw_ftfe_fprot0_bitfields
- {
- uint8_t PROT : 8; //!< [7:0] Program Flash Region Protect
- } B;
-} hw_ftfe_fprot0_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTFE_FPROT0 register
- */
-//@{
-#define HW_FTFE_FPROT0_ADDR (REGS_FTFE_BASE + 0x13U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTFE_FPROT0 (*(__IO hw_ftfe_fprot0_t *) HW_FTFE_FPROT0_ADDR)
-#define HW_FTFE_FPROT0_RD() (HW_FTFE_FPROT0.U)
-#define HW_FTFE_FPROT0_WR(v) (HW_FTFE_FPROT0.U = (v))
-#define HW_FTFE_FPROT0_SET(v) (HW_FTFE_FPROT0_WR(HW_FTFE_FPROT0_RD() | (v)))
-#define HW_FTFE_FPROT0_CLR(v) (HW_FTFE_FPROT0_WR(HW_FTFE_FPROT0_RD() & ~(v)))
-#define HW_FTFE_FPROT0_TOG(v) (HW_FTFE_FPROT0_WR(HW_FTFE_FPROT0_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTFE_FPROT0 bitfields
- */
-
-/*!
- * @name Register FTFE_FPROT0, field PROT[7:0] (RW)
- *
- * Each program flash region can be protected from program and erase operations
- * by setting the associated PROT bit. In NVM Normal mode: The protection can
- * only be increased, meaning that currently unprotected memory can be protected,
- * but currently protected memory cannot be unprotected. Since unprotected regions
- * are marked with a 1 and protected regions use a 0, only writes changing 1s to
- * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
- * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
- * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
- * writable without restriction. Unprotected areas can be protected and protected
- * areas can be unprotected. The user must never write to any FPROT register while
- * a command is running (CCIF=0). Trying to alter data in any protected area in
- * the program flash memory results in a protection violation error and sets the
- * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
- * if it contains any protected region.
- *
- * Values:
- * - 0 - Program flash region is protected.
- * - 1 - Program flash region is not protected
- */
-//@{
-#define BP_FTFE_FPROT0_PROT (0U) //!< Bit position for FTFE_FPROT0_PROT.
-#define BM_FTFE_FPROT0_PROT (0xFFU) //!< Bit mask for FTFE_FPROT0_PROT.
-#define BS_FTFE_FPROT0_PROT (8U) //!< Bit field size in bits for FTFE_FPROT0_PROT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FPROT0_PROT field.
-#define BR_FTFE_FPROT0_PROT (HW_FTFE_FPROT0.U)
-#endif
-
-//! @brief Format value for bitfield FTFE_FPROT0_PROT.
-#define BF_FTFE_FPROT0_PROT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FPROT0_PROT), uint8_t) & BM_FTFE_FPROT0_PROT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PROT field to a new value.
-#define BW_FTFE_FPROT0_PROT(v) (HW_FTFE_FPROT0_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTFE_FEPROT - EEPROM Protection Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTFE_FEPROT - EEPROM Protection Register (RW)
- *
- * Reset value: 0x00U
- *
- * For devices with FlexNVM: The FEPROT register defines which EEPROM regions of
- * the FlexRAM are protected against program and erase operations. Protected
- * EEPROM regions cannot have their content changed by writing to it. Unprotected
- * regions can be changed by writing to the FlexRAM. For devices with program flash
- * only: This register is reserved and not used.
- */
-typedef union _hw_ftfe_feprot
-{
- uint8_t U;
- struct _hw_ftfe_feprot_bitfields
- {
- uint8_t EPROT : 8; //!< [7:0] EEPROM Region Protect
- } B;
-} hw_ftfe_feprot_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTFE_FEPROT register
- */
-//@{
-#define HW_FTFE_FEPROT_ADDR (REGS_FTFE_BASE + 0x16U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTFE_FEPROT (*(__IO hw_ftfe_feprot_t *) HW_FTFE_FEPROT_ADDR)
-#define HW_FTFE_FEPROT_RD() (HW_FTFE_FEPROT.U)
-#define HW_FTFE_FEPROT_WR(v) (HW_FTFE_FEPROT.U = (v))
-#define HW_FTFE_FEPROT_SET(v) (HW_FTFE_FEPROT_WR(HW_FTFE_FEPROT_RD() | (v)))
-#define HW_FTFE_FEPROT_CLR(v) (HW_FTFE_FEPROT_WR(HW_FTFE_FEPROT_RD() & ~(v)))
-#define HW_FTFE_FEPROT_TOG(v) (HW_FTFE_FEPROT_WR(HW_FTFE_FEPROT_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTFE_FEPROT bitfields
- */
-
-/*!
- * @name Register FTFE_FEPROT, field EPROT[7:0] (RW)
- *
- * For devices with program flash only: Reserved For devices with FlexNVM:
- * Individual EEPROM regions can be protected from alteration by setting the
- * associated EPROT bit. The EPROT bits are not used when the FlexNVM Partition Code is
- * set to data flash only. When the FlexNVM Partition Code is set to data flash and
- * EEPROM or EEPROM only, each EPROT bit covers one-eighth of the configured
- * EEPROM data (see the EEPROM Data Set Size parameter description). In NVM Normal
- * mode: The protection can only be increased. This means that
- * currently-unprotected memory can be protected, but currently-protected memory cannot be
- * unprotected. Since unprotected regions are marked with a 1 and protected regions use a
- * 0, only writes changing 1s to 0s are accepted. This 1-to-0 transition check is
- * performed on a bit-by-bit basis. Those FEPROT bits with 1-to-0 transitions
- * are accepted while all bits with 0-to-1 transitions are ignored. In NVM Special
- * mode: All bits of the FEPROT register are writable without restriction.
- * Unprotected areas can be protected and protected areas can be unprotected. Never
- * write to the FEPROT register while a command is running (CCIF=0). Reset: During
- * the reset sequence, the FEPROT register is loaded with the contents of the
- * FlexRAM protection byte in the Flash Configuration Field located in program flash.
- * The flash basis for the reset values is signified by X in the register
- * diagram. To change the EEPROM protection that will be loaded during the reset
- * sequence, the sector of program flash that contains the Flash Configuration Field
- * must be unprotected; then the EEPROM protection byte must be erased and
- * reprogrammed. Trying to alter data by writing to any protected area in the EEPROM
- * results in a protection violation error and sets the FSTAT[FPVIOL] bit.
- *
- * Values:
- * - 0 - For devices with program flash only: Reserved For devices with FlexNVM:
- * EEPROM region is protected
- * - 1 - For devices with program flash only: Reserved For devices with FlexNVM:
- * EEPROM region is not protected
- */
-//@{
-#define BP_FTFE_FEPROT_EPROT (0U) //!< Bit position for FTFE_FEPROT_EPROT.
-#define BM_FTFE_FEPROT_EPROT (0xFFU) //!< Bit mask for FTFE_FEPROT_EPROT.
-#define BS_FTFE_FEPROT_EPROT (8U) //!< Bit field size in bits for FTFE_FEPROT_EPROT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FEPROT_EPROT field.
-#define BR_FTFE_FEPROT_EPROT (HW_FTFE_FEPROT.U)
-#endif
-
-//! @brief Format value for bitfield FTFE_FEPROT_EPROT.
-#define BF_FTFE_FEPROT_EPROT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FEPROT_EPROT), uint8_t) & BM_FTFE_FEPROT_EPROT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EPROT field to a new value.
-#define BW_FTFE_FEPROT_EPROT(v) (HW_FTFE_FEPROT_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTFE_FDPROT - Data Flash Protection Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTFE_FDPROT - Data Flash Protection Register (RW)
- *
- * Reset value: 0x00U
- *
- * The FDPROT register defines which data flash regions are protected against
- * program and erase operations. Protected Flash regions cannot have their content
- * changed; that is, these regions cannot be programmed and cannot be erased by
- * any FTFE command. Unprotected regions can be changed by both program and erase
- * operations.
- */
-typedef union _hw_ftfe_fdprot
-{
- uint8_t U;
- struct _hw_ftfe_fdprot_bitfields
- {
- uint8_t DPROT : 8; //!< [7:0] Data Flash Region Protect
- } B;
-} hw_ftfe_fdprot_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTFE_FDPROT register
- */
-//@{
-#define HW_FTFE_FDPROT_ADDR (REGS_FTFE_BASE + 0x17U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTFE_FDPROT (*(__IO hw_ftfe_fdprot_t *) HW_FTFE_FDPROT_ADDR)
-#define HW_FTFE_FDPROT_RD() (HW_FTFE_FDPROT.U)
-#define HW_FTFE_FDPROT_WR(v) (HW_FTFE_FDPROT.U = (v))
-#define HW_FTFE_FDPROT_SET(v) (HW_FTFE_FDPROT_WR(HW_FTFE_FDPROT_RD() | (v)))
-#define HW_FTFE_FDPROT_CLR(v) (HW_FTFE_FDPROT_WR(HW_FTFE_FDPROT_RD() & ~(v)))
-#define HW_FTFE_FDPROT_TOG(v) (HW_FTFE_FDPROT_WR(HW_FTFE_FDPROT_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTFE_FDPROT bitfields
- */
-
-/*!
- * @name Register FTFE_FDPROT, field DPROT[7:0] (RW)
- *
- * Individual data flash regions can be protected from program and erase
- * operations by setting the associated DPROT bit. Each DPROT bit protects one-eighth of
- * the partitioned data flash memory space. The granularity of data flash
- * protection cannot be less than the data flash sector size. If an unused DPROT bit is
- * set, the Erase all Blocks command does not execute and sets the FSTAT[FPVIOL]
- * bit. In NVM Normal mode: The protection can only be increased, meaning that
- * currently unprotected memory can be protected but currently protected memory
- * cannot be unprotected. Since unprotected regions are marked with a 1 and
- * protected regions use a 0, only writes changing 1s to 0s are accepted. This 1-to-0
- * transition check is performed on a bit-by-bit basis. Those FDPROT bits with
- * 1-to-0 transitions are accepted while all bits with 0-to-1 transitions are
- * ignored. In NVM Special mode: All bits of the FDPROT register are writable without
- * restriction. Unprotected areas can be protected and protected areas can be
- * unprotected. The user must never write to the FDPROT register while a command is
- * running (CCIF=0). Reset: During the reset sequence, the FDPROT register is
- * loaded with the contents of the data flash protection byte in the Flash
- * Configuration Field located in program flash memory. The flash basis for the reset values
- * is signified by X in the register diagram. To change the data flash
- * protection that will be loaded during the reset sequence, unprotect the sector of
- * program flash that contains the Flash Configuration Field. Then, erase and
- * reprogram the data flash protection byte. Trying to alter data with the program and
- * erase commands in any protected area in the data flash memory results in a
- * protection violation error and sets the FSTAT[FPVIOL] bit. A block erase of any
- * data flash memory block (see the Erase Flash Block command description) is not
- * possible if the data flash block contains any protected region or if the FlexNVM
- * memory has been partitioned for EEPROM.
- *
- * Values:
- * - 0 - Data Flash region is protected
- * - 1 - Data Flash region is not protected
- */
-//@{
-#define BP_FTFE_FDPROT_DPROT (0U) //!< Bit position for FTFE_FDPROT_DPROT.
-#define BM_FTFE_FDPROT_DPROT (0xFFU) //!< Bit mask for FTFE_FDPROT_DPROT.
-#define BS_FTFE_FDPROT_DPROT (8U) //!< Bit field size in bits for FTFE_FDPROT_DPROT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTFE_FDPROT_DPROT field.
-#define BR_FTFE_FDPROT_DPROT (HW_FTFE_FDPROT.U)
-#endif
-
-//! @brief Format value for bitfield FTFE_FDPROT_DPROT.
-#define BF_FTFE_FDPROT_DPROT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FDPROT_DPROT), uint8_t) & BM_FTFE_FDPROT_DPROT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DPROT field to a new value.
-#define BW_FTFE_FDPROT_DPROT(v) (HW_FTFE_FDPROT_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_ftfe_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All FTFE module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_ftfe
-{
- __IO hw_ftfe_fstat_t FSTAT; //!< [0x0] Flash Status Register
- __IO hw_ftfe_fcnfg_t FCNFG; //!< [0x1] Flash Configuration Register
- __I hw_ftfe_fsec_t FSEC; //!< [0x2] Flash Security Register
- __I hw_ftfe_fopt_t FOPT; //!< [0x3] Flash Option Register
- __IO hw_ftfe_fccob3_t FCCOB3; //!< [0x4] Flash Common Command Object Registers
- __IO hw_ftfe_fccob2_t FCCOB2; //!< [0x5] Flash Common Command Object Registers
- __IO hw_ftfe_fccob1_t FCCOB1; //!< [0x6] Flash Common Command Object Registers
- __IO hw_ftfe_fccob0_t FCCOB0; //!< [0x7] Flash Common Command Object Registers
- __IO hw_ftfe_fccob7_t FCCOB7; //!< [0x8] Flash Common Command Object Registers
- __IO hw_ftfe_fccob6_t FCCOB6; //!< [0x9] Flash Common Command Object Registers
- __IO hw_ftfe_fccob5_t FCCOB5; //!< [0xA] Flash Common Command Object Registers
- __IO hw_ftfe_fccob4_t FCCOB4; //!< [0xB] Flash Common Command Object Registers
- __IO hw_ftfe_fccobb_t FCCOBB; //!< [0xC] Flash Common Command Object Registers
- __IO hw_ftfe_fccoba_t FCCOBA; //!< [0xD] Flash Common Command Object Registers
- __IO hw_ftfe_fccob9_t FCCOB9; //!< [0xE] Flash Common Command Object Registers
- __IO hw_ftfe_fccob8_t FCCOB8; //!< [0xF] Flash Common Command Object Registers
- __IO hw_ftfe_fprot3_t FPROT3; //!< [0x10] Program Flash Protection Registers
- __IO hw_ftfe_fprot2_t FPROT2; //!< [0x11] Program Flash Protection Registers
- __IO hw_ftfe_fprot1_t FPROT1; //!< [0x12] Program Flash Protection Registers
- __IO hw_ftfe_fprot0_t FPROT0; //!< [0x13] Program Flash Protection Registers
- uint8_t _reserved0[2];
- __IO hw_ftfe_feprot_t FEPROT; //!< [0x16] EEPROM Protection Register
- __IO hw_ftfe_fdprot_t FDPROT; //!< [0x17] Data Flash Protection Register
-} hw_ftfe_t;
-#pragma pack()
-
-//! @brief Macro to access all FTFE registers.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_FTFE</code>.
-#define HW_FTFE (*(hw_ftfe_t *) REGS_FTFE_BASE)
-#endif
-
-#endif // __HW_FTFE_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_ftm.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,6616 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_FTM_REGISTERS_H__
-#define __HW_FTM_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 FTM
- *
- * FlexTimer Module
- *
- * Registers defined in this header file:
- * - HW_FTM_SC - Status And Control
- * - HW_FTM_CNT - Counter
- * - HW_FTM_MOD - Modulo
- * - HW_FTM_CnSC - Channel (n) Status And Control
- * - HW_FTM_CnV - Channel (n) Value
- * - HW_FTM_CNTIN - Counter Initial Value
- * - HW_FTM_STATUS - Capture And Compare Status
- * - HW_FTM_MODE - Features Mode Selection
- * - HW_FTM_SYNC - Synchronization
- * - HW_FTM_OUTINIT - Initial State For Channels Output
- * - HW_FTM_OUTMASK - Output Mask
- * - HW_FTM_COMBINE - Function For Linked Channels
- * - HW_FTM_DEADTIME - Deadtime Insertion Control
- * - HW_FTM_EXTTRIG - FTM External Trigger
- * - HW_FTM_POL - Channels Polarity
- * - HW_FTM_FMS - Fault Mode Status
- * - HW_FTM_FILTER - Input Capture Filter Control
- * - HW_FTM_FLTCTRL - Fault Control
- * - HW_FTM_QDCTRL - Quadrature Decoder Control And Status
- * - HW_FTM_CONF - Configuration
- * - HW_FTM_FLTPOL - FTM Fault Input Polarity
- * - HW_FTM_SYNCONF - Synchronization Configuration
- * - HW_FTM_INVCTRL - FTM Inverting Control
- * - HW_FTM_SWOCTRL - FTM Software Output Control
- * - HW_FTM_PWMLOAD - FTM PWM Load
- *
- * - hw_ftm_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_FTM_BASE
-#define HW_FTM_INSTANCE_COUNT (4U) //!< Number of instances of the FTM module.
-#define HW_FTM0 (0U) //!< Instance number for FTM0.
-#define HW_FTM1 (1U) //!< Instance number for FTM1.
-#define HW_FTM2 (2U) //!< Instance number for FTM2.
-#define HW_FTM3 (3U) //!< Instance number for FTM3.
-#define REGS_FTM0_BASE (0x40038000U) //!< Base address for FTM0.
-#define REGS_FTM1_BASE (0x40039000U) //!< Base address for FTM1.
-#define REGS_FTM2_BASE (0x4003A000U) //!< Base address for FTM2.
-#define REGS_FTM3_BASE (0x400B9000U) //!< Base address for FTM3.
-
-//! @brief Table of base addresses for FTM instances.
-static const uint32_t __g_regs_FTM_base_addresses[] = {
- REGS_FTM0_BASE,
- REGS_FTM1_BASE,
- REGS_FTM2_BASE,
- REGS_FTM3_BASE,
- };
-
-//! @brief Get the base address of FTM by instance number.
-//! @param x FTM instance number, from 0 through 3.
-#define REGS_FTM_BASE(x) (__g_regs_FTM_base_addresses[(x)])
-
-//! @brief Get the instance number given a base address.
-//! @param b Base address for an instance of FTM.
-#define REGS_FTM_INSTANCE(b) ((b) == REGS_FTM0_BASE ? HW_FTM0 : (b) == REGS_FTM1_BASE ? HW_FTM1 : (b) == REGS_FTM2_BASE ? HW_FTM2 : (b) == REGS_FTM3_BASE ? HW_FTM3 : 0)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTM_SC - Status And Control
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTM_SC - Status And Control (RW)
- *
- * Reset value: 0x00000000U
- *
- * SC contains the overflow status flag and control bits used to configure the
- * interrupt enable, FTM configuration, clock source, and prescaler factor. These
- * controls relate to all channels within this module.
- */
-typedef union _hw_ftm_sc
-{
- uint32_t U;
- struct _hw_ftm_sc_bitfields
- {
- uint32_t PS : 3; //!< [2:0] Prescale Factor Selection
- uint32_t CLKS : 2; //!< [4:3] Clock Source Selection
- uint32_t CPWMS : 1; //!< [5] Center-Aligned PWM Select
- uint32_t TOIE : 1; //!< [6] Timer Overflow Interrupt Enable
- uint32_t TOF : 1; //!< [7] Timer Overflow Flag
- uint32_t RESERVED0 : 24; //!< [31:8]
- } B;
-} hw_ftm_sc_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTM_SC register
- */
-//@{
-#define HW_FTM_SC_ADDR(x) (REGS_FTM_BASE(x) + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTM_SC(x) (*(__IO hw_ftm_sc_t *) HW_FTM_SC_ADDR(x))
-#define HW_FTM_SC_RD(x) (HW_FTM_SC(x).U)
-#define HW_FTM_SC_WR(x, v) (HW_FTM_SC(x).U = (v))
-#define HW_FTM_SC_SET(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) | (v)))
-#define HW_FTM_SC_CLR(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) & ~(v)))
-#define HW_FTM_SC_TOG(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTM_SC bitfields
- */
-
-/*!
- * @name Register FTM_SC, field PS[2:0] (RW)
- *
- * Selects one of 8 division factors for the clock source selected by CLKS. The
- * new prescaler factor affects the clock source on the next system clock cycle
- * after the new value is updated into the register bits. This field is write
- * protected. It can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 000 - Divide by 1
- * - 001 - Divide by 2
- * - 010 - Divide by 4
- * - 011 - Divide by 8
- * - 100 - Divide by 16
- * - 101 - Divide by 32
- * - 110 - Divide by 64
- * - 111 - Divide by 128
- */
-//@{
-#define BP_FTM_SC_PS (0U) //!< Bit position for FTM_SC_PS.
-#define BM_FTM_SC_PS (0x00000007U) //!< Bit mask for FTM_SC_PS.
-#define BS_FTM_SC_PS (3U) //!< Bit field size in bits for FTM_SC_PS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SC_PS field.
-#define BR_FTM_SC_PS(x) (HW_FTM_SC(x).B.PS)
-#endif
-
-//! @brief Format value for bitfield FTM_SC_PS.
-#define BF_FTM_SC_PS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SC_PS), uint32_t) & BM_FTM_SC_PS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PS field to a new value.
-#define BW_FTM_SC_PS(x, v) (HW_FTM_SC_WR(x, (HW_FTM_SC_RD(x) & ~BM_FTM_SC_PS) | BF_FTM_SC_PS(v)))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SC, field CLKS[4:3] (RW)
- *
- * Selects one of the three FTM counter clock sources. This field is write
- * protected. It can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 00 - No clock selected. This in effect disables the FTM counter.
- * - 01 - System clock
- * - 10 - Fixed frequency clock
- * - 11 - External clock
- */
-//@{
-#define BP_FTM_SC_CLKS (3U) //!< Bit position for FTM_SC_CLKS.
-#define BM_FTM_SC_CLKS (0x00000018U) //!< Bit mask for FTM_SC_CLKS.
-#define BS_FTM_SC_CLKS (2U) //!< Bit field size in bits for FTM_SC_CLKS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SC_CLKS field.
-#define BR_FTM_SC_CLKS(x) (HW_FTM_SC(x).B.CLKS)
-#endif
-
-//! @brief Format value for bitfield FTM_SC_CLKS.
-#define BF_FTM_SC_CLKS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SC_CLKS), uint32_t) & BM_FTM_SC_CLKS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CLKS field to a new value.
-#define BW_FTM_SC_CLKS(x, v) (HW_FTM_SC_WR(x, (HW_FTM_SC_RD(x) & ~BM_FTM_SC_CLKS) | BF_FTM_SC_CLKS(v)))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SC, field CPWMS[5] (RW)
- *
- * Selects CPWM mode. This mode configures the FTM to operate in Up-Down
- * Counting mode. This field is write protected. It can be written only when MODE[WPDIS]
- * = 1.
- *
- * Values:
- * - 0 - FTM counter operates in Up Counting mode.
- * - 1 - FTM counter operates in Up-Down Counting mode.
- */
-//@{
-#define BP_FTM_SC_CPWMS (5U) //!< Bit position for FTM_SC_CPWMS.
-#define BM_FTM_SC_CPWMS (0x00000020U) //!< Bit mask for FTM_SC_CPWMS.
-#define BS_FTM_SC_CPWMS (1U) //!< Bit field size in bits for FTM_SC_CPWMS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SC_CPWMS field.
-#define BR_FTM_SC_CPWMS(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_CPWMS))
-#endif
-
-//! @brief Format value for bitfield FTM_SC_CPWMS.
-#define BF_FTM_SC_CPWMS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SC_CPWMS), uint32_t) & BM_FTM_SC_CPWMS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CPWMS field to a new value.
-#define BW_FTM_SC_CPWMS(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_CPWMS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SC, field TOIE[6] (RW)
- *
- * Enables FTM overflow interrupts.
- *
- * Values:
- * - 0 - Disable TOF interrupts. Use software polling.
- * - 1 - Enable TOF interrupts. An interrupt is generated when TOF equals one.
- */
-//@{
-#define BP_FTM_SC_TOIE (6U) //!< Bit position for FTM_SC_TOIE.
-#define BM_FTM_SC_TOIE (0x00000040U) //!< Bit mask for FTM_SC_TOIE.
-#define BS_FTM_SC_TOIE (1U) //!< Bit field size in bits for FTM_SC_TOIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SC_TOIE field.
-#define BR_FTM_SC_TOIE(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOIE))
-#endif
-
-//! @brief Format value for bitfield FTM_SC_TOIE.
-#define BF_FTM_SC_TOIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SC_TOIE), uint32_t) & BM_FTM_SC_TOIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TOIE field to a new value.
-#define BW_FTM_SC_TOIE(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SC, field TOF[7] (ROWZ)
- *
- * Set by hardware when the FTM counter passes the value in the MOD register.
- * The TOF bit is cleared by reading the SC register while TOF is set and then
- * writing a 0 to TOF bit. Writing a 1 to TOF has no effect. If another FTM overflow
- * occurs between the read and write operations, the write operation has no
- * effect; therefore, TOF remains set indicating an overflow has occurred. In this
- * case, a TOF interrupt request is not lost due to the clearing sequence for a
- * previous TOF.
- *
- * Values:
- * - 0 - FTM counter has not overflowed.
- * - 1 - FTM counter has overflowed.
- */
-//@{
-#define BP_FTM_SC_TOF (7U) //!< Bit position for FTM_SC_TOF.
-#define BM_FTM_SC_TOF (0x00000080U) //!< Bit mask for FTM_SC_TOF.
-#define BS_FTM_SC_TOF (1U) //!< Bit field size in bits for FTM_SC_TOF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SC_TOF field.
-#define BR_FTM_SC_TOF(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOF))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTM_CNT - Counter
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTM_CNT - Counter (RW)
- *
- * Reset value: 0x00000000U
- *
- * The CNT register contains the FTM counter value. Reset clears the CNT
- * register. Writing any value to COUNT updates the counter with its initial value,
- * CNTIN. When BDM is active, the FTM counter is frozen. This is the value that you
- * may read.
- */
-typedef union _hw_ftm_cnt
-{
- uint32_t U;
- struct _hw_ftm_cnt_bitfields
- {
- uint32_t COUNT : 16; //!< [15:0] Counter Value
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_ftm_cnt_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTM_CNT register
- */
-//@{
-#define HW_FTM_CNT_ADDR(x) (REGS_FTM_BASE(x) + 0x4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTM_CNT(x) (*(__IO hw_ftm_cnt_t *) HW_FTM_CNT_ADDR(x))
-#define HW_FTM_CNT_RD(x) (HW_FTM_CNT(x).U)
-#define HW_FTM_CNT_WR(x, v) (HW_FTM_CNT(x).U = (v))
-#define HW_FTM_CNT_SET(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) | (v)))
-#define HW_FTM_CNT_CLR(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) & ~(v)))
-#define HW_FTM_CNT_TOG(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTM_CNT bitfields
- */
-
-/*!
- * @name Register FTM_CNT, field COUNT[15:0] (RW)
- */
-//@{
-#define BP_FTM_CNT_COUNT (0U) //!< Bit position for FTM_CNT_COUNT.
-#define BM_FTM_CNT_COUNT (0x0000FFFFU) //!< Bit mask for FTM_CNT_COUNT.
-#define BS_FTM_CNT_COUNT (16U) //!< Bit field size in bits for FTM_CNT_COUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_CNT_COUNT field.
-#define BR_FTM_CNT_COUNT(x) (HW_FTM_CNT(x).B.COUNT)
-#endif
-
-//! @brief Format value for bitfield FTM_CNT_COUNT.
-#define BF_FTM_CNT_COUNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CNT_COUNT), uint32_t) & BM_FTM_CNT_COUNT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the COUNT field to a new value.
-#define BW_FTM_CNT_COUNT(x, v) (HW_FTM_CNT_WR(x, (HW_FTM_CNT_RD(x) & ~BM_FTM_CNT_COUNT) | BF_FTM_CNT_COUNT(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTM_MOD - Modulo
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTM_MOD - Modulo (RW)
- *
- * Reset value: 0x00000000U
- *
- * The Modulo register contains the modulo value for the FTM counter. After the
- * FTM counter reaches the modulo value, the overflow flag (TOF) becomes set at
- * the next clock, and the next value of FTM counter depends on the selected
- * counting method; see Counter. Writing to the MOD register latches the value into a
- * buffer. The MOD register is updated with the value of its write buffer
- * according to Registers updated from write buffers. If FTMEN = 0, this write coherency
- * mechanism may be manually reset by writing to the SC register whether BDM is
- * active or not. Initialize the FTM counter, by writing to CNT, before writing
- * to the MOD register to avoid confusion about when the first counter overflow
- * will occur.
- */
-typedef union _hw_ftm_mod
-{
- uint32_t U;
- struct _hw_ftm_mod_bitfields
- {
- uint32_t MOD : 16; //!< [15:0]
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_ftm_mod_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTM_MOD register
- */
-//@{
-#define HW_FTM_MOD_ADDR(x) (REGS_FTM_BASE(x) + 0x8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTM_MOD(x) (*(__IO hw_ftm_mod_t *) HW_FTM_MOD_ADDR(x))
-#define HW_FTM_MOD_RD(x) (HW_FTM_MOD(x).U)
-#define HW_FTM_MOD_WR(x, v) (HW_FTM_MOD(x).U = (v))
-#define HW_FTM_MOD_SET(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) | (v)))
-#define HW_FTM_MOD_CLR(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) & ~(v)))
-#define HW_FTM_MOD_TOG(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTM_MOD bitfields
- */
-
-/*!
- * @name Register FTM_MOD, field MOD[15:0] (RW)
- *
- * Modulo Value
- */
-//@{
-#define BP_FTM_MOD_MOD (0U) //!< Bit position for FTM_MOD_MOD.
-#define BM_FTM_MOD_MOD (0x0000FFFFU) //!< Bit mask for FTM_MOD_MOD.
-#define BS_FTM_MOD_MOD (16U) //!< Bit field size in bits for FTM_MOD_MOD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_MOD_MOD field.
-#define BR_FTM_MOD_MOD(x) (HW_FTM_MOD(x).B.MOD)
-#endif
-
-//! @brief Format value for bitfield FTM_MOD_MOD.
-#define BF_FTM_MOD_MOD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MOD_MOD), uint32_t) & BM_FTM_MOD_MOD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MOD field to a new value.
-#define BW_FTM_MOD_MOD(x, v) (HW_FTM_MOD_WR(x, (HW_FTM_MOD_RD(x) & ~BM_FTM_MOD_MOD) | BF_FTM_MOD_MOD(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTM_CnSC - Channel (n) Status And Control
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTM_CnSC - Channel (n) Status And Control (RW)
- *
- * Reset value: 0x00000000U
- *
- * CnSC contains the channel-interrupt-status flag and control bits used to
- * configure the interrupt enable, channel configuration, and pin function. Mode,
- * edge, and level selection DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode
- * Configuration X X X XX 0 Pin not used for FTM-revert the channel pin to general
- * purpose I/O or other peripheral control 0 0 0 0 1 Input Capture Capture on Rising
- * Edge Only 10 Capture on Falling Edge Only 11 Capture on Rising or Falling Edge
- * 1 1 Output Compare Toggle Output on match 10 Clear Output on match 11 Set
- * Output on match 1X 10 Edge-Aligned PWM High-true pulses (clear Output on match)
- * X1 Low-true pulses (set Output on match) 1 XX 10 Center-Aligned PWM High-true
- * pulses (clear Output on match-up) X1 Low-true pulses (set Output on match-up) 1
- * 0 XX 10 Combine PWM High-true pulses (set on channel (n) match, and clear on
- * channel (n+1) match) X1 Low-true pulses (clear on channel (n) match, and set
- * on channel (n+1) match) 1 0 0 X0 See the following table (#ModeSel2Table). Dual
- * Edge Capture One-Shot Capture mode X1 Continuous Capture mode Dual Edge
- * Capture mode - edge polarity selection ELSnB ELSnA Channel Port Enable Detected
- * Edges 0 0 Disabled No edge 0 1 Enabled Rising edge 1 0 Enabled Falling edge 1 1
- * Enabled Rising and falling edges
- */
-typedef union _hw_ftm_cnsc
-{
- uint32_t U;
- struct _hw_ftm_cnsc_bitfields
- {
- uint32_t DMAb : 1; //!< [0] DMA Enable
- uint32_t RESERVED0 : 1; //!< [1]
- uint32_t ELSA : 1; //!< [2] Edge or Level Select
- uint32_t ELSB : 1; //!< [3] Edge or Level Select
- uint32_t MSA : 1; //!< [4] Channel Mode Select
- uint32_t MSB : 1; //!< [5] Channel Mode Select
- uint32_t CHIE : 1; //!< [6] Channel Interrupt Enable
- uint32_t CHF : 1; //!< [7] Channel Flag
- uint32_t RESERVED1 : 24; //!< [31:8]
- } B;
-} hw_ftm_cnsc_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTM_CnSC register
- */
-//@{
-#define HW_FTM_CnSC_COUNT (8U)
-
-#define HW_FTM_CnSC_ADDR(x, n) (REGS_FTM_BASE(x) + 0xCU + (0x8U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTM_CnSC(x, n) (*(__IO hw_ftm_cnsc_t *) HW_FTM_CnSC_ADDR(x, n))
-#define HW_FTM_CnSC_RD(x, n) (HW_FTM_CnSC(x, n).U)
-#define HW_FTM_CnSC_WR(x, n, v) (HW_FTM_CnSC(x, n).U = (v))
-#define HW_FTM_CnSC_SET(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) | (v)))
-#define HW_FTM_CnSC_CLR(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) & ~(v)))
-#define HW_FTM_CnSC_TOG(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTM_CnSC bitfields
- */
-
-/*!
- * @name Register FTM_CnSC, field DMA[0] (RW)
- *
- * Enables DMA transfers for the channel.
- *
- * Values:
- * - 0 - Disable DMA transfers.
- * - 1 - Enable DMA transfers.
- */
-//@{
-#define BP_FTM_CnSC_DMA (0U) //!< Bit position for FTM_CnSC_DMA.
-#define BM_FTM_CnSC_DMA (0x00000001U) //!< Bit mask for FTM_CnSC_DMA.
-#define BS_FTM_CnSC_DMA (1U) //!< Bit field size in bits for FTM_CnSC_DMA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_CnSC_DMA field.
-#define BR_FTM_CnSC_DMA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_DMA))
-#endif
-
-//! @brief Format value for bitfield FTM_CnSC_DMA.
-#define BF_FTM_CnSC_DMA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_DMA), uint32_t) & BM_FTM_CnSC_DMA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DMA field to a new value.
-#define BW_FTM_CnSC_DMA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_DMA) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_CnSC, field ELSA[2] (RW)
- *
- * The functionality of ELSB and ELSA depends on the channel mode. See
- * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
- * = 1.
- */
-//@{
-#define BP_FTM_CnSC_ELSA (2U) //!< Bit position for FTM_CnSC_ELSA.
-#define BM_FTM_CnSC_ELSA (0x00000004U) //!< Bit mask for FTM_CnSC_ELSA.
-#define BS_FTM_CnSC_ELSA (1U) //!< Bit field size in bits for FTM_CnSC_ELSA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_CnSC_ELSA field.
-#define BR_FTM_CnSC_ELSA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSA))
-#endif
-
-//! @brief Format value for bitfield FTM_CnSC_ELSA.
-#define BF_FTM_CnSC_ELSA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_ELSA), uint32_t) & BM_FTM_CnSC_ELSA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ELSA field to a new value.
-#define BW_FTM_CnSC_ELSA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSA) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_CnSC, field ELSB[3] (RW)
- *
- * The functionality of ELSB and ELSA depends on the channel mode. See
- * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
- * = 1.
- */
-//@{
-#define BP_FTM_CnSC_ELSB (3U) //!< Bit position for FTM_CnSC_ELSB.
-#define BM_FTM_CnSC_ELSB (0x00000008U) //!< Bit mask for FTM_CnSC_ELSB.
-#define BS_FTM_CnSC_ELSB (1U) //!< Bit field size in bits for FTM_CnSC_ELSB.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_CnSC_ELSB field.
-#define BR_FTM_CnSC_ELSB(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSB))
-#endif
-
-//! @brief Format value for bitfield FTM_CnSC_ELSB.
-#define BF_FTM_CnSC_ELSB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_ELSB), uint32_t) & BM_FTM_CnSC_ELSB)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ELSB field to a new value.
-#define BW_FTM_CnSC_ELSB(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSB) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_CnSC, field MSA[4] (RW)
- *
- * Used for further selections in the channel logic. Its functionality is
- * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
- * can be written only when MODE[WPDIS] = 1.
- */
-//@{
-#define BP_FTM_CnSC_MSA (4U) //!< Bit position for FTM_CnSC_MSA.
-#define BM_FTM_CnSC_MSA (0x00000010U) //!< Bit mask for FTM_CnSC_MSA.
-#define BS_FTM_CnSC_MSA (1U) //!< Bit field size in bits for FTM_CnSC_MSA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_CnSC_MSA field.
-#define BR_FTM_CnSC_MSA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSA))
-#endif
-
-//! @brief Format value for bitfield FTM_CnSC_MSA.
-#define BF_FTM_CnSC_MSA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_MSA), uint32_t) & BM_FTM_CnSC_MSA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MSA field to a new value.
-#define BW_FTM_CnSC_MSA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSA) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_CnSC, field MSB[5] (RW)
- *
- * Used for further selections in the channel logic. Its functionality is
- * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
- * can be written only when MODE[WPDIS] = 1.
- */
-//@{
-#define BP_FTM_CnSC_MSB (5U) //!< Bit position for FTM_CnSC_MSB.
-#define BM_FTM_CnSC_MSB (0x00000020U) //!< Bit mask for FTM_CnSC_MSB.
-#define BS_FTM_CnSC_MSB (1U) //!< Bit field size in bits for FTM_CnSC_MSB.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_CnSC_MSB field.
-#define BR_FTM_CnSC_MSB(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSB))
-#endif
-
-//! @brief Format value for bitfield FTM_CnSC_MSB.
-#define BF_FTM_CnSC_MSB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_MSB), uint32_t) & BM_FTM_CnSC_MSB)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MSB field to a new value.
-#define BW_FTM_CnSC_MSB(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSB) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_CnSC, field CHIE[6] (RW)
- *
- * Enables channel interrupts.
- *
- * Values:
- * - 0 - Disable channel interrupts. Use software polling.
- * - 1 - Enable channel interrupts.
- */
-//@{
-#define BP_FTM_CnSC_CHIE (6U) //!< Bit position for FTM_CnSC_CHIE.
-#define BM_FTM_CnSC_CHIE (0x00000040U) //!< Bit mask for FTM_CnSC_CHIE.
-#define BS_FTM_CnSC_CHIE (1U) //!< Bit field size in bits for FTM_CnSC_CHIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_CnSC_CHIE field.
-#define BR_FTM_CnSC_CHIE(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHIE))
-#endif
-
-//! @brief Format value for bitfield FTM_CnSC_CHIE.
-#define BF_FTM_CnSC_CHIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_CHIE), uint32_t) & BM_FTM_CnSC_CHIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CHIE field to a new value.
-#define BW_FTM_CnSC_CHIE(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_CnSC, field CHF[7] (ROWZ)
- *
- * Set by hardware when an event occurs on the channel. CHF is cleared by
- * reading the CSC register while CHnF is set and then writing a 0 to the CHF bit.
- * Writing a 1 to CHF has no effect. If another event occurs between the read and
- * write operations, the write operation has no effect; therefore, CHF remains set
- * indicating an event has occurred. In this case a CHF interrupt request is not
- * lost due to the clearing sequence for a previous CHF.
- *
- * Values:
- * - 0 - No channel event has occurred.
- * - 1 - A channel event has occurred.
- */
-//@{
-#define BP_FTM_CnSC_CHF (7U) //!< Bit position for FTM_CnSC_CHF.
-#define BM_FTM_CnSC_CHF (0x00000080U) //!< Bit mask for FTM_CnSC_CHF.
-#define BS_FTM_CnSC_CHF (1U) //!< Bit field size in bits for FTM_CnSC_CHF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_CnSC_CHF field.
-#define BR_FTM_CnSC_CHF(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHF))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_FTM_CnV - Channel (n) Value
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTM_CnV - Channel (n) Value (RW)
- *
- * Reset value: 0x00000000U
- *
- * These registers contain the captured FTM counter value for the input modes or
- * the match value for the output modes. In Input Capture, Capture Test, and
- * Dual Edge Capture modes, any write to a CnV register is ignored. In output modes,
- * writing to a CnV register latches the value into a buffer. A CnV register is
- * updated with the value of its write buffer according to Registers updated from
- * write buffers. If FTMEN = 0, this write coherency mechanism may be manually
- * reset by writing to the CnSC register whether BDM mode is active or not.
- */
-typedef union _hw_ftm_cnv
-{
- uint32_t U;
- struct _hw_ftm_cnv_bitfields
- {
- uint32_t VAL : 16; //!< [15:0] Channel Value
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_ftm_cnv_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTM_CnV register
- */
-//@{
-#define HW_FTM_CnV_COUNT (8U)
-
-#define HW_FTM_CnV_ADDR(x, n) (REGS_FTM_BASE(x) + 0x10U + (0x8U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTM_CnV(x, n) (*(__IO hw_ftm_cnv_t *) HW_FTM_CnV_ADDR(x, n))
-#define HW_FTM_CnV_RD(x, n) (HW_FTM_CnV(x, n).U)
-#define HW_FTM_CnV_WR(x, n, v) (HW_FTM_CnV(x, n).U = (v))
-#define HW_FTM_CnV_SET(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) | (v)))
-#define HW_FTM_CnV_CLR(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) & ~(v)))
-#define HW_FTM_CnV_TOG(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTM_CnV bitfields
- */
-
-/*!
- * @name Register FTM_CnV, field VAL[15:0] (RW)
- *
- * Captured FTM counter value of the input modes or the match value for the
- * output modes
- */
-//@{
-#define BP_FTM_CnV_VAL (0U) //!< Bit position for FTM_CnV_VAL.
-#define BM_FTM_CnV_VAL (0x0000FFFFU) //!< Bit mask for FTM_CnV_VAL.
-#define BS_FTM_CnV_VAL (16U) //!< Bit field size in bits for FTM_CnV_VAL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_CnV_VAL field.
-#define BR_FTM_CnV_VAL(x, n) (HW_FTM_CnV(x, n).B.VAL)
-#endif
-
-//! @brief Format value for bitfield FTM_CnV_VAL.
-#define BF_FTM_CnV_VAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnV_VAL), uint32_t) & BM_FTM_CnV_VAL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the VAL field to a new value.
-#define BW_FTM_CnV_VAL(x, n, v) (HW_FTM_CnV_WR(x, n, (HW_FTM_CnV_RD(x, n) & ~BM_FTM_CnV_VAL) | BF_FTM_CnV_VAL(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTM_CNTIN - Counter Initial Value
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTM_CNTIN - Counter Initial Value (RW)
- *
- * Reset value: 0x00000000U
- *
- * The Counter Initial Value register contains the initial value for the FTM
- * counter. Writing to the CNTIN register latches the value into a buffer. The CNTIN
- * register is updated with the value of its write buffer according to Registers
- * updated from write buffers. When the FTM clock is initially selected, by
- * writing a non-zero value to the CLKS bits, the FTM counter starts with the value
- * 0x0000. To avoid this behavior, before the first write to select the FTM clock,
- * write the new value to the the CNTIN register and then initialize the FTM
- * counter by writing any value to the CNT register.
- */
-typedef union _hw_ftm_cntin
-{
- uint32_t U;
- struct _hw_ftm_cntin_bitfields
- {
- uint32_t INIT : 16; //!< [15:0]
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_ftm_cntin_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTM_CNTIN register
- */
-//@{
-#define HW_FTM_CNTIN_ADDR(x) (REGS_FTM_BASE(x) + 0x4CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTM_CNTIN(x) (*(__IO hw_ftm_cntin_t *) HW_FTM_CNTIN_ADDR(x))
-#define HW_FTM_CNTIN_RD(x) (HW_FTM_CNTIN(x).U)
-#define HW_FTM_CNTIN_WR(x, v) (HW_FTM_CNTIN(x).U = (v))
-#define HW_FTM_CNTIN_SET(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) | (v)))
-#define HW_FTM_CNTIN_CLR(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) & ~(v)))
-#define HW_FTM_CNTIN_TOG(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTM_CNTIN bitfields
- */
-
-/*!
- * @name Register FTM_CNTIN, field INIT[15:0] (RW)
- *
- * Initial Value Of The FTM Counter
- */
-//@{
-#define BP_FTM_CNTIN_INIT (0U) //!< Bit position for FTM_CNTIN_INIT.
-#define BM_FTM_CNTIN_INIT (0x0000FFFFU) //!< Bit mask for FTM_CNTIN_INIT.
-#define BS_FTM_CNTIN_INIT (16U) //!< Bit field size in bits for FTM_CNTIN_INIT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_CNTIN_INIT field.
-#define BR_FTM_CNTIN_INIT(x) (HW_FTM_CNTIN(x).B.INIT)
-#endif
-
-//! @brief Format value for bitfield FTM_CNTIN_INIT.
-#define BF_FTM_CNTIN_INIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CNTIN_INIT), uint32_t) & BM_FTM_CNTIN_INIT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INIT field to a new value.
-#define BW_FTM_CNTIN_INIT(x, v) (HW_FTM_CNTIN_WR(x, (HW_FTM_CNTIN_RD(x) & ~BM_FTM_CNTIN_INIT) | BF_FTM_CNTIN_INIT(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTM_STATUS - Capture And Compare Status
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTM_STATUS - Capture And Compare Status (RW)
- *
- * Reset value: 0x00000000U
- *
- * The STATUS register contains a copy of the status flag CHnF bit in CnSC for
- * each FTM channel for software convenience. Each CHnF bit in STATUS is a mirror
- * of CHnF bit in CnSC. All CHnF bits can be checked using only one read of
- * STATUS. All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to
- * STATUS. Hardware sets the individual channel flags when an event occurs on the
- * channel. CHnF is cleared by reading STATUS while CHnF is set and then writing
- * a 0 to the CHnF bit. Writing a 1 to CHnF has no effect. If another event
- * occurs between the read and write operations, the write operation has no effect;
- * therefore, CHnF remains set indicating an event has occurred. In this case, a
- * CHnF interrupt request is not lost due to the clearing sequence for a previous
- * CHnF. The STATUS register should be used only in Combine mode.
- */
-typedef union _hw_ftm_status
-{
- uint32_t U;
- struct _hw_ftm_status_bitfields
- {
- uint32_t CH0F : 1; //!< [0] Channel 0 Flag
- uint32_t CH1F : 1; //!< [1] Channel 1 Flag
- uint32_t CH2F : 1; //!< [2] Channel 2 Flag
- uint32_t CH3F : 1; //!< [3] Channel 3 Flag
- uint32_t CH4F : 1; //!< [4] Channel 4 Flag
- uint32_t CH5F : 1; //!< [5] Channel 5 Flag
- uint32_t CH6F : 1; //!< [6] Channel 6 Flag
- uint32_t CH7F : 1; //!< [7] Channel 7 Flag
- uint32_t RESERVED0 : 24; //!< [31:8]
- } B;
-} hw_ftm_status_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTM_STATUS register
- */
-//@{
-#define HW_FTM_STATUS_ADDR(x) (REGS_FTM_BASE(x) + 0x50U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTM_STATUS(x) (*(__IO hw_ftm_status_t *) HW_FTM_STATUS_ADDR(x))
-#define HW_FTM_STATUS_RD(x) (HW_FTM_STATUS(x).U)
-#define HW_FTM_STATUS_WR(x, v) (HW_FTM_STATUS(x).U = (v))
-#define HW_FTM_STATUS_SET(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) | (v)))
-#define HW_FTM_STATUS_CLR(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) & ~(v)))
-#define HW_FTM_STATUS_TOG(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTM_STATUS bitfields
- */
-
-/*!
- * @name Register FTM_STATUS, field CH0F[0] (W1C)
- *
- * See the register description.
- *
- * Values:
- * - 0 - No channel event has occurred.
- * - 1 - A channel event has occurred.
- */
-//@{
-#define BP_FTM_STATUS_CH0F (0U) //!< Bit position for FTM_STATUS_CH0F.
-#define BM_FTM_STATUS_CH0F (0x00000001U) //!< Bit mask for FTM_STATUS_CH0F.
-#define BS_FTM_STATUS_CH0F (1U) //!< Bit field size in bits for FTM_STATUS_CH0F.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_STATUS_CH0F field.
-#define BR_FTM_STATUS_CH0F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH0F))
-#endif
-
-//! @brief Format value for bitfield FTM_STATUS_CH0F.
-#define BF_FTM_STATUS_CH0F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH0F), uint32_t) & BM_FTM_STATUS_CH0F)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH0F field to a new value.
-#define BW_FTM_STATUS_CH0F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH0F) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_STATUS, field CH1F[1] (W1C)
- *
- * See the register description.
- *
- * Values:
- * - 0 - No channel event has occurred.
- * - 1 - A channel event has occurred.
- */
-//@{
-#define BP_FTM_STATUS_CH1F (1U) //!< Bit position for FTM_STATUS_CH1F.
-#define BM_FTM_STATUS_CH1F (0x00000002U) //!< Bit mask for FTM_STATUS_CH1F.
-#define BS_FTM_STATUS_CH1F (1U) //!< Bit field size in bits for FTM_STATUS_CH1F.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_STATUS_CH1F field.
-#define BR_FTM_STATUS_CH1F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH1F))
-#endif
-
-//! @brief Format value for bitfield FTM_STATUS_CH1F.
-#define BF_FTM_STATUS_CH1F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH1F), uint32_t) & BM_FTM_STATUS_CH1F)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH1F field to a new value.
-#define BW_FTM_STATUS_CH1F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH1F) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_STATUS, field CH2F[2] (W1C)
- *
- * See the register description.
- *
- * Values:
- * - 0 - No channel event has occurred.
- * - 1 - A channel event has occurred.
- */
-//@{
-#define BP_FTM_STATUS_CH2F (2U) //!< Bit position for FTM_STATUS_CH2F.
-#define BM_FTM_STATUS_CH2F (0x00000004U) //!< Bit mask for FTM_STATUS_CH2F.
-#define BS_FTM_STATUS_CH2F (1U) //!< Bit field size in bits for FTM_STATUS_CH2F.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_STATUS_CH2F field.
-#define BR_FTM_STATUS_CH2F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH2F))
-#endif
-
-//! @brief Format value for bitfield FTM_STATUS_CH2F.
-#define BF_FTM_STATUS_CH2F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH2F), uint32_t) & BM_FTM_STATUS_CH2F)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH2F field to a new value.
-#define BW_FTM_STATUS_CH2F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH2F) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_STATUS, field CH3F[3] (W1C)
- *
- * See the register description.
- *
- * Values:
- * - 0 - No channel event has occurred.
- * - 1 - A channel event has occurred.
- */
-//@{
-#define BP_FTM_STATUS_CH3F (3U) //!< Bit position for FTM_STATUS_CH3F.
-#define BM_FTM_STATUS_CH3F (0x00000008U) //!< Bit mask for FTM_STATUS_CH3F.
-#define BS_FTM_STATUS_CH3F (1U) //!< Bit field size in bits for FTM_STATUS_CH3F.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_STATUS_CH3F field.
-#define BR_FTM_STATUS_CH3F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH3F))
-#endif
-
-//! @brief Format value for bitfield FTM_STATUS_CH3F.
-#define BF_FTM_STATUS_CH3F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH3F), uint32_t) & BM_FTM_STATUS_CH3F)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH3F field to a new value.
-#define BW_FTM_STATUS_CH3F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH3F) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_STATUS, field CH4F[4] (W1C)
- *
- * See the register description.
- *
- * Values:
- * - 0 - No channel event has occurred.
- * - 1 - A channel event has occurred.
- */
-//@{
-#define BP_FTM_STATUS_CH4F (4U) //!< Bit position for FTM_STATUS_CH4F.
-#define BM_FTM_STATUS_CH4F (0x00000010U) //!< Bit mask for FTM_STATUS_CH4F.
-#define BS_FTM_STATUS_CH4F (1U) //!< Bit field size in bits for FTM_STATUS_CH4F.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_STATUS_CH4F field.
-#define BR_FTM_STATUS_CH4F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH4F))
-#endif
-
-//! @brief Format value for bitfield FTM_STATUS_CH4F.
-#define BF_FTM_STATUS_CH4F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH4F), uint32_t) & BM_FTM_STATUS_CH4F)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH4F field to a new value.
-#define BW_FTM_STATUS_CH4F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH4F) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_STATUS, field CH5F[5] (W1C)
- *
- * See the register description.
- *
- * Values:
- * - 0 - No channel event has occurred.
- * - 1 - A channel event has occurred.
- */
-//@{
-#define BP_FTM_STATUS_CH5F (5U) //!< Bit position for FTM_STATUS_CH5F.
-#define BM_FTM_STATUS_CH5F (0x00000020U) //!< Bit mask for FTM_STATUS_CH5F.
-#define BS_FTM_STATUS_CH5F (1U) //!< Bit field size in bits for FTM_STATUS_CH5F.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_STATUS_CH5F field.
-#define BR_FTM_STATUS_CH5F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH5F))
-#endif
-
-//! @brief Format value for bitfield FTM_STATUS_CH5F.
-#define BF_FTM_STATUS_CH5F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH5F), uint32_t) & BM_FTM_STATUS_CH5F)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH5F field to a new value.
-#define BW_FTM_STATUS_CH5F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH5F) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_STATUS, field CH6F[6] (W1C)
- *
- * See the register description.
- *
- * Values:
- * - 0 - No channel event has occurred.
- * - 1 - A channel event has occurred.
- */
-//@{
-#define BP_FTM_STATUS_CH6F (6U) //!< Bit position for FTM_STATUS_CH6F.
-#define BM_FTM_STATUS_CH6F (0x00000040U) //!< Bit mask for FTM_STATUS_CH6F.
-#define BS_FTM_STATUS_CH6F (1U) //!< Bit field size in bits for FTM_STATUS_CH6F.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_STATUS_CH6F field.
-#define BR_FTM_STATUS_CH6F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH6F))
-#endif
-
-//! @brief Format value for bitfield FTM_STATUS_CH6F.
-#define BF_FTM_STATUS_CH6F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH6F), uint32_t) & BM_FTM_STATUS_CH6F)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH6F field to a new value.
-#define BW_FTM_STATUS_CH6F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH6F) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_STATUS, field CH7F[7] (W1C)
- *
- * See the register description.
- *
- * Values:
- * - 0 - No channel event has occurred.
- * - 1 - A channel event has occurred.
- */
-//@{
-#define BP_FTM_STATUS_CH7F (7U) //!< Bit position for FTM_STATUS_CH7F.
-#define BM_FTM_STATUS_CH7F (0x00000080U) //!< Bit mask for FTM_STATUS_CH7F.
-#define BS_FTM_STATUS_CH7F (1U) //!< Bit field size in bits for FTM_STATUS_CH7F.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_STATUS_CH7F field.
-#define BR_FTM_STATUS_CH7F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH7F))
-#endif
-
-//! @brief Format value for bitfield FTM_STATUS_CH7F.
-#define BF_FTM_STATUS_CH7F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH7F), uint32_t) & BM_FTM_STATUS_CH7F)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH7F field to a new value.
-#define BW_FTM_STATUS_CH7F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH7F) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTM_MODE - Features Mode Selection
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTM_MODE - Features Mode Selection (RW)
- *
- * Reset value: 0x00000004U
- *
- * This register contains the global enable bit for FTM-specific features and
- * the control bits used to configure: Fault control mode and interrupt Capture
- * Test mode PWM synchronization Write protection Channel output initialization
- * These controls relate to all channels within this module.
- */
-typedef union _hw_ftm_mode
-{
- uint32_t U;
- struct _hw_ftm_mode_bitfields
- {
- uint32_t FTMEN : 1; //!< [0] FTM Enable
- uint32_t INIT : 1; //!< [1] Initialize The Channels Output
- uint32_t WPDIS : 1; //!< [2] Write Protection Disable
- uint32_t PWMSYNC : 1; //!< [3] PWM Synchronization Mode
- uint32_t CAPTEST : 1; //!< [4] Capture Test Mode Enable
- uint32_t FAULTM : 2; //!< [6:5] Fault Control Mode
- uint32_t FAULTIE : 1; //!< [7] Fault Interrupt Enable
- uint32_t RESERVED0 : 24; //!< [31:8]
- } B;
-} hw_ftm_mode_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTM_MODE register
- */
-//@{
-#define HW_FTM_MODE_ADDR(x) (REGS_FTM_BASE(x) + 0x54U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTM_MODE(x) (*(__IO hw_ftm_mode_t *) HW_FTM_MODE_ADDR(x))
-#define HW_FTM_MODE_RD(x) (HW_FTM_MODE(x).U)
-#define HW_FTM_MODE_WR(x, v) (HW_FTM_MODE(x).U = (v))
-#define HW_FTM_MODE_SET(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) | (v)))
-#define HW_FTM_MODE_CLR(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) & ~(v)))
-#define HW_FTM_MODE_TOG(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTM_MODE bitfields
- */
-
-/*!
- * @name Register FTM_MODE, field FTMEN[0] (RW)
- *
- * This field is write protected. It can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - Only the TPM-compatible registers (first set of registers) can be used
- * without any restriction. Do not use the FTM-specific registers.
- * - 1 - All registers including the FTM-specific registers (second set of
- * registers) are available for use with no restrictions.
- */
-//@{
-#define BP_FTM_MODE_FTMEN (0U) //!< Bit position for FTM_MODE_FTMEN.
-#define BM_FTM_MODE_FTMEN (0x00000001U) //!< Bit mask for FTM_MODE_FTMEN.
-#define BS_FTM_MODE_FTMEN (1U) //!< Bit field size in bits for FTM_MODE_FTMEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_MODE_FTMEN field.
-#define BR_FTM_MODE_FTMEN(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FTMEN))
-#endif
-
-//! @brief Format value for bitfield FTM_MODE_FTMEN.
-#define BF_FTM_MODE_FTMEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_FTMEN), uint32_t) & BM_FTM_MODE_FTMEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FTMEN field to a new value.
-#define BW_FTM_MODE_FTMEN(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FTMEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_MODE, field INIT[1] (RW)
- *
- * When a 1 is written to INIT bit the channels output is initialized according
- * to the state of their corresponding bit in the OUTINIT register. Writing a 0
- * to INIT bit has no effect. The INIT bit is always read as 0.
- */
-//@{
-#define BP_FTM_MODE_INIT (1U) //!< Bit position for FTM_MODE_INIT.
-#define BM_FTM_MODE_INIT (0x00000002U) //!< Bit mask for FTM_MODE_INIT.
-#define BS_FTM_MODE_INIT (1U) //!< Bit field size in bits for FTM_MODE_INIT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_MODE_INIT field.
-#define BR_FTM_MODE_INIT(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_INIT))
-#endif
-
-//! @brief Format value for bitfield FTM_MODE_INIT.
-#define BF_FTM_MODE_INIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_INIT), uint32_t) & BM_FTM_MODE_INIT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INIT field to a new value.
-#define BW_FTM_MODE_INIT(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_INIT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_MODE, field WPDIS[2] (RW)
- *
- * When write protection is enabled (WPDIS = 0), write protected bits cannot be
- * written. When write protection is disabled (WPDIS = 1), write protected bits
- * can be written. The WPDIS bit is the negation of the WPEN bit. WPDIS is cleared
- * when 1 is written to WPEN. WPDIS is set when WPEN bit is read as a 1 and then
- * 1 is written to WPDIS. Writing 0 to WPDIS has no effect.
- *
- * Values:
- * - 0 - Write protection is enabled.
- * - 1 - Write protection is disabled.
- */
-//@{
-#define BP_FTM_MODE_WPDIS (2U) //!< Bit position for FTM_MODE_WPDIS.
-#define BM_FTM_MODE_WPDIS (0x00000004U) //!< Bit mask for FTM_MODE_WPDIS.
-#define BS_FTM_MODE_WPDIS (1U) //!< Bit field size in bits for FTM_MODE_WPDIS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_MODE_WPDIS field.
-#define BR_FTM_MODE_WPDIS(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_WPDIS))
-#endif
-
-//! @brief Format value for bitfield FTM_MODE_WPDIS.
-#define BF_FTM_MODE_WPDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_WPDIS), uint32_t) & BM_FTM_MODE_WPDIS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WPDIS field to a new value.
-#define BW_FTM_MODE_WPDIS(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_WPDIS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_MODE, field PWMSYNC[3] (RW)
- *
- * Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM counter
- * synchronization. See PWM synchronization. The PWMSYNC bit configures the
- * synchronization when SYNCMODE is 0.
- *
- * Values:
- * - 0 - No restrictions. Software and hardware triggers can be used by MOD,
- * CnV, OUTMASK, and FTM counter synchronization.
- * - 1 - Software trigger can only be used by MOD and CnV synchronization, and
- * hardware triggers can only be used by OUTMASK and FTM counter
- * synchronization.
- */
-//@{
-#define BP_FTM_MODE_PWMSYNC (3U) //!< Bit position for FTM_MODE_PWMSYNC.
-#define BM_FTM_MODE_PWMSYNC (0x00000008U) //!< Bit mask for FTM_MODE_PWMSYNC.
-#define BS_FTM_MODE_PWMSYNC (1U) //!< Bit field size in bits for FTM_MODE_PWMSYNC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_MODE_PWMSYNC field.
-#define BR_FTM_MODE_PWMSYNC(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_PWMSYNC))
-#endif
-
-//! @brief Format value for bitfield FTM_MODE_PWMSYNC.
-#define BF_FTM_MODE_PWMSYNC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_PWMSYNC), uint32_t) & BM_FTM_MODE_PWMSYNC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PWMSYNC field to a new value.
-#define BW_FTM_MODE_PWMSYNC(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_PWMSYNC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_MODE, field CAPTEST[4] (RW)
- *
- * Enables the capture test mode. This field is write protected. It can be
- * written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - Capture test mode is disabled.
- * - 1 - Capture test mode is enabled.
- */
-//@{
-#define BP_FTM_MODE_CAPTEST (4U) //!< Bit position for FTM_MODE_CAPTEST.
-#define BM_FTM_MODE_CAPTEST (0x00000010U) //!< Bit mask for FTM_MODE_CAPTEST.
-#define BS_FTM_MODE_CAPTEST (1U) //!< Bit field size in bits for FTM_MODE_CAPTEST.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_MODE_CAPTEST field.
-#define BR_FTM_MODE_CAPTEST(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_CAPTEST))
-#endif
-
-//! @brief Format value for bitfield FTM_MODE_CAPTEST.
-#define BF_FTM_MODE_CAPTEST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_CAPTEST), uint32_t) & BM_FTM_MODE_CAPTEST)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CAPTEST field to a new value.
-#define BW_FTM_MODE_CAPTEST(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_CAPTEST) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_MODE, field FAULTM[6:5] (RW)
- *
- * Defines the FTM fault control mode. This field is write protected. It can be
- * written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 00 - Fault control is disabled for all channels.
- * - 01 - Fault control is enabled for even channels only (channels 0, 2, 4, and
- * 6), and the selected mode is the manual fault clearing.
- * - 10 - Fault control is enabled for all channels, and the selected mode is
- * the manual fault clearing.
- * - 11 - Fault control is enabled for all channels, and the selected mode is
- * the automatic fault clearing.
- */
-//@{
-#define BP_FTM_MODE_FAULTM (5U) //!< Bit position for FTM_MODE_FAULTM.
-#define BM_FTM_MODE_FAULTM (0x00000060U) //!< Bit mask for FTM_MODE_FAULTM.
-#define BS_FTM_MODE_FAULTM (2U) //!< Bit field size in bits for FTM_MODE_FAULTM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_MODE_FAULTM field.
-#define BR_FTM_MODE_FAULTM(x) (HW_FTM_MODE(x).B.FAULTM)
-#endif
-
-//! @brief Format value for bitfield FTM_MODE_FAULTM.
-#define BF_FTM_MODE_FAULTM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_FAULTM), uint32_t) & BM_FTM_MODE_FAULTM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FAULTM field to a new value.
-#define BW_FTM_MODE_FAULTM(x, v) (HW_FTM_MODE_WR(x, (HW_FTM_MODE_RD(x) & ~BM_FTM_MODE_FAULTM) | BF_FTM_MODE_FAULTM(v)))
-#endif
-//@}
-
-/*!
- * @name Register FTM_MODE, field FAULTIE[7] (RW)
- *
- * Enables the generation of an interrupt when a fault is detected by FTM and
- * the FTM fault control is enabled.
- *
- * Values:
- * - 0 - Fault control interrupt is disabled.
- * - 1 - Fault control interrupt is enabled.
- */
-//@{
-#define BP_FTM_MODE_FAULTIE (7U) //!< Bit position for FTM_MODE_FAULTIE.
-#define BM_FTM_MODE_FAULTIE (0x00000080U) //!< Bit mask for FTM_MODE_FAULTIE.
-#define BS_FTM_MODE_FAULTIE (1U) //!< Bit field size in bits for FTM_MODE_FAULTIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_MODE_FAULTIE field.
-#define BR_FTM_MODE_FAULTIE(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FAULTIE))
-#endif
-
-//! @brief Format value for bitfield FTM_MODE_FAULTIE.
-#define BF_FTM_MODE_FAULTIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_FAULTIE), uint32_t) & BM_FTM_MODE_FAULTIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FAULTIE field to a new value.
-#define BW_FTM_MODE_FAULTIE(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FAULTIE) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTM_SYNC - Synchronization
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTM_SYNC - Synchronization (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register configures the PWM synchronization. A synchronization event can
- * perform the synchronized update of MOD, CV, and OUTMASK registers with the
- * value of their write buffer and the FTM counter initialization. The software
- * trigger, SWSYNC bit, and hardware triggers TRIG0, TRIG1, and TRIG2 bits have a
- * potential conflict if used together when SYNCMODE = 0. Use only hardware or
- * software triggers but not both at the same time, otherwise unpredictable behavior
- * is likely to happen. The selection of the loading point, CNTMAX and CNTMIN
- * bits, is intended to provide the update of MOD, CNTIN, and CnV registers across
- * all enabled channels simultaneously. The use of the loading point selection
- * together with SYNCMODE = 0 and hardware trigger selection, TRIG0, TRIG1, or TRIG2
- * bits, is likely to result in unpredictable behavior. The synchronization
- * event selection also depends on the PWMSYNC (MODE register) and SYNCMODE (SYNCONF
- * register) bits. See PWM synchronization.
- */
-typedef union _hw_ftm_sync
-{
- uint32_t U;
- struct _hw_ftm_sync_bitfields
- {
- uint32_t CNTMIN : 1; //!< [0] Minimum Loading Point Enable
- uint32_t CNTMAX : 1; //!< [1] Maximum Loading Point Enable
- uint32_t REINIT : 1; //!< [2] FTM Counter Reinitialization By
- //! Synchronization (FTM counter synchronization)
- uint32_t SYNCHOM : 1; //!< [3] Output Mask Synchronization
- uint32_t TRIG0 : 1; //!< [4] PWM Synchronization Hardware Trigger 0
- uint32_t TRIG1 : 1; //!< [5] PWM Synchronization Hardware Trigger 1
- uint32_t TRIG2 : 1; //!< [6] PWM Synchronization Hardware Trigger 2
- uint32_t SWSYNC : 1; //!< [7] PWM Synchronization Software Trigger
- uint32_t RESERVED0 : 24; //!< [31:8]
- } B;
-} hw_ftm_sync_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTM_SYNC register
- */
-//@{
-#define HW_FTM_SYNC_ADDR(x) (REGS_FTM_BASE(x) + 0x58U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTM_SYNC(x) (*(__IO hw_ftm_sync_t *) HW_FTM_SYNC_ADDR(x))
-#define HW_FTM_SYNC_RD(x) (HW_FTM_SYNC(x).U)
-#define HW_FTM_SYNC_WR(x, v) (HW_FTM_SYNC(x).U = (v))
-#define HW_FTM_SYNC_SET(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) | (v)))
-#define HW_FTM_SYNC_CLR(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) & ~(v)))
-#define HW_FTM_SYNC_TOG(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTM_SYNC bitfields
- */
-
-/*!
- * @name Register FTM_SYNC, field CNTMIN[0] (RW)
- *
- * Selects the minimum loading point to PWM synchronization. See Boundary cycle
- * and loading points. If CNTMIN is one, the selected loading point is when the
- * FTM counter reaches its minimum value (CNTIN register).
- *
- * Values:
- * - 0 - The minimum loading point is disabled.
- * - 1 - The minimum loading point is enabled.
- */
-//@{
-#define BP_FTM_SYNC_CNTMIN (0U) //!< Bit position for FTM_SYNC_CNTMIN.
-#define BM_FTM_SYNC_CNTMIN (0x00000001U) //!< Bit mask for FTM_SYNC_CNTMIN.
-#define BS_FTM_SYNC_CNTMIN (1U) //!< Bit field size in bits for FTM_SYNC_CNTMIN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SYNC_CNTMIN field.
-#define BR_FTM_SYNC_CNTMIN(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMIN))
-#endif
-
-//! @brief Format value for bitfield FTM_SYNC_CNTMIN.
-#define BF_FTM_SYNC_CNTMIN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_CNTMIN), uint32_t) & BM_FTM_SYNC_CNTMIN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CNTMIN field to a new value.
-#define BW_FTM_SYNC_CNTMIN(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMIN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SYNC, field CNTMAX[1] (RW)
- *
- * Selects the maximum loading point to PWM synchronization. See Boundary cycle
- * and loading points. If CNTMAX is 1, the selected loading point is when the FTM
- * counter reaches its maximum value (MOD register).
- *
- * Values:
- * - 0 - The maximum loading point is disabled.
- * - 1 - The maximum loading point is enabled.
- */
-//@{
-#define BP_FTM_SYNC_CNTMAX (1U) //!< Bit position for FTM_SYNC_CNTMAX.
-#define BM_FTM_SYNC_CNTMAX (0x00000002U) //!< Bit mask for FTM_SYNC_CNTMAX.
-#define BS_FTM_SYNC_CNTMAX (1U) //!< Bit field size in bits for FTM_SYNC_CNTMAX.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SYNC_CNTMAX field.
-#define BR_FTM_SYNC_CNTMAX(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMAX))
-#endif
-
-//! @brief Format value for bitfield FTM_SYNC_CNTMAX.
-#define BF_FTM_SYNC_CNTMAX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_CNTMAX), uint32_t) & BM_FTM_SYNC_CNTMAX)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CNTMAX field to a new value.
-#define BW_FTM_SYNC_CNTMAX(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMAX) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SYNC, field REINIT[2] (RW)
- *
- * Determines if the FTM counter is reinitialized when the selected trigger for
- * the synchronization is detected. The REINIT bit configures the synchronization
- * when SYNCMODE is zero.
- *
- * Values:
- * - 0 - FTM counter continues to count normally.
- * - 1 - FTM counter is updated with its initial value when the selected trigger
- * is detected.
- */
-//@{
-#define BP_FTM_SYNC_REINIT (2U) //!< Bit position for FTM_SYNC_REINIT.
-#define BM_FTM_SYNC_REINIT (0x00000004U) //!< Bit mask for FTM_SYNC_REINIT.
-#define BS_FTM_SYNC_REINIT (1U) //!< Bit field size in bits for FTM_SYNC_REINIT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SYNC_REINIT field.
-#define BR_FTM_SYNC_REINIT(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_REINIT))
-#endif
-
-//! @brief Format value for bitfield FTM_SYNC_REINIT.
-#define BF_FTM_SYNC_REINIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_REINIT), uint32_t) & BM_FTM_SYNC_REINIT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the REINIT field to a new value.
-#define BW_FTM_SYNC_REINIT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_REINIT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SYNC, field SYNCHOM[3] (RW)
- *
- * Selects when the OUTMASK register is updated with the value of its buffer.
- *
- * Values:
- * - 0 - OUTMASK register is updated with the value of its buffer in all rising
- * edges of the system clock.
- * - 1 - OUTMASK register is updated with the value of its buffer only by the
- * PWM synchronization.
- */
-//@{
-#define BP_FTM_SYNC_SYNCHOM (3U) //!< Bit position for FTM_SYNC_SYNCHOM.
-#define BM_FTM_SYNC_SYNCHOM (0x00000008U) //!< Bit mask for FTM_SYNC_SYNCHOM.
-#define BS_FTM_SYNC_SYNCHOM (1U) //!< Bit field size in bits for FTM_SYNC_SYNCHOM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SYNC_SYNCHOM field.
-#define BR_FTM_SYNC_SYNCHOM(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SYNCHOM))
-#endif
-
-//! @brief Format value for bitfield FTM_SYNC_SYNCHOM.
-#define BF_FTM_SYNC_SYNCHOM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_SYNCHOM), uint32_t) & BM_FTM_SYNC_SYNCHOM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SYNCHOM field to a new value.
-#define BW_FTM_SYNC_SYNCHOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SYNCHOM) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SYNC, field TRIG0[4] (RW)
- *
- * Enables hardware trigger 0 to the PWM synchronization. Hardware trigger 0
- * occurs when a rising edge is detected at the trigger 0 input signal.
- *
- * Values:
- * - 0 - Trigger is disabled.
- * - 1 - Trigger is enabled.
- */
-//@{
-#define BP_FTM_SYNC_TRIG0 (4U) //!< Bit position for FTM_SYNC_TRIG0.
-#define BM_FTM_SYNC_TRIG0 (0x00000010U) //!< Bit mask for FTM_SYNC_TRIG0.
-#define BS_FTM_SYNC_TRIG0 (1U) //!< Bit field size in bits for FTM_SYNC_TRIG0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SYNC_TRIG0 field.
-#define BR_FTM_SYNC_TRIG0(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG0))
-#endif
-
-//! @brief Format value for bitfield FTM_SYNC_TRIG0.
-#define BF_FTM_SYNC_TRIG0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_TRIG0), uint32_t) & BM_FTM_SYNC_TRIG0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TRIG0 field to a new value.
-#define BW_FTM_SYNC_TRIG0(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SYNC, field TRIG1[5] (RW)
- *
- * Enables hardware trigger 1 to the PWM synchronization. Hardware trigger 1
- * happens when a rising edge is detected at the trigger 1 input signal.
- *
- * Values:
- * - 0 - Trigger is disabled.
- * - 1 - Trigger is enabled.
- */
-//@{
-#define BP_FTM_SYNC_TRIG1 (5U) //!< Bit position for FTM_SYNC_TRIG1.
-#define BM_FTM_SYNC_TRIG1 (0x00000020U) //!< Bit mask for FTM_SYNC_TRIG1.
-#define BS_FTM_SYNC_TRIG1 (1U) //!< Bit field size in bits for FTM_SYNC_TRIG1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SYNC_TRIG1 field.
-#define BR_FTM_SYNC_TRIG1(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG1))
-#endif
-
-//! @brief Format value for bitfield FTM_SYNC_TRIG1.
-#define BF_FTM_SYNC_TRIG1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_TRIG1), uint32_t) & BM_FTM_SYNC_TRIG1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TRIG1 field to a new value.
-#define BW_FTM_SYNC_TRIG1(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SYNC, field TRIG2[6] (RW)
- *
- * Enables hardware trigger 2 to the PWM synchronization. Hardware trigger 2
- * happens when a rising edge is detected at the trigger 2 input signal.
- *
- * Values:
- * - 0 - Trigger is disabled.
- * - 1 - Trigger is enabled.
- */
-//@{
-#define BP_FTM_SYNC_TRIG2 (6U) //!< Bit position for FTM_SYNC_TRIG2.
-#define BM_FTM_SYNC_TRIG2 (0x00000040U) //!< Bit mask for FTM_SYNC_TRIG2.
-#define BS_FTM_SYNC_TRIG2 (1U) //!< Bit field size in bits for FTM_SYNC_TRIG2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SYNC_TRIG2 field.
-#define BR_FTM_SYNC_TRIG2(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG2))
-#endif
-
-//! @brief Format value for bitfield FTM_SYNC_TRIG2.
-#define BF_FTM_SYNC_TRIG2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_TRIG2), uint32_t) & BM_FTM_SYNC_TRIG2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TRIG2 field to a new value.
-#define BW_FTM_SYNC_TRIG2(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SYNC, field SWSYNC[7] (RW)
- *
- * Selects the software trigger as the PWM synchronization trigger. The software
- * trigger happens when a 1 is written to SWSYNC bit.
- *
- * Values:
- * - 0 - Software trigger is not selected.
- * - 1 - Software trigger is selected.
- */
-//@{
-#define BP_FTM_SYNC_SWSYNC (7U) //!< Bit position for FTM_SYNC_SWSYNC.
-#define BM_FTM_SYNC_SWSYNC (0x00000080U) //!< Bit mask for FTM_SYNC_SWSYNC.
-#define BS_FTM_SYNC_SWSYNC (1U) //!< Bit field size in bits for FTM_SYNC_SWSYNC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SYNC_SWSYNC field.
-#define BR_FTM_SYNC_SWSYNC(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SWSYNC))
-#endif
-
-//! @brief Format value for bitfield FTM_SYNC_SWSYNC.
-#define BF_FTM_SYNC_SWSYNC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_SWSYNC), uint32_t) & BM_FTM_SYNC_SWSYNC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SWSYNC field to a new value.
-#define BW_FTM_SYNC_SWSYNC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SWSYNC) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTM_OUTINIT - Initial State For Channels Output
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTM_OUTINIT - Initial State For Channels Output (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_ftm_outinit
-{
- uint32_t U;
- struct _hw_ftm_outinit_bitfields
- {
- uint32_t CH0OI : 1; //!< [0] Channel 0 Output Initialization Value
- uint32_t CH1OI : 1; //!< [1] Channel 1 Output Initialization Value
- uint32_t CH2OI : 1; //!< [2] Channel 2 Output Initialization Value
- uint32_t CH3OI : 1; //!< [3] Channel 3 Output Initialization Value
- uint32_t CH4OI : 1; //!< [4] Channel 4 Output Initialization Value
- uint32_t CH5OI : 1; //!< [5] Channel 5 Output Initialization Value
- uint32_t CH6OI : 1; //!< [6] Channel 6 Output Initialization Value
- uint32_t CH7OI : 1; //!< [7] Channel 7 Output Initialization Value
- uint32_t RESERVED0 : 24; //!< [31:8]
- } B;
-} hw_ftm_outinit_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTM_OUTINIT register
- */
-//@{
-#define HW_FTM_OUTINIT_ADDR(x) (REGS_FTM_BASE(x) + 0x5CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTM_OUTINIT(x) (*(__IO hw_ftm_outinit_t *) HW_FTM_OUTINIT_ADDR(x))
-#define HW_FTM_OUTINIT_RD(x) (HW_FTM_OUTINIT(x).U)
-#define HW_FTM_OUTINIT_WR(x, v) (HW_FTM_OUTINIT(x).U = (v))
-#define HW_FTM_OUTINIT_SET(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) | (v)))
-#define HW_FTM_OUTINIT_CLR(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) & ~(v)))
-#define HW_FTM_OUTINIT_TOG(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTM_OUTINIT bitfields
- */
-
-/*!
- * @name Register FTM_OUTINIT, field CH0OI[0] (RW)
- *
- * Selects the value that is forced into the channel output when the
- * initialization occurs.
- *
- * Values:
- * - 0 - The initialization value is 0.
- * - 1 - The initialization value is 1.
- */
-//@{
-#define BP_FTM_OUTINIT_CH0OI (0U) //!< Bit position for FTM_OUTINIT_CH0OI.
-#define BM_FTM_OUTINIT_CH0OI (0x00000001U) //!< Bit mask for FTM_OUTINIT_CH0OI.
-#define BS_FTM_OUTINIT_CH0OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH0OI.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_OUTINIT_CH0OI field.
-#define BR_FTM_OUTINIT_CH0OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH0OI))
-#endif
-
-//! @brief Format value for bitfield FTM_OUTINIT_CH0OI.
-#define BF_FTM_OUTINIT_CH0OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH0OI), uint32_t) & BM_FTM_OUTINIT_CH0OI)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH0OI field to a new value.
-#define BW_FTM_OUTINIT_CH0OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH0OI) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_OUTINIT, field CH1OI[1] (RW)
- *
- * Selects the value that is forced into the channel output when the
- * initialization occurs.
- *
- * Values:
- * - 0 - The initialization value is 0.
- * - 1 - The initialization value is 1.
- */
-//@{
-#define BP_FTM_OUTINIT_CH1OI (1U) //!< Bit position for FTM_OUTINIT_CH1OI.
-#define BM_FTM_OUTINIT_CH1OI (0x00000002U) //!< Bit mask for FTM_OUTINIT_CH1OI.
-#define BS_FTM_OUTINIT_CH1OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH1OI.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_OUTINIT_CH1OI field.
-#define BR_FTM_OUTINIT_CH1OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH1OI))
-#endif
-
-//! @brief Format value for bitfield FTM_OUTINIT_CH1OI.
-#define BF_FTM_OUTINIT_CH1OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH1OI), uint32_t) & BM_FTM_OUTINIT_CH1OI)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH1OI field to a new value.
-#define BW_FTM_OUTINIT_CH1OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH1OI) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_OUTINIT, field CH2OI[2] (RW)
- *
- * Selects the value that is forced into the channel output when the
- * initialization occurs.
- *
- * Values:
- * - 0 - The initialization value is 0.
- * - 1 - The initialization value is 1.
- */
-//@{
-#define BP_FTM_OUTINIT_CH2OI (2U) //!< Bit position for FTM_OUTINIT_CH2OI.
-#define BM_FTM_OUTINIT_CH2OI (0x00000004U) //!< Bit mask for FTM_OUTINIT_CH2OI.
-#define BS_FTM_OUTINIT_CH2OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH2OI.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_OUTINIT_CH2OI field.
-#define BR_FTM_OUTINIT_CH2OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH2OI))
-#endif
-
-//! @brief Format value for bitfield FTM_OUTINIT_CH2OI.
-#define BF_FTM_OUTINIT_CH2OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH2OI), uint32_t) & BM_FTM_OUTINIT_CH2OI)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH2OI field to a new value.
-#define BW_FTM_OUTINIT_CH2OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH2OI) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_OUTINIT, field CH3OI[3] (RW)
- *
- * Selects the value that is forced into the channel output when the
- * initialization occurs.
- *
- * Values:
- * - 0 - The initialization value is 0.
- * - 1 - The initialization value is 1.
- */
-//@{
-#define BP_FTM_OUTINIT_CH3OI (3U) //!< Bit position for FTM_OUTINIT_CH3OI.
-#define BM_FTM_OUTINIT_CH3OI (0x00000008U) //!< Bit mask for FTM_OUTINIT_CH3OI.
-#define BS_FTM_OUTINIT_CH3OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH3OI.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_OUTINIT_CH3OI field.
-#define BR_FTM_OUTINIT_CH3OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH3OI))
-#endif
-
-//! @brief Format value for bitfield FTM_OUTINIT_CH3OI.
-#define BF_FTM_OUTINIT_CH3OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH3OI), uint32_t) & BM_FTM_OUTINIT_CH3OI)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH3OI field to a new value.
-#define BW_FTM_OUTINIT_CH3OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH3OI) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_OUTINIT, field CH4OI[4] (RW)
- *
- * Selects the value that is forced into the channel output when the
- * initialization occurs.
- *
- * Values:
- * - 0 - The initialization value is 0.
- * - 1 - The initialization value is 1.
- */
-//@{
-#define BP_FTM_OUTINIT_CH4OI (4U) //!< Bit position for FTM_OUTINIT_CH4OI.
-#define BM_FTM_OUTINIT_CH4OI (0x00000010U) //!< Bit mask for FTM_OUTINIT_CH4OI.
-#define BS_FTM_OUTINIT_CH4OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH4OI.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_OUTINIT_CH4OI field.
-#define BR_FTM_OUTINIT_CH4OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH4OI))
-#endif
-
-//! @brief Format value for bitfield FTM_OUTINIT_CH4OI.
-#define BF_FTM_OUTINIT_CH4OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH4OI), uint32_t) & BM_FTM_OUTINIT_CH4OI)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH4OI field to a new value.
-#define BW_FTM_OUTINIT_CH4OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH4OI) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_OUTINIT, field CH5OI[5] (RW)
- *
- * Selects the value that is forced into the channel output when the
- * initialization occurs.
- *
- * Values:
- * - 0 - The initialization value is 0.
- * - 1 - The initialization value is 1.
- */
-//@{
-#define BP_FTM_OUTINIT_CH5OI (5U) //!< Bit position for FTM_OUTINIT_CH5OI.
-#define BM_FTM_OUTINIT_CH5OI (0x00000020U) //!< Bit mask for FTM_OUTINIT_CH5OI.
-#define BS_FTM_OUTINIT_CH5OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH5OI.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_OUTINIT_CH5OI field.
-#define BR_FTM_OUTINIT_CH5OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH5OI))
-#endif
-
-//! @brief Format value for bitfield FTM_OUTINIT_CH5OI.
-#define BF_FTM_OUTINIT_CH5OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH5OI), uint32_t) & BM_FTM_OUTINIT_CH5OI)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH5OI field to a new value.
-#define BW_FTM_OUTINIT_CH5OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH5OI) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_OUTINIT, field CH6OI[6] (RW)
- *
- * Selects the value that is forced into the channel output when the
- * initialization occurs.
- *
- * Values:
- * - 0 - The initialization value is 0.
- * - 1 - The initialization value is 1.
- */
-//@{
-#define BP_FTM_OUTINIT_CH6OI (6U) //!< Bit position for FTM_OUTINIT_CH6OI.
-#define BM_FTM_OUTINIT_CH6OI (0x00000040U) //!< Bit mask for FTM_OUTINIT_CH6OI.
-#define BS_FTM_OUTINIT_CH6OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH6OI.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_OUTINIT_CH6OI field.
-#define BR_FTM_OUTINIT_CH6OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH6OI))
-#endif
-
-//! @brief Format value for bitfield FTM_OUTINIT_CH6OI.
-#define BF_FTM_OUTINIT_CH6OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH6OI), uint32_t) & BM_FTM_OUTINIT_CH6OI)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH6OI field to a new value.
-#define BW_FTM_OUTINIT_CH6OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH6OI) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_OUTINIT, field CH7OI[7] (RW)
- *
- * Selects the value that is forced into the channel output when the
- * initialization occurs.
- *
- * Values:
- * - 0 - The initialization value is 0.
- * - 1 - The initialization value is 1.
- */
-//@{
-#define BP_FTM_OUTINIT_CH7OI (7U) //!< Bit position for FTM_OUTINIT_CH7OI.
-#define BM_FTM_OUTINIT_CH7OI (0x00000080U) //!< Bit mask for FTM_OUTINIT_CH7OI.
-#define BS_FTM_OUTINIT_CH7OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH7OI.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_OUTINIT_CH7OI field.
-#define BR_FTM_OUTINIT_CH7OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH7OI))
-#endif
-
-//! @brief Format value for bitfield FTM_OUTINIT_CH7OI.
-#define BF_FTM_OUTINIT_CH7OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH7OI), uint32_t) & BM_FTM_OUTINIT_CH7OI)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH7OI field to a new value.
-#define BW_FTM_OUTINIT_CH7OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH7OI) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTM_OUTMASK - Output Mask
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTM_OUTMASK - Output Mask (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register provides a mask for each FTM channel. The mask of a channel
- * determines if its output responds, that is, it is masked or not, when a match
- * occurs. This feature is used for BLDC control where the PWM signal is presented
- * to an electric motor at specific times to provide electronic commutation. Any
- * write to the OUTMASK register, stores the value in its write buffer. The
- * register is updated with the value of its write buffer according to PWM
- * synchronization.
- */
-typedef union _hw_ftm_outmask
-{
- uint32_t U;
- struct _hw_ftm_outmask_bitfields
- {
- uint32_t CH0OM : 1; //!< [0] Channel 0 Output Mask
- uint32_t CH1OM : 1; //!< [1] Channel 1 Output Mask
- uint32_t CH2OM : 1; //!< [2] Channel 2 Output Mask
- uint32_t CH3OM : 1; //!< [3] Channel 3 Output Mask
- uint32_t CH4OM : 1; //!< [4] Channel 4 Output Mask
- uint32_t CH5OM : 1; //!< [5] Channel 5 Output Mask
- uint32_t CH6OM : 1; //!< [6] Channel 6 Output Mask
- uint32_t CH7OM : 1; //!< [7] Channel 7 Output Mask
- uint32_t RESERVED0 : 24; //!< [31:8]
- } B;
-} hw_ftm_outmask_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTM_OUTMASK register
- */
-//@{
-#define HW_FTM_OUTMASK_ADDR(x) (REGS_FTM_BASE(x) + 0x60U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTM_OUTMASK(x) (*(__IO hw_ftm_outmask_t *) HW_FTM_OUTMASK_ADDR(x))
-#define HW_FTM_OUTMASK_RD(x) (HW_FTM_OUTMASK(x).U)
-#define HW_FTM_OUTMASK_WR(x, v) (HW_FTM_OUTMASK(x).U = (v))
-#define HW_FTM_OUTMASK_SET(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) | (v)))
-#define HW_FTM_OUTMASK_CLR(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) & ~(v)))
-#define HW_FTM_OUTMASK_TOG(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTM_OUTMASK bitfields
- */
-
-/*!
- * @name Register FTM_OUTMASK, field CH0OM[0] (RW)
- *
- * Defines if the channel output is masked or unmasked.
- *
- * Values:
- * - 0 - Channel output is not masked. It continues to operate normally.
- * - 1 - Channel output is masked. It is forced to its inactive state.
- */
-//@{
-#define BP_FTM_OUTMASK_CH0OM (0U) //!< Bit position for FTM_OUTMASK_CH0OM.
-#define BM_FTM_OUTMASK_CH0OM (0x00000001U) //!< Bit mask for FTM_OUTMASK_CH0OM.
-#define BS_FTM_OUTMASK_CH0OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH0OM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_OUTMASK_CH0OM field.
-#define BR_FTM_OUTMASK_CH0OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH0OM))
-#endif
-
-//! @brief Format value for bitfield FTM_OUTMASK_CH0OM.
-#define BF_FTM_OUTMASK_CH0OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH0OM), uint32_t) & BM_FTM_OUTMASK_CH0OM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH0OM field to a new value.
-#define BW_FTM_OUTMASK_CH0OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH0OM) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_OUTMASK, field CH1OM[1] (RW)
- *
- * Defines if the channel output is masked or unmasked.
- *
- * Values:
- * - 0 - Channel output is not masked. It continues to operate normally.
- * - 1 - Channel output is masked. It is forced to its inactive state.
- */
-//@{
-#define BP_FTM_OUTMASK_CH1OM (1U) //!< Bit position for FTM_OUTMASK_CH1OM.
-#define BM_FTM_OUTMASK_CH1OM (0x00000002U) //!< Bit mask for FTM_OUTMASK_CH1OM.
-#define BS_FTM_OUTMASK_CH1OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH1OM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_OUTMASK_CH1OM field.
-#define BR_FTM_OUTMASK_CH1OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH1OM))
-#endif
-
-//! @brief Format value for bitfield FTM_OUTMASK_CH1OM.
-#define BF_FTM_OUTMASK_CH1OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH1OM), uint32_t) & BM_FTM_OUTMASK_CH1OM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH1OM field to a new value.
-#define BW_FTM_OUTMASK_CH1OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH1OM) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_OUTMASK, field CH2OM[2] (RW)
- *
- * Defines if the channel output is masked or unmasked.
- *
- * Values:
- * - 0 - Channel output is not masked. It continues to operate normally.
- * - 1 - Channel output is masked. It is forced to its inactive state.
- */
-//@{
-#define BP_FTM_OUTMASK_CH2OM (2U) //!< Bit position for FTM_OUTMASK_CH2OM.
-#define BM_FTM_OUTMASK_CH2OM (0x00000004U) //!< Bit mask for FTM_OUTMASK_CH2OM.
-#define BS_FTM_OUTMASK_CH2OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH2OM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_OUTMASK_CH2OM field.
-#define BR_FTM_OUTMASK_CH2OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH2OM))
-#endif
-
-//! @brief Format value for bitfield FTM_OUTMASK_CH2OM.
-#define BF_FTM_OUTMASK_CH2OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH2OM), uint32_t) & BM_FTM_OUTMASK_CH2OM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH2OM field to a new value.
-#define BW_FTM_OUTMASK_CH2OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH2OM) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_OUTMASK, field CH3OM[3] (RW)
- *
- * Defines if the channel output is masked or unmasked.
- *
- * Values:
- * - 0 - Channel output is not masked. It continues to operate normally.
- * - 1 - Channel output is masked. It is forced to its inactive state.
- */
-//@{
-#define BP_FTM_OUTMASK_CH3OM (3U) //!< Bit position for FTM_OUTMASK_CH3OM.
-#define BM_FTM_OUTMASK_CH3OM (0x00000008U) //!< Bit mask for FTM_OUTMASK_CH3OM.
-#define BS_FTM_OUTMASK_CH3OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH3OM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_OUTMASK_CH3OM field.
-#define BR_FTM_OUTMASK_CH3OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH3OM))
-#endif
-
-//! @brief Format value for bitfield FTM_OUTMASK_CH3OM.
-#define BF_FTM_OUTMASK_CH3OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH3OM), uint32_t) & BM_FTM_OUTMASK_CH3OM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH3OM field to a new value.
-#define BW_FTM_OUTMASK_CH3OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH3OM) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_OUTMASK, field CH4OM[4] (RW)
- *
- * Defines if the channel output is masked or unmasked.
- *
- * Values:
- * - 0 - Channel output is not masked. It continues to operate normally.
- * - 1 - Channel output is masked. It is forced to its inactive state.
- */
-//@{
-#define BP_FTM_OUTMASK_CH4OM (4U) //!< Bit position for FTM_OUTMASK_CH4OM.
-#define BM_FTM_OUTMASK_CH4OM (0x00000010U) //!< Bit mask for FTM_OUTMASK_CH4OM.
-#define BS_FTM_OUTMASK_CH4OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH4OM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_OUTMASK_CH4OM field.
-#define BR_FTM_OUTMASK_CH4OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH4OM))
-#endif
-
-//! @brief Format value for bitfield FTM_OUTMASK_CH4OM.
-#define BF_FTM_OUTMASK_CH4OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH4OM), uint32_t) & BM_FTM_OUTMASK_CH4OM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH4OM field to a new value.
-#define BW_FTM_OUTMASK_CH4OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH4OM) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_OUTMASK, field CH5OM[5] (RW)
- *
- * Defines if the channel output is masked or unmasked.
- *
- * Values:
- * - 0 - Channel output is not masked. It continues to operate normally.
- * - 1 - Channel output is masked. It is forced to its inactive state.
- */
-//@{
-#define BP_FTM_OUTMASK_CH5OM (5U) //!< Bit position for FTM_OUTMASK_CH5OM.
-#define BM_FTM_OUTMASK_CH5OM (0x00000020U) //!< Bit mask for FTM_OUTMASK_CH5OM.
-#define BS_FTM_OUTMASK_CH5OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH5OM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_OUTMASK_CH5OM field.
-#define BR_FTM_OUTMASK_CH5OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH5OM))
-#endif
-
-//! @brief Format value for bitfield FTM_OUTMASK_CH5OM.
-#define BF_FTM_OUTMASK_CH5OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH5OM), uint32_t) & BM_FTM_OUTMASK_CH5OM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH5OM field to a new value.
-#define BW_FTM_OUTMASK_CH5OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH5OM) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_OUTMASK, field CH6OM[6] (RW)
- *
- * Defines if the channel output is masked or unmasked.
- *
- * Values:
- * - 0 - Channel output is not masked. It continues to operate normally.
- * - 1 - Channel output is masked. It is forced to its inactive state.
- */
-//@{
-#define BP_FTM_OUTMASK_CH6OM (6U) //!< Bit position for FTM_OUTMASK_CH6OM.
-#define BM_FTM_OUTMASK_CH6OM (0x00000040U) //!< Bit mask for FTM_OUTMASK_CH6OM.
-#define BS_FTM_OUTMASK_CH6OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH6OM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_OUTMASK_CH6OM field.
-#define BR_FTM_OUTMASK_CH6OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH6OM))
-#endif
-
-//! @brief Format value for bitfield FTM_OUTMASK_CH6OM.
-#define BF_FTM_OUTMASK_CH6OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH6OM), uint32_t) & BM_FTM_OUTMASK_CH6OM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH6OM field to a new value.
-#define BW_FTM_OUTMASK_CH6OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH6OM) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_OUTMASK, field CH7OM[7] (RW)
- *
- * Defines if the channel output is masked or unmasked.
- *
- * Values:
- * - 0 - Channel output is not masked. It continues to operate normally.
- * - 1 - Channel output is masked. It is forced to its inactive state.
- */
-//@{
-#define BP_FTM_OUTMASK_CH7OM (7U) //!< Bit position for FTM_OUTMASK_CH7OM.
-#define BM_FTM_OUTMASK_CH7OM (0x00000080U) //!< Bit mask for FTM_OUTMASK_CH7OM.
-#define BS_FTM_OUTMASK_CH7OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH7OM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_OUTMASK_CH7OM field.
-#define BR_FTM_OUTMASK_CH7OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH7OM))
-#endif
-
-//! @brief Format value for bitfield FTM_OUTMASK_CH7OM.
-#define BF_FTM_OUTMASK_CH7OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH7OM), uint32_t) & BM_FTM_OUTMASK_CH7OM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH7OM field to a new value.
-#define BW_FTM_OUTMASK_CH7OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH7OM) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTM_COMBINE - Function For Linked Channels
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTM_COMBINE - Function For Linked Channels (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register contains the control bits used to configure the fault control,
- * synchronization, deadtime insertion, Dual Edge Capture mode, Complementary,
- * and Combine mode for each pair of channels (n) and (n+1), where n equals 0, 2,
- * 4, and 6.
- */
-typedef union _hw_ftm_combine
-{
- uint32_t U;
- struct _hw_ftm_combine_bitfields
- {
- uint32_t COMBINE0 : 1; //!< [0] Combine Channels For n = 0
- uint32_t COMP0 : 1; //!< [1] Complement Of Channel (n) For n = 0
- uint32_t DECAPEN0 : 1; //!< [2] Dual Edge Capture Mode Enable For n =
- //! 0
- uint32_t DECAP0 : 1; //!< [3] Dual Edge Capture Mode Captures For n =
- //! 0
- uint32_t DTEN0 : 1; //!< [4] Deadtime Enable For n = 0
- uint32_t SYNCEN0 : 1; //!< [5] Synchronization Enable For n = 0
- uint32_t FAULTEN0 : 1; //!< [6] Fault Control Enable For n = 0
- uint32_t RESERVED0 : 1; //!< [7]
- uint32_t COMBINE1 : 1; //!< [8] Combine Channels For n = 2
- uint32_t COMP1 : 1; //!< [9] Complement Of Channel (n) For n = 2
- uint32_t DECAPEN1 : 1; //!< [10] Dual Edge Capture Mode Enable For n
- //! = 2
- uint32_t DECAP1 : 1; //!< [11] Dual Edge Capture Mode Captures For n
- //! = 2
- uint32_t DTEN1 : 1; //!< [12] Deadtime Enable For n = 2
- uint32_t SYNCEN1 : 1; //!< [13] Synchronization Enable For n = 2
- uint32_t FAULTEN1 : 1; //!< [14] Fault Control Enable For n = 2
- uint32_t RESERVED1 : 1; //!< [15]
- uint32_t COMBINE2 : 1; //!< [16] Combine Channels For n = 4
- uint32_t COMP2 : 1; //!< [17] Complement Of Channel (n) For n = 4
- uint32_t DECAPEN2 : 1; //!< [18] Dual Edge Capture Mode Enable For n
- //! = 4
- uint32_t DECAP2 : 1; //!< [19] Dual Edge Capture Mode Captures For n
- //! = 4
- uint32_t DTEN2 : 1; //!< [20] Deadtime Enable For n = 4
- uint32_t SYNCEN2 : 1; //!< [21] Synchronization Enable For n = 4
- uint32_t FAULTEN2 : 1; //!< [22] Fault Control Enable For n = 4
- uint32_t RESERVED2 : 1; //!< [23]
- uint32_t COMBINE3 : 1; //!< [24] Combine Channels For n = 6
- uint32_t COMP3 : 1; //!< [25] Complement Of Channel (n) for n = 6
- uint32_t DECAPEN3 : 1; //!< [26] Dual Edge Capture Mode Enable For n
- //! = 6
- uint32_t DECAP3 : 1; //!< [27] Dual Edge Capture Mode Captures For n
- //! = 6
- uint32_t DTEN3 : 1; //!< [28] Deadtime Enable For n = 6
- uint32_t SYNCEN3 : 1; //!< [29] Synchronization Enable For n = 6
- uint32_t FAULTEN3 : 1; //!< [30] Fault Control Enable For n = 6
- uint32_t RESERVED3 : 1; //!< [31]
- } B;
-} hw_ftm_combine_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTM_COMBINE register
- */
-//@{
-#define HW_FTM_COMBINE_ADDR(x) (REGS_FTM_BASE(x) + 0x64U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTM_COMBINE(x) (*(__IO hw_ftm_combine_t *) HW_FTM_COMBINE_ADDR(x))
-#define HW_FTM_COMBINE_RD(x) (HW_FTM_COMBINE(x).U)
-#define HW_FTM_COMBINE_WR(x, v) (HW_FTM_COMBINE(x).U = (v))
-#define HW_FTM_COMBINE_SET(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) | (v)))
-#define HW_FTM_COMBINE_CLR(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) & ~(v)))
-#define HW_FTM_COMBINE_TOG(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTM_COMBINE bitfields
- */
-
-/*!
- * @name Register FTM_COMBINE, field COMBINE0[0] (RW)
- *
- * Enables the combine feature for channels (n) and (n+1). This field is write
- * protected. It can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - Channels (n) and (n+1) are independent.
- * - 1 - Channels (n) and (n+1) are combined.
- */
-//@{
-#define BP_FTM_COMBINE_COMBINE0 (0U) //!< Bit position for FTM_COMBINE_COMBINE0.
-#define BM_FTM_COMBINE_COMBINE0 (0x00000001U) //!< Bit mask for FTM_COMBINE_COMBINE0.
-#define BS_FTM_COMBINE_COMBINE0 (1U) //!< Bit field size in bits for FTM_COMBINE_COMBINE0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_COMBINE_COMBINE0 field.
-#define BR_FTM_COMBINE_COMBINE0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE0))
-#endif
-
-//! @brief Format value for bitfield FTM_COMBINE_COMBINE0.
-#define BF_FTM_COMBINE_COMBINE0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMBINE0), uint32_t) & BM_FTM_COMBINE_COMBINE0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the COMBINE0 field to a new value.
-#define BW_FTM_COMBINE_COMBINE0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_COMBINE, field COMP0[1] (RW)
- *
- * Enables Complementary mode for the combined channels. In Complementary mode
- * the channel (n+1) output is the inverse of the channel (n) output. This field
- * is write protected. It can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - The channel (n+1) output is the same as the channel (n) output.
- * - 1 - The channel (n+1) output is the complement of the channel (n) output.
- */
-//@{
-#define BP_FTM_COMBINE_COMP0 (1U) //!< Bit position for FTM_COMBINE_COMP0.
-#define BM_FTM_COMBINE_COMP0 (0x00000002U) //!< Bit mask for FTM_COMBINE_COMP0.
-#define BS_FTM_COMBINE_COMP0 (1U) //!< Bit field size in bits for FTM_COMBINE_COMP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_COMBINE_COMP0 field.
-#define BR_FTM_COMBINE_COMP0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP0))
-#endif
-
-//! @brief Format value for bitfield FTM_COMBINE_COMP0.
-#define BF_FTM_COMBINE_COMP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMP0), uint32_t) & BM_FTM_COMBINE_COMP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the COMP0 field to a new value.
-#define BW_FTM_COMBINE_COMP0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_COMBINE, field DECAPEN0[2] (RW)
- *
- * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
- * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
- * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
- * when FTMEN = 1. This field is write protected. It can be written only when
- * MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
- * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
- */
-//@{
-#define BP_FTM_COMBINE_DECAPEN0 (2U) //!< Bit position for FTM_COMBINE_DECAPEN0.
-#define BM_FTM_COMBINE_DECAPEN0 (0x00000004U) //!< Bit mask for FTM_COMBINE_DECAPEN0.
-#define BS_FTM_COMBINE_DECAPEN0 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAPEN0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_COMBINE_DECAPEN0 field.
-#define BR_FTM_COMBINE_DECAPEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN0))
-#endif
-
-//! @brief Format value for bitfield FTM_COMBINE_DECAPEN0.
-#define BF_FTM_COMBINE_DECAPEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAPEN0), uint32_t) & BM_FTM_COMBINE_DECAPEN0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DECAPEN0 field to a new value.
-#define BW_FTM_COMBINE_DECAPEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_COMBINE, field DECAP0[3] (RW)
- *
- * Enables the capture of the FTM counter value according to the channel (n)
- * input event and the configuration of the dual edge capture bits. This field
- * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
- * hardware if dual edge capture - one-shot mode is selected and when the capture
- * of channel (n+1) event is made.
- *
- * Values:
- * - 0 - The dual edge captures are inactive.
- * - 1 - The dual edge captures are active.
- */
-//@{
-#define BP_FTM_COMBINE_DECAP0 (3U) //!< Bit position for FTM_COMBINE_DECAP0.
-#define BM_FTM_COMBINE_DECAP0 (0x00000008U) //!< Bit mask for FTM_COMBINE_DECAP0.
-#define BS_FTM_COMBINE_DECAP0 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_COMBINE_DECAP0 field.
-#define BR_FTM_COMBINE_DECAP0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP0))
-#endif
-
-//! @brief Format value for bitfield FTM_COMBINE_DECAP0.
-#define BF_FTM_COMBINE_DECAP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAP0), uint32_t) & BM_FTM_COMBINE_DECAP0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DECAP0 field to a new value.
-#define BW_FTM_COMBINE_DECAP0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_COMBINE, field DTEN0[4] (RW)
- *
- * Enables the deadtime insertion in the channels (n) and (n+1). This field is
- * write protected. It can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - The deadtime insertion in this pair of channels is disabled.
- * - 1 - The deadtime insertion in this pair of channels is enabled.
- */
-//@{
-#define BP_FTM_COMBINE_DTEN0 (4U) //!< Bit position for FTM_COMBINE_DTEN0.
-#define BM_FTM_COMBINE_DTEN0 (0x00000010U) //!< Bit mask for FTM_COMBINE_DTEN0.
-#define BS_FTM_COMBINE_DTEN0 (1U) //!< Bit field size in bits for FTM_COMBINE_DTEN0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_COMBINE_DTEN0 field.
-#define BR_FTM_COMBINE_DTEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN0))
-#endif
-
-//! @brief Format value for bitfield FTM_COMBINE_DTEN0.
-#define BF_FTM_COMBINE_DTEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DTEN0), uint32_t) & BM_FTM_COMBINE_DTEN0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DTEN0 field to a new value.
-#define BW_FTM_COMBINE_DTEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_COMBINE, field SYNCEN0[5] (RW)
- *
- * Enables PWM synchronization of registers C(n)V and C(n+1)V.
- *
- * Values:
- * - 0 - The PWM synchronization in this pair of channels is disabled.
- * - 1 - The PWM synchronization in this pair of channels is enabled.
- */
-//@{
-#define BP_FTM_COMBINE_SYNCEN0 (5U) //!< Bit position for FTM_COMBINE_SYNCEN0.
-#define BM_FTM_COMBINE_SYNCEN0 (0x00000020U) //!< Bit mask for FTM_COMBINE_SYNCEN0.
-#define BS_FTM_COMBINE_SYNCEN0 (1U) //!< Bit field size in bits for FTM_COMBINE_SYNCEN0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_COMBINE_SYNCEN0 field.
-#define BR_FTM_COMBINE_SYNCEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN0))
-#endif
-
-//! @brief Format value for bitfield FTM_COMBINE_SYNCEN0.
-#define BF_FTM_COMBINE_SYNCEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_SYNCEN0), uint32_t) & BM_FTM_COMBINE_SYNCEN0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SYNCEN0 field to a new value.
-#define BW_FTM_COMBINE_SYNCEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_COMBINE, field FAULTEN0[6] (RW)
- *
- * Enables the fault control in channels (n) and (n+1). This field is write
- * protected. It can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - The fault control in this pair of channels is disabled.
- * - 1 - The fault control in this pair of channels is enabled.
- */
-//@{
-#define BP_FTM_COMBINE_FAULTEN0 (6U) //!< Bit position for FTM_COMBINE_FAULTEN0.
-#define BM_FTM_COMBINE_FAULTEN0 (0x00000040U) //!< Bit mask for FTM_COMBINE_FAULTEN0.
-#define BS_FTM_COMBINE_FAULTEN0 (1U) //!< Bit field size in bits for FTM_COMBINE_FAULTEN0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_COMBINE_FAULTEN0 field.
-#define BR_FTM_COMBINE_FAULTEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN0))
-#endif
-
-//! @brief Format value for bitfield FTM_COMBINE_FAULTEN0.
-#define BF_FTM_COMBINE_FAULTEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_FAULTEN0), uint32_t) & BM_FTM_COMBINE_FAULTEN0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FAULTEN0 field to a new value.
-#define BW_FTM_COMBINE_FAULTEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_COMBINE, field COMBINE1[8] (RW)
- *
- * Enables the combine feature for channels (n) and (n+1). This field is write
- * protected. It can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - Channels (n) and (n+1) are independent.
- * - 1 - Channels (n) and (n+1) are combined.
- */
-//@{
-#define BP_FTM_COMBINE_COMBINE1 (8U) //!< Bit position for FTM_COMBINE_COMBINE1.
-#define BM_FTM_COMBINE_COMBINE1 (0x00000100U) //!< Bit mask for FTM_COMBINE_COMBINE1.
-#define BS_FTM_COMBINE_COMBINE1 (1U) //!< Bit field size in bits for FTM_COMBINE_COMBINE1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_COMBINE_COMBINE1 field.
-#define BR_FTM_COMBINE_COMBINE1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE1))
-#endif
-
-//! @brief Format value for bitfield FTM_COMBINE_COMBINE1.
-#define BF_FTM_COMBINE_COMBINE1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMBINE1), uint32_t) & BM_FTM_COMBINE_COMBINE1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the COMBINE1 field to a new value.
-#define BW_FTM_COMBINE_COMBINE1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_COMBINE, field COMP1[9] (RW)
- *
- * Enables Complementary mode for the combined channels. In Complementary mode
- * the channel (n+1) output is the inverse of the channel (n) output. This field
- * is write protected. It can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - The channel (n+1) output is the same as the channel (n) output.
- * - 1 - The channel (n+1) output is the complement of the channel (n) output.
- */
-//@{
-#define BP_FTM_COMBINE_COMP1 (9U) //!< Bit position for FTM_COMBINE_COMP1.
-#define BM_FTM_COMBINE_COMP1 (0x00000200U) //!< Bit mask for FTM_COMBINE_COMP1.
-#define BS_FTM_COMBINE_COMP1 (1U) //!< Bit field size in bits for FTM_COMBINE_COMP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_COMBINE_COMP1 field.
-#define BR_FTM_COMBINE_COMP1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP1))
-#endif
-
-//! @brief Format value for bitfield FTM_COMBINE_COMP1.
-#define BF_FTM_COMBINE_COMP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMP1), uint32_t) & BM_FTM_COMBINE_COMP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the COMP1 field to a new value.
-#define BW_FTM_COMBINE_COMP1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_COMBINE, field DECAPEN1[10] (RW)
- *
- * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
- * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
- * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
- * when FTMEN = 1. This field is write protected. It can be written only when
- * MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
- * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
- */
-//@{
-#define BP_FTM_COMBINE_DECAPEN1 (10U) //!< Bit position for FTM_COMBINE_DECAPEN1.
-#define BM_FTM_COMBINE_DECAPEN1 (0x00000400U) //!< Bit mask for FTM_COMBINE_DECAPEN1.
-#define BS_FTM_COMBINE_DECAPEN1 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAPEN1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_COMBINE_DECAPEN1 field.
-#define BR_FTM_COMBINE_DECAPEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN1))
-#endif
-
-//! @brief Format value for bitfield FTM_COMBINE_DECAPEN1.
-#define BF_FTM_COMBINE_DECAPEN1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAPEN1), uint32_t) & BM_FTM_COMBINE_DECAPEN1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DECAPEN1 field to a new value.
-#define BW_FTM_COMBINE_DECAPEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_COMBINE, field DECAP1[11] (RW)
- *
- * Enables the capture of the FTM counter value according to the channel (n)
- * input event and the configuration of the dual edge capture bits. This field
- * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
- * hardware if Dual Edge Capture - One-Shot mode is selected and when the capture
- * of channel (n+1) event is made.
- *
- * Values:
- * - 0 - The dual edge captures are inactive.
- * - 1 - The dual edge captures are active.
- */
-//@{
-#define BP_FTM_COMBINE_DECAP1 (11U) //!< Bit position for FTM_COMBINE_DECAP1.
-#define BM_FTM_COMBINE_DECAP1 (0x00000800U) //!< Bit mask for FTM_COMBINE_DECAP1.
-#define BS_FTM_COMBINE_DECAP1 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_COMBINE_DECAP1 field.
-#define BR_FTM_COMBINE_DECAP1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP1))
-#endif
-
-//! @brief Format value for bitfield FTM_COMBINE_DECAP1.
-#define BF_FTM_COMBINE_DECAP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAP1), uint32_t) & BM_FTM_COMBINE_DECAP1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DECAP1 field to a new value.
-#define BW_FTM_COMBINE_DECAP1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_COMBINE, field DTEN1[12] (RW)
- *
- * Enables the deadtime insertion in the channels (n) and (n+1). This field is
- * write protected. It can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - The deadtime insertion in this pair of channels is disabled.
- * - 1 - The deadtime insertion in this pair of channels is enabled.
- */
-//@{
-#define BP_FTM_COMBINE_DTEN1 (12U) //!< Bit position for FTM_COMBINE_DTEN1.
-#define BM_FTM_COMBINE_DTEN1 (0x00001000U) //!< Bit mask for FTM_COMBINE_DTEN1.
-#define BS_FTM_COMBINE_DTEN1 (1U) //!< Bit field size in bits for FTM_COMBINE_DTEN1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_COMBINE_DTEN1 field.
-#define BR_FTM_COMBINE_DTEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN1))
-#endif
-
-//! @brief Format value for bitfield FTM_COMBINE_DTEN1.
-#define BF_FTM_COMBINE_DTEN1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DTEN1), uint32_t) & BM_FTM_COMBINE_DTEN1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DTEN1 field to a new value.
-#define BW_FTM_COMBINE_DTEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_COMBINE, field SYNCEN1[13] (RW)
- *
- * Enables PWM synchronization of registers C(n)V and C(n+1)V.
- *
- * Values:
- * - 0 - The PWM synchronization in this pair of channels is disabled.
- * - 1 - The PWM synchronization in this pair of channels is enabled.
- */
-//@{
-#define BP_FTM_COMBINE_SYNCEN1 (13U) //!< Bit position for FTM_COMBINE_SYNCEN1.
-#define BM_FTM_COMBINE_SYNCEN1 (0x00002000U) //!< Bit mask for FTM_COMBINE_SYNCEN1.
-#define BS_FTM_COMBINE_SYNCEN1 (1U) //!< Bit field size in bits for FTM_COMBINE_SYNCEN1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_COMBINE_SYNCEN1 field.
-#define BR_FTM_COMBINE_SYNCEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN1))
-#endif
-
-//! @brief Format value for bitfield FTM_COMBINE_SYNCEN1.
-#define BF_FTM_COMBINE_SYNCEN1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_SYNCEN1), uint32_t) & BM_FTM_COMBINE_SYNCEN1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SYNCEN1 field to a new value.
-#define BW_FTM_COMBINE_SYNCEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_COMBINE, field FAULTEN1[14] (RW)
- *
- * Enables the fault control in channels (n) and (n+1). This field is write
- * protected. It can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - The fault control in this pair of channels is disabled.
- * - 1 - The fault control in this pair of channels is enabled.
- */
-//@{
-#define BP_FTM_COMBINE_FAULTEN1 (14U) //!< Bit position for FTM_COMBINE_FAULTEN1.
-#define BM_FTM_COMBINE_FAULTEN1 (0x00004000U) //!< Bit mask for FTM_COMBINE_FAULTEN1.
-#define BS_FTM_COMBINE_FAULTEN1 (1U) //!< Bit field size in bits for FTM_COMBINE_FAULTEN1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_COMBINE_FAULTEN1 field.
-#define BR_FTM_COMBINE_FAULTEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN1))
-#endif
-
-//! @brief Format value for bitfield FTM_COMBINE_FAULTEN1.
-#define BF_FTM_COMBINE_FAULTEN1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_FAULTEN1), uint32_t) & BM_FTM_COMBINE_FAULTEN1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FAULTEN1 field to a new value.
-#define BW_FTM_COMBINE_FAULTEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_COMBINE, field COMBINE2[16] (RW)
- *
- * Enables the combine feature for channels (n) and (n+1). This field is write
- * protected. It can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - Channels (n) and (n+1) are independent.
- * - 1 - Channels (n) and (n+1) are combined.
- */
-//@{
-#define BP_FTM_COMBINE_COMBINE2 (16U) //!< Bit position for FTM_COMBINE_COMBINE2.
-#define BM_FTM_COMBINE_COMBINE2 (0x00010000U) //!< Bit mask for FTM_COMBINE_COMBINE2.
-#define BS_FTM_COMBINE_COMBINE2 (1U) //!< Bit field size in bits for FTM_COMBINE_COMBINE2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_COMBINE_COMBINE2 field.
-#define BR_FTM_COMBINE_COMBINE2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE2))
-#endif
-
-//! @brief Format value for bitfield FTM_COMBINE_COMBINE2.
-#define BF_FTM_COMBINE_COMBINE2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMBINE2), uint32_t) & BM_FTM_COMBINE_COMBINE2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the COMBINE2 field to a new value.
-#define BW_FTM_COMBINE_COMBINE2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_COMBINE, field COMP2[17] (RW)
- *
- * Enables Complementary mode for the combined channels. In Complementary mode
- * the channel (n+1) output is the inverse of the channel (n) output. This field
- * is write protected. It can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - The channel (n+1) output is the same as the channel (n) output.
- * - 1 - The channel (n+1) output is the complement of the channel (n) output.
- */
-//@{
-#define BP_FTM_COMBINE_COMP2 (17U) //!< Bit position for FTM_COMBINE_COMP2.
-#define BM_FTM_COMBINE_COMP2 (0x00020000U) //!< Bit mask for FTM_COMBINE_COMP2.
-#define BS_FTM_COMBINE_COMP2 (1U) //!< Bit field size in bits for FTM_COMBINE_COMP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_COMBINE_COMP2 field.
-#define BR_FTM_COMBINE_COMP2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP2))
-#endif
-
-//! @brief Format value for bitfield FTM_COMBINE_COMP2.
-#define BF_FTM_COMBINE_COMP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMP2), uint32_t) & BM_FTM_COMBINE_COMP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the COMP2 field to a new value.
-#define BW_FTM_COMBINE_COMP2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_COMBINE, field DECAPEN2[18] (RW)
- *
- * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
- * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
- * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
- * when FTMEN = 1. This field is write protected. It can be written only when
- * MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
- * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
- */
-//@{
-#define BP_FTM_COMBINE_DECAPEN2 (18U) //!< Bit position for FTM_COMBINE_DECAPEN2.
-#define BM_FTM_COMBINE_DECAPEN2 (0x00040000U) //!< Bit mask for FTM_COMBINE_DECAPEN2.
-#define BS_FTM_COMBINE_DECAPEN2 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAPEN2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_COMBINE_DECAPEN2 field.
-#define BR_FTM_COMBINE_DECAPEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN2))
-#endif
-
-//! @brief Format value for bitfield FTM_COMBINE_DECAPEN2.
-#define BF_FTM_COMBINE_DECAPEN2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAPEN2), uint32_t) & BM_FTM_COMBINE_DECAPEN2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DECAPEN2 field to a new value.
-#define BW_FTM_COMBINE_DECAPEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_COMBINE, field DECAP2[19] (RW)
- *
- * Enables the capture of the FTM counter value according to the channel (n)
- * input event and the configuration of the dual edge capture bits. This field
- * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
- * hardware if dual edge capture - one-shot mode is selected and when the capture
- * of channel (n+1) event is made.
- *
- * Values:
- * - 0 - The dual edge captures are inactive.
- * - 1 - The dual edge captures are active.
- */
-//@{
-#define BP_FTM_COMBINE_DECAP2 (19U) //!< Bit position for FTM_COMBINE_DECAP2.
-#define BM_FTM_COMBINE_DECAP2 (0x00080000U) //!< Bit mask for FTM_COMBINE_DECAP2.
-#define BS_FTM_COMBINE_DECAP2 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_COMBINE_DECAP2 field.
-#define BR_FTM_COMBINE_DECAP2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP2))
-#endif
-
-//! @brief Format value for bitfield FTM_COMBINE_DECAP2.
-#define BF_FTM_COMBINE_DECAP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAP2), uint32_t) & BM_FTM_COMBINE_DECAP2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DECAP2 field to a new value.
-#define BW_FTM_COMBINE_DECAP2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_COMBINE, field DTEN2[20] (RW)
- *
- * Enables the deadtime insertion in the channels (n) and (n+1). This field is
- * write protected. It can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - The deadtime insertion in this pair of channels is disabled.
- * - 1 - The deadtime insertion in this pair of channels is enabled.
- */
-//@{
-#define BP_FTM_COMBINE_DTEN2 (20U) //!< Bit position for FTM_COMBINE_DTEN2.
-#define BM_FTM_COMBINE_DTEN2 (0x00100000U) //!< Bit mask for FTM_COMBINE_DTEN2.
-#define BS_FTM_COMBINE_DTEN2 (1U) //!< Bit field size in bits for FTM_COMBINE_DTEN2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_COMBINE_DTEN2 field.
-#define BR_FTM_COMBINE_DTEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN2))
-#endif
-
-//! @brief Format value for bitfield FTM_COMBINE_DTEN2.
-#define BF_FTM_COMBINE_DTEN2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DTEN2), uint32_t) & BM_FTM_COMBINE_DTEN2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DTEN2 field to a new value.
-#define BW_FTM_COMBINE_DTEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_COMBINE, field SYNCEN2[21] (RW)
- *
- * Enables PWM synchronization of registers C(n)V and C(n+1)V.
- *
- * Values:
- * - 0 - The PWM synchronization in this pair of channels is disabled.
- * - 1 - The PWM synchronization in this pair of channels is enabled.
- */
-//@{
-#define BP_FTM_COMBINE_SYNCEN2 (21U) //!< Bit position for FTM_COMBINE_SYNCEN2.
-#define BM_FTM_COMBINE_SYNCEN2 (0x00200000U) //!< Bit mask for FTM_COMBINE_SYNCEN2.
-#define BS_FTM_COMBINE_SYNCEN2 (1U) //!< Bit field size in bits for FTM_COMBINE_SYNCEN2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_COMBINE_SYNCEN2 field.
-#define BR_FTM_COMBINE_SYNCEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN2))
-#endif
-
-//! @brief Format value for bitfield FTM_COMBINE_SYNCEN2.
-#define BF_FTM_COMBINE_SYNCEN2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_SYNCEN2), uint32_t) & BM_FTM_COMBINE_SYNCEN2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SYNCEN2 field to a new value.
-#define BW_FTM_COMBINE_SYNCEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_COMBINE, field FAULTEN2[22] (RW)
- *
- * Enables the fault control in channels (n) and (n+1). This field is write
- * protected. It can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - The fault control in this pair of channels is disabled.
- * - 1 - The fault control in this pair of channels is enabled.
- */
-//@{
-#define BP_FTM_COMBINE_FAULTEN2 (22U) //!< Bit position for FTM_COMBINE_FAULTEN2.
-#define BM_FTM_COMBINE_FAULTEN2 (0x00400000U) //!< Bit mask for FTM_COMBINE_FAULTEN2.
-#define BS_FTM_COMBINE_FAULTEN2 (1U) //!< Bit field size in bits for FTM_COMBINE_FAULTEN2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_COMBINE_FAULTEN2 field.
-#define BR_FTM_COMBINE_FAULTEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN2))
-#endif
-
-//! @brief Format value for bitfield FTM_COMBINE_FAULTEN2.
-#define BF_FTM_COMBINE_FAULTEN2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_FAULTEN2), uint32_t) & BM_FTM_COMBINE_FAULTEN2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FAULTEN2 field to a new value.
-#define BW_FTM_COMBINE_FAULTEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_COMBINE, field COMBINE3[24] (RW)
- *
- * Enables the combine feature for channels (n) and (n+1). This field is write
- * protected. It can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - Channels (n) and (n+1) are independent.
- * - 1 - Channels (n) and (n+1) are combined.
- */
-//@{
-#define BP_FTM_COMBINE_COMBINE3 (24U) //!< Bit position for FTM_COMBINE_COMBINE3.
-#define BM_FTM_COMBINE_COMBINE3 (0x01000000U) //!< Bit mask for FTM_COMBINE_COMBINE3.
-#define BS_FTM_COMBINE_COMBINE3 (1U) //!< Bit field size in bits for FTM_COMBINE_COMBINE3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_COMBINE_COMBINE3 field.
-#define BR_FTM_COMBINE_COMBINE3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE3))
-#endif
-
-//! @brief Format value for bitfield FTM_COMBINE_COMBINE3.
-#define BF_FTM_COMBINE_COMBINE3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMBINE3), uint32_t) & BM_FTM_COMBINE_COMBINE3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the COMBINE3 field to a new value.
-#define BW_FTM_COMBINE_COMBINE3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_COMBINE, field COMP3[25] (RW)
- *
- * Enables Complementary mode for the combined channels. In Complementary mode
- * the channel (n+1) output is the inverse of the channel (n) output. This field
- * is write protected. It can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - The channel (n+1) output is the same as the channel (n) output.
- * - 1 - The channel (n+1) output is the complement of the channel (n) output.
- */
-//@{
-#define BP_FTM_COMBINE_COMP3 (25U) //!< Bit position for FTM_COMBINE_COMP3.
-#define BM_FTM_COMBINE_COMP3 (0x02000000U) //!< Bit mask for FTM_COMBINE_COMP3.
-#define BS_FTM_COMBINE_COMP3 (1U) //!< Bit field size in bits for FTM_COMBINE_COMP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_COMBINE_COMP3 field.
-#define BR_FTM_COMBINE_COMP3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP3))
-#endif
-
-//! @brief Format value for bitfield FTM_COMBINE_COMP3.
-#define BF_FTM_COMBINE_COMP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMP3), uint32_t) & BM_FTM_COMBINE_COMP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the COMP3 field to a new value.
-#define BW_FTM_COMBINE_COMP3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_COMBINE, field DECAPEN3[26] (RW)
- *
- * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
- * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
- * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
- * when FTMEN = 1. This field is write protected. It can be written only when
- * MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
- * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
- */
-//@{
-#define BP_FTM_COMBINE_DECAPEN3 (26U) //!< Bit position for FTM_COMBINE_DECAPEN3.
-#define BM_FTM_COMBINE_DECAPEN3 (0x04000000U) //!< Bit mask for FTM_COMBINE_DECAPEN3.
-#define BS_FTM_COMBINE_DECAPEN3 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAPEN3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_COMBINE_DECAPEN3 field.
-#define BR_FTM_COMBINE_DECAPEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN3))
-#endif
-
-//! @brief Format value for bitfield FTM_COMBINE_DECAPEN3.
-#define BF_FTM_COMBINE_DECAPEN3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAPEN3), uint32_t) & BM_FTM_COMBINE_DECAPEN3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DECAPEN3 field to a new value.
-#define BW_FTM_COMBINE_DECAPEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_COMBINE, field DECAP3[27] (RW)
- *
- * Enables the capture of the FTM counter value according to the channel (n)
- * input event and the configuration of the dual edge capture bits. This field
- * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
- * hardware if dual edge capture - one-shot mode is selected and when the capture
- * of channel (n+1) event is made.
- *
- * Values:
- * - 0 - The dual edge captures are inactive.
- * - 1 - The dual edge captures are active.
- */
-//@{
-#define BP_FTM_COMBINE_DECAP3 (27U) //!< Bit position for FTM_COMBINE_DECAP3.
-#define BM_FTM_COMBINE_DECAP3 (0x08000000U) //!< Bit mask for FTM_COMBINE_DECAP3.
-#define BS_FTM_COMBINE_DECAP3 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_COMBINE_DECAP3 field.
-#define BR_FTM_COMBINE_DECAP3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP3))
-#endif
-
-//! @brief Format value for bitfield FTM_COMBINE_DECAP3.
-#define BF_FTM_COMBINE_DECAP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAP3), uint32_t) & BM_FTM_COMBINE_DECAP3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DECAP3 field to a new value.
-#define BW_FTM_COMBINE_DECAP3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_COMBINE, field DTEN3[28] (RW)
- *
- * Enables the deadtime insertion in the channels (n) and (n+1). This field is
- * write protected. It can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - The deadtime insertion in this pair of channels is disabled.
- * - 1 - The deadtime insertion in this pair of channels is enabled.
- */
-//@{
-#define BP_FTM_COMBINE_DTEN3 (28U) //!< Bit position for FTM_COMBINE_DTEN3.
-#define BM_FTM_COMBINE_DTEN3 (0x10000000U) //!< Bit mask for FTM_COMBINE_DTEN3.
-#define BS_FTM_COMBINE_DTEN3 (1U) //!< Bit field size in bits for FTM_COMBINE_DTEN3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_COMBINE_DTEN3 field.
-#define BR_FTM_COMBINE_DTEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN3))
-#endif
-
-//! @brief Format value for bitfield FTM_COMBINE_DTEN3.
-#define BF_FTM_COMBINE_DTEN3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DTEN3), uint32_t) & BM_FTM_COMBINE_DTEN3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DTEN3 field to a new value.
-#define BW_FTM_COMBINE_DTEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_COMBINE, field SYNCEN3[29] (RW)
- *
- * Enables PWM synchronization of registers C(n)V and C(n+1)V.
- *
- * Values:
- * - 0 - The PWM synchronization in this pair of channels is disabled.
- * - 1 - The PWM synchronization in this pair of channels is enabled.
- */
-//@{
-#define BP_FTM_COMBINE_SYNCEN3 (29U) //!< Bit position for FTM_COMBINE_SYNCEN3.
-#define BM_FTM_COMBINE_SYNCEN3 (0x20000000U) //!< Bit mask for FTM_COMBINE_SYNCEN3.
-#define BS_FTM_COMBINE_SYNCEN3 (1U) //!< Bit field size in bits for FTM_COMBINE_SYNCEN3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_COMBINE_SYNCEN3 field.
-#define BR_FTM_COMBINE_SYNCEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN3))
-#endif
-
-//! @brief Format value for bitfield FTM_COMBINE_SYNCEN3.
-#define BF_FTM_COMBINE_SYNCEN3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_SYNCEN3), uint32_t) & BM_FTM_COMBINE_SYNCEN3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SYNCEN3 field to a new value.
-#define BW_FTM_COMBINE_SYNCEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_COMBINE, field FAULTEN3[30] (RW)
- *
- * Enables the fault control in channels (n) and (n+1). This field is write
- * protected. It can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - The fault control in this pair of channels is disabled.
- * - 1 - The fault control in this pair of channels is enabled.
- */
-//@{
-#define BP_FTM_COMBINE_FAULTEN3 (30U) //!< Bit position for FTM_COMBINE_FAULTEN3.
-#define BM_FTM_COMBINE_FAULTEN3 (0x40000000U) //!< Bit mask for FTM_COMBINE_FAULTEN3.
-#define BS_FTM_COMBINE_FAULTEN3 (1U) //!< Bit field size in bits for FTM_COMBINE_FAULTEN3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_COMBINE_FAULTEN3 field.
-#define BR_FTM_COMBINE_FAULTEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN3))
-#endif
-
-//! @brief Format value for bitfield FTM_COMBINE_FAULTEN3.
-#define BF_FTM_COMBINE_FAULTEN3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_FAULTEN3), uint32_t) & BM_FTM_COMBINE_FAULTEN3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FAULTEN3 field to a new value.
-#define BW_FTM_COMBINE_FAULTEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN3) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTM_DEADTIME - Deadtime Insertion Control
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTM_DEADTIME - Deadtime Insertion Control (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register selects the deadtime prescaler factor and deadtime value. All
- * FTM channels use this clock prescaler and this deadtime value for the deadtime
- * insertion.
- */
-typedef union _hw_ftm_deadtime
-{
- uint32_t U;
- struct _hw_ftm_deadtime_bitfields
- {
- uint32_t DTVAL : 6; //!< [5:0] Deadtime Value
- uint32_t DTPS : 2; //!< [7:6] Deadtime Prescaler Value
- uint32_t RESERVED0 : 24; //!< [31:8]
- } B;
-} hw_ftm_deadtime_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTM_DEADTIME register
- */
-//@{
-#define HW_FTM_DEADTIME_ADDR(x) (REGS_FTM_BASE(x) + 0x68U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTM_DEADTIME(x) (*(__IO hw_ftm_deadtime_t *) HW_FTM_DEADTIME_ADDR(x))
-#define HW_FTM_DEADTIME_RD(x) (HW_FTM_DEADTIME(x).U)
-#define HW_FTM_DEADTIME_WR(x, v) (HW_FTM_DEADTIME(x).U = (v))
-#define HW_FTM_DEADTIME_SET(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) | (v)))
-#define HW_FTM_DEADTIME_CLR(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) & ~(v)))
-#define HW_FTM_DEADTIME_TOG(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTM_DEADTIME bitfields
- */
-
-/*!
- * @name Register FTM_DEADTIME, field DTVAL[5:0] (RW)
- *
- * Selects the deadtime insertion value for the deadtime counter. The deadtime
- * counter is clocked by a scaled version of the system clock. See the description
- * of DTPS. Deadtime insert value = (DTPS * DTVAL). DTVAL selects the number of
- * deadtime counts inserted as follows: When DTVAL is 0, no counts are inserted.
- * When DTVAL is 1, 1 count is inserted. When DTVAL is 2, 2 counts are inserted.
- * This pattern continues up to a possible 63 counts. This field is write
- * protected. It can be written only when MODE[WPDIS] = 1.
- */
-//@{
-#define BP_FTM_DEADTIME_DTVAL (0U) //!< Bit position for FTM_DEADTIME_DTVAL.
-#define BM_FTM_DEADTIME_DTVAL (0x0000003FU) //!< Bit mask for FTM_DEADTIME_DTVAL.
-#define BS_FTM_DEADTIME_DTVAL (6U) //!< Bit field size in bits for FTM_DEADTIME_DTVAL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_DEADTIME_DTVAL field.
-#define BR_FTM_DEADTIME_DTVAL(x) (HW_FTM_DEADTIME(x).B.DTVAL)
-#endif
-
-//! @brief Format value for bitfield FTM_DEADTIME_DTVAL.
-#define BF_FTM_DEADTIME_DTVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_DEADTIME_DTVAL), uint32_t) & BM_FTM_DEADTIME_DTVAL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DTVAL field to a new value.
-#define BW_FTM_DEADTIME_DTVAL(x, v) (HW_FTM_DEADTIME_WR(x, (HW_FTM_DEADTIME_RD(x) & ~BM_FTM_DEADTIME_DTVAL) | BF_FTM_DEADTIME_DTVAL(v)))
-#endif
-//@}
-
-/*!
- * @name Register FTM_DEADTIME, field DTPS[7:6] (RW)
- *
- * Selects the division factor of the system clock. This prescaled clock is used
- * by the deadtime counter. This field is write protected. It can be written
- * only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0x - Divide the system clock by 1.
- * - 10 - Divide the system clock by 4.
- * - 11 - Divide the system clock by 16.
- */
-//@{
-#define BP_FTM_DEADTIME_DTPS (6U) //!< Bit position for FTM_DEADTIME_DTPS.
-#define BM_FTM_DEADTIME_DTPS (0x000000C0U) //!< Bit mask for FTM_DEADTIME_DTPS.
-#define BS_FTM_DEADTIME_DTPS (2U) //!< Bit field size in bits for FTM_DEADTIME_DTPS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_DEADTIME_DTPS field.
-#define BR_FTM_DEADTIME_DTPS(x) (HW_FTM_DEADTIME(x).B.DTPS)
-#endif
-
-//! @brief Format value for bitfield FTM_DEADTIME_DTPS.
-#define BF_FTM_DEADTIME_DTPS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_DEADTIME_DTPS), uint32_t) & BM_FTM_DEADTIME_DTPS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DTPS field to a new value.
-#define BW_FTM_DEADTIME_DTPS(x, v) (HW_FTM_DEADTIME_WR(x, (HW_FTM_DEADTIME_RD(x) & ~BM_FTM_DEADTIME_DTPS) | BF_FTM_DEADTIME_DTPS(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTM_EXTTRIG - FTM External Trigger
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTM_EXTTRIG - FTM External Trigger (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register: Indicates when a channel trigger was generated Enables the
- * generation of a trigger when the FTM counter is equal to its initial value
- * Selects which channels are used in the generation of the channel triggers Several
- * channels can be selected to generate multiple triggers in one PWM period.
- * Channels 6 and 7 are not used to generate channel triggers.
- */
-typedef union _hw_ftm_exttrig
-{
- uint32_t U;
- struct _hw_ftm_exttrig_bitfields
- {
- uint32_t CH2TRIG : 1; //!< [0] Channel 2 Trigger Enable
- uint32_t CH3TRIG : 1; //!< [1] Channel 3 Trigger Enable
- uint32_t CH4TRIG : 1; //!< [2] Channel 4 Trigger Enable
- uint32_t CH5TRIG : 1; //!< [3] Channel 5 Trigger Enable
- uint32_t CH0TRIG : 1; //!< [4] Channel 0 Trigger Enable
- uint32_t CH1TRIG : 1; //!< [5] Channel 1 Trigger Enable
- uint32_t INITTRIGEN : 1; //!< [6] Initialization Trigger Enable
- uint32_t TRIGF : 1; //!< [7] Channel Trigger Flag
- uint32_t RESERVED0 : 24; //!< [31:8]
- } B;
-} hw_ftm_exttrig_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTM_EXTTRIG register
- */
-//@{
-#define HW_FTM_EXTTRIG_ADDR(x) (REGS_FTM_BASE(x) + 0x6CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTM_EXTTRIG(x) (*(__IO hw_ftm_exttrig_t *) HW_FTM_EXTTRIG_ADDR(x))
-#define HW_FTM_EXTTRIG_RD(x) (HW_FTM_EXTTRIG(x).U)
-#define HW_FTM_EXTTRIG_WR(x, v) (HW_FTM_EXTTRIG(x).U = (v))
-#define HW_FTM_EXTTRIG_SET(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) | (v)))
-#define HW_FTM_EXTTRIG_CLR(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) & ~(v)))
-#define HW_FTM_EXTTRIG_TOG(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTM_EXTTRIG bitfields
- */
-
-/*!
- * @name Register FTM_EXTTRIG, field CH2TRIG[0] (RW)
- *
- * Enables the generation of the channel trigger when the FTM counter is equal
- * to the CnV register.
- *
- * Values:
- * - 0 - The generation of the channel trigger is disabled.
- * - 1 - The generation of the channel trigger is enabled.
- */
-//@{
-#define BP_FTM_EXTTRIG_CH2TRIG (0U) //!< Bit position for FTM_EXTTRIG_CH2TRIG.
-#define BM_FTM_EXTTRIG_CH2TRIG (0x00000001U) //!< Bit mask for FTM_EXTTRIG_CH2TRIG.
-#define BS_FTM_EXTTRIG_CH2TRIG (1U) //!< Bit field size in bits for FTM_EXTTRIG_CH2TRIG.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_EXTTRIG_CH2TRIG field.
-#define BR_FTM_EXTTRIG_CH2TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH2TRIG))
-#endif
-
-//! @brief Format value for bitfield FTM_EXTTRIG_CH2TRIG.
-#define BF_FTM_EXTTRIG_CH2TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH2TRIG), uint32_t) & BM_FTM_EXTTRIG_CH2TRIG)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH2TRIG field to a new value.
-#define BW_FTM_EXTTRIG_CH2TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH2TRIG) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_EXTTRIG, field CH3TRIG[1] (RW)
- *
- * Enables the generation of the channel trigger when the FTM counter is equal
- * to the CnV register.
- *
- * Values:
- * - 0 - The generation of the channel trigger is disabled.
- * - 1 - The generation of the channel trigger is enabled.
- */
-//@{
-#define BP_FTM_EXTTRIG_CH3TRIG (1U) //!< Bit position for FTM_EXTTRIG_CH3TRIG.
-#define BM_FTM_EXTTRIG_CH3TRIG (0x00000002U) //!< Bit mask for FTM_EXTTRIG_CH3TRIG.
-#define BS_FTM_EXTTRIG_CH3TRIG (1U) //!< Bit field size in bits for FTM_EXTTRIG_CH3TRIG.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_EXTTRIG_CH3TRIG field.
-#define BR_FTM_EXTTRIG_CH3TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH3TRIG))
-#endif
-
-//! @brief Format value for bitfield FTM_EXTTRIG_CH3TRIG.
-#define BF_FTM_EXTTRIG_CH3TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH3TRIG), uint32_t) & BM_FTM_EXTTRIG_CH3TRIG)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH3TRIG field to a new value.
-#define BW_FTM_EXTTRIG_CH3TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH3TRIG) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_EXTTRIG, field CH4TRIG[2] (RW)
- *
- * Enables the generation of the channel trigger when the FTM counter is equal
- * to the CnV register.
- *
- * Values:
- * - 0 - The generation of the channel trigger is disabled.
- * - 1 - The generation of the channel trigger is enabled.
- */
-//@{
-#define BP_FTM_EXTTRIG_CH4TRIG (2U) //!< Bit position for FTM_EXTTRIG_CH4TRIG.
-#define BM_FTM_EXTTRIG_CH4TRIG (0x00000004U) //!< Bit mask for FTM_EXTTRIG_CH4TRIG.
-#define BS_FTM_EXTTRIG_CH4TRIG (1U) //!< Bit field size in bits for FTM_EXTTRIG_CH4TRIG.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_EXTTRIG_CH4TRIG field.
-#define BR_FTM_EXTTRIG_CH4TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH4TRIG))
-#endif
-
-//! @brief Format value for bitfield FTM_EXTTRIG_CH4TRIG.
-#define BF_FTM_EXTTRIG_CH4TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH4TRIG), uint32_t) & BM_FTM_EXTTRIG_CH4TRIG)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH4TRIG field to a new value.
-#define BW_FTM_EXTTRIG_CH4TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH4TRIG) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_EXTTRIG, field CH5TRIG[3] (RW)
- *
- * Enables the generation of the channel trigger when the FTM counter is equal
- * to the CnV register.
- *
- * Values:
- * - 0 - The generation of the channel trigger is disabled.
- * - 1 - The generation of the channel trigger is enabled.
- */
-//@{
-#define BP_FTM_EXTTRIG_CH5TRIG (3U) //!< Bit position for FTM_EXTTRIG_CH5TRIG.
-#define BM_FTM_EXTTRIG_CH5TRIG (0x00000008U) //!< Bit mask for FTM_EXTTRIG_CH5TRIG.
-#define BS_FTM_EXTTRIG_CH5TRIG (1U) //!< Bit field size in bits for FTM_EXTTRIG_CH5TRIG.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_EXTTRIG_CH5TRIG field.
-#define BR_FTM_EXTTRIG_CH5TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH5TRIG))
-#endif
-
-//! @brief Format value for bitfield FTM_EXTTRIG_CH5TRIG.
-#define BF_FTM_EXTTRIG_CH5TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH5TRIG), uint32_t) & BM_FTM_EXTTRIG_CH5TRIG)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH5TRIG field to a new value.
-#define BW_FTM_EXTTRIG_CH5TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH5TRIG) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_EXTTRIG, field CH0TRIG[4] (RW)
- *
- * Enables the generation of the channel trigger when the FTM counter is equal
- * to the CnV register.
- *
- * Values:
- * - 0 - The generation of the channel trigger is disabled.
- * - 1 - The generation of the channel trigger is enabled.
- */
-//@{
-#define BP_FTM_EXTTRIG_CH0TRIG (4U) //!< Bit position for FTM_EXTTRIG_CH0TRIG.
-#define BM_FTM_EXTTRIG_CH0TRIG (0x00000010U) //!< Bit mask for FTM_EXTTRIG_CH0TRIG.
-#define BS_FTM_EXTTRIG_CH0TRIG (1U) //!< Bit field size in bits for FTM_EXTTRIG_CH0TRIG.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_EXTTRIG_CH0TRIG field.
-#define BR_FTM_EXTTRIG_CH0TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH0TRIG))
-#endif
-
-//! @brief Format value for bitfield FTM_EXTTRIG_CH0TRIG.
-#define BF_FTM_EXTTRIG_CH0TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH0TRIG), uint32_t) & BM_FTM_EXTTRIG_CH0TRIG)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH0TRIG field to a new value.
-#define BW_FTM_EXTTRIG_CH0TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH0TRIG) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_EXTTRIG, field CH1TRIG[5] (RW)
- *
- * Enables the generation of the channel trigger when the FTM counter is equal
- * to the CnV register.
- *
- * Values:
- * - 0 - The generation of the channel trigger is disabled.
- * - 1 - The generation of the channel trigger is enabled.
- */
-//@{
-#define BP_FTM_EXTTRIG_CH1TRIG (5U) //!< Bit position for FTM_EXTTRIG_CH1TRIG.
-#define BM_FTM_EXTTRIG_CH1TRIG (0x00000020U) //!< Bit mask for FTM_EXTTRIG_CH1TRIG.
-#define BS_FTM_EXTTRIG_CH1TRIG (1U) //!< Bit field size in bits for FTM_EXTTRIG_CH1TRIG.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_EXTTRIG_CH1TRIG field.
-#define BR_FTM_EXTTRIG_CH1TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH1TRIG))
-#endif
-
-//! @brief Format value for bitfield FTM_EXTTRIG_CH1TRIG.
-#define BF_FTM_EXTTRIG_CH1TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH1TRIG), uint32_t) & BM_FTM_EXTTRIG_CH1TRIG)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH1TRIG field to a new value.
-#define BW_FTM_EXTTRIG_CH1TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH1TRIG) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_EXTTRIG, field INITTRIGEN[6] (RW)
- *
- * Enables the generation of the trigger when the FTM counter is equal to the
- * CNTIN register.
- *
- * Values:
- * - 0 - The generation of initialization trigger is disabled.
- * - 1 - The generation of initialization trigger is enabled.
- */
-//@{
-#define BP_FTM_EXTTRIG_INITTRIGEN (6U) //!< Bit position for FTM_EXTTRIG_INITTRIGEN.
-#define BM_FTM_EXTTRIG_INITTRIGEN (0x00000040U) //!< Bit mask for FTM_EXTTRIG_INITTRIGEN.
-#define BS_FTM_EXTTRIG_INITTRIGEN (1U) //!< Bit field size in bits for FTM_EXTTRIG_INITTRIGEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_EXTTRIG_INITTRIGEN field.
-#define BR_FTM_EXTTRIG_INITTRIGEN(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_INITTRIGEN))
-#endif
-
-//! @brief Format value for bitfield FTM_EXTTRIG_INITTRIGEN.
-#define BF_FTM_EXTTRIG_INITTRIGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_INITTRIGEN), uint32_t) & BM_FTM_EXTTRIG_INITTRIGEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INITTRIGEN field to a new value.
-#define BW_FTM_EXTTRIG_INITTRIGEN(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_INITTRIGEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_EXTTRIG, field TRIGF[7] (ROWZ)
- *
- * Set by hardware when a channel trigger is generated. Clear TRIGF by reading
- * EXTTRIG while TRIGF is set and then writing a 0 to TRIGF. Writing a 1 to TRIGF
- * has no effect. If another channel trigger is generated before the clearing
- * sequence is completed, the sequence is reset so TRIGF remains set after the clear
- * sequence is completed for the earlier TRIGF.
- *
- * Values:
- * - 0 - No channel trigger was generated.
- * - 1 - A channel trigger was generated.
- */
-//@{
-#define BP_FTM_EXTTRIG_TRIGF (7U) //!< Bit position for FTM_EXTTRIG_TRIGF.
-#define BM_FTM_EXTTRIG_TRIGF (0x00000080U) //!< Bit mask for FTM_EXTTRIG_TRIGF.
-#define BS_FTM_EXTTRIG_TRIGF (1U) //!< Bit field size in bits for FTM_EXTTRIG_TRIGF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_EXTTRIG_TRIGF field.
-#define BR_FTM_EXTTRIG_TRIGF(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_TRIGF))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTM_POL - Channels Polarity
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTM_POL - Channels Polarity (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register defines the output polarity of the FTM channels. The safe value
- * that is driven in a channel output when the fault control is enabled and a
- * fault condition is detected is the inactive state of the channel. That is, the
- * safe value of a channel is the value of its POL bit.
- */
-typedef union _hw_ftm_pol
-{
- uint32_t U;
- struct _hw_ftm_pol_bitfields
- {
- uint32_t POL0 : 1; //!< [0] Channel 0 Polarity
- uint32_t POL1 : 1; //!< [1] Channel 1 Polarity
- uint32_t POL2 : 1; //!< [2] Channel 2 Polarity
- uint32_t POL3 : 1; //!< [3] Channel 3 Polarity
- uint32_t POL4 : 1; //!< [4] Channel 4 Polarity
- uint32_t POL5 : 1; //!< [5] Channel 5 Polarity
- uint32_t POL6 : 1; //!< [6] Channel 6 Polarity
- uint32_t POL7 : 1; //!< [7] Channel 7 Polarity
- uint32_t RESERVED0 : 24; //!< [31:8]
- } B;
-} hw_ftm_pol_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTM_POL register
- */
-//@{
-#define HW_FTM_POL_ADDR(x) (REGS_FTM_BASE(x) + 0x70U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTM_POL(x) (*(__IO hw_ftm_pol_t *) HW_FTM_POL_ADDR(x))
-#define HW_FTM_POL_RD(x) (HW_FTM_POL(x).U)
-#define HW_FTM_POL_WR(x, v) (HW_FTM_POL(x).U = (v))
-#define HW_FTM_POL_SET(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) | (v)))
-#define HW_FTM_POL_CLR(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) & ~(v)))
-#define HW_FTM_POL_TOG(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTM_POL bitfields
- */
-
-/*!
- * @name Register FTM_POL, field POL0[0] (RW)
- *
- * Defines the polarity of the channel output. This field is write protected. It
- * can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - The channel polarity is active high.
- * - 1 - The channel polarity is active low.
- */
-//@{
-#define BP_FTM_POL_POL0 (0U) //!< Bit position for FTM_POL_POL0.
-#define BM_FTM_POL_POL0 (0x00000001U) //!< Bit mask for FTM_POL_POL0.
-#define BS_FTM_POL_POL0 (1U) //!< Bit field size in bits for FTM_POL_POL0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_POL_POL0 field.
-#define BR_FTM_POL_POL0(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL0))
-#endif
-
-//! @brief Format value for bitfield FTM_POL_POL0.
-#define BF_FTM_POL_POL0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL0), uint32_t) & BM_FTM_POL_POL0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the POL0 field to a new value.
-#define BW_FTM_POL_POL0(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_POL, field POL1[1] (RW)
- *
- * Defines the polarity of the channel output. This field is write protected. It
- * can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - The channel polarity is active high.
- * - 1 - The channel polarity is active low.
- */
-//@{
-#define BP_FTM_POL_POL1 (1U) //!< Bit position for FTM_POL_POL1.
-#define BM_FTM_POL_POL1 (0x00000002U) //!< Bit mask for FTM_POL_POL1.
-#define BS_FTM_POL_POL1 (1U) //!< Bit field size in bits for FTM_POL_POL1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_POL_POL1 field.
-#define BR_FTM_POL_POL1(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL1))
-#endif
-
-//! @brief Format value for bitfield FTM_POL_POL1.
-#define BF_FTM_POL_POL1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL1), uint32_t) & BM_FTM_POL_POL1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the POL1 field to a new value.
-#define BW_FTM_POL_POL1(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_POL, field POL2[2] (RW)
- *
- * Defines the polarity of the channel output. This field is write protected. It
- * can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - The channel polarity is active high.
- * - 1 - The channel polarity is active low.
- */
-//@{
-#define BP_FTM_POL_POL2 (2U) //!< Bit position for FTM_POL_POL2.
-#define BM_FTM_POL_POL2 (0x00000004U) //!< Bit mask for FTM_POL_POL2.
-#define BS_FTM_POL_POL2 (1U) //!< Bit field size in bits for FTM_POL_POL2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_POL_POL2 field.
-#define BR_FTM_POL_POL2(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL2))
-#endif
-
-//! @brief Format value for bitfield FTM_POL_POL2.
-#define BF_FTM_POL_POL2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL2), uint32_t) & BM_FTM_POL_POL2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the POL2 field to a new value.
-#define BW_FTM_POL_POL2(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_POL, field POL3[3] (RW)
- *
- * Defines the polarity of the channel output. This field is write protected. It
- * can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - The channel polarity is active high.
- * - 1 - The channel polarity is active low.
- */
-//@{
-#define BP_FTM_POL_POL3 (3U) //!< Bit position for FTM_POL_POL3.
-#define BM_FTM_POL_POL3 (0x00000008U) //!< Bit mask for FTM_POL_POL3.
-#define BS_FTM_POL_POL3 (1U) //!< Bit field size in bits for FTM_POL_POL3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_POL_POL3 field.
-#define BR_FTM_POL_POL3(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL3))
-#endif
-
-//! @brief Format value for bitfield FTM_POL_POL3.
-#define BF_FTM_POL_POL3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL3), uint32_t) & BM_FTM_POL_POL3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the POL3 field to a new value.
-#define BW_FTM_POL_POL3(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_POL, field POL4[4] (RW)
- *
- * Defines the polarity of the channel output. This field is write protected. It
- * can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - The channel polarity is active high.
- * - 1 - The channel polarity is active low.
- */
-//@{
-#define BP_FTM_POL_POL4 (4U) //!< Bit position for FTM_POL_POL4.
-#define BM_FTM_POL_POL4 (0x00000010U) //!< Bit mask for FTM_POL_POL4.
-#define BS_FTM_POL_POL4 (1U) //!< Bit field size in bits for FTM_POL_POL4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_POL_POL4 field.
-#define BR_FTM_POL_POL4(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL4))
-#endif
-
-//! @brief Format value for bitfield FTM_POL_POL4.
-#define BF_FTM_POL_POL4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL4), uint32_t) & BM_FTM_POL_POL4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the POL4 field to a new value.
-#define BW_FTM_POL_POL4(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_POL, field POL5[5] (RW)
- *
- * Defines the polarity of the channel output. This field is write protected. It
- * can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - The channel polarity is active high.
- * - 1 - The channel polarity is active low.
- */
-//@{
-#define BP_FTM_POL_POL5 (5U) //!< Bit position for FTM_POL_POL5.
-#define BM_FTM_POL_POL5 (0x00000020U) //!< Bit mask for FTM_POL_POL5.
-#define BS_FTM_POL_POL5 (1U) //!< Bit field size in bits for FTM_POL_POL5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_POL_POL5 field.
-#define BR_FTM_POL_POL5(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL5))
-#endif
-
-//! @brief Format value for bitfield FTM_POL_POL5.
-#define BF_FTM_POL_POL5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL5), uint32_t) & BM_FTM_POL_POL5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the POL5 field to a new value.
-#define BW_FTM_POL_POL5(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_POL, field POL6[6] (RW)
- *
- * Defines the polarity of the channel output. This field is write protected. It
- * can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - The channel polarity is active high.
- * - 1 - The channel polarity is active low.
- */
-//@{
-#define BP_FTM_POL_POL6 (6U) //!< Bit position for FTM_POL_POL6.
-#define BM_FTM_POL_POL6 (0x00000040U) //!< Bit mask for FTM_POL_POL6.
-#define BS_FTM_POL_POL6 (1U) //!< Bit field size in bits for FTM_POL_POL6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_POL_POL6 field.
-#define BR_FTM_POL_POL6(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL6))
-#endif
-
-//! @brief Format value for bitfield FTM_POL_POL6.
-#define BF_FTM_POL_POL6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL6), uint32_t) & BM_FTM_POL_POL6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the POL6 field to a new value.
-#define BW_FTM_POL_POL6(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_POL, field POL7[7] (RW)
- *
- * Defines the polarity of the channel output. This field is write protected. It
- * can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - The channel polarity is active high.
- * - 1 - The channel polarity is active low.
- */
-//@{
-#define BP_FTM_POL_POL7 (7U) //!< Bit position for FTM_POL_POL7.
-#define BM_FTM_POL_POL7 (0x00000080U) //!< Bit mask for FTM_POL_POL7.
-#define BS_FTM_POL_POL7 (1U) //!< Bit field size in bits for FTM_POL_POL7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_POL_POL7 field.
-#define BR_FTM_POL_POL7(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL7))
-#endif
-
-//! @brief Format value for bitfield FTM_POL_POL7.
-#define BF_FTM_POL_POL7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL7), uint32_t) & BM_FTM_POL_POL7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the POL7 field to a new value.
-#define BW_FTM_POL_POL7(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL7) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTM_FMS - Fault Mode Status
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTM_FMS - Fault Mode Status (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register contains the fault detection flags, write protection enable
- * bit, and the logic OR of the enabled fault inputs.
- */
-typedef union _hw_ftm_fms
-{
- uint32_t U;
- struct _hw_ftm_fms_bitfields
- {
- uint32_t FAULTF0 : 1; //!< [0] Fault Detection Flag 0
- uint32_t FAULTF1 : 1; //!< [1] Fault Detection Flag 1
- uint32_t FAULTF2 : 1; //!< [2] Fault Detection Flag 2
- uint32_t FAULTF3 : 1; //!< [3] Fault Detection Flag 3
- uint32_t RESERVED0 : 1; //!< [4]
- uint32_t FAULTIN : 1; //!< [5] Fault Inputs
- uint32_t WPEN : 1; //!< [6] Write Protection Enable
- uint32_t FAULTF : 1; //!< [7] Fault Detection Flag
- uint32_t RESERVED1 : 24; //!< [31:8]
- } B;
-} hw_ftm_fms_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTM_FMS register
- */
-//@{
-#define HW_FTM_FMS_ADDR(x) (REGS_FTM_BASE(x) + 0x74U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTM_FMS(x) (*(__IO hw_ftm_fms_t *) HW_FTM_FMS_ADDR(x))
-#define HW_FTM_FMS_RD(x) (HW_FTM_FMS(x).U)
-#define HW_FTM_FMS_WR(x, v) (HW_FTM_FMS(x).U = (v))
-#define HW_FTM_FMS_SET(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) | (v)))
-#define HW_FTM_FMS_CLR(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) & ~(v)))
-#define HW_FTM_FMS_TOG(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTM_FMS bitfields
- */
-
-/*!
- * @name Register FTM_FMS, field FAULTF0[0] (ROWZ)
- *
- * Set by hardware when fault control is enabled, the corresponding fault input
- * is enabled and a fault condition is detected at the fault input. Clear FAULTF0
- * by reading the FMS register while FAULTF0 is set and then writing a 0 to
- * FAULTF0 while there is no existing fault condition at the corresponding fault
- * input. Writing a 1 to FAULTF0 has no effect. FAULTF0 bit is also cleared when
- * FAULTF bit is cleared. If another fault condition is detected at the corresponding
- * fault input before the clearing sequence is completed, the sequence is reset
- * so FAULTF0 remains set after the clearing sequence is completed for the
- * earlier fault condition.
- *
- * Values:
- * - 0 - No fault condition was detected at the fault input.
- * - 1 - A fault condition was detected at the fault input.
- */
-//@{
-#define BP_FTM_FMS_FAULTF0 (0U) //!< Bit position for FTM_FMS_FAULTF0.
-#define BM_FTM_FMS_FAULTF0 (0x00000001U) //!< Bit mask for FTM_FMS_FAULTF0.
-#define BS_FTM_FMS_FAULTF0 (1U) //!< Bit field size in bits for FTM_FMS_FAULTF0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_FMS_FAULTF0 field.
-#define BR_FTM_FMS_FAULTF0(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF0))
-#endif
-//@}
-
-/*!
- * @name Register FTM_FMS, field FAULTF1[1] (ROWZ)
- *
- * Set by hardware when fault control is enabled, the corresponding fault input
- * is enabled and a fault condition is detected at the fault input. Clear FAULTF1
- * by reading the FMS register while FAULTF1 is set and then writing a 0 to
- * FAULTF1 while there is no existing fault condition at the corresponding fault
- * input. Writing a 1 to FAULTF1 has no effect. FAULTF1 bit is also cleared when
- * FAULTF bit is cleared. If another fault condition is detected at the corresponding
- * fault input before the clearing sequence is completed, the sequence is reset
- * so FAULTF1 remains set after the clearing sequence is completed for the
- * earlier fault condition.
- *
- * Values:
- * - 0 - No fault condition was detected at the fault input.
- * - 1 - A fault condition was detected at the fault input.
- */
-//@{
-#define BP_FTM_FMS_FAULTF1 (1U) //!< Bit position for FTM_FMS_FAULTF1.
-#define BM_FTM_FMS_FAULTF1 (0x00000002U) //!< Bit mask for FTM_FMS_FAULTF1.
-#define BS_FTM_FMS_FAULTF1 (1U) //!< Bit field size in bits for FTM_FMS_FAULTF1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_FMS_FAULTF1 field.
-#define BR_FTM_FMS_FAULTF1(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF1))
-#endif
-//@}
-
-/*!
- * @name Register FTM_FMS, field FAULTF2[2] (ROWZ)
- *
- * Set by hardware when fault control is enabled, the corresponding fault input
- * is enabled and a fault condition is detected at the fault input. Clear FAULTF2
- * by reading the FMS register while FAULTF2 is set and then writing a 0 to
- * FAULTF2 while there is no existing fault condition at the corresponding fault
- * input. Writing a 1 to FAULTF2 has no effect. FAULTF2 bit is also cleared when
- * FAULTF bit is cleared. If another fault condition is detected at the corresponding
- * fault input before the clearing sequence is completed, the sequence is reset
- * so FAULTF2 remains set after the clearing sequence is completed for the
- * earlier fault condition.
- *
- * Values:
- * - 0 - No fault condition was detected at the fault input.
- * - 1 - A fault condition was detected at the fault input.
- */
-//@{
-#define BP_FTM_FMS_FAULTF2 (2U) //!< Bit position for FTM_FMS_FAULTF2.
-#define BM_FTM_FMS_FAULTF2 (0x00000004U) //!< Bit mask for FTM_FMS_FAULTF2.
-#define BS_FTM_FMS_FAULTF2 (1U) //!< Bit field size in bits for FTM_FMS_FAULTF2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_FMS_FAULTF2 field.
-#define BR_FTM_FMS_FAULTF2(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF2))
-#endif
-//@}
-
-/*!
- * @name Register FTM_FMS, field FAULTF3[3] (ROWZ)
- *
- * Set by hardware when fault control is enabled, the corresponding fault input
- * is enabled and a fault condition is detected at the fault input. Clear FAULTF3
- * by reading the FMS register while FAULTF3 is set and then writing a 0 to
- * FAULTF3 while there is no existing fault condition at the corresponding fault
- * input. Writing a 1 to FAULTF3 has no effect. FAULTF3 bit is also cleared when
- * FAULTF bit is cleared. If another fault condition is detected at the corresponding
- * fault input before the clearing sequence is completed, the sequence is reset
- * so FAULTF3 remains set after the clearing sequence is completed for the
- * earlier fault condition.
- *
- * Values:
- * - 0 - No fault condition was detected at the fault input.
- * - 1 - A fault condition was detected at the fault input.
- */
-//@{
-#define BP_FTM_FMS_FAULTF3 (3U) //!< Bit position for FTM_FMS_FAULTF3.
-#define BM_FTM_FMS_FAULTF3 (0x00000008U) //!< Bit mask for FTM_FMS_FAULTF3.
-#define BS_FTM_FMS_FAULTF3 (1U) //!< Bit field size in bits for FTM_FMS_FAULTF3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_FMS_FAULTF3 field.
-#define BR_FTM_FMS_FAULTF3(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF3))
-#endif
-//@}
-
-/*!
- * @name Register FTM_FMS, field FAULTIN[5] (RO)
- *
- * Represents the logic OR of the enabled fault inputs after their filter (if
- * their filter is enabled) when fault control is enabled.
- *
- * Values:
- * - 0 - The logic OR of the enabled fault inputs is 0.
- * - 1 - The logic OR of the enabled fault inputs is 1.
- */
-//@{
-#define BP_FTM_FMS_FAULTIN (5U) //!< Bit position for FTM_FMS_FAULTIN.
-#define BM_FTM_FMS_FAULTIN (0x00000020U) //!< Bit mask for FTM_FMS_FAULTIN.
-#define BS_FTM_FMS_FAULTIN (1U) //!< Bit field size in bits for FTM_FMS_FAULTIN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_FMS_FAULTIN field.
-#define BR_FTM_FMS_FAULTIN(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTIN))
-#endif
-//@}
-
-/*!
- * @name Register FTM_FMS, field WPEN[6] (RW)
- *
- * The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written
- * to it. WPEN is cleared when WPEN bit is read as a 1 and then 1 is written to
- * WPDIS. Writing 0 to WPEN has no effect.
- *
- * Values:
- * - 0 - Write protection is disabled. Write protected bits can be written.
- * - 1 - Write protection is enabled. Write protected bits cannot be written.
- */
-//@{
-#define BP_FTM_FMS_WPEN (6U) //!< Bit position for FTM_FMS_WPEN.
-#define BM_FTM_FMS_WPEN (0x00000040U) //!< Bit mask for FTM_FMS_WPEN.
-#define BS_FTM_FMS_WPEN (1U) //!< Bit field size in bits for FTM_FMS_WPEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_FMS_WPEN field.
-#define BR_FTM_FMS_WPEN(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_WPEN))
-#endif
-
-//! @brief Format value for bitfield FTM_FMS_WPEN.
-#define BF_FTM_FMS_WPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FMS_WPEN), uint32_t) & BM_FTM_FMS_WPEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WPEN field to a new value.
-#define BW_FTM_FMS_WPEN(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_WPEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_FMS, field FAULTF[7] (ROWZ)
- *
- * Represents the logic OR of the individual FAULTFj bits where j = 3, 2, 1, 0.
- * Clear FAULTF by reading the FMS register while FAULTF is set and then writing
- * a 0 to FAULTF while there is no existing fault condition at the enabled fault
- * inputs. Writing a 1 to FAULTF has no effect. If another fault condition is
- * detected in an enabled fault input before the clearing sequence is completed, the
- * sequence is reset so FAULTF remains set after the clearing sequence is
- * completed for the earlier fault condition. FAULTF is also cleared when FAULTFj bits
- * are cleared individually.
- *
- * Values:
- * - 0 - No fault condition was detected.
- * - 1 - A fault condition was detected.
- */
-//@{
-#define BP_FTM_FMS_FAULTF (7U) //!< Bit position for FTM_FMS_FAULTF.
-#define BM_FTM_FMS_FAULTF (0x00000080U) //!< Bit mask for FTM_FMS_FAULTF.
-#define BS_FTM_FMS_FAULTF (1U) //!< Bit field size in bits for FTM_FMS_FAULTF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_FMS_FAULTF field.
-#define BR_FTM_FMS_FAULTF(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTM_FILTER - Input Capture Filter Control
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTM_FILTER - Input Capture Filter Control (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register selects the filter value for the inputs of channels. Channels
- * 4, 5, 6 and 7 do not have an input filter. Writing to the FILTER register has
- * immediate effect and must be done only when the channels 0, 1, 2, and 3 are not
- * in input modes. Failure to do this could result in a missing valid signal.
- */
-typedef union _hw_ftm_filter
-{
- uint32_t U;
- struct _hw_ftm_filter_bitfields
- {
- uint32_t CH0FVAL : 4; //!< [3:0] Channel 0 Input Filter
- uint32_t CH1FVAL : 4; //!< [7:4] Channel 1 Input Filter
- uint32_t CH2FVAL : 4; //!< [11:8] Channel 2 Input Filter
- uint32_t CH3FVAL : 4; //!< [15:12] Channel 3 Input Filter
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_ftm_filter_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTM_FILTER register
- */
-//@{
-#define HW_FTM_FILTER_ADDR(x) (REGS_FTM_BASE(x) + 0x78U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTM_FILTER(x) (*(__IO hw_ftm_filter_t *) HW_FTM_FILTER_ADDR(x))
-#define HW_FTM_FILTER_RD(x) (HW_FTM_FILTER(x).U)
-#define HW_FTM_FILTER_WR(x, v) (HW_FTM_FILTER(x).U = (v))
-#define HW_FTM_FILTER_SET(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) | (v)))
-#define HW_FTM_FILTER_CLR(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) & ~(v)))
-#define HW_FTM_FILTER_TOG(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTM_FILTER bitfields
- */
-
-/*!
- * @name Register FTM_FILTER, field CH0FVAL[3:0] (RW)
- *
- * Selects the filter value for the channel input. The filter is disabled when
- * the value is zero.
- */
-//@{
-#define BP_FTM_FILTER_CH0FVAL (0U) //!< Bit position for FTM_FILTER_CH0FVAL.
-#define BM_FTM_FILTER_CH0FVAL (0x0000000FU) //!< Bit mask for FTM_FILTER_CH0FVAL.
-#define BS_FTM_FILTER_CH0FVAL (4U) //!< Bit field size in bits for FTM_FILTER_CH0FVAL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_FILTER_CH0FVAL field.
-#define BR_FTM_FILTER_CH0FVAL(x) (HW_FTM_FILTER(x).B.CH0FVAL)
-#endif
-
-//! @brief Format value for bitfield FTM_FILTER_CH0FVAL.
-#define BF_FTM_FILTER_CH0FVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FILTER_CH0FVAL), uint32_t) & BM_FTM_FILTER_CH0FVAL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH0FVAL field to a new value.
-#define BW_FTM_FILTER_CH0FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH0FVAL) | BF_FTM_FILTER_CH0FVAL(v)))
-#endif
-//@}
-
-/*!
- * @name Register FTM_FILTER, field CH1FVAL[7:4] (RW)
- *
- * Selects the filter value for the channel input. The filter is disabled when
- * the value is zero.
- */
-//@{
-#define BP_FTM_FILTER_CH1FVAL (4U) //!< Bit position for FTM_FILTER_CH1FVAL.
-#define BM_FTM_FILTER_CH1FVAL (0x000000F0U) //!< Bit mask for FTM_FILTER_CH1FVAL.
-#define BS_FTM_FILTER_CH1FVAL (4U) //!< Bit field size in bits for FTM_FILTER_CH1FVAL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_FILTER_CH1FVAL field.
-#define BR_FTM_FILTER_CH1FVAL(x) (HW_FTM_FILTER(x).B.CH1FVAL)
-#endif
-
-//! @brief Format value for bitfield FTM_FILTER_CH1FVAL.
-#define BF_FTM_FILTER_CH1FVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FILTER_CH1FVAL), uint32_t) & BM_FTM_FILTER_CH1FVAL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH1FVAL field to a new value.
-#define BW_FTM_FILTER_CH1FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH1FVAL) | BF_FTM_FILTER_CH1FVAL(v)))
-#endif
-//@}
-
-/*!
- * @name Register FTM_FILTER, field CH2FVAL[11:8] (RW)
- *
- * Selects the filter value for the channel input. The filter is disabled when
- * the value is zero.
- */
-//@{
-#define BP_FTM_FILTER_CH2FVAL (8U) //!< Bit position for FTM_FILTER_CH2FVAL.
-#define BM_FTM_FILTER_CH2FVAL (0x00000F00U) //!< Bit mask for FTM_FILTER_CH2FVAL.
-#define BS_FTM_FILTER_CH2FVAL (4U) //!< Bit field size in bits for FTM_FILTER_CH2FVAL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_FILTER_CH2FVAL field.
-#define BR_FTM_FILTER_CH2FVAL(x) (HW_FTM_FILTER(x).B.CH2FVAL)
-#endif
-
-//! @brief Format value for bitfield FTM_FILTER_CH2FVAL.
-#define BF_FTM_FILTER_CH2FVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FILTER_CH2FVAL), uint32_t) & BM_FTM_FILTER_CH2FVAL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH2FVAL field to a new value.
-#define BW_FTM_FILTER_CH2FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH2FVAL) | BF_FTM_FILTER_CH2FVAL(v)))
-#endif
-//@}
-
-/*!
- * @name Register FTM_FILTER, field CH3FVAL[15:12] (RW)
- *
- * Selects the filter value for the channel input. The filter is disabled when
- * the value is zero.
- */
-//@{
-#define BP_FTM_FILTER_CH3FVAL (12U) //!< Bit position for FTM_FILTER_CH3FVAL.
-#define BM_FTM_FILTER_CH3FVAL (0x0000F000U) //!< Bit mask for FTM_FILTER_CH3FVAL.
-#define BS_FTM_FILTER_CH3FVAL (4U) //!< Bit field size in bits for FTM_FILTER_CH3FVAL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_FILTER_CH3FVAL field.
-#define BR_FTM_FILTER_CH3FVAL(x) (HW_FTM_FILTER(x).B.CH3FVAL)
-#endif
-
-//! @brief Format value for bitfield FTM_FILTER_CH3FVAL.
-#define BF_FTM_FILTER_CH3FVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FILTER_CH3FVAL), uint32_t) & BM_FTM_FILTER_CH3FVAL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH3FVAL field to a new value.
-#define BW_FTM_FILTER_CH3FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH3FVAL) | BF_FTM_FILTER_CH3FVAL(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTM_FLTCTRL - Fault Control
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTM_FLTCTRL - Fault Control (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register selects the filter value for the fault inputs, enables the
- * fault inputs and the fault inputs filter.
- */
-typedef union _hw_ftm_fltctrl
-{
- uint32_t U;
- struct _hw_ftm_fltctrl_bitfields
- {
- uint32_t FAULT0EN : 1; //!< [0] Fault Input 0 Enable
- uint32_t FAULT1EN : 1; //!< [1] Fault Input 1 Enable
- uint32_t FAULT2EN : 1; //!< [2] Fault Input 2 Enable
- uint32_t FAULT3EN : 1; //!< [3] Fault Input 3 Enable
- uint32_t FFLTR0EN : 1; //!< [4] Fault Input 0 Filter Enable
- uint32_t FFLTR1EN : 1; //!< [5] Fault Input 1 Filter Enable
- uint32_t FFLTR2EN : 1; //!< [6] Fault Input 2 Filter Enable
- uint32_t FFLTR3EN : 1; //!< [7] Fault Input 3 Filter Enable
- uint32_t FFVAL : 4; //!< [11:8] Fault Input Filter
- uint32_t RESERVED0 : 20; //!< [31:12]
- } B;
-} hw_ftm_fltctrl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTM_FLTCTRL register
- */
-//@{
-#define HW_FTM_FLTCTRL_ADDR(x) (REGS_FTM_BASE(x) + 0x7CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTM_FLTCTRL(x) (*(__IO hw_ftm_fltctrl_t *) HW_FTM_FLTCTRL_ADDR(x))
-#define HW_FTM_FLTCTRL_RD(x) (HW_FTM_FLTCTRL(x).U)
-#define HW_FTM_FLTCTRL_WR(x, v) (HW_FTM_FLTCTRL(x).U = (v))
-#define HW_FTM_FLTCTRL_SET(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) | (v)))
-#define HW_FTM_FLTCTRL_CLR(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) & ~(v)))
-#define HW_FTM_FLTCTRL_TOG(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTM_FLTCTRL bitfields
- */
-
-/*!
- * @name Register FTM_FLTCTRL, field FAULT0EN[0] (RW)
- *
- * Enables the fault input. This field is write protected. It can be written
- * only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - Fault input is disabled.
- * - 1 - Fault input is enabled.
- */
-//@{
-#define BP_FTM_FLTCTRL_FAULT0EN (0U) //!< Bit position for FTM_FLTCTRL_FAULT0EN.
-#define BM_FTM_FLTCTRL_FAULT0EN (0x00000001U) //!< Bit mask for FTM_FLTCTRL_FAULT0EN.
-#define BS_FTM_FLTCTRL_FAULT0EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FAULT0EN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_FLTCTRL_FAULT0EN field.
-#define BR_FTM_FLTCTRL_FAULT0EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT0EN))
-#endif
-
-//! @brief Format value for bitfield FTM_FLTCTRL_FAULT0EN.
-#define BF_FTM_FLTCTRL_FAULT0EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FAULT0EN), uint32_t) & BM_FTM_FLTCTRL_FAULT0EN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FAULT0EN field to a new value.
-#define BW_FTM_FLTCTRL_FAULT0EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT0EN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_FLTCTRL, field FAULT1EN[1] (RW)
- *
- * Enables the fault input. This field is write protected. It can be written
- * only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - Fault input is disabled.
- * - 1 - Fault input is enabled.
- */
-//@{
-#define BP_FTM_FLTCTRL_FAULT1EN (1U) //!< Bit position for FTM_FLTCTRL_FAULT1EN.
-#define BM_FTM_FLTCTRL_FAULT1EN (0x00000002U) //!< Bit mask for FTM_FLTCTRL_FAULT1EN.
-#define BS_FTM_FLTCTRL_FAULT1EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FAULT1EN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_FLTCTRL_FAULT1EN field.
-#define BR_FTM_FLTCTRL_FAULT1EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT1EN))
-#endif
-
-//! @brief Format value for bitfield FTM_FLTCTRL_FAULT1EN.
-#define BF_FTM_FLTCTRL_FAULT1EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FAULT1EN), uint32_t) & BM_FTM_FLTCTRL_FAULT1EN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FAULT1EN field to a new value.
-#define BW_FTM_FLTCTRL_FAULT1EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT1EN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_FLTCTRL, field FAULT2EN[2] (RW)
- *
- * Enables the fault input. This field is write protected. It can be written
- * only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - Fault input is disabled.
- * - 1 - Fault input is enabled.
- */
-//@{
-#define BP_FTM_FLTCTRL_FAULT2EN (2U) //!< Bit position for FTM_FLTCTRL_FAULT2EN.
-#define BM_FTM_FLTCTRL_FAULT2EN (0x00000004U) //!< Bit mask for FTM_FLTCTRL_FAULT2EN.
-#define BS_FTM_FLTCTRL_FAULT2EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FAULT2EN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_FLTCTRL_FAULT2EN field.
-#define BR_FTM_FLTCTRL_FAULT2EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT2EN))
-#endif
-
-//! @brief Format value for bitfield FTM_FLTCTRL_FAULT2EN.
-#define BF_FTM_FLTCTRL_FAULT2EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FAULT2EN), uint32_t) & BM_FTM_FLTCTRL_FAULT2EN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FAULT2EN field to a new value.
-#define BW_FTM_FLTCTRL_FAULT2EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT2EN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_FLTCTRL, field FAULT3EN[3] (RW)
- *
- * Enables the fault input. This field is write protected. It can be written
- * only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - Fault input is disabled.
- * - 1 - Fault input is enabled.
- */
-//@{
-#define BP_FTM_FLTCTRL_FAULT3EN (3U) //!< Bit position for FTM_FLTCTRL_FAULT3EN.
-#define BM_FTM_FLTCTRL_FAULT3EN (0x00000008U) //!< Bit mask for FTM_FLTCTRL_FAULT3EN.
-#define BS_FTM_FLTCTRL_FAULT3EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FAULT3EN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_FLTCTRL_FAULT3EN field.
-#define BR_FTM_FLTCTRL_FAULT3EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT3EN))
-#endif
-
-//! @brief Format value for bitfield FTM_FLTCTRL_FAULT3EN.
-#define BF_FTM_FLTCTRL_FAULT3EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FAULT3EN), uint32_t) & BM_FTM_FLTCTRL_FAULT3EN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FAULT3EN field to a new value.
-#define BW_FTM_FLTCTRL_FAULT3EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT3EN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_FLTCTRL, field FFLTR0EN[4] (RW)
- *
- * Enables the filter for the fault input. This field is write protected. It can
- * be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - Fault input filter is disabled.
- * - 1 - Fault input filter is enabled.
- */
-//@{
-#define BP_FTM_FLTCTRL_FFLTR0EN (4U) //!< Bit position for FTM_FLTCTRL_FFLTR0EN.
-#define BM_FTM_FLTCTRL_FFLTR0EN (0x00000010U) //!< Bit mask for FTM_FLTCTRL_FFLTR0EN.
-#define BS_FTM_FLTCTRL_FFLTR0EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FFLTR0EN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_FLTCTRL_FFLTR0EN field.
-#define BR_FTM_FLTCTRL_FFLTR0EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR0EN))
-#endif
-
-//! @brief Format value for bitfield FTM_FLTCTRL_FFLTR0EN.
-#define BF_FTM_FLTCTRL_FFLTR0EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FFLTR0EN), uint32_t) & BM_FTM_FLTCTRL_FFLTR0EN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FFLTR0EN field to a new value.
-#define BW_FTM_FLTCTRL_FFLTR0EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR0EN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_FLTCTRL, field FFLTR1EN[5] (RW)
- *
- * Enables the filter for the fault input. This field is write protected. It can
- * be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - Fault input filter is disabled.
- * - 1 - Fault input filter is enabled.
- */
-//@{
-#define BP_FTM_FLTCTRL_FFLTR1EN (5U) //!< Bit position for FTM_FLTCTRL_FFLTR1EN.
-#define BM_FTM_FLTCTRL_FFLTR1EN (0x00000020U) //!< Bit mask for FTM_FLTCTRL_FFLTR1EN.
-#define BS_FTM_FLTCTRL_FFLTR1EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FFLTR1EN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_FLTCTRL_FFLTR1EN field.
-#define BR_FTM_FLTCTRL_FFLTR1EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR1EN))
-#endif
-
-//! @brief Format value for bitfield FTM_FLTCTRL_FFLTR1EN.
-#define BF_FTM_FLTCTRL_FFLTR1EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FFLTR1EN), uint32_t) & BM_FTM_FLTCTRL_FFLTR1EN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FFLTR1EN field to a new value.
-#define BW_FTM_FLTCTRL_FFLTR1EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR1EN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_FLTCTRL, field FFLTR2EN[6] (RW)
- *
- * Enables the filter for the fault input. This field is write protected. It can
- * be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - Fault input filter is disabled.
- * - 1 - Fault input filter is enabled.
- */
-//@{
-#define BP_FTM_FLTCTRL_FFLTR2EN (6U) //!< Bit position for FTM_FLTCTRL_FFLTR2EN.
-#define BM_FTM_FLTCTRL_FFLTR2EN (0x00000040U) //!< Bit mask for FTM_FLTCTRL_FFLTR2EN.
-#define BS_FTM_FLTCTRL_FFLTR2EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FFLTR2EN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_FLTCTRL_FFLTR2EN field.
-#define BR_FTM_FLTCTRL_FFLTR2EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR2EN))
-#endif
-
-//! @brief Format value for bitfield FTM_FLTCTRL_FFLTR2EN.
-#define BF_FTM_FLTCTRL_FFLTR2EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FFLTR2EN), uint32_t) & BM_FTM_FLTCTRL_FFLTR2EN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FFLTR2EN field to a new value.
-#define BW_FTM_FLTCTRL_FFLTR2EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR2EN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_FLTCTRL, field FFLTR3EN[7] (RW)
- *
- * Enables the filter for the fault input. This field is write protected. It can
- * be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - Fault input filter is disabled.
- * - 1 - Fault input filter is enabled.
- */
-//@{
-#define BP_FTM_FLTCTRL_FFLTR3EN (7U) //!< Bit position for FTM_FLTCTRL_FFLTR3EN.
-#define BM_FTM_FLTCTRL_FFLTR3EN (0x00000080U) //!< Bit mask for FTM_FLTCTRL_FFLTR3EN.
-#define BS_FTM_FLTCTRL_FFLTR3EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FFLTR3EN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_FLTCTRL_FFLTR3EN field.
-#define BR_FTM_FLTCTRL_FFLTR3EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR3EN))
-#endif
-
-//! @brief Format value for bitfield FTM_FLTCTRL_FFLTR3EN.
-#define BF_FTM_FLTCTRL_FFLTR3EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FFLTR3EN), uint32_t) & BM_FTM_FLTCTRL_FFLTR3EN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FFLTR3EN field to a new value.
-#define BW_FTM_FLTCTRL_FFLTR3EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR3EN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_FLTCTRL, field FFVAL[11:8] (RW)
- *
- * Selects the filter value for the fault inputs. The fault filter is disabled
- * when the value is zero. Writing to this field has immediate effect and must be
- * done only when the fault control or all fault inputs are disabled. Failure to
- * do this could result in a missing fault detection.
- */
-//@{
-#define BP_FTM_FLTCTRL_FFVAL (8U) //!< Bit position for FTM_FLTCTRL_FFVAL.
-#define BM_FTM_FLTCTRL_FFVAL (0x00000F00U) //!< Bit mask for FTM_FLTCTRL_FFVAL.
-#define BS_FTM_FLTCTRL_FFVAL (4U) //!< Bit field size in bits for FTM_FLTCTRL_FFVAL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_FLTCTRL_FFVAL field.
-#define BR_FTM_FLTCTRL_FFVAL(x) (HW_FTM_FLTCTRL(x).B.FFVAL)
-#endif
-
-//! @brief Format value for bitfield FTM_FLTCTRL_FFVAL.
-#define BF_FTM_FLTCTRL_FFVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FFVAL), uint32_t) & BM_FTM_FLTCTRL_FFVAL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FFVAL field to a new value.
-#define BW_FTM_FLTCTRL_FFVAL(x, v) (HW_FTM_FLTCTRL_WR(x, (HW_FTM_FLTCTRL_RD(x) & ~BM_FTM_FLTCTRL_FFVAL) | BF_FTM_FLTCTRL_FFVAL(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTM_QDCTRL - Quadrature Decoder Control And Status
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTM_QDCTRL - Quadrature Decoder Control And Status (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register has the control and status bits for the Quadrature Decoder mode.
- */
-typedef union _hw_ftm_qdctrl
-{
- uint32_t U;
- struct _hw_ftm_qdctrl_bitfields
- {
- uint32_t QUADEN : 1; //!< [0] Quadrature Decoder Mode Enable
- uint32_t TOFDIR : 1; //!< [1] Timer Overflow Direction In Quadrature
- //! Decoder Mode
- uint32_t QUADIR : 1; //!< [2] FTM Counter Direction In Quadrature
- //! Decoder Mode
- uint32_t QUADMODE : 1; //!< [3] Quadrature Decoder Mode
- uint32_t PHBPOL : 1; //!< [4] Phase B Input Polarity
- uint32_t PHAPOL : 1; //!< [5] Phase A Input Polarity
- uint32_t PHBFLTREN : 1; //!< [6] Phase B Input Filter Enable
- uint32_t PHAFLTREN : 1; //!< [7] Phase A Input Filter Enable
- uint32_t RESERVED0 : 24; //!< [31:8]
- } B;
-} hw_ftm_qdctrl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTM_QDCTRL register
- */
-//@{
-#define HW_FTM_QDCTRL_ADDR(x) (REGS_FTM_BASE(x) + 0x80U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTM_QDCTRL(x) (*(__IO hw_ftm_qdctrl_t *) HW_FTM_QDCTRL_ADDR(x))
-#define HW_FTM_QDCTRL_RD(x) (HW_FTM_QDCTRL(x).U)
-#define HW_FTM_QDCTRL_WR(x, v) (HW_FTM_QDCTRL(x).U = (v))
-#define HW_FTM_QDCTRL_SET(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) | (v)))
-#define HW_FTM_QDCTRL_CLR(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) & ~(v)))
-#define HW_FTM_QDCTRL_TOG(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTM_QDCTRL bitfields
- */
-
-/*!
- * @name Register FTM_QDCTRL, field QUADEN[0] (RW)
- *
- * Enables the Quadrature Decoder mode. In this mode, the phase A and B input
- * signals control the FTM counter direction. The Quadrature Decoder mode has
- * precedence over the other modes. See #ModeSel1Table. This field is write protected.
- * It can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - Quadrature Decoder mode is disabled.
- * - 1 - Quadrature Decoder mode is enabled.
- */
-//@{
-#define BP_FTM_QDCTRL_QUADEN (0U) //!< Bit position for FTM_QDCTRL_QUADEN.
-#define BM_FTM_QDCTRL_QUADEN (0x00000001U) //!< Bit mask for FTM_QDCTRL_QUADEN.
-#define BS_FTM_QDCTRL_QUADEN (1U) //!< Bit field size in bits for FTM_QDCTRL_QUADEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_QDCTRL_QUADEN field.
-#define BR_FTM_QDCTRL_QUADEN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADEN))
-#endif
-
-//! @brief Format value for bitfield FTM_QDCTRL_QUADEN.
-#define BF_FTM_QDCTRL_QUADEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_QUADEN), uint32_t) & BM_FTM_QDCTRL_QUADEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the QUADEN field to a new value.
-#define BW_FTM_QDCTRL_QUADEN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_QDCTRL, field TOFDIR[1] (RO)
- *
- * Indicates if the TOF bit was set on the top or the bottom of counting.
- *
- * Values:
- * - 0 - TOF bit was set on the bottom of counting. There was an FTM counter
- * decrement and FTM counter changes from its minimum value (CNTIN register) to
- * its maximum value (MOD register).
- * - 1 - TOF bit was set on the top of counting. There was an FTM counter
- * increment and FTM counter changes from its maximum value (MOD register) to its
- * minimum value (CNTIN register).
- */
-//@{
-#define BP_FTM_QDCTRL_TOFDIR (1U) //!< Bit position for FTM_QDCTRL_TOFDIR.
-#define BM_FTM_QDCTRL_TOFDIR (0x00000002U) //!< Bit mask for FTM_QDCTRL_TOFDIR.
-#define BS_FTM_QDCTRL_TOFDIR (1U) //!< Bit field size in bits for FTM_QDCTRL_TOFDIR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_QDCTRL_TOFDIR field.
-#define BR_FTM_QDCTRL_TOFDIR(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_TOFDIR))
-#endif
-//@}
-
-/*!
- * @name Register FTM_QDCTRL, field QUADIR[2] (RO)
- *
- * Indicates the counting direction.
- *
- * Values:
- * - 0 - Counting direction is decreasing (FTM counter decrement).
- * - 1 - Counting direction is increasing (FTM counter increment).
- */
-//@{
-#define BP_FTM_QDCTRL_QUADIR (2U) //!< Bit position for FTM_QDCTRL_QUADIR.
-#define BM_FTM_QDCTRL_QUADIR (0x00000004U) //!< Bit mask for FTM_QDCTRL_QUADIR.
-#define BS_FTM_QDCTRL_QUADIR (1U) //!< Bit field size in bits for FTM_QDCTRL_QUADIR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_QDCTRL_QUADIR field.
-#define BR_FTM_QDCTRL_QUADIR(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADIR))
-#endif
-//@}
-
-/*!
- * @name Register FTM_QDCTRL, field QUADMODE[3] (RW)
- *
- * Selects the encoding mode used in the Quadrature Decoder mode.
- *
- * Values:
- * - 0 - Phase A and phase B encoding mode.
- * - 1 - Count and direction encoding mode.
- */
-//@{
-#define BP_FTM_QDCTRL_QUADMODE (3U) //!< Bit position for FTM_QDCTRL_QUADMODE.
-#define BM_FTM_QDCTRL_QUADMODE (0x00000008U) //!< Bit mask for FTM_QDCTRL_QUADMODE.
-#define BS_FTM_QDCTRL_QUADMODE (1U) //!< Bit field size in bits for FTM_QDCTRL_QUADMODE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_QDCTRL_QUADMODE field.
-#define BR_FTM_QDCTRL_QUADMODE(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADMODE))
-#endif
-
-//! @brief Format value for bitfield FTM_QDCTRL_QUADMODE.
-#define BF_FTM_QDCTRL_QUADMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_QUADMODE), uint32_t) & BM_FTM_QDCTRL_QUADMODE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the QUADMODE field to a new value.
-#define BW_FTM_QDCTRL_QUADMODE(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADMODE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_QDCTRL, field PHBPOL[4] (RW)
- *
- * Selects the polarity for the quadrature decoder phase B input.
- *
- * Values:
- * - 0 - Normal polarity. Phase B input signal is not inverted before
- * identifying the rising and falling edges of this signal.
- * - 1 - Inverted polarity. Phase B input signal is inverted before identifying
- * the rising and falling edges of this signal.
- */
-//@{
-#define BP_FTM_QDCTRL_PHBPOL (4U) //!< Bit position for FTM_QDCTRL_PHBPOL.
-#define BM_FTM_QDCTRL_PHBPOL (0x00000010U) //!< Bit mask for FTM_QDCTRL_PHBPOL.
-#define BS_FTM_QDCTRL_PHBPOL (1U) //!< Bit field size in bits for FTM_QDCTRL_PHBPOL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_QDCTRL_PHBPOL field.
-#define BR_FTM_QDCTRL_PHBPOL(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBPOL))
-#endif
-
-//! @brief Format value for bitfield FTM_QDCTRL_PHBPOL.
-#define BF_FTM_QDCTRL_PHBPOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_PHBPOL), uint32_t) & BM_FTM_QDCTRL_PHBPOL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PHBPOL field to a new value.
-#define BW_FTM_QDCTRL_PHBPOL(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBPOL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_QDCTRL, field PHAPOL[5] (RW)
- *
- * Selects the polarity for the quadrature decoder phase A input.
- *
- * Values:
- * - 0 - Normal polarity. Phase A input signal is not inverted before
- * identifying the rising and falling edges of this signal.
- * - 1 - Inverted polarity. Phase A input signal is inverted before identifying
- * the rising and falling edges of this signal.
- */
-//@{
-#define BP_FTM_QDCTRL_PHAPOL (5U) //!< Bit position for FTM_QDCTRL_PHAPOL.
-#define BM_FTM_QDCTRL_PHAPOL (0x00000020U) //!< Bit mask for FTM_QDCTRL_PHAPOL.
-#define BS_FTM_QDCTRL_PHAPOL (1U) //!< Bit field size in bits for FTM_QDCTRL_PHAPOL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_QDCTRL_PHAPOL field.
-#define BR_FTM_QDCTRL_PHAPOL(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAPOL))
-#endif
-
-//! @brief Format value for bitfield FTM_QDCTRL_PHAPOL.
-#define BF_FTM_QDCTRL_PHAPOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_PHAPOL), uint32_t) & BM_FTM_QDCTRL_PHAPOL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PHAPOL field to a new value.
-#define BW_FTM_QDCTRL_PHAPOL(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAPOL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_QDCTRL, field PHBFLTREN[6] (RW)
- *
- * Enables the filter for the quadrature decoder phase B input. The filter value
- * for the phase B input is defined by the CH1FVAL field of FILTER. The phase B
- * filter is also disabled when CH1FVAL is zero.
- *
- * Values:
- * - 0 - Phase B input filter is disabled.
- * - 1 - Phase B input filter is enabled.
- */
-//@{
-#define BP_FTM_QDCTRL_PHBFLTREN (6U) //!< Bit position for FTM_QDCTRL_PHBFLTREN.
-#define BM_FTM_QDCTRL_PHBFLTREN (0x00000040U) //!< Bit mask for FTM_QDCTRL_PHBFLTREN.
-#define BS_FTM_QDCTRL_PHBFLTREN (1U) //!< Bit field size in bits for FTM_QDCTRL_PHBFLTREN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_QDCTRL_PHBFLTREN field.
-#define BR_FTM_QDCTRL_PHBFLTREN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBFLTREN))
-#endif
-
-//! @brief Format value for bitfield FTM_QDCTRL_PHBFLTREN.
-#define BF_FTM_QDCTRL_PHBFLTREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_PHBFLTREN), uint32_t) & BM_FTM_QDCTRL_PHBFLTREN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PHBFLTREN field to a new value.
-#define BW_FTM_QDCTRL_PHBFLTREN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBFLTREN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_QDCTRL, field PHAFLTREN[7] (RW)
- *
- * Enables the filter for the quadrature decoder phase A input. The filter value
- * for the phase A input is defined by the CH0FVAL field of FILTER. The phase A
- * filter is also disabled when CH0FVAL is zero.
- *
- * Values:
- * - 0 - Phase A input filter is disabled.
- * - 1 - Phase A input filter is enabled.
- */
-//@{
-#define BP_FTM_QDCTRL_PHAFLTREN (7U) //!< Bit position for FTM_QDCTRL_PHAFLTREN.
-#define BM_FTM_QDCTRL_PHAFLTREN (0x00000080U) //!< Bit mask for FTM_QDCTRL_PHAFLTREN.
-#define BS_FTM_QDCTRL_PHAFLTREN (1U) //!< Bit field size in bits for FTM_QDCTRL_PHAFLTREN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_QDCTRL_PHAFLTREN field.
-#define BR_FTM_QDCTRL_PHAFLTREN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAFLTREN))
-#endif
-
-//! @brief Format value for bitfield FTM_QDCTRL_PHAFLTREN.
-#define BF_FTM_QDCTRL_PHAFLTREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_PHAFLTREN), uint32_t) & BM_FTM_QDCTRL_PHAFLTREN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PHAFLTREN field to a new value.
-#define BW_FTM_QDCTRL_PHAFLTREN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAFLTREN) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTM_CONF - Configuration
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTM_CONF - Configuration (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register selects the number of times that the FTM counter overflow
- * should occur before the TOF bit to be set, the FTM behavior in BDM modes, the use
- * of an external global time base, and the global time base signal generation.
- */
-typedef union _hw_ftm_conf
-{
- uint32_t U;
- struct _hw_ftm_conf_bitfields
- {
- uint32_t NUMTOF : 5; //!< [4:0] TOF Frequency
- uint32_t RESERVED0 : 1; //!< [5]
- uint32_t BDMMODE : 2; //!< [7:6] BDM Mode
- uint32_t RESERVED1 : 1; //!< [8]
- uint32_t GTBEEN : 1; //!< [9] Global Time Base Enable
- uint32_t GTBEOUT : 1; //!< [10] Global Time Base Output
- uint32_t RESERVED2 : 21; //!< [31:11]
- } B;
-} hw_ftm_conf_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTM_CONF register
- */
-//@{
-#define HW_FTM_CONF_ADDR(x) (REGS_FTM_BASE(x) + 0x84U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTM_CONF(x) (*(__IO hw_ftm_conf_t *) HW_FTM_CONF_ADDR(x))
-#define HW_FTM_CONF_RD(x) (HW_FTM_CONF(x).U)
-#define HW_FTM_CONF_WR(x, v) (HW_FTM_CONF(x).U = (v))
-#define HW_FTM_CONF_SET(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) | (v)))
-#define HW_FTM_CONF_CLR(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) & ~(v)))
-#define HW_FTM_CONF_TOG(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTM_CONF bitfields
- */
-
-/*!
- * @name Register FTM_CONF, field NUMTOF[4:0] (RW)
- *
- * Selects the ratio between the number of counter overflows to the number of
- * times the TOF bit is set. NUMTOF = 0: The TOF bit is set for each counter
- * overflow. NUMTOF = 1: The TOF bit is set for the first counter overflow but not for
- * the next overflow. NUMTOF = 2: The TOF bit is set for the first counter
- * overflow but not for the next 2 overflows. NUMTOF = 3: The TOF bit is set for the
- * first counter overflow but not for the next 3 overflows. This pattern continues
- * up to a maximum of 31.
- */
-//@{
-#define BP_FTM_CONF_NUMTOF (0U) //!< Bit position for FTM_CONF_NUMTOF.
-#define BM_FTM_CONF_NUMTOF (0x0000001FU) //!< Bit mask for FTM_CONF_NUMTOF.
-#define BS_FTM_CONF_NUMTOF (5U) //!< Bit field size in bits for FTM_CONF_NUMTOF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_CONF_NUMTOF field.
-#define BR_FTM_CONF_NUMTOF(x) (HW_FTM_CONF(x).B.NUMTOF)
-#endif
-
-//! @brief Format value for bitfield FTM_CONF_NUMTOF.
-#define BF_FTM_CONF_NUMTOF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CONF_NUMTOF), uint32_t) & BM_FTM_CONF_NUMTOF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the NUMTOF field to a new value.
-#define BW_FTM_CONF_NUMTOF(x, v) (HW_FTM_CONF_WR(x, (HW_FTM_CONF_RD(x) & ~BM_FTM_CONF_NUMTOF) | BF_FTM_CONF_NUMTOF(v)))
-#endif
-//@}
-
-/*!
- * @name Register FTM_CONF, field BDMMODE[7:6] (RW)
- *
- * Selects the FTM behavior in BDM mode. See BDM mode.
- */
-//@{
-#define BP_FTM_CONF_BDMMODE (6U) //!< Bit position for FTM_CONF_BDMMODE.
-#define BM_FTM_CONF_BDMMODE (0x000000C0U) //!< Bit mask for FTM_CONF_BDMMODE.
-#define BS_FTM_CONF_BDMMODE (2U) //!< Bit field size in bits for FTM_CONF_BDMMODE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_CONF_BDMMODE field.
-#define BR_FTM_CONF_BDMMODE(x) (HW_FTM_CONF(x).B.BDMMODE)
-#endif
-
-//! @brief Format value for bitfield FTM_CONF_BDMMODE.
-#define BF_FTM_CONF_BDMMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CONF_BDMMODE), uint32_t) & BM_FTM_CONF_BDMMODE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BDMMODE field to a new value.
-#define BW_FTM_CONF_BDMMODE(x, v) (HW_FTM_CONF_WR(x, (HW_FTM_CONF_RD(x) & ~BM_FTM_CONF_BDMMODE) | BF_FTM_CONF_BDMMODE(v)))
-#endif
-//@}
-
-/*!
- * @name Register FTM_CONF, field GTBEEN[9] (RW)
- *
- * Configures the FTM to use an external global time base signal that is
- * generated by another FTM.
- *
- * Values:
- * - 0 - Use of an external global time base is disabled.
- * - 1 - Use of an external global time base is enabled.
- */
-//@{
-#define BP_FTM_CONF_GTBEEN (9U) //!< Bit position for FTM_CONF_GTBEEN.
-#define BM_FTM_CONF_GTBEEN (0x00000200U) //!< Bit mask for FTM_CONF_GTBEEN.
-#define BS_FTM_CONF_GTBEEN (1U) //!< Bit field size in bits for FTM_CONF_GTBEEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_CONF_GTBEEN field.
-#define BR_FTM_CONF_GTBEEN(x) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEEN))
-#endif
-
-//! @brief Format value for bitfield FTM_CONF_GTBEEN.
-#define BF_FTM_CONF_GTBEEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CONF_GTBEEN), uint32_t) & BM_FTM_CONF_GTBEEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the GTBEEN field to a new value.
-#define BW_FTM_CONF_GTBEEN(x, v) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_CONF, field GTBEOUT[10] (RW)
- *
- * Enables the global time base signal generation to other FTMs.
- *
- * Values:
- * - 0 - A global time base signal generation is disabled.
- * - 1 - A global time base signal generation is enabled.
- */
-//@{
-#define BP_FTM_CONF_GTBEOUT (10U) //!< Bit position for FTM_CONF_GTBEOUT.
-#define BM_FTM_CONF_GTBEOUT (0x00000400U) //!< Bit mask for FTM_CONF_GTBEOUT.
-#define BS_FTM_CONF_GTBEOUT (1U) //!< Bit field size in bits for FTM_CONF_GTBEOUT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_CONF_GTBEOUT field.
-#define BR_FTM_CONF_GTBEOUT(x) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEOUT))
-#endif
-
-//! @brief Format value for bitfield FTM_CONF_GTBEOUT.
-#define BF_FTM_CONF_GTBEOUT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CONF_GTBEOUT), uint32_t) & BM_FTM_CONF_GTBEOUT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the GTBEOUT field to a new value.
-#define BW_FTM_CONF_GTBEOUT(x, v) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEOUT) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTM_FLTPOL - FTM Fault Input Polarity
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTM_FLTPOL - FTM Fault Input Polarity (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register defines the fault inputs polarity.
- */
-typedef union _hw_ftm_fltpol
-{
- uint32_t U;
- struct _hw_ftm_fltpol_bitfields
- {
- uint32_t FLT0POL : 1; //!< [0] Fault Input 0 Polarity
- uint32_t FLT1POL : 1; //!< [1] Fault Input 1 Polarity
- uint32_t FLT2POL : 1; //!< [2] Fault Input 2 Polarity
- uint32_t FLT3POL : 1; //!< [3] Fault Input 3 Polarity
- uint32_t RESERVED0 : 28; //!< [31:4]
- } B;
-} hw_ftm_fltpol_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTM_FLTPOL register
- */
-//@{
-#define HW_FTM_FLTPOL_ADDR(x) (REGS_FTM_BASE(x) + 0x88U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTM_FLTPOL(x) (*(__IO hw_ftm_fltpol_t *) HW_FTM_FLTPOL_ADDR(x))
-#define HW_FTM_FLTPOL_RD(x) (HW_FTM_FLTPOL(x).U)
-#define HW_FTM_FLTPOL_WR(x, v) (HW_FTM_FLTPOL(x).U = (v))
-#define HW_FTM_FLTPOL_SET(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) | (v)))
-#define HW_FTM_FLTPOL_CLR(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) & ~(v)))
-#define HW_FTM_FLTPOL_TOG(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTM_FLTPOL bitfields
- */
-
-/*!
- * @name Register FTM_FLTPOL, field FLT0POL[0] (RW)
- *
- * Defines the polarity of the fault input. This field is write protected. It
- * can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - The fault input polarity is active high. A 1 at the fault input
- * indicates a fault.
- * - 1 - The fault input polarity is active low. A 0 at the fault input
- * indicates a fault.
- */
-//@{
-#define BP_FTM_FLTPOL_FLT0POL (0U) //!< Bit position for FTM_FLTPOL_FLT0POL.
-#define BM_FTM_FLTPOL_FLT0POL (0x00000001U) //!< Bit mask for FTM_FLTPOL_FLT0POL.
-#define BS_FTM_FLTPOL_FLT0POL (1U) //!< Bit field size in bits for FTM_FLTPOL_FLT0POL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_FLTPOL_FLT0POL field.
-#define BR_FTM_FLTPOL_FLT0POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT0POL))
-#endif
-
-//! @brief Format value for bitfield FTM_FLTPOL_FLT0POL.
-#define BF_FTM_FLTPOL_FLT0POL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTPOL_FLT0POL), uint32_t) & BM_FTM_FLTPOL_FLT0POL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FLT0POL field to a new value.
-#define BW_FTM_FLTPOL_FLT0POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT0POL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_FLTPOL, field FLT1POL[1] (RW)
- *
- * Defines the polarity of the fault input. This field is write protected. It
- * can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - The fault input polarity is active high. A 1 at the fault input
- * indicates a fault.
- * - 1 - The fault input polarity is active low. A 0 at the fault input
- * indicates a fault.
- */
-//@{
-#define BP_FTM_FLTPOL_FLT1POL (1U) //!< Bit position for FTM_FLTPOL_FLT1POL.
-#define BM_FTM_FLTPOL_FLT1POL (0x00000002U) //!< Bit mask for FTM_FLTPOL_FLT1POL.
-#define BS_FTM_FLTPOL_FLT1POL (1U) //!< Bit field size in bits for FTM_FLTPOL_FLT1POL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_FLTPOL_FLT1POL field.
-#define BR_FTM_FLTPOL_FLT1POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT1POL))
-#endif
-
-//! @brief Format value for bitfield FTM_FLTPOL_FLT1POL.
-#define BF_FTM_FLTPOL_FLT1POL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTPOL_FLT1POL), uint32_t) & BM_FTM_FLTPOL_FLT1POL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FLT1POL field to a new value.
-#define BW_FTM_FLTPOL_FLT1POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT1POL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_FLTPOL, field FLT2POL[2] (RW)
- *
- * Defines the polarity of the fault input. This field is write protected. It
- * can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - The fault input polarity is active high. A 1 at the fault input
- * indicates a fault.
- * - 1 - The fault input polarity is active low. A 0 at the fault input
- * indicates a fault.
- */
-//@{
-#define BP_FTM_FLTPOL_FLT2POL (2U) //!< Bit position for FTM_FLTPOL_FLT2POL.
-#define BM_FTM_FLTPOL_FLT2POL (0x00000004U) //!< Bit mask for FTM_FLTPOL_FLT2POL.
-#define BS_FTM_FLTPOL_FLT2POL (1U) //!< Bit field size in bits for FTM_FLTPOL_FLT2POL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_FLTPOL_FLT2POL field.
-#define BR_FTM_FLTPOL_FLT2POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT2POL))
-#endif
-
-//! @brief Format value for bitfield FTM_FLTPOL_FLT2POL.
-#define BF_FTM_FLTPOL_FLT2POL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTPOL_FLT2POL), uint32_t) & BM_FTM_FLTPOL_FLT2POL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FLT2POL field to a new value.
-#define BW_FTM_FLTPOL_FLT2POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT2POL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_FLTPOL, field FLT3POL[3] (RW)
- *
- * Defines the polarity of the fault input. This field is write protected. It
- * can be written only when MODE[WPDIS] = 1.
- *
- * Values:
- * - 0 - The fault input polarity is active high. A 1 at the fault input
- * indicates a fault.
- * - 1 - The fault input polarity is active low. A 0 at the fault input
- * indicates a fault.
- */
-//@{
-#define BP_FTM_FLTPOL_FLT3POL (3U) //!< Bit position for FTM_FLTPOL_FLT3POL.
-#define BM_FTM_FLTPOL_FLT3POL (0x00000008U) //!< Bit mask for FTM_FLTPOL_FLT3POL.
-#define BS_FTM_FLTPOL_FLT3POL (1U) //!< Bit field size in bits for FTM_FLTPOL_FLT3POL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_FLTPOL_FLT3POL field.
-#define BR_FTM_FLTPOL_FLT3POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT3POL))
-#endif
-
-//! @brief Format value for bitfield FTM_FLTPOL_FLT3POL.
-#define BF_FTM_FLTPOL_FLT3POL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTPOL_FLT3POL), uint32_t) & BM_FTM_FLTPOL_FLT3POL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FLT3POL field to a new value.
-#define BW_FTM_FLTPOL_FLT3POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT3POL) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTM_SYNCONF - Synchronization Configuration
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTM_SYNCONF - Synchronization Configuration (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register selects the PWM synchronization configuration, SWOCTRL, INVCTRL
- * and CNTIN registers synchronization, if FTM clears the TRIGj bit, where j =
- * 0, 1, 2, when the hardware trigger j is detected.
- */
-typedef union _hw_ftm_synconf
-{
- uint32_t U;
- struct _hw_ftm_synconf_bitfields
- {
- uint32_t HWTRIGMODE : 1; //!< [0] Hardware Trigger Mode
- uint32_t RESERVED0 : 1; //!< [1]
- uint32_t CNTINC : 1; //!< [2] CNTIN Register Synchronization
- uint32_t RESERVED1 : 1; //!< [3]
- uint32_t INVC : 1; //!< [4] INVCTRL Register Synchronization
- uint32_t SWOC : 1; //!< [5] SWOCTRL Register Synchronization
- uint32_t RESERVED2 : 1; //!< [6]
- uint32_t SYNCMODE : 1; //!< [7] Synchronization Mode
- uint32_t SWRSTCNT : 1; //!< [8]
- uint32_t SWWRBUF : 1; //!< [9]
- uint32_t SWOM : 1; //!< [10]
- uint32_t SWINVC : 1; //!< [11]
- uint32_t SWSOC : 1; //!< [12]
- uint32_t RESERVED3 : 3; //!< [15:13]
- uint32_t HWRSTCNT : 1; //!< [16]
- uint32_t HWWRBUF : 1; //!< [17]
- uint32_t HWOM : 1; //!< [18]
- uint32_t HWINVC : 1; //!< [19]
- uint32_t HWSOC : 1; //!< [20]
- uint32_t RESERVED4 : 11; //!< [31:21]
- } B;
-} hw_ftm_synconf_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTM_SYNCONF register
- */
-//@{
-#define HW_FTM_SYNCONF_ADDR(x) (REGS_FTM_BASE(x) + 0x8CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTM_SYNCONF(x) (*(__IO hw_ftm_synconf_t *) HW_FTM_SYNCONF_ADDR(x))
-#define HW_FTM_SYNCONF_RD(x) (HW_FTM_SYNCONF(x).U)
-#define HW_FTM_SYNCONF_WR(x, v) (HW_FTM_SYNCONF(x).U = (v))
-#define HW_FTM_SYNCONF_SET(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) | (v)))
-#define HW_FTM_SYNCONF_CLR(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) & ~(v)))
-#define HW_FTM_SYNCONF_TOG(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTM_SYNCONF bitfields
- */
-
-/*!
- * @name Register FTM_SYNCONF, field HWTRIGMODE[0] (RW)
- *
- * Values:
- * - 0 - FTM clears the TRIGj bit when the hardware trigger j is detected, where
- * j = 0, 1,2.
- * - 1 - FTM does not clear the TRIGj bit when the hardware trigger j is
- * detected, where j = 0, 1,2.
- */
-//@{
-#define BP_FTM_SYNCONF_HWTRIGMODE (0U) //!< Bit position for FTM_SYNCONF_HWTRIGMODE.
-#define BM_FTM_SYNCONF_HWTRIGMODE (0x00000001U) //!< Bit mask for FTM_SYNCONF_HWTRIGMODE.
-#define BS_FTM_SYNCONF_HWTRIGMODE (1U) //!< Bit field size in bits for FTM_SYNCONF_HWTRIGMODE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SYNCONF_HWTRIGMODE field.
-#define BR_FTM_SYNCONF_HWTRIGMODE(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWTRIGMODE))
-#endif
-
-//! @brief Format value for bitfield FTM_SYNCONF_HWTRIGMODE.
-#define BF_FTM_SYNCONF_HWTRIGMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWTRIGMODE), uint32_t) & BM_FTM_SYNCONF_HWTRIGMODE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the HWTRIGMODE field to a new value.
-#define BW_FTM_SYNCONF_HWTRIGMODE(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWTRIGMODE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SYNCONF, field CNTINC[2] (RW)
- *
- * Values:
- * - 0 - CNTIN register is updated with its buffer value at all rising edges of
- * system clock.
- * - 1 - CNTIN register is updated with its buffer value by the PWM
- * synchronization.
- */
-//@{
-#define BP_FTM_SYNCONF_CNTINC (2U) //!< Bit position for FTM_SYNCONF_CNTINC.
-#define BM_FTM_SYNCONF_CNTINC (0x00000004U) //!< Bit mask for FTM_SYNCONF_CNTINC.
-#define BS_FTM_SYNCONF_CNTINC (1U) //!< Bit field size in bits for FTM_SYNCONF_CNTINC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SYNCONF_CNTINC field.
-#define BR_FTM_SYNCONF_CNTINC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_CNTINC))
-#endif
-
-//! @brief Format value for bitfield FTM_SYNCONF_CNTINC.
-#define BF_FTM_SYNCONF_CNTINC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_CNTINC), uint32_t) & BM_FTM_SYNCONF_CNTINC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CNTINC field to a new value.
-#define BW_FTM_SYNCONF_CNTINC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_CNTINC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SYNCONF, field INVC[4] (RW)
- *
- * Values:
- * - 0 - INVCTRL register is updated with its buffer value at all rising edges
- * of system clock.
- * - 1 - INVCTRL register is updated with its buffer value by the PWM
- * synchronization.
- */
-//@{
-#define BP_FTM_SYNCONF_INVC (4U) //!< Bit position for FTM_SYNCONF_INVC.
-#define BM_FTM_SYNCONF_INVC (0x00000010U) //!< Bit mask for FTM_SYNCONF_INVC.
-#define BS_FTM_SYNCONF_INVC (1U) //!< Bit field size in bits for FTM_SYNCONF_INVC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SYNCONF_INVC field.
-#define BR_FTM_SYNCONF_INVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_INVC))
-#endif
-
-//! @brief Format value for bitfield FTM_SYNCONF_INVC.
-#define BF_FTM_SYNCONF_INVC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_INVC), uint32_t) & BM_FTM_SYNCONF_INVC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INVC field to a new value.
-#define BW_FTM_SYNCONF_INVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_INVC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SYNCONF, field SWOC[5] (RW)
- *
- * Values:
- * - 0 - SWOCTRL register is updated with its buffer value at all rising edges
- * of system clock.
- * - 1 - SWOCTRL register is updated with its buffer value by the PWM
- * synchronization.
- */
-//@{
-#define BP_FTM_SYNCONF_SWOC (5U) //!< Bit position for FTM_SYNCONF_SWOC.
-#define BM_FTM_SYNCONF_SWOC (0x00000020U) //!< Bit mask for FTM_SYNCONF_SWOC.
-#define BS_FTM_SYNCONF_SWOC (1U) //!< Bit field size in bits for FTM_SYNCONF_SWOC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SYNCONF_SWOC field.
-#define BR_FTM_SYNCONF_SWOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOC))
-#endif
-
-//! @brief Format value for bitfield FTM_SYNCONF_SWOC.
-#define BF_FTM_SYNCONF_SWOC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWOC), uint32_t) & BM_FTM_SYNCONF_SWOC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SWOC field to a new value.
-#define BW_FTM_SYNCONF_SWOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SYNCONF, field SYNCMODE[7] (RW)
- *
- * Selects the PWM Synchronization mode.
- *
- * Values:
- * - 0 - Legacy PWM synchronization is selected.
- * - 1 - Enhanced PWM synchronization is selected.
- */
-//@{
-#define BP_FTM_SYNCONF_SYNCMODE (7U) //!< Bit position for FTM_SYNCONF_SYNCMODE.
-#define BM_FTM_SYNCONF_SYNCMODE (0x00000080U) //!< Bit mask for FTM_SYNCONF_SYNCMODE.
-#define BS_FTM_SYNCONF_SYNCMODE (1U) //!< Bit field size in bits for FTM_SYNCONF_SYNCMODE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SYNCONF_SYNCMODE field.
-#define BR_FTM_SYNCONF_SYNCMODE(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SYNCMODE))
-#endif
-
-//! @brief Format value for bitfield FTM_SYNCONF_SYNCMODE.
-#define BF_FTM_SYNCONF_SYNCMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SYNCMODE), uint32_t) & BM_FTM_SYNCONF_SYNCMODE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SYNCMODE field to a new value.
-#define BW_FTM_SYNCONF_SYNCMODE(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SYNCMODE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SYNCONF, field SWRSTCNT[8] (RW)
- *
- * FTM counter synchronization is activated by the software trigger.
- *
- * Values:
- * - 0 - The software trigger does not activate the FTM counter synchronization.
- * - 1 - The software trigger activates the FTM counter synchronization.
- */
-//@{
-#define BP_FTM_SYNCONF_SWRSTCNT (8U) //!< Bit position for FTM_SYNCONF_SWRSTCNT.
-#define BM_FTM_SYNCONF_SWRSTCNT (0x00000100U) //!< Bit mask for FTM_SYNCONF_SWRSTCNT.
-#define BS_FTM_SYNCONF_SWRSTCNT (1U) //!< Bit field size in bits for FTM_SYNCONF_SWRSTCNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SYNCONF_SWRSTCNT field.
-#define BR_FTM_SYNCONF_SWRSTCNT(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWRSTCNT))
-#endif
-
-//! @brief Format value for bitfield FTM_SYNCONF_SWRSTCNT.
-#define BF_FTM_SYNCONF_SWRSTCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWRSTCNT), uint32_t) & BM_FTM_SYNCONF_SWRSTCNT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SWRSTCNT field to a new value.
-#define BW_FTM_SYNCONF_SWRSTCNT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWRSTCNT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SYNCONF, field SWWRBUF[9] (RW)
- *
- * MOD, CNTIN, and CV registers synchronization is activated by the software
- * trigger.
- *
- * Values:
- * - 0 - The software trigger does not activate MOD, CNTIN, and CV registers
- * synchronization.
- * - 1 - The software trigger activates MOD, CNTIN, and CV registers
- * synchronization.
- */
-//@{
-#define BP_FTM_SYNCONF_SWWRBUF (9U) //!< Bit position for FTM_SYNCONF_SWWRBUF.
-#define BM_FTM_SYNCONF_SWWRBUF (0x00000200U) //!< Bit mask for FTM_SYNCONF_SWWRBUF.
-#define BS_FTM_SYNCONF_SWWRBUF (1U) //!< Bit field size in bits for FTM_SYNCONF_SWWRBUF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SYNCONF_SWWRBUF field.
-#define BR_FTM_SYNCONF_SWWRBUF(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWWRBUF))
-#endif
-
-//! @brief Format value for bitfield FTM_SYNCONF_SWWRBUF.
-#define BF_FTM_SYNCONF_SWWRBUF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWWRBUF), uint32_t) & BM_FTM_SYNCONF_SWWRBUF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SWWRBUF field to a new value.
-#define BW_FTM_SYNCONF_SWWRBUF(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWWRBUF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SYNCONF, field SWOM[10] (RW)
- *
- * Output mask synchronization is activated by the software trigger.
- *
- * Values:
- * - 0 - The software trigger does not activate the OUTMASK register
- * synchronization.
- * - 1 - The software trigger activates the OUTMASK register synchronization.
- */
-//@{
-#define BP_FTM_SYNCONF_SWOM (10U) //!< Bit position for FTM_SYNCONF_SWOM.
-#define BM_FTM_SYNCONF_SWOM (0x00000400U) //!< Bit mask for FTM_SYNCONF_SWOM.
-#define BS_FTM_SYNCONF_SWOM (1U) //!< Bit field size in bits for FTM_SYNCONF_SWOM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SYNCONF_SWOM field.
-#define BR_FTM_SYNCONF_SWOM(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOM))
-#endif
-
-//! @brief Format value for bitfield FTM_SYNCONF_SWOM.
-#define BF_FTM_SYNCONF_SWOM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWOM), uint32_t) & BM_FTM_SYNCONF_SWOM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SWOM field to a new value.
-#define BW_FTM_SYNCONF_SWOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOM) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SYNCONF, field SWINVC[11] (RW)
- *
- * Inverting control synchronization is activated by the software trigger.
- *
- * Values:
- * - 0 - The software trigger does not activate the INVCTRL register
- * synchronization.
- * - 1 - The software trigger activates the INVCTRL register synchronization.
- */
-//@{
-#define BP_FTM_SYNCONF_SWINVC (11U) //!< Bit position for FTM_SYNCONF_SWINVC.
-#define BM_FTM_SYNCONF_SWINVC (0x00000800U) //!< Bit mask for FTM_SYNCONF_SWINVC.
-#define BS_FTM_SYNCONF_SWINVC (1U) //!< Bit field size in bits for FTM_SYNCONF_SWINVC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SYNCONF_SWINVC field.
-#define BR_FTM_SYNCONF_SWINVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWINVC))
-#endif
-
-//! @brief Format value for bitfield FTM_SYNCONF_SWINVC.
-#define BF_FTM_SYNCONF_SWINVC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWINVC), uint32_t) & BM_FTM_SYNCONF_SWINVC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SWINVC field to a new value.
-#define BW_FTM_SYNCONF_SWINVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWINVC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SYNCONF, field SWSOC[12] (RW)
- *
- * Software output control synchronization is activated by the software trigger.
- *
- * Values:
- * - 0 - The software trigger does not activate the SWOCTRL register
- * synchronization.
- * - 1 - The software trigger activates the SWOCTRL register synchronization.
- */
-//@{
-#define BP_FTM_SYNCONF_SWSOC (12U) //!< Bit position for FTM_SYNCONF_SWSOC.
-#define BM_FTM_SYNCONF_SWSOC (0x00001000U) //!< Bit mask for FTM_SYNCONF_SWSOC.
-#define BS_FTM_SYNCONF_SWSOC (1U) //!< Bit field size in bits for FTM_SYNCONF_SWSOC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SYNCONF_SWSOC field.
-#define BR_FTM_SYNCONF_SWSOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWSOC))
-#endif
-
-//! @brief Format value for bitfield FTM_SYNCONF_SWSOC.
-#define BF_FTM_SYNCONF_SWSOC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWSOC), uint32_t) & BM_FTM_SYNCONF_SWSOC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SWSOC field to a new value.
-#define BW_FTM_SYNCONF_SWSOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWSOC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SYNCONF, field HWRSTCNT[16] (RW)
- *
- * FTM counter synchronization is activated by a hardware trigger.
- *
- * Values:
- * - 0 - A hardware trigger does not activate the FTM counter synchronization.
- * - 1 - A hardware trigger activates the FTM counter synchronization.
- */
-//@{
-#define BP_FTM_SYNCONF_HWRSTCNT (16U) //!< Bit position for FTM_SYNCONF_HWRSTCNT.
-#define BM_FTM_SYNCONF_HWRSTCNT (0x00010000U) //!< Bit mask for FTM_SYNCONF_HWRSTCNT.
-#define BS_FTM_SYNCONF_HWRSTCNT (1U) //!< Bit field size in bits for FTM_SYNCONF_HWRSTCNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SYNCONF_HWRSTCNT field.
-#define BR_FTM_SYNCONF_HWRSTCNT(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWRSTCNT))
-#endif
-
-//! @brief Format value for bitfield FTM_SYNCONF_HWRSTCNT.
-#define BF_FTM_SYNCONF_HWRSTCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWRSTCNT), uint32_t) & BM_FTM_SYNCONF_HWRSTCNT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the HWRSTCNT field to a new value.
-#define BW_FTM_SYNCONF_HWRSTCNT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWRSTCNT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SYNCONF, field HWWRBUF[17] (RW)
- *
- * MOD, CNTIN, and CV registers synchronization is activated by a hardware
- * trigger.
- *
- * Values:
- * - 0 - A hardware trigger does not activate MOD, CNTIN, and CV registers
- * synchronization.
- * - 1 - A hardware trigger activates MOD, CNTIN, and CV registers
- * synchronization.
- */
-//@{
-#define BP_FTM_SYNCONF_HWWRBUF (17U) //!< Bit position for FTM_SYNCONF_HWWRBUF.
-#define BM_FTM_SYNCONF_HWWRBUF (0x00020000U) //!< Bit mask for FTM_SYNCONF_HWWRBUF.
-#define BS_FTM_SYNCONF_HWWRBUF (1U) //!< Bit field size in bits for FTM_SYNCONF_HWWRBUF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SYNCONF_HWWRBUF field.
-#define BR_FTM_SYNCONF_HWWRBUF(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWWRBUF))
-#endif
-
-//! @brief Format value for bitfield FTM_SYNCONF_HWWRBUF.
-#define BF_FTM_SYNCONF_HWWRBUF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWWRBUF), uint32_t) & BM_FTM_SYNCONF_HWWRBUF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the HWWRBUF field to a new value.
-#define BW_FTM_SYNCONF_HWWRBUF(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWWRBUF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SYNCONF, field HWOM[18] (RW)
- *
- * Output mask synchronization is activated by a hardware trigger.
- *
- * Values:
- * - 0 - A hardware trigger does not activate the OUTMASK register
- * synchronization.
- * - 1 - A hardware trigger activates the OUTMASK register synchronization.
- */
-//@{
-#define BP_FTM_SYNCONF_HWOM (18U) //!< Bit position for FTM_SYNCONF_HWOM.
-#define BM_FTM_SYNCONF_HWOM (0x00040000U) //!< Bit mask for FTM_SYNCONF_HWOM.
-#define BS_FTM_SYNCONF_HWOM (1U) //!< Bit field size in bits for FTM_SYNCONF_HWOM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SYNCONF_HWOM field.
-#define BR_FTM_SYNCONF_HWOM(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWOM))
-#endif
-
-//! @brief Format value for bitfield FTM_SYNCONF_HWOM.
-#define BF_FTM_SYNCONF_HWOM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWOM), uint32_t) & BM_FTM_SYNCONF_HWOM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the HWOM field to a new value.
-#define BW_FTM_SYNCONF_HWOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWOM) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SYNCONF, field HWINVC[19] (RW)
- *
- * Inverting control synchronization is activated by a hardware trigger.
- *
- * Values:
- * - 0 - A hardware trigger does not activate the INVCTRL register
- * synchronization.
- * - 1 - A hardware trigger activates the INVCTRL register synchronization.
- */
-//@{
-#define BP_FTM_SYNCONF_HWINVC (19U) //!< Bit position for FTM_SYNCONF_HWINVC.
-#define BM_FTM_SYNCONF_HWINVC (0x00080000U) //!< Bit mask for FTM_SYNCONF_HWINVC.
-#define BS_FTM_SYNCONF_HWINVC (1U) //!< Bit field size in bits for FTM_SYNCONF_HWINVC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SYNCONF_HWINVC field.
-#define BR_FTM_SYNCONF_HWINVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWINVC))
-#endif
-
-//! @brief Format value for bitfield FTM_SYNCONF_HWINVC.
-#define BF_FTM_SYNCONF_HWINVC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWINVC), uint32_t) & BM_FTM_SYNCONF_HWINVC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the HWINVC field to a new value.
-#define BW_FTM_SYNCONF_HWINVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWINVC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SYNCONF, field HWSOC[20] (RW)
- *
- * Software output control synchronization is activated by a hardware trigger.
- *
- * Values:
- * - 0 - A hardware trigger does not activate the SWOCTRL register
- * synchronization.
- * - 1 - A hardware trigger activates the SWOCTRL register synchronization.
- */
-//@{
-#define BP_FTM_SYNCONF_HWSOC (20U) //!< Bit position for FTM_SYNCONF_HWSOC.
-#define BM_FTM_SYNCONF_HWSOC (0x00100000U) //!< Bit mask for FTM_SYNCONF_HWSOC.
-#define BS_FTM_SYNCONF_HWSOC (1U) //!< Bit field size in bits for FTM_SYNCONF_HWSOC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SYNCONF_HWSOC field.
-#define BR_FTM_SYNCONF_HWSOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWSOC))
-#endif
-
-//! @brief Format value for bitfield FTM_SYNCONF_HWSOC.
-#define BF_FTM_SYNCONF_HWSOC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWSOC), uint32_t) & BM_FTM_SYNCONF_HWSOC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the HWSOC field to a new value.
-#define BW_FTM_SYNCONF_HWSOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWSOC) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTM_INVCTRL - FTM Inverting Control
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTM_INVCTRL - FTM Inverting Control (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register controls when the channel (n) output becomes the channel (n+1)
- * output, and channel (n+1) output becomes the channel (n) output. Each INVmEN
- * bit enables the inverting operation for the corresponding pair channels m. This
- * register has a write buffer. The INVmEN bit is updated by the INVCTRL
- * register synchronization.
- */
-typedef union _hw_ftm_invctrl
-{
- uint32_t U;
- struct _hw_ftm_invctrl_bitfields
- {
- uint32_t INV0EN : 1; //!< [0] Pair Channels 0 Inverting Enable
- uint32_t INV1EN : 1; //!< [1] Pair Channels 1 Inverting Enable
- uint32_t INV2EN : 1; //!< [2] Pair Channels 2 Inverting Enable
- uint32_t INV3EN : 1; //!< [3] Pair Channels 3 Inverting Enable
- uint32_t RESERVED0 : 28; //!< [31:4]
- } B;
-} hw_ftm_invctrl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTM_INVCTRL register
- */
-//@{
-#define HW_FTM_INVCTRL_ADDR(x) (REGS_FTM_BASE(x) + 0x90U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTM_INVCTRL(x) (*(__IO hw_ftm_invctrl_t *) HW_FTM_INVCTRL_ADDR(x))
-#define HW_FTM_INVCTRL_RD(x) (HW_FTM_INVCTRL(x).U)
-#define HW_FTM_INVCTRL_WR(x, v) (HW_FTM_INVCTRL(x).U = (v))
-#define HW_FTM_INVCTRL_SET(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) | (v)))
-#define HW_FTM_INVCTRL_CLR(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) & ~(v)))
-#define HW_FTM_INVCTRL_TOG(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTM_INVCTRL bitfields
- */
-
-/*!
- * @name Register FTM_INVCTRL, field INV0EN[0] (RW)
- *
- * Values:
- * - 0 - Inverting is disabled.
- * - 1 - Inverting is enabled.
- */
-//@{
-#define BP_FTM_INVCTRL_INV0EN (0U) //!< Bit position for FTM_INVCTRL_INV0EN.
-#define BM_FTM_INVCTRL_INV0EN (0x00000001U) //!< Bit mask for FTM_INVCTRL_INV0EN.
-#define BS_FTM_INVCTRL_INV0EN (1U) //!< Bit field size in bits for FTM_INVCTRL_INV0EN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_INVCTRL_INV0EN field.
-#define BR_FTM_INVCTRL_INV0EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV0EN))
-#endif
-
-//! @brief Format value for bitfield FTM_INVCTRL_INV0EN.
-#define BF_FTM_INVCTRL_INV0EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_INVCTRL_INV0EN), uint32_t) & BM_FTM_INVCTRL_INV0EN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INV0EN field to a new value.
-#define BW_FTM_INVCTRL_INV0EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV0EN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_INVCTRL, field INV1EN[1] (RW)
- *
- * Values:
- * - 0 - Inverting is disabled.
- * - 1 - Inverting is enabled.
- */
-//@{
-#define BP_FTM_INVCTRL_INV1EN (1U) //!< Bit position for FTM_INVCTRL_INV1EN.
-#define BM_FTM_INVCTRL_INV1EN (0x00000002U) //!< Bit mask for FTM_INVCTRL_INV1EN.
-#define BS_FTM_INVCTRL_INV1EN (1U) //!< Bit field size in bits for FTM_INVCTRL_INV1EN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_INVCTRL_INV1EN field.
-#define BR_FTM_INVCTRL_INV1EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV1EN))
-#endif
-
-//! @brief Format value for bitfield FTM_INVCTRL_INV1EN.
-#define BF_FTM_INVCTRL_INV1EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_INVCTRL_INV1EN), uint32_t) & BM_FTM_INVCTRL_INV1EN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INV1EN field to a new value.
-#define BW_FTM_INVCTRL_INV1EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV1EN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_INVCTRL, field INV2EN[2] (RW)
- *
- * Values:
- * - 0 - Inverting is disabled.
- * - 1 - Inverting is enabled.
- */
-//@{
-#define BP_FTM_INVCTRL_INV2EN (2U) //!< Bit position for FTM_INVCTRL_INV2EN.
-#define BM_FTM_INVCTRL_INV2EN (0x00000004U) //!< Bit mask for FTM_INVCTRL_INV2EN.
-#define BS_FTM_INVCTRL_INV2EN (1U) //!< Bit field size in bits for FTM_INVCTRL_INV2EN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_INVCTRL_INV2EN field.
-#define BR_FTM_INVCTRL_INV2EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV2EN))
-#endif
-
-//! @brief Format value for bitfield FTM_INVCTRL_INV2EN.
-#define BF_FTM_INVCTRL_INV2EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_INVCTRL_INV2EN), uint32_t) & BM_FTM_INVCTRL_INV2EN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INV2EN field to a new value.
-#define BW_FTM_INVCTRL_INV2EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV2EN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_INVCTRL, field INV3EN[3] (RW)
- *
- * Values:
- * - 0 - Inverting is disabled.
- * - 1 - Inverting is enabled.
- */
-//@{
-#define BP_FTM_INVCTRL_INV3EN (3U) //!< Bit position for FTM_INVCTRL_INV3EN.
-#define BM_FTM_INVCTRL_INV3EN (0x00000008U) //!< Bit mask for FTM_INVCTRL_INV3EN.
-#define BS_FTM_INVCTRL_INV3EN (1U) //!< Bit field size in bits for FTM_INVCTRL_INV3EN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_INVCTRL_INV3EN field.
-#define BR_FTM_INVCTRL_INV3EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV3EN))
-#endif
-
-//! @brief Format value for bitfield FTM_INVCTRL_INV3EN.
-#define BF_FTM_INVCTRL_INV3EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_INVCTRL_INV3EN), uint32_t) & BM_FTM_INVCTRL_INV3EN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INV3EN field to a new value.
-#define BW_FTM_INVCTRL_INV3EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV3EN) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTM_SWOCTRL - FTM Software Output Control
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTM_SWOCTRL - FTM Software Output Control (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register enables software control of channel (n) output and defines the
- * value forced to the channel (n) output: The CHnOC bits enable the control of
- * the corresponding channel (n) output by software. The CHnOCV bits select the
- * value that is forced at the corresponding channel (n) output. This register has
- * a write buffer. The fields are updated by the SWOCTRL register synchronization.
- */
-typedef union _hw_ftm_swoctrl
-{
- uint32_t U;
- struct _hw_ftm_swoctrl_bitfields
- {
- uint32_t CH0OC : 1; //!< [0] Channel 0 Software Output Control Enable
- uint32_t CH1OC : 1; //!< [1] Channel 1 Software Output Control Enable
- uint32_t CH2OC : 1; //!< [2] Channel 2 Software Output Control Enable
- uint32_t CH3OC : 1; //!< [3] Channel 3 Software Output Control Enable
- uint32_t CH4OC : 1; //!< [4] Channel 4 Software Output Control Enable
- uint32_t CH5OC : 1; //!< [5] Channel 5 Software Output Control Enable
- uint32_t CH6OC : 1; //!< [6] Channel 6 Software Output Control Enable
- uint32_t CH7OC : 1; //!< [7] Channel 7 Software Output Control Enable
- uint32_t CH0OCV : 1; //!< [8] Channel 0 Software Output Control Value
- uint32_t CH1OCV : 1; //!< [9] Channel 1 Software Output Control Value
- uint32_t CH2OCV : 1; //!< [10] Channel 2 Software Output Control Value
- uint32_t CH3OCV : 1; //!< [11] Channel 3 Software Output Control Value
- uint32_t CH4OCV : 1; //!< [12] Channel 4 Software Output Control Value
- uint32_t CH5OCV : 1; //!< [13] Channel 5 Software Output Control Value
- uint32_t CH6OCV : 1; //!< [14] Channel 6 Software Output Control Value
- uint32_t CH7OCV : 1; //!< [15] Channel 7 Software Output Control Value
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_ftm_swoctrl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTM_SWOCTRL register
- */
-//@{
-#define HW_FTM_SWOCTRL_ADDR(x) (REGS_FTM_BASE(x) + 0x94U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTM_SWOCTRL(x) (*(__IO hw_ftm_swoctrl_t *) HW_FTM_SWOCTRL_ADDR(x))
-#define HW_FTM_SWOCTRL_RD(x) (HW_FTM_SWOCTRL(x).U)
-#define HW_FTM_SWOCTRL_WR(x, v) (HW_FTM_SWOCTRL(x).U = (v))
-#define HW_FTM_SWOCTRL_SET(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) | (v)))
-#define HW_FTM_SWOCTRL_CLR(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) & ~(v)))
-#define HW_FTM_SWOCTRL_TOG(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTM_SWOCTRL bitfields
- */
-
-/*!
- * @name Register FTM_SWOCTRL, field CH0OC[0] (RW)
- *
- * Values:
- * - 0 - The channel output is not affected by software output control.
- * - 1 - The channel output is affected by software output control.
- */
-//@{
-#define BP_FTM_SWOCTRL_CH0OC (0U) //!< Bit position for FTM_SWOCTRL_CH0OC.
-#define BM_FTM_SWOCTRL_CH0OC (0x00000001U) //!< Bit mask for FTM_SWOCTRL_CH0OC.
-#define BS_FTM_SWOCTRL_CH0OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH0OC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SWOCTRL_CH0OC field.
-#define BR_FTM_SWOCTRL_CH0OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OC))
-#endif
-
-//! @brief Format value for bitfield FTM_SWOCTRL_CH0OC.
-#define BF_FTM_SWOCTRL_CH0OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH0OC), uint32_t) & BM_FTM_SWOCTRL_CH0OC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH0OC field to a new value.
-#define BW_FTM_SWOCTRL_CH0OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SWOCTRL, field CH1OC[1] (RW)
- *
- * Values:
- * - 0 - The channel output is not affected by software output control.
- * - 1 - The channel output is affected by software output control.
- */
-//@{
-#define BP_FTM_SWOCTRL_CH1OC (1U) //!< Bit position for FTM_SWOCTRL_CH1OC.
-#define BM_FTM_SWOCTRL_CH1OC (0x00000002U) //!< Bit mask for FTM_SWOCTRL_CH1OC.
-#define BS_FTM_SWOCTRL_CH1OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH1OC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SWOCTRL_CH1OC field.
-#define BR_FTM_SWOCTRL_CH1OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OC))
-#endif
-
-//! @brief Format value for bitfield FTM_SWOCTRL_CH1OC.
-#define BF_FTM_SWOCTRL_CH1OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH1OC), uint32_t) & BM_FTM_SWOCTRL_CH1OC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH1OC field to a new value.
-#define BW_FTM_SWOCTRL_CH1OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SWOCTRL, field CH2OC[2] (RW)
- *
- * Values:
- * - 0 - The channel output is not affected by software output control.
- * - 1 - The channel output is affected by software output control.
- */
-//@{
-#define BP_FTM_SWOCTRL_CH2OC (2U) //!< Bit position for FTM_SWOCTRL_CH2OC.
-#define BM_FTM_SWOCTRL_CH2OC (0x00000004U) //!< Bit mask for FTM_SWOCTRL_CH2OC.
-#define BS_FTM_SWOCTRL_CH2OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH2OC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SWOCTRL_CH2OC field.
-#define BR_FTM_SWOCTRL_CH2OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OC))
-#endif
-
-//! @brief Format value for bitfield FTM_SWOCTRL_CH2OC.
-#define BF_FTM_SWOCTRL_CH2OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH2OC), uint32_t) & BM_FTM_SWOCTRL_CH2OC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH2OC field to a new value.
-#define BW_FTM_SWOCTRL_CH2OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SWOCTRL, field CH3OC[3] (RW)
- *
- * Values:
- * - 0 - The channel output is not affected by software output control.
- * - 1 - The channel output is affected by software output control.
- */
-//@{
-#define BP_FTM_SWOCTRL_CH3OC (3U) //!< Bit position for FTM_SWOCTRL_CH3OC.
-#define BM_FTM_SWOCTRL_CH3OC (0x00000008U) //!< Bit mask for FTM_SWOCTRL_CH3OC.
-#define BS_FTM_SWOCTRL_CH3OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH3OC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SWOCTRL_CH3OC field.
-#define BR_FTM_SWOCTRL_CH3OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OC))
-#endif
-
-//! @brief Format value for bitfield FTM_SWOCTRL_CH3OC.
-#define BF_FTM_SWOCTRL_CH3OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH3OC), uint32_t) & BM_FTM_SWOCTRL_CH3OC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH3OC field to a new value.
-#define BW_FTM_SWOCTRL_CH3OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SWOCTRL, field CH4OC[4] (RW)
- *
- * Values:
- * - 0 - The channel output is not affected by software output control.
- * - 1 - The channel output is affected by software output control.
- */
-//@{
-#define BP_FTM_SWOCTRL_CH4OC (4U) //!< Bit position for FTM_SWOCTRL_CH4OC.
-#define BM_FTM_SWOCTRL_CH4OC (0x00000010U) //!< Bit mask for FTM_SWOCTRL_CH4OC.
-#define BS_FTM_SWOCTRL_CH4OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH4OC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SWOCTRL_CH4OC field.
-#define BR_FTM_SWOCTRL_CH4OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OC))
-#endif
-
-//! @brief Format value for bitfield FTM_SWOCTRL_CH4OC.
-#define BF_FTM_SWOCTRL_CH4OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH4OC), uint32_t) & BM_FTM_SWOCTRL_CH4OC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH4OC field to a new value.
-#define BW_FTM_SWOCTRL_CH4OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SWOCTRL, field CH5OC[5] (RW)
- *
- * Values:
- * - 0 - The channel output is not affected by software output control.
- * - 1 - The channel output is affected by software output control.
- */
-//@{
-#define BP_FTM_SWOCTRL_CH5OC (5U) //!< Bit position for FTM_SWOCTRL_CH5OC.
-#define BM_FTM_SWOCTRL_CH5OC (0x00000020U) //!< Bit mask for FTM_SWOCTRL_CH5OC.
-#define BS_FTM_SWOCTRL_CH5OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH5OC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SWOCTRL_CH5OC field.
-#define BR_FTM_SWOCTRL_CH5OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OC))
-#endif
-
-//! @brief Format value for bitfield FTM_SWOCTRL_CH5OC.
-#define BF_FTM_SWOCTRL_CH5OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH5OC), uint32_t) & BM_FTM_SWOCTRL_CH5OC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH5OC field to a new value.
-#define BW_FTM_SWOCTRL_CH5OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SWOCTRL, field CH6OC[6] (RW)
- *
- * Values:
- * - 0 - The channel output is not affected by software output control.
- * - 1 - The channel output is affected by software output control.
- */
-//@{
-#define BP_FTM_SWOCTRL_CH6OC (6U) //!< Bit position for FTM_SWOCTRL_CH6OC.
-#define BM_FTM_SWOCTRL_CH6OC (0x00000040U) //!< Bit mask for FTM_SWOCTRL_CH6OC.
-#define BS_FTM_SWOCTRL_CH6OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH6OC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SWOCTRL_CH6OC field.
-#define BR_FTM_SWOCTRL_CH6OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OC))
-#endif
-
-//! @brief Format value for bitfield FTM_SWOCTRL_CH6OC.
-#define BF_FTM_SWOCTRL_CH6OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH6OC), uint32_t) & BM_FTM_SWOCTRL_CH6OC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH6OC field to a new value.
-#define BW_FTM_SWOCTRL_CH6OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SWOCTRL, field CH7OC[7] (RW)
- *
- * Values:
- * - 0 - The channel output is not affected by software output control.
- * - 1 - The channel output is affected by software output control.
- */
-//@{
-#define BP_FTM_SWOCTRL_CH7OC (7U) //!< Bit position for FTM_SWOCTRL_CH7OC.
-#define BM_FTM_SWOCTRL_CH7OC (0x00000080U) //!< Bit mask for FTM_SWOCTRL_CH7OC.
-#define BS_FTM_SWOCTRL_CH7OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH7OC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SWOCTRL_CH7OC field.
-#define BR_FTM_SWOCTRL_CH7OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OC))
-#endif
-
-//! @brief Format value for bitfield FTM_SWOCTRL_CH7OC.
-#define BF_FTM_SWOCTRL_CH7OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH7OC), uint32_t) & BM_FTM_SWOCTRL_CH7OC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH7OC field to a new value.
-#define BW_FTM_SWOCTRL_CH7OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SWOCTRL, field CH0OCV[8] (RW)
- *
- * Values:
- * - 0 - The software output control forces 0 to the channel output.
- * - 1 - The software output control forces 1 to the channel output.
- */
-//@{
-#define BP_FTM_SWOCTRL_CH0OCV (8U) //!< Bit position for FTM_SWOCTRL_CH0OCV.
-#define BM_FTM_SWOCTRL_CH0OCV (0x00000100U) //!< Bit mask for FTM_SWOCTRL_CH0OCV.
-#define BS_FTM_SWOCTRL_CH0OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH0OCV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SWOCTRL_CH0OCV field.
-#define BR_FTM_SWOCTRL_CH0OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OCV))
-#endif
-
-//! @brief Format value for bitfield FTM_SWOCTRL_CH0OCV.
-#define BF_FTM_SWOCTRL_CH0OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH0OCV), uint32_t) & BM_FTM_SWOCTRL_CH0OCV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH0OCV field to a new value.
-#define BW_FTM_SWOCTRL_CH0OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OCV) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SWOCTRL, field CH1OCV[9] (RW)
- *
- * Values:
- * - 0 - The software output control forces 0 to the channel output.
- * - 1 - The software output control forces 1 to the channel output.
- */
-//@{
-#define BP_FTM_SWOCTRL_CH1OCV (9U) //!< Bit position for FTM_SWOCTRL_CH1OCV.
-#define BM_FTM_SWOCTRL_CH1OCV (0x00000200U) //!< Bit mask for FTM_SWOCTRL_CH1OCV.
-#define BS_FTM_SWOCTRL_CH1OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH1OCV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SWOCTRL_CH1OCV field.
-#define BR_FTM_SWOCTRL_CH1OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OCV))
-#endif
-
-//! @brief Format value for bitfield FTM_SWOCTRL_CH1OCV.
-#define BF_FTM_SWOCTRL_CH1OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH1OCV), uint32_t) & BM_FTM_SWOCTRL_CH1OCV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH1OCV field to a new value.
-#define BW_FTM_SWOCTRL_CH1OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OCV) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SWOCTRL, field CH2OCV[10] (RW)
- *
- * Values:
- * - 0 - The software output control forces 0 to the channel output.
- * - 1 - The software output control forces 1 to the channel output.
- */
-//@{
-#define BP_FTM_SWOCTRL_CH2OCV (10U) //!< Bit position for FTM_SWOCTRL_CH2OCV.
-#define BM_FTM_SWOCTRL_CH2OCV (0x00000400U) //!< Bit mask for FTM_SWOCTRL_CH2OCV.
-#define BS_FTM_SWOCTRL_CH2OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH2OCV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SWOCTRL_CH2OCV field.
-#define BR_FTM_SWOCTRL_CH2OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OCV))
-#endif
-
-//! @brief Format value for bitfield FTM_SWOCTRL_CH2OCV.
-#define BF_FTM_SWOCTRL_CH2OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH2OCV), uint32_t) & BM_FTM_SWOCTRL_CH2OCV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH2OCV field to a new value.
-#define BW_FTM_SWOCTRL_CH2OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OCV) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SWOCTRL, field CH3OCV[11] (RW)
- *
- * Values:
- * - 0 - The software output control forces 0 to the channel output.
- * - 1 - The software output control forces 1 to the channel output.
- */
-//@{
-#define BP_FTM_SWOCTRL_CH3OCV (11U) //!< Bit position for FTM_SWOCTRL_CH3OCV.
-#define BM_FTM_SWOCTRL_CH3OCV (0x00000800U) //!< Bit mask for FTM_SWOCTRL_CH3OCV.
-#define BS_FTM_SWOCTRL_CH3OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH3OCV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SWOCTRL_CH3OCV field.
-#define BR_FTM_SWOCTRL_CH3OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OCV))
-#endif
-
-//! @brief Format value for bitfield FTM_SWOCTRL_CH3OCV.
-#define BF_FTM_SWOCTRL_CH3OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH3OCV), uint32_t) & BM_FTM_SWOCTRL_CH3OCV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH3OCV field to a new value.
-#define BW_FTM_SWOCTRL_CH3OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OCV) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SWOCTRL, field CH4OCV[12] (RW)
- *
- * Values:
- * - 0 - The software output control forces 0 to the channel output.
- * - 1 - The software output control forces 1 to the channel output.
- */
-//@{
-#define BP_FTM_SWOCTRL_CH4OCV (12U) //!< Bit position for FTM_SWOCTRL_CH4OCV.
-#define BM_FTM_SWOCTRL_CH4OCV (0x00001000U) //!< Bit mask for FTM_SWOCTRL_CH4OCV.
-#define BS_FTM_SWOCTRL_CH4OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH4OCV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SWOCTRL_CH4OCV field.
-#define BR_FTM_SWOCTRL_CH4OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OCV))
-#endif
-
-//! @brief Format value for bitfield FTM_SWOCTRL_CH4OCV.
-#define BF_FTM_SWOCTRL_CH4OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH4OCV), uint32_t) & BM_FTM_SWOCTRL_CH4OCV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH4OCV field to a new value.
-#define BW_FTM_SWOCTRL_CH4OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OCV) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SWOCTRL, field CH5OCV[13] (RW)
- *
- * Values:
- * - 0 - The software output control forces 0 to the channel output.
- * - 1 - The software output control forces 1 to the channel output.
- */
-//@{
-#define BP_FTM_SWOCTRL_CH5OCV (13U) //!< Bit position for FTM_SWOCTRL_CH5OCV.
-#define BM_FTM_SWOCTRL_CH5OCV (0x00002000U) //!< Bit mask for FTM_SWOCTRL_CH5OCV.
-#define BS_FTM_SWOCTRL_CH5OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH5OCV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SWOCTRL_CH5OCV field.
-#define BR_FTM_SWOCTRL_CH5OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OCV))
-#endif
-
-//! @brief Format value for bitfield FTM_SWOCTRL_CH5OCV.
-#define BF_FTM_SWOCTRL_CH5OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH5OCV), uint32_t) & BM_FTM_SWOCTRL_CH5OCV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH5OCV field to a new value.
-#define BW_FTM_SWOCTRL_CH5OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OCV) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SWOCTRL, field CH6OCV[14] (RW)
- *
- * Values:
- * - 0 - The software output control forces 0 to the channel output.
- * - 1 - The software output control forces 1 to the channel output.
- */
-//@{
-#define BP_FTM_SWOCTRL_CH6OCV (14U) //!< Bit position for FTM_SWOCTRL_CH6OCV.
-#define BM_FTM_SWOCTRL_CH6OCV (0x00004000U) //!< Bit mask for FTM_SWOCTRL_CH6OCV.
-#define BS_FTM_SWOCTRL_CH6OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH6OCV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SWOCTRL_CH6OCV field.
-#define BR_FTM_SWOCTRL_CH6OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OCV))
-#endif
-
-//! @brief Format value for bitfield FTM_SWOCTRL_CH6OCV.
-#define BF_FTM_SWOCTRL_CH6OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH6OCV), uint32_t) & BM_FTM_SWOCTRL_CH6OCV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH6OCV field to a new value.
-#define BW_FTM_SWOCTRL_CH6OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OCV) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_SWOCTRL, field CH7OCV[15] (RW)
- *
- * Values:
- * - 0 - The software output control forces 0 to the channel output.
- * - 1 - The software output control forces 1 to the channel output.
- */
-//@{
-#define BP_FTM_SWOCTRL_CH7OCV (15U) //!< Bit position for FTM_SWOCTRL_CH7OCV.
-#define BM_FTM_SWOCTRL_CH7OCV (0x00008000U) //!< Bit mask for FTM_SWOCTRL_CH7OCV.
-#define BS_FTM_SWOCTRL_CH7OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH7OCV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_SWOCTRL_CH7OCV field.
-#define BR_FTM_SWOCTRL_CH7OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OCV))
-#endif
-
-//! @brief Format value for bitfield FTM_SWOCTRL_CH7OCV.
-#define BF_FTM_SWOCTRL_CH7OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH7OCV), uint32_t) & BM_FTM_SWOCTRL_CH7OCV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH7OCV field to a new value.
-#define BW_FTM_SWOCTRL_CH7OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OCV) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_FTM_PWMLOAD - FTM PWM Load
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_FTM_PWMLOAD - FTM PWM Load (RW)
- *
- * Reset value: 0x00000000U
- *
- * Enables the loading of the MOD, CNTIN, C(n)V, and C(n+1)V registers with the
- * values of their write buffers when the FTM counter changes from the MOD
- * register value to its next value or when a channel (j) match occurs. A match occurs
- * for the channel (j) when FTM counter = C(j)V.
- */
-typedef union _hw_ftm_pwmload
-{
- uint32_t U;
- struct _hw_ftm_pwmload_bitfields
- {
- uint32_t CH0SEL : 1; //!< [0] Channel 0 Select
- uint32_t CH1SEL : 1; //!< [1] Channel 1 Select
- uint32_t CH2SEL : 1; //!< [2] Channel 2 Select
- uint32_t CH3SEL : 1; //!< [3] Channel 3 Select
- uint32_t CH4SEL : 1; //!< [4] Channel 4 Select
- uint32_t CH5SEL : 1; //!< [5] Channel 5 Select
- uint32_t CH6SEL : 1; //!< [6] Channel 6 Select
- uint32_t CH7SEL : 1; //!< [7] Channel 7 Select
- uint32_t RESERVED0 : 1; //!< [8]
- uint32_t LDOK : 1; //!< [9] Load Enable
- uint32_t RESERVED1 : 22; //!< [31:10]
- } B;
-} hw_ftm_pwmload_t;
-#endif
-
-/*!
- * @name Constants and macros for entire FTM_PWMLOAD register
- */
-//@{
-#define HW_FTM_PWMLOAD_ADDR(x) (REGS_FTM_BASE(x) + 0x98U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_FTM_PWMLOAD(x) (*(__IO hw_ftm_pwmload_t *) HW_FTM_PWMLOAD_ADDR(x))
-#define HW_FTM_PWMLOAD_RD(x) (HW_FTM_PWMLOAD(x).U)
-#define HW_FTM_PWMLOAD_WR(x, v) (HW_FTM_PWMLOAD(x).U = (v))
-#define HW_FTM_PWMLOAD_SET(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) | (v)))
-#define HW_FTM_PWMLOAD_CLR(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) & ~(v)))
-#define HW_FTM_PWMLOAD_TOG(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual FTM_PWMLOAD bitfields
- */
-
-/*!
- * @name Register FTM_PWMLOAD, field CH0SEL[0] (RW)
- *
- * Values:
- * - 0 - Do not include the channel in the matching process.
- * - 1 - Include the channel in the matching process.
- */
-//@{
-#define BP_FTM_PWMLOAD_CH0SEL (0U) //!< Bit position for FTM_PWMLOAD_CH0SEL.
-#define BM_FTM_PWMLOAD_CH0SEL (0x00000001U) //!< Bit mask for FTM_PWMLOAD_CH0SEL.
-#define BS_FTM_PWMLOAD_CH0SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH0SEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_PWMLOAD_CH0SEL field.
-#define BR_FTM_PWMLOAD_CH0SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH0SEL))
-#endif
-
-//! @brief Format value for bitfield FTM_PWMLOAD_CH0SEL.
-#define BF_FTM_PWMLOAD_CH0SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH0SEL), uint32_t) & BM_FTM_PWMLOAD_CH0SEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH0SEL field to a new value.
-#define BW_FTM_PWMLOAD_CH0SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH0SEL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_PWMLOAD, field CH1SEL[1] (RW)
- *
- * Values:
- * - 0 - Do not include the channel in the matching process.
- * - 1 - Include the channel in the matching process.
- */
-//@{
-#define BP_FTM_PWMLOAD_CH1SEL (1U) //!< Bit position for FTM_PWMLOAD_CH1SEL.
-#define BM_FTM_PWMLOAD_CH1SEL (0x00000002U) //!< Bit mask for FTM_PWMLOAD_CH1SEL.
-#define BS_FTM_PWMLOAD_CH1SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH1SEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_PWMLOAD_CH1SEL field.
-#define BR_FTM_PWMLOAD_CH1SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH1SEL))
-#endif
-
-//! @brief Format value for bitfield FTM_PWMLOAD_CH1SEL.
-#define BF_FTM_PWMLOAD_CH1SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH1SEL), uint32_t) & BM_FTM_PWMLOAD_CH1SEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH1SEL field to a new value.
-#define BW_FTM_PWMLOAD_CH1SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH1SEL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_PWMLOAD, field CH2SEL[2] (RW)
- *
- * Values:
- * - 0 - Do not include the channel in the matching process.
- * - 1 - Include the channel in the matching process.
- */
-//@{
-#define BP_FTM_PWMLOAD_CH2SEL (2U) //!< Bit position for FTM_PWMLOAD_CH2SEL.
-#define BM_FTM_PWMLOAD_CH2SEL (0x00000004U) //!< Bit mask for FTM_PWMLOAD_CH2SEL.
-#define BS_FTM_PWMLOAD_CH2SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH2SEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_PWMLOAD_CH2SEL field.
-#define BR_FTM_PWMLOAD_CH2SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH2SEL))
-#endif
-
-//! @brief Format value for bitfield FTM_PWMLOAD_CH2SEL.
-#define BF_FTM_PWMLOAD_CH2SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH2SEL), uint32_t) & BM_FTM_PWMLOAD_CH2SEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH2SEL field to a new value.
-#define BW_FTM_PWMLOAD_CH2SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH2SEL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_PWMLOAD, field CH3SEL[3] (RW)
- *
- * Values:
- * - 0 - Do not include the channel in the matching process.
- * - 1 - Include the channel in the matching process.
- */
-//@{
-#define BP_FTM_PWMLOAD_CH3SEL (3U) //!< Bit position for FTM_PWMLOAD_CH3SEL.
-#define BM_FTM_PWMLOAD_CH3SEL (0x00000008U) //!< Bit mask for FTM_PWMLOAD_CH3SEL.
-#define BS_FTM_PWMLOAD_CH3SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH3SEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_PWMLOAD_CH3SEL field.
-#define BR_FTM_PWMLOAD_CH3SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH3SEL))
-#endif
-
-//! @brief Format value for bitfield FTM_PWMLOAD_CH3SEL.
-#define BF_FTM_PWMLOAD_CH3SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH3SEL), uint32_t) & BM_FTM_PWMLOAD_CH3SEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH3SEL field to a new value.
-#define BW_FTM_PWMLOAD_CH3SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH3SEL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_PWMLOAD, field CH4SEL[4] (RW)
- *
- * Values:
- * - 0 - Do not include the channel in the matching process.
- * - 1 - Include the channel in the matching process.
- */
-//@{
-#define BP_FTM_PWMLOAD_CH4SEL (4U) //!< Bit position for FTM_PWMLOAD_CH4SEL.
-#define BM_FTM_PWMLOAD_CH4SEL (0x00000010U) //!< Bit mask for FTM_PWMLOAD_CH4SEL.
-#define BS_FTM_PWMLOAD_CH4SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH4SEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_PWMLOAD_CH4SEL field.
-#define BR_FTM_PWMLOAD_CH4SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH4SEL))
-#endif
-
-//! @brief Format value for bitfield FTM_PWMLOAD_CH4SEL.
-#define BF_FTM_PWMLOAD_CH4SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH4SEL), uint32_t) & BM_FTM_PWMLOAD_CH4SEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH4SEL field to a new value.
-#define BW_FTM_PWMLOAD_CH4SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH4SEL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_PWMLOAD, field CH5SEL[5] (RW)
- *
- * Values:
- * - 0 - Do not include the channel in the matching process.
- * - 1 - Include the channel in the matching process.
- */
-//@{
-#define BP_FTM_PWMLOAD_CH5SEL (5U) //!< Bit position for FTM_PWMLOAD_CH5SEL.
-#define BM_FTM_PWMLOAD_CH5SEL (0x00000020U) //!< Bit mask for FTM_PWMLOAD_CH5SEL.
-#define BS_FTM_PWMLOAD_CH5SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH5SEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_PWMLOAD_CH5SEL field.
-#define BR_FTM_PWMLOAD_CH5SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH5SEL))
-#endif
-
-//! @brief Format value for bitfield FTM_PWMLOAD_CH5SEL.
-#define BF_FTM_PWMLOAD_CH5SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH5SEL), uint32_t) & BM_FTM_PWMLOAD_CH5SEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH5SEL field to a new value.
-#define BW_FTM_PWMLOAD_CH5SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH5SEL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_PWMLOAD, field CH6SEL[6] (RW)
- *
- * Values:
- * - 0 - Do not include the channel in the matching process.
- * - 1 - Include the channel in the matching process.
- */
-//@{
-#define BP_FTM_PWMLOAD_CH6SEL (6U) //!< Bit position for FTM_PWMLOAD_CH6SEL.
-#define BM_FTM_PWMLOAD_CH6SEL (0x00000040U) //!< Bit mask for FTM_PWMLOAD_CH6SEL.
-#define BS_FTM_PWMLOAD_CH6SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH6SEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_PWMLOAD_CH6SEL field.
-#define BR_FTM_PWMLOAD_CH6SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH6SEL))
-#endif
-
-//! @brief Format value for bitfield FTM_PWMLOAD_CH6SEL.
-#define BF_FTM_PWMLOAD_CH6SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH6SEL), uint32_t) & BM_FTM_PWMLOAD_CH6SEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH6SEL field to a new value.
-#define BW_FTM_PWMLOAD_CH6SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH6SEL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_PWMLOAD, field CH7SEL[7] (RW)
- *
- * Values:
- * - 0 - Do not include the channel in the matching process.
- * - 1 - Include the channel in the matching process.
- */
-//@{
-#define BP_FTM_PWMLOAD_CH7SEL (7U) //!< Bit position for FTM_PWMLOAD_CH7SEL.
-#define BM_FTM_PWMLOAD_CH7SEL (0x00000080U) //!< Bit mask for FTM_PWMLOAD_CH7SEL.
-#define BS_FTM_PWMLOAD_CH7SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH7SEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_PWMLOAD_CH7SEL field.
-#define BR_FTM_PWMLOAD_CH7SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH7SEL))
-#endif
-
-//! @brief Format value for bitfield FTM_PWMLOAD_CH7SEL.
-#define BF_FTM_PWMLOAD_CH7SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH7SEL), uint32_t) & BM_FTM_PWMLOAD_CH7SEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CH7SEL field to a new value.
-#define BW_FTM_PWMLOAD_CH7SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH7SEL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register FTM_PWMLOAD, field LDOK[9] (RW)
- *
- * Enables the loading of the MOD, CNTIN, and CV registers with the values of
- * their write buffers.
- *
- * Values:
- * - 0 - Loading updated values is disabled.
- * - 1 - Loading updated values is enabled.
- */
-//@{
-#define BP_FTM_PWMLOAD_LDOK (9U) //!< Bit position for FTM_PWMLOAD_LDOK.
-#define BM_FTM_PWMLOAD_LDOK (0x00000200U) //!< Bit mask for FTM_PWMLOAD_LDOK.
-#define BS_FTM_PWMLOAD_LDOK (1U) //!< Bit field size in bits for FTM_PWMLOAD_LDOK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the FTM_PWMLOAD_LDOK field.
-#define BR_FTM_PWMLOAD_LDOK(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_LDOK))
-#endif
-
-//! @brief Format value for bitfield FTM_PWMLOAD_LDOK.
-#define BF_FTM_PWMLOAD_LDOK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_LDOK), uint32_t) & BM_FTM_PWMLOAD_LDOK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LDOK field to a new value.
-#define BW_FTM_PWMLOAD_LDOK(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_LDOK) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_ftm_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All FTM module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_ftm
-{
- __IO hw_ftm_sc_t SC; //!< [0x0] Status And Control
- __IO hw_ftm_cnt_t CNT; //!< [0x4] Counter
- __IO hw_ftm_mod_t MOD; //!< [0x8] Modulo
- struct {
- __IO hw_ftm_cnsc_t CnSC; //!< [0xC] Channel (n) Status And Control
- __IO hw_ftm_cnv_t CnV; //!< [0x10] Channel (n) Value
- } CONTROLS[8];
- __IO hw_ftm_cntin_t CNTIN; //!< [0x4C] Counter Initial Value
- __IO hw_ftm_status_t STATUS; //!< [0x50] Capture And Compare Status
- __IO hw_ftm_mode_t MODE; //!< [0x54] Features Mode Selection
- __IO hw_ftm_sync_t SYNC; //!< [0x58] Synchronization
- __IO hw_ftm_outinit_t OUTINIT; //!< [0x5C] Initial State For Channels Output
- __IO hw_ftm_outmask_t OUTMASK; //!< [0x60] Output Mask
- __IO hw_ftm_combine_t COMBINE; //!< [0x64] Function For Linked Channels
- __IO hw_ftm_deadtime_t DEADTIME; //!< [0x68] Deadtime Insertion Control
- __IO hw_ftm_exttrig_t EXTTRIG; //!< [0x6C] FTM External Trigger
- __IO hw_ftm_pol_t POL; //!< [0x70] Channels Polarity
- __IO hw_ftm_fms_t FMS; //!< [0x74] Fault Mode Status
- __IO hw_ftm_filter_t FILTER; //!< [0x78] Input Capture Filter Control
- __IO hw_ftm_fltctrl_t FLTCTRL; //!< [0x7C] Fault Control
- __IO hw_ftm_qdctrl_t QDCTRL; //!< [0x80] Quadrature Decoder Control And Status
- __IO hw_ftm_conf_t CONF; //!< [0x84] Configuration
- __IO hw_ftm_fltpol_t FLTPOL; //!< [0x88] FTM Fault Input Polarity
- __IO hw_ftm_synconf_t SYNCONF; //!< [0x8C] Synchronization Configuration
- __IO hw_ftm_invctrl_t INVCTRL; //!< [0x90] FTM Inverting Control
- __IO hw_ftm_swoctrl_t SWOCTRL; //!< [0x94] FTM Software Output Control
- __IO hw_ftm_pwmload_t PWMLOAD; //!< [0x98] FTM PWM Load
-} hw_ftm_t;
-#pragma pack()
-
-//! @brief Macro to access all FTM registers.
-//! @param x FTM instance number.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_FTM(0)</code>.
-#define HW_FTM(x) (*(hw_ftm_t *) REGS_FTM_BASE(x))
-#endif
-
-#endif // __HW_FTM_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_gpio.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,500 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_GPIO_REGISTERS_H__
-#define __HW_GPIO_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 GPIO
- *
- * General Purpose Input/Output
- *
- * Registers defined in this header file:
- * - HW_GPIO_PDOR - Port Data Output Register
- * - HW_GPIO_PSOR - Port Set Output Register
- * - HW_GPIO_PCOR - Port Clear Output Register
- * - HW_GPIO_PTOR - Port Toggle Output Register
- * - HW_GPIO_PDIR - Port Data Input Register
- * - HW_GPIO_PDDR - Port Data Direction Register
- *
- * - hw_gpio_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_GPIO_BASE
-#define HW_GPIO_INSTANCE_COUNT (5U) //!< Number of instances of the GPIO module.
-#define HW_GPIOA (0U) //!< Instance number for GPIOA.
-#define HW_GPIOB (1U) //!< Instance number for GPIOB.
-#define HW_GPIOC (2U) //!< Instance number for GPIOC.
-#define HW_GPIOD (3U) //!< Instance number for GPIOD.
-#define HW_GPIOE (4U) //!< Instance number for GPIOE.
-#define REGS_GPIOA_BASE (0x400FF000U) //!< Base address for GPIOA.
-#define REGS_GPIOB_BASE (0x400FF040U) //!< Base address for GPIOB.
-#define REGS_GPIOC_BASE (0x400FF080U) //!< Base address for GPIOC.
-#define REGS_GPIOD_BASE (0x400FF0C0U) //!< Base address for GPIOD.
-#define REGS_GPIOE_BASE (0x400FF100U) //!< Base address for GPIOE.
-
-//! @brief Table of base addresses for GPIO instances.
-static const uint32_t __g_regs_GPIO_base_addresses[] = {
- REGS_GPIOA_BASE,
- REGS_GPIOB_BASE,
- REGS_GPIOC_BASE,
- REGS_GPIOD_BASE,
- REGS_GPIOE_BASE,
- };
-
-//! @brief Get the base address of GPIO by instance number.
-//! @param x GPIO instance number, from 0 through 4.
-#define REGS_GPIO_BASE(x) (__g_regs_GPIO_base_addresses[(x)])
-
-//! @brief Get the instance number given a base address.
-//! @param b Base address for an instance of GPIO.
-#define REGS_GPIO_INSTANCE(b) ((b) == REGS_GPIOA_BASE ? HW_GPIOA : (b) == REGS_GPIOB_BASE ? HW_GPIOB : (b) == REGS_GPIOC_BASE ? HW_GPIOC : (b) == REGS_GPIOD_BASE ? HW_GPIOD : (b) == REGS_GPIOE_BASE ? HW_GPIOE : 0)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_GPIO_PDOR - Port Data Output Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_GPIO_PDOR - Port Data Output Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register configures the logic levels that are driven on each
- * general-purpose output pins. Do not modify pin configuration registers associated with
- * pins not available in your selected package. All unbonded pins not available in
- * your package will default to DISABLE state for lowest power consumption.
- */
-typedef union _hw_gpio_pdor
-{
- uint32_t U;
- struct _hw_gpio_pdor_bitfields
- {
- uint32_t PDO : 32; //!< [31:0] Port Data Output
- } B;
-} hw_gpio_pdor_t;
-#endif
-
-/*!
- * @name Constants and macros for entire GPIO_PDOR register
- */
-//@{
-#define HW_GPIO_PDOR_ADDR(x) (REGS_GPIO_BASE(x) + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_GPIO_PDOR(x) (*(__IO hw_gpio_pdor_t *) HW_GPIO_PDOR_ADDR(x))
-#define HW_GPIO_PDOR_RD(x) (HW_GPIO_PDOR(x).U)
-#define HW_GPIO_PDOR_WR(x, v) (HW_GPIO_PDOR(x).U = (v))
-#define HW_GPIO_PDOR_SET(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) | (v)))
-#define HW_GPIO_PDOR_CLR(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) & ~(v)))
-#define HW_GPIO_PDOR_TOG(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual GPIO_PDOR bitfields
- */
-
-/*!
- * @name Register GPIO_PDOR, field PDO[31:0] (RW)
- *
- * Register bits for unbonded pins return a undefined value when read.
- *
- * Values:
- * - 0 - Logic level 0 is driven on pin, provided pin is configured for
- * general-purpose output.
- * - 1 - Logic level 1 is driven on pin, provided pin is configured for
- * general-purpose output.
- */
-//@{
-#define BP_GPIO_PDOR_PDO (0U) //!< Bit position for GPIO_PDOR_PDO.
-#define BM_GPIO_PDOR_PDO (0xFFFFFFFFU) //!< Bit mask for GPIO_PDOR_PDO.
-#define BS_GPIO_PDOR_PDO (32U) //!< Bit field size in bits for GPIO_PDOR_PDO.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the GPIO_PDOR_PDO field.
-#define BR_GPIO_PDOR_PDO(x) (HW_GPIO_PDOR(x).U)
-#endif
-
-//! @brief Format value for bitfield GPIO_PDOR_PDO.
-#define BF_GPIO_PDOR_PDO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PDOR_PDO), uint32_t) & BM_GPIO_PDOR_PDO)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PDO field to a new value.
-#define BW_GPIO_PDOR_PDO(x, v) (HW_GPIO_PDOR_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_GPIO_PSOR - Port Set Output Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_GPIO_PSOR - Port Set Output Register (WORZ)
- *
- * Reset value: 0x00000000U
- *
- * This register configures whether to set the fields of the PDOR.
- */
-typedef union _hw_gpio_psor
-{
- uint32_t U;
- struct _hw_gpio_psor_bitfields
- {
- uint32_t PTSO : 32; //!< [31:0] Port Set Output
- } B;
-} hw_gpio_psor_t;
-#endif
-
-/*!
- * @name Constants and macros for entire GPIO_PSOR register
- */
-//@{
-#define HW_GPIO_PSOR_ADDR(x) (REGS_GPIO_BASE(x) + 0x4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_GPIO_PSOR(x) (*(__O hw_gpio_psor_t *) HW_GPIO_PSOR_ADDR(x))
-#define HW_GPIO_PSOR_RD(x) (HW_GPIO_PSOR(x).U)
-#define HW_GPIO_PSOR_WR(x, v) (HW_GPIO_PSOR(x).U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual GPIO_PSOR bitfields
- */
-
-/*!
- * @name Register GPIO_PSOR, field PTSO[31:0] (WORZ)
- *
- * Writing to this register will update the contents of the corresponding bit in
- * the PDOR as follows:
- *
- * Values:
- * - 0 - Corresponding bit in PDORn does not change.
- * - 1 - Corresponding bit in PDORn is set to logic 1.
- */
-//@{
-#define BP_GPIO_PSOR_PTSO (0U) //!< Bit position for GPIO_PSOR_PTSO.
-#define BM_GPIO_PSOR_PTSO (0xFFFFFFFFU) //!< Bit mask for GPIO_PSOR_PTSO.
-#define BS_GPIO_PSOR_PTSO (32U) //!< Bit field size in bits for GPIO_PSOR_PTSO.
-
-//! @brief Format value for bitfield GPIO_PSOR_PTSO.
-#define BF_GPIO_PSOR_PTSO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PSOR_PTSO), uint32_t) & BM_GPIO_PSOR_PTSO)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PTSO field to a new value.
-#define BW_GPIO_PSOR_PTSO(x, v) (HW_GPIO_PSOR_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_GPIO_PCOR - Port Clear Output Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_GPIO_PCOR - Port Clear Output Register (WORZ)
- *
- * Reset value: 0x00000000U
- *
- * This register configures whether to clear the fields of PDOR.
- */
-typedef union _hw_gpio_pcor
-{
- uint32_t U;
- struct _hw_gpio_pcor_bitfields
- {
- uint32_t PTCO : 32; //!< [31:0] Port Clear Output
- } B;
-} hw_gpio_pcor_t;
-#endif
-
-/*!
- * @name Constants and macros for entire GPIO_PCOR register
- */
-//@{
-#define HW_GPIO_PCOR_ADDR(x) (REGS_GPIO_BASE(x) + 0x8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_GPIO_PCOR(x) (*(__O hw_gpio_pcor_t *) HW_GPIO_PCOR_ADDR(x))
-#define HW_GPIO_PCOR_RD(x) (HW_GPIO_PCOR(x).U)
-#define HW_GPIO_PCOR_WR(x, v) (HW_GPIO_PCOR(x).U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual GPIO_PCOR bitfields
- */
-
-/*!
- * @name Register GPIO_PCOR, field PTCO[31:0] (WORZ)
- *
- * Writing to this register will update the contents of the corresponding bit in
- * the Port Data Output Register (PDOR) as follows:
- *
- * Values:
- * - 0 - Corresponding bit in PDORn does not change.
- * - 1 - Corresponding bit in PDORn is cleared to logic 0.
- */
-//@{
-#define BP_GPIO_PCOR_PTCO (0U) //!< Bit position for GPIO_PCOR_PTCO.
-#define BM_GPIO_PCOR_PTCO (0xFFFFFFFFU) //!< Bit mask for GPIO_PCOR_PTCO.
-#define BS_GPIO_PCOR_PTCO (32U) //!< Bit field size in bits for GPIO_PCOR_PTCO.
-
-//! @brief Format value for bitfield GPIO_PCOR_PTCO.
-#define BF_GPIO_PCOR_PTCO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PCOR_PTCO), uint32_t) & BM_GPIO_PCOR_PTCO)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PTCO field to a new value.
-#define BW_GPIO_PCOR_PTCO(x, v) (HW_GPIO_PCOR_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_GPIO_PTOR - Port Toggle Output Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_GPIO_PTOR - Port Toggle Output Register (WORZ)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_gpio_ptor
-{
- uint32_t U;
- struct _hw_gpio_ptor_bitfields
- {
- uint32_t PTTO : 32; //!< [31:0] Port Toggle Output
- } B;
-} hw_gpio_ptor_t;
-#endif
-
-/*!
- * @name Constants and macros for entire GPIO_PTOR register
- */
-//@{
-#define HW_GPIO_PTOR_ADDR(x) (REGS_GPIO_BASE(x) + 0xCU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_GPIO_PTOR(x) (*(__O hw_gpio_ptor_t *) HW_GPIO_PTOR_ADDR(x))
-#define HW_GPIO_PTOR_RD(x) (HW_GPIO_PTOR(x).U)
-#define HW_GPIO_PTOR_WR(x, v) (HW_GPIO_PTOR(x).U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual GPIO_PTOR bitfields
- */
-
-/*!
- * @name Register GPIO_PTOR, field PTTO[31:0] (WORZ)
- *
- * Writing to this register will update the contents of the corresponding bit in
- * the PDOR as follows:
- *
- * Values:
- * - 0 - Corresponding bit in PDORn does not change.
- * - 1 - Corresponding bit in PDORn is set to the inverse of its existing logic
- * state.
- */
-//@{
-#define BP_GPIO_PTOR_PTTO (0U) //!< Bit position for GPIO_PTOR_PTTO.
-#define BM_GPIO_PTOR_PTTO (0xFFFFFFFFU) //!< Bit mask for GPIO_PTOR_PTTO.
-#define BS_GPIO_PTOR_PTTO (32U) //!< Bit field size in bits for GPIO_PTOR_PTTO.
-
-//! @brief Format value for bitfield GPIO_PTOR_PTTO.
-#define BF_GPIO_PTOR_PTTO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PTOR_PTTO), uint32_t) & BM_GPIO_PTOR_PTTO)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PTTO field to a new value.
-#define BW_GPIO_PTOR_PTTO(x, v) (HW_GPIO_PTOR_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_GPIO_PDIR - Port Data Input Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_GPIO_PDIR - Port Data Input Register (RO)
- *
- * Reset value: 0x00000000U
- *
- * Do not modify pin configuration registers associated with pins not available
- * in your selected package. All unbonded pins not available in your package will
- * default to DISABLE state for lowest power consumption.
- */
-typedef union _hw_gpio_pdir
-{
- uint32_t U;
- struct _hw_gpio_pdir_bitfields
- {
- uint32_t PDI : 32; //!< [31:0] Port Data Input
- } B;
-} hw_gpio_pdir_t;
-#endif
-
-/*!
- * @name Constants and macros for entire GPIO_PDIR register
- */
-//@{
-#define HW_GPIO_PDIR_ADDR(x) (REGS_GPIO_BASE(x) + 0x10U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_GPIO_PDIR(x) (*(__I hw_gpio_pdir_t *) HW_GPIO_PDIR_ADDR(x))
-#define HW_GPIO_PDIR_RD(x) (HW_GPIO_PDIR(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual GPIO_PDIR bitfields
- */
-
-/*!
- * @name Register GPIO_PDIR, field PDI[31:0] (RO)
- *
- * Reads 0 at the unimplemented pins for a particular device. Pins that are not
- * configured for a digital function read 0. If the Port Control and Interrupt
- * module is disabled, then the corresponding bit in PDIR does not update.
- *
- * Values:
- * - 0 - Pin logic level is logic 0, or is not configured for use by digital
- * function.
- * - 1 - Pin logic level is logic 1.
- */
-//@{
-#define BP_GPIO_PDIR_PDI (0U) //!< Bit position for GPIO_PDIR_PDI.
-#define BM_GPIO_PDIR_PDI (0xFFFFFFFFU) //!< Bit mask for GPIO_PDIR_PDI.
-#define BS_GPIO_PDIR_PDI (32U) //!< Bit field size in bits for GPIO_PDIR_PDI.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the GPIO_PDIR_PDI field.
-#define BR_GPIO_PDIR_PDI(x) (HW_GPIO_PDIR(x).U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_GPIO_PDDR - Port Data Direction Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_GPIO_PDDR - Port Data Direction Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * The PDDR configures the individual port pins for input or output.
- */
-typedef union _hw_gpio_pddr
-{
- uint32_t U;
- struct _hw_gpio_pddr_bitfields
- {
- uint32_t PDD : 32; //!< [31:0] Port Data Direction
- } B;
-} hw_gpio_pddr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire GPIO_PDDR register
- */
-//@{
-#define HW_GPIO_PDDR_ADDR(x) (REGS_GPIO_BASE(x) + 0x14U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_GPIO_PDDR(x) (*(__IO hw_gpio_pddr_t *) HW_GPIO_PDDR_ADDR(x))
-#define HW_GPIO_PDDR_RD(x) (HW_GPIO_PDDR(x).U)
-#define HW_GPIO_PDDR_WR(x, v) (HW_GPIO_PDDR(x).U = (v))
-#define HW_GPIO_PDDR_SET(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) | (v)))
-#define HW_GPIO_PDDR_CLR(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) & ~(v)))
-#define HW_GPIO_PDDR_TOG(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual GPIO_PDDR bitfields
- */
-
-/*!
- * @name Register GPIO_PDDR, field PDD[31:0] (RW)
- *
- * Configures individual port pins for input or output.
- *
- * Values:
- * - 0 - Pin is configured as general-purpose input, for the GPIO function.
- * - 1 - Pin is configured as general-purpose output, for the GPIO function.
- */
-//@{
-#define BP_GPIO_PDDR_PDD (0U) //!< Bit position for GPIO_PDDR_PDD.
-#define BM_GPIO_PDDR_PDD (0xFFFFFFFFU) //!< Bit mask for GPIO_PDDR_PDD.
-#define BS_GPIO_PDDR_PDD (32U) //!< Bit field size in bits for GPIO_PDDR_PDD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the GPIO_PDDR_PDD field.
-#define BR_GPIO_PDDR_PDD(x) (HW_GPIO_PDDR(x).U)
-#endif
-
-//! @brief Format value for bitfield GPIO_PDDR_PDD.
-#define BF_GPIO_PDDR_PDD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PDDR_PDD), uint32_t) & BM_GPIO_PDDR_PDD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PDD field to a new value.
-#define BW_GPIO_PDDR_PDD(x, v) (HW_GPIO_PDDR_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_gpio_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All GPIO module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_gpio
-{
- __IO hw_gpio_pdor_t PDOR; //!< [0x0] Port Data Output Register
- __O hw_gpio_psor_t PSOR; //!< [0x4] Port Set Output Register
- __O hw_gpio_pcor_t PCOR; //!< [0x8] Port Clear Output Register
- __O hw_gpio_ptor_t PTOR; //!< [0xC] Port Toggle Output Register
- __I hw_gpio_pdir_t PDIR; //!< [0x10] Port Data Input Register
- __IO hw_gpio_pddr_t PDDR; //!< [0x14] Port Data Direction Register
-} hw_gpio_t;
-#pragma pack()
-
-//! @brief Macro to access all GPIO registers.
-//! @param x GPIO instance number.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_GPIO(0)</code>.
-#define HW_GPIO(x) (*(hw_gpio_t *) REGS_GPIO_BASE(x))
-#endif
-
-#endif // __HW_GPIO_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_i2c.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1902 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_I2C_REGISTERS_H__
-#define __HW_I2C_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 I2C
- *
- * Inter-Integrated Circuit
- *
- * Registers defined in this header file:
- * - HW_I2C_A1 - I2C Address Register 1
- * - HW_I2C_F - I2C Frequency Divider register
- * - HW_I2C_C1 - I2C Control Register 1
- * - HW_I2C_S - I2C Status register
- * - HW_I2C_D - I2C Data I/O register
- * - HW_I2C_C2 - I2C Control Register 2
- * - HW_I2C_FLT - I2C Programmable Input Glitch Filter register
- * - HW_I2C_RA - I2C Range Address register
- * - HW_I2C_SMB - I2C SMBus Control and Status register
- * - HW_I2C_A2 - I2C Address Register 2
- * - HW_I2C_SLTH - I2C SCL Low Timeout Register High
- * - HW_I2C_SLTL - I2C SCL Low Timeout Register Low
- *
- * - hw_i2c_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_I2C_BASE
-#define HW_I2C_INSTANCE_COUNT (3U) //!< Number of instances of the I2C module.
-#define HW_I2C0 (0U) //!< Instance number for I2C0.
-#define HW_I2C1 (1U) //!< Instance number for I2C1.
-#define HW_I2C2 (2U) //!< Instance number for I2C2.
-#define REGS_I2C0_BASE (0x40066000U) //!< Base address for I2C0.
-#define REGS_I2C1_BASE (0x40067000U) //!< Base address for I2C1.
-#define REGS_I2C2_BASE (0x400E6000U) //!< Base address for I2C2.
-
-//! @brief Table of base addresses for I2C instances.
-static const uint32_t __g_regs_I2C_base_addresses[] = {
- REGS_I2C0_BASE,
- REGS_I2C1_BASE,
- REGS_I2C2_BASE,
- };
-
-//! @brief Get the base address of I2C by instance number.
-//! @param x I2C instance number, from 0 through 2.
-#define REGS_I2C_BASE(x) (__g_regs_I2C_base_addresses[(x)])
-
-//! @brief Get the instance number given a base address.
-//! @param b Base address for an instance of I2C.
-#define REGS_I2C_INSTANCE(b) ((b) == REGS_I2C0_BASE ? HW_I2C0 : (b) == REGS_I2C1_BASE ? HW_I2C1 : (b) == REGS_I2C2_BASE ? HW_I2C2 : 0)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2C_A1 - I2C Address Register 1
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2C_A1 - I2C Address Register 1 (RW)
- *
- * Reset value: 0x00U
- *
- * This register contains the slave address to be used by the I2C module.
- */
-typedef union _hw_i2c_a1
-{
- uint8_t U;
- struct _hw_i2c_a1_bitfields
- {
- uint8_t RESERVED0 : 1; //!< [0]
- uint8_t AD : 7; //!< [7:1] Address
- } B;
-} hw_i2c_a1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2C_A1 register
- */
-//@{
-#define HW_I2C_A1_ADDR(x) (REGS_I2C_BASE(x) + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2C_A1(x) (*(__IO hw_i2c_a1_t *) HW_I2C_A1_ADDR(x))
-#define HW_I2C_A1_RD(x) (HW_I2C_A1(x).U)
-#define HW_I2C_A1_WR(x, v) (HW_I2C_A1(x).U = (v))
-#define HW_I2C_A1_SET(x, v) (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) | (v)))
-#define HW_I2C_A1_CLR(x, v) (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) & ~(v)))
-#define HW_I2C_A1_TOG(x, v) (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2C_A1 bitfields
- */
-
-/*!
- * @name Register I2C_A1, field AD[7:1] (RW)
- *
- * Contains the primary slave address used by the I2C module when it is
- * addressed as a slave. This field is used in the 7-bit address scheme and the lower
- * seven bits in the 10-bit address scheme.
- */
-//@{
-#define BP_I2C_A1_AD (1U) //!< Bit position for I2C_A1_AD.
-#define BM_I2C_A1_AD (0xFEU) //!< Bit mask for I2C_A1_AD.
-#define BS_I2C_A1_AD (7U) //!< Bit field size in bits for I2C_A1_AD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_A1_AD field.
-#define BR_I2C_A1_AD(x) (HW_I2C_A1(x).B.AD)
-#endif
-
-//! @brief Format value for bitfield I2C_A1_AD.
-#define BF_I2C_A1_AD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_A1_AD), uint8_t) & BM_I2C_A1_AD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the AD field to a new value.
-#define BW_I2C_A1_AD(x, v) (HW_I2C_A1_WR(x, (HW_I2C_A1_RD(x) & ~BM_I2C_A1_AD) | BF_I2C_A1_AD(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2C_F - I2C Frequency Divider register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2C_F - I2C Frequency Divider register (RW)
- *
- * Reset value: 0x00U
- */
-typedef union _hw_i2c_f
-{
- uint8_t U;
- struct _hw_i2c_f_bitfields
- {
- uint8_t ICR : 6; //!< [5:0] ClockRate
- uint8_t MULT : 2; //!< [7:6] Multiplier Factor
- } B;
-} hw_i2c_f_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2C_F register
- */
-//@{
-#define HW_I2C_F_ADDR(x) (REGS_I2C_BASE(x) + 0x1U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2C_F(x) (*(__IO hw_i2c_f_t *) HW_I2C_F_ADDR(x))
-#define HW_I2C_F_RD(x) (HW_I2C_F(x).U)
-#define HW_I2C_F_WR(x, v) (HW_I2C_F(x).U = (v))
-#define HW_I2C_F_SET(x, v) (HW_I2C_F_WR(x, HW_I2C_F_RD(x) | (v)))
-#define HW_I2C_F_CLR(x, v) (HW_I2C_F_WR(x, HW_I2C_F_RD(x) & ~(v)))
-#define HW_I2C_F_TOG(x, v) (HW_I2C_F_WR(x, HW_I2C_F_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2C_F bitfields
- */
-
-/*!
- * @name Register I2C_F, field ICR[5:0] (RW)
- *
- * Prescales the I2C module clock for bit rate selection. This field and the
- * MULT field determine the I2C baud rate, the SDA hold time, the SCL start hold
- * time, and the SCL stop hold time. For a list of values corresponding to each ICR
- * setting, see I2C divider and hold values. The SCL divider multiplied by
- * multiplier factor (mul) determines the I2C baud rate. I2C baud rate = I2C module
- * clock speed (Hz)/(mul * SCL divider) The SDA hold time is the delay from the
- * falling edge of SCL (I2C clock) to the changing of SDA (I2C data). SDA hold time =
- * I2C module clock period (s) * mul * SDA hold value The SCL start hold time is
- * the delay from the falling edge of SDA (I2C data) while SCL is high (start
- * condition) to the falling edge of SCL (I2C clock). SCL start hold time = I2C
- * module clock period (s) * mul * SCL start hold value The SCL stop hold time is
- * the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C
- * data) while SCL is high (stop condition). SCL stop hold time = I2C module
- * clock period (s) * mul * SCL stop hold value For example, if the I2C module clock
- * speed is 8 MHz, the following table shows the possible hold time values with
- * different ICR and MULT selections to achieve an I2C baud rate of 100 kbit/s.
- * MULT ICR Hold times (μs) SDA SCL Start SCL Stop 2h 00h 3.500 3.000 5.500 1h
- * 07h 2.500 4.000 5.250 1h 0Bh 2.250 4.000 5.250 0h 14h 2.125 4.250 5.125 0h 18h
- * 1.125 4.750 5.125
- */
-//@{
-#define BP_I2C_F_ICR (0U) //!< Bit position for I2C_F_ICR.
-#define BM_I2C_F_ICR (0x3FU) //!< Bit mask for I2C_F_ICR.
-#define BS_I2C_F_ICR (6U) //!< Bit field size in bits for I2C_F_ICR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_F_ICR field.
-#define BR_I2C_F_ICR(x) (HW_I2C_F(x).B.ICR)
-#endif
-
-//! @brief Format value for bitfield I2C_F_ICR.
-#define BF_I2C_F_ICR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_F_ICR), uint8_t) & BM_I2C_F_ICR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ICR field to a new value.
-#define BW_I2C_F_ICR(x, v) (HW_I2C_F_WR(x, (HW_I2C_F_RD(x) & ~BM_I2C_F_ICR) | BF_I2C_F_ICR(v)))
-#endif
-//@}
-
-/*!
- * @name Register I2C_F, field MULT[7:6] (RW)
- *
- * Defines the multiplier factor (mul). This factor is used along with the SCL
- * divider to generate the I2C baud rate.
- *
- * Values:
- * - 00 - mul = 1
- * - 01 - mul = 2
- * - 10 - mul = 4
- * - 11 - Reserved
- */
-//@{
-#define BP_I2C_F_MULT (6U) //!< Bit position for I2C_F_MULT.
-#define BM_I2C_F_MULT (0xC0U) //!< Bit mask for I2C_F_MULT.
-#define BS_I2C_F_MULT (2U) //!< Bit field size in bits for I2C_F_MULT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_F_MULT field.
-#define BR_I2C_F_MULT(x) (HW_I2C_F(x).B.MULT)
-#endif
-
-//! @brief Format value for bitfield I2C_F_MULT.
-#define BF_I2C_F_MULT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_F_MULT), uint8_t) & BM_I2C_F_MULT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MULT field to a new value.
-#define BW_I2C_F_MULT(x, v) (HW_I2C_F_WR(x, (HW_I2C_F_RD(x) & ~BM_I2C_F_MULT) | BF_I2C_F_MULT(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2C_C1 - I2C Control Register 1
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2C_C1 - I2C Control Register 1 (RW)
- *
- * Reset value: 0x00U
- */
-typedef union _hw_i2c_c1
-{
- uint8_t U;
- struct _hw_i2c_c1_bitfields
- {
- uint8_t DMAEN : 1; //!< [0] DMA Enable
- uint8_t WUEN : 1; //!< [1] Wakeup Enable
- uint8_t RSTA : 1; //!< [2] Repeat START
- uint8_t TXAK : 1; //!< [3] Transmit Acknowledge Enable
- uint8_t TX : 1; //!< [4] Transmit Mode Select
- uint8_t MST : 1; //!< [5] Master Mode Select
- uint8_t IICIE : 1; //!< [6] I2C Interrupt Enable
- uint8_t IICEN : 1; //!< [7] I2C Enable
- } B;
-} hw_i2c_c1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2C_C1 register
- */
-//@{
-#define HW_I2C_C1_ADDR(x) (REGS_I2C_BASE(x) + 0x2U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2C_C1(x) (*(__IO hw_i2c_c1_t *) HW_I2C_C1_ADDR(x))
-#define HW_I2C_C1_RD(x) (HW_I2C_C1(x).U)
-#define HW_I2C_C1_WR(x, v) (HW_I2C_C1(x).U = (v))
-#define HW_I2C_C1_SET(x, v) (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) | (v)))
-#define HW_I2C_C1_CLR(x, v) (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) & ~(v)))
-#define HW_I2C_C1_TOG(x, v) (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2C_C1 bitfields
- */
-
-/*!
- * @name Register I2C_C1, field DMAEN[0] (RW)
- *
- * Enables or disables the DMA function.
- *
- * Values:
- * - 0 - All DMA signalling disabled.
- * - 1 - DMA transfer is enabled. While SMB[FACK] = 0, the following conditions
- * trigger the DMA request: a data byte is received, and either address or
- * data is transmitted. (ACK/NACK is automatic) the first byte received matches
- * the A1 register or is a general call address. If any address matching
- * occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known
- * from master to slave, then it is not required to check S[SRW]. With this
- * assumption, DMA can also be used in this case. In other cases, if the master
- * reads data from the slave, then it is required to rewrite the C1 register
- * operation. With this assumption, DMA cannot be used. When FACK = 1, an
- * address or a data byte is transmitted.
- */
-//@{
-#define BP_I2C_C1_DMAEN (0U) //!< Bit position for I2C_C1_DMAEN.
-#define BM_I2C_C1_DMAEN (0x01U) //!< Bit mask for I2C_C1_DMAEN.
-#define BS_I2C_C1_DMAEN (1U) //!< Bit field size in bits for I2C_C1_DMAEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_C1_DMAEN field.
-#define BR_I2C_C1_DMAEN(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_DMAEN))
-#endif
-
-//! @brief Format value for bitfield I2C_C1_DMAEN.
-#define BF_I2C_C1_DMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_DMAEN), uint8_t) & BM_I2C_C1_DMAEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DMAEN field to a new value.
-#define BW_I2C_C1_DMAEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_DMAEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2C_C1, field WUEN[1] (RW)
- *
- * The I2C module can wake the MCU from low power mode with no peripheral bus
- * running when slave address matching occurs.
- *
- * Values:
- * - 0 - Normal operation. No interrupt generated when address matching in low
- * power mode.
- * - 1 - Enables the wakeup function in low power mode.
- */
-//@{
-#define BP_I2C_C1_WUEN (1U) //!< Bit position for I2C_C1_WUEN.
-#define BM_I2C_C1_WUEN (0x02U) //!< Bit mask for I2C_C1_WUEN.
-#define BS_I2C_C1_WUEN (1U) //!< Bit field size in bits for I2C_C1_WUEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_C1_WUEN field.
-#define BR_I2C_C1_WUEN(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_WUEN))
-#endif
-
-//! @brief Format value for bitfield I2C_C1_WUEN.
-#define BF_I2C_C1_WUEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_WUEN), uint8_t) & BM_I2C_C1_WUEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUEN field to a new value.
-#define BW_I2C_C1_WUEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_WUEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2C_C1, field RSTA[2] (WORZ)
- *
- * Writing 1 to this bit generates a repeated START condition provided it is the
- * current master. This bit will always be read as 0. Attempting a repeat at the
- * wrong time results in loss of arbitration.
- */
-//@{
-#define BP_I2C_C1_RSTA (2U) //!< Bit position for I2C_C1_RSTA.
-#define BM_I2C_C1_RSTA (0x04U) //!< Bit mask for I2C_C1_RSTA.
-#define BS_I2C_C1_RSTA (1U) //!< Bit field size in bits for I2C_C1_RSTA.
-
-//! @brief Format value for bitfield I2C_C1_RSTA.
-#define BF_I2C_C1_RSTA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_RSTA), uint8_t) & BM_I2C_C1_RSTA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RSTA field to a new value.
-#define BW_I2C_C1_RSTA(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_RSTA) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2C_C1, field TXAK[3] (RW)
- *
- * Specifies the value driven onto the SDA during data acknowledge cycles for
- * both master and slave receivers. The value of SMB[FACK] affects NACK/ACK
- * generation. SCL is held low until TXAK is written.
- *
- * Values:
- * - 0 - An acknowledge signal is sent to the bus on the following receiving
- * byte (if FACK is cleared) or the current receiving byte (if FACK is set).
- * - 1 - No acknowledge signal is sent to the bus on the following receiving
- * data byte (if FACK is cleared) or the current receiving data byte (if FACK is
- * set).
- */
-//@{
-#define BP_I2C_C1_TXAK (3U) //!< Bit position for I2C_C1_TXAK.
-#define BM_I2C_C1_TXAK (0x08U) //!< Bit mask for I2C_C1_TXAK.
-#define BS_I2C_C1_TXAK (1U) //!< Bit field size in bits for I2C_C1_TXAK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_C1_TXAK field.
-#define BR_I2C_C1_TXAK(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TXAK))
-#endif
-
-//! @brief Format value for bitfield I2C_C1_TXAK.
-#define BF_I2C_C1_TXAK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_TXAK), uint8_t) & BM_I2C_C1_TXAK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TXAK field to a new value.
-#define BW_I2C_C1_TXAK(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TXAK) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2C_C1, field TX[4] (RW)
- *
- * Selects the direction of master and slave transfers. In master mode this bit
- * must be set according to the type of transfer required. Therefore, for address
- * cycles, this bit is always set. When addressed as a slave this bit must be
- * set by software according to the SRW bit in the status register.
- *
- * Values:
- * - 0 - Receive
- * - 1 - Transmit
- */
-//@{
-#define BP_I2C_C1_TX (4U) //!< Bit position for I2C_C1_TX.
-#define BM_I2C_C1_TX (0x10U) //!< Bit mask for I2C_C1_TX.
-#define BS_I2C_C1_TX (1U) //!< Bit field size in bits for I2C_C1_TX.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_C1_TX field.
-#define BR_I2C_C1_TX(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TX))
-#endif
-
-//! @brief Format value for bitfield I2C_C1_TX.
-#define BF_I2C_C1_TX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_TX), uint8_t) & BM_I2C_C1_TX)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TX field to a new value.
-#define BW_I2C_C1_TX(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TX) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2C_C1, field MST[5] (RW)
- *
- * When MST is changed from 0 to 1, a START signal is generated on the bus and
- * master mode is selected. When this bit changes from 1 to 0, a STOP signal is
- * generated and the mode of operation changes from master to slave.
- *
- * Values:
- * - 0 - Slave mode
- * - 1 - Master mode
- */
-//@{
-#define BP_I2C_C1_MST (5U) //!< Bit position for I2C_C1_MST.
-#define BM_I2C_C1_MST (0x20U) //!< Bit mask for I2C_C1_MST.
-#define BS_I2C_C1_MST (1U) //!< Bit field size in bits for I2C_C1_MST.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_C1_MST field.
-#define BR_I2C_C1_MST(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_MST))
-#endif
-
-//! @brief Format value for bitfield I2C_C1_MST.
-#define BF_I2C_C1_MST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_MST), uint8_t) & BM_I2C_C1_MST)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MST field to a new value.
-#define BW_I2C_C1_MST(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_MST) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2C_C1, field IICIE[6] (RW)
- *
- * Enables I2C interrupt requests.
- *
- * Values:
- * - 0 - Disabled
- * - 1 - Enabled
- */
-//@{
-#define BP_I2C_C1_IICIE (6U) //!< Bit position for I2C_C1_IICIE.
-#define BM_I2C_C1_IICIE (0x40U) //!< Bit mask for I2C_C1_IICIE.
-#define BS_I2C_C1_IICIE (1U) //!< Bit field size in bits for I2C_C1_IICIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_C1_IICIE field.
-#define BR_I2C_C1_IICIE(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICIE))
-#endif
-
-//! @brief Format value for bitfield I2C_C1_IICIE.
-#define BF_I2C_C1_IICIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_IICIE), uint8_t) & BM_I2C_C1_IICIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IICIE field to a new value.
-#define BW_I2C_C1_IICIE(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2C_C1, field IICEN[7] (RW)
- *
- * Enables I2C module operation.
- *
- * Values:
- * - 0 - Disabled
- * - 1 - Enabled
- */
-//@{
-#define BP_I2C_C1_IICEN (7U) //!< Bit position for I2C_C1_IICEN.
-#define BM_I2C_C1_IICEN (0x80U) //!< Bit mask for I2C_C1_IICEN.
-#define BS_I2C_C1_IICEN (1U) //!< Bit field size in bits for I2C_C1_IICEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_C1_IICEN field.
-#define BR_I2C_C1_IICEN(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICEN))
-#endif
-
-//! @brief Format value for bitfield I2C_C1_IICEN.
-#define BF_I2C_C1_IICEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_IICEN), uint8_t) & BM_I2C_C1_IICEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IICEN field to a new value.
-#define BW_I2C_C1_IICEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICEN) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2C_S - I2C Status register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2C_S - I2C Status register (RW)
- *
- * Reset value: 0x80U
- */
-typedef union _hw_i2c_s
-{
- uint8_t U;
- struct _hw_i2c_s_bitfields
- {
- uint8_t RXAK : 1; //!< [0] Receive Acknowledge
- uint8_t IICIF : 1; //!< [1] Interrupt Flag
- uint8_t SRW : 1; //!< [2] Slave Read/Write
- uint8_t RAM : 1; //!< [3] Range Address Match
- uint8_t ARBL : 1; //!< [4] Arbitration Lost
- uint8_t BUSY : 1; //!< [5] Bus Busy
- uint8_t IAAS : 1; //!< [6] Addressed As A Slave
- uint8_t TCF : 1; //!< [7] Transfer Complete Flag
- } B;
-} hw_i2c_s_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2C_S register
- */
-//@{
-#define HW_I2C_S_ADDR(x) (REGS_I2C_BASE(x) + 0x3U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2C_S(x) (*(__IO hw_i2c_s_t *) HW_I2C_S_ADDR(x))
-#define HW_I2C_S_RD(x) (HW_I2C_S(x).U)
-#define HW_I2C_S_WR(x, v) (HW_I2C_S(x).U = (v))
-#define HW_I2C_S_SET(x, v) (HW_I2C_S_WR(x, HW_I2C_S_RD(x) | (v)))
-#define HW_I2C_S_CLR(x, v) (HW_I2C_S_WR(x, HW_I2C_S_RD(x) & ~(v)))
-#define HW_I2C_S_TOG(x, v) (HW_I2C_S_WR(x, HW_I2C_S_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2C_S bitfields
- */
-
-/*!
- * @name Register I2C_S, field RXAK[0] (RO)
- *
- * Values:
- * - 0 - Acknowledge signal was received after the completion of one byte of
- * data transmission on the bus
- * - 1 - No acknowledge signal detected
- */
-//@{
-#define BP_I2C_S_RXAK (0U) //!< Bit position for I2C_S_RXAK.
-#define BM_I2C_S_RXAK (0x01U) //!< Bit mask for I2C_S_RXAK.
-#define BS_I2C_S_RXAK (1U) //!< Bit field size in bits for I2C_S_RXAK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_S_RXAK field.
-#define BR_I2C_S_RXAK(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RXAK))
-#endif
-//@}
-
-/*!
- * @name Register I2C_S, field IICIF[1] (W1C)
- *
- * This bit sets when an interrupt is pending. This bit must be cleared by
- * software by writing 1 to it, such as in the interrupt routine. One of the following
- * events can set this bit: One byte transfer, including ACK/NACK bit, completes
- * if FACK is 0. An ACK or NACK is sent on the bus by writing 0 or 1 to TXAK
- * after this bit is set in receive mode. One byte transfer, excluding ACK/NACK bit,
- * completes if FACK is 1. Match of slave address to calling address including
- * primary slave address, range slave address , alert response address, second
- * slave address, or general call address. Arbitration lost In SMBus mode, any
- * timeouts except SCL and SDA high timeouts I2C bus stop or start detection if the
- * SSIE bit in the Input Glitch Filter register is 1 To clear the I2C bus stop or
- * start detection interrupt: In the interrupt service routine, first clear the
- * STOPF or STARTF bit in the Input Glitch Filter register by writing 1 to it, and
- * then clear the IICIF bit. If this sequence is reversed, the IICIF bit is
- * asserted again.
- *
- * Values:
- * - 0 - No interrupt pending
- * - 1 - Interrupt pending
- */
-//@{
-#define BP_I2C_S_IICIF (1U) //!< Bit position for I2C_S_IICIF.
-#define BM_I2C_S_IICIF (0x02U) //!< Bit mask for I2C_S_IICIF.
-#define BS_I2C_S_IICIF (1U) //!< Bit field size in bits for I2C_S_IICIF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_S_IICIF field.
-#define BR_I2C_S_IICIF(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IICIF))
-#endif
-
-//! @brief Format value for bitfield I2C_S_IICIF.
-#define BF_I2C_S_IICIF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_S_IICIF), uint8_t) & BM_I2C_S_IICIF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IICIF field to a new value.
-#define BW_I2C_S_IICIF(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IICIF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2C_S, field SRW[2] (RO)
- *
- * When addressed as a slave, SRW indicates the value of the R/W command bit of
- * the calling address sent to the master.
- *
- * Values:
- * - 0 - Slave receive, master writing to slave
- * - 1 - Slave transmit, master reading from slave
- */
-//@{
-#define BP_I2C_S_SRW (2U) //!< Bit position for I2C_S_SRW.
-#define BM_I2C_S_SRW (0x04U) //!< Bit mask for I2C_S_SRW.
-#define BS_I2C_S_SRW (1U) //!< Bit field size in bits for I2C_S_SRW.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_S_SRW field.
-#define BR_I2C_S_SRW(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_SRW))
-#endif
-//@}
-
-/*!
- * @name Register I2C_S, field RAM[3] (RW)
- *
- * This bit is set to 1 by any of the following conditions, if I2C_C2[RMEN] = 1:
- * Any nonzero calling address is received that matches the address in the RA
- * register. The calling address is within the range of values of the A1 and RA
- * registers. For the RAM bit to be set to 1 correctly, C1[IICIE] must be set to 1.
- * Writing the C1 register with any value clears this bit to 0.
- *
- * Values:
- * - 0 - Not addressed
- * - 1 - Addressed as a slave
- */
-//@{
-#define BP_I2C_S_RAM (3U) //!< Bit position for I2C_S_RAM.
-#define BM_I2C_S_RAM (0x08U) //!< Bit mask for I2C_S_RAM.
-#define BS_I2C_S_RAM (1U) //!< Bit field size in bits for I2C_S_RAM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_S_RAM field.
-#define BR_I2C_S_RAM(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RAM))
-#endif
-
-//! @brief Format value for bitfield I2C_S_RAM.
-#define BF_I2C_S_RAM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_S_RAM), uint8_t) & BM_I2C_S_RAM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RAM field to a new value.
-#define BW_I2C_S_RAM(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RAM) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2C_S, field ARBL[4] (W1C)
- *
- * This bit is set by hardware when the arbitration procedure is lost. The ARBL
- * bit must be cleared by software, by writing 1 to it.
- *
- * Values:
- * - 0 - Standard bus operation.
- * - 1 - Loss of arbitration.
- */
-//@{
-#define BP_I2C_S_ARBL (4U) //!< Bit position for I2C_S_ARBL.
-#define BM_I2C_S_ARBL (0x10U) //!< Bit mask for I2C_S_ARBL.
-#define BS_I2C_S_ARBL (1U) //!< Bit field size in bits for I2C_S_ARBL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_S_ARBL field.
-#define BR_I2C_S_ARBL(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_ARBL))
-#endif
-
-//! @brief Format value for bitfield I2C_S_ARBL.
-#define BF_I2C_S_ARBL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_S_ARBL), uint8_t) & BM_I2C_S_ARBL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ARBL field to a new value.
-#define BW_I2C_S_ARBL(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_ARBL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2C_S, field BUSY[5] (RO)
- *
- * Indicates the status of the bus regardless of slave or master mode. This bit
- * is set when a START signal is detected and cleared when a STOP signal is
- * detected.
- *
- * Values:
- * - 0 - Bus is idle
- * - 1 - Bus is busy
- */
-//@{
-#define BP_I2C_S_BUSY (5U) //!< Bit position for I2C_S_BUSY.
-#define BM_I2C_S_BUSY (0x20U) //!< Bit mask for I2C_S_BUSY.
-#define BS_I2C_S_BUSY (1U) //!< Bit field size in bits for I2C_S_BUSY.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_S_BUSY field.
-#define BR_I2C_S_BUSY(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_BUSY))
-#endif
-//@}
-
-/*!
- * @name Register I2C_S, field IAAS[6] (RW)
- *
- * This bit is set by one of the following conditions: The calling address
- * matches the programmed primary slave address in the A1 register, or matches the
- * range address in the RA register (which must be set to a nonzero value and under
- * the condition I2C_C2[RMEN] = 1). C2[GCAEN] is set and a general call is
- * received. SMB[SIICAEN] is set and the calling address matches the second programmed
- * slave address. ALERTEN is set and an SMBus alert response address is received
- * RMEN is set and an address is received that is within the range between the
- * values of the A1 and RA registers. IAAS sets before the ACK bit. The CPU must
- * check the SRW bit and set TX/RX accordingly. Writing the C1 register with any
- * value clears this bit.
- *
- * Values:
- * - 0 - Not addressed
- * - 1 - Addressed as a slave
- */
-//@{
-#define BP_I2C_S_IAAS (6U) //!< Bit position for I2C_S_IAAS.
-#define BM_I2C_S_IAAS (0x40U) //!< Bit mask for I2C_S_IAAS.
-#define BS_I2C_S_IAAS (1U) //!< Bit field size in bits for I2C_S_IAAS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_S_IAAS field.
-#define BR_I2C_S_IAAS(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IAAS))
-#endif
-
-//! @brief Format value for bitfield I2C_S_IAAS.
-#define BF_I2C_S_IAAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_S_IAAS), uint8_t) & BM_I2C_S_IAAS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IAAS field to a new value.
-#define BW_I2C_S_IAAS(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IAAS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2C_S, field TCF[7] (RO)
- *
- * Acknowledges a byte transfer; TCF sets on the completion of a byte transfer.
- * This bit is valid only during or immediately following a transfer to or from
- * the I2C module. TCF is cleared by reading the I2C data register in receive mode
- * or by writing to the I2C data register in transmit mode.
- *
- * Values:
- * - 0 - Transfer in progress
- * - 1 - Transfer complete
- */
-//@{
-#define BP_I2C_S_TCF (7U) //!< Bit position for I2C_S_TCF.
-#define BM_I2C_S_TCF (0x80U) //!< Bit mask for I2C_S_TCF.
-#define BS_I2C_S_TCF (1U) //!< Bit field size in bits for I2C_S_TCF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_S_TCF field.
-#define BR_I2C_S_TCF(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_TCF))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2C_D - I2C Data I/O register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2C_D - I2C Data I/O register (RW)
- *
- * Reset value: 0x00U
- */
-typedef union _hw_i2c_d
-{
- uint8_t U;
- struct _hw_i2c_d_bitfields
- {
- uint8_t DATA : 8; //!< [7:0] Data
- } B;
-} hw_i2c_d_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2C_D register
- */
-//@{
-#define HW_I2C_D_ADDR(x) (REGS_I2C_BASE(x) + 0x4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2C_D(x) (*(__IO hw_i2c_d_t *) HW_I2C_D_ADDR(x))
-#define HW_I2C_D_RD(x) (HW_I2C_D(x).U)
-#define HW_I2C_D_WR(x, v) (HW_I2C_D(x).U = (v))
-#define HW_I2C_D_SET(x, v) (HW_I2C_D_WR(x, HW_I2C_D_RD(x) | (v)))
-#define HW_I2C_D_CLR(x, v) (HW_I2C_D_WR(x, HW_I2C_D_RD(x) & ~(v)))
-#define HW_I2C_D_TOG(x, v) (HW_I2C_D_WR(x, HW_I2C_D_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2C_D bitfields
- */
-
-/*!
- * @name Register I2C_D, field DATA[7:0] (RW)
- *
- * In master transmit mode, when data is written to this register, a data
- * transfer is initiated. The most significant bit is sent first. In master receive
- * mode, reading this register initiates receiving of the next byte of data. When
- * making the transition out of master receive mode, switch the I2C mode before
- * reading the Data register to prevent an inadvertent initiation of a master
- * receive data transfer. In slave mode, the same functions are available after an
- * address match occurs. The C1[TX] bit must correctly reflect the desired direction
- * of transfer in master and slave modes for the transmission to begin. For
- * example, if the I2C module is configured for master transmit but a master receive
- * is desired, reading the Data register does not initiate the receive. Reading
- * the Data register returns the last byte received while the I2C module is
- * configured in master receive or slave receive mode. The Data register does not
- * reflect every byte that is transmitted on the I2C bus, and neither can software
- * verify that a byte has been written to the Data register correctly by reading it
- * back. In master transmit mode, the first byte of data written to the Data
- * register following assertion of MST (start bit) or assertion of RSTA (repeated
- * start bit) is used for the address transfer and must consist of the calling
- * address (in bits 7-1) concatenated with the required R/W bit (in position bit 0).
- */
-//@{
-#define BP_I2C_D_DATA (0U) //!< Bit position for I2C_D_DATA.
-#define BM_I2C_D_DATA (0xFFU) //!< Bit mask for I2C_D_DATA.
-#define BS_I2C_D_DATA (8U) //!< Bit field size in bits for I2C_D_DATA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_D_DATA field.
-#define BR_I2C_D_DATA(x) (HW_I2C_D(x).U)
-#endif
-
-//! @brief Format value for bitfield I2C_D_DATA.
-#define BF_I2C_D_DATA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_D_DATA), uint8_t) & BM_I2C_D_DATA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DATA field to a new value.
-#define BW_I2C_D_DATA(x, v) (HW_I2C_D_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2C_C2 - I2C Control Register 2
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2C_C2 - I2C Control Register 2 (RW)
- *
- * Reset value: 0x00U
- */
-typedef union _hw_i2c_c2
-{
- uint8_t U;
- struct _hw_i2c_c2_bitfields
- {
- uint8_t AD : 3; //!< [2:0] Slave Address
- uint8_t RMEN : 1; //!< [3] Range Address Matching Enable
- uint8_t SBRC : 1; //!< [4] Slave Baud Rate Control
- uint8_t HDRS : 1; //!< [5] High Drive Select
- uint8_t ADEXT : 1; //!< [6] Address Extension
- uint8_t GCAEN : 1; //!< [7] General Call Address Enable
- } B;
-} hw_i2c_c2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2C_C2 register
- */
-//@{
-#define HW_I2C_C2_ADDR(x) (REGS_I2C_BASE(x) + 0x5U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2C_C2(x) (*(__IO hw_i2c_c2_t *) HW_I2C_C2_ADDR(x))
-#define HW_I2C_C2_RD(x) (HW_I2C_C2(x).U)
-#define HW_I2C_C2_WR(x, v) (HW_I2C_C2(x).U = (v))
-#define HW_I2C_C2_SET(x, v) (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) | (v)))
-#define HW_I2C_C2_CLR(x, v) (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) & ~(v)))
-#define HW_I2C_C2_TOG(x, v) (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2C_C2 bitfields
- */
-
-/*!
- * @name Register I2C_C2, field AD[2:0] (RW)
- *
- * Contains the upper three bits of the slave address in the 10-bit address
- * scheme. This field is valid only while the ADEXT bit is set.
- */
-//@{
-#define BP_I2C_C2_AD (0U) //!< Bit position for I2C_C2_AD.
-#define BM_I2C_C2_AD (0x07U) //!< Bit mask for I2C_C2_AD.
-#define BS_I2C_C2_AD (3U) //!< Bit field size in bits for I2C_C2_AD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_C2_AD field.
-#define BR_I2C_C2_AD(x) (HW_I2C_C2(x).B.AD)
-#endif
-
-//! @brief Format value for bitfield I2C_C2_AD.
-#define BF_I2C_C2_AD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_AD), uint8_t) & BM_I2C_C2_AD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the AD field to a new value.
-#define BW_I2C_C2_AD(x, v) (HW_I2C_C2_WR(x, (HW_I2C_C2_RD(x) & ~BM_I2C_C2_AD) | BF_I2C_C2_AD(v)))
-#endif
-//@}
-
-/*!
- * @name Register I2C_C2, field RMEN[3] (RW)
- *
- * This bit controls the slave address matching for addresses between the values
- * of the A1 and RA registers. When this bit is set, a slave address matching
- * occurs for any address greater than the value of the A1 register and less than
- * or equal to the value of the RA register.
- *
- * Values:
- * - 0 - Range mode disabled. No address matching occurs for an address within
- * the range of values of the A1 and RA registers.
- * - 1 - Range mode enabled. Address matching occurs when a slave receives an
- * address within the range of values of the A1 and RA registers.
- */
-//@{
-#define BP_I2C_C2_RMEN (3U) //!< Bit position for I2C_C2_RMEN.
-#define BM_I2C_C2_RMEN (0x08U) //!< Bit mask for I2C_C2_RMEN.
-#define BS_I2C_C2_RMEN (1U) //!< Bit field size in bits for I2C_C2_RMEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_C2_RMEN field.
-#define BR_I2C_C2_RMEN(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_RMEN))
-#endif
-
-//! @brief Format value for bitfield I2C_C2_RMEN.
-#define BF_I2C_C2_RMEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_RMEN), uint8_t) & BM_I2C_C2_RMEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RMEN field to a new value.
-#define BW_I2C_C2_RMEN(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_RMEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2C_C2, field SBRC[4] (RW)
- *
- * Enables independent slave mode baud rate at maximum frequency, which forces
- * clock stretching on SCL in very fast I2C modes. To a slave, an example of a
- * "very fast" mode is when the master transfers at 40 kbit/s but the slave can
- * capture the master's data at only 10 kbit/s.
- *
- * Values:
- * - 0 - The slave baud rate follows the master baud rate and clock stretching
- * may occur
- * - 1 - Slave baud rate is independent of the master baud rate
- */
-//@{
-#define BP_I2C_C2_SBRC (4U) //!< Bit position for I2C_C2_SBRC.
-#define BM_I2C_C2_SBRC (0x10U) //!< Bit mask for I2C_C2_SBRC.
-#define BS_I2C_C2_SBRC (1U) //!< Bit field size in bits for I2C_C2_SBRC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_C2_SBRC field.
-#define BR_I2C_C2_SBRC(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_SBRC))
-#endif
-
-//! @brief Format value for bitfield I2C_C2_SBRC.
-#define BF_I2C_C2_SBRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_SBRC), uint8_t) & BM_I2C_C2_SBRC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SBRC field to a new value.
-#define BW_I2C_C2_SBRC(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_SBRC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2C_C2, field HDRS[5] (RW)
- *
- * Controls the drive capability of the I2C pads.
- *
- * Values:
- * - 0 - Normal drive mode
- * - 1 - High drive mode
- */
-//@{
-#define BP_I2C_C2_HDRS (5U) //!< Bit position for I2C_C2_HDRS.
-#define BM_I2C_C2_HDRS (0x20U) //!< Bit mask for I2C_C2_HDRS.
-#define BS_I2C_C2_HDRS (1U) //!< Bit field size in bits for I2C_C2_HDRS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_C2_HDRS field.
-#define BR_I2C_C2_HDRS(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_HDRS))
-#endif
-
-//! @brief Format value for bitfield I2C_C2_HDRS.
-#define BF_I2C_C2_HDRS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_HDRS), uint8_t) & BM_I2C_C2_HDRS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the HDRS field to a new value.
-#define BW_I2C_C2_HDRS(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_HDRS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2C_C2, field ADEXT[6] (RW)
- *
- * Controls the number of bits used for the slave address.
- *
- * Values:
- * - 0 - 7-bit address scheme
- * - 1 - 10-bit address scheme
- */
-//@{
-#define BP_I2C_C2_ADEXT (6U) //!< Bit position for I2C_C2_ADEXT.
-#define BM_I2C_C2_ADEXT (0x40U) //!< Bit mask for I2C_C2_ADEXT.
-#define BS_I2C_C2_ADEXT (1U) //!< Bit field size in bits for I2C_C2_ADEXT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_C2_ADEXT field.
-#define BR_I2C_C2_ADEXT(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_ADEXT))
-#endif
-
-//! @brief Format value for bitfield I2C_C2_ADEXT.
-#define BF_I2C_C2_ADEXT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_ADEXT), uint8_t) & BM_I2C_C2_ADEXT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ADEXT field to a new value.
-#define BW_I2C_C2_ADEXT(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_ADEXT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2C_C2, field GCAEN[7] (RW)
- *
- * Enables general call address.
- *
- * Values:
- * - 0 - Disabled
- * - 1 - Enabled
- */
-//@{
-#define BP_I2C_C2_GCAEN (7U) //!< Bit position for I2C_C2_GCAEN.
-#define BM_I2C_C2_GCAEN (0x80U) //!< Bit mask for I2C_C2_GCAEN.
-#define BS_I2C_C2_GCAEN (1U) //!< Bit field size in bits for I2C_C2_GCAEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_C2_GCAEN field.
-#define BR_I2C_C2_GCAEN(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_GCAEN))
-#endif
-
-//! @brief Format value for bitfield I2C_C2_GCAEN.
-#define BF_I2C_C2_GCAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_GCAEN), uint8_t) & BM_I2C_C2_GCAEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the GCAEN field to a new value.
-#define BW_I2C_C2_GCAEN(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_GCAEN) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2C_FLT - I2C Programmable Input Glitch Filter register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2C_FLT - I2C Programmable Input Glitch Filter register (RW)
- *
- * Reset value: 0x00U
- */
-typedef union _hw_i2c_flt
-{
- uint8_t U;
- struct _hw_i2c_flt_bitfields
- {
- uint8_t FLT : 4; //!< [3:0] I2C Programmable Filter Factor
- uint8_t STARTF : 1; //!< [4] I2C Bus Start Detect Flag
- uint8_t SSIE : 1; //!< [5] I2C Bus Stop or Start Interrupt Enable
- uint8_t STOPF : 1; //!< [6] I2C Bus Stop Detect Flag
- uint8_t SHEN : 1; //!< [7] Stop Hold Enable
- } B;
-} hw_i2c_flt_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2C_FLT register
- */
-//@{
-#define HW_I2C_FLT_ADDR(x) (REGS_I2C_BASE(x) + 0x6U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2C_FLT(x) (*(__IO hw_i2c_flt_t *) HW_I2C_FLT_ADDR(x))
-#define HW_I2C_FLT_RD(x) (HW_I2C_FLT(x).U)
-#define HW_I2C_FLT_WR(x, v) (HW_I2C_FLT(x).U = (v))
-#define HW_I2C_FLT_SET(x, v) (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) | (v)))
-#define HW_I2C_FLT_CLR(x, v) (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) & ~(v)))
-#define HW_I2C_FLT_TOG(x, v) (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2C_FLT bitfields
- */
-
-/*!
- * @name Register I2C_FLT, field FLT[3:0] (RW)
- *
- * Controls the width of the glitch, in terms of I2C module clock cycles, that
- * the filter must absorb. For any glitch whose size is less than or equal to this
- * width setting, the filter does not allow the glitch to pass.
- *
- * Values:
- * - 0 - No filter/bypass
- */
-//@{
-#define BP_I2C_FLT_FLT (0U) //!< Bit position for I2C_FLT_FLT.
-#define BM_I2C_FLT_FLT (0x0FU) //!< Bit mask for I2C_FLT_FLT.
-#define BS_I2C_FLT_FLT (4U) //!< Bit field size in bits for I2C_FLT_FLT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_FLT_FLT field.
-#define BR_I2C_FLT_FLT(x) (HW_I2C_FLT(x).B.FLT)
-#endif
-
-//! @brief Format value for bitfield I2C_FLT_FLT.
-#define BF_I2C_FLT_FLT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_FLT_FLT), uint8_t) & BM_I2C_FLT_FLT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FLT field to a new value.
-#define BW_I2C_FLT_FLT(x, v) (HW_I2C_FLT_WR(x, (HW_I2C_FLT_RD(x) & ~BM_I2C_FLT_FLT) | BF_I2C_FLT_FLT(v)))
-#endif
-//@}
-
-/*!
- * @name Register I2C_FLT, field STARTF[4] (W1C)
- *
- * Hardware sets this bit when the I2C bus's start status is detected. The
- * STARTF bit must be cleared by writing 1 to it.
- *
- * Values:
- * - 0 - No start happens on I2C bus
- * - 1 - Start detected on I2C bus
- */
-//@{
-#define BP_I2C_FLT_STARTF (4U) //!< Bit position for I2C_FLT_STARTF.
-#define BM_I2C_FLT_STARTF (0x10U) //!< Bit mask for I2C_FLT_STARTF.
-#define BS_I2C_FLT_STARTF (1U) //!< Bit field size in bits for I2C_FLT_STARTF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_FLT_STARTF field.
-#define BR_I2C_FLT_STARTF(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STARTF))
-#endif
-
-//! @brief Format value for bitfield I2C_FLT_STARTF.
-#define BF_I2C_FLT_STARTF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_FLT_STARTF), uint8_t) & BM_I2C_FLT_STARTF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the STARTF field to a new value.
-#define BW_I2C_FLT_STARTF(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STARTF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2C_FLT, field SSIE[5] (RW)
- *
- * This bit enables the interrupt for I2C bus stop or start detection. To clear
- * the I2C bus stop or start detection interrupt: In the interrupt service
- * routine, first clear the STOPF or STARTF bit by writing 1 to it, and then clear the
- * IICIF bit in the status register. If this sequence is reversed, the IICIF bit
- * is asserted again.
- *
- * Values:
- * - 0 - Stop or start detection interrupt is disabled
- * - 1 - Stop or start detection interrupt is enabled
- */
-//@{
-#define BP_I2C_FLT_SSIE (5U) //!< Bit position for I2C_FLT_SSIE.
-#define BM_I2C_FLT_SSIE (0x20U) //!< Bit mask for I2C_FLT_SSIE.
-#define BS_I2C_FLT_SSIE (1U) //!< Bit field size in bits for I2C_FLT_SSIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_FLT_SSIE field.
-#define BR_I2C_FLT_SSIE(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SSIE))
-#endif
-
-//! @brief Format value for bitfield I2C_FLT_SSIE.
-#define BF_I2C_FLT_SSIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_FLT_SSIE), uint8_t) & BM_I2C_FLT_SSIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SSIE field to a new value.
-#define BW_I2C_FLT_SSIE(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SSIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2C_FLT, field STOPF[6] (W1C)
- *
- * Hardware sets this bit when the I2C bus's stop status is detected. The STOPF
- * bit must be cleared by writing 1 to it.
- *
- * Values:
- * - 0 - No stop happens on I2C bus
- * - 1 - Stop detected on I2C bus
- */
-//@{
-#define BP_I2C_FLT_STOPF (6U) //!< Bit position for I2C_FLT_STOPF.
-#define BM_I2C_FLT_STOPF (0x40U) //!< Bit mask for I2C_FLT_STOPF.
-#define BS_I2C_FLT_STOPF (1U) //!< Bit field size in bits for I2C_FLT_STOPF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_FLT_STOPF field.
-#define BR_I2C_FLT_STOPF(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STOPF))
-#endif
-
-//! @brief Format value for bitfield I2C_FLT_STOPF.
-#define BF_I2C_FLT_STOPF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_FLT_STOPF), uint8_t) & BM_I2C_FLT_STOPF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the STOPF field to a new value.
-#define BW_I2C_FLT_STOPF(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STOPF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2C_FLT, field SHEN[7] (RW)
- *
- * Set this bit to hold off entry to stop mode when any data transmission or
- * reception is occurring. The following scenario explains the holdoff
- * functionality: The I2C module is configured for a basic transfer, and the SHEN bit is set
- * to 1. A transfer begins. The MCU signals the I2C module to enter stop mode. The
- * byte currently being transferred, including both address and data, completes
- * its transfer. The I2C slave or master acknowledges that the in-transfer byte
- * completed its transfer and acknowledges the request to enter stop mode. After
- * receiving the I2C module's acknowledgment of the request to enter stop mode,
- * the MCU determines whether to shut off the I2C module's clock. If the SHEN bit
- * is set to 1 and the I2C module is in an idle or disabled state when the MCU
- * signals to enter stop mode, the module immediately acknowledges the request to
- * enter stop mode. If SHEN is cleared to 0 and the overall data transmission or
- * reception that was suspended by stop mode entry was incomplete: To resume the
- * overall transmission or reception after the MCU exits stop mode, software must
- * reinitialize the transfer by resending the address of the slave. If the I2C
- * Control Register 1's IICIE bit was set to 1 before the MCU entered stop mode,
- * system software will receive the interrupt triggered by the I2C Status Register's
- * TCF bit after the MCU wakes from the stop mode.
- *
- * Values:
- * - 0 - Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
- * - 1 - Stop holdoff is enabled.
- */
-//@{
-#define BP_I2C_FLT_SHEN (7U) //!< Bit position for I2C_FLT_SHEN.
-#define BM_I2C_FLT_SHEN (0x80U) //!< Bit mask for I2C_FLT_SHEN.
-#define BS_I2C_FLT_SHEN (1U) //!< Bit field size in bits for I2C_FLT_SHEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_FLT_SHEN field.
-#define BR_I2C_FLT_SHEN(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SHEN))
-#endif
-
-//! @brief Format value for bitfield I2C_FLT_SHEN.
-#define BF_I2C_FLT_SHEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_FLT_SHEN), uint8_t) & BM_I2C_FLT_SHEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SHEN field to a new value.
-#define BW_I2C_FLT_SHEN(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SHEN) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2C_RA - I2C Range Address register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2C_RA - I2C Range Address register (RW)
- *
- * Reset value: 0x00U
- */
-typedef union _hw_i2c_ra
-{
- uint8_t U;
- struct _hw_i2c_ra_bitfields
- {
- uint8_t RESERVED0 : 1; //!< [0]
- uint8_t RAD : 7; //!< [7:1] Range Slave Address
- } B;
-} hw_i2c_ra_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2C_RA register
- */
-//@{
-#define HW_I2C_RA_ADDR(x) (REGS_I2C_BASE(x) + 0x7U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2C_RA(x) (*(__IO hw_i2c_ra_t *) HW_I2C_RA_ADDR(x))
-#define HW_I2C_RA_RD(x) (HW_I2C_RA(x).U)
-#define HW_I2C_RA_WR(x, v) (HW_I2C_RA(x).U = (v))
-#define HW_I2C_RA_SET(x, v) (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) | (v)))
-#define HW_I2C_RA_CLR(x, v) (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) & ~(v)))
-#define HW_I2C_RA_TOG(x, v) (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2C_RA bitfields
- */
-
-/*!
- * @name Register I2C_RA, field RAD[7:1] (RW)
- *
- * This field contains the slave address to be used by the I2C module. The field
- * is used in the 7-bit address scheme. If I2C_C2[RMEN] is set to 1, any nonzero
- * value write enables this register. This register value can be considered as a
- * maximum boundary in the range matching mode.
- */
-//@{
-#define BP_I2C_RA_RAD (1U) //!< Bit position for I2C_RA_RAD.
-#define BM_I2C_RA_RAD (0xFEU) //!< Bit mask for I2C_RA_RAD.
-#define BS_I2C_RA_RAD (7U) //!< Bit field size in bits for I2C_RA_RAD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_RA_RAD field.
-#define BR_I2C_RA_RAD(x) (HW_I2C_RA(x).B.RAD)
-#endif
-
-//! @brief Format value for bitfield I2C_RA_RAD.
-#define BF_I2C_RA_RAD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_RA_RAD), uint8_t) & BM_I2C_RA_RAD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RAD field to a new value.
-#define BW_I2C_RA_RAD(x, v) (HW_I2C_RA_WR(x, (HW_I2C_RA_RD(x) & ~BM_I2C_RA_RAD) | BF_I2C_RA_RAD(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2C_SMB - I2C SMBus Control and Status register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2C_SMB - I2C SMBus Control and Status register (RW)
- *
- * Reset value: 0x00U
- *
- * When the SCL and SDA signals are held high for a length of time greater than
- * the high timeout period, the SHTF1 flag sets. Before reaching this threshold,
- * while the system is detecting how long these signals are being held high, a
- * master assumes that the bus is free. However, the SHTF1 bit is set to 1 in the
- * bus transmission process with the idle bus state. When the TCKSEL bit is set,
- * there is no need to monitor the SHTF1 bit because the bus speed is too high to
- * match the protocol of SMBus.
- */
-typedef union _hw_i2c_smb
-{
- uint8_t U;
- struct _hw_i2c_smb_bitfields
- {
- uint8_t SHTF2IE : 1; //!< [0] SHTF2 Interrupt Enable
- uint8_t SHTF2 : 1; //!< [1] SCL High Timeout Flag 2
- uint8_t SHTF1 : 1; //!< [2] SCL High Timeout Flag 1
- uint8_t SLTF : 1; //!< [3] SCL Low Timeout Flag
- uint8_t TCKSEL : 1; //!< [4] Timeout Counter Clock Select
- uint8_t SIICAEN : 1; //!< [5] Second I2C Address Enable
- uint8_t ALERTEN : 1; //!< [6] SMBus Alert Response Address Enable
- uint8_t FACK : 1; //!< [7] Fast NACK/ACK Enable
- } B;
-} hw_i2c_smb_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2C_SMB register
- */
-//@{
-#define HW_I2C_SMB_ADDR(x) (REGS_I2C_BASE(x) + 0x8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2C_SMB(x) (*(__IO hw_i2c_smb_t *) HW_I2C_SMB_ADDR(x))
-#define HW_I2C_SMB_RD(x) (HW_I2C_SMB(x).U)
-#define HW_I2C_SMB_WR(x, v) (HW_I2C_SMB(x).U = (v))
-#define HW_I2C_SMB_SET(x, v) (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) | (v)))
-#define HW_I2C_SMB_CLR(x, v) (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) & ~(v)))
-#define HW_I2C_SMB_TOG(x, v) (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2C_SMB bitfields
- */
-
-/*!
- * @name Register I2C_SMB, field SHTF2IE[0] (RW)
- *
- * Enables SCL high and SDA low timeout interrupt.
- *
- * Values:
- * - 0 - SHTF2 interrupt is disabled
- * - 1 - SHTF2 interrupt is enabled
- */
-//@{
-#define BP_I2C_SMB_SHTF2IE (0U) //!< Bit position for I2C_SMB_SHTF2IE.
-#define BM_I2C_SMB_SHTF2IE (0x01U) //!< Bit mask for I2C_SMB_SHTF2IE.
-#define BS_I2C_SMB_SHTF2IE (1U) //!< Bit field size in bits for I2C_SMB_SHTF2IE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_SMB_SHTF2IE field.
-#define BR_I2C_SMB_SHTF2IE(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2IE))
-#endif
-
-//! @brief Format value for bitfield I2C_SMB_SHTF2IE.
-#define BF_I2C_SMB_SHTF2IE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_SHTF2IE), uint8_t) & BM_I2C_SMB_SHTF2IE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SHTF2IE field to a new value.
-#define BW_I2C_SMB_SHTF2IE(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2IE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2C_SMB, field SHTF2[1] (W1C)
- *
- * This bit sets when SCL is held high and SDA is held low more than clock *
- * LoValue / 512. Software clears this bit by writing 1 to it.
- *
- * Values:
- * - 0 - No SCL high and SDA low timeout occurs
- * - 1 - SCL high and SDA low timeout occurs
- */
-//@{
-#define BP_I2C_SMB_SHTF2 (1U) //!< Bit position for I2C_SMB_SHTF2.
-#define BM_I2C_SMB_SHTF2 (0x02U) //!< Bit mask for I2C_SMB_SHTF2.
-#define BS_I2C_SMB_SHTF2 (1U) //!< Bit field size in bits for I2C_SMB_SHTF2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_SMB_SHTF2 field.
-#define BR_I2C_SMB_SHTF2(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2))
-#endif
-
-//! @brief Format value for bitfield I2C_SMB_SHTF2.
-#define BF_I2C_SMB_SHTF2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_SHTF2), uint8_t) & BM_I2C_SMB_SHTF2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SHTF2 field to a new value.
-#define BW_I2C_SMB_SHTF2(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2C_SMB, field SHTF1[2] (RO)
- *
- * This read-only bit sets when SCL and SDA are held high more than clock *
- * LoValue / 512, which indicates the bus is free. This bit is cleared automatically.
- *
- * Values:
- * - 0 - No SCL high and SDA high timeout occurs
- * - 1 - SCL high and SDA high timeout occurs
- */
-//@{
-#define BP_I2C_SMB_SHTF1 (2U) //!< Bit position for I2C_SMB_SHTF1.
-#define BM_I2C_SMB_SHTF1 (0x04U) //!< Bit mask for I2C_SMB_SHTF1.
-#define BS_I2C_SMB_SHTF1 (1U) //!< Bit field size in bits for I2C_SMB_SHTF1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_SMB_SHTF1 field.
-#define BR_I2C_SMB_SHTF1(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF1))
-#endif
-//@}
-
-/*!
- * @name Register I2C_SMB, field SLTF[3] (W1C)
- *
- * This bit is set when the SLT register (consisting of the SLTH and SLTL
- * registers) is loaded with a non-zero value (LoValue) and an SCL low timeout occurs.
- * Software clears this bit by writing a logic 1 to it. The low timeout function
- * is disabled when the SLT register's value is 0.
- *
- * Values:
- * - 0 - No low timeout occurs
- * - 1 - Low timeout occurs
- */
-//@{
-#define BP_I2C_SMB_SLTF (3U) //!< Bit position for I2C_SMB_SLTF.
-#define BM_I2C_SMB_SLTF (0x08U) //!< Bit mask for I2C_SMB_SLTF.
-#define BS_I2C_SMB_SLTF (1U) //!< Bit field size in bits for I2C_SMB_SLTF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_SMB_SLTF field.
-#define BR_I2C_SMB_SLTF(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SLTF))
-#endif
-
-//! @brief Format value for bitfield I2C_SMB_SLTF.
-#define BF_I2C_SMB_SLTF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_SLTF), uint8_t) & BM_I2C_SMB_SLTF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SLTF field to a new value.
-#define BW_I2C_SMB_SLTF(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SLTF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2C_SMB, field TCKSEL[4] (RW)
- *
- * Selects the clock source of the timeout counter.
- *
- * Values:
- * - 0 - Timeout counter counts at the frequency of the I2C module clock / 64
- * - 1 - Timeout counter counts at the frequency of the I2C module clock
- */
-//@{
-#define BP_I2C_SMB_TCKSEL (4U) //!< Bit position for I2C_SMB_TCKSEL.
-#define BM_I2C_SMB_TCKSEL (0x10U) //!< Bit mask for I2C_SMB_TCKSEL.
-#define BS_I2C_SMB_TCKSEL (1U) //!< Bit field size in bits for I2C_SMB_TCKSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_SMB_TCKSEL field.
-#define BR_I2C_SMB_TCKSEL(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_TCKSEL))
-#endif
-
-//! @brief Format value for bitfield I2C_SMB_TCKSEL.
-#define BF_I2C_SMB_TCKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_TCKSEL), uint8_t) & BM_I2C_SMB_TCKSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TCKSEL field to a new value.
-#define BW_I2C_SMB_TCKSEL(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_TCKSEL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2C_SMB, field SIICAEN[5] (RW)
- *
- * Enables or disables SMBus device default address.
- *
- * Values:
- * - 0 - I2C address register 2 matching is disabled
- * - 1 - I2C address register 2 matching is enabled
- */
-//@{
-#define BP_I2C_SMB_SIICAEN (5U) //!< Bit position for I2C_SMB_SIICAEN.
-#define BM_I2C_SMB_SIICAEN (0x20U) //!< Bit mask for I2C_SMB_SIICAEN.
-#define BS_I2C_SMB_SIICAEN (1U) //!< Bit field size in bits for I2C_SMB_SIICAEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_SMB_SIICAEN field.
-#define BR_I2C_SMB_SIICAEN(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SIICAEN))
-#endif
-
-//! @brief Format value for bitfield I2C_SMB_SIICAEN.
-#define BF_I2C_SMB_SIICAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_SIICAEN), uint8_t) & BM_I2C_SMB_SIICAEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SIICAEN field to a new value.
-#define BW_I2C_SMB_SIICAEN(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SIICAEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2C_SMB, field ALERTEN[6] (RW)
- *
- * Enables or disables SMBus alert response address matching. After the host
- * responds to a device that used the alert response address, you must use software
- * to put the device's address on the bus. The alert protocol is described in the
- * SMBus specification.
- *
- * Values:
- * - 0 - SMBus alert response address matching is disabled
- * - 1 - SMBus alert response address matching is enabled
- */
-//@{
-#define BP_I2C_SMB_ALERTEN (6U) //!< Bit position for I2C_SMB_ALERTEN.
-#define BM_I2C_SMB_ALERTEN (0x40U) //!< Bit mask for I2C_SMB_ALERTEN.
-#define BS_I2C_SMB_ALERTEN (1U) //!< Bit field size in bits for I2C_SMB_ALERTEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_SMB_ALERTEN field.
-#define BR_I2C_SMB_ALERTEN(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_ALERTEN))
-#endif
-
-//! @brief Format value for bitfield I2C_SMB_ALERTEN.
-#define BF_I2C_SMB_ALERTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_ALERTEN), uint8_t) & BM_I2C_SMB_ALERTEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ALERTEN field to a new value.
-#define BW_I2C_SMB_ALERTEN(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_ALERTEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2C_SMB, field FACK[7] (RW)
- *
- * For SMBus packet error checking, the CPU must be able to issue an ACK or NACK
- * according to the result of receiving data byte.
- *
- * Values:
- * - 0 - An ACK or NACK is sent on the following receiving data byte
- * - 1 - Writing 0 to TXAK after receiving a data byte generates an ACK. Writing
- * 1 to TXAK after receiving a data byte generates a NACK.
- */
-//@{
-#define BP_I2C_SMB_FACK (7U) //!< Bit position for I2C_SMB_FACK.
-#define BM_I2C_SMB_FACK (0x80U) //!< Bit mask for I2C_SMB_FACK.
-#define BS_I2C_SMB_FACK (1U) //!< Bit field size in bits for I2C_SMB_FACK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_SMB_FACK field.
-#define BR_I2C_SMB_FACK(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_FACK))
-#endif
-
-//! @brief Format value for bitfield I2C_SMB_FACK.
-#define BF_I2C_SMB_FACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_FACK), uint8_t) & BM_I2C_SMB_FACK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FACK field to a new value.
-#define BW_I2C_SMB_FACK(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_FACK) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2C_A2 - I2C Address Register 2
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2C_A2 - I2C Address Register 2 (RW)
- *
- * Reset value: 0xC2U
- */
-typedef union _hw_i2c_a2
-{
- uint8_t U;
- struct _hw_i2c_a2_bitfields
- {
- uint8_t RESERVED0 : 1; //!< [0]
- uint8_t SAD : 7; //!< [7:1] SMBus Address
- } B;
-} hw_i2c_a2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2C_A2 register
- */
-//@{
-#define HW_I2C_A2_ADDR(x) (REGS_I2C_BASE(x) + 0x9U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2C_A2(x) (*(__IO hw_i2c_a2_t *) HW_I2C_A2_ADDR(x))
-#define HW_I2C_A2_RD(x) (HW_I2C_A2(x).U)
-#define HW_I2C_A2_WR(x, v) (HW_I2C_A2(x).U = (v))
-#define HW_I2C_A2_SET(x, v) (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) | (v)))
-#define HW_I2C_A2_CLR(x, v) (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) & ~(v)))
-#define HW_I2C_A2_TOG(x, v) (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2C_A2 bitfields
- */
-
-/*!
- * @name Register I2C_A2, field SAD[7:1] (RW)
- *
- * Contains the slave address used by the SMBus. This field is used on the
- * device default address or other related addresses.
- */
-//@{
-#define BP_I2C_A2_SAD (1U) //!< Bit position for I2C_A2_SAD.
-#define BM_I2C_A2_SAD (0xFEU) //!< Bit mask for I2C_A2_SAD.
-#define BS_I2C_A2_SAD (7U) //!< Bit field size in bits for I2C_A2_SAD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_A2_SAD field.
-#define BR_I2C_A2_SAD(x) (HW_I2C_A2(x).B.SAD)
-#endif
-
-//! @brief Format value for bitfield I2C_A2_SAD.
-#define BF_I2C_A2_SAD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_A2_SAD), uint8_t) & BM_I2C_A2_SAD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SAD field to a new value.
-#define BW_I2C_A2_SAD(x, v) (HW_I2C_A2_WR(x, (HW_I2C_A2_RD(x) & ~BM_I2C_A2_SAD) | BF_I2C_A2_SAD(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2C_SLTH - I2C SCL Low Timeout Register High
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2C_SLTH - I2C SCL Low Timeout Register High (RW)
- *
- * Reset value: 0x00U
- */
-typedef union _hw_i2c_slth
-{
- uint8_t U;
- struct _hw_i2c_slth_bitfields
- {
- uint8_t SSLT : 8; //!< [7:0]
- } B;
-} hw_i2c_slth_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2C_SLTH register
- */
-//@{
-#define HW_I2C_SLTH_ADDR(x) (REGS_I2C_BASE(x) + 0xAU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2C_SLTH(x) (*(__IO hw_i2c_slth_t *) HW_I2C_SLTH_ADDR(x))
-#define HW_I2C_SLTH_RD(x) (HW_I2C_SLTH(x).U)
-#define HW_I2C_SLTH_WR(x, v) (HW_I2C_SLTH(x).U = (v))
-#define HW_I2C_SLTH_SET(x, v) (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) | (v)))
-#define HW_I2C_SLTH_CLR(x, v) (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) & ~(v)))
-#define HW_I2C_SLTH_TOG(x, v) (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2C_SLTH bitfields
- */
-
-/*!
- * @name Register I2C_SLTH, field SSLT[7:0] (RW)
- *
- * Most significant byte of SCL low timeout value that determines the timeout
- * period of SCL low.
- */
-//@{
-#define BP_I2C_SLTH_SSLT (0U) //!< Bit position for I2C_SLTH_SSLT.
-#define BM_I2C_SLTH_SSLT (0xFFU) //!< Bit mask for I2C_SLTH_SSLT.
-#define BS_I2C_SLTH_SSLT (8U) //!< Bit field size in bits for I2C_SLTH_SSLT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_SLTH_SSLT field.
-#define BR_I2C_SLTH_SSLT(x) (HW_I2C_SLTH(x).U)
-#endif
-
-//! @brief Format value for bitfield I2C_SLTH_SSLT.
-#define BF_I2C_SLTH_SSLT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SLTH_SSLT), uint8_t) & BM_I2C_SLTH_SSLT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SSLT field to a new value.
-#define BW_I2C_SLTH_SSLT(x, v) (HW_I2C_SLTH_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2C_SLTL - I2C SCL Low Timeout Register Low
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2C_SLTL - I2C SCL Low Timeout Register Low (RW)
- *
- * Reset value: 0x00U
- */
-typedef union _hw_i2c_sltl
-{
- uint8_t U;
- struct _hw_i2c_sltl_bitfields
- {
- uint8_t SSLT : 8; //!< [7:0]
- } B;
-} hw_i2c_sltl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2C_SLTL register
- */
-//@{
-#define HW_I2C_SLTL_ADDR(x) (REGS_I2C_BASE(x) + 0xBU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2C_SLTL(x) (*(__IO hw_i2c_sltl_t *) HW_I2C_SLTL_ADDR(x))
-#define HW_I2C_SLTL_RD(x) (HW_I2C_SLTL(x).U)
-#define HW_I2C_SLTL_WR(x, v) (HW_I2C_SLTL(x).U = (v))
-#define HW_I2C_SLTL_SET(x, v) (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) | (v)))
-#define HW_I2C_SLTL_CLR(x, v) (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) & ~(v)))
-#define HW_I2C_SLTL_TOG(x, v) (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2C_SLTL bitfields
- */
-
-/*!
- * @name Register I2C_SLTL, field SSLT[7:0] (RW)
- *
- * Least significant byte of SCL low timeout value that determines the timeout
- * period of SCL low.
- */
-//@{
-#define BP_I2C_SLTL_SSLT (0U) //!< Bit position for I2C_SLTL_SSLT.
-#define BM_I2C_SLTL_SSLT (0xFFU) //!< Bit mask for I2C_SLTL_SSLT.
-#define BS_I2C_SLTL_SSLT (8U) //!< Bit field size in bits for I2C_SLTL_SSLT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2C_SLTL_SSLT field.
-#define BR_I2C_SLTL_SSLT(x) (HW_I2C_SLTL(x).U)
-#endif
-
-//! @brief Format value for bitfield I2C_SLTL_SSLT.
-#define BF_I2C_SLTL_SSLT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SLTL_SSLT), uint8_t) & BM_I2C_SLTL_SSLT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SSLT field to a new value.
-#define BW_I2C_SLTL_SSLT(x, v) (HW_I2C_SLTL_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_i2c_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All I2C module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_i2c
-{
- __IO hw_i2c_a1_t A1; //!< [0x0] I2C Address Register 1
- __IO hw_i2c_f_t F; //!< [0x1] I2C Frequency Divider register
- __IO hw_i2c_c1_t C1; //!< [0x2] I2C Control Register 1
- __IO hw_i2c_s_t S; //!< [0x3] I2C Status register
- __IO hw_i2c_d_t D; //!< [0x4] I2C Data I/O register
- __IO hw_i2c_c2_t C2; //!< [0x5] I2C Control Register 2
- __IO hw_i2c_flt_t FLT; //!< [0x6] I2C Programmable Input Glitch Filter register
- __IO hw_i2c_ra_t RA; //!< [0x7] I2C Range Address register
- __IO hw_i2c_smb_t SMB; //!< [0x8] I2C SMBus Control and Status register
- __IO hw_i2c_a2_t A2; //!< [0x9] I2C Address Register 2
- __IO hw_i2c_slth_t SLTH; //!< [0xA] I2C SCL Low Timeout Register High
- __IO hw_i2c_sltl_t SLTL; //!< [0xB] I2C SCL Low Timeout Register Low
-} hw_i2c_t;
-#pragma pack()
-
-//! @brief Macro to access all I2C registers.
-//! @param x I2C instance number.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_I2C(0)</code>.
-#define HW_I2C(x) (*(hw_i2c_t *) REGS_I2C_BASE(x))
-#endif
-
-#endif // __HW_I2C_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_i2s.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,3463 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_I2S_REGISTERS_H__
-#define __HW_I2S_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 I2S
- *
- * Inter-IC Sound / Synchronous Audio Interface
- *
- * Registers defined in this header file:
- * - HW_I2S_TCSR - SAI Transmit Control Register
- * - HW_I2S_TCR1 - SAI Transmit Configuration 1 Register
- * - HW_I2S_TCR2 - SAI Transmit Configuration 2 Register
- * - HW_I2S_TCR3 - SAI Transmit Configuration 3 Register
- * - HW_I2S_TCR4 - SAI Transmit Configuration 4 Register
- * - HW_I2S_TCR5 - SAI Transmit Configuration 5 Register
- * - HW_I2S_TDRn - SAI Transmit Data Register
- * - HW_I2S_TFRn - SAI Transmit FIFO Register
- * - HW_I2S_TMR - SAI Transmit Mask Register
- * - HW_I2S_RCSR - SAI Receive Control Register
- * - HW_I2S_RCR1 - SAI Receive Configuration 1 Register
- * - HW_I2S_RCR2 - SAI Receive Configuration 2 Register
- * - HW_I2S_RCR3 - SAI Receive Configuration 3 Register
- * - HW_I2S_RCR4 - SAI Receive Configuration 4 Register
- * - HW_I2S_RCR5 - SAI Receive Configuration 5 Register
- * - HW_I2S_RDRn - SAI Receive Data Register
- * - HW_I2S_RFRn - SAI Receive FIFO Register
- * - HW_I2S_RMR - SAI Receive Mask Register
- * - HW_I2S_MCR - SAI MCLK Control Register
- * - HW_I2S_MDR - SAI MCLK Divide Register
- *
- * - hw_i2s_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_I2S_BASE
-#define HW_I2S_INSTANCE_COUNT (1U) //!< Number of instances of the I2S module.
-#define HW_I2S0 (0U) //!< Instance number for I2S0.
-#define REGS_I2S0_BASE (0x4002F000U) //!< Base address for I2S0.
-
-//! @brief Table of base addresses for I2S instances.
-static const uint32_t __g_regs_I2S_base_addresses[] = {
- REGS_I2S0_BASE,
- };
-
-//! @brief Get the base address of I2S by instance number.
-//! @param x I2S instance number, from 0 through 0.
-#define REGS_I2S_BASE(x) (__g_regs_I2S_base_addresses[(x)])
-
-//! @brief Get the instance number given a base address.
-//! @param b Base address for an instance of I2S.
-#define REGS_I2S_INSTANCE(b) ((b) == REGS_I2S0_BASE ? HW_I2S0 : 0)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2S_TCSR - SAI Transmit Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2S_TCSR - SAI Transmit Control Register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_i2s_tcsr
-{
- uint32_t U;
- struct _hw_i2s_tcsr_bitfields
- {
- uint32_t FRDE : 1; //!< [0] FIFO Request DMA Enable
- uint32_t FWDE : 1; //!< [1] FIFO Warning DMA Enable
- uint32_t RESERVED0 : 6; //!< [7:2]
- uint32_t FRIE : 1; //!< [8] FIFO Request Interrupt Enable
- uint32_t FWIE : 1; //!< [9] FIFO Warning Interrupt Enable
- uint32_t FEIE : 1; //!< [10] FIFO Error Interrupt Enable
- uint32_t SEIE : 1; //!< [11] Sync Error Interrupt Enable
- uint32_t WSIE : 1; //!< [12] Word Start Interrupt Enable
- uint32_t RESERVED1 : 3; //!< [15:13]
- uint32_t FRF : 1; //!< [16] FIFO Request Flag
- uint32_t FWF : 1; //!< [17] FIFO Warning Flag
- uint32_t FEF : 1; //!< [18] FIFO Error Flag
- uint32_t SEF : 1; //!< [19] Sync Error Flag
- uint32_t WSF : 1; //!< [20] Word Start Flag
- uint32_t RESERVED2 : 3; //!< [23:21]
- uint32_t SR : 1; //!< [24] Software Reset
- uint32_t FR : 1; //!< [25] FIFO Reset
- uint32_t RESERVED3 : 2; //!< [27:26]
- uint32_t BCE : 1; //!< [28] Bit Clock Enable
- uint32_t DBGE : 1; //!< [29] Debug Enable
- uint32_t STOPE : 1; //!< [30] Stop Enable
- uint32_t TE : 1; //!< [31] Transmitter Enable
- } B;
-} hw_i2s_tcsr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2S_TCSR register
- */
-//@{
-#define HW_I2S_TCSR_ADDR(x) (REGS_I2S_BASE(x) + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2S_TCSR(x) (*(__IO hw_i2s_tcsr_t *) HW_I2S_TCSR_ADDR(x))
-#define HW_I2S_TCSR_RD(x) (HW_I2S_TCSR(x).U)
-#define HW_I2S_TCSR_WR(x, v) (HW_I2S_TCSR(x).U = (v))
-#define HW_I2S_TCSR_SET(x, v) (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) | (v)))
-#define HW_I2S_TCSR_CLR(x, v) (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) & ~(v)))
-#define HW_I2S_TCSR_TOG(x, v) (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2S_TCSR bitfields
- */
-
-/*!
- * @name Register I2S_TCSR, field FRDE[0] (RW)
- *
- * Enables/disables DMA requests.
- *
- * Values:
- * - 0 - Disables the DMA request.
- * - 1 - Enables the DMA request.
- */
-//@{
-#define BP_I2S_TCSR_FRDE (0U) //!< Bit position for I2S_TCSR_FRDE.
-#define BM_I2S_TCSR_FRDE (0x00000001U) //!< Bit mask for I2S_TCSR_FRDE.
-#define BS_I2S_TCSR_FRDE (1U) //!< Bit field size in bits for I2S_TCSR_FRDE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCSR_FRDE field.
-#define BR_I2S_TCSR_FRDE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRDE))
-#endif
-
-//! @brief Format value for bitfield I2S_TCSR_FRDE.
-#define BF_I2S_TCSR_FRDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FRDE), uint32_t) & BM_I2S_TCSR_FRDE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FRDE field to a new value.
-#define BW_I2S_TCSR_FRDE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRDE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCSR, field FWDE[1] (RW)
- *
- * Enables/disables DMA requests.
- *
- * Values:
- * - 0 - Disables the DMA request.
- * - 1 - Enables the DMA request.
- */
-//@{
-#define BP_I2S_TCSR_FWDE (1U) //!< Bit position for I2S_TCSR_FWDE.
-#define BM_I2S_TCSR_FWDE (0x00000002U) //!< Bit mask for I2S_TCSR_FWDE.
-#define BS_I2S_TCSR_FWDE (1U) //!< Bit field size in bits for I2S_TCSR_FWDE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCSR_FWDE field.
-#define BR_I2S_TCSR_FWDE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWDE))
-#endif
-
-//! @brief Format value for bitfield I2S_TCSR_FWDE.
-#define BF_I2S_TCSR_FWDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FWDE), uint32_t) & BM_I2S_TCSR_FWDE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FWDE field to a new value.
-#define BW_I2S_TCSR_FWDE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWDE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCSR, field FRIE[8] (RW)
- *
- * Enables/disables FIFO request interrupts.
- *
- * Values:
- * - 0 - Disables the interrupt.
- * - 1 - Enables the interrupt.
- */
-//@{
-#define BP_I2S_TCSR_FRIE (8U) //!< Bit position for I2S_TCSR_FRIE.
-#define BM_I2S_TCSR_FRIE (0x00000100U) //!< Bit mask for I2S_TCSR_FRIE.
-#define BS_I2S_TCSR_FRIE (1U) //!< Bit field size in bits for I2S_TCSR_FRIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCSR_FRIE field.
-#define BR_I2S_TCSR_FRIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRIE))
-#endif
-
-//! @brief Format value for bitfield I2S_TCSR_FRIE.
-#define BF_I2S_TCSR_FRIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FRIE), uint32_t) & BM_I2S_TCSR_FRIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FRIE field to a new value.
-#define BW_I2S_TCSR_FRIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCSR, field FWIE[9] (RW)
- *
- * Enables/disables FIFO warning interrupts.
- *
- * Values:
- * - 0 - Disables the interrupt.
- * - 1 - Enables the interrupt.
- */
-//@{
-#define BP_I2S_TCSR_FWIE (9U) //!< Bit position for I2S_TCSR_FWIE.
-#define BM_I2S_TCSR_FWIE (0x00000200U) //!< Bit mask for I2S_TCSR_FWIE.
-#define BS_I2S_TCSR_FWIE (1U) //!< Bit field size in bits for I2S_TCSR_FWIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCSR_FWIE field.
-#define BR_I2S_TCSR_FWIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWIE))
-#endif
-
-//! @brief Format value for bitfield I2S_TCSR_FWIE.
-#define BF_I2S_TCSR_FWIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FWIE), uint32_t) & BM_I2S_TCSR_FWIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FWIE field to a new value.
-#define BW_I2S_TCSR_FWIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCSR, field FEIE[10] (RW)
- *
- * Enables/disables FIFO error interrupts.
- *
- * Values:
- * - 0 - Disables the interrupt.
- * - 1 - Enables the interrupt.
- */
-//@{
-#define BP_I2S_TCSR_FEIE (10U) //!< Bit position for I2S_TCSR_FEIE.
-#define BM_I2S_TCSR_FEIE (0x00000400U) //!< Bit mask for I2S_TCSR_FEIE.
-#define BS_I2S_TCSR_FEIE (1U) //!< Bit field size in bits for I2S_TCSR_FEIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCSR_FEIE field.
-#define BR_I2S_TCSR_FEIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEIE))
-#endif
-
-//! @brief Format value for bitfield I2S_TCSR_FEIE.
-#define BF_I2S_TCSR_FEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FEIE), uint32_t) & BM_I2S_TCSR_FEIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FEIE field to a new value.
-#define BW_I2S_TCSR_FEIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCSR, field SEIE[11] (RW)
- *
- * Enables/disables sync error interrupts.
- *
- * Values:
- * - 0 - Disables interrupt.
- * - 1 - Enables interrupt.
- */
-//@{
-#define BP_I2S_TCSR_SEIE (11U) //!< Bit position for I2S_TCSR_SEIE.
-#define BM_I2S_TCSR_SEIE (0x00000800U) //!< Bit mask for I2S_TCSR_SEIE.
-#define BS_I2S_TCSR_SEIE (1U) //!< Bit field size in bits for I2S_TCSR_SEIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCSR_SEIE field.
-#define BR_I2S_TCSR_SEIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEIE))
-#endif
-
-//! @brief Format value for bitfield I2S_TCSR_SEIE.
-#define BF_I2S_TCSR_SEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_SEIE), uint32_t) & BM_I2S_TCSR_SEIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SEIE field to a new value.
-#define BW_I2S_TCSR_SEIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCSR, field WSIE[12] (RW)
- *
- * Enables/disables word start interrupts.
- *
- * Values:
- * - 0 - Disables interrupt.
- * - 1 - Enables interrupt.
- */
-//@{
-#define BP_I2S_TCSR_WSIE (12U) //!< Bit position for I2S_TCSR_WSIE.
-#define BM_I2S_TCSR_WSIE (0x00001000U) //!< Bit mask for I2S_TCSR_WSIE.
-#define BS_I2S_TCSR_WSIE (1U) //!< Bit field size in bits for I2S_TCSR_WSIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCSR_WSIE field.
-#define BR_I2S_TCSR_WSIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSIE))
-#endif
-
-//! @brief Format value for bitfield I2S_TCSR_WSIE.
-#define BF_I2S_TCSR_WSIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_WSIE), uint32_t) & BM_I2S_TCSR_WSIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WSIE field to a new value.
-#define BW_I2S_TCSR_WSIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCSR, field FRF[16] (RO)
- *
- * Indicates that the number of words in an enabled transmit channel FIFO is
- * less than or equal to the transmit FIFO watermark.
- *
- * Values:
- * - 0 - Transmit FIFO watermark has not been reached.
- * - 1 - Transmit FIFO watermark has been reached.
- */
-//@{
-#define BP_I2S_TCSR_FRF (16U) //!< Bit position for I2S_TCSR_FRF.
-#define BM_I2S_TCSR_FRF (0x00010000U) //!< Bit mask for I2S_TCSR_FRF.
-#define BS_I2S_TCSR_FRF (1U) //!< Bit field size in bits for I2S_TCSR_FRF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCSR_FRF field.
-#define BR_I2S_TCSR_FRF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRF))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCSR, field FWF[17] (RO)
- *
- * Indicates that an enabled transmit FIFO is empty.
- *
- * Values:
- * - 0 - No enabled transmit FIFO is empty.
- * - 1 - Enabled transmit FIFO is empty.
- */
-//@{
-#define BP_I2S_TCSR_FWF (17U) //!< Bit position for I2S_TCSR_FWF.
-#define BM_I2S_TCSR_FWF (0x00020000U) //!< Bit mask for I2S_TCSR_FWF.
-#define BS_I2S_TCSR_FWF (1U) //!< Bit field size in bits for I2S_TCSR_FWF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCSR_FWF field.
-#define BR_I2S_TCSR_FWF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWF))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCSR, field FEF[18] (W1C)
- *
- * Indicates that an enabled transmit FIFO has underrun. Write a logic 1 to this
- * field to clear this flag.
- *
- * Values:
- * - 0 - Transmit underrun not detected.
- * - 1 - Transmit underrun detected.
- */
-//@{
-#define BP_I2S_TCSR_FEF (18U) //!< Bit position for I2S_TCSR_FEF.
-#define BM_I2S_TCSR_FEF (0x00040000U) //!< Bit mask for I2S_TCSR_FEF.
-#define BS_I2S_TCSR_FEF (1U) //!< Bit field size in bits for I2S_TCSR_FEF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCSR_FEF field.
-#define BR_I2S_TCSR_FEF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEF))
-#endif
-
-//! @brief Format value for bitfield I2S_TCSR_FEF.
-#define BF_I2S_TCSR_FEF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FEF), uint32_t) & BM_I2S_TCSR_FEF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FEF field to a new value.
-#define BW_I2S_TCSR_FEF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCSR, field SEF[19] (W1C)
- *
- * Indicates that an error in the externally-generated frame sync has been
- * detected. Write a logic 1 to this field to clear this flag.
- *
- * Values:
- * - 0 - Sync error not detected.
- * - 1 - Frame sync error detected.
- */
-//@{
-#define BP_I2S_TCSR_SEF (19U) //!< Bit position for I2S_TCSR_SEF.
-#define BM_I2S_TCSR_SEF (0x00080000U) //!< Bit mask for I2S_TCSR_SEF.
-#define BS_I2S_TCSR_SEF (1U) //!< Bit field size in bits for I2S_TCSR_SEF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCSR_SEF field.
-#define BR_I2S_TCSR_SEF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEF))
-#endif
-
-//! @brief Format value for bitfield I2S_TCSR_SEF.
-#define BF_I2S_TCSR_SEF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_SEF), uint32_t) & BM_I2S_TCSR_SEF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SEF field to a new value.
-#define BW_I2S_TCSR_SEF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCSR, field WSF[20] (W1C)
- *
- * Indicates that the start of the configured word has been detected. Write a
- * logic 1 to this field to clear this flag.
- *
- * Values:
- * - 0 - Start of word not detected.
- * - 1 - Start of word detected.
- */
-//@{
-#define BP_I2S_TCSR_WSF (20U) //!< Bit position for I2S_TCSR_WSF.
-#define BM_I2S_TCSR_WSF (0x00100000U) //!< Bit mask for I2S_TCSR_WSF.
-#define BS_I2S_TCSR_WSF (1U) //!< Bit field size in bits for I2S_TCSR_WSF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCSR_WSF field.
-#define BR_I2S_TCSR_WSF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSF))
-#endif
-
-//! @brief Format value for bitfield I2S_TCSR_WSF.
-#define BF_I2S_TCSR_WSF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_WSF), uint32_t) & BM_I2S_TCSR_WSF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WSF field to a new value.
-#define BW_I2S_TCSR_WSF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCSR, field SR[24] (RW)
- *
- * When set, resets the internal transmitter logic including the FIFO pointers.
- * Software-visible registers are not affected, except for the status registers.
- *
- * Values:
- * - 0 - No effect.
- * - 1 - Software reset.
- */
-//@{
-#define BP_I2S_TCSR_SR (24U) //!< Bit position for I2S_TCSR_SR.
-#define BM_I2S_TCSR_SR (0x01000000U) //!< Bit mask for I2S_TCSR_SR.
-#define BS_I2S_TCSR_SR (1U) //!< Bit field size in bits for I2S_TCSR_SR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCSR_SR field.
-#define BR_I2S_TCSR_SR(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SR))
-#endif
-
-//! @brief Format value for bitfield I2S_TCSR_SR.
-#define BF_I2S_TCSR_SR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_SR), uint32_t) & BM_I2S_TCSR_SR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SR field to a new value.
-#define BW_I2S_TCSR_SR(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCSR, field FR[25] (WORZ)
- *
- * Resets the FIFO pointers. Reading this field will always return zero. FIFO
- * pointers should only be reset when the transmitter is disabled or the FIFO error
- * flag is set.
- *
- * Values:
- * - 0 - No effect.
- * - 1 - FIFO reset.
- */
-//@{
-#define BP_I2S_TCSR_FR (25U) //!< Bit position for I2S_TCSR_FR.
-#define BM_I2S_TCSR_FR (0x02000000U) //!< Bit mask for I2S_TCSR_FR.
-#define BS_I2S_TCSR_FR (1U) //!< Bit field size in bits for I2S_TCSR_FR.
-
-//! @brief Format value for bitfield I2S_TCSR_FR.
-#define BF_I2S_TCSR_FR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FR), uint32_t) & BM_I2S_TCSR_FR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FR field to a new value.
-#define BW_I2S_TCSR_FR(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCSR, field BCE[28] (RW)
- *
- * Enables the transmit bit clock, separately from the TE. This field is
- * automatically set whenever TE is set. When software clears this field, the transmit
- * bit clock remains enabled, and this bit remains set, until the end of the
- * current frame.
- *
- * Values:
- * - 0 - Transmit bit clock is disabled.
- * - 1 - Transmit bit clock is enabled.
- */
-//@{
-#define BP_I2S_TCSR_BCE (28U) //!< Bit position for I2S_TCSR_BCE.
-#define BM_I2S_TCSR_BCE (0x10000000U) //!< Bit mask for I2S_TCSR_BCE.
-#define BS_I2S_TCSR_BCE (1U) //!< Bit field size in bits for I2S_TCSR_BCE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCSR_BCE field.
-#define BR_I2S_TCSR_BCE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_BCE))
-#endif
-
-//! @brief Format value for bitfield I2S_TCSR_BCE.
-#define BF_I2S_TCSR_BCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_BCE), uint32_t) & BM_I2S_TCSR_BCE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BCE field to a new value.
-#define BW_I2S_TCSR_BCE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_BCE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCSR, field DBGE[29] (RW)
- *
- * Enables/disables transmitter operation in Debug mode. The transmit bit clock
- * is not affected by debug mode.
- *
- * Values:
- * - 0 - Transmitter is disabled in Debug mode, after completing the current
- * frame.
- * - 1 - Transmitter is enabled in Debug mode.
- */
-//@{
-#define BP_I2S_TCSR_DBGE (29U) //!< Bit position for I2S_TCSR_DBGE.
-#define BM_I2S_TCSR_DBGE (0x20000000U) //!< Bit mask for I2S_TCSR_DBGE.
-#define BS_I2S_TCSR_DBGE (1U) //!< Bit field size in bits for I2S_TCSR_DBGE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCSR_DBGE field.
-#define BR_I2S_TCSR_DBGE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_DBGE))
-#endif
-
-//! @brief Format value for bitfield I2S_TCSR_DBGE.
-#define BF_I2S_TCSR_DBGE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_DBGE), uint32_t) & BM_I2S_TCSR_DBGE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DBGE field to a new value.
-#define BW_I2S_TCSR_DBGE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_DBGE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCSR, field STOPE[30] (RW)
- *
- * Configures transmitter operation in Stop mode. This field is ignored and the
- * transmitter is disabled in all low-leakage stop modes.
- *
- * Values:
- * - 0 - Transmitter disabled in Stop mode.
- * - 1 - Transmitter enabled in Stop mode.
- */
-//@{
-#define BP_I2S_TCSR_STOPE (30U) //!< Bit position for I2S_TCSR_STOPE.
-#define BM_I2S_TCSR_STOPE (0x40000000U) //!< Bit mask for I2S_TCSR_STOPE.
-#define BS_I2S_TCSR_STOPE (1U) //!< Bit field size in bits for I2S_TCSR_STOPE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCSR_STOPE field.
-#define BR_I2S_TCSR_STOPE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_STOPE))
-#endif
-
-//! @brief Format value for bitfield I2S_TCSR_STOPE.
-#define BF_I2S_TCSR_STOPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_STOPE), uint32_t) & BM_I2S_TCSR_STOPE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the STOPE field to a new value.
-#define BW_I2S_TCSR_STOPE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_STOPE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCSR, field TE[31] (RW)
- *
- * Enables/disables the transmitter. When software clears this field, the
- * transmitter remains enabled, and this bit remains set, until the end of the current
- * frame.
- *
- * Values:
- * - 0 - Transmitter is disabled.
- * - 1 - Transmitter is enabled, or transmitter has been disabled and has not
- * yet reached end of frame.
- */
-//@{
-#define BP_I2S_TCSR_TE (31U) //!< Bit position for I2S_TCSR_TE.
-#define BM_I2S_TCSR_TE (0x80000000U) //!< Bit mask for I2S_TCSR_TE.
-#define BS_I2S_TCSR_TE (1U) //!< Bit field size in bits for I2S_TCSR_TE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCSR_TE field.
-#define BR_I2S_TCSR_TE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_TE))
-#endif
-
-//! @brief Format value for bitfield I2S_TCSR_TE.
-#define BF_I2S_TCSR_TE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_TE), uint32_t) & BM_I2S_TCSR_TE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TE field to a new value.
-#define BW_I2S_TCSR_TE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_TE) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2S_TCR1 - SAI Transmit Configuration 1 Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2S_TCR1 - SAI Transmit Configuration 1 Register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_i2s_tcr1
-{
- uint32_t U;
- struct _hw_i2s_tcr1_bitfields
- {
- uint32_t TFW : 3; //!< [2:0] Transmit FIFO Watermark
- uint32_t RESERVED0 : 29; //!< [31:3]
- } B;
-} hw_i2s_tcr1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2S_TCR1 register
- */
-//@{
-#define HW_I2S_TCR1_ADDR(x) (REGS_I2S_BASE(x) + 0x4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2S_TCR1(x) (*(__IO hw_i2s_tcr1_t *) HW_I2S_TCR1_ADDR(x))
-#define HW_I2S_TCR1_RD(x) (HW_I2S_TCR1(x).U)
-#define HW_I2S_TCR1_WR(x, v) (HW_I2S_TCR1(x).U = (v))
-#define HW_I2S_TCR1_SET(x, v) (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) | (v)))
-#define HW_I2S_TCR1_CLR(x, v) (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) & ~(v)))
-#define HW_I2S_TCR1_TOG(x, v) (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2S_TCR1 bitfields
- */
-
-/*!
- * @name Register I2S_TCR1, field TFW[2:0] (RW)
- *
- * Configures the watermark level for all enabled transmit channels.
- */
-//@{
-#define BP_I2S_TCR1_TFW (0U) //!< Bit position for I2S_TCR1_TFW.
-#define BM_I2S_TCR1_TFW (0x00000007U) //!< Bit mask for I2S_TCR1_TFW.
-#define BS_I2S_TCR1_TFW (3U) //!< Bit field size in bits for I2S_TCR1_TFW.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCR1_TFW field.
-#define BR_I2S_TCR1_TFW(x) (HW_I2S_TCR1(x).B.TFW)
-#endif
-
-//! @brief Format value for bitfield I2S_TCR1_TFW.
-#define BF_I2S_TCR1_TFW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR1_TFW), uint32_t) & BM_I2S_TCR1_TFW)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TFW field to a new value.
-#define BW_I2S_TCR1_TFW(x, v) (HW_I2S_TCR1_WR(x, (HW_I2S_TCR1_RD(x) & ~BM_I2S_TCR1_TFW) | BF_I2S_TCR1_TFW(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2S_TCR2 - SAI Transmit Configuration 2 Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2S_TCR2 - SAI Transmit Configuration 2 Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register must not be altered when TCSR[TE] is set.
- */
-typedef union _hw_i2s_tcr2
-{
- uint32_t U;
- struct _hw_i2s_tcr2_bitfields
- {
- uint32_t DIV : 8; //!< [7:0] Bit Clock Divide
- uint32_t RESERVED0 : 16; //!< [23:8]
- uint32_t BCD : 1; //!< [24] Bit Clock Direction
- uint32_t BCP : 1; //!< [25] Bit Clock Polarity
- uint32_t MSEL : 2; //!< [27:26] MCLK Select
- uint32_t BCI : 1; //!< [28] Bit Clock Input
- uint32_t BCS : 1; //!< [29] Bit Clock Swap
- uint32_t SYNC : 2; //!< [31:30] Synchronous Mode
- } B;
-} hw_i2s_tcr2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2S_TCR2 register
- */
-//@{
-#define HW_I2S_TCR2_ADDR(x) (REGS_I2S_BASE(x) + 0x8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2S_TCR2(x) (*(__IO hw_i2s_tcr2_t *) HW_I2S_TCR2_ADDR(x))
-#define HW_I2S_TCR2_RD(x) (HW_I2S_TCR2(x).U)
-#define HW_I2S_TCR2_WR(x, v) (HW_I2S_TCR2(x).U = (v))
-#define HW_I2S_TCR2_SET(x, v) (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) | (v)))
-#define HW_I2S_TCR2_CLR(x, v) (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) & ~(v)))
-#define HW_I2S_TCR2_TOG(x, v) (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2S_TCR2 bitfields
- */
-
-/*!
- * @name Register I2S_TCR2, field DIV[7:0] (RW)
- *
- * Divides down the audio master clock to generate the bit clock when configured
- * for an internal bit clock. The division value is (DIV + 1) * 2.
- */
-//@{
-#define BP_I2S_TCR2_DIV (0U) //!< Bit position for I2S_TCR2_DIV.
-#define BM_I2S_TCR2_DIV (0x000000FFU) //!< Bit mask for I2S_TCR2_DIV.
-#define BS_I2S_TCR2_DIV (8U) //!< Bit field size in bits for I2S_TCR2_DIV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCR2_DIV field.
-#define BR_I2S_TCR2_DIV(x) (HW_I2S_TCR2(x).B.DIV)
-#endif
-
-//! @brief Format value for bitfield I2S_TCR2_DIV.
-#define BF_I2S_TCR2_DIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_DIV), uint32_t) & BM_I2S_TCR2_DIV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DIV field to a new value.
-#define BW_I2S_TCR2_DIV(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_DIV) | BF_I2S_TCR2_DIV(v)))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCR2, field BCD[24] (RW)
- *
- * Configures the direction of the bit clock.
- *
- * Values:
- * - 0 - Bit clock is generated externally in Slave mode.
- * - 1 - Bit clock is generated internally in Master mode.
- */
-//@{
-#define BP_I2S_TCR2_BCD (24U) //!< Bit position for I2S_TCR2_BCD.
-#define BM_I2S_TCR2_BCD (0x01000000U) //!< Bit mask for I2S_TCR2_BCD.
-#define BS_I2S_TCR2_BCD (1U) //!< Bit field size in bits for I2S_TCR2_BCD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCR2_BCD field.
-#define BR_I2S_TCR2_BCD(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCD))
-#endif
-
-//! @brief Format value for bitfield I2S_TCR2_BCD.
-#define BF_I2S_TCR2_BCD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_BCD), uint32_t) & BM_I2S_TCR2_BCD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BCD field to a new value.
-#define BW_I2S_TCR2_BCD(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCD) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCR2, field BCP[25] (RW)
- *
- * Configures the polarity of the bit clock.
- *
- * Values:
- * - 0 - Bit clock is active high with drive outputs on rising edge and sample
- * inputs on falling edge.
- * - 1 - Bit clock is active low with drive outputs on falling edge and sample
- * inputs on rising edge.
- */
-//@{
-#define BP_I2S_TCR2_BCP (25U) //!< Bit position for I2S_TCR2_BCP.
-#define BM_I2S_TCR2_BCP (0x02000000U) //!< Bit mask for I2S_TCR2_BCP.
-#define BS_I2S_TCR2_BCP (1U) //!< Bit field size in bits for I2S_TCR2_BCP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCR2_BCP field.
-#define BR_I2S_TCR2_BCP(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCP))
-#endif
-
-//! @brief Format value for bitfield I2S_TCR2_BCP.
-#define BF_I2S_TCR2_BCP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_BCP), uint32_t) & BM_I2S_TCR2_BCP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BCP field to a new value.
-#define BW_I2S_TCR2_BCP(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCP) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCR2, field MSEL[27:26] (RW)
- *
- * Selects the audio Master Clock option used to generate an internally
- * generated bit clock. This field has no effect when configured for an externally
- * generated bit clock. Depending on the device, some Master Clock options might not be
- * available. See the chip configuration details for the availability and
- * chip-specific meaning of each option.
- *
- * Values:
- * - 00 - Bus Clock selected.
- * - 01 - Master Clock (MCLK) 1 option selected.
- * - 10 - Master Clock (MCLK) 2 option selected.
- * - 11 - Master Clock (MCLK) 3 option selected.
- */
-//@{
-#define BP_I2S_TCR2_MSEL (26U) //!< Bit position for I2S_TCR2_MSEL.
-#define BM_I2S_TCR2_MSEL (0x0C000000U) //!< Bit mask for I2S_TCR2_MSEL.
-#define BS_I2S_TCR2_MSEL (2U) //!< Bit field size in bits for I2S_TCR2_MSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCR2_MSEL field.
-#define BR_I2S_TCR2_MSEL(x) (HW_I2S_TCR2(x).B.MSEL)
-#endif
-
-//! @brief Format value for bitfield I2S_TCR2_MSEL.
-#define BF_I2S_TCR2_MSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_MSEL), uint32_t) & BM_I2S_TCR2_MSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MSEL field to a new value.
-#define BW_I2S_TCR2_MSEL(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_MSEL) | BF_I2S_TCR2_MSEL(v)))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCR2, field BCI[28] (RW)
- *
- * When this field is set and using an internally generated bit clock in either
- * synchronous or asynchronous mode, the bit clock actually used by the
- * transmitter is delayed by the pad output delay (the transmitter is clocked by the pad
- * input as if the clock was externally generated). This has the effect of
- * decreasing the data input setup time, but increasing the data output valid time. The
- * slave mode timing from the datasheet should be used for the transmitter when
- * this bit is set. In synchronous mode, this bit allows the transmitter to use
- * the slave mode timing from the datasheet, while the receiver uses the master
- * mode timing. This field has no effect when configured for an externally generated
- * bit clock or when synchronous to another SAI peripheral .
- *
- * Values:
- * - 0 - No effect.
- * - 1 - Internal logic is clocked as if bit clock was externally generated.
- */
-//@{
-#define BP_I2S_TCR2_BCI (28U) //!< Bit position for I2S_TCR2_BCI.
-#define BM_I2S_TCR2_BCI (0x10000000U) //!< Bit mask for I2S_TCR2_BCI.
-#define BS_I2S_TCR2_BCI (1U) //!< Bit field size in bits for I2S_TCR2_BCI.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCR2_BCI field.
-#define BR_I2S_TCR2_BCI(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCI))
-#endif
-
-//! @brief Format value for bitfield I2S_TCR2_BCI.
-#define BF_I2S_TCR2_BCI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_BCI), uint32_t) & BM_I2S_TCR2_BCI)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BCI field to a new value.
-#define BW_I2S_TCR2_BCI(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCI) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCR2, field BCS[29] (RW)
- *
- * This field swaps the bit clock used by the transmitter. When the transmitter
- * is configured in asynchronous mode and this bit is set, the transmitter is
- * clocked by the receiver bit clock (SAI_RX_BCLK). This allows the transmitter and
- * receiver to share the same bit clock, but the transmitter continues to use the
- * transmit frame sync (SAI_TX_SYNC). When the transmitter is configured in
- * synchronous mode, the transmitter BCS field and receiver BCS field must be set to
- * the same value. When both are set, the transmitter and receiver are both
- * clocked by the transmitter bit clock (SAI_TX_BCLK) but use the receiver frame sync
- * (SAI_RX_SYNC). This field has no effect when synchronous to another SAI
- * peripheral.
- *
- * Values:
- * - 0 - Use the normal bit clock source.
- * - 1 - Swap the bit clock source.
- */
-//@{
-#define BP_I2S_TCR2_BCS (29U) //!< Bit position for I2S_TCR2_BCS.
-#define BM_I2S_TCR2_BCS (0x20000000U) //!< Bit mask for I2S_TCR2_BCS.
-#define BS_I2S_TCR2_BCS (1U) //!< Bit field size in bits for I2S_TCR2_BCS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCR2_BCS field.
-#define BR_I2S_TCR2_BCS(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCS))
-#endif
-
-//! @brief Format value for bitfield I2S_TCR2_BCS.
-#define BF_I2S_TCR2_BCS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_BCS), uint32_t) & BM_I2S_TCR2_BCS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BCS field to a new value.
-#define BW_I2S_TCR2_BCS(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCR2, field SYNC[31:30] (RW)
- *
- * Configures between asynchronous and synchronous modes of operation. When
- * configured for a synchronous mode of operation, the receiver or other SAI
- * peripheral must be configured for asynchronous operation.
- *
- * Values:
- * - 00 - Asynchronous mode.
- * - 01 - Synchronous with receiver.
- * - 10 - Synchronous with another SAI transmitter.
- * - 11 - Synchronous with another SAI receiver.
- */
-//@{
-#define BP_I2S_TCR2_SYNC (30U) //!< Bit position for I2S_TCR2_SYNC.
-#define BM_I2S_TCR2_SYNC (0xC0000000U) //!< Bit mask for I2S_TCR2_SYNC.
-#define BS_I2S_TCR2_SYNC (2U) //!< Bit field size in bits for I2S_TCR2_SYNC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCR2_SYNC field.
-#define BR_I2S_TCR2_SYNC(x) (HW_I2S_TCR2(x).B.SYNC)
-#endif
-
-//! @brief Format value for bitfield I2S_TCR2_SYNC.
-#define BF_I2S_TCR2_SYNC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_SYNC), uint32_t) & BM_I2S_TCR2_SYNC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SYNC field to a new value.
-#define BW_I2S_TCR2_SYNC(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_SYNC) | BF_I2S_TCR2_SYNC(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2S_TCR3 - SAI Transmit Configuration 3 Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2S_TCR3 - SAI Transmit Configuration 3 Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register must not be altered when TCSR[TE] is set.
- */
-typedef union _hw_i2s_tcr3
-{
- uint32_t U;
- struct _hw_i2s_tcr3_bitfields
- {
- uint32_t WDFL : 5; //!< [4:0] Word Flag Configuration
- uint32_t RESERVED0 : 11; //!< [15:5]
- uint32_t TCE : 2; //!< [17:16] Transmit Channel Enable
- uint32_t RESERVED1 : 14; //!< [31:18]
- } B;
-} hw_i2s_tcr3_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2S_TCR3 register
- */
-//@{
-#define HW_I2S_TCR3_ADDR(x) (REGS_I2S_BASE(x) + 0xCU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2S_TCR3(x) (*(__IO hw_i2s_tcr3_t *) HW_I2S_TCR3_ADDR(x))
-#define HW_I2S_TCR3_RD(x) (HW_I2S_TCR3(x).U)
-#define HW_I2S_TCR3_WR(x, v) (HW_I2S_TCR3(x).U = (v))
-#define HW_I2S_TCR3_SET(x, v) (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) | (v)))
-#define HW_I2S_TCR3_CLR(x, v) (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) & ~(v)))
-#define HW_I2S_TCR3_TOG(x, v) (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2S_TCR3 bitfields
- */
-
-/*!
- * @name Register I2S_TCR3, field WDFL[4:0] (RW)
- *
- * Configures which word sets the start of word flag. The value written must be
- * one less than the word number. For example, writing 0 configures the first
- * word in the frame. When configured to a value greater than TCR4[FRSZ], then the
- * start of word flag is never set.
- */
-//@{
-#define BP_I2S_TCR3_WDFL (0U) //!< Bit position for I2S_TCR3_WDFL.
-#define BM_I2S_TCR3_WDFL (0x0000001FU) //!< Bit mask for I2S_TCR3_WDFL.
-#define BS_I2S_TCR3_WDFL (5U) //!< Bit field size in bits for I2S_TCR3_WDFL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCR3_WDFL field.
-#define BR_I2S_TCR3_WDFL(x) (HW_I2S_TCR3(x).B.WDFL)
-#endif
-
-//! @brief Format value for bitfield I2S_TCR3_WDFL.
-#define BF_I2S_TCR3_WDFL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR3_WDFL), uint32_t) & BM_I2S_TCR3_WDFL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WDFL field to a new value.
-#define BW_I2S_TCR3_WDFL(x, v) (HW_I2S_TCR3_WR(x, (HW_I2S_TCR3_RD(x) & ~BM_I2S_TCR3_WDFL) | BF_I2S_TCR3_WDFL(v)))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCR3, field TCE[17:16] (RW)
- *
- * Enables the corresponding data channel for transmit operation. A channel must
- * be enabled before its FIFO is accessed.
- *
- * Values:
- * - 0 - Transmit data channel N is disabled.
- * - 1 - Transmit data channel N is enabled.
- */
-//@{
-#define BP_I2S_TCR3_TCE (16U) //!< Bit position for I2S_TCR3_TCE.
-#define BM_I2S_TCR3_TCE (0x00030000U) //!< Bit mask for I2S_TCR3_TCE.
-#define BS_I2S_TCR3_TCE (2U) //!< Bit field size in bits for I2S_TCR3_TCE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCR3_TCE field.
-#define BR_I2S_TCR3_TCE(x) (HW_I2S_TCR3(x).B.TCE)
-#endif
-
-//! @brief Format value for bitfield I2S_TCR3_TCE.
-#define BF_I2S_TCR3_TCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR3_TCE), uint32_t) & BM_I2S_TCR3_TCE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TCE field to a new value.
-#define BW_I2S_TCR3_TCE(x, v) (HW_I2S_TCR3_WR(x, (HW_I2S_TCR3_RD(x) & ~BM_I2S_TCR3_TCE) | BF_I2S_TCR3_TCE(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2S_TCR4 - SAI Transmit Configuration 4 Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2S_TCR4 - SAI Transmit Configuration 4 Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register must not be altered when TCSR[TE] is set.
- */
-typedef union _hw_i2s_tcr4
-{
- uint32_t U;
- struct _hw_i2s_tcr4_bitfields
- {
- uint32_t FSD : 1; //!< [0] Frame Sync Direction
- uint32_t FSP : 1; //!< [1] Frame Sync Polarity
- uint32_t RESERVED0 : 1; //!< [2]
- uint32_t FSE : 1; //!< [3] Frame Sync Early
- uint32_t MF : 1; //!< [4] MSB First
- uint32_t RESERVED1 : 3; //!< [7:5]
- uint32_t SYWD : 5; //!< [12:8] Sync Width
- uint32_t RESERVED2 : 3; //!< [15:13]
- uint32_t FRSZ : 5; //!< [20:16] Frame size
- uint32_t RESERVED3 : 11; //!< [31:21]
- } B;
-} hw_i2s_tcr4_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2S_TCR4 register
- */
-//@{
-#define HW_I2S_TCR4_ADDR(x) (REGS_I2S_BASE(x) + 0x10U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2S_TCR4(x) (*(__IO hw_i2s_tcr4_t *) HW_I2S_TCR4_ADDR(x))
-#define HW_I2S_TCR4_RD(x) (HW_I2S_TCR4(x).U)
-#define HW_I2S_TCR4_WR(x, v) (HW_I2S_TCR4(x).U = (v))
-#define HW_I2S_TCR4_SET(x, v) (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) | (v)))
-#define HW_I2S_TCR4_CLR(x, v) (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) & ~(v)))
-#define HW_I2S_TCR4_TOG(x, v) (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2S_TCR4 bitfields
- */
-
-/*!
- * @name Register I2S_TCR4, field FSD[0] (RW)
- *
- * Configures the direction of the frame sync.
- *
- * Values:
- * - 0 - Frame sync is generated externally in Slave mode.
- * - 1 - Frame sync is generated internally in Master mode.
- */
-//@{
-#define BP_I2S_TCR4_FSD (0U) //!< Bit position for I2S_TCR4_FSD.
-#define BM_I2S_TCR4_FSD (0x00000001U) //!< Bit mask for I2S_TCR4_FSD.
-#define BS_I2S_TCR4_FSD (1U) //!< Bit field size in bits for I2S_TCR4_FSD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCR4_FSD field.
-#define BR_I2S_TCR4_FSD(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSD))
-#endif
-
-//! @brief Format value for bitfield I2S_TCR4_FSD.
-#define BF_I2S_TCR4_FSD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_FSD), uint32_t) & BM_I2S_TCR4_FSD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FSD field to a new value.
-#define BW_I2S_TCR4_FSD(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSD) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCR4, field FSP[1] (RW)
- *
- * Configures the polarity of the frame sync.
- *
- * Values:
- * - 0 - Frame sync is active high.
- * - 1 - Frame sync is active low.
- */
-//@{
-#define BP_I2S_TCR4_FSP (1U) //!< Bit position for I2S_TCR4_FSP.
-#define BM_I2S_TCR4_FSP (0x00000002U) //!< Bit mask for I2S_TCR4_FSP.
-#define BS_I2S_TCR4_FSP (1U) //!< Bit field size in bits for I2S_TCR4_FSP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCR4_FSP field.
-#define BR_I2S_TCR4_FSP(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSP))
-#endif
-
-//! @brief Format value for bitfield I2S_TCR4_FSP.
-#define BF_I2S_TCR4_FSP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_FSP), uint32_t) & BM_I2S_TCR4_FSP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FSP field to a new value.
-#define BW_I2S_TCR4_FSP(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSP) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCR4, field FSE[3] (RW)
- *
- * Values:
- * - 0 - Frame sync asserts with the first bit of the frame.
- * - 1 - Frame sync asserts one bit before the first bit of the frame.
- */
-//@{
-#define BP_I2S_TCR4_FSE (3U) //!< Bit position for I2S_TCR4_FSE.
-#define BM_I2S_TCR4_FSE (0x00000008U) //!< Bit mask for I2S_TCR4_FSE.
-#define BS_I2S_TCR4_FSE (1U) //!< Bit field size in bits for I2S_TCR4_FSE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCR4_FSE field.
-#define BR_I2S_TCR4_FSE(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSE))
-#endif
-
-//! @brief Format value for bitfield I2S_TCR4_FSE.
-#define BF_I2S_TCR4_FSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_FSE), uint32_t) & BM_I2S_TCR4_FSE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FSE field to a new value.
-#define BW_I2S_TCR4_FSE(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCR4, field MF[4] (RW)
- *
- * Configures whether the LSB or the MSB is transmitted first.
- *
- * Values:
- * - 0 - LSB is transmitted first.
- * - 1 - MSB is transmitted first.
- */
-//@{
-#define BP_I2S_TCR4_MF (4U) //!< Bit position for I2S_TCR4_MF.
-#define BM_I2S_TCR4_MF (0x00000010U) //!< Bit mask for I2S_TCR4_MF.
-#define BS_I2S_TCR4_MF (1U) //!< Bit field size in bits for I2S_TCR4_MF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCR4_MF field.
-#define BR_I2S_TCR4_MF(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_MF))
-#endif
-
-//! @brief Format value for bitfield I2S_TCR4_MF.
-#define BF_I2S_TCR4_MF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_MF), uint32_t) & BM_I2S_TCR4_MF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MF field to a new value.
-#define BW_I2S_TCR4_MF(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_MF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCR4, field SYWD[12:8] (RW)
- *
- * Configures the length of the frame sync in number of bit clocks. The value
- * written must be one less than the number of bit clocks. For example, write 0 for
- * the frame sync to assert for one bit clock only. The sync width cannot be
- * configured longer than the first word of the frame.
- */
-//@{
-#define BP_I2S_TCR4_SYWD (8U) //!< Bit position for I2S_TCR4_SYWD.
-#define BM_I2S_TCR4_SYWD (0x00001F00U) //!< Bit mask for I2S_TCR4_SYWD.
-#define BS_I2S_TCR4_SYWD (5U) //!< Bit field size in bits for I2S_TCR4_SYWD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCR4_SYWD field.
-#define BR_I2S_TCR4_SYWD(x) (HW_I2S_TCR4(x).B.SYWD)
-#endif
-
-//! @brief Format value for bitfield I2S_TCR4_SYWD.
-#define BF_I2S_TCR4_SYWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_SYWD), uint32_t) & BM_I2S_TCR4_SYWD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SYWD field to a new value.
-#define BW_I2S_TCR4_SYWD(x, v) (HW_I2S_TCR4_WR(x, (HW_I2S_TCR4_RD(x) & ~BM_I2S_TCR4_SYWD) | BF_I2S_TCR4_SYWD(v)))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCR4, field FRSZ[20:16] (RW)
- *
- * Configures the number of words in each frame. The value written must be one
- * less than the number of words in the frame. For example, write 0 for one word
- * per frame. The maximum supported frame size is 32 words.
- */
-//@{
-#define BP_I2S_TCR4_FRSZ (16U) //!< Bit position for I2S_TCR4_FRSZ.
-#define BM_I2S_TCR4_FRSZ (0x001F0000U) //!< Bit mask for I2S_TCR4_FRSZ.
-#define BS_I2S_TCR4_FRSZ (5U) //!< Bit field size in bits for I2S_TCR4_FRSZ.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCR4_FRSZ field.
-#define BR_I2S_TCR4_FRSZ(x) (HW_I2S_TCR4(x).B.FRSZ)
-#endif
-
-//! @brief Format value for bitfield I2S_TCR4_FRSZ.
-#define BF_I2S_TCR4_FRSZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_FRSZ), uint32_t) & BM_I2S_TCR4_FRSZ)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FRSZ field to a new value.
-#define BW_I2S_TCR4_FRSZ(x, v) (HW_I2S_TCR4_WR(x, (HW_I2S_TCR4_RD(x) & ~BM_I2S_TCR4_FRSZ) | BF_I2S_TCR4_FRSZ(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2S_TCR5 - SAI Transmit Configuration 5 Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2S_TCR5 - SAI Transmit Configuration 5 Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register must not be altered when TCSR[TE] is set.
- */
-typedef union _hw_i2s_tcr5
-{
- uint32_t U;
- struct _hw_i2s_tcr5_bitfields
- {
- uint32_t RESERVED0 : 8; //!< [7:0]
- uint32_t FBT : 5; //!< [12:8] First Bit Shifted
- uint32_t RESERVED1 : 3; //!< [15:13]
- uint32_t W0W : 5; //!< [20:16] Word 0 Width
- uint32_t RESERVED2 : 3; //!< [23:21]
- uint32_t WNW : 5; //!< [28:24] Word N Width
- uint32_t RESERVED3 : 3; //!< [31:29]
- } B;
-} hw_i2s_tcr5_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2S_TCR5 register
- */
-//@{
-#define HW_I2S_TCR5_ADDR(x) (REGS_I2S_BASE(x) + 0x14U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2S_TCR5(x) (*(__IO hw_i2s_tcr5_t *) HW_I2S_TCR5_ADDR(x))
-#define HW_I2S_TCR5_RD(x) (HW_I2S_TCR5(x).U)
-#define HW_I2S_TCR5_WR(x, v) (HW_I2S_TCR5(x).U = (v))
-#define HW_I2S_TCR5_SET(x, v) (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) | (v)))
-#define HW_I2S_TCR5_CLR(x, v) (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) & ~(v)))
-#define HW_I2S_TCR5_TOG(x, v) (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2S_TCR5 bitfields
- */
-
-/*!
- * @name Register I2S_TCR5, field FBT[12:8] (RW)
- *
- * Configures the bit index for the first bit transmitted for each word in the
- * frame. If configured for MSB First, the index of the next bit transmitted is
- * one less than the current bit transmitted. If configured for LSB First, the
- * index of the next bit transmitted is one more than the current bit transmitted.
- * The value written must be greater than or equal to the word width when
- * configured for MSB First. The value written must be less than or equal to 31-word width
- * when configured for LSB First.
- */
-//@{
-#define BP_I2S_TCR5_FBT (8U) //!< Bit position for I2S_TCR5_FBT.
-#define BM_I2S_TCR5_FBT (0x00001F00U) //!< Bit mask for I2S_TCR5_FBT.
-#define BS_I2S_TCR5_FBT (5U) //!< Bit field size in bits for I2S_TCR5_FBT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCR5_FBT field.
-#define BR_I2S_TCR5_FBT(x) (HW_I2S_TCR5(x).B.FBT)
-#endif
-
-//! @brief Format value for bitfield I2S_TCR5_FBT.
-#define BF_I2S_TCR5_FBT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR5_FBT), uint32_t) & BM_I2S_TCR5_FBT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FBT field to a new value.
-#define BW_I2S_TCR5_FBT(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_FBT) | BF_I2S_TCR5_FBT(v)))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCR5, field W0W[20:16] (RW)
- *
- * Configures the number of bits in the first word in each frame. The value
- * written must be one less than the number of bits in the first word. Word width of
- * less than 8 bits is not supported if there is only one word per frame.
- */
-//@{
-#define BP_I2S_TCR5_W0W (16U) //!< Bit position for I2S_TCR5_W0W.
-#define BM_I2S_TCR5_W0W (0x001F0000U) //!< Bit mask for I2S_TCR5_W0W.
-#define BS_I2S_TCR5_W0W (5U) //!< Bit field size in bits for I2S_TCR5_W0W.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCR5_W0W field.
-#define BR_I2S_TCR5_W0W(x) (HW_I2S_TCR5(x).B.W0W)
-#endif
-
-//! @brief Format value for bitfield I2S_TCR5_W0W.
-#define BF_I2S_TCR5_W0W(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR5_W0W), uint32_t) & BM_I2S_TCR5_W0W)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the W0W field to a new value.
-#define BW_I2S_TCR5_W0W(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_W0W) | BF_I2S_TCR5_W0W(v)))
-#endif
-//@}
-
-/*!
- * @name Register I2S_TCR5, field WNW[28:24] (RW)
- *
- * Configures the number of bits in each word, for each word except the first in
- * the frame. The value written must be one less than the number of bits per
- * word. Word width of less than 8 bits is not supported.
- */
-//@{
-#define BP_I2S_TCR5_WNW (24U) //!< Bit position for I2S_TCR5_WNW.
-#define BM_I2S_TCR5_WNW (0x1F000000U) //!< Bit mask for I2S_TCR5_WNW.
-#define BS_I2S_TCR5_WNW (5U) //!< Bit field size in bits for I2S_TCR5_WNW.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TCR5_WNW field.
-#define BR_I2S_TCR5_WNW(x) (HW_I2S_TCR5(x).B.WNW)
-#endif
-
-//! @brief Format value for bitfield I2S_TCR5_WNW.
-#define BF_I2S_TCR5_WNW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR5_WNW), uint32_t) & BM_I2S_TCR5_WNW)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WNW field to a new value.
-#define BW_I2S_TCR5_WNW(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_WNW) | BF_I2S_TCR5_WNW(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2S_TDRn - SAI Transmit Data Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2S_TDRn - SAI Transmit Data Register (WORZ)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_i2s_tdrn
-{
- uint32_t U;
- struct _hw_i2s_tdrn_bitfields
- {
- uint32_t TDR : 32; //!< [31:0] Transmit Data Register
- } B;
-} hw_i2s_tdrn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2S_TDRn register
- */
-//@{
-#define HW_I2S_TDRn_COUNT (2U)
-
-#define HW_I2S_TDRn_ADDR(x, n) (REGS_I2S_BASE(x) + 0x20U + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2S_TDRn(x, n) (*(__O hw_i2s_tdrn_t *) HW_I2S_TDRn_ADDR(x, n))
-#define HW_I2S_TDRn_RD(x, n) (HW_I2S_TDRn(x, n).U)
-#define HW_I2S_TDRn_WR(x, n, v) (HW_I2S_TDRn(x, n).U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2S_TDRn bitfields
- */
-
-/*!
- * @name Register I2S_TDRn, field TDR[31:0] (WORZ)
- *
- * The corresponding TCR3[TCE] bit must be set before accessing the channel's
- * transmit data register. Writes to this register when the transmit FIFO is not
- * full will push the data written into the transmit data FIFO. Writes to this
- * register when the transmit FIFO is full are ignored.
- */
-//@{
-#define BP_I2S_TDRn_TDR (0U) //!< Bit position for I2S_TDRn_TDR.
-#define BM_I2S_TDRn_TDR (0xFFFFFFFFU) //!< Bit mask for I2S_TDRn_TDR.
-#define BS_I2S_TDRn_TDR (32U) //!< Bit field size in bits for I2S_TDRn_TDR.
-
-//! @brief Format value for bitfield I2S_TDRn_TDR.
-#define BF_I2S_TDRn_TDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TDRn_TDR), uint32_t) & BM_I2S_TDRn_TDR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TDR field to a new value.
-#define BW_I2S_TDRn_TDR(x, n, v) (HW_I2S_TDRn_WR(x, n, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2S_TFRn - SAI Transmit FIFO Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2S_TFRn - SAI Transmit FIFO Register (RO)
- *
- * Reset value: 0x00000000U
- *
- * The MSB of the read and write pointers is used to distinguish between FIFO
- * full and empty conditions. If the read and write pointers are identical, then
- * the FIFO is empty. If the read and write pointers are identical except for the
- * MSB, then the FIFO is full.
- */
-typedef union _hw_i2s_tfrn
-{
- uint32_t U;
- struct _hw_i2s_tfrn_bitfields
- {
- uint32_t RFP : 4; //!< [3:0] Read FIFO Pointer
- uint32_t RESERVED0 : 12; //!< [15:4]
- uint32_t WFP : 4; //!< [19:16] Write FIFO Pointer
- uint32_t RESERVED1 : 12; //!< [31:20]
- } B;
-} hw_i2s_tfrn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2S_TFRn register
- */
-//@{
-#define HW_I2S_TFRn_COUNT (2U)
-
-#define HW_I2S_TFRn_ADDR(x, n) (REGS_I2S_BASE(x) + 0x40U + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2S_TFRn(x, n) (*(__I hw_i2s_tfrn_t *) HW_I2S_TFRn_ADDR(x, n))
-#define HW_I2S_TFRn_RD(x, n) (HW_I2S_TFRn(x, n).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2S_TFRn bitfields
- */
-
-/*!
- * @name Register I2S_TFRn, field RFP[3:0] (RO)
- *
- * FIFO read pointer for transmit data channel.
- */
-//@{
-#define BP_I2S_TFRn_RFP (0U) //!< Bit position for I2S_TFRn_RFP.
-#define BM_I2S_TFRn_RFP (0x0000000FU) //!< Bit mask for I2S_TFRn_RFP.
-#define BS_I2S_TFRn_RFP (4U) //!< Bit field size in bits for I2S_TFRn_RFP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TFRn_RFP field.
-#define BR_I2S_TFRn_RFP(x, n) (HW_I2S_TFRn(x, n).B.RFP)
-#endif
-//@}
-
-/*!
- * @name Register I2S_TFRn, field WFP[19:16] (RO)
- *
- * FIFO write pointer for transmit data channel.
- */
-//@{
-#define BP_I2S_TFRn_WFP (16U) //!< Bit position for I2S_TFRn_WFP.
-#define BM_I2S_TFRn_WFP (0x000F0000U) //!< Bit mask for I2S_TFRn_WFP.
-#define BS_I2S_TFRn_WFP (4U) //!< Bit field size in bits for I2S_TFRn_WFP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TFRn_WFP field.
-#define BR_I2S_TFRn_WFP(x, n) (HW_I2S_TFRn(x, n).B.WFP)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2S_TMR - SAI Transmit Mask Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2S_TMR - SAI Transmit Mask Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register is double-buffered and updates: When TCSR[TE] is first set At
- * the end of each frame. This allows the masked words in each frame to change
- * from frame to frame.
- */
-typedef union _hw_i2s_tmr
-{
- uint32_t U;
- struct _hw_i2s_tmr_bitfields
- {
- uint32_t TWM : 32; //!< [31:0] Transmit Word Mask
- } B;
-} hw_i2s_tmr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2S_TMR register
- */
-//@{
-#define HW_I2S_TMR_ADDR(x) (REGS_I2S_BASE(x) + 0x60U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2S_TMR(x) (*(__IO hw_i2s_tmr_t *) HW_I2S_TMR_ADDR(x))
-#define HW_I2S_TMR_RD(x) (HW_I2S_TMR(x).U)
-#define HW_I2S_TMR_WR(x, v) (HW_I2S_TMR(x).U = (v))
-#define HW_I2S_TMR_SET(x, v) (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) | (v)))
-#define HW_I2S_TMR_CLR(x, v) (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) & ~(v)))
-#define HW_I2S_TMR_TOG(x, v) (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2S_TMR bitfields
- */
-
-/*!
- * @name Register I2S_TMR, field TWM[31:0] (RW)
- *
- * Configures whether the transmit word is masked (transmit data pin tristated
- * and transmit data not read from FIFO) for the corresponding word in the frame.
- *
- * Values:
- * - 0 - Word N is enabled.
- * - 1 - Word N is masked. The transmit data pins are tri-stated when masked.
- */
-//@{
-#define BP_I2S_TMR_TWM (0U) //!< Bit position for I2S_TMR_TWM.
-#define BM_I2S_TMR_TWM (0xFFFFFFFFU) //!< Bit mask for I2S_TMR_TWM.
-#define BS_I2S_TMR_TWM (32U) //!< Bit field size in bits for I2S_TMR_TWM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_TMR_TWM field.
-#define BR_I2S_TMR_TWM(x) (HW_I2S_TMR(x).U)
-#endif
-
-//! @brief Format value for bitfield I2S_TMR_TWM.
-#define BF_I2S_TMR_TWM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TMR_TWM), uint32_t) & BM_I2S_TMR_TWM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TWM field to a new value.
-#define BW_I2S_TMR_TWM(x, v) (HW_I2S_TMR_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2S_RCSR - SAI Receive Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2S_RCSR - SAI Receive Control Register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_i2s_rcsr
-{
- uint32_t U;
- struct _hw_i2s_rcsr_bitfields
- {
- uint32_t FRDE : 1; //!< [0] FIFO Request DMA Enable
- uint32_t FWDE : 1; //!< [1] FIFO Warning DMA Enable
- uint32_t RESERVED0 : 6; //!< [7:2]
- uint32_t FRIE : 1; //!< [8] FIFO Request Interrupt Enable
- uint32_t FWIE : 1; //!< [9] FIFO Warning Interrupt Enable
- uint32_t FEIE : 1; //!< [10] FIFO Error Interrupt Enable
- uint32_t SEIE : 1; //!< [11] Sync Error Interrupt Enable
- uint32_t WSIE : 1; //!< [12] Word Start Interrupt Enable
- uint32_t RESERVED1 : 3; //!< [15:13]
- uint32_t FRF : 1; //!< [16] FIFO Request Flag
- uint32_t FWF : 1; //!< [17] FIFO Warning Flag
- uint32_t FEF : 1; //!< [18] FIFO Error Flag
- uint32_t SEF : 1; //!< [19] Sync Error Flag
- uint32_t WSF : 1; //!< [20] Word Start Flag
- uint32_t RESERVED2 : 3; //!< [23:21]
- uint32_t SR : 1; //!< [24] Software Reset
- uint32_t FR : 1; //!< [25] FIFO Reset
- uint32_t RESERVED3 : 2; //!< [27:26]
- uint32_t BCE : 1; //!< [28] Bit Clock Enable
- uint32_t DBGE : 1; //!< [29] Debug Enable
- uint32_t STOPE : 1; //!< [30] Stop Enable
- uint32_t RE : 1; //!< [31] Receiver Enable
- } B;
-} hw_i2s_rcsr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2S_RCSR register
- */
-//@{
-#define HW_I2S_RCSR_ADDR(x) (REGS_I2S_BASE(x) + 0x80U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2S_RCSR(x) (*(__IO hw_i2s_rcsr_t *) HW_I2S_RCSR_ADDR(x))
-#define HW_I2S_RCSR_RD(x) (HW_I2S_RCSR(x).U)
-#define HW_I2S_RCSR_WR(x, v) (HW_I2S_RCSR(x).U = (v))
-#define HW_I2S_RCSR_SET(x, v) (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) | (v)))
-#define HW_I2S_RCSR_CLR(x, v) (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) & ~(v)))
-#define HW_I2S_RCSR_TOG(x, v) (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2S_RCSR bitfields
- */
-
-/*!
- * @name Register I2S_RCSR, field FRDE[0] (RW)
- *
- * Enables/disables DMA requests.
- *
- * Values:
- * - 0 - Disables the DMA request.
- * - 1 - Enables the DMA request.
- */
-//@{
-#define BP_I2S_RCSR_FRDE (0U) //!< Bit position for I2S_RCSR_FRDE.
-#define BM_I2S_RCSR_FRDE (0x00000001U) //!< Bit mask for I2S_RCSR_FRDE.
-#define BS_I2S_RCSR_FRDE (1U) //!< Bit field size in bits for I2S_RCSR_FRDE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCSR_FRDE field.
-#define BR_I2S_RCSR_FRDE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRDE))
-#endif
-
-//! @brief Format value for bitfield I2S_RCSR_FRDE.
-#define BF_I2S_RCSR_FRDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FRDE), uint32_t) & BM_I2S_RCSR_FRDE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FRDE field to a new value.
-#define BW_I2S_RCSR_FRDE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRDE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCSR, field FWDE[1] (RW)
- *
- * Enables/disables DMA requests.
- *
- * Values:
- * - 0 - Disables the DMA request.
- * - 1 - Enables the DMA request.
- */
-//@{
-#define BP_I2S_RCSR_FWDE (1U) //!< Bit position for I2S_RCSR_FWDE.
-#define BM_I2S_RCSR_FWDE (0x00000002U) //!< Bit mask for I2S_RCSR_FWDE.
-#define BS_I2S_RCSR_FWDE (1U) //!< Bit field size in bits for I2S_RCSR_FWDE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCSR_FWDE field.
-#define BR_I2S_RCSR_FWDE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWDE))
-#endif
-
-//! @brief Format value for bitfield I2S_RCSR_FWDE.
-#define BF_I2S_RCSR_FWDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FWDE), uint32_t) & BM_I2S_RCSR_FWDE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FWDE field to a new value.
-#define BW_I2S_RCSR_FWDE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWDE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCSR, field FRIE[8] (RW)
- *
- * Enables/disables FIFO request interrupts.
- *
- * Values:
- * - 0 - Disables the interrupt.
- * - 1 - Enables the interrupt.
- */
-//@{
-#define BP_I2S_RCSR_FRIE (8U) //!< Bit position for I2S_RCSR_FRIE.
-#define BM_I2S_RCSR_FRIE (0x00000100U) //!< Bit mask for I2S_RCSR_FRIE.
-#define BS_I2S_RCSR_FRIE (1U) //!< Bit field size in bits for I2S_RCSR_FRIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCSR_FRIE field.
-#define BR_I2S_RCSR_FRIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRIE))
-#endif
-
-//! @brief Format value for bitfield I2S_RCSR_FRIE.
-#define BF_I2S_RCSR_FRIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FRIE), uint32_t) & BM_I2S_RCSR_FRIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FRIE field to a new value.
-#define BW_I2S_RCSR_FRIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCSR, field FWIE[9] (RW)
- *
- * Enables/disables FIFO warning interrupts.
- *
- * Values:
- * - 0 - Disables the interrupt.
- * - 1 - Enables the interrupt.
- */
-//@{
-#define BP_I2S_RCSR_FWIE (9U) //!< Bit position for I2S_RCSR_FWIE.
-#define BM_I2S_RCSR_FWIE (0x00000200U) //!< Bit mask for I2S_RCSR_FWIE.
-#define BS_I2S_RCSR_FWIE (1U) //!< Bit field size in bits for I2S_RCSR_FWIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCSR_FWIE field.
-#define BR_I2S_RCSR_FWIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWIE))
-#endif
-
-//! @brief Format value for bitfield I2S_RCSR_FWIE.
-#define BF_I2S_RCSR_FWIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FWIE), uint32_t) & BM_I2S_RCSR_FWIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FWIE field to a new value.
-#define BW_I2S_RCSR_FWIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCSR, field FEIE[10] (RW)
- *
- * Enables/disables FIFO error interrupts.
- *
- * Values:
- * - 0 - Disables the interrupt.
- * - 1 - Enables the interrupt.
- */
-//@{
-#define BP_I2S_RCSR_FEIE (10U) //!< Bit position for I2S_RCSR_FEIE.
-#define BM_I2S_RCSR_FEIE (0x00000400U) //!< Bit mask for I2S_RCSR_FEIE.
-#define BS_I2S_RCSR_FEIE (1U) //!< Bit field size in bits for I2S_RCSR_FEIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCSR_FEIE field.
-#define BR_I2S_RCSR_FEIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEIE))
-#endif
-
-//! @brief Format value for bitfield I2S_RCSR_FEIE.
-#define BF_I2S_RCSR_FEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FEIE), uint32_t) & BM_I2S_RCSR_FEIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FEIE field to a new value.
-#define BW_I2S_RCSR_FEIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCSR, field SEIE[11] (RW)
- *
- * Enables/disables sync error interrupts.
- *
- * Values:
- * - 0 - Disables interrupt.
- * - 1 - Enables interrupt.
- */
-//@{
-#define BP_I2S_RCSR_SEIE (11U) //!< Bit position for I2S_RCSR_SEIE.
-#define BM_I2S_RCSR_SEIE (0x00000800U) //!< Bit mask for I2S_RCSR_SEIE.
-#define BS_I2S_RCSR_SEIE (1U) //!< Bit field size in bits for I2S_RCSR_SEIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCSR_SEIE field.
-#define BR_I2S_RCSR_SEIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEIE))
-#endif
-
-//! @brief Format value for bitfield I2S_RCSR_SEIE.
-#define BF_I2S_RCSR_SEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_SEIE), uint32_t) & BM_I2S_RCSR_SEIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SEIE field to a new value.
-#define BW_I2S_RCSR_SEIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCSR, field WSIE[12] (RW)
- *
- * Enables/disables word start interrupts.
- *
- * Values:
- * - 0 - Disables interrupt.
- * - 1 - Enables interrupt.
- */
-//@{
-#define BP_I2S_RCSR_WSIE (12U) //!< Bit position for I2S_RCSR_WSIE.
-#define BM_I2S_RCSR_WSIE (0x00001000U) //!< Bit mask for I2S_RCSR_WSIE.
-#define BS_I2S_RCSR_WSIE (1U) //!< Bit field size in bits for I2S_RCSR_WSIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCSR_WSIE field.
-#define BR_I2S_RCSR_WSIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSIE))
-#endif
-
-//! @brief Format value for bitfield I2S_RCSR_WSIE.
-#define BF_I2S_RCSR_WSIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_WSIE), uint32_t) & BM_I2S_RCSR_WSIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WSIE field to a new value.
-#define BW_I2S_RCSR_WSIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCSR, field FRF[16] (RO)
- *
- * Indicates that the number of words in an enabled receive channel FIFO is
- * greater than the receive FIFO watermark.
- *
- * Values:
- * - 0 - Receive FIFO watermark not reached.
- * - 1 - Receive FIFO watermark has been reached.
- */
-//@{
-#define BP_I2S_RCSR_FRF (16U) //!< Bit position for I2S_RCSR_FRF.
-#define BM_I2S_RCSR_FRF (0x00010000U) //!< Bit mask for I2S_RCSR_FRF.
-#define BS_I2S_RCSR_FRF (1U) //!< Bit field size in bits for I2S_RCSR_FRF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCSR_FRF field.
-#define BR_I2S_RCSR_FRF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRF))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCSR, field FWF[17] (RO)
- *
- * Indicates that an enabled receive FIFO is full.
- *
- * Values:
- * - 0 - No enabled receive FIFO is full.
- * - 1 - Enabled receive FIFO is full.
- */
-//@{
-#define BP_I2S_RCSR_FWF (17U) //!< Bit position for I2S_RCSR_FWF.
-#define BM_I2S_RCSR_FWF (0x00020000U) //!< Bit mask for I2S_RCSR_FWF.
-#define BS_I2S_RCSR_FWF (1U) //!< Bit field size in bits for I2S_RCSR_FWF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCSR_FWF field.
-#define BR_I2S_RCSR_FWF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWF))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCSR, field FEF[18] (W1C)
- *
- * Indicates that an enabled receive FIFO has overflowed. Write a logic 1 to
- * this field to clear this flag.
- *
- * Values:
- * - 0 - Receive overflow not detected.
- * - 1 - Receive overflow detected.
- */
-//@{
-#define BP_I2S_RCSR_FEF (18U) //!< Bit position for I2S_RCSR_FEF.
-#define BM_I2S_RCSR_FEF (0x00040000U) //!< Bit mask for I2S_RCSR_FEF.
-#define BS_I2S_RCSR_FEF (1U) //!< Bit field size in bits for I2S_RCSR_FEF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCSR_FEF field.
-#define BR_I2S_RCSR_FEF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEF))
-#endif
-
-//! @brief Format value for bitfield I2S_RCSR_FEF.
-#define BF_I2S_RCSR_FEF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FEF), uint32_t) & BM_I2S_RCSR_FEF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FEF field to a new value.
-#define BW_I2S_RCSR_FEF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCSR, field SEF[19] (W1C)
- *
- * Indicates that an error in the externally-generated frame sync has been
- * detected. Write a logic 1 to this field to clear this flag.
- *
- * Values:
- * - 0 - Sync error not detected.
- * - 1 - Frame sync error detected.
- */
-//@{
-#define BP_I2S_RCSR_SEF (19U) //!< Bit position for I2S_RCSR_SEF.
-#define BM_I2S_RCSR_SEF (0x00080000U) //!< Bit mask for I2S_RCSR_SEF.
-#define BS_I2S_RCSR_SEF (1U) //!< Bit field size in bits for I2S_RCSR_SEF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCSR_SEF field.
-#define BR_I2S_RCSR_SEF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEF))
-#endif
-
-//! @brief Format value for bitfield I2S_RCSR_SEF.
-#define BF_I2S_RCSR_SEF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_SEF), uint32_t) & BM_I2S_RCSR_SEF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SEF field to a new value.
-#define BW_I2S_RCSR_SEF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCSR, field WSF[20] (W1C)
- *
- * Indicates that the start of the configured word has been detected. Write a
- * logic 1 to this field to clear this flag.
- *
- * Values:
- * - 0 - Start of word not detected.
- * - 1 - Start of word detected.
- */
-//@{
-#define BP_I2S_RCSR_WSF (20U) //!< Bit position for I2S_RCSR_WSF.
-#define BM_I2S_RCSR_WSF (0x00100000U) //!< Bit mask for I2S_RCSR_WSF.
-#define BS_I2S_RCSR_WSF (1U) //!< Bit field size in bits for I2S_RCSR_WSF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCSR_WSF field.
-#define BR_I2S_RCSR_WSF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSF))
-#endif
-
-//! @brief Format value for bitfield I2S_RCSR_WSF.
-#define BF_I2S_RCSR_WSF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_WSF), uint32_t) & BM_I2S_RCSR_WSF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WSF field to a new value.
-#define BW_I2S_RCSR_WSF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCSR, field SR[24] (RW)
- *
- * Resets the internal receiver logic including the FIFO pointers.
- * Software-visible registers are not affected, except for the status registers.
- *
- * Values:
- * - 0 - No effect.
- * - 1 - Software reset.
- */
-//@{
-#define BP_I2S_RCSR_SR (24U) //!< Bit position for I2S_RCSR_SR.
-#define BM_I2S_RCSR_SR (0x01000000U) //!< Bit mask for I2S_RCSR_SR.
-#define BS_I2S_RCSR_SR (1U) //!< Bit field size in bits for I2S_RCSR_SR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCSR_SR field.
-#define BR_I2S_RCSR_SR(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SR))
-#endif
-
-//! @brief Format value for bitfield I2S_RCSR_SR.
-#define BF_I2S_RCSR_SR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_SR), uint32_t) & BM_I2S_RCSR_SR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SR field to a new value.
-#define BW_I2S_RCSR_SR(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCSR, field FR[25] (WORZ)
- *
- * Resets the FIFO pointers. Reading this field will always return zero. FIFO
- * pointers should only be reset when the receiver is disabled or the FIFO error
- * flag is set.
- *
- * Values:
- * - 0 - No effect.
- * - 1 - FIFO reset.
- */
-//@{
-#define BP_I2S_RCSR_FR (25U) //!< Bit position for I2S_RCSR_FR.
-#define BM_I2S_RCSR_FR (0x02000000U) //!< Bit mask for I2S_RCSR_FR.
-#define BS_I2S_RCSR_FR (1U) //!< Bit field size in bits for I2S_RCSR_FR.
-
-//! @brief Format value for bitfield I2S_RCSR_FR.
-#define BF_I2S_RCSR_FR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FR), uint32_t) & BM_I2S_RCSR_FR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FR field to a new value.
-#define BW_I2S_RCSR_FR(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCSR, field BCE[28] (RW)
- *
- * Enables the receive bit clock, separately from RE. This field is
- * automatically set whenever RE is set. When software clears this field, the receive bit
- * clock remains enabled, and this field remains set, until the end of the current
- * frame.
- *
- * Values:
- * - 0 - Receive bit clock is disabled.
- * - 1 - Receive bit clock is enabled.
- */
-//@{
-#define BP_I2S_RCSR_BCE (28U) //!< Bit position for I2S_RCSR_BCE.
-#define BM_I2S_RCSR_BCE (0x10000000U) //!< Bit mask for I2S_RCSR_BCE.
-#define BS_I2S_RCSR_BCE (1U) //!< Bit field size in bits for I2S_RCSR_BCE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCSR_BCE field.
-#define BR_I2S_RCSR_BCE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_BCE))
-#endif
-
-//! @brief Format value for bitfield I2S_RCSR_BCE.
-#define BF_I2S_RCSR_BCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_BCE), uint32_t) & BM_I2S_RCSR_BCE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BCE field to a new value.
-#define BW_I2S_RCSR_BCE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_BCE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCSR, field DBGE[29] (RW)
- *
- * Enables/disables receiver operation in Debug mode. The receive bit clock is
- * not affected by Debug mode.
- *
- * Values:
- * - 0 - Receiver is disabled in Debug mode, after completing the current frame.
- * - 1 - Receiver is enabled in Debug mode.
- */
-//@{
-#define BP_I2S_RCSR_DBGE (29U) //!< Bit position for I2S_RCSR_DBGE.
-#define BM_I2S_RCSR_DBGE (0x20000000U) //!< Bit mask for I2S_RCSR_DBGE.
-#define BS_I2S_RCSR_DBGE (1U) //!< Bit field size in bits for I2S_RCSR_DBGE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCSR_DBGE field.
-#define BR_I2S_RCSR_DBGE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_DBGE))
-#endif
-
-//! @brief Format value for bitfield I2S_RCSR_DBGE.
-#define BF_I2S_RCSR_DBGE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_DBGE), uint32_t) & BM_I2S_RCSR_DBGE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DBGE field to a new value.
-#define BW_I2S_RCSR_DBGE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_DBGE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCSR, field STOPE[30] (RW)
- *
- * Configures receiver operation in Stop mode. This bit is ignored and the
- * receiver is disabled in all low-leakage stop modes.
- *
- * Values:
- * - 0 - Receiver disabled in Stop mode.
- * - 1 - Receiver enabled in Stop mode.
- */
-//@{
-#define BP_I2S_RCSR_STOPE (30U) //!< Bit position for I2S_RCSR_STOPE.
-#define BM_I2S_RCSR_STOPE (0x40000000U) //!< Bit mask for I2S_RCSR_STOPE.
-#define BS_I2S_RCSR_STOPE (1U) //!< Bit field size in bits for I2S_RCSR_STOPE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCSR_STOPE field.
-#define BR_I2S_RCSR_STOPE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_STOPE))
-#endif
-
-//! @brief Format value for bitfield I2S_RCSR_STOPE.
-#define BF_I2S_RCSR_STOPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_STOPE), uint32_t) & BM_I2S_RCSR_STOPE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the STOPE field to a new value.
-#define BW_I2S_RCSR_STOPE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_STOPE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCSR, field RE[31] (RW)
- *
- * Enables/disables the receiver. When software clears this field, the receiver
- * remains enabled, and this bit remains set, until the end of the current frame.
- *
- * Values:
- * - 0 - Receiver is disabled.
- * - 1 - Receiver is enabled, or receiver has been disabled and has not yet
- * reached end of frame.
- */
-//@{
-#define BP_I2S_RCSR_RE (31U) //!< Bit position for I2S_RCSR_RE.
-#define BM_I2S_RCSR_RE (0x80000000U) //!< Bit mask for I2S_RCSR_RE.
-#define BS_I2S_RCSR_RE (1U) //!< Bit field size in bits for I2S_RCSR_RE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCSR_RE field.
-#define BR_I2S_RCSR_RE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_RE))
-#endif
-
-//! @brief Format value for bitfield I2S_RCSR_RE.
-#define BF_I2S_RCSR_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_RE), uint32_t) & BM_I2S_RCSR_RE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RE field to a new value.
-#define BW_I2S_RCSR_RE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_RE) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2S_RCR1 - SAI Receive Configuration 1 Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2S_RCR1 - SAI Receive Configuration 1 Register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_i2s_rcr1
-{
- uint32_t U;
- struct _hw_i2s_rcr1_bitfields
- {
- uint32_t RFW : 3; //!< [2:0] Receive FIFO Watermark
- uint32_t RESERVED0 : 29; //!< [31:3]
- } B;
-} hw_i2s_rcr1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2S_RCR1 register
- */
-//@{
-#define HW_I2S_RCR1_ADDR(x) (REGS_I2S_BASE(x) + 0x84U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2S_RCR1(x) (*(__IO hw_i2s_rcr1_t *) HW_I2S_RCR1_ADDR(x))
-#define HW_I2S_RCR1_RD(x) (HW_I2S_RCR1(x).U)
-#define HW_I2S_RCR1_WR(x, v) (HW_I2S_RCR1(x).U = (v))
-#define HW_I2S_RCR1_SET(x, v) (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) | (v)))
-#define HW_I2S_RCR1_CLR(x, v) (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) & ~(v)))
-#define HW_I2S_RCR1_TOG(x, v) (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2S_RCR1 bitfields
- */
-
-/*!
- * @name Register I2S_RCR1, field RFW[2:0] (RW)
- *
- * Configures the watermark level for all enabled receiver channels.
- */
-//@{
-#define BP_I2S_RCR1_RFW (0U) //!< Bit position for I2S_RCR1_RFW.
-#define BM_I2S_RCR1_RFW (0x00000007U) //!< Bit mask for I2S_RCR1_RFW.
-#define BS_I2S_RCR1_RFW (3U) //!< Bit field size in bits for I2S_RCR1_RFW.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCR1_RFW field.
-#define BR_I2S_RCR1_RFW(x) (HW_I2S_RCR1(x).B.RFW)
-#endif
-
-//! @brief Format value for bitfield I2S_RCR1_RFW.
-#define BF_I2S_RCR1_RFW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR1_RFW), uint32_t) & BM_I2S_RCR1_RFW)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RFW field to a new value.
-#define BW_I2S_RCR1_RFW(x, v) (HW_I2S_RCR1_WR(x, (HW_I2S_RCR1_RD(x) & ~BM_I2S_RCR1_RFW) | BF_I2S_RCR1_RFW(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2S_RCR2 - SAI Receive Configuration 2 Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2S_RCR2 - SAI Receive Configuration 2 Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register must not be altered when RCSR[RE] is set.
- */
-typedef union _hw_i2s_rcr2
-{
- uint32_t U;
- struct _hw_i2s_rcr2_bitfields
- {
- uint32_t DIV : 8; //!< [7:0] Bit Clock Divide
- uint32_t RESERVED0 : 16; //!< [23:8]
- uint32_t BCD : 1; //!< [24] Bit Clock Direction
- uint32_t BCP : 1; //!< [25] Bit Clock Polarity
- uint32_t MSEL : 2; //!< [27:26] MCLK Select
- uint32_t BCI : 1; //!< [28] Bit Clock Input
- uint32_t BCS : 1; //!< [29] Bit Clock Swap
- uint32_t SYNC : 2; //!< [31:30] Synchronous Mode
- } B;
-} hw_i2s_rcr2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2S_RCR2 register
- */
-//@{
-#define HW_I2S_RCR2_ADDR(x) (REGS_I2S_BASE(x) + 0x88U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2S_RCR2(x) (*(__IO hw_i2s_rcr2_t *) HW_I2S_RCR2_ADDR(x))
-#define HW_I2S_RCR2_RD(x) (HW_I2S_RCR2(x).U)
-#define HW_I2S_RCR2_WR(x, v) (HW_I2S_RCR2(x).U = (v))
-#define HW_I2S_RCR2_SET(x, v) (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) | (v)))
-#define HW_I2S_RCR2_CLR(x, v) (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) & ~(v)))
-#define HW_I2S_RCR2_TOG(x, v) (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2S_RCR2 bitfields
- */
-
-/*!
- * @name Register I2S_RCR2, field DIV[7:0] (RW)
- *
- * Divides down the audio master clock to generate the bit clock when configured
- * for an internal bit clock. The division value is (DIV + 1) * 2.
- */
-//@{
-#define BP_I2S_RCR2_DIV (0U) //!< Bit position for I2S_RCR2_DIV.
-#define BM_I2S_RCR2_DIV (0x000000FFU) //!< Bit mask for I2S_RCR2_DIV.
-#define BS_I2S_RCR2_DIV (8U) //!< Bit field size in bits for I2S_RCR2_DIV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCR2_DIV field.
-#define BR_I2S_RCR2_DIV(x) (HW_I2S_RCR2(x).B.DIV)
-#endif
-
-//! @brief Format value for bitfield I2S_RCR2_DIV.
-#define BF_I2S_RCR2_DIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_DIV), uint32_t) & BM_I2S_RCR2_DIV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DIV field to a new value.
-#define BW_I2S_RCR2_DIV(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_DIV) | BF_I2S_RCR2_DIV(v)))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCR2, field BCD[24] (RW)
- *
- * Configures the direction of the bit clock.
- *
- * Values:
- * - 0 - Bit clock is generated externally in Slave mode.
- * - 1 - Bit clock is generated internally in Master mode.
- */
-//@{
-#define BP_I2S_RCR2_BCD (24U) //!< Bit position for I2S_RCR2_BCD.
-#define BM_I2S_RCR2_BCD (0x01000000U) //!< Bit mask for I2S_RCR2_BCD.
-#define BS_I2S_RCR2_BCD (1U) //!< Bit field size in bits for I2S_RCR2_BCD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCR2_BCD field.
-#define BR_I2S_RCR2_BCD(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCD))
-#endif
-
-//! @brief Format value for bitfield I2S_RCR2_BCD.
-#define BF_I2S_RCR2_BCD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_BCD), uint32_t) & BM_I2S_RCR2_BCD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BCD field to a new value.
-#define BW_I2S_RCR2_BCD(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCD) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCR2, field BCP[25] (RW)
- *
- * Configures the polarity of the bit clock.
- *
- * Values:
- * - 0 - Bit Clock is active high with drive outputs on rising edge and sample
- * inputs on falling edge.
- * - 1 - Bit Clock is active low with drive outputs on falling edge and sample
- * inputs on rising edge.
- */
-//@{
-#define BP_I2S_RCR2_BCP (25U) //!< Bit position for I2S_RCR2_BCP.
-#define BM_I2S_RCR2_BCP (0x02000000U) //!< Bit mask for I2S_RCR2_BCP.
-#define BS_I2S_RCR2_BCP (1U) //!< Bit field size in bits for I2S_RCR2_BCP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCR2_BCP field.
-#define BR_I2S_RCR2_BCP(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCP))
-#endif
-
-//! @brief Format value for bitfield I2S_RCR2_BCP.
-#define BF_I2S_RCR2_BCP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_BCP), uint32_t) & BM_I2S_RCR2_BCP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BCP field to a new value.
-#define BW_I2S_RCR2_BCP(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCP) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCR2, field MSEL[27:26] (RW)
- *
- * Selects the audio Master Clock option used to generate an internally
- * generated bit clock. This field has no effect when configured for an externally
- * generated bit clock. Depending on the device, some Master Clock options might not be
- * available. See the chip configuration details for the availability and
- * chip-specific meaning of each option.
- *
- * Values:
- * - 00 - Bus Clock selected.
- * - 01 - Master Clock (MCLK) 1 option selected.
- * - 10 - Master Clock (MCLK) 2 option selected.
- * - 11 - Master Clock (MCLK) 3 option selected.
- */
-//@{
-#define BP_I2S_RCR2_MSEL (26U) //!< Bit position for I2S_RCR2_MSEL.
-#define BM_I2S_RCR2_MSEL (0x0C000000U) //!< Bit mask for I2S_RCR2_MSEL.
-#define BS_I2S_RCR2_MSEL (2U) //!< Bit field size in bits for I2S_RCR2_MSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCR2_MSEL field.
-#define BR_I2S_RCR2_MSEL(x) (HW_I2S_RCR2(x).B.MSEL)
-#endif
-
-//! @brief Format value for bitfield I2S_RCR2_MSEL.
-#define BF_I2S_RCR2_MSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_MSEL), uint32_t) & BM_I2S_RCR2_MSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MSEL field to a new value.
-#define BW_I2S_RCR2_MSEL(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_MSEL) | BF_I2S_RCR2_MSEL(v)))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCR2, field BCI[28] (RW)
- *
- * When this field is set and using an internally generated bit clock in either
- * synchronous or asynchronous mode, the bit clock actually used by the receiver
- * is delayed by the pad output delay (the receiver is clocked by the pad input
- * as if the clock was externally generated). This has the effect of decreasing
- * the data input setup time, but increasing the data output valid time. The slave
- * mode timing from the datasheet should be used for the receiver when this bit
- * is set. In synchronous mode, this bit allows the receiver to use the slave mode
- * timing from the datasheet, while the transmitter uses the master mode timing.
- * This field has no effect when configured for an externally generated bit
- * clock or when synchronous to another SAI peripheral .
- *
- * Values:
- * - 0 - No effect.
- * - 1 - Internal logic is clocked as if bit clock was externally generated.
- */
-//@{
-#define BP_I2S_RCR2_BCI (28U) //!< Bit position for I2S_RCR2_BCI.
-#define BM_I2S_RCR2_BCI (0x10000000U) //!< Bit mask for I2S_RCR2_BCI.
-#define BS_I2S_RCR2_BCI (1U) //!< Bit field size in bits for I2S_RCR2_BCI.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCR2_BCI field.
-#define BR_I2S_RCR2_BCI(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCI))
-#endif
-
-//! @brief Format value for bitfield I2S_RCR2_BCI.
-#define BF_I2S_RCR2_BCI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_BCI), uint32_t) & BM_I2S_RCR2_BCI)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BCI field to a new value.
-#define BW_I2S_RCR2_BCI(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCI) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCR2, field BCS[29] (RW)
- *
- * This field swaps the bit clock used by the receiver. When the receiver is
- * configured in asynchronous mode and this bit is set, the receiver is clocked by
- * the transmitter bit clock (SAI_TX_BCLK). This allows the transmitter and
- * receiver to share the same bit clock, but the receiver continues to use the receiver
- * frame sync (SAI_RX_SYNC). When the receiver is configured in synchronous
- * mode, the transmitter BCS field and receiver BCS field must be set to the same
- * value. When both are set, the transmitter and receiver are both clocked by the
- * receiver bit clock (SAI_RX_BCLK) but use the transmitter frame sync
- * (SAI_TX_SYNC). This field has no effect when synchronous to another SAI peripheral.
- *
- * Values:
- * - 0 - Use the normal bit clock source.
- * - 1 - Swap the bit clock source.
- */
-//@{
-#define BP_I2S_RCR2_BCS (29U) //!< Bit position for I2S_RCR2_BCS.
-#define BM_I2S_RCR2_BCS (0x20000000U) //!< Bit mask for I2S_RCR2_BCS.
-#define BS_I2S_RCR2_BCS (1U) //!< Bit field size in bits for I2S_RCR2_BCS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCR2_BCS field.
-#define BR_I2S_RCR2_BCS(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCS))
-#endif
-
-//! @brief Format value for bitfield I2S_RCR2_BCS.
-#define BF_I2S_RCR2_BCS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_BCS), uint32_t) & BM_I2S_RCR2_BCS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BCS field to a new value.
-#define BW_I2S_RCR2_BCS(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCR2, field SYNC[31:30] (RW)
- *
- * Configures between asynchronous and synchronous modes of operation. When
- * configured for a synchronous mode of operation, the transmitter or other SAI
- * peripheral must be configured for asynchronous operation.
- *
- * Values:
- * - 00 - Asynchronous mode.
- * - 01 - Synchronous with transmitter.
- * - 10 - Synchronous with another SAI receiver.
- * - 11 - Synchronous with another SAI transmitter.
- */
-//@{
-#define BP_I2S_RCR2_SYNC (30U) //!< Bit position for I2S_RCR2_SYNC.
-#define BM_I2S_RCR2_SYNC (0xC0000000U) //!< Bit mask for I2S_RCR2_SYNC.
-#define BS_I2S_RCR2_SYNC (2U) //!< Bit field size in bits for I2S_RCR2_SYNC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCR2_SYNC field.
-#define BR_I2S_RCR2_SYNC(x) (HW_I2S_RCR2(x).B.SYNC)
-#endif
-
-//! @brief Format value for bitfield I2S_RCR2_SYNC.
-#define BF_I2S_RCR2_SYNC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_SYNC), uint32_t) & BM_I2S_RCR2_SYNC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SYNC field to a new value.
-#define BW_I2S_RCR2_SYNC(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_SYNC) | BF_I2S_RCR2_SYNC(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2S_RCR3 - SAI Receive Configuration 3 Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2S_RCR3 - SAI Receive Configuration 3 Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register must not be altered when RCSR[RE] is set.
- */
-typedef union _hw_i2s_rcr3
-{
- uint32_t U;
- struct _hw_i2s_rcr3_bitfields
- {
- uint32_t WDFL : 5; //!< [4:0] Word Flag Configuration
- uint32_t RESERVED0 : 11; //!< [15:5]
- uint32_t RCE : 2; //!< [17:16] Receive Channel Enable
- uint32_t RESERVED1 : 14; //!< [31:18]
- } B;
-} hw_i2s_rcr3_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2S_RCR3 register
- */
-//@{
-#define HW_I2S_RCR3_ADDR(x) (REGS_I2S_BASE(x) + 0x8CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2S_RCR3(x) (*(__IO hw_i2s_rcr3_t *) HW_I2S_RCR3_ADDR(x))
-#define HW_I2S_RCR3_RD(x) (HW_I2S_RCR3(x).U)
-#define HW_I2S_RCR3_WR(x, v) (HW_I2S_RCR3(x).U = (v))
-#define HW_I2S_RCR3_SET(x, v) (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) | (v)))
-#define HW_I2S_RCR3_CLR(x, v) (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) & ~(v)))
-#define HW_I2S_RCR3_TOG(x, v) (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2S_RCR3 bitfields
- */
-
-/*!
- * @name Register I2S_RCR3, field WDFL[4:0] (RW)
- *
- * Configures which word the start of word flag is set. The value written should
- * be one less than the word number (for example, write zero to configure for
- * the first word in the frame). When configured to a value greater than the Frame
- * Size field, then the start of word flag is never set.
- */
-//@{
-#define BP_I2S_RCR3_WDFL (0U) //!< Bit position for I2S_RCR3_WDFL.
-#define BM_I2S_RCR3_WDFL (0x0000001FU) //!< Bit mask for I2S_RCR3_WDFL.
-#define BS_I2S_RCR3_WDFL (5U) //!< Bit field size in bits for I2S_RCR3_WDFL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCR3_WDFL field.
-#define BR_I2S_RCR3_WDFL(x) (HW_I2S_RCR3(x).B.WDFL)
-#endif
-
-//! @brief Format value for bitfield I2S_RCR3_WDFL.
-#define BF_I2S_RCR3_WDFL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR3_WDFL), uint32_t) & BM_I2S_RCR3_WDFL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WDFL field to a new value.
-#define BW_I2S_RCR3_WDFL(x, v) (HW_I2S_RCR3_WR(x, (HW_I2S_RCR3_RD(x) & ~BM_I2S_RCR3_WDFL) | BF_I2S_RCR3_WDFL(v)))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCR3, field RCE[17:16] (RW)
- *
- * Enables the corresponding data channel for receive operation. A channel must
- * be enabled before its FIFO is accessed.
- *
- * Values:
- * - 0 - Receive data channel N is disabled.
- * - 1 - Receive data channel N is enabled.
- */
-//@{
-#define BP_I2S_RCR3_RCE (16U) //!< Bit position for I2S_RCR3_RCE.
-#define BM_I2S_RCR3_RCE (0x00030000U) //!< Bit mask for I2S_RCR3_RCE.
-#define BS_I2S_RCR3_RCE (2U) //!< Bit field size in bits for I2S_RCR3_RCE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCR3_RCE field.
-#define BR_I2S_RCR3_RCE(x) (HW_I2S_RCR3(x).B.RCE)
-#endif
-
-//! @brief Format value for bitfield I2S_RCR3_RCE.
-#define BF_I2S_RCR3_RCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR3_RCE), uint32_t) & BM_I2S_RCR3_RCE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RCE field to a new value.
-#define BW_I2S_RCR3_RCE(x, v) (HW_I2S_RCR3_WR(x, (HW_I2S_RCR3_RD(x) & ~BM_I2S_RCR3_RCE) | BF_I2S_RCR3_RCE(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2S_RCR4 - SAI Receive Configuration 4 Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2S_RCR4 - SAI Receive Configuration 4 Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register must not be altered when RCSR[RE] is set.
- */
-typedef union _hw_i2s_rcr4
-{
- uint32_t U;
- struct _hw_i2s_rcr4_bitfields
- {
- uint32_t FSD : 1; //!< [0] Frame Sync Direction
- uint32_t FSP : 1; //!< [1] Frame Sync Polarity
- uint32_t RESERVED0 : 1; //!< [2]
- uint32_t FSE : 1; //!< [3] Frame Sync Early
- uint32_t MF : 1; //!< [4] MSB First
- uint32_t RESERVED1 : 3; //!< [7:5]
- uint32_t SYWD : 5; //!< [12:8] Sync Width
- uint32_t RESERVED2 : 3; //!< [15:13]
- uint32_t FRSZ : 5; //!< [20:16] Frame Size
- uint32_t RESERVED3 : 11; //!< [31:21]
- } B;
-} hw_i2s_rcr4_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2S_RCR4 register
- */
-//@{
-#define HW_I2S_RCR4_ADDR(x) (REGS_I2S_BASE(x) + 0x90U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2S_RCR4(x) (*(__IO hw_i2s_rcr4_t *) HW_I2S_RCR4_ADDR(x))
-#define HW_I2S_RCR4_RD(x) (HW_I2S_RCR4(x).U)
-#define HW_I2S_RCR4_WR(x, v) (HW_I2S_RCR4(x).U = (v))
-#define HW_I2S_RCR4_SET(x, v) (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) | (v)))
-#define HW_I2S_RCR4_CLR(x, v) (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) & ~(v)))
-#define HW_I2S_RCR4_TOG(x, v) (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2S_RCR4 bitfields
- */
-
-/*!
- * @name Register I2S_RCR4, field FSD[0] (RW)
- *
- * Configures the direction of the frame sync.
- *
- * Values:
- * - 0 - Frame Sync is generated externally in Slave mode.
- * - 1 - Frame Sync is generated internally in Master mode.
- */
-//@{
-#define BP_I2S_RCR4_FSD (0U) //!< Bit position for I2S_RCR4_FSD.
-#define BM_I2S_RCR4_FSD (0x00000001U) //!< Bit mask for I2S_RCR4_FSD.
-#define BS_I2S_RCR4_FSD (1U) //!< Bit field size in bits for I2S_RCR4_FSD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCR4_FSD field.
-#define BR_I2S_RCR4_FSD(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSD))
-#endif
-
-//! @brief Format value for bitfield I2S_RCR4_FSD.
-#define BF_I2S_RCR4_FSD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_FSD), uint32_t) & BM_I2S_RCR4_FSD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FSD field to a new value.
-#define BW_I2S_RCR4_FSD(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSD) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCR4, field FSP[1] (RW)
- *
- * Configures the polarity of the frame sync.
- *
- * Values:
- * - 0 - Frame sync is active high.
- * - 1 - Frame sync is active low.
- */
-//@{
-#define BP_I2S_RCR4_FSP (1U) //!< Bit position for I2S_RCR4_FSP.
-#define BM_I2S_RCR4_FSP (0x00000002U) //!< Bit mask for I2S_RCR4_FSP.
-#define BS_I2S_RCR4_FSP (1U) //!< Bit field size in bits for I2S_RCR4_FSP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCR4_FSP field.
-#define BR_I2S_RCR4_FSP(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSP))
-#endif
-
-//! @brief Format value for bitfield I2S_RCR4_FSP.
-#define BF_I2S_RCR4_FSP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_FSP), uint32_t) & BM_I2S_RCR4_FSP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FSP field to a new value.
-#define BW_I2S_RCR4_FSP(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSP) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCR4, field FSE[3] (RW)
- *
- * Values:
- * - 0 - Frame sync asserts with the first bit of the frame.
- * - 1 - Frame sync asserts one bit before the first bit of the frame.
- */
-//@{
-#define BP_I2S_RCR4_FSE (3U) //!< Bit position for I2S_RCR4_FSE.
-#define BM_I2S_RCR4_FSE (0x00000008U) //!< Bit mask for I2S_RCR4_FSE.
-#define BS_I2S_RCR4_FSE (1U) //!< Bit field size in bits for I2S_RCR4_FSE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCR4_FSE field.
-#define BR_I2S_RCR4_FSE(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSE))
-#endif
-
-//! @brief Format value for bitfield I2S_RCR4_FSE.
-#define BF_I2S_RCR4_FSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_FSE), uint32_t) & BM_I2S_RCR4_FSE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FSE field to a new value.
-#define BW_I2S_RCR4_FSE(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCR4, field MF[4] (RW)
- *
- * Configures whether the LSB or the MSB is received first.
- *
- * Values:
- * - 0 - LSB is received first.
- * - 1 - MSB is received first.
- */
-//@{
-#define BP_I2S_RCR4_MF (4U) //!< Bit position for I2S_RCR4_MF.
-#define BM_I2S_RCR4_MF (0x00000010U) //!< Bit mask for I2S_RCR4_MF.
-#define BS_I2S_RCR4_MF (1U) //!< Bit field size in bits for I2S_RCR4_MF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCR4_MF field.
-#define BR_I2S_RCR4_MF(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_MF))
-#endif
-
-//! @brief Format value for bitfield I2S_RCR4_MF.
-#define BF_I2S_RCR4_MF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_MF), uint32_t) & BM_I2S_RCR4_MF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MF field to a new value.
-#define BW_I2S_RCR4_MF(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_MF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCR4, field SYWD[12:8] (RW)
- *
- * Configures the length of the frame sync in number of bit clocks. The value
- * written must be one less than the number of bit clocks. For example, write 0 for
- * the frame sync to assert for one bit clock only. The sync width cannot be
- * configured longer than the first word of the frame.
- */
-//@{
-#define BP_I2S_RCR4_SYWD (8U) //!< Bit position for I2S_RCR4_SYWD.
-#define BM_I2S_RCR4_SYWD (0x00001F00U) //!< Bit mask for I2S_RCR4_SYWD.
-#define BS_I2S_RCR4_SYWD (5U) //!< Bit field size in bits for I2S_RCR4_SYWD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCR4_SYWD field.
-#define BR_I2S_RCR4_SYWD(x) (HW_I2S_RCR4(x).B.SYWD)
-#endif
-
-//! @brief Format value for bitfield I2S_RCR4_SYWD.
-#define BF_I2S_RCR4_SYWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_SYWD), uint32_t) & BM_I2S_RCR4_SYWD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SYWD field to a new value.
-#define BW_I2S_RCR4_SYWD(x, v) (HW_I2S_RCR4_WR(x, (HW_I2S_RCR4_RD(x) & ~BM_I2S_RCR4_SYWD) | BF_I2S_RCR4_SYWD(v)))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCR4, field FRSZ[20:16] (RW)
- *
- * Configures the number of words in each frame. The value written must be one
- * less than the number of words in the frame. For example, write 0 for one word
- * per frame. The maximum supported frame size is 32 words.
- */
-//@{
-#define BP_I2S_RCR4_FRSZ (16U) //!< Bit position for I2S_RCR4_FRSZ.
-#define BM_I2S_RCR4_FRSZ (0x001F0000U) //!< Bit mask for I2S_RCR4_FRSZ.
-#define BS_I2S_RCR4_FRSZ (5U) //!< Bit field size in bits for I2S_RCR4_FRSZ.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCR4_FRSZ field.
-#define BR_I2S_RCR4_FRSZ(x) (HW_I2S_RCR4(x).B.FRSZ)
-#endif
-
-//! @brief Format value for bitfield I2S_RCR4_FRSZ.
-#define BF_I2S_RCR4_FRSZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_FRSZ), uint32_t) & BM_I2S_RCR4_FRSZ)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FRSZ field to a new value.
-#define BW_I2S_RCR4_FRSZ(x, v) (HW_I2S_RCR4_WR(x, (HW_I2S_RCR4_RD(x) & ~BM_I2S_RCR4_FRSZ) | BF_I2S_RCR4_FRSZ(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2S_RCR5 - SAI Receive Configuration 5 Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2S_RCR5 - SAI Receive Configuration 5 Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register must not be altered when RCSR[RE] is set.
- */
-typedef union _hw_i2s_rcr5
-{
- uint32_t U;
- struct _hw_i2s_rcr5_bitfields
- {
- uint32_t RESERVED0 : 8; //!< [7:0]
- uint32_t FBT : 5; //!< [12:8] First Bit Shifted
- uint32_t RESERVED1 : 3; //!< [15:13]
- uint32_t W0W : 5; //!< [20:16] Word 0 Width
- uint32_t RESERVED2 : 3; //!< [23:21]
- uint32_t WNW : 5; //!< [28:24] Word N Width
- uint32_t RESERVED3 : 3; //!< [31:29]
- } B;
-} hw_i2s_rcr5_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2S_RCR5 register
- */
-//@{
-#define HW_I2S_RCR5_ADDR(x) (REGS_I2S_BASE(x) + 0x94U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2S_RCR5(x) (*(__IO hw_i2s_rcr5_t *) HW_I2S_RCR5_ADDR(x))
-#define HW_I2S_RCR5_RD(x) (HW_I2S_RCR5(x).U)
-#define HW_I2S_RCR5_WR(x, v) (HW_I2S_RCR5(x).U = (v))
-#define HW_I2S_RCR5_SET(x, v) (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) | (v)))
-#define HW_I2S_RCR5_CLR(x, v) (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) & ~(v)))
-#define HW_I2S_RCR5_TOG(x, v) (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2S_RCR5 bitfields
- */
-
-/*!
- * @name Register I2S_RCR5, field FBT[12:8] (RW)
- *
- * Configures the bit index for the first bit received for each word in the
- * frame. If configured for MSB First, the index of the next bit received is one less
- * than the current bit received. If configured for LSB First, the index of the
- * next bit received is one more than the current bit received. The value written
- * must be greater than or equal to the word width when configured for MSB
- * First. The value written must be less than or equal to 31-word width when
- * configured for LSB First.
- */
-//@{
-#define BP_I2S_RCR5_FBT (8U) //!< Bit position for I2S_RCR5_FBT.
-#define BM_I2S_RCR5_FBT (0x00001F00U) //!< Bit mask for I2S_RCR5_FBT.
-#define BS_I2S_RCR5_FBT (5U) //!< Bit field size in bits for I2S_RCR5_FBT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCR5_FBT field.
-#define BR_I2S_RCR5_FBT(x) (HW_I2S_RCR5(x).B.FBT)
-#endif
-
-//! @brief Format value for bitfield I2S_RCR5_FBT.
-#define BF_I2S_RCR5_FBT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR5_FBT), uint32_t) & BM_I2S_RCR5_FBT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FBT field to a new value.
-#define BW_I2S_RCR5_FBT(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_FBT) | BF_I2S_RCR5_FBT(v)))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCR5, field W0W[20:16] (RW)
- *
- * Configures the number of bits in the first word in each frame. The value
- * written must be one less than the number of bits in the first word. Word width of
- * less than 8 bits is not supported if there is only one word per frame.
- */
-//@{
-#define BP_I2S_RCR5_W0W (16U) //!< Bit position for I2S_RCR5_W0W.
-#define BM_I2S_RCR5_W0W (0x001F0000U) //!< Bit mask for I2S_RCR5_W0W.
-#define BS_I2S_RCR5_W0W (5U) //!< Bit field size in bits for I2S_RCR5_W0W.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCR5_W0W field.
-#define BR_I2S_RCR5_W0W(x) (HW_I2S_RCR5(x).B.W0W)
-#endif
-
-//! @brief Format value for bitfield I2S_RCR5_W0W.
-#define BF_I2S_RCR5_W0W(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR5_W0W), uint32_t) & BM_I2S_RCR5_W0W)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the W0W field to a new value.
-#define BW_I2S_RCR5_W0W(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_W0W) | BF_I2S_RCR5_W0W(v)))
-#endif
-//@}
-
-/*!
- * @name Register I2S_RCR5, field WNW[28:24] (RW)
- *
- * Configures the number of bits in each word, for each word except the first in
- * the frame. The value written must be one less than the number of bits per
- * word. Word width of less than 8 bits is not supported.
- */
-//@{
-#define BP_I2S_RCR5_WNW (24U) //!< Bit position for I2S_RCR5_WNW.
-#define BM_I2S_RCR5_WNW (0x1F000000U) //!< Bit mask for I2S_RCR5_WNW.
-#define BS_I2S_RCR5_WNW (5U) //!< Bit field size in bits for I2S_RCR5_WNW.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RCR5_WNW field.
-#define BR_I2S_RCR5_WNW(x) (HW_I2S_RCR5(x).B.WNW)
-#endif
-
-//! @brief Format value for bitfield I2S_RCR5_WNW.
-#define BF_I2S_RCR5_WNW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR5_WNW), uint32_t) & BM_I2S_RCR5_WNW)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WNW field to a new value.
-#define BW_I2S_RCR5_WNW(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_WNW) | BF_I2S_RCR5_WNW(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2S_RDRn - SAI Receive Data Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2S_RDRn - SAI Receive Data Register (RO)
- *
- * Reset value: 0x00000000U
- *
- * Reading this register introduces one additional peripheral clock wait state
- * on each read.
- */
-typedef union _hw_i2s_rdrn
-{
- uint32_t U;
- struct _hw_i2s_rdrn_bitfields
- {
- uint32_t RDR : 32; //!< [31:0] Receive Data Register
- } B;
-} hw_i2s_rdrn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2S_RDRn register
- */
-//@{
-#define HW_I2S_RDRn_COUNT (2U)
-
-#define HW_I2S_RDRn_ADDR(x, n) (REGS_I2S_BASE(x) + 0xA0U + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2S_RDRn(x, n) (*(__I hw_i2s_rdrn_t *) HW_I2S_RDRn_ADDR(x, n))
-#define HW_I2S_RDRn_RD(x, n) (HW_I2S_RDRn(x, n).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2S_RDRn bitfields
- */
-
-/*!
- * @name Register I2S_RDRn, field RDR[31:0] (RO)
- *
- * The corresponding RCR3[RCE] bit must be set before accessing the channel's
- * receive data register. Reads from this register when the receive FIFO is not
- * empty will return the data from the top of the receive FIFO. Reads from this
- * register when the receive FIFO is empty are ignored.
- */
-//@{
-#define BP_I2S_RDRn_RDR (0U) //!< Bit position for I2S_RDRn_RDR.
-#define BM_I2S_RDRn_RDR (0xFFFFFFFFU) //!< Bit mask for I2S_RDRn_RDR.
-#define BS_I2S_RDRn_RDR (32U) //!< Bit field size in bits for I2S_RDRn_RDR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RDRn_RDR field.
-#define BR_I2S_RDRn_RDR(x, n) (HW_I2S_RDRn(x, n).U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2S_RFRn - SAI Receive FIFO Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2S_RFRn - SAI Receive FIFO Register (RO)
- *
- * Reset value: 0x00000000U
- *
- * The MSB of the read and write pointers is used to distinguish between FIFO
- * full and empty conditions. If the read and write pointers are identical, then
- * the FIFO is empty. If the read and write pointers are identical except for the
- * MSB, then the FIFO is full.
- */
-typedef union _hw_i2s_rfrn
-{
- uint32_t U;
- struct _hw_i2s_rfrn_bitfields
- {
- uint32_t RFP : 4; //!< [3:0] Read FIFO Pointer
- uint32_t RESERVED0 : 12; //!< [15:4]
- uint32_t WFP : 4; //!< [19:16] Write FIFO Pointer
- uint32_t RESERVED1 : 12; //!< [31:20]
- } B;
-} hw_i2s_rfrn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2S_RFRn register
- */
-//@{
-#define HW_I2S_RFRn_COUNT (2U)
-
-#define HW_I2S_RFRn_ADDR(x, n) (REGS_I2S_BASE(x) + 0xC0U + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2S_RFRn(x, n) (*(__I hw_i2s_rfrn_t *) HW_I2S_RFRn_ADDR(x, n))
-#define HW_I2S_RFRn_RD(x, n) (HW_I2S_RFRn(x, n).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2S_RFRn bitfields
- */
-
-/*!
- * @name Register I2S_RFRn, field RFP[3:0] (RO)
- *
- * FIFO read pointer for receive data channel.
- */
-//@{
-#define BP_I2S_RFRn_RFP (0U) //!< Bit position for I2S_RFRn_RFP.
-#define BM_I2S_RFRn_RFP (0x0000000FU) //!< Bit mask for I2S_RFRn_RFP.
-#define BS_I2S_RFRn_RFP (4U) //!< Bit field size in bits for I2S_RFRn_RFP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RFRn_RFP field.
-#define BR_I2S_RFRn_RFP(x, n) (HW_I2S_RFRn(x, n).B.RFP)
-#endif
-//@}
-
-/*!
- * @name Register I2S_RFRn, field WFP[19:16] (RO)
- *
- * FIFO write pointer for receive data channel.
- */
-//@{
-#define BP_I2S_RFRn_WFP (16U) //!< Bit position for I2S_RFRn_WFP.
-#define BM_I2S_RFRn_WFP (0x000F0000U) //!< Bit mask for I2S_RFRn_WFP.
-#define BS_I2S_RFRn_WFP (4U) //!< Bit field size in bits for I2S_RFRn_WFP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RFRn_WFP field.
-#define BR_I2S_RFRn_WFP(x, n) (HW_I2S_RFRn(x, n).B.WFP)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2S_RMR - SAI Receive Mask Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2S_RMR - SAI Receive Mask Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register is double-buffered and updates: When RCSR[RE] is first set At
- * the end of each frame This allows the masked words in each frame to change from
- * frame to frame.
- */
-typedef union _hw_i2s_rmr
-{
- uint32_t U;
- struct _hw_i2s_rmr_bitfields
- {
- uint32_t RWM : 32; //!< [31:0] Receive Word Mask
- } B;
-} hw_i2s_rmr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2S_RMR register
- */
-//@{
-#define HW_I2S_RMR_ADDR(x) (REGS_I2S_BASE(x) + 0xE0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2S_RMR(x) (*(__IO hw_i2s_rmr_t *) HW_I2S_RMR_ADDR(x))
-#define HW_I2S_RMR_RD(x) (HW_I2S_RMR(x).U)
-#define HW_I2S_RMR_WR(x, v) (HW_I2S_RMR(x).U = (v))
-#define HW_I2S_RMR_SET(x, v) (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) | (v)))
-#define HW_I2S_RMR_CLR(x, v) (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) & ~(v)))
-#define HW_I2S_RMR_TOG(x, v) (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2S_RMR bitfields
- */
-
-/*!
- * @name Register I2S_RMR, field RWM[31:0] (RW)
- *
- * Configures whether the receive word is masked (received data ignored and not
- * written to receive FIFO) for the corresponding word in the frame.
- *
- * Values:
- * - 0 - Word N is enabled.
- * - 1 - Word N is masked.
- */
-//@{
-#define BP_I2S_RMR_RWM (0U) //!< Bit position for I2S_RMR_RWM.
-#define BM_I2S_RMR_RWM (0xFFFFFFFFU) //!< Bit mask for I2S_RMR_RWM.
-#define BS_I2S_RMR_RWM (32U) //!< Bit field size in bits for I2S_RMR_RWM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_RMR_RWM field.
-#define BR_I2S_RMR_RWM(x) (HW_I2S_RMR(x).U)
-#endif
-
-//! @brief Format value for bitfield I2S_RMR_RWM.
-#define BF_I2S_RMR_RWM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RMR_RWM), uint32_t) & BM_I2S_RMR_RWM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RWM field to a new value.
-#define BW_I2S_RMR_RWM(x, v) (HW_I2S_RMR_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2S_MCR - SAI MCLK Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2S_MCR - SAI MCLK Control Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * The MCLK Control Register (MCR) controls the clock source and direction of
- * the audio master clock.
- */
-typedef union _hw_i2s_mcr
-{
- uint32_t U;
- struct _hw_i2s_mcr_bitfields
- {
- uint32_t RESERVED0 : 24; //!< [23:0]
- uint32_t MICS : 2; //!< [25:24] MCLK Input Clock Select
- uint32_t RESERVED1 : 4; //!< [29:26]
- uint32_t MOE : 1; //!< [30] MCLK Output Enable
- uint32_t DUF : 1; //!< [31] Divider Update Flag
- } B;
-} hw_i2s_mcr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2S_MCR register
- */
-//@{
-#define HW_I2S_MCR_ADDR(x) (REGS_I2S_BASE(x) + 0x100U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2S_MCR(x) (*(__IO hw_i2s_mcr_t *) HW_I2S_MCR_ADDR(x))
-#define HW_I2S_MCR_RD(x) (HW_I2S_MCR(x).U)
-#define HW_I2S_MCR_WR(x, v) (HW_I2S_MCR(x).U = (v))
-#define HW_I2S_MCR_SET(x, v) (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) | (v)))
-#define HW_I2S_MCR_CLR(x, v) (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) & ~(v)))
-#define HW_I2S_MCR_TOG(x, v) (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2S_MCR bitfields
- */
-
-/*!
- * @name Register I2S_MCR, field MICS[25:24] (RW)
- *
- * Selects the clock input to the MCLK divider. This field cannot be changed
- * while the MCLK divider is enabled. See the chip configuration details for
- * information about the connections to these inputs.
- *
- * Values:
- * - 00 - MCLK divider input clock 0 selected.
- * - 01 - MCLK divider input clock 1 selected.
- * - 10 - MCLK divider input clock 2 selected.
- * - 11 - MCLK divider input clock 3 selected.
- */
-//@{
-#define BP_I2S_MCR_MICS (24U) //!< Bit position for I2S_MCR_MICS.
-#define BM_I2S_MCR_MICS (0x03000000U) //!< Bit mask for I2S_MCR_MICS.
-#define BS_I2S_MCR_MICS (2U) //!< Bit field size in bits for I2S_MCR_MICS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_MCR_MICS field.
-#define BR_I2S_MCR_MICS(x) (HW_I2S_MCR(x).B.MICS)
-#endif
-
-//! @brief Format value for bitfield I2S_MCR_MICS.
-#define BF_I2S_MCR_MICS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_MCR_MICS), uint32_t) & BM_I2S_MCR_MICS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MICS field to a new value.
-#define BW_I2S_MCR_MICS(x, v) (HW_I2S_MCR_WR(x, (HW_I2S_MCR_RD(x) & ~BM_I2S_MCR_MICS) | BF_I2S_MCR_MICS(v)))
-#endif
-//@}
-
-/*!
- * @name Register I2S_MCR, field MOE[30] (RW)
- *
- * Enables the MCLK divider and configures the MCLK signal pin as an output.
- * When software clears this field, it remains set until the MCLK divider is fully
- * disabled.
- *
- * Values:
- * - 0 - MCLK signal pin is configured as an input that bypasses the MCLK
- * divider.
- * - 1 - MCLK signal pin is configured as an output from the MCLK divider and
- * the MCLK divider is enabled.
- */
-//@{
-#define BP_I2S_MCR_MOE (30U) //!< Bit position for I2S_MCR_MOE.
-#define BM_I2S_MCR_MOE (0x40000000U) //!< Bit mask for I2S_MCR_MOE.
-#define BS_I2S_MCR_MOE (1U) //!< Bit field size in bits for I2S_MCR_MOE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_MCR_MOE field.
-#define BR_I2S_MCR_MOE(x) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_MOE))
-#endif
-
-//! @brief Format value for bitfield I2S_MCR_MOE.
-#define BF_I2S_MCR_MOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_MCR_MOE), uint32_t) & BM_I2S_MCR_MOE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MOE field to a new value.
-#define BW_I2S_MCR_MOE(x, v) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_MOE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register I2S_MCR, field DUF[31] (RO)
- *
- * Provides the status of on-the-fly updates to the MCLK divider ratio.
- *
- * Values:
- * - 0 - MCLK divider ratio is not being updated currently.
- * - 1 - MCLK divider ratio is updating on-the-fly. Further updates to the MCLK
- * divider ratio are blocked while this flag remains set.
- */
-//@{
-#define BP_I2S_MCR_DUF (31U) //!< Bit position for I2S_MCR_DUF.
-#define BM_I2S_MCR_DUF (0x80000000U) //!< Bit mask for I2S_MCR_DUF.
-#define BS_I2S_MCR_DUF (1U) //!< Bit field size in bits for I2S_MCR_DUF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_MCR_DUF field.
-#define BR_I2S_MCR_DUF(x) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_DUF))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_I2S_MDR - SAI MCLK Divide Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_I2S_MDR - SAI MCLK Divide Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * The MCLK Divide Register (MDR) configures the MCLK divide ratio. Although the
- * MDR can be changed when the MCLK divider clock is enabled, additional writes
- * to the MDR are blocked while MCR[DUF] is set. Writes to the MDR when the MCLK
- * divided clock is disabled do not set MCR[DUF].
- */
-typedef union _hw_i2s_mdr
-{
- uint32_t U;
- struct _hw_i2s_mdr_bitfields
- {
- uint32_t DIVIDE : 12; //!< [11:0] MCLK Divide
- uint32_t FRACT : 8; //!< [19:12] MCLK Fraction
- uint32_t RESERVED0 : 12; //!< [31:20]
- } B;
-} hw_i2s_mdr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire I2S_MDR register
- */
-//@{
-#define HW_I2S_MDR_ADDR(x) (REGS_I2S_BASE(x) + 0x104U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_I2S_MDR(x) (*(__IO hw_i2s_mdr_t *) HW_I2S_MDR_ADDR(x))
-#define HW_I2S_MDR_RD(x) (HW_I2S_MDR(x).U)
-#define HW_I2S_MDR_WR(x, v) (HW_I2S_MDR(x).U = (v))
-#define HW_I2S_MDR_SET(x, v) (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) | (v)))
-#define HW_I2S_MDR_CLR(x, v) (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) & ~(v)))
-#define HW_I2S_MDR_TOG(x, v) (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual I2S_MDR bitfields
- */
-
-/*!
- * @name Register I2S_MDR, field DIVIDE[11:0] (RW)
- *
- * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
- * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
- * DIVIDE field.
- */
-//@{
-#define BP_I2S_MDR_DIVIDE (0U) //!< Bit position for I2S_MDR_DIVIDE.
-#define BM_I2S_MDR_DIVIDE (0x00000FFFU) //!< Bit mask for I2S_MDR_DIVIDE.
-#define BS_I2S_MDR_DIVIDE (12U) //!< Bit field size in bits for I2S_MDR_DIVIDE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_MDR_DIVIDE field.
-#define BR_I2S_MDR_DIVIDE(x) (HW_I2S_MDR(x).B.DIVIDE)
-#endif
-
-//! @brief Format value for bitfield I2S_MDR_DIVIDE.
-#define BF_I2S_MDR_DIVIDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_MDR_DIVIDE), uint32_t) & BM_I2S_MDR_DIVIDE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DIVIDE field to a new value.
-#define BW_I2S_MDR_DIVIDE(x, v) (HW_I2S_MDR_WR(x, (HW_I2S_MDR_RD(x) & ~BM_I2S_MDR_DIVIDE) | BF_I2S_MDR_DIVIDE(v)))
-#endif
-//@}
-
-/*!
- * @name Register I2S_MDR, field FRACT[19:12] (RW)
- *
- * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
- * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
- * DIVIDE field.
- */
-//@{
-#define BP_I2S_MDR_FRACT (12U) //!< Bit position for I2S_MDR_FRACT.
-#define BM_I2S_MDR_FRACT (0x000FF000U) //!< Bit mask for I2S_MDR_FRACT.
-#define BS_I2S_MDR_FRACT (8U) //!< Bit field size in bits for I2S_MDR_FRACT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the I2S_MDR_FRACT field.
-#define BR_I2S_MDR_FRACT(x) (HW_I2S_MDR(x).B.FRACT)
-#endif
-
-//! @brief Format value for bitfield I2S_MDR_FRACT.
-#define BF_I2S_MDR_FRACT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_MDR_FRACT), uint32_t) & BM_I2S_MDR_FRACT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FRACT field to a new value.
-#define BW_I2S_MDR_FRACT(x, v) (HW_I2S_MDR_WR(x, (HW_I2S_MDR_RD(x) & ~BM_I2S_MDR_FRACT) | BF_I2S_MDR_FRACT(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_i2s_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All I2S module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_i2s
-{
- __IO hw_i2s_tcsr_t TCSR; //!< [0x0] SAI Transmit Control Register
- __IO hw_i2s_tcr1_t TCR1; //!< [0x4] SAI Transmit Configuration 1 Register
- __IO hw_i2s_tcr2_t TCR2; //!< [0x8] SAI Transmit Configuration 2 Register
- __IO hw_i2s_tcr3_t TCR3; //!< [0xC] SAI Transmit Configuration 3 Register
- __IO hw_i2s_tcr4_t TCR4; //!< [0x10] SAI Transmit Configuration 4 Register
- __IO hw_i2s_tcr5_t TCR5; //!< [0x14] SAI Transmit Configuration 5 Register
- uint8_t _reserved0[8];
- __O hw_i2s_tdrn_t TDRn[2]; //!< [0x20] SAI Transmit Data Register
- uint8_t _reserved1[24];
- __I hw_i2s_tfrn_t TFRn[2]; //!< [0x40] SAI Transmit FIFO Register
- uint8_t _reserved2[24];
- __IO hw_i2s_tmr_t TMR; //!< [0x60] SAI Transmit Mask Register
- uint8_t _reserved3[28];
- __IO hw_i2s_rcsr_t RCSR; //!< [0x80] SAI Receive Control Register
- __IO hw_i2s_rcr1_t RCR1; //!< [0x84] SAI Receive Configuration 1 Register
- __IO hw_i2s_rcr2_t RCR2; //!< [0x88] SAI Receive Configuration 2 Register
- __IO hw_i2s_rcr3_t RCR3; //!< [0x8C] SAI Receive Configuration 3 Register
- __IO hw_i2s_rcr4_t RCR4; //!< [0x90] SAI Receive Configuration 4 Register
- __IO hw_i2s_rcr5_t RCR5; //!< [0x94] SAI Receive Configuration 5 Register
- uint8_t _reserved4[8];
- __I hw_i2s_rdrn_t RDRn[2]; //!< [0xA0] SAI Receive Data Register
- uint8_t _reserved5[24];
- __I hw_i2s_rfrn_t RFRn[2]; //!< [0xC0] SAI Receive FIFO Register
- uint8_t _reserved6[24];
- __IO hw_i2s_rmr_t RMR; //!< [0xE0] SAI Receive Mask Register
- uint8_t _reserved7[28];
- __IO hw_i2s_mcr_t MCR; //!< [0x100] SAI MCLK Control Register
- __IO hw_i2s_mdr_t MDR; //!< [0x104] SAI MCLK Divide Register
-} hw_i2s_t;
-#pragma pack()
-
-//! @brief Macro to access all I2S registers.
-//! @param x I2S instance number.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_I2S(0)</code>.
-#define HW_I2S(x) (*(hw_i2s_t *) REGS_I2S_BASE(x))
-#endif
-
-#endif // __HW_I2S_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_llwu.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,2252 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_LLWU_REGISTERS_H__
-#define __HW_LLWU_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 LLWU
- *
- * Low leakage wakeup unit
- *
- * Registers defined in this header file:
- * - HW_LLWU_PE1 - LLWU Pin Enable 1 register
- * - HW_LLWU_PE2 - LLWU Pin Enable 2 register
- * - HW_LLWU_PE3 - LLWU Pin Enable 3 register
- * - HW_LLWU_PE4 - LLWU Pin Enable 4 register
- * - HW_LLWU_ME - LLWU Module Enable register
- * - HW_LLWU_F1 - LLWU Flag 1 register
- * - HW_LLWU_F2 - LLWU Flag 2 register
- * - HW_LLWU_F3 - LLWU Flag 3 register
- * - HW_LLWU_FILT1 - LLWU Pin Filter 1 register
- * - HW_LLWU_FILT2 - LLWU Pin Filter 2 register
- * - HW_LLWU_RST - LLWU Reset Enable register
- *
- * - hw_llwu_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_LLWU_BASE
-#define HW_LLWU_INSTANCE_COUNT (1U) //!< Number of instances of the LLWU module.
-#define REGS_LLWU_BASE (0x4007C000U) //!< Base address for LLWU.
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_LLWU_PE1 - LLWU Pin Enable 1 register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_LLWU_PE1 - LLWU Pin Enable 1 register (RW)
- *
- * Reset value: 0x00U
- *
- * LLWU_PE1 contains the field to enable and select the edge detect type for the
- * external wakeup input pins LLWU_P3-LLWU_P0. This register is reset on Chip
- * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
- * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
- * IntroductionInformation found here describes the registers of the Reset Control Module
- * (RCM). The RCM implements many of the reset functions for the chip. See the
- * chip's reset chapter for more information. details for more information.
- */
-typedef union _hw_llwu_pe1
-{
- uint8_t U;
- struct _hw_llwu_pe1_bitfields
- {
- uint8_t WUPE0 : 2; //!< [1:0] Wakeup Pin Enable For LLWU_P0
- uint8_t WUPE1 : 2; //!< [3:2] Wakeup Pin Enable For LLWU_P1
- uint8_t WUPE2 : 2; //!< [5:4] Wakeup Pin Enable For LLWU_P2
- uint8_t WUPE3 : 2; //!< [7:6] Wakeup Pin Enable For LLWU_P3
- } B;
-} hw_llwu_pe1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire LLWU_PE1 register
- */
-//@{
-#define HW_LLWU_PE1_ADDR (REGS_LLWU_BASE + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_LLWU_PE1 (*(__IO hw_llwu_pe1_t *) HW_LLWU_PE1_ADDR)
-#define HW_LLWU_PE1_RD() (HW_LLWU_PE1.U)
-#define HW_LLWU_PE1_WR(v) (HW_LLWU_PE1.U = (v))
-#define HW_LLWU_PE1_SET(v) (HW_LLWU_PE1_WR(HW_LLWU_PE1_RD() | (v)))
-#define HW_LLWU_PE1_CLR(v) (HW_LLWU_PE1_WR(HW_LLWU_PE1_RD() & ~(v)))
-#define HW_LLWU_PE1_TOG(v) (HW_LLWU_PE1_WR(HW_LLWU_PE1_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual LLWU_PE1 bitfields
- */
-
-/*!
- * @name Register LLWU_PE1, field WUPE0[1:0] (RW)
- *
- * Enables and configures the edge detection for the wakeup pin.
- *
- * Values:
- * - 00 - External input pin disabled as wakeup input
- * - 01 - External input pin enabled with rising edge detection
- * - 10 - External input pin enabled with falling edge detection
- * - 11 - External input pin enabled with any change detection
- */
-//@{
-#define BP_LLWU_PE1_WUPE0 (0U) //!< Bit position for LLWU_PE1_WUPE0.
-#define BM_LLWU_PE1_WUPE0 (0x03U) //!< Bit mask for LLWU_PE1_WUPE0.
-#define BS_LLWU_PE1_WUPE0 (2U) //!< Bit field size in bits for LLWU_PE1_WUPE0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_PE1_WUPE0 field.
-#define BR_LLWU_PE1_WUPE0 (HW_LLWU_PE1.B.WUPE0)
-#endif
-
-//! @brief Format value for bitfield LLWU_PE1_WUPE0.
-#define BF_LLWU_PE1_WUPE0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE1_WUPE0), uint8_t) & BM_LLWU_PE1_WUPE0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUPE0 field to a new value.
-#define BW_LLWU_PE1_WUPE0(v) (HW_LLWU_PE1_WR((HW_LLWU_PE1_RD() & ~BM_LLWU_PE1_WUPE0) | BF_LLWU_PE1_WUPE0(v)))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_PE1, field WUPE1[3:2] (RW)
- *
- * Enables and configures the edge detection for the wakeup pin.
- *
- * Values:
- * - 00 - External input pin disabled as wakeup input
- * - 01 - External input pin enabled with rising edge detection
- * - 10 - External input pin enabled with falling edge detection
- * - 11 - External input pin enabled with any change detection
- */
-//@{
-#define BP_LLWU_PE1_WUPE1 (2U) //!< Bit position for LLWU_PE1_WUPE1.
-#define BM_LLWU_PE1_WUPE1 (0x0CU) //!< Bit mask for LLWU_PE1_WUPE1.
-#define BS_LLWU_PE1_WUPE1 (2U) //!< Bit field size in bits for LLWU_PE1_WUPE1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_PE1_WUPE1 field.
-#define BR_LLWU_PE1_WUPE1 (HW_LLWU_PE1.B.WUPE1)
-#endif
-
-//! @brief Format value for bitfield LLWU_PE1_WUPE1.
-#define BF_LLWU_PE1_WUPE1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE1_WUPE1), uint8_t) & BM_LLWU_PE1_WUPE1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUPE1 field to a new value.
-#define BW_LLWU_PE1_WUPE1(v) (HW_LLWU_PE1_WR((HW_LLWU_PE1_RD() & ~BM_LLWU_PE1_WUPE1) | BF_LLWU_PE1_WUPE1(v)))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_PE1, field WUPE2[5:4] (RW)
- *
- * Enables and configures the edge detection for the wakeup pin.
- *
- * Values:
- * - 00 - External input pin disabled as wakeup input
- * - 01 - External input pin enabled with rising edge detection
- * - 10 - External input pin enabled with falling edge detection
- * - 11 - External input pin enabled with any change detection
- */
-//@{
-#define BP_LLWU_PE1_WUPE2 (4U) //!< Bit position for LLWU_PE1_WUPE2.
-#define BM_LLWU_PE1_WUPE2 (0x30U) //!< Bit mask for LLWU_PE1_WUPE2.
-#define BS_LLWU_PE1_WUPE2 (2U) //!< Bit field size in bits for LLWU_PE1_WUPE2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_PE1_WUPE2 field.
-#define BR_LLWU_PE1_WUPE2 (HW_LLWU_PE1.B.WUPE2)
-#endif
-
-//! @brief Format value for bitfield LLWU_PE1_WUPE2.
-#define BF_LLWU_PE1_WUPE2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE1_WUPE2), uint8_t) & BM_LLWU_PE1_WUPE2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUPE2 field to a new value.
-#define BW_LLWU_PE1_WUPE2(v) (HW_LLWU_PE1_WR((HW_LLWU_PE1_RD() & ~BM_LLWU_PE1_WUPE2) | BF_LLWU_PE1_WUPE2(v)))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_PE1, field WUPE3[7:6] (RW)
- *
- * Enables and configures the edge detection for the wakeup pin.
- *
- * Values:
- * - 00 - External input pin disabled as wakeup input
- * - 01 - External input pin enabled with rising edge detection
- * - 10 - External input pin enabled with falling edge detection
- * - 11 - External input pin enabled with any change detection
- */
-//@{
-#define BP_LLWU_PE1_WUPE3 (6U) //!< Bit position for LLWU_PE1_WUPE3.
-#define BM_LLWU_PE1_WUPE3 (0xC0U) //!< Bit mask for LLWU_PE1_WUPE3.
-#define BS_LLWU_PE1_WUPE3 (2U) //!< Bit field size in bits for LLWU_PE1_WUPE3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_PE1_WUPE3 field.
-#define BR_LLWU_PE1_WUPE3 (HW_LLWU_PE1.B.WUPE3)
-#endif
-
-//! @brief Format value for bitfield LLWU_PE1_WUPE3.
-#define BF_LLWU_PE1_WUPE3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE1_WUPE3), uint8_t) & BM_LLWU_PE1_WUPE3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUPE3 field to a new value.
-#define BW_LLWU_PE1_WUPE3(v) (HW_LLWU_PE1_WR((HW_LLWU_PE1_RD() & ~BM_LLWU_PE1_WUPE3) | BF_LLWU_PE1_WUPE3(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_LLWU_PE2 - LLWU Pin Enable 2 register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_LLWU_PE2 - LLWU Pin Enable 2 register (RW)
- *
- * Reset value: 0x00U
- *
- * LLWU_PE2 contains the field to enable and select the edge detect type for the
- * external wakeup input pins LLWU_P7-LLWU_P4. This register is reset on Chip
- * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
- * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
- * IntroductionInformation found here describes the registers of the Reset Control Module
- * (RCM). The RCM implements many of the reset functions for the chip. See the
- * chip's reset chapter for more information. details for more information.
- */
-typedef union _hw_llwu_pe2
-{
- uint8_t U;
- struct _hw_llwu_pe2_bitfields
- {
- uint8_t WUPE4 : 2; //!< [1:0] Wakeup Pin Enable For LLWU_P4
- uint8_t WUPE5 : 2; //!< [3:2] Wakeup Pin Enable For LLWU_P5
- uint8_t WUPE6 : 2; //!< [5:4] Wakeup Pin Enable For LLWU_P6
- uint8_t WUPE7 : 2; //!< [7:6] Wakeup Pin Enable For LLWU_P7
- } B;
-} hw_llwu_pe2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire LLWU_PE2 register
- */
-//@{
-#define HW_LLWU_PE2_ADDR (REGS_LLWU_BASE + 0x1U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_LLWU_PE2 (*(__IO hw_llwu_pe2_t *) HW_LLWU_PE2_ADDR)
-#define HW_LLWU_PE2_RD() (HW_LLWU_PE2.U)
-#define HW_LLWU_PE2_WR(v) (HW_LLWU_PE2.U = (v))
-#define HW_LLWU_PE2_SET(v) (HW_LLWU_PE2_WR(HW_LLWU_PE2_RD() | (v)))
-#define HW_LLWU_PE2_CLR(v) (HW_LLWU_PE2_WR(HW_LLWU_PE2_RD() & ~(v)))
-#define HW_LLWU_PE2_TOG(v) (HW_LLWU_PE2_WR(HW_LLWU_PE2_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual LLWU_PE2 bitfields
- */
-
-/*!
- * @name Register LLWU_PE2, field WUPE4[1:0] (RW)
- *
- * Enables and configures the edge detection for the wakeup pin.
- *
- * Values:
- * - 00 - External input pin disabled as wakeup input
- * - 01 - External input pin enabled with rising edge detection
- * - 10 - External input pin enabled with falling edge detection
- * - 11 - External input pin enabled with any change detection
- */
-//@{
-#define BP_LLWU_PE2_WUPE4 (0U) //!< Bit position for LLWU_PE2_WUPE4.
-#define BM_LLWU_PE2_WUPE4 (0x03U) //!< Bit mask for LLWU_PE2_WUPE4.
-#define BS_LLWU_PE2_WUPE4 (2U) //!< Bit field size in bits for LLWU_PE2_WUPE4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_PE2_WUPE4 field.
-#define BR_LLWU_PE2_WUPE4 (HW_LLWU_PE2.B.WUPE4)
-#endif
-
-//! @brief Format value for bitfield LLWU_PE2_WUPE4.
-#define BF_LLWU_PE2_WUPE4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE2_WUPE4), uint8_t) & BM_LLWU_PE2_WUPE4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUPE4 field to a new value.
-#define BW_LLWU_PE2_WUPE4(v) (HW_LLWU_PE2_WR((HW_LLWU_PE2_RD() & ~BM_LLWU_PE2_WUPE4) | BF_LLWU_PE2_WUPE4(v)))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_PE2, field WUPE5[3:2] (RW)
- *
- * Enables and configures the edge detection for the wakeup pin.
- *
- * Values:
- * - 00 - External input pin disabled as wakeup input
- * - 01 - External input pin enabled with rising edge detection
- * - 10 - External input pin enabled with falling edge detection
- * - 11 - External input pin enabled with any change detection
- */
-//@{
-#define BP_LLWU_PE2_WUPE5 (2U) //!< Bit position for LLWU_PE2_WUPE5.
-#define BM_LLWU_PE2_WUPE5 (0x0CU) //!< Bit mask for LLWU_PE2_WUPE5.
-#define BS_LLWU_PE2_WUPE5 (2U) //!< Bit field size in bits for LLWU_PE2_WUPE5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_PE2_WUPE5 field.
-#define BR_LLWU_PE2_WUPE5 (HW_LLWU_PE2.B.WUPE5)
-#endif
-
-//! @brief Format value for bitfield LLWU_PE2_WUPE5.
-#define BF_LLWU_PE2_WUPE5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE2_WUPE5), uint8_t) & BM_LLWU_PE2_WUPE5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUPE5 field to a new value.
-#define BW_LLWU_PE2_WUPE5(v) (HW_LLWU_PE2_WR((HW_LLWU_PE2_RD() & ~BM_LLWU_PE2_WUPE5) | BF_LLWU_PE2_WUPE5(v)))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_PE2, field WUPE6[5:4] (RW)
- *
- * Enables and configures the edge detection for the wakeup pin.
- *
- * Values:
- * - 00 - External input pin disabled as wakeup input
- * - 01 - External input pin enabled with rising edge detection
- * - 10 - External input pin enabled with falling edge detection
- * - 11 - External input pin enabled with any change detection
- */
-//@{
-#define BP_LLWU_PE2_WUPE6 (4U) //!< Bit position for LLWU_PE2_WUPE6.
-#define BM_LLWU_PE2_WUPE6 (0x30U) //!< Bit mask for LLWU_PE2_WUPE6.
-#define BS_LLWU_PE2_WUPE6 (2U) //!< Bit field size in bits for LLWU_PE2_WUPE6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_PE2_WUPE6 field.
-#define BR_LLWU_PE2_WUPE6 (HW_LLWU_PE2.B.WUPE6)
-#endif
-
-//! @brief Format value for bitfield LLWU_PE2_WUPE6.
-#define BF_LLWU_PE2_WUPE6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE2_WUPE6), uint8_t) & BM_LLWU_PE2_WUPE6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUPE6 field to a new value.
-#define BW_LLWU_PE2_WUPE6(v) (HW_LLWU_PE2_WR((HW_LLWU_PE2_RD() & ~BM_LLWU_PE2_WUPE6) | BF_LLWU_PE2_WUPE6(v)))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_PE2, field WUPE7[7:6] (RW)
- *
- * Enables and configures the edge detection for the wakeup pin.
- *
- * Values:
- * - 00 - External input pin disabled as wakeup input
- * - 01 - External input pin enabled with rising edge detection
- * - 10 - External input pin enabled with falling edge detection
- * - 11 - External input pin enabled with any change detection
- */
-//@{
-#define BP_LLWU_PE2_WUPE7 (6U) //!< Bit position for LLWU_PE2_WUPE7.
-#define BM_LLWU_PE2_WUPE7 (0xC0U) //!< Bit mask for LLWU_PE2_WUPE7.
-#define BS_LLWU_PE2_WUPE7 (2U) //!< Bit field size in bits for LLWU_PE2_WUPE7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_PE2_WUPE7 field.
-#define BR_LLWU_PE2_WUPE7 (HW_LLWU_PE2.B.WUPE7)
-#endif
-
-//! @brief Format value for bitfield LLWU_PE2_WUPE7.
-#define BF_LLWU_PE2_WUPE7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE2_WUPE7), uint8_t) & BM_LLWU_PE2_WUPE7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUPE7 field to a new value.
-#define BW_LLWU_PE2_WUPE7(v) (HW_LLWU_PE2_WR((HW_LLWU_PE2_RD() & ~BM_LLWU_PE2_WUPE7) | BF_LLWU_PE2_WUPE7(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_LLWU_PE3 - LLWU Pin Enable 3 register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_LLWU_PE3 - LLWU Pin Enable 3 register (RW)
- *
- * Reset value: 0x00U
- *
- * LLWU_PE3 contains the field to enable and select the edge detect type for the
- * external wakeup input pins LLWU_P11-LLWU_P8. This register is reset on Chip
- * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
- * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
- * IntroductionInformation found here describes the registers of the Reset Control Module
- * (RCM). The RCM implements many of the reset functions for the chip. See the
- * chip's reset chapter for more information. details for more information.
- */
-typedef union _hw_llwu_pe3
-{
- uint8_t U;
- struct _hw_llwu_pe3_bitfields
- {
- uint8_t WUPE8 : 2; //!< [1:0] Wakeup Pin Enable For LLWU_P8
- uint8_t WUPE9 : 2; //!< [3:2] Wakeup Pin Enable For LLWU_P9
- uint8_t WUPE10 : 2; //!< [5:4] Wakeup Pin Enable For LLWU_P10
- uint8_t WUPE11 : 2; //!< [7:6] Wakeup Pin Enable For LLWU_P11
- } B;
-} hw_llwu_pe3_t;
-#endif
-
-/*!
- * @name Constants and macros for entire LLWU_PE3 register
- */
-//@{
-#define HW_LLWU_PE3_ADDR (REGS_LLWU_BASE + 0x2U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_LLWU_PE3 (*(__IO hw_llwu_pe3_t *) HW_LLWU_PE3_ADDR)
-#define HW_LLWU_PE3_RD() (HW_LLWU_PE3.U)
-#define HW_LLWU_PE3_WR(v) (HW_LLWU_PE3.U = (v))
-#define HW_LLWU_PE3_SET(v) (HW_LLWU_PE3_WR(HW_LLWU_PE3_RD() | (v)))
-#define HW_LLWU_PE3_CLR(v) (HW_LLWU_PE3_WR(HW_LLWU_PE3_RD() & ~(v)))
-#define HW_LLWU_PE3_TOG(v) (HW_LLWU_PE3_WR(HW_LLWU_PE3_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual LLWU_PE3 bitfields
- */
-
-/*!
- * @name Register LLWU_PE3, field WUPE8[1:0] (RW)
- *
- * Enables and configures the edge detection for the wakeup pin.
- *
- * Values:
- * - 00 - External input pin disabled as wakeup input
- * - 01 - External input pin enabled with rising edge detection
- * - 10 - External input pin enabled with falling edge detection
- * - 11 - External input pin enabled with any change detection
- */
-//@{
-#define BP_LLWU_PE3_WUPE8 (0U) //!< Bit position for LLWU_PE3_WUPE8.
-#define BM_LLWU_PE3_WUPE8 (0x03U) //!< Bit mask for LLWU_PE3_WUPE8.
-#define BS_LLWU_PE3_WUPE8 (2U) //!< Bit field size in bits for LLWU_PE3_WUPE8.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_PE3_WUPE8 field.
-#define BR_LLWU_PE3_WUPE8 (HW_LLWU_PE3.B.WUPE8)
-#endif
-
-//! @brief Format value for bitfield LLWU_PE3_WUPE8.
-#define BF_LLWU_PE3_WUPE8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE3_WUPE8), uint8_t) & BM_LLWU_PE3_WUPE8)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUPE8 field to a new value.
-#define BW_LLWU_PE3_WUPE8(v) (HW_LLWU_PE3_WR((HW_LLWU_PE3_RD() & ~BM_LLWU_PE3_WUPE8) | BF_LLWU_PE3_WUPE8(v)))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_PE3, field WUPE9[3:2] (RW)
- *
- * Enables and configures the edge detection for the wakeup pin.
- *
- * Values:
- * - 00 - External input pin disabled as wakeup input
- * - 01 - External input pin enabled with rising edge detection
- * - 10 - External input pin enabled with falling edge detection
- * - 11 - External input pin enabled with any change detection
- */
-//@{
-#define BP_LLWU_PE3_WUPE9 (2U) //!< Bit position for LLWU_PE3_WUPE9.
-#define BM_LLWU_PE3_WUPE9 (0x0CU) //!< Bit mask for LLWU_PE3_WUPE9.
-#define BS_LLWU_PE3_WUPE9 (2U) //!< Bit field size in bits for LLWU_PE3_WUPE9.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_PE3_WUPE9 field.
-#define BR_LLWU_PE3_WUPE9 (HW_LLWU_PE3.B.WUPE9)
-#endif
-
-//! @brief Format value for bitfield LLWU_PE3_WUPE9.
-#define BF_LLWU_PE3_WUPE9(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE3_WUPE9), uint8_t) & BM_LLWU_PE3_WUPE9)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUPE9 field to a new value.
-#define BW_LLWU_PE3_WUPE9(v) (HW_LLWU_PE3_WR((HW_LLWU_PE3_RD() & ~BM_LLWU_PE3_WUPE9) | BF_LLWU_PE3_WUPE9(v)))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_PE3, field WUPE10[5:4] (RW)
- *
- * Enables and configures the edge detection for the wakeup pin.
- *
- * Values:
- * - 00 - External input pin disabled as wakeup input
- * - 01 - External input pin enabled with rising edge detection
- * - 10 - External input pin enabled with falling edge detection
- * - 11 - External input pin enabled with any change detection
- */
-//@{
-#define BP_LLWU_PE3_WUPE10 (4U) //!< Bit position for LLWU_PE3_WUPE10.
-#define BM_LLWU_PE3_WUPE10 (0x30U) //!< Bit mask for LLWU_PE3_WUPE10.
-#define BS_LLWU_PE3_WUPE10 (2U) //!< Bit field size in bits for LLWU_PE3_WUPE10.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_PE3_WUPE10 field.
-#define BR_LLWU_PE3_WUPE10 (HW_LLWU_PE3.B.WUPE10)
-#endif
-
-//! @brief Format value for bitfield LLWU_PE3_WUPE10.
-#define BF_LLWU_PE3_WUPE10(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE3_WUPE10), uint8_t) & BM_LLWU_PE3_WUPE10)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUPE10 field to a new value.
-#define BW_LLWU_PE3_WUPE10(v) (HW_LLWU_PE3_WR((HW_LLWU_PE3_RD() & ~BM_LLWU_PE3_WUPE10) | BF_LLWU_PE3_WUPE10(v)))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_PE3, field WUPE11[7:6] (RW)
- *
- * Enables and configures the edge detection for the wakeup pin.
- *
- * Values:
- * - 00 - External input pin disabled as wakeup input
- * - 01 - External input pin enabled with rising edge detection
- * - 10 - External input pin enabled with falling edge detection
- * - 11 - External input pin enabled with any change detection
- */
-//@{
-#define BP_LLWU_PE3_WUPE11 (6U) //!< Bit position for LLWU_PE3_WUPE11.
-#define BM_LLWU_PE3_WUPE11 (0xC0U) //!< Bit mask for LLWU_PE3_WUPE11.
-#define BS_LLWU_PE3_WUPE11 (2U) //!< Bit field size in bits for LLWU_PE3_WUPE11.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_PE3_WUPE11 field.
-#define BR_LLWU_PE3_WUPE11 (HW_LLWU_PE3.B.WUPE11)
-#endif
-
-//! @brief Format value for bitfield LLWU_PE3_WUPE11.
-#define BF_LLWU_PE3_WUPE11(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE3_WUPE11), uint8_t) & BM_LLWU_PE3_WUPE11)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUPE11 field to a new value.
-#define BW_LLWU_PE3_WUPE11(v) (HW_LLWU_PE3_WR((HW_LLWU_PE3_RD() & ~BM_LLWU_PE3_WUPE11) | BF_LLWU_PE3_WUPE11(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_LLWU_PE4 - LLWU Pin Enable 4 register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_LLWU_PE4 - LLWU Pin Enable 4 register (RW)
- *
- * Reset value: 0x00U
- *
- * LLWU_PE4 contains the field to enable and select the edge detect type for the
- * external wakeup input pins LLWU_P15-LLWU_P12. This register is reset on Chip
- * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
- * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
- * IntroductionInformation found here describes the registers of the Reset Control
- * Module (RCM). The RCM implements many of the reset functions for the chip. See the
- * chip's reset chapter for more information. details for more information.
- */
-typedef union _hw_llwu_pe4
-{
- uint8_t U;
- struct _hw_llwu_pe4_bitfields
- {
- uint8_t WUPE12 : 2; //!< [1:0] Wakeup Pin Enable For LLWU_P12
- uint8_t WUPE13 : 2; //!< [3:2] Wakeup Pin Enable For LLWU_P13
- uint8_t WUPE14 : 2; //!< [5:4] Wakeup Pin Enable For LLWU_P14
- uint8_t WUPE15 : 2; //!< [7:6] Wakeup Pin Enable For LLWU_P15
- } B;
-} hw_llwu_pe4_t;
-#endif
-
-/*!
- * @name Constants and macros for entire LLWU_PE4 register
- */
-//@{
-#define HW_LLWU_PE4_ADDR (REGS_LLWU_BASE + 0x3U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_LLWU_PE4 (*(__IO hw_llwu_pe4_t *) HW_LLWU_PE4_ADDR)
-#define HW_LLWU_PE4_RD() (HW_LLWU_PE4.U)
-#define HW_LLWU_PE4_WR(v) (HW_LLWU_PE4.U = (v))
-#define HW_LLWU_PE4_SET(v) (HW_LLWU_PE4_WR(HW_LLWU_PE4_RD() | (v)))
-#define HW_LLWU_PE4_CLR(v) (HW_LLWU_PE4_WR(HW_LLWU_PE4_RD() & ~(v)))
-#define HW_LLWU_PE4_TOG(v) (HW_LLWU_PE4_WR(HW_LLWU_PE4_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual LLWU_PE4 bitfields
- */
-
-/*!
- * @name Register LLWU_PE4, field WUPE12[1:0] (RW)
- *
- * Enables and configures the edge detection for the wakeup pin.
- *
- * Values:
- * - 00 - External input pin disabled as wakeup input
- * - 01 - External input pin enabled with rising edge detection
- * - 10 - External input pin enabled with falling edge detection
- * - 11 - External input pin enabled with any change detection
- */
-//@{
-#define BP_LLWU_PE4_WUPE12 (0U) //!< Bit position for LLWU_PE4_WUPE12.
-#define BM_LLWU_PE4_WUPE12 (0x03U) //!< Bit mask for LLWU_PE4_WUPE12.
-#define BS_LLWU_PE4_WUPE12 (2U) //!< Bit field size in bits for LLWU_PE4_WUPE12.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_PE4_WUPE12 field.
-#define BR_LLWU_PE4_WUPE12 (HW_LLWU_PE4.B.WUPE12)
-#endif
-
-//! @brief Format value for bitfield LLWU_PE4_WUPE12.
-#define BF_LLWU_PE4_WUPE12(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE4_WUPE12), uint8_t) & BM_LLWU_PE4_WUPE12)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUPE12 field to a new value.
-#define BW_LLWU_PE4_WUPE12(v) (HW_LLWU_PE4_WR((HW_LLWU_PE4_RD() & ~BM_LLWU_PE4_WUPE12) | BF_LLWU_PE4_WUPE12(v)))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_PE4, field WUPE13[3:2] (RW)
- *
- * Enables and configures the edge detection for the wakeup pin.
- *
- * Values:
- * - 00 - External input pin disabled as wakeup input
- * - 01 - External input pin enabled with rising edge detection
- * - 10 - External input pin enabled with falling edge detection
- * - 11 - External input pin enabled with any change detection
- */
-//@{
-#define BP_LLWU_PE4_WUPE13 (2U) //!< Bit position for LLWU_PE4_WUPE13.
-#define BM_LLWU_PE4_WUPE13 (0x0CU) //!< Bit mask for LLWU_PE4_WUPE13.
-#define BS_LLWU_PE4_WUPE13 (2U) //!< Bit field size in bits for LLWU_PE4_WUPE13.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_PE4_WUPE13 field.
-#define BR_LLWU_PE4_WUPE13 (HW_LLWU_PE4.B.WUPE13)
-#endif
-
-//! @brief Format value for bitfield LLWU_PE4_WUPE13.
-#define BF_LLWU_PE4_WUPE13(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE4_WUPE13), uint8_t) & BM_LLWU_PE4_WUPE13)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUPE13 field to a new value.
-#define BW_LLWU_PE4_WUPE13(v) (HW_LLWU_PE4_WR((HW_LLWU_PE4_RD() & ~BM_LLWU_PE4_WUPE13) | BF_LLWU_PE4_WUPE13(v)))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_PE4, field WUPE14[5:4] (RW)
- *
- * Enables and configures the edge detection for the wakeup pin.
- *
- * Values:
- * - 00 - External input pin disabled as wakeup input
- * - 01 - External input pin enabled with rising edge detection
- * - 10 - External input pin enabled with falling edge detection
- * - 11 - External input pin enabled with any change detection
- */
-//@{
-#define BP_LLWU_PE4_WUPE14 (4U) //!< Bit position for LLWU_PE4_WUPE14.
-#define BM_LLWU_PE4_WUPE14 (0x30U) //!< Bit mask for LLWU_PE4_WUPE14.
-#define BS_LLWU_PE4_WUPE14 (2U) //!< Bit field size in bits for LLWU_PE4_WUPE14.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_PE4_WUPE14 field.
-#define BR_LLWU_PE4_WUPE14 (HW_LLWU_PE4.B.WUPE14)
-#endif
-
-//! @brief Format value for bitfield LLWU_PE4_WUPE14.
-#define BF_LLWU_PE4_WUPE14(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE4_WUPE14), uint8_t) & BM_LLWU_PE4_WUPE14)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUPE14 field to a new value.
-#define BW_LLWU_PE4_WUPE14(v) (HW_LLWU_PE4_WR((HW_LLWU_PE4_RD() & ~BM_LLWU_PE4_WUPE14) | BF_LLWU_PE4_WUPE14(v)))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_PE4, field WUPE15[7:6] (RW)
- *
- * Enables and configures the edge detection for the wakeup pin.
- *
- * Values:
- * - 00 - External input pin disabled as wakeup input
- * - 01 - External input pin enabled with rising edge detection
- * - 10 - External input pin enabled with falling edge detection
- * - 11 - External input pin enabled with any change detection
- */
-//@{
-#define BP_LLWU_PE4_WUPE15 (6U) //!< Bit position for LLWU_PE4_WUPE15.
-#define BM_LLWU_PE4_WUPE15 (0xC0U) //!< Bit mask for LLWU_PE4_WUPE15.
-#define BS_LLWU_PE4_WUPE15 (2U) //!< Bit field size in bits for LLWU_PE4_WUPE15.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_PE4_WUPE15 field.
-#define BR_LLWU_PE4_WUPE15 (HW_LLWU_PE4.B.WUPE15)
-#endif
-
-//! @brief Format value for bitfield LLWU_PE4_WUPE15.
-#define BF_LLWU_PE4_WUPE15(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE4_WUPE15), uint8_t) & BM_LLWU_PE4_WUPE15)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUPE15 field to a new value.
-#define BW_LLWU_PE4_WUPE15(v) (HW_LLWU_PE4_WR((HW_LLWU_PE4_RD() & ~BM_LLWU_PE4_WUPE15) | BF_LLWU_PE4_WUPE15(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_LLWU_ME - LLWU Module Enable register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_LLWU_ME - LLWU Module Enable register (RW)
- *
- * Reset value: 0x00U
- *
- * LLWU_ME contains the bits to enable the internal module flag as a wakeup
- * input source for inputs MWUF7-MWUF0. This register is reset on Chip Reset not VLLS
- * and by reset types that trigger Chip Reset not VLLS. It is unaffected by
- * reset types that do not trigger Chip Reset not VLLS. See the
- * IntroductionInformation found here describes the registers of the Reset Control Module (RCM). The
- * RCM implements many of the reset functions for the chip. See the chip's reset
- * chapter for more information. details for more information.
- */
-typedef union _hw_llwu_me
-{
- uint8_t U;
- struct _hw_llwu_me_bitfields
- {
- uint8_t WUME0 : 1; //!< [0] Wakeup Module Enable For Module 0
- uint8_t WUME1 : 1; //!< [1] Wakeup Module Enable for Module 1
- uint8_t WUME2 : 1; //!< [2] Wakeup Module Enable For Module 2
- uint8_t WUME3 : 1; //!< [3] Wakeup Module Enable For Module 3
- uint8_t WUME4 : 1; //!< [4] Wakeup Module Enable For Module 4
- uint8_t WUME5 : 1; //!< [5] Wakeup Module Enable For Module 5
- uint8_t WUME6 : 1; //!< [6] Wakeup Module Enable For Module 6
- uint8_t WUME7 : 1; //!< [7] Wakeup Module Enable For Module 7
- } B;
-} hw_llwu_me_t;
-#endif
-
-/*!
- * @name Constants and macros for entire LLWU_ME register
- */
-//@{
-#define HW_LLWU_ME_ADDR (REGS_LLWU_BASE + 0x4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_LLWU_ME (*(__IO hw_llwu_me_t *) HW_LLWU_ME_ADDR)
-#define HW_LLWU_ME_RD() (HW_LLWU_ME.U)
-#define HW_LLWU_ME_WR(v) (HW_LLWU_ME.U = (v))
-#define HW_LLWU_ME_SET(v) (HW_LLWU_ME_WR(HW_LLWU_ME_RD() | (v)))
-#define HW_LLWU_ME_CLR(v) (HW_LLWU_ME_WR(HW_LLWU_ME_RD() & ~(v)))
-#define HW_LLWU_ME_TOG(v) (HW_LLWU_ME_WR(HW_LLWU_ME_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual LLWU_ME bitfields
- */
-
-/*!
- * @name Register LLWU_ME, field WUME0[0] (RW)
- *
- * Enables an internal module as a wakeup source input.
- *
- * Values:
- * - 0 - Internal module flag not used as wakeup source
- * - 1 - Internal module flag used as wakeup source
- */
-//@{
-#define BP_LLWU_ME_WUME0 (0U) //!< Bit position for LLWU_ME_WUME0.
-#define BM_LLWU_ME_WUME0 (0x01U) //!< Bit mask for LLWU_ME_WUME0.
-#define BS_LLWU_ME_WUME0 (1U) //!< Bit field size in bits for LLWU_ME_WUME0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_ME_WUME0 field.
-#define BR_LLWU_ME_WUME0 (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME0))
-#endif
-
-//! @brief Format value for bitfield LLWU_ME_WUME0.
-#define BF_LLWU_ME_WUME0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME0), uint8_t) & BM_LLWU_ME_WUME0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUME0 field to a new value.
-#define BW_LLWU_ME_WUME0(v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_ME, field WUME1[1] (RW)
- *
- * Enables an internal module as a wakeup source input.
- *
- * Values:
- * - 0 - Internal module flag not used as wakeup source
- * - 1 - Internal module flag used as wakeup source
- */
-//@{
-#define BP_LLWU_ME_WUME1 (1U) //!< Bit position for LLWU_ME_WUME1.
-#define BM_LLWU_ME_WUME1 (0x02U) //!< Bit mask for LLWU_ME_WUME1.
-#define BS_LLWU_ME_WUME1 (1U) //!< Bit field size in bits for LLWU_ME_WUME1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_ME_WUME1 field.
-#define BR_LLWU_ME_WUME1 (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME1))
-#endif
-
-//! @brief Format value for bitfield LLWU_ME_WUME1.
-#define BF_LLWU_ME_WUME1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME1), uint8_t) & BM_LLWU_ME_WUME1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUME1 field to a new value.
-#define BW_LLWU_ME_WUME1(v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_ME, field WUME2[2] (RW)
- *
- * Enables an internal module as a wakeup source input.
- *
- * Values:
- * - 0 - Internal module flag not used as wakeup source
- * - 1 - Internal module flag used as wakeup source
- */
-//@{
-#define BP_LLWU_ME_WUME2 (2U) //!< Bit position for LLWU_ME_WUME2.
-#define BM_LLWU_ME_WUME2 (0x04U) //!< Bit mask for LLWU_ME_WUME2.
-#define BS_LLWU_ME_WUME2 (1U) //!< Bit field size in bits for LLWU_ME_WUME2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_ME_WUME2 field.
-#define BR_LLWU_ME_WUME2 (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME2))
-#endif
-
-//! @brief Format value for bitfield LLWU_ME_WUME2.
-#define BF_LLWU_ME_WUME2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME2), uint8_t) & BM_LLWU_ME_WUME2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUME2 field to a new value.
-#define BW_LLWU_ME_WUME2(v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_ME, field WUME3[3] (RW)
- *
- * Enables an internal module as a wakeup source input.
- *
- * Values:
- * - 0 - Internal module flag not used as wakeup source
- * - 1 - Internal module flag used as wakeup source
- */
-//@{
-#define BP_LLWU_ME_WUME3 (3U) //!< Bit position for LLWU_ME_WUME3.
-#define BM_LLWU_ME_WUME3 (0x08U) //!< Bit mask for LLWU_ME_WUME3.
-#define BS_LLWU_ME_WUME3 (1U) //!< Bit field size in bits for LLWU_ME_WUME3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_ME_WUME3 field.
-#define BR_LLWU_ME_WUME3 (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME3))
-#endif
-
-//! @brief Format value for bitfield LLWU_ME_WUME3.
-#define BF_LLWU_ME_WUME3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME3), uint8_t) & BM_LLWU_ME_WUME3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUME3 field to a new value.
-#define BW_LLWU_ME_WUME3(v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_ME, field WUME4[4] (RW)
- *
- * Enables an internal module as a wakeup source input.
- *
- * Values:
- * - 0 - Internal module flag not used as wakeup source
- * - 1 - Internal module flag used as wakeup source
- */
-//@{
-#define BP_LLWU_ME_WUME4 (4U) //!< Bit position for LLWU_ME_WUME4.
-#define BM_LLWU_ME_WUME4 (0x10U) //!< Bit mask for LLWU_ME_WUME4.
-#define BS_LLWU_ME_WUME4 (1U) //!< Bit field size in bits for LLWU_ME_WUME4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_ME_WUME4 field.
-#define BR_LLWU_ME_WUME4 (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME4))
-#endif
-
-//! @brief Format value for bitfield LLWU_ME_WUME4.
-#define BF_LLWU_ME_WUME4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME4), uint8_t) & BM_LLWU_ME_WUME4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUME4 field to a new value.
-#define BW_LLWU_ME_WUME4(v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_ME, field WUME5[5] (RW)
- *
- * Enables an internal module as a wakeup source input.
- *
- * Values:
- * - 0 - Internal module flag not used as wakeup source
- * - 1 - Internal module flag used as wakeup source
- */
-//@{
-#define BP_LLWU_ME_WUME5 (5U) //!< Bit position for LLWU_ME_WUME5.
-#define BM_LLWU_ME_WUME5 (0x20U) //!< Bit mask for LLWU_ME_WUME5.
-#define BS_LLWU_ME_WUME5 (1U) //!< Bit field size in bits for LLWU_ME_WUME5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_ME_WUME5 field.
-#define BR_LLWU_ME_WUME5 (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME5))
-#endif
-
-//! @brief Format value for bitfield LLWU_ME_WUME5.
-#define BF_LLWU_ME_WUME5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME5), uint8_t) & BM_LLWU_ME_WUME5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUME5 field to a new value.
-#define BW_LLWU_ME_WUME5(v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_ME, field WUME6[6] (RW)
- *
- * Enables an internal module as a wakeup source input.
- *
- * Values:
- * - 0 - Internal module flag not used as wakeup source
- * - 1 - Internal module flag used as wakeup source
- */
-//@{
-#define BP_LLWU_ME_WUME6 (6U) //!< Bit position for LLWU_ME_WUME6.
-#define BM_LLWU_ME_WUME6 (0x40U) //!< Bit mask for LLWU_ME_WUME6.
-#define BS_LLWU_ME_WUME6 (1U) //!< Bit field size in bits for LLWU_ME_WUME6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_ME_WUME6 field.
-#define BR_LLWU_ME_WUME6 (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME6))
-#endif
-
-//! @brief Format value for bitfield LLWU_ME_WUME6.
-#define BF_LLWU_ME_WUME6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME6), uint8_t) & BM_LLWU_ME_WUME6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUME6 field to a new value.
-#define BW_LLWU_ME_WUME6(v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_ME, field WUME7[7] (RW)
- *
- * Enables an internal module as a wakeup source input.
- *
- * Values:
- * - 0 - Internal module flag not used as wakeup source
- * - 1 - Internal module flag used as wakeup source
- */
-//@{
-#define BP_LLWU_ME_WUME7 (7U) //!< Bit position for LLWU_ME_WUME7.
-#define BM_LLWU_ME_WUME7 (0x80U) //!< Bit mask for LLWU_ME_WUME7.
-#define BS_LLWU_ME_WUME7 (1U) //!< Bit field size in bits for LLWU_ME_WUME7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_ME_WUME7 field.
-#define BR_LLWU_ME_WUME7 (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME7))
-#endif
-
-//! @brief Format value for bitfield LLWU_ME_WUME7.
-#define BF_LLWU_ME_WUME7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME7), uint8_t) & BM_LLWU_ME_WUME7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUME7 field to a new value.
-#define BW_LLWU_ME_WUME7(v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME7) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_LLWU_F1 - LLWU Flag 1 register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_LLWU_F1 - LLWU Flag 1 register (W1C)
- *
- * Reset value: 0x00U
- *
- * LLWU_F1 contains the wakeup flags indicating which wakeup source caused the
- * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
- * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
- * external wakeup flags are read-only and clearing a flag is accomplished by a write
- * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
- * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
- * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
- * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
- * IntroductionInformation found here describes the registers of the Reset Control
- * Module (RCM). The RCM implements many of the reset functions for the chip. See the
- * chip's reset chapter for more information. details for more information.
- */
-typedef union _hw_llwu_f1
-{
- uint8_t U;
- struct _hw_llwu_f1_bitfields
- {
- uint8_t WUF0 : 1; //!< [0] Wakeup Flag For LLWU_P0
- uint8_t WUF1 : 1; //!< [1] Wakeup Flag For LLWU_P1
- uint8_t WUF2 : 1; //!< [2] Wakeup Flag For LLWU_P2
- uint8_t WUF3 : 1; //!< [3] Wakeup Flag For LLWU_P3
- uint8_t WUF4 : 1; //!< [4] Wakeup Flag For LLWU_P4
- uint8_t WUF5 : 1; //!< [5] Wakeup Flag For LLWU_P5
- uint8_t WUF6 : 1; //!< [6] Wakeup Flag For LLWU_P6
- uint8_t WUF7 : 1; //!< [7] Wakeup Flag For LLWU_P7
- } B;
-} hw_llwu_f1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire LLWU_F1 register
- */
-//@{
-#define HW_LLWU_F1_ADDR (REGS_LLWU_BASE + 0x5U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_LLWU_F1 (*(__IO hw_llwu_f1_t *) HW_LLWU_F1_ADDR)
-#define HW_LLWU_F1_RD() (HW_LLWU_F1.U)
-#define HW_LLWU_F1_WR(v) (HW_LLWU_F1.U = (v))
-#define HW_LLWU_F1_SET(v) (HW_LLWU_F1_WR(HW_LLWU_F1_RD() | (v)))
-#define HW_LLWU_F1_CLR(v) (HW_LLWU_F1_WR(HW_LLWU_F1_RD() & ~(v)))
-#define HW_LLWU_F1_TOG(v) (HW_LLWU_F1_WR(HW_LLWU_F1_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual LLWU_F1 bitfields
- */
-
-/*!
- * @name Register LLWU_F1, field WUF0[0] (W1C)
- *
- * Indicates that an enabled external wake-up pin was a source of exiting a
- * low-leakage power mode. To clear the flag, write a 1 to WUF0.
- *
- * Values:
- * - 0 - LLWU_P0 input was not a wakeup source
- * - 1 - LLWU_P0 input was a wakeup source
- */
-//@{
-#define BP_LLWU_F1_WUF0 (0U) //!< Bit position for LLWU_F1_WUF0.
-#define BM_LLWU_F1_WUF0 (0x01U) //!< Bit mask for LLWU_F1_WUF0.
-#define BS_LLWU_F1_WUF0 (1U) //!< Bit field size in bits for LLWU_F1_WUF0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_F1_WUF0 field.
-#define BR_LLWU_F1_WUF0 (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF0))
-#endif
-
-//! @brief Format value for bitfield LLWU_F1_WUF0.
-#define BF_LLWU_F1_WUF0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF0), uint8_t) & BM_LLWU_F1_WUF0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUF0 field to a new value.
-#define BW_LLWU_F1_WUF0(v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_F1, field WUF1[1] (W1C)
- *
- * Indicates that an enabled external wakeup pin was a source of exiting a
- * low-leakage power mode. To clear the flag, write a 1 to WUF1.
- *
- * Values:
- * - 0 - LLWU_P1 input was not a wakeup source
- * - 1 - LLWU_P1 input was a wakeup source
- */
-//@{
-#define BP_LLWU_F1_WUF1 (1U) //!< Bit position for LLWU_F1_WUF1.
-#define BM_LLWU_F1_WUF1 (0x02U) //!< Bit mask for LLWU_F1_WUF1.
-#define BS_LLWU_F1_WUF1 (1U) //!< Bit field size in bits for LLWU_F1_WUF1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_F1_WUF1 field.
-#define BR_LLWU_F1_WUF1 (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF1))
-#endif
-
-//! @brief Format value for bitfield LLWU_F1_WUF1.
-#define BF_LLWU_F1_WUF1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF1), uint8_t) & BM_LLWU_F1_WUF1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUF1 field to a new value.
-#define BW_LLWU_F1_WUF1(v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_F1, field WUF2[2] (W1C)
- *
- * Indicates that an enabled external wakeup pin was a source of exiting a
- * low-leakage power mode. To clear the flag, write a 1 to WUF2.
- *
- * Values:
- * - 0 - LLWU_P2 input was not a wakeup source
- * - 1 - LLWU_P2 input was a wakeup source
- */
-//@{
-#define BP_LLWU_F1_WUF2 (2U) //!< Bit position for LLWU_F1_WUF2.
-#define BM_LLWU_F1_WUF2 (0x04U) //!< Bit mask for LLWU_F1_WUF2.
-#define BS_LLWU_F1_WUF2 (1U) //!< Bit field size in bits for LLWU_F1_WUF2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_F1_WUF2 field.
-#define BR_LLWU_F1_WUF2 (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF2))
-#endif
-
-//! @brief Format value for bitfield LLWU_F1_WUF2.
-#define BF_LLWU_F1_WUF2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF2), uint8_t) & BM_LLWU_F1_WUF2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUF2 field to a new value.
-#define BW_LLWU_F1_WUF2(v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_F1, field WUF3[3] (W1C)
- *
- * Indicates that an enabled external wakeup pin was a source of exiting a
- * low-leakage power mode. To clear the flag, write a 1 to WUF3.
- *
- * Values:
- * - 0 - LLWU_P3 input was not a wake-up source
- * - 1 - LLWU_P3 input was a wake-up source
- */
-//@{
-#define BP_LLWU_F1_WUF3 (3U) //!< Bit position for LLWU_F1_WUF3.
-#define BM_LLWU_F1_WUF3 (0x08U) //!< Bit mask for LLWU_F1_WUF3.
-#define BS_LLWU_F1_WUF3 (1U) //!< Bit field size in bits for LLWU_F1_WUF3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_F1_WUF3 field.
-#define BR_LLWU_F1_WUF3 (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF3))
-#endif
-
-//! @brief Format value for bitfield LLWU_F1_WUF3.
-#define BF_LLWU_F1_WUF3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF3), uint8_t) & BM_LLWU_F1_WUF3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUF3 field to a new value.
-#define BW_LLWU_F1_WUF3(v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_F1, field WUF4[4] (W1C)
- *
- * Indicates that an enabled external wake-up pin was a source of exiting a
- * low-leakage power mode. To clear the flag, write a 1 to WUF4.
- *
- * Values:
- * - 0 - LLWU_P4 input was not a wakeup source
- * - 1 - LLWU_P4 input was a wakeup source
- */
-//@{
-#define BP_LLWU_F1_WUF4 (4U) //!< Bit position for LLWU_F1_WUF4.
-#define BM_LLWU_F1_WUF4 (0x10U) //!< Bit mask for LLWU_F1_WUF4.
-#define BS_LLWU_F1_WUF4 (1U) //!< Bit field size in bits for LLWU_F1_WUF4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_F1_WUF4 field.
-#define BR_LLWU_F1_WUF4 (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF4))
-#endif
-
-//! @brief Format value for bitfield LLWU_F1_WUF4.
-#define BF_LLWU_F1_WUF4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF4), uint8_t) & BM_LLWU_F1_WUF4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUF4 field to a new value.
-#define BW_LLWU_F1_WUF4(v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_F1, field WUF5[5] (W1C)
- *
- * Indicates that an enabled external wakeup pin was a source of exiting a
- * low-leakage power mode. To clear the flag, write a 1 to WUF5.
- *
- * Values:
- * - 0 - LLWU_P5 input was not a wakeup source
- * - 1 - LLWU_P5 input was a wakeup source
- */
-//@{
-#define BP_LLWU_F1_WUF5 (5U) //!< Bit position for LLWU_F1_WUF5.
-#define BM_LLWU_F1_WUF5 (0x20U) //!< Bit mask for LLWU_F1_WUF5.
-#define BS_LLWU_F1_WUF5 (1U) //!< Bit field size in bits for LLWU_F1_WUF5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_F1_WUF5 field.
-#define BR_LLWU_F1_WUF5 (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF5))
-#endif
-
-//! @brief Format value for bitfield LLWU_F1_WUF5.
-#define BF_LLWU_F1_WUF5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF5), uint8_t) & BM_LLWU_F1_WUF5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUF5 field to a new value.
-#define BW_LLWU_F1_WUF5(v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF5) = (v))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_F1, field WUF6[6] (W1C)
- *
- * Indicates that an enabled external wakeup pin was a source of exiting a
- * low-leakage power mode. To clear the flag, write a 1 to WUF6.
- *
- * Values:
- * - 0 - LLWU_P6 input was not a wakeup source
- * - 1 - LLWU_P6 input was a wakeup source
- */
-//@{
-#define BP_LLWU_F1_WUF6 (6U) //!< Bit position for LLWU_F1_WUF6.
-#define BM_LLWU_F1_WUF6 (0x40U) //!< Bit mask for LLWU_F1_WUF6.
-#define BS_LLWU_F1_WUF6 (1U) //!< Bit field size in bits for LLWU_F1_WUF6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_F1_WUF6 field.
-#define BR_LLWU_F1_WUF6 (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF6))
-#endif
-
-//! @brief Format value for bitfield LLWU_F1_WUF6.
-#define BF_LLWU_F1_WUF6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF6), uint8_t) & BM_LLWU_F1_WUF6)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUF6 field to a new value.
-#define BW_LLWU_F1_WUF6(v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF6) = (v))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_F1, field WUF7[7] (W1C)
- *
- * Indicates that an enabled external wakeup pin was a source of exiting a
- * low-leakage power mode. To clear the flag, write a 1 to WUF7.
- *
- * Values:
- * - 0 - LLWU_P7 input was not a wakeup source
- * - 1 - LLWU_P7 input was a wakeup source
- */
-//@{
-#define BP_LLWU_F1_WUF7 (7U) //!< Bit position for LLWU_F1_WUF7.
-#define BM_LLWU_F1_WUF7 (0x80U) //!< Bit mask for LLWU_F1_WUF7.
-#define BS_LLWU_F1_WUF7 (1U) //!< Bit field size in bits for LLWU_F1_WUF7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_F1_WUF7 field.
-#define BR_LLWU_F1_WUF7 (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF7))
-#endif
-
-//! @brief Format value for bitfield LLWU_F1_WUF7.
-#define BF_LLWU_F1_WUF7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF7), uint8_t) & BM_LLWU_F1_WUF7)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUF7 field to a new value.
-#define BW_LLWU_F1_WUF7(v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF7) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_LLWU_F2 - LLWU Flag 2 register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_LLWU_F2 - LLWU Flag 2 register (W1C)
- *
- * Reset value: 0x00U
- *
- * LLWU_F2 contains the wakeup flags indicating which wakeup source caused the
- * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
- * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
- * external wakeup flags are read-only and clearing a flag is accomplished by a write
- * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
- * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
- * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
- * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
- * IntroductionInformation found here describes the registers of the Reset Control
- * Module (RCM). The RCM implements many of the reset functions for the chip. See the
- * chip's reset chapter for more information. details for more information.
- */
-typedef union _hw_llwu_f2
-{
- uint8_t U;
- struct _hw_llwu_f2_bitfields
- {
- uint8_t WUF8 : 1; //!< [0] Wakeup Flag For LLWU_P8
- uint8_t WUF9 : 1; //!< [1] Wakeup Flag For LLWU_P9
- uint8_t WUF10 : 1; //!< [2] Wakeup Flag For LLWU_P10
- uint8_t WUF11 : 1; //!< [3] Wakeup Flag For LLWU_P11
- uint8_t WUF12 : 1; //!< [4] Wakeup Flag For LLWU_P12
- uint8_t WUF13 : 1; //!< [5] Wakeup Flag For LLWU_P13
- uint8_t WUF14 : 1; //!< [6] Wakeup Flag For LLWU_P14
- uint8_t WUF15 : 1; //!< [7] Wakeup Flag For LLWU_P15
- } B;
-} hw_llwu_f2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire LLWU_F2 register
- */
-//@{
-#define HW_LLWU_F2_ADDR (REGS_LLWU_BASE + 0x6U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_LLWU_F2 (*(__IO hw_llwu_f2_t *) HW_LLWU_F2_ADDR)
-#define HW_LLWU_F2_RD() (HW_LLWU_F2.U)
-#define HW_LLWU_F2_WR(v) (HW_LLWU_F2.U = (v))
-#define HW_LLWU_F2_SET(v) (HW_LLWU_F2_WR(HW_LLWU_F2_RD() | (v)))
-#define HW_LLWU_F2_CLR(v) (HW_LLWU_F2_WR(HW_LLWU_F2_RD() & ~(v)))
-#define HW_LLWU_F2_TOG(v) (HW_LLWU_F2_WR(HW_LLWU_F2_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual LLWU_F2 bitfields
- */
-
-/*!
- * @name Register LLWU_F2, field WUF8[0] (W1C)
- *
- * Indicates that an enabled external wakeup pin was a source of exiting a
- * low-leakage power mode. To clear the flag, write a 1 to WUF8.
- *
- * Values:
- * - 0 - LLWU_P8 input was not a wakeup source
- * - 1 - LLWU_P8 input was a wakeup source
- */
-//@{
-#define BP_LLWU_F2_WUF8 (0U) //!< Bit position for LLWU_F2_WUF8.
-#define BM_LLWU_F2_WUF8 (0x01U) //!< Bit mask for LLWU_F2_WUF8.
-#define BS_LLWU_F2_WUF8 (1U) //!< Bit field size in bits for LLWU_F2_WUF8.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_F2_WUF8 field.
-#define BR_LLWU_F2_WUF8 (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF8))
-#endif
-
-//! @brief Format value for bitfield LLWU_F2_WUF8.
-#define BF_LLWU_F2_WUF8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF8), uint8_t) & BM_LLWU_F2_WUF8)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUF8 field to a new value.
-#define BW_LLWU_F2_WUF8(v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF8) = (v))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_F2, field WUF9[1] (W1C)
- *
- * Indicates that an enabled external wakeup pin was a source of exiting a
- * low-leakage power mode. To clear the flag, write a 1 to WUF9.
- *
- * Values:
- * - 0 - LLWU_P9 input was not a wakeup source
- * - 1 - LLWU_P9 input was a wakeup source
- */
-//@{
-#define BP_LLWU_F2_WUF9 (1U) //!< Bit position for LLWU_F2_WUF9.
-#define BM_LLWU_F2_WUF9 (0x02U) //!< Bit mask for LLWU_F2_WUF9.
-#define BS_LLWU_F2_WUF9 (1U) //!< Bit field size in bits for LLWU_F2_WUF9.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_F2_WUF9 field.
-#define BR_LLWU_F2_WUF9 (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF9))
-#endif
-
-//! @brief Format value for bitfield LLWU_F2_WUF9.
-#define BF_LLWU_F2_WUF9(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF9), uint8_t) & BM_LLWU_F2_WUF9)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUF9 field to a new value.
-#define BW_LLWU_F2_WUF9(v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF9) = (v))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_F2, field WUF10[2] (W1C)
- *
- * Indicates that an enabled external wakeup pin was a source of exiting a
- * low-leakage power mode. To clear the flag, write a 1 to WUF10.
- *
- * Values:
- * - 0 - LLWU_P10 input was not a wakeup source
- * - 1 - LLWU_P10 input was a wakeup source
- */
-//@{
-#define BP_LLWU_F2_WUF10 (2U) //!< Bit position for LLWU_F2_WUF10.
-#define BM_LLWU_F2_WUF10 (0x04U) //!< Bit mask for LLWU_F2_WUF10.
-#define BS_LLWU_F2_WUF10 (1U) //!< Bit field size in bits for LLWU_F2_WUF10.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_F2_WUF10 field.
-#define BR_LLWU_F2_WUF10 (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF10))
-#endif
-
-//! @brief Format value for bitfield LLWU_F2_WUF10.
-#define BF_LLWU_F2_WUF10(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF10), uint8_t) & BM_LLWU_F2_WUF10)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUF10 field to a new value.
-#define BW_LLWU_F2_WUF10(v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF10) = (v))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_F2, field WUF11[3] (W1C)
- *
- * Indicates that an enabled external wakeup pin was a source of exiting a
- * low-leakage power mode. To clear the flag, write a 1 to WUF11.
- *
- * Values:
- * - 0 - LLWU_P11 input was not a wakeup source
- * - 1 - LLWU_P11 input was a wakeup source
- */
-//@{
-#define BP_LLWU_F2_WUF11 (3U) //!< Bit position for LLWU_F2_WUF11.
-#define BM_LLWU_F2_WUF11 (0x08U) //!< Bit mask for LLWU_F2_WUF11.
-#define BS_LLWU_F2_WUF11 (1U) //!< Bit field size in bits for LLWU_F2_WUF11.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_F2_WUF11 field.
-#define BR_LLWU_F2_WUF11 (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF11))
-#endif
-
-//! @brief Format value for bitfield LLWU_F2_WUF11.
-#define BF_LLWU_F2_WUF11(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF11), uint8_t) & BM_LLWU_F2_WUF11)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUF11 field to a new value.
-#define BW_LLWU_F2_WUF11(v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF11) = (v))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_F2, field WUF12[4] (W1C)
- *
- * Indicates that an enabled external wakeup pin was a source of exiting a
- * low-leakage power mode. To clear the flag, write a 1 to WUF12.
- *
- * Values:
- * - 0 - LLWU_P12 input was not a wakeup source
- * - 1 - LLWU_P12 input was a wakeup source
- */
-//@{
-#define BP_LLWU_F2_WUF12 (4U) //!< Bit position for LLWU_F2_WUF12.
-#define BM_LLWU_F2_WUF12 (0x10U) //!< Bit mask for LLWU_F2_WUF12.
-#define BS_LLWU_F2_WUF12 (1U) //!< Bit field size in bits for LLWU_F2_WUF12.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_F2_WUF12 field.
-#define BR_LLWU_F2_WUF12 (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF12))
-#endif
-
-//! @brief Format value for bitfield LLWU_F2_WUF12.
-#define BF_LLWU_F2_WUF12(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF12), uint8_t) & BM_LLWU_F2_WUF12)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUF12 field to a new value.
-#define BW_LLWU_F2_WUF12(v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF12) = (v))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_F2, field WUF13[5] (W1C)
- *
- * Indicates that an enabled external wakeup pin was a source of exiting a
- * low-leakage power mode. To clear the flag, write a 1 to WUF13.
- *
- * Values:
- * - 0 - LLWU_P13 input was not a wakeup source
- * - 1 - LLWU_P13 input was a wakeup source
- */
-//@{
-#define BP_LLWU_F2_WUF13 (5U) //!< Bit position for LLWU_F2_WUF13.
-#define BM_LLWU_F2_WUF13 (0x20U) //!< Bit mask for LLWU_F2_WUF13.
-#define BS_LLWU_F2_WUF13 (1U) //!< Bit field size in bits for LLWU_F2_WUF13.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_F2_WUF13 field.
-#define BR_LLWU_F2_WUF13 (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF13))
-#endif
-
-//! @brief Format value for bitfield LLWU_F2_WUF13.
-#define BF_LLWU_F2_WUF13(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF13), uint8_t) & BM_LLWU_F2_WUF13)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUF13 field to a new value.
-#define BW_LLWU_F2_WUF13(v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF13) = (v))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_F2, field WUF14[6] (W1C)
- *
- * Indicates that an enabled external wakeup pin was a source of exiting a
- * low-leakage power mode. To clear the flag, write a 1 to WUF14.
- *
- * Values:
- * - 0 - LLWU_P14 input was not a wakeup source
- * - 1 - LLWU_P14 input was a wakeup source
- */
-//@{
-#define BP_LLWU_F2_WUF14 (6U) //!< Bit position for LLWU_F2_WUF14.
-#define BM_LLWU_F2_WUF14 (0x40U) //!< Bit mask for LLWU_F2_WUF14.
-#define BS_LLWU_F2_WUF14 (1U) //!< Bit field size in bits for LLWU_F2_WUF14.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_F2_WUF14 field.
-#define BR_LLWU_F2_WUF14 (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF14))
-#endif
-
-//! @brief Format value for bitfield LLWU_F2_WUF14.
-#define BF_LLWU_F2_WUF14(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF14), uint8_t) & BM_LLWU_F2_WUF14)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUF14 field to a new value.
-#define BW_LLWU_F2_WUF14(v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF14) = (v))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_F2, field WUF15[7] (W1C)
- *
- * Indicates that an enabled external wakeup pin was a source of exiting a
- * low-leakage power mode. To clear the flag, write a 1 to WUF15.
- *
- * Values:
- * - 0 - LLWU_P15 input was not a wakeup source
- * - 1 - LLWU_P15 input was a wakeup source
- */
-//@{
-#define BP_LLWU_F2_WUF15 (7U) //!< Bit position for LLWU_F2_WUF15.
-#define BM_LLWU_F2_WUF15 (0x80U) //!< Bit mask for LLWU_F2_WUF15.
-#define BS_LLWU_F2_WUF15 (1U) //!< Bit field size in bits for LLWU_F2_WUF15.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_F2_WUF15 field.
-#define BR_LLWU_F2_WUF15 (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF15))
-#endif
-
-//! @brief Format value for bitfield LLWU_F2_WUF15.
-#define BF_LLWU_F2_WUF15(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF15), uint8_t) & BM_LLWU_F2_WUF15)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WUF15 field to a new value.
-#define BW_LLWU_F2_WUF15(v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF15) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_LLWU_F3 - LLWU Flag 3 register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_LLWU_F3 - LLWU Flag 3 register (RO)
- *
- * Reset value: 0x00U
- *
- * LLWU_F3 contains the wakeup flags indicating which internal wakeup source
- * caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the
- * CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow.
- * For internal peripherals that are capable of running in a low-leakage power
- * mode, such as a real time clock module or CMP module, the flag from the
- * associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared
- * in the peripheral instead of writing a 1 to the MWUFx bit. This register is
- * reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not
- * VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See
- * the IntroductionInformation found here describes the registers of the Reset
- * Control Module (RCM). The RCM implements many of the reset functions for the
- * chip. See the chip's reset chapter for more information. details for more
- * information.
- */
-typedef union _hw_llwu_f3
-{
- uint8_t U;
- struct _hw_llwu_f3_bitfields
- {
- uint8_t MWUF0 : 1; //!< [0] Wakeup flag For module 0
- uint8_t MWUF1 : 1; //!< [1] Wakeup flag For module 1
- uint8_t MWUF2 : 1; //!< [2] Wakeup flag For module 2
- uint8_t MWUF3 : 1; //!< [3] Wakeup flag For module 3
- uint8_t MWUF4 : 1; //!< [4] Wakeup flag For module 4
- uint8_t MWUF5 : 1; //!< [5] Wakeup flag For module 5
- uint8_t MWUF6 : 1; //!< [6] Wakeup flag For module 6
- uint8_t MWUF7 : 1; //!< [7] Wakeup flag For module 7
- } B;
-} hw_llwu_f3_t;
-#endif
-
-/*!
- * @name Constants and macros for entire LLWU_F3 register
- */
-//@{
-#define HW_LLWU_F3_ADDR (REGS_LLWU_BASE + 0x7U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_LLWU_F3 (*(__I hw_llwu_f3_t *) HW_LLWU_F3_ADDR)
-#define HW_LLWU_F3_RD() (HW_LLWU_F3.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual LLWU_F3 bitfields
- */
-
-/*!
- * @name Register LLWU_F3, field MWUF0[0] (RO)
- *
- * Indicates that an enabled internal peripheral was a source of exiting a
- * low-leakage power mode. To clear the flag, follow the internal peripheral flag
- * clearing mechanism.
- *
- * Values:
- * - 0 - Module 0 input was not a wakeup source
- * - 1 - Module 0 input was a wakeup source
- */
-//@{
-#define BP_LLWU_F3_MWUF0 (0U) //!< Bit position for LLWU_F3_MWUF0.
-#define BM_LLWU_F3_MWUF0 (0x01U) //!< Bit mask for LLWU_F3_MWUF0.
-#define BS_LLWU_F3_MWUF0 (1U) //!< Bit field size in bits for LLWU_F3_MWUF0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_F3_MWUF0 field.
-#define BR_LLWU_F3_MWUF0 (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF0))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_F3, field MWUF1[1] (RO)
- *
- * Indicates that an enabled internal peripheral was a source of exiting a
- * low-leakage power mode. To clear the flag, follow the internal peripheral flag
- * clearing mechanism.
- *
- * Values:
- * - 0 - Module 1 input was not a wakeup source
- * - 1 - Module 1 input was a wakeup source
- */
-//@{
-#define BP_LLWU_F3_MWUF1 (1U) //!< Bit position for LLWU_F3_MWUF1.
-#define BM_LLWU_F3_MWUF1 (0x02U) //!< Bit mask for LLWU_F3_MWUF1.
-#define BS_LLWU_F3_MWUF1 (1U) //!< Bit field size in bits for LLWU_F3_MWUF1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_F3_MWUF1 field.
-#define BR_LLWU_F3_MWUF1 (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF1))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_F3, field MWUF2[2] (RO)
- *
- * Indicates that an enabled internal peripheral was a source of exiting a
- * low-leakage power mode. To clear the flag, follow the internal peripheral flag
- * clearing mechanism.
- *
- * Values:
- * - 0 - Module 2 input was not a wakeup source
- * - 1 - Module 2 input was a wakeup source
- */
-//@{
-#define BP_LLWU_F3_MWUF2 (2U) //!< Bit position for LLWU_F3_MWUF2.
-#define BM_LLWU_F3_MWUF2 (0x04U) //!< Bit mask for LLWU_F3_MWUF2.
-#define BS_LLWU_F3_MWUF2 (1U) //!< Bit field size in bits for LLWU_F3_MWUF2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_F3_MWUF2 field.
-#define BR_LLWU_F3_MWUF2 (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF2))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_F3, field MWUF3[3] (RO)
- *
- * Indicates that an enabled internal peripheral was a source of exiting a
- * low-leakage power mode. To clear the flag, follow the internal peripheral flag
- * clearing mechanism.
- *
- * Values:
- * - 0 - Module 3 input was not a wakeup source
- * - 1 - Module 3 input was a wakeup source
- */
-//@{
-#define BP_LLWU_F3_MWUF3 (3U) //!< Bit position for LLWU_F3_MWUF3.
-#define BM_LLWU_F3_MWUF3 (0x08U) //!< Bit mask for LLWU_F3_MWUF3.
-#define BS_LLWU_F3_MWUF3 (1U) //!< Bit field size in bits for LLWU_F3_MWUF3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_F3_MWUF3 field.
-#define BR_LLWU_F3_MWUF3 (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF3))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_F3, field MWUF4[4] (RO)
- *
- * Indicates that an enabled internal peripheral was a source of exiting a
- * low-leakage power mode. To clear the flag, follow the internal peripheral flag
- * clearing mechanism.
- *
- * Values:
- * - 0 - Module 4 input was not a wakeup source
- * - 1 - Module 4 input was a wakeup source
- */
-//@{
-#define BP_LLWU_F3_MWUF4 (4U) //!< Bit position for LLWU_F3_MWUF4.
-#define BM_LLWU_F3_MWUF4 (0x10U) //!< Bit mask for LLWU_F3_MWUF4.
-#define BS_LLWU_F3_MWUF4 (1U) //!< Bit field size in bits for LLWU_F3_MWUF4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_F3_MWUF4 field.
-#define BR_LLWU_F3_MWUF4 (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF4))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_F3, field MWUF5[5] (RO)
- *
- * Indicates that an enabled internal peripheral was a source of exiting a
- * low-leakage power mode. To clear the flag, follow the internal peripheral flag
- * clearing mechanism.
- *
- * Values:
- * - 0 - Module 5 input was not a wakeup source
- * - 1 - Module 5 input was a wakeup source
- */
-//@{
-#define BP_LLWU_F3_MWUF5 (5U) //!< Bit position for LLWU_F3_MWUF5.
-#define BM_LLWU_F3_MWUF5 (0x20U) //!< Bit mask for LLWU_F3_MWUF5.
-#define BS_LLWU_F3_MWUF5 (1U) //!< Bit field size in bits for LLWU_F3_MWUF5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_F3_MWUF5 field.
-#define BR_LLWU_F3_MWUF5 (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF5))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_F3, field MWUF6[6] (RO)
- *
- * Indicates that an enabled internal peripheral was a source of exiting a
- * low-leakage power mode. To clear the flag, follow the internal peripheral flag
- * clearing mechanism.
- *
- * Values:
- * - 0 - Module 6 input was not a wakeup source
- * - 1 - Module 6 input was a wakeup source
- */
-//@{
-#define BP_LLWU_F3_MWUF6 (6U) //!< Bit position for LLWU_F3_MWUF6.
-#define BM_LLWU_F3_MWUF6 (0x40U) //!< Bit mask for LLWU_F3_MWUF6.
-#define BS_LLWU_F3_MWUF6 (1U) //!< Bit field size in bits for LLWU_F3_MWUF6.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_F3_MWUF6 field.
-#define BR_LLWU_F3_MWUF6 (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF6))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_F3, field MWUF7[7] (RO)
- *
- * Indicates that an enabled internal peripheral was a source of exiting a
- * low-leakage power mode. To clear the flag, follow the internal peripheral flag
- * clearing mechanism.
- *
- * Values:
- * - 0 - Module 7 input was not a wakeup source
- * - 1 - Module 7 input was a wakeup source
- */
-//@{
-#define BP_LLWU_F3_MWUF7 (7U) //!< Bit position for LLWU_F3_MWUF7.
-#define BM_LLWU_F3_MWUF7 (0x80U) //!< Bit mask for LLWU_F3_MWUF7.
-#define BS_LLWU_F3_MWUF7 (1U) //!< Bit field size in bits for LLWU_F3_MWUF7.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_F3_MWUF7 field.
-#define BR_LLWU_F3_MWUF7 (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF7))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_LLWU_FILT1 - LLWU Pin Filter 1 register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_LLWU_FILT1 - LLWU Pin Filter 1 register (RW)
- *
- * Reset value: 0x00U
- *
- * LLWU_FILT1 is a control and status register that is used to enable/disable
- * the digital filter 1 features for an external pin. This register is reset on
- * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
- * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
- * IntroductionInformation found here describes the registers of the Reset Control
- * Module (RCM). The RCM implements many of the reset functions for the chip. See
- * the chip's reset chapter for more information. details for more information.
- */
-typedef union _hw_llwu_filt1
-{
- uint8_t U;
- struct _hw_llwu_filt1_bitfields
- {
- uint8_t FILTSEL : 4; //!< [3:0] Filter Pin Select
- uint8_t RESERVED0 : 1; //!< [4]
- uint8_t FILTE : 2; //!< [6:5] Digital Filter On External Pin
- uint8_t FILTF : 1; //!< [7] Filter Detect Flag
- } B;
-} hw_llwu_filt1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire LLWU_FILT1 register
- */
-//@{
-#define HW_LLWU_FILT1_ADDR (REGS_LLWU_BASE + 0x8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_LLWU_FILT1 (*(__IO hw_llwu_filt1_t *) HW_LLWU_FILT1_ADDR)
-#define HW_LLWU_FILT1_RD() (HW_LLWU_FILT1.U)
-#define HW_LLWU_FILT1_WR(v) (HW_LLWU_FILT1.U = (v))
-#define HW_LLWU_FILT1_SET(v) (HW_LLWU_FILT1_WR(HW_LLWU_FILT1_RD() | (v)))
-#define HW_LLWU_FILT1_CLR(v) (HW_LLWU_FILT1_WR(HW_LLWU_FILT1_RD() & ~(v)))
-#define HW_LLWU_FILT1_TOG(v) (HW_LLWU_FILT1_WR(HW_LLWU_FILT1_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual LLWU_FILT1 bitfields
- */
-
-/*!
- * @name Register LLWU_FILT1, field FILTSEL[3:0] (RW)
- *
- * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
- *
- * Values:
- * - 0000 - Select LLWU_P0 for filter
- * - 1111 - Select LLWU_P15 for filter
- */
-//@{
-#define BP_LLWU_FILT1_FILTSEL (0U) //!< Bit position for LLWU_FILT1_FILTSEL.
-#define BM_LLWU_FILT1_FILTSEL (0x0FU) //!< Bit mask for LLWU_FILT1_FILTSEL.
-#define BS_LLWU_FILT1_FILTSEL (4U) //!< Bit field size in bits for LLWU_FILT1_FILTSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_FILT1_FILTSEL field.
-#define BR_LLWU_FILT1_FILTSEL (HW_LLWU_FILT1.B.FILTSEL)
-#endif
-
-//! @brief Format value for bitfield LLWU_FILT1_FILTSEL.
-#define BF_LLWU_FILT1_FILTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_FILT1_FILTSEL), uint8_t) & BM_LLWU_FILT1_FILTSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FILTSEL field to a new value.
-#define BW_LLWU_FILT1_FILTSEL(v) (HW_LLWU_FILT1_WR((HW_LLWU_FILT1_RD() & ~BM_LLWU_FILT1_FILTSEL) | BF_LLWU_FILT1_FILTSEL(v)))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_FILT1, field FILTE[6:5] (RW)
- *
- * Controls the digital filter options for the external pin detect.
- *
- * Values:
- * - 00 - Filter disabled
- * - 01 - Filter posedge detect enabled
- * - 10 - Filter negedge detect enabled
- * - 11 - Filter any edge detect enabled
- */
-//@{
-#define BP_LLWU_FILT1_FILTE (5U) //!< Bit position for LLWU_FILT1_FILTE.
-#define BM_LLWU_FILT1_FILTE (0x60U) //!< Bit mask for LLWU_FILT1_FILTE.
-#define BS_LLWU_FILT1_FILTE (2U) //!< Bit field size in bits for LLWU_FILT1_FILTE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_FILT1_FILTE field.
-#define BR_LLWU_FILT1_FILTE (HW_LLWU_FILT1.B.FILTE)
-#endif
-
-//! @brief Format value for bitfield LLWU_FILT1_FILTE.
-#define BF_LLWU_FILT1_FILTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_FILT1_FILTE), uint8_t) & BM_LLWU_FILT1_FILTE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FILTE field to a new value.
-#define BW_LLWU_FILT1_FILTE(v) (HW_LLWU_FILT1_WR((HW_LLWU_FILT1_RD() & ~BM_LLWU_FILT1_FILTE) | BF_LLWU_FILT1_FILTE(v)))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_FILT1, field FILTF[7] (W1C)
- *
- * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
- * source of exiting a low-leakage power mode. To clear the flag write a one to
- * FILTF.
- *
- * Values:
- * - 0 - Pin Filter 1 was not a wakeup source
- * - 1 - Pin Filter 1 was a wakeup source
- */
-//@{
-#define BP_LLWU_FILT1_FILTF (7U) //!< Bit position for LLWU_FILT1_FILTF.
-#define BM_LLWU_FILT1_FILTF (0x80U) //!< Bit mask for LLWU_FILT1_FILTF.
-#define BS_LLWU_FILT1_FILTF (1U) //!< Bit field size in bits for LLWU_FILT1_FILTF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_FILT1_FILTF field.
-#define BR_LLWU_FILT1_FILTF (BITBAND_ACCESS8(HW_LLWU_FILT1_ADDR, BP_LLWU_FILT1_FILTF))
-#endif
-
-//! @brief Format value for bitfield LLWU_FILT1_FILTF.
-#define BF_LLWU_FILT1_FILTF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_FILT1_FILTF), uint8_t) & BM_LLWU_FILT1_FILTF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FILTF field to a new value.
-#define BW_LLWU_FILT1_FILTF(v) (BITBAND_ACCESS8(HW_LLWU_FILT1_ADDR, BP_LLWU_FILT1_FILTF) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_LLWU_FILT2 - LLWU Pin Filter 2 register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_LLWU_FILT2 - LLWU Pin Filter 2 register (RW)
- *
- * Reset value: 0x00U
- *
- * LLWU_FILT2 is a control and status register that is used to enable/disable
- * the digital filter 2 features for an external pin. This register is reset on
- * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
- * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
- * IntroductionInformation found here describes the registers of the Reset Control
- * Module (RCM). The RCM implements many of the reset functions for the chip. See
- * the chip's reset chapter for more information. details for more information.
- */
-typedef union _hw_llwu_filt2
-{
- uint8_t U;
- struct _hw_llwu_filt2_bitfields
- {
- uint8_t FILTSEL : 4; //!< [3:0] Filter Pin Select
- uint8_t RESERVED0 : 1; //!< [4]
- uint8_t FILTE : 2; //!< [6:5] Digital Filter On External Pin
- uint8_t FILTF : 1; //!< [7] Filter Detect Flag
- } B;
-} hw_llwu_filt2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire LLWU_FILT2 register
- */
-//@{
-#define HW_LLWU_FILT2_ADDR (REGS_LLWU_BASE + 0x9U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_LLWU_FILT2 (*(__IO hw_llwu_filt2_t *) HW_LLWU_FILT2_ADDR)
-#define HW_LLWU_FILT2_RD() (HW_LLWU_FILT2.U)
-#define HW_LLWU_FILT2_WR(v) (HW_LLWU_FILT2.U = (v))
-#define HW_LLWU_FILT2_SET(v) (HW_LLWU_FILT2_WR(HW_LLWU_FILT2_RD() | (v)))
-#define HW_LLWU_FILT2_CLR(v) (HW_LLWU_FILT2_WR(HW_LLWU_FILT2_RD() & ~(v)))
-#define HW_LLWU_FILT2_TOG(v) (HW_LLWU_FILT2_WR(HW_LLWU_FILT2_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual LLWU_FILT2 bitfields
- */
-
-/*!
- * @name Register LLWU_FILT2, field FILTSEL[3:0] (RW)
- *
- * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
- *
- * Values:
- * - 0000 - Select LLWU_P0 for filter
- * - 1111 - Select LLWU_P15 for filter
- */
-//@{
-#define BP_LLWU_FILT2_FILTSEL (0U) //!< Bit position for LLWU_FILT2_FILTSEL.
-#define BM_LLWU_FILT2_FILTSEL (0x0FU) //!< Bit mask for LLWU_FILT2_FILTSEL.
-#define BS_LLWU_FILT2_FILTSEL (4U) //!< Bit field size in bits for LLWU_FILT2_FILTSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_FILT2_FILTSEL field.
-#define BR_LLWU_FILT2_FILTSEL (HW_LLWU_FILT2.B.FILTSEL)
-#endif
-
-//! @brief Format value for bitfield LLWU_FILT2_FILTSEL.
-#define BF_LLWU_FILT2_FILTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_FILT2_FILTSEL), uint8_t) & BM_LLWU_FILT2_FILTSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FILTSEL field to a new value.
-#define BW_LLWU_FILT2_FILTSEL(v) (HW_LLWU_FILT2_WR((HW_LLWU_FILT2_RD() & ~BM_LLWU_FILT2_FILTSEL) | BF_LLWU_FILT2_FILTSEL(v)))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_FILT2, field FILTE[6:5] (RW)
- *
- * Controls the digital filter options for the external pin detect.
- *
- * Values:
- * - 00 - Filter disabled
- * - 01 - Filter posedge detect enabled
- * - 10 - Filter negedge detect enabled
- * - 11 - Filter any edge detect enabled
- */
-//@{
-#define BP_LLWU_FILT2_FILTE (5U) //!< Bit position for LLWU_FILT2_FILTE.
-#define BM_LLWU_FILT2_FILTE (0x60U) //!< Bit mask for LLWU_FILT2_FILTE.
-#define BS_LLWU_FILT2_FILTE (2U) //!< Bit field size in bits for LLWU_FILT2_FILTE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_FILT2_FILTE field.
-#define BR_LLWU_FILT2_FILTE (HW_LLWU_FILT2.B.FILTE)
-#endif
-
-//! @brief Format value for bitfield LLWU_FILT2_FILTE.
-#define BF_LLWU_FILT2_FILTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_FILT2_FILTE), uint8_t) & BM_LLWU_FILT2_FILTE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FILTE field to a new value.
-#define BW_LLWU_FILT2_FILTE(v) (HW_LLWU_FILT2_WR((HW_LLWU_FILT2_RD() & ~BM_LLWU_FILT2_FILTE) | BF_LLWU_FILT2_FILTE(v)))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_FILT2, field FILTF[7] (W1C)
- *
- * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
- * source of exiting a low-leakage power mode. To clear the flag write a one to
- * FILTF.
- *
- * Values:
- * - 0 - Pin Filter 2 was not a wakeup source
- * - 1 - Pin Filter 2 was a wakeup source
- */
-//@{
-#define BP_LLWU_FILT2_FILTF (7U) //!< Bit position for LLWU_FILT2_FILTF.
-#define BM_LLWU_FILT2_FILTF (0x80U) //!< Bit mask for LLWU_FILT2_FILTF.
-#define BS_LLWU_FILT2_FILTF (1U) //!< Bit field size in bits for LLWU_FILT2_FILTF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_FILT2_FILTF field.
-#define BR_LLWU_FILT2_FILTF (BITBAND_ACCESS8(HW_LLWU_FILT2_ADDR, BP_LLWU_FILT2_FILTF))
-#endif
-
-//! @brief Format value for bitfield LLWU_FILT2_FILTF.
-#define BF_LLWU_FILT2_FILTF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_FILT2_FILTF), uint8_t) & BM_LLWU_FILT2_FILTF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FILTF field to a new value.
-#define BW_LLWU_FILT2_FILTF(v) (BITBAND_ACCESS8(HW_LLWU_FILT2_ADDR, BP_LLWU_FILT2_FILTF) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_LLWU_RST - LLWU Reset Enable register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_LLWU_RST - LLWU Reset Enable register (RW)
- *
- * Reset value: 0x02U
- *
- * LLWU_RST is a control register that is used to enable/disable the digital
- * filter for the external pin detect and RESET pin. This register is reset on Chip
- * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
- * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
- * IntroductionInformation found here describes the registers of the Reset Control
- * Module (RCM). The RCM implements many of the reset functions for the chip. See the
- * chip's reset chapter for more information. details for more information.
- */
-typedef union _hw_llwu_rst
-{
- uint8_t U;
- struct _hw_llwu_rst_bitfields
- {
- uint8_t RSTFILT : 1; //!< [0] Digital Filter On RESET Pin
- uint8_t LLRSTE : 1; //!< [1] Low-Leakage Mode RESET Enable
- uint8_t RESERVED0 : 6; //!< [7:2]
- } B;
-} hw_llwu_rst_t;
-#endif
-
-/*!
- * @name Constants and macros for entire LLWU_RST register
- */
-//@{
-#define HW_LLWU_RST_ADDR (REGS_LLWU_BASE + 0xAU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_LLWU_RST (*(__IO hw_llwu_rst_t *) HW_LLWU_RST_ADDR)
-#define HW_LLWU_RST_RD() (HW_LLWU_RST.U)
-#define HW_LLWU_RST_WR(v) (HW_LLWU_RST.U = (v))
-#define HW_LLWU_RST_SET(v) (HW_LLWU_RST_WR(HW_LLWU_RST_RD() | (v)))
-#define HW_LLWU_RST_CLR(v) (HW_LLWU_RST_WR(HW_LLWU_RST_RD() & ~(v)))
-#define HW_LLWU_RST_TOG(v) (HW_LLWU_RST_WR(HW_LLWU_RST_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual LLWU_RST bitfields
- */
-
-/*!
- * @name Register LLWU_RST, field RSTFILT[0] (RW)
- *
- * Enables the digital filter for the RESET pin during LLS, VLLS3, VLLS2, or
- * VLLS1 modes.
- *
- * Values:
- * - 0 - Filter not enabled
- * - 1 - Filter enabled
- */
-//@{
-#define BP_LLWU_RST_RSTFILT (0U) //!< Bit position for LLWU_RST_RSTFILT.
-#define BM_LLWU_RST_RSTFILT (0x01U) //!< Bit mask for LLWU_RST_RSTFILT.
-#define BS_LLWU_RST_RSTFILT (1U) //!< Bit field size in bits for LLWU_RST_RSTFILT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_RST_RSTFILT field.
-#define BR_LLWU_RST_RSTFILT (BITBAND_ACCESS8(HW_LLWU_RST_ADDR, BP_LLWU_RST_RSTFILT))
-#endif
-
-//! @brief Format value for bitfield LLWU_RST_RSTFILT.
-#define BF_LLWU_RST_RSTFILT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_RST_RSTFILT), uint8_t) & BM_LLWU_RST_RSTFILT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RSTFILT field to a new value.
-#define BW_LLWU_RST_RSTFILT(v) (BITBAND_ACCESS8(HW_LLWU_RST_ADDR, BP_LLWU_RST_RSTFILT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register LLWU_RST, field LLRSTE[1] (RW)
- *
- * This bit must be set to allow the device to be reset while in a low-leakage
- * power mode. On devices where Reset is not a dedicated pin, the RESET pin must
- * also be enabled in the explicit port mux control.
- *
- * Values:
- * - 0 - RESET pin not enabled as a leakage mode exit source
- * - 1 - RESET pin enabled as a low leakage mode exit source
- */
-//@{
-#define BP_LLWU_RST_LLRSTE (1U) //!< Bit position for LLWU_RST_LLRSTE.
-#define BM_LLWU_RST_LLRSTE (0x02U) //!< Bit mask for LLWU_RST_LLRSTE.
-#define BS_LLWU_RST_LLRSTE (1U) //!< Bit field size in bits for LLWU_RST_LLRSTE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LLWU_RST_LLRSTE field.
-#define BR_LLWU_RST_LLRSTE (BITBAND_ACCESS8(HW_LLWU_RST_ADDR, BP_LLWU_RST_LLRSTE))
-#endif
-
-//! @brief Format value for bitfield LLWU_RST_LLRSTE.
-#define BF_LLWU_RST_LLRSTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_RST_LLRSTE), uint8_t) & BM_LLWU_RST_LLRSTE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LLRSTE field to a new value.
-#define BW_LLWU_RST_LLRSTE(v) (BITBAND_ACCESS8(HW_LLWU_RST_ADDR, BP_LLWU_RST_LLRSTE) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_llwu_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All LLWU module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_llwu
-{
- __IO hw_llwu_pe1_t PE1; //!< [0x0] LLWU Pin Enable 1 register
- __IO hw_llwu_pe2_t PE2; //!< [0x1] LLWU Pin Enable 2 register
- __IO hw_llwu_pe3_t PE3; //!< [0x2] LLWU Pin Enable 3 register
- __IO hw_llwu_pe4_t PE4; //!< [0x3] LLWU Pin Enable 4 register
- __IO hw_llwu_me_t ME; //!< [0x4] LLWU Module Enable register
- __IO hw_llwu_f1_t F1; //!< [0x5] LLWU Flag 1 register
- __IO hw_llwu_f2_t F2; //!< [0x6] LLWU Flag 2 register
- __I hw_llwu_f3_t F3; //!< [0x7] LLWU Flag 3 register
- __IO hw_llwu_filt1_t FILT1; //!< [0x8] LLWU Pin Filter 1 register
- __IO hw_llwu_filt2_t FILT2; //!< [0x9] LLWU Pin Filter 2 register
- __IO hw_llwu_rst_t RST; //!< [0xA] LLWU Reset Enable register
-} hw_llwu_t;
-#pragma pack()
-
-//! @brief Macro to access all LLWU registers.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_LLWU</code>.
-#define HW_LLWU (*(hw_llwu_t *) REGS_LLWU_BASE)
-#endif
-
-#endif // __HW_LLWU_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_lptmr.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,629 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_LPTMR_REGISTERS_H__
-#define __HW_LPTMR_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 LPTMR
- *
- * Low Power Timer
- *
- * Registers defined in this header file:
- * - HW_LPTMR_CSR - Low Power Timer Control Status Register
- * - HW_LPTMR_PSR - Low Power Timer Prescale Register
- * - HW_LPTMR_CMR - Low Power Timer Compare Register
- * - HW_LPTMR_CNR - Low Power Timer Counter Register
- *
- * - hw_lptmr_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_LPTMR_BASE
-#define HW_LPTMR_INSTANCE_COUNT (1U) //!< Number of instances of the LPTMR module.
-#define REGS_LPTMR_BASE (0x40040000U) //!< Base address for LPTMR0.
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_LPTMR_CSR - Low Power Timer Control Status Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_LPTMR_CSR - Low Power Timer Control Status Register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_lptmr_csr
-{
- uint32_t U;
- struct _hw_lptmr_csr_bitfields
- {
- uint32_t TEN : 1; //!< [0] Timer Enable
- uint32_t TMS : 1; //!< [1] Timer Mode Select
- uint32_t TFC : 1; //!< [2] Timer Free-Running Counter
- uint32_t TPP : 1; //!< [3] Timer Pin Polarity
- uint32_t TPS : 2; //!< [5:4] Timer Pin Select
- uint32_t TIE : 1; //!< [6] Timer Interrupt Enable
- uint32_t TCF : 1; //!< [7] Timer Compare Flag
- uint32_t RESERVED0 : 24; //!< [31:8]
- } B;
-} hw_lptmr_csr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire LPTMR_CSR register
- */
-//@{
-#define HW_LPTMR_CSR_ADDR (REGS_LPTMR_BASE + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_LPTMR_CSR (*(__IO hw_lptmr_csr_t *) HW_LPTMR_CSR_ADDR)
-#define HW_LPTMR_CSR_RD() (HW_LPTMR_CSR.U)
-#define HW_LPTMR_CSR_WR(v) (HW_LPTMR_CSR.U = (v))
-#define HW_LPTMR_CSR_SET(v) (HW_LPTMR_CSR_WR(HW_LPTMR_CSR_RD() | (v)))
-#define HW_LPTMR_CSR_CLR(v) (HW_LPTMR_CSR_WR(HW_LPTMR_CSR_RD() & ~(v)))
-#define HW_LPTMR_CSR_TOG(v) (HW_LPTMR_CSR_WR(HW_LPTMR_CSR_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual LPTMR_CSR bitfields
- */
-
-/*!
- * @name Register LPTMR_CSR, field TEN[0] (RW)
- *
- * When TEN is clear, it resets the LPTMR internal logic, including the CNR and
- * TCF. When TEN is set, the LPTMR is enabled. While writing 1 to this field,
- * CSR[5:1] must not be altered.
- *
- * Values:
- * - 0 - LPTMR is disabled and internal logic is reset.
- * - 1 - LPTMR is enabled.
- */
-//@{
-#define BP_LPTMR_CSR_TEN (0U) //!< Bit position for LPTMR_CSR_TEN.
-#define BM_LPTMR_CSR_TEN (0x00000001U) //!< Bit mask for LPTMR_CSR_TEN.
-#define BS_LPTMR_CSR_TEN (1U) //!< Bit field size in bits for LPTMR_CSR_TEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LPTMR_CSR_TEN field.
-#define BR_LPTMR_CSR_TEN (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TEN))
-#endif
-
-//! @brief Format value for bitfield LPTMR_CSR_TEN.
-#define BF_LPTMR_CSR_TEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TEN), uint32_t) & BM_LPTMR_CSR_TEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TEN field to a new value.
-#define BW_LPTMR_CSR_TEN(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register LPTMR_CSR, field TMS[1] (RW)
- *
- * Configures the mode of the LPTMR. TMS must be altered only when the LPTMR is
- * disabled.
- *
- * Values:
- * - 0 - Time Counter mode.
- * - 1 - Pulse Counter mode.
- */
-//@{
-#define BP_LPTMR_CSR_TMS (1U) //!< Bit position for LPTMR_CSR_TMS.
-#define BM_LPTMR_CSR_TMS (0x00000002U) //!< Bit mask for LPTMR_CSR_TMS.
-#define BS_LPTMR_CSR_TMS (1U) //!< Bit field size in bits for LPTMR_CSR_TMS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LPTMR_CSR_TMS field.
-#define BR_LPTMR_CSR_TMS (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TMS))
-#endif
-
-//! @brief Format value for bitfield LPTMR_CSR_TMS.
-#define BF_LPTMR_CSR_TMS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TMS), uint32_t) & BM_LPTMR_CSR_TMS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TMS field to a new value.
-#define BW_LPTMR_CSR_TMS(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TMS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register LPTMR_CSR, field TFC[2] (RW)
- *
- * When clear, TFC configures the CNR to reset whenever TCF is set. When set,
- * TFC configures the CNR to reset on overflow. TFC must be altered only when the
- * LPTMR is disabled.
- *
- * Values:
- * - 0 - CNR is reset whenever TCF is set.
- * - 1 - CNR is reset on overflow.
- */
-//@{
-#define BP_LPTMR_CSR_TFC (2U) //!< Bit position for LPTMR_CSR_TFC.
-#define BM_LPTMR_CSR_TFC (0x00000004U) //!< Bit mask for LPTMR_CSR_TFC.
-#define BS_LPTMR_CSR_TFC (1U) //!< Bit field size in bits for LPTMR_CSR_TFC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LPTMR_CSR_TFC field.
-#define BR_LPTMR_CSR_TFC (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TFC))
-#endif
-
-//! @brief Format value for bitfield LPTMR_CSR_TFC.
-#define BF_LPTMR_CSR_TFC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TFC), uint32_t) & BM_LPTMR_CSR_TFC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TFC field to a new value.
-#define BW_LPTMR_CSR_TFC(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TFC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register LPTMR_CSR, field TPP[3] (RW)
- *
- * Configures the polarity of the input source in Pulse Counter mode. TPP must
- * be changed only when the LPTMR is disabled.
- *
- * Values:
- * - 0 - Pulse Counter input source is active-high, and the CNR will increment
- * on the rising-edge.
- * - 1 - Pulse Counter input source is active-low, and the CNR will increment on
- * the falling-edge.
- */
-//@{
-#define BP_LPTMR_CSR_TPP (3U) //!< Bit position for LPTMR_CSR_TPP.
-#define BM_LPTMR_CSR_TPP (0x00000008U) //!< Bit mask for LPTMR_CSR_TPP.
-#define BS_LPTMR_CSR_TPP (1U) //!< Bit field size in bits for LPTMR_CSR_TPP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LPTMR_CSR_TPP field.
-#define BR_LPTMR_CSR_TPP (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TPP))
-#endif
-
-//! @brief Format value for bitfield LPTMR_CSR_TPP.
-#define BF_LPTMR_CSR_TPP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TPP), uint32_t) & BM_LPTMR_CSR_TPP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TPP field to a new value.
-#define BW_LPTMR_CSR_TPP(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TPP) = (v))
-#endif
-//@}
-
-/*!
- * @name Register LPTMR_CSR, field TPS[5:4] (RW)
- *
- * Configures the input source to be used in Pulse Counter mode. TPS must be
- * altered only when the LPTMR is disabled. The input connections vary by device.
- * See the chip configuration details for information on the connections to these
- * inputs.
- *
- * Values:
- * - 00 - Pulse counter input 0 is selected.
- * - 01 - Pulse counter input 1 is selected.
- * - 10 - Pulse counter input 2 is selected.
- * - 11 - Pulse counter input 3 is selected.
- */
-//@{
-#define BP_LPTMR_CSR_TPS (4U) //!< Bit position for LPTMR_CSR_TPS.
-#define BM_LPTMR_CSR_TPS (0x00000030U) //!< Bit mask for LPTMR_CSR_TPS.
-#define BS_LPTMR_CSR_TPS (2U) //!< Bit field size in bits for LPTMR_CSR_TPS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LPTMR_CSR_TPS field.
-#define BR_LPTMR_CSR_TPS (HW_LPTMR_CSR.B.TPS)
-#endif
-
-//! @brief Format value for bitfield LPTMR_CSR_TPS.
-#define BF_LPTMR_CSR_TPS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TPS), uint32_t) & BM_LPTMR_CSR_TPS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TPS field to a new value.
-#define BW_LPTMR_CSR_TPS(v) (HW_LPTMR_CSR_WR((HW_LPTMR_CSR_RD() & ~BM_LPTMR_CSR_TPS) | BF_LPTMR_CSR_TPS(v)))
-#endif
-//@}
-
-/*!
- * @name Register LPTMR_CSR, field TIE[6] (RW)
- *
- * When TIE is set, the LPTMR Interrupt is generated whenever TCF is also set.
- *
- * Values:
- * - 0 - Timer interrupt disabled.
- * - 1 - Timer interrupt enabled.
- */
-//@{
-#define BP_LPTMR_CSR_TIE (6U) //!< Bit position for LPTMR_CSR_TIE.
-#define BM_LPTMR_CSR_TIE (0x00000040U) //!< Bit mask for LPTMR_CSR_TIE.
-#define BS_LPTMR_CSR_TIE (1U) //!< Bit field size in bits for LPTMR_CSR_TIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LPTMR_CSR_TIE field.
-#define BR_LPTMR_CSR_TIE (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TIE))
-#endif
-
-//! @brief Format value for bitfield LPTMR_CSR_TIE.
-#define BF_LPTMR_CSR_TIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TIE), uint32_t) & BM_LPTMR_CSR_TIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TIE field to a new value.
-#define BW_LPTMR_CSR_TIE(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register LPTMR_CSR, field TCF[7] (W1C)
- *
- * TCF is set when the LPTMR is enabled and the CNR equals the CMR and
- * increments. TCF is cleared when the LPTMR is disabled or a logic 1 is written to it.
- *
- * Values:
- * - 0 - The value of CNR is not equal to CMR and increments.
- * - 1 - The value of CNR is equal to CMR and increments.
- */
-//@{
-#define BP_LPTMR_CSR_TCF (7U) //!< Bit position for LPTMR_CSR_TCF.
-#define BM_LPTMR_CSR_TCF (0x00000080U) //!< Bit mask for LPTMR_CSR_TCF.
-#define BS_LPTMR_CSR_TCF (1U) //!< Bit field size in bits for LPTMR_CSR_TCF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LPTMR_CSR_TCF field.
-#define BR_LPTMR_CSR_TCF (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TCF))
-#endif
-
-//! @brief Format value for bitfield LPTMR_CSR_TCF.
-#define BF_LPTMR_CSR_TCF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TCF), uint32_t) & BM_LPTMR_CSR_TCF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TCF field to a new value.
-#define BW_LPTMR_CSR_TCF(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TCF) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_LPTMR_PSR - Low Power Timer Prescale Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_LPTMR_PSR - Low Power Timer Prescale Register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_lptmr_psr
-{
- uint32_t U;
- struct _hw_lptmr_psr_bitfields
- {
- uint32_t PCS : 2; //!< [1:0] Prescaler Clock Select
- uint32_t PBYP : 1; //!< [2] Prescaler Bypass
- uint32_t PRESCALE : 4; //!< [6:3] Prescale Value
- uint32_t RESERVED0 : 25; //!< [31:7]
- } B;
-} hw_lptmr_psr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire LPTMR_PSR register
- */
-//@{
-#define HW_LPTMR_PSR_ADDR (REGS_LPTMR_BASE + 0x4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_LPTMR_PSR (*(__IO hw_lptmr_psr_t *) HW_LPTMR_PSR_ADDR)
-#define HW_LPTMR_PSR_RD() (HW_LPTMR_PSR.U)
-#define HW_LPTMR_PSR_WR(v) (HW_LPTMR_PSR.U = (v))
-#define HW_LPTMR_PSR_SET(v) (HW_LPTMR_PSR_WR(HW_LPTMR_PSR_RD() | (v)))
-#define HW_LPTMR_PSR_CLR(v) (HW_LPTMR_PSR_WR(HW_LPTMR_PSR_RD() & ~(v)))
-#define HW_LPTMR_PSR_TOG(v) (HW_LPTMR_PSR_WR(HW_LPTMR_PSR_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual LPTMR_PSR bitfields
- */
-
-/*!
- * @name Register LPTMR_PSR, field PCS[1:0] (RW)
- *
- * Selects the clock to be used by the LPTMR prescaler/glitch filter. PCS must
- * be altered only when the LPTMR is disabled. The clock connections vary by
- * device. See the chip configuration details for information on the connections to
- * these inputs.
- *
- * Values:
- * - 00 - Prescaler/glitch filter clock 0 selected.
- * - 01 - Prescaler/glitch filter clock 1 selected.
- * - 10 - Prescaler/glitch filter clock 2 selected.
- * - 11 - Prescaler/glitch filter clock 3 selected.
- */
-//@{
-#define BP_LPTMR_PSR_PCS (0U) //!< Bit position for LPTMR_PSR_PCS.
-#define BM_LPTMR_PSR_PCS (0x00000003U) //!< Bit mask for LPTMR_PSR_PCS.
-#define BS_LPTMR_PSR_PCS (2U) //!< Bit field size in bits for LPTMR_PSR_PCS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LPTMR_PSR_PCS field.
-#define BR_LPTMR_PSR_PCS (HW_LPTMR_PSR.B.PCS)
-#endif
-
-//! @brief Format value for bitfield LPTMR_PSR_PCS.
-#define BF_LPTMR_PSR_PCS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_PSR_PCS), uint32_t) & BM_LPTMR_PSR_PCS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PCS field to a new value.
-#define BW_LPTMR_PSR_PCS(v) (HW_LPTMR_PSR_WR((HW_LPTMR_PSR_RD() & ~BM_LPTMR_PSR_PCS) | BF_LPTMR_PSR_PCS(v)))
-#endif
-//@}
-
-/*!
- * @name Register LPTMR_PSR, field PBYP[2] (RW)
- *
- * When PBYP is set, the selected prescaler clock in Time Counter mode or
- * selected input source in Pulse Counter mode directly clocks the CNR. When PBYP is
- * clear, the CNR is clocked by the output of the prescaler/glitch filter. PBYP
- * must be altered only when the LPTMR is disabled.
- *
- * Values:
- * - 0 - Prescaler/glitch filter is enabled.
- * - 1 - Prescaler/glitch filter is bypassed.
- */
-//@{
-#define BP_LPTMR_PSR_PBYP (2U) //!< Bit position for LPTMR_PSR_PBYP.
-#define BM_LPTMR_PSR_PBYP (0x00000004U) //!< Bit mask for LPTMR_PSR_PBYP.
-#define BS_LPTMR_PSR_PBYP (1U) //!< Bit field size in bits for LPTMR_PSR_PBYP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LPTMR_PSR_PBYP field.
-#define BR_LPTMR_PSR_PBYP (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR, BP_LPTMR_PSR_PBYP))
-#endif
-
-//! @brief Format value for bitfield LPTMR_PSR_PBYP.
-#define BF_LPTMR_PSR_PBYP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_PSR_PBYP), uint32_t) & BM_LPTMR_PSR_PBYP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PBYP field to a new value.
-#define BW_LPTMR_PSR_PBYP(v) (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR, BP_LPTMR_PSR_PBYP) = (v))
-#endif
-//@}
-
-/*!
- * @name Register LPTMR_PSR, field PRESCALE[6:3] (RW)
- *
- * Configures the size of the Prescaler in Time Counter mode or width of the
- * glitch filter in Pulse Counter mode. PRESCALE must be altered only when the LPTMR
- * is disabled.
- *
- * Values:
- * - 0000 - Prescaler divides the prescaler clock by 2; glitch filter does not
- * support this configuration.
- * - 0001 - Prescaler divides the prescaler clock by 4; glitch filter recognizes
- * change on input pin after 2 rising clock edges.
- * - 0010 - Prescaler divides the prescaler clock by 8; glitch filter recognizes
- * change on input pin after 4 rising clock edges.
- * - 0011 - Prescaler divides the prescaler clock by 16; glitch filter
- * recognizes change on input pin after 8 rising clock edges.
- * - 0100 - Prescaler divides the prescaler clock by 32; glitch filter
- * recognizes change on input pin after 16 rising clock edges.
- * - 0101 - Prescaler divides the prescaler clock by 64; glitch filter
- * recognizes change on input pin after 32 rising clock edges.
- * - 0110 - Prescaler divides the prescaler clock by 128; glitch filter
- * recognizes change on input pin after 64 rising clock edges.
- * - 0111 - Prescaler divides the prescaler clock by 256; glitch filter
- * recognizes change on input pin after 128 rising clock edges.
- * - 1000 - Prescaler divides the prescaler clock by 512; glitch filter
- * recognizes change on input pin after 256 rising clock edges.
- * - 1001 - Prescaler divides the prescaler clock by 1024; glitch filter
- * recognizes change on input pin after 512 rising clock edges.
- * - 1010 - Prescaler divides the prescaler clock by 2048; glitch filter
- * recognizes change on input pin after 1024 rising clock edges.
- * - 1011 - Prescaler divides the prescaler clock by 4096; glitch filter
- * recognizes change on input pin after 2048 rising clock edges.
- * - 1100 - Prescaler divides the prescaler clock by 8192; glitch filter
- * recognizes change on input pin after 4096 rising clock edges.
- * - 1101 - Prescaler divides the prescaler clock by 16,384; glitch filter
- * recognizes change on input pin after 8192 rising clock edges.
- * - 1110 - Prescaler divides the prescaler clock by 32,768; glitch filter
- * recognizes change on input pin after 16,384 rising clock edges.
- * - 1111 - Prescaler divides the prescaler clock by 65,536; glitch filter
- * recognizes change on input pin after 32,768 rising clock edges.
- */
-//@{
-#define BP_LPTMR_PSR_PRESCALE (3U) //!< Bit position for LPTMR_PSR_PRESCALE.
-#define BM_LPTMR_PSR_PRESCALE (0x00000078U) //!< Bit mask for LPTMR_PSR_PRESCALE.
-#define BS_LPTMR_PSR_PRESCALE (4U) //!< Bit field size in bits for LPTMR_PSR_PRESCALE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LPTMR_PSR_PRESCALE field.
-#define BR_LPTMR_PSR_PRESCALE (HW_LPTMR_PSR.B.PRESCALE)
-#endif
-
-//! @brief Format value for bitfield LPTMR_PSR_PRESCALE.
-#define BF_LPTMR_PSR_PRESCALE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_PSR_PRESCALE), uint32_t) & BM_LPTMR_PSR_PRESCALE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PRESCALE field to a new value.
-#define BW_LPTMR_PSR_PRESCALE(v) (HW_LPTMR_PSR_WR((HW_LPTMR_PSR_RD() & ~BM_LPTMR_PSR_PRESCALE) | BF_LPTMR_PSR_PRESCALE(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_LPTMR_CMR - Low Power Timer Compare Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_LPTMR_CMR - Low Power Timer Compare Register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_lptmr_cmr
-{
- uint32_t U;
- struct _hw_lptmr_cmr_bitfields
- {
- uint32_t COMPARE : 16; //!< [15:0] Compare Value
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_lptmr_cmr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire LPTMR_CMR register
- */
-//@{
-#define HW_LPTMR_CMR_ADDR (REGS_LPTMR_BASE + 0x8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_LPTMR_CMR (*(__IO hw_lptmr_cmr_t *) HW_LPTMR_CMR_ADDR)
-#define HW_LPTMR_CMR_RD() (HW_LPTMR_CMR.U)
-#define HW_LPTMR_CMR_WR(v) (HW_LPTMR_CMR.U = (v))
-#define HW_LPTMR_CMR_SET(v) (HW_LPTMR_CMR_WR(HW_LPTMR_CMR_RD() | (v)))
-#define HW_LPTMR_CMR_CLR(v) (HW_LPTMR_CMR_WR(HW_LPTMR_CMR_RD() & ~(v)))
-#define HW_LPTMR_CMR_TOG(v) (HW_LPTMR_CMR_WR(HW_LPTMR_CMR_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual LPTMR_CMR bitfields
- */
-
-/*!
- * @name Register LPTMR_CMR, field COMPARE[15:0] (RW)
- *
- * When the LPTMR is enabled and the CNR equals the value in the CMR and
- * increments, TCF is set and the hardware trigger asserts until the next time the CNR
- * increments. If the CMR is 0, the hardware trigger will remain asserted until
- * the LPTMR is disabled. If the LPTMR is enabled, the CMR must be altered only
- * when TCF is set.
- */
-//@{
-#define BP_LPTMR_CMR_COMPARE (0U) //!< Bit position for LPTMR_CMR_COMPARE.
-#define BM_LPTMR_CMR_COMPARE (0x0000FFFFU) //!< Bit mask for LPTMR_CMR_COMPARE.
-#define BS_LPTMR_CMR_COMPARE (16U) //!< Bit field size in bits for LPTMR_CMR_COMPARE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LPTMR_CMR_COMPARE field.
-#define BR_LPTMR_CMR_COMPARE (HW_LPTMR_CMR.B.COMPARE)
-#endif
-
-//! @brief Format value for bitfield LPTMR_CMR_COMPARE.
-#define BF_LPTMR_CMR_COMPARE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CMR_COMPARE), uint32_t) & BM_LPTMR_CMR_COMPARE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the COMPARE field to a new value.
-#define BW_LPTMR_CMR_COMPARE(v) (HW_LPTMR_CMR_WR((HW_LPTMR_CMR_RD() & ~BM_LPTMR_CMR_COMPARE) | BF_LPTMR_CMR_COMPARE(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_LPTMR_CNR - Low Power Timer Counter Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_LPTMR_CNR - Low Power Timer Counter Register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_lptmr_cnr
-{
- uint32_t U;
- struct _hw_lptmr_cnr_bitfields
- {
- uint32_t COUNTER : 16; //!< [15:0] Counter Value
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_lptmr_cnr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire LPTMR_CNR register
- */
-//@{
-#define HW_LPTMR_CNR_ADDR (REGS_LPTMR_BASE + 0xCU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_LPTMR_CNR (*(__IO hw_lptmr_cnr_t *) HW_LPTMR_CNR_ADDR)
-#define HW_LPTMR_CNR_RD() (HW_LPTMR_CNR.U)
-#define HW_LPTMR_CNR_WR(v) (HW_LPTMR_CNR.U = (v))
-#define HW_LPTMR_CNR_SET(v) (HW_LPTMR_CNR_WR(HW_LPTMR_CNR_RD() | (v)))
-#define HW_LPTMR_CNR_CLR(v) (HW_LPTMR_CNR_WR(HW_LPTMR_CNR_RD() & ~(v)))
-#define HW_LPTMR_CNR_TOG(v) (HW_LPTMR_CNR_WR(HW_LPTMR_CNR_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual LPTMR_CNR bitfields
- */
-
-/*!
- * @name Register LPTMR_CNR, field COUNTER[15:0] (RW)
- */
-//@{
-#define BP_LPTMR_CNR_COUNTER (0U) //!< Bit position for LPTMR_CNR_COUNTER.
-#define BM_LPTMR_CNR_COUNTER (0x0000FFFFU) //!< Bit mask for LPTMR_CNR_COUNTER.
-#define BS_LPTMR_CNR_COUNTER (16U) //!< Bit field size in bits for LPTMR_CNR_COUNTER.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the LPTMR_CNR_COUNTER field.
-#define BR_LPTMR_CNR_COUNTER (HW_LPTMR_CNR.B.COUNTER)
-#endif
-
-//! @brief Format value for bitfield LPTMR_CNR_COUNTER.
-#define BF_LPTMR_CNR_COUNTER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CNR_COUNTER), uint32_t) & BM_LPTMR_CNR_COUNTER)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the COUNTER field to a new value.
-#define BW_LPTMR_CNR_COUNTER(v) (HW_LPTMR_CNR_WR((HW_LPTMR_CNR_RD() & ~BM_LPTMR_CNR_COUNTER) | BF_LPTMR_CNR_COUNTER(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_lptmr_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All LPTMR module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_lptmr
-{
- __IO hw_lptmr_csr_t CSR; //!< [0x0] Low Power Timer Control Status Register
- __IO hw_lptmr_psr_t PSR; //!< [0x4] Low Power Timer Prescale Register
- __IO hw_lptmr_cmr_t CMR; //!< [0x8] Low Power Timer Compare Register
- __IO hw_lptmr_cnr_t CNR; //!< [0xC] Low Power Timer Counter Register
-} hw_lptmr_t;
-#pragma pack()
-
-//! @brief Macro to access all LPTMR registers.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_LPTMR</code>.
-#define HW_LPTMR (*(hw_lptmr_t *) REGS_LPTMR_BASE)
-#endif
-
-#endif // __HW_LPTMR_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_mcg.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1939 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_MCG_REGISTERS_H__
-#define __HW_MCG_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 MCG
- *
- * Multipurpose Clock Generator module
- *
- * Registers defined in this header file:
- * - HW_MCG_C1 - MCG Control 1 Register
- * - HW_MCG_C2 - MCG Control 2 Register
- * - HW_MCG_C3 - MCG Control 3 Register
- * - HW_MCG_C4 - MCG Control 4 Register
- * - HW_MCG_C5 - MCG Control 5 Register
- * - HW_MCG_C6 - MCG Control 6 Register
- * - HW_MCG_S - MCG Status Register
- * - HW_MCG_SC - MCG Status and Control Register
- * - HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register
- * - HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register
- * - HW_MCG_C7 - MCG Control 7 Register
- * - HW_MCG_C8 - MCG Control 8 Register
- *
- * - hw_mcg_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_MCG_BASE
-#define HW_MCG_INSTANCE_COUNT (1U) //!< Number of instances of the MCG module.
-#define REGS_MCG_BASE (0x40064000U) //!< Base address for MCG.
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_MCG_C1 - MCG Control 1 Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_MCG_C1 - MCG Control 1 Register (RW)
- *
- * Reset value: 0x04U
- */
-typedef union _hw_mcg_c1
-{
- uint8_t U;
- struct _hw_mcg_c1_bitfields
- {
- uint8_t IREFSTEN : 1; //!< [0] Internal Reference Stop Enable
- uint8_t IRCLKEN : 1; //!< [1] Internal Reference Clock Enable
- uint8_t IREFS : 1; //!< [2] Internal Reference Select
- uint8_t FRDIV : 3; //!< [5:3] FLL External Reference Divider
- uint8_t CLKS : 2; //!< [7:6] Clock Source Select
- } B;
-} hw_mcg_c1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire MCG_C1 register
- */
-//@{
-#define HW_MCG_C1_ADDR (REGS_MCG_BASE + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_MCG_C1 (*(__IO hw_mcg_c1_t *) HW_MCG_C1_ADDR)
-#define HW_MCG_C1_RD() (HW_MCG_C1.U)
-#define HW_MCG_C1_WR(v) (HW_MCG_C1.U = (v))
-#define HW_MCG_C1_SET(v) (HW_MCG_C1_WR(HW_MCG_C1_RD() | (v)))
-#define HW_MCG_C1_CLR(v) (HW_MCG_C1_WR(HW_MCG_C1_RD() & ~(v)))
-#define HW_MCG_C1_TOG(v) (HW_MCG_C1_WR(HW_MCG_C1_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual MCG_C1 bitfields
- */
-
-/*!
- * @name Register MCG_C1, field IREFSTEN[0] (RW)
- *
- * Controls whether or not the internal reference clock remains enabled when the
- * MCG enters Stop mode.
- *
- * Values:
- * - 0 - Internal reference clock is disabled in Stop mode.
- * - 1 - Internal reference clock is enabled in Stop mode if IRCLKEN is set or
- * if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
- */
-//@{
-#define BP_MCG_C1_IREFSTEN (0U) //!< Bit position for MCG_C1_IREFSTEN.
-#define BM_MCG_C1_IREFSTEN (0x01U) //!< Bit mask for MCG_C1_IREFSTEN.
-#define BS_MCG_C1_IREFSTEN (1U) //!< Bit field size in bits for MCG_C1_IREFSTEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_C1_IREFSTEN field.
-#define BR_MCG_C1_IREFSTEN (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IREFSTEN))
-#endif
-
-//! @brief Format value for bitfield MCG_C1_IREFSTEN.
-#define BF_MCG_C1_IREFSTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C1_IREFSTEN), uint8_t) & BM_MCG_C1_IREFSTEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IREFSTEN field to a new value.
-#define BW_MCG_C1_IREFSTEN(v) (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IREFSTEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCG_C1, field IRCLKEN[1] (RW)
- *
- * Enables the internal reference clock for use as MCGIRCLK.
- *
- * Values:
- * - 0 - MCGIRCLK inactive.
- * - 1 - MCGIRCLK active.
- */
-//@{
-#define BP_MCG_C1_IRCLKEN (1U) //!< Bit position for MCG_C1_IRCLKEN.
-#define BM_MCG_C1_IRCLKEN (0x02U) //!< Bit mask for MCG_C1_IRCLKEN.
-#define BS_MCG_C1_IRCLKEN (1U) //!< Bit field size in bits for MCG_C1_IRCLKEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_C1_IRCLKEN field.
-#define BR_MCG_C1_IRCLKEN (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IRCLKEN))
-#endif
-
-//! @brief Format value for bitfield MCG_C1_IRCLKEN.
-#define BF_MCG_C1_IRCLKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C1_IRCLKEN), uint8_t) & BM_MCG_C1_IRCLKEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IRCLKEN field to a new value.
-#define BW_MCG_C1_IRCLKEN(v) (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IRCLKEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCG_C1, field IREFS[2] (RW)
- *
- * Selects the reference clock source for the FLL.
- *
- * Values:
- * - 0 - External reference clock is selected.
- * - 1 - The slow internal reference clock is selected.
- */
-//@{
-#define BP_MCG_C1_IREFS (2U) //!< Bit position for MCG_C1_IREFS.
-#define BM_MCG_C1_IREFS (0x04U) //!< Bit mask for MCG_C1_IREFS.
-#define BS_MCG_C1_IREFS (1U) //!< Bit field size in bits for MCG_C1_IREFS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_C1_IREFS field.
-#define BR_MCG_C1_IREFS (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IREFS))
-#endif
-
-//! @brief Format value for bitfield MCG_C1_IREFS.
-#define BF_MCG_C1_IREFS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C1_IREFS), uint8_t) & BM_MCG_C1_IREFS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IREFS field to a new value.
-#define BW_MCG_C1_IREFS(v) (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IREFS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCG_C1, field FRDIV[5:3] (RW)
- *
- * Selects the amount to divide down the external reference clock for the FLL.
- * The resulting frequency must be in the range 31.25 kHz to 39.0625 kHz (This is
- * required when FLL/DCO is the clock source for MCGOUTCLK . In FBE mode, it is
- * not required to meet this range, but it is recommended in the cases when trying
- * to enter a FLL mode from FBE).
- *
- * Values:
- * - 000 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE
- * values, Divide Factor is 32.
- * - 001 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE
- * values, Divide Factor is 64.
- * - 010 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE
- * values, Divide Factor is 128.
- * - 011 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE
- * values, Divide Factor is 256.
- * - 100 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE
- * values, Divide Factor is 512.
- * - 101 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE
- * values, Divide Factor is 1024.
- * - 110 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE
- * values, Divide Factor is 1280 .
- * - 111 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE
- * values, Divide Factor is 1536 .
- */
-//@{
-#define BP_MCG_C1_FRDIV (3U) //!< Bit position for MCG_C1_FRDIV.
-#define BM_MCG_C1_FRDIV (0x38U) //!< Bit mask for MCG_C1_FRDIV.
-#define BS_MCG_C1_FRDIV (3U) //!< Bit field size in bits for MCG_C1_FRDIV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_C1_FRDIV field.
-#define BR_MCG_C1_FRDIV (HW_MCG_C1.B.FRDIV)
-#endif
-
-//! @brief Format value for bitfield MCG_C1_FRDIV.
-#define BF_MCG_C1_FRDIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C1_FRDIV), uint8_t) & BM_MCG_C1_FRDIV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FRDIV field to a new value.
-#define BW_MCG_C1_FRDIV(v) (HW_MCG_C1_WR((HW_MCG_C1_RD() & ~BM_MCG_C1_FRDIV) | BF_MCG_C1_FRDIV(v)))
-#endif
-//@}
-
-/*!
- * @name Register MCG_C1, field CLKS[7:6] (RW)
- *
- * Selects the clock source for MCGOUTCLK .
- *
- * Values:
- * - 00 - Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control
- * bit).
- * - 01 - Encoding 1 - Internal reference clock is selected.
- * - 10 - Encoding 2 - External reference clock is selected.
- * - 11 - Encoding 3 - Reserved.
- */
-//@{
-#define BP_MCG_C1_CLKS (6U) //!< Bit position for MCG_C1_CLKS.
-#define BM_MCG_C1_CLKS (0xC0U) //!< Bit mask for MCG_C1_CLKS.
-#define BS_MCG_C1_CLKS (2U) //!< Bit field size in bits for MCG_C1_CLKS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_C1_CLKS field.
-#define BR_MCG_C1_CLKS (HW_MCG_C1.B.CLKS)
-#endif
-
-//! @brief Format value for bitfield MCG_C1_CLKS.
-#define BF_MCG_C1_CLKS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C1_CLKS), uint8_t) & BM_MCG_C1_CLKS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CLKS field to a new value.
-#define BW_MCG_C1_CLKS(v) (HW_MCG_C1_WR((HW_MCG_C1_RD() & ~BM_MCG_C1_CLKS) | BF_MCG_C1_CLKS(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_MCG_C2 - MCG Control 2 Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_MCG_C2 - MCG Control 2 Register (RW)
- *
- * Reset value: 0x80U
- */
-typedef union _hw_mcg_c2
-{
- uint8_t U;
- struct _hw_mcg_c2_bitfields
- {
- uint8_t IRCS : 1; //!< [0] Internal Reference Clock Select
- uint8_t LP : 1; //!< [1] Low Power Select
- uint8_t EREFS : 1; //!< [2] External Reference Select
- uint8_t HGO : 1; //!< [3] High Gain Oscillator Select
- uint8_t RANGE : 2; //!< [5:4] Frequency Range Select
- uint8_t FCFTRIM : 1; //!< [6] Fast Internal Reference Clock Fine Trim
- uint8_t LOCRE0 : 1; //!< [7] Loss of Clock Reset Enable
- } B;
-} hw_mcg_c2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire MCG_C2 register
- */
-//@{
-#define HW_MCG_C2_ADDR (REGS_MCG_BASE + 0x1U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_MCG_C2 (*(__IO hw_mcg_c2_t *) HW_MCG_C2_ADDR)
-#define HW_MCG_C2_RD() (HW_MCG_C2.U)
-#define HW_MCG_C2_WR(v) (HW_MCG_C2.U = (v))
-#define HW_MCG_C2_SET(v) (HW_MCG_C2_WR(HW_MCG_C2_RD() | (v)))
-#define HW_MCG_C2_CLR(v) (HW_MCG_C2_WR(HW_MCG_C2_RD() & ~(v)))
-#define HW_MCG_C2_TOG(v) (HW_MCG_C2_WR(HW_MCG_C2_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual MCG_C2 bitfields
- */
-
-/*!
- * @name Register MCG_C2, field IRCS[0] (RW)
- *
- * Selects between the fast or slow internal reference clock source.
- *
- * Values:
- * - 0 - Slow internal reference clock selected.
- * - 1 - Fast internal reference clock selected.
- */
-//@{
-#define BP_MCG_C2_IRCS (0U) //!< Bit position for MCG_C2_IRCS.
-#define BM_MCG_C2_IRCS (0x01U) //!< Bit mask for MCG_C2_IRCS.
-#define BS_MCG_C2_IRCS (1U) //!< Bit field size in bits for MCG_C2_IRCS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_C2_IRCS field.
-#define BR_MCG_C2_IRCS (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_IRCS))
-#endif
-
-//! @brief Format value for bitfield MCG_C2_IRCS.
-#define BF_MCG_C2_IRCS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_IRCS), uint8_t) & BM_MCG_C2_IRCS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IRCS field to a new value.
-#define BW_MCG_C2_IRCS(v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_IRCS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCG_C2, field LP[1] (RW)
- *
- * Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. In FBE or
- * PBE modes, setting this bit to 1 will transition the MCG into BLPE mode; in
- * FBI mode, setting this bit to 1 will transition the MCG into BLPI mode. In any
- * other MCG mode, LP bit has no affect.
- *
- * Values:
- * - 0 - FLL or PLL is not disabled in bypass modes.
- * - 1 - FLL or PLL is disabled in bypass modes (lower power)
- */
-//@{
-#define BP_MCG_C2_LP (1U) //!< Bit position for MCG_C2_LP.
-#define BM_MCG_C2_LP (0x02U) //!< Bit mask for MCG_C2_LP.
-#define BS_MCG_C2_LP (1U) //!< Bit field size in bits for MCG_C2_LP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_C2_LP field.
-#define BR_MCG_C2_LP (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_LP))
-#endif
-
-//! @brief Format value for bitfield MCG_C2_LP.
-#define BF_MCG_C2_LP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_LP), uint8_t) & BM_MCG_C2_LP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LP field to a new value.
-#define BW_MCG_C2_LP(v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_LP) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCG_C2, field EREFS[2] (RW)
- *
- * Selects the source for the external reference clock. See the Oscillator (OSC)
- * chapter for more details.
- *
- * Values:
- * - 0 - External reference clock requested.
- * - 1 - Oscillator requested.
- */
-//@{
-#define BP_MCG_C2_EREFS (2U) //!< Bit position for MCG_C2_EREFS.
-#define BM_MCG_C2_EREFS (0x04U) //!< Bit mask for MCG_C2_EREFS.
-#define BS_MCG_C2_EREFS (1U) //!< Bit field size in bits for MCG_C2_EREFS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_C2_EREFS field.
-#define BR_MCG_C2_EREFS (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_EREFS))
-#endif
-
-//! @brief Format value for bitfield MCG_C2_EREFS.
-#define BF_MCG_C2_EREFS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_EREFS), uint8_t) & BM_MCG_C2_EREFS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EREFS field to a new value.
-#define BW_MCG_C2_EREFS(v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_EREFS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCG_C2, field HGO[3] (RW)
- *
- * Controls the crystal oscillator mode of operation. See the Oscillator (OSC)
- * chapter for more details.
- *
- * Values:
- * - 0 - Configure crystal oscillator for low-power operation.
- * - 1 - Configure crystal oscillator for high-gain operation.
- */
-//@{
-#define BP_MCG_C2_HGO (3U) //!< Bit position for MCG_C2_HGO.
-#define BM_MCG_C2_HGO (0x08U) //!< Bit mask for MCG_C2_HGO.
-#define BS_MCG_C2_HGO (1U) //!< Bit field size in bits for MCG_C2_HGO.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_C2_HGO field.
-#define BR_MCG_C2_HGO (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_HGO))
-#endif
-
-//! @brief Format value for bitfield MCG_C2_HGO.
-#define BF_MCG_C2_HGO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_HGO), uint8_t) & BM_MCG_C2_HGO)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the HGO field to a new value.
-#define BW_MCG_C2_HGO(v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_HGO) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCG_C2, field RANGE[5:4] (RW)
- *
- * Selects the frequency range for the crystal oscillator or external clock
- * source. See the Oscillator (OSC) chapter for more details and the device data
- * sheet for the frequency ranges used.
- *
- * Values:
- * - 00 - Encoding 0 - Low frequency range selected for the crystal oscillator .
- * - 01 - Encoding 1 - High frequency range selected for the crystal oscillator .
- */
-//@{
-#define BP_MCG_C2_RANGE (4U) //!< Bit position for MCG_C2_RANGE.
-#define BM_MCG_C2_RANGE (0x30U) //!< Bit mask for MCG_C2_RANGE.
-#define BS_MCG_C2_RANGE (2U) //!< Bit field size in bits for MCG_C2_RANGE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_C2_RANGE field.
-#define BR_MCG_C2_RANGE (HW_MCG_C2.B.RANGE)
-#endif
-
-//! @brief Format value for bitfield MCG_C2_RANGE.
-#define BF_MCG_C2_RANGE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_RANGE), uint8_t) & BM_MCG_C2_RANGE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RANGE field to a new value.
-#define BW_MCG_C2_RANGE(v) (HW_MCG_C2_WR((HW_MCG_C2_RD() & ~BM_MCG_C2_RANGE) | BF_MCG_C2_RANGE(v)))
-#endif
-//@}
-
-/*!
- * @name Register MCG_C2, field FCFTRIM[6] (RW)
- *
- * FCFTRIM controls the smallest adjustment of the fast internal reference clock
- * frequency. Setting FCFTRIM increases the period and clearing FCFTRIM
- * decreases the period by the smallest amount possible. If an FCFTRIM value stored in
- * nonvolatile memory is to be used, it is your responsibility to copy that value
- * from the nonvolatile memory location to this bit.
- */
-//@{
-#define BP_MCG_C2_FCFTRIM (6U) //!< Bit position for MCG_C2_FCFTRIM.
-#define BM_MCG_C2_FCFTRIM (0x40U) //!< Bit mask for MCG_C2_FCFTRIM.
-#define BS_MCG_C2_FCFTRIM (1U) //!< Bit field size in bits for MCG_C2_FCFTRIM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_C2_FCFTRIM field.
-#define BR_MCG_C2_FCFTRIM (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_FCFTRIM))
-#endif
-
-//! @brief Format value for bitfield MCG_C2_FCFTRIM.
-#define BF_MCG_C2_FCFTRIM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_FCFTRIM), uint8_t) & BM_MCG_C2_FCFTRIM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FCFTRIM field to a new value.
-#define BW_MCG_C2_FCFTRIM(v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_FCFTRIM) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCG_C2, field LOCRE0[7] (RW)
- *
- * Determines whether an interrupt or a reset request is made following a loss
- * of OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is
- * set.
- *
- * Values:
- * - 0 - Interrupt request is generated on a loss of OSC0 external reference
- * clock.
- * - 1 - Generate a reset request on a loss of OSC0 external reference clock.
- */
-//@{
-#define BP_MCG_C2_LOCRE0 (7U) //!< Bit position for MCG_C2_LOCRE0.
-#define BM_MCG_C2_LOCRE0 (0x80U) //!< Bit mask for MCG_C2_LOCRE0.
-#define BS_MCG_C2_LOCRE0 (1U) //!< Bit field size in bits for MCG_C2_LOCRE0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_C2_LOCRE0 field.
-#define BR_MCG_C2_LOCRE0 (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_LOCRE0))
-#endif
-
-//! @brief Format value for bitfield MCG_C2_LOCRE0.
-#define BF_MCG_C2_LOCRE0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_LOCRE0), uint8_t) & BM_MCG_C2_LOCRE0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LOCRE0 field to a new value.
-#define BW_MCG_C2_LOCRE0(v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_LOCRE0) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_MCG_C3 - MCG Control 3 Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_MCG_C3 - MCG Control 3 Register (RW)
- *
- * Reset value: 0x00U
- */
-typedef union _hw_mcg_c3
-{
- uint8_t U;
- struct _hw_mcg_c3_bitfields
- {
- uint8_t SCTRIM : 8; //!< [7:0] Slow Internal Reference Clock Trim
- //! Setting
- } B;
-} hw_mcg_c3_t;
-#endif
-
-/*!
- * @name Constants and macros for entire MCG_C3 register
- */
-//@{
-#define HW_MCG_C3_ADDR (REGS_MCG_BASE + 0x2U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_MCG_C3 (*(__IO hw_mcg_c3_t *) HW_MCG_C3_ADDR)
-#define HW_MCG_C3_RD() (HW_MCG_C3.U)
-#define HW_MCG_C3_WR(v) (HW_MCG_C3.U = (v))
-#define HW_MCG_C3_SET(v) (HW_MCG_C3_WR(HW_MCG_C3_RD() | (v)))
-#define HW_MCG_C3_CLR(v) (HW_MCG_C3_WR(HW_MCG_C3_RD() & ~(v)))
-#define HW_MCG_C3_TOG(v) (HW_MCG_C3_WR(HW_MCG_C3_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual MCG_C3 bitfields
- */
-
-/*!
- * @name Register MCG_C3, field SCTRIM[7:0] (RW)
- *
- * SCTRIM A value for SCTRIM is loaded during reset from a factory programmed
- * location. controls the slow internal reference clock frequency by controlling
- * the slow internal reference clock period. The SCTRIM bits are binary weighted,
- * that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value
- * increases the period, and decreasing the value decreases the period. An additional
- * fine trim bit is available in C4 register as the SCFTRIM bit. Upon reset,
- * this value is loaded with a factory trim value. If an SCTRIM value stored in
- * nonvolatile memory is to be used, it is your responsibility to copy that value
- * from the nonvolatile memory location to this register.
- */
-//@{
-#define BP_MCG_C3_SCTRIM (0U) //!< Bit position for MCG_C3_SCTRIM.
-#define BM_MCG_C3_SCTRIM (0xFFU) //!< Bit mask for MCG_C3_SCTRIM.
-#define BS_MCG_C3_SCTRIM (8U) //!< Bit field size in bits for MCG_C3_SCTRIM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_C3_SCTRIM field.
-#define BR_MCG_C3_SCTRIM (HW_MCG_C3.U)
-#endif
-
-//! @brief Format value for bitfield MCG_C3_SCTRIM.
-#define BF_MCG_C3_SCTRIM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C3_SCTRIM), uint8_t) & BM_MCG_C3_SCTRIM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SCTRIM field to a new value.
-#define BW_MCG_C3_SCTRIM(v) (HW_MCG_C3_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_MCG_C4 - MCG Control 4 Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_MCG_C4 - MCG Control 4 Register (RW)
- *
- * Reset value: 0x00U
- *
- * Reset values for DRST and DMX32 bits are 0.
- */
-typedef union _hw_mcg_c4
-{
- uint8_t U;
- struct _hw_mcg_c4_bitfields
- {
- uint8_t SCFTRIM : 1; //!< [0] Slow Internal Reference Clock Fine Trim
- uint8_t FCTRIM : 4; //!< [4:1] Fast Internal Reference Clock Trim
- //! Setting
- uint8_t DRST_DRS : 2; //!< [6:5] DCO Range Select
- uint8_t DMX32 : 1; //!< [7] DCO Maximum Frequency with 32.768 kHz
- //! Reference
- } B;
-} hw_mcg_c4_t;
-#endif
-
-/*!
- * @name Constants and macros for entire MCG_C4 register
- */
-//@{
-#define HW_MCG_C4_ADDR (REGS_MCG_BASE + 0x3U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_MCG_C4 (*(__IO hw_mcg_c4_t *) HW_MCG_C4_ADDR)
-#define HW_MCG_C4_RD() (HW_MCG_C4.U)
-#define HW_MCG_C4_WR(v) (HW_MCG_C4.U = (v))
-#define HW_MCG_C4_SET(v) (HW_MCG_C4_WR(HW_MCG_C4_RD() | (v)))
-#define HW_MCG_C4_CLR(v) (HW_MCG_C4_WR(HW_MCG_C4_RD() & ~(v)))
-#define HW_MCG_C4_TOG(v) (HW_MCG_C4_WR(HW_MCG_C4_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual MCG_C4 bitfields
- */
-
-/*!
- * @name Register MCG_C4, field SCFTRIM[0] (RW)
- *
- * SCFTRIM A value for SCFTRIM is loaded during reset from a factory programmed
- * location . controls the smallest adjustment of the slow internal reference
- * clock frequency. Setting SCFTRIM increases the period and clearing SCFTRIM
- * decreases the period by the smallest amount possible. If an SCFTRIM value stored in
- * nonvolatile memory is to be used, it is your responsibility to copy that value
- * from the nonvolatile memory location to this bit.
- */
-//@{
-#define BP_MCG_C4_SCFTRIM (0U) //!< Bit position for MCG_C4_SCFTRIM.
-#define BM_MCG_C4_SCFTRIM (0x01U) //!< Bit mask for MCG_C4_SCFTRIM.
-#define BS_MCG_C4_SCFTRIM (1U) //!< Bit field size in bits for MCG_C4_SCFTRIM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_C4_SCFTRIM field.
-#define BR_MCG_C4_SCFTRIM (BITBAND_ACCESS8(HW_MCG_C4_ADDR, BP_MCG_C4_SCFTRIM))
-#endif
-
-//! @brief Format value for bitfield MCG_C4_SCFTRIM.
-#define BF_MCG_C4_SCFTRIM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C4_SCFTRIM), uint8_t) & BM_MCG_C4_SCFTRIM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SCFTRIM field to a new value.
-#define BW_MCG_C4_SCFTRIM(v) (BITBAND_ACCESS8(HW_MCG_C4_ADDR, BP_MCG_C4_SCFTRIM) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCG_C4, field FCTRIM[4:1] (RW)
- *
- * FCTRIM A value for FCTRIM is loaded during reset from a factory programmed
- * location. controls the fast internal reference clock frequency by controlling
- * the fast internal reference clock period. The FCTRIM bits are binary weighted,
- * that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value
- * increases the period, and decreasing the value decreases the period. If an
- * FCTRIM[3:0] value stored in nonvolatile memory is to be used, it is your
- * responsibility to copy that value from the nonvolatile memory location to this register.
- */
-//@{
-#define BP_MCG_C4_FCTRIM (1U) //!< Bit position for MCG_C4_FCTRIM.
-#define BM_MCG_C4_FCTRIM (0x1EU) //!< Bit mask for MCG_C4_FCTRIM.
-#define BS_MCG_C4_FCTRIM (4U) //!< Bit field size in bits for MCG_C4_FCTRIM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_C4_FCTRIM field.
-#define BR_MCG_C4_FCTRIM (HW_MCG_C4.B.FCTRIM)
-#endif
-
-//! @brief Format value for bitfield MCG_C4_FCTRIM.
-#define BF_MCG_C4_FCTRIM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C4_FCTRIM), uint8_t) & BM_MCG_C4_FCTRIM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FCTRIM field to a new value.
-#define BW_MCG_C4_FCTRIM(v) (HW_MCG_C4_WR((HW_MCG_C4_RD() & ~BM_MCG_C4_FCTRIM) | BF_MCG_C4_FCTRIM(v)))
-#endif
-//@}
-
-/*!
- * @name Register MCG_C4, field DRST_DRS[6:5] (RW)
- *
- * The DRS bits select the frequency range for the FLL output, DCOOUT. When the
- * LP bit is set, writes to the DRS bits are ignored. The DRST read field
- * indicates the current frequency range for DCOOUT. The DRST field does not update
- * immediately after a write to the DRS field due to internal synchronization between
- * clock domains. See the DCO Frequency Range table for more details.
- *
- * Values:
- * - 00 - Encoding 0 - Low range (reset default).
- * - 01 - Encoding 1 - Mid range.
- * - 10 - Encoding 2 - Mid-high range.
- * - 11 - Encoding 3 - High range.
- */
-//@{
-#define BP_MCG_C4_DRST_DRS (5U) //!< Bit position for MCG_C4_DRST_DRS.
-#define BM_MCG_C4_DRST_DRS (0x60U) //!< Bit mask for MCG_C4_DRST_DRS.
-#define BS_MCG_C4_DRST_DRS (2U) //!< Bit field size in bits for MCG_C4_DRST_DRS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_C4_DRST_DRS field.
-#define BR_MCG_C4_DRST_DRS (HW_MCG_C4.B.DRST_DRS)
-#endif
-
-//! @brief Format value for bitfield MCG_C4_DRST_DRS.
-#define BF_MCG_C4_DRST_DRS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C4_DRST_DRS), uint8_t) & BM_MCG_C4_DRST_DRS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DRST_DRS field to a new value.
-#define BW_MCG_C4_DRST_DRS(v) (HW_MCG_C4_WR((HW_MCG_C4_RD() & ~BM_MCG_C4_DRST_DRS) | BF_MCG_C4_DRST_DRS(v)))
-#endif
-//@}
-
-/*!
- * @name Register MCG_C4, field DMX32[7] (RW)
- *
- * The DMX32 bit controls whether the DCO frequency range is narrowed to its
- * maximum frequency with a 32.768 kHz reference. The following table identifies
- * settings for the DCO frequency range. The system clocks derived from this source
- * should not exceed their specified maximums. DRST_DRS DMX32 Reference Range FLL
- * Factor DCO Range 00 0 31.25-39.0625 kHz 640 20-25 MHz 1 32.768 kHz 732 24 MHz
- * 01 0 31.25-39.0625 kHz 1280 40-50 MHz 1 32.768 kHz 1464 48 MHz 10 0
- * 31.25-39.0625 kHz 1920 60-75 MHz 1 32.768 kHz 2197 72 MHz 11 0 31.25-39.0625 kHz 2560
- * 80-100 MHz 1 32.768 kHz 2929 96 MHz
- *
- * Values:
- * - 0 - DCO has a default range of 25%.
- * - 1 - DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
- */
-//@{
-#define BP_MCG_C4_DMX32 (7U) //!< Bit position for MCG_C4_DMX32.
-#define BM_MCG_C4_DMX32 (0x80U) //!< Bit mask for MCG_C4_DMX32.
-#define BS_MCG_C4_DMX32 (1U) //!< Bit field size in bits for MCG_C4_DMX32.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_C4_DMX32 field.
-#define BR_MCG_C4_DMX32 (BITBAND_ACCESS8(HW_MCG_C4_ADDR, BP_MCG_C4_DMX32))
-#endif
-
-//! @brief Format value for bitfield MCG_C4_DMX32.
-#define BF_MCG_C4_DMX32(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C4_DMX32), uint8_t) & BM_MCG_C4_DMX32)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DMX32 field to a new value.
-#define BW_MCG_C4_DMX32(v) (BITBAND_ACCESS8(HW_MCG_C4_ADDR, BP_MCG_C4_DMX32) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_MCG_C5 - MCG Control 5 Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_MCG_C5 - MCG Control 5 Register (RW)
- *
- * Reset value: 0x00U
- */
-typedef union _hw_mcg_c5
-{
- uint8_t U;
- struct _hw_mcg_c5_bitfields
- {
- uint8_t PRDIV0 : 5; //!< [4:0] PLL External Reference Divider
- uint8_t PLLSTEN0 : 1; //!< [5] PLL Stop Enable
- uint8_t PLLCLKEN0 : 1; //!< [6] PLL Clock Enable
- uint8_t RESERVED0 : 1; //!< [7]
- } B;
-} hw_mcg_c5_t;
-#endif
-
-/*!
- * @name Constants and macros for entire MCG_C5 register
- */
-//@{
-#define HW_MCG_C5_ADDR (REGS_MCG_BASE + 0x4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_MCG_C5 (*(__IO hw_mcg_c5_t *) HW_MCG_C5_ADDR)
-#define HW_MCG_C5_RD() (HW_MCG_C5.U)
-#define HW_MCG_C5_WR(v) (HW_MCG_C5.U = (v))
-#define HW_MCG_C5_SET(v) (HW_MCG_C5_WR(HW_MCG_C5_RD() | (v)))
-#define HW_MCG_C5_CLR(v) (HW_MCG_C5_WR(HW_MCG_C5_RD() & ~(v)))
-#define HW_MCG_C5_TOG(v) (HW_MCG_C5_WR(HW_MCG_C5_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual MCG_C5 bitfields
- */
-
-/*!
- * @name Register MCG_C5, field PRDIV0[4:0] (RW)
- *
- * Selects the amount to divide down the external reference clock for the PLL.
- * The resulting frequency must be in the range of 2 MHz to 4 MHz. After the PLL
- * is enabled (by setting either PLLCLKEN 0 or PLLS), the PRDIV 0 value must not
- * be changed when LOCK0 is zero. PLL External Reference Divide Factor PRDIV 0
- * Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor
- * 00000 1 01000 9 10000 17 11000 25 00001 2 01001 10 10001 18 11001 Reserved
- * 00010 3 01010 11 10010 19 11010 Reserved 00011 4 01011 12 10011 20 11011 Reserved
- * 00100 5 01100 13 10100 21 11100 Reserved 00101 6 01101 14 10101 22 11101
- * Reserved 00110 7 01110 15 10110 23 11110 Reserved 00111 8 01111 16 10111 24 11111
- * Reserved
- */
-//@{
-#define BP_MCG_C5_PRDIV0 (0U) //!< Bit position for MCG_C5_PRDIV0.
-#define BM_MCG_C5_PRDIV0 (0x1FU) //!< Bit mask for MCG_C5_PRDIV0.
-#define BS_MCG_C5_PRDIV0 (5U) //!< Bit field size in bits for MCG_C5_PRDIV0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_C5_PRDIV0 field.
-#define BR_MCG_C5_PRDIV0 (HW_MCG_C5.B.PRDIV0)
-#endif
-
-//! @brief Format value for bitfield MCG_C5_PRDIV0.
-#define BF_MCG_C5_PRDIV0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C5_PRDIV0), uint8_t) & BM_MCG_C5_PRDIV0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PRDIV0 field to a new value.
-#define BW_MCG_C5_PRDIV0(v) (HW_MCG_C5_WR((HW_MCG_C5_RD() & ~BM_MCG_C5_PRDIV0) | BF_MCG_C5_PRDIV0(v)))
-#endif
-//@}
-
-/*!
- * @name Register MCG_C5, field PLLSTEN0[5] (RW)
- *
- * Enables the PLL Clock during Normal Stop. In Low Power Stop mode, the PLL
- * clock gets disabled even if PLLSTEN 0 =1. All other power modes, PLLSTEN 0 bit
- * has no affect and does not enable the PLL Clock to run if it is written to 1.
- *
- * Values:
- * - 0 - MCGPLLCLK is disabled in any of the Stop modes.
- * - 1 - MCGPLLCLK is enabled if system is in Normal Stop mode.
- */
-//@{
-#define BP_MCG_C5_PLLSTEN0 (5U) //!< Bit position for MCG_C5_PLLSTEN0.
-#define BM_MCG_C5_PLLSTEN0 (0x20U) //!< Bit mask for MCG_C5_PLLSTEN0.
-#define BS_MCG_C5_PLLSTEN0 (1U) //!< Bit field size in bits for MCG_C5_PLLSTEN0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_C5_PLLSTEN0 field.
-#define BR_MCG_C5_PLLSTEN0 (BITBAND_ACCESS8(HW_MCG_C5_ADDR, BP_MCG_C5_PLLSTEN0))
-#endif
-
-//! @brief Format value for bitfield MCG_C5_PLLSTEN0.
-#define BF_MCG_C5_PLLSTEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C5_PLLSTEN0), uint8_t) & BM_MCG_C5_PLLSTEN0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PLLSTEN0 field to a new value.
-#define BW_MCG_C5_PLLSTEN0(v) (BITBAND_ACCESS8(HW_MCG_C5_ADDR, BP_MCG_C5_PLLSTEN0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCG_C5, field PLLCLKEN0[6] (RW)
- *
- * Enables the PLL independent of PLLS and enables the PLL clock for use as
- * MCGPLLCLK. (PRDIV 0 needs to be programmed to the correct divider to generate a
- * PLL reference clock in the range of 2 - 4 MHz range prior to setting the
- * PLLCLKEN 0 bit). Setting PLLCLKEN 0 will enable the external oscillator if not
- * already enabled. Whenever the PLL is being enabled by means of the PLLCLKEN 0 bit,
- * and the external oscillator is being used as the reference clock, the OSCINIT 0
- * bit should be checked to make sure it is set.
- *
- * Values:
- * - 0 - MCGPLLCLK is inactive.
- * - 1 - MCGPLLCLK is active.
- */
-//@{
-#define BP_MCG_C5_PLLCLKEN0 (6U) //!< Bit position for MCG_C5_PLLCLKEN0.
-#define BM_MCG_C5_PLLCLKEN0 (0x40U) //!< Bit mask for MCG_C5_PLLCLKEN0.
-#define BS_MCG_C5_PLLCLKEN0 (1U) //!< Bit field size in bits for MCG_C5_PLLCLKEN0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_C5_PLLCLKEN0 field.
-#define BR_MCG_C5_PLLCLKEN0 (BITBAND_ACCESS8(HW_MCG_C5_ADDR, BP_MCG_C5_PLLCLKEN0))
-#endif
-
-//! @brief Format value for bitfield MCG_C5_PLLCLKEN0.
-#define BF_MCG_C5_PLLCLKEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C5_PLLCLKEN0), uint8_t) & BM_MCG_C5_PLLCLKEN0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PLLCLKEN0 field to a new value.
-#define BW_MCG_C5_PLLCLKEN0(v) (BITBAND_ACCESS8(HW_MCG_C5_ADDR, BP_MCG_C5_PLLCLKEN0) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_MCG_C6 - MCG Control 6 Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_MCG_C6 - MCG Control 6 Register (RW)
- *
- * Reset value: 0x00U
- */
-typedef union _hw_mcg_c6
-{
- uint8_t U;
- struct _hw_mcg_c6_bitfields
- {
- uint8_t VDIV0 : 5; //!< [4:0] VCO 0 Divider
- uint8_t CME0 : 1; //!< [5] Clock Monitor Enable
- uint8_t PLLS : 1; //!< [6] PLL Select
- uint8_t LOLIE0 : 1; //!< [7] Loss of Lock Interrrupt Enable
- } B;
-} hw_mcg_c6_t;
-#endif
-
-/*!
- * @name Constants and macros for entire MCG_C6 register
- */
-//@{
-#define HW_MCG_C6_ADDR (REGS_MCG_BASE + 0x5U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_MCG_C6 (*(__IO hw_mcg_c6_t *) HW_MCG_C6_ADDR)
-#define HW_MCG_C6_RD() (HW_MCG_C6.U)
-#define HW_MCG_C6_WR(v) (HW_MCG_C6.U = (v))
-#define HW_MCG_C6_SET(v) (HW_MCG_C6_WR(HW_MCG_C6_RD() | (v)))
-#define HW_MCG_C6_CLR(v) (HW_MCG_C6_WR(HW_MCG_C6_RD() & ~(v)))
-#define HW_MCG_C6_TOG(v) (HW_MCG_C6_WR(HW_MCG_C6_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual MCG_C6 bitfields
- */
-
-/*!
- * @name Register MCG_C6, field VDIV0[4:0] (RW)
- *
- * Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits
- * establish the multiplication factor (M) applied to the reference clock frequency.
- * After the PLL is enabled (by setting either PLLCLKEN 0 or PLLS), the VDIV 0
- * value must not be changed when LOCK 0 is zero. PLL VCO Divide Factor VDIV 0
- * Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply
- * Factor 00000 24 01000 32 10000 40 11000 48 00001 25 01001 33 10001 41 11001 49
- * 00010 26 01010 34 10010 42 11010 50 00011 27 01011 35 10011 43 11011 51 00100 28
- * 01100 36 10100 44 11100 52 00101 29 01101 37 10101 45 11101 53 00110 30 01110
- * 38 10110 46 11110 54 00111 31 01111 39 10111 47 11111 55
- */
-//@{
-#define BP_MCG_C6_VDIV0 (0U) //!< Bit position for MCG_C6_VDIV0.
-#define BM_MCG_C6_VDIV0 (0x1FU) //!< Bit mask for MCG_C6_VDIV0.
-#define BS_MCG_C6_VDIV0 (5U) //!< Bit field size in bits for MCG_C6_VDIV0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_C6_VDIV0 field.
-#define BR_MCG_C6_VDIV0 (HW_MCG_C6.B.VDIV0)
-#endif
-
-//! @brief Format value for bitfield MCG_C6_VDIV0.
-#define BF_MCG_C6_VDIV0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C6_VDIV0), uint8_t) & BM_MCG_C6_VDIV0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the VDIV0 field to a new value.
-#define BW_MCG_C6_VDIV0(v) (HW_MCG_C6_WR((HW_MCG_C6_RD() & ~BM_MCG_C6_VDIV0) | BF_MCG_C6_VDIV0(v)))
-#endif
-//@}
-
-/*!
- * @name Register MCG_C6, field CME0[5] (RW)
- *
- * Enables the loss of clock monitoring circuit for the OSC0 external reference
- * mux select. The LOCRE0 bit will determine if a interrupt or a reset request is
- * generated following a loss of OSC0 indication. The CME0 bit must only be set
- * to a logic 1 when the MCG is in an operational mode that uses the external
- * clock (FEE, FBE, PEE, PBE, or BLPE) . Whenever the CME0 bit is set to a logic 1,
- * the value of the RANGE0 bits in the C2 register should not be changed. CME0
- * bit should be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
- * reset request may occur while in Stop mode. CME0 should also be set to a
- * logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode.
- *
- * Values:
- * - 0 - External clock monitor is disabled for OSC0.
- * - 1 - External clock monitor is enabled for OSC0.
- */
-//@{
-#define BP_MCG_C6_CME0 (5U) //!< Bit position for MCG_C6_CME0.
-#define BM_MCG_C6_CME0 (0x20U) //!< Bit mask for MCG_C6_CME0.
-#define BS_MCG_C6_CME0 (1U) //!< Bit field size in bits for MCG_C6_CME0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_C6_CME0 field.
-#define BR_MCG_C6_CME0 (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_CME0))
-#endif
-
-//! @brief Format value for bitfield MCG_C6_CME0.
-#define BF_MCG_C6_CME0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C6_CME0), uint8_t) & BM_MCG_C6_CME0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CME0 field to a new value.
-#define BW_MCG_C6_CME0(v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_CME0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCG_C6, field PLLS[6] (RW)
- *
- * Controls whether the PLL or FLL output is selected as the MCG source when
- * CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN 0 is not set, the PLL is
- * disabled in all modes. If the PLLS is set, the FLL is disabled in all modes.
- *
- * Values:
- * - 0 - FLL is selected.
- * - 1 - PLL is selected (PRDIV 0 need to be programmed to the correct divider
- * to generate a PLL reference clock in the range of 2-4 MHz prior to setting
- * the PLLS bit).
- */
-//@{
-#define BP_MCG_C6_PLLS (6U) //!< Bit position for MCG_C6_PLLS.
-#define BM_MCG_C6_PLLS (0x40U) //!< Bit mask for MCG_C6_PLLS.
-#define BS_MCG_C6_PLLS (1U) //!< Bit field size in bits for MCG_C6_PLLS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_C6_PLLS field.
-#define BR_MCG_C6_PLLS (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_PLLS))
-#endif
-
-//! @brief Format value for bitfield MCG_C6_PLLS.
-#define BF_MCG_C6_PLLS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C6_PLLS), uint8_t) & BM_MCG_C6_PLLS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PLLS field to a new value.
-#define BW_MCG_C6_PLLS(v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_PLLS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCG_C6, field LOLIE0[7] (RW)
- *
- * Determines if an interrupt request is made following a loss of lock
- * indication. This bit only has an effect when LOLS 0 is set.
- *
- * Values:
- * - 0 - No interrupt request is generated on loss of lock.
- * - 1 - Generate an interrupt request on loss of lock.
- */
-//@{
-#define BP_MCG_C6_LOLIE0 (7U) //!< Bit position for MCG_C6_LOLIE0.
-#define BM_MCG_C6_LOLIE0 (0x80U) //!< Bit mask for MCG_C6_LOLIE0.
-#define BS_MCG_C6_LOLIE0 (1U) //!< Bit field size in bits for MCG_C6_LOLIE0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_C6_LOLIE0 field.
-#define BR_MCG_C6_LOLIE0 (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_LOLIE0))
-#endif
-
-//! @brief Format value for bitfield MCG_C6_LOLIE0.
-#define BF_MCG_C6_LOLIE0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C6_LOLIE0), uint8_t) & BM_MCG_C6_LOLIE0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LOLIE0 field to a new value.
-#define BW_MCG_C6_LOLIE0(v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_LOLIE0) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_MCG_S - MCG Status Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_MCG_S - MCG Status Register (RW)
- *
- * Reset value: 0x10U
- */
-typedef union _hw_mcg_s
-{
- uint8_t U;
- struct _hw_mcg_s_bitfields
- {
- uint8_t IRCST : 1; //!< [0] Internal Reference Clock Status
- uint8_t OSCINIT0 : 1; //!< [1] OSC Initialization
- uint8_t CLKST : 2; //!< [3:2] Clock Mode Status
- uint8_t IREFST : 1; //!< [4] Internal Reference Status
- uint8_t PLLST : 1; //!< [5] PLL Select Status
- uint8_t LOCK0 : 1; //!< [6] Lock Status
- uint8_t LOLS0 : 1; //!< [7] Loss of Lock Status
- } B;
-} hw_mcg_s_t;
-#endif
-
-/*!
- * @name Constants and macros for entire MCG_S register
- */
-//@{
-#define HW_MCG_S_ADDR (REGS_MCG_BASE + 0x6U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_MCG_S (*(__IO hw_mcg_s_t *) HW_MCG_S_ADDR)
-#define HW_MCG_S_RD() (HW_MCG_S.U)
-#define HW_MCG_S_WR(v) (HW_MCG_S.U = (v))
-#define HW_MCG_S_SET(v) (HW_MCG_S_WR(HW_MCG_S_RD() | (v)))
-#define HW_MCG_S_CLR(v) (HW_MCG_S_WR(HW_MCG_S_RD() & ~(v)))
-#define HW_MCG_S_TOG(v) (HW_MCG_S_WR(HW_MCG_S_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual MCG_S bitfields
- */
-
-/*!
- * @name Register MCG_S, field IRCST[0] (RO)
- *
- * The IRCST bit indicates the current source for the internal reference clock
- * select clock (IRCSCLK). The IRCST bit does not update immediately after a write
- * to the IRCS bit due to internal synchronization between clock domains. The
- * IRCST bit will only be updated if the internal reference clock is enabled,
- * either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN]
- * bit .
- *
- * Values:
- * - 0 - Source of internal reference clock is the slow clock (32 kHz IRC).
- * - 1 - Source of internal reference clock is the fast clock (4 MHz IRC).
- */
-//@{
-#define BP_MCG_S_IRCST (0U) //!< Bit position for MCG_S_IRCST.
-#define BM_MCG_S_IRCST (0x01U) //!< Bit mask for MCG_S_IRCST.
-#define BS_MCG_S_IRCST (1U) //!< Bit field size in bits for MCG_S_IRCST.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_S_IRCST field.
-#define BR_MCG_S_IRCST (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_IRCST))
-#endif
-//@}
-
-/*!
- * @name Register MCG_S, field OSCINIT0[1] (RO)
- *
- * This bit, which resets to 0, is set to 1 after the initialization cycles of
- * the crystal oscillator clock have completed. After being set, the bit is
- * cleared to 0 if the OSC is subsequently disabled. See the OSC module's detailed
- * description for more information.
- */
-//@{
-#define BP_MCG_S_OSCINIT0 (1U) //!< Bit position for MCG_S_OSCINIT0.
-#define BM_MCG_S_OSCINIT0 (0x02U) //!< Bit mask for MCG_S_OSCINIT0.
-#define BS_MCG_S_OSCINIT0 (1U) //!< Bit field size in bits for MCG_S_OSCINIT0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_S_OSCINIT0 field.
-#define BR_MCG_S_OSCINIT0 (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_OSCINIT0))
-#endif
-//@}
-
-/*!
- * @name Register MCG_S, field CLKST[3:2] (RO)
- *
- * These bits indicate the current clock mode. The CLKST bits do not update
- * immediately after a write to the CLKS bits due to internal synchronization between
- * clock domains.
- *
- * Values:
- * - 00 - Encoding 0 - Output of the FLL is selected (reset default).
- * - 01 - Encoding 1 - Internal reference clock is selected.
- * - 10 - Encoding 2 - External reference clock is selected.
- * - 11 - Encoding 3 - Output of the PLL is selected.
- */
-//@{
-#define BP_MCG_S_CLKST (2U) //!< Bit position for MCG_S_CLKST.
-#define BM_MCG_S_CLKST (0x0CU) //!< Bit mask for MCG_S_CLKST.
-#define BS_MCG_S_CLKST (2U) //!< Bit field size in bits for MCG_S_CLKST.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_S_CLKST field.
-#define BR_MCG_S_CLKST (HW_MCG_S.B.CLKST)
-#endif
-//@}
-
-/*!
- * @name Register MCG_S, field IREFST[4] (RO)
- *
- * This bit indicates the current source for the FLL reference clock. The IREFST
- * bit does not update immediately after a write to the IREFS bit due to
- * internal synchronization between clock domains.
- *
- * Values:
- * - 0 - Source of FLL reference clock is the external reference clock.
- * - 1 - Source of FLL reference clock is the internal reference clock.
- */
-//@{
-#define BP_MCG_S_IREFST (4U) //!< Bit position for MCG_S_IREFST.
-#define BM_MCG_S_IREFST (0x10U) //!< Bit mask for MCG_S_IREFST.
-#define BS_MCG_S_IREFST (1U) //!< Bit field size in bits for MCG_S_IREFST.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_S_IREFST field.
-#define BR_MCG_S_IREFST (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_IREFST))
-#endif
-//@}
-
-/*!
- * @name Register MCG_S, field PLLST[5] (RO)
- *
- * This bit indicates the clock source selected by PLLS . The PLLST bit does not
- * update immediately after a write to the PLLS bit due to internal
- * synchronization between clock domains.
- *
- * Values:
- * - 0 - Source of PLLS clock is FLL clock.
- * - 1 - Source of PLLS clock is PLL output clock.
- */
-//@{
-#define BP_MCG_S_PLLST (5U) //!< Bit position for MCG_S_PLLST.
-#define BM_MCG_S_PLLST (0x20U) //!< Bit mask for MCG_S_PLLST.
-#define BS_MCG_S_PLLST (1U) //!< Bit field size in bits for MCG_S_PLLST.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_S_PLLST field.
-#define BR_MCG_S_PLLST (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_PLLST))
-#endif
-//@}
-
-/*!
- * @name Register MCG_S, field LOCK0[6] (RO)
- *
- * This bit indicates whether the PLL has acquired lock. Lock detection is only
- * enabled when the PLL is enabled (either through clock mode selection or
- * PLLCLKEN0=1 setting). While the PLL clock is locking to the desired frequency, the
- * MCG PLL clock (MCGPLLCLK) will be gated off until the LOCK bit gets asserted.
- * If the lock status bit is set, changing the value of the PRDIV0 [4:0] bits in
- * the C5 register or the VDIV0[4:0] bits in the C6 register causes the lock
- * status bit to clear and stay cleared until the PLL has reacquired lock. Loss of PLL
- * reference clock will also cause the LOCK0 bit to clear until the PLL has
- * reacquired lock. Entry into LLS, VLPS, or regular Stop with PLLSTEN=0 also causes
- * the lock status bit to clear and stay cleared until the Stop mode is exited
- * and the PLL has reacquired lock. Any time the PLL is enabled and the LOCK0 bit
- * is cleared, the MCGPLLCLK will be gated off until the LOCK0 bit is asserted
- * again.
- *
- * Values:
- * - 0 - PLL is currently unlocked.
- * - 1 - PLL is currently locked.
- */
-//@{
-#define BP_MCG_S_LOCK0 (6U) //!< Bit position for MCG_S_LOCK0.
-#define BM_MCG_S_LOCK0 (0x40U) //!< Bit mask for MCG_S_LOCK0.
-#define BS_MCG_S_LOCK0 (1U) //!< Bit field size in bits for MCG_S_LOCK0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_S_LOCK0 field.
-#define BR_MCG_S_LOCK0 (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_LOCK0))
-#endif
-//@}
-
-/*!
- * @name Register MCG_S, field LOLS0[7] (W1C)
- *
- * This bit is a sticky bit indicating the lock status for the PLL. LOLS is set
- * if after acquiring lock, the PLL output frequency has fallen outside the lock
- * exit frequency tolerance, D unl . LOLIE determines whether an interrupt
- * request is made when LOLS is set. LOLRE determines whether a reset request is made
- * when LOLS is set. This bit is cleared by reset or by writing a logic 1 to it
- * when set. Writing a logic 0 to this bit has no effect.
- *
- * Values:
- * - 0 - PLL has not lost lock since LOLS 0 was last cleared.
- * - 1 - PLL has lost lock since LOLS 0 was last cleared.
- */
-//@{
-#define BP_MCG_S_LOLS0 (7U) //!< Bit position for MCG_S_LOLS0.
-#define BM_MCG_S_LOLS0 (0x80U) //!< Bit mask for MCG_S_LOLS0.
-#define BS_MCG_S_LOLS0 (1U) //!< Bit field size in bits for MCG_S_LOLS0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_S_LOLS0 field.
-#define BR_MCG_S_LOLS0 (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_LOLS0))
-#endif
-
-//! @brief Format value for bitfield MCG_S_LOLS0.
-#define BF_MCG_S_LOLS0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_S_LOLS0), uint8_t) & BM_MCG_S_LOLS0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LOLS0 field to a new value.
-#define BW_MCG_S_LOLS0(v) (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_LOLS0) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_MCG_SC - MCG Status and Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_MCG_SC - MCG Status and Control Register (RW)
- *
- * Reset value: 0x02U
- */
-typedef union _hw_mcg_sc
-{
- uint8_t U;
- struct _hw_mcg_sc_bitfields
- {
- uint8_t LOCS0 : 1; //!< [0] OSC0 Loss of Clock Status
- uint8_t FCRDIV : 3; //!< [3:1] Fast Clock Internal Reference Divider
- uint8_t FLTPRSRV : 1; //!< [4] FLL Filter Preserve Enable
- uint8_t ATMF : 1; //!< [5] Automatic Trim Machine Fail Flag
- uint8_t ATMS : 1; //!< [6] Automatic Trim Machine Select
- uint8_t ATME : 1; //!< [7] Automatic Trim Machine Enable
- } B;
-} hw_mcg_sc_t;
-#endif
-
-/*!
- * @name Constants and macros for entire MCG_SC register
- */
-//@{
-#define HW_MCG_SC_ADDR (REGS_MCG_BASE + 0x8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_MCG_SC (*(__IO hw_mcg_sc_t *) HW_MCG_SC_ADDR)
-#define HW_MCG_SC_RD() (HW_MCG_SC.U)
-#define HW_MCG_SC_WR(v) (HW_MCG_SC.U = (v))
-#define HW_MCG_SC_SET(v) (HW_MCG_SC_WR(HW_MCG_SC_RD() | (v)))
-#define HW_MCG_SC_CLR(v) (HW_MCG_SC_WR(HW_MCG_SC_RD() & ~(v)))
-#define HW_MCG_SC_TOG(v) (HW_MCG_SC_WR(HW_MCG_SC_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual MCG_SC bitfields
- */
-
-/*!
- * @name Register MCG_SC, field LOCS0[0] (W1C)
- *
- * The LOCS0 indicates when a loss of OSC0 reference clock has occurred. The
- * LOCS0 bit only has an effect when CME0 is set. This bit is cleared by writing a
- * logic 1 to it when set.
- *
- * Values:
- * - 0 - Loss of OSC0 has not occurred.
- * - 1 - Loss of OSC0 has occurred.
- */
-//@{
-#define BP_MCG_SC_LOCS0 (0U) //!< Bit position for MCG_SC_LOCS0.
-#define BM_MCG_SC_LOCS0 (0x01U) //!< Bit mask for MCG_SC_LOCS0.
-#define BS_MCG_SC_LOCS0 (1U) //!< Bit field size in bits for MCG_SC_LOCS0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_SC_LOCS0 field.
-#define BR_MCG_SC_LOCS0 (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_LOCS0))
-#endif
-
-//! @brief Format value for bitfield MCG_SC_LOCS0.
-#define BF_MCG_SC_LOCS0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_LOCS0), uint8_t) & BM_MCG_SC_LOCS0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LOCS0 field to a new value.
-#define BW_MCG_SC_LOCS0(v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_LOCS0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCG_SC, field FCRDIV[3:1] (RW)
- *
- * Selects the amount to divide down the fast internal reference clock. The
- * resulting frequency will be in the range 31.25 kHz to 4 MHz (Note: Changing the
- * divider when the Fast IRC is enabled is not supported).
- *
- * Values:
- * - 000 - Divide Factor is 1
- * - 001 - Divide Factor is 2.
- * - 010 - Divide Factor is 4.
- * - 011 - Divide Factor is 8.
- * - 100 - Divide Factor is 16
- * - 101 - Divide Factor is 32
- * - 110 - Divide Factor is 64
- * - 111 - Divide Factor is 128.
- */
-//@{
-#define BP_MCG_SC_FCRDIV (1U) //!< Bit position for MCG_SC_FCRDIV.
-#define BM_MCG_SC_FCRDIV (0x0EU) //!< Bit mask for MCG_SC_FCRDIV.
-#define BS_MCG_SC_FCRDIV (3U) //!< Bit field size in bits for MCG_SC_FCRDIV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_SC_FCRDIV field.
-#define BR_MCG_SC_FCRDIV (HW_MCG_SC.B.FCRDIV)
-#endif
-
-//! @brief Format value for bitfield MCG_SC_FCRDIV.
-#define BF_MCG_SC_FCRDIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_FCRDIV), uint8_t) & BM_MCG_SC_FCRDIV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FCRDIV field to a new value.
-#define BW_MCG_SC_FCRDIV(v) (HW_MCG_SC_WR((HW_MCG_SC_RD() & ~BM_MCG_SC_FCRDIV) | BF_MCG_SC_FCRDIV(v)))
-#endif
-//@}
-
-/*!
- * @name Register MCG_SC, field FLTPRSRV[4] (RW)
- *
- * This bit will prevent the FLL filter values from resetting allowing the FLL
- * output frequency to remain the same during clock mode changes where the FLL/DCO
- * output is still valid. (Note: This requires that the FLL reference frequency
- * to remain the same as what it was prior to the new clock mode switch.
- * Otherwise FLL filter and frequency values will change.)
- *
- * Values:
- * - 0 - FLL filter and FLL frequency will reset on changes to currect clock
- * mode.
- * - 1 - Fll filter and FLL frequency retain their previous values during new
- * clock mode change.
- */
-//@{
-#define BP_MCG_SC_FLTPRSRV (4U) //!< Bit position for MCG_SC_FLTPRSRV.
-#define BM_MCG_SC_FLTPRSRV (0x10U) //!< Bit mask for MCG_SC_FLTPRSRV.
-#define BS_MCG_SC_FLTPRSRV (1U) //!< Bit field size in bits for MCG_SC_FLTPRSRV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_SC_FLTPRSRV field.
-#define BR_MCG_SC_FLTPRSRV (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_FLTPRSRV))
-#endif
-
-//! @brief Format value for bitfield MCG_SC_FLTPRSRV.
-#define BF_MCG_SC_FLTPRSRV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_FLTPRSRV), uint8_t) & BM_MCG_SC_FLTPRSRV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FLTPRSRV field to a new value.
-#define BW_MCG_SC_FLTPRSRV(v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_FLTPRSRV) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCG_SC, field ATMF[5] (RW)
- *
- * Fail flag for the Automatic Trim Machine (ATM). This bit asserts when the
- * Automatic Trim Machine is enabled, ATME=1, and a write to the C1, C3, C4, and SC
- * registers is detected or the MCG enters into any Stop mode. A write to ATMF
- * clears the flag.
- *
- * Values:
- * - 0 - Automatic Trim Machine completed normally.
- * - 1 - Automatic Trim Machine failed.
- */
-//@{
-#define BP_MCG_SC_ATMF (5U) //!< Bit position for MCG_SC_ATMF.
-#define BM_MCG_SC_ATMF (0x20U) //!< Bit mask for MCG_SC_ATMF.
-#define BS_MCG_SC_ATMF (1U) //!< Bit field size in bits for MCG_SC_ATMF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_SC_ATMF field.
-#define BR_MCG_SC_ATMF (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATMF))
-#endif
-
-//! @brief Format value for bitfield MCG_SC_ATMF.
-#define BF_MCG_SC_ATMF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_ATMF), uint8_t) & BM_MCG_SC_ATMF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ATMF field to a new value.
-#define BW_MCG_SC_ATMF(v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATMF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCG_SC, field ATMS[6] (RW)
- *
- * Selects the IRCS clock for Auto Trim Test.
- *
- * Values:
- * - 0 - 32 kHz Internal Reference Clock selected.
- * - 1 - 4 MHz Internal Reference Clock selected.
- */
-//@{
-#define BP_MCG_SC_ATMS (6U) //!< Bit position for MCG_SC_ATMS.
-#define BM_MCG_SC_ATMS (0x40U) //!< Bit mask for MCG_SC_ATMS.
-#define BS_MCG_SC_ATMS (1U) //!< Bit field size in bits for MCG_SC_ATMS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_SC_ATMS field.
-#define BR_MCG_SC_ATMS (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATMS))
-#endif
-
-//! @brief Format value for bitfield MCG_SC_ATMS.
-#define BF_MCG_SC_ATMS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_ATMS), uint8_t) & BM_MCG_SC_ATMS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ATMS field to a new value.
-#define BW_MCG_SC_ATMS(v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATMS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCG_SC, field ATME[7] (RW)
- *
- * Enables the Auto Trim Machine to start automatically trimming the selected
- * Internal Reference Clock. ATME deasserts after the Auto Trim Machine has
- * completed trimming all trim bits of the IRCS clock selected by the ATMS bit. Writing
- * to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim
- * operation and clears this bit.
- *
- * Values:
- * - 0 - Auto Trim Machine disabled.
- * - 1 - Auto Trim Machine enabled.
- */
-//@{
-#define BP_MCG_SC_ATME (7U) //!< Bit position for MCG_SC_ATME.
-#define BM_MCG_SC_ATME (0x80U) //!< Bit mask for MCG_SC_ATME.
-#define BS_MCG_SC_ATME (1U) //!< Bit field size in bits for MCG_SC_ATME.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_SC_ATME field.
-#define BR_MCG_SC_ATME (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATME))
-#endif
-
-//! @brief Format value for bitfield MCG_SC_ATME.
-#define BF_MCG_SC_ATME(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_ATME), uint8_t) & BM_MCG_SC_ATME)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ATME field to a new value.
-#define BW_MCG_SC_ATME(v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATME) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register (RW)
- *
- * Reset value: 0x00U
- */
-typedef union _hw_mcg_atcvh
-{
- uint8_t U;
- struct _hw_mcg_atcvh_bitfields
- {
- uint8_t ATCVH : 8; //!< [7:0] ATM Compare Value High
- } B;
-} hw_mcg_atcvh_t;
-#endif
-
-/*!
- * @name Constants and macros for entire MCG_ATCVH register
- */
-//@{
-#define HW_MCG_ATCVH_ADDR (REGS_MCG_BASE + 0xAU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_MCG_ATCVH (*(__IO hw_mcg_atcvh_t *) HW_MCG_ATCVH_ADDR)
-#define HW_MCG_ATCVH_RD() (HW_MCG_ATCVH.U)
-#define HW_MCG_ATCVH_WR(v) (HW_MCG_ATCVH.U = (v))
-#define HW_MCG_ATCVH_SET(v) (HW_MCG_ATCVH_WR(HW_MCG_ATCVH_RD() | (v)))
-#define HW_MCG_ATCVH_CLR(v) (HW_MCG_ATCVH_WR(HW_MCG_ATCVH_RD() & ~(v)))
-#define HW_MCG_ATCVH_TOG(v) (HW_MCG_ATCVH_WR(HW_MCG_ATCVH_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual MCG_ATCVH bitfields
- */
-
-/*!
- * @name Register MCG_ATCVH, field ATCVH[7:0] (RW)
- *
- * Values are used by Auto Trim Machine to compare and adjust Internal Reference
- * trim values during ATM SAR conversion.
- */
-//@{
-#define BP_MCG_ATCVH_ATCVH (0U) //!< Bit position for MCG_ATCVH_ATCVH.
-#define BM_MCG_ATCVH_ATCVH (0xFFU) //!< Bit mask for MCG_ATCVH_ATCVH.
-#define BS_MCG_ATCVH_ATCVH (8U) //!< Bit field size in bits for MCG_ATCVH_ATCVH.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_ATCVH_ATCVH field.
-#define BR_MCG_ATCVH_ATCVH (HW_MCG_ATCVH.U)
-#endif
-
-//! @brief Format value for bitfield MCG_ATCVH_ATCVH.
-#define BF_MCG_ATCVH_ATCVH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_ATCVH_ATCVH), uint8_t) & BM_MCG_ATCVH_ATCVH)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ATCVH field to a new value.
-#define BW_MCG_ATCVH_ATCVH(v) (HW_MCG_ATCVH_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register (RW)
- *
- * Reset value: 0x00U
- */
-typedef union _hw_mcg_atcvl
-{
- uint8_t U;
- struct _hw_mcg_atcvl_bitfields
- {
- uint8_t ATCVL : 8; //!< [7:0] ATM Compare Value Low
- } B;
-} hw_mcg_atcvl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire MCG_ATCVL register
- */
-//@{
-#define HW_MCG_ATCVL_ADDR (REGS_MCG_BASE + 0xBU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_MCG_ATCVL (*(__IO hw_mcg_atcvl_t *) HW_MCG_ATCVL_ADDR)
-#define HW_MCG_ATCVL_RD() (HW_MCG_ATCVL.U)
-#define HW_MCG_ATCVL_WR(v) (HW_MCG_ATCVL.U = (v))
-#define HW_MCG_ATCVL_SET(v) (HW_MCG_ATCVL_WR(HW_MCG_ATCVL_RD() | (v)))
-#define HW_MCG_ATCVL_CLR(v) (HW_MCG_ATCVL_WR(HW_MCG_ATCVL_RD() & ~(v)))
-#define HW_MCG_ATCVL_TOG(v) (HW_MCG_ATCVL_WR(HW_MCG_ATCVL_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual MCG_ATCVL bitfields
- */
-
-/*!
- * @name Register MCG_ATCVL, field ATCVL[7:0] (RW)
- *
- * Values are used by Auto Trim Machine to compare and adjust Internal Reference
- * trim values during ATM SAR conversion.
- */
-//@{
-#define BP_MCG_ATCVL_ATCVL (0U) //!< Bit position for MCG_ATCVL_ATCVL.
-#define BM_MCG_ATCVL_ATCVL (0xFFU) //!< Bit mask for MCG_ATCVL_ATCVL.
-#define BS_MCG_ATCVL_ATCVL (8U) //!< Bit field size in bits for MCG_ATCVL_ATCVL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_ATCVL_ATCVL field.
-#define BR_MCG_ATCVL_ATCVL (HW_MCG_ATCVL.U)
-#endif
-
-//! @brief Format value for bitfield MCG_ATCVL_ATCVL.
-#define BF_MCG_ATCVL_ATCVL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_ATCVL_ATCVL), uint8_t) & BM_MCG_ATCVL_ATCVL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ATCVL field to a new value.
-#define BW_MCG_ATCVL_ATCVL(v) (HW_MCG_ATCVL_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_MCG_C7 - MCG Control 7 Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_MCG_C7 - MCG Control 7 Register (RW)
- *
- * Reset value: 0x00U
- */
-typedef union _hw_mcg_c7
-{
- uint8_t U;
- struct _hw_mcg_c7_bitfields
- {
- uint8_t OSCSEL : 2; //!< [1:0] MCG OSC Clock Select
- uint8_t RESERVED0 : 6; //!< [7:2]
- } B;
-} hw_mcg_c7_t;
-#endif
-
-/*!
- * @name Constants and macros for entire MCG_C7 register
- */
-//@{
-#define HW_MCG_C7_ADDR (REGS_MCG_BASE + 0xCU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_MCG_C7 (*(__IO hw_mcg_c7_t *) HW_MCG_C7_ADDR)
-#define HW_MCG_C7_RD() (HW_MCG_C7.U)
-#define HW_MCG_C7_WR(v) (HW_MCG_C7.U = (v))
-#define HW_MCG_C7_SET(v) (HW_MCG_C7_WR(HW_MCG_C7_RD() | (v)))
-#define HW_MCG_C7_CLR(v) (HW_MCG_C7_WR(HW_MCG_C7_RD() & ~(v)))
-#define HW_MCG_C7_TOG(v) (HW_MCG_C7_WR(HW_MCG_C7_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual MCG_C7 bitfields
- */
-
-/*!
- * @name Register MCG_C7, field OSCSEL[1:0] (RW)
- *
- * Selects the MCG FLL external reference clock
- *
- * Values:
- * - 00 - Selects Oscillator (OSCCLK0).
- * - 01 - Selects 32 kHz RTC Oscillator.
- * - 10 - Selects Oscillator (OSCCLK1).
- * - 11 - RESERVED
- */
-//@{
-#define BP_MCG_C7_OSCSEL (0U) //!< Bit position for MCG_C7_OSCSEL.
-#define BM_MCG_C7_OSCSEL (0x03U) //!< Bit mask for MCG_C7_OSCSEL.
-#define BS_MCG_C7_OSCSEL (2U) //!< Bit field size in bits for MCG_C7_OSCSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_C7_OSCSEL field.
-#define BR_MCG_C7_OSCSEL (HW_MCG_C7.B.OSCSEL)
-#endif
-
-//! @brief Format value for bitfield MCG_C7_OSCSEL.
-#define BF_MCG_C7_OSCSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C7_OSCSEL), uint8_t) & BM_MCG_C7_OSCSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the OSCSEL field to a new value.
-#define BW_MCG_C7_OSCSEL(v) (HW_MCG_C7_WR((HW_MCG_C7_RD() & ~BM_MCG_C7_OSCSEL) | BF_MCG_C7_OSCSEL(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_MCG_C8 - MCG Control 8 Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_MCG_C8 - MCG Control 8 Register (RW)
- *
- * Reset value: 0x80U
- */
-typedef union _hw_mcg_c8
-{
- uint8_t U;
- struct _hw_mcg_c8_bitfields
- {
- uint8_t LOCS1 : 1; //!< [0] RTC Loss of Clock Status
- uint8_t RESERVED0 : 4; //!< [4:1]
- uint8_t CME1 : 1; //!< [5] Clock Monitor Enable1
- uint8_t LOLRE : 1; //!< [6] PLL Loss of Lock Reset Enable
- uint8_t LOCRE1 : 1; //!< [7] Loss of Clock Reset Enable
- } B;
-} hw_mcg_c8_t;
-#endif
-
-/*!
- * @name Constants and macros for entire MCG_C8 register
- */
-//@{
-#define HW_MCG_C8_ADDR (REGS_MCG_BASE + 0xDU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_MCG_C8 (*(__IO hw_mcg_c8_t *) HW_MCG_C8_ADDR)
-#define HW_MCG_C8_RD() (HW_MCG_C8.U)
-#define HW_MCG_C8_WR(v) (HW_MCG_C8.U = (v))
-#define HW_MCG_C8_SET(v) (HW_MCG_C8_WR(HW_MCG_C8_RD() | (v)))
-#define HW_MCG_C8_CLR(v) (HW_MCG_C8_WR(HW_MCG_C8_RD() & ~(v)))
-#define HW_MCG_C8_TOG(v) (HW_MCG_C8_WR(HW_MCG_C8_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual MCG_C8 bitfields
- */
-
-/*!
- * @name Register MCG_C8, field LOCS1[0] (W1C)
- *
- * This bit indicates when a loss of clock has occurred. This bit is cleared by
- * writing a logic 1 to it when set.
- *
- * Values:
- * - 0 - Loss of RTC has not occur.
- * - 1 - Loss of RTC has occur
- */
-//@{
-#define BP_MCG_C8_LOCS1 (0U) //!< Bit position for MCG_C8_LOCS1.
-#define BM_MCG_C8_LOCS1 (0x01U) //!< Bit mask for MCG_C8_LOCS1.
-#define BS_MCG_C8_LOCS1 (1U) //!< Bit field size in bits for MCG_C8_LOCS1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_C8_LOCS1 field.
-#define BR_MCG_C8_LOCS1 (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOCS1))
-#endif
-
-//! @brief Format value for bitfield MCG_C8_LOCS1.
-#define BF_MCG_C8_LOCS1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C8_LOCS1), uint8_t) & BM_MCG_C8_LOCS1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LOCS1 field to a new value.
-#define BW_MCG_C8_LOCS1(v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOCS1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCG_C8, field CME1[5] (RW)
- *
- * Enables the loss of clock monitoring circuit for the output of the RTC
- * external reference clock. The LOCRE1 bit will determine whether an interrupt or a
- * reset request is generated following a loss of RTC clock indication. The CME1
- * bit should be set to a logic 1 when the MCG is in an operational mode that uses
- * the RTC as its external reference clock or if the RTC is operational. CME1 bit
- * must be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
- * reset request may occur when in Stop mode. CME1 should also be set to a logic 0
- * before entering VLPR or VLPW power modes.
- *
- * Values:
- * - 0 - External clock monitor is disabled for RTC clock.
- * - 1 - External clock monitor is enabled for RTC clock.
- */
-//@{
-#define BP_MCG_C8_CME1 (5U) //!< Bit position for MCG_C8_CME1.
-#define BM_MCG_C8_CME1 (0x20U) //!< Bit mask for MCG_C8_CME1.
-#define BS_MCG_C8_CME1 (1U) //!< Bit field size in bits for MCG_C8_CME1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_C8_CME1 field.
-#define BR_MCG_C8_CME1 (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_CME1))
-#endif
-
-//! @brief Format value for bitfield MCG_C8_CME1.
-#define BF_MCG_C8_CME1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C8_CME1), uint8_t) & BM_MCG_C8_CME1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CME1 field to a new value.
-#define BW_MCG_C8_CME1(v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_CME1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCG_C8, field LOLRE[6] (RW)
- *
- * Determines if an interrupt or a reset request is made following a PLL loss of
- * lock.
- *
- * Values:
- * - 0 - Interrupt request is generated on a PLL loss of lock indication. The
- * PLL loss of lock interrupt enable bit must also be set to generate the
- * interrupt request.
- * - 1 - Generate a reset request on a PLL loss of lock indication.
- */
-//@{
-#define BP_MCG_C8_LOLRE (6U) //!< Bit position for MCG_C8_LOLRE.
-#define BM_MCG_C8_LOLRE (0x40U) //!< Bit mask for MCG_C8_LOLRE.
-#define BS_MCG_C8_LOLRE (1U) //!< Bit field size in bits for MCG_C8_LOLRE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_C8_LOLRE field.
-#define BR_MCG_C8_LOLRE (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOLRE))
-#endif
-
-//! @brief Format value for bitfield MCG_C8_LOLRE.
-#define BF_MCG_C8_LOLRE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C8_LOLRE), uint8_t) & BM_MCG_C8_LOLRE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LOLRE field to a new value.
-#define BW_MCG_C8_LOLRE(v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOLRE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCG_C8, field LOCRE1[7] (RW)
- *
- * Determines if a interrupt or a reset request is made following a loss of RTC
- * external reference clock. The LOCRE1 only has an affect when CME1 is set.
- *
- * Values:
- * - 0 - Interrupt request is generated on a loss of RTC external reference
- * clock.
- * - 1 - Generate a reset request on a loss of RTC external reference clock
- */
-//@{
-#define BP_MCG_C8_LOCRE1 (7U) //!< Bit position for MCG_C8_LOCRE1.
-#define BM_MCG_C8_LOCRE1 (0x80U) //!< Bit mask for MCG_C8_LOCRE1.
-#define BS_MCG_C8_LOCRE1 (1U) //!< Bit field size in bits for MCG_C8_LOCRE1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCG_C8_LOCRE1 field.
-#define BR_MCG_C8_LOCRE1 (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOCRE1))
-#endif
-
-//! @brief Format value for bitfield MCG_C8_LOCRE1.
-#define BF_MCG_C8_LOCRE1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C8_LOCRE1), uint8_t) & BM_MCG_C8_LOCRE1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LOCRE1 field to a new value.
-#define BW_MCG_C8_LOCRE1(v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOCRE1) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_mcg_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All MCG module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_mcg
-{
- __IO hw_mcg_c1_t C1; //!< [0x0] MCG Control 1 Register
- __IO hw_mcg_c2_t C2; //!< [0x1] MCG Control 2 Register
- __IO hw_mcg_c3_t C3; //!< [0x2] MCG Control 3 Register
- __IO hw_mcg_c4_t C4; //!< [0x3] MCG Control 4 Register
- __IO hw_mcg_c5_t C5; //!< [0x4] MCG Control 5 Register
- __IO hw_mcg_c6_t C6; //!< [0x5] MCG Control 6 Register
- __IO hw_mcg_s_t S; //!< [0x6] MCG Status Register
- uint8_t _reserved0[1];
- __IO hw_mcg_sc_t SC; //!< [0x8] MCG Status and Control Register
- uint8_t _reserved1[1];
- __IO hw_mcg_atcvh_t ATCVH; //!< [0xA] MCG Auto Trim Compare Value High Register
- __IO hw_mcg_atcvl_t ATCVL; //!< [0xB] MCG Auto Trim Compare Value Low Register
- __IO hw_mcg_c7_t C7; //!< [0xC] MCG Control 7 Register
- __IO hw_mcg_c8_t C8; //!< [0xD] MCG Control 8 Register
-} hw_mcg_t;
-#pragma pack()
-
-//! @brief Macro to access all MCG registers.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_MCG</code>.
-#define HW_MCG (*(hw_mcg_t *) REGS_MCG_BASE)
-#endif
-
-#endif // __HW_MCG_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_mcm.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1164 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_MCM_REGISTERS_H__
-#define __HW_MCM_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 MCM
- *
- * Core Platform Miscellaneous Control Module
- *
- * Registers defined in this header file:
- * - HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
- * - HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
- * - HW_MCM_CR - Control Register
- * - HW_MCM_ISR - Interrupt Status Register
- * - HW_MCM_ETBCC - ETB Counter Control register
- * - HW_MCM_ETBRL - ETB Reload register
- * - HW_MCM_ETBCNT - ETB Counter Value register
- * - HW_MCM_PID - Process ID register
- *
- * - hw_mcm_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_MCM_BASE
-#define HW_MCM_INSTANCE_COUNT (1U) //!< Number of instances of the MCM module.
-#define REGS_MCM_BASE (0xE0080000U) //!< Base address for MCM.
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration (RO)
- *
- * Reset value: 0x001FU
- *
- * PLASC is a 16-bit read-only register identifying the presence/absence of bus
- * slave connections to the device's crossbar switch.
- */
-typedef union _hw_mcm_plasc
-{
- uint16_t U;
- struct _hw_mcm_plasc_bitfields
- {
- uint16_t ASC : 8; //!< [7:0] Each bit in the ASC field indicates
- //! whether there is a corresponding connection to the crossbar switch's slave
- //! input port.
- uint16_t RESERVED0 : 8; //!< [15:8]
- } B;
-} hw_mcm_plasc_t;
-#endif
-
-/*!
- * @name Constants and macros for entire MCM_PLASC register
- */
-//@{
-#define HW_MCM_PLASC_ADDR (REGS_MCM_BASE + 0x8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_MCM_PLASC (*(__I hw_mcm_plasc_t *) HW_MCM_PLASC_ADDR)
-#define HW_MCM_PLASC_RD() (HW_MCM_PLASC.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual MCM_PLASC bitfields
- */
-
-/*!
- * @name Register MCM_PLASC, field ASC[7:0] (RO)
- *
- * Values:
- * - 0 - A bus slave connection to AXBS input port n is absent
- * - 1 - A bus slave connection to AXBS input port n is present
- */
-//@{
-#define BP_MCM_PLASC_ASC (0U) //!< Bit position for MCM_PLASC_ASC.
-#define BM_MCM_PLASC_ASC (0x00FFU) //!< Bit mask for MCM_PLASC_ASC.
-#define BS_MCM_PLASC_ASC (8U) //!< Bit field size in bits for MCM_PLASC_ASC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCM_PLASC_ASC field.
-#define BR_MCM_PLASC_ASC (HW_MCM_PLASC.B.ASC)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration (RO)
- *
- * Reset value: 0x0037U
- *
- * PLAMC is a 16-bit read-only register identifying the presence/absence of bus
- * master connections to the device's crossbar switch.
- */
-typedef union _hw_mcm_plamc
-{
- uint16_t U;
- struct _hw_mcm_plamc_bitfields
- {
- uint16_t AMC : 8; //!< [7:0] Each bit in the AMC field indicates
- //! whether there is a corresponding connection to the AXBS master input port.
- uint16_t RESERVED0 : 8; //!< [15:8]
- } B;
-} hw_mcm_plamc_t;
-#endif
-
-/*!
- * @name Constants and macros for entire MCM_PLAMC register
- */
-//@{
-#define HW_MCM_PLAMC_ADDR (REGS_MCM_BASE + 0xAU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_MCM_PLAMC (*(__I hw_mcm_plamc_t *) HW_MCM_PLAMC_ADDR)
-#define HW_MCM_PLAMC_RD() (HW_MCM_PLAMC.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual MCM_PLAMC bitfields
- */
-
-/*!
- * @name Register MCM_PLAMC, field AMC[7:0] (RO)
- *
- * Values:
- * - 0 - A bus master connection to AXBS input port n is absent
- * - 1 - A bus master connection to AXBS input port n is present
- */
-//@{
-#define BP_MCM_PLAMC_AMC (0U) //!< Bit position for MCM_PLAMC_AMC.
-#define BM_MCM_PLAMC_AMC (0x00FFU) //!< Bit mask for MCM_PLAMC_AMC.
-#define BS_MCM_PLAMC_AMC (8U) //!< Bit field size in bits for MCM_PLAMC_AMC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCM_PLAMC_AMC field.
-#define BR_MCM_PLAMC_AMC (HW_MCM_PLAMC.B.AMC)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_MCM_CR - Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_MCM_CR - Control Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * CR defines the arbitration and protection schemes for the two system RAM
- * arrays.
- */
-typedef union _hw_mcm_cr
-{
- uint32_t U;
- struct _hw_mcm_cr_bitfields
- {
- uint32_t RESERVED0 : 24; //!< [23:0]
- uint32_t SRAMUAP : 2; //!< [25:24] SRAM_U arbitration priority
- uint32_t SRAMUWP : 1; //!< [26] SRAM_U write protect
- uint32_t RESERVED1 : 1; //!< [27]
- uint32_t SRAMLAP : 2; //!< [29:28] SRAM_L arbitration priority
- uint32_t SRAMLWP : 1; //!< [30] SRAM_L Write Protect
- uint32_t RESERVED2 : 1; //!< [31]
- } B;
-} hw_mcm_cr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire MCM_CR register
- */
-//@{
-#define HW_MCM_CR_ADDR (REGS_MCM_BASE + 0xCU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_MCM_CR (*(__IO hw_mcm_cr_t *) HW_MCM_CR_ADDR)
-#define HW_MCM_CR_RD() (HW_MCM_CR.U)
-#define HW_MCM_CR_WR(v) (HW_MCM_CR.U = (v))
-#define HW_MCM_CR_SET(v) (HW_MCM_CR_WR(HW_MCM_CR_RD() | (v)))
-#define HW_MCM_CR_CLR(v) (HW_MCM_CR_WR(HW_MCM_CR_RD() & ~(v)))
-#define HW_MCM_CR_TOG(v) (HW_MCM_CR_WR(HW_MCM_CR_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual MCM_CR bitfields
- */
-
-/*!
- * @name Register MCM_CR, field SRAMUAP[25:24] (RW)
- *
- * Defines the arbitration scheme and priority for the processor and SRAM
- * backdoor accesses to the SRAM_U array.
- *
- * Values:
- * - 00 - Round robin
- * - 01 - Special round robin (favors SRAM backoor accesses over the processor)
- * - 10 - Fixed priority. Processor has highest, backdoor has lowest
- * - 11 - Fixed priority. Backdoor has highest, processor has lowest
- */
-//@{
-#define BP_MCM_CR_SRAMUAP (24U) //!< Bit position for MCM_CR_SRAMUAP.
-#define BM_MCM_CR_SRAMUAP (0x03000000U) //!< Bit mask for MCM_CR_SRAMUAP.
-#define BS_MCM_CR_SRAMUAP (2U) //!< Bit field size in bits for MCM_CR_SRAMUAP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCM_CR_SRAMUAP field.
-#define BR_MCM_CR_SRAMUAP (HW_MCM_CR.B.SRAMUAP)
-#endif
-
-//! @brief Format value for bitfield MCM_CR_SRAMUAP.
-#define BF_MCM_CR_SRAMUAP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_CR_SRAMUAP), uint32_t) & BM_MCM_CR_SRAMUAP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SRAMUAP field to a new value.
-#define BW_MCM_CR_SRAMUAP(v) (HW_MCM_CR_WR((HW_MCM_CR_RD() & ~BM_MCM_CR_SRAMUAP) | BF_MCM_CR_SRAMUAP(v)))
-#endif
-//@}
-
-/*!
- * @name Register MCM_CR, field SRAMUWP[26] (RW)
- *
- * When this bit is set, writes to SRAM_U array generates a bus error.
- */
-//@{
-#define BP_MCM_CR_SRAMUWP (26U) //!< Bit position for MCM_CR_SRAMUWP.
-#define BM_MCM_CR_SRAMUWP (0x04000000U) //!< Bit mask for MCM_CR_SRAMUWP.
-#define BS_MCM_CR_SRAMUWP (1U) //!< Bit field size in bits for MCM_CR_SRAMUWP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCM_CR_SRAMUWP field.
-#define BR_MCM_CR_SRAMUWP (BITBAND_ACCESS32(HW_MCM_CR_ADDR, BP_MCM_CR_SRAMUWP))
-#endif
-
-//! @brief Format value for bitfield MCM_CR_SRAMUWP.
-#define BF_MCM_CR_SRAMUWP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_CR_SRAMUWP), uint32_t) & BM_MCM_CR_SRAMUWP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SRAMUWP field to a new value.
-#define BW_MCM_CR_SRAMUWP(v) (BITBAND_ACCESS32(HW_MCM_CR_ADDR, BP_MCM_CR_SRAMUWP) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCM_CR, field SRAMLAP[29:28] (RW)
- *
- * Defines the arbitration scheme and priority for the processor and SRAM
- * backdoor accesses to the SRAM_L array.
- *
- * Values:
- * - 00 - Round robin
- * - 01 - Special round robin (favors SRAM backoor accesses over the processor)
- * - 10 - Fixed priority. Processor has highest, backdoor has lowest
- * - 11 - Fixed priority. Backdoor has highest, processor has lowest
- */
-//@{
-#define BP_MCM_CR_SRAMLAP (28U) //!< Bit position for MCM_CR_SRAMLAP.
-#define BM_MCM_CR_SRAMLAP (0x30000000U) //!< Bit mask for MCM_CR_SRAMLAP.
-#define BS_MCM_CR_SRAMLAP (2U) //!< Bit field size in bits for MCM_CR_SRAMLAP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCM_CR_SRAMLAP field.
-#define BR_MCM_CR_SRAMLAP (HW_MCM_CR.B.SRAMLAP)
-#endif
-
-//! @brief Format value for bitfield MCM_CR_SRAMLAP.
-#define BF_MCM_CR_SRAMLAP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_CR_SRAMLAP), uint32_t) & BM_MCM_CR_SRAMLAP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SRAMLAP field to a new value.
-#define BW_MCM_CR_SRAMLAP(v) (HW_MCM_CR_WR((HW_MCM_CR_RD() & ~BM_MCM_CR_SRAMLAP) | BF_MCM_CR_SRAMLAP(v)))
-#endif
-//@}
-
-/*!
- * @name Register MCM_CR, field SRAMLWP[30] (RW)
- *
- * When this bit is set, writes to SRAM_L array generates a bus error.
- */
-//@{
-#define BP_MCM_CR_SRAMLWP (30U) //!< Bit position for MCM_CR_SRAMLWP.
-#define BM_MCM_CR_SRAMLWP (0x40000000U) //!< Bit mask for MCM_CR_SRAMLWP.
-#define BS_MCM_CR_SRAMLWP (1U) //!< Bit field size in bits for MCM_CR_SRAMLWP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCM_CR_SRAMLWP field.
-#define BR_MCM_CR_SRAMLWP (BITBAND_ACCESS32(HW_MCM_CR_ADDR, BP_MCM_CR_SRAMLWP))
-#endif
-
-//! @brief Format value for bitfield MCM_CR_SRAMLWP.
-#define BF_MCM_CR_SRAMLWP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_CR_SRAMLWP), uint32_t) & BM_MCM_CR_SRAMLWP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SRAMLWP field to a new value.
-#define BW_MCM_CR_SRAMLWP(v) (BITBAND_ACCESS32(HW_MCM_CR_ADDR, BP_MCM_CR_SRAMLWP) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_MCM_ISR - Interrupt Status Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_MCM_ISR - Interrupt Status Register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_mcm_isr
-{
- uint32_t U;
- struct _hw_mcm_isr_bitfields
- {
- uint32_t RESERVED0 : 1; //!< [0]
- uint32_t IRQ : 1; //!< [1] Normal Interrupt Pending
- uint32_t NMI : 1; //!< [2] Non-maskable Interrupt Pending
- uint32_t DHREQ : 1; //!< [3] Debug Halt Request Indicator
- uint32_t RESERVED1 : 4; //!< [7:4]
- uint32_t FIOC : 1; //!< [8] FPU invalid operation interrupt status
- uint32_t FDZC : 1; //!< [9] FPU divide-by-zero interrupt status
- uint32_t FOFC : 1; //!< [10] FPU overflow interrupt status
- uint32_t FUFC : 1; //!< [11] FPU underflow interrupt status
- uint32_t FIXC : 1; //!< [12] FPU inexact interrupt status
- uint32_t RESERVED2 : 2; //!< [14:13]
- uint32_t FIDC : 1; //!< [15] FPU input denormal interrupt status
- uint32_t RESERVED3 : 8; //!< [23:16]
- uint32_t FIOCE : 1; //!< [24] FPU invalid operation interrupt enable
- uint32_t FDZCE : 1; //!< [25] FPU divide-by-zero interrupt enable
- uint32_t FOFCE : 1; //!< [26] FPU overflow interrupt enable
- uint32_t FUFCE : 1; //!< [27] FPU underflow interrupt enable
- uint32_t FIXCE : 1; //!< [28] FPU inexact interrupt enable
- uint32_t RESERVED4 : 2; //!< [30:29]
- uint32_t FIDCE : 1; //!< [31] FPU input denormal interrupt enable
- } B;
-} hw_mcm_isr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire MCM_ISR register
- */
-//@{
-#define HW_MCM_ISR_ADDR (REGS_MCM_BASE + 0x10U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_MCM_ISR (*(__IO hw_mcm_isr_t *) HW_MCM_ISR_ADDR)
-#define HW_MCM_ISR_RD() (HW_MCM_ISR.U)
-#define HW_MCM_ISR_WR(v) (HW_MCM_ISR.U = (v))
-#define HW_MCM_ISR_SET(v) (HW_MCM_ISR_WR(HW_MCM_ISR_RD() | (v)))
-#define HW_MCM_ISR_CLR(v) (HW_MCM_ISR_WR(HW_MCM_ISR_RD() & ~(v)))
-#define HW_MCM_ISR_TOG(v) (HW_MCM_ISR_WR(HW_MCM_ISR_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual MCM_ISR bitfields
- */
-
-/*!
- * @name Register MCM_ISR, field IRQ[1] (W1C)
- *
- * If ETBCC[RSPT] is set to 01b, this bit is set when the ETB counter expires.
- *
- * Values:
- * - 0 - No pending interrupt
- * - 1 - Due to the ETB counter expiring, a normal interrupt is pending
- */
-//@{
-#define BP_MCM_ISR_IRQ (1U) //!< Bit position for MCM_ISR_IRQ.
-#define BM_MCM_ISR_IRQ (0x00000002U) //!< Bit mask for MCM_ISR_IRQ.
-#define BS_MCM_ISR_IRQ (1U) //!< Bit field size in bits for MCM_ISR_IRQ.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCM_ISR_IRQ field.
-#define BR_MCM_ISR_IRQ (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_IRQ))
-#endif
-
-//! @brief Format value for bitfield MCM_ISR_IRQ.
-#define BF_MCM_ISR_IRQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_IRQ), uint32_t) & BM_MCM_ISR_IRQ)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IRQ field to a new value.
-#define BW_MCM_ISR_IRQ(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_IRQ) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCM_ISR, field NMI[2] (W1C)
- *
- * If ETBCC[RSPT] is set to 10b, this bit is set when the ETB counter expires.
- *
- * Values:
- * - 0 - No pending NMI
- * - 1 - Due to the ETB counter expiring, an NMI is pending
- */
-//@{
-#define BP_MCM_ISR_NMI (2U) //!< Bit position for MCM_ISR_NMI.
-#define BM_MCM_ISR_NMI (0x00000004U) //!< Bit mask for MCM_ISR_NMI.
-#define BS_MCM_ISR_NMI (1U) //!< Bit field size in bits for MCM_ISR_NMI.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCM_ISR_NMI field.
-#define BR_MCM_ISR_NMI (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_NMI))
-#endif
-
-//! @brief Format value for bitfield MCM_ISR_NMI.
-#define BF_MCM_ISR_NMI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_NMI), uint32_t) & BM_MCM_ISR_NMI)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the NMI field to a new value.
-#define BW_MCM_ISR_NMI(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_NMI) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCM_ISR, field DHREQ[3] (RO)
- *
- * Indicates that a debug halt request is initiated due to a ETB counter
- * expiration, ETBCC[2:0] = 3b111 & ETBCV[10:0] = 11h0. This bit is cleared when the
- * counter is disabled or when the ETB counter is reloaded.
- *
- * Values:
- * - 0 - No debug halt request
- * - 1 - Debug halt request initiated
- */
-//@{
-#define BP_MCM_ISR_DHREQ (3U) //!< Bit position for MCM_ISR_DHREQ.
-#define BM_MCM_ISR_DHREQ (0x00000008U) //!< Bit mask for MCM_ISR_DHREQ.
-#define BS_MCM_ISR_DHREQ (1U) //!< Bit field size in bits for MCM_ISR_DHREQ.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCM_ISR_DHREQ field.
-#define BR_MCM_ISR_DHREQ (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_DHREQ))
-#endif
-//@}
-
-/*!
- * @name Register MCM_ISR, field FIOC[8] (RO)
- *
- * This read-only bit is a copy of the core's FPSCR[IOC] bit and signals an
- * illegal operation has been detected in the processor's FPU. Once set, this bit
- * remains set until software clears the FPSCR[IOC] bit.
- *
- * Values:
- * - 0 - No interrupt
- * - 1 - Interrupt occurred
- */
-//@{
-#define BP_MCM_ISR_FIOC (8U) //!< Bit position for MCM_ISR_FIOC.
-#define BM_MCM_ISR_FIOC (0x00000100U) //!< Bit mask for MCM_ISR_FIOC.
-#define BS_MCM_ISR_FIOC (1U) //!< Bit field size in bits for MCM_ISR_FIOC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCM_ISR_FIOC field.
-#define BR_MCM_ISR_FIOC (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIOC))
-#endif
-//@}
-
-/*!
- * @name Register MCM_ISR, field FDZC[9] (RO)
- *
- * This read-only bit is a copy of the core's FPSCR[DZC] bit and signals a
- * divide by zero has been detected in the processor's FPU. Once set, this bit remains
- * set until software clears the FPSCR[DZC] bit.
- *
- * Values:
- * - 0 - No interrupt
- * - 1 - Interrupt occurred
- */
-//@{
-#define BP_MCM_ISR_FDZC (9U) //!< Bit position for MCM_ISR_FDZC.
-#define BM_MCM_ISR_FDZC (0x00000200U) //!< Bit mask for MCM_ISR_FDZC.
-#define BS_MCM_ISR_FDZC (1U) //!< Bit field size in bits for MCM_ISR_FDZC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCM_ISR_FDZC field.
-#define BR_MCM_ISR_FDZC (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FDZC))
-#endif
-//@}
-
-/*!
- * @name Register MCM_ISR, field FOFC[10] (RO)
- *
- * This read-only bit is a copy of the core's FPSCR[OFC] bit and signals an
- * overflow has been detected in the processor's FPU. Once set, this bit remains set
- * until software clears the FPSCR[OFC] bit.
- *
- * Values:
- * - 0 - No interrupt
- * - 1 - Interrupt occurred
- */
-//@{
-#define BP_MCM_ISR_FOFC (10U) //!< Bit position for MCM_ISR_FOFC.
-#define BM_MCM_ISR_FOFC (0x00000400U) //!< Bit mask for MCM_ISR_FOFC.
-#define BS_MCM_ISR_FOFC (1U) //!< Bit field size in bits for MCM_ISR_FOFC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCM_ISR_FOFC field.
-#define BR_MCM_ISR_FOFC (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FOFC))
-#endif
-//@}
-
-/*!
- * @name Register MCM_ISR, field FUFC[11] (RO)
- *
- * This read-only bit is a copy of the core's FPSCR[UFC] bit and signals an
- * underflow has been detected in the processor's FPU. Once set, this bit remains set
- * until software clears the FPSCR[UFC] bit.
- *
- * Values:
- * - 0 - No interrupt
- * - 1 - Interrupt occurred
- */
-//@{
-#define BP_MCM_ISR_FUFC (11U) //!< Bit position for MCM_ISR_FUFC.
-#define BM_MCM_ISR_FUFC (0x00000800U) //!< Bit mask for MCM_ISR_FUFC.
-#define BS_MCM_ISR_FUFC (1U) //!< Bit field size in bits for MCM_ISR_FUFC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCM_ISR_FUFC field.
-#define BR_MCM_ISR_FUFC (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FUFC))
-#endif
-//@}
-
-/*!
- * @name Register MCM_ISR, field FIXC[12] (RO)
- *
- * This read-only bit is a copy of the core's FPSCR[IXC] bit and signals an
- * inexact number has been detected in the processor's FPU. Once set, this bit
- * remains set until software clears the FPSCR[IXC] bit.
- *
- * Values:
- * - 0 - No interrupt
- * - 1 - Interrupt occurred
- */
-//@{
-#define BP_MCM_ISR_FIXC (12U) //!< Bit position for MCM_ISR_FIXC.
-#define BM_MCM_ISR_FIXC (0x00001000U) //!< Bit mask for MCM_ISR_FIXC.
-#define BS_MCM_ISR_FIXC (1U) //!< Bit field size in bits for MCM_ISR_FIXC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCM_ISR_FIXC field.
-#define BR_MCM_ISR_FIXC (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIXC))
-#endif
-//@}
-
-/*!
- * @name Register MCM_ISR, field FIDC[15] (RO)
- *
- * This read-only bit is a copy of the core's FPSCR[IDC] bit and signals input
- * denormalized number has been detected in the processor's FPU. Once set, this
- * bit remains set until software clears the FPSCR[IDC] bit.
- *
- * Values:
- * - 0 - No interrupt
- * - 1 - Interrupt occurred
- */
-//@{
-#define BP_MCM_ISR_FIDC (15U) //!< Bit position for MCM_ISR_FIDC.
-#define BM_MCM_ISR_FIDC (0x00008000U) //!< Bit mask for MCM_ISR_FIDC.
-#define BS_MCM_ISR_FIDC (1U) //!< Bit field size in bits for MCM_ISR_FIDC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCM_ISR_FIDC field.
-#define BR_MCM_ISR_FIDC (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIDC))
-#endif
-//@}
-
-/*!
- * @name Register MCM_ISR, field FIOCE[24] (RW)
- *
- * Values:
- * - 0 - Disable interrupt
- * - 1 - Enable interrupt
- */
-//@{
-#define BP_MCM_ISR_FIOCE (24U) //!< Bit position for MCM_ISR_FIOCE.
-#define BM_MCM_ISR_FIOCE (0x01000000U) //!< Bit mask for MCM_ISR_FIOCE.
-#define BS_MCM_ISR_FIOCE (1U) //!< Bit field size in bits for MCM_ISR_FIOCE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCM_ISR_FIOCE field.
-#define BR_MCM_ISR_FIOCE (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIOCE))
-#endif
-
-//! @brief Format value for bitfield MCM_ISR_FIOCE.
-#define BF_MCM_ISR_FIOCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FIOCE), uint32_t) & BM_MCM_ISR_FIOCE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FIOCE field to a new value.
-#define BW_MCM_ISR_FIOCE(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIOCE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCM_ISR, field FDZCE[25] (RW)
- *
- * Values:
- * - 0 - Disable interrupt
- * - 1 - Enable interrupt
- */
-//@{
-#define BP_MCM_ISR_FDZCE (25U) //!< Bit position for MCM_ISR_FDZCE.
-#define BM_MCM_ISR_FDZCE (0x02000000U) //!< Bit mask for MCM_ISR_FDZCE.
-#define BS_MCM_ISR_FDZCE (1U) //!< Bit field size in bits for MCM_ISR_FDZCE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCM_ISR_FDZCE field.
-#define BR_MCM_ISR_FDZCE (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FDZCE))
-#endif
-
-//! @brief Format value for bitfield MCM_ISR_FDZCE.
-#define BF_MCM_ISR_FDZCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FDZCE), uint32_t) & BM_MCM_ISR_FDZCE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FDZCE field to a new value.
-#define BW_MCM_ISR_FDZCE(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FDZCE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCM_ISR, field FOFCE[26] (RW)
- *
- * Values:
- * - 0 - Disable interrupt
- * - 1 - Enable interrupt
- */
-//@{
-#define BP_MCM_ISR_FOFCE (26U) //!< Bit position for MCM_ISR_FOFCE.
-#define BM_MCM_ISR_FOFCE (0x04000000U) //!< Bit mask for MCM_ISR_FOFCE.
-#define BS_MCM_ISR_FOFCE (1U) //!< Bit field size in bits for MCM_ISR_FOFCE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCM_ISR_FOFCE field.
-#define BR_MCM_ISR_FOFCE (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FOFCE))
-#endif
-
-//! @brief Format value for bitfield MCM_ISR_FOFCE.
-#define BF_MCM_ISR_FOFCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FOFCE), uint32_t) & BM_MCM_ISR_FOFCE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FOFCE field to a new value.
-#define BW_MCM_ISR_FOFCE(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FOFCE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCM_ISR, field FUFCE[27] (RW)
- *
- * Values:
- * - 0 - Disable interrupt
- * - 1 - Enable interrupt
- */
-//@{
-#define BP_MCM_ISR_FUFCE (27U) //!< Bit position for MCM_ISR_FUFCE.
-#define BM_MCM_ISR_FUFCE (0x08000000U) //!< Bit mask for MCM_ISR_FUFCE.
-#define BS_MCM_ISR_FUFCE (1U) //!< Bit field size in bits for MCM_ISR_FUFCE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCM_ISR_FUFCE field.
-#define BR_MCM_ISR_FUFCE (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FUFCE))
-#endif
-
-//! @brief Format value for bitfield MCM_ISR_FUFCE.
-#define BF_MCM_ISR_FUFCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FUFCE), uint32_t) & BM_MCM_ISR_FUFCE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FUFCE field to a new value.
-#define BW_MCM_ISR_FUFCE(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FUFCE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCM_ISR, field FIXCE[28] (RW)
- *
- * Values:
- * - 0 - Disable interrupt
- * - 1 - Enable interrupt
- */
-//@{
-#define BP_MCM_ISR_FIXCE (28U) //!< Bit position for MCM_ISR_FIXCE.
-#define BM_MCM_ISR_FIXCE (0x10000000U) //!< Bit mask for MCM_ISR_FIXCE.
-#define BS_MCM_ISR_FIXCE (1U) //!< Bit field size in bits for MCM_ISR_FIXCE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCM_ISR_FIXCE field.
-#define BR_MCM_ISR_FIXCE (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIXCE))
-#endif
-
-//! @brief Format value for bitfield MCM_ISR_FIXCE.
-#define BF_MCM_ISR_FIXCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FIXCE), uint32_t) & BM_MCM_ISR_FIXCE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FIXCE field to a new value.
-#define BW_MCM_ISR_FIXCE(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIXCE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCM_ISR, field FIDCE[31] (RW)
- *
- * Values:
- * - 0 - Disable interrupt
- * - 1 - Enable interrupt
- */
-//@{
-#define BP_MCM_ISR_FIDCE (31U) //!< Bit position for MCM_ISR_FIDCE.
-#define BM_MCM_ISR_FIDCE (0x80000000U) //!< Bit mask for MCM_ISR_FIDCE.
-#define BS_MCM_ISR_FIDCE (1U) //!< Bit field size in bits for MCM_ISR_FIDCE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCM_ISR_FIDCE field.
-#define BR_MCM_ISR_FIDCE (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIDCE))
-#endif
-
-//! @brief Format value for bitfield MCM_ISR_FIDCE.
-#define BF_MCM_ISR_FIDCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FIDCE), uint32_t) & BM_MCM_ISR_FIDCE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FIDCE field to a new value.
-#define BW_MCM_ISR_FIDCE(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIDCE) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_MCM_ETBCC - ETB Counter Control register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_MCM_ETBCC - ETB Counter Control register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_mcm_etbcc
-{
- uint32_t U;
- struct _hw_mcm_etbcc_bitfields
- {
- uint32_t CNTEN : 1; //!< [0] Counter Enable
- uint32_t RSPT : 2; //!< [2:1] Response Type
- uint32_t RLRQ : 1; //!< [3] Reload Request
- uint32_t ETDIS : 1; //!< [4] ETM-To-TPIU Disable
- uint32_t ITDIS : 1; //!< [5] ITM-To-TPIU Disable
- uint32_t RESERVED0 : 26; //!< [31:6]
- } B;
-} hw_mcm_etbcc_t;
-#endif
-
-/*!
- * @name Constants and macros for entire MCM_ETBCC register
- */
-//@{
-#define HW_MCM_ETBCC_ADDR (REGS_MCM_BASE + 0x14U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_MCM_ETBCC (*(__IO hw_mcm_etbcc_t *) HW_MCM_ETBCC_ADDR)
-#define HW_MCM_ETBCC_RD() (HW_MCM_ETBCC.U)
-#define HW_MCM_ETBCC_WR(v) (HW_MCM_ETBCC.U = (v))
-#define HW_MCM_ETBCC_SET(v) (HW_MCM_ETBCC_WR(HW_MCM_ETBCC_RD() | (v)))
-#define HW_MCM_ETBCC_CLR(v) (HW_MCM_ETBCC_WR(HW_MCM_ETBCC_RD() & ~(v)))
-#define HW_MCM_ETBCC_TOG(v) (HW_MCM_ETBCC_WR(HW_MCM_ETBCC_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual MCM_ETBCC bitfields
- */
-
-/*!
- * @name Register MCM_ETBCC, field CNTEN[0] (RW)
- *
- * Enables the ETB counter.
- *
- * Values:
- * - 0 - ETB counter disabled
- * - 1 - ETB counter enabled
- */
-//@{
-#define BP_MCM_ETBCC_CNTEN (0U) //!< Bit position for MCM_ETBCC_CNTEN.
-#define BM_MCM_ETBCC_CNTEN (0x00000001U) //!< Bit mask for MCM_ETBCC_CNTEN.
-#define BS_MCM_ETBCC_CNTEN (1U) //!< Bit field size in bits for MCM_ETBCC_CNTEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCM_ETBCC_CNTEN field.
-#define BR_MCM_ETBCC_CNTEN (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_CNTEN))
-#endif
-
-//! @brief Format value for bitfield MCM_ETBCC_CNTEN.
-#define BF_MCM_ETBCC_CNTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBCC_CNTEN), uint32_t) & BM_MCM_ETBCC_CNTEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CNTEN field to a new value.
-#define BW_MCM_ETBCC_CNTEN(v) (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_CNTEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCM_ETBCC, field RSPT[2:1] (RW)
- *
- * Values:
- * - 00 - No response when the ETB count expires
- * - 01 - Generate a normal interrupt when the ETB count expires
- * - 10 - Generate an NMI when the ETB count expires
- * - 11 - Generate a debug halt when the ETB count expires
- */
-//@{
-#define BP_MCM_ETBCC_RSPT (1U) //!< Bit position for MCM_ETBCC_RSPT.
-#define BM_MCM_ETBCC_RSPT (0x00000006U) //!< Bit mask for MCM_ETBCC_RSPT.
-#define BS_MCM_ETBCC_RSPT (2U) //!< Bit field size in bits for MCM_ETBCC_RSPT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCM_ETBCC_RSPT field.
-#define BR_MCM_ETBCC_RSPT (HW_MCM_ETBCC.B.RSPT)
-#endif
-
-//! @brief Format value for bitfield MCM_ETBCC_RSPT.
-#define BF_MCM_ETBCC_RSPT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBCC_RSPT), uint32_t) & BM_MCM_ETBCC_RSPT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RSPT field to a new value.
-#define BW_MCM_ETBCC_RSPT(v) (HW_MCM_ETBCC_WR((HW_MCM_ETBCC_RD() & ~BM_MCM_ETBCC_RSPT) | BF_MCM_ETBCC_RSPT(v)))
-#endif
-//@}
-
-/*!
- * @name Register MCM_ETBCC, field RLRQ[3] (RW)
- *
- * Reloads the ETB packet counter with the MCM_ETBRL RELOAD value. If IRQ or NMI
- * interrupts were enabled and an NMI or IRQ interrupt was generated on counter
- * expiration, setting this bit clears the pending NMI or IRQ interrupt request.
- * If debug halt was enabled and a debug halt request was asserted on counter
- * expiration, setting this bit clears the debug halt request.
- *
- * Values:
- * - 0 - No effect
- * - 1 - Clears pending debug halt, NMI, or IRQ interrupt requests
- */
-//@{
-#define BP_MCM_ETBCC_RLRQ (3U) //!< Bit position for MCM_ETBCC_RLRQ.
-#define BM_MCM_ETBCC_RLRQ (0x00000008U) //!< Bit mask for MCM_ETBCC_RLRQ.
-#define BS_MCM_ETBCC_RLRQ (1U) //!< Bit field size in bits for MCM_ETBCC_RLRQ.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCM_ETBCC_RLRQ field.
-#define BR_MCM_ETBCC_RLRQ (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_RLRQ))
-#endif
-
-//! @brief Format value for bitfield MCM_ETBCC_RLRQ.
-#define BF_MCM_ETBCC_RLRQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBCC_RLRQ), uint32_t) & BM_MCM_ETBCC_RLRQ)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RLRQ field to a new value.
-#define BW_MCM_ETBCC_RLRQ(v) (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_RLRQ) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCM_ETBCC, field ETDIS[4] (RW)
- *
- * Disables the trace path from ETM to TPIU.
- *
- * Values:
- * - 0 - ETM-to-TPIU trace path enabled
- * - 1 - ETM-to-TPIU trace path disabled
- */
-//@{
-#define BP_MCM_ETBCC_ETDIS (4U) //!< Bit position for MCM_ETBCC_ETDIS.
-#define BM_MCM_ETBCC_ETDIS (0x00000010U) //!< Bit mask for MCM_ETBCC_ETDIS.
-#define BS_MCM_ETBCC_ETDIS (1U) //!< Bit field size in bits for MCM_ETBCC_ETDIS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCM_ETBCC_ETDIS field.
-#define BR_MCM_ETBCC_ETDIS (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_ETDIS))
-#endif
-
-//! @brief Format value for bitfield MCM_ETBCC_ETDIS.
-#define BF_MCM_ETBCC_ETDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBCC_ETDIS), uint32_t) & BM_MCM_ETBCC_ETDIS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ETDIS field to a new value.
-#define BW_MCM_ETBCC_ETDIS(v) (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_ETDIS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MCM_ETBCC, field ITDIS[5] (RW)
- *
- * Disables the trace path from ITM to TPIU.
- *
- * Values:
- * - 0 - ITM-to-TPIU trace path enabled
- * - 1 - ITM-to-TPIU trace path disabled
- */
-//@{
-#define BP_MCM_ETBCC_ITDIS (5U) //!< Bit position for MCM_ETBCC_ITDIS.
-#define BM_MCM_ETBCC_ITDIS (0x00000020U) //!< Bit mask for MCM_ETBCC_ITDIS.
-#define BS_MCM_ETBCC_ITDIS (1U) //!< Bit field size in bits for MCM_ETBCC_ITDIS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCM_ETBCC_ITDIS field.
-#define BR_MCM_ETBCC_ITDIS (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_ITDIS))
-#endif
-
-//! @brief Format value for bitfield MCM_ETBCC_ITDIS.
-#define BF_MCM_ETBCC_ITDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBCC_ITDIS), uint32_t) & BM_MCM_ETBCC_ITDIS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ITDIS field to a new value.
-#define BW_MCM_ETBCC_ITDIS(v) (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_ITDIS) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_MCM_ETBRL - ETB Reload register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_MCM_ETBRL - ETB Reload register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_mcm_etbrl
-{
- uint32_t U;
- struct _hw_mcm_etbrl_bitfields
- {
- uint32_t RELOAD : 11; //!< [10:0] Byte Count Reload Value
- uint32_t RESERVED0 : 21; //!< [31:11]
- } B;
-} hw_mcm_etbrl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire MCM_ETBRL register
- */
-//@{
-#define HW_MCM_ETBRL_ADDR (REGS_MCM_BASE + 0x18U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_MCM_ETBRL (*(__IO hw_mcm_etbrl_t *) HW_MCM_ETBRL_ADDR)
-#define HW_MCM_ETBRL_RD() (HW_MCM_ETBRL.U)
-#define HW_MCM_ETBRL_WR(v) (HW_MCM_ETBRL.U = (v))
-#define HW_MCM_ETBRL_SET(v) (HW_MCM_ETBRL_WR(HW_MCM_ETBRL_RD() | (v)))
-#define HW_MCM_ETBRL_CLR(v) (HW_MCM_ETBRL_WR(HW_MCM_ETBRL_RD() & ~(v)))
-#define HW_MCM_ETBRL_TOG(v) (HW_MCM_ETBRL_WR(HW_MCM_ETBRL_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual MCM_ETBRL bitfields
- */
-
-/*!
- * @name Register MCM_ETBRL, field RELOAD[10:0] (RW)
- *
- * Indicates the 0-mod-4 value the counter reloads to. Writing a non-0-mod-4
- * value to this field results in a bus error.
- */
-//@{
-#define BP_MCM_ETBRL_RELOAD (0U) //!< Bit position for MCM_ETBRL_RELOAD.
-#define BM_MCM_ETBRL_RELOAD (0x000007FFU) //!< Bit mask for MCM_ETBRL_RELOAD.
-#define BS_MCM_ETBRL_RELOAD (11U) //!< Bit field size in bits for MCM_ETBRL_RELOAD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCM_ETBRL_RELOAD field.
-#define BR_MCM_ETBRL_RELOAD (HW_MCM_ETBRL.B.RELOAD)
-#endif
-
-//! @brief Format value for bitfield MCM_ETBRL_RELOAD.
-#define BF_MCM_ETBRL_RELOAD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBRL_RELOAD), uint32_t) & BM_MCM_ETBRL_RELOAD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RELOAD field to a new value.
-#define BW_MCM_ETBRL_RELOAD(v) (HW_MCM_ETBRL_WR((HW_MCM_ETBRL_RD() & ~BM_MCM_ETBRL_RELOAD) | BF_MCM_ETBRL_RELOAD(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_MCM_ETBCNT - ETB Counter Value register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_MCM_ETBCNT - ETB Counter Value register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_mcm_etbcnt
-{
- uint32_t U;
- struct _hw_mcm_etbcnt_bitfields
- {
- uint32_t COUNTER : 11; //!< [10:0] Byte Count Counter Value
- uint32_t RESERVED0 : 21; //!< [31:11]
- } B;
-} hw_mcm_etbcnt_t;
-#endif
-
-/*!
- * @name Constants and macros for entire MCM_ETBCNT register
- */
-//@{
-#define HW_MCM_ETBCNT_ADDR (REGS_MCM_BASE + 0x1CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_MCM_ETBCNT (*(__I hw_mcm_etbcnt_t *) HW_MCM_ETBCNT_ADDR)
-#define HW_MCM_ETBCNT_RD() (HW_MCM_ETBCNT.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual MCM_ETBCNT bitfields
- */
-
-/*!
- * @name Register MCM_ETBCNT, field COUNTER[10:0] (RO)
- *
- * Indicates the current 0-mod-4 value of the counter.
- */
-//@{
-#define BP_MCM_ETBCNT_COUNTER (0U) //!< Bit position for MCM_ETBCNT_COUNTER.
-#define BM_MCM_ETBCNT_COUNTER (0x000007FFU) //!< Bit mask for MCM_ETBCNT_COUNTER.
-#define BS_MCM_ETBCNT_COUNTER (11U) //!< Bit field size in bits for MCM_ETBCNT_COUNTER.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCM_ETBCNT_COUNTER field.
-#define BR_MCM_ETBCNT_COUNTER (HW_MCM_ETBCNT.B.COUNTER)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_MCM_PID - Process ID register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_MCM_PID - Process ID register (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register drives the M0_PID and M1_PID values in the Memory Protection
- * Unit(MPU). System software loads this register before passing control to a given
- * user mode process. If the PID of the process does not match the value in this
- * register, a bus error occurs. See the MPU chapter for more details.
- */
-typedef union _hw_mcm_pid
-{
- uint32_t U;
- struct _hw_mcm_pid_bitfields
- {
- uint32_t PID : 8; //!< [7:0] M0_PID And M1_PID For MPU
- uint32_t RESERVED0 : 24; //!< [31:8]
- } B;
-} hw_mcm_pid_t;
-#endif
-
-/*!
- * @name Constants and macros for entire MCM_PID register
- */
-//@{
-#define HW_MCM_PID_ADDR (REGS_MCM_BASE + 0x30U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_MCM_PID (*(__IO hw_mcm_pid_t *) HW_MCM_PID_ADDR)
-#define HW_MCM_PID_RD() (HW_MCM_PID.U)
-#define HW_MCM_PID_WR(v) (HW_MCM_PID.U = (v))
-#define HW_MCM_PID_SET(v) (HW_MCM_PID_WR(HW_MCM_PID_RD() | (v)))
-#define HW_MCM_PID_CLR(v) (HW_MCM_PID_WR(HW_MCM_PID_RD() & ~(v)))
-#define HW_MCM_PID_TOG(v) (HW_MCM_PID_WR(HW_MCM_PID_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual MCM_PID bitfields
- */
-
-/*!
- * @name Register MCM_PID, field PID[7:0] (RW)
- *
- * Drives the M0_PID and M1_PID values in the MPU.
- */
-//@{
-#define BP_MCM_PID_PID (0U) //!< Bit position for MCM_PID_PID.
-#define BM_MCM_PID_PID (0x000000FFU) //!< Bit mask for MCM_PID_PID.
-#define BS_MCM_PID_PID (8U) //!< Bit field size in bits for MCM_PID_PID.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MCM_PID_PID field.
-#define BR_MCM_PID_PID (HW_MCM_PID.B.PID)
-#endif
-
-//! @brief Format value for bitfield MCM_PID_PID.
-#define BF_MCM_PID_PID(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_PID_PID), uint32_t) & BM_MCM_PID_PID)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PID field to a new value.
-#define BW_MCM_PID_PID(v) (HW_MCM_PID_WR((HW_MCM_PID_RD() & ~BM_MCM_PID_PID) | BF_MCM_PID_PID(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_mcm_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All MCM module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_mcm
-{
- uint8_t _reserved0[8];
- __I hw_mcm_plasc_t PLASC; //!< [0x8] Crossbar Switch (AXBS) Slave Configuration
- __I hw_mcm_plamc_t PLAMC; //!< [0xA] Crossbar Switch (AXBS) Master Configuration
- __IO hw_mcm_cr_t CR; //!< [0xC] Control Register
- __IO hw_mcm_isr_t ISR; //!< [0x10] Interrupt Status Register
- __IO hw_mcm_etbcc_t ETBCC; //!< [0x14] ETB Counter Control register
- __IO hw_mcm_etbrl_t ETBRL; //!< [0x18] ETB Reload register
- __I hw_mcm_etbcnt_t ETBCNT; //!< [0x1C] ETB Counter Value register
- uint8_t _reserved1[16];
- __IO hw_mcm_pid_t PID; //!< [0x30] Process ID register
-} hw_mcm_t;
-#pragma pack()
-
-//! @brief Macro to access all MCM registers.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_MCM</code>.
-#define HW_MCM (*(hw_mcm_t *) REGS_MCM_BASE)
-#endif
-
-#endif // __HW_MCM_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_mpu.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1923 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_MPU_REGISTERS_H__
-#define __HW_MPU_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 MPU
- *
- * Memory protection unit
- *
- * Registers defined in this header file:
- * - HW_MPU_CESR - Control/Error Status Register
- * - HW_MPU_EARn - Error Address Register, slave port n
- * - HW_MPU_EDRn - Error Detail Register, slave port n
- * - HW_MPU_RGDn_WORD0 - Region Descriptor n, Word 0
- * - HW_MPU_RGDn_WORD1 - Region Descriptor n, Word 1
- * - HW_MPU_RGDn_WORD2 - Region Descriptor n, Word 2
- * - HW_MPU_RGDn_WORD3 - Region Descriptor n, Word 3
- * - HW_MPU_RGDAACn - Region Descriptor Alternate Access Control n
- *
- * - hw_mpu_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_MPU_BASE
-#define HW_MPU_INSTANCE_COUNT (1U) //!< Number of instances of the MPU module.
-#define REGS_MPU_BASE (0x4000D000U) //!< Base address for MPU.
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_MPU_CESR - Control/Error Status Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_MPU_CESR - Control/Error Status Register (RW)
- *
- * Reset value: 0x00815101U
- */
-typedef union _hw_mpu_cesr
-{
- uint32_t U;
- struct _hw_mpu_cesr_bitfields
- {
- uint32_t VLD : 1; //!< [0] Valid
- uint32_t RESERVED0 : 7; //!< [7:1]
- uint32_t NRGD : 4; //!< [11:8] Number Of Region Descriptors
- uint32_t NSP : 4; //!< [15:12] Number Of Slave Ports
- uint32_t HRL : 4; //!< [19:16] Hardware Revision Level
- uint32_t RESERVED1 : 7; //!< [26:20]
- uint32_t SPERR : 5; //!< [31:27] Slave Port n Error
- } B;
-} hw_mpu_cesr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire MPU_CESR register
- */
-//@{
-#define HW_MPU_CESR_ADDR (REGS_MPU_BASE + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_MPU_CESR (*(__IO hw_mpu_cesr_t *) HW_MPU_CESR_ADDR)
-#define HW_MPU_CESR_RD() (HW_MPU_CESR.U)
-#define HW_MPU_CESR_WR(v) (HW_MPU_CESR.U = (v))
-#define HW_MPU_CESR_SET(v) (HW_MPU_CESR_WR(HW_MPU_CESR_RD() | (v)))
-#define HW_MPU_CESR_CLR(v) (HW_MPU_CESR_WR(HW_MPU_CESR_RD() & ~(v)))
-#define HW_MPU_CESR_TOG(v) (HW_MPU_CESR_WR(HW_MPU_CESR_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual MPU_CESR bitfields
- */
-
-/*!
- * @name Register MPU_CESR, field VLD[0] (RW)
- *
- * Global enable/disable for the MPU.
- *
- * Values:
- * - 0 - MPU is disabled. All accesses from all bus masters are allowed.
- * - 1 - MPU is enabled
- */
-//@{
-#define BP_MPU_CESR_VLD (0U) //!< Bit position for MPU_CESR_VLD.
-#define BM_MPU_CESR_VLD (0x00000001U) //!< Bit mask for MPU_CESR_VLD.
-#define BS_MPU_CESR_VLD (1U) //!< Bit field size in bits for MPU_CESR_VLD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_CESR_VLD field.
-#define BR_MPU_CESR_VLD (BITBAND_ACCESS32(HW_MPU_CESR_ADDR, BP_MPU_CESR_VLD))
-#endif
-
-//! @brief Format value for bitfield MPU_CESR_VLD.
-#define BF_MPU_CESR_VLD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_CESR_VLD), uint32_t) & BM_MPU_CESR_VLD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the VLD field to a new value.
-#define BW_MPU_CESR_VLD(v) (BITBAND_ACCESS32(HW_MPU_CESR_ADDR, BP_MPU_CESR_VLD) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MPU_CESR, field NRGD[11:8] (RO)
- *
- * Indicates the number of region descriptors implemented in the MPU.
- *
- * Values:
- * - 0000 - 8 region descriptors
- * - 0001 - 12 region descriptors
- * - 0010 - 16 region descriptors
- */
-//@{
-#define BP_MPU_CESR_NRGD (8U) //!< Bit position for MPU_CESR_NRGD.
-#define BM_MPU_CESR_NRGD (0x00000F00U) //!< Bit mask for MPU_CESR_NRGD.
-#define BS_MPU_CESR_NRGD (4U) //!< Bit field size in bits for MPU_CESR_NRGD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_CESR_NRGD field.
-#define BR_MPU_CESR_NRGD (HW_MPU_CESR.B.NRGD)
-#endif
-//@}
-
-/*!
- * @name Register MPU_CESR, field NSP[15:12] (RO)
- *
- * Specifies the number of slave ports connected to the MPU.
- */
-//@{
-#define BP_MPU_CESR_NSP (12U) //!< Bit position for MPU_CESR_NSP.
-#define BM_MPU_CESR_NSP (0x0000F000U) //!< Bit mask for MPU_CESR_NSP.
-#define BS_MPU_CESR_NSP (4U) //!< Bit field size in bits for MPU_CESR_NSP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_CESR_NSP field.
-#define BR_MPU_CESR_NSP (HW_MPU_CESR.B.NSP)
-#endif
-//@}
-
-/*!
- * @name Register MPU_CESR, field HRL[19:16] (RO)
- *
- * Specifies the MPU's hardware and definition revision level. It can be read by
- * software to determine the functional definition of the module.
- */
-//@{
-#define BP_MPU_CESR_HRL (16U) //!< Bit position for MPU_CESR_HRL.
-#define BM_MPU_CESR_HRL (0x000F0000U) //!< Bit mask for MPU_CESR_HRL.
-#define BS_MPU_CESR_HRL (4U) //!< Bit field size in bits for MPU_CESR_HRL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_CESR_HRL field.
-#define BR_MPU_CESR_HRL (HW_MPU_CESR.B.HRL)
-#endif
-//@}
-
-/*!
- * @name Register MPU_CESR, field SPERR[31:27] (W1C)
- *
- * Indicates a captured error in EARn and EDRn. This bit is set when the
- * hardware detects an error and records the faulting address and attributes. It is
- * cleared by writing one to it. If another error is captured at the exact same cycle
- * as the write, the flag remains set. A find-first-one instruction or
- * equivalent can detect the presence of a captured error. The following shows the
- * correspondence between the bit number and slave port number: Bit 31 corresponds to
- * slave port 0. Bit 30 corresponds to slave port 1. Bit 29 corresponds to slave
- * port 2. Bit 28 corresponds to slave port 3. Bit 27 corresponds to slave port 4.
- *
- * Values:
- * - 0 - No error has occurred for slave port n.
- * - 1 - An error has occurred for slave port n.
- */
-//@{
-#define BP_MPU_CESR_SPERR (27U) //!< Bit position for MPU_CESR_SPERR.
-#define BM_MPU_CESR_SPERR (0xF8000000U) //!< Bit mask for MPU_CESR_SPERR.
-#define BS_MPU_CESR_SPERR (5U) //!< Bit field size in bits for MPU_CESR_SPERR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_CESR_SPERR field.
-#define BR_MPU_CESR_SPERR (HW_MPU_CESR.B.SPERR)
-#endif
-
-//! @brief Format value for bitfield MPU_CESR_SPERR.
-#define BF_MPU_CESR_SPERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_CESR_SPERR), uint32_t) & BM_MPU_CESR_SPERR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SPERR field to a new value.
-#define BW_MPU_CESR_SPERR(v) (HW_MPU_CESR_WR((HW_MPU_CESR_RD() & ~BM_MPU_CESR_SPERR) | BF_MPU_CESR_SPERR(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_MPU_EARn - Error Address Register, slave port n
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_MPU_EARn - Error Address Register, slave port n (RO)
- *
- * Reset value: 0x00000000U
- *
- * When the MPU detects an access error on slave port n, the 32-bit reference
- * address is captured in this read-only register and the corresponding bit in
- * CESR[SPERR] set. Additional information about the faulting access is captured in
- * the corresponding EDRn at the same time. This register and the corresponding
- * EDRn contain the most recent access error; there are no hardware interlocks with
- * CESR[SPERR], as the error registers are always loaded upon the occurrence of
- * each protection violation.
- */
-typedef union _hw_mpu_earn
-{
- uint32_t U;
- struct _hw_mpu_earn_bitfields
- {
- uint32_t EADDR : 32; //!< [31:0] Error Address
- } B;
-} hw_mpu_earn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire MPU_EARn register
- */
-//@{
-#define HW_MPU_EARn_COUNT (5U)
-
-#define HW_MPU_EARn_ADDR(n) (REGS_MPU_BASE + 0x10U + (0x8U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_MPU_EARn(n) (*(__I hw_mpu_earn_t *) HW_MPU_EARn_ADDR(n))
-#define HW_MPU_EARn_RD(n) (HW_MPU_EARn(n).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual MPU_EARn bitfields
- */
-
-/*!
- * @name Register MPU_EARn, field EADDR[31:0] (RO)
- *
- * Indicates the reference address from slave port n that generated the access
- * error
- */
-//@{
-#define BP_MPU_EARn_EADDR (0U) //!< Bit position for MPU_EARn_EADDR.
-#define BM_MPU_EARn_EADDR (0xFFFFFFFFU) //!< Bit mask for MPU_EARn_EADDR.
-#define BS_MPU_EARn_EADDR (32U) //!< Bit field size in bits for MPU_EARn_EADDR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_EARn_EADDR field.
-#define BR_MPU_EARn_EADDR(n) (HW_MPU_EARn(n).U)
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_MPU_EDRn - Error Detail Register, slave port n
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_MPU_EDRn - Error Detail Register, slave port n (RO)
- *
- * Reset value: 0x00000000U
- *
- * When the MPU detects an access error on slave port n, 32 bits of error detail
- * are captured in this read-only register and the corresponding bit in
- * CESR[SPERR] is set. Information on the faulting address is captured in the
- * corresponding EARn register at the same time. This register and the corresponding EARn
- * register contain the most recent access error; there are no hardware interlocks
- * with CESR[SPERR] as the error registers are always loaded upon the occurrence
- * of each protection violation.
- */
-typedef union _hw_mpu_edrn
-{
- uint32_t U;
- struct _hw_mpu_edrn_bitfields
- {
- uint32_t ERW : 1; //!< [0] Error Read/Write
- uint32_t EATTR : 3; //!< [3:1] Error Attributes
- uint32_t EMN : 4; //!< [7:4] Error Master Number
- uint32_t EPID : 8; //!< [15:8] Error Process Identification
- uint32_t EACD : 16; //!< [31:16] Error Access Control Detail
- } B;
-} hw_mpu_edrn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire MPU_EDRn register
- */
-//@{
-#define HW_MPU_EDRn_COUNT (5U)
-
-#define HW_MPU_EDRn_ADDR(n) (REGS_MPU_BASE + 0x14U + (0x8U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_MPU_EDRn(n) (*(__I hw_mpu_edrn_t *) HW_MPU_EDRn_ADDR(n))
-#define HW_MPU_EDRn_RD(n) (HW_MPU_EDRn(n).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual MPU_EDRn bitfields
- */
-
-/*!
- * @name Register MPU_EDRn, field ERW[0] (RO)
- *
- * Indicates the access type of the faulting reference.
- *
- * Values:
- * - 0 - Read
- * - 1 - Write
- */
-//@{
-#define BP_MPU_EDRn_ERW (0U) //!< Bit position for MPU_EDRn_ERW.
-#define BM_MPU_EDRn_ERW (0x00000001U) //!< Bit mask for MPU_EDRn_ERW.
-#define BS_MPU_EDRn_ERW (1U) //!< Bit field size in bits for MPU_EDRn_ERW.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_EDRn_ERW field.
-#define BR_MPU_EDRn_ERW(n) (BITBAND_ACCESS32(HW_MPU_EDRn_ADDR(n), BP_MPU_EDRn_ERW))
-#endif
-//@}
-
-/*!
- * @name Register MPU_EDRn, field EATTR[3:1] (RO)
- *
- * Indicates attribute information about the faulting reference. All other
- * encodings are reserved.
- *
- * Values:
- * - 000 - User mode, instruction access
- * - 001 - User mode, data access
- * - 010 - Supervisor mode, instruction access
- * - 011 - Supervisor mode, data access
- */
-//@{
-#define BP_MPU_EDRn_EATTR (1U) //!< Bit position for MPU_EDRn_EATTR.
-#define BM_MPU_EDRn_EATTR (0x0000000EU) //!< Bit mask for MPU_EDRn_EATTR.
-#define BS_MPU_EDRn_EATTR (3U) //!< Bit field size in bits for MPU_EDRn_EATTR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_EDRn_EATTR field.
-#define BR_MPU_EDRn_EATTR(n) (HW_MPU_EDRn(n).B.EATTR)
-#endif
-//@}
-
-/*!
- * @name Register MPU_EDRn, field EMN[7:4] (RO)
- *
- * Indicates the bus master that generated the access error.
- */
-//@{
-#define BP_MPU_EDRn_EMN (4U) //!< Bit position for MPU_EDRn_EMN.
-#define BM_MPU_EDRn_EMN (0x000000F0U) //!< Bit mask for MPU_EDRn_EMN.
-#define BS_MPU_EDRn_EMN (4U) //!< Bit field size in bits for MPU_EDRn_EMN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_EDRn_EMN field.
-#define BR_MPU_EDRn_EMN(n) (HW_MPU_EDRn(n).B.EMN)
-#endif
-//@}
-
-/*!
- * @name Register MPU_EDRn, field EPID[15:8] (RO)
- *
- * Records the process identifier of the faulting reference. The process
- * identifier is typically driven only by processor cores; for other bus masters, this
- * field is cleared.
- */
-//@{
-#define BP_MPU_EDRn_EPID (8U) //!< Bit position for MPU_EDRn_EPID.
-#define BM_MPU_EDRn_EPID (0x0000FF00U) //!< Bit mask for MPU_EDRn_EPID.
-#define BS_MPU_EDRn_EPID (8U) //!< Bit field size in bits for MPU_EDRn_EPID.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_EDRn_EPID field.
-#define BR_MPU_EDRn_EPID(n) (HW_MPU_EDRn(n).B.EPID)
-#endif
-//@}
-
-/*!
- * @name Register MPU_EDRn, field EACD[31:16] (RO)
- *
- * Indicates the region descriptor with the access error. If EDRn contains a
- * captured error and EACD is cleared, an access did not hit in any region
- * descriptor. If only a single EACD bit is set, the protection error was caused by a
- * single non-overlapping region descriptor. If two or more EACD bits are set, the
- * protection error was caused by an overlapping set of region descriptors.
- */
-//@{
-#define BP_MPU_EDRn_EACD (16U) //!< Bit position for MPU_EDRn_EACD.
-#define BM_MPU_EDRn_EACD (0xFFFF0000U) //!< Bit mask for MPU_EDRn_EACD.
-#define BS_MPU_EDRn_EACD (16U) //!< Bit field size in bits for MPU_EDRn_EACD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_EDRn_EACD field.
-#define BR_MPU_EDRn_EACD(n) (HW_MPU_EDRn(n).B.EACD)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_MPU_RGDn_WORD0 - Region Descriptor n, Word 0
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_MPU_RGDn_WORD0 - Region Descriptor n, Word 0 (RW)
- *
- * Reset value: 0x00000000U
- *
- * The first word of the region descriptor defines the 0-modulo-32 byte start
- * address of the memory region. Writes to this register clear the region
- * descriptor's valid bit (RGDn_WORD3[VLD]).
- */
-typedef union _hw_mpu_rgdn_word0
-{
- uint32_t U;
- struct _hw_mpu_rgdn_word0_bitfields
- {
- uint32_t RESERVED0 : 5; //!< [4:0]
- uint32_t SRTADDR : 27; //!< [31:5] Start Address
- } B;
-} hw_mpu_rgdn_word0_t;
-#endif
-
-/*!
- * @name Constants and macros for entire MPU_RGDn_WORD0 register
- */
-//@{
-#define HW_MPU_RGDn_WORD0_COUNT (12U)
-
-#define HW_MPU_RGDn_WORD0_ADDR(n) (REGS_MPU_BASE + 0x400U + (0x10U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_MPU_RGDn_WORD0(n) (*(__IO hw_mpu_rgdn_word0_t *) HW_MPU_RGDn_WORD0_ADDR(n))
-#define HW_MPU_RGDn_WORD0_RD(n) (HW_MPU_RGDn_WORD0(n).U)
-#define HW_MPU_RGDn_WORD0_WR(n, v) (HW_MPU_RGDn_WORD0(n).U = (v))
-#define HW_MPU_RGDn_WORD0_SET(n, v) (HW_MPU_RGDn_WORD0_WR(n, HW_MPU_RGDn_WORD0_RD(n) | (v)))
-#define HW_MPU_RGDn_WORD0_CLR(n, v) (HW_MPU_RGDn_WORD0_WR(n, HW_MPU_RGDn_WORD0_RD(n) & ~(v)))
-#define HW_MPU_RGDn_WORD0_TOG(n, v) (HW_MPU_RGDn_WORD0_WR(n, HW_MPU_RGDn_WORD0_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual MPU_RGDn_WORD0 bitfields
- */
-
-/*!
- * @name Register MPU_RGDn_WORD0, field SRTADDR[31:5] (RW)
- *
- * Defines the most significant bits of the 0-modulo-32 byte start address of
- * the memory region.
- */
-//@{
-#define BP_MPU_RGDn_WORD0_SRTADDR (5U) //!< Bit position for MPU_RGDn_WORD0_SRTADDR.
-#define BM_MPU_RGDn_WORD0_SRTADDR (0xFFFFFFE0U) //!< Bit mask for MPU_RGDn_WORD0_SRTADDR.
-#define BS_MPU_RGDn_WORD0_SRTADDR (27U) //!< Bit field size in bits for MPU_RGDn_WORD0_SRTADDR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDn_WORD0_SRTADDR field.
-#define BR_MPU_RGDn_WORD0_SRTADDR(n) (HW_MPU_RGDn_WORD0(n).B.SRTADDR)
-#endif
-
-//! @brief Format value for bitfield MPU_RGDn_WORD0_SRTADDR.
-#define BF_MPU_RGDn_WORD0_SRTADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD0_SRTADDR), uint32_t) & BM_MPU_RGDn_WORD0_SRTADDR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SRTADDR field to a new value.
-#define BW_MPU_RGDn_WORD0_SRTADDR(n, v) (HW_MPU_RGDn_WORD0_WR(n, (HW_MPU_RGDn_WORD0_RD(n) & ~BM_MPU_RGDn_WORD0_SRTADDR) | BF_MPU_RGDn_WORD0_SRTADDR(v)))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_MPU_RGDn_WORD1 - Region Descriptor n, Word 1
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_MPU_RGDn_WORD1 - Region Descriptor n, Word 1 (RW)
- *
- * Reset value: 0xFFFFFFFFU
- *
- * The second word of the region descriptor defines the 31-modulo-32 byte end
- * address of the memory region. Writes to this register clear the region
- * descriptor's valid bit (RGDn_WORD3[VLD]).
- */
-typedef union _hw_mpu_rgdn_word1
-{
- uint32_t U;
- struct _hw_mpu_rgdn_word1_bitfields
- {
- uint32_t RESERVED0 : 5; //!< [4:0]
- uint32_t ENDADDR : 27; //!< [31:5] End Address
- } B;
-} hw_mpu_rgdn_word1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire MPU_RGDn_WORD1 register
- */
-//@{
-#define HW_MPU_RGDn_WORD1_COUNT (12U)
-
-#define HW_MPU_RGDn_WORD1_ADDR(n) (REGS_MPU_BASE + 0x404U + (0x10U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_MPU_RGDn_WORD1(n) (*(__IO hw_mpu_rgdn_word1_t *) HW_MPU_RGDn_WORD1_ADDR(n))
-#define HW_MPU_RGDn_WORD1_RD(n) (HW_MPU_RGDn_WORD1(n).U)
-#define HW_MPU_RGDn_WORD1_WR(n, v) (HW_MPU_RGDn_WORD1(n).U = (v))
-#define HW_MPU_RGDn_WORD1_SET(n, v) (HW_MPU_RGDn_WORD1_WR(n, HW_MPU_RGDn_WORD1_RD(n) | (v)))
-#define HW_MPU_RGDn_WORD1_CLR(n, v) (HW_MPU_RGDn_WORD1_WR(n, HW_MPU_RGDn_WORD1_RD(n) & ~(v)))
-#define HW_MPU_RGDn_WORD1_TOG(n, v) (HW_MPU_RGDn_WORD1_WR(n, HW_MPU_RGDn_WORD1_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual MPU_RGDn_WORD1 bitfields
- */
-
-/*!
- * @name Register MPU_RGDn_WORD1, field ENDADDR[31:5] (RW)
- *
- * Defines the most significant bits of the 31-modulo-32 byte end address of the
- * memory region. The MPU does not verify that ENDADDR >= SRTADDR.
- */
-//@{
-#define BP_MPU_RGDn_WORD1_ENDADDR (5U) //!< Bit position for MPU_RGDn_WORD1_ENDADDR.
-#define BM_MPU_RGDn_WORD1_ENDADDR (0xFFFFFFE0U) //!< Bit mask for MPU_RGDn_WORD1_ENDADDR.
-#define BS_MPU_RGDn_WORD1_ENDADDR (27U) //!< Bit field size in bits for MPU_RGDn_WORD1_ENDADDR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDn_WORD1_ENDADDR field.
-#define BR_MPU_RGDn_WORD1_ENDADDR(n) (HW_MPU_RGDn_WORD1(n).B.ENDADDR)
-#endif
-
-//! @brief Format value for bitfield MPU_RGDn_WORD1_ENDADDR.
-#define BF_MPU_RGDn_WORD1_ENDADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD1_ENDADDR), uint32_t) & BM_MPU_RGDn_WORD1_ENDADDR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ENDADDR field to a new value.
-#define BW_MPU_RGDn_WORD1_ENDADDR(n, v) (HW_MPU_RGDn_WORD1_WR(n, (HW_MPU_RGDn_WORD1_RD(n) & ~BM_MPU_RGDn_WORD1_ENDADDR) | BF_MPU_RGDn_WORD1_ENDADDR(v)))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_MPU_RGDn_WORD2 - Region Descriptor n, Word 2
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_MPU_RGDn_WORD2 - Region Descriptor n, Word 2 (RW)
- *
- * Reset value: 0x0061F7DFU
- *
- * The third word of the region descriptor defines the access control rights of
- * the memory region. The access control privileges depend on two broad
- * classifications of bus masters: Bus masters 0-3 have a 5-bit field defining separate
- * privilege rights for user and supervisor mode accesses, as well as the optional
- * inclusion of a process identification field within the definition. Bus masters
- * 4-7 are limited to separate read and write permissions. For the privilege
- * rights of bus masters 0-3, there are three flags associated with this function:
- * Read (r) refers to accessing the referenced memory address using an operand
- * (data) fetch Write (w) refers to updating the referenced memory address using a
- * store (data) instruction Execute (x) refers to reading the referenced memory
- * address using an instruction fetch Writes to RGDn_WORD2 clear the region
- * descriptor's valid bit (RGDn_WORD3[VLD]). If only updating the access controls, write
- * to RGDAACn instead because stores to these locations do not affect the
- * descriptor's valid bit.
- */
-typedef union _hw_mpu_rgdn_word2
-{
- uint32_t U;
- struct _hw_mpu_rgdn_word2_bitfields
- {
- uint32_t M0UM : 3; //!< [2:0] Bus Master 0 User Mode Access Control
- uint32_t M0SM : 2; //!< [4:3] Bus Master 0 Supervisor Mode Access
- //! Control
- uint32_t M0PE : 1; //!< [5] Bus Master 0 Process Identifier enable
- uint32_t M1UM : 3; //!< [8:6] Bus Master 1 User Mode Access Control
- uint32_t M1SM : 2; //!< [10:9] Bus Master 1 Supervisor Mode Access
- //! Control
- uint32_t M1PE : 1; //!< [11] Bus Master 1 Process Identifier enable
- uint32_t M2UM : 3; //!< [14:12] Bus Master 2 User Mode Access control
- uint32_t M2SM : 2; //!< [16:15] Bus Master 2 Supervisor Mode Access
- //! Control
- uint32_t M2PE : 1; //!< [17] Bus Master 2 Process Identifier Enable
- uint32_t M3UM : 3; //!< [20:18] Bus Master 3 User Mode Access Control
- uint32_t M3SM : 2; //!< [22:21] Bus Master 3 Supervisor Mode Access
- //! Control
- uint32_t M3PE : 1; //!< [23] Bus Master 3 Process Identifier Enable
- uint32_t M4WE : 1; //!< [24] Bus Master 4 Write Enable
- uint32_t M4RE : 1; //!< [25] Bus Master 4 Read Enable
- uint32_t M5WE : 1; //!< [26] Bus Master 5 Write Enable
- uint32_t M5RE : 1; //!< [27] Bus Master 5 Read Enable
- uint32_t M6WE : 1; //!< [28] Bus Master 6 Write Enable
- uint32_t M6RE : 1; //!< [29] Bus Master 6 Read Enable
- uint32_t M7WE : 1; //!< [30] Bus Master 7 Write Enable
- uint32_t M7RE : 1; //!< [31] Bus Master 7 Read Enable
- } B;
-} hw_mpu_rgdn_word2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire MPU_RGDn_WORD2 register
- */
-//@{
-#define HW_MPU_RGDn_WORD2_COUNT (12U)
-
-#define HW_MPU_RGDn_WORD2_ADDR(n) (REGS_MPU_BASE + 0x408U + (0x10U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_MPU_RGDn_WORD2(n) (*(__IO hw_mpu_rgdn_word2_t *) HW_MPU_RGDn_WORD2_ADDR(n))
-#define HW_MPU_RGDn_WORD2_RD(n) (HW_MPU_RGDn_WORD2(n).U)
-#define HW_MPU_RGDn_WORD2_WR(n, v) (HW_MPU_RGDn_WORD2(n).U = (v))
-#define HW_MPU_RGDn_WORD2_SET(n, v) (HW_MPU_RGDn_WORD2_WR(n, HW_MPU_RGDn_WORD2_RD(n) | (v)))
-#define HW_MPU_RGDn_WORD2_CLR(n, v) (HW_MPU_RGDn_WORD2_WR(n, HW_MPU_RGDn_WORD2_RD(n) & ~(v)))
-#define HW_MPU_RGDn_WORD2_TOG(n, v) (HW_MPU_RGDn_WORD2_WR(n, HW_MPU_RGDn_WORD2_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual MPU_RGDn_WORD2 bitfields
- */
-
-/*!
- * @name Register MPU_RGDn_WORD2, field M0UM[2:0] (RW)
- *
- * See M3UM description.
- */
-//@{
-#define BP_MPU_RGDn_WORD2_M0UM (0U) //!< Bit position for MPU_RGDn_WORD2_M0UM.
-#define BM_MPU_RGDn_WORD2_M0UM (0x00000007U) //!< Bit mask for MPU_RGDn_WORD2_M0UM.
-#define BS_MPU_RGDn_WORD2_M0UM (3U) //!< Bit field size in bits for MPU_RGDn_WORD2_M0UM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDn_WORD2_M0UM field.
-#define BR_MPU_RGDn_WORD2_M0UM(n) (HW_MPU_RGDn_WORD2(n).B.M0UM)
-#endif
-
-//! @brief Format value for bitfield MPU_RGDn_WORD2_M0UM.
-#define BF_MPU_RGDn_WORD2_M0UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M0UM), uint32_t) & BM_MPU_RGDn_WORD2_M0UM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M0UM field to a new value.
-#define BW_MPU_RGDn_WORD2_M0UM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M0UM) | BF_MPU_RGDn_WORD2_M0UM(v)))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDn_WORD2, field M0SM[4:3] (RW)
- *
- * See M3SM description.
- */
-//@{
-#define BP_MPU_RGDn_WORD2_M0SM (3U) //!< Bit position for MPU_RGDn_WORD2_M0SM.
-#define BM_MPU_RGDn_WORD2_M0SM (0x00000018U) //!< Bit mask for MPU_RGDn_WORD2_M0SM.
-#define BS_MPU_RGDn_WORD2_M0SM (2U) //!< Bit field size in bits for MPU_RGDn_WORD2_M0SM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDn_WORD2_M0SM field.
-#define BR_MPU_RGDn_WORD2_M0SM(n) (HW_MPU_RGDn_WORD2(n).B.M0SM)
-#endif
-
-//! @brief Format value for bitfield MPU_RGDn_WORD2_M0SM.
-#define BF_MPU_RGDn_WORD2_M0SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M0SM), uint32_t) & BM_MPU_RGDn_WORD2_M0SM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M0SM field to a new value.
-#define BW_MPU_RGDn_WORD2_M0SM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M0SM) | BF_MPU_RGDn_WORD2_M0SM(v)))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDn_WORD2, field M0PE[5] (RW)
- *
- * See M0PE description.
- */
-//@{
-#define BP_MPU_RGDn_WORD2_M0PE (5U) //!< Bit position for MPU_RGDn_WORD2_M0PE.
-#define BM_MPU_RGDn_WORD2_M0PE (0x00000020U) //!< Bit mask for MPU_RGDn_WORD2_M0PE.
-#define BS_MPU_RGDn_WORD2_M0PE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M0PE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDn_WORD2_M0PE field.
-#define BR_MPU_RGDn_WORD2_M0PE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M0PE))
-#endif
-
-//! @brief Format value for bitfield MPU_RGDn_WORD2_M0PE.
-#define BF_MPU_RGDn_WORD2_M0PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M0PE), uint32_t) & BM_MPU_RGDn_WORD2_M0PE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M0PE field to a new value.
-#define BW_MPU_RGDn_WORD2_M0PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M0PE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDn_WORD2, field M1UM[8:6] (RW)
- *
- * See M3UM description.
- */
-//@{
-#define BP_MPU_RGDn_WORD2_M1UM (6U) //!< Bit position for MPU_RGDn_WORD2_M1UM.
-#define BM_MPU_RGDn_WORD2_M1UM (0x000001C0U) //!< Bit mask for MPU_RGDn_WORD2_M1UM.
-#define BS_MPU_RGDn_WORD2_M1UM (3U) //!< Bit field size in bits for MPU_RGDn_WORD2_M1UM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDn_WORD2_M1UM field.
-#define BR_MPU_RGDn_WORD2_M1UM(n) (HW_MPU_RGDn_WORD2(n).B.M1UM)
-#endif
-
-//! @brief Format value for bitfield MPU_RGDn_WORD2_M1UM.
-#define BF_MPU_RGDn_WORD2_M1UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M1UM), uint32_t) & BM_MPU_RGDn_WORD2_M1UM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M1UM field to a new value.
-#define BW_MPU_RGDn_WORD2_M1UM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M1UM) | BF_MPU_RGDn_WORD2_M1UM(v)))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDn_WORD2, field M1SM[10:9] (RW)
- *
- * See M3SM description.
- */
-//@{
-#define BP_MPU_RGDn_WORD2_M1SM (9U) //!< Bit position for MPU_RGDn_WORD2_M1SM.
-#define BM_MPU_RGDn_WORD2_M1SM (0x00000600U) //!< Bit mask for MPU_RGDn_WORD2_M1SM.
-#define BS_MPU_RGDn_WORD2_M1SM (2U) //!< Bit field size in bits for MPU_RGDn_WORD2_M1SM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDn_WORD2_M1SM field.
-#define BR_MPU_RGDn_WORD2_M1SM(n) (HW_MPU_RGDn_WORD2(n).B.M1SM)
-#endif
-
-//! @brief Format value for bitfield MPU_RGDn_WORD2_M1SM.
-#define BF_MPU_RGDn_WORD2_M1SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M1SM), uint32_t) & BM_MPU_RGDn_WORD2_M1SM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M1SM field to a new value.
-#define BW_MPU_RGDn_WORD2_M1SM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M1SM) | BF_MPU_RGDn_WORD2_M1SM(v)))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDn_WORD2, field M1PE[11] (RW)
- *
- * See M3PE description.
- */
-//@{
-#define BP_MPU_RGDn_WORD2_M1PE (11U) //!< Bit position for MPU_RGDn_WORD2_M1PE.
-#define BM_MPU_RGDn_WORD2_M1PE (0x00000800U) //!< Bit mask for MPU_RGDn_WORD2_M1PE.
-#define BS_MPU_RGDn_WORD2_M1PE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M1PE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDn_WORD2_M1PE field.
-#define BR_MPU_RGDn_WORD2_M1PE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M1PE))
-#endif
-
-//! @brief Format value for bitfield MPU_RGDn_WORD2_M1PE.
-#define BF_MPU_RGDn_WORD2_M1PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M1PE), uint32_t) & BM_MPU_RGDn_WORD2_M1PE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M1PE field to a new value.
-#define BW_MPU_RGDn_WORD2_M1PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M1PE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDn_WORD2, field M2UM[14:12] (RW)
- *
- * See M3UM description.
- */
-//@{
-#define BP_MPU_RGDn_WORD2_M2UM (12U) //!< Bit position for MPU_RGDn_WORD2_M2UM.
-#define BM_MPU_RGDn_WORD2_M2UM (0x00007000U) //!< Bit mask for MPU_RGDn_WORD2_M2UM.
-#define BS_MPU_RGDn_WORD2_M2UM (3U) //!< Bit field size in bits for MPU_RGDn_WORD2_M2UM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDn_WORD2_M2UM field.
-#define BR_MPU_RGDn_WORD2_M2UM(n) (HW_MPU_RGDn_WORD2(n).B.M2UM)
-#endif
-
-//! @brief Format value for bitfield MPU_RGDn_WORD2_M2UM.
-#define BF_MPU_RGDn_WORD2_M2UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M2UM), uint32_t) & BM_MPU_RGDn_WORD2_M2UM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M2UM field to a new value.
-#define BW_MPU_RGDn_WORD2_M2UM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M2UM) | BF_MPU_RGDn_WORD2_M2UM(v)))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDn_WORD2, field M2SM[16:15] (RW)
- *
- * See M3SM description.
- */
-//@{
-#define BP_MPU_RGDn_WORD2_M2SM (15U) //!< Bit position for MPU_RGDn_WORD2_M2SM.
-#define BM_MPU_RGDn_WORD2_M2SM (0x00018000U) //!< Bit mask for MPU_RGDn_WORD2_M2SM.
-#define BS_MPU_RGDn_WORD2_M2SM (2U) //!< Bit field size in bits for MPU_RGDn_WORD2_M2SM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDn_WORD2_M2SM field.
-#define BR_MPU_RGDn_WORD2_M2SM(n) (HW_MPU_RGDn_WORD2(n).B.M2SM)
-#endif
-
-//! @brief Format value for bitfield MPU_RGDn_WORD2_M2SM.
-#define BF_MPU_RGDn_WORD2_M2SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M2SM), uint32_t) & BM_MPU_RGDn_WORD2_M2SM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M2SM field to a new value.
-#define BW_MPU_RGDn_WORD2_M2SM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M2SM) | BF_MPU_RGDn_WORD2_M2SM(v)))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDn_WORD2, field M2PE[17] (RW)
- *
- * See M3PE description.
- */
-//@{
-#define BP_MPU_RGDn_WORD2_M2PE (17U) //!< Bit position for MPU_RGDn_WORD2_M2PE.
-#define BM_MPU_RGDn_WORD2_M2PE (0x00020000U) //!< Bit mask for MPU_RGDn_WORD2_M2PE.
-#define BS_MPU_RGDn_WORD2_M2PE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M2PE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDn_WORD2_M2PE field.
-#define BR_MPU_RGDn_WORD2_M2PE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M2PE))
-#endif
-
-//! @brief Format value for bitfield MPU_RGDn_WORD2_M2PE.
-#define BF_MPU_RGDn_WORD2_M2PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M2PE), uint32_t) & BM_MPU_RGDn_WORD2_M2PE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M2PE field to a new value.
-#define BW_MPU_RGDn_WORD2_M2PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M2PE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDn_WORD2, field M3UM[20:18] (RW)
- *
- * Defines the access controls for bus master 3 in User mode. M3UM consists of
- * three independent bits, enabling read (r), write (w), and execute (x)
- * permissions.
- *
- * Values:
- * - 0 - An attempted access of that mode may be terminated with an access error
- * (if not allowed by another descriptor) and the access not performed.
- * - 1 - Allows the given access type to occur
- */
-//@{
-#define BP_MPU_RGDn_WORD2_M3UM (18U) //!< Bit position for MPU_RGDn_WORD2_M3UM.
-#define BM_MPU_RGDn_WORD2_M3UM (0x001C0000U) //!< Bit mask for MPU_RGDn_WORD2_M3UM.
-#define BS_MPU_RGDn_WORD2_M3UM (3U) //!< Bit field size in bits for MPU_RGDn_WORD2_M3UM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDn_WORD2_M3UM field.
-#define BR_MPU_RGDn_WORD2_M3UM(n) (HW_MPU_RGDn_WORD2(n).B.M3UM)
-#endif
-
-//! @brief Format value for bitfield MPU_RGDn_WORD2_M3UM.
-#define BF_MPU_RGDn_WORD2_M3UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M3UM), uint32_t) & BM_MPU_RGDn_WORD2_M3UM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M3UM field to a new value.
-#define BW_MPU_RGDn_WORD2_M3UM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M3UM) | BF_MPU_RGDn_WORD2_M3UM(v)))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDn_WORD2, field M3SM[22:21] (RW)
- *
- * Defines the access controls for bus master 3 in Supervisor mode.
- *
- * Values:
- * - 00 - r/w/x; read, write and execute allowed
- * - 01 - r/x; read and execute allowed, but no write
- * - 10 - r/w; read and write allowed, but no execute
- * - 11 - Same as User mode defined in M3UM
- */
-//@{
-#define BP_MPU_RGDn_WORD2_M3SM (21U) //!< Bit position for MPU_RGDn_WORD2_M3SM.
-#define BM_MPU_RGDn_WORD2_M3SM (0x00600000U) //!< Bit mask for MPU_RGDn_WORD2_M3SM.
-#define BS_MPU_RGDn_WORD2_M3SM (2U) //!< Bit field size in bits for MPU_RGDn_WORD2_M3SM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDn_WORD2_M3SM field.
-#define BR_MPU_RGDn_WORD2_M3SM(n) (HW_MPU_RGDn_WORD2(n).B.M3SM)
-#endif
-
-//! @brief Format value for bitfield MPU_RGDn_WORD2_M3SM.
-#define BF_MPU_RGDn_WORD2_M3SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M3SM), uint32_t) & BM_MPU_RGDn_WORD2_M3SM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M3SM field to a new value.
-#define BW_MPU_RGDn_WORD2_M3SM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M3SM) | BF_MPU_RGDn_WORD2_M3SM(v)))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDn_WORD2, field M3PE[23] (RW)
- *
- * Values:
- * - 0 - Do not include the process identifier in the evaluation
- * - 1 - Include the process identifier and mask (RGDn_WORD3) in the region hit
- * evaluation
- */
-//@{
-#define BP_MPU_RGDn_WORD2_M3PE (23U) //!< Bit position for MPU_RGDn_WORD2_M3PE.
-#define BM_MPU_RGDn_WORD2_M3PE (0x00800000U) //!< Bit mask for MPU_RGDn_WORD2_M3PE.
-#define BS_MPU_RGDn_WORD2_M3PE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M3PE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDn_WORD2_M3PE field.
-#define BR_MPU_RGDn_WORD2_M3PE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M3PE))
-#endif
-
-//! @brief Format value for bitfield MPU_RGDn_WORD2_M3PE.
-#define BF_MPU_RGDn_WORD2_M3PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M3PE), uint32_t) & BM_MPU_RGDn_WORD2_M3PE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M3PE field to a new value.
-#define BW_MPU_RGDn_WORD2_M3PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M3PE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDn_WORD2, field M4WE[24] (RW)
- *
- * Values:
- * - 0 - Bus master 4 writes terminate with an access error and the write is not
- * performed
- * - 1 - Bus master 4 writes allowed
- */
-//@{
-#define BP_MPU_RGDn_WORD2_M4WE (24U) //!< Bit position for MPU_RGDn_WORD2_M4WE.
-#define BM_MPU_RGDn_WORD2_M4WE (0x01000000U) //!< Bit mask for MPU_RGDn_WORD2_M4WE.
-#define BS_MPU_RGDn_WORD2_M4WE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M4WE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDn_WORD2_M4WE field.
-#define BR_MPU_RGDn_WORD2_M4WE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M4WE))
-#endif
-
-//! @brief Format value for bitfield MPU_RGDn_WORD2_M4WE.
-#define BF_MPU_RGDn_WORD2_M4WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M4WE), uint32_t) & BM_MPU_RGDn_WORD2_M4WE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M4WE field to a new value.
-#define BW_MPU_RGDn_WORD2_M4WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M4WE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDn_WORD2, field M4RE[25] (RW)
- *
- * Values:
- * - 0 - Bus master 4 reads terminate with an access error and the read is not
- * performed
- * - 1 - Bus master 4 reads allowed
- */
-//@{
-#define BP_MPU_RGDn_WORD2_M4RE (25U) //!< Bit position for MPU_RGDn_WORD2_M4RE.
-#define BM_MPU_RGDn_WORD2_M4RE (0x02000000U) //!< Bit mask for MPU_RGDn_WORD2_M4RE.
-#define BS_MPU_RGDn_WORD2_M4RE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M4RE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDn_WORD2_M4RE field.
-#define BR_MPU_RGDn_WORD2_M4RE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M4RE))
-#endif
-
-//! @brief Format value for bitfield MPU_RGDn_WORD2_M4RE.
-#define BF_MPU_RGDn_WORD2_M4RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M4RE), uint32_t) & BM_MPU_RGDn_WORD2_M4RE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M4RE field to a new value.
-#define BW_MPU_RGDn_WORD2_M4RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M4RE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDn_WORD2, field M5WE[26] (RW)
- *
- * Values:
- * - 0 - Bus master 5 writes terminate with an access error and the write is not
- * performed
- * - 1 - Bus master 5 writes allowed
- */
-//@{
-#define BP_MPU_RGDn_WORD2_M5WE (26U) //!< Bit position for MPU_RGDn_WORD2_M5WE.
-#define BM_MPU_RGDn_WORD2_M5WE (0x04000000U) //!< Bit mask for MPU_RGDn_WORD2_M5WE.
-#define BS_MPU_RGDn_WORD2_M5WE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M5WE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDn_WORD2_M5WE field.
-#define BR_MPU_RGDn_WORD2_M5WE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M5WE))
-#endif
-
-//! @brief Format value for bitfield MPU_RGDn_WORD2_M5WE.
-#define BF_MPU_RGDn_WORD2_M5WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M5WE), uint32_t) & BM_MPU_RGDn_WORD2_M5WE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M5WE field to a new value.
-#define BW_MPU_RGDn_WORD2_M5WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M5WE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDn_WORD2, field M5RE[27] (RW)
- *
- * Values:
- * - 0 - Bus master 5 reads terminate with an access error and the read is not
- * performed
- * - 1 - Bus master 5 reads allowed
- */
-//@{
-#define BP_MPU_RGDn_WORD2_M5RE (27U) //!< Bit position for MPU_RGDn_WORD2_M5RE.
-#define BM_MPU_RGDn_WORD2_M5RE (0x08000000U) //!< Bit mask for MPU_RGDn_WORD2_M5RE.
-#define BS_MPU_RGDn_WORD2_M5RE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M5RE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDn_WORD2_M5RE field.
-#define BR_MPU_RGDn_WORD2_M5RE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M5RE))
-#endif
-
-//! @brief Format value for bitfield MPU_RGDn_WORD2_M5RE.
-#define BF_MPU_RGDn_WORD2_M5RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M5RE), uint32_t) & BM_MPU_RGDn_WORD2_M5RE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M5RE field to a new value.
-#define BW_MPU_RGDn_WORD2_M5RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M5RE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDn_WORD2, field M6WE[28] (RW)
- *
- * Values:
- * - 0 - Bus master 6 writes terminate with an access error and the write is not
- * performed
- * - 1 - Bus master 6 writes allowed
- */
-//@{
-#define BP_MPU_RGDn_WORD2_M6WE (28U) //!< Bit position for MPU_RGDn_WORD2_M6WE.
-#define BM_MPU_RGDn_WORD2_M6WE (0x10000000U) //!< Bit mask for MPU_RGDn_WORD2_M6WE.
-#define BS_MPU_RGDn_WORD2_M6WE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M6WE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDn_WORD2_M6WE field.
-#define BR_MPU_RGDn_WORD2_M6WE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M6WE))
-#endif
-
-//! @brief Format value for bitfield MPU_RGDn_WORD2_M6WE.
-#define BF_MPU_RGDn_WORD2_M6WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M6WE), uint32_t) & BM_MPU_RGDn_WORD2_M6WE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M6WE field to a new value.
-#define BW_MPU_RGDn_WORD2_M6WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M6WE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDn_WORD2, field M6RE[29] (RW)
- *
- * Values:
- * - 0 - Bus master 6 reads terminate with an access error and the read is not
- * performed
- * - 1 - Bus master 6 reads allowed
- */
-//@{
-#define BP_MPU_RGDn_WORD2_M6RE (29U) //!< Bit position for MPU_RGDn_WORD2_M6RE.
-#define BM_MPU_RGDn_WORD2_M6RE (0x20000000U) //!< Bit mask for MPU_RGDn_WORD2_M6RE.
-#define BS_MPU_RGDn_WORD2_M6RE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M6RE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDn_WORD2_M6RE field.
-#define BR_MPU_RGDn_WORD2_M6RE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M6RE))
-#endif
-
-//! @brief Format value for bitfield MPU_RGDn_WORD2_M6RE.
-#define BF_MPU_RGDn_WORD2_M6RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M6RE), uint32_t) & BM_MPU_RGDn_WORD2_M6RE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M6RE field to a new value.
-#define BW_MPU_RGDn_WORD2_M6RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M6RE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDn_WORD2, field M7WE[30] (RW)
- *
- * Values:
- * - 0 - Bus master 7 writes terminate with an access error and the write is not
- * performed
- * - 1 - Bus master 7 writes allowed
- */
-//@{
-#define BP_MPU_RGDn_WORD2_M7WE (30U) //!< Bit position for MPU_RGDn_WORD2_M7WE.
-#define BM_MPU_RGDn_WORD2_M7WE (0x40000000U) //!< Bit mask for MPU_RGDn_WORD2_M7WE.
-#define BS_MPU_RGDn_WORD2_M7WE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M7WE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDn_WORD2_M7WE field.
-#define BR_MPU_RGDn_WORD2_M7WE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M7WE))
-#endif
-
-//! @brief Format value for bitfield MPU_RGDn_WORD2_M7WE.
-#define BF_MPU_RGDn_WORD2_M7WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M7WE), uint32_t) & BM_MPU_RGDn_WORD2_M7WE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M7WE field to a new value.
-#define BW_MPU_RGDn_WORD2_M7WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M7WE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDn_WORD2, field M7RE[31] (RW)
- *
- * Values:
- * - 0 - Bus master 7 reads terminate with an access error and the read is not
- * performed
- * - 1 - Bus master 7 reads allowed
- */
-//@{
-#define BP_MPU_RGDn_WORD2_M7RE (31U) //!< Bit position for MPU_RGDn_WORD2_M7RE.
-#define BM_MPU_RGDn_WORD2_M7RE (0x80000000U) //!< Bit mask for MPU_RGDn_WORD2_M7RE.
-#define BS_MPU_RGDn_WORD2_M7RE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M7RE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDn_WORD2_M7RE field.
-#define BR_MPU_RGDn_WORD2_M7RE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M7RE))
-#endif
-
-//! @brief Format value for bitfield MPU_RGDn_WORD2_M7RE.
-#define BF_MPU_RGDn_WORD2_M7RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M7RE), uint32_t) & BM_MPU_RGDn_WORD2_M7RE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M7RE field to a new value.
-#define BW_MPU_RGDn_WORD2_M7RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M7RE) = (v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_MPU_RGDn_WORD3 - Region Descriptor n, Word 3
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_MPU_RGDn_WORD3 - Region Descriptor n, Word 3 (RW)
- *
- * Reset value: 0x00000001U
- *
- * The fourth word of the region descriptor contains the optional process
- * identifier and mask, plus the region descriptor's valid bit.
- */
-typedef union _hw_mpu_rgdn_word3
-{
- uint32_t U;
- struct _hw_mpu_rgdn_word3_bitfields
- {
- uint32_t VLD : 1; //!< [0] Valid
- uint32_t RESERVED0 : 15; //!< [15:1]
- uint32_t PIDMASK : 8; //!< [23:16] Process Identifier Mask
- uint32_t PID : 8; //!< [31:24] Process Identifier
- } B;
-} hw_mpu_rgdn_word3_t;
-#endif
-
-/*!
- * @name Constants and macros for entire MPU_RGDn_WORD3 register
- */
-//@{
-#define HW_MPU_RGDn_WORD3_COUNT (12U)
-
-#define HW_MPU_RGDn_WORD3_ADDR(n) (REGS_MPU_BASE + 0x40CU + (0x10U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_MPU_RGDn_WORD3(n) (*(__IO hw_mpu_rgdn_word3_t *) HW_MPU_RGDn_WORD3_ADDR(n))
-#define HW_MPU_RGDn_WORD3_RD(n) (HW_MPU_RGDn_WORD3(n).U)
-#define HW_MPU_RGDn_WORD3_WR(n, v) (HW_MPU_RGDn_WORD3(n).U = (v))
-#define HW_MPU_RGDn_WORD3_SET(n, v) (HW_MPU_RGDn_WORD3_WR(n, HW_MPU_RGDn_WORD3_RD(n) | (v)))
-#define HW_MPU_RGDn_WORD3_CLR(n, v) (HW_MPU_RGDn_WORD3_WR(n, HW_MPU_RGDn_WORD3_RD(n) & ~(v)))
-#define HW_MPU_RGDn_WORD3_TOG(n, v) (HW_MPU_RGDn_WORD3_WR(n, HW_MPU_RGDn_WORD3_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual MPU_RGDn_WORD3 bitfields
- */
-
-/*!
- * @name Register MPU_RGDn_WORD3, field VLD[0] (RW)
- *
- * Signals the region descriptor is valid. Any write to RGDn_WORD0-2 clears this
- * bit.
- *
- * Values:
- * - 0 - Region descriptor is invalid
- * - 1 - Region descriptor is valid
- */
-//@{
-#define BP_MPU_RGDn_WORD3_VLD (0U) //!< Bit position for MPU_RGDn_WORD3_VLD.
-#define BM_MPU_RGDn_WORD3_VLD (0x00000001U) //!< Bit mask for MPU_RGDn_WORD3_VLD.
-#define BS_MPU_RGDn_WORD3_VLD (1U) //!< Bit field size in bits for MPU_RGDn_WORD3_VLD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDn_WORD3_VLD field.
-#define BR_MPU_RGDn_WORD3_VLD(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD3_ADDR(n), BP_MPU_RGDn_WORD3_VLD))
-#endif
-
-//! @brief Format value for bitfield MPU_RGDn_WORD3_VLD.
-#define BF_MPU_RGDn_WORD3_VLD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD3_VLD), uint32_t) & BM_MPU_RGDn_WORD3_VLD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the VLD field to a new value.
-#define BW_MPU_RGDn_WORD3_VLD(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD3_ADDR(n), BP_MPU_RGDn_WORD3_VLD) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDn_WORD3, field PIDMASK[23:16] (RW)
- *
- * Provides a masking capability so that multiple process identifiers can be
- * included as part of the region hit determination. If a bit in PIDMASK is set,
- * then the corresponding PID bit is ignored in the comparison. This field and PID
- * are included in the region hit determination if RGDn_WORD2[MxPE] is set. For
- * more information on the handling of the PID and PIDMASK, see "Access Evaluation
- * - Hit Determination."
- */
-//@{
-#define BP_MPU_RGDn_WORD3_PIDMASK (16U) //!< Bit position for MPU_RGDn_WORD3_PIDMASK.
-#define BM_MPU_RGDn_WORD3_PIDMASK (0x00FF0000U) //!< Bit mask for MPU_RGDn_WORD3_PIDMASK.
-#define BS_MPU_RGDn_WORD3_PIDMASK (8U) //!< Bit field size in bits for MPU_RGDn_WORD3_PIDMASK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDn_WORD3_PIDMASK field.
-#define BR_MPU_RGDn_WORD3_PIDMASK(n) (HW_MPU_RGDn_WORD3(n).B.PIDMASK)
-#endif
-
-//! @brief Format value for bitfield MPU_RGDn_WORD3_PIDMASK.
-#define BF_MPU_RGDn_WORD3_PIDMASK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD3_PIDMASK), uint32_t) & BM_MPU_RGDn_WORD3_PIDMASK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PIDMASK field to a new value.
-#define BW_MPU_RGDn_WORD3_PIDMASK(n, v) (HW_MPU_RGDn_WORD3_WR(n, (HW_MPU_RGDn_WORD3_RD(n) & ~BM_MPU_RGDn_WORD3_PIDMASK) | BF_MPU_RGDn_WORD3_PIDMASK(v)))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDn_WORD3, field PID[31:24] (RW)
- *
- * Specifies the process identifier that is included in the region hit
- * determination if RGDn_WORD2[MxPE] is set. PIDMASK can mask individual bits in this
- * field.
- */
-//@{
-#define BP_MPU_RGDn_WORD3_PID (24U) //!< Bit position for MPU_RGDn_WORD3_PID.
-#define BM_MPU_RGDn_WORD3_PID (0xFF000000U) //!< Bit mask for MPU_RGDn_WORD3_PID.
-#define BS_MPU_RGDn_WORD3_PID (8U) //!< Bit field size in bits for MPU_RGDn_WORD3_PID.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDn_WORD3_PID field.
-#define BR_MPU_RGDn_WORD3_PID(n) (HW_MPU_RGDn_WORD3(n).B.PID)
-#endif
-
-//! @brief Format value for bitfield MPU_RGDn_WORD3_PID.
-#define BF_MPU_RGDn_WORD3_PID(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD3_PID), uint32_t) & BM_MPU_RGDn_WORD3_PID)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PID field to a new value.
-#define BW_MPU_RGDn_WORD3_PID(n, v) (HW_MPU_RGDn_WORD3_WR(n, (HW_MPU_RGDn_WORD3_RD(n) & ~BM_MPU_RGDn_WORD3_PID) | BF_MPU_RGDn_WORD3_PID(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_MPU_RGDAACn - Region Descriptor Alternate Access Control n
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_MPU_RGDAACn - Region Descriptor Alternate Access Control n (RW)
- *
- * Reset value: 0x0061F7DFU
- *
- * Because software may adjust only the access controls within a region
- * descriptor (RGDn_WORD2) as different tasks execute, an alternate programming view of
- * this 32-bit entity is available. Writing to this register does not affect the
- * descriptor's valid bit.
- */
-typedef union _hw_mpu_rgdaacn
-{
- uint32_t U;
- struct _hw_mpu_rgdaacn_bitfields
- {
- uint32_t M0UM : 3; //!< [2:0] Bus Master 0 User Mode Access Control
- uint32_t M0SM : 2; //!< [4:3] Bus Master 0 Supervisor Mode Access
- //! Control
- uint32_t M0PE : 1; //!< [5] Bus Master 0 Process Identifier Enable
- uint32_t M1UM : 3; //!< [8:6] Bus Master 1 User Mode Access Control
- uint32_t M1SM : 2; //!< [10:9] Bus Master 1 Supervisor Mode Access
- //! Control
- uint32_t M1PE : 1; //!< [11] Bus Master 1 Process Identifier Enable
- uint32_t M2UM : 3; //!< [14:12] Bus Master 2 User Mode Access Control
- uint32_t M2SM : 2; //!< [16:15] Bus Master 2 Supervisor Mode Access
- //! Control
- uint32_t M2PE : 1; //!< [17] Bus Master 2 Process Identifier Enable
- uint32_t M3UM : 3; //!< [20:18] Bus Master 3 User Mode Access Control
- uint32_t M3SM : 2; //!< [22:21] Bus Master 3 Supervisor Mode Access
- //! Control
- uint32_t M3PE : 1; //!< [23] Bus Master 3 Process Identifier Enable
- uint32_t M4WE : 1; //!< [24] Bus Master 4 Write Enable
- uint32_t M4RE : 1; //!< [25] Bus Master 4 Read Enable
- uint32_t M5WE : 1; //!< [26] Bus Master 5 Write Enable
- uint32_t M5RE : 1; //!< [27] Bus Master 5 Read Enable
- uint32_t M6WE : 1; //!< [28] Bus Master 6 Write Enable
- uint32_t M6RE : 1; //!< [29] Bus Master 6 Read Enable
- uint32_t M7WE : 1; //!< [30] Bus Master 7 Write Enable
- uint32_t M7RE : 1; //!< [31] Bus Master 7 Read Enable
- } B;
-} hw_mpu_rgdaacn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire MPU_RGDAACn register
- */
-//@{
-#define HW_MPU_RGDAACn_COUNT (12U)
-
-#define HW_MPU_RGDAACn_ADDR(n) (REGS_MPU_BASE + 0x800U + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_MPU_RGDAACn(n) (*(__IO hw_mpu_rgdaacn_t *) HW_MPU_RGDAACn_ADDR(n))
-#define HW_MPU_RGDAACn_RD(n) (HW_MPU_RGDAACn(n).U)
-#define HW_MPU_RGDAACn_WR(n, v) (HW_MPU_RGDAACn(n).U = (v))
-#define HW_MPU_RGDAACn_SET(n, v) (HW_MPU_RGDAACn_WR(n, HW_MPU_RGDAACn_RD(n) | (v)))
-#define HW_MPU_RGDAACn_CLR(n, v) (HW_MPU_RGDAACn_WR(n, HW_MPU_RGDAACn_RD(n) & ~(v)))
-#define HW_MPU_RGDAACn_TOG(n, v) (HW_MPU_RGDAACn_WR(n, HW_MPU_RGDAACn_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual MPU_RGDAACn bitfields
- */
-
-/*!
- * @name Register MPU_RGDAACn, field M0UM[2:0] (RW)
- *
- * See M3UM description.
- */
-//@{
-#define BP_MPU_RGDAACn_M0UM (0U) //!< Bit position for MPU_RGDAACn_M0UM.
-#define BM_MPU_RGDAACn_M0UM (0x00000007U) //!< Bit mask for MPU_RGDAACn_M0UM.
-#define BS_MPU_RGDAACn_M0UM (3U) //!< Bit field size in bits for MPU_RGDAACn_M0UM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDAACn_M0UM field.
-#define BR_MPU_RGDAACn_M0UM(n) (HW_MPU_RGDAACn(n).B.M0UM)
-#endif
-
-//! @brief Format value for bitfield MPU_RGDAACn_M0UM.
-#define BF_MPU_RGDAACn_M0UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M0UM), uint32_t) & BM_MPU_RGDAACn_M0UM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M0UM field to a new value.
-#define BW_MPU_RGDAACn_M0UM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M0UM) | BF_MPU_RGDAACn_M0UM(v)))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDAACn, field M0SM[4:3] (RW)
- *
- * See M3SM description.
- */
-//@{
-#define BP_MPU_RGDAACn_M0SM (3U) //!< Bit position for MPU_RGDAACn_M0SM.
-#define BM_MPU_RGDAACn_M0SM (0x00000018U) //!< Bit mask for MPU_RGDAACn_M0SM.
-#define BS_MPU_RGDAACn_M0SM (2U) //!< Bit field size in bits for MPU_RGDAACn_M0SM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDAACn_M0SM field.
-#define BR_MPU_RGDAACn_M0SM(n) (HW_MPU_RGDAACn(n).B.M0SM)
-#endif
-
-//! @brief Format value for bitfield MPU_RGDAACn_M0SM.
-#define BF_MPU_RGDAACn_M0SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M0SM), uint32_t) & BM_MPU_RGDAACn_M0SM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M0SM field to a new value.
-#define BW_MPU_RGDAACn_M0SM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M0SM) | BF_MPU_RGDAACn_M0SM(v)))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDAACn, field M0PE[5] (RW)
- *
- * See M3PE description.
- */
-//@{
-#define BP_MPU_RGDAACn_M0PE (5U) //!< Bit position for MPU_RGDAACn_M0PE.
-#define BM_MPU_RGDAACn_M0PE (0x00000020U) //!< Bit mask for MPU_RGDAACn_M0PE.
-#define BS_MPU_RGDAACn_M0PE (1U) //!< Bit field size in bits for MPU_RGDAACn_M0PE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDAACn_M0PE field.
-#define BR_MPU_RGDAACn_M0PE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M0PE))
-#endif
-
-//! @brief Format value for bitfield MPU_RGDAACn_M0PE.
-#define BF_MPU_RGDAACn_M0PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M0PE), uint32_t) & BM_MPU_RGDAACn_M0PE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M0PE field to a new value.
-#define BW_MPU_RGDAACn_M0PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M0PE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDAACn, field M1UM[8:6] (RW)
- *
- * See M3UM description.
- */
-//@{
-#define BP_MPU_RGDAACn_M1UM (6U) //!< Bit position for MPU_RGDAACn_M1UM.
-#define BM_MPU_RGDAACn_M1UM (0x000001C0U) //!< Bit mask for MPU_RGDAACn_M1UM.
-#define BS_MPU_RGDAACn_M1UM (3U) //!< Bit field size in bits for MPU_RGDAACn_M1UM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDAACn_M1UM field.
-#define BR_MPU_RGDAACn_M1UM(n) (HW_MPU_RGDAACn(n).B.M1UM)
-#endif
-
-//! @brief Format value for bitfield MPU_RGDAACn_M1UM.
-#define BF_MPU_RGDAACn_M1UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M1UM), uint32_t) & BM_MPU_RGDAACn_M1UM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M1UM field to a new value.
-#define BW_MPU_RGDAACn_M1UM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M1UM) | BF_MPU_RGDAACn_M1UM(v)))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDAACn, field M1SM[10:9] (RW)
- *
- * See M3SM description.
- */
-//@{
-#define BP_MPU_RGDAACn_M1SM (9U) //!< Bit position for MPU_RGDAACn_M1SM.
-#define BM_MPU_RGDAACn_M1SM (0x00000600U) //!< Bit mask for MPU_RGDAACn_M1SM.
-#define BS_MPU_RGDAACn_M1SM (2U) //!< Bit field size in bits for MPU_RGDAACn_M1SM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDAACn_M1SM field.
-#define BR_MPU_RGDAACn_M1SM(n) (HW_MPU_RGDAACn(n).B.M1SM)
-#endif
-
-//! @brief Format value for bitfield MPU_RGDAACn_M1SM.
-#define BF_MPU_RGDAACn_M1SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M1SM), uint32_t) & BM_MPU_RGDAACn_M1SM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M1SM field to a new value.
-#define BW_MPU_RGDAACn_M1SM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M1SM) | BF_MPU_RGDAACn_M1SM(v)))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDAACn, field M1PE[11] (RW)
- *
- * See M3PE description.
- */
-//@{
-#define BP_MPU_RGDAACn_M1PE (11U) //!< Bit position for MPU_RGDAACn_M1PE.
-#define BM_MPU_RGDAACn_M1PE (0x00000800U) //!< Bit mask for MPU_RGDAACn_M1PE.
-#define BS_MPU_RGDAACn_M1PE (1U) //!< Bit field size in bits for MPU_RGDAACn_M1PE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDAACn_M1PE field.
-#define BR_MPU_RGDAACn_M1PE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M1PE))
-#endif
-
-//! @brief Format value for bitfield MPU_RGDAACn_M1PE.
-#define BF_MPU_RGDAACn_M1PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M1PE), uint32_t) & BM_MPU_RGDAACn_M1PE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M1PE field to a new value.
-#define BW_MPU_RGDAACn_M1PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M1PE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDAACn, field M2UM[14:12] (RW)
- *
- * See M3UM description.
- */
-//@{
-#define BP_MPU_RGDAACn_M2UM (12U) //!< Bit position for MPU_RGDAACn_M2UM.
-#define BM_MPU_RGDAACn_M2UM (0x00007000U) //!< Bit mask for MPU_RGDAACn_M2UM.
-#define BS_MPU_RGDAACn_M2UM (3U) //!< Bit field size in bits for MPU_RGDAACn_M2UM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDAACn_M2UM field.
-#define BR_MPU_RGDAACn_M2UM(n) (HW_MPU_RGDAACn(n).B.M2UM)
-#endif
-
-//! @brief Format value for bitfield MPU_RGDAACn_M2UM.
-#define BF_MPU_RGDAACn_M2UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M2UM), uint32_t) & BM_MPU_RGDAACn_M2UM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M2UM field to a new value.
-#define BW_MPU_RGDAACn_M2UM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M2UM) | BF_MPU_RGDAACn_M2UM(v)))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDAACn, field M2SM[16:15] (RW)
- *
- * See M3SM description.
- */
-//@{
-#define BP_MPU_RGDAACn_M2SM (15U) //!< Bit position for MPU_RGDAACn_M2SM.
-#define BM_MPU_RGDAACn_M2SM (0x00018000U) //!< Bit mask for MPU_RGDAACn_M2SM.
-#define BS_MPU_RGDAACn_M2SM (2U) //!< Bit field size in bits for MPU_RGDAACn_M2SM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDAACn_M2SM field.
-#define BR_MPU_RGDAACn_M2SM(n) (HW_MPU_RGDAACn(n).B.M2SM)
-#endif
-
-//! @brief Format value for bitfield MPU_RGDAACn_M2SM.
-#define BF_MPU_RGDAACn_M2SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M2SM), uint32_t) & BM_MPU_RGDAACn_M2SM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M2SM field to a new value.
-#define BW_MPU_RGDAACn_M2SM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M2SM) | BF_MPU_RGDAACn_M2SM(v)))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDAACn, field M2PE[17] (RW)
- *
- * See M3PE description.
- */
-//@{
-#define BP_MPU_RGDAACn_M2PE (17U) //!< Bit position for MPU_RGDAACn_M2PE.
-#define BM_MPU_RGDAACn_M2PE (0x00020000U) //!< Bit mask for MPU_RGDAACn_M2PE.
-#define BS_MPU_RGDAACn_M2PE (1U) //!< Bit field size in bits for MPU_RGDAACn_M2PE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDAACn_M2PE field.
-#define BR_MPU_RGDAACn_M2PE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M2PE))
-#endif
-
-//! @brief Format value for bitfield MPU_RGDAACn_M2PE.
-#define BF_MPU_RGDAACn_M2PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M2PE), uint32_t) & BM_MPU_RGDAACn_M2PE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M2PE field to a new value.
-#define BW_MPU_RGDAACn_M2PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M2PE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDAACn, field M3UM[20:18] (RW)
- *
- * Defines the access controls for bus master 3 in user mode. M3UM consists of
- * three independent bits, enabling read (r), write (w), and execute (x)
- * permissions.
- *
- * Values:
- * - 0 - An attempted access of that mode may be terminated with an access error
- * (if not allowed by another descriptor) and the access not performed.
- * - 1 - Allows the given access type to occur
- */
-//@{
-#define BP_MPU_RGDAACn_M3UM (18U) //!< Bit position for MPU_RGDAACn_M3UM.
-#define BM_MPU_RGDAACn_M3UM (0x001C0000U) //!< Bit mask for MPU_RGDAACn_M3UM.
-#define BS_MPU_RGDAACn_M3UM (3U) //!< Bit field size in bits for MPU_RGDAACn_M3UM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDAACn_M3UM field.
-#define BR_MPU_RGDAACn_M3UM(n) (HW_MPU_RGDAACn(n).B.M3UM)
-#endif
-
-//! @brief Format value for bitfield MPU_RGDAACn_M3UM.
-#define BF_MPU_RGDAACn_M3UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M3UM), uint32_t) & BM_MPU_RGDAACn_M3UM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M3UM field to a new value.
-#define BW_MPU_RGDAACn_M3UM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M3UM) | BF_MPU_RGDAACn_M3UM(v)))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDAACn, field M3SM[22:21] (RW)
- *
- * Defines the access controls for bus master 3 in Supervisor mode.
- *
- * Values:
- * - 00 - r/w/x; read, write and execute allowed
- * - 01 - r/x; read and execute allowed, but no write
- * - 10 - r/w; read and write allowed, but no execute
- * - 11 - Same as User mode defined in M3UM
- */
-//@{
-#define BP_MPU_RGDAACn_M3SM (21U) //!< Bit position for MPU_RGDAACn_M3SM.
-#define BM_MPU_RGDAACn_M3SM (0x00600000U) //!< Bit mask for MPU_RGDAACn_M3SM.
-#define BS_MPU_RGDAACn_M3SM (2U) //!< Bit field size in bits for MPU_RGDAACn_M3SM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDAACn_M3SM field.
-#define BR_MPU_RGDAACn_M3SM(n) (HW_MPU_RGDAACn(n).B.M3SM)
-#endif
-
-//! @brief Format value for bitfield MPU_RGDAACn_M3SM.
-#define BF_MPU_RGDAACn_M3SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M3SM), uint32_t) & BM_MPU_RGDAACn_M3SM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M3SM field to a new value.
-#define BW_MPU_RGDAACn_M3SM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M3SM) | BF_MPU_RGDAACn_M3SM(v)))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDAACn, field M3PE[23] (RW)
- *
- * Values:
- * - 0 - Do not include the process identifier in the evaluation
- * - 1 - Include the process identifier and mask (RGDn.RGDAAC) in the region hit
- * evaluation
- */
-//@{
-#define BP_MPU_RGDAACn_M3PE (23U) //!< Bit position for MPU_RGDAACn_M3PE.
-#define BM_MPU_RGDAACn_M3PE (0x00800000U) //!< Bit mask for MPU_RGDAACn_M3PE.
-#define BS_MPU_RGDAACn_M3PE (1U) //!< Bit field size in bits for MPU_RGDAACn_M3PE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDAACn_M3PE field.
-#define BR_MPU_RGDAACn_M3PE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M3PE))
-#endif
-
-//! @brief Format value for bitfield MPU_RGDAACn_M3PE.
-#define BF_MPU_RGDAACn_M3PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M3PE), uint32_t) & BM_MPU_RGDAACn_M3PE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M3PE field to a new value.
-#define BW_MPU_RGDAACn_M3PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M3PE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDAACn, field M4WE[24] (RW)
- *
- * Values:
- * - 0 - Bus master 4 writes terminate with an access error and the write is not
- * performed
- * - 1 - Bus master 4 writes allowed
- */
-//@{
-#define BP_MPU_RGDAACn_M4WE (24U) //!< Bit position for MPU_RGDAACn_M4WE.
-#define BM_MPU_RGDAACn_M4WE (0x01000000U) //!< Bit mask for MPU_RGDAACn_M4WE.
-#define BS_MPU_RGDAACn_M4WE (1U) //!< Bit field size in bits for MPU_RGDAACn_M4WE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDAACn_M4WE field.
-#define BR_MPU_RGDAACn_M4WE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M4WE))
-#endif
-
-//! @brief Format value for bitfield MPU_RGDAACn_M4WE.
-#define BF_MPU_RGDAACn_M4WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M4WE), uint32_t) & BM_MPU_RGDAACn_M4WE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M4WE field to a new value.
-#define BW_MPU_RGDAACn_M4WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M4WE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDAACn, field M4RE[25] (RW)
- *
- * Values:
- * - 0 - Bus master 4 reads terminate with an access error and the read is not
- * performed
- * - 1 - Bus master 4 reads allowed
- */
-//@{
-#define BP_MPU_RGDAACn_M4RE (25U) //!< Bit position for MPU_RGDAACn_M4RE.
-#define BM_MPU_RGDAACn_M4RE (0x02000000U) //!< Bit mask for MPU_RGDAACn_M4RE.
-#define BS_MPU_RGDAACn_M4RE (1U) //!< Bit field size in bits for MPU_RGDAACn_M4RE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDAACn_M4RE field.
-#define BR_MPU_RGDAACn_M4RE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M4RE))
-#endif
-
-//! @brief Format value for bitfield MPU_RGDAACn_M4RE.
-#define BF_MPU_RGDAACn_M4RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M4RE), uint32_t) & BM_MPU_RGDAACn_M4RE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M4RE field to a new value.
-#define BW_MPU_RGDAACn_M4RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M4RE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDAACn, field M5WE[26] (RW)
- *
- * Values:
- * - 0 - Bus master 5 writes terminate with an access error and the write is not
- * performed
- * - 1 - Bus master 5 writes allowed
- */
-//@{
-#define BP_MPU_RGDAACn_M5WE (26U) //!< Bit position for MPU_RGDAACn_M5WE.
-#define BM_MPU_RGDAACn_M5WE (0x04000000U) //!< Bit mask for MPU_RGDAACn_M5WE.
-#define BS_MPU_RGDAACn_M5WE (1U) //!< Bit field size in bits for MPU_RGDAACn_M5WE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDAACn_M5WE field.
-#define BR_MPU_RGDAACn_M5WE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M5WE))
-#endif
-
-//! @brief Format value for bitfield MPU_RGDAACn_M5WE.
-#define BF_MPU_RGDAACn_M5WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M5WE), uint32_t) & BM_MPU_RGDAACn_M5WE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M5WE field to a new value.
-#define BW_MPU_RGDAACn_M5WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M5WE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDAACn, field M5RE[27] (RW)
- *
- * Values:
- * - 0 - Bus master 5 reads terminate with an access error and the read is not
- * performed
- * - 1 - Bus master 5 reads allowed
- */
-//@{
-#define BP_MPU_RGDAACn_M5RE (27U) //!< Bit position for MPU_RGDAACn_M5RE.
-#define BM_MPU_RGDAACn_M5RE (0x08000000U) //!< Bit mask for MPU_RGDAACn_M5RE.
-#define BS_MPU_RGDAACn_M5RE (1U) //!< Bit field size in bits for MPU_RGDAACn_M5RE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDAACn_M5RE field.
-#define BR_MPU_RGDAACn_M5RE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M5RE))
-#endif
-
-//! @brief Format value for bitfield MPU_RGDAACn_M5RE.
-#define BF_MPU_RGDAACn_M5RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M5RE), uint32_t) & BM_MPU_RGDAACn_M5RE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M5RE field to a new value.
-#define BW_MPU_RGDAACn_M5RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M5RE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDAACn, field M6WE[28] (RW)
- *
- * Values:
- * - 0 - Bus master 6 writes terminate with an access error and the write is not
- * performed
- * - 1 - Bus master 6 writes allowed
- */
-//@{
-#define BP_MPU_RGDAACn_M6WE (28U) //!< Bit position for MPU_RGDAACn_M6WE.
-#define BM_MPU_RGDAACn_M6WE (0x10000000U) //!< Bit mask for MPU_RGDAACn_M6WE.
-#define BS_MPU_RGDAACn_M6WE (1U) //!< Bit field size in bits for MPU_RGDAACn_M6WE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDAACn_M6WE field.
-#define BR_MPU_RGDAACn_M6WE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M6WE))
-#endif
-
-//! @brief Format value for bitfield MPU_RGDAACn_M6WE.
-#define BF_MPU_RGDAACn_M6WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M6WE), uint32_t) & BM_MPU_RGDAACn_M6WE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M6WE field to a new value.
-#define BW_MPU_RGDAACn_M6WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M6WE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDAACn, field M6RE[29] (RW)
- *
- * Values:
- * - 0 - Bus master 6 reads terminate with an access error and the read is not
- * performed
- * - 1 - Bus master 6 reads allowed
- */
-//@{
-#define BP_MPU_RGDAACn_M6RE (29U) //!< Bit position for MPU_RGDAACn_M6RE.
-#define BM_MPU_RGDAACn_M6RE (0x20000000U) //!< Bit mask for MPU_RGDAACn_M6RE.
-#define BS_MPU_RGDAACn_M6RE (1U) //!< Bit field size in bits for MPU_RGDAACn_M6RE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDAACn_M6RE field.
-#define BR_MPU_RGDAACn_M6RE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M6RE))
-#endif
-
-//! @brief Format value for bitfield MPU_RGDAACn_M6RE.
-#define BF_MPU_RGDAACn_M6RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M6RE), uint32_t) & BM_MPU_RGDAACn_M6RE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M6RE field to a new value.
-#define BW_MPU_RGDAACn_M6RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M6RE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDAACn, field M7WE[30] (RW)
- *
- * Values:
- * - 0 - Bus master 7 writes terminate with an access error and the write is not
- * performed
- * - 1 - Bus master 7 writes allowed
- */
-//@{
-#define BP_MPU_RGDAACn_M7WE (30U) //!< Bit position for MPU_RGDAACn_M7WE.
-#define BM_MPU_RGDAACn_M7WE (0x40000000U) //!< Bit mask for MPU_RGDAACn_M7WE.
-#define BS_MPU_RGDAACn_M7WE (1U) //!< Bit field size in bits for MPU_RGDAACn_M7WE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDAACn_M7WE field.
-#define BR_MPU_RGDAACn_M7WE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M7WE))
-#endif
-
-//! @brief Format value for bitfield MPU_RGDAACn_M7WE.
-#define BF_MPU_RGDAACn_M7WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M7WE), uint32_t) & BM_MPU_RGDAACn_M7WE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M7WE field to a new value.
-#define BW_MPU_RGDAACn_M7WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M7WE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register MPU_RGDAACn, field M7RE[31] (RW)
- *
- * Values:
- * - 0 - Bus master 7 reads terminate with an access error and the read is not
- * performed
- * - 1 - Bus master 7 reads allowed
- */
-//@{
-#define BP_MPU_RGDAACn_M7RE (31U) //!< Bit position for MPU_RGDAACn_M7RE.
-#define BM_MPU_RGDAACn_M7RE (0x80000000U) //!< Bit mask for MPU_RGDAACn_M7RE.
-#define BS_MPU_RGDAACn_M7RE (1U) //!< Bit field size in bits for MPU_RGDAACn_M7RE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the MPU_RGDAACn_M7RE field.
-#define BR_MPU_RGDAACn_M7RE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M7RE))
-#endif
-
-//! @brief Format value for bitfield MPU_RGDAACn_M7RE.
-#define BF_MPU_RGDAACn_M7RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M7RE), uint32_t) & BM_MPU_RGDAACn_M7RE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M7RE field to a new value.
-#define BW_MPU_RGDAACn_M7RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M7RE) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_mpu_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All MPU module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_mpu
-{
- __IO hw_mpu_cesr_t CESR; //!< [0x0] Control/Error Status Register
- uint8_t _reserved0[12];
- struct {
- __I hw_mpu_earn_t EARn; //!< [0x10] Error Address Register, slave port n
- __I hw_mpu_edrn_t EDRn; //!< [0x14] Error Detail Register, slave port n
- } SP[5];
- uint8_t _reserved1[968];
- struct {
- __IO hw_mpu_rgdn_word0_t RGDn_WORD0; //!< [0x400] Region Descriptor n, Word 0
- __IO hw_mpu_rgdn_word1_t RGDn_WORD1; //!< [0x404] Region Descriptor n, Word 1
- __IO hw_mpu_rgdn_word2_t RGDn_WORD2; //!< [0x408] Region Descriptor n, Word 2
- __IO hw_mpu_rgdn_word3_t RGDn_WORD3; //!< [0x40C] Region Descriptor n, Word 3
- } RGD[12];
- uint8_t _reserved2[832];
- __IO hw_mpu_rgdaacn_t RGDAACn[12]; //!< [0x800] Region Descriptor Alternate Access Control n
-} hw_mpu_t;
-#pragma pack()
-
-//! @brief Macro to access all MPU registers.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_MPU</code>.
-#define HW_MPU (*(hw_mpu_t *) REGS_MPU_BASE)
-#endif
-
-#endif // __HW_MPU_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_nv.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,958 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_NV_REGISTERS_H__
-#define __HW_NV_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 NV
- *
- * Flash configuration field
- *
- * Registers defined in this header file:
- * - HW_NV_BACKKEY3 - Backdoor Comparison Key 3.
- * - HW_NV_BACKKEY2 - Backdoor Comparison Key 2.
- * - HW_NV_BACKKEY1 - Backdoor Comparison Key 1.
- * - HW_NV_BACKKEY0 - Backdoor Comparison Key 0.
- * - HW_NV_BACKKEY7 - Backdoor Comparison Key 7.
- * - HW_NV_BACKKEY6 - Backdoor Comparison Key 6.
- * - HW_NV_BACKKEY5 - Backdoor Comparison Key 5.
- * - HW_NV_BACKKEY4 - Backdoor Comparison Key 4.
- * - HW_NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register
- * - HW_NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register
- * - HW_NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register
- * - HW_NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register
- * - HW_NV_FSEC - Non-volatile Flash Security Register
- * - HW_NV_FOPT - Non-volatile Flash Option Register
- * - HW_NV_FEPROT - Non-volatile EERAM Protection Register
- * - HW_NV_FDPROT - Non-volatile D-Flash Protection Register
- *
- * - hw_nv_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_NV_BASE
-#define HW_NV_INSTANCE_COUNT (1U) //!< Number of instances of the NV module.
-#define REGS_NV_BASE (0x400U) //!< Base address for FTFE_FlashConfig.
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_NV_BACKKEY3 - Backdoor Comparison Key 3.
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_NV_BACKKEY3 - Backdoor Comparison Key 3. (RO)
- *
- * Reset value: 0xFFU
- */
-typedef union _hw_nv_backkey3
-{
- uint8_t U;
- struct _hw_nv_backkey3_bitfields
- {
- uint8_t KEY : 8; //!< [7:0] Backdoor Comparison Key.
- } B;
-} hw_nv_backkey3_t;
-#endif
-
-/*!
- * @name Constants and macros for entire NV_BACKKEY3 register
- */
-//@{
-#define HW_NV_BACKKEY3_ADDR (REGS_NV_BASE + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_NV_BACKKEY3 (*(__I hw_nv_backkey3_t *) HW_NV_BACKKEY3_ADDR)
-#define HW_NV_BACKKEY3_RD() (HW_NV_BACKKEY3.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual NV_BACKKEY3 bitfields
- */
-
-/*!
- * @name Register NV_BACKKEY3, field KEY[7:0] (RO)
- */
-//@{
-#define BP_NV_BACKKEY3_KEY (0U) //!< Bit position for NV_BACKKEY3_KEY.
-#define BM_NV_BACKKEY3_KEY (0xFFU) //!< Bit mask for NV_BACKKEY3_KEY.
-#define BS_NV_BACKKEY3_KEY (8U) //!< Bit field size in bits for NV_BACKKEY3_KEY.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the NV_BACKKEY3_KEY field.
-#define BR_NV_BACKKEY3_KEY (HW_NV_BACKKEY3.U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_NV_BACKKEY2 - Backdoor Comparison Key 2.
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_NV_BACKKEY2 - Backdoor Comparison Key 2. (RO)
- *
- * Reset value: 0xFFU
- */
-typedef union _hw_nv_backkey2
-{
- uint8_t U;
- struct _hw_nv_backkey2_bitfields
- {
- uint8_t KEY : 8; //!< [7:0] Backdoor Comparison Key.
- } B;
-} hw_nv_backkey2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire NV_BACKKEY2 register
- */
-//@{
-#define HW_NV_BACKKEY2_ADDR (REGS_NV_BASE + 0x1U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_NV_BACKKEY2 (*(__I hw_nv_backkey2_t *) HW_NV_BACKKEY2_ADDR)
-#define HW_NV_BACKKEY2_RD() (HW_NV_BACKKEY2.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual NV_BACKKEY2 bitfields
- */
-
-/*!
- * @name Register NV_BACKKEY2, field KEY[7:0] (RO)
- */
-//@{
-#define BP_NV_BACKKEY2_KEY (0U) //!< Bit position for NV_BACKKEY2_KEY.
-#define BM_NV_BACKKEY2_KEY (0xFFU) //!< Bit mask for NV_BACKKEY2_KEY.
-#define BS_NV_BACKKEY2_KEY (8U) //!< Bit field size in bits for NV_BACKKEY2_KEY.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the NV_BACKKEY2_KEY field.
-#define BR_NV_BACKKEY2_KEY (HW_NV_BACKKEY2.U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_NV_BACKKEY1 - Backdoor Comparison Key 1.
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_NV_BACKKEY1 - Backdoor Comparison Key 1. (RO)
- *
- * Reset value: 0xFFU
- */
-typedef union _hw_nv_backkey1
-{
- uint8_t U;
- struct _hw_nv_backkey1_bitfields
- {
- uint8_t KEY : 8; //!< [7:0] Backdoor Comparison Key.
- } B;
-} hw_nv_backkey1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire NV_BACKKEY1 register
- */
-//@{
-#define HW_NV_BACKKEY1_ADDR (REGS_NV_BASE + 0x2U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_NV_BACKKEY1 (*(__I hw_nv_backkey1_t *) HW_NV_BACKKEY1_ADDR)
-#define HW_NV_BACKKEY1_RD() (HW_NV_BACKKEY1.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual NV_BACKKEY1 bitfields
- */
-
-/*!
- * @name Register NV_BACKKEY1, field KEY[7:0] (RO)
- */
-//@{
-#define BP_NV_BACKKEY1_KEY (0U) //!< Bit position for NV_BACKKEY1_KEY.
-#define BM_NV_BACKKEY1_KEY (0xFFU) //!< Bit mask for NV_BACKKEY1_KEY.
-#define BS_NV_BACKKEY1_KEY (8U) //!< Bit field size in bits for NV_BACKKEY1_KEY.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the NV_BACKKEY1_KEY field.
-#define BR_NV_BACKKEY1_KEY (HW_NV_BACKKEY1.U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_NV_BACKKEY0 - Backdoor Comparison Key 0.
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_NV_BACKKEY0 - Backdoor Comparison Key 0. (RO)
- *
- * Reset value: 0xFFU
- */
-typedef union _hw_nv_backkey0
-{
- uint8_t U;
- struct _hw_nv_backkey0_bitfields
- {
- uint8_t KEY : 8; //!< [7:0] Backdoor Comparison Key.
- } B;
-} hw_nv_backkey0_t;
-#endif
-
-/*!
- * @name Constants and macros for entire NV_BACKKEY0 register
- */
-//@{
-#define HW_NV_BACKKEY0_ADDR (REGS_NV_BASE + 0x3U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_NV_BACKKEY0 (*(__I hw_nv_backkey0_t *) HW_NV_BACKKEY0_ADDR)
-#define HW_NV_BACKKEY0_RD() (HW_NV_BACKKEY0.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual NV_BACKKEY0 bitfields
- */
-
-/*!
- * @name Register NV_BACKKEY0, field KEY[7:0] (RO)
- */
-//@{
-#define BP_NV_BACKKEY0_KEY (0U) //!< Bit position for NV_BACKKEY0_KEY.
-#define BM_NV_BACKKEY0_KEY (0xFFU) //!< Bit mask for NV_BACKKEY0_KEY.
-#define BS_NV_BACKKEY0_KEY (8U) //!< Bit field size in bits for NV_BACKKEY0_KEY.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the NV_BACKKEY0_KEY field.
-#define BR_NV_BACKKEY0_KEY (HW_NV_BACKKEY0.U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_NV_BACKKEY7 - Backdoor Comparison Key 7.
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_NV_BACKKEY7 - Backdoor Comparison Key 7. (RO)
- *
- * Reset value: 0xFFU
- */
-typedef union _hw_nv_backkey7
-{
- uint8_t U;
- struct _hw_nv_backkey7_bitfields
- {
- uint8_t KEY : 8; //!< [7:0] Backdoor Comparison Key.
- } B;
-} hw_nv_backkey7_t;
-#endif
-
-/*!
- * @name Constants and macros for entire NV_BACKKEY7 register
- */
-//@{
-#define HW_NV_BACKKEY7_ADDR (REGS_NV_BASE + 0x4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_NV_BACKKEY7 (*(__I hw_nv_backkey7_t *) HW_NV_BACKKEY7_ADDR)
-#define HW_NV_BACKKEY7_RD() (HW_NV_BACKKEY7.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual NV_BACKKEY7 bitfields
- */
-
-/*!
- * @name Register NV_BACKKEY7, field KEY[7:0] (RO)
- */
-//@{
-#define BP_NV_BACKKEY7_KEY (0U) //!< Bit position for NV_BACKKEY7_KEY.
-#define BM_NV_BACKKEY7_KEY (0xFFU) //!< Bit mask for NV_BACKKEY7_KEY.
-#define BS_NV_BACKKEY7_KEY (8U) //!< Bit field size in bits for NV_BACKKEY7_KEY.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the NV_BACKKEY7_KEY field.
-#define BR_NV_BACKKEY7_KEY (HW_NV_BACKKEY7.U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_NV_BACKKEY6 - Backdoor Comparison Key 6.
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_NV_BACKKEY6 - Backdoor Comparison Key 6. (RO)
- *
- * Reset value: 0xFFU
- */
-typedef union _hw_nv_backkey6
-{
- uint8_t U;
- struct _hw_nv_backkey6_bitfields
- {
- uint8_t KEY : 8; //!< [7:0] Backdoor Comparison Key.
- } B;
-} hw_nv_backkey6_t;
-#endif
-
-/*!
- * @name Constants and macros for entire NV_BACKKEY6 register
- */
-//@{
-#define HW_NV_BACKKEY6_ADDR (REGS_NV_BASE + 0x5U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_NV_BACKKEY6 (*(__I hw_nv_backkey6_t *) HW_NV_BACKKEY6_ADDR)
-#define HW_NV_BACKKEY6_RD() (HW_NV_BACKKEY6.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual NV_BACKKEY6 bitfields
- */
-
-/*!
- * @name Register NV_BACKKEY6, field KEY[7:0] (RO)
- */
-//@{
-#define BP_NV_BACKKEY6_KEY (0U) //!< Bit position for NV_BACKKEY6_KEY.
-#define BM_NV_BACKKEY6_KEY (0xFFU) //!< Bit mask for NV_BACKKEY6_KEY.
-#define BS_NV_BACKKEY6_KEY (8U) //!< Bit field size in bits for NV_BACKKEY6_KEY.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the NV_BACKKEY6_KEY field.
-#define BR_NV_BACKKEY6_KEY (HW_NV_BACKKEY6.U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_NV_BACKKEY5 - Backdoor Comparison Key 5.
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_NV_BACKKEY5 - Backdoor Comparison Key 5. (RO)
- *
- * Reset value: 0xFFU
- */
-typedef union _hw_nv_backkey5
-{
- uint8_t U;
- struct _hw_nv_backkey5_bitfields
- {
- uint8_t KEY : 8; //!< [7:0] Backdoor Comparison Key.
- } B;
-} hw_nv_backkey5_t;
-#endif
-
-/*!
- * @name Constants and macros for entire NV_BACKKEY5 register
- */
-//@{
-#define HW_NV_BACKKEY5_ADDR (REGS_NV_BASE + 0x6U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_NV_BACKKEY5 (*(__I hw_nv_backkey5_t *) HW_NV_BACKKEY5_ADDR)
-#define HW_NV_BACKKEY5_RD() (HW_NV_BACKKEY5.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual NV_BACKKEY5 bitfields
- */
-
-/*!
- * @name Register NV_BACKKEY5, field KEY[7:0] (RO)
- */
-//@{
-#define BP_NV_BACKKEY5_KEY (0U) //!< Bit position for NV_BACKKEY5_KEY.
-#define BM_NV_BACKKEY5_KEY (0xFFU) //!< Bit mask for NV_BACKKEY5_KEY.
-#define BS_NV_BACKKEY5_KEY (8U) //!< Bit field size in bits for NV_BACKKEY5_KEY.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the NV_BACKKEY5_KEY field.
-#define BR_NV_BACKKEY5_KEY (HW_NV_BACKKEY5.U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_NV_BACKKEY4 - Backdoor Comparison Key 4.
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_NV_BACKKEY4 - Backdoor Comparison Key 4. (RO)
- *
- * Reset value: 0xFFU
- */
-typedef union _hw_nv_backkey4
-{
- uint8_t U;
- struct _hw_nv_backkey4_bitfields
- {
- uint8_t KEY : 8; //!< [7:0] Backdoor Comparison Key.
- } B;
-} hw_nv_backkey4_t;
-#endif
-
-/*!
- * @name Constants and macros for entire NV_BACKKEY4 register
- */
-//@{
-#define HW_NV_BACKKEY4_ADDR (REGS_NV_BASE + 0x7U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_NV_BACKKEY4 (*(__I hw_nv_backkey4_t *) HW_NV_BACKKEY4_ADDR)
-#define HW_NV_BACKKEY4_RD() (HW_NV_BACKKEY4.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual NV_BACKKEY4 bitfields
- */
-
-/*!
- * @name Register NV_BACKKEY4, field KEY[7:0] (RO)
- */
-//@{
-#define BP_NV_BACKKEY4_KEY (0U) //!< Bit position for NV_BACKKEY4_KEY.
-#define BM_NV_BACKKEY4_KEY (0xFFU) //!< Bit mask for NV_BACKKEY4_KEY.
-#define BS_NV_BACKKEY4_KEY (8U) //!< Bit field size in bits for NV_BACKKEY4_KEY.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the NV_BACKKEY4_KEY field.
-#define BR_NV_BACKKEY4_KEY (HW_NV_BACKKEY4.U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register (RO)
- *
- * Reset value: 0xFFU
- */
-typedef union _hw_nv_fprot3
-{
- uint8_t U;
- struct _hw_nv_fprot3_bitfields
- {
- uint8_t PROT : 8; //!< [7:0] P-Flash Region Protect
- } B;
-} hw_nv_fprot3_t;
-#endif
-
-/*!
- * @name Constants and macros for entire NV_FPROT3 register
- */
-//@{
-#define HW_NV_FPROT3_ADDR (REGS_NV_BASE + 0x8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_NV_FPROT3 (*(__I hw_nv_fprot3_t *) HW_NV_FPROT3_ADDR)
-#define HW_NV_FPROT3_RD() (HW_NV_FPROT3.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual NV_FPROT3 bitfields
- */
-
-/*!
- * @name Register NV_FPROT3, field PROT[7:0] (RO)
- */
-//@{
-#define BP_NV_FPROT3_PROT (0U) //!< Bit position for NV_FPROT3_PROT.
-#define BM_NV_FPROT3_PROT (0xFFU) //!< Bit mask for NV_FPROT3_PROT.
-#define BS_NV_FPROT3_PROT (8U) //!< Bit field size in bits for NV_FPROT3_PROT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the NV_FPROT3_PROT field.
-#define BR_NV_FPROT3_PROT (HW_NV_FPROT3.U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register (RO)
- *
- * Reset value: 0xFFU
- */
-typedef union _hw_nv_fprot2
-{
- uint8_t U;
- struct _hw_nv_fprot2_bitfields
- {
- uint8_t PROT : 8; //!< [7:0] P-Flash Region Protect
- } B;
-} hw_nv_fprot2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire NV_FPROT2 register
- */
-//@{
-#define HW_NV_FPROT2_ADDR (REGS_NV_BASE + 0x9U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_NV_FPROT2 (*(__I hw_nv_fprot2_t *) HW_NV_FPROT2_ADDR)
-#define HW_NV_FPROT2_RD() (HW_NV_FPROT2.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual NV_FPROT2 bitfields
- */
-
-/*!
- * @name Register NV_FPROT2, field PROT[7:0] (RO)
- */
-//@{
-#define BP_NV_FPROT2_PROT (0U) //!< Bit position for NV_FPROT2_PROT.
-#define BM_NV_FPROT2_PROT (0xFFU) //!< Bit mask for NV_FPROT2_PROT.
-#define BS_NV_FPROT2_PROT (8U) //!< Bit field size in bits for NV_FPROT2_PROT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the NV_FPROT2_PROT field.
-#define BR_NV_FPROT2_PROT (HW_NV_FPROT2.U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register (RO)
- *
- * Reset value: 0xFFU
- */
-typedef union _hw_nv_fprot1
-{
- uint8_t U;
- struct _hw_nv_fprot1_bitfields
- {
- uint8_t PROT : 8; //!< [7:0] P-Flash Region Protect
- } B;
-} hw_nv_fprot1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire NV_FPROT1 register
- */
-//@{
-#define HW_NV_FPROT1_ADDR (REGS_NV_BASE + 0xAU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_NV_FPROT1 (*(__I hw_nv_fprot1_t *) HW_NV_FPROT1_ADDR)
-#define HW_NV_FPROT1_RD() (HW_NV_FPROT1.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual NV_FPROT1 bitfields
- */
-
-/*!
- * @name Register NV_FPROT1, field PROT[7:0] (RO)
- */
-//@{
-#define BP_NV_FPROT1_PROT (0U) //!< Bit position for NV_FPROT1_PROT.
-#define BM_NV_FPROT1_PROT (0xFFU) //!< Bit mask for NV_FPROT1_PROT.
-#define BS_NV_FPROT1_PROT (8U) //!< Bit field size in bits for NV_FPROT1_PROT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the NV_FPROT1_PROT field.
-#define BR_NV_FPROT1_PROT (HW_NV_FPROT1.U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register (RO)
- *
- * Reset value: 0xFFU
- */
-typedef union _hw_nv_fprot0
-{
- uint8_t U;
- struct _hw_nv_fprot0_bitfields
- {
- uint8_t PROT : 8; //!< [7:0] P-Flash Region Protect
- } B;
-} hw_nv_fprot0_t;
-#endif
-
-/*!
- * @name Constants and macros for entire NV_FPROT0 register
- */
-//@{
-#define HW_NV_FPROT0_ADDR (REGS_NV_BASE + 0xBU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_NV_FPROT0 (*(__I hw_nv_fprot0_t *) HW_NV_FPROT0_ADDR)
-#define HW_NV_FPROT0_RD() (HW_NV_FPROT0.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual NV_FPROT0 bitfields
- */
-
-/*!
- * @name Register NV_FPROT0, field PROT[7:0] (RO)
- */
-//@{
-#define BP_NV_FPROT0_PROT (0U) //!< Bit position for NV_FPROT0_PROT.
-#define BM_NV_FPROT0_PROT (0xFFU) //!< Bit mask for NV_FPROT0_PROT.
-#define BS_NV_FPROT0_PROT (8U) //!< Bit field size in bits for NV_FPROT0_PROT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the NV_FPROT0_PROT field.
-#define BR_NV_FPROT0_PROT (HW_NV_FPROT0.U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_NV_FSEC - Non-volatile Flash Security Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_NV_FSEC - Non-volatile Flash Security Register (RO)
- *
- * Reset value: 0xFFU
- */
-typedef union _hw_nv_fsec
-{
- uint8_t U;
- struct _hw_nv_fsec_bitfields
- {
- uint8_t SEC : 2; //!< [1:0] Flash Security
- uint8_t FSLACC : 2; //!< [3:2] Freescale Failure Analysis Access Code
- uint8_t MEEN : 2; //!< [5:4]
- uint8_t KEYEN : 2; //!< [7:6] Backdoor Key Security Enable
- } B;
-} hw_nv_fsec_t;
-#endif
-
-/*!
- * @name Constants and macros for entire NV_FSEC register
- */
-//@{
-#define HW_NV_FSEC_ADDR (REGS_NV_BASE + 0xCU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_NV_FSEC (*(__I hw_nv_fsec_t *) HW_NV_FSEC_ADDR)
-#define HW_NV_FSEC_RD() (HW_NV_FSEC.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual NV_FSEC bitfields
- */
-
-/*!
- * @name Register NV_FSEC, field SEC[1:0] (RO)
- */
-//@{
-#define BP_NV_FSEC_SEC (0U) //!< Bit position for NV_FSEC_SEC.
-#define BM_NV_FSEC_SEC (0x03U) //!< Bit mask for NV_FSEC_SEC.
-#define BS_NV_FSEC_SEC (2U) //!< Bit field size in bits for NV_FSEC_SEC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the NV_FSEC_SEC field.
-#define BR_NV_FSEC_SEC (HW_NV_FSEC.B.SEC)
-#endif
-//@}
-
-/*!
- * @name Register NV_FSEC, field FSLACC[3:2] (RO)
- */
-//@{
-#define BP_NV_FSEC_FSLACC (2U) //!< Bit position for NV_FSEC_FSLACC.
-#define BM_NV_FSEC_FSLACC (0x0CU) //!< Bit mask for NV_FSEC_FSLACC.
-#define BS_NV_FSEC_FSLACC (2U) //!< Bit field size in bits for NV_FSEC_FSLACC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the NV_FSEC_FSLACC field.
-#define BR_NV_FSEC_FSLACC (HW_NV_FSEC.B.FSLACC)
-#endif
-//@}
-
-/*!
- * @name Register NV_FSEC, field MEEN[5:4] (RO)
- */
-//@{
-#define BP_NV_FSEC_MEEN (4U) //!< Bit position for NV_FSEC_MEEN.
-#define BM_NV_FSEC_MEEN (0x30U) //!< Bit mask for NV_FSEC_MEEN.
-#define BS_NV_FSEC_MEEN (2U) //!< Bit field size in bits for NV_FSEC_MEEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the NV_FSEC_MEEN field.
-#define BR_NV_FSEC_MEEN (HW_NV_FSEC.B.MEEN)
-#endif
-//@}
-
-/*!
- * @name Register NV_FSEC, field KEYEN[7:6] (RO)
- */
-//@{
-#define BP_NV_FSEC_KEYEN (6U) //!< Bit position for NV_FSEC_KEYEN.
-#define BM_NV_FSEC_KEYEN (0xC0U) //!< Bit mask for NV_FSEC_KEYEN.
-#define BS_NV_FSEC_KEYEN (2U) //!< Bit field size in bits for NV_FSEC_KEYEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the NV_FSEC_KEYEN field.
-#define BR_NV_FSEC_KEYEN (HW_NV_FSEC.B.KEYEN)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_NV_FOPT - Non-volatile Flash Option Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_NV_FOPT - Non-volatile Flash Option Register (RO)
- *
- * Reset value: 0xFFU
- */
-typedef union _hw_nv_fopt
-{
- uint8_t U;
- struct _hw_nv_fopt_bitfields
- {
- uint8_t LPBOOT : 1; //!< [0]
- uint8_t EZPORT_DIS : 1; //!< [1]
- uint8_t RESERVED0 : 6; //!< [7:2]
- } B;
-} hw_nv_fopt_t;
-#endif
-
-/*!
- * @name Constants and macros for entire NV_FOPT register
- */
-//@{
-#define HW_NV_FOPT_ADDR (REGS_NV_BASE + 0xDU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_NV_FOPT (*(__I hw_nv_fopt_t *) HW_NV_FOPT_ADDR)
-#define HW_NV_FOPT_RD() (HW_NV_FOPT.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual NV_FOPT bitfields
- */
-
-/*!
- * @name Register NV_FOPT, field LPBOOT[0] (RO)
- */
-//@{
-#define BP_NV_FOPT_LPBOOT (0U) //!< Bit position for NV_FOPT_LPBOOT.
-#define BM_NV_FOPT_LPBOOT (0x01U) //!< Bit mask for NV_FOPT_LPBOOT.
-#define BS_NV_FOPT_LPBOOT (1U) //!< Bit field size in bits for NV_FOPT_LPBOOT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the NV_FOPT_LPBOOT field.
-#define BR_NV_FOPT_LPBOOT (BITBAND_ACCESS8(HW_NV_FOPT_ADDR, BP_NV_FOPT_LPBOOT))
-#endif
-//@}
-
-/*!
- * @name Register NV_FOPT, field EZPORT_DIS[1] (RO)
- */
-//@{
-#define BP_NV_FOPT_EZPORT_DIS (1U) //!< Bit position for NV_FOPT_EZPORT_DIS.
-#define BM_NV_FOPT_EZPORT_DIS (0x02U) //!< Bit mask for NV_FOPT_EZPORT_DIS.
-#define BS_NV_FOPT_EZPORT_DIS (1U) //!< Bit field size in bits for NV_FOPT_EZPORT_DIS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the NV_FOPT_EZPORT_DIS field.
-#define BR_NV_FOPT_EZPORT_DIS (BITBAND_ACCESS8(HW_NV_FOPT_ADDR, BP_NV_FOPT_EZPORT_DIS))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_NV_FEPROT - Non-volatile EERAM Protection Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_NV_FEPROT - Non-volatile EERAM Protection Register (RO)
- *
- * Reset value: 0xFFU
- */
-typedef union _hw_nv_feprot
-{
- uint8_t U;
- struct _hw_nv_feprot_bitfields
- {
- uint8_t EPROT : 8; //!< [7:0]
- } B;
-} hw_nv_feprot_t;
-#endif
-
-/*!
- * @name Constants and macros for entire NV_FEPROT register
- */
-//@{
-#define HW_NV_FEPROT_ADDR (REGS_NV_BASE + 0xEU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_NV_FEPROT (*(__I hw_nv_feprot_t *) HW_NV_FEPROT_ADDR)
-#define HW_NV_FEPROT_RD() (HW_NV_FEPROT.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual NV_FEPROT bitfields
- */
-
-/*!
- * @name Register NV_FEPROT, field EPROT[7:0] (RO)
- */
-//@{
-#define BP_NV_FEPROT_EPROT (0U) //!< Bit position for NV_FEPROT_EPROT.
-#define BM_NV_FEPROT_EPROT (0xFFU) //!< Bit mask for NV_FEPROT_EPROT.
-#define BS_NV_FEPROT_EPROT (8U) //!< Bit field size in bits for NV_FEPROT_EPROT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the NV_FEPROT_EPROT field.
-#define BR_NV_FEPROT_EPROT (HW_NV_FEPROT.U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_NV_FDPROT - Non-volatile D-Flash Protection Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_NV_FDPROT - Non-volatile D-Flash Protection Register (RO)
- *
- * Reset value: 0xFFU
- */
-typedef union _hw_nv_fdprot
-{
- uint8_t U;
- struct _hw_nv_fdprot_bitfields
- {
- uint8_t DPROT : 8; //!< [7:0] D-Flash Region Protect
- } B;
-} hw_nv_fdprot_t;
-#endif
-
-/*!
- * @name Constants and macros for entire NV_FDPROT register
- */
-//@{
-#define HW_NV_FDPROT_ADDR (REGS_NV_BASE + 0xFU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_NV_FDPROT (*(__I hw_nv_fdprot_t *) HW_NV_FDPROT_ADDR)
-#define HW_NV_FDPROT_RD() (HW_NV_FDPROT.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual NV_FDPROT bitfields
- */
-
-/*!
- * @name Register NV_FDPROT, field DPROT[7:0] (RO)
- */
-//@{
-#define BP_NV_FDPROT_DPROT (0U) //!< Bit position for NV_FDPROT_DPROT.
-#define BM_NV_FDPROT_DPROT (0xFFU) //!< Bit mask for NV_FDPROT_DPROT.
-#define BS_NV_FDPROT_DPROT (8U) //!< Bit field size in bits for NV_FDPROT_DPROT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the NV_FDPROT_DPROT field.
-#define BR_NV_FDPROT_DPROT (HW_NV_FDPROT.U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_nv_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All NV module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_nv
-{
- __I hw_nv_backkey3_t BACKKEY3; //!< [0x0] Backdoor Comparison Key 3.
- __I hw_nv_backkey2_t BACKKEY2; //!< [0x1] Backdoor Comparison Key 2.
- __I hw_nv_backkey1_t BACKKEY1; //!< [0x2] Backdoor Comparison Key 1.
- __I hw_nv_backkey0_t BACKKEY0; //!< [0x3] Backdoor Comparison Key 0.
- __I hw_nv_backkey7_t BACKKEY7; //!< [0x4] Backdoor Comparison Key 7.
- __I hw_nv_backkey6_t BACKKEY6; //!< [0x5] Backdoor Comparison Key 6.
- __I hw_nv_backkey5_t BACKKEY5; //!< [0x6] Backdoor Comparison Key 5.
- __I hw_nv_backkey4_t BACKKEY4; //!< [0x7] Backdoor Comparison Key 4.
- __I hw_nv_fprot3_t FPROT3; //!< [0x8] Non-volatile P-Flash Protection 1 - Low Register
- __I hw_nv_fprot2_t FPROT2; //!< [0x9] Non-volatile P-Flash Protection 1 - High Register
- __I hw_nv_fprot1_t FPROT1; //!< [0xA] Non-volatile P-Flash Protection 0 - Low Register
- __I hw_nv_fprot0_t FPROT0; //!< [0xB] Non-volatile P-Flash Protection 0 - High Register
- __I hw_nv_fsec_t FSEC; //!< [0xC] Non-volatile Flash Security Register
- __I hw_nv_fopt_t FOPT; //!< [0xD] Non-volatile Flash Option Register
- __I hw_nv_feprot_t FEPROT; //!< [0xE] Non-volatile EERAM Protection Register
- __I hw_nv_fdprot_t FDPROT; //!< [0xF] Non-volatile D-Flash Protection Register
-} hw_nv_t;
-#pragma pack()
-
-//! @brief Macro to access all NV registers.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_NV</code>.
-#define HW_NV (*(hw_nv_t *) REGS_NV_BASE)
-#endif
-
-#endif // __HW_NV_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_osc.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,302 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_OSC_REGISTERS_H__
-#define __HW_OSC_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 OSC
- *
- * Oscillator
- *
- * Registers defined in this header file:
- * - HW_OSC_CR - OSC Control Register
- *
- * - hw_osc_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_OSC_BASE
-#define HW_OSC_INSTANCE_COUNT (1U) //!< Number of instances of the OSC module.
-#define HW_OSC0 (0U) //!< Instance number for OSC.
-#define REGS_OSC0_BASE (0x40065000U) //!< Base address for OSC.
-
-//! @brief Table of base addresses for OSC instances.
-static const uint32_t __g_regs_OSC_base_addresses[] = {
- REGS_OSC0_BASE,
- };
-
-//! @brief Get the base address of OSC by instance number.
-//! @param x OSC instance number, from 0 through 0.
-#define REGS_OSC_BASE(x) (__g_regs_OSC_base_addresses[(x)])
-
-//! @brief Get the instance number given a base address.
-//! @param b Base address for an instance of OSC.
-#define REGS_OSC_INSTANCE(b) ((b) == REGS_OSC0_BASE ? HW_OSC0 : 0)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_OSC_CR - OSC Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_OSC_CR - OSC Control Register (RW)
- *
- * Reset value: 0x00U
- *
- * After OSC is enabled and starts generating the clocks, the configurations
- * such as low power and frequency range, must not be changed.
- */
-typedef union _hw_osc_cr
-{
- uint8_t U;
- struct _hw_osc_cr_bitfields
- {
- uint8_t SC16P : 1; //!< [0] Oscillator 16 pF Capacitor Load Configure
- uint8_t SC8P : 1; //!< [1] Oscillator 8 pF Capacitor Load Configure
- uint8_t SC4P : 1; //!< [2] Oscillator 4 pF Capacitor Load Configure
- uint8_t SC2P : 1; //!< [3] Oscillator 2 pF Capacitor Load Configure
- uint8_t RESERVED0 : 1; //!< [4]
- uint8_t EREFSTEN : 1; //!< [5] External Reference Stop Enable
- uint8_t RESERVED1 : 1; //!< [6]
- uint8_t ERCLKEN : 1; //!< [7] External Reference Enable
- } B;
-} hw_osc_cr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire OSC_CR register
- */
-//@{
-#define HW_OSC_CR_ADDR(x) (REGS_OSC_BASE(x) + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_OSC_CR(x) (*(__IO hw_osc_cr_t *) HW_OSC_CR_ADDR(x))
-#define HW_OSC_CR_RD(x) (HW_OSC_CR(x).U)
-#define HW_OSC_CR_WR(x, v) (HW_OSC_CR(x).U = (v))
-#define HW_OSC_CR_SET(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) | (v)))
-#define HW_OSC_CR_CLR(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) & ~(v)))
-#define HW_OSC_CR_TOG(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual OSC_CR bitfields
- */
-
-/*!
- * @name Register OSC_CR, field SC16P[0] (RW)
- *
- * Configures the oscillator load.
- *
- * Values:
- * - 0 - Disable the selection.
- * - 1 - Add 16 pF capacitor to the oscillator load.
- */
-//@{
-#define BP_OSC_CR_SC16P (0U) //!< Bit position for OSC_CR_SC16P.
-#define BM_OSC_CR_SC16P (0x01U) //!< Bit mask for OSC_CR_SC16P.
-#define BS_OSC_CR_SC16P (1U) //!< Bit field size in bits for OSC_CR_SC16P.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the OSC_CR_SC16P field.
-#define BR_OSC_CR_SC16P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC16P))
-#endif
-
-//! @brief Format value for bitfield OSC_CR_SC16P.
-#define BF_OSC_CR_SC16P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_SC16P), uint8_t) & BM_OSC_CR_SC16P)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SC16P field to a new value.
-#define BW_OSC_CR_SC16P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC16P) = (v))
-#endif
-//@}
-
-/*!
- * @name Register OSC_CR, field SC8P[1] (RW)
- *
- * Configures the oscillator load.
- *
- * Values:
- * - 0 - Disable the selection.
- * - 1 - Add 8 pF capacitor to the oscillator load.
- */
-//@{
-#define BP_OSC_CR_SC8P (1U) //!< Bit position for OSC_CR_SC8P.
-#define BM_OSC_CR_SC8P (0x02U) //!< Bit mask for OSC_CR_SC8P.
-#define BS_OSC_CR_SC8P (1U) //!< Bit field size in bits for OSC_CR_SC8P.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the OSC_CR_SC8P field.
-#define BR_OSC_CR_SC8P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC8P))
-#endif
-
-//! @brief Format value for bitfield OSC_CR_SC8P.
-#define BF_OSC_CR_SC8P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_SC8P), uint8_t) & BM_OSC_CR_SC8P)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SC8P field to a new value.
-#define BW_OSC_CR_SC8P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC8P) = (v))
-#endif
-//@}
-
-/*!
- * @name Register OSC_CR, field SC4P[2] (RW)
- *
- * Configures the oscillator load.
- *
- * Values:
- * - 0 - Disable the selection.
- * - 1 - Add 4 pF capacitor to the oscillator load.
- */
-//@{
-#define BP_OSC_CR_SC4P (2U) //!< Bit position for OSC_CR_SC4P.
-#define BM_OSC_CR_SC4P (0x04U) //!< Bit mask for OSC_CR_SC4P.
-#define BS_OSC_CR_SC4P (1U) //!< Bit field size in bits for OSC_CR_SC4P.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the OSC_CR_SC4P field.
-#define BR_OSC_CR_SC4P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC4P))
-#endif
-
-//! @brief Format value for bitfield OSC_CR_SC4P.
-#define BF_OSC_CR_SC4P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_SC4P), uint8_t) & BM_OSC_CR_SC4P)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SC4P field to a new value.
-#define BW_OSC_CR_SC4P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC4P) = (v))
-#endif
-//@}
-
-/*!
- * @name Register OSC_CR, field SC2P[3] (RW)
- *
- * Configures the oscillator load.
- *
- * Values:
- * - 0 - Disable the selection.
- * - 1 - Add 2 pF capacitor to the oscillator load.
- */
-//@{
-#define BP_OSC_CR_SC2P (3U) //!< Bit position for OSC_CR_SC2P.
-#define BM_OSC_CR_SC2P (0x08U) //!< Bit mask for OSC_CR_SC2P.
-#define BS_OSC_CR_SC2P (1U) //!< Bit field size in bits for OSC_CR_SC2P.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the OSC_CR_SC2P field.
-#define BR_OSC_CR_SC2P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC2P))
-#endif
-
-//! @brief Format value for bitfield OSC_CR_SC2P.
-#define BF_OSC_CR_SC2P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_SC2P), uint8_t) & BM_OSC_CR_SC2P)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SC2P field to a new value.
-#define BW_OSC_CR_SC2P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC2P) = (v))
-#endif
-//@}
-
-/*!
- * @name Register OSC_CR, field EREFSTEN[5] (RW)
- *
- * Controls whether or not the external reference clock (OSCERCLK) remains
- * enabled when MCU enters Stop mode.
- *
- * Values:
- * - 0 - External reference clock is disabled in Stop mode.
- * - 1 - External reference clock stays enabled in Stop mode if ERCLKEN is set
- * before entering Stop mode.
- */
-//@{
-#define BP_OSC_CR_EREFSTEN (5U) //!< Bit position for OSC_CR_EREFSTEN.
-#define BM_OSC_CR_EREFSTEN (0x20U) //!< Bit mask for OSC_CR_EREFSTEN.
-#define BS_OSC_CR_EREFSTEN (1U) //!< Bit field size in bits for OSC_CR_EREFSTEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the OSC_CR_EREFSTEN field.
-#define BR_OSC_CR_EREFSTEN(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_EREFSTEN))
-#endif
-
-//! @brief Format value for bitfield OSC_CR_EREFSTEN.
-#define BF_OSC_CR_EREFSTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_EREFSTEN), uint8_t) & BM_OSC_CR_EREFSTEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EREFSTEN field to a new value.
-#define BW_OSC_CR_EREFSTEN(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_EREFSTEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register OSC_CR, field ERCLKEN[7] (RW)
- *
- * Enables external reference clock (OSCERCLK).
- *
- * Values:
- * - 0 - External reference clock is inactive.
- * - 1 - External reference clock is enabled.
- */
-//@{
-#define BP_OSC_CR_ERCLKEN (7U) //!< Bit position for OSC_CR_ERCLKEN.
-#define BM_OSC_CR_ERCLKEN (0x80U) //!< Bit mask for OSC_CR_ERCLKEN.
-#define BS_OSC_CR_ERCLKEN (1U) //!< Bit field size in bits for OSC_CR_ERCLKEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the OSC_CR_ERCLKEN field.
-#define BR_OSC_CR_ERCLKEN(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_ERCLKEN))
-#endif
-
-//! @brief Format value for bitfield OSC_CR_ERCLKEN.
-#define BF_OSC_CR_ERCLKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_ERCLKEN), uint8_t) & BM_OSC_CR_ERCLKEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERCLKEN field to a new value.
-#define BW_OSC_CR_ERCLKEN(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_ERCLKEN) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_osc_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All OSC module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_osc
-{
- __IO hw_osc_cr_t CR; //!< [0x0] OSC Control Register
-} hw_osc_t;
-#pragma pack()
-
-//! @brief Macro to access all OSC registers.
-//! @param x OSC instance number.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_OSC(0)</code>.
-#define HW_OSC(x) (*(hw_osc_t *) REGS_OSC_BASE(x))
-#endif
-
-#endif // __HW_OSC_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_pdb.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1433 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_PDB_REGISTERS_H__
-#define __HW_PDB_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 PDB
- *
- * Programmable Delay Block
- *
- * Registers defined in this header file:
- * - HW_PDB_SC - Status and Control register
- * - HW_PDB_MOD - Modulus register
- * - HW_PDB_CNT - Counter register
- * - HW_PDB_IDLY - Interrupt Delay register
- * - HW_PDB_CHnC1 - Channel n Control register 1
- * - HW_PDB_CHnS - Channel n Status register
- * - HW_PDB_CHnDLY0 - Channel n Delay 0 register
- * - HW_PDB_CHnDLY1 - Channel n Delay 1 register
- * - HW_PDB_DACINTCn - DAC Interval Trigger n Control register
- * - HW_PDB_DACINTn - DAC Interval n register
- * - HW_PDB_POEN - Pulse-Out n Enable register
- * - HW_PDB_POnDLY - Pulse-Out n Delay register
- *
- * - hw_pdb_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_PDB_BASE
-#define HW_PDB_INSTANCE_COUNT (1U) //!< Number of instances of the PDB module.
-#define REGS_PDB_BASE (0x40036000U) //!< Base address for PDB0.
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_PDB_SC - Status and Control register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_PDB_SC - Status and Control register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_pdb_sc
-{
- uint32_t U;
- struct _hw_pdb_sc_bitfields
- {
- uint32_t LDOK : 1; //!< [0] Load OK
- uint32_t CONT : 1; //!< [1] Continuous Mode Enable
- uint32_t MULT : 2; //!< [3:2] Multiplication Factor Select for
- //! Prescaler
- uint32_t RESERVED0 : 1; //!< [4]
- uint32_t PDBIE : 1; //!< [5] PDB Interrupt Enable
- uint32_t PDBIF : 1; //!< [6] PDB Interrupt Flag
- uint32_t PDBEN : 1; //!< [7] PDB Enable
- uint32_t TRGSEL : 4; //!< [11:8] Trigger Input Source Select
- uint32_t PRESCALER : 3; //!< [14:12] Prescaler Divider Select
- uint32_t DMAEN : 1; //!< [15] DMA Enable
- uint32_t SWTRIG : 1; //!< [16] Software Trigger
- uint32_t PDBEIE : 1; //!< [17] PDB Sequence Error Interrupt Enable
- uint32_t LDMOD : 2; //!< [19:18] Load Mode Select
- uint32_t RESERVED1 : 12; //!< [31:20]
- } B;
-} hw_pdb_sc_t;
-#endif
-
-/*!
- * @name Constants and macros for entire PDB_SC register
- */
-//@{
-#define HW_PDB_SC_ADDR (REGS_PDB_BASE + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_PDB_SC (*(__IO hw_pdb_sc_t *) HW_PDB_SC_ADDR)
-#define HW_PDB_SC_RD() (HW_PDB_SC.U)
-#define HW_PDB_SC_WR(v) (HW_PDB_SC.U = (v))
-#define HW_PDB_SC_SET(v) (HW_PDB_SC_WR(HW_PDB_SC_RD() | (v)))
-#define HW_PDB_SC_CLR(v) (HW_PDB_SC_WR(HW_PDB_SC_RD() & ~(v)))
-#define HW_PDB_SC_TOG(v) (HW_PDB_SC_WR(HW_PDB_SC_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual PDB_SC bitfields
- */
-
-/*!
- * @name Register PDB_SC, field LDOK[0] (RW)
- *
- * Writing 1 to this bit updates the internal registers of MOD, IDLY, CHnDLYm,
- * DACINTx,and POyDLY with the values written to their buffers. The MOD, IDLY,
- * CHnDLYm, DACINTx, and POyDLY will take effect according to the LDMOD. After 1 is
- * written to the LDOK field, the values in the buffers of above registers are
- * not effective and the buffers cannot be written until the values in buffers are
- * loaded into their internal registers. LDOK can be written only when PDBEN is
- * set or it can be written at the same time with PDBEN being written to 1. It is
- * automatically cleared when the values in buffers are loaded into the internal
- * registers or the PDBEN is cleared. Writing 0 to it has no effect.
- */
-//@{
-#define BP_PDB_SC_LDOK (0U) //!< Bit position for PDB_SC_LDOK.
-#define BM_PDB_SC_LDOK (0x00000001U) //!< Bit mask for PDB_SC_LDOK.
-#define BS_PDB_SC_LDOK (1U) //!< Bit field size in bits for PDB_SC_LDOK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PDB_SC_LDOK field.
-#define BR_PDB_SC_LDOK (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_LDOK))
-#endif
-
-//! @brief Format value for bitfield PDB_SC_LDOK.
-#define BF_PDB_SC_LDOK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_LDOK), uint32_t) & BM_PDB_SC_LDOK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LDOK field to a new value.
-#define BW_PDB_SC_LDOK(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_LDOK) = (v))
-#endif
-//@}
-
-/*!
- * @name Register PDB_SC, field CONT[1] (RW)
- *
- * Enables the PDB operation in Continuous mode.
- *
- * Values:
- * - 0 - PDB operation in One-Shot mode
- * - 1 - PDB operation in Continuous mode
- */
-//@{
-#define BP_PDB_SC_CONT (1U) //!< Bit position for PDB_SC_CONT.
-#define BM_PDB_SC_CONT (0x00000002U) //!< Bit mask for PDB_SC_CONT.
-#define BS_PDB_SC_CONT (1U) //!< Bit field size in bits for PDB_SC_CONT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PDB_SC_CONT field.
-#define BR_PDB_SC_CONT (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_CONT))
-#endif
-
-//! @brief Format value for bitfield PDB_SC_CONT.
-#define BF_PDB_SC_CONT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_CONT), uint32_t) & BM_PDB_SC_CONT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CONT field to a new value.
-#define BW_PDB_SC_CONT(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_CONT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register PDB_SC, field MULT[3:2] (RW)
- *
- * Selects the multiplication factor of the prescaler divider for the counter
- * clock.
- *
- * Values:
- * - 00 - Multiplication factor is 1.
- * - 01 - Multiplication factor is 10.
- * - 10 - Multiplication factor is 20.
- * - 11 - Multiplication factor is 40.
- */
-//@{
-#define BP_PDB_SC_MULT (2U) //!< Bit position for PDB_SC_MULT.
-#define BM_PDB_SC_MULT (0x0000000CU) //!< Bit mask for PDB_SC_MULT.
-#define BS_PDB_SC_MULT (2U) //!< Bit field size in bits for PDB_SC_MULT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PDB_SC_MULT field.
-#define BR_PDB_SC_MULT (HW_PDB_SC.B.MULT)
-#endif
-
-//! @brief Format value for bitfield PDB_SC_MULT.
-#define BF_PDB_SC_MULT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_MULT), uint32_t) & BM_PDB_SC_MULT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MULT field to a new value.
-#define BW_PDB_SC_MULT(v) (HW_PDB_SC_WR((HW_PDB_SC_RD() & ~BM_PDB_SC_MULT) | BF_PDB_SC_MULT(v)))
-#endif
-//@}
-
-/*!
- * @name Register PDB_SC, field PDBIE[5] (RW)
- *
- * Enables the PDB interrupt. When this field is set and DMAEN is cleared, PDBIF
- * generates a PDB interrupt.
- *
- * Values:
- * - 0 - PDB interrupt disabled.
- * - 1 - PDB interrupt enabled.
- */
-//@{
-#define BP_PDB_SC_PDBIE (5U) //!< Bit position for PDB_SC_PDBIE.
-#define BM_PDB_SC_PDBIE (0x00000020U) //!< Bit mask for PDB_SC_PDBIE.
-#define BS_PDB_SC_PDBIE (1U) //!< Bit field size in bits for PDB_SC_PDBIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PDB_SC_PDBIE field.
-#define BR_PDB_SC_PDBIE (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBIE))
-#endif
-
-//! @brief Format value for bitfield PDB_SC_PDBIE.
-#define BF_PDB_SC_PDBIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_PDBIE), uint32_t) & BM_PDB_SC_PDBIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PDBIE field to a new value.
-#define BW_PDB_SC_PDBIE(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register PDB_SC, field PDBIF[6] (RW)
- *
- * This field is set when the counter value is equal to the IDLY register.
- * Writing zero clears this field.
- */
-//@{
-#define BP_PDB_SC_PDBIF (6U) //!< Bit position for PDB_SC_PDBIF.
-#define BM_PDB_SC_PDBIF (0x00000040U) //!< Bit mask for PDB_SC_PDBIF.
-#define BS_PDB_SC_PDBIF (1U) //!< Bit field size in bits for PDB_SC_PDBIF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PDB_SC_PDBIF field.
-#define BR_PDB_SC_PDBIF (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBIF))
-#endif
-
-//! @brief Format value for bitfield PDB_SC_PDBIF.
-#define BF_PDB_SC_PDBIF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_PDBIF), uint32_t) & BM_PDB_SC_PDBIF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PDBIF field to a new value.
-#define BW_PDB_SC_PDBIF(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBIF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register PDB_SC, field PDBEN[7] (RW)
- *
- * Values:
- * - 0 - PDB disabled. Counter is off.
- * - 1 - PDB enabled.
- */
-//@{
-#define BP_PDB_SC_PDBEN (7U) //!< Bit position for PDB_SC_PDBEN.
-#define BM_PDB_SC_PDBEN (0x00000080U) //!< Bit mask for PDB_SC_PDBEN.
-#define BS_PDB_SC_PDBEN (1U) //!< Bit field size in bits for PDB_SC_PDBEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PDB_SC_PDBEN field.
-#define BR_PDB_SC_PDBEN (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBEN))
-#endif
-
-//! @brief Format value for bitfield PDB_SC_PDBEN.
-#define BF_PDB_SC_PDBEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_PDBEN), uint32_t) & BM_PDB_SC_PDBEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PDBEN field to a new value.
-#define BW_PDB_SC_PDBEN(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register PDB_SC, field TRGSEL[11:8] (RW)
- *
- * Selects the trigger input source for the PDB. The trigger input source can be
- * internal or external (EXTRG pin), or the software trigger. Refer to chip
- * configuration details for the actual PDB input trigger connections.
- *
- * Values:
- * - 0000 - Trigger-In 0 is selected.
- * - 0001 - Trigger-In 1 is selected.
- * - 0010 - Trigger-In 2 is selected.
- * - 0011 - Trigger-In 3 is selected.
- * - 0100 - Trigger-In 4 is selected.
- * - 0101 - Trigger-In 5 is selected.
- * - 0110 - Trigger-In 6 is selected.
- * - 0111 - Trigger-In 7 is selected.
- * - 1000 - Trigger-In 8 is selected.
- * - 1001 - Trigger-In 9 is selected.
- * - 1010 - Trigger-In 10 is selected.
- * - 1011 - Trigger-In 11 is selected.
- * - 1100 - Trigger-In 12 is selected.
- * - 1101 - Trigger-In 13 is selected.
- * - 1110 - Trigger-In 14 is selected.
- * - 1111 - Software trigger is selected.
- */
-//@{
-#define BP_PDB_SC_TRGSEL (8U) //!< Bit position for PDB_SC_TRGSEL.
-#define BM_PDB_SC_TRGSEL (0x00000F00U) //!< Bit mask for PDB_SC_TRGSEL.
-#define BS_PDB_SC_TRGSEL (4U) //!< Bit field size in bits for PDB_SC_TRGSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PDB_SC_TRGSEL field.
-#define BR_PDB_SC_TRGSEL (HW_PDB_SC.B.TRGSEL)
-#endif
-
-//! @brief Format value for bitfield PDB_SC_TRGSEL.
-#define BF_PDB_SC_TRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_TRGSEL), uint32_t) & BM_PDB_SC_TRGSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TRGSEL field to a new value.
-#define BW_PDB_SC_TRGSEL(v) (HW_PDB_SC_WR((HW_PDB_SC_RD() & ~BM_PDB_SC_TRGSEL) | BF_PDB_SC_TRGSEL(v)))
-#endif
-//@}
-
-/*!
- * @name Register PDB_SC, field PRESCALER[14:12] (RW)
- *
- * Values:
- * - 000 - Counting uses the peripheral clock divided by multiplication factor
- * selected by MULT.
- * - 001 - Counting uses the peripheral clock divided by twice of the
- * multiplication factor selected by MULT.
- * - 010 - Counting uses the peripheral clock divided by four times of the
- * multiplication factor selected by MULT.
- * - 011 - Counting uses the peripheral clock divided by eight times of the
- * multiplication factor selected by MULT.
- * - 100 - Counting uses the peripheral clock divided by 16 times of the
- * multiplication factor selected by MULT.
- * - 101 - Counting uses the peripheral clock divided by 32 times of the
- * multiplication factor selected by MULT.
- * - 110 - Counting uses the peripheral clock divided by 64 times of the
- * multiplication factor selected by MULT.
- * - 111 - Counting uses the peripheral clock divided by 128 times of the
- * multiplication factor selected by MULT.
- */
-//@{
-#define BP_PDB_SC_PRESCALER (12U) //!< Bit position for PDB_SC_PRESCALER.
-#define BM_PDB_SC_PRESCALER (0x00007000U) //!< Bit mask for PDB_SC_PRESCALER.
-#define BS_PDB_SC_PRESCALER (3U) //!< Bit field size in bits for PDB_SC_PRESCALER.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PDB_SC_PRESCALER field.
-#define BR_PDB_SC_PRESCALER (HW_PDB_SC.B.PRESCALER)
-#endif
-
-//! @brief Format value for bitfield PDB_SC_PRESCALER.
-#define BF_PDB_SC_PRESCALER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_PRESCALER), uint32_t) & BM_PDB_SC_PRESCALER)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PRESCALER field to a new value.
-#define BW_PDB_SC_PRESCALER(v) (HW_PDB_SC_WR((HW_PDB_SC_RD() & ~BM_PDB_SC_PRESCALER) | BF_PDB_SC_PRESCALER(v)))
-#endif
-//@}
-
-/*!
- * @name Register PDB_SC, field DMAEN[15] (RW)
- *
- * When DMA is enabled, the PDBIF flag generates a DMA request instead of an
- * interrupt.
- *
- * Values:
- * - 0 - DMA disabled.
- * - 1 - DMA enabled.
- */
-//@{
-#define BP_PDB_SC_DMAEN (15U) //!< Bit position for PDB_SC_DMAEN.
-#define BM_PDB_SC_DMAEN (0x00008000U) //!< Bit mask for PDB_SC_DMAEN.
-#define BS_PDB_SC_DMAEN (1U) //!< Bit field size in bits for PDB_SC_DMAEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PDB_SC_DMAEN field.
-#define BR_PDB_SC_DMAEN (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_DMAEN))
-#endif
-
-//! @brief Format value for bitfield PDB_SC_DMAEN.
-#define BF_PDB_SC_DMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_DMAEN), uint32_t) & BM_PDB_SC_DMAEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DMAEN field to a new value.
-#define BW_PDB_SC_DMAEN(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_DMAEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register PDB_SC, field SWTRIG[16] (WORZ)
- *
- * When PDB is enabled and the software trigger is selected as the trigger input
- * source, writing 1 to this field resets and restarts the counter. Writing 0 to
- * this field has no effect. Reading this field results 0.
- */
-//@{
-#define BP_PDB_SC_SWTRIG (16U) //!< Bit position for PDB_SC_SWTRIG.
-#define BM_PDB_SC_SWTRIG (0x00010000U) //!< Bit mask for PDB_SC_SWTRIG.
-#define BS_PDB_SC_SWTRIG (1U) //!< Bit field size in bits for PDB_SC_SWTRIG.
-
-//! @brief Format value for bitfield PDB_SC_SWTRIG.
-#define BF_PDB_SC_SWTRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_SWTRIG), uint32_t) & BM_PDB_SC_SWTRIG)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SWTRIG field to a new value.
-#define BW_PDB_SC_SWTRIG(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_SWTRIG) = (v))
-#endif
-//@}
-
-/*!
- * @name Register PDB_SC, field PDBEIE[17] (RW)
- *
- * Enables the PDB sequence error interrupt. When this field is set, any of the
- * PDB channel sequence error flags generates a PDB sequence error interrupt.
- *
- * Values:
- * - 0 - PDB sequence error interrupt disabled.
- * - 1 - PDB sequence error interrupt enabled.
- */
-//@{
-#define BP_PDB_SC_PDBEIE (17U) //!< Bit position for PDB_SC_PDBEIE.
-#define BM_PDB_SC_PDBEIE (0x00020000U) //!< Bit mask for PDB_SC_PDBEIE.
-#define BS_PDB_SC_PDBEIE (1U) //!< Bit field size in bits for PDB_SC_PDBEIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PDB_SC_PDBEIE field.
-#define BR_PDB_SC_PDBEIE (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBEIE))
-#endif
-
-//! @brief Format value for bitfield PDB_SC_PDBEIE.
-#define BF_PDB_SC_PDBEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_PDBEIE), uint32_t) & BM_PDB_SC_PDBEIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PDBEIE field to a new value.
-#define BW_PDB_SC_PDBEIE(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBEIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register PDB_SC, field LDMOD[19:18] (RW)
- *
- * Selects the mode to load the MOD, IDLY, CHnDLYm, INTx, and POyDLY registers,
- * after 1 is written to LDOK.
- *
- * Values:
- * - 00 - The internal registers are loaded with the values from their buffers
- * immediately after 1 is written to LDOK.
- * - 01 - The internal registers are loaded with the values from their buffers
- * when the PDB counter reaches the MOD register value after 1 is written to
- * LDOK.
- * - 10 - The internal registers are loaded with the values from their buffers
- * when a trigger input event is detected after 1 is written to LDOK.
- * - 11 - The internal registers are loaded with the values from their buffers
- * when either the PDB counter reaches the MOD register value or a trigger
- * input event is detected, after 1 is written to LDOK.
- */
-//@{
-#define BP_PDB_SC_LDMOD (18U) //!< Bit position for PDB_SC_LDMOD.
-#define BM_PDB_SC_LDMOD (0x000C0000U) //!< Bit mask for PDB_SC_LDMOD.
-#define BS_PDB_SC_LDMOD (2U) //!< Bit field size in bits for PDB_SC_LDMOD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PDB_SC_LDMOD field.
-#define BR_PDB_SC_LDMOD (HW_PDB_SC.B.LDMOD)
-#endif
-
-//! @brief Format value for bitfield PDB_SC_LDMOD.
-#define BF_PDB_SC_LDMOD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_LDMOD), uint32_t) & BM_PDB_SC_LDMOD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LDMOD field to a new value.
-#define BW_PDB_SC_LDMOD(v) (HW_PDB_SC_WR((HW_PDB_SC_RD() & ~BM_PDB_SC_LDMOD) | BF_PDB_SC_LDMOD(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_PDB_MOD - Modulus register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_PDB_MOD - Modulus register (RW)
- *
- * Reset value: 0x0000FFFFU
- */
-typedef union _hw_pdb_mod
-{
- uint32_t U;
- struct _hw_pdb_mod_bitfields
- {
- uint32_t MOD : 16; //!< [15:0] PDB Modulus
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_pdb_mod_t;
-#endif
-
-/*!
- * @name Constants and macros for entire PDB_MOD register
- */
-//@{
-#define HW_PDB_MOD_ADDR (REGS_PDB_BASE + 0x4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_PDB_MOD (*(__IO hw_pdb_mod_t *) HW_PDB_MOD_ADDR)
-#define HW_PDB_MOD_RD() (HW_PDB_MOD.U)
-#define HW_PDB_MOD_WR(v) (HW_PDB_MOD.U = (v))
-#define HW_PDB_MOD_SET(v) (HW_PDB_MOD_WR(HW_PDB_MOD_RD() | (v)))
-#define HW_PDB_MOD_CLR(v) (HW_PDB_MOD_WR(HW_PDB_MOD_RD() & ~(v)))
-#define HW_PDB_MOD_TOG(v) (HW_PDB_MOD_WR(HW_PDB_MOD_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual PDB_MOD bitfields
- */
-
-/*!
- * @name Register PDB_MOD, field MOD[15:0] (RW)
- *
- * Specifies the period of the counter. When the counter reaches this value, it
- * will be reset back to zero. If the PDB is in Continuous mode, the count begins
- * anew. Reading this field returns the value of the internal register that is
- * effective for the current cycle of PDB.
- */
-//@{
-#define BP_PDB_MOD_MOD (0U) //!< Bit position for PDB_MOD_MOD.
-#define BM_PDB_MOD_MOD (0x0000FFFFU) //!< Bit mask for PDB_MOD_MOD.
-#define BS_PDB_MOD_MOD (16U) //!< Bit field size in bits for PDB_MOD_MOD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PDB_MOD_MOD field.
-#define BR_PDB_MOD_MOD (HW_PDB_MOD.B.MOD)
-#endif
-
-//! @brief Format value for bitfield PDB_MOD_MOD.
-#define BF_PDB_MOD_MOD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_MOD_MOD), uint32_t) & BM_PDB_MOD_MOD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MOD field to a new value.
-#define BW_PDB_MOD_MOD(v) (HW_PDB_MOD_WR((HW_PDB_MOD_RD() & ~BM_PDB_MOD_MOD) | BF_PDB_MOD_MOD(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_PDB_CNT - Counter register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_PDB_CNT - Counter register (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_pdb_cnt
-{
- uint32_t U;
- struct _hw_pdb_cnt_bitfields
- {
- uint32_t CNT : 16; //!< [15:0] PDB Counter
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_pdb_cnt_t;
-#endif
-
-/*!
- * @name Constants and macros for entire PDB_CNT register
- */
-//@{
-#define HW_PDB_CNT_ADDR (REGS_PDB_BASE + 0x8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_PDB_CNT (*(__I hw_pdb_cnt_t *) HW_PDB_CNT_ADDR)
-#define HW_PDB_CNT_RD() (HW_PDB_CNT.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual PDB_CNT bitfields
- */
-
-/*!
- * @name Register PDB_CNT, field CNT[15:0] (RO)
- *
- * Contains the current value of the counter.
- */
-//@{
-#define BP_PDB_CNT_CNT (0U) //!< Bit position for PDB_CNT_CNT.
-#define BM_PDB_CNT_CNT (0x0000FFFFU) //!< Bit mask for PDB_CNT_CNT.
-#define BS_PDB_CNT_CNT (16U) //!< Bit field size in bits for PDB_CNT_CNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PDB_CNT_CNT field.
-#define BR_PDB_CNT_CNT (HW_PDB_CNT.B.CNT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_PDB_IDLY - Interrupt Delay register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_PDB_IDLY - Interrupt Delay register (RW)
- *
- * Reset value: 0x0000FFFFU
- */
-typedef union _hw_pdb_idly
-{
- uint32_t U;
- struct _hw_pdb_idly_bitfields
- {
- uint32_t IDLY : 16; //!< [15:0] PDB Interrupt Delay
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_pdb_idly_t;
-#endif
-
-/*!
- * @name Constants and macros for entire PDB_IDLY register
- */
-//@{
-#define HW_PDB_IDLY_ADDR (REGS_PDB_BASE + 0xCU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_PDB_IDLY (*(__IO hw_pdb_idly_t *) HW_PDB_IDLY_ADDR)
-#define HW_PDB_IDLY_RD() (HW_PDB_IDLY.U)
-#define HW_PDB_IDLY_WR(v) (HW_PDB_IDLY.U = (v))
-#define HW_PDB_IDLY_SET(v) (HW_PDB_IDLY_WR(HW_PDB_IDLY_RD() | (v)))
-#define HW_PDB_IDLY_CLR(v) (HW_PDB_IDLY_WR(HW_PDB_IDLY_RD() & ~(v)))
-#define HW_PDB_IDLY_TOG(v) (HW_PDB_IDLY_WR(HW_PDB_IDLY_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual PDB_IDLY bitfields
- */
-
-/*!
- * @name Register PDB_IDLY, field IDLY[15:0] (RW)
- *
- * Specifies the delay value to schedule the PDB interrupt. It can be used to
- * schedule an independent interrupt at some point in the PDB cycle. If enabled, a
- * PDB interrupt is generated, when the counter is equal to the IDLY. Reading
- * this field returns the value of internal register that is effective for the
- * current cycle of the PDB.
- */
-//@{
-#define BP_PDB_IDLY_IDLY (0U) //!< Bit position for PDB_IDLY_IDLY.
-#define BM_PDB_IDLY_IDLY (0x0000FFFFU) //!< Bit mask for PDB_IDLY_IDLY.
-#define BS_PDB_IDLY_IDLY (16U) //!< Bit field size in bits for PDB_IDLY_IDLY.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PDB_IDLY_IDLY field.
-#define BR_PDB_IDLY_IDLY (HW_PDB_IDLY.B.IDLY)
-#endif
-
-//! @brief Format value for bitfield PDB_IDLY_IDLY.
-#define BF_PDB_IDLY_IDLY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_IDLY_IDLY), uint32_t) & BM_PDB_IDLY_IDLY)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IDLY field to a new value.
-#define BW_PDB_IDLY_IDLY(v) (HW_PDB_IDLY_WR((HW_PDB_IDLY_RD() & ~BM_PDB_IDLY_IDLY) | BF_PDB_IDLY_IDLY(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_PDB_CHnC1 - Channel n Control register 1
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_PDB_CHnC1 - Channel n Control register 1 (RW)
- *
- * Reset value: 0x00000000U
- *
- * Each PDB channel has one control register, CHnC1. The bits in this register
- * control the functionality of each PDB channel operation.
- */
-typedef union _hw_pdb_chnc1
-{
- uint32_t U;
- struct _hw_pdb_chnc1_bitfields
- {
- uint32_t EN : 8; //!< [7:0] PDB Channel Pre-Trigger Enable
- uint32_t TOS : 8; //!< [15:8] PDB Channel Pre-Trigger Output Select
- uint32_t BB : 8; //!< [23:16] PDB Channel Pre-Trigger Back-to-Back
- //! Operation Enable
- uint32_t RESERVED0 : 8; //!< [31:24]
- } B;
-} hw_pdb_chnc1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire PDB_CHnC1 register
- */
-//@{
-#define HW_PDB_CHnC1_COUNT (2U)
-
-#define HW_PDB_CHnC1_ADDR(n) (REGS_PDB_BASE + 0x10U + (0x28U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_PDB_CHnC1(n) (*(__IO hw_pdb_chnc1_t *) HW_PDB_CHnC1_ADDR(n))
-#define HW_PDB_CHnC1_RD(n) (HW_PDB_CHnC1(n).U)
-#define HW_PDB_CHnC1_WR(n, v) (HW_PDB_CHnC1(n).U = (v))
-#define HW_PDB_CHnC1_SET(n, v) (HW_PDB_CHnC1_WR(n, HW_PDB_CHnC1_RD(n) | (v)))
-#define HW_PDB_CHnC1_CLR(n, v) (HW_PDB_CHnC1_WR(n, HW_PDB_CHnC1_RD(n) & ~(v)))
-#define HW_PDB_CHnC1_TOG(n, v) (HW_PDB_CHnC1_WR(n, HW_PDB_CHnC1_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual PDB_CHnC1 bitfields
- */
-
-/*!
- * @name Register PDB_CHnC1, field EN[7:0] (RW)
- *
- * These bits enable the PDB ADC pre-trigger outputs. Only lower M pre-trigger
- * bits are implemented in this MCU.
- *
- * Values:
- * - 0 - PDB channel's corresponding pre-trigger disabled.
- * - 1 - PDB channel's corresponding pre-trigger enabled.
- */
-//@{
-#define BP_PDB_CHnC1_EN (0U) //!< Bit position for PDB_CHnC1_EN.
-#define BM_PDB_CHnC1_EN (0x000000FFU) //!< Bit mask for PDB_CHnC1_EN.
-#define BS_PDB_CHnC1_EN (8U) //!< Bit field size in bits for PDB_CHnC1_EN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PDB_CHnC1_EN field.
-#define BR_PDB_CHnC1_EN(n) (HW_PDB_CHnC1(n).B.EN)
-#endif
-
-//! @brief Format value for bitfield PDB_CHnC1_EN.
-#define BF_PDB_CHnC1_EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnC1_EN), uint32_t) & BM_PDB_CHnC1_EN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EN field to a new value.
-#define BW_PDB_CHnC1_EN(n, v) (HW_PDB_CHnC1_WR(n, (HW_PDB_CHnC1_RD(n) & ~BM_PDB_CHnC1_EN) | BF_PDB_CHnC1_EN(v)))
-#endif
-//@}
-
-/*!
- * @name Register PDB_CHnC1, field TOS[15:8] (RW)
- *
- * Selects the PDB ADC pre-trigger outputs. Only lower M pre-trigger fields are
- * implemented in this MCU.
- *
- * Values:
- * - 0 - PDB channel's corresponding pre-trigger is in bypassed mode. The
- * pre-trigger asserts one peripheral clock cycle after a rising edge is detected
- * on selected trigger input source or software trigger is selected and SWTRIG
- * is written with 1.
- * - 1 - PDB channel's corresponding pre-trigger asserts when the counter
- * reaches the channel delay register and one peripheral clock cycle after a rising
- * edge is detected on selected trigger input source or software trigger is
- * selected and SETRIG is written with 1.
- */
-//@{
-#define BP_PDB_CHnC1_TOS (8U) //!< Bit position for PDB_CHnC1_TOS.
-#define BM_PDB_CHnC1_TOS (0x0000FF00U) //!< Bit mask for PDB_CHnC1_TOS.
-#define BS_PDB_CHnC1_TOS (8U) //!< Bit field size in bits for PDB_CHnC1_TOS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PDB_CHnC1_TOS field.
-#define BR_PDB_CHnC1_TOS(n) (HW_PDB_CHnC1(n).B.TOS)
-#endif
-
-//! @brief Format value for bitfield PDB_CHnC1_TOS.
-#define BF_PDB_CHnC1_TOS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnC1_TOS), uint32_t) & BM_PDB_CHnC1_TOS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TOS field to a new value.
-#define BW_PDB_CHnC1_TOS(n, v) (HW_PDB_CHnC1_WR(n, (HW_PDB_CHnC1_RD(n) & ~BM_PDB_CHnC1_TOS) | BF_PDB_CHnC1_TOS(v)))
-#endif
-//@}
-
-/*!
- * @name Register PDB_CHnC1, field BB[23:16] (RW)
- *
- * These bits enable the PDB ADC pre-trigger operation as back-to-back mode.
- * Only lower M pre-trigger bits are implemented in this MCU. Back-to-back operation
- * enables the ADC conversions complete to trigger the next PDB channel
- * pre-trigger and trigger output, so that the ADC conversions can be triggered on next
- * set of configuration and results registers. Application code must only enable
- * the back-to-back operation of the PDB pre-triggers at the leading of the
- * back-to-back connection chain.
- *
- * Values:
- * - 0 - PDB channel's corresponding pre-trigger back-to-back operation disabled.
- * - 1 - PDB channel's corresponding pre-trigger back-to-back operation enabled.
- */
-//@{
-#define BP_PDB_CHnC1_BB (16U) //!< Bit position for PDB_CHnC1_BB.
-#define BM_PDB_CHnC1_BB (0x00FF0000U) //!< Bit mask for PDB_CHnC1_BB.
-#define BS_PDB_CHnC1_BB (8U) //!< Bit field size in bits for PDB_CHnC1_BB.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PDB_CHnC1_BB field.
-#define BR_PDB_CHnC1_BB(n) (HW_PDB_CHnC1(n).B.BB)
-#endif
-
-//! @brief Format value for bitfield PDB_CHnC1_BB.
-#define BF_PDB_CHnC1_BB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnC1_BB), uint32_t) & BM_PDB_CHnC1_BB)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BB field to a new value.
-#define BW_PDB_CHnC1_BB(n, v) (HW_PDB_CHnC1_WR(n, (HW_PDB_CHnC1_RD(n) & ~BM_PDB_CHnC1_BB) | BF_PDB_CHnC1_BB(v)))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_PDB_CHnS - Channel n Status register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_PDB_CHnS - Channel n Status register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_pdb_chns
-{
- uint32_t U;
- struct _hw_pdb_chns_bitfields
- {
- uint32_t ERR : 8; //!< [7:0] PDB Channel Sequence Error Flags
- uint32_t RESERVED0 : 8; //!< [15:8]
- uint32_t CF : 8; //!< [23:16] PDB Channel Flags
- uint32_t RESERVED1 : 8; //!< [31:24]
- } B;
-} hw_pdb_chns_t;
-#endif
-
-/*!
- * @name Constants and macros for entire PDB_CHnS register
- */
-//@{
-#define HW_PDB_CHnS_COUNT (2U)
-
-#define HW_PDB_CHnS_ADDR(n) (REGS_PDB_BASE + 0x14U + (0x28U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_PDB_CHnS(n) (*(__IO hw_pdb_chns_t *) HW_PDB_CHnS_ADDR(n))
-#define HW_PDB_CHnS_RD(n) (HW_PDB_CHnS(n).U)
-#define HW_PDB_CHnS_WR(n, v) (HW_PDB_CHnS(n).U = (v))
-#define HW_PDB_CHnS_SET(n, v) (HW_PDB_CHnS_WR(n, HW_PDB_CHnS_RD(n) | (v)))
-#define HW_PDB_CHnS_CLR(n, v) (HW_PDB_CHnS_WR(n, HW_PDB_CHnS_RD(n) & ~(v)))
-#define HW_PDB_CHnS_TOG(n, v) (HW_PDB_CHnS_WR(n, HW_PDB_CHnS_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual PDB_CHnS bitfields
- */
-
-/*!
- * @name Register PDB_CHnS, field ERR[7:0] (RW)
- *
- * Only the lower M bits are implemented in this MCU.
- *
- * Values:
- * - 0 - Sequence error not detected on PDB channel's corresponding pre-trigger.
- * - 1 - Sequence error detected on PDB channel's corresponding pre-trigger.
- * ADCn block can be triggered for a conversion by one pre-trigger from PDB
- * channel n. When one conversion, which is triggered by one of the pre-triggers
- * from PDB channel n, is in progress, new trigger from PDB channel's
- * corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set.
- * Writing 0's to clear the sequence error flags.
- */
-//@{
-#define BP_PDB_CHnS_ERR (0U) //!< Bit position for PDB_CHnS_ERR.
-#define BM_PDB_CHnS_ERR (0x000000FFU) //!< Bit mask for PDB_CHnS_ERR.
-#define BS_PDB_CHnS_ERR (8U) //!< Bit field size in bits for PDB_CHnS_ERR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PDB_CHnS_ERR field.
-#define BR_PDB_CHnS_ERR(n) (HW_PDB_CHnS(n).B.ERR)
-#endif
-
-//! @brief Format value for bitfield PDB_CHnS_ERR.
-#define BF_PDB_CHnS_ERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnS_ERR), uint32_t) & BM_PDB_CHnS_ERR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERR field to a new value.
-#define BW_PDB_CHnS_ERR(n, v) (HW_PDB_CHnS_WR(n, (HW_PDB_CHnS_RD(n) & ~BM_PDB_CHnS_ERR) | BF_PDB_CHnS_ERR(v)))
-#endif
-//@}
-
-/*!
- * @name Register PDB_CHnS, field CF[23:16] (RW)
- *
- * The CF[m] bit is set when the PDB counter matches the CHnDLYm. Write 0 to
- * clear these bits.
- */
-//@{
-#define BP_PDB_CHnS_CF (16U) //!< Bit position for PDB_CHnS_CF.
-#define BM_PDB_CHnS_CF (0x00FF0000U) //!< Bit mask for PDB_CHnS_CF.
-#define BS_PDB_CHnS_CF (8U) //!< Bit field size in bits for PDB_CHnS_CF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PDB_CHnS_CF field.
-#define BR_PDB_CHnS_CF(n) (HW_PDB_CHnS(n).B.CF)
-#endif
-
-//! @brief Format value for bitfield PDB_CHnS_CF.
-#define BF_PDB_CHnS_CF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnS_CF), uint32_t) & BM_PDB_CHnS_CF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CF field to a new value.
-#define BW_PDB_CHnS_CF(n, v) (HW_PDB_CHnS_WR(n, (HW_PDB_CHnS_RD(n) & ~BM_PDB_CHnS_CF) | BF_PDB_CHnS_CF(v)))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_PDB_CHnDLY0 - Channel n Delay 0 register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_PDB_CHnDLY0 - Channel n Delay 0 register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_pdb_chndly0
-{
- uint32_t U;
- struct _hw_pdb_chndly0_bitfields
- {
- uint32_t DLY : 16; //!< [15:0] PDB Channel Delay
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_pdb_chndly0_t;
-#endif
-
-/*!
- * @name Constants and macros for entire PDB_CHnDLY0 register
- */
-//@{
-#define HW_PDB_CHnDLY0_COUNT (2U)
-
-#define HW_PDB_CHnDLY0_ADDR(n) (REGS_PDB_BASE + 0x18U + (0x28U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_PDB_CHnDLY0(n) (*(__IO hw_pdb_chndly0_t *) HW_PDB_CHnDLY0_ADDR(n))
-#define HW_PDB_CHnDLY0_RD(n) (HW_PDB_CHnDLY0(n).U)
-#define HW_PDB_CHnDLY0_WR(n, v) (HW_PDB_CHnDLY0(n).U = (v))
-#define HW_PDB_CHnDLY0_SET(n, v) (HW_PDB_CHnDLY0_WR(n, HW_PDB_CHnDLY0_RD(n) | (v)))
-#define HW_PDB_CHnDLY0_CLR(n, v) (HW_PDB_CHnDLY0_WR(n, HW_PDB_CHnDLY0_RD(n) & ~(v)))
-#define HW_PDB_CHnDLY0_TOG(n, v) (HW_PDB_CHnDLY0_WR(n, HW_PDB_CHnDLY0_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual PDB_CHnDLY0 bitfields
- */
-
-/*!
- * @name Register PDB_CHnDLY0, field DLY[15:0] (RW)
- *
- * Specifies the delay value for the channel's corresponding pre-trigger. The
- * pre-trigger asserts when the counter is equal to DLY. Reading this field returns
- * the value of internal register that is effective for the current PDB cycle.
- */
-//@{
-#define BP_PDB_CHnDLY0_DLY (0U) //!< Bit position for PDB_CHnDLY0_DLY.
-#define BM_PDB_CHnDLY0_DLY (0x0000FFFFU) //!< Bit mask for PDB_CHnDLY0_DLY.
-#define BS_PDB_CHnDLY0_DLY (16U) //!< Bit field size in bits for PDB_CHnDLY0_DLY.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PDB_CHnDLY0_DLY field.
-#define BR_PDB_CHnDLY0_DLY(n) (HW_PDB_CHnDLY0(n).B.DLY)
-#endif
-
-//! @brief Format value for bitfield PDB_CHnDLY0_DLY.
-#define BF_PDB_CHnDLY0_DLY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnDLY0_DLY), uint32_t) & BM_PDB_CHnDLY0_DLY)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DLY field to a new value.
-#define BW_PDB_CHnDLY0_DLY(n, v) (HW_PDB_CHnDLY0_WR(n, (HW_PDB_CHnDLY0_RD(n) & ~BM_PDB_CHnDLY0_DLY) | BF_PDB_CHnDLY0_DLY(v)))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_PDB_CHnDLY1 - Channel n Delay 1 register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_PDB_CHnDLY1 - Channel n Delay 1 register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_pdb_chndly1
-{
- uint32_t U;
- struct _hw_pdb_chndly1_bitfields
- {
- uint32_t DLY : 16; //!< [15:0] PDB Channel Delay
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_pdb_chndly1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire PDB_CHnDLY1 register
- */
-//@{
-#define HW_PDB_CHnDLY1_COUNT (2U)
-
-#define HW_PDB_CHnDLY1_ADDR(n) (REGS_PDB_BASE + 0x1CU + (0x28U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_PDB_CHnDLY1(n) (*(__IO hw_pdb_chndly1_t *) HW_PDB_CHnDLY1_ADDR(n))
-#define HW_PDB_CHnDLY1_RD(n) (HW_PDB_CHnDLY1(n).U)
-#define HW_PDB_CHnDLY1_WR(n, v) (HW_PDB_CHnDLY1(n).U = (v))
-#define HW_PDB_CHnDLY1_SET(n, v) (HW_PDB_CHnDLY1_WR(n, HW_PDB_CHnDLY1_RD(n) | (v)))
-#define HW_PDB_CHnDLY1_CLR(n, v) (HW_PDB_CHnDLY1_WR(n, HW_PDB_CHnDLY1_RD(n) & ~(v)))
-#define HW_PDB_CHnDLY1_TOG(n, v) (HW_PDB_CHnDLY1_WR(n, HW_PDB_CHnDLY1_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual PDB_CHnDLY1 bitfields
- */
-
-/*!
- * @name Register PDB_CHnDLY1, field DLY[15:0] (RW)
- *
- * These bits specify the delay value for the channel's corresponding
- * pre-trigger. The pre-trigger asserts when the counter is equal to DLY. Reading these
- * bits returns the value of internal register that is effective for the current PDB
- * cycle.
- */
-//@{
-#define BP_PDB_CHnDLY1_DLY (0U) //!< Bit position for PDB_CHnDLY1_DLY.
-#define BM_PDB_CHnDLY1_DLY (0x0000FFFFU) //!< Bit mask for PDB_CHnDLY1_DLY.
-#define BS_PDB_CHnDLY1_DLY (16U) //!< Bit field size in bits for PDB_CHnDLY1_DLY.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PDB_CHnDLY1_DLY field.
-#define BR_PDB_CHnDLY1_DLY(n) (HW_PDB_CHnDLY1(n).B.DLY)
-#endif
-
-//! @brief Format value for bitfield PDB_CHnDLY1_DLY.
-#define BF_PDB_CHnDLY1_DLY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnDLY1_DLY), uint32_t) & BM_PDB_CHnDLY1_DLY)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DLY field to a new value.
-#define BW_PDB_CHnDLY1_DLY(n, v) (HW_PDB_CHnDLY1_WR(n, (HW_PDB_CHnDLY1_RD(n) & ~BM_PDB_CHnDLY1_DLY) | BF_PDB_CHnDLY1_DLY(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_PDB_DACINTCn - DAC Interval Trigger n Control register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_PDB_DACINTCn - DAC Interval Trigger n Control register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_pdb_dacintcn
-{
- uint32_t U;
- struct _hw_pdb_dacintcn_bitfields
- {
- uint32_t TOE : 1; //!< [0] DAC Interval Trigger Enable
- uint32_t EXT : 1; //!< [1] DAC External Trigger Input Enable
- uint32_t RESERVED0 : 30; //!< [31:2]
- } B;
-} hw_pdb_dacintcn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire PDB_DACINTCn register
- */
-//@{
-#define HW_PDB_DACINTCn_COUNT (2U)
-
-#define HW_PDB_DACINTCn_ADDR(n) (REGS_PDB_BASE + 0x150U + (0x8U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_PDB_DACINTCn(n) (*(__IO hw_pdb_dacintcn_t *) HW_PDB_DACINTCn_ADDR(n))
-#define HW_PDB_DACINTCn_RD(n) (HW_PDB_DACINTCn(n).U)
-#define HW_PDB_DACINTCn_WR(n, v) (HW_PDB_DACINTCn(n).U = (v))
-#define HW_PDB_DACINTCn_SET(n, v) (HW_PDB_DACINTCn_WR(n, HW_PDB_DACINTCn_RD(n) | (v)))
-#define HW_PDB_DACINTCn_CLR(n, v) (HW_PDB_DACINTCn_WR(n, HW_PDB_DACINTCn_RD(n) & ~(v)))
-#define HW_PDB_DACINTCn_TOG(n, v) (HW_PDB_DACINTCn_WR(n, HW_PDB_DACINTCn_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual PDB_DACINTCn bitfields
- */
-
-/*!
- * @name Register PDB_DACINTCn, field TOE[0] (RW)
- *
- * This bit enables the DAC interval trigger.
- *
- * Values:
- * - 0 - DAC interval trigger disabled.
- * - 1 - DAC interval trigger enabled.
- */
-//@{
-#define BP_PDB_DACINTCn_TOE (0U) //!< Bit position for PDB_DACINTCn_TOE.
-#define BM_PDB_DACINTCn_TOE (0x00000001U) //!< Bit mask for PDB_DACINTCn_TOE.
-#define BS_PDB_DACINTCn_TOE (1U) //!< Bit field size in bits for PDB_DACINTCn_TOE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PDB_DACINTCn_TOE field.
-#define BR_PDB_DACINTCn_TOE(n) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(n), BP_PDB_DACINTCn_TOE))
-#endif
-
-//! @brief Format value for bitfield PDB_DACINTCn_TOE.
-#define BF_PDB_DACINTCn_TOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_DACINTCn_TOE), uint32_t) & BM_PDB_DACINTCn_TOE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TOE field to a new value.
-#define BW_PDB_DACINTCn_TOE(n, v) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(n), BP_PDB_DACINTCn_TOE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register PDB_DACINTCn, field EXT[1] (RW)
- *
- * Enables the external trigger for DAC interval counter.
- *
- * Values:
- * - 0 - DAC external trigger input disabled. DAC interval counter is reset and
- * counting starts when a rising edge is detected on selected trigger input
- * source or software trigger is selected and SWTRIG is written with 1.
- * - 1 - DAC external trigger input enabled. DAC interval counter is bypassed
- * and DAC external trigger input triggers the DAC interval trigger.
- */
-//@{
-#define BP_PDB_DACINTCn_EXT (1U) //!< Bit position for PDB_DACINTCn_EXT.
-#define BM_PDB_DACINTCn_EXT (0x00000002U) //!< Bit mask for PDB_DACINTCn_EXT.
-#define BS_PDB_DACINTCn_EXT (1U) //!< Bit field size in bits for PDB_DACINTCn_EXT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PDB_DACINTCn_EXT field.
-#define BR_PDB_DACINTCn_EXT(n) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(n), BP_PDB_DACINTCn_EXT))
-#endif
-
-//! @brief Format value for bitfield PDB_DACINTCn_EXT.
-#define BF_PDB_DACINTCn_EXT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_DACINTCn_EXT), uint32_t) & BM_PDB_DACINTCn_EXT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EXT field to a new value.
-#define BW_PDB_DACINTCn_EXT(n, v) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(n), BP_PDB_DACINTCn_EXT) = (v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_PDB_DACINTn - DAC Interval n register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_PDB_DACINTn - DAC Interval n register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_pdb_dacintn
-{
- uint32_t U;
- struct _hw_pdb_dacintn_bitfields
- {
- uint32_t INT : 16; //!< [15:0] DAC Interval
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_pdb_dacintn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire PDB_DACINTn register
- */
-//@{
-#define HW_PDB_DACINTn_COUNT (2U)
-
-#define HW_PDB_DACINTn_ADDR(n) (REGS_PDB_BASE + 0x154U + (0x8U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_PDB_DACINTn(n) (*(__IO hw_pdb_dacintn_t *) HW_PDB_DACINTn_ADDR(n))
-#define HW_PDB_DACINTn_RD(n) (HW_PDB_DACINTn(n).U)
-#define HW_PDB_DACINTn_WR(n, v) (HW_PDB_DACINTn(n).U = (v))
-#define HW_PDB_DACINTn_SET(n, v) (HW_PDB_DACINTn_WR(n, HW_PDB_DACINTn_RD(n) | (v)))
-#define HW_PDB_DACINTn_CLR(n, v) (HW_PDB_DACINTn_WR(n, HW_PDB_DACINTn_RD(n) & ~(v)))
-#define HW_PDB_DACINTn_TOG(n, v) (HW_PDB_DACINTn_WR(n, HW_PDB_DACINTn_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual PDB_DACINTn bitfields
- */
-
-/*!
- * @name Register PDB_DACINTn, field INT[15:0] (RW)
- *
- * Specifies the interval value for DAC interval trigger. DAC interval trigger
- * triggers DAC[1:0] update when the DAC interval counter is equal to the DACINT.
- * Reading this field returns the value of internal register that is effective
- * for the current PDB cycle.
- */
-//@{
-#define BP_PDB_DACINTn_INT (0U) //!< Bit position for PDB_DACINTn_INT.
-#define BM_PDB_DACINTn_INT (0x0000FFFFU) //!< Bit mask for PDB_DACINTn_INT.
-#define BS_PDB_DACINTn_INT (16U) //!< Bit field size in bits for PDB_DACINTn_INT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PDB_DACINTn_INT field.
-#define BR_PDB_DACINTn_INT(n) (HW_PDB_DACINTn(n).B.INT)
-#endif
-
-//! @brief Format value for bitfield PDB_DACINTn_INT.
-#define BF_PDB_DACINTn_INT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_DACINTn_INT), uint32_t) & BM_PDB_DACINTn_INT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INT field to a new value.
-#define BW_PDB_DACINTn_INT(n, v) (HW_PDB_DACINTn_WR(n, (HW_PDB_DACINTn_RD(n) & ~BM_PDB_DACINTn_INT) | BF_PDB_DACINTn_INT(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_PDB_POEN - Pulse-Out n Enable register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_PDB_POEN - Pulse-Out n Enable register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_pdb_poen
-{
- uint32_t U;
- struct _hw_pdb_poen_bitfields
- {
- uint32_t POEN : 8; //!< [7:0] PDB Pulse-Out Enable
- uint32_t RESERVED0 : 24; //!< [31:8]
- } B;
-} hw_pdb_poen_t;
-#endif
-
-/*!
- * @name Constants and macros for entire PDB_POEN register
- */
-//@{
-#define HW_PDB_POEN_ADDR (REGS_PDB_BASE + 0x190U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_PDB_POEN (*(__IO hw_pdb_poen_t *) HW_PDB_POEN_ADDR)
-#define HW_PDB_POEN_RD() (HW_PDB_POEN.U)
-#define HW_PDB_POEN_WR(v) (HW_PDB_POEN.U = (v))
-#define HW_PDB_POEN_SET(v) (HW_PDB_POEN_WR(HW_PDB_POEN_RD() | (v)))
-#define HW_PDB_POEN_CLR(v) (HW_PDB_POEN_WR(HW_PDB_POEN_RD() & ~(v)))
-#define HW_PDB_POEN_TOG(v) (HW_PDB_POEN_WR(HW_PDB_POEN_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual PDB_POEN bitfields
- */
-
-/*!
- * @name Register PDB_POEN, field POEN[7:0] (RW)
- *
- * Enables the pulse output. Only lower Y bits are implemented in this MCU.
- *
- * Values:
- * - 0 - PDB Pulse-Out disabled
- * - 1 - PDB Pulse-Out enabled
- */
-//@{
-#define BP_PDB_POEN_POEN (0U) //!< Bit position for PDB_POEN_POEN.
-#define BM_PDB_POEN_POEN (0x000000FFU) //!< Bit mask for PDB_POEN_POEN.
-#define BS_PDB_POEN_POEN (8U) //!< Bit field size in bits for PDB_POEN_POEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PDB_POEN_POEN field.
-#define BR_PDB_POEN_POEN (HW_PDB_POEN.B.POEN)
-#endif
-
-//! @brief Format value for bitfield PDB_POEN_POEN.
-#define BF_PDB_POEN_POEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_POEN_POEN), uint32_t) & BM_PDB_POEN_POEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the POEN field to a new value.
-#define BW_PDB_POEN_POEN(v) (HW_PDB_POEN_WR((HW_PDB_POEN_RD() & ~BM_PDB_POEN_POEN) | BF_PDB_POEN_POEN(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_PDB_POnDLY - Pulse-Out n Delay register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_PDB_POnDLY - Pulse-Out n Delay register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_pdb_pondly
-{
- uint32_t U;
- struct _hw_pdb_pondly_bitfields
- {
- uint32_t DLY2 : 16; //!< [15:0] PDB Pulse-Out Delay 2
- uint32_t DLY1 : 16; //!< [31:16] PDB Pulse-Out Delay 1
- } B;
-} hw_pdb_pondly_t;
-#endif
-
-/*!
- * @name Constants and macros for entire PDB_POnDLY register
- */
-//@{
-#define HW_PDB_POnDLY_COUNT (3U)
-
-#define HW_PDB_POnDLY_ADDR(n) (REGS_PDB_BASE + 0x194U + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_PDB_POnDLY(n) (*(__IO hw_pdb_pondly_t *) HW_PDB_POnDLY_ADDR(n))
-#define HW_PDB_POnDLY_RD(n) (HW_PDB_POnDLY(n).U)
-#define HW_PDB_POnDLY_WR(n, v) (HW_PDB_POnDLY(n).U = (v))
-#define HW_PDB_POnDLY_SET(n, v) (HW_PDB_POnDLY_WR(n, HW_PDB_POnDLY_RD(n) | (v)))
-#define HW_PDB_POnDLY_CLR(n, v) (HW_PDB_POnDLY_WR(n, HW_PDB_POnDLY_RD(n) & ~(v)))
-#define HW_PDB_POnDLY_TOG(n, v) (HW_PDB_POnDLY_WR(n, HW_PDB_POnDLY_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual PDB_POnDLY bitfields
- */
-
-/*!
- * @name Register PDB_POnDLY, field DLY2[15:0] (RW)
- *
- * These bits specify the delay 2 value for the PDB Pulse-Out. Pulse-Out goes
- * low when the PDB counter is equal to the DLY2. Reading these bits returns the
- * value of internal register that is effective for the current PDB cycle.
- */
-//@{
-#define BP_PDB_POnDLY_DLY2 (0U) //!< Bit position for PDB_POnDLY_DLY2.
-#define BM_PDB_POnDLY_DLY2 (0x0000FFFFU) //!< Bit mask for PDB_POnDLY_DLY2.
-#define BS_PDB_POnDLY_DLY2 (16U) //!< Bit field size in bits for PDB_POnDLY_DLY2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PDB_POnDLY_DLY2 field.
-#define BR_PDB_POnDLY_DLY2(n) (HW_PDB_POnDLY(n).B.DLY2)
-#endif
-
-//! @brief Format value for bitfield PDB_POnDLY_DLY2.
-#define BF_PDB_POnDLY_DLY2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_POnDLY_DLY2), uint32_t) & BM_PDB_POnDLY_DLY2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DLY2 field to a new value.
-#define BW_PDB_POnDLY_DLY2(n, v) (HW_PDB_POnDLY_WR(n, (HW_PDB_POnDLY_RD(n) & ~BM_PDB_POnDLY_DLY2) | BF_PDB_POnDLY_DLY2(v)))
-#endif
-//@}
-
-/*!
- * @name Register PDB_POnDLY, field DLY1[31:16] (RW)
- *
- * These bits specify the delay 1 value for the PDB Pulse-Out. Pulse-Out goes
- * high when the PDB counter is equal to the DLY1. Reading these bits returns the
- * value of internal register that is effective for the current PDB cycle.
- */
-//@{
-#define BP_PDB_POnDLY_DLY1 (16U) //!< Bit position for PDB_POnDLY_DLY1.
-#define BM_PDB_POnDLY_DLY1 (0xFFFF0000U) //!< Bit mask for PDB_POnDLY_DLY1.
-#define BS_PDB_POnDLY_DLY1 (16U) //!< Bit field size in bits for PDB_POnDLY_DLY1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PDB_POnDLY_DLY1 field.
-#define BR_PDB_POnDLY_DLY1(n) (HW_PDB_POnDLY(n).B.DLY1)
-#endif
-
-//! @brief Format value for bitfield PDB_POnDLY_DLY1.
-#define BF_PDB_POnDLY_DLY1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_POnDLY_DLY1), uint32_t) & BM_PDB_POnDLY_DLY1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DLY1 field to a new value.
-#define BW_PDB_POnDLY_DLY1(n, v) (HW_PDB_POnDLY_WR(n, (HW_PDB_POnDLY_RD(n) & ~BM_PDB_POnDLY_DLY1) | BF_PDB_POnDLY_DLY1(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_pdb_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All PDB module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_pdb
-{
- __IO hw_pdb_sc_t SC; //!< [0x0] Status and Control register
- __IO hw_pdb_mod_t MOD; //!< [0x4] Modulus register
- __I hw_pdb_cnt_t CNT; //!< [0x8] Counter register
- __IO hw_pdb_idly_t IDLY; //!< [0xC] Interrupt Delay register
- struct {
- __IO hw_pdb_chnc1_t CHnC1; //!< [0x10] Channel n Control register 1
- __IO hw_pdb_chns_t CHnS; //!< [0x14] Channel n Status register
- __IO hw_pdb_chndly0_t CHnDLY0; //!< [0x18] Channel n Delay 0 register
- __IO hw_pdb_chndly1_t CHnDLY1; //!< [0x1C] Channel n Delay 1 register
- uint8_t _reserved0[24];
- } CH[2];
- uint8_t _reserved0[240];
- struct {
- __IO hw_pdb_dacintcn_t DACINTCn; //!< [0x150] DAC Interval Trigger n Control register
- __IO hw_pdb_dacintn_t DACINTn; //!< [0x154] DAC Interval n register
- } DAC[2];
- uint8_t _reserved1[48];
- __IO hw_pdb_poen_t POEN; //!< [0x190] Pulse-Out n Enable register
- __IO hw_pdb_pondly_t POnDLY[3]; //!< [0x194] Pulse-Out n Delay register
-} hw_pdb_t;
-#pragma pack()
-
-//! @brief Macro to access all PDB registers.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_PDB</code>.
-#define HW_PDB (*(hw_pdb_t *) REGS_PDB_BASE)
-#endif
-
-#endif // __HW_PDB_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_pit.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,517 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_PIT_REGISTERS_H__
-#define __HW_PIT_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 PIT
- *
- * Periodic Interrupt Timer
- *
- * Registers defined in this header file:
- * - HW_PIT_MCR - PIT Module Control Register
- * - HW_PIT_LDVALn - Timer Load Value Register
- * - HW_PIT_CVALn - Current Timer Value Register
- * - HW_PIT_TCTRLn - Timer Control Register
- * - HW_PIT_TFLGn - Timer Flag Register
- *
- * - hw_pit_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_PIT_BASE
-#define HW_PIT_INSTANCE_COUNT (1U) //!< Number of instances of the PIT module.
-#define REGS_PIT_BASE (0x40037000U) //!< Base address for PIT.
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_PIT_MCR - PIT Module Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_PIT_MCR - PIT Module Control Register (RW)
- *
- * Reset value: 0x00000006U
- *
- * This register enables or disables the PIT timer clocks and controls the
- * timers when the PIT enters the Debug mode.
- */
-typedef union _hw_pit_mcr
-{
- uint32_t U;
- struct _hw_pit_mcr_bitfields
- {
- uint32_t FRZ : 1; //!< [0] Freeze
- uint32_t MDIS : 1; //!< [1] Module Disable - (PIT section)
- uint32_t RESERVED0 : 30; //!< [31:2]
- } B;
-} hw_pit_mcr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire PIT_MCR register
- */
-//@{
-#define HW_PIT_MCR_ADDR (REGS_PIT_BASE + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_PIT_MCR (*(__IO hw_pit_mcr_t *) HW_PIT_MCR_ADDR)
-#define HW_PIT_MCR_RD() (HW_PIT_MCR.U)
-#define HW_PIT_MCR_WR(v) (HW_PIT_MCR.U = (v))
-#define HW_PIT_MCR_SET(v) (HW_PIT_MCR_WR(HW_PIT_MCR_RD() | (v)))
-#define HW_PIT_MCR_CLR(v) (HW_PIT_MCR_WR(HW_PIT_MCR_RD() & ~(v)))
-#define HW_PIT_MCR_TOG(v) (HW_PIT_MCR_WR(HW_PIT_MCR_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual PIT_MCR bitfields
- */
-
-/*!
- * @name Register PIT_MCR, field FRZ[0] (RW)
- *
- * Allows the timers to be stopped when the device enters the Debug mode.
- *
- * Values:
- * - 0 - Timers continue to run in Debug mode.
- * - 1 - Timers are stopped in Debug mode.
- */
-//@{
-#define BP_PIT_MCR_FRZ (0U) //!< Bit position for PIT_MCR_FRZ.
-#define BM_PIT_MCR_FRZ (0x00000001U) //!< Bit mask for PIT_MCR_FRZ.
-#define BS_PIT_MCR_FRZ (1U) //!< Bit field size in bits for PIT_MCR_FRZ.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PIT_MCR_FRZ field.
-#define BR_PIT_MCR_FRZ (BITBAND_ACCESS32(HW_PIT_MCR_ADDR, BP_PIT_MCR_FRZ))
-#endif
-
-//! @brief Format value for bitfield PIT_MCR_FRZ.
-#define BF_PIT_MCR_FRZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_MCR_FRZ), uint32_t) & BM_PIT_MCR_FRZ)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FRZ field to a new value.
-#define BW_PIT_MCR_FRZ(v) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR, BP_PIT_MCR_FRZ) = (v))
-#endif
-//@}
-
-/*!
- * @name Register PIT_MCR, field MDIS[1] (RW)
- *
- * Disables the standard timers. This field must be enabled before any other
- * setup is done.
- *
- * Values:
- * - 0 - Clock for standard PIT timers is enabled.
- * - 1 - Clock for standard PIT timers is disabled.
- */
-//@{
-#define BP_PIT_MCR_MDIS (1U) //!< Bit position for PIT_MCR_MDIS.
-#define BM_PIT_MCR_MDIS (0x00000002U) //!< Bit mask for PIT_MCR_MDIS.
-#define BS_PIT_MCR_MDIS (1U) //!< Bit field size in bits for PIT_MCR_MDIS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PIT_MCR_MDIS field.
-#define BR_PIT_MCR_MDIS (BITBAND_ACCESS32(HW_PIT_MCR_ADDR, BP_PIT_MCR_MDIS))
-#endif
-
-//! @brief Format value for bitfield PIT_MCR_MDIS.
-#define BF_PIT_MCR_MDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_MCR_MDIS), uint32_t) & BM_PIT_MCR_MDIS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MDIS field to a new value.
-#define BW_PIT_MCR_MDIS(v) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR, BP_PIT_MCR_MDIS) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_PIT_LDVALn - Timer Load Value Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_PIT_LDVALn - Timer Load Value Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * These registers select the timeout period for the timer interrupts.
- */
-typedef union _hw_pit_ldvaln
-{
- uint32_t U;
- struct _hw_pit_ldvaln_bitfields
- {
- uint32_t TSV : 32; //!< [31:0] Timer Start Value
- } B;
-} hw_pit_ldvaln_t;
-#endif
-
-/*!
- * @name Constants and macros for entire PIT_LDVALn register
- */
-//@{
-#define HW_PIT_LDVALn_COUNT (4U)
-
-#define HW_PIT_LDVALn_ADDR(n) (REGS_PIT_BASE + 0x100U + (0x10U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_PIT_LDVALn(n) (*(__IO hw_pit_ldvaln_t *) HW_PIT_LDVALn_ADDR(n))
-#define HW_PIT_LDVALn_RD(n) (HW_PIT_LDVALn(n).U)
-#define HW_PIT_LDVALn_WR(n, v) (HW_PIT_LDVALn(n).U = (v))
-#define HW_PIT_LDVALn_SET(n, v) (HW_PIT_LDVALn_WR(n, HW_PIT_LDVALn_RD(n) | (v)))
-#define HW_PIT_LDVALn_CLR(n, v) (HW_PIT_LDVALn_WR(n, HW_PIT_LDVALn_RD(n) & ~(v)))
-#define HW_PIT_LDVALn_TOG(n, v) (HW_PIT_LDVALn_WR(n, HW_PIT_LDVALn_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual PIT_LDVALn bitfields
- */
-
-/*!
- * @name Register PIT_LDVALn, field TSV[31:0] (RW)
- *
- * Sets the timer start value. The timer will count down until it reaches 0,
- * then it will generate an interrupt and load this register value again. Writing a
- * new value to this register will not restart the timer; instead the value will
- * be loaded after the timer expires. To abort the current cycle and start a
- * timer period with the new value, the timer must be disabled and enabled again.
- */
-//@{
-#define BP_PIT_LDVALn_TSV (0U) //!< Bit position for PIT_LDVALn_TSV.
-#define BM_PIT_LDVALn_TSV (0xFFFFFFFFU) //!< Bit mask for PIT_LDVALn_TSV.
-#define BS_PIT_LDVALn_TSV (32U) //!< Bit field size in bits for PIT_LDVALn_TSV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PIT_LDVALn_TSV field.
-#define BR_PIT_LDVALn_TSV(n) (HW_PIT_LDVALn(n).U)
-#endif
-
-//! @brief Format value for bitfield PIT_LDVALn_TSV.
-#define BF_PIT_LDVALn_TSV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_LDVALn_TSV), uint32_t) & BM_PIT_LDVALn_TSV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TSV field to a new value.
-#define BW_PIT_LDVALn_TSV(n, v) (HW_PIT_LDVALn_WR(n, v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_PIT_CVALn - Current Timer Value Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_PIT_CVALn - Current Timer Value Register (RO)
- *
- * Reset value: 0x00000000U
- *
- * These registers indicate the current timer position.
- */
-typedef union _hw_pit_cvaln
-{
- uint32_t U;
- struct _hw_pit_cvaln_bitfields
- {
- uint32_t TVL : 32; //!< [31:0] Current Timer Value
- } B;
-} hw_pit_cvaln_t;
-#endif
-
-/*!
- * @name Constants and macros for entire PIT_CVALn register
- */
-//@{
-#define HW_PIT_CVALn_COUNT (4U)
-
-#define HW_PIT_CVALn_ADDR(n) (REGS_PIT_BASE + 0x104U + (0x10U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_PIT_CVALn(n) (*(__I hw_pit_cvaln_t *) HW_PIT_CVALn_ADDR(n))
-#define HW_PIT_CVALn_RD(n) (HW_PIT_CVALn(n).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual PIT_CVALn bitfields
- */
-
-/*!
- * @name Register PIT_CVALn, field TVL[31:0] (RO)
- *
- * Represents the current timer value, if the timer is enabled. If the timer is
- * disabled, do not use this field as its value is unreliable. The timer uses a
- * downcounter. The timer values are frozen in Debug mode if MCR[FRZ] is set.
- */
-//@{
-#define BP_PIT_CVALn_TVL (0U) //!< Bit position for PIT_CVALn_TVL.
-#define BM_PIT_CVALn_TVL (0xFFFFFFFFU) //!< Bit mask for PIT_CVALn_TVL.
-#define BS_PIT_CVALn_TVL (32U) //!< Bit field size in bits for PIT_CVALn_TVL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PIT_CVALn_TVL field.
-#define BR_PIT_CVALn_TVL(n) (HW_PIT_CVALn(n).U)
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_PIT_TCTRLn - Timer Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_PIT_TCTRLn - Timer Control Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * These registers contain the control bits for each timer.
- */
-typedef union _hw_pit_tctrln
-{
- uint32_t U;
- struct _hw_pit_tctrln_bitfields
- {
- uint32_t TEN : 1; //!< [0] Timer Enable
- uint32_t TIE : 1; //!< [1] Timer Interrupt Enable
- uint32_t CHN : 1; //!< [2] Chain Mode
- uint32_t RESERVED0 : 29; //!< [31:3]
- } B;
-} hw_pit_tctrln_t;
-#endif
-
-/*!
- * @name Constants and macros for entire PIT_TCTRLn register
- */
-//@{
-#define HW_PIT_TCTRLn_COUNT (4U)
-
-#define HW_PIT_TCTRLn_ADDR(n) (REGS_PIT_BASE + 0x108U + (0x10U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_PIT_TCTRLn(n) (*(__IO hw_pit_tctrln_t *) HW_PIT_TCTRLn_ADDR(n))
-#define HW_PIT_TCTRLn_RD(n) (HW_PIT_TCTRLn(n).U)
-#define HW_PIT_TCTRLn_WR(n, v) (HW_PIT_TCTRLn(n).U = (v))
-#define HW_PIT_TCTRLn_SET(n, v) (HW_PIT_TCTRLn_WR(n, HW_PIT_TCTRLn_RD(n) | (v)))
-#define HW_PIT_TCTRLn_CLR(n, v) (HW_PIT_TCTRLn_WR(n, HW_PIT_TCTRLn_RD(n) & ~(v)))
-#define HW_PIT_TCTRLn_TOG(n, v) (HW_PIT_TCTRLn_WR(n, HW_PIT_TCTRLn_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual PIT_TCTRLn bitfields
- */
-
-/*!
- * @name Register PIT_TCTRLn, field TEN[0] (RW)
- *
- * Enables or disables the timer.
- *
- * Values:
- * - 0 - Timer n is disabled.
- * - 1 - Timer n is enabled.
- */
-//@{
-#define BP_PIT_TCTRLn_TEN (0U) //!< Bit position for PIT_TCTRLn_TEN.
-#define BM_PIT_TCTRLn_TEN (0x00000001U) //!< Bit mask for PIT_TCTRLn_TEN.
-#define BS_PIT_TCTRLn_TEN (1U) //!< Bit field size in bits for PIT_TCTRLn_TEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PIT_TCTRLn_TEN field.
-#define BR_PIT_TCTRLn_TEN(n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_TEN))
-#endif
-
-//! @brief Format value for bitfield PIT_TCTRLn_TEN.
-#define BF_PIT_TCTRLn_TEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_TCTRLn_TEN), uint32_t) & BM_PIT_TCTRLn_TEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TEN field to a new value.
-#define BW_PIT_TCTRLn_TEN(n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_TEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register PIT_TCTRLn, field TIE[1] (RW)
- *
- * When an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt
- * will immediately cause an interrupt event. To avoid this, the associated
- * TFLGn[TIF] must be cleared first.
- *
- * Values:
- * - 0 - Interrupt requests from Timer n are disabled.
- * - 1 - Interrupt will be requested whenever TIF is set.
- */
-//@{
-#define BP_PIT_TCTRLn_TIE (1U) //!< Bit position for PIT_TCTRLn_TIE.
-#define BM_PIT_TCTRLn_TIE (0x00000002U) //!< Bit mask for PIT_TCTRLn_TIE.
-#define BS_PIT_TCTRLn_TIE (1U) //!< Bit field size in bits for PIT_TCTRLn_TIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PIT_TCTRLn_TIE field.
-#define BR_PIT_TCTRLn_TIE(n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_TIE))
-#endif
-
-//! @brief Format value for bitfield PIT_TCTRLn_TIE.
-#define BF_PIT_TCTRLn_TIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_TCTRLn_TIE), uint32_t) & BM_PIT_TCTRLn_TIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TIE field to a new value.
-#define BW_PIT_TCTRLn_TIE(n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_TIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register PIT_TCTRLn, field CHN[2] (RW)
- *
- * When activated, Timer n-1 needs to expire before timer n can decrement by 1.
- * Timer 0 cannot be chained.
- *
- * Values:
- * - 0 - Timer is not chained.
- * - 1 - Timer is chained to previous timer. For example, for Channel 2, if this
- * field is set, Timer 2 is chained to Timer 1.
- */
-//@{
-#define BP_PIT_TCTRLn_CHN (2U) //!< Bit position for PIT_TCTRLn_CHN.
-#define BM_PIT_TCTRLn_CHN (0x00000004U) //!< Bit mask for PIT_TCTRLn_CHN.
-#define BS_PIT_TCTRLn_CHN (1U) //!< Bit field size in bits for PIT_TCTRLn_CHN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PIT_TCTRLn_CHN field.
-#define BR_PIT_TCTRLn_CHN(n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_CHN))
-#endif
-
-//! @brief Format value for bitfield PIT_TCTRLn_CHN.
-#define BF_PIT_TCTRLn_CHN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_TCTRLn_CHN), uint32_t) & BM_PIT_TCTRLn_CHN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CHN field to a new value.
-#define BW_PIT_TCTRLn_CHN(n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_CHN) = (v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_PIT_TFLGn - Timer Flag Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_PIT_TFLGn - Timer Flag Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * These registers hold the PIT interrupt flags.
- */
-typedef union _hw_pit_tflgn
-{
- uint32_t U;
- struct _hw_pit_tflgn_bitfields
- {
- uint32_t TIF : 1; //!< [0] Timer Interrupt Flag
- uint32_t RESERVED0 : 31; //!< [31:1]
- } B;
-} hw_pit_tflgn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire PIT_TFLGn register
- */
-//@{
-#define HW_PIT_TFLGn_COUNT (4U)
-
-#define HW_PIT_TFLGn_ADDR(n) (REGS_PIT_BASE + 0x10CU + (0x10U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_PIT_TFLGn(n) (*(__IO hw_pit_tflgn_t *) HW_PIT_TFLGn_ADDR(n))
-#define HW_PIT_TFLGn_RD(n) (HW_PIT_TFLGn(n).U)
-#define HW_PIT_TFLGn_WR(n, v) (HW_PIT_TFLGn(n).U = (v))
-#define HW_PIT_TFLGn_SET(n, v) (HW_PIT_TFLGn_WR(n, HW_PIT_TFLGn_RD(n) | (v)))
-#define HW_PIT_TFLGn_CLR(n, v) (HW_PIT_TFLGn_WR(n, HW_PIT_TFLGn_RD(n) & ~(v)))
-#define HW_PIT_TFLGn_TOG(n, v) (HW_PIT_TFLGn_WR(n, HW_PIT_TFLGn_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual PIT_TFLGn bitfields
- */
-
-/*!
- * @name Register PIT_TFLGn, field TIF[0] (W1C)
- *
- * Sets to 1 at the end of the timer period. Writing 1 to this flag clears it.
- * Writing 0 has no effect. If enabled, or, when TCTRLn[TIE] = 1, TIF causes an
- * interrupt request.
- *
- * Values:
- * - 0 - Timeout has not yet occurred.
- * - 1 - Timeout has occurred.
- */
-//@{
-#define BP_PIT_TFLGn_TIF (0U) //!< Bit position for PIT_TFLGn_TIF.
-#define BM_PIT_TFLGn_TIF (0x00000001U) //!< Bit mask for PIT_TFLGn_TIF.
-#define BS_PIT_TFLGn_TIF (1U) //!< Bit field size in bits for PIT_TFLGn_TIF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PIT_TFLGn_TIF field.
-#define BR_PIT_TFLGn_TIF(n) (BITBAND_ACCESS32(HW_PIT_TFLGn_ADDR(n), BP_PIT_TFLGn_TIF))
-#endif
-
-//! @brief Format value for bitfield PIT_TFLGn_TIF.
-#define BF_PIT_TFLGn_TIF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_TFLGn_TIF), uint32_t) & BM_PIT_TFLGn_TIF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TIF field to a new value.
-#define BW_PIT_TFLGn_TIF(n, v) (BITBAND_ACCESS32(HW_PIT_TFLGn_ADDR(n), BP_PIT_TFLGn_TIF) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_pit_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All PIT module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_pit
-{
- __IO hw_pit_mcr_t MCR; //!< [0x0] PIT Module Control Register
- uint8_t _reserved0[252];
- struct {
- __IO hw_pit_ldvaln_t LDVALn; //!< [0x100] Timer Load Value Register
- __I hw_pit_cvaln_t CVALn; //!< [0x104] Current Timer Value Register
- __IO hw_pit_tctrln_t TCTRLn; //!< [0x108] Timer Control Register
- __IO hw_pit_tflgn_t TFLGn; //!< [0x10C] Timer Flag Register
- } CHANNEL[4];
-} hw_pit_t;
-#pragma pack()
-
-//! @brief Macro to access all PIT registers.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_PIT</code>.
-#define HW_PIT (*(hw_pit_t *) REGS_PIT_BASE)
-#endif
-
-#endif // __HW_PIT_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_pmc.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,577 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_PMC_REGISTERS_H__
-#define __HW_PMC_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 PMC
- *
- * Power Management Controller
- *
- * Registers defined in this header file:
- * - HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
- * - HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
- * - HW_PMC_REGSC - Regulator Status And Control register
- *
- * - hw_pmc_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_PMC_BASE
-#define HW_PMC_INSTANCE_COUNT (1U) //!< Number of instances of the PMC module.
-#define REGS_PMC_BASE (0x4007D000U) //!< Base address for PMC.
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register (RW)
- *
- * Reset value: 0x10U
- *
- * This register contains status and control bits to support the low voltage
- * detect function. This register should be written during the reset initialization
- * program to set the desired controls even if the desired settings are the same
- * as the reset settings. While the device is in the very low power or low
- * leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect
- * systems that must have LVD always on, configure the Power Mode Protection
- * (PMPROT) register of the SMC module (SMC_PMPROT) to disallow any very low power or
- * low leakage modes from being enabled. See the device's data sheet for the
- * exact LVD trip voltages. The LVDV bits are reset solely on a POR Only event. The
- * register's other bits are reset on Chip Reset Not VLLS. For more information
- * about these reset types, refer to the Reset section details.
- */
-typedef union _hw_pmc_lvdsc1
-{
- uint8_t U;
- struct _hw_pmc_lvdsc1_bitfields
- {
- uint8_t LVDV : 2; //!< [1:0] Low-Voltage Detect Voltage Select
- uint8_t RESERVED0 : 2; //!< [3:2]
- uint8_t LVDRE : 1; //!< [4] Low-Voltage Detect Reset Enable
- uint8_t LVDIE : 1; //!< [5] Low-Voltage Detect Interrupt Enable
- uint8_t LVDACK : 1; //!< [6] Low-Voltage Detect Acknowledge
- uint8_t LVDF : 1; //!< [7] Low-Voltage Detect Flag
- } B;
-} hw_pmc_lvdsc1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire PMC_LVDSC1 register
- */
-//@{
-#define HW_PMC_LVDSC1_ADDR (REGS_PMC_BASE + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_PMC_LVDSC1 (*(__IO hw_pmc_lvdsc1_t *) HW_PMC_LVDSC1_ADDR)
-#define HW_PMC_LVDSC1_RD() (HW_PMC_LVDSC1.U)
-#define HW_PMC_LVDSC1_WR(v) (HW_PMC_LVDSC1.U = (v))
-#define HW_PMC_LVDSC1_SET(v) (HW_PMC_LVDSC1_WR(HW_PMC_LVDSC1_RD() | (v)))
-#define HW_PMC_LVDSC1_CLR(v) (HW_PMC_LVDSC1_WR(HW_PMC_LVDSC1_RD() & ~(v)))
-#define HW_PMC_LVDSC1_TOG(v) (HW_PMC_LVDSC1_WR(HW_PMC_LVDSC1_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual PMC_LVDSC1 bitfields
- */
-
-/*!
- * @name Register PMC_LVDSC1, field LVDV[1:0] (RW)
- *
- * Selects the LVD trip point voltage (V LVD ).
- *
- * Values:
- * - 00 - Low trip point selected (V LVD = V LVDL )
- * - 01 - High trip point selected (V LVD = V LVDH )
- * - 10 - Reserved
- * - 11 - Reserved
- */
-//@{
-#define BP_PMC_LVDSC1_LVDV (0U) //!< Bit position for PMC_LVDSC1_LVDV.
-#define BM_PMC_LVDSC1_LVDV (0x03U) //!< Bit mask for PMC_LVDSC1_LVDV.
-#define BS_PMC_LVDSC1_LVDV (2U) //!< Bit field size in bits for PMC_LVDSC1_LVDV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PMC_LVDSC1_LVDV field.
-#define BR_PMC_LVDSC1_LVDV (HW_PMC_LVDSC1.B.LVDV)
-#endif
-
-//! @brief Format value for bitfield PMC_LVDSC1_LVDV.
-#define BF_PMC_LVDSC1_LVDV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC1_LVDV), uint8_t) & BM_PMC_LVDSC1_LVDV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LVDV field to a new value.
-#define BW_PMC_LVDSC1_LVDV(v) (HW_PMC_LVDSC1_WR((HW_PMC_LVDSC1_RD() & ~BM_PMC_LVDSC1_LVDV) | BF_PMC_LVDSC1_LVDV(v)))
-#endif
-//@}
-
-/*!
- * @name Register PMC_LVDSC1, field LVDRE[4] (RW)
- *
- * This write-once bit enables LVDF events to generate a hardware reset.
- * Additional writes are ignored.
- *
- * Values:
- * - 0 - LVDF does not generate hardware resets
- * - 1 - Force an MCU reset when LVDF = 1
- */
-//@{
-#define BP_PMC_LVDSC1_LVDRE (4U) //!< Bit position for PMC_LVDSC1_LVDRE.
-#define BM_PMC_LVDSC1_LVDRE (0x10U) //!< Bit mask for PMC_LVDSC1_LVDRE.
-#define BS_PMC_LVDSC1_LVDRE (1U) //!< Bit field size in bits for PMC_LVDSC1_LVDRE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PMC_LVDSC1_LVDRE field.
-#define BR_PMC_LVDSC1_LVDRE (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDRE))
-#endif
-
-//! @brief Format value for bitfield PMC_LVDSC1_LVDRE.
-#define BF_PMC_LVDSC1_LVDRE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC1_LVDRE), uint8_t) & BM_PMC_LVDSC1_LVDRE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LVDRE field to a new value.
-#define BW_PMC_LVDSC1_LVDRE(v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDRE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register PMC_LVDSC1, field LVDIE[5] (RW)
- *
- * Enables hardware interrupt requests for LVDF.
- *
- * Values:
- * - 0 - Hardware interrupt disabled (use polling)
- * - 1 - Request a hardware interrupt when LVDF = 1
- */
-//@{
-#define BP_PMC_LVDSC1_LVDIE (5U) //!< Bit position for PMC_LVDSC1_LVDIE.
-#define BM_PMC_LVDSC1_LVDIE (0x20U) //!< Bit mask for PMC_LVDSC1_LVDIE.
-#define BS_PMC_LVDSC1_LVDIE (1U) //!< Bit field size in bits for PMC_LVDSC1_LVDIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PMC_LVDSC1_LVDIE field.
-#define BR_PMC_LVDSC1_LVDIE (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDIE))
-#endif
-
-//! @brief Format value for bitfield PMC_LVDSC1_LVDIE.
-#define BF_PMC_LVDSC1_LVDIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC1_LVDIE), uint8_t) & BM_PMC_LVDSC1_LVDIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LVDIE field to a new value.
-#define BW_PMC_LVDSC1_LVDIE(v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register PMC_LVDSC1, field LVDACK[6] (WORZ)
- *
- * This write-only field is used to acknowledge low voltage detection errors.
- * Write 1 to clear LVDF. Reads always return 0.
- */
-//@{
-#define BP_PMC_LVDSC1_LVDACK (6U) //!< Bit position for PMC_LVDSC1_LVDACK.
-#define BM_PMC_LVDSC1_LVDACK (0x40U) //!< Bit mask for PMC_LVDSC1_LVDACK.
-#define BS_PMC_LVDSC1_LVDACK (1U) //!< Bit field size in bits for PMC_LVDSC1_LVDACK.
-
-//! @brief Format value for bitfield PMC_LVDSC1_LVDACK.
-#define BF_PMC_LVDSC1_LVDACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC1_LVDACK), uint8_t) & BM_PMC_LVDSC1_LVDACK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LVDACK field to a new value.
-#define BW_PMC_LVDSC1_LVDACK(v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDACK) = (v))
-#endif
-//@}
-
-/*!
- * @name Register PMC_LVDSC1, field LVDF[7] (RO)
- *
- * This read-only status field indicates a low-voltage detect event.
- *
- * Values:
- * - 0 - Low-voltage event not detected
- * - 1 - Low-voltage event detected
- */
-//@{
-#define BP_PMC_LVDSC1_LVDF (7U) //!< Bit position for PMC_LVDSC1_LVDF.
-#define BM_PMC_LVDSC1_LVDF (0x80U) //!< Bit mask for PMC_LVDSC1_LVDF.
-#define BS_PMC_LVDSC1_LVDF (1U) //!< Bit field size in bits for PMC_LVDSC1_LVDF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PMC_LVDSC1_LVDF field.
-#define BR_PMC_LVDSC1_LVDF (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDF))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register (RW)
- *
- * Reset value: 0x00U
- *
- * This register contains status and control bits to support the low voltage
- * warning function. While the device is in the very low power or low leakage modes,
- * the LVD system is disabled regardless of LVDSC2 settings. See the device's
- * data sheet for the exact LVD trip voltages. The LVW trip voltages depend on LVWV
- * and LVDV. LVWV is reset solely on a POR Only event. The other fields of the
- * register are reset on Chip Reset Not VLLS. For more information about these
- * reset types, refer to the Reset section details.
- */
-typedef union _hw_pmc_lvdsc2
-{
- uint8_t U;
- struct _hw_pmc_lvdsc2_bitfields
- {
- uint8_t LVWV : 2; //!< [1:0] Low-Voltage Warning Voltage Select
- uint8_t RESERVED0 : 3; //!< [4:2]
- uint8_t LVWIE : 1; //!< [5] Low-Voltage Warning Interrupt Enable
- uint8_t LVWACK : 1; //!< [6] Low-Voltage Warning Acknowledge
- uint8_t LVWF : 1; //!< [7] Low-Voltage Warning Flag
- } B;
-} hw_pmc_lvdsc2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire PMC_LVDSC2 register
- */
-//@{
-#define HW_PMC_LVDSC2_ADDR (REGS_PMC_BASE + 0x1U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_PMC_LVDSC2 (*(__IO hw_pmc_lvdsc2_t *) HW_PMC_LVDSC2_ADDR)
-#define HW_PMC_LVDSC2_RD() (HW_PMC_LVDSC2.U)
-#define HW_PMC_LVDSC2_WR(v) (HW_PMC_LVDSC2.U = (v))
-#define HW_PMC_LVDSC2_SET(v) (HW_PMC_LVDSC2_WR(HW_PMC_LVDSC2_RD() | (v)))
-#define HW_PMC_LVDSC2_CLR(v) (HW_PMC_LVDSC2_WR(HW_PMC_LVDSC2_RD() & ~(v)))
-#define HW_PMC_LVDSC2_TOG(v) (HW_PMC_LVDSC2_WR(HW_PMC_LVDSC2_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual PMC_LVDSC2 bitfields
- */
-
-/*!
- * @name Register PMC_LVDSC2, field LVWV[1:0] (RW)
- *
- * Selects the LVW trip point voltage (VLVW). The actual voltage for the warning
- * depends on LVDSC1[LVDV].
- *
- * Values:
- * - 00 - Low trip point selected (VLVW = VLVW1)
- * - 01 - Mid 1 trip point selected (VLVW = VLVW2)
- * - 10 - Mid 2 trip point selected (VLVW = VLVW3)
- * - 11 - High trip point selected (VLVW = VLVW4)
- */
-//@{
-#define BP_PMC_LVDSC2_LVWV (0U) //!< Bit position for PMC_LVDSC2_LVWV.
-#define BM_PMC_LVDSC2_LVWV (0x03U) //!< Bit mask for PMC_LVDSC2_LVWV.
-#define BS_PMC_LVDSC2_LVWV (2U) //!< Bit field size in bits for PMC_LVDSC2_LVWV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PMC_LVDSC2_LVWV field.
-#define BR_PMC_LVDSC2_LVWV (HW_PMC_LVDSC2.B.LVWV)
-#endif
-
-//! @brief Format value for bitfield PMC_LVDSC2_LVWV.
-#define BF_PMC_LVDSC2_LVWV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC2_LVWV), uint8_t) & BM_PMC_LVDSC2_LVWV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LVWV field to a new value.
-#define BW_PMC_LVDSC2_LVWV(v) (HW_PMC_LVDSC2_WR((HW_PMC_LVDSC2_RD() & ~BM_PMC_LVDSC2_LVWV) | BF_PMC_LVDSC2_LVWV(v)))
-#endif
-//@}
-
-/*!
- * @name Register PMC_LVDSC2, field LVWIE[5] (RW)
- *
- * Enables hardware interrupt requests for LVWF.
- *
- * Values:
- * - 0 - Hardware interrupt disabled (use polling)
- * - 1 - Request a hardware interrupt when LVWF = 1
- */
-//@{
-#define BP_PMC_LVDSC2_LVWIE (5U) //!< Bit position for PMC_LVDSC2_LVWIE.
-#define BM_PMC_LVDSC2_LVWIE (0x20U) //!< Bit mask for PMC_LVDSC2_LVWIE.
-#define BS_PMC_LVDSC2_LVWIE (1U) //!< Bit field size in bits for PMC_LVDSC2_LVWIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PMC_LVDSC2_LVWIE field.
-#define BR_PMC_LVDSC2_LVWIE (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR, BP_PMC_LVDSC2_LVWIE))
-#endif
-
-//! @brief Format value for bitfield PMC_LVDSC2_LVWIE.
-#define BF_PMC_LVDSC2_LVWIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC2_LVWIE), uint8_t) & BM_PMC_LVDSC2_LVWIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LVWIE field to a new value.
-#define BW_PMC_LVDSC2_LVWIE(v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR, BP_PMC_LVDSC2_LVWIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register PMC_LVDSC2, field LVWACK[6] (WORZ)
- *
- * This write-only field is used to acknowledge low voltage warning errors.
- * Write 1 to clear LVWF. Reads always return 0.
- */
-//@{
-#define BP_PMC_LVDSC2_LVWACK (6U) //!< Bit position for PMC_LVDSC2_LVWACK.
-#define BM_PMC_LVDSC2_LVWACK (0x40U) //!< Bit mask for PMC_LVDSC2_LVWACK.
-#define BS_PMC_LVDSC2_LVWACK (1U) //!< Bit field size in bits for PMC_LVDSC2_LVWACK.
-
-//! @brief Format value for bitfield PMC_LVDSC2_LVWACK.
-#define BF_PMC_LVDSC2_LVWACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC2_LVWACK), uint8_t) & BM_PMC_LVDSC2_LVWACK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LVWACK field to a new value.
-#define BW_PMC_LVDSC2_LVWACK(v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR, BP_PMC_LVDSC2_LVWACK) = (v))
-#endif
-//@}
-
-/*!
- * @name Register PMC_LVDSC2, field LVWF[7] (RO)
- *
- * This read-only status field indicates a low-voltage warning event. LVWF is
- * set when VSupply transitions below the trip point, or after reset and VSupply is
- * already below VLVW. LVWF may be 1 after power-on reset, therefore, to use LVW
- * interrupt function, before enabling LVWIE, LVWF must be cleared by writing
- * LVWACK first.
- *
- * Values:
- * - 0 - Low-voltage warning event not detected
- * - 1 - Low-voltage warning event detected
- */
-//@{
-#define BP_PMC_LVDSC2_LVWF (7U) //!< Bit position for PMC_LVDSC2_LVWF.
-#define BM_PMC_LVDSC2_LVWF (0x80U) //!< Bit mask for PMC_LVDSC2_LVWF.
-#define BS_PMC_LVDSC2_LVWF (1U) //!< Bit field size in bits for PMC_LVDSC2_LVWF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PMC_LVDSC2_LVWF field.
-#define BR_PMC_LVDSC2_LVWF (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR, BP_PMC_LVDSC2_LVWF))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_PMC_REGSC - Regulator Status And Control register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_PMC_REGSC - Regulator Status And Control register (RW)
- *
- * Reset value: 0x04U
- *
- * The PMC contains an internal voltage regulator. The voltage regulator design
- * uses a bandgap reference that is also available through a buffer as input to
- * certain internal peripherals, such as the CMP and ADC. The internal regulator
- * provides a status bit (REGONS) indicating the regulator is in run regulation.
- * This register is reset on Chip Reset Not VLLS and by reset types that trigger
- * Chip Reset not VLLS. See the Reset section details for more information.
- */
-typedef union _hw_pmc_regsc
-{
- uint8_t U;
- struct _hw_pmc_regsc_bitfields
- {
- uint8_t BGBE : 1; //!< [0] Bandgap Buffer Enable
- uint8_t RESERVED0 : 1; //!< [1]
- uint8_t REGONS : 1; //!< [2] Regulator In Run Regulation Status
- uint8_t ACKISO : 1; //!< [3] Acknowledge Isolation
- uint8_t BGEN : 1; //!< [4] Bandgap Enable In VLPx Operation
- uint8_t RESERVED1 : 3; //!< [7:5]
- } B;
-} hw_pmc_regsc_t;
-#endif
-
-/*!
- * @name Constants and macros for entire PMC_REGSC register
- */
-//@{
-#define HW_PMC_REGSC_ADDR (REGS_PMC_BASE + 0x2U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_PMC_REGSC (*(__IO hw_pmc_regsc_t *) HW_PMC_REGSC_ADDR)
-#define HW_PMC_REGSC_RD() (HW_PMC_REGSC.U)
-#define HW_PMC_REGSC_WR(v) (HW_PMC_REGSC.U = (v))
-#define HW_PMC_REGSC_SET(v) (HW_PMC_REGSC_WR(HW_PMC_REGSC_RD() | (v)))
-#define HW_PMC_REGSC_CLR(v) (HW_PMC_REGSC_WR(HW_PMC_REGSC_RD() & ~(v)))
-#define HW_PMC_REGSC_TOG(v) (HW_PMC_REGSC_WR(HW_PMC_REGSC_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual PMC_REGSC bitfields
- */
-
-/*!
- * @name Register PMC_REGSC, field BGBE[0] (RW)
- *
- * Enables the bandgap buffer.
- *
- * Values:
- * - 0 - Bandgap buffer not enabled
- * - 1 - Bandgap buffer enabled
- */
-//@{
-#define BP_PMC_REGSC_BGBE (0U) //!< Bit position for PMC_REGSC_BGBE.
-#define BM_PMC_REGSC_BGBE (0x01U) //!< Bit mask for PMC_REGSC_BGBE.
-#define BS_PMC_REGSC_BGBE (1U) //!< Bit field size in bits for PMC_REGSC_BGBE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PMC_REGSC_BGBE field.
-#define BR_PMC_REGSC_BGBE (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_BGBE))
-#endif
-
-//! @brief Format value for bitfield PMC_REGSC_BGBE.
-#define BF_PMC_REGSC_BGBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_REGSC_BGBE), uint8_t) & BM_PMC_REGSC_BGBE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BGBE field to a new value.
-#define BW_PMC_REGSC_BGBE(v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_BGBE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register PMC_REGSC, field REGONS[2] (RO)
- *
- * This read-only field provides the current status of the internal voltage
- * regulator.
- *
- * Values:
- * - 0 - Regulator is in stop regulation or in transition to/from it
- * - 1 - Regulator is in run regulation
- */
-//@{
-#define BP_PMC_REGSC_REGONS (2U) //!< Bit position for PMC_REGSC_REGONS.
-#define BM_PMC_REGSC_REGONS (0x04U) //!< Bit mask for PMC_REGSC_REGONS.
-#define BS_PMC_REGSC_REGONS (1U) //!< Bit field size in bits for PMC_REGSC_REGONS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PMC_REGSC_REGONS field.
-#define BR_PMC_REGSC_REGONS (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_REGONS))
-#endif
-//@}
-
-/*!
- * @name Register PMC_REGSC, field ACKISO[3] (W1C)
- *
- * Reading this field indicates whether certain peripherals and the I/O pads are
- * in a latched state as a result of having been in a VLLS mode. Writing 1 to
- * this field when it is set releases the I/O pads and certain peripherals to their
- * normal run mode state. After recovering from a VLLS mode, user should restore
- * chip configuration before clearing ACKISO. In particular, pin configuration
- * for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from
- * being falsely set when ACKISO is cleared.
- *
- * Values:
- * - 0 - Peripherals and I/O pads are in normal run state.
- * - 1 - Certain peripherals and I/O pads are in an isolated and latched state.
- */
-//@{
-#define BP_PMC_REGSC_ACKISO (3U) //!< Bit position for PMC_REGSC_ACKISO.
-#define BM_PMC_REGSC_ACKISO (0x08U) //!< Bit mask for PMC_REGSC_ACKISO.
-#define BS_PMC_REGSC_ACKISO (1U) //!< Bit field size in bits for PMC_REGSC_ACKISO.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PMC_REGSC_ACKISO field.
-#define BR_PMC_REGSC_ACKISO (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_ACKISO))
-#endif
-
-//! @brief Format value for bitfield PMC_REGSC_ACKISO.
-#define BF_PMC_REGSC_ACKISO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_REGSC_ACKISO), uint8_t) & BM_PMC_REGSC_ACKISO)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ACKISO field to a new value.
-#define BW_PMC_REGSC_ACKISO(v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_ACKISO) = (v))
-#endif
-//@}
-
-/*!
- * @name Register PMC_REGSC, field BGEN[4] (RW)
- *
- * BGEN controls whether the bandgap is enabled in lower power modes of
- * operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage
- * reference in low power modes of operation, set BGEN to continue to enable the
- * bandgap operation. When the bandgap voltage reference is not needed in low
- * power modes, clear BGEN to avoid excess power consumption.
- *
- * Values:
- * - 0 - Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
- * - 1 - Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
- */
-//@{
-#define BP_PMC_REGSC_BGEN (4U) //!< Bit position for PMC_REGSC_BGEN.
-#define BM_PMC_REGSC_BGEN (0x10U) //!< Bit mask for PMC_REGSC_BGEN.
-#define BS_PMC_REGSC_BGEN (1U) //!< Bit field size in bits for PMC_REGSC_BGEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PMC_REGSC_BGEN field.
-#define BR_PMC_REGSC_BGEN (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_BGEN))
-#endif
-
-//! @brief Format value for bitfield PMC_REGSC_BGEN.
-#define BF_PMC_REGSC_BGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_REGSC_BGEN), uint8_t) & BM_PMC_REGSC_BGEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BGEN field to a new value.
-#define BW_PMC_REGSC_BGEN(v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_BGEN) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_pmc_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All PMC module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_pmc
-{
- __IO hw_pmc_lvdsc1_t LVDSC1; //!< [0x0] Low Voltage Detect Status And Control 1 register
- __IO hw_pmc_lvdsc2_t LVDSC2; //!< [0x1] Low Voltage Detect Status And Control 2 register
- __IO hw_pmc_regsc_t REGSC; //!< [0x2] Regulator Status And Control register
-} hw_pmc_t;
-#pragma pack()
-
-//! @brief Macro to access all PMC registers.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_PMC</code>.
-#define HW_PMC (*(hw_pmc_t *) REGS_PMC_BASE)
-#endif
-
-#endif // __HW_PMC_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_port.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,957 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_PORT_REGISTERS_H__
-#define __HW_PORT_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 PORT
- *
- * Pin Control and Interrupts
- *
- * Registers defined in this header file:
- * - HW_PORT_PCRn - Pin Control Register n
- * - HW_PORT_GPCLR - Global Pin Control Low Register
- * - HW_PORT_GPCHR - Global Pin Control High Register
- * - HW_PORT_ISFR - Interrupt Status Flag Register
- * - HW_PORT_DFER - Digital Filter Enable Register
- * - HW_PORT_DFCR - Digital Filter Clock Register
- * - HW_PORT_DFWR - Digital Filter Width Register
- *
- * - hw_port_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_PORT_BASE
-#define HW_PORT_INSTANCE_COUNT (5U) //!< Number of instances of the PORT module.
-#define HW_PORTA (0U) //!< Instance number for PORTA.
-#define HW_PORTB (1U) //!< Instance number for PORTB.
-#define HW_PORTC (2U) //!< Instance number for PORTC.
-#define HW_PORTD (3U) //!< Instance number for PORTD.
-#define HW_PORTE (4U) //!< Instance number for PORTE.
-#define REGS_PORTA_BASE (0x40049000U) //!< Base address for PORTA.
-#define REGS_PORTB_BASE (0x4004A000U) //!< Base address for PORTB.
-#define REGS_PORTC_BASE (0x4004B000U) //!< Base address for PORTC.
-#define REGS_PORTD_BASE (0x4004C000U) //!< Base address for PORTD.
-#define REGS_PORTE_BASE (0x4004D000U) //!< Base address for PORTE.
-
-//! @brief Table of base addresses for PORT instances.
-static const uint32_t __g_regs_PORT_base_addresses[] = {
- REGS_PORTA_BASE,
- REGS_PORTB_BASE,
- REGS_PORTC_BASE,
- REGS_PORTD_BASE,
- REGS_PORTE_BASE,
- };
-
-//! @brief Get the base address of PORT by instance number.
-//! @param x PORT instance number, from 0 through 4.
-#define REGS_PORT_BASE(x) (__g_regs_PORT_base_addresses[(x)])
-
-//! @brief Get the instance number given a base address.
-//! @param b Base address for an instance of PORT.
-#define REGS_PORT_INSTANCE(b) ((b) == REGS_PORTA_BASE ? HW_PORTA : (b) == REGS_PORTB_BASE ? HW_PORTB : (b) == REGS_PORTC_BASE ? HW_PORTC : (b) == REGS_PORTD_BASE ? HW_PORTD : (b) == REGS_PORTE_BASE ? HW_PORTE : 0)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_PORT_PCRn - Pin Control Register n
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_PORT_PCRn - Pin Control Register n (RW)
- *
- * Reset value: 0x00000742U
- *
- * See the Signal Multiplexing and Pin Assignment chapter for the reset value of
- * this device. See the GPIO Configuration section for details on the available
- * functions for each pin. Do not modify pin configuration registers associated
- * with pins not available in your selected package. All unbonded pins not
- * available in your package will default to DISABLE state for lowest power consumption.
- */
-typedef union _hw_port_pcrn
-{
- uint32_t U;
- struct _hw_port_pcrn_bitfields
- {
- uint32_t PS : 1; //!< [0] Pull Select
- uint32_t PE : 1; //!< [1] Pull Enable
- uint32_t SRE : 1; //!< [2] Slew Rate Enable
- uint32_t RESERVED0 : 1; //!< [3]
- uint32_t PFE : 1; //!< [4] Passive Filter Enable
- uint32_t ODE : 1; //!< [5] Open Drain Enable
- uint32_t DSE : 1; //!< [6] Drive Strength Enable
- uint32_t RESERVED1 : 1; //!< [7]
- uint32_t MUX : 3; //!< [10:8] Pin Mux Control
- uint32_t RESERVED2 : 4; //!< [14:11]
- uint32_t LK : 1; //!< [15] Lock Register
- uint32_t IRQC : 4; //!< [19:16] Interrupt Configuration
- uint32_t RESERVED3 : 4; //!< [23:20]
- uint32_t ISF : 1; //!< [24] Interrupt Status Flag
- uint32_t RESERVED4 : 7; //!< [31:25]
- } B;
-} hw_port_pcrn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire PORT_PCRn register
- */
-//@{
-#define HW_PORT_PCRn_COUNT (32U)
-
-#define HW_PORT_PCRn_ADDR(x, n) (REGS_PORT_BASE(x) + 0x0U + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_PORT_PCRn(x, n) (*(__IO hw_port_pcrn_t *) HW_PORT_PCRn_ADDR(x, n))
-#define HW_PORT_PCRn_RD(x, n) (HW_PORT_PCRn(x, n).U)
-#define HW_PORT_PCRn_WR(x, n, v) (HW_PORT_PCRn(x, n).U = (v))
-#define HW_PORT_PCRn_SET(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) | (v)))
-#define HW_PORT_PCRn_CLR(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) & ~(v)))
-#define HW_PORT_PCRn_TOG(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual PORT_PCRn bitfields
- */
-
-/*!
- * @name Register PORT_PCRn, field PS[0] (RW)
- *
- * Pull configuration is valid in all digital pin muxing modes.
- *
- * Values:
- * - 0 - Internal pulldown resistor is enabled on the corresponding pin, if the
- * corresponding PE field is set.
- * - 1 - Internal pullup resistor is enabled on the corresponding pin, if the
- * corresponding PE field is set.
- */
-//@{
-#define BP_PORT_PCRn_PS (0U) //!< Bit position for PORT_PCRn_PS.
-#define BM_PORT_PCRn_PS (0x00000001U) //!< Bit mask for PORT_PCRn_PS.
-#define BS_PORT_PCRn_PS (1U) //!< Bit field size in bits for PORT_PCRn_PS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PORT_PCRn_PS field.
-#define BR_PORT_PCRn_PS(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS))
-#endif
-
-//! @brief Format value for bitfield PORT_PCRn_PS.
-#define BF_PORT_PCRn_PS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_PS), uint32_t) & BM_PORT_PCRn_PS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PS field to a new value.
-#define BW_PORT_PCRn_PS(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register PORT_PCRn, field PE[1] (RW)
- *
- * Pull configuration is valid in all digital pin muxing modes.
- *
- * Values:
- * - 0 - Internal pullup or pulldown resistor is not enabled on the
- * corresponding pin.
- * - 1 - Internal pullup or pulldown resistor is enabled on the corresponding
- * pin, if the pin is configured as a digital input.
- */
-//@{
-#define BP_PORT_PCRn_PE (1U) //!< Bit position for PORT_PCRn_PE.
-#define BM_PORT_PCRn_PE (0x00000002U) //!< Bit mask for PORT_PCRn_PE.
-#define BS_PORT_PCRn_PE (1U) //!< Bit field size in bits for PORT_PCRn_PE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PORT_PCRn_PE field.
-#define BR_PORT_PCRn_PE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE))
-#endif
-
-//! @brief Format value for bitfield PORT_PCRn_PE.
-#define BF_PORT_PCRn_PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_PE), uint32_t) & BM_PORT_PCRn_PE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PE field to a new value.
-#define BW_PORT_PCRn_PE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register PORT_PCRn, field SRE[2] (RW)
- *
- * Slew rate configuration is valid in all digital pin muxing modes.
- *
- * Values:
- * - 0 - Fast slew rate is configured on the corresponding pin, if the pin is
- * configured as a digital output.
- * - 1 - Slow slew rate is configured on the corresponding pin, if the pin is
- * configured as a digital output.
- */
-//@{
-#define BP_PORT_PCRn_SRE (2U) //!< Bit position for PORT_PCRn_SRE.
-#define BM_PORT_PCRn_SRE (0x00000004U) //!< Bit mask for PORT_PCRn_SRE.
-#define BS_PORT_PCRn_SRE (1U) //!< Bit field size in bits for PORT_PCRn_SRE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PORT_PCRn_SRE field.
-#define BR_PORT_PCRn_SRE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE))
-#endif
-
-//! @brief Format value for bitfield PORT_PCRn_SRE.
-#define BF_PORT_PCRn_SRE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_SRE), uint32_t) & BM_PORT_PCRn_SRE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SRE field to a new value.
-#define BW_PORT_PCRn_SRE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register PORT_PCRn, field PFE[4] (RW)
- *
- * Passive filter configuration is valid in all digital pin muxing modes.
- *
- * Values:
- * - 0 - Passive input filter is disabled on the corresponding pin.
- * - 1 - Passive input filter is enabled on the corresponding pin, if the pin is
- * configured as a digital input. Refer to the device data sheet for filter
- * characteristics.
- */
-//@{
-#define BP_PORT_PCRn_PFE (4U) //!< Bit position for PORT_PCRn_PFE.
-#define BM_PORT_PCRn_PFE (0x00000010U) //!< Bit mask for PORT_PCRn_PFE.
-#define BS_PORT_PCRn_PFE (1U) //!< Bit field size in bits for PORT_PCRn_PFE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PORT_PCRn_PFE field.
-#define BR_PORT_PCRn_PFE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE))
-#endif
-
-//! @brief Format value for bitfield PORT_PCRn_PFE.
-#define BF_PORT_PCRn_PFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_PFE), uint32_t) & BM_PORT_PCRn_PFE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PFE field to a new value.
-#define BW_PORT_PCRn_PFE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register PORT_PCRn, field ODE[5] (RW)
- *
- * Open drain configuration is valid in all digital pin muxing modes.
- *
- * Values:
- * - 0 - Open drain output is disabled on the corresponding pin.
- * - 1 - Open drain output is enabled on the corresponding pin, if the pin is
- * configured as a digital output.
- */
-//@{
-#define BP_PORT_PCRn_ODE (5U) //!< Bit position for PORT_PCRn_ODE.
-#define BM_PORT_PCRn_ODE (0x00000020U) //!< Bit mask for PORT_PCRn_ODE.
-#define BS_PORT_PCRn_ODE (1U) //!< Bit field size in bits for PORT_PCRn_ODE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PORT_PCRn_ODE field.
-#define BR_PORT_PCRn_ODE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE))
-#endif
-
-//! @brief Format value for bitfield PORT_PCRn_ODE.
-#define BF_PORT_PCRn_ODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_ODE), uint32_t) & BM_PORT_PCRn_ODE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ODE field to a new value.
-#define BW_PORT_PCRn_ODE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register PORT_PCRn, field DSE[6] (RW)
- *
- * Drive strength configuration is valid in all digital pin muxing modes.
- *
- * Values:
- * - 0 - Low drive strength is configured on the corresponding pin, if pin is
- * configured as a digital output.
- * - 1 - High drive strength is configured on the corresponding pin, if pin is
- * configured as a digital output.
- */
-//@{
-#define BP_PORT_PCRn_DSE (6U) //!< Bit position for PORT_PCRn_DSE.
-#define BM_PORT_PCRn_DSE (0x00000040U) //!< Bit mask for PORT_PCRn_DSE.
-#define BS_PORT_PCRn_DSE (1U) //!< Bit field size in bits for PORT_PCRn_DSE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PORT_PCRn_DSE field.
-#define BR_PORT_PCRn_DSE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE))
-#endif
-
-//! @brief Format value for bitfield PORT_PCRn_DSE.
-#define BF_PORT_PCRn_DSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_DSE), uint32_t) & BM_PORT_PCRn_DSE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DSE field to a new value.
-#define BW_PORT_PCRn_DSE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register PORT_PCRn, field MUX[10:8] (RW)
- *
- * Not all pins support all pin muxing slots. Unimplemented pin muxing slots are
- * reserved and may result in configuring the pin for a different pin muxing
- * slot. The corresponding pin is configured in the following pin muxing slot as
- * follows:
- *
- * Values:
- * - 000 - Pin disabled (analog).
- * - 001 - Alternative 1 (GPIO).
- * - 010 - Alternative 2 (chip-specific).
- * - 011 - Alternative 3 (chip-specific).
- * - 100 - Alternative 4 (chip-specific).
- * - 101 - Alternative 5 (chip-specific).
- * - 110 - Alternative 6 (chip-specific).
- * - 111 - Alternative 7 (chip-specific).
- */
-//@{
-#define BP_PORT_PCRn_MUX (8U) //!< Bit position for PORT_PCRn_MUX.
-#define BM_PORT_PCRn_MUX (0x00000700U) //!< Bit mask for PORT_PCRn_MUX.
-#define BS_PORT_PCRn_MUX (3U) //!< Bit field size in bits for PORT_PCRn_MUX.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PORT_PCRn_MUX field.
-#define BR_PORT_PCRn_MUX(x, n) (HW_PORT_PCRn(x, n).B.MUX)
-#endif
-
-//! @brief Format value for bitfield PORT_PCRn_MUX.
-#define BF_PORT_PCRn_MUX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_MUX), uint32_t) & BM_PORT_PCRn_MUX)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MUX field to a new value.
-#define BW_PORT_PCRn_MUX(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_MUX) | BF_PORT_PCRn_MUX(v)))
-#endif
-//@}
-
-/*!
- * @name Register PORT_PCRn, field LK[15] (RW)
- *
- * Values:
- * - 0 - Pin Control Register fields [15:0] are not locked.
- * - 1 - Pin Control Register fields [15:0] are locked and cannot be updated
- * until the next system reset.
- */
-//@{
-#define BP_PORT_PCRn_LK (15U) //!< Bit position for PORT_PCRn_LK.
-#define BM_PORT_PCRn_LK (0x00008000U) //!< Bit mask for PORT_PCRn_LK.
-#define BS_PORT_PCRn_LK (1U) //!< Bit field size in bits for PORT_PCRn_LK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PORT_PCRn_LK field.
-#define BR_PORT_PCRn_LK(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK))
-#endif
-
-//! @brief Format value for bitfield PORT_PCRn_LK.
-#define BF_PORT_PCRn_LK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_LK), uint32_t) & BM_PORT_PCRn_LK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LK field to a new value.
-#define BW_PORT_PCRn_LK(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK) = (v))
-#endif
-//@}
-
-/*!
- * @name Register PORT_PCRn, field IRQC[19:16] (RW)
- *
- * The pin interrupt configuration is valid in all digital pin muxing modes. The
- * corresponding pin is configured to generate interrupt/DMA request as follows:
- *
- * Values:
- * - 0000 - Interrupt/DMA request disabled.
- * - 0001 - DMA request on rising edge.
- * - 0010 - DMA request on falling edge.
- * - 0011 - DMA request on either edge.
- * - 1000 - Interrupt when logic 0.
- * - 1001 - Interrupt on rising-edge.
- * - 1010 - Interrupt on falling-edge.
- * - 1011 - Interrupt on either edge.
- * - 1100 - Interrupt when logic 1.
- */
-//@{
-#define BP_PORT_PCRn_IRQC (16U) //!< Bit position for PORT_PCRn_IRQC.
-#define BM_PORT_PCRn_IRQC (0x000F0000U) //!< Bit mask for PORT_PCRn_IRQC.
-#define BS_PORT_PCRn_IRQC (4U) //!< Bit field size in bits for PORT_PCRn_IRQC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PORT_PCRn_IRQC field.
-#define BR_PORT_PCRn_IRQC(x, n) (HW_PORT_PCRn(x, n).B.IRQC)
-#endif
-
-//! @brief Format value for bitfield PORT_PCRn_IRQC.
-#define BF_PORT_PCRn_IRQC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_IRQC), uint32_t) & BM_PORT_PCRn_IRQC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IRQC field to a new value.
-#define BW_PORT_PCRn_IRQC(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_IRQC) | BF_PORT_PCRn_IRQC(v)))
-#endif
-//@}
-
-/*!
- * @name Register PORT_PCRn, field ISF[24] (W1C)
- *
- * The pin interrupt configuration is valid in all digital pin muxing modes.
- *
- * Values:
- * - 0 - Configured interrupt is not detected.
- * - 1 - Configured interrupt is detected. If the pin is configured to generate
- * a DMA request, then the corresponding flag will be cleared automatically
- * at the completion of the requested DMA transfer. Otherwise, the flag
- * remains set until a logic 1 is written to the flag. If the pin is configured for
- * a level sensitive interrupt and the pin remains asserted, then the flag
- * is set again immediately after it is cleared.
- */
-//@{
-#define BP_PORT_PCRn_ISF (24U) //!< Bit position for PORT_PCRn_ISF.
-#define BM_PORT_PCRn_ISF (0x01000000U) //!< Bit mask for PORT_PCRn_ISF.
-#define BS_PORT_PCRn_ISF (1U) //!< Bit field size in bits for PORT_PCRn_ISF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PORT_PCRn_ISF field.
-#define BR_PORT_PCRn_ISF(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF))
-#endif
-
-//! @brief Format value for bitfield PORT_PCRn_ISF.
-#define BF_PORT_PCRn_ISF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_ISF), uint32_t) & BM_PORT_PCRn_ISF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ISF field to a new value.
-#define BW_PORT_PCRn_ISF(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_PORT_GPCLR - Global Pin Control Low Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_PORT_GPCLR - Global Pin Control Low Register (WORZ)
- *
- * Reset value: 0x00000000U
- *
- * Only 32-bit writes are supported to this register.
- */
-typedef union _hw_port_gpclr
-{
- uint32_t U;
- struct _hw_port_gpclr_bitfields
- {
- uint32_t GPWD : 16; //!< [15:0] Global Pin Write Data
- uint32_t GPWE : 16; //!< [31:16] Global Pin Write Enable
- } B;
-} hw_port_gpclr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire PORT_GPCLR register
- */
-//@{
-#define HW_PORT_GPCLR_ADDR(x) (REGS_PORT_BASE(x) + 0x80U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_PORT_GPCLR(x) (*(__O hw_port_gpclr_t *) HW_PORT_GPCLR_ADDR(x))
-#define HW_PORT_GPCLR_RD(x) (HW_PORT_GPCLR(x).U)
-#define HW_PORT_GPCLR_WR(x, v) (HW_PORT_GPCLR(x).U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual PORT_GPCLR bitfields
- */
-
-/*!
- * @name Register PORT_GPCLR, field GPWD[15:0] (WORZ)
- *
- * Write value that is written to all Pin Control Registers bits [15:0] that are
- * selected by GPWE.
- */
-//@{
-#define BP_PORT_GPCLR_GPWD (0U) //!< Bit position for PORT_GPCLR_GPWD.
-#define BM_PORT_GPCLR_GPWD (0x0000FFFFU) //!< Bit mask for PORT_GPCLR_GPWD.
-#define BS_PORT_GPCLR_GPWD (16U) //!< Bit field size in bits for PORT_GPCLR_GPWD.
-
-//! @brief Format value for bitfield PORT_GPCLR_GPWD.
-#define BF_PORT_GPCLR_GPWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_GPCLR_GPWD), uint32_t) & BM_PORT_GPCLR_GPWD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the GPWD field to a new value.
-#define BW_PORT_GPCLR_GPWD(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWD) | BF_PORT_GPCLR_GPWD(v)))
-#endif
-//@}
-
-/*!
- * @name Register PORT_GPCLR, field GPWE[31:16] (WORZ)
- *
- * Selects which Pin Control Registers (15 through 0) bits [15:0] update with
- * the value in GPWD. If a selected Pin Control Register is locked then the write
- * to that register is ignored.
- *
- * Values:
- * - 0 - Corresponding Pin Control Register is not updated with the value in
- * GPWD.
- * - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
- */
-//@{
-#define BP_PORT_GPCLR_GPWE (16U) //!< Bit position for PORT_GPCLR_GPWE.
-#define BM_PORT_GPCLR_GPWE (0xFFFF0000U) //!< Bit mask for PORT_GPCLR_GPWE.
-#define BS_PORT_GPCLR_GPWE (16U) //!< Bit field size in bits for PORT_GPCLR_GPWE.
-
-//! @brief Format value for bitfield PORT_GPCLR_GPWE.
-#define BF_PORT_GPCLR_GPWE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_GPCLR_GPWE), uint32_t) & BM_PORT_GPCLR_GPWE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the GPWE field to a new value.
-#define BW_PORT_GPCLR_GPWE(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWE) | BF_PORT_GPCLR_GPWE(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_PORT_GPCHR - Global Pin Control High Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_PORT_GPCHR - Global Pin Control High Register (WORZ)
- *
- * Reset value: 0x00000000U
- *
- * Only 32-bit writes are supported to this register.
- */
-typedef union _hw_port_gpchr
-{
- uint32_t U;
- struct _hw_port_gpchr_bitfields
- {
- uint32_t GPWD : 16; //!< [15:0] Global Pin Write Data
- uint32_t GPWE : 16; //!< [31:16] Global Pin Write Enable
- } B;
-} hw_port_gpchr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire PORT_GPCHR register
- */
-//@{
-#define HW_PORT_GPCHR_ADDR(x) (REGS_PORT_BASE(x) + 0x84U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_PORT_GPCHR(x) (*(__O hw_port_gpchr_t *) HW_PORT_GPCHR_ADDR(x))
-#define HW_PORT_GPCHR_RD(x) (HW_PORT_GPCHR(x).U)
-#define HW_PORT_GPCHR_WR(x, v) (HW_PORT_GPCHR(x).U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual PORT_GPCHR bitfields
- */
-
-/*!
- * @name Register PORT_GPCHR, field GPWD[15:0] (WORZ)
- *
- * Write value that is written to all Pin Control Registers bits [15:0] that are
- * selected by GPWE.
- */
-//@{
-#define BP_PORT_GPCHR_GPWD (0U) //!< Bit position for PORT_GPCHR_GPWD.
-#define BM_PORT_GPCHR_GPWD (0x0000FFFFU) //!< Bit mask for PORT_GPCHR_GPWD.
-#define BS_PORT_GPCHR_GPWD (16U) //!< Bit field size in bits for PORT_GPCHR_GPWD.
-
-//! @brief Format value for bitfield PORT_GPCHR_GPWD.
-#define BF_PORT_GPCHR_GPWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_GPCHR_GPWD), uint32_t) & BM_PORT_GPCHR_GPWD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the GPWD field to a new value.
-#define BW_PORT_GPCHR_GPWD(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWD) | BF_PORT_GPCHR_GPWD(v)))
-#endif
-//@}
-
-/*!
- * @name Register PORT_GPCHR, field GPWE[31:16] (WORZ)
- *
- * Selects which Pin Control Registers (31 through 16) bits [15:0] update with
- * the value in GPWD. If a selected Pin Control Register is locked then the write
- * to that register is ignored.
- *
- * Values:
- * - 0 - Corresponding Pin Control Register is not updated with the value in
- * GPWD.
- * - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
- */
-//@{
-#define BP_PORT_GPCHR_GPWE (16U) //!< Bit position for PORT_GPCHR_GPWE.
-#define BM_PORT_GPCHR_GPWE (0xFFFF0000U) //!< Bit mask for PORT_GPCHR_GPWE.
-#define BS_PORT_GPCHR_GPWE (16U) //!< Bit field size in bits for PORT_GPCHR_GPWE.
-
-//! @brief Format value for bitfield PORT_GPCHR_GPWE.
-#define BF_PORT_GPCHR_GPWE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_GPCHR_GPWE), uint32_t) & BM_PORT_GPCHR_GPWE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the GPWE field to a new value.
-#define BW_PORT_GPCHR_GPWE(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWE) | BF_PORT_GPCHR_GPWE(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_PORT_ISFR - Interrupt Status Flag Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_PORT_ISFR - Interrupt Status Flag Register (W1C)
- *
- * Reset value: 0x00000000U
- *
- * The pin interrupt configuration is valid in all digital pin muxing modes. The
- * Interrupt Status Flag for each pin is also visible in the corresponding Pin
- * Control Register, and each flag can be cleared in either location.
- */
-typedef union _hw_port_isfr
-{
- uint32_t U;
- struct _hw_port_isfr_bitfields
- {
- uint32_t ISF : 32; //!< [31:0] Interrupt Status Flag
- } B;
-} hw_port_isfr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire PORT_ISFR register
- */
-//@{
-#define HW_PORT_ISFR_ADDR(x) (REGS_PORT_BASE(x) + 0xA0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_PORT_ISFR(x) (*(__IO hw_port_isfr_t *) HW_PORT_ISFR_ADDR(x))
-#define HW_PORT_ISFR_RD(x) (HW_PORT_ISFR(x).U)
-#define HW_PORT_ISFR_WR(x, v) (HW_PORT_ISFR(x).U = (v))
-#define HW_PORT_ISFR_SET(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) | (v)))
-#define HW_PORT_ISFR_CLR(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) & ~(v)))
-#define HW_PORT_ISFR_TOG(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual PORT_ISFR bitfields
- */
-
-/*!
- * @name Register PORT_ISFR, field ISF[31:0] (W1C)
- *
- * Each bit in the field indicates the detection of the configured interrupt of
- * the same number as the field.
- *
- * Values:
- * - 0 - Configured interrupt is not detected.
- * - 1 - Configured interrupt is detected. If the pin is configured to generate
- * a DMA request, then the corresponding flag will be cleared automatically
- * at the completion of the requested DMA transfer. Otherwise, the flag
- * remains set until a logic 1 is written to the flag. If the pin is configured for
- * a level sensitive interrupt and the pin remains asserted, then the flag
- * is set again immediately after it is cleared.
- */
-//@{
-#define BP_PORT_ISFR_ISF (0U) //!< Bit position for PORT_ISFR_ISF.
-#define BM_PORT_ISFR_ISF (0xFFFFFFFFU) //!< Bit mask for PORT_ISFR_ISF.
-#define BS_PORT_ISFR_ISF (32U) //!< Bit field size in bits for PORT_ISFR_ISF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PORT_ISFR_ISF field.
-#define BR_PORT_ISFR_ISF(x) (HW_PORT_ISFR(x).U)
-#endif
-
-//! @brief Format value for bitfield PORT_ISFR_ISF.
-#define BF_PORT_ISFR_ISF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_ISFR_ISF), uint32_t) & BM_PORT_ISFR_ISF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ISF field to a new value.
-#define BW_PORT_ISFR_ISF(x, v) (HW_PORT_ISFR_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_PORT_DFER - Digital Filter Enable Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_PORT_DFER - Digital Filter Enable Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * The corresponding bit is read only for pins that do not support a digital
- * filter. Refer to the Chapter of Signal Multiplexing and Signal Descriptions for
- * the pins that support digital filter. The digital filter configuration is valid
- * in all digital pin muxing modes.
- */
-typedef union _hw_port_dfer
-{
- uint32_t U;
- struct _hw_port_dfer_bitfields
- {
- uint32_t DFE : 32; //!< [31:0] Digital Filter Enable
- } B;
-} hw_port_dfer_t;
-#endif
-
-/*!
- * @name Constants and macros for entire PORT_DFER register
- */
-//@{
-#define HW_PORT_DFER_ADDR(x) (REGS_PORT_BASE(x) + 0xC0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_PORT_DFER(x) (*(__IO hw_port_dfer_t *) HW_PORT_DFER_ADDR(x))
-#define HW_PORT_DFER_RD(x) (HW_PORT_DFER(x).U)
-#define HW_PORT_DFER_WR(x, v) (HW_PORT_DFER(x).U = (v))
-#define HW_PORT_DFER_SET(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) | (v)))
-#define HW_PORT_DFER_CLR(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) & ~(v)))
-#define HW_PORT_DFER_TOG(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual PORT_DFER bitfields
- */
-
-/*!
- * @name Register PORT_DFER, field DFE[31:0] (RW)
- *
- * The digital filter configuration is valid in all digital pin muxing modes.
- * The output of each digital filter is reset to zero at system reset and whenever
- * the digital filter is disabled. Each bit in the field enables the digital
- * filter of the same number as the field.
- *
- * Values:
- * - 0 - Digital filter is disabled on the corresponding pin and output of the
- * digital filter is reset to zero.
- * - 1 - Digital filter is enabled on the corresponding pin, if the pin is
- * configured as a digital input.
- */
-//@{
-#define BP_PORT_DFER_DFE (0U) //!< Bit position for PORT_DFER_DFE.
-#define BM_PORT_DFER_DFE (0xFFFFFFFFU) //!< Bit mask for PORT_DFER_DFE.
-#define BS_PORT_DFER_DFE (32U) //!< Bit field size in bits for PORT_DFER_DFE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PORT_DFER_DFE field.
-#define BR_PORT_DFER_DFE(x) (HW_PORT_DFER(x).U)
-#endif
-
-//! @brief Format value for bitfield PORT_DFER_DFE.
-#define BF_PORT_DFER_DFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_DFER_DFE), uint32_t) & BM_PORT_DFER_DFE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DFE field to a new value.
-#define BW_PORT_DFER_DFE(x, v) (HW_PORT_DFER_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_PORT_DFCR - Digital Filter Clock Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_PORT_DFCR - Digital Filter Clock Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register is read only for ports that do not support a digital filter.
- * The digital filter configuration is valid in all digital pin muxing modes.
- */
-typedef union _hw_port_dfcr
-{
- uint32_t U;
- struct _hw_port_dfcr_bitfields
- {
- uint32_t CS : 1; //!< [0] Clock Source
- uint32_t RESERVED0 : 31; //!< [31:1]
- } B;
-} hw_port_dfcr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire PORT_DFCR register
- */
-//@{
-#define HW_PORT_DFCR_ADDR(x) (REGS_PORT_BASE(x) + 0xC4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_PORT_DFCR(x) (*(__IO hw_port_dfcr_t *) HW_PORT_DFCR_ADDR(x))
-#define HW_PORT_DFCR_RD(x) (HW_PORT_DFCR(x).U)
-#define HW_PORT_DFCR_WR(x, v) (HW_PORT_DFCR(x).U = (v))
-#define HW_PORT_DFCR_SET(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) | (v)))
-#define HW_PORT_DFCR_CLR(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) & ~(v)))
-#define HW_PORT_DFCR_TOG(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual PORT_DFCR bitfields
- */
-
-/*!
- * @name Register PORT_DFCR, field CS[0] (RW)
- *
- * The digital filter configuration is valid in all digital pin muxing modes.
- * Configures the clock source for the digital input filters. Changing the filter
- * clock source must be done only when all digital filters are disabled.
- *
- * Values:
- * - 0 - Digital filters are clocked by the bus clock.
- * - 1 - Digital filters are clocked by the 1 kHz LPO clock.
- */
-//@{
-#define BP_PORT_DFCR_CS (0U) //!< Bit position for PORT_DFCR_CS.
-#define BM_PORT_DFCR_CS (0x00000001U) //!< Bit mask for PORT_DFCR_CS.
-#define BS_PORT_DFCR_CS (1U) //!< Bit field size in bits for PORT_DFCR_CS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PORT_DFCR_CS field.
-#define BR_PORT_DFCR_CS(x) (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS))
-#endif
-
-//! @brief Format value for bitfield PORT_DFCR_CS.
-#define BF_PORT_DFCR_CS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_DFCR_CS), uint32_t) & BM_PORT_DFCR_CS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CS field to a new value.
-#define BW_PORT_DFCR_CS(x, v) (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_PORT_DFWR - Digital Filter Width Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_PORT_DFWR - Digital Filter Width Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register is read only for ports that do not support a digital filter.
- * The digital filter configuration is valid in all digital pin muxing modes.
- */
-typedef union _hw_port_dfwr
-{
- uint32_t U;
- struct _hw_port_dfwr_bitfields
- {
- uint32_t FILT : 5; //!< [4:0] Filter Length
- uint32_t RESERVED0 : 27; //!< [31:5]
- } B;
-} hw_port_dfwr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire PORT_DFWR register
- */
-//@{
-#define HW_PORT_DFWR_ADDR(x) (REGS_PORT_BASE(x) + 0xC8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_PORT_DFWR(x) (*(__IO hw_port_dfwr_t *) HW_PORT_DFWR_ADDR(x))
-#define HW_PORT_DFWR_RD(x) (HW_PORT_DFWR(x).U)
-#define HW_PORT_DFWR_WR(x, v) (HW_PORT_DFWR(x).U = (v))
-#define HW_PORT_DFWR_SET(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) | (v)))
-#define HW_PORT_DFWR_CLR(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) & ~(v)))
-#define HW_PORT_DFWR_TOG(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual PORT_DFWR bitfields
- */
-
-/*!
- * @name Register PORT_DFWR, field FILT[4:0] (RW)
- *
- * The digital filter configuration is valid in all digital pin muxing modes.
- * Configures the maximum size of the glitches, in clock cycles, that the digital
- * filter absorbs for the enabled digital filters. Glitches that are longer than
- * this register setting will pass through the digital filter, and glitches that
- * are equal to or less than this register setting are filtered. Changing the
- * filter length must be done only after all filters are disabled.
- */
-//@{
-#define BP_PORT_DFWR_FILT (0U) //!< Bit position for PORT_DFWR_FILT.
-#define BM_PORT_DFWR_FILT (0x0000001FU) //!< Bit mask for PORT_DFWR_FILT.
-#define BS_PORT_DFWR_FILT (5U) //!< Bit field size in bits for PORT_DFWR_FILT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the PORT_DFWR_FILT field.
-#define BR_PORT_DFWR_FILT(x) (HW_PORT_DFWR(x).B.FILT)
-#endif
-
-//! @brief Format value for bitfield PORT_DFWR_FILT.
-#define BF_PORT_DFWR_FILT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_DFWR_FILT), uint32_t) & BM_PORT_DFWR_FILT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FILT field to a new value.
-#define BW_PORT_DFWR_FILT(x, v) (HW_PORT_DFWR_WR(x, (HW_PORT_DFWR_RD(x) & ~BM_PORT_DFWR_FILT) | BF_PORT_DFWR_FILT(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_port_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All PORT module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_port
-{
- __IO hw_port_pcrn_t PCRn[32]; //!< [0x0] Pin Control Register n
- __O hw_port_gpclr_t GPCLR; //!< [0x80] Global Pin Control Low Register
- __O hw_port_gpchr_t GPCHR; //!< [0x84] Global Pin Control High Register
- uint8_t _reserved0[24];
- __IO hw_port_isfr_t ISFR; //!< [0xA0] Interrupt Status Flag Register
- uint8_t _reserved1[28];
- __IO hw_port_dfer_t DFER; //!< [0xC0] Digital Filter Enable Register
- __IO hw_port_dfcr_t DFCR; //!< [0xC4] Digital Filter Clock Register
- __IO hw_port_dfwr_t DFWR; //!< [0xC8] Digital Filter Width Register
-} hw_port_t;
-#pragma pack()
-
-//! @brief Macro to access all PORT registers.
-//! @param x PORT instance number.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_PORT(0)</code>.
-#define HW_PORT(x) (*(hw_port_t *) REGS_PORT_BASE(x))
-#endif
-
-#endif // __HW_PORT_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_rcm.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,730 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_RCM_REGISTERS_H__
-#define __HW_RCM_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 RCM
- *
- * Reset Control Module
- *
- * Registers defined in this header file:
- * - HW_RCM_SRS0 - System Reset Status Register 0
- * - HW_RCM_SRS1 - System Reset Status Register 1
- * - HW_RCM_RPFC - Reset Pin Filter Control register
- * - HW_RCM_RPFW - Reset Pin Filter Width register
- * - HW_RCM_MR - Mode Register
- *
- * - hw_rcm_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_RCM_BASE
-#define HW_RCM_INSTANCE_COUNT (1U) //!< Number of instances of the RCM module.
-#define REGS_RCM_BASE (0x4007F000U) //!< Base address for RCM.
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_RCM_SRS0 - System Reset Status Register 0
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_RCM_SRS0 - System Reset Status Register 0 (RO)
- *
- * Reset value: 0x82U
- *
- * This register includes read-only status flags to indicate the source of the
- * most recent reset. The reset state of these bits depends on what caused the MCU
- * to reset. The reset value of this register depends on the reset source: POR
- * (including LVD) - 0x82 LVD (without POR) - 0x02 VLLS mode wakeup due to RESET
- * pin assertion - 0x41 VLLS mode wakeup due to other wakeup sources - 0x01 Other
- * reset - a bit is set if its corresponding reset source caused the reset
- */
-typedef union _hw_rcm_srs0
-{
- uint8_t U;
- struct _hw_rcm_srs0_bitfields
- {
- uint8_t WAKEUP : 1; //!< [0] Low Leakage Wakeup Reset
- uint8_t LVD : 1; //!< [1] Low-Voltage Detect Reset
- uint8_t LOC : 1; //!< [2] Loss-of-Clock Reset
- uint8_t LOL : 1; //!< [3] Loss-of-Lock Reset
- uint8_t RESERVED0 : 1; //!< [4]
- uint8_t WDOGb : 1; //!< [5] Watchdog
- uint8_t PIN : 1; //!< [6] External Reset Pin
- uint8_t POR : 1; //!< [7] Power-On Reset
- } B;
-} hw_rcm_srs0_t;
-#endif
-
-/*!
- * @name Constants and macros for entire RCM_SRS0 register
- */
-//@{
-#define HW_RCM_SRS0_ADDR (REGS_RCM_BASE + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_RCM_SRS0 (*(__I hw_rcm_srs0_t *) HW_RCM_SRS0_ADDR)
-#define HW_RCM_SRS0_RD() (HW_RCM_SRS0.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual RCM_SRS0 bitfields
- */
-
-/*!
- * @name Register RCM_SRS0, field WAKEUP[0] (RO)
- *
- * Indicates a reset has been caused by an enabled LLWU module wakeup source
- * while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only
- * wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx
- * mode causes a reset. This bit is cleared by any reset except WAKEUP.
- *
- * Values:
- * - 0 - Reset not caused by LLWU module wakeup source
- * - 1 - Reset caused by LLWU module wakeup source
- */
-//@{
-#define BP_RCM_SRS0_WAKEUP (0U) //!< Bit position for RCM_SRS0_WAKEUP.
-#define BM_RCM_SRS0_WAKEUP (0x01U) //!< Bit mask for RCM_SRS0_WAKEUP.
-#define BS_RCM_SRS0_WAKEUP (1U) //!< Bit field size in bits for RCM_SRS0_WAKEUP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RCM_SRS0_WAKEUP field.
-#define BR_RCM_SRS0_WAKEUP (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_WAKEUP))
-#endif
-//@}
-
-/*!
- * @name Register RCM_SRS0, field LVD[1] (RO)
- *
- * If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage,
- * an LVD reset occurs. This field is also set by POR.
- *
- * Values:
- * - 0 - Reset not caused by LVD trip or POR
- * - 1 - Reset caused by LVD trip or POR
- */
-//@{
-#define BP_RCM_SRS0_LVD (1U) //!< Bit position for RCM_SRS0_LVD.
-#define BM_RCM_SRS0_LVD (0x02U) //!< Bit mask for RCM_SRS0_LVD.
-#define BS_RCM_SRS0_LVD (1U) //!< Bit field size in bits for RCM_SRS0_LVD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RCM_SRS0_LVD field.
-#define BR_RCM_SRS0_LVD (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_LVD))
-#endif
-//@}
-
-/*!
- * @name Register RCM_SRS0, field LOC[2] (RO)
- *
- * Indicates a reset has been caused by a loss of external clock. The MCG clock
- * monitor must be enabled for a loss of clock to be detected. Refer to the
- * detailed MCG description for information on enabling the clock monitor.
- *
- * Values:
- * - 0 - Reset not caused by a loss of external clock.
- * - 1 - Reset caused by a loss of external clock.
- */
-//@{
-#define BP_RCM_SRS0_LOC (2U) //!< Bit position for RCM_SRS0_LOC.
-#define BM_RCM_SRS0_LOC (0x04U) //!< Bit mask for RCM_SRS0_LOC.
-#define BS_RCM_SRS0_LOC (1U) //!< Bit field size in bits for RCM_SRS0_LOC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RCM_SRS0_LOC field.
-#define BR_RCM_SRS0_LOC (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_LOC))
-#endif
-//@}
-
-/*!
- * @name Register RCM_SRS0, field LOL[3] (RO)
- *
- * Indicates a reset has been caused by a loss of lock in the MCG PLL. See the
- * MCG description for information on the loss-of-clock event.
- *
- * Values:
- * - 0 - Reset not caused by a loss of lock in the PLL
- * - 1 - Reset caused by a loss of lock in the PLL
- */
-//@{
-#define BP_RCM_SRS0_LOL (3U) //!< Bit position for RCM_SRS0_LOL.
-#define BM_RCM_SRS0_LOL (0x08U) //!< Bit mask for RCM_SRS0_LOL.
-#define BS_RCM_SRS0_LOL (1U) //!< Bit field size in bits for RCM_SRS0_LOL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RCM_SRS0_LOL field.
-#define BR_RCM_SRS0_LOL (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_LOL))
-#endif
-//@}
-
-/*!
- * @name Register RCM_SRS0, field WDOG[5] (RO)
- *
- * Indicates a reset has been caused by the watchdog timer Computer Operating
- * Properly (COP) timing out. This reset source can be blocked by disabling the COP
- * watchdog: write 00 to SIM_COPCTRL[COPT].
- *
- * Values:
- * - 0 - Reset not caused by watchdog timeout
- * - 1 - Reset caused by watchdog timeout
- */
-//@{
-#define BP_RCM_SRS0_WDOG (5U) //!< Bit position for RCM_SRS0_WDOG.
-#define BM_RCM_SRS0_WDOG (0x20U) //!< Bit mask for RCM_SRS0_WDOG.
-#define BS_RCM_SRS0_WDOG (1U) //!< Bit field size in bits for RCM_SRS0_WDOG.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RCM_SRS0_WDOG field.
-#define BR_RCM_SRS0_WDOG (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_WDOG))
-#endif
-//@}
-
-/*!
- * @name Register RCM_SRS0, field PIN[6] (RO)
- *
- * Indicates a reset has been caused by an active-low level on the external
- * RESET pin.
- *
- * Values:
- * - 0 - Reset not caused by external reset pin
- * - 1 - Reset caused by external reset pin
- */
-//@{
-#define BP_RCM_SRS0_PIN (6U) //!< Bit position for RCM_SRS0_PIN.
-#define BM_RCM_SRS0_PIN (0x40U) //!< Bit mask for RCM_SRS0_PIN.
-#define BS_RCM_SRS0_PIN (1U) //!< Bit field size in bits for RCM_SRS0_PIN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RCM_SRS0_PIN field.
-#define BR_RCM_SRS0_PIN (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_PIN))
-#endif
-//@}
-
-/*!
- * @name Register RCM_SRS0, field POR[7] (RO)
- *
- * Indicates a reset has been caused by the power-on detection logic. Because
- * the internal supply voltage was ramping up at the time, the low-voltage reset
- * (LVD) status bit is also set to indicate that the reset occurred while the
- * internal supply was below the LVD threshold.
- *
- * Values:
- * - 0 - Reset not caused by POR
- * - 1 - Reset caused by POR
- */
-//@{
-#define BP_RCM_SRS0_POR (7U) //!< Bit position for RCM_SRS0_POR.
-#define BM_RCM_SRS0_POR (0x80U) //!< Bit mask for RCM_SRS0_POR.
-#define BS_RCM_SRS0_POR (1U) //!< Bit field size in bits for RCM_SRS0_POR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RCM_SRS0_POR field.
-#define BR_RCM_SRS0_POR (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_POR))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_RCM_SRS1 - System Reset Status Register 1
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_RCM_SRS1 - System Reset Status Register 1 (RO)
- *
- * Reset value: 0x00U
- *
- * This register includes read-only status flags to indicate the source of the
- * most recent reset. The reset state of these bits depends on what caused the MCU
- * to reset. The reset value of this register depends on the reset source: POR
- * (including LVD) - 0x00 LVD (without POR) - 0x00 VLLS mode wakeup - 0x00 Other
- * reset - a bit is set if its corresponding reset source caused the reset
- */
-typedef union _hw_rcm_srs1
-{
- uint8_t U;
- struct _hw_rcm_srs1_bitfields
- {
- uint8_t JTAG : 1; //!< [0] JTAG Generated Reset
- uint8_t LOCKUP : 1; //!< [1] Core Lockup
- uint8_t SW : 1; //!< [2] Software
- uint8_t MDM_AP : 1; //!< [3] MDM-AP System Reset Request
- uint8_t EZPT : 1; //!< [4] EzPort Reset
- uint8_t SACKERR : 1; //!< [5] Stop Mode Acknowledge Error Reset
- uint8_t RESERVED0 : 2; //!< [7:6]
- } B;
-} hw_rcm_srs1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire RCM_SRS1 register
- */
-//@{
-#define HW_RCM_SRS1_ADDR (REGS_RCM_BASE + 0x1U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_RCM_SRS1 (*(__I hw_rcm_srs1_t *) HW_RCM_SRS1_ADDR)
-#define HW_RCM_SRS1_RD() (HW_RCM_SRS1.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual RCM_SRS1 bitfields
- */
-
-/*!
- * @name Register RCM_SRS1, field JTAG[0] (RO)
- *
- * Indicates a reset has been caused by JTAG selection of certain IR codes:
- * EZPORT, EXTEST, HIGHZ, and CLAMP.
- *
- * Values:
- * - 0 - Reset not caused by JTAG
- * - 1 - Reset caused by JTAG
- */
-//@{
-#define BP_RCM_SRS1_JTAG (0U) //!< Bit position for RCM_SRS1_JTAG.
-#define BM_RCM_SRS1_JTAG (0x01U) //!< Bit mask for RCM_SRS1_JTAG.
-#define BS_RCM_SRS1_JTAG (1U) //!< Bit field size in bits for RCM_SRS1_JTAG.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RCM_SRS1_JTAG field.
-#define BR_RCM_SRS1_JTAG (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_JTAG))
-#endif
-//@}
-
-/*!
- * @name Register RCM_SRS1, field LOCKUP[1] (RO)
- *
- * Indicates a reset has been caused by the ARM core indication of a LOCKUP
- * event.
- *
- * Values:
- * - 0 - Reset not caused by core LOCKUP event
- * - 1 - Reset caused by core LOCKUP event
- */
-//@{
-#define BP_RCM_SRS1_LOCKUP (1U) //!< Bit position for RCM_SRS1_LOCKUP.
-#define BM_RCM_SRS1_LOCKUP (0x02U) //!< Bit mask for RCM_SRS1_LOCKUP.
-#define BS_RCM_SRS1_LOCKUP (1U) //!< Bit field size in bits for RCM_SRS1_LOCKUP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RCM_SRS1_LOCKUP field.
-#define BR_RCM_SRS1_LOCKUP (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_LOCKUP))
-#endif
-//@}
-
-/*!
- * @name Register RCM_SRS1, field SW[2] (RO)
- *
- * Indicates a reset has been caused by software setting of SYSRESETREQ bit in
- * Application Interrupt and Reset Control Register in the ARM core.
- *
- * Values:
- * - 0 - Reset not caused by software setting of SYSRESETREQ bit
- * - 1 - Reset caused by software setting of SYSRESETREQ bit
- */
-//@{
-#define BP_RCM_SRS1_SW (2U) //!< Bit position for RCM_SRS1_SW.
-#define BM_RCM_SRS1_SW (0x04U) //!< Bit mask for RCM_SRS1_SW.
-#define BS_RCM_SRS1_SW (1U) //!< Bit field size in bits for RCM_SRS1_SW.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RCM_SRS1_SW field.
-#define BR_RCM_SRS1_SW (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_SW))
-#endif
-//@}
-
-/*!
- * @name Register RCM_SRS1, field MDM_AP[3] (RO)
- *
- * Indicates a reset has been caused by the host debugger system setting of the
- * System Reset Request bit in the MDM-AP Control Register.
- *
- * Values:
- * - 0 - Reset not caused by host debugger system setting of the System Reset
- * Request bit
- * - 1 - Reset caused by host debugger system setting of the System Reset
- * Request bit
- */
-//@{
-#define BP_RCM_SRS1_MDM_AP (3U) //!< Bit position for RCM_SRS1_MDM_AP.
-#define BM_RCM_SRS1_MDM_AP (0x08U) //!< Bit mask for RCM_SRS1_MDM_AP.
-#define BS_RCM_SRS1_MDM_AP (1U) //!< Bit field size in bits for RCM_SRS1_MDM_AP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RCM_SRS1_MDM_AP field.
-#define BR_RCM_SRS1_MDM_AP (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_MDM_AP))
-#endif
-//@}
-
-/*!
- * @name Register RCM_SRS1, field EZPT[4] (RO)
- *
- * Indicates a reset has been caused by EzPort receiving the RESET command while
- * the device is in EzPort mode.
- *
- * Values:
- * - 0 - Reset not caused by EzPort receiving the RESET command while the device
- * is in EzPort mode
- * - 1 - Reset caused by EzPort receiving the RESET command while the device is
- * in EzPort mode
- */
-//@{
-#define BP_RCM_SRS1_EZPT (4U) //!< Bit position for RCM_SRS1_EZPT.
-#define BM_RCM_SRS1_EZPT (0x10U) //!< Bit mask for RCM_SRS1_EZPT.
-#define BS_RCM_SRS1_EZPT (1U) //!< Bit field size in bits for RCM_SRS1_EZPT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RCM_SRS1_EZPT field.
-#define BR_RCM_SRS1_EZPT (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_EZPT))
-#endif
-//@}
-
-/*!
- * @name Register RCM_SRS1, field SACKERR[5] (RO)
- *
- * Indicates that after an attempt to enter Stop mode, a reset has been caused
- * by a failure of one or more peripherals to acknowledge within approximately one
- * second to enter stop mode.
- *
- * Values:
- * - 0 - Reset not caused by peripheral failure to acknowledge attempt to enter
- * stop mode
- * - 1 - Reset caused by peripheral failure to acknowledge attempt to enter stop
- * mode
- */
-//@{
-#define BP_RCM_SRS1_SACKERR (5U) //!< Bit position for RCM_SRS1_SACKERR.
-#define BM_RCM_SRS1_SACKERR (0x20U) //!< Bit mask for RCM_SRS1_SACKERR.
-#define BS_RCM_SRS1_SACKERR (1U) //!< Bit field size in bits for RCM_SRS1_SACKERR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RCM_SRS1_SACKERR field.
-#define BR_RCM_SRS1_SACKERR (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_SACKERR))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_RCM_RPFC - Reset Pin Filter Control register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_RCM_RPFC - Reset Pin Filter Control register (RW)
- *
- * Reset value: 0x00U
- *
- * The reset values of bits 2-0 are for Chip POR only. They are unaffected by
- * other reset types. The bus clock filter is reset when disabled or when entering
- * stop mode. The LPO filter is reset when disabled or when entering any low
- * leakage stop mode .
- */
-typedef union _hw_rcm_rpfc
-{
- uint8_t U;
- struct _hw_rcm_rpfc_bitfields
- {
- uint8_t RSTFLTSRW : 2; //!< [1:0] Reset Pin Filter Select in Run and
- //! Wait Modes
- uint8_t RSTFLTSS : 1; //!< [2] Reset Pin Filter Select in Stop Mode
- uint8_t RESERVED0 : 5; //!< [7:3]
- } B;
-} hw_rcm_rpfc_t;
-#endif
-
-/*!
- * @name Constants and macros for entire RCM_RPFC register
- */
-//@{
-#define HW_RCM_RPFC_ADDR (REGS_RCM_BASE + 0x4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_RCM_RPFC (*(__IO hw_rcm_rpfc_t *) HW_RCM_RPFC_ADDR)
-#define HW_RCM_RPFC_RD() (HW_RCM_RPFC.U)
-#define HW_RCM_RPFC_WR(v) (HW_RCM_RPFC.U = (v))
-#define HW_RCM_RPFC_SET(v) (HW_RCM_RPFC_WR(HW_RCM_RPFC_RD() | (v)))
-#define HW_RCM_RPFC_CLR(v) (HW_RCM_RPFC_WR(HW_RCM_RPFC_RD() & ~(v)))
-#define HW_RCM_RPFC_TOG(v) (HW_RCM_RPFC_WR(HW_RCM_RPFC_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual RCM_RPFC bitfields
- */
-
-/*!
- * @name Register RCM_RPFC, field RSTFLTSRW[1:0] (RW)
- *
- * Selects how the reset pin filter is enabled in run and wait modes.
- *
- * Values:
- * - 00 - All filtering disabled
- * - 01 - Bus clock filter enabled for normal operation
- * - 10 - LPO clock filter enabled for normal operation
- * - 11 - Reserved
- */
-//@{
-#define BP_RCM_RPFC_RSTFLTSRW (0U) //!< Bit position for RCM_RPFC_RSTFLTSRW.
-#define BM_RCM_RPFC_RSTFLTSRW (0x03U) //!< Bit mask for RCM_RPFC_RSTFLTSRW.
-#define BS_RCM_RPFC_RSTFLTSRW (2U) //!< Bit field size in bits for RCM_RPFC_RSTFLTSRW.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RCM_RPFC_RSTFLTSRW field.
-#define BR_RCM_RPFC_RSTFLTSRW (HW_RCM_RPFC.B.RSTFLTSRW)
-#endif
-
-//! @brief Format value for bitfield RCM_RPFC_RSTFLTSRW.
-#define BF_RCM_RPFC_RSTFLTSRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_RCM_RPFC_RSTFLTSRW), uint8_t) & BM_RCM_RPFC_RSTFLTSRW)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RSTFLTSRW field to a new value.
-#define BW_RCM_RPFC_RSTFLTSRW(v) (HW_RCM_RPFC_WR((HW_RCM_RPFC_RD() & ~BM_RCM_RPFC_RSTFLTSRW) | BF_RCM_RPFC_RSTFLTSRW(v)))
-#endif
-//@}
-
-/*!
- * @name Register RCM_RPFC, field RSTFLTSS[2] (RW)
- *
- * Selects how the reset pin filter is enabled in Stop and VLPS modes
- *
- * Values:
- * - 0 - All filtering disabled
- * - 1 - LPO clock filter enabled
- */
-//@{
-#define BP_RCM_RPFC_RSTFLTSS (2U) //!< Bit position for RCM_RPFC_RSTFLTSS.
-#define BM_RCM_RPFC_RSTFLTSS (0x04U) //!< Bit mask for RCM_RPFC_RSTFLTSS.
-#define BS_RCM_RPFC_RSTFLTSS (1U) //!< Bit field size in bits for RCM_RPFC_RSTFLTSS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RCM_RPFC_RSTFLTSS field.
-#define BR_RCM_RPFC_RSTFLTSS (BITBAND_ACCESS8(HW_RCM_RPFC_ADDR, BP_RCM_RPFC_RSTFLTSS))
-#endif
-
-//! @brief Format value for bitfield RCM_RPFC_RSTFLTSS.
-#define BF_RCM_RPFC_RSTFLTSS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_RCM_RPFC_RSTFLTSS), uint8_t) & BM_RCM_RPFC_RSTFLTSS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RSTFLTSS field to a new value.
-#define BW_RCM_RPFC_RSTFLTSS(v) (BITBAND_ACCESS8(HW_RCM_RPFC_ADDR, BP_RCM_RPFC_RSTFLTSS) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_RCM_RPFW - Reset Pin Filter Width register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_RCM_RPFW - Reset Pin Filter Width register (RW)
- *
- * Reset value: 0x00U
- *
- * The reset values of the bits in the RSTFLTSEL field are for Chip POR only.
- * They are unaffected by other reset types.
- */
-typedef union _hw_rcm_rpfw
-{
- uint8_t U;
- struct _hw_rcm_rpfw_bitfields
- {
- uint8_t RSTFLTSEL : 5; //!< [4:0] Reset Pin Filter Bus Clock Select
- uint8_t RESERVED0 : 3; //!< [7:5]
- } B;
-} hw_rcm_rpfw_t;
-#endif
-
-/*!
- * @name Constants and macros for entire RCM_RPFW register
- */
-//@{
-#define HW_RCM_RPFW_ADDR (REGS_RCM_BASE + 0x5U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_RCM_RPFW (*(__IO hw_rcm_rpfw_t *) HW_RCM_RPFW_ADDR)
-#define HW_RCM_RPFW_RD() (HW_RCM_RPFW.U)
-#define HW_RCM_RPFW_WR(v) (HW_RCM_RPFW.U = (v))
-#define HW_RCM_RPFW_SET(v) (HW_RCM_RPFW_WR(HW_RCM_RPFW_RD() | (v)))
-#define HW_RCM_RPFW_CLR(v) (HW_RCM_RPFW_WR(HW_RCM_RPFW_RD() & ~(v)))
-#define HW_RCM_RPFW_TOG(v) (HW_RCM_RPFW_WR(HW_RCM_RPFW_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual RCM_RPFW bitfields
- */
-
-/*!
- * @name Register RCM_RPFW, field RSTFLTSEL[4:0] (RW)
- *
- * Selects the reset pin bus clock filter width.
- *
- * Values:
- * - 00000 - Bus clock filter count is 1
- * - 00001 - Bus clock filter count is 2
- * - 00010 - Bus clock filter count is 3
- * - 00011 - Bus clock filter count is 4
- * - 00100 - Bus clock filter count is 5
- * - 00101 - Bus clock filter count is 6
- * - 00110 - Bus clock filter count is 7
- * - 00111 - Bus clock filter count is 8
- * - 01000 - Bus clock filter count is 9
- * - 01001 - Bus clock filter count is 10
- * - 01010 - Bus clock filter count is 11
- * - 01011 - Bus clock filter count is 12
- * - 01100 - Bus clock filter count is 13
- * - 01101 - Bus clock filter count is 14
- * - 01110 - Bus clock filter count is 15
- * - 01111 - Bus clock filter count is 16
- * - 10000 - Bus clock filter count is 17
- * - 10001 - Bus clock filter count is 18
- * - 10010 - Bus clock filter count is 19
- * - 10011 - Bus clock filter count is 20
- * - 10100 - Bus clock filter count is 21
- * - 10101 - Bus clock filter count is 22
- * - 10110 - Bus clock filter count is 23
- * - 10111 - Bus clock filter count is 24
- * - 11000 - Bus clock filter count is 25
- * - 11001 - Bus clock filter count is 26
- * - 11010 - Bus clock filter count is 27
- * - 11011 - Bus clock filter count is 28
- * - 11100 - Bus clock filter count is 29
- * - 11101 - Bus clock filter count is 30
- * - 11110 - Bus clock filter count is 31
- * - 11111 - Bus clock filter count is 32
- */
-//@{
-#define BP_RCM_RPFW_RSTFLTSEL (0U) //!< Bit position for RCM_RPFW_RSTFLTSEL.
-#define BM_RCM_RPFW_RSTFLTSEL (0x1FU) //!< Bit mask for RCM_RPFW_RSTFLTSEL.
-#define BS_RCM_RPFW_RSTFLTSEL (5U) //!< Bit field size in bits for RCM_RPFW_RSTFLTSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RCM_RPFW_RSTFLTSEL field.
-#define BR_RCM_RPFW_RSTFLTSEL (HW_RCM_RPFW.B.RSTFLTSEL)
-#endif
-
-//! @brief Format value for bitfield RCM_RPFW_RSTFLTSEL.
-#define BF_RCM_RPFW_RSTFLTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_RCM_RPFW_RSTFLTSEL), uint8_t) & BM_RCM_RPFW_RSTFLTSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RSTFLTSEL field to a new value.
-#define BW_RCM_RPFW_RSTFLTSEL(v) (HW_RCM_RPFW_WR((HW_RCM_RPFW_RD() & ~BM_RCM_RPFW_RSTFLTSEL) | BF_RCM_RPFW_RSTFLTSEL(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_RCM_MR - Mode Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_RCM_MR - Mode Register (RO)
- *
- * Reset value: 0x00U
- *
- * This register includes read-only status flags to indicate the state of the
- * mode pins during the last Chip Reset.
- */
-typedef union _hw_rcm_mr
-{
- uint8_t U;
- struct _hw_rcm_mr_bitfields
- {
- uint8_t RESERVED0 : 1; //!< [0]
- uint8_t EZP_MS : 1; //!< [1] EZP_MS_B pin state
- uint8_t RESERVED1 : 6; //!< [7:2]
- } B;
-} hw_rcm_mr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire RCM_MR register
- */
-//@{
-#define HW_RCM_MR_ADDR (REGS_RCM_BASE + 0x7U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_RCM_MR (*(__I hw_rcm_mr_t *) HW_RCM_MR_ADDR)
-#define HW_RCM_MR_RD() (HW_RCM_MR.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual RCM_MR bitfields
- */
-
-/*!
- * @name Register RCM_MR, field EZP_MS[1] (RO)
- *
- * Reflects the state of the EZP_MS pin during the last Chip Reset
- *
- * Values:
- * - 0 - Pin deasserted (logic 1)
- * - 1 - Pin asserted (logic 0)
- */
-//@{
-#define BP_RCM_MR_EZP_MS (1U) //!< Bit position for RCM_MR_EZP_MS.
-#define BM_RCM_MR_EZP_MS (0x02U) //!< Bit mask for RCM_MR_EZP_MS.
-#define BS_RCM_MR_EZP_MS (1U) //!< Bit field size in bits for RCM_MR_EZP_MS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RCM_MR_EZP_MS field.
-#define BR_RCM_MR_EZP_MS (BITBAND_ACCESS8(HW_RCM_MR_ADDR, BP_RCM_MR_EZP_MS))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_rcm_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All RCM module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_rcm
-{
- __I hw_rcm_srs0_t SRS0; //!< [0x0] System Reset Status Register 0
- __I hw_rcm_srs1_t SRS1; //!< [0x1] System Reset Status Register 1
- uint8_t _reserved0[2];
- __IO hw_rcm_rpfc_t RPFC; //!< [0x4] Reset Pin Filter Control register
- __IO hw_rcm_rpfw_t RPFW; //!< [0x5] Reset Pin Filter Width register
- uint8_t _reserved1[1];
- __I hw_rcm_mr_t MR; //!< [0x7] Mode Register
-} hw_rcm_t;
-#pragma pack()
-
-//! @brief Macro to access all RCM registers.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_RCM</code>.
-#define HW_RCM (*(hw_rcm_t *) REGS_RCM_BASE)
-#endif
-
-#endif // __HW_RCM_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_rfsys.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,210 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_RFSYS_REGISTERS_H__
-#define __HW_RFSYS_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 RFSYS
- *
- * System register file
- *
- * Registers defined in this header file:
- * - HW_RFSYS_REGn - Register file register
- *
- * - hw_rfsys_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_RFSYS_BASE
-#define HW_RFSYS_INSTANCE_COUNT (1U) //!< Number of instances of the RFSYS module.
-#define REGS_RFSYS_BASE (0x40041000U) //!< Base address for RFSYS.
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_RFSYS_REGn - Register file register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_RFSYS_REGn - Register file register (RW)
- *
- * Reset value: 0x00000000U
- *
- * Each register can be accessed as 8-, 16-, or 32-bits.
- */
-typedef union _hw_rfsys_regn
-{
- uint32_t U;
- struct _hw_rfsys_regn_bitfields
- {
- uint32_t LL : 8; //!< [7:0]
- uint32_t LH : 8; //!< [15:8]
- uint32_t HL : 8; //!< [23:16]
- uint32_t HH : 8; //!< [31:24]
- } B;
-} hw_rfsys_regn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire RFSYS_REGn register
- */
-//@{
-#define HW_RFSYS_REGn_COUNT (8U)
-
-#define HW_RFSYS_REGn_ADDR(n) (REGS_RFSYS_BASE + 0x0U + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_RFSYS_REGn(n) (*(__IO hw_rfsys_regn_t *) HW_RFSYS_REGn_ADDR(n))
-#define HW_RFSYS_REGn_RD(n) (HW_RFSYS_REGn(n).U)
-#define HW_RFSYS_REGn_WR(n, v) (HW_RFSYS_REGn(n).U = (v))
-#define HW_RFSYS_REGn_SET(n, v) (HW_RFSYS_REGn_WR(n, HW_RFSYS_REGn_RD(n) | (v)))
-#define HW_RFSYS_REGn_CLR(n, v) (HW_RFSYS_REGn_WR(n, HW_RFSYS_REGn_RD(n) & ~(v)))
-#define HW_RFSYS_REGn_TOG(n, v) (HW_RFSYS_REGn_WR(n, HW_RFSYS_REGn_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual RFSYS_REGn bitfields
- */
-
-/*!
- * @name Register RFSYS_REGn, field LL[7:0] (RW)
- *
- * Low lower byte
- */
-//@{
-#define BP_RFSYS_REGn_LL (0U) //!< Bit position for RFSYS_REGn_LL.
-#define BM_RFSYS_REGn_LL (0x000000FFU) //!< Bit mask for RFSYS_REGn_LL.
-#define BS_RFSYS_REGn_LL (8U) //!< Bit field size in bits for RFSYS_REGn_LL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RFSYS_REGn_LL field.
-#define BR_RFSYS_REGn_LL(n) (HW_RFSYS_REGn(n).B.LL)
-#endif
-
-//! @brief Format value for bitfield RFSYS_REGn_LL.
-#define BF_RFSYS_REGn_LL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFSYS_REGn_LL), uint32_t) & BM_RFSYS_REGn_LL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LL field to a new value.
-#define BW_RFSYS_REGn_LL(n, v) (HW_RFSYS_REGn_WR(n, (HW_RFSYS_REGn_RD(n) & ~BM_RFSYS_REGn_LL) | BF_RFSYS_REGn_LL(v)))
-#endif
-//@}
-
-/*!
- * @name Register RFSYS_REGn, field LH[15:8] (RW)
- *
- * Low higher byte
- */
-//@{
-#define BP_RFSYS_REGn_LH (8U) //!< Bit position for RFSYS_REGn_LH.
-#define BM_RFSYS_REGn_LH (0x0000FF00U) //!< Bit mask for RFSYS_REGn_LH.
-#define BS_RFSYS_REGn_LH (8U) //!< Bit field size in bits for RFSYS_REGn_LH.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RFSYS_REGn_LH field.
-#define BR_RFSYS_REGn_LH(n) (HW_RFSYS_REGn(n).B.LH)
-#endif
-
-//! @brief Format value for bitfield RFSYS_REGn_LH.
-#define BF_RFSYS_REGn_LH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFSYS_REGn_LH), uint32_t) & BM_RFSYS_REGn_LH)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LH field to a new value.
-#define BW_RFSYS_REGn_LH(n, v) (HW_RFSYS_REGn_WR(n, (HW_RFSYS_REGn_RD(n) & ~BM_RFSYS_REGn_LH) | BF_RFSYS_REGn_LH(v)))
-#endif
-//@}
-
-/*!
- * @name Register RFSYS_REGn, field HL[23:16] (RW)
- *
- * High lower byte
- */
-//@{
-#define BP_RFSYS_REGn_HL (16U) //!< Bit position for RFSYS_REGn_HL.
-#define BM_RFSYS_REGn_HL (0x00FF0000U) //!< Bit mask for RFSYS_REGn_HL.
-#define BS_RFSYS_REGn_HL (8U) //!< Bit field size in bits for RFSYS_REGn_HL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RFSYS_REGn_HL field.
-#define BR_RFSYS_REGn_HL(n) (HW_RFSYS_REGn(n).B.HL)
-#endif
-
-//! @brief Format value for bitfield RFSYS_REGn_HL.
-#define BF_RFSYS_REGn_HL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFSYS_REGn_HL), uint32_t) & BM_RFSYS_REGn_HL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the HL field to a new value.
-#define BW_RFSYS_REGn_HL(n, v) (HW_RFSYS_REGn_WR(n, (HW_RFSYS_REGn_RD(n) & ~BM_RFSYS_REGn_HL) | BF_RFSYS_REGn_HL(v)))
-#endif
-//@}
-
-/*!
- * @name Register RFSYS_REGn, field HH[31:24] (RW)
- *
- * High higher byte
- */
-//@{
-#define BP_RFSYS_REGn_HH (24U) //!< Bit position for RFSYS_REGn_HH.
-#define BM_RFSYS_REGn_HH (0xFF000000U) //!< Bit mask for RFSYS_REGn_HH.
-#define BS_RFSYS_REGn_HH (8U) //!< Bit field size in bits for RFSYS_REGn_HH.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RFSYS_REGn_HH field.
-#define BR_RFSYS_REGn_HH(n) (HW_RFSYS_REGn(n).B.HH)
-#endif
-
-//! @brief Format value for bitfield RFSYS_REGn_HH.
-#define BF_RFSYS_REGn_HH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFSYS_REGn_HH), uint32_t) & BM_RFSYS_REGn_HH)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the HH field to a new value.
-#define BW_RFSYS_REGn_HH(n, v) (HW_RFSYS_REGn_WR(n, (HW_RFSYS_REGn_RD(n) & ~BM_RFSYS_REGn_HH) | BF_RFSYS_REGn_HH(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_rfsys_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All RFSYS module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_rfsys
-{
- __IO hw_rfsys_regn_t REGn[8]; //!< [0x0] Register file register
-} hw_rfsys_t;
-#pragma pack()
-
-//! @brief Macro to access all RFSYS registers.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_RFSYS</code>.
-#define HW_RFSYS (*(hw_rfsys_t *) REGS_RFSYS_BASE)
-#endif
-
-#endif // __HW_RFSYS_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_rfvbat.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,210 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_RFVBAT_REGISTERS_H__
-#define __HW_RFVBAT_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 RFVBAT
- *
- * VBAT register file
- *
- * Registers defined in this header file:
- * - HW_RFVBAT_REGn - VBAT register file register
- *
- * - hw_rfvbat_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_RFVBAT_BASE
-#define HW_RFVBAT_INSTANCE_COUNT (1U) //!< Number of instances of the RFVBAT module.
-#define REGS_RFVBAT_BASE (0x4003E000U) //!< Base address for RFVBAT.
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_RFVBAT_REGn - VBAT register file register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_RFVBAT_REGn - VBAT register file register (RW)
- *
- * Reset value: 0x00000000U
- *
- * Each register can be accessed as 8-, 16-, or 32-bits.
- */
-typedef union _hw_rfvbat_regn
-{
- uint32_t U;
- struct _hw_rfvbat_regn_bitfields
- {
- uint32_t LL : 8; //!< [7:0]
- uint32_t LH : 8; //!< [15:8]
- uint32_t HL : 8; //!< [23:16]
- uint32_t HH : 8; //!< [31:24]
- } B;
-} hw_rfvbat_regn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire RFVBAT_REGn register
- */
-//@{
-#define HW_RFVBAT_REGn_COUNT (8U)
-
-#define HW_RFVBAT_REGn_ADDR(n) (REGS_RFVBAT_BASE + 0x0U + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_RFVBAT_REGn(n) (*(__IO hw_rfvbat_regn_t *) HW_RFVBAT_REGn_ADDR(n))
-#define HW_RFVBAT_REGn_RD(n) (HW_RFVBAT_REGn(n).U)
-#define HW_RFVBAT_REGn_WR(n, v) (HW_RFVBAT_REGn(n).U = (v))
-#define HW_RFVBAT_REGn_SET(n, v) (HW_RFVBAT_REGn_WR(n, HW_RFVBAT_REGn_RD(n) | (v)))
-#define HW_RFVBAT_REGn_CLR(n, v) (HW_RFVBAT_REGn_WR(n, HW_RFVBAT_REGn_RD(n) & ~(v)))
-#define HW_RFVBAT_REGn_TOG(n, v) (HW_RFVBAT_REGn_WR(n, HW_RFVBAT_REGn_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual RFVBAT_REGn bitfields
- */
-
-/*!
- * @name Register RFVBAT_REGn, field LL[7:0] (RW)
- *
- * Low lower byte
- */
-//@{
-#define BP_RFVBAT_REGn_LL (0U) //!< Bit position for RFVBAT_REGn_LL.
-#define BM_RFVBAT_REGn_LL (0x000000FFU) //!< Bit mask for RFVBAT_REGn_LL.
-#define BS_RFVBAT_REGn_LL (8U) //!< Bit field size in bits for RFVBAT_REGn_LL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RFVBAT_REGn_LL field.
-#define BR_RFVBAT_REGn_LL(n) (HW_RFVBAT_REGn(n).B.LL)
-#endif
-
-//! @brief Format value for bitfield RFVBAT_REGn_LL.
-#define BF_RFVBAT_REGn_LL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFVBAT_REGn_LL), uint32_t) & BM_RFVBAT_REGn_LL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LL field to a new value.
-#define BW_RFVBAT_REGn_LL(n, v) (HW_RFVBAT_REGn_WR(n, (HW_RFVBAT_REGn_RD(n) & ~BM_RFVBAT_REGn_LL) | BF_RFVBAT_REGn_LL(v)))
-#endif
-//@}
-
-/*!
- * @name Register RFVBAT_REGn, field LH[15:8] (RW)
- *
- * Low higher byte
- */
-//@{
-#define BP_RFVBAT_REGn_LH (8U) //!< Bit position for RFVBAT_REGn_LH.
-#define BM_RFVBAT_REGn_LH (0x0000FF00U) //!< Bit mask for RFVBAT_REGn_LH.
-#define BS_RFVBAT_REGn_LH (8U) //!< Bit field size in bits for RFVBAT_REGn_LH.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RFVBAT_REGn_LH field.
-#define BR_RFVBAT_REGn_LH(n) (HW_RFVBAT_REGn(n).B.LH)
-#endif
-
-//! @brief Format value for bitfield RFVBAT_REGn_LH.
-#define BF_RFVBAT_REGn_LH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFVBAT_REGn_LH), uint32_t) & BM_RFVBAT_REGn_LH)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LH field to a new value.
-#define BW_RFVBAT_REGn_LH(n, v) (HW_RFVBAT_REGn_WR(n, (HW_RFVBAT_REGn_RD(n) & ~BM_RFVBAT_REGn_LH) | BF_RFVBAT_REGn_LH(v)))
-#endif
-//@}
-
-/*!
- * @name Register RFVBAT_REGn, field HL[23:16] (RW)
- *
- * High lower byte
- */
-//@{
-#define BP_RFVBAT_REGn_HL (16U) //!< Bit position for RFVBAT_REGn_HL.
-#define BM_RFVBAT_REGn_HL (0x00FF0000U) //!< Bit mask for RFVBAT_REGn_HL.
-#define BS_RFVBAT_REGn_HL (8U) //!< Bit field size in bits for RFVBAT_REGn_HL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RFVBAT_REGn_HL field.
-#define BR_RFVBAT_REGn_HL(n) (HW_RFVBAT_REGn(n).B.HL)
-#endif
-
-//! @brief Format value for bitfield RFVBAT_REGn_HL.
-#define BF_RFVBAT_REGn_HL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFVBAT_REGn_HL), uint32_t) & BM_RFVBAT_REGn_HL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the HL field to a new value.
-#define BW_RFVBAT_REGn_HL(n, v) (HW_RFVBAT_REGn_WR(n, (HW_RFVBAT_REGn_RD(n) & ~BM_RFVBAT_REGn_HL) | BF_RFVBAT_REGn_HL(v)))
-#endif
-//@}
-
-/*!
- * @name Register RFVBAT_REGn, field HH[31:24] (RW)
- *
- * High higher byte
- */
-//@{
-#define BP_RFVBAT_REGn_HH (24U) //!< Bit position for RFVBAT_REGn_HH.
-#define BM_RFVBAT_REGn_HH (0xFF000000U) //!< Bit mask for RFVBAT_REGn_HH.
-#define BS_RFVBAT_REGn_HH (8U) //!< Bit field size in bits for RFVBAT_REGn_HH.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RFVBAT_REGn_HH field.
-#define BR_RFVBAT_REGn_HH(n) (HW_RFVBAT_REGn(n).B.HH)
-#endif
-
-//! @brief Format value for bitfield RFVBAT_REGn_HH.
-#define BF_RFVBAT_REGn_HH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFVBAT_REGn_HH), uint32_t) & BM_RFVBAT_REGn_HH)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the HH field to a new value.
-#define BW_RFVBAT_REGn_HH(n, v) (HW_RFVBAT_REGn_WR(n, (HW_RFVBAT_REGn_RD(n) & ~BM_RFVBAT_REGn_HH) | BF_RFVBAT_REGn_HH(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_rfvbat_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All RFVBAT module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_rfvbat
-{
- __IO hw_rfvbat_regn_t REGn[8]; //!< [0x0] VBAT register file register
-} hw_rfvbat_t;
-#pragma pack()
-
-//! @brief Macro to access all RFVBAT registers.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_RFVBAT</code>.
-#define HW_RFVBAT (*(hw_rfvbat_t *) REGS_RFVBAT_BASE)
-#endif
-
-#endif // __HW_RFVBAT_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_rng.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,590 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_RNG_REGISTERS_H__
-#define __HW_RNG_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 RNG
- *
- * Random Number Generator Accelerator
- *
- * Registers defined in this header file:
- * - HW_RNG_CR - RNGA Control Register
- * - HW_RNG_SR - RNGA Status Register
- * - HW_RNG_ER - RNGA Entropy Register
- * - HW_RNG_OR - RNGA Output Register
- *
- * - hw_rng_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_RNG_BASE
-#define HW_RNG_INSTANCE_COUNT (1U) //!< Number of instances of the RNG module.
-#define REGS_RNG_BASE (0x40029000U) //!< Base address for RNG.
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_RNG_CR - RNGA Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_RNG_CR - RNGA Control Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * Controls the operation of RNGA.
- */
-typedef union _hw_rng_cr
-{
- uint32_t U;
- struct _hw_rng_cr_bitfields
- {
- uint32_t GO : 1; //!< [0] Go
- uint32_t HA : 1; //!< [1] High Assurance
- uint32_t INTM : 1; //!< [2] Interrupt Mask
- uint32_t CLRI : 1; //!< [3] Clear Interrupt
- uint32_t SLP : 1; //!< [4] Sleep
- uint32_t RESERVED0 : 27; //!< [31:5]
- } B;
-} hw_rng_cr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire RNG_CR register
- */
-//@{
-#define HW_RNG_CR_ADDR (REGS_RNG_BASE + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_RNG_CR (*(__IO hw_rng_cr_t *) HW_RNG_CR_ADDR)
-#define HW_RNG_CR_RD() (HW_RNG_CR.U)
-#define HW_RNG_CR_WR(v) (HW_RNG_CR.U = (v))
-#define HW_RNG_CR_SET(v) (HW_RNG_CR_WR(HW_RNG_CR_RD() | (v)))
-#define HW_RNG_CR_CLR(v) (HW_RNG_CR_WR(HW_RNG_CR_RD() & ~(v)))
-#define HW_RNG_CR_TOG(v) (HW_RNG_CR_WR(HW_RNG_CR_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual RNG_CR bitfields
- */
-
-/*!
- * @name Register RNG_CR, field GO[0] (RW)
- *
- * Specifies whether random-data generation and loading (into OR[RANDOUT]) is
- * enabled.This field is sticky. You must reset RNGA to stop RNGA from loading
- * OR[RANDOUT] with data.
- *
- * Values:
- * - 0 - Disabled
- * - 1 - Enabled
- */
-//@{
-#define BP_RNG_CR_GO (0U) //!< Bit position for RNG_CR_GO.
-#define BM_RNG_CR_GO (0x00000001U) //!< Bit mask for RNG_CR_GO.
-#define BS_RNG_CR_GO (1U) //!< Bit field size in bits for RNG_CR_GO.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RNG_CR_GO field.
-#define BR_RNG_CR_GO (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_GO))
-#endif
-
-//! @brief Format value for bitfield RNG_CR_GO.
-#define BF_RNG_CR_GO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_GO), uint32_t) & BM_RNG_CR_GO)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the GO field to a new value.
-#define BW_RNG_CR_GO(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_GO) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RNG_CR, field HA[1] (RW)
- *
- * Enables notification of security violations (via SR[SECV]). A security
- * violation occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0. This field is sticky.
- * After enabling notification of security violations, you must reset RNGA to
- * disable them again.
- *
- * Values:
- * - 0 - Disabled
- * - 1 - Enabled
- */
-//@{
-#define BP_RNG_CR_HA (1U) //!< Bit position for RNG_CR_HA.
-#define BM_RNG_CR_HA (0x00000002U) //!< Bit mask for RNG_CR_HA.
-#define BS_RNG_CR_HA (1U) //!< Bit field size in bits for RNG_CR_HA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RNG_CR_HA field.
-#define BR_RNG_CR_HA (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_HA))
-#endif
-
-//! @brief Format value for bitfield RNG_CR_HA.
-#define BF_RNG_CR_HA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_HA), uint32_t) & BM_RNG_CR_HA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the HA field to a new value.
-#define BW_RNG_CR_HA(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_HA) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RNG_CR, field INTM[2] (RW)
- *
- * Masks the triggering of an error interrupt to the interrupt controller when
- * an OR underflow condition occurs. An OR underflow condition occurs when you
- * read OR[RANDOUT] and SR[OREG_LVL]=0. See the Output Register (OR) description.
- *
- * Values:
- * - 0 - Not masked
- * - 1 - Masked
- */
-//@{
-#define BP_RNG_CR_INTM (2U) //!< Bit position for RNG_CR_INTM.
-#define BM_RNG_CR_INTM (0x00000004U) //!< Bit mask for RNG_CR_INTM.
-#define BS_RNG_CR_INTM (1U) //!< Bit field size in bits for RNG_CR_INTM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RNG_CR_INTM field.
-#define BR_RNG_CR_INTM (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_INTM))
-#endif
-
-//! @brief Format value for bitfield RNG_CR_INTM.
-#define BF_RNG_CR_INTM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_INTM), uint32_t) & BM_RNG_CR_INTM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INTM field to a new value.
-#define BW_RNG_CR_INTM(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_INTM) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RNG_CR, field CLRI[3] (WORZ)
- *
- * Clears the interrupt by resetting the error-interrupt indicator (SR[ERRI]).
- *
- * Values:
- * - 0 - Do not clear the interrupt.
- * - 1 - Clear the interrupt. When you write 1 to this field, RNGA then resets
- * the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.
- */
-//@{
-#define BP_RNG_CR_CLRI (3U) //!< Bit position for RNG_CR_CLRI.
-#define BM_RNG_CR_CLRI (0x00000008U) //!< Bit mask for RNG_CR_CLRI.
-#define BS_RNG_CR_CLRI (1U) //!< Bit field size in bits for RNG_CR_CLRI.
-
-//! @brief Format value for bitfield RNG_CR_CLRI.
-#define BF_RNG_CR_CLRI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_CLRI), uint32_t) & BM_RNG_CR_CLRI)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CLRI field to a new value.
-#define BW_RNG_CR_CLRI(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_CLRI) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RNG_CR, field SLP[4] (RW)
- *
- * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
- * mode by asserting the DOZE signal.
- *
- * Values:
- * - 0 - Normal mode
- * - 1 - Sleep (low-power) mode
- */
-//@{
-#define BP_RNG_CR_SLP (4U) //!< Bit position for RNG_CR_SLP.
-#define BM_RNG_CR_SLP (0x00000010U) //!< Bit mask for RNG_CR_SLP.
-#define BS_RNG_CR_SLP (1U) //!< Bit field size in bits for RNG_CR_SLP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RNG_CR_SLP field.
-#define BR_RNG_CR_SLP (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_SLP))
-#endif
-
-//! @brief Format value for bitfield RNG_CR_SLP.
-#define BF_RNG_CR_SLP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_SLP), uint32_t) & BM_RNG_CR_SLP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SLP field to a new value.
-#define BW_RNG_CR_SLP(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_SLP) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_RNG_SR - RNGA Status Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_RNG_SR - RNGA Status Register (RO)
- *
- * Reset value: 0x00010000U
- *
- * Indicates the status of RNGA. This register is read-only.
- */
-typedef union _hw_rng_sr
-{
- uint32_t U;
- struct _hw_rng_sr_bitfields
- {
- uint32_t SECV : 1; //!< [0] Security Violation
- uint32_t LRS : 1; //!< [1] Last Read Status
- uint32_t ORU : 1; //!< [2] Output Register Underflow
- uint32_t ERRI : 1; //!< [3] Error Interrupt
- uint32_t SLP : 1; //!< [4] Sleep
- uint32_t RESERVED0 : 3; //!< [7:5]
- uint32_t OREG_LVL : 8; //!< [15:8] Output Register Level
- uint32_t OREG_SIZE : 8; //!< [23:16] Output Register Size
- uint32_t RESERVED1 : 8; //!< [31:24]
- } B;
-} hw_rng_sr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire RNG_SR register
- */
-//@{
-#define HW_RNG_SR_ADDR (REGS_RNG_BASE + 0x4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_RNG_SR (*(__I hw_rng_sr_t *) HW_RNG_SR_ADDR)
-#define HW_RNG_SR_RD() (HW_RNG_SR.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual RNG_SR bitfields
- */
-
-/*!
- * @name Register RNG_SR, field SECV[0] (RO)
- *
- * Used only when high assurance is enabled (CR[HA]). Indicates that a security
- * violation has occurred.This field is sticky. To clear SR[SECV], you must reset
- * RNGA.
- *
- * Values:
- * - 0 - No security violation
- * - 1 - Security violation
- */
-//@{
-#define BP_RNG_SR_SECV (0U) //!< Bit position for RNG_SR_SECV.
-#define BM_RNG_SR_SECV (0x00000001U) //!< Bit mask for RNG_SR_SECV.
-#define BS_RNG_SR_SECV (1U) //!< Bit field size in bits for RNG_SR_SECV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RNG_SR_SECV field.
-#define BR_RNG_SR_SECV (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_SECV))
-#endif
-//@}
-
-/*!
- * @name Register RNG_SR, field LRS[1] (RO)
- *
- * Indicates whether the most recent read of OR[RANDOUT] caused an OR underflow
- * condition, regardless of whether the error interrupt is masked (CR[INTM]). An
- * OR underflow condition occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0.
- * After you read this register, RNGA writes 0 to this field.
- *
- * Values:
- * - 0 - No underflow
- * - 1 - Underflow
- */
-//@{
-#define BP_RNG_SR_LRS (1U) //!< Bit position for RNG_SR_LRS.
-#define BM_RNG_SR_LRS (0x00000002U) //!< Bit mask for RNG_SR_LRS.
-#define BS_RNG_SR_LRS (1U) //!< Bit field size in bits for RNG_SR_LRS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RNG_SR_LRS field.
-#define BR_RNG_SR_LRS (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_LRS))
-#endif
-//@}
-
-/*!
- * @name Register RNG_SR, field ORU[2] (RO)
- *
- * Indicates whether an OR underflow condition has occurred since you last read
- * this register (SR) or RNGA was reset, regardless of whether the error
- * interrupt is masked (CR[INTM]). An OR underflow condition occurs when you read
- * OR[RANDOUT] and SR[OREG_LVL]=0. After you read this register, RNGA writes 0 to this
- * field.
- *
- * Values:
- * - 0 - No underflow
- * - 1 - Underflow
- */
-//@{
-#define BP_RNG_SR_ORU (2U) //!< Bit position for RNG_SR_ORU.
-#define BM_RNG_SR_ORU (0x00000004U) //!< Bit mask for RNG_SR_ORU.
-#define BS_RNG_SR_ORU (1U) //!< Bit field size in bits for RNG_SR_ORU.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RNG_SR_ORU field.
-#define BR_RNG_SR_ORU (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_ORU))
-#endif
-//@}
-
-/*!
- * @name Register RNG_SR, field ERRI[3] (RO)
- *
- * Indicates whether an OR underflow condition has occurred since you last
- * cleared the error interrupt (CR[CLRI]) or RNGA was reset, regardless of whether the
- * error interrupt is masked (CR[INTM]). An OR underflow condition occurs when
- * you read OR[RANDOUT] and SR[OREG_LVL]=0. After you reset the error-interrupt
- * indicator (via CR[CLRI]), RNGA writes 0 to this field.
- *
- * Values:
- * - 0 - No underflow
- * - 1 - Underflow
- */
-//@{
-#define BP_RNG_SR_ERRI (3U) //!< Bit position for RNG_SR_ERRI.
-#define BM_RNG_SR_ERRI (0x00000008U) //!< Bit mask for RNG_SR_ERRI.
-#define BS_RNG_SR_ERRI (1U) //!< Bit field size in bits for RNG_SR_ERRI.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RNG_SR_ERRI field.
-#define BR_RNG_SR_ERRI (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_ERRI))
-#endif
-//@}
-
-/*!
- * @name Register RNG_SR, field SLP[4] (RO)
- *
- * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
- * mode by asserting the DOZE signal.
- *
- * Values:
- * - 0 - Normal mode
- * - 1 - Sleep (low-power) mode
- */
-//@{
-#define BP_RNG_SR_SLP (4U) //!< Bit position for RNG_SR_SLP.
-#define BM_RNG_SR_SLP (0x00000010U) //!< Bit mask for RNG_SR_SLP.
-#define BS_RNG_SR_SLP (1U) //!< Bit field size in bits for RNG_SR_SLP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RNG_SR_SLP field.
-#define BR_RNG_SR_SLP (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_SLP))
-#endif
-//@}
-
-/*!
- * @name Register RNG_SR, field OREG_LVL[15:8] (RO)
- *
- * Indicates the number of random-data words that are in OR[RANDOUT], which
- * indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL]
- * is not 0, then the contents of a random number contained in OR[RANDOUT] are
- * returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL].
- *
- * Values:
- * - 0 - No words (empty)
- * - 1 - One word (valid)
- */
-//@{
-#define BP_RNG_SR_OREG_LVL (8U) //!< Bit position for RNG_SR_OREG_LVL.
-#define BM_RNG_SR_OREG_LVL (0x0000FF00U) //!< Bit mask for RNG_SR_OREG_LVL.
-#define BS_RNG_SR_OREG_LVL (8U) //!< Bit field size in bits for RNG_SR_OREG_LVL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RNG_SR_OREG_LVL field.
-#define BR_RNG_SR_OREG_LVL (HW_RNG_SR.B.OREG_LVL)
-#endif
-//@}
-
-/*!
- * @name Register RNG_SR, field OREG_SIZE[23:16] (RO)
- *
- * Indicates the size of the Output (OR) register in terms of the number of
- * 32-bit random-data words it can hold.
- *
- * Values:
- * - 1 - One word (this value is fixed)
- */
-//@{
-#define BP_RNG_SR_OREG_SIZE (16U) //!< Bit position for RNG_SR_OREG_SIZE.
-#define BM_RNG_SR_OREG_SIZE (0x00FF0000U) //!< Bit mask for RNG_SR_OREG_SIZE.
-#define BS_RNG_SR_OREG_SIZE (8U) //!< Bit field size in bits for RNG_SR_OREG_SIZE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RNG_SR_OREG_SIZE field.
-#define BR_RNG_SR_OREG_SIZE (HW_RNG_SR.B.OREG_SIZE)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_RNG_ER - RNGA Entropy Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_RNG_ER - RNGA Entropy Register (WORZ)
- *
- * Reset value: 0x00000000U
- *
- * Specifies an entropy value that RNGA uses in addition to its ring oscillators
- * to seed its pseudorandom algorithm. This is a write-only register; reads
- * return all zeros.
- */
-typedef union _hw_rng_er
-{
- uint32_t U;
- struct _hw_rng_er_bitfields
- {
- uint32_t EXT_ENT : 32; //!< [31:0] External Entropy
- } B;
-} hw_rng_er_t;
-#endif
-
-/*!
- * @name Constants and macros for entire RNG_ER register
- */
-//@{
-#define HW_RNG_ER_ADDR (REGS_RNG_BASE + 0x8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_RNG_ER (*(__O hw_rng_er_t *) HW_RNG_ER_ADDR)
-#define HW_RNG_ER_RD() (HW_RNG_ER.U)
-#define HW_RNG_ER_WR(v) (HW_RNG_ER.U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual RNG_ER bitfields
- */
-
-/*!
- * @name Register RNG_ER, field EXT_ENT[31:0] (WORZ)
- *
- * Specifies an entropy value that RNGA uses in addition to its ring oscillators
- * to seed its pseudorandom algorithm.Specifying a value for this field is
- * optional but recommended. You can write to this field at any time during operation.
- */
-//@{
-#define BP_RNG_ER_EXT_ENT (0U) //!< Bit position for RNG_ER_EXT_ENT.
-#define BM_RNG_ER_EXT_ENT (0xFFFFFFFFU) //!< Bit mask for RNG_ER_EXT_ENT.
-#define BS_RNG_ER_EXT_ENT (32U) //!< Bit field size in bits for RNG_ER_EXT_ENT.
-
-//! @brief Format value for bitfield RNG_ER_EXT_ENT.
-#define BF_RNG_ER_EXT_ENT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_ER_EXT_ENT), uint32_t) & BM_RNG_ER_EXT_ENT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EXT_ENT field to a new value.
-#define BW_RNG_ER_EXT_ENT(v) (HW_RNG_ER_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_RNG_OR - RNGA Output Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_RNG_OR - RNGA Output Register (RO)
- *
- * Reset value: 0x00000000U
- *
- * Stores a random-data word generated by RNGA.
- */
-typedef union _hw_rng_or
-{
- uint32_t U;
- struct _hw_rng_or_bitfields
- {
- uint32_t RANDOUT : 32; //!< [31:0] Random Output
- } B;
-} hw_rng_or_t;
-#endif
-
-/*!
- * @name Constants and macros for entire RNG_OR register
- */
-//@{
-#define HW_RNG_OR_ADDR (REGS_RNG_BASE + 0xCU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_RNG_OR (*(__I hw_rng_or_t *) HW_RNG_OR_ADDR)
-#define HW_RNG_OR_RD() (HW_RNG_OR.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual RNG_OR bitfields
- */
-
-/*!
- * @name Register RNG_OR, field RANDOUT[31:0] (RO)
- *
- * Stores a random-data word generated by RNGA. This is a read-only field.Before
- * reading RANDOUT, be sure it is valid (SR[OREG_LVL]=1).
- *
- * Values:
- * - 0 - Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is
- * 0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error
- * interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt
- * request to the interrupt controller).
- */
-//@{
-#define BP_RNG_OR_RANDOUT (0U) //!< Bit position for RNG_OR_RANDOUT.
-#define BM_RNG_OR_RANDOUT (0xFFFFFFFFU) //!< Bit mask for RNG_OR_RANDOUT.
-#define BS_RNG_OR_RANDOUT (32U) //!< Bit field size in bits for RNG_OR_RANDOUT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RNG_OR_RANDOUT field.
-#define BR_RNG_OR_RANDOUT (HW_RNG_OR.U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_rng_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All RNG module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_rng
-{
- __IO hw_rng_cr_t CR; //!< [0x0] RNGA Control Register
- __I hw_rng_sr_t SR; //!< [0x4] RNGA Status Register
- __O hw_rng_er_t ER; //!< [0x8] RNGA Entropy Register
- __I hw_rng_or_t OR; //!< [0xC] RNGA Output Register
-} hw_rng_t;
-#pragma pack()
-
-//! @brief Macro to access all RNG registers.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_RNG</code>.
-#define HW_RNG (*(hw_rng_t *) REGS_RNG_BASE)
-#endif
-
-#endif // __HW_RNG_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_rtc.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1828 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_RTC_REGISTERS_H__
-#define __HW_RTC_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 RTC
- *
- * Secure Real Time Clock
- *
- * Registers defined in this header file:
- * - HW_RTC_TSR - RTC Time Seconds Register
- * - HW_RTC_TPR - RTC Time Prescaler Register
- * - HW_RTC_TAR - RTC Time Alarm Register
- * - HW_RTC_TCR - RTC Time Compensation Register
- * - HW_RTC_CR - RTC Control Register
- * - HW_RTC_SR - RTC Status Register
- * - HW_RTC_LR - RTC Lock Register
- * - HW_RTC_IER - RTC Interrupt Enable Register
- * - HW_RTC_WAR - RTC Write Access Register
- * - HW_RTC_RAR - RTC Read Access Register
- *
- * - hw_rtc_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_RTC_BASE
-#define HW_RTC_INSTANCE_COUNT (1U) //!< Number of instances of the RTC module.
-#define REGS_RTC_BASE (0x4003D000U) //!< Base address for RTC.
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_RTC_TSR - RTC Time Seconds Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_RTC_TSR - RTC Time Seconds Register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_rtc_tsr
-{
- uint32_t U;
- struct _hw_rtc_tsr_bitfields
- {
- uint32_t TSR : 32; //!< [31:0] Time Seconds Register
- } B;
-} hw_rtc_tsr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire RTC_TSR register
- */
-//@{
-#define HW_RTC_TSR_ADDR (REGS_RTC_BASE + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_RTC_TSR (*(__IO hw_rtc_tsr_t *) HW_RTC_TSR_ADDR)
-#define HW_RTC_TSR_RD() (HW_RTC_TSR.U)
-#define HW_RTC_TSR_WR(v) (HW_RTC_TSR.U = (v))
-#define HW_RTC_TSR_SET(v) (HW_RTC_TSR_WR(HW_RTC_TSR_RD() | (v)))
-#define HW_RTC_TSR_CLR(v) (HW_RTC_TSR_WR(HW_RTC_TSR_RD() & ~(v)))
-#define HW_RTC_TSR_TOG(v) (HW_RTC_TSR_WR(HW_RTC_TSR_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual RTC_TSR bitfields
- */
-
-/*!
- * @name Register RTC_TSR, field TSR[31:0] (RW)
- *
- * When the time counter is enabled, the TSR is read only and increments once a
- * second provided SR[TOF] or SR[TIF] are not set. The time counter will read as
- * zero when SR[TOF] or SR[TIF] are set. When the time counter is disabled, the
- * TSR can be read or written. Writing to the TSR when the time counter is
- * disabled will clear the SR[TOF] and/or the SR[TIF]. Writing to TSR with zero is
- * supported, but not recommended because TSR will read as zero when SR[TIF] or
- * SR[TOF] are set (indicating the time is invalid).
- */
-//@{
-#define BP_RTC_TSR_TSR (0U) //!< Bit position for RTC_TSR_TSR.
-#define BM_RTC_TSR_TSR (0xFFFFFFFFU) //!< Bit mask for RTC_TSR_TSR.
-#define BS_RTC_TSR_TSR (32U) //!< Bit field size in bits for RTC_TSR_TSR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_TSR_TSR field.
-#define BR_RTC_TSR_TSR (HW_RTC_TSR.U)
-#endif
-
-//! @brief Format value for bitfield RTC_TSR_TSR.
-#define BF_RTC_TSR_TSR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_TSR_TSR), uint32_t) & BM_RTC_TSR_TSR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TSR field to a new value.
-#define BW_RTC_TSR_TSR(v) (HW_RTC_TSR_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_RTC_TPR - RTC Time Prescaler Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_RTC_TPR - RTC Time Prescaler Register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_rtc_tpr
-{
- uint32_t U;
- struct _hw_rtc_tpr_bitfields
- {
- uint32_t TPR : 16; //!< [15:0] Time Prescaler Register
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_rtc_tpr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire RTC_TPR register
- */
-//@{
-#define HW_RTC_TPR_ADDR (REGS_RTC_BASE + 0x4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_RTC_TPR (*(__IO hw_rtc_tpr_t *) HW_RTC_TPR_ADDR)
-#define HW_RTC_TPR_RD() (HW_RTC_TPR.U)
-#define HW_RTC_TPR_WR(v) (HW_RTC_TPR.U = (v))
-#define HW_RTC_TPR_SET(v) (HW_RTC_TPR_WR(HW_RTC_TPR_RD() | (v)))
-#define HW_RTC_TPR_CLR(v) (HW_RTC_TPR_WR(HW_RTC_TPR_RD() & ~(v)))
-#define HW_RTC_TPR_TOG(v) (HW_RTC_TPR_WR(HW_RTC_TPR_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual RTC_TPR bitfields
- */
-
-/*!
- * @name Register RTC_TPR, field TPR[15:0] (RW)
- *
- * When the time counter is enabled, the TPR is read only and increments every
- * 32.768 kHz clock cycle. The time counter will read as zero when SR[TOF] or
- * SR[TIF] are set. When the time counter is disabled, the TPR can be read or
- * written. The TSR[TSR] increments when bit 14 of the TPR transitions from a logic one
- * to a logic zero.
- */
-//@{
-#define BP_RTC_TPR_TPR (0U) //!< Bit position for RTC_TPR_TPR.
-#define BM_RTC_TPR_TPR (0x0000FFFFU) //!< Bit mask for RTC_TPR_TPR.
-#define BS_RTC_TPR_TPR (16U) //!< Bit field size in bits for RTC_TPR_TPR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_TPR_TPR field.
-#define BR_RTC_TPR_TPR (HW_RTC_TPR.B.TPR)
-#endif
-
-//! @brief Format value for bitfield RTC_TPR_TPR.
-#define BF_RTC_TPR_TPR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_TPR_TPR), uint32_t) & BM_RTC_TPR_TPR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TPR field to a new value.
-#define BW_RTC_TPR_TPR(v) (HW_RTC_TPR_WR((HW_RTC_TPR_RD() & ~BM_RTC_TPR_TPR) | BF_RTC_TPR_TPR(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_RTC_TAR - RTC Time Alarm Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_RTC_TAR - RTC Time Alarm Register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_rtc_tar
-{
- uint32_t U;
- struct _hw_rtc_tar_bitfields
- {
- uint32_t TAR : 32; //!< [31:0] Time Alarm Register
- } B;
-} hw_rtc_tar_t;
-#endif
-
-/*!
- * @name Constants and macros for entire RTC_TAR register
- */
-//@{
-#define HW_RTC_TAR_ADDR (REGS_RTC_BASE + 0x8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_RTC_TAR (*(__IO hw_rtc_tar_t *) HW_RTC_TAR_ADDR)
-#define HW_RTC_TAR_RD() (HW_RTC_TAR.U)
-#define HW_RTC_TAR_WR(v) (HW_RTC_TAR.U = (v))
-#define HW_RTC_TAR_SET(v) (HW_RTC_TAR_WR(HW_RTC_TAR_RD() | (v)))
-#define HW_RTC_TAR_CLR(v) (HW_RTC_TAR_WR(HW_RTC_TAR_RD() & ~(v)))
-#define HW_RTC_TAR_TOG(v) (HW_RTC_TAR_WR(HW_RTC_TAR_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual RTC_TAR bitfields
- */
-
-/*!
- * @name Register RTC_TAR, field TAR[31:0] (RW)
- *
- * When the time counter is enabled, the SR[TAF] is set whenever the TAR[TAR]
- * equals the TSR[TSR] and the TSR[TSR] increments. Writing to the TAR clears the
- * SR[TAF].
- */
-//@{
-#define BP_RTC_TAR_TAR (0U) //!< Bit position for RTC_TAR_TAR.
-#define BM_RTC_TAR_TAR (0xFFFFFFFFU) //!< Bit mask for RTC_TAR_TAR.
-#define BS_RTC_TAR_TAR (32U) //!< Bit field size in bits for RTC_TAR_TAR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_TAR_TAR field.
-#define BR_RTC_TAR_TAR (HW_RTC_TAR.U)
-#endif
-
-//! @brief Format value for bitfield RTC_TAR_TAR.
-#define BF_RTC_TAR_TAR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_TAR_TAR), uint32_t) & BM_RTC_TAR_TAR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TAR field to a new value.
-#define BW_RTC_TAR_TAR(v) (HW_RTC_TAR_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_RTC_TCR - RTC Time Compensation Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_RTC_TCR - RTC Time Compensation Register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_rtc_tcr
-{
- uint32_t U;
- struct _hw_rtc_tcr_bitfields
- {
- uint32_t TCR : 8; //!< [7:0] Time Compensation Register
- uint32_t CIR : 8; //!< [15:8] Compensation Interval Register
- uint32_t TCV : 8; //!< [23:16] Time Compensation Value
- uint32_t CIC : 8; //!< [31:24] Compensation Interval Counter
- } B;
-} hw_rtc_tcr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire RTC_TCR register
- */
-//@{
-#define HW_RTC_TCR_ADDR (REGS_RTC_BASE + 0xCU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_RTC_TCR (*(__IO hw_rtc_tcr_t *) HW_RTC_TCR_ADDR)
-#define HW_RTC_TCR_RD() (HW_RTC_TCR.U)
-#define HW_RTC_TCR_WR(v) (HW_RTC_TCR.U = (v))
-#define HW_RTC_TCR_SET(v) (HW_RTC_TCR_WR(HW_RTC_TCR_RD() | (v)))
-#define HW_RTC_TCR_CLR(v) (HW_RTC_TCR_WR(HW_RTC_TCR_RD() & ~(v)))
-#define HW_RTC_TCR_TOG(v) (HW_RTC_TCR_WR(HW_RTC_TCR_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual RTC_TCR bitfields
- */
-
-/*!
- * @name Register RTC_TCR, field TCR[7:0] (RW)
- *
- * Configures the number of 32.768 kHz clock cycles in each second. This
- * register is double buffered and writes do not take affect until the end of the
- * current compensation interval.
- *
- * Values:
- * - 10000000 - Time Prescaler Register overflows every 32896 clock cycles.
- * - 11111111 - Time Prescaler Register overflows every 32769 clock cycles.
- * - 0 - Time Prescaler Register overflows every 32768 clock cycles.
- * - 1 - Time Prescaler Register overflows every 32767 clock cycles.
- * - 1111111 - Time Prescaler Register overflows every 32641 clock cycles.
- */
-//@{
-#define BP_RTC_TCR_TCR (0U) //!< Bit position for RTC_TCR_TCR.
-#define BM_RTC_TCR_TCR (0x000000FFU) //!< Bit mask for RTC_TCR_TCR.
-#define BS_RTC_TCR_TCR (8U) //!< Bit field size in bits for RTC_TCR_TCR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_TCR_TCR field.
-#define BR_RTC_TCR_TCR (HW_RTC_TCR.B.TCR)
-#endif
-
-//! @brief Format value for bitfield RTC_TCR_TCR.
-#define BF_RTC_TCR_TCR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_TCR_TCR), uint32_t) & BM_RTC_TCR_TCR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TCR field to a new value.
-#define BW_RTC_TCR_TCR(v) (HW_RTC_TCR_WR((HW_RTC_TCR_RD() & ~BM_RTC_TCR_TCR) | BF_RTC_TCR_TCR(v)))
-#endif
-//@}
-
-/*!
- * @name Register RTC_TCR, field CIR[15:8] (RW)
- *
- * Configures the compensation interval in seconds from 1 to 256 to control how
- * frequently the TCR should adjust the number of 32.768 kHz cycles in each
- * second. The value written should be one less than the number of seconds. For
- * example, write zero to configure for a compensation interval of one second. This
- * register is double buffered and writes do not take affect until the end of the
- * current compensation interval.
- */
-//@{
-#define BP_RTC_TCR_CIR (8U) //!< Bit position for RTC_TCR_CIR.
-#define BM_RTC_TCR_CIR (0x0000FF00U) //!< Bit mask for RTC_TCR_CIR.
-#define BS_RTC_TCR_CIR (8U) //!< Bit field size in bits for RTC_TCR_CIR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_TCR_CIR field.
-#define BR_RTC_TCR_CIR (HW_RTC_TCR.B.CIR)
-#endif
-
-//! @brief Format value for bitfield RTC_TCR_CIR.
-#define BF_RTC_TCR_CIR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_TCR_CIR), uint32_t) & BM_RTC_TCR_CIR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CIR field to a new value.
-#define BW_RTC_TCR_CIR(v) (HW_RTC_TCR_WR((HW_RTC_TCR_RD() & ~BM_RTC_TCR_CIR) | BF_RTC_TCR_CIR(v)))
-#endif
-//@}
-
-/*!
- * @name Register RTC_TCR, field TCV[23:16] (RO)
- *
- * Current value used by the compensation logic for the present second interval.
- * Updated once a second if the CIC equals 0 with the contents of the TCR field.
- * If the CIC does not equal zero then it is loaded with zero (compensation is
- * not enabled for that second increment).
- */
-//@{
-#define BP_RTC_TCR_TCV (16U) //!< Bit position for RTC_TCR_TCV.
-#define BM_RTC_TCR_TCV (0x00FF0000U) //!< Bit mask for RTC_TCR_TCV.
-#define BS_RTC_TCR_TCV (8U) //!< Bit field size in bits for RTC_TCR_TCV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_TCR_TCV field.
-#define BR_RTC_TCR_TCV (HW_RTC_TCR.B.TCV)
-#endif
-//@}
-
-/*!
- * @name Register RTC_TCR, field CIC[31:24] (RO)
- *
- * Current value of the compensation interval counter. If the compensation
- * interval counter equals zero then it is loaded with the contents of the CIR. If the
- * CIC does not equal zero then it is decremented once a second.
- */
-//@{
-#define BP_RTC_TCR_CIC (24U) //!< Bit position for RTC_TCR_CIC.
-#define BM_RTC_TCR_CIC (0xFF000000U) //!< Bit mask for RTC_TCR_CIC.
-#define BS_RTC_TCR_CIC (8U) //!< Bit field size in bits for RTC_TCR_CIC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_TCR_CIC field.
-#define BR_RTC_TCR_CIC (HW_RTC_TCR.B.CIC)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_RTC_CR - RTC Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_RTC_CR - RTC Control Register (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_rtc_cr
-{
- uint32_t U;
- struct _hw_rtc_cr_bitfields
- {
- uint32_t SWR : 1; //!< [0] Software Reset
- uint32_t WPE : 1; //!< [1] Wakeup Pin Enable
- uint32_t SUP : 1; //!< [2] Supervisor Access
- uint32_t UM : 1; //!< [3] Update Mode
- uint32_t WPS : 1; //!< [4] Wakeup Pin Select
- uint32_t RESERVED0 : 3; //!< [7:5]
- uint32_t OSCE : 1; //!< [8] Oscillator Enable
- uint32_t CLKO : 1; //!< [9] Clock Output
- uint32_t SC16P : 1; //!< [10] Oscillator 16pF Load Configure
- uint32_t SC8P : 1; //!< [11] Oscillator 8pF Load Configure
- uint32_t SC4P : 1; //!< [12] Oscillator 4pF Load Configure
- uint32_t SC2P : 1; //!< [13] Oscillator 2pF Load Configure
- uint32_t RESERVED1 : 18; //!< [31:14]
- } B;
-} hw_rtc_cr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire RTC_CR register
- */
-//@{
-#define HW_RTC_CR_ADDR (REGS_RTC_BASE + 0x10U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_RTC_CR (*(__IO hw_rtc_cr_t *) HW_RTC_CR_ADDR)
-#define HW_RTC_CR_RD() (HW_RTC_CR.U)
-#define HW_RTC_CR_WR(v) (HW_RTC_CR.U = (v))
-#define HW_RTC_CR_SET(v) (HW_RTC_CR_WR(HW_RTC_CR_RD() | (v)))
-#define HW_RTC_CR_CLR(v) (HW_RTC_CR_WR(HW_RTC_CR_RD() & ~(v)))
-#define HW_RTC_CR_TOG(v) (HW_RTC_CR_WR(HW_RTC_CR_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual RTC_CR bitfields
- */
-
-/*!
- * @name Register RTC_CR, field SWR[0] (RW)
- *
- * Values:
- * - 0 - No effect.
- * - 1 - Resets all RTC registers except for the SWR bit and the RTC_WAR and
- * RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software
- * explicitly clearing it.
- */
-//@{
-#define BP_RTC_CR_SWR (0U) //!< Bit position for RTC_CR_SWR.
-#define BM_RTC_CR_SWR (0x00000001U) //!< Bit mask for RTC_CR_SWR.
-#define BS_RTC_CR_SWR (1U) //!< Bit field size in bits for RTC_CR_SWR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_CR_SWR field.
-#define BR_RTC_CR_SWR (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SWR))
-#endif
-
-//! @brief Format value for bitfield RTC_CR_SWR.
-#define BF_RTC_CR_SWR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SWR), uint32_t) & BM_RTC_CR_SWR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SWR field to a new value.
-#define BW_RTC_CR_SWR(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SWR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_CR, field WPE[1] (RW)
- *
- * The wakeup pin is optional and not available on all devices.
- *
- * Values:
- * - 0 - Wakeup pin is disabled.
- * - 1 - Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt
- * asserts or the wakeup pin is turned on.
- */
-//@{
-#define BP_RTC_CR_WPE (1U) //!< Bit position for RTC_CR_WPE.
-#define BM_RTC_CR_WPE (0x00000002U) //!< Bit mask for RTC_CR_WPE.
-#define BS_RTC_CR_WPE (1U) //!< Bit field size in bits for RTC_CR_WPE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_CR_WPE field.
-#define BR_RTC_CR_WPE (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_WPE))
-#endif
-
-//! @brief Format value for bitfield RTC_CR_WPE.
-#define BF_RTC_CR_WPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_WPE), uint32_t) & BM_RTC_CR_WPE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WPE field to a new value.
-#define BW_RTC_CR_WPE(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_WPE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_CR, field SUP[2] (RW)
- *
- * Values:
- * - 0 - Non-supervisor mode write accesses are not supported and generate a bus
- * error.
- * - 1 - Non-supervisor mode write accesses are supported.
- */
-//@{
-#define BP_RTC_CR_SUP (2U) //!< Bit position for RTC_CR_SUP.
-#define BM_RTC_CR_SUP (0x00000004U) //!< Bit mask for RTC_CR_SUP.
-#define BS_RTC_CR_SUP (1U) //!< Bit field size in bits for RTC_CR_SUP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_CR_SUP field.
-#define BR_RTC_CR_SUP (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SUP))
-#endif
-
-//! @brief Format value for bitfield RTC_CR_SUP.
-#define BF_RTC_CR_SUP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SUP), uint32_t) & BM_RTC_CR_SUP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SUP field to a new value.
-#define BW_RTC_CR_SUP(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SUP) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_CR, field UM[3] (RW)
- *
- * Allows SR[TCE] to be written even when the Status Register is locked. When
- * set, the SR[TCE] can always be written if the SR[TIF] or SR[TOF] are set or if
- * the SR[TCE] is clear.
- *
- * Values:
- * - 0 - Registers cannot be written when locked.
- * - 1 - Registers can be written when locked under limited conditions.
- */
-//@{
-#define BP_RTC_CR_UM (3U) //!< Bit position for RTC_CR_UM.
-#define BM_RTC_CR_UM (0x00000008U) //!< Bit mask for RTC_CR_UM.
-#define BS_RTC_CR_UM (1U) //!< Bit field size in bits for RTC_CR_UM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_CR_UM field.
-#define BR_RTC_CR_UM (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_UM))
-#endif
-
-//! @brief Format value for bitfield RTC_CR_UM.
-#define BF_RTC_CR_UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_UM), uint32_t) & BM_RTC_CR_UM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the UM field to a new value.
-#define BW_RTC_CR_UM(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_UM) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_CR, field WPS[4] (RW)
- *
- * The wakeup pin is optional and not available on all devices.
- *
- * Values:
- * - 0 - Wakeup pin asserts (active low, open drain) if the RTC interrupt
- * asserts or the wakeup pin is turned on.
- * - 1 - Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin
- * is turned on and the 32kHz clock is output to other peripherals.
- */
-//@{
-#define BP_RTC_CR_WPS (4U) //!< Bit position for RTC_CR_WPS.
-#define BM_RTC_CR_WPS (0x00000010U) //!< Bit mask for RTC_CR_WPS.
-#define BS_RTC_CR_WPS (1U) //!< Bit field size in bits for RTC_CR_WPS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_CR_WPS field.
-#define BR_RTC_CR_WPS (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_WPS))
-#endif
-
-//! @brief Format value for bitfield RTC_CR_WPS.
-#define BF_RTC_CR_WPS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_WPS), uint32_t) & BM_RTC_CR_WPS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WPS field to a new value.
-#define BW_RTC_CR_WPS(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_WPS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_CR, field OSCE[8] (RW)
- *
- * Values:
- * - 0 - 32.768 kHz oscillator is disabled.
- * - 1 - 32.768 kHz oscillator is enabled. After setting this bit, wait the
- * oscillator startup time before enabling the time counter to allow the 32.768
- * kHz clock time to stabilize.
- */
-//@{
-#define BP_RTC_CR_OSCE (8U) //!< Bit position for RTC_CR_OSCE.
-#define BM_RTC_CR_OSCE (0x00000100U) //!< Bit mask for RTC_CR_OSCE.
-#define BS_RTC_CR_OSCE (1U) //!< Bit field size in bits for RTC_CR_OSCE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_CR_OSCE field.
-#define BR_RTC_CR_OSCE (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_OSCE))
-#endif
-
-//! @brief Format value for bitfield RTC_CR_OSCE.
-#define BF_RTC_CR_OSCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_OSCE), uint32_t) & BM_RTC_CR_OSCE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the OSCE field to a new value.
-#define BW_RTC_CR_OSCE(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_OSCE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_CR, field CLKO[9] (RW)
- *
- * Values:
- * - 0 - The 32 kHz clock is output to other peripherals.
- * - 1 - The 32 kHz clock is not output to other peripherals.
- */
-//@{
-#define BP_RTC_CR_CLKO (9U) //!< Bit position for RTC_CR_CLKO.
-#define BM_RTC_CR_CLKO (0x00000200U) //!< Bit mask for RTC_CR_CLKO.
-#define BS_RTC_CR_CLKO (1U) //!< Bit field size in bits for RTC_CR_CLKO.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_CR_CLKO field.
-#define BR_RTC_CR_CLKO (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_CLKO))
-#endif
-
-//! @brief Format value for bitfield RTC_CR_CLKO.
-#define BF_RTC_CR_CLKO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_CLKO), uint32_t) & BM_RTC_CR_CLKO)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CLKO field to a new value.
-#define BW_RTC_CR_CLKO(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_CLKO) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_CR, field SC16P[10] (RW)
- *
- * Values:
- * - 0 - Disable the load.
- * - 1 - Enable the additional load.
- */
-//@{
-#define BP_RTC_CR_SC16P (10U) //!< Bit position for RTC_CR_SC16P.
-#define BM_RTC_CR_SC16P (0x00000400U) //!< Bit mask for RTC_CR_SC16P.
-#define BS_RTC_CR_SC16P (1U) //!< Bit field size in bits for RTC_CR_SC16P.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_CR_SC16P field.
-#define BR_RTC_CR_SC16P (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC16P))
-#endif
-
-//! @brief Format value for bitfield RTC_CR_SC16P.
-#define BF_RTC_CR_SC16P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SC16P), uint32_t) & BM_RTC_CR_SC16P)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SC16P field to a new value.
-#define BW_RTC_CR_SC16P(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC16P) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_CR, field SC8P[11] (RW)
- *
- * Values:
- * - 0 - Disable the load.
- * - 1 - Enable the additional load.
- */
-//@{
-#define BP_RTC_CR_SC8P (11U) //!< Bit position for RTC_CR_SC8P.
-#define BM_RTC_CR_SC8P (0x00000800U) //!< Bit mask for RTC_CR_SC8P.
-#define BS_RTC_CR_SC8P (1U) //!< Bit field size in bits for RTC_CR_SC8P.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_CR_SC8P field.
-#define BR_RTC_CR_SC8P (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC8P))
-#endif
-
-//! @brief Format value for bitfield RTC_CR_SC8P.
-#define BF_RTC_CR_SC8P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SC8P), uint32_t) & BM_RTC_CR_SC8P)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SC8P field to a new value.
-#define BW_RTC_CR_SC8P(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC8P) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_CR, field SC4P[12] (RW)
- *
- * Values:
- * - 0 - Disable the load.
- * - 1 - Enable the additional load.
- */
-//@{
-#define BP_RTC_CR_SC4P (12U) //!< Bit position for RTC_CR_SC4P.
-#define BM_RTC_CR_SC4P (0x00001000U) //!< Bit mask for RTC_CR_SC4P.
-#define BS_RTC_CR_SC4P (1U) //!< Bit field size in bits for RTC_CR_SC4P.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_CR_SC4P field.
-#define BR_RTC_CR_SC4P (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC4P))
-#endif
-
-//! @brief Format value for bitfield RTC_CR_SC4P.
-#define BF_RTC_CR_SC4P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SC4P), uint32_t) & BM_RTC_CR_SC4P)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SC4P field to a new value.
-#define BW_RTC_CR_SC4P(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC4P) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_CR, field SC2P[13] (RW)
- *
- * Values:
- * - 0 - Disable the load.
- * - 1 - Enable the additional load.
- */
-//@{
-#define BP_RTC_CR_SC2P (13U) //!< Bit position for RTC_CR_SC2P.
-#define BM_RTC_CR_SC2P (0x00002000U) //!< Bit mask for RTC_CR_SC2P.
-#define BS_RTC_CR_SC2P (1U) //!< Bit field size in bits for RTC_CR_SC2P.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_CR_SC2P field.
-#define BR_RTC_CR_SC2P (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC2P))
-#endif
-
-//! @brief Format value for bitfield RTC_CR_SC2P.
-#define BF_RTC_CR_SC2P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SC2P), uint32_t) & BM_RTC_CR_SC2P)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SC2P field to a new value.
-#define BW_RTC_CR_SC2P(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC2P) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_RTC_SR - RTC Status Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_RTC_SR - RTC Status Register (RW)
- *
- * Reset value: 0x00000001U
- */
-typedef union _hw_rtc_sr
-{
- uint32_t U;
- struct _hw_rtc_sr_bitfields
- {
- uint32_t TIF : 1; //!< [0] Time Invalid Flag
- uint32_t TOF : 1; //!< [1] Time Overflow Flag
- uint32_t TAF : 1; //!< [2] Time Alarm Flag
- uint32_t RESERVED0 : 1; //!< [3]
- uint32_t TCE : 1; //!< [4] Time Counter Enable
- uint32_t RESERVED1 : 27; //!< [31:5]
- } B;
-} hw_rtc_sr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire RTC_SR register
- */
-//@{
-#define HW_RTC_SR_ADDR (REGS_RTC_BASE + 0x14U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_RTC_SR (*(__IO hw_rtc_sr_t *) HW_RTC_SR_ADDR)
-#define HW_RTC_SR_RD() (HW_RTC_SR.U)
-#define HW_RTC_SR_WR(v) (HW_RTC_SR.U = (v))
-#define HW_RTC_SR_SET(v) (HW_RTC_SR_WR(HW_RTC_SR_RD() | (v)))
-#define HW_RTC_SR_CLR(v) (HW_RTC_SR_WR(HW_RTC_SR_RD() & ~(v)))
-#define HW_RTC_SR_TOG(v) (HW_RTC_SR_WR(HW_RTC_SR_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual RTC_SR bitfields
- */
-
-/*!
- * @name Register RTC_SR, field TIF[0] (RO)
- *
- * The time invalid flag is set on VBAT POR or software reset. The TSR and TPR
- * do not increment and read as zero when this bit is set. This bit is cleared by
- * writing the TSR register when the time counter is disabled.
- *
- * Values:
- * - 0 - Time is valid.
- * - 1 - Time is invalid and time counter is read as zero.
- */
-//@{
-#define BP_RTC_SR_TIF (0U) //!< Bit position for RTC_SR_TIF.
-#define BM_RTC_SR_TIF (0x00000001U) //!< Bit mask for RTC_SR_TIF.
-#define BS_RTC_SR_TIF (1U) //!< Bit field size in bits for RTC_SR_TIF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_SR_TIF field.
-#define BR_RTC_SR_TIF (BITBAND_ACCESS32(HW_RTC_SR_ADDR, BP_RTC_SR_TIF))
-#endif
-//@}
-
-/*!
- * @name Register RTC_SR, field TOF[1] (RO)
- *
- * Time overflow flag is set when the time counter is enabled and overflows. The
- * TSR and TPR do not increment and read as zero when this bit is set. This bit
- * is cleared by writing the TSR register when the time counter is disabled.
- *
- * Values:
- * - 0 - Time overflow has not occurred.
- * - 1 - Time overflow has occurred and time counter is read as zero.
- */
-//@{
-#define BP_RTC_SR_TOF (1U) //!< Bit position for RTC_SR_TOF.
-#define BM_RTC_SR_TOF (0x00000002U) //!< Bit mask for RTC_SR_TOF.
-#define BS_RTC_SR_TOF (1U) //!< Bit field size in bits for RTC_SR_TOF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_SR_TOF field.
-#define BR_RTC_SR_TOF (BITBAND_ACCESS32(HW_RTC_SR_ADDR, BP_RTC_SR_TOF))
-#endif
-//@}
-
-/*!
- * @name Register RTC_SR, field TAF[2] (RO)
- *
- * Time alarm flag is set when the TAR[TAR] equals the TSR[TSR] and the TSR[TSR]
- * increments. This bit is cleared by writing the TAR register.
- *
- * Values:
- * - 0 - Time alarm has not occurred.
- * - 1 - Time alarm has occurred.
- */
-//@{
-#define BP_RTC_SR_TAF (2U) //!< Bit position for RTC_SR_TAF.
-#define BM_RTC_SR_TAF (0x00000004U) //!< Bit mask for RTC_SR_TAF.
-#define BS_RTC_SR_TAF (1U) //!< Bit field size in bits for RTC_SR_TAF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_SR_TAF field.
-#define BR_RTC_SR_TAF (BITBAND_ACCESS32(HW_RTC_SR_ADDR, BP_RTC_SR_TAF))
-#endif
-//@}
-
-/*!
- * @name Register RTC_SR, field TCE[4] (RW)
- *
- * When time counter is disabled the TSR register and TPR register are
- * writeable, but do not increment. When time counter is enabled the TSR register and TPR
- * register are not writeable, but increment.
- *
- * Values:
- * - 0 - Time counter is disabled.
- * - 1 - Time counter is enabled.
- */
-//@{
-#define BP_RTC_SR_TCE (4U) //!< Bit position for RTC_SR_TCE.
-#define BM_RTC_SR_TCE (0x00000010U) //!< Bit mask for RTC_SR_TCE.
-#define BS_RTC_SR_TCE (1U) //!< Bit field size in bits for RTC_SR_TCE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_SR_TCE field.
-#define BR_RTC_SR_TCE (BITBAND_ACCESS32(HW_RTC_SR_ADDR, BP_RTC_SR_TCE))
-#endif
-
-//! @brief Format value for bitfield RTC_SR_TCE.
-#define BF_RTC_SR_TCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_SR_TCE), uint32_t) & BM_RTC_SR_TCE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TCE field to a new value.
-#define BW_RTC_SR_TCE(v) (BITBAND_ACCESS32(HW_RTC_SR_ADDR, BP_RTC_SR_TCE) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_RTC_LR - RTC Lock Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_RTC_LR - RTC Lock Register (RW)
- *
- * Reset value: 0x000000FFU
- */
-typedef union _hw_rtc_lr
-{
- uint32_t U;
- struct _hw_rtc_lr_bitfields
- {
- uint32_t RESERVED0 : 3; //!< [2:0]
- uint32_t TCL : 1; //!< [3] Time Compensation Lock
- uint32_t CRL : 1; //!< [4] Control Register Lock
- uint32_t SRL : 1; //!< [5] Status Register Lock
- uint32_t LRL : 1; //!< [6] Lock Register Lock
- uint32_t RESERVED1 : 25; //!< [31:7]
- } B;
-} hw_rtc_lr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire RTC_LR register
- */
-//@{
-#define HW_RTC_LR_ADDR (REGS_RTC_BASE + 0x18U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_RTC_LR (*(__IO hw_rtc_lr_t *) HW_RTC_LR_ADDR)
-#define HW_RTC_LR_RD() (HW_RTC_LR.U)
-#define HW_RTC_LR_WR(v) (HW_RTC_LR.U = (v))
-#define HW_RTC_LR_SET(v) (HW_RTC_LR_WR(HW_RTC_LR_RD() | (v)))
-#define HW_RTC_LR_CLR(v) (HW_RTC_LR_WR(HW_RTC_LR_RD() & ~(v)))
-#define HW_RTC_LR_TOG(v) (HW_RTC_LR_WR(HW_RTC_LR_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual RTC_LR bitfields
- */
-
-/*!
- * @name Register RTC_LR, field TCL[3] (RW)
- *
- * After being cleared, this bit can be set only by VBAT POR or software reset.
- *
- * Values:
- * - 0 - Time Compensation Register is locked and writes are ignored.
- * - 1 - Time Compensation Register is not locked and writes complete as normal.
- */
-//@{
-#define BP_RTC_LR_TCL (3U) //!< Bit position for RTC_LR_TCL.
-#define BM_RTC_LR_TCL (0x00000008U) //!< Bit mask for RTC_LR_TCL.
-#define BS_RTC_LR_TCL (1U) //!< Bit field size in bits for RTC_LR_TCL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_LR_TCL field.
-#define BR_RTC_LR_TCL (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_TCL))
-#endif
-
-//! @brief Format value for bitfield RTC_LR_TCL.
-#define BF_RTC_LR_TCL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_LR_TCL), uint32_t) & BM_RTC_LR_TCL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TCL field to a new value.
-#define BW_RTC_LR_TCL(v) (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_TCL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_LR, field CRL[4] (RW)
- *
- * After being cleared, this bit can only be set by VBAT POR.
- *
- * Values:
- * - 0 - Control Register is locked and writes are ignored.
- * - 1 - Control Register is not locked and writes complete as normal.
- */
-//@{
-#define BP_RTC_LR_CRL (4U) //!< Bit position for RTC_LR_CRL.
-#define BM_RTC_LR_CRL (0x00000010U) //!< Bit mask for RTC_LR_CRL.
-#define BS_RTC_LR_CRL (1U) //!< Bit field size in bits for RTC_LR_CRL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_LR_CRL field.
-#define BR_RTC_LR_CRL (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_CRL))
-#endif
-
-//! @brief Format value for bitfield RTC_LR_CRL.
-#define BF_RTC_LR_CRL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_LR_CRL), uint32_t) & BM_RTC_LR_CRL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CRL field to a new value.
-#define BW_RTC_LR_CRL(v) (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_CRL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_LR, field SRL[5] (RW)
- *
- * After being cleared, this bit can be set only by VBAT POR or software reset.
- *
- * Values:
- * - 0 - Status Register is locked and writes are ignored.
- * - 1 - Status Register is not locked and writes complete as normal.
- */
-//@{
-#define BP_RTC_LR_SRL (5U) //!< Bit position for RTC_LR_SRL.
-#define BM_RTC_LR_SRL (0x00000020U) //!< Bit mask for RTC_LR_SRL.
-#define BS_RTC_LR_SRL (1U) //!< Bit field size in bits for RTC_LR_SRL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_LR_SRL field.
-#define BR_RTC_LR_SRL (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_SRL))
-#endif
-
-//! @brief Format value for bitfield RTC_LR_SRL.
-#define BF_RTC_LR_SRL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_LR_SRL), uint32_t) & BM_RTC_LR_SRL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SRL field to a new value.
-#define BW_RTC_LR_SRL(v) (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_SRL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_LR, field LRL[6] (RW)
- *
- * After being cleared, this bit can be set only by VBAT POR or software reset.
- *
- * Values:
- * - 0 - Lock Register is locked and writes are ignored.
- * - 1 - Lock Register is not locked and writes complete as normal.
- */
-//@{
-#define BP_RTC_LR_LRL (6U) //!< Bit position for RTC_LR_LRL.
-#define BM_RTC_LR_LRL (0x00000040U) //!< Bit mask for RTC_LR_LRL.
-#define BS_RTC_LR_LRL (1U) //!< Bit field size in bits for RTC_LR_LRL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_LR_LRL field.
-#define BR_RTC_LR_LRL (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_LRL))
-#endif
-
-//! @brief Format value for bitfield RTC_LR_LRL.
-#define BF_RTC_LR_LRL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_LR_LRL), uint32_t) & BM_RTC_LR_LRL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LRL field to a new value.
-#define BW_RTC_LR_LRL(v) (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_LRL) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_RTC_IER - RTC Interrupt Enable Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_RTC_IER - RTC Interrupt Enable Register (RW)
- *
- * Reset value: 0x00000007U
- */
-typedef union _hw_rtc_ier
-{
- uint32_t U;
- struct _hw_rtc_ier_bitfields
- {
- uint32_t TIIE : 1; //!< [0] Time Invalid Interrupt Enable
- uint32_t TOIE : 1; //!< [1] Time Overflow Interrupt Enable
- uint32_t TAIE : 1; //!< [2] Time Alarm Interrupt Enable
- uint32_t RESERVED0 : 1; //!< [3]
- uint32_t TSIE : 1; //!< [4] Time Seconds Interrupt Enable
- uint32_t RESERVED1 : 2; //!< [6:5]
- uint32_t WPON : 1; //!< [7] Wakeup Pin On
- uint32_t RESERVED2 : 24; //!< [31:8]
- } B;
-} hw_rtc_ier_t;
-#endif
-
-/*!
- * @name Constants and macros for entire RTC_IER register
- */
-//@{
-#define HW_RTC_IER_ADDR (REGS_RTC_BASE + 0x1CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_RTC_IER (*(__IO hw_rtc_ier_t *) HW_RTC_IER_ADDR)
-#define HW_RTC_IER_RD() (HW_RTC_IER.U)
-#define HW_RTC_IER_WR(v) (HW_RTC_IER.U = (v))
-#define HW_RTC_IER_SET(v) (HW_RTC_IER_WR(HW_RTC_IER_RD() | (v)))
-#define HW_RTC_IER_CLR(v) (HW_RTC_IER_WR(HW_RTC_IER_RD() & ~(v)))
-#define HW_RTC_IER_TOG(v) (HW_RTC_IER_WR(HW_RTC_IER_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual RTC_IER bitfields
- */
-
-/*!
- * @name Register RTC_IER, field TIIE[0] (RW)
- *
- * Values:
- * - 0 - Time invalid flag does not generate an interrupt.
- * - 1 - Time invalid flag does generate an interrupt.
- */
-//@{
-#define BP_RTC_IER_TIIE (0U) //!< Bit position for RTC_IER_TIIE.
-#define BM_RTC_IER_TIIE (0x00000001U) //!< Bit mask for RTC_IER_TIIE.
-#define BS_RTC_IER_TIIE (1U) //!< Bit field size in bits for RTC_IER_TIIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_IER_TIIE field.
-#define BR_RTC_IER_TIIE (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TIIE))
-#endif
-
-//! @brief Format value for bitfield RTC_IER_TIIE.
-#define BF_RTC_IER_TIIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_IER_TIIE), uint32_t) & BM_RTC_IER_TIIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TIIE field to a new value.
-#define BW_RTC_IER_TIIE(v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TIIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_IER, field TOIE[1] (RW)
- *
- * Values:
- * - 0 - Time overflow flag does not generate an interrupt.
- * - 1 - Time overflow flag does generate an interrupt.
- */
-//@{
-#define BP_RTC_IER_TOIE (1U) //!< Bit position for RTC_IER_TOIE.
-#define BM_RTC_IER_TOIE (0x00000002U) //!< Bit mask for RTC_IER_TOIE.
-#define BS_RTC_IER_TOIE (1U) //!< Bit field size in bits for RTC_IER_TOIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_IER_TOIE field.
-#define BR_RTC_IER_TOIE (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TOIE))
-#endif
-
-//! @brief Format value for bitfield RTC_IER_TOIE.
-#define BF_RTC_IER_TOIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_IER_TOIE), uint32_t) & BM_RTC_IER_TOIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TOIE field to a new value.
-#define BW_RTC_IER_TOIE(v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TOIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_IER, field TAIE[2] (RW)
- *
- * Values:
- * - 0 - Time alarm flag does not generate an interrupt.
- * - 1 - Time alarm flag does generate an interrupt.
- */
-//@{
-#define BP_RTC_IER_TAIE (2U) //!< Bit position for RTC_IER_TAIE.
-#define BM_RTC_IER_TAIE (0x00000004U) //!< Bit mask for RTC_IER_TAIE.
-#define BS_RTC_IER_TAIE (1U) //!< Bit field size in bits for RTC_IER_TAIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_IER_TAIE field.
-#define BR_RTC_IER_TAIE (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TAIE))
-#endif
-
-//! @brief Format value for bitfield RTC_IER_TAIE.
-#define BF_RTC_IER_TAIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_IER_TAIE), uint32_t) & BM_RTC_IER_TAIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TAIE field to a new value.
-#define BW_RTC_IER_TAIE(v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TAIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_IER, field TSIE[4] (RW)
- *
- * The seconds interrupt is an edge-sensitive interrupt with a dedicated
- * interrupt vector. It is generated once a second and requires no software overhead
- * (there is no corresponding status flag to clear).
- *
- * Values:
- * - 0 - Seconds interrupt is disabled.
- * - 1 - Seconds interrupt is enabled.
- */
-//@{
-#define BP_RTC_IER_TSIE (4U) //!< Bit position for RTC_IER_TSIE.
-#define BM_RTC_IER_TSIE (0x00000010U) //!< Bit mask for RTC_IER_TSIE.
-#define BS_RTC_IER_TSIE (1U) //!< Bit field size in bits for RTC_IER_TSIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_IER_TSIE field.
-#define BR_RTC_IER_TSIE (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TSIE))
-#endif
-
-//! @brief Format value for bitfield RTC_IER_TSIE.
-#define BF_RTC_IER_TSIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_IER_TSIE), uint32_t) & BM_RTC_IER_TSIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TSIE field to a new value.
-#define BW_RTC_IER_TSIE(v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TSIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_IER, field WPON[7] (RW)
- *
- * The wakeup pin is optional and not available on all devices. Whenever the
- * wakeup pin is enabled and this bit is set, the wakeup pin will assert.
- *
- * Values:
- * - 0 - No effect.
- * - 1 - If the wakeup pin is enabled, then the wakeup pin will assert.
- */
-//@{
-#define BP_RTC_IER_WPON (7U) //!< Bit position for RTC_IER_WPON.
-#define BM_RTC_IER_WPON (0x00000080U) //!< Bit mask for RTC_IER_WPON.
-#define BS_RTC_IER_WPON (1U) //!< Bit field size in bits for RTC_IER_WPON.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_IER_WPON field.
-#define BR_RTC_IER_WPON (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_WPON))
-#endif
-
-//! @brief Format value for bitfield RTC_IER_WPON.
-#define BF_RTC_IER_WPON(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_IER_WPON), uint32_t) & BM_RTC_IER_WPON)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WPON field to a new value.
-#define BW_RTC_IER_WPON(v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_WPON) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_RTC_WAR - RTC Write Access Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_RTC_WAR - RTC Write Access Register (RW)
- *
- * Reset value: 0x000000FFU
- */
-typedef union _hw_rtc_war
-{
- uint32_t U;
- struct _hw_rtc_war_bitfields
- {
- uint32_t TSRW : 1; //!< [0] Time Seconds Register Write
- uint32_t TPRW : 1; //!< [1] Time Prescaler Register Write
- uint32_t TARW : 1; //!< [2] Time Alarm Register Write
- uint32_t TCRW : 1; //!< [3] Time Compensation Register Write
- uint32_t CRW : 1; //!< [4] Control Register Write
- uint32_t SRW : 1; //!< [5] Status Register Write
- uint32_t LRW : 1; //!< [6] Lock Register Write
- uint32_t IERW : 1; //!< [7] Interrupt Enable Register Write
- uint32_t RESERVED0 : 24; //!< [31:8]
- } B;
-} hw_rtc_war_t;
-#endif
-
-/*!
- * @name Constants and macros for entire RTC_WAR register
- */
-//@{
-#define HW_RTC_WAR_ADDR (REGS_RTC_BASE + 0x800U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_RTC_WAR (*(__IO hw_rtc_war_t *) HW_RTC_WAR_ADDR)
-#define HW_RTC_WAR_RD() (HW_RTC_WAR.U)
-#define HW_RTC_WAR_WR(v) (HW_RTC_WAR.U = (v))
-#define HW_RTC_WAR_SET(v) (HW_RTC_WAR_WR(HW_RTC_WAR_RD() | (v)))
-#define HW_RTC_WAR_CLR(v) (HW_RTC_WAR_WR(HW_RTC_WAR_RD() & ~(v)))
-#define HW_RTC_WAR_TOG(v) (HW_RTC_WAR_WR(HW_RTC_WAR_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual RTC_WAR bitfields
- */
-
-/*!
- * @name Register RTC_WAR, field TSRW[0] (RW)
- *
- * After being cleared, this bit is set only by system reset. It is not affected
- * by VBAT POR or software reset.
- *
- * Values:
- * - 0 - Writes to the Time Seconds Register are ignored.
- * - 1 - Writes to the Time Seconds Register complete as normal.
- */
-//@{
-#define BP_RTC_WAR_TSRW (0U) //!< Bit position for RTC_WAR_TSRW.
-#define BM_RTC_WAR_TSRW (0x00000001U) //!< Bit mask for RTC_WAR_TSRW.
-#define BS_RTC_WAR_TSRW (1U) //!< Bit field size in bits for RTC_WAR_TSRW.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_WAR_TSRW field.
-#define BR_RTC_WAR_TSRW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TSRW))
-#endif
-
-//! @brief Format value for bitfield RTC_WAR_TSRW.
-#define BF_RTC_WAR_TSRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_TSRW), uint32_t) & BM_RTC_WAR_TSRW)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TSRW field to a new value.
-#define BW_RTC_WAR_TSRW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TSRW) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_WAR, field TPRW[1] (RW)
- *
- * After being cleared, this bit is set only by system reset. It is not affected
- * by VBAT POR or software reset.
- *
- * Values:
- * - 0 - Writes to the Time Prescaler Register are ignored.
- * - 1 - Writes to the Time Prescaler Register complete as normal.
- */
-//@{
-#define BP_RTC_WAR_TPRW (1U) //!< Bit position for RTC_WAR_TPRW.
-#define BM_RTC_WAR_TPRW (0x00000002U) //!< Bit mask for RTC_WAR_TPRW.
-#define BS_RTC_WAR_TPRW (1U) //!< Bit field size in bits for RTC_WAR_TPRW.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_WAR_TPRW field.
-#define BR_RTC_WAR_TPRW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TPRW))
-#endif
-
-//! @brief Format value for bitfield RTC_WAR_TPRW.
-#define BF_RTC_WAR_TPRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_TPRW), uint32_t) & BM_RTC_WAR_TPRW)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TPRW field to a new value.
-#define BW_RTC_WAR_TPRW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TPRW) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_WAR, field TARW[2] (RW)
- *
- * After being cleared, this bit is set only by system reset. It is not affected
- * by VBAT POR or software reset.
- *
- * Values:
- * - 0 - Writes to the Time Alarm Register are ignored.
- * - 1 - Writes to the Time Alarm Register complete as normal.
- */
-//@{
-#define BP_RTC_WAR_TARW (2U) //!< Bit position for RTC_WAR_TARW.
-#define BM_RTC_WAR_TARW (0x00000004U) //!< Bit mask for RTC_WAR_TARW.
-#define BS_RTC_WAR_TARW (1U) //!< Bit field size in bits for RTC_WAR_TARW.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_WAR_TARW field.
-#define BR_RTC_WAR_TARW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TARW))
-#endif
-
-//! @brief Format value for bitfield RTC_WAR_TARW.
-#define BF_RTC_WAR_TARW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_TARW), uint32_t) & BM_RTC_WAR_TARW)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TARW field to a new value.
-#define BW_RTC_WAR_TARW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TARW) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_WAR, field TCRW[3] (RW)
- *
- * After being cleared, this bit is set only by system reset. It is not affected
- * by VBAT POR or software reset.
- *
- * Values:
- * - 0 - Writes to the Time Compensation Register are ignored.
- * - 1 - Writes to the Time Compensation Register complete as normal.
- */
-//@{
-#define BP_RTC_WAR_TCRW (3U) //!< Bit position for RTC_WAR_TCRW.
-#define BM_RTC_WAR_TCRW (0x00000008U) //!< Bit mask for RTC_WAR_TCRW.
-#define BS_RTC_WAR_TCRW (1U) //!< Bit field size in bits for RTC_WAR_TCRW.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_WAR_TCRW field.
-#define BR_RTC_WAR_TCRW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TCRW))
-#endif
-
-//! @brief Format value for bitfield RTC_WAR_TCRW.
-#define BF_RTC_WAR_TCRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_TCRW), uint32_t) & BM_RTC_WAR_TCRW)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TCRW field to a new value.
-#define BW_RTC_WAR_TCRW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TCRW) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_WAR, field CRW[4] (RW)
- *
- * After being cleared, this bit is set only by system reset. It is not affected
- * by VBAT POR or software reset.
- *
- * Values:
- * - 0 - Writes to the Control Register are ignored.
- * - 1 - Writes to the Control Register complete as normal.
- */
-//@{
-#define BP_RTC_WAR_CRW (4U) //!< Bit position for RTC_WAR_CRW.
-#define BM_RTC_WAR_CRW (0x00000010U) //!< Bit mask for RTC_WAR_CRW.
-#define BS_RTC_WAR_CRW (1U) //!< Bit field size in bits for RTC_WAR_CRW.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_WAR_CRW field.
-#define BR_RTC_WAR_CRW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_CRW))
-#endif
-
-//! @brief Format value for bitfield RTC_WAR_CRW.
-#define BF_RTC_WAR_CRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_CRW), uint32_t) & BM_RTC_WAR_CRW)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CRW field to a new value.
-#define BW_RTC_WAR_CRW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_CRW) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_WAR, field SRW[5] (RW)
- *
- * After being cleared, this bit is set only by system reset. It is not affected
- * by VBAT POR or software reset.
- *
- * Values:
- * - 0 - Writes to the Status Register are ignored.
- * - 1 - Writes to the Status Register complete as normal.
- */
-//@{
-#define BP_RTC_WAR_SRW (5U) //!< Bit position for RTC_WAR_SRW.
-#define BM_RTC_WAR_SRW (0x00000020U) //!< Bit mask for RTC_WAR_SRW.
-#define BS_RTC_WAR_SRW (1U) //!< Bit field size in bits for RTC_WAR_SRW.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_WAR_SRW field.
-#define BR_RTC_WAR_SRW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_SRW))
-#endif
-
-//! @brief Format value for bitfield RTC_WAR_SRW.
-#define BF_RTC_WAR_SRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_SRW), uint32_t) & BM_RTC_WAR_SRW)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SRW field to a new value.
-#define BW_RTC_WAR_SRW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_SRW) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_WAR, field LRW[6] (RW)
- *
- * After being cleared, this bit is set only by system reset. It is not affected
- * by VBAT POR or software reset.
- *
- * Values:
- * - 0 - Writes to the Lock Register are ignored.
- * - 1 - Writes to the Lock Register complete as normal.
- */
-//@{
-#define BP_RTC_WAR_LRW (6U) //!< Bit position for RTC_WAR_LRW.
-#define BM_RTC_WAR_LRW (0x00000040U) //!< Bit mask for RTC_WAR_LRW.
-#define BS_RTC_WAR_LRW (1U) //!< Bit field size in bits for RTC_WAR_LRW.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_WAR_LRW field.
-#define BR_RTC_WAR_LRW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_LRW))
-#endif
-
-//! @brief Format value for bitfield RTC_WAR_LRW.
-#define BF_RTC_WAR_LRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_LRW), uint32_t) & BM_RTC_WAR_LRW)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LRW field to a new value.
-#define BW_RTC_WAR_LRW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_LRW) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_WAR, field IERW[7] (RW)
- *
- * After being cleared, this bit is set only by system reset. It is not affected
- * by VBAT POR or software reset.
- *
- * Values:
- * - 0 - Writes to the Interupt Enable Register are ignored.
- * - 1 - Writes to the Interrupt Enable Register complete as normal.
- */
-//@{
-#define BP_RTC_WAR_IERW (7U) //!< Bit position for RTC_WAR_IERW.
-#define BM_RTC_WAR_IERW (0x00000080U) //!< Bit mask for RTC_WAR_IERW.
-#define BS_RTC_WAR_IERW (1U) //!< Bit field size in bits for RTC_WAR_IERW.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_WAR_IERW field.
-#define BR_RTC_WAR_IERW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_IERW))
-#endif
-
-//! @brief Format value for bitfield RTC_WAR_IERW.
-#define BF_RTC_WAR_IERW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_IERW), uint32_t) & BM_RTC_WAR_IERW)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IERW field to a new value.
-#define BW_RTC_WAR_IERW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_IERW) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_RTC_RAR - RTC Read Access Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_RTC_RAR - RTC Read Access Register (RW)
- *
- * Reset value: 0x000000FFU
- */
-typedef union _hw_rtc_rar
-{
- uint32_t U;
- struct _hw_rtc_rar_bitfields
- {
- uint32_t TSRR : 1; //!< [0] Time Seconds Register Read
- uint32_t TPRR : 1; //!< [1] Time Prescaler Register Read
- uint32_t TARR : 1; //!< [2] Time Alarm Register Read
- uint32_t TCRR : 1; //!< [3] Time Compensation Register Read
- uint32_t CRR : 1; //!< [4] Control Register Read
- uint32_t SRR : 1; //!< [5] Status Register Read
- uint32_t LRR : 1; //!< [6] Lock Register Read
- uint32_t IERR : 1; //!< [7] Interrupt Enable Register Read
- uint32_t RESERVED0 : 24; //!< [31:8]
- } B;
-} hw_rtc_rar_t;
-#endif
-
-/*!
- * @name Constants and macros for entire RTC_RAR register
- */
-//@{
-#define HW_RTC_RAR_ADDR (REGS_RTC_BASE + 0x804U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_RTC_RAR (*(__IO hw_rtc_rar_t *) HW_RTC_RAR_ADDR)
-#define HW_RTC_RAR_RD() (HW_RTC_RAR.U)
-#define HW_RTC_RAR_WR(v) (HW_RTC_RAR.U = (v))
-#define HW_RTC_RAR_SET(v) (HW_RTC_RAR_WR(HW_RTC_RAR_RD() | (v)))
-#define HW_RTC_RAR_CLR(v) (HW_RTC_RAR_WR(HW_RTC_RAR_RD() & ~(v)))
-#define HW_RTC_RAR_TOG(v) (HW_RTC_RAR_WR(HW_RTC_RAR_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual RTC_RAR bitfields
- */
-
-/*!
- * @name Register RTC_RAR, field TSRR[0] (RW)
- *
- * After being cleared, this bit is set only by system reset. It is not affected
- * by VBAT POR or software reset.
- *
- * Values:
- * - 0 - Reads to the Time Seconds Register are ignored.
- * - 1 - Reads to the Time Seconds Register complete as normal.
- */
-//@{
-#define BP_RTC_RAR_TSRR (0U) //!< Bit position for RTC_RAR_TSRR.
-#define BM_RTC_RAR_TSRR (0x00000001U) //!< Bit mask for RTC_RAR_TSRR.
-#define BS_RTC_RAR_TSRR (1U) //!< Bit field size in bits for RTC_RAR_TSRR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_RAR_TSRR field.
-#define BR_RTC_RAR_TSRR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TSRR))
-#endif
-
-//! @brief Format value for bitfield RTC_RAR_TSRR.
-#define BF_RTC_RAR_TSRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_TSRR), uint32_t) & BM_RTC_RAR_TSRR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TSRR field to a new value.
-#define BW_RTC_RAR_TSRR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TSRR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_RAR, field TPRR[1] (RW)
- *
- * After being cleared, this bit is set only by system reset. It is not affected
- * by VBAT POR or software reset.
- *
- * Values:
- * - 0 - Reads to the Time Pprescaler Register are ignored.
- * - 1 - Reads to the Time Prescaler Register complete as normal.
- */
-//@{
-#define BP_RTC_RAR_TPRR (1U) //!< Bit position for RTC_RAR_TPRR.
-#define BM_RTC_RAR_TPRR (0x00000002U) //!< Bit mask for RTC_RAR_TPRR.
-#define BS_RTC_RAR_TPRR (1U) //!< Bit field size in bits for RTC_RAR_TPRR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_RAR_TPRR field.
-#define BR_RTC_RAR_TPRR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TPRR))
-#endif
-
-//! @brief Format value for bitfield RTC_RAR_TPRR.
-#define BF_RTC_RAR_TPRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_TPRR), uint32_t) & BM_RTC_RAR_TPRR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TPRR field to a new value.
-#define BW_RTC_RAR_TPRR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TPRR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_RAR, field TARR[2] (RW)
- *
- * After being cleared, this bit is set only by system reset. It is not affected
- * by VBAT POR or software reset.
- *
- * Values:
- * - 0 - Reads to the Time Alarm Register are ignored.
- * - 1 - Reads to the Time Alarm Register complete as normal.
- */
-//@{
-#define BP_RTC_RAR_TARR (2U) //!< Bit position for RTC_RAR_TARR.
-#define BM_RTC_RAR_TARR (0x00000004U) //!< Bit mask for RTC_RAR_TARR.
-#define BS_RTC_RAR_TARR (1U) //!< Bit field size in bits for RTC_RAR_TARR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_RAR_TARR field.
-#define BR_RTC_RAR_TARR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TARR))
-#endif
-
-//! @brief Format value for bitfield RTC_RAR_TARR.
-#define BF_RTC_RAR_TARR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_TARR), uint32_t) & BM_RTC_RAR_TARR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TARR field to a new value.
-#define BW_RTC_RAR_TARR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TARR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_RAR, field TCRR[3] (RW)
- *
- * After being cleared, this bit is set only by system reset. It is not affected
- * by VBAT POR or software reset.
- *
- * Values:
- * - 0 - Reads to the Time Compensation Register are ignored.
- * - 1 - Reads to the Time Compensation Register complete as normal.
- */
-//@{
-#define BP_RTC_RAR_TCRR (3U) //!< Bit position for RTC_RAR_TCRR.
-#define BM_RTC_RAR_TCRR (0x00000008U) //!< Bit mask for RTC_RAR_TCRR.
-#define BS_RTC_RAR_TCRR (1U) //!< Bit field size in bits for RTC_RAR_TCRR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_RAR_TCRR field.
-#define BR_RTC_RAR_TCRR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TCRR))
-#endif
-
-//! @brief Format value for bitfield RTC_RAR_TCRR.
-#define BF_RTC_RAR_TCRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_TCRR), uint32_t) & BM_RTC_RAR_TCRR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TCRR field to a new value.
-#define BW_RTC_RAR_TCRR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TCRR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_RAR, field CRR[4] (RW)
- *
- * After being cleared, this bit is set only by system reset. It is not affected
- * by VBAT POR or software reset.
- *
- * Values:
- * - 0 - Reads to the Control Register are ignored.
- * - 1 - Reads to the Control Register complete as normal.
- */
-//@{
-#define BP_RTC_RAR_CRR (4U) //!< Bit position for RTC_RAR_CRR.
-#define BM_RTC_RAR_CRR (0x00000010U) //!< Bit mask for RTC_RAR_CRR.
-#define BS_RTC_RAR_CRR (1U) //!< Bit field size in bits for RTC_RAR_CRR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_RAR_CRR field.
-#define BR_RTC_RAR_CRR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_CRR))
-#endif
-
-//! @brief Format value for bitfield RTC_RAR_CRR.
-#define BF_RTC_RAR_CRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_CRR), uint32_t) & BM_RTC_RAR_CRR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CRR field to a new value.
-#define BW_RTC_RAR_CRR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_CRR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_RAR, field SRR[5] (RW)
- *
- * After being cleared, this bit is set only by system reset. It is not affected
- * by VBAT POR or software reset.
- *
- * Values:
- * - 0 - Reads to the Status Register are ignored.
- * - 1 - Reads to the Status Register complete as normal.
- */
-//@{
-#define BP_RTC_RAR_SRR (5U) //!< Bit position for RTC_RAR_SRR.
-#define BM_RTC_RAR_SRR (0x00000020U) //!< Bit mask for RTC_RAR_SRR.
-#define BS_RTC_RAR_SRR (1U) //!< Bit field size in bits for RTC_RAR_SRR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_RAR_SRR field.
-#define BR_RTC_RAR_SRR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_SRR))
-#endif
-
-//! @brief Format value for bitfield RTC_RAR_SRR.
-#define BF_RTC_RAR_SRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_SRR), uint32_t) & BM_RTC_RAR_SRR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SRR field to a new value.
-#define BW_RTC_RAR_SRR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_SRR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_RAR, field LRR[6] (RW)
- *
- * After being cleared, this bit is set only by system reset. It is not affected
- * by VBAT POR or software reset.
- *
- * Values:
- * - 0 - Reads to the Lock Register are ignored.
- * - 1 - Reads to the Lock Register complete as normal.
- */
-//@{
-#define BP_RTC_RAR_LRR (6U) //!< Bit position for RTC_RAR_LRR.
-#define BM_RTC_RAR_LRR (0x00000040U) //!< Bit mask for RTC_RAR_LRR.
-#define BS_RTC_RAR_LRR (1U) //!< Bit field size in bits for RTC_RAR_LRR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_RAR_LRR field.
-#define BR_RTC_RAR_LRR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_LRR))
-#endif
-
-//! @brief Format value for bitfield RTC_RAR_LRR.
-#define BF_RTC_RAR_LRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_LRR), uint32_t) & BM_RTC_RAR_LRR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LRR field to a new value.
-#define BW_RTC_RAR_LRR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_LRR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register RTC_RAR, field IERR[7] (RW)
- *
- * After being cleared, this bit is set only by system reset. It is not affected
- * by VBAT POR or software reset.
- *
- * Values:
- * - 0 - Reads to the Interrupt Enable Register are ignored.
- * - 1 - Reads to the Interrupt Enable Register complete as normal.
- */
-//@{
-#define BP_RTC_RAR_IERR (7U) //!< Bit position for RTC_RAR_IERR.
-#define BM_RTC_RAR_IERR (0x00000080U) //!< Bit mask for RTC_RAR_IERR.
-#define BS_RTC_RAR_IERR (1U) //!< Bit field size in bits for RTC_RAR_IERR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the RTC_RAR_IERR field.
-#define BR_RTC_RAR_IERR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_IERR))
-#endif
-
-//! @brief Format value for bitfield RTC_RAR_IERR.
-#define BF_RTC_RAR_IERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_IERR), uint32_t) & BM_RTC_RAR_IERR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IERR field to a new value.
-#define BW_RTC_RAR_IERR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_IERR) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_rtc_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All RTC module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_rtc
-{
- __IO hw_rtc_tsr_t TSR; //!< [0x0] RTC Time Seconds Register
- __IO hw_rtc_tpr_t TPR; //!< [0x4] RTC Time Prescaler Register
- __IO hw_rtc_tar_t TAR; //!< [0x8] RTC Time Alarm Register
- __IO hw_rtc_tcr_t TCR; //!< [0xC] RTC Time Compensation Register
- __IO hw_rtc_cr_t CR; //!< [0x10] RTC Control Register
- __IO hw_rtc_sr_t SR; //!< [0x14] RTC Status Register
- __IO hw_rtc_lr_t LR; //!< [0x18] RTC Lock Register
- __IO hw_rtc_ier_t IER; //!< [0x1C] RTC Interrupt Enable Register
- uint8_t _reserved0[2016];
- __IO hw_rtc_war_t WAR; //!< [0x800] RTC Write Access Register
- __IO hw_rtc_rar_t RAR; //!< [0x804] RTC Read Access Register
-} hw_rtc_t;
-#pragma pack()
-
-//! @brief Macro to access all RTC registers.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_RTC</code>.
-#define HW_RTC (*(hw_rtc_t *) REGS_RTC_BASE)
-#endif
-
-#endif // __HW_RTC_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_sdhc.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,5761 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_SDHC_REGISTERS_H__
-#define __HW_SDHC_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 SDHC
- *
- * Secured Digital Host Controller
- *
- * Registers defined in this header file:
- * - HW_SDHC_DSADDR - DMA System Address register
- * - HW_SDHC_BLKATTR - Block Attributes register
- * - HW_SDHC_CMDARG - Command Argument register
- * - HW_SDHC_XFERTYP - Transfer Type register
- * - HW_SDHC_CMDRSP0 - Command Response 0
- * - HW_SDHC_CMDRSP1 - Command Response 1
- * - HW_SDHC_CMDRSP2 - Command Response 2
- * - HW_SDHC_CMDRSP3 - Command Response 3
- * - HW_SDHC_DATPORT - Buffer Data Port register
- * - HW_SDHC_PRSSTAT - Present State register
- * - HW_SDHC_PROCTL - Protocol Control register
- * - HW_SDHC_SYSCTL - System Control register
- * - HW_SDHC_IRQSTAT - Interrupt Status register
- * - HW_SDHC_IRQSTATEN - Interrupt Status Enable register
- * - HW_SDHC_IRQSIGEN - Interrupt Signal Enable register
- * - HW_SDHC_AC12ERR - Auto CMD12 Error Status Register
- * - HW_SDHC_HTCAPBLT - Host Controller Capabilities
- * - HW_SDHC_WML - Watermark Level Register
- * - HW_SDHC_FEVT - Force Event register
- * - HW_SDHC_ADMAES - ADMA Error Status register
- * - HW_SDHC_ADSADDR - ADMA System Addressregister
- * - HW_SDHC_VENDOR - Vendor Specific register
- * - HW_SDHC_MMCBOOT - MMC Boot register
- * - HW_SDHC_HOSTVER - Host Controller Version
- *
- * - hw_sdhc_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_SDHC_BASE
-#define HW_SDHC_INSTANCE_COUNT (1U) //!< Number of instances of the SDHC module.
-#define REGS_SDHC_BASE (0x400B1000U) //!< Base address for SDHC.
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SDHC_DSADDR - DMA System Address register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SDHC_DSADDR - DMA System Address register (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register contains the physical system memory address used for DMA
- * transfers.
- */
-typedef union _hw_sdhc_dsaddr
-{
- uint32_t U;
- struct _hw_sdhc_dsaddr_bitfields
- {
- uint32_t RESERVED0 : 2; //!< [1:0]
- uint32_t DSADDR : 30; //!< [31:2] DMA System Address
- } B;
-} hw_sdhc_dsaddr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SDHC_DSADDR register
- */
-//@{
-#define HW_SDHC_DSADDR_ADDR (REGS_SDHC_BASE + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SDHC_DSADDR (*(__IO hw_sdhc_dsaddr_t *) HW_SDHC_DSADDR_ADDR)
-#define HW_SDHC_DSADDR_RD() (HW_SDHC_DSADDR.U)
-#define HW_SDHC_DSADDR_WR(v) (HW_SDHC_DSADDR.U = (v))
-#define HW_SDHC_DSADDR_SET(v) (HW_SDHC_DSADDR_WR(HW_SDHC_DSADDR_RD() | (v)))
-#define HW_SDHC_DSADDR_CLR(v) (HW_SDHC_DSADDR_WR(HW_SDHC_DSADDR_RD() & ~(v)))
-#define HW_SDHC_DSADDR_TOG(v) (HW_SDHC_DSADDR_WR(HW_SDHC_DSADDR_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SDHC_DSADDR bitfields
- */
-
-/*!
- * @name Register SDHC_DSADDR, field DSADDR[31:2] (RW)
- *
- * Contains the 32-bit system memory address for a DMA transfer. Because the
- * address must be word (4 bytes) align, the least 2 bits are reserved, always 0.
- * When the SDHC stops a DMA transfer, this register points to the system address
- * of the next contiguous data position. It can be accessed only when no
- * transaction is executing, that is, after a transaction has stopped. Read operation
- * during transfers may return an invalid value. The host driver shall initialize
- * this register before starting a DMA transaction. After DMA has stopped, the
- * system address of the next contiguous data position can be read from this register.
- * This register is protected during a data transfer. When data lines are
- * active, write to this register is ignored. The host driver shall wait, until
- * PRSSTAT[DLA] is cleared, before writing to this register. The SDHC internal DMA does
- * not support a virtual memory system. It supports only continuous physical
- * memory access. And due to AHB burst limitations, if the burst must cross the 1 KB
- * boundary, SDHC will automatically change SEQ burst type to NSEQ. Because this
- * register supports dynamic address reflecting, when IRQSTAT[TC] bit is set, it
- * automatically alters the value of internal address counter, so SW cannot
- * change this register when IRQSTAT[TC] is set.
- */
-//@{
-#define BP_SDHC_DSADDR_DSADDR (2U) //!< Bit position for SDHC_DSADDR_DSADDR.
-#define BM_SDHC_DSADDR_DSADDR (0xFFFFFFFCU) //!< Bit mask for SDHC_DSADDR_DSADDR.
-#define BS_SDHC_DSADDR_DSADDR (30U) //!< Bit field size in bits for SDHC_DSADDR_DSADDR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_DSADDR_DSADDR field.
-#define BR_SDHC_DSADDR_DSADDR (HW_SDHC_DSADDR.B.DSADDR)
-#endif
-
-//! @brief Format value for bitfield SDHC_DSADDR_DSADDR.
-#define BF_SDHC_DSADDR_DSADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_DSADDR_DSADDR), uint32_t) & BM_SDHC_DSADDR_DSADDR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DSADDR field to a new value.
-#define BW_SDHC_DSADDR_DSADDR(v) (HW_SDHC_DSADDR_WR((HW_SDHC_DSADDR_RD() & ~BM_SDHC_DSADDR_DSADDR) | BF_SDHC_DSADDR_DSADDR(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SDHC_BLKATTR - Block Attributes register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SDHC_BLKATTR - Block Attributes register (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register is used to configure the number of data blocks and the number
- * of bytes in each block.
- */
-typedef union _hw_sdhc_blkattr
-{
- uint32_t U;
- struct _hw_sdhc_blkattr_bitfields
- {
- uint32_t BLKSIZE : 13; //!< [12:0] Transfer Block Size
- uint32_t RESERVED0 : 3; //!< [15:13]
- uint32_t BLKCNT : 16; //!< [31:16] Blocks Count For Current Transfer
- } B;
-} hw_sdhc_blkattr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SDHC_BLKATTR register
- */
-//@{
-#define HW_SDHC_BLKATTR_ADDR (REGS_SDHC_BASE + 0x4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SDHC_BLKATTR (*(__IO hw_sdhc_blkattr_t *) HW_SDHC_BLKATTR_ADDR)
-#define HW_SDHC_BLKATTR_RD() (HW_SDHC_BLKATTR.U)
-#define HW_SDHC_BLKATTR_WR(v) (HW_SDHC_BLKATTR.U = (v))
-#define HW_SDHC_BLKATTR_SET(v) (HW_SDHC_BLKATTR_WR(HW_SDHC_BLKATTR_RD() | (v)))
-#define HW_SDHC_BLKATTR_CLR(v) (HW_SDHC_BLKATTR_WR(HW_SDHC_BLKATTR_RD() & ~(v)))
-#define HW_SDHC_BLKATTR_TOG(v) (HW_SDHC_BLKATTR_WR(HW_SDHC_BLKATTR_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SDHC_BLKATTR bitfields
- */
-
-/*!
- * @name Register SDHC_BLKATTR, field BLKSIZE[12:0] (RW)
- *
- * Specifies the block size for block data transfers. Values ranging from 1 byte
- * up to the maximum buffer size can be set. It can be accessed only when no
- * transaction is executing, that is, after a transaction has stopped. Read
- * operations during transfers may return an invalid value, and write operations will be
- * ignored.
- *
- * Values:
- * - 0 - No data transfer.
- * - 1 - 1 Byte
- * - 10 - 2 Bytes
- * - 11 - 3 Bytes
- * - 100 - 4 Bytes
- * - 111111111 - 511 Bytes
- * - 1000000000 - 512 Bytes
- * - 100000000000 - 2048 Bytes
- * - 1000000000000 - 4096 Bytes
- */
-//@{
-#define BP_SDHC_BLKATTR_BLKSIZE (0U) //!< Bit position for SDHC_BLKATTR_BLKSIZE.
-#define BM_SDHC_BLKATTR_BLKSIZE (0x00001FFFU) //!< Bit mask for SDHC_BLKATTR_BLKSIZE.
-#define BS_SDHC_BLKATTR_BLKSIZE (13U) //!< Bit field size in bits for SDHC_BLKATTR_BLKSIZE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_BLKATTR_BLKSIZE field.
-#define BR_SDHC_BLKATTR_BLKSIZE (HW_SDHC_BLKATTR.B.BLKSIZE)
-#endif
-
-//! @brief Format value for bitfield SDHC_BLKATTR_BLKSIZE.
-#define BF_SDHC_BLKATTR_BLKSIZE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_BLKATTR_BLKSIZE), uint32_t) & BM_SDHC_BLKATTR_BLKSIZE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BLKSIZE field to a new value.
-#define BW_SDHC_BLKATTR_BLKSIZE(v) (HW_SDHC_BLKATTR_WR((HW_SDHC_BLKATTR_RD() & ~BM_SDHC_BLKATTR_BLKSIZE) | BF_SDHC_BLKATTR_BLKSIZE(v)))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_BLKATTR, field BLKCNT[31:16] (RW)
- *
- * This register is enabled when XFERTYP[BCEN] is set to 1 and is valid only for
- * multiple block transfers. For single block transfer, this register will
- * always read as 1. The host driver shall set this register to a value between 1 and
- * the maximum block count. The SDHC decrements the block count after each block
- * transfer and stops when the count reaches zero. Setting the block count to 0
- * results in no data blocks being transferred. This register must be accessed
- * only when no transaction is executing, that is, after transactions are stopped.
- * During data transfer, read operations on this register may return an invalid
- * value and write operations are ignored. When saving transfer content as a result
- * of a suspend command, the number of blocks yet to be transferred can be
- * determined by reading this register. The reading of this register must be applied
- * after transfer is paused by stop at block gap operation and before sending the
- * command marked as suspend. This is because when suspend command is sent out,
- * SDHC will regard the current transfer as aborted and change BLKCNT back to its
- * original value instead of keeping the dynamical indicator of remained block
- * count. When restoring transfer content prior to issuing a resume command, the
- * host driver shall restore the previously saved block count. Although the BLKCNT
- * field is 0 after reset, the read of reset value is 0x1. This is because when
- * XFERTYP[MSBSEL] is 0, indicating a single block transfer, the read value of
- * BLKCNT is always 1.
- *
- * Values:
- * - 0 - Stop count.
- * - 1 - 1 block
- * - 10 - 2 blocks
- * - 1111111111111111 - 65535 blocks
- */
-//@{
-#define BP_SDHC_BLKATTR_BLKCNT (16U) //!< Bit position for SDHC_BLKATTR_BLKCNT.
-#define BM_SDHC_BLKATTR_BLKCNT (0xFFFF0000U) //!< Bit mask for SDHC_BLKATTR_BLKCNT.
-#define BS_SDHC_BLKATTR_BLKCNT (16U) //!< Bit field size in bits for SDHC_BLKATTR_BLKCNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_BLKATTR_BLKCNT field.
-#define BR_SDHC_BLKATTR_BLKCNT (HW_SDHC_BLKATTR.B.BLKCNT)
-#endif
-
-//! @brief Format value for bitfield SDHC_BLKATTR_BLKCNT.
-#define BF_SDHC_BLKATTR_BLKCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_BLKATTR_BLKCNT), uint32_t) & BM_SDHC_BLKATTR_BLKCNT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BLKCNT field to a new value.
-#define BW_SDHC_BLKATTR_BLKCNT(v) (HW_SDHC_BLKATTR_WR((HW_SDHC_BLKATTR_RD() & ~BM_SDHC_BLKATTR_BLKCNT) | BF_SDHC_BLKATTR_BLKCNT(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SDHC_CMDARG - Command Argument register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SDHC_CMDARG - Command Argument register (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register contains the SD/MMC command argument.
- */
-typedef union _hw_sdhc_cmdarg
-{
- uint32_t U;
- struct _hw_sdhc_cmdarg_bitfields
- {
- uint32_t CMDARG : 32; //!< [31:0] Command Argument
- } B;
-} hw_sdhc_cmdarg_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SDHC_CMDARG register
- */
-//@{
-#define HW_SDHC_CMDARG_ADDR (REGS_SDHC_BASE + 0x8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SDHC_CMDARG (*(__IO hw_sdhc_cmdarg_t *) HW_SDHC_CMDARG_ADDR)
-#define HW_SDHC_CMDARG_RD() (HW_SDHC_CMDARG.U)
-#define HW_SDHC_CMDARG_WR(v) (HW_SDHC_CMDARG.U = (v))
-#define HW_SDHC_CMDARG_SET(v) (HW_SDHC_CMDARG_WR(HW_SDHC_CMDARG_RD() | (v)))
-#define HW_SDHC_CMDARG_CLR(v) (HW_SDHC_CMDARG_WR(HW_SDHC_CMDARG_RD() & ~(v)))
-#define HW_SDHC_CMDARG_TOG(v) (HW_SDHC_CMDARG_WR(HW_SDHC_CMDARG_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SDHC_CMDARG bitfields
- */
-
-/*!
- * @name Register SDHC_CMDARG, field CMDARG[31:0] (RW)
- *
- * The SD/MMC command argument is specified as bits 39-8 of the command format
- * in the SD or MMC specification. This register is write protected when
- * PRSSTAT[CDIHB0] is set.
- */
-//@{
-#define BP_SDHC_CMDARG_CMDARG (0U) //!< Bit position for SDHC_CMDARG_CMDARG.
-#define BM_SDHC_CMDARG_CMDARG (0xFFFFFFFFU) //!< Bit mask for SDHC_CMDARG_CMDARG.
-#define BS_SDHC_CMDARG_CMDARG (32U) //!< Bit field size in bits for SDHC_CMDARG_CMDARG.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_CMDARG_CMDARG field.
-#define BR_SDHC_CMDARG_CMDARG (HW_SDHC_CMDARG.U)
-#endif
-
-//! @brief Format value for bitfield SDHC_CMDARG_CMDARG.
-#define BF_SDHC_CMDARG_CMDARG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_CMDARG_CMDARG), uint32_t) & BM_SDHC_CMDARG_CMDARG)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CMDARG field to a new value.
-#define BW_SDHC_CMDARG_CMDARG(v) (HW_SDHC_CMDARG_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SDHC_XFERTYP - Transfer Type register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SDHC_XFERTYP - Transfer Type register (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register is used to control the operation of data transfers. The host
- * driver shall set this register before issuing a command followed by a data
- * transfer, or before issuing a resume command. To prevent data loss, the SDHC
- * prevents writing to the bits that are involved in the data transfer of this
- * register, when data transfer is active. These bits are DPSEL, MBSEL, DTDSEL, AC12EN,
- * BCEN, and DMAEN. The host driver shall check PRSSTAT[CDIHB] and PRSSTAT[CIHB]
- * before writing to this register. When PRSSTAT[CDIHB] is set, any attempt to
- * send a command with data by writing to this register is ignored; when
- * PRSSTAT[CIHB] bit is set, any write to this register is ignored. On sending commands with
- * data transfer involved, it is mandatory that the block size is nonzero.
- * Besides, block count must also be nonzero, or indicated as single block transfer
- * (bit 5 of this register is 0 when written), or block count is disabled (bit 1 of
- * this register is 0 when written), otherwise SDHC will ignore the sending of
- * this command and do nothing. For write command, with all above restrictions, it
- * is also mandatory that the write protect switch is not active (WPSPL bit of
- * Present State Register is 1), otherwise SDHC will also ignore the command. If
- * the commands with data transfer does not receive the response in 64 clock
- * cycles, that is, response time-out, SDHC will regard the external device does not
- * accept the command and abort the data transfer. In this scenario, the driver
- * must issue the command again to retry the transfer. It is also possible that,
- * for some reason, the card responds to the command but SDHC does not receive the
- * response, and if it is internal DMA (either simple DMA or ADMA) read
- * operation, the external system memory is over-written by the internal DMA with data
- * sent back from the card. The following table shows the summary of how register
- * settings determine the type of data transfer. Transfer Type register setting for
- * various transfer types Multi/Single block select Block count enable Block
- * count Function 0 Don't care Don't care Single transfer 1 0 Don't care Infinite
- * transfer 1 1 Positive number Multiple transfer 1 1 Zero No data transfer The
- * following table shows the relationship between XFERTYP[CICEN] and XFERTYP[CCCEN],
- * in regards to XFERTYP[RSPTYP] as well as the name of the response type.
- * Relationship between parameters and the name of the response type Response type
- * (RSPTYP) Index check enable (CICEN) CRC check enable (CCCEN) Name of response
- * type 00 0 0 No Response 01 0 1 IR2 10 0 0 R3,R4 10 1 1 R1,R5,R6 11 1 1 R1b,R5b In
- * the SDIO specification, response type notation for R5b is not defined. R5
- * includes R5b in the SDIO specification. But R5b is defined in this specification
- * to specify that the SDHC will check the busy status after receiving a
- * response. For example, usually CMD52 is used with R5, but the I/O abort command shall
- * be used with R5b. The CRC field for R3 and R4 is expected to be all 1 bits.
- * The CRC check shall be disabled for these response types.
- */
-typedef union _hw_sdhc_xfertyp
-{
- uint32_t U;
- struct _hw_sdhc_xfertyp_bitfields
- {
- uint32_t DMAEN : 1; //!< [0] DMA Enable
- uint32_t BCEN : 1; //!< [1] Block Count Enable
- uint32_t AC12EN : 1; //!< [2] Auto CMD12 Enable
- uint32_t RESERVED0 : 1; //!< [3]
- uint32_t DTDSEL : 1; //!< [4] Data Transfer Direction Select
- uint32_t MSBSEL : 1; //!< [5] Multi/Single Block Select
- uint32_t RESERVED1 : 10; //!< [15:6]
- uint32_t RSPTYP : 2; //!< [17:16] Response Type Select
- uint32_t RESERVED2 : 1; //!< [18]
- uint32_t CCCEN : 1; //!< [19] Command CRC Check Enable
- uint32_t CICEN : 1; //!< [20] Command Index Check Enable
- uint32_t DPSEL : 1; //!< [21] Data Present Select
- uint32_t CMDTYP : 2; //!< [23:22] Command Type
- uint32_t CMDINX : 6; //!< [29:24] Command Index
- uint32_t RESERVED3 : 2; //!< [31:30]
- } B;
-} hw_sdhc_xfertyp_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SDHC_XFERTYP register
- */
-//@{
-#define HW_SDHC_XFERTYP_ADDR (REGS_SDHC_BASE + 0xCU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SDHC_XFERTYP (*(__IO hw_sdhc_xfertyp_t *) HW_SDHC_XFERTYP_ADDR)
-#define HW_SDHC_XFERTYP_RD() (HW_SDHC_XFERTYP.U)
-#define HW_SDHC_XFERTYP_WR(v) (HW_SDHC_XFERTYP.U = (v))
-#define HW_SDHC_XFERTYP_SET(v) (HW_SDHC_XFERTYP_WR(HW_SDHC_XFERTYP_RD() | (v)))
-#define HW_SDHC_XFERTYP_CLR(v) (HW_SDHC_XFERTYP_WR(HW_SDHC_XFERTYP_RD() & ~(v)))
-#define HW_SDHC_XFERTYP_TOG(v) (HW_SDHC_XFERTYP_WR(HW_SDHC_XFERTYP_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SDHC_XFERTYP bitfields
- */
-
-/*!
- * @name Register SDHC_XFERTYP, field DMAEN[0] (RW)
- *
- * Enables DMA functionality. If this bit is set to 1, a DMA operation shall
- * begin when the host driver sets the DPSEL bit of this register. Whether the
- * simple DMA, or the advanced DMA, is active depends on PROCTL[DMAS].
- *
- * Values:
- * - 0 - Disable
- * - 1 - Enable
- */
-//@{
-#define BP_SDHC_XFERTYP_DMAEN (0U) //!< Bit position for SDHC_XFERTYP_DMAEN.
-#define BM_SDHC_XFERTYP_DMAEN (0x00000001U) //!< Bit mask for SDHC_XFERTYP_DMAEN.
-#define BS_SDHC_XFERTYP_DMAEN (1U) //!< Bit field size in bits for SDHC_XFERTYP_DMAEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_XFERTYP_DMAEN field.
-#define BR_SDHC_XFERTYP_DMAEN (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DMAEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_XFERTYP_DMAEN.
-#define BF_SDHC_XFERTYP_DMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_DMAEN), uint32_t) & BM_SDHC_XFERTYP_DMAEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DMAEN field to a new value.
-#define BW_SDHC_XFERTYP_DMAEN(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DMAEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_XFERTYP, field BCEN[1] (RW)
- *
- * Used to enable the Block Count register, which is only relevant for multiple
- * block transfers. When this bit is 0, the internal counter for block is
- * disabled, which is useful in executing an infinite transfer.
- *
- * Values:
- * - 0 - Disable
- * - 1 - Enable
- */
-//@{
-#define BP_SDHC_XFERTYP_BCEN (1U) //!< Bit position for SDHC_XFERTYP_BCEN.
-#define BM_SDHC_XFERTYP_BCEN (0x00000002U) //!< Bit mask for SDHC_XFERTYP_BCEN.
-#define BS_SDHC_XFERTYP_BCEN (1U) //!< Bit field size in bits for SDHC_XFERTYP_BCEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_XFERTYP_BCEN field.
-#define BR_SDHC_XFERTYP_BCEN (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_BCEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_XFERTYP_BCEN.
-#define BF_SDHC_XFERTYP_BCEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_BCEN), uint32_t) & BM_SDHC_XFERTYP_BCEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BCEN field to a new value.
-#define BW_SDHC_XFERTYP_BCEN(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_BCEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_XFERTYP, field AC12EN[2] (RW)
- *
- * Multiple block transfers for memory require a CMD12 to stop the transaction.
- * When this bit is set to 1, the SDHC will issue a CMD12 automatically when the
- * last block transfer has completed. The host driver shall not set this bit to
- * issue commands that do not require CMD12 to stop a multiple block data
- * transfer. In particular, secure commands defined in File Security Specification (see
- * reference list) do not require CMD12. In single block transfer, the SDHC will
- * ignore this bit whether it is set or not.
- *
- * Values:
- * - 0 - Disable
- * - 1 - Enable
- */
-//@{
-#define BP_SDHC_XFERTYP_AC12EN (2U) //!< Bit position for SDHC_XFERTYP_AC12EN.
-#define BM_SDHC_XFERTYP_AC12EN (0x00000004U) //!< Bit mask for SDHC_XFERTYP_AC12EN.
-#define BS_SDHC_XFERTYP_AC12EN (1U) //!< Bit field size in bits for SDHC_XFERTYP_AC12EN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_XFERTYP_AC12EN field.
-#define BR_SDHC_XFERTYP_AC12EN (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_AC12EN))
-#endif
-
-//! @brief Format value for bitfield SDHC_XFERTYP_AC12EN.
-#define BF_SDHC_XFERTYP_AC12EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_AC12EN), uint32_t) & BM_SDHC_XFERTYP_AC12EN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the AC12EN field to a new value.
-#define BW_SDHC_XFERTYP_AC12EN(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_AC12EN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_XFERTYP, field DTDSEL[4] (RW)
- *
- * Defines the direction of DAT line data transfers. The bit is set to 1 by the
- * host driver to transfer data from the SD card to the SDHC and is set to 0 for
- * all other commands.
- *
- * Values:
- * - 0 - Write host to card.
- * - 1 - Read card to host.
- */
-//@{
-#define BP_SDHC_XFERTYP_DTDSEL (4U) //!< Bit position for SDHC_XFERTYP_DTDSEL.
-#define BM_SDHC_XFERTYP_DTDSEL (0x00000010U) //!< Bit mask for SDHC_XFERTYP_DTDSEL.
-#define BS_SDHC_XFERTYP_DTDSEL (1U) //!< Bit field size in bits for SDHC_XFERTYP_DTDSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_XFERTYP_DTDSEL field.
-#define BR_SDHC_XFERTYP_DTDSEL (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DTDSEL))
-#endif
-
-//! @brief Format value for bitfield SDHC_XFERTYP_DTDSEL.
-#define BF_SDHC_XFERTYP_DTDSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_DTDSEL), uint32_t) & BM_SDHC_XFERTYP_DTDSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DTDSEL field to a new value.
-#define BW_SDHC_XFERTYP_DTDSEL(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DTDSEL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_XFERTYP, field MSBSEL[5] (RW)
- *
- * Enables multiple block DAT line data transfers. For any other commands, this
- * bit shall be set to 0. If this bit is 0, it is not necessary to set the block
- * count register.
- *
- * Values:
- * - 0 - Single block.
- * - 1 - Multiple blocks.
- */
-//@{
-#define BP_SDHC_XFERTYP_MSBSEL (5U) //!< Bit position for SDHC_XFERTYP_MSBSEL.
-#define BM_SDHC_XFERTYP_MSBSEL (0x00000020U) //!< Bit mask for SDHC_XFERTYP_MSBSEL.
-#define BS_SDHC_XFERTYP_MSBSEL (1U) //!< Bit field size in bits for SDHC_XFERTYP_MSBSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_XFERTYP_MSBSEL field.
-#define BR_SDHC_XFERTYP_MSBSEL (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_MSBSEL))
-#endif
-
-//! @brief Format value for bitfield SDHC_XFERTYP_MSBSEL.
-#define BF_SDHC_XFERTYP_MSBSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_MSBSEL), uint32_t) & BM_SDHC_XFERTYP_MSBSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MSBSEL field to a new value.
-#define BW_SDHC_XFERTYP_MSBSEL(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_MSBSEL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_XFERTYP, field RSPTYP[17:16] (RW)
- *
- * Values:
- * - 00 - No response.
- * - 01 - Response length 136.
- * - 10 - Response length 48.
- * - 11 - Response length 48, check busy after response.
- */
-//@{
-#define BP_SDHC_XFERTYP_RSPTYP (16U) //!< Bit position for SDHC_XFERTYP_RSPTYP.
-#define BM_SDHC_XFERTYP_RSPTYP (0x00030000U) //!< Bit mask for SDHC_XFERTYP_RSPTYP.
-#define BS_SDHC_XFERTYP_RSPTYP (2U) //!< Bit field size in bits for SDHC_XFERTYP_RSPTYP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_XFERTYP_RSPTYP field.
-#define BR_SDHC_XFERTYP_RSPTYP (HW_SDHC_XFERTYP.B.RSPTYP)
-#endif
-
-//! @brief Format value for bitfield SDHC_XFERTYP_RSPTYP.
-#define BF_SDHC_XFERTYP_RSPTYP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_RSPTYP), uint32_t) & BM_SDHC_XFERTYP_RSPTYP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RSPTYP field to a new value.
-#define BW_SDHC_XFERTYP_RSPTYP(v) (HW_SDHC_XFERTYP_WR((HW_SDHC_XFERTYP_RD() & ~BM_SDHC_XFERTYP_RSPTYP) | BF_SDHC_XFERTYP_RSPTYP(v)))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_XFERTYP, field CCCEN[19] (RW)
- *
- * If this bit is set to 1, the SDHC shall check the CRC field in the response.
- * If an error is detected, it is reported as a Command CRC Error. If this bit is
- * set to 0, the CRC field is not checked. The number of bits checked by the CRC
- * field value changes according to the length of the response.
- *
- * Values:
- * - 0 - Disable
- * - 1 - Enable
- */
-//@{
-#define BP_SDHC_XFERTYP_CCCEN (19U) //!< Bit position for SDHC_XFERTYP_CCCEN.
-#define BM_SDHC_XFERTYP_CCCEN (0x00080000U) //!< Bit mask for SDHC_XFERTYP_CCCEN.
-#define BS_SDHC_XFERTYP_CCCEN (1U) //!< Bit field size in bits for SDHC_XFERTYP_CCCEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_XFERTYP_CCCEN field.
-#define BR_SDHC_XFERTYP_CCCEN (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_CCCEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_XFERTYP_CCCEN.
-#define BF_SDHC_XFERTYP_CCCEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_CCCEN), uint32_t) & BM_SDHC_XFERTYP_CCCEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CCCEN field to a new value.
-#define BW_SDHC_XFERTYP_CCCEN(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_CCCEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_XFERTYP, field CICEN[20] (RW)
- *
- * If this bit is set to 1, the SDHC will check the index field in the response
- * to see if it has the same value as the command index. If it is not, it is
- * reported as a command index error. If this bit is set to 0, the index field is not
- * checked.
- *
- * Values:
- * - 0 - Disable
- * - 1 - Enable
- */
-//@{
-#define BP_SDHC_XFERTYP_CICEN (20U) //!< Bit position for SDHC_XFERTYP_CICEN.
-#define BM_SDHC_XFERTYP_CICEN (0x00100000U) //!< Bit mask for SDHC_XFERTYP_CICEN.
-#define BS_SDHC_XFERTYP_CICEN (1U) //!< Bit field size in bits for SDHC_XFERTYP_CICEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_XFERTYP_CICEN field.
-#define BR_SDHC_XFERTYP_CICEN (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_CICEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_XFERTYP_CICEN.
-#define BF_SDHC_XFERTYP_CICEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_CICEN), uint32_t) & BM_SDHC_XFERTYP_CICEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CICEN field to a new value.
-#define BW_SDHC_XFERTYP_CICEN(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_CICEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_XFERTYP, field DPSEL[21] (RW)
- *
- * This bit is set to 1 to indicate that data is present and shall be
- * transferred using the DAT line. It is set to 0 for the following: Commands using only
- * the CMD line, for example: CMD52. Commands with no data transfer, but using the
- * busy signal on DAT[0] line, R1b or R5b, for example: CMD38. In resume command,
- * this bit shall be set, and other bits in this register shall be set the same
- * as when the transfer was initially launched. When the Write Protect switch is
- * on, that is, the WPSPL bit is active as 0, any command with a write operation
- * will be ignored. That is to say, when this bit is set, while the DTDSEL bit is
- * 0, writes to the register Transfer Type are ignored.
- *
- * Values:
- * - 0 - No data present.
- * - 1 - Data present.
- */
-//@{
-#define BP_SDHC_XFERTYP_DPSEL (21U) //!< Bit position for SDHC_XFERTYP_DPSEL.
-#define BM_SDHC_XFERTYP_DPSEL (0x00200000U) //!< Bit mask for SDHC_XFERTYP_DPSEL.
-#define BS_SDHC_XFERTYP_DPSEL (1U) //!< Bit field size in bits for SDHC_XFERTYP_DPSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_XFERTYP_DPSEL field.
-#define BR_SDHC_XFERTYP_DPSEL (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DPSEL))
-#endif
-
-//! @brief Format value for bitfield SDHC_XFERTYP_DPSEL.
-#define BF_SDHC_XFERTYP_DPSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_DPSEL), uint32_t) & BM_SDHC_XFERTYP_DPSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DPSEL field to a new value.
-#define BW_SDHC_XFERTYP_DPSEL(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DPSEL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_XFERTYP, field CMDTYP[23:22] (RW)
- *
- * There are three types of special commands: suspend, resume, and abort. These
- * bits shall be set to 00b for all other commands. Suspend command: If the
- * suspend command succeeds, the SDHC shall assume that the card bus has been released
- * and that it is possible to issue the next command which uses the DAT line.
- * Because the SDHC does not monitor the content of command response, it does not
- * know if the suspend command succeeded or not. It is the host driver's
- * responsibility to check the status of the suspend command and send another command
- * marked as suspend to inform the SDHC that a suspend command was successfully
- * issued. After the end bit of command is sent, the SDHC deasserts read wait for read
- * transactions and stops checking busy for write transactions. In 4-bit mode,
- * the interrupt cycle starts. If the suspend command fails, the SDHC will
- * maintain its current state, and the host driver shall restart the transfer by setting
- * PROCTL[CREQ]. Resume command: The host driver restarts the data transfer by
- * restoring the registers saved before sending the suspend command and then sends
- * the resume command. The SDHC will check for a pending busy state before
- * starting write transfers. Abort command: If this command is set when executing a
- * read transfer, the SDHC will stop reads to the buffer. If this command is set
- * when executing a write transfer, the SDHC will stop driving the DAT line. After
- * issuing the abort command, the host driver must issue a software reset (abort
- * transaction).
- *
- * Values:
- * - 00 - Normal other commands.
- * - 01 - Suspend CMD52 for writing bus suspend in CCCR.
- * - 10 - Resume CMD52 for writing function select in CCCR.
- * - 11 - Abort CMD12, CMD52 for writing I/O abort in CCCR.
- */
-//@{
-#define BP_SDHC_XFERTYP_CMDTYP (22U) //!< Bit position for SDHC_XFERTYP_CMDTYP.
-#define BM_SDHC_XFERTYP_CMDTYP (0x00C00000U) //!< Bit mask for SDHC_XFERTYP_CMDTYP.
-#define BS_SDHC_XFERTYP_CMDTYP (2U) //!< Bit field size in bits for SDHC_XFERTYP_CMDTYP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_XFERTYP_CMDTYP field.
-#define BR_SDHC_XFERTYP_CMDTYP (HW_SDHC_XFERTYP.B.CMDTYP)
-#endif
-
-//! @brief Format value for bitfield SDHC_XFERTYP_CMDTYP.
-#define BF_SDHC_XFERTYP_CMDTYP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_CMDTYP), uint32_t) & BM_SDHC_XFERTYP_CMDTYP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CMDTYP field to a new value.
-#define BW_SDHC_XFERTYP_CMDTYP(v) (HW_SDHC_XFERTYP_WR((HW_SDHC_XFERTYP_RD() & ~BM_SDHC_XFERTYP_CMDTYP) | BF_SDHC_XFERTYP_CMDTYP(v)))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_XFERTYP, field CMDINX[29:24] (RW)
- *
- * These bits shall be set to the command number that is specified in bits 45-40
- * of the command-format in the SD Memory Card Physical Layer Specification and
- * SDIO Card Specification.
- */
-//@{
-#define BP_SDHC_XFERTYP_CMDINX (24U) //!< Bit position for SDHC_XFERTYP_CMDINX.
-#define BM_SDHC_XFERTYP_CMDINX (0x3F000000U) //!< Bit mask for SDHC_XFERTYP_CMDINX.
-#define BS_SDHC_XFERTYP_CMDINX (6U) //!< Bit field size in bits for SDHC_XFERTYP_CMDINX.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_XFERTYP_CMDINX field.
-#define BR_SDHC_XFERTYP_CMDINX (HW_SDHC_XFERTYP.B.CMDINX)
-#endif
-
-//! @brief Format value for bitfield SDHC_XFERTYP_CMDINX.
-#define BF_SDHC_XFERTYP_CMDINX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_CMDINX), uint32_t) & BM_SDHC_XFERTYP_CMDINX)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CMDINX field to a new value.
-#define BW_SDHC_XFERTYP_CMDINX(v) (HW_SDHC_XFERTYP_WR((HW_SDHC_XFERTYP_RD() & ~BM_SDHC_XFERTYP_CMDINX) | BF_SDHC_XFERTYP_CMDINX(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SDHC_CMDRSP0 - Command Response 0
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SDHC_CMDRSP0 - Command Response 0 (RO)
- *
- * Reset value: 0x00000000U
- *
- * This register is used to store part 0 of the response bits from the card.
- */
-typedef union _hw_sdhc_cmdrsp0
-{
- uint32_t U;
- struct _hw_sdhc_cmdrsp0_bitfields
- {
- uint32_t CMDRSP0 : 32; //!< [31:0] Command Response 0
- } B;
-} hw_sdhc_cmdrsp0_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SDHC_CMDRSP0 register
- */
-//@{
-#define HW_SDHC_CMDRSP0_ADDR (REGS_SDHC_BASE + 0x10U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SDHC_CMDRSP0 (*(__I hw_sdhc_cmdrsp0_t *) HW_SDHC_CMDRSP0_ADDR)
-#define HW_SDHC_CMDRSP0_RD() (HW_SDHC_CMDRSP0.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual SDHC_CMDRSP0 bitfields
- */
-
-/*!
- * @name Register SDHC_CMDRSP0, field CMDRSP0[31:0] (RO)
- */
-//@{
-#define BP_SDHC_CMDRSP0_CMDRSP0 (0U) //!< Bit position for SDHC_CMDRSP0_CMDRSP0.
-#define BM_SDHC_CMDRSP0_CMDRSP0 (0xFFFFFFFFU) //!< Bit mask for SDHC_CMDRSP0_CMDRSP0.
-#define BS_SDHC_CMDRSP0_CMDRSP0 (32U) //!< Bit field size in bits for SDHC_CMDRSP0_CMDRSP0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_CMDRSP0_CMDRSP0 field.
-#define BR_SDHC_CMDRSP0_CMDRSP0 (HW_SDHC_CMDRSP0.U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SDHC_CMDRSP1 - Command Response 1
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SDHC_CMDRSP1 - Command Response 1 (RO)
- *
- * Reset value: 0x00000000U
- *
- * This register is used to store part 1 of the response bits from the card.
- */
-typedef union _hw_sdhc_cmdrsp1
-{
- uint32_t U;
- struct _hw_sdhc_cmdrsp1_bitfields
- {
- uint32_t CMDRSP1 : 32; //!< [31:0] Command Response 1
- } B;
-} hw_sdhc_cmdrsp1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SDHC_CMDRSP1 register
- */
-//@{
-#define HW_SDHC_CMDRSP1_ADDR (REGS_SDHC_BASE + 0x14U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SDHC_CMDRSP1 (*(__I hw_sdhc_cmdrsp1_t *) HW_SDHC_CMDRSP1_ADDR)
-#define HW_SDHC_CMDRSP1_RD() (HW_SDHC_CMDRSP1.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual SDHC_CMDRSP1 bitfields
- */
-
-/*!
- * @name Register SDHC_CMDRSP1, field CMDRSP1[31:0] (RO)
- */
-//@{
-#define BP_SDHC_CMDRSP1_CMDRSP1 (0U) //!< Bit position for SDHC_CMDRSP1_CMDRSP1.
-#define BM_SDHC_CMDRSP1_CMDRSP1 (0xFFFFFFFFU) //!< Bit mask for SDHC_CMDRSP1_CMDRSP1.
-#define BS_SDHC_CMDRSP1_CMDRSP1 (32U) //!< Bit field size in bits for SDHC_CMDRSP1_CMDRSP1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_CMDRSP1_CMDRSP1 field.
-#define BR_SDHC_CMDRSP1_CMDRSP1 (HW_SDHC_CMDRSP1.U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SDHC_CMDRSP2 - Command Response 2
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SDHC_CMDRSP2 - Command Response 2 (RO)
- *
- * Reset value: 0x00000000U
- *
- * This register is used to store part 2 of the response bits from the card.
- */
-typedef union _hw_sdhc_cmdrsp2
-{
- uint32_t U;
- struct _hw_sdhc_cmdrsp2_bitfields
- {
- uint32_t CMDRSP2 : 32; //!< [31:0] Command Response 2
- } B;
-} hw_sdhc_cmdrsp2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SDHC_CMDRSP2 register
- */
-//@{
-#define HW_SDHC_CMDRSP2_ADDR (REGS_SDHC_BASE + 0x18U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SDHC_CMDRSP2 (*(__I hw_sdhc_cmdrsp2_t *) HW_SDHC_CMDRSP2_ADDR)
-#define HW_SDHC_CMDRSP2_RD() (HW_SDHC_CMDRSP2.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual SDHC_CMDRSP2 bitfields
- */
-
-/*!
- * @name Register SDHC_CMDRSP2, field CMDRSP2[31:0] (RO)
- */
-//@{
-#define BP_SDHC_CMDRSP2_CMDRSP2 (0U) //!< Bit position for SDHC_CMDRSP2_CMDRSP2.
-#define BM_SDHC_CMDRSP2_CMDRSP2 (0xFFFFFFFFU) //!< Bit mask for SDHC_CMDRSP2_CMDRSP2.
-#define BS_SDHC_CMDRSP2_CMDRSP2 (32U) //!< Bit field size in bits for SDHC_CMDRSP2_CMDRSP2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_CMDRSP2_CMDRSP2 field.
-#define BR_SDHC_CMDRSP2_CMDRSP2 (HW_SDHC_CMDRSP2.U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SDHC_CMDRSP3 - Command Response 3
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SDHC_CMDRSP3 - Command Response 3 (RO)
- *
- * Reset value: 0x00000000U
- *
- * This register is used to store part 3 of the response bits from the card. The
- * following table describes the mapping of command responses from the SD bus to
- * command response registers for each response type. In the table, R[ ] refers
- * to a bit range within the response data as transmitted on the SD bus. Response
- * bit definition for each response type Response type Meaning of response
- * Response field Response register R1,R1b (normal response) Card status R[39:8]
- * CMDRSP0 R1b (Auto CMD12 response) Card status for auto CMD12 R[39:8] CMDRSP3 R2
- * (CID, CSD register) CID/CSD register [127:8] R[127:8] {CMDRSP3[23:0], CMDRSP2,
- * CMDRSP1, CMDRSP0} R3 (OCR register) OCR register for memory R[39:8] CMDRSP0 R4
- * (OCR register) OCR register for I/O etc. R[39:8] CMDRSP0 R5, R5b SDIO response
- * R[39:8] CMDRSP0 R6 (Publish RCA) New published RCA[31:16] and card
- * status[15:0] R[39:9] CMDRSP0 This table shows that most responses with a length of 48
- * (R[47:0]) have 32-bit of the response data (R[39:8]) stored in the CMDRSP0
- * register. Responses of type R1b (auto CMD12 responses) have response data bits
- * (R[39:8]) stored in the CMDRSP3 register. Responses with length 136 (R[135:0]) have
- * 120-bit of the response data (R[127:8]) stored in the CMDRSP0, 1, 2, and 3
- * registers. To be able to read the response status efficiently, the SDHC stores
- * only a part of the response data in the command response registers. This
- * enables the host driver to efficiently read 32-bit of response data in one read
- * cycle on a 32-bit bus system. Parts of the response, the index field and the CRC,
- * are checked by the SDHC, as specified by XFERTYP[CICEN] and XFERTYP[CCCEN],
- * and generate an error interrupt if any error is detected. The bit range for the
- * CRC check depends on the response length. If the response length is 48, the
- * SDHC will check R[47:1], and if the response length is 136 the SDHC will check
- * R[119:1]. Because the SDHC may have a multiple block data transfer executing
- * concurrently with a CMD_wo_DAT command, the SDHC stores the auto CMD12 response
- * in the CMDRSP3 register. The CMD_wo_DAT response is stored in CMDRSP0. This
- * allows the SDHC to avoid overwriting the Auto CMD12 response with the CMD_wo_DAT
- * and vice versa. When the SDHC modifies part of the command response
- * registers, as shown in the table above, it preserves the unmodified bits.
- */
-typedef union _hw_sdhc_cmdrsp3
-{
- uint32_t U;
- struct _hw_sdhc_cmdrsp3_bitfields
- {
- uint32_t CMDRSP3 : 32; //!< [31:0] Command Response 3
- } B;
-} hw_sdhc_cmdrsp3_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SDHC_CMDRSP3 register
- */
-//@{
-#define HW_SDHC_CMDRSP3_ADDR (REGS_SDHC_BASE + 0x1CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SDHC_CMDRSP3 (*(__I hw_sdhc_cmdrsp3_t *) HW_SDHC_CMDRSP3_ADDR)
-#define HW_SDHC_CMDRSP3_RD() (HW_SDHC_CMDRSP3.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual SDHC_CMDRSP3 bitfields
- */
-
-/*!
- * @name Register SDHC_CMDRSP3, field CMDRSP3[31:0] (RO)
- */
-//@{
-#define BP_SDHC_CMDRSP3_CMDRSP3 (0U) //!< Bit position for SDHC_CMDRSP3_CMDRSP3.
-#define BM_SDHC_CMDRSP3_CMDRSP3 (0xFFFFFFFFU) //!< Bit mask for SDHC_CMDRSP3_CMDRSP3.
-#define BS_SDHC_CMDRSP3_CMDRSP3 (32U) //!< Bit field size in bits for SDHC_CMDRSP3_CMDRSP3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_CMDRSP3_CMDRSP3 field.
-#define BR_SDHC_CMDRSP3_CMDRSP3 (HW_SDHC_CMDRSP3.U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SDHC_DATPORT - Buffer Data Port register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SDHC_DATPORT - Buffer Data Port register (RW)
- *
- * Reset value: 0x00000000U
- *
- * This is a 32-bit data port register used to access the internal buffer and it
- * cannot be updated in Idle mode.
- */
-typedef union _hw_sdhc_datport
-{
- uint32_t U;
- struct _hw_sdhc_datport_bitfields
- {
- uint32_t DATCONT : 32; //!< [31:0] Data Content
- } B;
-} hw_sdhc_datport_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SDHC_DATPORT register
- */
-//@{
-#define HW_SDHC_DATPORT_ADDR (REGS_SDHC_BASE + 0x20U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SDHC_DATPORT (*(__IO hw_sdhc_datport_t *) HW_SDHC_DATPORT_ADDR)
-#define HW_SDHC_DATPORT_RD() (HW_SDHC_DATPORT.U)
-#define HW_SDHC_DATPORT_WR(v) (HW_SDHC_DATPORT.U = (v))
-#define HW_SDHC_DATPORT_SET(v) (HW_SDHC_DATPORT_WR(HW_SDHC_DATPORT_RD() | (v)))
-#define HW_SDHC_DATPORT_CLR(v) (HW_SDHC_DATPORT_WR(HW_SDHC_DATPORT_RD() & ~(v)))
-#define HW_SDHC_DATPORT_TOG(v) (HW_SDHC_DATPORT_WR(HW_SDHC_DATPORT_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SDHC_DATPORT bitfields
- */
-
-/*!
- * @name Register SDHC_DATPORT, field DATCONT[31:0] (RW)
- *
- * The Buffer Data Port register is for 32-bit data access by the CPU or the
- * external DMA. When the internal DMA is enabled, any write to this register is
- * ignored, and any read from this register will always yield 0s.
- */
-//@{
-#define BP_SDHC_DATPORT_DATCONT (0U) //!< Bit position for SDHC_DATPORT_DATCONT.
-#define BM_SDHC_DATPORT_DATCONT (0xFFFFFFFFU) //!< Bit mask for SDHC_DATPORT_DATCONT.
-#define BS_SDHC_DATPORT_DATCONT (32U) //!< Bit field size in bits for SDHC_DATPORT_DATCONT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_DATPORT_DATCONT field.
-#define BR_SDHC_DATPORT_DATCONT (HW_SDHC_DATPORT.U)
-#endif
-
-//! @brief Format value for bitfield SDHC_DATPORT_DATCONT.
-#define BF_SDHC_DATPORT_DATCONT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_DATPORT_DATCONT), uint32_t) & BM_SDHC_DATPORT_DATCONT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DATCONT field to a new value.
-#define BW_SDHC_DATPORT_DATCONT(v) (HW_SDHC_DATPORT_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SDHC_PRSSTAT - Present State register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SDHC_PRSSTAT - Present State register (RO)
- *
- * Reset value: 0x00000000U
- *
- * The host driver can get status of the SDHC from this 32-bit read-only
- * register. The host driver can issue CMD0, CMD12, CMD13 (for memory) and CMD52 (for
- * SDIO) when the DAT lines are busy during a data transfer. These commands can be
- * issued when Command Inhibit (CIHB) is set to zero. Other commands shall be
- * issued when Command Inhibit (CDIHB) is set to zero. Possible changes to the SD
- * Physical Specification may add other commands to this list in the future.
- */
-typedef union _hw_sdhc_prsstat
-{
- uint32_t U;
- struct _hw_sdhc_prsstat_bitfields
- {
- uint32_t CIHB : 1; //!< [0] Command Inhibit (CMD)
- uint32_t CDIHB : 1; //!< [1] Command Inhibit (DAT)
- uint32_t DLA : 1; //!< [2] Data Line Active
- uint32_t SDSTB : 1; //!< [3] SD Clock Stable
- uint32_t IPGOFF : 1; //!< [4] Bus Clock Gated Off Internally
- uint32_t HCKOFF : 1; //!< [5] System Clock Gated Off Internally
- uint32_t PEROFF : 1; //!< [6] SDHC clock Gated Off Internally
- uint32_t SDOFF : 1; //!< [7] SD Clock Gated Off Internally
- uint32_t WTA : 1; //!< [8] Write Transfer Active
- uint32_t RTA : 1; //!< [9] Read Transfer Active
- uint32_t BWEN : 1; //!< [10] Buffer Write Enable
- uint32_t BREN : 1; //!< [11] Buffer Read Enable
- uint32_t RESERVED0 : 4; //!< [15:12]
- uint32_t CINS : 1; //!< [16] Card Inserted
- uint32_t RESERVED1 : 6; //!< [22:17]
- uint32_t CLSL : 1; //!< [23] CMD Line Signal Level
- uint32_t DLSL : 8; //!< [31:24] DAT Line Signal Level
- } B;
-} hw_sdhc_prsstat_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SDHC_PRSSTAT register
- */
-//@{
-#define HW_SDHC_PRSSTAT_ADDR (REGS_SDHC_BASE + 0x24U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SDHC_PRSSTAT (*(__I hw_sdhc_prsstat_t *) HW_SDHC_PRSSTAT_ADDR)
-#define HW_SDHC_PRSSTAT_RD() (HW_SDHC_PRSSTAT.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual SDHC_PRSSTAT bitfields
- */
-
-/*!
- * @name Register SDHC_PRSSTAT, field CIHB[0] (RO)
- *
- * If this status bit is 0, it indicates that the CMD line is not in use and the
- * SDHC can issue a SD/MMC Command using the CMD line. This bit is set also
- * immediately after the Transfer Type register is written. This bit is cleared when
- * the command response is received. Even if the CDIHB bit is set to 1, Commands
- * using only the CMD line can be issued if this bit is 0. Changing from 1 to 0
- * generates a command complete interrupt in the interrupt status register. If the
- * SDHC cannot issue the command because of a command conflict error (see
- * command CRC error) or because of a command not issued by auto CMD12 error, this bit
- * will remain 1 and the command complete is not set. The status of issuing an
- * auto CMD12 does not show on this bit.
- *
- * Values:
- * - 0 - Can issue command using only CMD line.
- * - 1 - Cannot issue command.
- */
-//@{
-#define BP_SDHC_PRSSTAT_CIHB (0U) //!< Bit position for SDHC_PRSSTAT_CIHB.
-#define BM_SDHC_PRSSTAT_CIHB (0x00000001U) //!< Bit mask for SDHC_PRSSTAT_CIHB.
-#define BS_SDHC_PRSSTAT_CIHB (1U) //!< Bit field size in bits for SDHC_PRSSTAT_CIHB.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_PRSSTAT_CIHB field.
-#define BR_SDHC_PRSSTAT_CIHB (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_CIHB))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_PRSSTAT, field CDIHB[1] (RO)
- *
- * This status bit is generated if either the DLA or the RTA is set to 1. If
- * this bit is 0, it indicates that the SDHC can issue the next SD/MMC Command.
- * Commands with a busy signal belong to CDIHB, for example, R1b, R5b type. Except in
- * the case when the command busy is finished, changing from 1 to 0 generates a
- * transfer complete interrupt in the Interrupt Status register. The SD host
- * driver can save registers for a suspend transaction after this bit has changed
- * from 1 to 0.
- *
- * Values:
- * - 0 - Can issue command which uses the DAT line.
- * - 1 - Cannot issue command which uses the DAT line.
- */
-//@{
-#define BP_SDHC_PRSSTAT_CDIHB (1U) //!< Bit position for SDHC_PRSSTAT_CDIHB.
-#define BM_SDHC_PRSSTAT_CDIHB (0x00000002U) //!< Bit mask for SDHC_PRSSTAT_CDIHB.
-#define BS_SDHC_PRSSTAT_CDIHB (1U) //!< Bit field size in bits for SDHC_PRSSTAT_CDIHB.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_PRSSTAT_CDIHB field.
-#define BR_SDHC_PRSSTAT_CDIHB (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_CDIHB))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_PRSSTAT, field DLA[2] (RO)
- *
- * Indicates whether one of the DAT lines on the SD bus is in use. In the case
- * of read transactions: This status indicates whether a read transfer is
- * executing on the SD bus. Changes in this value from 1 to 0, between data blocks,
- * generates a block gap event interrupt in the Interrupt Status register. This bit
- * will be set in either of the following cases: After the end bit of the read
- * command. When writing a 1 to PROCTL[CREQ] to restart a read transfer. This bit
- * will be cleared in either of the following cases: When the end bit of the last
- * data block is sent from the SD bus to the SDHC. When the read wait state is
- * stopped by a suspend command and the DAT2 line is released. The SDHC will wait at
- * the next block gap by driving read wait at the start of the interrupt cycle.
- * If the read wait signal is already driven (data buffer cannot receive data),
- * the SDHC can wait for a current block gap by continuing to drive the read wait
- * signal. It is necessary to support read wait to use the suspend / resume
- * function. This bit will remain 1 during read wait. In the case of write
- * transactions: This status indicates that a write transfer is executing on the SD bus.
- * Changes in this value from 1 to 0 generate a transfer complete interrupt in the
- * interrupt status register. This bit will be set in either of the following
- * cases: After the end bit of the write command. When writing to 1 to PROCTL[CREQ] to
- * continue a write transfer. This bit will be cleared in either of the
- * following cases: When the SD card releases write busy of the last data block, the SDHC
- * will also detect if the output is not busy. If the SD card does not drive the
- * busy signal after the CRC status is received, the SDHC shall assume the card
- * drive "Not busy". When the SD card releases write busy, prior to waiting for
- * write transfer, and as a result of a stop at block gap request. In the case of
- * command with busy pending: This status indicates that a busy state follows the
- * command and the data line is in use. This bit will be cleared when the DAT0
- * line is released.
- *
- * Values:
- * - 0 - DAT line inactive.
- * - 1 - DAT line active.
- */
-//@{
-#define BP_SDHC_PRSSTAT_DLA (2U) //!< Bit position for SDHC_PRSSTAT_DLA.
-#define BM_SDHC_PRSSTAT_DLA (0x00000004U) //!< Bit mask for SDHC_PRSSTAT_DLA.
-#define BS_SDHC_PRSSTAT_DLA (1U) //!< Bit field size in bits for SDHC_PRSSTAT_DLA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_PRSSTAT_DLA field.
-#define BR_SDHC_PRSSTAT_DLA (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_DLA))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_PRSSTAT, field SDSTB[3] (RO)
- *
- * Indicates that the internal card clock is stable. This bit is for the host
- * driver to poll clock status when changing the clock frequency. It is recommended
- * to clear SYSCTL[SDCLKEN] to remove glitch on the card clock when the
- * frequency is changing.
- *
- * Values:
- * - 0 - Clock is changing frequency and not stable.
- * - 1 - Clock is stable.
- */
-//@{
-#define BP_SDHC_PRSSTAT_SDSTB (3U) //!< Bit position for SDHC_PRSSTAT_SDSTB.
-#define BM_SDHC_PRSSTAT_SDSTB (0x00000008U) //!< Bit mask for SDHC_PRSSTAT_SDSTB.
-#define BS_SDHC_PRSSTAT_SDSTB (1U) //!< Bit field size in bits for SDHC_PRSSTAT_SDSTB.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_PRSSTAT_SDSTB field.
-#define BR_SDHC_PRSSTAT_SDSTB (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_SDSTB))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_PRSSTAT, field IPGOFF[4] (RO)
- *
- * Indicates that the bus clock is internally gated off. This bit is for the
- * host driver to debug.
- *
- * Values:
- * - 0 - Bus clock is active.
- * - 1 - Bus clock is gated off.
- */
-//@{
-#define BP_SDHC_PRSSTAT_IPGOFF (4U) //!< Bit position for SDHC_PRSSTAT_IPGOFF.
-#define BM_SDHC_PRSSTAT_IPGOFF (0x00000010U) //!< Bit mask for SDHC_PRSSTAT_IPGOFF.
-#define BS_SDHC_PRSSTAT_IPGOFF (1U) //!< Bit field size in bits for SDHC_PRSSTAT_IPGOFF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_PRSSTAT_IPGOFF field.
-#define BR_SDHC_PRSSTAT_IPGOFF (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_IPGOFF))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_PRSSTAT, field HCKOFF[5] (RO)
- *
- * Indicates that the system clock is internally gated off. This bit is for the
- * host driver to debug during a data transfer.
- *
- * Values:
- * - 0 - System clock is active.
- * - 1 - System clock is gated off.
- */
-//@{
-#define BP_SDHC_PRSSTAT_HCKOFF (5U) //!< Bit position for SDHC_PRSSTAT_HCKOFF.
-#define BM_SDHC_PRSSTAT_HCKOFF (0x00000020U) //!< Bit mask for SDHC_PRSSTAT_HCKOFF.
-#define BS_SDHC_PRSSTAT_HCKOFF (1U) //!< Bit field size in bits for SDHC_PRSSTAT_HCKOFF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_PRSSTAT_HCKOFF field.
-#define BR_SDHC_PRSSTAT_HCKOFF (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_HCKOFF))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_PRSSTAT, field PEROFF[6] (RO)
- *
- * Indicates that the is internally gated off. This bit is for the host driver
- * to debug transaction on the SD bus. When INITA bit is set, SDHC sending 80
- * clock cycles to the card, SDCLKEN must be 1 to enable the output card clock,
- * otherwise the will never be gate off, so and will be always active. SDHC clock SDHC
- * clock SDHC clock bus clock
- *
- * Values:
- * - 0 - SDHC clock is active.
- * - 1 - SDHC clock is gated off.
- */
-//@{
-#define BP_SDHC_PRSSTAT_PEROFF (6U) //!< Bit position for SDHC_PRSSTAT_PEROFF.
-#define BM_SDHC_PRSSTAT_PEROFF (0x00000040U) //!< Bit mask for SDHC_PRSSTAT_PEROFF.
-#define BS_SDHC_PRSSTAT_PEROFF (1U) //!< Bit field size in bits for SDHC_PRSSTAT_PEROFF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_PRSSTAT_PEROFF field.
-#define BR_SDHC_PRSSTAT_PEROFF (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_PEROFF))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_PRSSTAT, field SDOFF[7] (RO)
- *
- * Indicates that the SD clock is internally gated off, because of buffer
- * over/under-run or read pause without read wait assertion, or the driver has cleared
- * SYSCTL[SDCLKEN] to stop the SD clock. This bit is for the host driver to debug
- * data transaction on the SD bus.
- *
- * Values:
- * - 0 - SD clock is active.
- * - 1 - SD clock is gated off.
- */
-//@{
-#define BP_SDHC_PRSSTAT_SDOFF (7U) //!< Bit position for SDHC_PRSSTAT_SDOFF.
-#define BM_SDHC_PRSSTAT_SDOFF (0x00000080U) //!< Bit mask for SDHC_PRSSTAT_SDOFF.
-#define BS_SDHC_PRSSTAT_SDOFF (1U) //!< Bit field size in bits for SDHC_PRSSTAT_SDOFF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_PRSSTAT_SDOFF field.
-#define BR_SDHC_PRSSTAT_SDOFF (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_SDOFF))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_PRSSTAT, field WTA[8] (RO)
- *
- * Indicates that a write transfer is active. If this bit is 0, it means no
- * valid write data exists in the SDHC. This bit is set in either of the following
- * cases: After the end bit of the write command. When writing 1 to PROCTL[CREQ] to
- * restart a write transfer. This bit is cleared in either of the following
- * cases: After getting the CRC status of the last data block as specified by the
- * transfer count (single and multiple). After getting the CRC status of any block
- * where data transmission is about to be stopped by a stop at block gap request.
- * During a write transaction, a block gap event interrupt is generated when this
- * bit is changed to 0, as result of the stop at block gap request being set.
- * This status is useful for the host driver in determining when to issue commands
- * during write busy state.
- *
- * Values:
- * - 0 - No valid data.
- * - 1 - Transferring data.
- */
-//@{
-#define BP_SDHC_PRSSTAT_WTA (8U) //!< Bit position for SDHC_PRSSTAT_WTA.
-#define BM_SDHC_PRSSTAT_WTA (0x00000100U) //!< Bit mask for SDHC_PRSSTAT_WTA.
-#define BS_SDHC_PRSSTAT_WTA (1U) //!< Bit field size in bits for SDHC_PRSSTAT_WTA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_PRSSTAT_WTA field.
-#define BR_SDHC_PRSSTAT_WTA (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_WTA))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_PRSSTAT, field RTA[9] (RO)
- *
- * Used for detecting completion of a read transfer. This bit is set for either
- * of the following conditions: After the end bit of the read command. When
- * writing a 1 to PROCTL[CREQ] to restart a read transfer. A transfer complete
- * interrupt is generated when this bit changes to 0. This bit is cleared for either of
- * the following conditions: When the last data block as specified by block
- * length is transferred to the system, that is, all data are read away from SDHC
- * internal buffer. When all valid data blocks have been transferred from SDHC
- * internal buffer to the system and no current block transfers are being sent as a
- * result of the stop at block gap request being set to 1.
- *
- * Values:
- * - 0 - No valid data.
- * - 1 - Transferring data.
- */
-//@{
-#define BP_SDHC_PRSSTAT_RTA (9U) //!< Bit position for SDHC_PRSSTAT_RTA.
-#define BM_SDHC_PRSSTAT_RTA (0x00000200U) //!< Bit mask for SDHC_PRSSTAT_RTA.
-#define BS_SDHC_PRSSTAT_RTA (1U) //!< Bit field size in bits for SDHC_PRSSTAT_RTA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_PRSSTAT_RTA field.
-#define BR_SDHC_PRSSTAT_RTA (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_RTA))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_PRSSTAT, field BWEN[10] (RO)
- *
- * Used for non-DMA write transfers. The SDHC can implement multiple buffers to
- * transfer data efficiently. This read-only flag indicates whether space is
- * available for write data. If this bit is 1, valid data greater than the watermark
- * level can be written to the buffer. This read-only flag indicates whether
- * space is available for write data.
- *
- * Values:
- * - 0 - Write disable, the buffer can hold valid data less than the write
- * watermark level.
- * - 1 - Write enable, the buffer can hold valid data greater than the write
- * watermark level.
- */
-//@{
-#define BP_SDHC_PRSSTAT_BWEN (10U) //!< Bit position for SDHC_PRSSTAT_BWEN.
-#define BM_SDHC_PRSSTAT_BWEN (0x00000400U) //!< Bit mask for SDHC_PRSSTAT_BWEN.
-#define BS_SDHC_PRSSTAT_BWEN (1U) //!< Bit field size in bits for SDHC_PRSSTAT_BWEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_PRSSTAT_BWEN field.
-#define BR_SDHC_PRSSTAT_BWEN (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_BWEN))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_PRSSTAT, field BREN[11] (RO)
- *
- * Used for non-DMA read transfers. The SDHC may implement multiple buffers to
- * transfer data efficiently. This read-only flag indicates that valid data exists
- * in the host side buffer. If this bit is high, valid data greater than the
- * watermark level exist in the buffer. This read-only flag indicates that valid
- * data exists in the host side buffer.
- *
- * Values:
- * - 0 - Read disable, valid data less than the watermark level exist in the
- * buffer.
- * - 1 - Read enable, valid data greater than the watermark level exist in the
- * buffer.
- */
-//@{
-#define BP_SDHC_PRSSTAT_BREN (11U) //!< Bit position for SDHC_PRSSTAT_BREN.
-#define BM_SDHC_PRSSTAT_BREN (0x00000800U) //!< Bit mask for SDHC_PRSSTAT_BREN.
-#define BS_SDHC_PRSSTAT_BREN (1U) //!< Bit field size in bits for SDHC_PRSSTAT_BREN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_PRSSTAT_BREN field.
-#define BR_SDHC_PRSSTAT_BREN (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_BREN))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_PRSSTAT, field CINS[16] (RO)
- *
- * Indicates whether a card has been inserted. The SDHC debounces this signal so
- * that the host driver will not need to wait for it to stabilize. Changing from
- * a 0 to 1 generates a card insertion interrupt in the Interrupt Status
- * register. Changing from a 1 to 0 generates a card removal interrupt in the Interrupt
- * Status register. A write to the force event register does not effect this bit.
- * SYSCTL[RSTA] does not effect this bit. A software reset does not effect this
- * bit.
- *
- * Values:
- * - 0 - Power on reset or no card.
- * - 1 - Card inserted.
- */
-//@{
-#define BP_SDHC_PRSSTAT_CINS (16U) //!< Bit position for SDHC_PRSSTAT_CINS.
-#define BM_SDHC_PRSSTAT_CINS (0x00010000U) //!< Bit mask for SDHC_PRSSTAT_CINS.
-#define BS_SDHC_PRSSTAT_CINS (1U) //!< Bit field size in bits for SDHC_PRSSTAT_CINS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_PRSSTAT_CINS field.
-#define BR_SDHC_PRSSTAT_CINS (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_CINS))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_PRSSTAT, field CLSL[23] (RO)
- *
- * Used to check the CMD line level to recover from errors, and for debugging.
- * The reset value is effected by the external pullup/pulldown resistor, by
- * default, the read value of this bit after reset is 1b, when the command line is
- * pulled up.
- */
-//@{
-#define BP_SDHC_PRSSTAT_CLSL (23U) //!< Bit position for SDHC_PRSSTAT_CLSL.
-#define BM_SDHC_PRSSTAT_CLSL (0x00800000U) //!< Bit mask for SDHC_PRSSTAT_CLSL.
-#define BS_SDHC_PRSSTAT_CLSL (1U) //!< Bit field size in bits for SDHC_PRSSTAT_CLSL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_PRSSTAT_CLSL field.
-#define BR_SDHC_PRSSTAT_CLSL (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_CLSL))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_PRSSTAT, field DLSL[31:24] (RO)
- *
- * Used to check the DAT line level to recover from errors, and for debugging.
- * This is especially useful in detecting the busy signal level from DAT[0]. The
- * reset value is effected by the external pullup/pulldown resistors. By default,
- * the read value of this field after reset is 8'b11110111, when DAT[3] is pulled
- * down and the other lines are pulled up.
- */
-//@{
-#define BP_SDHC_PRSSTAT_DLSL (24U) //!< Bit position for SDHC_PRSSTAT_DLSL.
-#define BM_SDHC_PRSSTAT_DLSL (0xFF000000U) //!< Bit mask for SDHC_PRSSTAT_DLSL.
-#define BS_SDHC_PRSSTAT_DLSL (8U) //!< Bit field size in bits for SDHC_PRSSTAT_DLSL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_PRSSTAT_DLSL field.
-#define BR_SDHC_PRSSTAT_DLSL (HW_SDHC_PRSSTAT.B.DLSL)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SDHC_PROCTL - Protocol Control register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SDHC_PROCTL - Protocol Control register (RW)
- *
- * Reset value: 0x00000020U
- *
- * There are three cases to restart the transfer after stop at the block gap.
- * Which case is appropriate depends on whether the SDHC issues a suspend command
- * or the SD card accepts the suspend command: If the host driver does not issue a
- * suspend command, the continue request shall be used to restart the transfer.
- * If the host driver issues a suspend command and the SD card accepts it, a
- * resume command shall be used to restart the transfer. If the host driver issues a
- * suspend command and the SD card does not accept it, the continue request shall
- * be used to restart the transfer. Any time stop at block gap request stops the
- * data transfer, the host driver shall wait for a transfer complete (in the
- * interrupt status register), before attempting to restart the transfer. When
- * restarting the data transfer by continue request, the host driver shall clear the
- * stop at block gap request before or simultaneously.
- */
-typedef union _hw_sdhc_proctl
-{
- uint32_t U;
- struct _hw_sdhc_proctl_bitfields
- {
- uint32_t LCTL : 1; //!< [0] LED Control
- uint32_t DTW : 2; //!< [2:1] Data Transfer Width
- uint32_t D3CD : 1; //!< [3] DAT3 As Card Detection Pin
- uint32_t EMODE : 2; //!< [5:4] Endian Mode
- uint32_t CDTL : 1; //!< [6] Card Detect Test Level
- uint32_t CDSS : 1; //!< [7] Card Detect Signal Selection
- uint32_t DMAS : 2; //!< [9:8] DMA Select
- uint32_t RESERVED0 : 6; //!< [15:10]
- uint32_t SABGREQ : 1; //!< [16] Stop At Block Gap Request
- uint32_t CREQ : 1; //!< [17] Continue Request
- uint32_t RWCTL : 1; //!< [18] Read Wait Control
- uint32_t IABG : 1; //!< [19] Interrupt At Block Gap
- uint32_t RESERVED1 : 4; //!< [23:20]
- uint32_t WECINT : 1; //!< [24] Wakeup Event Enable On Card Interrupt
- uint32_t WECINS : 1; //!< [25] Wakeup Event Enable On SD Card
- //! Insertion
- uint32_t WECRM : 1; //!< [26] Wakeup Event Enable On SD Card Removal
- uint32_t RESERVED2 : 5; //!< [31:27]
- } B;
-} hw_sdhc_proctl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SDHC_PROCTL register
- */
-//@{
-#define HW_SDHC_PROCTL_ADDR (REGS_SDHC_BASE + 0x28U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SDHC_PROCTL (*(__IO hw_sdhc_proctl_t *) HW_SDHC_PROCTL_ADDR)
-#define HW_SDHC_PROCTL_RD() (HW_SDHC_PROCTL.U)
-#define HW_SDHC_PROCTL_WR(v) (HW_SDHC_PROCTL.U = (v))
-#define HW_SDHC_PROCTL_SET(v) (HW_SDHC_PROCTL_WR(HW_SDHC_PROCTL_RD() | (v)))
-#define HW_SDHC_PROCTL_CLR(v) (HW_SDHC_PROCTL_WR(HW_SDHC_PROCTL_RD() & ~(v)))
-#define HW_SDHC_PROCTL_TOG(v) (HW_SDHC_PROCTL_WR(HW_SDHC_PROCTL_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SDHC_PROCTL bitfields
- */
-
-/*!
- * @name Register SDHC_PROCTL, field LCTL[0] (RW)
- *
- * This bit, fully controlled by the host driver, is used to caution the user
- * not to remove the card while the card is being accessed. If the software is
- * going to issue multiple SD commands, this bit can be set during all these
- * transactions. It is not necessary to change for each transaction. When the software
- * issues multiple SD commands, setting the bit once before the first command is
- * sufficient: it is not necessary to reset the bit between commands.
- *
- * Values:
- * - 0 - LED off.
- * - 1 - LED on.
- */
-//@{
-#define BP_SDHC_PROCTL_LCTL (0U) //!< Bit position for SDHC_PROCTL_LCTL.
-#define BM_SDHC_PROCTL_LCTL (0x00000001U) //!< Bit mask for SDHC_PROCTL_LCTL.
-#define BS_SDHC_PROCTL_LCTL (1U) //!< Bit field size in bits for SDHC_PROCTL_LCTL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_PROCTL_LCTL field.
-#define BR_SDHC_PROCTL_LCTL (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_LCTL))
-#endif
-
-//! @brief Format value for bitfield SDHC_PROCTL_LCTL.
-#define BF_SDHC_PROCTL_LCTL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_LCTL), uint32_t) & BM_SDHC_PROCTL_LCTL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LCTL field to a new value.
-#define BW_SDHC_PROCTL_LCTL(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_LCTL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_PROCTL, field DTW[2:1] (RW)
- *
- * Selects the data width of the SD bus for a data transfer. The host driver
- * shall set it to match the data width of the card. Possible data transfer width is
- * 1-bit, 4-bits or 8-bits.
- *
- * Values:
- * - 00 - 1-bit mode
- * - 01 - 4-bit mode
- * - 10 - 8-bit mode
- * - 11 - Reserved
- */
-//@{
-#define BP_SDHC_PROCTL_DTW (1U) //!< Bit position for SDHC_PROCTL_DTW.
-#define BM_SDHC_PROCTL_DTW (0x00000006U) //!< Bit mask for SDHC_PROCTL_DTW.
-#define BS_SDHC_PROCTL_DTW (2U) //!< Bit field size in bits for SDHC_PROCTL_DTW.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_PROCTL_DTW field.
-#define BR_SDHC_PROCTL_DTW (HW_SDHC_PROCTL.B.DTW)
-#endif
-
-//! @brief Format value for bitfield SDHC_PROCTL_DTW.
-#define BF_SDHC_PROCTL_DTW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_DTW), uint32_t) & BM_SDHC_PROCTL_DTW)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DTW field to a new value.
-#define BW_SDHC_PROCTL_DTW(v) (HW_SDHC_PROCTL_WR((HW_SDHC_PROCTL_RD() & ~BM_SDHC_PROCTL_DTW) | BF_SDHC_PROCTL_DTW(v)))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_PROCTL, field D3CD[3] (RW)
- *
- * If this bit is set, DAT3 should be pulled down to act as a card detection
- * pin. Be cautious when using this feature, because DAT3 is also a chip-select for
- * the SPI mode. A pulldown on this pin and CMD0 may set the card into the SPI
- * mode, which the SDHC does not support. Note: Keep this bit set if SDIO interrupt
- * is used.
- *
- * Values:
- * - 0 - DAT3 does not monitor card Insertion.
- * - 1 - DAT3 as card detection pin.
- */
-//@{
-#define BP_SDHC_PROCTL_D3CD (3U) //!< Bit position for SDHC_PROCTL_D3CD.
-#define BM_SDHC_PROCTL_D3CD (0x00000008U) //!< Bit mask for SDHC_PROCTL_D3CD.
-#define BS_SDHC_PROCTL_D3CD (1U) //!< Bit field size in bits for SDHC_PROCTL_D3CD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_PROCTL_D3CD field.
-#define BR_SDHC_PROCTL_D3CD (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_D3CD))
-#endif
-
-//! @brief Format value for bitfield SDHC_PROCTL_D3CD.
-#define BF_SDHC_PROCTL_D3CD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_D3CD), uint32_t) & BM_SDHC_PROCTL_D3CD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the D3CD field to a new value.
-#define BW_SDHC_PROCTL_D3CD(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_D3CD) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_PROCTL, field EMODE[5:4] (RW)
- *
- * The SDHC supports all four endian modes in data transfer.
- *
- * Values:
- * - 00 - Big endian mode
- * - 01 - Half word big endian mode
- * - 10 - Little endian mode
- * - 11 - Reserved
- */
-//@{
-#define BP_SDHC_PROCTL_EMODE (4U) //!< Bit position for SDHC_PROCTL_EMODE.
-#define BM_SDHC_PROCTL_EMODE (0x00000030U) //!< Bit mask for SDHC_PROCTL_EMODE.
-#define BS_SDHC_PROCTL_EMODE (2U) //!< Bit field size in bits for SDHC_PROCTL_EMODE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_PROCTL_EMODE field.
-#define BR_SDHC_PROCTL_EMODE (HW_SDHC_PROCTL.B.EMODE)
-#endif
-
-//! @brief Format value for bitfield SDHC_PROCTL_EMODE.
-#define BF_SDHC_PROCTL_EMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_EMODE), uint32_t) & BM_SDHC_PROCTL_EMODE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EMODE field to a new value.
-#define BW_SDHC_PROCTL_EMODE(v) (HW_SDHC_PROCTL_WR((HW_SDHC_PROCTL_RD() & ~BM_SDHC_PROCTL_EMODE) | BF_SDHC_PROCTL_EMODE(v)))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_PROCTL, field CDTL[6] (RW)
- *
- * Enabled while the CDSS is set to 1 and it indicates card insertion.
- *
- * Values:
- * - 0 - Card detect test level is 0, no card inserted.
- * - 1 - Card detect test level is 1, card inserted.
- */
-//@{
-#define BP_SDHC_PROCTL_CDTL (6U) //!< Bit position for SDHC_PROCTL_CDTL.
-#define BM_SDHC_PROCTL_CDTL (0x00000040U) //!< Bit mask for SDHC_PROCTL_CDTL.
-#define BS_SDHC_PROCTL_CDTL (1U) //!< Bit field size in bits for SDHC_PROCTL_CDTL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_PROCTL_CDTL field.
-#define BR_SDHC_PROCTL_CDTL (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CDTL))
-#endif
-
-//! @brief Format value for bitfield SDHC_PROCTL_CDTL.
-#define BF_SDHC_PROCTL_CDTL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_CDTL), uint32_t) & BM_SDHC_PROCTL_CDTL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CDTL field to a new value.
-#define BW_SDHC_PROCTL_CDTL(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CDTL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_PROCTL, field CDSS[7] (RW)
- *
- * Selects the source for the card detection.
- *
- * Values:
- * - 0 - Card detection level is selected for normal purpose.
- * - 1 - Card detection test level is selected for test purpose.
- */
-//@{
-#define BP_SDHC_PROCTL_CDSS (7U) //!< Bit position for SDHC_PROCTL_CDSS.
-#define BM_SDHC_PROCTL_CDSS (0x00000080U) //!< Bit mask for SDHC_PROCTL_CDSS.
-#define BS_SDHC_PROCTL_CDSS (1U) //!< Bit field size in bits for SDHC_PROCTL_CDSS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_PROCTL_CDSS field.
-#define BR_SDHC_PROCTL_CDSS (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CDSS))
-#endif
-
-//! @brief Format value for bitfield SDHC_PROCTL_CDSS.
-#define BF_SDHC_PROCTL_CDSS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_CDSS), uint32_t) & BM_SDHC_PROCTL_CDSS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CDSS field to a new value.
-#define BW_SDHC_PROCTL_CDSS(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CDSS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_PROCTL, field DMAS[9:8] (RW)
- *
- * This field is valid while DMA (SDMA or ADMA) is enabled and selects the DMA
- * operation.
- *
- * Values:
- * - 00 - No DMA or simple DMA is selected.
- * - 01 - ADMA1 is selected.
- * - 10 - ADMA2 is selected.
- * - 11 - Reserved
- */
-//@{
-#define BP_SDHC_PROCTL_DMAS (8U) //!< Bit position for SDHC_PROCTL_DMAS.
-#define BM_SDHC_PROCTL_DMAS (0x00000300U) //!< Bit mask for SDHC_PROCTL_DMAS.
-#define BS_SDHC_PROCTL_DMAS (2U) //!< Bit field size in bits for SDHC_PROCTL_DMAS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_PROCTL_DMAS field.
-#define BR_SDHC_PROCTL_DMAS (HW_SDHC_PROCTL.B.DMAS)
-#endif
-
-//! @brief Format value for bitfield SDHC_PROCTL_DMAS.
-#define BF_SDHC_PROCTL_DMAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_DMAS), uint32_t) & BM_SDHC_PROCTL_DMAS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DMAS field to a new value.
-#define BW_SDHC_PROCTL_DMAS(v) (HW_SDHC_PROCTL_WR((HW_SDHC_PROCTL_RD() & ~BM_SDHC_PROCTL_DMAS) | BF_SDHC_PROCTL_DMAS(v)))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_PROCTL, field SABGREQ[16] (RW)
- *
- * Used to stop executing a transaction at the next block gap for both DMA and
- * non-DMA transfers. Until the IRQSTATEN[TCSEN] is set to 1, indicating a
- * transfer completion, the host driver shall leave this bit set to 1. Clearing both
- * PROCTL[SABGREQ] and PROCTL[CREQ] does not cause the transaction to restart. Read
- * Wait is used to stop the read transaction at the block gap. The SDHC will
- * honor the PROCTL[SABGREQ] for write transfers, but for read transfers it requires
- * that SDIO card support read wait. Therefore, the host driver shall not set
- * this bit during read transfers unless the SDIO card supports read wait and has
- * set PROCTL[RWCTL] to 1, otherwise the SDHC will stop the SD bus clock to pause
- * the read operation during block gap. In the case of write transfers in which
- * the host driver writes data to the data port register, the host driver shall set
- * this bit after all block data is written. If this bit is set to 1, the host
- * driver shall not write data to the Data Port register after a block is sent.
- * Once this bit is set, the host driver shall not clear this bit before
- * IRQSTATEN[TCSEN] is set, otherwise the SDHC's behavior is undefined. This bit effects
- * PRSSTAT[RTA], PRSSTAT[WTA], and PRSSTAT[CDIHB].
- *
- * Values:
- * - 0 - Transfer
- * - 1 - Stop
- */
-//@{
-#define BP_SDHC_PROCTL_SABGREQ (16U) //!< Bit position for SDHC_PROCTL_SABGREQ.
-#define BM_SDHC_PROCTL_SABGREQ (0x00010000U) //!< Bit mask for SDHC_PROCTL_SABGREQ.
-#define BS_SDHC_PROCTL_SABGREQ (1U) //!< Bit field size in bits for SDHC_PROCTL_SABGREQ.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_PROCTL_SABGREQ field.
-#define BR_SDHC_PROCTL_SABGREQ (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_SABGREQ))
-#endif
-
-//! @brief Format value for bitfield SDHC_PROCTL_SABGREQ.
-#define BF_SDHC_PROCTL_SABGREQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_SABGREQ), uint32_t) & BM_SDHC_PROCTL_SABGREQ)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SABGREQ field to a new value.
-#define BW_SDHC_PROCTL_SABGREQ(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_SABGREQ) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_PROCTL, field CREQ[17] (RW)
- *
- * Used to restart a transaction which was stopped using the PROCTL[SABGREQ].
- * When a suspend operation is not accepted by the card, it is also by setting this
- * bit to restart the paused transfer. To cancel stop at the block gap, set
- * PROCTL[SABGREQ] to 0 and set this bit to 1 to restart the transfer. The SDHC
- * automatically clears this bit, therefore it is not necessary for the host driver to
- * set this bit to 0. If both PROCTL[SABGREQ] and this bit are 1, the continue
- * request is ignored.
- *
- * Values:
- * - 0 - No effect.
- * - 1 - Restart
- */
-//@{
-#define BP_SDHC_PROCTL_CREQ (17U) //!< Bit position for SDHC_PROCTL_CREQ.
-#define BM_SDHC_PROCTL_CREQ (0x00020000U) //!< Bit mask for SDHC_PROCTL_CREQ.
-#define BS_SDHC_PROCTL_CREQ (1U) //!< Bit field size in bits for SDHC_PROCTL_CREQ.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_PROCTL_CREQ field.
-#define BR_SDHC_PROCTL_CREQ (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CREQ))
-#endif
-
-//! @brief Format value for bitfield SDHC_PROCTL_CREQ.
-#define BF_SDHC_PROCTL_CREQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_CREQ), uint32_t) & BM_SDHC_PROCTL_CREQ)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CREQ field to a new value.
-#define BW_SDHC_PROCTL_CREQ(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CREQ) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_PROCTL, field RWCTL[18] (RW)
- *
- * The read wait function is optional for SDIO cards. If the card supports read
- * wait, set this bit to enable use of the read wait protocol to stop read data
- * using the DAT[2] line. Otherwise, the SDHC has to stop the SD Clock to hold
- * read data, which restricts commands generation. When the host driver detects an
- * SDIO card insertion, it shall set this bit according to the CCCR of the card.
- * If the card does not support read wait, this bit shall never be set to 1,
- * otherwise DAT line conflicts may occur. If this bit is set to 0, stop at block gap
- * during read operation is also supported, but the SDHC will stop the SD Clock
- * to pause reading operation.
- *
- * Values:
- * - 0 - Disable read wait control, and stop SD clock at block gap when SABGREQ
- * is set.
- * - 1 - Enable read wait control, and assert read wait without stopping SD
- * clock at block gap when SABGREQ bit is set.
- */
-//@{
-#define BP_SDHC_PROCTL_RWCTL (18U) //!< Bit position for SDHC_PROCTL_RWCTL.
-#define BM_SDHC_PROCTL_RWCTL (0x00040000U) //!< Bit mask for SDHC_PROCTL_RWCTL.
-#define BS_SDHC_PROCTL_RWCTL (1U) //!< Bit field size in bits for SDHC_PROCTL_RWCTL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_PROCTL_RWCTL field.
-#define BR_SDHC_PROCTL_RWCTL (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_RWCTL))
-#endif
-
-//! @brief Format value for bitfield SDHC_PROCTL_RWCTL.
-#define BF_SDHC_PROCTL_RWCTL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_RWCTL), uint32_t) & BM_SDHC_PROCTL_RWCTL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RWCTL field to a new value.
-#define BW_SDHC_PROCTL_RWCTL(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_RWCTL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_PROCTL, field IABG[19] (RW)
- *
- * Valid only in 4-bit mode, of the SDIO card, and selects a sample point in the
- * interrupt cycle. Setting to 1 enables interrupt detection at the block gap
- * for a multiple block transfer. Setting to 0 disables interrupt detection during
- * a multiple block transfer. If the SDIO card can't signal an interrupt during a
- * multiple block transfer, this bit must be set to 0 to avoid an inadvertent
- * interrupt. When the host driver detects an SDIO card insertion, it shall set
- * this bit according to the CCCR of the card.
- *
- * Values:
- * - 0 - Disabled
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_PROCTL_IABG (19U) //!< Bit position for SDHC_PROCTL_IABG.
-#define BM_SDHC_PROCTL_IABG (0x00080000U) //!< Bit mask for SDHC_PROCTL_IABG.
-#define BS_SDHC_PROCTL_IABG (1U) //!< Bit field size in bits for SDHC_PROCTL_IABG.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_PROCTL_IABG field.
-#define BR_SDHC_PROCTL_IABG (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_IABG))
-#endif
-
-//! @brief Format value for bitfield SDHC_PROCTL_IABG.
-#define BF_SDHC_PROCTL_IABG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_IABG), uint32_t) & BM_SDHC_PROCTL_IABG)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IABG field to a new value.
-#define BW_SDHC_PROCTL_IABG(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_IABG) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_PROCTL, field WECINT[24] (RW)
- *
- * Enables a wakeup event, via IRQSTAT[CINT]. This bit can be set to 1 if FN_WUS
- * (Wake Up Support) in CIS is set to 1. When this bit is set, the card
- * interrupt status and the SDHC interrupt can be asserted without SD_CLK toggling. When
- * the wakeup feature is not enabled, the SD_CLK must be active to assert the
- * card interrupt status and the SDHC interrupt.
- *
- * Values:
- * - 0 - Disabled
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_PROCTL_WECINT (24U) //!< Bit position for SDHC_PROCTL_WECINT.
-#define BM_SDHC_PROCTL_WECINT (0x01000000U) //!< Bit mask for SDHC_PROCTL_WECINT.
-#define BS_SDHC_PROCTL_WECINT (1U) //!< Bit field size in bits for SDHC_PROCTL_WECINT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_PROCTL_WECINT field.
-#define BR_SDHC_PROCTL_WECINT (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECINT))
-#endif
-
-//! @brief Format value for bitfield SDHC_PROCTL_WECINT.
-#define BF_SDHC_PROCTL_WECINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_WECINT), uint32_t) & BM_SDHC_PROCTL_WECINT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WECINT field to a new value.
-#define BW_SDHC_PROCTL_WECINT(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECINT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_PROCTL, field WECINS[25] (RW)
- *
- * Enables a wakeup event, via IRQSTAT[CINS]. FN_WUS (Wake Up Support) in CIS
- * does not effect this bit. When this bit is set, IRQSTATEN[CINSEN] and the SDHC
- * interrupt can be asserted without SD_CLK toggling. When the wakeup feature is
- * not enabled, the SD_CLK must be active to assert IRQSTATEN[CINSEN] and the SDHC
- * interrupt.
- *
- * Values:
- * - 0 - Disabled
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_PROCTL_WECINS (25U) //!< Bit position for SDHC_PROCTL_WECINS.
-#define BM_SDHC_PROCTL_WECINS (0x02000000U) //!< Bit mask for SDHC_PROCTL_WECINS.
-#define BS_SDHC_PROCTL_WECINS (1U) //!< Bit field size in bits for SDHC_PROCTL_WECINS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_PROCTL_WECINS field.
-#define BR_SDHC_PROCTL_WECINS (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECINS))
-#endif
-
-//! @brief Format value for bitfield SDHC_PROCTL_WECINS.
-#define BF_SDHC_PROCTL_WECINS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_WECINS), uint32_t) & BM_SDHC_PROCTL_WECINS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WECINS field to a new value.
-#define BW_SDHC_PROCTL_WECINS(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECINS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_PROCTL, field WECRM[26] (RW)
- *
- * Enables a wakeup event, via IRQSTAT[CRM]. FN_WUS (Wake Up Support) in CIS
- * does not effect this bit. When this bit is set, IRQSTAT[CRM] and the SDHC
- * interrupt can be asserted without SD_CLK toggling. When the wakeup feature is not
- * enabled, the SD_CLK must be active to assert IRQSTAT[CRM] and the SDHC interrupt.
- *
- * Values:
- * - 0 - Disabled
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_PROCTL_WECRM (26U) //!< Bit position for SDHC_PROCTL_WECRM.
-#define BM_SDHC_PROCTL_WECRM (0x04000000U) //!< Bit mask for SDHC_PROCTL_WECRM.
-#define BS_SDHC_PROCTL_WECRM (1U) //!< Bit field size in bits for SDHC_PROCTL_WECRM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_PROCTL_WECRM field.
-#define BR_SDHC_PROCTL_WECRM (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECRM))
-#endif
-
-//! @brief Format value for bitfield SDHC_PROCTL_WECRM.
-#define BF_SDHC_PROCTL_WECRM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_WECRM), uint32_t) & BM_SDHC_PROCTL_WECRM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WECRM field to a new value.
-#define BW_SDHC_PROCTL_WECRM(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECRM) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SDHC_SYSCTL - System Control register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SDHC_SYSCTL - System Control register (RW)
- *
- * Reset value: 0x00008008U
- */
-typedef union _hw_sdhc_sysctl
-{
- uint32_t U;
- struct _hw_sdhc_sysctl_bitfields
- {
- uint32_t IPGEN : 1; //!< [0] IPG Clock Enable
- uint32_t HCKEN : 1; //!< [1] System Clock Enable
- uint32_t PEREN : 1; //!< [2] Peripheral Clock Enable
- uint32_t SDCLKEN : 1; //!< [3] SD Clock Enable
- uint32_t DVS : 4; //!< [7:4] Divisor
- uint32_t SDCLKFS : 8; //!< [15:8] SDCLK Frequency Select
- uint32_t DTOCV : 4; //!< [19:16] Data Timeout Counter Value
- uint32_t RESERVED0 : 4; //!< [23:20]
- uint32_t RSTA : 1; //!< [24] Software Reset For ALL
- uint32_t RSTC : 1; //!< [25] Software Reset For CMD Line
- uint32_t RSTD : 1; //!< [26] Software Reset For DAT Line
- uint32_t INITA : 1; //!< [27] Initialization Active
- uint32_t RESERVED1 : 4; //!< [31:28]
- } B;
-} hw_sdhc_sysctl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SDHC_SYSCTL register
- */
-//@{
-#define HW_SDHC_SYSCTL_ADDR (REGS_SDHC_BASE + 0x2CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SDHC_SYSCTL (*(__IO hw_sdhc_sysctl_t *) HW_SDHC_SYSCTL_ADDR)
-#define HW_SDHC_SYSCTL_RD() (HW_SDHC_SYSCTL.U)
-#define HW_SDHC_SYSCTL_WR(v) (HW_SDHC_SYSCTL.U = (v))
-#define HW_SDHC_SYSCTL_SET(v) (HW_SDHC_SYSCTL_WR(HW_SDHC_SYSCTL_RD() | (v)))
-#define HW_SDHC_SYSCTL_CLR(v) (HW_SDHC_SYSCTL_WR(HW_SDHC_SYSCTL_RD() & ~(v)))
-#define HW_SDHC_SYSCTL_TOG(v) (HW_SDHC_SYSCTL_WR(HW_SDHC_SYSCTL_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SDHC_SYSCTL bitfields
- */
-
-/*!
- * @name Register SDHC_SYSCTL, field IPGEN[0] (RW)
- *
- * If this bit is set, bus clock will always be active and no automatic gating
- * is applied. The bus clock will be internally gated off, if none of the
- * following factors are met: The cmd part is reset, or Data part is reset, or Soft
- * reset, or The cmd is about to send, or Clock divisor is just updated, or Continue
- * request is just set, or This bit is set, or Card insertion is detected, or Card
- * removal is detected, or Card external interrupt is detected, or The SDHC
- * clock is not gated off The bus clock will not be auto gated off if the SDHC clock
- * is not gated off. So clearing only this bit has no effect unless the PEREN bit
- * is also cleared.
- *
- * Values:
- * - 0 - Bus clock will be internally gated off.
- * - 1 - Bus clock will not be automatically gated off.
- */
-//@{
-#define BP_SDHC_SYSCTL_IPGEN (0U) //!< Bit position for SDHC_SYSCTL_IPGEN.
-#define BM_SDHC_SYSCTL_IPGEN (0x00000001U) //!< Bit mask for SDHC_SYSCTL_IPGEN.
-#define BS_SDHC_SYSCTL_IPGEN (1U) //!< Bit field size in bits for SDHC_SYSCTL_IPGEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_SYSCTL_IPGEN field.
-#define BR_SDHC_SYSCTL_IPGEN (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_IPGEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_SYSCTL_IPGEN.
-#define BF_SDHC_SYSCTL_IPGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_IPGEN), uint32_t) & BM_SDHC_SYSCTL_IPGEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IPGEN field to a new value.
-#define BW_SDHC_SYSCTL_IPGEN(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_IPGEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_SYSCTL, field HCKEN[1] (RW)
- *
- * If this bit is set, system clock will always be active and no automatic
- * gating is applied. When this bit is cleared, system clock will be automatically off
- * when no data transfer is on the SD bus.
- *
- * Values:
- * - 0 - System clock will be internally gated off.
- * - 1 - System clock will not be automatically gated off.
- */
-//@{
-#define BP_SDHC_SYSCTL_HCKEN (1U) //!< Bit position for SDHC_SYSCTL_HCKEN.
-#define BM_SDHC_SYSCTL_HCKEN (0x00000002U) //!< Bit mask for SDHC_SYSCTL_HCKEN.
-#define BS_SDHC_SYSCTL_HCKEN (1U) //!< Bit field size in bits for SDHC_SYSCTL_HCKEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_SYSCTL_HCKEN field.
-#define BR_SDHC_SYSCTL_HCKEN (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_HCKEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_SYSCTL_HCKEN.
-#define BF_SDHC_SYSCTL_HCKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_HCKEN), uint32_t) & BM_SDHC_SYSCTL_HCKEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the HCKEN field to a new value.
-#define BW_SDHC_SYSCTL_HCKEN(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_HCKEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_SYSCTL, field PEREN[2] (RW)
- *
- * If this bit is set, SDHC clock will always be active and no automatic gating
- * is applied. Thus the SDCLK is active except for when auto gating-off during
- * buffer danger (buffer about to over-run or under-run). When this bit is cleared,
- * the SDHC clock will be automatically off whenever there is no transaction on
- * the SD bus. Because this bit is only a feature enabling bit, clearing this bit
- * does not stop SDCLK immediately. The SDHC clock will be internally gated off,
- * if none of the following factors are met: The cmd part is reset, or Data part
- * is reset, or A soft reset, or The cmd is about to send, or Clock divisor is
- * just updated, or Continue request is just set, or This bit is set, or Card
- * insertion is detected, or Card removal is detected, or Card external interrupt is
- * detected, or 80 clocks for initialization phase is ongoing
- *
- * Values:
- * - 0 - SDHC clock will be internally gated off.
- * - 1 - SDHC clock will not be automatically gated off.
- */
-//@{
-#define BP_SDHC_SYSCTL_PEREN (2U) //!< Bit position for SDHC_SYSCTL_PEREN.
-#define BM_SDHC_SYSCTL_PEREN (0x00000004U) //!< Bit mask for SDHC_SYSCTL_PEREN.
-#define BS_SDHC_SYSCTL_PEREN (1U) //!< Bit field size in bits for SDHC_SYSCTL_PEREN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_SYSCTL_PEREN field.
-#define BR_SDHC_SYSCTL_PEREN (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_PEREN))
-#endif
-
-//! @brief Format value for bitfield SDHC_SYSCTL_PEREN.
-#define BF_SDHC_SYSCTL_PEREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_PEREN), uint32_t) & BM_SDHC_SYSCTL_PEREN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PEREN field to a new value.
-#define BW_SDHC_SYSCTL_PEREN(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_PEREN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_SYSCTL, field SDCLKEN[3] (RW)
- *
- * The host controller shall stop SDCLK when writing this bit to 0. SDCLK
- * frequency can be changed when this bit is 0. Then, the host controller shall
- * maintain the same clock frequency until SDCLK is stopped (stop at SDCLK = 0). If the
- * IRQSTAT[CINS] is cleared, this bit must be cleared by the host driver to save
- * power.
- */
-//@{
-#define BP_SDHC_SYSCTL_SDCLKEN (3U) //!< Bit position for SDHC_SYSCTL_SDCLKEN.
-#define BM_SDHC_SYSCTL_SDCLKEN (0x00000008U) //!< Bit mask for SDHC_SYSCTL_SDCLKEN.
-#define BS_SDHC_SYSCTL_SDCLKEN (1U) //!< Bit field size in bits for SDHC_SYSCTL_SDCLKEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_SYSCTL_SDCLKEN field.
-#define BR_SDHC_SYSCTL_SDCLKEN (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_SDCLKEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_SYSCTL_SDCLKEN.
-#define BF_SDHC_SYSCTL_SDCLKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_SDCLKEN), uint32_t) & BM_SDHC_SYSCTL_SDCLKEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SDCLKEN field to a new value.
-#define BW_SDHC_SYSCTL_SDCLKEN(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_SDCLKEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_SYSCTL, field DVS[7:4] (RW)
- *
- * Used to provide a more exact divisor to generate the desired SD clock
- * frequency. Note the divider can even support odd divisor without deterioration of
- * duty cycle. The setting are as following:
- *
- * Values:
- * - 0 - Divisor by 1.
- * - 1 - Divisor by 2.
- * - 1110 - Divisor by 15.
- * - 1111 - Divisor by 16.
- */
-//@{
-#define BP_SDHC_SYSCTL_DVS (4U) //!< Bit position for SDHC_SYSCTL_DVS.
-#define BM_SDHC_SYSCTL_DVS (0x000000F0U) //!< Bit mask for SDHC_SYSCTL_DVS.
-#define BS_SDHC_SYSCTL_DVS (4U) //!< Bit field size in bits for SDHC_SYSCTL_DVS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_SYSCTL_DVS field.
-#define BR_SDHC_SYSCTL_DVS (HW_SDHC_SYSCTL.B.DVS)
-#endif
-
-//! @brief Format value for bitfield SDHC_SYSCTL_DVS.
-#define BF_SDHC_SYSCTL_DVS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_DVS), uint32_t) & BM_SDHC_SYSCTL_DVS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DVS field to a new value.
-#define BW_SDHC_SYSCTL_DVS(v) (HW_SDHC_SYSCTL_WR((HW_SDHC_SYSCTL_RD() & ~BM_SDHC_SYSCTL_DVS) | BF_SDHC_SYSCTL_DVS(v)))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_SYSCTL, field SDCLKFS[15:8] (RW)
- *
- * Used to select the frequency of the SDCLK pin. The frequency is not
- * programmed directly. Rather this register holds the prescaler (this register) and
- * divisor (next register) of the base clock frequency register. Setting 00h bypasses
- * the frequency prescaler of the SD Clock. Multiple bits must not be set, or the
- * behavior of this prescaler is undefined. The two default divider values can
- * be calculated by the frequency of SDHC clock and the following divisor bits.
- * The frequency of SDCLK is set by the following formula: Clock frequency = (Base
- * clock) / (prescaler x divisor) For example, if the base clock frequency is 96
- * MHz, and the target frequency is 25 MHz, then choosing the prescaler value of
- * 01h and divisor value of 1h will yield 24 MHz, which is the nearest frequency
- * less than or equal to the target. Similarly, to approach a clock value of 400
- * kHz, the prescaler value of 08h and divisor value of eh yields the exact clock
- * value of 400 kHz. The reset value of this field is 80h, so if the input base
- * clock ( SDHC clock ) is about 96 MHz, the default SD clock after reset is 375
- * kHz. According to the SD Physical Specification Version 1.1 and the SDIO Card
- * Specification Version 1.2, the maximum SD clock frequency is 50 MHz and shall
- * never exceed this limit. Only the following settings are allowed:
- *
- * Values:
- * - 1 - Base clock divided by 2.
- * - 10 - Base clock divided by 4.
- * - 100 - Base clock divided by 8.
- * - 1000 - Base clock divided by 16.
- * - 10000 - Base clock divided by 32.
- * - 100000 - Base clock divided by 64.
- * - 1000000 - Base clock divided by 128.
- * - 10000000 - Base clock divided by 256.
- */
-//@{
-#define BP_SDHC_SYSCTL_SDCLKFS (8U) //!< Bit position for SDHC_SYSCTL_SDCLKFS.
-#define BM_SDHC_SYSCTL_SDCLKFS (0x0000FF00U) //!< Bit mask for SDHC_SYSCTL_SDCLKFS.
-#define BS_SDHC_SYSCTL_SDCLKFS (8U) //!< Bit field size in bits for SDHC_SYSCTL_SDCLKFS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_SYSCTL_SDCLKFS field.
-#define BR_SDHC_SYSCTL_SDCLKFS (HW_SDHC_SYSCTL.B.SDCLKFS)
-#endif
-
-//! @brief Format value for bitfield SDHC_SYSCTL_SDCLKFS.
-#define BF_SDHC_SYSCTL_SDCLKFS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_SDCLKFS), uint32_t) & BM_SDHC_SYSCTL_SDCLKFS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SDCLKFS field to a new value.
-#define BW_SDHC_SYSCTL_SDCLKFS(v) (HW_SDHC_SYSCTL_WR((HW_SDHC_SYSCTL_RD() & ~BM_SDHC_SYSCTL_SDCLKFS) | BF_SDHC_SYSCTL_SDCLKFS(v)))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_SYSCTL, field DTOCV[19:16] (RW)
- *
- * Determines the interval by which DAT line timeouts are detected. See
- * IRQSTAT[DTOE] for information on factors that dictate time-out generation. Time-out
- * clock frequency will be generated by dividing the base clock SDCLK value by this
- * value. The host driver can clear IRQSTATEN[DTOESEN] to prevent inadvertent
- * time-out events.
- *
- * Values:
- * - 0000 - SDCLK x 2 13
- * - 0001 - SDCLK x 2 14
- * - 1110 - SDCLK x 2 27
- * - 1111 - Reserved
- */
-//@{
-#define BP_SDHC_SYSCTL_DTOCV (16U) //!< Bit position for SDHC_SYSCTL_DTOCV.
-#define BM_SDHC_SYSCTL_DTOCV (0x000F0000U) //!< Bit mask for SDHC_SYSCTL_DTOCV.
-#define BS_SDHC_SYSCTL_DTOCV (4U) //!< Bit field size in bits for SDHC_SYSCTL_DTOCV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_SYSCTL_DTOCV field.
-#define BR_SDHC_SYSCTL_DTOCV (HW_SDHC_SYSCTL.B.DTOCV)
-#endif
-
-//! @brief Format value for bitfield SDHC_SYSCTL_DTOCV.
-#define BF_SDHC_SYSCTL_DTOCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_DTOCV), uint32_t) & BM_SDHC_SYSCTL_DTOCV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DTOCV field to a new value.
-#define BW_SDHC_SYSCTL_DTOCV(v) (HW_SDHC_SYSCTL_WR((HW_SDHC_SYSCTL_RD() & ~BM_SDHC_SYSCTL_DTOCV) | BF_SDHC_SYSCTL_DTOCV(v)))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_SYSCTL, field RSTA[24] (WORZ)
- *
- * Effects the entire host controller except for the card detection circuit.
- * Register bits of type ROC, RW, RW1C, RWAC are cleared. During its initialization,
- * the host driver shall set this bit to 1 to reset the SDHC. The SDHC shall
- * reset this bit to 0 when the capabilities registers are valid and the host driver
- * can read them. Additional use of software reset for all does not affect the
- * value of the capabilities registers. After this bit is set, it is recommended
- * that the host driver reset the external card and reinitialize it.
- *
- * Values:
- * - 0 - No reset.
- * - 1 - Reset.
- */
-//@{
-#define BP_SDHC_SYSCTL_RSTA (24U) //!< Bit position for SDHC_SYSCTL_RSTA.
-#define BM_SDHC_SYSCTL_RSTA (0x01000000U) //!< Bit mask for SDHC_SYSCTL_RSTA.
-#define BS_SDHC_SYSCTL_RSTA (1U) //!< Bit field size in bits for SDHC_SYSCTL_RSTA.
-
-//! @brief Format value for bitfield SDHC_SYSCTL_RSTA.
-#define BF_SDHC_SYSCTL_RSTA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_RSTA), uint32_t) & BM_SDHC_SYSCTL_RSTA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RSTA field to a new value.
-#define BW_SDHC_SYSCTL_RSTA(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_RSTA) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_SYSCTL, field RSTC[25] (WORZ)
- *
- * Only part of the command circuit is reset. The following registers and bits
- * are cleared by this bit: PRSSTAT[CIHB] IRQSTAT[CC]
- *
- * Values:
- * - 0 - No reset.
- * - 1 - Reset.
- */
-//@{
-#define BP_SDHC_SYSCTL_RSTC (25U) //!< Bit position for SDHC_SYSCTL_RSTC.
-#define BM_SDHC_SYSCTL_RSTC (0x02000000U) //!< Bit mask for SDHC_SYSCTL_RSTC.
-#define BS_SDHC_SYSCTL_RSTC (1U) //!< Bit field size in bits for SDHC_SYSCTL_RSTC.
-
-//! @brief Format value for bitfield SDHC_SYSCTL_RSTC.
-#define BF_SDHC_SYSCTL_RSTC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_RSTC), uint32_t) & BM_SDHC_SYSCTL_RSTC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RSTC field to a new value.
-#define BW_SDHC_SYSCTL_RSTC(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_RSTC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_SYSCTL, field RSTD[26] (WORZ)
- *
- * Only part of the data circuit is reset. DMA circuit is also reset. The
- * following registers and bits are cleared by this bit: Data Port register Buffer Is
- * Cleared And Initialized.Present State register Buffer Read Enable Buffer Write
- * Enable Read Transfer Active Write Transfer Active DAT Line Active Command
- * Inhibit (DAT) Protocol Control register Continue Request Stop At Block Gap Request
- * Interrupt Status register Buffer Read Ready Buffer Write Ready DMA Interrupt
- * Block Gap Event Transfer Complete
- *
- * Values:
- * - 0 - No reset.
- * - 1 - Reset.
- */
-//@{
-#define BP_SDHC_SYSCTL_RSTD (26U) //!< Bit position for SDHC_SYSCTL_RSTD.
-#define BM_SDHC_SYSCTL_RSTD (0x04000000U) //!< Bit mask for SDHC_SYSCTL_RSTD.
-#define BS_SDHC_SYSCTL_RSTD (1U) //!< Bit field size in bits for SDHC_SYSCTL_RSTD.
-
-//! @brief Format value for bitfield SDHC_SYSCTL_RSTD.
-#define BF_SDHC_SYSCTL_RSTD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_RSTD), uint32_t) & BM_SDHC_SYSCTL_RSTD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RSTD field to a new value.
-#define BW_SDHC_SYSCTL_RSTD(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_RSTD) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_SYSCTL, field INITA[27] (RW)
- *
- * When this bit is set, 80 SD-clocks are sent to the card. After the 80 clocks
- * are sent, this bit is self-cleared. This bit is very useful during the card
- * power-up period when 74 SD-clocks are needed and the clock auto gating feature
- * is enabled. Writing 1 to this bit when this bit is already 1 has no effect.
- * Writing 0 to this bit at any time has no effect. When either of the PRSSTAT[CIHB]
- * and PRSSTAT[CDIHB] bits are set, writing 1 to this bit is ignored, that is,
- * when command line or data lines are active, write to this bit is not allowed.
- * On the otherhand, when this bit is set, that is, during intialization active
- * period, it is allowed to issue command, and the command bit stream will appear
- * on the CMD pad after all 80 clock cycles are done. So when this command ends,
- * the driver can make sure the 80 clock cycles are sent out. This is very useful
- * when the driver needs send 80 cycles to the card and does not want to wait
- * till this bit is self-cleared.
- */
-//@{
-#define BP_SDHC_SYSCTL_INITA (27U) //!< Bit position for SDHC_SYSCTL_INITA.
-#define BM_SDHC_SYSCTL_INITA (0x08000000U) //!< Bit mask for SDHC_SYSCTL_INITA.
-#define BS_SDHC_SYSCTL_INITA (1U) //!< Bit field size in bits for SDHC_SYSCTL_INITA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_SYSCTL_INITA field.
-#define BR_SDHC_SYSCTL_INITA (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_INITA))
-#endif
-
-//! @brief Format value for bitfield SDHC_SYSCTL_INITA.
-#define BF_SDHC_SYSCTL_INITA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_INITA), uint32_t) & BM_SDHC_SYSCTL_INITA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INITA field to a new value.
-#define BW_SDHC_SYSCTL_INITA(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_INITA) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SDHC_IRQSTAT - Interrupt Status register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SDHC_IRQSTAT - Interrupt Status register (RW)
- *
- * Reset value: 0x00000000U
- *
- * An interrupt is generated when the Normal Interrupt Signal Enable is enabled
- * and at least one of the status bits is set to 1. For all bits, writing 1 to a
- * bit clears it; writing to 0 keeps the bit unchanged. More than one status can
- * be cleared with a single register write. For Card Interrupt, before writing 1
- * to clear, it is required that the card stops asserting the interrupt, meaning
- * that when the Card Driver services the interrupt condition, otherwise the CINT
- * bit will be asserted again. The table below shows the relationship between
- * the CTOE and the CC bits. SDHC status for CTOE/CC bit combinations Command
- * complete Command timeout error Meaning of the status 0 0 X X 1 Response not
- * received within 64 SDCLK cycles 1 0 Response received The table below shows the
- * relationship between the Transfer Complete and the Data Timeout Error. SDHC status
- * for data timeout error/transfer complete bit combinations Transfer complete
- * Data timeout error Meaning of the status 0 0 X 0 1 Timeout occurred during
- * transfer 1 X Data transfer complete The table below shows the relationship between
- * the command CRC Error (CCE) and Command Timeout Error (CTOE). SDHC status for
- * CCE/CTOE Bit Combinations Command complete Command timeout error Meaning of
- * the status 0 0 No error 0 1 Response timeout error 1 0 Response CRC error 1 1
- * CMD line conflict
- */
-typedef union _hw_sdhc_irqstat
-{
- uint32_t U;
- struct _hw_sdhc_irqstat_bitfields
- {
- uint32_t CC : 1; //!< [0] Command Complete
- uint32_t TC : 1; //!< [1] Transfer Complete
- uint32_t BGE : 1; //!< [2] Block Gap Event
- uint32_t DINT : 1; //!< [3] DMA Interrupt
- uint32_t BWR : 1; //!< [4] Buffer Write Ready
- uint32_t BRR : 1; //!< [5] Buffer Read Ready
- uint32_t CINS : 1; //!< [6] Card Insertion
- uint32_t CRM : 1; //!< [7] Card Removal
- uint32_t CINT : 1; //!< [8] Card Interrupt
- uint32_t RESERVED0 : 7; //!< [15:9]
- uint32_t CTOE : 1; //!< [16] Command Timeout Error
- uint32_t CCE : 1; //!< [17] Command CRC Error
- uint32_t CEBE : 1; //!< [18] Command End Bit Error
- uint32_t CIE : 1; //!< [19] Command Index Error
- uint32_t DTOE : 1; //!< [20] Data Timeout Error
- uint32_t DCE : 1; //!< [21] Data CRC Error
- uint32_t DEBE : 1; //!< [22] Data End Bit Error
- uint32_t RESERVED1 : 1; //!< [23]
- uint32_t AC12E : 1; //!< [24] Auto CMD12 Error
- uint32_t RESERVED2 : 3; //!< [27:25]
- uint32_t DMAE : 1; //!< [28] DMA Error
- uint32_t RESERVED3 : 3; //!< [31:29]
- } B;
-} hw_sdhc_irqstat_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SDHC_IRQSTAT register
- */
-//@{
-#define HW_SDHC_IRQSTAT_ADDR (REGS_SDHC_BASE + 0x30U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SDHC_IRQSTAT (*(__IO hw_sdhc_irqstat_t *) HW_SDHC_IRQSTAT_ADDR)
-#define HW_SDHC_IRQSTAT_RD() (HW_SDHC_IRQSTAT.U)
-#define HW_SDHC_IRQSTAT_WR(v) (HW_SDHC_IRQSTAT.U = (v))
-#define HW_SDHC_IRQSTAT_SET(v) (HW_SDHC_IRQSTAT_WR(HW_SDHC_IRQSTAT_RD() | (v)))
-#define HW_SDHC_IRQSTAT_CLR(v) (HW_SDHC_IRQSTAT_WR(HW_SDHC_IRQSTAT_RD() & ~(v)))
-#define HW_SDHC_IRQSTAT_TOG(v) (HW_SDHC_IRQSTAT_WR(HW_SDHC_IRQSTAT_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SDHC_IRQSTAT bitfields
- */
-
-/*!
- * @name Register SDHC_IRQSTAT, field CC[0] (W1C)
- *
- * This bit is set when you receive the end bit of the command response, except
- * Auto CMD12. See PRSSTAT[CIHB].
- *
- * Values:
- * - 0 - Command not complete.
- * - 1 - Command complete.
- */
-//@{
-#define BP_SDHC_IRQSTAT_CC (0U) //!< Bit position for SDHC_IRQSTAT_CC.
-#define BM_SDHC_IRQSTAT_CC (0x00000001U) //!< Bit mask for SDHC_IRQSTAT_CC.
-#define BS_SDHC_IRQSTAT_CC (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTAT_CC field.
-#define BR_SDHC_IRQSTAT_CC (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CC))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTAT_CC.
-#define BF_SDHC_IRQSTAT_CC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CC), uint32_t) & BM_SDHC_IRQSTAT_CC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CC field to a new value.
-#define BW_SDHC_IRQSTAT_CC(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTAT, field TC[1] (W1C)
- *
- * This bit is set when a read or write transfer is completed. In the case of a
- * read transaction: This bit is set at the falling edge of the read transfer
- * active status. There are two cases in which this interrupt is generated. The
- * first is when a data transfer is completed as specified by the data length, after
- * the last data has been read to the host system. The second is when data has
- * stopped at the block gap and completed the data transfer by setting
- * PROCTL[SABGREQ], after valid data has been read to the host system. In the case of a write
- * transaction: This bit is set at the falling edge of the DAT line active
- * status. There are two cases in which this interrupt is generated. The first is when
- * the last data is written to the SD card as specified by the data length and
- * the busy signal is released. The second is when data transfers are stopped at
- * the block gap, by setting PROCTL[SABGREQ], and the data transfers are
- * completed,after valid data is written to the SD card and the busy signal released.
- *
- * Values:
- * - 0 - Transfer not complete.
- * - 1 - Transfer complete.
- */
-//@{
-#define BP_SDHC_IRQSTAT_TC (1U) //!< Bit position for SDHC_IRQSTAT_TC.
-#define BM_SDHC_IRQSTAT_TC (0x00000002U) //!< Bit mask for SDHC_IRQSTAT_TC.
-#define BS_SDHC_IRQSTAT_TC (1U) //!< Bit field size in bits for SDHC_IRQSTAT_TC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTAT_TC field.
-#define BR_SDHC_IRQSTAT_TC (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_TC))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTAT_TC.
-#define BF_SDHC_IRQSTAT_TC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_TC), uint32_t) & BM_SDHC_IRQSTAT_TC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TC field to a new value.
-#define BW_SDHC_IRQSTAT_TC(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_TC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTAT, field BGE[2] (W1C)
- *
- * If PROCTL[SABGREQ] is set, this bit is set when a read or write transaction
- * is stopped at a block gap. If PROCTL[SABGREQ] is not set to 1, this bit is not
- * set to 1. In the case of a read transaction: This bit is set at the falling
- * edge of the DAT line active status, when the transaction is stopped at SD Bus
- * timing. The read wait must be supported in order to use this function. In the
- * case of write transaction: This bit is set at the falling edge of write transfer
- * active status, after getting CRC status at SD bus timing.
- *
- * Values:
- * - 0 - No block gap event.
- * - 1 - Transaction stopped at block gap.
- */
-//@{
-#define BP_SDHC_IRQSTAT_BGE (2U) //!< Bit position for SDHC_IRQSTAT_BGE.
-#define BM_SDHC_IRQSTAT_BGE (0x00000004U) //!< Bit mask for SDHC_IRQSTAT_BGE.
-#define BS_SDHC_IRQSTAT_BGE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_BGE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTAT_BGE field.
-#define BR_SDHC_IRQSTAT_BGE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BGE))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTAT_BGE.
-#define BF_SDHC_IRQSTAT_BGE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_BGE), uint32_t) & BM_SDHC_IRQSTAT_BGE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BGE field to a new value.
-#define BW_SDHC_IRQSTAT_BGE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BGE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTAT, field DINT[3] (W1C)
- *
- * Occurs only when the internal DMA finishes the data transfer successfully.
- * Whenever errors occur during data transfer, this bit will not be set. Instead,
- * the DMAE bit will be set. Either Simple DMA or ADMA finishes data transferring,
- * this bit will be set.
- *
- * Values:
- * - 0 - No DMA Interrupt.
- * - 1 - DMA Interrupt is generated.
- */
-//@{
-#define BP_SDHC_IRQSTAT_DINT (3U) //!< Bit position for SDHC_IRQSTAT_DINT.
-#define BM_SDHC_IRQSTAT_DINT (0x00000008U) //!< Bit mask for SDHC_IRQSTAT_DINT.
-#define BS_SDHC_IRQSTAT_DINT (1U) //!< Bit field size in bits for SDHC_IRQSTAT_DINT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTAT_DINT field.
-#define BR_SDHC_IRQSTAT_DINT (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DINT))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTAT_DINT.
-#define BF_SDHC_IRQSTAT_DINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_DINT), uint32_t) & BM_SDHC_IRQSTAT_DINT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DINT field to a new value.
-#define BW_SDHC_IRQSTAT_DINT(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DINT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTAT, field BWR[4] (W1C)
- *
- * This status bit is set if the Buffer Write Enable bit, in the Present State
- * register, changes from 0 to 1. See the Buffer Write Enable bit in the Present
- * State register for additional information.
- *
- * Values:
- * - 0 - Not ready to write buffer.
- * - 1 - Ready to write buffer.
- */
-//@{
-#define BP_SDHC_IRQSTAT_BWR (4U) //!< Bit position for SDHC_IRQSTAT_BWR.
-#define BM_SDHC_IRQSTAT_BWR (0x00000010U) //!< Bit mask for SDHC_IRQSTAT_BWR.
-#define BS_SDHC_IRQSTAT_BWR (1U) //!< Bit field size in bits for SDHC_IRQSTAT_BWR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTAT_BWR field.
-#define BR_SDHC_IRQSTAT_BWR (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BWR))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTAT_BWR.
-#define BF_SDHC_IRQSTAT_BWR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_BWR), uint32_t) & BM_SDHC_IRQSTAT_BWR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BWR field to a new value.
-#define BW_SDHC_IRQSTAT_BWR(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BWR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTAT, field BRR[5] (W1C)
- *
- * This status bit is set if the Buffer Read Enable bit, in the Present State
- * register, changes from 0 to 1. See the Buffer Read Enable bit in the Present
- * State register for additional information.
- *
- * Values:
- * - 0 - Not ready to read buffer.
- * - 1 - Ready to read buffer.
- */
-//@{
-#define BP_SDHC_IRQSTAT_BRR (5U) //!< Bit position for SDHC_IRQSTAT_BRR.
-#define BM_SDHC_IRQSTAT_BRR (0x00000020U) //!< Bit mask for SDHC_IRQSTAT_BRR.
-#define BS_SDHC_IRQSTAT_BRR (1U) //!< Bit field size in bits for SDHC_IRQSTAT_BRR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTAT_BRR field.
-#define BR_SDHC_IRQSTAT_BRR (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BRR))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTAT_BRR.
-#define BF_SDHC_IRQSTAT_BRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_BRR), uint32_t) & BM_SDHC_IRQSTAT_BRR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BRR field to a new value.
-#define BW_SDHC_IRQSTAT_BRR(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BRR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTAT, field CINS[6] (W1C)
- *
- * This status bit is set if the Card Inserted bit in the Present State register
- * changes from 0 to 1. When the host driver writes this bit to 1 to clear this
- * status, the status of the Card Inserted in the Present State register must be
- * confirmed. Because the card state may possibly be changed when the host driver
- * clears this bit and the interrupt event may not be generated. When this bit
- * is cleared, it will be set again if a card is inserted. To leave it cleared,
- * clear the Card Inserted Status Enable bit in Interrupt Status Enable register.
- *
- * Values:
- * - 0 - Card state unstable or removed.
- * - 1 - Card inserted.
- */
-//@{
-#define BP_SDHC_IRQSTAT_CINS (6U) //!< Bit position for SDHC_IRQSTAT_CINS.
-#define BM_SDHC_IRQSTAT_CINS (0x00000040U) //!< Bit mask for SDHC_IRQSTAT_CINS.
-#define BS_SDHC_IRQSTAT_CINS (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CINS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTAT_CINS field.
-#define BR_SDHC_IRQSTAT_CINS (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CINS))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTAT_CINS.
-#define BF_SDHC_IRQSTAT_CINS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CINS), uint32_t) & BM_SDHC_IRQSTAT_CINS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CINS field to a new value.
-#define BW_SDHC_IRQSTAT_CINS(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CINS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTAT, field CRM[7] (W1C)
- *
- * This status bit is set if the Card Inserted bit in the Present State register
- * changes from 1 to 0. When the host driver writes this bit to 1 to clear this
- * status, the status of the Card Inserted in the Present State register must be
- * confirmed. Because the card state may possibly be changed when the host driver
- * clears this bit and the interrupt event may not be generated. When this bit
- * is cleared, it will be set again if no card is inserted. To leave it cleared,
- * clear the Card Removal Status Enable bit in Interrupt Status Enable register.
- *
- * Values:
- * - 0 - Card state unstable or inserted.
- * - 1 - Card removed.
- */
-//@{
-#define BP_SDHC_IRQSTAT_CRM (7U) //!< Bit position for SDHC_IRQSTAT_CRM.
-#define BM_SDHC_IRQSTAT_CRM (0x00000080U) //!< Bit mask for SDHC_IRQSTAT_CRM.
-#define BS_SDHC_IRQSTAT_CRM (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CRM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTAT_CRM field.
-#define BR_SDHC_IRQSTAT_CRM (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CRM))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTAT_CRM.
-#define BF_SDHC_IRQSTAT_CRM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CRM), uint32_t) & BM_SDHC_IRQSTAT_CRM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CRM field to a new value.
-#define BW_SDHC_IRQSTAT_CRM(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CRM) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTAT, field CINT[8] (W1C)
- *
- * This status bit is set when an interrupt signal is detected from the external
- * card. In 1-bit mode, the SDHC will detect the Card Interrupt without the SD
- * Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled
- * during the interrupt cycle, so the interrupt from card can only be sampled
- * during interrupt cycle, introducing some delay between the interrupt signal from
- * the SDIO card and the interrupt to the host system. Writing this bit to 1 can
- * clear this bit, but as the interrupt factor from the SDIO card does not clear,
- * this bit is set again. To clear this bit, it is required to reset the interrupt
- * factor from the external card followed by a writing 1 to this bit. When this
- * status has been set, and the host driver needs to service this interrupt, the
- * Card Interrupt Signal Enable in the Interrupt Signal Enable register should be
- * 0 to stop driving the interrupt signal to the host system. After completion
- * of the card interrupt service (it must reset the interrupt factors in the SDIO
- * card and the interrupt signal may not be asserted), write 1 to clear this bit,
- * set the Card Interrupt Signal Enable to 1, and start sampling the interrupt
- * signal again.
- *
- * Values:
- * - 0 - No Card Interrupt.
- * - 1 - Generate Card Interrupt.
- */
-//@{
-#define BP_SDHC_IRQSTAT_CINT (8U) //!< Bit position for SDHC_IRQSTAT_CINT.
-#define BM_SDHC_IRQSTAT_CINT (0x00000100U) //!< Bit mask for SDHC_IRQSTAT_CINT.
-#define BS_SDHC_IRQSTAT_CINT (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CINT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTAT_CINT field.
-#define BR_SDHC_IRQSTAT_CINT (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CINT))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTAT_CINT.
-#define BF_SDHC_IRQSTAT_CINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CINT), uint32_t) & BM_SDHC_IRQSTAT_CINT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CINT field to a new value.
-#define BW_SDHC_IRQSTAT_CINT(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CINT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTAT, field CTOE[16] (W1C)
- *
- * Occurs only if no response is returned within 64 SDCLK cycles from the end
- * bit of the command. If the SDHC detects a CMD line conflict, in which case a
- * Command CRC Error shall also be set, this bit shall be set without waiting for 64
- * SDCLK cycles. This is because the command will be aborted by the SDHC.
- *
- * Values:
- * - 0 - No error.
- * - 1 - Time out.
- */
-//@{
-#define BP_SDHC_IRQSTAT_CTOE (16U) //!< Bit position for SDHC_IRQSTAT_CTOE.
-#define BM_SDHC_IRQSTAT_CTOE (0x00010000U) //!< Bit mask for SDHC_IRQSTAT_CTOE.
-#define BS_SDHC_IRQSTAT_CTOE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CTOE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTAT_CTOE field.
-#define BR_SDHC_IRQSTAT_CTOE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CTOE))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTAT_CTOE.
-#define BF_SDHC_IRQSTAT_CTOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CTOE), uint32_t) & BM_SDHC_IRQSTAT_CTOE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CTOE field to a new value.
-#define BW_SDHC_IRQSTAT_CTOE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CTOE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTAT, field CCE[17] (W1C)
- *
- * Command CRC Error is generated in two cases. If a response is returned and
- * the Command Timeout Error is set to 0, indicating no time-out, this bit is set
- * when detecting a CRC error in the command response. The SDHC detects a CMD line
- * conflict by monitoring the CMD line when a command is issued. If the SDHC
- * drives the CMD line to 1, but detects 0 on the CMD line at the next SDCLK edge,
- * then the SDHC shall abort the command (Stop driving CMD line) and set this bit
- * to 1. The Command Timeout Error shall also be set to 1 to distinguish CMD line
- * conflict.
- *
- * Values:
- * - 0 - No error.
- * - 1 - CRC Error generated.
- */
-//@{
-#define BP_SDHC_IRQSTAT_CCE (17U) //!< Bit position for SDHC_IRQSTAT_CCE.
-#define BM_SDHC_IRQSTAT_CCE (0x00020000U) //!< Bit mask for SDHC_IRQSTAT_CCE.
-#define BS_SDHC_IRQSTAT_CCE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CCE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTAT_CCE field.
-#define BR_SDHC_IRQSTAT_CCE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CCE))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTAT_CCE.
-#define BF_SDHC_IRQSTAT_CCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CCE), uint32_t) & BM_SDHC_IRQSTAT_CCE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CCE field to a new value.
-#define BW_SDHC_IRQSTAT_CCE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CCE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTAT, field CEBE[18] (W1C)
- *
- * Occurs when detecting that the end bit of a command response is 0.
- *
- * Values:
- * - 0 - No error.
- * - 1 - End Bit Error generated.
- */
-//@{
-#define BP_SDHC_IRQSTAT_CEBE (18U) //!< Bit position for SDHC_IRQSTAT_CEBE.
-#define BM_SDHC_IRQSTAT_CEBE (0x00040000U) //!< Bit mask for SDHC_IRQSTAT_CEBE.
-#define BS_SDHC_IRQSTAT_CEBE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CEBE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTAT_CEBE field.
-#define BR_SDHC_IRQSTAT_CEBE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CEBE))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTAT_CEBE.
-#define BF_SDHC_IRQSTAT_CEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CEBE), uint32_t) & BM_SDHC_IRQSTAT_CEBE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CEBE field to a new value.
-#define BW_SDHC_IRQSTAT_CEBE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CEBE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTAT, field CIE[19] (W1C)
- *
- * Occurs if a Command Index error occurs in the command response.
- *
- * Values:
- * - 0 - No error.
- * - 1 - Error.
- */
-//@{
-#define BP_SDHC_IRQSTAT_CIE (19U) //!< Bit position for SDHC_IRQSTAT_CIE.
-#define BM_SDHC_IRQSTAT_CIE (0x00080000U) //!< Bit mask for SDHC_IRQSTAT_CIE.
-#define BS_SDHC_IRQSTAT_CIE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTAT_CIE field.
-#define BR_SDHC_IRQSTAT_CIE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CIE))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTAT_CIE.
-#define BF_SDHC_IRQSTAT_CIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CIE), uint32_t) & BM_SDHC_IRQSTAT_CIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CIE field to a new value.
-#define BW_SDHC_IRQSTAT_CIE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTAT, field DTOE[20] (W1C)
- *
- * Occurs when detecting one of following time-out conditions. Busy time-out for
- * R1b,R5b type Busy time-out after Write CRC status Read Data time-out
- *
- * Values:
- * - 0 - No error.
- * - 1 - Time out.
- */
-//@{
-#define BP_SDHC_IRQSTAT_DTOE (20U) //!< Bit position for SDHC_IRQSTAT_DTOE.
-#define BM_SDHC_IRQSTAT_DTOE (0x00100000U) //!< Bit mask for SDHC_IRQSTAT_DTOE.
-#define BS_SDHC_IRQSTAT_DTOE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_DTOE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTAT_DTOE field.
-#define BR_SDHC_IRQSTAT_DTOE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DTOE))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTAT_DTOE.
-#define BF_SDHC_IRQSTAT_DTOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_DTOE), uint32_t) & BM_SDHC_IRQSTAT_DTOE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DTOE field to a new value.
-#define BW_SDHC_IRQSTAT_DTOE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DTOE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTAT, field DCE[21] (W1C)
- *
- * Occurs when detecting a CRC error when transferring read data, which uses the
- * DAT line, or when detecting the Write CRC status having a value other than
- * 010.
- *
- * Values:
- * - 0 - No error.
- * - 1 - Error.
- */
-//@{
-#define BP_SDHC_IRQSTAT_DCE (21U) //!< Bit position for SDHC_IRQSTAT_DCE.
-#define BM_SDHC_IRQSTAT_DCE (0x00200000U) //!< Bit mask for SDHC_IRQSTAT_DCE.
-#define BS_SDHC_IRQSTAT_DCE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_DCE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTAT_DCE field.
-#define BR_SDHC_IRQSTAT_DCE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DCE))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTAT_DCE.
-#define BF_SDHC_IRQSTAT_DCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_DCE), uint32_t) & BM_SDHC_IRQSTAT_DCE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DCE field to a new value.
-#define BW_SDHC_IRQSTAT_DCE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DCE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTAT, field DEBE[22] (W1C)
- *
- * Occurs either when detecting 0 at the end bit position of read data, which
- * uses the DAT line, or at the end bit position of the CRC.
- *
- * Values:
- * - 0 - No error.
- * - 1 - Error.
- */
-//@{
-#define BP_SDHC_IRQSTAT_DEBE (22U) //!< Bit position for SDHC_IRQSTAT_DEBE.
-#define BM_SDHC_IRQSTAT_DEBE (0x00400000U) //!< Bit mask for SDHC_IRQSTAT_DEBE.
-#define BS_SDHC_IRQSTAT_DEBE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_DEBE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTAT_DEBE field.
-#define BR_SDHC_IRQSTAT_DEBE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DEBE))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTAT_DEBE.
-#define BF_SDHC_IRQSTAT_DEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_DEBE), uint32_t) & BM_SDHC_IRQSTAT_DEBE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DEBE field to a new value.
-#define BW_SDHC_IRQSTAT_DEBE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DEBE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTAT, field AC12E[24] (W1C)
- *
- * Occurs when detecting that one of the bits in the Auto CMD12 Error Status
- * register has changed from 0 to 1. This bit is set to 1, not only when the errors
- * in Auto CMD12 occur, but also when the Auto CMD12 is not executed due to the
- * previous command error.
- *
- * Values:
- * - 0 - No error.
- * - 1 - Error.
- */
-//@{
-#define BP_SDHC_IRQSTAT_AC12E (24U) //!< Bit position for SDHC_IRQSTAT_AC12E.
-#define BM_SDHC_IRQSTAT_AC12E (0x01000000U) //!< Bit mask for SDHC_IRQSTAT_AC12E.
-#define BS_SDHC_IRQSTAT_AC12E (1U) //!< Bit field size in bits for SDHC_IRQSTAT_AC12E.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTAT_AC12E field.
-#define BR_SDHC_IRQSTAT_AC12E (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_AC12E))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTAT_AC12E.
-#define BF_SDHC_IRQSTAT_AC12E(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_AC12E), uint32_t) & BM_SDHC_IRQSTAT_AC12E)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the AC12E field to a new value.
-#define BW_SDHC_IRQSTAT_AC12E(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_AC12E) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTAT, field DMAE[28] (W1C)
- *
- * Occurs when an Internal DMA transfer has failed. This bit is set to 1, when
- * some error occurs in the data transfer. This error can be caused by either
- * Simple DMA or ADMA, depending on which DMA is in use. The value in DMA System
- * Address register is the next fetch address where the error occurs. Because any
- * error corrupts the whole data block, the host driver shall restart the transfer
- * from the corrupted block boundary. The address of the block boundary can be
- * calculated either from the current DSADDR value or from the remaining number of
- * blocks and the block size.
- *
- * Values:
- * - 0 - No error.
- * - 1 - Error.
- */
-//@{
-#define BP_SDHC_IRQSTAT_DMAE (28U) //!< Bit position for SDHC_IRQSTAT_DMAE.
-#define BM_SDHC_IRQSTAT_DMAE (0x10000000U) //!< Bit mask for SDHC_IRQSTAT_DMAE.
-#define BS_SDHC_IRQSTAT_DMAE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_DMAE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTAT_DMAE field.
-#define BR_SDHC_IRQSTAT_DMAE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DMAE))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTAT_DMAE.
-#define BF_SDHC_IRQSTAT_DMAE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_DMAE), uint32_t) & BM_SDHC_IRQSTAT_DMAE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DMAE field to a new value.
-#define BW_SDHC_IRQSTAT_DMAE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DMAE) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SDHC_IRQSTATEN - Interrupt Status Enable register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SDHC_IRQSTATEN - Interrupt Status Enable register (RW)
- *
- * Reset value: 0x117F013FU
- *
- * Setting the bits in this register to 1 enables the corresponding interrupt
- * status to be set by the specified event. If any bit is cleared, the
- * corresponding interrupt status bit is also cleared, that is, when the bit in this register
- * is cleared, the corresponding bit in interrupt status register is always 0.
- * Depending on PROCTL[IABG] bit setting, SDHC may be programmed to sample the
- * card interrupt signal during the interrupt period and hold its value in the
- * flip-flop. There will be some delays on the card interrupt, asserted from the card,
- * to the time the host system is informed. To detect a CMD line conflict, the
- * host driver must set both IRQSTATEN[CTOESEN] and IRQSTATEN[CCESEN] to 1.
- */
-typedef union _hw_sdhc_irqstaten
-{
- uint32_t U;
- struct _hw_sdhc_irqstaten_bitfields
- {
- uint32_t CCSEN : 1; //!< [0] Command Complete Status Enable
- uint32_t TCSEN : 1; //!< [1] Transfer Complete Status Enable
- uint32_t BGESEN : 1; //!< [2] Block Gap Event Status Enable
- uint32_t DINTSEN : 1; //!< [3] DMA Interrupt Status Enable
- uint32_t BWRSEN : 1; //!< [4] Buffer Write Ready Status Enable
- uint32_t BRRSEN : 1; //!< [5] Buffer Read Ready Status Enable
- uint32_t CINSEN : 1; //!< [6] Card Insertion Status Enable
- uint32_t CRMSEN : 1; //!< [7] Card Removal Status Enable
- uint32_t CINTSEN : 1; //!< [8] Card Interrupt Status Enable
- uint32_t RESERVED0 : 7; //!< [15:9]
- uint32_t CTOESEN : 1; //!< [16] Command Timeout Error Status Enable
- uint32_t CCESEN : 1; //!< [17] Command CRC Error Status Enable
- uint32_t CEBESEN : 1; //!< [18] Command End Bit Error Status Enable
- uint32_t CIESEN : 1; //!< [19] Command Index Error Status Enable
- uint32_t DTOESEN : 1; //!< [20] Data Timeout Error Status Enable
- uint32_t DCESEN : 1; //!< [21] Data CRC Error Status Enable
- uint32_t DEBESEN : 1; //!< [22] Data End Bit Error Status Enable
- uint32_t RESERVED1 : 1; //!< [23]
- uint32_t AC12ESEN : 1; //!< [24] Auto CMD12 Error Status Enable
- uint32_t RESERVED2 : 3; //!< [27:25]
- uint32_t DMAESEN : 1; //!< [28] DMA Error Status Enable
- uint32_t RESERVED3 : 3; //!< [31:29]
- } B;
-} hw_sdhc_irqstaten_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SDHC_IRQSTATEN register
- */
-//@{
-#define HW_SDHC_IRQSTATEN_ADDR (REGS_SDHC_BASE + 0x34U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SDHC_IRQSTATEN (*(__IO hw_sdhc_irqstaten_t *) HW_SDHC_IRQSTATEN_ADDR)
-#define HW_SDHC_IRQSTATEN_RD() (HW_SDHC_IRQSTATEN.U)
-#define HW_SDHC_IRQSTATEN_WR(v) (HW_SDHC_IRQSTATEN.U = (v))
-#define HW_SDHC_IRQSTATEN_SET(v) (HW_SDHC_IRQSTATEN_WR(HW_SDHC_IRQSTATEN_RD() | (v)))
-#define HW_SDHC_IRQSTATEN_CLR(v) (HW_SDHC_IRQSTATEN_WR(HW_SDHC_IRQSTATEN_RD() & ~(v)))
-#define HW_SDHC_IRQSTATEN_TOG(v) (HW_SDHC_IRQSTATEN_WR(HW_SDHC_IRQSTATEN_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SDHC_IRQSTATEN bitfields
- */
-
-/*!
- * @name Register SDHC_IRQSTATEN, field CCSEN[0] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSTATEN_CCSEN (0U) //!< Bit position for SDHC_IRQSTATEN_CCSEN.
-#define BM_SDHC_IRQSTATEN_CCSEN (0x00000001U) //!< Bit mask for SDHC_IRQSTATEN_CCSEN.
-#define BS_SDHC_IRQSTATEN_CCSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CCSEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTATEN_CCSEN field.
-#define BR_SDHC_IRQSTATEN_CCSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CCSEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTATEN_CCSEN.
-#define BF_SDHC_IRQSTATEN_CCSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CCSEN), uint32_t) & BM_SDHC_IRQSTATEN_CCSEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CCSEN field to a new value.
-#define BW_SDHC_IRQSTATEN_CCSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CCSEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTATEN, field TCSEN[1] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSTATEN_TCSEN (1U) //!< Bit position for SDHC_IRQSTATEN_TCSEN.
-#define BM_SDHC_IRQSTATEN_TCSEN (0x00000002U) //!< Bit mask for SDHC_IRQSTATEN_TCSEN.
-#define BS_SDHC_IRQSTATEN_TCSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_TCSEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTATEN_TCSEN field.
-#define BR_SDHC_IRQSTATEN_TCSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_TCSEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTATEN_TCSEN.
-#define BF_SDHC_IRQSTATEN_TCSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_TCSEN), uint32_t) & BM_SDHC_IRQSTATEN_TCSEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TCSEN field to a new value.
-#define BW_SDHC_IRQSTATEN_TCSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_TCSEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTATEN, field BGESEN[2] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSTATEN_BGESEN (2U) //!< Bit position for SDHC_IRQSTATEN_BGESEN.
-#define BM_SDHC_IRQSTATEN_BGESEN (0x00000004U) //!< Bit mask for SDHC_IRQSTATEN_BGESEN.
-#define BS_SDHC_IRQSTATEN_BGESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_BGESEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTATEN_BGESEN field.
-#define BR_SDHC_IRQSTATEN_BGESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BGESEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTATEN_BGESEN.
-#define BF_SDHC_IRQSTATEN_BGESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_BGESEN), uint32_t) & BM_SDHC_IRQSTATEN_BGESEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BGESEN field to a new value.
-#define BW_SDHC_IRQSTATEN_BGESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BGESEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTATEN, field DINTSEN[3] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSTATEN_DINTSEN (3U) //!< Bit position for SDHC_IRQSTATEN_DINTSEN.
-#define BM_SDHC_IRQSTATEN_DINTSEN (0x00000008U) //!< Bit mask for SDHC_IRQSTATEN_DINTSEN.
-#define BS_SDHC_IRQSTATEN_DINTSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_DINTSEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTATEN_DINTSEN field.
-#define BR_SDHC_IRQSTATEN_DINTSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DINTSEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTATEN_DINTSEN.
-#define BF_SDHC_IRQSTATEN_DINTSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_DINTSEN), uint32_t) & BM_SDHC_IRQSTATEN_DINTSEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DINTSEN field to a new value.
-#define BW_SDHC_IRQSTATEN_DINTSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DINTSEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTATEN, field BWRSEN[4] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSTATEN_BWRSEN (4U) //!< Bit position for SDHC_IRQSTATEN_BWRSEN.
-#define BM_SDHC_IRQSTATEN_BWRSEN (0x00000010U) //!< Bit mask for SDHC_IRQSTATEN_BWRSEN.
-#define BS_SDHC_IRQSTATEN_BWRSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_BWRSEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTATEN_BWRSEN field.
-#define BR_SDHC_IRQSTATEN_BWRSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BWRSEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTATEN_BWRSEN.
-#define BF_SDHC_IRQSTATEN_BWRSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_BWRSEN), uint32_t) & BM_SDHC_IRQSTATEN_BWRSEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BWRSEN field to a new value.
-#define BW_SDHC_IRQSTATEN_BWRSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BWRSEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTATEN, field BRRSEN[5] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSTATEN_BRRSEN (5U) //!< Bit position for SDHC_IRQSTATEN_BRRSEN.
-#define BM_SDHC_IRQSTATEN_BRRSEN (0x00000020U) //!< Bit mask for SDHC_IRQSTATEN_BRRSEN.
-#define BS_SDHC_IRQSTATEN_BRRSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_BRRSEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTATEN_BRRSEN field.
-#define BR_SDHC_IRQSTATEN_BRRSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BRRSEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTATEN_BRRSEN.
-#define BF_SDHC_IRQSTATEN_BRRSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_BRRSEN), uint32_t) & BM_SDHC_IRQSTATEN_BRRSEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BRRSEN field to a new value.
-#define BW_SDHC_IRQSTATEN_BRRSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BRRSEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTATEN, field CINSEN[6] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSTATEN_CINSEN (6U) //!< Bit position for SDHC_IRQSTATEN_CINSEN.
-#define BM_SDHC_IRQSTATEN_CINSEN (0x00000040U) //!< Bit mask for SDHC_IRQSTATEN_CINSEN.
-#define BS_SDHC_IRQSTATEN_CINSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CINSEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTATEN_CINSEN field.
-#define BR_SDHC_IRQSTATEN_CINSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CINSEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTATEN_CINSEN.
-#define BF_SDHC_IRQSTATEN_CINSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CINSEN), uint32_t) & BM_SDHC_IRQSTATEN_CINSEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CINSEN field to a new value.
-#define BW_SDHC_IRQSTATEN_CINSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CINSEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTATEN, field CRMSEN[7] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSTATEN_CRMSEN (7U) //!< Bit position for SDHC_IRQSTATEN_CRMSEN.
-#define BM_SDHC_IRQSTATEN_CRMSEN (0x00000080U) //!< Bit mask for SDHC_IRQSTATEN_CRMSEN.
-#define BS_SDHC_IRQSTATEN_CRMSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CRMSEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTATEN_CRMSEN field.
-#define BR_SDHC_IRQSTATEN_CRMSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CRMSEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTATEN_CRMSEN.
-#define BF_SDHC_IRQSTATEN_CRMSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CRMSEN), uint32_t) & BM_SDHC_IRQSTATEN_CRMSEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CRMSEN field to a new value.
-#define BW_SDHC_IRQSTATEN_CRMSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CRMSEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTATEN, field CINTSEN[8] (RW)
- *
- * If this bit is set to 0, the SDHC will clear the interrupt request to the
- * system. The card interrupt detection is stopped when this bit is cleared and
- * restarted when this bit is set to 1. The host driver must clear the this bit
- * before servicing the card interrupt and must set this bit again after all interrupt
- * requests from the card are cleared to prevent inadvertent interrupts.
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSTATEN_CINTSEN (8U) //!< Bit position for SDHC_IRQSTATEN_CINTSEN.
-#define BM_SDHC_IRQSTATEN_CINTSEN (0x00000100U) //!< Bit mask for SDHC_IRQSTATEN_CINTSEN.
-#define BS_SDHC_IRQSTATEN_CINTSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CINTSEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTATEN_CINTSEN field.
-#define BR_SDHC_IRQSTATEN_CINTSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CINTSEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTATEN_CINTSEN.
-#define BF_SDHC_IRQSTATEN_CINTSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CINTSEN), uint32_t) & BM_SDHC_IRQSTATEN_CINTSEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CINTSEN field to a new value.
-#define BW_SDHC_IRQSTATEN_CINTSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CINTSEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTATEN, field CTOESEN[16] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSTATEN_CTOESEN (16U) //!< Bit position for SDHC_IRQSTATEN_CTOESEN.
-#define BM_SDHC_IRQSTATEN_CTOESEN (0x00010000U) //!< Bit mask for SDHC_IRQSTATEN_CTOESEN.
-#define BS_SDHC_IRQSTATEN_CTOESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CTOESEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTATEN_CTOESEN field.
-#define BR_SDHC_IRQSTATEN_CTOESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CTOESEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTATEN_CTOESEN.
-#define BF_SDHC_IRQSTATEN_CTOESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CTOESEN), uint32_t) & BM_SDHC_IRQSTATEN_CTOESEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CTOESEN field to a new value.
-#define BW_SDHC_IRQSTATEN_CTOESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CTOESEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTATEN, field CCESEN[17] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSTATEN_CCESEN (17U) //!< Bit position for SDHC_IRQSTATEN_CCESEN.
-#define BM_SDHC_IRQSTATEN_CCESEN (0x00020000U) //!< Bit mask for SDHC_IRQSTATEN_CCESEN.
-#define BS_SDHC_IRQSTATEN_CCESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CCESEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTATEN_CCESEN field.
-#define BR_SDHC_IRQSTATEN_CCESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CCESEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTATEN_CCESEN.
-#define BF_SDHC_IRQSTATEN_CCESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CCESEN), uint32_t) & BM_SDHC_IRQSTATEN_CCESEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CCESEN field to a new value.
-#define BW_SDHC_IRQSTATEN_CCESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CCESEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTATEN, field CEBESEN[18] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSTATEN_CEBESEN (18U) //!< Bit position for SDHC_IRQSTATEN_CEBESEN.
-#define BM_SDHC_IRQSTATEN_CEBESEN (0x00040000U) //!< Bit mask for SDHC_IRQSTATEN_CEBESEN.
-#define BS_SDHC_IRQSTATEN_CEBESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CEBESEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTATEN_CEBESEN field.
-#define BR_SDHC_IRQSTATEN_CEBESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CEBESEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTATEN_CEBESEN.
-#define BF_SDHC_IRQSTATEN_CEBESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CEBESEN), uint32_t) & BM_SDHC_IRQSTATEN_CEBESEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CEBESEN field to a new value.
-#define BW_SDHC_IRQSTATEN_CEBESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CEBESEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTATEN, field CIESEN[19] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSTATEN_CIESEN (19U) //!< Bit position for SDHC_IRQSTATEN_CIESEN.
-#define BM_SDHC_IRQSTATEN_CIESEN (0x00080000U) //!< Bit mask for SDHC_IRQSTATEN_CIESEN.
-#define BS_SDHC_IRQSTATEN_CIESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CIESEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTATEN_CIESEN field.
-#define BR_SDHC_IRQSTATEN_CIESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CIESEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTATEN_CIESEN.
-#define BF_SDHC_IRQSTATEN_CIESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CIESEN), uint32_t) & BM_SDHC_IRQSTATEN_CIESEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CIESEN field to a new value.
-#define BW_SDHC_IRQSTATEN_CIESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CIESEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTATEN, field DTOESEN[20] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSTATEN_DTOESEN (20U) //!< Bit position for SDHC_IRQSTATEN_DTOESEN.
-#define BM_SDHC_IRQSTATEN_DTOESEN (0x00100000U) //!< Bit mask for SDHC_IRQSTATEN_DTOESEN.
-#define BS_SDHC_IRQSTATEN_DTOESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_DTOESEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTATEN_DTOESEN field.
-#define BR_SDHC_IRQSTATEN_DTOESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DTOESEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTATEN_DTOESEN.
-#define BF_SDHC_IRQSTATEN_DTOESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_DTOESEN), uint32_t) & BM_SDHC_IRQSTATEN_DTOESEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DTOESEN field to a new value.
-#define BW_SDHC_IRQSTATEN_DTOESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DTOESEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTATEN, field DCESEN[21] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSTATEN_DCESEN (21U) //!< Bit position for SDHC_IRQSTATEN_DCESEN.
-#define BM_SDHC_IRQSTATEN_DCESEN (0x00200000U) //!< Bit mask for SDHC_IRQSTATEN_DCESEN.
-#define BS_SDHC_IRQSTATEN_DCESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_DCESEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTATEN_DCESEN field.
-#define BR_SDHC_IRQSTATEN_DCESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DCESEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTATEN_DCESEN.
-#define BF_SDHC_IRQSTATEN_DCESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_DCESEN), uint32_t) & BM_SDHC_IRQSTATEN_DCESEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DCESEN field to a new value.
-#define BW_SDHC_IRQSTATEN_DCESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DCESEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTATEN, field DEBESEN[22] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSTATEN_DEBESEN (22U) //!< Bit position for SDHC_IRQSTATEN_DEBESEN.
-#define BM_SDHC_IRQSTATEN_DEBESEN (0x00400000U) //!< Bit mask for SDHC_IRQSTATEN_DEBESEN.
-#define BS_SDHC_IRQSTATEN_DEBESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_DEBESEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTATEN_DEBESEN field.
-#define BR_SDHC_IRQSTATEN_DEBESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DEBESEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTATEN_DEBESEN.
-#define BF_SDHC_IRQSTATEN_DEBESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_DEBESEN), uint32_t) & BM_SDHC_IRQSTATEN_DEBESEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DEBESEN field to a new value.
-#define BW_SDHC_IRQSTATEN_DEBESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DEBESEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTATEN, field AC12ESEN[24] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSTATEN_AC12ESEN (24U) //!< Bit position for SDHC_IRQSTATEN_AC12ESEN.
-#define BM_SDHC_IRQSTATEN_AC12ESEN (0x01000000U) //!< Bit mask for SDHC_IRQSTATEN_AC12ESEN.
-#define BS_SDHC_IRQSTATEN_AC12ESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_AC12ESEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTATEN_AC12ESEN field.
-#define BR_SDHC_IRQSTATEN_AC12ESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_AC12ESEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTATEN_AC12ESEN.
-#define BF_SDHC_IRQSTATEN_AC12ESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_AC12ESEN), uint32_t) & BM_SDHC_IRQSTATEN_AC12ESEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the AC12ESEN field to a new value.
-#define BW_SDHC_IRQSTATEN_AC12ESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_AC12ESEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSTATEN, field DMAESEN[28] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSTATEN_DMAESEN (28U) //!< Bit position for SDHC_IRQSTATEN_DMAESEN.
-#define BM_SDHC_IRQSTATEN_DMAESEN (0x10000000U) //!< Bit mask for SDHC_IRQSTATEN_DMAESEN.
-#define BS_SDHC_IRQSTATEN_DMAESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_DMAESEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSTATEN_DMAESEN field.
-#define BR_SDHC_IRQSTATEN_DMAESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DMAESEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSTATEN_DMAESEN.
-#define BF_SDHC_IRQSTATEN_DMAESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_DMAESEN), uint32_t) & BM_SDHC_IRQSTATEN_DMAESEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DMAESEN field to a new value.
-#define BW_SDHC_IRQSTATEN_DMAESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DMAESEN) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SDHC_IRQSIGEN - Interrupt Signal Enable register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SDHC_IRQSIGEN - Interrupt Signal Enable register (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register is used to select which interrupt status is indicated to the
- * host system as the interrupt. All of these status bits share the same interrupt
- * line. Setting any of these bits to 1 enables interrupt generation. The
- * corresponding status register bit will generate an interrupt when the corresponding
- * interrupt signal enable bit is set.
- */
-typedef union _hw_sdhc_irqsigen
-{
- uint32_t U;
- struct _hw_sdhc_irqsigen_bitfields
- {
- uint32_t CCIEN : 1; //!< [0] Command Complete Interrupt Enable
- uint32_t TCIEN : 1; //!< [1] Transfer Complete Interrupt Enable
- uint32_t BGEIEN : 1; //!< [2] Block Gap Event Interrupt Enable
- uint32_t DINTIEN : 1; //!< [3] DMA Interrupt Enable
- uint32_t BWRIEN : 1; //!< [4] Buffer Write Ready Interrupt Enable
- uint32_t BRRIEN : 1; //!< [5] Buffer Read Ready Interrupt Enable
- uint32_t CINSIEN : 1; //!< [6] Card Insertion Interrupt Enable
- uint32_t CRMIEN : 1; //!< [7] Card Removal Interrupt Enable
- uint32_t CINTIEN : 1; //!< [8] Card Interrupt Enable
- uint32_t RESERVED0 : 7; //!< [15:9]
- uint32_t CTOEIEN : 1; //!< [16] Command Timeout Error Interrupt Enable
- uint32_t CCEIEN : 1; //!< [17] Command CRC Error Interrupt Enable
- uint32_t CEBEIEN : 1; //!< [18] Command End Bit Error Interrupt Enable
- uint32_t CIEIEN : 1; //!< [19] Command Index Error Interrupt Enable
- uint32_t DTOEIEN : 1; //!< [20] Data Timeout Error Interrupt Enable
- uint32_t DCEIEN : 1; //!< [21] Data CRC Error Interrupt Enable
- uint32_t DEBEIEN : 1; //!< [22] Data End Bit Error Interrupt Enable
- uint32_t RESERVED1 : 1; //!< [23]
- uint32_t AC12EIEN : 1; //!< [24] Auto CMD12 Error Interrupt Enable
- uint32_t RESERVED2 : 3; //!< [27:25]
- uint32_t DMAEIEN : 1; //!< [28] DMA Error Interrupt Enable
- uint32_t RESERVED3 : 3; //!< [31:29]
- } B;
-} hw_sdhc_irqsigen_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SDHC_IRQSIGEN register
- */
-//@{
-#define HW_SDHC_IRQSIGEN_ADDR (REGS_SDHC_BASE + 0x38U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SDHC_IRQSIGEN (*(__IO hw_sdhc_irqsigen_t *) HW_SDHC_IRQSIGEN_ADDR)
-#define HW_SDHC_IRQSIGEN_RD() (HW_SDHC_IRQSIGEN.U)
-#define HW_SDHC_IRQSIGEN_WR(v) (HW_SDHC_IRQSIGEN.U = (v))
-#define HW_SDHC_IRQSIGEN_SET(v) (HW_SDHC_IRQSIGEN_WR(HW_SDHC_IRQSIGEN_RD() | (v)))
-#define HW_SDHC_IRQSIGEN_CLR(v) (HW_SDHC_IRQSIGEN_WR(HW_SDHC_IRQSIGEN_RD() & ~(v)))
-#define HW_SDHC_IRQSIGEN_TOG(v) (HW_SDHC_IRQSIGEN_WR(HW_SDHC_IRQSIGEN_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SDHC_IRQSIGEN bitfields
- */
-
-/*!
- * @name Register SDHC_IRQSIGEN, field CCIEN[0] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSIGEN_CCIEN (0U) //!< Bit position for SDHC_IRQSIGEN_CCIEN.
-#define BM_SDHC_IRQSIGEN_CCIEN (0x00000001U) //!< Bit mask for SDHC_IRQSIGEN_CCIEN.
-#define BS_SDHC_IRQSIGEN_CCIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CCIEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSIGEN_CCIEN field.
-#define BR_SDHC_IRQSIGEN_CCIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CCIEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSIGEN_CCIEN.
-#define BF_SDHC_IRQSIGEN_CCIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CCIEN), uint32_t) & BM_SDHC_IRQSIGEN_CCIEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CCIEN field to a new value.
-#define BW_SDHC_IRQSIGEN_CCIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CCIEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSIGEN, field TCIEN[1] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSIGEN_TCIEN (1U) //!< Bit position for SDHC_IRQSIGEN_TCIEN.
-#define BM_SDHC_IRQSIGEN_TCIEN (0x00000002U) //!< Bit mask for SDHC_IRQSIGEN_TCIEN.
-#define BS_SDHC_IRQSIGEN_TCIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_TCIEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSIGEN_TCIEN field.
-#define BR_SDHC_IRQSIGEN_TCIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_TCIEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSIGEN_TCIEN.
-#define BF_SDHC_IRQSIGEN_TCIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_TCIEN), uint32_t) & BM_SDHC_IRQSIGEN_TCIEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TCIEN field to a new value.
-#define BW_SDHC_IRQSIGEN_TCIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_TCIEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSIGEN, field BGEIEN[2] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSIGEN_BGEIEN (2U) //!< Bit position for SDHC_IRQSIGEN_BGEIEN.
-#define BM_SDHC_IRQSIGEN_BGEIEN (0x00000004U) //!< Bit mask for SDHC_IRQSIGEN_BGEIEN.
-#define BS_SDHC_IRQSIGEN_BGEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_BGEIEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSIGEN_BGEIEN field.
-#define BR_SDHC_IRQSIGEN_BGEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BGEIEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSIGEN_BGEIEN.
-#define BF_SDHC_IRQSIGEN_BGEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_BGEIEN), uint32_t) & BM_SDHC_IRQSIGEN_BGEIEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BGEIEN field to a new value.
-#define BW_SDHC_IRQSIGEN_BGEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BGEIEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSIGEN, field DINTIEN[3] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSIGEN_DINTIEN (3U) //!< Bit position for SDHC_IRQSIGEN_DINTIEN.
-#define BM_SDHC_IRQSIGEN_DINTIEN (0x00000008U) //!< Bit mask for SDHC_IRQSIGEN_DINTIEN.
-#define BS_SDHC_IRQSIGEN_DINTIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_DINTIEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSIGEN_DINTIEN field.
-#define BR_SDHC_IRQSIGEN_DINTIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DINTIEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSIGEN_DINTIEN.
-#define BF_SDHC_IRQSIGEN_DINTIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_DINTIEN), uint32_t) & BM_SDHC_IRQSIGEN_DINTIEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DINTIEN field to a new value.
-#define BW_SDHC_IRQSIGEN_DINTIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DINTIEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSIGEN, field BWRIEN[4] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSIGEN_BWRIEN (4U) //!< Bit position for SDHC_IRQSIGEN_BWRIEN.
-#define BM_SDHC_IRQSIGEN_BWRIEN (0x00000010U) //!< Bit mask for SDHC_IRQSIGEN_BWRIEN.
-#define BS_SDHC_IRQSIGEN_BWRIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_BWRIEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSIGEN_BWRIEN field.
-#define BR_SDHC_IRQSIGEN_BWRIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BWRIEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSIGEN_BWRIEN.
-#define BF_SDHC_IRQSIGEN_BWRIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_BWRIEN), uint32_t) & BM_SDHC_IRQSIGEN_BWRIEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BWRIEN field to a new value.
-#define BW_SDHC_IRQSIGEN_BWRIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BWRIEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSIGEN, field BRRIEN[5] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSIGEN_BRRIEN (5U) //!< Bit position for SDHC_IRQSIGEN_BRRIEN.
-#define BM_SDHC_IRQSIGEN_BRRIEN (0x00000020U) //!< Bit mask for SDHC_IRQSIGEN_BRRIEN.
-#define BS_SDHC_IRQSIGEN_BRRIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_BRRIEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSIGEN_BRRIEN field.
-#define BR_SDHC_IRQSIGEN_BRRIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BRRIEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSIGEN_BRRIEN.
-#define BF_SDHC_IRQSIGEN_BRRIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_BRRIEN), uint32_t) & BM_SDHC_IRQSIGEN_BRRIEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BRRIEN field to a new value.
-#define BW_SDHC_IRQSIGEN_BRRIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BRRIEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSIGEN, field CINSIEN[6] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSIGEN_CINSIEN (6U) //!< Bit position for SDHC_IRQSIGEN_CINSIEN.
-#define BM_SDHC_IRQSIGEN_CINSIEN (0x00000040U) //!< Bit mask for SDHC_IRQSIGEN_CINSIEN.
-#define BS_SDHC_IRQSIGEN_CINSIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CINSIEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSIGEN_CINSIEN field.
-#define BR_SDHC_IRQSIGEN_CINSIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CINSIEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSIGEN_CINSIEN.
-#define BF_SDHC_IRQSIGEN_CINSIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CINSIEN), uint32_t) & BM_SDHC_IRQSIGEN_CINSIEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CINSIEN field to a new value.
-#define BW_SDHC_IRQSIGEN_CINSIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CINSIEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSIGEN, field CRMIEN[7] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSIGEN_CRMIEN (7U) //!< Bit position for SDHC_IRQSIGEN_CRMIEN.
-#define BM_SDHC_IRQSIGEN_CRMIEN (0x00000080U) //!< Bit mask for SDHC_IRQSIGEN_CRMIEN.
-#define BS_SDHC_IRQSIGEN_CRMIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CRMIEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSIGEN_CRMIEN field.
-#define BR_SDHC_IRQSIGEN_CRMIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CRMIEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSIGEN_CRMIEN.
-#define BF_SDHC_IRQSIGEN_CRMIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CRMIEN), uint32_t) & BM_SDHC_IRQSIGEN_CRMIEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CRMIEN field to a new value.
-#define BW_SDHC_IRQSIGEN_CRMIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CRMIEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSIGEN, field CINTIEN[8] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSIGEN_CINTIEN (8U) //!< Bit position for SDHC_IRQSIGEN_CINTIEN.
-#define BM_SDHC_IRQSIGEN_CINTIEN (0x00000100U) //!< Bit mask for SDHC_IRQSIGEN_CINTIEN.
-#define BS_SDHC_IRQSIGEN_CINTIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CINTIEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSIGEN_CINTIEN field.
-#define BR_SDHC_IRQSIGEN_CINTIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CINTIEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSIGEN_CINTIEN.
-#define BF_SDHC_IRQSIGEN_CINTIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CINTIEN), uint32_t) & BM_SDHC_IRQSIGEN_CINTIEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CINTIEN field to a new value.
-#define BW_SDHC_IRQSIGEN_CINTIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CINTIEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSIGEN, field CTOEIEN[16] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSIGEN_CTOEIEN (16U) //!< Bit position for SDHC_IRQSIGEN_CTOEIEN.
-#define BM_SDHC_IRQSIGEN_CTOEIEN (0x00010000U) //!< Bit mask for SDHC_IRQSIGEN_CTOEIEN.
-#define BS_SDHC_IRQSIGEN_CTOEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CTOEIEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSIGEN_CTOEIEN field.
-#define BR_SDHC_IRQSIGEN_CTOEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CTOEIEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSIGEN_CTOEIEN.
-#define BF_SDHC_IRQSIGEN_CTOEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CTOEIEN), uint32_t) & BM_SDHC_IRQSIGEN_CTOEIEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CTOEIEN field to a new value.
-#define BW_SDHC_IRQSIGEN_CTOEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CTOEIEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSIGEN, field CCEIEN[17] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSIGEN_CCEIEN (17U) //!< Bit position for SDHC_IRQSIGEN_CCEIEN.
-#define BM_SDHC_IRQSIGEN_CCEIEN (0x00020000U) //!< Bit mask for SDHC_IRQSIGEN_CCEIEN.
-#define BS_SDHC_IRQSIGEN_CCEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CCEIEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSIGEN_CCEIEN field.
-#define BR_SDHC_IRQSIGEN_CCEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CCEIEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSIGEN_CCEIEN.
-#define BF_SDHC_IRQSIGEN_CCEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CCEIEN), uint32_t) & BM_SDHC_IRQSIGEN_CCEIEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CCEIEN field to a new value.
-#define BW_SDHC_IRQSIGEN_CCEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CCEIEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSIGEN, field CEBEIEN[18] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSIGEN_CEBEIEN (18U) //!< Bit position for SDHC_IRQSIGEN_CEBEIEN.
-#define BM_SDHC_IRQSIGEN_CEBEIEN (0x00040000U) //!< Bit mask for SDHC_IRQSIGEN_CEBEIEN.
-#define BS_SDHC_IRQSIGEN_CEBEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CEBEIEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSIGEN_CEBEIEN field.
-#define BR_SDHC_IRQSIGEN_CEBEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CEBEIEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSIGEN_CEBEIEN.
-#define BF_SDHC_IRQSIGEN_CEBEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CEBEIEN), uint32_t) & BM_SDHC_IRQSIGEN_CEBEIEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CEBEIEN field to a new value.
-#define BW_SDHC_IRQSIGEN_CEBEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CEBEIEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSIGEN, field CIEIEN[19] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSIGEN_CIEIEN (19U) //!< Bit position for SDHC_IRQSIGEN_CIEIEN.
-#define BM_SDHC_IRQSIGEN_CIEIEN (0x00080000U) //!< Bit mask for SDHC_IRQSIGEN_CIEIEN.
-#define BS_SDHC_IRQSIGEN_CIEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CIEIEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSIGEN_CIEIEN field.
-#define BR_SDHC_IRQSIGEN_CIEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CIEIEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSIGEN_CIEIEN.
-#define BF_SDHC_IRQSIGEN_CIEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CIEIEN), uint32_t) & BM_SDHC_IRQSIGEN_CIEIEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CIEIEN field to a new value.
-#define BW_SDHC_IRQSIGEN_CIEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CIEIEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSIGEN, field DTOEIEN[20] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSIGEN_DTOEIEN (20U) //!< Bit position for SDHC_IRQSIGEN_DTOEIEN.
-#define BM_SDHC_IRQSIGEN_DTOEIEN (0x00100000U) //!< Bit mask for SDHC_IRQSIGEN_DTOEIEN.
-#define BS_SDHC_IRQSIGEN_DTOEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_DTOEIEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSIGEN_DTOEIEN field.
-#define BR_SDHC_IRQSIGEN_DTOEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DTOEIEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSIGEN_DTOEIEN.
-#define BF_SDHC_IRQSIGEN_DTOEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_DTOEIEN), uint32_t) & BM_SDHC_IRQSIGEN_DTOEIEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DTOEIEN field to a new value.
-#define BW_SDHC_IRQSIGEN_DTOEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DTOEIEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSIGEN, field DCEIEN[21] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSIGEN_DCEIEN (21U) //!< Bit position for SDHC_IRQSIGEN_DCEIEN.
-#define BM_SDHC_IRQSIGEN_DCEIEN (0x00200000U) //!< Bit mask for SDHC_IRQSIGEN_DCEIEN.
-#define BS_SDHC_IRQSIGEN_DCEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_DCEIEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSIGEN_DCEIEN field.
-#define BR_SDHC_IRQSIGEN_DCEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DCEIEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSIGEN_DCEIEN.
-#define BF_SDHC_IRQSIGEN_DCEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_DCEIEN), uint32_t) & BM_SDHC_IRQSIGEN_DCEIEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DCEIEN field to a new value.
-#define BW_SDHC_IRQSIGEN_DCEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DCEIEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSIGEN, field DEBEIEN[22] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSIGEN_DEBEIEN (22U) //!< Bit position for SDHC_IRQSIGEN_DEBEIEN.
-#define BM_SDHC_IRQSIGEN_DEBEIEN (0x00400000U) //!< Bit mask for SDHC_IRQSIGEN_DEBEIEN.
-#define BS_SDHC_IRQSIGEN_DEBEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_DEBEIEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSIGEN_DEBEIEN field.
-#define BR_SDHC_IRQSIGEN_DEBEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DEBEIEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSIGEN_DEBEIEN.
-#define BF_SDHC_IRQSIGEN_DEBEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_DEBEIEN), uint32_t) & BM_SDHC_IRQSIGEN_DEBEIEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DEBEIEN field to a new value.
-#define BW_SDHC_IRQSIGEN_DEBEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DEBEIEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSIGEN, field AC12EIEN[24] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSIGEN_AC12EIEN (24U) //!< Bit position for SDHC_IRQSIGEN_AC12EIEN.
-#define BM_SDHC_IRQSIGEN_AC12EIEN (0x01000000U) //!< Bit mask for SDHC_IRQSIGEN_AC12EIEN.
-#define BS_SDHC_IRQSIGEN_AC12EIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_AC12EIEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSIGEN_AC12EIEN field.
-#define BR_SDHC_IRQSIGEN_AC12EIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_AC12EIEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSIGEN_AC12EIEN.
-#define BF_SDHC_IRQSIGEN_AC12EIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_AC12EIEN), uint32_t) & BM_SDHC_IRQSIGEN_AC12EIEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the AC12EIEN field to a new value.
-#define BW_SDHC_IRQSIGEN_AC12EIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_AC12EIEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_IRQSIGEN, field DMAEIEN[28] (RW)
- *
- * Values:
- * - 0 - Masked
- * - 1 - Enabled
- */
-//@{
-#define BP_SDHC_IRQSIGEN_DMAEIEN (28U) //!< Bit position for SDHC_IRQSIGEN_DMAEIEN.
-#define BM_SDHC_IRQSIGEN_DMAEIEN (0x10000000U) //!< Bit mask for SDHC_IRQSIGEN_DMAEIEN.
-#define BS_SDHC_IRQSIGEN_DMAEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_DMAEIEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_IRQSIGEN_DMAEIEN field.
-#define BR_SDHC_IRQSIGEN_DMAEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DMAEIEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_IRQSIGEN_DMAEIEN.
-#define BF_SDHC_IRQSIGEN_DMAEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_DMAEIEN), uint32_t) & BM_SDHC_IRQSIGEN_DMAEIEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DMAEIEN field to a new value.
-#define BW_SDHC_IRQSIGEN_DMAEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DMAEIEN) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SDHC_AC12ERR - Auto CMD12 Error Status Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SDHC_AC12ERR - Auto CMD12 Error Status Register (RO)
- *
- * Reset value: 0x00000000U
- *
- * When the AC12ESEN bit in the Status register is set, the host driver shall
- * check this register to identify what kind of error the Auto CMD12 indicated.
- * This register is valid only when the Auto CMD12 Error status bit is set. The
- * following table shows the relationship between the Auto CMGD12 CRC error and the
- * Auto CMD12 command timeout error. Relationship between Command CRC Error and
- * Command Timeout Error For Auto CMD12 Auto CMD12 CRC error Auto CMD12 timeout
- * error Type of error 0 0 No error 0 1 Response timeout error 1 0 Response CRC
- * error 1 1 CMD line conflict Changes in Auto CMD12 Error Status register can be
- * classified in three scenarios: When the SDHC is going to issue an Auto CMD12: Set
- * bit 0 to 1 if the Auto CMD12 can't be issued due to an error in the previous
- * command. Set bit 0 to 0 if the auto CMD12 is issued. At the end bit of an auto
- * CMD12 response: Check errors corresponding to bits 1-4. Set bits 1-4
- * corresponding to detected errors. Clear bits 1-4 corresponding to detected errors.
- * Before reading the Auto CMD12 error status bit 7: Set bit 7 to 1 if there is a
- * command that can't be issued. Clear bit 7 if there is no command to issue. The
- * timing for generating the auto CMD12 error and writing to the command register
- * are asynchronous. After that, bit 7 shall be sampled when the driver is not
- * writing to the command register. So it is suggested to read this register only
- * when IRQSTAT[AC12E] is set. An Auto CMD12 error interrupt is generated when one
- * of the error bits (0-4) is set to 1. The command not issued by auto CMD12
- * error does not generate an interrupt.
- */
-typedef union _hw_sdhc_ac12err
-{
- uint32_t U;
- struct _hw_sdhc_ac12err_bitfields
- {
- uint32_t AC12NE : 1; //!< [0] Auto CMD12 Not Executed
- uint32_t AC12TOE : 1; //!< [1] Auto CMD12 Timeout Error
- uint32_t AC12EBE : 1; //!< [2] Auto CMD12 End Bit Error
- uint32_t AC12CE : 1; //!< [3] Auto CMD12 CRC Error
- uint32_t AC12IE : 1; //!< [4] Auto CMD12 Index Error
- uint32_t RESERVED0 : 2; //!< [6:5]
- uint32_t CNIBAC12E : 1; //!< [7] Command Not Issued By Auto CMD12
- //! Error
- uint32_t RESERVED1 : 24; //!< [31:8]
- } B;
-} hw_sdhc_ac12err_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SDHC_AC12ERR register
- */
-//@{
-#define HW_SDHC_AC12ERR_ADDR (REGS_SDHC_BASE + 0x3CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SDHC_AC12ERR (*(__I hw_sdhc_ac12err_t *) HW_SDHC_AC12ERR_ADDR)
-#define HW_SDHC_AC12ERR_RD() (HW_SDHC_AC12ERR.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual SDHC_AC12ERR bitfields
- */
-
-/*!
- * @name Register SDHC_AC12ERR, field AC12NE[0] (RO)
- *
- * If memory multiple block data transfer is not started, due to a command
- * error, this bit is not set because it is not necessary to issue an auto CMD12.
- * Setting this bit to 1 means the SDHC cannot issue the auto CMD12 to stop a memory
- * multiple block data transfer due to some error. If this bit is set to 1, other
- * error status bits (1-4) have no meaning.
- *
- * Values:
- * - 0 - Executed.
- * - 1 - Not executed.
- */
-//@{
-#define BP_SDHC_AC12ERR_AC12NE (0U) //!< Bit position for SDHC_AC12ERR_AC12NE.
-#define BM_SDHC_AC12ERR_AC12NE (0x00000001U) //!< Bit mask for SDHC_AC12ERR_AC12NE.
-#define BS_SDHC_AC12ERR_AC12NE (1U) //!< Bit field size in bits for SDHC_AC12ERR_AC12NE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_AC12ERR_AC12NE field.
-#define BR_SDHC_AC12ERR_AC12NE (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_AC12NE))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_AC12ERR, field AC12TOE[1] (RO)
- *
- * Occurs if no response is returned within 64 SDCLK cycles from the end bit of
- * the command. If this bit is set to 1, the other error status bits (2-4) have
- * no meaning.
- *
- * Values:
- * - 0 - No error.
- * - 1 - Time out.
- */
-//@{
-#define BP_SDHC_AC12ERR_AC12TOE (1U) //!< Bit position for SDHC_AC12ERR_AC12TOE.
-#define BM_SDHC_AC12ERR_AC12TOE (0x00000002U) //!< Bit mask for SDHC_AC12ERR_AC12TOE.
-#define BS_SDHC_AC12ERR_AC12TOE (1U) //!< Bit field size in bits for SDHC_AC12ERR_AC12TOE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_AC12ERR_AC12TOE field.
-#define BR_SDHC_AC12ERR_AC12TOE (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_AC12TOE))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_AC12ERR, field AC12EBE[2] (RO)
- *
- * Occurs when detecting that the end bit of command response is 0 which must be
- * 1.
- *
- * Values:
- * - 0 - No error.
- * - 1 - End bit error generated.
- */
-//@{
-#define BP_SDHC_AC12ERR_AC12EBE (2U) //!< Bit position for SDHC_AC12ERR_AC12EBE.
-#define BM_SDHC_AC12ERR_AC12EBE (0x00000004U) //!< Bit mask for SDHC_AC12ERR_AC12EBE.
-#define BS_SDHC_AC12ERR_AC12EBE (1U) //!< Bit field size in bits for SDHC_AC12ERR_AC12EBE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_AC12ERR_AC12EBE field.
-#define BR_SDHC_AC12ERR_AC12EBE (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_AC12EBE))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_AC12ERR, field AC12CE[3] (RO)
- *
- * Occurs when detecting a CRC error in the command response.
- *
- * Values:
- * - 0 - No CRC error.
- * - 1 - CRC error met in Auto CMD12 response.
- */
-//@{
-#define BP_SDHC_AC12ERR_AC12CE (3U) //!< Bit position for SDHC_AC12ERR_AC12CE.
-#define BM_SDHC_AC12ERR_AC12CE (0x00000008U) //!< Bit mask for SDHC_AC12ERR_AC12CE.
-#define BS_SDHC_AC12ERR_AC12CE (1U) //!< Bit field size in bits for SDHC_AC12ERR_AC12CE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_AC12ERR_AC12CE field.
-#define BR_SDHC_AC12ERR_AC12CE (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_AC12CE))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_AC12ERR, field AC12IE[4] (RO)
- *
- * Occurs if the command index error occurs in response to a command.
- *
- * Values:
- * - 0 - No error.
- * - 1 - Error, the CMD index in response is not CMD12.
- */
-//@{
-#define BP_SDHC_AC12ERR_AC12IE (4U) //!< Bit position for SDHC_AC12ERR_AC12IE.
-#define BM_SDHC_AC12ERR_AC12IE (0x00000010U) //!< Bit mask for SDHC_AC12ERR_AC12IE.
-#define BS_SDHC_AC12ERR_AC12IE (1U) //!< Bit field size in bits for SDHC_AC12ERR_AC12IE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_AC12ERR_AC12IE field.
-#define BR_SDHC_AC12ERR_AC12IE (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_AC12IE))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_AC12ERR, field CNIBAC12E[7] (RO)
- *
- * Setting this bit to 1 means CMD_wo_DAT is not executed due to an auto CMD12
- * error (D04-D01) in this register.
- *
- * Values:
- * - 0 - No error.
- * - 1 - Not issued.
- */
-//@{
-#define BP_SDHC_AC12ERR_CNIBAC12E (7U) //!< Bit position for SDHC_AC12ERR_CNIBAC12E.
-#define BM_SDHC_AC12ERR_CNIBAC12E (0x00000080U) //!< Bit mask for SDHC_AC12ERR_CNIBAC12E.
-#define BS_SDHC_AC12ERR_CNIBAC12E (1U) //!< Bit field size in bits for SDHC_AC12ERR_CNIBAC12E.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_AC12ERR_CNIBAC12E field.
-#define BR_SDHC_AC12ERR_CNIBAC12E (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_CNIBAC12E))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SDHC_HTCAPBLT - Host Controller Capabilities
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SDHC_HTCAPBLT - Host Controller Capabilities (RO)
- *
- * Reset value: 0x07F30000U
- *
- * This register provides the host driver with information specific to the SDHC
- * implementation. The value in this register is the power-on-reset value, and
- * does not change with a software reset. Any write to this register is ignored.
- */
-typedef union _hw_sdhc_htcapblt
-{
- uint32_t U;
- struct _hw_sdhc_htcapblt_bitfields
- {
- uint32_t RESERVED0 : 16; //!< [15:0]
- uint32_t MBL : 3; //!< [18:16] Max Block Length
- uint32_t RESERVED1 : 1; //!< [19]
- uint32_t ADMAS : 1; //!< [20] ADMA Support
- uint32_t HSS : 1; //!< [21] High Speed Support
- uint32_t DMAS : 1; //!< [22] DMA Support
- uint32_t SRS : 1; //!< [23] Suspend/Resume Support
- uint32_t VS33 : 1; //!< [24] Voltage Support 3.3 V
- uint32_t RESERVED2 : 7; //!< [31:25]
- } B;
-} hw_sdhc_htcapblt_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SDHC_HTCAPBLT register
- */
-//@{
-#define HW_SDHC_HTCAPBLT_ADDR (REGS_SDHC_BASE + 0x40U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SDHC_HTCAPBLT (*(__I hw_sdhc_htcapblt_t *) HW_SDHC_HTCAPBLT_ADDR)
-#define HW_SDHC_HTCAPBLT_RD() (HW_SDHC_HTCAPBLT.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual SDHC_HTCAPBLT bitfields
- */
-
-/*!
- * @name Register SDHC_HTCAPBLT, field MBL[18:16] (RO)
- *
- * This value indicates the maximum block size that the host driver can read and
- * write to the buffer in the SDHC. The buffer shall transfer block size without
- * wait cycles.
- *
- * Values:
- * - 000 - 512 bytes
- * - 001 - 1024 bytes
- * - 010 - 2048 bytes
- * - 011 - 4096 bytes
- */
-//@{
-#define BP_SDHC_HTCAPBLT_MBL (16U) //!< Bit position for SDHC_HTCAPBLT_MBL.
-#define BM_SDHC_HTCAPBLT_MBL (0x00070000U) //!< Bit mask for SDHC_HTCAPBLT_MBL.
-#define BS_SDHC_HTCAPBLT_MBL (3U) //!< Bit field size in bits for SDHC_HTCAPBLT_MBL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_HTCAPBLT_MBL field.
-#define BR_SDHC_HTCAPBLT_MBL (HW_SDHC_HTCAPBLT.B.MBL)
-#endif
-//@}
-
-/*!
- * @name Register SDHC_HTCAPBLT, field ADMAS[20] (RO)
- *
- * This bit indicates whether the SDHC supports the ADMA feature.
- *
- * Values:
- * - 0 - Advanced DMA not supported.
- * - 1 - Advanced DMA supported.
- */
-//@{
-#define BP_SDHC_HTCAPBLT_ADMAS (20U) //!< Bit position for SDHC_HTCAPBLT_ADMAS.
-#define BM_SDHC_HTCAPBLT_ADMAS (0x00100000U) //!< Bit mask for SDHC_HTCAPBLT_ADMAS.
-#define BS_SDHC_HTCAPBLT_ADMAS (1U) //!< Bit field size in bits for SDHC_HTCAPBLT_ADMAS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_HTCAPBLT_ADMAS field.
-#define BR_SDHC_HTCAPBLT_ADMAS (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR, BP_SDHC_HTCAPBLT_ADMAS))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_HTCAPBLT, field HSS[21] (RO)
- *
- * This bit indicates whether the SDHC supports high speed mode and the host
- * system can supply a SD Clock frequency from 25 MHz to 50 MHz.
- *
- * Values:
- * - 0 - High speed not supported.
- * - 1 - High speed supported.
- */
-//@{
-#define BP_SDHC_HTCAPBLT_HSS (21U) //!< Bit position for SDHC_HTCAPBLT_HSS.
-#define BM_SDHC_HTCAPBLT_HSS (0x00200000U) //!< Bit mask for SDHC_HTCAPBLT_HSS.
-#define BS_SDHC_HTCAPBLT_HSS (1U) //!< Bit field size in bits for SDHC_HTCAPBLT_HSS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_HTCAPBLT_HSS field.
-#define BR_SDHC_HTCAPBLT_HSS (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR, BP_SDHC_HTCAPBLT_HSS))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_HTCAPBLT, field DMAS[22] (RO)
- *
- * This bit indicates whether the SDHC is capable of using the internal DMA to
- * transfer data between system memory and the data buffer directly.
- *
- * Values:
- * - 0 - DMA not supported.
- * - 1 - DMA supported.
- */
-//@{
-#define BP_SDHC_HTCAPBLT_DMAS (22U) //!< Bit position for SDHC_HTCAPBLT_DMAS.
-#define BM_SDHC_HTCAPBLT_DMAS (0x00400000U) //!< Bit mask for SDHC_HTCAPBLT_DMAS.
-#define BS_SDHC_HTCAPBLT_DMAS (1U) //!< Bit field size in bits for SDHC_HTCAPBLT_DMAS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_HTCAPBLT_DMAS field.
-#define BR_SDHC_HTCAPBLT_DMAS (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR, BP_SDHC_HTCAPBLT_DMAS))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_HTCAPBLT, field SRS[23] (RO)
- *
- * This bit indicates whether the SDHC supports suspend / resume functionality.
- * If this bit is 0, the suspend and resume mechanism, as well as the read Wwait,
- * are not supported, and the host driver shall not issue either suspend or
- * resume commands.
- *
- * Values:
- * - 0 - Not supported.
- * - 1 - Supported.
- */
-//@{
-#define BP_SDHC_HTCAPBLT_SRS (23U) //!< Bit position for SDHC_HTCAPBLT_SRS.
-#define BM_SDHC_HTCAPBLT_SRS (0x00800000U) //!< Bit mask for SDHC_HTCAPBLT_SRS.
-#define BS_SDHC_HTCAPBLT_SRS (1U) //!< Bit field size in bits for SDHC_HTCAPBLT_SRS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_HTCAPBLT_SRS field.
-#define BR_SDHC_HTCAPBLT_SRS (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR, BP_SDHC_HTCAPBLT_SRS))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_HTCAPBLT, field VS33[24] (RO)
- *
- * This bit shall depend on the host system ability.
- *
- * Values:
- * - 0 - 3.3 V not supported.
- * - 1 - 3.3 V supported.
- */
-//@{
-#define BP_SDHC_HTCAPBLT_VS33 (24U) //!< Bit position for SDHC_HTCAPBLT_VS33.
-#define BM_SDHC_HTCAPBLT_VS33 (0x01000000U) //!< Bit mask for SDHC_HTCAPBLT_VS33.
-#define BS_SDHC_HTCAPBLT_VS33 (1U) //!< Bit field size in bits for SDHC_HTCAPBLT_VS33.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_HTCAPBLT_VS33 field.
-#define BR_SDHC_HTCAPBLT_VS33 (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR, BP_SDHC_HTCAPBLT_VS33))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SDHC_WML - Watermark Level Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SDHC_WML - Watermark Level Register (RW)
- *
- * Reset value: 0x00100010U
- *
- * Both write and read watermark levels (FIFO threshold) are configurable. There
- * value can range from 1 to 128 words. Both write and read burst lengths are
- * also configurable. There value can range from 1 to 31 words.
- */
-typedef union _hw_sdhc_wml
-{
- uint32_t U;
- struct _hw_sdhc_wml_bitfields
- {
- uint32_t RDWML : 8; //!< [7:0] Read Watermark Level
- uint32_t RESERVED0 : 8; //!< [15:8]
- uint32_t WRWML : 8; //!< [23:16] Write Watermark Level
- uint32_t RESERVED1 : 8; //!< [31:24]
- } B;
-} hw_sdhc_wml_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SDHC_WML register
- */
-//@{
-#define HW_SDHC_WML_ADDR (REGS_SDHC_BASE + 0x44U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SDHC_WML (*(__IO hw_sdhc_wml_t *) HW_SDHC_WML_ADDR)
-#define HW_SDHC_WML_RD() (HW_SDHC_WML.U)
-#define HW_SDHC_WML_WR(v) (HW_SDHC_WML.U = (v))
-#define HW_SDHC_WML_SET(v) (HW_SDHC_WML_WR(HW_SDHC_WML_RD() | (v)))
-#define HW_SDHC_WML_CLR(v) (HW_SDHC_WML_WR(HW_SDHC_WML_RD() & ~(v)))
-#define HW_SDHC_WML_TOG(v) (HW_SDHC_WML_WR(HW_SDHC_WML_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SDHC_WML bitfields
- */
-
-/*!
- * @name Register SDHC_WML, field RDWML[7:0] (RW)
- *
- * The number of words used as the watermark level (FIFO threshold) in a DMA
- * read operation. Also the number of words as a sequence of read bursts in
- * back-to-back mode. The maximum legal value for the read water mark level is 128.
- */
-//@{
-#define BP_SDHC_WML_RDWML (0U) //!< Bit position for SDHC_WML_RDWML.
-#define BM_SDHC_WML_RDWML (0x000000FFU) //!< Bit mask for SDHC_WML_RDWML.
-#define BS_SDHC_WML_RDWML (8U) //!< Bit field size in bits for SDHC_WML_RDWML.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_WML_RDWML field.
-#define BR_SDHC_WML_RDWML (HW_SDHC_WML.B.RDWML)
-#endif
-
-//! @brief Format value for bitfield SDHC_WML_RDWML.
-#define BF_SDHC_WML_RDWML(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_WML_RDWML), uint32_t) & BM_SDHC_WML_RDWML)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RDWML field to a new value.
-#define BW_SDHC_WML_RDWML(v) (HW_SDHC_WML_WR((HW_SDHC_WML_RD() & ~BM_SDHC_WML_RDWML) | BF_SDHC_WML_RDWML(v)))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_WML, field WRWML[23:16] (RW)
- *
- * The number of words used as the watermark level (FIFO threshold) in a DMA
- * write operation. Also the number of words as a sequence of write bursts in
- * back-to-back mode. The maximum legal value for the write watermark level is 128.
- */
-//@{
-#define BP_SDHC_WML_WRWML (16U) //!< Bit position for SDHC_WML_WRWML.
-#define BM_SDHC_WML_WRWML (0x00FF0000U) //!< Bit mask for SDHC_WML_WRWML.
-#define BS_SDHC_WML_WRWML (8U) //!< Bit field size in bits for SDHC_WML_WRWML.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_WML_WRWML field.
-#define BR_SDHC_WML_WRWML (HW_SDHC_WML.B.WRWML)
-#endif
-
-//! @brief Format value for bitfield SDHC_WML_WRWML.
-#define BF_SDHC_WML_WRWML(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_WML_WRWML), uint32_t) & BM_SDHC_WML_WRWML)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WRWML field to a new value.
-#define BW_SDHC_WML_WRWML(v) (HW_SDHC_WML_WR((HW_SDHC_WML_RD() & ~BM_SDHC_WML_WRWML) | BF_SDHC_WML_WRWML(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SDHC_FEVT - Force Event register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SDHC_FEVT - Force Event register (WO)
- *
- * Reset value: 0x00000000U
- *
- * The Force Event (FEVT) register is not a physically implemented register.
- * Rather, it is an address at which the Interrupt Status register can be written if
- * the corresponding bit of the Interrupt Status Enable register is set. This
- * register is a write only register and writing 0 to it has no effect. Writing 1
- * to this register actually sets the corresponding bit of Interrupt Status
- * register. A read from this register always results in 0's. To change the
- * corresponding status bits in the interrupt status register, make sure to set
- * SYSCTL[IPGEN] so that bus clock is always active. Forcing a card interrupt will generate a
- * short pulse on the DAT[1] line, and the driver may treat this interrupt as a
- * normal interrupt. The interrupt service routine may skip polling the card
- * interrupt factor as the interrupt is selfcleared.
- */
-typedef union _hw_sdhc_fevt
-{
- uint32_t U;
- struct _hw_sdhc_fevt_bitfields
- {
- uint32_t AC12NE : 1; //!< [0] Force Event Auto Command 12 Not Executed
- uint32_t AC12TOE : 1; //!< [1] Force Event Auto Command 12 Time Out
- //! Error
- uint32_t AC12CE : 1; //!< [2] Force Event Auto Command 12 CRC Error
- uint32_t AC12EBE : 1; //!< [3] Force Event Auto Command 12 End Bit
- //! Error
- uint32_t AC12IE : 1; //!< [4] Force Event Auto Command 12 Index Error
- uint32_t RESERVED0 : 2; //!< [6:5]
- uint32_t CNIBAC12E : 1; //!< [7] Force Event Command Not Executed By
- //! Auto Command 12 Error
- uint32_t RESERVED1 : 8; //!< [15:8]
- uint32_t CTOE : 1; //!< [16] Force Event Command Time Out Error
- uint32_t CCE : 1; //!< [17] Force Event Command CRC Error
- uint32_t CEBE : 1; //!< [18] Force Event Command End Bit Error
- uint32_t CIE : 1; //!< [19] Force Event Command Index Error
- uint32_t DTOE : 1; //!< [20] Force Event Data Time Out Error
- uint32_t DCE : 1; //!< [21] Force Event Data CRC Error
- uint32_t DEBE : 1; //!< [22] Force Event Data End Bit Error
- uint32_t RESERVED2 : 1; //!< [23]
- uint32_t AC12E : 1; //!< [24] Force Event Auto Command 12 Error
- uint32_t RESERVED3 : 3; //!< [27:25]
- uint32_t DMAE : 1; //!< [28] Force Event DMA Error
- uint32_t RESERVED4 : 2; //!< [30:29]
- uint32_t CINT : 1; //!< [31] Force Event Card Interrupt
- } B;
-} hw_sdhc_fevt_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SDHC_FEVT register
- */
-//@{
-#define HW_SDHC_FEVT_ADDR (REGS_SDHC_BASE + 0x50U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SDHC_FEVT (*(__O hw_sdhc_fevt_t *) HW_SDHC_FEVT_ADDR)
-#define HW_SDHC_FEVT_RD() (HW_SDHC_FEVT.U)
-#define HW_SDHC_FEVT_WR(v) (HW_SDHC_FEVT.U = (v))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SDHC_FEVT bitfields
- */
-
-/*!
- * @name Register SDHC_FEVT, field AC12NE[0] (WORZ)
- *
- * Forces AC12ERR[AC12NE] to be set.
- */
-//@{
-#define BP_SDHC_FEVT_AC12NE (0U) //!< Bit position for SDHC_FEVT_AC12NE.
-#define BM_SDHC_FEVT_AC12NE (0x00000001U) //!< Bit mask for SDHC_FEVT_AC12NE.
-#define BS_SDHC_FEVT_AC12NE (1U) //!< Bit field size in bits for SDHC_FEVT_AC12NE.
-
-//! @brief Format value for bitfield SDHC_FEVT_AC12NE.
-#define BF_SDHC_FEVT_AC12NE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12NE), uint32_t) & BM_SDHC_FEVT_AC12NE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the AC12NE field to a new value.
-#define BW_SDHC_FEVT_AC12NE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12NE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_FEVT, field AC12TOE[1] (WORZ)
- *
- * Forces AC12ERR[AC12TOE] to be set.
- */
-//@{
-#define BP_SDHC_FEVT_AC12TOE (1U) //!< Bit position for SDHC_FEVT_AC12TOE.
-#define BM_SDHC_FEVT_AC12TOE (0x00000002U) //!< Bit mask for SDHC_FEVT_AC12TOE.
-#define BS_SDHC_FEVT_AC12TOE (1U) //!< Bit field size in bits for SDHC_FEVT_AC12TOE.
-
-//! @brief Format value for bitfield SDHC_FEVT_AC12TOE.
-#define BF_SDHC_FEVT_AC12TOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12TOE), uint32_t) & BM_SDHC_FEVT_AC12TOE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the AC12TOE field to a new value.
-#define BW_SDHC_FEVT_AC12TOE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12TOE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_FEVT, field AC12CE[2] (WORZ)
- *
- * Forces AC12ERR[AC12CE] to be set.
- */
-//@{
-#define BP_SDHC_FEVT_AC12CE (2U) //!< Bit position for SDHC_FEVT_AC12CE.
-#define BM_SDHC_FEVT_AC12CE (0x00000004U) //!< Bit mask for SDHC_FEVT_AC12CE.
-#define BS_SDHC_FEVT_AC12CE (1U) //!< Bit field size in bits for SDHC_FEVT_AC12CE.
-
-//! @brief Format value for bitfield SDHC_FEVT_AC12CE.
-#define BF_SDHC_FEVT_AC12CE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12CE), uint32_t) & BM_SDHC_FEVT_AC12CE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the AC12CE field to a new value.
-#define BW_SDHC_FEVT_AC12CE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12CE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_FEVT, field AC12EBE[3] (WORZ)
- *
- * Forces AC12ERR[AC12EBE] to be set.
- */
-//@{
-#define BP_SDHC_FEVT_AC12EBE (3U) //!< Bit position for SDHC_FEVT_AC12EBE.
-#define BM_SDHC_FEVT_AC12EBE (0x00000008U) //!< Bit mask for SDHC_FEVT_AC12EBE.
-#define BS_SDHC_FEVT_AC12EBE (1U) //!< Bit field size in bits for SDHC_FEVT_AC12EBE.
-
-//! @brief Format value for bitfield SDHC_FEVT_AC12EBE.
-#define BF_SDHC_FEVT_AC12EBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12EBE), uint32_t) & BM_SDHC_FEVT_AC12EBE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the AC12EBE field to a new value.
-#define BW_SDHC_FEVT_AC12EBE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12EBE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_FEVT, field AC12IE[4] (WORZ)
- *
- * Forces AC12ERR[AC12IE] to be set.
- */
-//@{
-#define BP_SDHC_FEVT_AC12IE (4U) //!< Bit position for SDHC_FEVT_AC12IE.
-#define BM_SDHC_FEVT_AC12IE (0x00000010U) //!< Bit mask for SDHC_FEVT_AC12IE.
-#define BS_SDHC_FEVT_AC12IE (1U) //!< Bit field size in bits for SDHC_FEVT_AC12IE.
-
-//! @brief Format value for bitfield SDHC_FEVT_AC12IE.
-#define BF_SDHC_FEVT_AC12IE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12IE), uint32_t) & BM_SDHC_FEVT_AC12IE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the AC12IE field to a new value.
-#define BW_SDHC_FEVT_AC12IE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12IE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_FEVT, field CNIBAC12E[7] (WORZ)
- *
- * Forces AC12ERR[CNIBAC12E] to be set.
- */
-//@{
-#define BP_SDHC_FEVT_CNIBAC12E (7U) //!< Bit position for SDHC_FEVT_CNIBAC12E.
-#define BM_SDHC_FEVT_CNIBAC12E (0x00000080U) //!< Bit mask for SDHC_FEVT_CNIBAC12E.
-#define BS_SDHC_FEVT_CNIBAC12E (1U) //!< Bit field size in bits for SDHC_FEVT_CNIBAC12E.
-
-//! @brief Format value for bitfield SDHC_FEVT_CNIBAC12E.
-#define BF_SDHC_FEVT_CNIBAC12E(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CNIBAC12E), uint32_t) & BM_SDHC_FEVT_CNIBAC12E)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CNIBAC12E field to a new value.
-#define BW_SDHC_FEVT_CNIBAC12E(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CNIBAC12E) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_FEVT, field CTOE[16] (WORZ)
- *
- * Forces IRQSTAT[CTOE] to be set.
- */
-//@{
-#define BP_SDHC_FEVT_CTOE (16U) //!< Bit position for SDHC_FEVT_CTOE.
-#define BM_SDHC_FEVT_CTOE (0x00010000U) //!< Bit mask for SDHC_FEVT_CTOE.
-#define BS_SDHC_FEVT_CTOE (1U) //!< Bit field size in bits for SDHC_FEVT_CTOE.
-
-//! @brief Format value for bitfield SDHC_FEVT_CTOE.
-#define BF_SDHC_FEVT_CTOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CTOE), uint32_t) & BM_SDHC_FEVT_CTOE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CTOE field to a new value.
-#define BW_SDHC_FEVT_CTOE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CTOE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_FEVT, field CCE[17] (WORZ)
- *
- * Forces IRQSTAT[CCE] to be set.
- */
-//@{
-#define BP_SDHC_FEVT_CCE (17U) //!< Bit position for SDHC_FEVT_CCE.
-#define BM_SDHC_FEVT_CCE (0x00020000U) //!< Bit mask for SDHC_FEVT_CCE.
-#define BS_SDHC_FEVT_CCE (1U) //!< Bit field size in bits for SDHC_FEVT_CCE.
-
-//! @brief Format value for bitfield SDHC_FEVT_CCE.
-#define BF_SDHC_FEVT_CCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CCE), uint32_t) & BM_SDHC_FEVT_CCE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CCE field to a new value.
-#define BW_SDHC_FEVT_CCE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CCE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_FEVT, field CEBE[18] (WORZ)
- *
- * Forces IRQSTAT[CEBE] to be set.
- */
-//@{
-#define BP_SDHC_FEVT_CEBE (18U) //!< Bit position for SDHC_FEVT_CEBE.
-#define BM_SDHC_FEVT_CEBE (0x00040000U) //!< Bit mask for SDHC_FEVT_CEBE.
-#define BS_SDHC_FEVT_CEBE (1U) //!< Bit field size in bits for SDHC_FEVT_CEBE.
-
-//! @brief Format value for bitfield SDHC_FEVT_CEBE.
-#define BF_SDHC_FEVT_CEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CEBE), uint32_t) & BM_SDHC_FEVT_CEBE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CEBE field to a new value.
-#define BW_SDHC_FEVT_CEBE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CEBE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_FEVT, field CIE[19] (WORZ)
- *
- * Forces IRQSTAT[CCE] to be set.
- */
-//@{
-#define BP_SDHC_FEVT_CIE (19U) //!< Bit position for SDHC_FEVT_CIE.
-#define BM_SDHC_FEVT_CIE (0x00080000U) //!< Bit mask for SDHC_FEVT_CIE.
-#define BS_SDHC_FEVT_CIE (1U) //!< Bit field size in bits for SDHC_FEVT_CIE.
-
-//! @brief Format value for bitfield SDHC_FEVT_CIE.
-#define BF_SDHC_FEVT_CIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CIE), uint32_t) & BM_SDHC_FEVT_CIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CIE field to a new value.
-#define BW_SDHC_FEVT_CIE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_FEVT, field DTOE[20] (WORZ)
- *
- * Forces IRQSTAT[DTOE] to be set.
- */
-//@{
-#define BP_SDHC_FEVT_DTOE (20U) //!< Bit position for SDHC_FEVT_DTOE.
-#define BM_SDHC_FEVT_DTOE (0x00100000U) //!< Bit mask for SDHC_FEVT_DTOE.
-#define BS_SDHC_FEVT_DTOE (1U) //!< Bit field size in bits for SDHC_FEVT_DTOE.
-
-//! @brief Format value for bitfield SDHC_FEVT_DTOE.
-#define BF_SDHC_FEVT_DTOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_DTOE), uint32_t) & BM_SDHC_FEVT_DTOE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DTOE field to a new value.
-#define BW_SDHC_FEVT_DTOE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_DTOE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_FEVT, field DCE[21] (WORZ)
- *
- * Forces IRQSTAT[DCE] to be set.
- */
-//@{
-#define BP_SDHC_FEVT_DCE (21U) //!< Bit position for SDHC_FEVT_DCE.
-#define BM_SDHC_FEVT_DCE (0x00200000U) //!< Bit mask for SDHC_FEVT_DCE.
-#define BS_SDHC_FEVT_DCE (1U) //!< Bit field size in bits for SDHC_FEVT_DCE.
-
-//! @brief Format value for bitfield SDHC_FEVT_DCE.
-#define BF_SDHC_FEVT_DCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_DCE), uint32_t) & BM_SDHC_FEVT_DCE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DCE field to a new value.
-#define BW_SDHC_FEVT_DCE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_DCE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_FEVT, field DEBE[22] (WORZ)
- *
- * Forces IRQSTAT[DEBE] to be set.
- */
-//@{
-#define BP_SDHC_FEVT_DEBE (22U) //!< Bit position for SDHC_FEVT_DEBE.
-#define BM_SDHC_FEVT_DEBE (0x00400000U) //!< Bit mask for SDHC_FEVT_DEBE.
-#define BS_SDHC_FEVT_DEBE (1U) //!< Bit field size in bits for SDHC_FEVT_DEBE.
-
-//! @brief Format value for bitfield SDHC_FEVT_DEBE.
-#define BF_SDHC_FEVT_DEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_DEBE), uint32_t) & BM_SDHC_FEVT_DEBE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DEBE field to a new value.
-#define BW_SDHC_FEVT_DEBE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_DEBE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_FEVT, field AC12E[24] (WORZ)
- *
- * Forces IRQSTAT[AC12E] to be set.
- */
-//@{
-#define BP_SDHC_FEVT_AC12E (24U) //!< Bit position for SDHC_FEVT_AC12E.
-#define BM_SDHC_FEVT_AC12E (0x01000000U) //!< Bit mask for SDHC_FEVT_AC12E.
-#define BS_SDHC_FEVT_AC12E (1U) //!< Bit field size in bits for SDHC_FEVT_AC12E.
-
-//! @brief Format value for bitfield SDHC_FEVT_AC12E.
-#define BF_SDHC_FEVT_AC12E(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12E), uint32_t) & BM_SDHC_FEVT_AC12E)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the AC12E field to a new value.
-#define BW_SDHC_FEVT_AC12E(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12E) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_FEVT, field DMAE[28] (WORZ)
- *
- * Forces the DMAE bit of Interrupt Status Register to be set.
- */
-//@{
-#define BP_SDHC_FEVT_DMAE (28U) //!< Bit position for SDHC_FEVT_DMAE.
-#define BM_SDHC_FEVT_DMAE (0x10000000U) //!< Bit mask for SDHC_FEVT_DMAE.
-#define BS_SDHC_FEVT_DMAE (1U) //!< Bit field size in bits for SDHC_FEVT_DMAE.
-
-//! @brief Format value for bitfield SDHC_FEVT_DMAE.
-#define BF_SDHC_FEVT_DMAE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_DMAE), uint32_t) & BM_SDHC_FEVT_DMAE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DMAE field to a new value.
-#define BW_SDHC_FEVT_DMAE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_DMAE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_FEVT, field CINT[31] (WORZ)
- *
- * Writing 1 to this bit generates a short low-level pulse on the internal
- * DAT[1] line, as if a self-clearing interrupt was received from the external card.
- * If enabled, the CINT bit will be set and the interrupt service routine may
- * treat this interrupt as a normal interrupt from the external card.
- */
-//@{
-#define BP_SDHC_FEVT_CINT (31U) //!< Bit position for SDHC_FEVT_CINT.
-#define BM_SDHC_FEVT_CINT (0x80000000U) //!< Bit mask for SDHC_FEVT_CINT.
-#define BS_SDHC_FEVT_CINT (1U) //!< Bit field size in bits for SDHC_FEVT_CINT.
-
-//! @brief Format value for bitfield SDHC_FEVT_CINT.
-#define BF_SDHC_FEVT_CINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CINT), uint32_t) & BM_SDHC_FEVT_CINT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CINT field to a new value.
-#define BW_SDHC_FEVT_CINT(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CINT) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SDHC_ADMAES - ADMA Error Status register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SDHC_ADMAES - ADMA Error Status register (RO)
- *
- * Reset value: 0x00000000U
- *
- * When an ADMA error interrupt has occurred, the ADMA Error States field in
- * this register holds the ADMA state and the ADMA System Address register holds the
- * address around the error descriptor. For recovering from this error, the host
- * driver requires the ADMA state to identify the error descriptor address as
- * follows: ST_STOP: Previous location set in the ADMA System Address register is
- * the error descriptor address. ST_FDS: Current location set in the ADMA System
- * Address register is the error descriptor address. ST_CADR: This state is never
- * set because it only increments the descriptor pointer and doesn't generate an
- * ADMA error. ST_TFR: Previous location set in the ADMA System Address register
- * is the error descriptor address. In case of a write operation, the host driver
- * must use the ACMD22 to get the number of the written block, rather than using
- * this information, because unwritten data may exist in the host controller.
- * The host controller generates the ADMA error interrupt when it detects invalid
- * descriptor data (valid = 0) in the ST_FDS state. The host driver can
- * distinguish this error by reading the valid bit of the error descriptor. ADMA Error
- * State coding D01-D00 ADMA Error State when error has occurred Contents of ADMA
- * System Address register 00 ST_STOP (Stop DMA) Holds the address of the next
- * executable descriptor command 01 ST_FDS (fetch descriptor) Holds the valid
- * descriptor address 10 ST_CADR (change address) No ADMA error is generated 11 ST_TFR
- * (Transfer Data) Holds the address of the next executable descriptor command
- */
-typedef union _hw_sdhc_admaes
-{
- uint32_t U;
- struct _hw_sdhc_admaes_bitfields
- {
- uint32_t ADMAES : 2; //!< [1:0] ADMA Error State (When ADMA Error Is
- //! Occurred.)
- uint32_t ADMALME : 1; //!< [2] ADMA Length Mismatch Error
- uint32_t ADMADCE : 1; //!< [3] ADMA Descriptor Error
- uint32_t RESERVED0 : 28; //!< [31:4]
- } B;
-} hw_sdhc_admaes_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SDHC_ADMAES register
- */
-//@{
-#define HW_SDHC_ADMAES_ADDR (REGS_SDHC_BASE + 0x54U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SDHC_ADMAES (*(__I hw_sdhc_admaes_t *) HW_SDHC_ADMAES_ADDR)
-#define HW_SDHC_ADMAES_RD() (HW_SDHC_ADMAES.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual SDHC_ADMAES bitfields
- */
-
-/*!
- * @name Register SDHC_ADMAES, field ADMAES[1:0] (RO)
- *
- * Indicates the state of the ADMA when an error has occurred during an ADMA
- * data transfer.
- */
-//@{
-#define BP_SDHC_ADMAES_ADMAES (0U) //!< Bit position for SDHC_ADMAES_ADMAES.
-#define BM_SDHC_ADMAES_ADMAES (0x00000003U) //!< Bit mask for SDHC_ADMAES_ADMAES.
-#define BS_SDHC_ADMAES_ADMAES (2U) //!< Bit field size in bits for SDHC_ADMAES_ADMAES.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_ADMAES_ADMAES field.
-#define BR_SDHC_ADMAES_ADMAES (HW_SDHC_ADMAES.B.ADMAES)
-#endif
-//@}
-
-/*!
- * @name Register SDHC_ADMAES, field ADMALME[2] (RO)
- *
- * This error occurs in the following 2 cases: While the block count enable is
- * being set, the total data length specified by the descriptor table is different
- * from that specified by the block count and block length. Total data length
- * can not be divided by the block length.
- *
- * Values:
- * - 0 - No error.
- * - 1 - Error.
- */
-//@{
-#define BP_SDHC_ADMAES_ADMALME (2U) //!< Bit position for SDHC_ADMAES_ADMALME.
-#define BM_SDHC_ADMAES_ADMALME (0x00000004U) //!< Bit mask for SDHC_ADMAES_ADMALME.
-#define BS_SDHC_ADMAES_ADMALME (1U) //!< Bit field size in bits for SDHC_ADMAES_ADMALME.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_ADMAES_ADMALME field.
-#define BR_SDHC_ADMAES_ADMALME (BITBAND_ACCESS32(HW_SDHC_ADMAES_ADDR, BP_SDHC_ADMAES_ADMALME))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_ADMAES, field ADMADCE[3] (RO)
- *
- * This error occurs when an invalid descriptor is fetched by ADMA.
- *
- * Values:
- * - 0 - No error.
- * - 1 - Error.
- */
-//@{
-#define BP_SDHC_ADMAES_ADMADCE (3U) //!< Bit position for SDHC_ADMAES_ADMADCE.
-#define BM_SDHC_ADMAES_ADMADCE (0x00000008U) //!< Bit mask for SDHC_ADMAES_ADMADCE.
-#define BS_SDHC_ADMAES_ADMADCE (1U) //!< Bit field size in bits for SDHC_ADMAES_ADMADCE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_ADMAES_ADMADCE field.
-#define BR_SDHC_ADMAES_ADMADCE (BITBAND_ACCESS32(HW_SDHC_ADMAES_ADDR, BP_SDHC_ADMAES_ADMADCE))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SDHC_ADSADDR - ADMA System Addressregister
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SDHC_ADSADDR - ADMA System Addressregister (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register contains the physical system memory address used for ADMA
- * transfers.
- */
-typedef union _hw_sdhc_adsaddr
-{
- uint32_t U;
- struct _hw_sdhc_adsaddr_bitfields
- {
- uint32_t RESERVED0 : 2; //!< [1:0]
- uint32_t ADSADDR : 30; //!< [31:2] ADMA System Address
- } B;
-} hw_sdhc_adsaddr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SDHC_ADSADDR register
- */
-//@{
-#define HW_SDHC_ADSADDR_ADDR (REGS_SDHC_BASE + 0x58U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SDHC_ADSADDR (*(__IO hw_sdhc_adsaddr_t *) HW_SDHC_ADSADDR_ADDR)
-#define HW_SDHC_ADSADDR_RD() (HW_SDHC_ADSADDR.U)
-#define HW_SDHC_ADSADDR_WR(v) (HW_SDHC_ADSADDR.U = (v))
-#define HW_SDHC_ADSADDR_SET(v) (HW_SDHC_ADSADDR_WR(HW_SDHC_ADSADDR_RD() | (v)))
-#define HW_SDHC_ADSADDR_CLR(v) (HW_SDHC_ADSADDR_WR(HW_SDHC_ADSADDR_RD() & ~(v)))
-#define HW_SDHC_ADSADDR_TOG(v) (HW_SDHC_ADSADDR_WR(HW_SDHC_ADSADDR_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SDHC_ADSADDR bitfields
- */
-
-/*!
- * @name Register SDHC_ADSADDR, field ADSADDR[31:2] (RW)
- *
- * Holds the word address of the executing command in the descriptor table. At
- * the start of ADMA, the host driver shall set the start address of the
- * Descriptor table. The ADMA engine increments this register address whenever fetching a
- * descriptor command. When the ADMA is stopped at the block gap, this register
- * indicates the address of the next executable descriptor command. When the ADMA
- * error interrupt is generated, this register shall hold the valid descriptor
- * address depending on the ADMA state. The lower 2 bits of this register is tied
- * to '0' so the ADMA address is always word-aligned. Because this register
- * supports dynamic address reflecting, when TC bit is set, it automatically alters the
- * value of internal address counter, so SW cannot change this register when TC
- * bit is set.
- */
-//@{
-#define BP_SDHC_ADSADDR_ADSADDR (2U) //!< Bit position for SDHC_ADSADDR_ADSADDR.
-#define BM_SDHC_ADSADDR_ADSADDR (0xFFFFFFFCU) //!< Bit mask for SDHC_ADSADDR_ADSADDR.
-#define BS_SDHC_ADSADDR_ADSADDR (30U) //!< Bit field size in bits for SDHC_ADSADDR_ADSADDR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_ADSADDR_ADSADDR field.
-#define BR_SDHC_ADSADDR_ADSADDR (HW_SDHC_ADSADDR.B.ADSADDR)
-#endif
-
-//! @brief Format value for bitfield SDHC_ADSADDR_ADSADDR.
-#define BF_SDHC_ADSADDR_ADSADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_ADSADDR_ADSADDR), uint32_t) & BM_SDHC_ADSADDR_ADSADDR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ADSADDR field to a new value.
-#define BW_SDHC_ADSADDR_ADSADDR(v) (HW_SDHC_ADSADDR_WR((HW_SDHC_ADSADDR_RD() & ~BM_SDHC_ADSADDR_ADSADDR) | BF_SDHC_ADSADDR_ADSADDR(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SDHC_VENDOR - Vendor Specific register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SDHC_VENDOR - Vendor Specific register (RW)
- *
- * Reset value: 0x00000001U
- *
- * This register contains the vendor-specific control/status register.
- */
-typedef union _hw_sdhc_vendor
-{
- uint32_t U;
- struct _hw_sdhc_vendor_bitfields
- {
- uint32_t EXTDMAEN : 1; //!< [0] External DMA Request Enable
- uint32_t EXBLKNU : 1; //!< [1] Exact Block Number Block Read Enable
- //! For SDIO CMD53
- uint32_t RESERVED0 : 14; //!< [15:2]
- uint32_t INTSTVAL : 8; //!< [23:16] Internal State Value
- uint32_t RESERVED1 : 8; //!< [31:24]
- } B;
-} hw_sdhc_vendor_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SDHC_VENDOR register
- */
-//@{
-#define HW_SDHC_VENDOR_ADDR (REGS_SDHC_BASE + 0xC0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SDHC_VENDOR (*(__IO hw_sdhc_vendor_t *) HW_SDHC_VENDOR_ADDR)
-#define HW_SDHC_VENDOR_RD() (HW_SDHC_VENDOR.U)
-#define HW_SDHC_VENDOR_WR(v) (HW_SDHC_VENDOR.U = (v))
-#define HW_SDHC_VENDOR_SET(v) (HW_SDHC_VENDOR_WR(HW_SDHC_VENDOR_RD() | (v)))
-#define HW_SDHC_VENDOR_CLR(v) (HW_SDHC_VENDOR_WR(HW_SDHC_VENDOR_RD() & ~(v)))
-#define HW_SDHC_VENDOR_TOG(v) (HW_SDHC_VENDOR_WR(HW_SDHC_VENDOR_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SDHC_VENDOR bitfields
- */
-
-/*!
- * @name Register SDHC_VENDOR, field EXTDMAEN[0] (RW)
- *
- * Enables the request to external DMA. When the internal DMA (either simple DMA
- * or advanced DMA) is not in use, and this bit is set, SDHC will send out DMA
- * request when the internal buffer is ready. This bit is particularly useful when
- * transferring data by CPU polling mode, and it is not allowed to send out the
- * external DMA request. By default, this bit is set.
- *
- * Values:
- * - 0 - In any scenario, SDHC does not send out the external DMA request.
- * - 1 - When internal DMA is not active, the external DMA request will be sent
- * out.
- */
-//@{
-#define BP_SDHC_VENDOR_EXTDMAEN (0U) //!< Bit position for SDHC_VENDOR_EXTDMAEN.
-#define BM_SDHC_VENDOR_EXTDMAEN (0x00000001U) //!< Bit mask for SDHC_VENDOR_EXTDMAEN.
-#define BS_SDHC_VENDOR_EXTDMAEN (1U) //!< Bit field size in bits for SDHC_VENDOR_EXTDMAEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_VENDOR_EXTDMAEN field.
-#define BR_SDHC_VENDOR_EXTDMAEN (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR, BP_SDHC_VENDOR_EXTDMAEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_VENDOR_EXTDMAEN.
-#define BF_SDHC_VENDOR_EXTDMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_VENDOR_EXTDMAEN), uint32_t) & BM_SDHC_VENDOR_EXTDMAEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EXTDMAEN field to a new value.
-#define BW_SDHC_VENDOR_EXTDMAEN(v) (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR, BP_SDHC_VENDOR_EXTDMAEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_VENDOR, field EXBLKNU[1] (RW)
- *
- * This bit must be set before S/W issues CMD53 multi-block read with exact
- * block number. This bit must not be set if the CMD53 multi-block read is not exact
- * block number.
- *
- * Values:
- * - 0 - None exact block read.
- * - 1 - Exact block read for SDIO CMD53.
- */
-//@{
-#define BP_SDHC_VENDOR_EXBLKNU (1U) //!< Bit position for SDHC_VENDOR_EXBLKNU.
-#define BM_SDHC_VENDOR_EXBLKNU (0x00000002U) //!< Bit mask for SDHC_VENDOR_EXBLKNU.
-#define BS_SDHC_VENDOR_EXBLKNU (1U) //!< Bit field size in bits for SDHC_VENDOR_EXBLKNU.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_VENDOR_EXBLKNU field.
-#define BR_SDHC_VENDOR_EXBLKNU (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR, BP_SDHC_VENDOR_EXBLKNU))
-#endif
-
-//! @brief Format value for bitfield SDHC_VENDOR_EXBLKNU.
-#define BF_SDHC_VENDOR_EXBLKNU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_VENDOR_EXBLKNU), uint32_t) & BM_SDHC_VENDOR_EXBLKNU)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EXBLKNU field to a new value.
-#define BW_SDHC_VENDOR_EXBLKNU(v) (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR, BP_SDHC_VENDOR_EXBLKNU) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_VENDOR, field INTSTVAL[23:16] (RO)
- *
- * Internal state value, reflecting the corresponding state value selected by
- * Debug Select field. This field is read-only and write to this field does not
- * have effect.
- */
-//@{
-#define BP_SDHC_VENDOR_INTSTVAL (16U) //!< Bit position for SDHC_VENDOR_INTSTVAL.
-#define BM_SDHC_VENDOR_INTSTVAL (0x00FF0000U) //!< Bit mask for SDHC_VENDOR_INTSTVAL.
-#define BS_SDHC_VENDOR_INTSTVAL (8U) //!< Bit field size in bits for SDHC_VENDOR_INTSTVAL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_VENDOR_INTSTVAL field.
-#define BR_SDHC_VENDOR_INTSTVAL (HW_SDHC_VENDOR.B.INTSTVAL)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SDHC_MMCBOOT - MMC Boot register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SDHC_MMCBOOT - MMC Boot register (RW)
- *
- * Reset value: 0x00000000U
- *
- * This register contains the MMC fast boot control register.
- */
-typedef union _hw_sdhc_mmcboot
-{
- uint32_t U;
- struct _hw_sdhc_mmcboot_bitfields
- {
- uint32_t DTOCVACK : 4; //!< [3:0] Boot ACK Time Out Counter Value
- uint32_t BOOTACK : 1; //!< [4] Boot Ack Mode Select
- uint32_t BOOTMODE : 1; //!< [5] Boot Mode Select
- uint32_t BOOTEN : 1; //!< [6] Boot Mode Enable
- uint32_t AUTOSABGEN : 1; //!< [7]
- uint32_t RESERVED0 : 8; //!< [15:8]
- uint32_t BOOTBLKCNT : 16; //!< [31:16]
- } B;
-} hw_sdhc_mmcboot_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SDHC_MMCBOOT register
- */
-//@{
-#define HW_SDHC_MMCBOOT_ADDR (REGS_SDHC_BASE + 0xC4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SDHC_MMCBOOT (*(__IO hw_sdhc_mmcboot_t *) HW_SDHC_MMCBOOT_ADDR)
-#define HW_SDHC_MMCBOOT_RD() (HW_SDHC_MMCBOOT.U)
-#define HW_SDHC_MMCBOOT_WR(v) (HW_SDHC_MMCBOOT.U = (v))
-#define HW_SDHC_MMCBOOT_SET(v) (HW_SDHC_MMCBOOT_WR(HW_SDHC_MMCBOOT_RD() | (v)))
-#define HW_SDHC_MMCBOOT_CLR(v) (HW_SDHC_MMCBOOT_WR(HW_SDHC_MMCBOOT_RD() & ~(v)))
-#define HW_SDHC_MMCBOOT_TOG(v) (HW_SDHC_MMCBOOT_WR(HW_SDHC_MMCBOOT_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SDHC_MMCBOOT bitfields
- */
-
-/*!
- * @name Register SDHC_MMCBOOT, field DTOCVACK[3:0] (RW)
- *
- * Values:
- * - 0000 - SDCLK x 2^8
- * - 0001 - SDCLK x 2^9
- * - 0010 - SDCLK x 2^10
- * - 0011 - SDCLK x 2^11
- * - 0100 - SDCLK x 2^12
- * - 0101 - SDCLK x 2^13
- * - 0110 - SDCLK x 2^14
- * - 0111 - SDCLK x 2^15
- * - 1110 - SDCLK x 2^22
- * - 1111 - Reserved
- */
-//@{
-#define BP_SDHC_MMCBOOT_DTOCVACK (0U) //!< Bit position for SDHC_MMCBOOT_DTOCVACK.
-#define BM_SDHC_MMCBOOT_DTOCVACK (0x0000000FU) //!< Bit mask for SDHC_MMCBOOT_DTOCVACK.
-#define BS_SDHC_MMCBOOT_DTOCVACK (4U) //!< Bit field size in bits for SDHC_MMCBOOT_DTOCVACK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_MMCBOOT_DTOCVACK field.
-#define BR_SDHC_MMCBOOT_DTOCVACK (HW_SDHC_MMCBOOT.B.DTOCVACK)
-#endif
-
-//! @brief Format value for bitfield SDHC_MMCBOOT_DTOCVACK.
-#define BF_SDHC_MMCBOOT_DTOCVACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_DTOCVACK), uint32_t) & BM_SDHC_MMCBOOT_DTOCVACK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DTOCVACK field to a new value.
-#define BW_SDHC_MMCBOOT_DTOCVACK(v) (HW_SDHC_MMCBOOT_WR((HW_SDHC_MMCBOOT_RD() & ~BM_SDHC_MMCBOOT_DTOCVACK) | BF_SDHC_MMCBOOT_DTOCVACK(v)))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_MMCBOOT, field BOOTACK[4] (RW)
- *
- * Values:
- * - 0 - No ack.
- * - 1 - Ack.
- */
-//@{
-#define BP_SDHC_MMCBOOT_BOOTACK (4U) //!< Bit position for SDHC_MMCBOOT_BOOTACK.
-#define BM_SDHC_MMCBOOT_BOOTACK (0x00000010U) //!< Bit mask for SDHC_MMCBOOT_BOOTACK.
-#define BS_SDHC_MMCBOOT_BOOTACK (1U) //!< Bit field size in bits for SDHC_MMCBOOT_BOOTACK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_MMCBOOT_BOOTACK field.
-#define BR_SDHC_MMCBOOT_BOOTACK (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTACK))
-#endif
-
-//! @brief Format value for bitfield SDHC_MMCBOOT_BOOTACK.
-#define BF_SDHC_MMCBOOT_BOOTACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_BOOTACK), uint32_t) & BM_SDHC_MMCBOOT_BOOTACK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BOOTACK field to a new value.
-#define BW_SDHC_MMCBOOT_BOOTACK(v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTACK) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_MMCBOOT, field BOOTMODE[5] (RW)
- *
- * Values:
- * - 0 - Normal boot.
- * - 1 - Alternative boot.
- */
-//@{
-#define BP_SDHC_MMCBOOT_BOOTMODE (5U) //!< Bit position for SDHC_MMCBOOT_BOOTMODE.
-#define BM_SDHC_MMCBOOT_BOOTMODE (0x00000020U) //!< Bit mask for SDHC_MMCBOOT_BOOTMODE.
-#define BS_SDHC_MMCBOOT_BOOTMODE (1U) //!< Bit field size in bits for SDHC_MMCBOOT_BOOTMODE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_MMCBOOT_BOOTMODE field.
-#define BR_SDHC_MMCBOOT_BOOTMODE (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTMODE))
-#endif
-
-//! @brief Format value for bitfield SDHC_MMCBOOT_BOOTMODE.
-#define BF_SDHC_MMCBOOT_BOOTMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_BOOTMODE), uint32_t) & BM_SDHC_MMCBOOT_BOOTMODE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BOOTMODE field to a new value.
-#define BW_SDHC_MMCBOOT_BOOTMODE(v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTMODE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_MMCBOOT, field BOOTEN[6] (RW)
- *
- * Values:
- * - 0 - Fast boot disable.
- * - 1 - Fast boot enable.
- */
-//@{
-#define BP_SDHC_MMCBOOT_BOOTEN (6U) //!< Bit position for SDHC_MMCBOOT_BOOTEN.
-#define BM_SDHC_MMCBOOT_BOOTEN (0x00000040U) //!< Bit mask for SDHC_MMCBOOT_BOOTEN.
-#define BS_SDHC_MMCBOOT_BOOTEN (1U) //!< Bit field size in bits for SDHC_MMCBOOT_BOOTEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_MMCBOOT_BOOTEN field.
-#define BR_SDHC_MMCBOOT_BOOTEN (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_MMCBOOT_BOOTEN.
-#define BF_SDHC_MMCBOOT_BOOTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_BOOTEN), uint32_t) & BM_SDHC_MMCBOOT_BOOTEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BOOTEN field to a new value.
-#define BW_SDHC_MMCBOOT_BOOTEN(v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_MMCBOOT, field AUTOSABGEN[7] (RW)
- *
- * When boot, enable auto stop at block gap function. This function will be
- * triggered, and host will stop at block gap when received card block cnt is equal
- * to BOOTBLKCNT.
- */
-//@{
-#define BP_SDHC_MMCBOOT_AUTOSABGEN (7U) //!< Bit position for SDHC_MMCBOOT_AUTOSABGEN.
-#define BM_SDHC_MMCBOOT_AUTOSABGEN (0x00000080U) //!< Bit mask for SDHC_MMCBOOT_AUTOSABGEN.
-#define BS_SDHC_MMCBOOT_AUTOSABGEN (1U) //!< Bit field size in bits for SDHC_MMCBOOT_AUTOSABGEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_MMCBOOT_AUTOSABGEN field.
-#define BR_SDHC_MMCBOOT_AUTOSABGEN (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_AUTOSABGEN))
-#endif
-
-//! @brief Format value for bitfield SDHC_MMCBOOT_AUTOSABGEN.
-#define BF_SDHC_MMCBOOT_AUTOSABGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_AUTOSABGEN), uint32_t) & BM_SDHC_MMCBOOT_AUTOSABGEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the AUTOSABGEN field to a new value.
-#define BW_SDHC_MMCBOOT_AUTOSABGEN(v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_AUTOSABGEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SDHC_MMCBOOT, field BOOTBLKCNT[31:16] (RW)
- *
- * Defines the stop at block gap value of automatic mode. When received card
- * block cnt is equal to BOOTBLKCNT and AUTOSABGEN is 1, then stop at block gap.
- */
-//@{
-#define BP_SDHC_MMCBOOT_BOOTBLKCNT (16U) //!< Bit position for SDHC_MMCBOOT_BOOTBLKCNT.
-#define BM_SDHC_MMCBOOT_BOOTBLKCNT (0xFFFF0000U) //!< Bit mask for SDHC_MMCBOOT_BOOTBLKCNT.
-#define BS_SDHC_MMCBOOT_BOOTBLKCNT (16U) //!< Bit field size in bits for SDHC_MMCBOOT_BOOTBLKCNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_MMCBOOT_BOOTBLKCNT field.
-#define BR_SDHC_MMCBOOT_BOOTBLKCNT (HW_SDHC_MMCBOOT.B.BOOTBLKCNT)
-#endif
-
-//! @brief Format value for bitfield SDHC_MMCBOOT_BOOTBLKCNT.
-#define BF_SDHC_MMCBOOT_BOOTBLKCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_BOOTBLKCNT), uint32_t) & BM_SDHC_MMCBOOT_BOOTBLKCNT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BOOTBLKCNT field to a new value.
-#define BW_SDHC_MMCBOOT_BOOTBLKCNT(v) (HW_SDHC_MMCBOOT_WR((HW_SDHC_MMCBOOT_RD() & ~BM_SDHC_MMCBOOT_BOOTBLKCNT) | BF_SDHC_MMCBOOT_BOOTBLKCNT(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SDHC_HOSTVER - Host Controller Version
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SDHC_HOSTVER - Host Controller Version (RO)
- *
- * Reset value: 0x00001201U
- *
- * This register contains the vendor host controller version information. All
- * bits are read only and will read the same as the power-reset value.
- */
-typedef union _hw_sdhc_hostver
-{
- uint32_t U;
- struct _hw_sdhc_hostver_bitfields
- {
- uint32_t SVN : 8; //!< [7:0] Specification Version Number
- uint32_t VVN : 8; //!< [15:8] Vendor Version Number
- uint32_t RESERVED0 : 16; //!< [31:16]
- } B;
-} hw_sdhc_hostver_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SDHC_HOSTVER register
- */
-//@{
-#define HW_SDHC_HOSTVER_ADDR (REGS_SDHC_BASE + 0xFCU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SDHC_HOSTVER (*(__I hw_sdhc_hostver_t *) HW_SDHC_HOSTVER_ADDR)
-#define HW_SDHC_HOSTVER_RD() (HW_SDHC_HOSTVER.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual SDHC_HOSTVER bitfields
- */
-
-/*!
- * @name Register SDHC_HOSTVER, field SVN[7:0] (RO)
- *
- * These status bits indicate the host controller specification version.
- *
- * Values:
- * - 1 - SD host specification version 2.0, supports test event register and
- * ADMA.
- */
-//@{
-#define BP_SDHC_HOSTVER_SVN (0U) //!< Bit position for SDHC_HOSTVER_SVN.
-#define BM_SDHC_HOSTVER_SVN (0x000000FFU) //!< Bit mask for SDHC_HOSTVER_SVN.
-#define BS_SDHC_HOSTVER_SVN (8U) //!< Bit field size in bits for SDHC_HOSTVER_SVN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_HOSTVER_SVN field.
-#define BR_SDHC_HOSTVER_SVN (HW_SDHC_HOSTVER.B.SVN)
-#endif
-//@}
-
-/*!
- * @name Register SDHC_HOSTVER, field VVN[15:8] (RO)
- *
- * These status bits are reserved for the vendor version number. The host driver
- * shall not use this status.
- *
- * Values:
- * - 0 - Freescale SDHC version 1.0
- * - 10000 - Freescale SDHC version 2.0
- * - 10001 - Freescale SDHC version 2.1
- * - 10010 - Freescale SDHC version 2.2
- */
-//@{
-#define BP_SDHC_HOSTVER_VVN (8U) //!< Bit position for SDHC_HOSTVER_VVN.
-#define BM_SDHC_HOSTVER_VVN (0x0000FF00U) //!< Bit mask for SDHC_HOSTVER_VVN.
-#define BS_SDHC_HOSTVER_VVN (8U) //!< Bit field size in bits for SDHC_HOSTVER_VVN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SDHC_HOSTVER_VVN field.
-#define BR_SDHC_HOSTVER_VVN (HW_SDHC_HOSTVER.B.VVN)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_sdhc_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All SDHC module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_sdhc
-{
- __IO hw_sdhc_dsaddr_t DSADDR; //!< [0x0] DMA System Address register
- __IO hw_sdhc_blkattr_t BLKATTR; //!< [0x4] Block Attributes register
- __IO hw_sdhc_cmdarg_t CMDARG; //!< [0x8] Command Argument register
- __IO hw_sdhc_xfertyp_t XFERTYP; //!< [0xC] Transfer Type register
- __I hw_sdhc_cmdrsp0_t CMDRSP0; //!< [0x10] Command Response 0
- __I hw_sdhc_cmdrsp1_t CMDRSP1; //!< [0x14] Command Response 1
- __I hw_sdhc_cmdrsp2_t CMDRSP2; //!< [0x18] Command Response 2
- __I hw_sdhc_cmdrsp3_t CMDRSP3; //!< [0x1C] Command Response 3
- __IO hw_sdhc_datport_t DATPORT; //!< [0x20] Buffer Data Port register
- __I hw_sdhc_prsstat_t PRSSTAT; //!< [0x24] Present State register
- __IO hw_sdhc_proctl_t PROCTL; //!< [0x28] Protocol Control register
- __IO hw_sdhc_sysctl_t SYSCTL; //!< [0x2C] System Control register
- __IO hw_sdhc_irqstat_t IRQSTAT; //!< [0x30] Interrupt Status register
- __IO hw_sdhc_irqstaten_t IRQSTATEN; //!< [0x34] Interrupt Status Enable register
- __IO hw_sdhc_irqsigen_t IRQSIGEN; //!< [0x38] Interrupt Signal Enable register
- __I hw_sdhc_ac12err_t AC12ERR; //!< [0x3C] Auto CMD12 Error Status Register
- __I hw_sdhc_htcapblt_t HTCAPBLT; //!< [0x40] Host Controller Capabilities
- __IO hw_sdhc_wml_t WML; //!< [0x44] Watermark Level Register
- uint8_t _reserved0[8];
- __O hw_sdhc_fevt_t FEVT; //!< [0x50] Force Event register
- __I hw_sdhc_admaes_t ADMAES; //!< [0x54] ADMA Error Status register
- __IO hw_sdhc_adsaddr_t ADSADDR; //!< [0x58] ADMA System Addressregister
- uint8_t _reserved1[100];
- __IO hw_sdhc_vendor_t VENDOR; //!< [0xC0] Vendor Specific register
- __IO hw_sdhc_mmcboot_t MMCBOOT; //!< [0xC4] MMC Boot register
- uint8_t _reserved2[52];
- __I hw_sdhc_hostver_t HOSTVER; //!< [0xFC] Host Controller Version
-} hw_sdhc_t;
-#pragma pack()
-
-//! @brief Macro to access all SDHC registers.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_SDHC</code>.
-#define HW_SDHC (*(hw_sdhc_t *) REGS_SDHC_BASE)
-#endif
-
-#endif // __HW_SDHC_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_sim.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,4553 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_SIM_REGISTERS_H__
-#define __HW_SIM_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 SIM
- *
- * System Integration Module
- *
- * Registers defined in this header file:
- * - HW_SIM_SOPT1 - System Options Register 1
- * - HW_SIM_SOPT1CFG - SOPT1 Configuration Register
- * - HW_SIM_SOPT2 - System Options Register 2
- * - HW_SIM_SOPT4 - System Options Register 4
- * - HW_SIM_SOPT5 - System Options Register 5
- * - HW_SIM_SOPT7 - System Options Register 7
- * - HW_SIM_SDID - System Device Identification Register
- * - HW_SIM_SCGC1 - System Clock Gating Control Register 1
- * - HW_SIM_SCGC2 - System Clock Gating Control Register 2
- * - HW_SIM_SCGC3 - System Clock Gating Control Register 3
- * - HW_SIM_SCGC4 - System Clock Gating Control Register 4
- * - HW_SIM_SCGC5 - System Clock Gating Control Register 5
- * - HW_SIM_SCGC6 - System Clock Gating Control Register 6
- * - HW_SIM_SCGC7 - System Clock Gating Control Register 7
- * - HW_SIM_CLKDIV1 - System Clock Divider Register 1
- * - HW_SIM_CLKDIV2 - System Clock Divider Register 2
- * - HW_SIM_FCFG1 - Flash Configuration Register 1
- * - HW_SIM_FCFG2 - Flash Configuration Register 2
- * - HW_SIM_UIDH - Unique Identification Register High
- * - HW_SIM_UIDMH - Unique Identification Register Mid-High
- * - HW_SIM_UIDML - Unique Identification Register Mid Low
- * - HW_SIM_UIDL - Unique Identification Register Low
- *
- * - hw_sim_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_SIM_BASE
-#define HW_SIM_INSTANCE_COUNT (1U) //!< Number of instances of the SIM module.
-#define REGS_SIM_BASE (0x40047000U) //!< Base address for SIM.
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SIM_SOPT1 - System Options Register 1
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SIM_SOPT1 - System Options Register 1 (RW)
- *
- * Reset value: 0x80000000U
- *
- * The SOPT1 register is only reset on POR or LVD.
- */
-typedef union _hw_sim_sopt1
-{
- uint32_t U;
- struct _hw_sim_sopt1_bitfields
- {
- uint32_t RESERVED0 : 12; //!< [11:0]
- uint32_t RAMSIZE : 4; //!< [15:12] RAM size
- uint32_t RESERVED1 : 2; //!< [17:16]
- uint32_t OSC32KSEL : 2; //!< [19:18] 32K oscillator clock select
- uint32_t RESERVED2 : 9; //!< [28:20]
- uint32_t USBVSTBY : 1; //!< [29] USB voltage regulator in standby
- //! mode during VLPR and VLPW modes
- uint32_t USBSSTBY : 1; //!< [30] USB voltage regulator in standby
- //! mode during Stop, VLPS, LLS and VLLS modes.
- uint32_t USBREGEN : 1; //!< [31] USB voltage regulator enable
- } B;
-} hw_sim_sopt1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SIM_SOPT1 register
- */
-//@{
-#define HW_SIM_SOPT1_ADDR (REGS_SIM_BASE + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SIM_SOPT1 (*(__IO hw_sim_sopt1_t *) HW_SIM_SOPT1_ADDR)
-#define HW_SIM_SOPT1_RD() (HW_SIM_SOPT1.U)
-#define HW_SIM_SOPT1_WR(v) (HW_SIM_SOPT1.U = (v))
-#define HW_SIM_SOPT1_SET(v) (HW_SIM_SOPT1_WR(HW_SIM_SOPT1_RD() | (v)))
-#define HW_SIM_SOPT1_CLR(v) (HW_SIM_SOPT1_WR(HW_SIM_SOPT1_RD() & ~(v)))
-#define HW_SIM_SOPT1_TOG(v) (HW_SIM_SOPT1_WR(HW_SIM_SOPT1_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SIM_SOPT1 bitfields
- */
-
-/*!
- * @name Register SIM_SOPT1, field RAMSIZE[15:12] (RO)
- *
- * This field specifies the amount of system RAM available on the device.
- *
- * Values:
- * - 0001 - 8 KB
- * - 0011 - 16 KB
- * - 0100 - 24 KB
- * - 0101 - 32 KB
- * - 0110 - 48 KB
- * - 0111 - 64 KB
- * - 1000 - 96 KB
- * - 1001 - 128 KB
- * - 1011 - 256 KB
- */
-//@{
-#define BP_SIM_SOPT1_RAMSIZE (12U) //!< Bit position for SIM_SOPT1_RAMSIZE.
-#define BM_SIM_SOPT1_RAMSIZE (0x0000F000U) //!< Bit mask for SIM_SOPT1_RAMSIZE.
-#define BS_SIM_SOPT1_RAMSIZE (4U) //!< Bit field size in bits for SIM_SOPT1_RAMSIZE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT1_RAMSIZE field.
-#define BR_SIM_SOPT1_RAMSIZE (HW_SIM_SOPT1.B.RAMSIZE)
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT1, field OSC32KSEL[19:18] (RW)
- *
- * Selects the 32 kHz clock source (ERCLK32K) for LPTMR. This field is reset
- * only on POR/LVD.
- *
- * Values:
- * - 00 - System oscillator (OSC32KCLK)
- * - 01 - Reserved
- * - 10 - RTC 32.768kHz oscillator
- * - 11 - LPO 1 kHz
- */
-//@{
-#define BP_SIM_SOPT1_OSC32KSEL (18U) //!< Bit position for SIM_SOPT1_OSC32KSEL.
-#define BM_SIM_SOPT1_OSC32KSEL (0x000C0000U) //!< Bit mask for SIM_SOPT1_OSC32KSEL.
-#define BS_SIM_SOPT1_OSC32KSEL (2U) //!< Bit field size in bits for SIM_SOPT1_OSC32KSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT1_OSC32KSEL field.
-#define BR_SIM_SOPT1_OSC32KSEL (HW_SIM_SOPT1.B.OSC32KSEL)
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT1_OSC32KSEL.
-#define BF_SIM_SOPT1_OSC32KSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1_OSC32KSEL), uint32_t) & BM_SIM_SOPT1_OSC32KSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the OSC32KSEL field to a new value.
-#define BW_SIM_SOPT1_OSC32KSEL(v) (HW_SIM_SOPT1_WR((HW_SIM_SOPT1_RD() & ~BM_SIM_SOPT1_OSC32KSEL) | BF_SIM_SOPT1_OSC32KSEL(v)))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT1, field USBVSTBY[29] (RW)
- *
- * Controls whether the USB voltage regulator is placed in standby mode during
- * VLPR and VLPW modes.
- *
- * Values:
- * - 0 - USB voltage regulator not in standby during VLPR and VLPW modes.
- * - 1 - USB voltage regulator in standby during VLPR and VLPW modes.
- */
-//@{
-#define BP_SIM_SOPT1_USBVSTBY (29U) //!< Bit position for SIM_SOPT1_USBVSTBY.
-#define BM_SIM_SOPT1_USBVSTBY (0x20000000U) //!< Bit mask for SIM_SOPT1_USBVSTBY.
-#define BS_SIM_SOPT1_USBVSTBY (1U) //!< Bit field size in bits for SIM_SOPT1_USBVSTBY.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT1_USBVSTBY field.
-#define BR_SIM_SOPT1_USBVSTBY (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBVSTBY))
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT1_USBVSTBY.
-#define BF_SIM_SOPT1_USBVSTBY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1_USBVSTBY), uint32_t) & BM_SIM_SOPT1_USBVSTBY)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the USBVSTBY field to a new value.
-#define BW_SIM_SOPT1_USBVSTBY(v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBVSTBY) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT1, field USBSSTBY[30] (RW)
- *
- * Controls whether the USB voltage regulator is placed in standby mode during
- * Stop, VLPS, LLS and VLLS modes.
- *
- * Values:
- * - 0 - USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS
- * modes.
- * - 1 - USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes.
- */
-//@{
-#define BP_SIM_SOPT1_USBSSTBY (30U) //!< Bit position for SIM_SOPT1_USBSSTBY.
-#define BM_SIM_SOPT1_USBSSTBY (0x40000000U) //!< Bit mask for SIM_SOPT1_USBSSTBY.
-#define BS_SIM_SOPT1_USBSSTBY (1U) //!< Bit field size in bits for SIM_SOPT1_USBSSTBY.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT1_USBSSTBY field.
-#define BR_SIM_SOPT1_USBSSTBY (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBSSTBY))
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT1_USBSSTBY.
-#define BF_SIM_SOPT1_USBSSTBY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1_USBSSTBY), uint32_t) & BM_SIM_SOPT1_USBSSTBY)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the USBSSTBY field to a new value.
-#define BW_SIM_SOPT1_USBSSTBY(v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBSSTBY) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT1, field USBREGEN[31] (RW)
- *
- * Controls whether the USB voltage regulator is enabled.
- *
- * Values:
- * - 0 - USB voltage regulator is disabled.
- * - 1 - USB voltage regulator is enabled.
- */
-//@{
-#define BP_SIM_SOPT1_USBREGEN (31U) //!< Bit position for SIM_SOPT1_USBREGEN.
-#define BM_SIM_SOPT1_USBREGEN (0x80000000U) //!< Bit mask for SIM_SOPT1_USBREGEN.
-#define BS_SIM_SOPT1_USBREGEN (1U) //!< Bit field size in bits for SIM_SOPT1_USBREGEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT1_USBREGEN field.
-#define BR_SIM_SOPT1_USBREGEN (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBREGEN))
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT1_USBREGEN.
-#define BF_SIM_SOPT1_USBREGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1_USBREGEN), uint32_t) & BM_SIM_SOPT1_USBREGEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the USBREGEN field to a new value.
-#define BW_SIM_SOPT1_USBREGEN(v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBREGEN) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SIM_SOPT1CFG - SOPT1 Configuration Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SIM_SOPT1CFG - SOPT1 Configuration Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * The SOPT1CFG register is reset on System Reset not VLLS.
- */
-typedef union _hw_sim_sopt1cfg
-{
- uint32_t U;
- struct _hw_sim_sopt1cfg_bitfields
- {
- uint32_t RESERVED0 : 24; //!< [23:0]
- uint32_t URWE : 1; //!< [24] USB voltage regulator enable write enable
- uint32_t UVSWE : 1; //!< [25] USB voltage regulator VLP standby write
- //! enable
- uint32_t USSWE : 1; //!< [26] USB voltage regulator stop standby
- //! write enable
- uint32_t RESERVED1 : 5; //!< [31:27]
- } B;
-} hw_sim_sopt1cfg_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SIM_SOPT1CFG register
- */
-//@{
-#define HW_SIM_SOPT1CFG_ADDR (REGS_SIM_BASE + 0x4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SIM_SOPT1CFG (*(__IO hw_sim_sopt1cfg_t *) HW_SIM_SOPT1CFG_ADDR)
-#define HW_SIM_SOPT1CFG_RD() (HW_SIM_SOPT1CFG.U)
-#define HW_SIM_SOPT1CFG_WR(v) (HW_SIM_SOPT1CFG.U = (v))
-#define HW_SIM_SOPT1CFG_SET(v) (HW_SIM_SOPT1CFG_WR(HW_SIM_SOPT1CFG_RD() | (v)))
-#define HW_SIM_SOPT1CFG_CLR(v) (HW_SIM_SOPT1CFG_WR(HW_SIM_SOPT1CFG_RD() & ~(v)))
-#define HW_SIM_SOPT1CFG_TOG(v) (HW_SIM_SOPT1CFG_WR(HW_SIM_SOPT1CFG_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SIM_SOPT1CFG bitfields
- */
-
-/*!
- * @name Register SIM_SOPT1CFG, field URWE[24] (RW)
- *
- * Writing one to the URWE bit allows the SOPT1 USBREGEN bit to be written. This
- * register bit clears after a write to USBREGEN.
- *
- * Values:
- * - 0 - SOPT1 USBREGEN cannot be written.
- * - 1 - SOPT1 USBREGEN can be written.
- */
-//@{
-#define BP_SIM_SOPT1CFG_URWE (24U) //!< Bit position for SIM_SOPT1CFG_URWE.
-#define BM_SIM_SOPT1CFG_URWE (0x01000000U) //!< Bit mask for SIM_SOPT1CFG_URWE.
-#define BS_SIM_SOPT1CFG_URWE (1U) //!< Bit field size in bits for SIM_SOPT1CFG_URWE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT1CFG_URWE field.
-#define BR_SIM_SOPT1CFG_URWE (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_URWE))
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT1CFG_URWE.
-#define BF_SIM_SOPT1CFG_URWE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1CFG_URWE), uint32_t) & BM_SIM_SOPT1CFG_URWE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the URWE field to a new value.
-#define BW_SIM_SOPT1CFG_URWE(v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_URWE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT1CFG, field UVSWE[25] (RW)
- *
- * Writing one to the UVSWE bit allows the SOPT1 USBVSTBY bit to be written.
- * This register bit clears after a write to USBVSTBY.
- *
- * Values:
- * - 0 - SOPT1 USBVSTBY cannot be written.
- * - 1 - SOPT1 USBVSTBY can be written.
- */
-//@{
-#define BP_SIM_SOPT1CFG_UVSWE (25U) //!< Bit position for SIM_SOPT1CFG_UVSWE.
-#define BM_SIM_SOPT1CFG_UVSWE (0x02000000U) //!< Bit mask for SIM_SOPT1CFG_UVSWE.
-#define BS_SIM_SOPT1CFG_UVSWE (1U) //!< Bit field size in bits for SIM_SOPT1CFG_UVSWE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT1CFG_UVSWE field.
-#define BR_SIM_SOPT1CFG_UVSWE (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_UVSWE))
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT1CFG_UVSWE.
-#define BF_SIM_SOPT1CFG_UVSWE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1CFG_UVSWE), uint32_t) & BM_SIM_SOPT1CFG_UVSWE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the UVSWE field to a new value.
-#define BW_SIM_SOPT1CFG_UVSWE(v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_UVSWE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT1CFG, field USSWE[26] (RW)
- *
- * Writing one to the USSWE bit allows the SOPT1 USBSSTBY bit to be written.
- * This register bit clears after a write to USBSSTBY.
- *
- * Values:
- * - 0 - SOPT1 USBSSTBY cannot be written.
- * - 1 - SOPT1 USBSSTBY can be written.
- */
-//@{
-#define BP_SIM_SOPT1CFG_USSWE (26U) //!< Bit position for SIM_SOPT1CFG_USSWE.
-#define BM_SIM_SOPT1CFG_USSWE (0x04000000U) //!< Bit mask for SIM_SOPT1CFG_USSWE.
-#define BS_SIM_SOPT1CFG_USSWE (1U) //!< Bit field size in bits for SIM_SOPT1CFG_USSWE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT1CFG_USSWE field.
-#define BR_SIM_SOPT1CFG_USSWE (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_USSWE))
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT1CFG_USSWE.
-#define BF_SIM_SOPT1CFG_USSWE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1CFG_USSWE), uint32_t) & BM_SIM_SOPT1CFG_USSWE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the USSWE field to a new value.
-#define BW_SIM_SOPT1CFG_USSWE(v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_USSWE) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SIM_SOPT2 - System Options Register 2
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SIM_SOPT2 - System Options Register 2 (RW)
- *
- * Reset value: 0x00001000U
- *
- * SOPT2 contains the controls for selecting many of the module clock source
- * options on this device. See the Clock Distribution chapter for more information
- * including clocking diagrams and definitions of device clocks.
- */
-typedef union _hw_sim_sopt2
-{
- uint32_t U;
- struct _hw_sim_sopt2_bitfields
- {
- uint32_t RESERVED0 : 4; //!< [3:0]
- uint32_t RTCCLKOUTSEL : 1; //!< [4] RTC clock out select
- uint32_t CLKOUTSEL : 3; //!< [7:5] CLKOUT select
- uint32_t FBSL : 2; //!< [9:8] FlexBus security level
- uint32_t RESERVED1 : 1; //!< [10]
- uint32_t PTD7PAD : 1; //!< [11] PTD7 pad drive strength
- uint32_t TRACECLKSEL : 1; //!< [12] Debug trace clock select
- uint32_t RESERVED2 : 3; //!< [15:13]
- uint32_t PLLFLLSEL : 2; //!< [17:16] PLL/FLL clock select
- uint32_t USBSRC : 1; //!< [18] USB clock source select
- uint32_t RMIISRC : 1; //!< [19] RMII clock source select
- uint32_t TIMESRC : 2; //!< [21:20] IEEE 1588 timestamp clock source
- //! select
- uint32_t RESERVED3 : 6; //!< [27:22]
- uint32_t SDHCSRC : 2; //!< [29:28] SDHC clock source select
- uint32_t RESERVED4 : 2; //!< [31:30]
- } B;
-} hw_sim_sopt2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SIM_SOPT2 register
- */
-//@{
-#define HW_SIM_SOPT2_ADDR (REGS_SIM_BASE + 0x1004U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SIM_SOPT2 (*(__IO hw_sim_sopt2_t *) HW_SIM_SOPT2_ADDR)
-#define HW_SIM_SOPT2_RD() (HW_SIM_SOPT2.U)
-#define HW_SIM_SOPT2_WR(v) (HW_SIM_SOPT2.U = (v))
-#define HW_SIM_SOPT2_SET(v) (HW_SIM_SOPT2_WR(HW_SIM_SOPT2_RD() | (v)))
-#define HW_SIM_SOPT2_CLR(v) (HW_SIM_SOPT2_WR(HW_SIM_SOPT2_RD() & ~(v)))
-#define HW_SIM_SOPT2_TOG(v) (HW_SIM_SOPT2_WR(HW_SIM_SOPT2_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SIM_SOPT2 bitfields
- */
-
-/*!
- * @name Register SIM_SOPT2, field RTCCLKOUTSEL[4] (RW)
- *
- * Selects either the RTC 1 Hz clock or the 32.768kHz clock to be output on the
- * RTC_CLKOUT pin.
- *
- * Values:
- * - 0 - RTC 1 Hz clock is output on the RTC_CLKOUT pin.
- * - 1 - RTC 32.768kHz clock is output on the RTC_CLKOUT pin.
- */
-//@{
-#define BP_SIM_SOPT2_RTCCLKOUTSEL (4U) //!< Bit position for SIM_SOPT2_RTCCLKOUTSEL.
-#define BM_SIM_SOPT2_RTCCLKOUTSEL (0x00000010U) //!< Bit mask for SIM_SOPT2_RTCCLKOUTSEL.
-#define BS_SIM_SOPT2_RTCCLKOUTSEL (1U) //!< Bit field size in bits for SIM_SOPT2_RTCCLKOUTSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT2_RTCCLKOUTSEL field.
-#define BR_SIM_SOPT2_RTCCLKOUTSEL (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_RTCCLKOUTSEL))
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT2_RTCCLKOUTSEL.
-#define BF_SIM_SOPT2_RTCCLKOUTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_RTCCLKOUTSEL), uint32_t) & BM_SIM_SOPT2_RTCCLKOUTSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RTCCLKOUTSEL field to a new value.
-#define BW_SIM_SOPT2_RTCCLKOUTSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_RTCCLKOUTSEL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT2, field CLKOUTSEL[7:5] (RW)
- *
- * Selects the clock to output on the CLKOUT pin.
- *
- * Values:
- * - 000 - FlexBus CLKOUT
- * - 001 - Reserved
- * - 010 - Flash clock
- * - 011 - LPO clock (1 kHz)
- * - 100 - MCGIRCLK
- * - 101 - RTC 32.768kHz clock
- * - 110 - OSCERCLK0
- * - 111 - IRC 48 MHz clock
- */
-//@{
-#define BP_SIM_SOPT2_CLKOUTSEL (5U) //!< Bit position for SIM_SOPT2_CLKOUTSEL.
-#define BM_SIM_SOPT2_CLKOUTSEL (0x000000E0U) //!< Bit mask for SIM_SOPT2_CLKOUTSEL.
-#define BS_SIM_SOPT2_CLKOUTSEL (3U) //!< Bit field size in bits for SIM_SOPT2_CLKOUTSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT2_CLKOUTSEL field.
-#define BR_SIM_SOPT2_CLKOUTSEL (HW_SIM_SOPT2.B.CLKOUTSEL)
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT2_CLKOUTSEL.
-#define BF_SIM_SOPT2_CLKOUTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_CLKOUTSEL), uint32_t) & BM_SIM_SOPT2_CLKOUTSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CLKOUTSEL field to a new value.
-#define BW_SIM_SOPT2_CLKOUTSEL(v) (HW_SIM_SOPT2_WR((HW_SIM_SOPT2_RD() & ~BM_SIM_SOPT2_CLKOUTSEL) | BF_SIM_SOPT2_CLKOUTSEL(v)))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT2, field FBSL[9:8] (RW)
- *
- * If flash security is enabled, then this field affects what CPU operations can
- * access off-chip via the FlexBus interface. This field has no effect if flash
- * security is not enabled.
- *
- * Values:
- * - 00 - All off-chip accesses (instruction and data) via the FlexBus are
- * disallowed.
- * - 01 - All off-chip accesses (instruction and data) via the FlexBus are
- * disallowed.
- * - 10 - Off-chip instruction accesses are disallowed. Data accesses are
- * allowed.
- * - 11 - Off-chip instruction accesses and data accesses are allowed.
- */
-//@{
-#define BP_SIM_SOPT2_FBSL (8U) //!< Bit position for SIM_SOPT2_FBSL.
-#define BM_SIM_SOPT2_FBSL (0x00000300U) //!< Bit mask for SIM_SOPT2_FBSL.
-#define BS_SIM_SOPT2_FBSL (2U) //!< Bit field size in bits for SIM_SOPT2_FBSL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT2_FBSL field.
-#define BR_SIM_SOPT2_FBSL (HW_SIM_SOPT2.B.FBSL)
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT2_FBSL.
-#define BF_SIM_SOPT2_FBSL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_FBSL), uint32_t) & BM_SIM_SOPT2_FBSL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FBSL field to a new value.
-#define BW_SIM_SOPT2_FBSL(v) (HW_SIM_SOPT2_WR((HW_SIM_SOPT2_RD() & ~BM_SIM_SOPT2_FBSL) | BF_SIM_SOPT2_FBSL(v)))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT2, field PTD7PAD[11] (RW)
- *
- * Controls the output drive strength of the PTD7 pin by selecting either one or
- * two pads to drive it.
- *
- * Values:
- * - 0 - Single-pad drive strength for PTD7.
- * - 1 - Double pad drive strength for PTD7.
- */
-//@{
-#define BP_SIM_SOPT2_PTD7PAD (11U) //!< Bit position for SIM_SOPT2_PTD7PAD.
-#define BM_SIM_SOPT2_PTD7PAD (0x00000800U) //!< Bit mask for SIM_SOPT2_PTD7PAD.
-#define BS_SIM_SOPT2_PTD7PAD (1U) //!< Bit field size in bits for SIM_SOPT2_PTD7PAD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT2_PTD7PAD field.
-#define BR_SIM_SOPT2_PTD7PAD (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_PTD7PAD))
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT2_PTD7PAD.
-#define BF_SIM_SOPT2_PTD7PAD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_PTD7PAD), uint32_t) & BM_SIM_SOPT2_PTD7PAD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PTD7PAD field to a new value.
-#define BW_SIM_SOPT2_PTD7PAD(v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_PTD7PAD) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT2, field TRACECLKSEL[12] (RW)
- *
- * Selects the core/system clock or MCG output clock (MCGOUTCLK) as the trace
- * clock source.
- *
- * Values:
- * - 0 - MCGOUTCLK
- * - 1 - Core/system clock
- */
-//@{
-#define BP_SIM_SOPT2_TRACECLKSEL (12U) //!< Bit position for SIM_SOPT2_TRACECLKSEL.
-#define BM_SIM_SOPT2_TRACECLKSEL (0x00001000U) //!< Bit mask for SIM_SOPT2_TRACECLKSEL.
-#define BS_SIM_SOPT2_TRACECLKSEL (1U) //!< Bit field size in bits for SIM_SOPT2_TRACECLKSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT2_TRACECLKSEL field.
-#define BR_SIM_SOPT2_TRACECLKSEL (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_TRACECLKSEL))
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT2_TRACECLKSEL.
-#define BF_SIM_SOPT2_TRACECLKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_TRACECLKSEL), uint32_t) & BM_SIM_SOPT2_TRACECLKSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TRACECLKSEL field to a new value.
-#define BW_SIM_SOPT2_TRACECLKSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_TRACECLKSEL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT2, field PLLFLLSEL[17:16] (RW)
- *
- * Selects the high frequency clock for various peripheral clocking options.
- *
- * Values:
- * - 00 - MCGFLLCLK clock
- * - 01 - MCGPLLCLK clock
- * - 10 - Reserved
- * - 11 - IRC48 MHz clock
- */
-//@{
-#define BP_SIM_SOPT2_PLLFLLSEL (16U) //!< Bit position for SIM_SOPT2_PLLFLLSEL.
-#define BM_SIM_SOPT2_PLLFLLSEL (0x00030000U) //!< Bit mask for SIM_SOPT2_PLLFLLSEL.
-#define BS_SIM_SOPT2_PLLFLLSEL (2U) //!< Bit field size in bits for SIM_SOPT2_PLLFLLSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT2_PLLFLLSEL field.
-#define BR_SIM_SOPT2_PLLFLLSEL (HW_SIM_SOPT2.B.PLLFLLSEL)
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT2_PLLFLLSEL.
-#define BF_SIM_SOPT2_PLLFLLSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_PLLFLLSEL), uint32_t) & BM_SIM_SOPT2_PLLFLLSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PLLFLLSEL field to a new value.
-#define BW_SIM_SOPT2_PLLFLLSEL(v) (HW_SIM_SOPT2_WR((HW_SIM_SOPT2_RD() & ~BM_SIM_SOPT2_PLLFLLSEL) | BF_SIM_SOPT2_PLLFLLSEL(v)))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT2, field USBSRC[18] (RW)
- *
- * Selects the clock source for the USB 48 MHz clock.
- *
- * Values:
- * - 0 - External bypass clock (USB_CLKIN).
- * - 1 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
- * SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by
- * SIM_CLKDIV2[USBFRAC, USBDIV].
- */
-//@{
-#define BP_SIM_SOPT2_USBSRC (18U) //!< Bit position for SIM_SOPT2_USBSRC.
-#define BM_SIM_SOPT2_USBSRC (0x00040000U) //!< Bit mask for SIM_SOPT2_USBSRC.
-#define BS_SIM_SOPT2_USBSRC (1U) //!< Bit field size in bits for SIM_SOPT2_USBSRC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT2_USBSRC field.
-#define BR_SIM_SOPT2_USBSRC (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_USBSRC))
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT2_USBSRC.
-#define BF_SIM_SOPT2_USBSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_USBSRC), uint32_t) & BM_SIM_SOPT2_USBSRC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the USBSRC field to a new value.
-#define BW_SIM_SOPT2_USBSRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_USBSRC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT2, field RMIISRC[19] (RW)
- *
- * Selects the clock source for the Ethernet RMII interface
- *
- * Values:
- * - 0 - EXTAL clock
- * - 1 - External bypass clock (ENET_1588_CLKIN).
- */
-//@{
-#define BP_SIM_SOPT2_RMIISRC (19U) //!< Bit position for SIM_SOPT2_RMIISRC.
-#define BM_SIM_SOPT2_RMIISRC (0x00080000U) //!< Bit mask for SIM_SOPT2_RMIISRC.
-#define BS_SIM_SOPT2_RMIISRC (1U) //!< Bit field size in bits for SIM_SOPT2_RMIISRC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT2_RMIISRC field.
-#define BR_SIM_SOPT2_RMIISRC (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_RMIISRC))
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT2_RMIISRC.
-#define BF_SIM_SOPT2_RMIISRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_RMIISRC), uint32_t) & BM_SIM_SOPT2_RMIISRC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RMIISRC field to a new value.
-#define BW_SIM_SOPT2_RMIISRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_RMIISRC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT2, field TIMESRC[21:20] (RW)
- *
- * Selects the clock source for the Ethernet timestamp clock.
- *
- * Values:
- * - 00 - Core/system clock.
- * - 01 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
- * SOPT2[PLLFLLSEL].
- * - 10 - OSCERCLK clock
- * - 11 - External bypass clock (ENET_1588_CLKIN).
- */
-//@{
-#define BP_SIM_SOPT2_TIMESRC (20U) //!< Bit position for SIM_SOPT2_TIMESRC.
-#define BM_SIM_SOPT2_TIMESRC (0x00300000U) //!< Bit mask for SIM_SOPT2_TIMESRC.
-#define BS_SIM_SOPT2_TIMESRC (2U) //!< Bit field size in bits for SIM_SOPT2_TIMESRC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT2_TIMESRC field.
-#define BR_SIM_SOPT2_TIMESRC (HW_SIM_SOPT2.B.TIMESRC)
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT2_TIMESRC.
-#define BF_SIM_SOPT2_TIMESRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_TIMESRC), uint32_t) & BM_SIM_SOPT2_TIMESRC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TIMESRC field to a new value.
-#define BW_SIM_SOPT2_TIMESRC(v) (HW_SIM_SOPT2_WR((HW_SIM_SOPT2_RD() & ~BM_SIM_SOPT2_TIMESRC) | BF_SIM_SOPT2_TIMESRC(v)))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT2, field SDHCSRC[29:28] (RW)
- *
- * Selects the clock source for the SDHC clock .
- *
- * Values:
- * - 00 - Core/system clock.
- * - 01 - MCGFLLCLK, or MCGPLLCLK , or IRC48M clock as selected by
- * SOPT2[PLLFLLSEL].
- * - 10 - OSCERCLK clock
- * - 11 - External bypass clock (SDHC0_CLKIN)
- */
-//@{
-#define BP_SIM_SOPT2_SDHCSRC (28U) //!< Bit position for SIM_SOPT2_SDHCSRC.
-#define BM_SIM_SOPT2_SDHCSRC (0x30000000U) //!< Bit mask for SIM_SOPT2_SDHCSRC.
-#define BS_SIM_SOPT2_SDHCSRC (2U) //!< Bit field size in bits for SIM_SOPT2_SDHCSRC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT2_SDHCSRC field.
-#define BR_SIM_SOPT2_SDHCSRC (HW_SIM_SOPT2.B.SDHCSRC)
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT2_SDHCSRC.
-#define BF_SIM_SOPT2_SDHCSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_SDHCSRC), uint32_t) & BM_SIM_SOPT2_SDHCSRC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SDHCSRC field to a new value.
-#define BW_SIM_SOPT2_SDHCSRC(v) (HW_SIM_SOPT2_WR((HW_SIM_SOPT2_RD() & ~BM_SIM_SOPT2_SDHCSRC) | BF_SIM_SOPT2_SDHCSRC(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SIM_SOPT4 - System Options Register 4
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SIM_SOPT4 - System Options Register 4 (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_sim_sopt4
-{
- uint32_t U;
- struct _hw_sim_sopt4_bitfields
- {
- uint32_t FTM0FLT0 : 1; //!< [0] FTM0 Fault 0 Select
- uint32_t FTM0FLT1 : 1; //!< [1] FTM0 Fault 1 Select
- uint32_t FTM0FLT2 : 1; //!< [2] FTM0 Fault 2 Select
- uint32_t RESERVED0 : 1; //!< [3]
- uint32_t FTM1FLT0 : 1; //!< [4] FTM1 Fault 0 Select
- uint32_t RESERVED1 : 3; //!< [7:5]
- uint32_t FTM2FLT0 : 1; //!< [8] FTM2 Fault 0 Select
- uint32_t RESERVED2 : 3; //!< [11:9]
- uint32_t FTM3FLT0 : 1; //!< [12] FTM3 Fault 0 Select
- uint32_t RESERVED3 : 5; //!< [17:13]
- uint32_t FTM1CH0SRC : 2; //!< [19:18] FTM1 channel 0 input capture
- //! source select
- uint32_t FTM2CH0SRC : 2; //!< [21:20] FTM2 channel 0 input capture
- //! source select
- uint32_t RESERVED4 : 2; //!< [23:22]
- uint32_t FTM0CLKSEL : 1; //!< [24] FlexTimer 0 External Clock Pin
- //! Select
- uint32_t FTM1CLKSEL : 1; //!< [25] FTM1 External Clock Pin Select
- uint32_t FTM2CLKSEL : 1; //!< [26] FlexTimer 2 External Clock Pin
- //! Select
- uint32_t FTM3CLKSEL : 1; //!< [27] FlexTimer 3 External Clock Pin
- //! Select
- uint32_t FTM0TRG0SRC : 1; //!< [28] FlexTimer 0 Hardware Trigger 0
- //! Source Select
- uint32_t FTM0TRG1SRC : 1; //!< [29] FlexTimer 0 Hardware Trigger 1
- //! Source Select
- uint32_t FTM3TRG0SRC : 1; //!< [30] FlexTimer 3 Hardware Trigger 0
- //! Source Select
- uint32_t FTM3TRG1SRC : 1; //!< [31] FlexTimer 3 Hardware Trigger 1
- //! Source Select
- } B;
-} hw_sim_sopt4_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SIM_SOPT4 register
- */
-//@{
-#define HW_SIM_SOPT4_ADDR (REGS_SIM_BASE + 0x100CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SIM_SOPT4 (*(__IO hw_sim_sopt4_t *) HW_SIM_SOPT4_ADDR)
-#define HW_SIM_SOPT4_RD() (HW_SIM_SOPT4.U)
-#define HW_SIM_SOPT4_WR(v) (HW_SIM_SOPT4.U = (v))
-#define HW_SIM_SOPT4_SET(v) (HW_SIM_SOPT4_WR(HW_SIM_SOPT4_RD() | (v)))
-#define HW_SIM_SOPT4_CLR(v) (HW_SIM_SOPT4_WR(HW_SIM_SOPT4_RD() & ~(v)))
-#define HW_SIM_SOPT4_TOG(v) (HW_SIM_SOPT4_WR(HW_SIM_SOPT4_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SIM_SOPT4 bitfields
- */
-
-/*!
- * @name Register SIM_SOPT4, field FTM0FLT0[0] (RW)
- *
- * Selects the source of FTM0 fault 0. The pin source for fault 0 must be
- * configured for the FTM module fault function through the appropriate pin control
- * register in the port control module.
- *
- * Values:
- * - 0 - FTM0_FLT0 pin
- * - 1 - CMP0 out
- */
-//@{
-#define BP_SIM_SOPT4_FTM0FLT0 (0U) //!< Bit position for SIM_SOPT4_FTM0FLT0.
-#define BM_SIM_SOPT4_FTM0FLT0 (0x00000001U) //!< Bit mask for SIM_SOPT4_FTM0FLT0.
-#define BS_SIM_SOPT4_FTM0FLT0 (1U) //!< Bit field size in bits for SIM_SOPT4_FTM0FLT0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT4_FTM0FLT0 field.
-#define BR_SIM_SOPT4_FTM0FLT0 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT0))
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT4_FTM0FLT0.
-#define BF_SIM_SOPT4_FTM0FLT0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0FLT0), uint32_t) & BM_SIM_SOPT4_FTM0FLT0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FTM0FLT0 field to a new value.
-#define BW_SIM_SOPT4_FTM0FLT0(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT4, field FTM0FLT1[1] (RW)
- *
- * Selects the source of FTM0 fault 1. The pin source for fault 1 must be
- * configured for the FTM module fault function through the appropriate pin control
- * register in the port control module.
- *
- * Values:
- * - 0 - FTM0_FLT1 pin
- * - 1 - CMP1 out
- */
-//@{
-#define BP_SIM_SOPT4_FTM0FLT1 (1U) //!< Bit position for SIM_SOPT4_FTM0FLT1.
-#define BM_SIM_SOPT4_FTM0FLT1 (0x00000002U) //!< Bit mask for SIM_SOPT4_FTM0FLT1.
-#define BS_SIM_SOPT4_FTM0FLT1 (1U) //!< Bit field size in bits for SIM_SOPT4_FTM0FLT1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT4_FTM0FLT1 field.
-#define BR_SIM_SOPT4_FTM0FLT1 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT1))
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT4_FTM0FLT1.
-#define BF_SIM_SOPT4_FTM0FLT1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0FLT1), uint32_t) & BM_SIM_SOPT4_FTM0FLT1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FTM0FLT1 field to a new value.
-#define BW_SIM_SOPT4_FTM0FLT1(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT4, field FTM0FLT2[2] (RW)
- *
- * Selects the source of FTM0 fault 2. The pin source for fault 2 must be
- * configured for the FTM module fault function through the appropriate pin control
- * register in the port control module.
- *
- * Values:
- * - 0 - FTM0_FLT2 pin
- * - 1 - CMP2 out
- */
-//@{
-#define BP_SIM_SOPT4_FTM0FLT2 (2U) //!< Bit position for SIM_SOPT4_FTM0FLT2.
-#define BM_SIM_SOPT4_FTM0FLT2 (0x00000004U) //!< Bit mask for SIM_SOPT4_FTM0FLT2.
-#define BS_SIM_SOPT4_FTM0FLT2 (1U) //!< Bit field size in bits for SIM_SOPT4_FTM0FLT2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT4_FTM0FLT2 field.
-#define BR_SIM_SOPT4_FTM0FLT2 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT2))
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT4_FTM0FLT2.
-#define BF_SIM_SOPT4_FTM0FLT2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0FLT2), uint32_t) & BM_SIM_SOPT4_FTM0FLT2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FTM0FLT2 field to a new value.
-#define BW_SIM_SOPT4_FTM0FLT2(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT4, field FTM1FLT0[4] (RW)
- *
- * Selects the source of FTM1 fault 0. The pin source for fault 0 must be
- * configured for the FTM module fault function through the appropriate pin control
- * register in the port control module.
- *
- * Values:
- * - 0 - FTM1_FLT0 pin
- * - 1 - CMP0 out
- */
-//@{
-#define BP_SIM_SOPT4_FTM1FLT0 (4U) //!< Bit position for SIM_SOPT4_FTM1FLT0.
-#define BM_SIM_SOPT4_FTM1FLT0 (0x00000010U) //!< Bit mask for SIM_SOPT4_FTM1FLT0.
-#define BS_SIM_SOPT4_FTM1FLT0 (1U) //!< Bit field size in bits for SIM_SOPT4_FTM1FLT0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT4_FTM1FLT0 field.
-#define BR_SIM_SOPT4_FTM1FLT0 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM1FLT0))
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT4_FTM1FLT0.
-#define BF_SIM_SOPT4_FTM1FLT0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM1FLT0), uint32_t) & BM_SIM_SOPT4_FTM1FLT0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FTM1FLT0 field to a new value.
-#define BW_SIM_SOPT4_FTM1FLT0(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM1FLT0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT4, field FTM2FLT0[8] (RW)
- *
- * Selects the source of FTM2 fault 0. The pin source for fault 0 must be
- * configured for the FTM module fault function through the appropriate PORTx pin
- * control register.
- *
- * Values:
- * - 0 - FTM2_FLT0 pin
- * - 1 - CMP0 out
- */
-//@{
-#define BP_SIM_SOPT4_FTM2FLT0 (8U) //!< Bit position for SIM_SOPT4_FTM2FLT0.
-#define BM_SIM_SOPT4_FTM2FLT0 (0x00000100U) //!< Bit mask for SIM_SOPT4_FTM2FLT0.
-#define BS_SIM_SOPT4_FTM2FLT0 (1U) //!< Bit field size in bits for SIM_SOPT4_FTM2FLT0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT4_FTM2FLT0 field.
-#define BR_SIM_SOPT4_FTM2FLT0 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM2FLT0))
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT4_FTM2FLT0.
-#define BF_SIM_SOPT4_FTM2FLT0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM2FLT0), uint32_t) & BM_SIM_SOPT4_FTM2FLT0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FTM2FLT0 field to a new value.
-#define BW_SIM_SOPT4_FTM2FLT0(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM2FLT0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT4, field FTM3FLT0[12] (RW)
- *
- * Selects the source of FTM3 fault 0. The pin source for fault 0 must be
- * configured for the FTM module fault function through the appropriate PORTx pin
- * control register.
- *
- * Values:
- * - 0 - FTM3_FLT0 pin
- * - 1 - CMP0 out
- */
-//@{
-#define BP_SIM_SOPT4_FTM3FLT0 (12U) //!< Bit position for SIM_SOPT4_FTM3FLT0.
-#define BM_SIM_SOPT4_FTM3FLT0 (0x00001000U) //!< Bit mask for SIM_SOPT4_FTM3FLT0.
-#define BS_SIM_SOPT4_FTM3FLT0 (1U) //!< Bit field size in bits for SIM_SOPT4_FTM3FLT0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT4_FTM3FLT0 field.
-#define BR_SIM_SOPT4_FTM3FLT0 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3FLT0))
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT4_FTM3FLT0.
-#define BF_SIM_SOPT4_FTM3FLT0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM3FLT0), uint32_t) & BM_SIM_SOPT4_FTM3FLT0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FTM3FLT0 field to a new value.
-#define BW_SIM_SOPT4_FTM3FLT0(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3FLT0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT4, field FTM1CH0SRC[19:18] (RW)
- *
- * Selects the source for FTM1 channel 0 input capture. When the FTM is not in
- * input capture mode, clear this field.
- *
- * Values:
- * - 00 - FTM1_CH0 signal
- * - 01 - CMP0 output
- * - 10 - CMP1 output
- * - 11 - USB start of frame pulse
- */
-//@{
-#define BP_SIM_SOPT4_FTM1CH0SRC (18U) //!< Bit position for SIM_SOPT4_FTM1CH0SRC.
-#define BM_SIM_SOPT4_FTM1CH0SRC (0x000C0000U) //!< Bit mask for SIM_SOPT4_FTM1CH0SRC.
-#define BS_SIM_SOPT4_FTM1CH0SRC (2U) //!< Bit field size in bits for SIM_SOPT4_FTM1CH0SRC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT4_FTM1CH0SRC field.
-#define BR_SIM_SOPT4_FTM1CH0SRC (HW_SIM_SOPT4.B.FTM1CH0SRC)
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT4_FTM1CH0SRC.
-#define BF_SIM_SOPT4_FTM1CH0SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM1CH0SRC), uint32_t) & BM_SIM_SOPT4_FTM1CH0SRC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FTM1CH0SRC field to a new value.
-#define BW_SIM_SOPT4_FTM1CH0SRC(v) (HW_SIM_SOPT4_WR((HW_SIM_SOPT4_RD() & ~BM_SIM_SOPT4_FTM1CH0SRC) | BF_SIM_SOPT4_FTM1CH0SRC(v)))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT4, field FTM2CH0SRC[21:20] (RW)
- *
- * Selects the source for FTM2 channel 0 input capture. When the FTM is not in
- * input capture mode, clear this field.
- *
- * Values:
- * - 00 - FTM2_CH0 signal
- * - 01 - CMP0 output
- * - 10 - CMP1 output
- * - 11 - Reserved
- */
-//@{
-#define BP_SIM_SOPT4_FTM2CH0SRC (20U) //!< Bit position for SIM_SOPT4_FTM2CH0SRC.
-#define BM_SIM_SOPT4_FTM2CH0SRC (0x00300000U) //!< Bit mask for SIM_SOPT4_FTM2CH0SRC.
-#define BS_SIM_SOPT4_FTM2CH0SRC (2U) //!< Bit field size in bits for SIM_SOPT4_FTM2CH0SRC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT4_FTM2CH0SRC field.
-#define BR_SIM_SOPT4_FTM2CH0SRC (HW_SIM_SOPT4.B.FTM2CH0SRC)
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT4_FTM2CH0SRC.
-#define BF_SIM_SOPT4_FTM2CH0SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM2CH0SRC), uint32_t) & BM_SIM_SOPT4_FTM2CH0SRC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FTM2CH0SRC field to a new value.
-#define BW_SIM_SOPT4_FTM2CH0SRC(v) (HW_SIM_SOPT4_WR((HW_SIM_SOPT4_RD() & ~BM_SIM_SOPT4_FTM2CH0SRC) | BF_SIM_SOPT4_FTM2CH0SRC(v)))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT4, field FTM0CLKSEL[24] (RW)
- *
- * Selects the external pin used to drive the clock to the FTM0 module. The
- * selected pin must also be configured for the FTM external clock function through
- * the appropriate pin control register in the port control module.
- *
- * Values:
- * - 0 - FTM_CLK0 pin
- * - 1 - FTM_CLK1 pin
- */
-//@{
-#define BP_SIM_SOPT4_FTM0CLKSEL (24U) //!< Bit position for SIM_SOPT4_FTM0CLKSEL.
-#define BM_SIM_SOPT4_FTM0CLKSEL (0x01000000U) //!< Bit mask for SIM_SOPT4_FTM0CLKSEL.
-#define BS_SIM_SOPT4_FTM0CLKSEL (1U) //!< Bit field size in bits for SIM_SOPT4_FTM0CLKSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT4_FTM0CLKSEL field.
-#define BR_SIM_SOPT4_FTM0CLKSEL (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0CLKSEL))
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT4_FTM0CLKSEL.
-#define BF_SIM_SOPT4_FTM0CLKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0CLKSEL), uint32_t) & BM_SIM_SOPT4_FTM0CLKSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FTM0CLKSEL field to a new value.
-#define BW_SIM_SOPT4_FTM0CLKSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0CLKSEL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT4, field FTM1CLKSEL[25] (RW)
- *
- * Selects the external pin used to drive the clock to the FTM1 module. The
- * selected pin must also be configured for the FTM external clock function through
- * the appropriate pin control register in the port control module.
- *
- * Values:
- * - 0 - FTM_CLK0 pin
- * - 1 - FTM_CLK1 pin
- */
-//@{
-#define BP_SIM_SOPT4_FTM1CLKSEL (25U) //!< Bit position for SIM_SOPT4_FTM1CLKSEL.
-#define BM_SIM_SOPT4_FTM1CLKSEL (0x02000000U) //!< Bit mask for SIM_SOPT4_FTM1CLKSEL.
-#define BS_SIM_SOPT4_FTM1CLKSEL (1U) //!< Bit field size in bits for SIM_SOPT4_FTM1CLKSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT4_FTM1CLKSEL field.
-#define BR_SIM_SOPT4_FTM1CLKSEL (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM1CLKSEL))
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT4_FTM1CLKSEL.
-#define BF_SIM_SOPT4_FTM1CLKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM1CLKSEL), uint32_t) & BM_SIM_SOPT4_FTM1CLKSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FTM1CLKSEL field to a new value.
-#define BW_SIM_SOPT4_FTM1CLKSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM1CLKSEL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT4, field FTM2CLKSEL[26] (RW)
- *
- * Selects the external pin used to drive the clock to the FTM2 module. The
- * selected pin must also be configured for the FTM2 module external clock function
- * through the appropriate pin control register in the port control module.
- *
- * Values:
- * - 0 - FTM2 external clock driven by FTM_CLK0 pin.
- * - 1 - FTM2 external clock driven by FTM_CLK1 pin.
- */
-//@{
-#define BP_SIM_SOPT4_FTM2CLKSEL (26U) //!< Bit position for SIM_SOPT4_FTM2CLKSEL.
-#define BM_SIM_SOPT4_FTM2CLKSEL (0x04000000U) //!< Bit mask for SIM_SOPT4_FTM2CLKSEL.
-#define BS_SIM_SOPT4_FTM2CLKSEL (1U) //!< Bit field size in bits for SIM_SOPT4_FTM2CLKSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT4_FTM2CLKSEL field.
-#define BR_SIM_SOPT4_FTM2CLKSEL (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM2CLKSEL))
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT4_FTM2CLKSEL.
-#define BF_SIM_SOPT4_FTM2CLKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM2CLKSEL), uint32_t) & BM_SIM_SOPT4_FTM2CLKSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FTM2CLKSEL field to a new value.
-#define BW_SIM_SOPT4_FTM2CLKSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM2CLKSEL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT4, field FTM3CLKSEL[27] (RW)
- *
- * Selects the external pin used to drive the clock to the FTM3 module. The
- * selected pin must also be configured for the FTM3 module external clock function
- * through the appropriate pin control register in the port control module.
- *
- * Values:
- * - 0 - FTM3 external clock driven by FTM_CLK0 pin.
- * - 1 - FTM3 external clock driven by FTM_CLK1 pin.
- */
-//@{
-#define BP_SIM_SOPT4_FTM3CLKSEL (27U) //!< Bit position for SIM_SOPT4_FTM3CLKSEL.
-#define BM_SIM_SOPT4_FTM3CLKSEL (0x08000000U) //!< Bit mask for SIM_SOPT4_FTM3CLKSEL.
-#define BS_SIM_SOPT4_FTM3CLKSEL (1U) //!< Bit field size in bits for SIM_SOPT4_FTM3CLKSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT4_FTM3CLKSEL field.
-#define BR_SIM_SOPT4_FTM3CLKSEL (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3CLKSEL))
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT4_FTM3CLKSEL.
-#define BF_SIM_SOPT4_FTM3CLKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM3CLKSEL), uint32_t) & BM_SIM_SOPT4_FTM3CLKSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FTM3CLKSEL field to a new value.
-#define BW_SIM_SOPT4_FTM3CLKSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3CLKSEL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT4, field FTM0TRG0SRC[28] (RW)
- *
- * Selects the source of FTM0 hardware trigger 0.
- *
- * Values:
- * - 0 - HSCMP0 output drives FTM0 hardware trigger 0
- * - 1 - FTM1 channel match drives FTM0 hardware trigger 0
- */
-//@{
-#define BP_SIM_SOPT4_FTM0TRG0SRC (28U) //!< Bit position for SIM_SOPT4_FTM0TRG0SRC.
-#define BM_SIM_SOPT4_FTM0TRG0SRC (0x10000000U) //!< Bit mask for SIM_SOPT4_FTM0TRG0SRC.
-#define BS_SIM_SOPT4_FTM0TRG0SRC (1U) //!< Bit field size in bits for SIM_SOPT4_FTM0TRG0SRC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT4_FTM0TRG0SRC field.
-#define BR_SIM_SOPT4_FTM0TRG0SRC (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0TRG0SRC))
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT4_FTM0TRG0SRC.
-#define BF_SIM_SOPT4_FTM0TRG0SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0TRG0SRC), uint32_t) & BM_SIM_SOPT4_FTM0TRG0SRC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FTM0TRG0SRC field to a new value.
-#define BW_SIM_SOPT4_FTM0TRG0SRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0TRG0SRC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT4, field FTM0TRG1SRC[29] (RW)
- *
- * Selects the source of FTM0 hardware trigger 1.
- *
- * Values:
- * - 0 - PDB output trigger 1 drives FTM0 hardware trigger 1
- * - 1 - FTM2 channel match drives FTM0 hardware trigger 1
- */
-//@{
-#define BP_SIM_SOPT4_FTM0TRG1SRC (29U) //!< Bit position for SIM_SOPT4_FTM0TRG1SRC.
-#define BM_SIM_SOPT4_FTM0TRG1SRC (0x20000000U) //!< Bit mask for SIM_SOPT4_FTM0TRG1SRC.
-#define BS_SIM_SOPT4_FTM0TRG1SRC (1U) //!< Bit field size in bits for SIM_SOPT4_FTM0TRG1SRC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT4_FTM0TRG1SRC field.
-#define BR_SIM_SOPT4_FTM0TRG1SRC (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0TRG1SRC))
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT4_FTM0TRG1SRC.
-#define BF_SIM_SOPT4_FTM0TRG1SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0TRG1SRC), uint32_t) & BM_SIM_SOPT4_FTM0TRG1SRC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FTM0TRG1SRC field to a new value.
-#define BW_SIM_SOPT4_FTM0TRG1SRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0TRG1SRC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT4, field FTM3TRG0SRC[30] (RW)
- *
- * Selects the source of FTM3 hardware trigger 0.
- *
- * Values:
- * - 0 - Reserved
- * - 1 - FTM1 channel match drives FTM3 hardware trigger 0
- */
-//@{
-#define BP_SIM_SOPT4_FTM3TRG0SRC (30U) //!< Bit position for SIM_SOPT4_FTM3TRG0SRC.
-#define BM_SIM_SOPT4_FTM3TRG0SRC (0x40000000U) //!< Bit mask for SIM_SOPT4_FTM3TRG0SRC.
-#define BS_SIM_SOPT4_FTM3TRG0SRC (1U) //!< Bit field size in bits for SIM_SOPT4_FTM3TRG0SRC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT4_FTM3TRG0SRC field.
-#define BR_SIM_SOPT4_FTM3TRG0SRC (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3TRG0SRC))
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT4_FTM3TRG0SRC.
-#define BF_SIM_SOPT4_FTM3TRG0SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM3TRG0SRC), uint32_t) & BM_SIM_SOPT4_FTM3TRG0SRC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FTM3TRG0SRC field to a new value.
-#define BW_SIM_SOPT4_FTM3TRG0SRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3TRG0SRC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT4, field FTM3TRG1SRC[31] (RW)
- *
- * Selects the source of FTM3 hardware trigger 1.
- *
- * Values:
- * - 0 - Reserved
- * - 1 - FTM2 channel match drives FTM3 hardware trigger 1
- */
-//@{
-#define BP_SIM_SOPT4_FTM3TRG1SRC (31U) //!< Bit position for SIM_SOPT4_FTM3TRG1SRC.
-#define BM_SIM_SOPT4_FTM3TRG1SRC (0x80000000U) //!< Bit mask for SIM_SOPT4_FTM3TRG1SRC.
-#define BS_SIM_SOPT4_FTM3TRG1SRC (1U) //!< Bit field size in bits for SIM_SOPT4_FTM3TRG1SRC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT4_FTM3TRG1SRC field.
-#define BR_SIM_SOPT4_FTM3TRG1SRC (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3TRG1SRC))
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT4_FTM3TRG1SRC.
-#define BF_SIM_SOPT4_FTM3TRG1SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM3TRG1SRC), uint32_t) & BM_SIM_SOPT4_FTM3TRG1SRC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FTM3TRG1SRC field to a new value.
-#define BW_SIM_SOPT4_FTM3TRG1SRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3TRG1SRC) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SIM_SOPT5 - System Options Register 5
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SIM_SOPT5 - System Options Register 5 (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_sim_sopt5
-{
- uint32_t U;
- struct _hw_sim_sopt5_bitfields
- {
- uint32_t UART0TXSRC : 2; //!< [1:0] UART 0 transmit data source select
- uint32_t UART0RXSRC : 2; //!< [3:2] UART 0 receive data source select
- uint32_t UART1TXSRC : 2; //!< [5:4] UART 1 transmit data source select
- uint32_t UART1RXSRC : 2; //!< [7:6] UART 1 receive data source select
- uint32_t RESERVED0 : 24; //!< [31:8]
- } B;
-} hw_sim_sopt5_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SIM_SOPT5 register
- */
-//@{
-#define HW_SIM_SOPT5_ADDR (REGS_SIM_BASE + 0x1010U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SIM_SOPT5 (*(__IO hw_sim_sopt5_t *) HW_SIM_SOPT5_ADDR)
-#define HW_SIM_SOPT5_RD() (HW_SIM_SOPT5.U)
-#define HW_SIM_SOPT5_WR(v) (HW_SIM_SOPT5.U = (v))
-#define HW_SIM_SOPT5_SET(v) (HW_SIM_SOPT5_WR(HW_SIM_SOPT5_RD() | (v)))
-#define HW_SIM_SOPT5_CLR(v) (HW_SIM_SOPT5_WR(HW_SIM_SOPT5_RD() & ~(v)))
-#define HW_SIM_SOPT5_TOG(v) (HW_SIM_SOPT5_WR(HW_SIM_SOPT5_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SIM_SOPT5 bitfields
- */
-
-/*!
- * @name Register SIM_SOPT5, field UART0TXSRC[1:0] (RW)
- *
- * Selects the source for the UART 0 transmit data.
- *
- * Values:
- * - 00 - UART0_TX pin
- * - 01 - UART0_TX pin modulated with FTM1 channel 0 output
- * - 10 - UART0_TX pin modulated with FTM2 channel 0 output
- * - 11 - Reserved
- */
-//@{
-#define BP_SIM_SOPT5_UART0TXSRC (0U) //!< Bit position for SIM_SOPT5_UART0TXSRC.
-#define BM_SIM_SOPT5_UART0TXSRC (0x00000003U) //!< Bit mask for SIM_SOPT5_UART0TXSRC.
-#define BS_SIM_SOPT5_UART0TXSRC (2U) //!< Bit field size in bits for SIM_SOPT5_UART0TXSRC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT5_UART0TXSRC field.
-#define BR_SIM_SOPT5_UART0TXSRC (HW_SIM_SOPT5.B.UART0TXSRC)
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT5_UART0TXSRC.
-#define BF_SIM_SOPT5_UART0TXSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT5_UART0TXSRC), uint32_t) & BM_SIM_SOPT5_UART0TXSRC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the UART0TXSRC field to a new value.
-#define BW_SIM_SOPT5_UART0TXSRC(v) (HW_SIM_SOPT5_WR((HW_SIM_SOPT5_RD() & ~BM_SIM_SOPT5_UART0TXSRC) | BF_SIM_SOPT5_UART0TXSRC(v)))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT5, field UART0RXSRC[3:2] (RW)
- *
- * Selects the source for the UART 0 receive data.
- *
- * Values:
- * - 00 - UART0_RX pin
- * - 01 - CMP0
- * - 10 - CMP1
- * - 11 - Reserved
- */
-//@{
-#define BP_SIM_SOPT5_UART0RXSRC (2U) //!< Bit position for SIM_SOPT5_UART0RXSRC.
-#define BM_SIM_SOPT5_UART0RXSRC (0x0000000CU) //!< Bit mask for SIM_SOPT5_UART0RXSRC.
-#define BS_SIM_SOPT5_UART0RXSRC (2U) //!< Bit field size in bits for SIM_SOPT5_UART0RXSRC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT5_UART0RXSRC field.
-#define BR_SIM_SOPT5_UART0RXSRC (HW_SIM_SOPT5.B.UART0RXSRC)
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT5_UART0RXSRC.
-#define BF_SIM_SOPT5_UART0RXSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT5_UART0RXSRC), uint32_t) & BM_SIM_SOPT5_UART0RXSRC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the UART0RXSRC field to a new value.
-#define BW_SIM_SOPT5_UART0RXSRC(v) (HW_SIM_SOPT5_WR((HW_SIM_SOPT5_RD() & ~BM_SIM_SOPT5_UART0RXSRC) | BF_SIM_SOPT5_UART0RXSRC(v)))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT5, field UART1TXSRC[5:4] (RW)
- *
- * Selects the source for the UART 1 transmit data.
- *
- * Values:
- * - 00 - UART1_TX pin
- * - 01 - UART1_TX pin modulated with FTM1 channel 0 output
- * - 10 - UART1_TX pin modulated with FTM2 channel 0 output
- * - 11 - Reserved
- */
-//@{
-#define BP_SIM_SOPT5_UART1TXSRC (4U) //!< Bit position for SIM_SOPT5_UART1TXSRC.
-#define BM_SIM_SOPT5_UART1TXSRC (0x00000030U) //!< Bit mask for SIM_SOPT5_UART1TXSRC.
-#define BS_SIM_SOPT5_UART1TXSRC (2U) //!< Bit field size in bits for SIM_SOPT5_UART1TXSRC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT5_UART1TXSRC field.
-#define BR_SIM_SOPT5_UART1TXSRC (HW_SIM_SOPT5.B.UART1TXSRC)
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT5_UART1TXSRC.
-#define BF_SIM_SOPT5_UART1TXSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT5_UART1TXSRC), uint32_t) & BM_SIM_SOPT5_UART1TXSRC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the UART1TXSRC field to a new value.
-#define BW_SIM_SOPT5_UART1TXSRC(v) (HW_SIM_SOPT5_WR((HW_SIM_SOPT5_RD() & ~BM_SIM_SOPT5_UART1TXSRC) | BF_SIM_SOPT5_UART1TXSRC(v)))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT5, field UART1RXSRC[7:6] (RW)
- *
- * Selects the source for the UART 1 receive data.
- *
- * Values:
- * - 00 - UART1_RX pin
- * - 01 - CMP0
- * - 10 - CMP1
- * - 11 - Reserved
- */
-//@{
-#define BP_SIM_SOPT5_UART1RXSRC (6U) //!< Bit position for SIM_SOPT5_UART1RXSRC.
-#define BM_SIM_SOPT5_UART1RXSRC (0x000000C0U) //!< Bit mask for SIM_SOPT5_UART1RXSRC.
-#define BS_SIM_SOPT5_UART1RXSRC (2U) //!< Bit field size in bits for SIM_SOPT5_UART1RXSRC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT5_UART1RXSRC field.
-#define BR_SIM_SOPT5_UART1RXSRC (HW_SIM_SOPT5.B.UART1RXSRC)
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT5_UART1RXSRC.
-#define BF_SIM_SOPT5_UART1RXSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT5_UART1RXSRC), uint32_t) & BM_SIM_SOPT5_UART1RXSRC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the UART1RXSRC field to a new value.
-#define BW_SIM_SOPT5_UART1RXSRC(v) (HW_SIM_SOPT5_WR((HW_SIM_SOPT5_RD() & ~BM_SIM_SOPT5_UART1RXSRC) | BF_SIM_SOPT5_UART1RXSRC(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SIM_SOPT7 - System Options Register 7
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SIM_SOPT7 - System Options Register 7 (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_sim_sopt7
-{
- uint32_t U;
- struct _hw_sim_sopt7_bitfields
- {
- uint32_t ADC0TRGSEL : 4; //!< [3:0] ADC0 trigger select
- uint32_t ADC0PRETRGSEL : 1; //!< [4] ADC0 pretrigger select
- uint32_t RESERVED0 : 2; //!< [6:5]
- uint32_t ADC0ALTTRGEN : 1; //!< [7] ADC0 alternate trigger enable
- uint32_t ADC1TRGSEL : 4; //!< [11:8] ADC1 trigger select
- uint32_t ADC1PRETRGSEL : 1; //!< [12] ADC1 pre-trigger select
- uint32_t RESERVED1 : 2; //!< [14:13]
- uint32_t ADC1ALTTRGEN : 1; //!< [15] ADC1 alternate trigger enable
- uint32_t RESERVED2 : 16; //!< [31:16]
- } B;
-} hw_sim_sopt7_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SIM_SOPT7 register
- */
-//@{
-#define HW_SIM_SOPT7_ADDR (REGS_SIM_BASE + 0x1018U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SIM_SOPT7 (*(__IO hw_sim_sopt7_t *) HW_SIM_SOPT7_ADDR)
-#define HW_SIM_SOPT7_RD() (HW_SIM_SOPT7.U)
-#define HW_SIM_SOPT7_WR(v) (HW_SIM_SOPT7.U = (v))
-#define HW_SIM_SOPT7_SET(v) (HW_SIM_SOPT7_WR(HW_SIM_SOPT7_RD() | (v)))
-#define HW_SIM_SOPT7_CLR(v) (HW_SIM_SOPT7_WR(HW_SIM_SOPT7_RD() & ~(v)))
-#define HW_SIM_SOPT7_TOG(v) (HW_SIM_SOPT7_WR(HW_SIM_SOPT7_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SIM_SOPT7 bitfields
- */
-
-/*!
- * @name Register SIM_SOPT7, field ADC0TRGSEL[3:0] (RW)
- *
- * Selects the ADC0 trigger source when alternative triggers are functional in
- * stop and VLPS modes. .
- *
- * Values:
- * - 0000 - PDB external trigger pin input (PDB0_EXTRG)
- * - 0001 - High speed comparator 0 output
- * - 0010 - High speed comparator 1 output
- * - 0011 - High speed comparator 2 output
- * - 0100 - PIT trigger 0
- * - 0101 - PIT trigger 1
- * - 0110 - PIT trigger 2
- * - 0111 - PIT trigger 3
- * - 1000 - FTM0 trigger
- * - 1001 - FTM1 trigger
- * - 1010 - FTM2 trigger
- * - 1011 - FTM3 trigger
- * - 1100 - RTC alarm
- * - 1101 - RTC seconds
- * - 1110 - Low-power timer (LPTMR) trigger
- * - 1111 - Reserved
- */
-//@{
-#define BP_SIM_SOPT7_ADC0TRGSEL (0U) //!< Bit position for SIM_SOPT7_ADC0TRGSEL.
-#define BM_SIM_SOPT7_ADC0TRGSEL (0x0000000FU) //!< Bit mask for SIM_SOPT7_ADC0TRGSEL.
-#define BS_SIM_SOPT7_ADC0TRGSEL (4U) //!< Bit field size in bits for SIM_SOPT7_ADC0TRGSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT7_ADC0TRGSEL field.
-#define BR_SIM_SOPT7_ADC0TRGSEL (HW_SIM_SOPT7.B.ADC0TRGSEL)
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT7_ADC0TRGSEL.
-#define BF_SIM_SOPT7_ADC0TRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC0TRGSEL), uint32_t) & BM_SIM_SOPT7_ADC0TRGSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ADC0TRGSEL field to a new value.
-#define BW_SIM_SOPT7_ADC0TRGSEL(v) (HW_SIM_SOPT7_WR((HW_SIM_SOPT7_RD() & ~BM_SIM_SOPT7_ADC0TRGSEL) | BF_SIM_SOPT7_ADC0TRGSEL(v)))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT7, field ADC0PRETRGSEL[4] (RW)
- *
- * Selects the ADC0 pre-trigger source when alternative triggers are enabled
- * through ADC0ALTTRGEN.
- *
- * Values:
- * - 0 - Pre-trigger A
- * - 1 - Pre-trigger B
- */
-//@{
-#define BP_SIM_SOPT7_ADC0PRETRGSEL (4U) //!< Bit position for SIM_SOPT7_ADC0PRETRGSEL.
-#define BM_SIM_SOPT7_ADC0PRETRGSEL (0x00000010U) //!< Bit mask for SIM_SOPT7_ADC0PRETRGSEL.
-#define BS_SIM_SOPT7_ADC0PRETRGSEL (1U) //!< Bit field size in bits for SIM_SOPT7_ADC0PRETRGSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT7_ADC0PRETRGSEL field.
-#define BR_SIM_SOPT7_ADC0PRETRGSEL (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC0PRETRGSEL))
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT7_ADC0PRETRGSEL.
-#define BF_SIM_SOPT7_ADC0PRETRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC0PRETRGSEL), uint32_t) & BM_SIM_SOPT7_ADC0PRETRGSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ADC0PRETRGSEL field to a new value.
-#define BW_SIM_SOPT7_ADC0PRETRGSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC0PRETRGSEL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT7, field ADC0ALTTRGEN[7] (RW)
- *
- * Enable alternative conversion triggers for ADC0.
- *
- * Values:
- * - 0 - PDB trigger selected for ADC0.
- * - 1 - Alternate trigger selected for ADC0.
- */
-//@{
-#define BP_SIM_SOPT7_ADC0ALTTRGEN (7U) //!< Bit position for SIM_SOPT7_ADC0ALTTRGEN.
-#define BM_SIM_SOPT7_ADC0ALTTRGEN (0x00000080U) //!< Bit mask for SIM_SOPT7_ADC0ALTTRGEN.
-#define BS_SIM_SOPT7_ADC0ALTTRGEN (1U) //!< Bit field size in bits for SIM_SOPT7_ADC0ALTTRGEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT7_ADC0ALTTRGEN field.
-#define BR_SIM_SOPT7_ADC0ALTTRGEN (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC0ALTTRGEN))
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT7_ADC0ALTTRGEN.
-#define BF_SIM_SOPT7_ADC0ALTTRGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC0ALTTRGEN), uint32_t) & BM_SIM_SOPT7_ADC0ALTTRGEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ADC0ALTTRGEN field to a new value.
-#define BW_SIM_SOPT7_ADC0ALTTRGEN(v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC0ALTTRGEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT7, field ADC1TRGSEL[11:8] (RW)
- *
- * Selects the ADC1 trigger source when alternative triggers are functional in
- * stop and VLPS modes.
- *
- * Values:
- * - 0000 - PDB external trigger pin input (PDB0_EXTRG)
- * - 0001 - High speed comparator 0 output
- * - 0010 - High speed comparator 1 output
- * - 0011 - High speed comparator 2 output
- * - 0100 - PIT trigger 0
- * - 0101 - PIT trigger 1
- * - 0110 - PIT trigger 2
- * - 0111 - PIT trigger 3
- * - 1000 - FTM0 trigger
- * - 1001 - FTM1 trigger
- * - 1010 - FTM2 trigger
- * - 1011 - FTM3 trigger
- * - 1100 - RTC alarm
- * - 1101 - RTC seconds
- * - 1110 - Low-power timer (LPTMR) trigger
- * - 1111 - Reserved
- */
-//@{
-#define BP_SIM_SOPT7_ADC1TRGSEL (8U) //!< Bit position for SIM_SOPT7_ADC1TRGSEL.
-#define BM_SIM_SOPT7_ADC1TRGSEL (0x00000F00U) //!< Bit mask for SIM_SOPT7_ADC1TRGSEL.
-#define BS_SIM_SOPT7_ADC1TRGSEL (4U) //!< Bit field size in bits for SIM_SOPT7_ADC1TRGSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT7_ADC1TRGSEL field.
-#define BR_SIM_SOPT7_ADC1TRGSEL (HW_SIM_SOPT7.B.ADC1TRGSEL)
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT7_ADC1TRGSEL.
-#define BF_SIM_SOPT7_ADC1TRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC1TRGSEL), uint32_t) & BM_SIM_SOPT7_ADC1TRGSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ADC1TRGSEL field to a new value.
-#define BW_SIM_SOPT7_ADC1TRGSEL(v) (HW_SIM_SOPT7_WR((HW_SIM_SOPT7_RD() & ~BM_SIM_SOPT7_ADC1TRGSEL) | BF_SIM_SOPT7_ADC1TRGSEL(v)))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT7, field ADC1PRETRGSEL[12] (RW)
- *
- * Selects the ADC1 pre-trigger source when alternative triggers are enabled
- * through ADC1ALTTRGEN.
- *
- * Values:
- * - 0 - Pre-trigger A selected for ADC1.
- * - 1 - Pre-trigger B selected for ADC1.
- */
-//@{
-#define BP_SIM_SOPT7_ADC1PRETRGSEL (12U) //!< Bit position for SIM_SOPT7_ADC1PRETRGSEL.
-#define BM_SIM_SOPT7_ADC1PRETRGSEL (0x00001000U) //!< Bit mask for SIM_SOPT7_ADC1PRETRGSEL.
-#define BS_SIM_SOPT7_ADC1PRETRGSEL (1U) //!< Bit field size in bits for SIM_SOPT7_ADC1PRETRGSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT7_ADC1PRETRGSEL field.
-#define BR_SIM_SOPT7_ADC1PRETRGSEL (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC1PRETRGSEL))
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT7_ADC1PRETRGSEL.
-#define BF_SIM_SOPT7_ADC1PRETRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC1PRETRGSEL), uint32_t) & BM_SIM_SOPT7_ADC1PRETRGSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ADC1PRETRGSEL field to a new value.
-#define BW_SIM_SOPT7_ADC1PRETRGSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC1PRETRGSEL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SOPT7, field ADC1ALTTRGEN[15] (RW)
- *
- * Enable alternative conversion triggers for ADC1.
- *
- * Values:
- * - 0 - PDB trigger selected for ADC1
- * - 1 - Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.
- */
-//@{
-#define BP_SIM_SOPT7_ADC1ALTTRGEN (15U) //!< Bit position for SIM_SOPT7_ADC1ALTTRGEN.
-#define BM_SIM_SOPT7_ADC1ALTTRGEN (0x00008000U) //!< Bit mask for SIM_SOPT7_ADC1ALTTRGEN.
-#define BS_SIM_SOPT7_ADC1ALTTRGEN (1U) //!< Bit field size in bits for SIM_SOPT7_ADC1ALTTRGEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SOPT7_ADC1ALTTRGEN field.
-#define BR_SIM_SOPT7_ADC1ALTTRGEN (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC1ALTTRGEN))
-#endif
-
-//! @brief Format value for bitfield SIM_SOPT7_ADC1ALTTRGEN.
-#define BF_SIM_SOPT7_ADC1ALTTRGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC1ALTTRGEN), uint32_t) & BM_SIM_SOPT7_ADC1ALTTRGEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ADC1ALTTRGEN field to a new value.
-#define BW_SIM_SOPT7_ADC1ALTTRGEN(v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC1ALTTRGEN) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SIM_SDID - System Device Identification Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SIM_SDID - System Device Identification Register (RO)
- *
- * Reset value: 0x00000380U
- */
-typedef union _hw_sim_sdid
-{
- uint32_t U;
- struct _hw_sim_sdid_bitfields
- {
- uint32_t PINID : 4; //!< [3:0] Pincount identification
- uint32_t FAMID : 3; //!< [6:4] Kinetis family identification
- uint32_t DIEID : 5; //!< [11:7] Device Die ID
- uint32_t REVID : 4; //!< [15:12] Device revision number
- uint32_t RESERVED0 : 4; //!< [19:16]
- uint32_t SERIESID : 4; //!< [23:20] Kinetis Series ID
- uint32_t SUBFAMID : 4; //!< [27:24] Kinetis Sub-Family ID
- uint32_t FAMILYID : 4; //!< [31:28] Kinetis Family ID
- } B;
-} hw_sim_sdid_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SIM_SDID register
- */
-//@{
-#define HW_SIM_SDID_ADDR (REGS_SIM_BASE + 0x1024U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SIM_SDID (*(__I hw_sim_sdid_t *) HW_SIM_SDID_ADDR)
-#define HW_SIM_SDID_RD() (HW_SIM_SDID.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual SIM_SDID bitfields
- */
-
-/*!
- * @name Register SIM_SDID, field PINID[3:0] (RO)
- *
- * Specifies the pincount of the device.
- *
- * Values:
- * - 0000 - Reserved
- * - 0001 - Reserved
- * - 0010 - 32-pin
- * - 0011 - Reserved
- * - 0100 - 48-pin
- * - 0101 - 64-pin
- * - 0110 - 80-pin
- * - 0111 - 81-pin or 121-pin
- * - 1000 - 100-pin
- * - 1001 - 121-pin
- * - 1010 - 144-pin
- * - 1011 - Custom pinout (WLCSP)
- * - 1100 - 169-pin
- * - 1101 - Reserved
- * - 1110 - 256-pin
- * - 1111 - Reserved
- */
-//@{
-#define BP_SIM_SDID_PINID (0U) //!< Bit position for SIM_SDID_PINID.
-#define BM_SIM_SDID_PINID (0x0000000FU) //!< Bit mask for SIM_SDID_PINID.
-#define BS_SIM_SDID_PINID (4U) //!< Bit field size in bits for SIM_SDID_PINID.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SDID_PINID field.
-#define BR_SIM_SDID_PINID (HW_SIM_SDID.B.PINID)
-#endif
-//@}
-
-/*!
- * @name Register SIM_SDID, field FAMID[6:4] (RO)
- *
- * This field is maintained for compatibility only, but has been superceded by
- * the SERIESID, FAMILYID and SUBFAMID fields in this register.
- *
- * Values:
- * - 000 - K1x Family (without tamper)
- * - 001 - K2x Family (without tamper)
- * - 010 - K3x Family or K1x/K6x Family (with tamper)
- * - 011 - K4x Family or K2x Family (with tamper)
- * - 100 - K6x Family (without tamper)
- * - 101 - K7x Family
- * - 110 - Reserved
- * - 111 - Reserved
- */
-//@{
-#define BP_SIM_SDID_FAMID (4U) //!< Bit position for SIM_SDID_FAMID.
-#define BM_SIM_SDID_FAMID (0x00000070U) //!< Bit mask for SIM_SDID_FAMID.
-#define BS_SIM_SDID_FAMID (3U) //!< Bit field size in bits for SIM_SDID_FAMID.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SDID_FAMID field.
-#define BR_SIM_SDID_FAMID (HW_SIM_SDID.B.FAMID)
-#endif
-//@}
-
-/*!
- * @name Register SIM_SDID, field DIEID[11:7] (RO)
- *
- * Specifies the silicon feature set identication number for the device.
- */
-//@{
-#define BP_SIM_SDID_DIEID (7U) //!< Bit position for SIM_SDID_DIEID.
-#define BM_SIM_SDID_DIEID (0x00000F80U) //!< Bit mask for SIM_SDID_DIEID.
-#define BS_SIM_SDID_DIEID (5U) //!< Bit field size in bits for SIM_SDID_DIEID.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SDID_DIEID field.
-#define BR_SIM_SDID_DIEID (HW_SIM_SDID.B.DIEID)
-#endif
-//@}
-
-/*!
- * @name Register SIM_SDID, field REVID[15:12] (RO)
- *
- * Specifies the silicon implementation number for the device.
- */
-//@{
-#define BP_SIM_SDID_REVID (12U) //!< Bit position for SIM_SDID_REVID.
-#define BM_SIM_SDID_REVID (0x0000F000U) //!< Bit mask for SIM_SDID_REVID.
-#define BS_SIM_SDID_REVID (4U) //!< Bit field size in bits for SIM_SDID_REVID.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SDID_REVID field.
-#define BR_SIM_SDID_REVID (HW_SIM_SDID.B.REVID)
-#endif
-//@}
-
-/*!
- * @name Register SIM_SDID, field SERIESID[23:20] (RO)
- *
- * Specifies the Kinetis series of the device.
- *
- * Values:
- * - 0000 - Kinetis K series
- * - 0001 - Kinetis L series
- * - 0101 - Kinetis W series
- * - 0110 - Kinetis V series
- */
-//@{
-#define BP_SIM_SDID_SERIESID (20U) //!< Bit position for SIM_SDID_SERIESID.
-#define BM_SIM_SDID_SERIESID (0x00F00000U) //!< Bit mask for SIM_SDID_SERIESID.
-#define BS_SIM_SDID_SERIESID (4U) //!< Bit field size in bits for SIM_SDID_SERIESID.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SDID_SERIESID field.
-#define BR_SIM_SDID_SERIESID (HW_SIM_SDID.B.SERIESID)
-#endif
-//@}
-
-/*!
- * @name Register SIM_SDID, field SUBFAMID[27:24] (RO)
- *
- * Specifies the Kinetis sub-family of the device.
- *
- * Values:
- * - 0000 - Kx0 Subfamily
- * - 0001 - Kx1 Subfamily (tamper detect)
- * - 0010 - Kx2 Subfamily
- * - 0011 - Kx3 Subfamily (tamper detect)
- * - 0100 - Kx4 Subfamily
- * - 0101 - Kx5 Subfamily (tamper detect)
- * - 0110 - Kx6 Subfamily
- */
-//@{
-#define BP_SIM_SDID_SUBFAMID (24U) //!< Bit position for SIM_SDID_SUBFAMID.
-#define BM_SIM_SDID_SUBFAMID (0x0F000000U) //!< Bit mask for SIM_SDID_SUBFAMID.
-#define BS_SIM_SDID_SUBFAMID (4U) //!< Bit field size in bits for SIM_SDID_SUBFAMID.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SDID_SUBFAMID field.
-#define BR_SIM_SDID_SUBFAMID (HW_SIM_SDID.B.SUBFAMID)
-#endif
-//@}
-
-/*!
- * @name Register SIM_SDID, field FAMILYID[31:28] (RO)
- *
- * Specifies the Kinetis family of the device.
- *
- * Values:
- * - 0001 - K1x Family
- * - 0010 - K2x Family
- * - 0011 - K3x Family
- * - 0100 - K4x Family
- * - 0110 - K6x Family
- * - 0111 - K7x Family
- */
-//@{
-#define BP_SIM_SDID_FAMILYID (28U) //!< Bit position for SIM_SDID_FAMILYID.
-#define BM_SIM_SDID_FAMILYID (0xF0000000U) //!< Bit mask for SIM_SDID_FAMILYID.
-#define BS_SIM_SDID_FAMILYID (4U) //!< Bit field size in bits for SIM_SDID_FAMILYID.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SDID_FAMILYID field.
-#define BR_SIM_SDID_FAMILYID (HW_SIM_SDID.B.FAMILYID)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SIM_SCGC1 - System Clock Gating Control Register 1
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SIM_SCGC1 - System Clock Gating Control Register 1 (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_sim_scgc1
-{
- uint32_t U;
- struct _hw_sim_scgc1_bitfields
- {
- uint32_t RESERVED0 : 6; //!< [5:0]
- uint32_t I2C2b : 1; //!< [6] I2C2 Clock Gate Control
- uint32_t RESERVED1 : 3; //!< [9:7]
- uint32_t UART4b : 1; //!< [10] UART4 Clock Gate Control
- uint32_t UART5b : 1; //!< [11] UART5 Clock Gate Control
- uint32_t RESERVED2 : 20; //!< [31:12]
- } B;
-} hw_sim_scgc1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SIM_SCGC1 register
- */
-//@{
-#define HW_SIM_SCGC1_ADDR (REGS_SIM_BASE + 0x1028U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SIM_SCGC1 (*(__IO hw_sim_scgc1_t *) HW_SIM_SCGC1_ADDR)
-#define HW_SIM_SCGC1_RD() (HW_SIM_SCGC1.U)
-#define HW_SIM_SCGC1_WR(v) (HW_SIM_SCGC1.U = (v))
-#define HW_SIM_SCGC1_SET(v) (HW_SIM_SCGC1_WR(HW_SIM_SCGC1_RD() | (v)))
-#define HW_SIM_SCGC1_CLR(v) (HW_SIM_SCGC1_WR(HW_SIM_SCGC1_RD() & ~(v)))
-#define HW_SIM_SCGC1_TOG(v) (HW_SIM_SCGC1_WR(HW_SIM_SCGC1_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SIM_SCGC1 bitfields
- */
-
-/*!
- * @name Register SIM_SCGC1, field I2C2[6] (RW)
- *
- * This bit controls the clock gate to the I2C2 module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC1_I2C2 (6U) //!< Bit position for SIM_SCGC1_I2C2.
-#define BM_SIM_SCGC1_I2C2 (0x00000040U) //!< Bit mask for SIM_SCGC1_I2C2.
-#define BS_SIM_SCGC1_I2C2 (1U) //!< Bit field size in bits for SIM_SCGC1_I2C2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC1_I2C2 field.
-#define BR_SIM_SCGC1_I2C2 (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_I2C2))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC1_I2C2.
-#define BF_SIM_SCGC1_I2C2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC1_I2C2), uint32_t) & BM_SIM_SCGC1_I2C2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the I2C2 field to a new value.
-#define BW_SIM_SCGC1_I2C2(v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_I2C2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC1, field UART4[10] (RW)
- *
- * This bit controls the clock gate to the UART4 module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC1_UART4 (10U) //!< Bit position for SIM_SCGC1_UART4.
-#define BM_SIM_SCGC1_UART4 (0x00000400U) //!< Bit mask for SIM_SCGC1_UART4.
-#define BS_SIM_SCGC1_UART4 (1U) //!< Bit field size in bits for SIM_SCGC1_UART4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC1_UART4 field.
-#define BR_SIM_SCGC1_UART4 (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_UART4))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC1_UART4.
-#define BF_SIM_SCGC1_UART4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC1_UART4), uint32_t) & BM_SIM_SCGC1_UART4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the UART4 field to a new value.
-#define BW_SIM_SCGC1_UART4(v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_UART4) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC1, field UART5[11] (RW)
- *
- * This bit controls the clock gate to the UART5 module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC1_UART5 (11U) //!< Bit position for SIM_SCGC1_UART5.
-#define BM_SIM_SCGC1_UART5 (0x00000800U) //!< Bit mask for SIM_SCGC1_UART5.
-#define BS_SIM_SCGC1_UART5 (1U) //!< Bit field size in bits for SIM_SCGC1_UART5.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC1_UART5 field.
-#define BR_SIM_SCGC1_UART5 (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_UART5))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC1_UART5.
-#define BF_SIM_SCGC1_UART5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC1_UART5), uint32_t) & BM_SIM_SCGC1_UART5)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the UART5 field to a new value.
-#define BW_SIM_SCGC1_UART5(v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_UART5) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SIM_SCGC2 - System Clock Gating Control Register 2
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SIM_SCGC2 - System Clock Gating Control Register 2 (RW)
- *
- * Reset value: 0x00000000U
- *
- * DAC0 can be accessed through both AIPS0 and AIPS1. When accessing through
- * AIPS1, define the clock gate control bits in the SCGC2. When accessing through
- * AIPS0, define the clock gate control bits in SCGC6.
- */
-typedef union _hw_sim_scgc2
-{
- uint32_t U;
- struct _hw_sim_scgc2_bitfields
- {
- uint32_t ENETb : 1; //!< [0] ENET Clock Gate Control
- uint32_t RESERVED0 : 11; //!< [11:1]
- uint32_t DAC0b : 1; //!< [12] DAC0 Clock Gate Control
- uint32_t DAC1b : 1; //!< [13] DAC1 Clock Gate Control
- uint32_t RESERVED1 : 18; //!< [31:14]
- } B;
-} hw_sim_scgc2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SIM_SCGC2 register
- */
-//@{
-#define HW_SIM_SCGC2_ADDR (REGS_SIM_BASE + 0x102CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SIM_SCGC2 (*(__IO hw_sim_scgc2_t *) HW_SIM_SCGC2_ADDR)
-#define HW_SIM_SCGC2_RD() (HW_SIM_SCGC2.U)
-#define HW_SIM_SCGC2_WR(v) (HW_SIM_SCGC2.U = (v))
-#define HW_SIM_SCGC2_SET(v) (HW_SIM_SCGC2_WR(HW_SIM_SCGC2_RD() | (v)))
-#define HW_SIM_SCGC2_CLR(v) (HW_SIM_SCGC2_WR(HW_SIM_SCGC2_RD() & ~(v)))
-#define HW_SIM_SCGC2_TOG(v) (HW_SIM_SCGC2_WR(HW_SIM_SCGC2_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SIM_SCGC2 bitfields
- */
-
-/*!
- * @name Register SIM_SCGC2, field ENET[0] (RW)
- *
- * This bit controls the clock gate to the ENET module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC2_ENET (0U) //!< Bit position for SIM_SCGC2_ENET.
-#define BM_SIM_SCGC2_ENET (0x00000001U) //!< Bit mask for SIM_SCGC2_ENET.
-#define BS_SIM_SCGC2_ENET (1U) //!< Bit field size in bits for SIM_SCGC2_ENET.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC2_ENET field.
-#define BR_SIM_SCGC2_ENET (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_ENET))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC2_ENET.
-#define BF_SIM_SCGC2_ENET(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC2_ENET), uint32_t) & BM_SIM_SCGC2_ENET)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ENET field to a new value.
-#define BW_SIM_SCGC2_ENET(v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_ENET) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC2, field DAC0[12] (RW)
- *
- * This bit controls the clock gate to the DAC0 module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC2_DAC0 (12U) //!< Bit position for SIM_SCGC2_DAC0.
-#define BM_SIM_SCGC2_DAC0 (0x00001000U) //!< Bit mask for SIM_SCGC2_DAC0.
-#define BS_SIM_SCGC2_DAC0 (1U) //!< Bit field size in bits for SIM_SCGC2_DAC0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC2_DAC0 field.
-#define BR_SIM_SCGC2_DAC0 (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_DAC0))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC2_DAC0.
-#define BF_SIM_SCGC2_DAC0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC2_DAC0), uint32_t) & BM_SIM_SCGC2_DAC0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DAC0 field to a new value.
-#define BW_SIM_SCGC2_DAC0(v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_DAC0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC2, field DAC1[13] (RW)
- *
- * This bit controls the clock gate to the DAC1 module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC2_DAC1 (13U) //!< Bit position for SIM_SCGC2_DAC1.
-#define BM_SIM_SCGC2_DAC1 (0x00002000U) //!< Bit mask for SIM_SCGC2_DAC1.
-#define BS_SIM_SCGC2_DAC1 (1U) //!< Bit field size in bits for SIM_SCGC2_DAC1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC2_DAC1 field.
-#define BR_SIM_SCGC2_DAC1 (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_DAC1))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC2_DAC1.
-#define BF_SIM_SCGC2_DAC1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC2_DAC1), uint32_t) & BM_SIM_SCGC2_DAC1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DAC1 field to a new value.
-#define BW_SIM_SCGC2_DAC1(v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_DAC1) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SIM_SCGC3 - System Clock Gating Control Register 3
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SIM_SCGC3 - System Clock Gating Control Register 3 (RW)
- *
- * Reset value: 0x00000000U
- *
- * FTM2 and RNGA can be accessed through both AIPS0 and AIPS1. When accessing
- * through AIPS1, define the clock gate control bits in the SCGC3. When accessing
- * through AIPS0, define the clock gate control bits in SCGC6.
- */
-typedef union _hw_sim_scgc3
-{
- uint32_t U;
- struct _hw_sim_scgc3_bitfields
- {
- uint32_t RNGA : 1; //!< [0] RNGA Clock Gate Control
- uint32_t RESERVED0 : 11; //!< [11:1]
- uint32_t SPI2b : 1; //!< [12] SPI2 Clock Gate Control
- uint32_t RESERVED1 : 4; //!< [16:13]
- uint32_t SDHCb : 1; //!< [17] SDHC Clock Gate Control
- uint32_t RESERVED2 : 6; //!< [23:18]
- uint32_t FTM2b : 1; //!< [24] FTM2 Clock Gate Control
- uint32_t FTM3b : 1; //!< [25] FTM3 Clock Gate Control
- uint32_t RESERVED3 : 1; //!< [26]
- uint32_t ADC1b : 1; //!< [27] ADC1 Clock Gate Control
- uint32_t RESERVED4 : 4; //!< [31:28]
- } B;
-} hw_sim_scgc3_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SIM_SCGC3 register
- */
-//@{
-#define HW_SIM_SCGC3_ADDR (REGS_SIM_BASE + 0x1030U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SIM_SCGC3 (*(__IO hw_sim_scgc3_t *) HW_SIM_SCGC3_ADDR)
-#define HW_SIM_SCGC3_RD() (HW_SIM_SCGC3.U)
-#define HW_SIM_SCGC3_WR(v) (HW_SIM_SCGC3.U = (v))
-#define HW_SIM_SCGC3_SET(v) (HW_SIM_SCGC3_WR(HW_SIM_SCGC3_RD() | (v)))
-#define HW_SIM_SCGC3_CLR(v) (HW_SIM_SCGC3_WR(HW_SIM_SCGC3_RD() & ~(v)))
-#define HW_SIM_SCGC3_TOG(v) (HW_SIM_SCGC3_WR(HW_SIM_SCGC3_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SIM_SCGC3 bitfields
- */
-
-/*!
- * @name Register SIM_SCGC3, field RNGA[0] (RW)
- *
- * This bit controls the clock gate to the RNGA module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC3_RNGA (0U) //!< Bit position for SIM_SCGC3_RNGA.
-#define BM_SIM_SCGC3_RNGA (0x00000001U) //!< Bit mask for SIM_SCGC3_RNGA.
-#define BS_SIM_SCGC3_RNGA (1U) //!< Bit field size in bits for SIM_SCGC3_RNGA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC3_RNGA field.
-#define BR_SIM_SCGC3_RNGA (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_RNGA))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC3_RNGA.
-#define BF_SIM_SCGC3_RNGA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_RNGA), uint32_t) & BM_SIM_SCGC3_RNGA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RNGA field to a new value.
-#define BW_SIM_SCGC3_RNGA(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_RNGA) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC3, field SPI2[12] (RW)
- *
- * This bit controls the clock gate to the SPI2 module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC3_SPI2 (12U) //!< Bit position for SIM_SCGC3_SPI2.
-#define BM_SIM_SCGC3_SPI2 (0x00001000U) //!< Bit mask for SIM_SCGC3_SPI2.
-#define BS_SIM_SCGC3_SPI2 (1U) //!< Bit field size in bits for SIM_SCGC3_SPI2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC3_SPI2 field.
-#define BR_SIM_SCGC3_SPI2 (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_SPI2))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC3_SPI2.
-#define BF_SIM_SCGC3_SPI2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_SPI2), uint32_t) & BM_SIM_SCGC3_SPI2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SPI2 field to a new value.
-#define BW_SIM_SCGC3_SPI2(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_SPI2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC3, field SDHC[17] (RW)
- *
- * This bit controls the clock gate to the SDHC module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC3_SDHC (17U) //!< Bit position for SIM_SCGC3_SDHC.
-#define BM_SIM_SCGC3_SDHC (0x00020000U) //!< Bit mask for SIM_SCGC3_SDHC.
-#define BS_SIM_SCGC3_SDHC (1U) //!< Bit field size in bits for SIM_SCGC3_SDHC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC3_SDHC field.
-#define BR_SIM_SCGC3_SDHC (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_SDHC))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC3_SDHC.
-#define BF_SIM_SCGC3_SDHC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_SDHC), uint32_t) & BM_SIM_SCGC3_SDHC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SDHC field to a new value.
-#define BW_SIM_SCGC3_SDHC(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_SDHC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC3, field FTM2[24] (RW)
- *
- * This bit controls the clock gate to the FTM2 module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC3_FTM2 (24U) //!< Bit position for SIM_SCGC3_FTM2.
-#define BM_SIM_SCGC3_FTM2 (0x01000000U) //!< Bit mask for SIM_SCGC3_FTM2.
-#define BS_SIM_SCGC3_FTM2 (1U) //!< Bit field size in bits for SIM_SCGC3_FTM2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC3_FTM2 field.
-#define BR_SIM_SCGC3_FTM2 (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_FTM2))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC3_FTM2.
-#define BF_SIM_SCGC3_FTM2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_FTM2), uint32_t) & BM_SIM_SCGC3_FTM2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FTM2 field to a new value.
-#define BW_SIM_SCGC3_FTM2(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_FTM2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC3, field FTM3[25] (RW)
- *
- * This bit controls the clock gate to the FTM3 module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC3_FTM3 (25U) //!< Bit position for SIM_SCGC3_FTM3.
-#define BM_SIM_SCGC3_FTM3 (0x02000000U) //!< Bit mask for SIM_SCGC3_FTM3.
-#define BS_SIM_SCGC3_FTM3 (1U) //!< Bit field size in bits for SIM_SCGC3_FTM3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC3_FTM3 field.
-#define BR_SIM_SCGC3_FTM3 (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_FTM3))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC3_FTM3.
-#define BF_SIM_SCGC3_FTM3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_FTM3), uint32_t) & BM_SIM_SCGC3_FTM3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FTM3 field to a new value.
-#define BW_SIM_SCGC3_FTM3(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_FTM3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC3, field ADC1[27] (RW)
- *
- * This bit controls the clock gate to the ADC1 module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC3_ADC1 (27U) //!< Bit position for SIM_SCGC3_ADC1.
-#define BM_SIM_SCGC3_ADC1 (0x08000000U) //!< Bit mask for SIM_SCGC3_ADC1.
-#define BS_SIM_SCGC3_ADC1 (1U) //!< Bit field size in bits for SIM_SCGC3_ADC1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC3_ADC1 field.
-#define BR_SIM_SCGC3_ADC1 (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_ADC1))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC3_ADC1.
-#define BF_SIM_SCGC3_ADC1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_ADC1), uint32_t) & BM_SIM_SCGC3_ADC1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ADC1 field to a new value.
-#define BW_SIM_SCGC3_ADC1(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_ADC1) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SIM_SCGC4 - System Clock Gating Control Register 4
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SIM_SCGC4 - System Clock Gating Control Register 4 (RW)
- *
- * Reset value: 0xF0100030U
- */
-typedef union _hw_sim_scgc4
-{
- uint32_t U;
- struct _hw_sim_scgc4_bitfields
- {
- uint32_t RESERVED0 : 1; //!< [0]
- uint32_t EWMb : 1; //!< [1] EWM Clock Gate Control
- uint32_t CMTb : 1; //!< [2] CMT Clock Gate Control
- uint32_t RESERVED1 : 3; //!< [5:3]
- uint32_t I2C0b : 1; //!< [6] I2C0 Clock Gate Control
- uint32_t I2C1b : 1; //!< [7] I2C1 Clock Gate Control
- uint32_t RESERVED2 : 2; //!< [9:8]
- uint32_t UART0b : 1; //!< [10] UART0 Clock Gate Control
- uint32_t UART1b : 1; //!< [11] UART1 Clock Gate Control
- uint32_t UART2b : 1; //!< [12] UART2 Clock Gate Control
- uint32_t UART3b : 1; //!< [13] UART3 Clock Gate Control
- uint32_t RESERVED3 : 4; //!< [17:14]
- uint32_t USBOTG : 1; //!< [18] USB Clock Gate Control
- uint32_t CMP : 1; //!< [19] Comparator Clock Gate Control
- uint32_t VREFb : 1; //!< [20] VREF Clock Gate Control
- uint32_t RESERVED4 : 11; //!< [31:21]
- } B;
-} hw_sim_scgc4_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SIM_SCGC4 register
- */
-//@{
-#define HW_SIM_SCGC4_ADDR (REGS_SIM_BASE + 0x1034U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SIM_SCGC4 (*(__IO hw_sim_scgc4_t *) HW_SIM_SCGC4_ADDR)
-#define HW_SIM_SCGC4_RD() (HW_SIM_SCGC4.U)
-#define HW_SIM_SCGC4_WR(v) (HW_SIM_SCGC4.U = (v))
-#define HW_SIM_SCGC4_SET(v) (HW_SIM_SCGC4_WR(HW_SIM_SCGC4_RD() | (v)))
-#define HW_SIM_SCGC4_CLR(v) (HW_SIM_SCGC4_WR(HW_SIM_SCGC4_RD() & ~(v)))
-#define HW_SIM_SCGC4_TOG(v) (HW_SIM_SCGC4_WR(HW_SIM_SCGC4_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SIM_SCGC4 bitfields
- */
-
-/*!
- * @name Register SIM_SCGC4, field EWM[1] (RW)
- *
- * This bit controls the clock gate to the EWM module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC4_EWM (1U) //!< Bit position for SIM_SCGC4_EWM.
-#define BM_SIM_SCGC4_EWM (0x00000002U) //!< Bit mask for SIM_SCGC4_EWM.
-#define BS_SIM_SCGC4_EWM (1U) //!< Bit field size in bits for SIM_SCGC4_EWM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC4_EWM field.
-#define BR_SIM_SCGC4_EWM (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_EWM))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC4_EWM.
-#define BF_SIM_SCGC4_EWM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_EWM), uint32_t) & BM_SIM_SCGC4_EWM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EWM field to a new value.
-#define BW_SIM_SCGC4_EWM(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_EWM) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC4, field CMT[2] (RW)
- *
- * This bit controls the clock gate to the CMT module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC4_CMT (2U) //!< Bit position for SIM_SCGC4_CMT.
-#define BM_SIM_SCGC4_CMT (0x00000004U) //!< Bit mask for SIM_SCGC4_CMT.
-#define BS_SIM_SCGC4_CMT (1U) //!< Bit field size in bits for SIM_SCGC4_CMT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC4_CMT field.
-#define BR_SIM_SCGC4_CMT (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_CMT))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC4_CMT.
-#define BF_SIM_SCGC4_CMT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_CMT), uint32_t) & BM_SIM_SCGC4_CMT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CMT field to a new value.
-#define BW_SIM_SCGC4_CMT(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_CMT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC4, field I2C0[6] (RW)
- *
- * This bit controls the clock gate to the I 2 C0 module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC4_I2C0 (6U) //!< Bit position for SIM_SCGC4_I2C0.
-#define BM_SIM_SCGC4_I2C0 (0x00000040U) //!< Bit mask for SIM_SCGC4_I2C0.
-#define BS_SIM_SCGC4_I2C0 (1U) //!< Bit field size in bits for SIM_SCGC4_I2C0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC4_I2C0 field.
-#define BR_SIM_SCGC4_I2C0 (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_I2C0))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC4_I2C0.
-#define BF_SIM_SCGC4_I2C0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_I2C0), uint32_t) & BM_SIM_SCGC4_I2C0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the I2C0 field to a new value.
-#define BW_SIM_SCGC4_I2C0(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_I2C0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC4, field I2C1[7] (RW)
- *
- * This bit controls the clock gate to the I 2 C1 module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC4_I2C1 (7U) //!< Bit position for SIM_SCGC4_I2C1.
-#define BM_SIM_SCGC4_I2C1 (0x00000080U) //!< Bit mask for SIM_SCGC4_I2C1.
-#define BS_SIM_SCGC4_I2C1 (1U) //!< Bit field size in bits for SIM_SCGC4_I2C1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC4_I2C1 field.
-#define BR_SIM_SCGC4_I2C1 (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_I2C1))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC4_I2C1.
-#define BF_SIM_SCGC4_I2C1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_I2C1), uint32_t) & BM_SIM_SCGC4_I2C1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the I2C1 field to a new value.
-#define BW_SIM_SCGC4_I2C1(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_I2C1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC4, field UART0[10] (RW)
- *
- * This bit controls the clock gate to the UART0 module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC4_UART0 (10U) //!< Bit position for SIM_SCGC4_UART0.
-#define BM_SIM_SCGC4_UART0 (0x00000400U) //!< Bit mask for SIM_SCGC4_UART0.
-#define BS_SIM_SCGC4_UART0 (1U) //!< Bit field size in bits for SIM_SCGC4_UART0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC4_UART0 field.
-#define BR_SIM_SCGC4_UART0 (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART0))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC4_UART0.
-#define BF_SIM_SCGC4_UART0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_UART0), uint32_t) & BM_SIM_SCGC4_UART0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the UART0 field to a new value.
-#define BW_SIM_SCGC4_UART0(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC4, field UART1[11] (RW)
- *
- * This bit controls the clock gate to the UART1 module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC4_UART1 (11U) //!< Bit position for SIM_SCGC4_UART1.
-#define BM_SIM_SCGC4_UART1 (0x00000800U) //!< Bit mask for SIM_SCGC4_UART1.
-#define BS_SIM_SCGC4_UART1 (1U) //!< Bit field size in bits for SIM_SCGC4_UART1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC4_UART1 field.
-#define BR_SIM_SCGC4_UART1 (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART1))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC4_UART1.
-#define BF_SIM_SCGC4_UART1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_UART1), uint32_t) & BM_SIM_SCGC4_UART1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the UART1 field to a new value.
-#define BW_SIM_SCGC4_UART1(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC4, field UART2[12] (RW)
- *
- * This bit controls the clock gate to the UART2 module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC4_UART2 (12U) //!< Bit position for SIM_SCGC4_UART2.
-#define BM_SIM_SCGC4_UART2 (0x00001000U) //!< Bit mask for SIM_SCGC4_UART2.
-#define BS_SIM_SCGC4_UART2 (1U) //!< Bit field size in bits for SIM_SCGC4_UART2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC4_UART2 field.
-#define BR_SIM_SCGC4_UART2 (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART2))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC4_UART2.
-#define BF_SIM_SCGC4_UART2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_UART2), uint32_t) & BM_SIM_SCGC4_UART2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the UART2 field to a new value.
-#define BW_SIM_SCGC4_UART2(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC4, field UART3[13] (RW)
- *
- * This bit controls the clock gate to the UART3 module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC4_UART3 (13U) //!< Bit position for SIM_SCGC4_UART3.
-#define BM_SIM_SCGC4_UART3 (0x00002000U) //!< Bit mask for SIM_SCGC4_UART3.
-#define BS_SIM_SCGC4_UART3 (1U) //!< Bit field size in bits for SIM_SCGC4_UART3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC4_UART3 field.
-#define BR_SIM_SCGC4_UART3 (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART3))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC4_UART3.
-#define BF_SIM_SCGC4_UART3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_UART3), uint32_t) & BM_SIM_SCGC4_UART3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the UART3 field to a new value.
-#define BW_SIM_SCGC4_UART3(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART3) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC4, field USBOTG[18] (RW)
- *
- * This bit controls the clock gate to the USB module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC4_USBOTG (18U) //!< Bit position for SIM_SCGC4_USBOTG.
-#define BM_SIM_SCGC4_USBOTG (0x00040000U) //!< Bit mask for SIM_SCGC4_USBOTG.
-#define BS_SIM_SCGC4_USBOTG (1U) //!< Bit field size in bits for SIM_SCGC4_USBOTG.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC4_USBOTG field.
-#define BR_SIM_SCGC4_USBOTG (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_USBOTG))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC4_USBOTG.
-#define BF_SIM_SCGC4_USBOTG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_USBOTG), uint32_t) & BM_SIM_SCGC4_USBOTG)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the USBOTG field to a new value.
-#define BW_SIM_SCGC4_USBOTG(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_USBOTG) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC4, field CMP[19] (RW)
- *
- * This bit controls the clock gate to the comparator module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC4_CMP (19U) //!< Bit position for SIM_SCGC4_CMP.
-#define BM_SIM_SCGC4_CMP (0x00080000U) //!< Bit mask for SIM_SCGC4_CMP.
-#define BS_SIM_SCGC4_CMP (1U) //!< Bit field size in bits for SIM_SCGC4_CMP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC4_CMP field.
-#define BR_SIM_SCGC4_CMP (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_CMP))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC4_CMP.
-#define BF_SIM_SCGC4_CMP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_CMP), uint32_t) & BM_SIM_SCGC4_CMP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CMP field to a new value.
-#define BW_SIM_SCGC4_CMP(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_CMP) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC4, field VREF[20] (RW)
- *
- * This bit controls the clock gate to the VREF module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC4_VREF (20U) //!< Bit position for SIM_SCGC4_VREF.
-#define BM_SIM_SCGC4_VREF (0x00100000U) //!< Bit mask for SIM_SCGC4_VREF.
-#define BS_SIM_SCGC4_VREF (1U) //!< Bit field size in bits for SIM_SCGC4_VREF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC4_VREF field.
-#define BR_SIM_SCGC4_VREF (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_VREF))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC4_VREF.
-#define BF_SIM_SCGC4_VREF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_VREF), uint32_t) & BM_SIM_SCGC4_VREF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the VREF field to a new value.
-#define BW_SIM_SCGC4_VREF(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_VREF) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SIM_SCGC5 - System Clock Gating Control Register 5
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SIM_SCGC5 - System Clock Gating Control Register 5 (RW)
- *
- * Reset value: 0x00040182U
- */
-typedef union _hw_sim_scgc5
-{
- uint32_t U;
- struct _hw_sim_scgc5_bitfields
- {
- uint32_t LPTMR : 1; //!< [0] Low Power Timer Access Control
- uint32_t RESERVED0 : 8; //!< [8:1]
- uint32_t PORTAb : 1; //!< [9] Port A Clock Gate Control
- uint32_t PORTBb : 1; //!< [10] Port B Clock Gate Control
- uint32_t PORTCb : 1; //!< [11] Port C Clock Gate Control
- uint32_t PORTDb : 1; //!< [12] Port D Clock Gate Control
- uint32_t PORTEb : 1; //!< [13] Port E Clock Gate Control
- uint32_t RESERVED1 : 18; //!< [31:14]
- } B;
-} hw_sim_scgc5_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SIM_SCGC5 register
- */
-//@{
-#define HW_SIM_SCGC5_ADDR (REGS_SIM_BASE + 0x1038U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SIM_SCGC5 (*(__IO hw_sim_scgc5_t *) HW_SIM_SCGC5_ADDR)
-#define HW_SIM_SCGC5_RD() (HW_SIM_SCGC5.U)
-#define HW_SIM_SCGC5_WR(v) (HW_SIM_SCGC5.U = (v))
-#define HW_SIM_SCGC5_SET(v) (HW_SIM_SCGC5_WR(HW_SIM_SCGC5_RD() | (v)))
-#define HW_SIM_SCGC5_CLR(v) (HW_SIM_SCGC5_WR(HW_SIM_SCGC5_RD() & ~(v)))
-#define HW_SIM_SCGC5_TOG(v) (HW_SIM_SCGC5_WR(HW_SIM_SCGC5_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SIM_SCGC5 bitfields
- */
-
-/*!
- * @name Register SIM_SCGC5, field LPTMR[0] (RW)
- *
- * This bit controls software access to the Low Power Timer module.
- *
- * Values:
- * - 0 - Access disabled
- * - 1 - Access enabled
- */
-//@{
-#define BP_SIM_SCGC5_LPTMR (0U) //!< Bit position for SIM_SCGC5_LPTMR.
-#define BM_SIM_SCGC5_LPTMR (0x00000001U) //!< Bit mask for SIM_SCGC5_LPTMR.
-#define BS_SIM_SCGC5_LPTMR (1U) //!< Bit field size in bits for SIM_SCGC5_LPTMR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC5_LPTMR field.
-#define BR_SIM_SCGC5_LPTMR (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_LPTMR))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC5_LPTMR.
-#define BF_SIM_SCGC5_LPTMR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_LPTMR), uint32_t) & BM_SIM_SCGC5_LPTMR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LPTMR field to a new value.
-#define BW_SIM_SCGC5_LPTMR(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_LPTMR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC5, field PORTA[9] (RW)
- *
- * This bit controls the clock gate to the Port A module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC5_PORTA (9U) //!< Bit position for SIM_SCGC5_PORTA.
-#define BM_SIM_SCGC5_PORTA (0x00000200U) //!< Bit mask for SIM_SCGC5_PORTA.
-#define BS_SIM_SCGC5_PORTA (1U) //!< Bit field size in bits for SIM_SCGC5_PORTA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC5_PORTA field.
-#define BR_SIM_SCGC5_PORTA (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTA))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC5_PORTA.
-#define BF_SIM_SCGC5_PORTA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_PORTA), uint32_t) & BM_SIM_SCGC5_PORTA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PORTA field to a new value.
-#define BW_SIM_SCGC5_PORTA(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTA) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC5, field PORTB[10] (RW)
- *
- * This bit controls the clock gate to the Port B module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC5_PORTB (10U) //!< Bit position for SIM_SCGC5_PORTB.
-#define BM_SIM_SCGC5_PORTB (0x00000400U) //!< Bit mask for SIM_SCGC5_PORTB.
-#define BS_SIM_SCGC5_PORTB (1U) //!< Bit field size in bits for SIM_SCGC5_PORTB.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC5_PORTB field.
-#define BR_SIM_SCGC5_PORTB (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTB))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC5_PORTB.
-#define BF_SIM_SCGC5_PORTB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_PORTB), uint32_t) & BM_SIM_SCGC5_PORTB)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PORTB field to a new value.
-#define BW_SIM_SCGC5_PORTB(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTB) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC5, field PORTC[11] (RW)
- *
- * This bit controls the clock gate to the Port C module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC5_PORTC (11U) //!< Bit position for SIM_SCGC5_PORTC.
-#define BM_SIM_SCGC5_PORTC (0x00000800U) //!< Bit mask for SIM_SCGC5_PORTC.
-#define BS_SIM_SCGC5_PORTC (1U) //!< Bit field size in bits for SIM_SCGC5_PORTC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC5_PORTC field.
-#define BR_SIM_SCGC5_PORTC (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTC))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC5_PORTC.
-#define BF_SIM_SCGC5_PORTC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_PORTC), uint32_t) & BM_SIM_SCGC5_PORTC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PORTC field to a new value.
-#define BW_SIM_SCGC5_PORTC(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC5, field PORTD[12] (RW)
- *
- * This bit controls the clock gate to the Port D module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC5_PORTD (12U) //!< Bit position for SIM_SCGC5_PORTD.
-#define BM_SIM_SCGC5_PORTD (0x00001000U) //!< Bit mask for SIM_SCGC5_PORTD.
-#define BS_SIM_SCGC5_PORTD (1U) //!< Bit field size in bits for SIM_SCGC5_PORTD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC5_PORTD field.
-#define BR_SIM_SCGC5_PORTD (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTD))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC5_PORTD.
-#define BF_SIM_SCGC5_PORTD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_PORTD), uint32_t) & BM_SIM_SCGC5_PORTD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PORTD field to a new value.
-#define BW_SIM_SCGC5_PORTD(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTD) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC5, field PORTE[13] (RW)
- *
- * This bit controls the clock gate to the Port E module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC5_PORTE (13U) //!< Bit position for SIM_SCGC5_PORTE.
-#define BM_SIM_SCGC5_PORTE (0x00002000U) //!< Bit mask for SIM_SCGC5_PORTE.
-#define BS_SIM_SCGC5_PORTE (1U) //!< Bit field size in bits for SIM_SCGC5_PORTE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC5_PORTE field.
-#define BR_SIM_SCGC5_PORTE (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTE))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC5_PORTE.
-#define BF_SIM_SCGC5_PORTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_PORTE), uint32_t) & BM_SIM_SCGC5_PORTE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PORTE field to a new value.
-#define BW_SIM_SCGC5_PORTE(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTE) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SIM_SCGC6 - System Clock Gating Control Register 6
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SIM_SCGC6 - System Clock Gating Control Register 6 (RW)
- *
- * Reset value: 0x40000001U
- *
- * DAC0, FTM2, and RNGA can be accessed through both AIPS0 and AIPS1. When
- * accessing through AIPS1, define the clock gate control bits in the SCGC2 and SCGC3.
- * When accessing through AIPS0, define the clock gate control bits in SCGC6.
- */
-typedef union _hw_sim_scgc6
-{
- uint32_t U;
- struct _hw_sim_scgc6_bitfields
- {
- uint32_t FTF : 1; //!< [0] Flash Memory Clock Gate Control
- uint32_t DMAMUXb : 1; //!< [1] DMA Mux Clock Gate Control
- uint32_t RESERVED0 : 2; //!< [3:2]
- uint32_t FLEXCAN0 : 1; //!< [4] FlexCAN0 Clock Gate Control
- uint32_t RESERVED1 : 4; //!< [8:5]
- uint32_t RNGA : 1; //!< [9] RNGA Clock Gate Control
- uint32_t RESERVED2 : 2; //!< [11:10]
- uint32_t SPI0b : 1; //!< [12] SPI0 Clock Gate Control
- uint32_t SPI1b : 1; //!< [13] SPI1 Clock Gate Control
- uint32_t RESERVED3 : 1; //!< [14]
- uint32_t I2S : 1; //!< [15] I2S Clock Gate Control
- uint32_t RESERVED4 : 2; //!< [17:16]
- uint32_t CRCb : 1; //!< [18] CRC Clock Gate Control
- uint32_t RESERVED5 : 2; //!< [20:19]
- uint32_t USBDCDb : 1; //!< [21] USB DCD Clock Gate Control
- uint32_t PDB : 1; //!< [22] PDB Clock Gate Control
- uint32_t PITb : 1; //!< [23] PIT Clock Gate Control
- uint32_t FTM0b : 1; //!< [24] FTM0 Clock Gate Control
- uint32_t FTM1b : 1; //!< [25] FTM1 Clock Gate Control
- uint32_t FTM2b : 1; //!< [26] FTM2 Clock Gate Control
- uint32_t ADC0b : 1; //!< [27] ADC0 Clock Gate Control
- uint32_t RESERVED6 : 1; //!< [28]
- uint32_t RTCb : 1; //!< [29] RTC Access Control
- uint32_t RESERVED7 : 1; //!< [30]
- uint32_t DAC0b : 1; //!< [31] DAC0 Clock Gate Control
- } B;
-} hw_sim_scgc6_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SIM_SCGC6 register
- */
-//@{
-#define HW_SIM_SCGC6_ADDR (REGS_SIM_BASE + 0x103CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SIM_SCGC6 (*(__IO hw_sim_scgc6_t *) HW_SIM_SCGC6_ADDR)
-#define HW_SIM_SCGC6_RD() (HW_SIM_SCGC6.U)
-#define HW_SIM_SCGC6_WR(v) (HW_SIM_SCGC6.U = (v))
-#define HW_SIM_SCGC6_SET(v) (HW_SIM_SCGC6_WR(HW_SIM_SCGC6_RD() | (v)))
-#define HW_SIM_SCGC6_CLR(v) (HW_SIM_SCGC6_WR(HW_SIM_SCGC6_RD() & ~(v)))
-#define HW_SIM_SCGC6_TOG(v) (HW_SIM_SCGC6_WR(HW_SIM_SCGC6_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SIM_SCGC6 bitfields
- */
-
-/*!
- * @name Register SIM_SCGC6, field FTF[0] (RW)
- *
- * This bit controls the clock gate to the flash memory. Flash reads are still
- * supported while the flash memory is clock gated, but entry into low power modes
- * is blocked.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC6_FTF (0U) //!< Bit position for SIM_SCGC6_FTF.
-#define BM_SIM_SCGC6_FTF (0x00000001U) //!< Bit mask for SIM_SCGC6_FTF.
-#define BS_SIM_SCGC6_FTF (1U) //!< Bit field size in bits for SIM_SCGC6_FTF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC6_FTF field.
-#define BR_SIM_SCGC6_FTF (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTF))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC6_FTF.
-#define BF_SIM_SCGC6_FTF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_FTF), uint32_t) & BM_SIM_SCGC6_FTF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FTF field to a new value.
-#define BW_SIM_SCGC6_FTF(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC6, field DMAMUX[1] (RW)
- *
- * This bit controls the clock gate to the DMA Mux module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC6_DMAMUX (1U) //!< Bit position for SIM_SCGC6_DMAMUX.
-#define BM_SIM_SCGC6_DMAMUX (0x00000002U) //!< Bit mask for SIM_SCGC6_DMAMUX.
-#define BS_SIM_SCGC6_DMAMUX (1U) //!< Bit field size in bits for SIM_SCGC6_DMAMUX.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC6_DMAMUX field.
-#define BR_SIM_SCGC6_DMAMUX (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_DMAMUX))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC6_DMAMUX.
-#define BF_SIM_SCGC6_DMAMUX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_DMAMUX), uint32_t) & BM_SIM_SCGC6_DMAMUX)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DMAMUX field to a new value.
-#define BW_SIM_SCGC6_DMAMUX(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_DMAMUX) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC6, field FLEXCAN0[4] (RW)
- *
- * This bit controls the clock gate to the FlexCAN0 module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC6_FLEXCAN0 (4U) //!< Bit position for SIM_SCGC6_FLEXCAN0.
-#define BM_SIM_SCGC6_FLEXCAN0 (0x00000010U) //!< Bit mask for SIM_SCGC6_FLEXCAN0.
-#define BS_SIM_SCGC6_FLEXCAN0 (1U) //!< Bit field size in bits for SIM_SCGC6_FLEXCAN0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC6_FLEXCAN0 field.
-#define BR_SIM_SCGC6_FLEXCAN0 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FLEXCAN0))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC6_FLEXCAN0.
-#define BF_SIM_SCGC6_FLEXCAN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_FLEXCAN0), uint32_t) & BM_SIM_SCGC6_FLEXCAN0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FLEXCAN0 field to a new value.
-#define BW_SIM_SCGC6_FLEXCAN0(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FLEXCAN0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC6, field RNGA[9] (RW)
- *
- * This bit controls the clock gate to the RNGA module.
- */
-//@{
-#define BP_SIM_SCGC6_RNGA (9U) //!< Bit position for SIM_SCGC6_RNGA.
-#define BM_SIM_SCGC6_RNGA (0x00000200U) //!< Bit mask for SIM_SCGC6_RNGA.
-#define BS_SIM_SCGC6_RNGA (1U) //!< Bit field size in bits for SIM_SCGC6_RNGA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC6_RNGA field.
-#define BR_SIM_SCGC6_RNGA (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_RNGA))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC6_RNGA.
-#define BF_SIM_SCGC6_RNGA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_RNGA), uint32_t) & BM_SIM_SCGC6_RNGA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RNGA field to a new value.
-#define BW_SIM_SCGC6_RNGA(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_RNGA) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC6, field SPI0[12] (RW)
- *
- * This bit controls the clock gate to the SPI0 module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC6_SPI0 (12U) //!< Bit position for SIM_SCGC6_SPI0.
-#define BM_SIM_SCGC6_SPI0 (0x00001000U) //!< Bit mask for SIM_SCGC6_SPI0.
-#define BS_SIM_SCGC6_SPI0 (1U) //!< Bit field size in bits for SIM_SCGC6_SPI0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC6_SPI0 field.
-#define BR_SIM_SCGC6_SPI0 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_SPI0))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC6_SPI0.
-#define BF_SIM_SCGC6_SPI0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_SPI0), uint32_t) & BM_SIM_SCGC6_SPI0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SPI0 field to a new value.
-#define BW_SIM_SCGC6_SPI0(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_SPI0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC6, field SPI1[13] (RW)
- *
- * This bit controls the clock gate to the SPI1 module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC6_SPI1 (13U) //!< Bit position for SIM_SCGC6_SPI1.
-#define BM_SIM_SCGC6_SPI1 (0x00002000U) //!< Bit mask for SIM_SCGC6_SPI1.
-#define BS_SIM_SCGC6_SPI1 (1U) //!< Bit field size in bits for SIM_SCGC6_SPI1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC6_SPI1 field.
-#define BR_SIM_SCGC6_SPI1 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_SPI1))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC6_SPI1.
-#define BF_SIM_SCGC6_SPI1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_SPI1), uint32_t) & BM_SIM_SCGC6_SPI1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SPI1 field to a new value.
-#define BW_SIM_SCGC6_SPI1(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_SPI1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC6, field I2S[15] (RW)
- *
- * This bit controls the clock gate to the I 2 S module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC6_I2S (15U) //!< Bit position for SIM_SCGC6_I2S.
-#define BM_SIM_SCGC6_I2S (0x00008000U) //!< Bit mask for SIM_SCGC6_I2S.
-#define BS_SIM_SCGC6_I2S (1U) //!< Bit field size in bits for SIM_SCGC6_I2S.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC6_I2S field.
-#define BR_SIM_SCGC6_I2S (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_I2S))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC6_I2S.
-#define BF_SIM_SCGC6_I2S(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_I2S), uint32_t) & BM_SIM_SCGC6_I2S)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the I2S field to a new value.
-#define BW_SIM_SCGC6_I2S(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_I2S) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC6, field CRC[18] (RW)
- *
- * This bit controls the clock gate to the CRC module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC6_CRC (18U) //!< Bit position for SIM_SCGC6_CRC.
-#define BM_SIM_SCGC6_CRC (0x00040000U) //!< Bit mask for SIM_SCGC6_CRC.
-#define BS_SIM_SCGC6_CRC (1U) //!< Bit field size in bits for SIM_SCGC6_CRC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC6_CRC field.
-#define BR_SIM_SCGC6_CRC (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_CRC))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC6_CRC.
-#define BF_SIM_SCGC6_CRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_CRC), uint32_t) & BM_SIM_SCGC6_CRC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CRC field to a new value.
-#define BW_SIM_SCGC6_CRC(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_CRC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC6, field USBDCD[21] (RW)
- *
- * This bit controls the clock gate to the USB DCD module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC6_USBDCD (21U) //!< Bit position for SIM_SCGC6_USBDCD.
-#define BM_SIM_SCGC6_USBDCD (0x00200000U) //!< Bit mask for SIM_SCGC6_USBDCD.
-#define BS_SIM_SCGC6_USBDCD (1U) //!< Bit field size in bits for SIM_SCGC6_USBDCD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC6_USBDCD field.
-#define BR_SIM_SCGC6_USBDCD (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_USBDCD))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC6_USBDCD.
-#define BF_SIM_SCGC6_USBDCD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_USBDCD), uint32_t) & BM_SIM_SCGC6_USBDCD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the USBDCD field to a new value.
-#define BW_SIM_SCGC6_USBDCD(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_USBDCD) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC6, field PDB[22] (RW)
- *
- * This bit controls the clock gate to the PDB module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC6_PDB (22U) //!< Bit position for SIM_SCGC6_PDB.
-#define BM_SIM_SCGC6_PDB (0x00400000U) //!< Bit mask for SIM_SCGC6_PDB.
-#define BS_SIM_SCGC6_PDB (1U) //!< Bit field size in bits for SIM_SCGC6_PDB.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC6_PDB field.
-#define BR_SIM_SCGC6_PDB (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_PDB))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC6_PDB.
-#define BF_SIM_SCGC6_PDB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_PDB), uint32_t) & BM_SIM_SCGC6_PDB)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PDB field to a new value.
-#define BW_SIM_SCGC6_PDB(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_PDB) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC6, field PIT[23] (RW)
- *
- * This bit controls the clock gate to the PIT module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC6_PIT (23U) //!< Bit position for SIM_SCGC6_PIT.
-#define BM_SIM_SCGC6_PIT (0x00800000U) //!< Bit mask for SIM_SCGC6_PIT.
-#define BS_SIM_SCGC6_PIT (1U) //!< Bit field size in bits for SIM_SCGC6_PIT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC6_PIT field.
-#define BR_SIM_SCGC6_PIT (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_PIT))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC6_PIT.
-#define BF_SIM_SCGC6_PIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_PIT), uint32_t) & BM_SIM_SCGC6_PIT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PIT field to a new value.
-#define BW_SIM_SCGC6_PIT(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_PIT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC6, field FTM0[24] (RW)
- *
- * This bit controls the clock gate to the FTM0 module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC6_FTM0 (24U) //!< Bit position for SIM_SCGC6_FTM0.
-#define BM_SIM_SCGC6_FTM0 (0x01000000U) //!< Bit mask for SIM_SCGC6_FTM0.
-#define BS_SIM_SCGC6_FTM0 (1U) //!< Bit field size in bits for SIM_SCGC6_FTM0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC6_FTM0 field.
-#define BR_SIM_SCGC6_FTM0 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM0))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC6_FTM0.
-#define BF_SIM_SCGC6_FTM0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_FTM0), uint32_t) & BM_SIM_SCGC6_FTM0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FTM0 field to a new value.
-#define BW_SIM_SCGC6_FTM0(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC6, field FTM1[25] (RW)
- *
- * This bit controls the clock gate to the FTM1 module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC6_FTM1 (25U) //!< Bit position for SIM_SCGC6_FTM1.
-#define BM_SIM_SCGC6_FTM1 (0x02000000U) //!< Bit mask for SIM_SCGC6_FTM1.
-#define BS_SIM_SCGC6_FTM1 (1U) //!< Bit field size in bits for SIM_SCGC6_FTM1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC6_FTM1 field.
-#define BR_SIM_SCGC6_FTM1 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM1))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC6_FTM1.
-#define BF_SIM_SCGC6_FTM1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_FTM1), uint32_t) & BM_SIM_SCGC6_FTM1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FTM1 field to a new value.
-#define BW_SIM_SCGC6_FTM1(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM1) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC6, field FTM2[26] (RW)
- *
- * This bit controls the clock gate to the FTM2 module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC6_FTM2 (26U) //!< Bit position for SIM_SCGC6_FTM2.
-#define BM_SIM_SCGC6_FTM2 (0x04000000U) //!< Bit mask for SIM_SCGC6_FTM2.
-#define BS_SIM_SCGC6_FTM2 (1U) //!< Bit field size in bits for SIM_SCGC6_FTM2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC6_FTM2 field.
-#define BR_SIM_SCGC6_FTM2 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM2))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC6_FTM2.
-#define BF_SIM_SCGC6_FTM2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_FTM2), uint32_t) & BM_SIM_SCGC6_FTM2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FTM2 field to a new value.
-#define BW_SIM_SCGC6_FTM2(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC6, field ADC0[27] (RW)
- *
- * This bit controls the clock gate to the ADC0 module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC6_ADC0 (27U) //!< Bit position for SIM_SCGC6_ADC0.
-#define BM_SIM_SCGC6_ADC0 (0x08000000U) //!< Bit mask for SIM_SCGC6_ADC0.
-#define BS_SIM_SCGC6_ADC0 (1U) //!< Bit field size in bits for SIM_SCGC6_ADC0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC6_ADC0 field.
-#define BR_SIM_SCGC6_ADC0 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_ADC0))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC6_ADC0.
-#define BF_SIM_SCGC6_ADC0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_ADC0), uint32_t) & BM_SIM_SCGC6_ADC0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ADC0 field to a new value.
-#define BW_SIM_SCGC6_ADC0(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_ADC0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC6, field RTC[29] (RW)
- *
- * This bit controls software access and interrupts to the RTC module.
- *
- * Values:
- * - 0 - Access and interrupts disabled
- * - 1 - Access and interrupts enabled
- */
-//@{
-#define BP_SIM_SCGC6_RTC (29U) //!< Bit position for SIM_SCGC6_RTC.
-#define BM_SIM_SCGC6_RTC (0x20000000U) //!< Bit mask for SIM_SCGC6_RTC.
-#define BS_SIM_SCGC6_RTC (1U) //!< Bit field size in bits for SIM_SCGC6_RTC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC6_RTC field.
-#define BR_SIM_SCGC6_RTC (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_RTC))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC6_RTC.
-#define BF_SIM_SCGC6_RTC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_RTC), uint32_t) & BM_SIM_SCGC6_RTC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RTC field to a new value.
-#define BW_SIM_SCGC6_RTC(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_RTC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC6, field DAC0[31] (RW)
- *
- * This bit controls the clock gate to the DAC0 module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC6_DAC0 (31U) //!< Bit position for SIM_SCGC6_DAC0.
-#define BM_SIM_SCGC6_DAC0 (0x80000000U) //!< Bit mask for SIM_SCGC6_DAC0.
-#define BS_SIM_SCGC6_DAC0 (1U) //!< Bit field size in bits for SIM_SCGC6_DAC0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC6_DAC0 field.
-#define BR_SIM_SCGC6_DAC0 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_DAC0))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC6_DAC0.
-#define BF_SIM_SCGC6_DAC0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_DAC0), uint32_t) & BM_SIM_SCGC6_DAC0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DAC0 field to a new value.
-#define BW_SIM_SCGC6_DAC0(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_DAC0) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SIM_SCGC7 - System Clock Gating Control Register 7
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SIM_SCGC7 - System Clock Gating Control Register 7 (RW)
- *
- * Reset value: 0x00000006U
- */
-typedef union _hw_sim_scgc7
-{
- uint32_t U;
- struct _hw_sim_scgc7_bitfields
- {
- uint32_t FLEXBUS : 1; //!< [0] FlexBus Clock Gate Control
- uint32_t DMAb : 1; //!< [1] DMA Clock Gate Control
- uint32_t MPUb : 1; //!< [2] MPU Clock Gate Control
- uint32_t RESERVED0 : 29; //!< [31:3]
- } B;
-} hw_sim_scgc7_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SIM_SCGC7 register
- */
-//@{
-#define HW_SIM_SCGC7_ADDR (REGS_SIM_BASE + 0x1040U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SIM_SCGC7 (*(__IO hw_sim_scgc7_t *) HW_SIM_SCGC7_ADDR)
-#define HW_SIM_SCGC7_RD() (HW_SIM_SCGC7.U)
-#define HW_SIM_SCGC7_WR(v) (HW_SIM_SCGC7.U = (v))
-#define HW_SIM_SCGC7_SET(v) (HW_SIM_SCGC7_WR(HW_SIM_SCGC7_RD() | (v)))
-#define HW_SIM_SCGC7_CLR(v) (HW_SIM_SCGC7_WR(HW_SIM_SCGC7_RD() & ~(v)))
-#define HW_SIM_SCGC7_TOG(v) (HW_SIM_SCGC7_WR(HW_SIM_SCGC7_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SIM_SCGC7 bitfields
- */
-
-/*!
- * @name Register SIM_SCGC7, field FLEXBUS[0] (RW)
- *
- * This bit controls the clock gate to the FlexBus module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC7_FLEXBUS (0U) //!< Bit position for SIM_SCGC7_FLEXBUS.
-#define BM_SIM_SCGC7_FLEXBUS (0x00000001U) //!< Bit mask for SIM_SCGC7_FLEXBUS.
-#define BS_SIM_SCGC7_FLEXBUS (1U) //!< Bit field size in bits for SIM_SCGC7_FLEXBUS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC7_FLEXBUS field.
-#define BR_SIM_SCGC7_FLEXBUS (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_FLEXBUS))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC7_FLEXBUS.
-#define BF_SIM_SCGC7_FLEXBUS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC7_FLEXBUS), uint32_t) & BM_SIM_SCGC7_FLEXBUS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FLEXBUS field to a new value.
-#define BW_SIM_SCGC7_FLEXBUS(v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_FLEXBUS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC7, field DMA[1] (RW)
- *
- * This bit controls the clock gate to the DMA module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC7_DMA (1U) //!< Bit position for SIM_SCGC7_DMA.
-#define BM_SIM_SCGC7_DMA (0x00000002U) //!< Bit mask for SIM_SCGC7_DMA.
-#define BS_SIM_SCGC7_DMA (1U) //!< Bit field size in bits for SIM_SCGC7_DMA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC7_DMA field.
-#define BR_SIM_SCGC7_DMA (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_DMA))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC7_DMA.
-#define BF_SIM_SCGC7_DMA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC7_DMA), uint32_t) & BM_SIM_SCGC7_DMA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DMA field to a new value.
-#define BW_SIM_SCGC7_DMA(v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_DMA) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_SCGC7, field MPU[2] (RW)
- *
- * This bit controls the clock gate to the MPU module.
- *
- * Values:
- * - 0 - Clock disabled
- * - 1 - Clock enabled
- */
-//@{
-#define BP_SIM_SCGC7_MPU (2U) //!< Bit position for SIM_SCGC7_MPU.
-#define BM_SIM_SCGC7_MPU (0x00000004U) //!< Bit mask for SIM_SCGC7_MPU.
-#define BS_SIM_SCGC7_MPU (1U) //!< Bit field size in bits for SIM_SCGC7_MPU.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_SCGC7_MPU field.
-#define BR_SIM_SCGC7_MPU (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_MPU))
-#endif
-
-//! @brief Format value for bitfield SIM_SCGC7_MPU.
-#define BF_SIM_SCGC7_MPU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC7_MPU), uint32_t) & BM_SIM_SCGC7_MPU)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MPU field to a new value.
-#define BW_SIM_SCGC7_MPU(v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_MPU) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SIM_CLKDIV1 - System Clock Divider Register 1
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SIM_CLKDIV1 - System Clock Divider Register 1 (RW)
- *
- * Reset value: 0x00010000U
- *
- * When updating CLKDIV1, update all fields using the one write command.
- * Attempting to write an invalid clock ratio to the CLKDIV1 register will cause the
- * write to be ignored. The maximum divide ratio that can be programmed between
- * core/system clock and the other divided clocks is divide by 8. When OUTDIV1 equals
- * 0000 (divide by 1), the other dividers cannot be set higher than 0111 (divide
- * by 8). The CLKDIV1 register cannot be written to when the device is in VLPR
- * mode.
- */
-typedef union _hw_sim_clkdiv1
-{
- uint32_t U;
- struct _hw_sim_clkdiv1_bitfields
- {
- uint32_t RESERVED0 : 16; //!< [15:0]
- uint32_t OUTDIV4 : 4; //!< [19:16] Clock 4 output divider value
- uint32_t OUTDIV3 : 4; //!< [23:20] Clock 3 output divider value
- uint32_t OUTDIV2 : 4; //!< [27:24] Clock 2 output divider value
- uint32_t OUTDIV1 : 4; //!< [31:28] Clock 1 output divider value
- } B;
-} hw_sim_clkdiv1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SIM_CLKDIV1 register
- */
-//@{
-#define HW_SIM_CLKDIV1_ADDR (REGS_SIM_BASE + 0x1044U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SIM_CLKDIV1 (*(__IO hw_sim_clkdiv1_t *) HW_SIM_CLKDIV1_ADDR)
-#define HW_SIM_CLKDIV1_RD() (HW_SIM_CLKDIV1.U)
-#define HW_SIM_CLKDIV1_WR(v) (HW_SIM_CLKDIV1.U = (v))
-#define HW_SIM_CLKDIV1_SET(v) (HW_SIM_CLKDIV1_WR(HW_SIM_CLKDIV1_RD() | (v)))
-#define HW_SIM_CLKDIV1_CLR(v) (HW_SIM_CLKDIV1_WR(HW_SIM_CLKDIV1_RD() & ~(v)))
-#define HW_SIM_CLKDIV1_TOG(v) (HW_SIM_CLKDIV1_WR(HW_SIM_CLKDIV1_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SIM_CLKDIV1 bitfields
- */
-
-/*!
- * @name Register SIM_CLKDIV1, field OUTDIV4[19:16] (RW)
- *
- * This field sets the divide value for the flash clock from MCGOUTCLK. At the
- * end of reset, it is loaded with either 0001 or 1111 depending on
- * FTF_FOPT[LPBOOT]. The flash clock frequency must be an integer divide of the system clock
- * frequency.
- *
- * Values:
- * - 0000 - Divide-by-1.
- * - 0001 - Divide-by-2.
- * - 0010 - Divide-by-3.
- * - 0011 - Divide-by-4.
- * - 0100 - Divide-by-5.
- * - 0101 - Divide-by-6.
- * - 0110 - Divide-by-7.
- * - 0111 - Divide-by-8.
- * - 1000 - Divide-by-9.
- * - 1001 - Divide-by-10.
- * - 1010 - Divide-by-11.
- * - 1011 - Divide-by-12.
- * - 1100 - Divide-by-13.
- * - 1101 - Divide-by-14.
- * - 1110 - Divide-by-15.
- * - 1111 - Divide-by-16.
- */
-//@{
-#define BP_SIM_CLKDIV1_OUTDIV4 (16U) //!< Bit position for SIM_CLKDIV1_OUTDIV4.
-#define BM_SIM_CLKDIV1_OUTDIV4 (0x000F0000U) //!< Bit mask for SIM_CLKDIV1_OUTDIV4.
-#define BS_SIM_CLKDIV1_OUTDIV4 (4U) //!< Bit field size in bits for SIM_CLKDIV1_OUTDIV4.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_CLKDIV1_OUTDIV4 field.
-#define BR_SIM_CLKDIV1_OUTDIV4 (HW_SIM_CLKDIV1.B.OUTDIV4)
-#endif
-
-//! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV4.
-#define BF_SIM_CLKDIV1_OUTDIV4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV1_OUTDIV4), uint32_t) & BM_SIM_CLKDIV1_OUTDIV4)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the OUTDIV4 field to a new value.
-#define BW_SIM_CLKDIV1_OUTDIV4(v) (HW_SIM_CLKDIV1_WR((HW_SIM_CLKDIV1_RD() & ~BM_SIM_CLKDIV1_OUTDIV4) | BF_SIM_CLKDIV1_OUTDIV4(v)))
-#endif
-//@}
-
-/*!
- * @name Register SIM_CLKDIV1, field OUTDIV3[23:20] (RW)
- *
- * This field sets the divide value for the FlexBus clock (external pin FB_CLK)
- * from MCGOUTCLK. At the end of reset, it is loaded with either 0001 or 1111
- * depending on FTF_FOPT[LPBOOT]. The FlexBus clock frequency must be an integer
- * divide of the system clock frequency.
- *
- * Values:
- * - 0000 - Divide-by-1.
- * - 0001 - Divide-by-2.
- * - 0010 - Divide-by-3.
- * - 0011 - Divide-by-4.
- * - 0100 - Divide-by-5.
- * - 0101 - Divide-by-6.
- * - 0110 - Divide-by-7.
- * - 0111 - Divide-by-8.
- * - 1000 - Divide-by-9.
- * - 1001 - Divide-by-10.
- * - 1010 - Divide-by-11.
- * - 1011 - Divide-by-12.
- * - 1100 - Divide-by-13.
- * - 1101 - Divide-by-14.
- * - 1110 - Divide-by-15.
- * - 1111 - Divide-by-16.
- */
-//@{
-#define BP_SIM_CLKDIV1_OUTDIV3 (20U) //!< Bit position for SIM_CLKDIV1_OUTDIV3.
-#define BM_SIM_CLKDIV1_OUTDIV3 (0x00F00000U) //!< Bit mask for SIM_CLKDIV1_OUTDIV3.
-#define BS_SIM_CLKDIV1_OUTDIV3 (4U) //!< Bit field size in bits for SIM_CLKDIV1_OUTDIV3.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_CLKDIV1_OUTDIV3 field.
-#define BR_SIM_CLKDIV1_OUTDIV3 (HW_SIM_CLKDIV1.B.OUTDIV3)
-#endif
-
-//! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV3.
-#define BF_SIM_CLKDIV1_OUTDIV3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV1_OUTDIV3), uint32_t) & BM_SIM_CLKDIV1_OUTDIV3)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the OUTDIV3 field to a new value.
-#define BW_SIM_CLKDIV1_OUTDIV3(v) (HW_SIM_CLKDIV1_WR((HW_SIM_CLKDIV1_RD() & ~BM_SIM_CLKDIV1_OUTDIV3) | BF_SIM_CLKDIV1_OUTDIV3(v)))
-#endif
-//@}
-
-/*!
- * @name Register SIM_CLKDIV1, field OUTDIV2[27:24] (RW)
- *
- * This field sets the divide value for the bus clock from MCGOUTCLK. At the end
- * of reset, it is loaded with either 0000 or 0111 depending on
- * FTF_FOPT[LPBOOT]. The bus clock frequency must be an integer divide of the core/system clock
- * frequency.
- *
- * Values:
- * - 0000 - Divide-by-1.
- * - 0001 - Divide-by-2.
- * - 0010 - Divide-by-3.
- * - 0011 - Divide-by-4.
- * - 0100 - Divide-by-5.
- * - 0101 - Divide-by-6.
- * - 0110 - Divide-by-7.
- * - 0111 - Divide-by-8.
- * - 1000 - Divide-by-9.
- * - 1001 - Divide-by-10.
- * - 1010 - Divide-by-11.
- * - 1011 - Divide-by-12.
- * - 1100 - Divide-by-13.
- * - 1101 - Divide-by-14.
- * - 1110 - Divide-by-15.
- * - 1111 - Divide-by-16.
- */
-//@{
-#define BP_SIM_CLKDIV1_OUTDIV2 (24U) //!< Bit position for SIM_CLKDIV1_OUTDIV2.
-#define BM_SIM_CLKDIV1_OUTDIV2 (0x0F000000U) //!< Bit mask for SIM_CLKDIV1_OUTDIV2.
-#define BS_SIM_CLKDIV1_OUTDIV2 (4U) //!< Bit field size in bits for SIM_CLKDIV1_OUTDIV2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_CLKDIV1_OUTDIV2 field.
-#define BR_SIM_CLKDIV1_OUTDIV2 (HW_SIM_CLKDIV1.B.OUTDIV2)
-#endif
-
-//! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV2.
-#define BF_SIM_CLKDIV1_OUTDIV2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV1_OUTDIV2), uint32_t) & BM_SIM_CLKDIV1_OUTDIV2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the OUTDIV2 field to a new value.
-#define BW_SIM_CLKDIV1_OUTDIV2(v) (HW_SIM_CLKDIV1_WR((HW_SIM_CLKDIV1_RD() & ~BM_SIM_CLKDIV1_OUTDIV2) | BF_SIM_CLKDIV1_OUTDIV2(v)))
-#endif
-//@}
-
-/*!
- * @name Register SIM_CLKDIV1, field OUTDIV1[31:28] (RW)
- *
- * This field sets the divide value for the core/system clock from MCGOUTCLK. At
- * the end of reset, it is loaded with either 0000 or 0111 depending on
- * FTF_FOPT[LPBOOT].
- *
- * Values:
- * - 0000 - Divide-by-1.
- * - 0001 - Divide-by-2.
- * - 0010 - Divide-by-3.
- * - 0011 - Divide-by-4.
- * - 0100 - Divide-by-5.
- * - 0101 - Divide-by-6.
- * - 0110 - Divide-by-7.
- * - 0111 - Divide-by-8.
- * - 1000 - Divide-by-9.
- * - 1001 - Divide-by-10.
- * - 1010 - Divide-by-11.
- * - 1011 - Divide-by-12.
- * - 1100 - Divide-by-13.
- * - 1101 - Divide-by-14.
- * - 1110 - Divide-by-15.
- * - 1111 - Divide-by-16.
- */
-//@{
-#define BP_SIM_CLKDIV1_OUTDIV1 (28U) //!< Bit position for SIM_CLKDIV1_OUTDIV1.
-#define BM_SIM_CLKDIV1_OUTDIV1 (0xF0000000U) //!< Bit mask for SIM_CLKDIV1_OUTDIV1.
-#define BS_SIM_CLKDIV1_OUTDIV1 (4U) //!< Bit field size in bits for SIM_CLKDIV1_OUTDIV1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_CLKDIV1_OUTDIV1 field.
-#define BR_SIM_CLKDIV1_OUTDIV1 (HW_SIM_CLKDIV1.B.OUTDIV1)
-#endif
-
-//! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV1.
-#define BF_SIM_CLKDIV1_OUTDIV1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV1_OUTDIV1), uint32_t) & BM_SIM_CLKDIV1_OUTDIV1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the OUTDIV1 field to a new value.
-#define BW_SIM_CLKDIV1_OUTDIV1(v) (HW_SIM_CLKDIV1_WR((HW_SIM_CLKDIV1_RD() & ~BM_SIM_CLKDIV1_OUTDIV1) | BF_SIM_CLKDIV1_OUTDIV1(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SIM_CLKDIV2 - System Clock Divider Register 2
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SIM_CLKDIV2 - System Clock Divider Register 2 (RW)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_sim_clkdiv2
-{
- uint32_t U;
- struct _hw_sim_clkdiv2_bitfields
- {
- uint32_t USBFRAC : 1; //!< [0] USB clock divider fraction
- uint32_t USBDIV : 3; //!< [3:1] USB clock divider divisor
- uint32_t RESERVED0 : 28; //!< [31:4]
- } B;
-} hw_sim_clkdiv2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SIM_CLKDIV2 register
- */
-//@{
-#define HW_SIM_CLKDIV2_ADDR (REGS_SIM_BASE + 0x1048U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SIM_CLKDIV2 (*(__IO hw_sim_clkdiv2_t *) HW_SIM_CLKDIV2_ADDR)
-#define HW_SIM_CLKDIV2_RD() (HW_SIM_CLKDIV2.U)
-#define HW_SIM_CLKDIV2_WR(v) (HW_SIM_CLKDIV2.U = (v))
-#define HW_SIM_CLKDIV2_SET(v) (HW_SIM_CLKDIV2_WR(HW_SIM_CLKDIV2_RD() | (v)))
-#define HW_SIM_CLKDIV2_CLR(v) (HW_SIM_CLKDIV2_WR(HW_SIM_CLKDIV2_RD() & ~(v)))
-#define HW_SIM_CLKDIV2_TOG(v) (HW_SIM_CLKDIV2_WR(HW_SIM_CLKDIV2_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SIM_CLKDIV2 bitfields
- */
-
-/*!
- * @name Register SIM_CLKDIV2, field USBFRAC[0] (RW)
- *
- * This field sets the fraction multiply value for the fractional clock divider
- * when the MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] =
- * 1). Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
- */
-//@{
-#define BP_SIM_CLKDIV2_USBFRAC (0U) //!< Bit position for SIM_CLKDIV2_USBFRAC.
-#define BM_SIM_CLKDIV2_USBFRAC (0x00000001U) //!< Bit mask for SIM_CLKDIV2_USBFRAC.
-#define BS_SIM_CLKDIV2_USBFRAC (1U) //!< Bit field size in bits for SIM_CLKDIV2_USBFRAC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_CLKDIV2_USBFRAC field.
-#define BR_SIM_CLKDIV2_USBFRAC (BITBAND_ACCESS32(HW_SIM_CLKDIV2_ADDR, BP_SIM_CLKDIV2_USBFRAC))
-#endif
-
-//! @brief Format value for bitfield SIM_CLKDIV2_USBFRAC.
-#define BF_SIM_CLKDIV2_USBFRAC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV2_USBFRAC), uint32_t) & BM_SIM_CLKDIV2_USBFRAC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the USBFRAC field to a new value.
-#define BW_SIM_CLKDIV2_USBFRAC(v) (BITBAND_ACCESS32(HW_SIM_CLKDIV2_ADDR, BP_SIM_CLKDIV2_USBFRAC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_CLKDIV2, field USBDIV[3:1] (RW)
- *
- * This field sets the divide value for the fractional clock divider when the
- * MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = 1). Divider
- * output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
- */
-//@{
-#define BP_SIM_CLKDIV2_USBDIV (1U) //!< Bit position for SIM_CLKDIV2_USBDIV.
-#define BM_SIM_CLKDIV2_USBDIV (0x0000000EU) //!< Bit mask for SIM_CLKDIV2_USBDIV.
-#define BS_SIM_CLKDIV2_USBDIV (3U) //!< Bit field size in bits for SIM_CLKDIV2_USBDIV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_CLKDIV2_USBDIV field.
-#define BR_SIM_CLKDIV2_USBDIV (HW_SIM_CLKDIV2.B.USBDIV)
-#endif
-
-//! @brief Format value for bitfield SIM_CLKDIV2_USBDIV.
-#define BF_SIM_CLKDIV2_USBDIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV2_USBDIV), uint32_t) & BM_SIM_CLKDIV2_USBDIV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the USBDIV field to a new value.
-#define BW_SIM_CLKDIV2_USBDIV(v) (HW_SIM_CLKDIV2_WR((HW_SIM_CLKDIV2_RD() & ~BM_SIM_CLKDIV2_USBDIV) | BF_SIM_CLKDIV2_USBDIV(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SIM_FCFG1 - Flash Configuration Register 1
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SIM_FCFG1 - Flash Configuration Register 1 (RW)
- *
- * Reset value: 0xFF0F0F00U
- *
- * For devices with FlexNVM: The reset value of EESIZE and DEPART are based on
- * user programming in user IFR via the PGMPART flash command. For devices with
- * program flash only:
- */
-typedef union _hw_sim_fcfg1
-{
- uint32_t U;
- struct _hw_sim_fcfg1_bitfields
- {
- uint32_t FLASHDIS : 1; //!< [0] Flash Disable
- uint32_t FLASHDOZE : 1; //!< [1] Flash Doze
- uint32_t RESERVED0 : 6; //!< [7:2]
- uint32_t DEPART : 4; //!< [11:8] FlexNVM partition
- uint32_t RESERVED1 : 4; //!< [15:12]
- uint32_t EESIZE : 4; //!< [19:16] EEPROM size
- uint32_t RESERVED2 : 4; //!< [23:20]
- uint32_t PFSIZE : 4; //!< [27:24] Program flash size
- uint32_t NVMSIZE : 4; //!< [31:28] FlexNVM size
- } B;
-} hw_sim_fcfg1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SIM_FCFG1 register
- */
-//@{
-#define HW_SIM_FCFG1_ADDR (REGS_SIM_BASE + 0x104CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SIM_FCFG1 (*(__IO hw_sim_fcfg1_t *) HW_SIM_FCFG1_ADDR)
-#define HW_SIM_FCFG1_RD() (HW_SIM_FCFG1.U)
-#define HW_SIM_FCFG1_WR(v) (HW_SIM_FCFG1.U = (v))
-#define HW_SIM_FCFG1_SET(v) (HW_SIM_FCFG1_WR(HW_SIM_FCFG1_RD() | (v)))
-#define HW_SIM_FCFG1_CLR(v) (HW_SIM_FCFG1_WR(HW_SIM_FCFG1_RD() & ~(v)))
-#define HW_SIM_FCFG1_TOG(v) (HW_SIM_FCFG1_WR(HW_SIM_FCFG1_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SIM_FCFG1 bitfields
- */
-
-/*!
- * @name Register SIM_FCFG1, field FLASHDIS[0] (RW)
- *
- * Flash accesses are disabled (and generate a bus error) and the Flash memory
- * is placed in a low power state. This bit should not be changed during VLP
- * modes. Relocate the interrupt vectors out of Flash memory before disabling the
- * Flash.
- *
- * Values:
- * - 0 - Flash is enabled
- * - 1 - Flash is disabled
- */
-//@{
-#define BP_SIM_FCFG1_FLASHDIS (0U) //!< Bit position for SIM_FCFG1_FLASHDIS.
-#define BM_SIM_FCFG1_FLASHDIS (0x00000001U) //!< Bit mask for SIM_FCFG1_FLASHDIS.
-#define BS_SIM_FCFG1_FLASHDIS (1U) //!< Bit field size in bits for SIM_FCFG1_FLASHDIS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_FCFG1_FLASHDIS field.
-#define BR_SIM_FCFG1_FLASHDIS (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR, BP_SIM_FCFG1_FLASHDIS))
-#endif
-
-//! @brief Format value for bitfield SIM_FCFG1_FLASHDIS.
-#define BF_SIM_FCFG1_FLASHDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_FCFG1_FLASHDIS), uint32_t) & BM_SIM_FCFG1_FLASHDIS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FLASHDIS field to a new value.
-#define BW_SIM_FCFG1_FLASHDIS(v) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR, BP_SIM_FCFG1_FLASHDIS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_FCFG1, field FLASHDOZE[1] (RW)
- *
- * When set, Flash memory is disabled for the duration of Wait mode. An attempt
- * by the DMA or other bus master to access the Flash when the Flash is disabled
- * will result in a bus error. This bit should be clear during VLP modes. The
- * Flash will be automatically enabled again at the end of Wait mode so interrupt
- * vectors do not need to be relocated out of Flash memory. The wakeup time from
- * Wait mode is extended when this bit is set.
- *
- * Values:
- * - 0 - Flash remains enabled during Wait mode
- * - 1 - Flash is disabled for the duration of Wait mode
- */
-//@{
-#define BP_SIM_FCFG1_FLASHDOZE (1U) //!< Bit position for SIM_FCFG1_FLASHDOZE.
-#define BM_SIM_FCFG1_FLASHDOZE (0x00000002U) //!< Bit mask for SIM_FCFG1_FLASHDOZE.
-#define BS_SIM_FCFG1_FLASHDOZE (1U) //!< Bit field size in bits for SIM_FCFG1_FLASHDOZE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_FCFG1_FLASHDOZE field.
-#define BR_SIM_FCFG1_FLASHDOZE (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR, BP_SIM_FCFG1_FLASHDOZE))
-#endif
-
-//! @brief Format value for bitfield SIM_FCFG1_FLASHDOZE.
-#define BF_SIM_FCFG1_FLASHDOZE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_FCFG1_FLASHDOZE), uint32_t) & BM_SIM_FCFG1_FLASHDOZE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FLASHDOZE field to a new value.
-#define BW_SIM_FCFG1_FLASHDOZE(v) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR, BP_SIM_FCFG1_FLASHDOZE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SIM_FCFG1, field DEPART[11:8] (RO)
- *
- * For devices with FlexNVM: Data flash / EEPROM backup split . See DEPART bit
- * description in FTFE chapter. For devices without FlexNVM: Reserved
- */
-//@{
-#define BP_SIM_FCFG1_DEPART (8U) //!< Bit position for SIM_FCFG1_DEPART.
-#define BM_SIM_FCFG1_DEPART (0x00000F00U) //!< Bit mask for SIM_FCFG1_DEPART.
-#define BS_SIM_FCFG1_DEPART (4U) //!< Bit field size in bits for SIM_FCFG1_DEPART.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_FCFG1_DEPART field.
-#define BR_SIM_FCFG1_DEPART (HW_SIM_FCFG1.B.DEPART)
-#endif
-//@}
-
-/*!
- * @name Register SIM_FCFG1, field EESIZE[19:16] (RO)
- *
- * EEPROM data size .
- *
- * Values:
- * - 0000 - 16 KB
- * - 0001 - 8 KB
- * - 0010 - 4 KB
- * - 0011 - 2 KB
- * - 0100 - 1 KB
- * - 0101 - 512 Bytes
- * - 0110 - 256 Bytes
- * - 0111 - 128 Bytes
- * - 1000 - 64 Bytes
- * - 1001 - 32 Bytes
- * - 1111 - 0 Bytes
- */
-//@{
-#define BP_SIM_FCFG1_EESIZE (16U) //!< Bit position for SIM_FCFG1_EESIZE.
-#define BM_SIM_FCFG1_EESIZE (0x000F0000U) //!< Bit mask for SIM_FCFG1_EESIZE.
-#define BS_SIM_FCFG1_EESIZE (4U) //!< Bit field size in bits for SIM_FCFG1_EESIZE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_FCFG1_EESIZE field.
-#define BR_SIM_FCFG1_EESIZE (HW_SIM_FCFG1.B.EESIZE)
-#endif
-//@}
-
-/*!
- * @name Register SIM_FCFG1, field PFSIZE[27:24] (RO)
- *
- * This field specifies the amount of program flash memory available on the
- * device . Undefined values are reserved.
- *
- * Values:
- * - 0011 - 32 KB of program flash memory
- * - 0101 - 64 KB of program flash memory
- * - 0111 - 128 KB of program flash memory
- * - 1001 - 256 KB of program flash memory
- * - 1011 - 512 KB of program flash memory
- * - 1101 - 1024 KB of program flash memory
- * - 1111 - 1024 KB of program flash memory
- */
-//@{
-#define BP_SIM_FCFG1_PFSIZE (24U) //!< Bit position for SIM_FCFG1_PFSIZE.
-#define BM_SIM_FCFG1_PFSIZE (0x0F000000U) //!< Bit mask for SIM_FCFG1_PFSIZE.
-#define BS_SIM_FCFG1_PFSIZE (4U) //!< Bit field size in bits for SIM_FCFG1_PFSIZE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_FCFG1_PFSIZE field.
-#define BR_SIM_FCFG1_PFSIZE (HW_SIM_FCFG1.B.PFSIZE)
-#endif
-//@}
-
-/*!
- * @name Register SIM_FCFG1, field NVMSIZE[31:28] (RO)
- *
- * This field specifies the amount of FlexNVM memory available on the device .
- * Undefined values are reserved.
- *
- * Values:
- * - 0000 - 0 KB of FlexNVM
- * - 0011 - 32 KB of FlexNVM
- * - 0101 - 64 KB of FlexNVM
- * - 0111 - 128 KB of FlexNVM
- * - 1001 - 256 KB of FlexNVM
- * - 1011 - 512 KB of FlexNVM
- * - 1111 - 512 KB of FlexNVM
- */
-//@{
-#define BP_SIM_FCFG1_NVMSIZE (28U) //!< Bit position for SIM_FCFG1_NVMSIZE.
-#define BM_SIM_FCFG1_NVMSIZE (0xF0000000U) //!< Bit mask for SIM_FCFG1_NVMSIZE.
-#define BS_SIM_FCFG1_NVMSIZE (4U) //!< Bit field size in bits for SIM_FCFG1_NVMSIZE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_FCFG1_NVMSIZE field.
-#define BR_SIM_FCFG1_NVMSIZE (HW_SIM_FCFG1.B.NVMSIZE)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SIM_FCFG2 - Flash Configuration Register 2
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SIM_FCFG2 - Flash Configuration Register 2 (RO)
- *
- * Reset value: 0x7F7F0000U
- */
-typedef union _hw_sim_fcfg2
-{
- uint32_t U;
- struct _hw_sim_fcfg2_bitfields
- {
- uint32_t RESERVED0 : 16; //!< [15:0]
- uint32_t MAXADDR1 : 7; //!< [22:16] Max address block 1
- uint32_t PFLSH : 1; //!< [23] Program flash only
- uint32_t MAXADDR0 : 7; //!< [30:24] Max address block 0
- uint32_t RESERVED1 : 1; //!< [31]
- } B;
-} hw_sim_fcfg2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SIM_FCFG2 register
- */
-//@{
-#define HW_SIM_FCFG2_ADDR (REGS_SIM_BASE + 0x1050U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SIM_FCFG2 (*(__I hw_sim_fcfg2_t *) HW_SIM_FCFG2_ADDR)
-#define HW_SIM_FCFG2_RD() (HW_SIM_FCFG2.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual SIM_FCFG2 bitfields
- */
-
-/*!
- * @name Register SIM_FCFG2, field MAXADDR1[22:16] (RO)
- *
- * For devices with FlexNVM: This field concatenated with 13 trailing zeros plus
- * the FlexNVM base address indicates the first invalid address of the FlexNVM
- * flash block. For example, if MAXADDR1 = 0x20 the first invalid address of
- * FlexNVM flash block is 0x4_0000 + 0x1000_0000 . This would be the MAXADDR1 value
- * for a device with 256 KB FlexNVM. For devices with program flash only: This
- * field equals zero if there is only one program flash block, otherwise it equals
- * the value of the MAXADDR0 field. For example, with MAXADDR0 = MAXADDR1 = 0x20
- * the first invalid address of flash block 1 is 0x4_0000 + 0x4_0000. This would be
- * the MAXADDR1 value for a device with 512 KB program flash memory across two
- * flash blocks and no FlexNVM.
- */
-//@{
-#define BP_SIM_FCFG2_MAXADDR1 (16U) //!< Bit position for SIM_FCFG2_MAXADDR1.
-#define BM_SIM_FCFG2_MAXADDR1 (0x007F0000U) //!< Bit mask for SIM_FCFG2_MAXADDR1.
-#define BS_SIM_FCFG2_MAXADDR1 (7U) //!< Bit field size in bits for SIM_FCFG2_MAXADDR1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_FCFG2_MAXADDR1 field.
-#define BR_SIM_FCFG2_MAXADDR1 (HW_SIM_FCFG2.B.MAXADDR1)
-#endif
-//@}
-
-/*!
- * @name Register SIM_FCFG2, field PFLSH[23] (RO)
- *
- * For devices with FlexNVM, this bit is always clear. For devices without
- * FlexNVM, this bit is always set.
- *
- * Values:
- * - 0 - Device supports FlexNVM
- * - 1 - Program Flash only, device does not support FlexNVM
- */
-//@{
-#define BP_SIM_FCFG2_PFLSH (23U) //!< Bit position for SIM_FCFG2_PFLSH.
-#define BM_SIM_FCFG2_PFLSH (0x00800000U) //!< Bit mask for SIM_FCFG2_PFLSH.
-#define BS_SIM_FCFG2_PFLSH (1U) //!< Bit field size in bits for SIM_FCFG2_PFLSH.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_FCFG2_PFLSH field.
-#define BR_SIM_FCFG2_PFLSH (BITBAND_ACCESS32(HW_SIM_FCFG2_ADDR, BP_SIM_FCFG2_PFLSH))
-#endif
-//@}
-
-/*!
- * @name Register SIM_FCFG2, field MAXADDR0[30:24] (RO)
- *
- * This field concatenated with 13 trailing zeros indicates the first invalid
- * address of each program flash block. For example, if MAXADDR0 = 0x20 the first
- * invalid address of flash block 0 is 0x0004_0000. This would be the MAXADDR0
- * value for a device with 256 KB program flash in flash block 0.
- */
-//@{
-#define BP_SIM_FCFG2_MAXADDR0 (24U) //!< Bit position for SIM_FCFG2_MAXADDR0.
-#define BM_SIM_FCFG2_MAXADDR0 (0x7F000000U) //!< Bit mask for SIM_FCFG2_MAXADDR0.
-#define BS_SIM_FCFG2_MAXADDR0 (7U) //!< Bit field size in bits for SIM_FCFG2_MAXADDR0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_FCFG2_MAXADDR0 field.
-#define BR_SIM_FCFG2_MAXADDR0 (HW_SIM_FCFG2.B.MAXADDR0)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SIM_UIDH - Unique Identification Register High
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SIM_UIDH - Unique Identification Register High (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_sim_uidh
-{
- uint32_t U;
- struct _hw_sim_uidh_bitfields
- {
- uint32_t UID : 32; //!< [31:0] Unique Identification
- } B;
-} hw_sim_uidh_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SIM_UIDH register
- */
-//@{
-#define HW_SIM_UIDH_ADDR (REGS_SIM_BASE + 0x1054U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SIM_UIDH (*(__I hw_sim_uidh_t *) HW_SIM_UIDH_ADDR)
-#define HW_SIM_UIDH_RD() (HW_SIM_UIDH.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual SIM_UIDH bitfields
- */
-
-/*!
- * @name Register SIM_UIDH, field UID[31:0] (RO)
- *
- * Unique identification for the device.
- */
-//@{
-#define BP_SIM_UIDH_UID (0U) //!< Bit position for SIM_UIDH_UID.
-#define BM_SIM_UIDH_UID (0xFFFFFFFFU) //!< Bit mask for SIM_UIDH_UID.
-#define BS_SIM_UIDH_UID (32U) //!< Bit field size in bits for SIM_UIDH_UID.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_UIDH_UID field.
-#define BR_SIM_UIDH_UID (HW_SIM_UIDH.U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SIM_UIDMH - Unique Identification Register Mid-High
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SIM_UIDMH - Unique Identification Register Mid-High (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_sim_uidmh
-{
- uint32_t U;
- struct _hw_sim_uidmh_bitfields
- {
- uint32_t UID : 32; //!< [31:0] Unique Identification
- } B;
-} hw_sim_uidmh_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SIM_UIDMH register
- */
-//@{
-#define HW_SIM_UIDMH_ADDR (REGS_SIM_BASE + 0x1058U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SIM_UIDMH (*(__I hw_sim_uidmh_t *) HW_SIM_UIDMH_ADDR)
-#define HW_SIM_UIDMH_RD() (HW_SIM_UIDMH.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual SIM_UIDMH bitfields
- */
-
-/*!
- * @name Register SIM_UIDMH, field UID[31:0] (RO)
- *
- * Unique identification for the device.
- */
-//@{
-#define BP_SIM_UIDMH_UID (0U) //!< Bit position for SIM_UIDMH_UID.
-#define BM_SIM_UIDMH_UID (0xFFFFFFFFU) //!< Bit mask for SIM_UIDMH_UID.
-#define BS_SIM_UIDMH_UID (32U) //!< Bit field size in bits for SIM_UIDMH_UID.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_UIDMH_UID field.
-#define BR_SIM_UIDMH_UID (HW_SIM_UIDMH.U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SIM_UIDML - Unique Identification Register Mid Low
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SIM_UIDML - Unique Identification Register Mid Low (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_sim_uidml
-{
- uint32_t U;
- struct _hw_sim_uidml_bitfields
- {
- uint32_t UID : 32; //!< [31:0] Unique Identification
- } B;
-} hw_sim_uidml_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SIM_UIDML register
- */
-//@{
-#define HW_SIM_UIDML_ADDR (REGS_SIM_BASE + 0x105CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SIM_UIDML (*(__I hw_sim_uidml_t *) HW_SIM_UIDML_ADDR)
-#define HW_SIM_UIDML_RD() (HW_SIM_UIDML.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual SIM_UIDML bitfields
- */
-
-/*!
- * @name Register SIM_UIDML, field UID[31:0] (RO)
- *
- * Unique identification for the device.
- */
-//@{
-#define BP_SIM_UIDML_UID (0U) //!< Bit position for SIM_UIDML_UID.
-#define BM_SIM_UIDML_UID (0xFFFFFFFFU) //!< Bit mask for SIM_UIDML_UID.
-#define BS_SIM_UIDML_UID (32U) //!< Bit field size in bits for SIM_UIDML_UID.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_UIDML_UID field.
-#define BR_SIM_UIDML_UID (HW_SIM_UIDML.U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SIM_UIDL - Unique Identification Register Low
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SIM_UIDL - Unique Identification Register Low (RO)
- *
- * Reset value: 0x00000000U
- */
-typedef union _hw_sim_uidl
-{
- uint32_t U;
- struct _hw_sim_uidl_bitfields
- {
- uint32_t UID : 32; //!< [31:0] Unique Identification
- } B;
-} hw_sim_uidl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SIM_UIDL register
- */
-//@{
-#define HW_SIM_UIDL_ADDR (REGS_SIM_BASE + 0x1060U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SIM_UIDL (*(__I hw_sim_uidl_t *) HW_SIM_UIDL_ADDR)
-#define HW_SIM_UIDL_RD() (HW_SIM_UIDL.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual SIM_UIDL bitfields
- */
-
-/*!
- * @name Register SIM_UIDL, field UID[31:0] (RO)
- *
- * Unique identification for the device.
- */
-//@{
-#define BP_SIM_UIDL_UID (0U) //!< Bit position for SIM_UIDL_UID.
-#define BM_SIM_UIDL_UID (0xFFFFFFFFU) //!< Bit mask for SIM_UIDL_UID.
-#define BS_SIM_UIDL_UID (32U) //!< Bit field size in bits for SIM_UIDL_UID.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SIM_UIDL_UID field.
-#define BR_SIM_UIDL_UID (HW_SIM_UIDL.U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_sim_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All SIM module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_sim
-{
- __IO hw_sim_sopt1_t SOPT1; //!< [0x0] System Options Register 1
- __IO hw_sim_sopt1cfg_t SOPT1CFG; //!< [0x4] SOPT1 Configuration Register
- uint8_t _reserved0[4092];
- __IO hw_sim_sopt2_t SOPT2; //!< [0x1004] System Options Register 2
- uint8_t _reserved1[4];
- __IO hw_sim_sopt4_t SOPT4; //!< [0x100C] System Options Register 4
- __IO hw_sim_sopt5_t SOPT5; //!< [0x1010] System Options Register 5
- uint8_t _reserved2[4];
- __IO hw_sim_sopt7_t SOPT7; //!< [0x1018] System Options Register 7
- uint8_t _reserved3[8];
- __I hw_sim_sdid_t SDID; //!< [0x1024] System Device Identification Register
- __IO hw_sim_scgc1_t SCGC1; //!< [0x1028] System Clock Gating Control Register 1
- __IO hw_sim_scgc2_t SCGC2; //!< [0x102C] System Clock Gating Control Register 2
- __IO hw_sim_scgc3_t SCGC3; //!< [0x1030] System Clock Gating Control Register 3
- __IO hw_sim_scgc4_t SCGC4; //!< [0x1034] System Clock Gating Control Register 4
- __IO hw_sim_scgc5_t SCGC5; //!< [0x1038] System Clock Gating Control Register 5
- __IO hw_sim_scgc6_t SCGC6; //!< [0x103C] System Clock Gating Control Register 6
- __IO hw_sim_scgc7_t SCGC7; //!< [0x1040] System Clock Gating Control Register 7
- __IO hw_sim_clkdiv1_t CLKDIV1; //!< [0x1044] System Clock Divider Register 1
- __IO hw_sim_clkdiv2_t CLKDIV2; //!< [0x1048] System Clock Divider Register 2
- __IO hw_sim_fcfg1_t FCFG1; //!< [0x104C] Flash Configuration Register 1
- __I hw_sim_fcfg2_t FCFG2; //!< [0x1050] Flash Configuration Register 2
- __I hw_sim_uidh_t UIDH; //!< [0x1054] Unique Identification Register High
- __I hw_sim_uidmh_t UIDMH; //!< [0x1058] Unique Identification Register Mid-High
- __I hw_sim_uidml_t UIDML; //!< [0x105C] Unique Identification Register Mid Low
- __I hw_sim_uidl_t UIDL; //!< [0x1060] Unique Identification Register Low
-} hw_sim_t;
-#pragma pack()
-
-//! @brief Macro to access all SIM registers.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_SIM</code>.
-#define HW_SIM (*(hw_sim_t *) REGS_SIM_BASE)
-#endif
-
-#endif // __HW_SIM_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_smc.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,566 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_SMC_REGISTERS_H__
-#define __HW_SMC_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 SMC
- *
- * System Mode Controller
- *
- * Registers defined in this header file:
- * - HW_SMC_PMPROT - Power Mode Protection register
- * - HW_SMC_PMCTRL - Power Mode Control register
- * - HW_SMC_VLLSCTRL - VLLS Control register
- * - HW_SMC_PMSTAT - Power Mode Status register
- *
- * - hw_smc_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_SMC_BASE
-#define HW_SMC_INSTANCE_COUNT (1U) //!< Number of instances of the SMC module.
-#define REGS_SMC_BASE (0x4007E000U) //!< Base address for SMC.
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SMC_PMPROT - Power Mode Protection register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SMC_PMPROT - Power Mode Protection register (RW)
- *
- * Reset value: 0x00U
- *
- * This register provides protection for entry into any low-power run or stop
- * mode. The enabling of the low-power run or stop mode occurs by configuring the
- * Power Mode Control register (PMCTRL). The PMPROT register can be written only
- * once after any system reset. If the MCU is configured for a disallowed or
- * reserved power mode, the MCU remains in its current power mode. For example, if the
- * MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using
- * PMCTRL[RUNM] is blocked and PMCTRL[RUNM] remains 00b, indicating the MCU is
- * still in Normal Run mode. This register is reset on Chip Reset not VLLS and by
- * reset types that trigger Chip Reset not VLLS. It is unaffected by reset types
- * that do not trigger Chip Reset not VLLS. See the Reset section details for more
- * information.
- */
-typedef union _hw_smc_pmprot
-{
- uint8_t U;
- struct _hw_smc_pmprot_bitfields
- {
- uint8_t RESERVED0 : 1; //!< [0]
- uint8_t AVLLS : 1; //!< [1] Allow Very-Low-Leakage Stop Mode
- uint8_t RESERVED1 : 1; //!< [2]
- uint8_t ALLS : 1; //!< [3] Allow Low-Leakage Stop Mode
- uint8_t RESERVED2 : 1; //!< [4]
- uint8_t AVLP : 1; //!< [5] Allow Very-Low-Power Modes
- uint8_t RESERVED3 : 2; //!< [7:6]
- } B;
-} hw_smc_pmprot_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SMC_PMPROT register
- */
-//@{
-#define HW_SMC_PMPROT_ADDR (REGS_SMC_BASE + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SMC_PMPROT (*(__IO hw_smc_pmprot_t *) HW_SMC_PMPROT_ADDR)
-#define HW_SMC_PMPROT_RD() (HW_SMC_PMPROT.U)
-#define HW_SMC_PMPROT_WR(v) (HW_SMC_PMPROT.U = (v))
-#define HW_SMC_PMPROT_SET(v) (HW_SMC_PMPROT_WR(HW_SMC_PMPROT_RD() | (v)))
-#define HW_SMC_PMPROT_CLR(v) (HW_SMC_PMPROT_WR(HW_SMC_PMPROT_RD() & ~(v)))
-#define HW_SMC_PMPROT_TOG(v) (HW_SMC_PMPROT_WR(HW_SMC_PMPROT_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SMC_PMPROT bitfields
- */
-
-/*!
- * @name Register SMC_PMPROT, field AVLLS[1] (RW)
- *
- * Provided the appropriate control bits are set up in PMCTRL, this write once
- * bit allows the MCU to enter any very-low-leakage stop mode (VLLSx).
- *
- * Values:
- * - 0 - Any VLLSx mode is not allowed
- * - 1 - Any VLLSx mode is allowed
- */
-//@{
-#define BP_SMC_PMPROT_AVLLS (1U) //!< Bit position for SMC_PMPROT_AVLLS.
-#define BM_SMC_PMPROT_AVLLS (0x02U) //!< Bit mask for SMC_PMPROT_AVLLS.
-#define BS_SMC_PMPROT_AVLLS (1U) //!< Bit field size in bits for SMC_PMPROT_AVLLS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SMC_PMPROT_AVLLS field.
-#define BR_SMC_PMPROT_AVLLS (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_AVLLS))
-#endif
-
-//! @brief Format value for bitfield SMC_PMPROT_AVLLS.
-#define BF_SMC_PMPROT_AVLLS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMPROT_AVLLS), uint8_t) & BM_SMC_PMPROT_AVLLS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the AVLLS field to a new value.
-#define BW_SMC_PMPROT_AVLLS(v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_AVLLS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SMC_PMPROT, field ALLS[3] (RW)
- *
- * Provided the appropriate control bits are set up in PMCTRL, this write-once
- * field allows the MCU to enter any low-leakage stop mode (LLS).
- *
- * Values:
- * - 0 - LLS is not allowed
- * - 1 - LLS is allowed
- */
-//@{
-#define BP_SMC_PMPROT_ALLS (3U) //!< Bit position for SMC_PMPROT_ALLS.
-#define BM_SMC_PMPROT_ALLS (0x08U) //!< Bit mask for SMC_PMPROT_ALLS.
-#define BS_SMC_PMPROT_ALLS (1U) //!< Bit field size in bits for SMC_PMPROT_ALLS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SMC_PMPROT_ALLS field.
-#define BR_SMC_PMPROT_ALLS (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_ALLS))
-#endif
-
-//! @brief Format value for bitfield SMC_PMPROT_ALLS.
-#define BF_SMC_PMPROT_ALLS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMPROT_ALLS), uint8_t) & BM_SMC_PMPROT_ALLS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ALLS field to a new value.
-#define BW_SMC_PMPROT_ALLS(v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_ALLS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SMC_PMPROT, field AVLP[5] (RW)
- *
- * Provided the appropriate control bits are set up in PMCTRL, this write-once
- * field allows the MCU to enter any very-low-power mode (VLPR, VLPW, and VLPS).
- *
- * Values:
- * - 0 - VLPR, VLPW, and VLPS are not allowed.
- * - 1 - VLPR, VLPW, and VLPS are allowed.
- */
-//@{
-#define BP_SMC_PMPROT_AVLP (5U) //!< Bit position for SMC_PMPROT_AVLP.
-#define BM_SMC_PMPROT_AVLP (0x20U) //!< Bit mask for SMC_PMPROT_AVLP.
-#define BS_SMC_PMPROT_AVLP (1U) //!< Bit field size in bits for SMC_PMPROT_AVLP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SMC_PMPROT_AVLP field.
-#define BR_SMC_PMPROT_AVLP (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_AVLP))
-#endif
-
-//! @brief Format value for bitfield SMC_PMPROT_AVLP.
-#define BF_SMC_PMPROT_AVLP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMPROT_AVLP), uint8_t) & BM_SMC_PMPROT_AVLP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the AVLP field to a new value.
-#define BW_SMC_PMPROT_AVLP(v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_AVLP) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SMC_PMCTRL - Power Mode Control register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SMC_PMCTRL - Power Mode Control register (RW)
- *
- * Reset value: 0x00U
- *
- * The PMCTRL register controls entry into low-power Run and Stop modes,
- * provided that the selected power mode is allowed via an appropriate setting of the
- * protection (PMPROT) register. This register is reset on Chip POR not VLLS and by
- * reset types that trigger Chip POR not VLLS. It is unaffected by reset types
- * that do not trigger Chip POR not VLLS. See the Reset section details for more
- * information.
- */
-typedef union _hw_smc_pmctrl
-{
- uint8_t U;
- struct _hw_smc_pmctrl_bitfields
- {
- uint8_t STOPM : 3; //!< [2:0] Stop Mode Control
- uint8_t STOPA : 1; //!< [3] Stop Aborted
- uint8_t RESERVED0 : 1; //!< [4]
- uint8_t RUNM : 2; //!< [6:5] Run Mode Control
- uint8_t LPWUI : 1; //!< [7] Low-Power Wake Up On Interrupt
- } B;
-} hw_smc_pmctrl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SMC_PMCTRL register
- */
-//@{
-#define HW_SMC_PMCTRL_ADDR (REGS_SMC_BASE + 0x1U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SMC_PMCTRL (*(__IO hw_smc_pmctrl_t *) HW_SMC_PMCTRL_ADDR)
-#define HW_SMC_PMCTRL_RD() (HW_SMC_PMCTRL.U)
-#define HW_SMC_PMCTRL_WR(v) (HW_SMC_PMCTRL.U = (v))
-#define HW_SMC_PMCTRL_SET(v) (HW_SMC_PMCTRL_WR(HW_SMC_PMCTRL_RD() | (v)))
-#define HW_SMC_PMCTRL_CLR(v) (HW_SMC_PMCTRL_WR(HW_SMC_PMCTRL_RD() & ~(v)))
-#define HW_SMC_PMCTRL_TOG(v) (HW_SMC_PMCTRL_WR(HW_SMC_PMCTRL_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SMC_PMCTRL bitfields
- */
-
-/*!
- * @name Register SMC_PMCTRL, field STOPM[2:0] (RW)
- *
- * When written, controls entry into the selected stop mode when Sleep-Now or
- * Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are
- * blocked if the protection level has not been enabled using the PMPROT register.
- * After any system reset, this field is cleared by hardware on any successful write
- * to the PMPROT register. When set to VLLSx, the VLLSM field in the VLLSCTRL
- * register is used to further select the particular VLLS submode which will be
- * entered.
- *
- * Values:
- * - 000 - Normal Stop (STOP)
- * - 001 - Reserved
- * - 010 - Very-Low-Power Stop (VLPS)
- * - 011 - Low-Leakage Stop (LLS)
- * - 100 - Very-Low-Leakage Stop (VLLSx)
- * - 101 - Reserved
- * - 110 - Reseved
- * - 111 - Reserved
- */
-//@{
-#define BP_SMC_PMCTRL_STOPM (0U) //!< Bit position for SMC_PMCTRL_STOPM.
-#define BM_SMC_PMCTRL_STOPM (0x07U) //!< Bit mask for SMC_PMCTRL_STOPM.
-#define BS_SMC_PMCTRL_STOPM (3U) //!< Bit field size in bits for SMC_PMCTRL_STOPM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SMC_PMCTRL_STOPM field.
-#define BR_SMC_PMCTRL_STOPM (HW_SMC_PMCTRL.B.STOPM)
-#endif
-
-//! @brief Format value for bitfield SMC_PMCTRL_STOPM.
-#define BF_SMC_PMCTRL_STOPM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMCTRL_STOPM), uint8_t) & BM_SMC_PMCTRL_STOPM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the STOPM field to a new value.
-#define BW_SMC_PMCTRL_STOPM(v) (HW_SMC_PMCTRL_WR((HW_SMC_PMCTRL_RD() & ~BM_SMC_PMCTRL_STOPM) | BF_SMC_PMCTRL_STOPM(v)))
-#endif
-//@}
-
-/*!
- * @name Register SMC_PMCTRL, field STOPA[3] (RO)
- *
- * When set, this read-only status bit indicates an interrupt or reset occured
- * during the previous stop mode entry sequence, preventing the system from
- * entering that mode. This field is cleared by hardware at the beginning of any stop
- * mode entry sequence and is set if the sequence was aborted.
- *
- * Values:
- * - 0 - The previous stop mode entry was successsful.
- * - 1 - The previous stop mode entry was aborted.
- */
-//@{
-#define BP_SMC_PMCTRL_STOPA (3U) //!< Bit position for SMC_PMCTRL_STOPA.
-#define BM_SMC_PMCTRL_STOPA (0x08U) //!< Bit mask for SMC_PMCTRL_STOPA.
-#define BS_SMC_PMCTRL_STOPA (1U) //!< Bit field size in bits for SMC_PMCTRL_STOPA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SMC_PMCTRL_STOPA field.
-#define BR_SMC_PMCTRL_STOPA (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR, BP_SMC_PMCTRL_STOPA))
-#endif
-//@}
-
-/*!
- * @name Register SMC_PMCTRL, field RUNM[6:5] (RW)
- *
- * When written, causes entry into the selected run mode. Writes to this field
- * are blocked if the protection level has not been enabled using the PMPROT
- * register. RUNM may be set to VLPR only when PMSTAT=RUN. After being written to
- * VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR.
- *
- * Values:
- * - 00 - Normal Run mode (RUN)
- * - 01 - Reserved
- * - 10 - Very-Low-Power Run mode (VLPR)
- * - 11 - Reserved
- */
-//@{
-#define BP_SMC_PMCTRL_RUNM (5U) //!< Bit position for SMC_PMCTRL_RUNM.
-#define BM_SMC_PMCTRL_RUNM (0x60U) //!< Bit mask for SMC_PMCTRL_RUNM.
-#define BS_SMC_PMCTRL_RUNM (2U) //!< Bit field size in bits for SMC_PMCTRL_RUNM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SMC_PMCTRL_RUNM field.
-#define BR_SMC_PMCTRL_RUNM (HW_SMC_PMCTRL.B.RUNM)
-#endif
-
-//! @brief Format value for bitfield SMC_PMCTRL_RUNM.
-#define BF_SMC_PMCTRL_RUNM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMCTRL_RUNM), uint8_t) & BM_SMC_PMCTRL_RUNM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RUNM field to a new value.
-#define BW_SMC_PMCTRL_RUNM(v) (HW_SMC_PMCTRL_WR((HW_SMC_PMCTRL_RD() & ~BM_SMC_PMCTRL_RUNM) | BF_SMC_PMCTRL_RUNM(v)))
-#endif
-//@}
-
-/*!
- * @name Register SMC_PMCTRL, field LPWUI[7] (RW)
- *
- * Causes the SMC to exit to normal RUN mode when any active MCU interrupt
- * occurs while in a VLP mode (VLPR, VLPW or VLPS). If VLPS mode was entered directly
- * from RUN mode, the SMC will always exit back to normal RUN mode regardless of
- * the LPWUI setting. LPWUI must be modified only while the system is in RUN
- * mode, that is, when PMSTAT=RUN.
- *
- * Values:
- * - 0 - The system remains in a VLP mode on an interrupt
- * - 1 - The system exits to Normal RUN mode on an interrupt
- */
-//@{
-#define BP_SMC_PMCTRL_LPWUI (7U) //!< Bit position for SMC_PMCTRL_LPWUI.
-#define BM_SMC_PMCTRL_LPWUI (0x80U) //!< Bit mask for SMC_PMCTRL_LPWUI.
-#define BS_SMC_PMCTRL_LPWUI (1U) //!< Bit field size in bits for SMC_PMCTRL_LPWUI.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SMC_PMCTRL_LPWUI field.
-#define BR_SMC_PMCTRL_LPWUI (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR, BP_SMC_PMCTRL_LPWUI))
-#endif
-
-//! @brief Format value for bitfield SMC_PMCTRL_LPWUI.
-#define BF_SMC_PMCTRL_LPWUI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMCTRL_LPWUI), uint8_t) & BM_SMC_PMCTRL_LPWUI)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LPWUI field to a new value.
-#define BW_SMC_PMCTRL_LPWUI(v) (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR, BP_SMC_PMCTRL_LPWUI) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SMC_VLLSCTRL - VLLS Control register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SMC_VLLSCTRL - VLLS Control register (RW)
- *
- * Reset value: 0x03U
- *
- * The VLLSCTRL register controls features related to VLLS modes. This register
- * is reset on Chip POR not VLLS and by reset types that trigger Chip POR not
- * VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See
- * the Reset section details for more information.
- */
-typedef union _hw_smc_vllsctrl
-{
- uint8_t U;
- struct _hw_smc_vllsctrl_bitfields
- {
- uint8_t VLLSM : 3; //!< [2:0] VLLS Mode Control
- uint8_t RESERVED0 : 2; //!< [4:3]
- uint8_t PORPO : 1; //!< [5] POR Power Option
- uint8_t RESERVED1 : 2; //!< [7:6]
- } B;
-} hw_smc_vllsctrl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SMC_VLLSCTRL register
- */
-//@{
-#define HW_SMC_VLLSCTRL_ADDR (REGS_SMC_BASE + 0x2U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SMC_VLLSCTRL (*(__IO hw_smc_vllsctrl_t *) HW_SMC_VLLSCTRL_ADDR)
-#define HW_SMC_VLLSCTRL_RD() (HW_SMC_VLLSCTRL.U)
-#define HW_SMC_VLLSCTRL_WR(v) (HW_SMC_VLLSCTRL.U = (v))
-#define HW_SMC_VLLSCTRL_SET(v) (HW_SMC_VLLSCTRL_WR(HW_SMC_VLLSCTRL_RD() | (v)))
-#define HW_SMC_VLLSCTRL_CLR(v) (HW_SMC_VLLSCTRL_WR(HW_SMC_VLLSCTRL_RD() & ~(v)))
-#define HW_SMC_VLLSCTRL_TOG(v) (HW_SMC_VLLSCTRL_WR(HW_SMC_VLLSCTRL_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SMC_VLLSCTRL bitfields
- */
-
-/*!
- * @name Register SMC_VLLSCTRL, field VLLSM[2:0] (RW)
- *
- * Controls which VLLS sub-mode to enter if STOPM=VLLS.
- *
- * Values:
- * - 000 - VLLS0
- * - 001 - VLLS1
- * - 010 - VLLS2
- * - 011 - VLLS3
- * - 100 - Reserved
- * - 101 - Reserved
- * - 110 - Reserved
- * - 111 - Reserved
- */
-//@{
-#define BP_SMC_VLLSCTRL_VLLSM (0U) //!< Bit position for SMC_VLLSCTRL_VLLSM.
-#define BM_SMC_VLLSCTRL_VLLSM (0x07U) //!< Bit mask for SMC_VLLSCTRL_VLLSM.
-#define BS_SMC_VLLSCTRL_VLLSM (3U) //!< Bit field size in bits for SMC_VLLSCTRL_VLLSM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SMC_VLLSCTRL_VLLSM field.
-#define BR_SMC_VLLSCTRL_VLLSM (HW_SMC_VLLSCTRL.B.VLLSM)
-#endif
-
-//! @brief Format value for bitfield SMC_VLLSCTRL_VLLSM.
-#define BF_SMC_VLLSCTRL_VLLSM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_VLLSCTRL_VLLSM), uint8_t) & BM_SMC_VLLSCTRL_VLLSM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the VLLSM field to a new value.
-#define BW_SMC_VLLSCTRL_VLLSM(v) (HW_SMC_VLLSCTRL_WR((HW_SMC_VLLSCTRL_RD() & ~BM_SMC_VLLSCTRL_VLLSM) | BF_SMC_VLLSCTRL_VLLSM(v)))
-#endif
-//@}
-
-/*!
- * @name Register SMC_VLLSCTRL, field PORPO[5] (RW)
- *
- * Controls whether the POR detect circuit (for brown-out detection) is enabled
- * in VLLS0 mode.
- *
- * Values:
- * - 0 - POR detect circuit is enabled in VLLS0.
- * - 1 - POR detect circuit is disabled in VLLS0.
- */
-//@{
-#define BP_SMC_VLLSCTRL_PORPO (5U) //!< Bit position for SMC_VLLSCTRL_PORPO.
-#define BM_SMC_VLLSCTRL_PORPO (0x20U) //!< Bit mask for SMC_VLLSCTRL_PORPO.
-#define BS_SMC_VLLSCTRL_PORPO (1U) //!< Bit field size in bits for SMC_VLLSCTRL_PORPO.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SMC_VLLSCTRL_PORPO field.
-#define BR_SMC_VLLSCTRL_PORPO (BITBAND_ACCESS8(HW_SMC_VLLSCTRL_ADDR, BP_SMC_VLLSCTRL_PORPO))
-#endif
-
-//! @brief Format value for bitfield SMC_VLLSCTRL_PORPO.
-#define BF_SMC_VLLSCTRL_PORPO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_VLLSCTRL_PORPO), uint8_t) & BM_SMC_VLLSCTRL_PORPO)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PORPO field to a new value.
-#define BW_SMC_VLLSCTRL_PORPO(v) (BITBAND_ACCESS8(HW_SMC_VLLSCTRL_ADDR, BP_SMC_VLLSCTRL_PORPO) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SMC_PMSTAT - Power Mode Status register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SMC_PMSTAT - Power Mode Status register (RO)
- *
- * Reset value: 0x01U
- *
- * PMSTAT is a read-only, one-hot register which indicates the current power
- * mode of the system. This register is reset on Chip POR not VLLS and by reset
- * types that trigger Chip POR not VLLS. It is unaffected by reset types that do not
- * trigger Chip POR not VLLS. See the Reset section details for more information.
- */
-typedef union _hw_smc_pmstat
-{
- uint8_t U;
- struct _hw_smc_pmstat_bitfields
- {
- uint8_t PMSTAT : 7; //!< [6:0]
- uint8_t RESERVED0 : 1; //!< [7]
- } B;
-} hw_smc_pmstat_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SMC_PMSTAT register
- */
-//@{
-#define HW_SMC_PMSTAT_ADDR (REGS_SMC_BASE + 0x3U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SMC_PMSTAT (*(__I hw_smc_pmstat_t *) HW_SMC_PMSTAT_ADDR)
-#define HW_SMC_PMSTAT_RD() (HW_SMC_PMSTAT.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual SMC_PMSTAT bitfields
- */
-
-/*!
- * @name Register SMC_PMSTAT, field PMSTAT[6:0] (RO)
- *
- * When debug is enabled, the PMSTAT will not update to STOP or VLPS
- */
-//@{
-#define BP_SMC_PMSTAT_PMSTAT (0U) //!< Bit position for SMC_PMSTAT_PMSTAT.
-#define BM_SMC_PMSTAT_PMSTAT (0x7FU) //!< Bit mask for SMC_PMSTAT_PMSTAT.
-#define BS_SMC_PMSTAT_PMSTAT (7U) //!< Bit field size in bits for SMC_PMSTAT_PMSTAT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SMC_PMSTAT_PMSTAT field.
-#define BR_SMC_PMSTAT_PMSTAT (HW_SMC_PMSTAT.B.PMSTAT)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_smc_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All SMC module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_smc
-{
- __IO hw_smc_pmprot_t PMPROT; //!< [0x0] Power Mode Protection register
- __IO hw_smc_pmctrl_t PMCTRL; //!< [0x1] Power Mode Control register
- __IO hw_smc_vllsctrl_t VLLSCTRL; //!< [0x2] VLLS Control register
- __I hw_smc_pmstat_t PMSTAT; //!< [0x3] Power Mode Status register
-} hw_smc_t;
-#pragma pack()
-
-//! @brief Macro to access all SMC registers.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_SMC</code>.
-#define HW_SMC (*(hw_smc_t *) REGS_SMC_BASE)
-#endif
-
-#endif // __HW_SMC_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_spi.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,2445 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_SPI_REGISTERS_H__
-#define __HW_SPI_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 SPI
- *
- * Serial Peripheral Interface
- *
- * Registers defined in this header file:
- * - HW_SPI_MCR - Module Configuration Register
- * - HW_SPI_TCR - Transfer Count Register
- * - HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode)
- * - HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
- * - HW_SPI_SR - Status Register
- * - HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register
- * - HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode
- * - HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
- * - HW_SPI_POPR - POP RX FIFO Register
- * - HW_SPI_TXFRn - Transmit FIFO Registers
- * - HW_SPI_RXFRn - Receive FIFO Registers
- *
- * - hw_spi_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_SPI_BASE
-#define HW_SPI_INSTANCE_COUNT (3U) //!< Number of instances of the SPI module.
-#define HW_SPI0 (0U) //!< Instance number for SPI0.
-#define HW_SPI1 (1U) //!< Instance number for SPI1.
-#define HW_SPI2 (2U) //!< Instance number for SPI2.
-#define REGS_SPI0_BASE (0x4002C000U) //!< Base address for SPI0.
-#define REGS_SPI1_BASE (0x4002D000U) //!< Base address for SPI1.
-#define REGS_SPI2_BASE (0x400AC000U) //!< Base address for SPI2.
-
-//! @brief Table of base addresses for SPI instances.
-static const uint32_t __g_regs_SPI_base_addresses[] = {
- REGS_SPI0_BASE,
- REGS_SPI1_BASE,
- REGS_SPI2_BASE,
- };
-
-//! @brief Get the base address of SPI by instance number.
-//! @param x SPI instance number, from 0 through 2.
-#define REGS_SPI_BASE(x) (__g_regs_SPI_base_addresses[(x)])
-
-//! @brief Get the instance number given a base address.
-//! @param b Base address for an instance of SPI.
-#define REGS_SPI_INSTANCE(b) ((b) == REGS_SPI0_BASE ? HW_SPI0 : (b) == REGS_SPI1_BASE ? HW_SPI1 : (b) == REGS_SPI2_BASE ? HW_SPI2 : 0)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SPI_MCR - Module Configuration Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SPI_MCR - Module Configuration Register (RW)
- *
- * Reset value: 0x00004001U
- *
- * Contains bits to configure various attributes associated with the module
- * operations. The HALT and MDIS bits can be changed at any time, but the effect
- * takes place only on the next frame boundary. Only the HALT and MDIS bits in the
- * MCR can be changed, while the module is in the Running state.
- */
-typedef union _hw_spi_mcr
-{
- uint32_t U;
- struct _hw_spi_mcr_bitfields
- {
- uint32_t HALT : 1; //!< [0] Halt
- uint32_t RESERVED0 : 7; //!< [7:1]
- uint32_t SMPL_PT : 2; //!< [9:8] Sample Point
- uint32_t CLR_RXF : 1; //!< [10]
- uint32_t CLR_TXF : 1; //!< [11] Clear TX FIFO
- uint32_t DIS_RXF : 1; //!< [12] Disable Receive FIFO
- uint32_t DIS_TXF : 1; //!< [13] Disable Transmit FIFO
- uint32_t MDIS : 1; //!< [14] Module Disable
- uint32_t DOZE : 1; //!< [15] Doze Enable
- uint32_t PCSIS : 6; //!< [21:16] Peripheral Chip Select x Inactive
- //! State
- uint32_t RESERVED1 : 2; //!< [23:22]
- uint32_t ROOE : 1; //!< [24] Receive FIFO Overflow Overwrite Enable
- uint32_t PCSSE : 1; //!< [25] Peripheral Chip Select Strobe Enable
- uint32_t MTFE : 1; //!< [26] Modified Timing Format Enable
- uint32_t FRZ : 1; //!< [27] Freeze
- uint32_t DCONF : 2; //!< [29:28] SPI Configuration.
- uint32_t CONT_SCKE : 1; //!< [30] Continuous SCK Enable
- uint32_t MSTR : 1; //!< [31] Master/Slave Mode Select
- } B;
-} hw_spi_mcr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SPI_MCR register
- */
-//@{
-#define HW_SPI_MCR_ADDR(x) (REGS_SPI_BASE(x) + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SPI_MCR(x) (*(__IO hw_spi_mcr_t *) HW_SPI_MCR_ADDR(x))
-#define HW_SPI_MCR_RD(x) (HW_SPI_MCR(x).U)
-#define HW_SPI_MCR_WR(x, v) (HW_SPI_MCR(x).U = (v))
-#define HW_SPI_MCR_SET(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) | (v)))
-#define HW_SPI_MCR_CLR(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) & ~(v)))
-#define HW_SPI_MCR_TOG(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SPI_MCR bitfields
- */
-
-/*!
- * @name Register SPI_MCR, field HALT[0] (RW)
- *
- * The HALT bit starts and stops frame transfers. See Start and Stop of Module
- * transfers
- *
- * Values:
- * - 0 - Start transfers.
- * - 1 - Stop transfers.
- */
-//@{
-#define BP_SPI_MCR_HALT (0U) //!< Bit position for SPI_MCR_HALT.
-#define BM_SPI_MCR_HALT (0x00000001U) //!< Bit mask for SPI_MCR_HALT.
-#define BS_SPI_MCR_HALT (1U) //!< Bit field size in bits for SPI_MCR_HALT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_MCR_HALT field.
-#define BR_SPI_MCR_HALT(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_HALT))
-#endif
-
-//! @brief Format value for bitfield SPI_MCR_HALT.
-#define BF_SPI_MCR_HALT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_HALT), uint32_t) & BM_SPI_MCR_HALT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the HALT field to a new value.
-#define BW_SPI_MCR_HALT(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_HALT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_MCR, field SMPL_PT[9:8] (RW)
- *
- * Controls when the module master samples SIN in Modified Transfer Format. This
- * field is valid only when CPHA bit in CTARn[CPHA] is 0.
- *
- * Values:
- * - 00 - 0 protocol clock cycles between SCK edge and SIN sample
- * - 01 - 1 protocol clock cycle between SCK edge and SIN sample
- * - 10 - 2 protocol clock cycles between SCK edge and SIN sample
- * - 11 - Reserved
- */
-//@{
-#define BP_SPI_MCR_SMPL_PT (8U) //!< Bit position for SPI_MCR_SMPL_PT.
-#define BM_SPI_MCR_SMPL_PT (0x00000300U) //!< Bit mask for SPI_MCR_SMPL_PT.
-#define BS_SPI_MCR_SMPL_PT (2U) //!< Bit field size in bits for SPI_MCR_SMPL_PT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_MCR_SMPL_PT field.
-#define BR_SPI_MCR_SMPL_PT(x) (HW_SPI_MCR(x).B.SMPL_PT)
-#endif
-
-//! @brief Format value for bitfield SPI_MCR_SMPL_PT.
-#define BF_SPI_MCR_SMPL_PT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_SMPL_PT), uint32_t) & BM_SPI_MCR_SMPL_PT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SMPL_PT field to a new value.
-#define BW_SPI_MCR_SMPL_PT(x, v) (HW_SPI_MCR_WR(x, (HW_SPI_MCR_RD(x) & ~BM_SPI_MCR_SMPL_PT) | BF_SPI_MCR_SMPL_PT(v)))
-#endif
-//@}
-
-/*!
- * @name Register SPI_MCR, field CLR_RXF[10] (WORZ)
- *
- * Flushes the RX FIFO. Writing a 1 to CLR_RXF clears the RX Counter. The
- * CLR_RXF bit is always read as zero.
- *
- * Values:
- * - 0 - Do not clear the RX FIFO counter.
- * - 1 - Clear the RX FIFO counter.
- */
-//@{
-#define BP_SPI_MCR_CLR_RXF (10U) //!< Bit position for SPI_MCR_CLR_RXF.
-#define BM_SPI_MCR_CLR_RXF (0x00000400U) //!< Bit mask for SPI_MCR_CLR_RXF.
-#define BS_SPI_MCR_CLR_RXF (1U) //!< Bit field size in bits for SPI_MCR_CLR_RXF.
-
-//! @brief Format value for bitfield SPI_MCR_CLR_RXF.
-#define BF_SPI_MCR_CLR_RXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_CLR_RXF), uint32_t) & BM_SPI_MCR_CLR_RXF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CLR_RXF field to a new value.
-#define BW_SPI_MCR_CLR_RXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CLR_RXF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_MCR, field CLR_TXF[11] (WORZ)
- *
- * Flushes the TX FIFO. Writing a 1 to CLR_TXF clears the TX FIFO Counter. The
- * CLR_TXF bit is always read as zero.
- *
- * Values:
- * - 0 - Do not clear the TX FIFO counter.
- * - 1 - Clear the TX FIFO counter.
- */
-//@{
-#define BP_SPI_MCR_CLR_TXF (11U) //!< Bit position for SPI_MCR_CLR_TXF.
-#define BM_SPI_MCR_CLR_TXF (0x00000800U) //!< Bit mask for SPI_MCR_CLR_TXF.
-#define BS_SPI_MCR_CLR_TXF (1U) //!< Bit field size in bits for SPI_MCR_CLR_TXF.
-
-//! @brief Format value for bitfield SPI_MCR_CLR_TXF.
-#define BF_SPI_MCR_CLR_TXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_CLR_TXF), uint32_t) & BM_SPI_MCR_CLR_TXF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CLR_TXF field to a new value.
-#define BW_SPI_MCR_CLR_TXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CLR_TXF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_MCR, field DIS_RXF[12] (RW)
- *
- * When the RX FIFO is disabled, the receive part of the module operates as a
- * simplified double-buffered SPI. This bit can only be written when the MDIS bit
- * is cleared.
- *
- * Values:
- * - 0 - RX FIFO is enabled.
- * - 1 - RX FIFO is disabled.
- */
-//@{
-#define BP_SPI_MCR_DIS_RXF (12U) //!< Bit position for SPI_MCR_DIS_RXF.
-#define BM_SPI_MCR_DIS_RXF (0x00001000U) //!< Bit mask for SPI_MCR_DIS_RXF.
-#define BS_SPI_MCR_DIS_RXF (1U) //!< Bit field size in bits for SPI_MCR_DIS_RXF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_MCR_DIS_RXF field.
-#define BR_SPI_MCR_DIS_RXF(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_RXF))
-#endif
-
-//! @brief Format value for bitfield SPI_MCR_DIS_RXF.
-#define BF_SPI_MCR_DIS_RXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_DIS_RXF), uint32_t) & BM_SPI_MCR_DIS_RXF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DIS_RXF field to a new value.
-#define BW_SPI_MCR_DIS_RXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_RXF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_MCR, field DIS_TXF[13] (RW)
- *
- * When the TX FIFO is disabled, the transmit part of the module operates as a
- * simplified double-buffered SPI. This bit can be written only when the MDIS bit
- * is cleared.
- *
- * Values:
- * - 0 - TX FIFO is enabled.
- * - 1 - TX FIFO is disabled.
- */
-//@{
-#define BP_SPI_MCR_DIS_TXF (13U) //!< Bit position for SPI_MCR_DIS_TXF.
-#define BM_SPI_MCR_DIS_TXF (0x00002000U) //!< Bit mask for SPI_MCR_DIS_TXF.
-#define BS_SPI_MCR_DIS_TXF (1U) //!< Bit field size in bits for SPI_MCR_DIS_TXF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_MCR_DIS_TXF field.
-#define BR_SPI_MCR_DIS_TXF(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_TXF))
-#endif
-
-//! @brief Format value for bitfield SPI_MCR_DIS_TXF.
-#define BF_SPI_MCR_DIS_TXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_DIS_TXF), uint32_t) & BM_SPI_MCR_DIS_TXF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DIS_TXF field to a new value.
-#define BW_SPI_MCR_DIS_TXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_TXF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_MCR, field MDIS[14] (RW)
- *
- * Allows the clock to be stopped to the non-memory mapped logic in the module
- * effectively putting it in a software-controlled power-saving state. The reset
- * value of the MDIS bit is parameterized, with a default reset value of 0. When
- * the module is used in Slave Mode, we recommend leaving this bit 0, because a
- * slave doesn't have control over master transactions.
- *
- * Values:
- * - 0 - Enables the module clocks.
- * - 1 - Allows external logic to disable the module clocks.
- */
-//@{
-#define BP_SPI_MCR_MDIS (14U) //!< Bit position for SPI_MCR_MDIS.
-#define BM_SPI_MCR_MDIS (0x00004000U) //!< Bit mask for SPI_MCR_MDIS.
-#define BS_SPI_MCR_MDIS (1U) //!< Bit field size in bits for SPI_MCR_MDIS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_MCR_MDIS field.
-#define BR_SPI_MCR_MDIS(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MDIS))
-#endif
-
-//! @brief Format value for bitfield SPI_MCR_MDIS.
-#define BF_SPI_MCR_MDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_MDIS), uint32_t) & BM_SPI_MCR_MDIS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MDIS field to a new value.
-#define BW_SPI_MCR_MDIS(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MDIS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_MCR, field DOZE[15] (RW)
- *
- * Provides support for an externally controlled Doze mode power-saving
- * mechanism.
- *
- * Values:
- * - 0 - Doze mode has no effect on the module.
- * - 1 - Doze mode disables the module.
- */
-//@{
-#define BP_SPI_MCR_DOZE (15U) //!< Bit position for SPI_MCR_DOZE.
-#define BM_SPI_MCR_DOZE (0x00008000U) //!< Bit mask for SPI_MCR_DOZE.
-#define BS_SPI_MCR_DOZE (1U) //!< Bit field size in bits for SPI_MCR_DOZE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_MCR_DOZE field.
-#define BR_SPI_MCR_DOZE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DOZE))
-#endif
-
-//! @brief Format value for bitfield SPI_MCR_DOZE.
-#define BF_SPI_MCR_DOZE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_DOZE), uint32_t) & BM_SPI_MCR_DOZE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DOZE field to a new value.
-#define BW_SPI_MCR_DOZE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DOZE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_MCR, field PCSIS[21:16] (RW)
- *
- * Determines the inactive state of PCSx.
- *
- * Values:
- * - 0 - The inactive state of PCSx is low.
- * - 1 - The inactive state of PCSx is high.
- */
-//@{
-#define BP_SPI_MCR_PCSIS (16U) //!< Bit position for SPI_MCR_PCSIS.
-#define BM_SPI_MCR_PCSIS (0x003F0000U) //!< Bit mask for SPI_MCR_PCSIS.
-#define BS_SPI_MCR_PCSIS (6U) //!< Bit field size in bits for SPI_MCR_PCSIS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_MCR_PCSIS field.
-#define BR_SPI_MCR_PCSIS(x) (HW_SPI_MCR(x).B.PCSIS)
-#endif
-
-//! @brief Format value for bitfield SPI_MCR_PCSIS.
-#define BF_SPI_MCR_PCSIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_PCSIS), uint32_t) & BM_SPI_MCR_PCSIS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PCSIS field to a new value.
-#define BW_SPI_MCR_PCSIS(x, v) (HW_SPI_MCR_WR(x, (HW_SPI_MCR_RD(x) & ~BM_SPI_MCR_PCSIS) | BF_SPI_MCR_PCSIS(v)))
-#endif
-//@}
-
-/*!
- * @name Register SPI_MCR, field ROOE[24] (RW)
- *
- * In the RX FIFO overflow condition, configures the module to ignore the
- * incoming serial data or overwrite existing data. If the RX FIFO is full and new data
- * is received, the data from the transfer, generating the overflow, is ignored
- * or shifted into the shift register.
- *
- * Values:
- * - 0 - Incoming data is ignored.
- * - 1 - Incoming data is shifted into the shift register.
- */
-//@{
-#define BP_SPI_MCR_ROOE (24U) //!< Bit position for SPI_MCR_ROOE.
-#define BM_SPI_MCR_ROOE (0x01000000U) //!< Bit mask for SPI_MCR_ROOE.
-#define BS_SPI_MCR_ROOE (1U) //!< Bit field size in bits for SPI_MCR_ROOE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_MCR_ROOE field.
-#define BR_SPI_MCR_ROOE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_ROOE))
-#endif
-
-//! @brief Format value for bitfield SPI_MCR_ROOE.
-#define BF_SPI_MCR_ROOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_ROOE), uint32_t) & BM_SPI_MCR_ROOE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ROOE field to a new value.
-#define BW_SPI_MCR_ROOE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_ROOE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_MCR, field PCSSE[25] (RW)
- *
- * Enables the PCS5/ PCSS to operate as a PCS Strobe output signal.
- *
- * Values:
- * - 0 - PCS5/ PCSS is used as the Peripheral Chip Select[5] signal.
- * - 1 - PCS5/ PCSS is used as an active-low PCS Strobe signal.
- */
-//@{
-#define BP_SPI_MCR_PCSSE (25U) //!< Bit position for SPI_MCR_PCSSE.
-#define BM_SPI_MCR_PCSSE (0x02000000U) //!< Bit mask for SPI_MCR_PCSSE.
-#define BS_SPI_MCR_PCSSE (1U) //!< Bit field size in bits for SPI_MCR_PCSSE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_MCR_PCSSE field.
-#define BR_SPI_MCR_PCSSE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_PCSSE))
-#endif
-
-//! @brief Format value for bitfield SPI_MCR_PCSSE.
-#define BF_SPI_MCR_PCSSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_PCSSE), uint32_t) & BM_SPI_MCR_PCSSE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PCSSE field to a new value.
-#define BW_SPI_MCR_PCSSE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_PCSSE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_MCR, field MTFE[26] (RW)
- *
- * Enables a modified transfer format to be used.
- *
- * Values:
- * - 0 - Modified SPI transfer format disabled.
- * - 1 - Modified SPI transfer format enabled.
- */
-//@{
-#define BP_SPI_MCR_MTFE (26U) //!< Bit position for SPI_MCR_MTFE.
-#define BM_SPI_MCR_MTFE (0x04000000U) //!< Bit mask for SPI_MCR_MTFE.
-#define BS_SPI_MCR_MTFE (1U) //!< Bit field size in bits for SPI_MCR_MTFE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_MCR_MTFE field.
-#define BR_SPI_MCR_MTFE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MTFE))
-#endif
-
-//! @brief Format value for bitfield SPI_MCR_MTFE.
-#define BF_SPI_MCR_MTFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_MTFE), uint32_t) & BM_SPI_MCR_MTFE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MTFE field to a new value.
-#define BW_SPI_MCR_MTFE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MTFE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_MCR, field FRZ[27] (RW)
- *
- * Enables transfers to be stopped on the next frame boundary when the device
- * enters Debug mode.
- *
- * Values:
- * - 0 - Do not halt serial transfers in Debug mode.
- * - 1 - Halt serial transfers in Debug mode.
- */
-//@{
-#define BP_SPI_MCR_FRZ (27U) //!< Bit position for SPI_MCR_FRZ.
-#define BM_SPI_MCR_FRZ (0x08000000U) //!< Bit mask for SPI_MCR_FRZ.
-#define BS_SPI_MCR_FRZ (1U) //!< Bit field size in bits for SPI_MCR_FRZ.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_MCR_FRZ field.
-#define BR_SPI_MCR_FRZ(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_FRZ))
-#endif
-
-//! @brief Format value for bitfield SPI_MCR_FRZ.
-#define BF_SPI_MCR_FRZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_FRZ), uint32_t) & BM_SPI_MCR_FRZ)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FRZ field to a new value.
-#define BW_SPI_MCR_FRZ(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_FRZ) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_MCR, field DCONF[29:28] (RO)
- *
- * Selects among the different configurations of the module.
- *
- * Values:
- * - 00 - SPI
- * - 01 - Reserved
- * - 10 - Reserved
- * - 11 - Reserved
- */
-//@{
-#define BP_SPI_MCR_DCONF (28U) //!< Bit position for SPI_MCR_DCONF.
-#define BM_SPI_MCR_DCONF (0x30000000U) //!< Bit mask for SPI_MCR_DCONF.
-#define BS_SPI_MCR_DCONF (2U) //!< Bit field size in bits for SPI_MCR_DCONF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_MCR_DCONF field.
-#define BR_SPI_MCR_DCONF(x) (HW_SPI_MCR(x).B.DCONF)
-#endif
-//@}
-
-/*!
- * @name Register SPI_MCR, field CONT_SCKE[30] (RW)
- *
- * Enables the Serial Communication Clock (SCK) to run continuously.
- *
- * Values:
- * - 0 - Continuous SCK disabled.
- * - 1 - Continuous SCK enabled.
- */
-//@{
-#define BP_SPI_MCR_CONT_SCKE (30U) //!< Bit position for SPI_MCR_CONT_SCKE.
-#define BM_SPI_MCR_CONT_SCKE (0x40000000U) //!< Bit mask for SPI_MCR_CONT_SCKE.
-#define BS_SPI_MCR_CONT_SCKE (1U) //!< Bit field size in bits for SPI_MCR_CONT_SCKE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_MCR_CONT_SCKE field.
-#define BR_SPI_MCR_CONT_SCKE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CONT_SCKE))
-#endif
-
-//! @brief Format value for bitfield SPI_MCR_CONT_SCKE.
-#define BF_SPI_MCR_CONT_SCKE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_CONT_SCKE), uint32_t) & BM_SPI_MCR_CONT_SCKE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CONT_SCKE field to a new value.
-#define BW_SPI_MCR_CONT_SCKE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CONT_SCKE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_MCR, field MSTR[31] (RW)
- *
- * Enables either Master mode (if supported) or Slave mode (if supported)
- * operation.
- *
- * Values:
- * - 0 - Enables Slave mode
- * - 1 - Enables Master mode
- */
-//@{
-#define BP_SPI_MCR_MSTR (31U) //!< Bit position for SPI_MCR_MSTR.
-#define BM_SPI_MCR_MSTR (0x80000000U) //!< Bit mask for SPI_MCR_MSTR.
-#define BS_SPI_MCR_MSTR (1U) //!< Bit field size in bits for SPI_MCR_MSTR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_MCR_MSTR field.
-#define BR_SPI_MCR_MSTR(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MSTR))
-#endif
-
-//! @brief Format value for bitfield SPI_MCR_MSTR.
-#define BF_SPI_MCR_MSTR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_MSTR), uint32_t) & BM_SPI_MCR_MSTR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MSTR field to a new value.
-#define BW_SPI_MCR_MSTR(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MSTR) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SPI_TCR - Transfer Count Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SPI_TCR - Transfer Count Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * TCR contains a counter that indicates the number of SPI transfers made. The
- * transfer counter is intended to assist in queue management. Do not write the
- * TCR when the module is in the Running state.
- */
-typedef union _hw_spi_tcr
-{
- uint32_t U;
- struct _hw_spi_tcr_bitfields
- {
- uint32_t RESERVED0 : 16; //!< [15:0]
- uint32_t SPI_TCNT : 16; //!< [31:16] SPI Transfer Counter
- } B;
-} hw_spi_tcr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SPI_TCR register
- */
-//@{
-#define HW_SPI_TCR_ADDR(x) (REGS_SPI_BASE(x) + 0x8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SPI_TCR(x) (*(__IO hw_spi_tcr_t *) HW_SPI_TCR_ADDR(x))
-#define HW_SPI_TCR_RD(x) (HW_SPI_TCR(x).U)
-#define HW_SPI_TCR_WR(x, v) (HW_SPI_TCR(x).U = (v))
-#define HW_SPI_TCR_SET(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) | (v)))
-#define HW_SPI_TCR_CLR(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) & ~(v)))
-#define HW_SPI_TCR_TOG(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SPI_TCR bitfields
- */
-
-/*!
- * @name Register SPI_TCR, field SPI_TCNT[31:16] (RW)
- *
- * Counts the number of SPI transfers the module makes. The SPI_TCNT field
- * increments every time the last bit of an SPI frame is transmitted. A value written
- * to SPI_TCNT presets the counter to that value. SPI_TCNT is reset to zero at
- * the beginning of the frame when the CTCNT field is set in the executing SPI
- * command. The Transfer Counter wraps around; incrementing the counter past 65535
- * resets the counter to zero.
- */
-//@{
-#define BP_SPI_TCR_SPI_TCNT (16U) //!< Bit position for SPI_TCR_SPI_TCNT.
-#define BM_SPI_TCR_SPI_TCNT (0xFFFF0000U) //!< Bit mask for SPI_TCR_SPI_TCNT.
-#define BS_SPI_TCR_SPI_TCNT (16U) //!< Bit field size in bits for SPI_TCR_SPI_TCNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_TCR_SPI_TCNT field.
-#define BR_SPI_TCR_SPI_TCNT(x) (HW_SPI_TCR(x).B.SPI_TCNT)
-#endif
-
-//! @brief Format value for bitfield SPI_TCR_SPI_TCNT.
-#define BF_SPI_TCR_SPI_TCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_TCR_SPI_TCNT), uint32_t) & BM_SPI_TCR_SPI_TCNT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SPI_TCNT field to a new value.
-#define BW_SPI_TCR_SPI_TCNT(x, v) (HW_SPI_TCR_WR(x, (HW_SPI_TCR_RD(x) & ~BM_SPI_TCR_SPI_TCNT) | BF_SPI_TCR_SPI_TCNT(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode)
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode) (RW)
- *
- * Reset value: 0x78000000U
- *
- * CTAR registers are used to define different transfer attributes. Do not write
- * to the CTAR registers while the module is in the Running state. In Master
- * mode, the CTAR registers define combinations of transfer attributes such as frame
- * size, clock phase and polarity, data bit ordering, baud rate, and various
- * delays. In slave mode, a subset of the bitfields in CTAR0 are used to set the
- * slave transfer attributes. When the module is configured as an SPI master, the
- * CTAS field in the command portion of the TX FIFO entry selects which of the CTAR
- * registers is used. When the module is configured as an SPI bus slave, it uses
- * the CTAR0 register.
- */
-typedef union _hw_spi_ctarn
-{
- uint32_t U;
- struct _hw_spi_ctarn_bitfields
- {
- uint32_t BR : 4; //!< [3:0] Baud Rate Scaler
- uint32_t DT : 4; //!< [7:4] Delay After Transfer Scaler
- uint32_t ASC : 4; //!< [11:8] After SCK Delay Scaler
- uint32_t CSSCK : 4; //!< [15:12] PCS to SCK Delay Scaler
- uint32_t PBR : 2; //!< [17:16] Baud Rate Prescaler
- uint32_t PDT : 2; //!< [19:18] Delay after Transfer Prescaler
- uint32_t PASC : 2; //!< [21:20] After SCK Delay Prescaler
- uint32_t PCSSCK : 2; //!< [23:22] PCS to SCK Delay Prescaler
- uint32_t LSBFE : 1; //!< [24] LSB First
- uint32_t CPHA : 1; //!< [25] Clock Phase
- uint32_t CPOL : 1; //!< [26] Clock Polarity
- uint32_t FMSZ : 4; //!< [30:27] Frame Size
- uint32_t DBR : 1; //!< [31] Double Baud Rate
- } B;
-} hw_spi_ctarn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SPI_CTARn register
- */
-//@{
-#define HW_SPI_CTARn_COUNT (2U)
-
-#define HW_SPI_CTARn_ADDR(x, n) (REGS_SPI_BASE(x) + 0xCU + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SPI_CTARn(x, n) (*(__IO hw_spi_ctarn_t *) HW_SPI_CTARn_ADDR(x, n))
-#define HW_SPI_CTARn_RD(x, n) (HW_SPI_CTARn(x, n).U)
-#define HW_SPI_CTARn_WR(x, n, v) (HW_SPI_CTARn(x, n).U = (v))
-#define HW_SPI_CTARn_SET(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) | (v)))
-#define HW_SPI_CTARn_CLR(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) & ~(v)))
-#define HW_SPI_CTARn_TOG(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SPI_CTARn bitfields
- */
-
-/*!
- * @name Register SPI_CTARn, field BR[3:0] (RW)
- *
- * Selects the scaler value for the baud rate. This field is used only in master
- * mode. The prescaled protocol clock is divided by the Baud Rate Scaler to
- * generate the frequency of the SCK. The baud rate is computed according to the
- * following equation: SCK baud rate = (fP /PBR) x [(1+DBR)/BR] The following table
- * lists the baud rate scaler values. Baud Rate Scaler CTARn[BR] Baud Rate Scaler
- * Value 0000 2 0001 4 0010 6 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256
- * 1001 512 1010 1024 1011 2048 1100 4096 1101 8192 1110 16384 1111 32768
- */
-//@{
-#define BP_SPI_CTARn_BR (0U) //!< Bit position for SPI_CTARn_BR.
-#define BM_SPI_CTARn_BR (0x0000000FU) //!< Bit mask for SPI_CTARn_BR.
-#define BS_SPI_CTARn_BR (4U) //!< Bit field size in bits for SPI_CTARn_BR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_CTARn_BR field.
-#define BR_SPI_CTARn_BR(x, n) (HW_SPI_CTARn(x, n).B.BR)
-#endif
-
-//! @brief Format value for bitfield SPI_CTARn_BR.
-#define BF_SPI_CTARn_BR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_BR), uint32_t) & BM_SPI_CTARn_BR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BR field to a new value.
-#define BW_SPI_CTARn_BR(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_BR) | BF_SPI_CTARn_BR(v)))
-#endif
-//@}
-
-/*!
- * @name Register SPI_CTARn, field DT[7:4] (RW)
- *
- * Selects the Delay after Transfer Scaler. This field is used only in master
- * mode. The Delay after Transfer is the time between the negation of the PCS
- * signal at the end of a frame and the assertion of PCS at the beginning of the next
- * frame. In the Continuous Serial Communications Clock operation, the DT value
- * is fixed to one SCK clock period, The Delay after Transfer is a multiple of the
- * protocol clock period, and it is computed according to the following
- * equation: tDT = (1/fP ) x PDT x DT See Delay Scaler Encoding table in CTARn[CSSCK] bit
- * field description for scaler values.
- */
-//@{
-#define BP_SPI_CTARn_DT (4U) //!< Bit position for SPI_CTARn_DT.
-#define BM_SPI_CTARn_DT (0x000000F0U) //!< Bit mask for SPI_CTARn_DT.
-#define BS_SPI_CTARn_DT (4U) //!< Bit field size in bits for SPI_CTARn_DT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_CTARn_DT field.
-#define BR_SPI_CTARn_DT(x, n) (HW_SPI_CTARn(x, n).B.DT)
-#endif
-
-//! @brief Format value for bitfield SPI_CTARn_DT.
-#define BF_SPI_CTARn_DT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_DT), uint32_t) & BM_SPI_CTARn_DT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DT field to a new value.
-#define BW_SPI_CTARn_DT(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_DT) | BF_SPI_CTARn_DT(v)))
-#endif
-//@}
-
-/*!
- * @name Register SPI_CTARn, field ASC[11:8] (RW)
- *
- * Selects the scaler value for the After SCK Delay. This field is used only in
- * master mode. The After SCK Delay is the delay between the last edge of SCK and
- * the negation of PCS. The delay is a multiple of the protocol clock period,
- * and it is computed according to the following equation: t ASC = (1/fP) x PASC x
- * ASC See Delay Scaler Encoding table in CTARn[CSSCK] bit field description for
- * scaler values. Refer After SCK Delay (tASC ) for more details.
- */
-//@{
-#define BP_SPI_CTARn_ASC (8U) //!< Bit position for SPI_CTARn_ASC.
-#define BM_SPI_CTARn_ASC (0x00000F00U) //!< Bit mask for SPI_CTARn_ASC.
-#define BS_SPI_CTARn_ASC (4U) //!< Bit field size in bits for SPI_CTARn_ASC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_CTARn_ASC field.
-#define BR_SPI_CTARn_ASC(x, n) (HW_SPI_CTARn(x, n).B.ASC)
-#endif
-
-//! @brief Format value for bitfield SPI_CTARn_ASC.
-#define BF_SPI_CTARn_ASC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_ASC), uint32_t) & BM_SPI_CTARn_ASC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ASC field to a new value.
-#define BW_SPI_CTARn_ASC(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_ASC) | BF_SPI_CTARn_ASC(v)))
-#endif
-//@}
-
-/*!
- * @name Register SPI_CTARn, field CSSCK[15:12] (RW)
- *
- * Selects the scaler value for the PCS to SCK delay. This field is used only in
- * master mode. The PCS to SCK Delay is the delay between the assertion of PCS
- * and the first edge of the SCK. The delay is a multiple of the protocol clock
- * period, and it is computed according to the following equation: t CSC = (1/fP )
- * x PCSSCK x CSSCK. The following table lists the delay scaler values. Delay
- * Scaler Encoding Field Value Delay Scaler Value 0000 2 0001 4 0010 8 0011 16 0100
- * 32 0101 64 0110 128 0111 256 1000 512 1001 1024 1010 2048 1011 4096 1100 8192
- * 1101 16384 1110 32768 1111 65536 Refer PCS to SCK Delay (tCSC ) for more
- * details.
- */
-//@{
-#define BP_SPI_CTARn_CSSCK (12U) //!< Bit position for SPI_CTARn_CSSCK.
-#define BM_SPI_CTARn_CSSCK (0x0000F000U) //!< Bit mask for SPI_CTARn_CSSCK.
-#define BS_SPI_CTARn_CSSCK (4U) //!< Bit field size in bits for SPI_CTARn_CSSCK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_CTARn_CSSCK field.
-#define BR_SPI_CTARn_CSSCK(x, n) (HW_SPI_CTARn(x, n).B.CSSCK)
-#endif
-
-//! @brief Format value for bitfield SPI_CTARn_CSSCK.
-#define BF_SPI_CTARn_CSSCK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_CSSCK), uint32_t) & BM_SPI_CTARn_CSSCK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CSSCK field to a new value.
-#define BW_SPI_CTARn_CSSCK(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_CSSCK) | BF_SPI_CTARn_CSSCK(v)))
-#endif
-//@}
-
-/*!
- * @name Register SPI_CTARn, field PBR[17:16] (RW)
- *
- * Selects the prescaler value for the baud rate. This field is used only in
- * master mode. The baud rate is the frequency of the SCK. The protocol clock is
- * divided by the prescaler value before the baud rate selection takes place. See
- * the BR field description for details on how to compute the baud rate.
- *
- * Values:
- * - 00 - Baud Rate Prescaler value is 2.
- * - 01 - Baud Rate Prescaler value is 3.
- * - 10 - Baud Rate Prescaler value is 5.
- * - 11 - Baud Rate Prescaler value is 7.
- */
-//@{
-#define BP_SPI_CTARn_PBR (16U) //!< Bit position for SPI_CTARn_PBR.
-#define BM_SPI_CTARn_PBR (0x00030000U) //!< Bit mask for SPI_CTARn_PBR.
-#define BS_SPI_CTARn_PBR (2U) //!< Bit field size in bits for SPI_CTARn_PBR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_CTARn_PBR field.
-#define BR_SPI_CTARn_PBR(x, n) (HW_SPI_CTARn(x, n).B.PBR)
-#endif
-
-//! @brief Format value for bitfield SPI_CTARn_PBR.
-#define BF_SPI_CTARn_PBR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_PBR), uint32_t) & BM_SPI_CTARn_PBR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PBR field to a new value.
-#define BW_SPI_CTARn_PBR(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PBR) | BF_SPI_CTARn_PBR(v)))
-#endif
-//@}
-
-/*!
- * @name Register SPI_CTARn, field PDT[19:18] (RW)
- *
- * Selects the prescaler value for the delay between the negation of the PCS
- * signal at the end of a frame and the assertion of PCS at the beginning of the
- * next frame. The PDT field is only used in master mode. See the DT field
- * description for details on how to compute the Delay after Transfer. Refer Delay after
- * Transfer (tDT ) for more details.
- *
- * Values:
- * - 00 - Delay after Transfer Prescaler value is 1.
- * - 01 - Delay after Transfer Prescaler value is 3.
- * - 10 - Delay after Transfer Prescaler value is 5.
- * - 11 - Delay after Transfer Prescaler value is 7.
- */
-//@{
-#define BP_SPI_CTARn_PDT (18U) //!< Bit position for SPI_CTARn_PDT.
-#define BM_SPI_CTARn_PDT (0x000C0000U) //!< Bit mask for SPI_CTARn_PDT.
-#define BS_SPI_CTARn_PDT (2U) //!< Bit field size in bits for SPI_CTARn_PDT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_CTARn_PDT field.
-#define BR_SPI_CTARn_PDT(x, n) (HW_SPI_CTARn(x, n).B.PDT)
-#endif
-
-//! @brief Format value for bitfield SPI_CTARn_PDT.
-#define BF_SPI_CTARn_PDT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_PDT), uint32_t) & BM_SPI_CTARn_PDT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PDT field to a new value.
-#define BW_SPI_CTARn_PDT(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PDT) | BF_SPI_CTARn_PDT(v)))
-#endif
-//@}
-
-/*!
- * @name Register SPI_CTARn, field PASC[21:20] (RW)
- *
- * Selects the prescaler value for the delay between the last edge of SCK and
- * the negation of PCS. See the ASC field description for information on how to
- * compute the After SCK Delay. Refer After SCK Delay (tASC ) for more details.
- *
- * Values:
- * - 00 - Delay after Transfer Prescaler value is 1.
- * - 01 - Delay after Transfer Prescaler value is 3.
- * - 10 - Delay after Transfer Prescaler value is 5.
- * - 11 - Delay after Transfer Prescaler value is 7.
- */
-//@{
-#define BP_SPI_CTARn_PASC (20U) //!< Bit position for SPI_CTARn_PASC.
-#define BM_SPI_CTARn_PASC (0x00300000U) //!< Bit mask for SPI_CTARn_PASC.
-#define BS_SPI_CTARn_PASC (2U) //!< Bit field size in bits for SPI_CTARn_PASC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_CTARn_PASC field.
-#define BR_SPI_CTARn_PASC(x, n) (HW_SPI_CTARn(x, n).B.PASC)
-#endif
-
-//! @brief Format value for bitfield SPI_CTARn_PASC.
-#define BF_SPI_CTARn_PASC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_PASC), uint32_t) & BM_SPI_CTARn_PASC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PASC field to a new value.
-#define BW_SPI_CTARn_PASC(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PASC) | BF_SPI_CTARn_PASC(v)))
-#endif
-//@}
-
-/*!
- * @name Register SPI_CTARn, field PCSSCK[23:22] (RW)
- *
- * Selects the prescaler value for the delay between assertion of PCS and the
- * first edge of the SCK. See the CSSCK field description for information on how to
- * compute the PCS to SCK Delay. Refer PCS to SCK Delay (tCSC ) for more details.
- *
- * Values:
- * - 00 - PCS to SCK Prescaler value is 1.
- * - 01 - PCS to SCK Prescaler value is 3.
- * - 10 - PCS to SCK Prescaler value is 5.
- * - 11 - PCS to SCK Prescaler value is 7.
- */
-//@{
-#define BP_SPI_CTARn_PCSSCK (22U) //!< Bit position for SPI_CTARn_PCSSCK.
-#define BM_SPI_CTARn_PCSSCK (0x00C00000U) //!< Bit mask for SPI_CTARn_PCSSCK.
-#define BS_SPI_CTARn_PCSSCK (2U) //!< Bit field size in bits for SPI_CTARn_PCSSCK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_CTARn_PCSSCK field.
-#define BR_SPI_CTARn_PCSSCK(x, n) (HW_SPI_CTARn(x, n).B.PCSSCK)
-#endif
-
-//! @brief Format value for bitfield SPI_CTARn_PCSSCK.
-#define BF_SPI_CTARn_PCSSCK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_PCSSCK), uint32_t) & BM_SPI_CTARn_PCSSCK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PCSSCK field to a new value.
-#define BW_SPI_CTARn_PCSSCK(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PCSSCK) | BF_SPI_CTARn_PCSSCK(v)))
-#endif
-//@}
-
-/*!
- * @name Register SPI_CTARn, field LSBFE[24] (RW)
- *
- * Specifies whether the LSB or MSB of the frame is transferred first.
- *
- * Values:
- * - 0 - Data is transferred MSB first.
- * - 1 - Data is transferred LSB first.
- */
-//@{
-#define BP_SPI_CTARn_LSBFE (24U) //!< Bit position for SPI_CTARn_LSBFE.
-#define BM_SPI_CTARn_LSBFE (0x01000000U) //!< Bit mask for SPI_CTARn_LSBFE.
-#define BS_SPI_CTARn_LSBFE (1U) //!< Bit field size in bits for SPI_CTARn_LSBFE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_CTARn_LSBFE field.
-#define BR_SPI_CTARn_LSBFE(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_LSBFE))
-#endif
-
-//! @brief Format value for bitfield SPI_CTARn_LSBFE.
-#define BF_SPI_CTARn_LSBFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_LSBFE), uint32_t) & BM_SPI_CTARn_LSBFE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LSBFE field to a new value.
-#define BW_SPI_CTARn_LSBFE(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_LSBFE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_CTARn, field CPHA[25] (RW)
- *
- * Selects which edge of SCK causes data to change and which edge causes data to
- * be captured. This bit is used in both master and slave mode. For successful
- * communication between serial devices, the devices must have identical clock
- * phase settings. In Continuous SCK mode, the bit value is ignored and the
- * transfers are done as if the CPHA bit is set to 1.
- *
- * Values:
- * - 0 - Data is captured on the leading edge of SCK and changed on the
- * following edge.
- * - 1 - Data is changed on the leading edge of SCK and captured on the
- * following edge.
- */
-//@{
-#define BP_SPI_CTARn_CPHA (25U) //!< Bit position for SPI_CTARn_CPHA.
-#define BM_SPI_CTARn_CPHA (0x02000000U) //!< Bit mask for SPI_CTARn_CPHA.
-#define BS_SPI_CTARn_CPHA (1U) //!< Bit field size in bits for SPI_CTARn_CPHA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_CTARn_CPHA field.
-#define BR_SPI_CTARn_CPHA(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPHA))
-#endif
-
-//! @brief Format value for bitfield SPI_CTARn_CPHA.
-#define BF_SPI_CTARn_CPHA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_CPHA), uint32_t) & BM_SPI_CTARn_CPHA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CPHA field to a new value.
-#define BW_SPI_CTARn_CPHA(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPHA) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_CTARn, field CPOL[26] (RW)
- *
- * Selects the inactive state of the Serial Communications Clock (SCK). This bit
- * is used in both master and slave mode. For successful communication between
- * serial devices, the devices must have identical clock polarities. When the
- * Continuous Selection Format is selected, switching between clock polarities
- * without stopping the module can cause errors in the transfer due to the peripheral
- * device interpreting the switch of clock polarity as a valid clock edge. In case
- * of continous sck mode, when the module goes in low power mode(disabled),
- * inactive state of sck is not guaranted.
- *
- * Values:
- * - 0 - The inactive state value of SCK is low.
- * - 1 - The inactive state value of SCK is high.
- */
-//@{
-#define BP_SPI_CTARn_CPOL (26U) //!< Bit position for SPI_CTARn_CPOL.
-#define BM_SPI_CTARn_CPOL (0x04000000U) //!< Bit mask for SPI_CTARn_CPOL.
-#define BS_SPI_CTARn_CPOL (1U) //!< Bit field size in bits for SPI_CTARn_CPOL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_CTARn_CPOL field.
-#define BR_SPI_CTARn_CPOL(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPOL))
-#endif
-
-//! @brief Format value for bitfield SPI_CTARn_CPOL.
-#define BF_SPI_CTARn_CPOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_CPOL), uint32_t) & BM_SPI_CTARn_CPOL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CPOL field to a new value.
-#define BW_SPI_CTARn_CPOL(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPOL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_CTARn, field FMSZ[30:27] (RW)
- *
- * The number of bits transferred per frame is equal to the FMSZ value plus 1.
- * Regardless of the transmission mode, the minimum valid frame size value is 4.
- */
-//@{
-#define BP_SPI_CTARn_FMSZ (27U) //!< Bit position for SPI_CTARn_FMSZ.
-#define BM_SPI_CTARn_FMSZ (0x78000000U) //!< Bit mask for SPI_CTARn_FMSZ.
-#define BS_SPI_CTARn_FMSZ (4U) //!< Bit field size in bits for SPI_CTARn_FMSZ.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_CTARn_FMSZ field.
-#define BR_SPI_CTARn_FMSZ(x, n) (HW_SPI_CTARn(x, n).B.FMSZ)
-#endif
-
-//! @brief Format value for bitfield SPI_CTARn_FMSZ.
-#define BF_SPI_CTARn_FMSZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_FMSZ), uint32_t) & BM_SPI_CTARn_FMSZ)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FMSZ field to a new value.
-#define BW_SPI_CTARn_FMSZ(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_FMSZ) | BF_SPI_CTARn_FMSZ(v)))
-#endif
-//@}
-
-/*!
- * @name Register SPI_CTARn, field DBR[31] (RW)
- *
- * Doubles the effective baud rate of the Serial Communications Clock (SCK).
- * This field is used only in master mode. It effectively halves the Baud Rate
- * division ratio, supporting faster frequencies, and odd division ratios for the
- * Serial Communications Clock (SCK). When the DBR bit is set, the duty cycle of the
- * Serial Communications Clock (SCK) depends on the value in the Baud Rate
- * Prescaler and the Clock Phase bit as listed in the following table. See the BR field
- * description for details on how to compute the baud rate. SPI SCK Duty Cycle
- * DBR CPHA PBR SCK Duty Cycle 0 any any 50/50 1 0 00 50/50 1 0 01 33/66 1 0 10
- * 40/60 1 0 11 43/57 1 1 00 50/50 1 1 01 66/33 1 1 10 60/40 1 1 11 57/43
- *
- * Values:
- * - 0 - The baud rate is computed normally with a 50/50 duty cycle.
- * - 1 - The baud rate is doubled with the duty cycle depending on the Baud Rate
- * Prescaler.
- */
-//@{
-#define BP_SPI_CTARn_DBR (31U) //!< Bit position for SPI_CTARn_DBR.
-#define BM_SPI_CTARn_DBR (0x80000000U) //!< Bit mask for SPI_CTARn_DBR.
-#define BS_SPI_CTARn_DBR (1U) //!< Bit field size in bits for SPI_CTARn_DBR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_CTARn_DBR field.
-#define BR_SPI_CTARn_DBR(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_DBR))
-#endif
-
-//! @brief Format value for bitfield SPI_CTARn_DBR.
-#define BF_SPI_CTARn_DBR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_DBR), uint32_t) & BM_SPI_CTARn_DBR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DBR field to a new value.
-#define BW_SPI_CTARn_DBR(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_DBR) = (v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) (RW)
- *
- * Reset value: 0x78000000U
- *
- * When the module is configured as an SPI bus slave, the CTAR0 register is used.
- */
-typedef union _hw_spi_ctarn_slave
-{
- uint32_t U;
- struct _hw_spi_ctarn_slave_bitfields
- {
- uint32_t RESERVED0 : 25; //!< [24:0]
- uint32_t CPHA : 1; //!< [25] Clock Phase
- uint32_t CPOL : 1; //!< [26] Clock Polarity
- uint32_t FMSZ : 5; //!< [31:27] Frame Size
- } B;
-} hw_spi_ctarn_slave_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SPI_CTARn_SLAVE register
- */
-//@{
-#define HW_SPI_CTARn_SLAVE_COUNT (1U)
-
-#define HW_SPI_CTARn_SLAVE_ADDR(x, n) (REGS_SPI_BASE(x) + 0xCU + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SPI_CTARn_SLAVE(x, n) (*(__IO hw_spi_ctarn_slave_t *) HW_SPI_CTARn_SLAVE_ADDR(x, n))
-#define HW_SPI_CTARn_SLAVE_RD(x, n) (HW_SPI_CTARn_SLAVE(x, n).U)
-#define HW_SPI_CTARn_SLAVE_WR(x, n, v) (HW_SPI_CTARn_SLAVE(x, n).U = (v))
-#define HW_SPI_CTARn_SLAVE_SET(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) | (v)))
-#define HW_SPI_CTARn_SLAVE_CLR(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) & ~(v)))
-#define HW_SPI_CTARn_SLAVE_TOG(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SPI_CTARn_SLAVE bitfields
- */
-
-/*!
- * @name Register SPI_CTARn_SLAVE, field CPHA[25] (RW)
- *
- * Selects which edge of SCK causes data to change and which edge causes data to
- * be captured. This bit is used in both master and slave mode. For successful
- * communication between serial devices, the devices must have identical clock
- * phase settings. In Continuous SCK mode, the bit value is ignored and the
- * transfers are done as if the CPHA bit is set to 1.
- *
- * Values:
- * - 0 - Data is captured on the leading edge of SCK and changed on the
- * following edge.
- * - 1 - Data is changed on the leading edge of SCK and captured on the
- * following edge.
- */
-//@{
-#define BP_SPI_CTARn_SLAVE_CPHA (25U) //!< Bit position for SPI_CTARn_SLAVE_CPHA.
-#define BM_SPI_CTARn_SLAVE_CPHA (0x02000000U) //!< Bit mask for SPI_CTARn_SLAVE_CPHA.
-#define BS_SPI_CTARn_SLAVE_CPHA (1U) //!< Bit field size in bits for SPI_CTARn_SLAVE_CPHA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_CTARn_SLAVE_CPHA field.
-#define BR_SPI_CTARn_SLAVE_CPHA(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPHA))
-#endif
-
-//! @brief Format value for bitfield SPI_CTARn_SLAVE_CPHA.
-#define BF_SPI_CTARn_SLAVE_CPHA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_SLAVE_CPHA), uint32_t) & BM_SPI_CTARn_SLAVE_CPHA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CPHA field to a new value.
-#define BW_SPI_CTARn_SLAVE_CPHA(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPHA) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_CTARn_SLAVE, field CPOL[26] (RW)
- *
- * Selects the inactive state of the Serial Communications Clock (SCK). In case
- * of continous sck mode, when the module goes in low power mode(disabled),
- * inactive state of sck is not guaranted.
- *
- * Values:
- * - 0 - The inactive state value of SCK is low.
- * - 1 - The inactive state value of SCK is high.
- */
-//@{
-#define BP_SPI_CTARn_SLAVE_CPOL (26U) //!< Bit position for SPI_CTARn_SLAVE_CPOL.
-#define BM_SPI_CTARn_SLAVE_CPOL (0x04000000U) //!< Bit mask for SPI_CTARn_SLAVE_CPOL.
-#define BS_SPI_CTARn_SLAVE_CPOL (1U) //!< Bit field size in bits for SPI_CTARn_SLAVE_CPOL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_CTARn_SLAVE_CPOL field.
-#define BR_SPI_CTARn_SLAVE_CPOL(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPOL))
-#endif
-
-//! @brief Format value for bitfield SPI_CTARn_SLAVE_CPOL.
-#define BF_SPI_CTARn_SLAVE_CPOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_SLAVE_CPOL), uint32_t) & BM_SPI_CTARn_SLAVE_CPOL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CPOL field to a new value.
-#define BW_SPI_CTARn_SLAVE_CPOL(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPOL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_CTARn_SLAVE, field FMSZ[31:27] (RW)
- *
- * The number of bits transfered per frame is equal to the FMSZ field value plus
- * 1. Note that the minimum valid value of frame size is 4.
- */
-//@{
-#define BP_SPI_CTARn_SLAVE_FMSZ (27U) //!< Bit position for SPI_CTARn_SLAVE_FMSZ.
-#define BM_SPI_CTARn_SLAVE_FMSZ (0xF8000000U) //!< Bit mask for SPI_CTARn_SLAVE_FMSZ.
-#define BS_SPI_CTARn_SLAVE_FMSZ (5U) //!< Bit field size in bits for SPI_CTARn_SLAVE_FMSZ.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_CTARn_SLAVE_FMSZ field.
-#define BR_SPI_CTARn_SLAVE_FMSZ(x, n) (HW_SPI_CTARn_SLAVE(x, n).B.FMSZ)
-#endif
-
-//! @brief Format value for bitfield SPI_CTARn_SLAVE_FMSZ.
-#define BF_SPI_CTARn_SLAVE_FMSZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_SLAVE_FMSZ), uint32_t) & BM_SPI_CTARn_SLAVE_FMSZ)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FMSZ field to a new value.
-#define BW_SPI_CTARn_SLAVE_FMSZ(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, (HW_SPI_CTARn_SLAVE_RD(x, n) & ~BM_SPI_CTARn_SLAVE_FMSZ) | BF_SPI_CTARn_SLAVE_FMSZ(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SPI_SR - Status Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SPI_SR - Status Register (RW)
- *
- * Reset value: 0x02000000U
- *
- * SR contains status and flag bits. The bits reflect the status of the module
- * and indicate the occurrence of events that can generate interrupt or DMA
- * requests. Software can clear flag bits in the SR by writing a 1 to them. Writing a 0
- * to a flag bit has no effect. This register may not be writable in Module
- * Disable mode due to the use of power saving mechanisms.
- */
-typedef union _hw_spi_sr
-{
- uint32_t U;
- struct _hw_spi_sr_bitfields
- {
- uint32_t POPNXTPTR : 4; //!< [3:0] Pop Next Pointer
- uint32_t RXCTR : 4; //!< [7:4] RX FIFO Counter
- uint32_t TXNXTPTR : 4; //!< [11:8] Transmit Next Pointer
- uint32_t TXCTR : 4; //!< [15:12] TX FIFO Counter
- uint32_t RESERVED0 : 1; //!< [16]
- uint32_t RFDF : 1; //!< [17] Receive FIFO Drain Flag
- uint32_t RESERVED1 : 1; //!< [18]
- uint32_t RFOF : 1; //!< [19] Receive FIFO Overflow Flag
- uint32_t RESERVED2 : 5; //!< [24:20]
- uint32_t TFFF : 1; //!< [25] Transmit FIFO Fill Flag
- uint32_t RESERVED3 : 1; //!< [26]
- uint32_t TFUF : 1; //!< [27] Transmit FIFO Underflow Flag
- uint32_t EOQF : 1; //!< [28] End of Queue Flag
- uint32_t RESERVED4 : 1; //!< [29]
- uint32_t TXRXS : 1; //!< [30] TX and RX Status
- uint32_t TCF : 1; //!< [31] Transfer Complete Flag
- } B;
-} hw_spi_sr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SPI_SR register
- */
-//@{
-#define HW_SPI_SR_ADDR(x) (REGS_SPI_BASE(x) + 0x2CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SPI_SR(x) (*(__IO hw_spi_sr_t *) HW_SPI_SR_ADDR(x))
-#define HW_SPI_SR_RD(x) (HW_SPI_SR(x).U)
-#define HW_SPI_SR_WR(x, v) (HW_SPI_SR(x).U = (v))
-#define HW_SPI_SR_SET(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) | (v)))
-#define HW_SPI_SR_CLR(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) & ~(v)))
-#define HW_SPI_SR_TOG(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SPI_SR bitfields
- */
-
-/*!
- * @name Register SPI_SR, field POPNXTPTR[3:0] (RO)
- *
- * Contains a pointer to the RX FIFO entry to be returned when the POPR is read.
- * The POPNXTPTR is updated when the POPR is read.
- */
-//@{
-#define BP_SPI_SR_POPNXTPTR (0U) //!< Bit position for SPI_SR_POPNXTPTR.
-#define BM_SPI_SR_POPNXTPTR (0x0000000FU) //!< Bit mask for SPI_SR_POPNXTPTR.
-#define BS_SPI_SR_POPNXTPTR (4U) //!< Bit field size in bits for SPI_SR_POPNXTPTR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_SR_POPNXTPTR field.
-#define BR_SPI_SR_POPNXTPTR(x) (HW_SPI_SR(x).B.POPNXTPTR)
-#endif
-//@}
-
-/*!
- * @name Register SPI_SR, field RXCTR[7:4] (RO)
- *
- * Indicates the number of entries in the RX FIFO. The RXCTR is decremented
- * every time the POPR is read. The RXCTR is incremented every time data is
- * transferred from the shift register to the RX FIFO.
- */
-//@{
-#define BP_SPI_SR_RXCTR (4U) //!< Bit position for SPI_SR_RXCTR.
-#define BM_SPI_SR_RXCTR (0x000000F0U) //!< Bit mask for SPI_SR_RXCTR.
-#define BS_SPI_SR_RXCTR (4U) //!< Bit field size in bits for SPI_SR_RXCTR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_SR_RXCTR field.
-#define BR_SPI_SR_RXCTR(x) (HW_SPI_SR(x).B.RXCTR)
-#endif
-//@}
-
-/*!
- * @name Register SPI_SR, field TXNXTPTR[11:8] (RO)
- *
- * Indicates which TX FIFO entry is transmitted during the next transfer. The
- * TXNXTPTR field is updated every time SPI data is transferred from the TX FIFO to
- * the shift register.
- */
-//@{
-#define BP_SPI_SR_TXNXTPTR (8U) //!< Bit position for SPI_SR_TXNXTPTR.
-#define BM_SPI_SR_TXNXTPTR (0x00000F00U) //!< Bit mask for SPI_SR_TXNXTPTR.
-#define BS_SPI_SR_TXNXTPTR (4U) //!< Bit field size in bits for SPI_SR_TXNXTPTR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_SR_TXNXTPTR field.
-#define BR_SPI_SR_TXNXTPTR(x) (HW_SPI_SR(x).B.TXNXTPTR)
-#endif
-//@}
-
-/*!
- * @name Register SPI_SR, field TXCTR[15:12] (RO)
- *
- * Indicates the number of valid entries in the TX FIFO. The TXCTR is
- * incremented every time the PUSHR is written. The TXCTR is decremented every time an SPI
- * command is executed and the SPI data is transferred to the shift register.
- */
-//@{
-#define BP_SPI_SR_TXCTR (12U) //!< Bit position for SPI_SR_TXCTR.
-#define BM_SPI_SR_TXCTR (0x0000F000U) //!< Bit mask for SPI_SR_TXCTR.
-#define BS_SPI_SR_TXCTR (4U) //!< Bit field size in bits for SPI_SR_TXCTR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_SR_TXCTR field.
-#define BR_SPI_SR_TXCTR(x) (HW_SPI_SR(x).B.TXCTR)
-#endif
-//@}
-
-/*!
- * @name Register SPI_SR, field RFDF[17] (W1C)
- *
- * Provides a method for the module to request that entries be removed from the
- * RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be
- * cleared by writing 1 to it or by acknowledgement from the DMA controller when
- * the RX FIFO is empty.
- *
- * Values:
- * - 0 - RX FIFO is empty.
- * - 1 - RX FIFO is not empty.
- */
-//@{
-#define BP_SPI_SR_RFDF (17U) //!< Bit position for SPI_SR_RFDF.
-#define BM_SPI_SR_RFDF (0x00020000U) //!< Bit mask for SPI_SR_RFDF.
-#define BS_SPI_SR_RFDF (1U) //!< Bit field size in bits for SPI_SR_RFDF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_SR_RFDF field.
-#define BR_SPI_SR_RFDF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFDF))
-#endif
-
-//! @brief Format value for bitfield SPI_SR_RFDF.
-#define BF_SPI_SR_RFDF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_RFDF), uint32_t) & BM_SPI_SR_RFDF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RFDF field to a new value.
-#define BW_SPI_SR_RFDF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFDF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_SR, field RFOF[19] (W1C)
- *
- * Indicates an overflow condition in the RX FIFO. The field is set when the RX
- * FIFO and shift register are full and a transfer is initiated. The bit remains
- * set until it is cleared by writing a 1 to it.
- *
- * Values:
- * - 0 - No Rx FIFO overflow.
- * - 1 - Rx FIFO overflow has occurred.
- */
-//@{
-#define BP_SPI_SR_RFOF (19U) //!< Bit position for SPI_SR_RFOF.
-#define BM_SPI_SR_RFOF (0x00080000U) //!< Bit mask for SPI_SR_RFOF.
-#define BS_SPI_SR_RFOF (1U) //!< Bit field size in bits for SPI_SR_RFOF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_SR_RFOF field.
-#define BR_SPI_SR_RFOF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFOF))
-#endif
-
-//! @brief Format value for bitfield SPI_SR_RFOF.
-#define BF_SPI_SR_RFOF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_RFOF), uint32_t) & BM_SPI_SR_RFOF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RFOF field to a new value.
-#define BW_SPI_SR_RFOF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFOF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_SR, field TFFF[25] (W1C)
- *
- * Provides a method for the module to request more entries to be added to the
- * TX FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be
- * cleared by writing 1 to it or by acknowledgement from the DMA controller to
- * the TX FIFO full request.
- *
- * Values:
- * - 0 - TX FIFO is full.
- * - 1 - TX FIFO is not full.
- */
-//@{
-#define BP_SPI_SR_TFFF (25U) //!< Bit position for SPI_SR_TFFF.
-#define BM_SPI_SR_TFFF (0x02000000U) //!< Bit mask for SPI_SR_TFFF.
-#define BS_SPI_SR_TFFF (1U) //!< Bit field size in bits for SPI_SR_TFFF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_SR_TFFF field.
-#define BR_SPI_SR_TFFF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFFF))
-#endif
-
-//! @brief Format value for bitfield SPI_SR_TFFF.
-#define BF_SPI_SR_TFFF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_TFFF), uint32_t) & BM_SPI_SR_TFFF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TFFF field to a new value.
-#define BW_SPI_SR_TFFF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFFF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_SR, field TFUF[27] (W1C)
- *
- * Indicates an underflow condition in the TX FIFO. The transmit underflow
- * condition is detected only for SPI blocks operating in Slave mode and SPI
- * configuration. TFUF is set when the TX FIFO of the module operating in SPI Slave mode
- * is empty and an external SPI master initiates a transfer. The TFUF bit remains
- * set until cleared by writing 1 to it.
- *
- * Values:
- * - 0 - No TX FIFO underflow.
- * - 1 - TX FIFO underflow has occurred.
- */
-//@{
-#define BP_SPI_SR_TFUF (27U) //!< Bit position for SPI_SR_TFUF.
-#define BM_SPI_SR_TFUF (0x08000000U) //!< Bit mask for SPI_SR_TFUF.
-#define BS_SPI_SR_TFUF (1U) //!< Bit field size in bits for SPI_SR_TFUF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_SR_TFUF field.
-#define BR_SPI_SR_TFUF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFUF))
-#endif
-
-//! @brief Format value for bitfield SPI_SR_TFUF.
-#define BF_SPI_SR_TFUF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_TFUF), uint32_t) & BM_SPI_SR_TFUF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TFUF field to a new value.
-#define BW_SPI_SR_TFUF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFUF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_SR, field EOQF[28] (W1C)
- *
- * Indicates that the last entry in a queue has been transmitted when the module
- * is in Master mode. The EOQF bit is set when the TX FIFO entry has the EOQ bit
- * set in the command halfword and the end of the transfer is reached. The EOQF
- * bit remains set until cleared by writing a 1 to it. When the EOQF bit is set,
- * the TXRXS bit is automatically cleared.
- *
- * Values:
- * - 0 - EOQ is not set in the executing command.
- * - 1 - EOQ is set in the executing SPI command.
- */
-//@{
-#define BP_SPI_SR_EOQF (28U) //!< Bit position for SPI_SR_EOQF.
-#define BM_SPI_SR_EOQF (0x10000000U) //!< Bit mask for SPI_SR_EOQF.
-#define BS_SPI_SR_EOQF (1U) //!< Bit field size in bits for SPI_SR_EOQF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_SR_EOQF field.
-#define BR_SPI_SR_EOQF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_EOQF))
-#endif
-
-//! @brief Format value for bitfield SPI_SR_EOQF.
-#define BF_SPI_SR_EOQF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_EOQF), uint32_t) & BM_SPI_SR_EOQF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EOQF field to a new value.
-#define BW_SPI_SR_EOQF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_EOQF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_SR, field TXRXS[30] (W1C)
- *
- * Reflects the run status of the module.
- *
- * Values:
- * - 0 - Transmit and receive operations are disabled (The module is in Stopped
- * state).
- * - 1 - Transmit and receive operations are enabled (The module is in Running
- * state).
- */
-//@{
-#define BP_SPI_SR_TXRXS (30U) //!< Bit position for SPI_SR_TXRXS.
-#define BM_SPI_SR_TXRXS (0x40000000U) //!< Bit mask for SPI_SR_TXRXS.
-#define BS_SPI_SR_TXRXS (1U) //!< Bit field size in bits for SPI_SR_TXRXS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_SR_TXRXS field.
-#define BR_SPI_SR_TXRXS(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TXRXS))
-#endif
-
-//! @brief Format value for bitfield SPI_SR_TXRXS.
-#define BF_SPI_SR_TXRXS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_TXRXS), uint32_t) & BM_SPI_SR_TXRXS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TXRXS field to a new value.
-#define BW_SPI_SR_TXRXS(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TXRXS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_SR, field TCF[31] (W1C)
- *
- * Indicates that all bits in a frame have been shifted out. TCF remains set
- * until it is cleared by writing a 1 to it.
- *
- * Values:
- * - 0 - Transfer not complete.
- * - 1 - Transfer complete.
- */
-//@{
-#define BP_SPI_SR_TCF (31U) //!< Bit position for SPI_SR_TCF.
-#define BM_SPI_SR_TCF (0x80000000U) //!< Bit mask for SPI_SR_TCF.
-#define BS_SPI_SR_TCF (1U) //!< Bit field size in bits for SPI_SR_TCF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_SR_TCF field.
-#define BR_SPI_SR_TCF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TCF))
-#endif
-
-//! @brief Format value for bitfield SPI_SR_TCF.
-#define BF_SPI_SR_TCF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_TCF), uint32_t) & BM_SPI_SR_TCF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TCF field to a new value.
-#define BW_SPI_SR_TCF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TCF) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register (RW)
- *
- * Reset value: 0x00000000U
- *
- * RSER controls DMA and interrupt requests. Do not write to the RSER while the
- * module is in the Running state.
- */
-typedef union _hw_spi_rser
-{
- uint32_t U;
- struct _hw_spi_rser_bitfields
- {
- uint32_t RESERVED0 : 16; //!< [15:0]
- uint32_t RFDF_DIRS : 1; //!< [16] Receive FIFO Drain DMA or Interrupt
- //! Request Select
- uint32_t RFDF_RE : 1; //!< [17] Receive FIFO Drain Request Enable
- uint32_t RESERVED1 : 1; //!< [18]
- uint32_t RFOF_RE : 1; //!< [19] Receive FIFO Overflow Request Enable
- uint32_t RESERVED2 : 4; //!< [23:20]
- uint32_t TFFF_DIRS : 1; //!< [24] Transmit FIFO Fill DMA or Interrupt
- //! Request Select
- uint32_t TFFF_RE : 1; //!< [25] Transmit FIFO Fill Request Enable
- uint32_t RESERVED3 : 1; //!< [26]
- uint32_t TFUF_RE : 1; //!< [27] Transmit FIFO Underflow Request Enable
- uint32_t EOQF_RE : 1; //!< [28] Finished Request Enable
- uint32_t RESERVED4 : 2; //!< [30:29]
- uint32_t TCF_RE : 1; //!< [31] Transmission Complete Request Enable
- } B;
-} hw_spi_rser_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SPI_RSER register
- */
-//@{
-#define HW_SPI_RSER_ADDR(x) (REGS_SPI_BASE(x) + 0x30U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SPI_RSER(x) (*(__IO hw_spi_rser_t *) HW_SPI_RSER_ADDR(x))
-#define HW_SPI_RSER_RD(x) (HW_SPI_RSER(x).U)
-#define HW_SPI_RSER_WR(x, v) (HW_SPI_RSER(x).U = (v))
-#define HW_SPI_RSER_SET(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) | (v)))
-#define HW_SPI_RSER_CLR(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) & ~(v)))
-#define HW_SPI_RSER_TOG(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SPI_RSER bitfields
- */
-
-/*!
- * @name Register SPI_RSER, field RFDF_DIRS[16] (RW)
- *
- * Selects between generating a DMA request or an interrupt request. When the
- * RFDF flag bit in the SR is set, and the RFDF_RE bit in the RSER is set, the
- * RFDF_DIRS bit selects between generating an interrupt request or a DMA request.
- *
- * Values:
- * - 0 - Interrupt request.
- * - 1 - DMA request.
- */
-//@{
-#define BP_SPI_RSER_RFDF_DIRS (16U) //!< Bit position for SPI_RSER_RFDF_DIRS.
-#define BM_SPI_RSER_RFDF_DIRS (0x00010000U) //!< Bit mask for SPI_RSER_RFDF_DIRS.
-#define BS_SPI_RSER_RFDF_DIRS (1U) //!< Bit field size in bits for SPI_RSER_RFDF_DIRS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_RSER_RFDF_DIRS field.
-#define BR_SPI_RSER_RFDF_DIRS(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_DIRS))
-#endif
-
-//! @brief Format value for bitfield SPI_RSER_RFDF_DIRS.
-#define BF_SPI_RSER_RFDF_DIRS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_RFDF_DIRS), uint32_t) & BM_SPI_RSER_RFDF_DIRS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RFDF_DIRS field to a new value.
-#define BW_SPI_RSER_RFDF_DIRS(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_DIRS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_RSER, field RFDF_RE[17] (RW)
- *
- * Enables the RFDF flag in the SR to generate a request. The RFDF_DIRS bit
- * selects between generating an interrupt request or a DMA request.
- *
- * Values:
- * - 0 - RFDF interrupt or DMA requests are disabled.
- * - 1 - RFDF interrupt or DMA requests are enabled.
- */
-//@{
-#define BP_SPI_RSER_RFDF_RE (17U) //!< Bit position for SPI_RSER_RFDF_RE.
-#define BM_SPI_RSER_RFDF_RE (0x00020000U) //!< Bit mask for SPI_RSER_RFDF_RE.
-#define BS_SPI_RSER_RFDF_RE (1U) //!< Bit field size in bits for SPI_RSER_RFDF_RE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_RSER_RFDF_RE field.
-#define BR_SPI_RSER_RFDF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_RE))
-#endif
-
-//! @brief Format value for bitfield SPI_RSER_RFDF_RE.
-#define BF_SPI_RSER_RFDF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_RFDF_RE), uint32_t) & BM_SPI_RSER_RFDF_RE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RFDF_RE field to a new value.
-#define BW_SPI_RSER_RFDF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_RE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_RSER, field RFOF_RE[19] (RW)
- *
- * Enables the RFOF flag in the SR to generate an interrupt request.
- *
- * Values:
- * - 0 - RFOF interrupt requests are disabled.
- * - 1 - RFOF interrupt requests are enabled.
- */
-//@{
-#define BP_SPI_RSER_RFOF_RE (19U) //!< Bit position for SPI_RSER_RFOF_RE.
-#define BM_SPI_RSER_RFOF_RE (0x00080000U) //!< Bit mask for SPI_RSER_RFOF_RE.
-#define BS_SPI_RSER_RFOF_RE (1U) //!< Bit field size in bits for SPI_RSER_RFOF_RE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_RSER_RFOF_RE field.
-#define BR_SPI_RSER_RFOF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFOF_RE))
-#endif
-
-//! @brief Format value for bitfield SPI_RSER_RFOF_RE.
-#define BF_SPI_RSER_RFOF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_RFOF_RE), uint32_t) & BM_SPI_RSER_RFOF_RE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RFOF_RE field to a new value.
-#define BW_SPI_RSER_RFOF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFOF_RE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_RSER, field TFFF_DIRS[24] (RW)
- *
- * Selects between generating a DMA request or an interrupt request. When
- * SR[TFFF] and RSER[TFFF_RE] are set, this field selects between generating an
- * interrupt request or a DMA request.
- *
- * Values:
- * - 0 - TFFF flag generates interrupt requests.
- * - 1 - TFFF flag generates DMA requests.
- */
-//@{
-#define BP_SPI_RSER_TFFF_DIRS (24U) //!< Bit position for SPI_RSER_TFFF_DIRS.
-#define BM_SPI_RSER_TFFF_DIRS (0x01000000U) //!< Bit mask for SPI_RSER_TFFF_DIRS.
-#define BS_SPI_RSER_TFFF_DIRS (1U) //!< Bit field size in bits for SPI_RSER_TFFF_DIRS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_RSER_TFFF_DIRS field.
-#define BR_SPI_RSER_TFFF_DIRS(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_DIRS))
-#endif
-
-//! @brief Format value for bitfield SPI_RSER_TFFF_DIRS.
-#define BF_SPI_RSER_TFFF_DIRS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_TFFF_DIRS), uint32_t) & BM_SPI_RSER_TFFF_DIRS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TFFF_DIRS field to a new value.
-#define BW_SPI_RSER_TFFF_DIRS(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_DIRS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_RSER, field TFFF_RE[25] (RW)
- *
- * Enables the TFFF flag in the SR to generate a request. The TFFF_DIRS bit
- * selects between generating an interrupt request or a DMA request.
- *
- * Values:
- * - 0 - TFFF interrupts or DMA requests are disabled.
- * - 1 - TFFF interrupts or DMA requests are enabled.
- */
-//@{
-#define BP_SPI_RSER_TFFF_RE (25U) //!< Bit position for SPI_RSER_TFFF_RE.
-#define BM_SPI_RSER_TFFF_RE (0x02000000U) //!< Bit mask for SPI_RSER_TFFF_RE.
-#define BS_SPI_RSER_TFFF_RE (1U) //!< Bit field size in bits for SPI_RSER_TFFF_RE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_RSER_TFFF_RE field.
-#define BR_SPI_RSER_TFFF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_RE))
-#endif
-
-//! @brief Format value for bitfield SPI_RSER_TFFF_RE.
-#define BF_SPI_RSER_TFFF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_TFFF_RE), uint32_t) & BM_SPI_RSER_TFFF_RE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TFFF_RE field to a new value.
-#define BW_SPI_RSER_TFFF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_RE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_RSER, field TFUF_RE[27] (RW)
- *
- * Enables the TFUF flag in the SR to generate an interrupt request.
- *
- * Values:
- * - 0 - TFUF interrupt requests are disabled.
- * - 1 - TFUF interrupt requests are enabled.
- */
-//@{
-#define BP_SPI_RSER_TFUF_RE (27U) //!< Bit position for SPI_RSER_TFUF_RE.
-#define BM_SPI_RSER_TFUF_RE (0x08000000U) //!< Bit mask for SPI_RSER_TFUF_RE.
-#define BS_SPI_RSER_TFUF_RE (1U) //!< Bit field size in bits for SPI_RSER_TFUF_RE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_RSER_TFUF_RE field.
-#define BR_SPI_RSER_TFUF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFUF_RE))
-#endif
-
-//! @brief Format value for bitfield SPI_RSER_TFUF_RE.
-#define BF_SPI_RSER_TFUF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_TFUF_RE), uint32_t) & BM_SPI_RSER_TFUF_RE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TFUF_RE field to a new value.
-#define BW_SPI_RSER_TFUF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFUF_RE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_RSER, field EOQF_RE[28] (RW)
- *
- * Enables the EOQF flag in the SR to generate an interrupt request.
- *
- * Values:
- * - 0 - EOQF interrupt requests are disabled.
- * - 1 - EOQF interrupt requests are enabled.
- */
-//@{
-#define BP_SPI_RSER_EOQF_RE (28U) //!< Bit position for SPI_RSER_EOQF_RE.
-#define BM_SPI_RSER_EOQF_RE (0x10000000U) //!< Bit mask for SPI_RSER_EOQF_RE.
-#define BS_SPI_RSER_EOQF_RE (1U) //!< Bit field size in bits for SPI_RSER_EOQF_RE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_RSER_EOQF_RE field.
-#define BR_SPI_RSER_EOQF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_EOQF_RE))
-#endif
-
-//! @brief Format value for bitfield SPI_RSER_EOQF_RE.
-#define BF_SPI_RSER_EOQF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_EOQF_RE), uint32_t) & BM_SPI_RSER_EOQF_RE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EOQF_RE field to a new value.
-#define BW_SPI_RSER_EOQF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_EOQF_RE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_RSER, field TCF_RE[31] (RW)
- *
- * Enables TCF flag in the SR to generate an interrupt request.
- *
- * Values:
- * - 0 - TCF interrupt requests are disabled.
- * - 1 - TCF interrupt requests are enabled.
- */
-//@{
-#define BP_SPI_RSER_TCF_RE (31U) //!< Bit position for SPI_RSER_TCF_RE.
-#define BM_SPI_RSER_TCF_RE (0x80000000U) //!< Bit mask for SPI_RSER_TCF_RE.
-#define BS_SPI_RSER_TCF_RE (1U) //!< Bit field size in bits for SPI_RSER_TCF_RE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_RSER_TCF_RE field.
-#define BR_SPI_RSER_TCF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TCF_RE))
-#endif
-
-//! @brief Format value for bitfield SPI_RSER_TCF_RE.
-#define BF_SPI_RSER_TCF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_TCF_RE), uint32_t) & BM_SPI_RSER_TCF_RE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TCF_RE field to a new value.
-#define BW_SPI_RSER_TCF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TCF_RE) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode (RW)
- *
- * Reset value: 0x00000000U
- *
- * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
- * transfers all 32 bits to the TX FIFO. In Master mode, the register transfers
- * 16 bits of data and 16 bits of command information. In Slave mode, all 32 bits
- * can be used as data, supporting up to 32-bit frame operation. A read access
- * of PUSHR returns the topmost TX FIFO entry. When the module is disabled,
- * writing to this register does not update the FIFO. Therefore, any reads performed
- * while the module is disabled return the last PUSHR write performed while the
- * module was still enabled.
- */
-typedef union _hw_spi_pushr
-{
- uint32_t U;
- struct _hw_spi_pushr_bitfields
- {
- uint32_t TXDATA : 16; //!< [15:0] Transmit Data
- uint32_t PCS : 6; //!< [21:16]
- uint32_t RESERVED0 : 4; //!< [25:22]
- uint32_t CTCNT : 1; //!< [26] Clear Transfer Counter
- uint32_t EOQ : 1; //!< [27] End Of Queue
- uint32_t CTAS : 3; //!< [30:28] Clock and Transfer Attributes Select
- uint32_t CONT : 1; //!< [31] Continuous Peripheral Chip Select Enable
- } B;
-} hw_spi_pushr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SPI_PUSHR register
- */
-//@{
-#define HW_SPI_PUSHR_ADDR(x) (REGS_SPI_BASE(x) + 0x34U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SPI_PUSHR(x) (*(__IO hw_spi_pushr_t *) HW_SPI_PUSHR_ADDR(x))
-#define HW_SPI_PUSHR_RD(x) (HW_SPI_PUSHR(x).U)
-#define HW_SPI_PUSHR_WR(x, v) (HW_SPI_PUSHR(x).U = (v))
-#define HW_SPI_PUSHR_SET(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) | (v)))
-#define HW_SPI_PUSHR_CLR(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) & ~(v)))
-#define HW_SPI_PUSHR_TOG(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SPI_PUSHR bitfields
- */
-
-/*!
- * @name Register SPI_PUSHR, field TXDATA[15:0] (RW)
- *
- * Holds SPI data to be transferred according to the associated SPI command.
- */
-//@{
-#define BP_SPI_PUSHR_TXDATA (0U) //!< Bit position for SPI_PUSHR_TXDATA.
-#define BM_SPI_PUSHR_TXDATA (0x0000FFFFU) //!< Bit mask for SPI_PUSHR_TXDATA.
-#define BS_SPI_PUSHR_TXDATA (16U) //!< Bit field size in bits for SPI_PUSHR_TXDATA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_PUSHR_TXDATA field.
-#define BR_SPI_PUSHR_TXDATA(x) (HW_SPI_PUSHR(x).B.TXDATA)
-#endif
-
-//! @brief Format value for bitfield SPI_PUSHR_TXDATA.
-#define BF_SPI_PUSHR_TXDATA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_TXDATA), uint32_t) & BM_SPI_PUSHR_TXDATA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TXDATA field to a new value.
-#define BW_SPI_PUSHR_TXDATA(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_TXDATA) | BF_SPI_PUSHR_TXDATA(v)))
-#endif
-//@}
-
-/*!
- * @name Register SPI_PUSHR, field PCS[21:16] (RW)
- *
- * Select which PCS signals are to be asserted for the transfer. Refer to the
- * chip configuration details for the number of PCS signals used in this MCU.
- *
- * Values:
- * - 0 - Negate the PCS[x] signal.
- * - 1 - Assert the PCS[x] signal.
- */
-//@{
-#define BP_SPI_PUSHR_PCS (16U) //!< Bit position for SPI_PUSHR_PCS.
-#define BM_SPI_PUSHR_PCS (0x003F0000U) //!< Bit mask for SPI_PUSHR_PCS.
-#define BS_SPI_PUSHR_PCS (6U) //!< Bit field size in bits for SPI_PUSHR_PCS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_PUSHR_PCS field.
-#define BR_SPI_PUSHR_PCS(x) (HW_SPI_PUSHR(x).B.PCS)
-#endif
-
-//! @brief Format value for bitfield SPI_PUSHR_PCS.
-#define BF_SPI_PUSHR_PCS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_PCS), uint32_t) & BM_SPI_PUSHR_PCS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PCS field to a new value.
-#define BW_SPI_PUSHR_PCS(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_PCS) | BF_SPI_PUSHR_PCS(v)))
-#endif
-//@}
-
-/*!
- * @name Register SPI_PUSHR, field CTCNT[26] (RW)
- *
- * Clears the TCNT field in the TCR register. The TCNT field is cleared before
- * the module starts transmitting the current SPI frame.
- *
- * Values:
- * - 0 - Do not clear the TCR[TCNT] field.
- * - 1 - Clear the TCR[TCNT] field.
- */
-//@{
-#define BP_SPI_PUSHR_CTCNT (26U) //!< Bit position for SPI_PUSHR_CTCNT.
-#define BM_SPI_PUSHR_CTCNT (0x04000000U) //!< Bit mask for SPI_PUSHR_CTCNT.
-#define BS_SPI_PUSHR_CTCNT (1U) //!< Bit field size in bits for SPI_PUSHR_CTCNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_PUSHR_CTCNT field.
-#define BR_SPI_PUSHR_CTCNT(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CTCNT))
-#endif
-
-//! @brief Format value for bitfield SPI_PUSHR_CTCNT.
-#define BF_SPI_PUSHR_CTCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_CTCNT), uint32_t) & BM_SPI_PUSHR_CTCNT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CTCNT field to a new value.
-#define BW_SPI_PUSHR_CTCNT(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CTCNT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_PUSHR, field EOQ[27] (RW)
- *
- * Host software uses this bit to signal to the module that the current SPI
- * transfer is the last in a queue. At the end of the transfer, the EOQF bit in the
- * SR is set.
- *
- * Values:
- * - 0 - The SPI data is not the last data to transfer.
- * - 1 - The SPI data is the last data to transfer.
- */
-//@{
-#define BP_SPI_PUSHR_EOQ (27U) //!< Bit position for SPI_PUSHR_EOQ.
-#define BM_SPI_PUSHR_EOQ (0x08000000U) //!< Bit mask for SPI_PUSHR_EOQ.
-#define BS_SPI_PUSHR_EOQ (1U) //!< Bit field size in bits for SPI_PUSHR_EOQ.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_PUSHR_EOQ field.
-#define BR_SPI_PUSHR_EOQ(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_EOQ))
-#endif
-
-//! @brief Format value for bitfield SPI_PUSHR_EOQ.
-#define BF_SPI_PUSHR_EOQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_EOQ), uint32_t) & BM_SPI_PUSHR_EOQ)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EOQ field to a new value.
-#define BW_SPI_PUSHR_EOQ(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_EOQ) = (v))
-#endif
-//@}
-
-/*!
- * @name Register SPI_PUSHR, field CTAS[30:28] (RW)
- *
- * Selects which CTAR to use in master mode to specify the transfer attributes
- * for the associated SPI frame. In SPI Slave mode, CTAR0 is used. See the chip
- * configuration details to determine how many CTARs this device has. You should
- * not program a value in this field for a register that is not present.
- *
- * Values:
- * - 000 - CTAR0
- * - 001 - CTAR1
- * - 010 - Reserved
- * - 011 - Reserved
- * - 100 - Reserved
- * - 101 - Reserved
- * - 110 - Reserved
- * - 111 - Reserved
- */
-//@{
-#define BP_SPI_PUSHR_CTAS (28U) //!< Bit position for SPI_PUSHR_CTAS.
-#define BM_SPI_PUSHR_CTAS (0x70000000U) //!< Bit mask for SPI_PUSHR_CTAS.
-#define BS_SPI_PUSHR_CTAS (3U) //!< Bit field size in bits for SPI_PUSHR_CTAS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_PUSHR_CTAS field.
-#define BR_SPI_PUSHR_CTAS(x) (HW_SPI_PUSHR(x).B.CTAS)
-#endif
-
-//! @brief Format value for bitfield SPI_PUSHR_CTAS.
-#define BF_SPI_PUSHR_CTAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_CTAS), uint32_t) & BM_SPI_PUSHR_CTAS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CTAS field to a new value.
-#define BW_SPI_PUSHR_CTAS(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_CTAS) | BF_SPI_PUSHR_CTAS(v)))
-#endif
-//@}
-
-/*!
- * @name Register SPI_PUSHR, field CONT[31] (RW)
- *
- * Selects a continuous selection format. The bit is used in SPI Master mode.
- * The bit enables the selected PCS signals to remain asserted between transfers.
- *
- * Values:
- * - 0 - Return PCSn signals to their inactive state between transfers.
- * - 1 - Keep PCSn signals asserted between transfers.
- */
-//@{
-#define BP_SPI_PUSHR_CONT (31U) //!< Bit position for SPI_PUSHR_CONT.
-#define BM_SPI_PUSHR_CONT (0x80000000U) //!< Bit mask for SPI_PUSHR_CONT.
-#define BS_SPI_PUSHR_CONT (1U) //!< Bit field size in bits for SPI_PUSHR_CONT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_PUSHR_CONT field.
-#define BR_SPI_PUSHR_CONT(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CONT))
-#endif
-
-//! @brief Format value for bitfield SPI_PUSHR_CONT.
-#define BF_SPI_PUSHR_CONT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_CONT), uint32_t) & BM_SPI_PUSHR_CONT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CONT field to a new value.
-#define BW_SPI_PUSHR_CONT(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CONT) = (v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode (RW)
- *
- * Reset value: 0x00000000U
- *
- * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
- * to PUSHR transfers all 32 bits to the TX FIFO. In master mode, the register
- * transfers 16 bits of data and 16 bits of command information to the TX FIFO. In
- * slave mode, all 32 register bits can be used as data, supporting up to 32-bit
- * SPI Frame operation.
- */
-typedef union _hw_spi_pushr_slave
-{
- uint32_t U;
- struct _hw_spi_pushr_slave_bitfields
- {
- uint32_t TXDATA : 32; //!< [31:0] Transmit Data
- } B;
-} hw_spi_pushr_slave_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SPI_PUSHR_SLAVE register
- */
-//@{
-#define HW_SPI_PUSHR_SLAVE_ADDR(x) (REGS_SPI_BASE(x) + 0x34U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SPI_PUSHR_SLAVE(x) (*(__IO hw_spi_pushr_slave_t *) HW_SPI_PUSHR_SLAVE_ADDR(x))
-#define HW_SPI_PUSHR_SLAVE_RD(x) (HW_SPI_PUSHR_SLAVE(x).U)
-#define HW_SPI_PUSHR_SLAVE_WR(x, v) (HW_SPI_PUSHR_SLAVE(x).U = (v))
-#define HW_SPI_PUSHR_SLAVE_SET(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) | (v)))
-#define HW_SPI_PUSHR_SLAVE_CLR(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) & ~(v)))
-#define HW_SPI_PUSHR_SLAVE_TOG(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual SPI_PUSHR_SLAVE bitfields
- */
-
-/*!
- * @name Register SPI_PUSHR_SLAVE, field TXDATA[31:0] (RW)
- *
- * Holds SPI data to be transferred according to the associated SPI command.
- */
-//@{
-#define BP_SPI_PUSHR_SLAVE_TXDATA (0U) //!< Bit position for SPI_PUSHR_SLAVE_TXDATA.
-#define BM_SPI_PUSHR_SLAVE_TXDATA (0xFFFFFFFFU) //!< Bit mask for SPI_PUSHR_SLAVE_TXDATA.
-#define BS_SPI_PUSHR_SLAVE_TXDATA (32U) //!< Bit field size in bits for SPI_PUSHR_SLAVE_TXDATA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_PUSHR_SLAVE_TXDATA field.
-#define BR_SPI_PUSHR_SLAVE_TXDATA(x) (HW_SPI_PUSHR_SLAVE(x).U)
-#endif
-
-//! @brief Format value for bitfield SPI_PUSHR_SLAVE_TXDATA.
-#define BF_SPI_PUSHR_SLAVE_TXDATA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_SLAVE_TXDATA), uint32_t) & BM_SPI_PUSHR_SLAVE_TXDATA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TXDATA field to a new value.
-#define BW_SPI_PUSHR_SLAVE_TXDATA(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SPI_POPR - POP RX FIFO Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SPI_POPR - POP RX FIFO Register (RO)
- *
- * Reset value: 0x00000000U
- *
- * POPR is used to read the RX FIFO. Eight- or sixteen-bit read accesses to the
- * POPR have the same effect on the RX FIFO as 32-bit read accesses. A write to
- * this register will generate a Transfer Error.
- */
-typedef union _hw_spi_popr
-{
- uint32_t U;
- struct _hw_spi_popr_bitfields
- {
- uint32_t RXDATA : 32; //!< [31:0] Received Data
- } B;
-} hw_spi_popr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SPI_POPR register
- */
-//@{
-#define HW_SPI_POPR_ADDR(x) (REGS_SPI_BASE(x) + 0x38U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SPI_POPR(x) (*(__I hw_spi_popr_t *) HW_SPI_POPR_ADDR(x))
-#define HW_SPI_POPR_RD(x) (HW_SPI_POPR(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual SPI_POPR bitfields
- */
-
-/*!
- * @name Register SPI_POPR, field RXDATA[31:0] (RO)
- *
- * Contains the SPI data from the RX FIFO entry to which the Pop Next Data
- * Pointer points.
- */
-//@{
-#define BP_SPI_POPR_RXDATA (0U) //!< Bit position for SPI_POPR_RXDATA.
-#define BM_SPI_POPR_RXDATA (0xFFFFFFFFU) //!< Bit mask for SPI_POPR_RXDATA.
-#define BS_SPI_POPR_RXDATA (32U) //!< Bit field size in bits for SPI_POPR_RXDATA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_POPR_RXDATA field.
-#define BR_SPI_POPR_RXDATA(x) (HW_SPI_POPR(x).U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SPI_TXFRn - Transmit FIFO Registers
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SPI_TXFRn - Transmit FIFO Registers (RO)
- *
- * Reset value: 0x00000000U
- *
- * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
- * Each register is an entry in the TX FIFO. The registers are read-only and
- * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
- * FIFO.
- */
-typedef union _hw_spi_txfrn
-{
- uint32_t U;
- struct _hw_spi_txfrn_bitfields
- {
- uint32_t TXDATA : 16; //!< [15:0] Transmit Data
- uint32_t TXCMD_TXDATA : 16; //!< [31:16] Transmit Command or Transmit
- //! Data
- } B;
-} hw_spi_txfrn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SPI_TXFRn register
- */
-//@{
-#define HW_SPI_TXFRn_COUNT (4U)
-
-#define HW_SPI_TXFRn_ADDR(x, n) (REGS_SPI_BASE(x) + 0x3CU + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SPI_TXFRn(x, n) (*(__I hw_spi_txfrn_t *) HW_SPI_TXFRn_ADDR(x, n))
-#define HW_SPI_TXFRn_RD(x, n) (HW_SPI_TXFRn(x, n).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual SPI_TXFRn bitfields
- */
-
-/*!
- * @name Register SPI_TXFRn, field TXDATA[15:0] (RO)
- *
- * Contains the SPI data to be shifted out.
- */
-//@{
-#define BP_SPI_TXFRn_TXDATA (0U) //!< Bit position for SPI_TXFRn_TXDATA.
-#define BM_SPI_TXFRn_TXDATA (0x0000FFFFU) //!< Bit mask for SPI_TXFRn_TXDATA.
-#define BS_SPI_TXFRn_TXDATA (16U) //!< Bit field size in bits for SPI_TXFRn_TXDATA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_TXFRn_TXDATA field.
-#define BR_SPI_TXFRn_TXDATA(x, n) (HW_SPI_TXFRn(x, n).B.TXDATA)
-#endif
-//@}
-
-/*!
- * @name Register SPI_TXFRn, field TXCMD_TXDATA[31:16] (RO)
- *
- * In Master mode the TXCMD field contains the command that sets the transfer
- * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
- * the SPI data to be shifted out.
- */
-//@{
-#define BP_SPI_TXFRn_TXCMD_TXDATA (16U) //!< Bit position for SPI_TXFRn_TXCMD_TXDATA.
-#define BM_SPI_TXFRn_TXCMD_TXDATA (0xFFFF0000U) //!< Bit mask for SPI_TXFRn_TXCMD_TXDATA.
-#define BS_SPI_TXFRn_TXCMD_TXDATA (16U) //!< Bit field size in bits for SPI_TXFRn_TXCMD_TXDATA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_TXFRn_TXCMD_TXDATA field.
-#define BR_SPI_TXFRn_TXCMD_TXDATA(x, n) (HW_SPI_TXFRn(x, n).B.TXCMD_TXDATA)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_SPI_RXFRn - Receive FIFO Registers
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_SPI_RXFRn - Receive FIFO Registers (RO)
- *
- * Reset value: 0x00000000U
- *
- * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
- * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
- * RXFRx registers does not alter the state of the RX FIFO.
- */
-typedef union _hw_spi_rxfrn
-{
- uint32_t U;
- struct _hw_spi_rxfrn_bitfields
- {
- uint32_t RXDATA : 32; //!< [31:0] Receive Data
- } B;
-} hw_spi_rxfrn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire SPI_RXFRn register
- */
-//@{
-#define HW_SPI_RXFRn_COUNT (4U)
-
-#define HW_SPI_RXFRn_ADDR(x, n) (REGS_SPI_BASE(x) + 0x7CU + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_SPI_RXFRn(x, n) (*(__I hw_spi_rxfrn_t *) HW_SPI_RXFRn_ADDR(x, n))
-#define HW_SPI_RXFRn_RD(x, n) (HW_SPI_RXFRn(x, n).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual SPI_RXFRn bitfields
- */
-
-/*!
- * @name Register SPI_RXFRn, field RXDATA[31:0] (RO)
- *
- * Contains the received SPI data.
- */
-//@{
-#define BP_SPI_RXFRn_RXDATA (0U) //!< Bit position for SPI_RXFRn_RXDATA.
-#define BM_SPI_RXFRn_RXDATA (0xFFFFFFFFU) //!< Bit mask for SPI_RXFRn_RXDATA.
-#define BS_SPI_RXFRn_RXDATA (32U) //!< Bit field size in bits for SPI_RXFRn_RXDATA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the SPI_RXFRn_RXDATA field.
-#define BR_SPI_RXFRn_RXDATA(x, n) (HW_SPI_RXFRn(x, n).U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_spi_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All SPI module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_spi
-{
- __IO hw_spi_mcr_t MCR; //!< [0x0] Module Configuration Register
- uint8_t _reserved0[4];
- __IO hw_spi_tcr_t TCR; //!< [0x8] Transfer Count Register
- union {
- __IO hw_spi_ctarn_t CTARn[2]; //!< [0xC] Clock and Transfer Attributes Register (In Master Mode)
- __IO hw_spi_ctarn_slave_t CTARn_SLAVE[1]; //!< [0xC] Clock and Transfer Attributes Register (In Slave Mode)
- };
- uint8_t _reserved1[24];
- __IO hw_spi_sr_t SR; //!< [0x2C] Status Register
- __IO hw_spi_rser_t RSER; //!< [0x30] DMA/Interrupt Request Select and Enable Register
- union {
- __IO hw_spi_pushr_t PUSHR; //!< [0x34] PUSH TX FIFO Register In Master Mode
- __IO hw_spi_pushr_slave_t PUSHR_SLAVE; //!< [0x34] PUSH TX FIFO Register In Slave Mode
- };
- __I hw_spi_popr_t POPR; //!< [0x38] POP RX FIFO Register
- __I hw_spi_txfrn_t TXFRn[4]; //!< [0x3C] Transmit FIFO Registers
- uint8_t _reserved2[48];
- __I hw_spi_rxfrn_t RXFRn[4]; //!< [0x7C] Receive FIFO Registers
-} hw_spi_t;
-#pragma pack()
-
-//! @brief Macro to access all SPI registers.
-//! @param x SPI instance number.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_SPI(0)</code>.
-#define HW_SPI(x) (*(hw_spi_t *) REGS_SPI_BASE(x))
-#endif
-
-#endif // __HW_SPI_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_uart.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,4933 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_UART_REGISTERS_H__
-#define __HW_UART_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 UART
- *
- * Serial Communication Interface
- *
- * Registers defined in this header file:
- * - HW_UART_BDH - UART Baud Rate Registers: High
- * - HW_UART_BDL - UART Baud Rate Registers: Low
- * - HW_UART_C1 - UART Control Register 1
- * - HW_UART_C2 - UART Control Register 2
- * - HW_UART_S1 - UART Status Register 1
- * - HW_UART_S2 - UART Status Register 2
- * - HW_UART_C3 - UART Control Register 3
- * - HW_UART_D - UART Data Register
- * - HW_UART_MA1 - UART Match Address Registers 1
- * - HW_UART_MA2 - UART Match Address Registers 2
- * - HW_UART_C4 - UART Control Register 4
- * - HW_UART_C5 - UART Control Register 5
- * - HW_UART_ED - UART Extended Data Register
- * - HW_UART_MODEM - UART Modem Register
- * - HW_UART_IR - UART Infrared Register
- * - HW_UART_PFIFO - UART FIFO Parameters
- * - HW_UART_CFIFO - UART FIFO Control Register
- * - HW_UART_SFIFO - UART FIFO Status Register
- * - HW_UART_TWFIFO - UART FIFO Transmit Watermark
- * - HW_UART_TCFIFO - UART FIFO Transmit Count
- * - HW_UART_RWFIFO - UART FIFO Receive Watermark
- * - HW_UART_RCFIFO - UART FIFO Receive Count
- * - HW_UART_C7816 - UART 7816 Control Register
- * - HW_UART_IE7816 - UART 7816 Interrupt Enable Register
- * - HW_UART_IS7816 - UART 7816 Interrupt Status Register
- * - HW_UART_WP7816_T_TYPE0 - UART 7816 Wait Parameter Register
- * - HW_UART_WP7816_T_TYPE1 - UART 7816 Wait Parameter Register
- * - HW_UART_WN7816 - UART 7816 Wait N Register
- * - HW_UART_WF7816 - UART 7816 Wait FD Register
- * - HW_UART_ET7816 - UART 7816 Error Threshold Register
- * - HW_UART_TL7816 - UART 7816 Transmit Length Register
- *
- * - hw_uart_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_UART_BASE
-#define HW_UART_INSTANCE_COUNT (6U) //!< Number of instances of the UART module.
-#define HW_UART0 (0U) //!< Instance number for UART0.
-#define HW_UART1 (1U) //!< Instance number for UART1.
-#define HW_UART2 (2U) //!< Instance number for UART2.
-#define HW_UART3 (3U) //!< Instance number for UART3.
-#define HW_UART4 (4U) //!< Instance number for UART4.
-#define HW_UART5 (5U) //!< Instance number for UART5.
-#define REGS_UART0_BASE (0x4006A000U) //!< Base address for UART0.
-#define REGS_UART1_BASE (0x4006B000U) //!< Base address for UART1.
-#define REGS_UART2_BASE (0x4006C000U) //!< Base address for UART2.
-#define REGS_UART3_BASE (0x4006D000U) //!< Base address for UART3.
-#define REGS_UART4_BASE (0x400EA000U) //!< Base address for UART4.
-#define REGS_UART5_BASE (0x400EB000U) //!< Base address for UART5.
-
-//! @brief Table of base addresses for UART instances.
-static const uint32_t __g_regs_UART_base_addresses[] = {
- REGS_UART0_BASE,
- REGS_UART1_BASE,
- REGS_UART2_BASE,
- REGS_UART3_BASE,
- REGS_UART4_BASE,
- REGS_UART5_BASE,
- };
-
-//! @brief Get the base address of UART by instance number.
-//! @param x UART instance number, from 0 through 5.
-#define REGS_UART_BASE(x) (__g_regs_UART_base_addresses[(x)])
-
-//! @brief Get the instance number given a base address.
-//! @param b Base address for an instance of UART.
-#define REGS_UART_INSTANCE(b) ((b) == REGS_UART0_BASE ? HW_UART0 : (b) == REGS_UART1_BASE ? HW_UART1 : (b) == REGS_UART2_BASE ? HW_UART2 : (b) == REGS_UART3_BASE ? HW_UART3 : (b) == REGS_UART4_BASE ? HW_UART4 : (b) == REGS_UART5_BASE ? HW_UART5 : 0)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_BDH - UART Baud Rate Registers: High
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_BDH - UART Baud Rate Registers: High (RW)
- *
- * Reset value: 0x00U
- *
- * This register, along with the BDL register, controls the prescale divisor for
- * UART baud rate generation. To update the 13-bit baud rate setting
- * (SBR[12:0]), first write to BDH to buffer the high half of the new value and then write
- * to BDL. The working value in BDH does not change until BDL is written. BDL is
- * reset to a nonzero value, but after reset, the baud rate generator remains
- * disabled until the first time the receiver or transmitter is enabled, that is,
- * when C2[RE] or C2[TE] is set.
- */
-typedef union _hw_uart_bdh
-{
- uint8_t U;
- struct _hw_uart_bdh_bitfields
- {
- uint8_t SBR : 5; //!< [4:0] UART Baud Rate Bits
- uint8_t SBNS : 1; //!< [5] Stop Bit Number Select
- uint8_t RXEDGIE : 1; //!< [6] RxD Input Active Edge Interrupt Enable
- uint8_t LBKDIE : 1; //!< [7] LIN Break Detect Interrupt or DMA
- //! Request Enable
- } B;
-} hw_uart_bdh_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_BDH register
- */
-//@{
-#define HW_UART_BDH_ADDR(x) (REGS_UART_BASE(x) + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_BDH(x) (*(__IO hw_uart_bdh_t *) HW_UART_BDH_ADDR(x))
-#define HW_UART_BDH_RD(x) (HW_UART_BDH(x).U)
-#define HW_UART_BDH_WR(x, v) (HW_UART_BDH(x).U = (v))
-#define HW_UART_BDH_SET(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) | (v)))
-#define HW_UART_BDH_CLR(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) & ~(v)))
-#define HW_UART_BDH_TOG(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_BDH bitfields
- */
-
-/*!
- * @name Register UART_BDH, field SBR[4:0] (RW)
- *
- * The baud rate for the UART is determined by the 13 SBR fields. See Baud rate
- * generation for details. The baud rate generator is disabled until C2[TE] or
- * C2[RE] is set for the first time after reset.The baud rate generator is disabled
- * when SBR = 0. Writing to BDH has no effect without writing to BDL, because
- * writing to BDH puts the data in a temporary location until BDL is written.
- */
-//@{
-#define BP_UART_BDH_SBR (0U) //!< Bit position for UART_BDH_SBR.
-#define BM_UART_BDH_SBR (0x1FU) //!< Bit mask for UART_BDH_SBR.
-#define BS_UART_BDH_SBR (5U) //!< Bit field size in bits for UART_BDH_SBR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_BDH_SBR field.
-#define BR_UART_BDH_SBR(x) (HW_UART_BDH(x).B.SBR)
-#endif
-
-//! @brief Format value for bitfield UART_BDH_SBR.
-#define BF_UART_BDH_SBR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_BDH_SBR), uint8_t) & BM_UART_BDH_SBR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SBR field to a new value.
-#define BW_UART_BDH_SBR(x, v) (HW_UART_BDH_WR(x, (HW_UART_BDH_RD(x) & ~BM_UART_BDH_SBR) | BF_UART_BDH_SBR(v)))
-#endif
-//@}
-
-/*!
- * @name Register UART_BDH, field SBNS[5] (RW)
- *
- * SBNS selects the number of stop bits present in a data frame. This field
- * valid for all 8, 9 and 10 bit data formats available. This field is not valid when
- * C7816[ISO7816E] is enabled.
- *
- * Values:
- * - 0 - Data frame consists of a single stop bit.
- * - 1 - Data frame consists of two stop bits.
- */
-//@{
-#define BP_UART_BDH_SBNS (5U) //!< Bit position for UART_BDH_SBNS.
-#define BM_UART_BDH_SBNS (0x20U) //!< Bit mask for UART_BDH_SBNS.
-#define BS_UART_BDH_SBNS (1U) //!< Bit field size in bits for UART_BDH_SBNS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_BDH_SBNS field.
-#define BR_UART_BDH_SBNS(x) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_SBNS))
-#endif
-
-//! @brief Format value for bitfield UART_BDH_SBNS.
-#define BF_UART_BDH_SBNS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_BDH_SBNS), uint8_t) & BM_UART_BDH_SBNS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SBNS field to a new value.
-#define BW_UART_BDH_SBNS(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_SBNS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_BDH, field RXEDGIE[6] (RW)
- *
- * Enables the receive input active edge, RXEDGIF, to generate interrupt
- * requests.
- *
- * Values:
- * - 0 - Hardware interrupts from RXEDGIF disabled using polling.
- * - 1 - RXEDGIF interrupt request enabled.
- */
-//@{
-#define BP_UART_BDH_RXEDGIE (6U) //!< Bit position for UART_BDH_RXEDGIE.
-#define BM_UART_BDH_RXEDGIE (0x40U) //!< Bit mask for UART_BDH_RXEDGIE.
-#define BS_UART_BDH_RXEDGIE (1U) //!< Bit field size in bits for UART_BDH_RXEDGIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_BDH_RXEDGIE field.
-#define BR_UART_BDH_RXEDGIE(x) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_RXEDGIE))
-#endif
-
-//! @brief Format value for bitfield UART_BDH_RXEDGIE.
-#define BF_UART_BDH_RXEDGIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_BDH_RXEDGIE), uint8_t) & BM_UART_BDH_RXEDGIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RXEDGIE field to a new value.
-#define BW_UART_BDH_RXEDGIE(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_RXEDGIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_BDH, field LBKDIE[7] (RW)
- *
- * Enables the LIN break detect flag, LBKDIF, to generate interrupt requests
- * based on the state of LBKDDMAS. or DMA transfer requests,
- *
- * Values:
- * - 0 - LBKDIF interrupt and DMA transfer requests disabled.
- * - 1 - LBKDIF interrupt or DMA transfer requests enabled.
- */
-//@{
-#define BP_UART_BDH_LBKDIE (7U) //!< Bit position for UART_BDH_LBKDIE.
-#define BM_UART_BDH_LBKDIE (0x80U) //!< Bit mask for UART_BDH_LBKDIE.
-#define BS_UART_BDH_LBKDIE (1U) //!< Bit field size in bits for UART_BDH_LBKDIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_BDH_LBKDIE field.
-#define BR_UART_BDH_LBKDIE(x) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_LBKDIE))
-#endif
-
-//! @brief Format value for bitfield UART_BDH_LBKDIE.
-#define BF_UART_BDH_LBKDIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_BDH_LBKDIE), uint8_t) & BM_UART_BDH_LBKDIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LBKDIE field to a new value.
-#define BW_UART_BDH_LBKDIE(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_LBKDIE) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_BDL - UART Baud Rate Registers: Low
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_BDL - UART Baud Rate Registers: Low (RW)
- *
- * Reset value: 0x04U
- *
- * This register, along with the BDH register, controls the prescale divisor for
- * UART baud rate generation. To update the 13-bit baud rate setting, SBR[12:0],
- * first write to BDH to buffer the high half of the new value and then write to
- * BDL. The working value in BDH does not change until BDL is written. BDL is
- * reset to a nonzero value, but after reset, the baud rate generator remains
- * disabled until the first time the receiver or transmitter is enabled, that is, when
- * C2[RE] or C2[TE] is set.
- */
-typedef union _hw_uart_bdl
-{
- uint8_t U;
- struct _hw_uart_bdl_bitfields
- {
- uint8_t SBR : 8; //!< [7:0] UART Baud Rate Bits
- } B;
-} hw_uart_bdl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_BDL register
- */
-//@{
-#define HW_UART_BDL_ADDR(x) (REGS_UART_BASE(x) + 0x1U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_BDL(x) (*(__IO hw_uart_bdl_t *) HW_UART_BDL_ADDR(x))
-#define HW_UART_BDL_RD(x) (HW_UART_BDL(x).U)
-#define HW_UART_BDL_WR(x, v) (HW_UART_BDL(x).U = (v))
-#define HW_UART_BDL_SET(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) | (v)))
-#define HW_UART_BDL_CLR(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) & ~(v)))
-#define HW_UART_BDL_TOG(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_BDL bitfields
- */
-
-/*!
- * @name Register UART_BDL, field SBR[7:0] (RW)
- *
- * The baud rate for the UART is determined by the 13 SBR fields. See Baud rate
- * generation for details. The baud rate generator is disabled until C2[TE] or
- * C2[RE] is set for the first time after reset.The baud rate generator is disabled
- * when SBR = 0. Writing to BDH has no effect without writing to BDL, because
- * writing to BDH puts the data in a temporary location until BDL is written. When
- * the 1/32 narrow pulse width is selected for infrared (IrDA), the baud rate
- * fields must be even, the least significant bit is 0. See MODEM register for more
- * details.
- */
-//@{
-#define BP_UART_BDL_SBR (0U) //!< Bit position for UART_BDL_SBR.
-#define BM_UART_BDL_SBR (0xFFU) //!< Bit mask for UART_BDL_SBR.
-#define BS_UART_BDL_SBR (8U) //!< Bit field size in bits for UART_BDL_SBR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_BDL_SBR field.
-#define BR_UART_BDL_SBR(x) (HW_UART_BDL(x).U)
-#endif
-
-//! @brief Format value for bitfield UART_BDL_SBR.
-#define BF_UART_BDL_SBR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_BDL_SBR), uint8_t) & BM_UART_BDL_SBR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SBR field to a new value.
-#define BW_UART_BDL_SBR(x, v) (HW_UART_BDL_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_C1 - UART Control Register 1
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_C1 - UART Control Register 1 (RW)
- *
- * Reset value: 0x00U
- *
- * This read/write register controls various optional features of the UART
- * system.
- */
-typedef union _hw_uart_c1
-{
- uint8_t U;
- struct _hw_uart_c1_bitfields
- {
- uint8_t PT : 1; //!< [0] Parity Type
- uint8_t PE : 1; //!< [1] Parity Enable
- uint8_t ILT : 1; //!< [2] Idle Line Type Select
- uint8_t WAKE : 1; //!< [3] Receiver Wakeup Method Select
- uint8_t M : 1; //!< [4] 9-bit or 8-bit Mode Select
- uint8_t RSRC : 1; //!< [5] Receiver Source Select
- uint8_t UARTSWAI : 1; //!< [6] UART Stops in Wait Mode
- uint8_t LOOPS : 1; //!< [7] Loop Mode Select
- } B;
-} hw_uart_c1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_C1 register
- */
-//@{
-#define HW_UART_C1_ADDR(x) (REGS_UART_BASE(x) + 0x2U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_C1(x) (*(__IO hw_uart_c1_t *) HW_UART_C1_ADDR(x))
-#define HW_UART_C1_RD(x) (HW_UART_C1(x).U)
-#define HW_UART_C1_WR(x, v) (HW_UART_C1(x).U = (v))
-#define HW_UART_C1_SET(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) | (v)))
-#define HW_UART_C1_CLR(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) & ~(v)))
-#define HW_UART_C1_TOG(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_C1 bitfields
- */
-
-/*!
- * @name Register UART_C1, field PT[0] (RW)
- *
- * Determines whether the UART generates and checks for even parity or odd
- * parity. With even parity, an even number of 1s clears the parity bit and an odd
- * number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the
- * parity bit and an even number of 1s sets the parity bit. This field must be
- * cleared when C7816[ISO_7816E] is set/enabled.
- *
- * Values:
- * - 0 - Even parity.
- * - 1 - Odd parity.
- */
-//@{
-#define BP_UART_C1_PT (0U) //!< Bit position for UART_C1_PT.
-#define BM_UART_C1_PT (0x01U) //!< Bit mask for UART_C1_PT.
-#define BS_UART_C1_PT (1U) //!< Bit field size in bits for UART_C1_PT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C1_PT field.
-#define BR_UART_C1_PT(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PT))
-#endif
-
-//! @brief Format value for bitfield UART_C1_PT.
-#define BF_UART_C1_PT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_PT), uint8_t) & BM_UART_C1_PT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PT field to a new value.
-#define BW_UART_C1_PT(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C1, field PE[1] (RW)
- *
- * Enables the parity function. When parity is enabled, parity function inserts
- * a parity bit in the bit position immediately preceding the stop bit. This
- * field must be set when C7816[ISO_7816E] is set/enabled.
- *
- * Values:
- * - 0 - Parity function disabled.
- * - 1 - Parity function enabled.
- */
-//@{
-#define BP_UART_C1_PE (1U) //!< Bit position for UART_C1_PE.
-#define BM_UART_C1_PE (0x02U) //!< Bit mask for UART_C1_PE.
-#define BS_UART_C1_PE (1U) //!< Bit field size in bits for UART_C1_PE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C1_PE field.
-#define BR_UART_C1_PE(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PE))
-#endif
-
-//! @brief Format value for bitfield UART_C1_PE.
-#define BF_UART_C1_PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_PE), uint8_t) & BM_UART_C1_PE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PE field to a new value.
-#define BW_UART_C1_PE(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C1, field ILT[2] (RW)
- *
- * Determines when the receiver starts counting logic 1s as idle character bits.
- * The count begins either after a valid start bit or after the stop bit. If the
- * count begins after the start bit, then a string of logic 1s preceding the
- * stop bit can cause false recognition of an idle character. Beginning the count
- * after the stop bit avoids false idle character recognition, but requires
- * properly synchronized transmissions. In case the UART is programmed with ILT = 1, a
- * logic of 1'b0 is automatically shifted after a received stop bit, therefore
- * resetting the idle count. In case the UART is programmed for IDLE line wakeup
- * (RWU = 1 and WAKE = 0), ILT has no effect on when the receiver starts counting
- * logic 1s as idle character bits. In idle line wakeup, an idle character is
- * recognized at anytime the receiver sees 10, 11, or 12 1s depending on the M, PE,
- * and C4[M10] fields.
- *
- * Values:
- * - 0 - Idle character bit count starts after start bit.
- * - 1 - Idle character bit count starts after stop bit.
- */
-//@{
-#define BP_UART_C1_ILT (2U) //!< Bit position for UART_C1_ILT.
-#define BM_UART_C1_ILT (0x04U) //!< Bit mask for UART_C1_ILT.
-#define BS_UART_C1_ILT (1U) //!< Bit field size in bits for UART_C1_ILT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C1_ILT field.
-#define BR_UART_C1_ILT(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_ILT))
-#endif
-
-//! @brief Format value for bitfield UART_C1_ILT.
-#define BF_UART_C1_ILT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_ILT), uint8_t) & BM_UART_C1_ILT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ILT field to a new value.
-#define BW_UART_C1_ILT(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_ILT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C1, field WAKE[3] (RW)
- *
- * Determines which condition wakes the UART: Address mark in the most
- * significant bit position of a received data character, or An idle condition on the
- * receive pin input signal.
- *
- * Values:
- * - 0 - Idle line wakeup.
- * - 1 - Address mark wakeup.
- */
-//@{
-#define BP_UART_C1_WAKE (3U) //!< Bit position for UART_C1_WAKE.
-#define BM_UART_C1_WAKE (0x08U) //!< Bit mask for UART_C1_WAKE.
-#define BS_UART_C1_WAKE (1U) //!< Bit field size in bits for UART_C1_WAKE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C1_WAKE field.
-#define BR_UART_C1_WAKE(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_WAKE))
-#endif
-
-//! @brief Format value for bitfield UART_C1_WAKE.
-#define BF_UART_C1_WAKE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_WAKE), uint8_t) & BM_UART_C1_WAKE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WAKE field to a new value.
-#define BW_UART_C1_WAKE(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_WAKE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C1, field M[4] (RW)
- *
- * This field must be set when C7816[ISO_7816E] is set/enabled.
- *
- * Values:
- * - 0 - Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
- * - 1 - Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
- */
-//@{
-#define BP_UART_C1_M (4U) //!< Bit position for UART_C1_M.
-#define BM_UART_C1_M (0x10U) //!< Bit mask for UART_C1_M.
-#define BS_UART_C1_M (1U) //!< Bit field size in bits for UART_C1_M.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C1_M field.
-#define BR_UART_C1_M(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_M))
-#endif
-
-//! @brief Format value for bitfield UART_C1_M.
-#define BF_UART_C1_M(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_M), uint8_t) & BM_UART_C1_M)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M field to a new value.
-#define BW_UART_C1_M(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_M) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C1, field RSRC[5] (RW)
- *
- * This field has no meaning or effect unless the LOOPS field is set. When LOOPS
- * is set, the RSRC field determines the source for the receiver shift register
- * input.
- *
- * Values:
- * - 0 - Selects internal loop back mode. The receiver input is internally
- * connected to transmitter output.
- * - 1 - Single wire UART mode where the receiver input is connected to the
- * transmit pin input signal.
- */
-//@{
-#define BP_UART_C1_RSRC (5U) //!< Bit position for UART_C1_RSRC.
-#define BM_UART_C1_RSRC (0x20U) //!< Bit mask for UART_C1_RSRC.
-#define BS_UART_C1_RSRC (1U) //!< Bit field size in bits for UART_C1_RSRC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C1_RSRC field.
-#define BR_UART_C1_RSRC(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_RSRC))
-#endif
-
-//! @brief Format value for bitfield UART_C1_RSRC.
-#define BF_UART_C1_RSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_RSRC), uint8_t) & BM_UART_C1_RSRC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RSRC field to a new value.
-#define BW_UART_C1_RSRC(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_RSRC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C1, field UARTSWAI[6] (RW)
- *
- * Values:
- * - 0 - UART clock continues to run in Wait mode.
- * - 1 - UART clock freezes while CPU is in Wait mode.
- */
-//@{
-#define BP_UART_C1_UARTSWAI (6U) //!< Bit position for UART_C1_UARTSWAI.
-#define BM_UART_C1_UARTSWAI (0x40U) //!< Bit mask for UART_C1_UARTSWAI.
-#define BS_UART_C1_UARTSWAI (1U) //!< Bit field size in bits for UART_C1_UARTSWAI.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C1_UARTSWAI field.
-#define BR_UART_C1_UARTSWAI(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_UARTSWAI))
-#endif
-
-//! @brief Format value for bitfield UART_C1_UARTSWAI.
-#define BF_UART_C1_UARTSWAI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_UARTSWAI), uint8_t) & BM_UART_C1_UARTSWAI)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the UARTSWAI field to a new value.
-#define BW_UART_C1_UARTSWAI(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_UARTSWAI) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C1, field LOOPS[7] (RW)
- *
- * When LOOPS is set, the RxD pin is disconnected from the UART and the
- * transmitter output is internally connected to the receiver input. The transmitter and
- * the receiver must be enabled to use the loop function.
- *
- * Values:
- * - 0 - Normal operation.
- * - 1 - Loop mode where transmitter output is internally connected to receiver
- * input. The receiver input is determined by RSRC.
- */
-//@{
-#define BP_UART_C1_LOOPS (7U) //!< Bit position for UART_C1_LOOPS.
-#define BM_UART_C1_LOOPS (0x80U) //!< Bit mask for UART_C1_LOOPS.
-#define BS_UART_C1_LOOPS (1U) //!< Bit field size in bits for UART_C1_LOOPS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C1_LOOPS field.
-#define BR_UART_C1_LOOPS(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_LOOPS))
-#endif
-
-//! @brief Format value for bitfield UART_C1_LOOPS.
-#define BF_UART_C1_LOOPS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_LOOPS), uint8_t) & BM_UART_C1_LOOPS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LOOPS field to a new value.
-#define BW_UART_C1_LOOPS(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_LOOPS) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_C2 - UART Control Register 2
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_C2 - UART Control Register 2 (RW)
- *
- * Reset value: 0x00U
- *
- * This register can be read or written at any time.
- */
-typedef union _hw_uart_c2
-{
- uint8_t U;
- struct _hw_uart_c2_bitfields
- {
- uint8_t SBK : 1; //!< [0] Send Break
- uint8_t RWU : 1; //!< [1] Receiver Wakeup Control
- uint8_t RE : 1; //!< [2] Receiver Enable
- uint8_t TE : 1; //!< [3] Transmitter Enable
- uint8_t ILIE : 1; //!< [4] Idle Line Interrupt DMA Transfer Enable
- uint8_t RIE : 1; //!< [5] Receiver Full Interrupt or DMA Transfer
- //! Enable
- uint8_t TCIE : 1; //!< [6] Transmission Complete Interrupt or DMA
- //! Transfer Enable
- uint8_t TIE : 1; //!< [7] Transmitter Interrupt or DMA Transfer
- //! Enable.
- } B;
-} hw_uart_c2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_C2 register
- */
-//@{
-#define HW_UART_C2_ADDR(x) (REGS_UART_BASE(x) + 0x3U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_C2(x) (*(__IO hw_uart_c2_t *) HW_UART_C2_ADDR(x))
-#define HW_UART_C2_RD(x) (HW_UART_C2(x).U)
-#define HW_UART_C2_WR(x, v) (HW_UART_C2(x).U = (v))
-#define HW_UART_C2_SET(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) | (v)))
-#define HW_UART_C2_CLR(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) & ~(v)))
-#define HW_UART_C2_TOG(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_C2 bitfields
- */
-
-/*!
- * @name Register UART_C2, field SBK[0] (RW)
- *
- * Toggling SBK sends one break character from the following: See Transmitting
- * break characters for the number of logic 0s for the different configurations.
- * Toggling implies clearing the SBK field before the break character has finished
- * transmitting. As long as SBK is set, the transmitter continues to send
- * complete break characters (10, 11, or 12 bits, or 13 or 14 bits, or 15 or 16 bits).
- * Ensure that C2[TE] is asserted atleast 1 clock before assertion of this bit.
- * 10, 11, or 12 logic 0s if S2[BRK13] is cleared 13 or 14 logic 0s if S2[BRK13]
- * is set. 15 or 16 logic 0s if BDH[SBNS] is set. This field must be cleared when
- * C7816[ISO_7816E] is set.
- *
- * Values:
- * - 0 - Normal transmitter operation.
- * - 1 - Queue break characters to be sent.
- */
-//@{
-#define BP_UART_C2_SBK (0U) //!< Bit position for UART_C2_SBK.
-#define BM_UART_C2_SBK (0x01U) //!< Bit mask for UART_C2_SBK.
-#define BS_UART_C2_SBK (1U) //!< Bit field size in bits for UART_C2_SBK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C2_SBK field.
-#define BR_UART_C2_SBK(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_SBK))
-#endif
-
-//! @brief Format value for bitfield UART_C2_SBK.
-#define BF_UART_C2_SBK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_SBK), uint8_t) & BM_UART_C2_SBK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SBK field to a new value.
-#define BW_UART_C2_SBK(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_SBK) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C2, field RWU[1] (RW)
- *
- * This field can be set to place the UART receiver in a standby state. RWU
- * automatically clears when an RWU event occurs, that is, an IDLE event when
- * C1[WAKE] is clear or an address match when C1[WAKE] is set. This field must be
- * cleared when C7816[ISO_7816E] is set. RWU must be set only with C1[WAKE] = 0 (wakeup
- * on idle) if the channel is currently not idle. This can be determined by
- * S2[RAF]. If the flag is set to wake up an IDLE event and the channel is already
- * idle, it is possible that the UART will discard data. This is because the data
- * must be received or a LIN break detected after an IDLE is detected before IDLE
- * is allowed to reasserted.
- *
- * Values:
- * - 0 - Normal operation.
- * - 1 - RWU enables the wakeup function and inhibits further receiver interrupt
- * requests. Normally, hardware wakes the receiver by automatically clearing
- * RWU.
- */
-//@{
-#define BP_UART_C2_RWU (1U) //!< Bit position for UART_C2_RWU.
-#define BM_UART_C2_RWU (0x02U) //!< Bit mask for UART_C2_RWU.
-#define BS_UART_C2_RWU (1U) //!< Bit field size in bits for UART_C2_RWU.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C2_RWU field.
-#define BR_UART_C2_RWU(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RWU))
-#endif
-
-//! @brief Format value for bitfield UART_C2_RWU.
-#define BF_UART_C2_RWU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_RWU), uint8_t) & BM_UART_C2_RWU)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RWU field to a new value.
-#define BW_UART_C2_RWU(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RWU) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C2, field RE[2] (RW)
- *
- * Enables the UART receiver.
- *
- * Values:
- * - 0 - Receiver off.
- * - 1 - Receiver on.
- */
-//@{
-#define BP_UART_C2_RE (2U) //!< Bit position for UART_C2_RE.
-#define BM_UART_C2_RE (0x04U) //!< Bit mask for UART_C2_RE.
-#define BS_UART_C2_RE (1U) //!< Bit field size in bits for UART_C2_RE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C2_RE field.
-#define BR_UART_C2_RE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RE))
-#endif
-
-//! @brief Format value for bitfield UART_C2_RE.
-#define BF_UART_C2_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_RE), uint8_t) & BM_UART_C2_RE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RE field to a new value.
-#define BW_UART_C2_RE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C2, field TE[3] (RW)
- *
- * Enables the UART transmitter. TE can be used to queue an idle preamble by
- * clearing and then setting TE. When C7816[ISO_7816E] is set/enabled and
- * C7816[TTYPE] = 1, this field is automatically cleared after the requested block has been
- * transmitted. This condition is detected when TL7816[TLEN] = 0 and four
- * additional characters are transmitted.
- *
- * Values:
- * - 0 - Transmitter off.
- * - 1 - Transmitter on.
- */
-//@{
-#define BP_UART_C2_TE (3U) //!< Bit position for UART_C2_TE.
-#define BM_UART_C2_TE (0x08U) //!< Bit mask for UART_C2_TE.
-#define BS_UART_C2_TE (1U) //!< Bit field size in bits for UART_C2_TE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C2_TE field.
-#define BR_UART_C2_TE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TE))
-#endif
-
-//! @brief Format value for bitfield UART_C2_TE.
-#define BF_UART_C2_TE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_TE), uint8_t) & BM_UART_C2_TE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TE field to a new value.
-#define BW_UART_C2_TE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C2, field ILIE[4] (RW)
- *
- * Enables the idle line flag, S1[IDLE], to generate interrupt requestsor DMA
- * transfer requests based on the state of C5[ILDMAS].
- *
- * Values:
- * - 0 - IDLE interrupt requests disabled. and DMA transfer
- * - 1 - IDLE interrupt requests enabled. or DMA transfer
- */
-//@{
-#define BP_UART_C2_ILIE (4U) //!< Bit position for UART_C2_ILIE.
-#define BM_UART_C2_ILIE (0x10U) //!< Bit mask for UART_C2_ILIE.
-#define BS_UART_C2_ILIE (1U) //!< Bit field size in bits for UART_C2_ILIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C2_ILIE field.
-#define BR_UART_C2_ILIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_ILIE))
-#endif
-
-//! @brief Format value for bitfield UART_C2_ILIE.
-#define BF_UART_C2_ILIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_ILIE), uint8_t) & BM_UART_C2_ILIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ILIE field to a new value.
-#define BW_UART_C2_ILIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_ILIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C2, field RIE[5] (RW)
- *
- * Enables S1[RDRF] to generate interrupt requests or DMA transfer requests,
- * based on the state of C5[RDMAS].
- *
- * Values:
- * - 0 - RDRF interrupt and DMA transfer requests disabled.
- * - 1 - RDRF interrupt or DMA transfer requests enabled.
- */
-//@{
-#define BP_UART_C2_RIE (5U) //!< Bit position for UART_C2_RIE.
-#define BM_UART_C2_RIE (0x20U) //!< Bit mask for UART_C2_RIE.
-#define BS_UART_C2_RIE (1U) //!< Bit field size in bits for UART_C2_RIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C2_RIE field.
-#define BR_UART_C2_RIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RIE))
-#endif
-
-//! @brief Format value for bitfield UART_C2_RIE.
-#define BF_UART_C2_RIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_RIE), uint8_t) & BM_UART_C2_RIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RIE field to a new value.
-#define BW_UART_C2_RIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C2, field TCIE[6] (RW)
- *
- * Enables the transmission complete flag, S1[TC], to generate interrupt
- * requests . or DMA transfer requests based on the state of C5[TCDMAS] If C2[TCIE] and
- * C5[TCDMAS] are both set, then TIE must be cleared, and D[D] must not be
- * written unless servicing a DMA request.
- *
- * Values:
- * - 0 - TC interrupt and DMA transfer requests disabled.
- * - 1 - TC interrupt or DMA transfer requests enabled.
- */
-//@{
-#define BP_UART_C2_TCIE (6U) //!< Bit position for UART_C2_TCIE.
-#define BM_UART_C2_TCIE (0x40U) //!< Bit mask for UART_C2_TCIE.
-#define BS_UART_C2_TCIE (1U) //!< Bit field size in bits for UART_C2_TCIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C2_TCIE field.
-#define BR_UART_C2_TCIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TCIE))
-#endif
-
-//! @brief Format value for bitfield UART_C2_TCIE.
-#define BF_UART_C2_TCIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_TCIE), uint8_t) & BM_UART_C2_TCIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TCIE field to a new value.
-#define BW_UART_C2_TCIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TCIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C2, field TIE[7] (RW)
- *
- * Enables S1[TDRE] to generate interrupt requests or DMA transfer requests,
- * based on the state of C5[TDMAS]. If C2[TIE] and C5[TDMAS] are both set, then TCIE
- * must be cleared, and D[D] must not be written unless servicing a DMA request.
- *
- * Values:
- * - 0 - TDRE interrupt and DMA transfer requests disabled.
- * - 1 - TDRE interrupt or DMA transfer requests enabled.
- */
-//@{
-#define BP_UART_C2_TIE (7U) //!< Bit position for UART_C2_TIE.
-#define BM_UART_C2_TIE (0x80U) //!< Bit mask for UART_C2_TIE.
-#define BS_UART_C2_TIE (1U) //!< Bit field size in bits for UART_C2_TIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C2_TIE field.
-#define BR_UART_C2_TIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TIE))
-#endif
-
-//! @brief Format value for bitfield UART_C2_TIE.
-#define BF_UART_C2_TIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_TIE), uint8_t) & BM_UART_C2_TIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TIE field to a new value.
-#define BW_UART_C2_TIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TIE) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_S1 - UART Status Register 1
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_S1 - UART Status Register 1 (RO)
- *
- * Reset value: 0xC0U
- *
- * The S1 register provides inputs to the MCU for generation of UART interrupts
- * or DMA requests. This register can also be polled by the MCU to check the
- * status of its fields. To clear a flag, the status register should be read followed
- * by a read or write to D register, depending on the interrupt flag type. Other
- * instructions can be executed between the two steps as long the handling of
- * I/O is not compromised, but the order of operations is important for flag
- * clearing. When a flag is configured to trigger a DMA request, assertion of the
- * associated DMA done signal from the DMA controller clears the flag. If the
- * condition that results in the assertion of the flag, interrupt, or DMA request is not
- * resolved prior to clearing the flag, the flag, and interrupt/DMA request,
- * reasserts. For example, if the DMA or interrupt service routine fails to write
- * sufficient data to the transmit buffer to raise it above the watermark level, the
- * flag reasserts and generates another interrupt or DMA request. Reading an
- * empty data register to clear one of the flags of the S1 register causes the FIFO
- * pointers to become misaligned. A receive FIFO flush reinitializes the
- * pointers. A better way to prevent this situation is to always leave one byte in FIFO
- * and this byte will be read eventually in clearing the flag bit.
- */
-typedef union _hw_uart_s1
-{
- uint8_t U;
- struct _hw_uart_s1_bitfields
- {
- uint8_t PF : 1; //!< [0] Parity Error Flag
- uint8_t FE : 1; //!< [1] Framing Error Flag
- uint8_t NF : 1; //!< [2] Noise Flag
- uint8_t OR : 1; //!< [3] Receiver Overrun Flag
- uint8_t IDLE : 1; //!< [4] Idle Line Flag
- uint8_t RDRF : 1; //!< [5] Receive Data Register Full Flag
- uint8_t TC : 1; //!< [6] Transmit Complete Flag
- uint8_t TDRE : 1; //!< [7] Transmit Data Register Empty Flag
- } B;
-} hw_uart_s1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_S1 register
- */
-//@{
-#define HW_UART_S1_ADDR(x) (REGS_UART_BASE(x) + 0x4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_S1(x) (*(__I hw_uart_s1_t *) HW_UART_S1_ADDR(x))
-#define HW_UART_S1_RD(x) (HW_UART_S1(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_S1 bitfields
- */
-
-/*!
- * @name Register UART_S1, field PF[0] (RO)
- *
- * PF is set when PE is set and the parity of the received data does not match
- * its parity bit. The PF is not set in the case of an overrun condition. When PF
- * is set, it indicates only that a dataword was received with parity error since
- * the last time it was cleared. There is no guarantee that the first dataword
- * read from the receive buffer has a parity error or that there is only one
- * dataword in the buffer that was received with a parity error, unless the receive
- * buffer has a depth of one. To clear PF, read S1 and then read D., S2[LBKDE] is
- * disabled, Within the receive buffer structure the received dataword is tagged
- * if it is received with a parity error. This information is available by reading
- * the ED register prior to reading the D register.
- *
- * Values:
- * - 0 - No parity error detected since the last time this flag was cleared. If
- * the receive buffer has a depth greater than 1, then there may be data in
- * the receive buffer what was received with a parity error.
- * - 1 - At least one dataword was received with a parity error since the last
- * time this flag was cleared.
- */
-//@{
-#define BP_UART_S1_PF (0U) //!< Bit position for UART_S1_PF.
-#define BM_UART_S1_PF (0x01U) //!< Bit mask for UART_S1_PF.
-#define BS_UART_S1_PF (1U) //!< Bit field size in bits for UART_S1_PF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_S1_PF field.
-#define BR_UART_S1_PF(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_PF))
-#endif
-//@}
-
-/*!
- * @name Register UART_S1, field FE[1] (RO)
- *
- * FE is set when a logic 0 is accepted as the stop bit. When BDH[SBNS] is set,
- * then FE will set when a logic 0 is accepted for either of the two stop bits.
- * FE does not set in the case of an overrun or while the LIN break detect feature
- * is enabled (S2[LBKDE] = 1). FE inhibits further data reception until it is
- * cleared. To clear FE, read S1 with FE set and then read D. The last data in the
- * receive buffer represents the data that was received with the frame error
- * enabled. Framing errors are not supported when 7816E is set/enabled. However, if
- * this flag is set, data is still not received in 7816 mode.
- *
- * Values:
- * - 0 - No framing error detected.
- * - 1 - Framing error.
- */
-//@{
-#define BP_UART_S1_FE (1U) //!< Bit position for UART_S1_FE.
-#define BM_UART_S1_FE (0x02U) //!< Bit mask for UART_S1_FE.
-#define BS_UART_S1_FE (1U) //!< Bit field size in bits for UART_S1_FE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_S1_FE field.
-#define BR_UART_S1_FE(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_FE))
-#endif
-//@}
-
-/*!
- * @name Register UART_S1, field NF[2] (RO)
- *
- * NF is set when the UART detects noise on the receiver input. NF does not
- * become set in the case of an overrun or while the LIN break detect feature is
- * enabled (S2[LBKDE] = 1). When NF is set, it indicates only that a dataword has
- * been received with noise since the last time it was cleared. There is no
- * guarantee that the first dataword read from the receive buffer has noise or that there
- * is only one dataword in the buffer that was received with noise unless the
- * receive buffer has a depth of one. To clear NF, read S1 and then read D.
- *
- * Values:
- * - 0 - No noise detected since the last time this flag was cleared. If the
- * receive buffer has a depth greater than 1 then there may be data in the
- * receiver buffer that was received with noise.
- * - 1 - At least one dataword was received with noise detected since the last
- * time the flag was cleared.
- */
-//@{
-#define BP_UART_S1_NF (2U) //!< Bit position for UART_S1_NF.
-#define BM_UART_S1_NF (0x04U) //!< Bit mask for UART_S1_NF.
-#define BS_UART_S1_NF (1U) //!< Bit field size in bits for UART_S1_NF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_S1_NF field.
-#define BR_UART_S1_NF(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_NF))
-#endif
-//@}
-
-/*!
- * @name Register UART_S1, field OR[3] (RO)
- *
- * OR is set when software fails to prevent the receive data register from
- * overflowing with data. The OR bit is set immediately after the stop bit has been
- * completely received for the dataword that overflows the buffer and all the other
- * error flags (FE, NF, and PF) are prevented from setting. The data in the
- * shift register is lost, but the data already in the UART data registers is not
- * affected. If the OR flag is set, no data is stored in the data buffer even if
- * sufficient room exists. Additionally, while the OR flag is set, the RDRF and IDLE
- * flags are blocked from asserting, that is, transition from an inactive to an
- * active state. To clear OR, read S1 when OR is set and then read D. See
- * functional description for more details regarding the operation of the OR bit.If
- * LBKDE is enabled and a LIN Break is detected, the OR field asserts if S2[LBKDIF]
- * is not cleared before the next data character is received. In 7816 mode, it is
- * possible to configure a NACK to be returned by programing C7816[ONACK].
- *
- * Values:
- * - 0 - No overrun has occurred since the last time the flag was cleared.
- * - 1 - Overrun has occurred or the overrun flag has not been cleared since the
- * last overrun occured.
- */
-//@{
-#define BP_UART_S1_OR (3U) //!< Bit position for UART_S1_OR.
-#define BM_UART_S1_OR (0x08U) //!< Bit mask for UART_S1_OR.
-#define BS_UART_S1_OR (1U) //!< Bit field size in bits for UART_S1_OR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_S1_OR field.
-#define BR_UART_S1_OR(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_OR))
-#endif
-//@}
-
-/*!
- * @name Register UART_S1, field IDLE[4] (RO)
- *
- * After the IDLE flag is cleared, a frame must be received (although not
- * necessarily stored in the data buffer, for example if C2[RWU] is set), or a LIN
- * break character must set the S2[LBKDIF] flag before an idle condition can set the
- * IDLE flag. To clear IDLE, read UART status S1 with IDLE set and then read D.
- * IDLE is set when either of the following appear on the receiver input: 10
- * consecutive logic 1s if C1[M] = 0 11 consecutive logic 1s if C1[M] = 1 and C4[M10]
- * = 0 12 consecutive logic 1s if C1[M] = 1, C4[M10] = 1, and C1[PE] = 1 Idle
- * detection is not supported when 7816E is set/enabled and hence this flag is
- * ignored. When RWU is set and WAKE is cleared, an idle line condition sets the IDLE
- * flag if RWUID is set, else the IDLE flag does not become set.
- *
- * Values:
- * - 0 - Receiver input is either active now or has never become active since
- * the IDLE flag was last cleared.
- * - 1 - Receiver input has become idle or the flag has not been cleared since
- * it last asserted.
- */
-//@{
-#define BP_UART_S1_IDLE (4U) //!< Bit position for UART_S1_IDLE.
-#define BM_UART_S1_IDLE (0x10U) //!< Bit mask for UART_S1_IDLE.
-#define BS_UART_S1_IDLE (1U) //!< Bit field size in bits for UART_S1_IDLE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_S1_IDLE field.
-#define BR_UART_S1_IDLE(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_IDLE))
-#endif
-//@}
-
-/*!
- * @name Register UART_S1, field RDRF[5] (RO)
- *
- * RDRF is set when the number of datawords in the receive buffer is equal to or
- * more than the number indicated by RWFIFO[RXWATER]. A dataword that is in the
- * process of being received is not included in the count. To clear RDRF, read S1
- * when RDRF is set and then read D. For more efficient interrupt and DMA
- * operation, read all data except the final value from the buffer, using D/C3[T8]/ED.
- * Then read S1 and the final data value, resulting in the clearing of the RDRF
- * flag. Even if RDRF is set, data will continue to be received until an overrun
- * condition occurs.RDRF is prevented from setting while S2[LBKDE] is set.
- * Additionally, when S2[LBKDE] is set, the received datawords are stored in the receive
- * buffer but over-write each other.
- *
- * Values:
- * - 0 - The number of datawords in the receive buffer is less than the number
- * indicated by RXWATER.
- * - 1 - The number of datawords in the receive buffer is equal to or greater
- * than the number indicated by RXWATER at some point in time since this flag
- * was last cleared.
- */
-//@{
-#define BP_UART_S1_RDRF (5U) //!< Bit position for UART_S1_RDRF.
-#define BM_UART_S1_RDRF (0x20U) //!< Bit mask for UART_S1_RDRF.
-#define BS_UART_S1_RDRF (1U) //!< Bit field size in bits for UART_S1_RDRF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_S1_RDRF field.
-#define BR_UART_S1_RDRF(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_RDRF))
-#endif
-//@}
-
-/*!
- * @name Register UART_S1, field TC[6] (RO)
- *
- * TC is set when the transmit buffer is empty and no data, preamble, or break
- * character is being transmitted. When TC is set, the transmit data output signal
- * becomes idle (logic 1). TC is cleared by reading S1 with TC set and then
- * doing one of the following: When C7816[ISO_7816E] is set/enabled, this field is
- * set after any NACK signal has been received, but prior to any corresponding
- * guard times expiring. Writing to D to transmit new data. Queuing a preamble by
- * clearing and then setting C2[TE]. Queuing a break character by writing 1 to SBK
- * in C2.
- *
- * Values:
- * - 0 - Transmitter active (sending data, a preamble, or a break).
- * - 1 - Transmitter idle (transmission activity complete).
- */
-//@{
-#define BP_UART_S1_TC (6U) //!< Bit position for UART_S1_TC.
-#define BM_UART_S1_TC (0x40U) //!< Bit mask for UART_S1_TC.
-#define BS_UART_S1_TC (1U) //!< Bit field size in bits for UART_S1_TC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_S1_TC field.
-#define BR_UART_S1_TC(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_TC))
-#endif
-//@}
-
-/*!
- * @name Register UART_S1, field TDRE[7] (RO)
- *
- * TDRE will set when the number of datawords in the transmit buffer (D and
- * C3[T8])is equal to or less than the number indicated by TWFIFO[TXWATER]. A
- * character that is in the process of being transmitted is not included in the count.
- * To clear TDRE, read S1 when TDRE is set and then write to the UART data
- * register (D). For more efficient interrupt servicing, all data except the final value
- * to be written to the buffer must be written to D/C3[T8]. Then S1 can be read
- * before writing the final data value, resulting in the clearing of the TRDE
- * flag. This is more efficient because the TDRE reasserts until the watermark has
- * been exceeded. So, attempting to clear the TDRE with every write will be
- * ineffective until sufficient data has been written.
- *
- * Values:
- * - 0 - The amount of data in the transmit buffer is greater than the value
- * indicated by TWFIFO[TXWATER].
- * - 1 - The amount of data in the transmit buffer is less than or equal to the
- * value indicated by TWFIFO[TXWATER] at some point in time since the flag
- * has been cleared.
- */
-//@{
-#define BP_UART_S1_TDRE (7U) //!< Bit position for UART_S1_TDRE.
-#define BM_UART_S1_TDRE (0x80U) //!< Bit mask for UART_S1_TDRE.
-#define BS_UART_S1_TDRE (1U) //!< Bit field size in bits for UART_S1_TDRE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_S1_TDRE field.
-#define BR_UART_S1_TDRE(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_TDRE))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_S2 - UART Status Register 2
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_S2 - UART Status Register 2 (RW)
- *
- * Reset value: 0x00U
- *
- * The S2 register provides inputs to the MCU for generation of UART interrupts
- * or DMA requests. Also, this register can be polled by the MCU to check the
- * status of these bits. This register can be read or written at any time, with the
- * exception of the MSBF and RXINV bits, which should be changed by the user only
- * between transmit and receive packets.
- */
-typedef union _hw_uart_s2
-{
- uint8_t U;
- struct _hw_uart_s2_bitfields
- {
- uint8_t RAF : 1; //!< [0] Receiver Active Flag
- uint8_t LBKDE : 1; //!< [1] LIN Break Detection Enable
- uint8_t BRK13 : 1; //!< [2] Break Transmit Character Length
- uint8_t RWUID : 1; //!< [3] Receive Wakeup Idle Detect
- uint8_t RXINV : 1; //!< [4] Receive Data Inversion
- uint8_t MSBF : 1; //!< [5] Most Significant Bit First
- uint8_t RXEDGIF : 1; //!< [6] RxD Pin Active Edge Interrupt Flag
- uint8_t LBKDIF : 1; //!< [7] LIN Break Detect Interrupt Flag
- } B;
-} hw_uart_s2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_S2 register
- */
-//@{
-#define HW_UART_S2_ADDR(x) (REGS_UART_BASE(x) + 0x5U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_S2(x) (*(__IO hw_uart_s2_t *) HW_UART_S2_ADDR(x))
-#define HW_UART_S2_RD(x) (HW_UART_S2(x).U)
-#define HW_UART_S2_WR(x, v) (HW_UART_S2(x).U = (v))
-#define HW_UART_S2_SET(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) | (v)))
-#define HW_UART_S2_CLR(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) & ~(v)))
-#define HW_UART_S2_TOG(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_S2 bitfields
- */
-
-/*!
- * @name Register UART_S2, field RAF[0] (RO)
- *
- * RAF is set when the UART receiver detects a logic 0 during the RT1 time
- * period of the start bit search. RAF is cleared when the receiver detects an idle
- * character when C7816[ISO7816E] is cleared/disabled. When C7816[ISO7816E] is
- * enabled, the RAF is cleared if the C7816[TTYPE] = 0 expires or the C7816[TTYPE] =
- * 1 expires.In case C7816[ISO7816E] is set and C7816[TTYPE] = 0, it is possible
- * to configure the guard time to 12. However, if a NACK is required to be
- * transmitted, the data transfer actually takes 13 ETU with the 13th ETU slot being a
- * inactive buffer. Therefore, in this situation, the RAF may deassert one ETU
- * prior to actually being inactive.
- *
- * Values:
- * - 0 - UART receiver idle/inactive waiting for a start bit.
- * - 1 - UART receiver active, RxD input not idle.
- */
-//@{
-#define BP_UART_S2_RAF (0U) //!< Bit position for UART_S2_RAF.
-#define BM_UART_S2_RAF (0x01U) //!< Bit mask for UART_S2_RAF.
-#define BS_UART_S2_RAF (1U) //!< Bit field size in bits for UART_S2_RAF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_S2_RAF field.
-#define BR_UART_S2_RAF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RAF))
-#endif
-//@}
-
-/*!
- * @name Register UART_S2, field LBKDE[1] (RW)
- *
- * Enables the LIN Break detection feature. While LBKDE is set, S1[RDRF],
- * S1[NF], S1[FE], and S1[PF] are prevented from setting. When LBKDE is set, see .
- * Overrun operation LBKDE must be cleared when C7816[ISO7816E] is set.
- *
- * Values:
- * - 0 - Break character detection is disabled.
- * - 1 - Break character is detected at length of 11 bit times if C1[M] = 0 or
- * 12 bits time if C1[M] = 1.
- */
-//@{
-#define BP_UART_S2_LBKDE (1U) //!< Bit position for UART_S2_LBKDE.
-#define BM_UART_S2_LBKDE (0x02U) //!< Bit mask for UART_S2_LBKDE.
-#define BS_UART_S2_LBKDE (1U) //!< Bit field size in bits for UART_S2_LBKDE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_S2_LBKDE field.
-#define BR_UART_S2_LBKDE(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDE))
-#endif
-
-//! @brief Format value for bitfield UART_S2_LBKDE.
-#define BF_UART_S2_LBKDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_LBKDE), uint8_t) & BM_UART_S2_LBKDE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LBKDE field to a new value.
-#define BW_UART_S2_LBKDE(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_S2, field BRK13[2] (RW)
- *
- * Determines whether the transmit break character is 10, 11, or 12 bits long,
- * or 13 or 14 bits long. See for the length of the break character for the
- * different configurations. The detection of a framing error is not affected by this
- * field. Transmitting break characters
- *
- * Values:
- * - 0 - Break character is 10, 11, or 12 bits long.
- * - 1 - Break character is 13 or 14 bits long.
- */
-//@{
-#define BP_UART_S2_BRK13 (2U) //!< Bit position for UART_S2_BRK13.
-#define BM_UART_S2_BRK13 (0x04U) //!< Bit mask for UART_S2_BRK13.
-#define BS_UART_S2_BRK13 (1U) //!< Bit field size in bits for UART_S2_BRK13.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_S2_BRK13 field.
-#define BR_UART_S2_BRK13(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_BRK13))
-#endif
-
-//! @brief Format value for bitfield UART_S2_BRK13.
-#define BF_UART_S2_BRK13(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_BRK13), uint8_t) & BM_UART_S2_BRK13)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BRK13 field to a new value.
-#define BW_UART_S2_BRK13(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_BRK13) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_S2, field RWUID[3] (RW)
- *
- * When RWU is set and WAKE is cleared, this field controls whether the idle
- * character that wakes the receiver sets S1[IDLE]. This field must be cleared when
- * C7816[ISO7816E] is set/enabled.
- *
- * Values:
- * - 0 - S1[IDLE] is not set upon detection of an idle character.
- * - 1 - S1[IDLE] is set upon detection of an idle character.
- */
-//@{
-#define BP_UART_S2_RWUID (3U) //!< Bit position for UART_S2_RWUID.
-#define BM_UART_S2_RWUID (0x08U) //!< Bit mask for UART_S2_RWUID.
-#define BS_UART_S2_RWUID (1U) //!< Bit field size in bits for UART_S2_RWUID.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_S2_RWUID field.
-#define BR_UART_S2_RWUID(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RWUID))
-#endif
-
-//! @brief Format value for bitfield UART_S2_RWUID.
-#define BF_UART_S2_RWUID(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_RWUID), uint8_t) & BM_UART_S2_RWUID)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RWUID field to a new value.
-#define BW_UART_S2_RWUID(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RWUID) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_S2, field RXINV[4] (RW)
- *
- * Setting this field reverses the polarity of the received data input. In NRZ
- * format, a one is represented by a mark and a zero is represented by a space for
- * normal polarity, and the opposite for inverted polarity. In IrDA format, a
- * zero is represented by short high pulse in the middle of a bit time remaining
- * idle low for a one for normal polarity. A zero is represented by a short low
- * pulse in the middle of a bit time remaining idle high for a one for inverted
- * polarity. This field is automatically set when C7816[INIT] and C7816[ISO7816E] are
- * enabled and an initial character is detected in T = 0 protocol mode. Setting
- * RXINV inverts the RxD input for data bits, start and stop bits, break, and
- * idle. When C7816[ISO7816E] is set/enabled, only the data bits and the parity bit
- * are inverted.
- *
- * Values:
- * - 0 - Receive data is not inverted.
- * - 1 - Receive data is inverted.
- */
-//@{
-#define BP_UART_S2_RXINV (4U) //!< Bit position for UART_S2_RXINV.
-#define BM_UART_S2_RXINV (0x10U) //!< Bit mask for UART_S2_RXINV.
-#define BS_UART_S2_RXINV (1U) //!< Bit field size in bits for UART_S2_RXINV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_S2_RXINV field.
-#define BR_UART_S2_RXINV(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXINV))
-#endif
-
-//! @brief Format value for bitfield UART_S2_RXINV.
-#define BF_UART_S2_RXINV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_RXINV), uint8_t) & BM_UART_S2_RXINV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RXINV field to a new value.
-#define BW_UART_S2_RXINV(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXINV) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_S2, field MSBF[5] (RW)
- *
- * Setting this field reverses the order of the bits that are transmitted and
- * received on the wire. This field does not affect the polarity of the bits, the
- * location of the parity bit, or the location of the start or stop bits. This
- * field is automatically set when C7816[INIT] and C7816[ISO7816E] are enabled and
- * an initial character is detected in T = 0 protocol mode.
- *
- * Values:
- * - 0 - LSB (bit0) is the first bit that is transmitted following the start
- * bit. Further, the first bit received after the start bit is identified as
- * bit0.
- * - 1 - MSB (bit8, bit7 or bit6) is the first bit that is transmitted following
- * the start bit, depending on the setting of C1[M] and C1[PE]. Further, the
- * first bit received after the start bit is identified as bit8, bit7, or
- * bit6, depending on the setting of C1[M] and C1[PE].
- */
-//@{
-#define BP_UART_S2_MSBF (5U) //!< Bit position for UART_S2_MSBF.
-#define BM_UART_S2_MSBF (0x20U) //!< Bit mask for UART_S2_MSBF.
-#define BS_UART_S2_MSBF (1U) //!< Bit field size in bits for UART_S2_MSBF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_S2_MSBF field.
-#define BR_UART_S2_MSBF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_MSBF))
-#endif
-
-//! @brief Format value for bitfield UART_S2_MSBF.
-#define BF_UART_S2_MSBF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_MSBF), uint8_t) & BM_UART_S2_MSBF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MSBF field to a new value.
-#define BW_UART_S2_MSBF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_MSBF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_S2, field RXEDGIF[6] (W1C)
- *
- * RXEDGIF is set when an active edge occurs on the RxD pin. The active edge is
- * falling if RXINV = 0, and rising if RXINV=1. RXEDGIF is cleared by writing a 1
- * to it. See for additional details. RXEDGIF description The active edge is
- * detected only in two wire mode and on receiving data coming from the RxD pin.
- *
- * Values:
- * - 0 - No active edge on the receive pin has occurred.
- * - 1 - An active edge on the receive pin has occurred.
- */
-//@{
-#define BP_UART_S2_RXEDGIF (6U) //!< Bit position for UART_S2_RXEDGIF.
-#define BM_UART_S2_RXEDGIF (0x40U) //!< Bit mask for UART_S2_RXEDGIF.
-#define BS_UART_S2_RXEDGIF (1U) //!< Bit field size in bits for UART_S2_RXEDGIF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_S2_RXEDGIF field.
-#define BR_UART_S2_RXEDGIF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXEDGIF))
-#endif
-
-//! @brief Format value for bitfield UART_S2_RXEDGIF.
-#define BF_UART_S2_RXEDGIF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_RXEDGIF), uint8_t) & BM_UART_S2_RXEDGIF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RXEDGIF field to a new value.
-#define BW_UART_S2_RXEDGIF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXEDGIF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_S2, field LBKDIF[7] (W1C)
- *
- * LBKDIF is set when LBKDE is set and a LIN break character is detected on the
- * receiver input. The LIN break characters are 11 consecutive logic 0s if C1[M]
- * = 0 or 12 consecutive logic 0s if C1[M] = 1. LBKDIF is set after receiving the
- * last LIN break character. LBKDIF is cleared by writing a 1 to it.
- *
- * Values:
- * - 0 - No LIN break character detected.
- * - 1 - LIN break character detected.
- */
-//@{
-#define BP_UART_S2_LBKDIF (7U) //!< Bit position for UART_S2_LBKDIF.
-#define BM_UART_S2_LBKDIF (0x80U) //!< Bit mask for UART_S2_LBKDIF.
-#define BS_UART_S2_LBKDIF (1U) //!< Bit field size in bits for UART_S2_LBKDIF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_S2_LBKDIF field.
-#define BR_UART_S2_LBKDIF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDIF))
-#endif
-
-//! @brief Format value for bitfield UART_S2_LBKDIF.
-#define BF_UART_S2_LBKDIF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_LBKDIF), uint8_t) & BM_UART_S2_LBKDIF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LBKDIF field to a new value.
-#define BW_UART_S2_LBKDIF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDIF) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_C3 - UART Control Register 3
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_C3 - UART Control Register 3 (RW)
- *
- * Reset value: 0x00U
- *
- * Writing R8 does not have any effect. TXDIR and TXINV can be changed only
- * between transmit and receive packets.
- */
-typedef union _hw_uart_c3
-{
- uint8_t U;
- struct _hw_uart_c3_bitfields
- {
- uint8_t PEIE : 1; //!< [0] Parity Error Interrupt Enable
- uint8_t FEIE : 1; //!< [1] Framing Error Interrupt Enable
- uint8_t NEIE : 1; //!< [2] Noise Error Interrupt Enable
- uint8_t ORIE : 1; //!< [3] Overrun Error Interrupt Enable
- uint8_t TXINV : 1; //!< [4] Transmit Data Inversion.
- uint8_t TXDIR : 1; //!< [5] Transmitter Pin Data Direction in
- //! Single-Wire mode
- uint8_t T8 : 1; //!< [6] Transmit Bit 8
- uint8_t R8 : 1; //!< [7] Received Bit 8
- } B;
-} hw_uart_c3_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_C3 register
- */
-//@{
-#define HW_UART_C3_ADDR(x) (REGS_UART_BASE(x) + 0x6U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_C3(x) (*(__IO hw_uart_c3_t *) HW_UART_C3_ADDR(x))
-#define HW_UART_C3_RD(x) (HW_UART_C3(x).U)
-#define HW_UART_C3_WR(x, v) (HW_UART_C3(x).U = (v))
-#define HW_UART_C3_SET(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) | (v)))
-#define HW_UART_C3_CLR(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) & ~(v)))
-#define HW_UART_C3_TOG(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_C3 bitfields
- */
-
-/*!
- * @name Register UART_C3, field PEIE[0] (RW)
- *
- * Enables the parity error flag, S1[PF], to generate interrupt requests.
- *
- * Values:
- * - 0 - PF interrupt requests are disabled.
- * - 1 - PF interrupt requests are enabled.
- */
-//@{
-#define BP_UART_C3_PEIE (0U) //!< Bit position for UART_C3_PEIE.
-#define BM_UART_C3_PEIE (0x01U) //!< Bit mask for UART_C3_PEIE.
-#define BS_UART_C3_PEIE (1U) //!< Bit field size in bits for UART_C3_PEIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C3_PEIE field.
-#define BR_UART_C3_PEIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_PEIE))
-#endif
-
-//! @brief Format value for bitfield UART_C3_PEIE.
-#define BF_UART_C3_PEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_PEIE), uint8_t) & BM_UART_C3_PEIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PEIE field to a new value.
-#define BW_UART_C3_PEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_PEIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C3, field FEIE[1] (RW)
- *
- * Enables the framing error flag, S1[FE], to generate interrupt requests.
- *
- * Values:
- * - 0 - FE interrupt requests are disabled.
- * - 1 - FE interrupt requests are enabled.
- */
-//@{
-#define BP_UART_C3_FEIE (1U) //!< Bit position for UART_C3_FEIE.
-#define BM_UART_C3_FEIE (0x02U) //!< Bit mask for UART_C3_FEIE.
-#define BS_UART_C3_FEIE (1U) //!< Bit field size in bits for UART_C3_FEIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C3_FEIE field.
-#define BR_UART_C3_FEIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_FEIE))
-#endif
-
-//! @brief Format value for bitfield UART_C3_FEIE.
-#define BF_UART_C3_FEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_FEIE), uint8_t) & BM_UART_C3_FEIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FEIE field to a new value.
-#define BW_UART_C3_FEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_FEIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C3, field NEIE[2] (RW)
- *
- * Enables the noise flag, S1[NF], to generate interrupt requests.
- *
- * Values:
- * - 0 - NF interrupt requests are disabled.
- * - 1 - NF interrupt requests are enabled.
- */
-//@{
-#define BP_UART_C3_NEIE (2U) //!< Bit position for UART_C3_NEIE.
-#define BM_UART_C3_NEIE (0x04U) //!< Bit mask for UART_C3_NEIE.
-#define BS_UART_C3_NEIE (1U) //!< Bit field size in bits for UART_C3_NEIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C3_NEIE field.
-#define BR_UART_C3_NEIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_NEIE))
-#endif
-
-//! @brief Format value for bitfield UART_C3_NEIE.
-#define BF_UART_C3_NEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_NEIE), uint8_t) & BM_UART_C3_NEIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the NEIE field to a new value.
-#define BW_UART_C3_NEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_NEIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C3, field ORIE[3] (RW)
- *
- * Enables the overrun error flag, S1[OR], to generate interrupt requests.
- *
- * Values:
- * - 0 - OR interrupts are disabled.
- * - 1 - OR interrupt requests are enabled.
- */
-//@{
-#define BP_UART_C3_ORIE (3U) //!< Bit position for UART_C3_ORIE.
-#define BM_UART_C3_ORIE (0x08U) //!< Bit mask for UART_C3_ORIE.
-#define BS_UART_C3_ORIE (1U) //!< Bit field size in bits for UART_C3_ORIE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C3_ORIE field.
-#define BR_UART_C3_ORIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_ORIE))
-#endif
-
-//! @brief Format value for bitfield UART_C3_ORIE.
-#define BF_UART_C3_ORIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_ORIE), uint8_t) & BM_UART_C3_ORIE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ORIE field to a new value.
-#define BW_UART_C3_ORIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_ORIE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C3, field TXINV[4] (RW)
- *
- * Setting this field reverses the polarity of the transmitted data output. In
- * NRZ format, a one is represented by a mark and a zero is represented by a space
- * for normal polarity, and the opposite for inverted polarity. In IrDA format,
- * a zero is represented by short high pulse in the middle of a bit time
- * remaining idle low for a one for normal polarity, and a zero is represented by short
- * low pulse in the middle of a bit time remaining idle high for a one for
- * inverted polarity. This field is automatically set when C7816[INIT] and
- * C7816[ISO7816E] are enabled and an initial character is detected in T = 0 protocol mode.
- * Setting TXINV inverts all transmitted values, including idle, break, start, and
- * stop bits. In loop mode, if TXINV is set, the receiver gets the transmit
- * inversion bit when RXINV is disabled. When C7816[ISO7816E] is set/enabled then only
- * the transmitted data bits and parity bit are inverted.
- *
- * Values:
- * - 0 - Transmit data is not inverted.
- * - 1 - Transmit data is inverted.
- */
-//@{
-#define BP_UART_C3_TXINV (4U) //!< Bit position for UART_C3_TXINV.
-#define BM_UART_C3_TXINV (0x10U) //!< Bit mask for UART_C3_TXINV.
-#define BS_UART_C3_TXINV (1U) //!< Bit field size in bits for UART_C3_TXINV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C3_TXINV field.
-#define BR_UART_C3_TXINV(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXINV))
-#endif
-
-//! @brief Format value for bitfield UART_C3_TXINV.
-#define BF_UART_C3_TXINV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_TXINV), uint8_t) & BM_UART_C3_TXINV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TXINV field to a new value.
-#define BW_UART_C3_TXINV(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXINV) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C3, field TXDIR[5] (RW)
- *
- * Determines whether the TXD pin is used as an input or output in the
- * single-wire mode of operation. This field is relevant only to the single wire mode.
- * When C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 1, this field is
- * automatically cleared after the requested block is transmitted. This condition is
- * detected when TL7816[TLEN] = 0 and 4 additional characters are transmitted.
- * Additionally, if C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 0 and a NACK is
- * being transmitted, the hardware automatically overrides this field as needed. In
- * this situation, TXDIR does not reflect the temporary state associated with
- * the NACK.
- *
- * Values:
- * - 0 - TXD pin is an input in single wire mode.
- * - 1 - TXD pin is an output in single wire mode.
- */
-//@{
-#define BP_UART_C3_TXDIR (5U) //!< Bit position for UART_C3_TXDIR.
-#define BM_UART_C3_TXDIR (0x20U) //!< Bit mask for UART_C3_TXDIR.
-#define BS_UART_C3_TXDIR (1U) //!< Bit field size in bits for UART_C3_TXDIR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C3_TXDIR field.
-#define BR_UART_C3_TXDIR(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXDIR))
-#endif
-
-//! @brief Format value for bitfield UART_C3_TXDIR.
-#define BF_UART_C3_TXDIR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_TXDIR), uint8_t) & BM_UART_C3_TXDIR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TXDIR field to a new value.
-#define BW_UART_C3_TXDIR(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXDIR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C3, field T8[6] (RW)
- *
- * T8 is the ninth data bit transmitted when the UART is configured for 9-bit
- * data format, that is, if C1[M] = 1 or C4[M10] = 1. If the value of T8 is the
- * same as in the previous transmission, T8 does not have to be rewritten. The same
- * value is transmitted until T8 is rewritten. To correctly transmit the 9th bit,
- * write UARTx_C3[T8] to the desired value, then write the UARTx_D register with
- * the remaining data.
- */
-//@{
-#define BP_UART_C3_T8 (6U) //!< Bit position for UART_C3_T8.
-#define BM_UART_C3_T8 (0x40U) //!< Bit mask for UART_C3_T8.
-#define BS_UART_C3_T8 (1U) //!< Bit field size in bits for UART_C3_T8.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C3_T8 field.
-#define BR_UART_C3_T8(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_T8))
-#endif
-
-//! @brief Format value for bitfield UART_C3_T8.
-#define BF_UART_C3_T8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_T8), uint8_t) & BM_UART_C3_T8)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the T8 field to a new value.
-#define BW_UART_C3_T8(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_T8) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C3, field R8[7] (RO)
- *
- * R8 is the ninth data bit received when the UART is configured for 9-bit data
- * format, that is, if C1[M] = 1 or C4[M10] = 1. The R8 value corresponds to the
- * current data value in the UARTx_D register. To read the 9th bit, read the
- * value of UARTx_C3[R8], then read the UARTx_D register.
- */
-//@{
-#define BP_UART_C3_R8 (7U) //!< Bit position for UART_C3_R8.
-#define BM_UART_C3_R8 (0x80U) //!< Bit mask for UART_C3_R8.
-#define BS_UART_C3_R8 (1U) //!< Bit field size in bits for UART_C3_R8.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C3_R8 field.
-#define BR_UART_C3_R8(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_R8))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_D - UART Data Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_D - UART Data Register (RW)
- *
- * Reset value: 0x00U
- *
- * This register is actually two separate registers. Reads return the contents
- * of the read-only receive data register and writes go to the write-only transmit
- * data register. In 8-bit or 9-bit data format, only UART data register (D)
- * needs to be accessed to clear the S1[RDRF] bit (assuming receiver buffer level is
- * less than RWFIFO[RXWATER]). The C3 register needs to be read, prior to the D
- * register, only if the ninth bit of data needs to be captured. Similarly, the
- * ED register needs to be read, prior to the D register, only if the additional
- * flag data for the dataword needs to be captured. In the normal 8-bit mode (M
- * bit cleared) if the parity is enabled, you get seven data bits and one parity
- * bit. That one parity bit is loaded into the D register. So, for the data bits,
- * mask off the parity bit from the value you read out of this register. When
- * transmitting in 9-bit data format and using 8-bit write instructions, write first
- * to transmit bit 8 in UART control register 3 (C3[T8]), then D. A write to
- * C3[T8] stores the data in a temporary register. If D register is written first,
- * and then the new data on data bus is stored in D, the temporary value written by
- * the last write to C3[T8] gets stored in the C3[T8] register.
- */
-typedef union _hw_uart_d
-{
- uint8_t U;
- struct _hw_uart_d_bitfields
- {
- uint8_t RT : 8; //!< [7:0]
- } B;
-} hw_uart_d_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_D register
- */
-//@{
-#define HW_UART_D_ADDR(x) (REGS_UART_BASE(x) + 0x7U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_D(x) (*(__IO hw_uart_d_t *) HW_UART_D_ADDR(x))
-#define HW_UART_D_RD(x) (HW_UART_D(x).U)
-#define HW_UART_D_WR(x, v) (HW_UART_D(x).U = (v))
-#define HW_UART_D_SET(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) | (v)))
-#define HW_UART_D_CLR(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) & ~(v)))
-#define HW_UART_D_TOG(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_D bitfields
- */
-
-/*!
- * @name Register UART_D, field RT[7:0] (RW)
- *
- * Reads return the contents of the read-only receive data register and writes
- * go to the write-only transmit data register.
- */
-//@{
-#define BP_UART_D_RT (0U) //!< Bit position for UART_D_RT.
-#define BM_UART_D_RT (0xFFU) //!< Bit mask for UART_D_RT.
-#define BS_UART_D_RT (8U) //!< Bit field size in bits for UART_D_RT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_D_RT field.
-#define BR_UART_D_RT(x) (HW_UART_D(x).U)
-#endif
-
-//! @brief Format value for bitfield UART_D_RT.
-#define BF_UART_D_RT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_D_RT), uint8_t) & BM_UART_D_RT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RT field to a new value.
-#define BW_UART_D_RT(x, v) (HW_UART_D_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_MA1 - UART Match Address Registers 1
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_MA1 - UART Match Address Registers 1 (RW)
- *
- * Reset value: 0x00U
- *
- * The MA1 and MA2 registers are compared to input data addresses when the most
- * significant bit is set and the associated C4[MAEN] field is set. If a match
- * occurs, the following data is transferred to the data register. If a match
- * fails, the following data is discarded. These registers can be read and written at
- * anytime.
- */
-typedef union _hw_uart_ma1
-{
- uint8_t U;
- struct _hw_uart_ma1_bitfields
- {
- uint8_t MA : 8; //!< [7:0] Match Address
- } B;
-} hw_uart_ma1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_MA1 register
- */
-//@{
-#define HW_UART_MA1_ADDR(x) (REGS_UART_BASE(x) + 0x8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_MA1(x) (*(__IO hw_uart_ma1_t *) HW_UART_MA1_ADDR(x))
-#define HW_UART_MA1_RD(x) (HW_UART_MA1(x).U)
-#define HW_UART_MA1_WR(x, v) (HW_UART_MA1(x).U = (v))
-#define HW_UART_MA1_SET(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) | (v)))
-#define HW_UART_MA1_CLR(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) & ~(v)))
-#define HW_UART_MA1_TOG(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_MA1 bitfields
- */
-
-/*!
- * @name Register UART_MA1, field MA[7:0] (RW)
- */
-//@{
-#define BP_UART_MA1_MA (0U) //!< Bit position for UART_MA1_MA.
-#define BM_UART_MA1_MA (0xFFU) //!< Bit mask for UART_MA1_MA.
-#define BS_UART_MA1_MA (8U) //!< Bit field size in bits for UART_MA1_MA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_MA1_MA field.
-#define BR_UART_MA1_MA(x) (HW_UART_MA1(x).U)
-#endif
-
-//! @brief Format value for bitfield UART_MA1_MA.
-#define BF_UART_MA1_MA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MA1_MA), uint8_t) & BM_UART_MA1_MA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MA field to a new value.
-#define BW_UART_MA1_MA(x, v) (HW_UART_MA1_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_MA2 - UART Match Address Registers 2
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_MA2 - UART Match Address Registers 2 (RW)
- *
- * Reset value: 0x00U
- *
- * These registers can be read and written at anytime. The MA1 and MA2 registers
- * are compared to input data addresses when the most significant bit is set and
- * the associated C4[MAEN] field is set. If a match occurs, the following data
- * is transferred to the data register. If a match fails, the following data is
- * discarded.
- */
-typedef union _hw_uart_ma2
-{
- uint8_t U;
- struct _hw_uart_ma2_bitfields
- {
- uint8_t MA : 8; //!< [7:0] Match Address
- } B;
-} hw_uart_ma2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_MA2 register
- */
-//@{
-#define HW_UART_MA2_ADDR(x) (REGS_UART_BASE(x) + 0x9U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_MA2(x) (*(__IO hw_uart_ma2_t *) HW_UART_MA2_ADDR(x))
-#define HW_UART_MA2_RD(x) (HW_UART_MA2(x).U)
-#define HW_UART_MA2_WR(x, v) (HW_UART_MA2(x).U = (v))
-#define HW_UART_MA2_SET(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) | (v)))
-#define HW_UART_MA2_CLR(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) & ~(v)))
-#define HW_UART_MA2_TOG(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_MA2 bitfields
- */
-
-/*!
- * @name Register UART_MA2, field MA[7:0] (RW)
- */
-//@{
-#define BP_UART_MA2_MA (0U) //!< Bit position for UART_MA2_MA.
-#define BM_UART_MA2_MA (0xFFU) //!< Bit mask for UART_MA2_MA.
-#define BS_UART_MA2_MA (8U) //!< Bit field size in bits for UART_MA2_MA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_MA2_MA field.
-#define BR_UART_MA2_MA(x) (HW_UART_MA2(x).U)
-#endif
-
-//! @brief Format value for bitfield UART_MA2_MA.
-#define BF_UART_MA2_MA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MA2_MA), uint8_t) & BM_UART_MA2_MA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MA field to a new value.
-#define BW_UART_MA2_MA(x, v) (HW_UART_MA2_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_C4 - UART Control Register 4
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_C4 - UART Control Register 4 (RW)
- *
- * Reset value: 0x00U
- */
-typedef union _hw_uart_c4
-{
- uint8_t U;
- struct _hw_uart_c4_bitfields
- {
- uint8_t BRFA : 5; //!< [4:0] Baud Rate Fine Adjust
- uint8_t M10 : 1; //!< [5] 10-bit Mode select
- uint8_t MAEN2 : 1; //!< [6] Match Address Mode Enable 2
- uint8_t MAEN1 : 1; //!< [7] Match Address Mode Enable 1
- } B;
-} hw_uart_c4_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_C4 register
- */
-//@{
-#define HW_UART_C4_ADDR(x) (REGS_UART_BASE(x) + 0xAU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_C4(x) (*(__IO hw_uart_c4_t *) HW_UART_C4_ADDR(x))
-#define HW_UART_C4_RD(x) (HW_UART_C4(x).U)
-#define HW_UART_C4_WR(x, v) (HW_UART_C4(x).U = (v))
-#define HW_UART_C4_SET(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) | (v)))
-#define HW_UART_C4_CLR(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) & ~(v)))
-#define HW_UART_C4_TOG(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_C4 bitfields
- */
-
-/*!
- * @name Register UART_C4, field BRFA[4:0] (RW)
- *
- * This bit field is used to add more timing resolution to the average baud
- * frequency, in increments of 1/32. See Baud rate generation for more information.
- */
-//@{
-#define BP_UART_C4_BRFA (0U) //!< Bit position for UART_C4_BRFA.
-#define BM_UART_C4_BRFA (0x1FU) //!< Bit mask for UART_C4_BRFA.
-#define BS_UART_C4_BRFA (5U) //!< Bit field size in bits for UART_C4_BRFA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C4_BRFA field.
-#define BR_UART_C4_BRFA(x) (HW_UART_C4(x).B.BRFA)
-#endif
-
-//! @brief Format value for bitfield UART_C4_BRFA.
-#define BF_UART_C4_BRFA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C4_BRFA), uint8_t) & BM_UART_C4_BRFA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BRFA field to a new value.
-#define BW_UART_C4_BRFA(x, v) (HW_UART_C4_WR(x, (HW_UART_C4_RD(x) & ~BM_UART_C4_BRFA) | BF_UART_C4_BRFA(v)))
-#endif
-//@}
-
-/*!
- * @name Register UART_C4, field M10[5] (RW)
- *
- * Causes a tenth, non-memory mapped bit to be part of the serial transmission.
- * This tenth bit is generated and interpreted as a parity bit. The M10 field
- * does not affect the LIN send or detect break behavior. If M10 is set, then both
- * C1[M] and C1[PE] must also be set. This field must be cleared when
- * C7816[ISO7816E] is set/enabled. See Data format (non ISO-7816) for more information.
- *
- * Values:
- * - 0 - The parity bit is the ninth bit in the serial transmission.
- * - 1 - The parity bit is the tenth bit in the serial transmission.
- */
-//@{
-#define BP_UART_C4_M10 (5U) //!< Bit position for UART_C4_M10.
-#define BM_UART_C4_M10 (0x20U) //!< Bit mask for UART_C4_M10.
-#define BS_UART_C4_M10 (1U) //!< Bit field size in bits for UART_C4_M10.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C4_M10 field.
-#define BR_UART_C4_M10(x) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_M10))
-#endif
-
-//! @brief Format value for bitfield UART_C4_M10.
-#define BF_UART_C4_M10(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C4_M10), uint8_t) & BM_UART_C4_M10)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the M10 field to a new value.
-#define BW_UART_C4_M10(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_M10) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C4, field MAEN2[6] (RW)
- *
- * See Match address operation for more information.
- *
- * Values:
- * - 0 - All data received is transferred to the data buffer if MAEN1 is cleared.
- * - 1 - All data received with the most significant bit cleared, is discarded.
- * All data received with the most significant bit set, is compared with
- * contents of MA2 register. If no match occurs, the data is discarded. If a
- * match occurs, data is transferred to the data buffer. This field must be
- * cleared when C7816[ISO7816E] is set/enabled.
- */
-//@{
-#define BP_UART_C4_MAEN2 (6U) //!< Bit position for UART_C4_MAEN2.
-#define BM_UART_C4_MAEN2 (0x40U) //!< Bit mask for UART_C4_MAEN2.
-#define BS_UART_C4_MAEN2 (1U) //!< Bit field size in bits for UART_C4_MAEN2.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C4_MAEN2 field.
-#define BR_UART_C4_MAEN2(x) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN2))
-#endif
-
-//! @brief Format value for bitfield UART_C4_MAEN2.
-#define BF_UART_C4_MAEN2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C4_MAEN2), uint8_t) & BM_UART_C4_MAEN2)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MAEN2 field to a new value.
-#define BW_UART_C4_MAEN2(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN2) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C4, field MAEN1[7] (RW)
- *
- * See Match address operation for more information.
- *
- * Values:
- * - 0 - All data received is transferred to the data buffer if MAEN2 is cleared.
- * - 1 - All data received with the most significant bit cleared, is discarded.
- * All data received with the most significant bit set, is compared with
- * contents of MA1 register. If no match occurs, the data is discarded. If match
- * occurs, data is transferred to the data buffer. This field must be cleared
- * when C7816[ISO7816E] is set/enabled.
- */
-//@{
-#define BP_UART_C4_MAEN1 (7U) //!< Bit position for UART_C4_MAEN1.
-#define BM_UART_C4_MAEN1 (0x80U) //!< Bit mask for UART_C4_MAEN1.
-#define BS_UART_C4_MAEN1 (1U) //!< Bit field size in bits for UART_C4_MAEN1.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C4_MAEN1 field.
-#define BR_UART_C4_MAEN1(x) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN1))
-#endif
-
-//! @brief Format value for bitfield UART_C4_MAEN1.
-#define BF_UART_C4_MAEN1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C4_MAEN1), uint8_t) & BM_UART_C4_MAEN1)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MAEN1 field to a new value.
-#define BW_UART_C4_MAEN1(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN1) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_C5 - UART Control Register 5
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_C5 - UART Control Register 5 (RW)
- *
- * Reset value: 0x00U
- */
-typedef union _hw_uart_c5
-{
- uint8_t U;
- struct _hw_uart_c5_bitfields
- {
- uint8_t RESERVED0 : 3; //!< [2:0]
- uint8_t LBKDDMAS : 1; //!< [3] LIN Break Detect DMA Select Bit
- uint8_t ILDMAS : 1; //!< [4] Idle Line DMA Select
- uint8_t RDMAS : 1; //!< [5] Receiver Full DMA Select
- uint8_t TCDMAS : 1; //!< [6] Transmission Complete DMA Select
- uint8_t TDMAS : 1; //!< [7] Transmitter DMA Select
- } B;
-} hw_uart_c5_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_C5 register
- */
-//@{
-#define HW_UART_C5_ADDR(x) (REGS_UART_BASE(x) + 0xBU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_C5(x) (*(__IO hw_uart_c5_t *) HW_UART_C5_ADDR(x))
-#define HW_UART_C5_RD(x) (HW_UART_C5(x).U)
-#define HW_UART_C5_WR(x, v) (HW_UART_C5(x).U = (v))
-#define HW_UART_C5_SET(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) | (v)))
-#define HW_UART_C5_CLR(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) & ~(v)))
-#define HW_UART_C5_TOG(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_C5 bitfields
- */
-
-/*!
- * @name Register UART_C5, field LBKDDMAS[3] (RW)
- *
- * Configures the LIN break detect flag, S2[LBKDIF], to generate interrupt or
- * DMA requests if BDH[LBKDIE] is set. If BDH[LBKDIE] is cleared, and S2[LBKDIF] is
- * set, the LBKDIF DMA and LBKDIF interrupt signals are not asserted, regardless
- * of the state of LBKDDMAS.
- *
- * Values:
- * - 0 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is
- * asserted to request an interrupt service.
- * - 1 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is
- * asserted to request a DMA transfer.
- */
-//@{
-#define BP_UART_C5_LBKDDMAS (3U) //!< Bit position for UART_C5_LBKDDMAS.
-#define BM_UART_C5_LBKDDMAS (0x08U) //!< Bit mask for UART_C5_LBKDDMAS.
-#define BS_UART_C5_LBKDDMAS (1U) //!< Bit field size in bits for UART_C5_LBKDDMAS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C5_LBKDDMAS field.
-#define BR_UART_C5_LBKDDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_LBKDDMAS))
-#endif
-
-//! @brief Format value for bitfield UART_C5_LBKDDMAS.
-#define BF_UART_C5_LBKDDMAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C5_LBKDDMAS), uint8_t) & BM_UART_C5_LBKDDMAS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LBKDDMAS field to a new value.
-#define BW_UART_C5_LBKDDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_LBKDDMAS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C5, field ILDMAS[4] (RW)
- *
- * Configures the idle line flag, S1[IDLE], to generate interrupt or DMA
- * requests if C2[ILIE] is set. If C2[ILIE] is cleared, and S1[IDLE] is set, the IDLE
- * DMA and IDLE interrupt request signals are not asserted, regardless of the state
- * of ILDMAS.
- *
- * Values:
- * - 0 - If C2[ILIE] and S1[IDLE] are set, the IDLE interrupt request signal is
- * asserted to request an interrupt service.
- * - 1 - If C2[ILIE] and S1[IDLE] are set, the IDLE DMA request signal is
- * asserted to request a DMA transfer.
- */
-//@{
-#define BP_UART_C5_ILDMAS (4U) //!< Bit position for UART_C5_ILDMAS.
-#define BM_UART_C5_ILDMAS (0x10U) //!< Bit mask for UART_C5_ILDMAS.
-#define BS_UART_C5_ILDMAS (1U) //!< Bit field size in bits for UART_C5_ILDMAS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C5_ILDMAS field.
-#define BR_UART_C5_ILDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_ILDMAS))
-#endif
-
-//! @brief Format value for bitfield UART_C5_ILDMAS.
-#define BF_UART_C5_ILDMAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C5_ILDMAS), uint8_t) & BM_UART_C5_ILDMAS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ILDMAS field to a new value.
-#define BW_UART_C5_ILDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_ILDMAS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C5, field RDMAS[5] (RW)
- *
- * Configures the receiver data register full flag, S1[RDRF], to generate
- * interrupt or DMA requests if C2[RIE] is set. If C2[RIE] is cleared, and S1[RDRF] is
- * set, the RDRF DMA and RDFR interrupt request signals are not asserted,
- * regardless of the state of RDMAS.
- *
- * Values:
- * - 0 - If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is
- * asserted to request an interrupt service.
- * - 1 - If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is
- * asserted to request a DMA transfer.
- */
-//@{
-#define BP_UART_C5_RDMAS (5U) //!< Bit position for UART_C5_RDMAS.
-#define BM_UART_C5_RDMAS (0x20U) //!< Bit mask for UART_C5_RDMAS.
-#define BS_UART_C5_RDMAS (1U) //!< Bit field size in bits for UART_C5_RDMAS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C5_RDMAS field.
-#define BR_UART_C5_RDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_RDMAS))
-#endif
-
-//! @brief Format value for bitfield UART_C5_RDMAS.
-#define BF_UART_C5_RDMAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C5_RDMAS), uint8_t) & BM_UART_C5_RDMAS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RDMAS field to a new value.
-#define BW_UART_C5_RDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_RDMAS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C5, field TCDMAS[6] (RW)
- *
- * Configures the transmission complete flag, S1[TC], to generate interrupt or
- * DMA requests if C2[TCIE] is set. If C2[TCIE] is cleared, the TC DMA and TC
- * interrupt request signals are not asserted when the S1[TC] flag is set, regardless
- * of the state of TCDMAS. If C2[TCIE] and TCDMAS are both set, then C2[TIE]
- * must be cleared, and D must not be written unless a DMA request is being serviced.
- *
- * Values:
- * - 0 - If C2[TCIE] is set and the S1[TC] flag is set, the TC interrupt request
- * signal is asserted to request an interrupt service.
- * - 1 - If C2[TCIE] is set and the S1[TC] flag is set, the TC DMA request
- * signal is asserted to request a DMA transfer.
- */
-//@{
-#define BP_UART_C5_TCDMAS (6U) //!< Bit position for UART_C5_TCDMAS.
-#define BM_UART_C5_TCDMAS (0x40U) //!< Bit mask for UART_C5_TCDMAS.
-#define BS_UART_C5_TCDMAS (1U) //!< Bit field size in bits for UART_C5_TCDMAS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C5_TCDMAS field.
-#define BR_UART_C5_TCDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TCDMAS))
-#endif
-
-//! @brief Format value for bitfield UART_C5_TCDMAS.
-#define BF_UART_C5_TCDMAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C5_TCDMAS), uint8_t) & BM_UART_C5_TCDMAS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TCDMAS field to a new value.
-#define BW_UART_C5_TCDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TCDMAS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C5, field TDMAS[7] (RW)
- *
- * Configures the transmit data register empty flag, S1[TDRE], to generate
- * interrupt or DMA requests if C2[TIE] is set. If C2[TIE] is cleared, TDRE DMA and
- * TDRE interrupt request signals are not asserted when the TDRE flag is set,
- * regardless of the state of TDMAS. If C2[TIE] and TDMAS are both set, then C2[TCIE]
- * must be cleared, and D must not be written unless a DMA request is being
- * serviced.
- *
- * Values:
- * - 0 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt
- * request signal is asserted to request interrupt service.
- * - 1 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request
- * signal is asserted to request a DMA transfer.
- */
-//@{
-#define BP_UART_C5_TDMAS (7U) //!< Bit position for UART_C5_TDMAS.
-#define BM_UART_C5_TDMAS (0x80U) //!< Bit mask for UART_C5_TDMAS.
-#define BS_UART_C5_TDMAS (1U) //!< Bit field size in bits for UART_C5_TDMAS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C5_TDMAS field.
-#define BR_UART_C5_TDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TDMAS))
-#endif
-
-//! @brief Format value for bitfield UART_C5_TDMAS.
-#define BF_UART_C5_TDMAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C5_TDMAS), uint8_t) & BM_UART_C5_TDMAS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TDMAS field to a new value.
-#define BW_UART_C5_TDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TDMAS) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_ED - UART Extended Data Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_ED - UART Extended Data Register (RO)
- *
- * Reset value: 0x00U
- *
- * This register contains additional information flags that are stored with a
- * received dataword. This register may be read at any time but contains valid data
- * only if there is a dataword in the receive FIFO. The data contained in this
- * register represents additional information regarding the conditions on which a
- * dataword was received. The importance of this data varies with the
- * application, and in some cases maybe completely optional. These fields automatically
- * update to reflect the conditions of the next dataword whenever D is read. If
- * S1[NF] and S1[PF] have not been set since the last time the receive buffer was
- * empty, the NOISY and PARITYE fields will be zero.
- */
-typedef union _hw_uart_ed
-{
- uint8_t U;
- struct _hw_uart_ed_bitfields
- {
- uint8_t RESERVED0 : 6; //!< [5:0]
- uint8_t PARITYE : 1; //!< [6]
- uint8_t NOISY : 1; //!< [7]
- } B;
-} hw_uart_ed_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_ED register
- */
-//@{
-#define HW_UART_ED_ADDR(x) (REGS_UART_BASE(x) + 0xCU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_ED(x) (*(__I hw_uart_ed_t *) HW_UART_ED_ADDR(x))
-#define HW_UART_ED_RD(x) (HW_UART_ED(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_ED bitfields
- */
-
-/*!
- * @name Register UART_ED, field PARITYE[6] (RO)
- *
- * The current received dataword contained in D and C3[R8] was received with a
- * parity error.
- *
- * Values:
- * - 0 - The dataword was received without a parity error.
- * - 1 - The dataword was received with a parity error.
- */
-//@{
-#define BP_UART_ED_PARITYE (6U) //!< Bit position for UART_ED_PARITYE.
-#define BM_UART_ED_PARITYE (0x40U) //!< Bit mask for UART_ED_PARITYE.
-#define BS_UART_ED_PARITYE (1U) //!< Bit field size in bits for UART_ED_PARITYE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_ED_PARITYE field.
-#define BR_UART_ED_PARITYE(x) (BITBAND_ACCESS8(HW_UART_ED_ADDR(x), BP_UART_ED_PARITYE))
-#endif
-//@}
-
-/*!
- * @name Register UART_ED, field NOISY[7] (RO)
- *
- * The current received dataword contained in D and C3[R8] was received with
- * noise.
- *
- * Values:
- * - 0 - The dataword was received without noise.
- * - 1 - The data was received with noise.
- */
-//@{
-#define BP_UART_ED_NOISY (7U) //!< Bit position for UART_ED_NOISY.
-#define BM_UART_ED_NOISY (0x80U) //!< Bit mask for UART_ED_NOISY.
-#define BS_UART_ED_NOISY (1U) //!< Bit field size in bits for UART_ED_NOISY.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_ED_NOISY field.
-#define BR_UART_ED_NOISY(x) (BITBAND_ACCESS8(HW_UART_ED_ADDR(x), BP_UART_ED_NOISY))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_MODEM - UART Modem Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_MODEM - UART Modem Register (RW)
- *
- * Reset value: 0x00U
- *
- * The MODEM register controls options for setting the modem configuration.
- * RXRTSE, TXRTSPOL, TXRTSE, and TXCTSE must all be cleared when C7816[ISO7816EN] is
- * enabled. This will cause the RTS to deassert during ISO-7816 wait times. The
- * ISO-7816 protocol does not use the RTS and CTS signals.
- */
-typedef union _hw_uart_modem
-{
- uint8_t U;
- struct _hw_uart_modem_bitfields
- {
- uint8_t TXCTSE : 1; //!< [0] Transmitter clear-to-send enable
- uint8_t TXRTSE : 1; //!< [1] Transmitter request-to-send enable
- uint8_t TXRTSPOL : 1; //!< [2] Transmitter request-to-send polarity
- uint8_t RXRTSE : 1; //!< [3] Receiver request-to-send enable
- uint8_t RESERVED0 : 4; //!< [7:4]
- } B;
-} hw_uart_modem_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_MODEM register
- */
-//@{
-#define HW_UART_MODEM_ADDR(x) (REGS_UART_BASE(x) + 0xDU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_MODEM(x) (*(__IO hw_uart_modem_t *) HW_UART_MODEM_ADDR(x))
-#define HW_UART_MODEM_RD(x) (HW_UART_MODEM(x).U)
-#define HW_UART_MODEM_WR(x, v) (HW_UART_MODEM(x).U = (v))
-#define HW_UART_MODEM_SET(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) | (v)))
-#define HW_UART_MODEM_CLR(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) & ~(v)))
-#define HW_UART_MODEM_TOG(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_MODEM bitfields
- */
-
-/*!
- * @name Register UART_MODEM, field TXCTSE[0] (RW)
- *
- * TXCTSE controls the operation of the transmitter. TXCTSE can be set
- * independently from the state of TXRTSE and RXRTSE.
- *
- * Values:
- * - 0 - CTS has no effect on the transmitter.
- * - 1 - Enables clear-to-send operation. The transmitter checks the state of
- * CTS each time it is ready to send a character. If CTS is asserted, the
- * character is sent. If CTS is deasserted, the signal TXD remains in the mark
- * state and transmission is delayed until CTS is asserted. Changes in CTS as a
- * character is being sent do not affect its transmission.
- */
-//@{
-#define BP_UART_MODEM_TXCTSE (0U) //!< Bit position for UART_MODEM_TXCTSE.
-#define BM_UART_MODEM_TXCTSE (0x01U) //!< Bit mask for UART_MODEM_TXCTSE.
-#define BS_UART_MODEM_TXCTSE (1U) //!< Bit field size in bits for UART_MODEM_TXCTSE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_MODEM_TXCTSE field.
-#define BR_UART_MODEM_TXCTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXCTSE))
-#endif
-
-//! @brief Format value for bitfield UART_MODEM_TXCTSE.
-#define BF_UART_MODEM_TXCTSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MODEM_TXCTSE), uint8_t) & BM_UART_MODEM_TXCTSE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TXCTSE field to a new value.
-#define BW_UART_MODEM_TXCTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXCTSE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_MODEM, field TXRTSE[1] (RW)
- *
- * Controls RTS before and after a transmission.
- *
- * Values:
- * - 0 - The transmitter has no effect on RTS.
- * - 1 - When a character is placed into an empty transmitter data buffer , RTS
- * asserts one bit time before the start bit is transmitted. RTS deasserts
- * one bit time after all characters in the transmitter data buffer and shift
- * register are completely sent, including the last stop bit. (FIFO) (FIFO)
- */
-//@{
-#define BP_UART_MODEM_TXRTSE (1U) //!< Bit position for UART_MODEM_TXRTSE.
-#define BM_UART_MODEM_TXRTSE (0x02U) //!< Bit mask for UART_MODEM_TXRTSE.
-#define BS_UART_MODEM_TXRTSE (1U) //!< Bit field size in bits for UART_MODEM_TXRTSE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_MODEM_TXRTSE field.
-#define BR_UART_MODEM_TXRTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSE))
-#endif
-
-//! @brief Format value for bitfield UART_MODEM_TXRTSE.
-#define BF_UART_MODEM_TXRTSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MODEM_TXRTSE), uint8_t) & BM_UART_MODEM_TXRTSE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TXRTSE field to a new value.
-#define BW_UART_MODEM_TXRTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_MODEM, field TXRTSPOL[2] (RW)
- *
- * Controls the polarity of the transmitter RTS. TXRTSPOL does not affect the
- * polarity of the receiver RTS. RTS will remain negated in the active low state
- * unless TXRTSE is set.
- *
- * Values:
- * - 0 - Transmitter RTS is active low.
- * - 1 - Transmitter RTS is active high.
- */
-//@{
-#define BP_UART_MODEM_TXRTSPOL (2U) //!< Bit position for UART_MODEM_TXRTSPOL.
-#define BM_UART_MODEM_TXRTSPOL (0x04U) //!< Bit mask for UART_MODEM_TXRTSPOL.
-#define BS_UART_MODEM_TXRTSPOL (1U) //!< Bit field size in bits for UART_MODEM_TXRTSPOL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_MODEM_TXRTSPOL field.
-#define BR_UART_MODEM_TXRTSPOL(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSPOL))
-#endif
-
-//! @brief Format value for bitfield UART_MODEM_TXRTSPOL.
-#define BF_UART_MODEM_TXRTSPOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MODEM_TXRTSPOL), uint8_t) & BM_UART_MODEM_TXRTSPOL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TXRTSPOL field to a new value.
-#define BW_UART_MODEM_TXRTSPOL(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSPOL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_MODEM, field RXRTSE[3] (RW)
- *
- * Allows the RTS output to control the CTS input of the transmitting device to
- * prevent receiver overrun. Do not set both RXRTSE and TXRTSE.
- *
- * Values:
- * - 0 - The receiver has no effect on RTS.
- * - 1 - RTS is deasserted if the number of characters in the receiver data
- * register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted
- * when the number of characters in the receiver data register (FIFO) is less
- * than RWFIFO[RXWATER].
- */
-//@{
-#define BP_UART_MODEM_RXRTSE (3U) //!< Bit position for UART_MODEM_RXRTSE.
-#define BM_UART_MODEM_RXRTSE (0x08U) //!< Bit mask for UART_MODEM_RXRTSE.
-#define BS_UART_MODEM_RXRTSE (1U) //!< Bit field size in bits for UART_MODEM_RXRTSE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_MODEM_RXRTSE field.
-#define BR_UART_MODEM_RXRTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_RXRTSE))
-#endif
-
-//! @brief Format value for bitfield UART_MODEM_RXRTSE.
-#define BF_UART_MODEM_RXRTSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MODEM_RXRTSE), uint8_t) & BM_UART_MODEM_RXRTSE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RXRTSE field to a new value.
-#define BW_UART_MODEM_RXRTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_RXRTSE) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_IR - UART Infrared Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_IR - UART Infrared Register (RW)
- *
- * Reset value: 0x00U
- *
- * The IR register controls options for setting the infrared configuration.
- */
-typedef union _hw_uart_ir
-{
- uint8_t U;
- struct _hw_uart_ir_bitfields
- {
- uint8_t TNP : 2; //!< [1:0] Transmitter narrow pulse
- uint8_t IREN : 1; //!< [2] Infrared enable
- uint8_t RESERVED0 : 5; //!< [7:3]
- } B;
-} hw_uart_ir_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_IR register
- */
-//@{
-#define HW_UART_IR_ADDR(x) (REGS_UART_BASE(x) + 0xEU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_IR(x) (*(__IO hw_uart_ir_t *) HW_UART_IR_ADDR(x))
-#define HW_UART_IR_RD(x) (HW_UART_IR(x).U)
-#define HW_UART_IR_WR(x, v) (HW_UART_IR(x).U = (v))
-#define HW_UART_IR_SET(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) | (v)))
-#define HW_UART_IR_CLR(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) & ~(v)))
-#define HW_UART_IR_TOG(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_IR bitfields
- */
-
-/*!
- * @name Register UART_IR, field TNP[1:0] (RW)
- *
- * Enables whether the UART transmits a 1/16, 3/16, 1/32, or 1/4 narrow pulse.
- *
- * Values:
- * - 00 - 3/16.
- * - 01 - 1/16.
- * - 10 - 1/32.
- * - 11 - 1/4.
- */
-//@{
-#define BP_UART_IR_TNP (0U) //!< Bit position for UART_IR_TNP.
-#define BM_UART_IR_TNP (0x03U) //!< Bit mask for UART_IR_TNP.
-#define BS_UART_IR_TNP (2U) //!< Bit field size in bits for UART_IR_TNP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_IR_TNP field.
-#define BR_UART_IR_TNP(x) (HW_UART_IR(x).B.TNP)
-#endif
-
-//! @brief Format value for bitfield UART_IR_TNP.
-#define BF_UART_IR_TNP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IR_TNP), uint8_t) & BM_UART_IR_TNP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TNP field to a new value.
-#define BW_UART_IR_TNP(x, v) (HW_UART_IR_WR(x, (HW_UART_IR_RD(x) & ~BM_UART_IR_TNP) | BF_UART_IR_TNP(v)))
-#endif
-//@}
-
-/*!
- * @name Register UART_IR, field IREN[2] (RW)
- *
- * Enables/disables the infrared modulation/demodulation.
- *
- * Values:
- * - 0 - IR disabled.
- * - 1 - IR enabled.
- */
-//@{
-#define BP_UART_IR_IREN (2U) //!< Bit position for UART_IR_IREN.
-#define BM_UART_IR_IREN (0x04U) //!< Bit mask for UART_IR_IREN.
-#define BS_UART_IR_IREN (1U) //!< Bit field size in bits for UART_IR_IREN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_IR_IREN field.
-#define BR_UART_IR_IREN(x) (BITBAND_ACCESS8(HW_UART_IR_ADDR(x), BP_UART_IR_IREN))
-#endif
-
-//! @brief Format value for bitfield UART_IR_IREN.
-#define BF_UART_IR_IREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IR_IREN), uint8_t) & BM_UART_IR_IREN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IREN field to a new value.
-#define BW_UART_IR_IREN(x, v) (BITBAND_ACCESS8(HW_UART_IR_ADDR(x), BP_UART_IR_IREN) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_PFIFO - UART FIFO Parameters
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_PFIFO - UART FIFO Parameters (RW)
- *
- * Reset value: 0x00U
- *
- * This register provides the ability for the programmer to turn on and off FIFO
- * functionality. It also provides the size of the FIFO that has been
- * implemented. This register may be read at any time. This register must be written only
- * when C2[RE] and C2[TE] are cleared/not set and when the data buffer/FIFO is
- * empty.
- */
-typedef union _hw_uart_pfifo
-{
- uint8_t U;
- struct _hw_uart_pfifo_bitfields
- {
- uint8_t RXFIFOSIZE : 3; //!< [2:0] Receive FIFO. Buffer Depth
- uint8_t RXFE : 1; //!< [3] Receive FIFO Enable
- uint8_t TXFIFOSIZE : 3; //!< [6:4] Transmit FIFO. Buffer Depth
- uint8_t TXFE : 1; //!< [7] Transmit FIFO Enable
- } B;
-} hw_uart_pfifo_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_PFIFO register
- */
-//@{
-#define HW_UART_PFIFO_ADDR(x) (REGS_UART_BASE(x) + 0x10U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_PFIFO(x) (*(__IO hw_uart_pfifo_t *) HW_UART_PFIFO_ADDR(x))
-#define HW_UART_PFIFO_RD(x) (HW_UART_PFIFO(x).U)
-#define HW_UART_PFIFO_WR(x, v) (HW_UART_PFIFO(x).U = (v))
-#define HW_UART_PFIFO_SET(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) | (v)))
-#define HW_UART_PFIFO_CLR(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) & ~(v)))
-#define HW_UART_PFIFO_TOG(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_PFIFO bitfields
- */
-
-/*!
- * @name Register UART_PFIFO, field RXFIFOSIZE[2:0] (RO)
- *
- * The maximum number of receive datawords that can be stored in the receive
- * buffer before an overrun occurs. This field is read only.
- *
- * Values:
- * - 000 - Receive FIFO/Buffer depth = 1 dataword.
- * - 001 - Receive FIFO/Buffer depth = 4 datawords.
- * - 010 - Receive FIFO/Buffer depth = 8 datawords.
- * - 011 - Receive FIFO/Buffer depth = 16 datawords.
- * - 100 - Receive FIFO/Buffer depth = 32 datawords.
- * - 101 - Receive FIFO/Buffer depth = 64 datawords.
- * - 110 - Receive FIFO/Buffer depth = 128 datawords.
- * - 111 - Reserved.
- */
-//@{
-#define BP_UART_PFIFO_RXFIFOSIZE (0U) //!< Bit position for UART_PFIFO_RXFIFOSIZE.
-#define BM_UART_PFIFO_RXFIFOSIZE (0x07U) //!< Bit mask for UART_PFIFO_RXFIFOSIZE.
-#define BS_UART_PFIFO_RXFIFOSIZE (3U) //!< Bit field size in bits for UART_PFIFO_RXFIFOSIZE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_PFIFO_RXFIFOSIZE field.
-#define BR_UART_PFIFO_RXFIFOSIZE(x) (HW_UART_PFIFO(x).B.RXFIFOSIZE)
-#endif
-//@}
-
-/*!
- * @name Register UART_PFIFO, field RXFE[3] (RW)
- *
- * When this field is set, the built in FIFO structure for the receive buffer is
- * enabled. The size of the FIFO structure is indicated by the RXFIFOSIZE field.
- * If this field is not set, the receive buffer operates as a FIFO of depth one
- * dataword regardless of the value in RXFIFOSIZE. Both C2[TE] and C2[RE] must be
- * cleared prior to changing this field. Additionally, TXFLUSH and RXFLUSH
- * commands must be issued immediately after changing this field.
- *
- * Values:
- * - 0 - Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
- * - 1 - Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
- */
-//@{
-#define BP_UART_PFIFO_RXFE (3U) //!< Bit position for UART_PFIFO_RXFE.
-#define BM_UART_PFIFO_RXFE (0x08U) //!< Bit mask for UART_PFIFO_RXFE.
-#define BS_UART_PFIFO_RXFE (1U) //!< Bit field size in bits for UART_PFIFO_RXFE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_PFIFO_RXFE field.
-#define BR_UART_PFIFO_RXFE(x) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_RXFE))
-#endif
-
-//! @brief Format value for bitfield UART_PFIFO_RXFE.
-#define BF_UART_PFIFO_RXFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_PFIFO_RXFE), uint8_t) & BM_UART_PFIFO_RXFE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RXFE field to a new value.
-#define BW_UART_PFIFO_RXFE(x, v) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_RXFE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_PFIFO, field TXFIFOSIZE[6:4] (RO)
- *
- * The maximum number of transmit datawords that can be stored in the transmit
- * buffer. This field is read only.
- *
- * Values:
- * - 000 - Transmit FIFO/Buffer depth = 1 dataword.
- * - 001 - Transmit FIFO/Buffer depth = 4 datawords.
- * - 010 - Transmit FIFO/Buffer depth = 8 datawords.
- * - 011 - Transmit FIFO/Buffer depth = 16 datawords.
- * - 100 - Transmit FIFO/Buffer depth = 32 datawords.
- * - 101 - Transmit FIFO/Buffer depth = 64 datawords.
- * - 110 - Transmit FIFO/Buffer depth = 128 datawords.
- * - 111 - Reserved.
- */
-//@{
-#define BP_UART_PFIFO_TXFIFOSIZE (4U) //!< Bit position for UART_PFIFO_TXFIFOSIZE.
-#define BM_UART_PFIFO_TXFIFOSIZE (0x70U) //!< Bit mask for UART_PFIFO_TXFIFOSIZE.
-#define BS_UART_PFIFO_TXFIFOSIZE (3U) //!< Bit field size in bits for UART_PFIFO_TXFIFOSIZE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_PFIFO_TXFIFOSIZE field.
-#define BR_UART_PFIFO_TXFIFOSIZE(x) (HW_UART_PFIFO(x).B.TXFIFOSIZE)
-#endif
-//@}
-
-/*!
- * @name Register UART_PFIFO, field TXFE[7] (RW)
- *
- * When this field is set, the built in FIFO structure for the transmit buffer
- * is enabled. The size of the FIFO structure is indicated by TXFIFOSIZE. If this
- * field is not set, the transmit buffer operates as a FIFO of depth one dataword
- * regardless of the value in TXFIFOSIZE. Both C2[TE] and C2[RE] must be cleared
- * prior to changing this field. Additionally, TXFLUSH and RXFLUSH commands must
- * be issued immediately after changing this field.
- *
- * Values:
- * - 0 - Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
- * - 1 - Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
- */
-//@{
-#define BP_UART_PFIFO_TXFE (7U) //!< Bit position for UART_PFIFO_TXFE.
-#define BM_UART_PFIFO_TXFE (0x80U) //!< Bit mask for UART_PFIFO_TXFE.
-#define BS_UART_PFIFO_TXFE (1U) //!< Bit field size in bits for UART_PFIFO_TXFE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_PFIFO_TXFE field.
-#define BR_UART_PFIFO_TXFE(x) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_TXFE))
-#endif
-
-//! @brief Format value for bitfield UART_PFIFO_TXFE.
-#define BF_UART_PFIFO_TXFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_PFIFO_TXFE), uint8_t) & BM_UART_PFIFO_TXFE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TXFE field to a new value.
-#define BW_UART_PFIFO_TXFE(x, v) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_TXFE) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_CFIFO - UART FIFO Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_CFIFO - UART FIFO Control Register (RW)
- *
- * Reset value: 0x00U
- *
- * This register provides the ability to program various control fields for FIFO
- * operation. This register may be read or written at any time. Note that
- * writing to TXFLUSH and RXFLUSH may result in data loss and requires careful action
- * to prevent unintended/unpredictable behavior. Therefore, it is recommended that
- * TE and RE be cleared prior to flushing the corresponding FIFO.
- */
-typedef union _hw_uart_cfifo
-{
- uint8_t U;
- struct _hw_uart_cfifo_bitfields
- {
- uint8_t RXUFE : 1; //!< [0] Receive FIFO Underflow Interrupt Enable
- uint8_t TXOFE : 1; //!< [1] Transmit FIFO Overflow Interrupt Enable
- uint8_t RXOFE : 1; //!< [2] Receive FIFO Overflow Interrupt Enable
- uint8_t RESERVED0 : 3; //!< [5:3]
- uint8_t RXFLUSH : 1; //!< [6] Receive FIFO/Buffer Flush
- uint8_t TXFLUSH : 1; //!< [7] Transmit FIFO/Buffer Flush
- } B;
-} hw_uart_cfifo_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_CFIFO register
- */
-//@{
-#define HW_UART_CFIFO_ADDR(x) (REGS_UART_BASE(x) + 0x11U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_CFIFO(x) (*(__IO hw_uart_cfifo_t *) HW_UART_CFIFO_ADDR(x))
-#define HW_UART_CFIFO_RD(x) (HW_UART_CFIFO(x).U)
-#define HW_UART_CFIFO_WR(x, v) (HW_UART_CFIFO(x).U = (v))
-#define HW_UART_CFIFO_SET(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) | (v)))
-#define HW_UART_CFIFO_CLR(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) & ~(v)))
-#define HW_UART_CFIFO_TOG(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_CFIFO bitfields
- */
-
-/*!
- * @name Register UART_CFIFO, field RXUFE[0] (RW)
- *
- * When this field is set, the RXUF flag generates an interrupt to the host.
- *
- * Values:
- * - 0 - RXUF flag does not generate an interrupt to the host.
- * - 1 - RXUF flag generates an interrupt to the host.
- */
-//@{
-#define BP_UART_CFIFO_RXUFE (0U) //!< Bit position for UART_CFIFO_RXUFE.
-#define BM_UART_CFIFO_RXUFE (0x01U) //!< Bit mask for UART_CFIFO_RXUFE.
-#define BS_UART_CFIFO_RXUFE (1U) //!< Bit field size in bits for UART_CFIFO_RXUFE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_CFIFO_RXUFE field.
-#define BR_UART_CFIFO_RXUFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXUFE))
-#endif
-
-//! @brief Format value for bitfield UART_CFIFO_RXUFE.
-#define BF_UART_CFIFO_RXUFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_CFIFO_RXUFE), uint8_t) & BM_UART_CFIFO_RXUFE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RXUFE field to a new value.
-#define BW_UART_CFIFO_RXUFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXUFE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_CFIFO, field TXOFE[1] (RW)
- *
- * When this field is set, the TXOF flag generates an interrupt to the host.
- *
- * Values:
- * - 0 - TXOF flag does not generate an interrupt to the host.
- * - 1 - TXOF flag generates an interrupt to the host.
- */
-//@{
-#define BP_UART_CFIFO_TXOFE (1U) //!< Bit position for UART_CFIFO_TXOFE.
-#define BM_UART_CFIFO_TXOFE (0x02U) //!< Bit mask for UART_CFIFO_TXOFE.
-#define BS_UART_CFIFO_TXOFE (1U) //!< Bit field size in bits for UART_CFIFO_TXOFE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_CFIFO_TXOFE field.
-#define BR_UART_CFIFO_TXOFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXOFE))
-#endif
-
-//! @brief Format value for bitfield UART_CFIFO_TXOFE.
-#define BF_UART_CFIFO_TXOFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_CFIFO_TXOFE), uint8_t) & BM_UART_CFIFO_TXOFE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TXOFE field to a new value.
-#define BW_UART_CFIFO_TXOFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXOFE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_CFIFO, field RXOFE[2] (RW)
- *
- * When this field is set, the RXOF flag generates an interrupt to the host.
- *
- * Values:
- * - 0 - RXOF flag does not generate an interrupt to the host.
- * - 1 - RXOF flag generates an interrupt to the host.
- */
-//@{
-#define BP_UART_CFIFO_RXOFE (2U) //!< Bit position for UART_CFIFO_RXOFE.
-#define BM_UART_CFIFO_RXOFE (0x04U) //!< Bit mask for UART_CFIFO_RXOFE.
-#define BS_UART_CFIFO_RXOFE (1U) //!< Bit field size in bits for UART_CFIFO_RXOFE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_CFIFO_RXOFE field.
-#define BR_UART_CFIFO_RXOFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXOFE))
-#endif
-
-//! @brief Format value for bitfield UART_CFIFO_RXOFE.
-#define BF_UART_CFIFO_RXOFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_CFIFO_RXOFE), uint8_t) & BM_UART_CFIFO_RXOFE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RXOFE field to a new value.
-#define BW_UART_CFIFO_RXOFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXOFE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_CFIFO, field RXFLUSH[6] (WORZ)
- *
- * Writing to this field causes all data that is stored in the receive
- * FIFO/buffer to be flushed. This does not affect data that is in the receive shift
- * register.
- *
- * Values:
- * - 0 - No flush operation occurs.
- * - 1 - All data in the receive FIFO/buffer is cleared out.
- */
-//@{
-#define BP_UART_CFIFO_RXFLUSH (6U) //!< Bit position for UART_CFIFO_RXFLUSH.
-#define BM_UART_CFIFO_RXFLUSH (0x40U) //!< Bit mask for UART_CFIFO_RXFLUSH.
-#define BS_UART_CFIFO_RXFLUSH (1U) //!< Bit field size in bits for UART_CFIFO_RXFLUSH.
-
-//! @brief Format value for bitfield UART_CFIFO_RXFLUSH.
-#define BF_UART_CFIFO_RXFLUSH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_CFIFO_RXFLUSH), uint8_t) & BM_UART_CFIFO_RXFLUSH)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RXFLUSH field to a new value.
-#define BW_UART_CFIFO_RXFLUSH(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXFLUSH) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_CFIFO, field TXFLUSH[7] (WORZ)
- *
- * Writing to this field causes all data that is stored in the transmit
- * FIFO/buffer to be flushed. This does not affect data that is in the transmit shift
- * register.
- *
- * Values:
- * - 0 - No flush operation occurs.
- * - 1 - All data in the transmit FIFO/Buffer is cleared out.
- */
-//@{
-#define BP_UART_CFIFO_TXFLUSH (7U) //!< Bit position for UART_CFIFO_TXFLUSH.
-#define BM_UART_CFIFO_TXFLUSH (0x80U) //!< Bit mask for UART_CFIFO_TXFLUSH.
-#define BS_UART_CFIFO_TXFLUSH (1U) //!< Bit field size in bits for UART_CFIFO_TXFLUSH.
-
-//! @brief Format value for bitfield UART_CFIFO_TXFLUSH.
-#define BF_UART_CFIFO_TXFLUSH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_CFIFO_TXFLUSH), uint8_t) & BM_UART_CFIFO_TXFLUSH)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TXFLUSH field to a new value.
-#define BW_UART_CFIFO_TXFLUSH(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXFLUSH) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_SFIFO - UART FIFO Status Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_SFIFO - UART FIFO Status Register (RW)
- *
- * Reset value: 0xC0U
- *
- * This register provides status information regarding the transmit and receiver
- * buffers/FIFOs, including interrupt information. This register may be written
- * to or read at any time.
- */
-typedef union _hw_uart_sfifo
-{
- uint8_t U;
- struct _hw_uart_sfifo_bitfields
- {
- uint8_t RXUF : 1; //!< [0] Receiver Buffer Underflow Flag
- uint8_t TXOF : 1; //!< [1] Transmitter Buffer Overflow Flag
- uint8_t RXOF : 1; //!< [2] Receiver Buffer Overflow Flag
- uint8_t RESERVED0 : 3; //!< [5:3]
- uint8_t RXEMPT : 1; //!< [6] Receive Buffer/FIFO Empty
- uint8_t TXEMPT : 1; //!< [7] Transmit Buffer/FIFO Empty
- } B;
-} hw_uart_sfifo_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_SFIFO register
- */
-//@{
-#define HW_UART_SFIFO_ADDR(x) (REGS_UART_BASE(x) + 0x12U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_SFIFO(x) (*(__IO hw_uart_sfifo_t *) HW_UART_SFIFO_ADDR(x))
-#define HW_UART_SFIFO_RD(x) (HW_UART_SFIFO(x).U)
-#define HW_UART_SFIFO_WR(x, v) (HW_UART_SFIFO(x).U = (v))
-#define HW_UART_SFIFO_SET(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) | (v)))
-#define HW_UART_SFIFO_CLR(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) & ~(v)))
-#define HW_UART_SFIFO_TOG(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_SFIFO bitfields
- */
-
-/*!
- * @name Register UART_SFIFO, field RXUF[0] (W1C)
- *
- * Indicates that more data has been read from the receive buffer than was
- * present. This field will assert regardless of the value of CFIFO[RXUFE]. However,
- * an interrupt will be issued to the host only if CFIFO[RXUFE] is set. This flag
- * is cleared by writing a 1.
- *
- * Values:
- * - 0 - No receive buffer underflow has occurred since the last time the flag
- * was cleared.
- * - 1 - At least one receive buffer underflow has occurred since the last time
- * the flag was cleared.
- */
-//@{
-#define BP_UART_SFIFO_RXUF (0U) //!< Bit position for UART_SFIFO_RXUF.
-#define BM_UART_SFIFO_RXUF (0x01U) //!< Bit mask for UART_SFIFO_RXUF.
-#define BS_UART_SFIFO_RXUF (1U) //!< Bit field size in bits for UART_SFIFO_RXUF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_SFIFO_RXUF field.
-#define BR_UART_SFIFO_RXUF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXUF))
-#endif
-
-//! @brief Format value for bitfield UART_SFIFO_RXUF.
-#define BF_UART_SFIFO_RXUF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_SFIFO_RXUF), uint8_t) & BM_UART_SFIFO_RXUF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RXUF field to a new value.
-#define BW_UART_SFIFO_RXUF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXUF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_SFIFO, field TXOF[1] (W1C)
- *
- * Indicates that more data has been written to the transmit buffer than it can
- * hold. This field will assert regardless of the value of CFIFO[TXOFE]. However,
- * an interrupt will be issued to the host only if CFIFO[TXOFE] is set. This
- * flag is cleared by writing a 1.
- *
- * Values:
- * - 0 - No transmit buffer overflow has occurred since the last time the flag
- * was cleared.
- * - 1 - At least one transmit buffer overflow has occurred since the last time
- * the flag was cleared.
- */
-//@{
-#define BP_UART_SFIFO_TXOF (1U) //!< Bit position for UART_SFIFO_TXOF.
-#define BM_UART_SFIFO_TXOF (0x02U) //!< Bit mask for UART_SFIFO_TXOF.
-#define BS_UART_SFIFO_TXOF (1U) //!< Bit field size in bits for UART_SFIFO_TXOF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_SFIFO_TXOF field.
-#define BR_UART_SFIFO_TXOF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXOF))
-#endif
-
-//! @brief Format value for bitfield UART_SFIFO_TXOF.
-#define BF_UART_SFIFO_TXOF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_SFIFO_TXOF), uint8_t) & BM_UART_SFIFO_TXOF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TXOF field to a new value.
-#define BW_UART_SFIFO_TXOF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXOF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_SFIFO, field RXOF[2] (W1C)
- *
- * Indicates that more data has been written to the receive buffer than it can
- * hold. This field will assert regardless of the value of CFIFO[RXOFE]. However,
- * an interrupt will be issued to the host only if CFIFO[RXOFE] is set. This flag
- * is cleared by writing a 1.
- *
- * Values:
- * - 0 - No receive buffer overflow has occurred since the last time the flag
- * was cleared.
- * - 1 - At least one receive buffer overflow has occurred since the last time
- * the flag was cleared.
- */
-//@{
-#define BP_UART_SFIFO_RXOF (2U) //!< Bit position for UART_SFIFO_RXOF.
-#define BM_UART_SFIFO_RXOF (0x04U) //!< Bit mask for UART_SFIFO_RXOF.
-#define BS_UART_SFIFO_RXOF (1U) //!< Bit field size in bits for UART_SFIFO_RXOF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_SFIFO_RXOF field.
-#define BR_UART_SFIFO_RXOF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXOF))
-#endif
-
-//! @brief Format value for bitfield UART_SFIFO_RXOF.
-#define BF_UART_SFIFO_RXOF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_SFIFO_RXOF), uint8_t) & BM_UART_SFIFO_RXOF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RXOF field to a new value.
-#define BW_UART_SFIFO_RXOF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXOF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_SFIFO, field RXEMPT[6] (RO)
- *
- * Asserts when there is no data in the receive FIFO/Buffer. This field does not
- * take into account data that is in the receive shift register.
- *
- * Values:
- * - 0 - Receive buffer is not empty.
- * - 1 - Receive buffer is empty.
- */
-//@{
-#define BP_UART_SFIFO_RXEMPT (6U) //!< Bit position for UART_SFIFO_RXEMPT.
-#define BM_UART_SFIFO_RXEMPT (0x40U) //!< Bit mask for UART_SFIFO_RXEMPT.
-#define BS_UART_SFIFO_RXEMPT (1U) //!< Bit field size in bits for UART_SFIFO_RXEMPT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_SFIFO_RXEMPT field.
-#define BR_UART_SFIFO_RXEMPT(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXEMPT))
-#endif
-//@}
-
-/*!
- * @name Register UART_SFIFO, field TXEMPT[7] (RO)
- *
- * Asserts when there is no data in the Transmit FIFO/buffer. This field does
- * not take into account data that is in the transmit shift register.
- *
- * Values:
- * - 0 - Transmit buffer is not empty.
- * - 1 - Transmit buffer is empty.
- */
-//@{
-#define BP_UART_SFIFO_TXEMPT (7U) //!< Bit position for UART_SFIFO_TXEMPT.
-#define BM_UART_SFIFO_TXEMPT (0x80U) //!< Bit mask for UART_SFIFO_TXEMPT.
-#define BS_UART_SFIFO_TXEMPT (1U) //!< Bit field size in bits for UART_SFIFO_TXEMPT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_SFIFO_TXEMPT field.
-#define BR_UART_SFIFO_TXEMPT(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXEMPT))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_TWFIFO - UART FIFO Transmit Watermark
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_TWFIFO - UART FIFO Transmit Watermark (RW)
- *
- * Reset value: 0x00U
- *
- * This register provides the ability to set a programmable threshold for
- * notification of needing additional transmit data. This register may be read at any
- * time but must be written only when C2[TE] is not set. Changing the value of the
- * watermark will not clear the S1[TDRE] flag.
- */
-typedef union _hw_uart_twfifo
-{
- uint8_t U;
- struct _hw_uart_twfifo_bitfields
- {
- uint8_t TXWATER : 8; //!< [7:0] Transmit Watermark
- } B;
-} hw_uart_twfifo_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_TWFIFO register
- */
-//@{
-#define HW_UART_TWFIFO_ADDR(x) (REGS_UART_BASE(x) + 0x13U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_TWFIFO(x) (*(__IO hw_uart_twfifo_t *) HW_UART_TWFIFO_ADDR(x))
-#define HW_UART_TWFIFO_RD(x) (HW_UART_TWFIFO(x).U)
-#define HW_UART_TWFIFO_WR(x, v) (HW_UART_TWFIFO(x).U = (v))
-#define HW_UART_TWFIFO_SET(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) | (v)))
-#define HW_UART_TWFIFO_CLR(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) & ~(v)))
-#define HW_UART_TWFIFO_TOG(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_TWFIFO bitfields
- */
-
-/*!
- * @name Register UART_TWFIFO, field TXWATER[7:0] (RW)
- *
- * When the number of datawords in the transmit FIFO/buffer is equal to or less
- * than the value in this register field, an interrupt via S1[TDRE] or a DMA
- * request via C5[TDMAS] is generated as determined by C5[TDMAS] and C2[TIE]. For
- * proper operation, the value in TXWATER must be set to be less than the size of
- * the transmit buffer/FIFO size as indicated by PFIFO[TXFIFOSIZE] and PFIFO[TXFE].
- */
-//@{
-#define BP_UART_TWFIFO_TXWATER (0U) //!< Bit position for UART_TWFIFO_TXWATER.
-#define BM_UART_TWFIFO_TXWATER (0xFFU) //!< Bit mask for UART_TWFIFO_TXWATER.
-#define BS_UART_TWFIFO_TXWATER (8U) //!< Bit field size in bits for UART_TWFIFO_TXWATER.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_TWFIFO_TXWATER field.
-#define BR_UART_TWFIFO_TXWATER(x) (HW_UART_TWFIFO(x).U)
-#endif
-
-//! @brief Format value for bitfield UART_TWFIFO_TXWATER.
-#define BF_UART_TWFIFO_TXWATER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_TWFIFO_TXWATER), uint8_t) & BM_UART_TWFIFO_TXWATER)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TXWATER field to a new value.
-#define BW_UART_TWFIFO_TXWATER(x, v) (HW_UART_TWFIFO_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_TCFIFO - UART FIFO Transmit Count
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_TCFIFO - UART FIFO Transmit Count (RO)
- *
- * Reset value: 0x00U
- *
- * This is a read only register that indicates how many datawords are currently
- * in the transmit buffer/FIFO. It may be read at any time.
- */
-typedef union _hw_uart_tcfifo
-{
- uint8_t U;
- struct _hw_uart_tcfifo_bitfields
- {
- uint8_t TXCOUNT : 8; //!< [7:0] Transmit Counter
- } B;
-} hw_uart_tcfifo_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_TCFIFO register
- */
-//@{
-#define HW_UART_TCFIFO_ADDR(x) (REGS_UART_BASE(x) + 0x14U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_TCFIFO(x) (*(__I hw_uart_tcfifo_t *) HW_UART_TCFIFO_ADDR(x))
-#define HW_UART_TCFIFO_RD(x) (HW_UART_TCFIFO(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_TCFIFO bitfields
- */
-
-/*!
- * @name Register UART_TCFIFO, field TXCOUNT[7:0] (RO)
- *
- * The value in this register indicates the number of datawords that are in the
- * transmit FIFO/buffer. If a dataword is being transmitted, that is, in the
- * transmit shift register, it is not included in the count. This value may be used
- * in conjunction with PFIFO[TXFIFOSIZE] to calculate how much room is left in the
- * transmit FIFO/buffer.
- */
-//@{
-#define BP_UART_TCFIFO_TXCOUNT (0U) //!< Bit position for UART_TCFIFO_TXCOUNT.
-#define BM_UART_TCFIFO_TXCOUNT (0xFFU) //!< Bit mask for UART_TCFIFO_TXCOUNT.
-#define BS_UART_TCFIFO_TXCOUNT (8U) //!< Bit field size in bits for UART_TCFIFO_TXCOUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_TCFIFO_TXCOUNT field.
-#define BR_UART_TCFIFO_TXCOUNT(x) (HW_UART_TCFIFO(x).U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_RWFIFO - UART FIFO Receive Watermark
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_RWFIFO - UART FIFO Receive Watermark (RW)
- *
- * Reset value: 0x01U
- *
- * This register provides the ability to set a programmable threshold for
- * notification of the need to remove data from the receiver FIFO/buffer. This register
- * may be read at any time but must be written only when C2[RE] is not asserted.
- * Changing the value in this register will not clear S1[RDRF].
- */
-typedef union _hw_uart_rwfifo
-{
- uint8_t U;
- struct _hw_uart_rwfifo_bitfields
- {
- uint8_t RXWATER : 8; //!< [7:0] Receive Watermark
- } B;
-} hw_uart_rwfifo_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_RWFIFO register
- */
-//@{
-#define HW_UART_RWFIFO_ADDR(x) (REGS_UART_BASE(x) + 0x15U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_RWFIFO(x) (*(__IO hw_uart_rwfifo_t *) HW_UART_RWFIFO_ADDR(x))
-#define HW_UART_RWFIFO_RD(x) (HW_UART_RWFIFO(x).U)
-#define HW_UART_RWFIFO_WR(x, v) (HW_UART_RWFIFO(x).U = (v))
-#define HW_UART_RWFIFO_SET(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) | (v)))
-#define HW_UART_RWFIFO_CLR(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) & ~(v)))
-#define HW_UART_RWFIFO_TOG(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_RWFIFO bitfields
- */
-
-/*!
- * @name Register UART_RWFIFO, field RXWATER[7:0] (RW)
- *
- * When the number of datawords in the receive FIFO/buffer is equal to or
- * greater than the value in this register field, an interrupt via S1[RDRF] or a DMA
- * request via C5[RDMAS] is generated as determined by C5[RDMAS] and C2[RIE]. For
- * proper operation, the value in RXWATER must be set to be less than the receive
- * FIFO/buffer size as indicated by PFIFO[RXFIFOSIZE] and PFIFO[RXFE] and must be
- * greater than 0.
- */
-//@{
-#define BP_UART_RWFIFO_RXWATER (0U) //!< Bit position for UART_RWFIFO_RXWATER.
-#define BM_UART_RWFIFO_RXWATER (0xFFU) //!< Bit mask for UART_RWFIFO_RXWATER.
-#define BS_UART_RWFIFO_RXWATER (8U) //!< Bit field size in bits for UART_RWFIFO_RXWATER.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_RWFIFO_RXWATER field.
-#define BR_UART_RWFIFO_RXWATER(x) (HW_UART_RWFIFO(x).U)
-#endif
-
-//! @brief Format value for bitfield UART_RWFIFO_RXWATER.
-#define BF_UART_RWFIFO_RXWATER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_RWFIFO_RXWATER), uint8_t) & BM_UART_RWFIFO_RXWATER)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RXWATER field to a new value.
-#define BW_UART_RWFIFO_RXWATER(x, v) (HW_UART_RWFIFO_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_RCFIFO - UART FIFO Receive Count
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_RCFIFO - UART FIFO Receive Count (RO)
- *
- * Reset value: 0x00U
- *
- * This is a read only register that indicates how many datawords are currently
- * in the receive FIFO/buffer. It may be read at any time.
- */
-typedef union _hw_uart_rcfifo
-{
- uint8_t U;
- struct _hw_uart_rcfifo_bitfields
- {
- uint8_t RXCOUNT : 8; //!< [7:0] Receive Counter
- } B;
-} hw_uart_rcfifo_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_RCFIFO register
- */
-//@{
-#define HW_UART_RCFIFO_ADDR(x) (REGS_UART_BASE(x) + 0x16U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_RCFIFO(x) (*(__I hw_uart_rcfifo_t *) HW_UART_RCFIFO_ADDR(x))
-#define HW_UART_RCFIFO_RD(x) (HW_UART_RCFIFO(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_RCFIFO bitfields
- */
-
-/*!
- * @name Register UART_RCFIFO, field RXCOUNT[7:0] (RO)
- *
- * The value in this register indicates the number of datawords that are in the
- * receive FIFO/buffer. If a dataword is being received, that is, in the receive
- * shift register, it is not included in the count. This value may be used in
- * conjunction with PFIFO[RXFIFOSIZE] to calculate how much room is left in the
- * receive FIFO/buffer.
- */
-//@{
-#define BP_UART_RCFIFO_RXCOUNT (0U) //!< Bit position for UART_RCFIFO_RXCOUNT.
-#define BM_UART_RCFIFO_RXCOUNT (0xFFU) //!< Bit mask for UART_RCFIFO_RXCOUNT.
-#define BS_UART_RCFIFO_RXCOUNT (8U) //!< Bit field size in bits for UART_RCFIFO_RXCOUNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_RCFIFO_RXCOUNT field.
-#define BR_UART_RCFIFO_RXCOUNT(x) (HW_UART_RCFIFO(x).U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_C7816 - UART 7816 Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_C7816 - UART 7816 Control Register (RW)
- *
- * Reset value: 0x00U
- *
- * The C7816 register is the primary control register for ISO-7816 specific
- * functionality. This register is specific to 7816 functionality and the values in
- * this register have no effect on UART operation and should be ignored if
- * ISO_7816E is not set/enabled. This register may be read at any time but values must
- * be changed only when ISO_7816E is not set.
- */
-typedef union _hw_uart_c7816
-{
- uint8_t U;
- struct _hw_uart_c7816_bitfields
- {
- uint8_t ISO_7816E : 1; //!< [0] ISO-7816 Functionality Enabled
- uint8_t TTYPE : 1; //!< [1] Transfer Type
- uint8_t INIT : 1; //!< [2] Detect Initial Character
- uint8_t ANACK : 1; //!< [3] Generate NACK on Error
- uint8_t ONACK : 1; //!< [4] Generate NACK on Overflow
- uint8_t RESERVED0 : 3; //!< [7:5]
- } B;
-} hw_uart_c7816_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_C7816 register
- */
-//@{
-#define HW_UART_C7816_ADDR(x) (REGS_UART_BASE(x) + 0x18U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_C7816(x) (*(__IO hw_uart_c7816_t *) HW_UART_C7816_ADDR(x))
-#define HW_UART_C7816_RD(x) (HW_UART_C7816(x).U)
-#define HW_UART_C7816_WR(x, v) (HW_UART_C7816(x).U = (v))
-#define HW_UART_C7816_SET(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) | (v)))
-#define HW_UART_C7816_CLR(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) & ~(v)))
-#define HW_UART_C7816_TOG(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_C7816 bitfields
- */
-
-/*!
- * @name Register UART_C7816, field ISO_7816E[0] (RW)
- *
- * Indicates that the UART is operating according to the ISO-7816 protocol. This
- * field must be modified only when no transmit or receive is occurring. If this
- * field is changed during a data transfer, the data being transmitted or
- * received may be transferred incorrectly.
- *
- * Values:
- * - 0 - ISO-7816 functionality is turned off/not enabled.
- * - 1 - ISO-7816 functionality is turned on/enabled.
- */
-//@{
-#define BP_UART_C7816_ISO_7816E (0U) //!< Bit position for UART_C7816_ISO_7816E.
-#define BM_UART_C7816_ISO_7816E (0x01U) //!< Bit mask for UART_C7816_ISO_7816E.
-#define BS_UART_C7816_ISO_7816E (1U) //!< Bit field size in bits for UART_C7816_ISO_7816E.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C7816_ISO_7816E field.
-#define BR_UART_C7816_ISO_7816E(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ISO_7816E))
-#endif
-
-//! @brief Format value for bitfield UART_C7816_ISO_7816E.
-#define BF_UART_C7816_ISO_7816E(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C7816_ISO_7816E), uint8_t) & BM_UART_C7816_ISO_7816E)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ISO_7816E field to a new value.
-#define BW_UART_C7816_ISO_7816E(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ISO_7816E) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C7816, field TTYPE[1] (RW)
- *
- * Indicates the transfer protocol being used. See ISO-7816 / smartcard support
- * for more details.
- *
- * Values:
- * - 0 - T = 0 per the ISO-7816 specification.
- * - 1 - T = 1 per the ISO-7816 specification.
- */
-//@{
-#define BP_UART_C7816_TTYPE (1U) //!< Bit position for UART_C7816_TTYPE.
-#define BM_UART_C7816_TTYPE (0x02U) //!< Bit mask for UART_C7816_TTYPE.
-#define BS_UART_C7816_TTYPE (1U) //!< Bit field size in bits for UART_C7816_TTYPE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C7816_TTYPE field.
-#define BR_UART_C7816_TTYPE(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_TTYPE))
-#endif
-
-//! @brief Format value for bitfield UART_C7816_TTYPE.
-#define BF_UART_C7816_TTYPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C7816_TTYPE), uint8_t) & BM_UART_C7816_TTYPE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TTYPE field to a new value.
-#define BW_UART_C7816_TTYPE(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_TTYPE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C7816, field INIT[2] (RW)
- *
- * When this field is set, all received characters are searched for a valid
- * initial character. If an invalid initial character is identified, and ANACK is
- * set, a NACK is sent. All received data is discarded and error flags blocked
- * (S1[NF], S1[OR], S1[FE], S1[PF], IS7816[WT], IS7816[CWT], IS7816[BWT], IS7816[GTV])
- * until a valid initial character is detected. Upon detecting a valid initial
- * character, the configuration values S2[MSBF], C3[TXINV], and S2[RXINV] are
- * automatically updated to reflect the initial character that was received. The
- * actual INIT data value is not stored in the receive buffer. Additionally, upon
- * detection of a valid initial character, IS7816[INITD] is set and an interrupt
- * issued as programmed by IE7816[INITDE]. When a valid initial character is
- * detected, INIT is automatically cleared. This Initial Character Detect feature is
- * supported only in T = 0 protocol mode.
- *
- * Values:
- * - 0 - Normal operating mode. Receiver does not seek to identify initial
- * character.
- * - 1 - Receiver searches for initial character.
- */
-//@{
-#define BP_UART_C7816_INIT (2U) //!< Bit position for UART_C7816_INIT.
-#define BM_UART_C7816_INIT (0x04U) //!< Bit mask for UART_C7816_INIT.
-#define BS_UART_C7816_INIT (1U) //!< Bit field size in bits for UART_C7816_INIT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C7816_INIT field.
-#define BR_UART_C7816_INIT(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_INIT))
-#endif
-
-//! @brief Format value for bitfield UART_C7816_INIT.
-#define BF_UART_C7816_INIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C7816_INIT), uint8_t) & BM_UART_C7816_INIT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INIT field to a new value.
-#define BW_UART_C7816_INIT(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_INIT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C7816, field ANACK[3] (RW)
- *
- * When this field is set, the receiver automatically generates a NACK response
- * if a parity error occurs or if INIT is set and an invalid initial character is
- * detected. A NACK is generated only if TTYPE = 0. If ANACK is set, the UART
- * attempts to retransmit the data indefinitely. To stop retransmission attempts,
- * clear C2[TE] or ISO_7816E and do not set until S1[TC] sets C2[TE] again.
- *
- * Values:
- * - 0 - No NACK is automatically generated.
- * - 1 - A NACK is automatically generated if a parity error is detected or if
- * an invalid initial character is detected.
- */
-//@{
-#define BP_UART_C7816_ANACK (3U) //!< Bit position for UART_C7816_ANACK.
-#define BM_UART_C7816_ANACK (0x08U) //!< Bit mask for UART_C7816_ANACK.
-#define BS_UART_C7816_ANACK (1U) //!< Bit field size in bits for UART_C7816_ANACK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C7816_ANACK field.
-#define BR_UART_C7816_ANACK(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ANACK))
-#endif
-
-//! @brief Format value for bitfield UART_C7816_ANACK.
-#define BF_UART_C7816_ANACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C7816_ANACK), uint8_t) & BM_UART_C7816_ANACK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ANACK field to a new value.
-#define BW_UART_C7816_ANACK(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ANACK) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_C7816, field ONACK[4] (RW)
- *
- * When this field is set, the receiver automatically generates a NACK response
- * if a receive buffer overrun occurs, as indicated by S1[OR]. In many systems,
- * this results in the transmitter resending the packet that overflowed until the
- * retransmit threshold for that transmitter is reached. A NACK is generated only
- * if TTYPE=0. This field operates independently of ANACK. See . Overrun NACK
- * considerations
- *
- * Values:
- * - 0 - The received data does not generate a NACK when the receipt of the data
- * results in an overflow event.
- * - 1 - If the receiver buffer overflows, a NACK is automatically sent on a
- * received character.
- */
-//@{
-#define BP_UART_C7816_ONACK (4U) //!< Bit position for UART_C7816_ONACK.
-#define BM_UART_C7816_ONACK (0x10U) //!< Bit mask for UART_C7816_ONACK.
-#define BS_UART_C7816_ONACK (1U) //!< Bit field size in bits for UART_C7816_ONACK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_C7816_ONACK field.
-#define BR_UART_C7816_ONACK(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ONACK))
-#endif
-
-//! @brief Format value for bitfield UART_C7816_ONACK.
-#define BF_UART_C7816_ONACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C7816_ONACK), uint8_t) & BM_UART_C7816_ONACK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ONACK field to a new value.
-#define BW_UART_C7816_ONACK(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ONACK) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_IE7816 - UART 7816 Interrupt Enable Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_IE7816 - UART 7816 Interrupt Enable Register (RW)
- *
- * Reset value: 0x00U
- *
- * The IE7816 register controls which flags result in an interrupt being issued.
- * This register is specific to 7816 functionality, the corresponding flags that
- * drive the interrupts are not asserted when 7816E is not set/enabled. However,
- * these flags may remain set if they are asserted while 7816E was set and not
- * subsequently cleared. This register may be read or written to at any time.
- */
-typedef union _hw_uart_ie7816
-{
- uint8_t U;
- struct _hw_uart_ie7816_bitfields
- {
- uint8_t RXTE : 1; //!< [0] Receive Threshold Exceeded Interrupt Enable
- uint8_t TXTE : 1; //!< [1] Transmit Threshold Exceeded Interrupt
- //! Enable
- uint8_t GTVE : 1; //!< [2] Guard Timer Violated Interrupt Enable
- uint8_t RESERVED0 : 1; //!< [3]
- uint8_t INITDE : 1; //!< [4] Initial Character Detected Interrupt
- //! Enable
- uint8_t BWTE : 1; //!< [5] Block Wait Timer Interrupt Enable
- uint8_t CWTE : 1; //!< [6] Character Wait Timer Interrupt Enable
- uint8_t WTE : 1; //!< [7] Wait Timer Interrupt Enable
- } B;
-} hw_uart_ie7816_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_IE7816 register
- */
-//@{
-#define HW_UART_IE7816_ADDR(x) (REGS_UART_BASE(x) + 0x19U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_IE7816(x) (*(__IO hw_uart_ie7816_t *) HW_UART_IE7816_ADDR(x))
-#define HW_UART_IE7816_RD(x) (HW_UART_IE7816(x).U)
-#define HW_UART_IE7816_WR(x, v) (HW_UART_IE7816(x).U = (v))
-#define HW_UART_IE7816_SET(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) | (v)))
-#define HW_UART_IE7816_CLR(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) & ~(v)))
-#define HW_UART_IE7816_TOG(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_IE7816 bitfields
- */
-
-/*!
- * @name Register UART_IE7816, field RXTE[0] (RW)
- *
- * Values:
- * - 0 - The assertion of IS7816[RXT] does not result in the generation of an
- * interrupt.
- * - 1 - The assertion of IS7816[RXT] results in the generation of an interrupt.
- */
-//@{
-#define BP_UART_IE7816_RXTE (0U) //!< Bit position for UART_IE7816_RXTE.
-#define BM_UART_IE7816_RXTE (0x01U) //!< Bit mask for UART_IE7816_RXTE.
-#define BS_UART_IE7816_RXTE (1U) //!< Bit field size in bits for UART_IE7816_RXTE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_IE7816_RXTE field.
-#define BR_UART_IE7816_RXTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_RXTE))
-#endif
-
-//! @brief Format value for bitfield UART_IE7816_RXTE.
-#define BF_UART_IE7816_RXTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_RXTE), uint8_t) & BM_UART_IE7816_RXTE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RXTE field to a new value.
-#define BW_UART_IE7816_RXTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_RXTE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_IE7816, field TXTE[1] (RW)
- *
- * Values:
- * - 0 - The assertion of IS7816[TXT] does not result in the generation of an
- * interrupt.
- * - 1 - The assertion of IS7816[TXT] results in the generation of an interrupt.
- */
-//@{
-#define BP_UART_IE7816_TXTE (1U) //!< Bit position for UART_IE7816_TXTE.
-#define BM_UART_IE7816_TXTE (0x02U) //!< Bit mask for UART_IE7816_TXTE.
-#define BS_UART_IE7816_TXTE (1U) //!< Bit field size in bits for UART_IE7816_TXTE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_IE7816_TXTE field.
-#define BR_UART_IE7816_TXTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_TXTE))
-#endif
-
-//! @brief Format value for bitfield UART_IE7816_TXTE.
-#define BF_UART_IE7816_TXTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_TXTE), uint8_t) & BM_UART_IE7816_TXTE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TXTE field to a new value.
-#define BW_UART_IE7816_TXTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_TXTE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_IE7816, field GTVE[2] (RW)
- *
- * Values:
- * - 0 - The assertion of IS7816[GTV] does not result in the generation of an
- * interrupt.
- * - 1 - The assertion of IS7816[GTV] results in the generation of an interrupt.
- */
-//@{
-#define BP_UART_IE7816_GTVE (2U) //!< Bit position for UART_IE7816_GTVE.
-#define BM_UART_IE7816_GTVE (0x04U) //!< Bit mask for UART_IE7816_GTVE.
-#define BS_UART_IE7816_GTVE (1U) //!< Bit field size in bits for UART_IE7816_GTVE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_IE7816_GTVE field.
-#define BR_UART_IE7816_GTVE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_GTVE))
-#endif
-
-//! @brief Format value for bitfield UART_IE7816_GTVE.
-#define BF_UART_IE7816_GTVE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_GTVE), uint8_t) & BM_UART_IE7816_GTVE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the GTVE field to a new value.
-#define BW_UART_IE7816_GTVE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_GTVE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_IE7816, field INITDE[4] (RW)
- *
- * Values:
- * - 0 - The assertion of IS7816[INITD] does not result in the generation of an
- * interrupt.
- * - 1 - The assertion of IS7816[INITD] results in the generation of an
- * interrupt.
- */
-//@{
-#define BP_UART_IE7816_INITDE (4U) //!< Bit position for UART_IE7816_INITDE.
-#define BM_UART_IE7816_INITDE (0x10U) //!< Bit mask for UART_IE7816_INITDE.
-#define BS_UART_IE7816_INITDE (1U) //!< Bit field size in bits for UART_IE7816_INITDE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_IE7816_INITDE field.
-#define BR_UART_IE7816_INITDE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_INITDE))
-#endif
-
-//! @brief Format value for bitfield UART_IE7816_INITDE.
-#define BF_UART_IE7816_INITDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_INITDE), uint8_t) & BM_UART_IE7816_INITDE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INITDE field to a new value.
-#define BW_UART_IE7816_INITDE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_INITDE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_IE7816, field BWTE[5] (RW)
- *
- * Values:
- * - 0 - The assertion of IS7816[BWT] does not result in the generation of an
- * interrupt.
- * - 1 - The assertion of IS7816[BWT] results in the generation of an interrupt.
- */
-//@{
-#define BP_UART_IE7816_BWTE (5U) //!< Bit position for UART_IE7816_BWTE.
-#define BM_UART_IE7816_BWTE (0x20U) //!< Bit mask for UART_IE7816_BWTE.
-#define BS_UART_IE7816_BWTE (1U) //!< Bit field size in bits for UART_IE7816_BWTE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_IE7816_BWTE field.
-#define BR_UART_IE7816_BWTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_BWTE))
-#endif
-
-//! @brief Format value for bitfield UART_IE7816_BWTE.
-#define BF_UART_IE7816_BWTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_BWTE), uint8_t) & BM_UART_IE7816_BWTE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BWTE field to a new value.
-#define BW_UART_IE7816_BWTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_BWTE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_IE7816, field CWTE[6] (RW)
- *
- * Values:
- * - 0 - The assertion of IS7816[CWT] does not result in the generation of an
- * interrupt.
- * - 1 - The assertion of IS7816[CWT] results in the generation of an interrupt.
- */
-//@{
-#define BP_UART_IE7816_CWTE (6U) //!< Bit position for UART_IE7816_CWTE.
-#define BM_UART_IE7816_CWTE (0x40U) //!< Bit mask for UART_IE7816_CWTE.
-#define BS_UART_IE7816_CWTE (1U) //!< Bit field size in bits for UART_IE7816_CWTE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_IE7816_CWTE field.
-#define BR_UART_IE7816_CWTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_CWTE))
-#endif
-
-//! @brief Format value for bitfield UART_IE7816_CWTE.
-#define BF_UART_IE7816_CWTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_CWTE), uint8_t) & BM_UART_IE7816_CWTE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CWTE field to a new value.
-#define BW_UART_IE7816_CWTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_CWTE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_IE7816, field WTE[7] (RW)
- *
- * Values:
- * - 0 - The assertion of IS7816[WT] does not result in the generation of an
- * interrupt.
- * - 1 - The assertion of IS7816[WT] results in the generation of an interrupt.
- */
-//@{
-#define BP_UART_IE7816_WTE (7U) //!< Bit position for UART_IE7816_WTE.
-#define BM_UART_IE7816_WTE (0x80U) //!< Bit mask for UART_IE7816_WTE.
-#define BS_UART_IE7816_WTE (1U) //!< Bit field size in bits for UART_IE7816_WTE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_IE7816_WTE field.
-#define BR_UART_IE7816_WTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_WTE))
-#endif
-
-//! @brief Format value for bitfield UART_IE7816_WTE.
-#define BF_UART_IE7816_WTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_WTE), uint8_t) & BM_UART_IE7816_WTE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WTE field to a new value.
-#define BW_UART_IE7816_WTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_WTE) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_IS7816 - UART 7816 Interrupt Status Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_IS7816 - UART 7816 Interrupt Status Register (RW)
- *
- * Reset value: 0x00U
- *
- * The IS7816 register provides a mechanism to read and clear the interrupt
- * flags. All flags/interrupts are cleared by writing a 1 to the field location.
- * Writing a 0 has no effect. All bits are "sticky", meaning they indicate that only
- * the flag condition that occurred since the last time the bit was cleared, not
- * that the condition currently exists. The status flags are set regardless of
- * whether the corresponding field in the IE7816 is set or cleared. The IE7816
- * controls only if an interrupt is issued to the host processor. This register is
- * specific to 7816 functionality and the values in this register have no affect on
- * UART operation and should be ignored if 7816E is not set/enabled. This
- * register may be read or written at anytime.
- */
-typedef union _hw_uart_is7816
-{
- uint8_t U;
- struct _hw_uart_is7816_bitfields
- {
- uint8_t RXT : 1; //!< [0] Receive Threshold Exceeded Interrupt
- uint8_t TXT : 1; //!< [1] Transmit Threshold Exceeded Interrupt
- uint8_t GTV : 1; //!< [2] Guard Timer Violated Interrupt
- uint8_t RESERVED0 : 1; //!< [3]
- uint8_t INITD : 1; //!< [4] Initial Character Detected Interrupt
- uint8_t BWT : 1; //!< [5] Block Wait Timer Interrupt
- uint8_t CWT : 1; //!< [6] Character Wait Timer Interrupt
- uint8_t WT : 1; //!< [7] Wait Timer Interrupt
- } B;
-} hw_uart_is7816_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_IS7816 register
- */
-//@{
-#define HW_UART_IS7816_ADDR(x) (REGS_UART_BASE(x) + 0x1AU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_IS7816(x) (*(__IO hw_uart_is7816_t *) HW_UART_IS7816_ADDR(x))
-#define HW_UART_IS7816_RD(x) (HW_UART_IS7816(x).U)
-#define HW_UART_IS7816_WR(x, v) (HW_UART_IS7816(x).U = (v))
-#define HW_UART_IS7816_SET(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) | (v)))
-#define HW_UART_IS7816_CLR(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) & ~(v)))
-#define HW_UART_IS7816_TOG(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_IS7816 bitfields
- */
-
-/*!
- * @name Register UART_IS7816, field RXT[0] (W1C)
- *
- * Indicates that there are more than ET7816[RXTHRESHOLD] consecutive NACKS
- * generated in response to parity errors on received data. This flag requires ANACK
- * to be set. Additionally, this flag asserts only when C7816[TTYPE] = 0.
- * Clearing this field also resets the counter keeping track of consecutive NACKS. The
- * UART will continue to attempt to receive data regardless of whether this flag
- * is set. If 7816E is cleared/disabled, RE is cleared/disabled, C7816[TTYPE] = 1,
- * or packet is received without needing to issue a NACK, the internal NACK
- * detection counter is cleared and the count restarts from zero on the next
- * transmitted NACK. This interrupt is cleared by writing 1.
- *
- * Values:
- * - 0 - The number of consecutive NACKS generated as a result of parity errors
- * and buffer overruns is less than or equal to the value in
- * ET7816[RXTHRESHOLD].
- * - 1 - The number of consecutive NACKS generated as a result of parity errors
- * and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].
- */
-//@{
-#define BP_UART_IS7816_RXT (0U) //!< Bit position for UART_IS7816_RXT.
-#define BM_UART_IS7816_RXT (0x01U) //!< Bit mask for UART_IS7816_RXT.
-#define BS_UART_IS7816_RXT (1U) //!< Bit field size in bits for UART_IS7816_RXT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_IS7816_RXT field.
-#define BR_UART_IS7816_RXT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_RXT))
-#endif
-
-//! @brief Format value for bitfield UART_IS7816_RXT.
-#define BF_UART_IS7816_RXT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_RXT), uint8_t) & BM_UART_IS7816_RXT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RXT field to a new value.
-#define BW_UART_IS7816_RXT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_RXT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_IS7816, field TXT[1] (W1C)
- *
- * Indicates that the transmit NACK threshold has been exceeded as indicated by
- * ET7816[TXTHRESHOLD]. Regardless of whether this flag is set, the UART
- * continues to retransmit indefinitely. This flag asserts only when C7816[TTYPE] = 0. If
- * 7816E is cleared/disabled, ANACK is cleared/disabled, C2[TE] is
- * cleared/disabled, C7816[TTYPE] = 1, or packet is transferred without receiving a NACK, the
- * internal NACK detection counter is cleared and the count restarts from zero on
- * the next received NACK. This interrupt is cleared by writing 1.
- *
- * Values:
- * - 0 - The number of retries and corresponding NACKS does not exceed the value
- * in ET7816[TXTHRESHOLD].
- * - 1 - The number of retries and corresponding NACKS exceeds the value in
- * ET7816[TXTHRESHOLD].
- */
-//@{
-#define BP_UART_IS7816_TXT (1U) //!< Bit position for UART_IS7816_TXT.
-#define BM_UART_IS7816_TXT (0x02U) //!< Bit mask for UART_IS7816_TXT.
-#define BS_UART_IS7816_TXT (1U) //!< Bit field size in bits for UART_IS7816_TXT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_IS7816_TXT field.
-#define BR_UART_IS7816_TXT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_TXT))
-#endif
-
-//! @brief Format value for bitfield UART_IS7816_TXT.
-#define BF_UART_IS7816_TXT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_TXT), uint8_t) & BM_UART_IS7816_TXT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TXT field to a new value.
-#define BW_UART_IS7816_TXT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_TXT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_IS7816, field GTV[2] (W1C)
- *
- * Indicates that one or more of the character guard time, block guard time, or
- * guard time are violated. This interrupt is cleared by writing 1.
- *
- * Values:
- * - 0 - A guard time (GT, CGT, or BGT) has not been violated.
- * - 1 - A guard time (GT, CGT, or BGT) has been violated.
- */
-//@{
-#define BP_UART_IS7816_GTV (2U) //!< Bit position for UART_IS7816_GTV.
-#define BM_UART_IS7816_GTV (0x04U) //!< Bit mask for UART_IS7816_GTV.
-#define BS_UART_IS7816_GTV (1U) //!< Bit field size in bits for UART_IS7816_GTV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_IS7816_GTV field.
-#define BR_UART_IS7816_GTV(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_GTV))
-#endif
-
-//! @brief Format value for bitfield UART_IS7816_GTV.
-#define BF_UART_IS7816_GTV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_GTV), uint8_t) & BM_UART_IS7816_GTV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the GTV field to a new value.
-#define BW_UART_IS7816_GTV(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_GTV) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_IS7816, field INITD[4] (W1C)
- *
- * Indicates that a valid initial character is received. This interrupt is
- * cleared by writing 1.
- *
- * Values:
- * - 0 - A valid initial character has not been received.
- * - 1 - A valid initial character has been received.
- */
-//@{
-#define BP_UART_IS7816_INITD (4U) //!< Bit position for UART_IS7816_INITD.
-#define BM_UART_IS7816_INITD (0x10U) //!< Bit mask for UART_IS7816_INITD.
-#define BS_UART_IS7816_INITD (1U) //!< Bit field size in bits for UART_IS7816_INITD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_IS7816_INITD field.
-#define BR_UART_IS7816_INITD(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_INITD))
-#endif
-
-//! @brief Format value for bitfield UART_IS7816_INITD.
-#define BF_UART_IS7816_INITD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_INITD), uint8_t) & BM_UART_IS7816_INITD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INITD field to a new value.
-#define BW_UART_IS7816_INITD(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_INITD) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_IS7816, field BWT[5] (W1C)
- *
- * Indicates that the block wait time, the time between the leading edge of
- * first received character of a block and the leading edge of the last character the
- * previously transmitted block, has exceeded the programmed value. This flag
- * asserts only when C7816[TTYPE] = 1.This interrupt is cleared by writing 1.
- *
- * Values:
- * - 0 - Block wait time (BWT) has not been violated.
- * - 1 - Block wait time (BWT) has been violated.
- */
-//@{
-#define BP_UART_IS7816_BWT (5U) //!< Bit position for UART_IS7816_BWT.
-#define BM_UART_IS7816_BWT (0x20U) //!< Bit mask for UART_IS7816_BWT.
-#define BS_UART_IS7816_BWT (1U) //!< Bit field size in bits for UART_IS7816_BWT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_IS7816_BWT field.
-#define BR_UART_IS7816_BWT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_BWT))
-#endif
-
-//! @brief Format value for bitfield UART_IS7816_BWT.
-#define BF_UART_IS7816_BWT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_BWT), uint8_t) & BM_UART_IS7816_BWT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BWT field to a new value.
-#define BW_UART_IS7816_BWT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_BWT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_IS7816, field CWT[6] (W1C)
- *
- * Indicates that the character wait time, the time between the leading edges of
- * two consecutive characters in a block, has exceeded the programmed value.
- * This flag asserts only when C7816[TTYPE] = 1. This interrupt is cleared by
- * writing 1.
- *
- * Values:
- * - 0 - Character wait time (CWT) has not been violated.
- * - 1 - Character wait time (CWT) has been violated.
- */
-//@{
-#define BP_UART_IS7816_CWT (6U) //!< Bit position for UART_IS7816_CWT.
-#define BM_UART_IS7816_CWT (0x40U) //!< Bit mask for UART_IS7816_CWT.
-#define BS_UART_IS7816_CWT (1U) //!< Bit field size in bits for UART_IS7816_CWT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_IS7816_CWT field.
-#define BR_UART_IS7816_CWT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_CWT))
-#endif
-
-//! @brief Format value for bitfield UART_IS7816_CWT.
-#define BF_UART_IS7816_CWT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_CWT), uint8_t) & BM_UART_IS7816_CWT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CWT field to a new value.
-#define BW_UART_IS7816_CWT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_CWT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register UART_IS7816, field WT[7] (W1C)
- *
- * Indicates that the wait time, the time between the leading edge of a
- * character being transmitted and the leading edge of the next response character, has
- * exceeded the programmed value. This flag asserts only when C7816[TTYPE] = 0.
- * This interrupt is cleared by writing 1.
- *
- * Values:
- * - 0 - Wait time (WT) has not been violated.
- * - 1 - Wait time (WT) has been violated.
- */
-//@{
-#define BP_UART_IS7816_WT (7U) //!< Bit position for UART_IS7816_WT.
-#define BM_UART_IS7816_WT (0x80U) //!< Bit mask for UART_IS7816_WT.
-#define BS_UART_IS7816_WT (1U) //!< Bit field size in bits for UART_IS7816_WT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_IS7816_WT field.
-#define BR_UART_IS7816_WT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_WT))
-#endif
-
-//! @brief Format value for bitfield UART_IS7816_WT.
-#define BF_UART_IS7816_WT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_WT), uint8_t) & BM_UART_IS7816_WT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WT field to a new value.
-#define BW_UART_IS7816_WT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_WT) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_WP7816_T_TYPE0 - UART 7816 Wait Parameter Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_WP7816_T_TYPE0 - UART 7816 Wait Parameter Register (RW)
- *
- * Reset value: 0x0AU
- *
- * The WP7816 register contains constants used in the generation of various wait
- * timer counters. To save register space, this register is used differently
- * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
- * time. This register must be written to only when C7816[ISO_7816E] is not set.
- */
-typedef union _hw_uart_wp7816_t_type0
-{
- uint8_t U;
- struct _hw_uart_wp7816_t_type0_bitfields
- {
- uint8_t WI : 8; //!< [7:0] Wait Time Integer (C7816[TTYPE] = 0)
- } B;
-} hw_uart_wp7816_t_type0_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_WP7816_T_TYPE0 register
- */
-//@{
-#define HW_UART_WP7816_T_TYPE0_ADDR(x) (REGS_UART_BASE(x) + 0x1BU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_WP7816_T_TYPE0(x) (*(__IO hw_uart_wp7816_t_type0_t *) HW_UART_WP7816_T_TYPE0_ADDR(x))
-#define HW_UART_WP7816_T_TYPE0_RD(x) (HW_UART_WP7816_T_TYPE0(x).U)
-#define HW_UART_WP7816_T_TYPE0_WR(x, v) (HW_UART_WP7816_T_TYPE0(x).U = (v))
-#define HW_UART_WP7816_T_TYPE0_SET(x, v) (HW_UART_WP7816_T_TYPE0_WR(x, HW_UART_WP7816_T_TYPE0_RD(x) | (v)))
-#define HW_UART_WP7816_T_TYPE0_CLR(x, v) (HW_UART_WP7816_T_TYPE0_WR(x, HW_UART_WP7816_T_TYPE0_RD(x) & ~(v)))
-#define HW_UART_WP7816_T_TYPE0_TOG(x, v) (HW_UART_WP7816_T_TYPE0_WR(x, HW_UART_WP7816_T_TYPE0_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_WP7816_T_TYPE0 bitfields
- */
-
-/*!
- * @name Register UART_WP7816_T_TYPE0, field WI[7:0] (RW)
- *
- * Used to calculate the value used for the WT counter. It represents a value
- * between 1 and 255. The value of zero is not valid. This value is used only when
- * C7816[TTYPE] = 0. See Wait time and guard time parameters.
- */
-//@{
-#define BP_UART_WP7816_T_TYPE0_WI (0U) //!< Bit position for UART_WP7816_T_TYPE0_WI.
-#define BM_UART_WP7816_T_TYPE0_WI (0xFFU) //!< Bit mask for UART_WP7816_T_TYPE0_WI.
-#define BS_UART_WP7816_T_TYPE0_WI (8U) //!< Bit field size in bits for UART_WP7816_T_TYPE0_WI.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_WP7816_T_TYPE0_WI field.
-#define BR_UART_WP7816_T_TYPE0_WI(x) (HW_UART_WP7816_T_TYPE0(x).U)
-#endif
-
-//! @brief Format value for bitfield UART_WP7816_T_TYPE0_WI.
-#define BF_UART_WP7816_T_TYPE0_WI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_WP7816_T_TYPE0_WI), uint8_t) & BM_UART_WP7816_T_TYPE0_WI)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WI field to a new value.
-#define BW_UART_WP7816_T_TYPE0_WI(x, v) (HW_UART_WP7816_T_TYPE0_WR(x, v))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_UART_WP7816_T_TYPE1 - UART 7816 Wait Parameter Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_WP7816_T_TYPE1 - UART 7816 Wait Parameter Register (RW)
- *
- * Reset value: 0x0AU
- *
- * The WP7816 register contains constants used in the generation of various wait
- * timer counters. To save register space, this register is used differently
- * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
- * time. This register must be written to only when C7816[ISO_7816E] is not set.
- */
-typedef union _hw_uart_wp7816_t_type1
-{
- uint8_t U;
- struct _hw_uart_wp7816_t_type1_bitfields
- {
- uint8_t BWI : 4; //!< [3:0] Block Wait Time Integer(C7816[TTYPE] = 1)
- uint8_t CWI : 4; //!< [7:4] Character Wait Time Integer (C7816[TTYPE]
- //! = 1)
- } B;
-} hw_uart_wp7816_t_type1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_WP7816_T_TYPE1 register
- */
-//@{
-#define HW_UART_WP7816_T_TYPE1_ADDR(x) (REGS_UART_BASE(x) + 0x1BU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_WP7816_T_TYPE1(x) (*(__IO hw_uart_wp7816_t_type1_t *) HW_UART_WP7816_T_TYPE1_ADDR(x))
-#define HW_UART_WP7816_T_TYPE1_RD(x) (HW_UART_WP7816_T_TYPE1(x).U)
-#define HW_UART_WP7816_T_TYPE1_WR(x, v) (HW_UART_WP7816_T_TYPE1(x).U = (v))
-#define HW_UART_WP7816_T_TYPE1_SET(x, v) (HW_UART_WP7816_T_TYPE1_WR(x, HW_UART_WP7816_T_TYPE1_RD(x) | (v)))
-#define HW_UART_WP7816_T_TYPE1_CLR(x, v) (HW_UART_WP7816_T_TYPE1_WR(x, HW_UART_WP7816_T_TYPE1_RD(x) & ~(v)))
-#define HW_UART_WP7816_T_TYPE1_TOG(x, v) (HW_UART_WP7816_T_TYPE1_WR(x, HW_UART_WP7816_T_TYPE1_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_WP7816_T_TYPE1 bitfields
- */
-
-/*!
- * @name Register UART_WP7816_T_TYPE1, field BWI[3:0] (RW)
- *
- * Used to calculate the value used for the BWT counter. It represent a value
- * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
- * and guard time parameters .
- */
-//@{
-#define BP_UART_WP7816_T_TYPE1_BWI (0U) //!< Bit position for UART_WP7816_T_TYPE1_BWI.
-#define BM_UART_WP7816_T_TYPE1_BWI (0x0FU) //!< Bit mask for UART_WP7816_T_TYPE1_BWI.
-#define BS_UART_WP7816_T_TYPE1_BWI (4U) //!< Bit field size in bits for UART_WP7816_T_TYPE1_BWI.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_WP7816_T_TYPE1_BWI field.
-#define BR_UART_WP7816_T_TYPE1_BWI(x) (HW_UART_WP7816_T_TYPE1(x).B.BWI)
-#endif
-
-//! @brief Format value for bitfield UART_WP7816_T_TYPE1_BWI.
-#define BF_UART_WP7816_T_TYPE1_BWI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_WP7816_T_TYPE1_BWI), uint8_t) & BM_UART_WP7816_T_TYPE1_BWI)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BWI field to a new value.
-#define BW_UART_WP7816_T_TYPE1_BWI(x, v) (HW_UART_WP7816_T_TYPE1_WR(x, (HW_UART_WP7816_T_TYPE1_RD(x) & ~BM_UART_WP7816_T_TYPE1_BWI) | BF_UART_WP7816_T_TYPE1_BWI(v)))
-#endif
-//@}
-
-/*!
- * @name Register UART_WP7816_T_TYPE1, field CWI[7:4] (RW)
- *
- * Used to calculate the value used for the CWT counter. It represents a value
- * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
- * and guard time parameters .
- */
-//@{
-#define BP_UART_WP7816_T_TYPE1_CWI (4U) //!< Bit position for UART_WP7816_T_TYPE1_CWI.
-#define BM_UART_WP7816_T_TYPE1_CWI (0xF0U) //!< Bit mask for UART_WP7816_T_TYPE1_CWI.
-#define BS_UART_WP7816_T_TYPE1_CWI (4U) //!< Bit field size in bits for UART_WP7816_T_TYPE1_CWI.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_WP7816_T_TYPE1_CWI field.
-#define BR_UART_WP7816_T_TYPE1_CWI(x) (HW_UART_WP7816_T_TYPE1(x).B.CWI)
-#endif
-
-//! @brief Format value for bitfield UART_WP7816_T_TYPE1_CWI.
-#define BF_UART_WP7816_T_TYPE1_CWI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_WP7816_T_TYPE1_CWI), uint8_t) & BM_UART_WP7816_T_TYPE1_CWI)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CWI field to a new value.
-#define BW_UART_WP7816_T_TYPE1_CWI(x, v) (HW_UART_WP7816_T_TYPE1_WR(x, (HW_UART_WP7816_T_TYPE1_RD(x) & ~BM_UART_WP7816_T_TYPE1_CWI) | BF_UART_WP7816_T_TYPE1_CWI(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_WN7816 - UART 7816 Wait N Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_WN7816 - UART 7816 Wait N Register (RW)
- *
- * Reset value: 0x00U
- *
- * The WN7816 register contains a parameter that is used in the calculation of
- * the guard time counter. This register may be read at any time. This register
- * must be written to only when C7816[ISO_7816E] is not set.
- */
-typedef union _hw_uart_wn7816
-{
- uint8_t U;
- struct _hw_uart_wn7816_bitfields
- {
- uint8_t GTN : 8; //!< [7:0] Guard Band N
- } B;
-} hw_uart_wn7816_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_WN7816 register
- */
-//@{
-#define HW_UART_WN7816_ADDR(x) (REGS_UART_BASE(x) + 0x1CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_WN7816(x) (*(__IO hw_uart_wn7816_t *) HW_UART_WN7816_ADDR(x))
-#define HW_UART_WN7816_RD(x) (HW_UART_WN7816(x).U)
-#define HW_UART_WN7816_WR(x, v) (HW_UART_WN7816(x).U = (v))
-#define HW_UART_WN7816_SET(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) | (v)))
-#define HW_UART_WN7816_CLR(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) & ~(v)))
-#define HW_UART_WN7816_TOG(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_WN7816 bitfields
- */
-
-/*!
- * @name Register UART_WN7816, field GTN[7:0] (RW)
- *
- * Defines a parameter used in the calculation of GT, CGT, and BGT counters. The
- * value represents an integer number between 0 and 255. See Wait time and guard
- * time parameters .
- */
-//@{
-#define BP_UART_WN7816_GTN (0U) //!< Bit position for UART_WN7816_GTN.
-#define BM_UART_WN7816_GTN (0xFFU) //!< Bit mask for UART_WN7816_GTN.
-#define BS_UART_WN7816_GTN (8U) //!< Bit field size in bits for UART_WN7816_GTN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_WN7816_GTN field.
-#define BR_UART_WN7816_GTN(x) (HW_UART_WN7816(x).U)
-#endif
-
-//! @brief Format value for bitfield UART_WN7816_GTN.
-#define BF_UART_WN7816_GTN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_WN7816_GTN), uint8_t) & BM_UART_WN7816_GTN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the GTN field to a new value.
-#define BW_UART_WN7816_GTN(x, v) (HW_UART_WN7816_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_WF7816 - UART 7816 Wait FD Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_WF7816 - UART 7816 Wait FD Register (RW)
- *
- * Reset value: 0x01U
- *
- * The WF7816 contains parameters that are used in the generation of various
- * counters including GT, CGT, BGT, WT, and BWT. This register may be read at any
- * time. This register must be written to only when C7816[ISO_7816E] is not set.
- */
-typedef union _hw_uart_wf7816
-{
- uint8_t U;
- struct _hw_uart_wf7816_bitfields
- {
- uint8_t GTFD : 8; //!< [7:0] FD Multiplier
- } B;
-} hw_uart_wf7816_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_WF7816 register
- */
-//@{
-#define HW_UART_WF7816_ADDR(x) (REGS_UART_BASE(x) + 0x1DU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_WF7816(x) (*(__IO hw_uart_wf7816_t *) HW_UART_WF7816_ADDR(x))
-#define HW_UART_WF7816_RD(x) (HW_UART_WF7816(x).U)
-#define HW_UART_WF7816_WR(x, v) (HW_UART_WF7816(x).U = (v))
-#define HW_UART_WF7816_SET(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) | (v)))
-#define HW_UART_WF7816_CLR(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) & ~(v)))
-#define HW_UART_WF7816_TOG(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_WF7816 bitfields
- */
-
-/*!
- * @name Register UART_WF7816, field GTFD[7:0] (RW)
- *
- * Used as another multiplier in the calculation of WT and BWT. This value
- * represents a number between 1 and 255. The value of 0 is invalid. This value is not
- * used in baud rate generation. See Wait time and guard time parameters and
- * Baud rate generation .
- */
-//@{
-#define BP_UART_WF7816_GTFD (0U) //!< Bit position for UART_WF7816_GTFD.
-#define BM_UART_WF7816_GTFD (0xFFU) //!< Bit mask for UART_WF7816_GTFD.
-#define BS_UART_WF7816_GTFD (8U) //!< Bit field size in bits for UART_WF7816_GTFD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_WF7816_GTFD field.
-#define BR_UART_WF7816_GTFD(x) (HW_UART_WF7816(x).U)
-#endif
-
-//! @brief Format value for bitfield UART_WF7816_GTFD.
-#define BF_UART_WF7816_GTFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_WF7816_GTFD), uint8_t) & BM_UART_WF7816_GTFD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the GTFD field to a new value.
-#define BW_UART_WF7816_GTFD(x, v) (HW_UART_WF7816_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_ET7816 - UART 7816 Error Threshold Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_ET7816 - UART 7816 Error Threshold Register (RW)
- *
- * Reset value: 0x00U
- *
- * The ET7816 register contains fields that determine the number of NACKs that
- * must be received or transmitted before the host processor is notified. This
- * register may be read at anytime. This register must be written to only when
- * C7816[ISO_7816E] is not set.
- */
-typedef union _hw_uart_et7816
-{
- uint8_t U;
- struct _hw_uart_et7816_bitfields
- {
- uint8_t RXTHRESHOLD : 4; //!< [3:0] Receive NACK Threshold
- uint8_t TXTHRESHOLD : 4; //!< [7:4] Transmit NACK Threshold
- } B;
-} hw_uart_et7816_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_ET7816 register
- */
-//@{
-#define HW_UART_ET7816_ADDR(x) (REGS_UART_BASE(x) + 0x1EU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_ET7816(x) (*(__IO hw_uart_et7816_t *) HW_UART_ET7816_ADDR(x))
-#define HW_UART_ET7816_RD(x) (HW_UART_ET7816(x).U)
-#define HW_UART_ET7816_WR(x, v) (HW_UART_ET7816(x).U = (v))
-#define HW_UART_ET7816_SET(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) | (v)))
-#define HW_UART_ET7816_CLR(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) & ~(v)))
-#define HW_UART_ET7816_TOG(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_ET7816 bitfields
- */
-
-/*!
- * @name Register UART_ET7816, field RXTHRESHOLD[3:0] (RW)
- *
- * The value written to this field indicates the maximum number of consecutive
- * NACKs generated as a result of a parity error or receiver buffer overruns
- * before the host processor is notified. After the counter exceeds that value in the
- * field, the IS7816[RXT] is asserted. This field is meaningful only when
- * C7816[TTYPE] = 0. The value read from this field represents the number of consecutive
- * NACKs that have been transmitted since the last successful reception. This
- * counter saturates at 4'hF and does not wrap around. Regardless of the number of
- * NACKs sent, the UART continues to receive valid packets indefinitely. For
- * additional information, see IS7816[RXT] field description.
- */
-//@{
-#define BP_UART_ET7816_RXTHRESHOLD (0U) //!< Bit position for UART_ET7816_RXTHRESHOLD.
-#define BM_UART_ET7816_RXTHRESHOLD (0x0FU) //!< Bit mask for UART_ET7816_RXTHRESHOLD.
-#define BS_UART_ET7816_RXTHRESHOLD (4U) //!< Bit field size in bits for UART_ET7816_RXTHRESHOLD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_ET7816_RXTHRESHOLD field.
-#define BR_UART_ET7816_RXTHRESHOLD(x) (HW_UART_ET7816(x).B.RXTHRESHOLD)
-#endif
-
-//! @brief Format value for bitfield UART_ET7816_RXTHRESHOLD.
-#define BF_UART_ET7816_RXTHRESHOLD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_ET7816_RXTHRESHOLD), uint8_t) & BM_UART_ET7816_RXTHRESHOLD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RXTHRESHOLD field to a new value.
-#define BW_UART_ET7816_RXTHRESHOLD(x, v) (HW_UART_ET7816_WR(x, (HW_UART_ET7816_RD(x) & ~BM_UART_ET7816_RXTHRESHOLD) | BF_UART_ET7816_RXTHRESHOLD(v)))
-#endif
-//@}
-
-/*!
- * @name Register UART_ET7816, field TXTHRESHOLD[7:4] (RW)
- *
- * The value written to this field indicates the maximum number of failed
- * attempts (NACKs) a transmitted character can have before the host processor is
- * notified. This field is meaningful only when C7816[TTYPE] = 0 and C7816[ANACK] = 1.
- * The value read from this field represents the number of consecutive NACKs
- * that have been received since the last successful transmission. This counter
- * saturates at 4'hF and does not wrap around. Regardless of how many NACKs that are
- * received, the UART continues to retransmit indefinitely. This flag only
- * asserts when C7816[TTYPE] = 0. For additional information see the IS7816[TXT] field
- * description.
- *
- * Values:
- * - 0 - TXT asserts on the first NACK that is received.
- * - 1 - TXT asserts on the second NACK that is received.
- */
-//@{
-#define BP_UART_ET7816_TXTHRESHOLD (4U) //!< Bit position for UART_ET7816_TXTHRESHOLD.
-#define BM_UART_ET7816_TXTHRESHOLD (0xF0U) //!< Bit mask for UART_ET7816_TXTHRESHOLD.
-#define BS_UART_ET7816_TXTHRESHOLD (4U) //!< Bit field size in bits for UART_ET7816_TXTHRESHOLD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_ET7816_TXTHRESHOLD field.
-#define BR_UART_ET7816_TXTHRESHOLD(x) (HW_UART_ET7816(x).B.TXTHRESHOLD)
-#endif
-
-//! @brief Format value for bitfield UART_ET7816_TXTHRESHOLD.
-#define BF_UART_ET7816_TXTHRESHOLD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_ET7816_TXTHRESHOLD), uint8_t) & BM_UART_ET7816_TXTHRESHOLD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TXTHRESHOLD field to a new value.
-#define BW_UART_ET7816_TXTHRESHOLD(x, v) (HW_UART_ET7816_WR(x, (HW_UART_ET7816_RD(x) & ~BM_UART_ET7816_TXTHRESHOLD) | BF_UART_ET7816_TXTHRESHOLD(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_UART_TL7816 - UART 7816 Transmit Length Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_UART_TL7816 - UART 7816 Transmit Length Register (RW)
- *
- * Reset value: 0x00U
- *
- * The TL7816 register is used to indicate the number of characters contained in
- * the block being transmitted. This register is used only when C7816[TTYPE] =
- * 1. This register may be read at anytime. This register must be written only
- * when C2[TE] is not enabled.
- */
-typedef union _hw_uart_tl7816
-{
- uint8_t U;
- struct _hw_uart_tl7816_bitfields
- {
- uint8_t TLEN : 8; //!< [7:0] Transmit Length
- } B;
-} hw_uart_tl7816_t;
-#endif
-
-/*!
- * @name Constants and macros for entire UART_TL7816 register
- */
-//@{
-#define HW_UART_TL7816_ADDR(x) (REGS_UART_BASE(x) + 0x1FU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_UART_TL7816(x) (*(__IO hw_uart_tl7816_t *) HW_UART_TL7816_ADDR(x))
-#define HW_UART_TL7816_RD(x) (HW_UART_TL7816(x).U)
-#define HW_UART_TL7816_WR(x, v) (HW_UART_TL7816(x).U = (v))
-#define HW_UART_TL7816_SET(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) | (v)))
-#define HW_UART_TL7816_CLR(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) & ~(v)))
-#define HW_UART_TL7816_TOG(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual UART_TL7816 bitfields
- */
-
-/*!
- * @name Register UART_TL7816, field TLEN[7:0] (RW)
- *
- * This value plus four indicates the number of characters contained in the
- * block being transmitted. This register is automatically decremented by 1 for each
- * character in the information field portion of the block. Additionally, this
- * register is automatically decremented by 1 for the first character of a CRC in
- * the epilogue field. Therefore, this register must be programmed with the number
- * of bytes in the data packet if an LRC is being transmitted, and the number of
- * bytes + 1 if a CRC is being transmitted. This register is not decremented for
- * characters that are assumed to be part of the Prologue field, that is, the
- * first three characters transmitted in a block, or the LRC or last CRC character
- * in the Epilogue field, that is, the last character transmitted. This field
- * must be programed or adjusted only when C2[TE] is cleared.
- */
-//@{
-#define BP_UART_TL7816_TLEN (0U) //!< Bit position for UART_TL7816_TLEN.
-#define BM_UART_TL7816_TLEN (0xFFU) //!< Bit mask for UART_TL7816_TLEN.
-#define BS_UART_TL7816_TLEN (8U) //!< Bit field size in bits for UART_TL7816_TLEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the UART_TL7816_TLEN field.
-#define BR_UART_TL7816_TLEN(x) (HW_UART_TL7816(x).U)
-#endif
-
-//! @brief Format value for bitfield UART_TL7816_TLEN.
-#define BF_UART_TL7816_TLEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_TL7816_TLEN), uint8_t) & BM_UART_TL7816_TLEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TLEN field to a new value.
-#define BW_UART_TL7816_TLEN(x, v) (HW_UART_TL7816_WR(x, v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_uart_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All UART module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_uart
-{
- __IO hw_uart_bdh_t BDH; //!< [0x0] UART Baud Rate Registers: High
- __IO hw_uart_bdl_t BDL; //!< [0x1] UART Baud Rate Registers: Low
- __IO hw_uart_c1_t C1; //!< [0x2] UART Control Register 1
- __IO hw_uart_c2_t C2; //!< [0x3] UART Control Register 2
- __I hw_uart_s1_t S1; //!< [0x4] UART Status Register 1
- __IO hw_uart_s2_t S2; //!< [0x5] UART Status Register 2
- __IO hw_uart_c3_t C3; //!< [0x6] UART Control Register 3
- __IO hw_uart_d_t D; //!< [0x7] UART Data Register
- __IO hw_uart_ma1_t MA1; //!< [0x8] UART Match Address Registers 1
- __IO hw_uart_ma2_t MA2; //!< [0x9] UART Match Address Registers 2
- __IO hw_uart_c4_t C4; //!< [0xA] UART Control Register 4
- __IO hw_uart_c5_t C5; //!< [0xB] UART Control Register 5
- __I hw_uart_ed_t ED; //!< [0xC] UART Extended Data Register
- __IO hw_uart_modem_t MODEM; //!< [0xD] UART Modem Register
- __IO hw_uart_ir_t IR; //!< [0xE] UART Infrared Register
- uint8_t _reserved0[1];
- __IO hw_uart_pfifo_t PFIFO; //!< [0x10] UART FIFO Parameters
- __IO hw_uart_cfifo_t CFIFO; //!< [0x11] UART FIFO Control Register
- __IO hw_uart_sfifo_t SFIFO; //!< [0x12] UART FIFO Status Register
- __IO hw_uart_twfifo_t TWFIFO; //!< [0x13] UART FIFO Transmit Watermark
- __I hw_uart_tcfifo_t TCFIFO; //!< [0x14] UART FIFO Transmit Count
- __IO hw_uart_rwfifo_t RWFIFO; //!< [0x15] UART FIFO Receive Watermark
- __I hw_uart_rcfifo_t RCFIFO; //!< [0x16] UART FIFO Receive Count
- uint8_t _reserved1[1];
- __IO hw_uart_c7816_t C7816; //!< [0x18] UART 7816 Control Register
- __IO hw_uart_ie7816_t IE7816; //!< [0x19] UART 7816 Interrupt Enable Register
- __IO hw_uart_is7816_t IS7816; //!< [0x1A] UART 7816 Interrupt Status Register
- union {
- __IO hw_uart_wp7816_t_type0_t WP7816_T_TYPE0; //!< [0x1B] UART 7816 Wait Parameter Register
- __IO hw_uart_wp7816_t_type1_t WP7816_T_TYPE1; //!< [0x1B] UART 7816 Wait Parameter Register
- };
- __IO hw_uart_wn7816_t WN7816; //!< [0x1C] UART 7816 Wait N Register
- __IO hw_uart_wf7816_t WF7816; //!< [0x1D] UART 7816 Wait FD Register
- __IO hw_uart_et7816_t ET7816; //!< [0x1E] UART 7816 Error Threshold Register
- __IO hw_uart_tl7816_t TL7816; //!< [0x1F] UART 7816 Transmit Length Register
-} hw_uart_t;
-#pragma pack()
-
-//! @brief Macro to access all UART registers.
-//! @param x UART instance number.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_UART(0)</code>.
-#define HW_UART(x) (*(hw_uart_t *) REGS_UART_BASE(x))
-#endif
-
-#endif // __HW_UART_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_usb.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,4276 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_USB_REGISTERS_H__
-#define __HW_USB_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 USB
- *
- * Universal Serial Bus, OTG Capable Controller
- *
- * Registers defined in this header file:
- * - HW_USB_PERID - Peripheral ID register
- * - HW_USB_IDCOMP - Peripheral ID Complement register
- * - HW_USB_REV - Peripheral Revision register
- * - HW_USB_ADDINFO - Peripheral Additional Info register
- * - HW_USB_OTGISTAT - OTG Interrupt Status register
- * - HW_USB_OTGICR - OTG Interrupt Control register
- * - HW_USB_OTGSTAT - OTG Status register
- * - HW_USB_OTGCTL - OTG Control register
- * - HW_USB_ISTAT - Interrupt Status register
- * - HW_USB_INTEN - Interrupt Enable register
- * - HW_USB_ERRSTAT - Error Interrupt Status register
- * - HW_USB_ERREN - Error Interrupt Enable register
- * - HW_USB_STAT - Status register
- * - HW_USB_CTL - Control register
- * - HW_USB_ADDR - Address register
- * - HW_USB_BDTPAGE1 - BDT Page register 1
- * - HW_USB_FRMNUML - Frame Number register Low
- * - HW_USB_FRMNUMH - Frame Number register High
- * - HW_USB_TOKEN - Token register
- * - HW_USB_SOFTHLD - SOF Threshold register
- * - HW_USB_BDTPAGE2 - BDT Page Register 2
- * - HW_USB_BDTPAGE3 - BDT Page Register 3
- * - HW_USB_ENDPTn - Endpoint Control register
- * - HW_USB_USBCTRL - USB Control register
- * - HW_USB_OBSERVE - USB OTG Observe register
- * - HW_USB_CONTROL - USB OTG Control register
- * - HW_USB_USBTRC0 - USB Transceiver Control register 0
- * - HW_USB_USBFRMADJUST - Frame Adjust Register
- * - HW_USB_CLK_RECOVER_CTRL - USB Clock recovery control
- * - HW_USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register
- * - HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status
- *
- * - hw_usb_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_USB_BASE
-#define HW_USB_INSTANCE_COUNT (1U) //!< Number of instances of the USB module.
-#define REGS_USB_BASE (0x40072000U) //!< Base address for USB0.
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_PERID - Peripheral ID register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_PERID - Peripheral ID register (RO)
- *
- * Reset value: 0x04U
- *
- * Reads back the value of 0x04. This value is defined for the USB peripheral.
- */
-typedef union _hw_usb_perid
-{
- uint8_t U;
- struct _hw_usb_perid_bitfields
- {
- uint8_t ID : 6; //!< [5:0] Peripheral Identification
- uint8_t RESERVED0 : 2; //!< [7:6]
- } B;
-} hw_usb_perid_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_PERID register
- */
-//@{
-#define HW_USB_PERID_ADDR (REGS_USB_BASE + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_PERID (*(__I hw_usb_perid_t *) HW_USB_PERID_ADDR)
-#define HW_USB_PERID_RD() (HW_USB_PERID.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_PERID bitfields
- */
-
-/*!
- * @name Register USB_PERID, field ID[5:0] (RO)
- *
- * This field always reads 0x4h.
- */
-//@{
-#define BP_USB_PERID_ID (0U) //!< Bit position for USB_PERID_ID.
-#define BM_USB_PERID_ID (0x3FU) //!< Bit mask for USB_PERID_ID.
-#define BS_USB_PERID_ID (6U) //!< Bit field size in bits for USB_PERID_ID.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_PERID_ID field.
-#define BR_USB_PERID_ID (HW_USB_PERID.B.ID)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_IDCOMP - Peripheral ID Complement register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_IDCOMP - Peripheral ID Complement register (RO)
- *
- * Reset value: 0xFBU
- *
- * Reads back the complement of the Peripheral ID register. For the USB
- * peripheral, the value is 0xFB.
- */
-typedef union _hw_usb_idcomp
-{
- uint8_t U;
- struct _hw_usb_idcomp_bitfields
- {
- uint8_t NID : 6; //!< [5:0]
- uint8_t RESERVED0 : 2; //!< [7:6]
- } B;
-} hw_usb_idcomp_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_IDCOMP register
- */
-//@{
-#define HW_USB_IDCOMP_ADDR (REGS_USB_BASE + 0x4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_IDCOMP (*(__I hw_usb_idcomp_t *) HW_USB_IDCOMP_ADDR)
-#define HW_USB_IDCOMP_RD() (HW_USB_IDCOMP.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_IDCOMP bitfields
- */
-
-/*!
- * @name Register USB_IDCOMP, field NID[5:0] (RO)
- *
- * Ones' complement of PERID[ID]. bits.
- */
-//@{
-#define BP_USB_IDCOMP_NID (0U) //!< Bit position for USB_IDCOMP_NID.
-#define BM_USB_IDCOMP_NID (0x3FU) //!< Bit mask for USB_IDCOMP_NID.
-#define BS_USB_IDCOMP_NID (6U) //!< Bit field size in bits for USB_IDCOMP_NID.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_IDCOMP_NID field.
-#define BR_USB_IDCOMP_NID (HW_USB_IDCOMP.B.NID)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_REV - Peripheral Revision register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_REV - Peripheral Revision register (RO)
- *
- * Reset value: 0x33U
- *
- * Contains the revision number of the USB module.
- */
-typedef union _hw_usb_rev
-{
- uint8_t U;
- struct _hw_usb_rev_bitfields
- {
- uint8_t REV : 8; //!< [7:0] Revision
- } B;
-} hw_usb_rev_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_REV register
- */
-//@{
-#define HW_USB_REV_ADDR (REGS_USB_BASE + 0x8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_REV (*(__I hw_usb_rev_t *) HW_USB_REV_ADDR)
-#define HW_USB_REV_RD() (HW_USB_REV.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_REV bitfields
- */
-
-/*!
- * @name Register USB_REV, field REV[7:0] (RO)
- *
- * Indicates the revision number of the USB Core.
- */
-//@{
-#define BP_USB_REV_REV (0U) //!< Bit position for USB_REV_REV.
-#define BM_USB_REV_REV (0xFFU) //!< Bit mask for USB_REV_REV.
-#define BS_USB_REV_REV (8U) //!< Bit field size in bits for USB_REV_REV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_REV_REV field.
-#define BR_USB_REV_REV (HW_USB_REV.U)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_ADDINFO - Peripheral Additional Info register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_ADDINFO - Peripheral Additional Info register (RO)
- *
- * Reset value: 0x01U
- *
- * Reads back the value of the fixed Interrupt Request Level (IRQNUM) along with
- * the Host Enable bit.
- */
-typedef union _hw_usb_addinfo
-{
- uint8_t U;
- struct _hw_usb_addinfo_bitfields
- {
- uint8_t IEHOST : 1; //!< [0]
- uint8_t RESERVED0 : 2; //!< [2:1]
- uint8_t IRQNUM : 5; //!< [7:3] Assigned Interrupt Request Number
- } B;
-} hw_usb_addinfo_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_ADDINFO register
- */
-//@{
-#define HW_USB_ADDINFO_ADDR (REGS_USB_BASE + 0xCU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_ADDINFO (*(__I hw_usb_addinfo_t *) HW_USB_ADDINFO_ADDR)
-#define HW_USB_ADDINFO_RD() (HW_USB_ADDINFO.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_ADDINFO bitfields
- */
-
-/*!
- * @name Register USB_ADDINFO, field IEHOST[0] (RO)
- *
- * This bit is set if host mode is enabled.
- */
-//@{
-#define BP_USB_ADDINFO_IEHOST (0U) //!< Bit position for USB_ADDINFO_IEHOST.
-#define BM_USB_ADDINFO_IEHOST (0x01U) //!< Bit mask for USB_ADDINFO_IEHOST.
-#define BS_USB_ADDINFO_IEHOST (1U) //!< Bit field size in bits for USB_ADDINFO_IEHOST.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ADDINFO_IEHOST field.
-#define BR_USB_ADDINFO_IEHOST (BITBAND_ACCESS8(HW_USB_ADDINFO_ADDR, BP_USB_ADDINFO_IEHOST))
-#endif
-//@}
-
-/*!
- * @name Register USB_ADDINFO, field IRQNUM[7:3] (RO)
- */
-//@{
-#define BP_USB_ADDINFO_IRQNUM (3U) //!< Bit position for USB_ADDINFO_IRQNUM.
-#define BM_USB_ADDINFO_IRQNUM (0xF8U) //!< Bit mask for USB_ADDINFO_IRQNUM.
-#define BS_USB_ADDINFO_IRQNUM (5U) //!< Bit field size in bits for USB_ADDINFO_IRQNUM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ADDINFO_IRQNUM field.
-#define BR_USB_ADDINFO_IRQNUM (HW_USB_ADDINFO.B.IRQNUM)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_OTGISTAT - OTG Interrupt Status register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_OTGISTAT - OTG Interrupt Status register (RW)
- *
- * Reset value: 0x00U
- *
- * Records changes of the ID sense and VBUS signals. Software can read this
- * register to determine the event that triggers an interrupt. Only bits that have
- * changed since the last software read are set. Writing a one to a bit clears the
- * associated interrupt.
- */
-typedef union _hw_usb_otgistat
-{
- uint8_t U;
- struct _hw_usb_otgistat_bitfields
- {
- uint8_t AVBUSCHG : 1; //!< [0]
- uint8_t RESERVED0 : 1; //!< [1]
- uint8_t B_SESS_CHG : 1; //!< [2]
- uint8_t SESSVLDCHG : 1; //!< [3]
- uint8_t RESERVED1 : 1; //!< [4]
- uint8_t LINE_STATE_CHG : 1; //!< [5]
- uint8_t ONEMSEC : 1; //!< [6]
- uint8_t IDCHG : 1; //!< [7]
- } B;
-} hw_usb_otgistat_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_OTGISTAT register
- */
-//@{
-#define HW_USB_OTGISTAT_ADDR (REGS_USB_BASE + 0x10U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_OTGISTAT (*(__IO hw_usb_otgistat_t *) HW_USB_OTGISTAT_ADDR)
-#define HW_USB_OTGISTAT_RD() (HW_USB_OTGISTAT.U)
-#define HW_USB_OTGISTAT_WR(v) (HW_USB_OTGISTAT.U = (v))
-#define HW_USB_OTGISTAT_SET(v) (HW_USB_OTGISTAT_WR(HW_USB_OTGISTAT_RD() | (v)))
-#define HW_USB_OTGISTAT_CLR(v) (HW_USB_OTGISTAT_WR(HW_USB_OTGISTAT_RD() & ~(v)))
-#define HW_USB_OTGISTAT_TOG(v) (HW_USB_OTGISTAT_WR(HW_USB_OTGISTAT_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_OTGISTAT bitfields
- */
-
-/*!
- * @name Register USB_OTGISTAT, field AVBUSCHG[0] (RW)
- *
- * This bit is set when a change in VBUS is detected on an A device.
- */
-//@{
-#define BP_USB_OTGISTAT_AVBUSCHG (0U) //!< Bit position for USB_OTGISTAT_AVBUSCHG.
-#define BM_USB_OTGISTAT_AVBUSCHG (0x01U) //!< Bit mask for USB_OTGISTAT_AVBUSCHG.
-#define BS_USB_OTGISTAT_AVBUSCHG (1U) //!< Bit field size in bits for USB_OTGISTAT_AVBUSCHG.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_OTGISTAT_AVBUSCHG field.
-#define BR_USB_OTGISTAT_AVBUSCHG (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_AVBUSCHG))
-#endif
-
-//! @brief Format value for bitfield USB_OTGISTAT_AVBUSCHG.
-#define BF_USB_OTGISTAT_AVBUSCHG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGISTAT_AVBUSCHG), uint8_t) & BM_USB_OTGISTAT_AVBUSCHG)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the AVBUSCHG field to a new value.
-#define BW_USB_OTGISTAT_AVBUSCHG(v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_AVBUSCHG) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_OTGISTAT, field B_SESS_CHG[2] (RW)
- *
- * This bit is set when a change in VBUS is detected on a B device.
- */
-//@{
-#define BP_USB_OTGISTAT_B_SESS_CHG (2U) //!< Bit position for USB_OTGISTAT_B_SESS_CHG.
-#define BM_USB_OTGISTAT_B_SESS_CHG (0x04U) //!< Bit mask for USB_OTGISTAT_B_SESS_CHG.
-#define BS_USB_OTGISTAT_B_SESS_CHG (1U) //!< Bit field size in bits for USB_OTGISTAT_B_SESS_CHG.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_OTGISTAT_B_SESS_CHG field.
-#define BR_USB_OTGISTAT_B_SESS_CHG (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_B_SESS_CHG))
-#endif
-
-//! @brief Format value for bitfield USB_OTGISTAT_B_SESS_CHG.
-#define BF_USB_OTGISTAT_B_SESS_CHG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGISTAT_B_SESS_CHG), uint8_t) & BM_USB_OTGISTAT_B_SESS_CHG)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the B_SESS_CHG field to a new value.
-#define BW_USB_OTGISTAT_B_SESS_CHG(v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_B_SESS_CHG) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_OTGISTAT, field SESSVLDCHG[3] (RW)
- *
- * This bit is set when a change in VBUS is detected indicating a session valid
- * or a session no longer valid.
- */
-//@{
-#define BP_USB_OTGISTAT_SESSVLDCHG (3U) //!< Bit position for USB_OTGISTAT_SESSVLDCHG.
-#define BM_USB_OTGISTAT_SESSVLDCHG (0x08U) //!< Bit mask for USB_OTGISTAT_SESSVLDCHG.
-#define BS_USB_OTGISTAT_SESSVLDCHG (1U) //!< Bit field size in bits for USB_OTGISTAT_SESSVLDCHG.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_OTGISTAT_SESSVLDCHG field.
-#define BR_USB_OTGISTAT_SESSVLDCHG (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_SESSVLDCHG))
-#endif
-
-//! @brief Format value for bitfield USB_OTGISTAT_SESSVLDCHG.
-#define BF_USB_OTGISTAT_SESSVLDCHG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGISTAT_SESSVLDCHG), uint8_t) & BM_USB_OTGISTAT_SESSVLDCHG)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SESSVLDCHG field to a new value.
-#define BW_USB_OTGISTAT_SESSVLDCHG(v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_SESSVLDCHG) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_OTGISTAT, field LINE_STATE_CHG[5] (RW)
- *
- * This interrupt is set when the USB line state (CTL[SE0] and CTL[JSTATE] bits)
- * are stable without change for 1 millisecond, and the value of the line state
- * is different from the last time when the line state was stable. It is set on
- * transitions between SE0 and J-state, SE0 and K-state, and J-state and K-state.
- * Changes in J-state while SE0 is true do not cause an interrupt. This interrupt
- * can be used in detecting Reset, Resume, Connect, and Data Line Pulse
- * signaling.
- */
-//@{
-#define BP_USB_OTGISTAT_LINE_STATE_CHG (5U) //!< Bit position for USB_OTGISTAT_LINE_STATE_CHG.
-#define BM_USB_OTGISTAT_LINE_STATE_CHG (0x20U) //!< Bit mask for USB_OTGISTAT_LINE_STATE_CHG.
-#define BS_USB_OTGISTAT_LINE_STATE_CHG (1U) //!< Bit field size in bits for USB_OTGISTAT_LINE_STATE_CHG.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_OTGISTAT_LINE_STATE_CHG field.
-#define BR_USB_OTGISTAT_LINE_STATE_CHG (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_LINE_STATE_CHG))
-#endif
-
-//! @brief Format value for bitfield USB_OTGISTAT_LINE_STATE_CHG.
-#define BF_USB_OTGISTAT_LINE_STATE_CHG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGISTAT_LINE_STATE_CHG), uint8_t) & BM_USB_OTGISTAT_LINE_STATE_CHG)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LINE_STATE_CHG field to a new value.
-#define BW_USB_OTGISTAT_LINE_STATE_CHG(v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_LINE_STATE_CHG) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_OTGISTAT, field ONEMSEC[6] (RW)
- *
- * This bit is set when the 1 millisecond timer expires. This bit stays asserted
- * until cleared by software. The interrupt must be serviced every millisecond
- * to avoid losing 1msec counts.
- */
-//@{
-#define BP_USB_OTGISTAT_ONEMSEC (6U) //!< Bit position for USB_OTGISTAT_ONEMSEC.
-#define BM_USB_OTGISTAT_ONEMSEC (0x40U) //!< Bit mask for USB_OTGISTAT_ONEMSEC.
-#define BS_USB_OTGISTAT_ONEMSEC (1U) //!< Bit field size in bits for USB_OTGISTAT_ONEMSEC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_OTGISTAT_ONEMSEC field.
-#define BR_USB_OTGISTAT_ONEMSEC (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_ONEMSEC))
-#endif
-
-//! @brief Format value for bitfield USB_OTGISTAT_ONEMSEC.
-#define BF_USB_OTGISTAT_ONEMSEC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGISTAT_ONEMSEC), uint8_t) & BM_USB_OTGISTAT_ONEMSEC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ONEMSEC field to a new value.
-#define BW_USB_OTGISTAT_ONEMSEC(v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_ONEMSEC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_OTGISTAT, field IDCHG[7] (RW)
- *
- * This bit is set when a change in the ID Signal from the USB connector is
- * sensed.
- */
-//@{
-#define BP_USB_OTGISTAT_IDCHG (7U) //!< Bit position for USB_OTGISTAT_IDCHG.
-#define BM_USB_OTGISTAT_IDCHG (0x80U) //!< Bit mask for USB_OTGISTAT_IDCHG.
-#define BS_USB_OTGISTAT_IDCHG (1U) //!< Bit field size in bits for USB_OTGISTAT_IDCHG.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_OTGISTAT_IDCHG field.
-#define BR_USB_OTGISTAT_IDCHG (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_IDCHG))
-#endif
-
-//! @brief Format value for bitfield USB_OTGISTAT_IDCHG.
-#define BF_USB_OTGISTAT_IDCHG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGISTAT_IDCHG), uint8_t) & BM_USB_OTGISTAT_IDCHG)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IDCHG field to a new value.
-#define BW_USB_OTGISTAT_IDCHG(v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_IDCHG) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_OTGICR - OTG Interrupt Control register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_OTGICR - OTG Interrupt Control register (RW)
- *
- * Reset value: 0x00U
- *
- * Enables the corresponding interrupt status bits defined in the OTG Interrupt
- * Status Register.
- */
-typedef union _hw_usb_otgicr
-{
- uint8_t U;
- struct _hw_usb_otgicr_bitfields
- {
- uint8_t AVBUSEN : 1; //!< [0] A VBUS Valid Interrupt Enable
- uint8_t RESERVED0 : 1; //!< [1]
- uint8_t BSESSEN : 1; //!< [2] B Session END Interrupt Enable
- uint8_t SESSVLDEN : 1; //!< [3] Session Valid Interrupt Enable
- uint8_t RESERVED1 : 1; //!< [4]
- uint8_t LINESTATEEN : 1; //!< [5] Line State Change Interrupt Enable
- uint8_t ONEMSECEN : 1; //!< [6] One Millisecond Interrupt Enable
- uint8_t IDEN : 1; //!< [7] ID Interrupt Enable
- } B;
-} hw_usb_otgicr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_OTGICR register
- */
-//@{
-#define HW_USB_OTGICR_ADDR (REGS_USB_BASE + 0x14U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_OTGICR (*(__IO hw_usb_otgicr_t *) HW_USB_OTGICR_ADDR)
-#define HW_USB_OTGICR_RD() (HW_USB_OTGICR.U)
-#define HW_USB_OTGICR_WR(v) (HW_USB_OTGICR.U = (v))
-#define HW_USB_OTGICR_SET(v) (HW_USB_OTGICR_WR(HW_USB_OTGICR_RD() | (v)))
-#define HW_USB_OTGICR_CLR(v) (HW_USB_OTGICR_WR(HW_USB_OTGICR_RD() & ~(v)))
-#define HW_USB_OTGICR_TOG(v) (HW_USB_OTGICR_WR(HW_USB_OTGICR_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_OTGICR bitfields
- */
-
-/*!
- * @name Register USB_OTGICR, field AVBUSEN[0] (RW)
- *
- * Values:
- * - 0 - Disables the AVBUSCHG interrupt.
- * - 1 - Enables the AVBUSCHG interrupt.
- */
-//@{
-#define BP_USB_OTGICR_AVBUSEN (0U) //!< Bit position for USB_OTGICR_AVBUSEN.
-#define BM_USB_OTGICR_AVBUSEN (0x01U) //!< Bit mask for USB_OTGICR_AVBUSEN.
-#define BS_USB_OTGICR_AVBUSEN (1U) //!< Bit field size in bits for USB_OTGICR_AVBUSEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_OTGICR_AVBUSEN field.
-#define BR_USB_OTGICR_AVBUSEN (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_AVBUSEN))
-#endif
-
-//! @brief Format value for bitfield USB_OTGICR_AVBUSEN.
-#define BF_USB_OTGICR_AVBUSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGICR_AVBUSEN), uint8_t) & BM_USB_OTGICR_AVBUSEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the AVBUSEN field to a new value.
-#define BW_USB_OTGICR_AVBUSEN(v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_AVBUSEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_OTGICR, field BSESSEN[2] (RW)
- *
- * Values:
- * - 0 - Disables the B_SESS_CHG interrupt.
- * - 1 - Enables the B_SESS_CHG interrupt.
- */
-//@{
-#define BP_USB_OTGICR_BSESSEN (2U) //!< Bit position for USB_OTGICR_BSESSEN.
-#define BM_USB_OTGICR_BSESSEN (0x04U) //!< Bit mask for USB_OTGICR_BSESSEN.
-#define BS_USB_OTGICR_BSESSEN (1U) //!< Bit field size in bits for USB_OTGICR_BSESSEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_OTGICR_BSESSEN field.
-#define BR_USB_OTGICR_BSESSEN (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_BSESSEN))
-#endif
-
-//! @brief Format value for bitfield USB_OTGICR_BSESSEN.
-#define BF_USB_OTGICR_BSESSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGICR_BSESSEN), uint8_t) & BM_USB_OTGICR_BSESSEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BSESSEN field to a new value.
-#define BW_USB_OTGICR_BSESSEN(v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_BSESSEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_OTGICR, field SESSVLDEN[3] (RW)
- *
- * Values:
- * - 0 - Disables the SESSVLDCHG interrupt.
- * - 1 - Enables the SESSVLDCHG interrupt.
- */
-//@{
-#define BP_USB_OTGICR_SESSVLDEN (3U) //!< Bit position for USB_OTGICR_SESSVLDEN.
-#define BM_USB_OTGICR_SESSVLDEN (0x08U) //!< Bit mask for USB_OTGICR_SESSVLDEN.
-#define BS_USB_OTGICR_SESSVLDEN (1U) //!< Bit field size in bits for USB_OTGICR_SESSVLDEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_OTGICR_SESSVLDEN field.
-#define BR_USB_OTGICR_SESSVLDEN (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_SESSVLDEN))
-#endif
-
-//! @brief Format value for bitfield USB_OTGICR_SESSVLDEN.
-#define BF_USB_OTGICR_SESSVLDEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGICR_SESSVLDEN), uint8_t) & BM_USB_OTGICR_SESSVLDEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SESSVLDEN field to a new value.
-#define BW_USB_OTGICR_SESSVLDEN(v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_SESSVLDEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_OTGICR, field LINESTATEEN[5] (RW)
- *
- * Values:
- * - 0 - Disables the LINE_STAT_CHG interrupt.
- * - 1 - Enables the LINE_STAT_CHG interrupt.
- */
-//@{
-#define BP_USB_OTGICR_LINESTATEEN (5U) //!< Bit position for USB_OTGICR_LINESTATEEN.
-#define BM_USB_OTGICR_LINESTATEEN (0x20U) //!< Bit mask for USB_OTGICR_LINESTATEEN.
-#define BS_USB_OTGICR_LINESTATEEN (1U) //!< Bit field size in bits for USB_OTGICR_LINESTATEEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_OTGICR_LINESTATEEN field.
-#define BR_USB_OTGICR_LINESTATEEN (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_LINESTATEEN))
-#endif
-
-//! @brief Format value for bitfield USB_OTGICR_LINESTATEEN.
-#define BF_USB_OTGICR_LINESTATEEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGICR_LINESTATEEN), uint8_t) & BM_USB_OTGICR_LINESTATEEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LINESTATEEN field to a new value.
-#define BW_USB_OTGICR_LINESTATEEN(v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_LINESTATEEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_OTGICR, field ONEMSECEN[6] (RW)
- *
- * Values:
- * - 0 - Diables the 1ms timer interrupt.
- * - 1 - Enables the 1ms timer interrupt.
- */
-//@{
-#define BP_USB_OTGICR_ONEMSECEN (6U) //!< Bit position for USB_OTGICR_ONEMSECEN.
-#define BM_USB_OTGICR_ONEMSECEN (0x40U) //!< Bit mask for USB_OTGICR_ONEMSECEN.
-#define BS_USB_OTGICR_ONEMSECEN (1U) //!< Bit field size in bits for USB_OTGICR_ONEMSECEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_OTGICR_ONEMSECEN field.
-#define BR_USB_OTGICR_ONEMSECEN (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_ONEMSECEN))
-#endif
-
-//! @brief Format value for bitfield USB_OTGICR_ONEMSECEN.
-#define BF_USB_OTGICR_ONEMSECEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGICR_ONEMSECEN), uint8_t) & BM_USB_OTGICR_ONEMSECEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ONEMSECEN field to a new value.
-#define BW_USB_OTGICR_ONEMSECEN(v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_ONEMSECEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_OTGICR, field IDEN[7] (RW)
- *
- * Values:
- * - 0 - The ID interrupt is disabled
- * - 1 - The ID interrupt is enabled
- */
-//@{
-#define BP_USB_OTGICR_IDEN (7U) //!< Bit position for USB_OTGICR_IDEN.
-#define BM_USB_OTGICR_IDEN (0x80U) //!< Bit mask for USB_OTGICR_IDEN.
-#define BS_USB_OTGICR_IDEN (1U) //!< Bit field size in bits for USB_OTGICR_IDEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_OTGICR_IDEN field.
-#define BR_USB_OTGICR_IDEN (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_IDEN))
-#endif
-
-//! @brief Format value for bitfield USB_OTGICR_IDEN.
-#define BF_USB_OTGICR_IDEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGICR_IDEN), uint8_t) & BM_USB_OTGICR_IDEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IDEN field to a new value.
-#define BW_USB_OTGICR_IDEN(v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_IDEN) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_OTGSTAT - OTG Status register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_OTGSTAT - OTG Status register (RW)
- *
- * Reset value: 0x00U
- *
- * Displays the actual value from the external comparator outputs of the ID pin
- * and VBUS.
- */
-typedef union _hw_usb_otgstat
-{
- uint8_t U;
- struct _hw_usb_otgstat_bitfields
- {
- uint8_t AVBUSVLD : 1; //!< [0] A VBUS Valid
- uint8_t RESERVED0 : 1; //!< [1]
- uint8_t BSESSEND : 1; //!< [2] B Session End
- uint8_t SESS_VLD : 1; //!< [3] Session Valid
- uint8_t RESERVED1 : 1; //!< [4]
- uint8_t LINESTATESTABLE : 1; //!< [5]
- uint8_t ONEMSECEN : 1; //!< [6]
- uint8_t ID : 1; //!< [7]
- } B;
-} hw_usb_otgstat_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_OTGSTAT register
- */
-//@{
-#define HW_USB_OTGSTAT_ADDR (REGS_USB_BASE + 0x18U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_OTGSTAT (*(__IO hw_usb_otgstat_t *) HW_USB_OTGSTAT_ADDR)
-#define HW_USB_OTGSTAT_RD() (HW_USB_OTGSTAT.U)
-#define HW_USB_OTGSTAT_WR(v) (HW_USB_OTGSTAT.U = (v))
-#define HW_USB_OTGSTAT_SET(v) (HW_USB_OTGSTAT_WR(HW_USB_OTGSTAT_RD() | (v)))
-#define HW_USB_OTGSTAT_CLR(v) (HW_USB_OTGSTAT_WR(HW_USB_OTGSTAT_RD() & ~(v)))
-#define HW_USB_OTGSTAT_TOG(v) (HW_USB_OTGSTAT_WR(HW_USB_OTGSTAT_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_OTGSTAT bitfields
- */
-
-/*!
- * @name Register USB_OTGSTAT, field AVBUSVLD[0] (RW)
- *
- * Values:
- * - 0 - The VBUS voltage is below the A VBUS Valid threshold.
- * - 1 - The VBUS voltage is above the A VBUS Valid threshold.
- */
-//@{
-#define BP_USB_OTGSTAT_AVBUSVLD (0U) //!< Bit position for USB_OTGSTAT_AVBUSVLD.
-#define BM_USB_OTGSTAT_AVBUSVLD (0x01U) //!< Bit mask for USB_OTGSTAT_AVBUSVLD.
-#define BS_USB_OTGSTAT_AVBUSVLD (1U) //!< Bit field size in bits for USB_OTGSTAT_AVBUSVLD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_OTGSTAT_AVBUSVLD field.
-#define BR_USB_OTGSTAT_AVBUSVLD (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_AVBUSVLD))
-#endif
-
-//! @brief Format value for bitfield USB_OTGSTAT_AVBUSVLD.
-#define BF_USB_OTGSTAT_AVBUSVLD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGSTAT_AVBUSVLD), uint8_t) & BM_USB_OTGSTAT_AVBUSVLD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the AVBUSVLD field to a new value.
-#define BW_USB_OTGSTAT_AVBUSVLD(v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_AVBUSVLD) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_OTGSTAT, field BSESSEND[2] (RW)
- *
- * Values:
- * - 0 - The VBUS voltage is above the B session end threshold.
- * - 1 - The VBUS voltage is below the B session end threshold.
- */
-//@{
-#define BP_USB_OTGSTAT_BSESSEND (2U) //!< Bit position for USB_OTGSTAT_BSESSEND.
-#define BM_USB_OTGSTAT_BSESSEND (0x04U) //!< Bit mask for USB_OTGSTAT_BSESSEND.
-#define BS_USB_OTGSTAT_BSESSEND (1U) //!< Bit field size in bits for USB_OTGSTAT_BSESSEND.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_OTGSTAT_BSESSEND field.
-#define BR_USB_OTGSTAT_BSESSEND (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_BSESSEND))
-#endif
-
-//! @brief Format value for bitfield USB_OTGSTAT_BSESSEND.
-#define BF_USB_OTGSTAT_BSESSEND(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGSTAT_BSESSEND), uint8_t) & BM_USB_OTGSTAT_BSESSEND)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BSESSEND field to a new value.
-#define BW_USB_OTGSTAT_BSESSEND(v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_BSESSEND) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_OTGSTAT, field SESS_VLD[3] (RW)
- *
- * Values:
- * - 0 - The VBUS voltage is below the B session valid threshold
- * - 1 - The VBUS voltage is above the B session valid threshold.
- */
-//@{
-#define BP_USB_OTGSTAT_SESS_VLD (3U) //!< Bit position for USB_OTGSTAT_SESS_VLD.
-#define BM_USB_OTGSTAT_SESS_VLD (0x08U) //!< Bit mask for USB_OTGSTAT_SESS_VLD.
-#define BS_USB_OTGSTAT_SESS_VLD (1U) //!< Bit field size in bits for USB_OTGSTAT_SESS_VLD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_OTGSTAT_SESS_VLD field.
-#define BR_USB_OTGSTAT_SESS_VLD (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_SESS_VLD))
-#endif
-
-//! @brief Format value for bitfield USB_OTGSTAT_SESS_VLD.
-#define BF_USB_OTGSTAT_SESS_VLD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGSTAT_SESS_VLD), uint8_t) & BM_USB_OTGSTAT_SESS_VLD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SESS_VLD field to a new value.
-#define BW_USB_OTGSTAT_SESS_VLD(v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_SESS_VLD) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_OTGSTAT, field LINESTATESTABLE[5] (RW)
- *
- * Indicates that the internal signals that control the LINE_STATE_CHG field of
- * OTGISTAT are stable for at least 1 millisecond. First read LINE_STATE_CHG
- * field and then read this field. If this field reads as 1, then the value of
- * LINE_STATE_CHG can be considered stable.
- *
- * Values:
- * - 0 - The LINE_STAT_CHG bit is not yet stable.
- * - 1 - The LINE_STAT_CHG bit has been debounced and is stable.
- */
-//@{
-#define BP_USB_OTGSTAT_LINESTATESTABLE (5U) //!< Bit position for USB_OTGSTAT_LINESTATESTABLE.
-#define BM_USB_OTGSTAT_LINESTATESTABLE (0x20U) //!< Bit mask for USB_OTGSTAT_LINESTATESTABLE.
-#define BS_USB_OTGSTAT_LINESTATESTABLE (1U) //!< Bit field size in bits for USB_OTGSTAT_LINESTATESTABLE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_OTGSTAT_LINESTATESTABLE field.
-#define BR_USB_OTGSTAT_LINESTATESTABLE (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_LINESTATESTABLE))
-#endif
-
-//! @brief Format value for bitfield USB_OTGSTAT_LINESTATESTABLE.
-#define BF_USB_OTGSTAT_LINESTATESTABLE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGSTAT_LINESTATESTABLE), uint8_t) & BM_USB_OTGSTAT_LINESTATESTABLE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LINESTATESTABLE field to a new value.
-#define BW_USB_OTGSTAT_LINESTATESTABLE(v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_LINESTATESTABLE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_OTGSTAT, field ONEMSECEN[6] (RW)
- *
- * This bit is reserved for the 1ms count, but it is not useful to software.
- */
-//@{
-#define BP_USB_OTGSTAT_ONEMSECEN (6U) //!< Bit position for USB_OTGSTAT_ONEMSECEN.
-#define BM_USB_OTGSTAT_ONEMSECEN (0x40U) //!< Bit mask for USB_OTGSTAT_ONEMSECEN.
-#define BS_USB_OTGSTAT_ONEMSECEN (1U) //!< Bit field size in bits for USB_OTGSTAT_ONEMSECEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_OTGSTAT_ONEMSECEN field.
-#define BR_USB_OTGSTAT_ONEMSECEN (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_ONEMSECEN))
-#endif
-
-//! @brief Format value for bitfield USB_OTGSTAT_ONEMSECEN.
-#define BF_USB_OTGSTAT_ONEMSECEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGSTAT_ONEMSECEN), uint8_t) & BM_USB_OTGSTAT_ONEMSECEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ONEMSECEN field to a new value.
-#define BW_USB_OTGSTAT_ONEMSECEN(v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_ONEMSECEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_OTGSTAT, field ID[7] (RW)
- *
- * Indicates the current state of the ID pin on the USB connector
- *
- * Values:
- * - 0 - Indicates a Type A cable is plugged into the USB connector.
- * - 1 - Indicates no cable is attached or a Type B cable is plugged into the
- * USB connector.
- */
-//@{
-#define BP_USB_OTGSTAT_ID (7U) //!< Bit position for USB_OTGSTAT_ID.
-#define BM_USB_OTGSTAT_ID (0x80U) //!< Bit mask for USB_OTGSTAT_ID.
-#define BS_USB_OTGSTAT_ID (1U) //!< Bit field size in bits for USB_OTGSTAT_ID.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_OTGSTAT_ID field.
-#define BR_USB_OTGSTAT_ID (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_ID))
-#endif
-
-//! @brief Format value for bitfield USB_OTGSTAT_ID.
-#define BF_USB_OTGSTAT_ID(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGSTAT_ID), uint8_t) & BM_USB_OTGSTAT_ID)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ID field to a new value.
-#define BW_USB_OTGSTAT_ID(v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_ID) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_OTGCTL - OTG Control register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_OTGCTL - OTG Control register (RW)
- *
- * Reset value: 0x00U
- *
- * Controls the operation of VBUS and Data Line termination resistors.
- */
-typedef union _hw_usb_otgctl
-{
- uint8_t U;
- struct _hw_usb_otgctl_bitfields
- {
- uint8_t RESERVED0 : 2; //!< [1:0]
- uint8_t OTGEN : 1; //!< [2] On-The-Go pullup/pulldown resistor enable
- uint8_t RESERVED1 : 1; //!< [3]
- uint8_t DMLOW : 1; //!< [4] D- Data Line pull-down resistor enable
- uint8_t DPLOW : 1; //!< [5] D+ Data Line pull-down resistor enable
- uint8_t RESERVED2 : 1; //!< [6]
- uint8_t DPHIGH : 1; //!< [7] D+ Data Line pullup resistor enable
- } B;
-} hw_usb_otgctl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_OTGCTL register
- */
-//@{
-#define HW_USB_OTGCTL_ADDR (REGS_USB_BASE + 0x1CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_OTGCTL (*(__IO hw_usb_otgctl_t *) HW_USB_OTGCTL_ADDR)
-#define HW_USB_OTGCTL_RD() (HW_USB_OTGCTL.U)
-#define HW_USB_OTGCTL_WR(v) (HW_USB_OTGCTL.U = (v))
-#define HW_USB_OTGCTL_SET(v) (HW_USB_OTGCTL_WR(HW_USB_OTGCTL_RD() | (v)))
-#define HW_USB_OTGCTL_CLR(v) (HW_USB_OTGCTL_WR(HW_USB_OTGCTL_RD() & ~(v)))
-#define HW_USB_OTGCTL_TOG(v) (HW_USB_OTGCTL_WR(HW_USB_OTGCTL_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_OTGCTL bitfields
- */
-
-/*!
- * @name Register USB_OTGCTL, field OTGEN[2] (RW)
- *
- * Values:
- * - 0 - If USB_EN is 1 and HOST_MODE is 0 in the Control Register (CTL), then
- * the D+ Data Line pull-up resistors are enabled. If HOST_MODE is 1 the D+
- * and D- Data Line pull-down resistors are engaged.
- * - 1 - The pull-up and pull-down controls in this register are used.
- */
-//@{
-#define BP_USB_OTGCTL_OTGEN (2U) //!< Bit position for USB_OTGCTL_OTGEN.
-#define BM_USB_OTGCTL_OTGEN (0x04U) //!< Bit mask for USB_OTGCTL_OTGEN.
-#define BS_USB_OTGCTL_OTGEN (1U) //!< Bit field size in bits for USB_OTGCTL_OTGEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_OTGCTL_OTGEN field.
-#define BR_USB_OTGCTL_OTGEN (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR, BP_USB_OTGCTL_OTGEN))
-#endif
-
-//! @brief Format value for bitfield USB_OTGCTL_OTGEN.
-#define BF_USB_OTGCTL_OTGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGCTL_OTGEN), uint8_t) & BM_USB_OTGCTL_OTGEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the OTGEN field to a new value.
-#define BW_USB_OTGCTL_OTGEN(v) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR, BP_USB_OTGCTL_OTGEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_OTGCTL, field DMLOW[4] (RW)
- *
- * Values:
- * - 0 - D- pulldown resistor is not enabled.
- * - 1 - D- pulldown resistor is enabled.
- */
-//@{
-#define BP_USB_OTGCTL_DMLOW (4U) //!< Bit position for USB_OTGCTL_DMLOW.
-#define BM_USB_OTGCTL_DMLOW (0x10U) //!< Bit mask for USB_OTGCTL_DMLOW.
-#define BS_USB_OTGCTL_DMLOW (1U) //!< Bit field size in bits for USB_OTGCTL_DMLOW.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_OTGCTL_DMLOW field.
-#define BR_USB_OTGCTL_DMLOW (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR, BP_USB_OTGCTL_DMLOW))
-#endif
-
-//! @brief Format value for bitfield USB_OTGCTL_DMLOW.
-#define BF_USB_OTGCTL_DMLOW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGCTL_DMLOW), uint8_t) & BM_USB_OTGCTL_DMLOW)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DMLOW field to a new value.
-#define BW_USB_OTGCTL_DMLOW(v) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR, BP_USB_OTGCTL_DMLOW) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_OTGCTL, field DPLOW[5] (RW)
- *
- * This bit should always be enabled together with bit 4 (DMLOW)
- *
- * Values:
- * - 0 - D+ pulldown resistor is not enabled.
- * - 1 - D+ pulldown resistor is enabled.
- */
-//@{
-#define BP_USB_OTGCTL_DPLOW (5U) //!< Bit position for USB_OTGCTL_DPLOW.
-#define BM_USB_OTGCTL_DPLOW (0x20U) //!< Bit mask for USB_OTGCTL_DPLOW.
-#define BS_USB_OTGCTL_DPLOW (1U) //!< Bit field size in bits for USB_OTGCTL_DPLOW.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_OTGCTL_DPLOW field.
-#define BR_USB_OTGCTL_DPLOW (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR, BP_USB_OTGCTL_DPLOW))
-#endif
-
-//! @brief Format value for bitfield USB_OTGCTL_DPLOW.
-#define BF_USB_OTGCTL_DPLOW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGCTL_DPLOW), uint8_t) & BM_USB_OTGCTL_DPLOW)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DPLOW field to a new value.
-#define BW_USB_OTGCTL_DPLOW(v) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR, BP_USB_OTGCTL_DPLOW) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_OTGCTL, field DPHIGH[7] (RW)
- *
- * Values:
- * - 0 - D+ pullup resistor is not enabled
- * - 1 - D+ pullup resistor is enabled
- */
-//@{
-#define BP_USB_OTGCTL_DPHIGH (7U) //!< Bit position for USB_OTGCTL_DPHIGH.
-#define BM_USB_OTGCTL_DPHIGH (0x80U) //!< Bit mask for USB_OTGCTL_DPHIGH.
-#define BS_USB_OTGCTL_DPHIGH (1U) //!< Bit field size in bits for USB_OTGCTL_DPHIGH.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_OTGCTL_DPHIGH field.
-#define BR_USB_OTGCTL_DPHIGH (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR, BP_USB_OTGCTL_DPHIGH))
-#endif
-
-//! @brief Format value for bitfield USB_OTGCTL_DPHIGH.
-#define BF_USB_OTGCTL_DPHIGH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGCTL_DPHIGH), uint8_t) & BM_USB_OTGCTL_DPHIGH)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DPHIGH field to a new value.
-#define BW_USB_OTGCTL_DPHIGH(v) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR, BP_USB_OTGCTL_DPHIGH) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_ISTAT - Interrupt Status register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_ISTAT - Interrupt Status register (W1C)
- *
- * Reset value: 0x00U
- *
- * Contains fields for each of the interrupt sources within the USB Module. Each
- * of these fields are qualified with their respective interrupt enable bits.
- * All fields of this register are logically OR'd together along with the OTG
- * Interrupt Status Register (OTGSTAT) to form a single interrupt source for the
- * processor's interrupt controller. After an interrupt bit has been set it may only
- * be cleared by writing a one to the respective interrupt bit. This register
- * contains the value of 0x00 after a reset.
- */
-typedef union _hw_usb_istat
-{
- uint8_t U;
- struct _hw_usb_istat_bitfields
- {
- uint8_t USBRST : 1; //!< [0]
- uint8_t ERROR : 1; //!< [1]
- uint8_t SOFTOK : 1; //!< [2]
- uint8_t TOKDNE : 1; //!< [3]
- uint8_t SLEEP : 1; //!< [4]
- uint8_t RESUME : 1; //!< [5]
- uint8_t ATTACH : 1; //!< [6] Attach Interrupt
- uint8_t STALL : 1; //!< [7] Stall Interrupt
- } B;
-} hw_usb_istat_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_ISTAT register
- */
-//@{
-#define HW_USB_ISTAT_ADDR (REGS_USB_BASE + 0x80U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_ISTAT (*(__IO hw_usb_istat_t *) HW_USB_ISTAT_ADDR)
-#define HW_USB_ISTAT_RD() (HW_USB_ISTAT.U)
-#define HW_USB_ISTAT_WR(v) (HW_USB_ISTAT.U = (v))
-#define HW_USB_ISTAT_SET(v) (HW_USB_ISTAT_WR(HW_USB_ISTAT_RD() | (v)))
-#define HW_USB_ISTAT_CLR(v) (HW_USB_ISTAT_WR(HW_USB_ISTAT_RD() & ~(v)))
-#define HW_USB_ISTAT_TOG(v) (HW_USB_ISTAT_WR(HW_USB_ISTAT_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_ISTAT bitfields
- */
-
-/*!
- * @name Register USB_ISTAT, field USBRST[0] (W1C)
- *
- * This bit is set when the USB Module has decoded a valid USB reset. This
- * informs the processor that it should write 0x00 into the address register and
- * enable endpoint 0. USBRST is set after a USB reset has been detected for 2.5
- * microseconds. It is not asserted again until the USB reset condition has been
- * removed and then reasserted.
- */
-//@{
-#define BP_USB_ISTAT_USBRST (0U) //!< Bit position for USB_ISTAT_USBRST.
-#define BM_USB_ISTAT_USBRST (0x01U) //!< Bit mask for USB_ISTAT_USBRST.
-#define BS_USB_ISTAT_USBRST (1U) //!< Bit field size in bits for USB_ISTAT_USBRST.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ISTAT_USBRST field.
-#define BR_USB_ISTAT_USBRST (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_USBRST))
-#endif
-
-//! @brief Format value for bitfield USB_ISTAT_USBRST.
-#define BF_USB_ISTAT_USBRST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ISTAT_USBRST), uint8_t) & BM_USB_ISTAT_USBRST)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the USBRST field to a new value.
-#define BW_USB_ISTAT_USBRST(v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_USBRST) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_ISTAT, field ERROR[1] (W1C)
- *
- * This bit is set when any of the error conditions within Error Interrupt
- * Status (ERRSTAT) register occur. The processor must then read the ERRSTAT register
- * to determine the source of the error.
- */
-//@{
-#define BP_USB_ISTAT_ERROR (1U) //!< Bit position for USB_ISTAT_ERROR.
-#define BM_USB_ISTAT_ERROR (0x02U) //!< Bit mask for USB_ISTAT_ERROR.
-#define BS_USB_ISTAT_ERROR (1U) //!< Bit field size in bits for USB_ISTAT_ERROR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ISTAT_ERROR field.
-#define BR_USB_ISTAT_ERROR (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_ERROR))
-#endif
-
-//! @brief Format value for bitfield USB_ISTAT_ERROR.
-#define BF_USB_ISTAT_ERROR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ISTAT_ERROR), uint8_t) & BM_USB_ISTAT_ERROR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERROR field to a new value.
-#define BW_USB_ISTAT_ERROR(v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_ERROR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_ISTAT, field SOFTOK[2] (W1C)
- *
- * This bit is set when the USB Module receives a Start Of Frame (SOF) token. In
- * Host mode this field is set when the SOF threshold is reached, so that
- * software can prepare for the next SOF.
- */
-//@{
-#define BP_USB_ISTAT_SOFTOK (2U) //!< Bit position for USB_ISTAT_SOFTOK.
-#define BM_USB_ISTAT_SOFTOK (0x04U) //!< Bit mask for USB_ISTAT_SOFTOK.
-#define BS_USB_ISTAT_SOFTOK (1U) //!< Bit field size in bits for USB_ISTAT_SOFTOK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ISTAT_SOFTOK field.
-#define BR_USB_ISTAT_SOFTOK (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_SOFTOK))
-#endif
-
-//! @brief Format value for bitfield USB_ISTAT_SOFTOK.
-#define BF_USB_ISTAT_SOFTOK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ISTAT_SOFTOK), uint8_t) & BM_USB_ISTAT_SOFTOK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SOFTOK field to a new value.
-#define BW_USB_ISTAT_SOFTOK(v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_SOFTOK) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_ISTAT, field TOKDNE[3] (W1C)
- *
- * This bit is set when the current token being processed has completed. The
- * processor must immediately read the STATUS (STAT) register to determine the
- * EndPoint and BD used for this token. Clearing this bit (by writing a one) causes
- * STAT to be cleared or the STAT holding register to be loaded into the STAT
- * register.
- */
-//@{
-#define BP_USB_ISTAT_TOKDNE (3U) //!< Bit position for USB_ISTAT_TOKDNE.
-#define BM_USB_ISTAT_TOKDNE (0x08U) //!< Bit mask for USB_ISTAT_TOKDNE.
-#define BS_USB_ISTAT_TOKDNE (1U) //!< Bit field size in bits for USB_ISTAT_TOKDNE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ISTAT_TOKDNE field.
-#define BR_USB_ISTAT_TOKDNE (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_TOKDNE))
-#endif
-
-//! @brief Format value for bitfield USB_ISTAT_TOKDNE.
-#define BF_USB_ISTAT_TOKDNE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ISTAT_TOKDNE), uint8_t) & BM_USB_ISTAT_TOKDNE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TOKDNE field to a new value.
-#define BW_USB_ISTAT_TOKDNE(v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_TOKDNE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_ISTAT, field SLEEP[4] (W1C)
- *
- * This bit is set when the USB Module detects a constant idle on the USB bus
- * for 3 ms. The sleep timer is reset by activity on the USB bus.
- */
-//@{
-#define BP_USB_ISTAT_SLEEP (4U) //!< Bit position for USB_ISTAT_SLEEP.
-#define BM_USB_ISTAT_SLEEP (0x10U) //!< Bit mask for USB_ISTAT_SLEEP.
-#define BS_USB_ISTAT_SLEEP (1U) //!< Bit field size in bits for USB_ISTAT_SLEEP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ISTAT_SLEEP field.
-#define BR_USB_ISTAT_SLEEP (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_SLEEP))
-#endif
-
-//! @brief Format value for bitfield USB_ISTAT_SLEEP.
-#define BF_USB_ISTAT_SLEEP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ISTAT_SLEEP), uint8_t) & BM_USB_ISTAT_SLEEP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SLEEP field to a new value.
-#define BW_USB_ISTAT_SLEEP(v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_SLEEP) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_ISTAT, field RESUME[5] (W1C)
- *
- * This bit is set when a K-state is observed on the DP/DM signals for 2.5 us.
- * When not in suspend mode this interrupt must be disabled.
- */
-//@{
-#define BP_USB_ISTAT_RESUME (5U) //!< Bit position for USB_ISTAT_RESUME.
-#define BM_USB_ISTAT_RESUME (0x20U) //!< Bit mask for USB_ISTAT_RESUME.
-#define BS_USB_ISTAT_RESUME (1U) //!< Bit field size in bits for USB_ISTAT_RESUME.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ISTAT_RESUME field.
-#define BR_USB_ISTAT_RESUME (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_RESUME))
-#endif
-
-//! @brief Format value for bitfield USB_ISTAT_RESUME.
-#define BF_USB_ISTAT_RESUME(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ISTAT_RESUME), uint8_t) & BM_USB_ISTAT_RESUME)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RESUME field to a new value.
-#define BW_USB_ISTAT_RESUME(v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_RESUME) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_ISTAT, field ATTACH[6] (W1C)
- *
- * This bit is set when the USB Module detects an attach of a USB device. This
- * signal is only valid if HOSTMODEEN is true. This interrupt signifies that a
- * peripheral is now present and must be configured; it is asserted if there have
- * been no transitions on the USB for 2.5 us and the current bus state is not SE0."
- */
-//@{
-#define BP_USB_ISTAT_ATTACH (6U) //!< Bit position for USB_ISTAT_ATTACH.
-#define BM_USB_ISTAT_ATTACH (0x40U) //!< Bit mask for USB_ISTAT_ATTACH.
-#define BS_USB_ISTAT_ATTACH (1U) //!< Bit field size in bits for USB_ISTAT_ATTACH.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ISTAT_ATTACH field.
-#define BR_USB_ISTAT_ATTACH (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_ATTACH))
-#endif
-
-//! @brief Format value for bitfield USB_ISTAT_ATTACH.
-#define BF_USB_ISTAT_ATTACH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ISTAT_ATTACH), uint8_t) & BM_USB_ISTAT_ATTACH)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ATTACH field to a new value.
-#define BW_USB_ISTAT_ATTACH(v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_ATTACH) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_ISTAT, field STALL[7] (W1C)
- *
- * In Target mode this bit is asserted when a STALL handshake is sent by the
- * SIE. In Host mode this bit is set when the USB Module detects a STALL acknowledge
- * during the handshake phase of a USB transaction.This interrupt can be used to
- * determine whether the last USB transaction was completed successfully or
- * stalled.
- */
-//@{
-#define BP_USB_ISTAT_STALL (7U) //!< Bit position for USB_ISTAT_STALL.
-#define BM_USB_ISTAT_STALL (0x80U) //!< Bit mask for USB_ISTAT_STALL.
-#define BS_USB_ISTAT_STALL (1U) //!< Bit field size in bits for USB_ISTAT_STALL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ISTAT_STALL field.
-#define BR_USB_ISTAT_STALL (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_STALL))
-#endif
-
-//! @brief Format value for bitfield USB_ISTAT_STALL.
-#define BF_USB_ISTAT_STALL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ISTAT_STALL), uint8_t) & BM_USB_ISTAT_STALL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the STALL field to a new value.
-#define BW_USB_ISTAT_STALL(v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_STALL) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_INTEN - Interrupt Enable register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_INTEN - Interrupt Enable register (RW)
- *
- * Reset value: 0x00U
- *
- * Contains enable fields for each of the interrupt sources within the USB
- * Module. Setting any of these bits enables the respective interrupt source in the
- * ISTAT register. This register contains the value of 0x00 after a reset.
- */
-typedef union _hw_usb_inten
-{
- uint8_t U;
- struct _hw_usb_inten_bitfields
- {
- uint8_t USBRSTEN : 1; //!< [0] USBRST Interrupt Enable
- uint8_t ERROREN : 1; //!< [1] ERROR Interrupt Enable
- uint8_t SOFTOKEN : 1; //!< [2] SOFTOK Interrupt Enable
- uint8_t TOKDNEEN : 1; //!< [3] TOKDNE Interrupt Enable
- uint8_t SLEEPEN : 1; //!< [4] SLEEP Interrupt Enable
- uint8_t RESUMEEN : 1; //!< [5] RESUME Interrupt Enable
- uint8_t ATTACHEN : 1; //!< [6] ATTACH Interrupt Enable
- uint8_t STALLEN : 1; //!< [7] STALL Interrupt Enable
- } B;
-} hw_usb_inten_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_INTEN register
- */
-//@{
-#define HW_USB_INTEN_ADDR (REGS_USB_BASE + 0x84U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_INTEN (*(__IO hw_usb_inten_t *) HW_USB_INTEN_ADDR)
-#define HW_USB_INTEN_RD() (HW_USB_INTEN.U)
-#define HW_USB_INTEN_WR(v) (HW_USB_INTEN.U = (v))
-#define HW_USB_INTEN_SET(v) (HW_USB_INTEN_WR(HW_USB_INTEN_RD() | (v)))
-#define HW_USB_INTEN_CLR(v) (HW_USB_INTEN_WR(HW_USB_INTEN_RD() & ~(v)))
-#define HW_USB_INTEN_TOG(v) (HW_USB_INTEN_WR(HW_USB_INTEN_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_INTEN bitfields
- */
-
-/*!
- * @name Register USB_INTEN, field USBRSTEN[0] (RW)
- *
- * Values:
- * - 0 - Disables the USBRST interrupt.
- * - 1 - Enables the USBRST interrupt.
- */
-//@{
-#define BP_USB_INTEN_USBRSTEN (0U) //!< Bit position for USB_INTEN_USBRSTEN.
-#define BM_USB_INTEN_USBRSTEN (0x01U) //!< Bit mask for USB_INTEN_USBRSTEN.
-#define BS_USB_INTEN_USBRSTEN (1U) //!< Bit field size in bits for USB_INTEN_USBRSTEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_INTEN_USBRSTEN field.
-#define BR_USB_INTEN_USBRSTEN (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_USBRSTEN))
-#endif
-
-//! @brief Format value for bitfield USB_INTEN_USBRSTEN.
-#define BF_USB_INTEN_USBRSTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_INTEN_USBRSTEN), uint8_t) & BM_USB_INTEN_USBRSTEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the USBRSTEN field to a new value.
-#define BW_USB_INTEN_USBRSTEN(v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_USBRSTEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_INTEN, field ERROREN[1] (RW)
- *
- * Values:
- * - 0 - Disables the ERROR interrupt.
- * - 1 - Enables the ERROR interrupt.
- */
-//@{
-#define BP_USB_INTEN_ERROREN (1U) //!< Bit position for USB_INTEN_ERROREN.
-#define BM_USB_INTEN_ERROREN (0x02U) //!< Bit mask for USB_INTEN_ERROREN.
-#define BS_USB_INTEN_ERROREN (1U) //!< Bit field size in bits for USB_INTEN_ERROREN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_INTEN_ERROREN field.
-#define BR_USB_INTEN_ERROREN (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_ERROREN))
-#endif
-
-//! @brief Format value for bitfield USB_INTEN_ERROREN.
-#define BF_USB_INTEN_ERROREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_INTEN_ERROREN), uint8_t) & BM_USB_INTEN_ERROREN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ERROREN field to a new value.
-#define BW_USB_INTEN_ERROREN(v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_ERROREN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_INTEN, field SOFTOKEN[2] (RW)
- *
- * Values:
- * - 0 - Disbles the SOFTOK interrupt.
- * - 1 - Enables the SOFTOK interrupt.
- */
-//@{
-#define BP_USB_INTEN_SOFTOKEN (2U) //!< Bit position for USB_INTEN_SOFTOKEN.
-#define BM_USB_INTEN_SOFTOKEN (0x04U) //!< Bit mask for USB_INTEN_SOFTOKEN.
-#define BS_USB_INTEN_SOFTOKEN (1U) //!< Bit field size in bits for USB_INTEN_SOFTOKEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_INTEN_SOFTOKEN field.
-#define BR_USB_INTEN_SOFTOKEN (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_SOFTOKEN))
-#endif
-
-//! @brief Format value for bitfield USB_INTEN_SOFTOKEN.
-#define BF_USB_INTEN_SOFTOKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_INTEN_SOFTOKEN), uint8_t) & BM_USB_INTEN_SOFTOKEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SOFTOKEN field to a new value.
-#define BW_USB_INTEN_SOFTOKEN(v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_SOFTOKEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_INTEN, field TOKDNEEN[3] (RW)
- *
- * Values:
- * - 0 - Disables the TOKDNE interrupt.
- * - 1 - Enables the TOKDNE interrupt.
- */
-//@{
-#define BP_USB_INTEN_TOKDNEEN (3U) //!< Bit position for USB_INTEN_TOKDNEEN.
-#define BM_USB_INTEN_TOKDNEEN (0x08U) //!< Bit mask for USB_INTEN_TOKDNEEN.
-#define BS_USB_INTEN_TOKDNEEN (1U) //!< Bit field size in bits for USB_INTEN_TOKDNEEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_INTEN_TOKDNEEN field.
-#define BR_USB_INTEN_TOKDNEEN (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_TOKDNEEN))
-#endif
-
-//! @brief Format value for bitfield USB_INTEN_TOKDNEEN.
-#define BF_USB_INTEN_TOKDNEEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_INTEN_TOKDNEEN), uint8_t) & BM_USB_INTEN_TOKDNEEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TOKDNEEN field to a new value.
-#define BW_USB_INTEN_TOKDNEEN(v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_TOKDNEEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_INTEN, field SLEEPEN[4] (RW)
- *
- * Values:
- * - 0 - Disables the SLEEP interrupt.
- * - 1 - Enables the SLEEP interrupt.
- */
-//@{
-#define BP_USB_INTEN_SLEEPEN (4U) //!< Bit position for USB_INTEN_SLEEPEN.
-#define BM_USB_INTEN_SLEEPEN (0x10U) //!< Bit mask for USB_INTEN_SLEEPEN.
-#define BS_USB_INTEN_SLEEPEN (1U) //!< Bit field size in bits for USB_INTEN_SLEEPEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_INTEN_SLEEPEN field.
-#define BR_USB_INTEN_SLEEPEN (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_SLEEPEN))
-#endif
-
-//! @brief Format value for bitfield USB_INTEN_SLEEPEN.
-#define BF_USB_INTEN_SLEEPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_INTEN_SLEEPEN), uint8_t) & BM_USB_INTEN_SLEEPEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SLEEPEN field to a new value.
-#define BW_USB_INTEN_SLEEPEN(v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_SLEEPEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_INTEN, field RESUMEEN[5] (RW)
- *
- * Values:
- * - 0 - Disables the RESUME interrupt.
- * - 1 - Enables the RESUME interrupt.
- */
-//@{
-#define BP_USB_INTEN_RESUMEEN (5U) //!< Bit position for USB_INTEN_RESUMEEN.
-#define BM_USB_INTEN_RESUMEEN (0x20U) //!< Bit mask for USB_INTEN_RESUMEEN.
-#define BS_USB_INTEN_RESUMEEN (1U) //!< Bit field size in bits for USB_INTEN_RESUMEEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_INTEN_RESUMEEN field.
-#define BR_USB_INTEN_RESUMEEN (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_RESUMEEN))
-#endif
-
-//! @brief Format value for bitfield USB_INTEN_RESUMEEN.
-#define BF_USB_INTEN_RESUMEEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_INTEN_RESUMEEN), uint8_t) & BM_USB_INTEN_RESUMEEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RESUMEEN field to a new value.
-#define BW_USB_INTEN_RESUMEEN(v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_RESUMEEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_INTEN, field ATTACHEN[6] (RW)
- *
- * Values:
- * - 0 - Disables the ATTACH interrupt.
- * - 1 - Enables the ATTACH interrupt.
- */
-//@{
-#define BP_USB_INTEN_ATTACHEN (6U) //!< Bit position for USB_INTEN_ATTACHEN.
-#define BM_USB_INTEN_ATTACHEN (0x40U) //!< Bit mask for USB_INTEN_ATTACHEN.
-#define BS_USB_INTEN_ATTACHEN (1U) //!< Bit field size in bits for USB_INTEN_ATTACHEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_INTEN_ATTACHEN field.
-#define BR_USB_INTEN_ATTACHEN (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_ATTACHEN))
-#endif
-
-//! @brief Format value for bitfield USB_INTEN_ATTACHEN.
-#define BF_USB_INTEN_ATTACHEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_INTEN_ATTACHEN), uint8_t) & BM_USB_INTEN_ATTACHEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ATTACHEN field to a new value.
-#define BW_USB_INTEN_ATTACHEN(v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_ATTACHEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_INTEN, field STALLEN[7] (RW)
- *
- * Values:
- * - 0 - Diasbles the STALL interrupt.
- * - 1 - Enables the STALL interrupt.
- */
-//@{
-#define BP_USB_INTEN_STALLEN (7U) //!< Bit position for USB_INTEN_STALLEN.
-#define BM_USB_INTEN_STALLEN (0x80U) //!< Bit mask for USB_INTEN_STALLEN.
-#define BS_USB_INTEN_STALLEN (1U) //!< Bit field size in bits for USB_INTEN_STALLEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_INTEN_STALLEN field.
-#define BR_USB_INTEN_STALLEN (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_STALLEN))
-#endif
-
-//! @brief Format value for bitfield USB_INTEN_STALLEN.
-#define BF_USB_INTEN_STALLEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_INTEN_STALLEN), uint8_t) & BM_USB_INTEN_STALLEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the STALLEN field to a new value.
-#define BW_USB_INTEN_STALLEN(v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_STALLEN) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_ERRSTAT - Error Interrupt Status register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_ERRSTAT - Error Interrupt Status register (RW)
- *
- * Reset value: 0x00U
- *
- * Contains enable bits for each of the error sources within the USB Module.
- * Each of these bits are qualified with their respective error enable bits. All
- * bits of this register are logically OR'd together and the result placed in the
- * ERROR bit of the ISTAT register. After an interrupt bit has been set it may only
- * be cleared by writing a one to the respective interrupt bit. Each bit is set
- * as soon as the error condition is detected. Therefore, the interrupt does not
- * typically correspond with the end of a token being processed. This register
- * contains the value of 0x00 after a reset.
- */
-typedef union _hw_usb_errstat
-{
- uint8_t U;
- struct _hw_usb_errstat_bitfields
- {
- uint8_t PIDERR : 1; //!< [0]
- uint8_t CRC5EOF : 1; //!< [1]
- uint8_t CRC16 : 1; //!< [2]
- uint8_t DFN8 : 1; //!< [3]
- uint8_t BTOERR : 1; //!< [4]
- uint8_t DMAERR : 1; //!< [5]
- uint8_t RESERVED0 : 1; //!< [6]
- uint8_t BTSERR : 1; //!< [7]
- } B;
-} hw_usb_errstat_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_ERRSTAT register
- */
-//@{
-#define HW_USB_ERRSTAT_ADDR (REGS_USB_BASE + 0x88U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_ERRSTAT (*(__IO hw_usb_errstat_t *) HW_USB_ERRSTAT_ADDR)
-#define HW_USB_ERRSTAT_RD() (HW_USB_ERRSTAT.U)
-#define HW_USB_ERRSTAT_WR(v) (HW_USB_ERRSTAT.U = (v))
-#define HW_USB_ERRSTAT_SET(v) (HW_USB_ERRSTAT_WR(HW_USB_ERRSTAT_RD() | (v)))
-#define HW_USB_ERRSTAT_CLR(v) (HW_USB_ERRSTAT_WR(HW_USB_ERRSTAT_RD() & ~(v)))
-#define HW_USB_ERRSTAT_TOG(v) (HW_USB_ERRSTAT_WR(HW_USB_ERRSTAT_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_ERRSTAT bitfields
- */
-
-/*!
- * @name Register USB_ERRSTAT, field PIDERR[0] (W1C)
- *
- * This bit is set when the PID check field fails.
- */
-//@{
-#define BP_USB_ERRSTAT_PIDERR (0U) //!< Bit position for USB_ERRSTAT_PIDERR.
-#define BM_USB_ERRSTAT_PIDERR (0x01U) //!< Bit mask for USB_ERRSTAT_PIDERR.
-#define BS_USB_ERRSTAT_PIDERR (1U) //!< Bit field size in bits for USB_ERRSTAT_PIDERR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ERRSTAT_PIDERR field.
-#define BR_USB_ERRSTAT_PIDERR (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_PIDERR))
-#endif
-
-//! @brief Format value for bitfield USB_ERRSTAT_PIDERR.
-#define BF_USB_ERRSTAT_PIDERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERRSTAT_PIDERR), uint8_t) & BM_USB_ERRSTAT_PIDERR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PIDERR field to a new value.
-#define BW_USB_ERRSTAT_PIDERR(v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_PIDERR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_ERRSTAT, field CRC5EOF[1] (W1C)
- *
- * This error interrupt has two functions. When the USB Module is operating in
- * peripheral mode (HOSTMODEEN=0), this interrupt detects CRC5 errors in the token
- * packets generated by the host. If set the token packet was rejected due to a
- * CRC5 error. When the USB Module is operating in host mode (HOSTMODEEN=1), this
- * interrupt detects End Of Frame (EOF) error conditions. This occurs when the
- * USB Module is transmitting or receiving data and the SOF counter reaches zero.
- * This interrupt is useful when developing USB packet scheduling software to
- * ensure that no USB transactions cross the start of the next frame.
- */
-//@{
-#define BP_USB_ERRSTAT_CRC5EOF (1U) //!< Bit position for USB_ERRSTAT_CRC5EOF.
-#define BM_USB_ERRSTAT_CRC5EOF (0x02U) //!< Bit mask for USB_ERRSTAT_CRC5EOF.
-#define BS_USB_ERRSTAT_CRC5EOF (1U) //!< Bit field size in bits for USB_ERRSTAT_CRC5EOF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ERRSTAT_CRC5EOF field.
-#define BR_USB_ERRSTAT_CRC5EOF (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_CRC5EOF))
-#endif
-
-//! @brief Format value for bitfield USB_ERRSTAT_CRC5EOF.
-#define BF_USB_ERRSTAT_CRC5EOF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERRSTAT_CRC5EOF), uint8_t) & BM_USB_ERRSTAT_CRC5EOF)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CRC5EOF field to a new value.
-#define BW_USB_ERRSTAT_CRC5EOF(v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_CRC5EOF) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_ERRSTAT, field CRC16[2] (W1C)
- *
- * This bit is set when a data packet is rejected due to a CRC16 error.
- */
-//@{
-#define BP_USB_ERRSTAT_CRC16 (2U) //!< Bit position for USB_ERRSTAT_CRC16.
-#define BM_USB_ERRSTAT_CRC16 (0x04U) //!< Bit mask for USB_ERRSTAT_CRC16.
-#define BS_USB_ERRSTAT_CRC16 (1U) //!< Bit field size in bits for USB_ERRSTAT_CRC16.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ERRSTAT_CRC16 field.
-#define BR_USB_ERRSTAT_CRC16 (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_CRC16))
-#endif
-
-//! @brief Format value for bitfield USB_ERRSTAT_CRC16.
-#define BF_USB_ERRSTAT_CRC16(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERRSTAT_CRC16), uint8_t) & BM_USB_ERRSTAT_CRC16)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CRC16 field to a new value.
-#define BW_USB_ERRSTAT_CRC16(v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_CRC16) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_ERRSTAT, field DFN8[3] (W1C)
- *
- * This bit is set if the data field received was not 8 bits in length. USB
- * Specification 1.0 requires that data fields be an integral number of bytes. If the
- * data field was not an integral number of bytes, this bit is set.
- */
-//@{
-#define BP_USB_ERRSTAT_DFN8 (3U) //!< Bit position for USB_ERRSTAT_DFN8.
-#define BM_USB_ERRSTAT_DFN8 (0x08U) //!< Bit mask for USB_ERRSTAT_DFN8.
-#define BS_USB_ERRSTAT_DFN8 (1U) //!< Bit field size in bits for USB_ERRSTAT_DFN8.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ERRSTAT_DFN8 field.
-#define BR_USB_ERRSTAT_DFN8 (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_DFN8))
-#endif
-
-//! @brief Format value for bitfield USB_ERRSTAT_DFN8.
-#define BF_USB_ERRSTAT_DFN8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERRSTAT_DFN8), uint8_t) & BM_USB_ERRSTAT_DFN8)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DFN8 field to a new value.
-#define BW_USB_ERRSTAT_DFN8(v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_DFN8) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_ERRSTAT, field BTOERR[4] (W1C)
- *
- * This bit is set when a bus turnaround timeout error occurs. The USB module
- * contains a bus turnaround timer that keeps track of the amount of time elapsed
- * between the token and data phases of a SETUP or OUT TOKEN or the data and
- * handshake phases of a IN TOKEN. If more than 16 bit times are counted from the
- * previous EOP before a transition from IDLE, a bus turnaround timeout error occurs.
- */
-//@{
-#define BP_USB_ERRSTAT_BTOERR (4U) //!< Bit position for USB_ERRSTAT_BTOERR.
-#define BM_USB_ERRSTAT_BTOERR (0x10U) //!< Bit mask for USB_ERRSTAT_BTOERR.
-#define BS_USB_ERRSTAT_BTOERR (1U) //!< Bit field size in bits for USB_ERRSTAT_BTOERR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ERRSTAT_BTOERR field.
-#define BR_USB_ERRSTAT_BTOERR (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_BTOERR))
-#endif
-
-//! @brief Format value for bitfield USB_ERRSTAT_BTOERR.
-#define BF_USB_ERRSTAT_BTOERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERRSTAT_BTOERR), uint8_t) & BM_USB_ERRSTAT_BTOERR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BTOERR field to a new value.
-#define BW_USB_ERRSTAT_BTOERR(v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_BTOERR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_ERRSTAT, field DMAERR[5] (W1C)
- *
- * This bit is set if the USB Module has requested a DMA access to read a new
- * BDT but has not been given the bus before it needs to receive or transmit data.
- * If processing a TX transfer this would cause a transmit data underflow
- * condition. If processing a RX transfer this would cause a receive data overflow
- * condition. This interrupt is useful when developing device arbitration hardware for
- * the microprocessor and the USB module to minimize bus request and bus grant
- * latency. This bit is also set if a data packet to or from the host is larger
- * than the buffer size allocated in the BDT. In this case the data packet is
- * truncated as it is put in buffer memory.
- */
-//@{
-#define BP_USB_ERRSTAT_DMAERR (5U) //!< Bit position for USB_ERRSTAT_DMAERR.
-#define BM_USB_ERRSTAT_DMAERR (0x20U) //!< Bit mask for USB_ERRSTAT_DMAERR.
-#define BS_USB_ERRSTAT_DMAERR (1U) //!< Bit field size in bits for USB_ERRSTAT_DMAERR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ERRSTAT_DMAERR field.
-#define BR_USB_ERRSTAT_DMAERR (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_DMAERR))
-#endif
-
-//! @brief Format value for bitfield USB_ERRSTAT_DMAERR.
-#define BF_USB_ERRSTAT_DMAERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERRSTAT_DMAERR), uint8_t) & BM_USB_ERRSTAT_DMAERR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DMAERR field to a new value.
-#define BW_USB_ERRSTAT_DMAERR(v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_DMAERR) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_ERRSTAT, field BTSERR[7] (W1C)
- *
- * This bit is set when a bit stuff error is detected. If set, the corresponding
- * packet is rejected due to the error.
- */
-//@{
-#define BP_USB_ERRSTAT_BTSERR (7U) //!< Bit position for USB_ERRSTAT_BTSERR.
-#define BM_USB_ERRSTAT_BTSERR (0x80U) //!< Bit mask for USB_ERRSTAT_BTSERR.
-#define BS_USB_ERRSTAT_BTSERR (1U) //!< Bit field size in bits for USB_ERRSTAT_BTSERR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ERRSTAT_BTSERR field.
-#define BR_USB_ERRSTAT_BTSERR (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_BTSERR))
-#endif
-
-//! @brief Format value for bitfield USB_ERRSTAT_BTSERR.
-#define BF_USB_ERRSTAT_BTSERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERRSTAT_BTSERR), uint8_t) & BM_USB_ERRSTAT_BTSERR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BTSERR field to a new value.
-#define BW_USB_ERRSTAT_BTSERR(v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_BTSERR) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_ERREN - Error Interrupt Enable register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_ERREN - Error Interrupt Enable register (RW)
- *
- * Reset value: 0x00U
- *
- * Contains enable bits for each of the error interrupt sources within the USB
- * module. Setting any of these bits enables the respective interrupt source in
- * ERRSTAT. Each bit is set as soon as the error condition is detected. Therefore,
- * the interrupt does not typically correspond with the end of a token being
- * processed. This register contains the value of 0x00 after a reset.
- */
-typedef union _hw_usb_erren
-{
- uint8_t U;
- struct _hw_usb_erren_bitfields
- {
- uint8_t PIDERREN : 1; //!< [0] PIDERR Interrupt Enable
- uint8_t CRC5EOFEN : 1; //!< [1] CRC5/EOF Interrupt Enable
- uint8_t CRC16EN : 1; //!< [2] CRC16 Interrupt Enable
- uint8_t DFN8EN : 1; //!< [3] DFN8 Interrupt Enable
- uint8_t BTOERREN : 1; //!< [4] BTOERR Interrupt Enable
- uint8_t DMAERREN : 1; //!< [5] DMAERR Interrupt Enable
- uint8_t RESERVED0 : 1; //!< [6]
- uint8_t BTSERREN : 1; //!< [7] BTSERR Interrupt Enable
- } B;
-} hw_usb_erren_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_ERREN register
- */
-//@{
-#define HW_USB_ERREN_ADDR (REGS_USB_BASE + 0x8CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_ERREN (*(__IO hw_usb_erren_t *) HW_USB_ERREN_ADDR)
-#define HW_USB_ERREN_RD() (HW_USB_ERREN.U)
-#define HW_USB_ERREN_WR(v) (HW_USB_ERREN.U = (v))
-#define HW_USB_ERREN_SET(v) (HW_USB_ERREN_WR(HW_USB_ERREN_RD() | (v)))
-#define HW_USB_ERREN_CLR(v) (HW_USB_ERREN_WR(HW_USB_ERREN_RD() & ~(v)))
-#define HW_USB_ERREN_TOG(v) (HW_USB_ERREN_WR(HW_USB_ERREN_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_ERREN bitfields
- */
-
-/*!
- * @name Register USB_ERREN, field PIDERREN[0] (RW)
- *
- * Values:
- * - 0 - Disables the PIDERR interrupt.
- * - 1 - Enters the PIDERR interrupt.
- */
-//@{
-#define BP_USB_ERREN_PIDERREN (0U) //!< Bit position for USB_ERREN_PIDERREN.
-#define BM_USB_ERREN_PIDERREN (0x01U) //!< Bit mask for USB_ERREN_PIDERREN.
-#define BS_USB_ERREN_PIDERREN (1U) //!< Bit field size in bits for USB_ERREN_PIDERREN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ERREN_PIDERREN field.
-#define BR_USB_ERREN_PIDERREN (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_PIDERREN))
-#endif
-
-//! @brief Format value for bitfield USB_ERREN_PIDERREN.
-#define BF_USB_ERREN_PIDERREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERREN_PIDERREN), uint8_t) & BM_USB_ERREN_PIDERREN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PIDERREN field to a new value.
-#define BW_USB_ERREN_PIDERREN(v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_PIDERREN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_ERREN, field CRC5EOFEN[1] (RW)
- *
- * Values:
- * - 0 - Disables the CRC5/EOF interrupt.
- * - 1 - Enables the CRC5/EOF interrupt.
- */
-//@{
-#define BP_USB_ERREN_CRC5EOFEN (1U) //!< Bit position for USB_ERREN_CRC5EOFEN.
-#define BM_USB_ERREN_CRC5EOFEN (0x02U) //!< Bit mask for USB_ERREN_CRC5EOFEN.
-#define BS_USB_ERREN_CRC5EOFEN (1U) //!< Bit field size in bits for USB_ERREN_CRC5EOFEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ERREN_CRC5EOFEN field.
-#define BR_USB_ERREN_CRC5EOFEN (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_CRC5EOFEN))
-#endif
-
-//! @brief Format value for bitfield USB_ERREN_CRC5EOFEN.
-#define BF_USB_ERREN_CRC5EOFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERREN_CRC5EOFEN), uint8_t) & BM_USB_ERREN_CRC5EOFEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CRC5EOFEN field to a new value.
-#define BW_USB_ERREN_CRC5EOFEN(v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_CRC5EOFEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_ERREN, field CRC16EN[2] (RW)
- *
- * Values:
- * - 0 - Disables the CRC16 interrupt.
- * - 1 - Enables the CRC16 interrupt.
- */
-//@{
-#define BP_USB_ERREN_CRC16EN (2U) //!< Bit position for USB_ERREN_CRC16EN.
-#define BM_USB_ERREN_CRC16EN (0x04U) //!< Bit mask for USB_ERREN_CRC16EN.
-#define BS_USB_ERREN_CRC16EN (1U) //!< Bit field size in bits for USB_ERREN_CRC16EN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ERREN_CRC16EN field.
-#define BR_USB_ERREN_CRC16EN (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_CRC16EN))
-#endif
-
-//! @brief Format value for bitfield USB_ERREN_CRC16EN.
-#define BF_USB_ERREN_CRC16EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERREN_CRC16EN), uint8_t) & BM_USB_ERREN_CRC16EN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CRC16EN field to a new value.
-#define BW_USB_ERREN_CRC16EN(v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_CRC16EN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_ERREN, field DFN8EN[3] (RW)
- *
- * Values:
- * - 0 - Disables the DFN8 interrupt.
- * - 1 - Enables the DFN8 interrupt.
- */
-//@{
-#define BP_USB_ERREN_DFN8EN (3U) //!< Bit position for USB_ERREN_DFN8EN.
-#define BM_USB_ERREN_DFN8EN (0x08U) //!< Bit mask for USB_ERREN_DFN8EN.
-#define BS_USB_ERREN_DFN8EN (1U) //!< Bit field size in bits for USB_ERREN_DFN8EN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ERREN_DFN8EN field.
-#define BR_USB_ERREN_DFN8EN (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_DFN8EN))
-#endif
-
-//! @brief Format value for bitfield USB_ERREN_DFN8EN.
-#define BF_USB_ERREN_DFN8EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERREN_DFN8EN), uint8_t) & BM_USB_ERREN_DFN8EN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DFN8EN field to a new value.
-#define BW_USB_ERREN_DFN8EN(v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_DFN8EN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_ERREN, field BTOERREN[4] (RW)
- *
- * Values:
- * - 0 - Disables the BTOERR interrupt.
- * - 1 - Enables the BTOERR interrupt.
- */
-//@{
-#define BP_USB_ERREN_BTOERREN (4U) //!< Bit position for USB_ERREN_BTOERREN.
-#define BM_USB_ERREN_BTOERREN (0x10U) //!< Bit mask for USB_ERREN_BTOERREN.
-#define BS_USB_ERREN_BTOERREN (1U) //!< Bit field size in bits for USB_ERREN_BTOERREN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ERREN_BTOERREN field.
-#define BR_USB_ERREN_BTOERREN (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_BTOERREN))
-#endif
-
-//! @brief Format value for bitfield USB_ERREN_BTOERREN.
-#define BF_USB_ERREN_BTOERREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERREN_BTOERREN), uint8_t) & BM_USB_ERREN_BTOERREN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BTOERREN field to a new value.
-#define BW_USB_ERREN_BTOERREN(v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_BTOERREN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_ERREN, field DMAERREN[5] (RW)
- *
- * Values:
- * - 0 - Disables the DMAERR interrupt.
- * - 1 - Enables the DMAERR interrupt.
- */
-//@{
-#define BP_USB_ERREN_DMAERREN (5U) //!< Bit position for USB_ERREN_DMAERREN.
-#define BM_USB_ERREN_DMAERREN (0x20U) //!< Bit mask for USB_ERREN_DMAERREN.
-#define BS_USB_ERREN_DMAERREN (1U) //!< Bit field size in bits for USB_ERREN_DMAERREN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ERREN_DMAERREN field.
-#define BR_USB_ERREN_DMAERREN (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_DMAERREN))
-#endif
-
-//! @brief Format value for bitfield USB_ERREN_DMAERREN.
-#define BF_USB_ERREN_DMAERREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERREN_DMAERREN), uint8_t) & BM_USB_ERREN_DMAERREN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DMAERREN field to a new value.
-#define BW_USB_ERREN_DMAERREN(v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_DMAERREN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_ERREN, field BTSERREN[7] (RW)
- *
- * Values:
- * - 0 - Disables the BTSERR interrupt.
- * - 1 - Enables the BTSERR interrupt.
- */
-//@{
-#define BP_USB_ERREN_BTSERREN (7U) //!< Bit position for USB_ERREN_BTSERREN.
-#define BM_USB_ERREN_BTSERREN (0x80U) //!< Bit mask for USB_ERREN_BTSERREN.
-#define BS_USB_ERREN_BTSERREN (1U) //!< Bit field size in bits for USB_ERREN_BTSERREN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ERREN_BTSERREN field.
-#define BR_USB_ERREN_BTSERREN (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_BTSERREN))
-#endif
-
-//! @brief Format value for bitfield USB_ERREN_BTSERREN.
-#define BF_USB_ERREN_BTSERREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERREN_BTSERREN), uint8_t) & BM_USB_ERREN_BTSERREN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BTSERREN field to a new value.
-#define BW_USB_ERREN_BTSERREN(v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_BTSERREN) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_STAT - Status register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_STAT - Status register (RO)
- *
- * Reset value: 0x00U
- *
- * Reports the transaction status within the USB module. When the processor's
- * interrupt controller has received a TOKDNE, interrupt the Status Register must
- * be read to determine the status of the previous endpoint communication. The
- * data in the status register is valid when TOKDNE interrupt is asserted. The
- * Status register is actually a read window into a status FIFO maintained by the USB
- * module. When the USB module uses a BD, it updates the Status register. If
- * another USB transaction is performed before the TOKDNE interrupt is serviced, the
- * USB module stores the status of the next transaction in the STAT FIFO. Thus
- * STAT is actually a four byte FIFO that allows the processor core to process one
- * transaction while the SIE is processing the next transaction. Clearing the
- * TOKDNE bit in the ISTAT register causes the SIE to update STAT with the contents
- * of the next STAT value. If the data in the STAT holding register is valid, the
- * SIE immediately reasserts to TOKDNE interrupt.
- */
-typedef union _hw_usb_stat
-{
- uint8_t U;
- struct _hw_usb_stat_bitfields
- {
- uint8_t RESERVED0 : 2; //!< [1:0]
- uint8_t ODD : 1; //!< [2]
- uint8_t TX : 1; //!< [3] Transmit Indicator
- uint8_t ENDP : 4; //!< [7:4]
- } B;
-} hw_usb_stat_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_STAT register
- */
-//@{
-#define HW_USB_STAT_ADDR (REGS_USB_BASE + 0x90U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_STAT (*(__I hw_usb_stat_t *) HW_USB_STAT_ADDR)
-#define HW_USB_STAT_RD() (HW_USB_STAT.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_STAT bitfields
- */
-
-/*!
- * @name Register USB_STAT, field ODD[2] (RO)
- *
- * This bit is set if the last buffer descriptor updated was in the odd bank of
- * the BDT.
- */
-//@{
-#define BP_USB_STAT_ODD (2U) //!< Bit position for USB_STAT_ODD.
-#define BM_USB_STAT_ODD (0x04U) //!< Bit mask for USB_STAT_ODD.
-#define BS_USB_STAT_ODD (1U) //!< Bit field size in bits for USB_STAT_ODD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_STAT_ODD field.
-#define BR_USB_STAT_ODD (BITBAND_ACCESS8(HW_USB_STAT_ADDR, BP_USB_STAT_ODD))
-#endif
-//@}
-
-/*!
- * @name Register USB_STAT, field TX[3] (RO)
- *
- * Values:
- * - 0 - The most recent transaction was a receive operation.
- * - 1 - The most recent transaction was a transmit operation.
- */
-//@{
-#define BP_USB_STAT_TX (3U) //!< Bit position for USB_STAT_TX.
-#define BM_USB_STAT_TX (0x08U) //!< Bit mask for USB_STAT_TX.
-#define BS_USB_STAT_TX (1U) //!< Bit field size in bits for USB_STAT_TX.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_STAT_TX field.
-#define BR_USB_STAT_TX (BITBAND_ACCESS8(HW_USB_STAT_ADDR, BP_USB_STAT_TX))
-#endif
-//@}
-
-/*!
- * @name Register USB_STAT, field ENDP[7:4] (RO)
- *
- * This four-bit field encodes the endpoint address that received or transmitted
- * the previous token. This allows the processor core to determine the BDT entry
- * that was updated by the last USB transaction.
- */
-//@{
-#define BP_USB_STAT_ENDP (4U) //!< Bit position for USB_STAT_ENDP.
-#define BM_USB_STAT_ENDP (0xF0U) //!< Bit mask for USB_STAT_ENDP.
-#define BS_USB_STAT_ENDP (4U) //!< Bit field size in bits for USB_STAT_ENDP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_STAT_ENDP field.
-#define BR_USB_STAT_ENDP (HW_USB_STAT.B.ENDP)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_CTL - Control register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_CTL - Control register (RW)
- *
- * Reset value: 0x00U
- *
- * Provides various control and configuration information for the USB module.
- */
-typedef union _hw_usb_ctl
-{
- uint8_t U;
- struct _hw_usb_ctl_bitfields
- {
- uint8_t USBENSOFEN : 1; //!< [0] USB Enable
- uint8_t ODDRST : 1; //!< [1]
- uint8_t RESUME : 1; //!< [2]
- uint8_t HOSTMODEEN : 1; //!< [3]
- uint8_t RESET : 1; //!< [4]
- uint8_t TXSUSPENDTOKENBUSY : 1; //!< [5]
- uint8_t SE0 : 1; //!< [6] Live USB Single Ended Zero signal
- uint8_t JSTATE : 1; //!< [7] Live USB differential receiver JSTATE
- //! signal
- } B;
-} hw_usb_ctl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_CTL register
- */
-//@{
-#define HW_USB_CTL_ADDR (REGS_USB_BASE + 0x94U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_CTL (*(__IO hw_usb_ctl_t *) HW_USB_CTL_ADDR)
-#define HW_USB_CTL_RD() (HW_USB_CTL.U)
-#define HW_USB_CTL_WR(v) (HW_USB_CTL.U = (v))
-#define HW_USB_CTL_SET(v) (HW_USB_CTL_WR(HW_USB_CTL_RD() | (v)))
-#define HW_USB_CTL_CLR(v) (HW_USB_CTL_WR(HW_USB_CTL_RD() & ~(v)))
-#define HW_USB_CTL_TOG(v) (HW_USB_CTL_WR(HW_USB_CTL_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_CTL bitfields
- */
-
-/*!
- * @name Register USB_CTL, field USBENSOFEN[0] (RW)
- *
- * Setting this bit enables the USB-FS to operate; clearing it disables the
- * USB-FS. Setting the bit causes the SIE to reset all of its ODD bits to the BDTs.
- * Therefore, setting this bit resets much of the logic in the SIE. When host mode
- * is enabled, clearing this bit causes the SIE to stop sending SOF tokens.
- *
- * Values:
- * - 0 - Disables the USB Module.
- * - 1 - Enables the USB Module.
- */
-//@{
-#define BP_USB_CTL_USBENSOFEN (0U) //!< Bit position for USB_CTL_USBENSOFEN.
-#define BM_USB_CTL_USBENSOFEN (0x01U) //!< Bit mask for USB_CTL_USBENSOFEN.
-#define BS_USB_CTL_USBENSOFEN (1U) //!< Bit field size in bits for USB_CTL_USBENSOFEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_CTL_USBENSOFEN field.
-#define BR_USB_CTL_USBENSOFEN (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_USBENSOFEN))
-#endif
-
-//! @brief Format value for bitfield USB_CTL_USBENSOFEN.
-#define BF_USB_CTL_USBENSOFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CTL_USBENSOFEN), uint8_t) & BM_USB_CTL_USBENSOFEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the USBENSOFEN field to a new value.
-#define BW_USB_CTL_USBENSOFEN(v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_USBENSOFEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_CTL, field ODDRST[1] (RW)
- *
- * Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0, which
- * then specifies the EVEN BDT bank.
- */
-//@{
-#define BP_USB_CTL_ODDRST (1U) //!< Bit position for USB_CTL_ODDRST.
-#define BM_USB_CTL_ODDRST (0x02U) //!< Bit mask for USB_CTL_ODDRST.
-#define BS_USB_CTL_ODDRST (1U) //!< Bit field size in bits for USB_CTL_ODDRST.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_CTL_ODDRST field.
-#define BR_USB_CTL_ODDRST (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_ODDRST))
-#endif
-
-//! @brief Format value for bitfield USB_CTL_ODDRST.
-#define BF_USB_CTL_ODDRST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CTL_ODDRST), uint8_t) & BM_USB_CTL_ODDRST)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ODDRST field to a new value.
-#define BW_USB_CTL_ODDRST(v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_ODDRST) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_CTL, field RESUME[2] (RW)
- *
- * When set to 1 this bit enables the USB Module to execute resume signaling.
- * This allows the USB Module to perform remote wake-up. Software must set RESUME
- * to 1 for the required amount of time and then clear it to 0. If the HOSTMODEEN
- * bit is set, the USB module appends a Low Speed End of Packet to the Resume
- * signaling when the RESUME bit is cleared. For more information on RESUME
- * signaling see Section 7.1.4.5 of the USB specification version 1.0.
- */
-//@{
-#define BP_USB_CTL_RESUME (2U) //!< Bit position for USB_CTL_RESUME.
-#define BM_USB_CTL_RESUME (0x04U) //!< Bit mask for USB_CTL_RESUME.
-#define BS_USB_CTL_RESUME (1U) //!< Bit field size in bits for USB_CTL_RESUME.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_CTL_RESUME field.
-#define BR_USB_CTL_RESUME (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_RESUME))
-#endif
-
-//! @brief Format value for bitfield USB_CTL_RESUME.
-#define BF_USB_CTL_RESUME(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CTL_RESUME), uint8_t) & BM_USB_CTL_RESUME)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RESUME field to a new value.
-#define BW_USB_CTL_RESUME(v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_RESUME) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_CTL, field HOSTMODEEN[3] (RW)
- *
- * When set to 1, this bit enables the USB Module to operate in Host mode. In
- * host mode, the USB module performs USB transactions under the programmed control
- * of the host processor.
- */
-//@{
-#define BP_USB_CTL_HOSTMODEEN (3U) //!< Bit position for USB_CTL_HOSTMODEEN.
-#define BM_USB_CTL_HOSTMODEEN (0x08U) //!< Bit mask for USB_CTL_HOSTMODEEN.
-#define BS_USB_CTL_HOSTMODEEN (1U) //!< Bit field size in bits for USB_CTL_HOSTMODEEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_CTL_HOSTMODEEN field.
-#define BR_USB_CTL_HOSTMODEEN (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_HOSTMODEEN))
-#endif
-
-//! @brief Format value for bitfield USB_CTL_HOSTMODEEN.
-#define BF_USB_CTL_HOSTMODEEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CTL_HOSTMODEEN), uint8_t) & BM_USB_CTL_HOSTMODEEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the HOSTMODEEN field to a new value.
-#define BW_USB_CTL_HOSTMODEEN(v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_HOSTMODEEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_CTL, field RESET[4] (RW)
- *
- * Setting this bit enables the USB Module to generate USB reset signaling. This
- * allows the USB Module to reset USB peripherals. This control signal is only
- * valid in Host mode (HOSTMODEEN=1). Software must set RESET to 1 for the
- * required amount of time and then clear it to 0 to end reset signaling. For more
- * information on reset signaling see Section 7.1.4.3 of the USB specification version
- * 1.0.
- */
-//@{
-#define BP_USB_CTL_RESET (4U) //!< Bit position for USB_CTL_RESET.
-#define BM_USB_CTL_RESET (0x10U) //!< Bit mask for USB_CTL_RESET.
-#define BS_USB_CTL_RESET (1U) //!< Bit field size in bits for USB_CTL_RESET.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_CTL_RESET field.
-#define BR_USB_CTL_RESET (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_RESET))
-#endif
-
-//! @brief Format value for bitfield USB_CTL_RESET.
-#define BF_USB_CTL_RESET(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CTL_RESET), uint8_t) & BM_USB_CTL_RESET)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RESET field to a new value.
-#define BW_USB_CTL_RESET(v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_RESET) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_CTL, field TXSUSPENDTOKENBUSY[5] (RW)
- *
- * In Host mode, TOKEN_BUSY is set when the USB module is busy executing a USB
- * token. Software must not write more token commands to the Token Register when
- * TOKEN_BUSY is set. Software should check this field before writing any tokens
- * to the Token Register to ensure that token commands are not lost. In Target
- * mode, TXD_SUSPEND is set when the SIE has disabled packet transmission and
- * reception. Clearing this bit allows the SIE to continue token processing. This bit
- * is set by the SIE when a SETUP Token is received allowing software to dequeue
- * any pending packet transactions in the BDT before resuming token processing.
- */
-//@{
-#define BP_USB_CTL_TXSUSPENDTOKENBUSY (5U) //!< Bit position for USB_CTL_TXSUSPENDTOKENBUSY.
-#define BM_USB_CTL_TXSUSPENDTOKENBUSY (0x20U) //!< Bit mask for USB_CTL_TXSUSPENDTOKENBUSY.
-#define BS_USB_CTL_TXSUSPENDTOKENBUSY (1U) //!< Bit field size in bits for USB_CTL_TXSUSPENDTOKENBUSY.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_CTL_TXSUSPENDTOKENBUSY field.
-#define BR_USB_CTL_TXSUSPENDTOKENBUSY (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_TXSUSPENDTOKENBUSY))
-#endif
-
-//! @brief Format value for bitfield USB_CTL_TXSUSPENDTOKENBUSY.
-#define BF_USB_CTL_TXSUSPENDTOKENBUSY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CTL_TXSUSPENDTOKENBUSY), uint8_t) & BM_USB_CTL_TXSUSPENDTOKENBUSY)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TXSUSPENDTOKENBUSY field to a new value.
-#define BW_USB_CTL_TXSUSPENDTOKENBUSY(v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_TXSUSPENDTOKENBUSY) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_CTL, field SE0[6] (RW)
- */
-//@{
-#define BP_USB_CTL_SE0 (6U) //!< Bit position for USB_CTL_SE0.
-#define BM_USB_CTL_SE0 (0x40U) //!< Bit mask for USB_CTL_SE0.
-#define BS_USB_CTL_SE0 (1U) //!< Bit field size in bits for USB_CTL_SE0.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_CTL_SE0 field.
-#define BR_USB_CTL_SE0 (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_SE0))
-#endif
-
-//! @brief Format value for bitfield USB_CTL_SE0.
-#define BF_USB_CTL_SE0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CTL_SE0), uint8_t) & BM_USB_CTL_SE0)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SE0 field to a new value.
-#define BW_USB_CTL_SE0(v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_SE0) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_CTL, field JSTATE[7] (RW)
- *
- * The polarity of this signal is affected by the current state of LSEN .
- */
-//@{
-#define BP_USB_CTL_JSTATE (7U) //!< Bit position for USB_CTL_JSTATE.
-#define BM_USB_CTL_JSTATE (0x80U) //!< Bit mask for USB_CTL_JSTATE.
-#define BS_USB_CTL_JSTATE (1U) //!< Bit field size in bits for USB_CTL_JSTATE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_CTL_JSTATE field.
-#define BR_USB_CTL_JSTATE (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_JSTATE))
-#endif
-
-//! @brief Format value for bitfield USB_CTL_JSTATE.
-#define BF_USB_CTL_JSTATE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CTL_JSTATE), uint8_t) & BM_USB_CTL_JSTATE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the JSTATE field to a new value.
-#define BW_USB_CTL_JSTATE(v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_JSTATE) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_ADDR - Address register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_ADDR - Address register (RW)
- *
- * Reset value: 0x00U
- *
- * Holds the unique USB address that the USB module decodes when in Peripheral
- * mode (HOSTMODEEN=0). When operating in Host mode (HOSTMODEEN=1) the USB module
- * transmits this address with a TOKEN packet. This enables the USB module to
- * uniquely address any USB peripheral. In either mode, CTL[USBENSOFEN] must be 1.
- * The Address register is reset to 0x00 after the reset input becomes active or
- * the USB module decodes a USB reset signal. This action initializes the Address
- * register to decode address 0x00 as required by the USB specification.
- */
-typedef union _hw_usb_addr
-{
- uint8_t U;
- struct _hw_usb_addr_bitfields
- {
- uint8_t ADDR : 7; //!< [6:0] USB Address
- uint8_t LSEN : 1; //!< [7] Low Speed Enable bit
- } B;
-} hw_usb_addr_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_ADDR register
- */
-//@{
-#define HW_USB_ADDR_ADDR (REGS_USB_BASE + 0x98U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_ADDR (*(__IO hw_usb_addr_t *) HW_USB_ADDR_ADDR)
-#define HW_USB_ADDR_RD() (HW_USB_ADDR.U)
-#define HW_USB_ADDR_WR(v) (HW_USB_ADDR.U = (v))
-#define HW_USB_ADDR_SET(v) (HW_USB_ADDR_WR(HW_USB_ADDR_RD() | (v)))
-#define HW_USB_ADDR_CLR(v) (HW_USB_ADDR_WR(HW_USB_ADDR_RD() & ~(v)))
-#define HW_USB_ADDR_TOG(v) (HW_USB_ADDR_WR(HW_USB_ADDR_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_ADDR bitfields
- */
-
-/*!
- * @name Register USB_ADDR, field ADDR[6:0] (RW)
- *
- * Defines the USB address that the USB module decodes in peripheral mode, or
- * transmits when in host mode.
- */
-//@{
-#define BP_USB_ADDR_ADDR (0U) //!< Bit position for USB_ADDR_ADDR.
-#define BM_USB_ADDR_ADDR (0x7FU) //!< Bit mask for USB_ADDR_ADDR.
-#define BS_USB_ADDR_ADDR (7U) //!< Bit field size in bits for USB_ADDR_ADDR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ADDR_ADDR field.
-#define BR_USB_ADDR_ADDR (HW_USB_ADDR.B.ADDR)
-#endif
-
-//! @brief Format value for bitfield USB_ADDR_ADDR.
-#define BF_USB_ADDR_ADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ADDR_ADDR), uint8_t) & BM_USB_ADDR_ADDR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ADDR field to a new value.
-#define BW_USB_ADDR_ADDR(v) (HW_USB_ADDR_WR((HW_USB_ADDR_RD() & ~BM_USB_ADDR_ADDR) | BF_USB_ADDR_ADDR(v)))
-#endif
-//@}
-
-/*!
- * @name Register USB_ADDR, field LSEN[7] (RW)
- *
- * Informs the USB module that the next token command written to the token
- * register must be performed at low speed. This enables the USB module to perform the
- * necessary preamble required for low-speed data transmissions.
- */
-//@{
-#define BP_USB_ADDR_LSEN (7U) //!< Bit position for USB_ADDR_LSEN.
-#define BM_USB_ADDR_LSEN (0x80U) //!< Bit mask for USB_ADDR_LSEN.
-#define BS_USB_ADDR_LSEN (1U) //!< Bit field size in bits for USB_ADDR_LSEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ADDR_LSEN field.
-#define BR_USB_ADDR_LSEN (BITBAND_ACCESS8(HW_USB_ADDR_ADDR, BP_USB_ADDR_LSEN))
-#endif
-
-//! @brief Format value for bitfield USB_ADDR_LSEN.
-#define BF_USB_ADDR_LSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ADDR_LSEN), uint8_t) & BM_USB_ADDR_LSEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the LSEN field to a new value.
-#define BW_USB_ADDR_LSEN(v) (BITBAND_ACCESS8(HW_USB_ADDR_ADDR, BP_USB_ADDR_LSEN) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_BDTPAGE1 - BDT Page register 1
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_BDTPAGE1 - BDT Page register 1 (RW)
- *
- * Reset value: 0x00U
- *
- * Provides address bits 15 through 9 of the base address where the current
- * Buffer Descriptor Table (BDT) resides in system memory. See Buffer Descriptor
- * Table. The 32-bit BDT Base Address is always aligned on 512-byte boundaries, so
- * bits 8 through 0 of the base address are always zero.
- */
-typedef union _hw_usb_bdtpage1
-{
- uint8_t U;
- struct _hw_usb_bdtpage1_bitfields
- {
- uint8_t RESERVED0 : 1; //!< [0]
- uint8_t BDTBA : 7; //!< [7:1]
- } B;
-} hw_usb_bdtpage1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_BDTPAGE1 register
- */
-//@{
-#define HW_USB_BDTPAGE1_ADDR (REGS_USB_BASE + 0x9CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_BDTPAGE1 (*(__IO hw_usb_bdtpage1_t *) HW_USB_BDTPAGE1_ADDR)
-#define HW_USB_BDTPAGE1_RD() (HW_USB_BDTPAGE1.U)
-#define HW_USB_BDTPAGE1_WR(v) (HW_USB_BDTPAGE1.U = (v))
-#define HW_USB_BDTPAGE1_SET(v) (HW_USB_BDTPAGE1_WR(HW_USB_BDTPAGE1_RD() | (v)))
-#define HW_USB_BDTPAGE1_CLR(v) (HW_USB_BDTPAGE1_WR(HW_USB_BDTPAGE1_RD() & ~(v)))
-#define HW_USB_BDTPAGE1_TOG(v) (HW_USB_BDTPAGE1_WR(HW_USB_BDTPAGE1_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_BDTPAGE1 bitfields
- */
-
-/*!
- * @name Register USB_BDTPAGE1, field BDTBA[7:1] (RW)
- *
- * Provides address bits 15 through 9 of the BDT base address.
- */
-//@{
-#define BP_USB_BDTPAGE1_BDTBA (1U) //!< Bit position for USB_BDTPAGE1_BDTBA.
-#define BM_USB_BDTPAGE1_BDTBA (0xFEU) //!< Bit mask for USB_BDTPAGE1_BDTBA.
-#define BS_USB_BDTPAGE1_BDTBA (7U) //!< Bit field size in bits for USB_BDTPAGE1_BDTBA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_BDTPAGE1_BDTBA field.
-#define BR_USB_BDTPAGE1_BDTBA (HW_USB_BDTPAGE1.B.BDTBA)
-#endif
-
-//! @brief Format value for bitfield USB_BDTPAGE1_BDTBA.
-#define BF_USB_BDTPAGE1_BDTBA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_BDTPAGE1_BDTBA), uint8_t) & BM_USB_BDTPAGE1_BDTBA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BDTBA field to a new value.
-#define BW_USB_BDTPAGE1_BDTBA(v) (HW_USB_BDTPAGE1_WR((HW_USB_BDTPAGE1_RD() & ~BM_USB_BDTPAGE1_BDTBA) | BF_USB_BDTPAGE1_BDTBA(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_FRMNUML - Frame Number register Low
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_FRMNUML - Frame Number register Low (RW)
- *
- * Reset value: 0x00U
- *
- * The Frame Number registers (low and high) contain the 11-bit frame number.
- * These registers are updated with the current frame number whenever a SOF TOKEN
- * is received.
- */
-typedef union _hw_usb_frmnuml
-{
- uint8_t U;
- struct _hw_usb_frmnuml_bitfields
- {
- uint8_t FRM : 8; //!< [7:0]
- } B;
-} hw_usb_frmnuml_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_FRMNUML register
- */
-//@{
-#define HW_USB_FRMNUML_ADDR (REGS_USB_BASE + 0xA0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_FRMNUML (*(__IO hw_usb_frmnuml_t *) HW_USB_FRMNUML_ADDR)
-#define HW_USB_FRMNUML_RD() (HW_USB_FRMNUML.U)
-#define HW_USB_FRMNUML_WR(v) (HW_USB_FRMNUML.U = (v))
-#define HW_USB_FRMNUML_SET(v) (HW_USB_FRMNUML_WR(HW_USB_FRMNUML_RD() | (v)))
-#define HW_USB_FRMNUML_CLR(v) (HW_USB_FRMNUML_WR(HW_USB_FRMNUML_RD() & ~(v)))
-#define HW_USB_FRMNUML_TOG(v) (HW_USB_FRMNUML_WR(HW_USB_FRMNUML_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_FRMNUML bitfields
- */
-
-/*!
- * @name Register USB_FRMNUML, field FRM[7:0] (RW)
- *
- * This 8-bit field and the 3-bit field in the Frame Number Register High are
- * used to compute the address where the current Buffer Descriptor Table (BDT)
- * resides in system memory.
- */
-//@{
-#define BP_USB_FRMNUML_FRM (0U) //!< Bit position for USB_FRMNUML_FRM.
-#define BM_USB_FRMNUML_FRM (0xFFU) //!< Bit mask for USB_FRMNUML_FRM.
-#define BS_USB_FRMNUML_FRM (8U) //!< Bit field size in bits for USB_FRMNUML_FRM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_FRMNUML_FRM field.
-#define BR_USB_FRMNUML_FRM (HW_USB_FRMNUML.U)
-#endif
-
-//! @brief Format value for bitfield USB_FRMNUML_FRM.
-#define BF_USB_FRMNUML_FRM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_FRMNUML_FRM), uint8_t) & BM_USB_FRMNUML_FRM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FRM field to a new value.
-#define BW_USB_FRMNUML_FRM(v) (HW_USB_FRMNUML_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_FRMNUMH - Frame Number register High
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_FRMNUMH - Frame Number register High (RW)
- *
- * Reset value: 0x00U
- *
- * The Frame Number registers (low and high) contain the 11-bit frame number.
- * These registers are updated with the current frame number whenever a SOF TOKEN
- * is received.
- */
-typedef union _hw_usb_frmnumh
-{
- uint8_t U;
- struct _hw_usb_frmnumh_bitfields
- {
- uint8_t FRM : 3; //!< [2:0]
- uint8_t RESERVED0 : 5; //!< [7:3]
- } B;
-} hw_usb_frmnumh_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_FRMNUMH register
- */
-//@{
-#define HW_USB_FRMNUMH_ADDR (REGS_USB_BASE + 0xA4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_FRMNUMH (*(__IO hw_usb_frmnumh_t *) HW_USB_FRMNUMH_ADDR)
-#define HW_USB_FRMNUMH_RD() (HW_USB_FRMNUMH.U)
-#define HW_USB_FRMNUMH_WR(v) (HW_USB_FRMNUMH.U = (v))
-#define HW_USB_FRMNUMH_SET(v) (HW_USB_FRMNUMH_WR(HW_USB_FRMNUMH_RD() | (v)))
-#define HW_USB_FRMNUMH_CLR(v) (HW_USB_FRMNUMH_WR(HW_USB_FRMNUMH_RD() & ~(v)))
-#define HW_USB_FRMNUMH_TOG(v) (HW_USB_FRMNUMH_WR(HW_USB_FRMNUMH_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_FRMNUMH bitfields
- */
-
-/*!
- * @name Register USB_FRMNUMH, field FRM[2:0] (RW)
- *
- * This 3-bit field and the 8-bit field in the Frame Number Register Low are
- * used to compute the address where the current Buffer Descriptor Table (BDT)
- * resides in system memory.
- */
-//@{
-#define BP_USB_FRMNUMH_FRM (0U) //!< Bit position for USB_FRMNUMH_FRM.
-#define BM_USB_FRMNUMH_FRM (0x07U) //!< Bit mask for USB_FRMNUMH_FRM.
-#define BS_USB_FRMNUMH_FRM (3U) //!< Bit field size in bits for USB_FRMNUMH_FRM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_FRMNUMH_FRM field.
-#define BR_USB_FRMNUMH_FRM (HW_USB_FRMNUMH.B.FRM)
-#endif
-
-//! @brief Format value for bitfield USB_FRMNUMH_FRM.
-#define BF_USB_FRMNUMH_FRM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_FRMNUMH_FRM), uint8_t) & BM_USB_FRMNUMH_FRM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the FRM field to a new value.
-#define BW_USB_FRMNUMH_FRM(v) (HW_USB_FRMNUMH_WR((HW_USB_FRMNUMH_RD() & ~BM_USB_FRMNUMH_FRM) | BF_USB_FRMNUMH_FRM(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_TOKEN - Token register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_TOKEN - Token register (RW)
- *
- * Reset value: 0x00U
- *
- * Used to initiate USB transactions when in host mode (HOSTMODEEN=1). When the
- * software needs to execute a USB transaction to a peripheral, it writes the
- * TOKEN type and endpoint to this register. After this register has been written,
- * the USB module begins the specified USB transaction to the address contained in
- * the address register. The processor core must always check that the
- * TOKEN_BUSY bit in the control register is not 1 before writing to the Token Register.
- * This ensures that the token commands are not overwritten before they can be
- * executed. The address register and endpoint control register 0 are also used when
- * performing a token command and therefore must also be written before the
- * Token Register. The address register is used to select the USB peripheral address
- * transmitted by the token command. The endpoint control register determines the
- * handshake and retry policies used during the transfer.
- */
-typedef union _hw_usb_token
-{
- uint8_t U;
- struct _hw_usb_token_bitfields
- {
- uint8_t TOKENENDPT : 4; //!< [3:0]
- uint8_t TOKENPID : 4; //!< [7:4]
- } B;
-} hw_usb_token_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_TOKEN register
- */
-//@{
-#define HW_USB_TOKEN_ADDR (REGS_USB_BASE + 0xA8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_TOKEN (*(__IO hw_usb_token_t *) HW_USB_TOKEN_ADDR)
-#define HW_USB_TOKEN_RD() (HW_USB_TOKEN.U)
-#define HW_USB_TOKEN_WR(v) (HW_USB_TOKEN.U = (v))
-#define HW_USB_TOKEN_SET(v) (HW_USB_TOKEN_WR(HW_USB_TOKEN_RD() | (v)))
-#define HW_USB_TOKEN_CLR(v) (HW_USB_TOKEN_WR(HW_USB_TOKEN_RD() & ~(v)))
-#define HW_USB_TOKEN_TOG(v) (HW_USB_TOKEN_WR(HW_USB_TOKEN_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_TOKEN bitfields
- */
-
-/*!
- * @name Register USB_TOKEN, field TOKENENDPT[3:0] (RW)
- *
- * Holds the Endpoint address for the token command. The four bit value written
- * must be a valid endpoint.
- */
-//@{
-#define BP_USB_TOKEN_TOKENENDPT (0U) //!< Bit position for USB_TOKEN_TOKENENDPT.
-#define BM_USB_TOKEN_TOKENENDPT (0x0FU) //!< Bit mask for USB_TOKEN_TOKENENDPT.
-#define BS_USB_TOKEN_TOKENENDPT (4U) //!< Bit field size in bits for USB_TOKEN_TOKENENDPT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_TOKEN_TOKENENDPT field.
-#define BR_USB_TOKEN_TOKENENDPT (HW_USB_TOKEN.B.TOKENENDPT)
-#endif
-
-//! @brief Format value for bitfield USB_TOKEN_TOKENENDPT.
-#define BF_USB_TOKEN_TOKENENDPT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_TOKEN_TOKENENDPT), uint8_t) & BM_USB_TOKEN_TOKENENDPT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TOKENENDPT field to a new value.
-#define BW_USB_TOKEN_TOKENENDPT(v) (HW_USB_TOKEN_WR((HW_USB_TOKEN_RD() & ~BM_USB_TOKEN_TOKENENDPT) | BF_USB_TOKEN_TOKENENDPT(v)))
-#endif
-//@}
-
-/*!
- * @name Register USB_TOKEN, field TOKENPID[7:4] (RW)
- *
- * Contains the token type executed by the USB module.
- *
- * Values:
- * - 0001 - OUT Token. USB Module performs an OUT (TX) transaction.
- * - 1001 - IN Token. USB Module performs an In (RX) transaction.
- * - 1101 - SETUP Token. USB Module performs a SETUP (TX) transaction
- */
-//@{
-#define BP_USB_TOKEN_TOKENPID (4U) //!< Bit position for USB_TOKEN_TOKENPID.
-#define BM_USB_TOKEN_TOKENPID (0xF0U) //!< Bit mask for USB_TOKEN_TOKENPID.
-#define BS_USB_TOKEN_TOKENPID (4U) //!< Bit field size in bits for USB_TOKEN_TOKENPID.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_TOKEN_TOKENPID field.
-#define BR_USB_TOKEN_TOKENPID (HW_USB_TOKEN.B.TOKENPID)
-#endif
-
-//! @brief Format value for bitfield USB_TOKEN_TOKENPID.
-#define BF_USB_TOKEN_TOKENPID(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_TOKEN_TOKENPID), uint8_t) & BM_USB_TOKEN_TOKENPID)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TOKENPID field to a new value.
-#define BW_USB_TOKEN_TOKENPID(v) (HW_USB_TOKEN_WR((HW_USB_TOKEN_RD() & ~BM_USB_TOKEN_TOKENPID) | BF_USB_TOKEN_TOKENPID(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_SOFTHLD - SOF Threshold register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_SOFTHLD - SOF Threshold register (RW)
- *
- * Reset value: 0x00U
- *
- * The SOF Threshold Register is used only in Host mode (HOSTMODEEN=1). When in
- * Host mode, the 14-bit SOF counter counts the interval between SOF frames. The
- * SOF must be transmitted every 1ms so therefore the SOF counter is loaded with
- * a value of 12000. When the SOF counter reaches zero, a Start Of Frame (SOF)
- * token is transmitted. The SOF threshold register is used to program the number
- * of USB byte times before the SOF to stop initiating token packet transactions.
- * This register must be set to a value that ensures that other packets are not
- * actively being transmitted when the SOF time counts to zero. When the SOF
- * counter reaches the threshold value, no more tokens are transmitted until after the
- * SOF has been transmitted. The value programmed into the threshold register
- * must reserve enough time to ensure the worst case transaction completes. In
- * general the worst case transaction is an IN token followed by a data packet from
- * the target followed by the response from the host. The actual time required is
- * a function of the maximum packet size on the bus. Typical values for the SOF
- * threshold are: 64-byte packets=74; 32-byte packets=42; 16-byte packets=26;
- * 8-byte packets=18.
- */
-typedef union _hw_usb_softhld
-{
- uint8_t U;
- struct _hw_usb_softhld_bitfields
- {
- uint8_t CNT : 8; //!< [7:0]
- } B;
-} hw_usb_softhld_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_SOFTHLD register
- */
-//@{
-#define HW_USB_SOFTHLD_ADDR (REGS_USB_BASE + 0xACU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_SOFTHLD (*(__IO hw_usb_softhld_t *) HW_USB_SOFTHLD_ADDR)
-#define HW_USB_SOFTHLD_RD() (HW_USB_SOFTHLD.U)
-#define HW_USB_SOFTHLD_WR(v) (HW_USB_SOFTHLD.U = (v))
-#define HW_USB_SOFTHLD_SET(v) (HW_USB_SOFTHLD_WR(HW_USB_SOFTHLD_RD() | (v)))
-#define HW_USB_SOFTHLD_CLR(v) (HW_USB_SOFTHLD_WR(HW_USB_SOFTHLD_RD() & ~(v)))
-#define HW_USB_SOFTHLD_TOG(v) (HW_USB_SOFTHLD_WR(HW_USB_SOFTHLD_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_SOFTHLD bitfields
- */
-
-/*!
- * @name Register USB_SOFTHLD, field CNT[7:0] (RW)
- *
- * Represents the SOF count threshold in byte times.
- */
-//@{
-#define BP_USB_SOFTHLD_CNT (0U) //!< Bit position for USB_SOFTHLD_CNT.
-#define BM_USB_SOFTHLD_CNT (0xFFU) //!< Bit mask for USB_SOFTHLD_CNT.
-#define BS_USB_SOFTHLD_CNT (8U) //!< Bit field size in bits for USB_SOFTHLD_CNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_SOFTHLD_CNT field.
-#define BR_USB_SOFTHLD_CNT (HW_USB_SOFTHLD.U)
-#endif
-
-//! @brief Format value for bitfield USB_SOFTHLD_CNT.
-#define BF_USB_SOFTHLD_CNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_SOFTHLD_CNT), uint8_t) & BM_USB_SOFTHLD_CNT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CNT field to a new value.
-#define BW_USB_SOFTHLD_CNT(v) (HW_USB_SOFTHLD_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_BDTPAGE2 - BDT Page Register 2
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_BDTPAGE2 - BDT Page Register 2 (RW)
- *
- * Reset value: 0x00U
- *
- * Contains an 8-bit value used to compute the address where the current Buffer
- * Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table.
- */
-typedef union _hw_usb_bdtpage2
-{
- uint8_t U;
- struct _hw_usb_bdtpage2_bitfields
- {
- uint8_t BDTBA : 8; //!< [7:0]
- } B;
-} hw_usb_bdtpage2_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_BDTPAGE2 register
- */
-//@{
-#define HW_USB_BDTPAGE2_ADDR (REGS_USB_BASE + 0xB0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_BDTPAGE2 (*(__IO hw_usb_bdtpage2_t *) HW_USB_BDTPAGE2_ADDR)
-#define HW_USB_BDTPAGE2_RD() (HW_USB_BDTPAGE2.U)
-#define HW_USB_BDTPAGE2_WR(v) (HW_USB_BDTPAGE2.U = (v))
-#define HW_USB_BDTPAGE2_SET(v) (HW_USB_BDTPAGE2_WR(HW_USB_BDTPAGE2_RD() | (v)))
-#define HW_USB_BDTPAGE2_CLR(v) (HW_USB_BDTPAGE2_WR(HW_USB_BDTPAGE2_RD() & ~(v)))
-#define HW_USB_BDTPAGE2_TOG(v) (HW_USB_BDTPAGE2_WR(HW_USB_BDTPAGE2_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_BDTPAGE2 bitfields
- */
-
-/*!
- * @name Register USB_BDTPAGE2, field BDTBA[7:0] (RW)
- *
- * Provides address bits 23 through 16 of the BDT base address that defines the
- * location of Buffer Descriptor Table resides in system memory.
- */
-//@{
-#define BP_USB_BDTPAGE2_BDTBA (0U) //!< Bit position for USB_BDTPAGE2_BDTBA.
-#define BM_USB_BDTPAGE2_BDTBA (0xFFU) //!< Bit mask for USB_BDTPAGE2_BDTBA.
-#define BS_USB_BDTPAGE2_BDTBA (8U) //!< Bit field size in bits for USB_BDTPAGE2_BDTBA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_BDTPAGE2_BDTBA field.
-#define BR_USB_BDTPAGE2_BDTBA (HW_USB_BDTPAGE2.U)
-#endif
-
-//! @brief Format value for bitfield USB_BDTPAGE2_BDTBA.
-#define BF_USB_BDTPAGE2_BDTBA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_BDTPAGE2_BDTBA), uint8_t) & BM_USB_BDTPAGE2_BDTBA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BDTBA field to a new value.
-#define BW_USB_BDTPAGE2_BDTBA(v) (HW_USB_BDTPAGE2_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_BDTPAGE3 - BDT Page Register 3
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_BDTPAGE3 - BDT Page Register 3 (RW)
- *
- * Reset value: 0x00U
- *
- * Contains an 8-bit value used to compute the address where the current Buffer
- * Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table.
- */
-typedef union _hw_usb_bdtpage3
-{
- uint8_t U;
- struct _hw_usb_bdtpage3_bitfields
- {
- uint8_t BDTBA : 8; //!< [7:0]
- } B;
-} hw_usb_bdtpage3_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_BDTPAGE3 register
- */
-//@{
-#define HW_USB_BDTPAGE3_ADDR (REGS_USB_BASE + 0xB4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_BDTPAGE3 (*(__IO hw_usb_bdtpage3_t *) HW_USB_BDTPAGE3_ADDR)
-#define HW_USB_BDTPAGE3_RD() (HW_USB_BDTPAGE3.U)
-#define HW_USB_BDTPAGE3_WR(v) (HW_USB_BDTPAGE3.U = (v))
-#define HW_USB_BDTPAGE3_SET(v) (HW_USB_BDTPAGE3_WR(HW_USB_BDTPAGE3_RD() | (v)))
-#define HW_USB_BDTPAGE3_CLR(v) (HW_USB_BDTPAGE3_WR(HW_USB_BDTPAGE3_RD() & ~(v)))
-#define HW_USB_BDTPAGE3_TOG(v) (HW_USB_BDTPAGE3_WR(HW_USB_BDTPAGE3_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_BDTPAGE3 bitfields
- */
-
-/*!
- * @name Register USB_BDTPAGE3, field BDTBA[7:0] (RW)
- *
- * Provides address bits 31 through 24 of the BDT base address that defines the
- * location of Buffer Descriptor Table resides in system memory.
- */
-//@{
-#define BP_USB_BDTPAGE3_BDTBA (0U) //!< Bit position for USB_BDTPAGE3_BDTBA.
-#define BM_USB_BDTPAGE3_BDTBA (0xFFU) //!< Bit mask for USB_BDTPAGE3_BDTBA.
-#define BS_USB_BDTPAGE3_BDTBA (8U) //!< Bit field size in bits for USB_BDTPAGE3_BDTBA.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_BDTPAGE3_BDTBA field.
-#define BR_USB_BDTPAGE3_BDTBA (HW_USB_BDTPAGE3.U)
-#endif
-
-//! @brief Format value for bitfield USB_BDTPAGE3_BDTBA.
-#define BF_USB_BDTPAGE3_BDTBA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_BDTPAGE3_BDTBA), uint8_t) & BM_USB_BDTPAGE3_BDTBA)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BDTBA field to a new value.
-#define BW_USB_BDTPAGE3_BDTBA(v) (HW_USB_BDTPAGE3_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_ENDPTn - Endpoint Control register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_ENDPTn - Endpoint Control register (RW)
- *
- * Reset value: 0x00U
- *
- * Contains the endpoint control bits for each of the 16 endpoints available
- * within the USB module for a decoded address. The format for these registers is
- * shown in the following figure. Endpoint 0 (ENDPT0) is associated with control
- * pipe 0, which is required for all USB functions. Therefore, after a USBRST
- * interrupt occurs the processor core should set ENDPT0 to contain 0x0D. In Host mode
- * ENDPT0 is used to determine the handshake, retry and low speed
- * characteristics of the host transfer. For Control, Bulk and Interrupt transfers, the EPHSHK
- * bit should be 1. For Isochronous transfers it should be 0. Common values to
- * use for ENDPT0 in host mode are 0x4D for Control, Bulk, and Interrupt transfers,
- * and 0x4C for Isochronous transfers. The three bits EPCTLDIS, EPRXEN, and
- * EPTXEN define if an endpoint is enabled and define the direction of the endpoint.
- * The endpoint enable/direction control is defined in the following table.
- * Endpoint enable and direction control EPCTLDIS EPRXEN EPTXEN Endpoint
- * enable/direction control X 0 0 Disable endpoint X 0 1 Enable endpoint for Tx transfers only
- * X 1 0 Enable endpoint for Rx transfers only 1 1 1 Enable endpoint for Rx and
- * Tx transfers 0 1 1 Enable Endpoint for RX and TX as well as control (SETUP)
- * transfers.
- */
-typedef union _hw_usb_endptn
-{
- uint8_t U;
- struct _hw_usb_endptn_bitfields
- {
- uint8_t EPHSHK : 1; //!< [0]
- uint8_t EPSTALL : 1; //!< [1]
- uint8_t EPTXEN : 1; //!< [2]
- uint8_t EPRXEN : 1; //!< [3]
- uint8_t EPCTLDIS : 1; //!< [4]
- uint8_t RESERVED0 : 1; //!< [5]
- uint8_t RETRYDIS : 1; //!< [6]
- uint8_t HOSTWOHUB : 1; //!< [7]
- } B;
-} hw_usb_endptn_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_ENDPTn register
- */
-//@{
-#define HW_USB_ENDPTn_COUNT (16U)
-
-#define HW_USB_ENDPTn_ADDR(n) (REGS_USB_BASE + 0xC0U + (0x4U * n))
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_ENDPTn(n) (*(__IO hw_usb_endptn_t *) HW_USB_ENDPTn_ADDR(n))
-#define HW_USB_ENDPTn_RD(n) (HW_USB_ENDPTn(n).U)
-#define HW_USB_ENDPTn_WR(n, v) (HW_USB_ENDPTn(n).U = (v))
-#define HW_USB_ENDPTn_SET(n, v) (HW_USB_ENDPTn_WR(n, HW_USB_ENDPTn_RD(n) | (v)))
-#define HW_USB_ENDPTn_CLR(n, v) (HW_USB_ENDPTn_WR(n, HW_USB_ENDPTn_RD(n) & ~(v)))
-#define HW_USB_ENDPTn_TOG(n, v) (HW_USB_ENDPTn_WR(n, HW_USB_ENDPTn_RD(n) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_ENDPTn bitfields
- */
-
-/*!
- * @name Register USB_ENDPTn, field EPHSHK[0] (RW)
- *
- * When set this bit enables an endpoint to perform handshaking during a
- * transaction to this endpoint. This bit is generally 1 unless the endpoint is
- * Isochronous.
- */
-//@{
-#define BP_USB_ENDPTn_EPHSHK (0U) //!< Bit position for USB_ENDPTn_EPHSHK.
-#define BM_USB_ENDPTn_EPHSHK (0x01U) //!< Bit mask for USB_ENDPTn_EPHSHK.
-#define BS_USB_ENDPTn_EPHSHK (1U) //!< Bit field size in bits for USB_ENDPTn_EPHSHK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ENDPTn_EPHSHK field.
-#define BR_USB_ENDPTn_EPHSHK(n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPHSHK))
-#endif
-
-//! @brief Format value for bitfield USB_ENDPTn_EPHSHK.
-#define BF_USB_ENDPTn_EPHSHK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ENDPTn_EPHSHK), uint8_t) & BM_USB_ENDPTn_EPHSHK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EPHSHK field to a new value.
-#define BW_USB_ENDPTn_EPHSHK(n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPHSHK) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_ENDPTn, field EPSTALL[1] (RW)
- *
- * When set this bit indicates that the endpoint is called. This bit has
- * priority over all other control bits in the EndPoint Enable Register, but it is only
- * valid if EPTXEN=1 or EPRXEN=1. Any access to this endpoint causes the USB
- * Module to return a STALL handshake. After an endpoint is stalled it requires
- * intervention from the Host Controller.
- */
-//@{
-#define BP_USB_ENDPTn_EPSTALL (1U) //!< Bit position for USB_ENDPTn_EPSTALL.
-#define BM_USB_ENDPTn_EPSTALL (0x02U) //!< Bit mask for USB_ENDPTn_EPSTALL.
-#define BS_USB_ENDPTn_EPSTALL (1U) //!< Bit field size in bits for USB_ENDPTn_EPSTALL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ENDPTn_EPSTALL field.
-#define BR_USB_ENDPTn_EPSTALL(n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPSTALL))
-#endif
-
-//! @brief Format value for bitfield USB_ENDPTn_EPSTALL.
-#define BF_USB_ENDPTn_EPSTALL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ENDPTn_EPSTALL), uint8_t) & BM_USB_ENDPTn_EPSTALL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EPSTALL field to a new value.
-#define BW_USB_ENDPTn_EPSTALL(n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPSTALL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_ENDPTn, field EPTXEN[2] (RW)
- *
- * This bit, when set, enables the endpoint for TX transfers.
- */
-//@{
-#define BP_USB_ENDPTn_EPTXEN (2U) //!< Bit position for USB_ENDPTn_EPTXEN.
-#define BM_USB_ENDPTn_EPTXEN (0x04U) //!< Bit mask for USB_ENDPTn_EPTXEN.
-#define BS_USB_ENDPTn_EPTXEN (1U) //!< Bit field size in bits for USB_ENDPTn_EPTXEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ENDPTn_EPTXEN field.
-#define BR_USB_ENDPTn_EPTXEN(n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPTXEN))
-#endif
-
-//! @brief Format value for bitfield USB_ENDPTn_EPTXEN.
-#define BF_USB_ENDPTn_EPTXEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ENDPTn_EPTXEN), uint8_t) & BM_USB_ENDPTn_EPTXEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EPTXEN field to a new value.
-#define BW_USB_ENDPTn_EPTXEN(n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPTXEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_ENDPTn, field EPRXEN[3] (RW)
- *
- * This bit, when set, enables the endpoint for RX transfers.
- */
-//@{
-#define BP_USB_ENDPTn_EPRXEN (3U) //!< Bit position for USB_ENDPTn_EPRXEN.
-#define BM_USB_ENDPTn_EPRXEN (0x08U) //!< Bit mask for USB_ENDPTn_EPRXEN.
-#define BS_USB_ENDPTn_EPRXEN (1U) //!< Bit field size in bits for USB_ENDPTn_EPRXEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ENDPTn_EPRXEN field.
-#define BR_USB_ENDPTn_EPRXEN(n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPRXEN))
-#endif
-
-//! @brief Format value for bitfield USB_ENDPTn_EPRXEN.
-#define BF_USB_ENDPTn_EPRXEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ENDPTn_EPRXEN), uint8_t) & BM_USB_ENDPTn_EPRXEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EPRXEN field to a new value.
-#define BW_USB_ENDPTn_EPRXEN(n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPRXEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_ENDPTn, field EPCTLDIS[4] (RW)
- *
- * This bit, when set, disables control (SETUP) transfers. When cleared, control
- * transfers are enabled. This applies if and only if the EPRXEN and EPTXEN bits
- * are also set.
- */
-//@{
-#define BP_USB_ENDPTn_EPCTLDIS (4U) //!< Bit position for USB_ENDPTn_EPCTLDIS.
-#define BM_USB_ENDPTn_EPCTLDIS (0x10U) //!< Bit mask for USB_ENDPTn_EPCTLDIS.
-#define BS_USB_ENDPTn_EPCTLDIS (1U) //!< Bit field size in bits for USB_ENDPTn_EPCTLDIS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ENDPTn_EPCTLDIS field.
-#define BR_USB_ENDPTn_EPCTLDIS(n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPCTLDIS))
-#endif
-
-//! @brief Format value for bitfield USB_ENDPTn_EPCTLDIS.
-#define BF_USB_ENDPTn_EPCTLDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ENDPTn_EPCTLDIS), uint8_t) & BM_USB_ENDPTn_EPCTLDIS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the EPCTLDIS field to a new value.
-#define BW_USB_ENDPTn_EPCTLDIS(n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPCTLDIS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_ENDPTn, field RETRYDIS[6] (RW)
- *
- * This is a Host mode only bit and is present in the control register for
- * endpoint 0 (ENDPT0) only. When set this bit causes the host to not retry NAK'ed
- * (Negative Acknowledgement) transactions. When a transaction is NAKed, the BDT PID
- * field is updated with the NAK PID, and the TOKEN_DNE interrupt is set. When
- * this bit is cleared, NAKed transactions are retried in hardware. This bit must
- * be set when the host is attempting to poll an interrupt endpoint.
- */
-//@{
-#define BP_USB_ENDPTn_RETRYDIS (6U) //!< Bit position for USB_ENDPTn_RETRYDIS.
-#define BM_USB_ENDPTn_RETRYDIS (0x40U) //!< Bit mask for USB_ENDPTn_RETRYDIS.
-#define BS_USB_ENDPTn_RETRYDIS (1U) //!< Bit field size in bits for USB_ENDPTn_RETRYDIS.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ENDPTn_RETRYDIS field.
-#define BR_USB_ENDPTn_RETRYDIS(n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_RETRYDIS))
-#endif
-
-//! @brief Format value for bitfield USB_ENDPTn_RETRYDIS.
-#define BF_USB_ENDPTn_RETRYDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ENDPTn_RETRYDIS), uint8_t) & BM_USB_ENDPTn_RETRYDIS)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RETRYDIS field to a new value.
-#define BW_USB_ENDPTn_RETRYDIS(n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_RETRYDIS) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_ENDPTn, field HOSTWOHUB[7] (RW)
- *
- * This is a Host mode only field and is present in the control register for
- * endpoint 0 (ENDPT0) only. When set this bit allows the host to communicate to a
- * directly connected low speed device. When cleared, the host produces the
- * PRE_PID. It then switches to low-speed signaling when sending a token to a low speed
- * device as required to communicate with a low speed device through a hub.
- */
-//@{
-#define BP_USB_ENDPTn_HOSTWOHUB (7U) //!< Bit position for USB_ENDPTn_HOSTWOHUB.
-#define BM_USB_ENDPTn_HOSTWOHUB (0x80U) //!< Bit mask for USB_ENDPTn_HOSTWOHUB.
-#define BS_USB_ENDPTn_HOSTWOHUB (1U) //!< Bit field size in bits for USB_ENDPTn_HOSTWOHUB.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_ENDPTn_HOSTWOHUB field.
-#define BR_USB_ENDPTn_HOSTWOHUB(n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_HOSTWOHUB))
-#endif
-
-//! @brief Format value for bitfield USB_ENDPTn_HOSTWOHUB.
-#define BF_USB_ENDPTn_HOSTWOHUB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ENDPTn_HOSTWOHUB), uint8_t) & BM_USB_ENDPTn_HOSTWOHUB)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the HOSTWOHUB field to a new value.
-#define BW_USB_ENDPTn_HOSTWOHUB(n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_HOSTWOHUB) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_USBCTRL - USB Control register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_USBCTRL - USB Control register (RW)
- *
- * Reset value: 0xC0U
- */
-typedef union _hw_usb_usbctrl
-{
- uint8_t U;
- struct _hw_usb_usbctrl_bitfields
- {
- uint8_t RESERVED0 : 6; //!< [5:0]
- uint8_t PDE : 1; //!< [6]
- uint8_t SUSP : 1; //!< [7]
- } B;
-} hw_usb_usbctrl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_USBCTRL register
- */
-//@{
-#define HW_USB_USBCTRL_ADDR (REGS_USB_BASE + 0x100U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_USBCTRL (*(__IO hw_usb_usbctrl_t *) HW_USB_USBCTRL_ADDR)
-#define HW_USB_USBCTRL_RD() (HW_USB_USBCTRL.U)
-#define HW_USB_USBCTRL_WR(v) (HW_USB_USBCTRL.U = (v))
-#define HW_USB_USBCTRL_SET(v) (HW_USB_USBCTRL_WR(HW_USB_USBCTRL_RD() | (v)))
-#define HW_USB_USBCTRL_CLR(v) (HW_USB_USBCTRL_WR(HW_USB_USBCTRL_RD() & ~(v)))
-#define HW_USB_USBCTRL_TOG(v) (HW_USB_USBCTRL_WR(HW_USB_USBCTRL_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_USBCTRL bitfields
- */
-
-/*!
- * @name Register USB_USBCTRL, field PDE[6] (RW)
- *
- * Enables the weak pulldowns on the USB transceiver.
- *
- * Values:
- * - 0 - Weak pulldowns are disabled on D+ and D-.
- * - 1 - Weak pulldowns are enabled on D+ and D-.
- */
-//@{
-#define BP_USB_USBCTRL_PDE (6U) //!< Bit position for USB_USBCTRL_PDE.
-#define BM_USB_USBCTRL_PDE (0x40U) //!< Bit mask for USB_USBCTRL_PDE.
-#define BS_USB_USBCTRL_PDE (1U) //!< Bit field size in bits for USB_USBCTRL_PDE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_USBCTRL_PDE field.
-#define BR_USB_USBCTRL_PDE (BITBAND_ACCESS8(HW_USB_USBCTRL_ADDR, BP_USB_USBCTRL_PDE))
-#endif
-
-//! @brief Format value for bitfield USB_USBCTRL_PDE.
-#define BF_USB_USBCTRL_PDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_USBCTRL_PDE), uint8_t) & BM_USB_USBCTRL_PDE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PDE field to a new value.
-#define BW_USB_USBCTRL_PDE(v) (BITBAND_ACCESS8(HW_USB_USBCTRL_ADDR, BP_USB_USBCTRL_PDE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_USBCTRL, field SUSP[7] (RW)
- *
- * Places the USB transceiver into the suspend state.
- *
- * Values:
- * - 0 - USB transceiver is not in suspend state.
- * - 1 - USB transceiver is in suspend state.
- */
-//@{
-#define BP_USB_USBCTRL_SUSP (7U) //!< Bit position for USB_USBCTRL_SUSP.
-#define BM_USB_USBCTRL_SUSP (0x80U) //!< Bit mask for USB_USBCTRL_SUSP.
-#define BS_USB_USBCTRL_SUSP (1U) //!< Bit field size in bits for USB_USBCTRL_SUSP.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_USBCTRL_SUSP field.
-#define BR_USB_USBCTRL_SUSP (BITBAND_ACCESS8(HW_USB_USBCTRL_ADDR, BP_USB_USBCTRL_SUSP))
-#endif
-
-//! @brief Format value for bitfield USB_USBCTRL_SUSP.
-#define BF_USB_USBCTRL_SUSP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_USBCTRL_SUSP), uint8_t) & BM_USB_USBCTRL_SUSP)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SUSP field to a new value.
-#define BW_USB_USBCTRL_SUSP(v) (BITBAND_ACCESS8(HW_USB_USBCTRL_ADDR, BP_USB_USBCTRL_SUSP) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_OBSERVE - USB OTG Observe register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_OBSERVE - USB OTG Observe register (RO)
- *
- * Reset value: 0x50U
- *
- * Provides visibility on the state of the pull-ups and pull-downs at the
- * transceiver. Useful when interfacing to an external OTG control module via a serial
- * interface.
- */
-typedef union _hw_usb_observe
-{
- uint8_t U;
- struct _hw_usb_observe_bitfields
- {
- uint8_t RESERVED0 : 4; //!< [3:0]
- uint8_t DMPD : 1; //!< [4]
- uint8_t RESERVED1 : 1; //!< [5]
- uint8_t DPPD : 1; //!< [6]
- uint8_t DPPU : 1; //!< [7]
- } B;
-} hw_usb_observe_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_OBSERVE register
- */
-//@{
-#define HW_USB_OBSERVE_ADDR (REGS_USB_BASE + 0x104U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_OBSERVE (*(__I hw_usb_observe_t *) HW_USB_OBSERVE_ADDR)
-#define HW_USB_OBSERVE_RD() (HW_USB_OBSERVE.U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_OBSERVE bitfields
- */
-
-/*!
- * @name Register USB_OBSERVE, field DMPD[4] (RO)
- *
- * Provides observability of the D- Pulldown enable at the USB transceiver.
- *
- * Values:
- * - 0 - D- pulldown disabled.
- * - 1 - D- pulldown enabled.
- */
-//@{
-#define BP_USB_OBSERVE_DMPD (4U) //!< Bit position for USB_OBSERVE_DMPD.
-#define BM_USB_OBSERVE_DMPD (0x10U) //!< Bit mask for USB_OBSERVE_DMPD.
-#define BS_USB_OBSERVE_DMPD (1U) //!< Bit field size in bits for USB_OBSERVE_DMPD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_OBSERVE_DMPD field.
-#define BR_USB_OBSERVE_DMPD (BITBAND_ACCESS8(HW_USB_OBSERVE_ADDR, BP_USB_OBSERVE_DMPD))
-#endif
-//@}
-
-/*!
- * @name Register USB_OBSERVE, field DPPD[6] (RO)
- *
- * Provides observability of the D+ Pulldown enable at the USB transceiver.
- *
- * Values:
- * - 0 - D+ pulldown disabled.
- * - 1 - D+ pulldown enabled.
- */
-//@{
-#define BP_USB_OBSERVE_DPPD (6U) //!< Bit position for USB_OBSERVE_DPPD.
-#define BM_USB_OBSERVE_DPPD (0x40U) //!< Bit mask for USB_OBSERVE_DPPD.
-#define BS_USB_OBSERVE_DPPD (1U) //!< Bit field size in bits for USB_OBSERVE_DPPD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_OBSERVE_DPPD field.
-#define BR_USB_OBSERVE_DPPD (BITBAND_ACCESS8(HW_USB_OBSERVE_ADDR, BP_USB_OBSERVE_DPPD))
-#endif
-//@}
-
-/*!
- * @name Register USB_OBSERVE, field DPPU[7] (RO)
- *
- * Provides observability of the D+ Pullup enable at the USB transceiver.
- *
- * Values:
- * - 0 - D+ pullup disabled.
- * - 1 - D+ pullup enabled.
- */
-//@{
-#define BP_USB_OBSERVE_DPPU (7U) //!< Bit position for USB_OBSERVE_DPPU.
-#define BM_USB_OBSERVE_DPPU (0x80U) //!< Bit mask for USB_OBSERVE_DPPU.
-#define BS_USB_OBSERVE_DPPU (1U) //!< Bit field size in bits for USB_OBSERVE_DPPU.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_OBSERVE_DPPU field.
-#define BR_USB_OBSERVE_DPPU (BITBAND_ACCESS8(HW_USB_OBSERVE_ADDR, BP_USB_OBSERVE_DPPU))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_CONTROL - USB OTG Control register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_CONTROL - USB OTG Control register (RW)
- *
- * Reset value: 0x00U
- */
-typedef union _hw_usb_control
-{
- uint8_t U;
- struct _hw_usb_control_bitfields
- {
- uint8_t RESERVED0 : 4; //!< [3:0]
- uint8_t DPPULLUPNONOTG : 1; //!< [4]
- uint8_t RESERVED1 : 3; //!< [7:5]
- } B;
-} hw_usb_control_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_CONTROL register
- */
-//@{
-#define HW_USB_CONTROL_ADDR (REGS_USB_BASE + 0x108U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_CONTROL (*(__IO hw_usb_control_t *) HW_USB_CONTROL_ADDR)
-#define HW_USB_CONTROL_RD() (HW_USB_CONTROL.U)
-#define HW_USB_CONTROL_WR(v) (HW_USB_CONTROL.U = (v))
-#define HW_USB_CONTROL_SET(v) (HW_USB_CONTROL_WR(HW_USB_CONTROL_RD() | (v)))
-#define HW_USB_CONTROL_CLR(v) (HW_USB_CONTROL_WR(HW_USB_CONTROL_RD() & ~(v)))
-#define HW_USB_CONTROL_TOG(v) (HW_USB_CONTROL_WR(HW_USB_CONTROL_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_CONTROL bitfields
- */
-
-/*!
- * @name Register USB_CONTROL, field DPPULLUPNONOTG[4] (RW)
- *
- * Provides control of the DP Pullup in USBOTG, if USB is configured in non-OTG
- * device mode.
- *
- * Values:
- * - 0 - DP Pullup in non-OTG device mode is not enabled.
- * - 1 - DP Pullup in non-OTG device mode is enabled.
- */
-//@{
-#define BP_USB_CONTROL_DPPULLUPNONOTG (4U) //!< Bit position for USB_CONTROL_DPPULLUPNONOTG.
-#define BM_USB_CONTROL_DPPULLUPNONOTG (0x10U) //!< Bit mask for USB_CONTROL_DPPULLUPNONOTG.
-#define BS_USB_CONTROL_DPPULLUPNONOTG (1U) //!< Bit field size in bits for USB_CONTROL_DPPULLUPNONOTG.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_CONTROL_DPPULLUPNONOTG field.
-#define BR_USB_CONTROL_DPPULLUPNONOTG (BITBAND_ACCESS8(HW_USB_CONTROL_ADDR, BP_USB_CONTROL_DPPULLUPNONOTG))
-#endif
-
-//! @brief Format value for bitfield USB_CONTROL_DPPULLUPNONOTG.
-#define BF_USB_CONTROL_DPPULLUPNONOTG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CONTROL_DPPULLUPNONOTG), uint8_t) & BM_USB_CONTROL_DPPULLUPNONOTG)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DPPULLUPNONOTG field to a new value.
-#define BW_USB_CONTROL_DPPULLUPNONOTG(v) (BITBAND_ACCESS8(HW_USB_CONTROL_ADDR, BP_USB_CONTROL_DPPULLUPNONOTG) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_USBTRC0 - USB Transceiver Control register 0
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_USBTRC0 - USB Transceiver Control register 0 (RW)
- *
- * Reset value: 0x00U
- *
- * Includes signals for basic operation of the on-chip USB Full Speed
- * transceiver and configuration of the USB data connection that are not otherwise included
- * in the USB Full Speed controller registers.
- */
-typedef union _hw_usb_usbtrc0
-{
- uint8_t U;
- struct _hw_usb_usbtrc0_bitfields
- {
- uint8_t USB_RESUME_INT : 1; //!< [0] USB Asynchronous Interrupt
- uint8_t SYNC_DET : 1; //!< [1] Synchronous USB Interrupt Detect
- uint8_t USB_CLK_RECOVERY_INT : 1; //!< [2] Combined USB Clock
- //! Recovery interrupt status
- uint8_t RESERVED0 : 2; //!< [4:3]
- uint8_t USBRESMEN : 1; //!< [5] Asynchronous Resume Interrupt Enable
- uint8_t RESERVED1 : 1; //!< [6]
- uint8_t USBRESET : 1; //!< [7] USB Reset
- } B;
-} hw_usb_usbtrc0_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_USBTRC0 register
- */
-//@{
-#define HW_USB_USBTRC0_ADDR (REGS_USB_BASE + 0x10CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_USBTRC0 (*(__IO hw_usb_usbtrc0_t *) HW_USB_USBTRC0_ADDR)
-#define HW_USB_USBTRC0_RD() (HW_USB_USBTRC0.U)
-#define HW_USB_USBTRC0_WR(v) (HW_USB_USBTRC0.U = (v))
-#define HW_USB_USBTRC0_SET(v) (HW_USB_USBTRC0_WR(HW_USB_USBTRC0_RD() | (v)))
-#define HW_USB_USBTRC0_CLR(v) (HW_USB_USBTRC0_WR(HW_USB_USBTRC0_RD() & ~(v)))
-#define HW_USB_USBTRC0_TOG(v) (HW_USB_USBTRC0_WR(HW_USB_USBTRC0_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_USBTRC0 bitfields
- */
-
-/*!
- * @name Register USB_USBTRC0, field USB_RESUME_INT[0] (RO)
- *
- * Values:
- * - 0 - No interrupt was generated.
- * - 1 - Interrupt was generated because of the USB asynchronous interrupt.
- */
-//@{
-#define BP_USB_USBTRC0_USB_RESUME_INT (0U) //!< Bit position for USB_USBTRC0_USB_RESUME_INT.
-#define BM_USB_USBTRC0_USB_RESUME_INT (0x01U) //!< Bit mask for USB_USBTRC0_USB_RESUME_INT.
-#define BS_USB_USBTRC0_USB_RESUME_INT (1U) //!< Bit field size in bits for USB_USBTRC0_USB_RESUME_INT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_USBTRC0_USB_RESUME_INT field.
-#define BR_USB_USBTRC0_USB_RESUME_INT (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR, BP_USB_USBTRC0_USB_RESUME_INT))
-#endif
-//@}
-
-/*!
- * @name Register USB_USBTRC0, field SYNC_DET[1] (RO)
- *
- * Values:
- * - 0 - Synchronous interrupt has not been detected.
- * - 1 - Synchronous interrupt has been detected.
- */
-//@{
-#define BP_USB_USBTRC0_SYNC_DET (1U) //!< Bit position for USB_USBTRC0_SYNC_DET.
-#define BM_USB_USBTRC0_SYNC_DET (0x02U) //!< Bit mask for USB_USBTRC0_SYNC_DET.
-#define BS_USB_USBTRC0_SYNC_DET (1U) //!< Bit field size in bits for USB_USBTRC0_SYNC_DET.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_USBTRC0_SYNC_DET field.
-#define BR_USB_USBTRC0_SYNC_DET (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR, BP_USB_USBTRC0_SYNC_DET))
-#endif
-//@}
-
-/*!
- * @name Register USB_USBTRC0, field USB_CLK_RECOVERY_INT[2] (RO)
- *
- * This read-only field will be set to value high at 1'b1 when any of USB clock
- * recovery interrupt conditions are detected and those interrupts are unmasked.
- * For customer use the only unmasked USB clock recovery interrupt condition
- * results from an overflow of the frequency trim setting values indicating that the
- * frequency trim calculated is out of the adjustment range of the IRC48M output
- * clock. To clear this bit after it has been set, Write 0xFF to register
- * USB_CLK_RECOVER_INT_STATUS.
- */
-//@{
-#define BP_USB_USBTRC0_USB_CLK_RECOVERY_INT (2U) //!< Bit position for USB_USBTRC0_USB_CLK_RECOVERY_INT.
-#define BM_USB_USBTRC0_USB_CLK_RECOVERY_INT (0x04U) //!< Bit mask for USB_USBTRC0_USB_CLK_RECOVERY_INT.
-#define BS_USB_USBTRC0_USB_CLK_RECOVERY_INT (1U) //!< Bit field size in bits for USB_USBTRC0_USB_CLK_RECOVERY_INT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_USBTRC0_USB_CLK_RECOVERY_INT field.
-#define BR_USB_USBTRC0_USB_CLK_RECOVERY_INT (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR, BP_USB_USBTRC0_USB_CLK_RECOVERY_INT))
-#endif
-//@}
-
-/*!
- * @name Register USB_USBTRC0, field USBRESMEN[5] (RW)
- *
- * This bit, when set, allows the USB module to send an asynchronous wakeup
- * event to the MCU upon detection of resume signaling on the USB bus. The MCU then
- * re-enables clocks to the USB module. It is used for low-power suspend mode when
- * USB module clocks are stopped or the USB transceiver is in Suspend mode.
- * Async wakeup only works in device mode.
- *
- * Values:
- * - 0 - USB asynchronous wakeup from suspend mode disabled.
- * - 1 - USB asynchronous wakeup from suspend mode enabled. The asynchronous
- * resume interrupt differs from the synchronous resume interrupt in that it
- * asynchronously detects K-state using the unfiltered state of the D+ and D-
- * pins. This interrupt should only be enabled when the Transceiver is
- * suspended.
- */
-//@{
-#define BP_USB_USBTRC0_USBRESMEN (5U) //!< Bit position for USB_USBTRC0_USBRESMEN.
-#define BM_USB_USBTRC0_USBRESMEN (0x20U) //!< Bit mask for USB_USBTRC0_USBRESMEN.
-#define BS_USB_USBTRC0_USBRESMEN (1U) //!< Bit field size in bits for USB_USBTRC0_USBRESMEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_USBTRC0_USBRESMEN field.
-#define BR_USB_USBTRC0_USBRESMEN (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR, BP_USB_USBTRC0_USBRESMEN))
-#endif
-
-//! @brief Format value for bitfield USB_USBTRC0_USBRESMEN.
-#define BF_USB_USBTRC0_USBRESMEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_USBTRC0_USBRESMEN), uint8_t) & BM_USB_USBTRC0_USBRESMEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the USBRESMEN field to a new value.
-#define BW_USB_USBTRC0_USBRESMEN(v) (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR, BP_USB_USBTRC0_USBRESMEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_USBTRC0, field USBRESET[7] (WO)
- *
- * Generates a hard reset to USBOTG. After this bit is set and the reset occurs,
- * this bit is automatically cleared. This bit is always read as zero. Wait two
- * USB clock cycles after setting this bit.
- *
- * Values:
- * - 0 - Normal USB module operation.
- * - 1 - Returns the USB module to its reset state.
- */
-//@{
-#define BP_USB_USBTRC0_USBRESET (7U) //!< Bit position for USB_USBTRC0_USBRESET.
-#define BM_USB_USBTRC0_USBRESET (0x80U) //!< Bit mask for USB_USBTRC0_USBRESET.
-#define BS_USB_USBTRC0_USBRESET (1U) //!< Bit field size in bits for USB_USBTRC0_USBRESET.
-
-//! @brief Format value for bitfield USB_USBTRC0_USBRESET.
-#define BF_USB_USBTRC0_USBRESET(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_USBTRC0_USBRESET), uint8_t) & BM_USB_USBTRC0_USBRESET)
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_USBFRMADJUST - Frame Adjust Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_USBFRMADJUST - Frame Adjust Register (RW)
- *
- * Reset value: 0x00U
- */
-typedef union _hw_usb_usbfrmadjust
-{
- uint8_t U;
- struct _hw_usb_usbfrmadjust_bitfields
- {
- uint8_t ADJ : 8; //!< [7:0] Frame Adjustment
- } B;
-} hw_usb_usbfrmadjust_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_USBFRMADJUST register
- */
-//@{
-#define HW_USB_USBFRMADJUST_ADDR (REGS_USB_BASE + 0x114U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_USBFRMADJUST (*(__IO hw_usb_usbfrmadjust_t *) HW_USB_USBFRMADJUST_ADDR)
-#define HW_USB_USBFRMADJUST_RD() (HW_USB_USBFRMADJUST.U)
-#define HW_USB_USBFRMADJUST_WR(v) (HW_USB_USBFRMADJUST.U = (v))
-#define HW_USB_USBFRMADJUST_SET(v) (HW_USB_USBFRMADJUST_WR(HW_USB_USBFRMADJUST_RD() | (v)))
-#define HW_USB_USBFRMADJUST_CLR(v) (HW_USB_USBFRMADJUST_WR(HW_USB_USBFRMADJUST_RD() & ~(v)))
-#define HW_USB_USBFRMADJUST_TOG(v) (HW_USB_USBFRMADJUST_WR(HW_USB_USBFRMADJUST_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_USBFRMADJUST bitfields
- */
-
-/*!
- * @name Register USB_USBFRMADJUST, field ADJ[7:0] (RW)
- *
- * In Host mode, the frame adjustment is a twos complement number that adjusts
- * the period of each USB frame in 12-MHz clock periods. A SOF is normally
- * generated every 12,000 12-MHz clock cycles. The Frame Adjust Register can adjust this
- * by -128 to +127 to compensate for inaccuracies in the USB 48-MHz clock.
- * Changes to the ADJ bit take effect at the next start of the next frame.
- */
-//@{
-#define BP_USB_USBFRMADJUST_ADJ (0U) //!< Bit position for USB_USBFRMADJUST_ADJ.
-#define BM_USB_USBFRMADJUST_ADJ (0xFFU) //!< Bit mask for USB_USBFRMADJUST_ADJ.
-#define BS_USB_USBFRMADJUST_ADJ (8U) //!< Bit field size in bits for USB_USBFRMADJUST_ADJ.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_USBFRMADJUST_ADJ field.
-#define BR_USB_USBFRMADJUST_ADJ (HW_USB_USBFRMADJUST.U)
-#endif
-
-//! @brief Format value for bitfield USB_USBFRMADJUST_ADJ.
-#define BF_USB_USBFRMADJUST_ADJ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_USBFRMADJUST_ADJ), uint8_t) & BM_USB_USBFRMADJUST_ADJ)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ADJ field to a new value.
-#define BW_USB_USBFRMADJUST_ADJ(v) (HW_USB_USBFRMADJUST_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_CLK_RECOVER_CTRL - USB Clock recovery control
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_CLK_RECOVER_CTRL - USB Clock recovery control (RW)
- *
- * Reset value: 0x00U
- *
- * Signals in this register control the crystal-less USB clock mode in which the
- * internal IRC48M oscillator is tuned to match the clock extracted from the
- * incoming USB data stream. The IRC48M internal oscillator module must be enabled
- * in register USB_CLK_RECOVER_IRC_EN for this mode.
- */
-typedef union _hw_usb_clk_recover_ctrl
-{
- uint8_t U;
- struct _hw_usb_clk_recover_ctrl_bitfields
- {
- uint8_t RESERVED0 : 5; //!< [4:0]
- uint8_t RESTART_IFRTRIM_EN : 1; //!< [5] Restart from IFR trim value
- uint8_t RESET_RESUME_ROUGH_EN : 1; //!< [6] Reset/resume to rough
- //! phase enable
- uint8_t CLOCK_RECOVER_EN : 1; //!< [7] Crystal-less USB enable
- } B;
-} hw_usb_clk_recover_ctrl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_CLK_RECOVER_CTRL register
- */
-//@{
-#define HW_USB_CLK_RECOVER_CTRL_ADDR (REGS_USB_BASE + 0x140U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_CLK_RECOVER_CTRL (*(__IO hw_usb_clk_recover_ctrl_t *) HW_USB_CLK_RECOVER_CTRL_ADDR)
-#define HW_USB_CLK_RECOVER_CTRL_RD() (HW_USB_CLK_RECOVER_CTRL.U)
-#define HW_USB_CLK_RECOVER_CTRL_WR(v) (HW_USB_CLK_RECOVER_CTRL.U = (v))
-#define HW_USB_CLK_RECOVER_CTRL_SET(v) (HW_USB_CLK_RECOVER_CTRL_WR(HW_USB_CLK_RECOVER_CTRL_RD() | (v)))
-#define HW_USB_CLK_RECOVER_CTRL_CLR(v) (HW_USB_CLK_RECOVER_CTRL_WR(HW_USB_CLK_RECOVER_CTRL_RD() & ~(v)))
-#define HW_USB_CLK_RECOVER_CTRL_TOG(v) (HW_USB_CLK_RECOVER_CTRL_WR(HW_USB_CLK_RECOVER_CTRL_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_CLK_RECOVER_CTRL bitfields
- */
-
-/*!
- * @name Register USB_CLK_RECOVER_CTRL, field RESTART_IFRTRIM_EN[5] (RW)
- *
- * IRC48 has a default trim fine value whose default value is factory trimmed
- * (the IFR trim value). Clock recover block tracks the accuracy of the clock 48Mhz
- * and keeps updating the trim fine value accordingly
- *
- * Values:
- * - 0 - Trim fine adjustment always works based on the previous updated trim
- * fine value (default)
- * - 1 - Trim fine restarts from the IFR trim value whenever
- * bus_reset/bus_resume is detected or module enable is desasserted
- */
-//@{
-#define BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (5U) //!< Bit position for USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN.
-#define BM_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (0x20U) //!< Bit mask for USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN.
-#define BS_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (1U) //!< Bit field size in bits for USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN field.
-#define BR_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR, BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN))
-#endif
-
-//! @brief Format value for bitfield USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN.
-#define BF_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN), uint8_t) & BM_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RESTART_IFRTRIM_EN field to a new value.
-#define BW_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR, BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_CLK_RECOVER_CTRL, field RESET_RESUME_ROUGH_EN[6] (RW)
- *
- * The clock recovery block tracks the IRC48Mhz to get an accurate 48Mhz clock.
- * It has two phases after user enables clock_recover_en bit, rough phase and
- * tracking phase. The step to fine tune the IRC 48Mhz by adjusting the trim fine
- * value is different during these two phases. The step in rough phase is larger
- * than that in tracking phase. Switch back to rough stage whenever USB bus reset
- * or bus resume occurs.
- *
- * Values:
- * - 0 - Always works in tracking phase after the 1st time rough to track
- * transition (default)
- * - 1 - Go back to rough stage whenever bus reset or bus resume occurs
- */
-//@{
-#define BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (6U) //!< Bit position for USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN.
-#define BM_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (0x40U) //!< Bit mask for USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN.
-#define BS_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (1U) //!< Bit field size in bits for USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN field.
-#define BR_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR, BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN))
-#endif
-
-//! @brief Format value for bitfield USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN.
-#define BF_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN), uint8_t) & BM_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RESET_RESUME_ROUGH_EN field to a new value.
-#define BW_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR, BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_CLK_RECOVER_CTRL, field CLOCK_RECOVER_EN[7] (RW)
- *
- * This bit must be enabled if user wants to use the crystal-less USB mode for
- * the Full Speed USB controller and transceiver. This bit should not be set for
- * USB host mode or OTG.
- *
- * Values:
- * - 0 - Disable clock recovery block (default)
- * - 1 - Enable clock recovery block
- */
-//@{
-#define BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (7U) //!< Bit position for USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN.
-#define BM_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (0x80U) //!< Bit mask for USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN.
-#define BS_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (1U) //!< Bit field size in bits for USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN field.
-#define BR_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR, BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN))
-#endif
-
-//! @brief Format value for bitfield USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN.
-#define BF_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN), uint8_t) & BM_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CLOCK_RECOVER_EN field to a new value.
-#define BW_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR, BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register (RW)
- *
- * Reset value: 0x01U
- *
- * Controls basic operation of the on-chip IRC48M module used to produce nominal
- * 48MHz clocks for USB crystal-less operation and other functions. See
- * additional information about the IRC48M operation in the Clock Distribution chapter.
- */
-typedef union _hw_usb_clk_recover_irc_en
-{
- uint8_t U;
- struct _hw_usb_clk_recover_irc_en_bitfields
- {
- uint8_t REG_EN : 1; //!< [0] IRC48M regulator enable
- uint8_t IRC_EN : 1; //!< [1] IRC48M enable
- uint8_t RESERVED0 : 6; //!< [7:2]
- } B;
-} hw_usb_clk_recover_irc_en_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_CLK_RECOVER_IRC_EN register
- */
-//@{
-#define HW_USB_CLK_RECOVER_IRC_EN_ADDR (REGS_USB_BASE + 0x144U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_CLK_RECOVER_IRC_EN (*(__IO hw_usb_clk_recover_irc_en_t *) HW_USB_CLK_RECOVER_IRC_EN_ADDR)
-#define HW_USB_CLK_RECOVER_IRC_EN_RD() (HW_USB_CLK_RECOVER_IRC_EN.U)
-#define HW_USB_CLK_RECOVER_IRC_EN_WR(v) (HW_USB_CLK_RECOVER_IRC_EN.U = (v))
-#define HW_USB_CLK_RECOVER_IRC_EN_SET(v) (HW_USB_CLK_RECOVER_IRC_EN_WR(HW_USB_CLK_RECOVER_IRC_EN_RD() | (v)))
-#define HW_USB_CLK_RECOVER_IRC_EN_CLR(v) (HW_USB_CLK_RECOVER_IRC_EN_WR(HW_USB_CLK_RECOVER_IRC_EN_RD() & ~(v)))
-#define HW_USB_CLK_RECOVER_IRC_EN_TOG(v) (HW_USB_CLK_RECOVER_IRC_EN_WR(HW_USB_CLK_RECOVER_IRC_EN_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_CLK_RECOVER_IRC_EN bitfields
- */
-
-/*!
- * @name Register USB_CLK_RECOVER_IRC_EN, field REG_EN[0] (RW)
- *
- * This bit is used to enable the local analog regulator for IRC48Mhz module.
- * This bit must be set if user wants to use the crystal-less USB clock
- * configuration.
- *
- * Values:
- * - 0 - IRC48M local regulator is disabled
- * - 1 - IRC48M local regulator is enabled (default)
- */
-//@{
-#define BP_USB_CLK_RECOVER_IRC_EN_REG_EN (0U) //!< Bit position for USB_CLK_RECOVER_IRC_EN_REG_EN.
-#define BM_USB_CLK_RECOVER_IRC_EN_REG_EN (0x01U) //!< Bit mask for USB_CLK_RECOVER_IRC_EN_REG_EN.
-#define BS_USB_CLK_RECOVER_IRC_EN_REG_EN (1U) //!< Bit field size in bits for USB_CLK_RECOVER_IRC_EN_REG_EN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_CLK_RECOVER_IRC_EN_REG_EN field.
-#define BR_USB_CLK_RECOVER_IRC_EN_REG_EN (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR, BP_USB_CLK_RECOVER_IRC_EN_REG_EN))
-#endif
-
-//! @brief Format value for bitfield USB_CLK_RECOVER_IRC_EN_REG_EN.
-#define BF_USB_CLK_RECOVER_IRC_EN_REG_EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CLK_RECOVER_IRC_EN_REG_EN), uint8_t) & BM_USB_CLK_RECOVER_IRC_EN_REG_EN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the REG_EN field to a new value.
-#define BW_USB_CLK_RECOVER_IRC_EN_REG_EN(v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR, BP_USB_CLK_RECOVER_IRC_EN_REG_EN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USB_CLK_RECOVER_IRC_EN, field IRC_EN[1] (RW)
- *
- * This bit is used to enable the on-chip IRC48Mhz module to generate clocks for
- * crystal-less USB. It can only be used for FS USB device mode operation. This
- * bit must be set before using the crystal-less USB clock configuration.
- *
- * Values:
- * - 0 - Disable the IRC48M module (default)
- * - 1 - Enable the IRC48M module
- */
-//@{
-#define BP_USB_CLK_RECOVER_IRC_EN_IRC_EN (1U) //!< Bit position for USB_CLK_RECOVER_IRC_EN_IRC_EN.
-#define BM_USB_CLK_RECOVER_IRC_EN_IRC_EN (0x02U) //!< Bit mask for USB_CLK_RECOVER_IRC_EN_IRC_EN.
-#define BS_USB_CLK_RECOVER_IRC_EN_IRC_EN (1U) //!< Bit field size in bits for USB_CLK_RECOVER_IRC_EN_IRC_EN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_CLK_RECOVER_IRC_EN_IRC_EN field.
-#define BR_USB_CLK_RECOVER_IRC_EN_IRC_EN (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR, BP_USB_CLK_RECOVER_IRC_EN_IRC_EN))
-#endif
-
-//! @brief Format value for bitfield USB_CLK_RECOVER_IRC_EN_IRC_EN.
-#define BF_USB_CLK_RECOVER_IRC_EN_IRC_EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CLK_RECOVER_IRC_EN_IRC_EN), uint8_t) & BM_USB_CLK_RECOVER_IRC_EN_IRC_EN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IRC_EN field to a new value.
-#define BW_USB_CLK_RECOVER_IRC_EN_IRC_EN(v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR, BP_USB_CLK_RECOVER_IRC_EN_IRC_EN) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status (W1C)
- *
- * Reset value: 0x00U
- *
- * A Write operation with value high at 1'b1 on any combination of individual
- * bits will clear those bits.
- */
-typedef union _hw_usb_clk_recover_int_status
-{
- uint8_t U;
- struct _hw_usb_clk_recover_int_status_bitfields
- {
- uint8_t RESERVED0 : 4; //!< [3:0]
- uint8_t OVF_ERROR : 1; //!< [4]
- uint8_t RESERVED1 : 3; //!< [7:5]
- } B;
-} hw_usb_clk_recover_int_status_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USB_CLK_RECOVER_INT_STATUS register
- */
-//@{
-#define HW_USB_CLK_RECOVER_INT_STATUS_ADDR (REGS_USB_BASE + 0x15CU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USB_CLK_RECOVER_INT_STATUS (*(__IO hw_usb_clk_recover_int_status_t *) HW_USB_CLK_RECOVER_INT_STATUS_ADDR)
-#define HW_USB_CLK_RECOVER_INT_STATUS_RD() (HW_USB_CLK_RECOVER_INT_STATUS.U)
-#define HW_USB_CLK_RECOVER_INT_STATUS_WR(v) (HW_USB_CLK_RECOVER_INT_STATUS.U = (v))
-#define HW_USB_CLK_RECOVER_INT_STATUS_SET(v) (HW_USB_CLK_RECOVER_INT_STATUS_WR(HW_USB_CLK_RECOVER_INT_STATUS_RD() | (v)))
-#define HW_USB_CLK_RECOVER_INT_STATUS_CLR(v) (HW_USB_CLK_RECOVER_INT_STATUS_WR(HW_USB_CLK_RECOVER_INT_STATUS_RD() & ~(v)))
-#define HW_USB_CLK_RECOVER_INT_STATUS_TOG(v) (HW_USB_CLK_RECOVER_INT_STATUS_WR(HW_USB_CLK_RECOVER_INT_STATUS_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USB_CLK_RECOVER_INT_STATUS bitfields
- */
-
-/*!
- * @name Register USB_CLK_RECOVER_INT_STATUS, field OVF_ERROR[4] (W1C)
- *
- * Indicates that the USB clock recovery algorithm has detected that the
- * frequency trim adjustment needed for the IRC48M output clock is outside the available
- * TRIM_FINE adjustment range for the IRC48M module.
- *
- * Values:
- * - 0 - No interrupt is reported
- * - 1 - Unmasked interrupt has been generated
- */
-//@{
-#define BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR (4U) //!< Bit position for USB_CLK_RECOVER_INT_STATUS_OVF_ERROR.
-#define BM_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR (0x10U) //!< Bit mask for USB_CLK_RECOVER_INT_STATUS_OVF_ERROR.
-#define BS_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR (1U) //!< Bit field size in bits for USB_CLK_RECOVER_INT_STATUS_OVF_ERROR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USB_CLK_RECOVER_INT_STATUS_OVF_ERROR field.
-#define BR_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_INT_STATUS_ADDR, BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR))
-#endif
-
-//! @brief Format value for bitfield USB_CLK_RECOVER_INT_STATUS_OVF_ERROR.
-#define BF_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR), uint8_t) & BM_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the OVF_ERROR field to a new value.
-#define BW_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_INT_STATUS_ADDR, BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_usb_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All USB module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_usb
-{
- __I hw_usb_perid_t PERID; //!< [0x0] Peripheral ID register
- uint8_t _reserved0[3];
- __I hw_usb_idcomp_t IDCOMP; //!< [0x4] Peripheral ID Complement register
- uint8_t _reserved1[3];
- __I hw_usb_rev_t REV; //!< [0x8] Peripheral Revision register
- uint8_t _reserved2[3];
- __I hw_usb_addinfo_t ADDINFO; //!< [0xC] Peripheral Additional Info register
- uint8_t _reserved3[3];
- __IO hw_usb_otgistat_t OTGISTAT; //!< [0x10] OTG Interrupt Status register
- uint8_t _reserved4[3];
- __IO hw_usb_otgicr_t OTGICR; //!< [0x14] OTG Interrupt Control register
- uint8_t _reserved5[3];
- __IO hw_usb_otgstat_t OTGSTAT; //!< [0x18] OTG Status register
- uint8_t _reserved6[3];
- __IO hw_usb_otgctl_t OTGCTL; //!< [0x1C] OTG Control register
- uint8_t _reserved7[99];
- __IO hw_usb_istat_t ISTAT; //!< [0x80] Interrupt Status register
- uint8_t _reserved8[3];
- __IO hw_usb_inten_t INTEN; //!< [0x84] Interrupt Enable register
- uint8_t _reserved9[3];
- __IO hw_usb_errstat_t ERRSTAT; //!< [0x88] Error Interrupt Status register
- uint8_t _reserved10[3];
- __IO hw_usb_erren_t ERREN; //!< [0x8C] Error Interrupt Enable register
- uint8_t _reserved11[3];
- __I hw_usb_stat_t STAT; //!< [0x90] Status register
- uint8_t _reserved12[3];
- __IO hw_usb_ctl_t CTL; //!< [0x94] Control register
- uint8_t _reserved13[3];
- __IO hw_usb_addr_t ADDR; //!< [0x98] Address register
- uint8_t _reserved14[3];
- __IO hw_usb_bdtpage1_t BDTPAGE1; //!< [0x9C] BDT Page register 1
- uint8_t _reserved15[3];
- __IO hw_usb_frmnuml_t FRMNUML; //!< [0xA0] Frame Number register Low
- uint8_t _reserved16[3];
- __IO hw_usb_frmnumh_t FRMNUMH; //!< [0xA4] Frame Number register High
- uint8_t _reserved17[3];
- __IO hw_usb_token_t TOKEN; //!< [0xA8] Token register
- uint8_t _reserved18[3];
- __IO hw_usb_softhld_t SOFTHLD; //!< [0xAC] SOF Threshold register
- uint8_t _reserved19[3];
- __IO hw_usb_bdtpage2_t BDTPAGE2; //!< [0xB0] BDT Page Register 2
- uint8_t _reserved20[3];
- __IO hw_usb_bdtpage3_t BDTPAGE3; //!< [0xB4] BDT Page Register 3
- uint8_t _reserved21[11];
- struct {
- __IO hw_usb_endptn_t ENDPTn; //!< [0xC0] Endpoint Control register
- uint8_t _reserved0[3];
- } ENDPOINT[16];
- __IO hw_usb_usbctrl_t USBCTRL; //!< [0x100] USB Control register
- uint8_t _reserved22[3];
- __I hw_usb_observe_t OBSERVE; //!< [0x104] USB OTG Observe register
- uint8_t _reserved23[3];
- __IO hw_usb_control_t CONTROL; //!< [0x108] USB OTG Control register
- uint8_t _reserved24[3];
- __IO hw_usb_usbtrc0_t USBTRC0; //!< [0x10C] USB Transceiver Control register 0
- uint8_t _reserved25[7];
- __IO hw_usb_usbfrmadjust_t USBFRMADJUST; //!< [0x114] Frame Adjust Register
- uint8_t _reserved26[43];
- __IO hw_usb_clk_recover_ctrl_t CLK_RECOVER_CTRL; //!< [0x140] USB Clock recovery control
- uint8_t _reserved27[3];
- __IO hw_usb_clk_recover_irc_en_t CLK_RECOVER_IRC_EN; //!< [0x144] IRC48M oscillator enable register
- uint8_t _reserved28[23];
- __IO hw_usb_clk_recover_int_status_t CLK_RECOVER_INT_STATUS; //!< [0x15C] Clock recovery separated interrupt status
-} hw_usb_t;
-#pragma pack()
-
-//! @brief Macro to access all USB registers.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_USB</code>.
-#define HW_USB (*(hw_usb_t *) REGS_USB_BASE)
-#endif
-
-#endif // __HW_USB_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_usbdcd.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,957 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_USBDCD_REGISTERS_H__
-#define __HW_USBDCD_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 USBDCD
- *
- * USB Device Charger Detection module
- *
- * Registers defined in this header file:
- * - HW_USBDCD_CONTROL - Control register
- * - HW_USBDCD_CLOCK - Clock register
- * - HW_USBDCD_STATUS - Status register
- * - HW_USBDCD_TIMER0 - TIMER0 register
- * - HW_USBDCD_TIMER1 - TIMER1 register
- * - HW_USBDCD_TIMER2_BC11 - TIMER2_BC11 register
- * - HW_USBDCD_TIMER2_BC12 - TIMER2_BC12 register
- *
- * - hw_usbdcd_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_USBDCD_BASE
-#define HW_USBDCD_INSTANCE_COUNT (1U) //!< Number of instances of the USBDCD module.
-#define HW_USBDCD0 (0U) //!< Instance number for USBDCD.
-#define REGS_USBDCD0_BASE (0x40035000U) //!< Base address for USBDCD.
-
-//! @brief Table of base addresses for USBDCD instances.
-static const uint32_t __g_regs_USBDCD_base_addresses[] = {
- REGS_USBDCD0_BASE,
- };
-
-//! @brief Get the base address of USBDCD by instance number.
-//! @param x USBDCD instance number, from 0 through 0.
-#define REGS_USBDCD_BASE(x) (__g_regs_USBDCD_base_addresses[(x)])
-
-//! @brief Get the instance number given a base address.
-//! @param b Base address for an instance of USBDCD.
-#define REGS_USBDCD_INSTANCE(b) ((b) == REGS_USBDCD0_BASE ? HW_USBDCD0 : 0)
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USBDCD_CONTROL - Control register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USBDCD_CONTROL - Control register (RW)
- *
- * Reset value: 0x00010000U
- *
- * Contains the control and interrupt bit fields.
- */
-typedef union _hw_usbdcd_control
-{
- uint32_t U;
- struct _hw_usbdcd_control_bitfields
- {
- uint32_t IACK : 1; //!< [0] Interrupt Acknowledge
- uint32_t RESERVED0 : 7; //!< [7:1]
- uint32_t IF : 1; //!< [8] Interrupt Flag
- uint32_t RESERVED1 : 7; //!< [15:9]
- uint32_t IE : 1; //!< [16] Interrupt Enable
- uint32_t BC12 : 1; //!< [17]
- uint32_t RESERVED2 : 6; //!< [23:18]
- uint32_t START : 1; //!< [24] Start Change Detection Sequence
- uint32_t SR : 1; //!< [25] Software Reset
- uint32_t RESERVED3 : 6; //!< [31:26]
- } B;
-} hw_usbdcd_control_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USBDCD_CONTROL register
- */
-//@{
-#define HW_USBDCD_CONTROL_ADDR(x) (REGS_USBDCD_BASE(x) + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USBDCD_CONTROL(x) (*(__IO hw_usbdcd_control_t *) HW_USBDCD_CONTROL_ADDR(x))
-#define HW_USBDCD_CONTROL_RD(x) (HW_USBDCD_CONTROL(x).U)
-#define HW_USBDCD_CONTROL_WR(x, v) (HW_USBDCD_CONTROL(x).U = (v))
-#define HW_USBDCD_CONTROL_SET(x, v) (HW_USBDCD_CONTROL_WR(x, HW_USBDCD_CONTROL_RD(x) | (v)))
-#define HW_USBDCD_CONTROL_CLR(x, v) (HW_USBDCD_CONTROL_WR(x, HW_USBDCD_CONTROL_RD(x) & ~(v)))
-#define HW_USBDCD_CONTROL_TOG(x, v) (HW_USBDCD_CONTROL_WR(x, HW_USBDCD_CONTROL_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USBDCD_CONTROL bitfields
- */
-
-/*!
- * @name Register USBDCD_CONTROL, field IACK[0] (WORZ)
- *
- * Determines whether the interrupt is cleared.
- *
- * Values:
- * - 0 - Do not clear the interrupt.
- * - 1 - Clear the IF bit (interrupt flag).
- */
-//@{
-#define BP_USBDCD_CONTROL_IACK (0U) //!< Bit position for USBDCD_CONTROL_IACK.
-#define BM_USBDCD_CONTROL_IACK (0x00000001U) //!< Bit mask for USBDCD_CONTROL_IACK.
-#define BS_USBDCD_CONTROL_IACK (1U) //!< Bit field size in bits for USBDCD_CONTROL_IACK.
-
-//! @brief Format value for bitfield USBDCD_CONTROL_IACK.
-#define BF_USBDCD_CONTROL_IACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CONTROL_IACK), uint32_t) & BM_USBDCD_CONTROL_IACK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IACK field to a new value.
-#define BW_USBDCD_CONTROL_IACK(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IACK) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USBDCD_CONTROL, field IF[8] (RO)
- *
- * Determines whether an interrupt is pending.
- *
- * Values:
- * - 0 - No interrupt is pending.
- * - 1 - An interrupt is pending.
- */
-//@{
-#define BP_USBDCD_CONTROL_IF (8U) //!< Bit position for USBDCD_CONTROL_IF.
-#define BM_USBDCD_CONTROL_IF (0x00000100U) //!< Bit mask for USBDCD_CONTROL_IF.
-#define BS_USBDCD_CONTROL_IF (1U) //!< Bit field size in bits for USBDCD_CONTROL_IF.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USBDCD_CONTROL_IF field.
-#define BR_USBDCD_CONTROL_IF(x) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IF))
-#endif
-//@}
-
-/*!
- * @name Register USBDCD_CONTROL, field IE[16] (RW)
- *
- * Enables/disables interrupts to the system.
- *
- * Values:
- * - 0 - Disable interrupts to the system.
- * - 1 - Enable interrupts to the system.
- */
-//@{
-#define BP_USBDCD_CONTROL_IE (16U) //!< Bit position for USBDCD_CONTROL_IE.
-#define BM_USBDCD_CONTROL_IE (0x00010000U) //!< Bit mask for USBDCD_CONTROL_IE.
-#define BS_USBDCD_CONTROL_IE (1U) //!< Bit field size in bits for USBDCD_CONTROL_IE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USBDCD_CONTROL_IE field.
-#define BR_USBDCD_CONTROL_IE(x) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IE))
-#endif
-
-//! @brief Format value for bitfield USBDCD_CONTROL_IE.
-#define BF_USBDCD_CONTROL_IE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CONTROL_IE), uint32_t) & BM_USBDCD_CONTROL_IE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IE field to a new value.
-#define BW_USBDCD_CONTROL_IE(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USBDCD_CONTROL, field BC12[17] (RW)
- *
- * BC1.2 compatibility. This bit cannot be changed after start detection.
- *
- * Values:
- * - 0 - Compatible with BC1.1 (default)
- * - 1 - Compatible with BC1.2
- */
-//@{
-#define BP_USBDCD_CONTROL_BC12 (17U) //!< Bit position for USBDCD_CONTROL_BC12.
-#define BM_USBDCD_CONTROL_BC12 (0x00020000U) //!< Bit mask for USBDCD_CONTROL_BC12.
-#define BS_USBDCD_CONTROL_BC12 (1U) //!< Bit field size in bits for USBDCD_CONTROL_BC12.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USBDCD_CONTROL_BC12 field.
-#define BR_USBDCD_CONTROL_BC12(x) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_BC12))
-#endif
-
-//! @brief Format value for bitfield USBDCD_CONTROL_BC12.
-#define BF_USBDCD_CONTROL_BC12(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CONTROL_BC12), uint32_t) & BM_USBDCD_CONTROL_BC12)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BC12 field to a new value.
-#define BW_USBDCD_CONTROL_BC12(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_BC12) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USBDCD_CONTROL, field START[24] (WORZ)
- *
- * Determines whether the charger detection sequence is initiated.
- *
- * Values:
- * - 0 - Do not start the sequence. Writes of this value have no effect.
- * - 1 - Initiate the charger detection sequence. If the sequence is already
- * running, writes of this value have no effect.
- */
-//@{
-#define BP_USBDCD_CONTROL_START (24U) //!< Bit position for USBDCD_CONTROL_START.
-#define BM_USBDCD_CONTROL_START (0x01000000U) //!< Bit mask for USBDCD_CONTROL_START.
-#define BS_USBDCD_CONTROL_START (1U) //!< Bit field size in bits for USBDCD_CONTROL_START.
-
-//! @brief Format value for bitfield USBDCD_CONTROL_START.
-#define BF_USBDCD_CONTROL_START(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CONTROL_START), uint32_t) & BM_USBDCD_CONTROL_START)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the START field to a new value.
-#define BW_USBDCD_CONTROL_START(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_START) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USBDCD_CONTROL, field SR[25] (WORZ)
- *
- * Determines whether a software reset is performed.
- *
- * Values:
- * - 0 - Do not perform a software reset.
- * - 1 - Perform a software reset.
- */
-//@{
-#define BP_USBDCD_CONTROL_SR (25U) //!< Bit position for USBDCD_CONTROL_SR.
-#define BM_USBDCD_CONTROL_SR (0x02000000U) //!< Bit mask for USBDCD_CONTROL_SR.
-#define BS_USBDCD_CONTROL_SR (1U) //!< Bit field size in bits for USBDCD_CONTROL_SR.
-
-//! @brief Format value for bitfield USBDCD_CONTROL_SR.
-#define BF_USBDCD_CONTROL_SR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CONTROL_SR), uint32_t) & BM_USBDCD_CONTROL_SR)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the SR field to a new value.
-#define BW_USBDCD_CONTROL_SR(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_SR) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USBDCD_CLOCK - Clock register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USBDCD_CLOCK - Clock register (RW)
- *
- * Reset value: 0x000000C1U
- */
-typedef union _hw_usbdcd_clock
-{
- uint32_t U;
- struct _hw_usbdcd_clock_bitfields
- {
- uint32_t CLOCK_UNIT : 1; //!< [0] Unit of Measurement Encoding for
- //! Clock Speed
- uint32_t RESERVED0 : 1; //!< [1]
- uint32_t CLOCK_SPEED : 10; //!< [11:2] Numerical Value of Clock Speed
- //! in Binary
- uint32_t RESERVED1 : 20; //!< [31:12]
- } B;
-} hw_usbdcd_clock_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USBDCD_CLOCK register
- */
-//@{
-#define HW_USBDCD_CLOCK_ADDR(x) (REGS_USBDCD_BASE(x) + 0x4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USBDCD_CLOCK(x) (*(__IO hw_usbdcd_clock_t *) HW_USBDCD_CLOCK_ADDR(x))
-#define HW_USBDCD_CLOCK_RD(x) (HW_USBDCD_CLOCK(x).U)
-#define HW_USBDCD_CLOCK_WR(x, v) (HW_USBDCD_CLOCK(x).U = (v))
-#define HW_USBDCD_CLOCK_SET(x, v) (HW_USBDCD_CLOCK_WR(x, HW_USBDCD_CLOCK_RD(x) | (v)))
-#define HW_USBDCD_CLOCK_CLR(x, v) (HW_USBDCD_CLOCK_WR(x, HW_USBDCD_CLOCK_RD(x) & ~(v)))
-#define HW_USBDCD_CLOCK_TOG(x, v) (HW_USBDCD_CLOCK_WR(x, HW_USBDCD_CLOCK_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USBDCD_CLOCK bitfields
- */
-
-/*!
- * @name Register USBDCD_CLOCK, field CLOCK_UNIT[0] (RW)
- *
- * Specifies the unit of measure for the clock speed.
- *
- * Values:
- * - 0 - kHz Speed (between 1 kHz and 1023 kHz)
- * - 1 - MHz Speed (between 1 MHz and 1023 MHz)
- */
-//@{
-#define BP_USBDCD_CLOCK_CLOCK_UNIT (0U) //!< Bit position for USBDCD_CLOCK_CLOCK_UNIT.
-#define BM_USBDCD_CLOCK_CLOCK_UNIT (0x00000001U) //!< Bit mask for USBDCD_CLOCK_CLOCK_UNIT.
-#define BS_USBDCD_CLOCK_CLOCK_UNIT (1U) //!< Bit field size in bits for USBDCD_CLOCK_CLOCK_UNIT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USBDCD_CLOCK_CLOCK_UNIT field.
-#define BR_USBDCD_CLOCK_CLOCK_UNIT(x) (BITBAND_ACCESS32(HW_USBDCD_CLOCK_ADDR(x), BP_USBDCD_CLOCK_CLOCK_UNIT))
-#endif
-
-//! @brief Format value for bitfield USBDCD_CLOCK_CLOCK_UNIT.
-#define BF_USBDCD_CLOCK_CLOCK_UNIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CLOCK_CLOCK_UNIT), uint32_t) & BM_USBDCD_CLOCK_CLOCK_UNIT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CLOCK_UNIT field to a new value.
-#define BW_USBDCD_CLOCK_CLOCK_UNIT(x, v) (BITBAND_ACCESS32(HW_USBDCD_CLOCK_ADDR(x), BP_USBDCD_CLOCK_CLOCK_UNIT) = (v))
-#endif
-//@}
-
-/*!
- * @name Register USBDCD_CLOCK, field CLOCK_SPEED[11:2] (RW)
- *
- * The unit of measure is programmed in CLOCK_UNIT. The valid range is from 1 to
- * 1023 when clock unit is MHz and 4 to 1023 when clock unit is kHz. Examples
- * with CLOCK_UNIT = 1: For 48 MHz: 0b00_0011_0000 (48) (Default) For 24 MHz:
- * 0b00_0001_1000 (24) Examples with CLOCK_UNIT = 0: For 100 kHz: 0b00_0110_0100 (100)
- * For 500 kHz: 0b01_1111_0100 (500)
- */
-//@{
-#define BP_USBDCD_CLOCK_CLOCK_SPEED (2U) //!< Bit position for USBDCD_CLOCK_CLOCK_SPEED.
-#define BM_USBDCD_CLOCK_CLOCK_SPEED (0x00000FFCU) //!< Bit mask for USBDCD_CLOCK_CLOCK_SPEED.
-#define BS_USBDCD_CLOCK_CLOCK_SPEED (10U) //!< Bit field size in bits for USBDCD_CLOCK_CLOCK_SPEED.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USBDCD_CLOCK_CLOCK_SPEED field.
-#define BR_USBDCD_CLOCK_CLOCK_SPEED(x) (HW_USBDCD_CLOCK(x).B.CLOCK_SPEED)
-#endif
-
-//! @brief Format value for bitfield USBDCD_CLOCK_CLOCK_SPEED.
-#define BF_USBDCD_CLOCK_CLOCK_SPEED(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CLOCK_CLOCK_SPEED), uint32_t) & BM_USBDCD_CLOCK_CLOCK_SPEED)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CLOCK_SPEED field to a new value.
-#define BW_USBDCD_CLOCK_CLOCK_SPEED(x, v) (HW_USBDCD_CLOCK_WR(x, (HW_USBDCD_CLOCK_RD(x) & ~BM_USBDCD_CLOCK_CLOCK_SPEED) | BF_USBDCD_CLOCK_CLOCK_SPEED(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USBDCD_STATUS - Status register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USBDCD_STATUS - Status register (RO)
- *
- * Reset value: 0x00000000U
- *
- * Provides the current state of the module for system software monitoring.
- */
-typedef union _hw_usbdcd_status
-{
- uint32_t U;
- struct _hw_usbdcd_status_bitfields
- {
- uint32_t RESERVED0 : 16; //!< [15:0]
- uint32_t SEQ_RES : 2; //!< [17:16] Charger Detection Sequence Results
- uint32_t SEQ_STAT : 2; //!< [19:18] Charger Detection Sequence Status
- uint32_t ERR : 1; //!< [20] Error Flag
- uint32_t TO : 1; //!< [21] Timeout Flag
- uint32_t ACTIVE : 1; //!< [22] Active Status Indicator
- uint32_t RESERVED1 : 9; //!< [31:23]
- } B;
-} hw_usbdcd_status_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USBDCD_STATUS register
- */
-//@{
-#define HW_USBDCD_STATUS_ADDR(x) (REGS_USBDCD_BASE(x) + 0x8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USBDCD_STATUS(x) (*(__I hw_usbdcd_status_t *) HW_USBDCD_STATUS_ADDR(x))
-#define HW_USBDCD_STATUS_RD(x) (HW_USBDCD_STATUS(x).U)
-#endif
-//@}
-
-/*
- * Constants & macros for individual USBDCD_STATUS bitfields
- */
-
-/*!
- * @name Register USBDCD_STATUS, field SEQ_RES[17:16] (RO)
- *
- * Reports how the charger detection is attached.
- *
- * Values:
- * - 00 - No results to report.
- * - 01 - Attached to a standard host. Must comply with USB 2.0 by drawing only
- * 2.5 mA (max) until connected.
- * - 10 - Attached to a charging port. The exact meaning depends on bit 18: 0:
- * Attached to either a charging host or a dedicated charger. The charger type
- * detection has not completed. 1: Attached to a charging host. The charger
- * type detection has completed.
- * - 11 - Attached to a dedicated charger.
- */
-//@{
-#define BP_USBDCD_STATUS_SEQ_RES (16U) //!< Bit position for USBDCD_STATUS_SEQ_RES.
-#define BM_USBDCD_STATUS_SEQ_RES (0x00030000U) //!< Bit mask for USBDCD_STATUS_SEQ_RES.
-#define BS_USBDCD_STATUS_SEQ_RES (2U) //!< Bit field size in bits for USBDCD_STATUS_SEQ_RES.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USBDCD_STATUS_SEQ_RES field.
-#define BR_USBDCD_STATUS_SEQ_RES(x) (HW_USBDCD_STATUS(x).B.SEQ_RES)
-#endif
-//@}
-
-/*!
- * @name Register USBDCD_STATUS, field SEQ_STAT[19:18] (RO)
- *
- * Indicates the status of the charger detection sequence.
- *
- * Values:
- * - 00 - The module is either not enabled, or the module is enabled but the
- * data pins have not yet been detected.
- * - 01 - Data pin contact detection is complete.
- * - 10 - Charging port detection is complete.
- * - 11 - Charger type detection is complete.
- */
-//@{
-#define BP_USBDCD_STATUS_SEQ_STAT (18U) //!< Bit position for USBDCD_STATUS_SEQ_STAT.
-#define BM_USBDCD_STATUS_SEQ_STAT (0x000C0000U) //!< Bit mask for USBDCD_STATUS_SEQ_STAT.
-#define BS_USBDCD_STATUS_SEQ_STAT (2U) //!< Bit field size in bits for USBDCD_STATUS_SEQ_STAT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USBDCD_STATUS_SEQ_STAT field.
-#define BR_USBDCD_STATUS_SEQ_STAT(x) (HW_USBDCD_STATUS(x).B.SEQ_STAT)
-#endif
-//@}
-
-/*!
- * @name Register USBDCD_STATUS, field ERR[20] (RO)
- *
- * Indicates whether there is an error in the detection sequence.
- *
- * Values:
- * - 0 - No sequence errors.
- * - 1 - Error in the detection sequence. See the SEQ_STAT field to determine
- * the phase in which the error occurred.
- */
-//@{
-#define BP_USBDCD_STATUS_ERR (20U) //!< Bit position for USBDCD_STATUS_ERR.
-#define BM_USBDCD_STATUS_ERR (0x00100000U) //!< Bit mask for USBDCD_STATUS_ERR.
-#define BS_USBDCD_STATUS_ERR (1U) //!< Bit field size in bits for USBDCD_STATUS_ERR.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USBDCD_STATUS_ERR field.
-#define BR_USBDCD_STATUS_ERR(x) (BITBAND_ACCESS32(HW_USBDCD_STATUS_ADDR(x), BP_USBDCD_STATUS_ERR))
-#endif
-//@}
-
-/*!
- * @name Register USBDCD_STATUS, field TO[21] (RO)
- *
- * Indicates whether the detection sequence has passed the timeout threshhold.
- *
- * Values:
- * - 0 - The detection sequence has not been running for over 1 s.
- * - 1 - It has been over 1 s since the data pin contact was detected and
- * debounced.
- */
-//@{
-#define BP_USBDCD_STATUS_TO (21U) //!< Bit position for USBDCD_STATUS_TO.
-#define BM_USBDCD_STATUS_TO (0x00200000U) //!< Bit mask for USBDCD_STATUS_TO.
-#define BS_USBDCD_STATUS_TO (1U) //!< Bit field size in bits for USBDCD_STATUS_TO.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USBDCD_STATUS_TO field.
-#define BR_USBDCD_STATUS_TO(x) (BITBAND_ACCESS32(HW_USBDCD_STATUS_ADDR(x), BP_USBDCD_STATUS_TO))
-#endif
-//@}
-
-/*!
- * @name Register USBDCD_STATUS, field ACTIVE[22] (RO)
- *
- * Indicates whether the sequence is running.
- *
- * Values:
- * - 0 - The sequence is not running.
- * - 1 - The sequence is running.
- */
-//@{
-#define BP_USBDCD_STATUS_ACTIVE (22U) //!< Bit position for USBDCD_STATUS_ACTIVE.
-#define BM_USBDCD_STATUS_ACTIVE (0x00400000U) //!< Bit mask for USBDCD_STATUS_ACTIVE.
-#define BS_USBDCD_STATUS_ACTIVE (1U) //!< Bit field size in bits for USBDCD_STATUS_ACTIVE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USBDCD_STATUS_ACTIVE field.
-#define BR_USBDCD_STATUS_ACTIVE(x) (BITBAND_ACCESS32(HW_USBDCD_STATUS_ADDR(x), BP_USBDCD_STATUS_ACTIVE))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USBDCD_TIMER0 - TIMER0 register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USBDCD_TIMER0 - TIMER0 register (RW)
- *
- * Reset value: 0x00100000U
- *
- * TIMER0 has an TSEQ_INIT field that represents the system latency in ms.
- * Latency is measured from the time when VBUS goes active until the time system
- * software initiates charger detection sequence in USBDCD module. When software sets
- * the CONTROL[START] bit, the Unit Connection Timer (TUNITCON) is initialized
- * with the value of TSEQ_INIT. Valid values are 0-1023, however the USB Battery
- * Charging Specification requires the entire sequence, including TSEQ_INIT, to be
- * completed in 1s or less.
- */
-typedef union _hw_usbdcd_timer0
-{
- uint32_t U;
- struct _hw_usbdcd_timer0_bitfields
- {
- uint32_t TUNITCON : 12; //!< [11:0] Unit Connection Timer Elapse (in
- //! ms)
- uint32_t RESERVED0 : 4; //!< [15:12]
- uint32_t TSEQ_INIT : 10; //!< [25:16] Sequence Initiation Time
- uint32_t RESERVED1 : 6; //!< [31:26]
- } B;
-} hw_usbdcd_timer0_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USBDCD_TIMER0 register
- */
-//@{
-#define HW_USBDCD_TIMER0_ADDR(x) (REGS_USBDCD_BASE(x) + 0x10U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USBDCD_TIMER0(x) (*(__IO hw_usbdcd_timer0_t *) HW_USBDCD_TIMER0_ADDR(x))
-#define HW_USBDCD_TIMER0_RD(x) (HW_USBDCD_TIMER0(x).U)
-#define HW_USBDCD_TIMER0_WR(x, v) (HW_USBDCD_TIMER0(x).U = (v))
-#define HW_USBDCD_TIMER0_SET(x, v) (HW_USBDCD_TIMER0_WR(x, HW_USBDCD_TIMER0_RD(x) | (v)))
-#define HW_USBDCD_TIMER0_CLR(x, v) (HW_USBDCD_TIMER0_WR(x, HW_USBDCD_TIMER0_RD(x) & ~(v)))
-#define HW_USBDCD_TIMER0_TOG(x, v) (HW_USBDCD_TIMER0_WR(x, HW_USBDCD_TIMER0_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USBDCD_TIMER0 bitfields
- */
-
-/*!
- * @name Register USBDCD_TIMER0, field TUNITCON[11:0] (RO)
- *
- * Displays the amount of elapsed time since the event of setting the START bit
- * plus the value of TSEQ_INIT. The timer is automatically initialized with the
- * value of TSEQ_INIT before starting to count. This timer enables compliance with
- * the maximum time allowed to connect T UNIT_CON under the USB Battery Charging
- * Specification. If the timer reaches the one second limit, the module triggers
- * an interrupt and sets the error flag STATUS[ERR]. The timer continues
- * counting throughout the charger detection sequence, even when control has been passed
- * to software. As long as the module is active, the timer continues to count
- * until it reaches the maximum value of 0xFFF (4095 ms). The timer does not
- * rollover to zero. A software reset clears the timer.
- */
-//@{
-#define BP_USBDCD_TIMER0_TUNITCON (0U) //!< Bit position for USBDCD_TIMER0_TUNITCON.
-#define BM_USBDCD_TIMER0_TUNITCON (0x00000FFFU) //!< Bit mask for USBDCD_TIMER0_TUNITCON.
-#define BS_USBDCD_TIMER0_TUNITCON (12U) //!< Bit field size in bits for USBDCD_TIMER0_TUNITCON.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USBDCD_TIMER0_TUNITCON field.
-#define BR_USBDCD_TIMER0_TUNITCON(x) (HW_USBDCD_TIMER0(x).B.TUNITCON)
-#endif
-//@}
-
-/*!
- * @name Register USBDCD_TIMER0, field TSEQ_INIT[25:16] (RW)
- *
- * TSEQ_INIT represents the system latency (in ms) measured from the time VBUS
- * goes active to the time system software initiates the charger detection
- * sequence in the USBDCD module. When software sets the CONTROL[START] bit, the Unit
- * Connection Timer (TUNITCON) is initialized with the value of TSEQ_INIT. Valid
- * values are 0-1023, but the USB Battery Charging Specification requires the
- * entire sequence, including TSEQ_INIT, to be completed in 1s or less.
- */
-//@{
-#define BP_USBDCD_TIMER0_TSEQ_INIT (16U) //!< Bit position for USBDCD_TIMER0_TSEQ_INIT.
-#define BM_USBDCD_TIMER0_TSEQ_INIT (0x03FF0000U) //!< Bit mask for USBDCD_TIMER0_TSEQ_INIT.
-#define BS_USBDCD_TIMER0_TSEQ_INIT (10U) //!< Bit field size in bits for USBDCD_TIMER0_TSEQ_INIT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USBDCD_TIMER0_TSEQ_INIT field.
-#define BR_USBDCD_TIMER0_TSEQ_INIT(x) (HW_USBDCD_TIMER0(x).B.TSEQ_INIT)
-#endif
-
-//! @brief Format value for bitfield USBDCD_TIMER0_TSEQ_INIT.
-#define BF_USBDCD_TIMER0_TSEQ_INIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER0_TSEQ_INIT), uint32_t) & BM_USBDCD_TIMER0_TSEQ_INIT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TSEQ_INIT field to a new value.
-#define BW_USBDCD_TIMER0_TSEQ_INIT(x, v) (HW_USBDCD_TIMER0_WR(x, (HW_USBDCD_TIMER0_RD(x) & ~BM_USBDCD_TIMER0_TSEQ_INIT) | BF_USBDCD_TIMER0_TSEQ_INIT(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USBDCD_TIMER1 - TIMER1 register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USBDCD_TIMER1 - TIMER1 register (RW)
- *
- * Reset value: 0x000A0028U
- *
- * TIMER1 contains timing parameters. Note that register values can be written
- * that are not compliant with the USB Battery Charging Specification, so care
- * should be taken when overwriting the default values.
- */
-typedef union _hw_usbdcd_timer1
-{
- uint32_t U;
- struct _hw_usbdcd_timer1_bitfields
- {
- uint32_t TVDPSRC_ON : 10; //!< [9:0] Time Period Comparator Enabled
- uint32_t RESERVED0 : 6; //!< [15:10]
- uint32_t TDCD_DBNC : 10; //!< [25:16] Time Period to Debounce D+
- //! Signal
- uint32_t RESERVED1 : 6; //!< [31:26]
- } B;
-} hw_usbdcd_timer1_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USBDCD_TIMER1 register
- */
-//@{
-#define HW_USBDCD_TIMER1_ADDR(x) (REGS_USBDCD_BASE(x) + 0x14U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USBDCD_TIMER1(x) (*(__IO hw_usbdcd_timer1_t *) HW_USBDCD_TIMER1_ADDR(x))
-#define HW_USBDCD_TIMER1_RD(x) (HW_USBDCD_TIMER1(x).U)
-#define HW_USBDCD_TIMER1_WR(x, v) (HW_USBDCD_TIMER1(x).U = (v))
-#define HW_USBDCD_TIMER1_SET(x, v) (HW_USBDCD_TIMER1_WR(x, HW_USBDCD_TIMER1_RD(x) | (v)))
-#define HW_USBDCD_TIMER1_CLR(x, v) (HW_USBDCD_TIMER1_WR(x, HW_USBDCD_TIMER1_RD(x) & ~(v)))
-#define HW_USBDCD_TIMER1_TOG(x, v) (HW_USBDCD_TIMER1_WR(x, HW_USBDCD_TIMER1_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USBDCD_TIMER1 bitfields
- */
-
-/*!
- * @name Register USBDCD_TIMER1, field TVDPSRC_ON[9:0] (RW)
- *
- * This timing parameter is used after detection of the data pin. See "Charging
- * Port Detection". Valid values are 1-1023, but the USB Battery Charging
- * Specification requires a minimum value of 40 ms.
- */
-//@{
-#define BP_USBDCD_TIMER1_TVDPSRC_ON (0U) //!< Bit position for USBDCD_TIMER1_TVDPSRC_ON.
-#define BM_USBDCD_TIMER1_TVDPSRC_ON (0x000003FFU) //!< Bit mask for USBDCD_TIMER1_TVDPSRC_ON.
-#define BS_USBDCD_TIMER1_TVDPSRC_ON (10U) //!< Bit field size in bits for USBDCD_TIMER1_TVDPSRC_ON.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USBDCD_TIMER1_TVDPSRC_ON field.
-#define BR_USBDCD_TIMER1_TVDPSRC_ON(x) (HW_USBDCD_TIMER1(x).B.TVDPSRC_ON)
-#endif
-
-//! @brief Format value for bitfield USBDCD_TIMER1_TVDPSRC_ON.
-#define BF_USBDCD_TIMER1_TVDPSRC_ON(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER1_TVDPSRC_ON), uint32_t) & BM_USBDCD_TIMER1_TVDPSRC_ON)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TVDPSRC_ON field to a new value.
-#define BW_USBDCD_TIMER1_TVDPSRC_ON(x, v) (HW_USBDCD_TIMER1_WR(x, (HW_USBDCD_TIMER1_RD(x) & ~BM_USBDCD_TIMER1_TVDPSRC_ON) | BF_USBDCD_TIMER1_TVDPSRC_ON(v)))
-#endif
-//@}
-
-/*!
- * @name Register USBDCD_TIMER1, field TDCD_DBNC[25:16] (RW)
- *
- * Sets the time period (ms) to debounce the D+ signal during the data pin
- * contact detection phase. See "Debouncing the data pin contact" Valid values are
- * 1-1023, but the USB Battery Charging Specification requires a minimum value of 10
- * ms.
- */
-//@{
-#define BP_USBDCD_TIMER1_TDCD_DBNC (16U) //!< Bit position for USBDCD_TIMER1_TDCD_DBNC.
-#define BM_USBDCD_TIMER1_TDCD_DBNC (0x03FF0000U) //!< Bit mask for USBDCD_TIMER1_TDCD_DBNC.
-#define BS_USBDCD_TIMER1_TDCD_DBNC (10U) //!< Bit field size in bits for USBDCD_TIMER1_TDCD_DBNC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USBDCD_TIMER1_TDCD_DBNC field.
-#define BR_USBDCD_TIMER1_TDCD_DBNC(x) (HW_USBDCD_TIMER1(x).B.TDCD_DBNC)
-#endif
-
-//! @brief Format value for bitfield USBDCD_TIMER1_TDCD_DBNC.
-#define BF_USBDCD_TIMER1_TDCD_DBNC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER1_TDCD_DBNC), uint32_t) & BM_USBDCD_TIMER1_TDCD_DBNC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TDCD_DBNC field to a new value.
-#define BW_USBDCD_TIMER1_TDCD_DBNC(x, v) (HW_USBDCD_TIMER1_WR(x, (HW_USBDCD_TIMER1_RD(x) & ~BM_USBDCD_TIMER1_TDCD_DBNC) | BF_USBDCD_TIMER1_TDCD_DBNC(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_USBDCD_TIMER2_BC11 - TIMER2_BC11 register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USBDCD_TIMER2_BC11 - TIMER2_BC11 register (RW)
- *
- * Reset value: 0x00280001U
- *
- * TIMER2_BC11 contains timing parameters for USB Battery Charging
- * Specification, v1.1. Register values can be written that are not compliant with the USB
- * Battery Charging Specification, so care should be taken when overwriting the
- * default values.
- */
-typedef union _hw_usbdcd_timer2_bc11
-{
- uint32_t U;
- struct _hw_usbdcd_timer2_bc11_bitfields
- {
- uint32_t CHECK_DM : 4; //!< [3:0] Time Before Check of D- Line
- uint32_t RESERVED0 : 12; //!< [15:4]
- uint32_t TVDPSRC_CON : 10; //!< [25:16] Time Period Before Enabling
- //! D+ Pullup
- uint32_t RESERVED1 : 6; //!< [31:26]
- } B;
-} hw_usbdcd_timer2_bc11_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USBDCD_TIMER2_BC11 register
- */
-//@{
-#define HW_USBDCD_TIMER2_BC11_ADDR(x) (REGS_USBDCD_BASE(x) + 0x18U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USBDCD_TIMER2_BC11(x) (*(__IO hw_usbdcd_timer2_bc11_t *) HW_USBDCD_TIMER2_BC11_ADDR(x))
-#define HW_USBDCD_TIMER2_BC11_RD(x) (HW_USBDCD_TIMER2_BC11(x).U)
-#define HW_USBDCD_TIMER2_BC11_WR(x, v) (HW_USBDCD_TIMER2_BC11(x).U = (v))
-#define HW_USBDCD_TIMER2_BC11_SET(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, HW_USBDCD_TIMER2_BC11_RD(x) | (v)))
-#define HW_USBDCD_TIMER2_BC11_CLR(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, HW_USBDCD_TIMER2_BC11_RD(x) & ~(v)))
-#define HW_USBDCD_TIMER2_BC11_TOG(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, HW_USBDCD_TIMER2_BC11_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USBDCD_TIMER2_BC11 bitfields
- */
-
-/*!
- * @name Register USBDCD_TIMER2_BC11, field CHECK_DM[3:0] (RW)
- *
- * Sets the amount of time (in ms) that the module waits after the device
- * connects to the USB bus until checking the state of the D- line to determine the
- * type of charging port. See "Charger Type Detection." Valid values are 1-15ms.
- */
-//@{
-#define BP_USBDCD_TIMER2_BC11_CHECK_DM (0U) //!< Bit position for USBDCD_TIMER2_BC11_CHECK_DM.
-#define BM_USBDCD_TIMER2_BC11_CHECK_DM (0x0000000FU) //!< Bit mask for USBDCD_TIMER2_BC11_CHECK_DM.
-#define BS_USBDCD_TIMER2_BC11_CHECK_DM (4U) //!< Bit field size in bits for USBDCD_TIMER2_BC11_CHECK_DM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USBDCD_TIMER2_BC11_CHECK_DM field.
-#define BR_USBDCD_TIMER2_BC11_CHECK_DM(x) (HW_USBDCD_TIMER2_BC11(x).B.CHECK_DM)
-#endif
-
-//! @brief Format value for bitfield USBDCD_TIMER2_BC11_CHECK_DM.
-#define BF_USBDCD_TIMER2_BC11_CHECK_DM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER2_BC11_CHECK_DM), uint32_t) & BM_USBDCD_TIMER2_BC11_CHECK_DM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CHECK_DM field to a new value.
-#define BW_USBDCD_TIMER2_BC11_CHECK_DM(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, (HW_USBDCD_TIMER2_BC11_RD(x) & ~BM_USBDCD_TIMER2_BC11_CHECK_DM) | BF_USBDCD_TIMER2_BC11_CHECK_DM(v)))
-#endif
-//@}
-
-/*!
- * @name Register USBDCD_TIMER2_BC11, field TVDPSRC_CON[25:16] (RW)
- *
- * Sets the time period (ms) that the module waits after charging port detection
- * before system software must enable the D+ pullup to connect to the USB host.
- * Valid values are 1-1023, but the USB Battery Charging Specification requires a
- * minimum value of 40 ms.
- */
-//@{
-#define BP_USBDCD_TIMER2_BC11_TVDPSRC_CON (16U) //!< Bit position for USBDCD_TIMER2_BC11_TVDPSRC_CON.
-#define BM_USBDCD_TIMER2_BC11_TVDPSRC_CON (0x03FF0000U) //!< Bit mask for USBDCD_TIMER2_BC11_TVDPSRC_CON.
-#define BS_USBDCD_TIMER2_BC11_TVDPSRC_CON (10U) //!< Bit field size in bits for USBDCD_TIMER2_BC11_TVDPSRC_CON.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USBDCD_TIMER2_BC11_TVDPSRC_CON field.
-#define BR_USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (HW_USBDCD_TIMER2_BC11(x).B.TVDPSRC_CON)
-#endif
-
-//! @brief Format value for bitfield USBDCD_TIMER2_BC11_TVDPSRC_CON.
-#define BF_USBDCD_TIMER2_BC11_TVDPSRC_CON(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER2_BC11_TVDPSRC_CON), uint32_t) & BM_USBDCD_TIMER2_BC11_TVDPSRC_CON)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TVDPSRC_CON field to a new value.
-#define BW_USBDCD_TIMER2_BC11_TVDPSRC_CON(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, (HW_USBDCD_TIMER2_BC11_RD(x) & ~BM_USBDCD_TIMER2_BC11_TVDPSRC_CON) | BF_USBDCD_TIMER2_BC11_TVDPSRC_CON(v)))
-#endif
-//@}
-//-------------------------------------------------------------------------------------------
-// HW_USBDCD_TIMER2_BC12 - TIMER2_BC12 register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_USBDCD_TIMER2_BC12 - TIMER2_BC12 register (RW)
- *
- * Reset value: 0x00010028U
- *
- * TIMER2_BC12 contains timing parameters for USB Battery Charging
- * Specification, v1.2. Register values can be written that are not compliant with the USB
- * Battery Charging Specification, so care should be taken when overwriting the
- * default values.
- */
-typedef union _hw_usbdcd_timer2_bc12
-{
- uint32_t U;
- struct _hw_usbdcd_timer2_bc12_bitfields
- {
- uint32_t TVDMSRC_ON : 10; //!< [9:0]
- uint32_t RESERVED0 : 6; //!< [15:10]
- uint32_t TWAIT_AFTER_PRD : 10; //!< [25:16]
- uint32_t RESERVED1 : 6; //!< [31:26]
- } B;
-} hw_usbdcd_timer2_bc12_t;
-#endif
-
-/*!
- * @name Constants and macros for entire USBDCD_TIMER2_BC12 register
- */
-//@{
-#define HW_USBDCD_TIMER2_BC12_ADDR(x) (REGS_USBDCD_BASE(x) + 0x18U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_USBDCD_TIMER2_BC12(x) (*(__IO hw_usbdcd_timer2_bc12_t *) HW_USBDCD_TIMER2_BC12_ADDR(x))
-#define HW_USBDCD_TIMER2_BC12_RD(x) (HW_USBDCD_TIMER2_BC12(x).U)
-#define HW_USBDCD_TIMER2_BC12_WR(x, v) (HW_USBDCD_TIMER2_BC12(x).U = (v))
-#define HW_USBDCD_TIMER2_BC12_SET(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, HW_USBDCD_TIMER2_BC12_RD(x) | (v)))
-#define HW_USBDCD_TIMER2_BC12_CLR(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, HW_USBDCD_TIMER2_BC12_RD(x) & ~(v)))
-#define HW_USBDCD_TIMER2_BC12_TOG(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, HW_USBDCD_TIMER2_BC12_RD(x) ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual USBDCD_TIMER2_BC12 bitfields
- */
-
-/*!
- * @name Register USBDCD_TIMER2_BC12, field TVDMSRC_ON[9:0] (RW)
- *
- * Sets the amount of time (in ms) that the module enables the VDM_SRC. Valid
- * values are 0-40ms.
- */
-//@{
-#define BP_USBDCD_TIMER2_BC12_TVDMSRC_ON (0U) //!< Bit position for USBDCD_TIMER2_BC12_TVDMSRC_ON.
-#define BM_USBDCD_TIMER2_BC12_TVDMSRC_ON (0x000003FFU) //!< Bit mask for USBDCD_TIMER2_BC12_TVDMSRC_ON.
-#define BS_USBDCD_TIMER2_BC12_TVDMSRC_ON (10U) //!< Bit field size in bits for USBDCD_TIMER2_BC12_TVDMSRC_ON.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USBDCD_TIMER2_BC12_TVDMSRC_ON field.
-#define BR_USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (HW_USBDCD_TIMER2_BC12(x).B.TVDMSRC_ON)
-#endif
-
-//! @brief Format value for bitfield USBDCD_TIMER2_BC12_TVDMSRC_ON.
-#define BF_USBDCD_TIMER2_BC12_TVDMSRC_ON(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER2_BC12_TVDMSRC_ON), uint32_t) & BM_USBDCD_TIMER2_BC12_TVDMSRC_ON)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TVDMSRC_ON field to a new value.
-#define BW_USBDCD_TIMER2_BC12_TVDMSRC_ON(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, (HW_USBDCD_TIMER2_BC12_RD(x) & ~BM_USBDCD_TIMER2_BC12_TVDMSRC_ON) | BF_USBDCD_TIMER2_BC12_TVDMSRC_ON(v)))
-#endif
-//@}
-
-/*!
- * @name Register USBDCD_TIMER2_BC12, field TWAIT_AFTER_PRD[25:16] (RW)
- *
- * Sets the amount of time (in ms) that the module waits after primary detection
- * before start to secondary detection. Valid values are 1-1023ms. Default is
- * 1ms.
- */
-//@{
-#define BP_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD (16U) //!< Bit position for USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD.
-#define BM_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD (0x03FF0000U) //!< Bit mask for USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD.
-#define BS_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD (10U) //!< Bit field size in bits for USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD field.
-#define BR_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (HW_USBDCD_TIMER2_BC12(x).B.TWAIT_AFTER_PRD)
-#endif
-
-//! @brief Format value for bitfield USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD.
-#define BF_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD), uint32_t) & BM_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TWAIT_AFTER_PRD field to a new value.
-#define BW_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, (HW_USBDCD_TIMER2_BC12_RD(x) & ~BM_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD) | BF_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_usbdcd_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All USBDCD module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_usbdcd
-{
- __IO hw_usbdcd_control_t CONTROL; //!< [0x0] Control register
- __IO hw_usbdcd_clock_t CLOCK; //!< [0x4] Clock register
- __I hw_usbdcd_status_t STATUS; //!< [0x8] Status register
- uint8_t _reserved0[4];
- __IO hw_usbdcd_timer0_t TIMER0; //!< [0x10] TIMER0 register
- __IO hw_usbdcd_timer1_t TIMER1; //!< [0x14] TIMER1 register
- union {
- __IO hw_usbdcd_timer2_bc11_t TIMER2_BC11; //!< [0x18] TIMER2_BC11 register
- __IO hw_usbdcd_timer2_bc12_t TIMER2_BC12; //!< [0x18] TIMER2_BC12 register
- };
-} hw_usbdcd_t;
-#pragma pack()
-
-//! @brief Macro to access all USBDCD registers.
-//! @param x USBDCD instance number.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_USBDCD(0)</code>.
-#define HW_USBDCD(x) (*(hw_usbdcd_t *) REGS_USBDCD_BASE(x))
-#endif
-
-#endif // __HW_USBDCD_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_vref.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,369 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_VREF_REGISTERS_H__
-#define __HW_VREF_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 VREF
- *
- * Voltage Reference
- *
- * Registers defined in this header file:
- * - HW_VREF_TRM - VREF Trim Register
- * - HW_VREF_SC - VREF Status and Control Register
- *
- * - hw_vref_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_VREF_BASE
-#define HW_VREF_INSTANCE_COUNT (1U) //!< Number of instances of the VREF module.
-#define REGS_VREF_BASE (0x40074000U) //!< Base address for VREF.
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_VREF_TRM - VREF Trim Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_VREF_TRM - VREF Trim Register (RW)
- *
- * Reset value: 0x00U
- *
- * This register contains bits that contain the trim data for the Voltage
- * Reference.
- */
-typedef union _hw_vref_trm
-{
- uint8_t U;
- struct _hw_vref_trm_bitfields
- {
- uint8_t TRIM : 6; //!< [5:0] Trim bits
- uint8_t CHOPEN : 1; //!< [6] Chop oscillator enable. When set,
- //! internal chopping operation is enabled and the internal analog offset will
- //! be minimized.
- uint8_t RESERVED0 : 1; //!< [7]
- } B;
-} hw_vref_trm_t;
-#endif
-
-/*!
- * @name Constants and macros for entire VREF_TRM register
- */
-//@{
-#define HW_VREF_TRM_ADDR (REGS_VREF_BASE + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_VREF_TRM (*(__IO hw_vref_trm_t *) HW_VREF_TRM_ADDR)
-#define HW_VREF_TRM_RD() (HW_VREF_TRM.U)
-#define HW_VREF_TRM_WR(v) (HW_VREF_TRM.U = (v))
-#define HW_VREF_TRM_SET(v) (HW_VREF_TRM_WR(HW_VREF_TRM_RD() | (v)))
-#define HW_VREF_TRM_CLR(v) (HW_VREF_TRM_WR(HW_VREF_TRM_RD() & ~(v)))
-#define HW_VREF_TRM_TOG(v) (HW_VREF_TRM_WR(HW_VREF_TRM_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual VREF_TRM bitfields
- */
-
-/*!
- * @name Register VREF_TRM, field TRIM[5:0] (RW)
- *
- * These bits change the resulting VREF by approximately +/- 0.5 mV for each
- * step. Min = minimum and max = maximum voltage reference output. For minimum and
- * maximum voltage reference output values, refer to the Data Sheet for this chip.
- *
- * Values:
- * - 000000 - Min
- * - 111111 - Max
- */
-//@{
-#define BP_VREF_TRM_TRIM (0U) //!< Bit position for VREF_TRM_TRIM.
-#define BM_VREF_TRM_TRIM (0x3FU) //!< Bit mask for VREF_TRM_TRIM.
-#define BS_VREF_TRM_TRIM (6U) //!< Bit field size in bits for VREF_TRM_TRIM.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the VREF_TRM_TRIM field.
-#define BR_VREF_TRM_TRIM (HW_VREF_TRM.B.TRIM)
-#endif
-
-//! @brief Format value for bitfield VREF_TRM_TRIM.
-#define BF_VREF_TRM_TRIM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_TRM_TRIM), uint8_t) & BM_VREF_TRM_TRIM)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TRIM field to a new value.
-#define BW_VREF_TRM_TRIM(v) (HW_VREF_TRM_WR((HW_VREF_TRM_RD() & ~BM_VREF_TRM_TRIM) | BF_VREF_TRM_TRIM(v)))
-#endif
-//@}
-
-/*!
- * @name Register VREF_TRM, field CHOPEN[6] (RW)
- *
- * This bit is set during factory trimming of the VREF voltage. This bit should
- * be written to 1 to achieve the performance stated in the data sheet.
- *
- * Values:
- * - 0 - Chop oscillator is disabled.
- * - 1 - Chop oscillator is enabled.
- */
-//@{
-#define BP_VREF_TRM_CHOPEN (6U) //!< Bit position for VREF_TRM_CHOPEN.
-#define BM_VREF_TRM_CHOPEN (0x40U) //!< Bit mask for VREF_TRM_CHOPEN.
-#define BS_VREF_TRM_CHOPEN (1U) //!< Bit field size in bits for VREF_TRM_CHOPEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the VREF_TRM_CHOPEN field.
-#define BR_VREF_TRM_CHOPEN (BITBAND_ACCESS8(HW_VREF_TRM_ADDR, BP_VREF_TRM_CHOPEN))
-#endif
-
-//! @brief Format value for bitfield VREF_TRM_CHOPEN.
-#define BF_VREF_TRM_CHOPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_TRM_CHOPEN), uint8_t) & BM_VREF_TRM_CHOPEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CHOPEN field to a new value.
-#define BW_VREF_TRM_CHOPEN(v) (BITBAND_ACCESS8(HW_VREF_TRM_ADDR, BP_VREF_TRM_CHOPEN) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_VREF_SC - VREF Status and Control Register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_VREF_SC - VREF Status and Control Register (RW)
- *
- * Reset value: 0x00U
- *
- * This register contains the control bits used to enable the internal voltage
- * reference and to select the buffer mode to be used.
- */
-typedef union _hw_vref_sc
-{
- uint8_t U;
- struct _hw_vref_sc_bitfields
- {
- uint8_t MODE_LV : 2; //!< [1:0] Buffer Mode selection
- uint8_t VREFST : 1; //!< [2] Internal Voltage Reference stable
- uint8_t RESERVED0 : 2; //!< [4:3]
- uint8_t ICOMPEN : 1; //!< [5] Second order curvature compensation
- //! enable
- uint8_t REGEN : 1; //!< [6] Regulator enable
- uint8_t VREFEN : 1; //!< [7] Internal Voltage Reference enable
- } B;
-} hw_vref_sc_t;
-#endif
-
-/*!
- * @name Constants and macros for entire VREF_SC register
- */
-//@{
-#define HW_VREF_SC_ADDR (REGS_VREF_BASE + 0x1U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_VREF_SC (*(__IO hw_vref_sc_t *) HW_VREF_SC_ADDR)
-#define HW_VREF_SC_RD() (HW_VREF_SC.U)
-#define HW_VREF_SC_WR(v) (HW_VREF_SC.U = (v))
-#define HW_VREF_SC_SET(v) (HW_VREF_SC_WR(HW_VREF_SC_RD() | (v)))
-#define HW_VREF_SC_CLR(v) (HW_VREF_SC_WR(HW_VREF_SC_RD() & ~(v)))
-#define HW_VREF_SC_TOG(v) (HW_VREF_SC_WR(HW_VREF_SC_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual VREF_SC bitfields
- */
-
-/*!
- * @name Register VREF_SC, field MODE_LV[1:0] (RW)
- *
- * These bits select the buffer modes for the Voltage Reference module.
- *
- * Values:
- * - 00 - Bandgap on only, for stabilization and startup
- * - 01 - High power buffer mode enabled
- * - 10 - Low-power buffer mode enabled
- * - 11 - Reserved
- */
-//@{
-#define BP_VREF_SC_MODE_LV (0U) //!< Bit position for VREF_SC_MODE_LV.
-#define BM_VREF_SC_MODE_LV (0x03U) //!< Bit mask for VREF_SC_MODE_LV.
-#define BS_VREF_SC_MODE_LV (2U) //!< Bit field size in bits for VREF_SC_MODE_LV.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the VREF_SC_MODE_LV field.
-#define BR_VREF_SC_MODE_LV (HW_VREF_SC.B.MODE_LV)
-#endif
-
-//! @brief Format value for bitfield VREF_SC_MODE_LV.
-#define BF_VREF_SC_MODE_LV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_SC_MODE_LV), uint8_t) & BM_VREF_SC_MODE_LV)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the MODE_LV field to a new value.
-#define BW_VREF_SC_MODE_LV(v) (HW_VREF_SC_WR((HW_VREF_SC_RD() & ~BM_VREF_SC_MODE_LV) | BF_VREF_SC_MODE_LV(v)))
-#endif
-//@}
-
-/*!
- * @name Register VREF_SC, field VREFST[2] (RO)
- *
- * This bit indicates that the bandgap reference within the Voltage Reference
- * module has completed its startup and stabilization.
- *
- * Values:
- * - 0 - The module is disabled or not stable.
- * - 1 - The module is stable.
- */
-//@{
-#define BP_VREF_SC_VREFST (2U) //!< Bit position for VREF_SC_VREFST.
-#define BM_VREF_SC_VREFST (0x04U) //!< Bit mask for VREF_SC_VREFST.
-#define BS_VREF_SC_VREFST (1U) //!< Bit field size in bits for VREF_SC_VREFST.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the VREF_SC_VREFST field.
-#define BR_VREF_SC_VREFST (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_VREFST))
-#endif
-//@}
-
-/*!
- * @name Register VREF_SC, field ICOMPEN[5] (RW)
- *
- * This bit is set during factory trimming of the VREF voltage. This bit should
- * be written to 1 to achieve the performance stated in the data sheet.
- *
- * Values:
- * - 0 - Disabled
- * - 1 - Enabled
- */
-//@{
-#define BP_VREF_SC_ICOMPEN (5U) //!< Bit position for VREF_SC_ICOMPEN.
-#define BM_VREF_SC_ICOMPEN (0x20U) //!< Bit mask for VREF_SC_ICOMPEN.
-#define BS_VREF_SC_ICOMPEN (1U) //!< Bit field size in bits for VREF_SC_ICOMPEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the VREF_SC_ICOMPEN field.
-#define BR_VREF_SC_ICOMPEN (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_ICOMPEN))
-#endif
-
-//! @brief Format value for bitfield VREF_SC_ICOMPEN.
-#define BF_VREF_SC_ICOMPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_SC_ICOMPEN), uint8_t) & BM_VREF_SC_ICOMPEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ICOMPEN field to a new value.
-#define BW_VREF_SC_ICOMPEN(v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_ICOMPEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register VREF_SC, field REGEN[6] (RW)
- *
- * This bit is used to enable the internal 1.75 V regulator to produce a
- * constant internal voltage supply in order to reduce the sensitivity to external
- * supply noise and variation. If it is desired to keep the regulator enabled in very
- * low power modes, refer to the Chip Configuration details for a description on
- * how this can be achieved. This bit is set during factory trimming of the VREF
- * voltage. This bit should be written to 1 to achieve the performance stated in
- * the data sheet.
- *
- * Values:
- * - 0 - Internal 1.75 V regulator is disabled.
- * - 1 - Internal 1.75 V regulator is enabled.
- */
-//@{
-#define BP_VREF_SC_REGEN (6U) //!< Bit position for VREF_SC_REGEN.
-#define BM_VREF_SC_REGEN (0x40U) //!< Bit mask for VREF_SC_REGEN.
-#define BS_VREF_SC_REGEN (1U) //!< Bit field size in bits for VREF_SC_REGEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the VREF_SC_REGEN field.
-#define BR_VREF_SC_REGEN (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_REGEN))
-#endif
-
-//! @brief Format value for bitfield VREF_SC_REGEN.
-#define BF_VREF_SC_REGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_SC_REGEN), uint8_t) & BM_VREF_SC_REGEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the REGEN field to a new value.
-#define BW_VREF_SC_REGEN(v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_REGEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register VREF_SC, field VREFEN[7] (RW)
- *
- * This bit is used to enable the bandgap reference within the Voltage Reference
- * module. After the VREF is enabled, turning off the clock to the VREF module
- * via the corresponding clock gate register will not disable the VREF. VREF must
- * be disabled via this VREFEN bit.
- *
- * Values:
- * - 0 - The module is disabled.
- * - 1 - The module is enabled.
- */
-//@{
-#define BP_VREF_SC_VREFEN (7U) //!< Bit position for VREF_SC_VREFEN.
-#define BM_VREF_SC_VREFEN (0x80U) //!< Bit mask for VREF_SC_VREFEN.
-#define BS_VREF_SC_VREFEN (1U) //!< Bit field size in bits for VREF_SC_VREFEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the VREF_SC_VREFEN field.
-#define BR_VREF_SC_VREFEN (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_VREFEN))
-#endif
-
-//! @brief Format value for bitfield VREF_SC_VREFEN.
-#define BF_VREF_SC_VREFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_SC_VREFEN), uint8_t) & BM_VREF_SC_VREFEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the VREFEN field to a new value.
-#define BW_VREF_SC_VREFEN(v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_VREFEN) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_vref_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All VREF module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_vref
-{
- __IO hw_vref_trm_t TRM; //!< [0x0] VREF Trim Register
- __IO hw_vref_sc_t SC; //!< [0x1] VREF Status and Control Register
-} hw_vref_t;
-#pragma pack()
-
-//! @brief Macro to access all VREF registers.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_VREF</code>.
-#define HW_VREF (*(hw_vref_t *) REGS_VREF_BASE)
-#endif
-
-#endif // __HW_VREF_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_wdog.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1244 +0,0 @@
-/*
- * Copyright (c) 2014, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
- *
- * This file was generated automatically and any changes may be lost.
- */
-#ifndef __HW_WDOG_REGISTERS_H__
-#define __HW_WDOG_REGISTERS_H__
-
-#include "regs.h"
-
-/*
- * MK64F12 WDOG
- *
- * Generation 2008 Watchdog Timer
- *
- * Registers defined in this header file:
- * - HW_WDOG_STCTRLH - Watchdog Status and Control Register High
- * - HW_WDOG_STCTRLL - Watchdog Status and Control Register Low
- * - HW_WDOG_TOVALH - Watchdog Time-out Value Register High
- * - HW_WDOG_TOVALL - Watchdog Time-out Value Register Low
- * - HW_WDOG_WINH - Watchdog Window Register High
- * - HW_WDOG_WINL - Watchdog Window Register Low
- * - HW_WDOG_REFRESH - Watchdog Refresh register
- * - HW_WDOG_UNLOCK - Watchdog Unlock register
- * - HW_WDOG_TMROUTH - Watchdog Timer Output Register High
- * - HW_WDOG_TMROUTL - Watchdog Timer Output Register Low
- * - HW_WDOG_RSTCNT - Watchdog Reset Count register
- * - HW_WDOG_PRESC - Watchdog Prescaler register
- *
- * - hw_wdog_t - Struct containing all module registers.
- */
-
-//! @name Module base addresses
-//@{
-#ifndef REGS_WDOG_BASE
-#define HW_WDOG_INSTANCE_COUNT (1U) //!< Number of instances of the WDOG module.
-#define REGS_WDOG_BASE (0x40052000U) //!< Base address for WDOG.
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_WDOG_STCTRLH - Watchdog Status and Control Register High
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_WDOG_STCTRLH - Watchdog Status and Control Register High (RW)
- *
- * Reset value: 0x01D3U
- */
-typedef union _hw_wdog_stctrlh
-{
- uint16_t U;
- struct _hw_wdog_stctrlh_bitfields
- {
- uint16_t WDOGEN : 1; //!< [0]
- uint16_t CLKSRC : 1; //!< [1]
- uint16_t IRQRSTEN : 1; //!< [2]
- uint16_t WINEN : 1; //!< [3]
- uint16_t ALLOWUPDATE : 1; //!< [4]
- uint16_t DBGEN : 1; //!< [5]
- uint16_t STOPEN : 1; //!< [6]
- uint16_t WAITEN : 1; //!< [7]
- uint16_t RESERVED0 : 2; //!< [9:8]
- uint16_t TESTWDOG : 1; //!< [10]
- uint16_t TESTSEL : 1; //!< [11]
- uint16_t BYTESEL : 2; //!< [13:12]
- uint16_t DISTESTWDOG : 1; //!< [14]
- uint16_t RESERVED1 : 1; //!< [15]
- } B;
-} hw_wdog_stctrlh_t;
-#endif
-
-/*!
- * @name Constants and macros for entire WDOG_STCTRLH register
- */
-//@{
-#define HW_WDOG_STCTRLH_ADDR (REGS_WDOG_BASE + 0x0U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_WDOG_STCTRLH (*(__IO hw_wdog_stctrlh_t *) HW_WDOG_STCTRLH_ADDR)
-#define HW_WDOG_STCTRLH_RD() (HW_WDOG_STCTRLH.U)
-#define HW_WDOG_STCTRLH_WR(v) (HW_WDOG_STCTRLH.U = (v))
-#define HW_WDOG_STCTRLH_SET(v) (HW_WDOG_STCTRLH_WR(HW_WDOG_STCTRLH_RD() | (v)))
-#define HW_WDOG_STCTRLH_CLR(v) (HW_WDOG_STCTRLH_WR(HW_WDOG_STCTRLH_RD() & ~(v)))
-#define HW_WDOG_STCTRLH_TOG(v) (HW_WDOG_STCTRLH_WR(HW_WDOG_STCTRLH_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual WDOG_STCTRLH bitfields
- */
-
-/*!
- * @name Register WDOG_STCTRLH, field WDOGEN[0] (RW)
- *
- * Enables or disables the WDOG's operation. In the disabled state, the watchdog
- * timer is kept in the reset state, but the other exception conditions can
- * still trigger a reset/interrupt. A change in the value of this bit must be held
- * for more than one WDOG_CLK cycle for the WDOG to be enabled or disabled.
- *
- * Values:
- * - 0 - WDOG is disabled.
- * - 1 - WDOG is enabled.
- */
-//@{
-#define BP_WDOG_STCTRLH_WDOGEN (0U) //!< Bit position for WDOG_STCTRLH_WDOGEN.
-#define BM_WDOG_STCTRLH_WDOGEN (0x0001U) //!< Bit mask for WDOG_STCTRLH_WDOGEN.
-#define BS_WDOG_STCTRLH_WDOGEN (1U) //!< Bit field size in bits for WDOG_STCTRLH_WDOGEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the WDOG_STCTRLH_WDOGEN field.
-#define BR_WDOG_STCTRLH_WDOGEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WDOGEN))
-#endif
-
-//! @brief Format value for bitfield WDOG_STCTRLH_WDOGEN.
-#define BF_WDOG_STCTRLH_WDOGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_WDOGEN), uint16_t) & BM_WDOG_STCTRLH_WDOGEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WDOGEN field to a new value.
-#define BW_WDOG_STCTRLH_WDOGEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WDOGEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register WDOG_STCTRLH, field CLKSRC[1] (RW)
- *
- * Selects clock source for the WDOG timer and other internal timing operations.
- *
- * Values:
- * - 0 - WDOG clock sourced from LPO .
- * - 1 - WDOG clock sourced from alternate clock source.
- */
-//@{
-#define BP_WDOG_STCTRLH_CLKSRC (1U) //!< Bit position for WDOG_STCTRLH_CLKSRC.
-#define BM_WDOG_STCTRLH_CLKSRC (0x0002U) //!< Bit mask for WDOG_STCTRLH_CLKSRC.
-#define BS_WDOG_STCTRLH_CLKSRC (1U) //!< Bit field size in bits for WDOG_STCTRLH_CLKSRC.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the WDOG_STCTRLH_CLKSRC field.
-#define BR_WDOG_STCTRLH_CLKSRC (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_CLKSRC))
-#endif
-
-//! @brief Format value for bitfield WDOG_STCTRLH_CLKSRC.
-#define BF_WDOG_STCTRLH_CLKSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_CLKSRC), uint16_t) & BM_WDOG_STCTRLH_CLKSRC)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the CLKSRC field to a new value.
-#define BW_WDOG_STCTRLH_CLKSRC(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_CLKSRC) = (v))
-#endif
-//@}
-
-/*!
- * @name Register WDOG_STCTRLH, field IRQRSTEN[2] (RW)
- *
- * Used to enable the debug breadcrumbs feature. A change in this bit is updated
- * immediately, as opposed to updating after WCT.
- *
- * Values:
- * - 0 - WDOG time-out generates reset only.
- * - 1 - WDOG time-out initially generates an interrupt. After WCT, it generates
- * a reset.
- */
-//@{
-#define BP_WDOG_STCTRLH_IRQRSTEN (2U) //!< Bit position for WDOG_STCTRLH_IRQRSTEN.
-#define BM_WDOG_STCTRLH_IRQRSTEN (0x0004U) //!< Bit mask for WDOG_STCTRLH_IRQRSTEN.
-#define BS_WDOG_STCTRLH_IRQRSTEN (1U) //!< Bit field size in bits for WDOG_STCTRLH_IRQRSTEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the WDOG_STCTRLH_IRQRSTEN field.
-#define BR_WDOG_STCTRLH_IRQRSTEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_IRQRSTEN))
-#endif
-
-//! @brief Format value for bitfield WDOG_STCTRLH_IRQRSTEN.
-#define BF_WDOG_STCTRLH_IRQRSTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_IRQRSTEN), uint16_t) & BM_WDOG_STCTRLH_IRQRSTEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the IRQRSTEN field to a new value.
-#define BW_WDOG_STCTRLH_IRQRSTEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_IRQRSTEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register WDOG_STCTRLH, field WINEN[3] (RW)
- *
- * Enables Windowing mode.
- *
- * Values:
- * - 0 - Windowing mode is disabled.
- * - 1 - Windowing mode is enabled.
- */
-//@{
-#define BP_WDOG_STCTRLH_WINEN (3U) //!< Bit position for WDOG_STCTRLH_WINEN.
-#define BM_WDOG_STCTRLH_WINEN (0x0008U) //!< Bit mask for WDOG_STCTRLH_WINEN.
-#define BS_WDOG_STCTRLH_WINEN (1U) //!< Bit field size in bits for WDOG_STCTRLH_WINEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the WDOG_STCTRLH_WINEN field.
-#define BR_WDOG_STCTRLH_WINEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WINEN))
-#endif
-
-//! @brief Format value for bitfield WDOG_STCTRLH_WINEN.
-#define BF_WDOG_STCTRLH_WINEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_WINEN), uint16_t) & BM_WDOG_STCTRLH_WINEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WINEN field to a new value.
-#define BW_WDOG_STCTRLH_WINEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WINEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register WDOG_STCTRLH, field ALLOWUPDATE[4] (RW)
- *
- * Enables updates to watchdog write-once registers, after the reset-triggered
- * initial configuration window (WCT) closes, through unlock sequence.
- *
- * Values:
- * - 0 - No further updates allowed to WDOG write-once registers.
- * - 1 - WDOG write-once registers can be unlocked for updating.
- */
-//@{
-#define BP_WDOG_STCTRLH_ALLOWUPDATE (4U) //!< Bit position for WDOG_STCTRLH_ALLOWUPDATE.
-#define BM_WDOG_STCTRLH_ALLOWUPDATE (0x0010U) //!< Bit mask for WDOG_STCTRLH_ALLOWUPDATE.
-#define BS_WDOG_STCTRLH_ALLOWUPDATE (1U) //!< Bit field size in bits for WDOG_STCTRLH_ALLOWUPDATE.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the WDOG_STCTRLH_ALLOWUPDATE field.
-#define BR_WDOG_STCTRLH_ALLOWUPDATE (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_ALLOWUPDATE))
-#endif
-
-//! @brief Format value for bitfield WDOG_STCTRLH_ALLOWUPDATE.
-#define BF_WDOG_STCTRLH_ALLOWUPDATE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_ALLOWUPDATE), uint16_t) & BM_WDOG_STCTRLH_ALLOWUPDATE)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the ALLOWUPDATE field to a new value.
-#define BW_WDOG_STCTRLH_ALLOWUPDATE(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_ALLOWUPDATE) = (v))
-#endif
-//@}
-
-/*!
- * @name Register WDOG_STCTRLH, field DBGEN[5] (RW)
- *
- * Enables or disables WDOG in Debug mode.
- *
- * Values:
- * - 0 - WDOG is disabled in CPU Debug mode.
- * - 1 - WDOG is enabled in CPU Debug mode.
- */
-//@{
-#define BP_WDOG_STCTRLH_DBGEN (5U) //!< Bit position for WDOG_STCTRLH_DBGEN.
-#define BM_WDOG_STCTRLH_DBGEN (0x0020U) //!< Bit mask for WDOG_STCTRLH_DBGEN.
-#define BS_WDOG_STCTRLH_DBGEN (1U) //!< Bit field size in bits for WDOG_STCTRLH_DBGEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the WDOG_STCTRLH_DBGEN field.
-#define BR_WDOG_STCTRLH_DBGEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_DBGEN))
-#endif
-
-//! @brief Format value for bitfield WDOG_STCTRLH_DBGEN.
-#define BF_WDOG_STCTRLH_DBGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_DBGEN), uint16_t) & BM_WDOG_STCTRLH_DBGEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DBGEN field to a new value.
-#define BW_WDOG_STCTRLH_DBGEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_DBGEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register WDOG_STCTRLH, field STOPEN[6] (RW)
- *
- * Enables or disables WDOG in Stop mode.
- *
- * Values:
- * - 0 - WDOG is disabled in CPU Stop mode.
- * - 1 - WDOG is enabled in CPU Stop mode.
- */
-//@{
-#define BP_WDOG_STCTRLH_STOPEN (6U) //!< Bit position for WDOG_STCTRLH_STOPEN.
-#define BM_WDOG_STCTRLH_STOPEN (0x0040U) //!< Bit mask for WDOG_STCTRLH_STOPEN.
-#define BS_WDOG_STCTRLH_STOPEN (1U) //!< Bit field size in bits for WDOG_STCTRLH_STOPEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the WDOG_STCTRLH_STOPEN field.
-#define BR_WDOG_STCTRLH_STOPEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_STOPEN))
-#endif
-
-//! @brief Format value for bitfield WDOG_STCTRLH_STOPEN.
-#define BF_WDOG_STCTRLH_STOPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_STOPEN), uint16_t) & BM_WDOG_STCTRLH_STOPEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the STOPEN field to a new value.
-#define BW_WDOG_STCTRLH_STOPEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_STOPEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register WDOG_STCTRLH, field WAITEN[7] (RW)
- *
- * Enables or disables WDOG in Wait mode.
- *
- * Values:
- * - 0 - WDOG is disabled in CPU Wait mode.
- * - 1 - WDOG is enabled in CPU Wait mode.
- */
-//@{
-#define BP_WDOG_STCTRLH_WAITEN (7U) //!< Bit position for WDOG_STCTRLH_WAITEN.
-#define BM_WDOG_STCTRLH_WAITEN (0x0080U) //!< Bit mask for WDOG_STCTRLH_WAITEN.
-#define BS_WDOG_STCTRLH_WAITEN (1U) //!< Bit field size in bits for WDOG_STCTRLH_WAITEN.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the WDOG_STCTRLH_WAITEN field.
-#define BR_WDOG_STCTRLH_WAITEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WAITEN))
-#endif
-
-//! @brief Format value for bitfield WDOG_STCTRLH_WAITEN.
-#define BF_WDOG_STCTRLH_WAITEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_WAITEN), uint16_t) & BM_WDOG_STCTRLH_WAITEN)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WAITEN field to a new value.
-#define BW_WDOG_STCTRLH_WAITEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WAITEN) = (v))
-#endif
-//@}
-
-/*!
- * @name Register WDOG_STCTRLH, field TESTWDOG[10] (RW)
- *
- * Puts the watchdog in the functional test mode. In this mode, the watchdog
- * timer and the associated compare and reset generation logic is tested for correct
- * operation. The clock for the timer is switched from the main watchdog clock
- * to the fast clock input for watchdog functional test. The TESTSEL bit selects
- * the test to be run.
- */
-//@{
-#define BP_WDOG_STCTRLH_TESTWDOG (10U) //!< Bit position for WDOG_STCTRLH_TESTWDOG.
-#define BM_WDOG_STCTRLH_TESTWDOG (0x0400U) //!< Bit mask for WDOG_STCTRLH_TESTWDOG.
-#define BS_WDOG_STCTRLH_TESTWDOG (1U) //!< Bit field size in bits for WDOG_STCTRLH_TESTWDOG.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the WDOG_STCTRLH_TESTWDOG field.
-#define BR_WDOG_STCTRLH_TESTWDOG (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_TESTWDOG))
-#endif
-
-//! @brief Format value for bitfield WDOG_STCTRLH_TESTWDOG.
-#define BF_WDOG_STCTRLH_TESTWDOG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_TESTWDOG), uint16_t) & BM_WDOG_STCTRLH_TESTWDOG)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TESTWDOG field to a new value.
-#define BW_WDOG_STCTRLH_TESTWDOG(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_TESTWDOG) = (v))
-#endif
-//@}
-
-/*!
- * @name Register WDOG_STCTRLH, field TESTSEL[11] (RW)
- *
- * Effective only if TESTWDOG is set. Selects the test to be run on the watchdog
- * timer.
- *
- * Values:
- * - 0 - Quick test. The timer runs in normal operation. You can load a small
- * time-out value to do a quick test.
- * - 1 - Byte test. Puts the timer in the byte test mode where individual bytes
- * of the timer are enabled for operation and are compared for time-out
- * against the corresponding byte of the programmed time-out value. Select the
- * byte through BYTESEL[1:0] for testing.
- */
-//@{
-#define BP_WDOG_STCTRLH_TESTSEL (11U) //!< Bit position for WDOG_STCTRLH_TESTSEL.
-#define BM_WDOG_STCTRLH_TESTSEL (0x0800U) //!< Bit mask for WDOG_STCTRLH_TESTSEL.
-#define BS_WDOG_STCTRLH_TESTSEL (1U) //!< Bit field size in bits for WDOG_STCTRLH_TESTSEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the WDOG_STCTRLH_TESTSEL field.
-#define BR_WDOG_STCTRLH_TESTSEL (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_TESTSEL))
-#endif
-
-//! @brief Format value for bitfield WDOG_STCTRLH_TESTSEL.
-#define BF_WDOG_STCTRLH_TESTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_TESTSEL), uint16_t) & BM_WDOG_STCTRLH_TESTSEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TESTSEL field to a new value.
-#define BW_WDOG_STCTRLH_TESTSEL(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_TESTSEL) = (v))
-#endif
-//@}
-
-/*!
- * @name Register WDOG_STCTRLH, field BYTESEL[13:12] (RW)
- *
- * This 2-bit field selects the byte to be tested when the watchdog is in the
- * byte test mode.
- *
- * Values:
- * - 00 - Byte 0 selected
- * - 01 - Byte 1 selected
- * - 10 - Byte 2 selected
- * - 11 - Byte 3 selected
- */
-//@{
-#define BP_WDOG_STCTRLH_BYTESEL (12U) //!< Bit position for WDOG_STCTRLH_BYTESEL.
-#define BM_WDOG_STCTRLH_BYTESEL (0x3000U) //!< Bit mask for WDOG_STCTRLH_BYTESEL.
-#define BS_WDOG_STCTRLH_BYTESEL (2U) //!< Bit field size in bits for WDOG_STCTRLH_BYTESEL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the WDOG_STCTRLH_BYTESEL field.
-#define BR_WDOG_STCTRLH_BYTESEL (HW_WDOG_STCTRLH.B.BYTESEL)
-#endif
-
-//! @brief Format value for bitfield WDOG_STCTRLH_BYTESEL.
-#define BF_WDOG_STCTRLH_BYTESEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_BYTESEL), uint16_t) & BM_WDOG_STCTRLH_BYTESEL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the BYTESEL field to a new value.
-#define BW_WDOG_STCTRLH_BYTESEL(v) (HW_WDOG_STCTRLH_WR((HW_WDOG_STCTRLH_RD() & ~BM_WDOG_STCTRLH_BYTESEL) | BF_WDOG_STCTRLH_BYTESEL(v)))
-#endif
-//@}
-
-/*!
- * @name Register WDOG_STCTRLH, field DISTESTWDOG[14] (RW)
- *
- * Allows the WDOG's functional test mode to be disabled permanently. After it
- * is set, it can only be cleared by a reset. It cannot be unlocked for editing
- * after it is set.
- *
- * Values:
- * - 0 - WDOG functional test mode is not disabled.
- * - 1 - WDOG functional test mode is disabled permanently until reset.
- */
-//@{
-#define BP_WDOG_STCTRLH_DISTESTWDOG (14U) //!< Bit position for WDOG_STCTRLH_DISTESTWDOG.
-#define BM_WDOG_STCTRLH_DISTESTWDOG (0x4000U) //!< Bit mask for WDOG_STCTRLH_DISTESTWDOG.
-#define BS_WDOG_STCTRLH_DISTESTWDOG (1U) //!< Bit field size in bits for WDOG_STCTRLH_DISTESTWDOG.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the WDOG_STCTRLH_DISTESTWDOG field.
-#define BR_WDOG_STCTRLH_DISTESTWDOG (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_DISTESTWDOG))
-#endif
-
-//! @brief Format value for bitfield WDOG_STCTRLH_DISTESTWDOG.
-#define BF_WDOG_STCTRLH_DISTESTWDOG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_DISTESTWDOG), uint16_t) & BM_WDOG_STCTRLH_DISTESTWDOG)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the DISTESTWDOG field to a new value.
-#define BW_WDOG_STCTRLH_DISTESTWDOG(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_DISTESTWDOG) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_WDOG_STCTRLL - Watchdog Status and Control Register Low
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_WDOG_STCTRLL - Watchdog Status and Control Register Low (RW)
- *
- * Reset value: 0x0001U
- */
-typedef union _hw_wdog_stctrll
-{
- uint16_t U;
- struct _hw_wdog_stctrll_bitfields
- {
- uint16_t RESERVED0 : 15; //!< [14:0]
- uint16_t INTFLG : 1; //!< [15]
- } B;
-} hw_wdog_stctrll_t;
-#endif
-
-/*!
- * @name Constants and macros for entire WDOG_STCTRLL register
- */
-//@{
-#define HW_WDOG_STCTRLL_ADDR (REGS_WDOG_BASE + 0x2U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_WDOG_STCTRLL (*(__IO hw_wdog_stctrll_t *) HW_WDOG_STCTRLL_ADDR)
-#define HW_WDOG_STCTRLL_RD() (HW_WDOG_STCTRLL.U)
-#define HW_WDOG_STCTRLL_WR(v) (HW_WDOG_STCTRLL.U = (v))
-#define HW_WDOG_STCTRLL_SET(v) (HW_WDOG_STCTRLL_WR(HW_WDOG_STCTRLL_RD() | (v)))
-#define HW_WDOG_STCTRLL_CLR(v) (HW_WDOG_STCTRLL_WR(HW_WDOG_STCTRLL_RD() & ~(v)))
-#define HW_WDOG_STCTRLL_TOG(v) (HW_WDOG_STCTRLL_WR(HW_WDOG_STCTRLL_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual WDOG_STCTRLL bitfields
- */
-
-/*!
- * @name Register WDOG_STCTRLL, field INTFLG[15] (RW)
- *
- * Interrupt flag. It is set when an exception occurs. IRQRSTEN = 1 is a
- * precondition to set this flag. INTFLG = 1 results in an interrupt being issued
- * followed by a reset, WCT later. The interrupt can be cleared by writing 1 to this
- * bit. It also gets cleared on a system reset.
- */
-//@{
-#define BP_WDOG_STCTRLL_INTFLG (15U) //!< Bit position for WDOG_STCTRLL_INTFLG.
-#define BM_WDOG_STCTRLL_INTFLG (0x8000U) //!< Bit mask for WDOG_STCTRLL_INTFLG.
-#define BS_WDOG_STCTRLL_INTFLG (1U) //!< Bit field size in bits for WDOG_STCTRLL_INTFLG.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the WDOG_STCTRLL_INTFLG field.
-#define BR_WDOG_STCTRLL_INTFLG (BITBAND_ACCESS16(HW_WDOG_STCTRLL_ADDR, BP_WDOG_STCTRLL_INTFLG))
-#endif
-
-//! @brief Format value for bitfield WDOG_STCTRLL_INTFLG.
-#define BF_WDOG_STCTRLL_INTFLG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLL_INTFLG), uint16_t) & BM_WDOG_STCTRLL_INTFLG)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the INTFLG field to a new value.
-#define BW_WDOG_STCTRLL_INTFLG(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLL_ADDR, BP_WDOG_STCTRLL_INTFLG) = (v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_WDOG_TOVALH - Watchdog Time-out Value Register High
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_WDOG_TOVALH - Watchdog Time-out Value Register High (RW)
- *
- * Reset value: 0x004CU
- */
-typedef union _hw_wdog_tovalh
-{
- uint16_t U;
- struct _hw_wdog_tovalh_bitfields
- {
- uint16_t TOVALHIGH : 16; //!< [15:0]
- } B;
-} hw_wdog_tovalh_t;
-#endif
-
-/*!
- * @name Constants and macros for entire WDOG_TOVALH register
- */
-//@{
-#define HW_WDOG_TOVALH_ADDR (REGS_WDOG_BASE + 0x4U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_WDOG_TOVALH (*(__IO hw_wdog_tovalh_t *) HW_WDOG_TOVALH_ADDR)
-#define HW_WDOG_TOVALH_RD() (HW_WDOG_TOVALH.U)
-#define HW_WDOG_TOVALH_WR(v) (HW_WDOG_TOVALH.U = (v))
-#define HW_WDOG_TOVALH_SET(v) (HW_WDOG_TOVALH_WR(HW_WDOG_TOVALH_RD() | (v)))
-#define HW_WDOG_TOVALH_CLR(v) (HW_WDOG_TOVALH_WR(HW_WDOG_TOVALH_RD() & ~(v)))
-#define HW_WDOG_TOVALH_TOG(v) (HW_WDOG_TOVALH_WR(HW_WDOG_TOVALH_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual WDOG_TOVALH bitfields
- */
-
-/*!
- * @name Register WDOG_TOVALH, field TOVALHIGH[15:0] (RW)
- *
- * Defines the upper 16 bits of the 32-bit time-out value for the watchdog
- * timer. It is defined in terms of cycles of the watchdog clock.
- */
-//@{
-#define BP_WDOG_TOVALH_TOVALHIGH (0U) //!< Bit position for WDOG_TOVALH_TOVALHIGH.
-#define BM_WDOG_TOVALH_TOVALHIGH (0xFFFFU) //!< Bit mask for WDOG_TOVALH_TOVALHIGH.
-#define BS_WDOG_TOVALH_TOVALHIGH (16U) //!< Bit field size in bits for WDOG_TOVALH_TOVALHIGH.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the WDOG_TOVALH_TOVALHIGH field.
-#define BR_WDOG_TOVALH_TOVALHIGH (HW_WDOG_TOVALH.U)
-#endif
-
-//! @brief Format value for bitfield WDOG_TOVALH_TOVALHIGH.
-#define BF_WDOG_TOVALH_TOVALHIGH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_TOVALH_TOVALHIGH), uint16_t) & BM_WDOG_TOVALH_TOVALHIGH)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TOVALHIGH field to a new value.
-#define BW_WDOG_TOVALH_TOVALHIGH(v) (HW_WDOG_TOVALH_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_WDOG_TOVALL - Watchdog Time-out Value Register Low
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_WDOG_TOVALL - Watchdog Time-out Value Register Low (RW)
- *
- * Reset value: 0x4B4CU
- *
- * The time-out value of the watchdog must be set to a minimum of four watchdog
- * clock cycles. This is to take into account the delay in new settings taking
- * effect in the watchdog clock domain.
- */
-typedef union _hw_wdog_tovall
-{
- uint16_t U;
- struct _hw_wdog_tovall_bitfields
- {
- uint16_t TOVALLOW : 16; //!< [15:0]
- } B;
-} hw_wdog_tovall_t;
-#endif
-
-/*!
- * @name Constants and macros for entire WDOG_TOVALL register
- */
-//@{
-#define HW_WDOG_TOVALL_ADDR (REGS_WDOG_BASE + 0x6U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_WDOG_TOVALL (*(__IO hw_wdog_tovall_t *) HW_WDOG_TOVALL_ADDR)
-#define HW_WDOG_TOVALL_RD() (HW_WDOG_TOVALL.U)
-#define HW_WDOG_TOVALL_WR(v) (HW_WDOG_TOVALL.U = (v))
-#define HW_WDOG_TOVALL_SET(v) (HW_WDOG_TOVALL_WR(HW_WDOG_TOVALL_RD() | (v)))
-#define HW_WDOG_TOVALL_CLR(v) (HW_WDOG_TOVALL_WR(HW_WDOG_TOVALL_RD() & ~(v)))
-#define HW_WDOG_TOVALL_TOG(v) (HW_WDOG_TOVALL_WR(HW_WDOG_TOVALL_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual WDOG_TOVALL bitfields
- */
-
-/*!
- * @name Register WDOG_TOVALL, field TOVALLOW[15:0] (RW)
- *
- * Defines the lower 16 bits of the 32-bit time-out value for the watchdog
- * timer. It is defined in terms of cycles of the watchdog clock.
- */
-//@{
-#define BP_WDOG_TOVALL_TOVALLOW (0U) //!< Bit position for WDOG_TOVALL_TOVALLOW.
-#define BM_WDOG_TOVALL_TOVALLOW (0xFFFFU) //!< Bit mask for WDOG_TOVALL_TOVALLOW.
-#define BS_WDOG_TOVALL_TOVALLOW (16U) //!< Bit field size in bits for WDOG_TOVALL_TOVALLOW.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the WDOG_TOVALL_TOVALLOW field.
-#define BR_WDOG_TOVALL_TOVALLOW (HW_WDOG_TOVALL.U)
-#endif
-
-//! @brief Format value for bitfield WDOG_TOVALL_TOVALLOW.
-#define BF_WDOG_TOVALL_TOVALLOW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_TOVALL_TOVALLOW), uint16_t) & BM_WDOG_TOVALL_TOVALLOW)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TOVALLOW field to a new value.
-#define BW_WDOG_TOVALL_TOVALLOW(v) (HW_WDOG_TOVALL_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_WDOG_WINH - Watchdog Window Register High
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_WDOG_WINH - Watchdog Window Register High (RW)
- *
- * Reset value: 0x0000U
- *
- * You must set the Window Register value lower than the Time-out Value Register.
- */
-typedef union _hw_wdog_winh
-{
- uint16_t U;
- struct _hw_wdog_winh_bitfields
- {
- uint16_t WINHIGH : 16; //!< [15:0]
- } B;
-} hw_wdog_winh_t;
-#endif
-
-/*!
- * @name Constants and macros for entire WDOG_WINH register
- */
-//@{
-#define HW_WDOG_WINH_ADDR (REGS_WDOG_BASE + 0x8U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_WDOG_WINH (*(__IO hw_wdog_winh_t *) HW_WDOG_WINH_ADDR)
-#define HW_WDOG_WINH_RD() (HW_WDOG_WINH.U)
-#define HW_WDOG_WINH_WR(v) (HW_WDOG_WINH.U = (v))
-#define HW_WDOG_WINH_SET(v) (HW_WDOG_WINH_WR(HW_WDOG_WINH_RD() | (v)))
-#define HW_WDOG_WINH_CLR(v) (HW_WDOG_WINH_WR(HW_WDOG_WINH_RD() & ~(v)))
-#define HW_WDOG_WINH_TOG(v) (HW_WDOG_WINH_WR(HW_WDOG_WINH_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual WDOG_WINH bitfields
- */
-
-/*!
- * @name Register WDOG_WINH, field WINHIGH[15:0] (RW)
- *
- * Defines the upper 16 bits of the 32-bit window for the windowed mode of
- * operation of the watchdog. It is defined in terms of cycles of the watchdog clock.
- * In this mode, the watchdog can be refreshed only when the timer has reached a
- * value greater than or equal to this window length. A refresh outside this
- * window resets the system or if IRQRSTEN is set, it interrupts and then resets the
- * system.
- */
-//@{
-#define BP_WDOG_WINH_WINHIGH (0U) //!< Bit position for WDOG_WINH_WINHIGH.
-#define BM_WDOG_WINH_WINHIGH (0xFFFFU) //!< Bit mask for WDOG_WINH_WINHIGH.
-#define BS_WDOG_WINH_WINHIGH (16U) //!< Bit field size in bits for WDOG_WINH_WINHIGH.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the WDOG_WINH_WINHIGH field.
-#define BR_WDOG_WINH_WINHIGH (HW_WDOG_WINH.U)
-#endif
-
-//! @brief Format value for bitfield WDOG_WINH_WINHIGH.
-#define BF_WDOG_WINH_WINHIGH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_WINH_WINHIGH), uint16_t) & BM_WDOG_WINH_WINHIGH)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WINHIGH field to a new value.
-#define BW_WDOG_WINH_WINHIGH(v) (HW_WDOG_WINH_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_WDOG_WINL - Watchdog Window Register Low
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_WDOG_WINL - Watchdog Window Register Low (RW)
- *
- * Reset value: 0x0010U
- *
- * You must set the Window Register value lower than the Time-out Value Register.
- */
-typedef union _hw_wdog_winl
-{
- uint16_t U;
- struct _hw_wdog_winl_bitfields
- {
- uint16_t WINLOW : 16; //!< [15:0]
- } B;
-} hw_wdog_winl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire WDOG_WINL register
- */
-//@{
-#define HW_WDOG_WINL_ADDR (REGS_WDOG_BASE + 0xAU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_WDOG_WINL (*(__IO hw_wdog_winl_t *) HW_WDOG_WINL_ADDR)
-#define HW_WDOG_WINL_RD() (HW_WDOG_WINL.U)
-#define HW_WDOG_WINL_WR(v) (HW_WDOG_WINL.U = (v))
-#define HW_WDOG_WINL_SET(v) (HW_WDOG_WINL_WR(HW_WDOG_WINL_RD() | (v)))
-#define HW_WDOG_WINL_CLR(v) (HW_WDOG_WINL_WR(HW_WDOG_WINL_RD() & ~(v)))
-#define HW_WDOG_WINL_TOG(v) (HW_WDOG_WINL_WR(HW_WDOG_WINL_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual WDOG_WINL bitfields
- */
-
-/*!
- * @name Register WDOG_WINL, field WINLOW[15:0] (RW)
- *
- * Defines the lower 16 bits of the 32-bit window for the windowed mode of
- * operation of the watchdog. It is defined in terms of cycles of the pre-scaled
- * watchdog clock. In this mode, the watchdog can be refreshed only when the timer
- * reaches a value greater than or equal to this window length value. A refresh
- * outside of this window resets the system or if IRQRSTEN is set, it interrupts and
- * then resets the system.
- */
-//@{
-#define BP_WDOG_WINL_WINLOW (0U) //!< Bit position for WDOG_WINL_WINLOW.
-#define BM_WDOG_WINL_WINLOW (0xFFFFU) //!< Bit mask for WDOG_WINL_WINLOW.
-#define BS_WDOG_WINL_WINLOW (16U) //!< Bit field size in bits for WDOG_WINL_WINLOW.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the WDOG_WINL_WINLOW field.
-#define BR_WDOG_WINL_WINLOW (HW_WDOG_WINL.U)
-#endif
-
-//! @brief Format value for bitfield WDOG_WINL_WINLOW.
-#define BF_WDOG_WINL_WINLOW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_WINL_WINLOW), uint16_t) & BM_WDOG_WINL_WINLOW)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WINLOW field to a new value.
-#define BW_WDOG_WINL_WINLOW(v) (HW_WDOG_WINL_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_WDOG_REFRESH - Watchdog Refresh register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_WDOG_REFRESH - Watchdog Refresh register (RW)
- *
- * Reset value: 0xB480U
- */
-typedef union _hw_wdog_refresh
-{
- uint16_t U;
- struct _hw_wdog_refresh_bitfields
- {
- uint16_t WDOGREFRESH : 16; //!< [15:0]
- } B;
-} hw_wdog_refresh_t;
-#endif
-
-/*!
- * @name Constants and macros for entire WDOG_REFRESH register
- */
-//@{
-#define HW_WDOG_REFRESH_ADDR (REGS_WDOG_BASE + 0xCU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_WDOG_REFRESH (*(__IO hw_wdog_refresh_t *) HW_WDOG_REFRESH_ADDR)
-#define HW_WDOG_REFRESH_RD() (HW_WDOG_REFRESH.U)
-#define HW_WDOG_REFRESH_WR(v) (HW_WDOG_REFRESH.U = (v))
-#define HW_WDOG_REFRESH_SET(v) (HW_WDOG_REFRESH_WR(HW_WDOG_REFRESH_RD() | (v)))
-#define HW_WDOG_REFRESH_CLR(v) (HW_WDOG_REFRESH_WR(HW_WDOG_REFRESH_RD() & ~(v)))
-#define HW_WDOG_REFRESH_TOG(v) (HW_WDOG_REFRESH_WR(HW_WDOG_REFRESH_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual WDOG_REFRESH bitfields
- */
-
-/*!
- * @name Register WDOG_REFRESH, field WDOGREFRESH[15:0] (RW)
- *
- * Watchdog refresh register. A sequence of 0xA602 followed by 0xB480 within 20
- * bus clock cycles written to this register refreshes the WDOG and prevents it
- * from resetting the system. Writing a value other than the above mentioned
- * sequence or if the sequence is longer than 20 bus cycles, resets the system, or if
- * IRQRSTEN is set, it interrupts and then resets the system.
- */
-//@{
-#define BP_WDOG_REFRESH_WDOGREFRESH (0U) //!< Bit position for WDOG_REFRESH_WDOGREFRESH.
-#define BM_WDOG_REFRESH_WDOGREFRESH (0xFFFFU) //!< Bit mask for WDOG_REFRESH_WDOGREFRESH.
-#define BS_WDOG_REFRESH_WDOGREFRESH (16U) //!< Bit field size in bits for WDOG_REFRESH_WDOGREFRESH.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the WDOG_REFRESH_WDOGREFRESH field.
-#define BR_WDOG_REFRESH_WDOGREFRESH (HW_WDOG_REFRESH.U)
-#endif
-
-//! @brief Format value for bitfield WDOG_REFRESH_WDOGREFRESH.
-#define BF_WDOG_REFRESH_WDOGREFRESH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_REFRESH_WDOGREFRESH), uint16_t) & BM_WDOG_REFRESH_WDOGREFRESH)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WDOGREFRESH field to a new value.
-#define BW_WDOG_REFRESH_WDOGREFRESH(v) (HW_WDOG_REFRESH_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_WDOG_UNLOCK - Watchdog Unlock register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_WDOG_UNLOCK - Watchdog Unlock register (RW)
- *
- * Reset value: 0xD928U
- */
-typedef union _hw_wdog_unlock
-{
- uint16_t U;
- struct _hw_wdog_unlock_bitfields
- {
- uint16_t WDOGUNLOCK : 16; //!< [15:0]
- } B;
-} hw_wdog_unlock_t;
-#endif
-
-/*!
- * @name Constants and macros for entire WDOG_UNLOCK register
- */
-//@{
-#define HW_WDOG_UNLOCK_ADDR (REGS_WDOG_BASE + 0xEU)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_WDOG_UNLOCK (*(__IO hw_wdog_unlock_t *) HW_WDOG_UNLOCK_ADDR)
-#define HW_WDOG_UNLOCK_RD() (HW_WDOG_UNLOCK.U)
-#define HW_WDOG_UNLOCK_WR(v) (HW_WDOG_UNLOCK.U = (v))
-#define HW_WDOG_UNLOCK_SET(v) (HW_WDOG_UNLOCK_WR(HW_WDOG_UNLOCK_RD() | (v)))
-#define HW_WDOG_UNLOCK_CLR(v) (HW_WDOG_UNLOCK_WR(HW_WDOG_UNLOCK_RD() & ~(v)))
-#define HW_WDOG_UNLOCK_TOG(v) (HW_WDOG_UNLOCK_WR(HW_WDOG_UNLOCK_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual WDOG_UNLOCK bitfields
- */
-
-/*!
- * @name Register WDOG_UNLOCK, field WDOGUNLOCK[15:0] (RW)
- *
- * Writing the unlock sequence values to this register to makes the watchdog
- * write-once registers writable again. The required unlock sequence is 0xC520
- * followed by 0xD928 within 20 bus clock cycles. A valid unlock sequence opens a
- * window equal in length to the WCT within which you can update the registers.
- * Writing a value other than the above mentioned sequence or if the sequence is
- * longer than 20 bus cycles, resets the system or if IRQRSTEN is set, it interrupts
- * and then resets the system. The unlock sequence is effective only if
- * ALLOWUPDATE is set.
- */
-//@{
-#define BP_WDOG_UNLOCK_WDOGUNLOCK (0U) //!< Bit position for WDOG_UNLOCK_WDOGUNLOCK.
-#define BM_WDOG_UNLOCK_WDOGUNLOCK (0xFFFFU) //!< Bit mask for WDOG_UNLOCK_WDOGUNLOCK.
-#define BS_WDOG_UNLOCK_WDOGUNLOCK (16U) //!< Bit field size in bits for WDOG_UNLOCK_WDOGUNLOCK.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the WDOG_UNLOCK_WDOGUNLOCK field.
-#define BR_WDOG_UNLOCK_WDOGUNLOCK (HW_WDOG_UNLOCK.U)
-#endif
-
-//! @brief Format value for bitfield WDOG_UNLOCK_WDOGUNLOCK.
-#define BF_WDOG_UNLOCK_WDOGUNLOCK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_UNLOCK_WDOGUNLOCK), uint16_t) & BM_WDOG_UNLOCK_WDOGUNLOCK)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the WDOGUNLOCK field to a new value.
-#define BW_WDOG_UNLOCK_WDOGUNLOCK(v) (HW_WDOG_UNLOCK_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_WDOG_TMROUTH - Watchdog Timer Output Register High
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_WDOG_TMROUTH - Watchdog Timer Output Register High (RW)
- *
- * Reset value: 0x0000U
- */
-typedef union _hw_wdog_tmrouth
-{
- uint16_t U;
- struct _hw_wdog_tmrouth_bitfields
- {
- uint16_t TIMEROUTHIGH : 16; //!< [15:0]
- } B;
-} hw_wdog_tmrouth_t;
-#endif
-
-/*!
- * @name Constants and macros for entire WDOG_TMROUTH register
- */
-//@{
-#define HW_WDOG_TMROUTH_ADDR (REGS_WDOG_BASE + 0x10U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_WDOG_TMROUTH (*(__IO hw_wdog_tmrouth_t *) HW_WDOG_TMROUTH_ADDR)
-#define HW_WDOG_TMROUTH_RD() (HW_WDOG_TMROUTH.U)
-#define HW_WDOG_TMROUTH_WR(v) (HW_WDOG_TMROUTH.U = (v))
-#define HW_WDOG_TMROUTH_SET(v) (HW_WDOG_TMROUTH_WR(HW_WDOG_TMROUTH_RD() | (v)))
-#define HW_WDOG_TMROUTH_CLR(v) (HW_WDOG_TMROUTH_WR(HW_WDOG_TMROUTH_RD() & ~(v)))
-#define HW_WDOG_TMROUTH_TOG(v) (HW_WDOG_TMROUTH_WR(HW_WDOG_TMROUTH_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual WDOG_TMROUTH bitfields
- */
-
-/*!
- * @name Register WDOG_TMROUTH, field TIMEROUTHIGH[15:0] (RW)
- *
- * Shows the value of the upper 16 bits of the watchdog timer.
- */
-//@{
-#define BP_WDOG_TMROUTH_TIMEROUTHIGH (0U) //!< Bit position for WDOG_TMROUTH_TIMEROUTHIGH.
-#define BM_WDOG_TMROUTH_TIMEROUTHIGH (0xFFFFU) //!< Bit mask for WDOG_TMROUTH_TIMEROUTHIGH.
-#define BS_WDOG_TMROUTH_TIMEROUTHIGH (16U) //!< Bit field size in bits for WDOG_TMROUTH_TIMEROUTHIGH.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the WDOG_TMROUTH_TIMEROUTHIGH field.
-#define BR_WDOG_TMROUTH_TIMEROUTHIGH (HW_WDOG_TMROUTH.U)
-#endif
-
-//! @brief Format value for bitfield WDOG_TMROUTH_TIMEROUTHIGH.
-#define BF_WDOG_TMROUTH_TIMEROUTHIGH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_TMROUTH_TIMEROUTHIGH), uint16_t) & BM_WDOG_TMROUTH_TIMEROUTHIGH)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TIMEROUTHIGH field to a new value.
-#define BW_WDOG_TMROUTH_TIMEROUTHIGH(v) (HW_WDOG_TMROUTH_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_WDOG_TMROUTL - Watchdog Timer Output Register Low
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_WDOG_TMROUTL - Watchdog Timer Output Register Low (RW)
- *
- * Reset value: 0x0000U
- *
- * During Stop mode, the WDOG_TIMER_OUT will be caught at the pre-stop value of
- * the watchdog timer. After exiting Stop mode, a maximum delay of 1 WDOG_CLK
- * cycle + 3 bus clock cycles will occur before the WDOG_TIMER_OUT starts following
- * the watchdog timer.
- */
-typedef union _hw_wdog_tmroutl
-{
- uint16_t U;
- struct _hw_wdog_tmroutl_bitfields
- {
- uint16_t TIMEROUTLOW : 16; //!< [15:0]
- } B;
-} hw_wdog_tmroutl_t;
-#endif
-
-/*!
- * @name Constants and macros for entire WDOG_TMROUTL register
- */
-//@{
-#define HW_WDOG_TMROUTL_ADDR (REGS_WDOG_BASE + 0x12U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_WDOG_TMROUTL (*(__IO hw_wdog_tmroutl_t *) HW_WDOG_TMROUTL_ADDR)
-#define HW_WDOG_TMROUTL_RD() (HW_WDOG_TMROUTL.U)
-#define HW_WDOG_TMROUTL_WR(v) (HW_WDOG_TMROUTL.U = (v))
-#define HW_WDOG_TMROUTL_SET(v) (HW_WDOG_TMROUTL_WR(HW_WDOG_TMROUTL_RD() | (v)))
-#define HW_WDOG_TMROUTL_CLR(v) (HW_WDOG_TMROUTL_WR(HW_WDOG_TMROUTL_RD() & ~(v)))
-#define HW_WDOG_TMROUTL_TOG(v) (HW_WDOG_TMROUTL_WR(HW_WDOG_TMROUTL_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual WDOG_TMROUTL bitfields
- */
-
-/*!
- * @name Register WDOG_TMROUTL, field TIMEROUTLOW[15:0] (RW)
- *
- * Shows the value of the lower 16 bits of the watchdog timer.
- */
-//@{
-#define BP_WDOG_TMROUTL_TIMEROUTLOW (0U) //!< Bit position for WDOG_TMROUTL_TIMEROUTLOW.
-#define BM_WDOG_TMROUTL_TIMEROUTLOW (0xFFFFU) //!< Bit mask for WDOG_TMROUTL_TIMEROUTLOW.
-#define BS_WDOG_TMROUTL_TIMEROUTLOW (16U) //!< Bit field size in bits for WDOG_TMROUTL_TIMEROUTLOW.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the WDOG_TMROUTL_TIMEROUTLOW field.
-#define BR_WDOG_TMROUTL_TIMEROUTLOW (HW_WDOG_TMROUTL.U)
-#endif
-
-//! @brief Format value for bitfield WDOG_TMROUTL_TIMEROUTLOW.
-#define BF_WDOG_TMROUTL_TIMEROUTLOW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_TMROUTL_TIMEROUTLOW), uint16_t) & BM_WDOG_TMROUTL_TIMEROUTLOW)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the TIMEROUTLOW field to a new value.
-#define BW_WDOG_TMROUTL_TIMEROUTLOW(v) (HW_WDOG_TMROUTL_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_WDOG_RSTCNT - Watchdog Reset Count register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_WDOG_RSTCNT - Watchdog Reset Count register (RW)
- *
- * Reset value: 0x0000U
- */
-typedef union _hw_wdog_rstcnt
-{
- uint16_t U;
- struct _hw_wdog_rstcnt_bitfields
- {
- uint16_t RSTCNT : 16; //!< [15:0]
- } B;
-} hw_wdog_rstcnt_t;
-#endif
-
-/*!
- * @name Constants and macros for entire WDOG_RSTCNT register
- */
-//@{
-#define HW_WDOG_RSTCNT_ADDR (REGS_WDOG_BASE + 0x14U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_WDOG_RSTCNT (*(__IO hw_wdog_rstcnt_t *) HW_WDOG_RSTCNT_ADDR)
-#define HW_WDOG_RSTCNT_RD() (HW_WDOG_RSTCNT.U)
-#define HW_WDOG_RSTCNT_WR(v) (HW_WDOG_RSTCNT.U = (v))
-#define HW_WDOG_RSTCNT_SET(v) (HW_WDOG_RSTCNT_WR(HW_WDOG_RSTCNT_RD() | (v)))
-#define HW_WDOG_RSTCNT_CLR(v) (HW_WDOG_RSTCNT_WR(HW_WDOG_RSTCNT_RD() & ~(v)))
-#define HW_WDOG_RSTCNT_TOG(v) (HW_WDOG_RSTCNT_WR(HW_WDOG_RSTCNT_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual WDOG_RSTCNT bitfields
- */
-
-/*!
- * @name Register WDOG_RSTCNT, field RSTCNT[15:0] (RW)
- *
- * Counts the number of times the watchdog resets the system. This register is
- * reset only on a POR. Writing 1 to the bit to be cleared enables you to clear
- * the contents of this register.
- */
-//@{
-#define BP_WDOG_RSTCNT_RSTCNT (0U) //!< Bit position for WDOG_RSTCNT_RSTCNT.
-#define BM_WDOG_RSTCNT_RSTCNT (0xFFFFU) //!< Bit mask for WDOG_RSTCNT_RSTCNT.
-#define BS_WDOG_RSTCNT_RSTCNT (16U) //!< Bit field size in bits for WDOG_RSTCNT_RSTCNT.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the WDOG_RSTCNT_RSTCNT field.
-#define BR_WDOG_RSTCNT_RSTCNT (HW_WDOG_RSTCNT.U)
-#endif
-
-//! @brief Format value for bitfield WDOG_RSTCNT_RSTCNT.
-#define BF_WDOG_RSTCNT_RSTCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_RSTCNT_RSTCNT), uint16_t) & BM_WDOG_RSTCNT_RSTCNT)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the RSTCNT field to a new value.
-#define BW_WDOG_RSTCNT_RSTCNT(v) (HW_WDOG_RSTCNT_WR(v))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// HW_WDOG_PRESC - Watchdog Prescaler register
-//-------------------------------------------------------------------------------------------
-
-#ifndef __LANGUAGE_ASM__
-/*!
- * @brief HW_WDOG_PRESC - Watchdog Prescaler register (RW)
- *
- * Reset value: 0x0400U
- */
-typedef union _hw_wdog_presc
-{
- uint16_t U;
- struct _hw_wdog_presc_bitfields
- {
- uint16_t RESERVED0 : 8; //!< [7:0]
- uint16_t PRESCVAL : 3; //!< [10:8]
- uint16_t RESERVED1 : 5; //!< [15:11]
- } B;
-} hw_wdog_presc_t;
-#endif
-
-/*!
- * @name Constants and macros for entire WDOG_PRESC register
- */
-//@{
-#define HW_WDOG_PRESC_ADDR (REGS_WDOG_BASE + 0x16U)
-
-#ifndef __LANGUAGE_ASM__
-#define HW_WDOG_PRESC (*(__IO hw_wdog_presc_t *) HW_WDOG_PRESC_ADDR)
-#define HW_WDOG_PRESC_RD() (HW_WDOG_PRESC.U)
-#define HW_WDOG_PRESC_WR(v) (HW_WDOG_PRESC.U = (v))
-#define HW_WDOG_PRESC_SET(v) (HW_WDOG_PRESC_WR(HW_WDOG_PRESC_RD() | (v)))
-#define HW_WDOG_PRESC_CLR(v) (HW_WDOG_PRESC_WR(HW_WDOG_PRESC_RD() & ~(v)))
-#define HW_WDOG_PRESC_TOG(v) (HW_WDOG_PRESC_WR(HW_WDOG_PRESC_RD() ^ (v)))
-#endif
-//@}
-
-/*
- * Constants & macros for individual WDOG_PRESC bitfields
- */
-
-/*!
- * @name Register WDOG_PRESC, field PRESCVAL[10:8] (RW)
- *
- * 3-bit prescaler for the watchdog clock source. A value of zero indicates no
- * division of the input WDOG clock. The watchdog clock is divided by (PRESCVAL +
- * 1) to provide the prescaled WDOG_CLK.
- */
-//@{
-#define BP_WDOG_PRESC_PRESCVAL (8U) //!< Bit position for WDOG_PRESC_PRESCVAL.
-#define BM_WDOG_PRESC_PRESCVAL (0x0700U) //!< Bit mask for WDOG_PRESC_PRESCVAL.
-#define BS_WDOG_PRESC_PRESCVAL (3U) //!< Bit field size in bits for WDOG_PRESC_PRESCVAL.
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Read current value of the WDOG_PRESC_PRESCVAL field.
-#define BR_WDOG_PRESC_PRESCVAL (HW_WDOG_PRESC.B.PRESCVAL)
-#endif
-
-//! @brief Format value for bitfield WDOG_PRESC_PRESCVAL.
-#define BF_WDOG_PRESC_PRESCVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_PRESC_PRESCVAL), uint16_t) & BM_WDOG_PRESC_PRESCVAL)
-
-#ifndef __LANGUAGE_ASM__
-//! @brief Set the PRESCVAL field to a new value.
-#define BW_WDOG_PRESC_PRESCVAL(v) (HW_WDOG_PRESC_WR((HW_WDOG_PRESC_RD() & ~BM_WDOG_PRESC_PRESCVAL) | BF_WDOG_PRESC_PRESCVAL(v)))
-#endif
-//@}
-
-//-------------------------------------------------------------------------------------------
-// hw_wdog_t - module struct
-//-------------------------------------------------------------------------------------------
-/*!
- * @brief All WDOG module registers.
- */
-#ifndef __LANGUAGE_ASM__
-#pragma pack(1)
-typedef struct _hw_wdog
-{
- __IO hw_wdog_stctrlh_t STCTRLH; //!< [0x0] Watchdog Status and Control Register High
- __IO hw_wdog_stctrll_t STCTRLL; //!< [0x2] Watchdog Status and Control Register Low
- __IO hw_wdog_tovalh_t TOVALH; //!< [0x4] Watchdog Time-out Value Register High
- __IO hw_wdog_tovall_t TOVALL; //!< [0x6] Watchdog Time-out Value Register Low
- __IO hw_wdog_winh_t WINH; //!< [0x8] Watchdog Window Register High
- __IO hw_wdog_winl_t WINL; //!< [0xA] Watchdog Window Register Low
- __IO hw_wdog_refresh_t REFRESH; //!< [0xC] Watchdog Refresh register
- __IO hw_wdog_unlock_t UNLOCK; //!< [0xE] Watchdog Unlock register
- __IO hw_wdog_tmrouth_t TMROUTH; //!< [0x10] Watchdog Timer Output Register High
- __IO hw_wdog_tmroutl_t TMROUTL; //!< [0x12] Watchdog Timer Output Register Low
- __IO hw_wdog_rstcnt_t RSTCNT; //!< [0x14] Watchdog Reset Count register
- __IO hw_wdog_presc_t PRESC; //!< [0x16] Watchdog Prescaler register
-} hw_wdog_t;
-#pragma pack()
-
-//! @brief Macro to access all WDOG registers.
-//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
-//! use the '&' operator, like <code>&HW_WDOG</code>.
-#define HW_WDOG (*(hw_wdog_t *) REGS_WDOG_BASE)
-#endif
-
-#endif // __HW_WDOG_REGISTERS_H__
-// v22/130726/0.9
-// EOF
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/regs.h Fri Aug 15 15:28:31 2014 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,525 +0,0 @@ -/* - * Copyright (c) 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - */ - -#ifndef _REGS_H -#define _REGS_H 1 - -#include <stdint.h> -#include <stdlib.h> - -// -// define base address of the register block only if it is not already -// defined, which allows the compiler to override at build time for -// users who've mapped their registers to locations other than the -// physical location -// - -#include <stdint.h> - -#ifndef REGS_BASE -#define REGS_BASE 0x00000000 -#endif - -// -// common register types -// - -#ifndef __LANGUAGE_ASM__ -typedef unsigned char reg8_t; -typedef unsigned short reg16_t; -typedef unsigned int reg32_t; -#endif - -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -#define BME_AND_MASK (1<<26) -#define BME_OR_MASK (1<<27) -#define BME_XOR_MASK (3<<26) -#define BME_BFI_MASK(BIT,WIDTH) (1<<28) | (BIT<<23) | ((WIDTH-1)<<19) -#define BME_UBFX_MASK(BIT,WIDTH) (1<<28) | (BIT<<23) | ((WIDTH-1)<<19) - -/** - * @brief Macro to access a single bit of a 32-bit peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_ACCESS32(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))))) - -/** - * @brief Macro to access a single bit of a 16-bit peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_ACCESS16(Reg,Bit) (*((uint16_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))))) - -/** - * @brief Macro to access a single bit of an 8-bit peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_ACCESS8(Reg,Bit) (*((uint8_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))))) - -// -// Typecast macro for C or asm. In C, the cast is applied, while in asm it is excluded. This is -// used to simplify macro definitions in the module register headers. -// -#ifndef __REG_VALUE_TYPE - #ifndef __LANGUAGE_ASM__ - #define __REG_VALUE_TYPE(v, t) ((t)(v)) - #else - #define __REG_VALUE_TYPE(v, t) (v) - #endif -#endif - -// -// macros for single instance registers -// - -#define BF_SET(reg, field) HW_##reg##_SET(BM_##reg##_##field) -#define BF_CLR(reg, field) HW_##reg##_CLR(BM_##reg##_##field) -#define BF_TOG(reg, field) HW_##reg##_TOG(BM_##reg##_##field) - -#define BF_SETV(reg, field, v) HW_##reg##_SET(BF_##reg##_##field(v)) -#define BF_CLRV(reg, field, v) HW_##reg##_CLR(BF_##reg##_##field(v)) -#define BF_TOGV(reg, field, v) HW_##reg##_TOG(BF_##reg##_##field(v)) - -#define BV_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) -#define BV_VAL(reg, field, sym) BV_##reg##_##field##__##sym - -#define BF_RD(reg, field) HW_##reg.B.field -#define BF_WR(reg, field, v) BW_##reg##_##field(v) - -#define BF_CS1(reg, f1, v1) \ - (HW_##reg##_CLR(BM_##reg##_##f1), \ - HW_##reg##_SET(BF_##reg##_##f1(v1))) - -#define BF_CS2(reg, f1, v1, f2, v2) \ - (HW_##reg##_CLR(BM_##reg##_##f1 | \ - BM_##reg##_##f2), \ - HW_##reg##_SET(BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2))) - -#define BF_CS3(reg, f1, v1, f2, v2, f3, v3) \ - (HW_##reg##_CLR(BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3), \ - HW_##reg##_SET(BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3))) - -#define BF_CS4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \ - (HW_##reg##_CLR(BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4), \ - HW_##reg##_SET(BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4))) - -#define BF_CS5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ - (HW_##reg##_CLR(BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5), \ - HW_##reg##_SET(BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5))) - -#define BF_CS6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ - (HW_##reg##_CLR(BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6), \ - HW_##reg##_SET(BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6))) - -#define BF_CS7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ - (HW_##reg##_CLR(BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6 | \ - BM_##reg##_##f7), \ - HW_##reg##_SET(BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6) | \ - BF_##reg##_##f7(v7))) - -#define BF_CS8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ - (HW_##reg##_CLR(BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6 | \ - BM_##reg##_##f7 | \ - BM_##reg##_##f8), \ - HW_##reg##_SET(BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6) | \ - BF_##reg##_##f7(v7) | \ - BF_##reg##_##f8(v8))) - -// -// macros for multiple instance registers -// - -#define BF_SETn(reg, n, field) HW_##reg##_SET(n, BM_##reg##_##field) -#define BF_CLRn(reg, n, field) HW_##reg##_CLR(n, BM_##reg##_##field) -#define BF_TOGn(reg, n, field) HW_##reg##_TOG(n, BM_##reg##_##field) - -#define BF_SETVn(reg, n, field, v) HW_##reg##_SET(n, BF_##reg##_##field(v)) -#define BF_CLRVn(reg, n, field, v) HW_##reg##_CLR(n, BF_##reg##_##field(v)) -#define BF_TOGVn(reg, n, field, v) HW_##reg##_TOG(n, BF_##reg##_##field(v)) - -#define BV_FLDn(reg, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) -#define BV_VALn(reg, n, field, sym) BV_##reg##_##field##__##sym - -#define BF_RDn(reg, n, field) HW_##reg(n).B.field -#define BF_WRn(reg, n, field, v) BW_##reg##_##field(n, v) - -#define BF_CS1n(reg, n, f1, v1) \ - (HW_##reg##_CLR(n, (BM_##reg##_##f1)), \ - HW_##reg##_SET(n, (BF_##reg##_##f1(v1)))) - -#define BF_CS2n(reg, n, f1, v1, f2, v2) \ - (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2)), \ - HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2)))) - -#define BF_CS3n(reg, n, f1, v1, f2, v2, f3, v3) \ - (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3)), \ - HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3)))) - -#define BF_CS4n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4) \ - (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4)), \ - HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4)))) - -#define BF_CS5n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ - (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5)), \ - HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5)))) - -#define BF_CS6n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ - (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6)), \ - HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6)))) - -#define BF_CS7n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ - (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6 | \ - BM_##reg##_##f7)), \ - HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6) | \ - BF_##reg##_##f7(v7)))) - -#define BF_CS8n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ - (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6 | \ - BM_##reg##_##f7 | \ - BM_##reg##_##f8)), \ - HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6) | \ - BF_##reg##_##f7(v7) | \ - BF_##reg##_##f8(v8)))) - -// -// macros for single instance MULTI-BLOCK registers -// - -#define BFn_SET(reg, blk, field) HW_##reg##_SET(blk, BM_##reg##_##field) -#define BFn_CLR(reg, blk, field) HW_##reg##_CLR(blk, BM_##reg##_##field) -#define BFn_TOG(reg, blk, field) HW_##reg##_TOG(blk, BM_##reg##_##field) - -#define BFn_SETV(reg, blk, field, v) HW_##reg##_SET(blk, BF_##reg##_##field(v)) -#define BFn_CLRV(reg, blk, field, v) HW_##reg##_CLR(blk, BF_##reg##_##field(v)) -#define BFn_TOGV(reg, blk, field, v) HW_##reg##_TOG(blk, BF_##reg##_##field(v)) - -#define BVn_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) -#define BVn_VAL(reg, field, sym) BV_##reg##_##field##__##sym - -#define BFn_RD(reg, blk, field) HW_##reg(blk).B.field -#define BFn_WR(reg, blk, field, v) BW_##reg##_##field(blk, v) - -#define BFn_CS1(reg, blk, f1, v1) \ - (HW_##reg##_CLR(blk, BM_##reg##_##f1), \ - HW_##reg##_SET(blk, BF_##reg##_##f1(v1))) - -#define BFn_CS2(reg, blk, f1, v1, f2, v2) \ - (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ - BM_##reg##_##f2), \ - HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2))) - -#define BFn_CS3(reg, blk, f1, v1, f2, v2, f3, v3) \ - (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3), \ - HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3))) - -#define BFn_CS4(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4) \ - (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4), \ - HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4))) - -#define BFn_CS5(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ - (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5), \ - HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5))) - -#define BFn_CS6(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ - (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6), \ - HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6))) - -#define BFn_CS7(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ - (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6 | \ - BM_##reg##_##f7), \ - HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6) | \ - BF_##reg##_##f7(v7))) - -#define BFn_CS8(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ - (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6 | \ - BM_##reg##_##f7 | \ - BM_##reg##_##f8), \ - HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6) | \ - BF_##reg##_##f7(v7) | \ - BF_##reg##_##f8(v8))) - -// -// macros for MULTI-BLOCK multiple instance registers -// - -#define BFn_SETn(reg, blk, n, field) HW_##reg##_SET(blk, n, BM_##reg##_##field) -#define BFn_CLRn(reg, blk, n, field) HW_##reg##_CLR(blk, n, BM_##reg##_##field) -#define BFn_TOGn(reg, blk, n, field) HW_##reg##_TOG(blk, n, BM_##reg##_##field) - -#define BFn_SETVn(reg, blk, n, field, v) HW_##reg##_SET(blk, n, BF_##reg##_##field(v)) -#define BFn_CLRVn(reg, blk, n, field, v) HW_##reg##_CLR(blk, n, BF_##reg##_##field(v)) -#define BFn_TOGVn(reg, blk, n, field, v) HW_##reg##_TOG(blk, n, BF_##reg##_##field(v)) - -#define BVn_FLDn(reg, blk, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) -#define BVn_VALn(reg, blk, n, field, sym) BV_##reg##_##field##__##sym - -#define BFn_RDn(reg, blk, n, field) HW_##reg(n).B.field -#define BFn_WRn(reg, blk, n, field, v) BW_##reg##_##field(n, v) - -#define BFn_CS1n(reg, blk, n, f1, v1) \ - (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1)), \ - HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1)))) - -#define BFn_CS2n(reg, blk, n, f1, v1, f2, v2) \ - (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2)), \ - HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2)))) - -#define BFn_CS3n(reg, blk, n, f1, v1, f2, v2, f3, v3) \ - (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3)), \ - HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3)))) - -#define BFn_CS4n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4) \ - (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4)), \ - HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4)))) - -#define BFn_CS5n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ - (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5)), \ - HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5)))) - -#define BFn_CS6n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ - (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6)), \ - HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6)))) - -#define BFn_CS7n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ - (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6 | \ - BM_##reg##_##f7)), \ - HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6) | \ - BF_##reg##_##f7(v7)))) - -#define BFn_CS8n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ - (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ - BM_##reg##_##f2 | \ - BM_##reg##_##f3 | \ - BM_##reg##_##f4 | \ - BM_##reg##_##f5 | \ - BM_##reg##_##f6 | \ - BM_##reg##_##f7 | \ - BM_##reg##_##f8)), \ - HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ - BF_##reg##_##f2(v2) | \ - BF_##reg##_##f3(v3) | \ - BF_##reg##_##f4(v4) | \ - BF_##reg##_##f5(v5) | \ - BF_##reg##_##f6(v6) | \ - BF_##reg##_##f7(v7) | \ - BF_##reg##_##f8(v8)))) - -#endif // _REGS_H - -////////////////////////////////////////////////////////////////////////////////
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/system_MK64F12.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,169 +0,0 @@
-/*
-** ###################################################################
-** Processor: MK64FN1M0VMD12
-** Compilers: ARM Compiler
-** Freescale C/C++ for Embedded ARM
-** GNU C Compiler
-** GNU C Compiler - CodeSourcery Sourcery G++
-** IAR ANSI C/C++ Compiler for ARM
-**
-** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
-** Version: rev. 2.3, 2014-01-24
-**
-** Abstract:
-** Provides a system configuration function and a global variable that
-** contains the system frequency. It configures the device and initializes
-** the oscillator (PLL) that is part of the microcontroller device.
-**
-** Copyright: 2014 Freescale, Inc. All Rights Reserved.
-**
-** http: www.freescale.com
-** mail: support@freescale.com
-**
-** Revisions:
-** - rev. 1.0 (2013-08-12)
-** Initial version.
-** - rev. 2.0 (2013-10-29)
-** Register accessor macros added to the memory map.
-** Symbols for Processor Expert memory map compatibility added to the memory map.
-** Startup file for gcc has been updated according to CMSIS 3.2.
-** System initialization updated.
-** MCG - registers updated.
-** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
-** - rev. 2.1 (2013-10-29)
-** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
-** - rev. 2.2 (2013-12-09)
-** DMA - EARS register removed.
-** AIPS0, AIPS1 - MPRA register updated.
-** - rev. 2.3 (2014-01-24)
-** Update according to reference manual rev. 2
-** ENET, MCG, MCM, SIM, USB - registers updated
-**
-** ###################################################################
-*/
-
-/*!
- * @file MK64F12
- * @version 2.3
- * @date 2014-01-24
- * @brief Device specific configuration file for MK64F12 (header file)
- *
- * Provides a system configuration function and a global variable that contains
- * the system frequency. It configures the device and initializes the oscillator
- * (PLL) that is part of the microcontroller device.
- */
-
-#ifndef SYSTEM_MK64F12_H_
-#define SYSTEM_MK64F12_H_ /**< Symbol preventing repeated inclusion */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-#define DISABLE_WDOG 1
-
-#ifndef CLOCK_SETUP
-#define CLOCK_SETUP 4
-#endif
-/* Predefined clock setups
- 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
- Default part configuration.
- Reference clock source for MCG module is the slow internal clock source 32.768kHz
- Core clock = 20.97MHz, BusClock = 20.97MHz
- 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
- Maximum achievable clock frequency configuration.
- Reference clock source for MCG module is an external clock source 50MHz
- Core clock = 120MHz, BusClock = 60MHz
- 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power Internal (BLPI) mode
- Core clock/Bus clock derived directly from an fast internal clock 4MHz with no multiplication
- The clock settings is ready for Very Low Power Run mode.
- Core clock = 4MHz, BusClock = 4MHz
- 3 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
- Core clock/Bus clock derived directly from the RTC oscillator clock source 32.768kHz
- The clock settings is ready for Very Low Power Run mode.
- Core clock = 32.768kHz, BusClock = 32.768kHz
- 4 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
- USB clock setup
- USB clock divider is set for USB to receive 48MHz input clock.
- Reference clock source for MCG module is an external clock source 50MHz
- USB clock divider is set for USB to receive 48MHz input clock.
- Core clock = 120MHz, BusClock = 60MHz
-*/
-
-/*----------------------------------------------------------------------------
- Define clock source values
- *----------------------------------------------------------------------------*/
-#if (CLOCK_SETUP == 0)
- #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
- #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
- #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
- #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
- #define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
- #define DEFAULT_SYSTEM_CLOCK 20485760u /* Default System clock value */
-#elif (CLOCK_SETUP == 1)
- #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
- #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
- #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
- #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
- #define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
- #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
-#elif (CLOCK_SETUP == 2)
- #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
- #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
- #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
- #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
- #define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
- #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
-#elif (CLOCK_SETUP == 3)
- #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
- #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
- #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
- #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
- #define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
- #define DEFAULT_SYSTEM_CLOCK 32768u /* Default System clock value */
-#elif (CLOCK_SETUP == 4)
- #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
- #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
- #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
- #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
- #define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
- #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
-#endif /* (CLOCK_SETUP == 4) */
-
-
-/**
- * @brief System clock frequency (core clock)
- *
- * The system clock frequency supplied to the SysTick timer and the processor
- * core clock. This variable can be used by the user application to setup the
- * SysTick timer or configure other parameters. It may also be used by debugger to
- * query the frequency of the debug timer or configure the trace clock speed
- * SystemCoreClock is initialized with a correct predefined value.
- */
-extern uint32_t SystemCoreClock;
-
-/**
- * @brief Setup the microcontroller system.
- *
- * Typically this function configures the oscillator (PLL) that is part of the
- * microcontroller device. For systems with variable clock speed it also updates
- * the variable SystemCoreClock. SystemInit is called from startup_device file.
- */
-void SystemInit (void);
-
-/**
- * @brief Updates the SystemCoreClock variable.
- *
- * It must be called whenever the core clock is changed during program
- * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
- * the current core clock.
- */
-void SystemCoreClockUpdate (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* #if !defined(SYSTEM_MK64F12_H_) */
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/fsl_device_registers.h Fri Aug 15 15:28:31 2014 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,572 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __FSL_DEVICE_REGISTERS_H__ -#define __FSL_DEVICE_REGISTERS_H__ - -/* - * Include the cpu specific register header files. - * - * The CPU macro should be declared in the project or makefile. - */ -#if (defined(CPU_MK22FN512VDC12)) - #define K22F51212_SERIES - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/ - #include "device/MK22F51212/MK22F51212_adc.h" - #include "device/MK22F51212/MK22F51212_aips.h" - #include "device/MK22F51212/MK22F51212_cmp.h" - #include "device/MK22F51212/MK22F51212_crc.h" - #include "device/MK22F51212/MK22F51212_dac.h" - #include "device/MK22F51212/MK22F51212_dma.h" - #include "device/MK22F51212/MK22F51212_dmamux.h" - #include "device/MK22F51212/MK22F51212_ewm.h" - #include "device/MK22F51212/MK22F51212_fb.h" - #include "device/MK22F51212/MK22F51212_fmc.h" - #include "device/MK22F51212/MK22F51212_ftfa.h" - #include "device/MK22F51212/MK22F51212_ftm.h" - #include "device/MK22F51212/MK22F51212_gpio.h" - #include "device/MK22F51212/MK22F51212_i2c.h" - #include "device/MK22F51212/MK22F51212_i2s.h" - #include "device/MK22F51212/MK22F51212_llwu.h" - #include "device/MK22F51212/MK22F51212_lptmr.h" - #include "device/MK22F51212/MK22F51212_mcg.h" - #include "device/MK22F51212/MK22F51212_mcm.h" - #include "device/MK22F51212/MK22F51212_nv.h" - #include "device/MK22F51212/MK22F51212_osc.h" - #include "device/MK22F51212/MK22F51212_pdb.h" - #include "device/MK22F51212/MK22F51212_pit.h" - #include "device/MK22F51212/MK22F51212_pmc.h" - #include "device/MK22F51212/MK22F51212_port.h" - #include "device/MK22F51212/MK22F51212_rcm.h" - #include "device/MK22F51212/MK22F51212_rfsys.h" - #include "device/MK22F51212/MK22F51212_rfvbat.h" - #include "device/MK22F51212/MK22F51212_rng.h" - #include "device/MK22F51212/MK22F51212_rtc.h" - #include "device/MK22F51212/MK22F51212_sim.h" - #include "device/MK22F51212/MK22F51212_smc.h" - #include "device/MK22F51212/MK22F51212_spi.h" - #include "device/MK22F51212/MK22F51212_uart.h" - #include "device/MK22F51212/MK22F51212_usb.h" - #include "device/MK22F51212/MK22F51212_vref.h" - #include "device/MK22F51212/MK22F51212_wdog.h" - - /* CMSIS-style register definitions*/ - #include "device/MK22F51212/MK22F51212.h" - -#elif (defined(CPU_MK24FN1M0VLQ12)) - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/ - #include "device/MK24F12/MK24F12_adc.h" - #include "device/MK24F12/MK24F12_aips.h" - #include "device/MK24F12/MK24F12_axbs.h" - #include "device/MK24F12/MK24F12_can.h" - #include "device/MK24F12/MK24F12_cau.h" - #include "device/MK24F12/MK24F12_cmp.h" - #include "device/MK24F12/MK24F12_cmt.h" - #include "device/MK24F12/MK24F12_crc.h" - #include "device/MK24F12/MK24F12_dac.h" - #include "device/MK24F12/MK24F12_dma.h" - #include "device/MK24F12/MK24F12_dmamux.h" - #include "device/MK24F12/MK24F12_ewm.h" - #include "device/MK24F12/MK24F12_fb.h" - #include "device/MK24F12/MK24F12_fmc.h" - #include "device/MK24F12/MK24F12_ftfe.h" - #include "device/MK24F12/MK24F12_ftm.h" - #include "device/MK24F12/MK24F12_gpio.h" - #include "device/MK24F12/MK24F12_i2c.h" - #include "device/MK24F12/MK24F12_i2s.h" - #include "device/MK24F12/MK24F12_llwu.h" - #include "device/MK24F12/MK24F12_lptmr.h" - #include "device/MK24F12/MK24F12_mcg.h" - #include "device/MK24F12/MK24F12_mcm.h" - #include "device/MK24F12/MK24F12_mpu.h" - #include "device/MK24F12/MK24F12_nv.h" - #include "device/MK24F12/MK24F12_osc.h" - #include "device/MK24F12/MK24F12_pdb.h" - #include "device/MK24F12/MK24F12_pit.h" - #include "device/MK24F12/MK24F12_pmc.h" - #include "device/MK24F12/MK24F12_port.h" - #include "device/MK24F12/MK24F12_rcm.h" - #include "device/MK24F12/MK24F12_rfsys.h" - #include "device/MK24F12/MK24F12_rfvbat.h" - #include "device/MK24F12/MK24F12_rng.h" - #include "device/MK24F12/MK24F12_rtc.h" - #include "device/MK24F12/MK24F12_sdhc.h" - #include "device/MK24F12/MK24F12_sim.h" - #include "device/MK24F12/MK24F12_smc.h" - #include "device/MK24F12/MK24F12_spi.h" - #include "device/MK24F12/MK24F12_uart.h" - #include "device/MK24F12/MK24F12_usb.h" - #include "device/MK24F12/MK24F12_usbdcd.h" - #include "device/MK24F12/MK24F12_vref.h" - #include "device/MK24F12/MK24F12_wdog.h" - - /* CMSIS-style register definitions*/ - #include "device/MK24F12/MK24F12.h" - -#elif (defined(CPU_MK63FN1M0VMD12)) - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/ - #include "device/MK63F12/MK63F12_adc.h" - #include "device/MK63F12/MK63F12_aips.h" - #include "device/MK63F12/MK63F12_axbs.h" - #include "device/MK63F12/MK63F12_can.h" - #include "device/MK63F12/MK63F12_cau.h" - #include "device/MK63F12/MK63F12_cmp.h" - #include "device/MK63F12/MK63F12_cmt.h" - #include "device/MK63F12/MK63F12_crc.h" - #include "device/MK63F12/MK63F12_dac.h" - #include "device/MK63F12/MK63F12_dma.h" - #include "device/MK63F12/MK63F12_dmamux.h" - #include "device/MK63F12/MK63F12_enet.h" - #include "device/MK63F12/MK63F12_ewm.h" - #include "device/MK63F12/MK63F12_fb.h" - #include "device/MK63F12/MK63F12_fmc.h" - #include "device/MK63F12/MK63F12_ftfe.h" - #include "device/MK63F12/MK63F12_ftm.h" - #include "device/MK63F12/MK63F12_gpio.h" - #include "device/MK63F12/MK63F12_i2c.h" - #include "device/MK63F12/MK63F12_i2s.h" - #include "device/MK63F12/MK63F12_llwu.h" - #include "device/MK63F12/MK63F12_lptmr.h" - #include "device/MK63F12/MK63F12_mcg.h" - #include "device/MK63F12/MK63F12_mcm.h" - #include "device/MK63F12/MK63F12_mpu.h" - #include "device/MK63F12/MK63F12_nv.h" - #include "device/MK63F12/MK63F12_osc.h" - #include "device/MK63F12/MK63F12_pdb.h" - #include "device/MK63F12/MK63F12_pit.h" - #include "device/MK63F12/MK63F12_pmc.h" - #include "device/MK63F12/MK63F12_port.h" - #include "device/MK63F12/MK63F12_rcm.h" - #include "device/MK63F12/MK63F12_rfsys.h" - #include "device/MK63F12/MK63F12_rfvbat.h" - #include "device/MK63F12/MK63F12_rng.h" - #include "device/MK63F12/MK63F12_rtc.h" - #include "device/MK63F12/MK63F12_sdhc.h" - #include "device/MK63F12/MK63F12_sim.h" - #include "device/MK63F12/MK63F12_smc.h" - #include "device/MK63F12/MK63F12_spi.h" - #include "device/MK63F12/MK63F12_uart.h" - #include "device/MK63F12/MK63F12_usb.h" - #include "device/MK63F12/MK63F12_usbdcd.h" - #include "device/MK63F12/MK63F12_vref.h" - #include "device/MK63F12/MK63F12_wdog.h" - - /* CMSIS-style register definitions*/ - #include "device/MK63F12/MK63F12.h" - -#elif (defined(CPU_MK63FN1M0VMD12WS)) - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/ - #include "device/MK63F12WS/MK63F12WS_adc.h" - #include "device/MK63F12WS/MK63F12WS_aips.h" - #include "device/MK63F12WS/MK63F12WS_axbs.h" - #include "device/MK63F12WS/MK63F12WS_can.h" - #include "device/MK63F12WS/MK63F12WS_cau.h" - #include "device/MK63F12WS/MK63F12WS_cmp.h" - #include "device/MK63F12WS/MK63F12WS_cmt.h" - #include "device/MK63F12WS/MK63F12WS_crc.h" - #include "device/MK63F12WS/MK63F12WS_dac.h" - #include "device/MK63F12WS/MK63F12WS_dma.h" - #include "device/MK63F12WS/MK63F12WS_dmamux.h" - #include "device/MK63F12WS/MK63F12WS_dry.h" - #include "device/MK63F12WS/MK63F12WS_enet.h" - #include "device/MK63F12WS/MK63F12WS_ewm.h" - #include "device/MK63F12WS/MK63F12WS_fb.h" - #include "device/MK63F12WS/MK63F12WS_fmc.h" - #include "device/MK63F12WS/MK63F12WS_ftfe.h" - #include "device/MK63F12WS/MK63F12WS_ftm.h" - #include "device/MK63F12WS/MK63F12WS_gpio.h" - #include "device/MK63F12WS/MK63F12WS_i2c.h" - #include "device/MK63F12WS/MK63F12WS_i2s.h" - #include "device/MK63F12WS/MK63F12WS_llwu.h" - #include "device/MK63F12WS/MK63F12WS_lptmr.h" - #include "device/MK63F12WS/MK63F12WS_mcg.h" - #include "device/MK63F12WS/MK63F12WS_mcm.h" - #include "device/MK63F12WS/MK63F12WS_mpu.h" - #include "device/MK63F12WS/MK63F12WS_nv.h" - #include "device/MK63F12WS/MK63F12WS_osc.h" - #include "device/MK63F12WS/MK63F12WS_pdb.h" - #include "device/MK63F12WS/MK63F12WS_pit.h" - #include "device/MK63F12WS/MK63F12WS_pmc.h" - #include "device/MK63F12WS/MK63F12WS_port.h" - #include "device/MK63F12WS/MK63F12WS_rcm.h" - #include "device/MK63F12WS/MK63F12WS_rfsys.h" - #include "device/MK63F12WS/MK63F12WS_rfvbat.h" - #include "device/MK63F12WS/MK63F12WS_rng.h" - #include "device/MK63F12WS/MK63F12WS_rtc.h" - #include "device/MK63F12WS/MK63F12WS_sdhc.h" - #include "device/MK63F12WS/MK63F12WS_sim.h" - #include "device/MK63F12WS/MK63F12WS_smc.h" - #include "device/MK63F12WS/MK63F12WS_spi.h" - #include "device/MK63F12WS/MK63F12WS_uart.h" - #include "device/MK63F12WS/MK63F12WS_usb.h" - #include "device/MK63F12WS/MK63F12WS_usbdcd.h" - #include "device/MK63F12WS/MK63F12WS_vref.h" - #include "device/MK63F12WS/MK63F12WS_wdog.h" - - /* CMSIS-style register definitions*/ - #include "device/MK63F12WS/MK63F12WS.h" - -#elif (defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12)) - #define K64F12_SERIES - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/ - #include "device/MK64F12/MK64F12_adc.h" - #include "device/MK64F12/MK64F12_aips.h" - #include "device/MK64F12/MK64F12_axbs.h" - #include "device/MK64F12/MK64F12_can.h" - #include "device/MK64F12/MK64F12_cau.h" - #include "device/MK64F12/MK64F12_cmp.h" - #include "device/MK64F12/MK64F12_cmt.h" - #include "device/MK64F12/MK64F12_crc.h" - #include "device/MK64F12/MK64F12_dac.h" - #include "device/MK64F12/MK64F12_dma.h" - #include "device/MK64F12/MK64F12_dmamux.h" - #include "device/MK64F12/MK64F12_enet.h" - #include "device/MK64F12/MK64F12_ewm.h" - #include "device/MK64F12/MK64F12_fb.h" - #include "device/MK64F12/MK64F12_fmc.h" - #include "device/MK64F12/MK64F12_ftfe.h" - #include "device/MK64F12/MK64F12_ftm.h" - #include "device/MK64F12/MK64F12_gpio.h" - #include "device/MK64F12/MK64F12_i2c.h" - #include "device/MK64F12/MK64F12_i2s.h" - #include "device/MK64F12/MK64F12_llwu.h" - #include "device/MK64F12/MK64F12_lptmr.h" - #include "device/MK64F12/MK64F12_mcg.h" - #include "device/MK64F12/MK64F12_mcm.h" - #include "device/MK64F12/MK64F12_mpu.h" - #include "device/MK64F12/MK64F12_nv.h" - #include "device/MK64F12/MK64F12_osc.h" - #include "device/MK64F12/MK64F12_pdb.h" - #include "device/MK64F12/MK64F12_pit.h" - #include "device/MK64F12/MK64F12_pmc.h" - #include "device/MK64F12/MK64F12_port.h" - #include "device/MK64F12/MK64F12_rcm.h" - #include "device/MK64F12/MK64F12_rfsys.h" - #include "device/MK64F12/MK64F12_rfvbat.h" - #include "device/MK64F12/MK64F12_rng.h" - #include "device/MK64F12/MK64F12_rtc.h" - #include "device/MK64F12/MK64F12_sdhc.h" - #include "device/MK64F12/MK64F12_sim.h" - #include "device/MK64F12/MK64F12_smc.h" - #include "device/MK64F12/MK64F12_spi.h" - #include "device/MK64F12/MK64F12_uart.h" - #include "device/MK64F12/MK64F12_usb.h" - #include "device/MK64F12/MK64F12_usbdcd.h" - #include "device/MK64F12/MK64F12_vref.h" - #include "device/MK64F12/MK64F12_wdog.h" - - /* CMSIS-style register definitions*/ - #include "device/MK64F12/MK64F12.h" - -#elif (defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \ - defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \ - defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)) - #define K70F12_SERIES - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/ - #include "device/MK70F12/MK70F12_adc.h" - #include "device/MK70F12/MK70F12_aips.h" - #include "device/MK70F12/MK70F12_axbs.h" - #include "device/MK70F12/MK70F12_can.h" - #include "device/MK70F12/MK70F12_cau.h" - #include "device/MK70F12/MK70F12_cmp.h" - #include "device/MK70F12/MK70F12_cmt.h" - #include "device/MK70F12/MK70F12_crc.h" - #include "device/MK70F12/MK70F12_dac.h" - #include "device/MK70F12/MK70F12_ddr.h" - #include "device/MK70F12/MK70F12_dma.h" - #include "device/MK70F12/MK70F12_dmamux.h" - #include "device/MK70F12/MK70F12_enet.h" - #include "device/MK70F12/MK70F12_ewm.h" - #include "device/MK70F12/MK70F12_fb.h" - #include "device/MK70F12/MK70F12_fmc.h" - #include "device/MK70F12/MK70F12_ftfe.h" - #include "device/MK70F12/MK70F12_ftm.h" - #include "device/MK70F12/MK70F12_gpio.h" - #include "device/MK70F12/MK70F12_i2c.h" - #include "device/MK70F12/MK70F12_i2s.h" - #include "device/MK70F12/MK70F12_lcdc.h" - #include "device/MK70F12/MK70F12_llwu.h" - #include "device/MK70F12/MK70F12_lmem.h" - #include "device/MK70F12/MK70F12_lptmr.h" - #include "device/MK70F12/MK70F12_mcg.h" - #include "device/MK70F12/MK70F12_mcm.h" - #include "device/MK70F12/MK70F12_mpu.h" - #include "device/MK70F12/MK70F12_nfc.h" - #include "device/MK70F12/MK70F12_nv.h" - #include "device/MK70F12/MK70F12_osc.h" - #include "device/MK70F12/MK70F12_pdb.h" - #include "device/MK70F12/MK70F12_pit.h" - #include "device/MK70F12/MK70F12_pmc.h" - #include "device/MK70F12/MK70F12_port.h" - #include "device/MK70F12/MK70F12_rcm.h" - #include "device/MK70F12/MK70F12_rfsys.h" - #include "device/MK70F12/MK70F12_rfvbat.h" - #include "device/MK70F12/MK70F12_rng.h" - #include "device/MK70F12/MK70F12_rtc.h" - #include "device/MK70F12/MK70F12_sdhc.h" - #include "device/MK70F12/MK70F12_sim.h" - #include "device/MK70F12/MK70F12_smc.h" - #include "device/MK70F12/MK70F12_spi.h" - #include "device/MK70F12/MK70F12_tsi.h" - #include "device/MK70F12/MK70F12_uart.h" - #include "device/MK70F12/MK70F12_usb.h" - #include "device/MK70F12/MK70F12_usbdcd.h" - #include "device/MK70F12/MK70F12_usbhs.h" - #include "device/MK70F12/MK70F12_vref.h" - #include "device/MK70F12/MK70F12_wdog.h" - - /* CMSIS-style register definitions*/ - #include "device/MK70F12/MK70F12.h" - -#elif (defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \ - defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \ - defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)) - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/ - #include "device/MK70F15/MK70F15_adc.h" - #include "device/MK70F15/MK70F15_aips.h" - #include "device/MK70F15/MK70F15_axbs.h" - #include "device/MK70F15/MK70F15_can.h" - #include "device/MK70F15/MK70F15_cau.h" - #include "device/MK70F15/MK70F15_cmp.h" - #include "device/MK70F15/MK70F15_cmt.h" - #include "device/MK70F15/MK70F15_crc.h" - #include "device/MK70F15/MK70F15_dac.h" - #include "device/MK70F15/MK70F15_ddr.h" - #include "device/MK70F15/MK70F15_dma.h" - #include "device/MK70F15/MK70F15_dmamux.h" - #include "device/MK70F15/MK70F15_enet.h" - #include "device/MK70F15/MK70F15_ewm.h" - #include "device/MK70F15/MK70F15_fb.h" - #include "device/MK70F15/MK70F15_fmc.h" - #include "device/MK70F15/MK70F15_ftfe.h" - #include "device/MK70F15/MK70F15_ftm.h" - #include "device/MK70F15/MK70F15_gpio.h" - #include "device/MK70F15/MK70F15_i2c.h" - #include "device/MK70F15/MK70F15_i2s.h" - #include "device/MK70F15/MK70F15_lcdc.h" - #include "device/MK70F15/MK70F15_llwu.h" - #include "device/MK70F15/MK70F15_lmem.h" - #include "device/MK70F15/MK70F15_lptmr.h" - #include "device/MK70F15/MK70F15_mcg.h" - #include "device/MK70F15/MK70F15_mcm.h" - #include "device/MK70F15/MK70F15_mpu.h" - #include "device/MK70F15/MK70F15_nfc.h" - #include "device/MK70F15/MK70F15_nv.h" - #include "device/MK70F15/MK70F15_osc.h" - #include "device/MK70F15/MK70F15_pdb.h" - #include "device/MK70F15/MK70F15_pit.h" - #include "device/MK70F15/MK70F15_pmc.h" - #include "device/MK70F15/MK70F15_port.h" - #include "device/MK70F15/MK70F15_rcm.h" - #include "device/MK70F15/MK70F15_rfsys.h" - #include "device/MK70F15/MK70F15_rfvbat.h" - #include "device/MK70F15/MK70F15_rng.h" - #include "device/MK70F15/MK70F15_rtc.h" - #include "device/MK70F15/MK70F15_sdhc.h" - #include "device/MK70F15/MK70F15_sim.h" - #include "device/MK70F15/MK70F15_smc.h" - #include "device/MK70F15/MK70F15_spi.h" - #include "device/MK70F15/MK70F15_tsi.h" - #include "device/MK70F15/MK70F15_uart.h" - #include "device/MK70F15/MK70F15_usb.h" - #include "device/MK70F15/MK70F15_usbdcd.h" - #include "device/MK70F15/MK70F15_usbhs.h" - #include "device/MK70F15/MK70F15_vref.h" - #include "device/MK70F15/MK70F15_wdog.h" - - /* CMSIS-style register definitions*/ - #include "device/MK70F15/MK70F15.h" - -#elif (defined(CPU_MK70FN1M0VMJ12WS) || defined(CPU_MK70FX512VMJ12WS) || defined(CPU_MK70FN1M0VMJ15WS) || \ - defined(CPU_MK70FX512VMJ15WS)) - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/ - #include "device/MK70F12WS/MK70F12WS_adc.h" - #include "device/MK70F12WS/MK70F12WS_aips.h" - #include "device/MK70F12WS/MK70F12WS_axbs.h" - #include "device/MK70F12WS/MK70F12WS_can.h" - #include "device/MK70F12WS/MK70F12WS_cau.h" - #include "device/MK70F12WS/MK70F12WS_cmp.h" - #include "device/MK70F12WS/MK70F12WS_cmt.h" - #include "device/MK70F12WS/MK70F12WS_crc.h" - #include "device/MK70F12WS/MK70F12WS_dac.h" - #include "device/MK70F12WS/MK70F12WS_ddr.h" - #include "device/MK70F12WS/MK70F12WS_dma.h" - #include "device/MK70F12WS/MK70F12WS_dmamux.h" - #include "device/MK70F12WS/MK70F12WS_dry.h" - #include "device/MK70F12WS/MK70F12WS_enet.h" - #include "device/MK70F12WS/MK70F12WS_ewm.h" - #include "device/MK70F12WS/MK70F12WS_fb.h" - #include "device/MK70F12WS/MK70F12WS_fmc.h" - #include "device/MK70F12WS/MK70F12WS_ftfe.h" - #include "device/MK70F12WS/MK70F12WS_ftm.h" - #include "device/MK70F12WS/MK70F12WS_gpio.h" - #include "device/MK70F12WS/MK70F12WS_i2c.h" - #include "device/MK70F12WS/MK70F12WS_i2s.h" - #include "device/MK70F12WS/MK70F12WS_lcdc.h" - #include "device/MK70F12WS/MK70F12WS_llwu.h" - #include "device/MK70F12WS/MK70F12WS_lmem.h" - #include "device/MK70F12WS/MK70F12WS_lptmr.h" - #include "device/MK70F12WS/MK70F12WS_mcg.h" - #include "device/MK70F12WS/MK70F12WS_mcm.h" - #include "device/MK70F12WS/MK70F12WS_mpu.h" - #include "device/MK70F12WS/MK70F12WS_nfc.h" - #include "device/MK70F12WS/MK70F12WS_nv.h" - #include "device/MK70F12WS/MK70F12WS_osc.h" - #include "device/MK70F12WS/MK70F12WS_pdb.h" - #include "device/MK70F12WS/MK70F12WS_pit.h" - #include "device/MK70F12WS/MK70F12WS_pmc.h" - #include "device/MK70F12WS/MK70F12WS_port.h" - #include "device/MK70F12WS/MK70F12WS_rcm.h" - #include "device/MK70F12WS/MK70F12WS_rfsys.h" - #include "device/MK70F12WS/MK70F12WS_rfvbat.h" - #include "device/MK70F12WS/MK70F12WS_rng.h" - #include "device/MK70F12WS/MK70F12WS_rtc.h" - #include "device/MK70F12WS/MK70F12WS_sdhc.h" - #include "device/MK70F12WS/MK70F12WS_sim.h" - #include "device/MK70F12WS/MK70F12WS_smc.h" - #include "device/MK70F12WS/MK70F12WS_spi.h" - #include "device/MK70F12WS/MK70F12WS_tsi.h" - #include "device/MK70F12WS/MK70F12WS_uart.h" - #include "device/MK70F12WS/MK70F12WS_usb.h" - #include "device/MK70F12WS/MK70F12WS_usbdcd.h" - #include "device/MK70F12WS/MK70F12WS_usbhs.h" - #include "device/MK70F12WS/MK70F12WS_vref.h" - #include "device/MK70F12WS/MK70F12WS_wdog.h" - - /* CMSIS-style register definitions*/ - #include "device/MK70F12WS/MK70F12WS.h" - -#elif (defined(CPU_MK70FN1M0VMJ12WS) || defined(CPU_MK70FX512VMJ12WS) || defined(CPU_MK70FN1M0VMJ15WS) || \ - defined(CPU_MK70FX512VMJ15WS)) - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/ - #include "device/MK70F15WS/MK70F15WS_adc.h" - #include "device/MK70F15WS/MK70F15WS_aips.h" - #include "device/MK70F15WS/MK70F15WS_axbs.h" - #include "device/MK70F15WS/MK70F15WS_can.h" - #include "device/MK70F15WS/MK70F15WS_cau.h" - #include "device/MK70F15WS/MK70F15WS_cmp.h" - #include "device/MK70F15WS/MK70F15WS_cmt.h" - #include "device/MK70F15WS/MK70F15WS_crc.h" - #include "device/MK70F15WS/MK70F15WS_dac.h" - #include "device/MK70F15WS/MK70F15WS_ddr.h" - #include "device/MK70F15WS/MK70F15WS_dma.h" - #include "device/MK70F15WS/MK70F15WS_dmamux.h" - #include "device/MK70F15WS/MK70F15WS_dry.h" - #include "device/MK70F15WS/MK70F15WS_enet.h" - #include "device/MK70F15WS/MK70F15WS_ewm.h" - #include "device/MK70F15WS/MK70F15WS_fb.h" - #include "device/MK70F15WS/MK70F15WS_fmc.h" - #include "device/MK70F15WS/MK70F15WS_ftfe.h" - #include "device/MK70F15WS/MK70F15WS_ftm.h" - #include "device/MK70F15WS/MK70F15WS_gpio.h" - #include "device/MK70F15WS/MK70F15WS_i2c.h" - #include "device/MK70F15WS/MK70F15WS_i2s.h" - #include "device/MK70F15WS/MK70F15WS_lcdc.h" - #include "device/MK70F15WS/MK70F15WS_llwu.h" - #include "device/MK70F15WS/MK70F15WS_lmem.h" - #include "device/MK70F15WS/MK70F15WS_lptmr.h" - #include "device/MK70F15WS/MK70F15WS_mcg.h" - #include "device/MK70F15WS/MK70F15WS_mcm.h" - #include "device/MK70F15WS/MK70F15WS_mpu.h" - #include "device/MK70F15WS/MK70F15WS_nfc.h" - #include "device/MK70F15WS/MK70F15WS_nv.h" - #include "device/MK70F15WS/MK70F15WS_osc.h" - #include "device/MK70F15WS/MK70F15WS_pdb.h" - #include "device/MK70F15WS/MK70F15WS_pit.h" - #include "device/MK70F15WS/MK70F15WS_pmc.h" - #include "device/MK70F15WS/MK70F15WS_port.h" - #include "device/MK70F15WS/MK70F15WS_rcm.h" - #include "device/MK70F15WS/MK70F15WS_rfsys.h" - #include "device/MK70F15WS/MK70F15WS_rfvbat.h" - #include "device/MK70F15WS/MK70F15WS_rng.h" - #include "device/MK70F15WS/MK70F15WS_rtc.h" - #include "device/MK70F15WS/MK70F15WS_sdhc.h" - #include "device/MK70F15WS/MK70F15WS_sim.h" - #include "device/MK70F15WS/MK70F15WS_smc.h" - #include "device/MK70F15WS/MK70F15WS_spi.h" - #include "device/MK70F15WS/MK70F15WS_tsi.h" - #include "device/MK70F15WS/MK70F15WS_uart.h" - #include "device/MK70F15WS/MK70F15WS_usb.h" - #include "device/MK70F15WS/MK70F15WS_usbdcd.h" - #include "device/MK70F15WS/MK70F15WS_usbhs.h" - #include "device/MK70F15WS/MK70F15WS_vref.h" - #include "device/MK70F15WS/MK70F15WS_wdog.h" - - /* CMSIS-style register definitions*/ - #include "device/MK70F15WS/MK70F15WS.h" - -#elif (defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \ - defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || \ - defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \ - defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4)) - #define KL25Z4_SERIES - /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/ - #include "device/MKL25Z4/MKL25Z4_adc.h" - #include "device/MKL25Z4/MKL25Z4_cmp.h" - #include "device/MKL25Z4/MKL25Z4_dac.h" - #include "device/MKL25Z4/MKL25Z4_dma.h" - #include "device/MKL25Z4/MKL25Z4_dmamux.h" - #include "device/MKL25Z4/MKL25Z4_fgpio.h" - #include "device/MKL25Z4/MKL25Z4_ftfa.h" - #include "device/MKL25Z4/MKL25Z4_gpio.h" - #include "device/MKL25Z4/MKL25Z4_i2c.h" - #include "device/MKL25Z4/MKL25Z4_llwu.h" - #include "device/MKL25Z4/MKL25Z4_lptmr.h" - #include "device/MKL25Z4/MKL25Z4_mcg.h" - #include "device/MKL25Z4/MKL25Z4_mcm.h" - #include "device/MKL25Z4/MKL25Z4_mtb.h" - #include "device/MKL25Z4/MKL25Z4_mtbdwt.h" - #include "device/MKL25Z4/MKL25Z4_nv.h" - #include "device/MKL25Z4/MKL25Z4_osc.h" - #include "device/MKL25Z4/MKL25Z4_pit.h" - #include "device/MKL25Z4/MKL25Z4_pmc.h" - #include "device/MKL25Z4/MKL25Z4_port.h" - #include "device/MKL25Z4/MKL25Z4_rcm.h" - #include "device/MKL25Z4/MKL25Z4_rom.h" - #include "device/MKL25Z4/MKL25Z4_rtc.h" - #include "device/MKL25Z4/MKL25Z4_sim.h" - #include "device/MKL25Z4/MKL25Z4_smc.h" - #include "device/MKL25Z4/MKL25Z4_spi.h" - #include "device/MKL25Z4/MKL25Z4_tpm.h" - #include "device/MKL25Z4/MKL25Z4_tsi.h" - #include "device/MKL25Z4/MKL25Z4_uart.h" - #include "device/MKL25Z4/MKL25Z4_uart0.h" - #include "device/MKL25Z4/MKL25Z4_usb.h" - - /* CMSIS-style register definitions*/ - #include "device/MKL25Z4/MKL25Z4.h" - -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_DEVICE_REGISTERS_H__*/ -/******************************************************************************* - * EOF - ******************************************************************************/
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/gpio_object.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,50 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#include "mbed_assert.h"
-#include "fsl_gpio_hal.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
- PinName pinName;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value) {
- MBED_ASSERT(obj->pinName != (PinName)NC);
- uint32_t port = obj->pinName >> GPIO_PORT_SHIFT;
- uint32_t pin = obj->pinName & 0xFF;
-
- gpio_hal_write_pin_output(port, pin, value);
-}
-
-static inline int gpio_read(gpio_t *obj) {
- MBED_ASSERT(obj->pinName != (PinName)NC);
- uint32_t port = obj->pinName >> GPIO_PORT_SHIFT;
- uint32_t pin = obj->pinName & 0xFF;
-
- return (int)gpio_hal_read_pin_input(port, pin);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/objects.h Fri Aug 15 15:28:31 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,69 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
- uint32_t port;
- uint32_t pin;
- uint32_t ch;
-};
-
-struct port_s {
- PortName port;
- uint32_t mask;
-};
-
-struct pwmout_s {
- PWMName pwm_name;
-};
-
-struct serial_s {
- int index;
-};
-
-struct analogin_s {
- ADCName adc;
-};
-
-struct i2c_s {
- uint32_t instance;
-};
-
-struct spi_s {
- uint32_t instance;
-};
-
-struct dac_s {
- DACName dac;
-};
-
-#include "gpio_object.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/PeripheralPins.h Fri Sep 12 16:41:52 2014 +0100 @@ -0,0 +1,49 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +/************RTC***************/ +extern const PinMap PinMap_RTC[]; + +/************ADC***************/ +extern const PinMap PinMap_ADC[]; + +/************DAC***************/ +extern const PinMap PinMap_DAC[]; + +/************I2C***************/ +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; + +/************UART***************/ +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; + +/************SPI***************/ +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SSEL[]; + +/************PWM***************/ +extern const PinMap PinMap_PWM[]; + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/PortNames.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,35 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PortA = 0,
+ PortB = 1,
+ PortC = 2,
+ PortD = 3,
+ PortE = 4
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/PeripheralNames.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,131 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ OSC32KCLK = 0,
+} RTCName;
+
+typedef enum {
+ UART_0 = 0,
+ UART_1 = 1,
+ UART_2 = 2,
+ UART_3 = 3,
+ UART_4 = 4,
+} UARTName;
+
+#define STDIO_UART_TX USBTX
+#define STDIO_UART_RX USBRX
+#define STDIO_UART UART_0
+
+typedef enum {
+ I2C_0 = 0,
+ I2C_1 = 1,
+ I2C_2 = 2,
+} I2CName;
+
+#define TPM_SHIFT 8
+typedef enum {
+ PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0
+ PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1
+ PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2
+ PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3
+ PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4
+ PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5
+ PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6
+ PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7
+ PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0
+ PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1
+ PWM_11 = (1 << TPM_SHIFT) | (2), // FTM1 CH2
+ PWM_12 = (1 << TPM_SHIFT) | (3), // FTM1 CH3
+ PWM_13 = (1 << TPM_SHIFT) | (4), // FTM1 CH4
+ PWM_14 = (1 << TPM_SHIFT) | (5), // FTM1 CH5
+ PWM_15 = (1 << TPM_SHIFT) | (6), // FTM1 CH6
+ PWM_16 = (1 << TPM_SHIFT) | (7), // FTM1 CH7
+ PWM_17 = (2 << TPM_SHIFT) | (0), // FTM2 CH0
+ PWM_18 = (2 << TPM_SHIFT) | (1), // FTM2 CH1
+ PWM_19 = (2 << TPM_SHIFT) | (2), // FTM2 CH2
+ PWM_20 = (2 << TPM_SHIFT) | (3), // FTM2 CH3
+ PWM_21 = (2 << TPM_SHIFT) | (4), // FTM2 CH4
+ PWM_22 = (2 << TPM_SHIFT) | (5), // FTM2 CH5
+ PWM_23 = (2 << TPM_SHIFT) | (6), // FTM2 CH6
+ PWM_24 = (2 << TPM_SHIFT) | (7), // FTM2 CH7
+ // could be 4 or could be 3... not sure what register
+ // this is for... too much abstraction
+ PWM_25 = (3 << TPM_SHIFT) | (0), // FTM3 CH0
+ PWM_26 = (3 << TPM_SHIFT) | (1), // FTM3 CH1
+ PWM_27 = (3 << TPM_SHIFT) | (2), // FTM3 CH2
+ PWM_28 = (3 << TPM_SHIFT) | (3), // FTM3 CH3
+ PWM_29 = (3 << TPM_SHIFT) | (4), // FTM3 CH4
+ PWM_30 = (3 << TPM_SHIFT) | (5), // FTM3 CH5
+ PWM_31 = (3 << TPM_SHIFT) | (6), // FTM3 CH6
+ PWM_32 = (3 << TPM_SHIFT) | (7), // FTM3 CH7
+} PWMName;
+
+#define ADC_INSTANCE_SHIFT 8
+#define ADC_B_CHANNEL_SHIFT 5
+typedef enum {
+ ADC0_SE4b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4,
+ ADC0_SE5b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5,
+ ADC0_SE6b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6,
+ ADC0_SE7b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7,
+ ADC0_SE8 = (0 << ADC_INSTANCE_SHIFT) | 8,
+ ADC0_SE9 = (0 << ADC_INSTANCE_SHIFT) | 9,
+ ADC0_SE12 = (0 << ADC_INSTANCE_SHIFT) | 12,
+ ADC0_SE13 = (0 << ADC_INSTANCE_SHIFT) | 13,
+ ADC0_SE14 = (0 << ADC_INSTANCE_SHIFT) | 14,
+ ADC0_SE15 = (0 << ADC_INSTANCE_SHIFT) | 15,
+ ADC0_SE16 = (0 << ADC_INSTANCE_SHIFT) | 16,
+ ADC0_SE17 = (0 << ADC_INSTANCE_SHIFT) | 17,
+ ADC0_SE18 = (0 << ADC_INSTANCE_SHIFT) | 18,
+ ADC1_SE4b = (1 << ADC_INSTANCE_SHIFT) | 4,
+ ADC1_SE5b = (1 << ADC_INSTANCE_SHIFT) | 5,
+ ADC1_SE6b = (1 << ADC_INSTANCE_SHIFT) | 6,
+ ADC1_SE7b = (1 << ADC_INSTANCE_SHIFT) | 7,
+ ADC1_SE8 = (1 << ADC_INSTANCE_SHIFT) | 8,
+ ADC1_SE9 = (1 << ADC_INSTANCE_SHIFT) | 9,
+ ADC1_SE12 = (1 << ADC_INSTANCE_SHIFT) | 12,
+ ADC1_SE13 = (1 << ADC_INSTANCE_SHIFT) | 13,
+ ADC1_SE14 = (1 << ADC_INSTANCE_SHIFT) | 14,
+ ADC1_SE15 = (1 << ADC_INSTANCE_SHIFT) | 15,
+ ADC1_SE16 = (1 << ADC_INSTANCE_SHIFT) | 16,
+ ADC1_SE17 = (1 << ADC_INSTANCE_SHIFT) | 17,
+ ADC1_SE18 = (1 << ADC_INSTANCE_SHIFT) | 18,
+} ADCName;
+
+typedef enum {
+ DAC_0 = 0
+} DACName;
+
+
+typedef enum {
+ SPI_0 = 0,
+ SPI_1 = 1,
+ SPI_2 = 2,
+} SPIName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/PinNames.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,258 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+#define GPIO_PORT_SHIFT 12
+
+typedef enum {
+ PTA0 = (0 << GPIO_PORT_SHIFT | 0 ),
+ PTA1 = (0 << GPIO_PORT_SHIFT | 1 ),
+ PTA2 = (0 << GPIO_PORT_SHIFT | 2 ),
+ PTA3 = (0 << GPIO_PORT_SHIFT | 3 ),
+ PTA4 = (0 << GPIO_PORT_SHIFT | 4 ),
+ PTA5 = (0 << GPIO_PORT_SHIFT | 5 ),
+ PTA6 = (0 << GPIO_PORT_SHIFT | 6 ),
+ PTA7 = (0 << GPIO_PORT_SHIFT | 7 ),
+ PTA8 = (0 << GPIO_PORT_SHIFT | 8 ),
+ PTA9 = (0 << GPIO_PORT_SHIFT | 9 ),
+ PTA10 = (0 << GPIO_PORT_SHIFT | 10),
+ PTA11 = (0 << GPIO_PORT_SHIFT | 11),
+ PTA12 = (0 << GPIO_PORT_SHIFT | 12),
+ PTA13 = (0 << GPIO_PORT_SHIFT | 13),
+ PTA14 = (0 << GPIO_PORT_SHIFT | 14),
+ PTA15 = (0 << GPIO_PORT_SHIFT | 15),
+ PTA16 = (0 << GPIO_PORT_SHIFT | 16),
+ PTA17 = (0 << GPIO_PORT_SHIFT | 17),
+ PTA18 = (0 << GPIO_PORT_SHIFT | 18),
+ PTA19 = (0 << GPIO_PORT_SHIFT | 19),
+ PTA20 = (0 << GPIO_PORT_SHIFT | 20),
+ PTA21 = (0 << GPIO_PORT_SHIFT | 21),
+ PTA22 = (0 << GPIO_PORT_SHIFT | 22),
+ PTA23 = (0 << GPIO_PORT_SHIFT | 23),
+ PTA24 = (0 << GPIO_PORT_SHIFT | 24),
+ PTA25 = (0 << GPIO_PORT_SHIFT | 25),
+ PTA26 = (0 << GPIO_PORT_SHIFT | 26),
+ PTA27 = (0 << GPIO_PORT_SHIFT | 27),
+ PTA28 = (0 << GPIO_PORT_SHIFT | 28),
+ PTA29 = (0 << GPIO_PORT_SHIFT | 29),
+ PTA30 = (0 << GPIO_PORT_SHIFT | 30),
+ PTA31 = (0 << GPIO_PORT_SHIFT | 31),
+ PTB0 = (1 << GPIO_PORT_SHIFT | 0 ),
+ PTB1 = (1 << GPIO_PORT_SHIFT | 1 ),
+ PTB2 = (1 << GPIO_PORT_SHIFT | 2 ),
+ PTB3 = (1 << GPIO_PORT_SHIFT | 3 ),
+ PTB4 = (1 << GPIO_PORT_SHIFT | 4 ),
+ PTB5 = (1 << GPIO_PORT_SHIFT | 5 ),
+ PTB6 = (1 << GPIO_PORT_SHIFT | 6 ),
+ PTB7 = (1 << GPIO_PORT_SHIFT | 7 ),
+ PTB8 = (1 << GPIO_PORT_SHIFT | 8 ),
+ PTB9 = (1 << GPIO_PORT_SHIFT | 9 ),
+ PTB10 = (1 << GPIO_PORT_SHIFT | 10),
+ PTB11 = (1 << GPIO_PORT_SHIFT | 11),
+ PTB12 = (1 << GPIO_PORT_SHIFT | 12),
+ PTB13 = (1 << GPIO_PORT_SHIFT | 13),
+ PTB14 = (1 << GPIO_PORT_SHIFT | 14),
+ PTB15 = (1 << GPIO_PORT_SHIFT | 15),
+ PTB16 = (1 << GPIO_PORT_SHIFT | 16),
+ PTB17 = (1 << GPIO_PORT_SHIFT | 17),
+ PTB18 = (1 << GPIO_PORT_SHIFT | 18),
+ PTB19 = (1 << GPIO_PORT_SHIFT | 19),
+ PTB20 = (1 << GPIO_PORT_SHIFT | 20),
+ PTB21 = (1 << GPIO_PORT_SHIFT | 21),
+ PTB22 = (1 << GPIO_PORT_SHIFT | 22),
+ PTB23 = (1 << GPIO_PORT_SHIFT | 23),
+ PTB24 = (1 << GPIO_PORT_SHIFT | 24),
+ PTB25 = (1 << GPIO_PORT_SHIFT | 25),
+ PTB26 = (1 << GPIO_PORT_SHIFT | 26),
+ PTB27 = (1 << GPIO_PORT_SHIFT | 27),
+ PTB28 = (1 << GPIO_PORT_SHIFT | 28),
+ PTB29 = (1 << GPIO_PORT_SHIFT | 29),
+ PTB30 = (1 << GPIO_PORT_SHIFT | 30),
+ PTB31 = (1 << GPIO_PORT_SHIFT | 31),
+ PTC0 = (2 << GPIO_PORT_SHIFT | 0 ),
+ PTC1 = (2 << GPIO_PORT_SHIFT | 1 ),
+ PTC2 = (2 << GPIO_PORT_SHIFT | 2 ),
+ PTC3 = (2 << GPIO_PORT_SHIFT | 3 ),
+ PTC4 = (2 << GPIO_PORT_SHIFT | 4 ),
+ PTC5 = (2 << GPIO_PORT_SHIFT | 5 ),
+ PTC6 = (2 << GPIO_PORT_SHIFT | 6 ),
+ PTC7 = (2 << GPIO_PORT_SHIFT | 7 ),
+ PTC8 = (2 << GPIO_PORT_SHIFT | 8 ),
+ PTC9 = (2 << GPIO_PORT_SHIFT | 9 ),
+ PTC10 = (2 << GPIO_PORT_SHIFT | 10),
+ PTC11 = (2 << GPIO_PORT_SHIFT | 11),
+ PTC12 = (2 << GPIO_PORT_SHIFT | 12),
+ PTC13 = (2 << GPIO_PORT_SHIFT | 13),
+ PTC14 = (2 << GPIO_PORT_SHIFT | 14),
+ PTC15 = (2 << GPIO_PORT_SHIFT | 15),
+ PTC16 = (2 << GPIO_PORT_SHIFT | 16),
+ PTC17 = (2 << GPIO_PORT_SHIFT | 17),
+ PTC18 = (2 << GPIO_PORT_SHIFT | 18),
+ PTC19 = (2 << GPIO_PORT_SHIFT | 19),
+ PTC20 = (2 << GPIO_PORT_SHIFT | 20),
+ PTC21 = (2 << GPIO_PORT_SHIFT | 21),
+ PTC22 = (2 << GPIO_PORT_SHIFT | 22),
+ PTC23 = (2 << GPIO_PORT_SHIFT | 23),
+ PTC24 = (2 << GPIO_PORT_SHIFT | 24),
+ PTC25 = (2 << GPIO_PORT_SHIFT | 25),
+ PTC26 = (2 << GPIO_PORT_SHIFT | 26),
+ PTC27 = (2 << GPIO_PORT_SHIFT | 27),
+ PTC28 = (2 << GPIO_PORT_SHIFT | 28),
+ PTC29 = (2 << GPIO_PORT_SHIFT | 29),
+ PTC30 = (2 << GPIO_PORT_SHIFT | 30),
+ PTC31 = (2 << GPIO_PORT_SHIFT | 31),
+ PTD0 = (3 << GPIO_PORT_SHIFT | 0 ),
+ PTD1 = (3 << GPIO_PORT_SHIFT | 1 ),
+ PTD2 = (3 << GPIO_PORT_SHIFT | 2 ),
+ PTD3 = (3 << GPIO_PORT_SHIFT | 3 ),
+ PTD4 = (3 << GPIO_PORT_SHIFT | 4 ),
+ PTD5 = (3 << GPIO_PORT_SHIFT | 5 ),
+ PTD6 = (3 << GPIO_PORT_SHIFT | 6 ),
+ PTD7 = (3 << GPIO_PORT_SHIFT | 7 ),
+ PTD8 = (3 << GPIO_PORT_SHIFT | 8 ),
+ PTD9 = (3 << GPIO_PORT_SHIFT | 9 ),
+ PTD10 = (3 << GPIO_PORT_SHIFT | 10),
+ PTD11 = (3 << GPIO_PORT_SHIFT | 11),
+ PTD12 = (3 << GPIO_PORT_SHIFT | 12),
+ PTD13 = (3 << GPIO_PORT_SHIFT | 13),
+ PTD14 = (3 << GPIO_PORT_SHIFT | 14),
+ PTD15 = (3 << GPIO_PORT_SHIFT | 15),
+ PTD16 = (3 << GPIO_PORT_SHIFT | 16),
+ PTD17 = (3 << GPIO_PORT_SHIFT | 17),
+ PTD18 = (3 << GPIO_PORT_SHIFT | 18),
+ PTD19 = (3 << GPIO_PORT_SHIFT | 19),
+ PTD20 = (3 << GPIO_PORT_SHIFT | 20),
+ PTD21 = (3 << GPIO_PORT_SHIFT | 21),
+ PTD22 = (3 << GPIO_PORT_SHIFT | 22),
+ PTD23 = (3 << GPIO_PORT_SHIFT | 23),
+ PTD24 = (3 << GPIO_PORT_SHIFT | 24),
+ PTD25 = (3 << GPIO_PORT_SHIFT | 25),
+ PTD26 = (3 << GPIO_PORT_SHIFT | 26),
+ PTD27 = (3 << GPIO_PORT_SHIFT | 27),
+ PTD28 = (3 << GPIO_PORT_SHIFT | 28),
+ PTD29 = (3 << GPIO_PORT_SHIFT | 29),
+ PTD30 = (3 << GPIO_PORT_SHIFT | 30),
+ PTD31 = (3 << GPIO_PORT_SHIFT | 31),
+ PTE0 = (4 << GPIO_PORT_SHIFT | 0 ),
+ PTE1 = (4 << GPIO_PORT_SHIFT | 1 ),
+ PTE2 = (4 << GPIO_PORT_SHIFT | 2 ),
+ PTE3 = (4 << GPIO_PORT_SHIFT | 3 ),
+ PTE4 = (4 << GPIO_PORT_SHIFT | 4 ),
+ PTE5 = (4 << GPIO_PORT_SHIFT | 5 ),
+ PTE6 = (4 << GPIO_PORT_SHIFT | 6 ),
+ PTE7 = (4 << GPIO_PORT_SHIFT | 7 ),
+ PTE8 = (4 << GPIO_PORT_SHIFT | 8 ),
+ PTE9 = (4 << GPIO_PORT_SHIFT | 9 ),
+ PTE10 = (4 << GPIO_PORT_SHIFT | 10),
+ PTE11 = (4 << GPIO_PORT_SHIFT | 11),
+ PTE12 = (4 << GPIO_PORT_SHIFT | 12),
+ PTE13 = (4 << GPIO_PORT_SHIFT | 13),
+ PTE14 = (4 << GPIO_PORT_SHIFT | 14),
+ PTE15 = (4 << GPIO_PORT_SHIFT | 15),
+ PTE16 = (4 << GPIO_PORT_SHIFT | 16),
+ PTE17 = (4 << GPIO_PORT_SHIFT | 17),
+ PTE18 = (4 << GPIO_PORT_SHIFT | 18),
+ PTE19 = (4 << GPIO_PORT_SHIFT | 19),
+ PTE20 = (4 << GPIO_PORT_SHIFT | 20),
+ PTE21 = (4 << GPIO_PORT_SHIFT | 21),
+ PTE22 = (4 << GPIO_PORT_SHIFT | 22),
+ PTE23 = (4 << GPIO_PORT_SHIFT | 23),
+ PTE24 = (4 << GPIO_PORT_SHIFT | 24),
+ PTE25 = (4 << GPIO_PORT_SHIFT | 25),
+ PTE26 = (4 << GPIO_PORT_SHIFT | 26),
+ PTE27 = (4 << GPIO_PORT_SHIFT | 27),
+ PTE28 = (4 << GPIO_PORT_SHIFT | 28),
+ PTE29 = (4 << GPIO_PORT_SHIFT | 29),
+ PTE30 = (4 << GPIO_PORT_SHIFT | 30),
+ PTE31 = (4 << GPIO_PORT_SHIFT | 31),
+
+ LED_RED = PTB22,
+ LED_GREEN = PTE26,
+ LED_BLUE = PTB21,
+
+ // mbed original LED naming
+ LED1 = LED_RED,
+ LED2 = LED_GREEN,
+ LED3 = LED_BLUE,
+ LED4 = LED_RED,
+
+ //Push buttons
+ SW2 = PTC6,
+ SW3 = PTA4,
+
+ // USB Pins
+ USBTX = PTB17,
+ USBRX = PTB16,
+
+ // Arduino Headers
+ D0 = PTC16,
+ D1 = PTC17,
+ D2 = PTB9,
+ D3 = PTA1,
+ D4 = PTB23,
+ D5 = PTA2,
+ D6 = PTC2,
+ D7 = PTC3,
+ D8 = PTA0,
+ D9 = PTC4,
+ D10 = PTD0,
+ D11 = PTD2,
+ D12 = PTD3,
+ D13 = PTD1,
+ D14 = PTE25,
+ D15 = PTE24,
+
+ I2C_SCL = D15,
+ I2C_SDA = D14,
+
+ A0 = PTB2,
+ A1 = PTB3,
+ A2 = PTB10,
+ A3 = PTB11,
+ A4 = PTC10,
+ A5 = PTC11,
+
+ DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+
+typedef enum {
+ PullNone = 0,
+ PullDown = 1,
+ PullUp = 2,
+ PullDefault = PullUp
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/device.h Fri Sep 12 16:41:52 2014 +0100 @@ -0,0 +1,58 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 1 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 1 + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,13704 @@
+/*
+** ###################################################################
+** Processor: MK64FN1M0VMD12
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** GNU C Compiler - CodeSourcery Sourcery G++
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
+** Version: rev. 2.3, 2014-01-24
+**
+** Abstract:
+** CMSIS Peripheral Access Layer for MK64F12
+**
+** Copyright: 1997 - 2014 Freescale, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2013-08-12)
+** Initial version.
+** - rev. 2.0 (2013-10-29)
+** Register accessor macros added to the memory map.
+** Symbols for Processor Expert memory map compatibility added to the memory map.
+** Startup file for gcc has been updated according to CMSIS 3.2.
+** System initialization updated.
+** MCG - registers updated.
+** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+** - rev. 2.1 (2013-10-29)
+** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+** - rev. 2.2 (2013-12-09)
+** DMA - EARS register removed.
+** AIPS0, AIPS1 - MPRA register updated.
+** - rev. 2.3 (2014-01-24)
+** Update according to reference manual rev. 2
+** ENET, MCG, MCM, SIM, USB - registers updated
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK64F12.h
+ * @version 2.3
+ * @date 2014-01-24
+ * @brief CMSIS Peripheral Access Layer for MK64F12
+ *
+ * CMSIS Peripheral Access Layer for MK64F12
+ */
+
+#if !defined(MK64F12_H_)
+#define MK64F12_H_ /**< Symbol preventing repeated inclusion */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCU activation
+ ---------------------------------------------------------------------------- */
+
+/* Prevention from multiple including the same memory map */
+#if !defined(MCU_MK64F12) /* Check if memory map has not been already included */
+#define MCU_MK64F12
+
+/* Check if another memory map has not been also included */
+#if (defined(MCU_ACTIVE))
+ #error MK64F12 memory map: There is already included another memory map. Only one memory map can be included.
+#endif /* (defined(MCU_ACTIVE)) */
+#define MCU_ACTIVE
+
+#include <stdint.h>
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0200u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0003u
+
+/**
+ * @brief Macro to calculate address of an aliased word in the peripheral
+ * bitband area for a peripheral register and bit (bit band region 0x40000000 to
+ * 0x400FFFFF).
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Address of the aliased word in the peripheral bitband area.
+ */
+#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ * be used for peripherals with 32bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ * be used for peripherals with 16bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ * be used for peripherals with 8bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+
+/* ----------------------------------------------------------------------------
+ -- Interrupt vector numbers
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+typedef enum IRQn {
+ /* Core interrupts */
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
+
+ /* Device specific interrupts */
+ DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */
+ DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */
+ DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */
+ DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */
+ DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */
+ DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */
+ DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */
+ DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */
+ DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */
+ DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */
+ DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */
+ DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */
+ DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */
+ DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */
+ DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */
+ DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */
+ DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
+ MCM_IRQn = 17, /**< Normal Interrupt */
+ FTFE_IRQn = 18, /**< FTFE Command complete interrupt */
+ Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
+ LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
+ LLW_IRQn = 21, /**< Low Leakage Wakeup */
+ Watchdog_IRQn = 22, /**< WDOG Interrupt */
+ RNG_IRQn = 23, /**< RNG Interrupt */
+ I2C0_IRQn = 24, /**< I2C0 interrupt */
+ I2C1_IRQn = 25, /**< I2C1 interrupt */
+ SPI0_IRQn = 26, /**< SPI0 Interrupt */
+ SPI1_IRQn = 27, /**< SPI1 Interrupt */
+ I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */
+ I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */
+ UART0_LON_IRQn = 30, /**< UART0 LON interrupt */
+ UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */
+ UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */
+ UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */
+ UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */
+ UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */
+ UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */
+ UART3_RX_TX_IRQn = 37, /**< UART3 Receive/Transmit interrupt */
+ UART3_ERR_IRQn = 38, /**< UART3 Error interrupt */
+ ADC0_IRQn = 39, /**< ADC0 interrupt */
+ CMP0_IRQn = 40, /**< CMP0 interrupt */
+ CMP1_IRQn = 41, /**< CMP1 interrupt */
+ FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */
+ FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */
+ FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */
+ CMT_IRQn = 45, /**< CMT interrupt */
+ RTC_IRQn = 46, /**< RTC interrupt */
+ RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */
+ PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */
+ PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */
+ PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
+ PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
+ PDB0_IRQn = 52, /**< PDB0 Interrupt */
+ USB0_IRQn = 53, /**< USB0 interrupt */
+ USBDCD_IRQn = 54, /**< USBDCD Interrupt */
+ Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
+ DAC0_IRQn = 56, /**< DAC0 interrupt */
+ MCG_IRQn = 57, /**< MCG Interrupt */
+ LPTimer_IRQn = 58, /**< LPTimer interrupt */
+ PORTA_IRQn = 59, /**< Port A interrupt */
+ PORTB_IRQn = 60, /**< Port B interrupt */
+ PORTC_IRQn = 61, /**< Port C interrupt */
+ PORTD_IRQn = 62, /**< Port D interrupt */
+ PORTE_IRQn = 63, /**< Port E interrupt */
+ SWI_IRQn = 64, /**< Software interrupt */
+ SPI2_IRQn = 65, /**< SPI2 Interrupt */
+ UART4_RX_TX_IRQn = 66, /**< UART4 Receive/Transmit interrupt */
+ UART4_ERR_IRQn = 67, /**< UART4 Error interrupt */
+ UART5_RX_TX_IRQn = 68, /**< UART5 Receive/Transmit interrupt */
+ UART5_ERR_IRQn = 69, /**< UART5 Error interrupt */
+ CMP2_IRQn = 70, /**< CMP2 interrupt */
+ FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */
+ DAC1_IRQn = 72, /**< DAC1 interrupt */
+ ADC1_IRQn = 73, /**< ADC1 interrupt */
+ I2C2_IRQn = 74, /**< I2C2 interrupt */
+ CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */
+ CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */
+ CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */
+ CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */
+ CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */
+ CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */
+ SDHC_IRQn = 81, /**< SDHC interrupt */
+ ENET_1588_Timer_IRQn = 82, /**< Ethernet MAC IEEE 1588 Timer Interrupt */
+ ENET_Transmit_IRQn = 83, /**< Ethernet MAC Transmit Interrupt */
+ ENET_Receive_IRQn = 84, /**< Ethernet MAC Receive Interrupt */
+ ENET_Error_IRQn = 85 /**< Ethernet MAC Error and miscelaneous Interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+ -- Cortex M4 Core Configuration
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
+
+#include "core_cm4.h" /* Core Peripheral Access Layer */
+#include "system_MK64F12.h" /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+ -- Device Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__CWCC__)
+ #pragma push
+ #pragma cpp_extensions on
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- ADC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+ __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
+ __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
+ __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+ __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
+ __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
+ __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
+ __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
+ __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
+ __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
+ __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
+ __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+ __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+ __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+ __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+ __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+ __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+ __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
+ __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
+ __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
+ __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
+ __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
+ __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
+ __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
+} ADC_Type, *ADC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- ADC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register accessors */
+#define ADC_SC1_REG(base,index) ((base)->SC1[index])
+#define ADC_CFG1_REG(base) ((base)->CFG1)
+#define ADC_CFG2_REG(base) ((base)->CFG2)
+#define ADC_R_REG(base,index) ((base)->R[index])
+#define ADC_CV1_REG(base) ((base)->CV1)
+#define ADC_CV2_REG(base) ((base)->CV2)
+#define ADC_SC2_REG(base) ((base)->SC2)
+#define ADC_SC3_REG(base) ((base)->SC3)
+#define ADC_OFS_REG(base) ((base)->OFS)
+#define ADC_PG_REG(base) ((base)->PG)
+#define ADC_MG_REG(base) ((base)->MG)
+#define ADC_CLPD_REG(base) ((base)->CLPD)
+#define ADC_CLPS_REG(base) ((base)->CLPS)
+#define ADC_CLP4_REG(base) ((base)->CLP4)
+#define ADC_CLP3_REG(base) ((base)->CLP3)
+#define ADC_CLP2_REG(base) ((base)->CLP2)
+#define ADC_CLP1_REG(base) ((base)->CLP1)
+#define ADC_CLP0_REG(base) ((base)->CLP0)
+#define ADC_CLMD_REG(base) ((base)->CLMD)
+#define ADC_CLMS_REG(base) ((base)->CLMS)
+#define ADC_CLM4_REG(base) ((base)->CLM4)
+#define ADC_CLM3_REG(base) ((base)->CLM3)
+#define ADC_CLM2_REG(base) ((base)->CLM2)
+#define ADC_CLM1_REG(base) ((base)->CLM1)
+#define ADC_CLM0_REG(base) ((base)->CLM0)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- ADC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK 0x1Fu
+#define ADC_SC1_ADCH_SHIFT 0
+#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK 0x20u
+#define ADC_SC1_DIFF_SHIFT 5
+#define ADC_SC1_AIEN_MASK 0x40u
+#define ADC_SC1_AIEN_SHIFT 6
+#define ADC_SC1_COCO_MASK 0x80u
+#define ADC_SC1_COCO_SHIFT 7
+/* CFG1 Bit Fields */
+#define ADC_CFG1_ADICLK_MASK 0x3u
+#define ADC_CFG1_ADICLK_SHIFT 0
+#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK 0xCu
+#define ADC_CFG1_MODE_SHIFT 2
+#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK 0x10u
+#define ADC_CFG1_ADLSMP_SHIFT 4
+#define ADC_CFG1_ADIV_MASK 0x60u
+#define ADC_CFG1_ADIV_SHIFT 5
+#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK 0x80u
+#define ADC_CFG1_ADLPC_SHIFT 7
+/* CFG2 Bit Fields */
+#define ADC_CFG2_ADLSTS_MASK 0x3u
+#define ADC_CFG2_ADLSTS_SHIFT 0
+#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK 0x4u
+#define ADC_CFG2_ADHSC_SHIFT 2
+#define ADC_CFG2_ADACKEN_MASK 0x8u
+#define ADC_CFG2_ADACKEN_SHIFT 3
+#define ADC_CFG2_MUXSEL_MASK 0x10u
+#define ADC_CFG2_MUXSEL_SHIFT 4
+/* R Bit Fields */
+#define ADC_R_D_MASK 0xFFFFu
+#define ADC_R_D_SHIFT 0
+#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
+/* CV1 Bit Fields */
+#define ADC_CV1_CV_MASK 0xFFFFu
+#define ADC_CV1_CV_SHIFT 0
+#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
+/* CV2 Bit Fields */
+#define ADC_CV2_CV_MASK 0xFFFFu
+#define ADC_CV2_CV_SHIFT 0
+#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK 0x3u
+#define ADC_SC2_REFSEL_SHIFT 0
+#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK 0x4u
+#define ADC_SC2_DMAEN_SHIFT 2
+#define ADC_SC2_ACREN_MASK 0x8u
+#define ADC_SC2_ACREN_SHIFT 3
+#define ADC_SC2_ACFGT_MASK 0x10u
+#define ADC_SC2_ACFGT_SHIFT 4
+#define ADC_SC2_ACFE_MASK 0x20u
+#define ADC_SC2_ACFE_SHIFT 5
+#define ADC_SC2_ADTRG_MASK 0x40u
+#define ADC_SC2_ADTRG_SHIFT 6
+#define ADC_SC2_ADACT_MASK 0x80u
+#define ADC_SC2_ADACT_SHIFT 7
+/* SC3 Bit Fields */
+#define ADC_SC3_AVGS_MASK 0x3u
+#define ADC_SC3_AVGS_SHIFT 0
+#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK 0x4u
+#define ADC_SC3_AVGE_SHIFT 2
+#define ADC_SC3_ADCO_MASK 0x8u
+#define ADC_SC3_ADCO_SHIFT 3
+#define ADC_SC3_CALF_MASK 0x40u
+#define ADC_SC3_CALF_SHIFT 6
+#define ADC_SC3_CAL_MASK 0x80u
+#define ADC_SC3_CAL_SHIFT 7
+/* OFS Bit Fields */
+#define ADC_OFS_OFS_MASK 0xFFFFu
+#define ADC_OFS_OFS_SHIFT 0
+#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
+/* PG Bit Fields */
+#define ADC_PG_PG_MASK 0xFFFFu
+#define ADC_PG_PG_SHIFT 0
+#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
+/* MG Bit Fields */
+#define ADC_MG_MG_MASK 0xFFFFu
+#define ADC_MG_MG_SHIFT 0
+#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
+/* CLPD Bit Fields */
+#define ADC_CLPD_CLPD_MASK 0x3Fu
+#define ADC_CLPD_CLPD_SHIFT 0
+#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
+/* CLPS Bit Fields */
+#define ADC_CLPS_CLPS_MASK 0x3Fu
+#define ADC_CLPS_CLPS_SHIFT 0
+#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
+/* CLP4 Bit Fields */
+#define ADC_CLP4_CLP4_MASK 0x3FFu
+#define ADC_CLP4_CLP4_SHIFT 0
+#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
+/* CLP3 Bit Fields */
+#define ADC_CLP3_CLP3_MASK 0x1FFu
+#define ADC_CLP3_CLP3_SHIFT 0
+#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
+/* CLP2 Bit Fields */
+#define ADC_CLP2_CLP2_MASK 0xFFu
+#define ADC_CLP2_CLP2_SHIFT 0
+#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
+/* CLP1 Bit Fields */
+#define ADC_CLP1_CLP1_MASK 0x7Fu
+#define ADC_CLP1_CLP1_SHIFT 0
+#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
+/* CLP0 Bit Fields */
+#define ADC_CLP0_CLP0_MASK 0x3Fu
+#define ADC_CLP0_CLP0_SHIFT 0
+#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
+/* CLMD Bit Fields */
+#define ADC_CLMD_CLMD_MASK 0x3Fu
+#define ADC_CLMD_CLMD_SHIFT 0
+#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
+/* CLMS Bit Fields */
+#define ADC_CLMS_CLMS_MASK 0x3Fu
+#define ADC_CLMS_CLMS_SHIFT 0
+#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
+/* CLM4 Bit Fields */
+#define ADC_CLM4_CLM4_MASK 0x3FFu
+#define ADC_CLM4_CLM4_SHIFT 0
+#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
+/* CLM3 Bit Fields */
+#define ADC_CLM3_CLM3_MASK 0x1FFu
+#define ADC_CLM3_CLM3_SHIFT 0
+#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
+/* CLM2 Bit Fields */
+#define ADC_CLM2_CLM2_MASK 0xFFu
+#define ADC_CLM2_CLM2_SHIFT 0
+#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
+/* CLM1 Bit Fields */
+#define ADC_CLM1_CLM1_MASK 0x7Fu
+#define ADC_CLM1_CLM1_SHIFT 0
+#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
+/* CLM0 Bit Fields */
+#define ADC_CLM0_CLM0_MASK 0x3Fu
+#define ADC_CLM0_CLM0_SHIFT 0
+#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0 ((ADC_Type *)ADC0_BASE)
+#define ADC0_BASE_PTR (ADC0)
+/** Peripheral ADC1 base address */
+#define ADC1_BASE (0x400BB000u)
+/** Peripheral ADC1 base pointer */
+#define ADC1 ((ADC_Type *)ADC1_BASE)
+#define ADC1_BASE_PTR (ADC1)
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASES { ADC0, ADC1 }
+
+/* ----------------------------------------------------------------------------
+ -- ADC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register instance definitions */
+/* ADC0 */
+#define ADC0_SC1A ADC_SC1_REG(ADC0,0)
+#define ADC0_SC1B ADC_SC1_REG(ADC0,1)
+#define ADC0_CFG1 ADC_CFG1_REG(ADC0)
+#define ADC0_CFG2 ADC_CFG2_REG(ADC0)
+#define ADC0_RA ADC_R_REG(ADC0,0)
+#define ADC0_RB ADC_R_REG(ADC0,1)
+#define ADC0_CV1 ADC_CV1_REG(ADC0)
+#define ADC0_CV2 ADC_CV2_REG(ADC0)
+#define ADC0_SC2 ADC_SC2_REG(ADC0)
+#define ADC0_SC3 ADC_SC3_REG(ADC0)
+#define ADC0_OFS ADC_OFS_REG(ADC0)
+#define ADC0_PG ADC_PG_REG(ADC0)
+#define ADC0_MG ADC_MG_REG(ADC0)
+#define ADC0_CLPD ADC_CLPD_REG(ADC0)
+#define ADC0_CLPS ADC_CLPS_REG(ADC0)
+#define ADC0_CLP4 ADC_CLP4_REG(ADC0)
+#define ADC0_CLP3 ADC_CLP3_REG(ADC0)
+#define ADC0_CLP2 ADC_CLP2_REG(ADC0)
+#define ADC0_CLP1 ADC_CLP1_REG(ADC0)
+#define ADC0_CLP0 ADC_CLP0_REG(ADC0)
+#define ADC0_CLMD ADC_CLMD_REG(ADC0)
+#define ADC0_CLMS ADC_CLMS_REG(ADC0)
+#define ADC0_CLM4 ADC_CLM4_REG(ADC0)
+#define ADC0_CLM3 ADC_CLM3_REG(ADC0)
+#define ADC0_CLM2 ADC_CLM2_REG(ADC0)
+#define ADC0_CLM1 ADC_CLM1_REG(ADC0)
+#define ADC0_CLM0 ADC_CLM0_REG(ADC0)
+/* ADC1 */
+#define ADC1_SC1A ADC_SC1_REG(ADC1,0)
+#define ADC1_SC1B ADC_SC1_REG(ADC1,1)
+#define ADC1_CFG1 ADC_CFG1_REG(ADC1)
+#define ADC1_CFG2 ADC_CFG2_REG(ADC1)
+#define ADC1_RA ADC_R_REG(ADC1,0)
+#define ADC1_RB ADC_R_REG(ADC1,1)
+#define ADC1_CV1 ADC_CV1_REG(ADC1)
+#define ADC1_CV2 ADC_CV2_REG(ADC1)
+#define ADC1_SC2 ADC_SC2_REG(ADC1)
+#define ADC1_SC3 ADC_SC3_REG(ADC1)
+#define ADC1_OFS ADC_OFS_REG(ADC1)
+#define ADC1_PG ADC_PG_REG(ADC1)
+#define ADC1_MG ADC_MG_REG(ADC1)
+#define ADC1_CLPD ADC_CLPD_REG(ADC1)
+#define ADC1_CLPS ADC_CLPS_REG(ADC1)
+#define ADC1_CLP4 ADC_CLP4_REG(ADC1)
+#define ADC1_CLP3 ADC_CLP3_REG(ADC1)
+#define ADC1_CLP2 ADC_CLP2_REG(ADC1)
+#define ADC1_CLP1 ADC_CLP1_REG(ADC1)
+#define ADC1_CLP0 ADC_CLP0_REG(ADC1)
+#define ADC1_CLMD ADC_CLMD_REG(ADC1)
+#define ADC1_CLMS ADC_CLMS_REG(ADC1)
+#define ADC1_CLM4 ADC_CLM4_REG(ADC1)
+#define ADC1_CLM3 ADC_CLM3_REG(ADC1)
+#define ADC1_CLM2 ADC_CLM2_REG(ADC1)
+#define ADC1_CLM1 ADC_CLM1_REG(ADC1)
+#define ADC1_CLM0 ADC_CLM0_REG(ADC1)
+
+/* ADC - Register array accessors */
+#define ADC0_SC1(index) ADC_SC1_REG(ADC0,index)
+#define ADC1_SC1(index) ADC_SC1_REG(ADC1,index)
+#define ADC0_R(index) ADC_R_REG(ADC0,index)
+#define ADC1_R(index) ADC_R_REG(ADC1,index)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- AIPS Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
+ * @{
+ */
+
+/** AIPS - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
+ uint8_t RESERVED_0[28];
+ __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
+ __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
+ __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
+ __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
+ uint8_t RESERVED_1[16];
+ __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
+ __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
+ __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
+ __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
+ __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
+ __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
+ __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
+ __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
+ __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
+ __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
+ __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
+ __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
+ uint8_t RESERVED_2[16];
+ __IO uint32_t PACRU; /**< Peripheral Access Control Register, offset: 0x80 */
+} AIPS_Type, *AIPS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- AIPS - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
+ * @{
+ */
+
+
+/* AIPS - Register accessors */
+#define AIPS_MPRA_REG(base) ((base)->MPRA)
+#define AIPS_PACRA_REG(base) ((base)->PACRA)
+#define AIPS_PACRB_REG(base) ((base)->PACRB)
+#define AIPS_PACRC_REG(base) ((base)->PACRC)
+#define AIPS_PACRD_REG(base) ((base)->PACRD)
+#define AIPS_PACRE_REG(base) ((base)->PACRE)
+#define AIPS_PACRF_REG(base) ((base)->PACRF)
+#define AIPS_PACRG_REG(base) ((base)->PACRG)
+#define AIPS_PACRH_REG(base) ((base)->PACRH)
+#define AIPS_PACRI_REG(base) ((base)->PACRI)
+#define AIPS_PACRJ_REG(base) ((base)->PACRJ)
+#define AIPS_PACRK_REG(base) ((base)->PACRK)
+#define AIPS_PACRL_REG(base) ((base)->PACRL)
+#define AIPS_PACRM_REG(base) ((base)->PACRM)
+#define AIPS_PACRN_REG(base) ((base)->PACRN)
+#define AIPS_PACRO_REG(base) ((base)->PACRO)
+#define AIPS_PACRP_REG(base) ((base)->PACRP)
+#define AIPS_PACRU_REG(base) ((base)->PACRU)
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- AIPS Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Masks AIPS Register Masks
+ * @{
+ */
+
+/* MPRA Bit Fields */
+#define AIPS_MPRA_MPL5_MASK 0x100u
+#define AIPS_MPRA_MPL5_SHIFT 8
+#define AIPS_MPRA_MTW5_MASK 0x200u
+#define AIPS_MPRA_MTW5_SHIFT 9
+#define AIPS_MPRA_MTR5_MASK 0x400u
+#define AIPS_MPRA_MTR5_SHIFT 10
+#define AIPS_MPRA_MPL4_MASK 0x1000u
+#define AIPS_MPRA_MPL4_SHIFT 12
+#define AIPS_MPRA_MTW4_MASK 0x2000u
+#define AIPS_MPRA_MTW4_SHIFT 13
+#define AIPS_MPRA_MTR4_MASK 0x4000u
+#define AIPS_MPRA_MTR4_SHIFT 14
+#define AIPS_MPRA_MPL3_MASK 0x10000u
+#define AIPS_MPRA_MPL3_SHIFT 16
+#define AIPS_MPRA_MTW3_MASK 0x20000u
+#define AIPS_MPRA_MTW3_SHIFT 17
+#define AIPS_MPRA_MTR3_MASK 0x40000u
+#define AIPS_MPRA_MTR3_SHIFT 18
+#define AIPS_MPRA_MPL2_MASK 0x100000u
+#define AIPS_MPRA_MPL2_SHIFT 20
+#define AIPS_MPRA_MTW2_MASK 0x200000u
+#define AIPS_MPRA_MTW2_SHIFT 21
+#define AIPS_MPRA_MTR2_MASK 0x400000u
+#define AIPS_MPRA_MTR2_SHIFT 22
+#define AIPS_MPRA_MPL1_MASK 0x1000000u
+#define AIPS_MPRA_MPL1_SHIFT 24
+#define AIPS_MPRA_MTW1_MASK 0x2000000u
+#define AIPS_MPRA_MTW1_SHIFT 25
+#define AIPS_MPRA_MTR1_MASK 0x4000000u
+#define AIPS_MPRA_MTR1_SHIFT 26
+#define AIPS_MPRA_MPL0_MASK 0x10000000u
+#define AIPS_MPRA_MPL0_SHIFT 28
+#define AIPS_MPRA_MTW0_MASK 0x20000000u
+#define AIPS_MPRA_MTW0_SHIFT 29
+#define AIPS_MPRA_MTR0_MASK 0x40000000u
+#define AIPS_MPRA_MTR0_SHIFT 30
+/* PACRA Bit Fields */
+#define AIPS_PACRA_TP7_MASK 0x1u
+#define AIPS_PACRA_TP7_SHIFT 0
+#define AIPS_PACRA_WP7_MASK 0x2u
+#define AIPS_PACRA_WP7_SHIFT 1
+#define AIPS_PACRA_SP7_MASK 0x4u
+#define AIPS_PACRA_SP7_SHIFT 2
+#define AIPS_PACRA_TP6_MASK 0x10u
+#define AIPS_PACRA_TP6_SHIFT 4
+#define AIPS_PACRA_WP6_MASK 0x20u
+#define AIPS_PACRA_WP6_SHIFT 5
+#define AIPS_PACRA_SP6_MASK 0x40u
+#define AIPS_PACRA_SP6_SHIFT 6
+#define AIPS_PACRA_TP5_MASK 0x100u
+#define AIPS_PACRA_TP5_SHIFT 8
+#define AIPS_PACRA_WP5_MASK 0x200u
+#define AIPS_PACRA_WP5_SHIFT 9
+#define AIPS_PACRA_SP5_MASK 0x400u
+#define AIPS_PACRA_SP5_SHIFT 10
+#define AIPS_PACRA_TP4_MASK 0x1000u
+#define AIPS_PACRA_TP4_SHIFT 12
+#define AIPS_PACRA_WP4_MASK 0x2000u
+#define AIPS_PACRA_WP4_SHIFT 13
+#define AIPS_PACRA_SP4_MASK 0x4000u
+#define AIPS_PACRA_SP4_SHIFT 14
+#define AIPS_PACRA_TP3_MASK 0x10000u
+#define AIPS_PACRA_TP3_SHIFT 16
+#define AIPS_PACRA_WP3_MASK 0x20000u
+#define AIPS_PACRA_WP3_SHIFT 17
+#define AIPS_PACRA_SP3_MASK 0x40000u
+#define AIPS_PACRA_SP3_SHIFT 18
+#define AIPS_PACRA_TP2_MASK 0x100000u
+#define AIPS_PACRA_TP2_SHIFT 20
+#define AIPS_PACRA_WP2_MASK 0x200000u
+#define AIPS_PACRA_WP2_SHIFT 21
+#define AIPS_PACRA_SP2_MASK 0x400000u
+#define AIPS_PACRA_SP2_SHIFT 22
+#define AIPS_PACRA_TP1_MASK 0x1000000u
+#define AIPS_PACRA_TP1_SHIFT 24
+#define AIPS_PACRA_WP1_MASK 0x2000000u
+#define AIPS_PACRA_WP1_SHIFT 25
+#define AIPS_PACRA_SP1_MASK 0x4000000u
+#define AIPS_PACRA_SP1_SHIFT 26
+#define AIPS_PACRA_TP0_MASK 0x10000000u
+#define AIPS_PACRA_TP0_SHIFT 28
+#define AIPS_PACRA_WP0_MASK 0x20000000u
+#define AIPS_PACRA_WP0_SHIFT 29
+#define AIPS_PACRA_SP0_MASK 0x40000000u
+#define AIPS_PACRA_SP0_SHIFT 30
+/* PACRB Bit Fields */
+#define AIPS_PACRB_TP7_MASK 0x1u
+#define AIPS_PACRB_TP7_SHIFT 0
+#define AIPS_PACRB_WP7_MASK 0x2u
+#define AIPS_PACRB_WP7_SHIFT 1
+#define AIPS_PACRB_SP7_MASK 0x4u
+#define AIPS_PACRB_SP7_SHIFT 2
+#define AIPS_PACRB_TP6_MASK 0x10u
+#define AIPS_PACRB_TP6_SHIFT 4
+#define AIPS_PACRB_WP6_MASK 0x20u
+#define AIPS_PACRB_WP6_SHIFT 5
+#define AIPS_PACRB_SP6_MASK 0x40u
+#define AIPS_PACRB_SP6_SHIFT 6
+#define AIPS_PACRB_TP5_MASK 0x100u
+#define AIPS_PACRB_TP5_SHIFT 8
+#define AIPS_PACRB_WP5_MASK 0x200u
+#define AIPS_PACRB_WP5_SHIFT 9
+#define AIPS_PACRB_SP5_MASK 0x400u
+#define AIPS_PACRB_SP5_SHIFT 10
+#define AIPS_PACRB_TP4_MASK 0x1000u
+#define AIPS_PACRB_TP4_SHIFT 12
+#define AIPS_PACRB_WP4_MASK 0x2000u
+#define AIPS_PACRB_WP4_SHIFT 13
+#define AIPS_PACRB_SP4_MASK 0x4000u
+#define AIPS_PACRB_SP4_SHIFT 14
+#define AIPS_PACRB_TP3_MASK 0x10000u
+#define AIPS_PACRB_TP3_SHIFT 16
+#define AIPS_PACRB_WP3_MASK 0x20000u
+#define AIPS_PACRB_WP3_SHIFT 17
+#define AIPS_PACRB_SP3_MASK 0x40000u
+#define AIPS_PACRB_SP3_SHIFT 18
+#define AIPS_PACRB_TP2_MASK 0x100000u
+#define AIPS_PACRB_TP2_SHIFT 20
+#define AIPS_PACRB_WP2_MASK 0x200000u
+#define AIPS_PACRB_WP2_SHIFT 21
+#define AIPS_PACRB_SP2_MASK 0x400000u
+#define AIPS_PACRB_SP2_SHIFT 22
+#define AIPS_PACRB_TP1_MASK 0x1000000u
+#define AIPS_PACRB_TP1_SHIFT 24
+#define AIPS_PACRB_WP1_MASK 0x2000000u
+#define AIPS_PACRB_WP1_SHIFT 25
+#define AIPS_PACRB_SP1_MASK 0x4000000u
+#define AIPS_PACRB_SP1_SHIFT 26
+#define AIPS_PACRB_TP0_MASK 0x10000000u
+#define AIPS_PACRB_TP0_SHIFT 28
+#define AIPS_PACRB_WP0_MASK 0x20000000u
+#define AIPS_PACRB_WP0_SHIFT 29
+#define AIPS_PACRB_SP0_MASK 0x40000000u
+#define AIPS_PACRB_SP0_SHIFT 30
+/* PACRC Bit Fields */
+#define AIPS_PACRC_TP7_MASK 0x1u
+#define AIPS_PACRC_TP7_SHIFT 0
+#define AIPS_PACRC_WP7_MASK 0x2u
+#define AIPS_PACRC_WP7_SHIFT 1
+#define AIPS_PACRC_SP7_MASK 0x4u
+#define AIPS_PACRC_SP7_SHIFT 2
+#define AIPS_PACRC_TP6_MASK 0x10u
+#define AIPS_PACRC_TP6_SHIFT 4
+#define AIPS_PACRC_WP6_MASK 0x20u
+#define AIPS_PACRC_WP6_SHIFT 5
+#define AIPS_PACRC_SP6_MASK 0x40u
+#define AIPS_PACRC_SP6_SHIFT 6
+#define AIPS_PACRC_TP5_MASK 0x100u
+#define AIPS_PACRC_TP5_SHIFT 8
+#define AIPS_PACRC_WP5_MASK 0x200u
+#define AIPS_PACRC_WP5_SHIFT 9
+#define AIPS_PACRC_SP5_MASK 0x400u
+#define AIPS_PACRC_SP5_SHIFT 10
+#define AIPS_PACRC_TP4_MASK 0x1000u
+#define AIPS_PACRC_TP4_SHIFT 12
+#define AIPS_PACRC_WP4_MASK 0x2000u
+#define AIPS_PACRC_WP4_SHIFT 13
+#define AIPS_PACRC_SP4_MASK 0x4000u
+#define AIPS_PACRC_SP4_SHIFT 14
+#define AIPS_PACRC_TP3_MASK 0x10000u
+#define AIPS_PACRC_TP3_SHIFT 16
+#define AIPS_PACRC_WP3_MASK 0x20000u
+#define AIPS_PACRC_WP3_SHIFT 17
+#define AIPS_PACRC_SP3_MASK 0x40000u
+#define AIPS_PACRC_SP3_SHIFT 18
+#define AIPS_PACRC_TP2_MASK 0x100000u
+#define AIPS_PACRC_TP2_SHIFT 20
+#define AIPS_PACRC_WP2_MASK 0x200000u
+#define AIPS_PACRC_WP2_SHIFT 21
+#define AIPS_PACRC_SP2_MASK 0x400000u
+#define AIPS_PACRC_SP2_SHIFT 22
+#define AIPS_PACRC_TP1_MASK 0x1000000u
+#define AIPS_PACRC_TP1_SHIFT 24
+#define AIPS_PACRC_WP1_MASK 0x2000000u
+#define AIPS_PACRC_WP1_SHIFT 25
+#define AIPS_PACRC_SP1_MASK 0x4000000u
+#define AIPS_PACRC_SP1_SHIFT 26
+#define AIPS_PACRC_TP0_MASK 0x10000000u
+#define AIPS_PACRC_TP0_SHIFT 28
+#define AIPS_PACRC_WP0_MASK 0x20000000u
+#define AIPS_PACRC_WP0_SHIFT 29
+#define AIPS_PACRC_SP0_MASK 0x40000000u
+#define AIPS_PACRC_SP0_SHIFT 30
+/* PACRD Bit Fields */
+#define AIPS_PACRD_TP7_MASK 0x1u
+#define AIPS_PACRD_TP7_SHIFT 0
+#define AIPS_PACRD_WP7_MASK 0x2u
+#define AIPS_PACRD_WP7_SHIFT 1
+#define AIPS_PACRD_SP7_MASK 0x4u
+#define AIPS_PACRD_SP7_SHIFT 2
+#define AIPS_PACRD_TP6_MASK 0x10u
+#define AIPS_PACRD_TP6_SHIFT 4
+#define AIPS_PACRD_WP6_MASK 0x20u
+#define AIPS_PACRD_WP6_SHIFT 5
+#define AIPS_PACRD_SP6_MASK 0x40u
+#define AIPS_PACRD_SP6_SHIFT 6
+#define AIPS_PACRD_TP5_MASK 0x100u
+#define AIPS_PACRD_TP5_SHIFT 8
+#define AIPS_PACRD_WP5_MASK 0x200u
+#define AIPS_PACRD_WP5_SHIFT 9
+#define AIPS_PACRD_SP5_MASK 0x400u
+#define AIPS_PACRD_SP5_SHIFT 10
+#define AIPS_PACRD_TP4_MASK 0x1000u
+#define AIPS_PACRD_TP4_SHIFT 12
+#define AIPS_PACRD_WP4_MASK 0x2000u
+#define AIPS_PACRD_WP4_SHIFT 13
+#define AIPS_PACRD_SP4_MASK 0x4000u
+#define AIPS_PACRD_SP4_SHIFT 14
+#define AIPS_PACRD_TP3_MASK 0x10000u
+#define AIPS_PACRD_TP3_SHIFT 16
+#define AIPS_PACRD_WP3_MASK 0x20000u
+#define AIPS_PACRD_WP3_SHIFT 17
+#define AIPS_PACRD_SP3_MASK 0x40000u
+#define AIPS_PACRD_SP3_SHIFT 18
+#define AIPS_PACRD_TP2_MASK 0x100000u
+#define AIPS_PACRD_TP2_SHIFT 20
+#define AIPS_PACRD_WP2_MASK 0x200000u
+#define AIPS_PACRD_WP2_SHIFT 21
+#define AIPS_PACRD_SP2_MASK 0x400000u
+#define AIPS_PACRD_SP2_SHIFT 22
+#define AIPS_PACRD_TP1_MASK 0x1000000u
+#define AIPS_PACRD_TP1_SHIFT 24
+#define AIPS_PACRD_WP1_MASK 0x2000000u
+#define AIPS_PACRD_WP1_SHIFT 25
+#define AIPS_PACRD_SP1_MASK 0x4000000u
+#define AIPS_PACRD_SP1_SHIFT 26
+#define AIPS_PACRD_TP0_MASK 0x10000000u
+#define AIPS_PACRD_TP0_SHIFT 28
+#define AIPS_PACRD_WP0_MASK 0x20000000u
+#define AIPS_PACRD_WP0_SHIFT 29
+#define AIPS_PACRD_SP0_MASK 0x40000000u
+#define AIPS_PACRD_SP0_SHIFT 30
+/* PACRE Bit Fields */
+#define AIPS_PACRE_TP7_MASK 0x1u
+#define AIPS_PACRE_TP7_SHIFT 0
+#define AIPS_PACRE_WP7_MASK 0x2u
+#define AIPS_PACRE_WP7_SHIFT 1
+#define AIPS_PACRE_SP7_MASK 0x4u
+#define AIPS_PACRE_SP7_SHIFT 2
+#define AIPS_PACRE_TP6_MASK 0x10u
+#define AIPS_PACRE_TP6_SHIFT 4
+#define AIPS_PACRE_WP6_MASK 0x20u
+#define AIPS_PACRE_WP6_SHIFT 5
+#define AIPS_PACRE_SP6_MASK 0x40u
+#define AIPS_PACRE_SP6_SHIFT 6
+#define AIPS_PACRE_TP5_MASK 0x100u
+#define AIPS_PACRE_TP5_SHIFT 8
+#define AIPS_PACRE_WP5_MASK 0x200u
+#define AIPS_PACRE_WP5_SHIFT 9
+#define AIPS_PACRE_SP5_MASK 0x400u
+#define AIPS_PACRE_SP5_SHIFT 10
+#define AIPS_PACRE_TP4_MASK 0x1000u
+#define AIPS_PACRE_TP4_SHIFT 12
+#define AIPS_PACRE_WP4_MASK 0x2000u
+#define AIPS_PACRE_WP4_SHIFT 13
+#define AIPS_PACRE_SP4_MASK 0x4000u
+#define AIPS_PACRE_SP4_SHIFT 14
+#define AIPS_PACRE_TP3_MASK 0x10000u
+#define AIPS_PACRE_TP3_SHIFT 16
+#define AIPS_PACRE_WP3_MASK 0x20000u
+#define AIPS_PACRE_WP3_SHIFT 17
+#define AIPS_PACRE_SP3_MASK 0x40000u
+#define AIPS_PACRE_SP3_SHIFT 18
+#define AIPS_PACRE_TP2_MASK 0x100000u
+#define AIPS_PACRE_TP2_SHIFT 20
+#define AIPS_PACRE_WP2_MASK 0x200000u
+#define AIPS_PACRE_WP2_SHIFT 21
+#define AIPS_PACRE_SP2_MASK 0x400000u
+#define AIPS_PACRE_SP2_SHIFT 22
+#define AIPS_PACRE_TP1_MASK 0x1000000u
+#define AIPS_PACRE_TP1_SHIFT 24
+#define AIPS_PACRE_WP1_MASK 0x2000000u
+#define AIPS_PACRE_WP1_SHIFT 25
+#define AIPS_PACRE_SP1_MASK 0x4000000u
+#define AIPS_PACRE_SP1_SHIFT 26
+#define AIPS_PACRE_TP0_MASK 0x10000000u
+#define AIPS_PACRE_TP0_SHIFT 28
+#define AIPS_PACRE_WP0_MASK 0x20000000u
+#define AIPS_PACRE_WP0_SHIFT 29
+#define AIPS_PACRE_SP0_MASK 0x40000000u
+#define AIPS_PACRE_SP0_SHIFT 30
+/* PACRF Bit Fields */
+#define AIPS_PACRF_TP7_MASK 0x1u
+#define AIPS_PACRF_TP7_SHIFT 0
+#define AIPS_PACRF_WP7_MASK 0x2u
+#define AIPS_PACRF_WP7_SHIFT 1
+#define AIPS_PACRF_SP7_MASK 0x4u
+#define AIPS_PACRF_SP7_SHIFT 2
+#define AIPS_PACRF_TP6_MASK 0x10u
+#define AIPS_PACRF_TP6_SHIFT 4
+#define AIPS_PACRF_WP6_MASK 0x20u
+#define AIPS_PACRF_WP6_SHIFT 5
+#define AIPS_PACRF_SP6_MASK 0x40u
+#define AIPS_PACRF_SP6_SHIFT 6
+#define AIPS_PACRF_TP5_MASK 0x100u
+#define AIPS_PACRF_TP5_SHIFT 8
+#define AIPS_PACRF_WP5_MASK 0x200u
+#define AIPS_PACRF_WP5_SHIFT 9
+#define AIPS_PACRF_SP5_MASK 0x400u
+#define AIPS_PACRF_SP5_SHIFT 10
+#define AIPS_PACRF_TP4_MASK 0x1000u
+#define AIPS_PACRF_TP4_SHIFT 12
+#define AIPS_PACRF_WP4_MASK 0x2000u
+#define AIPS_PACRF_WP4_SHIFT 13
+#define AIPS_PACRF_SP4_MASK 0x4000u
+#define AIPS_PACRF_SP4_SHIFT 14
+#define AIPS_PACRF_TP3_MASK 0x10000u
+#define AIPS_PACRF_TP3_SHIFT 16
+#define AIPS_PACRF_WP3_MASK 0x20000u
+#define AIPS_PACRF_WP3_SHIFT 17
+#define AIPS_PACRF_SP3_MASK 0x40000u
+#define AIPS_PACRF_SP3_SHIFT 18
+#define AIPS_PACRF_TP2_MASK 0x100000u
+#define AIPS_PACRF_TP2_SHIFT 20
+#define AIPS_PACRF_WP2_MASK 0x200000u
+#define AIPS_PACRF_WP2_SHIFT 21
+#define AIPS_PACRF_SP2_MASK 0x400000u
+#define AIPS_PACRF_SP2_SHIFT 22
+#define AIPS_PACRF_TP1_MASK 0x1000000u
+#define AIPS_PACRF_TP1_SHIFT 24
+#define AIPS_PACRF_WP1_MASK 0x2000000u
+#define AIPS_PACRF_WP1_SHIFT 25
+#define AIPS_PACRF_SP1_MASK 0x4000000u
+#define AIPS_PACRF_SP1_SHIFT 26
+#define AIPS_PACRF_TP0_MASK 0x10000000u
+#define AIPS_PACRF_TP0_SHIFT 28
+#define AIPS_PACRF_WP0_MASK 0x20000000u
+#define AIPS_PACRF_WP0_SHIFT 29
+#define AIPS_PACRF_SP0_MASK 0x40000000u
+#define AIPS_PACRF_SP0_SHIFT 30
+/* PACRG Bit Fields */
+#define AIPS_PACRG_TP7_MASK 0x1u
+#define AIPS_PACRG_TP7_SHIFT 0
+#define AIPS_PACRG_WP7_MASK 0x2u
+#define AIPS_PACRG_WP7_SHIFT 1
+#define AIPS_PACRG_SP7_MASK 0x4u
+#define AIPS_PACRG_SP7_SHIFT 2
+#define AIPS_PACRG_TP6_MASK 0x10u
+#define AIPS_PACRG_TP6_SHIFT 4
+#define AIPS_PACRG_WP6_MASK 0x20u
+#define AIPS_PACRG_WP6_SHIFT 5
+#define AIPS_PACRG_SP6_MASK 0x40u
+#define AIPS_PACRG_SP6_SHIFT 6
+#define AIPS_PACRG_TP5_MASK 0x100u
+#define AIPS_PACRG_TP5_SHIFT 8
+#define AIPS_PACRG_WP5_MASK 0x200u
+#define AIPS_PACRG_WP5_SHIFT 9
+#define AIPS_PACRG_SP5_MASK 0x400u
+#define AIPS_PACRG_SP5_SHIFT 10
+#define AIPS_PACRG_TP4_MASK 0x1000u
+#define AIPS_PACRG_TP4_SHIFT 12
+#define AIPS_PACRG_WP4_MASK 0x2000u
+#define AIPS_PACRG_WP4_SHIFT 13
+#define AIPS_PACRG_SP4_MASK 0x4000u
+#define AIPS_PACRG_SP4_SHIFT 14
+#define AIPS_PACRG_TP3_MASK 0x10000u
+#define AIPS_PACRG_TP3_SHIFT 16
+#define AIPS_PACRG_WP3_MASK 0x20000u
+#define AIPS_PACRG_WP3_SHIFT 17
+#define AIPS_PACRG_SP3_MASK 0x40000u
+#define AIPS_PACRG_SP3_SHIFT 18
+#define AIPS_PACRG_TP2_MASK 0x100000u
+#define AIPS_PACRG_TP2_SHIFT 20
+#define AIPS_PACRG_WP2_MASK 0x200000u
+#define AIPS_PACRG_WP2_SHIFT 21
+#define AIPS_PACRG_SP2_MASK 0x400000u
+#define AIPS_PACRG_SP2_SHIFT 22
+#define AIPS_PACRG_TP1_MASK 0x1000000u
+#define AIPS_PACRG_TP1_SHIFT 24
+#define AIPS_PACRG_WP1_MASK 0x2000000u
+#define AIPS_PACRG_WP1_SHIFT 25
+#define AIPS_PACRG_SP1_MASK 0x4000000u
+#define AIPS_PACRG_SP1_SHIFT 26
+#define AIPS_PACRG_TP0_MASK 0x10000000u
+#define AIPS_PACRG_TP0_SHIFT 28
+#define AIPS_PACRG_WP0_MASK 0x20000000u
+#define AIPS_PACRG_WP0_SHIFT 29
+#define AIPS_PACRG_SP0_MASK 0x40000000u
+#define AIPS_PACRG_SP0_SHIFT 30
+/* PACRH Bit Fields */
+#define AIPS_PACRH_TP7_MASK 0x1u
+#define AIPS_PACRH_TP7_SHIFT 0
+#define AIPS_PACRH_WP7_MASK 0x2u
+#define AIPS_PACRH_WP7_SHIFT 1
+#define AIPS_PACRH_SP7_MASK 0x4u
+#define AIPS_PACRH_SP7_SHIFT 2
+#define AIPS_PACRH_TP6_MASK 0x10u
+#define AIPS_PACRH_TP6_SHIFT 4
+#define AIPS_PACRH_WP6_MASK 0x20u
+#define AIPS_PACRH_WP6_SHIFT 5
+#define AIPS_PACRH_SP6_MASK 0x40u
+#define AIPS_PACRH_SP6_SHIFT 6
+#define AIPS_PACRH_TP5_MASK 0x100u
+#define AIPS_PACRH_TP5_SHIFT 8
+#define AIPS_PACRH_WP5_MASK 0x200u
+#define AIPS_PACRH_WP5_SHIFT 9
+#define AIPS_PACRH_SP5_MASK 0x400u
+#define AIPS_PACRH_SP5_SHIFT 10
+#define AIPS_PACRH_TP4_MASK 0x1000u
+#define AIPS_PACRH_TP4_SHIFT 12
+#define AIPS_PACRH_WP4_MASK 0x2000u
+#define AIPS_PACRH_WP4_SHIFT 13
+#define AIPS_PACRH_SP4_MASK 0x4000u
+#define AIPS_PACRH_SP4_SHIFT 14
+#define AIPS_PACRH_TP3_MASK 0x10000u
+#define AIPS_PACRH_TP3_SHIFT 16
+#define AIPS_PACRH_WP3_MASK 0x20000u
+#define AIPS_PACRH_WP3_SHIFT 17
+#define AIPS_PACRH_SP3_MASK 0x40000u
+#define AIPS_PACRH_SP3_SHIFT 18
+#define AIPS_PACRH_TP2_MASK 0x100000u
+#define AIPS_PACRH_TP2_SHIFT 20
+#define AIPS_PACRH_WP2_MASK 0x200000u
+#define AIPS_PACRH_WP2_SHIFT 21
+#define AIPS_PACRH_SP2_MASK 0x400000u
+#define AIPS_PACRH_SP2_SHIFT 22
+#define AIPS_PACRH_TP1_MASK 0x1000000u
+#define AIPS_PACRH_TP1_SHIFT 24
+#define AIPS_PACRH_WP1_MASK 0x2000000u
+#define AIPS_PACRH_WP1_SHIFT 25
+#define AIPS_PACRH_SP1_MASK 0x4000000u
+#define AIPS_PACRH_SP1_SHIFT 26
+#define AIPS_PACRH_TP0_MASK 0x10000000u
+#define AIPS_PACRH_TP0_SHIFT 28
+#define AIPS_PACRH_WP0_MASK 0x20000000u
+#define AIPS_PACRH_WP0_SHIFT 29
+#define AIPS_PACRH_SP0_MASK 0x40000000u
+#define AIPS_PACRH_SP0_SHIFT 30
+/* PACRI Bit Fields */
+#define AIPS_PACRI_TP7_MASK 0x1u
+#define AIPS_PACRI_TP7_SHIFT 0
+#define AIPS_PACRI_WP7_MASK 0x2u
+#define AIPS_PACRI_WP7_SHIFT 1
+#define AIPS_PACRI_SP7_MASK 0x4u
+#define AIPS_PACRI_SP7_SHIFT 2
+#define AIPS_PACRI_TP6_MASK 0x10u
+#define AIPS_PACRI_TP6_SHIFT 4
+#define AIPS_PACRI_WP6_MASK 0x20u
+#define AIPS_PACRI_WP6_SHIFT 5
+#define AIPS_PACRI_SP6_MASK 0x40u
+#define AIPS_PACRI_SP6_SHIFT 6
+#define AIPS_PACRI_TP5_MASK 0x100u
+#define AIPS_PACRI_TP5_SHIFT 8
+#define AIPS_PACRI_WP5_MASK 0x200u
+#define AIPS_PACRI_WP5_SHIFT 9
+#define AIPS_PACRI_SP5_MASK 0x400u
+#define AIPS_PACRI_SP5_SHIFT 10
+#define AIPS_PACRI_TP4_MASK 0x1000u
+#define AIPS_PACRI_TP4_SHIFT 12
+#define AIPS_PACRI_WP4_MASK 0x2000u
+#define AIPS_PACRI_WP4_SHIFT 13
+#define AIPS_PACRI_SP4_MASK 0x4000u
+#define AIPS_PACRI_SP4_SHIFT 14
+#define AIPS_PACRI_TP3_MASK 0x10000u
+#define AIPS_PACRI_TP3_SHIFT 16
+#define AIPS_PACRI_WP3_MASK 0x20000u
+#define AIPS_PACRI_WP3_SHIFT 17
+#define AIPS_PACRI_SP3_MASK 0x40000u
+#define AIPS_PACRI_SP3_SHIFT 18
+#define AIPS_PACRI_TP2_MASK 0x100000u
+#define AIPS_PACRI_TP2_SHIFT 20
+#define AIPS_PACRI_WP2_MASK 0x200000u
+#define AIPS_PACRI_WP2_SHIFT 21
+#define AIPS_PACRI_SP2_MASK 0x400000u
+#define AIPS_PACRI_SP2_SHIFT 22
+#define AIPS_PACRI_TP1_MASK 0x1000000u
+#define AIPS_PACRI_TP1_SHIFT 24
+#define AIPS_PACRI_WP1_MASK 0x2000000u
+#define AIPS_PACRI_WP1_SHIFT 25
+#define AIPS_PACRI_SP1_MASK 0x4000000u
+#define AIPS_PACRI_SP1_SHIFT 26
+#define AIPS_PACRI_TP0_MASK 0x10000000u
+#define AIPS_PACRI_TP0_SHIFT 28
+#define AIPS_PACRI_WP0_MASK 0x20000000u
+#define AIPS_PACRI_WP0_SHIFT 29
+#define AIPS_PACRI_SP0_MASK 0x40000000u
+#define AIPS_PACRI_SP0_SHIFT 30
+/* PACRJ Bit Fields */
+#define AIPS_PACRJ_TP7_MASK 0x1u
+#define AIPS_PACRJ_TP7_SHIFT 0
+#define AIPS_PACRJ_WP7_MASK 0x2u
+#define AIPS_PACRJ_WP7_SHIFT 1
+#define AIPS_PACRJ_SP7_MASK 0x4u
+#define AIPS_PACRJ_SP7_SHIFT 2
+#define AIPS_PACRJ_TP6_MASK 0x10u
+#define AIPS_PACRJ_TP6_SHIFT 4
+#define AIPS_PACRJ_WP6_MASK 0x20u
+#define AIPS_PACRJ_WP6_SHIFT 5
+#define AIPS_PACRJ_SP6_MASK 0x40u
+#define AIPS_PACRJ_SP6_SHIFT 6
+#define AIPS_PACRJ_TP5_MASK 0x100u
+#define AIPS_PACRJ_TP5_SHIFT 8
+#define AIPS_PACRJ_WP5_MASK 0x200u
+#define AIPS_PACRJ_WP5_SHIFT 9
+#define AIPS_PACRJ_SP5_MASK 0x400u
+#define AIPS_PACRJ_SP5_SHIFT 10
+#define AIPS_PACRJ_TP4_MASK 0x1000u
+#define AIPS_PACRJ_TP4_SHIFT 12
+#define AIPS_PACRJ_WP4_MASK 0x2000u
+#define AIPS_PACRJ_WP4_SHIFT 13
+#define AIPS_PACRJ_SP4_MASK 0x4000u
+#define AIPS_PACRJ_SP4_SHIFT 14
+#define AIPS_PACRJ_TP3_MASK 0x10000u
+#define AIPS_PACRJ_TP3_SHIFT 16
+#define AIPS_PACRJ_WP3_MASK 0x20000u
+#define AIPS_PACRJ_WP3_SHIFT 17
+#define AIPS_PACRJ_SP3_MASK 0x40000u
+#define AIPS_PACRJ_SP3_SHIFT 18
+#define AIPS_PACRJ_TP2_MASK 0x100000u
+#define AIPS_PACRJ_TP2_SHIFT 20
+#define AIPS_PACRJ_WP2_MASK 0x200000u
+#define AIPS_PACRJ_WP2_SHIFT 21
+#define AIPS_PACRJ_SP2_MASK 0x400000u
+#define AIPS_PACRJ_SP2_SHIFT 22
+#define AIPS_PACRJ_TP1_MASK 0x1000000u
+#define AIPS_PACRJ_TP1_SHIFT 24
+#define AIPS_PACRJ_WP1_MASK 0x2000000u
+#define AIPS_PACRJ_WP1_SHIFT 25
+#define AIPS_PACRJ_SP1_MASK 0x4000000u
+#define AIPS_PACRJ_SP1_SHIFT 26
+#define AIPS_PACRJ_TP0_MASK 0x10000000u
+#define AIPS_PACRJ_TP0_SHIFT 28
+#define AIPS_PACRJ_WP0_MASK 0x20000000u
+#define AIPS_PACRJ_WP0_SHIFT 29
+#define AIPS_PACRJ_SP0_MASK 0x40000000u
+#define AIPS_PACRJ_SP0_SHIFT 30
+/* PACRK Bit Fields */
+#define AIPS_PACRK_TP7_MASK 0x1u
+#define AIPS_PACRK_TP7_SHIFT 0
+#define AIPS_PACRK_WP7_MASK 0x2u
+#define AIPS_PACRK_WP7_SHIFT 1
+#define AIPS_PACRK_SP7_MASK 0x4u
+#define AIPS_PACRK_SP7_SHIFT 2
+#define AIPS_PACRK_TP6_MASK 0x10u
+#define AIPS_PACRK_TP6_SHIFT 4
+#define AIPS_PACRK_WP6_MASK 0x20u
+#define AIPS_PACRK_WP6_SHIFT 5
+#define AIPS_PACRK_SP6_MASK 0x40u
+#define AIPS_PACRK_SP6_SHIFT 6
+#define AIPS_PACRK_TP5_MASK 0x100u
+#define AIPS_PACRK_TP5_SHIFT 8
+#define AIPS_PACRK_WP5_MASK 0x200u
+#define AIPS_PACRK_WP5_SHIFT 9
+#define AIPS_PACRK_SP5_MASK 0x400u
+#define AIPS_PACRK_SP5_SHIFT 10
+#define AIPS_PACRK_TP4_MASK 0x1000u
+#define AIPS_PACRK_TP4_SHIFT 12
+#define AIPS_PACRK_WP4_MASK 0x2000u
+#define AIPS_PACRK_WP4_SHIFT 13
+#define AIPS_PACRK_SP4_MASK 0x4000u
+#define AIPS_PACRK_SP4_SHIFT 14
+#define AIPS_PACRK_TP3_MASK 0x10000u
+#define AIPS_PACRK_TP3_SHIFT 16
+#define AIPS_PACRK_WP3_MASK 0x20000u
+#define AIPS_PACRK_WP3_SHIFT 17
+#define AIPS_PACRK_SP3_MASK 0x40000u
+#define AIPS_PACRK_SP3_SHIFT 18
+#define AIPS_PACRK_TP2_MASK 0x100000u
+#define AIPS_PACRK_TP2_SHIFT 20
+#define AIPS_PACRK_WP2_MASK 0x200000u
+#define AIPS_PACRK_WP2_SHIFT 21
+#define AIPS_PACRK_SP2_MASK 0x400000u
+#define AIPS_PACRK_SP2_SHIFT 22
+#define AIPS_PACRK_TP1_MASK 0x1000000u
+#define AIPS_PACRK_TP1_SHIFT 24
+#define AIPS_PACRK_WP1_MASK 0x2000000u
+#define AIPS_PACRK_WP1_SHIFT 25
+#define AIPS_PACRK_SP1_MASK 0x4000000u
+#define AIPS_PACRK_SP1_SHIFT 26
+#define AIPS_PACRK_TP0_MASK 0x10000000u
+#define AIPS_PACRK_TP0_SHIFT 28
+#define AIPS_PACRK_WP0_MASK 0x20000000u
+#define AIPS_PACRK_WP0_SHIFT 29
+#define AIPS_PACRK_SP0_MASK 0x40000000u
+#define AIPS_PACRK_SP0_SHIFT 30
+/* PACRL Bit Fields */
+#define AIPS_PACRL_TP7_MASK 0x1u
+#define AIPS_PACRL_TP7_SHIFT 0
+#define AIPS_PACRL_WP7_MASK 0x2u
+#define AIPS_PACRL_WP7_SHIFT 1
+#define AIPS_PACRL_SP7_MASK 0x4u
+#define AIPS_PACRL_SP7_SHIFT 2
+#define AIPS_PACRL_TP6_MASK 0x10u
+#define AIPS_PACRL_TP6_SHIFT 4
+#define AIPS_PACRL_WP6_MASK 0x20u
+#define AIPS_PACRL_WP6_SHIFT 5
+#define AIPS_PACRL_SP6_MASK 0x40u
+#define AIPS_PACRL_SP6_SHIFT 6
+#define AIPS_PACRL_TP5_MASK 0x100u
+#define AIPS_PACRL_TP5_SHIFT 8
+#define AIPS_PACRL_WP5_MASK 0x200u
+#define AIPS_PACRL_WP5_SHIFT 9
+#define AIPS_PACRL_SP5_MASK 0x400u
+#define AIPS_PACRL_SP5_SHIFT 10
+#define AIPS_PACRL_TP4_MASK 0x1000u
+#define AIPS_PACRL_TP4_SHIFT 12
+#define AIPS_PACRL_WP4_MASK 0x2000u
+#define AIPS_PACRL_WP4_SHIFT 13
+#define AIPS_PACRL_SP4_MASK 0x4000u
+#define AIPS_PACRL_SP4_SHIFT 14
+#define AIPS_PACRL_TP3_MASK 0x10000u
+#define AIPS_PACRL_TP3_SHIFT 16
+#define AIPS_PACRL_WP3_MASK 0x20000u
+#define AIPS_PACRL_WP3_SHIFT 17
+#define AIPS_PACRL_SP3_MASK 0x40000u
+#define AIPS_PACRL_SP3_SHIFT 18
+#define AIPS_PACRL_TP2_MASK 0x100000u
+#define AIPS_PACRL_TP2_SHIFT 20
+#define AIPS_PACRL_WP2_MASK 0x200000u
+#define AIPS_PACRL_WP2_SHIFT 21
+#define AIPS_PACRL_SP2_MASK 0x400000u
+#define AIPS_PACRL_SP2_SHIFT 22
+#define AIPS_PACRL_TP1_MASK 0x1000000u
+#define AIPS_PACRL_TP1_SHIFT 24
+#define AIPS_PACRL_WP1_MASK 0x2000000u
+#define AIPS_PACRL_WP1_SHIFT 25
+#define AIPS_PACRL_SP1_MASK 0x4000000u
+#define AIPS_PACRL_SP1_SHIFT 26
+#define AIPS_PACRL_TP0_MASK 0x10000000u
+#define AIPS_PACRL_TP0_SHIFT 28
+#define AIPS_PACRL_WP0_MASK 0x20000000u
+#define AIPS_PACRL_WP0_SHIFT 29
+#define AIPS_PACRL_SP0_MASK 0x40000000u
+#define AIPS_PACRL_SP0_SHIFT 30
+/* PACRM Bit Fields */
+#define AIPS_PACRM_TP7_MASK 0x1u
+#define AIPS_PACRM_TP7_SHIFT 0
+#define AIPS_PACRM_WP7_MASK 0x2u
+#define AIPS_PACRM_WP7_SHIFT 1
+#define AIPS_PACRM_SP7_MASK 0x4u
+#define AIPS_PACRM_SP7_SHIFT 2
+#define AIPS_PACRM_TP6_MASK 0x10u
+#define AIPS_PACRM_TP6_SHIFT 4
+#define AIPS_PACRM_WP6_MASK 0x20u
+#define AIPS_PACRM_WP6_SHIFT 5
+#define AIPS_PACRM_SP6_MASK 0x40u
+#define AIPS_PACRM_SP6_SHIFT 6
+#define AIPS_PACRM_TP5_MASK 0x100u
+#define AIPS_PACRM_TP5_SHIFT 8
+#define AIPS_PACRM_WP5_MASK 0x200u
+#define AIPS_PACRM_WP5_SHIFT 9
+#define AIPS_PACRM_SP5_MASK 0x400u
+#define AIPS_PACRM_SP5_SHIFT 10
+#define AIPS_PACRM_TP4_MASK 0x1000u
+#define AIPS_PACRM_TP4_SHIFT 12
+#define AIPS_PACRM_WP4_MASK 0x2000u
+#define AIPS_PACRM_WP4_SHIFT 13
+#define AIPS_PACRM_SP4_MASK 0x4000u
+#define AIPS_PACRM_SP4_SHIFT 14
+#define AIPS_PACRM_TP3_MASK 0x10000u
+#define AIPS_PACRM_TP3_SHIFT 16
+#define AIPS_PACRM_WP3_MASK 0x20000u
+#define AIPS_PACRM_WP3_SHIFT 17
+#define AIPS_PACRM_SP3_MASK 0x40000u
+#define AIPS_PACRM_SP3_SHIFT 18
+#define AIPS_PACRM_TP2_MASK 0x100000u
+#define AIPS_PACRM_TP2_SHIFT 20
+#define AIPS_PACRM_WP2_MASK 0x200000u
+#define AIPS_PACRM_WP2_SHIFT 21
+#define AIPS_PACRM_SP2_MASK 0x400000u
+#define AIPS_PACRM_SP2_SHIFT 22
+#define AIPS_PACRM_TP1_MASK 0x1000000u
+#define AIPS_PACRM_TP1_SHIFT 24
+#define AIPS_PACRM_WP1_MASK 0x2000000u
+#define AIPS_PACRM_WP1_SHIFT 25
+#define AIPS_PACRM_SP1_MASK 0x4000000u
+#define AIPS_PACRM_SP1_SHIFT 26
+#define AIPS_PACRM_TP0_MASK 0x10000000u
+#define AIPS_PACRM_TP0_SHIFT 28
+#define AIPS_PACRM_WP0_MASK 0x20000000u
+#define AIPS_PACRM_WP0_SHIFT 29
+#define AIPS_PACRM_SP0_MASK 0x40000000u
+#define AIPS_PACRM_SP0_SHIFT 30
+/* PACRN Bit Fields */
+#define AIPS_PACRN_TP7_MASK 0x1u
+#define AIPS_PACRN_TP7_SHIFT 0
+#define AIPS_PACRN_WP7_MASK 0x2u
+#define AIPS_PACRN_WP7_SHIFT 1
+#define AIPS_PACRN_SP7_MASK 0x4u
+#define AIPS_PACRN_SP7_SHIFT 2
+#define AIPS_PACRN_TP6_MASK 0x10u
+#define AIPS_PACRN_TP6_SHIFT 4
+#define AIPS_PACRN_WP6_MASK 0x20u
+#define AIPS_PACRN_WP6_SHIFT 5
+#define AIPS_PACRN_SP6_MASK 0x40u
+#define AIPS_PACRN_SP6_SHIFT 6
+#define AIPS_PACRN_TP5_MASK 0x100u
+#define AIPS_PACRN_TP5_SHIFT 8
+#define AIPS_PACRN_WP5_MASK 0x200u
+#define AIPS_PACRN_WP5_SHIFT 9
+#define AIPS_PACRN_SP5_MASK 0x400u
+#define AIPS_PACRN_SP5_SHIFT 10
+#define AIPS_PACRN_TP4_MASK 0x1000u
+#define AIPS_PACRN_TP4_SHIFT 12
+#define AIPS_PACRN_WP4_MASK 0x2000u
+#define AIPS_PACRN_WP4_SHIFT 13
+#define AIPS_PACRN_SP4_MASK 0x4000u
+#define AIPS_PACRN_SP4_SHIFT 14
+#define AIPS_PACRN_TP3_MASK 0x10000u
+#define AIPS_PACRN_TP3_SHIFT 16
+#define AIPS_PACRN_WP3_MASK 0x20000u
+#define AIPS_PACRN_WP3_SHIFT 17
+#define AIPS_PACRN_SP3_MASK 0x40000u
+#define AIPS_PACRN_SP3_SHIFT 18
+#define AIPS_PACRN_TP2_MASK 0x100000u
+#define AIPS_PACRN_TP2_SHIFT 20
+#define AIPS_PACRN_WP2_MASK 0x200000u
+#define AIPS_PACRN_WP2_SHIFT 21
+#define AIPS_PACRN_SP2_MASK 0x400000u
+#define AIPS_PACRN_SP2_SHIFT 22
+#define AIPS_PACRN_TP1_MASK 0x1000000u
+#define AIPS_PACRN_TP1_SHIFT 24
+#define AIPS_PACRN_WP1_MASK 0x2000000u
+#define AIPS_PACRN_WP1_SHIFT 25
+#define AIPS_PACRN_SP1_MASK 0x4000000u
+#define AIPS_PACRN_SP1_SHIFT 26
+#define AIPS_PACRN_TP0_MASK 0x10000000u
+#define AIPS_PACRN_TP0_SHIFT 28
+#define AIPS_PACRN_WP0_MASK 0x20000000u
+#define AIPS_PACRN_WP0_SHIFT 29
+#define AIPS_PACRN_SP0_MASK 0x40000000u
+#define AIPS_PACRN_SP0_SHIFT 30
+/* PACRO Bit Fields */
+#define AIPS_PACRO_TP7_MASK 0x1u
+#define AIPS_PACRO_TP7_SHIFT 0
+#define AIPS_PACRO_WP7_MASK 0x2u
+#define AIPS_PACRO_WP7_SHIFT 1
+#define AIPS_PACRO_SP7_MASK 0x4u
+#define AIPS_PACRO_SP7_SHIFT 2
+#define AIPS_PACRO_TP6_MASK 0x10u
+#define AIPS_PACRO_TP6_SHIFT 4
+#define AIPS_PACRO_WP6_MASK 0x20u
+#define AIPS_PACRO_WP6_SHIFT 5
+#define AIPS_PACRO_SP6_MASK 0x40u
+#define AIPS_PACRO_SP6_SHIFT 6
+#define AIPS_PACRO_TP5_MASK 0x100u
+#define AIPS_PACRO_TP5_SHIFT 8
+#define AIPS_PACRO_WP5_MASK 0x200u
+#define AIPS_PACRO_WP5_SHIFT 9
+#define AIPS_PACRO_SP5_MASK 0x400u
+#define AIPS_PACRO_SP5_SHIFT 10
+#define AIPS_PACRO_TP4_MASK 0x1000u
+#define AIPS_PACRO_TP4_SHIFT 12
+#define AIPS_PACRO_WP4_MASK 0x2000u
+#define AIPS_PACRO_WP4_SHIFT 13
+#define AIPS_PACRO_SP4_MASK 0x4000u
+#define AIPS_PACRO_SP4_SHIFT 14
+#define AIPS_PACRO_TP3_MASK 0x10000u
+#define AIPS_PACRO_TP3_SHIFT 16
+#define AIPS_PACRO_WP3_MASK 0x20000u
+#define AIPS_PACRO_WP3_SHIFT 17
+#define AIPS_PACRO_SP3_MASK 0x40000u
+#define AIPS_PACRO_SP3_SHIFT 18
+#define AIPS_PACRO_TP2_MASK 0x100000u
+#define AIPS_PACRO_TP2_SHIFT 20
+#define AIPS_PACRO_WP2_MASK 0x200000u
+#define AIPS_PACRO_WP2_SHIFT 21
+#define AIPS_PACRO_SP2_MASK 0x400000u
+#define AIPS_PACRO_SP2_SHIFT 22
+#define AIPS_PACRO_TP1_MASK 0x1000000u
+#define AIPS_PACRO_TP1_SHIFT 24
+#define AIPS_PACRO_WP1_MASK 0x2000000u
+#define AIPS_PACRO_WP1_SHIFT 25
+#define AIPS_PACRO_SP1_MASK 0x4000000u
+#define AIPS_PACRO_SP1_SHIFT 26
+#define AIPS_PACRO_TP0_MASK 0x10000000u
+#define AIPS_PACRO_TP0_SHIFT 28
+#define AIPS_PACRO_WP0_MASK 0x20000000u
+#define AIPS_PACRO_WP0_SHIFT 29
+#define AIPS_PACRO_SP0_MASK 0x40000000u
+#define AIPS_PACRO_SP0_SHIFT 30
+/* PACRP Bit Fields */
+#define AIPS_PACRP_TP7_MASK 0x1u
+#define AIPS_PACRP_TP7_SHIFT 0
+#define AIPS_PACRP_WP7_MASK 0x2u
+#define AIPS_PACRP_WP7_SHIFT 1
+#define AIPS_PACRP_SP7_MASK 0x4u
+#define AIPS_PACRP_SP7_SHIFT 2
+#define AIPS_PACRP_TP6_MASK 0x10u
+#define AIPS_PACRP_TP6_SHIFT 4
+#define AIPS_PACRP_WP6_MASK 0x20u
+#define AIPS_PACRP_WP6_SHIFT 5
+#define AIPS_PACRP_SP6_MASK 0x40u
+#define AIPS_PACRP_SP6_SHIFT 6
+#define AIPS_PACRP_TP5_MASK 0x100u
+#define AIPS_PACRP_TP5_SHIFT 8
+#define AIPS_PACRP_WP5_MASK 0x200u
+#define AIPS_PACRP_WP5_SHIFT 9
+#define AIPS_PACRP_SP5_MASK 0x400u
+#define AIPS_PACRP_SP5_SHIFT 10
+#define AIPS_PACRP_TP4_MASK 0x1000u
+#define AIPS_PACRP_TP4_SHIFT 12
+#define AIPS_PACRP_WP4_MASK 0x2000u
+#define AIPS_PACRP_WP4_SHIFT 13
+#define AIPS_PACRP_SP4_MASK 0x4000u
+#define AIPS_PACRP_SP4_SHIFT 14
+#define AIPS_PACRP_TP3_MASK 0x10000u
+#define AIPS_PACRP_TP3_SHIFT 16
+#define AIPS_PACRP_WP3_MASK 0x20000u
+#define AIPS_PACRP_WP3_SHIFT 17
+#define AIPS_PACRP_SP3_MASK 0x40000u
+#define AIPS_PACRP_SP3_SHIFT 18
+#define AIPS_PACRP_TP2_MASK 0x100000u
+#define AIPS_PACRP_TP2_SHIFT 20
+#define AIPS_PACRP_WP2_MASK 0x200000u
+#define AIPS_PACRP_WP2_SHIFT 21
+#define AIPS_PACRP_SP2_MASK 0x400000u
+#define AIPS_PACRP_SP2_SHIFT 22
+#define AIPS_PACRP_TP1_MASK 0x1000000u
+#define AIPS_PACRP_TP1_SHIFT 24
+#define AIPS_PACRP_WP1_MASK 0x2000000u
+#define AIPS_PACRP_WP1_SHIFT 25
+#define AIPS_PACRP_SP1_MASK 0x4000000u
+#define AIPS_PACRP_SP1_SHIFT 26
+#define AIPS_PACRP_TP0_MASK 0x10000000u
+#define AIPS_PACRP_TP0_SHIFT 28
+#define AIPS_PACRP_WP0_MASK 0x20000000u
+#define AIPS_PACRP_WP0_SHIFT 29
+#define AIPS_PACRP_SP0_MASK 0x40000000u
+#define AIPS_PACRP_SP0_SHIFT 30
+/* PACRU Bit Fields */
+#define AIPS_PACRU_TP1_MASK 0x1000000u
+#define AIPS_PACRU_TP1_SHIFT 24
+#define AIPS_PACRU_WP1_MASK 0x2000000u
+#define AIPS_PACRU_WP1_SHIFT 25
+#define AIPS_PACRU_SP1_MASK 0x4000000u
+#define AIPS_PACRU_SP1_SHIFT 26
+#define AIPS_PACRU_TP0_MASK 0x10000000u
+#define AIPS_PACRU_TP0_SHIFT 28
+#define AIPS_PACRU_WP0_MASK 0x20000000u
+#define AIPS_PACRU_WP0_SHIFT 29
+#define AIPS_PACRU_SP0_MASK 0x40000000u
+#define AIPS_PACRU_SP0_SHIFT 30
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Masks */
+
+
+/* AIPS - Peripheral instance base addresses */
+/** Peripheral AIPS0 base address */
+#define AIPS0_BASE (0x40000000u)
+/** Peripheral AIPS0 base pointer */
+#define AIPS0 ((AIPS_Type *)AIPS0_BASE)
+#define AIPS0_BASE_PTR (AIPS0)
+/** Peripheral AIPS1 base address */
+#define AIPS1_BASE (0x40080000u)
+/** Peripheral AIPS1 base pointer */
+#define AIPS1 ((AIPS_Type *)AIPS1_BASE)
+#define AIPS1_BASE_PTR (AIPS1)
+/** Array initializer of AIPS peripheral base pointers */
+#define AIPS_BASES { AIPS0, AIPS1 }
+
+/* ----------------------------------------------------------------------------
+ -- AIPS - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
+ * @{
+ */
+
+
+/* AIPS - Register instance definitions */
+/* AIPS0 */
+#define AIPS0_MPRA AIPS_MPRA_REG(AIPS0)
+#define AIPS0_PACRA AIPS_PACRA_REG(AIPS0)
+#define AIPS0_PACRB AIPS_PACRB_REG(AIPS0)
+#define AIPS0_PACRC AIPS_PACRC_REG(AIPS0)
+#define AIPS0_PACRD AIPS_PACRD_REG(AIPS0)
+#define AIPS0_PACRE AIPS_PACRE_REG(AIPS0)
+#define AIPS0_PACRF AIPS_PACRF_REG(AIPS0)
+#define AIPS0_PACRG AIPS_PACRG_REG(AIPS0)
+#define AIPS0_PACRH AIPS_PACRH_REG(AIPS0)
+#define AIPS0_PACRI AIPS_PACRI_REG(AIPS0)
+#define AIPS0_PACRJ AIPS_PACRJ_REG(AIPS0)
+#define AIPS0_PACRK AIPS_PACRK_REG(AIPS0)
+#define AIPS0_PACRL AIPS_PACRL_REG(AIPS0)
+#define AIPS0_PACRM AIPS_PACRM_REG(AIPS0)
+#define AIPS0_PACRN AIPS_PACRN_REG(AIPS0)
+#define AIPS0_PACRO AIPS_PACRO_REG(AIPS0)
+#define AIPS0_PACRP AIPS_PACRP_REG(AIPS0)
+#define AIPS0_PACRU AIPS_PACRU_REG(AIPS0)
+/* AIPS1 */
+#define AIPS1_MPRA AIPS_MPRA_REG(AIPS1)
+#define AIPS1_PACRA AIPS_PACRA_REG(AIPS1)
+#define AIPS1_PACRB AIPS_PACRB_REG(AIPS1)
+#define AIPS1_PACRC AIPS_PACRC_REG(AIPS1)
+#define AIPS1_PACRD AIPS_PACRD_REG(AIPS1)
+#define AIPS1_PACRE AIPS_PACRE_REG(AIPS1)
+#define AIPS1_PACRF AIPS_PACRF_REG(AIPS1)
+#define AIPS1_PACRG AIPS_PACRG_REG(AIPS1)
+#define AIPS1_PACRH AIPS_PACRH_REG(AIPS1)
+#define AIPS1_PACRI AIPS_PACRI_REG(AIPS1)
+#define AIPS1_PACRJ AIPS_PACRJ_REG(AIPS1)
+#define AIPS1_PACRK AIPS_PACRK_REG(AIPS1)
+#define AIPS1_PACRL AIPS_PACRL_REG(AIPS1)
+#define AIPS1_PACRM AIPS_PACRM_REG(AIPS1)
+#define AIPS1_PACRN AIPS_PACRN_REG(AIPS1)
+#define AIPS1_PACRO AIPS_PACRO_REG(AIPS1)
+#define AIPS1_PACRP AIPS_PACRP_REG(AIPS1)
+#define AIPS1_PACRU AIPS_PACRU_REG(AIPS1)
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group AIPS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- AXBS Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
+ * @{
+ */
+
+/** AXBS - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x100 */
+ __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
+ uint8_t RESERVED_0[12];
+ __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
+ uint8_t RESERVED_1[236];
+ } SLAVE[5];
+ uint8_t RESERVED_0[768];
+ __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
+ uint8_t RESERVED_1[252];
+ __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
+ uint8_t RESERVED_2[252];
+ __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
+ uint8_t RESERVED_3[252];
+ __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */
+ uint8_t RESERVED_4[252];
+ __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
+ uint8_t RESERVED_5[252];
+ __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */
+} AXBS_Type, *AXBS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- AXBS - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
+ * @{
+ */
+
+
+/* AXBS - Register accessors */
+#define AXBS_PRS_REG(base,index) ((base)->SLAVE[index].PRS)
+#define AXBS_CRS_REG(base,index) ((base)->SLAVE[index].CRS)
+#define AXBS_MGPCR0_REG(base) ((base)->MGPCR0)
+#define AXBS_MGPCR1_REG(base) ((base)->MGPCR1)
+#define AXBS_MGPCR2_REG(base) ((base)->MGPCR2)
+#define AXBS_MGPCR3_REG(base) ((base)->MGPCR3)
+#define AXBS_MGPCR4_REG(base) ((base)->MGPCR4)
+#define AXBS_MGPCR5_REG(base) ((base)->MGPCR5)
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- AXBS Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Masks AXBS Register Masks
+ * @{
+ */
+
+/* PRS Bit Fields */
+#define AXBS_PRS_M0_MASK 0x7u
+#define AXBS_PRS_M0_SHIFT 0
+#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK)
+#define AXBS_PRS_M1_MASK 0x70u
+#define AXBS_PRS_M1_SHIFT 4
+#define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK)
+#define AXBS_PRS_M2_MASK 0x700u
+#define AXBS_PRS_M2_SHIFT 8
+#define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK)
+#define AXBS_PRS_M3_MASK 0x7000u
+#define AXBS_PRS_M3_SHIFT 12
+#define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M3_SHIFT))&AXBS_PRS_M3_MASK)
+#define AXBS_PRS_M4_MASK 0x70000u
+#define AXBS_PRS_M4_SHIFT 16
+#define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK)
+#define AXBS_PRS_M5_MASK 0x700000u
+#define AXBS_PRS_M5_SHIFT 20
+#define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK)
+/* CRS Bit Fields */
+#define AXBS_CRS_PARK_MASK 0x7u
+#define AXBS_CRS_PARK_SHIFT 0
+#define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK)
+#define AXBS_CRS_PCTL_MASK 0x30u
+#define AXBS_CRS_PCTL_SHIFT 4
+#define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK)
+#define AXBS_CRS_ARB_MASK 0x300u
+#define AXBS_CRS_ARB_SHIFT 8
+#define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK)
+#define AXBS_CRS_HLP_MASK 0x40000000u
+#define AXBS_CRS_HLP_SHIFT 30
+#define AXBS_CRS_RO_MASK 0x80000000u
+#define AXBS_CRS_RO_SHIFT 31
+/* MGPCR0 Bit Fields */
+#define AXBS_MGPCR0_AULB_MASK 0x7u
+#define AXBS_MGPCR0_AULB_SHIFT 0
+#define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK)
+/* MGPCR1 Bit Fields */
+#define AXBS_MGPCR1_AULB_MASK 0x7u
+#define AXBS_MGPCR1_AULB_SHIFT 0
+#define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK)
+/* MGPCR2 Bit Fields */
+#define AXBS_MGPCR2_AULB_MASK 0x7u
+#define AXBS_MGPCR2_AULB_SHIFT 0
+#define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK)
+/* MGPCR3 Bit Fields */
+#define AXBS_MGPCR3_AULB_MASK 0x7u
+#define AXBS_MGPCR3_AULB_SHIFT 0
+#define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR3_AULB_SHIFT))&AXBS_MGPCR3_AULB_MASK)
+/* MGPCR4 Bit Fields */
+#define AXBS_MGPCR4_AULB_MASK 0x7u
+#define AXBS_MGPCR4_AULB_SHIFT 0
+#define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR4_AULB_SHIFT))&AXBS_MGPCR4_AULB_MASK)
+/* MGPCR5 Bit Fields */
+#define AXBS_MGPCR5_AULB_MASK 0x7u
+#define AXBS_MGPCR5_AULB_SHIFT 0
+#define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR5_AULB_SHIFT))&AXBS_MGPCR5_AULB_MASK)
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Masks */
+
+
+/* AXBS - Peripheral instance base addresses */
+/** Peripheral AXBS base address */
+#define AXBS_BASE (0x40004000u)
+/** Peripheral AXBS base pointer */
+#define AXBS ((AXBS_Type *)AXBS_BASE)
+#define AXBS_BASE_PTR (AXBS)
+/** Array initializer of AXBS peripheral base pointers */
+#define AXBS_BASES { AXBS }
+
+/* ----------------------------------------------------------------------------
+ -- AXBS - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
+ * @{
+ */
+
+
+/* AXBS - Register instance definitions */
+/* AXBS */
+#define AXBS_PRS0 AXBS_PRS_REG(AXBS,0)
+#define AXBS_CRS0 AXBS_CRS_REG(AXBS,0)
+#define AXBS_PRS1 AXBS_PRS_REG(AXBS,1)
+#define AXBS_CRS1 AXBS_CRS_REG(AXBS,1)
+#define AXBS_PRS2 AXBS_PRS_REG(AXBS,2)
+#define AXBS_CRS2 AXBS_CRS_REG(AXBS,2)
+#define AXBS_PRS3 AXBS_PRS_REG(AXBS,3)
+#define AXBS_CRS3 AXBS_CRS_REG(AXBS,3)
+#define AXBS_PRS4 AXBS_PRS_REG(AXBS,4)
+#define AXBS_CRS4 AXBS_CRS_REG(AXBS,4)
+#define AXBS_MGPCR0 AXBS_MGPCR0_REG(AXBS)
+#define AXBS_MGPCR1 AXBS_MGPCR1_REG(AXBS)
+#define AXBS_MGPCR2 AXBS_MGPCR2_REG(AXBS)
+#define AXBS_MGPCR3 AXBS_MGPCR3_REG(AXBS)
+#define AXBS_MGPCR4 AXBS_MGPCR4_REG(AXBS)
+#define AXBS_MGPCR5 AXBS_MGPCR5_REG(AXBS)
+
+/* AXBS - Register array accessors */
+#define AXBS_PRS(index) AXBS_PRS_REG(AXBS,index)
+#define AXBS_CRS(index) AXBS_CRS_REG(AXBS,index)
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group AXBS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CAN Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
+ * @{
+ */
+
+/** CAN - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
+ __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */
+ __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
+ __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */
+ __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */
+ __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
+ __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */
+ __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */
+ __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */
+ uint8_t RESERVED_3[8];
+ __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
+ __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */
+ __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
+ uint8_t RESERVED_4[48];
+ struct { /* offset: 0x80, array step: 0x10 */
+ __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
+ __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
+ __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
+ __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
+ } MB[16];
+ uint8_t RESERVED_5[1792];
+ __IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
+} CAN_Type, *CAN_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- CAN - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
+ * @{
+ */
+
+
+/* CAN - Register accessors */
+#define CAN_MCR_REG(base) ((base)->MCR)
+#define CAN_CTRL1_REG(base) ((base)->CTRL1)
+#define CAN_TIMER_REG(base) ((base)->TIMER)
+#define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK)
+#define CAN_RX14MASK_REG(base) ((base)->RX14MASK)
+#define CAN_RX15MASK_REG(base) ((base)->RX15MASK)
+#define CAN_ECR_REG(base) ((base)->ECR)
+#define CAN_ESR1_REG(base) ((base)->ESR1)
+#define CAN_IMASK1_REG(base) ((base)->IMASK1)
+#define CAN_IFLAG1_REG(base) ((base)->IFLAG1)
+#define CAN_CTRL2_REG(base) ((base)->CTRL2)
+#define CAN_ESR2_REG(base) ((base)->ESR2)
+#define CAN_CRCR_REG(base) ((base)->CRCR)
+#define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK)
+#define CAN_RXFIR_REG(base) ((base)->RXFIR)
+#define CAN_CS_REG(base,index) ((base)->MB[index].CS)
+#define CAN_ID_REG(base,index) ((base)->MB[index].ID)
+#define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0)
+#define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1)
+#define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index])
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- CAN Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Masks CAN Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define CAN_MCR_MAXMB_MASK 0x7Fu
+#define CAN_MCR_MAXMB_SHIFT 0
+#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
+#define CAN_MCR_IDAM_MASK 0x300u
+#define CAN_MCR_IDAM_SHIFT 8
+#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
+#define CAN_MCR_AEN_MASK 0x1000u
+#define CAN_MCR_AEN_SHIFT 12
+#define CAN_MCR_LPRIOEN_MASK 0x2000u
+#define CAN_MCR_LPRIOEN_SHIFT 13
+#define CAN_MCR_IRMQ_MASK 0x10000u
+#define CAN_MCR_IRMQ_SHIFT 16
+#define CAN_MCR_SRXDIS_MASK 0x20000u
+#define CAN_MCR_SRXDIS_SHIFT 17
+#define CAN_MCR_WAKSRC_MASK 0x80000u
+#define CAN_MCR_WAKSRC_SHIFT 19
+#define CAN_MCR_LPMACK_MASK 0x100000u
+#define CAN_MCR_LPMACK_SHIFT 20
+#define CAN_MCR_WRNEN_MASK 0x200000u
+#define CAN_MCR_WRNEN_SHIFT 21
+#define CAN_MCR_SLFWAK_MASK 0x400000u
+#define CAN_MCR_SLFWAK_SHIFT 22
+#define CAN_MCR_SUPV_MASK 0x800000u
+#define CAN_MCR_SUPV_SHIFT 23
+#define CAN_MCR_FRZACK_MASK 0x1000000u
+#define CAN_MCR_FRZACK_SHIFT 24
+#define CAN_MCR_SOFTRST_MASK 0x2000000u
+#define CAN_MCR_SOFTRST_SHIFT 25
+#define CAN_MCR_WAKMSK_MASK 0x4000000u
+#define CAN_MCR_WAKMSK_SHIFT 26
+#define CAN_MCR_NOTRDY_MASK 0x8000000u
+#define CAN_MCR_NOTRDY_SHIFT 27
+#define CAN_MCR_HALT_MASK 0x10000000u
+#define CAN_MCR_HALT_SHIFT 28
+#define CAN_MCR_RFEN_MASK 0x20000000u
+#define CAN_MCR_RFEN_SHIFT 29
+#define CAN_MCR_FRZ_MASK 0x40000000u
+#define CAN_MCR_FRZ_SHIFT 30
+#define CAN_MCR_MDIS_MASK 0x80000000u
+#define CAN_MCR_MDIS_SHIFT 31
+/* CTRL1 Bit Fields */
+#define CAN_CTRL1_PROPSEG_MASK 0x7u
+#define CAN_CTRL1_PROPSEG_SHIFT 0
+#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
+#define CAN_CTRL1_LOM_MASK 0x8u
+#define CAN_CTRL1_LOM_SHIFT 3
+#define CAN_CTRL1_LBUF_MASK 0x10u
+#define CAN_CTRL1_LBUF_SHIFT 4
+#define CAN_CTRL1_TSYN_MASK 0x20u
+#define CAN_CTRL1_TSYN_SHIFT 5
+#define CAN_CTRL1_BOFFREC_MASK 0x40u
+#define CAN_CTRL1_BOFFREC_SHIFT 6
+#define CAN_CTRL1_SMP_MASK 0x80u
+#define CAN_CTRL1_SMP_SHIFT 7
+#define CAN_CTRL1_RWRNMSK_MASK 0x400u
+#define CAN_CTRL1_RWRNMSK_SHIFT 10
+#define CAN_CTRL1_TWRNMSK_MASK 0x800u
+#define CAN_CTRL1_TWRNMSK_SHIFT 11
+#define CAN_CTRL1_LPB_MASK 0x1000u
+#define CAN_CTRL1_LPB_SHIFT 12
+#define CAN_CTRL1_CLKSRC_MASK 0x2000u
+#define CAN_CTRL1_CLKSRC_SHIFT 13
+#define CAN_CTRL1_ERRMSK_MASK 0x4000u
+#define CAN_CTRL1_ERRMSK_SHIFT 14
+#define CAN_CTRL1_BOFFMSK_MASK 0x8000u
+#define CAN_CTRL1_BOFFMSK_SHIFT 15
+#define CAN_CTRL1_PSEG2_MASK 0x70000u
+#define CAN_CTRL1_PSEG2_SHIFT 16
+#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
+#define CAN_CTRL1_PSEG1_MASK 0x380000u
+#define CAN_CTRL1_PSEG1_SHIFT 19
+#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
+#define CAN_CTRL1_RJW_MASK 0xC00000u
+#define CAN_CTRL1_RJW_SHIFT 22
+#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
+#define CAN_CTRL1_PRESDIV_MASK 0xFF000000u
+#define CAN_CTRL1_PRESDIV_SHIFT 24
+#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
+/* TIMER Bit Fields */
+#define CAN_TIMER_TIMER_MASK 0xFFFFu
+#define CAN_TIMER_TIMER_SHIFT 0
+#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
+/* RXMGMASK Bit Fields */
+#define CAN_RXMGMASK_MG_MASK 0xFFFFFFFFu
+#define CAN_RXMGMASK_MG_SHIFT 0
+#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
+/* RX14MASK Bit Fields */
+#define CAN_RX14MASK_RX14M_MASK 0xFFFFFFFFu
+#define CAN_RX14MASK_RX14M_SHIFT 0
+#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
+/* RX15MASK Bit Fields */
+#define CAN_RX15MASK_RX15M_MASK 0xFFFFFFFFu
+#define CAN_RX15MASK_RX15M_SHIFT 0
+#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
+/* ECR Bit Fields */
+#define CAN_ECR_TXERRCNT_MASK 0xFFu
+#define CAN_ECR_TXERRCNT_SHIFT 0
+#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
+#define CAN_ECR_RXERRCNT_MASK 0xFF00u
+#define CAN_ECR_RXERRCNT_SHIFT 8
+#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
+/* ESR1 Bit Fields */
+#define CAN_ESR1_WAKINT_MASK 0x1u
+#define CAN_ESR1_WAKINT_SHIFT 0
+#define CAN_ESR1_ERRINT_MASK 0x2u
+#define CAN_ESR1_ERRINT_SHIFT 1
+#define CAN_ESR1_BOFFINT_MASK 0x4u
+#define CAN_ESR1_BOFFINT_SHIFT 2
+#define CAN_ESR1_RX_MASK 0x8u
+#define CAN_ESR1_RX_SHIFT 3
+#define CAN_ESR1_FLTCONF_MASK 0x30u
+#define CAN_ESR1_FLTCONF_SHIFT 4
+#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
+#define CAN_ESR1_TX_MASK 0x40u
+#define CAN_ESR1_TX_SHIFT 6
+#define CAN_ESR1_IDLE_MASK 0x80u
+#define CAN_ESR1_IDLE_SHIFT 7
+#define CAN_ESR1_RXWRN_MASK 0x100u
+#define CAN_ESR1_RXWRN_SHIFT 8
+#define CAN_ESR1_TXWRN_MASK 0x200u
+#define CAN_ESR1_TXWRN_SHIFT 9
+#define CAN_ESR1_STFERR_MASK 0x400u
+#define CAN_ESR1_STFERR_SHIFT 10
+#define CAN_ESR1_FRMERR_MASK 0x800u
+#define CAN_ESR1_FRMERR_SHIFT 11
+#define CAN_ESR1_CRCERR_MASK 0x1000u
+#define CAN_ESR1_CRCERR_SHIFT 12
+#define CAN_ESR1_ACKERR_MASK 0x2000u
+#define CAN_ESR1_ACKERR_SHIFT 13
+#define CAN_ESR1_BIT0ERR_MASK 0x4000u
+#define CAN_ESR1_BIT0ERR_SHIFT 14
+#define CAN_ESR1_BIT1ERR_MASK 0x8000u
+#define CAN_ESR1_BIT1ERR_SHIFT 15
+#define CAN_ESR1_RWRNINT_MASK 0x10000u
+#define CAN_ESR1_RWRNINT_SHIFT 16
+#define CAN_ESR1_TWRNINT_MASK 0x20000u
+#define CAN_ESR1_TWRNINT_SHIFT 17
+#define CAN_ESR1_SYNCH_MASK 0x40000u
+#define CAN_ESR1_SYNCH_SHIFT 18
+/* IMASK1 Bit Fields */
+#define CAN_IMASK1_BUFLM_MASK 0xFFFFFFFFu
+#define CAN_IMASK1_BUFLM_SHIFT 0
+#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)
+/* IFLAG1 Bit Fields */
+#define CAN_IFLAG1_BUF0I_MASK 0x1u
+#define CAN_IFLAG1_BUF0I_SHIFT 0
+#define CAN_IFLAG1_BUF4TO1I_MASK 0x1Eu
+#define CAN_IFLAG1_BUF4TO1I_SHIFT 1
+#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO1I_SHIFT))&CAN_IFLAG1_BUF4TO1I_MASK)
+#define CAN_IFLAG1_BUF5I_MASK 0x20u
+#define CAN_IFLAG1_BUF5I_SHIFT 5
+#define CAN_IFLAG1_BUF6I_MASK 0x40u
+#define CAN_IFLAG1_BUF6I_SHIFT 6
+#define CAN_IFLAG1_BUF7I_MASK 0x80u
+#define CAN_IFLAG1_BUF7I_SHIFT 7
+#define CAN_IFLAG1_BUF31TO8I_MASK 0xFFFFFF00u
+#define CAN_IFLAG1_BUF31TO8I_SHIFT 8
+#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
+/* CTRL2 Bit Fields */
+#define CAN_CTRL2_EACEN_MASK 0x10000u
+#define CAN_CTRL2_EACEN_SHIFT 16
+#define CAN_CTRL2_RRS_MASK 0x20000u
+#define CAN_CTRL2_RRS_SHIFT 17
+#define CAN_CTRL2_MRP_MASK 0x40000u
+#define CAN_CTRL2_MRP_SHIFT 18
+#define CAN_CTRL2_TASD_MASK 0xF80000u
+#define CAN_CTRL2_TASD_SHIFT 19
+#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
+#define CAN_CTRL2_RFFN_MASK 0xF000000u
+#define CAN_CTRL2_RFFN_SHIFT 24
+#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
+#define CAN_CTRL2_WRMFRZ_MASK 0x10000000u
+#define CAN_CTRL2_WRMFRZ_SHIFT 28
+/* ESR2 Bit Fields */
+#define CAN_ESR2_IMB_MASK 0x2000u
+#define CAN_ESR2_IMB_SHIFT 13
+#define CAN_ESR2_VPS_MASK 0x4000u
+#define CAN_ESR2_VPS_SHIFT 14
+#define CAN_ESR2_LPTM_MASK 0x7F0000u
+#define CAN_ESR2_LPTM_SHIFT 16
+#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
+/* CRCR Bit Fields */
+#define CAN_CRCR_TXCRC_MASK 0x7FFFu
+#define CAN_CRCR_TXCRC_SHIFT 0
+#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
+#define CAN_CRCR_MBCRC_MASK 0x7F0000u
+#define CAN_CRCR_MBCRC_SHIFT 16
+#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
+/* RXFGMASK Bit Fields */
+#define CAN_RXFGMASK_FGM_MASK 0xFFFFFFFFu
+#define CAN_RXFGMASK_FGM_SHIFT 0
+#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
+/* RXFIR Bit Fields */
+#define CAN_RXFIR_IDHIT_MASK 0x1FFu
+#define CAN_RXFIR_IDHIT_SHIFT 0
+#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
+/* CS Bit Fields */
+#define CAN_CS_TIME_STAMP_MASK 0xFFFFu
+#define CAN_CS_TIME_STAMP_SHIFT 0
+#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
+#define CAN_CS_DLC_MASK 0xF0000u
+#define CAN_CS_DLC_SHIFT 16
+#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
+#define CAN_CS_RTR_MASK 0x100000u
+#define CAN_CS_RTR_SHIFT 20
+#define CAN_CS_IDE_MASK 0x200000u
+#define CAN_CS_IDE_SHIFT 21
+#define CAN_CS_SRR_MASK 0x400000u
+#define CAN_CS_SRR_SHIFT 22
+#define CAN_CS_CODE_MASK 0xF000000u
+#define CAN_CS_CODE_SHIFT 24
+#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
+/* ID Bit Fields */
+#define CAN_ID_EXT_MASK 0x3FFFFu
+#define CAN_ID_EXT_SHIFT 0
+#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
+#define CAN_ID_STD_MASK 0x1FFC0000u
+#define CAN_ID_STD_SHIFT 18
+#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
+#define CAN_ID_PRIO_MASK 0xE0000000u
+#define CAN_ID_PRIO_SHIFT 29
+#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
+/* WORD0 Bit Fields */
+#define CAN_WORD0_DATA_BYTE_3_MASK 0xFFu
+#define CAN_WORD0_DATA_BYTE_3_SHIFT 0
+#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
+#define CAN_WORD0_DATA_BYTE_2_MASK 0xFF00u
+#define CAN_WORD0_DATA_BYTE_2_SHIFT 8
+#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
+#define CAN_WORD0_DATA_BYTE_1_MASK 0xFF0000u
+#define CAN_WORD0_DATA_BYTE_1_SHIFT 16
+#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
+#define CAN_WORD0_DATA_BYTE_0_MASK 0xFF000000u
+#define CAN_WORD0_DATA_BYTE_0_SHIFT 24
+#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
+/* WORD1 Bit Fields */
+#define CAN_WORD1_DATA_BYTE_7_MASK 0xFFu
+#define CAN_WORD1_DATA_BYTE_7_SHIFT 0
+#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
+#define CAN_WORD1_DATA_BYTE_6_MASK 0xFF00u
+#define CAN_WORD1_DATA_BYTE_6_SHIFT 8
+#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
+#define CAN_WORD1_DATA_BYTE_5_MASK 0xFF0000u
+#define CAN_WORD1_DATA_BYTE_5_SHIFT 16
+#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
+#define CAN_WORD1_DATA_BYTE_4_MASK 0xFF000000u
+#define CAN_WORD1_DATA_BYTE_4_SHIFT 24
+#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
+/* RXIMR Bit Fields */
+#define CAN_RXIMR_MI_MASK 0xFFFFFFFFu
+#define CAN_RXIMR_MI_SHIFT 0
+#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Masks */
+
+
+/* CAN - Peripheral instance base addresses */
+/** Peripheral CAN0 base address */
+#define CAN0_BASE (0x40024000u)
+/** Peripheral CAN0 base pointer */
+#define CAN0 ((CAN_Type *)CAN0_BASE)
+#define CAN0_BASE_PTR (CAN0)
+/** Array initializer of CAN peripheral base pointers */
+#define CAN_BASES { CAN0 }
+
+/* ----------------------------------------------------------------------------
+ -- CAN - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
+ * @{
+ */
+
+
+/* CAN - Register instance definitions */
+/* CAN0 */
+#define CAN0_MCR CAN_MCR_REG(CAN0)
+#define CAN0_CTRL1 CAN_CTRL1_REG(CAN0)
+#define CAN0_TIMER CAN_TIMER_REG(CAN0)
+#define CAN0_RXMGMASK CAN_RXMGMASK_REG(CAN0)
+#define CAN0_RX14MASK CAN_RX14MASK_REG(CAN0)
+#define CAN0_RX15MASK CAN_RX15MASK_REG(CAN0)
+#define CAN0_ECR CAN_ECR_REG(CAN0)
+#define CAN0_ESR1 CAN_ESR1_REG(CAN0)
+#define CAN0_IMASK1 CAN_IMASK1_REG(CAN0)
+#define CAN0_IFLAG1 CAN_IFLAG1_REG(CAN0)
+#define CAN0_CTRL2 CAN_CTRL2_REG(CAN0)
+#define CAN0_ESR2 CAN_ESR2_REG(CAN0)
+#define CAN0_CRCR CAN_CRCR_REG(CAN0)
+#define CAN0_RXFGMASK CAN_RXFGMASK_REG(CAN0)
+#define CAN0_RXFIR CAN_RXFIR_REG(CAN0)
+#define CAN0_CS0 CAN_CS_REG(CAN0,0)
+#define CAN0_ID0 CAN_ID_REG(CAN0,0)
+#define CAN0_WORD00 CAN_WORD0_REG(CAN0,0)
+#define CAN0_WORD10 CAN_WORD1_REG(CAN0,0)
+#define CAN0_CS1 CAN_CS_REG(CAN0,1)
+#define CAN0_ID1 CAN_ID_REG(CAN0,1)
+#define CAN0_WORD01 CAN_WORD0_REG(CAN0,1)
+#define CAN0_WORD11 CAN_WORD1_REG(CAN0,1)
+#define CAN0_CS2 CAN_CS_REG(CAN0,2)
+#define CAN0_ID2 CAN_ID_REG(CAN0,2)
+#define CAN0_WORD02 CAN_WORD0_REG(CAN0,2)
+#define CAN0_WORD12 CAN_WORD1_REG(CAN0,2)
+#define CAN0_CS3 CAN_CS_REG(CAN0,3)
+#define CAN0_ID3 CAN_ID_REG(CAN0,3)
+#define CAN0_WORD03 CAN_WORD0_REG(CAN0,3)
+#define CAN0_WORD13 CAN_WORD1_REG(CAN0,3)
+#define CAN0_CS4 CAN_CS_REG(CAN0,4)
+#define CAN0_ID4 CAN_ID_REG(CAN0,4)
+#define CAN0_WORD04 CAN_WORD0_REG(CAN0,4)
+#define CAN0_WORD14 CAN_WORD1_REG(CAN0,4)
+#define CAN0_CS5 CAN_CS_REG(CAN0,5)
+#define CAN0_ID5 CAN_ID_REG(CAN0,5)
+#define CAN0_WORD05 CAN_WORD0_REG(CAN0,5)
+#define CAN0_WORD15 CAN_WORD1_REG(CAN0,5)
+#define CAN0_CS6 CAN_CS_REG(CAN0,6)
+#define CAN0_ID6 CAN_ID_REG(CAN0,6)
+#define CAN0_WORD06 CAN_WORD0_REG(CAN0,6)
+#define CAN0_WORD16 CAN_WORD1_REG(CAN0,6)
+#define CAN0_CS7 CAN_CS_REG(CAN0,7)
+#define CAN0_ID7 CAN_ID_REG(CAN0,7)
+#define CAN0_WORD07 CAN_WORD0_REG(CAN0,7)
+#define CAN0_WORD17 CAN_WORD1_REG(CAN0,7)
+#define CAN0_CS8 CAN_CS_REG(CAN0,8)
+#define CAN0_ID8 CAN_ID_REG(CAN0,8)
+#define CAN0_WORD08 CAN_WORD0_REG(CAN0,8)
+#define CAN0_WORD18 CAN_WORD1_REG(CAN0,8)
+#define CAN0_CS9 CAN_CS_REG(CAN0,9)
+#define CAN0_ID9 CAN_ID_REG(CAN0,9)
+#define CAN0_WORD09 CAN_WORD0_REG(CAN0,9)
+#define CAN0_WORD19 CAN_WORD1_REG(CAN0,9)
+#define CAN0_CS10 CAN_CS_REG(CAN0,10)
+#define CAN0_ID10 CAN_ID_REG(CAN0,10)
+#define CAN0_WORD010 CAN_WORD0_REG(CAN0,10)
+#define CAN0_WORD110 CAN_WORD1_REG(CAN0,10)
+#define CAN0_CS11 CAN_CS_REG(CAN0,11)
+#define CAN0_ID11 CAN_ID_REG(CAN0,11)
+#define CAN0_WORD011 CAN_WORD0_REG(CAN0,11)
+#define CAN0_WORD111 CAN_WORD1_REG(CAN0,11)
+#define CAN0_CS12 CAN_CS_REG(CAN0,12)
+#define CAN0_ID12 CAN_ID_REG(CAN0,12)
+#define CAN0_WORD012 CAN_WORD0_REG(CAN0,12)
+#define CAN0_WORD112 CAN_WORD1_REG(CAN0,12)
+#define CAN0_CS13 CAN_CS_REG(CAN0,13)
+#define CAN0_ID13 CAN_ID_REG(CAN0,13)
+#define CAN0_WORD013 CAN_WORD0_REG(CAN0,13)
+#define CAN0_WORD113 CAN_WORD1_REG(CAN0,13)
+#define CAN0_CS14 CAN_CS_REG(CAN0,14)
+#define CAN0_ID14 CAN_ID_REG(CAN0,14)
+#define CAN0_WORD014 CAN_WORD0_REG(CAN0,14)
+#define CAN0_WORD114 CAN_WORD1_REG(CAN0,14)
+#define CAN0_CS15 CAN_CS_REG(CAN0,15)
+#define CAN0_ID15 CAN_ID_REG(CAN0,15)
+#define CAN0_WORD015 CAN_WORD0_REG(CAN0,15)
+#define CAN0_WORD115 CAN_WORD1_REG(CAN0,15)
+#define CAN0_RXIMR0 CAN_RXIMR_REG(CAN0,0)
+#define CAN0_RXIMR1 CAN_RXIMR_REG(CAN0,1)
+#define CAN0_RXIMR2 CAN_RXIMR_REG(CAN0,2)
+#define CAN0_RXIMR3 CAN_RXIMR_REG(CAN0,3)
+#define CAN0_RXIMR4 CAN_RXIMR_REG(CAN0,4)
+#define CAN0_RXIMR5 CAN_RXIMR_REG(CAN0,5)
+#define CAN0_RXIMR6 CAN_RXIMR_REG(CAN0,6)
+#define CAN0_RXIMR7 CAN_RXIMR_REG(CAN0,7)
+#define CAN0_RXIMR8 CAN_RXIMR_REG(CAN0,8)
+#define CAN0_RXIMR9 CAN_RXIMR_REG(CAN0,9)
+#define CAN0_RXIMR10 CAN_RXIMR_REG(CAN0,10)
+#define CAN0_RXIMR11 CAN_RXIMR_REG(CAN0,11)
+#define CAN0_RXIMR12 CAN_RXIMR_REG(CAN0,12)
+#define CAN0_RXIMR13 CAN_RXIMR_REG(CAN0,13)
+#define CAN0_RXIMR14 CAN_RXIMR_REG(CAN0,14)
+#define CAN0_RXIMR15 CAN_RXIMR_REG(CAN0,15)
+
+/* CAN - Register array accessors */
+#define CAN0_CS(index) CAN_CS_REG(CAN0,index)
+#define CAN0_ID(index) CAN_ID_REG(CAN0,index)
+#define CAN0_WORD0(index) CAN_WORD0_REG(CAN0,index)
+#define CAN0_WORD1(index) CAN_WORD1_REG(CAN0,index)
+#define CAN0_RXIMR(index) CAN_RXIMR_REG(CAN0,index)
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CAN_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CAU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
+ * @{
+ */
+
+/** CAU - Register Layout Typedef */
+typedef struct {
+ __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
+ uint8_t RESERVED_0[2048];
+ __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
+ __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
+ __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
+ uint8_t RESERVED_1[20];
+ __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
+ __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
+ __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
+ uint8_t RESERVED_2[20];
+ __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
+ __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
+ __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
+ uint8_t RESERVED_3[20];
+ __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
+ __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
+ __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
+ uint8_t RESERVED_4[84];
+ __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
+ __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
+ __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
+ uint8_t RESERVED_5[20];
+ __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
+ __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
+ __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
+ uint8_t RESERVED_6[276];
+ __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
+ __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
+ __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
+ uint8_t RESERVED_7[20];
+ __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
+ __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
+ __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
+} CAU_Type, *CAU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- CAU - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
+ * @{
+ */
+
+
+/* CAU - Register accessors */
+#define CAU_DIRECT_REG(base,index) ((base)->DIRECT[index])
+#define CAU_LDR_CASR_REG(base) ((base)->LDR_CASR)
+#define CAU_LDR_CAA_REG(base) ((base)->LDR_CAA)
+#define CAU_LDR_CA_REG(base,index) ((base)->LDR_CA[index])
+#define CAU_STR_CASR_REG(base) ((base)->STR_CASR)
+#define CAU_STR_CAA_REG(base) ((base)->STR_CAA)
+#define CAU_STR_CA_REG(base,index) ((base)->STR_CA[index])
+#define CAU_ADR_CASR_REG(base) ((base)->ADR_CASR)
+#define CAU_ADR_CAA_REG(base) ((base)->ADR_CAA)
+#define CAU_ADR_CA_REG(base,index) ((base)->ADR_CA[index])
+#define CAU_RADR_CASR_REG(base) ((base)->RADR_CASR)
+#define CAU_RADR_CAA_REG(base) ((base)->RADR_CAA)
+#define CAU_RADR_CA_REG(base,index) ((base)->RADR_CA[index])
+#define CAU_XOR_CASR_REG(base) ((base)->XOR_CASR)
+#define CAU_XOR_CAA_REG(base) ((base)->XOR_CAA)
+#define CAU_XOR_CA_REG(base,index) ((base)->XOR_CA[index])
+#define CAU_ROTL_CASR_REG(base) ((base)->ROTL_CASR)
+#define CAU_ROTL_CAA_REG(base) ((base)->ROTL_CAA)
+#define CAU_ROTL_CA_REG(base,index) ((base)->ROTL_CA[index])
+#define CAU_AESC_CASR_REG(base) ((base)->AESC_CASR)
+#define CAU_AESC_CAA_REG(base) ((base)->AESC_CAA)
+#define CAU_AESC_CA_REG(base,index) ((base)->AESC_CA[index])
+#define CAU_AESIC_CASR_REG(base) ((base)->AESIC_CASR)
+#define CAU_AESIC_CAA_REG(base) ((base)->AESIC_CAA)
+#define CAU_AESIC_CA_REG(base,index) ((base)->AESIC_CA[index])
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- CAU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Masks CAU Register Masks
+ * @{
+ */
+
+/* LDR_CASR Bit Fields */
+#define CAU_LDR_CASR_IC_MASK 0x1u
+#define CAU_LDR_CASR_IC_SHIFT 0
+#define CAU_LDR_CASR_DPE_MASK 0x2u
+#define CAU_LDR_CASR_DPE_SHIFT 1
+#define CAU_LDR_CASR_VER_MASK 0xF0000000u
+#define CAU_LDR_CASR_VER_SHIFT 28
+#define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_VER_SHIFT))&CAU_LDR_CASR_VER_MASK)
+/* STR_CASR Bit Fields */
+#define CAU_STR_CASR_IC_MASK 0x1u
+#define CAU_STR_CASR_IC_SHIFT 0
+#define CAU_STR_CASR_DPE_MASK 0x2u
+#define CAU_STR_CASR_DPE_SHIFT 1
+#define CAU_STR_CASR_VER_MASK 0xF0000000u
+#define CAU_STR_CASR_VER_SHIFT 28
+#define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_VER_SHIFT))&CAU_STR_CASR_VER_MASK)
+/* ADR_CASR Bit Fields */
+#define CAU_ADR_CASR_IC_MASK 0x1u
+#define CAU_ADR_CASR_IC_SHIFT 0
+#define CAU_ADR_CASR_DPE_MASK 0x2u
+#define CAU_ADR_CASR_DPE_SHIFT 1
+#define CAU_ADR_CASR_VER_MASK 0xF0000000u
+#define CAU_ADR_CASR_VER_SHIFT 28
+#define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_VER_SHIFT))&CAU_ADR_CASR_VER_MASK)
+/* RADR_CASR Bit Fields */
+#define CAU_RADR_CASR_IC_MASK 0x1u
+#define CAU_RADR_CASR_IC_SHIFT 0
+#define CAU_RADR_CASR_DPE_MASK 0x2u
+#define CAU_RADR_CASR_DPE_SHIFT 1
+#define CAU_RADR_CASR_VER_MASK 0xF0000000u
+#define CAU_RADR_CASR_VER_SHIFT 28
+#define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_VER_SHIFT))&CAU_RADR_CASR_VER_MASK)
+/* XOR_CASR Bit Fields */
+#define CAU_XOR_CASR_IC_MASK 0x1u
+#define CAU_XOR_CASR_IC_SHIFT 0
+#define CAU_XOR_CASR_DPE_MASK 0x2u
+#define CAU_XOR_CASR_DPE_SHIFT 1
+#define CAU_XOR_CASR_VER_MASK 0xF0000000u
+#define CAU_XOR_CASR_VER_SHIFT 28
+#define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_VER_SHIFT))&CAU_XOR_CASR_VER_MASK)
+/* ROTL_CASR Bit Fields */
+#define CAU_ROTL_CASR_IC_MASK 0x1u
+#define CAU_ROTL_CASR_IC_SHIFT 0
+#define CAU_ROTL_CASR_DPE_MASK 0x2u
+#define CAU_ROTL_CASR_DPE_SHIFT 1
+#define CAU_ROTL_CASR_VER_MASK 0xF0000000u
+#define CAU_ROTL_CASR_VER_SHIFT 28
+#define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_VER_SHIFT))&CAU_ROTL_CASR_VER_MASK)
+/* AESC_CASR Bit Fields */
+#define CAU_AESC_CASR_IC_MASK 0x1u
+#define CAU_AESC_CASR_IC_SHIFT 0
+#define CAU_AESC_CASR_DPE_MASK 0x2u
+#define CAU_AESC_CASR_DPE_SHIFT 1
+#define CAU_AESC_CASR_VER_MASK 0xF0000000u
+#define CAU_AESC_CASR_VER_SHIFT 28
+#define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_VER_SHIFT))&CAU_AESC_CASR_VER_MASK)
+/* AESIC_CASR Bit Fields */
+#define CAU_AESIC_CASR_IC_MASK 0x1u
+#define CAU_AESIC_CASR_IC_SHIFT 0
+#define CAU_AESIC_CASR_DPE_MASK 0x2u
+#define CAU_AESIC_CASR_DPE_SHIFT 1
+#define CAU_AESIC_CASR_VER_MASK 0xF0000000u
+#define CAU_AESIC_CASR_VER_SHIFT 28
+#define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_VER_SHIFT))&CAU_AESIC_CASR_VER_MASK)
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Masks */
+
+
+/* CAU - Peripheral instance base addresses */
+/** Peripheral CAU base address */
+#define CAU_BASE (0xE0081000u)
+/** Peripheral CAU base pointer */
+#define CAU ((CAU_Type *)CAU_BASE)
+#define CAU_BASE_PTR (CAU)
+/** Array initializer of CAU peripheral base pointers */
+#define CAU_BASES { CAU }
+
+/* ----------------------------------------------------------------------------
+ -- CAU - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
+ * @{
+ */
+
+
+/* CAU - Register instance definitions */
+/* CAU */
+#define CAU_DIRECT0 CAU_DIRECT_REG(CAU,0)
+#define CAU_DIRECT1 CAU_DIRECT_REG(CAU,1)
+#define CAU_DIRECT2 CAU_DIRECT_REG(CAU,2)
+#define CAU_DIRECT3 CAU_DIRECT_REG(CAU,3)
+#define CAU_DIRECT4 CAU_DIRECT_REG(CAU,4)
+#define CAU_DIRECT5 CAU_DIRECT_REG(CAU,5)
+#define CAU_DIRECT6 CAU_DIRECT_REG(CAU,6)
+#define CAU_DIRECT7 CAU_DIRECT_REG(CAU,7)
+#define CAU_DIRECT8 CAU_DIRECT_REG(CAU,8)
+#define CAU_DIRECT9 CAU_DIRECT_REG(CAU,9)
+#define CAU_DIRECT10 CAU_DIRECT_REG(CAU,10)
+#define CAU_DIRECT11 CAU_DIRECT_REG(CAU,11)
+#define CAU_DIRECT12 CAU_DIRECT_REG(CAU,12)
+#define CAU_DIRECT13 CAU_DIRECT_REG(CAU,13)
+#define CAU_DIRECT14 CAU_DIRECT_REG(CAU,14)
+#define CAU_DIRECT15 CAU_DIRECT_REG(CAU,15)
+#define CAU_LDR_CASR CAU_LDR_CASR_REG(CAU)
+#define CAU_LDR_CAA CAU_LDR_CAA_REG(CAU)
+#define CAU_LDR_CA0 CAU_LDR_CA_REG(CAU,0)
+#define CAU_LDR_CA1 CAU_LDR_CA_REG(CAU,1)
+#define CAU_LDR_CA2 CAU_LDR_CA_REG(CAU,2)
+#define CAU_LDR_CA3 CAU_LDR_CA_REG(CAU,3)
+#define CAU_LDR_CA4 CAU_LDR_CA_REG(CAU,4)
+#define CAU_LDR_CA5 CAU_LDR_CA_REG(CAU,5)
+#define CAU_LDR_CA6 CAU_LDR_CA_REG(CAU,6)
+#define CAU_LDR_CA7 CAU_LDR_CA_REG(CAU,7)
+#define CAU_LDR_CA8 CAU_LDR_CA_REG(CAU,8)
+#define CAU_STR_CASR CAU_STR_CASR_REG(CAU)
+#define CAU_STR_CAA CAU_STR_CAA_REG(CAU)
+#define CAU_STR_CA0 CAU_STR_CA_REG(CAU,0)
+#define CAU_STR_CA1 CAU_STR_CA_REG(CAU,1)
+#define CAU_STR_CA2 CAU_STR_CA_REG(CAU,2)
+#define CAU_STR_CA3 CAU_STR_CA_REG(CAU,3)
+#define CAU_STR_CA4 CAU_STR_CA_REG(CAU,4)
+#define CAU_STR_CA5 CAU_STR_CA_REG(CAU,5)
+#define CAU_STR_CA6 CAU_STR_CA_REG(CAU,6)
+#define CAU_STR_CA7 CAU_STR_CA_REG(CAU,7)
+#define CAU_STR_CA8 CAU_STR_CA_REG(CAU,8)
+#define CAU_ADR_CASR CAU_ADR_CASR_REG(CAU)
+#define CAU_ADR_CAA CAU_ADR_CAA_REG(CAU)
+#define CAU_ADR_CA0 CAU_ADR_CA_REG(CAU,0)
+#define CAU_ADR_CA1 CAU_ADR_CA_REG(CAU,1)
+#define CAU_ADR_CA2 CAU_ADR_CA_REG(CAU,2)
+#define CAU_ADR_CA3 CAU_ADR_CA_REG(CAU,3)
+#define CAU_ADR_CA4 CAU_ADR_CA_REG(CAU,4)
+#define CAU_ADR_CA5 CAU_ADR_CA_REG(CAU,5)
+#define CAU_ADR_CA6 CAU_ADR_CA_REG(CAU,6)
+#define CAU_ADR_CA7 CAU_ADR_CA_REG(CAU,7)
+#define CAU_ADR_CA8 CAU_ADR_CA_REG(CAU,8)
+#define CAU_RADR_CASR CAU_RADR_CASR_REG(CAU)
+#define CAU_RADR_CAA CAU_RADR_CAA_REG(CAU)
+#define CAU_RADR_CA0 CAU_RADR_CA_REG(CAU,0)
+#define CAU_RADR_CA1 CAU_RADR_CA_REG(CAU,1)
+#define CAU_RADR_CA2 CAU_RADR_CA_REG(CAU,2)
+#define CAU_RADR_CA3 CAU_RADR_CA_REG(CAU,3)
+#define CAU_RADR_CA4 CAU_RADR_CA_REG(CAU,4)
+#define CAU_RADR_CA5 CAU_RADR_CA_REG(CAU,5)
+#define CAU_RADR_CA6 CAU_RADR_CA_REG(CAU,6)
+#define CAU_RADR_CA7 CAU_RADR_CA_REG(CAU,7)
+#define CAU_RADR_CA8 CAU_RADR_CA_REG(CAU,8)
+#define CAU_XOR_CASR CAU_XOR_CASR_REG(CAU)
+#define CAU_XOR_CAA CAU_XOR_CAA_REG(CAU)
+#define CAU_XOR_CA0 CAU_XOR_CA_REG(CAU,0)
+#define CAU_XOR_CA1 CAU_XOR_CA_REG(CAU,1)
+#define CAU_XOR_CA2 CAU_XOR_CA_REG(CAU,2)
+#define CAU_XOR_CA3 CAU_XOR_CA_REG(CAU,3)
+#define CAU_XOR_CA4 CAU_XOR_CA_REG(CAU,4)
+#define CAU_XOR_CA5 CAU_XOR_CA_REG(CAU,5)
+#define CAU_XOR_CA6 CAU_XOR_CA_REG(CAU,6)
+#define CAU_XOR_CA7 CAU_XOR_CA_REG(CAU,7)
+#define CAU_XOR_CA8 CAU_XOR_CA_REG(CAU,8)
+#define CAU_ROTL_CASR CAU_ROTL_CASR_REG(CAU)
+#define CAU_ROTL_CAA CAU_ROTL_CAA_REG(CAU)
+#define CAU_ROTL_CA0 CAU_ROTL_CA_REG(CAU,0)
+#define CAU_ROTL_CA1 CAU_ROTL_CA_REG(CAU,1)
+#define CAU_ROTL_CA2 CAU_ROTL_CA_REG(CAU,2)
+#define CAU_ROTL_CA3 CAU_ROTL_CA_REG(CAU,3)
+#define CAU_ROTL_CA4 CAU_ROTL_CA_REG(CAU,4)
+#define CAU_ROTL_CA5 CAU_ROTL_CA_REG(CAU,5)
+#define CAU_ROTL_CA6 CAU_ROTL_CA_REG(CAU,6)
+#define CAU_ROTL_CA7 CAU_ROTL_CA_REG(CAU,7)
+#define CAU_ROTL_CA8 CAU_ROTL_CA_REG(CAU,8)
+#define CAU_AESC_CASR CAU_AESC_CASR_REG(CAU)
+#define CAU_AESC_CAA CAU_AESC_CAA_REG(CAU)
+#define CAU_AESC_CA0 CAU_AESC_CA_REG(CAU,0)
+#define CAU_AESC_CA1 CAU_AESC_CA_REG(CAU,1)
+#define CAU_AESC_CA2 CAU_AESC_CA_REG(CAU,2)
+#define CAU_AESC_CA3 CAU_AESC_CA_REG(CAU,3)
+#define CAU_AESC_CA4 CAU_AESC_CA_REG(CAU,4)
+#define CAU_AESC_CA5 CAU_AESC_CA_REG(CAU,5)
+#define CAU_AESC_CA6 CAU_AESC_CA_REG(CAU,6)
+#define CAU_AESC_CA7 CAU_AESC_CA_REG(CAU,7)
+#define CAU_AESC_CA8 CAU_AESC_CA_REG(CAU,8)
+#define CAU_AESIC_CASR CAU_AESIC_CASR_REG(CAU)
+#define CAU_AESIC_CAA CAU_AESIC_CAA_REG(CAU)
+#define CAU_AESIC_CA0 CAU_AESIC_CA_REG(CAU,0)
+#define CAU_AESIC_CA1 CAU_AESIC_CA_REG(CAU,1)
+#define CAU_AESIC_CA2 CAU_AESIC_CA_REG(CAU,2)
+#define CAU_AESIC_CA3 CAU_AESIC_CA_REG(CAU,3)
+#define CAU_AESIC_CA4 CAU_AESIC_CA_REG(CAU,4)
+#define CAU_AESIC_CA5 CAU_AESIC_CA_REG(CAU,5)
+#define CAU_AESIC_CA6 CAU_AESIC_CA_REG(CAU,6)
+#define CAU_AESIC_CA7 CAU_AESIC_CA_REG(CAU,7)
+#define CAU_AESIC_CA8 CAU_AESIC_CA_REG(CAU,8)
+
+/* CAU - Register array accessors */
+#define CAU_DIRECT(index) CAU_DIRECT_REG(CAU,index)
+#define CAU_LDR_CA(index) CAU_LDR_CA_REG(CAU,index)
+#define CAU_STR_CA(index) CAU_STR_CA_REG(CAU,index)
+#define CAU_ADR_CA(index) CAU_ADR_CA_REG(CAU,index)
+#define CAU_RADR_CA(index) CAU_RADR_CA_REG(CAU,index)
+#define CAU_XOR_CA(index) CAU_XOR_CA_REG(CAU,index)
+#define CAU_ROTL_CA(index) CAU_ROTL_CA_REG(CAU,index)
+#define CAU_AESC_CA(index) CAU_AESC_CA_REG(CAU,index)
+#define CAU_AESIC_CA(index) CAU_AESIC_CA_REG(CAU,index)
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CAU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
+ __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
+ __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
+ __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
+ __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
+ __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
+} CMP_Type, *CMP_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- CMP - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
+ * @{
+ */
+
+
+/* CMP - Register accessors */
+#define CMP_CR0_REG(base) ((base)->CR0)
+#define CMP_CR1_REG(base) ((base)->CR1)
+#define CMP_FPR_REG(base) ((base)->FPR)
+#define CMP_SCR_REG(base) ((base)->SCR)
+#define CMP_DACCR_REG(base) ((base)->DACCR)
+#define CMP_MUXCR_REG(base) ((base)->MUXCR)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/* CR0 Bit Fields */
+#define CMP_CR0_HYSTCTR_MASK 0x3u
+#define CMP_CR0_HYSTCTR_SHIFT 0
+#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK 0x70u
+#define CMP_CR0_FILTER_CNT_SHIFT 4
+#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
+/* CR1 Bit Fields */
+#define CMP_CR1_EN_MASK 0x1u
+#define CMP_CR1_EN_SHIFT 0
+#define CMP_CR1_OPE_MASK 0x2u
+#define CMP_CR1_OPE_SHIFT 1
+#define CMP_CR1_COS_MASK 0x4u
+#define CMP_CR1_COS_SHIFT 2
+#define CMP_CR1_INV_MASK 0x8u
+#define CMP_CR1_INV_SHIFT 3
+#define CMP_CR1_PMODE_MASK 0x10u
+#define CMP_CR1_PMODE_SHIFT 4
+#define CMP_CR1_WE_MASK 0x40u
+#define CMP_CR1_WE_SHIFT 6
+#define CMP_CR1_SE_MASK 0x80u
+#define CMP_CR1_SE_SHIFT 7
+/* FPR Bit Fields */
+#define CMP_FPR_FILT_PER_MASK 0xFFu
+#define CMP_FPR_FILT_PER_SHIFT 0
+#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
+/* SCR Bit Fields */
+#define CMP_SCR_COUT_MASK 0x1u
+#define CMP_SCR_COUT_SHIFT 0
+#define CMP_SCR_CFF_MASK 0x2u
+#define CMP_SCR_CFF_SHIFT 1
+#define CMP_SCR_CFR_MASK 0x4u
+#define CMP_SCR_CFR_SHIFT 2
+#define CMP_SCR_IEF_MASK 0x8u
+#define CMP_SCR_IEF_SHIFT 3
+#define CMP_SCR_IER_MASK 0x10u
+#define CMP_SCR_IER_SHIFT 4
+#define CMP_SCR_DMAEN_MASK 0x40u
+#define CMP_SCR_DMAEN_SHIFT 6
+/* DACCR Bit Fields */
+#define CMP_DACCR_VOSEL_MASK 0x3Fu
+#define CMP_DACCR_VOSEL_SHIFT 0
+#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK 0x40u
+#define CMP_DACCR_VRSEL_SHIFT 6
+#define CMP_DACCR_DACEN_MASK 0x80u
+#define CMP_DACCR_DACEN_SHIFT 7
+/* MUXCR Bit Fields */
+#define CMP_MUXCR_MSEL_MASK 0x7u
+#define CMP_MUXCR_MSEL_SHIFT 0
+#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK 0x38u
+#define CMP_MUXCR_PSEL_SHIFT 3
+#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_PSTM_MASK 0x80u
+#define CMP_MUXCR_PSTM_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0 ((CMP_Type *)CMP0_BASE)
+#define CMP0_BASE_PTR (CMP0)
+/** Peripheral CMP1 base address */
+#define CMP1_BASE (0x40073008u)
+/** Peripheral CMP1 base pointer */
+#define CMP1 ((CMP_Type *)CMP1_BASE)
+#define CMP1_BASE_PTR (CMP1)
+/** Peripheral CMP2 base address */
+#define CMP2_BASE (0x40073010u)
+/** Peripheral CMP2 base pointer */
+#define CMP2 ((CMP_Type *)CMP2_BASE)
+#define CMP2_BASE_PTR (CMP2)
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASES { CMP0, CMP1, CMP2 }
+
+/* ----------------------------------------------------------------------------
+ -- CMP - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
+ * @{
+ */
+
+
+/* CMP - Register instance definitions */
+/* CMP0 */
+#define CMP0_CR0 CMP_CR0_REG(CMP0)
+#define CMP0_CR1 CMP_CR1_REG(CMP0)
+#define CMP0_FPR CMP_FPR_REG(CMP0)
+#define CMP0_SCR CMP_SCR_REG(CMP0)
+#define CMP0_DACCR CMP_DACCR_REG(CMP0)
+#define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
+/* CMP1 */
+#define CMP1_CR0 CMP_CR0_REG(CMP1)
+#define CMP1_CR1 CMP_CR1_REG(CMP1)
+#define CMP1_FPR CMP_FPR_REG(CMP1)
+#define CMP1_SCR CMP_SCR_REG(CMP1)
+#define CMP1_DACCR CMP_DACCR_REG(CMP1)
+#define CMP1_MUXCR CMP_MUXCR_REG(CMP1)
+/* CMP2 */
+#define CMP2_CR0 CMP_CR0_REG(CMP2)
+#define CMP2_CR1 CMP_CR1_REG(CMP2)
+#define CMP2_FPR CMP_FPR_REG(CMP2)
+#define CMP2_SCR CMP_SCR_REG(CMP2)
+#define CMP2_DACCR CMP_DACCR_REG(CMP2)
+#define CMP2_MUXCR CMP_MUXCR_REG(CMP2)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
+ * @{
+ */
+
+/** CMT - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
+ __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
+ __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
+ __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
+ __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
+ __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
+ __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
+ __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
+ __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
+ __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
+ __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
+ __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */
+} CMT_Type, *CMT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- CMT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
+ * @{
+ */
+
+
+/* CMT - Register accessors */
+#define CMT_CGH1_REG(base) ((base)->CGH1)
+#define CMT_CGL1_REG(base) ((base)->CGL1)
+#define CMT_CGH2_REG(base) ((base)->CGH2)
+#define CMT_CGL2_REG(base) ((base)->CGL2)
+#define CMT_OC_REG(base) ((base)->OC)
+#define CMT_MSC_REG(base) ((base)->MSC)
+#define CMT_CMD1_REG(base) ((base)->CMD1)
+#define CMT_CMD2_REG(base) ((base)->CMD2)
+#define CMT_CMD3_REG(base) ((base)->CMD3)
+#define CMT_CMD4_REG(base) ((base)->CMD4)
+#define CMT_PPS_REG(base) ((base)->PPS)
+#define CMT_DMA_REG(base) ((base)->DMA)
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Masks CMT Register Masks
+ * @{
+ */
+
+/* CGH1 Bit Fields */
+#define CMT_CGH1_PH_MASK 0xFFu
+#define CMT_CGH1_PH_SHIFT 0
+#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
+/* CGL1 Bit Fields */
+#define CMT_CGL1_PL_MASK 0xFFu
+#define CMT_CGL1_PL_SHIFT 0
+#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
+/* CGH2 Bit Fields */
+#define CMT_CGH2_SH_MASK 0xFFu
+#define CMT_CGH2_SH_SHIFT 0
+#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
+/* CGL2 Bit Fields */
+#define CMT_CGL2_SL_MASK 0xFFu
+#define CMT_CGL2_SL_SHIFT 0
+#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
+/* OC Bit Fields */
+#define CMT_OC_IROPEN_MASK 0x20u
+#define CMT_OC_IROPEN_SHIFT 5
+#define CMT_OC_CMTPOL_MASK 0x40u
+#define CMT_OC_CMTPOL_SHIFT 6
+#define CMT_OC_IROL_MASK 0x80u
+#define CMT_OC_IROL_SHIFT 7
+/* MSC Bit Fields */
+#define CMT_MSC_MCGEN_MASK 0x1u
+#define CMT_MSC_MCGEN_SHIFT 0
+#define CMT_MSC_EOCIE_MASK 0x2u
+#define CMT_MSC_EOCIE_SHIFT 1
+#define CMT_MSC_FSK_MASK 0x4u
+#define CMT_MSC_FSK_SHIFT 2
+#define CMT_MSC_BASE_MASK 0x8u
+#define CMT_MSC_BASE_SHIFT 3
+#define CMT_MSC_EXSPC_MASK 0x10u
+#define CMT_MSC_EXSPC_SHIFT 4
+#define CMT_MSC_CMTDIV_MASK 0x60u
+#define CMT_MSC_CMTDIV_SHIFT 5
+#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
+#define CMT_MSC_EOCF_MASK 0x80u
+#define CMT_MSC_EOCF_SHIFT 7
+/* CMD1 Bit Fields */
+#define CMT_CMD1_MB_MASK 0xFFu
+#define CMT_CMD1_MB_SHIFT 0
+#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
+/* CMD2 Bit Fields */
+#define CMT_CMD2_MB_MASK 0xFFu
+#define CMT_CMD2_MB_SHIFT 0
+#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
+/* CMD3 Bit Fields */
+#define CMT_CMD3_SB_MASK 0xFFu
+#define CMT_CMD3_SB_SHIFT 0
+#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
+/* CMD4 Bit Fields */
+#define CMT_CMD4_SB_MASK 0xFFu
+#define CMT_CMD4_SB_SHIFT 0
+#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
+/* PPS Bit Fields */
+#define CMT_PPS_PPSDIV_MASK 0xFu
+#define CMT_PPS_PPSDIV_SHIFT 0
+#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
+/* DMA Bit Fields */
+#define CMT_DMA_DMA_MASK 0x1u
+#define CMT_DMA_DMA_SHIFT 0
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Masks */
+
+
+/* CMT - Peripheral instance base addresses */
+/** Peripheral CMT base address */
+#define CMT_BASE (0x40062000u)
+/** Peripheral CMT base pointer */
+#define CMT ((CMT_Type *)CMT_BASE)
+#define CMT_BASE_PTR (CMT)
+/** Array initializer of CMT peripheral base pointers */
+#define CMT_BASES { CMT }
+
+/* ----------------------------------------------------------------------------
+ -- CMT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
+ * @{
+ */
+
+
+/* CMT - Register instance definitions */
+/* CMT */
+#define CMT_CGH1 CMT_CGH1_REG(CMT)
+#define CMT_CGL1 CMT_CGL1_REG(CMT)
+#define CMT_CGH2 CMT_CGH2_REG(CMT)
+#define CMT_CGL2 CMT_CGL2_REG(CMT)
+#define CMT_OC CMT_OC_REG(CMT)
+#define CMT_MSC CMT_MSC_REG(CMT)
+#define CMT_CMD1 CMT_CMD1_REG(CMT)
+#define CMT_CMD2 CMT_CMD2_REG(CMT)
+#define CMT_CMD3 CMT_CMD3_REG(CMT)
+#define CMT_CMD4 CMT_CMD4_REG(CMT)
+#define CMT_PPS CMT_PPS_REG(CMT)
+#define CMT_DMA CMT_DMA_REG(CMT)
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CMT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CRC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+ union { /* offset: 0x0 */
+ struct { /* offset: 0x0 */
+ __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
+ __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
+ } ACCESS16BIT;
+ __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
+ struct { /* offset: 0x0 */
+ __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
+ __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
+ __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
+ __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
+ } ACCESS8BIT;
+ };
+ union { /* offset: 0x4 */
+ struct { /* offset: 0x4 */
+ __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
+ __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
+ } GPOLY_ACCESS16BIT;
+ __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
+ struct { /* offset: 0x4 */
+ __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
+ __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
+ __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
+ __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
+ } GPOLY_ACCESS8BIT;
+ };
+ union { /* offset: 0x8 */
+ __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
+ struct { /* offset: 0x8 */
+ uint8_t RESERVED_0[3];
+ __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
+ } CTRL_ACCESS8BIT;
+ };
+} CRC_Type, *CRC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- CRC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
+ * @{
+ */
+
+
+/* CRC - Register accessors */
+#define CRC_DATAL_REG(base) ((base)->ACCESS16BIT.DATAL)
+#define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH)
+#define CRC_DATA_REG(base) ((base)->DATA)
+#define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL)
+#define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU)
+#define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL)
+#define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU)
+#define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL)
+#define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH)
+#define CRC_GPOLY_REG(base) ((base)->GPOLY)
+#define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
+#define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
+#define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
+#define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
+#define CRC_CTRL_REG(base) ((base)->CTRL)
+#define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- CRC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/* DATAL Bit Fields */
+#define CRC_DATAL_DATAL_MASK 0xFFFFu
+#define CRC_DATAL_DATAL_SHIFT 0
+#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
+/* DATAH Bit Fields */
+#define CRC_DATAH_DATAH_MASK 0xFFFFu
+#define CRC_DATAH_DATAH_SHIFT 0
+#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
+/* DATA Bit Fields */
+#define CRC_DATA_LL_MASK 0xFFu
+#define CRC_DATA_LL_SHIFT 0
+#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
+#define CRC_DATA_LU_MASK 0xFF00u
+#define CRC_DATA_LU_SHIFT 8
+#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
+#define CRC_DATA_HL_MASK 0xFF0000u
+#define CRC_DATA_HL_SHIFT 16
+#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
+#define CRC_DATA_HU_MASK 0xFF000000u
+#define CRC_DATA_HU_SHIFT 24
+#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
+/* DATALL Bit Fields */
+#define CRC_DATALL_DATALL_MASK 0xFFu
+#define CRC_DATALL_DATALL_SHIFT 0
+#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
+/* DATALU Bit Fields */
+#define CRC_DATALU_DATALU_MASK 0xFFu
+#define CRC_DATALU_DATALU_SHIFT 0
+#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
+/* DATAHL Bit Fields */
+#define CRC_DATAHL_DATAHL_MASK 0xFFu
+#define CRC_DATAHL_DATAHL_SHIFT 0
+#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
+/* DATAHU Bit Fields */
+#define CRC_DATAHU_DATAHU_MASK 0xFFu
+#define CRC_DATAHU_DATAHU_SHIFT 0
+#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
+/* GPOLYL Bit Fields */
+#define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
+#define CRC_GPOLYL_GPOLYL_SHIFT 0
+#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
+/* GPOLYH Bit Fields */
+#define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
+#define CRC_GPOLYH_GPOLYH_SHIFT 0
+#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
+/* GPOLY Bit Fields */
+#define CRC_GPOLY_LOW_MASK 0xFFFFu
+#define CRC_GPOLY_LOW_SHIFT 0
+#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
+#define CRC_GPOLY_HIGH_SHIFT 16
+#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
+/* GPOLYLL Bit Fields */
+#define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
+#define CRC_GPOLYLL_GPOLYLL_SHIFT 0
+#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
+/* GPOLYLU Bit Fields */
+#define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
+#define CRC_GPOLYLU_GPOLYLU_SHIFT 0
+#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
+/* GPOLYHL Bit Fields */
+#define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
+#define CRC_GPOLYHL_GPOLYHL_SHIFT 0
+#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
+/* GPOLYHU Bit Fields */
+#define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
+#define CRC_GPOLYHU_GPOLYHU_SHIFT 0
+#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
+/* CTRL Bit Fields */
+#define CRC_CTRL_TCRC_MASK 0x1000000u
+#define CRC_CTRL_TCRC_SHIFT 24
+#define CRC_CTRL_WAS_MASK 0x2000000u
+#define CRC_CTRL_WAS_SHIFT 25
+#define CRC_CTRL_FXOR_MASK 0x4000000u
+#define CRC_CTRL_FXOR_SHIFT 26
+#define CRC_CTRL_TOTR_MASK 0x30000000u
+#define CRC_CTRL_TOTR_SHIFT 28
+#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK 0xC0000000u
+#define CRC_CTRL_TOT_SHIFT 30
+#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
+/* CTRLHU Bit Fields */
+#define CRC_CTRLHU_TCRC_MASK 0x1u
+#define CRC_CTRLHU_TCRC_SHIFT 0
+#define CRC_CTRLHU_WAS_MASK 0x2u
+#define CRC_CTRLHU_WAS_SHIFT 1
+#define CRC_CTRLHU_FXOR_MASK 0x4u
+#define CRC_CTRLHU_FXOR_SHIFT 2
+#define CRC_CTRLHU_TOTR_MASK 0x30u
+#define CRC_CTRLHU_TOTR_SHIFT 4
+#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOT_MASK 0xC0u
+#define CRC_CTRLHU_TOT_SHIFT 6
+#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC base address */
+#define CRC_BASE (0x40032000u)
+/** Peripheral CRC base pointer */
+#define CRC0 ((CRC_Type *)CRC_BASE)
+#define CRC_BASE_PTR (CRC0)
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASES { CRC0 }
+
+/* ----------------------------------------------------------------------------
+ -- CRC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
+ * @{
+ */
+
+
+/* CRC - Register instance definitions */
+/* CRC */
+#define CRC_DATA CRC_DATA_REG(CRC0)
+#define CRC_DATAL CRC_DATAL_REG(CRC0)
+#define CRC_DATALL CRC_DATALL_REG(CRC0)
+#define CRC_DATALU CRC_DATALU_REG(CRC0)
+#define CRC_DATAH CRC_DATAH_REG(CRC0)
+#define CRC_DATAHL CRC_DATAHL_REG(CRC0)
+#define CRC_DATAHU CRC_DATAHU_REG(CRC0)
+#define CRC_GPOLY CRC_GPOLY_REG(CRC0)
+#define CRC_GPOLYL CRC_GPOLYL_REG(CRC0)
+#define CRC_GPOLYLL CRC_GPOLYLL_REG(CRC0)
+#define CRC_GPOLYLU CRC_GPOLYLU_REG(CRC0)
+#define CRC_GPOLYH CRC_GPOLYH_REG(CRC0)
+#define CRC_GPOLYHL CRC_GPOLYHL_REG(CRC0)
+#define CRC_GPOLYHU CRC_GPOLYHU_REG(CRC0)
+#define CRC_CTRL CRC_CTRL_REG(CRC0)
+#define CRC_CTRLHU CRC_CTRLHU_REG(CRC0)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DAC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+ } DAT[16];
+ __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
+ __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
+ __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
+ __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type, *DAC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- DAC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @{
+ */
+
+
+/* DAC - Register accessors */
+#define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
+#define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
+#define DAC_SR_REG(base) ((base)->SR)
+#define DAC_C0_REG(base) ((base)->C0)
+#define DAC_C1_REG(base) ((base)->C1)
+#define DAC_C2_REG(base) ((base)->C2)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- DAC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/* DATL Bit Fields */
+#define DAC_DATL_DATA0_MASK 0xFFu
+#define DAC_DATL_DATA0_SHIFT 0
+#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
+/* DATH Bit Fields */
+#define DAC_DATH_DATA1_MASK 0xFu
+#define DAC_DATH_DATA1_SHIFT 0
+#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
+/* SR Bit Fields */
+#define DAC_SR_DACBFRPBF_MASK 0x1u
+#define DAC_SR_DACBFRPBF_SHIFT 0
+#define DAC_SR_DACBFRPTF_MASK 0x2u
+#define DAC_SR_DACBFRPTF_SHIFT 1
+#define DAC_SR_DACBFWMF_MASK 0x4u
+#define DAC_SR_DACBFWMF_SHIFT 2
+/* C0 Bit Fields */
+#define DAC_C0_DACBBIEN_MASK 0x1u
+#define DAC_C0_DACBBIEN_SHIFT 0
+#define DAC_C0_DACBTIEN_MASK 0x2u
+#define DAC_C0_DACBTIEN_SHIFT 1
+#define DAC_C0_DACBWIEN_MASK 0x4u
+#define DAC_C0_DACBWIEN_SHIFT 2
+#define DAC_C0_LPEN_MASK 0x8u
+#define DAC_C0_LPEN_SHIFT 3
+#define DAC_C0_DACSWTRG_MASK 0x10u
+#define DAC_C0_DACSWTRG_SHIFT 4
+#define DAC_C0_DACTRGSEL_MASK 0x20u
+#define DAC_C0_DACTRGSEL_SHIFT 5
+#define DAC_C0_DACRFS_MASK 0x40u
+#define DAC_C0_DACRFS_SHIFT 6
+#define DAC_C0_DACEN_MASK 0x80u
+#define DAC_C0_DACEN_SHIFT 7
+/* C1 Bit Fields */
+#define DAC_C1_DACBFEN_MASK 0x1u
+#define DAC_C1_DACBFEN_SHIFT 0
+#define DAC_C1_DACBFMD_MASK 0x6u
+#define DAC_C1_DACBFMD_SHIFT 1
+#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
+#define DAC_C1_DACBFWM_MASK 0x18u
+#define DAC_C1_DACBFWM_SHIFT 3
+#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
+#define DAC_C1_DMAEN_MASK 0x80u
+#define DAC_C1_DMAEN_SHIFT 7
+/* C2 Bit Fields */
+#define DAC_C2_DACBFUP_MASK 0xFu
+#define DAC_C2_DACBFUP_SHIFT 0
+#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
+#define DAC_C2_DACBFRP_MASK 0xF0u
+#define DAC_C2_DACBFRP_SHIFT 4
+#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE (0x400CC000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0 ((DAC_Type *)DAC0_BASE)
+#define DAC0_BASE_PTR (DAC0)
+/** Peripheral DAC1 base address */
+#define DAC1_BASE (0x400CD000u)
+/** Peripheral DAC1 base pointer */
+#define DAC1 ((DAC_Type *)DAC1_BASE)
+#define DAC1_BASE_PTR (DAC1)
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASES { DAC0, DAC1 }
+
+/* ----------------------------------------------------------------------------
+ -- DAC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @{
+ */
+
+
+/* DAC - Register instance definitions */
+/* DAC0 */
+#define DAC0_DAT0L DAC_DATL_REG(DAC0,0)
+#define DAC0_DAT0H DAC_DATH_REG(DAC0,0)
+#define DAC0_DAT1L DAC_DATL_REG(DAC0,1)
+#define DAC0_DAT1H DAC_DATH_REG(DAC0,1)
+#define DAC0_DAT2L DAC_DATL_REG(DAC0,2)
+#define DAC0_DAT2H DAC_DATH_REG(DAC0,2)
+#define DAC0_DAT3L DAC_DATL_REG(DAC0,3)
+#define DAC0_DAT3H DAC_DATH_REG(DAC0,3)
+#define DAC0_DAT4L DAC_DATL_REG(DAC0,4)
+#define DAC0_DAT4H DAC_DATH_REG(DAC0,4)
+#define DAC0_DAT5L DAC_DATL_REG(DAC0,5)
+#define DAC0_DAT5H DAC_DATH_REG(DAC0,5)
+#define DAC0_DAT6L DAC_DATL_REG(DAC0,6)
+#define DAC0_DAT6H DAC_DATH_REG(DAC0,6)
+#define DAC0_DAT7L DAC_DATL_REG(DAC0,7)
+#define DAC0_DAT7H DAC_DATH_REG(DAC0,7)
+#define DAC0_DAT8L DAC_DATL_REG(DAC0,8)
+#define DAC0_DAT8H DAC_DATH_REG(DAC0,8)
+#define DAC0_DAT9L DAC_DATL_REG(DAC0,9)
+#define DAC0_DAT9H DAC_DATH_REG(DAC0,9)
+#define DAC0_DAT10L DAC_DATL_REG(DAC0,10)
+#define DAC0_DAT10H DAC_DATH_REG(DAC0,10)
+#define DAC0_DAT11L DAC_DATL_REG(DAC0,11)
+#define DAC0_DAT11H DAC_DATH_REG(DAC0,11)
+#define DAC0_DAT12L DAC_DATL_REG(DAC0,12)
+#define DAC0_DAT12H DAC_DATH_REG(DAC0,12)
+#define DAC0_DAT13L DAC_DATL_REG(DAC0,13)
+#define DAC0_DAT13H DAC_DATH_REG(DAC0,13)
+#define DAC0_DAT14L DAC_DATL_REG(DAC0,14)
+#define DAC0_DAT14H DAC_DATH_REG(DAC0,14)
+#define DAC0_DAT15L DAC_DATL_REG(DAC0,15)
+#define DAC0_DAT15H DAC_DATH_REG(DAC0,15)
+#define DAC0_SR DAC_SR_REG(DAC0)
+#define DAC0_C0 DAC_C0_REG(DAC0)
+#define DAC0_C1 DAC_C1_REG(DAC0)
+#define DAC0_C2 DAC_C2_REG(DAC0)
+/* DAC1 */
+#define DAC1_DAT0L DAC_DATL_REG(DAC1,0)
+#define DAC1_DAT0H DAC_DATH_REG(DAC1,0)
+#define DAC1_DAT1L DAC_DATL_REG(DAC1,1)
+#define DAC1_DAT1H DAC_DATH_REG(DAC1,1)
+#define DAC1_DAT2L DAC_DATL_REG(DAC1,2)
+#define DAC1_DAT2H DAC_DATH_REG(DAC1,2)
+#define DAC1_DAT3L DAC_DATL_REG(DAC1,3)
+#define DAC1_DAT3H DAC_DATH_REG(DAC1,3)
+#define DAC1_DAT4L DAC_DATL_REG(DAC1,4)
+#define DAC1_DAT4H DAC_DATH_REG(DAC1,4)
+#define DAC1_DAT5L DAC_DATL_REG(DAC1,5)
+#define DAC1_DAT5H DAC_DATH_REG(DAC1,5)
+#define DAC1_DAT6L DAC_DATL_REG(DAC1,6)
+#define DAC1_DAT6H DAC_DATH_REG(DAC1,6)
+#define DAC1_DAT7L DAC_DATL_REG(DAC1,7)
+#define DAC1_DAT7H DAC_DATH_REG(DAC1,7)
+#define DAC1_DAT8L DAC_DATL_REG(DAC1,8)
+#define DAC1_DAT8H DAC_DATH_REG(DAC1,8)
+#define DAC1_DAT9L DAC_DATL_REG(DAC1,9)
+#define DAC1_DAT9H DAC_DATH_REG(DAC1,9)
+#define DAC1_DAT10L DAC_DATL_REG(DAC1,10)
+#define DAC1_DAT10H DAC_DATH_REG(DAC1,10)
+#define DAC1_DAT11L DAC_DATL_REG(DAC1,11)
+#define DAC1_DAT11H DAC_DATH_REG(DAC1,11)
+#define DAC1_DAT12L DAC_DATL_REG(DAC1,12)
+#define DAC1_DAT12H DAC_DATH_REG(DAC1,12)
+#define DAC1_DAT13L DAC_DATL_REG(DAC1,13)
+#define DAC1_DAT13H DAC_DATH_REG(DAC1,13)
+#define DAC1_DAT14L DAC_DATL_REG(DAC1,14)
+#define DAC1_DAT14H DAC_DATH_REG(DAC1,14)
+#define DAC1_DAT15L DAC_DATL_REG(DAC1,15)
+#define DAC1_DAT15H DAC_DATH_REG(DAC1,15)
+#define DAC1_SR DAC_SR_REG(DAC1)
+#define DAC1_C0 DAC_C0_REG(DAC1)
+#define DAC1_C1 DAC_C1_REG(DAC1)
+#define DAC1_C2 DAC_C2_REG(DAC1)
+
+/* DAC - Register array accessors */
+#define DAC0_DATL(index) DAC_DATL_REG(DAC0,index)
+#define DAC1_DATL(index) DAC_DATL_REG(DAC1,index)
+#define DAC0_DATH(index) DAC_DATH_REG(DAC0,index)
+#define DAC1_DATH(index) DAC_DATH_REG(DAC1,index)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CR; /**< Control Register, offset: 0x0 */
+ __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
+ __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
+ __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
+ __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
+ __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
+ __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
+ __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
+ __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
+ __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
+ uint8_t RESERVED_4[4];
+ __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
+ uint8_t RESERVED_5[200];
+ __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
+ __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
+ __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
+ __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
+ __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
+ __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
+ __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
+ __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
+ __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
+ __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
+ __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
+ __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
+ __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
+ __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
+ __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
+ __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
+ uint8_t RESERVED_6[3824];
+ struct { /* offset: 0x1000, array step: 0x20 */
+ __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
+ __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
+ __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
+ union { /* offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
+ };
+ __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
+ __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
+ __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
+ union { /* offset: 0x1016, array step: 0x20 */
+ __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
+ __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
+ };
+ __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
+ __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
+ union { /* offset: 0x101E, array step: 0x20 */
+ __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
+ __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
+ };
+ } TCD[16];
+} DMA_Type, *DMA_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- DMA - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
+ * @{
+ */
+
+
+/* DMA - Register accessors */
+#define DMA_CR_REG(base) ((base)->CR)
+#define DMA_ES_REG(base) ((base)->ES)
+#define DMA_ERQ_REG(base) ((base)->ERQ)
+#define DMA_EEI_REG(base) ((base)->EEI)
+#define DMA_CEEI_REG(base) ((base)->CEEI)
+#define DMA_SEEI_REG(base) ((base)->SEEI)
+#define DMA_CERQ_REG(base) ((base)->CERQ)
+#define DMA_SERQ_REG(base) ((base)->SERQ)
+#define DMA_CDNE_REG(base) ((base)->CDNE)
+#define DMA_SSRT_REG(base) ((base)->SSRT)
+#define DMA_CERR_REG(base) ((base)->CERR)
+#define DMA_CINT_REG(base) ((base)->CINT)
+#define DMA_INT_REG(base) ((base)->INT)
+#define DMA_ERR_REG(base) ((base)->ERR)
+#define DMA_HRS_REG(base) ((base)->HRS)
+#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3)
+#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2)
+#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1)
+#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0)
+#define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7)
+#define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6)
+#define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5)
+#define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4)
+#define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11)
+#define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10)
+#define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9)
+#define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8)
+#define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15)
+#define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14)
+#define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13)
+#define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12)
+#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR)
+#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF)
+#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR)
+#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO)
+#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO)
+#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES)
+#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST)
+#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR)
+#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF)
+#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO)
+#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES)
+#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA)
+#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR)
+#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO)
+#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define DMA_CR_EDBG_MASK 0x2u
+#define DMA_CR_EDBG_SHIFT 1
+#define DMA_CR_ERCA_MASK 0x4u
+#define DMA_CR_ERCA_SHIFT 2
+#define DMA_CR_HOE_MASK 0x10u
+#define DMA_CR_HOE_SHIFT 4
+#define DMA_CR_HALT_MASK 0x20u
+#define DMA_CR_HALT_SHIFT 5
+#define DMA_CR_CLM_MASK 0x40u
+#define DMA_CR_CLM_SHIFT 6
+#define DMA_CR_EMLM_MASK 0x80u
+#define DMA_CR_EMLM_SHIFT 7
+#define DMA_CR_ECX_MASK 0x10000u
+#define DMA_CR_ECX_SHIFT 16
+#define DMA_CR_CX_MASK 0x20000u
+#define DMA_CR_CX_SHIFT 17
+/* ES Bit Fields */
+#define DMA_ES_DBE_MASK 0x1u
+#define DMA_ES_DBE_SHIFT 0
+#define DMA_ES_SBE_MASK 0x2u
+#define DMA_ES_SBE_SHIFT 1
+#define DMA_ES_SGE_MASK 0x4u
+#define DMA_ES_SGE_SHIFT 2
+#define DMA_ES_NCE_MASK 0x8u
+#define DMA_ES_NCE_SHIFT 3
+#define DMA_ES_DOE_MASK 0x10u
+#define DMA_ES_DOE_SHIFT 4
+#define DMA_ES_DAE_MASK 0x20u
+#define DMA_ES_DAE_SHIFT 5
+#define DMA_ES_SOE_MASK 0x40u
+#define DMA_ES_SOE_SHIFT 6
+#define DMA_ES_SAE_MASK 0x80u
+#define DMA_ES_SAE_SHIFT 7
+#define DMA_ES_ERRCHN_MASK 0xF00u
+#define DMA_ES_ERRCHN_SHIFT 8
+#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
+#define DMA_ES_CPE_MASK 0x4000u
+#define DMA_ES_CPE_SHIFT 14
+#define DMA_ES_ECX_MASK 0x10000u
+#define DMA_ES_ECX_SHIFT 16
+#define DMA_ES_VLD_MASK 0x80000000u
+#define DMA_ES_VLD_SHIFT 31
+/* ERQ Bit Fields */
+#define DMA_ERQ_ERQ0_MASK 0x1u
+#define DMA_ERQ_ERQ0_SHIFT 0
+#define DMA_ERQ_ERQ1_MASK 0x2u
+#define DMA_ERQ_ERQ1_SHIFT 1
+#define DMA_ERQ_ERQ2_MASK 0x4u
+#define DMA_ERQ_ERQ2_SHIFT 2
+#define DMA_ERQ_ERQ3_MASK 0x8u
+#define DMA_ERQ_ERQ3_SHIFT 3
+#define DMA_ERQ_ERQ4_MASK 0x10u
+#define DMA_ERQ_ERQ4_SHIFT 4
+#define DMA_ERQ_ERQ5_MASK 0x20u
+#define DMA_ERQ_ERQ5_SHIFT 5
+#define DMA_ERQ_ERQ6_MASK 0x40u
+#define DMA_ERQ_ERQ6_SHIFT 6
+#define DMA_ERQ_ERQ7_MASK 0x80u
+#define DMA_ERQ_ERQ7_SHIFT 7
+#define DMA_ERQ_ERQ8_MASK 0x100u
+#define DMA_ERQ_ERQ8_SHIFT 8
+#define DMA_ERQ_ERQ9_MASK 0x200u
+#define DMA_ERQ_ERQ9_SHIFT 9
+#define DMA_ERQ_ERQ10_MASK 0x400u
+#define DMA_ERQ_ERQ10_SHIFT 10
+#define DMA_ERQ_ERQ11_MASK 0x800u
+#define DMA_ERQ_ERQ11_SHIFT 11
+#define DMA_ERQ_ERQ12_MASK 0x1000u
+#define DMA_ERQ_ERQ12_SHIFT 12
+#define DMA_ERQ_ERQ13_MASK 0x2000u
+#define DMA_ERQ_ERQ13_SHIFT 13
+#define DMA_ERQ_ERQ14_MASK 0x4000u
+#define DMA_ERQ_ERQ14_SHIFT 14
+#define DMA_ERQ_ERQ15_MASK 0x8000u
+#define DMA_ERQ_ERQ15_SHIFT 15
+/* EEI Bit Fields */
+#define DMA_EEI_EEI0_MASK 0x1u
+#define DMA_EEI_EEI0_SHIFT 0
+#define DMA_EEI_EEI1_MASK 0x2u
+#define DMA_EEI_EEI1_SHIFT 1
+#define DMA_EEI_EEI2_MASK 0x4u
+#define DMA_EEI_EEI2_SHIFT 2
+#define DMA_EEI_EEI3_MASK 0x8u
+#define DMA_EEI_EEI3_SHIFT 3
+#define DMA_EEI_EEI4_MASK 0x10u
+#define DMA_EEI_EEI4_SHIFT 4
+#define DMA_EEI_EEI5_MASK 0x20u
+#define DMA_EEI_EEI5_SHIFT 5
+#define DMA_EEI_EEI6_MASK 0x40u
+#define DMA_EEI_EEI6_SHIFT 6
+#define DMA_EEI_EEI7_MASK 0x80u
+#define DMA_EEI_EEI7_SHIFT 7
+#define DMA_EEI_EEI8_MASK 0x100u
+#define DMA_EEI_EEI8_SHIFT 8
+#define DMA_EEI_EEI9_MASK 0x200u
+#define DMA_EEI_EEI9_SHIFT 9
+#define DMA_EEI_EEI10_MASK 0x400u
+#define DMA_EEI_EEI10_SHIFT 10
+#define DMA_EEI_EEI11_MASK 0x800u
+#define DMA_EEI_EEI11_SHIFT 11
+#define DMA_EEI_EEI12_MASK 0x1000u
+#define DMA_EEI_EEI12_SHIFT 12
+#define DMA_EEI_EEI13_MASK 0x2000u
+#define DMA_EEI_EEI13_SHIFT 13
+#define DMA_EEI_EEI14_MASK 0x4000u
+#define DMA_EEI_EEI14_SHIFT 14
+#define DMA_EEI_EEI15_MASK 0x8000u
+#define DMA_EEI_EEI15_SHIFT 15
+/* CEEI Bit Fields */
+#define DMA_CEEI_CEEI_MASK 0xFu
+#define DMA_CEEI_CEEI_SHIFT 0
+#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CAEE_MASK 0x40u
+#define DMA_CEEI_CAEE_SHIFT 6
+#define DMA_CEEI_NOP_MASK 0x80u
+#define DMA_CEEI_NOP_SHIFT 7
+/* SEEI Bit Fields */
+#define DMA_SEEI_SEEI_MASK 0xFu
+#define DMA_SEEI_SEEI_SHIFT 0
+#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SAEE_MASK 0x40u
+#define DMA_SEEI_SAEE_SHIFT 6
+#define DMA_SEEI_NOP_MASK 0x80u
+#define DMA_SEEI_NOP_SHIFT 7
+/* CERQ Bit Fields */
+#define DMA_CERQ_CERQ_MASK 0xFu
+#define DMA_CERQ_CERQ_SHIFT 0
+#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CAER_MASK 0x40u
+#define DMA_CERQ_CAER_SHIFT 6
+#define DMA_CERQ_NOP_MASK 0x80u
+#define DMA_CERQ_NOP_SHIFT 7
+/* SERQ Bit Fields */
+#define DMA_SERQ_SERQ_MASK 0xFu
+#define DMA_SERQ_SERQ_SHIFT 0
+#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SAER_MASK 0x40u
+#define DMA_SERQ_SAER_SHIFT 6
+#define DMA_SERQ_NOP_MASK 0x80u
+#define DMA_SERQ_NOP_SHIFT 7
+/* CDNE Bit Fields */
+#define DMA_CDNE_CDNE_MASK 0xFu
+#define DMA_CDNE_CDNE_SHIFT 0
+#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CADN_MASK 0x40u
+#define DMA_CDNE_CADN_SHIFT 6
+#define DMA_CDNE_NOP_MASK 0x80u
+#define DMA_CDNE_NOP_SHIFT 7
+/* SSRT Bit Fields */
+#define DMA_SSRT_SSRT_MASK 0xFu
+#define DMA_SSRT_SSRT_SHIFT 0
+#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SAST_MASK 0x40u
+#define DMA_SSRT_SAST_SHIFT 6
+#define DMA_SSRT_NOP_MASK 0x80u
+#define DMA_SSRT_NOP_SHIFT 7
+/* CERR Bit Fields */
+#define DMA_CERR_CERR_MASK 0xFu
+#define DMA_CERR_CERR_SHIFT 0
+#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
+#define DMA_CERR_CAEI_MASK 0x40u
+#define DMA_CERR_CAEI_SHIFT 6
+#define DMA_CERR_NOP_MASK 0x80u
+#define DMA_CERR_NOP_SHIFT 7
+/* CINT Bit Fields */
+#define DMA_CINT_CINT_MASK 0xFu
+#define DMA_CINT_CINT_SHIFT 0
+#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
+#define DMA_CINT_CAIR_MASK 0x40u
+#define DMA_CINT_CAIR_SHIFT 6
+#define DMA_CINT_NOP_MASK 0x80u
+#define DMA_CINT_NOP_SHIFT 7
+/* INT Bit Fields */
+#define DMA_INT_INT0_MASK 0x1u
+#define DMA_INT_INT0_SHIFT 0
+#define DMA_INT_INT1_MASK 0x2u
+#define DMA_INT_INT1_SHIFT 1
+#define DMA_INT_INT2_MASK 0x4u
+#define DMA_INT_INT2_SHIFT 2
+#define DMA_INT_INT3_MASK 0x8u
+#define DMA_INT_INT3_SHIFT 3
+#define DMA_INT_INT4_MASK 0x10u
+#define DMA_INT_INT4_SHIFT 4
+#define DMA_INT_INT5_MASK 0x20u
+#define DMA_INT_INT5_SHIFT 5
+#define DMA_INT_INT6_MASK 0x40u
+#define DMA_INT_INT6_SHIFT 6
+#define DMA_INT_INT7_MASK 0x80u
+#define DMA_INT_INT7_SHIFT 7
+#define DMA_INT_INT8_MASK 0x100u
+#define DMA_INT_INT8_SHIFT 8
+#define DMA_INT_INT9_MASK 0x200u
+#define DMA_INT_INT9_SHIFT 9
+#define DMA_INT_INT10_MASK 0x400u
+#define DMA_INT_INT10_SHIFT 10
+#define DMA_INT_INT11_MASK 0x800u
+#define DMA_INT_INT11_SHIFT 11
+#define DMA_INT_INT12_MASK 0x1000u
+#define DMA_INT_INT12_SHIFT 12
+#define DMA_INT_INT13_MASK 0x2000u
+#define DMA_INT_INT13_SHIFT 13
+#define DMA_INT_INT14_MASK 0x4000u
+#define DMA_INT_INT14_SHIFT 14
+#define DMA_INT_INT15_MASK 0x8000u
+#define DMA_INT_INT15_SHIFT 15
+/* ERR Bit Fields */
+#define DMA_ERR_ERR0_MASK 0x1u
+#define DMA_ERR_ERR0_SHIFT 0
+#define DMA_ERR_ERR1_MASK 0x2u
+#define DMA_ERR_ERR1_SHIFT 1
+#define DMA_ERR_ERR2_MASK 0x4u
+#define DMA_ERR_ERR2_SHIFT 2
+#define DMA_ERR_ERR3_MASK 0x8u
+#define DMA_ERR_ERR3_SHIFT 3
+#define DMA_ERR_ERR4_MASK 0x10u
+#define DMA_ERR_ERR4_SHIFT 4
+#define DMA_ERR_ERR5_MASK 0x20u
+#define DMA_ERR_ERR5_SHIFT 5
+#define DMA_ERR_ERR6_MASK 0x40u
+#define DMA_ERR_ERR6_SHIFT 6
+#define DMA_ERR_ERR7_MASK 0x80u
+#define DMA_ERR_ERR7_SHIFT 7
+#define DMA_ERR_ERR8_MASK 0x100u
+#define DMA_ERR_ERR8_SHIFT 8
+#define DMA_ERR_ERR9_MASK 0x200u
+#define DMA_ERR_ERR9_SHIFT 9
+#define DMA_ERR_ERR10_MASK 0x400u
+#define DMA_ERR_ERR10_SHIFT 10
+#define DMA_ERR_ERR11_MASK 0x800u
+#define DMA_ERR_ERR11_SHIFT 11
+#define DMA_ERR_ERR12_MASK 0x1000u
+#define DMA_ERR_ERR12_SHIFT 12
+#define DMA_ERR_ERR13_MASK 0x2000u
+#define DMA_ERR_ERR13_SHIFT 13
+#define DMA_ERR_ERR14_MASK 0x4000u
+#define DMA_ERR_ERR14_SHIFT 14
+#define DMA_ERR_ERR15_MASK 0x8000u
+#define DMA_ERR_ERR15_SHIFT 15
+/* HRS Bit Fields */
+#define DMA_HRS_HRS0_MASK 0x1u
+#define DMA_HRS_HRS0_SHIFT 0
+#define DMA_HRS_HRS1_MASK 0x2u
+#define DMA_HRS_HRS1_SHIFT 1
+#define DMA_HRS_HRS2_MASK 0x4u
+#define DMA_HRS_HRS2_SHIFT 2
+#define DMA_HRS_HRS3_MASK 0x8u
+#define DMA_HRS_HRS3_SHIFT 3
+#define DMA_HRS_HRS4_MASK 0x10u
+#define DMA_HRS_HRS4_SHIFT 4
+#define DMA_HRS_HRS5_MASK 0x20u
+#define DMA_HRS_HRS5_SHIFT 5
+#define DMA_HRS_HRS6_MASK 0x40u
+#define DMA_HRS_HRS6_SHIFT 6
+#define DMA_HRS_HRS7_MASK 0x80u
+#define DMA_HRS_HRS7_SHIFT 7
+#define DMA_HRS_HRS8_MASK 0x100u
+#define DMA_HRS_HRS8_SHIFT 8
+#define DMA_HRS_HRS9_MASK 0x200u
+#define DMA_HRS_HRS9_SHIFT 9
+#define DMA_HRS_HRS10_MASK 0x400u
+#define DMA_HRS_HRS10_SHIFT 10
+#define DMA_HRS_HRS11_MASK 0x800u
+#define DMA_HRS_HRS11_SHIFT 11
+#define DMA_HRS_HRS12_MASK 0x1000u
+#define DMA_HRS_HRS12_SHIFT 12
+#define DMA_HRS_HRS13_MASK 0x2000u
+#define DMA_HRS_HRS13_SHIFT 13
+#define DMA_HRS_HRS14_MASK 0x4000u
+#define DMA_HRS_HRS14_SHIFT 14
+#define DMA_HRS_HRS15_MASK 0x8000u
+#define DMA_HRS_HRS15_SHIFT 15
+/* DCHPRI3 Bit Fields */
+#define DMA_DCHPRI3_CHPRI_MASK 0xFu
+#define DMA_DCHPRI3_CHPRI_SHIFT 0
+#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
+#define DMA_DCHPRI3_DPA_MASK 0x40u
+#define DMA_DCHPRI3_DPA_SHIFT 6
+#define DMA_DCHPRI3_ECP_MASK 0x80u
+#define DMA_DCHPRI3_ECP_SHIFT 7
+/* DCHPRI2 Bit Fields */
+#define DMA_DCHPRI2_CHPRI_MASK 0xFu
+#define DMA_DCHPRI2_CHPRI_SHIFT 0
+#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
+#define DMA_DCHPRI2_DPA_MASK 0x40u
+#define DMA_DCHPRI2_DPA_SHIFT 6
+#define DMA_DCHPRI2_ECP_MASK 0x80u
+#define DMA_DCHPRI2_ECP_SHIFT 7
+/* DCHPRI1 Bit Fields */
+#define DMA_DCHPRI1_CHPRI_MASK 0xFu
+#define DMA_DCHPRI1_CHPRI_SHIFT 0
+#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
+#define DMA_DCHPRI1_DPA_MASK 0x40u
+#define DMA_DCHPRI1_DPA_SHIFT 6
+#define DMA_DCHPRI1_ECP_MASK 0x80u
+#define DMA_DCHPRI1_ECP_SHIFT 7
+/* DCHPRI0 Bit Fields */
+#define DMA_DCHPRI0_CHPRI_MASK 0xFu
+#define DMA_DCHPRI0_CHPRI_SHIFT 0
+#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
+#define DMA_DCHPRI0_DPA_MASK 0x40u
+#define DMA_DCHPRI0_DPA_SHIFT 6
+#define DMA_DCHPRI0_ECP_MASK 0x80u
+#define DMA_DCHPRI0_ECP_SHIFT 7
+/* DCHPRI7 Bit Fields */
+#define DMA_DCHPRI7_CHPRI_MASK 0xFu
+#define DMA_DCHPRI7_CHPRI_SHIFT 0
+#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
+#define DMA_DCHPRI7_DPA_MASK 0x40u
+#define DMA_DCHPRI7_DPA_SHIFT 6
+#define DMA_DCHPRI7_ECP_MASK 0x80u
+#define DMA_DCHPRI7_ECP_SHIFT 7
+/* DCHPRI6 Bit Fields */
+#define DMA_DCHPRI6_CHPRI_MASK 0xFu
+#define DMA_DCHPRI6_CHPRI_SHIFT 0
+#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
+#define DMA_DCHPRI6_DPA_MASK 0x40u
+#define DMA_DCHPRI6_DPA_SHIFT 6
+#define DMA_DCHPRI6_ECP_MASK 0x80u
+#define DMA_DCHPRI6_ECP_SHIFT 7
+/* DCHPRI5 Bit Fields */
+#define DMA_DCHPRI5_CHPRI_MASK 0xFu
+#define DMA_DCHPRI5_CHPRI_SHIFT 0
+#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
+#define DMA_DCHPRI5_DPA_MASK 0x40u
+#define DMA_DCHPRI5_DPA_SHIFT 6
+#define DMA_DCHPRI5_ECP_MASK 0x80u
+#define DMA_DCHPRI5_ECP_SHIFT 7
+/* DCHPRI4 Bit Fields */
+#define DMA_DCHPRI4_CHPRI_MASK 0xFu
+#define DMA_DCHPRI4_CHPRI_SHIFT 0
+#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
+#define DMA_DCHPRI4_DPA_MASK 0x40u
+#define DMA_DCHPRI4_DPA_SHIFT 6
+#define DMA_DCHPRI4_ECP_MASK 0x80u
+#define DMA_DCHPRI4_ECP_SHIFT 7
+/* DCHPRI11 Bit Fields */
+#define DMA_DCHPRI11_CHPRI_MASK 0xFu
+#define DMA_DCHPRI11_CHPRI_SHIFT 0
+#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
+#define DMA_DCHPRI11_DPA_MASK 0x40u
+#define DMA_DCHPRI11_DPA_SHIFT 6
+#define DMA_DCHPRI11_ECP_MASK 0x80u
+#define DMA_DCHPRI11_ECP_SHIFT 7
+/* DCHPRI10 Bit Fields */
+#define DMA_DCHPRI10_CHPRI_MASK 0xFu
+#define DMA_DCHPRI10_CHPRI_SHIFT 0
+#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
+#define DMA_DCHPRI10_DPA_MASK 0x40u
+#define DMA_DCHPRI10_DPA_SHIFT 6
+#define DMA_DCHPRI10_ECP_MASK 0x80u
+#define DMA_DCHPRI10_ECP_SHIFT 7
+/* DCHPRI9 Bit Fields */
+#define DMA_DCHPRI9_CHPRI_MASK 0xFu
+#define DMA_DCHPRI9_CHPRI_SHIFT 0
+#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
+#define DMA_DCHPRI9_DPA_MASK 0x40u
+#define DMA_DCHPRI9_DPA_SHIFT 6
+#define DMA_DCHPRI9_ECP_MASK 0x80u
+#define DMA_DCHPRI9_ECP_SHIFT 7
+/* DCHPRI8 Bit Fields */
+#define DMA_DCHPRI8_CHPRI_MASK 0xFu
+#define DMA_DCHPRI8_CHPRI_SHIFT 0
+#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
+#define DMA_DCHPRI8_DPA_MASK 0x40u
+#define DMA_DCHPRI8_DPA_SHIFT 6
+#define DMA_DCHPRI8_ECP_MASK 0x80u
+#define DMA_DCHPRI8_ECP_SHIFT 7
+/* DCHPRI15 Bit Fields */
+#define DMA_DCHPRI15_CHPRI_MASK 0xFu
+#define DMA_DCHPRI15_CHPRI_SHIFT 0
+#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
+#define DMA_DCHPRI15_DPA_MASK 0x40u
+#define DMA_DCHPRI15_DPA_SHIFT 6
+#define DMA_DCHPRI15_ECP_MASK 0x80u
+#define DMA_DCHPRI15_ECP_SHIFT 7
+/* DCHPRI14 Bit Fields */
+#define DMA_DCHPRI14_CHPRI_MASK 0xFu
+#define DMA_DCHPRI14_CHPRI_SHIFT 0
+#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
+#define DMA_DCHPRI14_DPA_MASK 0x40u
+#define DMA_DCHPRI14_DPA_SHIFT 6
+#define DMA_DCHPRI14_ECP_MASK 0x80u
+#define DMA_DCHPRI14_ECP_SHIFT 7
+/* DCHPRI13 Bit Fields */
+#define DMA_DCHPRI13_CHPRI_MASK 0xFu
+#define DMA_DCHPRI13_CHPRI_SHIFT 0
+#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
+#define DMA_DCHPRI13_DPA_MASK 0x40u
+#define DMA_DCHPRI13_DPA_SHIFT 6
+#define DMA_DCHPRI13_ECP_MASK 0x80u
+#define DMA_DCHPRI13_ECP_SHIFT 7
+/* DCHPRI12 Bit Fields */
+#define DMA_DCHPRI12_CHPRI_MASK 0xFu
+#define DMA_DCHPRI12_CHPRI_SHIFT 0
+#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
+#define DMA_DCHPRI12_DPA_MASK 0x40u
+#define DMA_DCHPRI12_DPA_SHIFT 6
+#define DMA_DCHPRI12_ECP_MASK 0x80u
+#define DMA_DCHPRI12_ECP_SHIFT 7
+/* SADDR Bit Fields */
+#define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
+#define DMA_SADDR_SADDR_SHIFT 0
+#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
+/* SOFF Bit Fields */
+#define DMA_SOFF_SOFF_MASK 0xFFFFu
+#define DMA_SOFF_SOFF_SHIFT 0
+#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
+/* ATTR Bit Fields */
+#define DMA_ATTR_DSIZE_MASK 0x7u
+#define DMA_ATTR_DSIZE_SHIFT 0
+#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
+#define DMA_ATTR_DMOD_MASK 0xF8u
+#define DMA_ATTR_DMOD_SHIFT 3
+#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
+#define DMA_ATTR_SSIZE_MASK 0x700u
+#define DMA_ATTR_SSIZE_SHIFT 8
+#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
+#define DMA_ATTR_SMOD_MASK 0xF800u
+#define DMA_ATTR_SMOD_SHIFT 11
+#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
+/* NBYTES_MLNO Bit Fields */
+#define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
+#define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
+#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
+/* NBYTES_MLOFFNO Bit Fields */
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
+#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
+#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
+#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
+#define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
+#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
+/* NBYTES_MLOFFYES Bit Fields */
+#define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
+#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
+#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
+#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
+#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
+#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
+#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
+/* SLAST Bit Fields */
+#define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
+#define DMA_SLAST_SLAST_SHIFT 0
+#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
+/* DADDR Bit Fields */
+#define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
+#define DMA_DADDR_DADDR_SHIFT 0
+#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
+/* DOFF Bit Fields */
+#define DMA_DOFF_DOFF_MASK 0xFFFFu
+#define DMA_DOFF_DOFF_SHIFT 0
+#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
+/* CITER_ELINKNO Bit Fields */
+#define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
+#define DMA_CITER_ELINKNO_CITER_SHIFT 0
+#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
+#define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
+#define DMA_CITER_ELINKNO_ELINK_SHIFT 15
+/* CITER_ELINKYES Bit Fields */
+#define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
+#define DMA_CITER_ELINKYES_CITER_SHIFT 0
+#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
+#define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
+#define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
+#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
+#define DMA_CITER_ELINKYES_ELINK_SHIFT 15
+/* DLAST_SGA Bit Fields */
+#define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
+#define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
+#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
+/* CSR Bit Fields */
+#define DMA_CSR_START_MASK 0x1u
+#define DMA_CSR_START_SHIFT 0
+#define DMA_CSR_INTMAJOR_MASK 0x2u
+#define DMA_CSR_INTMAJOR_SHIFT 1
+#define DMA_CSR_INTHALF_MASK 0x4u
+#define DMA_CSR_INTHALF_SHIFT 2
+#define DMA_CSR_DREQ_MASK 0x8u
+#define DMA_CSR_DREQ_SHIFT 3
+#define DMA_CSR_ESG_MASK 0x10u
+#define DMA_CSR_ESG_SHIFT 4
+#define DMA_CSR_MAJORELINK_MASK 0x20u
+#define DMA_CSR_MAJORELINK_SHIFT 5
+#define DMA_CSR_ACTIVE_MASK 0x40u
+#define DMA_CSR_ACTIVE_SHIFT 6
+#define DMA_CSR_DONE_MASK 0x80u
+#define DMA_CSR_DONE_SHIFT 7
+#define DMA_CSR_MAJORLINKCH_MASK 0xF00u
+#define DMA_CSR_MAJORLINKCH_SHIFT 8
+#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
+#define DMA_CSR_BWC_MASK 0xC000u
+#define DMA_CSR_BWC_SHIFT 14
+#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
+/* BITER_ELINKNO Bit Fields */
+#define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
+#define DMA_BITER_ELINKNO_BITER_SHIFT 0
+#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
+#define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
+#define DMA_BITER_ELINKNO_ELINK_SHIFT 15
+/* BITER_ELINKYES Bit Fields */
+#define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
+#define DMA_BITER_ELINKYES_BITER_SHIFT 0
+#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
+#define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
+#define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
+#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
+#define DMA_BITER_ELINKYES_ELINK_SHIFT 15
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0 ((DMA_Type *)DMA_BASE)
+#define DMA_BASE_PTR (DMA0)
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASES { DMA0 }
+
+/* ----------------------------------------------------------------------------
+ -- DMA - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
+ * @{
+ */
+
+
+/* DMA - Register instance definitions */
+/* DMA */
+#define DMA_CR DMA_CR_REG(DMA0)
+#define DMA_ES DMA_ES_REG(DMA0)
+#define DMA_ERQ DMA_ERQ_REG(DMA0)
+#define DMA_EEI DMA_EEI_REG(DMA0)
+#define DMA_CEEI DMA_CEEI_REG(DMA0)
+#define DMA_SEEI DMA_SEEI_REG(DMA0)
+#define DMA_CERQ DMA_CERQ_REG(DMA0)
+#define DMA_SERQ DMA_SERQ_REG(DMA0)
+#define DMA_CDNE DMA_CDNE_REG(DMA0)
+#define DMA_SSRT DMA_SSRT_REG(DMA0)
+#define DMA_CERR DMA_CERR_REG(DMA0)
+#define DMA_CINT DMA_CINT_REG(DMA0)
+#define DMA_INT DMA_INT_REG(DMA0)
+#define DMA_ERR DMA_ERR_REG(DMA0)
+#define DMA_HRS DMA_HRS_REG(DMA0)
+#define DMA_DCHPRI3 DMA_DCHPRI3_REG(DMA0)
+#define DMA_DCHPRI2 DMA_DCHPRI2_REG(DMA0)
+#define DMA_DCHPRI1 DMA_DCHPRI1_REG(DMA0)
+#define DMA_DCHPRI0 DMA_DCHPRI0_REG(DMA0)
+#define DMA_DCHPRI7 DMA_DCHPRI7_REG(DMA0)
+#define DMA_DCHPRI6 DMA_DCHPRI6_REG(DMA0)
+#define DMA_DCHPRI5 DMA_DCHPRI5_REG(DMA0)
+#define DMA_DCHPRI4 DMA_DCHPRI4_REG(DMA0)
+#define DMA_DCHPRI11 DMA_DCHPRI11_REG(DMA0)
+#define DMA_DCHPRI10 DMA_DCHPRI10_REG(DMA0)
+#define DMA_DCHPRI9 DMA_DCHPRI9_REG(DMA0)
+#define DMA_DCHPRI8 DMA_DCHPRI8_REG(DMA0)
+#define DMA_DCHPRI15 DMA_DCHPRI15_REG(DMA0)
+#define DMA_DCHPRI14 DMA_DCHPRI14_REG(DMA0)
+#define DMA_DCHPRI13 DMA_DCHPRI13_REG(DMA0)
+#define DMA_DCHPRI12 DMA_DCHPRI12_REG(DMA0)
+#define DMA_TCD0_SADDR DMA_SADDR_REG(DMA0,0)
+#define DMA_TCD0_SOFF DMA_SOFF_REG(DMA0,0)
+#define DMA_TCD0_ATTR DMA_ATTR_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,0)
+#define DMA_TCD0_SLAST DMA_SLAST_REG(DMA0,0)
+#define DMA_TCD0_DADDR DMA_DADDR_REG(DMA0,0)
+#define DMA_TCD0_DOFF DMA_DOFF_REG(DMA0,0)
+#define DMA_TCD0_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,0)
+#define DMA_TCD0_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,0)
+#define DMA_TCD0_DLASTSGA DMA_DLAST_SGA_REG(DMA0,0)
+#define DMA_TCD0_CSR DMA_CSR_REG(DMA0,0)
+#define DMA_TCD0_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,0)
+#define DMA_TCD0_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,0)
+#define DMA_TCD1_SADDR DMA_SADDR_REG(DMA0,1)
+#define DMA_TCD1_SOFF DMA_SOFF_REG(DMA0,1)
+#define DMA_TCD1_ATTR DMA_ATTR_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,1)
+#define DMA_TCD1_SLAST DMA_SLAST_REG(DMA0,1)
+#define DMA_TCD1_DADDR DMA_DADDR_REG(DMA0,1)
+#define DMA_TCD1_DOFF DMA_DOFF_REG(DMA0,1)
+#define DMA_TCD1_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,1)
+#define DMA_TCD1_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,1)
+#define DMA_TCD1_DLASTSGA DMA_DLAST_SGA_REG(DMA0,1)
+#define DMA_TCD1_CSR DMA_CSR_REG(DMA0,1)
+#define DMA_TCD1_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,1)
+#define DMA_TCD1_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,1)
+#define DMA_TCD2_SADDR DMA_SADDR_REG(DMA0,2)
+#define DMA_TCD2_SOFF DMA_SOFF_REG(DMA0,2)
+#define DMA_TCD2_ATTR DMA_ATTR_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,2)
+#define DMA_TCD2_SLAST DMA_SLAST_REG(DMA0,2)
+#define DMA_TCD2_DADDR DMA_DADDR_REG(DMA0,2)
+#define DMA_TCD2_DOFF DMA_DOFF_REG(DMA0,2)
+#define DMA_TCD2_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,2)
+#define DMA_TCD2_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,2)
+#define DMA_TCD2_DLASTSGA DMA_DLAST_SGA_REG(DMA0,2)
+#define DMA_TCD2_CSR DMA_CSR_REG(DMA0,2)
+#define DMA_TCD2_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,2)
+#define DMA_TCD2_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,2)
+#define DMA_TCD3_SADDR DMA_SADDR_REG(DMA0,3)
+#define DMA_TCD3_SOFF DMA_SOFF_REG(DMA0,3)
+#define DMA_TCD3_ATTR DMA_ATTR_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,3)
+#define DMA_TCD3_SLAST DMA_SLAST_REG(DMA0,3)
+#define DMA_TCD3_DADDR DMA_DADDR_REG(DMA0,3)
+#define DMA_TCD3_DOFF DMA_DOFF_REG(DMA0,3)
+#define DMA_TCD3_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,3)
+#define DMA_TCD3_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,3)
+#define DMA_TCD3_DLASTSGA DMA_DLAST_SGA_REG(DMA0,3)
+#define DMA_TCD3_CSR DMA_CSR_REG(DMA0,3)
+#define DMA_TCD3_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,3)
+#define DMA_TCD3_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,3)
+#define DMA_TCD4_SADDR DMA_SADDR_REG(DMA0,4)
+#define DMA_TCD4_SOFF DMA_SOFF_REG(DMA0,4)
+#define DMA_TCD4_ATTR DMA_ATTR_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,4)
+#define DMA_TCD4_SLAST DMA_SLAST_REG(DMA0,4)
+#define DMA_TCD4_DADDR DMA_DADDR_REG(DMA0,4)
+#define DMA_TCD4_DOFF DMA_DOFF_REG(DMA0,4)
+#define DMA_TCD4_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,4)
+#define DMA_TCD4_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,4)
+#define DMA_TCD4_DLASTSGA DMA_DLAST_SGA_REG(DMA0,4)
+#define DMA_TCD4_CSR DMA_CSR_REG(DMA0,4)
+#define DMA_TCD4_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,4)
+#define DMA_TCD4_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,4)
+#define DMA_TCD5_SADDR DMA_SADDR_REG(DMA0,5)
+#define DMA_TCD5_SOFF DMA_SOFF_REG(DMA0,5)
+#define DMA_TCD5_ATTR DMA_ATTR_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,5)
+#define DMA_TCD5_SLAST DMA_SLAST_REG(DMA0,5)
+#define DMA_TCD5_DADDR DMA_DADDR_REG(DMA0,5)
+#define DMA_TCD5_DOFF DMA_DOFF_REG(DMA0,5)
+#define DMA_TCD5_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,5)
+#define DMA_TCD5_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,5)
+#define DMA_TCD5_DLASTSGA DMA_DLAST_SGA_REG(DMA0,5)
+#define DMA_TCD5_CSR DMA_CSR_REG(DMA0,5)
+#define DMA_TCD5_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,5)
+#define DMA_TCD5_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,5)
+#define DMA_TCD6_SADDR DMA_SADDR_REG(DMA0,6)
+#define DMA_TCD6_SOFF DMA_SOFF_REG(DMA0,6)
+#define DMA_TCD6_ATTR DMA_ATTR_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,6)
+#define DMA_TCD6_SLAST DMA_SLAST_REG(DMA0,6)
+#define DMA_TCD6_DADDR DMA_DADDR_REG(DMA0,6)
+#define DMA_TCD6_DOFF DMA_DOFF_REG(DMA0,6)
+#define DMA_TCD6_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,6)
+#define DMA_TCD6_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,6)
+#define DMA_TCD6_DLASTSGA DMA_DLAST_SGA_REG(DMA0,6)
+#define DMA_TCD6_CSR DMA_CSR_REG(DMA0,6)
+#define DMA_TCD6_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,6)
+#define DMA_TCD6_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,6)
+#define DMA_TCD7_SADDR DMA_SADDR_REG(DMA0,7)
+#define DMA_TCD7_SOFF DMA_SOFF_REG(DMA0,7)
+#define DMA_TCD7_ATTR DMA_ATTR_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,7)
+#define DMA_TCD7_SLAST DMA_SLAST_REG(DMA0,7)
+#define DMA_TCD7_DADDR DMA_DADDR_REG(DMA0,7)
+#define DMA_TCD7_DOFF DMA_DOFF_REG(DMA0,7)
+#define DMA_TCD7_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,7)
+#define DMA_TCD7_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,7)
+#define DMA_TCD7_DLASTSGA DMA_DLAST_SGA_REG(DMA0,7)
+#define DMA_TCD7_CSR DMA_CSR_REG(DMA0,7)
+#define DMA_TCD7_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,7)
+#define DMA_TCD7_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,7)
+#define DMA_TCD8_SADDR DMA_SADDR_REG(DMA0,8)
+#define DMA_TCD8_SOFF DMA_SOFF_REG(DMA0,8)
+#define DMA_TCD8_ATTR DMA_ATTR_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,8)
+#define DMA_TCD8_SLAST DMA_SLAST_REG(DMA0,8)
+#define DMA_TCD8_DADDR DMA_DADDR_REG(DMA0,8)
+#define DMA_TCD8_DOFF DMA_DOFF_REG(DMA0,8)
+#define DMA_TCD8_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,8)
+#define DMA_TCD8_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,8)
+#define DMA_TCD8_DLASTSGA DMA_DLAST_SGA_REG(DMA0,8)
+#define DMA_TCD8_CSR DMA_CSR_REG(DMA0,8)
+#define DMA_TCD8_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,8)
+#define DMA_TCD8_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,8)
+#define DMA_TCD9_SADDR DMA_SADDR_REG(DMA0,9)
+#define DMA_TCD9_SOFF DMA_SOFF_REG(DMA0,9)
+#define DMA_TCD9_ATTR DMA_ATTR_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,9)
+#define DMA_TCD9_SLAST DMA_SLAST_REG(DMA0,9)
+#define DMA_TCD9_DADDR DMA_DADDR_REG(DMA0,9)
+#define DMA_TCD9_DOFF DMA_DOFF_REG(DMA0,9)
+#define DMA_TCD9_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,9)
+#define DMA_TCD9_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,9)
+#define DMA_TCD9_DLASTSGA DMA_DLAST_SGA_REG(DMA0,9)
+#define DMA_TCD9_CSR DMA_CSR_REG(DMA0,9)
+#define DMA_TCD9_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,9)
+#define DMA_TCD9_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,9)
+#define DMA_TCD10_SADDR DMA_SADDR_REG(DMA0,10)
+#define DMA_TCD10_SOFF DMA_SOFF_REG(DMA0,10)
+#define DMA_TCD10_ATTR DMA_ATTR_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,10)
+#define DMA_TCD10_SLAST DMA_SLAST_REG(DMA0,10)
+#define DMA_TCD10_DADDR DMA_DADDR_REG(DMA0,10)
+#define DMA_TCD10_DOFF DMA_DOFF_REG(DMA0,10)
+#define DMA_TCD10_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,10)
+#define DMA_TCD10_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,10)
+#define DMA_TCD10_DLASTSGA DMA_DLAST_SGA_REG(DMA0,10)
+#define DMA_TCD10_CSR DMA_CSR_REG(DMA0,10)
+#define DMA_TCD10_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,10)
+#define DMA_TCD10_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,10)
+#define DMA_TCD11_SADDR DMA_SADDR_REG(DMA0,11)
+#define DMA_TCD11_SOFF DMA_SOFF_REG(DMA0,11)
+#define DMA_TCD11_ATTR DMA_ATTR_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,11)
+#define DMA_TCD11_SLAST DMA_SLAST_REG(DMA0,11)
+#define DMA_TCD11_DADDR DMA_DADDR_REG(DMA0,11)
+#define DMA_TCD11_DOFF DMA_DOFF_REG(DMA0,11)
+#define DMA_TCD11_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,11)
+#define DMA_TCD11_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,11)
+#define DMA_TCD11_DLASTSGA DMA_DLAST_SGA_REG(DMA0,11)
+#define DMA_TCD11_CSR DMA_CSR_REG(DMA0,11)
+#define DMA_TCD11_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,11)
+#define DMA_TCD11_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,11)
+#define DMA_TCD12_SADDR DMA_SADDR_REG(DMA0,12)
+#define DMA_TCD12_SOFF DMA_SOFF_REG(DMA0,12)
+#define DMA_TCD12_ATTR DMA_ATTR_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,12)
+#define DMA_TCD12_SLAST DMA_SLAST_REG(DMA0,12)
+#define DMA_TCD12_DADDR DMA_DADDR_REG(DMA0,12)
+#define DMA_TCD12_DOFF DMA_DOFF_REG(DMA0,12)
+#define DMA_TCD12_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,12)
+#define DMA_TCD12_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,12)
+#define DMA_TCD12_DLASTSGA DMA_DLAST_SGA_REG(DMA0,12)
+#define DMA_TCD12_CSR DMA_CSR_REG(DMA0,12)
+#define DMA_TCD12_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,12)
+#define DMA_TCD12_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,12)
+#define DMA_TCD13_SADDR DMA_SADDR_REG(DMA0,13)
+#define DMA_TCD13_SOFF DMA_SOFF_REG(DMA0,13)
+#define DMA_TCD13_ATTR DMA_ATTR_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,13)
+#define DMA_TCD13_SLAST DMA_SLAST_REG(DMA0,13)
+#define DMA_TCD13_DADDR DMA_DADDR_REG(DMA0,13)
+#define DMA_TCD13_DOFF DMA_DOFF_REG(DMA0,13)
+#define DMA_TCD13_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,13)
+#define DMA_TCD13_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,13)
+#define DMA_TCD13_DLASTSGA DMA_DLAST_SGA_REG(DMA0,13)
+#define DMA_TCD13_CSR DMA_CSR_REG(DMA0,13)
+#define DMA_TCD13_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,13)
+#define DMA_TCD13_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,13)
+#define DMA_TCD14_SADDR DMA_SADDR_REG(DMA0,14)
+#define DMA_TCD14_SOFF DMA_SOFF_REG(DMA0,14)
+#define DMA_TCD14_ATTR DMA_ATTR_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,14)
+#define DMA_TCD14_SLAST DMA_SLAST_REG(DMA0,14)
+#define DMA_TCD14_DADDR DMA_DADDR_REG(DMA0,14)
+#define DMA_TCD14_DOFF DMA_DOFF_REG(DMA0,14)
+#define DMA_TCD14_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,14)
+#define DMA_TCD14_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,14)
+#define DMA_TCD14_DLASTSGA DMA_DLAST_SGA_REG(DMA0,14)
+#define DMA_TCD14_CSR DMA_CSR_REG(DMA0,14)
+#define DMA_TCD14_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,14)
+#define DMA_TCD14_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,14)
+#define DMA_TCD15_SADDR DMA_SADDR_REG(DMA0,15)
+#define DMA_TCD15_SOFF DMA_SOFF_REG(DMA0,15)
+#define DMA_TCD15_ATTR DMA_ATTR_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,15)
+#define DMA_TCD15_SLAST DMA_SLAST_REG(DMA0,15)
+#define DMA_TCD15_DADDR DMA_DADDR_REG(DMA0,15)
+#define DMA_TCD15_DOFF DMA_DOFF_REG(DMA0,15)
+#define DMA_TCD15_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,15)
+#define DMA_TCD15_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,15)
+#define DMA_TCD15_DLASTSGA DMA_DLAST_SGA_REG(DMA0,15)
+#define DMA_TCD15_CSR DMA_CSR_REG(DMA0,15)
+#define DMA_TCD15_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,15)
+#define DMA_TCD15_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,15)
+
+/* DMA - Register array accessors */
+#define DMA_SADDR(index) DMA_SADDR_REG(DMA0,index)
+#define DMA_SOFF(index) DMA_SOFF_REG(DMA0,index)
+#define DMA_ATTR(index) DMA_ATTR_REG(DMA0,index)
+#define DMA_NBYTES_MLNO(index) DMA_NBYTES_MLNO_REG(DMA0,index)
+#define DMA_NBYTES_MLOFFNO(index) DMA_NBYTES_MLOFFNO_REG(DMA0,index)
+#define DMA_NBYTES_MLOFFYES(index) DMA_NBYTES_MLOFFYES_REG(DMA0,index)
+#define DMA_SLAST(index) DMA_SLAST_REG(DMA0,index)
+#define DMA_DADDR(index) DMA_DADDR_REG(DMA0,index)
+#define DMA_DOFF(index) DMA_DOFF_REG(DMA0,index)
+#define DMA_CITER_ELINKNO(index) DMA_CITER_ELINKNO_REG(DMA0,index)
+#define DMA_CITER_ELINKYES(index) DMA_CITER_ELINKYES_REG(DMA0,index)
+#define DMA_DLAST_SGA(index) DMA_DLAST_SGA_REG(DMA0,index)
+#define DMA_CSR(index) DMA_CSR_REG(DMA0,index)
+#define DMA_BITER_ELINKNO(index) DMA_BITER_ELINKNO_REG(DMA0,index)
+#define DMA_BITER_ELINKYES(index) DMA_BITER_ELINKYES_REG(DMA0,index)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type, *DMAMUX_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
+ * @{
+ */
+
+
+/* DMAMUX - Register accessors */
+#define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index])
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/* CHCFG Bit Fields */
+#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
+#define DMAMUX_CHCFG_SOURCE_SHIFT 0
+#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK 0x40u
+#define DMAMUX_CHCFG_TRIG_SHIFT 6
+#define DMAMUX_CHCFG_ENBL_MASK 0x80u
+#define DMAMUX_CHCFG_ENBL_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX base address */
+#define DMAMUX_BASE (0x40021000u)
+/** Peripheral DMAMUX base pointer */
+#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
+#define DMAMUX_BASE_PTR (DMAMUX)
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASES { DMAMUX }
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
+ * @{
+ */
+
+
+/* DMAMUX - Register instance definitions */
+/* DMAMUX */
+#define DMAMUX_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX,0)
+#define DMAMUX_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX,1)
+#define DMAMUX_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX,2)
+#define DMAMUX_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX,3)
+#define DMAMUX_CHCFG4 DMAMUX_CHCFG_REG(DMAMUX,4)
+#define DMAMUX_CHCFG5 DMAMUX_CHCFG_REG(DMAMUX,5)
+#define DMAMUX_CHCFG6 DMAMUX_CHCFG_REG(DMAMUX,6)
+#define DMAMUX_CHCFG7 DMAMUX_CHCFG_REG(DMAMUX,7)
+#define DMAMUX_CHCFG8 DMAMUX_CHCFG_REG(DMAMUX,8)
+#define DMAMUX_CHCFG9 DMAMUX_CHCFG_REG(DMAMUX,9)
+#define DMAMUX_CHCFG10 DMAMUX_CHCFG_REG(DMAMUX,10)
+#define DMAMUX_CHCFG11 DMAMUX_CHCFG_REG(DMAMUX,11)
+#define DMAMUX_CHCFG12 DMAMUX_CHCFG_REG(DMAMUX,12)
+#define DMAMUX_CHCFG13 DMAMUX_CHCFG_REG(DMAMUX,13)
+#define DMAMUX_CHCFG14 DMAMUX_CHCFG_REG(DMAMUX,14)
+#define DMAMUX_CHCFG15 DMAMUX_CHCFG_REG(DMAMUX,15)
+
+/* DMAMUX - Register array accessors */
+#define DMAMUX_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX,index)
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- ENET Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
+ * @{
+ */
+
+/** ENET - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[4];
+ __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */
+ __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */
+ __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */
+ uint8_t RESERVED_2[12];
+ __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */
+ uint8_t RESERVED_3[24];
+ __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */
+ __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */
+ uint8_t RESERVED_4[28];
+ __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */
+ uint8_t RESERVED_5[28];
+ __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */
+ uint8_t RESERVED_6[60];
+ __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */
+ uint8_t RESERVED_7[28];
+ __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */
+ __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */
+ __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */
+ uint8_t RESERVED_8[40];
+ __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */
+ __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */
+ __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */
+ __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */
+ uint8_t RESERVED_9[28];
+ __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */
+ uint8_t RESERVED_10[56];
+ __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */
+ __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
+ __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */
+ uint8_t RESERVED_11[4];
+ __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */
+ __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
+ __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
+ __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
+ __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
+ __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
+ __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
+ __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */
+ __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */
+ uint8_t RESERVED_12[12];
+ __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
+ __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
+ uint8_t RESERVED_13[60];
+ __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */
+ __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
+ __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
+ __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
+ __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
+ __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
+ __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
+ __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
+ __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */
+ __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
+ __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
+ __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
+ __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
+ __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
+ __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
+ __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
+ __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */
+ uint8_t RESERVED_14[4];
+ __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
+ __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
+ __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
+ __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
+ __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
+ __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
+ __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
+ __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
+ uint8_t RESERVED_15[4];
+ __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
+ __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
+ uint8_t RESERVED_16[12];
+ __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */
+ __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
+ __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
+ __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
+ __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
+ __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
+ __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
+ __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
+ uint8_t RESERVED_17[4];
+ __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
+ __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
+ __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
+ __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
+ __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
+ __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
+ __I uint32_t RMON_R_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
+ __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */
+ __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
+ __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */
+ __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
+ __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
+ __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
+ __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
+ __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
+ uint8_t RESERVED_18[284];
+ __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */
+ __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */
+ __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */
+ __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */
+ __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */
+ __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */
+ __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
+ uint8_t RESERVED_19[488];
+ __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */
+ struct { /* offset: 0x608, array step: 0x8 */
+ __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
+ __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
+ } CHANNEL[4];
+} ENET_Type, *ENET_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- ENET - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
+ * @{
+ */
+
+
+/* ENET - Register accessors */
+#define ENET_EIR_REG(base) ((base)->EIR)
+#define ENET_EIMR_REG(base) ((base)->EIMR)
+#define ENET_RDAR_REG(base) ((base)->RDAR)
+#define ENET_TDAR_REG(base) ((base)->TDAR)
+#define ENET_ECR_REG(base) ((base)->ECR)
+#define ENET_MMFR_REG(base) ((base)->MMFR)
+#define ENET_MSCR_REG(base) ((base)->MSCR)
+#define ENET_MIBC_REG(base) ((base)->MIBC)
+#define ENET_RCR_REG(base) ((base)->RCR)
+#define ENET_TCR_REG(base) ((base)->TCR)
+#define ENET_PALR_REG(base) ((base)->PALR)
+#define ENET_PAUR_REG(base) ((base)->PAUR)
+#define ENET_OPD_REG(base) ((base)->OPD)
+#define ENET_IAUR_REG(base) ((base)->IAUR)
+#define ENET_IALR_REG(base) ((base)->IALR)
+#define ENET_GAUR_REG(base) ((base)->GAUR)
+#define ENET_GALR_REG(base) ((base)->GALR)
+#define ENET_TFWR_REG(base) ((base)->TFWR)
+#define ENET_RDSR_REG(base) ((base)->RDSR)
+#define ENET_TDSR_REG(base) ((base)->TDSR)
+#define ENET_MRBR_REG(base) ((base)->MRBR)
+#define ENET_RSFL_REG(base) ((base)->RSFL)
+#define ENET_RSEM_REG(base) ((base)->RSEM)
+#define ENET_RAEM_REG(base) ((base)->RAEM)
+#define ENET_RAFL_REG(base) ((base)->RAFL)
+#define ENET_TSEM_REG(base) ((base)->TSEM)
+#define ENET_TAEM_REG(base) ((base)->TAEM)
+#define ENET_TAFL_REG(base) ((base)->TAFL)
+#define ENET_TIPG_REG(base) ((base)->TIPG)
+#define ENET_FTRL_REG(base) ((base)->FTRL)
+#define ENET_TACC_REG(base) ((base)->TACC)
+#define ENET_RACC_REG(base) ((base)->RACC)
+#define ENET_RMON_T_PACKETS_REG(base) ((base)->RMON_T_PACKETS)
+#define ENET_RMON_T_BC_PKT_REG(base) ((base)->RMON_T_BC_PKT)
+#define ENET_RMON_T_MC_PKT_REG(base) ((base)->RMON_T_MC_PKT)
+#define ENET_RMON_T_CRC_ALIGN_REG(base) ((base)->RMON_T_CRC_ALIGN)
+#define ENET_RMON_T_UNDERSIZE_REG(base) ((base)->RMON_T_UNDERSIZE)
+#define ENET_RMON_T_OVERSIZE_REG(base) ((base)->RMON_T_OVERSIZE)
+#define ENET_RMON_T_FRAG_REG(base) ((base)->RMON_T_FRAG)
+#define ENET_RMON_T_JAB_REG(base) ((base)->RMON_T_JAB)
+#define ENET_RMON_T_COL_REG(base) ((base)->RMON_T_COL)
+#define ENET_RMON_T_P64_REG(base) ((base)->RMON_T_P64)
+#define ENET_RMON_T_P65TO127_REG(base) ((base)->RMON_T_P65TO127)
+#define ENET_RMON_T_P128TO255_REG(base) ((base)->RMON_T_P128TO255)
+#define ENET_RMON_T_P256TO511_REG(base) ((base)->RMON_T_P256TO511)
+#define ENET_RMON_T_P512TO1023_REG(base) ((base)->RMON_T_P512TO1023)
+#define ENET_RMON_T_P1024TO2047_REG(base) ((base)->RMON_T_P1024TO2047)
+#define ENET_RMON_T_P_GTE2048_REG(base) ((base)->RMON_T_P_GTE2048)
+#define ENET_RMON_T_OCTETS_REG(base) ((base)->RMON_T_OCTETS)
+#define ENET_IEEE_T_FRAME_OK_REG(base) ((base)->IEEE_T_FRAME_OK)
+#define ENET_IEEE_T_1COL_REG(base) ((base)->IEEE_T_1COL)
+#define ENET_IEEE_T_MCOL_REG(base) ((base)->IEEE_T_MCOL)
+#define ENET_IEEE_T_DEF_REG(base) ((base)->IEEE_T_DEF)
+#define ENET_IEEE_T_LCOL_REG(base) ((base)->IEEE_T_LCOL)
+#define ENET_IEEE_T_EXCOL_REG(base) ((base)->IEEE_T_EXCOL)
+#define ENET_IEEE_T_MACERR_REG(base) ((base)->IEEE_T_MACERR)
+#define ENET_IEEE_T_CSERR_REG(base) ((base)->IEEE_T_CSERR)
+#define ENET_IEEE_T_FDXFC_REG(base) ((base)->IEEE_T_FDXFC)
+#define ENET_IEEE_T_OCTETS_OK_REG(base) ((base)->IEEE_T_OCTETS_OK)
+#define ENET_RMON_R_PACKETS_REG(base) ((base)->RMON_R_PACKETS)
+#define ENET_RMON_R_BC_PKT_REG(base) ((base)->RMON_R_BC_PKT)
+#define ENET_RMON_R_MC_PKT_REG(base) ((base)->RMON_R_MC_PKT)
+#define ENET_RMON_R_CRC_ALIGN_REG(base) ((base)->RMON_R_CRC_ALIGN)
+#define ENET_RMON_R_UNDERSIZE_REG(base) ((base)->RMON_R_UNDERSIZE)
+#define ENET_RMON_R_OVERSIZE_REG(base) ((base)->RMON_R_OVERSIZE)
+#define ENET_RMON_R_FRAG_REG(base) ((base)->RMON_R_FRAG)
+#define ENET_RMON_R_JAB_REG(base) ((base)->RMON_R_JAB)
+#define ENET_RMON_R_P64_REG(base) ((base)->RMON_R_P64)
+#define ENET_RMON_R_P65TO127_REG(base) ((base)->RMON_R_P65TO127)
+#define ENET_RMON_R_P128TO255_REG(base) ((base)->RMON_R_P128TO255)
+#define ENET_RMON_R_P256TO511_REG(base) ((base)->RMON_R_P256TO511)
+#define ENET_RMON_R_P512TO1023_REG(base) ((base)->RMON_R_P512TO1023)
+#define ENET_RMON_R_P1024TO2047_REG(base) ((base)->RMON_R_P1024TO2047)
+#define ENET_RMON_R_GTE2048_REG(base) ((base)->RMON_R_GTE2048)
+#define ENET_RMON_R_OCTETS_REG(base) ((base)->RMON_R_OCTETS)
+#define ENET_IEEE_R_DROP_REG(base) ((base)->IEEE_R_DROP)
+#define ENET_IEEE_R_FRAME_OK_REG(base) ((base)->IEEE_R_FRAME_OK)
+#define ENET_IEEE_R_CRC_REG(base) ((base)->IEEE_R_CRC)
+#define ENET_IEEE_R_ALIGN_REG(base) ((base)->IEEE_R_ALIGN)
+#define ENET_IEEE_R_MACERR_REG(base) ((base)->IEEE_R_MACERR)
+#define ENET_IEEE_R_FDXFC_REG(base) ((base)->IEEE_R_FDXFC)
+#define ENET_IEEE_R_OCTETS_OK_REG(base) ((base)->IEEE_R_OCTETS_OK)
+#define ENET_ATCR_REG(base) ((base)->ATCR)
+#define ENET_ATVR_REG(base) ((base)->ATVR)
+#define ENET_ATOFF_REG(base) ((base)->ATOFF)
+#define ENET_ATPER_REG(base) ((base)->ATPER)
+#define ENET_ATCOR_REG(base) ((base)->ATCOR)
+#define ENET_ATINC_REG(base) ((base)->ATINC)
+#define ENET_ATSTMP_REG(base) ((base)->ATSTMP)
+#define ENET_TGSR_REG(base) ((base)->TGSR)
+#define ENET_TCSR_REG(base,index) ((base)->CHANNEL[index].TCSR)
+#define ENET_TCCR_REG(base,index) ((base)->CHANNEL[index].TCCR)
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- ENET Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Masks ENET Register Masks
+ * @{
+ */
+
+/* EIR Bit Fields */
+#define ENET_EIR_TS_TIMER_MASK 0x8000u
+#define ENET_EIR_TS_TIMER_SHIFT 15
+#define ENET_EIR_TS_AVAIL_MASK 0x10000u
+#define ENET_EIR_TS_AVAIL_SHIFT 16
+#define ENET_EIR_WAKEUP_MASK 0x20000u
+#define ENET_EIR_WAKEUP_SHIFT 17
+#define ENET_EIR_PLR_MASK 0x40000u
+#define ENET_EIR_PLR_SHIFT 18
+#define ENET_EIR_UN_MASK 0x80000u
+#define ENET_EIR_UN_SHIFT 19
+#define ENET_EIR_RL_MASK 0x100000u
+#define ENET_EIR_RL_SHIFT 20
+#define ENET_EIR_LC_MASK 0x200000u
+#define ENET_EIR_LC_SHIFT 21
+#define ENET_EIR_EBERR_MASK 0x400000u
+#define ENET_EIR_EBERR_SHIFT 22
+#define ENET_EIR_MII_MASK 0x800000u
+#define ENET_EIR_MII_SHIFT 23
+#define ENET_EIR_RXB_MASK 0x1000000u
+#define ENET_EIR_RXB_SHIFT 24
+#define ENET_EIR_RXF_MASK 0x2000000u
+#define ENET_EIR_RXF_SHIFT 25
+#define ENET_EIR_TXB_MASK 0x4000000u
+#define ENET_EIR_TXB_SHIFT 26
+#define ENET_EIR_TXF_MASK 0x8000000u
+#define ENET_EIR_TXF_SHIFT 27
+#define ENET_EIR_GRA_MASK 0x10000000u
+#define ENET_EIR_GRA_SHIFT 28
+#define ENET_EIR_BABT_MASK 0x20000000u
+#define ENET_EIR_BABT_SHIFT 29
+#define ENET_EIR_BABR_MASK 0x40000000u
+#define ENET_EIR_BABR_SHIFT 30
+/* EIMR Bit Fields */
+#define ENET_EIMR_TS_TIMER_MASK 0x8000u
+#define ENET_EIMR_TS_TIMER_SHIFT 15
+#define ENET_EIMR_TS_AVAIL_MASK 0x10000u
+#define ENET_EIMR_TS_AVAIL_SHIFT 16
+#define ENET_EIMR_WAKEUP_MASK 0x20000u
+#define ENET_EIMR_WAKEUP_SHIFT 17
+#define ENET_EIMR_PLR_MASK 0x40000u
+#define ENET_EIMR_PLR_SHIFT 18
+#define ENET_EIMR_UN_MASK 0x80000u
+#define ENET_EIMR_UN_SHIFT 19
+#define ENET_EIMR_RL_MASK 0x100000u
+#define ENET_EIMR_RL_SHIFT 20
+#define ENET_EIMR_LC_MASK 0x200000u
+#define ENET_EIMR_LC_SHIFT 21
+#define ENET_EIMR_EBERR_MASK 0x400000u
+#define ENET_EIMR_EBERR_SHIFT 22
+#define ENET_EIMR_MII_MASK 0x800000u
+#define ENET_EIMR_MII_SHIFT 23
+#define ENET_EIMR_RXB_MASK 0x1000000u
+#define ENET_EIMR_RXB_SHIFT 24
+#define ENET_EIMR_RXF_MASK 0x2000000u
+#define ENET_EIMR_RXF_SHIFT 25
+#define ENET_EIMR_TXB_MASK 0x4000000u
+#define ENET_EIMR_TXB_SHIFT 26
+#define ENET_EIMR_TXF_MASK 0x8000000u
+#define ENET_EIMR_TXF_SHIFT 27
+#define ENET_EIMR_GRA_MASK 0x10000000u
+#define ENET_EIMR_GRA_SHIFT 28
+#define ENET_EIMR_BABT_MASK 0x20000000u
+#define ENET_EIMR_BABT_SHIFT 29
+#define ENET_EIMR_BABR_MASK 0x40000000u
+#define ENET_EIMR_BABR_SHIFT 30
+/* RDAR Bit Fields */
+#define ENET_RDAR_RDAR_MASK 0x1000000u
+#define ENET_RDAR_RDAR_SHIFT 24
+/* TDAR Bit Fields */
+#define ENET_TDAR_TDAR_MASK 0x1000000u
+#define ENET_TDAR_TDAR_SHIFT 24
+/* ECR Bit Fields */
+#define ENET_ECR_RESET_MASK 0x1u
+#define ENET_ECR_RESET_SHIFT 0
+#define ENET_ECR_ETHEREN_MASK 0x2u
+#define ENET_ECR_ETHEREN_SHIFT 1
+#define ENET_ECR_MAGICEN_MASK 0x4u
+#define ENET_ECR_MAGICEN_SHIFT 2
+#define ENET_ECR_SLEEP_MASK 0x8u
+#define ENET_ECR_SLEEP_SHIFT 3
+#define ENET_ECR_EN1588_MASK 0x10u
+#define ENET_ECR_EN1588_SHIFT 4
+#define ENET_ECR_DBGEN_MASK 0x40u
+#define ENET_ECR_DBGEN_SHIFT 6
+#define ENET_ECR_STOPEN_MASK 0x80u
+#define ENET_ECR_STOPEN_SHIFT 7
+#define ENET_ECR_DBSWP_MASK 0x100u
+#define ENET_ECR_DBSWP_SHIFT 8
+/* MMFR Bit Fields */
+#define ENET_MMFR_DATA_MASK 0xFFFFu
+#define ENET_MMFR_DATA_SHIFT 0
+#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK)
+#define ENET_MMFR_TA_MASK 0x30000u
+#define ENET_MMFR_TA_SHIFT 16
+#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK)
+#define ENET_MMFR_RA_MASK 0x7C0000u
+#define ENET_MMFR_RA_SHIFT 18
+#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK)
+#define ENET_MMFR_PA_MASK 0xF800000u
+#define ENET_MMFR_PA_SHIFT 23
+#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK)
+#define ENET_MMFR_OP_MASK 0x30000000u
+#define ENET_MMFR_OP_SHIFT 28
+#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK)
+#define ENET_MMFR_ST_MASK 0xC0000000u
+#define ENET_MMFR_ST_SHIFT 30
+#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK)
+/* MSCR Bit Fields */
+#define ENET_MSCR_MII_SPEED_MASK 0x7Eu
+#define ENET_MSCR_MII_SPEED_SHIFT 1
+#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK)
+#define ENET_MSCR_DIS_PRE_MASK 0x80u
+#define ENET_MSCR_DIS_PRE_SHIFT 7
+#define ENET_MSCR_HOLDTIME_MASK 0x700u
+#define ENET_MSCR_HOLDTIME_SHIFT 8
+#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK)
+/* MIBC Bit Fields */
+#define ENET_MIBC_MIB_CLEAR_MASK 0x20000000u
+#define ENET_MIBC_MIB_CLEAR_SHIFT 29
+#define ENET_MIBC_MIB_IDLE_MASK 0x40000000u
+#define ENET_MIBC_MIB_IDLE_SHIFT 30
+#define ENET_MIBC_MIB_DIS_MASK 0x80000000u
+#define ENET_MIBC_MIB_DIS_SHIFT 31
+/* RCR Bit Fields */
+#define ENET_RCR_LOOP_MASK 0x1u
+#define ENET_RCR_LOOP_SHIFT 0
+#define ENET_RCR_DRT_MASK 0x2u
+#define ENET_RCR_DRT_SHIFT 1
+#define ENET_RCR_MII_MODE_MASK 0x4u
+#define ENET_RCR_MII_MODE_SHIFT 2
+#define ENET_RCR_PROM_MASK 0x8u
+#define ENET_RCR_PROM_SHIFT 3
+#define ENET_RCR_BC_REJ_MASK 0x10u
+#define ENET_RCR_BC_REJ_SHIFT 4
+#define ENET_RCR_FCE_MASK 0x20u
+#define ENET_RCR_FCE_SHIFT 5
+#define ENET_RCR_RMII_MODE_MASK 0x100u
+#define ENET_RCR_RMII_MODE_SHIFT 8
+#define ENET_RCR_RMII_10T_MASK 0x200u
+#define ENET_RCR_RMII_10T_SHIFT 9
+#define ENET_RCR_PADEN_MASK 0x1000u
+#define ENET_RCR_PADEN_SHIFT 12
+#define ENET_RCR_PAUFWD_MASK 0x2000u
+#define ENET_RCR_PAUFWD_SHIFT 13
+#define ENET_RCR_CRCFWD_MASK 0x4000u
+#define ENET_RCR_CRCFWD_SHIFT 14
+#define ENET_RCR_CFEN_MASK 0x8000u
+#define ENET_RCR_CFEN_SHIFT 15
+#define ENET_RCR_MAX_FL_MASK 0x3FFF0000u
+#define ENET_RCR_MAX_FL_SHIFT 16
+#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK)
+#define ENET_RCR_NLC_MASK 0x40000000u
+#define ENET_RCR_NLC_SHIFT 30
+#define ENET_RCR_GRS_MASK 0x80000000u
+#define ENET_RCR_GRS_SHIFT 31
+/* TCR Bit Fields */
+#define ENET_TCR_GTS_MASK 0x1u
+#define ENET_TCR_GTS_SHIFT 0
+#define ENET_TCR_FDEN_MASK 0x4u
+#define ENET_TCR_FDEN_SHIFT 2
+#define ENET_TCR_TFC_PAUSE_MASK 0x8u
+#define ENET_TCR_TFC_PAUSE_SHIFT 3
+#define ENET_TCR_RFC_PAUSE_MASK 0x10u
+#define ENET_TCR_RFC_PAUSE_SHIFT 4
+#define ENET_TCR_ADDSEL_MASK 0xE0u
+#define ENET_TCR_ADDSEL_SHIFT 5
+#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK)
+#define ENET_TCR_ADDINS_MASK 0x100u
+#define ENET_TCR_ADDINS_SHIFT 8
+#define ENET_TCR_CRCFWD_MASK 0x200u
+#define ENET_TCR_CRCFWD_SHIFT 9
+/* PALR Bit Fields */
+#define ENET_PALR_PADDR1_MASK 0xFFFFFFFFu
+#define ENET_PALR_PADDR1_SHIFT 0
+#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK)
+/* PAUR Bit Fields */
+#define ENET_PAUR_TYPE_MASK 0xFFFFu
+#define ENET_PAUR_TYPE_SHIFT 0
+#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK)
+#define ENET_PAUR_PADDR2_MASK 0xFFFF0000u
+#define ENET_PAUR_PADDR2_SHIFT 16
+#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK)
+/* OPD Bit Fields */
+#define ENET_OPD_PAUSE_DUR_MASK 0xFFFFu
+#define ENET_OPD_PAUSE_DUR_SHIFT 0
+#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK)
+#define ENET_OPD_OPCODE_MASK 0xFFFF0000u
+#define ENET_OPD_OPCODE_SHIFT 16
+#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK)
+/* IAUR Bit Fields */
+#define ENET_IAUR_IADDR1_MASK 0xFFFFFFFFu
+#define ENET_IAUR_IADDR1_SHIFT 0
+#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK)
+/* IALR Bit Fields */
+#define ENET_IALR_IADDR2_MASK 0xFFFFFFFFu
+#define ENET_IALR_IADDR2_SHIFT 0
+#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK)
+/* GAUR Bit Fields */
+#define ENET_GAUR_GADDR1_MASK 0xFFFFFFFFu
+#define ENET_GAUR_GADDR1_SHIFT 0
+#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK)
+/* GALR Bit Fields */
+#define ENET_GALR_GADDR2_MASK 0xFFFFFFFFu
+#define ENET_GALR_GADDR2_SHIFT 0
+#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK)
+/* TFWR Bit Fields */
+#define ENET_TFWR_TFWR_MASK 0x3Fu
+#define ENET_TFWR_TFWR_SHIFT 0
+#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK)
+#define ENET_TFWR_STRFWD_MASK 0x100u
+#define ENET_TFWR_STRFWD_SHIFT 8
+/* RDSR Bit Fields */
+#define ENET_RDSR_R_DES_START_MASK 0xFFFFFFF8u
+#define ENET_RDSR_R_DES_START_SHIFT 3
+#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK)
+/* TDSR Bit Fields */
+#define ENET_TDSR_X_DES_START_MASK 0xFFFFFFF8u
+#define ENET_TDSR_X_DES_START_SHIFT 3
+#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK)
+/* MRBR Bit Fields */
+#define ENET_MRBR_R_BUF_SIZE_MASK 0x3FF0u
+#define ENET_MRBR_R_BUF_SIZE_SHIFT 4
+#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK)
+/* RSFL Bit Fields */
+#define ENET_RSFL_RX_SECTION_FULL_MASK 0xFFu
+#define ENET_RSFL_RX_SECTION_FULL_SHIFT 0
+#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK)
+/* RSEM Bit Fields */
+#define ENET_RSEM_RX_SECTION_EMPTY_MASK 0xFFu
+#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT 0
+#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK)
+#define ENET_RSEM_STAT_SECTION_EMPTY_MASK 0x1F0000u
+#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT 16
+#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_STAT_SECTION_EMPTY_SHIFT))&ENET_RSEM_STAT_SECTION_EMPTY_MASK)
+/* RAEM Bit Fields */
+#define ENET_RAEM_RX_ALMOST_EMPTY_MASK 0xFFu
+#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT 0
+#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK)
+/* RAFL Bit Fields */
+#define ENET_RAFL_RX_ALMOST_FULL_MASK 0xFFu
+#define ENET_RAFL_RX_ALMOST_FULL_SHIFT 0
+#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK)
+/* TSEM Bit Fields */
+#define ENET_TSEM_TX_SECTION_EMPTY_MASK 0xFFu
+#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT 0
+#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK)
+/* TAEM Bit Fields */
+#define ENET_TAEM_TX_ALMOST_EMPTY_MASK 0xFFu
+#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT 0
+#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK)
+/* TAFL Bit Fields */
+#define ENET_TAFL_TX_ALMOST_FULL_MASK 0xFFu
+#define ENET_TAFL_TX_ALMOST_FULL_SHIFT 0
+#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK)
+/* TIPG Bit Fields */
+#define ENET_TIPG_IPG_MASK 0x1Fu
+#define ENET_TIPG_IPG_SHIFT 0
+#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK)
+/* FTRL Bit Fields */
+#define ENET_FTRL_TRUNC_FL_MASK 0x3FFFu
+#define ENET_FTRL_TRUNC_FL_SHIFT 0
+#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK)
+/* TACC Bit Fields */
+#define ENET_TACC_SHIFT16_MASK 0x1u
+#define ENET_TACC_SHIFT16_SHIFT 0
+#define ENET_TACC_IPCHK_MASK 0x8u
+#define ENET_TACC_IPCHK_SHIFT 3
+#define ENET_TACC_PROCHK_MASK 0x10u
+#define ENET_TACC_PROCHK_SHIFT 4
+/* RACC Bit Fields */
+#define ENET_RACC_PADREM_MASK 0x1u
+#define ENET_RACC_PADREM_SHIFT 0
+#define ENET_RACC_IPDIS_MASK 0x2u
+#define ENET_RACC_IPDIS_SHIFT 1
+#define ENET_RACC_PRODIS_MASK 0x4u
+#define ENET_RACC_PRODIS_SHIFT 2
+#define ENET_RACC_LINEDIS_MASK 0x40u
+#define ENET_RACC_LINEDIS_SHIFT 6
+#define ENET_RACC_SHIFT16_MASK 0x80u
+#define ENET_RACC_SHIFT16_SHIFT 7
+/* RMON_T_PACKETS Bit Fields */
+#define ENET_RMON_T_PACKETS_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT 0
+#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_PACKETS_TXPKTS_SHIFT))&ENET_RMON_T_PACKETS_TXPKTS_MASK)
+/* RMON_T_BC_PKT Bit Fields */
+#define ENET_RMON_T_BC_PKT_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT 0
+#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_BC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_BC_PKT_TXPKTS_MASK)
+/* RMON_T_MC_PKT Bit Fields */
+#define ENET_RMON_T_MC_PKT_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT 0
+#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_MC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_MC_PKT_TXPKTS_MASK)
+/* RMON_T_CRC_ALIGN Bit Fields */
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT 0
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT))&ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
+/* RMON_T_UNDERSIZE Bit Fields */
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT 0
+#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
+/* RMON_T_OVERSIZE Bit Fields */
+#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT 0
+#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
+/* RMON_T_FRAG Bit Fields */
+#define ENET_RMON_T_FRAG_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_FRAG_TXPKTS_SHIFT 0
+#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_FRAG_TXPKTS_SHIFT))&ENET_RMON_T_FRAG_TXPKTS_MASK)
+/* RMON_T_JAB Bit Fields */
+#define ENET_RMON_T_JAB_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_JAB_TXPKTS_SHIFT 0
+#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_JAB_TXPKTS_SHIFT))&ENET_RMON_T_JAB_TXPKTS_MASK)
+/* RMON_T_COL Bit Fields */
+#define ENET_RMON_T_COL_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_COL_TXPKTS_SHIFT 0
+#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_COL_TXPKTS_SHIFT))&ENET_RMON_T_COL_TXPKTS_MASK)
+/* RMON_T_P64 Bit Fields */
+#define ENET_RMON_T_P64_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_P64_TXPKTS_SHIFT 0
+#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P64_TXPKTS_SHIFT))&ENET_RMON_T_P64_TXPKTS_MASK)
+/* RMON_T_P65TO127 Bit Fields */
+#define ENET_RMON_T_P65TO127_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT 0
+#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P65TO127_TXPKTS_SHIFT))&ENET_RMON_T_P65TO127_TXPKTS_MASK)
+/* RMON_T_P128TO255 Bit Fields */
+#define ENET_RMON_T_P128TO255_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT 0
+#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P128TO255_TXPKTS_SHIFT))&ENET_RMON_T_P128TO255_TXPKTS_MASK)
+/* RMON_T_P256TO511 Bit Fields */
+#define ENET_RMON_T_P256TO511_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT 0
+#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P256TO511_TXPKTS_SHIFT))&ENET_RMON_T_P256TO511_TXPKTS_MASK)
+/* RMON_T_P512TO1023 Bit Fields */
+#define ENET_RMON_T_P512TO1023_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT 0
+#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P512TO1023_TXPKTS_SHIFT))&ENET_RMON_T_P512TO1023_TXPKTS_MASK)
+/* RMON_T_P1024TO2047 Bit Fields */
+#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT 0
+#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT))&ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
+/* RMON_T_P_GTE2048 Bit Fields */
+#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK 0xFFFFu
+#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT 0
+#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT))&ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
+/* RMON_T_OCTETS Bit Fields */
+#define ENET_RMON_T_OCTETS_TXOCTS_MASK 0xFFFFFFFFu
+#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT 0
+#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OCTETS_TXOCTS_SHIFT))&ENET_RMON_T_OCTETS_TXOCTS_MASK)
+/* IEEE_T_FRAME_OK Bit Fields */
+#define ENET_IEEE_T_FRAME_OK_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT 0
+#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_T_FRAME_OK_COUNT_MASK)
+/* IEEE_T_1COL Bit Fields */
+#define ENET_IEEE_T_1COL_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_T_1COL_COUNT_SHIFT 0
+#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_1COL_COUNT_SHIFT))&ENET_IEEE_T_1COL_COUNT_MASK)
+/* IEEE_T_MCOL Bit Fields */
+#define ENET_IEEE_T_MCOL_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_T_MCOL_COUNT_SHIFT 0
+#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MCOL_COUNT_SHIFT))&ENET_IEEE_T_MCOL_COUNT_MASK)
+/* IEEE_T_DEF Bit Fields */
+#define ENET_IEEE_T_DEF_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_T_DEF_COUNT_SHIFT 0
+#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_DEF_COUNT_SHIFT))&ENET_IEEE_T_DEF_COUNT_MASK)
+/* IEEE_T_LCOL Bit Fields */
+#define ENET_IEEE_T_LCOL_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_T_LCOL_COUNT_SHIFT 0
+#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_LCOL_COUNT_SHIFT))&ENET_IEEE_T_LCOL_COUNT_MASK)
+/* IEEE_T_EXCOL Bit Fields */
+#define ENET_IEEE_T_EXCOL_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_T_EXCOL_COUNT_SHIFT 0
+#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_EXCOL_COUNT_SHIFT))&ENET_IEEE_T_EXCOL_COUNT_MASK)
+/* IEEE_T_MACERR Bit Fields */
+#define ENET_IEEE_T_MACERR_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_T_MACERR_COUNT_SHIFT 0
+#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MACERR_COUNT_SHIFT))&ENET_IEEE_T_MACERR_COUNT_MASK)
+/* IEEE_T_CSERR Bit Fields */
+#define ENET_IEEE_T_CSERR_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_T_CSERR_COUNT_SHIFT 0
+#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_CSERR_COUNT_SHIFT))&ENET_IEEE_T_CSERR_COUNT_MASK)
+/* IEEE_T_FDXFC Bit Fields */
+#define ENET_IEEE_T_FDXFC_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_T_FDXFC_COUNT_SHIFT 0
+#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FDXFC_COUNT_SHIFT))&ENET_IEEE_T_FDXFC_COUNT_MASK)
+/* IEEE_T_OCTETS_OK Bit Fields */
+#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu
+#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT 0
+#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
+/* RMON_R_PACKETS Bit Fields */
+#define ENET_RMON_R_PACKETS_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_PACKETS_COUNT_SHIFT 0
+#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_PACKETS_COUNT_SHIFT))&ENET_RMON_R_PACKETS_COUNT_MASK)
+/* RMON_R_BC_PKT Bit Fields */
+#define ENET_RMON_R_BC_PKT_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_BC_PKT_COUNT_SHIFT 0
+#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_BC_PKT_COUNT_SHIFT))&ENET_RMON_R_BC_PKT_COUNT_MASK)
+/* RMON_R_MC_PKT Bit Fields */
+#define ENET_RMON_R_MC_PKT_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_MC_PKT_COUNT_SHIFT 0
+#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_MC_PKT_COUNT_SHIFT))&ENET_RMON_R_MC_PKT_COUNT_MASK)
+/* RMON_R_CRC_ALIGN Bit Fields */
+#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT 0
+#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT))&ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
+/* RMON_R_UNDERSIZE Bit Fields */
+#define ENET_RMON_R_UNDERSIZE_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT 0
+#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_UNDERSIZE_COUNT_SHIFT))&ENET_RMON_R_UNDERSIZE_COUNT_MASK)
+/* RMON_R_OVERSIZE Bit Fields */
+#define ENET_RMON_R_OVERSIZE_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT 0
+#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OVERSIZE_COUNT_SHIFT))&ENET_RMON_R_OVERSIZE_COUNT_MASK)
+/* RMON_R_FRAG Bit Fields */
+#define ENET_RMON_R_FRAG_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_FRAG_COUNT_SHIFT 0
+#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_FRAG_COUNT_SHIFT))&ENET_RMON_R_FRAG_COUNT_MASK)
+/* RMON_R_JAB Bit Fields */
+#define ENET_RMON_R_JAB_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_JAB_COUNT_SHIFT 0
+#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_JAB_COUNT_SHIFT))&ENET_RMON_R_JAB_COUNT_MASK)
+/* RMON_R_P64 Bit Fields */
+#define ENET_RMON_R_P64_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_P64_COUNT_SHIFT 0
+#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P64_COUNT_SHIFT))&ENET_RMON_R_P64_COUNT_MASK)
+/* RMON_R_P65TO127 Bit Fields */
+#define ENET_RMON_R_P65TO127_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_P65TO127_COUNT_SHIFT 0
+#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P65TO127_COUNT_SHIFT))&ENET_RMON_R_P65TO127_COUNT_MASK)
+/* RMON_R_P128TO255 Bit Fields */
+#define ENET_RMON_R_P128TO255_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_P128TO255_COUNT_SHIFT 0
+#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P128TO255_COUNT_SHIFT))&ENET_RMON_R_P128TO255_COUNT_MASK)
+/* RMON_R_P256TO511 Bit Fields */
+#define ENET_RMON_R_P256TO511_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_P256TO511_COUNT_SHIFT 0
+#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P256TO511_COUNT_SHIFT))&ENET_RMON_R_P256TO511_COUNT_MASK)
+/* RMON_R_P512TO1023 Bit Fields */
+#define ENET_RMON_R_P512TO1023_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_P512TO1023_COUNT_SHIFT 0
+#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P512TO1023_COUNT_SHIFT))&ENET_RMON_R_P512TO1023_COUNT_MASK)
+/* RMON_R_P1024TO2047 Bit Fields */
+#define ENET_RMON_R_P1024TO2047_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT 0
+#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P1024TO2047_COUNT_SHIFT))&ENET_RMON_R_P1024TO2047_COUNT_MASK)
+/* RMON_R_GTE2048 Bit Fields */
+#define ENET_RMON_R_GTE2048_COUNT_MASK 0xFFFFu
+#define ENET_RMON_R_GTE2048_COUNT_SHIFT 0
+#define ENET_RMON_R_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_GTE2048_COUNT_SHIFT))&ENET_RMON_R_GTE2048_COUNT_MASK)
+/* RMON_R_OCTETS Bit Fields */
+#define ENET_RMON_R_OCTETS_COUNT_MASK 0xFFFFFFFFu
+#define ENET_RMON_R_OCTETS_COUNT_SHIFT 0
+#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OCTETS_COUNT_SHIFT))&ENET_RMON_R_OCTETS_COUNT_MASK)
+/* IEEE_R_DROP Bit Fields */
+#define ENET_IEEE_R_DROP_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_R_DROP_COUNT_SHIFT 0
+#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_DROP_COUNT_SHIFT))&ENET_IEEE_R_DROP_COUNT_MASK)
+/* IEEE_R_FRAME_OK Bit Fields */
+#define ENET_IEEE_R_FRAME_OK_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT 0
+#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_R_FRAME_OK_COUNT_MASK)
+/* IEEE_R_CRC Bit Fields */
+#define ENET_IEEE_R_CRC_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_R_CRC_COUNT_SHIFT 0
+#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_CRC_COUNT_SHIFT))&ENET_IEEE_R_CRC_COUNT_MASK)
+/* IEEE_R_ALIGN Bit Fields */
+#define ENET_IEEE_R_ALIGN_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_R_ALIGN_COUNT_SHIFT 0
+#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_ALIGN_COUNT_SHIFT))&ENET_IEEE_R_ALIGN_COUNT_MASK)
+/* IEEE_R_MACERR Bit Fields */
+#define ENET_IEEE_R_MACERR_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_R_MACERR_COUNT_SHIFT 0
+#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_MACERR_COUNT_SHIFT))&ENET_IEEE_R_MACERR_COUNT_MASK)
+/* IEEE_R_FDXFC Bit Fields */
+#define ENET_IEEE_R_FDXFC_COUNT_MASK 0xFFFFu
+#define ENET_IEEE_R_FDXFC_COUNT_SHIFT 0
+#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FDXFC_COUNT_SHIFT))&ENET_IEEE_R_FDXFC_COUNT_MASK)
+/* IEEE_R_OCTETS_OK Bit Fields */
+#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu
+#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT 0
+#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
+/* ATCR Bit Fields */
+#define ENET_ATCR_EN_MASK 0x1u
+#define ENET_ATCR_EN_SHIFT 0
+#define ENET_ATCR_OFFEN_MASK 0x4u
+#define ENET_ATCR_OFFEN_SHIFT 2
+#define ENET_ATCR_OFFRST_MASK 0x8u
+#define ENET_ATCR_OFFRST_SHIFT 3
+#define ENET_ATCR_PEREN_MASK 0x10u
+#define ENET_ATCR_PEREN_SHIFT 4
+#define ENET_ATCR_PINPER_MASK 0x80u
+#define ENET_ATCR_PINPER_SHIFT 7
+#define ENET_ATCR_RESTART_MASK 0x200u
+#define ENET_ATCR_RESTART_SHIFT 9
+#define ENET_ATCR_CAPTURE_MASK 0x800u
+#define ENET_ATCR_CAPTURE_SHIFT 11
+#define ENET_ATCR_SLAVE_MASK 0x2000u
+#define ENET_ATCR_SLAVE_SHIFT 13
+/* ATVR Bit Fields */
+#define ENET_ATVR_ATIME_MASK 0xFFFFFFFFu
+#define ENET_ATVR_ATIME_SHIFT 0
+#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK)
+/* ATOFF Bit Fields */
+#define ENET_ATOFF_OFFSET_MASK 0xFFFFFFFFu
+#define ENET_ATOFF_OFFSET_SHIFT 0
+#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK)
+/* ATPER Bit Fields */
+#define ENET_ATPER_PERIOD_MASK 0xFFFFFFFFu
+#define ENET_ATPER_PERIOD_SHIFT 0
+#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK)
+/* ATCOR Bit Fields */
+#define ENET_ATCOR_COR_MASK 0x7FFFFFFFu
+#define ENET_ATCOR_COR_SHIFT 0
+#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK)
+/* ATINC Bit Fields */
+#define ENET_ATINC_INC_MASK 0x7Fu
+#define ENET_ATINC_INC_SHIFT 0
+#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK)
+#define ENET_ATINC_INC_CORR_MASK 0x7F00u
+#define ENET_ATINC_INC_CORR_SHIFT 8
+#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK)
+/* ATSTMP Bit Fields */
+#define ENET_ATSTMP_TIMESTAMP_MASK 0xFFFFFFFFu
+#define ENET_ATSTMP_TIMESTAMP_SHIFT 0
+#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK)
+/* TGSR Bit Fields */
+#define ENET_TGSR_TF0_MASK 0x1u
+#define ENET_TGSR_TF0_SHIFT 0
+#define ENET_TGSR_TF1_MASK 0x2u
+#define ENET_TGSR_TF1_SHIFT 1
+#define ENET_TGSR_TF2_MASK 0x4u
+#define ENET_TGSR_TF2_SHIFT 2
+#define ENET_TGSR_TF3_MASK 0x8u
+#define ENET_TGSR_TF3_SHIFT 3
+/* TCSR Bit Fields */
+#define ENET_TCSR_TDRE_MASK 0x1u
+#define ENET_TCSR_TDRE_SHIFT 0
+#define ENET_TCSR_TMODE_MASK 0x3Cu
+#define ENET_TCSR_TMODE_SHIFT 2
+#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK)
+#define ENET_TCSR_TIE_MASK 0x40u
+#define ENET_TCSR_TIE_SHIFT 6
+#define ENET_TCSR_TF_MASK 0x80u
+#define ENET_TCSR_TF_SHIFT 7
+/* TCCR Bit Fields */
+#define ENET_TCCR_TCC_MASK 0xFFFFFFFFu
+#define ENET_TCCR_TCC_SHIFT 0
+#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK)
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Masks */
+
+
+/* ENET - Peripheral instance base addresses */
+/** Peripheral ENET base address */
+#define ENET_BASE (0x400C0000u)
+/** Peripheral ENET base pointer */
+#define ENET ((ENET_Type *)ENET_BASE)
+#define ENET_BASE_PTR (ENET)
+/** Array initializer of ENET peripheral base pointers */
+#define ENET_BASES { ENET }
+
+/* ----------------------------------------------------------------------------
+ -- ENET - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
+ * @{
+ */
+
+
+/* ENET - Register instance definitions */
+/* ENET */
+#define ENET_EIR ENET_EIR_REG(ENET)
+#define ENET_EIMR ENET_EIMR_REG(ENET)
+#define ENET_RDAR ENET_RDAR_REG(ENET)
+#define ENET_TDAR ENET_TDAR_REG(ENET)
+#define ENET_ECR ENET_ECR_REG(ENET)
+#define ENET_MMFR ENET_MMFR_REG(ENET)
+#define ENET_MSCR ENET_MSCR_REG(ENET)
+#define ENET_MIBC ENET_MIBC_REG(ENET)
+#define ENET_RCR ENET_RCR_REG(ENET)
+#define ENET_TCR ENET_TCR_REG(ENET)
+#define ENET_PALR ENET_PALR_REG(ENET)
+#define ENET_PAUR ENET_PAUR_REG(ENET)
+#define ENET_OPD ENET_OPD_REG(ENET)
+#define ENET_IAUR ENET_IAUR_REG(ENET)
+#define ENET_IALR ENET_IALR_REG(ENET)
+#define ENET_GAUR ENET_GAUR_REG(ENET)
+#define ENET_GALR ENET_GALR_REG(ENET)
+#define ENET_TFWR ENET_TFWR_REG(ENET)
+#define ENET_RDSR ENET_RDSR_REG(ENET)
+#define ENET_TDSR ENET_TDSR_REG(ENET)
+#define ENET_MRBR ENET_MRBR_REG(ENET)
+#define ENET_RSFL ENET_RSFL_REG(ENET)
+#define ENET_RSEM ENET_RSEM_REG(ENET)
+#define ENET_RAEM ENET_RAEM_REG(ENET)
+#define ENET_RAFL ENET_RAFL_REG(ENET)
+#define ENET_TSEM ENET_TSEM_REG(ENET)
+#define ENET_TAEM ENET_TAEM_REG(ENET)
+#define ENET_TAFL ENET_TAFL_REG(ENET)
+#define ENET_TIPG ENET_TIPG_REG(ENET)
+#define ENET_FTRL ENET_FTRL_REG(ENET)
+#define ENET_TACC ENET_TACC_REG(ENET)
+#define ENET_RACC ENET_RACC_REG(ENET)
+#define ENET_RMON_T_PACKETS ENET_RMON_T_PACKETS_REG(ENET)
+#define ENET_RMON_T_BC_PKT ENET_RMON_T_BC_PKT_REG(ENET)
+#define ENET_RMON_T_MC_PKT ENET_RMON_T_MC_PKT_REG(ENET)
+#define ENET_RMON_T_CRC_ALIGN ENET_RMON_T_CRC_ALIGN_REG(ENET)
+#define ENET_RMON_T_UNDERSIZE ENET_RMON_T_UNDERSIZE_REG(ENET)
+#define ENET_RMON_T_OVERSIZE ENET_RMON_T_OVERSIZE_REG(ENET)
+#define ENET_RMON_T_FRAG ENET_RMON_T_FRAG_REG(ENET)
+#define ENET_RMON_T_JAB ENET_RMON_T_JAB_REG(ENET)
+#define ENET_RMON_T_COL ENET_RMON_T_COL_REG(ENET)
+#define ENET_RMON_T_P64 ENET_RMON_T_P64_REG(ENET)
+#define ENET_RMON_T_P65TO127 ENET_RMON_T_P65TO127_REG(ENET)
+#define ENET_RMON_T_P128TO255 ENET_RMON_T_P128TO255_REG(ENET)
+#define ENET_RMON_T_P256TO511 ENET_RMON_T_P256TO511_REG(ENET)
+#define ENET_RMON_T_P512TO1023 ENET_RMON_T_P512TO1023_REG(ENET)
+#define ENET_RMON_T_P1024TO2047 ENET_RMON_T_P1024TO2047_REG(ENET)
+#define ENET_RMON_T_P_GTE2048 ENET_RMON_T_P_GTE2048_REG(ENET)
+#define ENET_RMON_T_OCTETS ENET_RMON_T_OCTETS_REG(ENET)
+#define ENET_IEEE_T_FRAME_OK ENET_IEEE_T_FRAME_OK_REG(ENET)
+#define ENET_IEEE_T_1COL ENET_IEEE_T_1COL_REG(ENET)
+#define ENET_IEEE_T_MCOL ENET_IEEE_T_MCOL_REG(ENET)
+#define ENET_IEEE_T_DEF ENET_IEEE_T_DEF_REG(ENET)
+#define ENET_IEEE_T_LCOL ENET_IEEE_T_LCOL_REG(ENET)
+#define ENET_IEEE_T_EXCOL ENET_IEEE_T_EXCOL_REG(ENET)
+#define ENET_IEEE_T_MACERR ENET_IEEE_T_MACERR_REG(ENET)
+#define ENET_IEEE_T_CSERR ENET_IEEE_T_CSERR_REG(ENET)
+#define ENET_IEEE_T_FDXFC ENET_IEEE_T_FDXFC_REG(ENET)
+#define ENET_IEEE_T_OCTETS_OK ENET_IEEE_T_OCTETS_OK_REG(ENET)
+#define ENET_RMON_R_PACKETS ENET_RMON_R_PACKETS_REG(ENET)
+#define ENET_RMON_R_BC_PKT ENET_RMON_R_BC_PKT_REG(ENET)
+#define ENET_RMON_R_MC_PKT ENET_RMON_R_MC_PKT_REG(ENET)
+#define ENET_RMON_R_CRC_ALIGN ENET_RMON_R_CRC_ALIGN_REG(ENET)
+#define ENET_RMON_R_UNDERSIZE ENET_RMON_R_UNDERSIZE_REG(ENET)
+#define ENET_RMON_R_OVERSIZE ENET_RMON_R_OVERSIZE_REG(ENET)
+#define ENET_RMON_R_FRAG ENET_RMON_R_FRAG_REG(ENET)
+#define ENET_RMON_R_JAB ENET_RMON_R_JAB_REG(ENET)
+#define ENET_RMON_R_P64 ENET_RMON_R_P64_REG(ENET)
+#define ENET_RMON_R_P65TO127 ENET_RMON_R_P65TO127_REG(ENET)
+#define ENET_RMON_R_P128TO255 ENET_RMON_R_P128TO255_REG(ENET)
+#define ENET_RMON_R_P256TO511 ENET_RMON_R_P256TO511_REG(ENET)
+#define ENET_RMON_R_P512TO1023 ENET_RMON_R_P512TO1023_REG(ENET)
+#define ENET_RMON_R_P1024TO2047 ENET_RMON_R_P1024TO2047_REG(ENET)
+#define ENET_RMON_R_GTE2048 ENET_RMON_R_GTE2048_REG(ENET)
+#define ENET_RMON_R_OCTETS ENET_RMON_R_OCTETS_REG(ENET)
+#define ENET_IEEE_R_DROP ENET_IEEE_R_DROP_REG(ENET)
+#define ENET_IEEE_R_FRAME_OK ENET_IEEE_R_FRAME_OK_REG(ENET)
+#define ENET_IEEE_R_CRC ENET_IEEE_R_CRC_REG(ENET)
+#define ENET_IEEE_R_ALIGN ENET_IEEE_R_ALIGN_REG(ENET)
+#define ENET_IEEE_R_MACERR ENET_IEEE_R_MACERR_REG(ENET)
+#define ENET_IEEE_R_FDXFC ENET_IEEE_R_FDXFC_REG(ENET)
+#define ENET_IEEE_R_OCTETS_OK ENET_IEEE_R_OCTETS_OK_REG(ENET)
+#define ENET_ATCR ENET_ATCR_REG(ENET)
+#define ENET_ATVR ENET_ATVR_REG(ENET)
+#define ENET_ATOFF ENET_ATOFF_REG(ENET)
+#define ENET_ATPER ENET_ATPER_REG(ENET)
+#define ENET_ATCOR ENET_ATCOR_REG(ENET)
+#define ENET_ATINC ENET_ATINC_REG(ENET)
+#define ENET_ATSTMP ENET_ATSTMP_REG(ENET)
+#define ENET_TGSR ENET_TGSR_REG(ENET)
+#define ENET_TCSR0 ENET_TCSR_REG(ENET,0)
+#define ENET_TCCR0 ENET_TCCR_REG(ENET,0)
+#define ENET_TCSR1 ENET_TCSR_REG(ENET,1)
+#define ENET_TCCR1 ENET_TCCR_REG(ENET,1)
+#define ENET_TCSR2 ENET_TCSR_REG(ENET,2)
+#define ENET_TCCR2 ENET_TCCR_REG(ENET,2)
+#define ENET_TCSR3 ENET_TCSR_REG(ENET,3)
+#define ENET_TCCR3 ENET_TCCR_REG(ENET,3)
+
+/* ENET - Register array accessors */
+#define ENET_TCSR(index) ENET_TCSR_REG(ENET,index)
+#define ENET_TCCR(index) ENET_TCCR_REG(ENET,index)
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ENET_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- EWM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
+ * @{
+ */
+
+/** EWM - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
+ __O uint8_t SERV; /**< Service Register, offset: 0x1 */
+ __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
+ __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
+} EWM_Type, *EWM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- EWM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
+ * @{
+ */
+
+
+/* EWM - Register accessors */
+#define EWM_CTRL_REG(base) ((base)->CTRL)
+#define EWM_SERV_REG(base) ((base)->SERV)
+#define EWM_CMPL_REG(base) ((base)->CMPL)
+#define EWM_CMPH_REG(base) ((base)->CMPH)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- EWM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Masks EWM Register Masks
+ * @{
+ */
+
+/* CTRL Bit Fields */
+#define EWM_CTRL_EWMEN_MASK 0x1u
+#define EWM_CTRL_EWMEN_SHIFT 0
+#define EWM_CTRL_ASSIN_MASK 0x2u
+#define EWM_CTRL_ASSIN_SHIFT 1
+#define EWM_CTRL_INEN_MASK 0x4u
+#define EWM_CTRL_INEN_SHIFT 2
+#define EWM_CTRL_INTEN_MASK 0x8u
+#define EWM_CTRL_INTEN_SHIFT 3
+/* SERV Bit Fields */
+#define EWM_SERV_SERVICE_MASK 0xFFu
+#define EWM_SERV_SERVICE_SHIFT 0
+#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
+/* CMPL Bit Fields */
+#define EWM_CMPL_COMPAREL_MASK 0xFFu
+#define EWM_CMPL_COMPAREL_SHIFT 0
+#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
+/* CMPH Bit Fields */
+#define EWM_CMPH_COMPAREH_MASK 0xFFu
+#define EWM_CMPH_COMPAREH_SHIFT 0
+#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Masks */
+
+
+/* EWM - Peripheral instance base addresses */
+/** Peripheral EWM base address */
+#define EWM_BASE (0x40061000u)
+/** Peripheral EWM base pointer */
+#define EWM ((EWM_Type *)EWM_BASE)
+#define EWM_BASE_PTR (EWM)
+/** Array initializer of EWM peripheral base pointers */
+#define EWM_BASES { EWM }
+
+/* ----------------------------------------------------------------------------
+ -- EWM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
+ * @{
+ */
+
+
+/* EWM - Register instance definitions */
+/* EWM */
+#define EWM_CTRL EWM_CTRL_REG(EWM)
+#define EWM_SERV EWM_SERV_REG(EWM)
+#define EWM_CMPL EWM_CMPL_REG(EWM)
+#define EWM_CMPH EWM_CMPH_REG(EWM)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group EWM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
+ * @{
+ */
+
+/** FB - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0xC */
+ __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
+ __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
+ __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
+ } CS[6];
+ uint8_t RESERVED_0[24];
+ __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
+} FB_Type, *FB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- FB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
+ * @{
+ */
+
+
+/* FB - Register accessors */
+#define FB_CSAR_REG(base,index) ((base)->CS[index].CSAR)
+#define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR)
+#define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR)
+#define FB_CSPMCR_REG(base) ((base)->CSPMCR)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- FB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Masks FB Register Masks
+ * @{
+ */
+
+/* CSAR Bit Fields */
+#define FB_CSAR_BA_MASK 0xFFFF0000u
+#define FB_CSAR_BA_SHIFT 16
+#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
+/* CSMR Bit Fields */
+#define FB_CSMR_V_MASK 0x1u
+#define FB_CSMR_V_SHIFT 0
+#define FB_CSMR_WP_MASK 0x100u
+#define FB_CSMR_WP_SHIFT 8
+#define FB_CSMR_BAM_MASK 0xFFFF0000u
+#define FB_CSMR_BAM_SHIFT 16
+#define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
+/* CSCR Bit Fields */
+#define FB_CSCR_BSTW_MASK 0x8u
+#define FB_CSCR_BSTW_SHIFT 3
+#define FB_CSCR_BSTR_MASK 0x10u
+#define FB_CSCR_BSTR_SHIFT 4
+#define FB_CSCR_BEM_MASK 0x20u
+#define FB_CSCR_BEM_SHIFT 5
+#define FB_CSCR_PS_MASK 0xC0u
+#define FB_CSCR_PS_SHIFT 6
+#define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
+#define FB_CSCR_AA_MASK 0x100u
+#define FB_CSCR_AA_SHIFT 8
+#define FB_CSCR_BLS_MASK 0x200u
+#define FB_CSCR_BLS_SHIFT 9
+#define FB_CSCR_WS_MASK 0xFC00u
+#define FB_CSCR_WS_SHIFT 10
+#define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
+#define FB_CSCR_WRAH_MASK 0x30000u
+#define FB_CSCR_WRAH_SHIFT 16
+#define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
+#define FB_CSCR_RDAH_MASK 0xC0000u
+#define FB_CSCR_RDAH_SHIFT 18
+#define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
+#define FB_CSCR_ASET_MASK 0x300000u
+#define FB_CSCR_ASET_SHIFT 20
+#define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
+#define FB_CSCR_EXTS_MASK 0x400000u
+#define FB_CSCR_EXTS_SHIFT 22
+#define FB_CSCR_SWSEN_MASK 0x800000u
+#define FB_CSCR_SWSEN_SHIFT 23
+#define FB_CSCR_SWS_MASK 0xFC000000u
+#define FB_CSCR_SWS_SHIFT 26
+#define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
+/* CSPMCR Bit Fields */
+#define FB_CSPMCR_GROUP5_MASK 0xF000u
+#define FB_CSPMCR_GROUP5_SHIFT 12
+#define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
+#define FB_CSPMCR_GROUP4_MASK 0xF0000u
+#define FB_CSPMCR_GROUP4_SHIFT 16
+#define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
+#define FB_CSPMCR_GROUP3_MASK 0xF00000u
+#define FB_CSPMCR_GROUP3_SHIFT 20
+#define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
+#define FB_CSPMCR_GROUP2_MASK 0xF000000u
+#define FB_CSPMCR_GROUP2_SHIFT 24
+#define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
+#define FB_CSPMCR_GROUP1_MASK 0xF0000000u
+#define FB_CSPMCR_GROUP1_SHIFT 28
+#define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Masks */
+
+
+/* FB - Peripheral instance base addresses */
+/** Peripheral FB base address */
+#define FB_BASE (0x4000C000u)
+/** Peripheral FB base pointer */
+#define FB ((FB_Type *)FB_BASE)
+#define FB_BASE_PTR (FB)
+/** Array initializer of FB peripheral base pointers */
+#define FB_BASES { FB }
+
+/* ----------------------------------------------------------------------------
+ -- FB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
+ * @{
+ */
+
+
+/* FB - Register instance definitions */
+/* FB */
+#define FB_CSAR0 FB_CSAR_REG(FB,0)
+#define FB_CSMR0 FB_CSMR_REG(FB,0)
+#define FB_CSCR0 FB_CSCR_REG(FB,0)
+#define FB_CSAR1 FB_CSAR_REG(FB,1)
+#define FB_CSMR1 FB_CSMR_REG(FB,1)
+#define FB_CSCR1 FB_CSCR_REG(FB,1)
+#define FB_CSAR2 FB_CSAR_REG(FB,2)
+#define FB_CSMR2 FB_CSMR_REG(FB,2)
+#define FB_CSCR2 FB_CSCR_REG(FB,2)
+#define FB_CSAR3 FB_CSAR_REG(FB,3)
+#define FB_CSMR3 FB_CSMR_REG(FB,3)
+#define FB_CSCR3 FB_CSCR_REG(FB,3)
+#define FB_CSAR4 FB_CSAR_REG(FB,4)
+#define FB_CSMR4 FB_CSMR_REG(FB,4)
+#define FB_CSCR4 FB_CSCR_REG(FB,4)
+#define FB_CSAR5 FB_CSAR_REG(FB,5)
+#define FB_CSMR5 FB_CSMR_REG(FB,5)
+#define FB_CSCR5 FB_CSCR_REG(FB,5)
+#define FB_CSPMCR FB_CSPMCR_REG(FB)
+
+/* FB - Register array accessors */
+#define FB_CSAR(index) FB_CSAR_REG(FB,index)
+#define FB_CSMR(index) FB_CSMR_REG(FB,index)
+#define FB_CSCR(index) FB_CSCR_REG(FB,index)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
+ * @{
+ */
+
+/** FMC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
+ __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */
+ __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */
+ uint8_t RESERVED_0[244];
+ __IO uint32_t TAGVDW0S[4]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
+ __IO uint32_t TAGVDW1S[4]; /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */
+ __IO uint32_t TAGVDW2S[4]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
+ __IO uint32_t TAGVDW3S[4]; /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */
+ uint8_t RESERVED_1[192];
+ struct { /* offset: 0x200, array step: index*0x20, index2*0x8 */
+ __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8 */
+ __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8 */
+ } SET[4][4];
+} FMC_Type, *FMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- FMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
+ * @{
+ */
+
+
+/* FMC - Register accessors */
+#define FMC_PFAPR_REG(base) ((base)->PFAPR)
+#define FMC_PFB0CR_REG(base) ((base)->PFB0CR)
+#define FMC_PFB1CR_REG(base) ((base)->PFB1CR)
+#define FMC_TAGVDW0S_REG(base,index) ((base)->TAGVDW0S[index])
+#define FMC_TAGVDW1S_REG(base,index) ((base)->TAGVDW1S[index])
+#define FMC_TAGVDW2S_REG(base,index) ((base)->TAGVDW2S[index])
+#define FMC_TAGVDW3S_REG(base,index) ((base)->TAGVDW3S[index])
+#define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U)
+#define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L)
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- FMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Masks FMC Register Masks
+ * @{
+ */
+
+/* PFAPR Bit Fields */
+#define FMC_PFAPR_M0AP_MASK 0x3u
+#define FMC_PFAPR_M0AP_SHIFT 0
+#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
+#define FMC_PFAPR_M1AP_MASK 0xCu
+#define FMC_PFAPR_M1AP_SHIFT 2
+#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
+#define FMC_PFAPR_M2AP_MASK 0x30u
+#define FMC_PFAPR_M2AP_SHIFT 4
+#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
+#define FMC_PFAPR_M3AP_MASK 0xC0u
+#define FMC_PFAPR_M3AP_SHIFT 6
+#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
+#define FMC_PFAPR_M4AP_MASK 0x300u
+#define FMC_PFAPR_M4AP_SHIFT 8
+#define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
+#define FMC_PFAPR_M5AP_MASK 0xC00u
+#define FMC_PFAPR_M5AP_SHIFT 10
+#define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
+#define FMC_PFAPR_M6AP_MASK 0x3000u
+#define FMC_PFAPR_M6AP_SHIFT 12
+#define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
+#define FMC_PFAPR_M7AP_MASK 0xC000u
+#define FMC_PFAPR_M7AP_SHIFT 14
+#define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
+#define FMC_PFAPR_M0PFD_MASK 0x10000u
+#define FMC_PFAPR_M0PFD_SHIFT 16
+#define FMC_PFAPR_M1PFD_MASK 0x20000u
+#define FMC_PFAPR_M1PFD_SHIFT 17
+#define FMC_PFAPR_M2PFD_MASK 0x40000u
+#define FMC_PFAPR_M2PFD_SHIFT 18
+#define FMC_PFAPR_M3PFD_MASK 0x80000u
+#define FMC_PFAPR_M3PFD_SHIFT 19
+#define FMC_PFAPR_M4PFD_MASK 0x100000u
+#define FMC_PFAPR_M4PFD_SHIFT 20
+#define FMC_PFAPR_M5PFD_MASK 0x200000u
+#define FMC_PFAPR_M5PFD_SHIFT 21
+#define FMC_PFAPR_M6PFD_MASK 0x400000u
+#define FMC_PFAPR_M6PFD_SHIFT 22
+#define FMC_PFAPR_M7PFD_MASK 0x800000u
+#define FMC_PFAPR_M7PFD_SHIFT 23
+/* PFB0CR Bit Fields */
+#define FMC_PFB0CR_B0SEBE_MASK 0x1u
+#define FMC_PFB0CR_B0SEBE_SHIFT 0
+#define FMC_PFB0CR_B0IPE_MASK 0x2u
+#define FMC_PFB0CR_B0IPE_SHIFT 1
+#define FMC_PFB0CR_B0DPE_MASK 0x4u
+#define FMC_PFB0CR_B0DPE_SHIFT 2
+#define FMC_PFB0CR_B0ICE_MASK 0x8u
+#define FMC_PFB0CR_B0ICE_SHIFT 3
+#define FMC_PFB0CR_B0DCE_MASK 0x10u
+#define FMC_PFB0CR_B0DCE_SHIFT 4
+#define FMC_PFB0CR_CRC_MASK 0xE0u
+#define FMC_PFB0CR_CRC_SHIFT 5
+#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
+#define FMC_PFB0CR_B0MW_MASK 0x60000u
+#define FMC_PFB0CR_B0MW_SHIFT 17
+#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
+#define FMC_PFB0CR_S_B_INV_MASK 0x80000u
+#define FMC_PFB0CR_S_B_INV_SHIFT 19
+#define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
+#define FMC_PFB0CR_CINV_WAY_SHIFT 20
+#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
+#define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
+#define FMC_PFB0CR_CLCK_WAY_SHIFT 24
+#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
+#define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
+#define FMC_PFB0CR_B0RWSC_SHIFT 28
+#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
+/* PFB1CR Bit Fields */
+#define FMC_PFB1CR_B1SEBE_MASK 0x1u
+#define FMC_PFB1CR_B1SEBE_SHIFT 0
+#define FMC_PFB1CR_B1IPE_MASK 0x2u
+#define FMC_PFB1CR_B1IPE_SHIFT 1
+#define FMC_PFB1CR_B1DPE_MASK 0x4u
+#define FMC_PFB1CR_B1DPE_SHIFT 2
+#define FMC_PFB1CR_B1ICE_MASK 0x8u
+#define FMC_PFB1CR_B1ICE_SHIFT 3
+#define FMC_PFB1CR_B1DCE_MASK 0x10u
+#define FMC_PFB1CR_B1DCE_SHIFT 4
+#define FMC_PFB1CR_B1MW_MASK 0x60000u
+#define FMC_PFB1CR_B1MW_SHIFT 17
+#define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
+#define FMC_PFB1CR_B1RWSC_MASK 0xF0000000u
+#define FMC_PFB1CR_B1RWSC_SHIFT 28
+#define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
+/* TAGVDW0S Bit Fields */
+#define FMC_TAGVDW0S_valid_MASK 0x1u
+#define FMC_TAGVDW0S_valid_SHIFT 0
+#define FMC_TAGVDW0S_tag_MASK 0x7FFE0u
+#define FMC_TAGVDW0S_tag_SHIFT 5
+#define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_tag_SHIFT))&FMC_TAGVDW0S_tag_MASK)
+/* TAGVDW1S Bit Fields */
+#define FMC_TAGVDW1S_valid_MASK 0x1u
+#define FMC_TAGVDW1S_valid_SHIFT 0
+#define FMC_TAGVDW1S_tag_MASK 0x7FFE0u
+#define FMC_TAGVDW1S_tag_SHIFT 5
+#define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_tag_SHIFT))&FMC_TAGVDW1S_tag_MASK)
+/* TAGVDW2S Bit Fields */
+#define FMC_TAGVDW2S_valid_MASK 0x1u
+#define FMC_TAGVDW2S_valid_SHIFT 0
+#define FMC_TAGVDW2S_tag_MASK 0x7FFE0u
+#define FMC_TAGVDW2S_tag_SHIFT 5
+#define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_tag_SHIFT))&FMC_TAGVDW2S_tag_MASK)
+/* TAGVDW3S Bit Fields */
+#define FMC_TAGVDW3S_valid_MASK 0x1u
+#define FMC_TAGVDW3S_valid_SHIFT 0
+#define FMC_TAGVDW3S_tag_MASK 0x7FFE0u
+#define FMC_TAGVDW3S_tag_SHIFT 5
+#define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_tag_SHIFT))&FMC_TAGVDW3S_tag_MASK)
+/* DATA_U Bit Fields */
+#define FMC_DATA_U_data_MASK 0xFFFFFFFFu
+#define FMC_DATA_U_data_SHIFT 0
+#define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
+/* DATA_L Bit Fields */
+#define FMC_DATA_L_data_MASK 0xFFFFFFFFu
+#define FMC_DATA_L_data_SHIFT 0
+#define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Masks */
+
+
+/* FMC - Peripheral instance base addresses */
+/** Peripheral FMC base address */
+#define FMC_BASE (0x4001F000u)
+/** Peripheral FMC base pointer */
+#define FMC ((FMC_Type *)FMC_BASE)
+#define FMC_BASE_PTR (FMC)
+/** Array initializer of FMC peripheral base pointers */
+#define FMC_BASES { FMC }
+
+/* ----------------------------------------------------------------------------
+ -- FMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
+ * @{
+ */
+
+
+/* FMC - Register instance definitions */
+/* FMC */
+#define FMC_PFAPR FMC_PFAPR_REG(FMC)
+#define FMC_PFB0CR FMC_PFB0CR_REG(FMC)
+#define FMC_PFB1CR FMC_PFB1CR_REG(FMC)
+#define FMC_TAGVDW0S0 FMC_TAGVDW0S_REG(FMC,0)
+#define FMC_TAGVDW0S1 FMC_TAGVDW0S_REG(FMC,1)
+#define FMC_TAGVDW0S2 FMC_TAGVDW0S_REG(FMC,2)
+#define FMC_TAGVDW0S3 FMC_TAGVDW0S_REG(FMC,3)
+#define FMC_TAGVDW1S0 FMC_TAGVDW1S_REG(FMC,0)
+#define FMC_TAGVDW1S1 FMC_TAGVDW1S_REG(FMC,1)
+#define FMC_TAGVDW1S2 FMC_TAGVDW1S_REG(FMC,2)
+#define FMC_TAGVDW1S3 FMC_TAGVDW1S_REG(FMC,3)
+#define FMC_TAGVDW2S0 FMC_TAGVDW2S_REG(FMC,0)
+#define FMC_TAGVDW2S1 FMC_TAGVDW2S_REG(FMC,1)
+#define FMC_TAGVDW2S2 FMC_TAGVDW2S_REG(FMC,2)
+#define FMC_TAGVDW2S3 FMC_TAGVDW2S_REG(FMC,3)
+#define FMC_TAGVDW3S0 FMC_TAGVDW3S_REG(FMC,0)
+#define FMC_TAGVDW3S1 FMC_TAGVDW3S_REG(FMC,1)
+#define FMC_TAGVDW3S2 FMC_TAGVDW3S_REG(FMC,2)
+#define FMC_TAGVDW3S3 FMC_TAGVDW3S_REG(FMC,3)
+#define FMC_DATAW0S0U FMC_DATA_U_REG(FMC,0,0)
+#define FMC_DATAW0S0L FMC_DATA_L_REG(FMC,0,0)
+#define FMC_DATAW0S1U FMC_DATA_U_REG(FMC,0,1)
+#define FMC_DATAW0S1L FMC_DATA_L_REG(FMC,0,1)
+#define FMC_DATAW0S2U FMC_DATA_U_REG(FMC,0,2)
+#define FMC_DATAW0S2L FMC_DATA_L_REG(FMC,0,2)
+#define FMC_DATAW0S3U FMC_DATA_U_REG(FMC,0,3)
+#define FMC_DATAW0S3L FMC_DATA_L_REG(FMC,0,3)
+#define FMC_DATAW1S0U FMC_DATA_U_REG(FMC,1,0)
+#define FMC_DATAW1S0L FMC_DATA_L_REG(FMC,1,0)
+#define FMC_DATAW1S1U FMC_DATA_U_REG(FMC,1,1)
+#define FMC_DATAW1S1L FMC_DATA_L_REG(FMC,1,1)
+#define FMC_DATAW1S2U FMC_DATA_U_REG(FMC,1,2)
+#define FMC_DATAW1S2L FMC_DATA_L_REG(FMC,1,2)
+#define FMC_DATAW1S3U FMC_DATA_U_REG(FMC,1,3)
+#define FMC_DATAW1S3L FMC_DATA_L_REG(FMC,1,3)
+#define FMC_DATAW2S0U FMC_DATA_U_REG(FMC,2,0)
+#define FMC_DATAW2S0L FMC_DATA_L_REG(FMC,2,0)
+#define FMC_DATAW2S1U FMC_DATA_U_REG(FMC,2,1)
+#define FMC_DATAW2S1L FMC_DATA_L_REG(FMC,2,1)
+#define FMC_DATAW2S2U FMC_DATA_U_REG(FMC,2,2)
+#define FMC_DATAW2S2L FMC_DATA_L_REG(FMC,2,2)
+#define FMC_DATAW2S3U FMC_DATA_U_REG(FMC,2,3)
+#define FMC_DATAW2S3L FMC_DATA_L_REG(FMC,2,3)
+#define FMC_DATAW3S0U FMC_DATA_U_REG(FMC,3,0)
+#define FMC_DATAW3S0L FMC_DATA_L_REG(FMC,3,0)
+#define FMC_DATAW3S1U FMC_DATA_U_REG(FMC,3,1)
+#define FMC_DATAW3S1L FMC_DATA_L_REG(FMC,3,1)
+#define FMC_DATAW3S2U FMC_DATA_U_REG(FMC,3,2)
+#define FMC_DATAW3S2L FMC_DATA_L_REG(FMC,3,2)
+#define FMC_DATAW3S3U FMC_DATA_U_REG(FMC,3,3)
+#define FMC_DATAW3S3L FMC_DATA_L_REG(FMC,3,3)
+
+/* FMC - Register array accessors */
+#define FMC_TAGVDW0S(index) FMC_TAGVDW0S_REG(FMC,index)
+#define FMC_TAGVDW1S(index) FMC_TAGVDW1S_REG(FMC,index)
+#define FMC_TAGVDW2S(index) FMC_TAGVDW2S_REG(FMC,index)
+#define FMC_TAGVDW3S(index) FMC_TAGVDW3S_REG(FMC,index)
+#define FMC_DATA_U(index,index2) FMC_DATA_U_REG(FMC,index,index2)
+#define FMC_DATA_L(index,index2) FMC_DATA_L_REG(FMC,index,index2)
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFE Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
+ * @{
+ */
+
+/** FTFE - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
+ __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
+ __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
+ __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
+ __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
+ __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
+ __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
+ __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
+ __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
+ __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
+ __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
+ __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
+ __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
+ __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
+ __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
+ __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
+ __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
+ __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
+ __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
+ __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
+ __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
+} FTFE_Type, *FTFE_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- FTFE - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
+ * @{
+ */
+
+
+/* FTFE - Register accessors */
+#define FTFE_FSTAT_REG(base) ((base)->FSTAT)
+#define FTFE_FCNFG_REG(base) ((base)->FCNFG)
+#define FTFE_FSEC_REG(base) ((base)->FSEC)
+#define FTFE_FOPT_REG(base) ((base)->FOPT)
+#define FTFE_FCCOB3_REG(base) ((base)->FCCOB3)
+#define FTFE_FCCOB2_REG(base) ((base)->FCCOB2)
+#define FTFE_FCCOB1_REG(base) ((base)->FCCOB1)
+#define FTFE_FCCOB0_REG(base) ((base)->FCCOB0)
+#define FTFE_FCCOB7_REG(base) ((base)->FCCOB7)
+#define FTFE_FCCOB6_REG(base) ((base)->FCCOB6)
+#define FTFE_FCCOB5_REG(base) ((base)->FCCOB5)
+#define FTFE_FCCOB4_REG(base) ((base)->FCCOB4)
+#define FTFE_FCCOBB_REG(base) ((base)->FCCOBB)
+#define FTFE_FCCOBA_REG(base) ((base)->FCCOBA)
+#define FTFE_FCCOB9_REG(base) ((base)->FCCOB9)
+#define FTFE_FCCOB8_REG(base) ((base)->FCCOB8)
+#define FTFE_FPROT3_REG(base) ((base)->FPROT3)
+#define FTFE_FPROT2_REG(base) ((base)->FPROT2)
+#define FTFE_FPROT1_REG(base) ((base)->FPROT1)
+#define FTFE_FPROT0_REG(base) ((base)->FPROT0)
+#define FTFE_FEPROT_REG(base) ((base)->FEPROT)
+#define FTFE_FDPROT_REG(base) ((base)->FDPROT)
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFE Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Masks FTFE Register Masks
+ * @{
+ */
+
+/* FSTAT Bit Fields */
+#define FTFE_FSTAT_MGSTAT0_MASK 0x1u
+#define FTFE_FSTAT_MGSTAT0_SHIFT 0
+#define FTFE_FSTAT_FPVIOL_MASK 0x10u
+#define FTFE_FSTAT_FPVIOL_SHIFT 4
+#define FTFE_FSTAT_ACCERR_MASK 0x20u
+#define FTFE_FSTAT_ACCERR_SHIFT 5
+#define FTFE_FSTAT_RDCOLERR_MASK 0x40u
+#define FTFE_FSTAT_RDCOLERR_SHIFT 6
+#define FTFE_FSTAT_CCIF_MASK 0x80u
+#define FTFE_FSTAT_CCIF_SHIFT 7
+/* FCNFG Bit Fields */
+#define FTFE_FCNFG_EEERDY_MASK 0x1u
+#define FTFE_FCNFG_EEERDY_SHIFT 0
+#define FTFE_FCNFG_RAMRDY_MASK 0x2u
+#define FTFE_FCNFG_RAMRDY_SHIFT 1
+#define FTFE_FCNFG_PFLSH_MASK 0x4u
+#define FTFE_FCNFG_PFLSH_SHIFT 2
+#define FTFE_FCNFG_SWAP_MASK 0x8u
+#define FTFE_FCNFG_SWAP_SHIFT 3
+#define FTFE_FCNFG_ERSSUSP_MASK 0x10u
+#define FTFE_FCNFG_ERSSUSP_SHIFT 4
+#define FTFE_FCNFG_ERSAREQ_MASK 0x20u
+#define FTFE_FCNFG_ERSAREQ_SHIFT 5
+#define FTFE_FCNFG_RDCOLLIE_MASK 0x40u
+#define FTFE_FCNFG_RDCOLLIE_SHIFT 6
+#define FTFE_FCNFG_CCIE_MASK 0x80u
+#define FTFE_FCNFG_CCIE_SHIFT 7
+/* FSEC Bit Fields */
+#define FTFE_FSEC_SEC_MASK 0x3u
+#define FTFE_FSEC_SEC_SHIFT 0
+#define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_SEC_SHIFT))&FTFE_FSEC_SEC_MASK)
+#define FTFE_FSEC_FSLACC_MASK 0xCu
+#define FTFE_FSEC_FSLACC_SHIFT 2
+#define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_FSLACC_SHIFT))&FTFE_FSEC_FSLACC_MASK)
+#define FTFE_FSEC_MEEN_MASK 0x30u
+#define FTFE_FSEC_MEEN_SHIFT 4
+#define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_MEEN_SHIFT))&FTFE_FSEC_MEEN_MASK)
+#define FTFE_FSEC_KEYEN_MASK 0xC0u
+#define FTFE_FSEC_KEYEN_SHIFT 6
+#define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_KEYEN_SHIFT))&FTFE_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define FTFE_FOPT_OPT_MASK 0xFFu
+#define FTFE_FOPT_OPT_SHIFT 0
+#define FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FOPT_OPT_SHIFT))&FTFE_FOPT_OPT_MASK)
+/* FCCOB3 Bit Fields */
+#define FTFE_FCCOB3_CCOBn_MASK 0xFFu
+#define FTFE_FCCOB3_CCOBn_SHIFT 0
+#define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB3_CCOBn_SHIFT))&FTFE_FCCOB3_CCOBn_MASK)
+/* FCCOB2 Bit Fields */
+#define FTFE_FCCOB2_CCOBn_MASK 0xFFu
+#define FTFE_FCCOB2_CCOBn_SHIFT 0
+#define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB2_CCOBn_SHIFT))&FTFE_FCCOB2_CCOBn_MASK)
+/* FCCOB1 Bit Fields */
+#define FTFE_FCCOB1_CCOBn_MASK 0xFFu
+#define FTFE_FCCOB1_CCOBn_SHIFT 0
+#define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB1_CCOBn_SHIFT))&FTFE_FCCOB1_CCOBn_MASK)
+/* FCCOB0 Bit Fields */
+#define FTFE_FCCOB0_CCOBn_MASK 0xFFu
+#define FTFE_FCCOB0_CCOBn_SHIFT 0
+#define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB0_CCOBn_SHIFT))&FTFE_FCCOB0_CCOBn_MASK)
+/* FCCOB7 Bit Fields */
+#define FTFE_FCCOB7_CCOBn_MASK 0xFFu
+#define FTFE_FCCOB7_CCOBn_SHIFT 0
+#define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB7_CCOBn_SHIFT))&FTFE_FCCOB7_CCOBn_MASK)
+/* FCCOB6 Bit Fields */
+#define FTFE_FCCOB6_CCOBn_MASK 0xFFu
+#define FTFE_FCCOB6_CCOBn_SHIFT 0
+#define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB6_CCOBn_SHIFT))&FTFE_FCCOB6_CCOBn_MASK)
+/* FCCOB5 Bit Fields */
+#define FTFE_FCCOB5_CCOBn_MASK 0xFFu
+#define FTFE_FCCOB5_CCOBn_SHIFT 0
+#define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB5_CCOBn_SHIFT))&FTFE_FCCOB5_CCOBn_MASK)
+/* FCCOB4 Bit Fields */
+#define FTFE_FCCOB4_CCOBn_MASK 0xFFu
+#define FTFE_FCCOB4_CCOBn_SHIFT 0
+#define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB4_CCOBn_SHIFT))&FTFE_FCCOB4_CCOBn_MASK)
+/* FCCOBB Bit Fields */
+#define FTFE_FCCOBB_CCOBn_MASK 0xFFu
+#define FTFE_FCCOBB_CCOBn_SHIFT 0
+#define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBB_CCOBn_SHIFT))&FTFE_FCCOBB_CCOBn_MASK)
+/* FCCOBA Bit Fields */
+#define FTFE_FCCOBA_CCOBn_MASK 0xFFu
+#define FTFE_FCCOBA_CCOBn_SHIFT 0
+#define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBA_CCOBn_SHIFT))&FTFE_FCCOBA_CCOBn_MASK)
+/* FCCOB9 Bit Fields */
+#define FTFE_FCCOB9_CCOBn_MASK 0xFFu
+#define FTFE_FCCOB9_CCOBn_SHIFT 0
+#define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB9_CCOBn_SHIFT))&FTFE_FCCOB9_CCOBn_MASK)
+/* FCCOB8 Bit Fields */
+#define FTFE_FCCOB8_CCOBn_MASK 0xFFu
+#define FTFE_FCCOB8_CCOBn_SHIFT 0
+#define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB8_CCOBn_SHIFT))&FTFE_FCCOB8_CCOBn_MASK)
+/* FPROT3 Bit Fields */
+#define FTFE_FPROT3_PROT_MASK 0xFFu
+#define FTFE_FPROT3_PROT_SHIFT 0
+#define FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT3_PROT_SHIFT))&FTFE_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define FTFE_FPROT2_PROT_MASK 0xFFu
+#define FTFE_FPROT2_PROT_SHIFT 0
+#define FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT2_PROT_SHIFT))&FTFE_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define FTFE_FPROT1_PROT_MASK 0xFFu
+#define FTFE_FPROT1_PROT_SHIFT 0
+#define FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT1_PROT_SHIFT))&FTFE_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define FTFE_FPROT0_PROT_MASK 0xFFu
+#define FTFE_FPROT0_PROT_SHIFT 0
+#define FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT0_PROT_SHIFT))&FTFE_FPROT0_PROT_MASK)
+/* FEPROT Bit Fields */
+#define FTFE_FEPROT_EPROT_MASK 0xFFu
+#define FTFE_FEPROT_EPROT_SHIFT 0
+#define FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FEPROT_EPROT_SHIFT))&FTFE_FEPROT_EPROT_MASK)
+/* FDPROT Bit Fields */
+#define FTFE_FDPROT_DPROT_MASK 0xFFu
+#define FTFE_FDPROT_DPROT_SHIFT 0
+#define FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FDPROT_DPROT_SHIFT))&FTFE_FDPROT_DPROT_MASK)
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Masks */
+
+
+/* FTFE - Peripheral instance base addresses */
+/** Peripheral FTFE base address */
+#define FTFE_BASE (0x40020000u)
+/** Peripheral FTFE base pointer */
+#define FTFE ((FTFE_Type *)FTFE_BASE)
+#define FTFE_BASE_PTR (FTFE)
+/** Array initializer of FTFE peripheral base pointers */
+#define FTFE_BASES { FTFE }
+
+/* ----------------------------------------------------------------------------
+ -- FTFE - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
+ * @{
+ */
+
+
+/* FTFE - Register instance definitions */
+/* FTFE */
+#define FTFE_FSTAT FTFE_FSTAT_REG(FTFE)
+#define FTFE_FCNFG FTFE_FCNFG_REG(FTFE)
+#define FTFE_FSEC FTFE_FSEC_REG(FTFE)
+#define FTFE_FOPT FTFE_FOPT_REG(FTFE)
+#define FTFE_FCCOB3 FTFE_FCCOB3_REG(FTFE)
+#define FTFE_FCCOB2 FTFE_FCCOB2_REG(FTFE)
+#define FTFE_FCCOB1 FTFE_FCCOB1_REG(FTFE)
+#define FTFE_FCCOB0 FTFE_FCCOB0_REG(FTFE)
+#define FTFE_FCCOB7 FTFE_FCCOB7_REG(FTFE)
+#define FTFE_FCCOB6 FTFE_FCCOB6_REG(FTFE)
+#define FTFE_FCCOB5 FTFE_FCCOB5_REG(FTFE)
+#define FTFE_FCCOB4 FTFE_FCCOB4_REG(FTFE)
+#define FTFE_FCCOBB FTFE_FCCOBB_REG(FTFE)
+#define FTFE_FCCOBA FTFE_FCCOBA_REG(FTFE)
+#define FTFE_FCCOB9 FTFE_FCCOB9_REG(FTFE)
+#define FTFE_FCCOB8 FTFE_FCCOB8_REG(FTFE)
+#define FTFE_FPROT3 FTFE_FPROT3_REG(FTFE)
+#define FTFE_FPROT2 FTFE_FPROT2_REG(FTFE)
+#define FTFE_FPROT1 FTFE_FPROT1_REG(FTFE)
+#define FTFE_FPROT0 FTFE_FPROT0_REG(FTFE)
+#define FTFE_FEPROT FTFE_FEPROT_REG(FTFE)
+#define FTFE_FDPROT FTFE_FDPROT_REG(FTFE)
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FTFE_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
+ * @{
+ */
+
+/** FTM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
+ __IO uint32_t CNT; /**< Counter, offset: 0x4 */
+ __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
+ struct { /* offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+ } CONTROLS[8];
+ __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
+ __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
+ __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
+ __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
+ __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
+ __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
+ __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
+ __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
+ __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
+ __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
+ __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
+ __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
+ __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
+ __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
+ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
+ __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
+ __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
+ __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
+ __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
+ __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
+} FTM_Type, *FTM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- FTM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
+ * @{
+ */
+
+
+/* FTM - Register accessors */
+#define FTM_SC_REG(base) ((base)->SC)
+#define FTM_CNT_REG(base) ((base)->CNT)
+#define FTM_MOD_REG(base) ((base)->MOD)
+#define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
+#define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
+#define FTM_CNTIN_REG(base) ((base)->CNTIN)
+#define FTM_STATUS_REG(base) ((base)->STATUS)
+#define FTM_MODE_REG(base) ((base)->MODE)
+#define FTM_SYNC_REG(base) ((base)->SYNC)
+#define FTM_OUTINIT_REG(base) ((base)->OUTINIT)
+#define FTM_OUTMASK_REG(base) ((base)->OUTMASK)
+#define FTM_COMBINE_REG(base) ((base)->COMBINE)
+#define FTM_DEADTIME_REG(base) ((base)->DEADTIME)
+#define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG)
+#define FTM_POL_REG(base) ((base)->POL)
+#define FTM_FMS_REG(base) ((base)->FMS)
+#define FTM_FILTER_REG(base) ((base)->FILTER)
+#define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL)
+#define FTM_QDCTRL_REG(base) ((base)->QDCTRL)
+#define FTM_CONF_REG(base) ((base)->CONF)
+#define FTM_FLTPOL_REG(base) ((base)->FLTPOL)
+#define FTM_SYNCONF_REG(base) ((base)->SYNCONF)
+#define FTM_INVCTRL_REG(base) ((base)->INVCTRL)
+#define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL)
+#define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Masks FTM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define FTM_SC_PS_MASK 0x7u
+#define FTM_SC_PS_SHIFT 0
+#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
+#define FTM_SC_CLKS_MASK 0x18u
+#define FTM_SC_CLKS_SHIFT 3
+#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
+#define FTM_SC_CPWMS_MASK 0x20u
+#define FTM_SC_CPWMS_SHIFT 5
+#define FTM_SC_TOIE_MASK 0x40u
+#define FTM_SC_TOIE_SHIFT 6
+#define FTM_SC_TOF_MASK 0x80u
+#define FTM_SC_TOF_SHIFT 7
+/* CNT Bit Fields */
+#define FTM_CNT_COUNT_MASK 0xFFFFu
+#define FTM_CNT_COUNT_SHIFT 0
+#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define FTM_MOD_MOD_MASK 0xFFFFu
+#define FTM_MOD_MOD_SHIFT 0
+#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define FTM_CnSC_DMA_MASK 0x1u
+#define FTM_CnSC_DMA_SHIFT 0
+#define FTM_CnSC_ELSA_MASK 0x4u
+#define FTM_CnSC_ELSA_SHIFT 2
+#define FTM_CnSC_ELSB_MASK 0x8u
+#define FTM_CnSC_ELSB_SHIFT 3
+#define FTM_CnSC_MSA_MASK 0x10u
+#define FTM_CnSC_MSA_SHIFT 4
+#define FTM_CnSC_MSB_MASK 0x20u
+#define FTM_CnSC_MSB_SHIFT 5
+#define FTM_CnSC_CHIE_MASK 0x40u
+#define FTM_CnSC_CHIE_SHIFT 6
+#define FTM_CnSC_CHF_MASK 0x80u
+#define FTM_CnSC_CHF_SHIFT 7
+/* CnV Bit Fields */
+#define FTM_CnV_VAL_MASK 0xFFFFu
+#define FTM_CnV_VAL_SHIFT 0
+#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
+/* CNTIN Bit Fields */
+#define FTM_CNTIN_INIT_MASK 0xFFFFu
+#define FTM_CNTIN_INIT_SHIFT 0
+#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
+/* STATUS Bit Fields */
+#define FTM_STATUS_CH0F_MASK 0x1u
+#define FTM_STATUS_CH0F_SHIFT 0
+#define FTM_STATUS_CH1F_MASK 0x2u
+#define FTM_STATUS_CH1F_SHIFT 1
+#define FTM_STATUS_CH2F_MASK 0x4u
+#define FTM_STATUS_CH2F_SHIFT 2
+#define FTM_STATUS_CH3F_MASK 0x8u
+#define FTM_STATUS_CH3F_SHIFT 3
+#define FTM_STATUS_CH4F_MASK 0x10u
+#define FTM_STATUS_CH4F_SHIFT 4
+#define FTM_STATUS_CH5F_MASK 0x20u
+#define FTM_STATUS_CH5F_SHIFT 5
+#define FTM_STATUS_CH6F_MASK 0x40u
+#define FTM_STATUS_CH6F_SHIFT 6
+#define FTM_STATUS_CH7F_MASK 0x80u
+#define FTM_STATUS_CH7F_SHIFT 7
+/* MODE Bit Fields */
+#define FTM_MODE_FTMEN_MASK 0x1u
+#define FTM_MODE_FTMEN_SHIFT 0
+#define FTM_MODE_INIT_MASK 0x2u
+#define FTM_MODE_INIT_SHIFT 1
+#define FTM_MODE_WPDIS_MASK 0x4u
+#define FTM_MODE_WPDIS_SHIFT 2
+#define FTM_MODE_PWMSYNC_MASK 0x8u
+#define FTM_MODE_PWMSYNC_SHIFT 3
+#define FTM_MODE_CAPTEST_MASK 0x10u
+#define FTM_MODE_CAPTEST_SHIFT 4
+#define FTM_MODE_FAULTM_MASK 0x60u
+#define FTM_MODE_FAULTM_SHIFT 5
+#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
+#define FTM_MODE_FAULTIE_MASK 0x80u
+#define FTM_MODE_FAULTIE_SHIFT 7
+/* SYNC Bit Fields */
+#define FTM_SYNC_CNTMIN_MASK 0x1u
+#define FTM_SYNC_CNTMIN_SHIFT 0
+#define FTM_SYNC_CNTMAX_MASK 0x2u
+#define FTM_SYNC_CNTMAX_SHIFT 1
+#define FTM_SYNC_REINIT_MASK 0x4u
+#define FTM_SYNC_REINIT_SHIFT 2
+#define FTM_SYNC_SYNCHOM_MASK 0x8u
+#define FTM_SYNC_SYNCHOM_SHIFT 3
+#define FTM_SYNC_TRIG0_MASK 0x10u
+#define FTM_SYNC_TRIG0_SHIFT 4
+#define FTM_SYNC_TRIG1_MASK 0x20u
+#define FTM_SYNC_TRIG1_SHIFT 5
+#define FTM_SYNC_TRIG2_MASK 0x40u
+#define FTM_SYNC_TRIG2_SHIFT 6
+#define FTM_SYNC_SWSYNC_MASK 0x80u
+#define FTM_SYNC_SWSYNC_SHIFT 7
+/* OUTINIT Bit Fields */
+#define FTM_OUTINIT_CH0OI_MASK 0x1u
+#define FTM_OUTINIT_CH0OI_SHIFT 0
+#define FTM_OUTINIT_CH1OI_MASK 0x2u
+#define FTM_OUTINIT_CH1OI_SHIFT 1
+#define FTM_OUTINIT_CH2OI_MASK 0x4u
+#define FTM_OUTINIT_CH2OI_SHIFT 2
+#define FTM_OUTINIT_CH3OI_MASK 0x8u
+#define FTM_OUTINIT_CH3OI_SHIFT 3
+#define FTM_OUTINIT_CH4OI_MASK 0x10u
+#define FTM_OUTINIT_CH4OI_SHIFT 4
+#define FTM_OUTINIT_CH5OI_MASK 0x20u
+#define FTM_OUTINIT_CH5OI_SHIFT 5
+#define FTM_OUTINIT_CH6OI_MASK 0x40u
+#define FTM_OUTINIT_CH6OI_SHIFT 6
+#define FTM_OUTINIT_CH7OI_MASK 0x80u
+#define FTM_OUTINIT_CH7OI_SHIFT 7
+/* OUTMASK Bit Fields */
+#define FTM_OUTMASK_CH0OM_MASK 0x1u
+#define FTM_OUTMASK_CH0OM_SHIFT 0
+#define FTM_OUTMASK_CH1OM_MASK 0x2u
+#define FTM_OUTMASK_CH1OM_SHIFT 1
+#define FTM_OUTMASK_CH2OM_MASK 0x4u
+#define FTM_OUTMASK_CH2OM_SHIFT 2
+#define FTM_OUTMASK_CH3OM_MASK 0x8u
+#define FTM_OUTMASK_CH3OM_SHIFT 3
+#define FTM_OUTMASK_CH4OM_MASK 0x10u
+#define FTM_OUTMASK_CH4OM_SHIFT 4
+#define FTM_OUTMASK_CH5OM_MASK 0x20u
+#define FTM_OUTMASK_CH5OM_SHIFT 5
+#define FTM_OUTMASK_CH6OM_MASK 0x40u
+#define FTM_OUTMASK_CH6OM_SHIFT 6
+#define FTM_OUTMASK_CH7OM_MASK 0x80u
+#define FTM_OUTMASK_CH7OM_SHIFT 7
+/* COMBINE Bit Fields */
+#define FTM_COMBINE_COMBINE0_MASK 0x1u
+#define FTM_COMBINE_COMBINE0_SHIFT 0
+#define FTM_COMBINE_COMP0_MASK 0x2u
+#define FTM_COMBINE_COMP0_SHIFT 1
+#define FTM_COMBINE_DECAPEN0_MASK 0x4u
+#define FTM_COMBINE_DECAPEN0_SHIFT 2
+#define FTM_COMBINE_DECAP0_MASK 0x8u
+#define FTM_COMBINE_DECAP0_SHIFT 3
+#define FTM_COMBINE_DTEN0_MASK 0x10u
+#define FTM_COMBINE_DTEN0_SHIFT 4
+#define FTM_COMBINE_SYNCEN0_MASK 0x20u
+#define FTM_COMBINE_SYNCEN0_SHIFT 5
+#define FTM_COMBINE_FAULTEN0_MASK 0x40u
+#define FTM_COMBINE_FAULTEN0_SHIFT 6
+#define FTM_COMBINE_COMBINE1_MASK 0x100u
+#define FTM_COMBINE_COMBINE1_SHIFT 8
+#define FTM_COMBINE_COMP1_MASK 0x200u
+#define FTM_COMBINE_COMP1_SHIFT 9
+#define FTM_COMBINE_DECAPEN1_MASK 0x400u
+#define FTM_COMBINE_DECAPEN1_SHIFT 10
+#define FTM_COMBINE_DECAP1_MASK 0x800u
+#define FTM_COMBINE_DECAP1_SHIFT 11
+#define FTM_COMBINE_DTEN1_MASK 0x1000u
+#define FTM_COMBINE_DTEN1_SHIFT 12
+#define FTM_COMBINE_SYNCEN1_MASK 0x2000u
+#define FTM_COMBINE_SYNCEN1_SHIFT 13
+#define FTM_COMBINE_FAULTEN1_MASK 0x4000u
+#define FTM_COMBINE_FAULTEN1_SHIFT 14
+#define FTM_COMBINE_COMBINE2_MASK 0x10000u
+#define FTM_COMBINE_COMBINE2_SHIFT 16
+#define FTM_COMBINE_COMP2_MASK 0x20000u
+#define FTM_COMBINE_COMP2_SHIFT 17
+#define FTM_COMBINE_DECAPEN2_MASK 0x40000u
+#define FTM_COMBINE_DECAPEN2_SHIFT 18
+#define FTM_COMBINE_DECAP2_MASK 0x80000u
+#define FTM_COMBINE_DECAP2_SHIFT 19
+#define FTM_COMBINE_DTEN2_MASK 0x100000u
+#define FTM_COMBINE_DTEN2_SHIFT 20
+#define FTM_COMBINE_SYNCEN2_MASK 0x200000u
+#define FTM_COMBINE_SYNCEN2_SHIFT 21
+#define FTM_COMBINE_FAULTEN2_MASK 0x400000u
+#define FTM_COMBINE_FAULTEN2_SHIFT 22
+#define FTM_COMBINE_COMBINE3_MASK 0x1000000u
+#define FTM_COMBINE_COMBINE3_SHIFT 24
+#define FTM_COMBINE_COMP3_MASK 0x2000000u
+#define FTM_COMBINE_COMP3_SHIFT 25
+#define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
+#define FTM_COMBINE_DECAPEN3_SHIFT 26
+#define FTM_COMBINE_DECAP3_MASK 0x8000000u
+#define FTM_COMBINE_DECAP3_SHIFT 27
+#define FTM_COMBINE_DTEN3_MASK 0x10000000u
+#define FTM_COMBINE_DTEN3_SHIFT 28
+#define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
+#define FTM_COMBINE_SYNCEN3_SHIFT 29
+#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
+#define FTM_COMBINE_FAULTEN3_SHIFT 30
+/* DEADTIME Bit Fields */
+#define FTM_DEADTIME_DTVAL_MASK 0x3Fu
+#define FTM_DEADTIME_DTVAL_SHIFT 0
+#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
+#define FTM_DEADTIME_DTPS_MASK 0xC0u
+#define FTM_DEADTIME_DTPS_SHIFT 6
+#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
+/* EXTTRIG Bit Fields */
+#define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
+#define FTM_EXTTRIG_CH2TRIG_SHIFT 0
+#define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
+#define FTM_EXTTRIG_CH3TRIG_SHIFT 1
+#define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
+#define FTM_EXTTRIG_CH4TRIG_SHIFT 2
+#define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
+#define FTM_EXTTRIG_CH5TRIG_SHIFT 3
+#define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
+#define FTM_EXTTRIG_CH0TRIG_SHIFT 4
+#define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
+#define FTM_EXTTRIG_CH1TRIG_SHIFT 5
+#define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
+#define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
+#define FTM_EXTTRIG_TRIGF_MASK 0x80u
+#define FTM_EXTTRIG_TRIGF_SHIFT 7
+/* POL Bit Fields */
+#define FTM_POL_POL0_MASK 0x1u
+#define FTM_POL_POL0_SHIFT 0
+#define FTM_POL_POL1_MASK 0x2u
+#define FTM_POL_POL1_SHIFT 1
+#define FTM_POL_POL2_MASK 0x4u
+#define FTM_POL_POL2_SHIFT 2
+#define FTM_POL_POL3_MASK 0x8u
+#define FTM_POL_POL3_SHIFT 3
+#define FTM_POL_POL4_MASK 0x10u
+#define FTM_POL_POL4_SHIFT 4
+#define FTM_POL_POL5_MASK 0x20u
+#define FTM_POL_POL5_SHIFT 5
+#define FTM_POL_POL6_MASK 0x40u
+#define FTM_POL_POL6_SHIFT 6
+#define FTM_POL_POL7_MASK 0x80u
+#define FTM_POL_POL7_SHIFT 7
+/* FMS Bit Fields */
+#define FTM_FMS_FAULTF0_MASK 0x1u
+#define FTM_FMS_FAULTF0_SHIFT 0
+#define FTM_FMS_FAULTF1_MASK 0x2u
+#define FTM_FMS_FAULTF1_SHIFT 1
+#define FTM_FMS_FAULTF2_MASK 0x4u
+#define FTM_FMS_FAULTF2_SHIFT 2
+#define FTM_FMS_FAULTF3_MASK 0x8u
+#define FTM_FMS_FAULTF3_SHIFT 3
+#define FTM_FMS_FAULTIN_MASK 0x20u
+#define FTM_FMS_FAULTIN_SHIFT 5
+#define FTM_FMS_WPEN_MASK 0x40u
+#define FTM_FMS_WPEN_SHIFT 6
+#define FTM_FMS_FAULTF_MASK 0x80u
+#define FTM_FMS_FAULTF_SHIFT 7
+/* FILTER Bit Fields */
+#define FTM_FILTER_CH0FVAL_MASK 0xFu
+#define FTM_FILTER_CH0FVAL_SHIFT 0
+#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
+#define FTM_FILTER_CH1FVAL_MASK 0xF0u
+#define FTM_FILTER_CH1FVAL_SHIFT 4
+#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
+#define FTM_FILTER_CH2FVAL_MASK 0xF00u
+#define FTM_FILTER_CH2FVAL_SHIFT 8
+#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
+#define FTM_FILTER_CH3FVAL_MASK 0xF000u
+#define FTM_FILTER_CH3FVAL_SHIFT 12
+#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
+/* FLTCTRL Bit Fields */
+#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
+#define FTM_FLTCTRL_FAULT0EN_SHIFT 0
+#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
+#define FTM_FLTCTRL_FAULT1EN_SHIFT 1
+#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
+#define FTM_FLTCTRL_FAULT2EN_SHIFT 2
+#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
+#define FTM_FLTCTRL_FAULT3EN_SHIFT 3
+#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
+#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
+#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
+#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
+#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
+#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
+#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
+#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
+#define FTM_FLTCTRL_FFVAL_MASK 0xF00u
+#define FTM_FLTCTRL_FFVAL_SHIFT 8
+#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
+/* QDCTRL Bit Fields */
+#define FTM_QDCTRL_QUADEN_MASK 0x1u
+#define FTM_QDCTRL_QUADEN_SHIFT 0
+#define FTM_QDCTRL_TOFDIR_MASK 0x2u
+#define FTM_QDCTRL_TOFDIR_SHIFT 1
+#define FTM_QDCTRL_QUADIR_MASK 0x4u
+#define FTM_QDCTRL_QUADIR_SHIFT 2
+#define FTM_QDCTRL_QUADMODE_MASK 0x8u
+#define FTM_QDCTRL_QUADMODE_SHIFT 3
+#define FTM_QDCTRL_PHBPOL_MASK 0x10u
+#define FTM_QDCTRL_PHBPOL_SHIFT 4
+#define FTM_QDCTRL_PHAPOL_MASK 0x20u
+#define FTM_QDCTRL_PHAPOL_SHIFT 5
+#define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
+#define FTM_QDCTRL_PHBFLTREN_SHIFT 6
+#define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
+#define FTM_QDCTRL_PHAFLTREN_SHIFT 7
+/* CONF Bit Fields */
+#define FTM_CONF_NUMTOF_MASK 0x1Fu
+#define FTM_CONF_NUMTOF_SHIFT 0
+#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
+#define FTM_CONF_BDMMODE_MASK 0xC0u
+#define FTM_CONF_BDMMODE_SHIFT 6
+#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
+#define FTM_CONF_GTBEEN_MASK 0x200u
+#define FTM_CONF_GTBEEN_SHIFT 9
+#define FTM_CONF_GTBEOUT_MASK 0x400u
+#define FTM_CONF_GTBEOUT_SHIFT 10
+/* FLTPOL Bit Fields */
+#define FTM_FLTPOL_FLT0POL_MASK 0x1u
+#define FTM_FLTPOL_FLT0POL_SHIFT 0
+#define FTM_FLTPOL_FLT1POL_MASK 0x2u
+#define FTM_FLTPOL_FLT1POL_SHIFT 1
+#define FTM_FLTPOL_FLT2POL_MASK 0x4u
+#define FTM_FLTPOL_FLT2POL_SHIFT 2
+#define FTM_FLTPOL_FLT3POL_MASK 0x8u
+#define FTM_FLTPOL_FLT3POL_SHIFT 3
+/* SYNCONF Bit Fields */
+#define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
+#define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
+#define FTM_SYNCONF_CNTINC_MASK 0x4u
+#define FTM_SYNCONF_CNTINC_SHIFT 2
+#define FTM_SYNCONF_INVC_MASK 0x10u
+#define FTM_SYNCONF_INVC_SHIFT 4
+#define FTM_SYNCONF_SWOC_MASK 0x20u
+#define FTM_SYNCONF_SWOC_SHIFT 5
+#define FTM_SYNCONF_SYNCMODE_MASK 0x80u
+#define FTM_SYNCONF_SYNCMODE_SHIFT 7
+#define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
+#define FTM_SYNCONF_SWRSTCNT_SHIFT 8
+#define FTM_SYNCONF_SWWRBUF_MASK 0x200u
+#define FTM_SYNCONF_SWWRBUF_SHIFT 9
+#define FTM_SYNCONF_SWOM_MASK 0x400u
+#define FTM_SYNCONF_SWOM_SHIFT 10
+#define FTM_SYNCONF_SWINVC_MASK 0x800u
+#define FTM_SYNCONF_SWINVC_SHIFT 11
+#define FTM_SYNCONF_SWSOC_MASK 0x1000u
+#define FTM_SYNCONF_SWSOC_SHIFT 12
+#define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
+#define FTM_SYNCONF_HWRSTCNT_SHIFT 16
+#define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
+#define FTM_SYNCONF_HWWRBUF_SHIFT 17
+#define FTM_SYNCONF_HWOM_MASK 0x40000u
+#define FTM_SYNCONF_HWOM_SHIFT 18
+#define FTM_SYNCONF_HWINVC_MASK 0x80000u
+#define FTM_SYNCONF_HWINVC_SHIFT 19
+#define FTM_SYNCONF_HWSOC_MASK 0x100000u
+#define FTM_SYNCONF_HWSOC_SHIFT 20
+/* INVCTRL Bit Fields */
+#define FTM_INVCTRL_INV0EN_MASK 0x1u
+#define FTM_INVCTRL_INV0EN_SHIFT 0
+#define FTM_INVCTRL_INV1EN_MASK 0x2u
+#define FTM_INVCTRL_INV1EN_SHIFT 1
+#define FTM_INVCTRL_INV2EN_MASK 0x4u
+#define FTM_INVCTRL_INV2EN_SHIFT 2
+#define FTM_INVCTRL_INV3EN_MASK 0x8u
+#define FTM_INVCTRL_INV3EN_SHIFT 3
+/* SWOCTRL Bit Fields */
+#define FTM_SWOCTRL_CH0OC_MASK 0x1u
+#define FTM_SWOCTRL_CH0OC_SHIFT 0
+#define FTM_SWOCTRL_CH1OC_MASK 0x2u
+#define FTM_SWOCTRL_CH1OC_SHIFT 1
+#define FTM_SWOCTRL_CH2OC_MASK 0x4u
+#define FTM_SWOCTRL_CH2OC_SHIFT 2
+#define FTM_SWOCTRL_CH3OC_MASK 0x8u
+#define FTM_SWOCTRL_CH3OC_SHIFT 3
+#define FTM_SWOCTRL_CH4OC_MASK 0x10u
+#define FTM_SWOCTRL_CH4OC_SHIFT 4
+#define FTM_SWOCTRL_CH5OC_MASK 0x20u
+#define FTM_SWOCTRL_CH5OC_SHIFT 5
+#define FTM_SWOCTRL_CH6OC_MASK 0x40u
+#define FTM_SWOCTRL_CH6OC_SHIFT 6
+#define FTM_SWOCTRL_CH7OC_MASK 0x80u
+#define FTM_SWOCTRL_CH7OC_SHIFT 7
+#define FTM_SWOCTRL_CH0OCV_MASK 0x100u
+#define FTM_SWOCTRL_CH0OCV_SHIFT 8
+#define FTM_SWOCTRL_CH1OCV_MASK 0x200u
+#define FTM_SWOCTRL_CH1OCV_SHIFT 9
+#define FTM_SWOCTRL_CH2OCV_MASK 0x400u
+#define FTM_SWOCTRL_CH2OCV_SHIFT 10
+#define FTM_SWOCTRL_CH3OCV_MASK 0x800u
+#define FTM_SWOCTRL_CH3OCV_SHIFT 11
+#define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
+#define FTM_SWOCTRL_CH4OCV_SHIFT 12
+#define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
+#define FTM_SWOCTRL_CH5OCV_SHIFT 13
+#define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
+#define FTM_SWOCTRL_CH6OCV_SHIFT 14
+#define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
+#define FTM_SWOCTRL_CH7OCV_SHIFT 15
+/* PWMLOAD Bit Fields */
+#define FTM_PWMLOAD_CH0SEL_MASK 0x1u
+#define FTM_PWMLOAD_CH0SEL_SHIFT 0
+#define FTM_PWMLOAD_CH1SEL_MASK 0x2u
+#define FTM_PWMLOAD_CH1SEL_SHIFT 1
+#define FTM_PWMLOAD_CH2SEL_MASK 0x4u
+#define FTM_PWMLOAD_CH2SEL_SHIFT 2
+#define FTM_PWMLOAD_CH3SEL_MASK 0x8u
+#define FTM_PWMLOAD_CH3SEL_SHIFT 3
+#define FTM_PWMLOAD_CH4SEL_MASK 0x10u
+#define FTM_PWMLOAD_CH4SEL_SHIFT 4
+#define FTM_PWMLOAD_CH5SEL_MASK 0x20u
+#define FTM_PWMLOAD_CH5SEL_SHIFT 5
+#define FTM_PWMLOAD_CH6SEL_MASK 0x40u
+#define FTM_PWMLOAD_CH6SEL_SHIFT 6
+#define FTM_PWMLOAD_CH7SEL_MASK 0x80u
+#define FTM_PWMLOAD_CH7SEL_SHIFT 7
+#define FTM_PWMLOAD_LDOK_MASK 0x200u
+#define FTM_PWMLOAD_LDOK_SHIFT 9
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Masks */
+
+
+/* FTM - Peripheral instance base addresses */
+/** Peripheral FTM0 base address */
+#define FTM0_BASE (0x40038000u)
+/** Peripheral FTM0 base pointer */
+#define FTM0 ((FTM_Type *)FTM0_BASE)
+#define FTM0_BASE_PTR (FTM0)
+/** Peripheral FTM1 base address */
+#define FTM1_BASE (0x40039000u)
+/** Peripheral FTM1 base pointer */
+#define FTM1 ((FTM_Type *)FTM1_BASE)
+#define FTM1_BASE_PTR (FTM1)
+/** Peripheral FTM2 base address */
+#define FTM2_BASE (0x4003A000u)
+/** Peripheral FTM2 base pointer */
+#define FTM2 ((FTM_Type *)FTM2_BASE)
+#define FTM2_BASE_PTR (FTM2)
+/** Peripheral FTM3 base address */
+#define FTM3_BASE (0x400B9000u)
+/** Peripheral FTM3 base pointer */
+#define FTM3 ((FTM_Type *)FTM3_BASE)
+#define FTM3_BASE_PTR (FTM3)
+/** Array initializer of FTM peripheral base pointers */
+#define FTM_BASES { FTM0, FTM1, FTM2, FTM3 }
+
+/* ----------------------------------------------------------------------------
+ -- FTM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
+ * @{
+ */
+
+
+/* FTM - Register instance definitions */
+/* FTM0 */
+#define FTM0_SC FTM_SC_REG(FTM0)
+#define FTM0_CNT FTM_CNT_REG(FTM0)
+#define FTM0_MOD FTM_MOD_REG(FTM0)
+#define FTM0_C0SC FTM_CnSC_REG(FTM0,0)
+#define FTM0_C0V FTM_CnV_REG(FTM0,0)
+#define FTM0_C1SC FTM_CnSC_REG(FTM0,1)
+#define FTM0_C1V FTM_CnV_REG(FTM0,1)
+#define FTM0_C2SC FTM_CnSC_REG(FTM0,2)
+#define FTM0_C2V FTM_CnV_REG(FTM0,2)
+#define FTM0_C3SC FTM_CnSC_REG(FTM0,3)
+#define FTM0_C3V FTM_CnV_REG(FTM0,3)
+#define FTM0_C4SC FTM_CnSC_REG(FTM0,4)
+#define FTM0_C4V FTM_CnV_REG(FTM0,4)
+#define FTM0_C5SC FTM_CnSC_REG(FTM0,5)
+#define FTM0_C5V FTM_CnV_REG(FTM0,5)
+#define FTM0_C6SC FTM_CnSC_REG(FTM0,6)
+#define FTM0_C6V FTM_CnV_REG(FTM0,6)
+#define FTM0_C7SC FTM_CnSC_REG(FTM0,7)
+#define FTM0_C7V FTM_CnV_REG(FTM0,7)
+#define FTM0_CNTIN FTM_CNTIN_REG(FTM0)
+#define FTM0_STATUS FTM_STATUS_REG(FTM0)
+#define FTM0_MODE FTM_MODE_REG(FTM0)
+#define FTM0_SYNC FTM_SYNC_REG(FTM0)
+#define FTM0_OUTINIT FTM_OUTINIT_REG(FTM0)
+#define FTM0_OUTMASK FTM_OUTMASK_REG(FTM0)
+#define FTM0_COMBINE FTM_COMBINE_REG(FTM0)
+#define FTM0_DEADTIME FTM_DEADTIME_REG(FTM0)
+#define FTM0_EXTTRIG FTM_EXTTRIG_REG(FTM0)
+#define FTM0_POL FTM_POL_REG(FTM0)
+#define FTM0_FMS FTM_FMS_REG(FTM0)
+#define FTM0_FILTER FTM_FILTER_REG(FTM0)
+#define FTM0_FLTCTRL FTM_FLTCTRL_REG(FTM0)
+#define FTM0_QDCTRL FTM_QDCTRL_REG(FTM0)
+#define FTM0_CONF FTM_CONF_REG(FTM0)
+#define FTM0_FLTPOL FTM_FLTPOL_REG(FTM0)
+#define FTM0_SYNCONF FTM_SYNCONF_REG(FTM0)
+#define FTM0_INVCTRL FTM_INVCTRL_REG(FTM0)
+#define FTM0_SWOCTRL FTM_SWOCTRL_REG(FTM0)
+#define FTM0_PWMLOAD FTM_PWMLOAD_REG(FTM0)
+/* FTM1 */
+#define FTM1_SC FTM_SC_REG(FTM1)
+#define FTM1_CNT FTM_CNT_REG(FTM1)
+#define FTM1_MOD FTM_MOD_REG(FTM1)
+#define FTM1_C0SC FTM_CnSC_REG(FTM1,0)
+#define FTM1_C0V FTM_CnV_REG(FTM1,0)
+#define FTM1_C1SC FTM_CnSC_REG(FTM1,1)
+#define FTM1_C1V FTM_CnV_REG(FTM1,1)
+#define FTM1_CNTIN FTM_CNTIN_REG(FTM1)
+#define FTM1_STATUS FTM_STATUS_REG(FTM1)
+#define FTM1_MODE FTM_MODE_REG(FTM1)
+#define FTM1_SYNC FTM_SYNC_REG(FTM1)
+#define FTM1_OUTINIT FTM_OUTINIT_REG(FTM1)
+#define FTM1_OUTMASK FTM_OUTMASK_REG(FTM1)
+#define FTM1_COMBINE FTM_COMBINE_REG(FTM1)
+#define FTM1_DEADTIME FTM_DEADTIME_REG(FTM1)
+#define FTM1_EXTTRIG FTM_EXTTRIG_REG(FTM1)
+#define FTM1_POL FTM_POL_REG(FTM1)
+#define FTM1_FMS FTM_FMS_REG(FTM1)
+#define FTM1_FILTER FTM_FILTER_REG(FTM1)
+#define FTM1_FLTCTRL FTM_FLTCTRL_REG(FTM1)
+#define FTM1_QDCTRL FTM_QDCTRL_REG(FTM1)
+#define FTM1_CONF FTM_CONF_REG(FTM1)
+#define FTM1_FLTPOL FTM_FLTPOL_REG(FTM1)
+#define FTM1_SYNCONF FTM_SYNCONF_REG(FTM1)
+#define FTM1_INVCTRL FTM_INVCTRL_REG(FTM1)
+#define FTM1_SWOCTRL FTM_SWOCTRL_REG(FTM1)
+#define FTM1_PWMLOAD FTM_PWMLOAD_REG(FTM1)
+/* FTM2 */
+#define FTM2_SC FTM_SC_REG(FTM2)
+#define FTM2_CNT FTM_CNT_REG(FTM2)
+#define FTM2_MOD FTM_MOD_REG(FTM2)
+#define FTM2_C0SC FTM_CnSC_REG(FTM2,0)
+#define FTM2_C0V FTM_CnV_REG(FTM2,0)
+#define FTM2_C1SC FTM_CnSC_REG(FTM2,1)
+#define FTM2_C1V FTM_CnV_REG(FTM2,1)
+#define FTM2_CNTIN FTM_CNTIN_REG(FTM2)
+#define FTM2_STATUS FTM_STATUS_REG(FTM2)
+#define FTM2_MODE FTM_MODE_REG(FTM2)
+#define FTM2_SYNC FTM_SYNC_REG(FTM2)
+#define FTM2_OUTINIT FTM_OUTINIT_REG(FTM2)
+#define FTM2_OUTMASK FTM_OUTMASK_REG(FTM2)
+#define FTM2_COMBINE FTM_COMBINE_REG(FTM2)
+#define FTM2_DEADTIME FTM_DEADTIME_REG(FTM2)
+#define FTM2_EXTTRIG FTM_EXTTRIG_REG(FTM2)
+#define FTM2_POL FTM_POL_REG(FTM2)
+#define FTM2_FMS FTM_FMS_REG(FTM2)
+#define FTM2_FILTER FTM_FILTER_REG(FTM2)
+#define FTM2_FLTCTRL FTM_FLTCTRL_REG(FTM2)
+#define FTM2_QDCTRL FTM_QDCTRL_REG(FTM2)
+#define FTM2_CONF FTM_CONF_REG(FTM2)
+#define FTM2_FLTPOL FTM_FLTPOL_REG(FTM2)
+#define FTM2_SYNCONF FTM_SYNCONF_REG(FTM2)
+#define FTM2_INVCTRL FTM_INVCTRL_REG(FTM2)
+#define FTM2_SWOCTRL FTM_SWOCTRL_REG(FTM2)
+#define FTM2_PWMLOAD FTM_PWMLOAD_REG(FTM2)
+/* FTM3 */
+#define FTM3_SC FTM_SC_REG(FTM3)
+#define FTM3_CNT FTM_CNT_REG(FTM3)
+#define FTM3_MOD FTM_MOD_REG(FTM3)
+#define FTM3_C0SC FTM_CnSC_REG(FTM3,0)
+#define FTM3_C0V FTM_CnV_REG(FTM3,0)
+#define FTM3_C1SC FTM_CnSC_REG(FTM3,1)
+#define FTM3_C1V FTM_CnV_REG(FTM3,1)
+#define FTM3_C2SC FTM_CnSC_REG(FTM3,2)
+#define FTM3_C2V FTM_CnV_REG(FTM3,2)
+#define FTM3_C3SC FTM_CnSC_REG(FTM3,3)
+#define FTM3_C3V FTM_CnV_REG(FTM3,3)
+#define FTM3_C4SC FTM_CnSC_REG(FTM3,4)
+#define FTM3_C4V FTM_CnV_REG(FTM3,4)
+#define FTM3_C5SC FTM_CnSC_REG(FTM3,5)
+#define FTM3_C5V FTM_CnV_REG(FTM3,5)
+#define FTM3_C6SC FTM_CnSC_REG(FTM3,6)
+#define FTM3_C6V FTM_CnV_REG(FTM3,6)
+#define FTM3_C7SC FTM_CnSC_REG(FTM3,7)
+#define FTM3_C7V FTM_CnV_REG(FTM3,7)
+#define FTM3_CNTIN FTM_CNTIN_REG(FTM3)
+#define FTM3_STATUS FTM_STATUS_REG(FTM3)
+#define FTM3_MODE FTM_MODE_REG(FTM3)
+#define FTM3_SYNC FTM_SYNC_REG(FTM3)
+#define FTM3_OUTINIT FTM_OUTINIT_REG(FTM3)
+#define FTM3_OUTMASK FTM_OUTMASK_REG(FTM3)
+#define FTM3_COMBINE FTM_COMBINE_REG(FTM3)
+#define FTM3_DEADTIME FTM_DEADTIME_REG(FTM3)
+#define FTM3_EXTTRIG FTM_EXTTRIG_REG(FTM3)
+#define FTM3_POL FTM_POL_REG(FTM3)
+#define FTM3_FMS FTM_FMS_REG(FTM3)
+#define FTM3_FILTER FTM_FILTER_REG(FTM3)
+#define FTM3_FLTCTRL FTM_FLTCTRL_REG(FTM3)
+#define FTM3_QDCTRL FTM_QDCTRL_REG(FTM3)
+#define FTM3_CONF FTM_CONF_REG(FTM3)
+#define FTM3_FLTPOL FTM_FLTPOL_REG(FTM3)
+#define FTM3_SYNCONF FTM_SYNCONF_REG(FTM3)
+#define FTM3_INVCTRL FTM_INVCTRL_REG(FTM3)
+#define FTM3_SWOCTRL FTM_SWOCTRL_REG(FTM3)
+#define FTM3_PWMLOAD FTM_PWMLOAD_REG(FTM3)
+
+/* FTM - Register array accessors */
+#define FTM0_CnSC(index) FTM_CnSC_REG(FTM0,index)
+#define FTM1_CnSC(index) FTM_CnSC_REG(FTM1,index)
+#define FTM2_CnSC(index) FTM_CnSC_REG(FTM2,index)
+#define FTM3_CnSC(index) FTM_CnSC_REG(FTM3,index)
+#define FTM0_CnV(index) FTM_CnV_REG(FTM0,index)
+#define FTM1_CnV(index) FTM_CnV_REG(FTM1,index)
+#define FTM2_CnV(index) FTM_CnV_REG(FTM2,index)
+#define FTM3_CnV(index) FTM_CnV_REG(FTM3,index)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FTM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type, *GPIO_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- GPIO - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @{
+ */
+
+
+/* GPIO - Register accessors */
+#define GPIO_PDOR_REG(base) ((base)->PDOR)
+#define GPIO_PSOR_REG(base) ((base)->PSOR)
+#define GPIO_PCOR_REG(base) ((base)->PCOR)
+#define GPIO_PTOR_REG(base) ((base)->PTOR)
+#define GPIO_PDIR_REG(base) ((base)->PDIR)
+#define GPIO_PDDR_REG(base) ((base)->PDDR)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT 0
+#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT 0
+#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT 0
+#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT 0
+#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT 0
+#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT 0
+#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral PTA base address */
+#define PTA_BASE (0x400FF000u)
+/** Peripheral PTA base pointer */
+#define PTA ((GPIO_Type *)PTA_BASE)
+#define PTA_BASE_PTR (PTA)
+/** Peripheral PTB base address */
+#define PTB_BASE (0x400FF040u)
+/** Peripheral PTB base pointer */
+#define PTB ((GPIO_Type *)PTB_BASE)
+#define PTB_BASE_PTR (PTB)
+/** Peripheral PTC base address */
+#define PTC_BASE (0x400FF080u)
+/** Peripheral PTC base pointer */
+#define PTC ((GPIO_Type *)PTC_BASE)
+#define PTC_BASE_PTR (PTC)
+/** Peripheral PTD base address */
+#define PTD_BASE (0x400FF0C0u)
+/** Peripheral PTD base pointer */
+#define PTD ((GPIO_Type *)PTD_BASE)
+#define PTD_BASE_PTR (PTD)
+/** Peripheral PTE base address */
+#define PTE_BASE (0x400FF100u)
+/** Peripheral PTE base pointer */
+#define PTE ((GPIO_Type *)PTE_BASE)
+#define PTE_BASE_PTR (PTE)
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
+
+/* ----------------------------------------------------------------------------
+ -- GPIO - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @{
+ */
+
+
+/* GPIO - Register instance definitions */
+/* PTA */
+#define GPIOA_PDOR GPIO_PDOR_REG(PTA)
+#define GPIOA_PSOR GPIO_PSOR_REG(PTA)
+#define GPIOA_PCOR GPIO_PCOR_REG(PTA)
+#define GPIOA_PTOR GPIO_PTOR_REG(PTA)
+#define GPIOA_PDIR GPIO_PDIR_REG(PTA)
+#define GPIOA_PDDR GPIO_PDDR_REG(PTA)
+/* PTB */
+#define GPIOB_PDOR GPIO_PDOR_REG(PTB)
+#define GPIOB_PSOR GPIO_PSOR_REG(PTB)
+#define GPIOB_PCOR GPIO_PCOR_REG(PTB)
+#define GPIOB_PTOR GPIO_PTOR_REG(PTB)
+#define GPIOB_PDIR GPIO_PDIR_REG(PTB)
+#define GPIOB_PDDR GPIO_PDDR_REG(PTB)
+/* PTC */
+#define GPIOC_PDOR GPIO_PDOR_REG(PTC)
+#define GPIOC_PSOR GPIO_PSOR_REG(PTC)
+#define GPIOC_PCOR GPIO_PCOR_REG(PTC)
+#define GPIOC_PTOR GPIO_PTOR_REG(PTC)
+#define GPIOC_PDIR GPIO_PDIR_REG(PTC)
+#define GPIOC_PDDR GPIO_PDDR_REG(PTC)
+/* PTD */
+#define GPIOD_PDOR GPIO_PDOR_REG(PTD)
+#define GPIOD_PSOR GPIO_PSOR_REG(PTD)
+#define GPIOD_PCOR GPIO_PCOR_REG(PTD)
+#define GPIOD_PTOR GPIO_PTOR_REG(PTD)
+#define GPIOD_PDIR GPIO_PDIR_REG(PTD)
+#define GPIOD_PDDR GPIO_PDDR_REG(PTD)
+/* PTE */
+#define GPIOE_PDOR GPIO_PDOR_REG(PTE)
+#define GPIOE_PSOR GPIO_PSOR_REG(PTE)
+#define GPIOE_PCOR GPIO_PCOR_REG(PTE)
+#define GPIOE_PTOR GPIO_PTOR_REG(PTE)
+#define GPIOE_PDIR GPIO_PDIR_REG(PTE)
+#define GPIOE_PDDR GPIO_PDDR_REG(PTE)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
+ __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
+ __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
+ __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
+ __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
+ __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
+ __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+ __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
+ __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
+ __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
+ __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
+ __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_Type, *I2C_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- I2C - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
+ * @{
+ */
+
+
+/* I2C - Register accessors */
+#define I2C_A1_REG(base) ((base)->A1)
+#define I2C_F_REG(base) ((base)->F)
+#define I2C_C1_REG(base) ((base)->C1)
+#define I2C_S_REG(base) ((base)->S)
+#define I2C_D_REG(base) ((base)->D)
+#define I2C_C2_REG(base) ((base)->C2)
+#define I2C_FLT_REG(base) ((base)->FLT)
+#define I2C_RA_REG(base) ((base)->RA)
+#define I2C_SMB_REG(base) ((base)->SMB)
+#define I2C_A2_REG(base) ((base)->A2)
+#define I2C_SLTH_REG(base) ((base)->SLTH)
+#define I2C_SLTL_REG(base) ((base)->SLTL)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK 0xFEu
+#define I2C_A1_AD_SHIFT 1
+#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
+/* F Bit Fields */
+#define I2C_F_ICR_MASK 0x3Fu
+#define I2C_F_ICR_SHIFT 0
+#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK 0xC0u
+#define I2C_F_MULT_SHIFT 6
+#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
+/* C1 Bit Fields */
+#define I2C_C1_DMAEN_MASK 0x1u
+#define I2C_C1_DMAEN_SHIFT 0
+#define I2C_C1_WUEN_MASK 0x2u
+#define I2C_C1_WUEN_SHIFT 1
+#define I2C_C1_RSTA_MASK 0x4u
+#define I2C_C1_RSTA_SHIFT 2
+#define I2C_C1_TXAK_MASK 0x8u
+#define I2C_C1_TXAK_SHIFT 3
+#define I2C_C1_TX_MASK 0x10u
+#define I2C_C1_TX_SHIFT 4
+#define I2C_C1_MST_MASK 0x20u
+#define I2C_C1_MST_SHIFT 5
+#define I2C_C1_IICIE_MASK 0x40u
+#define I2C_C1_IICIE_SHIFT 6
+#define I2C_C1_IICEN_MASK 0x80u
+#define I2C_C1_IICEN_SHIFT 7
+/* S Bit Fields */
+#define I2C_S_RXAK_MASK 0x1u
+#define I2C_S_RXAK_SHIFT 0
+#define I2C_S_IICIF_MASK 0x2u
+#define I2C_S_IICIF_SHIFT 1
+#define I2C_S_SRW_MASK 0x4u
+#define I2C_S_SRW_SHIFT 2
+#define I2C_S_RAM_MASK 0x8u
+#define I2C_S_RAM_SHIFT 3
+#define I2C_S_ARBL_MASK 0x10u
+#define I2C_S_ARBL_SHIFT 4
+#define I2C_S_BUSY_MASK 0x20u
+#define I2C_S_BUSY_SHIFT 5
+#define I2C_S_IAAS_MASK 0x40u
+#define I2C_S_IAAS_SHIFT 6
+#define I2C_S_TCF_MASK 0x80u
+#define I2C_S_TCF_SHIFT 7
+/* D Bit Fields */
+#define I2C_D_DATA_MASK 0xFFu
+#define I2C_D_DATA_SHIFT 0
+#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
+/* C2 Bit Fields */
+#define I2C_C2_AD_MASK 0x7u
+#define I2C_C2_AD_SHIFT 0
+#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK 0x8u
+#define I2C_C2_RMEN_SHIFT 3
+#define I2C_C2_SBRC_MASK 0x10u
+#define I2C_C2_SBRC_SHIFT 4
+#define I2C_C2_HDRS_MASK 0x20u
+#define I2C_C2_HDRS_SHIFT 5
+#define I2C_C2_ADEXT_MASK 0x40u
+#define I2C_C2_ADEXT_SHIFT 6
+#define I2C_C2_GCAEN_MASK 0x80u
+#define I2C_C2_GCAEN_SHIFT 7
+/* FLT Bit Fields */
+#define I2C_FLT_FLT_MASK 0xFu
+#define I2C_FLT_FLT_SHIFT 0
+#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
+#define I2C_FLT_STARTF_MASK 0x10u
+#define I2C_FLT_STARTF_SHIFT 4
+#define I2C_FLT_SSIE_MASK 0x20u
+#define I2C_FLT_SSIE_SHIFT 5
+#define I2C_FLT_STOPF_MASK 0x40u
+#define I2C_FLT_STOPF_SHIFT 6
+#define I2C_FLT_SHEN_MASK 0x80u
+#define I2C_FLT_SHEN_SHIFT 7
+/* RA Bit Fields */
+#define I2C_RA_RAD_MASK 0xFEu
+#define I2C_RA_RAD_SHIFT 1
+#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
+/* SMB Bit Fields */
+#define I2C_SMB_SHTF2IE_MASK 0x1u
+#define I2C_SMB_SHTF2IE_SHIFT 0
+#define I2C_SMB_SHTF2_MASK 0x2u
+#define I2C_SMB_SHTF2_SHIFT 1
+#define I2C_SMB_SHTF1_MASK 0x4u
+#define I2C_SMB_SHTF1_SHIFT 2
+#define I2C_SMB_SLTF_MASK 0x8u
+#define I2C_SMB_SLTF_SHIFT 3
+#define I2C_SMB_TCKSEL_MASK 0x10u
+#define I2C_SMB_TCKSEL_SHIFT 4
+#define I2C_SMB_SIICAEN_MASK 0x20u
+#define I2C_SMB_SIICAEN_SHIFT 5
+#define I2C_SMB_ALERTEN_MASK 0x40u
+#define I2C_SMB_ALERTEN_SHIFT 6
+#define I2C_SMB_FACK_MASK 0x80u
+#define I2C_SMB_FACK_SHIFT 7
+/* A2 Bit Fields */
+#define I2C_A2_SAD_MASK 0xFEu
+#define I2C_A2_SAD_SHIFT 1
+#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
+/* SLTH Bit Fields */
+#define I2C_SLTH_SSLT_MASK 0xFFu
+#define I2C_SLTH_SSLT_SHIFT 0
+#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
+/* SLTL Bit Fields */
+#define I2C_SLTL_SSLT_MASK 0xFFu
+#define I2C_SLTL_SSLT_SHIFT 0
+#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0 ((I2C_Type *)I2C0_BASE)
+#define I2C0_BASE_PTR (I2C0)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE (0x40067000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1 ((I2C_Type *)I2C1_BASE)
+#define I2C1_BASE_PTR (I2C1)
+/** Peripheral I2C2 base address */
+#define I2C2_BASE (0x400E6000u)
+/** Peripheral I2C2 base pointer */
+#define I2C2 ((I2C_Type *)I2C2_BASE)
+#define I2C2_BASE_PTR (I2C2)
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASES { I2C0, I2C1, I2C2 }
+
+/* ----------------------------------------------------------------------------
+ -- I2C - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
+ * @{
+ */
+
+
+/* I2C - Register instance definitions */
+/* I2C0 */
+#define I2C0_A1 I2C_A1_REG(I2C0)
+#define I2C0_F I2C_F_REG(I2C0)
+#define I2C0_C1 I2C_C1_REG(I2C0)
+#define I2C0_S I2C_S_REG(I2C0)
+#define I2C0_D I2C_D_REG(I2C0)
+#define I2C0_C2 I2C_C2_REG(I2C0)
+#define I2C0_FLT I2C_FLT_REG(I2C0)
+#define I2C0_RA I2C_RA_REG(I2C0)
+#define I2C0_SMB I2C_SMB_REG(I2C0)
+#define I2C0_A2 I2C_A2_REG(I2C0)
+#define I2C0_SLTH I2C_SLTH_REG(I2C0)
+#define I2C0_SLTL I2C_SLTL_REG(I2C0)
+/* I2C1 */
+#define I2C1_A1 I2C_A1_REG(I2C1)
+#define I2C1_F I2C_F_REG(I2C1)
+#define I2C1_C1 I2C_C1_REG(I2C1)
+#define I2C1_S I2C_S_REG(I2C1)
+#define I2C1_D I2C_D_REG(I2C1)
+#define I2C1_C2 I2C_C2_REG(I2C1)
+#define I2C1_FLT I2C_FLT_REG(I2C1)
+#define I2C1_RA I2C_RA_REG(I2C1)
+#define I2C1_SMB I2C_SMB_REG(I2C1)
+#define I2C1_A2 I2C_A2_REG(I2C1)
+#define I2C1_SLTH I2C_SLTH_REG(I2C1)
+#define I2C1_SLTL I2C_SLTL_REG(I2C1)
+/* I2C2 */
+#define I2C2_A1 I2C_A1_REG(I2C2)
+#define I2C2_F I2C_F_REG(I2C2)
+#define I2C2_C1 I2C_C1_REG(I2C2)
+#define I2C2_S I2C_S_REG(I2C2)
+#define I2C2_D I2C_D_REG(I2C2)
+#define I2C2_C2 I2C_C2_REG(I2C2)
+#define I2C2_FLT I2C_FLT_REG(I2C2)
+#define I2C2_RA I2C_RA_REG(I2C2)
+#define I2C2_SMB I2C_SMB_REG(I2C2)
+#define I2C2_A2 I2C_A2_REG(I2C2)
+#define I2C2_SLTH I2C_SLTH_REG(I2C2)
+#define I2C2_SLTL I2C_SLTL_REG(I2C2)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2S Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
+ __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
+ __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
+ __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
+ __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
+ __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
+ uint8_t RESERVED_0[8];
+ __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+ uint8_t RESERVED_1[24];
+ __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
+ uint8_t RESERVED_2[24];
+ __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
+ uint8_t RESERVED_3[28];
+ __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
+ __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
+ __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
+ __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
+ __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
+ __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
+ uint8_t RESERVED_4[8];
+ __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+ uint8_t RESERVED_5[24];
+ __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_6[24];
+ __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
+ uint8_t RESERVED_7[28];
+ __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
+ __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
+} I2S_Type, *I2S_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- I2S - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
+ * @{
+ */
+
+
+/* I2S - Register accessors */
+#define I2S_TCSR_REG(base) ((base)->TCSR)
+#define I2S_TCR1_REG(base) ((base)->TCR1)
+#define I2S_TCR2_REG(base) ((base)->TCR2)
+#define I2S_TCR3_REG(base) ((base)->TCR3)
+#define I2S_TCR4_REG(base) ((base)->TCR4)
+#define I2S_TCR5_REG(base) ((base)->TCR5)
+#define I2S_TDR_REG(base,index) ((base)->TDR[index])
+#define I2S_TFR_REG(base,index) ((base)->TFR[index])
+#define I2S_TMR_REG(base) ((base)->TMR)
+#define I2S_RCSR_REG(base) ((base)->RCSR)
+#define I2S_RCR1_REG(base) ((base)->RCR1)
+#define I2S_RCR2_REG(base) ((base)->RCR2)
+#define I2S_RCR3_REG(base) ((base)->RCR3)
+#define I2S_RCR4_REG(base) ((base)->RCR4)
+#define I2S_RCR5_REG(base) ((base)->RCR5)
+#define I2S_RDR_REG(base,index) ((base)->RDR[index])
+#define I2S_RFR_REG(base,index) ((base)->RFR[index])
+#define I2S_RMR_REG(base) ((base)->RMR)
+#define I2S_MCR_REG(base) ((base)->MCR)
+#define I2S_MDR_REG(base) ((base)->MDR)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2S Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/* TCSR Bit Fields */
+#define I2S_TCSR_FRDE_MASK 0x1u
+#define I2S_TCSR_FRDE_SHIFT 0
+#define I2S_TCSR_FWDE_MASK 0x2u
+#define I2S_TCSR_FWDE_SHIFT 1
+#define I2S_TCSR_FRIE_MASK 0x100u
+#define I2S_TCSR_FRIE_SHIFT 8
+#define I2S_TCSR_FWIE_MASK 0x200u
+#define I2S_TCSR_FWIE_SHIFT 9
+#define I2S_TCSR_FEIE_MASK 0x400u
+#define I2S_TCSR_FEIE_SHIFT 10
+#define I2S_TCSR_SEIE_MASK 0x800u
+#define I2S_TCSR_SEIE_SHIFT 11
+#define I2S_TCSR_WSIE_MASK 0x1000u
+#define I2S_TCSR_WSIE_SHIFT 12
+#define I2S_TCSR_FRF_MASK 0x10000u
+#define I2S_TCSR_FRF_SHIFT 16
+#define I2S_TCSR_FWF_MASK 0x20000u
+#define I2S_TCSR_FWF_SHIFT 17
+#define I2S_TCSR_FEF_MASK 0x40000u
+#define I2S_TCSR_FEF_SHIFT 18
+#define I2S_TCSR_SEF_MASK 0x80000u
+#define I2S_TCSR_SEF_SHIFT 19
+#define I2S_TCSR_WSF_MASK 0x100000u
+#define I2S_TCSR_WSF_SHIFT 20
+#define I2S_TCSR_SR_MASK 0x1000000u
+#define I2S_TCSR_SR_SHIFT 24
+#define I2S_TCSR_FR_MASK 0x2000000u
+#define I2S_TCSR_FR_SHIFT 25
+#define I2S_TCSR_BCE_MASK 0x10000000u
+#define I2S_TCSR_BCE_SHIFT 28
+#define I2S_TCSR_DBGE_MASK 0x20000000u
+#define I2S_TCSR_DBGE_SHIFT 29
+#define I2S_TCSR_STOPE_MASK 0x40000000u
+#define I2S_TCSR_STOPE_SHIFT 30
+#define I2S_TCSR_TE_MASK 0x80000000u
+#define I2S_TCSR_TE_SHIFT 31
+/* TCR1 Bit Fields */
+#define I2S_TCR1_TFW_MASK 0x7u
+#define I2S_TCR1_TFW_SHIFT 0
+#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
+/* TCR2 Bit Fields */
+#define I2S_TCR2_DIV_MASK 0xFFu
+#define I2S_TCR2_DIV_SHIFT 0
+#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK 0x1000000u
+#define I2S_TCR2_BCD_SHIFT 24
+#define I2S_TCR2_BCP_MASK 0x2000000u
+#define I2S_TCR2_BCP_SHIFT 25
+#define I2S_TCR2_MSEL_MASK 0xC000000u
+#define I2S_TCR2_MSEL_SHIFT 26
+#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI_MASK 0x10000000u
+#define I2S_TCR2_BCI_SHIFT 28
+#define I2S_TCR2_BCS_MASK 0x20000000u
+#define I2S_TCR2_BCS_SHIFT 29
+#define I2S_TCR2_SYNC_MASK 0xC0000000u
+#define I2S_TCR2_SYNC_SHIFT 30
+#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
+/* TCR3 Bit Fields */
+#define I2S_TCR3_WDFL_MASK 0x1Fu
+#define I2S_TCR3_WDFL_SHIFT 0
+#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_TCE_MASK 0x30000u
+#define I2S_TCR3_TCE_SHIFT 16
+#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
+/* TCR4 Bit Fields */
+#define I2S_TCR4_FSD_MASK 0x1u
+#define I2S_TCR4_FSD_SHIFT 0
+#define I2S_TCR4_FSP_MASK 0x2u
+#define I2S_TCR4_FSP_SHIFT 1
+#define I2S_TCR4_FSE_MASK 0x8u
+#define I2S_TCR4_FSE_SHIFT 3
+#define I2S_TCR4_MF_MASK 0x10u
+#define I2S_TCR4_MF_SHIFT 4
+#define I2S_TCR4_SYWD_MASK 0x1F00u
+#define I2S_TCR4_SYWD_SHIFT 8
+#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK 0x1F0000u
+#define I2S_TCR4_FRSZ_SHIFT 16
+#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
+/* TCR5 Bit Fields */
+#define I2S_TCR5_FBT_MASK 0x1F00u
+#define I2S_TCR5_FBT_SHIFT 8
+#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK 0x1F0000u
+#define I2S_TCR5_W0W_SHIFT 16
+#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK 0x1F000000u
+#define I2S_TCR5_WNW_SHIFT 24
+#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
+/* TDR Bit Fields */
+#define I2S_TDR_TDR_MASK 0xFFFFFFFFu
+#define I2S_TDR_TDR_SHIFT 0
+#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
+/* TFR Bit Fields */
+#define I2S_TFR_RFP_MASK 0xFu
+#define I2S_TFR_RFP_SHIFT 0
+#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
+#define I2S_TFR_WFP_MASK 0xF0000u
+#define I2S_TFR_WFP_SHIFT 16
+#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
+/* TMR Bit Fields */
+#define I2S_TMR_TWM_MASK 0xFFFFFFFFu
+#define I2S_TMR_TWM_SHIFT 0
+#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
+/* RCSR Bit Fields */
+#define I2S_RCSR_FRDE_MASK 0x1u
+#define I2S_RCSR_FRDE_SHIFT 0
+#define I2S_RCSR_FWDE_MASK 0x2u
+#define I2S_RCSR_FWDE_SHIFT 1
+#define I2S_RCSR_FRIE_MASK 0x100u
+#define I2S_RCSR_FRIE_SHIFT 8
+#define I2S_RCSR_FWIE_MASK 0x200u
+#define I2S_RCSR_FWIE_SHIFT 9
+#define I2S_RCSR_FEIE_MASK 0x400u
+#define I2S_RCSR_FEIE_SHIFT 10
+#define I2S_RCSR_SEIE_MASK 0x800u
+#define I2S_RCSR_SEIE_SHIFT 11
+#define I2S_RCSR_WSIE_MASK 0x1000u
+#define I2S_RCSR_WSIE_SHIFT 12
+#define I2S_RCSR_FRF_MASK 0x10000u
+#define I2S_RCSR_FRF_SHIFT 16
+#define I2S_RCSR_FWF_MASK 0x20000u
+#define I2S_RCSR_FWF_SHIFT 17
+#define I2S_RCSR_FEF_MASK 0x40000u
+#define I2S_RCSR_FEF_SHIFT 18
+#define I2S_RCSR_SEF_MASK 0x80000u
+#define I2S_RCSR_SEF_SHIFT 19
+#define I2S_RCSR_WSF_MASK 0x100000u
+#define I2S_RCSR_WSF_SHIFT 20
+#define I2S_RCSR_SR_MASK 0x1000000u
+#define I2S_RCSR_SR_SHIFT 24
+#define I2S_RCSR_FR_MASK 0x2000000u
+#define I2S_RCSR_FR_SHIFT 25
+#define I2S_RCSR_BCE_MASK 0x10000000u
+#define I2S_RCSR_BCE_SHIFT 28
+#define I2S_RCSR_DBGE_MASK 0x20000000u
+#define I2S_RCSR_DBGE_SHIFT 29
+#define I2S_RCSR_STOPE_MASK 0x40000000u
+#define I2S_RCSR_STOPE_SHIFT 30
+#define I2S_RCSR_RE_MASK 0x80000000u
+#define I2S_RCSR_RE_SHIFT 31
+/* RCR1 Bit Fields */
+#define I2S_RCR1_RFW_MASK 0x7u
+#define I2S_RCR1_RFW_SHIFT 0
+#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
+/* RCR2 Bit Fields */
+#define I2S_RCR2_DIV_MASK 0xFFu
+#define I2S_RCR2_DIV_SHIFT 0
+#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK 0x1000000u
+#define I2S_RCR2_BCD_SHIFT 24
+#define I2S_RCR2_BCP_MASK 0x2000000u
+#define I2S_RCR2_BCP_SHIFT 25
+#define I2S_RCR2_MSEL_MASK 0xC000000u
+#define I2S_RCR2_MSEL_SHIFT 26
+#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI_MASK 0x10000000u
+#define I2S_RCR2_BCI_SHIFT 28
+#define I2S_RCR2_BCS_MASK 0x20000000u
+#define I2S_RCR2_BCS_SHIFT 29
+#define I2S_RCR2_SYNC_MASK 0xC0000000u
+#define I2S_RCR2_SYNC_SHIFT 30
+#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
+/* RCR3 Bit Fields */
+#define I2S_RCR3_WDFL_MASK 0x1Fu
+#define I2S_RCR3_WDFL_SHIFT 0
+#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_RCE_MASK 0x30000u
+#define I2S_RCR3_RCE_SHIFT 16
+#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
+/* RCR4 Bit Fields */
+#define I2S_RCR4_FSD_MASK 0x1u
+#define I2S_RCR4_FSD_SHIFT 0
+#define I2S_RCR4_FSP_MASK 0x2u
+#define I2S_RCR4_FSP_SHIFT 1
+#define I2S_RCR4_FSE_MASK 0x8u
+#define I2S_RCR4_FSE_SHIFT 3
+#define I2S_RCR4_MF_MASK 0x10u
+#define I2S_RCR4_MF_SHIFT 4
+#define I2S_RCR4_SYWD_MASK 0x1F00u
+#define I2S_RCR4_SYWD_SHIFT 8
+#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK 0x1F0000u
+#define I2S_RCR4_FRSZ_SHIFT 16
+#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
+/* RCR5 Bit Fields */
+#define I2S_RCR5_FBT_MASK 0x1F00u
+#define I2S_RCR5_FBT_SHIFT 8
+#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK 0x1F0000u
+#define I2S_RCR5_W0W_SHIFT 16
+#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK 0x1F000000u
+#define I2S_RCR5_WNW_SHIFT 24
+#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
+/* RDR Bit Fields */
+#define I2S_RDR_RDR_MASK 0xFFFFFFFFu
+#define I2S_RDR_RDR_SHIFT 0
+#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
+/* RFR Bit Fields */
+#define I2S_RFR_RFP_MASK 0xFu
+#define I2S_RFR_RFP_SHIFT 0
+#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
+#define I2S_RFR_WFP_MASK 0xF0000u
+#define I2S_RFR_WFP_SHIFT 16
+#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
+/* RMR Bit Fields */
+#define I2S_RMR_RWM_MASK 0xFFFFFFFFu
+#define I2S_RMR_RWM_SHIFT 0
+#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
+/* MCR Bit Fields */
+#define I2S_MCR_MICS_MASK 0x3000000u
+#define I2S_MCR_MICS_SHIFT 24
+#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK 0x40000000u
+#define I2S_MCR_MOE_SHIFT 30
+#define I2S_MCR_DUF_MASK 0x80000000u
+#define I2S_MCR_DUF_SHIFT 31
+/* MDR Bit Fields */
+#define I2S_MDR_DIVIDE_MASK 0xFFFu
+#define I2S_MDR_DIVIDE_SHIFT 0
+#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_FRACT_MASK 0xFF000u
+#define I2S_MDR_FRACT_SHIFT 12
+#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE (0x4002F000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0 ((I2S_Type *)I2S0_BASE)
+#define I2S0_BASE_PTR (I2S0)
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASES { I2S0 }
+
+/* ----------------------------------------------------------------------------
+ -- I2S - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
+ * @{
+ */
+
+
+/* I2S - Register instance definitions */
+/* I2S0 */
+#define I2S0_TCSR I2S_TCSR_REG(I2S0)
+#define I2S0_TCR1 I2S_TCR1_REG(I2S0)
+#define I2S0_TCR2 I2S_TCR2_REG(I2S0)
+#define I2S0_TCR3 I2S_TCR3_REG(I2S0)
+#define I2S0_TCR4 I2S_TCR4_REG(I2S0)
+#define I2S0_TCR5 I2S_TCR5_REG(I2S0)
+#define I2S0_TDR0 I2S_TDR_REG(I2S0,0)
+#define I2S0_TDR1 I2S_TDR_REG(I2S0,1)
+#define I2S0_TFR0 I2S_TFR_REG(I2S0,0)
+#define I2S0_TFR1 I2S_TFR_REG(I2S0,1)
+#define I2S0_TMR I2S_TMR_REG(I2S0)
+#define I2S0_RCSR I2S_RCSR_REG(I2S0)
+#define I2S0_RCR1 I2S_RCR1_REG(I2S0)
+#define I2S0_RCR2 I2S_RCR2_REG(I2S0)
+#define I2S0_RCR3 I2S_RCR3_REG(I2S0)
+#define I2S0_RCR4 I2S_RCR4_REG(I2S0)
+#define I2S0_RCR5 I2S_RCR5_REG(I2S0)
+#define I2S0_RDR0 I2S_RDR_REG(I2S0,0)
+#define I2S0_RDR1 I2S_RDR_REG(I2S0,1)
+#define I2S0_RFR0 I2S_RFR_REG(I2S0,0)
+#define I2S0_RFR1 I2S_RFR_REG(I2S0,1)
+#define I2S0_RMR I2S_RMR_REG(I2S0)
+#define I2S0_MCR I2S_MCR_REG(I2S0)
+#define I2S0_MDR I2S_MDR_REG(I2S0)
+
+/* I2S - Register array accessors */
+#define I2S0_TDR(index) I2S_TDR_REG(I2S0,index)
+#define I2S0_TFR(index) I2S_TFR_REG(I2S0,index)
+#define I2S0_RDR(index) I2S_RDR_REG(I2S0,index)
+#define I2S0_RFR(index) I2S_RFR_REG(I2S0,index)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
+ __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
+ __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
+ __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
+ __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
+ __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
+ __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
+ __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
+ __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
+ __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
+ __IO uint8_t RST; /**< LLWU Reset Enable register, offset: 0xA */
+} LLWU_Type, *LLWU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- LLWU - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
+ * @{
+ */
+
+
+/* LLWU - Register accessors */
+#define LLWU_PE1_REG(base) ((base)->PE1)
+#define LLWU_PE2_REG(base) ((base)->PE2)
+#define LLWU_PE3_REG(base) ((base)->PE3)
+#define LLWU_PE4_REG(base) ((base)->PE4)
+#define LLWU_ME_REG(base) ((base)->ME)
+#define LLWU_F1_REG(base) ((base)->F1)
+#define LLWU_F2_REG(base) ((base)->F2)
+#define LLWU_F3_REG(base) ((base)->F3)
+#define LLWU_FILT1_REG(base) ((base)->FILT1)
+#define LLWU_FILT2_REG(base) ((base)->FILT2)
+#define LLWU_RST_REG(base) ((base)->RST)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/* PE1 Bit Fields */
+#define LLWU_PE1_WUPE0_MASK 0x3u
+#define LLWU_PE1_WUPE0_SHIFT 0
+#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK 0xCu
+#define LLWU_PE1_WUPE1_SHIFT 2
+#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK 0x30u
+#define LLWU_PE1_WUPE2_SHIFT 4
+#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK 0xC0u
+#define LLWU_PE1_WUPE3_SHIFT 6
+#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
+/* PE2 Bit Fields */
+#define LLWU_PE2_WUPE4_MASK 0x3u
+#define LLWU_PE2_WUPE4_SHIFT 0
+#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK 0xCu
+#define LLWU_PE2_WUPE5_SHIFT 2
+#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK 0x30u
+#define LLWU_PE2_WUPE6_SHIFT 4
+#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK 0xC0u
+#define LLWU_PE2_WUPE7_SHIFT 6
+#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
+/* PE3 Bit Fields */
+#define LLWU_PE3_WUPE8_MASK 0x3u
+#define LLWU_PE3_WUPE8_SHIFT 0
+#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK 0xCu
+#define LLWU_PE3_WUPE9_SHIFT 2
+#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK 0x30u
+#define LLWU_PE3_WUPE10_SHIFT 4
+#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK 0xC0u
+#define LLWU_PE3_WUPE11_SHIFT 6
+#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
+/* PE4 Bit Fields */
+#define LLWU_PE4_WUPE12_MASK 0x3u
+#define LLWU_PE4_WUPE12_SHIFT 0
+#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK 0xCu
+#define LLWU_PE4_WUPE13_SHIFT 2
+#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK 0x30u
+#define LLWU_PE4_WUPE14_SHIFT 4
+#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK 0xC0u
+#define LLWU_PE4_WUPE15_SHIFT 6
+#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
+/* ME Bit Fields */
+#define LLWU_ME_WUME0_MASK 0x1u
+#define LLWU_ME_WUME0_SHIFT 0
+#define LLWU_ME_WUME1_MASK 0x2u
+#define LLWU_ME_WUME1_SHIFT 1
+#define LLWU_ME_WUME2_MASK 0x4u
+#define LLWU_ME_WUME2_SHIFT 2
+#define LLWU_ME_WUME3_MASK 0x8u
+#define LLWU_ME_WUME3_SHIFT 3
+#define LLWU_ME_WUME4_MASK 0x10u
+#define LLWU_ME_WUME4_SHIFT 4
+#define LLWU_ME_WUME5_MASK 0x20u
+#define LLWU_ME_WUME5_SHIFT 5
+#define LLWU_ME_WUME6_MASK 0x40u
+#define LLWU_ME_WUME6_SHIFT 6
+#define LLWU_ME_WUME7_MASK 0x80u
+#define LLWU_ME_WUME7_SHIFT 7
+/* F1 Bit Fields */
+#define LLWU_F1_WUF0_MASK 0x1u
+#define LLWU_F1_WUF0_SHIFT 0
+#define LLWU_F1_WUF1_MASK 0x2u
+#define LLWU_F1_WUF1_SHIFT 1
+#define LLWU_F1_WUF2_MASK 0x4u
+#define LLWU_F1_WUF2_SHIFT 2
+#define LLWU_F1_WUF3_MASK 0x8u
+#define LLWU_F1_WUF3_SHIFT 3
+#define LLWU_F1_WUF4_MASK 0x10u
+#define LLWU_F1_WUF4_SHIFT 4
+#define LLWU_F1_WUF5_MASK 0x20u
+#define LLWU_F1_WUF5_SHIFT 5
+#define LLWU_F1_WUF6_MASK 0x40u
+#define LLWU_F1_WUF6_SHIFT 6
+#define LLWU_F1_WUF7_MASK 0x80u
+#define LLWU_F1_WUF7_SHIFT 7
+/* F2 Bit Fields */
+#define LLWU_F2_WUF8_MASK 0x1u
+#define LLWU_F2_WUF8_SHIFT 0
+#define LLWU_F2_WUF9_MASK 0x2u
+#define LLWU_F2_WUF9_SHIFT 1
+#define LLWU_F2_WUF10_MASK 0x4u
+#define LLWU_F2_WUF10_SHIFT 2
+#define LLWU_F2_WUF11_MASK 0x8u
+#define LLWU_F2_WUF11_SHIFT 3
+#define LLWU_F2_WUF12_MASK 0x10u
+#define LLWU_F2_WUF12_SHIFT 4
+#define LLWU_F2_WUF13_MASK 0x20u
+#define LLWU_F2_WUF13_SHIFT 5
+#define LLWU_F2_WUF14_MASK 0x40u
+#define LLWU_F2_WUF14_SHIFT 6
+#define LLWU_F2_WUF15_MASK 0x80u
+#define LLWU_F2_WUF15_SHIFT 7
+/* F3 Bit Fields */
+#define LLWU_F3_MWUF0_MASK 0x1u
+#define LLWU_F3_MWUF0_SHIFT 0
+#define LLWU_F3_MWUF1_MASK 0x2u
+#define LLWU_F3_MWUF1_SHIFT 1
+#define LLWU_F3_MWUF2_MASK 0x4u
+#define LLWU_F3_MWUF2_SHIFT 2
+#define LLWU_F3_MWUF3_MASK 0x8u
+#define LLWU_F3_MWUF3_SHIFT 3
+#define LLWU_F3_MWUF4_MASK 0x10u
+#define LLWU_F3_MWUF4_SHIFT 4
+#define LLWU_F3_MWUF5_MASK 0x20u
+#define LLWU_F3_MWUF5_SHIFT 5
+#define LLWU_F3_MWUF6_MASK 0x40u
+#define LLWU_F3_MWUF6_SHIFT 6
+#define LLWU_F3_MWUF7_MASK 0x80u
+#define LLWU_F3_MWUF7_SHIFT 7
+/* FILT1 Bit Fields */
+#define LLWU_FILT1_FILTSEL_MASK 0xFu
+#define LLWU_FILT1_FILTSEL_SHIFT 0
+#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK 0x60u
+#define LLWU_FILT1_FILTE_SHIFT 5
+#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK 0x80u
+#define LLWU_FILT1_FILTF_SHIFT 7
+/* FILT2 Bit Fields */
+#define LLWU_FILT2_FILTSEL_MASK 0xFu
+#define LLWU_FILT2_FILTSEL_SHIFT 0
+#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK 0x60u
+#define LLWU_FILT2_FILTE_SHIFT 5
+#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK 0x80u
+#define LLWU_FILT2_FILTF_SHIFT 7
+/* RST Bit Fields */
+#define LLWU_RST_RSTFILT_MASK 0x1u
+#define LLWU_RST_RSTFILT_SHIFT 0
+#define LLWU_RST_LLRSTE_MASK 0x2u
+#define LLWU_RST_LLRSTE_SHIFT 1
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU ((LLWU_Type *)LLWU_BASE)
+#define LLWU_BASE_PTR (LLWU)
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASES { LLWU }
+
+/* ----------------------------------------------------------------------------
+ -- LLWU - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
+ * @{
+ */
+
+
+/* LLWU - Register instance definitions */
+/* LLWU */
+#define LLWU_PE1 LLWU_PE1_REG(LLWU)
+#define LLWU_PE2 LLWU_PE2_REG(LLWU)
+#define LLWU_PE3 LLWU_PE3_REG(LLWU)
+#define LLWU_PE4 LLWU_PE4_REG(LLWU)
+#define LLWU_ME LLWU_ME_REG(LLWU)
+#define LLWU_F1 LLWU_F1_REG(LLWU)
+#define LLWU_F2 LLWU_F2_REG(LLWU)
+#define LLWU_F3 LLWU_F3_REG(LLWU)
+#define LLWU_FILT1 LLWU_FILT1_REG(LLWU)
+#define LLWU_FILT2 LLWU_FILT2_REG(LLWU)
+#define LLWU_RST LLWU_RST_REG(LLWU)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
+ __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
+ __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
+ __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type, *LPTMR_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
+ * @{
+ */
+
+
+/* LPTMR - Register accessors */
+#define LPTMR_CSR_REG(base) ((base)->CSR)
+#define LPTMR_PSR_REG(base) ((base)->PSR)
+#define LPTMR_CMR_REG(base) ((base)->CMR)
+#define LPTMR_CNR_REG(base) ((base)->CNR)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/* CSR Bit Fields */
+#define LPTMR_CSR_TEN_MASK 0x1u
+#define LPTMR_CSR_TEN_SHIFT 0
+#define LPTMR_CSR_TMS_MASK 0x2u
+#define LPTMR_CSR_TMS_SHIFT 1
+#define LPTMR_CSR_TFC_MASK 0x4u
+#define LPTMR_CSR_TFC_SHIFT 2
+#define LPTMR_CSR_TPP_MASK 0x8u
+#define LPTMR_CSR_TPP_SHIFT 3
+#define LPTMR_CSR_TPS_MASK 0x30u
+#define LPTMR_CSR_TPS_SHIFT 4
+#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK 0x40u
+#define LPTMR_CSR_TIE_SHIFT 6
+#define LPTMR_CSR_TCF_MASK 0x80u
+#define LPTMR_CSR_TCF_SHIFT 7
+/* PSR Bit Fields */
+#define LPTMR_PSR_PCS_MASK 0x3u
+#define LPTMR_PSR_PCS_SHIFT 0
+#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK 0x4u
+#define LPTMR_PSR_PBYP_SHIFT 2
+#define LPTMR_PSR_PRESCALE_MASK 0x78u
+#define LPTMR_PSR_PRESCALE_SHIFT 3
+#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
+/* CMR Bit Fields */
+#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
+#define LPTMR_CMR_COMPARE_SHIFT 0
+#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
+/* CNR Bit Fields */
+#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
+#define LPTMR_CNR_COUNTER_SHIFT 0
+#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
+#define LPTMR0_BASE_PTR (LPTMR0)
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASES { LPTMR0 }
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
+ * @{
+ */
+
+
+/* LPTMR - Register instance definitions */
+/* LPTMR0 */
+#define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0)
+#define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0)
+#define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0)
+#define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
+ __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
+ __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
+ __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
+ __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
+ __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
+ __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+ __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+ __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
+ __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
+} MCG_Type, *MCG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- MCG - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
+ * @{
+ */
+
+
+/* MCG - Register accessors */
+#define MCG_C1_REG(base) ((base)->C1)
+#define MCG_C2_REG(base) ((base)->C2)
+#define MCG_C3_REG(base) ((base)->C3)
+#define MCG_C4_REG(base) ((base)->C4)
+#define MCG_C5_REG(base) ((base)->C5)
+#define MCG_C6_REG(base) ((base)->C6)
+#define MCG_S_REG(base) ((base)->S)
+#define MCG_SC_REG(base) ((base)->SC)
+#define MCG_ATCVH_REG(base) ((base)->ATCVH)
+#define MCG_ATCVL_REG(base) ((base)->ATCVL)
+#define MCG_C7_REG(base) ((base)->C7)
+#define MCG_C8_REG(base) ((base)->C8)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define MCG_C1_IREFSTEN_MASK 0x1u
+#define MCG_C1_IREFSTEN_SHIFT 0
+#define MCG_C1_IRCLKEN_MASK 0x2u
+#define MCG_C1_IRCLKEN_SHIFT 1
+#define MCG_C1_IREFS_MASK 0x4u
+#define MCG_C1_IREFS_SHIFT 2
+#define MCG_C1_FRDIV_MASK 0x38u
+#define MCG_C1_FRDIV_SHIFT 3
+#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK 0xC0u
+#define MCG_C1_CLKS_SHIFT 6
+#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
+/* C2 Bit Fields */
+#define MCG_C2_IRCS_MASK 0x1u
+#define MCG_C2_IRCS_SHIFT 0
+#define MCG_C2_LP_MASK 0x2u
+#define MCG_C2_LP_SHIFT 1
+#define MCG_C2_EREFS_MASK 0x4u
+#define MCG_C2_EREFS_SHIFT 2
+#define MCG_C2_HGO_MASK 0x8u
+#define MCG_C2_HGO_SHIFT 3
+#define MCG_C2_RANGE_MASK 0x30u
+#define MCG_C2_RANGE_SHIFT 4
+#define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)
+#define MCG_C2_FCFTRIM_MASK 0x40u
+#define MCG_C2_FCFTRIM_SHIFT 6
+#define MCG_C2_LOCRE0_MASK 0x80u
+#define MCG_C2_LOCRE0_SHIFT 7
+/* C3 Bit Fields */
+#define MCG_C3_SCTRIM_MASK 0xFFu
+#define MCG_C3_SCTRIM_SHIFT 0
+#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
+/* C4 Bit Fields */
+#define MCG_C4_SCFTRIM_MASK 0x1u
+#define MCG_C4_SCFTRIM_SHIFT 0
+#define MCG_C4_FCTRIM_MASK 0x1Eu
+#define MCG_C4_FCTRIM_SHIFT 1
+#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK 0x60u
+#define MCG_C4_DRST_DRS_SHIFT 5
+#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK 0x80u
+#define MCG_C4_DMX32_SHIFT 7
+/* C5 Bit Fields */
+#define MCG_C5_PRDIV0_MASK 0x1Fu
+#define MCG_C5_PRDIV0_SHIFT 0
+#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
+#define MCG_C5_PLLSTEN0_MASK 0x20u
+#define MCG_C5_PLLSTEN0_SHIFT 5
+#define MCG_C5_PLLCLKEN0_MASK 0x40u
+#define MCG_C5_PLLCLKEN0_SHIFT 6
+/* C6 Bit Fields */
+#define MCG_C6_VDIV0_MASK 0x1Fu
+#define MCG_C6_VDIV0_SHIFT 0
+#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
+#define MCG_C6_CME0_MASK 0x20u
+#define MCG_C6_CME0_SHIFT 5
+#define MCG_C6_PLLS_MASK 0x40u
+#define MCG_C6_PLLS_SHIFT 6
+#define MCG_C6_LOLIE0_MASK 0x80u
+#define MCG_C6_LOLIE0_SHIFT 7
+/* S Bit Fields */
+#define MCG_S_IRCST_MASK 0x1u
+#define MCG_S_IRCST_SHIFT 0
+#define MCG_S_OSCINIT0_MASK 0x2u
+#define MCG_S_OSCINIT0_SHIFT 1
+#define MCG_S_CLKST_MASK 0xCu
+#define MCG_S_CLKST_SHIFT 2
+#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK 0x10u
+#define MCG_S_IREFST_SHIFT 4
+#define MCG_S_PLLST_MASK 0x20u
+#define MCG_S_PLLST_SHIFT 5
+#define MCG_S_LOCK0_MASK 0x40u
+#define MCG_S_LOCK0_SHIFT 6
+#define MCG_S_LOLS0_MASK 0x80u
+#define MCG_S_LOLS0_SHIFT 7
+/* SC Bit Fields */
+#define MCG_SC_LOCS0_MASK 0x1u
+#define MCG_SC_LOCS0_SHIFT 0
+#define MCG_SC_FCRDIV_MASK 0xEu
+#define MCG_SC_FCRDIV_SHIFT 1
+#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK 0x10u
+#define MCG_SC_FLTPRSRV_SHIFT 4
+#define MCG_SC_ATMF_MASK 0x20u
+#define MCG_SC_ATMF_SHIFT 5
+#define MCG_SC_ATMS_MASK 0x40u
+#define MCG_SC_ATMS_SHIFT 6
+#define MCG_SC_ATME_MASK 0x80u
+#define MCG_SC_ATME_SHIFT 7
+/* ATCVH Bit Fields */
+#define MCG_ATCVH_ATCVH_MASK 0xFFu
+#define MCG_ATCVH_ATCVH_SHIFT 0
+#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
+/* ATCVL Bit Fields */
+#define MCG_ATCVL_ATCVL_MASK 0xFFu
+#define MCG_ATCVL_ATCVL_SHIFT 0
+#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
+/* C7 Bit Fields */
+#define MCG_C7_OSCSEL_MASK 0x3u
+#define MCG_C7_OSCSEL_SHIFT 0
+#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x))<<MCG_C7_OSCSEL_SHIFT))&MCG_C7_OSCSEL_MASK)
+/* C8 Bit Fields */
+#define MCG_C8_LOCS1_MASK 0x1u
+#define MCG_C8_LOCS1_SHIFT 0
+#define MCG_C8_CME1_MASK 0x20u
+#define MCG_C8_CME1_SHIFT 5
+#define MCG_C8_LOLRE_MASK 0x40u
+#define MCG_C8_LOLRE_SHIFT 6
+#define MCG_C8_LOCRE1_MASK 0x80u
+#define MCG_C8_LOCRE1_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG ((MCG_Type *)MCG_BASE)
+#define MCG_BASE_PTR (MCG)
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASES { MCG }
+
+/* ----------------------------------------------------------------------------
+ -- MCG - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
+ * @{
+ */
+
+
+/* MCG - Register instance definitions */
+/* MCG */
+#define MCG_C1 MCG_C1_REG(MCG)
+#define MCG_C2 MCG_C2_REG(MCG)
+#define MCG_C3 MCG_C3_REG(MCG)
+#define MCG_C4 MCG_C4_REG(MCG)
+#define MCG_C5 MCG_C5_REG(MCG)
+#define MCG_C6 MCG_C6_REG(MCG)
+#define MCG_S MCG_S_REG(MCG)
+#define MCG_SC MCG_SC_REG(MCG)
+#define MCG_ATCVH MCG_ATCVH_REG(MCG)
+#define MCG_ATCVL MCG_ATCVL_REG(MCG)
+#define MCG_C7 MCG_C7_REG(MCG)
+#define MCG_C8 MCG_C8_REG(MCG)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[8];
+ __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+ __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+ __IO uint32_t CR; /**< Control Register, offset: 0xC */
+ __IO uint32_t ISR; /**< Interrupt Status Register, offset: 0x10 */
+ __IO uint32_t ETBCC; /**< ETB Counter Control register, offset: 0x14 */
+ __IO uint32_t ETBRL; /**< ETB Reload register, offset: 0x18 */
+ __I uint32_t ETBCNT; /**< ETB Counter Value register, offset: 0x1C */
+ uint8_t RESERVED_1[16];
+ __IO uint32_t PID; /**< Process ID register, offset: 0x30 */
+} MCM_Type, *MCM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- MCM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
+ * @{
+ */
+
+
+/* MCM - Register accessors */
+#define MCM_PLASC_REG(base) ((base)->PLASC)
+#define MCM_PLAMC_REG(base) ((base)->PLAMC)
+#define MCM_CR_REG(base) ((base)->CR)
+#define MCM_ISR_REG(base) ((base)->ISR)
+#define MCM_ETBCC_REG(base) ((base)->ETBCC)
+#define MCM_ETBRL_REG(base) ((base)->ETBRL)
+#define MCM_ETBCNT_REG(base) ((base)->ETBCNT)
+#define MCM_PID_REG(base) ((base)->PID)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/* PLASC Bit Fields */
+#define MCM_PLASC_ASC_MASK 0xFFu
+#define MCM_PLASC_ASC_SHIFT 0
+#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
+/* PLAMC Bit Fields */
+#define MCM_PLAMC_AMC_MASK 0xFFu
+#define MCM_PLAMC_AMC_SHIFT 0
+#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
+/* CR Bit Fields */
+#define MCM_CR_SRAMUAP_MASK 0x3000000u
+#define MCM_CR_SRAMUAP_SHIFT 24
+#define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMUAP_SHIFT))&MCM_CR_SRAMUAP_MASK)
+#define MCM_CR_SRAMUWP_MASK 0x4000000u
+#define MCM_CR_SRAMUWP_SHIFT 26
+#define MCM_CR_SRAMLAP_MASK 0x30000000u
+#define MCM_CR_SRAMLAP_SHIFT 28
+#define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMLAP_SHIFT))&MCM_CR_SRAMLAP_MASK)
+#define MCM_CR_SRAMLWP_MASK 0x40000000u
+#define MCM_CR_SRAMLWP_SHIFT 30
+/* ISR Bit Fields */
+#define MCM_ISR_IRQ_MASK 0x2u
+#define MCM_ISR_IRQ_SHIFT 1
+#define MCM_ISR_NMI_MASK 0x4u
+#define MCM_ISR_NMI_SHIFT 2
+#define MCM_ISR_DHREQ_MASK 0x8u
+#define MCM_ISR_DHREQ_SHIFT 3
+#define MCM_ISR_FIOC_MASK 0x100u
+#define MCM_ISR_FIOC_SHIFT 8
+#define MCM_ISR_FDZC_MASK 0x200u
+#define MCM_ISR_FDZC_SHIFT 9
+#define MCM_ISR_FOFC_MASK 0x400u
+#define MCM_ISR_FOFC_SHIFT 10
+#define MCM_ISR_FUFC_MASK 0x800u
+#define MCM_ISR_FUFC_SHIFT 11
+#define MCM_ISR_FIXC_MASK 0x1000u
+#define MCM_ISR_FIXC_SHIFT 12
+#define MCM_ISR_FIDC_MASK 0x8000u
+#define MCM_ISR_FIDC_SHIFT 15
+#define MCM_ISR_FIOCE_MASK 0x1000000u
+#define MCM_ISR_FIOCE_SHIFT 24
+#define MCM_ISR_FDZCE_MASK 0x2000000u
+#define MCM_ISR_FDZCE_SHIFT 25
+#define MCM_ISR_FOFCE_MASK 0x4000000u
+#define MCM_ISR_FOFCE_SHIFT 26
+#define MCM_ISR_FUFCE_MASK 0x8000000u
+#define MCM_ISR_FUFCE_SHIFT 27
+#define MCM_ISR_FIXCE_MASK 0x10000000u
+#define MCM_ISR_FIXCE_SHIFT 28
+#define MCM_ISR_FIDCE_MASK 0x80000000u
+#define MCM_ISR_FIDCE_SHIFT 31
+/* ETBCC Bit Fields */
+#define MCM_ETBCC_CNTEN_MASK 0x1u
+#define MCM_ETBCC_CNTEN_SHIFT 0
+#define MCM_ETBCC_RSPT_MASK 0x6u
+#define MCM_ETBCC_RSPT_SHIFT 1
+#define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RSPT_SHIFT))&MCM_ETBCC_RSPT_MASK)
+#define MCM_ETBCC_RLRQ_MASK 0x8u
+#define MCM_ETBCC_RLRQ_SHIFT 3
+#define MCM_ETBCC_ETDIS_MASK 0x10u
+#define MCM_ETBCC_ETDIS_SHIFT 4
+#define MCM_ETBCC_ITDIS_MASK 0x20u
+#define MCM_ETBCC_ITDIS_SHIFT 5
+/* ETBRL Bit Fields */
+#define MCM_ETBRL_RELOAD_MASK 0x7FFu
+#define MCM_ETBRL_RELOAD_SHIFT 0
+#define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBRL_RELOAD_SHIFT))&MCM_ETBRL_RELOAD_MASK)
+/* ETBCNT Bit Fields */
+#define MCM_ETBCNT_COUNTER_MASK 0x7FFu
+#define MCM_ETBCNT_COUNTER_SHIFT 0
+#define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCNT_COUNTER_SHIFT))&MCM_ETBCNT_COUNTER_MASK)
+/* PID Bit Fields */
+#define MCM_PID_PID_MASK 0xFFu
+#define MCM_PID_PID_SHIFT 0
+#define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x))<<MCM_PID_PID_SHIFT))&MCM_PID_PID_MASK)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE (0xE0080000u)
+/** Peripheral MCM base pointer */
+#define MCM ((MCM_Type *)MCM_BASE)
+#define MCM_BASE_PTR (MCM)
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASES { MCM }
+
+/* ----------------------------------------------------------------------------
+ -- MCM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
+ * @{
+ */
+
+
+/* MCM - Register instance definitions */
+/* MCM */
+#define MCM_PLASC MCM_PLASC_REG(MCM)
+#define MCM_PLAMC MCM_PLAMC_REG(MCM)
+#define MCM_CR MCM_CR_REG(MCM)
+#define MCM_ISCR MCM_ISR_REG(MCM)
+#define MCM_ETBCC MCM_ETBCC_REG(MCM)
+#define MCM_ETBRL MCM_ETBRL_REG(MCM)
+#define MCM_ETBCNT MCM_ETBCNT_REG(MCM)
+#define MCM_PID MCM_PID_REG(MCM)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MPU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
+ * @{
+ */
+
+/** MPU - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */
+ uint8_t RESERVED_0[12];
+ struct { /* offset: 0x10, array step: 0x8 */
+ __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
+ __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
+ } SP[5];
+ uint8_t RESERVED_1[968];
+ __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
+ uint8_t RESERVED_2[832];
+ __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
+} MPU_Type, *MPU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- MPU - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
+ * @{
+ */
+
+
+/* MPU - Register accessors */
+#define MPU_CESR_REG(base) ((base)->CESR)
+#define MPU_EAR_REG(base,index) ((base)->SP[index].EAR)
+#define MPU_EDR_REG(base,index) ((base)->SP[index].EDR)
+#define MPU_WORD_REG(base,index,index2) ((base)->WORD[index][index2])
+#define MPU_RGDAAC_REG(base,index) ((base)->RGDAAC[index])
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- MPU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Masks MPU Register Masks
+ * @{
+ */
+
+/* CESR Bit Fields */
+#define MPU_CESR_VLD_MASK 0x1u
+#define MPU_CESR_VLD_SHIFT 0
+#define MPU_CESR_NRGD_MASK 0xF00u
+#define MPU_CESR_NRGD_SHIFT 8
+#define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK)
+#define MPU_CESR_NSP_MASK 0xF000u
+#define MPU_CESR_NSP_SHIFT 12
+#define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK)
+#define MPU_CESR_HRL_MASK 0xF0000u
+#define MPU_CESR_HRL_SHIFT 16
+#define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK)
+#define MPU_CESR_SPERR_MASK 0xF8000000u
+#define MPU_CESR_SPERR_SHIFT 27
+#define MPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR_SHIFT))&MPU_CESR_SPERR_MASK)
+/* EAR Bit Fields */
+#define MPU_EAR_EADDR_MASK 0xFFFFFFFFu
+#define MPU_EAR_EADDR_SHIFT 0
+#define MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK)
+/* EDR Bit Fields */
+#define MPU_EDR_ERW_MASK 0x1u
+#define MPU_EDR_ERW_SHIFT 0
+#define MPU_EDR_EATTR_MASK 0xEu
+#define MPU_EDR_EATTR_SHIFT 1
+#define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK)
+#define MPU_EDR_EMN_MASK 0xF0u
+#define MPU_EDR_EMN_SHIFT 4
+#define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK)
+#define MPU_EDR_EPID_MASK 0xFF00u
+#define MPU_EDR_EPID_SHIFT 8
+#define MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EPID_SHIFT))&MPU_EDR_EPID_MASK)
+#define MPU_EDR_EACD_MASK 0xFFFF0000u
+#define MPU_EDR_EACD_SHIFT 16
+#define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK)
+/* WORD Bit Fields */
+#define MPU_WORD_VLD_MASK 0x1u
+#define MPU_WORD_VLD_SHIFT 0
+#define MPU_WORD_M0UM_MASK 0x7u
+#define MPU_WORD_M0UM_SHIFT 0
+#define MPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0UM_SHIFT))&MPU_WORD_M0UM_MASK)
+#define MPU_WORD_M0SM_MASK 0x18u
+#define MPU_WORD_M0SM_SHIFT 3
+#define MPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0SM_SHIFT))&MPU_WORD_M0SM_MASK)
+#define MPU_WORD_M0PE_MASK 0x20u
+#define MPU_WORD_M0PE_SHIFT 5
+#define MPU_WORD_ENDADDR_MASK 0xFFFFFFE0u
+#define MPU_WORD_ENDADDR_SHIFT 5
+#define MPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_ENDADDR_SHIFT))&MPU_WORD_ENDADDR_MASK)
+#define MPU_WORD_SRTADDR_MASK 0xFFFFFFE0u
+#define MPU_WORD_SRTADDR_SHIFT 5
+#define MPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_SRTADDR_SHIFT))&MPU_WORD_SRTADDR_MASK)
+#define MPU_WORD_M1UM_MASK 0x1C0u
+#define MPU_WORD_M1UM_SHIFT 6
+#define MPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1UM_SHIFT))&MPU_WORD_M1UM_MASK)
+#define MPU_WORD_M1SM_MASK 0x600u
+#define MPU_WORD_M1SM_SHIFT 9
+#define MPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1SM_SHIFT))&MPU_WORD_M1SM_MASK)
+#define MPU_WORD_M1PE_MASK 0x800u
+#define MPU_WORD_M1PE_SHIFT 11
+#define MPU_WORD_M2UM_MASK 0x7000u
+#define MPU_WORD_M2UM_SHIFT 12
+#define MPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2UM_SHIFT))&MPU_WORD_M2UM_MASK)
+#define MPU_WORD_M2SM_MASK 0x18000u
+#define MPU_WORD_M2SM_SHIFT 15
+#define MPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2SM_SHIFT))&MPU_WORD_M2SM_MASK)
+#define MPU_WORD_PIDMASK_MASK 0xFF0000u
+#define MPU_WORD_PIDMASK_SHIFT 16
+#define MPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PIDMASK_SHIFT))&MPU_WORD_PIDMASK_MASK)
+#define MPU_WORD_M2PE_MASK 0x20000u
+#define MPU_WORD_M2PE_SHIFT 17
+#define MPU_WORD_M3UM_MASK 0x1C0000u
+#define MPU_WORD_M3UM_SHIFT 18
+#define MPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3UM_SHIFT))&MPU_WORD_M3UM_MASK)
+#define MPU_WORD_M3SM_MASK 0x600000u
+#define MPU_WORD_M3SM_SHIFT 21
+#define MPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3SM_SHIFT))&MPU_WORD_M3SM_MASK)
+#define MPU_WORD_M3PE_MASK 0x800000u
+#define MPU_WORD_M3PE_SHIFT 23
+#define MPU_WORD_PID_MASK 0xFF000000u
+#define MPU_WORD_PID_SHIFT 24
+#define MPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PID_SHIFT))&MPU_WORD_PID_MASK)
+#define MPU_WORD_M4WE_MASK 0x1000000u
+#define MPU_WORD_M4WE_SHIFT 24
+#define MPU_WORD_M4RE_MASK 0x2000000u
+#define MPU_WORD_M4RE_SHIFT 25
+#define MPU_WORD_M5WE_MASK 0x4000000u
+#define MPU_WORD_M5WE_SHIFT 26
+#define MPU_WORD_M5RE_MASK 0x8000000u
+#define MPU_WORD_M5RE_SHIFT 27
+#define MPU_WORD_M6WE_MASK 0x10000000u
+#define MPU_WORD_M6WE_SHIFT 28
+#define MPU_WORD_M6RE_MASK 0x20000000u
+#define MPU_WORD_M6RE_SHIFT 29
+#define MPU_WORD_M7WE_MASK 0x40000000u
+#define MPU_WORD_M7WE_SHIFT 30
+#define MPU_WORD_M7RE_MASK 0x80000000u
+#define MPU_WORD_M7RE_SHIFT 31
+/* RGDAAC Bit Fields */
+#define MPU_RGDAAC_M0UM_MASK 0x7u
+#define MPU_RGDAAC_M0UM_SHIFT 0
+#define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK)
+#define MPU_RGDAAC_M0SM_MASK 0x18u
+#define MPU_RGDAAC_M0SM_SHIFT 3
+#define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK)
+#define MPU_RGDAAC_M0PE_MASK 0x20u
+#define MPU_RGDAAC_M0PE_SHIFT 5
+#define MPU_RGDAAC_M1UM_MASK 0x1C0u
+#define MPU_RGDAAC_M1UM_SHIFT 6
+#define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK)
+#define MPU_RGDAAC_M1SM_MASK 0x600u
+#define MPU_RGDAAC_M1SM_SHIFT 9
+#define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK)
+#define MPU_RGDAAC_M1PE_MASK 0x800u
+#define MPU_RGDAAC_M1PE_SHIFT 11
+#define MPU_RGDAAC_M2UM_MASK 0x7000u
+#define MPU_RGDAAC_M2UM_SHIFT 12
+#define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK)
+#define MPU_RGDAAC_M2SM_MASK 0x18000u
+#define MPU_RGDAAC_M2SM_SHIFT 15
+#define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK)
+#define MPU_RGDAAC_M2PE_MASK 0x20000u
+#define MPU_RGDAAC_M2PE_SHIFT 17
+#define MPU_RGDAAC_M3UM_MASK 0x1C0000u
+#define MPU_RGDAAC_M3UM_SHIFT 18
+#define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK)
+#define MPU_RGDAAC_M3SM_MASK 0x600000u
+#define MPU_RGDAAC_M3SM_SHIFT 21
+#define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK)
+#define MPU_RGDAAC_M3PE_MASK 0x800000u
+#define MPU_RGDAAC_M3PE_SHIFT 23
+#define MPU_RGDAAC_M4WE_MASK 0x1000000u
+#define MPU_RGDAAC_M4WE_SHIFT 24
+#define MPU_RGDAAC_M4RE_MASK 0x2000000u
+#define MPU_RGDAAC_M4RE_SHIFT 25
+#define MPU_RGDAAC_M5WE_MASK 0x4000000u
+#define MPU_RGDAAC_M5WE_SHIFT 26
+#define MPU_RGDAAC_M5RE_MASK 0x8000000u
+#define MPU_RGDAAC_M5RE_SHIFT 27
+#define MPU_RGDAAC_M6WE_MASK 0x10000000u
+#define MPU_RGDAAC_M6WE_SHIFT 28
+#define MPU_RGDAAC_M6RE_MASK 0x20000000u
+#define MPU_RGDAAC_M6RE_SHIFT 29
+#define MPU_RGDAAC_M7WE_MASK 0x40000000u
+#define MPU_RGDAAC_M7WE_SHIFT 30
+#define MPU_RGDAAC_M7RE_MASK 0x80000000u
+#define MPU_RGDAAC_M7RE_SHIFT 31
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Masks */
+
+
+/* MPU - Peripheral instance base addresses */
+/** Peripheral MPU base address */
+#define MPU_BASE (0x4000D000u)
+/** Peripheral MPU base pointer */
+#define MPU ((MPU_Type *)MPU_BASE)
+#define MPU_BASE_PTR (MPU)
+/** Array initializer of MPU peripheral base pointers */
+#define MPU_BASES { MPU }
+
+/* ----------------------------------------------------------------------------
+ -- MPU - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
+ * @{
+ */
+
+
+/* MPU - Register instance definitions */
+/* MPU */
+#define MPU_CESR MPU_CESR_REG(MPU)
+#define MPU_EAR0 MPU_EAR_REG(MPU,0)
+#define MPU_EDR0 MPU_EDR_REG(MPU,0)
+#define MPU_EAR1 MPU_EAR_REG(MPU,1)
+#define MPU_EDR1 MPU_EDR_REG(MPU,1)
+#define MPU_EAR2 MPU_EAR_REG(MPU,2)
+#define MPU_EDR2 MPU_EDR_REG(MPU,2)
+#define MPU_EAR3 MPU_EAR_REG(MPU,3)
+#define MPU_EDR3 MPU_EDR_REG(MPU,3)
+#define MPU_EAR4 MPU_EAR_REG(MPU,4)
+#define MPU_EDR4 MPU_EDR_REG(MPU,4)
+#define MPU_RGD0_WORD0 MPU_WORD_REG(MPU,0,0)
+#define MPU_RGD0_WORD1 MPU_WORD_REG(MPU,0,1)
+#define MPU_RGD0_WORD2 MPU_WORD_REG(MPU,0,2)
+#define MPU_RGD0_WORD3 MPU_WORD_REG(MPU,0,3)
+#define MPU_RGD1_WORD0 MPU_WORD_REG(MPU,1,0)
+#define MPU_RGD1_WORD1 MPU_WORD_REG(MPU,1,1)
+#define MPU_RGD1_WORD2 MPU_WORD_REG(MPU,1,2)
+#define MPU_RGD1_WORD3 MPU_WORD_REG(MPU,1,3)
+#define MPU_RGD2_WORD0 MPU_WORD_REG(MPU,2,0)
+#define MPU_RGD2_WORD1 MPU_WORD_REG(MPU,2,1)
+#define MPU_RGD2_WORD2 MPU_WORD_REG(MPU,2,2)
+#define MPU_RGD2_WORD3 MPU_WORD_REG(MPU,2,3)
+#define MPU_RGD3_WORD0 MPU_WORD_REG(MPU,3,0)
+#define MPU_RGD3_WORD1 MPU_WORD_REG(MPU,3,1)
+#define MPU_RGD3_WORD2 MPU_WORD_REG(MPU,3,2)
+#define MPU_RGD3_WORD3 MPU_WORD_REG(MPU,3,3)
+#define MPU_RGD4_WORD0 MPU_WORD_REG(MPU,4,0)
+#define MPU_RGD4_WORD1 MPU_WORD_REG(MPU,4,1)
+#define MPU_RGD4_WORD2 MPU_WORD_REG(MPU,4,2)
+#define MPU_RGD4_WORD3 MPU_WORD_REG(MPU,4,3)
+#define MPU_RGD5_WORD0 MPU_WORD_REG(MPU,5,0)
+#define MPU_RGD5_WORD1 MPU_WORD_REG(MPU,5,1)
+#define MPU_RGD5_WORD2 MPU_WORD_REG(MPU,5,2)
+#define MPU_RGD5_WORD3 MPU_WORD_REG(MPU,5,3)
+#define MPU_RGD6_WORD0 MPU_WORD_REG(MPU,6,0)
+#define MPU_RGD6_WORD1 MPU_WORD_REG(MPU,6,1)
+#define MPU_RGD6_WORD2 MPU_WORD_REG(MPU,6,2)
+#define MPU_RGD6_WORD3 MPU_WORD_REG(MPU,6,3)
+#define MPU_RGD7_WORD0 MPU_WORD_REG(MPU,7,0)
+#define MPU_RGD7_WORD1 MPU_WORD_REG(MPU,7,1)
+#define MPU_RGD7_WORD2 MPU_WORD_REG(MPU,7,2)
+#define MPU_RGD7_WORD3 MPU_WORD_REG(MPU,7,3)
+#define MPU_RGD8_WORD0 MPU_WORD_REG(MPU,8,0)
+#define MPU_RGD8_WORD1 MPU_WORD_REG(MPU,8,1)
+#define MPU_RGD8_WORD2 MPU_WORD_REG(MPU,8,2)
+#define MPU_RGD8_WORD3 MPU_WORD_REG(MPU,8,3)
+#define MPU_RGD9_WORD0 MPU_WORD_REG(MPU,9,0)
+#define MPU_RGD9_WORD1 MPU_WORD_REG(MPU,9,1)
+#define MPU_RGD9_WORD2 MPU_WORD_REG(MPU,9,2)
+#define MPU_RGD9_WORD3 MPU_WORD_REG(MPU,9,3)
+#define MPU_RGD10_WORD0 MPU_WORD_REG(MPU,10,0)
+#define MPU_RGD10_WORD1 MPU_WORD_REG(MPU,10,1)
+#define MPU_RGD10_WORD2 MPU_WORD_REG(MPU,10,2)
+#define MPU_RGD10_WORD3 MPU_WORD_REG(MPU,10,3)
+#define MPU_RGD11_WORD0 MPU_WORD_REG(MPU,11,0)
+#define MPU_RGD11_WORD1 MPU_WORD_REG(MPU,11,1)
+#define MPU_RGD11_WORD2 MPU_WORD_REG(MPU,11,2)
+#define MPU_RGD11_WORD3 MPU_WORD_REG(MPU,11,3)
+#define MPU_RGDAAC0 MPU_RGDAAC_REG(MPU,0)
+#define MPU_RGDAAC1 MPU_RGDAAC_REG(MPU,1)
+#define MPU_RGDAAC2 MPU_RGDAAC_REG(MPU,2)
+#define MPU_RGDAAC3 MPU_RGDAAC_REG(MPU,3)
+#define MPU_RGDAAC4 MPU_RGDAAC_REG(MPU,4)
+#define MPU_RGDAAC5 MPU_RGDAAC_REG(MPU,5)
+#define MPU_RGDAAC6 MPU_RGDAAC_REG(MPU,6)
+#define MPU_RGDAAC7 MPU_RGDAAC_REG(MPU,7)
+#define MPU_RGDAAC8 MPU_RGDAAC_REG(MPU,8)
+#define MPU_RGDAAC9 MPU_RGDAAC_REG(MPU,9)
+#define MPU_RGDAAC10 MPU_RGDAAC_REG(MPU,10)
+#define MPU_RGDAAC11 MPU_RGDAAC_REG(MPU,11)
+
+/* MPU - Register array accessors */
+#define MPU_EAR(index) MPU_EAR_REG(MPU,index)
+#define MPU_EDR(index) MPU_EDR_REG(MPU,index)
+#define MPU_WORD(index,index2) MPU_WORD_REG(MPU,index,index2)
+#define MPU_RGDAAC(index) MPU_RGDAAC_REG(MPU,index)
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MPU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- NV Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+ __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
+ __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
+ __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
+ __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
+ __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
+ __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
+ __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
+ __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
+ __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+ __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+ __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+ __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+ __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
+ __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
+ __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
+ __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
+} NV_Type, *NV_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- NV - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
+ * @{
+ */
+
+
+/* NV - Register accessors */
+#define NV_BACKKEY3_REG(base) ((base)->BACKKEY3)
+#define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
+#define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
+#define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
+#define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
+#define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
+#define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
+#define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
+#define NV_FPROT3_REG(base) ((base)->FPROT3)
+#define NV_FPROT2_REG(base) ((base)->FPROT2)
+#define NV_FPROT1_REG(base) ((base)->FPROT1)
+#define NV_FPROT0_REG(base) ((base)->FPROT0)
+#define NV_FSEC_REG(base) ((base)->FSEC)
+#define NV_FOPT_REG(base) ((base)->FOPT)
+#define NV_FEPROT_REG(base) ((base)->FEPROT)
+#define NV_FDPROT_REG(base) ((base)->FDPROT)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- NV Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK 0xFFu
+#define NV_BACKKEY3_KEY_SHIFT 0
+#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
+/* BACKKEY2 Bit Fields */
+#define NV_BACKKEY2_KEY_MASK 0xFFu
+#define NV_BACKKEY2_KEY_SHIFT 0
+#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
+/* BACKKEY1 Bit Fields */
+#define NV_BACKKEY1_KEY_MASK 0xFFu
+#define NV_BACKKEY1_KEY_SHIFT 0
+#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
+/* BACKKEY0 Bit Fields */
+#define NV_BACKKEY0_KEY_MASK 0xFFu
+#define NV_BACKKEY0_KEY_SHIFT 0
+#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
+/* BACKKEY7 Bit Fields */
+#define NV_BACKKEY7_KEY_MASK 0xFFu
+#define NV_BACKKEY7_KEY_SHIFT 0
+#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
+/* BACKKEY6 Bit Fields */
+#define NV_BACKKEY6_KEY_MASK 0xFFu
+#define NV_BACKKEY6_KEY_SHIFT 0
+#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
+/* BACKKEY5 Bit Fields */
+#define NV_BACKKEY5_KEY_MASK 0xFFu
+#define NV_BACKKEY5_KEY_SHIFT 0
+#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
+/* BACKKEY4 Bit Fields */
+#define NV_BACKKEY4_KEY_MASK 0xFFu
+#define NV_BACKKEY4_KEY_SHIFT 0
+#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
+/* FPROT3 Bit Fields */
+#define NV_FPROT3_PROT_MASK 0xFFu
+#define NV_FPROT3_PROT_SHIFT 0
+#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define NV_FPROT2_PROT_MASK 0xFFu
+#define NV_FPROT2_PROT_SHIFT 0
+#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define NV_FPROT1_PROT_MASK 0xFFu
+#define NV_FPROT1_PROT_SHIFT 0
+#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define NV_FPROT0_PROT_MASK 0xFFu
+#define NV_FPROT0_PROT_SHIFT 0
+#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
+/* FSEC Bit Fields */
+#define NV_FSEC_SEC_MASK 0x3u
+#define NV_FSEC_SEC_SHIFT 0
+#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK 0xCu
+#define NV_FSEC_FSLACC_SHIFT 2
+#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK 0x30u
+#define NV_FSEC_MEEN_SHIFT 4
+#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK 0xC0u
+#define NV_FSEC_KEYEN_SHIFT 6
+#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define NV_FOPT_LPBOOT_MASK 0x1u
+#define NV_FOPT_LPBOOT_SHIFT 0
+#define NV_FOPT_EZPORT_DIS_MASK 0x2u
+#define NV_FOPT_EZPORT_DIS_SHIFT 1
+/* FEPROT Bit Fields */
+#define NV_FEPROT_EPROT_MASK 0xFFu
+#define NV_FEPROT_EPROT_SHIFT 0
+#define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
+/* FDPROT Bit Fields */
+#define NV_FDPROT_DPROT_MASK 0xFFu
+#define NV_FDPROT_DPROT_SHIFT 0
+#define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFE_FlashConfig base address */
+#define FTFE_FlashConfig_BASE (0x400u)
+/** Peripheral FTFE_FlashConfig base pointer */
+#define FTFE_FlashConfig ((NV_Type *)FTFE_FlashConfig_BASE)
+#define FTFE_FlashConfig_BASE_PTR (FTFE_FlashConfig)
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASES { FTFE_FlashConfig }
+
+/* ----------------------------------------------------------------------------
+ -- NV - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
+ * @{
+ */
+
+
+/* NV - Register instance definitions */
+/* FTFE_FlashConfig */
+#define NV_BACKKEY3 NV_BACKKEY3_REG(FTFE_FlashConfig)
+#define NV_BACKKEY2 NV_BACKKEY2_REG(FTFE_FlashConfig)
+#define NV_BACKKEY1 NV_BACKKEY1_REG(FTFE_FlashConfig)
+#define NV_BACKKEY0 NV_BACKKEY0_REG(FTFE_FlashConfig)
+#define NV_BACKKEY7 NV_BACKKEY7_REG(FTFE_FlashConfig)
+#define NV_BACKKEY6 NV_BACKKEY6_REG(FTFE_FlashConfig)
+#define NV_BACKKEY5 NV_BACKKEY5_REG(FTFE_FlashConfig)
+#define NV_BACKKEY4 NV_BACKKEY4_REG(FTFE_FlashConfig)
+#define NV_FPROT3 NV_FPROT3_REG(FTFE_FlashConfig)
+#define NV_FPROT2 NV_FPROT2_REG(FTFE_FlashConfig)
+#define NV_FPROT1 NV_FPROT1_REG(FTFE_FlashConfig)
+#define NV_FPROT0 NV_FPROT0_REG(FTFE_FlashConfig)
+#define NV_FSEC NV_FSEC_REG(FTFE_FlashConfig)
+#define NV_FOPT NV_FOPT_REG(FTFE_FlashConfig)
+#define NV_FEPROT NV_FEPROT_REG(FTFE_FlashConfig)
+#define NV_FDPROT NV_FDPROT_REG(FTFE_FlashConfig)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- OSC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
+} OSC_Type, *OSC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- OSC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
+ * @{
+ */
+
+
+/* OSC - Register accessors */
+#define OSC_CR_REG(base) ((base)->CR)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- OSC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define OSC_CR_SC16P_MASK 0x1u
+#define OSC_CR_SC16P_SHIFT 0
+#define OSC_CR_SC8P_MASK 0x2u
+#define OSC_CR_SC8P_SHIFT 1
+#define OSC_CR_SC4P_MASK 0x4u
+#define OSC_CR_SC4P_SHIFT 2
+#define OSC_CR_SC2P_MASK 0x8u
+#define OSC_CR_SC2P_SHIFT 3
+#define OSC_CR_EREFSTEN_MASK 0x20u
+#define OSC_CR_EREFSTEN_SHIFT 5
+#define OSC_CR_ERCLKEN_MASK 0x80u
+#define OSC_CR_ERCLKEN_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC base address */
+#define OSC_BASE (0x40065000u)
+/** Peripheral OSC base pointer */
+#define OSC ((OSC_Type *)OSC_BASE)
+#define OSC_BASE_PTR (OSC)
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASES { OSC }
+
+/* ----------------------------------------------------------------------------
+ -- OSC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
+ * @{
+ */
+
+
+/* OSC - Register instance definitions */
+/* OSC */
+#define OSC_CR OSC_CR_REG(OSC)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PDB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
+ * @{
+ */
+
+/** PDB - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
+ __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
+ __I uint32_t CNT; /**< Counter register, offset: 0x8 */
+ __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
+ struct { /* offset: 0x10, array step: 0x28 */
+ __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
+ __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
+ __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
+ uint8_t RESERVED_0[24];
+ } CH[2];
+ uint8_t RESERVED_0[240];
+ struct { /* offset: 0x150, array step: 0x8 */
+ __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
+ __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
+ } DAC[2];
+ uint8_t RESERVED_1[48];
+ __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
+ __IO uint32_t PODLY[3]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
+} PDB_Type, *PDB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- PDB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
+ * @{
+ */
+
+
+/* PDB - Register accessors */
+#define PDB_SC_REG(base) ((base)->SC)
+#define PDB_MOD_REG(base) ((base)->MOD)
+#define PDB_CNT_REG(base) ((base)->CNT)
+#define PDB_IDLY_REG(base) ((base)->IDLY)
+#define PDB_C1_REG(base,index) ((base)->CH[index].C1)
+#define PDB_S_REG(base,index) ((base)->CH[index].S)
+#define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2])
+#define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC)
+#define PDB_INT_REG(base,index) ((base)->DAC[index].INT)
+#define PDB_POEN_REG(base) ((base)->POEN)
+#define PDB_PODLY_REG(base,index) ((base)->PODLY[index])
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- PDB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Masks PDB Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define PDB_SC_LDOK_MASK 0x1u
+#define PDB_SC_LDOK_SHIFT 0
+#define PDB_SC_CONT_MASK 0x2u
+#define PDB_SC_CONT_SHIFT 1
+#define PDB_SC_MULT_MASK 0xCu
+#define PDB_SC_MULT_SHIFT 2
+#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
+#define PDB_SC_PDBIE_MASK 0x20u
+#define PDB_SC_PDBIE_SHIFT 5
+#define PDB_SC_PDBIF_MASK 0x40u
+#define PDB_SC_PDBIF_SHIFT 6
+#define PDB_SC_PDBEN_MASK 0x80u
+#define PDB_SC_PDBEN_SHIFT 7
+#define PDB_SC_TRGSEL_MASK 0xF00u
+#define PDB_SC_TRGSEL_SHIFT 8
+#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
+#define PDB_SC_PRESCALER_MASK 0x7000u
+#define PDB_SC_PRESCALER_SHIFT 12
+#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
+#define PDB_SC_DMAEN_MASK 0x8000u
+#define PDB_SC_DMAEN_SHIFT 15
+#define PDB_SC_SWTRIG_MASK 0x10000u
+#define PDB_SC_SWTRIG_SHIFT 16
+#define PDB_SC_PDBEIE_MASK 0x20000u
+#define PDB_SC_PDBEIE_SHIFT 17
+#define PDB_SC_LDMOD_MASK 0xC0000u
+#define PDB_SC_LDMOD_SHIFT 18
+#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
+/* MOD Bit Fields */
+#define PDB_MOD_MOD_MASK 0xFFFFu
+#define PDB_MOD_MOD_SHIFT 0
+#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
+/* CNT Bit Fields */
+#define PDB_CNT_CNT_MASK 0xFFFFu
+#define PDB_CNT_CNT_SHIFT 0
+#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
+/* IDLY Bit Fields */
+#define PDB_IDLY_IDLY_MASK 0xFFFFu
+#define PDB_IDLY_IDLY_SHIFT 0
+#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
+/* C1 Bit Fields */
+#define PDB_C1_EN_MASK 0xFFu
+#define PDB_C1_EN_SHIFT 0
+#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
+#define PDB_C1_TOS_MASK 0xFF00u
+#define PDB_C1_TOS_SHIFT 8
+#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
+#define PDB_C1_BB_MASK 0xFF0000u
+#define PDB_C1_BB_SHIFT 16
+#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
+/* S Bit Fields */
+#define PDB_S_ERR_MASK 0xFFu
+#define PDB_S_ERR_SHIFT 0
+#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
+#define PDB_S_CF_MASK 0xFF0000u
+#define PDB_S_CF_SHIFT 16
+#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
+/* DLY Bit Fields */
+#define PDB_DLY_DLY_MASK 0xFFFFu
+#define PDB_DLY_DLY_SHIFT 0
+#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
+/* INTC Bit Fields */
+#define PDB_INTC_TOE_MASK 0x1u
+#define PDB_INTC_TOE_SHIFT 0
+#define PDB_INTC_EXT_MASK 0x2u
+#define PDB_INTC_EXT_SHIFT 1
+/* INT Bit Fields */
+#define PDB_INT_INT_MASK 0xFFFFu
+#define PDB_INT_INT_SHIFT 0
+#define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
+/* POEN Bit Fields */
+#define PDB_POEN_POEN_MASK 0xFFu
+#define PDB_POEN_POEN_SHIFT 0
+#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
+/* PODLY Bit Fields */
+#define PDB_PODLY_DLY2_MASK 0xFFFFu
+#define PDB_PODLY_DLY2_SHIFT 0
+#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
+#define PDB_PODLY_DLY1_MASK 0xFFFF0000u
+#define PDB_PODLY_DLY1_SHIFT 16
+#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Masks */
+
+
+/* PDB - Peripheral instance base addresses */
+/** Peripheral PDB0 base address */
+#define PDB0_BASE (0x40036000u)
+/** Peripheral PDB0 base pointer */
+#define PDB0 ((PDB_Type *)PDB0_BASE)
+#define PDB0_BASE_PTR (PDB0)
+/** Array initializer of PDB peripheral base pointers */
+#define PDB_BASES { PDB0 }
+
+/* ----------------------------------------------------------------------------
+ -- PDB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
+ * @{
+ */
+
+
+/* PDB - Register instance definitions */
+/* PDB0 */
+#define PDB0_SC PDB_SC_REG(PDB0)
+#define PDB0_MOD PDB_MOD_REG(PDB0)
+#define PDB0_CNT PDB_CNT_REG(PDB0)
+#define PDB0_IDLY PDB_IDLY_REG(PDB0)
+#define PDB0_CH0C1 PDB_C1_REG(PDB0,0)
+#define PDB0_CH0S PDB_S_REG(PDB0,0)
+#define PDB0_CH0DLY0 PDB_DLY_REG(PDB0,0,0)
+#define PDB0_CH0DLY1 PDB_DLY_REG(PDB0,0,1)
+#define PDB0_CH1C1 PDB_C1_REG(PDB0,1)
+#define PDB0_CH1S PDB_S_REG(PDB0,1)
+#define PDB0_CH1DLY0 PDB_DLY_REG(PDB0,1,0)
+#define PDB0_CH1DLY1 PDB_DLY_REG(PDB0,1,1)
+#define PDB0_DACINTC0 PDB_INTC_REG(PDB0,0)
+#define PDB0_DACINT0 PDB_INT_REG(PDB0,0)
+#define PDB0_DACINTC1 PDB_INTC_REG(PDB0,1)
+#define PDB0_DACINT1 PDB_INT_REG(PDB0,1)
+#define PDB0_POEN PDB_POEN_REG(PDB0)
+#define PDB0_PO0DLY PDB_PODLY_REG(PDB0,0)
+#define PDB0_PO1DLY PDB_PODLY_REG(PDB0,1)
+#define PDB0_PO2DLY PDB_PODLY_REG(PDB0,2)
+
+/* PDB - Register array accessors */
+#define PDB0_C1(index) PDB_C1_REG(PDB0,index)
+#define PDB0_S(index) PDB_S_REG(PDB0,index)
+#define PDB0_DLY(index,index2) PDB_DLY_REG(PDB0,index,index2)
+#define PDB0_INTC(index) PDB_INTC_REG(PDB0,index)
+#define PDB0_INT(index) PDB_INT_REG(PDB0,index)
+#define PDB0_PODLY(index) PDB_PODLY_REG(PDB0,index)
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PDB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PIT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[252];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+ __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+ __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+ __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+ } CHANNEL[4];
+} PIT_Type, *PIT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- PIT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @{
+ */
+
+
+/* PIT - Register accessors */
+#define PIT_MCR_REG(base) ((base)->MCR)
+#define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL)
+#define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
+#define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
+#define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- PIT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK 0x1u
+#define PIT_MCR_FRZ_SHIFT 0
+#define PIT_MCR_MDIS_MASK 0x2u
+#define PIT_MCR_MDIS_SHIFT 1
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT 0
+#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
+/* CVAL Bit Fields */
+#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
+#define PIT_CVAL_TVL_SHIFT 0
+#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
+/* TCTRL Bit Fields */
+#define PIT_TCTRL_TEN_MASK 0x1u
+#define PIT_TCTRL_TEN_SHIFT 0
+#define PIT_TCTRL_TIE_MASK 0x2u
+#define PIT_TCTRL_TIE_SHIFT 1
+#define PIT_TCTRL_CHN_MASK 0x4u
+#define PIT_TCTRL_CHN_SHIFT 2
+/* TFLG Bit Fields */
+#define PIT_TFLG_TIF_MASK 0x1u
+#define PIT_TFLG_TIF_SHIFT 0
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT ((PIT_Type *)PIT_BASE)
+#define PIT_BASE_PTR (PIT)
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASES { PIT }
+
+/* ----------------------------------------------------------------------------
+ -- PIT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @{
+ */
+
+
+/* PIT - Register instance definitions */
+/* PIT */
+#define PIT_MCR PIT_MCR_REG(PIT)
+#define PIT_LDVAL0 PIT_LDVAL_REG(PIT,0)
+#define PIT_CVAL0 PIT_CVAL_REG(PIT,0)
+#define PIT_TCTRL0 PIT_TCTRL_REG(PIT,0)
+#define PIT_TFLG0 PIT_TFLG_REG(PIT,0)
+#define PIT_LDVAL1 PIT_LDVAL_REG(PIT,1)
+#define PIT_CVAL1 PIT_CVAL_REG(PIT,1)
+#define PIT_TCTRL1 PIT_TCTRL_REG(PIT,1)
+#define PIT_TFLG1 PIT_TFLG_REG(PIT,1)
+#define PIT_LDVAL2 PIT_LDVAL_REG(PIT,2)
+#define PIT_CVAL2 PIT_CVAL_REG(PIT,2)
+#define PIT_TCTRL2 PIT_TCTRL_REG(PIT,2)
+#define PIT_TFLG2 PIT_TFLG_REG(PIT,2)
+#define PIT_LDVAL3 PIT_LDVAL_REG(PIT,3)
+#define PIT_CVAL3 PIT_CVAL_REG(PIT,3)
+#define PIT_TCTRL3 PIT_TCTRL_REG(PIT,3)
+#define PIT_TFLG3 PIT_TFLG_REG(PIT,3)
+
+/* PIT - Register array accessors */
+#define PIT_LDVAL(index) PIT_LDVAL_REG(PIT,index)
+#define PIT_CVAL(index) PIT_CVAL_REG(PIT,index)
+#define PIT_TCTRL(index) PIT_TCTRL_REG(PIT,index)
+#define PIT_TFLG(index) PIT_TFLG_REG(PIT,index)
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
+ __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
+ __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
+} PMC_Type, *PMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- PMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
+ * @{
+ */
+
+
+/* PMC - Register accessors */
+#define PMC_LVDSC1_REG(base) ((base)->LVDSC1)
+#define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
+#define PMC_REGSC_REG(base) ((base)->REGSC)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/* LVDSC1 Bit Fields */
+#define PMC_LVDSC1_LVDV_MASK 0x3u
+#define PMC_LVDSC1_LVDV_SHIFT 0
+#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK 0x10u
+#define PMC_LVDSC1_LVDRE_SHIFT 4
+#define PMC_LVDSC1_LVDIE_MASK 0x20u
+#define PMC_LVDSC1_LVDIE_SHIFT 5
+#define PMC_LVDSC1_LVDACK_MASK 0x40u
+#define PMC_LVDSC1_LVDACK_SHIFT 6
+#define PMC_LVDSC1_LVDF_MASK 0x80u
+#define PMC_LVDSC1_LVDF_SHIFT 7
+/* LVDSC2 Bit Fields */
+#define PMC_LVDSC2_LVWV_MASK 0x3u
+#define PMC_LVDSC2_LVWV_SHIFT 0
+#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK 0x20u
+#define PMC_LVDSC2_LVWIE_SHIFT 5
+#define PMC_LVDSC2_LVWACK_MASK 0x40u
+#define PMC_LVDSC2_LVWACK_SHIFT 6
+#define PMC_LVDSC2_LVWF_MASK 0x80u
+#define PMC_LVDSC2_LVWF_SHIFT 7
+/* REGSC Bit Fields */
+#define PMC_REGSC_BGBE_MASK 0x1u
+#define PMC_REGSC_BGBE_SHIFT 0
+#define PMC_REGSC_REGONS_MASK 0x4u
+#define PMC_REGSC_REGONS_SHIFT 2
+#define PMC_REGSC_ACKISO_MASK 0x8u
+#define PMC_REGSC_ACKISO_SHIFT 3
+#define PMC_REGSC_BGEN_MASK 0x10u
+#define PMC_REGSC_BGEN_SHIFT 4
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC ((PMC_Type *)PMC_BASE)
+#define PMC_BASE_PTR (PMC)
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASES { PMC }
+
+/* ----------------------------------------------------------------------------
+ -- PMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
+ * @{
+ */
+
+
+/* PMC - Register instance definitions */
+/* PMC */
+#define PMC_LVDSC1 PMC_LVDSC1_REG(PMC)
+#define PMC_LVDSC2 PMC_LVDSC2_REG(PMC)
+#define PMC_REGSC PMC_REGSC_REG(PMC)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PORT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+ __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
+ __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
+ uint8_t RESERVED_0[24];
+ __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
+ uint8_t RESERVED_1[28];
+ __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
+ __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
+ __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
+} PORT_Type, *PORT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- PORT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
+ * @{
+ */
+
+
+/* PORT - Register accessors */
+#define PORT_PCR_REG(base,index) ((base)->PCR[index])
+#define PORT_GPCLR_REG(base) ((base)->GPCLR)
+#define PORT_GPCHR_REG(base) ((base)->GPCHR)
+#define PORT_ISFR_REG(base) ((base)->ISFR)
+#define PORT_DFER_REG(base) ((base)->DFER)
+#define PORT_DFCR_REG(base) ((base)->DFCR)
+#define PORT_DFWR_REG(base) ((base)->DFWR)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- PORT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/* PCR Bit Fields */
+#define PORT_PCR_PS_MASK 0x1u
+#define PORT_PCR_PS_SHIFT 0
+#define PORT_PCR_PE_MASK 0x2u
+#define PORT_PCR_PE_SHIFT 1
+#define PORT_PCR_SRE_MASK 0x4u
+#define PORT_PCR_SRE_SHIFT 2
+#define PORT_PCR_PFE_MASK 0x10u
+#define PORT_PCR_PFE_SHIFT 4
+#define PORT_PCR_ODE_MASK 0x20u
+#define PORT_PCR_ODE_SHIFT 5
+#define PORT_PCR_DSE_MASK 0x40u
+#define PORT_PCR_DSE_SHIFT 6
+#define PORT_PCR_MUX_MASK 0x700u
+#define PORT_PCR_MUX_SHIFT 8
+#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
+#define PORT_PCR_LK_MASK 0x8000u
+#define PORT_PCR_LK_SHIFT 15
+#define PORT_PCR_IRQC_MASK 0xF0000u
+#define PORT_PCR_IRQC_SHIFT 16
+#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK 0x1000000u
+#define PORT_PCR_ISF_SHIFT 24
+/* GPCLR Bit Fields */
+#define PORT_GPCLR_GPWD_MASK 0xFFFFu
+#define PORT_GPCLR_GPWD_SHIFT 0
+#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCLR_GPWE_SHIFT 16
+#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
+/* GPCHR Bit Fields */
+#define PORT_GPCHR_GPWD_MASK 0xFFFFu
+#define PORT_GPCHR_GPWD_SHIFT 0
+#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCHR_GPWE_SHIFT 16
+#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
+/* ISFR Bit Fields */
+#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
+#define PORT_ISFR_ISF_SHIFT 0
+#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
+/* DFER Bit Fields */
+#define PORT_DFER_DFE_MASK 0xFFFFFFFFu
+#define PORT_DFER_DFE_SHIFT 0
+#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
+/* DFCR Bit Fields */
+#define PORT_DFCR_CS_MASK 0x1u
+#define PORT_DFCR_CS_SHIFT 0
+/* DFWR Bit Fields */
+#define PORT_DFWR_FILT_MASK 0x1Fu
+#define PORT_DFWR_FILT_SHIFT 0
+#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA ((PORT_Type *)PORTA_BASE)
+#define PORTA_BASE_PTR (PORTA)
+/** Peripheral PORTB base address */
+#define PORTB_BASE (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB ((PORT_Type *)PORTB_BASE)
+#define PORTB_BASE_PTR (PORTB)
+/** Peripheral PORTC base address */
+#define PORTC_BASE (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC ((PORT_Type *)PORTC_BASE)
+#define PORTC_BASE_PTR (PORTC)
+/** Peripheral PORTD base address */
+#define PORTD_BASE (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD ((PORT_Type *)PORTD_BASE)
+#define PORTD_BASE_PTR (PORTD)
+/** Peripheral PORTE base address */
+#define PORTE_BASE (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE ((PORT_Type *)PORTE_BASE)
+#define PORTE_BASE_PTR (PORTE)
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
+
+/* ----------------------------------------------------------------------------
+ -- PORT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
+ * @{
+ */
+
+
+/* PORT - Register instance definitions */
+/* PORTA */
+#define PORTA_PCR0 PORT_PCR_REG(PORTA,0)
+#define PORTA_PCR1 PORT_PCR_REG(PORTA,1)
+#define PORTA_PCR2 PORT_PCR_REG(PORTA,2)
+#define PORTA_PCR3 PORT_PCR_REG(PORTA,3)
+#define PORTA_PCR4 PORT_PCR_REG(PORTA,4)
+#define PORTA_PCR5 PORT_PCR_REG(PORTA,5)
+#define PORTA_PCR6 PORT_PCR_REG(PORTA,6)
+#define PORTA_PCR7 PORT_PCR_REG(PORTA,7)
+#define PORTA_PCR8 PORT_PCR_REG(PORTA,8)
+#define PORTA_PCR9 PORT_PCR_REG(PORTA,9)
+#define PORTA_PCR10 PORT_PCR_REG(PORTA,10)
+#define PORTA_PCR11 PORT_PCR_REG(PORTA,11)
+#define PORTA_PCR12 PORT_PCR_REG(PORTA,12)
+#define PORTA_PCR13 PORT_PCR_REG(PORTA,13)
+#define PORTA_PCR14 PORT_PCR_REG(PORTA,14)
+#define PORTA_PCR15 PORT_PCR_REG(PORTA,15)
+#define PORTA_PCR16 PORT_PCR_REG(PORTA,16)
+#define PORTA_PCR17 PORT_PCR_REG(PORTA,17)
+#define PORTA_PCR18 PORT_PCR_REG(PORTA,18)
+#define PORTA_PCR19 PORT_PCR_REG(PORTA,19)
+#define PORTA_PCR20 PORT_PCR_REG(PORTA,20)
+#define PORTA_PCR21 PORT_PCR_REG(PORTA,21)
+#define PORTA_PCR22 PORT_PCR_REG(PORTA,22)
+#define PORTA_PCR23 PORT_PCR_REG(PORTA,23)
+#define PORTA_PCR24 PORT_PCR_REG(PORTA,24)
+#define PORTA_PCR25 PORT_PCR_REG(PORTA,25)
+#define PORTA_PCR26 PORT_PCR_REG(PORTA,26)
+#define PORTA_PCR27 PORT_PCR_REG(PORTA,27)
+#define PORTA_PCR28 PORT_PCR_REG(PORTA,28)
+#define PORTA_PCR29 PORT_PCR_REG(PORTA,29)
+#define PORTA_PCR30 PORT_PCR_REG(PORTA,30)
+#define PORTA_PCR31 PORT_PCR_REG(PORTA,31)
+#define PORTA_GPCLR PORT_GPCLR_REG(PORTA)
+#define PORTA_GPCHR PORT_GPCHR_REG(PORTA)
+#define PORTA_ISFR PORT_ISFR_REG(PORTA)
+/* PORTB */
+#define PORTB_PCR0 PORT_PCR_REG(PORTB,0)
+#define PORTB_PCR1 PORT_PCR_REG(PORTB,1)
+#define PORTB_PCR2 PORT_PCR_REG(PORTB,2)
+#define PORTB_PCR3 PORT_PCR_REG(PORTB,3)
+#define PORTB_PCR4 PORT_PCR_REG(PORTB,4)
+#define PORTB_PCR5 PORT_PCR_REG(PORTB,5)
+#define PORTB_PCR6 PORT_PCR_REG(PORTB,6)
+#define PORTB_PCR7 PORT_PCR_REG(PORTB,7)
+#define PORTB_PCR8 PORT_PCR_REG(PORTB,8)
+#define PORTB_PCR9 PORT_PCR_REG(PORTB,9)
+#define PORTB_PCR10 PORT_PCR_REG(PORTB,10)
+#define PORTB_PCR11 PORT_PCR_REG(PORTB,11)
+#define PORTB_PCR12 PORT_PCR_REG(PORTB,12)
+#define PORTB_PCR13 PORT_PCR_REG(PORTB,13)
+#define PORTB_PCR14 PORT_PCR_REG(PORTB,14)
+#define PORTB_PCR15 PORT_PCR_REG(PORTB,15)
+#define PORTB_PCR16 PORT_PCR_REG(PORTB,16)
+#define PORTB_PCR17 PORT_PCR_REG(PORTB,17)
+#define PORTB_PCR18 PORT_PCR_REG(PORTB,18)
+#define PORTB_PCR19 PORT_PCR_REG(PORTB,19)
+#define PORTB_PCR20 PORT_PCR_REG(PORTB,20)
+#define PORTB_PCR21 PORT_PCR_REG(PORTB,21)
+#define PORTB_PCR22 PORT_PCR_REG(PORTB,22)
+#define PORTB_PCR23 PORT_PCR_REG(PORTB,23)
+#define PORTB_PCR24 PORT_PCR_REG(PORTB,24)
+#define PORTB_PCR25 PORT_PCR_REG(PORTB,25)
+#define PORTB_PCR26 PORT_PCR_REG(PORTB,26)
+#define PORTB_PCR27 PORT_PCR_REG(PORTB,27)
+#define PORTB_PCR28 PORT_PCR_REG(PORTB,28)
+#define PORTB_PCR29 PORT_PCR_REG(PORTB,29)
+#define PORTB_PCR30 PORT_PCR_REG(PORTB,30)
+#define PORTB_PCR31 PORT_PCR_REG(PORTB,31)
+#define PORTB_GPCLR PORT_GPCLR_REG(PORTB)
+#define PORTB_GPCHR PORT_GPCHR_REG(PORTB)
+#define PORTB_ISFR PORT_ISFR_REG(PORTB)
+/* PORTC */
+#define PORTC_PCR0 PORT_PCR_REG(PORTC,0)
+#define PORTC_PCR1 PORT_PCR_REG(PORTC,1)
+#define PORTC_PCR2 PORT_PCR_REG(PORTC,2)
+#define PORTC_PCR3 PORT_PCR_REG(PORTC,3)
+#define PORTC_PCR4 PORT_PCR_REG(PORTC,4)
+#define PORTC_PCR5 PORT_PCR_REG(PORTC,5)
+#define PORTC_PCR6 PORT_PCR_REG(PORTC,6)
+#define PORTC_PCR7 PORT_PCR_REG(PORTC,7)
+#define PORTC_PCR8 PORT_PCR_REG(PORTC,8)
+#define PORTC_PCR9 PORT_PCR_REG(PORTC,9)
+#define PORTC_PCR10 PORT_PCR_REG(PORTC,10)
+#define PORTC_PCR11 PORT_PCR_REG(PORTC,11)
+#define PORTC_PCR12 PORT_PCR_REG(PORTC,12)
+#define PORTC_PCR13 PORT_PCR_REG(PORTC,13)
+#define PORTC_PCR14 PORT_PCR_REG(PORTC,14)
+#define PORTC_PCR15 PORT_PCR_REG(PORTC,15)
+#define PORTC_PCR16 PORT_PCR_REG(PORTC,16)
+#define PORTC_PCR17 PORT_PCR_REG(PORTC,17)
+#define PORTC_PCR18 PORT_PCR_REG(PORTC,18)
+#define PORTC_PCR19 PORT_PCR_REG(PORTC,19)
+#define PORTC_PCR20 PORT_PCR_REG(PORTC,20)
+#define PORTC_PCR21 PORT_PCR_REG(PORTC,21)
+#define PORTC_PCR22 PORT_PCR_REG(PORTC,22)
+#define PORTC_PCR23 PORT_PCR_REG(PORTC,23)
+#define PORTC_PCR24 PORT_PCR_REG(PORTC,24)
+#define PORTC_PCR25 PORT_PCR_REG(PORTC,25)
+#define PORTC_PCR26 PORT_PCR_REG(PORTC,26)
+#define PORTC_PCR27 PORT_PCR_REG(PORTC,27)
+#define PORTC_PCR28 PORT_PCR_REG(PORTC,28)
+#define PORTC_PCR29 PORT_PCR_REG(PORTC,29)
+#define PORTC_PCR30 PORT_PCR_REG(PORTC,30)
+#define PORTC_PCR31 PORT_PCR_REG(PORTC,31)
+#define PORTC_GPCLR PORT_GPCLR_REG(PORTC)
+#define PORTC_GPCHR PORT_GPCHR_REG(PORTC)
+#define PORTC_ISFR PORT_ISFR_REG(PORTC)
+/* PORTD */
+#define PORTD_PCR0 PORT_PCR_REG(PORTD,0)
+#define PORTD_PCR1 PORT_PCR_REG(PORTD,1)
+#define PORTD_PCR2 PORT_PCR_REG(PORTD,2)
+#define PORTD_PCR3 PORT_PCR_REG(PORTD,3)
+#define PORTD_PCR4 PORT_PCR_REG(PORTD,4)
+#define PORTD_PCR5 PORT_PCR_REG(PORTD,5)
+#define PORTD_PCR6 PORT_PCR_REG(PORTD,6)
+#define PORTD_PCR7 PORT_PCR_REG(PORTD,7)
+#define PORTD_PCR8 PORT_PCR_REG(PORTD,8)
+#define PORTD_PCR9 PORT_PCR_REG(PORTD,9)
+#define PORTD_PCR10 PORT_PCR_REG(PORTD,10)
+#define PORTD_PCR11 PORT_PCR_REG(PORTD,11)
+#define PORTD_PCR12 PORT_PCR_REG(PORTD,12)
+#define PORTD_PCR13 PORT_PCR_REG(PORTD,13)
+#define PORTD_PCR14 PORT_PCR_REG(PORTD,14)
+#define PORTD_PCR15 PORT_PCR_REG(PORTD,15)
+#define PORTD_PCR16 PORT_PCR_REG(PORTD,16)
+#define PORTD_PCR17 PORT_PCR_REG(PORTD,17)
+#define PORTD_PCR18 PORT_PCR_REG(PORTD,18)
+#define PORTD_PCR19 PORT_PCR_REG(PORTD,19)
+#define PORTD_PCR20 PORT_PCR_REG(PORTD,20)
+#define PORTD_PCR21 PORT_PCR_REG(PORTD,21)
+#define PORTD_PCR22 PORT_PCR_REG(PORTD,22)
+#define PORTD_PCR23 PORT_PCR_REG(PORTD,23)
+#define PORTD_PCR24 PORT_PCR_REG(PORTD,24)
+#define PORTD_PCR25 PORT_PCR_REG(PORTD,25)
+#define PORTD_PCR26 PORT_PCR_REG(PORTD,26)
+#define PORTD_PCR27 PORT_PCR_REG(PORTD,27)
+#define PORTD_PCR28 PORT_PCR_REG(PORTD,28)
+#define PORTD_PCR29 PORT_PCR_REG(PORTD,29)
+#define PORTD_PCR30 PORT_PCR_REG(PORTD,30)
+#define PORTD_PCR31 PORT_PCR_REG(PORTD,31)
+#define PORTD_GPCLR PORT_GPCLR_REG(PORTD)
+#define PORTD_GPCHR PORT_GPCHR_REG(PORTD)
+#define PORTD_ISFR PORT_ISFR_REG(PORTD)
+#define PORTD_DFER PORT_DFER_REG(PORTD)
+#define PORTD_DFCR PORT_DFCR_REG(PORTD)
+#define PORTD_DFWR PORT_DFWR_REG(PORTD)
+/* PORTE */
+#define PORTE_PCR0 PORT_PCR_REG(PORTE,0)
+#define PORTE_PCR1 PORT_PCR_REG(PORTE,1)
+#define PORTE_PCR2 PORT_PCR_REG(PORTE,2)
+#define PORTE_PCR3 PORT_PCR_REG(PORTE,3)
+#define PORTE_PCR4 PORT_PCR_REG(PORTE,4)
+#define PORTE_PCR5 PORT_PCR_REG(PORTE,5)
+#define PORTE_PCR6 PORT_PCR_REG(PORTE,6)
+#define PORTE_PCR7 PORT_PCR_REG(PORTE,7)
+#define PORTE_PCR8 PORT_PCR_REG(PORTE,8)
+#define PORTE_PCR9 PORT_PCR_REG(PORTE,9)
+#define PORTE_PCR10 PORT_PCR_REG(PORTE,10)
+#define PORTE_PCR11 PORT_PCR_REG(PORTE,11)
+#define PORTE_PCR12 PORT_PCR_REG(PORTE,12)
+#define PORTE_PCR13 PORT_PCR_REG(PORTE,13)
+#define PORTE_PCR14 PORT_PCR_REG(PORTE,14)
+#define PORTE_PCR15 PORT_PCR_REG(PORTE,15)
+#define PORTE_PCR16 PORT_PCR_REG(PORTE,16)
+#define PORTE_PCR17 PORT_PCR_REG(PORTE,17)
+#define PORTE_PCR18 PORT_PCR_REG(PORTE,18)
+#define PORTE_PCR19 PORT_PCR_REG(PORTE,19)
+#define PORTE_PCR20 PORT_PCR_REG(PORTE,20)
+#define PORTE_PCR21 PORT_PCR_REG(PORTE,21)
+#define PORTE_PCR22 PORT_PCR_REG(PORTE,22)
+#define PORTE_PCR23 PORT_PCR_REG(PORTE,23)
+#define PORTE_PCR24 PORT_PCR_REG(PORTE,24)
+#define PORTE_PCR25 PORT_PCR_REG(PORTE,25)
+#define PORTE_PCR26 PORT_PCR_REG(PORTE,26)
+#define PORTE_PCR27 PORT_PCR_REG(PORTE,27)
+#define PORTE_PCR28 PORT_PCR_REG(PORTE,28)
+#define PORTE_PCR29 PORT_PCR_REG(PORTE,29)
+#define PORTE_PCR30 PORT_PCR_REG(PORTE,30)
+#define PORTE_PCR31 PORT_PCR_REG(PORTE,31)
+#define PORTE_GPCLR PORT_GPCLR_REG(PORTE)
+#define PORTE_GPCHR PORT_GPCHR_REG(PORTE)
+#define PORTE_ISFR PORT_ISFR_REG(PORTE)
+
+/* PORT - Register array accessors */
+#define PORTA_PCR(index) PORT_PCR_REG(PORTA,index)
+#define PORTB_PCR(index) PORT_PCR_REG(PORTB,index)
+#define PORTC_PCR(index) PORT_PCR_REG(PORTC,index)
+#define PORTD_PCR(index) PORT_PCR_REG(PORTD,index)
+#define PORTE_PCR(index) PORT_PCR_REG(PORTE,index)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+ __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
+ __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
+ __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
+ uint8_t RESERVED_1[1];
+ __I uint8_t MR; /**< Mode Register, offset: 0x7 */
+} RCM_Type, *RCM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- RCM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
+ * @{
+ */
+
+
+/* RCM - Register accessors */
+#define RCM_SRS0_REG(base) ((base)->SRS0)
+#define RCM_SRS1_REG(base) ((base)->SRS1)
+#define RCM_RPFC_REG(base) ((base)->RPFC)
+#define RCM_RPFW_REG(base) ((base)->RPFW)
+#define RCM_MR_REG(base) ((base)->MR)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/* SRS0 Bit Fields */
+#define RCM_SRS0_WAKEUP_MASK 0x1u
+#define RCM_SRS0_WAKEUP_SHIFT 0
+#define RCM_SRS0_LVD_MASK 0x2u
+#define RCM_SRS0_LVD_SHIFT 1
+#define RCM_SRS0_LOC_MASK 0x4u
+#define RCM_SRS0_LOC_SHIFT 2
+#define RCM_SRS0_LOL_MASK 0x8u
+#define RCM_SRS0_LOL_SHIFT 3
+#define RCM_SRS0_WDOG_MASK 0x20u
+#define RCM_SRS0_WDOG_SHIFT 5
+#define RCM_SRS0_PIN_MASK 0x40u
+#define RCM_SRS0_PIN_SHIFT 6
+#define RCM_SRS0_POR_MASK 0x80u
+#define RCM_SRS0_POR_SHIFT 7
+/* SRS1 Bit Fields */
+#define RCM_SRS1_JTAG_MASK 0x1u
+#define RCM_SRS1_JTAG_SHIFT 0
+#define RCM_SRS1_LOCKUP_MASK 0x2u
+#define RCM_SRS1_LOCKUP_SHIFT 1
+#define RCM_SRS1_SW_MASK 0x4u
+#define RCM_SRS1_SW_SHIFT 2
+#define RCM_SRS1_MDM_AP_MASK 0x8u
+#define RCM_SRS1_MDM_AP_SHIFT 3
+#define RCM_SRS1_EZPT_MASK 0x10u
+#define RCM_SRS1_EZPT_SHIFT 4
+#define RCM_SRS1_SACKERR_MASK 0x20u
+#define RCM_SRS1_SACKERR_SHIFT 5
+/* RPFC Bit Fields */
+#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
+#define RCM_RPFC_RSTFLTSRW_SHIFT 0
+#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK 0x4u
+#define RCM_RPFC_RSTFLTSS_SHIFT 2
+/* RPFW Bit Fields */
+#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
+#define RCM_RPFW_RSTFLTSEL_SHIFT 0
+#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
+/* MR Bit Fields */
+#define RCM_MR_EZP_MS_MASK 0x2u
+#define RCM_MR_EZP_MS_SHIFT 1
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM ((RCM_Type *)RCM_BASE)
+#define RCM_BASE_PTR (RCM)
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASES { RCM }
+
+/* ----------------------------------------------------------------------------
+ -- RCM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
+ * @{
+ */
+
+
+/* RCM - Register instance definitions */
+/* RCM */
+#define RCM_SRS0 RCM_SRS0_REG(RCM)
+#define RCM_SRS1 RCM_SRS1_REG(RCM)
+#define RCM_RPFC RCM_RPFC_REG(RCM)
+#define RCM_RPFW RCM_RPFW_REG(RCM)
+#define RCM_MR RCM_MR_REG(RCM)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
+ * @{
+ */
+
+/** RFSYS - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
+} RFSYS_Type, *RFSYS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
+ * @{
+ */
+
+
+/* RFSYS - Register accessors */
+#define RFSYS_REG_REG(base,index) ((base)->REG[index])
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFSYS_REG_LL_MASK 0xFFu
+#define RFSYS_REG_LL_SHIFT 0
+#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LH_MASK 0xFF00u
+#define RFSYS_REG_LH_SHIFT 8
+#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
+#define RFSYS_REG_HL_MASK 0xFF0000u
+#define RFSYS_REG_HL_SHIFT 16
+#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HH_MASK 0xFF000000u
+#define RFSYS_REG_HH_SHIFT 24
+#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Masks */
+
+
+/* RFSYS - Peripheral instance base addresses */
+/** Peripheral RFSYS base address */
+#define RFSYS_BASE (0x40041000u)
+/** Peripheral RFSYS base pointer */
+#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
+#define RFSYS_BASE_PTR (RFSYS)
+/** Array initializer of RFSYS peripheral base pointers */
+#define RFSYS_BASES { RFSYS }
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
+ * @{
+ */
+
+
+/* RFSYS - Register instance definitions */
+/* RFSYS */
+#define RFSYS_REG0 RFSYS_REG_REG(RFSYS,0)
+#define RFSYS_REG1 RFSYS_REG_REG(RFSYS,1)
+#define RFSYS_REG2 RFSYS_REG_REG(RFSYS,2)
+#define RFSYS_REG3 RFSYS_REG_REG(RFSYS,3)
+#define RFSYS_REG4 RFSYS_REG_REG(RFSYS,4)
+#define RFSYS_REG5 RFSYS_REG_REG(RFSYS,5)
+#define RFSYS_REG6 RFSYS_REG_REG(RFSYS,6)
+#define RFSYS_REG7 RFSYS_REG_REG(RFSYS,7)
+
+/* RFSYS - Register array accessors */
+#define RFSYS_REG(index) RFSYS_REG_REG(RFSYS,index)
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFVBAT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
+ * @{
+ */
+
+/** RFVBAT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
+} RFVBAT_Type, *RFVBAT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- RFVBAT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
+ * @{
+ */
+
+
+/* RFVBAT - Register accessors */
+#define RFVBAT_REG_REG(base,index) ((base)->REG[index])
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFVBAT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFVBAT_REG_LL_MASK 0xFFu
+#define RFVBAT_REG_LL_SHIFT 0
+#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
+#define RFVBAT_REG_LH_MASK 0xFF00u
+#define RFVBAT_REG_LH_SHIFT 8
+#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
+#define RFVBAT_REG_HL_MASK 0xFF0000u
+#define RFVBAT_REG_HL_SHIFT 16
+#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
+#define RFVBAT_REG_HH_MASK 0xFF000000u
+#define RFVBAT_REG_HH_SHIFT 24
+#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Masks */
+
+
+/* RFVBAT - Peripheral instance base addresses */
+/** Peripheral RFVBAT base address */
+#define RFVBAT_BASE (0x4003E000u)
+/** Peripheral RFVBAT base pointer */
+#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
+#define RFVBAT_BASE_PTR (RFVBAT)
+/** Array initializer of RFVBAT peripheral base pointers */
+#define RFVBAT_BASES { RFVBAT }
+
+/* ----------------------------------------------------------------------------
+ -- RFVBAT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
+ * @{
+ */
+
+
+/* RFVBAT - Register instance definitions */
+/* RFVBAT */
+#define RFVBAT_REG0 RFVBAT_REG_REG(RFVBAT,0)
+#define RFVBAT_REG1 RFVBAT_REG_REG(RFVBAT,1)
+#define RFVBAT_REG2 RFVBAT_REG_REG(RFVBAT,2)
+#define RFVBAT_REG3 RFVBAT_REG_REG(RFVBAT,3)
+#define RFVBAT_REG4 RFVBAT_REG_REG(RFVBAT,4)
+#define RFVBAT_REG5 RFVBAT_REG_REG(RFVBAT,5)
+#define RFVBAT_REG6 RFVBAT_REG_REG(RFVBAT,6)
+#define RFVBAT_REG7 RFVBAT_REG_REG(RFVBAT,7)
+
+/* RFVBAT - Register array accessors */
+#define RFVBAT_REG(index) RFVBAT_REG_REG(RFVBAT,index)
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RNG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
+ * @{
+ */
+
+/** RNG - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */
+ __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */
+ __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */
+ __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */
+} RNG_Type, *RNG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- RNG - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
+ * @{
+ */
+
+
+/* RNG - Register accessors */
+#define RNG_CR_REG(base) ((base)->CR)
+#define RNG_SR_REG(base) ((base)->SR)
+#define RNG_ER_REG(base) ((base)->ER)
+#define RNG_OR_REG(base) ((base)->OR)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RNG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Masks RNG Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define RNG_CR_GO_MASK 0x1u
+#define RNG_CR_GO_SHIFT 0
+#define RNG_CR_HA_MASK 0x2u
+#define RNG_CR_HA_SHIFT 1
+#define RNG_CR_INTM_MASK 0x4u
+#define RNG_CR_INTM_SHIFT 2
+#define RNG_CR_CLRI_MASK 0x8u
+#define RNG_CR_CLRI_SHIFT 3
+#define RNG_CR_SLP_MASK 0x10u
+#define RNG_CR_SLP_SHIFT 4
+/* SR Bit Fields */
+#define RNG_SR_SECV_MASK 0x1u
+#define RNG_SR_SECV_SHIFT 0
+#define RNG_SR_LRS_MASK 0x2u
+#define RNG_SR_LRS_SHIFT 1
+#define RNG_SR_ORU_MASK 0x4u
+#define RNG_SR_ORU_SHIFT 2
+#define RNG_SR_ERRI_MASK 0x8u
+#define RNG_SR_ERRI_SHIFT 3
+#define RNG_SR_SLP_MASK 0x10u
+#define RNG_SR_SLP_SHIFT 4
+#define RNG_SR_OREG_LVL_MASK 0xFF00u
+#define RNG_SR_OREG_LVL_SHIFT 8
+#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_LVL_SHIFT))&RNG_SR_OREG_LVL_MASK)
+#define RNG_SR_OREG_SIZE_MASK 0xFF0000u
+#define RNG_SR_OREG_SIZE_SHIFT 16
+#define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_SIZE_SHIFT))&RNG_SR_OREG_SIZE_MASK)
+/* ER Bit Fields */
+#define RNG_ER_EXT_ENT_MASK 0xFFFFFFFFu
+#define RNG_ER_EXT_ENT_SHIFT 0
+#define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x))<<RNG_ER_EXT_ENT_SHIFT))&RNG_ER_EXT_ENT_MASK)
+/* OR Bit Fields */
+#define RNG_OR_RANDOUT_MASK 0xFFFFFFFFu
+#define RNG_OR_RANDOUT_SHIFT 0
+#define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x))<<RNG_OR_RANDOUT_SHIFT))&RNG_OR_RANDOUT_MASK)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Masks */
+
+
+/* RNG - Peripheral instance base addresses */
+/** Peripheral RNG base address */
+#define RNG_BASE (0x40029000u)
+/** Peripheral RNG base pointer */
+#define RNG ((RNG_Type *)RNG_BASE)
+#define RNG_BASE_PTR (RNG)
+/** Array initializer of RNG peripheral base pointers */
+#define RNG_BASES { RNG }
+
+/* ----------------------------------------------------------------------------
+ -- RNG - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
+ * @{
+ */
+
+
+/* RNG - Register instance definitions */
+/* RNG */
+#define RNG_CR RNG_CR_REG(RNG)
+#define RNG_SR RNG_SR_REG(RNG)
+#define RNG_ER RNG_ER_REG(RNG)
+#define RNG_OR RNG_OR_REG(RNG)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RNG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
+ __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
+ __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
+ __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
+ __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
+ __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
+ __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
+ __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
+ uint8_t RESERVED_0[2016];
+ __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
+ __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
+} RTC_Type, *RTC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- RTC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
+ * @{
+ */
+
+
+/* RTC - Register accessors */
+#define RTC_TSR_REG(base) ((base)->TSR)
+#define RTC_TPR_REG(base) ((base)->TPR)
+#define RTC_TAR_REG(base) ((base)->TAR)
+#define RTC_TCR_REG(base) ((base)->TCR)
+#define RTC_CR_REG(base) ((base)->CR)
+#define RTC_SR_REG(base) ((base)->SR)
+#define RTC_LR_REG(base) ((base)->LR)
+#define RTC_IER_REG(base) ((base)->IER)
+#define RTC_WAR_REG(base) ((base)->WAR)
+#define RTC_RAR_REG(base) ((base)->RAR)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/* TSR Bit Fields */
+#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
+#define RTC_TSR_TSR_SHIFT 0
+#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
+/* TPR Bit Fields */
+#define RTC_TPR_TPR_MASK 0xFFFFu
+#define RTC_TPR_TPR_SHIFT 0
+#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
+/* TAR Bit Fields */
+#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
+#define RTC_TAR_TAR_SHIFT 0
+#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
+/* TCR Bit Fields */
+#define RTC_TCR_TCR_MASK 0xFFu
+#define RTC_TCR_TCR_SHIFT 0
+#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK 0xFF00u
+#define RTC_TCR_CIR_SHIFT 8
+#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK 0xFF0000u
+#define RTC_TCR_TCV_SHIFT 16
+#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK 0xFF000000u
+#define RTC_TCR_CIC_SHIFT 24
+#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
+/* CR Bit Fields */
+#define RTC_CR_SWR_MASK 0x1u
+#define RTC_CR_SWR_SHIFT 0
+#define RTC_CR_WPE_MASK 0x2u
+#define RTC_CR_WPE_SHIFT 1
+#define RTC_CR_SUP_MASK 0x4u
+#define RTC_CR_SUP_SHIFT 2
+#define RTC_CR_UM_MASK 0x8u
+#define RTC_CR_UM_SHIFT 3
+#define RTC_CR_WPS_MASK 0x10u
+#define RTC_CR_WPS_SHIFT 4
+#define RTC_CR_OSCE_MASK 0x100u
+#define RTC_CR_OSCE_SHIFT 8
+#define RTC_CR_CLKO_MASK 0x200u
+#define RTC_CR_CLKO_SHIFT 9
+#define RTC_CR_SC16P_MASK 0x400u
+#define RTC_CR_SC16P_SHIFT 10
+#define RTC_CR_SC8P_MASK 0x800u
+#define RTC_CR_SC8P_SHIFT 11
+#define RTC_CR_SC4P_MASK 0x1000u
+#define RTC_CR_SC4P_SHIFT 12
+#define RTC_CR_SC2P_MASK 0x2000u
+#define RTC_CR_SC2P_SHIFT 13
+/* SR Bit Fields */
+#define RTC_SR_TIF_MASK 0x1u
+#define RTC_SR_TIF_SHIFT 0
+#define RTC_SR_TOF_MASK 0x2u
+#define RTC_SR_TOF_SHIFT 1
+#define RTC_SR_TAF_MASK 0x4u
+#define RTC_SR_TAF_SHIFT 2
+#define RTC_SR_TCE_MASK 0x10u
+#define RTC_SR_TCE_SHIFT 4
+/* LR Bit Fields */
+#define RTC_LR_TCL_MASK 0x8u
+#define RTC_LR_TCL_SHIFT 3
+#define RTC_LR_CRL_MASK 0x10u
+#define RTC_LR_CRL_SHIFT 4
+#define RTC_LR_SRL_MASK 0x20u
+#define RTC_LR_SRL_SHIFT 5
+#define RTC_LR_LRL_MASK 0x40u
+#define RTC_LR_LRL_SHIFT 6
+/* IER Bit Fields */
+#define RTC_IER_TIIE_MASK 0x1u
+#define RTC_IER_TIIE_SHIFT 0
+#define RTC_IER_TOIE_MASK 0x2u
+#define RTC_IER_TOIE_SHIFT 1
+#define RTC_IER_TAIE_MASK 0x4u
+#define RTC_IER_TAIE_SHIFT 2
+#define RTC_IER_TSIE_MASK 0x10u
+#define RTC_IER_TSIE_SHIFT 4
+#define RTC_IER_WPON_MASK 0x80u
+#define RTC_IER_WPON_SHIFT 7
+/* WAR Bit Fields */
+#define RTC_WAR_TSRW_MASK 0x1u
+#define RTC_WAR_TSRW_SHIFT 0
+#define RTC_WAR_TPRW_MASK 0x2u
+#define RTC_WAR_TPRW_SHIFT 1
+#define RTC_WAR_TARW_MASK 0x4u
+#define RTC_WAR_TARW_SHIFT 2
+#define RTC_WAR_TCRW_MASK 0x8u
+#define RTC_WAR_TCRW_SHIFT 3
+#define RTC_WAR_CRW_MASK 0x10u
+#define RTC_WAR_CRW_SHIFT 4
+#define RTC_WAR_SRW_MASK 0x20u
+#define RTC_WAR_SRW_SHIFT 5
+#define RTC_WAR_LRW_MASK 0x40u
+#define RTC_WAR_LRW_SHIFT 6
+#define RTC_WAR_IERW_MASK 0x80u
+#define RTC_WAR_IERW_SHIFT 7
+/* RAR Bit Fields */
+#define RTC_RAR_TSRR_MASK 0x1u
+#define RTC_RAR_TSRR_SHIFT 0
+#define RTC_RAR_TPRR_MASK 0x2u
+#define RTC_RAR_TPRR_SHIFT 1
+#define RTC_RAR_TARR_MASK 0x4u
+#define RTC_RAR_TARR_SHIFT 2
+#define RTC_RAR_TCRR_MASK 0x8u
+#define RTC_RAR_TCRR_SHIFT 3
+#define RTC_RAR_CRR_MASK 0x10u
+#define RTC_RAR_CRR_SHIFT 4
+#define RTC_RAR_SRR_MASK 0x20u
+#define RTC_RAR_SRR_SHIFT 5
+#define RTC_RAR_LRR_MASK 0x40u
+#define RTC_RAR_LRR_SHIFT 6
+#define RTC_RAR_IERR_MASK 0x80u
+#define RTC_RAR_IERR_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC ((RTC_Type *)RTC_BASE)
+#define RTC_BASE_PTR (RTC)
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASES { RTC }
+
+/* ----------------------------------------------------------------------------
+ -- RTC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
+ * @{
+ */
+
+
+/* RTC - Register instance definitions */
+/* RTC */
+#define RTC_TSR RTC_TSR_REG(RTC)
+#define RTC_TPR RTC_TPR_REG(RTC)
+#define RTC_TAR RTC_TAR_REG(RTC)
+#define RTC_TCR RTC_TCR_REG(RTC)
+#define RTC_CR RTC_CR_REG(RTC)
+#define RTC_SR RTC_SR_REG(RTC)
+#define RTC_LR RTC_LR_REG(RTC)
+#define RTC_IER RTC_IER_REG(RTC)
+#define RTC_WAR RTC_WAR_REG(RTC)
+#define RTC_RAR RTC_RAR_REG(RTC)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SDHC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
+ * @{
+ */
+
+/** SDHC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t DSADDR; /**< DMA System Address register, offset: 0x0 */
+ __IO uint32_t BLKATTR; /**< Block Attributes register, offset: 0x4 */
+ __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x8 */
+ __IO uint32_t XFERTYP; /**< Transfer Type register, offset: 0xC */
+ __I uint32_t CMDRSP[4]; /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
+ __IO uint32_t DATPORT; /**< Buffer Data Port register, offset: 0x20 */
+ __I uint32_t PRSSTAT; /**< Present State register, offset: 0x24 */
+ __IO uint32_t PROCTL; /**< Protocol Control register, offset: 0x28 */
+ __IO uint32_t SYSCTL; /**< System Control register, offset: 0x2C */
+ __IO uint32_t IRQSTAT; /**< Interrupt Status register, offset: 0x30 */
+ __IO uint32_t IRQSTATEN; /**< Interrupt Status Enable register, offset: 0x34 */
+ __IO uint32_t IRQSIGEN; /**< Interrupt Signal Enable register, offset: 0x38 */
+ __I uint32_t AC12ERR; /**< Auto CMD12 Error Status Register, offset: 0x3C */
+ __I uint32_t HTCAPBLT; /**< Host Controller Capabilities, offset: 0x40 */
+ __IO uint32_t WML; /**< Watermark Level Register, offset: 0x44 */
+ uint8_t RESERVED_0[8];
+ __O uint32_t FEVT; /**< Force Event register, offset: 0x50 */
+ __I uint32_t ADMAES; /**< ADMA Error Status register, offset: 0x54 */
+ __IO uint32_t ADSADDR; /**< ADMA System Addressregister, offset: 0x58 */
+ uint8_t RESERVED_1[100];
+ __IO uint32_t VENDOR; /**< Vendor Specific register, offset: 0xC0 */
+ __IO uint32_t MMCBOOT; /**< MMC Boot register, offset: 0xC4 */
+ uint8_t RESERVED_2[52];
+ __I uint32_t HOSTVER; /**< Host Controller Version, offset: 0xFC */
+} SDHC_Type, *SDHC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- SDHC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
+ * @{
+ */
+
+
+/* SDHC - Register accessors */
+#define SDHC_DSADDR_REG(base) ((base)->DSADDR)
+#define SDHC_BLKATTR_REG(base) ((base)->BLKATTR)
+#define SDHC_CMDARG_REG(base) ((base)->CMDARG)
+#define SDHC_XFERTYP_REG(base) ((base)->XFERTYP)
+#define SDHC_CMDRSP_REG(base,index) ((base)->CMDRSP[index])
+#define SDHC_DATPORT_REG(base) ((base)->DATPORT)
+#define SDHC_PRSSTAT_REG(base) ((base)->PRSSTAT)
+#define SDHC_PROCTL_REG(base) ((base)->PROCTL)
+#define SDHC_SYSCTL_REG(base) ((base)->SYSCTL)
+#define SDHC_IRQSTAT_REG(base) ((base)->IRQSTAT)
+#define SDHC_IRQSTATEN_REG(base) ((base)->IRQSTATEN)
+#define SDHC_IRQSIGEN_REG(base) ((base)->IRQSIGEN)
+#define SDHC_AC12ERR_REG(base) ((base)->AC12ERR)
+#define SDHC_HTCAPBLT_REG(base) ((base)->HTCAPBLT)
+#define SDHC_WML_REG(base) ((base)->WML)
+#define SDHC_FEVT_REG(base) ((base)->FEVT)
+#define SDHC_ADMAES_REG(base) ((base)->ADMAES)
+#define SDHC_ADSADDR_REG(base) ((base)->ADSADDR)
+#define SDHC_VENDOR_REG(base) ((base)->VENDOR)
+#define SDHC_MMCBOOT_REG(base) ((base)->MMCBOOT)
+#define SDHC_HOSTVER_REG(base) ((base)->HOSTVER)
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SDHC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Masks SDHC Register Masks
+ * @{
+ */
+
+/* DSADDR Bit Fields */
+#define SDHC_DSADDR_DSADDR_MASK 0xFFFFFFFCu
+#define SDHC_DSADDR_DSADDR_SHIFT 2
+#define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DSADDR_DSADDR_SHIFT))&SDHC_DSADDR_DSADDR_MASK)
+/* BLKATTR Bit Fields */
+#define SDHC_BLKATTR_BLKSIZE_MASK 0x1FFFu
+#define SDHC_BLKATTR_BLKSIZE_SHIFT 0
+#define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKSIZE_SHIFT))&SDHC_BLKATTR_BLKSIZE_MASK)
+#define SDHC_BLKATTR_BLKCNT_MASK 0xFFFF0000u
+#define SDHC_BLKATTR_BLKCNT_SHIFT 16
+#define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKCNT_SHIFT))&SDHC_BLKATTR_BLKCNT_MASK)
+/* CMDARG Bit Fields */
+#define SDHC_CMDARG_CMDARG_MASK 0xFFFFFFFFu
+#define SDHC_CMDARG_CMDARG_SHIFT 0
+#define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDARG_CMDARG_SHIFT))&SDHC_CMDARG_CMDARG_MASK)
+/* XFERTYP Bit Fields */
+#define SDHC_XFERTYP_DMAEN_MASK 0x1u
+#define SDHC_XFERTYP_DMAEN_SHIFT 0
+#define SDHC_XFERTYP_BCEN_MASK 0x2u
+#define SDHC_XFERTYP_BCEN_SHIFT 1
+#define SDHC_XFERTYP_AC12EN_MASK 0x4u
+#define SDHC_XFERTYP_AC12EN_SHIFT 2
+#define SDHC_XFERTYP_DTDSEL_MASK 0x10u
+#define SDHC_XFERTYP_DTDSEL_SHIFT 4
+#define SDHC_XFERTYP_MSBSEL_MASK 0x20u
+#define SDHC_XFERTYP_MSBSEL_SHIFT 5
+#define SDHC_XFERTYP_RSPTYP_MASK 0x30000u
+#define SDHC_XFERTYP_RSPTYP_SHIFT 16
+#define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_RSPTYP_SHIFT))&SDHC_XFERTYP_RSPTYP_MASK)
+#define SDHC_XFERTYP_CCCEN_MASK 0x80000u
+#define SDHC_XFERTYP_CCCEN_SHIFT 19
+#define SDHC_XFERTYP_CICEN_MASK 0x100000u
+#define SDHC_XFERTYP_CICEN_SHIFT 20
+#define SDHC_XFERTYP_DPSEL_MASK 0x200000u
+#define SDHC_XFERTYP_DPSEL_SHIFT 21
+#define SDHC_XFERTYP_CMDTYP_MASK 0xC00000u
+#define SDHC_XFERTYP_CMDTYP_SHIFT 22
+#define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDTYP_SHIFT))&SDHC_XFERTYP_CMDTYP_MASK)
+#define SDHC_XFERTYP_CMDINX_MASK 0x3F000000u
+#define SDHC_XFERTYP_CMDINX_SHIFT 24
+#define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDINX_SHIFT))&SDHC_XFERTYP_CMDINX_MASK)
+/* CMDRSP Bit Fields */
+#define SDHC_CMDRSP_CMDRSP0_MASK 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP0_SHIFT 0
+#define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP0_SHIFT))&SDHC_CMDRSP_CMDRSP0_MASK)
+#define SDHC_CMDRSP_CMDRSP1_MASK 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP1_SHIFT 0
+#define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP1_SHIFT))&SDHC_CMDRSP_CMDRSP1_MASK)
+#define SDHC_CMDRSP_CMDRSP2_MASK 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP2_SHIFT 0
+#define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP2_SHIFT))&SDHC_CMDRSP_CMDRSP2_MASK)
+#define SDHC_CMDRSP_CMDRSP3_MASK 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP3_SHIFT 0
+#define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP3_SHIFT))&SDHC_CMDRSP_CMDRSP3_MASK)
+/* DATPORT Bit Fields */
+#define SDHC_DATPORT_DATCONT_MASK 0xFFFFFFFFu
+#define SDHC_DATPORT_DATCONT_SHIFT 0
+#define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DATPORT_DATCONT_SHIFT))&SDHC_DATPORT_DATCONT_MASK)
+/* PRSSTAT Bit Fields */
+#define SDHC_PRSSTAT_CIHB_MASK 0x1u
+#define SDHC_PRSSTAT_CIHB_SHIFT 0
+#define SDHC_PRSSTAT_CDIHB_MASK 0x2u
+#define SDHC_PRSSTAT_CDIHB_SHIFT 1
+#define SDHC_PRSSTAT_DLA_MASK 0x4u
+#define SDHC_PRSSTAT_DLA_SHIFT 2
+#define SDHC_PRSSTAT_SDSTB_MASK 0x8u
+#define SDHC_PRSSTAT_SDSTB_SHIFT 3
+#define SDHC_PRSSTAT_IPGOFF_MASK 0x10u
+#define SDHC_PRSSTAT_IPGOFF_SHIFT 4
+#define SDHC_PRSSTAT_HCKOFF_MASK 0x20u
+#define SDHC_PRSSTAT_HCKOFF_SHIFT 5
+#define SDHC_PRSSTAT_PEROFF_MASK 0x40u
+#define SDHC_PRSSTAT_PEROFF_SHIFT 6
+#define SDHC_PRSSTAT_SDOFF_MASK 0x80u
+#define SDHC_PRSSTAT_SDOFF_SHIFT 7
+#define SDHC_PRSSTAT_WTA_MASK 0x100u
+#define SDHC_PRSSTAT_WTA_SHIFT 8
+#define SDHC_PRSSTAT_RTA_MASK 0x200u
+#define SDHC_PRSSTAT_RTA_SHIFT 9
+#define SDHC_PRSSTAT_BWEN_MASK 0x400u
+#define SDHC_PRSSTAT_BWEN_SHIFT 10
+#define SDHC_PRSSTAT_BREN_MASK 0x800u
+#define SDHC_PRSSTAT_BREN_SHIFT 11
+#define SDHC_PRSSTAT_CINS_MASK 0x10000u
+#define SDHC_PRSSTAT_CINS_SHIFT 16
+#define SDHC_PRSSTAT_CLSL_MASK 0x800000u
+#define SDHC_PRSSTAT_CLSL_SHIFT 23
+#define SDHC_PRSSTAT_DLSL_MASK 0xFF000000u
+#define SDHC_PRSSTAT_DLSL_SHIFT 24
+#define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLSL_SHIFT))&SDHC_PRSSTAT_DLSL_MASK)
+/* PROCTL Bit Fields */
+#define SDHC_PROCTL_LCTL_MASK 0x1u
+#define SDHC_PROCTL_LCTL_SHIFT 0
+#define SDHC_PROCTL_DTW_MASK 0x6u
+#define SDHC_PROCTL_DTW_SHIFT 1
+#define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DTW_SHIFT))&SDHC_PROCTL_DTW_MASK)
+#define SDHC_PROCTL_D3CD_MASK 0x8u
+#define SDHC_PROCTL_D3CD_SHIFT 3
+#define SDHC_PROCTL_EMODE_MASK 0x30u
+#define SDHC_PROCTL_EMODE_SHIFT 4
+#define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_EMODE_SHIFT))&SDHC_PROCTL_EMODE_MASK)
+#define SDHC_PROCTL_CDTL_MASK 0x40u
+#define SDHC_PROCTL_CDTL_SHIFT 6
+#define SDHC_PROCTL_CDSS_MASK 0x80u
+#define SDHC_PROCTL_CDSS_SHIFT 7
+#define SDHC_PROCTL_DMAS_MASK 0x300u
+#define SDHC_PROCTL_DMAS_SHIFT 8
+#define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DMAS_SHIFT))&SDHC_PROCTL_DMAS_MASK)
+#define SDHC_PROCTL_SABGREQ_MASK 0x10000u
+#define SDHC_PROCTL_SABGREQ_SHIFT 16
+#define SDHC_PROCTL_CREQ_MASK 0x20000u
+#define SDHC_PROCTL_CREQ_SHIFT 17
+#define SDHC_PROCTL_RWCTL_MASK 0x40000u
+#define SDHC_PROCTL_RWCTL_SHIFT 18
+#define SDHC_PROCTL_IABG_MASK 0x80000u
+#define SDHC_PROCTL_IABG_SHIFT 19
+#define SDHC_PROCTL_WECINT_MASK 0x1000000u
+#define SDHC_PROCTL_WECINT_SHIFT 24
+#define SDHC_PROCTL_WECINS_MASK 0x2000000u
+#define SDHC_PROCTL_WECINS_SHIFT 25
+#define SDHC_PROCTL_WECRM_MASK 0x4000000u
+#define SDHC_PROCTL_WECRM_SHIFT 26
+/* SYSCTL Bit Fields */
+#define SDHC_SYSCTL_IPGEN_MASK 0x1u
+#define SDHC_SYSCTL_IPGEN_SHIFT 0
+#define SDHC_SYSCTL_HCKEN_MASK 0x2u
+#define SDHC_SYSCTL_HCKEN_SHIFT 1
+#define SDHC_SYSCTL_PEREN_MASK 0x4u
+#define SDHC_SYSCTL_PEREN_SHIFT 2
+#define SDHC_SYSCTL_SDCLKEN_MASK 0x8u
+#define SDHC_SYSCTL_SDCLKEN_SHIFT 3
+#define SDHC_SYSCTL_DVS_MASK 0xF0u
+#define SDHC_SYSCTL_DVS_SHIFT 4
+#define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DVS_SHIFT))&SDHC_SYSCTL_DVS_MASK)
+#define SDHC_SYSCTL_SDCLKFS_MASK 0xFF00u
+#define SDHC_SYSCTL_SDCLKFS_SHIFT 8
+#define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKFS_SHIFT))&SDHC_SYSCTL_SDCLKFS_MASK)
+#define SDHC_SYSCTL_DTOCV_MASK 0xF0000u
+#define SDHC_SYSCTL_DTOCV_SHIFT 16
+#define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DTOCV_SHIFT))&SDHC_SYSCTL_DTOCV_MASK)
+#define SDHC_SYSCTL_RSTA_MASK 0x1000000u
+#define SDHC_SYSCTL_RSTA_SHIFT 24
+#define SDHC_SYSCTL_RSTC_MASK 0x2000000u
+#define SDHC_SYSCTL_RSTC_SHIFT 25
+#define SDHC_SYSCTL_RSTD_MASK 0x4000000u
+#define SDHC_SYSCTL_RSTD_SHIFT 26
+#define SDHC_SYSCTL_INITA_MASK 0x8000000u
+#define SDHC_SYSCTL_INITA_SHIFT 27
+/* IRQSTAT Bit Fields */
+#define SDHC_IRQSTAT_CC_MASK 0x1u
+#define SDHC_IRQSTAT_CC_SHIFT 0
+#define SDHC_IRQSTAT_TC_MASK 0x2u
+#define SDHC_IRQSTAT_TC_SHIFT 1
+#define SDHC_IRQSTAT_BGE_MASK 0x4u
+#define SDHC_IRQSTAT_BGE_SHIFT 2
+#define SDHC_IRQSTAT_DINT_MASK 0x8u
+#define SDHC_IRQSTAT_DINT_SHIFT 3
+#define SDHC_IRQSTAT_BWR_MASK 0x10u
+#define SDHC_IRQSTAT_BWR_SHIFT 4
+#define SDHC_IRQSTAT_BRR_MASK 0x20u
+#define SDHC_IRQSTAT_BRR_SHIFT 5
+#define SDHC_IRQSTAT_CINS_MASK 0x40u
+#define SDHC_IRQSTAT_CINS_SHIFT 6
+#define SDHC_IRQSTAT_CRM_MASK 0x80u
+#define SDHC_IRQSTAT_CRM_SHIFT 7
+#define SDHC_IRQSTAT_CINT_MASK 0x100u
+#define SDHC_IRQSTAT_CINT_SHIFT 8
+#define SDHC_IRQSTAT_CTOE_MASK 0x10000u
+#define SDHC_IRQSTAT_CTOE_SHIFT 16
+#define SDHC_IRQSTAT_CCE_MASK 0x20000u
+#define SDHC_IRQSTAT_CCE_SHIFT 17
+#define SDHC_IRQSTAT_CEBE_MASK 0x40000u
+#define SDHC_IRQSTAT_CEBE_SHIFT 18
+#define SDHC_IRQSTAT_CIE_MASK 0x80000u
+#define SDHC_IRQSTAT_CIE_SHIFT 19
+#define SDHC_IRQSTAT_DTOE_MASK 0x100000u
+#define SDHC_IRQSTAT_DTOE_SHIFT 20
+#define SDHC_IRQSTAT_DCE_MASK 0x200000u
+#define SDHC_IRQSTAT_DCE_SHIFT 21
+#define SDHC_IRQSTAT_DEBE_MASK 0x400000u
+#define SDHC_IRQSTAT_DEBE_SHIFT 22
+#define SDHC_IRQSTAT_AC12E_MASK 0x1000000u
+#define SDHC_IRQSTAT_AC12E_SHIFT 24
+#define SDHC_IRQSTAT_DMAE_MASK 0x10000000u
+#define SDHC_IRQSTAT_DMAE_SHIFT 28
+/* IRQSTATEN Bit Fields */
+#define SDHC_IRQSTATEN_CCSEN_MASK 0x1u
+#define SDHC_IRQSTATEN_CCSEN_SHIFT 0
+#define SDHC_IRQSTATEN_TCSEN_MASK 0x2u
+#define SDHC_IRQSTATEN_TCSEN_SHIFT 1
+#define SDHC_IRQSTATEN_BGESEN_MASK 0x4u
+#define SDHC_IRQSTATEN_BGESEN_SHIFT 2
+#define SDHC_IRQSTATEN_DINTSEN_MASK 0x8u
+#define SDHC_IRQSTATEN_DINTSEN_SHIFT 3
+#define SDHC_IRQSTATEN_BWRSEN_MASK 0x10u
+#define SDHC_IRQSTATEN_BWRSEN_SHIFT 4
+#define SDHC_IRQSTATEN_BRRSEN_MASK 0x20u
+#define SDHC_IRQSTATEN_BRRSEN_SHIFT 5
+#define SDHC_IRQSTATEN_CINSEN_MASK 0x40u
+#define SDHC_IRQSTATEN_CINSEN_SHIFT 6
+#define SDHC_IRQSTATEN_CRMSEN_MASK 0x80u
+#define SDHC_IRQSTATEN_CRMSEN_SHIFT 7
+#define SDHC_IRQSTATEN_CINTSEN_MASK 0x100u
+#define SDHC_IRQSTATEN_CINTSEN_SHIFT 8
+#define SDHC_IRQSTATEN_CTOESEN_MASK 0x10000u
+#define SDHC_IRQSTATEN_CTOESEN_SHIFT 16
+#define SDHC_IRQSTATEN_CCESEN_MASK 0x20000u
+#define SDHC_IRQSTATEN_CCESEN_SHIFT 17
+#define SDHC_IRQSTATEN_CEBESEN_MASK 0x40000u
+#define SDHC_IRQSTATEN_CEBESEN_SHIFT 18
+#define SDHC_IRQSTATEN_CIESEN_MASK 0x80000u
+#define SDHC_IRQSTATEN_CIESEN_SHIFT 19
+#define SDHC_IRQSTATEN_DTOESEN_MASK 0x100000u
+#define SDHC_IRQSTATEN_DTOESEN_SHIFT 20
+#define SDHC_IRQSTATEN_DCESEN_MASK 0x200000u
+#define SDHC_IRQSTATEN_DCESEN_SHIFT 21
+#define SDHC_IRQSTATEN_DEBESEN_MASK 0x400000u
+#define SDHC_IRQSTATEN_DEBESEN_SHIFT 22
+#define SDHC_IRQSTATEN_AC12ESEN_MASK 0x1000000u
+#define SDHC_IRQSTATEN_AC12ESEN_SHIFT 24
+#define SDHC_IRQSTATEN_DMAESEN_MASK 0x10000000u
+#define SDHC_IRQSTATEN_DMAESEN_SHIFT 28
+/* IRQSIGEN Bit Fields */
+#define SDHC_IRQSIGEN_CCIEN_MASK 0x1u
+#define SDHC_IRQSIGEN_CCIEN_SHIFT 0
+#define SDHC_IRQSIGEN_TCIEN_MASK 0x2u
+#define SDHC_IRQSIGEN_TCIEN_SHIFT 1
+#define SDHC_IRQSIGEN_BGEIEN_MASK 0x4u
+#define SDHC_IRQSIGEN_BGEIEN_SHIFT 2
+#define SDHC_IRQSIGEN_DINTIEN_MASK 0x8u
+#define SDHC_IRQSIGEN_DINTIEN_SHIFT 3
+#define SDHC_IRQSIGEN_BWRIEN_MASK 0x10u
+#define SDHC_IRQSIGEN_BWRIEN_SHIFT 4
+#define SDHC_IRQSIGEN_BRRIEN_MASK 0x20u
+#define SDHC_IRQSIGEN_BRRIEN_SHIFT 5
+#define SDHC_IRQSIGEN_CINSIEN_MASK 0x40u
+#define SDHC_IRQSIGEN_CINSIEN_SHIFT 6
+#define SDHC_IRQSIGEN_CRMIEN_MASK 0x80u
+#define SDHC_IRQSIGEN_CRMIEN_SHIFT 7
+#define SDHC_IRQSIGEN_CINTIEN_MASK 0x100u
+#define SDHC_IRQSIGEN_CINTIEN_SHIFT 8
+#define SDHC_IRQSIGEN_CTOEIEN_MASK 0x10000u
+#define SDHC_IRQSIGEN_CTOEIEN_SHIFT 16
+#define SDHC_IRQSIGEN_CCEIEN_MASK 0x20000u
+#define SDHC_IRQSIGEN_CCEIEN_SHIFT 17
+#define SDHC_IRQSIGEN_CEBEIEN_MASK 0x40000u
+#define SDHC_IRQSIGEN_CEBEIEN_SHIFT 18
+#define SDHC_IRQSIGEN_CIEIEN_MASK 0x80000u
+#define SDHC_IRQSIGEN_CIEIEN_SHIFT 19
+#define SDHC_IRQSIGEN_DTOEIEN_MASK 0x100000u
+#define SDHC_IRQSIGEN_DTOEIEN_SHIFT 20
+#define SDHC_IRQSIGEN_DCEIEN_MASK 0x200000u
+#define SDHC_IRQSIGEN_DCEIEN_SHIFT 21
+#define SDHC_IRQSIGEN_DEBEIEN_MASK 0x400000u
+#define SDHC_IRQSIGEN_DEBEIEN_SHIFT 22
+#define SDHC_IRQSIGEN_AC12EIEN_MASK 0x1000000u
+#define SDHC_IRQSIGEN_AC12EIEN_SHIFT 24
+#define SDHC_IRQSIGEN_DMAEIEN_MASK 0x10000000u
+#define SDHC_IRQSIGEN_DMAEIEN_SHIFT 28
+/* AC12ERR Bit Fields */
+#define SDHC_AC12ERR_AC12NE_MASK 0x1u
+#define SDHC_AC12ERR_AC12NE_SHIFT 0
+#define SDHC_AC12ERR_AC12TOE_MASK 0x2u
+#define SDHC_AC12ERR_AC12TOE_SHIFT 1
+#define SDHC_AC12ERR_AC12EBE_MASK 0x4u
+#define SDHC_AC12ERR_AC12EBE_SHIFT 2
+#define SDHC_AC12ERR_AC12CE_MASK 0x8u
+#define SDHC_AC12ERR_AC12CE_SHIFT 3
+#define SDHC_AC12ERR_AC12IE_MASK 0x10u
+#define SDHC_AC12ERR_AC12IE_SHIFT 4
+#define SDHC_AC12ERR_CNIBAC12E_MASK 0x80u
+#define SDHC_AC12ERR_CNIBAC12E_SHIFT 7
+/* HTCAPBLT Bit Fields */
+#define SDHC_HTCAPBLT_MBL_MASK 0x70000u
+#define SDHC_HTCAPBLT_MBL_SHIFT 16
+#define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_MBL_SHIFT))&SDHC_HTCAPBLT_MBL_MASK)
+#define SDHC_HTCAPBLT_ADMAS_MASK 0x100000u
+#define SDHC_HTCAPBLT_ADMAS_SHIFT 20
+#define SDHC_HTCAPBLT_HSS_MASK 0x200000u
+#define SDHC_HTCAPBLT_HSS_SHIFT 21
+#define SDHC_HTCAPBLT_DMAS_MASK 0x400000u
+#define SDHC_HTCAPBLT_DMAS_SHIFT 22
+#define SDHC_HTCAPBLT_SRS_MASK 0x800000u
+#define SDHC_HTCAPBLT_SRS_SHIFT 23
+#define SDHC_HTCAPBLT_VS33_MASK 0x1000000u
+#define SDHC_HTCAPBLT_VS33_SHIFT 24
+/* WML Bit Fields */
+#define SDHC_WML_RDWML_MASK 0xFFu
+#define SDHC_WML_RDWML_SHIFT 0
+#define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_RDWML_SHIFT))&SDHC_WML_RDWML_MASK)
+#define SDHC_WML_WRWML_MASK 0xFF0000u
+#define SDHC_WML_WRWML_SHIFT 16
+#define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRWML_SHIFT))&SDHC_WML_WRWML_MASK)
+/* FEVT Bit Fields */
+#define SDHC_FEVT_AC12NE_MASK 0x1u
+#define SDHC_FEVT_AC12NE_SHIFT 0
+#define SDHC_FEVT_AC12TOE_MASK 0x2u
+#define SDHC_FEVT_AC12TOE_SHIFT 1
+#define SDHC_FEVT_AC12CE_MASK 0x4u
+#define SDHC_FEVT_AC12CE_SHIFT 2
+#define SDHC_FEVT_AC12EBE_MASK 0x8u
+#define SDHC_FEVT_AC12EBE_SHIFT 3
+#define SDHC_FEVT_AC12IE_MASK 0x10u
+#define SDHC_FEVT_AC12IE_SHIFT 4
+#define SDHC_FEVT_CNIBAC12E_MASK 0x80u
+#define SDHC_FEVT_CNIBAC12E_SHIFT 7
+#define SDHC_FEVT_CTOE_MASK 0x10000u
+#define SDHC_FEVT_CTOE_SHIFT 16
+#define SDHC_FEVT_CCE_MASK 0x20000u
+#define SDHC_FEVT_CCE_SHIFT 17
+#define SDHC_FEVT_CEBE_MASK 0x40000u
+#define SDHC_FEVT_CEBE_SHIFT 18
+#define SDHC_FEVT_CIE_MASK 0x80000u
+#define SDHC_FEVT_CIE_SHIFT 19
+#define SDHC_FEVT_DTOE_MASK 0x100000u
+#define SDHC_FEVT_DTOE_SHIFT 20
+#define SDHC_FEVT_DCE_MASK 0x200000u
+#define SDHC_FEVT_DCE_SHIFT 21
+#define SDHC_FEVT_DEBE_MASK 0x400000u
+#define SDHC_FEVT_DEBE_SHIFT 22
+#define SDHC_FEVT_AC12E_MASK 0x1000000u
+#define SDHC_FEVT_AC12E_SHIFT 24
+#define SDHC_FEVT_DMAE_MASK 0x10000000u
+#define SDHC_FEVT_DMAE_SHIFT 28
+#define SDHC_FEVT_CINT_MASK 0x80000000u
+#define SDHC_FEVT_CINT_SHIFT 31
+/* ADMAES Bit Fields */
+#define SDHC_ADMAES_ADMAES_MASK 0x3u
+#define SDHC_ADMAES_ADMAES_SHIFT 0
+#define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMAES_SHIFT))&SDHC_ADMAES_ADMAES_MASK)
+#define SDHC_ADMAES_ADMALME_MASK 0x4u
+#define SDHC_ADMAES_ADMALME_SHIFT 2
+#define SDHC_ADMAES_ADMADCE_MASK 0x8u
+#define SDHC_ADMAES_ADMADCE_SHIFT 3
+/* ADSADDR Bit Fields */
+#define SDHC_ADSADDR_ADSADDR_MASK 0xFFFFFFFCu
+#define SDHC_ADSADDR_ADSADDR_SHIFT 2
+#define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADSADDR_ADSADDR_SHIFT))&SDHC_ADSADDR_ADSADDR_MASK)
+/* VENDOR Bit Fields */
+#define SDHC_VENDOR_EXTDMAEN_MASK 0x1u
+#define SDHC_VENDOR_EXTDMAEN_SHIFT 0
+#define SDHC_VENDOR_EXBLKNU_MASK 0x2u
+#define SDHC_VENDOR_EXBLKNU_SHIFT 1
+#define SDHC_VENDOR_INTSTVAL_MASK 0xFF0000u
+#define SDHC_VENDOR_INTSTVAL_SHIFT 16
+#define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_INTSTVAL_SHIFT))&SDHC_VENDOR_INTSTVAL_MASK)
+/* MMCBOOT Bit Fields */
+#define SDHC_MMCBOOT_DTOCVACK_MASK 0xFu
+#define SDHC_MMCBOOT_DTOCVACK_SHIFT 0
+#define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_DTOCVACK_SHIFT))&SDHC_MMCBOOT_DTOCVACK_MASK)
+#define SDHC_MMCBOOT_BOOTACK_MASK 0x10u
+#define SDHC_MMCBOOT_BOOTACK_SHIFT 4
+#define SDHC_MMCBOOT_BOOTMODE_MASK 0x20u
+#define SDHC_MMCBOOT_BOOTMODE_SHIFT 5
+#define SDHC_MMCBOOT_BOOTEN_MASK 0x40u
+#define SDHC_MMCBOOT_BOOTEN_SHIFT 6
+#define SDHC_MMCBOOT_AUTOSABGEN_MASK 0x80u
+#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT 7
+#define SDHC_MMCBOOT_BOOTBLKCNT_MASK 0xFFFF0000u
+#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT 16
+#define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTBLKCNT_SHIFT))&SDHC_MMCBOOT_BOOTBLKCNT_MASK)
+/* HOSTVER Bit Fields */
+#define SDHC_HOSTVER_SVN_MASK 0xFFu
+#define SDHC_HOSTVER_SVN_SHIFT 0
+#define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_SVN_SHIFT))&SDHC_HOSTVER_SVN_MASK)
+#define SDHC_HOSTVER_VVN_MASK 0xFF00u
+#define SDHC_HOSTVER_VVN_SHIFT 8
+#define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_VVN_SHIFT))&SDHC_HOSTVER_VVN_MASK)
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Masks */
+
+
+/* SDHC - Peripheral instance base addresses */
+/** Peripheral SDHC base address */
+#define SDHC_BASE (0x400B1000u)
+/** Peripheral SDHC base pointer */
+#define SDHC ((SDHC_Type *)SDHC_BASE)
+#define SDHC_BASE_PTR (SDHC)
+/** Array initializer of SDHC peripheral base pointers */
+#define SDHC_BASES { SDHC }
+
+/* ----------------------------------------------------------------------------
+ -- SDHC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
+ * @{
+ */
+
+
+/* SDHC - Register instance definitions */
+/* SDHC */
+#define SDHC_DSADDR SDHC_DSADDR_REG(SDHC)
+#define SDHC_BLKATTR SDHC_BLKATTR_REG(SDHC)
+#define SDHC_CMDARG SDHC_CMDARG_REG(SDHC)
+#define SDHC_XFERTYP SDHC_XFERTYP_REG(SDHC)
+#define SDHC_CMDRSP0 SDHC_CMDRSP_REG(SDHC,0)
+#define SDHC_CMDRSP1 SDHC_CMDRSP_REG(SDHC,1)
+#define SDHC_CMDRSP2 SDHC_CMDRSP_REG(SDHC,2)
+#define SDHC_CMDRSP3 SDHC_CMDRSP_REG(SDHC,3)
+#define SDHC_DATPORT SDHC_DATPORT_REG(SDHC)
+#define SDHC_PRSSTAT SDHC_PRSSTAT_REG(SDHC)
+#define SDHC_PROCTL SDHC_PROCTL_REG(SDHC)
+#define SDHC_SYSCTL SDHC_SYSCTL_REG(SDHC)
+#define SDHC_IRQSTAT SDHC_IRQSTAT_REG(SDHC)
+#define SDHC_IRQSTATEN SDHC_IRQSTATEN_REG(SDHC)
+#define SDHC_IRQSIGEN SDHC_IRQSIGEN_REG(SDHC)
+#define SDHC_AC12ERR SDHC_AC12ERR_REG(SDHC)
+#define SDHC_HTCAPBLT SDHC_HTCAPBLT_REG(SDHC)
+#define SDHC_WML SDHC_WML_REG(SDHC)
+#define SDHC_FEVT SDHC_FEVT_REG(SDHC)
+#define SDHC_ADMAES SDHC_ADMAES_REG(SDHC)
+#define SDHC_ADSADDR SDHC_ADSADDR_REG(SDHC)
+#define SDHC_VENDOR SDHC_VENDOR_REG(SDHC)
+#define SDHC_MMCBOOT SDHC_MMCBOOT_REG(SDHC)
+#define SDHC_HOSTVER SDHC_HOSTVER_REG(SDHC)
+
+/* SDHC - Register array accessors */
+#define SDHC_CMDRSP(index) SDHC_CMDRSP_REG(SDHC,index)
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SDHC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SIM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
+ __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
+ uint8_t RESERVED_0[4092];
+ __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
+ __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
+ uint8_t RESERVED_3[8];
+ __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
+ __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */
+ __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */
+ __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */
+ __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
+ __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
+ __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
+ __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
+ __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
+ __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
+ __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
+ __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
+ __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
+ __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
+ __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
+ __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
+} SIM_Type, *SIM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- SIM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
+ * @{
+ */
+
+
+/* SIM - Register accessors */
+#define SIM_SOPT1_REG(base) ((base)->SOPT1)
+#define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG)
+#define SIM_SOPT2_REG(base) ((base)->SOPT2)
+#define SIM_SOPT4_REG(base) ((base)->SOPT4)
+#define SIM_SOPT5_REG(base) ((base)->SOPT5)
+#define SIM_SOPT7_REG(base) ((base)->SOPT7)
+#define SIM_SDID_REG(base) ((base)->SDID)
+#define SIM_SCGC1_REG(base) ((base)->SCGC1)
+#define SIM_SCGC2_REG(base) ((base)->SCGC2)
+#define SIM_SCGC3_REG(base) ((base)->SCGC3)
+#define SIM_SCGC4_REG(base) ((base)->SCGC4)
+#define SIM_SCGC5_REG(base) ((base)->SCGC5)
+#define SIM_SCGC6_REG(base) ((base)->SCGC6)
+#define SIM_SCGC7_REG(base) ((base)->SCGC7)
+#define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)
+#define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2)
+#define SIM_FCFG1_REG(base) ((base)->FCFG1)
+#define SIM_FCFG2_REG(base) ((base)->FCFG2)
+#define SIM_UIDH_REG(base) ((base)->UIDH)
+#define SIM_UIDMH_REG(base) ((base)->UIDMH)
+#define SIM_UIDML_REG(base) ((base)->UIDML)
+#define SIM_UIDL_REG(base) ((base)->UIDL)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SIM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/* SOPT1 Bit Fields */
+#define SIM_SOPT1_RAMSIZE_MASK 0xF000u
+#define SIM_SOPT1_RAMSIZE_SHIFT 12
+#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
+#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
+#define SIM_SOPT1_OSC32KSEL_SHIFT 18
+#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
+#define SIM_SOPT1_USBVSTBY_SHIFT 29
+#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
+#define SIM_SOPT1_USBSSTBY_SHIFT 30
+#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
+#define SIM_SOPT1_USBREGEN_SHIFT 31
+/* SOPT1CFG Bit Fields */
+#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
+#define SIM_SOPT1CFG_URWE_SHIFT 24
+#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
+#define SIM_SOPT1CFG_UVSWE_SHIFT 25
+#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
+#define SIM_SOPT1CFG_USSWE_SHIFT 26
+/* SOPT2 Bit Fields */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
+#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
+#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
+#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_FBSL_MASK 0x300u
+#define SIM_SOPT2_FBSL_SHIFT 8
+#define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
+#define SIM_SOPT2_PTD7PAD_MASK 0x800u
+#define SIM_SOPT2_PTD7PAD_SHIFT 11
+#define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
+#define SIM_SOPT2_TRACECLKSEL_SHIFT 12
+#define SIM_SOPT2_PLLFLLSEL_MASK 0x30000u
+#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
+#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PLLFLLSEL_SHIFT))&SIM_SOPT2_PLLFLLSEL_MASK)
+#define SIM_SOPT2_USBSRC_MASK 0x40000u
+#define SIM_SOPT2_USBSRC_SHIFT 18
+#define SIM_SOPT2_RMIISRC_MASK 0x80000u
+#define SIM_SOPT2_RMIISRC_SHIFT 19
+#define SIM_SOPT2_TIMESRC_MASK 0x300000u
+#define SIM_SOPT2_TIMESRC_SHIFT 20
+#define SIM_SOPT2_TIMESRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TIMESRC_SHIFT))&SIM_SOPT2_TIMESRC_MASK)
+#define SIM_SOPT2_SDHCSRC_MASK 0x30000000u
+#define SIM_SOPT2_SDHCSRC_SHIFT 28
+#define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_SDHCSRC_SHIFT))&SIM_SOPT2_SDHCSRC_MASK)
+/* SOPT4 Bit Fields */
+#define SIM_SOPT4_FTM0FLT0_MASK 0x1u
+#define SIM_SOPT4_FTM0FLT0_SHIFT 0
+#define SIM_SOPT4_FTM0FLT1_MASK 0x2u
+#define SIM_SOPT4_FTM0FLT1_SHIFT 1
+#define SIM_SOPT4_FTM0FLT2_MASK 0x4u
+#define SIM_SOPT4_FTM0FLT2_SHIFT 2
+#define SIM_SOPT4_FTM1FLT0_MASK 0x10u
+#define SIM_SOPT4_FTM1FLT0_SHIFT 4
+#define SIM_SOPT4_FTM2FLT0_MASK 0x100u
+#define SIM_SOPT4_FTM2FLT0_SHIFT 8
+#define SIM_SOPT4_FTM3FLT0_MASK 0x1000u
+#define SIM_SOPT4_FTM3FLT0_SHIFT 12
+#define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
+#define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
+#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
+#define SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u
+#define SIM_SOPT4_FTM2CH0SRC_SHIFT 20
+#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
+#define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
+#define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
+#define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
+#define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
+#define SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u
+#define SIM_SOPT4_FTM2CLKSEL_SHIFT 26
+#define SIM_SOPT4_FTM3CLKSEL_MASK 0x8000000u
+#define SIM_SOPT4_FTM3CLKSEL_SHIFT 27
+#define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
+#define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
+#define SIM_SOPT4_FTM0TRG1SRC_MASK 0x20000000u
+#define SIM_SOPT4_FTM0TRG1SRC_SHIFT 29
+#define SIM_SOPT4_FTM3TRG0SRC_MASK 0x40000000u
+#define SIM_SOPT4_FTM3TRG0SRC_SHIFT 30
+#define SIM_SOPT4_FTM3TRG1SRC_MASK 0x80000000u
+#define SIM_SOPT4_FTM3TRG1SRC_SHIFT 31
+/* SOPT5 Bit Fields */
+#define SIM_SOPT5_UART0TXSRC_MASK 0x3u
+#define SIM_SOPT5_UART0TXSRC_SHIFT 0
+#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC_MASK 0xCu
+#define SIM_SOPT5_UART0RXSRC_SHIFT 2
+#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
+#define SIM_SOPT5_UART1TXSRC_MASK 0x30u
+#define SIM_SOPT5_UART1TXSRC_SHIFT 4
+#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
+#define SIM_SOPT5_UART1RXSRC_SHIFT 6
+#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
+/* SOPT7 Bit Fields */
+#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
+#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
+#define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u
+#define SIM_SOPT7_ADC1TRGSEL_SHIFT 8
+#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
+#define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u
+#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12
+#define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u
+#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15
+/* SDID Bit Fields */
+#define SIM_SDID_PINID_MASK 0xFu
+#define SIM_SDID_PINID_SHIFT 0
+#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
+#define SIM_SDID_FAMID_MASK 0x70u
+#define SIM_SDID_FAMID_SHIFT 4
+#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
+#define SIM_SDID_DIEID_MASK 0xF80u
+#define SIM_SDID_DIEID_SHIFT 7
+#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK 0xF000u
+#define SIM_SDID_REVID_SHIFT 12
+#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
+#define SIM_SDID_SERIESID_MASK 0xF00000u
+#define SIM_SDID_SERIESID_SHIFT 20
+#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK 0xF000000u
+#define SIM_SDID_SUBFAMID_SHIFT 24
+#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMILYID_MASK 0xF0000000u
+#define SIM_SDID_FAMILYID_SHIFT 28
+#define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMILYID_SHIFT))&SIM_SDID_FAMILYID_MASK)
+/* SCGC1 Bit Fields */
+#define SIM_SCGC1_I2C2_MASK 0x40u
+#define SIM_SCGC1_I2C2_SHIFT 6
+#define SIM_SCGC1_UART4_MASK 0x400u
+#define SIM_SCGC1_UART4_SHIFT 10
+#define SIM_SCGC1_UART5_MASK 0x800u
+#define SIM_SCGC1_UART5_SHIFT 11
+/* SCGC2 Bit Fields */
+#define SIM_SCGC2_ENET_MASK 0x1u
+#define SIM_SCGC2_ENET_SHIFT 0
+#define SIM_SCGC2_DAC0_MASK 0x1000u
+#define SIM_SCGC2_DAC0_SHIFT 12
+#define SIM_SCGC2_DAC1_MASK 0x2000u
+#define SIM_SCGC2_DAC1_SHIFT 13
+/* SCGC3 Bit Fields */
+#define SIM_SCGC3_RNGA_MASK 0x1u
+#define SIM_SCGC3_RNGA_SHIFT 0
+#define SIM_SCGC3_SPI2_MASK 0x1000u
+#define SIM_SCGC3_SPI2_SHIFT 12
+#define SIM_SCGC3_SDHC_MASK 0x20000u
+#define SIM_SCGC3_SDHC_SHIFT 17
+#define SIM_SCGC3_FTM2_MASK 0x1000000u
+#define SIM_SCGC3_FTM2_SHIFT 24
+#define SIM_SCGC3_FTM3_MASK 0x2000000u
+#define SIM_SCGC3_FTM3_SHIFT 25
+#define SIM_SCGC3_ADC1_MASK 0x8000000u
+#define SIM_SCGC3_ADC1_SHIFT 27
+/* SCGC4 Bit Fields */
+#define SIM_SCGC4_EWM_MASK 0x2u
+#define SIM_SCGC4_EWM_SHIFT 1
+#define SIM_SCGC4_CMT_MASK 0x4u
+#define SIM_SCGC4_CMT_SHIFT 2
+#define SIM_SCGC4_I2C0_MASK 0x40u
+#define SIM_SCGC4_I2C0_SHIFT 6
+#define SIM_SCGC4_I2C1_MASK 0x80u
+#define SIM_SCGC4_I2C1_SHIFT 7
+#define SIM_SCGC4_UART0_MASK 0x400u
+#define SIM_SCGC4_UART0_SHIFT 10
+#define SIM_SCGC4_UART1_MASK 0x800u
+#define SIM_SCGC4_UART1_SHIFT 11
+#define SIM_SCGC4_UART2_MASK 0x1000u
+#define SIM_SCGC4_UART2_SHIFT 12
+#define SIM_SCGC4_UART3_MASK 0x2000u
+#define SIM_SCGC4_UART3_SHIFT 13
+#define SIM_SCGC4_USBOTG_MASK 0x40000u
+#define SIM_SCGC4_USBOTG_SHIFT 18
+#define SIM_SCGC4_CMP_MASK 0x80000u
+#define SIM_SCGC4_CMP_SHIFT 19
+#define SIM_SCGC4_VREF_MASK 0x100000u
+#define SIM_SCGC4_VREF_SHIFT 20
+/* SCGC5 Bit Fields */
+#define SIM_SCGC5_LPTMR_MASK 0x1u
+#define SIM_SCGC5_LPTMR_SHIFT 0
+#define SIM_SCGC5_PORTA_MASK 0x200u
+#define SIM_SCGC5_PORTA_SHIFT 9
+#define SIM_SCGC5_PORTB_MASK 0x400u
+#define SIM_SCGC5_PORTB_SHIFT 10
+#define SIM_SCGC5_PORTC_MASK 0x800u
+#define SIM_SCGC5_PORTC_SHIFT 11
+#define SIM_SCGC5_PORTD_MASK 0x1000u
+#define SIM_SCGC5_PORTD_SHIFT 12
+#define SIM_SCGC5_PORTE_MASK 0x2000u
+#define SIM_SCGC5_PORTE_SHIFT 13
+/* SCGC6 Bit Fields */
+#define SIM_SCGC6_FTF_MASK 0x1u
+#define SIM_SCGC6_FTF_SHIFT 0
+#define SIM_SCGC6_DMAMUX_MASK 0x2u
+#define SIM_SCGC6_DMAMUX_SHIFT 1
+#define SIM_SCGC6_FLEXCAN0_MASK 0x10u
+#define SIM_SCGC6_FLEXCAN0_SHIFT 4
+#define SIM_SCGC6_RNGA_MASK 0x200u
+#define SIM_SCGC6_RNGA_SHIFT 9
+#define SIM_SCGC6_SPI0_MASK 0x1000u
+#define SIM_SCGC6_SPI0_SHIFT 12
+#define SIM_SCGC6_SPI1_MASK 0x2000u
+#define SIM_SCGC6_SPI1_SHIFT 13
+#define SIM_SCGC6_I2S_MASK 0x8000u
+#define SIM_SCGC6_I2S_SHIFT 15
+#define SIM_SCGC6_CRC_MASK 0x40000u
+#define SIM_SCGC6_CRC_SHIFT 18
+#define SIM_SCGC6_USBDCD_MASK 0x200000u
+#define SIM_SCGC6_USBDCD_SHIFT 21
+#define SIM_SCGC6_PDB_MASK 0x400000u
+#define SIM_SCGC6_PDB_SHIFT 22
+#define SIM_SCGC6_PIT_MASK 0x800000u
+#define SIM_SCGC6_PIT_SHIFT 23
+#define SIM_SCGC6_FTM0_MASK 0x1000000u
+#define SIM_SCGC6_FTM0_SHIFT 24
+#define SIM_SCGC6_FTM1_MASK 0x2000000u
+#define SIM_SCGC6_FTM1_SHIFT 25
+#define SIM_SCGC6_FTM2_MASK 0x4000000u
+#define SIM_SCGC6_FTM2_SHIFT 26
+#define SIM_SCGC6_ADC0_MASK 0x8000000u
+#define SIM_SCGC6_ADC0_SHIFT 27
+#define SIM_SCGC6_RTC_MASK 0x20000000u
+#define SIM_SCGC6_RTC_SHIFT 29
+#define SIM_SCGC6_DAC0_MASK 0x80000000u
+#define SIM_SCGC6_DAC0_SHIFT 31
+/* SCGC7 Bit Fields */
+#define SIM_SCGC7_FLEXBUS_MASK 0x1u
+#define SIM_SCGC7_FLEXBUS_SHIFT 0
+#define SIM_SCGC7_DMA_MASK 0x2u
+#define SIM_SCGC7_DMA_SHIFT 1
+#define SIM_SCGC7_MPU_MASK 0x4u
+#define SIM_SCGC7_MPU_SHIFT 2
+/* CLKDIV1 Bit Fields */
+#define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
+#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
+#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV3_MASK 0xF00000u
+#define SIM_CLKDIV1_OUTDIV3_SHIFT 20
+#define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
+#define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
+#define SIM_CLKDIV1_OUTDIV2_SHIFT 24
+#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
+#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
+#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
+/* CLKDIV2 Bit Fields */
+#define SIM_CLKDIV2_USBFRAC_MASK 0x1u
+#define SIM_CLKDIV2_USBFRAC_SHIFT 0
+#define SIM_CLKDIV2_USBDIV_MASK 0xEu
+#define SIM_CLKDIV2_USBDIV_SHIFT 1
+#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
+/* FCFG1 Bit Fields */
+#define SIM_FCFG1_FLASHDIS_MASK 0x1u
+#define SIM_FCFG1_FLASHDIS_SHIFT 0
+#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
+#define SIM_FCFG1_FLASHDOZE_SHIFT 1
+#define SIM_FCFG1_DEPART_MASK 0xF00u
+#define SIM_FCFG1_DEPART_SHIFT 8
+#define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
+#define SIM_FCFG1_EESIZE_MASK 0xF0000u
+#define SIM_FCFG1_EESIZE_SHIFT 16
+#define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
+#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
+#define SIM_FCFG1_PFSIZE_SHIFT 24
+#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
+#define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u
+#define SIM_FCFG1_NVMSIZE_SHIFT 28
+#define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
+/* FCFG2 Bit Fields */
+#define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
+#define SIM_FCFG2_MAXADDR1_SHIFT 16
+#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_PFLSH_MASK 0x800000u
+#define SIM_FCFG2_PFLSH_SHIFT 23
+#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
+#define SIM_FCFG2_MAXADDR0_SHIFT 24
+#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
+/* UIDH Bit Fields */
+#define SIM_UIDH_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDH_UID_SHIFT 0
+#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
+/* UIDMH Bit Fields */
+#define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDMH_UID_SHIFT 0
+#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
+/* UIDML Bit Fields */
+#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDML_UID_SHIFT 0
+#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
+/* UIDL Bit Fields */
+#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDL_UID_SHIFT 0
+#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM ((SIM_Type *)SIM_BASE)
+#define SIM_BASE_PTR (SIM)
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASES { SIM }
+
+/* ----------------------------------------------------------------------------
+ -- SIM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
+ * @{
+ */
+
+
+/* SIM - Register instance definitions */
+/* SIM */
+#define SIM_SOPT1 SIM_SOPT1_REG(SIM)
+#define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM)
+#define SIM_SOPT2 SIM_SOPT2_REG(SIM)
+#define SIM_SOPT4 SIM_SOPT4_REG(SIM)
+#define SIM_SOPT5 SIM_SOPT5_REG(SIM)
+#define SIM_SOPT7 SIM_SOPT7_REG(SIM)
+#define SIM_SDID SIM_SDID_REG(SIM)
+#define SIM_SCGC1 SIM_SCGC1_REG(SIM)
+#define SIM_SCGC2 SIM_SCGC2_REG(SIM)
+#define SIM_SCGC3 SIM_SCGC3_REG(SIM)
+#define SIM_SCGC4 SIM_SCGC4_REG(SIM)
+#define SIM_SCGC5 SIM_SCGC5_REG(SIM)
+#define SIM_SCGC6 SIM_SCGC6_REG(SIM)
+#define SIM_SCGC7 SIM_SCGC7_REG(SIM)
+#define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM)
+#define SIM_CLKDIV2 SIM_CLKDIV2_REG(SIM)
+#define SIM_FCFG1 SIM_FCFG1_REG(SIM)
+#define SIM_FCFG2 SIM_FCFG2_REG(SIM)
+#define SIM_UIDH SIM_UIDH_REG(SIM)
+#define SIM_UIDMH SIM_UIDMH_REG(SIM)
+#define SIM_UIDML SIM_UIDML_REG(SIM)
+#define SIM_UIDL SIM_UIDL_REG(SIM)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
+ __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
+ __IO uint8_t VLLSCTRL; /**< VLLS Control register, offset: 0x2 */
+ __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
+} SMC_Type, *SMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- SMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
+ * @{
+ */
+
+
+/* SMC - Register accessors */
+#define SMC_PMPROT_REG(base) ((base)->PMPROT)
+#define SMC_PMCTRL_REG(base) ((base)->PMCTRL)
+#define SMC_VLLSCTRL_REG(base) ((base)->VLLSCTRL)
+#define SMC_PMSTAT_REG(base) ((base)->PMSTAT)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/* PMPROT Bit Fields */
+#define SMC_PMPROT_AVLLS_MASK 0x2u
+#define SMC_PMPROT_AVLLS_SHIFT 1
+#define SMC_PMPROT_ALLS_MASK 0x8u
+#define SMC_PMPROT_ALLS_SHIFT 3
+#define SMC_PMPROT_AVLP_MASK 0x20u
+#define SMC_PMPROT_AVLP_SHIFT 5
+/* PMCTRL Bit Fields */
+#define SMC_PMCTRL_STOPM_MASK 0x7u
+#define SMC_PMCTRL_STOPM_SHIFT 0
+#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK 0x8u
+#define SMC_PMCTRL_STOPA_SHIFT 3
+#define SMC_PMCTRL_RUNM_MASK 0x60u
+#define SMC_PMCTRL_RUNM_SHIFT 5
+#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
+#define SMC_PMCTRL_LPWUI_MASK 0x80u
+#define SMC_PMCTRL_LPWUI_SHIFT 7
+/* VLLSCTRL Bit Fields */
+#define SMC_VLLSCTRL_VLLSM_MASK 0x7u
+#define SMC_VLLSCTRL_VLLSM_SHIFT 0
+#define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
+#define SMC_VLLSCTRL_PORPO_MASK 0x20u
+#define SMC_VLLSCTRL_PORPO_SHIFT 5
+/* PMSTAT Bit Fields */
+#define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
+#define SMC_PMSTAT_PMSTAT_SHIFT 0
+#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC ((SMC_Type *)SMC_BASE)
+#define SMC_BASE_PTR (SMC)
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASES { SMC }
+
+/* ----------------------------------------------------------------------------
+ -- SMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
+ * @{
+ */
+
+
+/* SMC - Register instance definitions */
+/* SMC */
+#define SMC_PMPROT SMC_PMPROT_REG(SMC)
+#define SMC_PMCTRL SMC_PMCTRL_REG(SMC)
+#define SMC_VLLSCTRL SMC_VLLSCTRL_REG(SMC)
+#define SMC_PMSTAT SMC_PMSTAT_REG(SMC)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
+ union { /* offset: 0xC */
+ __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
+ __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
+ };
+ uint8_t RESERVED_1[24];
+ __IO uint32_t SR; /**< Status Register, offset: 0x2C */
+ __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
+ union { /* offset: 0x34 */
+ __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
+ __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
+ };
+ __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
+ __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */
+ __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */
+ __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */
+ __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */
+ uint8_t RESERVED_2[48];
+ __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */
+ __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
+ __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
+ __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
+} SPI_Type, *SPI_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- SPI - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @{
+ */
+
+
+/* SPI - Register accessors */
+#define SPI_MCR_REG(base) ((base)->MCR)
+#define SPI_TCR_REG(base) ((base)->TCR)
+#define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2])
+#define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2])
+#define SPI_SR_REG(base) ((base)->SR)
+#define SPI_RSER_REG(base) ((base)->RSER)
+#define SPI_PUSHR_REG(base) ((base)->PUSHR)
+#define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE)
+#define SPI_POPR_REG(base) ((base)->POPR)
+#define SPI_TXFR0_REG(base) ((base)->TXFR0)
+#define SPI_TXFR1_REG(base) ((base)->TXFR1)
+#define SPI_TXFR2_REG(base) ((base)->TXFR2)
+#define SPI_TXFR3_REG(base) ((base)->TXFR3)
+#define SPI_RXFR0_REG(base) ((base)->RXFR0)
+#define SPI_RXFR1_REG(base) ((base)->RXFR1)
+#define SPI_RXFR2_REG(base) ((base)->RXFR2)
+#define SPI_RXFR3_REG(base) ((base)->RXFR3)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define SPI_MCR_HALT_MASK 0x1u
+#define SPI_MCR_HALT_SHIFT 0
+#define SPI_MCR_SMPL_PT_MASK 0x300u
+#define SPI_MCR_SMPL_PT_SHIFT 8
+#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
+#define SPI_MCR_CLR_RXF_MASK 0x400u
+#define SPI_MCR_CLR_RXF_SHIFT 10
+#define SPI_MCR_CLR_TXF_MASK 0x800u
+#define SPI_MCR_CLR_TXF_SHIFT 11
+#define SPI_MCR_DIS_RXF_MASK 0x1000u
+#define SPI_MCR_DIS_RXF_SHIFT 12
+#define SPI_MCR_DIS_TXF_MASK 0x2000u
+#define SPI_MCR_DIS_TXF_SHIFT 13
+#define SPI_MCR_MDIS_MASK 0x4000u
+#define SPI_MCR_MDIS_SHIFT 14
+#define SPI_MCR_DOZE_MASK 0x8000u
+#define SPI_MCR_DOZE_SHIFT 15
+#define SPI_MCR_PCSIS_MASK 0x3F0000u
+#define SPI_MCR_PCSIS_SHIFT 16
+#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
+#define SPI_MCR_ROOE_MASK 0x1000000u
+#define SPI_MCR_ROOE_SHIFT 24
+#define SPI_MCR_PCSSE_MASK 0x2000000u
+#define SPI_MCR_PCSSE_SHIFT 25
+#define SPI_MCR_MTFE_MASK 0x4000000u
+#define SPI_MCR_MTFE_SHIFT 26
+#define SPI_MCR_FRZ_MASK 0x8000000u
+#define SPI_MCR_FRZ_SHIFT 27
+#define SPI_MCR_DCONF_MASK 0x30000000u
+#define SPI_MCR_DCONF_SHIFT 28
+#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
+#define SPI_MCR_CONT_SCKE_MASK 0x40000000u
+#define SPI_MCR_CONT_SCKE_SHIFT 30
+#define SPI_MCR_MSTR_MASK 0x80000000u
+#define SPI_MCR_MSTR_SHIFT 31
+/* TCR Bit Fields */
+#define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
+#define SPI_TCR_SPI_TCNT_SHIFT 16
+#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
+/* CTAR Bit Fields */
+#define SPI_CTAR_BR_MASK 0xFu
+#define SPI_CTAR_BR_SHIFT 0
+#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
+#define SPI_CTAR_DT_MASK 0xF0u
+#define SPI_CTAR_DT_SHIFT 4
+#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
+#define SPI_CTAR_ASC_MASK 0xF00u
+#define SPI_CTAR_ASC_SHIFT 8
+#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
+#define SPI_CTAR_CSSCK_MASK 0xF000u
+#define SPI_CTAR_CSSCK_SHIFT 12
+#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
+#define SPI_CTAR_PBR_MASK 0x30000u
+#define SPI_CTAR_PBR_SHIFT 16
+#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
+#define SPI_CTAR_PDT_MASK 0xC0000u
+#define SPI_CTAR_PDT_SHIFT 18
+#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
+#define SPI_CTAR_PASC_MASK 0x300000u
+#define SPI_CTAR_PASC_SHIFT 20
+#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
+#define SPI_CTAR_PCSSCK_MASK 0xC00000u
+#define SPI_CTAR_PCSSCK_SHIFT 22
+#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
+#define SPI_CTAR_LSBFE_MASK 0x1000000u
+#define SPI_CTAR_LSBFE_SHIFT 24
+#define SPI_CTAR_CPHA_MASK 0x2000000u
+#define SPI_CTAR_CPHA_SHIFT 25
+#define SPI_CTAR_CPOL_MASK 0x4000000u
+#define SPI_CTAR_CPOL_SHIFT 26
+#define SPI_CTAR_FMSZ_MASK 0x78000000u
+#define SPI_CTAR_FMSZ_SHIFT 27
+#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
+#define SPI_CTAR_DBR_MASK 0x80000000u
+#define SPI_CTAR_DBR_SHIFT 31
+/* CTAR_SLAVE Bit Fields */
+#define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
+#define SPI_CTAR_SLAVE_CPHA_SHIFT 25
+#define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
+#define SPI_CTAR_SLAVE_CPOL_SHIFT 26
+#define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
+#define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
+#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
+/* SR Bit Fields */
+#define SPI_SR_POPNXTPTR_MASK 0xFu
+#define SPI_SR_POPNXTPTR_SHIFT 0
+#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
+#define SPI_SR_RXCTR_MASK 0xF0u
+#define SPI_SR_RXCTR_SHIFT 4
+#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
+#define SPI_SR_TXNXTPTR_MASK 0xF00u
+#define SPI_SR_TXNXTPTR_SHIFT 8
+#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
+#define SPI_SR_TXCTR_MASK 0xF000u
+#define SPI_SR_TXCTR_SHIFT 12
+#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
+#define SPI_SR_RFDF_MASK 0x20000u
+#define SPI_SR_RFDF_SHIFT 17
+#define SPI_SR_RFOF_MASK 0x80000u
+#define SPI_SR_RFOF_SHIFT 19
+#define SPI_SR_TFFF_MASK 0x2000000u
+#define SPI_SR_TFFF_SHIFT 25
+#define SPI_SR_TFUF_MASK 0x8000000u
+#define SPI_SR_TFUF_SHIFT 27
+#define SPI_SR_EOQF_MASK 0x10000000u
+#define SPI_SR_EOQF_SHIFT 28
+#define SPI_SR_TXRXS_MASK 0x40000000u
+#define SPI_SR_TXRXS_SHIFT 30
+#define SPI_SR_TCF_MASK 0x80000000u
+#define SPI_SR_TCF_SHIFT 31
+/* RSER Bit Fields */
+#define SPI_RSER_RFDF_DIRS_MASK 0x10000u
+#define SPI_RSER_RFDF_DIRS_SHIFT 16
+#define SPI_RSER_RFDF_RE_MASK 0x20000u
+#define SPI_RSER_RFDF_RE_SHIFT 17
+#define SPI_RSER_RFOF_RE_MASK 0x80000u
+#define SPI_RSER_RFOF_RE_SHIFT 19
+#define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
+#define SPI_RSER_TFFF_DIRS_SHIFT 24
+#define SPI_RSER_TFFF_RE_MASK 0x2000000u
+#define SPI_RSER_TFFF_RE_SHIFT 25
+#define SPI_RSER_TFUF_RE_MASK 0x8000000u
+#define SPI_RSER_TFUF_RE_SHIFT 27
+#define SPI_RSER_EOQF_RE_MASK 0x10000000u
+#define SPI_RSER_EOQF_RE_SHIFT 28
+#define SPI_RSER_TCF_RE_MASK 0x80000000u
+#define SPI_RSER_TCF_RE_SHIFT 31
+/* PUSHR Bit Fields */
+#define SPI_PUSHR_TXDATA_MASK 0xFFFFu
+#define SPI_PUSHR_TXDATA_SHIFT 0
+#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
+#define SPI_PUSHR_PCS_MASK 0x3F0000u
+#define SPI_PUSHR_PCS_SHIFT 16
+#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
+#define SPI_PUSHR_CTCNT_MASK 0x4000000u
+#define SPI_PUSHR_CTCNT_SHIFT 26
+#define SPI_PUSHR_EOQ_MASK 0x8000000u
+#define SPI_PUSHR_EOQ_SHIFT 27
+#define SPI_PUSHR_CTAS_MASK 0x70000000u
+#define SPI_PUSHR_CTAS_SHIFT 28
+#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
+#define SPI_PUSHR_CONT_MASK 0x80000000u
+#define SPI_PUSHR_CONT_SHIFT 31
+/* PUSHR_SLAVE Bit Fields */
+#define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
+#define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
+#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
+/* POPR Bit Fields */
+#define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_POPR_RXDATA_SHIFT 0
+#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
+/* TXFR0 Bit Fields */
+#define SPI_TXFR0_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR0_TXDATA_SHIFT 0
+#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
+#define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
+/* TXFR1 Bit Fields */
+#define SPI_TXFR1_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR1_TXDATA_SHIFT 0
+#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
+#define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
+/* TXFR2 Bit Fields */
+#define SPI_TXFR2_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR2_TXDATA_SHIFT 0
+#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
+#define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
+/* TXFR3 Bit Fields */
+#define SPI_TXFR3_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR3_TXDATA_SHIFT 0
+#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
+#define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
+/* RXFR0 Bit Fields */
+#define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR0_RXDATA_SHIFT 0
+#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
+/* RXFR1 Bit Fields */
+#define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR1_RXDATA_SHIFT 0
+#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
+/* RXFR2 Bit Fields */
+#define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR2_RXDATA_SHIFT 0
+#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
+/* RXFR3 Bit Fields */
+#define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR3_RXDATA_SHIFT 0
+#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE (0x4002C000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0 ((SPI_Type *)SPI0_BASE)
+#define SPI0_BASE_PTR (SPI0)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE (0x4002D000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1 ((SPI_Type *)SPI1_BASE)
+#define SPI1_BASE_PTR (SPI1)
+/** Peripheral SPI2 base address */
+#define SPI2_BASE (0x400AC000u)
+/** Peripheral SPI2 base pointer */
+#define SPI2 ((SPI_Type *)SPI2_BASE)
+#define SPI2_BASE_PTR (SPI2)
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASES { SPI0, SPI1, SPI2 }
+
+/* ----------------------------------------------------------------------------
+ -- SPI - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @{
+ */
+
+
+/* SPI - Register instance definitions */
+/* SPI0 */
+#define SPI0_MCR SPI_MCR_REG(SPI0)
+#define SPI0_TCR SPI_TCR_REG(SPI0)
+#define SPI0_CTAR0 SPI_CTAR_REG(SPI0,0)
+#define SPI0_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI0,0)
+#define SPI0_CTAR1 SPI_CTAR_REG(SPI0,1)
+#define SPI0_SR SPI_SR_REG(SPI0)
+#define SPI0_RSER SPI_RSER_REG(SPI0)
+#define SPI0_PUSHR SPI_PUSHR_REG(SPI0)
+#define SPI0_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI0)
+#define SPI0_POPR SPI_POPR_REG(SPI0)
+#define SPI0_TXFR0 SPI_TXFR0_REG(SPI0)
+#define SPI0_TXFR1 SPI_TXFR1_REG(SPI0)
+#define SPI0_TXFR2 SPI_TXFR2_REG(SPI0)
+#define SPI0_TXFR3 SPI_TXFR3_REG(SPI0)
+#define SPI0_RXFR0 SPI_RXFR0_REG(SPI0)
+#define SPI0_RXFR1 SPI_RXFR1_REG(SPI0)
+#define SPI0_RXFR2 SPI_RXFR2_REG(SPI0)
+#define SPI0_RXFR3 SPI_RXFR3_REG(SPI0)
+/* SPI1 */
+#define SPI1_MCR SPI_MCR_REG(SPI1)
+#define SPI1_TCR SPI_TCR_REG(SPI1)
+#define SPI1_CTAR0 SPI_CTAR_REG(SPI1,0)
+#define SPI1_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI1,0)
+#define SPI1_CTAR1 SPI_CTAR_REG(SPI1,1)
+#define SPI1_SR SPI_SR_REG(SPI1)
+#define SPI1_RSER SPI_RSER_REG(SPI1)
+#define SPI1_PUSHR SPI_PUSHR_REG(SPI1)
+#define SPI1_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI1)
+#define SPI1_POPR SPI_POPR_REG(SPI1)
+#define SPI1_TXFR0 SPI_TXFR0_REG(SPI1)
+#define SPI1_TXFR1 SPI_TXFR1_REG(SPI1)
+#define SPI1_TXFR2 SPI_TXFR2_REG(SPI1)
+#define SPI1_TXFR3 SPI_TXFR3_REG(SPI1)
+#define SPI1_RXFR0 SPI_RXFR0_REG(SPI1)
+#define SPI1_RXFR1 SPI_RXFR1_REG(SPI1)
+#define SPI1_RXFR2 SPI_RXFR2_REG(SPI1)
+#define SPI1_RXFR3 SPI_RXFR3_REG(SPI1)
+/* SPI2 */
+#define SPI2_MCR SPI_MCR_REG(SPI2)
+#define SPI2_TCR SPI_TCR_REG(SPI2)
+#define SPI2_CTAR0 SPI_CTAR_REG(SPI2,0)
+#define SPI2_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI2,0)
+#define SPI2_CTAR1 SPI_CTAR_REG(SPI2,1)
+#define SPI2_SR SPI_SR_REG(SPI2)
+#define SPI2_RSER SPI_RSER_REG(SPI2)
+#define SPI2_PUSHR SPI_PUSHR_REG(SPI2)
+#define SPI2_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI2)
+#define SPI2_POPR SPI_POPR_REG(SPI2)
+#define SPI2_TXFR0 SPI_TXFR0_REG(SPI2)
+#define SPI2_TXFR1 SPI_TXFR1_REG(SPI2)
+#define SPI2_TXFR2 SPI_TXFR2_REG(SPI2)
+#define SPI2_TXFR3 SPI_TXFR3_REG(SPI2)
+#define SPI2_RXFR0 SPI_RXFR0_REG(SPI2)
+#define SPI2_RXFR1 SPI_RXFR1_REG(SPI2)
+#define SPI2_RXFR2 SPI_RXFR2_REG(SPI2)
+#define SPI2_RXFR3 SPI_RXFR3_REG(SPI2)
+
+/* SPI - Register array accessors */
+#define SPI0_CTAR(index2) SPI_CTAR_REG(SPI0,index2)
+#define SPI1_CTAR(index2) SPI_CTAR_REG(SPI1,index2)
+#define SPI2_CTAR(index2) SPI_CTAR_REG(SPI2,index2)
+#define SPI0_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI0,index2)
+#define SPI1_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI1,index2)
+#define SPI2_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI2,index2)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
+ __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
+ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
+ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
+ __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
+ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
+ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
+ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
+ __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
+ __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
+ __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
+ __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
+ __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
+ __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
+ __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
+ __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
+ __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
+ __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
+ __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
+ __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
+ __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
+ __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
+ __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
+ union { /* offset: 0x1B */
+ __IO uint8_t WP7816_T_TYPE0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+ __IO uint8_t WP7816_T_TYPE1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+ };
+ __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
+ __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
+ __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
+ __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
+} UART_Type, *UART_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- UART - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
+ * @{
+ */
+
+
+/* UART - Register accessors */
+#define UART_BDH_REG(base) ((base)->BDH)
+#define UART_BDL_REG(base) ((base)->BDL)
+#define UART_C1_REG(base) ((base)->C1)
+#define UART_C2_REG(base) ((base)->C2)
+#define UART_S1_REG(base) ((base)->S1)
+#define UART_S2_REG(base) ((base)->S2)
+#define UART_C3_REG(base) ((base)->C3)
+#define UART_D_REG(base) ((base)->D)
+#define UART_MA1_REG(base) ((base)->MA1)
+#define UART_MA2_REG(base) ((base)->MA2)
+#define UART_C4_REG(base) ((base)->C4)
+#define UART_C5_REG(base) ((base)->C5)
+#define UART_ED_REG(base) ((base)->ED)
+#define UART_MODEM_REG(base) ((base)->MODEM)
+#define UART_IR_REG(base) ((base)->IR)
+#define UART_PFIFO_REG(base) ((base)->PFIFO)
+#define UART_CFIFO_REG(base) ((base)->CFIFO)
+#define UART_SFIFO_REG(base) ((base)->SFIFO)
+#define UART_TWFIFO_REG(base) ((base)->TWFIFO)
+#define UART_TCFIFO_REG(base) ((base)->TCFIFO)
+#define UART_RWFIFO_REG(base) ((base)->RWFIFO)
+#define UART_RCFIFO_REG(base) ((base)->RCFIFO)
+#define UART_C7816_REG(base) ((base)->C7816)
+#define UART_IE7816_REG(base) ((base)->IE7816)
+#define UART_IS7816_REG(base) ((base)->IS7816)
+#define UART_WP7816_T_TYPE0_REG(base) ((base)->WP7816_T_TYPE0)
+#define UART_WP7816_T_TYPE1_REG(base) ((base)->WP7816_T_TYPE1)
+#define UART_WN7816_REG(base) ((base)->WN7816)
+#define UART_WF7816_REG(base) ((base)->WF7816)
+#define UART_ET7816_REG(base) ((base)->ET7816)
+#define UART_TL7816_REG(base) ((base)->TL7816)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART_BDH_SBR_MASK 0x1Fu
+#define UART_BDH_SBR_SHIFT 0
+#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
+#define UART_BDH_SBNS_MASK 0x20u
+#define UART_BDH_SBNS_SHIFT 5
+#define UART_BDH_RXEDGIE_MASK 0x40u
+#define UART_BDH_RXEDGIE_SHIFT 6
+#define UART_BDH_LBKDIE_MASK 0x80u
+#define UART_BDH_LBKDIE_SHIFT 7
+/* BDL Bit Fields */
+#define UART_BDL_SBR_MASK 0xFFu
+#define UART_BDL_SBR_SHIFT 0
+#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART_C1_PT_MASK 0x1u
+#define UART_C1_PT_SHIFT 0
+#define UART_C1_PE_MASK 0x2u
+#define UART_C1_PE_SHIFT 1
+#define UART_C1_ILT_MASK 0x4u
+#define UART_C1_ILT_SHIFT 2
+#define UART_C1_WAKE_MASK 0x8u
+#define UART_C1_WAKE_SHIFT 3
+#define UART_C1_M_MASK 0x10u
+#define UART_C1_M_SHIFT 4
+#define UART_C1_RSRC_MASK 0x20u
+#define UART_C1_RSRC_SHIFT 5
+#define UART_C1_UARTSWAI_MASK 0x40u
+#define UART_C1_UARTSWAI_SHIFT 6
+#define UART_C1_LOOPS_MASK 0x80u
+#define UART_C1_LOOPS_SHIFT 7
+/* C2 Bit Fields */
+#define UART_C2_SBK_MASK 0x1u
+#define UART_C2_SBK_SHIFT 0
+#define UART_C2_RWU_MASK 0x2u
+#define UART_C2_RWU_SHIFT 1
+#define UART_C2_RE_MASK 0x4u
+#define UART_C2_RE_SHIFT 2
+#define UART_C2_TE_MASK 0x8u
+#define UART_C2_TE_SHIFT 3
+#define UART_C2_ILIE_MASK 0x10u
+#define UART_C2_ILIE_SHIFT 4
+#define UART_C2_RIE_MASK 0x20u
+#define UART_C2_RIE_SHIFT 5
+#define UART_C2_TCIE_MASK 0x40u
+#define UART_C2_TCIE_SHIFT 6
+#define UART_C2_TIE_MASK 0x80u
+#define UART_C2_TIE_SHIFT 7
+/* S1 Bit Fields */
+#define UART_S1_PF_MASK 0x1u
+#define UART_S1_PF_SHIFT 0
+#define UART_S1_FE_MASK 0x2u
+#define UART_S1_FE_SHIFT 1
+#define UART_S1_NF_MASK 0x4u
+#define UART_S1_NF_SHIFT 2
+#define UART_S1_OR_MASK 0x8u
+#define UART_S1_OR_SHIFT 3
+#define UART_S1_IDLE_MASK 0x10u
+#define UART_S1_IDLE_SHIFT 4
+#define UART_S1_RDRF_MASK 0x20u
+#define UART_S1_RDRF_SHIFT 5
+#define UART_S1_TC_MASK 0x40u
+#define UART_S1_TC_SHIFT 6
+#define UART_S1_TDRE_MASK 0x80u
+#define UART_S1_TDRE_SHIFT 7
+/* S2 Bit Fields */
+#define UART_S2_RAF_MASK 0x1u
+#define UART_S2_RAF_SHIFT 0
+#define UART_S2_LBKDE_MASK 0x2u
+#define UART_S2_LBKDE_SHIFT 1
+#define UART_S2_BRK13_MASK 0x4u
+#define UART_S2_BRK13_SHIFT 2
+#define UART_S2_RWUID_MASK 0x8u
+#define UART_S2_RWUID_SHIFT 3
+#define UART_S2_RXINV_MASK 0x10u
+#define UART_S2_RXINV_SHIFT 4
+#define UART_S2_MSBF_MASK 0x20u
+#define UART_S2_MSBF_SHIFT 5
+#define UART_S2_RXEDGIF_MASK 0x40u
+#define UART_S2_RXEDGIF_SHIFT 6
+#define UART_S2_LBKDIF_MASK 0x80u
+#define UART_S2_LBKDIF_SHIFT 7
+/* C3 Bit Fields */
+#define UART_C3_PEIE_MASK 0x1u
+#define UART_C3_PEIE_SHIFT 0
+#define UART_C3_FEIE_MASK 0x2u
+#define UART_C3_FEIE_SHIFT 1
+#define UART_C3_NEIE_MASK 0x4u
+#define UART_C3_NEIE_SHIFT 2
+#define UART_C3_ORIE_MASK 0x8u
+#define UART_C3_ORIE_SHIFT 3
+#define UART_C3_TXINV_MASK 0x10u
+#define UART_C3_TXINV_SHIFT 4
+#define UART_C3_TXDIR_MASK 0x20u
+#define UART_C3_TXDIR_SHIFT 5
+#define UART_C3_T8_MASK 0x40u
+#define UART_C3_T8_SHIFT 6
+#define UART_C3_R8_MASK 0x80u
+#define UART_C3_R8_SHIFT 7
+/* D Bit Fields */
+#define UART_D_RT_MASK 0xFFu
+#define UART_D_RT_SHIFT 0
+#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
+/* MA1 Bit Fields */
+#define UART_MA1_MA_MASK 0xFFu
+#define UART_MA1_MA_SHIFT 0
+#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
+/* MA2 Bit Fields */
+#define UART_MA2_MA_MASK 0xFFu
+#define UART_MA2_MA_SHIFT 0
+#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
+/* C4 Bit Fields */
+#define UART_C4_BRFA_MASK 0x1Fu
+#define UART_C4_BRFA_SHIFT 0
+#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
+#define UART_C4_M10_MASK 0x20u
+#define UART_C4_M10_SHIFT 5
+#define UART_C4_MAEN2_MASK 0x40u
+#define UART_C4_MAEN2_SHIFT 6
+#define UART_C4_MAEN1_MASK 0x80u
+#define UART_C4_MAEN1_SHIFT 7
+/* C5 Bit Fields */
+#define UART_C5_LBKDDMAS_MASK 0x8u
+#define UART_C5_LBKDDMAS_SHIFT 3
+#define UART_C5_ILDMAS_MASK 0x10u
+#define UART_C5_ILDMAS_SHIFT 4
+#define UART_C5_RDMAS_MASK 0x20u
+#define UART_C5_RDMAS_SHIFT 5
+#define UART_C5_TCDMAS_MASK 0x40u
+#define UART_C5_TCDMAS_SHIFT 6
+#define UART_C5_TDMAS_MASK 0x80u
+#define UART_C5_TDMAS_SHIFT 7
+/* ED Bit Fields */
+#define UART_ED_PARITYE_MASK 0x40u
+#define UART_ED_PARITYE_SHIFT 6
+#define UART_ED_NOISY_MASK 0x80u
+#define UART_ED_NOISY_SHIFT 7
+/* MODEM Bit Fields */
+#define UART_MODEM_TXCTSE_MASK 0x1u
+#define UART_MODEM_TXCTSE_SHIFT 0
+#define UART_MODEM_TXRTSE_MASK 0x2u
+#define UART_MODEM_TXRTSE_SHIFT 1
+#define UART_MODEM_TXRTSPOL_MASK 0x4u
+#define UART_MODEM_TXRTSPOL_SHIFT 2
+#define UART_MODEM_RXRTSE_MASK 0x8u
+#define UART_MODEM_RXRTSE_SHIFT 3
+/* IR Bit Fields */
+#define UART_IR_TNP_MASK 0x3u
+#define UART_IR_TNP_SHIFT 0
+#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
+#define UART_IR_IREN_MASK 0x4u
+#define UART_IR_IREN_SHIFT 2
+/* PFIFO Bit Fields */
+#define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
+#define UART_PFIFO_RXFIFOSIZE_SHIFT 0
+#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
+#define UART_PFIFO_RXFE_MASK 0x8u
+#define UART_PFIFO_RXFE_SHIFT 3
+#define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
+#define UART_PFIFO_TXFIFOSIZE_SHIFT 4
+#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
+#define UART_PFIFO_TXFE_MASK 0x80u
+#define UART_PFIFO_TXFE_SHIFT 7
+/* CFIFO Bit Fields */
+#define UART_CFIFO_RXUFE_MASK 0x1u
+#define UART_CFIFO_RXUFE_SHIFT 0
+#define UART_CFIFO_TXOFE_MASK 0x2u
+#define UART_CFIFO_TXOFE_SHIFT 1
+#define UART_CFIFO_RXOFE_MASK 0x4u
+#define UART_CFIFO_RXOFE_SHIFT 2
+#define UART_CFIFO_RXFLUSH_MASK 0x40u
+#define UART_CFIFO_RXFLUSH_SHIFT 6
+#define UART_CFIFO_TXFLUSH_MASK 0x80u
+#define UART_CFIFO_TXFLUSH_SHIFT 7
+/* SFIFO Bit Fields */
+#define UART_SFIFO_RXUF_MASK 0x1u
+#define UART_SFIFO_RXUF_SHIFT 0
+#define UART_SFIFO_TXOF_MASK 0x2u
+#define UART_SFIFO_TXOF_SHIFT 1
+#define UART_SFIFO_RXOF_MASK 0x4u
+#define UART_SFIFO_RXOF_SHIFT 2
+#define UART_SFIFO_RXEMPT_MASK 0x40u
+#define UART_SFIFO_RXEMPT_SHIFT 6
+#define UART_SFIFO_TXEMPT_MASK 0x80u
+#define UART_SFIFO_TXEMPT_SHIFT 7
+/* TWFIFO Bit Fields */
+#define UART_TWFIFO_TXWATER_MASK 0xFFu
+#define UART_TWFIFO_TXWATER_SHIFT 0
+#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
+/* TCFIFO Bit Fields */
+#define UART_TCFIFO_TXCOUNT_MASK 0xFFu
+#define UART_TCFIFO_TXCOUNT_SHIFT 0
+#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
+/* RWFIFO Bit Fields */
+#define UART_RWFIFO_RXWATER_MASK 0xFFu
+#define UART_RWFIFO_RXWATER_SHIFT 0
+#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
+/* RCFIFO Bit Fields */
+#define UART_RCFIFO_RXCOUNT_MASK 0xFFu
+#define UART_RCFIFO_RXCOUNT_SHIFT 0
+#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
+/* C7816 Bit Fields */
+#define UART_C7816_ISO_7816E_MASK 0x1u
+#define UART_C7816_ISO_7816E_SHIFT 0
+#define UART_C7816_TTYPE_MASK 0x2u
+#define UART_C7816_TTYPE_SHIFT 1
+#define UART_C7816_INIT_MASK 0x4u
+#define UART_C7816_INIT_SHIFT 2
+#define UART_C7816_ANACK_MASK 0x8u
+#define UART_C7816_ANACK_SHIFT 3
+#define UART_C7816_ONACK_MASK 0x10u
+#define UART_C7816_ONACK_SHIFT 4
+/* IE7816 Bit Fields */
+#define UART_IE7816_RXTE_MASK 0x1u
+#define UART_IE7816_RXTE_SHIFT 0
+#define UART_IE7816_TXTE_MASK 0x2u
+#define UART_IE7816_TXTE_SHIFT 1
+#define UART_IE7816_GTVE_MASK 0x4u
+#define UART_IE7816_GTVE_SHIFT 2
+#define UART_IE7816_INITDE_MASK 0x10u
+#define UART_IE7816_INITDE_SHIFT 4
+#define UART_IE7816_BWTE_MASK 0x20u
+#define UART_IE7816_BWTE_SHIFT 5
+#define UART_IE7816_CWTE_MASK 0x40u
+#define UART_IE7816_CWTE_SHIFT 6
+#define UART_IE7816_WTE_MASK 0x80u
+#define UART_IE7816_WTE_SHIFT 7
+/* IS7816 Bit Fields */
+#define UART_IS7816_RXT_MASK 0x1u
+#define UART_IS7816_RXT_SHIFT 0
+#define UART_IS7816_TXT_MASK 0x2u
+#define UART_IS7816_TXT_SHIFT 1
+#define UART_IS7816_GTV_MASK 0x4u
+#define UART_IS7816_GTV_SHIFT 2
+#define UART_IS7816_INITD_MASK 0x10u
+#define UART_IS7816_INITD_SHIFT 4
+#define UART_IS7816_BWT_MASK 0x20u
+#define UART_IS7816_BWT_SHIFT 5
+#define UART_IS7816_CWT_MASK 0x40u
+#define UART_IS7816_CWT_SHIFT 6
+#define UART_IS7816_WT_MASK 0x80u
+#define UART_IS7816_WT_SHIFT 7
+/* WP7816_T_TYPE0 Bit Fields */
+#define UART_WP7816_T_TYPE0_WI_MASK 0xFFu
+#define UART_WP7816_T_TYPE0_WI_SHIFT 0
+#define UART_WP7816_T_TYPE0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE0_WI_SHIFT))&UART_WP7816_T_TYPE0_WI_MASK)
+/* WP7816_T_TYPE1 Bit Fields */
+#define UART_WP7816_T_TYPE1_BWI_MASK 0xFu
+#define UART_WP7816_T_TYPE1_BWI_SHIFT 0
+#define UART_WP7816_T_TYPE1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_BWI_SHIFT))&UART_WP7816_T_TYPE1_BWI_MASK)
+#define UART_WP7816_T_TYPE1_CWI_MASK 0xF0u
+#define UART_WP7816_T_TYPE1_CWI_SHIFT 4
+#define UART_WP7816_T_TYPE1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_CWI_SHIFT))&UART_WP7816_T_TYPE1_CWI_MASK)
+/* WN7816 Bit Fields */
+#define UART_WN7816_GTN_MASK 0xFFu
+#define UART_WN7816_GTN_SHIFT 0
+#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
+/* WF7816 Bit Fields */
+#define UART_WF7816_GTFD_MASK 0xFFu
+#define UART_WF7816_GTFD_SHIFT 0
+#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
+/* ET7816 Bit Fields */
+#define UART_ET7816_RXTHRESHOLD_MASK 0xFu
+#define UART_ET7816_RXTHRESHOLD_SHIFT 0
+#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
+#define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
+#define UART_ET7816_TXTHRESHOLD_SHIFT 4
+#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
+/* TL7816 Bit Fields */
+#define UART_TL7816_TLEN_MASK 0xFFu
+#define UART_TL7816_TLEN_SHIFT 0
+#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0 ((UART_Type *)UART0_BASE)
+#define UART0_BASE_PTR (UART0)
+/** Peripheral UART1 base address */
+#define UART1_BASE (0x4006B000u)
+/** Peripheral UART1 base pointer */
+#define UART1 ((UART_Type *)UART1_BASE)
+#define UART1_BASE_PTR (UART1)
+/** Peripheral UART2 base address */
+#define UART2_BASE (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2 ((UART_Type *)UART2_BASE)
+#define UART2_BASE_PTR (UART2)
+/** Peripheral UART3 base address */
+#define UART3_BASE (0x4006D000u)
+/** Peripheral UART3 base pointer */
+#define UART3 ((UART_Type *)UART3_BASE)
+#define UART3_BASE_PTR (UART3)
+/** Peripheral UART4 base address */
+#define UART4_BASE (0x400EA000u)
+/** Peripheral UART4 base pointer */
+#define UART4 ((UART_Type *)UART4_BASE)
+#define UART4_BASE_PTR (UART4)
+/** Peripheral UART5 base address */
+#define UART5_BASE (0x400EB000u)
+/** Peripheral UART5 base pointer */
+#define UART5 ((UART_Type *)UART5_BASE)
+#define UART5_BASE_PTR (UART5)
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASES { UART0, UART1, UART2, UART3, UART4, UART5 }
+
+/* ----------------------------------------------------------------------------
+ -- UART - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
+ * @{
+ */
+
+
+/* UART - Register instance definitions */
+/* UART0 */
+#define UART0_BDH UART_BDH_REG(UART0)
+#define UART0_BDL UART_BDL_REG(UART0)
+#define UART0_C1 UART_C1_REG(UART0)
+#define UART0_C2 UART_C2_REG(UART0)
+#define UART0_S1 UART_S1_REG(UART0)
+#define UART0_S2 UART_S2_REG(UART0)
+#define UART0_C3 UART_C3_REG(UART0)
+#define UART0_D UART_D_REG(UART0)
+#define UART0_MA1 UART_MA1_REG(UART0)
+#define UART0_MA2 UART_MA2_REG(UART0)
+#define UART0_C4 UART_C4_REG(UART0)
+#define UART0_C5 UART_C5_REG(UART0)
+#define UART0_ED UART_ED_REG(UART0)
+#define UART0_MODEM UART_MODEM_REG(UART0)
+#define UART0_IR UART_IR_REG(UART0)
+#define UART0_PFIFO UART_PFIFO_REG(UART0)
+#define UART0_CFIFO UART_CFIFO_REG(UART0)
+#define UART0_SFIFO UART_SFIFO_REG(UART0)
+#define UART0_TWFIFO UART_TWFIFO_REG(UART0)
+#define UART0_TCFIFO UART_TCFIFO_REG(UART0)
+#define UART0_RWFIFO UART_RWFIFO_REG(UART0)
+#define UART0_RCFIFO UART_RCFIFO_REG(UART0)
+#define UART0_C7816 UART_C7816_REG(UART0)
+#define UART0_IE7816 UART_IE7816_REG(UART0)
+#define UART0_IS7816 UART_IS7816_REG(UART0)
+#define UART0_WP7816T0 UART_WP7816_T_TYPE0_REG(UART0)
+#define UART0_WP7816T1 UART_WP7816_T_TYPE1_REG(UART0)
+#define UART0_WN7816 UART_WN7816_REG(UART0)
+#define UART0_WF7816 UART_WF7816_REG(UART0)
+#define UART0_ET7816 UART_ET7816_REG(UART0)
+#define UART0_TL7816 UART_TL7816_REG(UART0)
+/* UART1 */
+#define UART1_BDH UART_BDH_REG(UART1)
+#define UART1_BDL UART_BDL_REG(UART1)
+#define UART1_C1 UART_C1_REG(UART1)
+#define UART1_C2 UART_C2_REG(UART1)
+#define UART1_S1 UART_S1_REG(UART1)
+#define UART1_S2 UART_S2_REG(UART1)
+#define UART1_C3 UART_C3_REG(UART1)
+#define UART1_D UART_D_REG(UART1)
+#define UART1_MA1 UART_MA1_REG(UART1)
+#define UART1_MA2 UART_MA2_REG(UART1)
+#define UART1_C4 UART_C4_REG(UART1)
+#define UART1_C5 UART_C5_REG(UART1)
+#define UART1_ED UART_ED_REG(UART1)
+#define UART1_MODEM UART_MODEM_REG(UART1)
+#define UART1_IR UART_IR_REG(UART1)
+#define UART1_PFIFO UART_PFIFO_REG(UART1)
+#define UART1_CFIFO UART_CFIFO_REG(UART1)
+#define UART1_SFIFO UART_SFIFO_REG(UART1)
+#define UART1_TWFIFO UART_TWFIFO_REG(UART1)
+#define UART1_TCFIFO UART_TCFIFO_REG(UART1)
+#define UART1_RWFIFO UART_RWFIFO_REG(UART1)
+#define UART1_RCFIFO UART_RCFIFO_REG(UART1)
+/* UART2 */
+#define UART2_BDH UART_BDH_REG(UART2)
+#define UART2_BDL UART_BDL_REG(UART2)
+#define UART2_C1 UART_C1_REG(UART2)
+#define UART2_C2 UART_C2_REG(UART2)
+#define UART2_S1 UART_S1_REG(UART2)
+#define UART2_S2 UART_S2_REG(UART2)
+#define UART2_C3 UART_C3_REG(UART2)
+#define UART2_D UART_D_REG(UART2)
+#define UART2_MA1 UART_MA1_REG(UART2)
+#define UART2_MA2 UART_MA2_REG(UART2)
+#define UART2_C4 UART_C4_REG(UART2)
+#define UART2_C5 UART_C5_REG(UART2)
+#define UART2_ED UART_ED_REG(UART2)
+#define UART2_MODEM UART_MODEM_REG(UART2)
+#define UART2_IR UART_IR_REG(UART2)
+#define UART2_PFIFO UART_PFIFO_REG(UART2)
+#define UART2_CFIFO UART_CFIFO_REG(UART2)
+#define UART2_SFIFO UART_SFIFO_REG(UART2)
+#define UART2_TWFIFO UART_TWFIFO_REG(UART2)
+#define UART2_TCFIFO UART_TCFIFO_REG(UART2)
+#define UART2_RWFIFO UART_RWFIFO_REG(UART2)
+#define UART2_RCFIFO UART_RCFIFO_REG(UART2)
+/* UART3 */
+#define UART3_BDH UART_BDH_REG(UART3)
+#define UART3_BDL UART_BDL_REG(UART3)
+#define UART3_C1 UART_C1_REG(UART3)
+#define UART3_C2 UART_C2_REG(UART3)
+#define UART3_S1 UART_S1_REG(UART3)
+#define UART3_S2 UART_S2_REG(UART3)
+#define UART3_C3 UART_C3_REG(UART3)
+#define UART3_D UART_D_REG(UART3)
+#define UART3_MA1 UART_MA1_REG(UART3)
+#define UART3_MA2 UART_MA2_REG(UART3)
+#define UART3_C4 UART_C4_REG(UART3)
+#define UART3_C5 UART_C5_REG(UART3)
+#define UART3_ED UART_ED_REG(UART3)
+#define UART3_MODEM UART_MODEM_REG(UART3)
+#define UART3_IR UART_IR_REG(UART3)
+#define UART3_PFIFO UART_PFIFO_REG(UART3)
+#define UART3_CFIFO UART_CFIFO_REG(UART3)
+#define UART3_SFIFO UART_SFIFO_REG(UART3)
+#define UART3_TWFIFO UART_TWFIFO_REG(UART3)
+#define UART3_TCFIFO UART_TCFIFO_REG(UART3)
+#define UART3_RWFIFO UART_RWFIFO_REG(UART3)
+#define UART3_RCFIFO UART_RCFIFO_REG(UART3)
+/* UART4 */
+#define UART4_BDH UART_BDH_REG(UART4)
+#define UART4_BDL UART_BDL_REG(UART4)
+#define UART4_C1 UART_C1_REG(UART4)
+#define UART4_C2 UART_C2_REG(UART4)
+#define UART4_S1 UART_S1_REG(UART4)
+#define UART4_S2 UART_S2_REG(UART4)
+#define UART4_C3 UART_C3_REG(UART4)
+#define UART4_D UART_D_REG(UART4)
+#define UART4_MA1 UART_MA1_REG(UART4)
+#define UART4_MA2 UART_MA2_REG(UART4)
+#define UART4_C4 UART_C4_REG(UART4)
+#define UART4_C5 UART_C5_REG(UART4)
+#define UART4_ED UART_ED_REG(UART4)
+#define UART4_MODEM UART_MODEM_REG(UART4)
+#define UART4_IR UART_IR_REG(UART4)
+#define UART4_PFIFO UART_PFIFO_REG(UART4)
+#define UART4_CFIFO UART_CFIFO_REG(UART4)
+#define UART4_SFIFO UART_SFIFO_REG(UART4)
+#define UART4_TWFIFO UART_TWFIFO_REG(UART4)
+#define UART4_TCFIFO UART_TCFIFO_REG(UART4)
+#define UART4_RWFIFO UART_RWFIFO_REG(UART4)
+#define UART4_RCFIFO UART_RCFIFO_REG(UART4)
+/* UART5 */
+#define UART5_BDH UART_BDH_REG(UART5)
+#define UART5_BDL UART_BDL_REG(UART5)
+#define UART5_C1 UART_C1_REG(UART5)
+#define UART5_C2 UART_C2_REG(UART5)
+#define UART5_S1 UART_S1_REG(UART5)
+#define UART5_S2 UART_S2_REG(UART5)
+#define UART5_C3 UART_C3_REG(UART5)
+#define UART5_D UART_D_REG(UART5)
+#define UART5_MA1 UART_MA1_REG(UART5)
+#define UART5_MA2 UART_MA2_REG(UART5)
+#define UART5_C4 UART_C4_REG(UART5)
+#define UART5_C5 UART_C5_REG(UART5)
+#define UART5_ED UART_ED_REG(UART5)
+#define UART5_MODEM UART_MODEM_REG(UART5)
+#define UART5_IR UART_IR_REG(UART5)
+#define UART5_PFIFO UART_PFIFO_REG(UART5)
+#define UART5_CFIFO UART_CFIFO_REG(UART5)
+#define UART5_SFIFO UART_SFIFO_REG(UART5)
+#define UART5_TWFIFO UART_TWFIFO_REG(UART5)
+#define UART5_TCFIFO UART_TCFIFO_REG(UART5)
+#define UART5_RWFIFO UART_RWFIFO_REG(UART5)
+#define UART5_RCFIFO UART_RCFIFO_REG(UART5)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+ __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
+ uint8_t RESERVED_0[3];
+ __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
+ uint8_t RESERVED_1[3];
+ __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
+ uint8_t RESERVED_2[3];
+ __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
+ uint8_t RESERVED_3[3];
+ __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
+ uint8_t RESERVED_4[3];
+ __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
+ uint8_t RESERVED_5[3];
+ __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
+ uint8_t RESERVED_6[3];
+ __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
+ uint8_t RESERVED_7[99];
+ __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
+ uint8_t RESERVED_8[3];
+ __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
+ uint8_t RESERVED_9[3];
+ __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
+ uint8_t RESERVED_10[3];
+ __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
+ uint8_t RESERVED_11[3];
+ __I uint8_t STAT; /**< Status register, offset: 0x90 */
+ uint8_t RESERVED_12[3];
+ __IO uint8_t CTL; /**< Control register, offset: 0x94 */
+ uint8_t RESERVED_13[3];
+ __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
+ uint8_t RESERVED_14[3];
+ __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
+ uint8_t RESERVED_15[3];
+ __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
+ uint8_t RESERVED_16[3];
+ __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
+ uint8_t RESERVED_17[3];
+ __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
+ uint8_t RESERVED_18[3];
+ __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
+ uint8_t RESERVED_19[3];
+ __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
+ uint8_t RESERVED_20[3];
+ __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
+ uint8_t RESERVED_21[11];
+ struct { /* offset: 0xC0, array step: 0x4 */
+ __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_0[3];
+ } ENDPOINT[16];
+ __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
+ uint8_t RESERVED_22[3];
+ __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
+ uint8_t RESERVED_23[3];
+ __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
+ uint8_t RESERVED_24[3];
+ __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
+ uint8_t RESERVED_25[7];
+ __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
+ uint8_t RESERVED_26[43];
+ __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
+ uint8_t RESERVED_27[3];
+ __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
+ uint8_t RESERVED_28[23];
+ __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
+} USB_Type, *USB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- USB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
+ * @{
+ */
+
+
+/* USB - Register accessors */
+#define USB_PERID_REG(base) ((base)->PERID)
+#define USB_IDCOMP_REG(base) ((base)->IDCOMP)
+#define USB_REV_REG(base) ((base)->REV)
+#define USB_ADDINFO_REG(base) ((base)->ADDINFO)
+#define USB_OTGISTAT_REG(base) ((base)->OTGISTAT)
+#define USB_OTGICR_REG(base) ((base)->OTGICR)
+#define USB_OTGSTAT_REG(base) ((base)->OTGSTAT)
+#define USB_OTGCTL_REG(base) ((base)->OTGCTL)
+#define USB_ISTAT_REG(base) ((base)->ISTAT)
+#define USB_INTEN_REG(base) ((base)->INTEN)
+#define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
+#define USB_ERREN_REG(base) ((base)->ERREN)
+#define USB_STAT_REG(base) ((base)->STAT)
+#define USB_CTL_REG(base) ((base)->CTL)
+#define USB_ADDR_REG(base) ((base)->ADDR)
+#define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
+#define USB_FRMNUML_REG(base) ((base)->FRMNUML)
+#define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
+#define USB_TOKEN_REG(base) ((base)->TOKEN)
+#define USB_SOFTHLD_REG(base) ((base)->SOFTHLD)
+#define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
+#define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
+#define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
+#define USB_USBCTRL_REG(base) ((base)->USBCTRL)
+#define USB_OBSERVE_REG(base) ((base)->OBSERVE)
+#define USB_CONTROL_REG(base) ((base)->CONTROL)
+#define USB_USBTRC0_REG(base) ((base)->USBTRC0)
+#define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)
+#define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL)
+#define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN)
+#define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- USB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/* PERID Bit Fields */
+#define USB_PERID_ID_MASK 0x3Fu
+#define USB_PERID_ID_SHIFT 0
+#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
+/* IDCOMP Bit Fields */
+#define USB_IDCOMP_NID_MASK 0x3Fu
+#define USB_IDCOMP_NID_SHIFT 0
+#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
+/* REV Bit Fields */
+#define USB_REV_REV_MASK 0xFFu
+#define USB_REV_REV_SHIFT 0
+#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
+/* ADDINFO Bit Fields */
+#define USB_ADDINFO_IEHOST_MASK 0x1u
+#define USB_ADDINFO_IEHOST_SHIFT 0
+#define USB_ADDINFO_IRQNUM_MASK 0xF8u
+#define USB_ADDINFO_IRQNUM_SHIFT 3
+#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
+/* OTGISTAT Bit Fields */
+#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
+#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
+#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
+#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
+#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
+#define USB_OTGISTAT_ONEMSEC_SHIFT 6
+#define USB_OTGISTAT_IDCHG_MASK 0x80u
+#define USB_OTGISTAT_IDCHG_SHIFT 7
+/* OTGICR Bit Fields */
+#define USB_OTGICR_AVBUSEN_MASK 0x1u
+#define USB_OTGICR_AVBUSEN_SHIFT 0
+#define USB_OTGICR_BSESSEN_MASK 0x4u
+#define USB_OTGICR_BSESSEN_SHIFT 2
+#define USB_OTGICR_SESSVLDEN_MASK 0x8u
+#define USB_OTGICR_SESSVLDEN_SHIFT 3
+#define USB_OTGICR_LINESTATEEN_MASK 0x20u
+#define USB_OTGICR_LINESTATEEN_SHIFT 5
+#define USB_OTGICR_ONEMSECEN_MASK 0x40u
+#define USB_OTGICR_ONEMSECEN_SHIFT 6
+#define USB_OTGICR_IDEN_MASK 0x80u
+#define USB_OTGICR_IDEN_SHIFT 7
+/* OTGSTAT Bit Fields */
+#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
+#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
+#define USB_OTGSTAT_BSESSEND_MASK 0x4u
+#define USB_OTGSTAT_BSESSEND_SHIFT 2
+#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
+#define USB_OTGSTAT_SESS_VLD_SHIFT 3
+#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
+#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
+#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
+#define USB_OTGSTAT_ID_MASK 0x80u
+#define USB_OTGSTAT_ID_SHIFT 7
+/* OTGCTL Bit Fields */
+#define USB_OTGCTL_OTGEN_MASK 0x4u
+#define USB_OTGCTL_OTGEN_SHIFT 2
+#define USB_OTGCTL_DMLOW_MASK 0x10u
+#define USB_OTGCTL_DMLOW_SHIFT 4
+#define USB_OTGCTL_DPLOW_MASK 0x20u
+#define USB_OTGCTL_DPLOW_SHIFT 5
+#define USB_OTGCTL_DPHIGH_MASK 0x80u
+#define USB_OTGCTL_DPHIGH_SHIFT 7
+/* ISTAT Bit Fields */
+#define USB_ISTAT_USBRST_MASK 0x1u
+#define USB_ISTAT_USBRST_SHIFT 0
+#define USB_ISTAT_ERROR_MASK 0x2u
+#define USB_ISTAT_ERROR_SHIFT 1
+#define USB_ISTAT_SOFTOK_MASK 0x4u
+#define USB_ISTAT_SOFTOK_SHIFT 2
+#define USB_ISTAT_TOKDNE_MASK 0x8u
+#define USB_ISTAT_TOKDNE_SHIFT 3
+#define USB_ISTAT_SLEEP_MASK 0x10u
+#define USB_ISTAT_SLEEP_SHIFT 4
+#define USB_ISTAT_RESUME_MASK 0x20u
+#define USB_ISTAT_RESUME_SHIFT 5
+#define USB_ISTAT_ATTACH_MASK 0x40u
+#define USB_ISTAT_ATTACH_SHIFT 6
+#define USB_ISTAT_STALL_MASK 0x80u
+#define USB_ISTAT_STALL_SHIFT 7
+/* INTEN Bit Fields */
+#define USB_INTEN_USBRSTEN_MASK 0x1u
+#define USB_INTEN_USBRSTEN_SHIFT 0
+#define USB_INTEN_ERROREN_MASK 0x2u
+#define USB_INTEN_ERROREN_SHIFT 1
+#define USB_INTEN_SOFTOKEN_MASK 0x4u
+#define USB_INTEN_SOFTOKEN_SHIFT 2
+#define USB_INTEN_TOKDNEEN_MASK 0x8u
+#define USB_INTEN_TOKDNEEN_SHIFT 3
+#define USB_INTEN_SLEEPEN_MASK 0x10u
+#define USB_INTEN_SLEEPEN_SHIFT 4
+#define USB_INTEN_RESUMEEN_MASK 0x20u
+#define USB_INTEN_RESUMEEN_SHIFT 5
+#define USB_INTEN_ATTACHEN_MASK 0x40u
+#define USB_INTEN_ATTACHEN_SHIFT 6
+#define USB_INTEN_STALLEN_MASK 0x80u
+#define USB_INTEN_STALLEN_SHIFT 7
+/* ERRSTAT Bit Fields */
+#define USB_ERRSTAT_PIDERR_MASK 0x1u
+#define USB_ERRSTAT_PIDERR_SHIFT 0
+#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
+#define USB_ERRSTAT_CRC5EOF_SHIFT 1
+#define USB_ERRSTAT_CRC16_MASK 0x4u
+#define USB_ERRSTAT_CRC16_SHIFT 2
+#define USB_ERRSTAT_DFN8_MASK 0x8u
+#define USB_ERRSTAT_DFN8_SHIFT 3
+#define USB_ERRSTAT_BTOERR_MASK 0x10u
+#define USB_ERRSTAT_BTOERR_SHIFT 4
+#define USB_ERRSTAT_DMAERR_MASK 0x20u
+#define USB_ERRSTAT_DMAERR_SHIFT 5
+#define USB_ERRSTAT_BTSERR_MASK 0x80u
+#define USB_ERRSTAT_BTSERR_SHIFT 7
+/* ERREN Bit Fields */
+#define USB_ERREN_PIDERREN_MASK 0x1u
+#define USB_ERREN_PIDERREN_SHIFT 0
+#define USB_ERREN_CRC5EOFEN_MASK 0x2u
+#define USB_ERREN_CRC5EOFEN_SHIFT 1
+#define USB_ERREN_CRC16EN_MASK 0x4u
+#define USB_ERREN_CRC16EN_SHIFT 2
+#define USB_ERREN_DFN8EN_MASK 0x8u
+#define USB_ERREN_DFN8EN_SHIFT 3
+#define USB_ERREN_BTOERREN_MASK 0x10u
+#define USB_ERREN_BTOERREN_SHIFT 4
+#define USB_ERREN_DMAERREN_MASK 0x20u
+#define USB_ERREN_DMAERREN_SHIFT 5
+#define USB_ERREN_BTSERREN_MASK 0x80u
+#define USB_ERREN_BTSERREN_SHIFT 7
+/* STAT Bit Fields */
+#define USB_STAT_ODD_MASK 0x4u
+#define USB_STAT_ODD_SHIFT 2
+#define USB_STAT_TX_MASK 0x8u
+#define USB_STAT_TX_SHIFT 3
+#define USB_STAT_ENDP_MASK 0xF0u
+#define USB_STAT_ENDP_SHIFT 4
+#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
+/* CTL Bit Fields */
+#define USB_CTL_USBENSOFEN_MASK 0x1u
+#define USB_CTL_USBENSOFEN_SHIFT 0
+#define USB_CTL_ODDRST_MASK 0x2u
+#define USB_CTL_ODDRST_SHIFT 1
+#define USB_CTL_RESUME_MASK 0x4u
+#define USB_CTL_RESUME_SHIFT 2
+#define USB_CTL_HOSTMODEEN_MASK 0x8u
+#define USB_CTL_HOSTMODEEN_SHIFT 3
+#define USB_CTL_RESET_MASK 0x10u
+#define USB_CTL_RESET_SHIFT 4
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
+#define USB_CTL_SE0_MASK 0x40u
+#define USB_CTL_SE0_SHIFT 6
+#define USB_CTL_JSTATE_MASK 0x80u
+#define USB_CTL_JSTATE_SHIFT 7
+/* ADDR Bit Fields */
+#define USB_ADDR_ADDR_MASK 0x7Fu
+#define USB_ADDR_ADDR_SHIFT 0
+#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK 0x80u
+#define USB_ADDR_LSEN_SHIFT 7
+/* BDTPAGE1 Bit Fields */
+#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
+#define USB_BDTPAGE1_BDTBA_SHIFT 1
+#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
+/* FRMNUML Bit Fields */
+#define USB_FRMNUML_FRM_MASK 0xFFu
+#define USB_FRMNUML_FRM_SHIFT 0
+#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
+/* FRMNUMH Bit Fields */
+#define USB_FRMNUMH_FRM_MASK 0x7u
+#define USB_FRMNUMH_FRM_SHIFT 0
+#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
+/* TOKEN Bit Fields */
+#define USB_TOKEN_TOKENENDPT_MASK 0xFu
+#define USB_TOKEN_TOKENENDPT_SHIFT 0
+#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK 0xF0u
+#define USB_TOKEN_TOKENPID_SHIFT 4
+#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
+/* SOFTHLD Bit Fields */
+#define USB_SOFTHLD_CNT_MASK 0xFFu
+#define USB_SOFTHLD_CNT_SHIFT 0
+#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
+/* BDTPAGE2 Bit Fields */
+#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE2_BDTBA_SHIFT 0
+#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
+/* BDTPAGE3 Bit Fields */
+#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE3_BDTBA_SHIFT 0
+#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
+/* ENDPT Bit Fields */
+#define USB_ENDPT_EPHSHK_MASK 0x1u
+#define USB_ENDPT_EPHSHK_SHIFT 0
+#define USB_ENDPT_EPSTALL_MASK 0x2u
+#define USB_ENDPT_EPSTALL_SHIFT 1
+#define USB_ENDPT_EPTXEN_MASK 0x4u
+#define USB_ENDPT_EPTXEN_SHIFT 2
+#define USB_ENDPT_EPRXEN_MASK 0x8u
+#define USB_ENDPT_EPRXEN_SHIFT 3
+#define USB_ENDPT_EPCTLDIS_MASK 0x10u
+#define USB_ENDPT_EPCTLDIS_SHIFT 4
+#define USB_ENDPT_RETRYDIS_MASK 0x40u
+#define USB_ENDPT_RETRYDIS_SHIFT 6
+#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
+#define USB_ENDPT_HOSTWOHUB_SHIFT 7
+/* USBCTRL Bit Fields */
+#define USB_USBCTRL_PDE_MASK 0x40u
+#define USB_USBCTRL_PDE_SHIFT 6
+#define USB_USBCTRL_SUSP_MASK 0x80u
+#define USB_USBCTRL_SUSP_SHIFT 7
+/* OBSERVE Bit Fields */
+#define USB_OBSERVE_DMPD_MASK 0x10u
+#define USB_OBSERVE_DMPD_SHIFT 4
+#define USB_OBSERVE_DPPD_MASK 0x40u
+#define USB_OBSERVE_DPPD_SHIFT 6
+#define USB_OBSERVE_DPPU_MASK 0x80u
+#define USB_OBSERVE_DPPU_SHIFT 7
+/* CONTROL Bit Fields */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
+/* USBTRC0 Bit Fields */
+#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
+#define USB_USBTRC0_SYNC_DET_MASK 0x2u
+#define USB_USBTRC0_SYNC_DET_SHIFT 1
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK 0x4u
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT 2
+#define USB_USBTRC0_USBRESMEN_MASK 0x20u
+#define USB_USBTRC0_USBRESMEN_SHIFT 5
+#define USB_USBTRC0_USBRESET_MASK 0x80u
+#define USB_USBTRC0_USBRESET_SHIFT 7
+/* USBFRMADJUST Bit Fields */
+#define USB_USBFRMADJUST_ADJ_MASK 0xFFu
+#define USB_USBFRMADJUST_ADJ_SHIFT 0
+#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
+/* CLK_RECOVER_CTRL Bit Fields */
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
+/* CLK_RECOVER_IRC_EN Bit Fields */
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK 0x1u
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT 0
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK 0x2u
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT 1
+/* CLK_RECOVER_INT_STATUS Bit Fields */
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0 ((USB_Type *)USB0_BASE)
+#define USB0_BASE_PTR (USB0)
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASES { USB0 }
+
+/* ----------------------------------------------------------------------------
+ -- USB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
+ * @{
+ */
+
+
+/* USB - Register instance definitions */
+/* USB0 */
+#define USB0_PERID USB_PERID_REG(USB0)
+#define USB0_IDCOMP USB_IDCOMP_REG(USB0)
+#define USB0_REV USB_REV_REG(USB0)
+#define USB0_ADDINFO USB_ADDINFO_REG(USB0)
+#define USB0_OTGISTAT USB_OTGISTAT_REG(USB0)
+#define USB0_OTGICR USB_OTGICR_REG(USB0)
+#define USB0_OTGSTAT USB_OTGSTAT_REG(USB0)
+#define USB0_OTGCTL USB_OTGCTL_REG(USB0)
+#define USB0_ISTAT USB_ISTAT_REG(USB0)
+#define USB0_INTEN USB_INTEN_REG(USB0)
+#define USB0_ERRSTAT USB_ERRSTAT_REG(USB0)
+#define USB0_ERREN USB_ERREN_REG(USB0)
+#define USB0_STAT USB_STAT_REG(USB0)
+#define USB0_CTL USB_CTL_REG(USB0)
+#define USB0_ADDR USB_ADDR_REG(USB0)
+#define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0)
+#define USB0_FRMNUML USB_FRMNUML_REG(USB0)
+#define USB0_FRMNUMH USB_FRMNUMH_REG(USB0)
+#define USB0_TOKEN USB_TOKEN_REG(USB0)
+#define USB0_SOFTHLD USB_SOFTHLD_REG(USB0)
+#define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0)
+#define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0)
+#define USB0_ENDPT0 USB_ENDPT_REG(USB0,0)
+#define USB0_ENDPT1 USB_ENDPT_REG(USB0,1)
+#define USB0_ENDPT2 USB_ENDPT_REG(USB0,2)
+#define USB0_ENDPT3 USB_ENDPT_REG(USB0,3)
+#define USB0_ENDPT4 USB_ENDPT_REG(USB0,4)
+#define USB0_ENDPT5 USB_ENDPT_REG(USB0,5)
+#define USB0_ENDPT6 USB_ENDPT_REG(USB0,6)
+#define USB0_ENDPT7 USB_ENDPT_REG(USB0,7)
+#define USB0_ENDPT8 USB_ENDPT_REG(USB0,8)
+#define USB0_ENDPT9 USB_ENDPT_REG(USB0,9)
+#define USB0_ENDPT10 USB_ENDPT_REG(USB0,10)
+#define USB0_ENDPT11 USB_ENDPT_REG(USB0,11)
+#define USB0_ENDPT12 USB_ENDPT_REG(USB0,12)
+#define USB0_ENDPT13 USB_ENDPT_REG(USB0,13)
+#define USB0_ENDPT14 USB_ENDPT_REG(USB0,14)
+#define USB0_ENDPT15 USB_ENDPT_REG(USB0,15)
+#define USB0_USBCTRL USB_USBCTRL_REG(USB0)
+#define USB0_OBSERVE USB_OBSERVE_REG(USB0)
+#define USB0_CONTROL USB_CONTROL_REG(USB0)
+#define USB0_USBTRC0 USB_USBTRC0_REG(USB0)
+#define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0)
+#define USB0_CLK_RECOVER_CTRL USB_CLK_RECOVER_CTRL_REG(USB0)
+#define USB0_CLK_RECOVER_IRC_EN USB_CLK_RECOVER_IRC_EN_REG(USB0)
+#define USB0_CLK_RECOVER_INT_STATUS USB_CLK_RECOVER_INT_STATUS_REG(USB0)
+
+/* USB - Register array accessors */
+#define USB0_ENDPT(index) USB_ENDPT_REG(USB0,index)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USBDCD Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
+ * @{
+ */
+
+/** USBDCD - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */
+ __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */
+ __I uint32_t STATUS; /**< Status register, offset: 0x8 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */
+ __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */
+ union { /* offset: 0x18 */
+ __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */
+ __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */
+ };
+} USBDCD_Type, *USBDCD_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- USBDCD - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
+ * @{
+ */
+
+
+/* USBDCD - Register accessors */
+#define USBDCD_CONTROL_REG(base) ((base)->CONTROL)
+#define USBDCD_CLOCK_REG(base) ((base)->CLOCK)
+#define USBDCD_STATUS_REG(base) ((base)->STATUS)
+#define USBDCD_TIMER0_REG(base) ((base)->TIMER0)
+#define USBDCD_TIMER1_REG(base) ((base)->TIMER1)
+#define USBDCD_TIMER2_BC11_REG(base) ((base)->TIMER2_BC11)
+#define USBDCD_TIMER2_BC12_REG(base) ((base)->TIMER2_BC12)
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- USBDCD Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
+ * @{
+ */
+
+/* CONTROL Bit Fields */
+#define USBDCD_CONTROL_IACK_MASK 0x1u
+#define USBDCD_CONTROL_IACK_SHIFT 0
+#define USBDCD_CONTROL_IF_MASK 0x100u
+#define USBDCD_CONTROL_IF_SHIFT 8
+#define USBDCD_CONTROL_IE_MASK 0x10000u
+#define USBDCD_CONTROL_IE_SHIFT 16
+#define USBDCD_CONTROL_BC12_MASK 0x20000u
+#define USBDCD_CONTROL_BC12_SHIFT 17
+#define USBDCD_CONTROL_START_MASK 0x1000000u
+#define USBDCD_CONTROL_START_SHIFT 24
+#define USBDCD_CONTROL_SR_MASK 0x2000000u
+#define USBDCD_CONTROL_SR_SHIFT 25
+/* CLOCK Bit Fields */
+#define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u
+#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0
+#define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu
+#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2
+#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
+/* STATUS Bit Fields */
+#define USBDCD_STATUS_SEQ_RES_MASK 0x30000u
+#define USBDCD_STATUS_SEQ_RES_SHIFT 16
+#define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
+#define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u
+#define USBDCD_STATUS_SEQ_STAT_SHIFT 18
+#define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
+#define USBDCD_STATUS_ERR_MASK 0x100000u
+#define USBDCD_STATUS_ERR_SHIFT 20
+#define USBDCD_STATUS_TO_MASK 0x200000u
+#define USBDCD_STATUS_TO_SHIFT 21
+#define USBDCD_STATUS_ACTIVE_MASK 0x400000u
+#define USBDCD_STATUS_ACTIVE_SHIFT 22
+/* TIMER0 Bit Fields */
+#define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu
+#define USBDCD_TIMER0_TUNITCON_SHIFT 0
+#define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
+#define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u
+#define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16
+#define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
+/* TIMER1 Bit Fields */
+#define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu
+#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0
+#define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
+#define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u
+#define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16
+#define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
+/* TIMER2_BC11 Bit Fields */
+#define USBDCD_TIMER2_BC11_CHECK_DM_MASK 0xFu
+#define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT 0
+#define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_CHECK_DM_SHIFT))&USBDCD_TIMER2_BC11_CHECK_DM_MASK)
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK 0x3FF0000u
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT 16
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
+/* TIMER2_BC12 Bit Fields */
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK 0x3FFu
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT 0
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT))&USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK 0x3FF0000u
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT 16
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT))&USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Masks */
+
+
+/* USBDCD - Peripheral instance base addresses */
+/** Peripheral USBDCD base address */
+#define USBDCD_BASE (0x40035000u)
+/** Peripheral USBDCD base pointer */
+#define USBDCD ((USBDCD_Type *)USBDCD_BASE)
+#define USBDCD_BASE_PTR (USBDCD)
+/** Array initializer of USBDCD peripheral base pointers */
+#define USBDCD_BASES { USBDCD }
+
+/* ----------------------------------------------------------------------------
+ -- USBDCD - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
+ * @{
+ */
+
+
+/* USBDCD - Register instance definitions */
+/* USBDCD */
+#define USBDCD_CONTROL USBDCD_CONTROL_REG(USBDCD)
+#define USBDCD_CLOCK USBDCD_CLOCK_REG(USBDCD)
+#define USBDCD_STATUS USBDCD_STATUS_REG(USBDCD)
+#define USBDCD_TIMER0 USBDCD_TIMER0_REG(USBDCD)
+#define USBDCD_TIMER1 USBDCD_TIMER1_REG(USBDCD)
+#define USBDCD_TIMER2_BC11 USBDCD_TIMER2_BC11_REG(USBDCD)
+#define USBDCD_TIMER2_BC12 USBDCD_TIMER2_BC12_REG(USBDCD)
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- VREF Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
+ * @{
+ */
+
+/** VREF - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
+ __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
+} VREF_Type, *VREF_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- VREF - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
+ * @{
+ */
+
+
+/* VREF - Register accessors */
+#define VREF_TRM_REG(base) ((base)->TRM)
+#define VREF_SC_REG(base) ((base)->SC)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- VREF Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Masks VREF Register Masks
+ * @{
+ */
+
+/* TRM Bit Fields */
+#define VREF_TRM_TRIM_MASK 0x3Fu
+#define VREF_TRM_TRIM_SHIFT 0
+#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
+#define VREF_TRM_CHOPEN_MASK 0x40u
+#define VREF_TRM_CHOPEN_SHIFT 6
+/* SC Bit Fields */
+#define VREF_SC_MODE_LV_MASK 0x3u
+#define VREF_SC_MODE_LV_SHIFT 0
+#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST_MASK 0x4u
+#define VREF_SC_VREFST_SHIFT 2
+#define VREF_SC_ICOMPEN_MASK 0x20u
+#define VREF_SC_ICOMPEN_SHIFT 5
+#define VREF_SC_REGEN_MASK 0x40u
+#define VREF_SC_REGEN_SHIFT 6
+#define VREF_SC_VREFEN_MASK 0x80u
+#define VREF_SC_VREFEN_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Masks */
+
+
+/* VREF - Peripheral instance base addresses */
+/** Peripheral VREF base address */
+#define VREF_BASE (0x40074000u)
+/** Peripheral VREF base pointer */
+#define VREF ((VREF_Type *)VREF_BASE)
+#define VREF_BASE_PTR (VREF)
+/** Array initializer of VREF peripheral base pointers */
+#define VREF_BASES { VREF }
+
+/* ----------------------------------------------------------------------------
+ -- VREF - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
+ * @{
+ */
+
+
+/* VREF - Register instance definitions */
+/* VREF */
+#define VREF_TRM VREF_TRM_REG(VREF)
+#define VREF_SC VREF_SC_REG(VREF)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group VREF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- WDOG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
+ * @{
+ */
+
+/** WDOG - Register Layout Typedef */
+typedef struct {
+ __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
+ __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
+ __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
+ __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
+ __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
+ __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
+ __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
+ __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
+ __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
+ __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
+ __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
+ __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
+} WDOG_Type, *WDOG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- WDOG - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
+ * @{
+ */
+
+
+/* WDOG - Register accessors */
+#define WDOG_STCTRLH_REG(base) ((base)->STCTRLH)
+#define WDOG_STCTRLL_REG(base) ((base)->STCTRLL)
+#define WDOG_TOVALH_REG(base) ((base)->TOVALH)
+#define WDOG_TOVALL_REG(base) ((base)->TOVALL)
+#define WDOG_WINH_REG(base) ((base)->WINH)
+#define WDOG_WINL_REG(base) ((base)->WINL)
+#define WDOG_REFRESH_REG(base) ((base)->REFRESH)
+#define WDOG_UNLOCK_REG(base) ((base)->UNLOCK)
+#define WDOG_TMROUTH_REG(base) ((base)->TMROUTH)
+#define WDOG_TMROUTL_REG(base) ((base)->TMROUTL)
+#define WDOG_RSTCNT_REG(base) ((base)->RSTCNT)
+#define WDOG_PRESC_REG(base) ((base)->PRESC)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- WDOG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Masks WDOG Register Masks
+ * @{
+ */
+
+/* STCTRLH Bit Fields */
+#define WDOG_STCTRLH_WDOGEN_MASK 0x1u
+#define WDOG_STCTRLH_WDOGEN_SHIFT 0
+#define WDOG_STCTRLH_CLKSRC_MASK 0x2u
+#define WDOG_STCTRLH_CLKSRC_SHIFT 1
+#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
+#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
+#define WDOG_STCTRLH_WINEN_MASK 0x8u
+#define WDOG_STCTRLH_WINEN_SHIFT 3
+#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
+#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
+#define WDOG_STCTRLH_DBGEN_MASK 0x20u
+#define WDOG_STCTRLH_DBGEN_SHIFT 5
+#define WDOG_STCTRLH_STOPEN_MASK 0x40u
+#define WDOG_STCTRLH_STOPEN_SHIFT 6
+#define WDOG_STCTRLH_WAITEN_MASK 0x80u
+#define WDOG_STCTRLH_WAITEN_SHIFT 7
+#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
+#define WDOG_STCTRLH_TESTWDOG_SHIFT 10
+#define WDOG_STCTRLH_TESTSEL_MASK 0x800u
+#define WDOG_STCTRLH_TESTSEL_SHIFT 11
+#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
+#define WDOG_STCTRLH_BYTESEL_SHIFT 12
+#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
+#define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
+#define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
+/* STCTRLL Bit Fields */
+#define WDOG_STCTRLL_INTFLG_MASK 0x8000u
+#define WDOG_STCTRLL_INTFLG_SHIFT 15
+/* TOVALH Bit Fields */
+#define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
+#define WDOG_TOVALH_TOVALHIGH_SHIFT 0
+#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
+/* TOVALL Bit Fields */
+#define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
+#define WDOG_TOVALL_TOVALLOW_SHIFT 0
+#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
+/* WINH Bit Fields */
+#define WDOG_WINH_WINHIGH_MASK 0xFFFFu
+#define WDOG_WINH_WINHIGH_SHIFT 0
+#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
+/* WINL Bit Fields */
+#define WDOG_WINL_WINLOW_MASK 0xFFFFu
+#define WDOG_WINL_WINLOW_SHIFT 0
+#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
+/* REFRESH Bit Fields */
+#define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
+#define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
+#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
+/* UNLOCK Bit Fields */
+#define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
+#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
+#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
+/* TMROUTH Bit Fields */
+#define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
+#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
+#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
+/* TMROUTL Bit Fields */
+#define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
+#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
+#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
+/* RSTCNT Bit Fields */
+#define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
+#define WDOG_RSTCNT_RSTCNT_SHIFT 0
+#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
+/* PRESC Bit Fields */
+#define WDOG_PRESC_PRESCVAL_MASK 0x700u
+#define WDOG_PRESC_PRESCVAL_SHIFT 8
+#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Masks */
+
+
+/* WDOG - Peripheral instance base addresses */
+/** Peripheral WDOG base address */
+#define WDOG_BASE (0x40052000u)
+/** Peripheral WDOG base pointer */
+#define WDOG ((WDOG_Type *)WDOG_BASE)
+#define WDOG_BASE_PTR (WDOG)
+/** Array initializer of WDOG peripheral base pointers */
+#define WDOG_BASES { WDOG }
+
+/* ----------------------------------------------------------------------------
+ -- WDOG - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
+ * @{
+ */
+
+
+/* WDOG - Register instance definitions */
+/* WDOG */
+#define WDOG_STCTRLH WDOG_STCTRLH_REG(WDOG)
+#define WDOG_STCTRLL WDOG_STCTRLL_REG(WDOG)
+#define WDOG_TOVALH WDOG_TOVALH_REG(WDOG)
+#define WDOG_TOVALL WDOG_TOVALL_REG(WDOG)
+#define WDOG_WINH WDOG_WINH_REG(WDOG)
+#define WDOG_WINL WDOG_WINL_REG(WDOG)
+#define WDOG_REFRESH WDOG_REFRESH_REG(WDOG)
+#define WDOG_UNLOCK WDOG_UNLOCK_REG(WDOG)
+#define WDOG_TMROUTH WDOG_TMROUTH_REG(WDOG)
+#define WDOG_TMROUTL WDOG_TMROUTL_REG(WDOG)
+#define WDOG_RSTCNT WDOG_RSTCNT_REG(WDOG)
+#define WDOG_PRESC WDOG_PRESC_REG(WDOG)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group WDOG_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma pop
+#elif defined(__CWCC__)
+ #pragma pop
+#elif defined(__GNUC__)
+ /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=default
+#else
+ #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- Backward Compatibility
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @{
+ */
+
+#define DMA_EARS_REG(base) This_symbol_has_been_deprecated
+#define DMA_EARS This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_0_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_0_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_1_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_1_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_2_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_2_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_3_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_3_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_4_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_4_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_5_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_5_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_6_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_6_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_7_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_7_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_8_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_8_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_9_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_9_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_10_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_10_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_11_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_11_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_12_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_12_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_13_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_13_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_14_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_14_SHIFT This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_15_MASK This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_15_SHIFT This_symbol_has_been_deprecated
+#define ENET_RMON_T_DROP_REG(base) This_symbol_has_been_deprecated
+#define ENET_IEEE_T_DROP_REG(base) This_symbol_has_been_deprecated
+#define ENET_IEEE_T_SQE_REG(base) This_symbol_has_been_deprecated
+#define ENET_RMON_R_RESVD_0_REG(base) This_symbol_has_been_deprecated
+#define ENET_RMON_R_DROP_REG(base) ENET_IEEE_R_DROP_REG(base)
+#define ENET_RMON_R_FRAME_OK_REG(base) ENET_IEEE_R_FRAME_OK_REG(base)
+#define ENET_RMON_T_DROP This_symbol_has_been_deprecated
+#define ENET_IEEE_T_DROP This_symbol_has_been_deprecated
+#define ENET_IEEE_T_SQE This_symbol_has_been_deprecated
+#define ENET_RMON_R_RESVD_0 This_symbol_has_been_deprecated
+#define MCG_C9_REG(base) This_symbol_has_been_deprecated
+#define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
+#define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
+#define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
+#define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
+#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
+#define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
+#define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
+#define MCG_C9 This_symbol_has_been_deprecated
+#define MCM_PLACR_REG(base) This_symbol_has_been_deprecated
+#define MCM_PLACR_ARB_MASK This_symbol_has_been_deprecated
+#define MCM_PLACR_ARB_SHIFT This_symbol_has_been_deprecated
+#define MCM_PLACR This_symbol_has_been_deprecated
+
+/*!
+ * @}
+ */ /* end of group Backward_Compatibility_Symbols */
+
+
+#else /* #if !defined(MCU_MK64F12) */
+ /* There is already included the same memory map. Check if it is compatible (has the same major version) */
+ #if (MCU_MEM_MAP_VERSION != 0x0200u)
+ #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
+ #warning There are included two not compatible versions of memory maps. Please check possible differences.
+ #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
+ #endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */
+#endif /* #if !defined(MCU_MK64F12) */
+
+#endif /* #if !defined(MK64F12_H_) */
+
+/* MK64F12.h, eof. */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_adc.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,2578 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_ADC_REGISTERS_H__
+#define __HW_ADC_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 ADC
+ *
+ * Analog-to-Digital Converter
+ *
+ * Registers defined in this header file:
+ * - HW_ADC_SC1n - ADC Status and Control Registers 1
+ * - HW_ADC_CFG1 - ADC Configuration Register 1
+ * - HW_ADC_CFG2 - ADC Configuration Register 2
+ * - HW_ADC_Rn - ADC Data Result Register
+ * - HW_ADC_CV1 - Compare Value Registers
+ * - HW_ADC_CV2 - Compare Value Registers
+ * - HW_ADC_SC2 - Status and Control Register 2
+ * - HW_ADC_SC3 - Status and Control Register 3
+ * - HW_ADC_OFS - ADC Offset Correction Register
+ * - HW_ADC_PG - ADC Plus-Side Gain Register
+ * - HW_ADC_MG - ADC Minus-Side Gain Register
+ * - HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register
+ * - HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register
+ * - HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register
+ * - HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register
+ * - HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register
+ * - HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register
+ * - HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register
+ * - HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register
+ * - HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register
+ * - HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register
+ * - HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register
+ * - HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register
+ * - HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register
+ * - HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register
+ *
+ * - hw_adc_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_ADC_BASE
+#define HW_ADC_INSTANCE_COUNT (2U) //!< Number of instances of the ADC module.
+#define HW_ADC0 (0U) //!< Instance number for ADC0.
+#define HW_ADC1 (1U) //!< Instance number for ADC1.
+#define REGS_ADC0_BASE (0x4003B000U) //!< Base address for ADC0.
+#define REGS_ADC1_BASE (0x400BB000U) //!< Base address for ADC1.
+
+//! @brief Table of base addresses for ADC instances.
+static const uint32_t __g_regs_ADC_base_addresses[] = {
+ REGS_ADC0_BASE,
+ REGS_ADC1_BASE,
+ };
+
+//! @brief Get the base address of ADC by instance number.
+//! @param x ADC instance number, from 0 through 1.
+#define REGS_ADC_BASE(x) (__g_regs_ADC_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of ADC.
+#define REGS_ADC_INSTANCE(b) ((b) == REGS_ADC0_BASE ? HW_ADC0 : (b) == REGS_ADC1_BASE ? HW_ADC1 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_SC1n - ADC Status and Control Registers 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_SC1n - ADC Status and Control Registers 1 (RW)
+ *
+ * Reset value: 0x0000001FU
+ *
+ * SC1A is used for both software and hardware trigger modes of operation. To
+ * allow sequential conversions of the ADC to be triggered by internal peripherals,
+ * the ADC can have more than one status and control register: one for each
+ * conversion. The SC1B-SC1n registers indicate potentially multiple SC1 registers
+ * for use only in hardware trigger mode. See the chip configuration information
+ * about the number of SC1n registers specific to this device. The SC1n registers
+ * have identical fields, and are used in a "ping-pong" approach to control ADC
+ * operation. At any one point in time, only one of the SC1n registers is actively
+ * controlling ADC conversions. Updating SC1A while SC1n is actively controlling
+ * a conversion is allowed, and vice-versa for any of the SC1n registers specific
+ * to this MCU. Writing SC1A while SC1A is actively controlling a conversion
+ * aborts the current conversion. In Software Trigger mode, when SC2[ADTRG]=0,
+ * writes to SC1A subsequently initiate a new conversion, if SC1[ADCH] contains a
+ * value other than all 1s. Writing any of the SC1n registers while that specific
+ * SC1n register is actively controlling a conversion aborts the current conversion.
+ * None of the SC1B-SC1n registers are used for software trigger operation and
+ * therefore writes to the SC1B-SC1n registers do not initiate a new conversion.
+ */
+typedef union _hw_adc_sc1n
+{
+ uint32_t U;
+ struct _hw_adc_sc1n_bitfields
+ {
+ uint32_t ADCH : 5; //!< [4:0] Input channel select
+ uint32_t DIFF : 1; //!< [5] Differential Mode Enable
+ uint32_t AIEN : 1; //!< [6] Interrupt Enable
+ uint32_t COCO : 1; //!< [7] Conversion Complete Flag
+ uint32_t RESERVED0 : 24; //!< [31:8]
+ } B;
+} hw_adc_sc1n_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_SC1n register
+ */
+//@{
+#define HW_ADC_SC1n_COUNT (2U)
+
+#define HW_ADC_SC1n_ADDR(x, n) (REGS_ADC_BASE(x) + 0x0U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_SC1n(x, n) (*(__IO hw_adc_sc1n_t *) HW_ADC_SC1n_ADDR(x, n))
+#define HW_ADC_SC1n_RD(x, n) (HW_ADC_SC1n(x, n).U)
+#define HW_ADC_SC1n_WR(x, n, v) (HW_ADC_SC1n(x, n).U = (v))
+#define HW_ADC_SC1n_SET(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) | (v)))
+#define HW_ADC_SC1n_CLR(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) & ~(v)))
+#define HW_ADC_SC1n_TOG(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_SC1n bitfields
+ */
+
+/*!
+ * @name Register ADC_SC1n, field ADCH[4:0] (RW)
+ *
+ * Selects one of the input channels. The input channel decode depends on the
+ * value of DIFF. DAD0-DAD3 are associated with the input pin pairs DADPx and
+ * DADMx. Some of the input channel options in the bitfield-setting descriptions might
+ * not be available for your device. For the actual ADC channel assignments for
+ * your device, see the Chip Configuration details. The successive approximation
+ * converter subsystem is turned off when the channel select bits are all set,
+ * that is, ADCH = 11111. This feature allows explicit disabling of the ADC and
+ * isolation of the input channel from all sources. Terminating continuous
+ * conversions this way prevents an additional single conversion from being performed. It
+ * is not necessary to set ADCH to all 1s to place the ADC in a low-power state
+ * when continuous conversions are not enabled because the module automatically
+ * enters a low-power state when a conversion completes.
+ *
+ * Values:
+ * - 00000 - When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is
+ * selected as input.
+ * - 00001 - When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is
+ * selected as input.
+ * - 00010 - When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is
+ * selected as input.
+ * - 00011 - When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is
+ * selected as input.
+ * - 00100 - When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
+ * - 00101 - When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
+ * - 00110 - When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
+ * - 00111 - When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
+ * - 01000 - When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
+ * - 01001 - When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
+ * - 01010 - When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
+ * - 01011 - When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
+ * - 01100 - When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
+ * - 01101 - When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
+ * - 01110 - When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
+ * - 01111 - When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
+ * - 10000 - When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
+ * - 10001 - When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
+ * - 10010 - When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
+ * - 10011 - When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
+ * - 10100 - When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
+ * - 10101 - When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
+ * - 10110 - When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
+ * - 10111 - When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
+ * - 11000 - Reserved.
+ * - 11001 - Reserved.
+ * - 11010 - When DIFF=0, Temp Sensor (single-ended) is selected as input; when
+ * DIFF=1, Temp Sensor (differential) is selected as input.
+ * - 11011 - When DIFF=0, Bandgap (single-ended) is selected as input; when
+ * DIFF=1, Bandgap (differential) is selected as input.
+ * - 11100 - Reserved.
+ * - 11101 - When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH
+ * (differential) is selected as input. Voltage reference selected is determined
+ * by SC2[REFSEL].
+ * - 11110 - When DIFF=0,VREFSL is selected as input; when DIFF=1, it is
+ * reserved. Voltage reference selected is determined by SC2[REFSEL].
+ * - 11111 - Module is disabled.
+ */
+//@{
+#define BP_ADC_SC1n_ADCH (0U) //!< Bit position for ADC_SC1n_ADCH.
+#define BM_ADC_SC1n_ADCH (0x0000001FU) //!< Bit mask for ADC_SC1n_ADCH.
+#define BS_ADC_SC1n_ADCH (5U) //!< Bit field size in bits for ADC_SC1n_ADCH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC1n_ADCH field.
+#define BR_ADC_SC1n_ADCH(x, n) (HW_ADC_SC1n(x, n).B.ADCH)
+#endif
+
+//! @brief Format value for bitfield ADC_SC1n_ADCH.
+#define BF_ADC_SC1n_ADCH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC1n_ADCH), uint32_t) & BM_ADC_SC1n_ADCH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADCH field to a new value.
+#define BW_ADC_SC1n_ADCH(x, n, v) (HW_ADC_SC1n_WR(x, n, (HW_ADC_SC1n_RD(x, n) & ~BM_ADC_SC1n_ADCH) | BF_ADC_SC1n_ADCH(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_SC1n, field DIFF[5] (RW)
+ *
+ * Configures the ADC to operate in differential mode. When enabled, this mode
+ * automatically selects from the differential channels, and changes the
+ * conversion algorithm and the number of cycles to complete a conversion.
+ *
+ * Values:
+ * - 0 - Single-ended conversions and input channels are selected.
+ * - 1 - Differential conversions and input channels are selected.
+ */
+//@{
+#define BP_ADC_SC1n_DIFF (5U) //!< Bit position for ADC_SC1n_DIFF.
+#define BM_ADC_SC1n_DIFF (0x00000020U) //!< Bit mask for ADC_SC1n_DIFF.
+#define BS_ADC_SC1n_DIFF (1U) //!< Bit field size in bits for ADC_SC1n_DIFF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC1n_DIFF field.
+#define BR_ADC_SC1n_DIFF(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_DIFF))
+#endif
+
+//! @brief Format value for bitfield ADC_SC1n_DIFF.
+#define BF_ADC_SC1n_DIFF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC1n_DIFF), uint32_t) & BM_ADC_SC1n_DIFF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DIFF field to a new value.
+#define BW_ADC_SC1n_DIFF(x, n, v) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_DIFF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_SC1n, field AIEN[6] (RW)
+ *
+ * Enables conversion complete interrupts. When COCO becomes set while the
+ * respective AIEN is high, an interrupt is asserted.
+ *
+ * Values:
+ * - 0 - Conversion complete interrupt is disabled.
+ * - 1 - Conversion complete interrupt is enabled.
+ */
+//@{
+#define BP_ADC_SC1n_AIEN (6U) //!< Bit position for ADC_SC1n_AIEN.
+#define BM_ADC_SC1n_AIEN (0x00000040U) //!< Bit mask for ADC_SC1n_AIEN.
+#define BS_ADC_SC1n_AIEN (1U) //!< Bit field size in bits for ADC_SC1n_AIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC1n_AIEN field.
+#define BR_ADC_SC1n_AIEN(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_AIEN))
+#endif
+
+//! @brief Format value for bitfield ADC_SC1n_AIEN.
+#define BF_ADC_SC1n_AIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC1n_AIEN), uint32_t) & BM_ADC_SC1n_AIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AIEN field to a new value.
+#define BW_ADC_SC1n_AIEN(x, n, v) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_AIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_SC1n, field COCO[7] (RO)
+ *
+ * This is a read-only field that is set each time a conversion is completed
+ * when the compare function is disabled, or SC2[ACFE]=0 and the hardware average
+ * function is disabled, or SC3[AVGE]=0. When the compare function is enabled, or
+ * SC2[ACFE]=1, COCO is set upon completion of a conversion only if the compare
+ * result is true. When the hardware average function is enabled, or SC3[AVGE]=1,
+ * COCO is set upon completion of the selected number of conversions (determined
+ * by AVGS). COCO in SC1A is also set at the completion of a calibration sequence.
+ * COCO is cleared when the respective SC1n register is written or when the
+ * respective Rn register is read.
+ *
+ * Values:
+ * - 0 - Conversion is not completed.
+ * - 1 - Conversion is completed.
+ */
+//@{
+#define BP_ADC_SC1n_COCO (7U) //!< Bit position for ADC_SC1n_COCO.
+#define BM_ADC_SC1n_COCO (0x00000080U) //!< Bit mask for ADC_SC1n_COCO.
+#define BS_ADC_SC1n_COCO (1U) //!< Bit field size in bits for ADC_SC1n_COCO.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC1n_COCO field.
+#define BR_ADC_SC1n_COCO(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_COCO))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CFG1 - ADC Configuration Register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CFG1 - ADC Configuration Register 1 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The configuration Register 1 (CFG1) selects the mode of operation, clock
+ * source, clock divide, and configuration for low power or long sample time.
+ */
+typedef union _hw_adc_cfg1
+{
+ uint32_t U;
+ struct _hw_adc_cfg1_bitfields
+ {
+ uint32_t ADICLK : 2; //!< [1:0] Input Clock Select
+ uint32_t MODE : 2; //!< [3:2] Conversion mode selection
+ uint32_t ADLSMP : 1; //!< [4] Sample Time Configuration
+ uint32_t ADIV : 2; //!< [6:5] Clock Divide Select
+ uint32_t ADLPC : 1; //!< [7] Low-Power Configuration
+ uint32_t RESERVED0 : 24; //!< [31:8]
+ } B;
+} hw_adc_cfg1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CFG1 register
+ */
+//@{
+#define HW_ADC_CFG1_ADDR(x) (REGS_ADC_BASE(x) + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CFG1(x) (*(__IO hw_adc_cfg1_t *) HW_ADC_CFG1_ADDR(x))
+#define HW_ADC_CFG1_RD(x) (HW_ADC_CFG1(x).U)
+#define HW_ADC_CFG1_WR(x, v) (HW_ADC_CFG1(x).U = (v))
+#define HW_ADC_CFG1_SET(x, v) (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) | (v)))
+#define HW_ADC_CFG1_CLR(x, v) (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) & ~(v)))
+#define HW_ADC_CFG1_TOG(x, v) (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CFG1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CFG1, field ADICLK[1:0] (RW)
+ *
+ * Selects the input clock source to generate the internal clock, ADCK. Note
+ * that when the ADACK clock source is selected, it is not required to be active
+ * prior to conversion start. When it is selected and it is not active prior to a
+ * conversion start, when CFG2[ADACKEN]=0, the asynchronous clock is activated at
+ * the start of a conversion and deactivated when conversions are terminated. In
+ * this case, there is an associated clock startup delay each time the clock
+ * source is re-activated.
+ *
+ * Values:
+ * - 00 - Bus clock
+ * - 01 - Alternate clock 2 (ALTCLK2)
+ * - 10 - Alternate clock (ALTCLK)
+ * - 11 - Asynchronous clock (ADACK)
+ */
+//@{
+#define BP_ADC_CFG1_ADICLK (0U) //!< Bit position for ADC_CFG1_ADICLK.
+#define BM_ADC_CFG1_ADICLK (0x00000003U) //!< Bit mask for ADC_CFG1_ADICLK.
+#define BS_ADC_CFG1_ADICLK (2U) //!< Bit field size in bits for ADC_CFG1_ADICLK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CFG1_ADICLK field.
+#define BR_ADC_CFG1_ADICLK(x) (HW_ADC_CFG1(x).B.ADICLK)
+#endif
+
+//! @brief Format value for bitfield ADC_CFG1_ADICLK.
+#define BF_ADC_CFG1_ADICLK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG1_ADICLK), uint32_t) & BM_ADC_CFG1_ADICLK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADICLK field to a new value.
+#define BW_ADC_CFG1_ADICLK(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_ADICLK) | BF_ADC_CFG1_ADICLK(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_CFG1, field MODE[3:2] (RW)
+ *
+ * Selects the ADC resolution mode.
+ *
+ * Values:
+ * - 00 - When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is
+ * differential 9-bit conversion with 2's complement output.
+ * - 01 - When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is
+ * differential 13-bit conversion with 2's complement output.
+ * - 10 - When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is
+ * differential 11-bit conversion with 2's complement output
+ * - 11 - When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is
+ * differential 16-bit conversion with 2's complement output
+ */
+//@{
+#define BP_ADC_CFG1_MODE (2U) //!< Bit position for ADC_CFG1_MODE.
+#define BM_ADC_CFG1_MODE (0x0000000CU) //!< Bit mask for ADC_CFG1_MODE.
+#define BS_ADC_CFG1_MODE (2U) //!< Bit field size in bits for ADC_CFG1_MODE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CFG1_MODE field.
+#define BR_ADC_CFG1_MODE(x) (HW_ADC_CFG1(x).B.MODE)
+#endif
+
+//! @brief Format value for bitfield ADC_CFG1_MODE.
+#define BF_ADC_CFG1_MODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG1_MODE), uint32_t) & BM_ADC_CFG1_MODE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MODE field to a new value.
+#define BW_ADC_CFG1_MODE(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_MODE) | BF_ADC_CFG1_MODE(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_CFG1, field ADLSMP[4] (RW)
+ *
+ * Selects between different sample times based on the conversion mode selected.
+ * This field adjusts the sample period to allow higher impedance inputs to be
+ * accurately sampled or to maximize conversion speed for lower impedance inputs.
+ * Longer sample times can also be used to lower overall power consumption if
+ * continuous conversions are enabled and high conversion rates are not required.
+ * When ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the
+ * extent of the long sample time.
+ *
+ * Values:
+ * - 0 - Short sample time.
+ * - 1 - Long sample time.
+ */
+//@{
+#define BP_ADC_CFG1_ADLSMP (4U) //!< Bit position for ADC_CFG1_ADLSMP.
+#define BM_ADC_CFG1_ADLSMP (0x00000010U) //!< Bit mask for ADC_CFG1_ADLSMP.
+#define BS_ADC_CFG1_ADLSMP (1U) //!< Bit field size in bits for ADC_CFG1_ADLSMP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CFG1_ADLSMP field.
+#define BR_ADC_CFG1_ADLSMP(x) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLSMP))
+#endif
+
+//! @brief Format value for bitfield ADC_CFG1_ADLSMP.
+#define BF_ADC_CFG1_ADLSMP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG1_ADLSMP), uint32_t) & BM_ADC_CFG1_ADLSMP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADLSMP field to a new value.
+#define BW_ADC_CFG1_ADLSMP(x, v) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLSMP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_CFG1, field ADIV[6:5] (RW)
+ *
+ * Selects the divide ratio used by the ADC to generate the internal clock ADCK.
+ *
+ * Values:
+ * - 00 - The divide ratio is 1 and the clock rate is input clock.
+ * - 01 - The divide ratio is 2 and the clock rate is (input clock)/2.
+ * - 10 - The divide ratio is 4 and the clock rate is (input clock)/4.
+ * - 11 - The divide ratio is 8 and the clock rate is (input clock)/8.
+ */
+//@{
+#define BP_ADC_CFG1_ADIV (5U) //!< Bit position for ADC_CFG1_ADIV.
+#define BM_ADC_CFG1_ADIV (0x00000060U) //!< Bit mask for ADC_CFG1_ADIV.
+#define BS_ADC_CFG1_ADIV (2U) //!< Bit field size in bits for ADC_CFG1_ADIV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CFG1_ADIV field.
+#define BR_ADC_CFG1_ADIV(x) (HW_ADC_CFG1(x).B.ADIV)
+#endif
+
+//! @brief Format value for bitfield ADC_CFG1_ADIV.
+#define BF_ADC_CFG1_ADIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG1_ADIV), uint32_t) & BM_ADC_CFG1_ADIV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADIV field to a new value.
+#define BW_ADC_CFG1_ADIV(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_ADIV) | BF_ADC_CFG1_ADIV(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_CFG1, field ADLPC[7] (RW)
+ *
+ * Controls the power configuration of the successive approximation converter.
+ * This optimizes power consumption when higher sample rates are not required.
+ *
+ * Values:
+ * - 0 - Normal power configuration.
+ * - 1 - Low-power configuration. The power is reduced at the expense of maximum
+ * clock speed.
+ */
+//@{
+#define BP_ADC_CFG1_ADLPC (7U) //!< Bit position for ADC_CFG1_ADLPC.
+#define BM_ADC_CFG1_ADLPC (0x00000080U) //!< Bit mask for ADC_CFG1_ADLPC.
+#define BS_ADC_CFG1_ADLPC (1U) //!< Bit field size in bits for ADC_CFG1_ADLPC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CFG1_ADLPC field.
+#define BR_ADC_CFG1_ADLPC(x) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLPC))
+#endif
+
+//! @brief Format value for bitfield ADC_CFG1_ADLPC.
+#define BF_ADC_CFG1_ADLPC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG1_ADLPC), uint32_t) & BM_ADC_CFG1_ADLPC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADLPC field to a new value.
+#define BW_ADC_CFG1_ADLPC(x, v) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLPC) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CFG2 - ADC Configuration Register 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CFG2 - ADC Configuration Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Configuration Register 2 (CFG2) selects the special high-speed configuration
+ * for very high speed conversions and selects the long sample time duration
+ * during long sample mode.
+ */
+typedef union _hw_adc_cfg2
+{
+ uint32_t U;
+ struct _hw_adc_cfg2_bitfields
+ {
+ uint32_t ADLSTS : 2; //!< [1:0] Long Sample Time Select
+ uint32_t ADHSC : 1; //!< [2] High-Speed Configuration
+ uint32_t ADACKEN : 1; //!< [3] Asynchronous Clock Output Enable
+ uint32_t MUXSEL : 1; //!< [4] ADC Mux Select
+ uint32_t RESERVED0 : 27; //!< [31:5]
+ } B;
+} hw_adc_cfg2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CFG2 register
+ */
+//@{
+#define HW_ADC_CFG2_ADDR(x) (REGS_ADC_BASE(x) + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CFG2(x) (*(__IO hw_adc_cfg2_t *) HW_ADC_CFG2_ADDR(x))
+#define HW_ADC_CFG2_RD(x) (HW_ADC_CFG2(x).U)
+#define HW_ADC_CFG2_WR(x, v) (HW_ADC_CFG2(x).U = (v))
+#define HW_ADC_CFG2_SET(x, v) (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) | (v)))
+#define HW_ADC_CFG2_CLR(x, v) (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) & ~(v)))
+#define HW_ADC_CFG2_TOG(x, v) (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CFG2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CFG2, field ADLSTS[1:0] (RW)
+ *
+ * Selects between the extended sample times when long sample time is selected,
+ * that is, when CFG1[ADLSMP]=1. This allows higher impedance inputs to be
+ * accurately sampled or to maximize conversion speed for lower impedance inputs.
+ * Longer sample times can also be used to lower overall power consumption when
+ * continuous conversions are enabled if high conversion rates are not required.
+ *
+ * Values:
+ * - 00 - Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles
+ * total.
+ * - 01 - 12 extra ADCK cycles; 16 ADCK cycles total sample time.
+ * - 10 - 6 extra ADCK cycles; 10 ADCK cycles total sample time.
+ * - 11 - 2 extra ADCK cycles; 6 ADCK cycles total sample time.
+ */
+//@{
+#define BP_ADC_CFG2_ADLSTS (0U) //!< Bit position for ADC_CFG2_ADLSTS.
+#define BM_ADC_CFG2_ADLSTS (0x00000003U) //!< Bit mask for ADC_CFG2_ADLSTS.
+#define BS_ADC_CFG2_ADLSTS (2U) //!< Bit field size in bits for ADC_CFG2_ADLSTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CFG2_ADLSTS field.
+#define BR_ADC_CFG2_ADLSTS(x) (HW_ADC_CFG2(x).B.ADLSTS)
+#endif
+
+//! @brief Format value for bitfield ADC_CFG2_ADLSTS.
+#define BF_ADC_CFG2_ADLSTS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG2_ADLSTS), uint32_t) & BM_ADC_CFG2_ADLSTS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADLSTS field to a new value.
+#define BW_ADC_CFG2_ADLSTS(x, v) (HW_ADC_CFG2_WR(x, (HW_ADC_CFG2_RD(x) & ~BM_ADC_CFG2_ADLSTS) | BF_ADC_CFG2_ADLSTS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_CFG2, field ADHSC[2] (RW)
+ *
+ * Configures the ADC for very high-speed operation. The conversion sequence is
+ * altered with 2 ADCK cycles added to the conversion time to allow higher speed
+ * conversion clocks.
+ *
+ * Values:
+ * - 0 - Normal conversion sequence selected.
+ * - 1 - High-speed conversion sequence selected with 2 additional ADCK cycles
+ * to total conversion time.
+ */
+//@{
+#define BP_ADC_CFG2_ADHSC (2U) //!< Bit position for ADC_CFG2_ADHSC.
+#define BM_ADC_CFG2_ADHSC (0x00000004U) //!< Bit mask for ADC_CFG2_ADHSC.
+#define BS_ADC_CFG2_ADHSC (1U) //!< Bit field size in bits for ADC_CFG2_ADHSC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CFG2_ADHSC field.
+#define BR_ADC_CFG2_ADHSC(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADHSC))
+#endif
+
+//! @brief Format value for bitfield ADC_CFG2_ADHSC.
+#define BF_ADC_CFG2_ADHSC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG2_ADHSC), uint32_t) & BM_ADC_CFG2_ADHSC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADHSC field to a new value.
+#define BW_ADC_CFG2_ADHSC(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADHSC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_CFG2, field ADACKEN[3] (RW)
+ *
+ * Enables the asynchronous clock source and the clock source output regardless
+ * of the conversion and status of CFG1[ADICLK]. Based on MCU configuration, the
+ * asynchronous clock may be used by other modules. See chip configuration
+ * information. Setting this field allows the clock to be used even while the ADC is
+ * idle or operating from a different clock source. Also, latency of initiating a
+ * single or first-continuous conversion with the asynchronous clock selected is
+ * reduced because the ADACK clock is already operational.
+ *
+ * Values:
+ * - 0 - Asynchronous clock output disabled; Asynchronous clock is enabled only
+ * if selected by ADICLK and a conversion is active.
+ * - 1 - Asynchronous clock and clock output is enabled regardless of the state
+ * of the ADC.
+ */
+//@{
+#define BP_ADC_CFG2_ADACKEN (3U) //!< Bit position for ADC_CFG2_ADACKEN.
+#define BM_ADC_CFG2_ADACKEN (0x00000008U) //!< Bit mask for ADC_CFG2_ADACKEN.
+#define BS_ADC_CFG2_ADACKEN (1U) //!< Bit field size in bits for ADC_CFG2_ADACKEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CFG2_ADACKEN field.
+#define BR_ADC_CFG2_ADACKEN(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADACKEN))
+#endif
+
+//! @brief Format value for bitfield ADC_CFG2_ADACKEN.
+#define BF_ADC_CFG2_ADACKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG2_ADACKEN), uint32_t) & BM_ADC_CFG2_ADACKEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADACKEN field to a new value.
+#define BW_ADC_CFG2_ADACKEN(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADACKEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_CFG2, field MUXSEL[4] (RW)
+ *
+ * Changes the ADC mux setting to select between alternate sets of ADC channels.
+ *
+ * Values:
+ * - 0 - ADxxa channels are selected.
+ * - 1 - ADxxb channels are selected.
+ */
+//@{
+#define BP_ADC_CFG2_MUXSEL (4U) //!< Bit position for ADC_CFG2_MUXSEL.
+#define BM_ADC_CFG2_MUXSEL (0x00000010U) //!< Bit mask for ADC_CFG2_MUXSEL.
+#define BS_ADC_CFG2_MUXSEL (1U) //!< Bit field size in bits for ADC_CFG2_MUXSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CFG2_MUXSEL field.
+#define BR_ADC_CFG2_MUXSEL(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_MUXSEL))
+#endif
+
+//! @brief Format value for bitfield ADC_CFG2_MUXSEL.
+#define BF_ADC_CFG2_MUXSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CFG2_MUXSEL), uint32_t) & BM_ADC_CFG2_MUXSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MUXSEL field to a new value.
+#define BW_ADC_CFG2_MUXSEL(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_MUXSEL) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_Rn - ADC Data Result Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_Rn - ADC Data Result Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The data result registers (Rn) contain the result of an ADC conversion of the
+ * channel selected by the corresponding status and channel control register
+ * (SC1A:SC1n). For every status and channel control register, there is a
+ * corresponding data result register. Unused bits in R n are cleared in unsigned
+ * right-aligned modes and carry the sign bit (MSB) in sign-extended 2's complement modes.
+ * For example, when configured for 10-bit single-ended mode, D[15:10] are
+ * cleared. When configured for 11-bit differential mode, D[15:10] carry the sign bit,
+ * that is, bit 10 extended through bit 15. The following table describes the
+ * behavior of the data result registers in the different modes of operation. Data
+ * result register description Conversion mode D15 D14 D13 D12 D11 D10 D9 D8 D7
+ * D6 D5 D4 D3 D2 D1 D0 Format 16-bit differential S D D D D D D D D D D D D D D D
+ * Signed 2's complement 16-bit single-ended D D D D D D D D D D D D D D D D
+ * Unsigned right justified 13-bit differential S S S S D D D D D D D D D D D D
+ * Sign-extended 2's complement 12-bit single-ended 0 0 0 0 D D D D D D D D D D D D
+ * Unsigned right-justified 11-bit differential S S S S S S D D D D D D D D D D
+ * Sign-extended 2's complement 10-bit single-ended 0 0 0 0 0 0 D D D D D D D D D D
+ * Unsigned right-justified 9-bit differential S S S S S S S S D D D D D D D D
+ * Sign-extended 2's complement 8-bit single-ended 0 0 0 0 0 0 0 0 D D D D D D D D
+ * Unsigned right-justified S: Sign bit or sign bit extension; D: Data, which is
+ * 2's complement data if indicated
+ */
+typedef union _hw_adc_rn
+{
+ uint32_t U;
+ struct _hw_adc_rn_bitfields
+ {
+ uint32_t D : 16; //!< [15:0] Data result
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_adc_rn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_Rn register
+ */
+//@{
+#define HW_ADC_Rn_COUNT (2U)
+
+#define HW_ADC_Rn_ADDR(x, n) (REGS_ADC_BASE(x) + 0x10U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_Rn(x, n) (*(__I hw_adc_rn_t *) HW_ADC_Rn_ADDR(x, n))
+#define HW_ADC_Rn_RD(x, n) (HW_ADC_Rn(x, n).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_Rn bitfields
+ */
+
+/*!
+ * @name Register ADC_Rn, field D[15:0] (RO)
+ */
+//@{
+#define BP_ADC_Rn_D (0U) //!< Bit position for ADC_Rn_D.
+#define BM_ADC_Rn_D (0x0000FFFFU) //!< Bit mask for ADC_Rn_D.
+#define BS_ADC_Rn_D (16U) //!< Bit field size in bits for ADC_Rn_D.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_Rn_D field.
+#define BR_ADC_Rn_D(x, n) (HW_ADC_Rn(x, n).B.D)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CV1 - Compare Value Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CV1 - Compare Value Registers (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Compare Value Registers (CV1 and CV2) contain a compare value used to
+ * compare the conversion result when the compare function is enabled, that is,
+ * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
+ * different modes of operation for both bit position definition and value format
+ * using unsigned or sign-extended 2's complement. Therefore, the compare function
+ * uses only the CVn fields that are related to the ADC mode of operation. The
+ * compare value 2 register (CV2) is used only when the compare range function is
+ * enabled, that is, SC2[ACREN]=1.
+ */
+typedef union _hw_adc_cv1
+{
+ uint32_t U;
+ struct _hw_adc_cv1_bitfields
+ {
+ uint32_t CV : 16; //!< [15:0] Compare Value.
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_adc_cv1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CV1 register
+ */
+//@{
+#define HW_ADC_CV1_ADDR(x) (REGS_ADC_BASE(x) + 0x18U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CV1(x) (*(__IO hw_adc_cv1_t *) HW_ADC_CV1_ADDR(x))
+#define HW_ADC_CV1_RD(x) (HW_ADC_CV1(x).U)
+#define HW_ADC_CV1_WR(x, v) (HW_ADC_CV1(x).U = (v))
+#define HW_ADC_CV1_SET(x, v) (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) | (v)))
+#define HW_ADC_CV1_CLR(x, v) (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) & ~(v)))
+#define HW_ADC_CV1_TOG(x, v) (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CV1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CV1, field CV[15:0] (RW)
+ */
+//@{
+#define BP_ADC_CV1_CV (0U) //!< Bit position for ADC_CV1_CV.
+#define BM_ADC_CV1_CV (0x0000FFFFU) //!< Bit mask for ADC_CV1_CV.
+#define BS_ADC_CV1_CV (16U) //!< Bit field size in bits for ADC_CV1_CV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CV1_CV field.
+#define BR_ADC_CV1_CV(x) (HW_ADC_CV1(x).B.CV)
+#endif
+
+//! @brief Format value for bitfield ADC_CV1_CV.
+#define BF_ADC_CV1_CV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CV1_CV), uint32_t) & BM_ADC_CV1_CV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CV field to a new value.
+#define BW_ADC_CV1_CV(x, v) (HW_ADC_CV1_WR(x, (HW_ADC_CV1_RD(x) & ~BM_ADC_CV1_CV) | BF_ADC_CV1_CV(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CV2 - Compare Value Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CV2 - Compare Value Registers (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Compare Value Registers (CV1 and CV2) contain a compare value used to
+ * compare the conversion result when the compare function is enabled, that is,
+ * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
+ * different modes of operation for both bit position definition and value format
+ * using unsigned or sign-extended 2's complement. Therefore, the compare function
+ * uses only the CVn fields that are related to the ADC mode of operation. The
+ * compare value 2 register (CV2) is used only when the compare range function is
+ * enabled, that is, SC2[ACREN]=1.
+ */
+typedef union _hw_adc_cv2
+{
+ uint32_t U;
+ struct _hw_adc_cv2_bitfields
+ {
+ uint32_t CV : 16; //!< [15:0] Compare Value.
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_adc_cv2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CV2 register
+ */
+//@{
+#define HW_ADC_CV2_ADDR(x) (REGS_ADC_BASE(x) + 0x1CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CV2(x) (*(__IO hw_adc_cv2_t *) HW_ADC_CV2_ADDR(x))
+#define HW_ADC_CV2_RD(x) (HW_ADC_CV2(x).U)
+#define HW_ADC_CV2_WR(x, v) (HW_ADC_CV2(x).U = (v))
+#define HW_ADC_CV2_SET(x, v) (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) | (v)))
+#define HW_ADC_CV2_CLR(x, v) (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) & ~(v)))
+#define HW_ADC_CV2_TOG(x, v) (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CV2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CV2, field CV[15:0] (RW)
+ */
+//@{
+#define BP_ADC_CV2_CV (0U) //!< Bit position for ADC_CV2_CV.
+#define BM_ADC_CV2_CV (0x0000FFFFU) //!< Bit mask for ADC_CV2_CV.
+#define BS_ADC_CV2_CV (16U) //!< Bit field size in bits for ADC_CV2_CV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CV2_CV field.
+#define BR_ADC_CV2_CV(x) (HW_ADC_CV2(x).B.CV)
+#endif
+
+//! @brief Format value for bitfield ADC_CV2_CV.
+#define BF_ADC_CV2_CV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CV2_CV), uint32_t) & BM_ADC_CV2_CV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CV field to a new value.
+#define BW_ADC_CV2_CV(x, v) (HW_ADC_CV2_WR(x, (HW_ADC_CV2_RD(x) & ~BM_ADC_CV2_CV) | BF_ADC_CV2_CV(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_SC2 - Status and Control Register 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_SC2 - Status and Control Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The status and control register 2 (SC2) contains the conversion active,
+ * hardware/software trigger select, compare function, and voltage reference select of
+ * the ADC module.
+ */
+typedef union _hw_adc_sc2
+{
+ uint32_t U;
+ struct _hw_adc_sc2_bitfields
+ {
+ uint32_t REFSEL : 2; //!< [1:0] Voltage Reference Selection
+ uint32_t DMAEN : 1; //!< [2] DMA Enable
+ uint32_t ACREN : 1; //!< [3] Compare Function Range Enable
+ uint32_t ACFGT : 1; //!< [4] Compare Function Greater Than Enable
+ uint32_t ACFE : 1; //!< [5] Compare Function Enable
+ uint32_t ADTRG : 1; //!< [6] Conversion Trigger Select
+ uint32_t ADACT : 1; //!< [7] Conversion Active
+ uint32_t RESERVED0 : 24; //!< [31:8]
+ } B;
+} hw_adc_sc2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_SC2 register
+ */
+//@{
+#define HW_ADC_SC2_ADDR(x) (REGS_ADC_BASE(x) + 0x20U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_SC2(x) (*(__IO hw_adc_sc2_t *) HW_ADC_SC2_ADDR(x))
+#define HW_ADC_SC2_RD(x) (HW_ADC_SC2(x).U)
+#define HW_ADC_SC2_WR(x, v) (HW_ADC_SC2(x).U = (v))
+#define HW_ADC_SC2_SET(x, v) (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) | (v)))
+#define HW_ADC_SC2_CLR(x, v) (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) & ~(v)))
+#define HW_ADC_SC2_TOG(x, v) (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_SC2 bitfields
+ */
+
+/*!
+ * @name Register ADC_SC2, field REFSEL[1:0] (RW)
+ *
+ * Selects the voltage reference source used for conversions.
+ *
+ * Values:
+ * - 00 - Default voltage reference pin pair, that is, external pins VREFH and
+ * VREFL
+ * - 01 - Alternate reference pair, that is, VALTH and VALTL . This pair may be
+ * additional external pins or internal sources depending on the MCU
+ * configuration. See the chip configuration information for details specific to this
+ * MCU
+ * - 10 - Reserved
+ * - 11 - Reserved
+ */
+//@{
+#define BP_ADC_SC2_REFSEL (0U) //!< Bit position for ADC_SC2_REFSEL.
+#define BM_ADC_SC2_REFSEL (0x00000003U) //!< Bit mask for ADC_SC2_REFSEL.
+#define BS_ADC_SC2_REFSEL (2U) //!< Bit field size in bits for ADC_SC2_REFSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC2_REFSEL field.
+#define BR_ADC_SC2_REFSEL(x) (HW_ADC_SC2(x).B.REFSEL)
+#endif
+
+//! @brief Format value for bitfield ADC_SC2_REFSEL.
+#define BF_ADC_SC2_REFSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_REFSEL), uint32_t) & BM_ADC_SC2_REFSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the REFSEL field to a new value.
+#define BW_ADC_SC2_REFSEL(x, v) (HW_ADC_SC2_WR(x, (HW_ADC_SC2_RD(x) & ~BM_ADC_SC2_REFSEL) | BF_ADC_SC2_REFSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_SC2, field DMAEN[2] (RW)
+ *
+ * Values:
+ * - 0 - DMA is disabled.
+ * - 1 - DMA is enabled and will assert the ADC DMA request during an ADC
+ * conversion complete event noted when any of the SC1n[COCO] flags is asserted.
+ */
+//@{
+#define BP_ADC_SC2_DMAEN (2U) //!< Bit position for ADC_SC2_DMAEN.
+#define BM_ADC_SC2_DMAEN (0x00000004U) //!< Bit mask for ADC_SC2_DMAEN.
+#define BS_ADC_SC2_DMAEN (1U) //!< Bit field size in bits for ADC_SC2_DMAEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC2_DMAEN field.
+#define BR_ADC_SC2_DMAEN(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_DMAEN))
+#endif
+
+//! @brief Format value for bitfield ADC_SC2_DMAEN.
+#define BF_ADC_SC2_DMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_DMAEN), uint32_t) & BM_ADC_SC2_DMAEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMAEN field to a new value.
+#define BW_ADC_SC2_DMAEN(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_DMAEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_SC2, field ACREN[3] (RW)
+ *
+ * Configures the compare function to check if the conversion result of the
+ * input being monitored is either between or outside the range formed by CV1 and CV2
+ * determined by the value of ACFGT. ACFE must be set for ACFGT to have any
+ * effect.
+ *
+ * Values:
+ * - 0 - Range function disabled. Only CV1 is compared.
+ * - 1 - Range function enabled. Both CV1 and CV2 are compared.
+ */
+//@{
+#define BP_ADC_SC2_ACREN (3U) //!< Bit position for ADC_SC2_ACREN.
+#define BM_ADC_SC2_ACREN (0x00000008U) //!< Bit mask for ADC_SC2_ACREN.
+#define BS_ADC_SC2_ACREN (1U) //!< Bit field size in bits for ADC_SC2_ACREN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC2_ACREN field.
+#define BR_ADC_SC2_ACREN(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACREN))
+#endif
+
+//! @brief Format value for bitfield ADC_SC2_ACREN.
+#define BF_ADC_SC2_ACREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_ACREN), uint32_t) & BM_ADC_SC2_ACREN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ACREN field to a new value.
+#define BW_ADC_SC2_ACREN(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACREN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_SC2, field ACFGT[4] (RW)
+ *
+ * Configures the compare function to check the conversion result relative to
+ * the CV1 and CV2 based upon the value of ACREN. ACFE must be set for ACFGT to
+ * have any effect.
+ *
+ * Values:
+ * - 0 - Configures less than threshold, outside range not inclusive and inside
+ * range not inclusive; functionality based on the values placed in CV1 and
+ * CV2.
+ * - 1 - Configures greater than or equal to threshold, outside and inside
+ * ranges inclusive; functionality based on the values placed in CV1 and CV2.
+ */
+//@{
+#define BP_ADC_SC2_ACFGT (4U) //!< Bit position for ADC_SC2_ACFGT.
+#define BM_ADC_SC2_ACFGT (0x00000010U) //!< Bit mask for ADC_SC2_ACFGT.
+#define BS_ADC_SC2_ACFGT (1U) //!< Bit field size in bits for ADC_SC2_ACFGT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC2_ACFGT field.
+#define BR_ADC_SC2_ACFGT(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFGT))
+#endif
+
+//! @brief Format value for bitfield ADC_SC2_ACFGT.
+#define BF_ADC_SC2_ACFGT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_ACFGT), uint32_t) & BM_ADC_SC2_ACFGT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ACFGT field to a new value.
+#define BW_ADC_SC2_ACFGT(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFGT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_SC2, field ACFE[5] (RW)
+ *
+ * Enables the compare function.
+ *
+ * Values:
+ * - 0 - Compare function disabled.
+ * - 1 - Compare function enabled.
+ */
+//@{
+#define BP_ADC_SC2_ACFE (5U) //!< Bit position for ADC_SC2_ACFE.
+#define BM_ADC_SC2_ACFE (0x00000020U) //!< Bit mask for ADC_SC2_ACFE.
+#define BS_ADC_SC2_ACFE (1U) //!< Bit field size in bits for ADC_SC2_ACFE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC2_ACFE field.
+#define BR_ADC_SC2_ACFE(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFE))
+#endif
+
+//! @brief Format value for bitfield ADC_SC2_ACFE.
+#define BF_ADC_SC2_ACFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_ACFE), uint32_t) & BM_ADC_SC2_ACFE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ACFE field to a new value.
+#define BW_ADC_SC2_ACFE(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_SC2, field ADTRG[6] (RW)
+ *
+ * Selects the type of trigger used for initiating a conversion. Two types of
+ * trigger are selectable: Software trigger: When software trigger is selected, a
+ * conversion is initiated following a write to SC1A. Hardware trigger: When
+ * hardware trigger is selected, a conversion is initiated following the assertion of
+ * the ADHWT input after a pulse of the ADHWTSn input.
+ *
+ * Values:
+ * - 0 - Software trigger selected.
+ * - 1 - Hardware trigger selected.
+ */
+//@{
+#define BP_ADC_SC2_ADTRG (6U) //!< Bit position for ADC_SC2_ADTRG.
+#define BM_ADC_SC2_ADTRG (0x00000040U) //!< Bit mask for ADC_SC2_ADTRG.
+#define BS_ADC_SC2_ADTRG (1U) //!< Bit field size in bits for ADC_SC2_ADTRG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC2_ADTRG field.
+#define BR_ADC_SC2_ADTRG(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADTRG))
+#endif
+
+//! @brief Format value for bitfield ADC_SC2_ADTRG.
+#define BF_ADC_SC2_ADTRG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC2_ADTRG), uint32_t) & BM_ADC_SC2_ADTRG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADTRG field to a new value.
+#define BW_ADC_SC2_ADTRG(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADTRG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_SC2, field ADACT[7] (RO)
+ *
+ * Indicates that a conversion or hardware averaging is in progress. ADACT is
+ * set when a conversion is initiated and cleared when a conversion is completed or
+ * aborted.
+ *
+ * Values:
+ * - 0 - Conversion not in progress.
+ * - 1 - Conversion in progress.
+ */
+//@{
+#define BP_ADC_SC2_ADACT (7U) //!< Bit position for ADC_SC2_ADACT.
+#define BM_ADC_SC2_ADACT (0x00000080U) //!< Bit mask for ADC_SC2_ADACT.
+#define BS_ADC_SC2_ADACT (1U) //!< Bit field size in bits for ADC_SC2_ADACT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC2_ADACT field.
+#define BR_ADC_SC2_ADACT(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADACT))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_SC3 - Status and Control Register 3
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_SC3 - Status and Control Register 3 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Status and Control Register 3 (SC3) controls the calibration, continuous
+ * convert, and hardware averaging functions of the ADC module.
+ */
+typedef union _hw_adc_sc3
+{
+ uint32_t U;
+ struct _hw_adc_sc3_bitfields
+ {
+ uint32_t AVGS : 2; //!< [1:0] Hardware Average Select
+ uint32_t AVGE : 1; //!< [2] Hardware Average Enable
+ uint32_t ADCO : 1; //!< [3] Continuous Conversion Enable
+ uint32_t RESERVED0 : 2; //!< [5:4]
+ uint32_t CALF : 1; //!< [6] Calibration Failed Flag
+ uint32_t CAL : 1; //!< [7] Calibration
+ uint32_t RESERVED1 : 24; //!< [31:8]
+ } B;
+} hw_adc_sc3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_SC3 register
+ */
+//@{
+#define HW_ADC_SC3_ADDR(x) (REGS_ADC_BASE(x) + 0x24U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_SC3(x) (*(__IO hw_adc_sc3_t *) HW_ADC_SC3_ADDR(x))
+#define HW_ADC_SC3_RD(x) (HW_ADC_SC3(x).U)
+#define HW_ADC_SC3_WR(x, v) (HW_ADC_SC3(x).U = (v))
+#define HW_ADC_SC3_SET(x, v) (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) | (v)))
+#define HW_ADC_SC3_CLR(x, v) (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) & ~(v)))
+#define HW_ADC_SC3_TOG(x, v) (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_SC3 bitfields
+ */
+
+/*!
+ * @name Register ADC_SC3, field AVGS[1:0] (RW)
+ *
+ * Determines how many ADC conversions will be averaged to create the ADC
+ * average result.
+ *
+ * Values:
+ * - 00 - 4 samples averaged.
+ * - 01 - 8 samples averaged.
+ * - 10 - 16 samples averaged.
+ * - 11 - 32 samples averaged.
+ */
+//@{
+#define BP_ADC_SC3_AVGS (0U) //!< Bit position for ADC_SC3_AVGS.
+#define BM_ADC_SC3_AVGS (0x00000003U) //!< Bit mask for ADC_SC3_AVGS.
+#define BS_ADC_SC3_AVGS (2U) //!< Bit field size in bits for ADC_SC3_AVGS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC3_AVGS field.
+#define BR_ADC_SC3_AVGS(x) (HW_ADC_SC3(x).B.AVGS)
+#endif
+
+//! @brief Format value for bitfield ADC_SC3_AVGS.
+#define BF_ADC_SC3_AVGS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC3_AVGS), uint32_t) & BM_ADC_SC3_AVGS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AVGS field to a new value.
+#define BW_ADC_SC3_AVGS(x, v) (HW_ADC_SC3_WR(x, (HW_ADC_SC3_RD(x) & ~BM_ADC_SC3_AVGS) | BF_ADC_SC3_AVGS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_SC3, field AVGE[2] (RW)
+ *
+ * Enables the hardware average function of the ADC.
+ *
+ * Values:
+ * - 0 - Hardware average function disabled.
+ * - 1 - Hardware average function enabled.
+ */
+//@{
+#define BP_ADC_SC3_AVGE (2U) //!< Bit position for ADC_SC3_AVGE.
+#define BM_ADC_SC3_AVGE (0x00000004U) //!< Bit mask for ADC_SC3_AVGE.
+#define BS_ADC_SC3_AVGE (1U) //!< Bit field size in bits for ADC_SC3_AVGE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC3_AVGE field.
+#define BR_ADC_SC3_AVGE(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_AVGE))
+#endif
+
+//! @brief Format value for bitfield ADC_SC3_AVGE.
+#define BF_ADC_SC3_AVGE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC3_AVGE), uint32_t) & BM_ADC_SC3_AVGE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AVGE field to a new value.
+#define BW_ADC_SC3_AVGE(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_AVGE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_SC3, field ADCO[3] (RW)
+ *
+ * Enables continuous conversions.
+ *
+ * Values:
+ * - 0 - One conversion or one set of conversions if the hardware average
+ * function is enabled, that is, AVGE=1, after initiating a conversion.
+ * - 1 - Continuous conversions or sets of conversions if the hardware average
+ * function is enabled, that is, AVGE=1, after initiating a conversion.
+ */
+//@{
+#define BP_ADC_SC3_ADCO (3U) //!< Bit position for ADC_SC3_ADCO.
+#define BM_ADC_SC3_ADCO (0x00000008U) //!< Bit mask for ADC_SC3_ADCO.
+#define BS_ADC_SC3_ADCO (1U) //!< Bit field size in bits for ADC_SC3_ADCO.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC3_ADCO field.
+#define BR_ADC_SC3_ADCO(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_ADCO))
+#endif
+
+//! @brief Format value for bitfield ADC_SC3_ADCO.
+#define BF_ADC_SC3_ADCO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC3_ADCO), uint32_t) & BM_ADC_SC3_ADCO)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADCO field to a new value.
+#define BW_ADC_SC3_ADCO(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_ADCO) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_SC3, field CALF[6] (RO)
+ *
+ * Displays the result of the calibration sequence. The calibration sequence
+ * will fail if SC2[ADTRG] = 1, any ADC register is written, or any stop mode is
+ * entered before the calibration sequence completes. Writing 1 to CALF clears it.
+ *
+ * Values:
+ * - 0 - Calibration completed normally.
+ * - 1 - Calibration failed. ADC accuracy specifications are not guaranteed.
+ */
+//@{
+#define BP_ADC_SC3_CALF (6U) //!< Bit position for ADC_SC3_CALF.
+#define BM_ADC_SC3_CALF (0x00000040U) //!< Bit mask for ADC_SC3_CALF.
+#define BS_ADC_SC3_CALF (1U) //!< Bit field size in bits for ADC_SC3_CALF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC3_CALF field.
+#define BR_ADC_SC3_CALF(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CALF))
+#endif
+//@}
+
+/*!
+ * @name Register ADC_SC3, field CAL[7] (RW)
+ *
+ * Begins the calibration sequence when set. This field stays set while the
+ * calibration is in progress and is cleared when the calibration sequence is
+ * completed. CALF must be checked to determine the result of the calibration sequence.
+ * Once started, the calibration routine cannot be interrupted by writes to the
+ * ADC registers or the results will be invalid and CALF will set. Setting CAL
+ * will abort any current conversion.
+ */
+//@{
+#define BP_ADC_SC3_CAL (7U) //!< Bit position for ADC_SC3_CAL.
+#define BM_ADC_SC3_CAL (0x00000080U) //!< Bit mask for ADC_SC3_CAL.
+#define BS_ADC_SC3_CAL (1U) //!< Bit field size in bits for ADC_SC3_CAL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_SC3_CAL field.
+#define BR_ADC_SC3_CAL(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CAL))
+#endif
+
+//! @brief Format value for bitfield ADC_SC3_CAL.
+#define BF_ADC_SC3_CAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_SC3_CAL), uint32_t) & BM_ADC_SC3_CAL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CAL field to a new value.
+#define BW_ADC_SC3_CAL(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CAL) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_OFS - ADC Offset Correction Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_OFS - ADC Offset Correction Register (RW)
+ *
+ * Reset value: 0x00000004U
+ *
+ * The ADC Offset Correction Register (OFS) contains the user-selected or
+ * calibration-generated offset error correction value. This register is a 2's
+ * complement, left-justified, 16-bit value . The value in OFS is subtracted from the
+ * conversion and the result is transferred into the result registers, Rn. If the
+ * result is greater than the maximum or less than the minimum result value, it is
+ * forced to the appropriate limit for the current mode of operation.
+ */
+typedef union _hw_adc_ofs
+{
+ uint32_t U;
+ struct _hw_adc_ofs_bitfields
+ {
+ uint32_t OFS : 16; //!< [15:0] Offset Error Correction Value
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_adc_ofs_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_OFS register
+ */
+//@{
+#define HW_ADC_OFS_ADDR(x) (REGS_ADC_BASE(x) + 0x28U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_OFS(x) (*(__IO hw_adc_ofs_t *) HW_ADC_OFS_ADDR(x))
+#define HW_ADC_OFS_RD(x) (HW_ADC_OFS(x).U)
+#define HW_ADC_OFS_WR(x, v) (HW_ADC_OFS(x).U = (v))
+#define HW_ADC_OFS_SET(x, v) (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) | (v)))
+#define HW_ADC_OFS_CLR(x, v) (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) & ~(v)))
+#define HW_ADC_OFS_TOG(x, v) (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_OFS bitfields
+ */
+
+/*!
+ * @name Register ADC_OFS, field OFS[15:0] (RW)
+ */
+//@{
+#define BP_ADC_OFS_OFS (0U) //!< Bit position for ADC_OFS_OFS.
+#define BM_ADC_OFS_OFS (0x0000FFFFU) //!< Bit mask for ADC_OFS_OFS.
+#define BS_ADC_OFS_OFS (16U) //!< Bit field size in bits for ADC_OFS_OFS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_OFS_OFS field.
+#define BR_ADC_OFS_OFS(x) (HW_ADC_OFS(x).B.OFS)
+#endif
+
+//! @brief Format value for bitfield ADC_OFS_OFS.
+#define BF_ADC_OFS_OFS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_OFS_OFS), uint32_t) & BM_ADC_OFS_OFS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OFS field to a new value.
+#define BW_ADC_OFS_OFS(x, v) (HW_ADC_OFS_WR(x, (HW_ADC_OFS_RD(x) & ~BM_ADC_OFS_OFS) | BF_ADC_OFS_OFS(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_PG - ADC Plus-Side Gain Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_PG - ADC Plus-Side Gain Register (RW)
+ *
+ * Reset value: 0x00008200U
+ *
+ * The Plus-Side Gain Register (PG) contains the gain error correction for the
+ * plus-side input in differential mode or the overall conversion in single-ended
+ * mode. PG, a 16-bit real number in binary format, is the gain adjustment
+ * factor, with the radix point fixed between ADPG15 and ADPG14. This register must be
+ * written by the user with the value described in the calibration procedure.
+ * Otherwise, the gain error specifications may not be met.
+ */
+typedef union _hw_adc_pg
+{
+ uint32_t U;
+ struct _hw_adc_pg_bitfields
+ {
+ uint32_t PG : 16; //!< [15:0] Plus-Side Gain
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_adc_pg_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_PG register
+ */
+//@{
+#define HW_ADC_PG_ADDR(x) (REGS_ADC_BASE(x) + 0x2CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_PG(x) (*(__IO hw_adc_pg_t *) HW_ADC_PG_ADDR(x))
+#define HW_ADC_PG_RD(x) (HW_ADC_PG(x).U)
+#define HW_ADC_PG_WR(x, v) (HW_ADC_PG(x).U = (v))
+#define HW_ADC_PG_SET(x, v) (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) | (v)))
+#define HW_ADC_PG_CLR(x, v) (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) & ~(v)))
+#define HW_ADC_PG_TOG(x, v) (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_PG bitfields
+ */
+
+/*!
+ * @name Register ADC_PG, field PG[15:0] (RW)
+ */
+//@{
+#define BP_ADC_PG_PG (0U) //!< Bit position for ADC_PG_PG.
+#define BM_ADC_PG_PG (0x0000FFFFU) //!< Bit mask for ADC_PG_PG.
+#define BS_ADC_PG_PG (16U) //!< Bit field size in bits for ADC_PG_PG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_PG_PG field.
+#define BR_ADC_PG_PG(x) (HW_ADC_PG(x).B.PG)
+#endif
+
+//! @brief Format value for bitfield ADC_PG_PG.
+#define BF_ADC_PG_PG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_PG_PG), uint32_t) & BM_ADC_PG_PG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PG field to a new value.
+#define BW_ADC_PG_PG(x, v) (HW_ADC_PG_WR(x, (HW_ADC_PG_RD(x) & ~BM_ADC_PG_PG) | BF_ADC_PG_PG(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_MG - ADC Minus-Side Gain Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_MG - ADC Minus-Side Gain Register (RW)
+ *
+ * Reset value: 0x00008200U
+ *
+ * The Minus-Side Gain Register (MG) contains the gain error correction for the
+ * minus-side input in differential mode. This register is ignored in
+ * single-ended mode. MG, a 16-bit real number in binary format, is the gain adjustment
+ * factor, with the radix point fixed between ADMG15 and ADMG14. This register must
+ * be written by the user with the value described in the calibration procedure.
+ * Otherwise, the gain error specifications may not be met.
+ */
+typedef union _hw_adc_mg
+{
+ uint32_t U;
+ struct _hw_adc_mg_bitfields
+ {
+ uint32_t MG : 16; //!< [15:0] Minus-Side Gain
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_adc_mg_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_MG register
+ */
+//@{
+#define HW_ADC_MG_ADDR(x) (REGS_ADC_BASE(x) + 0x30U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_MG(x) (*(__IO hw_adc_mg_t *) HW_ADC_MG_ADDR(x))
+#define HW_ADC_MG_RD(x) (HW_ADC_MG(x).U)
+#define HW_ADC_MG_WR(x, v) (HW_ADC_MG(x).U = (v))
+#define HW_ADC_MG_SET(x, v) (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) | (v)))
+#define HW_ADC_MG_CLR(x, v) (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) & ~(v)))
+#define HW_ADC_MG_TOG(x, v) (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_MG bitfields
+ */
+
+/*!
+ * @name Register ADC_MG, field MG[15:0] (RW)
+ */
+//@{
+#define BP_ADC_MG_MG (0U) //!< Bit position for ADC_MG_MG.
+#define BM_ADC_MG_MG (0x0000FFFFU) //!< Bit mask for ADC_MG_MG.
+#define BS_ADC_MG_MG (16U) //!< Bit field size in bits for ADC_MG_MG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_MG_MG field.
+#define BR_ADC_MG_MG(x) (HW_ADC_MG(x).B.MG)
+#endif
+
+//! @brief Format value for bitfield ADC_MG_MG.
+#define BF_ADC_MG_MG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_MG_MG), uint32_t) & BM_ADC_MG_MG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MG field to a new value.
+#define BW_ADC_MG_MG(x, v) (HW_ADC_MG_WR(x, (HW_ADC_MG_RD(x) & ~BM_ADC_MG_MG) | BF_ADC_MG_MG(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x0000000AU
+ *
+ * The Plus-Side General Calibration Value Registers (CLPx) contain calibration
+ * information that is generated by the calibration function. These registers
+ * contain seven calibration values of varying widths: CLP0[5:0], CLP1[6:0],
+ * CLP2[7:0], CLP3[8:0], CLP4[9:0], CLPS[5:0], and CLPD[5:0]. CLPx are automatically set
+ * when the self-calibration sequence is done, that is, CAL is cleared. If these
+ * registers are written by the user after calibration, the linearity error
+ * specifications may not be met.
+ */
+typedef union _hw_adc_clpd
+{
+ uint32_t U;
+ struct _hw_adc_clpd_bitfields
+ {
+ uint32_t CLPD : 6; //!< [5:0]
+ uint32_t RESERVED0 : 26; //!< [31:6]
+ } B;
+} hw_adc_clpd_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CLPD register
+ */
+//@{
+#define HW_ADC_CLPD_ADDR(x) (REGS_ADC_BASE(x) + 0x34U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CLPD(x) (*(__IO hw_adc_clpd_t *) HW_ADC_CLPD_ADDR(x))
+#define HW_ADC_CLPD_RD(x) (HW_ADC_CLPD(x).U)
+#define HW_ADC_CLPD_WR(x, v) (HW_ADC_CLPD(x).U = (v))
+#define HW_ADC_CLPD_SET(x, v) (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) | (v)))
+#define HW_ADC_CLPD_CLR(x, v) (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) & ~(v)))
+#define HW_ADC_CLPD_TOG(x, v) (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CLPD bitfields
+ */
+
+/*!
+ * @name Register ADC_CLPD, field CLPD[5:0] (RW)
+ *
+ * Calibration Value
+ */
+//@{
+#define BP_ADC_CLPD_CLPD (0U) //!< Bit position for ADC_CLPD_CLPD.
+#define BM_ADC_CLPD_CLPD (0x0000003FU) //!< Bit mask for ADC_CLPD_CLPD.
+#define BS_ADC_CLPD_CLPD (6U) //!< Bit field size in bits for ADC_CLPD_CLPD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CLPD_CLPD field.
+#define BR_ADC_CLPD_CLPD(x) (HW_ADC_CLPD(x).B.CLPD)
+#endif
+
+//! @brief Format value for bitfield ADC_CLPD_CLPD.
+#define BF_ADC_CLPD_CLPD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLPD_CLPD), uint32_t) & BM_ADC_CLPD_CLPD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLPD field to a new value.
+#define BW_ADC_CLPD_CLPD(x, v) (HW_ADC_CLPD_WR(x, (HW_ADC_CLPD_RD(x) & ~BM_ADC_CLPD_CLPD) | BF_ADC_CLPD_CLPD(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLPD register description.
+ */
+typedef union _hw_adc_clps
+{
+ uint32_t U;
+ struct _hw_adc_clps_bitfields
+ {
+ uint32_t CLPS : 6; //!< [5:0]
+ uint32_t RESERVED0 : 26; //!< [31:6]
+ } B;
+} hw_adc_clps_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CLPS register
+ */
+//@{
+#define HW_ADC_CLPS_ADDR(x) (REGS_ADC_BASE(x) + 0x38U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CLPS(x) (*(__IO hw_adc_clps_t *) HW_ADC_CLPS_ADDR(x))
+#define HW_ADC_CLPS_RD(x) (HW_ADC_CLPS(x).U)
+#define HW_ADC_CLPS_WR(x, v) (HW_ADC_CLPS(x).U = (v))
+#define HW_ADC_CLPS_SET(x, v) (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) | (v)))
+#define HW_ADC_CLPS_CLR(x, v) (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) & ~(v)))
+#define HW_ADC_CLPS_TOG(x, v) (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CLPS bitfields
+ */
+
+/*!
+ * @name Register ADC_CLPS, field CLPS[5:0] (RW)
+ *
+ * Calibration Value
+ */
+//@{
+#define BP_ADC_CLPS_CLPS (0U) //!< Bit position for ADC_CLPS_CLPS.
+#define BM_ADC_CLPS_CLPS (0x0000003FU) //!< Bit mask for ADC_CLPS_CLPS.
+#define BS_ADC_CLPS_CLPS (6U) //!< Bit field size in bits for ADC_CLPS_CLPS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CLPS_CLPS field.
+#define BR_ADC_CLPS_CLPS(x) (HW_ADC_CLPS(x).B.CLPS)
+#endif
+
+//! @brief Format value for bitfield ADC_CLPS_CLPS.
+#define BF_ADC_CLPS_CLPS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLPS_CLPS), uint32_t) & BM_ADC_CLPS_CLPS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLPS field to a new value.
+#define BW_ADC_CLPS_CLPS(x, v) (HW_ADC_CLPS_WR(x, (HW_ADC_CLPS_RD(x) & ~BM_ADC_CLPS_CLPS) | BF_ADC_CLPS_CLPS(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000200U
+ *
+ * For more information, see CLPD register description.
+ */
+typedef union _hw_adc_clp4
+{
+ uint32_t U;
+ struct _hw_adc_clp4_bitfields
+ {
+ uint32_t CLP4 : 10; //!< [9:0]
+ uint32_t RESERVED0 : 22; //!< [31:10]
+ } B;
+} hw_adc_clp4_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CLP4 register
+ */
+//@{
+#define HW_ADC_CLP4_ADDR(x) (REGS_ADC_BASE(x) + 0x3CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CLP4(x) (*(__IO hw_adc_clp4_t *) HW_ADC_CLP4_ADDR(x))
+#define HW_ADC_CLP4_RD(x) (HW_ADC_CLP4(x).U)
+#define HW_ADC_CLP4_WR(x, v) (HW_ADC_CLP4(x).U = (v))
+#define HW_ADC_CLP4_SET(x, v) (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) | (v)))
+#define HW_ADC_CLP4_CLR(x, v) (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) & ~(v)))
+#define HW_ADC_CLP4_TOG(x, v) (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CLP4 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP4, field CLP4[9:0] (RW)
+ *
+ * Calibration Value
+ */
+//@{
+#define BP_ADC_CLP4_CLP4 (0U) //!< Bit position for ADC_CLP4_CLP4.
+#define BM_ADC_CLP4_CLP4 (0x000003FFU) //!< Bit mask for ADC_CLP4_CLP4.
+#define BS_ADC_CLP4_CLP4 (10U) //!< Bit field size in bits for ADC_CLP4_CLP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CLP4_CLP4 field.
+#define BR_ADC_CLP4_CLP4(x) (HW_ADC_CLP4(x).B.CLP4)
+#endif
+
+//! @brief Format value for bitfield ADC_CLP4_CLP4.
+#define BF_ADC_CLP4_CLP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLP4_CLP4), uint32_t) & BM_ADC_CLP4_CLP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLP4 field to a new value.
+#define BW_ADC_CLP4_CLP4(x, v) (HW_ADC_CLP4_WR(x, (HW_ADC_CLP4_RD(x) & ~BM_ADC_CLP4_CLP4) | BF_ADC_CLP4_CLP4(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000100U
+ *
+ * For more information, see CLPD register description.
+ */
+typedef union _hw_adc_clp3
+{
+ uint32_t U;
+ struct _hw_adc_clp3_bitfields
+ {
+ uint32_t CLP3 : 9; //!< [8:0]
+ uint32_t RESERVED0 : 23; //!< [31:9]
+ } B;
+} hw_adc_clp3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CLP3 register
+ */
+//@{
+#define HW_ADC_CLP3_ADDR(x) (REGS_ADC_BASE(x) + 0x40U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CLP3(x) (*(__IO hw_adc_clp3_t *) HW_ADC_CLP3_ADDR(x))
+#define HW_ADC_CLP3_RD(x) (HW_ADC_CLP3(x).U)
+#define HW_ADC_CLP3_WR(x, v) (HW_ADC_CLP3(x).U = (v))
+#define HW_ADC_CLP3_SET(x, v) (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) | (v)))
+#define HW_ADC_CLP3_CLR(x, v) (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) & ~(v)))
+#define HW_ADC_CLP3_TOG(x, v) (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CLP3 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP3, field CLP3[8:0] (RW)
+ *
+ * Calibration Value
+ */
+//@{
+#define BP_ADC_CLP3_CLP3 (0U) //!< Bit position for ADC_CLP3_CLP3.
+#define BM_ADC_CLP3_CLP3 (0x000001FFU) //!< Bit mask for ADC_CLP3_CLP3.
+#define BS_ADC_CLP3_CLP3 (9U) //!< Bit field size in bits for ADC_CLP3_CLP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CLP3_CLP3 field.
+#define BR_ADC_CLP3_CLP3(x) (HW_ADC_CLP3(x).B.CLP3)
+#endif
+
+//! @brief Format value for bitfield ADC_CLP3_CLP3.
+#define BF_ADC_CLP3_CLP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLP3_CLP3), uint32_t) & BM_ADC_CLP3_CLP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLP3 field to a new value.
+#define BW_ADC_CLP3_CLP3(x, v) (HW_ADC_CLP3_WR(x, (HW_ADC_CLP3_RD(x) & ~BM_ADC_CLP3_CLP3) | BF_ADC_CLP3_CLP3(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000080U
+ *
+ * For more information, see CLPD register description.
+ */
+typedef union _hw_adc_clp2
+{
+ uint32_t U;
+ struct _hw_adc_clp2_bitfields
+ {
+ uint32_t CLP2 : 8; //!< [7:0]
+ uint32_t RESERVED0 : 24; //!< [31:8]
+ } B;
+} hw_adc_clp2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CLP2 register
+ */
+//@{
+#define HW_ADC_CLP2_ADDR(x) (REGS_ADC_BASE(x) + 0x44U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CLP2(x) (*(__IO hw_adc_clp2_t *) HW_ADC_CLP2_ADDR(x))
+#define HW_ADC_CLP2_RD(x) (HW_ADC_CLP2(x).U)
+#define HW_ADC_CLP2_WR(x, v) (HW_ADC_CLP2(x).U = (v))
+#define HW_ADC_CLP2_SET(x, v) (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) | (v)))
+#define HW_ADC_CLP2_CLR(x, v) (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) & ~(v)))
+#define HW_ADC_CLP2_TOG(x, v) (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CLP2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP2, field CLP2[7:0] (RW)
+ *
+ * Calibration Value
+ */
+//@{
+#define BP_ADC_CLP2_CLP2 (0U) //!< Bit position for ADC_CLP2_CLP2.
+#define BM_ADC_CLP2_CLP2 (0x000000FFU) //!< Bit mask for ADC_CLP2_CLP2.
+#define BS_ADC_CLP2_CLP2 (8U) //!< Bit field size in bits for ADC_CLP2_CLP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CLP2_CLP2 field.
+#define BR_ADC_CLP2_CLP2(x) (HW_ADC_CLP2(x).B.CLP2)
+#endif
+
+//! @brief Format value for bitfield ADC_CLP2_CLP2.
+#define BF_ADC_CLP2_CLP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLP2_CLP2), uint32_t) & BM_ADC_CLP2_CLP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLP2 field to a new value.
+#define BW_ADC_CLP2_CLP2(x, v) (HW_ADC_CLP2_WR(x, (HW_ADC_CLP2_RD(x) & ~BM_ADC_CLP2_CLP2) | BF_ADC_CLP2_CLP2(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000040U
+ *
+ * For more information, see CLPD register description.
+ */
+typedef union _hw_adc_clp1
+{
+ uint32_t U;
+ struct _hw_adc_clp1_bitfields
+ {
+ uint32_t CLP1 : 7; //!< [6:0]
+ uint32_t RESERVED0 : 25; //!< [31:7]
+ } B;
+} hw_adc_clp1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CLP1 register
+ */
+//@{
+#define HW_ADC_CLP1_ADDR(x) (REGS_ADC_BASE(x) + 0x48U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CLP1(x) (*(__IO hw_adc_clp1_t *) HW_ADC_CLP1_ADDR(x))
+#define HW_ADC_CLP1_RD(x) (HW_ADC_CLP1(x).U)
+#define HW_ADC_CLP1_WR(x, v) (HW_ADC_CLP1(x).U = (v))
+#define HW_ADC_CLP1_SET(x, v) (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) | (v)))
+#define HW_ADC_CLP1_CLR(x, v) (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) & ~(v)))
+#define HW_ADC_CLP1_TOG(x, v) (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CLP1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP1, field CLP1[6:0] (RW)
+ *
+ * Calibration Value
+ */
+//@{
+#define BP_ADC_CLP1_CLP1 (0U) //!< Bit position for ADC_CLP1_CLP1.
+#define BM_ADC_CLP1_CLP1 (0x0000007FU) //!< Bit mask for ADC_CLP1_CLP1.
+#define BS_ADC_CLP1_CLP1 (7U) //!< Bit field size in bits for ADC_CLP1_CLP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CLP1_CLP1 field.
+#define BR_ADC_CLP1_CLP1(x) (HW_ADC_CLP1(x).B.CLP1)
+#endif
+
+//! @brief Format value for bitfield ADC_CLP1_CLP1.
+#define BF_ADC_CLP1_CLP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLP1_CLP1), uint32_t) & BM_ADC_CLP1_CLP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLP1 field to a new value.
+#define BW_ADC_CLP1_CLP1(x, v) (HW_ADC_CLP1_WR(x, (HW_ADC_CLP1_RD(x) & ~BM_ADC_CLP1_CLP1) | BF_ADC_CLP1_CLP1(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLPD register description.
+ */
+typedef union _hw_adc_clp0
+{
+ uint32_t U;
+ struct _hw_adc_clp0_bitfields
+ {
+ uint32_t CLP0 : 6; //!< [5:0]
+ uint32_t RESERVED0 : 26; //!< [31:6]
+ } B;
+} hw_adc_clp0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CLP0 register
+ */
+//@{
+#define HW_ADC_CLP0_ADDR(x) (REGS_ADC_BASE(x) + 0x4CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CLP0(x) (*(__IO hw_adc_clp0_t *) HW_ADC_CLP0_ADDR(x))
+#define HW_ADC_CLP0_RD(x) (HW_ADC_CLP0(x).U)
+#define HW_ADC_CLP0_WR(x, v) (HW_ADC_CLP0(x).U = (v))
+#define HW_ADC_CLP0_SET(x, v) (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) | (v)))
+#define HW_ADC_CLP0_CLR(x, v) (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) & ~(v)))
+#define HW_ADC_CLP0_TOG(x, v) (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CLP0 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP0, field CLP0[5:0] (RW)
+ *
+ * Calibration Value
+ */
+//@{
+#define BP_ADC_CLP0_CLP0 (0U) //!< Bit position for ADC_CLP0_CLP0.
+#define BM_ADC_CLP0_CLP0 (0x0000003FU) //!< Bit mask for ADC_CLP0_CLP0.
+#define BS_ADC_CLP0_CLP0 (6U) //!< Bit field size in bits for ADC_CLP0_CLP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CLP0_CLP0 field.
+#define BR_ADC_CLP0_CLP0(x) (HW_ADC_CLP0(x).B.CLP0)
+#endif
+
+//! @brief Format value for bitfield ADC_CLP0_CLP0.
+#define BF_ADC_CLP0_CLP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLP0_CLP0), uint32_t) & BM_ADC_CLP0_CLP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLP0 field to a new value.
+#define BW_ADC_CLP0_CLP0(x, v) (HW_ADC_CLP0_WR(x, (HW_ADC_CLP0_RD(x) & ~BM_ADC_CLP0_CLP0) | BF_ADC_CLP0_CLP0(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x0000000AU
+ *
+ * The Minus-Side General Calibration Value (CLMx) registers contain calibration
+ * information that is generated by the calibration function. These registers
+ * contain seven calibration values of varying widths: CLM0[5:0], CLM1[6:0],
+ * CLM2[7:0], CLM3[8:0], CLM4[9:0], CLMS[5:0], and CLMD[5:0]. CLMx are automatically
+ * set when the self-calibration sequence is done, that is, CAL is cleared. If
+ * these registers are written by the user after calibration, the linearity error
+ * specifications may not be met.
+ */
+typedef union _hw_adc_clmd
+{
+ uint32_t U;
+ struct _hw_adc_clmd_bitfields
+ {
+ uint32_t CLMD : 6; //!< [5:0]
+ uint32_t RESERVED0 : 26; //!< [31:6]
+ } B;
+} hw_adc_clmd_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CLMD register
+ */
+//@{
+#define HW_ADC_CLMD_ADDR(x) (REGS_ADC_BASE(x) + 0x54U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CLMD(x) (*(__IO hw_adc_clmd_t *) HW_ADC_CLMD_ADDR(x))
+#define HW_ADC_CLMD_RD(x) (HW_ADC_CLMD(x).U)
+#define HW_ADC_CLMD_WR(x, v) (HW_ADC_CLMD(x).U = (v))
+#define HW_ADC_CLMD_SET(x, v) (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) | (v)))
+#define HW_ADC_CLMD_CLR(x, v) (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) & ~(v)))
+#define HW_ADC_CLMD_TOG(x, v) (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CLMD bitfields
+ */
+
+/*!
+ * @name Register ADC_CLMD, field CLMD[5:0] (RW)
+ *
+ * Calibration Value
+ */
+//@{
+#define BP_ADC_CLMD_CLMD (0U) //!< Bit position for ADC_CLMD_CLMD.
+#define BM_ADC_CLMD_CLMD (0x0000003FU) //!< Bit mask for ADC_CLMD_CLMD.
+#define BS_ADC_CLMD_CLMD (6U) //!< Bit field size in bits for ADC_CLMD_CLMD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CLMD_CLMD field.
+#define BR_ADC_CLMD_CLMD(x) (HW_ADC_CLMD(x).B.CLMD)
+#endif
+
+//! @brief Format value for bitfield ADC_CLMD_CLMD.
+#define BF_ADC_CLMD_CLMD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLMD_CLMD), uint32_t) & BM_ADC_CLMD_CLMD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLMD field to a new value.
+#define BW_ADC_CLMD_CLMD(x, v) (HW_ADC_CLMD_WR(x, (HW_ADC_CLMD_RD(x) & ~BM_ADC_CLMD_CLMD) | BF_ADC_CLMD_CLMD(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLMD register description.
+ */
+typedef union _hw_adc_clms
+{
+ uint32_t U;
+ struct _hw_adc_clms_bitfields
+ {
+ uint32_t CLMS : 6; //!< [5:0]
+ uint32_t RESERVED0 : 26; //!< [31:6]
+ } B;
+} hw_adc_clms_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CLMS register
+ */
+//@{
+#define HW_ADC_CLMS_ADDR(x) (REGS_ADC_BASE(x) + 0x58U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CLMS(x) (*(__IO hw_adc_clms_t *) HW_ADC_CLMS_ADDR(x))
+#define HW_ADC_CLMS_RD(x) (HW_ADC_CLMS(x).U)
+#define HW_ADC_CLMS_WR(x, v) (HW_ADC_CLMS(x).U = (v))
+#define HW_ADC_CLMS_SET(x, v) (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) | (v)))
+#define HW_ADC_CLMS_CLR(x, v) (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) & ~(v)))
+#define HW_ADC_CLMS_TOG(x, v) (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CLMS bitfields
+ */
+
+/*!
+ * @name Register ADC_CLMS, field CLMS[5:0] (RW)
+ *
+ * Calibration Value
+ */
+//@{
+#define BP_ADC_CLMS_CLMS (0U) //!< Bit position for ADC_CLMS_CLMS.
+#define BM_ADC_CLMS_CLMS (0x0000003FU) //!< Bit mask for ADC_CLMS_CLMS.
+#define BS_ADC_CLMS_CLMS (6U) //!< Bit field size in bits for ADC_CLMS_CLMS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CLMS_CLMS field.
+#define BR_ADC_CLMS_CLMS(x) (HW_ADC_CLMS(x).B.CLMS)
+#endif
+
+//! @brief Format value for bitfield ADC_CLMS_CLMS.
+#define BF_ADC_CLMS_CLMS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLMS_CLMS), uint32_t) & BM_ADC_CLMS_CLMS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLMS field to a new value.
+#define BW_ADC_CLMS_CLMS(x, v) (HW_ADC_CLMS_WR(x, (HW_ADC_CLMS_RD(x) & ~BM_ADC_CLMS_CLMS) | BF_ADC_CLMS_CLMS(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000200U
+ *
+ * For more information, see CLMD register description.
+ */
+typedef union _hw_adc_clm4
+{
+ uint32_t U;
+ struct _hw_adc_clm4_bitfields
+ {
+ uint32_t CLM4 : 10; //!< [9:0]
+ uint32_t RESERVED0 : 22; //!< [31:10]
+ } B;
+} hw_adc_clm4_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CLM4 register
+ */
+//@{
+#define HW_ADC_CLM4_ADDR(x) (REGS_ADC_BASE(x) + 0x5CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CLM4(x) (*(__IO hw_adc_clm4_t *) HW_ADC_CLM4_ADDR(x))
+#define HW_ADC_CLM4_RD(x) (HW_ADC_CLM4(x).U)
+#define HW_ADC_CLM4_WR(x, v) (HW_ADC_CLM4(x).U = (v))
+#define HW_ADC_CLM4_SET(x, v) (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) | (v)))
+#define HW_ADC_CLM4_CLR(x, v) (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) & ~(v)))
+#define HW_ADC_CLM4_TOG(x, v) (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CLM4 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM4, field CLM4[9:0] (RW)
+ *
+ * Calibration Value
+ */
+//@{
+#define BP_ADC_CLM4_CLM4 (0U) //!< Bit position for ADC_CLM4_CLM4.
+#define BM_ADC_CLM4_CLM4 (0x000003FFU) //!< Bit mask for ADC_CLM4_CLM4.
+#define BS_ADC_CLM4_CLM4 (10U) //!< Bit field size in bits for ADC_CLM4_CLM4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CLM4_CLM4 field.
+#define BR_ADC_CLM4_CLM4(x) (HW_ADC_CLM4(x).B.CLM4)
+#endif
+
+//! @brief Format value for bitfield ADC_CLM4_CLM4.
+#define BF_ADC_CLM4_CLM4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLM4_CLM4), uint32_t) & BM_ADC_CLM4_CLM4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLM4 field to a new value.
+#define BW_ADC_CLM4_CLM4(x, v) (HW_ADC_CLM4_WR(x, (HW_ADC_CLM4_RD(x) & ~BM_ADC_CLM4_CLM4) | BF_ADC_CLM4_CLM4(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000100U
+ *
+ * For more information, see CLMD register description.
+ */
+typedef union _hw_adc_clm3
+{
+ uint32_t U;
+ struct _hw_adc_clm3_bitfields
+ {
+ uint32_t CLM3 : 9; //!< [8:0]
+ uint32_t RESERVED0 : 23; //!< [31:9]
+ } B;
+} hw_adc_clm3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CLM3 register
+ */
+//@{
+#define HW_ADC_CLM3_ADDR(x) (REGS_ADC_BASE(x) + 0x60U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CLM3(x) (*(__IO hw_adc_clm3_t *) HW_ADC_CLM3_ADDR(x))
+#define HW_ADC_CLM3_RD(x) (HW_ADC_CLM3(x).U)
+#define HW_ADC_CLM3_WR(x, v) (HW_ADC_CLM3(x).U = (v))
+#define HW_ADC_CLM3_SET(x, v) (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) | (v)))
+#define HW_ADC_CLM3_CLR(x, v) (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) & ~(v)))
+#define HW_ADC_CLM3_TOG(x, v) (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CLM3 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM3, field CLM3[8:0] (RW)
+ *
+ * Calibration Value
+ */
+//@{
+#define BP_ADC_CLM3_CLM3 (0U) //!< Bit position for ADC_CLM3_CLM3.
+#define BM_ADC_CLM3_CLM3 (0x000001FFU) //!< Bit mask for ADC_CLM3_CLM3.
+#define BS_ADC_CLM3_CLM3 (9U) //!< Bit field size in bits for ADC_CLM3_CLM3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CLM3_CLM3 field.
+#define BR_ADC_CLM3_CLM3(x) (HW_ADC_CLM3(x).B.CLM3)
+#endif
+
+//! @brief Format value for bitfield ADC_CLM3_CLM3.
+#define BF_ADC_CLM3_CLM3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLM3_CLM3), uint32_t) & BM_ADC_CLM3_CLM3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLM3 field to a new value.
+#define BW_ADC_CLM3_CLM3(x, v) (HW_ADC_CLM3_WR(x, (HW_ADC_CLM3_RD(x) & ~BM_ADC_CLM3_CLM3) | BF_ADC_CLM3_CLM3(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000080U
+ *
+ * For more information, see CLMD register description.
+ */
+typedef union _hw_adc_clm2
+{
+ uint32_t U;
+ struct _hw_adc_clm2_bitfields
+ {
+ uint32_t CLM2 : 8; //!< [7:0]
+ uint32_t RESERVED0 : 24; //!< [31:8]
+ } B;
+} hw_adc_clm2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CLM2 register
+ */
+//@{
+#define HW_ADC_CLM2_ADDR(x) (REGS_ADC_BASE(x) + 0x64U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CLM2(x) (*(__IO hw_adc_clm2_t *) HW_ADC_CLM2_ADDR(x))
+#define HW_ADC_CLM2_RD(x) (HW_ADC_CLM2(x).U)
+#define HW_ADC_CLM2_WR(x, v) (HW_ADC_CLM2(x).U = (v))
+#define HW_ADC_CLM2_SET(x, v) (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) | (v)))
+#define HW_ADC_CLM2_CLR(x, v) (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) & ~(v)))
+#define HW_ADC_CLM2_TOG(x, v) (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CLM2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM2, field CLM2[7:0] (RW)
+ *
+ * Calibration Value
+ */
+//@{
+#define BP_ADC_CLM2_CLM2 (0U) //!< Bit position for ADC_CLM2_CLM2.
+#define BM_ADC_CLM2_CLM2 (0x000000FFU) //!< Bit mask for ADC_CLM2_CLM2.
+#define BS_ADC_CLM2_CLM2 (8U) //!< Bit field size in bits for ADC_CLM2_CLM2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CLM2_CLM2 field.
+#define BR_ADC_CLM2_CLM2(x) (HW_ADC_CLM2(x).B.CLM2)
+#endif
+
+//! @brief Format value for bitfield ADC_CLM2_CLM2.
+#define BF_ADC_CLM2_CLM2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLM2_CLM2), uint32_t) & BM_ADC_CLM2_CLM2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLM2 field to a new value.
+#define BW_ADC_CLM2_CLM2(x, v) (HW_ADC_CLM2_WR(x, (HW_ADC_CLM2_RD(x) & ~BM_ADC_CLM2_CLM2) | BF_ADC_CLM2_CLM2(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000040U
+ *
+ * For more information, see CLMD register description.
+ */
+typedef union _hw_adc_clm1
+{
+ uint32_t U;
+ struct _hw_adc_clm1_bitfields
+ {
+ uint32_t CLM1 : 7; //!< [6:0]
+ uint32_t RESERVED0 : 25; //!< [31:7]
+ } B;
+} hw_adc_clm1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CLM1 register
+ */
+//@{
+#define HW_ADC_CLM1_ADDR(x) (REGS_ADC_BASE(x) + 0x68U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CLM1(x) (*(__IO hw_adc_clm1_t *) HW_ADC_CLM1_ADDR(x))
+#define HW_ADC_CLM1_RD(x) (HW_ADC_CLM1(x).U)
+#define HW_ADC_CLM1_WR(x, v) (HW_ADC_CLM1(x).U = (v))
+#define HW_ADC_CLM1_SET(x, v) (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) | (v)))
+#define HW_ADC_CLM1_CLR(x, v) (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) & ~(v)))
+#define HW_ADC_CLM1_TOG(x, v) (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CLM1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM1, field CLM1[6:0] (RW)
+ *
+ * Calibration Value
+ */
+//@{
+#define BP_ADC_CLM1_CLM1 (0U) //!< Bit position for ADC_CLM1_CLM1.
+#define BM_ADC_CLM1_CLM1 (0x0000007FU) //!< Bit mask for ADC_CLM1_CLM1.
+#define BS_ADC_CLM1_CLM1 (7U) //!< Bit field size in bits for ADC_CLM1_CLM1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CLM1_CLM1 field.
+#define BR_ADC_CLM1_CLM1(x) (HW_ADC_CLM1(x).B.CLM1)
+#endif
+
+//! @brief Format value for bitfield ADC_CLM1_CLM1.
+#define BF_ADC_CLM1_CLM1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLM1_CLM1), uint32_t) & BM_ADC_CLM1_CLM1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLM1 field to a new value.
+#define BW_ADC_CLM1_CLM1(x, v) (HW_ADC_CLM1_WR(x, (HW_ADC_CLM1_RD(x) & ~BM_ADC_CLM1_CLM1) | BF_ADC_CLM1_CLM1(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLMD register description.
+ */
+typedef union _hw_adc_clm0
+{
+ uint32_t U;
+ struct _hw_adc_clm0_bitfields
+ {
+ uint32_t CLM0 : 6; //!< [5:0]
+ uint32_t RESERVED0 : 26; //!< [31:6]
+ } B;
+} hw_adc_clm0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ADC_CLM0 register
+ */
+//@{
+#define HW_ADC_CLM0_ADDR(x) (REGS_ADC_BASE(x) + 0x6CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ADC_CLM0(x) (*(__IO hw_adc_clm0_t *) HW_ADC_CLM0_ADDR(x))
+#define HW_ADC_CLM0_RD(x) (HW_ADC_CLM0(x).U)
+#define HW_ADC_CLM0_WR(x, v) (HW_ADC_CLM0(x).U = (v))
+#define HW_ADC_CLM0_SET(x, v) (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) | (v)))
+#define HW_ADC_CLM0_CLR(x, v) (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) & ~(v)))
+#define HW_ADC_CLM0_TOG(x, v) (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ADC_CLM0 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM0, field CLM0[5:0] (RW)
+ *
+ * Calibration Value
+ */
+//@{
+#define BP_ADC_CLM0_CLM0 (0U) //!< Bit position for ADC_CLM0_CLM0.
+#define BM_ADC_CLM0_CLM0 (0x0000003FU) //!< Bit mask for ADC_CLM0_CLM0.
+#define BS_ADC_CLM0_CLM0 (6U) //!< Bit field size in bits for ADC_CLM0_CLM0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ADC_CLM0_CLM0 field.
+#define BR_ADC_CLM0_CLM0(x) (HW_ADC_CLM0(x).B.CLM0)
+#endif
+
+//! @brief Format value for bitfield ADC_CLM0_CLM0.
+#define BF_ADC_CLM0_CLM0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ADC_CLM0_CLM0), uint32_t) & BM_ADC_CLM0_CLM0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLM0 field to a new value.
+#define BW_ADC_CLM0_CLM0(x, v) (HW_ADC_CLM0_WR(x, (HW_ADC_CLM0_RD(x) & ~BM_ADC_CLM0_CLM0) | BF_ADC_CLM0_CLM0(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_adc_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All ADC module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_adc
+{
+ __IO hw_adc_sc1n_t SC1n[2]; //!< [0x0] ADC Status and Control Registers 1
+ __IO hw_adc_cfg1_t CFG1; //!< [0x8] ADC Configuration Register 1
+ __IO hw_adc_cfg2_t CFG2; //!< [0xC] ADC Configuration Register 2
+ __I hw_adc_rn_t Rn[2]; //!< [0x10] ADC Data Result Register
+ __IO hw_adc_cv1_t CV1; //!< [0x18] Compare Value Registers
+ __IO hw_adc_cv2_t CV2; //!< [0x1C] Compare Value Registers
+ __IO hw_adc_sc2_t SC2; //!< [0x20] Status and Control Register 2
+ __IO hw_adc_sc3_t SC3; //!< [0x24] Status and Control Register 3
+ __IO hw_adc_ofs_t OFS; //!< [0x28] ADC Offset Correction Register
+ __IO hw_adc_pg_t PG; //!< [0x2C] ADC Plus-Side Gain Register
+ __IO hw_adc_mg_t MG; //!< [0x30] ADC Minus-Side Gain Register
+ __IO hw_adc_clpd_t CLPD; //!< [0x34] ADC Plus-Side General Calibration Value Register
+ __IO hw_adc_clps_t CLPS; //!< [0x38] ADC Plus-Side General Calibration Value Register
+ __IO hw_adc_clp4_t CLP4; //!< [0x3C] ADC Plus-Side General Calibration Value Register
+ __IO hw_adc_clp3_t CLP3; //!< [0x40] ADC Plus-Side General Calibration Value Register
+ __IO hw_adc_clp2_t CLP2; //!< [0x44] ADC Plus-Side General Calibration Value Register
+ __IO hw_adc_clp1_t CLP1; //!< [0x48] ADC Plus-Side General Calibration Value Register
+ __IO hw_adc_clp0_t CLP0; //!< [0x4C] ADC Plus-Side General Calibration Value Register
+ uint8_t _reserved0[4];
+ __IO hw_adc_clmd_t CLMD; //!< [0x54] ADC Minus-Side General Calibration Value Register
+ __IO hw_adc_clms_t CLMS; //!< [0x58] ADC Minus-Side General Calibration Value Register
+ __IO hw_adc_clm4_t CLM4; //!< [0x5C] ADC Minus-Side General Calibration Value Register
+ __IO hw_adc_clm3_t CLM3; //!< [0x60] ADC Minus-Side General Calibration Value Register
+ __IO hw_adc_clm2_t CLM2; //!< [0x64] ADC Minus-Side General Calibration Value Register
+ __IO hw_adc_clm1_t CLM1; //!< [0x68] ADC Minus-Side General Calibration Value Register
+ __IO hw_adc_clm0_t CLM0; //!< [0x6C] ADC Minus-Side General Calibration Value Register
+} hw_adc_t;
+#pragma pack()
+
+//! @brief Macro to access all ADC registers.
+//! @param x ADC instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_ADC(0)</code>.
+#define HW_ADC(x) (*(hw_adc_t *) REGS_ADC_BASE(x))
+#endif
+
+#endif // __HW_ADC_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_aips.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,14135 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_AIPS_REGISTERS_H__
+#define __HW_AIPS_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 AIPS
+ *
+ * AIPS-Lite Bridge
+ *
+ * Registers defined in this header file:
+ * - HW_AIPS_MPRA - Master Privilege Register A
+ * - HW_AIPS_PACRA - Peripheral Access Control Register
+ * - HW_AIPS_PACRB - Peripheral Access Control Register
+ * - HW_AIPS_PACRC - Peripheral Access Control Register
+ * - HW_AIPS_PACRD - Peripheral Access Control Register
+ * - HW_AIPS_PACRE - Peripheral Access Control Register
+ * - HW_AIPS_PACRF - Peripheral Access Control Register
+ * - HW_AIPS_PACRG - Peripheral Access Control Register
+ * - HW_AIPS_PACRH - Peripheral Access Control Register
+ * - HW_AIPS_PACRI - Peripheral Access Control Register
+ * - HW_AIPS_PACRJ - Peripheral Access Control Register
+ * - HW_AIPS_PACRK - Peripheral Access Control Register
+ * - HW_AIPS_PACRL - Peripheral Access Control Register
+ * - HW_AIPS_PACRM - Peripheral Access Control Register
+ * - HW_AIPS_PACRN - Peripheral Access Control Register
+ * - HW_AIPS_PACRO - Peripheral Access Control Register
+ * - HW_AIPS_PACRP - Peripheral Access Control Register
+ * - HW_AIPS_PACRU - Peripheral Access Control Register
+ *
+ * - hw_aips_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_AIPS_BASE
+#define HW_AIPS_INSTANCE_COUNT (2U) //!< Number of instances of the AIPS module.
+#define HW_AIPS0 (0U) //!< Instance number for AIPS0.
+#define HW_AIPS1 (1U) //!< Instance number for AIPS1.
+#define REGS_AIPS0_BASE (0x40000000U) //!< Base address for AIPS0.
+#define REGS_AIPS1_BASE (0x40080000U) //!< Base address for AIPS1.
+
+//! @brief Table of base addresses for AIPS instances.
+static const uint32_t __g_regs_AIPS_base_addresses[] = {
+ REGS_AIPS0_BASE,
+ REGS_AIPS1_BASE,
+ };
+
+//! @brief Get the base address of AIPS by instance number.
+//! @param x AIPS instance number, from 0 through 1.
+#define REGS_AIPS_BASE(x) (__g_regs_AIPS_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of AIPS.
+#define REGS_AIPS_INSTANCE(b) ((b) == REGS_AIPS0_BASE ? HW_AIPS0 : (b) == REGS_AIPS1_BASE ? HW_AIPS1 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_MPRA - Master Privilege Register A
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_MPRA - Master Privilege Register A (RW)
+ *
+ * Reset value: 0x77700000U
+ *
+ * The MPRA specifies identical 4-bit fields defining the access-privilege level
+ * associated with a bus master to various peripherals on the chip. The register
+ * provides one field per bus master. At reset, the default value loaded into
+ * the MPRA fields is chip-specific. See the chip configuration details for the
+ * value of a particular device. A register field that maps to an unimplemented
+ * master or peripheral behaves as read-only-zero. Each master is assigned a logical
+ * ID from 0 to 15. See the master logical ID assignment table in the
+ * chip-specific AIPS information.
+ */
+typedef union _hw_aips_mpra
+{
+ uint32_t U;
+ struct _hw_aips_mpra_bitfields
+ {
+ uint32_t RESERVED0 : 8; //!< [7:0]
+ uint32_t MPL5 : 1; //!< [8] Master 5 Privilege Level
+ uint32_t MTW5 : 1; //!< [9] Master 5 Trusted For Writes
+ uint32_t MTR5 : 1; //!< [10] Master 5 Trusted For Read
+ uint32_t RESERVED1 : 1; //!< [11]
+ uint32_t MPL4 : 1; //!< [12] Master 4 Privilege Level
+ uint32_t MTW4 : 1; //!< [13] Master 4 Trusted For Writes
+ uint32_t MTR4 : 1; //!< [14] Master 4 Trusted For Read
+ uint32_t RESERVED2 : 1; //!< [15]
+ uint32_t MPL3 : 1; //!< [16] Master 3 Privilege Level
+ uint32_t MTW3 : 1; //!< [17] Master 3 Trusted For Writes
+ uint32_t MTR3 : 1; //!< [18] Master 3 Trusted For Read
+ uint32_t RESERVED3 : 1; //!< [19]
+ uint32_t MPL2 : 1; //!< [20] Master 2 Privilege Level
+ uint32_t MTW2 : 1; //!< [21] Master 2 Trusted For Writes
+ uint32_t MTR2 : 1; //!< [22] Master 2 Trusted For Read
+ uint32_t RESERVED4 : 1; //!< [23]
+ uint32_t MPL1 : 1; //!< [24] Master 1 Privilege Level
+ uint32_t MTW1 : 1; //!< [25] Master 1 Trusted for Writes
+ uint32_t MTR1 : 1; //!< [26] Master 1 Trusted for Read
+ uint32_t RESERVED5 : 1; //!< [27]
+ uint32_t MPL0 : 1; //!< [28] Master 0 Privilege Level
+ uint32_t MTW0 : 1; //!< [29] Master 0 Trusted For Writes
+ uint32_t MTR0 : 1; //!< [30] Master 0 Trusted For Read
+ uint32_t RESERVED6 : 1; //!< [31]
+ } B;
+} hw_aips_mpra_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_MPRA register
+ */
+//@{
+#define HW_AIPS_MPRA_ADDR(x) (REGS_AIPS_BASE(x) + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_MPRA(x) (*(__IO hw_aips_mpra_t *) HW_AIPS_MPRA_ADDR(x))
+#define HW_AIPS_MPRA_RD(x) (HW_AIPS_MPRA(x).U)
+#define HW_AIPS_MPRA_WR(x, v) (HW_AIPS_MPRA(x).U = (v))
+#define HW_AIPS_MPRA_SET(x, v) (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) | (v)))
+#define HW_AIPS_MPRA_CLR(x, v) (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) & ~(v)))
+#define HW_AIPS_MPRA_TOG(x, v) (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_MPRA bitfields
+ */
+
+/*!
+ * @name Register AIPS_MPRA, field MPL5[8] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0 - Accesses from this master are forced to user-mode.
+ * - 1 - Accesses from this master are not forced to user-mode.
+ */
+//@{
+#define BP_AIPS_MPRA_MPL5 (8U) //!< Bit position for AIPS_MPRA_MPL5.
+#define BM_AIPS_MPRA_MPL5 (0x00000100U) //!< Bit mask for AIPS_MPRA_MPL5.
+#define BS_AIPS_MPRA_MPL5 (1U) //!< Bit field size in bits for AIPS_MPRA_MPL5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MPL5 field.
+#define BR_AIPS_MPRA_MPL5(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL5))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MPL5.
+#define BF_AIPS_MPRA_MPL5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MPL5), uint32_t) & BM_AIPS_MPRA_MPL5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MPL5 field to a new value.
+#define BW_AIPS_MPRA_MPL5(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MTW5[9] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0 - This master is not trusted for write accesses.
+ * - 1 - This master is trusted for write accesses.
+ */
+//@{
+#define BP_AIPS_MPRA_MTW5 (9U) //!< Bit position for AIPS_MPRA_MTW5.
+#define BM_AIPS_MPRA_MTW5 (0x00000200U) //!< Bit mask for AIPS_MPRA_MTW5.
+#define BS_AIPS_MPRA_MTW5 (1U) //!< Bit field size in bits for AIPS_MPRA_MTW5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MTW5 field.
+#define BR_AIPS_MPRA_MTW5(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW5))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MTW5.
+#define BF_AIPS_MPRA_MTW5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTW5), uint32_t) & BM_AIPS_MPRA_MTW5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MTW5 field to a new value.
+#define BW_AIPS_MPRA_MTW5(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MTR5[10] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0 - This master is not trusted for read accesses.
+ * - 1 - This master is trusted for read accesses.
+ */
+//@{
+#define BP_AIPS_MPRA_MTR5 (10U) //!< Bit position for AIPS_MPRA_MTR5.
+#define BM_AIPS_MPRA_MTR5 (0x00000400U) //!< Bit mask for AIPS_MPRA_MTR5.
+#define BS_AIPS_MPRA_MTR5 (1U) //!< Bit field size in bits for AIPS_MPRA_MTR5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MTR5 field.
+#define BR_AIPS_MPRA_MTR5(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR5))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MTR5.
+#define BF_AIPS_MPRA_MTR5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTR5), uint32_t) & BM_AIPS_MPRA_MTR5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MTR5 field to a new value.
+#define BW_AIPS_MPRA_MTR5(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MPL4[12] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0 - Accesses from this master are forced to user-mode.
+ * - 1 - Accesses from this master are not forced to user-mode.
+ */
+//@{
+#define BP_AIPS_MPRA_MPL4 (12U) //!< Bit position for AIPS_MPRA_MPL4.
+#define BM_AIPS_MPRA_MPL4 (0x00001000U) //!< Bit mask for AIPS_MPRA_MPL4.
+#define BS_AIPS_MPRA_MPL4 (1U) //!< Bit field size in bits for AIPS_MPRA_MPL4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MPL4 field.
+#define BR_AIPS_MPRA_MPL4(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL4))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MPL4.
+#define BF_AIPS_MPRA_MPL4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MPL4), uint32_t) & BM_AIPS_MPRA_MPL4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MPL4 field to a new value.
+#define BW_AIPS_MPRA_MPL4(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MTW4[13] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0 - This master is not trusted for write accesses.
+ * - 1 - This master is trusted for write accesses.
+ */
+//@{
+#define BP_AIPS_MPRA_MTW4 (13U) //!< Bit position for AIPS_MPRA_MTW4.
+#define BM_AIPS_MPRA_MTW4 (0x00002000U) //!< Bit mask for AIPS_MPRA_MTW4.
+#define BS_AIPS_MPRA_MTW4 (1U) //!< Bit field size in bits for AIPS_MPRA_MTW4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MTW4 field.
+#define BR_AIPS_MPRA_MTW4(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW4))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MTW4.
+#define BF_AIPS_MPRA_MTW4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTW4), uint32_t) & BM_AIPS_MPRA_MTW4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MTW4 field to a new value.
+#define BW_AIPS_MPRA_MTW4(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MTR4[14] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0 - This master is not trusted for read accesses.
+ * - 1 - This master is trusted for read accesses.
+ */
+//@{
+#define BP_AIPS_MPRA_MTR4 (14U) //!< Bit position for AIPS_MPRA_MTR4.
+#define BM_AIPS_MPRA_MTR4 (0x00004000U) //!< Bit mask for AIPS_MPRA_MTR4.
+#define BS_AIPS_MPRA_MTR4 (1U) //!< Bit field size in bits for AIPS_MPRA_MTR4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MTR4 field.
+#define BR_AIPS_MPRA_MTR4(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR4))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MTR4.
+#define BF_AIPS_MPRA_MTR4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTR4), uint32_t) & BM_AIPS_MPRA_MTR4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MTR4 field to a new value.
+#define BW_AIPS_MPRA_MTR4(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MPL3[16] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0 - Accesses from this master are forced to user-mode.
+ * - 1 - Accesses from this master are not forced to user-mode.
+ */
+//@{
+#define BP_AIPS_MPRA_MPL3 (16U) //!< Bit position for AIPS_MPRA_MPL3.
+#define BM_AIPS_MPRA_MPL3 (0x00010000U) //!< Bit mask for AIPS_MPRA_MPL3.
+#define BS_AIPS_MPRA_MPL3 (1U) //!< Bit field size in bits for AIPS_MPRA_MPL3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MPL3 field.
+#define BR_AIPS_MPRA_MPL3(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL3))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MPL3.
+#define BF_AIPS_MPRA_MPL3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MPL3), uint32_t) & BM_AIPS_MPRA_MPL3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MPL3 field to a new value.
+#define BW_AIPS_MPRA_MPL3(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MTW3[17] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0 - This master is not trusted for write accesses.
+ * - 1 - This master is trusted for write accesses.
+ */
+//@{
+#define BP_AIPS_MPRA_MTW3 (17U) //!< Bit position for AIPS_MPRA_MTW3.
+#define BM_AIPS_MPRA_MTW3 (0x00020000U) //!< Bit mask for AIPS_MPRA_MTW3.
+#define BS_AIPS_MPRA_MTW3 (1U) //!< Bit field size in bits for AIPS_MPRA_MTW3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MTW3 field.
+#define BR_AIPS_MPRA_MTW3(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW3))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MTW3.
+#define BF_AIPS_MPRA_MTW3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTW3), uint32_t) & BM_AIPS_MPRA_MTW3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MTW3 field to a new value.
+#define BW_AIPS_MPRA_MTW3(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MTR3[18] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0 - This master is not trusted for read accesses.
+ * - 1 - This master is trusted for read accesses.
+ */
+//@{
+#define BP_AIPS_MPRA_MTR3 (18U) //!< Bit position for AIPS_MPRA_MTR3.
+#define BM_AIPS_MPRA_MTR3 (0x00040000U) //!< Bit mask for AIPS_MPRA_MTR3.
+#define BS_AIPS_MPRA_MTR3 (1U) //!< Bit field size in bits for AIPS_MPRA_MTR3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MTR3 field.
+#define BR_AIPS_MPRA_MTR3(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR3))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MTR3.
+#define BF_AIPS_MPRA_MTR3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTR3), uint32_t) & BM_AIPS_MPRA_MTR3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MTR3 field to a new value.
+#define BW_AIPS_MPRA_MTR3(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MPL2[20] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0 - Accesses from this master are forced to user-mode.
+ * - 1 - Accesses from this master are not forced to user-mode.
+ */
+//@{
+#define BP_AIPS_MPRA_MPL2 (20U) //!< Bit position for AIPS_MPRA_MPL2.
+#define BM_AIPS_MPRA_MPL2 (0x00100000U) //!< Bit mask for AIPS_MPRA_MPL2.
+#define BS_AIPS_MPRA_MPL2 (1U) //!< Bit field size in bits for AIPS_MPRA_MPL2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MPL2 field.
+#define BR_AIPS_MPRA_MPL2(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL2))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MPL2.
+#define BF_AIPS_MPRA_MPL2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MPL2), uint32_t) & BM_AIPS_MPRA_MPL2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MPL2 field to a new value.
+#define BW_AIPS_MPRA_MPL2(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MTW2[21] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0 - This master is not trusted for write accesses.
+ * - 1 - This master is trusted for write accesses.
+ */
+//@{
+#define BP_AIPS_MPRA_MTW2 (21U) //!< Bit position for AIPS_MPRA_MTW2.
+#define BM_AIPS_MPRA_MTW2 (0x00200000U) //!< Bit mask for AIPS_MPRA_MTW2.
+#define BS_AIPS_MPRA_MTW2 (1U) //!< Bit field size in bits for AIPS_MPRA_MTW2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MTW2 field.
+#define BR_AIPS_MPRA_MTW2(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW2))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MTW2.
+#define BF_AIPS_MPRA_MTW2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTW2), uint32_t) & BM_AIPS_MPRA_MTW2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MTW2 field to a new value.
+#define BW_AIPS_MPRA_MTW2(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MTR2[22] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0 - This master is not trusted for read accesses.
+ * - 1 - This master is trusted for read accesses.
+ */
+//@{
+#define BP_AIPS_MPRA_MTR2 (22U) //!< Bit position for AIPS_MPRA_MTR2.
+#define BM_AIPS_MPRA_MTR2 (0x00400000U) //!< Bit mask for AIPS_MPRA_MTR2.
+#define BS_AIPS_MPRA_MTR2 (1U) //!< Bit field size in bits for AIPS_MPRA_MTR2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MTR2 field.
+#define BR_AIPS_MPRA_MTR2(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR2))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MTR2.
+#define BF_AIPS_MPRA_MTR2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTR2), uint32_t) & BM_AIPS_MPRA_MTR2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MTR2 field to a new value.
+#define BW_AIPS_MPRA_MTR2(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MPL1[24] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0 - Accesses from this master are forced to user-mode.
+ * - 1 - Accesses from this master are not forced to user-mode.
+ */
+//@{
+#define BP_AIPS_MPRA_MPL1 (24U) //!< Bit position for AIPS_MPRA_MPL1.
+#define BM_AIPS_MPRA_MPL1 (0x01000000U) //!< Bit mask for AIPS_MPRA_MPL1.
+#define BS_AIPS_MPRA_MPL1 (1U) //!< Bit field size in bits for AIPS_MPRA_MPL1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MPL1 field.
+#define BR_AIPS_MPRA_MPL1(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL1))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MPL1.
+#define BF_AIPS_MPRA_MPL1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MPL1), uint32_t) & BM_AIPS_MPRA_MPL1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MPL1 field to a new value.
+#define BW_AIPS_MPRA_MPL1(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MTW1[25] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0 - This master is not trusted for write accesses.
+ * - 1 - This master is trusted for write accesses.
+ */
+//@{
+#define BP_AIPS_MPRA_MTW1 (25U) //!< Bit position for AIPS_MPRA_MTW1.
+#define BM_AIPS_MPRA_MTW1 (0x02000000U) //!< Bit mask for AIPS_MPRA_MTW1.
+#define BS_AIPS_MPRA_MTW1 (1U) //!< Bit field size in bits for AIPS_MPRA_MTW1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MTW1 field.
+#define BR_AIPS_MPRA_MTW1(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW1))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MTW1.
+#define BF_AIPS_MPRA_MTW1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTW1), uint32_t) & BM_AIPS_MPRA_MTW1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MTW1 field to a new value.
+#define BW_AIPS_MPRA_MTW1(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MTR1[26] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0 - This master is not trusted for read accesses.
+ * - 1 - This master is trusted for read accesses.
+ */
+//@{
+#define BP_AIPS_MPRA_MTR1 (26U) //!< Bit position for AIPS_MPRA_MTR1.
+#define BM_AIPS_MPRA_MTR1 (0x04000000U) //!< Bit mask for AIPS_MPRA_MTR1.
+#define BS_AIPS_MPRA_MTR1 (1U) //!< Bit field size in bits for AIPS_MPRA_MTR1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MTR1 field.
+#define BR_AIPS_MPRA_MTR1(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR1))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MTR1.
+#define BF_AIPS_MPRA_MTR1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTR1), uint32_t) & BM_AIPS_MPRA_MTR1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MTR1 field to a new value.
+#define BW_AIPS_MPRA_MTR1(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MPL0[28] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0 - Accesses from this master are forced to user-mode.
+ * - 1 - Accesses from this master are not forced to user-mode.
+ */
+//@{
+#define BP_AIPS_MPRA_MPL0 (28U) //!< Bit position for AIPS_MPRA_MPL0.
+#define BM_AIPS_MPRA_MPL0 (0x10000000U) //!< Bit mask for AIPS_MPRA_MPL0.
+#define BS_AIPS_MPRA_MPL0 (1U) //!< Bit field size in bits for AIPS_MPRA_MPL0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MPL0 field.
+#define BR_AIPS_MPRA_MPL0(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL0))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MPL0.
+#define BF_AIPS_MPRA_MPL0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MPL0), uint32_t) & BM_AIPS_MPRA_MPL0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MPL0 field to a new value.
+#define BW_AIPS_MPRA_MPL0(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MTW0[29] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0 - This master is not trusted for write accesses.
+ * - 1 - This master is trusted for write accesses.
+ */
+//@{
+#define BP_AIPS_MPRA_MTW0 (29U) //!< Bit position for AIPS_MPRA_MTW0.
+#define BM_AIPS_MPRA_MTW0 (0x20000000U) //!< Bit mask for AIPS_MPRA_MTW0.
+#define BS_AIPS_MPRA_MTW0 (1U) //!< Bit field size in bits for AIPS_MPRA_MTW0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MTW0 field.
+#define BR_AIPS_MPRA_MTW0(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW0))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MTW0.
+#define BF_AIPS_MPRA_MTW0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTW0), uint32_t) & BM_AIPS_MPRA_MTW0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MTW0 field to a new value.
+#define BW_AIPS_MPRA_MTW0(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_MPRA, field MTR0[30] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0 - This master is not trusted for read accesses.
+ * - 1 - This master is trusted for read accesses.
+ */
+//@{
+#define BP_AIPS_MPRA_MTR0 (30U) //!< Bit position for AIPS_MPRA_MTR0.
+#define BM_AIPS_MPRA_MTR0 (0x40000000U) //!< Bit mask for AIPS_MPRA_MTR0.
+#define BS_AIPS_MPRA_MTR0 (1U) //!< Bit field size in bits for AIPS_MPRA_MTR0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_MPRA_MTR0 field.
+#define BR_AIPS_MPRA_MTR0(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR0))
+#endif
+
+//! @brief Format value for bitfield AIPS_MPRA_MTR0.
+#define BF_AIPS_MPRA_MTR0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_MPRA_MTR0), uint32_t) & BM_AIPS_MPRA_MTR0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MTR0 field to a new value.
+#define BW_AIPS_MPRA_MTR0(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRA - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRA - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x50004000U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+typedef union _hw_aips_pacra
+{
+ uint32_t U;
+ struct _hw_aips_pacra_bitfields
+ {
+ uint32_t TP7 : 1; //!< [0] Trusted Protect
+ uint32_t WP7 : 1; //!< [1] Write Protect
+ uint32_t SP7 : 1; //!< [2] Supervisor Protect
+ uint32_t RESERVED0 : 1; //!< [3]
+ uint32_t TP6 : 1; //!< [4] Trusted Protect
+ uint32_t WP6 : 1; //!< [5] Write Protect
+ uint32_t SP6 : 1; //!< [6] Supervisor Protect
+ uint32_t RESERVED1 : 1; //!< [7]
+ uint32_t TP5 : 1; //!< [8] Trusted Protect
+ uint32_t WP5 : 1; //!< [9] Write Protect
+ uint32_t SP5 : 1; //!< [10] Supervisor Protect
+ uint32_t RESERVED2 : 1; //!< [11]
+ uint32_t TP4 : 1; //!< [12] Trusted Protect
+ uint32_t WP4 : 1; //!< [13] Write Protect
+ uint32_t SP4 : 1; //!< [14] Supervisor Protect
+ uint32_t RESERVED3 : 1; //!< [15]
+ uint32_t TP3 : 1; //!< [16] Trusted Protect
+ uint32_t WP3 : 1; //!< [17] Write Protect
+ uint32_t SP3 : 1; //!< [18] Supervisor Protect
+ uint32_t RESERVED4 : 1; //!< [19]
+ uint32_t TP2 : 1; //!< [20] Trusted Protect
+ uint32_t WP2 : 1; //!< [21] Write Protect
+ uint32_t SP2 : 1; //!< [22] Supervisor Protect
+ uint32_t RESERVED5 : 1; //!< [23]
+ uint32_t TP1 : 1; //!< [24] Trusted Protect
+ uint32_t WP1 : 1; //!< [25] Write Protect
+ uint32_t SP1 : 1; //!< [26] Supervisor Protect
+ uint32_t RESERVED6 : 1; //!< [27]
+ uint32_t TP0 : 1; //!< [28] Trusted Protect
+ uint32_t WP0 : 1; //!< [29] Write Protect
+ uint32_t SP0 : 1; //!< [30] Supervisor Protect
+ uint32_t RESERVED7 : 1; //!< [31]
+ } B;
+} hw_aips_pacra_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRA register
+ */
+//@{
+#define HW_AIPS_PACRA_ADDR(x) (REGS_AIPS_BASE(x) + 0x20U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRA(x) (*(__IO hw_aips_pacra_t *) HW_AIPS_PACRA_ADDR(x))
+#define HW_AIPS_PACRA_RD(x) (HW_AIPS_PACRA(x).U)
+#define HW_AIPS_PACRA_WR(x, v) (HW_AIPS_PACRA(x).U = (v))
+#define HW_AIPS_PACRA_SET(x, v) (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) | (v)))
+#define HW_AIPS_PACRA_CLR(x, v) (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) & ~(v)))
+#define HW_AIPS_PACRA_TOG(x, v) (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRA bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRA, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRA_TP7 (0U) //!< Bit position for AIPS_PACRA_TP7.
+#define BM_AIPS_PACRA_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRA_TP7.
+#define BS_AIPS_PACRA_TP7 (1U) //!< Bit field size in bits for AIPS_PACRA_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_TP7 field.
+#define BR_AIPS_PACRA_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_TP7.
+#define BF_AIPS_PACRA_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP7), uint32_t) & BM_AIPS_PACRA_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRA_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRA_WP7 (1U) //!< Bit position for AIPS_PACRA_WP7.
+#define BM_AIPS_PACRA_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRA_WP7.
+#define BS_AIPS_PACRA_WP7 (1U) //!< Bit field size in bits for AIPS_PACRA_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_WP7 field.
+#define BR_AIPS_PACRA_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_WP7.
+#define BF_AIPS_PACRA_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP7), uint32_t) & BM_AIPS_PACRA_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRA_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRA_SP7 (2U) //!< Bit position for AIPS_PACRA_SP7.
+#define BM_AIPS_PACRA_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRA_SP7.
+#define BS_AIPS_PACRA_SP7 (1U) //!< Bit field size in bits for AIPS_PACRA_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_SP7 field.
+#define BR_AIPS_PACRA_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_SP7.
+#define BF_AIPS_PACRA_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP7), uint32_t) & BM_AIPS_PACRA_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRA_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRA_TP6 (4U) //!< Bit position for AIPS_PACRA_TP6.
+#define BM_AIPS_PACRA_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRA_TP6.
+#define BS_AIPS_PACRA_TP6 (1U) //!< Bit field size in bits for AIPS_PACRA_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_TP6 field.
+#define BR_AIPS_PACRA_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_TP6.
+#define BF_AIPS_PACRA_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP6), uint32_t) & BM_AIPS_PACRA_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRA_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRA_WP6 (5U) //!< Bit position for AIPS_PACRA_WP6.
+#define BM_AIPS_PACRA_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRA_WP6.
+#define BS_AIPS_PACRA_WP6 (1U) //!< Bit field size in bits for AIPS_PACRA_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_WP6 field.
+#define BR_AIPS_PACRA_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_WP6.
+#define BF_AIPS_PACRA_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP6), uint32_t) & BM_AIPS_PACRA_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRA_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRA_SP6 (6U) //!< Bit position for AIPS_PACRA_SP6.
+#define BM_AIPS_PACRA_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRA_SP6.
+#define BS_AIPS_PACRA_SP6 (1U) //!< Bit field size in bits for AIPS_PACRA_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_SP6 field.
+#define BR_AIPS_PACRA_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_SP6.
+#define BF_AIPS_PACRA_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP6), uint32_t) & BM_AIPS_PACRA_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRA_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRA_TP5 (8U) //!< Bit position for AIPS_PACRA_TP5.
+#define BM_AIPS_PACRA_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRA_TP5.
+#define BS_AIPS_PACRA_TP5 (1U) //!< Bit field size in bits for AIPS_PACRA_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_TP5 field.
+#define BR_AIPS_PACRA_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_TP5.
+#define BF_AIPS_PACRA_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP5), uint32_t) & BM_AIPS_PACRA_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRA_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRA_WP5 (9U) //!< Bit position for AIPS_PACRA_WP5.
+#define BM_AIPS_PACRA_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRA_WP5.
+#define BS_AIPS_PACRA_WP5 (1U) //!< Bit field size in bits for AIPS_PACRA_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_WP5 field.
+#define BR_AIPS_PACRA_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_WP5.
+#define BF_AIPS_PACRA_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP5), uint32_t) & BM_AIPS_PACRA_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRA_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRA_SP5 (10U) //!< Bit position for AIPS_PACRA_SP5.
+#define BM_AIPS_PACRA_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRA_SP5.
+#define BS_AIPS_PACRA_SP5 (1U) //!< Bit field size in bits for AIPS_PACRA_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_SP5 field.
+#define BR_AIPS_PACRA_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_SP5.
+#define BF_AIPS_PACRA_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP5), uint32_t) & BM_AIPS_PACRA_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRA_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRA_TP4 (12U) //!< Bit position for AIPS_PACRA_TP4.
+#define BM_AIPS_PACRA_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRA_TP4.
+#define BS_AIPS_PACRA_TP4 (1U) //!< Bit field size in bits for AIPS_PACRA_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_TP4 field.
+#define BR_AIPS_PACRA_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_TP4.
+#define BF_AIPS_PACRA_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP4), uint32_t) & BM_AIPS_PACRA_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRA_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRA_WP4 (13U) //!< Bit position for AIPS_PACRA_WP4.
+#define BM_AIPS_PACRA_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRA_WP4.
+#define BS_AIPS_PACRA_WP4 (1U) //!< Bit field size in bits for AIPS_PACRA_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_WP4 field.
+#define BR_AIPS_PACRA_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_WP4.
+#define BF_AIPS_PACRA_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP4), uint32_t) & BM_AIPS_PACRA_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRA_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRA_SP4 (14U) //!< Bit position for AIPS_PACRA_SP4.
+#define BM_AIPS_PACRA_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRA_SP4.
+#define BS_AIPS_PACRA_SP4 (1U) //!< Bit field size in bits for AIPS_PACRA_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_SP4 field.
+#define BR_AIPS_PACRA_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_SP4.
+#define BF_AIPS_PACRA_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP4), uint32_t) & BM_AIPS_PACRA_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRA_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRA_TP3 (16U) //!< Bit position for AIPS_PACRA_TP3.
+#define BM_AIPS_PACRA_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRA_TP3.
+#define BS_AIPS_PACRA_TP3 (1U) //!< Bit field size in bits for AIPS_PACRA_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_TP3 field.
+#define BR_AIPS_PACRA_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_TP3.
+#define BF_AIPS_PACRA_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP3), uint32_t) & BM_AIPS_PACRA_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRA_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRA_WP3 (17U) //!< Bit position for AIPS_PACRA_WP3.
+#define BM_AIPS_PACRA_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRA_WP3.
+#define BS_AIPS_PACRA_WP3 (1U) //!< Bit field size in bits for AIPS_PACRA_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_WP3 field.
+#define BR_AIPS_PACRA_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_WP3.
+#define BF_AIPS_PACRA_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP3), uint32_t) & BM_AIPS_PACRA_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRA_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRA_SP3 (18U) //!< Bit position for AIPS_PACRA_SP3.
+#define BM_AIPS_PACRA_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRA_SP3.
+#define BS_AIPS_PACRA_SP3 (1U) //!< Bit field size in bits for AIPS_PACRA_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_SP3 field.
+#define BR_AIPS_PACRA_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_SP3.
+#define BF_AIPS_PACRA_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP3), uint32_t) & BM_AIPS_PACRA_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRA_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRA_TP2 (20U) //!< Bit position for AIPS_PACRA_TP2.
+#define BM_AIPS_PACRA_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRA_TP2.
+#define BS_AIPS_PACRA_TP2 (1U) //!< Bit field size in bits for AIPS_PACRA_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_TP2 field.
+#define BR_AIPS_PACRA_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_TP2.
+#define BF_AIPS_PACRA_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP2), uint32_t) & BM_AIPS_PACRA_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRA_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRA_WP2 (21U) //!< Bit position for AIPS_PACRA_WP2.
+#define BM_AIPS_PACRA_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRA_WP2.
+#define BS_AIPS_PACRA_WP2 (1U) //!< Bit field size in bits for AIPS_PACRA_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_WP2 field.
+#define BR_AIPS_PACRA_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_WP2.
+#define BF_AIPS_PACRA_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP2), uint32_t) & BM_AIPS_PACRA_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRA_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRA_SP2 (22U) //!< Bit position for AIPS_PACRA_SP2.
+#define BM_AIPS_PACRA_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRA_SP2.
+#define BS_AIPS_PACRA_SP2 (1U) //!< Bit field size in bits for AIPS_PACRA_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_SP2 field.
+#define BR_AIPS_PACRA_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_SP2.
+#define BF_AIPS_PACRA_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP2), uint32_t) & BM_AIPS_PACRA_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRA_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRA_TP1 (24U) //!< Bit position for AIPS_PACRA_TP1.
+#define BM_AIPS_PACRA_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRA_TP1.
+#define BS_AIPS_PACRA_TP1 (1U) //!< Bit field size in bits for AIPS_PACRA_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_TP1 field.
+#define BR_AIPS_PACRA_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_TP1.
+#define BF_AIPS_PACRA_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP1), uint32_t) & BM_AIPS_PACRA_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRA_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRA_WP1 (25U) //!< Bit position for AIPS_PACRA_WP1.
+#define BM_AIPS_PACRA_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRA_WP1.
+#define BS_AIPS_PACRA_WP1 (1U) //!< Bit field size in bits for AIPS_PACRA_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_WP1 field.
+#define BR_AIPS_PACRA_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_WP1.
+#define BF_AIPS_PACRA_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP1), uint32_t) & BM_AIPS_PACRA_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRA_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRA_SP1 (26U) //!< Bit position for AIPS_PACRA_SP1.
+#define BM_AIPS_PACRA_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRA_SP1.
+#define BS_AIPS_PACRA_SP1 (1U) //!< Bit field size in bits for AIPS_PACRA_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_SP1 field.
+#define BR_AIPS_PACRA_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_SP1.
+#define BF_AIPS_PACRA_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP1), uint32_t) & BM_AIPS_PACRA_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRA_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRA_TP0 (28U) //!< Bit position for AIPS_PACRA_TP0.
+#define BM_AIPS_PACRA_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRA_TP0.
+#define BS_AIPS_PACRA_TP0 (1U) //!< Bit field size in bits for AIPS_PACRA_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_TP0 field.
+#define BR_AIPS_PACRA_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_TP0.
+#define BF_AIPS_PACRA_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_TP0), uint32_t) & BM_AIPS_PACRA_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRA_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRA_WP0 (29U) //!< Bit position for AIPS_PACRA_WP0.
+#define BM_AIPS_PACRA_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRA_WP0.
+#define BS_AIPS_PACRA_WP0 (1U) //!< Bit field size in bits for AIPS_PACRA_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_WP0 field.
+#define BR_AIPS_PACRA_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_WP0.
+#define BF_AIPS_PACRA_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_WP0), uint32_t) & BM_AIPS_PACRA_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRA_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRA, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRA_SP0 (30U) //!< Bit position for AIPS_PACRA_SP0.
+#define BM_AIPS_PACRA_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRA_SP0.
+#define BS_AIPS_PACRA_SP0 (1U) //!< Bit field size in bits for AIPS_PACRA_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRA_SP0 field.
+#define BR_AIPS_PACRA_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRA_SP0.
+#define BF_AIPS_PACRA_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRA_SP0), uint32_t) & BM_AIPS_PACRA_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRA_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRB - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRB - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44004400U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+typedef union _hw_aips_pacrb
+{
+ uint32_t U;
+ struct _hw_aips_pacrb_bitfields
+ {
+ uint32_t TP7 : 1; //!< [0] Trusted Protect
+ uint32_t WP7 : 1; //!< [1] Write Protect
+ uint32_t SP7 : 1; //!< [2] Supervisor Protect
+ uint32_t RESERVED0 : 1; //!< [3]
+ uint32_t TP6 : 1; //!< [4] Trusted Protect
+ uint32_t WP6 : 1; //!< [5] Write Protect
+ uint32_t SP6 : 1; //!< [6] Supervisor Protect
+ uint32_t RESERVED1 : 1; //!< [7]
+ uint32_t TP5 : 1; //!< [8] Trusted Protect
+ uint32_t WP5 : 1; //!< [9] Write Protect
+ uint32_t SP5 : 1; //!< [10] Supervisor Protect
+ uint32_t RESERVED2 : 1; //!< [11]
+ uint32_t TP4 : 1; //!< [12] Trusted Protect
+ uint32_t WP4 : 1; //!< [13] Write Protect
+ uint32_t SP4 : 1; //!< [14] Supervisor Protect
+ uint32_t RESERVED3 : 1; //!< [15]
+ uint32_t TP3 : 1; //!< [16] Trusted Protect
+ uint32_t WP3 : 1; //!< [17] Write Protect
+ uint32_t SP3 : 1; //!< [18] Supervisor Protect
+ uint32_t RESERVED4 : 1; //!< [19]
+ uint32_t TP2 : 1; //!< [20] Trusted Protect
+ uint32_t WP2 : 1; //!< [21] Write Protect
+ uint32_t SP2 : 1; //!< [22] Supervisor Protect
+ uint32_t RESERVED5 : 1; //!< [23]
+ uint32_t TP1 : 1; //!< [24] Trusted Protect
+ uint32_t WP1 : 1; //!< [25] Write Protect
+ uint32_t SP1 : 1; //!< [26] Supervisor Protect
+ uint32_t RESERVED6 : 1; //!< [27]
+ uint32_t TP0 : 1; //!< [28] Trusted Protect
+ uint32_t WP0 : 1; //!< [29] Write Protect
+ uint32_t SP0 : 1; //!< [30] Supervisor Protect
+ uint32_t RESERVED7 : 1; //!< [31]
+ } B;
+} hw_aips_pacrb_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRB register
+ */
+//@{
+#define HW_AIPS_PACRB_ADDR(x) (REGS_AIPS_BASE(x) + 0x24U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRB(x) (*(__IO hw_aips_pacrb_t *) HW_AIPS_PACRB_ADDR(x))
+#define HW_AIPS_PACRB_RD(x) (HW_AIPS_PACRB(x).U)
+#define HW_AIPS_PACRB_WR(x, v) (HW_AIPS_PACRB(x).U = (v))
+#define HW_AIPS_PACRB_SET(x, v) (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) | (v)))
+#define HW_AIPS_PACRB_CLR(x, v) (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) & ~(v)))
+#define HW_AIPS_PACRB_TOG(x, v) (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRB bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRB, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRB_TP7 (0U) //!< Bit position for AIPS_PACRB_TP7.
+#define BM_AIPS_PACRB_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRB_TP7.
+#define BS_AIPS_PACRB_TP7 (1U) //!< Bit field size in bits for AIPS_PACRB_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_TP7 field.
+#define BR_AIPS_PACRB_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_TP7.
+#define BF_AIPS_PACRB_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP7), uint32_t) & BM_AIPS_PACRB_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRB_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRB_WP7 (1U) //!< Bit position for AIPS_PACRB_WP7.
+#define BM_AIPS_PACRB_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRB_WP7.
+#define BS_AIPS_PACRB_WP7 (1U) //!< Bit field size in bits for AIPS_PACRB_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_WP7 field.
+#define BR_AIPS_PACRB_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_WP7.
+#define BF_AIPS_PACRB_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP7), uint32_t) & BM_AIPS_PACRB_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRB_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRB_SP7 (2U) //!< Bit position for AIPS_PACRB_SP7.
+#define BM_AIPS_PACRB_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRB_SP7.
+#define BS_AIPS_PACRB_SP7 (1U) //!< Bit field size in bits for AIPS_PACRB_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_SP7 field.
+#define BR_AIPS_PACRB_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_SP7.
+#define BF_AIPS_PACRB_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP7), uint32_t) & BM_AIPS_PACRB_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRB_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRB_TP6 (4U) //!< Bit position for AIPS_PACRB_TP6.
+#define BM_AIPS_PACRB_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRB_TP6.
+#define BS_AIPS_PACRB_TP6 (1U) //!< Bit field size in bits for AIPS_PACRB_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_TP6 field.
+#define BR_AIPS_PACRB_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_TP6.
+#define BF_AIPS_PACRB_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP6), uint32_t) & BM_AIPS_PACRB_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRB_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRB_WP6 (5U) //!< Bit position for AIPS_PACRB_WP6.
+#define BM_AIPS_PACRB_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRB_WP6.
+#define BS_AIPS_PACRB_WP6 (1U) //!< Bit field size in bits for AIPS_PACRB_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_WP6 field.
+#define BR_AIPS_PACRB_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_WP6.
+#define BF_AIPS_PACRB_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP6), uint32_t) & BM_AIPS_PACRB_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRB_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRB_SP6 (6U) //!< Bit position for AIPS_PACRB_SP6.
+#define BM_AIPS_PACRB_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRB_SP6.
+#define BS_AIPS_PACRB_SP6 (1U) //!< Bit field size in bits for AIPS_PACRB_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_SP6 field.
+#define BR_AIPS_PACRB_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_SP6.
+#define BF_AIPS_PACRB_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP6), uint32_t) & BM_AIPS_PACRB_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRB_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRB_TP5 (8U) //!< Bit position for AIPS_PACRB_TP5.
+#define BM_AIPS_PACRB_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRB_TP5.
+#define BS_AIPS_PACRB_TP5 (1U) //!< Bit field size in bits for AIPS_PACRB_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_TP5 field.
+#define BR_AIPS_PACRB_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_TP5.
+#define BF_AIPS_PACRB_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP5), uint32_t) & BM_AIPS_PACRB_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRB_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRB_WP5 (9U) //!< Bit position for AIPS_PACRB_WP5.
+#define BM_AIPS_PACRB_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRB_WP5.
+#define BS_AIPS_PACRB_WP5 (1U) //!< Bit field size in bits for AIPS_PACRB_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_WP5 field.
+#define BR_AIPS_PACRB_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_WP5.
+#define BF_AIPS_PACRB_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP5), uint32_t) & BM_AIPS_PACRB_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRB_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRB_SP5 (10U) //!< Bit position for AIPS_PACRB_SP5.
+#define BM_AIPS_PACRB_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRB_SP5.
+#define BS_AIPS_PACRB_SP5 (1U) //!< Bit field size in bits for AIPS_PACRB_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_SP5 field.
+#define BR_AIPS_PACRB_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_SP5.
+#define BF_AIPS_PACRB_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP5), uint32_t) & BM_AIPS_PACRB_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRB_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRB_TP4 (12U) //!< Bit position for AIPS_PACRB_TP4.
+#define BM_AIPS_PACRB_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRB_TP4.
+#define BS_AIPS_PACRB_TP4 (1U) //!< Bit field size in bits for AIPS_PACRB_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_TP4 field.
+#define BR_AIPS_PACRB_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_TP4.
+#define BF_AIPS_PACRB_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP4), uint32_t) & BM_AIPS_PACRB_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRB_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRB_WP4 (13U) //!< Bit position for AIPS_PACRB_WP4.
+#define BM_AIPS_PACRB_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRB_WP4.
+#define BS_AIPS_PACRB_WP4 (1U) //!< Bit field size in bits for AIPS_PACRB_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_WP4 field.
+#define BR_AIPS_PACRB_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_WP4.
+#define BF_AIPS_PACRB_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP4), uint32_t) & BM_AIPS_PACRB_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRB_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRB_SP4 (14U) //!< Bit position for AIPS_PACRB_SP4.
+#define BM_AIPS_PACRB_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRB_SP4.
+#define BS_AIPS_PACRB_SP4 (1U) //!< Bit field size in bits for AIPS_PACRB_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_SP4 field.
+#define BR_AIPS_PACRB_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_SP4.
+#define BF_AIPS_PACRB_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP4), uint32_t) & BM_AIPS_PACRB_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRB_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRB_TP3 (16U) //!< Bit position for AIPS_PACRB_TP3.
+#define BM_AIPS_PACRB_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRB_TP3.
+#define BS_AIPS_PACRB_TP3 (1U) //!< Bit field size in bits for AIPS_PACRB_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_TP3 field.
+#define BR_AIPS_PACRB_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_TP3.
+#define BF_AIPS_PACRB_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP3), uint32_t) & BM_AIPS_PACRB_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRB_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRB_WP3 (17U) //!< Bit position for AIPS_PACRB_WP3.
+#define BM_AIPS_PACRB_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRB_WP3.
+#define BS_AIPS_PACRB_WP3 (1U) //!< Bit field size in bits for AIPS_PACRB_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_WP3 field.
+#define BR_AIPS_PACRB_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_WP3.
+#define BF_AIPS_PACRB_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP3), uint32_t) & BM_AIPS_PACRB_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRB_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRB_SP3 (18U) //!< Bit position for AIPS_PACRB_SP3.
+#define BM_AIPS_PACRB_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRB_SP3.
+#define BS_AIPS_PACRB_SP3 (1U) //!< Bit field size in bits for AIPS_PACRB_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_SP3 field.
+#define BR_AIPS_PACRB_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_SP3.
+#define BF_AIPS_PACRB_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP3), uint32_t) & BM_AIPS_PACRB_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRB_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRB_TP2 (20U) //!< Bit position for AIPS_PACRB_TP2.
+#define BM_AIPS_PACRB_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRB_TP2.
+#define BS_AIPS_PACRB_TP2 (1U) //!< Bit field size in bits for AIPS_PACRB_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_TP2 field.
+#define BR_AIPS_PACRB_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_TP2.
+#define BF_AIPS_PACRB_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP2), uint32_t) & BM_AIPS_PACRB_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRB_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRB_WP2 (21U) //!< Bit position for AIPS_PACRB_WP2.
+#define BM_AIPS_PACRB_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRB_WP2.
+#define BS_AIPS_PACRB_WP2 (1U) //!< Bit field size in bits for AIPS_PACRB_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_WP2 field.
+#define BR_AIPS_PACRB_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_WP2.
+#define BF_AIPS_PACRB_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP2), uint32_t) & BM_AIPS_PACRB_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRB_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRB_SP2 (22U) //!< Bit position for AIPS_PACRB_SP2.
+#define BM_AIPS_PACRB_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRB_SP2.
+#define BS_AIPS_PACRB_SP2 (1U) //!< Bit field size in bits for AIPS_PACRB_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_SP2 field.
+#define BR_AIPS_PACRB_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_SP2.
+#define BF_AIPS_PACRB_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP2), uint32_t) & BM_AIPS_PACRB_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRB_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRB_TP1 (24U) //!< Bit position for AIPS_PACRB_TP1.
+#define BM_AIPS_PACRB_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRB_TP1.
+#define BS_AIPS_PACRB_TP1 (1U) //!< Bit field size in bits for AIPS_PACRB_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_TP1 field.
+#define BR_AIPS_PACRB_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_TP1.
+#define BF_AIPS_PACRB_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP1), uint32_t) & BM_AIPS_PACRB_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRB_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRB_WP1 (25U) //!< Bit position for AIPS_PACRB_WP1.
+#define BM_AIPS_PACRB_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRB_WP1.
+#define BS_AIPS_PACRB_WP1 (1U) //!< Bit field size in bits for AIPS_PACRB_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_WP1 field.
+#define BR_AIPS_PACRB_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_WP1.
+#define BF_AIPS_PACRB_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP1), uint32_t) & BM_AIPS_PACRB_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRB_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRB_SP1 (26U) //!< Bit position for AIPS_PACRB_SP1.
+#define BM_AIPS_PACRB_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRB_SP1.
+#define BS_AIPS_PACRB_SP1 (1U) //!< Bit field size in bits for AIPS_PACRB_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_SP1 field.
+#define BR_AIPS_PACRB_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_SP1.
+#define BF_AIPS_PACRB_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP1), uint32_t) & BM_AIPS_PACRB_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRB_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRB_TP0 (28U) //!< Bit position for AIPS_PACRB_TP0.
+#define BM_AIPS_PACRB_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRB_TP0.
+#define BS_AIPS_PACRB_TP0 (1U) //!< Bit field size in bits for AIPS_PACRB_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_TP0 field.
+#define BR_AIPS_PACRB_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_TP0.
+#define BF_AIPS_PACRB_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_TP0), uint32_t) & BM_AIPS_PACRB_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRB_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRB_WP0 (29U) //!< Bit position for AIPS_PACRB_WP0.
+#define BM_AIPS_PACRB_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRB_WP0.
+#define BS_AIPS_PACRB_WP0 (1U) //!< Bit field size in bits for AIPS_PACRB_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_WP0 field.
+#define BR_AIPS_PACRB_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_WP0.
+#define BF_AIPS_PACRB_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_WP0), uint32_t) & BM_AIPS_PACRB_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRB_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRB, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRB_SP0 (30U) //!< Bit position for AIPS_PACRB_SP0.
+#define BM_AIPS_PACRB_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRB_SP0.
+#define BS_AIPS_PACRB_SP0 (1U) //!< Bit field size in bits for AIPS_PACRB_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRB_SP0 field.
+#define BR_AIPS_PACRB_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRB_SP0.
+#define BF_AIPS_PACRB_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRB_SP0), uint32_t) & BM_AIPS_PACRB_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRB_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRC - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRC - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+typedef union _hw_aips_pacrc
+{
+ uint32_t U;
+ struct _hw_aips_pacrc_bitfields
+ {
+ uint32_t TP7 : 1; //!< [0] Trusted Protect
+ uint32_t WP7 : 1; //!< [1] Write Protect
+ uint32_t SP7 : 1; //!< [2] Supervisor Protect
+ uint32_t RESERVED0 : 1; //!< [3]
+ uint32_t TP6 : 1; //!< [4] Trusted Protect
+ uint32_t WP6 : 1; //!< [5] Write Protect
+ uint32_t SP6 : 1; //!< [6] Supervisor Protect
+ uint32_t RESERVED1 : 1; //!< [7]
+ uint32_t TP5 : 1; //!< [8] Trusted Protect
+ uint32_t WP5 : 1; //!< [9] Write Protect
+ uint32_t SP5 : 1; //!< [10] Supervisor Protect
+ uint32_t RESERVED2 : 1; //!< [11]
+ uint32_t TP4 : 1; //!< [12] Trusted Protect
+ uint32_t WP4 : 1; //!< [13] Write Protect
+ uint32_t SP4 : 1; //!< [14] Supervisor Protect
+ uint32_t RESERVED3 : 1; //!< [15]
+ uint32_t TP3 : 1; //!< [16] Trusted Protect
+ uint32_t WP3 : 1; //!< [17] Write Protect
+ uint32_t SP3 : 1; //!< [18] Supervisor Protect
+ uint32_t RESERVED4 : 1; //!< [19]
+ uint32_t TP2 : 1; //!< [20] Trusted Protect
+ uint32_t WP2 : 1; //!< [21] Write Protect
+ uint32_t SP2 : 1; //!< [22] Supervisor Protect
+ uint32_t RESERVED5 : 1; //!< [23]
+ uint32_t TP1 : 1; //!< [24] Trusted Protect
+ uint32_t WP1 : 1; //!< [25] Write Protect
+ uint32_t SP1 : 1; //!< [26] Supervisor Protect
+ uint32_t RESERVED6 : 1; //!< [27]
+ uint32_t TP0 : 1; //!< [28] Trusted Protect
+ uint32_t WP0 : 1; //!< [29] Write Protect
+ uint32_t SP0 : 1; //!< [30] Supervisor Protect
+ uint32_t RESERVED7 : 1; //!< [31]
+ } B;
+} hw_aips_pacrc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRC register
+ */
+//@{
+#define HW_AIPS_PACRC_ADDR(x) (REGS_AIPS_BASE(x) + 0x28U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRC(x) (*(__IO hw_aips_pacrc_t *) HW_AIPS_PACRC_ADDR(x))
+#define HW_AIPS_PACRC_RD(x) (HW_AIPS_PACRC(x).U)
+#define HW_AIPS_PACRC_WR(x, v) (HW_AIPS_PACRC(x).U = (v))
+#define HW_AIPS_PACRC_SET(x, v) (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) | (v)))
+#define HW_AIPS_PACRC_CLR(x, v) (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) & ~(v)))
+#define HW_AIPS_PACRC_TOG(x, v) (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRC bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRC, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRC_TP7 (0U) //!< Bit position for AIPS_PACRC_TP7.
+#define BM_AIPS_PACRC_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRC_TP7.
+#define BS_AIPS_PACRC_TP7 (1U) //!< Bit field size in bits for AIPS_PACRC_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_TP7 field.
+#define BR_AIPS_PACRC_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_TP7.
+#define BF_AIPS_PACRC_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP7), uint32_t) & BM_AIPS_PACRC_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRC_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRC_WP7 (1U) //!< Bit position for AIPS_PACRC_WP7.
+#define BM_AIPS_PACRC_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRC_WP7.
+#define BS_AIPS_PACRC_WP7 (1U) //!< Bit field size in bits for AIPS_PACRC_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_WP7 field.
+#define BR_AIPS_PACRC_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_WP7.
+#define BF_AIPS_PACRC_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP7), uint32_t) & BM_AIPS_PACRC_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRC_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRC_SP7 (2U) //!< Bit position for AIPS_PACRC_SP7.
+#define BM_AIPS_PACRC_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRC_SP7.
+#define BS_AIPS_PACRC_SP7 (1U) //!< Bit field size in bits for AIPS_PACRC_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_SP7 field.
+#define BR_AIPS_PACRC_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_SP7.
+#define BF_AIPS_PACRC_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP7), uint32_t) & BM_AIPS_PACRC_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRC_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRC_TP6 (4U) //!< Bit position for AIPS_PACRC_TP6.
+#define BM_AIPS_PACRC_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRC_TP6.
+#define BS_AIPS_PACRC_TP6 (1U) //!< Bit field size in bits for AIPS_PACRC_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_TP6 field.
+#define BR_AIPS_PACRC_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_TP6.
+#define BF_AIPS_PACRC_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP6), uint32_t) & BM_AIPS_PACRC_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRC_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRC_WP6 (5U) //!< Bit position for AIPS_PACRC_WP6.
+#define BM_AIPS_PACRC_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRC_WP6.
+#define BS_AIPS_PACRC_WP6 (1U) //!< Bit field size in bits for AIPS_PACRC_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_WP6 field.
+#define BR_AIPS_PACRC_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_WP6.
+#define BF_AIPS_PACRC_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP6), uint32_t) & BM_AIPS_PACRC_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRC_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRC_SP6 (6U) //!< Bit position for AIPS_PACRC_SP6.
+#define BM_AIPS_PACRC_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRC_SP6.
+#define BS_AIPS_PACRC_SP6 (1U) //!< Bit field size in bits for AIPS_PACRC_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_SP6 field.
+#define BR_AIPS_PACRC_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_SP6.
+#define BF_AIPS_PACRC_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP6), uint32_t) & BM_AIPS_PACRC_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRC_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRC_TP5 (8U) //!< Bit position for AIPS_PACRC_TP5.
+#define BM_AIPS_PACRC_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRC_TP5.
+#define BS_AIPS_PACRC_TP5 (1U) //!< Bit field size in bits for AIPS_PACRC_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_TP5 field.
+#define BR_AIPS_PACRC_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_TP5.
+#define BF_AIPS_PACRC_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP5), uint32_t) & BM_AIPS_PACRC_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRC_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRC_WP5 (9U) //!< Bit position for AIPS_PACRC_WP5.
+#define BM_AIPS_PACRC_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRC_WP5.
+#define BS_AIPS_PACRC_WP5 (1U) //!< Bit field size in bits for AIPS_PACRC_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_WP5 field.
+#define BR_AIPS_PACRC_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_WP5.
+#define BF_AIPS_PACRC_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP5), uint32_t) & BM_AIPS_PACRC_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRC_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRC_SP5 (10U) //!< Bit position for AIPS_PACRC_SP5.
+#define BM_AIPS_PACRC_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRC_SP5.
+#define BS_AIPS_PACRC_SP5 (1U) //!< Bit field size in bits for AIPS_PACRC_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_SP5 field.
+#define BR_AIPS_PACRC_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_SP5.
+#define BF_AIPS_PACRC_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP5), uint32_t) & BM_AIPS_PACRC_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRC_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRC_TP4 (12U) //!< Bit position for AIPS_PACRC_TP4.
+#define BM_AIPS_PACRC_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRC_TP4.
+#define BS_AIPS_PACRC_TP4 (1U) //!< Bit field size in bits for AIPS_PACRC_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_TP4 field.
+#define BR_AIPS_PACRC_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_TP4.
+#define BF_AIPS_PACRC_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP4), uint32_t) & BM_AIPS_PACRC_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRC_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRC_WP4 (13U) //!< Bit position for AIPS_PACRC_WP4.
+#define BM_AIPS_PACRC_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRC_WP4.
+#define BS_AIPS_PACRC_WP4 (1U) //!< Bit field size in bits for AIPS_PACRC_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_WP4 field.
+#define BR_AIPS_PACRC_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_WP4.
+#define BF_AIPS_PACRC_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP4), uint32_t) & BM_AIPS_PACRC_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRC_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRC_SP4 (14U) //!< Bit position for AIPS_PACRC_SP4.
+#define BM_AIPS_PACRC_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRC_SP4.
+#define BS_AIPS_PACRC_SP4 (1U) //!< Bit field size in bits for AIPS_PACRC_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_SP4 field.
+#define BR_AIPS_PACRC_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_SP4.
+#define BF_AIPS_PACRC_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP4), uint32_t) & BM_AIPS_PACRC_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRC_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRC_TP3 (16U) //!< Bit position for AIPS_PACRC_TP3.
+#define BM_AIPS_PACRC_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRC_TP3.
+#define BS_AIPS_PACRC_TP3 (1U) //!< Bit field size in bits for AIPS_PACRC_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_TP3 field.
+#define BR_AIPS_PACRC_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_TP3.
+#define BF_AIPS_PACRC_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP3), uint32_t) & BM_AIPS_PACRC_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRC_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRC_WP3 (17U) //!< Bit position for AIPS_PACRC_WP3.
+#define BM_AIPS_PACRC_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRC_WP3.
+#define BS_AIPS_PACRC_WP3 (1U) //!< Bit field size in bits for AIPS_PACRC_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_WP3 field.
+#define BR_AIPS_PACRC_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_WP3.
+#define BF_AIPS_PACRC_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP3), uint32_t) & BM_AIPS_PACRC_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRC_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRC_SP3 (18U) //!< Bit position for AIPS_PACRC_SP3.
+#define BM_AIPS_PACRC_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRC_SP3.
+#define BS_AIPS_PACRC_SP3 (1U) //!< Bit field size in bits for AIPS_PACRC_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_SP3 field.
+#define BR_AIPS_PACRC_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_SP3.
+#define BF_AIPS_PACRC_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP3), uint32_t) & BM_AIPS_PACRC_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRC_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRC_TP2 (20U) //!< Bit position for AIPS_PACRC_TP2.
+#define BM_AIPS_PACRC_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRC_TP2.
+#define BS_AIPS_PACRC_TP2 (1U) //!< Bit field size in bits for AIPS_PACRC_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_TP2 field.
+#define BR_AIPS_PACRC_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_TP2.
+#define BF_AIPS_PACRC_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP2), uint32_t) & BM_AIPS_PACRC_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRC_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRC_WP2 (21U) //!< Bit position for AIPS_PACRC_WP2.
+#define BM_AIPS_PACRC_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRC_WP2.
+#define BS_AIPS_PACRC_WP2 (1U) //!< Bit field size in bits for AIPS_PACRC_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_WP2 field.
+#define BR_AIPS_PACRC_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_WP2.
+#define BF_AIPS_PACRC_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP2), uint32_t) & BM_AIPS_PACRC_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRC_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRC_SP2 (22U) //!< Bit position for AIPS_PACRC_SP2.
+#define BM_AIPS_PACRC_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRC_SP2.
+#define BS_AIPS_PACRC_SP2 (1U) //!< Bit field size in bits for AIPS_PACRC_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_SP2 field.
+#define BR_AIPS_PACRC_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_SP2.
+#define BF_AIPS_PACRC_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP2), uint32_t) & BM_AIPS_PACRC_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRC_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRC_TP1 (24U) //!< Bit position for AIPS_PACRC_TP1.
+#define BM_AIPS_PACRC_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRC_TP1.
+#define BS_AIPS_PACRC_TP1 (1U) //!< Bit field size in bits for AIPS_PACRC_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_TP1 field.
+#define BR_AIPS_PACRC_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_TP1.
+#define BF_AIPS_PACRC_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP1), uint32_t) & BM_AIPS_PACRC_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRC_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRC_WP1 (25U) //!< Bit position for AIPS_PACRC_WP1.
+#define BM_AIPS_PACRC_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRC_WP1.
+#define BS_AIPS_PACRC_WP1 (1U) //!< Bit field size in bits for AIPS_PACRC_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_WP1 field.
+#define BR_AIPS_PACRC_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_WP1.
+#define BF_AIPS_PACRC_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP1), uint32_t) & BM_AIPS_PACRC_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRC_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRC_SP1 (26U) //!< Bit position for AIPS_PACRC_SP1.
+#define BM_AIPS_PACRC_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRC_SP1.
+#define BS_AIPS_PACRC_SP1 (1U) //!< Bit field size in bits for AIPS_PACRC_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_SP1 field.
+#define BR_AIPS_PACRC_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_SP1.
+#define BF_AIPS_PACRC_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP1), uint32_t) & BM_AIPS_PACRC_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRC_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRC_TP0 (28U) //!< Bit position for AIPS_PACRC_TP0.
+#define BM_AIPS_PACRC_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRC_TP0.
+#define BS_AIPS_PACRC_TP0 (1U) //!< Bit field size in bits for AIPS_PACRC_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_TP0 field.
+#define BR_AIPS_PACRC_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_TP0.
+#define BF_AIPS_PACRC_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_TP0), uint32_t) & BM_AIPS_PACRC_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRC_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRC_WP0 (29U) //!< Bit position for AIPS_PACRC_WP0.
+#define BM_AIPS_PACRC_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRC_WP0.
+#define BS_AIPS_PACRC_WP0 (1U) //!< Bit field size in bits for AIPS_PACRC_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_WP0 field.
+#define BR_AIPS_PACRC_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_WP0.
+#define BF_AIPS_PACRC_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_WP0), uint32_t) & BM_AIPS_PACRC_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRC_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRC, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRC_SP0 (30U) //!< Bit position for AIPS_PACRC_SP0.
+#define BM_AIPS_PACRC_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRC_SP0.
+#define BS_AIPS_PACRC_SP0 (1U) //!< Bit field size in bits for AIPS_PACRC_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRC_SP0 field.
+#define BR_AIPS_PACRC_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRC_SP0.
+#define BF_AIPS_PACRC_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRC_SP0), uint32_t) & BM_AIPS_PACRC_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRC_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRD - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRD - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x00000004U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+typedef union _hw_aips_pacrd
+{
+ uint32_t U;
+ struct _hw_aips_pacrd_bitfields
+ {
+ uint32_t TP7 : 1; //!< [0] Trusted Protect
+ uint32_t WP7 : 1; //!< [1] Write Protect
+ uint32_t SP7 : 1; //!< [2] Supervisor Protect
+ uint32_t RESERVED0 : 1; //!< [3]
+ uint32_t TP6 : 1; //!< [4] Trusted Protect
+ uint32_t WP6 : 1; //!< [5] Write Protect
+ uint32_t SP6 : 1; //!< [6] Supervisor Protect
+ uint32_t RESERVED1 : 1; //!< [7]
+ uint32_t TP5 : 1; //!< [8] Trusted Protect
+ uint32_t WP5 : 1; //!< [9] Write Protect
+ uint32_t SP5 : 1; //!< [10] Supervisor Protect
+ uint32_t RESERVED2 : 1; //!< [11]
+ uint32_t TP4 : 1; //!< [12] Trusted Protect
+ uint32_t WP4 : 1; //!< [13] Write Protect
+ uint32_t SP4 : 1; //!< [14] Supervisor Protect
+ uint32_t RESERVED3 : 1; //!< [15]
+ uint32_t TP3 : 1; //!< [16] Trusted Protect
+ uint32_t WP3 : 1; //!< [17] Write Protect
+ uint32_t SP3 : 1; //!< [18] Supervisor Protect
+ uint32_t RESERVED4 : 1; //!< [19]
+ uint32_t TP2 : 1; //!< [20] Trusted Protect
+ uint32_t WP2 : 1; //!< [21] Write Protect
+ uint32_t SP2 : 1; //!< [22] Supervisor Protect
+ uint32_t RESERVED5 : 1; //!< [23]
+ uint32_t TP1 : 1; //!< [24] Trusted Protect
+ uint32_t WP1 : 1; //!< [25] Write Protect
+ uint32_t SP1 : 1; //!< [26] Supervisor Protect
+ uint32_t RESERVED6 : 1; //!< [27]
+ uint32_t TP0 : 1; //!< [28] Trusted Protect
+ uint32_t WP0 : 1; //!< [29] Write Protect
+ uint32_t SP0 : 1; //!< [30] Supervisor Protect
+ uint32_t RESERVED7 : 1; //!< [31]
+ } B;
+} hw_aips_pacrd_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRD register
+ */
+//@{
+#define HW_AIPS_PACRD_ADDR(x) (REGS_AIPS_BASE(x) + 0x2CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRD(x) (*(__IO hw_aips_pacrd_t *) HW_AIPS_PACRD_ADDR(x))
+#define HW_AIPS_PACRD_RD(x) (HW_AIPS_PACRD(x).U)
+#define HW_AIPS_PACRD_WR(x, v) (HW_AIPS_PACRD(x).U = (v))
+#define HW_AIPS_PACRD_SET(x, v) (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) | (v)))
+#define HW_AIPS_PACRD_CLR(x, v) (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) & ~(v)))
+#define HW_AIPS_PACRD_TOG(x, v) (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRD bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRD, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRD_TP7 (0U) //!< Bit position for AIPS_PACRD_TP7.
+#define BM_AIPS_PACRD_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRD_TP7.
+#define BS_AIPS_PACRD_TP7 (1U) //!< Bit field size in bits for AIPS_PACRD_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_TP7 field.
+#define BR_AIPS_PACRD_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_TP7.
+#define BF_AIPS_PACRD_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP7), uint32_t) & BM_AIPS_PACRD_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRD_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRD_WP7 (1U) //!< Bit position for AIPS_PACRD_WP7.
+#define BM_AIPS_PACRD_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRD_WP7.
+#define BS_AIPS_PACRD_WP7 (1U) //!< Bit field size in bits for AIPS_PACRD_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_WP7 field.
+#define BR_AIPS_PACRD_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_WP7.
+#define BF_AIPS_PACRD_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP7), uint32_t) & BM_AIPS_PACRD_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRD_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRD_SP7 (2U) //!< Bit position for AIPS_PACRD_SP7.
+#define BM_AIPS_PACRD_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRD_SP7.
+#define BS_AIPS_PACRD_SP7 (1U) //!< Bit field size in bits for AIPS_PACRD_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_SP7 field.
+#define BR_AIPS_PACRD_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_SP7.
+#define BF_AIPS_PACRD_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP7), uint32_t) & BM_AIPS_PACRD_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRD_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRD_TP6 (4U) //!< Bit position for AIPS_PACRD_TP6.
+#define BM_AIPS_PACRD_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRD_TP6.
+#define BS_AIPS_PACRD_TP6 (1U) //!< Bit field size in bits for AIPS_PACRD_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_TP6 field.
+#define BR_AIPS_PACRD_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_TP6.
+#define BF_AIPS_PACRD_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP6), uint32_t) & BM_AIPS_PACRD_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRD_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRD_WP6 (5U) //!< Bit position for AIPS_PACRD_WP6.
+#define BM_AIPS_PACRD_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRD_WP6.
+#define BS_AIPS_PACRD_WP6 (1U) //!< Bit field size in bits for AIPS_PACRD_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_WP6 field.
+#define BR_AIPS_PACRD_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_WP6.
+#define BF_AIPS_PACRD_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP6), uint32_t) & BM_AIPS_PACRD_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRD_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRD_SP6 (6U) //!< Bit position for AIPS_PACRD_SP6.
+#define BM_AIPS_PACRD_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRD_SP6.
+#define BS_AIPS_PACRD_SP6 (1U) //!< Bit field size in bits for AIPS_PACRD_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_SP6 field.
+#define BR_AIPS_PACRD_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_SP6.
+#define BF_AIPS_PACRD_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP6), uint32_t) & BM_AIPS_PACRD_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRD_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRD_TP5 (8U) //!< Bit position for AIPS_PACRD_TP5.
+#define BM_AIPS_PACRD_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRD_TP5.
+#define BS_AIPS_PACRD_TP5 (1U) //!< Bit field size in bits for AIPS_PACRD_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_TP5 field.
+#define BR_AIPS_PACRD_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_TP5.
+#define BF_AIPS_PACRD_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP5), uint32_t) & BM_AIPS_PACRD_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRD_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRD_WP5 (9U) //!< Bit position for AIPS_PACRD_WP5.
+#define BM_AIPS_PACRD_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRD_WP5.
+#define BS_AIPS_PACRD_WP5 (1U) //!< Bit field size in bits for AIPS_PACRD_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_WP5 field.
+#define BR_AIPS_PACRD_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_WP5.
+#define BF_AIPS_PACRD_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP5), uint32_t) & BM_AIPS_PACRD_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRD_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRD_SP5 (10U) //!< Bit position for AIPS_PACRD_SP5.
+#define BM_AIPS_PACRD_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRD_SP5.
+#define BS_AIPS_PACRD_SP5 (1U) //!< Bit field size in bits for AIPS_PACRD_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_SP5 field.
+#define BR_AIPS_PACRD_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_SP5.
+#define BF_AIPS_PACRD_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP5), uint32_t) & BM_AIPS_PACRD_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRD_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRD_TP4 (12U) //!< Bit position for AIPS_PACRD_TP4.
+#define BM_AIPS_PACRD_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRD_TP4.
+#define BS_AIPS_PACRD_TP4 (1U) //!< Bit field size in bits for AIPS_PACRD_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_TP4 field.
+#define BR_AIPS_PACRD_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_TP4.
+#define BF_AIPS_PACRD_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP4), uint32_t) & BM_AIPS_PACRD_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRD_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRD_WP4 (13U) //!< Bit position for AIPS_PACRD_WP4.
+#define BM_AIPS_PACRD_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRD_WP4.
+#define BS_AIPS_PACRD_WP4 (1U) //!< Bit field size in bits for AIPS_PACRD_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_WP4 field.
+#define BR_AIPS_PACRD_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_WP4.
+#define BF_AIPS_PACRD_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP4), uint32_t) & BM_AIPS_PACRD_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRD_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRD_SP4 (14U) //!< Bit position for AIPS_PACRD_SP4.
+#define BM_AIPS_PACRD_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRD_SP4.
+#define BS_AIPS_PACRD_SP4 (1U) //!< Bit field size in bits for AIPS_PACRD_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_SP4 field.
+#define BR_AIPS_PACRD_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_SP4.
+#define BF_AIPS_PACRD_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP4), uint32_t) & BM_AIPS_PACRD_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRD_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRD_TP3 (16U) //!< Bit position for AIPS_PACRD_TP3.
+#define BM_AIPS_PACRD_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRD_TP3.
+#define BS_AIPS_PACRD_TP3 (1U) //!< Bit field size in bits for AIPS_PACRD_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_TP3 field.
+#define BR_AIPS_PACRD_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_TP3.
+#define BF_AIPS_PACRD_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP3), uint32_t) & BM_AIPS_PACRD_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRD_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRD_WP3 (17U) //!< Bit position for AIPS_PACRD_WP3.
+#define BM_AIPS_PACRD_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRD_WP3.
+#define BS_AIPS_PACRD_WP3 (1U) //!< Bit field size in bits for AIPS_PACRD_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_WP3 field.
+#define BR_AIPS_PACRD_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_WP3.
+#define BF_AIPS_PACRD_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP3), uint32_t) & BM_AIPS_PACRD_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRD_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRD_SP3 (18U) //!< Bit position for AIPS_PACRD_SP3.
+#define BM_AIPS_PACRD_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRD_SP3.
+#define BS_AIPS_PACRD_SP3 (1U) //!< Bit field size in bits for AIPS_PACRD_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_SP3 field.
+#define BR_AIPS_PACRD_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_SP3.
+#define BF_AIPS_PACRD_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP3), uint32_t) & BM_AIPS_PACRD_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRD_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRD_TP2 (20U) //!< Bit position for AIPS_PACRD_TP2.
+#define BM_AIPS_PACRD_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRD_TP2.
+#define BS_AIPS_PACRD_TP2 (1U) //!< Bit field size in bits for AIPS_PACRD_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_TP2 field.
+#define BR_AIPS_PACRD_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_TP2.
+#define BF_AIPS_PACRD_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP2), uint32_t) & BM_AIPS_PACRD_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRD_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRD_WP2 (21U) //!< Bit position for AIPS_PACRD_WP2.
+#define BM_AIPS_PACRD_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRD_WP2.
+#define BS_AIPS_PACRD_WP2 (1U) //!< Bit field size in bits for AIPS_PACRD_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_WP2 field.
+#define BR_AIPS_PACRD_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_WP2.
+#define BF_AIPS_PACRD_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP2), uint32_t) & BM_AIPS_PACRD_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRD_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRD_SP2 (22U) //!< Bit position for AIPS_PACRD_SP2.
+#define BM_AIPS_PACRD_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRD_SP2.
+#define BS_AIPS_PACRD_SP2 (1U) //!< Bit field size in bits for AIPS_PACRD_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_SP2 field.
+#define BR_AIPS_PACRD_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_SP2.
+#define BF_AIPS_PACRD_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP2), uint32_t) & BM_AIPS_PACRD_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRD_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRD_TP1 (24U) //!< Bit position for AIPS_PACRD_TP1.
+#define BM_AIPS_PACRD_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRD_TP1.
+#define BS_AIPS_PACRD_TP1 (1U) //!< Bit field size in bits for AIPS_PACRD_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_TP1 field.
+#define BR_AIPS_PACRD_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_TP1.
+#define BF_AIPS_PACRD_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP1), uint32_t) & BM_AIPS_PACRD_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRD_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRD_WP1 (25U) //!< Bit position for AIPS_PACRD_WP1.
+#define BM_AIPS_PACRD_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRD_WP1.
+#define BS_AIPS_PACRD_WP1 (1U) //!< Bit field size in bits for AIPS_PACRD_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_WP1 field.
+#define BR_AIPS_PACRD_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_WP1.
+#define BF_AIPS_PACRD_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP1), uint32_t) & BM_AIPS_PACRD_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRD_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRD_SP1 (26U) //!< Bit position for AIPS_PACRD_SP1.
+#define BM_AIPS_PACRD_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRD_SP1.
+#define BS_AIPS_PACRD_SP1 (1U) //!< Bit field size in bits for AIPS_PACRD_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_SP1 field.
+#define BR_AIPS_PACRD_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_SP1.
+#define BF_AIPS_PACRD_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP1), uint32_t) & BM_AIPS_PACRD_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRD_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRD_TP0 (28U) //!< Bit position for AIPS_PACRD_TP0.
+#define BM_AIPS_PACRD_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRD_TP0.
+#define BS_AIPS_PACRD_TP0 (1U) //!< Bit field size in bits for AIPS_PACRD_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_TP0 field.
+#define BR_AIPS_PACRD_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_TP0.
+#define BF_AIPS_PACRD_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_TP0), uint32_t) & BM_AIPS_PACRD_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRD_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRD_WP0 (29U) //!< Bit position for AIPS_PACRD_WP0.
+#define BM_AIPS_PACRD_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRD_WP0.
+#define BS_AIPS_PACRD_WP0 (1U) //!< Bit field size in bits for AIPS_PACRD_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_WP0 field.
+#define BR_AIPS_PACRD_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_WP0.
+#define BF_AIPS_PACRD_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_WP0), uint32_t) & BM_AIPS_PACRD_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRD_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRD, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRD_SP0 (30U) //!< Bit position for AIPS_PACRD_SP0.
+#define BM_AIPS_PACRD_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRD_SP0.
+#define BS_AIPS_PACRD_SP0 (1U) //!< Bit field size in bits for AIPS_PACRD_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRD_SP0 field.
+#define BR_AIPS_PACRD_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRD_SP0.
+#define BF_AIPS_PACRD_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRD_SP0), uint32_t) & BM_AIPS_PACRD_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRD_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRE - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRE - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+typedef union _hw_aips_pacre
+{
+ uint32_t U;
+ struct _hw_aips_pacre_bitfields
+ {
+ uint32_t TP7 : 1; //!< [0] Trusted Protect
+ uint32_t WP7 : 1; //!< [1] Write Protect
+ uint32_t SP7 : 1; //!< [2] Supervisor Protect
+ uint32_t RESERVED0 : 1; //!< [3]
+ uint32_t TP6 : 1; //!< [4] Trusted Protect
+ uint32_t WP6 : 1; //!< [5] Write Protect
+ uint32_t SP6 : 1; //!< [6] Supervisor Protect
+ uint32_t RESERVED1 : 1; //!< [7]
+ uint32_t TP5 : 1; //!< [8] Trusted Protect
+ uint32_t WP5 : 1; //!< [9] Write Protect
+ uint32_t SP5 : 1; //!< [10] Supervisor Protect
+ uint32_t RESERVED2 : 1; //!< [11]
+ uint32_t TP4 : 1; //!< [12] Trusted Protect
+ uint32_t WP4 : 1; //!< [13] Write Protect
+ uint32_t SP4 : 1; //!< [14] Supervisor Protect
+ uint32_t RESERVED3 : 1; //!< [15]
+ uint32_t TP3 : 1; //!< [16] Trusted Protect
+ uint32_t WP3 : 1; //!< [17] Write Protect
+ uint32_t SP3 : 1; //!< [18] Supervisor Protect
+ uint32_t RESERVED4 : 1; //!< [19]
+ uint32_t TP2 : 1; //!< [20] Trusted Protect
+ uint32_t WP2 : 1; //!< [21] Write Protect
+ uint32_t SP2 : 1; //!< [22] Supervisor Protect
+ uint32_t RESERVED5 : 1; //!< [23]
+ uint32_t TP1 : 1; //!< [24] Trusted Protect
+ uint32_t WP1 : 1; //!< [25] Write Protect
+ uint32_t SP1 : 1; //!< [26] Supervisor Protect
+ uint32_t RESERVED6 : 1; //!< [27]
+ uint32_t TP0 : 1; //!< [28] Trusted Protect
+ uint32_t WP0 : 1; //!< [29] Write Protect
+ uint32_t SP0 : 1; //!< [30] Supervisor Protect
+ uint32_t RESERVED7 : 1; //!< [31]
+ } B;
+} hw_aips_pacre_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRE register
+ */
+//@{
+#define HW_AIPS_PACRE_ADDR(x) (REGS_AIPS_BASE(x) + 0x40U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRE(x) (*(__IO hw_aips_pacre_t *) HW_AIPS_PACRE_ADDR(x))
+#define HW_AIPS_PACRE_RD(x) (HW_AIPS_PACRE(x).U)
+#define HW_AIPS_PACRE_WR(x, v) (HW_AIPS_PACRE(x).U = (v))
+#define HW_AIPS_PACRE_SET(x, v) (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) | (v)))
+#define HW_AIPS_PACRE_CLR(x, v) (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) & ~(v)))
+#define HW_AIPS_PACRE_TOG(x, v) (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRE bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRE, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRE_TP7 (0U) //!< Bit position for AIPS_PACRE_TP7.
+#define BM_AIPS_PACRE_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRE_TP7.
+#define BS_AIPS_PACRE_TP7 (1U) //!< Bit field size in bits for AIPS_PACRE_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_TP7 field.
+#define BR_AIPS_PACRE_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_TP7.
+#define BF_AIPS_PACRE_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP7), uint32_t) & BM_AIPS_PACRE_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRE_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRE_WP7 (1U) //!< Bit position for AIPS_PACRE_WP7.
+#define BM_AIPS_PACRE_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRE_WP7.
+#define BS_AIPS_PACRE_WP7 (1U) //!< Bit field size in bits for AIPS_PACRE_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_WP7 field.
+#define BR_AIPS_PACRE_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_WP7.
+#define BF_AIPS_PACRE_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP7), uint32_t) & BM_AIPS_PACRE_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRE_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRE_SP7 (2U) //!< Bit position for AIPS_PACRE_SP7.
+#define BM_AIPS_PACRE_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRE_SP7.
+#define BS_AIPS_PACRE_SP7 (1U) //!< Bit field size in bits for AIPS_PACRE_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_SP7 field.
+#define BR_AIPS_PACRE_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_SP7.
+#define BF_AIPS_PACRE_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP7), uint32_t) & BM_AIPS_PACRE_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRE_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRE_TP6 (4U) //!< Bit position for AIPS_PACRE_TP6.
+#define BM_AIPS_PACRE_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRE_TP6.
+#define BS_AIPS_PACRE_TP6 (1U) //!< Bit field size in bits for AIPS_PACRE_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_TP6 field.
+#define BR_AIPS_PACRE_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_TP6.
+#define BF_AIPS_PACRE_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP6), uint32_t) & BM_AIPS_PACRE_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRE_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRE_WP6 (5U) //!< Bit position for AIPS_PACRE_WP6.
+#define BM_AIPS_PACRE_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRE_WP6.
+#define BS_AIPS_PACRE_WP6 (1U) //!< Bit field size in bits for AIPS_PACRE_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_WP6 field.
+#define BR_AIPS_PACRE_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_WP6.
+#define BF_AIPS_PACRE_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP6), uint32_t) & BM_AIPS_PACRE_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRE_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRE_SP6 (6U) //!< Bit position for AIPS_PACRE_SP6.
+#define BM_AIPS_PACRE_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRE_SP6.
+#define BS_AIPS_PACRE_SP6 (1U) //!< Bit field size in bits for AIPS_PACRE_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_SP6 field.
+#define BR_AIPS_PACRE_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_SP6.
+#define BF_AIPS_PACRE_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP6), uint32_t) & BM_AIPS_PACRE_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRE_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRE_TP5 (8U) //!< Bit position for AIPS_PACRE_TP5.
+#define BM_AIPS_PACRE_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRE_TP5.
+#define BS_AIPS_PACRE_TP5 (1U) //!< Bit field size in bits for AIPS_PACRE_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_TP5 field.
+#define BR_AIPS_PACRE_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_TP5.
+#define BF_AIPS_PACRE_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP5), uint32_t) & BM_AIPS_PACRE_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRE_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRE_WP5 (9U) //!< Bit position for AIPS_PACRE_WP5.
+#define BM_AIPS_PACRE_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRE_WP5.
+#define BS_AIPS_PACRE_WP5 (1U) //!< Bit field size in bits for AIPS_PACRE_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_WP5 field.
+#define BR_AIPS_PACRE_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_WP5.
+#define BF_AIPS_PACRE_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP5), uint32_t) & BM_AIPS_PACRE_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRE_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRE_SP5 (10U) //!< Bit position for AIPS_PACRE_SP5.
+#define BM_AIPS_PACRE_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRE_SP5.
+#define BS_AIPS_PACRE_SP5 (1U) //!< Bit field size in bits for AIPS_PACRE_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_SP5 field.
+#define BR_AIPS_PACRE_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_SP5.
+#define BF_AIPS_PACRE_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP5), uint32_t) & BM_AIPS_PACRE_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRE_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRE_TP4 (12U) //!< Bit position for AIPS_PACRE_TP4.
+#define BM_AIPS_PACRE_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRE_TP4.
+#define BS_AIPS_PACRE_TP4 (1U) //!< Bit field size in bits for AIPS_PACRE_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_TP4 field.
+#define BR_AIPS_PACRE_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_TP4.
+#define BF_AIPS_PACRE_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP4), uint32_t) & BM_AIPS_PACRE_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRE_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRE_WP4 (13U) //!< Bit position for AIPS_PACRE_WP4.
+#define BM_AIPS_PACRE_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRE_WP4.
+#define BS_AIPS_PACRE_WP4 (1U) //!< Bit field size in bits for AIPS_PACRE_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_WP4 field.
+#define BR_AIPS_PACRE_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_WP4.
+#define BF_AIPS_PACRE_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP4), uint32_t) & BM_AIPS_PACRE_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRE_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRE_SP4 (14U) //!< Bit position for AIPS_PACRE_SP4.
+#define BM_AIPS_PACRE_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRE_SP4.
+#define BS_AIPS_PACRE_SP4 (1U) //!< Bit field size in bits for AIPS_PACRE_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_SP4 field.
+#define BR_AIPS_PACRE_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_SP4.
+#define BF_AIPS_PACRE_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP4), uint32_t) & BM_AIPS_PACRE_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRE_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRE_TP3 (16U) //!< Bit position for AIPS_PACRE_TP3.
+#define BM_AIPS_PACRE_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRE_TP3.
+#define BS_AIPS_PACRE_TP3 (1U) //!< Bit field size in bits for AIPS_PACRE_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_TP3 field.
+#define BR_AIPS_PACRE_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_TP3.
+#define BF_AIPS_PACRE_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP3), uint32_t) & BM_AIPS_PACRE_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRE_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRE_WP3 (17U) //!< Bit position for AIPS_PACRE_WP3.
+#define BM_AIPS_PACRE_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRE_WP3.
+#define BS_AIPS_PACRE_WP3 (1U) //!< Bit field size in bits for AIPS_PACRE_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_WP3 field.
+#define BR_AIPS_PACRE_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_WP3.
+#define BF_AIPS_PACRE_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP3), uint32_t) & BM_AIPS_PACRE_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRE_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRE_SP3 (18U) //!< Bit position for AIPS_PACRE_SP3.
+#define BM_AIPS_PACRE_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRE_SP3.
+#define BS_AIPS_PACRE_SP3 (1U) //!< Bit field size in bits for AIPS_PACRE_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_SP3 field.
+#define BR_AIPS_PACRE_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_SP3.
+#define BF_AIPS_PACRE_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP3), uint32_t) & BM_AIPS_PACRE_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRE_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRE_TP2 (20U) //!< Bit position for AIPS_PACRE_TP2.
+#define BM_AIPS_PACRE_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRE_TP2.
+#define BS_AIPS_PACRE_TP2 (1U) //!< Bit field size in bits for AIPS_PACRE_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_TP2 field.
+#define BR_AIPS_PACRE_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_TP2.
+#define BF_AIPS_PACRE_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP2), uint32_t) & BM_AIPS_PACRE_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRE_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRE_WP2 (21U) //!< Bit position for AIPS_PACRE_WP2.
+#define BM_AIPS_PACRE_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRE_WP2.
+#define BS_AIPS_PACRE_WP2 (1U) //!< Bit field size in bits for AIPS_PACRE_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_WP2 field.
+#define BR_AIPS_PACRE_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_WP2.
+#define BF_AIPS_PACRE_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP2), uint32_t) & BM_AIPS_PACRE_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRE_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRE_SP2 (22U) //!< Bit position for AIPS_PACRE_SP2.
+#define BM_AIPS_PACRE_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRE_SP2.
+#define BS_AIPS_PACRE_SP2 (1U) //!< Bit field size in bits for AIPS_PACRE_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_SP2 field.
+#define BR_AIPS_PACRE_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_SP2.
+#define BF_AIPS_PACRE_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP2), uint32_t) & BM_AIPS_PACRE_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRE_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRE_TP1 (24U) //!< Bit position for AIPS_PACRE_TP1.
+#define BM_AIPS_PACRE_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRE_TP1.
+#define BS_AIPS_PACRE_TP1 (1U) //!< Bit field size in bits for AIPS_PACRE_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_TP1 field.
+#define BR_AIPS_PACRE_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_TP1.
+#define BF_AIPS_PACRE_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP1), uint32_t) & BM_AIPS_PACRE_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRE_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRE_WP1 (25U) //!< Bit position for AIPS_PACRE_WP1.
+#define BM_AIPS_PACRE_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRE_WP1.
+#define BS_AIPS_PACRE_WP1 (1U) //!< Bit field size in bits for AIPS_PACRE_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_WP1 field.
+#define BR_AIPS_PACRE_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_WP1.
+#define BF_AIPS_PACRE_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP1), uint32_t) & BM_AIPS_PACRE_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRE_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRE_SP1 (26U) //!< Bit position for AIPS_PACRE_SP1.
+#define BM_AIPS_PACRE_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRE_SP1.
+#define BS_AIPS_PACRE_SP1 (1U) //!< Bit field size in bits for AIPS_PACRE_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_SP1 field.
+#define BR_AIPS_PACRE_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_SP1.
+#define BF_AIPS_PACRE_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP1), uint32_t) & BM_AIPS_PACRE_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRE_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRE_TP0 (28U) //!< Bit position for AIPS_PACRE_TP0.
+#define BM_AIPS_PACRE_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRE_TP0.
+#define BS_AIPS_PACRE_TP0 (1U) //!< Bit field size in bits for AIPS_PACRE_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_TP0 field.
+#define BR_AIPS_PACRE_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_TP0.
+#define BF_AIPS_PACRE_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_TP0), uint32_t) & BM_AIPS_PACRE_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRE_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRE_WP0 (29U) //!< Bit position for AIPS_PACRE_WP0.
+#define BM_AIPS_PACRE_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRE_WP0.
+#define BS_AIPS_PACRE_WP0 (1U) //!< Bit field size in bits for AIPS_PACRE_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_WP0 field.
+#define BR_AIPS_PACRE_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_WP0.
+#define BF_AIPS_PACRE_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_WP0), uint32_t) & BM_AIPS_PACRE_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRE_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRE, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRE_SP0 (30U) //!< Bit position for AIPS_PACRE_SP0.
+#define BM_AIPS_PACRE_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRE_SP0.
+#define BS_AIPS_PACRE_SP0 (1U) //!< Bit field size in bits for AIPS_PACRE_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRE_SP0 field.
+#define BR_AIPS_PACRE_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRE_SP0.
+#define BF_AIPS_PACRE_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRE_SP0), uint32_t) & BM_AIPS_PACRE_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRE_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRF - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRF - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+typedef union _hw_aips_pacrf
+{
+ uint32_t U;
+ struct _hw_aips_pacrf_bitfields
+ {
+ uint32_t TP7 : 1; //!< [0] Trusted Protect
+ uint32_t WP7 : 1; //!< [1] Write Protect
+ uint32_t SP7 : 1; //!< [2] Supervisor Protect
+ uint32_t RESERVED0 : 1; //!< [3]
+ uint32_t TP6 : 1; //!< [4] Trusted Protect
+ uint32_t WP6 : 1; //!< [5] Write Protect
+ uint32_t SP6 : 1; //!< [6] Supervisor Protect
+ uint32_t RESERVED1 : 1; //!< [7]
+ uint32_t TP5 : 1; //!< [8] Trusted Protect
+ uint32_t WP5 : 1; //!< [9] Write Protect
+ uint32_t SP5 : 1; //!< [10] Supervisor Protect
+ uint32_t RESERVED2 : 1; //!< [11]
+ uint32_t TP4 : 1; //!< [12] Trusted Protect
+ uint32_t WP4 : 1; //!< [13] Write Protect
+ uint32_t SP4 : 1; //!< [14] Supervisor Protect
+ uint32_t RESERVED3 : 1; //!< [15]
+ uint32_t TP3 : 1; //!< [16] Trusted Protect
+ uint32_t WP3 : 1; //!< [17] Write Protect
+ uint32_t SP3 : 1; //!< [18] Supervisor Protect
+ uint32_t RESERVED4 : 1; //!< [19]
+ uint32_t TP2 : 1; //!< [20] Trusted Protect
+ uint32_t WP2 : 1; //!< [21] Write Protect
+ uint32_t SP2 : 1; //!< [22] Supervisor Protect
+ uint32_t RESERVED5 : 1; //!< [23]
+ uint32_t TP1 : 1; //!< [24] Trusted Protect
+ uint32_t WP1 : 1; //!< [25] Write Protect
+ uint32_t SP1 : 1; //!< [26] Supervisor Protect
+ uint32_t RESERVED6 : 1; //!< [27]
+ uint32_t TP0 : 1; //!< [28] Trusted Protect
+ uint32_t WP0 : 1; //!< [29] Write Protect
+ uint32_t SP0 : 1; //!< [30] Supervisor Protect
+ uint32_t RESERVED7 : 1; //!< [31]
+ } B;
+} hw_aips_pacrf_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRF register
+ */
+//@{
+#define HW_AIPS_PACRF_ADDR(x) (REGS_AIPS_BASE(x) + 0x44U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRF(x) (*(__IO hw_aips_pacrf_t *) HW_AIPS_PACRF_ADDR(x))
+#define HW_AIPS_PACRF_RD(x) (HW_AIPS_PACRF(x).U)
+#define HW_AIPS_PACRF_WR(x, v) (HW_AIPS_PACRF(x).U = (v))
+#define HW_AIPS_PACRF_SET(x, v) (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) | (v)))
+#define HW_AIPS_PACRF_CLR(x, v) (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) & ~(v)))
+#define HW_AIPS_PACRF_TOG(x, v) (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRF bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRF, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRF_TP7 (0U) //!< Bit position for AIPS_PACRF_TP7.
+#define BM_AIPS_PACRF_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRF_TP7.
+#define BS_AIPS_PACRF_TP7 (1U) //!< Bit field size in bits for AIPS_PACRF_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_TP7 field.
+#define BR_AIPS_PACRF_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_TP7.
+#define BF_AIPS_PACRF_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP7), uint32_t) & BM_AIPS_PACRF_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRF_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRF_WP7 (1U) //!< Bit position for AIPS_PACRF_WP7.
+#define BM_AIPS_PACRF_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRF_WP7.
+#define BS_AIPS_PACRF_WP7 (1U) //!< Bit field size in bits for AIPS_PACRF_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_WP7 field.
+#define BR_AIPS_PACRF_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_WP7.
+#define BF_AIPS_PACRF_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP7), uint32_t) & BM_AIPS_PACRF_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRF_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRF_SP7 (2U) //!< Bit position for AIPS_PACRF_SP7.
+#define BM_AIPS_PACRF_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRF_SP7.
+#define BS_AIPS_PACRF_SP7 (1U) //!< Bit field size in bits for AIPS_PACRF_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_SP7 field.
+#define BR_AIPS_PACRF_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_SP7.
+#define BF_AIPS_PACRF_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP7), uint32_t) & BM_AIPS_PACRF_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRF_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRF_TP6 (4U) //!< Bit position for AIPS_PACRF_TP6.
+#define BM_AIPS_PACRF_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRF_TP6.
+#define BS_AIPS_PACRF_TP6 (1U) //!< Bit field size in bits for AIPS_PACRF_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_TP6 field.
+#define BR_AIPS_PACRF_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_TP6.
+#define BF_AIPS_PACRF_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP6), uint32_t) & BM_AIPS_PACRF_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRF_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRF_WP6 (5U) //!< Bit position for AIPS_PACRF_WP6.
+#define BM_AIPS_PACRF_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRF_WP6.
+#define BS_AIPS_PACRF_WP6 (1U) //!< Bit field size in bits for AIPS_PACRF_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_WP6 field.
+#define BR_AIPS_PACRF_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_WP6.
+#define BF_AIPS_PACRF_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP6), uint32_t) & BM_AIPS_PACRF_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRF_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRF_SP6 (6U) //!< Bit position for AIPS_PACRF_SP6.
+#define BM_AIPS_PACRF_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRF_SP6.
+#define BS_AIPS_PACRF_SP6 (1U) //!< Bit field size in bits for AIPS_PACRF_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_SP6 field.
+#define BR_AIPS_PACRF_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_SP6.
+#define BF_AIPS_PACRF_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP6), uint32_t) & BM_AIPS_PACRF_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRF_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRF_TP5 (8U) //!< Bit position for AIPS_PACRF_TP5.
+#define BM_AIPS_PACRF_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRF_TP5.
+#define BS_AIPS_PACRF_TP5 (1U) //!< Bit field size in bits for AIPS_PACRF_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_TP5 field.
+#define BR_AIPS_PACRF_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_TP5.
+#define BF_AIPS_PACRF_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP5), uint32_t) & BM_AIPS_PACRF_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRF_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRF_WP5 (9U) //!< Bit position for AIPS_PACRF_WP5.
+#define BM_AIPS_PACRF_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRF_WP5.
+#define BS_AIPS_PACRF_WP5 (1U) //!< Bit field size in bits for AIPS_PACRF_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_WP5 field.
+#define BR_AIPS_PACRF_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_WP5.
+#define BF_AIPS_PACRF_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP5), uint32_t) & BM_AIPS_PACRF_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRF_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRF_SP5 (10U) //!< Bit position for AIPS_PACRF_SP5.
+#define BM_AIPS_PACRF_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRF_SP5.
+#define BS_AIPS_PACRF_SP5 (1U) //!< Bit field size in bits for AIPS_PACRF_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_SP5 field.
+#define BR_AIPS_PACRF_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_SP5.
+#define BF_AIPS_PACRF_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP5), uint32_t) & BM_AIPS_PACRF_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRF_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRF_TP4 (12U) //!< Bit position for AIPS_PACRF_TP4.
+#define BM_AIPS_PACRF_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRF_TP4.
+#define BS_AIPS_PACRF_TP4 (1U) //!< Bit field size in bits for AIPS_PACRF_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_TP4 field.
+#define BR_AIPS_PACRF_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_TP4.
+#define BF_AIPS_PACRF_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP4), uint32_t) & BM_AIPS_PACRF_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRF_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRF_WP4 (13U) //!< Bit position for AIPS_PACRF_WP4.
+#define BM_AIPS_PACRF_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRF_WP4.
+#define BS_AIPS_PACRF_WP4 (1U) //!< Bit field size in bits for AIPS_PACRF_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_WP4 field.
+#define BR_AIPS_PACRF_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_WP4.
+#define BF_AIPS_PACRF_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP4), uint32_t) & BM_AIPS_PACRF_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRF_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRF_SP4 (14U) //!< Bit position for AIPS_PACRF_SP4.
+#define BM_AIPS_PACRF_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRF_SP4.
+#define BS_AIPS_PACRF_SP4 (1U) //!< Bit field size in bits for AIPS_PACRF_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_SP4 field.
+#define BR_AIPS_PACRF_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_SP4.
+#define BF_AIPS_PACRF_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP4), uint32_t) & BM_AIPS_PACRF_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRF_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRF_TP3 (16U) //!< Bit position for AIPS_PACRF_TP3.
+#define BM_AIPS_PACRF_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRF_TP3.
+#define BS_AIPS_PACRF_TP3 (1U) //!< Bit field size in bits for AIPS_PACRF_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_TP3 field.
+#define BR_AIPS_PACRF_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_TP3.
+#define BF_AIPS_PACRF_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP3), uint32_t) & BM_AIPS_PACRF_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRF_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRF_WP3 (17U) //!< Bit position for AIPS_PACRF_WP3.
+#define BM_AIPS_PACRF_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRF_WP3.
+#define BS_AIPS_PACRF_WP3 (1U) //!< Bit field size in bits for AIPS_PACRF_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_WP3 field.
+#define BR_AIPS_PACRF_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_WP3.
+#define BF_AIPS_PACRF_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP3), uint32_t) & BM_AIPS_PACRF_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRF_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRF_SP3 (18U) //!< Bit position for AIPS_PACRF_SP3.
+#define BM_AIPS_PACRF_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRF_SP3.
+#define BS_AIPS_PACRF_SP3 (1U) //!< Bit field size in bits for AIPS_PACRF_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_SP3 field.
+#define BR_AIPS_PACRF_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_SP3.
+#define BF_AIPS_PACRF_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP3), uint32_t) & BM_AIPS_PACRF_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRF_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRF_TP2 (20U) //!< Bit position for AIPS_PACRF_TP2.
+#define BM_AIPS_PACRF_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRF_TP2.
+#define BS_AIPS_PACRF_TP2 (1U) //!< Bit field size in bits for AIPS_PACRF_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_TP2 field.
+#define BR_AIPS_PACRF_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_TP2.
+#define BF_AIPS_PACRF_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP2), uint32_t) & BM_AIPS_PACRF_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRF_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRF_WP2 (21U) //!< Bit position for AIPS_PACRF_WP2.
+#define BM_AIPS_PACRF_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRF_WP2.
+#define BS_AIPS_PACRF_WP2 (1U) //!< Bit field size in bits for AIPS_PACRF_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_WP2 field.
+#define BR_AIPS_PACRF_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_WP2.
+#define BF_AIPS_PACRF_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP2), uint32_t) & BM_AIPS_PACRF_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRF_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRF_SP2 (22U) //!< Bit position for AIPS_PACRF_SP2.
+#define BM_AIPS_PACRF_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRF_SP2.
+#define BS_AIPS_PACRF_SP2 (1U) //!< Bit field size in bits for AIPS_PACRF_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_SP2 field.
+#define BR_AIPS_PACRF_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_SP2.
+#define BF_AIPS_PACRF_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP2), uint32_t) & BM_AIPS_PACRF_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRF_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRF_TP1 (24U) //!< Bit position for AIPS_PACRF_TP1.
+#define BM_AIPS_PACRF_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRF_TP1.
+#define BS_AIPS_PACRF_TP1 (1U) //!< Bit field size in bits for AIPS_PACRF_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_TP1 field.
+#define BR_AIPS_PACRF_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_TP1.
+#define BF_AIPS_PACRF_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP1), uint32_t) & BM_AIPS_PACRF_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRF_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRF_WP1 (25U) //!< Bit position for AIPS_PACRF_WP1.
+#define BM_AIPS_PACRF_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRF_WP1.
+#define BS_AIPS_PACRF_WP1 (1U) //!< Bit field size in bits for AIPS_PACRF_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_WP1 field.
+#define BR_AIPS_PACRF_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_WP1.
+#define BF_AIPS_PACRF_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP1), uint32_t) & BM_AIPS_PACRF_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRF_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRF_SP1 (26U) //!< Bit position for AIPS_PACRF_SP1.
+#define BM_AIPS_PACRF_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRF_SP1.
+#define BS_AIPS_PACRF_SP1 (1U) //!< Bit field size in bits for AIPS_PACRF_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_SP1 field.
+#define BR_AIPS_PACRF_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_SP1.
+#define BF_AIPS_PACRF_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP1), uint32_t) & BM_AIPS_PACRF_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRF_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRF_TP0 (28U) //!< Bit position for AIPS_PACRF_TP0.
+#define BM_AIPS_PACRF_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRF_TP0.
+#define BS_AIPS_PACRF_TP0 (1U) //!< Bit field size in bits for AIPS_PACRF_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_TP0 field.
+#define BR_AIPS_PACRF_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_TP0.
+#define BF_AIPS_PACRF_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_TP0), uint32_t) & BM_AIPS_PACRF_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRF_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRF_WP0 (29U) //!< Bit position for AIPS_PACRF_WP0.
+#define BM_AIPS_PACRF_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRF_WP0.
+#define BS_AIPS_PACRF_WP0 (1U) //!< Bit field size in bits for AIPS_PACRF_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_WP0 field.
+#define BR_AIPS_PACRF_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_WP0.
+#define BF_AIPS_PACRF_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_WP0), uint32_t) & BM_AIPS_PACRF_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRF_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRF, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRF_SP0 (30U) //!< Bit position for AIPS_PACRF_SP0.
+#define BM_AIPS_PACRF_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRF_SP0.
+#define BS_AIPS_PACRF_SP0 (1U) //!< Bit field size in bits for AIPS_PACRF_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRF_SP0 field.
+#define BR_AIPS_PACRF_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRF_SP0.
+#define BF_AIPS_PACRF_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRF_SP0), uint32_t) & BM_AIPS_PACRF_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRF_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRG - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRG - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+typedef union _hw_aips_pacrg
+{
+ uint32_t U;
+ struct _hw_aips_pacrg_bitfields
+ {
+ uint32_t TP7 : 1; //!< [0] Trusted Protect
+ uint32_t WP7 : 1; //!< [1] Write Protect
+ uint32_t SP7 : 1; //!< [2] Supervisor Protect
+ uint32_t RESERVED0 : 1; //!< [3]
+ uint32_t TP6 : 1; //!< [4] Trusted Protect
+ uint32_t WP6 : 1; //!< [5] Write Protect
+ uint32_t SP6 : 1; //!< [6] Supervisor Protect
+ uint32_t RESERVED1 : 1; //!< [7]
+ uint32_t TP5 : 1; //!< [8] Trusted Protect
+ uint32_t WP5 : 1; //!< [9] Write Protect
+ uint32_t SP5 : 1; //!< [10] Supervisor Protect
+ uint32_t RESERVED2 : 1; //!< [11]
+ uint32_t TP4 : 1; //!< [12] Trusted Protect
+ uint32_t WP4 : 1; //!< [13] Write Protect
+ uint32_t SP4 : 1; //!< [14] Supervisor Protect
+ uint32_t RESERVED3 : 1; //!< [15]
+ uint32_t TP3 : 1; //!< [16] Trusted Protect
+ uint32_t WP3 : 1; //!< [17] Write Protect
+ uint32_t SP3 : 1; //!< [18] Supervisor Protect
+ uint32_t RESERVED4 : 1; //!< [19]
+ uint32_t TP2 : 1; //!< [20] Trusted Protect
+ uint32_t WP2 : 1; //!< [21] Write Protect
+ uint32_t SP2 : 1; //!< [22] Supervisor Protect
+ uint32_t RESERVED5 : 1; //!< [23]
+ uint32_t TP1 : 1; //!< [24] Trusted Protect
+ uint32_t WP1 : 1; //!< [25] Write Protect
+ uint32_t SP1 : 1; //!< [26] Supervisor Protect
+ uint32_t RESERVED6 : 1; //!< [27]
+ uint32_t TP0 : 1; //!< [28] Trusted Protect
+ uint32_t WP0 : 1; //!< [29] Write Protect
+ uint32_t SP0 : 1; //!< [30] Supervisor Protect
+ uint32_t RESERVED7 : 1; //!< [31]
+ } B;
+} hw_aips_pacrg_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRG register
+ */
+//@{
+#define HW_AIPS_PACRG_ADDR(x) (REGS_AIPS_BASE(x) + 0x48U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRG(x) (*(__IO hw_aips_pacrg_t *) HW_AIPS_PACRG_ADDR(x))
+#define HW_AIPS_PACRG_RD(x) (HW_AIPS_PACRG(x).U)
+#define HW_AIPS_PACRG_WR(x, v) (HW_AIPS_PACRG(x).U = (v))
+#define HW_AIPS_PACRG_SET(x, v) (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) | (v)))
+#define HW_AIPS_PACRG_CLR(x, v) (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) & ~(v)))
+#define HW_AIPS_PACRG_TOG(x, v) (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRG bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRG, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRG_TP7 (0U) //!< Bit position for AIPS_PACRG_TP7.
+#define BM_AIPS_PACRG_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRG_TP7.
+#define BS_AIPS_PACRG_TP7 (1U) //!< Bit field size in bits for AIPS_PACRG_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_TP7 field.
+#define BR_AIPS_PACRG_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_TP7.
+#define BF_AIPS_PACRG_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP7), uint32_t) & BM_AIPS_PACRG_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRG_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRG_WP7 (1U) //!< Bit position for AIPS_PACRG_WP7.
+#define BM_AIPS_PACRG_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRG_WP7.
+#define BS_AIPS_PACRG_WP7 (1U) //!< Bit field size in bits for AIPS_PACRG_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_WP7 field.
+#define BR_AIPS_PACRG_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_WP7.
+#define BF_AIPS_PACRG_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP7), uint32_t) & BM_AIPS_PACRG_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRG_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRG_SP7 (2U) //!< Bit position for AIPS_PACRG_SP7.
+#define BM_AIPS_PACRG_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRG_SP7.
+#define BS_AIPS_PACRG_SP7 (1U) //!< Bit field size in bits for AIPS_PACRG_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_SP7 field.
+#define BR_AIPS_PACRG_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_SP7.
+#define BF_AIPS_PACRG_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP7), uint32_t) & BM_AIPS_PACRG_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRG_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRG_TP6 (4U) //!< Bit position for AIPS_PACRG_TP6.
+#define BM_AIPS_PACRG_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRG_TP6.
+#define BS_AIPS_PACRG_TP6 (1U) //!< Bit field size in bits for AIPS_PACRG_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_TP6 field.
+#define BR_AIPS_PACRG_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_TP6.
+#define BF_AIPS_PACRG_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP6), uint32_t) & BM_AIPS_PACRG_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRG_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRG_WP6 (5U) //!< Bit position for AIPS_PACRG_WP6.
+#define BM_AIPS_PACRG_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRG_WP6.
+#define BS_AIPS_PACRG_WP6 (1U) //!< Bit field size in bits for AIPS_PACRG_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_WP6 field.
+#define BR_AIPS_PACRG_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_WP6.
+#define BF_AIPS_PACRG_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP6), uint32_t) & BM_AIPS_PACRG_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRG_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRG_SP6 (6U) //!< Bit position for AIPS_PACRG_SP6.
+#define BM_AIPS_PACRG_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRG_SP6.
+#define BS_AIPS_PACRG_SP6 (1U) //!< Bit field size in bits for AIPS_PACRG_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_SP6 field.
+#define BR_AIPS_PACRG_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_SP6.
+#define BF_AIPS_PACRG_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP6), uint32_t) & BM_AIPS_PACRG_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRG_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRG_TP5 (8U) //!< Bit position for AIPS_PACRG_TP5.
+#define BM_AIPS_PACRG_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRG_TP5.
+#define BS_AIPS_PACRG_TP5 (1U) //!< Bit field size in bits for AIPS_PACRG_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_TP5 field.
+#define BR_AIPS_PACRG_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_TP5.
+#define BF_AIPS_PACRG_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP5), uint32_t) & BM_AIPS_PACRG_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRG_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRG_WP5 (9U) //!< Bit position for AIPS_PACRG_WP5.
+#define BM_AIPS_PACRG_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRG_WP5.
+#define BS_AIPS_PACRG_WP5 (1U) //!< Bit field size in bits for AIPS_PACRG_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_WP5 field.
+#define BR_AIPS_PACRG_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_WP5.
+#define BF_AIPS_PACRG_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP5), uint32_t) & BM_AIPS_PACRG_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRG_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRG_SP5 (10U) //!< Bit position for AIPS_PACRG_SP5.
+#define BM_AIPS_PACRG_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRG_SP5.
+#define BS_AIPS_PACRG_SP5 (1U) //!< Bit field size in bits for AIPS_PACRG_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_SP5 field.
+#define BR_AIPS_PACRG_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_SP5.
+#define BF_AIPS_PACRG_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP5), uint32_t) & BM_AIPS_PACRG_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRG_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRG_TP4 (12U) //!< Bit position for AIPS_PACRG_TP4.
+#define BM_AIPS_PACRG_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRG_TP4.
+#define BS_AIPS_PACRG_TP4 (1U) //!< Bit field size in bits for AIPS_PACRG_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_TP4 field.
+#define BR_AIPS_PACRG_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_TP4.
+#define BF_AIPS_PACRG_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP4), uint32_t) & BM_AIPS_PACRG_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRG_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRG_WP4 (13U) //!< Bit position for AIPS_PACRG_WP4.
+#define BM_AIPS_PACRG_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRG_WP4.
+#define BS_AIPS_PACRG_WP4 (1U) //!< Bit field size in bits for AIPS_PACRG_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_WP4 field.
+#define BR_AIPS_PACRG_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_WP4.
+#define BF_AIPS_PACRG_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP4), uint32_t) & BM_AIPS_PACRG_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRG_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRG_SP4 (14U) //!< Bit position for AIPS_PACRG_SP4.
+#define BM_AIPS_PACRG_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRG_SP4.
+#define BS_AIPS_PACRG_SP4 (1U) //!< Bit field size in bits for AIPS_PACRG_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_SP4 field.
+#define BR_AIPS_PACRG_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_SP4.
+#define BF_AIPS_PACRG_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP4), uint32_t) & BM_AIPS_PACRG_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRG_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRG_TP3 (16U) //!< Bit position for AIPS_PACRG_TP3.
+#define BM_AIPS_PACRG_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRG_TP3.
+#define BS_AIPS_PACRG_TP3 (1U) //!< Bit field size in bits for AIPS_PACRG_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_TP3 field.
+#define BR_AIPS_PACRG_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_TP3.
+#define BF_AIPS_PACRG_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP3), uint32_t) & BM_AIPS_PACRG_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRG_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRG_WP3 (17U) //!< Bit position for AIPS_PACRG_WP3.
+#define BM_AIPS_PACRG_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRG_WP3.
+#define BS_AIPS_PACRG_WP3 (1U) //!< Bit field size in bits for AIPS_PACRG_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_WP3 field.
+#define BR_AIPS_PACRG_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_WP3.
+#define BF_AIPS_PACRG_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP3), uint32_t) & BM_AIPS_PACRG_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRG_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRG_SP3 (18U) //!< Bit position for AIPS_PACRG_SP3.
+#define BM_AIPS_PACRG_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRG_SP3.
+#define BS_AIPS_PACRG_SP3 (1U) //!< Bit field size in bits for AIPS_PACRG_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_SP3 field.
+#define BR_AIPS_PACRG_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_SP3.
+#define BF_AIPS_PACRG_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP3), uint32_t) & BM_AIPS_PACRG_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRG_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRG_TP2 (20U) //!< Bit position for AIPS_PACRG_TP2.
+#define BM_AIPS_PACRG_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRG_TP2.
+#define BS_AIPS_PACRG_TP2 (1U) //!< Bit field size in bits for AIPS_PACRG_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_TP2 field.
+#define BR_AIPS_PACRG_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_TP2.
+#define BF_AIPS_PACRG_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP2), uint32_t) & BM_AIPS_PACRG_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRG_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRG_WP2 (21U) //!< Bit position for AIPS_PACRG_WP2.
+#define BM_AIPS_PACRG_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRG_WP2.
+#define BS_AIPS_PACRG_WP2 (1U) //!< Bit field size in bits for AIPS_PACRG_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_WP2 field.
+#define BR_AIPS_PACRG_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_WP2.
+#define BF_AIPS_PACRG_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP2), uint32_t) & BM_AIPS_PACRG_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRG_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRG_SP2 (22U) //!< Bit position for AIPS_PACRG_SP2.
+#define BM_AIPS_PACRG_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRG_SP2.
+#define BS_AIPS_PACRG_SP2 (1U) //!< Bit field size in bits for AIPS_PACRG_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_SP2 field.
+#define BR_AIPS_PACRG_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_SP2.
+#define BF_AIPS_PACRG_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP2), uint32_t) & BM_AIPS_PACRG_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRG_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRG_TP1 (24U) //!< Bit position for AIPS_PACRG_TP1.
+#define BM_AIPS_PACRG_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRG_TP1.
+#define BS_AIPS_PACRG_TP1 (1U) //!< Bit field size in bits for AIPS_PACRG_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_TP1 field.
+#define BR_AIPS_PACRG_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_TP1.
+#define BF_AIPS_PACRG_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP1), uint32_t) & BM_AIPS_PACRG_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRG_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRG_WP1 (25U) //!< Bit position for AIPS_PACRG_WP1.
+#define BM_AIPS_PACRG_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRG_WP1.
+#define BS_AIPS_PACRG_WP1 (1U) //!< Bit field size in bits for AIPS_PACRG_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_WP1 field.
+#define BR_AIPS_PACRG_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_WP1.
+#define BF_AIPS_PACRG_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP1), uint32_t) & BM_AIPS_PACRG_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRG_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRG_SP1 (26U) //!< Bit position for AIPS_PACRG_SP1.
+#define BM_AIPS_PACRG_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRG_SP1.
+#define BS_AIPS_PACRG_SP1 (1U) //!< Bit field size in bits for AIPS_PACRG_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_SP1 field.
+#define BR_AIPS_PACRG_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_SP1.
+#define BF_AIPS_PACRG_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP1), uint32_t) & BM_AIPS_PACRG_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRG_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRG_TP0 (28U) //!< Bit position for AIPS_PACRG_TP0.
+#define BM_AIPS_PACRG_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRG_TP0.
+#define BS_AIPS_PACRG_TP0 (1U) //!< Bit field size in bits for AIPS_PACRG_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_TP0 field.
+#define BR_AIPS_PACRG_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_TP0.
+#define BF_AIPS_PACRG_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_TP0), uint32_t) & BM_AIPS_PACRG_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRG_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRG_WP0 (29U) //!< Bit position for AIPS_PACRG_WP0.
+#define BM_AIPS_PACRG_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRG_WP0.
+#define BS_AIPS_PACRG_WP0 (1U) //!< Bit field size in bits for AIPS_PACRG_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_WP0 field.
+#define BR_AIPS_PACRG_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_WP0.
+#define BF_AIPS_PACRG_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_WP0), uint32_t) & BM_AIPS_PACRG_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRG_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRG, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRG_SP0 (30U) //!< Bit position for AIPS_PACRG_SP0.
+#define BM_AIPS_PACRG_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRG_SP0.
+#define BS_AIPS_PACRG_SP0 (1U) //!< Bit field size in bits for AIPS_PACRG_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRG_SP0 field.
+#define BR_AIPS_PACRG_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRG_SP0.
+#define BF_AIPS_PACRG_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRG_SP0), uint32_t) & BM_AIPS_PACRG_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRG_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRH - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRH - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+typedef union _hw_aips_pacrh
+{
+ uint32_t U;
+ struct _hw_aips_pacrh_bitfields
+ {
+ uint32_t TP7 : 1; //!< [0] Trusted Protect
+ uint32_t WP7 : 1; //!< [1] Write Protect
+ uint32_t SP7 : 1; //!< [2] Supervisor Protect
+ uint32_t RESERVED0 : 1; //!< [3]
+ uint32_t TP6 : 1; //!< [4] Trusted Protect
+ uint32_t WP6 : 1; //!< [5] Write Protect
+ uint32_t SP6 : 1; //!< [6] Supervisor Protect
+ uint32_t RESERVED1 : 1; //!< [7]
+ uint32_t TP5 : 1; //!< [8] Trusted Protect
+ uint32_t WP5 : 1; //!< [9] Write Protect
+ uint32_t SP5 : 1; //!< [10] Supervisor Protect
+ uint32_t RESERVED2 : 1; //!< [11]
+ uint32_t TP4 : 1; //!< [12] Trusted Protect
+ uint32_t WP4 : 1; //!< [13] Write Protect
+ uint32_t SP4 : 1; //!< [14] Supervisor Protect
+ uint32_t RESERVED3 : 1; //!< [15]
+ uint32_t TP3 : 1; //!< [16] Trusted Protect
+ uint32_t WP3 : 1; //!< [17] Write Protect
+ uint32_t SP3 : 1; //!< [18] Supervisor Protect
+ uint32_t RESERVED4 : 1; //!< [19]
+ uint32_t TP2 : 1; //!< [20] Trusted Protect
+ uint32_t WP2 : 1; //!< [21] Write Protect
+ uint32_t SP2 : 1; //!< [22] Supervisor Protect
+ uint32_t RESERVED5 : 1; //!< [23]
+ uint32_t TP1 : 1; //!< [24] Trusted Protect
+ uint32_t WP1 : 1; //!< [25] Write Protect
+ uint32_t SP1 : 1; //!< [26] Supervisor Protect
+ uint32_t RESERVED6 : 1; //!< [27]
+ uint32_t TP0 : 1; //!< [28] Trusted Protect
+ uint32_t WP0 : 1; //!< [29] Write Protect
+ uint32_t SP0 : 1; //!< [30] Supervisor Protect
+ uint32_t RESERVED7 : 1; //!< [31]
+ } B;
+} hw_aips_pacrh_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRH register
+ */
+//@{
+#define HW_AIPS_PACRH_ADDR(x) (REGS_AIPS_BASE(x) + 0x4CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRH(x) (*(__IO hw_aips_pacrh_t *) HW_AIPS_PACRH_ADDR(x))
+#define HW_AIPS_PACRH_RD(x) (HW_AIPS_PACRH(x).U)
+#define HW_AIPS_PACRH_WR(x, v) (HW_AIPS_PACRH(x).U = (v))
+#define HW_AIPS_PACRH_SET(x, v) (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) | (v)))
+#define HW_AIPS_PACRH_CLR(x, v) (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) & ~(v)))
+#define HW_AIPS_PACRH_TOG(x, v) (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRH bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRH, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRH_TP7 (0U) //!< Bit position for AIPS_PACRH_TP7.
+#define BM_AIPS_PACRH_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRH_TP7.
+#define BS_AIPS_PACRH_TP7 (1U) //!< Bit field size in bits for AIPS_PACRH_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_TP7 field.
+#define BR_AIPS_PACRH_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_TP7.
+#define BF_AIPS_PACRH_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP7), uint32_t) & BM_AIPS_PACRH_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRH_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRH_WP7 (1U) //!< Bit position for AIPS_PACRH_WP7.
+#define BM_AIPS_PACRH_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRH_WP7.
+#define BS_AIPS_PACRH_WP7 (1U) //!< Bit field size in bits for AIPS_PACRH_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_WP7 field.
+#define BR_AIPS_PACRH_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_WP7.
+#define BF_AIPS_PACRH_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP7), uint32_t) & BM_AIPS_PACRH_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRH_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRH_SP7 (2U) //!< Bit position for AIPS_PACRH_SP7.
+#define BM_AIPS_PACRH_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRH_SP7.
+#define BS_AIPS_PACRH_SP7 (1U) //!< Bit field size in bits for AIPS_PACRH_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_SP7 field.
+#define BR_AIPS_PACRH_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_SP7.
+#define BF_AIPS_PACRH_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP7), uint32_t) & BM_AIPS_PACRH_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRH_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRH_TP6 (4U) //!< Bit position for AIPS_PACRH_TP6.
+#define BM_AIPS_PACRH_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRH_TP6.
+#define BS_AIPS_PACRH_TP6 (1U) //!< Bit field size in bits for AIPS_PACRH_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_TP6 field.
+#define BR_AIPS_PACRH_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_TP6.
+#define BF_AIPS_PACRH_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP6), uint32_t) & BM_AIPS_PACRH_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRH_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRH_WP6 (5U) //!< Bit position for AIPS_PACRH_WP6.
+#define BM_AIPS_PACRH_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRH_WP6.
+#define BS_AIPS_PACRH_WP6 (1U) //!< Bit field size in bits for AIPS_PACRH_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_WP6 field.
+#define BR_AIPS_PACRH_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_WP6.
+#define BF_AIPS_PACRH_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP6), uint32_t) & BM_AIPS_PACRH_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRH_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRH_SP6 (6U) //!< Bit position for AIPS_PACRH_SP6.
+#define BM_AIPS_PACRH_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRH_SP6.
+#define BS_AIPS_PACRH_SP6 (1U) //!< Bit field size in bits for AIPS_PACRH_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_SP6 field.
+#define BR_AIPS_PACRH_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_SP6.
+#define BF_AIPS_PACRH_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP6), uint32_t) & BM_AIPS_PACRH_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRH_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRH_TP5 (8U) //!< Bit position for AIPS_PACRH_TP5.
+#define BM_AIPS_PACRH_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRH_TP5.
+#define BS_AIPS_PACRH_TP5 (1U) //!< Bit field size in bits for AIPS_PACRH_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_TP5 field.
+#define BR_AIPS_PACRH_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_TP5.
+#define BF_AIPS_PACRH_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP5), uint32_t) & BM_AIPS_PACRH_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRH_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRH_WP5 (9U) //!< Bit position for AIPS_PACRH_WP5.
+#define BM_AIPS_PACRH_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRH_WP5.
+#define BS_AIPS_PACRH_WP5 (1U) //!< Bit field size in bits for AIPS_PACRH_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_WP5 field.
+#define BR_AIPS_PACRH_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_WP5.
+#define BF_AIPS_PACRH_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP5), uint32_t) & BM_AIPS_PACRH_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRH_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRH_SP5 (10U) //!< Bit position for AIPS_PACRH_SP5.
+#define BM_AIPS_PACRH_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRH_SP5.
+#define BS_AIPS_PACRH_SP5 (1U) //!< Bit field size in bits for AIPS_PACRH_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_SP5 field.
+#define BR_AIPS_PACRH_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_SP5.
+#define BF_AIPS_PACRH_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP5), uint32_t) & BM_AIPS_PACRH_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRH_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRH_TP4 (12U) //!< Bit position for AIPS_PACRH_TP4.
+#define BM_AIPS_PACRH_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRH_TP4.
+#define BS_AIPS_PACRH_TP4 (1U) //!< Bit field size in bits for AIPS_PACRH_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_TP4 field.
+#define BR_AIPS_PACRH_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_TP4.
+#define BF_AIPS_PACRH_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP4), uint32_t) & BM_AIPS_PACRH_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRH_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRH_WP4 (13U) //!< Bit position for AIPS_PACRH_WP4.
+#define BM_AIPS_PACRH_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRH_WP4.
+#define BS_AIPS_PACRH_WP4 (1U) //!< Bit field size in bits for AIPS_PACRH_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_WP4 field.
+#define BR_AIPS_PACRH_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_WP4.
+#define BF_AIPS_PACRH_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP4), uint32_t) & BM_AIPS_PACRH_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRH_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRH_SP4 (14U) //!< Bit position for AIPS_PACRH_SP4.
+#define BM_AIPS_PACRH_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRH_SP4.
+#define BS_AIPS_PACRH_SP4 (1U) //!< Bit field size in bits for AIPS_PACRH_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_SP4 field.
+#define BR_AIPS_PACRH_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_SP4.
+#define BF_AIPS_PACRH_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP4), uint32_t) & BM_AIPS_PACRH_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRH_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRH_TP3 (16U) //!< Bit position for AIPS_PACRH_TP3.
+#define BM_AIPS_PACRH_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRH_TP3.
+#define BS_AIPS_PACRH_TP3 (1U) //!< Bit field size in bits for AIPS_PACRH_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_TP3 field.
+#define BR_AIPS_PACRH_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_TP3.
+#define BF_AIPS_PACRH_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP3), uint32_t) & BM_AIPS_PACRH_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRH_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRH_WP3 (17U) //!< Bit position for AIPS_PACRH_WP3.
+#define BM_AIPS_PACRH_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRH_WP3.
+#define BS_AIPS_PACRH_WP3 (1U) //!< Bit field size in bits for AIPS_PACRH_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_WP3 field.
+#define BR_AIPS_PACRH_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_WP3.
+#define BF_AIPS_PACRH_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP3), uint32_t) & BM_AIPS_PACRH_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRH_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRH_SP3 (18U) //!< Bit position for AIPS_PACRH_SP3.
+#define BM_AIPS_PACRH_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRH_SP3.
+#define BS_AIPS_PACRH_SP3 (1U) //!< Bit field size in bits for AIPS_PACRH_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_SP3 field.
+#define BR_AIPS_PACRH_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_SP3.
+#define BF_AIPS_PACRH_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP3), uint32_t) & BM_AIPS_PACRH_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRH_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRH_TP2 (20U) //!< Bit position for AIPS_PACRH_TP2.
+#define BM_AIPS_PACRH_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRH_TP2.
+#define BS_AIPS_PACRH_TP2 (1U) //!< Bit field size in bits for AIPS_PACRH_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_TP2 field.
+#define BR_AIPS_PACRH_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_TP2.
+#define BF_AIPS_PACRH_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP2), uint32_t) & BM_AIPS_PACRH_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRH_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRH_WP2 (21U) //!< Bit position for AIPS_PACRH_WP2.
+#define BM_AIPS_PACRH_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRH_WP2.
+#define BS_AIPS_PACRH_WP2 (1U) //!< Bit field size in bits for AIPS_PACRH_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_WP2 field.
+#define BR_AIPS_PACRH_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_WP2.
+#define BF_AIPS_PACRH_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP2), uint32_t) & BM_AIPS_PACRH_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRH_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRH_SP2 (22U) //!< Bit position for AIPS_PACRH_SP2.
+#define BM_AIPS_PACRH_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRH_SP2.
+#define BS_AIPS_PACRH_SP2 (1U) //!< Bit field size in bits for AIPS_PACRH_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_SP2 field.
+#define BR_AIPS_PACRH_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_SP2.
+#define BF_AIPS_PACRH_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP2), uint32_t) & BM_AIPS_PACRH_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRH_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRH_TP1 (24U) //!< Bit position for AIPS_PACRH_TP1.
+#define BM_AIPS_PACRH_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRH_TP1.
+#define BS_AIPS_PACRH_TP1 (1U) //!< Bit field size in bits for AIPS_PACRH_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_TP1 field.
+#define BR_AIPS_PACRH_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_TP1.
+#define BF_AIPS_PACRH_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP1), uint32_t) & BM_AIPS_PACRH_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRH_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRH_WP1 (25U) //!< Bit position for AIPS_PACRH_WP1.
+#define BM_AIPS_PACRH_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRH_WP1.
+#define BS_AIPS_PACRH_WP1 (1U) //!< Bit field size in bits for AIPS_PACRH_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_WP1 field.
+#define BR_AIPS_PACRH_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_WP1.
+#define BF_AIPS_PACRH_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP1), uint32_t) & BM_AIPS_PACRH_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRH_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRH_SP1 (26U) //!< Bit position for AIPS_PACRH_SP1.
+#define BM_AIPS_PACRH_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRH_SP1.
+#define BS_AIPS_PACRH_SP1 (1U) //!< Bit field size in bits for AIPS_PACRH_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_SP1 field.
+#define BR_AIPS_PACRH_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_SP1.
+#define BF_AIPS_PACRH_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP1), uint32_t) & BM_AIPS_PACRH_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRH_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRH_TP0 (28U) //!< Bit position for AIPS_PACRH_TP0.
+#define BM_AIPS_PACRH_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRH_TP0.
+#define BS_AIPS_PACRH_TP0 (1U) //!< Bit field size in bits for AIPS_PACRH_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_TP0 field.
+#define BR_AIPS_PACRH_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_TP0.
+#define BF_AIPS_PACRH_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_TP0), uint32_t) & BM_AIPS_PACRH_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRH_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRH_WP0 (29U) //!< Bit position for AIPS_PACRH_WP0.
+#define BM_AIPS_PACRH_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRH_WP0.
+#define BS_AIPS_PACRH_WP0 (1U) //!< Bit field size in bits for AIPS_PACRH_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_WP0 field.
+#define BR_AIPS_PACRH_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_WP0.
+#define BF_AIPS_PACRH_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_WP0), uint32_t) & BM_AIPS_PACRH_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRH_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRH, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRH_SP0 (30U) //!< Bit position for AIPS_PACRH_SP0.
+#define BM_AIPS_PACRH_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRH_SP0.
+#define BS_AIPS_PACRH_SP0 (1U) //!< Bit field size in bits for AIPS_PACRH_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRH_SP0 field.
+#define BR_AIPS_PACRH_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRH_SP0.
+#define BF_AIPS_PACRH_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRH_SP0), uint32_t) & BM_AIPS_PACRH_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRH_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRI - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRI - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+typedef union _hw_aips_pacri
+{
+ uint32_t U;
+ struct _hw_aips_pacri_bitfields
+ {
+ uint32_t TP7 : 1; //!< [0] Trusted Protect
+ uint32_t WP7 : 1; //!< [1] Write Protect
+ uint32_t SP7 : 1; //!< [2] Supervisor Protect
+ uint32_t RESERVED0 : 1; //!< [3]
+ uint32_t TP6 : 1; //!< [4] Trusted Protect
+ uint32_t WP6 : 1; //!< [5] Write Protect
+ uint32_t SP6 : 1; //!< [6] Supervisor Protect
+ uint32_t RESERVED1 : 1; //!< [7]
+ uint32_t TP5 : 1; //!< [8] Trusted Protect
+ uint32_t WP5 : 1; //!< [9] Write Protect
+ uint32_t SP5 : 1; //!< [10] Supervisor Protect
+ uint32_t RESERVED2 : 1; //!< [11]
+ uint32_t TP4 : 1; //!< [12] Trusted Protect
+ uint32_t WP4 : 1; //!< [13] Write Protect
+ uint32_t SP4 : 1; //!< [14] Supervisor Protect
+ uint32_t RESERVED3 : 1; //!< [15]
+ uint32_t TP3 : 1; //!< [16] Trusted Protect
+ uint32_t WP3 : 1; //!< [17] Write Protect
+ uint32_t SP3 : 1; //!< [18] Supervisor Protect
+ uint32_t RESERVED4 : 1; //!< [19]
+ uint32_t TP2 : 1; //!< [20] Trusted Protect
+ uint32_t WP2 : 1; //!< [21] Write Protect
+ uint32_t SP2 : 1; //!< [22] Supervisor Protect
+ uint32_t RESERVED5 : 1; //!< [23]
+ uint32_t TP1 : 1; //!< [24] Trusted Protect
+ uint32_t WP1 : 1; //!< [25] Write Protect
+ uint32_t SP1 : 1; //!< [26] Supervisor Protect
+ uint32_t RESERVED6 : 1; //!< [27]
+ uint32_t TP0 : 1; //!< [28] Trusted Protect
+ uint32_t WP0 : 1; //!< [29] Write Protect
+ uint32_t SP0 : 1; //!< [30] Supervisor Protect
+ uint32_t RESERVED7 : 1; //!< [31]
+ } B;
+} hw_aips_pacri_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRI register
+ */
+//@{
+#define HW_AIPS_PACRI_ADDR(x) (REGS_AIPS_BASE(x) + 0x50U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRI(x) (*(__IO hw_aips_pacri_t *) HW_AIPS_PACRI_ADDR(x))
+#define HW_AIPS_PACRI_RD(x) (HW_AIPS_PACRI(x).U)
+#define HW_AIPS_PACRI_WR(x, v) (HW_AIPS_PACRI(x).U = (v))
+#define HW_AIPS_PACRI_SET(x, v) (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) | (v)))
+#define HW_AIPS_PACRI_CLR(x, v) (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) & ~(v)))
+#define HW_AIPS_PACRI_TOG(x, v) (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRI bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRI, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRI_TP7 (0U) //!< Bit position for AIPS_PACRI_TP7.
+#define BM_AIPS_PACRI_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRI_TP7.
+#define BS_AIPS_PACRI_TP7 (1U) //!< Bit field size in bits for AIPS_PACRI_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_TP7 field.
+#define BR_AIPS_PACRI_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_TP7.
+#define BF_AIPS_PACRI_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP7), uint32_t) & BM_AIPS_PACRI_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRI_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRI_WP7 (1U) //!< Bit position for AIPS_PACRI_WP7.
+#define BM_AIPS_PACRI_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRI_WP7.
+#define BS_AIPS_PACRI_WP7 (1U) //!< Bit field size in bits for AIPS_PACRI_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_WP7 field.
+#define BR_AIPS_PACRI_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_WP7.
+#define BF_AIPS_PACRI_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP7), uint32_t) & BM_AIPS_PACRI_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRI_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRI_SP7 (2U) //!< Bit position for AIPS_PACRI_SP7.
+#define BM_AIPS_PACRI_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRI_SP7.
+#define BS_AIPS_PACRI_SP7 (1U) //!< Bit field size in bits for AIPS_PACRI_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_SP7 field.
+#define BR_AIPS_PACRI_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_SP7.
+#define BF_AIPS_PACRI_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP7), uint32_t) & BM_AIPS_PACRI_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRI_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRI_TP6 (4U) //!< Bit position for AIPS_PACRI_TP6.
+#define BM_AIPS_PACRI_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRI_TP6.
+#define BS_AIPS_PACRI_TP6 (1U) //!< Bit field size in bits for AIPS_PACRI_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_TP6 field.
+#define BR_AIPS_PACRI_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_TP6.
+#define BF_AIPS_PACRI_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP6), uint32_t) & BM_AIPS_PACRI_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRI_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRI_WP6 (5U) //!< Bit position for AIPS_PACRI_WP6.
+#define BM_AIPS_PACRI_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRI_WP6.
+#define BS_AIPS_PACRI_WP6 (1U) //!< Bit field size in bits for AIPS_PACRI_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_WP6 field.
+#define BR_AIPS_PACRI_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_WP6.
+#define BF_AIPS_PACRI_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP6), uint32_t) & BM_AIPS_PACRI_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRI_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRI_SP6 (6U) //!< Bit position for AIPS_PACRI_SP6.
+#define BM_AIPS_PACRI_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRI_SP6.
+#define BS_AIPS_PACRI_SP6 (1U) //!< Bit field size in bits for AIPS_PACRI_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_SP6 field.
+#define BR_AIPS_PACRI_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_SP6.
+#define BF_AIPS_PACRI_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP6), uint32_t) & BM_AIPS_PACRI_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRI_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRI_TP5 (8U) //!< Bit position for AIPS_PACRI_TP5.
+#define BM_AIPS_PACRI_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRI_TP5.
+#define BS_AIPS_PACRI_TP5 (1U) //!< Bit field size in bits for AIPS_PACRI_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_TP5 field.
+#define BR_AIPS_PACRI_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_TP5.
+#define BF_AIPS_PACRI_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP5), uint32_t) & BM_AIPS_PACRI_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRI_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRI_WP5 (9U) //!< Bit position for AIPS_PACRI_WP5.
+#define BM_AIPS_PACRI_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRI_WP5.
+#define BS_AIPS_PACRI_WP5 (1U) //!< Bit field size in bits for AIPS_PACRI_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_WP5 field.
+#define BR_AIPS_PACRI_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_WP5.
+#define BF_AIPS_PACRI_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP5), uint32_t) & BM_AIPS_PACRI_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRI_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRI_SP5 (10U) //!< Bit position for AIPS_PACRI_SP5.
+#define BM_AIPS_PACRI_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRI_SP5.
+#define BS_AIPS_PACRI_SP5 (1U) //!< Bit field size in bits for AIPS_PACRI_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_SP5 field.
+#define BR_AIPS_PACRI_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_SP5.
+#define BF_AIPS_PACRI_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP5), uint32_t) & BM_AIPS_PACRI_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRI_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRI_TP4 (12U) //!< Bit position for AIPS_PACRI_TP4.
+#define BM_AIPS_PACRI_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRI_TP4.
+#define BS_AIPS_PACRI_TP4 (1U) //!< Bit field size in bits for AIPS_PACRI_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_TP4 field.
+#define BR_AIPS_PACRI_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_TP4.
+#define BF_AIPS_PACRI_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP4), uint32_t) & BM_AIPS_PACRI_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRI_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRI_WP4 (13U) //!< Bit position for AIPS_PACRI_WP4.
+#define BM_AIPS_PACRI_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRI_WP4.
+#define BS_AIPS_PACRI_WP4 (1U) //!< Bit field size in bits for AIPS_PACRI_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_WP4 field.
+#define BR_AIPS_PACRI_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_WP4.
+#define BF_AIPS_PACRI_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP4), uint32_t) & BM_AIPS_PACRI_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRI_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRI_SP4 (14U) //!< Bit position for AIPS_PACRI_SP4.
+#define BM_AIPS_PACRI_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRI_SP4.
+#define BS_AIPS_PACRI_SP4 (1U) //!< Bit field size in bits for AIPS_PACRI_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_SP4 field.
+#define BR_AIPS_PACRI_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_SP4.
+#define BF_AIPS_PACRI_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP4), uint32_t) & BM_AIPS_PACRI_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRI_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRI_TP3 (16U) //!< Bit position for AIPS_PACRI_TP3.
+#define BM_AIPS_PACRI_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRI_TP3.
+#define BS_AIPS_PACRI_TP3 (1U) //!< Bit field size in bits for AIPS_PACRI_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_TP3 field.
+#define BR_AIPS_PACRI_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_TP3.
+#define BF_AIPS_PACRI_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP3), uint32_t) & BM_AIPS_PACRI_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRI_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRI_WP3 (17U) //!< Bit position for AIPS_PACRI_WP3.
+#define BM_AIPS_PACRI_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRI_WP3.
+#define BS_AIPS_PACRI_WP3 (1U) //!< Bit field size in bits for AIPS_PACRI_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_WP3 field.
+#define BR_AIPS_PACRI_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_WP3.
+#define BF_AIPS_PACRI_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP3), uint32_t) & BM_AIPS_PACRI_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRI_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRI_SP3 (18U) //!< Bit position for AIPS_PACRI_SP3.
+#define BM_AIPS_PACRI_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRI_SP3.
+#define BS_AIPS_PACRI_SP3 (1U) //!< Bit field size in bits for AIPS_PACRI_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_SP3 field.
+#define BR_AIPS_PACRI_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_SP3.
+#define BF_AIPS_PACRI_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP3), uint32_t) & BM_AIPS_PACRI_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRI_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRI_TP2 (20U) //!< Bit position for AIPS_PACRI_TP2.
+#define BM_AIPS_PACRI_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRI_TP2.
+#define BS_AIPS_PACRI_TP2 (1U) //!< Bit field size in bits for AIPS_PACRI_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_TP2 field.
+#define BR_AIPS_PACRI_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_TP2.
+#define BF_AIPS_PACRI_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP2), uint32_t) & BM_AIPS_PACRI_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRI_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRI_WP2 (21U) //!< Bit position for AIPS_PACRI_WP2.
+#define BM_AIPS_PACRI_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRI_WP2.
+#define BS_AIPS_PACRI_WP2 (1U) //!< Bit field size in bits for AIPS_PACRI_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_WP2 field.
+#define BR_AIPS_PACRI_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_WP2.
+#define BF_AIPS_PACRI_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP2), uint32_t) & BM_AIPS_PACRI_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRI_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRI_SP2 (22U) //!< Bit position for AIPS_PACRI_SP2.
+#define BM_AIPS_PACRI_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRI_SP2.
+#define BS_AIPS_PACRI_SP2 (1U) //!< Bit field size in bits for AIPS_PACRI_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_SP2 field.
+#define BR_AIPS_PACRI_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_SP2.
+#define BF_AIPS_PACRI_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP2), uint32_t) & BM_AIPS_PACRI_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRI_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRI_TP1 (24U) //!< Bit position for AIPS_PACRI_TP1.
+#define BM_AIPS_PACRI_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRI_TP1.
+#define BS_AIPS_PACRI_TP1 (1U) //!< Bit field size in bits for AIPS_PACRI_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_TP1 field.
+#define BR_AIPS_PACRI_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_TP1.
+#define BF_AIPS_PACRI_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP1), uint32_t) & BM_AIPS_PACRI_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRI_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRI_WP1 (25U) //!< Bit position for AIPS_PACRI_WP1.
+#define BM_AIPS_PACRI_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRI_WP1.
+#define BS_AIPS_PACRI_WP1 (1U) //!< Bit field size in bits for AIPS_PACRI_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_WP1 field.
+#define BR_AIPS_PACRI_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_WP1.
+#define BF_AIPS_PACRI_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP1), uint32_t) & BM_AIPS_PACRI_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRI_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRI_SP1 (26U) //!< Bit position for AIPS_PACRI_SP1.
+#define BM_AIPS_PACRI_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRI_SP1.
+#define BS_AIPS_PACRI_SP1 (1U) //!< Bit field size in bits for AIPS_PACRI_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_SP1 field.
+#define BR_AIPS_PACRI_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_SP1.
+#define BF_AIPS_PACRI_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP1), uint32_t) & BM_AIPS_PACRI_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRI_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRI_TP0 (28U) //!< Bit position for AIPS_PACRI_TP0.
+#define BM_AIPS_PACRI_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRI_TP0.
+#define BS_AIPS_PACRI_TP0 (1U) //!< Bit field size in bits for AIPS_PACRI_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_TP0 field.
+#define BR_AIPS_PACRI_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_TP0.
+#define BF_AIPS_PACRI_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_TP0), uint32_t) & BM_AIPS_PACRI_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRI_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRI_WP0 (29U) //!< Bit position for AIPS_PACRI_WP0.
+#define BM_AIPS_PACRI_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRI_WP0.
+#define BS_AIPS_PACRI_WP0 (1U) //!< Bit field size in bits for AIPS_PACRI_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_WP0 field.
+#define BR_AIPS_PACRI_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_WP0.
+#define BF_AIPS_PACRI_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_WP0), uint32_t) & BM_AIPS_PACRI_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRI_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRI, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRI_SP0 (30U) //!< Bit position for AIPS_PACRI_SP0.
+#define BM_AIPS_PACRI_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRI_SP0.
+#define BS_AIPS_PACRI_SP0 (1U) //!< Bit field size in bits for AIPS_PACRI_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRI_SP0 field.
+#define BR_AIPS_PACRI_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRI_SP0.
+#define BF_AIPS_PACRI_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRI_SP0), uint32_t) & BM_AIPS_PACRI_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRI_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRJ - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRJ - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+typedef union _hw_aips_pacrj
+{
+ uint32_t U;
+ struct _hw_aips_pacrj_bitfields
+ {
+ uint32_t TP7 : 1; //!< [0] Trusted Protect
+ uint32_t WP7 : 1; //!< [1] Write Protect
+ uint32_t SP7 : 1; //!< [2] Supervisor Protect
+ uint32_t RESERVED0 : 1; //!< [3]
+ uint32_t TP6 : 1; //!< [4] Trusted Protect
+ uint32_t WP6 : 1; //!< [5] Write Protect
+ uint32_t SP6 : 1; //!< [6] Supervisor Protect
+ uint32_t RESERVED1 : 1; //!< [7]
+ uint32_t TP5 : 1; //!< [8] Trusted Protect
+ uint32_t WP5 : 1; //!< [9] Write Protect
+ uint32_t SP5 : 1; //!< [10] Supervisor Protect
+ uint32_t RESERVED2 : 1; //!< [11]
+ uint32_t TP4 : 1; //!< [12] Trusted Protect
+ uint32_t WP4 : 1; //!< [13] Write Protect
+ uint32_t SP4 : 1; //!< [14] Supervisor Protect
+ uint32_t RESERVED3 : 1; //!< [15]
+ uint32_t TP3 : 1; //!< [16] Trusted Protect
+ uint32_t WP3 : 1; //!< [17] Write Protect
+ uint32_t SP3 : 1; //!< [18] Supervisor Protect
+ uint32_t RESERVED4 : 1; //!< [19]
+ uint32_t TP2 : 1; //!< [20] Trusted Protect
+ uint32_t WP2 : 1; //!< [21] Write Protect
+ uint32_t SP2 : 1; //!< [22] Supervisor Protect
+ uint32_t RESERVED5 : 1; //!< [23]
+ uint32_t TP1 : 1; //!< [24] Trusted Protect
+ uint32_t WP1 : 1; //!< [25] Write Protect
+ uint32_t SP1 : 1; //!< [26] Supervisor Protect
+ uint32_t RESERVED6 : 1; //!< [27]
+ uint32_t TP0 : 1; //!< [28] Trusted Protect
+ uint32_t WP0 : 1; //!< [29] Write Protect
+ uint32_t SP0 : 1; //!< [30] Supervisor Protect
+ uint32_t RESERVED7 : 1; //!< [31]
+ } B;
+} hw_aips_pacrj_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRJ register
+ */
+//@{
+#define HW_AIPS_PACRJ_ADDR(x) (REGS_AIPS_BASE(x) + 0x54U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRJ(x) (*(__IO hw_aips_pacrj_t *) HW_AIPS_PACRJ_ADDR(x))
+#define HW_AIPS_PACRJ_RD(x) (HW_AIPS_PACRJ(x).U)
+#define HW_AIPS_PACRJ_WR(x, v) (HW_AIPS_PACRJ(x).U = (v))
+#define HW_AIPS_PACRJ_SET(x, v) (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) | (v)))
+#define HW_AIPS_PACRJ_CLR(x, v) (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) & ~(v)))
+#define HW_AIPS_PACRJ_TOG(x, v) (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRJ bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRJ, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRJ_TP7 (0U) //!< Bit position for AIPS_PACRJ_TP7.
+#define BM_AIPS_PACRJ_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRJ_TP7.
+#define BS_AIPS_PACRJ_TP7 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_TP7 field.
+#define BR_AIPS_PACRJ_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_TP7.
+#define BF_AIPS_PACRJ_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP7), uint32_t) & BM_AIPS_PACRJ_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRJ_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRJ_WP7 (1U) //!< Bit position for AIPS_PACRJ_WP7.
+#define BM_AIPS_PACRJ_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRJ_WP7.
+#define BS_AIPS_PACRJ_WP7 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_WP7 field.
+#define BR_AIPS_PACRJ_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_WP7.
+#define BF_AIPS_PACRJ_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP7), uint32_t) & BM_AIPS_PACRJ_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRJ_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRJ_SP7 (2U) //!< Bit position for AIPS_PACRJ_SP7.
+#define BM_AIPS_PACRJ_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRJ_SP7.
+#define BS_AIPS_PACRJ_SP7 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_SP7 field.
+#define BR_AIPS_PACRJ_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_SP7.
+#define BF_AIPS_PACRJ_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP7), uint32_t) & BM_AIPS_PACRJ_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRJ_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRJ_TP6 (4U) //!< Bit position for AIPS_PACRJ_TP6.
+#define BM_AIPS_PACRJ_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRJ_TP6.
+#define BS_AIPS_PACRJ_TP6 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_TP6 field.
+#define BR_AIPS_PACRJ_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_TP6.
+#define BF_AIPS_PACRJ_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP6), uint32_t) & BM_AIPS_PACRJ_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRJ_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRJ_WP6 (5U) //!< Bit position for AIPS_PACRJ_WP6.
+#define BM_AIPS_PACRJ_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRJ_WP6.
+#define BS_AIPS_PACRJ_WP6 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_WP6 field.
+#define BR_AIPS_PACRJ_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_WP6.
+#define BF_AIPS_PACRJ_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP6), uint32_t) & BM_AIPS_PACRJ_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRJ_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRJ_SP6 (6U) //!< Bit position for AIPS_PACRJ_SP6.
+#define BM_AIPS_PACRJ_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRJ_SP6.
+#define BS_AIPS_PACRJ_SP6 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_SP6 field.
+#define BR_AIPS_PACRJ_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_SP6.
+#define BF_AIPS_PACRJ_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP6), uint32_t) & BM_AIPS_PACRJ_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRJ_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRJ_TP5 (8U) //!< Bit position for AIPS_PACRJ_TP5.
+#define BM_AIPS_PACRJ_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRJ_TP5.
+#define BS_AIPS_PACRJ_TP5 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_TP5 field.
+#define BR_AIPS_PACRJ_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_TP5.
+#define BF_AIPS_PACRJ_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP5), uint32_t) & BM_AIPS_PACRJ_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRJ_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRJ_WP5 (9U) //!< Bit position for AIPS_PACRJ_WP5.
+#define BM_AIPS_PACRJ_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRJ_WP5.
+#define BS_AIPS_PACRJ_WP5 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_WP5 field.
+#define BR_AIPS_PACRJ_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_WP5.
+#define BF_AIPS_PACRJ_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP5), uint32_t) & BM_AIPS_PACRJ_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRJ_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRJ_SP5 (10U) //!< Bit position for AIPS_PACRJ_SP5.
+#define BM_AIPS_PACRJ_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRJ_SP5.
+#define BS_AIPS_PACRJ_SP5 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_SP5 field.
+#define BR_AIPS_PACRJ_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_SP5.
+#define BF_AIPS_PACRJ_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP5), uint32_t) & BM_AIPS_PACRJ_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRJ_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRJ_TP4 (12U) //!< Bit position for AIPS_PACRJ_TP4.
+#define BM_AIPS_PACRJ_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRJ_TP4.
+#define BS_AIPS_PACRJ_TP4 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_TP4 field.
+#define BR_AIPS_PACRJ_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_TP4.
+#define BF_AIPS_PACRJ_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP4), uint32_t) & BM_AIPS_PACRJ_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRJ_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRJ_WP4 (13U) //!< Bit position for AIPS_PACRJ_WP4.
+#define BM_AIPS_PACRJ_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRJ_WP4.
+#define BS_AIPS_PACRJ_WP4 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_WP4 field.
+#define BR_AIPS_PACRJ_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_WP4.
+#define BF_AIPS_PACRJ_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP4), uint32_t) & BM_AIPS_PACRJ_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRJ_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRJ_SP4 (14U) //!< Bit position for AIPS_PACRJ_SP4.
+#define BM_AIPS_PACRJ_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRJ_SP4.
+#define BS_AIPS_PACRJ_SP4 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_SP4 field.
+#define BR_AIPS_PACRJ_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_SP4.
+#define BF_AIPS_PACRJ_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP4), uint32_t) & BM_AIPS_PACRJ_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRJ_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRJ_TP3 (16U) //!< Bit position for AIPS_PACRJ_TP3.
+#define BM_AIPS_PACRJ_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRJ_TP3.
+#define BS_AIPS_PACRJ_TP3 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_TP3 field.
+#define BR_AIPS_PACRJ_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_TP3.
+#define BF_AIPS_PACRJ_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP3), uint32_t) & BM_AIPS_PACRJ_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRJ_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRJ_WP3 (17U) //!< Bit position for AIPS_PACRJ_WP3.
+#define BM_AIPS_PACRJ_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRJ_WP3.
+#define BS_AIPS_PACRJ_WP3 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_WP3 field.
+#define BR_AIPS_PACRJ_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_WP3.
+#define BF_AIPS_PACRJ_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP3), uint32_t) & BM_AIPS_PACRJ_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRJ_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRJ_SP3 (18U) //!< Bit position for AIPS_PACRJ_SP3.
+#define BM_AIPS_PACRJ_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRJ_SP3.
+#define BS_AIPS_PACRJ_SP3 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_SP3 field.
+#define BR_AIPS_PACRJ_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_SP3.
+#define BF_AIPS_PACRJ_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP3), uint32_t) & BM_AIPS_PACRJ_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRJ_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRJ_TP2 (20U) //!< Bit position for AIPS_PACRJ_TP2.
+#define BM_AIPS_PACRJ_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRJ_TP2.
+#define BS_AIPS_PACRJ_TP2 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_TP2 field.
+#define BR_AIPS_PACRJ_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_TP2.
+#define BF_AIPS_PACRJ_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP2), uint32_t) & BM_AIPS_PACRJ_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRJ_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRJ_WP2 (21U) //!< Bit position for AIPS_PACRJ_WP2.
+#define BM_AIPS_PACRJ_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRJ_WP2.
+#define BS_AIPS_PACRJ_WP2 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_WP2 field.
+#define BR_AIPS_PACRJ_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_WP2.
+#define BF_AIPS_PACRJ_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP2), uint32_t) & BM_AIPS_PACRJ_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRJ_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRJ_SP2 (22U) //!< Bit position for AIPS_PACRJ_SP2.
+#define BM_AIPS_PACRJ_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRJ_SP2.
+#define BS_AIPS_PACRJ_SP2 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_SP2 field.
+#define BR_AIPS_PACRJ_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_SP2.
+#define BF_AIPS_PACRJ_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP2), uint32_t) & BM_AIPS_PACRJ_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRJ_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRJ_TP1 (24U) //!< Bit position for AIPS_PACRJ_TP1.
+#define BM_AIPS_PACRJ_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRJ_TP1.
+#define BS_AIPS_PACRJ_TP1 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_TP1 field.
+#define BR_AIPS_PACRJ_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_TP1.
+#define BF_AIPS_PACRJ_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP1), uint32_t) & BM_AIPS_PACRJ_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRJ_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRJ_WP1 (25U) //!< Bit position for AIPS_PACRJ_WP1.
+#define BM_AIPS_PACRJ_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRJ_WP1.
+#define BS_AIPS_PACRJ_WP1 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_WP1 field.
+#define BR_AIPS_PACRJ_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_WP1.
+#define BF_AIPS_PACRJ_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP1), uint32_t) & BM_AIPS_PACRJ_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRJ_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRJ_SP1 (26U) //!< Bit position for AIPS_PACRJ_SP1.
+#define BM_AIPS_PACRJ_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRJ_SP1.
+#define BS_AIPS_PACRJ_SP1 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_SP1 field.
+#define BR_AIPS_PACRJ_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_SP1.
+#define BF_AIPS_PACRJ_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP1), uint32_t) & BM_AIPS_PACRJ_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRJ_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRJ_TP0 (28U) //!< Bit position for AIPS_PACRJ_TP0.
+#define BM_AIPS_PACRJ_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRJ_TP0.
+#define BS_AIPS_PACRJ_TP0 (1U) //!< Bit field size in bits for AIPS_PACRJ_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_TP0 field.
+#define BR_AIPS_PACRJ_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_TP0.
+#define BF_AIPS_PACRJ_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_TP0), uint32_t) & BM_AIPS_PACRJ_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRJ_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRJ_WP0 (29U) //!< Bit position for AIPS_PACRJ_WP0.
+#define BM_AIPS_PACRJ_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRJ_WP0.
+#define BS_AIPS_PACRJ_WP0 (1U) //!< Bit field size in bits for AIPS_PACRJ_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_WP0 field.
+#define BR_AIPS_PACRJ_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_WP0.
+#define BF_AIPS_PACRJ_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_WP0), uint32_t) & BM_AIPS_PACRJ_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRJ_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRJ, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRJ_SP0 (30U) //!< Bit position for AIPS_PACRJ_SP0.
+#define BM_AIPS_PACRJ_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRJ_SP0.
+#define BS_AIPS_PACRJ_SP0 (1U) //!< Bit field size in bits for AIPS_PACRJ_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRJ_SP0 field.
+#define BR_AIPS_PACRJ_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRJ_SP0.
+#define BF_AIPS_PACRJ_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRJ_SP0), uint32_t) & BM_AIPS_PACRJ_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRJ_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRK - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRK - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+typedef union _hw_aips_pacrk
+{
+ uint32_t U;
+ struct _hw_aips_pacrk_bitfields
+ {
+ uint32_t TP7 : 1; //!< [0] Trusted Protect
+ uint32_t WP7 : 1; //!< [1] Write Protect
+ uint32_t SP7 : 1; //!< [2] Supervisor Protect
+ uint32_t RESERVED0 : 1; //!< [3]
+ uint32_t TP6 : 1; //!< [4] Trusted Protect
+ uint32_t WP6 : 1; //!< [5] Write Protect
+ uint32_t SP6 : 1; //!< [6] Supervisor Protect
+ uint32_t RESERVED1 : 1; //!< [7]
+ uint32_t TP5 : 1; //!< [8] Trusted Protect
+ uint32_t WP5 : 1; //!< [9] Write Protect
+ uint32_t SP5 : 1; //!< [10] Supervisor Protect
+ uint32_t RESERVED2 : 1; //!< [11]
+ uint32_t TP4 : 1; //!< [12] Trusted Protect
+ uint32_t WP4 : 1; //!< [13] Write Protect
+ uint32_t SP4 : 1; //!< [14] Supervisor Protect
+ uint32_t RESERVED3 : 1; //!< [15]
+ uint32_t TP3 : 1; //!< [16] Trusted Protect
+ uint32_t WP3 : 1; //!< [17] Write Protect
+ uint32_t SP3 : 1; //!< [18] Supervisor Protect
+ uint32_t RESERVED4 : 1; //!< [19]
+ uint32_t TP2 : 1; //!< [20] Trusted Protect
+ uint32_t WP2 : 1; //!< [21] Write Protect
+ uint32_t SP2 : 1; //!< [22] Supervisor Protect
+ uint32_t RESERVED5 : 1; //!< [23]
+ uint32_t TP1 : 1; //!< [24] Trusted Protect
+ uint32_t WP1 : 1; //!< [25] Write Protect
+ uint32_t SP1 : 1; //!< [26] Supervisor Protect
+ uint32_t RESERVED6 : 1; //!< [27]
+ uint32_t TP0 : 1; //!< [28] Trusted Protect
+ uint32_t WP0 : 1; //!< [29] Write Protect
+ uint32_t SP0 : 1; //!< [30] Supervisor Protect
+ uint32_t RESERVED7 : 1; //!< [31]
+ } B;
+} hw_aips_pacrk_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRK register
+ */
+//@{
+#define HW_AIPS_PACRK_ADDR(x) (REGS_AIPS_BASE(x) + 0x58U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRK(x) (*(__IO hw_aips_pacrk_t *) HW_AIPS_PACRK_ADDR(x))
+#define HW_AIPS_PACRK_RD(x) (HW_AIPS_PACRK(x).U)
+#define HW_AIPS_PACRK_WR(x, v) (HW_AIPS_PACRK(x).U = (v))
+#define HW_AIPS_PACRK_SET(x, v) (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) | (v)))
+#define HW_AIPS_PACRK_CLR(x, v) (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) & ~(v)))
+#define HW_AIPS_PACRK_TOG(x, v) (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRK bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRK, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRK_TP7 (0U) //!< Bit position for AIPS_PACRK_TP7.
+#define BM_AIPS_PACRK_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRK_TP7.
+#define BS_AIPS_PACRK_TP7 (1U) //!< Bit field size in bits for AIPS_PACRK_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_TP7 field.
+#define BR_AIPS_PACRK_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_TP7.
+#define BF_AIPS_PACRK_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP7), uint32_t) & BM_AIPS_PACRK_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRK_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRK_WP7 (1U) //!< Bit position for AIPS_PACRK_WP7.
+#define BM_AIPS_PACRK_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRK_WP7.
+#define BS_AIPS_PACRK_WP7 (1U) //!< Bit field size in bits for AIPS_PACRK_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_WP7 field.
+#define BR_AIPS_PACRK_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_WP7.
+#define BF_AIPS_PACRK_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP7), uint32_t) & BM_AIPS_PACRK_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRK_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRK_SP7 (2U) //!< Bit position for AIPS_PACRK_SP7.
+#define BM_AIPS_PACRK_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRK_SP7.
+#define BS_AIPS_PACRK_SP7 (1U) //!< Bit field size in bits for AIPS_PACRK_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_SP7 field.
+#define BR_AIPS_PACRK_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_SP7.
+#define BF_AIPS_PACRK_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP7), uint32_t) & BM_AIPS_PACRK_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRK_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRK_TP6 (4U) //!< Bit position for AIPS_PACRK_TP6.
+#define BM_AIPS_PACRK_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRK_TP6.
+#define BS_AIPS_PACRK_TP6 (1U) //!< Bit field size in bits for AIPS_PACRK_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_TP6 field.
+#define BR_AIPS_PACRK_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_TP6.
+#define BF_AIPS_PACRK_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP6), uint32_t) & BM_AIPS_PACRK_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRK_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRK_WP6 (5U) //!< Bit position for AIPS_PACRK_WP6.
+#define BM_AIPS_PACRK_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRK_WP6.
+#define BS_AIPS_PACRK_WP6 (1U) //!< Bit field size in bits for AIPS_PACRK_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_WP6 field.
+#define BR_AIPS_PACRK_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_WP6.
+#define BF_AIPS_PACRK_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP6), uint32_t) & BM_AIPS_PACRK_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRK_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRK_SP6 (6U) //!< Bit position for AIPS_PACRK_SP6.
+#define BM_AIPS_PACRK_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRK_SP6.
+#define BS_AIPS_PACRK_SP6 (1U) //!< Bit field size in bits for AIPS_PACRK_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_SP6 field.
+#define BR_AIPS_PACRK_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_SP6.
+#define BF_AIPS_PACRK_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP6), uint32_t) & BM_AIPS_PACRK_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRK_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRK_TP5 (8U) //!< Bit position for AIPS_PACRK_TP5.
+#define BM_AIPS_PACRK_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRK_TP5.
+#define BS_AIPS_PACRK_TP5 (1U) //!< Bit field size in bits for AIPS_PACRK_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_TP5 field.
+#define BR_AIPS_PACRK_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_TP5.
+#define BF_AIPS_PACRK_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP5), uint32_t) & BM_AIPS_PACRK_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRK_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRK_WP5 (9U) //!< Bit position for AIPS_PACRK_WP5.
+#define BM_AIPS_PACRK_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRK_WP5.
+#define BS_AIPS_PACRK_WP5 (1U) //!< Bit field size in bits for AIPS_PACRK_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_WP5 field.
+#define BR_AIPS_PACRK_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_WP5.
+#define BF_AIPS_PACRK_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP5), uint32_t) & BM_AIPS_PACRK_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRK_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRK_SP5 (10U) //!< Bit position for AIPS_PACRK_SP5.
+#define BM_AIPS_PACRK_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRK_SP5.
+#define BS_AIPS_PACRK_SP5 (1U) //!< Bit field size in bits for AIPS_PACRK_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_SP5 field.
+#define BR_AIPS_PACRK_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_SP5.
+#define BF_AIPS_PACRK_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP5), uint32_t) & BM_AIPS_PACRK_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRK_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRK_TP4 (12U) //!< Bit position for AIPS_PACRK_TP4.
+#define BM_AIPS_PACRK_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRK_TP4.
+#define BS_AIPS_PACRK_TP4 (1U) //!< Bit field size in bits for AIPS_PACRK_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_TP4 field.
+#define BR_AIPS_PACRK_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_TP4.
+#define BF_AIPS_PACRK_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP4), uint32_t) & BM_AIPS_PACRK_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRK_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRK_WP4 (13U) //!< Bit position for AIPS_PACRK_WP4.
+#define BM_AIPS_PACRK_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRK_WP4.
+#define BS_AIPS_PACRK_WP4 (1U) //!< Bit field size in bits for AIPS_PACRK_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_WP4 field.
+#define BR_AIPS_PACRK_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_WP4.
+#define BF_AIPS_PACRK_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP4), uint32_t) & BM_AIPS_PACRK_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRK_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRK_SP4 (14U) //!< Bit position for AIPS_PACRK_SP4.
+#define BM_AIPS_PACRK_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRK_SP4.
+#define BS_AIPS_PACRK_SP4 (1U) //!< Bit field size in bits for AIPS_PACRK_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_SP4 field.
+#define BR_AIPS_PACRK_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_SP4.
+#define BF_AIPS_PACRK_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP4), uint32_t) & BM_AIPS_PACRK_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRK_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRK_TP3 (16U) //!< Bit position for AIPS_PACRK_TP3.
+#define BM_AIPS_PACRK_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRK_TP3.
+#define BS_AIPS_PACRK_TP3 (1U) //!< Bit field size in bits for AIPS_PACRK_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_TP3 field.
+#define BR_AIPS_PACRK_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_TP3.
+#define BF_AIPS_PACRK_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP3), uint32_t) & BM_AIPS_PACRK_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRK_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRK_WP3 (17U) //!< Bit position for AIPS_PACRK_WP3.
+#define BM_AIPS_PACRK_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRK_WP3.
+#define BS_AIPS_PACRK_WP3 (1U) //!< Bit field size in bits for AIPS_PACRK_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_WP3 field.
+#define BR_AIPS_PACRK_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_WP3.
+#define BF_AIPS_PACRK_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP3), uint32_t) & BM_AIPS_PACRK_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRK_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRK_SP3 (18U) //!< Bit position for AIPS_PACRK_SP3.
+#define BM_AIPS_PACRK_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRK_SP3.
+#define BS_AIPS_PACRK_SP3 (1U) //!< Bit field size in bits for AIPS_PACRK_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_SP3 field.
+#define BR_AIPS_PACRK_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_SP3.
+#define BF_AIPS_PACRK_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP3), uint32_t) & BM_AIPS_PACRK_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRK_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRK_TP2 (20U) //!< Bit position for AIPS_PACRK_TP2.
+#define BM_AIPS_PACRK_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRK_TP2.
+#define BS_AIPS_PACRK_TP2 (1U) //!< Bit field size in bits for AIPS_PACRK_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_TP2 field.
+#define BR_AIPS_PACRK_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_TP2.
+#define BF_AIPS_PACRK_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP2), uint32_t) & BM_AIPS_PACRK_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRK_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRK_WP2 (21U) //!< Bit position for AIPS_PACRK_WP2.
+#define BM_AIPS_PACRK_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRK_WP2.
+#define BS_AIPS_PACRK_WP2 (1U) //!< Bit field size in bits for AIPS_PACRK_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_WP2 field.
+#define BR_AIPS_PACRK_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_WP2.
+#define BF_AIPS_PACRK_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP2), uint32_t) & BM_AIPS_PACRK_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRK_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRK_SP2 (22U) //!< Bit position for AIPS_PACRK_SP2.
+#define BM_AIPS_PACRK_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRK_SP2.
+#define BS_AIPS_PACRK_SP2 (1U) //!< Bit field size in bits for AIPS_PACRK_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_SP2 field.
+#define BR_AIPS_PACRK_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_SP2.
+#define BF_AIPS_PACRK_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP2), uint32_t) & BM_AIPS_PACRK_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRK_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRK_TP1 (24U) //!< Bit position for AIPS_PACRK_TP1.
+#define BM_AIPS_PACRK_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRK_TP1.
+#define BS_AIPS_PACRK_TP1 (1U) //!< Bit field size in bits for AIPS_PACRK_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_TP1 field.
+#define BR_AIPS_PACRK_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_TP1.
+#define BF_AIPS_PACRK_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP1), uint32_t) & BM_AIPS_PACRK_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRK_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRK_WP1 (25U) //!< Bit position for AIPS_PACRK_WP1.
+#define BM_AIPS_PACRK_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRK_WP1.
+#define BS_AIPS_PACRK_WP1 (1U) //!< Bit field size in bits for AIPS_PACRK_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_WP1 field.
+#define BR_AIPS_PACRK_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_WP1.
+#define BF_AIPS_PACRK_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP1), uint32_t) & BM_AIPS_PACRK_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRK_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRK_SP1 (26U) //!< Bit position for AIPS_PACRK_SP1.
+#define BM_AIPS_PACRK_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRK_SP1.
+#define BS_AIPS_PACRK_SP1 (1U) //!< Bit field size in bits for AIPS_PACRK_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_SP1 field.
+#define BR_AIPS_PACRK_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_SP1.
+#define BF_AIPS_PACRK_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP1), uint32_t) & BM_AIPS_PACRK_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRK_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRK_TP0 (28U) //!< Bit position for AIPS_PACRK_TP0.
+#define BM_AIPS_PACRK_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRK_TP0.
+#define BS_AIPS_PACRK_TP0 (1U) //!< Bit field size in bits for AIPS_PACRK_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_TP0 field.
+#define BR_AIPS_PACRK_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_TP0.
+#define BF_AIPS_PACRK_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_TP0), uint32_t) & BM_AIPS_PACRK_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRK_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRK_WP0 (29U) //!< Bit position for AIPS_PACRK_WP0.
+#define BM_AIPS_PACRK_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRK_WP0.
+#define BS_AIPS_PACRK_WP0 (1U) //!< Bit field size in bits for AIPS_PACRK_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_WP0 field.
+#define BR_AIPS_PACRK_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_WP0.
+#define BF_AIPS_PACRK_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_WP0), uint32_t) & BM_AIPS_PACRK_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRK_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRK, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRK_SP0 (30U) //!< Bit position for AIPS_PACRK_SP0.
+#define BM_AIPS_PACRK_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRK_SP0.
+#define BS_AIPS_PACRK_SP0 (1U) //!< Bit field size in bits for AIPS_PACRK_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRK_SP0 field.
+#define BR_AIPS_PACRK_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRK_SP0.
+#define BF_AIPS_PACRK_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRK_SP0), uint32_t) & BM_AIPS_PACRK_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRK_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRL - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRL - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+typedef union _hw_aips_pacrl
+{
+ uint32_t U;
+ struct _hw_aips_pacrl_bitfields
+ {
+ uint32_t TP7 : 1; //!< [0] Trusted Protect
+ uint32_t WP7 : 1; //!< [1] Write Protect
+ uint32_t SP7 : 1; //!< [2] Supervisor Protect
+ uint32_t RESERVED0 : 1; //!< [3]
+ uint32_t TP6 : 1; //!< [4] Trusted Protect
+ uint32_t WP6 : 1; //!< [5] Write Protect
+ uint32_t SP6 : 1; //!< [6] Supervisor Protect
+ uint32_t RESERVED1 : 1; //!< [7]
+ uint32_t TP5 : 1; //!< [8] Trusted Protect
+ uint32_t WP5 : 1; //!< [9] Write Protect
+ uint32_t SP5 : 1; //!< [10] Supervisor Protect
+ uint32_t RESERVED2 : 1; //!< [11]
+ uint32_t TP4 : 1; //!< [12] Trusted Protect
+ uint32_t WP4 : 1; //!< [13] Write Protect
+ uint32_t SP4 : 1; //!< [14] Supervisor Protect
+ uint32_t RESERVED3 : 1; //!< [15]
+ uint32_t TP3 : 1; //!< [16] Trusted Protect
+ uint32_t WP3 : 1; //!< [17] Write Protect
+ uint32_t SP3 : 1; //!< [18] Supervisor Protect
+ uint32_t RESERVED4 : 1; //!< [19]
+ uint32_t TP2 : 1; //!< [20] Trusted Protect
+ uint32_t WP2 : 1; //!< [21] Write Protect
+ uint32_t SP2 : 1; //!< [22] Supervisor Protect
+ uint32_t RESERVED5 : 1; //!< [23]
+ uint32_t TP1 : 1; //!< [24] Trusted Protect
+ uint32_t WP1 : 1; //!< [25] Write Protect
+ uint32_t SP1 : 1; //!< [26] Supervisor Protect
+ uint32_t RESERVED6 : 1; //!< [27]
+ uint32_t TP0 : 1; //!< [28] Trusted Protect
+ uint32_t WP0 : 1; //!< [29] Write Protect
+ uint32_t SP0 : 1; //!< [30] Supervisor Protect
+ uint32_t RESERVED7 : 1; //!< [31]
+ } B;
+} hw_aips_pacrl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRL register
+ */
+//@{
+#define HW_AIPS_PACRL_ADDR(x) (REGS_AIPS_BASE(x) + 0x5CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRL(x) (*(__IO hw_aips_pacrl_t *) HW_AIPS_PACRL_ADDR(x))
+#define HW_AIPS_PACRL_RD(x) (HW_AIPS_PACRL(x).U)
+#define HW_AIPS_PACRL_WR(x, v) (HW_AIPS_PACRL(x).U = (v))
+#define HW_AIPS_PACRL_SET(x, v) (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) | (v)))
+#define HW_AIPS_PACRL_CLR(x, v) (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) & ~(v)))
+#define HW_AIPS_PACRL_TOG(x, v) (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRL bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRL, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRL_TP7 (0U) //!< Bit position for AIPS_PACRL_TP7.
+#define BM_AIPS_PACRL_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRL_TP7.
+#define BS_AIPS_PACRL_TP7 (1U) //!< Bit field size in bits for AIPS_PACRL_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_TP7 field.
+#define BR_AIPS_PACRL_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_TP7.
+#define BF_AIPS_PACRL_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP7), uint32_t) & BM_AIPS_PACRL_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRL_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRL_WP7 (1U) //!< Bit position for AIPS_PACRL_WP7.
+#define BM_AIPS_PACRL_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRL_WP7.
+#define BS_AIPS_PACRL_WP7 (1U) //!< Bit field size in bits for AIPS_PACRL_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_WP7 field.
+#define BR_AIPS_PACRL_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_WP7.
+#define BF_AIPS_PACRL_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP7), uint32_t) & BM_AIPS_PACRL_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRL_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRL_SP7 (2U) //!< Bit position for AIPS_PACRL_SP7.
+#define BM_AIPS_PACRL_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRL_SP7.
+#define BS_AIPS_PACRL_SP7 (1U) //!< Bit field size in bits for AIPS_PACRL_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_SP7 field.
+#define BR_AIPS_PACRL_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_SP7.
+#define BF_AIPS_PACRL_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP7), uint32_t) & BM_AIPS_PACRL_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRL_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRL_TP6 (4U) //!< Bit position for AIPS_PACRL_TP6.
+#define BM_AIPS_PACRL_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRL_TP6.
+#define BS_AIPS_PACRL_TP6 (1U) //!< Bit field size in bits for AIPS_PACRL_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_TP6 field.
+#define BR_AIPS_PACRL_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_TP6.
+#define BF_AIPS_PACRL_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP6), uint32_t) & BM_AIPS_PACRL_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRL_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRL_WP6 (5U) //!< Bit position for AIPS_PACRL_WP6.
+#define BM_AIPS_PACRL_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRL_WP6.
+#define BS_AIPS_PACRL_WP6 (1U) //!< Bit field size in bits for AIPS_PACRL_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_WP6 field.
+#define BR_AIPS_PACRL_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_WP6.
+#define BF_AIPS_PACRL_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP6), uint32_t) & BM_AIPS_PACRL_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRL_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRL_SP6 (6U) //!< Bit position for AIPS_PACRL_SP6.
+#define BM_AIPS_PACRL_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRL_SP6.
+#define BS_AIPS_PACRL_SP6 (1U) //!< Bit field size in bits for AIPS_PACRL_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_SP6 field.
+#define BR_AIPS_PACRL_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_SP6.
+#define BF_AIPS_PACRL_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP6), uint32_t) & BM_AIPS_PACRL_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRL_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRL_TP5 (8U) //!< Bit position for AIPS_PACRL_TP5.
+#define BM_AIPS_PACRL_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRL_TP5.
+#define BS_AIPS_PACRL_TP5 (1U) //!< Bit field size in bits for AIPS_PACRL_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_TP5 field.
+#define BR_AIPS_PACRL_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_TP5.
+#define BF_AIPS_PACRL_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP5), uint32_t) & BM_AIPS_PACRL_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRL_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRL_WP5 (9U) //!< Bit position for AIPS_PACRL_WP5.
+#define BM_AIPS_PACRL_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRL_WP5.
+#define BS_AIPS_PACRL_WP5 (1U) //!< Bit field size in bits for AIPS_PACRL_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_WP5 field.
+#define BR_AIPS_PACRL_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_WP5.
+#define BF_AIPS_PACRL_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP5), uint32_t) & BM_AIPS_PACRL_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRL_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRL_SP5 (10U) //!< Bit position for AIPS_PACRL_SP5.
+#define BM_AIPS_PACRL_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRL_SP5.
+#define BS_AIPS_PACRL_SP5 (1U) //!< Bit field size in bits for AIPS_PACRL_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_SP5 field.
+#define BR_AIPS_PACRL_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_SP5.
+#define BF_AIPS_PACRL_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP5), uint32_t) & BM_AIPS_PACRL_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRL_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRL_TP4 (12U) //!< Bit position for AIPS_PACRL_TP4.
+#define BM_AIPS_PACRL_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRL_TP4.
+#define BS_AIPS_PACRL_TP4 (1U) //!< Bit field size in bits for AIPS_PACRL_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_TP4 field.
+#define BR_AIPS_PACRL_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_TP4.
+#define BF_AIPS_PACRL_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP4), uint32_t) & BM_AIPS_PACRL_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRL_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRL_WP4 (13U) //!< Bit position for AIPS_PACRL_WP4.
+#define BM_AIPS_PACRL_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRL_WP4.
+#define BS_AIPS_PACRL_WP4 (1U) //!< Bit field size in bits for AIPS_PACRL_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_WP4 field.
+#define BR_AIPS_PACRL_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_WP4.
+#define BF_AIPS_PACRL_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP4), uint32_t) & BM_AIPS_PACRL_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRL_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRL_SP4 (14U) //!< Bit position for AIPS_PACRL_SP4.
+#define BM_AIPS_PACRL_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRL_SP4.
+#define BS_AIPS_PACRL_SP4 (1U) //!< Bit field size in bits for AIPS_PACRL_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_SP4 field.
+#define BR_AIPS_PACRL_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_SP4.
+#define BF_AIPS_PACRL_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP4), uint32_t) & BM_AIPS_PACRL_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRL_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRL_TP3 (16U) //!< Bit position for AIPS_PACRL_TP3.
+#define BM_AIPS_PACRL_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRL_TP3.
+#define BS_AIPS_PACRL_TP3 (1U) //!< Bit field size in bits for AIPS_PACRL_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_TP3 field.
+#define BR_AIPS_PACRL_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_TP3.
+#define BF_AIPS_PACRL_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP3), uint32_t) & BM_AIPS_PACRL_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRL_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRL_WP3 (17U) //!< Bit position for AIPS_PACRL_WP3.
+#define BM_AIPS_PACRL_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRL_WP3.
+#define BS_AIPS_PACRL_WP3 (1U) //!< Bit field size in bits for AIPS_PACRL_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_WP3 field.
+#define BR_AIPS_PACRL_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_WP3.
+#define BF_AIPS_PACRL_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP3), uint32_t) & BM_AIPS_PACRL_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRL_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRL_SP3 (18U) //!< Bit position for AIPS_PACRL_SP3.
+#define BM_AIPS_PACRL_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRL_SP3.
+#define BS_AIPS_PACRL_SP3 (1U) //!< Bit field size in bits for AIPS_PACRL_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_SP3 field.
+#define BR_AIPS_PACRL_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_SP3.
+#define BF_AIPS_PACRL_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP3), uint32_t) & BM_AIPS_PACRL_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRL_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRL_TP2 (20U) //!< Bit position for AIPS_PACRL_TP2.
+#define BM_AIPS_PACRL_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRL_TP2.
+#define BS_AIPS_PACRL_TP2 (1U) //!< Bit field size in bits for AIPS_PACRL_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_TP2 field.
+#define BR_AIPS_PACRL_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_TP2.
+#define BF_AIPS_PACRL_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP2), uint32_t) & BM_AIPS_PACRL_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRL_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRL_WP2 (21U) //!< Bit position for AIPS_PACRL_WP2.
+#define BM_AIPS_PACRL_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRL_WP2.
+#define BS_AIPS_PACRL_WP2 (1U) //!< Bit field size in bits for AIPS_PACRL_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_WP2 field.
+#define BR_AIPS_PACRL_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_WP2.
+#define BF_AIPS_PACRL_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP2), uint32_t) & BM_AIPS_PACRL_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRL_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRL_SP2 (22U) //!< Bit position for AIPS_PACRL_SP2.
+#define BM_AIPS_PACRL_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRL_SP2.
+#define BS_AIPS_PACRL_SP2 (1U) //!< Bit field size in bits for AIPS_PACRL_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_SP2 field.
+#define BR_AIPS_PACRL_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_SP2.
+#define BF_AIPS_PACRL_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP2), uint32_t) & BM_AIPS_PACRL_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRL_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRL_TP1 (24U) //!< Bit position for AIPS_PACRL_TP1.
+#define BM_AIPS_PACRL_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRL_TP1.
+#define BS_AIPS_PACRL_TP1 (1U) //!< Bit field size in bits for AIPS_PACRL_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_TP1 field.
+#define BR_AIPS_PACRL_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_TP1.
+#define BF_AIPS_PACRL_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP1), uint32_t) & BM_AIPS_PACRL_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRL_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRL_WP1 (25U) //!< Bit position for AIPS_PACRL_WP1.
+#define BM_AIPS_PACRL_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRL_WP1.
+#define BS_AIPS_PACRL_WP1 (1U) //!< Bit field size in bits for AIPS_PACRL_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_WP1 field.
+#define BR_AIPS_PACRL_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_WP1.
+#define BF_AIPS_PACRL_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP1), uint32_t) & BM_AIPS_PACRL_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRL_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRL_SP1 (26U) //!< Bit position for AIPS_PACRL_SP1.
+#define BM_AIPS_PACRL_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRL_SP1.
+#define BS_AIPS_PACRL_SP1 (1U) //!< Bit field size in bits for AIPS_PACRL_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_SP1 field.
+#define BR_AIPS_PACRL_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_SP1.
+#define BF_AIPS_PACRL_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP1), uint32_t) & BM_AIPS_PACRL_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRL_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRL_TP0 (28U) //!< Bit position for AIPS_PACRL_TP0.
+#define BM_AIPS_PACRL_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRL_TP0.
+#define BS_AIPS_PACRL_TP0 (1U) //!< Bit field size in bits for AIPS_PACRL_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_TP0 field.
+#define BR_AIPS_PACRL_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_TP0.
+#define BF_AIPS_PACRL_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_TP0), uint32_t) & BM_AIPS_PACRL_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRL_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRL_WP0 (29U) //!< Bit position for AIPS_PACRL_WP0.
+#define BM_AIPS_PACRL_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRL_WP0.
+#define BS_AIPS_PACRL_WP0 (1U) //!< Bit field size in bits for AIPS_PACRL_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_WP0 field.
+#define BR_AIPS_PACRL_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_WP0.
+#define BF_AIPS_PACRL_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_WP0), uint32_t) & BM_AIPS_PACRL_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRL_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRL, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRL_SP0 (30U) //!< Bit position for AIPS_PACRL_SP0.
+#define BM_AIPS_PACRL_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRL_SP0.
+#define BS_AIPS_PACRL_SP0 (1U) //!< Bit field size in bits for AIPS_PACRL_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRL_SP0 field.
+#define BR_AIPS_PACRL_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRL_SP0.
+#define BF_AIPS_PACRL_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRL_SP0), uint32_t) & BM_AIPS_PACRL_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRL_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRM - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRM - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+typedef union _hw_aips_pacrm
+{
+ uint32_t U;
+ struct _hw_aips_pacrm_bitfields
+ {
+ uint32_t TP7 : 1; //!< [0] Trusted Protect
+ uint32_t WP7 : 1; //!< [1] Write Protect
+ uint32_t SP7 : 1; //!< [2] Supervisor Protect
+ uint32_t RESERVED0 : 1; //!< [3]
+ uint32_t TP6 : 1; //!< [4] Trusted Protect
+ uint32_t WP6 : 1; //!< [5] Write Protect
+ uint32_t SP6 : 1; //!< [6] Supervisor Protect
+ uint32_t RESERVED1 : 1; //!< [7]
+ uint32_t TP5 : 1; //!< [8] Trusted Protect
+ uint32_t WP5 : 1; //!< [9] Write Protect
+ uint32_t SP5 : 1; //!< [10] Supervisor Protect
+ uint32_t RESERVED2 : 1; //!< [11]
+ uint32_t TP4 : 1; //!< [12] Trusted Protect
+ uint32_t WP4 : 1; //!< [13] Write Protect
+ uint32_t SP4 : 1; //!< [14] Supervisor Protect
+ uint32_t RESERVED3 : 1; //!< [15]
+ uint32_t TP3 : 1; //!< [16] Trusted Protect
+ uint32_t WP3 : 1; //!< [17] Write Protect
+ uint32_t SP3 : 1; //!< [18] Supervisor Protect
+ uint32_t RESERVED4 : 1; //!< [19]
+ uint32_t TP2 : 1; //!< [20] Trusted Protect
+ uint32_t WP2 : 1; //!< [21] Write Protect
+ uint32_t SP2 : 1; //!< [22] Supervisor Protect
+ uint32_t RESERVED5 : 1; //!< [23]
+ uint32_t TP1 : 1; //!< [24] Trusted Protect
+ uint32_t WP1 : 1; //!< [25] Write Protect
+ uint32_t SP1 : 1; //!< [26] Supervisor Protect
+ uint32_t RESERVED6 : 1; //!< [27]
+ uint32_t TP0 : 1; //!< [28] Trusted Protect
+ uint32_t WP0 : 1; //!< [29] Write Protect
+ uint32_t SP0 : 1; //!< [30] Supervisor Protect
+ uint32_t RESERVED7 : 1; //!< [31]
+ } B;
+} hw_aips_pacrm_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRM register
+ */
+//@{
+#define HW_AIPS_PACRM_ADDR(x) (REGS_AIPS_BASE(x) + 0x60U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRM(x) (*(__IO hw_aips_pacrm_t *) HW_AIPS_PACRM_ADDR(x))
+#define HW_AIPS_PACRM_RD(x) (HW_AIPS_PACRM(x).U)
+#define HW_AIPS_PACRM_WR(x, v) (HW_AIPS_PACRM(x).U = (v))
+#define HW_AIPS_PACRM_SET(x, v) (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) | (v)))
+#define HW_AIPS_PACRM_CLR(x, v) (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) & ~(v)))
+#define HW_AIPS_PACRM_TOG(x, v) (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRM bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRM, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRM_TP7 (0U) //!< Bit position for AIPS_PACRM_TP7.
+#define BM_AIPS_PACRM_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRM_TP7.
+#define BS_AIPS_PACRM_TP7 (1U) //!< Bit field size in bits for AIPS_PACRM_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_TP7 field.
+#define BR_AIPS_PACRM_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_TP7.
+#define BF_AIPS_PACRM_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP7), uint32_t) & BM_AIPS_PACRM_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRM_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRM_WP7 (1U) //!< Bit position for AIPS_PACRM_WP7.
+#define BM_AIPS_PACRM_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRM_WP7.
+#define BS_AIPS_PACRM_WP7 (1U) //!< Bit field size in bits for AIPS_PACRM_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_WP7 field.
+#define BR_AIPS_PACRM_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_WP7.
+#define BF_AIPS_PACRM_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP7), uint32_t) & BM_AIPS_PACRM_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRM_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRM_SP7 (2U) //!< Bit position for AIPS_PACRM_SP7.
+#define BM_AIPS_PACRM_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRM_SP7.
+#define BS_AIPS_PACRM_SP7 (1U) //!< Bit field size in bits for AIPS_PACRM_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_SP7 field.
+#define BR_AIPS_PACRM_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_SP7.
+#define BF_AIPS_PACRM_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP7), uint32_t) & BM_AIPS_PACRM_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRM_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRM_TP6 (4U) //!< Bit position for AIPS_PACRM_TP6.
+#define BM_AIPS_PACRM_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRM_TP6.
+#define BS_AIPS_PACRM_TP6 (1U) //!< Bit field size in bits for AIPS_PACRM_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_TP6 field.
+#define BR_AIPS_PACRM_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_TP6.
+#define BF_AIPS_PACRM_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP6), uint32_t) & BM_AIPS_PACRM_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRM_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRM_WP6 (5U) //!< Bit position for AIPS_PACRM_WP6.
+#define BM_AIPS_PACRM_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRM_WP6.
+#define BS_AIPS_PACRM_WP6 (1U) //!< Bit field size in bits for AIPS_PACRM_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_WP6 field.
+#define BR_AIPS_PACRM_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_WP6.
+#define BF_AIPS_PACRM_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP6), uint32_t) & BM_AIPS_PACRM_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRM_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRM_SP6 (6U) //!< Bit position for AIPS_PACRM_SP6.
+#define BM_AIPS_PACRM_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRM_SP6.
+#define BS_AIPS_PACRM_SP6 (1U) //!< Bit field size in bits for AIPS_PACRM_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_SP6 field.
+#define BR_AIPS_PACRM_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_SP6.
+#define BF_AIPS_PACRM_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP6), uint32_t) & BM_AIPS_PACRM_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRM_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRM_TP5 (8U) //!< Bit position for AIPS_PACRM_TP5.
+#define BM_AIPS_PACRM_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRM_TP5.
+#define BS_AIPS_PACRM_TP5 (1U) //!< Bit field size in bits for AIPS_PACRM_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_TP5 field.
+#define BR_AIPS_PACRM_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_TP5.
+#define BF_AIPS_PACRM_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP5), uint32_t) & BM_AIPS_PACRM_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRM_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRM_WP5 (9U) //!< Bit position for AIPS_PACRM_WP5.
+#define BM_AIPS_PACRM_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRM_WP5.
+#define BS_AIPS_PACRM_WP5 (1U) //!< Bit field size in bits for AIPS_PACRM_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_WP5 field.
+#define BR_AIPS_PACRM_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_WP5.
+#define BF_AIPS_PACRM_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP5), uint32_t) & BM_AIPS_PACRM_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRM_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRM_SP5 (10U) //!< Bit position for AIPS_PACRM_SP5.
+#define BM_AIPS_PACRM_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRM_SP5.
+#define BS_AIPS_PACRM_SP5 (1U) //!< Bit field size in bits for AIPS_PACRM_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_SP5 field.
+#define BR_AIPS_PACRM_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_SP5.
+#define BF_AIPS_PACRM_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP5), uint32_t) & BM_AIPS_PACRM_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRM_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRM_TP4 (12U) //!< Bit position for AIPS_PACRM_TP4.
+#define BM_AIPS_PACRM_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRM_TP4.
+#define BS_AIPS_PACRM_TP4 (1U) //!< Bit field size in bits for AIPS_PACRM_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_TP4 field.
+#define BR_AIPS_PACRM_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_TP4.
+#define BF_AIPS_PACRM_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP4), uint32_t) & BM_AIPS_PACRM_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRM_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRM_WP4 (13U) //!< Bit position for AIPS_PACRM_WP4.
+#define BM_AIPS_PACRM_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRM_WP4.
+#define BS_AIPS_PACRM_WP4 (1U) //!< Bit field size in bits for AIPS_PACRM_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_WP4 field.
+#define BR_AIPS_PACRM_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_WP4.
+#define BF_AIPS_PACRM_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP4), uint32_t) & BM_AIPS_PACRM_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRM_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRM_SP4 (14U) //!< Bit position for AIPS_PACRM_SP4.
+#define BM_AIPS_PACRM_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRM_SP4.
+#define BS_AIPS_PACRM_SP4 (1U) //!< Bit field size in bits for AIPS_PACRM_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_SP4 field.
+#define BR_AIPS_PACRM_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_SP4.
+#define BF_AIPS_PACRM_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP4), uint32_t) & BM_AIPS_PACRM_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRM_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRM_TP3 (16U) //!< Bit position for AIPS_PACRM_TP3.
+#define BM_AIPS_PACRM_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRM_TP3.
+#define BS_AIPS_PACRM_TP3 (1U) //!< Bit field size in bits for AIPS_PACRM_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_TP3 field.
+#define BR_AIPS_PACRM_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_TP3.
+#define BF_AIPS_PACRM_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP3), uint32_t) & BM_AIPS_PACRM_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRM_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRM_WP3 (17U) //!< Bit position for AIPS_PACRM_WP3.
+#define BM_AIPS_PACRM_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRM_WP3.
+#define BS_AIPS_PACRM_WP3 (1U) //!< Bit field size in bits for AIPS_PACRM_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_WP3 field.
+#define BR_AIPS_PACRM_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_WP3.
+#define BF_AIPS_PACRM_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP3), uint32_t) & BM_AIPS_PACRM_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRM_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRM_SP3 (18U) //!< Bit position for AIPS_PACRM_SP3.
+#define BM_AIPS_PACRM_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRM_SP3.
+#define BS_AIPS_PACRM_SP3 (1U) //!< Bit field size in bits for AIPS_PACRM_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_SP3 field.
+#define BR_AIPS_PACRM_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_SP3.
+#define BF_AIPS_PACRM_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP3), uint32_t) & BM_AIPS_PACRM_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRM_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRM_TP2 (20U) //!< Bit position for AIPS_PACRM_TP2.
+#define BM_AIPS_PACRM_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRM_TP2.
+#define BS_AIPS_PACRM_TP2 (1U) //!< Bit field size in bits for AIPS_PACRM_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_TP2 field.
+#define BR_AIPS_PACRM_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_TP2.
+#define BF_AIPS_PACRM_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP2), uint32_t) & BM_AIPS_PACRM_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRM_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRM_WP2 (21U) //!< Bit position for AIPS_PACRM_WP2.
+#define BM_AIPS_PACRM_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRM_WP2.
+#define BS_AIPS_PACRM_WP2 (1U) //!< Bit field size in bits for AIPS_PACRM_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_WP2 field.
+#define BR_AIPS_PACRM_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_WP2.
+#define BF_AIPS_PACRM_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP2), uint32_t) & BM_AIPS_PACRM_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRM_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRM_SP2 (22U) //!< Bit position for AIPS_PACRM_SP2.
+#define BM_AIPS_PACRM_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRM_SP2.
+#define BS_AIPS_PACRM_SP2 (1U) //!< Bit field size in bits for AIPS_PACRM_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_SP2 field.
+#define BR_AIPS_PACRM_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_SP2.
+#define BF_AIPS_PACRM_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP2), uint32_t) & BM_AIPS_PACRM_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRM_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRM_TP1 (24U) //!< Bit position for AIPS_PACRM_TP1.
+#define BM_AIPS_PACRM_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRM_TP1.
+#define BS_AIPS_PACRM_TP1 (1U) //!< Bit field size in bits for AIPS_PACRM_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_TP1 field.
+#define BR_AIPS_PACRM_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_TP1.
+#define BF_AIPS_PACRM_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP1), uint32_t) & BM_AIPS_PACRM_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRM_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRM_WP1 (25U) //!< Bit position for AIPS_PACRM_WP1.
+#define BM_AIPS_PACRM_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRM_WP1.
+#define BS_AIPS_PACRM_WP1 (1U) //!< Bit field size in bits for AIPS_PACRM_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_WP1 field.
+#define BR_AIPS_PACRM_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_WP1.
+#define BF_AIPS_PACRM_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP1), uint32_t) & BM_AIPS_PACRM_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRM_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRM_SP1 (26U) //!< Bit position for AIPS_PACRM_SP1.
+#define BM_AIPS_PACRM_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRM_SP1.
+#define BS_AIPS_PACRM_SP1 (1U) //!< Bit field size in bits for AIPS_PACRM_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_SP1 field.
+#define BR_AIPS_PACRM_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_SP1.
+#define BF_AIPS_PACRM_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP1), uint32_t) & BM_AIPS_PACRM_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRM_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRM_TP0 (28U) //!< Bit position for AIPS_PACRM_TP0.
+#define BM_AIPS_PACRM_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRM_TP0.
+#define BS_AIPS_PACRM_TP0 (1U) //!< Bit field size in bits for AIPS_PACRM_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_TP0 field.
+#define BR_AIPS_PACRM_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_TP0.
+#define BF_AIPS_PACRM_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_TP0), uint32_t) & BM_AIPS_PACRM_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRM_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRM_WP0 (29U) //!< Bit position for AIPS_PACRM_WP0.
+#define BM_AIPS_PACRM_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRM_WP0.
+#define BS_AIPS_PACRM_WP0 (1U) //!< Bit field size in bits for AIPS_PACRM_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_WP0 field.
+#define BR_AIPS_PACRM_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_WP0.
+#define BF_AIPS_PACRM_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_WP0), uint32_t) & BM_AIPS_PACRM_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRM_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRM, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRM_SP0 (30U) //!< Bit position for AIPS_PACRM_SP0.
+#define BM_AIPS_PACRM_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRM_SP0.
+#define BS_AIPS_PACRM_SP0 (1U) //!< Bit field size in bits for AIPS_PACRM_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRM_SP0 field.
+#define BR_AIPS_PACRM_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRM_SP0.
+#define BF_AIPS_PACRM_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRM_SP0), uint32_t) & BM_AIPS_PACRM_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRM_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRN - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRN - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+typedef union _hw_aips_pacrn
+{
+ uint32_t U;
+ struct _hw_aips_pacrn_bitfields
+ {
+ uint32_t TP7 : 1; //!< [0] Trusted Protect
+ uint32_t WP7 : 1; //!< [1] Write Protect
+ uint32_t SP7 : 1; //!< [2] Supervisor Protect
+ uint32_t RESERVED0 : 1; //!< [3]
+ uint32_t TP6 : 1; //!< [4] Trusted Protect
+ uint32_t WP6 : 1; //!< [5] Write Protect
+ uint32_t SP6 : 1; //!< [6] Supervisor Protect
+ uint32_t RESERVED1 : 1; //!< [7]
+ uint32_t TP5 : 1; //!< [8] Trusted Protect
+ uint32_t WP5 : 1; //!< [9] Write Protect
+ uint32_t SP5 : 1; //!< [10] Supervisor Protect
+ uint32_t RESERVED2 : 1; //!< [11]
+ uint32_t TP4 : 1; //!< [12] Trusted Protect
+ uint32_t WP4 : 1; //!< [13] Write Protect
+ uint32_t SP4 : 1; //!< [14] Supervisor Protect
+ uint32_t RESERVED3 : 1; //!< [15]
+ uint32_t TP3 : 1; //!< [16] Trusted Protect
+ uint32_t WP3 : 1; //!< [17] Write Protect
+ uint32_t SP3 : 1; //!< [18] Supervisor Protect
+ uint32_t RESERVED4 : 1; //!< [19]
+ uint32_t TP2 : 1; //!< [20] Trusted Protect
+ uint32_t WP2 : 1; //!< [21] Write Protect
+ uint32_t SP2 : 1; //!< [22] Supervisor Protect
+ uint32_t RESERVED5 : 1; //!< [23]
+ uint32_t TP1 : 1; //!< [24] Trusted Protect
+ uint32_t WP1 : 1; //!< [25] Write Protect
+ uint32_t SP1 : 1; //!< [26] Supervisor Protect
+ uint32_t RESERVED6 : 1; //!< [27]
+ uint32_t TP0 : 1; //!< [28] Trusted Protect
+ uint32_t WP0 : 1; //!< [29] Write Protect
+ uint32_t SP0 : 1; //!< [30] Supervisor Protect
+ uint32_t RESERVED7 : 1; //!< [31]
+ } B;
+} hw_aips_pacrn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRN register
+ */
+//@{
+#define HW_AIPS_PACRN_ADDR(x) (REGS_AIPS_BASE(x) + 0x64U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRN(x) (*(__IO hw_aips_pacrn_t *) HW_AIPS_PACRN_ADDR(x))
+#define HW_AIPS_PACRN_RD(x) (HW_AIPS_PACRN(x).U)
+#define HW_AIPS_PACRN_WR(x, v) (HW_AIPS_PACRN(x).U = (v))
+#define HW_AIPS_PACRN_SET(x, v) (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) | (v)))
+#define HW_AIPS_PACRN_CLR(x, v) (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) & ~(v)))
+#define HW_AIPS_PACRN_TOG(x, v) (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRN bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRN, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRN_TP7 (0U) //!< Bit position for AIPS_PACRN_TP7.
+#define BM_AIPS_PACRN_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRN_TP7.
+#define BS_AIPS_PACRN_TP7 (1U) //!< Bit field size in bits for AIPS_PACRN_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_TP7 field.
+#define BR_AIPS_PACRN_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_TP7.
+#define BF_AIPS_PACRN_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP7), uint32_t) & BM_AIPS_PACRN_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRN_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRN_WP7 (1U) //!< Bit position for AIPS_PACRN_WP7.
+#define BM_AIPS_PACRN_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRN_WP7.
+#define BS_AIPS_PACRN_WP7 (1U) //!< Bit field size in bits for AIPS_PACRN_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_WP7 field.
+#define BR_AIPS_PACRN_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_WP7.
+#define BF_AIPS_PACRN_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP7), uint32_t) & BM_AIPS_PACRN_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRN_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRN_SP7 (2U) //!< Bit position for AIPS_PACRN_SP7.
+#define BM_AIPS_PACRN_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRN_SP7.
+#define BS_AIPS_PACRN_SP7 (1U) //!< Bit field size in bits for AIPS_PACRN_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_SP7 field.
+#define BR_AIPS_PACRN_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_SP7.
+#define BF_AIPS_PACRN_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP7), uint32_t) & BM_AIPS_PACRN_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRN_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRN_TP6 (4U) //!< Bit position for AIPS_PACRN_TP6.
+#define BM_AIPS_PACRN_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRN_TP6.
+#define BS_AIPS_PACRN_TP6 (1U) //!< Bit field size in bits for AIPS_PACRN_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_TP6 field.
+#define BR_AIPS_PACRN_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_TP6.
+#define BF_AIPS_PACRN_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP6), uint32_t) & BM_AIPS_PACRN_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRN_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRN_WP6 (5U) //!< Bit position for AIPS_PACRN_WP6.
+#define BM_AIPS_PACRN_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRN_WP6.
+#define BS_AIPS_PACRN_WP6 (1U) //!< Bit field size in bits for AIPS_PACRN_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_WP6 field.
+#define BR_AIPS_PACRN_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_WP6.
+#define BF_AIPS_PACRN_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP6), uint32_t) & BM_AIPS_PACRN_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRN_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRN_SP6 (6U) //!< Bit position for AIPS_PACRN_SP6.
+#define BM_AIPS_PACRN_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRN_SP6.
+#define BS_AIPS_PACRN_SP6 (1U) //!< Bit field size in bits for AIPS_PACRN_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_SP6 field.
+#define BR_AIPS_PACRN_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_SP6.
+#define BF_AIPS_PACRN_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP6), uint32_t) & BM_AIPS_PACRN_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRN_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRN_TP5 (8U) //!< Bit position for AIPS_PACRN_TP5.
+#define BM_AIPS_PACRN_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRN_TP5.
+#define BS_AIPS_PACRN_TP5 (1U) //!< Bit field size in bits for AIPS_PACRN_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_TP5 field.
+#define BR_AIPS_PACRN_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_TP5.
+#define BF_AIPS_PACRN_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP5), uint32_t) & BM_AIPS_PACRN_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRN_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRN_WP5 (9U) //!< Bit position for AIPS_PACRN_WP5.
+#define BM_AIPS_PACRN_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRN_WP5.
+#define BS_AIPS_PACRN_WP5 (1U) //!< Bit field size in bits for AIPS_PACRN_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_WP5 field.
+#define BR_AIPS_PACRN_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_WP5.
+#define BF_AIPS_PACRN_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP5), uint32_t) & BM_AIPS_PACRN_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRN_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRN_SP5 (10U) //!< Bit position for AIPS_PACRN_SP5.
+#define BM_AIPS_PACRN_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRN_SP5.
+#define BS_AIPS_PACRN_SP5 (1U) //!< Bit field size in bits for AIPS_PACRN_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_SP5 field.
+#define BR_AIPS_PACRN_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_SP5.
+#define BF_AIPS_PACRN_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP5), uint32_t) & BM_AIPS_PACRN_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRN_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRN_TP4 (12U) //!< Bit position for AIPS_PACRN_TP4.
+#define BM_AIPS_PACRN_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRN_TP4.
+#define BS_AIPS_PACRN_TP4 (1U) //!< Bit field size in bits for AIPS_PACRN_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_TP4 field.
+#define BR_AIPS_PACRN_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_TP4.
+#define BF_AIPS_PACRN_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP4), uint32_t) & BM_AIPS_PACRN_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRN_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRN_WP4 (13U) //!< Bit position for AIPS_PACRN_WP4.
+#define BM_AIPS_PACRN_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRN_WP4.
+#define BS_AIPS_PACRN_WP4 (1U) //!< Bit field size in bits for AIPS_PACRN_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_WP4 field.
+#define BR_AIPS_PACRN_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_WP4.
+#define BF_AIPS_PACRN_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP4), uint32_t) & BM_AIPS_PACRN_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRN_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRN_SP4 (14U) //!< Bit position for AIPS_PACRN_SP4.
+#define BM_AIPS_PACRN_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRN_SP4.
+#define BS_AIPS_PACRN_SP4 (1U) //!< Bit field size in bits for AIPS_PACRN_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_SP4 field.
+#define BR_AIPS_PACRN_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_SP4.
+#define BF_AIPS_PACRN_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP4), uint32_t) & BM_AIPS_PACRN_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRN_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRN_TP3 (16U) //!< Bit position for AIPS_PACRN_TP3.
+#define BM_AIPS_PACRN_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRN_TP3.
+#define BS_AIPS_PACRN_TP3 (1U) //!< Bit field size in bits for AIPS_PACRN_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_TP3 field.
+#define BR_AIPS_PACRN_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_TP3.
+#define BF_AIPS_PACRN_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP3), uint32_t) & BM_AIPS_PACRN_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRN_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRN_WP3 (17U) //!< Bit position for AIPS_PACRN_WP3.
+#define BM_AIPS_PACRN_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRN_WP3.
+#define BS_AIPS_PACRN_WP3 (1U) //!< Bit field size in bits for AIPS_PACRN_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_WP3 field.
+#define BR_AIPS_PACRN_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_WP3.
+#define BF_AIPS_PACRN_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP3), uint32_t) & BM_AIPS_PACRN_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRN_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRN_SP3 (18U) //!< Bit position for AIPS_PACRN_SP3.
+#define BM_AIPS_PACRN_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRN_SP3.
+#define BS_AIPS_PACRN_SP3 (1U) //!< Bit field size in bits for AIPS_PACRN_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_SP3 field.
+#define BR_AIPS_PACRN_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_SP3.
+#define BF_AIPS_PACRN_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP3), uint32_t) & BM_AIPS_PACRN_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRN_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRN_TP2 (20U) //!< Bit position for AIPS_PACRN_TP2.
+#define BM_AIPS_PACRN_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRN_TP2.
+#define BS_AIPS_PACRN_TP2 (1U) //!< Bit field size in bits for AIPS_PACRN_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_TP2 field.
+#define BR_AIPS_PACRN_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_TP2.
+#define BF_AIPS_PACRN_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP2), uint32_t) & BM_AIPS_PACRN_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRN_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRN_WP2 (21U) //!< Bit position for AIPS_PACRN_WP2.
+#define BM_AIPS_PACRN_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRN_WP2.
+#define BS_AIPS_PACRN_WP2 (1U) //!< Bit field size in bits for AIPS_PACRN_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_WP2 field.
+#define BR_AIPS_PACRN_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_WP2.
+#define BF_AIPS_PACRN_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP2), uint32_t) & BM_AIPS_PACRN_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRN_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRN_SP2 (22U) //!< Bit position for AIPS_PACRN_SP2.
+#define BM_AIPS_PACRN_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRN_SP2.
+#define BS_AIPS_PACRN_SP2 (1U) //!< Bit field size in bits for AIPS_PACRN_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_SP2 field.
+#define BR_AIPS_PACRN_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_SP2.
+#define BF_AIPS_PACRN_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP2), uint32_t) & BM_AIPS_PACRN_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRN_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRN_TP1 (24U) //!< Bit position for AIPS_PACRN_TP1.
+#define BM_AIPS_PACRN_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRN_TP1.
+#define BS_AIPS_PACRN_TP1 (1U) //!< Bit field size in bits for AIPS_PACRN_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_TP1 field.
+#define BR_AIPS_PACRN_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_TP1.
+#define BF_AIPS_PACRN_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP1), uint32_t) & BM_AIPS_PACRN_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRN_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRN_WP1 (25U) //!< Bit position for AIPS_PACRN_WP1.
+#define BM_AIPS_PACRN_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRN_WP1.
+#define BS_AIPS_PACRN_WP1 (1U) //!< Bit field size in bits for AIPS_PACRN_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_WP1 field.
+#define BR_AIPS_PACRN_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_WP1.
+#define BF_AIPS_PACRN_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP1), uint32_t) & BM_AIPS_PACRN_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRN_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRN_SP1 (26U) //!< Bit position for AIPS_PACRN_SP1.
+#define BM_AIPS_PACRN_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRN_SP1.
+#define BS_AIPS_PACRN_SP1 (1U) //!< Bit field size in bits for AIPS_PACRN_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_SP1 field.
+#define BR_AIPS_PACRN_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_SP1.
+#define BF_AIPS_PACRN_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP1), uint32_t) & BM_AIPS_PACRN_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRN_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRN_TP0 (28U) //!< Bit position for AIPS_PACRN_TP0.
+#define BM_AIPS_PACRN_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRN_TP0.
+#define BS_AIPS_PACRN_TP0 (1U) //!< Bit field size in bits for AIPS_PACRN_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_TP0 field.
+#define BR_AIPS_PACRN_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_TP0.
+#define BF_AIPS_PACRN_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_TP0), uint32_t) & BM_AIPS_PACRN_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRN_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRN_WP0 (29U) //!< Bit position for AIPS_PACRN_WP0.
+#define BM_AIPS_PACRN_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRN_WP0.
+#define BS_AIPS_PACRN_WP0 (1U) //!< Bit field size in bits for AIPS_PACRN_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_WP0 field.
+#define BR_AIPS_PACRN_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_WP0.
+#define BF_AIPS_PACRN_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_WP0), uint32_t) & BM_AIPS_PACRN_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRN_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRN, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRN_SP0 (30U) //!< Bit position for AIPS_PACRN_SP0.
+#define BM_AIPS_PACRN_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRN_SP0.
+#define BS_AIPS_PACRN_SP0 (1U) //!< Bit field size in bits for AIPS_PACRN_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRN_SP0 field.
+#define BR_AIPS_PACRN_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRN_SP0.
+#define BF_AIPS_PACRN_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRN_SP0), uint32_t) & BM_AIPS_PACRN_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRN_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRO - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRO - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+typedef union _hw_aips_pacro
+{
+ uint32_t U;
+ struct _hw_aips_pacro_bitfields
+ {
+ uint32_t TP7 : 1; //!< [0] Trusted Protect
+ uint32_t WP7 : 1; //!< [1] Write Protect
+ uint32_t SP7 : 1; //!< [2] Supervisor Protect
+ uint32_t RESERVED0 : 1; //!< [3]
+ uint32_t TP6 : 1; //!< [4] Trusted Protect
+ uint32_t WP6 : 1; //!< [5] Write Protect
+ uint32_t SP6 : 1; //!< [6] Supervisor Protect
+ uint32_t RESERVED1 : 1; //!< [7]
+ uint32_t TP5 : 1; //!< [8] Trusted Protect
+ uint32_t WP5 : 1; //!< [9] Write Protect
+ uint32_t SP5 : 1; //!< [10] Supervisor Protect
+ uint32_t RESERVED2 : 1; //!< [11]
+ uint32_t TP4 : 1; //!< [12] Trusted Protect
+ uint32_t WP4 : 1; //!< [13] Write Protect
+ uint32_t SP4 : 1; //!< [14] Supervisor Protect
+ uint32_t RESERVED3 : 1; //!< [15]
+ uint32_t TP3 : 1; //!< [16] Trusted Protect
+ uint32_t WP3 : 1; //!< [17] Write Protect
+ uint32_t SP3 : 1; //!< [18] Supervisor Protect
+ uint32_t RESERVED4 : 1; //!< [19]
+ uint32_t TP2 : 1; //!< [20] Trusted Protect
+ uint32_t WP2 : 1; //!< [21] Write Protect
+ uint32_t SP2 : 1; //!< [22] Supervisor Protect
+ uint32_t RESERVED5 : 1; //!< [23]
+ uint32_t TP1 : 1; //!< [24] Trusted Protect
+ uint32_t WP1 : 1; //!< [25] Write Protect
+ uint32_t SP1 : 1; //!< [26] Supervisor Protect
+ uint32_t RESERVED6 : 1; //!< [27]
+ uint32_t TP0 : 1; //!< [28] Trusted Protect
+ uint32_t WP0 : 1; //!< [29] Write Protect
+ uint32_t SP0 : 1; //!< [30] Supervisor Protect
+ uint32_t RESERVED7 : 1; //!< [31]
+ } B;
+} hw_aips_pacro_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRO register
+ */
+//@{
+#define HW_AIPS_PACRO_ADDR(x) (REGS_AIPS_BASE(x) + 0x68U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRO(x) (*(__IO hw_aips_pacro_t *) HW_AIPS_PACRO_ADDR(x))
+#define HW_AIPS_PACRO_RD(x) (HW_AIPS_PACRO(x).U)
+#define HW_AIPS_PACRO_WR(x, v) (HW_AIPS_PACRO(x).U = (v))
+#define HW_AIPS_PACRO_SET(x, v) (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) | (v)))
+#define HW_AIPS_PACRO_CLR(x, v) (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) & ~(v)))
+#define HW_AIPS_PACRO_TOG(x, v) (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRO bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRO, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRO_TP7 (0U) //!< Bit position for AIPS_PACRO_TP7.
+#define BM_AIPS_PACRO_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRO_TP7.
+#define BS_AIPS_PACRO_TP7 (1U) //!< Bit field size in bits for AIPS_PACRO_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_TP7 field.
+#define BR_AIPS_PACRO_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_TP7.
+#define BF_AIPS_PACRO_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP7), uint32_t) & BM_AIPS_PACRO_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRO_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRO_WP7 (1U) //!< Bit position for AIPS_PACRO_WP7.
+#define BM_AIPS_PACRO_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRO_WP7.
+#define BS_AIPS_PACRO_WP7 (1U) //!< Bit field size in bits for AIPS_PACRO_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_WP7 field.
+#define BR_AIPS_PACRO_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_WP7.
+#define BF_AIPS_PACRO_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP7), uint32_t) & BM_AIPS_PACRO_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRO_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRO_SP7 (2U) //!< Bit position for AIPS_PACRO_SP7.
+#define BM_AIPS_PACRO_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRO_SP7.
+#define BS_AIPS_PACRO_SP7 (1U) //!< Bit field size in bits for AIPS_PACRO_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_SP7 field.
+#define BR_AIPS_PACRO_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_SP7.
+#define BF_AIPS_PACRO_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP7), uint32_t) & BM_AIPS_PACRO_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRO_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRO_TP6 (4U) //!< Bit position for AIPS_PACRO_TP6.
+#define BM_AIPS_PACRO_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRO_TP6.
+#define BS_AIPS_PACRO_TP6 (1U) //!< Bit field size in bits for AIPS_PACRO_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_TP6 field.
+#define BR_AIPS_PACRO_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_TP6.
+#define BF_AIPS_PACRO_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP6), uint32_t) & BM_AIPS_PACRO_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRO_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRO_WP6 (5U) //!< Bit position for AIPS_PACRO_WP6.
+#define BM_AIPS_PACRO_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRO_WP6.
+#define BS_AIPS_PACRO_WP6 (1U) //!< Bit field size in bits for AIPS_PACRO_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_WP6 field.
+#define BR_AIPS_PACRO_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_WP6.
+#define BF_AIPS_PACRO_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP6), uint32_t) & BM_AIPS_PACRO_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRO_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRO_SP6 (6U) //!< Bit position for AIPS_PACRO_SP6.
+#define BM_AIPS_PACRO_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRO_SP6.
+#define BS_AIPS_PACRO_SP6 (1U) //!< Bit field size in bits for AIPS_PACRO_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_SP6 field.
+#define BR_AIPS_PACRO_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_SP6.
+#define BF_AIPS_PACRO_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP6), uint32_t) & BM_AIPS_PACRO_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRO_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRO_TP5 (8U) //!< Bit position for AIPS_PACRO_TP5.
+#define BM_AIPS_PACRO_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRO_TP5.
+#define BS_AIPS_PACRO_TP5 (1U) //!< Bit field size in bits for AIPS_PACRO_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_TP5 field.
+#define BR_AIPS_PACRO_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_TP5.
+#define BF_AIPS_PACRO_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP5), uint32_t) & BM_AIPS_PACRO_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRO_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRO_WP5 (9U) //!< Bit position for AIPS_PACRO_WP5.
+#define BM_AIPS_PACRO_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRO_WP5.
+#define BS_AIPS_PACRO_WP5 (1U) //!< Bit field size in bits for AIPS_PACRO_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_WP5 field.
+#define BR_AIPS_PACRO_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_WP5.
+#define BF_AIPS_PACRO_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP5), uint32_t) & BM_AIPS_PACRO_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRO_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRO_SP5 (10U) //!< Bit position for AIPS_PACRO_SP5.
+#define BM_AIPS_PACRO_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRO_SP5.
+#define BS_AIPS_PACRO_SP5 (1U) //!< Bit field size in bits for AIPS_PACRO_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_SP5 field.
+#define BR_AIPS_PACRO_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_SP5.
+#define BF_AIPS_PACRO_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP5), uint32_t) & BM_AIPS_PACRO_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRO_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRO_TP4 (12U) //!< Bit position for AIPS_PACRO_TP4.
+#define BM_AIPS_PACRO_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRO_TP4.
+#define BS_AIPS_PACRO_TP4 (1U) //!< Bit field size in bits for AIPS_PACRO_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_TP4 field.
+#define BR_AIPS_PACRO_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_TP4.
+#define BF_AIPS_PACRO_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP4), uint32_t) & BM_AIPS_PACRO_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRO_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRO_WP4 (13U) //!< Bit position for AIPS_PACRO_WP4.
+#define BM_AIPS_PACRO_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRO_WP4.
+#define BS_AIPS_PACRO_WP4 (1U) //!< Bit field size in bits for AIPS_PACRO_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_WP4 field.
+#define BR_AIPS_PACRO_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_WP4.
+#define BF_AIPS_PACRO_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP4), uint32_t) & BM_AIPS_PACRO_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRO_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRO_SP4 (14U) //!< Bit position for AIPS_PACRO_SP4.
+#define BM_AIPS_PACRO_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRO_SP4.
+#define BS_AIPS_PACRO_SP4 (1U) //!< Bit field size in bits for AIPS_PACRO_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_SP4 field.
+#define BR_AIPS_PACRO_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_SP4.
+#define BF_AIPS_PACRO_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP4), uint32_t) & BM_AIPS_PACRO_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRO_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRO_TP3 (16U) //!< Bit position for AIPS_PACRO_TP3.
+#define BM_AIPS_PACRO_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRO_TP3.
+#define BS_AIPS_PACRO_TP3 (1U) //!< Bit field size in bits for AIPS_PACRO_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_TP3 field.
+#define BR_AIPS_PACRO_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_TP3.
+#define BF_AIPS_PACRO_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP3), uint32_t) & BM_AIPS_PACRO_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRO_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRO_WP3 (17U) //!< Bit position for AIPS_PACRO_WP3.
+#define BM_AIPS_PACRO_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRO_WP3.
+#define BS_AIPS_PACRO_WP3 (1U) //!< Bit field size in bits for AIPS_PACRO_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_WP3 field.
+#define BR_AIPS_PACRO_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_WP3.
+#define BF_AIPS_PACRO_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP3), uint32_t) & BM_AIPS_PACRO_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRO_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRO_SP3 (18U) //!< Bit position for AIPS_PACRO_SP3.
+#define BM_AIPS_PACRO_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRO_SP3.
+#define BS_AIPS_PACRO_SP3 (1U) //!< Bit field size in bits for AIPS_PACRO_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_SP3 field.
+#define BR_AIPS_PACRO_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_SP3.
+#define BF_AIPS_PACRO_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP3), uint32_t) & BM_AIPS_PACRO_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRO_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRO_TP2 (20U) //!< Bit position for AIPS_PACRO_TP2.
+#define BM_AIPS_PACRO_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRO_TP2.
+#define BS_AIPS_PACRO_TP2 (1U) //!< Bit field size in bits for AIPS_PACRO_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_TP2 field.
+#define BR_AIPS_PACRO_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_TP2.
+#define BF_AIPS_PACRO_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP2), uint32_t) & BM_AIPS_PACRO_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRO_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRO_WP2 (21U) //!< Bit position for AIPS_PACRO_WP2.
+#define BM_AIPS_PACRO_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRO_WP2.
+#define BS_AIPS_PACRO_WP2 (1U) //!< Bit field size in bits for AIPS_PACRO_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_WP2 field.
+#define BR_AIPS_PACRO_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_WP2.
+#define BF_AIPS_PACRO_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP2), uint32_t) & BM_AIPS_PACRO_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRO_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRO_SP2 (22U) //!< Bit position for AIPS_PACRO_SP2.
+#define BM_AIPS_PACRO_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRO_SP2.
+#define BS_AIPS_PACRO_SP2 (1U) //!< Bit field size in bits for AIPS_PACRO_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_SP2 field.
+#define BR_AIPS_PACRO_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_SP2.
+#define BF_AIPS_PACRO_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP2), uint32_t) & BM_AIPS_PACRO_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRO_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRO_TP1 (24U) //!< Bit position for AIPS_PACRO_TP1.
+#define BM_AIPS_PACRO_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRO_TP1.
+#define BS_AIPS_PACRO_TP1 (1U) //!< Bit field size in bits for AIPS_PACRO_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_TP1 field.
+#define BR_AIPS_PACRO_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_TP1.
+#define BF_AIPS_PACRO_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP1), uint32_t) & BM_AIPS_PACRO_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRO_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRO_WP1 (25U) //!< Bit position for AIPS_PACRO_WP1.
+#define BM_AIPS_PACRO_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRO_WP1.
+#define BS_AIPS_PACRO_WP1 (1U) //!< Bit field size in bits for AIPS_PACRO_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_WP1 field.
+#define BR_AIPS_PACRO_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_WP1.
+#define BF_AIPS_PACRO_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP1), uint32_t) & BM_AIPS_PACRO_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRO_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRO_SP1 (26U) //!< Bit position for AIPS_PACRO_SP1.
+#define BM_AIPS_PACRO_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRO_SP1.
+#define BS_AIPS_PACRO_SP1 (1U) //!< Bit field size in bits for AIPS_PACRO_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_SP1 field.
+#define BR_AIPS_PACRO_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_SP1.
+#define BF_AIPS_PACRO_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP1), uint32_t) & BM_AIPS_PACRO_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRO_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRO_TP0 (28U) //!< Bit position for AIPS_PACRO_TP0.
+#define BM_AIPS_PACRO_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRO_TP0.
+#define BS_AIPS_PACRO_TP0 (1U) //!< Bit field size in bits for AIPS_PACRO_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_TP0 field.
+#define BR_AIPS_PACRO_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_TP0.
+#define BF_AIPS_PACRO_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_TP0), uint32_t) & BM_AIPS_PACRO_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRO_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRO_WP0 (29U) //!< Bit position for AIPS_PACRO_WP0.
+#define BM_AIPS_PACRO_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRO_WP0.
+#define BS_AIPS_PACRO_WP0 (1U) //!< Bit field size in bits for AIPS_PACRO_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_WP0 field.
+#define BR_AIPS_PACRO_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_WP0.
+#define BF_AIPS_PACRO_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_WP0), uint32_t) & BM_AIPS_PACRO_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRO_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRO, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRO_SP0 (30U) //!< Bit position for AIPS_PACRO_SP0.
+#define BM_AIPS_PACRO_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRO_SP0.
+#define BS_AIPS_PACRO_SP0 (1U) //!< Bit field size in bits for AIPS_PACRO_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRO_SP0 field.
+#define BR_AIPS_PACRO_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRO_SP0.
+#define BF_AIPS_PACRO_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRO_SP0), uint32_t) & BM_AIPS_PACRO_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRO_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRP - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRP - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+typedef union _hw_aips_pacrp
+{
+ uint32_t U;
+ struct _hw_aips_pacrp_bitfields
+ {
+ uint32_t TP7 : 1; //!< [0] Trusted Protect
+ uint32_t WP7 : 1; //!< [1] Write Protect
+ uint32_t SP7 : 1; //!< [2] Supervisor Protect
+ uint32_t RESERVED0 : 1; //!< [3]
+ uint32_t TP6 : 1; //!< [4] Trusted Protect
+ uint32_t WP6 : 1; //!< [5] Write Protect
+ uint32_t SP6 : 1; //!< [6] Supervisor Protect
+ uint32_t RESERVED1 : 1; //!< [7]
+ uint32_t TP5 : 1; //!< [8] Trusted Protect
+ uint32_t WP5 : 1; //!< [9] Write Protect
+ uint32_t SP5 : 1; //!< [10] Supervisor Protect
+ uint32_t RESERVED2 : 1; //!< [11]
+ uint32_t TP4 : 1; //!< [12] Trusted Protect
+ uint32_t WP4 : 1; //!< [13] Write Protect
+ uint32_t SP4 : 1; //!< [14] Supervisor Protect
+ uint32_t RESERVED3 : 1; //!< [15]
+ uint32_t TP3 : 1; //!< [16] Trusted Protect
+ uint32_t WP3 : 1; //!< [17] Write Protect
+ uint32_t SP3 : 1; //!< [18] Supervisor Protect
+ uint32_t RESERVED4 : 1; //!< [19]
+ uint32_t TP2 : 1; //!< [20] Trusted Protect
+ uint32_t WP2 : 1; //!< [21] Write Protect
+ uint32_t SP2 : 1; //!< [22] Supervisor Protect
+ uint32_t RESERVED5 : 1; //!< [23]
+ uint32_t TP1 : 1; //!< [24] Trusted Protect
+ uint32_t WP1 : 1; //!< [25] Write Protect
+ uint32_t SP1 : 1; //!< [26] Supervisor Protect
+ uint32_t RESERVED6 : 1; //!< [27]
+ uint32_t TP0 : 1; //!< [28] Trusted Protect
+ uint32_t WP0 : 1; //!< [29] Write Protect
+ uint32_t SP0 : 1; //!< [30] Supervisor Protect
+ uint32_t RESERVED7 : 1; //!< [31]
+ } B;
+} hw_aips_pacrp_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRP register
+ */
+//@{
+#define HW_AIPS_PACRP_ADDR(x) (REGS_AIPS_BASE(x) + 0x6CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRP(x) (*(__IO hw_aips_pacrp_t *) HW_AIPS_PACRP_ADDR(x))
+#define HW_AIPS_PACRP_RD(x) (HW_AIPS_PACRP(x).U)
+#define HW_AIPS_PACRP_WR(x, v) (HW_AIPS_PACRP(x).U = (v))
+#define HW_AIPS_PACRP_SET(x, v) (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) | (v)))
+#define HW_AIPS_PACRP_CLR(x, v) (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) & ~(v)))
+#define HW_AIPS_PACRP_TOG(x, v) (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRP bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRP, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRP_TP7 (0U) //!< Bit position for AIPS_PACRP_TP7.
+#define BM_AIPS_PACRP_TP7 (0x00000001U) //!< Bit mask for AIPS_PACRP_TP7.
+#define BS_AIPS_PACRP_TP7 (1U) //!< Bit field size in bits for AIPS_PACRP_TP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_TP7 field.
+#define BR_AIPS_PACRP_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_TP7.
+#define BF_AIPS_PACRP_TP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP7), uint32_t) & BM_AIPS_PACRP_TP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP7 field to a new value.
+#define BW_AIPS_PACRP_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRP_WP7 (1U) //!< Bit position for AIPS_PACRP_WP7.
+#define BM_AIPS_PACRP_WP7 (0x00000002U) //!< Bit mask for AIPS_PACRP_WP7.
+#define BS_AIPS_PACRP_WP7 (1U) //!< Bit field size in bits for AIPS_PACRP_WP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_WP7 field.
+#define BR_AIPS_PACRP_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_WP7.
+#define BF_AIPS_PACRP_WP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP7), uint32_t) & BM_AIPS_PACRP_WP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP7 field to a new value.
+#define BW_AIPS_PACRP_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRP_SP7 (2U) //!< Bit position for AIPS_PACRP_SP7.
+#define BM_AIPS_PACRP_SP7 (0x00000004U) //!< Bit mask for AIPS_PACRP_SP7.
+#define BS_AIPS_PACRP_SP7 (1U) //!< Bit field size in bits for AIPS_PACRP_SP7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_SP7 field.
+#define BR_AIPS_PACRP_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP7))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_SP7.
+#define BF_AIPS_PACRP_SP7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP7), uint32_t) & BM_AIPS_PACRP_SP7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP7 field to a new value.
+#define BW_AIPS_PACRP_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRP_TP6 (4U) //!< Bit position for AIPS_PACRP_TP6.
+#define BM_AIPS_PACRP_TP6 (0x00000010U) //!< Bit mask for AIPS_PACRP_TP6.
+#define BS_AIPS_PACRP_TP6 (1U) //!< Bit field size in bits for AIPS_PACRP_TP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_TP6 field.
+#define BR_AIPS_PACRP_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_TP6.
+#define BF_AIPS_PACRP_TP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP6), uint32_t) & BM_AIPS_PACRP_TP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP6 field to a new value.
+#define BW_AIPS_PACRP_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRP_WP6 (5U) //!< Bit position for AIPS_PACRP_WP6.
+#define BM_AIPS_PACRP_WP6 (0x00000020U) //!< Bit mask for AIPS_PACRP_WP6.
+#define BS_AIPS_PACRP_WP6 (1U) //!< Bit field size in bits for AIPS_PACRP_WP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_WP6 field.
+#define BR_AIPS_PACRP_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_WP6.
+#define BF_AIPS_PACRP_WP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP6), uint32_t) & BM_AIPS_PACRP_WP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP6 field to a new value.
+#define BW_AIPS_PACRP_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRP_SP6 (6U) //!< Bit position for AIPS_PACRP_SP6.
+#define BM_AIPS_PACRP_SP6 (0x00000040U) //!< Bit mask for AIPS_PACRP_SP6.
+#define BS_AIPS_PACRP_SP6 (1U) //!< Bit field size in bits for AIPS_PACRP_SP6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_SP6 field.
+#define BR_AIPS_PACRP_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP6))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_SP6.
+#define BF_AIPS_PACRP_SP6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP6), uint32_t) & BM_AIPS_PACRP_SP6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP6 field to a new value.
+#define BW_AIPS_PACRP_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRP_TP5 (8U) //!< Bit position for AIPS_PACRP_TP5.
+#define BM_AIPS_PACRP_TP5 (0x00000100U) //!< Bit mask for AIPS_PACRP_TP5.
+#define BS_AIPS_PACRP_TP5 (1U) //!< Bit field size in bits for AIPS_PACRP_TP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_TP5 field.
+#define BR_AIPS_PACRP_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_TP5.
+#define BF_AIPS_PACRP_TP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP5), uint32_t) & BM_AIPS_PACRP_TP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP5 field to a new value.
+#define BW_AIPS_PACRP_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRP_WP5 (9U) //!< Bit position for AIPS_PACRP_WP5.
+#define BM_AIPS_PACRP_WP5 (0x00000200U) //!< Bit mask for AIPS_PACRP_WP5.
+#define BS_AIPS_PACRP_WP5 (1U) //!< Bit field size in bits for AIPS_PACRP_WP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_WP5 field.
+#define BR_AIPS_PACRP_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_WP5.
+#define BF_AIPS_PACRP_WP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP5), uint32_t) & BM_AIPS_PACRP_WP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP5 field to a new value.
+#define BW_AIPS_PACRP_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRP_SP5 (10U) //!< Bit position for AIPS_PACRP_SP5.
+#define BM_AIPS_PACRP_SP5 (0x00000400U) //!< Bit mask for AIPS_PACRP_SP5.
+#define BS_AIPS_PACRP_SP5 (1U) //!< Bit field size in bits for AIPS_PACRP_SP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_SP5 field.
+#define BR_AIPS_PACRP_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP5))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_SP5.
+#define BF_AIPS_PACRP_SP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP5), uint32_t) & BM_AIPS_PACRP_SP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP5 field to a new value.
+#define BW_AIPS_PACRP_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRP_TP4 (12U) //!< Bit position for AIPS_PACRP_TP4.
+#define BM_AIPS_PACRP_TP4 (0x00001000U) //!< Bit mask for AIPS_PACRP_TP4.
+#define BS_AIPS_PACRP_TP4 (1U) //!< Bit field size in bits for AIPS_PACRP_TP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_TP4 field.
+#define BR_AIPS_PACRP_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_TP4.
+#define BF_AIPS_PACRP_TP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP4), uint32_t) & BM_AIPS_PACRP_TP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP4 field to a new value.
+#define BW_AIPS_PACRP_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRP_WP4 (13U) //!< Bit position for AIPS_PACRP_WP4.
+#define BM_AIPS_PACRP_WP4 (0x00002000U) //!< Bit mask for AIPS_PACRP_WP4.
+#define BS_AIPS_PACRP_WP4 (1U) //!< Bit field size in bits for AIPS_PACRP_WP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_WP4 field.
+#define BR_AIPS_PACRP_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_WP4.
+#define BF_AIPS_PACRP_WP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP4), uint32_t) & BM_AIPS_PACRP_WP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP4 field to a new value.
+#define BW_AIPS_PACRP_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRP_SP4 (14U) //!< Bit position for AIPS_PACRP_SP4.
+#define BM_AIPS_PACRP_SP4 (0x00004000U) //!< Bit mask for AIPS_PACRP_SP4.
+#define BS_AIPS_PACRP_SP4 (1U) //!< Bit field size in bits for AIPS_PACRP_SP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_SP4 field.
+#define BR_AIPS_PACRP_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP4))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_SP4.
+#define BF_AIPS_PACRP_SP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP4), uint32_t) & BM_AIPS_PACRP_SP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP4 field to a new value.
+#define BW_AIPS_PACRP_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRP_TP3 (16U) //!< Bit position for AIPS_PACRP_TP3.
+#define BM_AIPS_PACRP_TP3 (0x00010000U) //!< Bit mask for AIPS_PACRP_TP3.
+#define BS_AIPS_PACRP_TP3 (1U) //!< Bit field size in bits for AIPS_PACRP_TP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_TP3 field.
+#define BR_AIPS_PACRP_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_TP3.
+#define BF_AIPS_PACRP_TP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP3), uint32_t) & BM_AIPS_PACRP_TP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP3 field to a new value.
+#define BW_AIPS_PACRP_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRP_WP3 (17U) //!< Bit position for AIPS_PACRP_WP3.
+#define BM_AIPS_PACRP_WP3 (0x00020000U) //!< Bit mask for AIPS_PACRP_WP3.
+#define BS_AIPS_PACRP_WP3 (1U) //!< Bit field size in bits for AIPS_PACRP_WP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_WP3 field.
+#define BR_AIPS_PACRP_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_WP3.
+#define BF_AIPS_PACRP_WP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP3), uint32_t) & BM_AIPS_PACRP_WP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP3 field to a new value.
+#define BW_AIPS_PACRP_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRP_SP3 (18U) //!< Bit position for AIPS_PACRP_SP3.
+#define BM_AIPS_PACRP_SP3 (0x00040000U) //!< Bit mask for AIPS_PACRP_SP3.
+#define BS_AIPS_PACRP_SP3 (1U) //!< Bit field size in bits for AIPS_PACRP_SP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_SP3 field.
+#define BR_AIPS_PACRP_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP3))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_SP3.
+#define BF_AIPS_PACRP_SP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP3), uint32_t) & BM_AIPS_PACRP_SP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP3 field to a new value.
+#define BW_AIPS_PACRP_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRP_TP2 (20U) //!< Bit position for AIPS_PACRP_TP2.
+#define BM_AIPS_PACRP_TP2 (0x00100000U) //!< Bit mask for AIPS_PACRP_TP2.
+#define BS_AIPS_PACRP_TP2 (1U) //!< Bit field size in bits for AIPS_PACRP_TP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_TP2 field.
+#define BR_AIPS_PACRP_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_TP2.
+#define BF_AIPS_PACRP_TP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP2), uint32_t) & BM_AIPS_PACRP_TP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP2 field to a new value.
+#define BW_AIPS_PACRP_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRP_WP2 (21U) //!< Bit position for AIPS_PACRP_WP2.
+#define BM_AIPS_PACRP_WP2 (0x00200000U) //!< Bit mask for AIPS_PACRP_WP2.
+#define BS_AIPS_PACRP_WP2 (1U) //!< Bit field size in bits for AIPS_PACRP_WP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_WP2 field.
+#define BR_AIPS_PACRP_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_WP2.
+#define BF_AIPS_PACRP_WP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP2), uint32_t) & BM_AIPS_PACRP_WP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP2 field to a new value.
+#define BW_AIPS_PACRP_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRP_SP2 (22U) //!< Bit position for AIPS_PACRP_SP2.
+#define BM_AIPS_PACRP_SP2 (0x00400000U) //!< Bit mask for AIPS_PACRP_SP2.
+#define BS_AIPS_PACRP_SP2 (1U) //!< Bit field size in bits for AIPS_PACRP_SP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_SP2 field.
+#define BR_AIPS_PACRP_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP2))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_SP2.
+#define BF_AIPS_PACRP_SP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP2), uint32_t) & BM_AIPS_PACRP_SP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP2 field to a new value.
+#define BW_AIPS_PACRP_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRP_TP1 (24U) //!< Bit position for AIPS_PACRP_TP1.
+#define BM_AIPS_PACRP_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRP_TP1.
+#define BS_AIPS_PACRP_TP1 (1U) //!< Bit field size in bits for AIPS_PACRP_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_TP1 field.
+#define BR_AIPS_PACRP_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_TP1.
+#define BF_AIPS_PACRP_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP1), uint32_t) & BM_AIPS_PACRP_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRP_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRP_WP1 (25U) //!< Bit position for AIPS_PACRP_WP1.
+#define BM_AIPS_PACRP_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRP_WP1.
+#define BS_AIPS_PACRP_WP1 (1U) //!< Bit field size in bits for AIPS_PACRP_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_WP1 field.
+#define BR_AIPS_PACRP_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_WP1.
+#define BF_AIPS_PACRP_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP1), uint32_t) & BM_AIPS_PACRP_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRP_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRP_SP1 (26U) //!< Bit position for AIPS_PACRP_SP1.
+#define BM_AIPS_PACRP_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRP_SP1.
+#define BS_AIPS_PACRP_SP1 (1U) //!< Bit field size in bits for AIPS_PACRP_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_SP1 field.
+#define BR_AIPS_PACRP_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_SP1.
+#define BF_AIPS_PACRP_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP1), uint32_t) & BM_AIPS_PACRP_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRP_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRP_TP0 (28U) //!< Bit position for AIPS_PACRP_TP0.
+#define BM_AIPS_PACRP_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRP_TP0.
+#define BS_AIPS_PACRP_TP0 (1U) //!< Bit field size in bits for AIPS_PACRP_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_TP0 field.
+#define BR_AIPS_PACRP_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_TP0.
+#define BF_AIPS_PACRP_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_TP0), uint32_t) & BM_AIPS_PACRP_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRP_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRP_WP0 (29U) //!< Bit position for AIPS_PACRP_WP0.
+#define BM_AIPS_PACRP_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRP_WP0.
+#define BS_AIPS_PACRP_WP0 (1U) //!< Bit field size in bits for AIPS_PACRP_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_WP0 field.
+#define BR_AIPS_PACRP_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_WP0.
+#define BF_AIPS_PACRP_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_WP0), uint32_t) & BM_AIPS_PACRP_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRP_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRP, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRP_SP0 (30U) //!< Bit position for AIPS_PACRP_SP0.
+#define BM_AIPS_PACRP_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRP_SP0.
+#define BS_AIPS_PACRP_SP0 (1U) //!< Bit field size in bits for AIPS_PACRP_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRP_SP0 field.
+#define BR_AIPS_PACRP_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRP_SP0.
+#define BF_AIPS_PACRP_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRP_SP0), uint32_t) & BM_AIPS_PACRP_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRP_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AIPS_PACRU - Peripheral Access Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AIPS_PACRU - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44000000U
+ *
+ * PACRU defines the access levels for the two global spaces.
+ */
+typedef union _hw_aips_pacru
+{
+ uint32_t U;
+ struct _hw_aips_pacru_bitfields
+ {
+ uint32_t RESERVED0 : 24; //!< [23:0]
+ uint32_t TP1 : 1; //!< [24] Trusted Protect
+ uint32_t WP1 : 1; //!< [25] Write Protect
+ uint32_t SP1 : 1; //!< [26] Supervisor Protect
+ uint32_t RESERVED1 : 1; //!< [27]
+ uint32_t TP0 : 1; //!< [28] Trusted Protect
+ uint32_t WP0 : 1; //!< [29] Write Protect
+ uint32_t SP0 : 1; //!< [30] Supervisor Protect
+ uint32_t RESERVED2 : 1; //!< [31]
+ } B;
+} hw_aips_pacru_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AIPS_PACRU register
+ */
+//@{
+#define HW_AIPS_PACRU_ADDR(x) (REGS_AIPS_BASE(x) + 0x80U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AIPS_PACRU(x) (*(__IO hw_aips_pacru_t *) HW_AIPS_PACRU_ADDR(x))
+#define HW_AIPS_PACRU_RD(x) (HW_AIPS_PACRU(x).U)
+#define HW_AIPS_PACRU_WR(x, v) (HW_AIPS_PACRU(x).U = (v))
+#define HW_AIPS_PACRU_SET(x, v) (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) | (v)))
+#define HW_AIPS_PACRU_CLR(x, v) (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) & ~(v)))
+#define HW_AIPS_PACRU_TOG(x, v) (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AIPS_PACRU bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRU, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRU_TP1 (24U) //!< Bit position for AIPS_PACRU_TP1.
+#define BM_AIPS_PACRU_TP1 (0x01000000U) //!< Bit mask for AIPS_PACRU_TP1.
+#define BS_AIPS_PACRU_TP1 (1U) //!< Bit field size in bits for AIPS_PACRU_TP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRU_TP1 field.
+#define BR_AIPS_PACRU_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRU_TP1.
+#define BF_AIPS_PACRU_TP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_TP1), uint32_t) & BM_AIPS_PACRU_TP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP1 field to a new value.
+#define BW_AIPS_PACRU_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRU, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRU_WP1 (25U) //!< Bit position for AIPS_PACRU_WP1.
+#define BM_AIPS_PACRU_WP1 (0x02000000U) //!< Bit mask for AIPS_PACRU_WP1.
+#define BS_AIPS_PACRU_WP1 (1U) //!< Bit field size in bits for AIPS_PACRU_WP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRU_WP1 field.
+#define BR_AIPS_PACRU_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRU_WP1.
+#define BF_AIPS_PACRU_WP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_WP1), uint32_t) & BM_AIPS_PACRU_WP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP1 field to a new value.
+#define BW_AIPS_PACRU_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRU, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRU_SP1 (26U) //!< Bit position for AIPS_PACRU_SP1.
+#define BM_AIPS_PACRU_SP1 (0x04000000U) //!< Bit mask for AIPS_PACRU_SP1.
+#define BS_AIPS_PACRU_SP1 (1U) //!< Bit field size in bits for AIPS_PACRU_SP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRU_SP1 field.
+#define BR_AIPS_PACRU_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP1))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRU_SP1.
+#define BF_AIPS_PACRU_SP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_SP1), uint32_t) & BM_AIPS_PACRU_SP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP1 field to a new value.
+#define BW_AIPS_PACRU_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRU, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - Accesses from an untrusted master are allowed.
+ * - 1 - Accesses from an untrusted master are not allowed.
+ */
+//@{
+#define BP_AIPS_PACRU_TP0 (28U) //!< Bit position for AIPS_PACRU_TP0.
+#define BM_AIPS_PACRU_TP0 (0x10000000U) //!< Bit mask for AIPS_PACRU_TP0.
+#define BS_AIPS_PACRU_TP0 (1U) //!< Bit field size in bits for AIPS_PACRU_TP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRU_TP0 field.
+#define BR_AIPS_PACRU_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRU_TP0.
+#define BF_AIPS_PACRU_TP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_TP0), uint32_t) & BM_AIPS_PACRU_TP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TP0 field to a new value.
+#define BW_AIPS_PACRU_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRU, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0 - This peripheral allows write accesses.
+ * - 1 - This peripheral is write protected.
+ */
+//@{
+#define BP_AIPS_PACRU_WP0 (29U) //!< Bit position for AIPS_PACRU_WP0.
+#define BM_AIPS_PACRU_WP0 (0x20000000U) //!< Bit mask for AIPS_PACRU_WP0.
+#define BS_AIPS_PACRU_WP0 (1U) //!< Bit field size in bits for AIPS_PACRU_WP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRU_WP0 field.
+#define BR_AIPS_PACRU_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRU_WP0.
+#define BF_AIPS_PACRU_WP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_WP0), uint32_t) & BM_AIPS_PACRU_WP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP0 field to a new value.
+#define BW_AIPS_PACRU_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AIPS_PACRU, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0 - This peripheral does not require supervisor privilege level for
+ * accesses.
+ * - 1 - This peripheral requires supervisor privilege level for accesses.
+ */
+//@{
+#define BP_AIPS_PACRU_SP0 (30U) //!< Bit position for AIPS_PACRU_SP0.
+#define BM_AIPS_PACRU_SP0 (0x40000000U) //!< Bit mask for AIPS_PACRU_SP0.
+#define BS_AIPS_PACRU_SP0 (1U) //!< Bit field size in bits for AIPS_PACRU_SP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AIPS_PACRU_SP0 field.
+#define BR_AIPS_PACRU_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP0))
+#endif
+
+//! @brief Format value for bitfield AIPS_PACRU_SP0.
+#define BF_AIPS_PACRU_SP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AIPS_PACRU_SP0), uint32_t) & BM_AIPS_PACRU_SP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SP0 field to a new value.
+#define BW_AIPS_PACRU_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_aips_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All AIPS module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_aips
+{
+ __IO hw_aips_mpra_t MPRA; //!< [0x0] Master Privilege Register A
+ uint8_t _reserved0[28];
+ __IO hw_aips_pacra_t PACRA; //!< [0x20] Peripheral Access Control Register
+ __IO hw_aips_pacrb_t PACRB; //!< [0x24] Peripheral Access Control Register
+ __IO hw_aips_pacrc_t PACRC; //!< [0x28] Peripheral Access Control Register
+ __IO hw_aips_pacrd_t PACRD; //!< [0x2C] Peripheral Access Control Register
+ uint8_t _reserved1[16];
+ __IO hw_aips_pacre_t PACRE; //!< [0x40] Peripheral Access Control Register
+ __IO hw_aips_pacrf_t PACRF; //!< [0x44] Peripheral Access Control Register
+ __IO hw_aips_pacrg_t PACRG; //!< [0x48] Peripheral Access Control Register
+ __IO hw_aips_pacrh_t PACRH; //!< [0x4C] Peripheral Access Control Register
+ __IO hw_aips_pacri_t PACRI; //!< [0x50] Peripheral Access Control Register
+ __IO hw_aips_pacrj_t PACRJ; //!< [0x54] Peripheral Access Control Register
+ __IO hw_aips_pacrk_t PACRK; //!< [0x58] Peripheral Access Control Register
+ __IO hw_aips_pacrl_t PACRL; //!< [0x5C] Peripheral Access Control Register
+ __IO hw_aips_pacrm_t PACRM; //!< [0x60] Peripheral Access Control Register
+ __IO hw_aips_pacrn_t PACRN; //!< [0x64] Peripheral Access Control Register
+ __IO hw_aips_pacro_t PACRO; //!< [0x68] Peripheral Access Control Register
+ __IO hw_aips_pacrp_t PACRP; //!< [0x6C] Peripheral Access Control Register
+ uint8_t _reserved2[16];
+ __IO hw_aips_pacru_t PACRU; //!< [0x80] Peripheral Access Control Register
+} hw_aips_t;
+#pragma pack()
+
+//! @brief Macro to access all AIPS registers.
+//! @param x AIPS instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_AIPS(0)</code>.
+#define HW_AIPS(x) (*(hw_aips_t *) REGS_AIPS_BASE(x))
+#endif
+
+#endif // __HW_AIPS_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_axbs.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,1078 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_AXBS_REGISTERS_H__
+#define __HW_AXBS_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 AXBS
+ *
+ * Crossbar switch
+ *
+ * Registers defined in this header file:
+ * - HW_AXBS_PRSn - Priority Registers Slave
+ * - HW_AXBS_CRSn - Control Register
+ * - HW_AXBS_MGPCR0 - Master General Purpose Control Register
+ * - HW_AXBS_MGPCR1 - Master General Purpose Control Register
+ * - HW_AXBS_MGPCR2 - Master General Purpose Control Register
+ * - HW_AXBS_MGPCR3 - Master General Purpose Control Register
+ * - HW_AXBS_MGPCR4 - Master General Purpose Control Register
+ * - HW_AXBS_MGPCR5 - Master General Purpose Control Register
+ *
+ * - hw_axbs_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_AXBS_BASE
+#define HW_AXBS_INSTANCE_COUNT (1U) //!< Number of instances of the AXBS module.
+#define REGS_AXBS_BASE (0x40004000U) //!< Base address for AXBS.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AXBS_PRSn - Priority Registers Slave
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AXBS_PRSn - Priority Registers Slave (RW)
+ *
+ * Reset value: 0x00543210U
+ *
+ * The priority registers (PRSn) set the priority of each master port on a per
+ * slave port basis and reside in each slave port. The priority register can be
+ * accessed only with 32-bit accesses. After the CRSn[RO] bit is set, the PRSn
+ * register can only be read; attempts to write to it have no effect on PRSn and
+ * result in a bus-error response to the master initiating the write. Two available
+ * masters must not be programmed with the same priority level. Attempts to
+ * program two or more masters with the same priority level result in a bus-error
+ * response and the PRSn is not updated. Valid values for the Mn priority fields
+ * depend on which masters are available on the chip. This information can be found in
+ * the chip-specific information for the crossbar. If the chip contains less
+ * than five masters, values 0 to 3 are valid. Writing other values will result in
+ * an error. If the chip contains five or more masters, valid values are 0 to n-1,
+ * where n is the number of masters attached to the AXBS module. Other values
+ * will result in an error.
+ */
+typedef union _hw_axbs_prsn
+{
+ uint32_t U;
+ struct _hw_axbs_prsn_bitfields
+ {
+ uint32_t M0 : 3; //!< [2:0] Master 0 Priority. Sets the arbitration
+ //! priority for this port on the associated slave port.
+ uint32_t RESERVED0 : 1; //!< [3]
+ uint32_t M1 : 3; //!< [6:4] Master 1 Priority. Sets the arbitration
+ //! priority for this port on the associated slave port.
+ uint32_t RESERVED1 : 1; //!< [7]
+ uint32_t M2 : 3; //!< [10:8] Master 2 Priority. Sets the arbitration
+ //! priority for this port on the associated slave port.
+ uint32_t RESERVED2 : 1; //!< [11]
+ uint32_t M3 : 3; //!< [14:12] Master 3 Priority. Sets the arbitration
+ //! priority for this port on the associated slave port.
+ uint32_t RESERVED3 : 1; //!< [15]
+ uint32_t M4 : 3; //!< [18:16] Master 4 Priority. Sets the arbitration
+ //! priority for this port on the associated slave port.
+ uint32_t RESERVED4 : 1; //!< [19]
+ uint32_t M5 : 3; //!< [22:20] Master 5 Priority. Sets the arbitration
+ //! priority for this port on the associated slave port.
+ uint32_t RESERVED5 : 9; //!< [31:23]
+ } B;
+} hw_axbs_prsn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AXBS_PRSn register
+ */
+//@{
+#define HW_AXBS_PRSn_COUNT (5U)
+
+#define HW_AXBS_PRSn_ADDR(n) (REGS_AXBS_BASE + 0x0U + (0x100U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AXBS_PRSn(n) (*(__IO hw_axbs_prsn_t *) HW_AXBS_PRSn_ADDR(n))
+#define HW_AXBS_PRSn_RD(n) (HW_AXBS_PRSn(n).U)
+#define HW_AXBS_PRSn_WR(n, v) (HW_AXBS_PRSn(n).U = (v))
+#define HW_AXBS_PRSn_SET(n, v) (HW_AXBS_PRSn_WR(n, HW_AXBS_PRSn_RD(n) | (v)))
+#define HW_AXBS_PRSn_CLR(n, v) (HW_AXBS_PRSn_WR(n, HW_AXBS_PRSn_RD(n) & ~(v)))
+#define HW_AXBS_PRSn_TOG(n, v) (HW_AXBS_PRSn_WR(n, HW_AXBS_PRSn_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AXBS_PRSn bitfields
+ */
+
+/*!
+ * @name Register AXBS_PRSn, field M0[2:0] (RW)
+ *
+ * Values:
+ * - 000 - This master has level 1, or highest, priority when accessing the
+ * slave port.
+ * - 001 - This master has level 2 priority when accessing the slave port.
+ * - 010 - This master has level 3 priority when accessing the slave port.
+ * - 011 - This master has level 4 priority when accessing the slave port.
+ * - 100 - This master has level 5 priority when accessing the slave port.
+ * - 101 - This master has level 6 priority when accessing the slave port.
+ * - 110 - This master has level 7 priority when accessing the slave port.
+ * - 111 - This master has level 8, or lowest, priority when accessing the slave
+ * port.
+ */
+//@{
+#define BP_AXBS_PRSn_M0 (0U) //!< Bit position for AXBS_PRSn_M0.
+#define BM_AXBS_PRSn_M0 (0x00000007U) //!< Bit mask for AXBS_PRSn_M0.
+#define BS_AXBS_PRSn_M0 (3U) //!< Bit field size in bits for AXBS_PRSn_M0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_PRSn_M0 field.
+#define BR_AXBS_PRSn_M0(n) (HW_AXBS_PRSn(n).B.M0)
+#endif
+
+//! @brief Format value for bitfield AXBS_PRSn_M0.
+#define BF_AXBS_PRSn_M0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M0), uint32_t) & BM_AXBS_PRSn_M0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M0 field to a new value.
+#define BW_AXBS_PRSn_M0(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M0) | BF_AXBS_PRSn_M0(v)))
+#endif
+//@}
+
+/*!
+ * @name Register AXBS_PRSn, field M1[6:4] (RW)
+ *
+ * Values:
+ * - 000 - This master has level 1, or highest, priority when accessing the
+ * slave port.
+ * - 001 - This master has level 2 priority when accessing the slave port.
+ * - 010 - This master has level 3 priority when accessing the slave port.
+ * - 011 - This master has level 4 priority when accessing the slave port.
+ * - 100 - This master has level 5 priority when accessing the slave port.
+ * - 101 - This master has level 6 priority when accessing the slave port.
+ * - 110 - This master has level 7 priority when accessing the slave port.
+ * - 111 - This master has level 8, or lowest, priority when accessing the slave
+ * port.
+ */
+//@{
+#define BP_AXBS_PRSn_M1 (4U) //!< Bit position for AXBS_PRSn_M1.
+#define BM_AXBS_PRSn_M1 (0x00000070U) //!< Bit mask for AXBS_PRSn_M1.
+#define BS_AXBS_PRSn_M1 (3U) //!< Bit field size in bits for AXBS_PRSn_M1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_PRSn_M1 field.
+#define BR_AXBS_PRSn_M1(n) (HW_AXBS_PRSn(n).B.M1)
+#endif
+
+//! @brief Format value for bitfield AXBS_PRSn_M1.
+#define BF_AXBS_PRSn_M1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M1), uint32_t) & BM_AXBS_PRSn_M1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M1 field to a new value.
+#define BW_AXBS_PRSn_M1(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M1) | BF_AXBS_PRSn_M1(v)))
+#endif
+//@}
+
+/*!
+ * @name Register AXBS_PRSn, field M2[10:8] (RW)
+ *
+ * Values:
+ * - 000 - This master has level 1, or highest, priority when accessing the
+ * slave port.
+ * - 001 - This master has level 2 priority when accessing the slave port.
+ * - 010 - This master has level 3 priority when accessing the slave port.
+ * - 011 - This master has level 4 priority when accessing the slave port.
+ * - 100 - This master has level 5 priority when accessing the slave port.
+ * - 101 - This master has level 6 priority when accessing the slave port.
+ * - 110 - This master has level 7 priority when accessing the slave port.
+ * - 111 - This master has level 8, or lowest, priority when accessing the slave
+ * port.
+ */
+//@{
+#define BP_AXBS_PRSn_M2 (8U) //!< Bit position for AXBS_PRSn_M2.
+#define BM_AXBS_PRSn_M2 (0x00000700U) //!< Bit mask for AXBS_PRSn_M2.
+#define BS_AXBS_PRSn_M2 (3U) //!< Bit field size in bits for AXBS_PRSn_M2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_PRSn_M2 field.
+#define BR_AXBS_PRSn_M2(n) (HW_AXBS_PRSn(n).B.M2)
+#endif
+
+//! @brief Format value for bitfield AXBS_PRSn_M2.
+#define BF_AXBS_PRSn_M2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M2), uint32_t) & BM_AXBS_PRSn_M2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M2 field to a new value.
+#define BW_AXBS_PRSn_M2(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M2) | BF_AXBS_PRSn_M2(v)))
+#endif
+//@}
+
+/*!
+ * @name Register AXBS_PRSn, field M3[14:12] (RW)
+ *
+ * Values:
+ * - 000 - This master has level 1, or highest, priority when accessing the
+ * slave port.
+ * - 001 - This master has level 2 priority when accessing the slave port.
+ * - 010 - This master has level 3 priority when accessing the slave port.
+ * - 011 - This master has level 4 priority when accessing the slave port.
+ * - 100 - This master has level 5 priority when accessing the slave port.
+ * - 101 - This master has level 6 priority when accessing the slave port.
+ * - 110 - This master has level 7 priority when accessing the slave port.
+ * - 111 - This master has level 8, or lowest, priority when accessing the slave
+ * port.
+ */
+//@{
+#define BP_AXBS_PRSn_M3 (12U) //!< Bit position for AXBS_PRSn_M3.
+#define BM_AXBS_PRSn_M3 (0x00007000U) //!< Bit mask for AXBS_PRSn_M3.
+#define BS_AXBS_PRSn_M3 (3U) //!< Bit field size in bits for AXBS_PRSn_M3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_PRSn_M3 field.
+#define BR_AXBS_PRSn_M3(n) (HW_AXBS_PRSn(n).B.M3)
+#endif
+
+//! @brief Format value for bitfield AXBS_PRSn_M3.
+#define BF_AXBS_PRSn_M3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M3), uint32_t) & BM_AXBS_PRSn_M3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M3 field to a new value.
+#define BW_AXBS_PRSn_M3(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M3) | BF_AXBS_PRSn_M3(v)))
+#endif
+//@}
+
+/*!
+ * @name Register AXBS_PRSn, field M4[18:16] (RW)
+ *
+ * Values:
+ * - 000 - This master has level 1, or highest, priority when accessing the
+ * slave port.
+ * - 001 - This master has level 2 priority when accessing the slave port.
+ * - 010 - This master has level 3 priority when accessing the slave port.
+ * - 011 - This master has level 4 priority when accessing the slave port.
+ * - 100 - This master has level 5 priority when accessing the slave port.
+ * - 101 - This master has level 6 priority when accessing the slave port.
+ * - 110 - This master has level 7 priority when accessing the slave port.
+ * - 111 - This master has level 8, or lowest, priority when accessing the slave
+ * port.
+ */
+//@{
+#define BP_AXBS_PRSn_M4 (16U) //!< Bit position for AXBS_PRSn_M4.
+#define BM_AXBS_PRSn_M4 (0x00070000U) //!< Bit mask for AXBS_PRSn_M4.
+#define BS_AXBS_PRSn_M4 (3U) //!< Bit field size in bits for AXBS_PRSn_M4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_PRSn_M4 field.
+#define BR_AXBS_PRSn_M4(n) (HW_AXBS_PRSn(n).B.M4)
+#endif
+
+//! @brief Format value for bitfield AXBS_PRSn_M4.
+#define BF_AXBS_PRSn_M4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M4), uint32_t) & BM_AXBS_PRSn_M4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M4 field to a new value.
+#define BW_AXBS_PRSn_M4(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M4) | BF_AXBS_PRSn_M4(v)))
+#endif
+//@}
+
+/*!
+ * @name Register AXBS_PRSn, field M5[22:20] (RW)
+ *
+ * Values:
+ * - 000 - This master has level 1, or highest, priority when accessing the
+ * slave port.
+ * - 001 - This master has level 2 priority when accessing the slave port.
+ * - 010 - This master has level 3 priority when accessing the slave port.
+ * - 011 - This master has level 4 priority when accessing the slave port.
+ * - 100 - This master has level 5 priority when accessing the slave port.
+ * - 101 - This master has level 6 priority when accessing the slave port.
+ * - 110 - This master has level 7 priority when accessing the slave port.
+ * - 111 - This master has level 8, or lowest, priority when accessing the slave
+ * port.
+ */
+//@{
+#define BP_AXBS_PRSn_M5 (20U) //!< Bit position for AXBS_PRSn_M5.
+#define BM_AXBS_PRSn_M5 (0x00700000U) //!< Bit mask for AXBS_PRSn_M5.
+#define BS_AXBS_PRSn_M5 (3U) //!< Bit field size in bits for AXBS_PRSn_M5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_PRSn_M5 field.
+#define BR_AXBS_PRSn_M5(n) (HW_AXBS_PRSn(n).B.M5)
+#endif
+
+//! @brief Format value for bitfield AXBS_PRSn_M5.
+#define BF_AXBS_PRSn_M5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_PRSn_M5), uint32_t) & BM_AXBS_PRSn_M5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M5 field to a new value.
+#define BW_AXBS_PRSn_M5(n, v) (HW_AXBS_PRSn_WR(n, (HW_AXBS_PRSn_RD(n) & ~BM_AXBS_PRSn_M5) | BF_AXBS_PRSn_M5(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_AXBS_CRSn - Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AXBS_CRSn - Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers control several features of each slave port and must be
+ * accessed using 32-bit accesses. After CRSn[RO] is set, the PRSn can only be read;
+ * attempts to write to it have no effect and result in an error response.
+ */
+typedef union _hw_axbs_crsn
+{
+ uint32_t U;
+ struct _hw_axbs_crsn_bitfields
+ {
+ uint32_t PARK : 3; //!< [2:0] Park
+ uint32_t RESERVED0 : 1; //!< [3]
+ uint32_t PCTL : 2; //!< [5:4] Parking Control
+ uint32_t RESERVED1 : 2; //!< [7:6]
+ uint32_t ARB : 2; //!< [9:8] Arbitration Mode
+ uint32_t RESERVED2 : 20; //!< [29:10]
+ uint32_t HLP : 1; //!< [30] Halt Low Priority
+ uint32_t RO : 1; //!< [31] Read Only
+ } B;
+} hw_axbs_crsn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AXBS_CRSn register
+ */
+//@{
+#define HW_AXBS_CRSn_COUNT (5U)
+
+#define HW_AXBS_CRSn_ADDR(n) (REGS_AXBS_BASE + 0x10U + (0x100U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AXBS_CRSn(n) (*(__IO hw_axbs_crsn_t *) HW_AXBS_CRSn_ADDR(n))
+#define HW_AXBS_CRSn_RD(n) (HW_AXBS_CRSn(n).U)
+#define HW_AXBS_CRSn_WR(n, v) (HW_AXBS_CRSn(n).U = (v))
+#define HW_AXBS_CRSn_SET(n, v) (HW_AXBS_CRSn_WR(n, HW_AXBS_CRSn_RD(n) | (v)))
+#define HW_AXBS_CRSn_CLR(n, v) (HW_AXBS_CRSn_WR(n, HW_AXBS_CRSn_RD(n) & ~(v)))
+#define HW_AXBS_CRSn_TOG(n, v) (HW_AXBS_CRSn_WR(n, HW_AXBS_CRSn_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AXBS_CRSn bitfields
+ */
+
+/*!
+ * @name Register AXBS_CRSn, field PARK[2:0] (RW)
+ *
+ * Determines which master port the current slave port parks on when no masters
+ * are actively making requests and the PCTL bits are cleared. Select only master
+ * ports that are present on the chip. Otherwise, undefined behavior might occur.
+ *
+ * Values:
+ * - 000 - Park on master port M0
+ * - 001 - Park on master port M1
+ * - 010 - Park on master port M2
+ * - 011 - Park on master port M3
+ * - 100 - Park on master port M4
+ * - 101 - Park on master port M5
+ * - 110 - Park on master port M6
+ * - 111 - Park on master port M7
+ */
+//@{
+#define BP_AXBS_CRSn_PARK (0U) //!< Bit position for AXBS_CRSn_PARK.
+#define BM_AXBS_CRSn_PARK (0x00000007U) //!< Bit mask for AXBS_CRSn_PARK.
+#define BS_AXBS_CRSn_PARK (3U) //!< Bit field size in bits for AXBS_CRSn_PARK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_CRSn_PARK field.
+#define BR_AXBS_CRSn_PARK(n) (HW_AXBS_CRSn(n).B.PARK)
+#endif
+
+//! @brief Format value for bitfield AXBS_CRSn_PARK.
+#define BF_AXBS_CRSn_PARK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_CRSn_PARK), uint32_t) & BM_AXBS_CRSn_PARK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PARK field to a new value.
+#define BW_AXBS_CRSn_PARK(n, v) (HW_AXBS_CRSn_WR(n, (HW_AXBS_CRSn_RD(n) & ~BM_AXBS_CRSn_PARK) | BF_AXBS_CRSn_PARK(v)))
+#endif
+//@}
+
+/*!
+ * @name Register AXBS_CRSn, field PCTL[5:4] (RW)
+ *
+ * Determines the slave port's parking control. The low-power park feature
+ * results in an overall power savings if the slave port is not saturated. However,
+ * this forces an extra latency clock when any master tries to access the slave
+ * port while not in use because it is not parked on any master.
+ *
+ * Values:
+ * - 00 - When no master makes a request, the arbiter parks the slave port on
+ * the master port defined by the PARK field
+ * - 01 - When no master makes a request, the arbiter parks the slave port on
+ * the last master to be in control of the slave port
+ * - 10 - When no master makes a request, the slave port is not parked on a
+ * master and the arbiter drives all outputs to a constant safe state
+ * - 11 - Reserved
+ */
+//@{
+#define BP_AXBS_CRSn_PCTL (4U) //!< Bit position for AXBS_CRSn_PCTL.
+#define BM_AXBS_CRSn_PCTL (0x00000030U) //!< Bit mask for AXBS_CRSn_PCTL.
+#define BS_AXBS_CRSn_PCTL (2U) //!< Bit field size in bits for AXBS_CRSn_PCTL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_CRSn_PCTL field.
+#define BR_AXBS_CRSn_PCTL(n) (HW_AXBS_CRSn(n).B.PCTL)
+#endif
+
+//! @brief Format value for bitfield AXBS_CRSn_PCTL.
+#define BF_AXBS_CRSn_PCTL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_CRSn_PCTL), uint32_t) & BM_AXBS_CRSn_PCTL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PCTL field to a new value.
+#define BW_AXBS_CRSn_PCTL(n, v) (HW_AXBS_CRSn_WR(n, (HW_AXBS_CRSn_RD(n) & ~BM_AXBS_CRSn_PCTL) | BF_AXBS_CRSn_PCTL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register AXBS_CRSn, field ARB[9:8] (RW)
+ *
+ * Selects the arbitration policy for the slave port.
+ *
+ * Values:
+ * - 00 - Fixed priority
+ * - 01 - Round-robin, or rotating, priority
+ * - 10 - Reserved
+ * - 11 - Reserved
+ */
+//@{
+#define BP_AXBS_CRSn_ARB (8U) //!< Bit position for AXBS_CRSn_ARB.
+#define BM_AXBS_CRSn_ARB (0x00000300U) //!< Bit mask for AXBS_CRSn_ARB.
+#define BS_AXBS_CRSn_ARB (2U) //!< Bit field size in bits for AXBS_CRSn_ARB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_CRSn_ARB field.
+#define BR_AXBS_CRSn_ARB(n) (HW_AXBS_CRSn(n).B.ARB)
+#endif
+
+//! @brief Format value for bitfield AXBS_CRSn_ARB.
+#define BF_AXBS_CRSn_ARB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_CRSn_ARB), uint32_t) & BM_AXBS_CRSn_ARB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ARB field to a new value.
+#define BW_AXBS_CRSn_ARB(n, v) (HW_AXBS_CRSn_WR(n, (HW_AXBS_CRSn_RD(n) & ~BM_AXBS_CRSn_ARB) | BF_AXBS_CRSn_ARB(v)))
+#endif
+//@}
+
+/*!
+ * @name Register AXBS_CRSn, field HLP[30] (RW)
+ *
+ * Sets the initial arbitration priority for low power mode requests . Setting
+ * this bit will not affect the request for low power mode from attaining highest
+ * priority once it has control of the slave ports.
+ *
+ * Values:
+ * - 0 - The low power mode request has the highest priority for arbitration on
+ * this slave port
+ * - 1 - The low power mode request has the lowest initial priority for
+ * arbitration on this slave port
+ */
+//@{
+#define BP_AXBS_CRSn_HLP (30U) //!< Bit position for AXBS_CRSn_HLP.
+#define BM_AXBS_CRSn_HLP (0x40000000U) //!< Bit mask for AXBS_CRSn_HLP.
+#define BS_AXBS_CRSn_HLP (1U) //!< Bit field size in bits for AXBS_CRSn_HLP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_CRSn_HLP field.
+#define BR_AXBS_CRSn_HLP(n) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(n), BP_AXBS_CRSn_HLP))
+#endif
+
+//! @brief Format value for bitfield AXBS_CRSn_HLP.
+#define BF_AXBS_CRSn_HLP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_CRSn_HLP), uint32_t) & BM_AXBS_CRSn_HLP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HLP field to a new value.
+#define BW_AXBS_CRSn_HLP(n, v) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(n), BP_AXBS_CRSn_HLP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register AXBS_CRSn, field RO[31] (RW)
+ *
+ * Forces the slave port's CSRn and PRSn registers to be read-only. After set,
+ * only a hardware reset clears it.
+ *
+ * Values:
+ * - 0 - The slave port's registers are writeable
+ * - 1 - The slave port's registers are read-only and cannot be written.
+ * Attempted writes have no effect on the registers and result in a bus error
+ * response.
+ */
+//@{
+#define BP_AXBS_CRSn_RO (31U) //!< Bit position for AXBS_CRSn_RO.
+#define BM_AXBS_CRSn_RO (0x80000000U) //!< Bit mask for AXBS_CRSn_RO.
+#define BS_AXBS_CRSn_RO (1U) //!< Bit field size in bits for AXBS_CRSn_RO.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_CRSn_RO field.
+#define BR_AXBS_CRSn_RO(n) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(n), BP_AXBS_CRSn_RO))
+#endif
+
+//! @brief Format value for bitfield AXBS_CRSn_RO.
+#define BF_AXBS_CRSn_RO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_CRSn_RO), uint32_t) & BM_AXBS_CRSn_RO)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RO field to a new value.
+#define BW_AXBS_CRSn_RO(n, v) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(n), BP_AXBS_CRSn_RO) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AXBS_MGPCR0 - Master General Purpose Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AXBS_MGPCR0 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+typedef union _hw_axbs_mgpcr0
+{
+ uint32_t U;
+ struct _hw_axbs_mgpcr0_bitfields
+ {
+ uint32_t AULB : 3; //!< [2:0] Arbitrates On Undefined Length Bursts
+ uint32_t RESERVED0 : 29; //!< [31:3]
+ } B;
+} hw_axbs_mgpcr0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR0 register
+ */
+//@{
+#define HW_AXBS_MGPCR0_ADDR (REGS_AXBS_BASE + 0x800U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AXBS_MGPCR0 (*(__IO hw_axbs_mgpcr0_t *) HW_AXBS_MGPCR0_ADDR)
+#define HW_AXBS_MGPCR0_RD() (HW_AXBS_MGPCR0.U)
+#define HW_AXBS_MGPCR0_WR(v) (HW_AXBS_MGPCR0.U = (v))
+#define HW_AXBS_MGPCR0_SET(v) (HW_AXBS_MGPCR0_WR(HW_AXBS_MGPCR0_RD() | (v)))
+#define HW_AXBS_MGPCR0_CLR(v) (HW_AXBS_MGPCR0_WR(HW_AXBS_MGPCR0_RD() & ~(v)))
+#define HW_AXBS_MGPCR0_TOG(v) (HW_AXBS_MGPCR0_WR(HW_AXBS_MGPCR0_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AXBS_MGPCR0 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR0, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 000 - No arbitration is allowed during an undefined length burst
+ * - 001 - Arbitration is allowed at any time during an undefined length burst
+ * - 010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 011 - Arbitration is allowed after eight beats of an undefined length burst
+ * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 101 - Reserved
+ * - 110 - Reserved
+ * - 111 - Reserved
+ */
+//@{
+#define BP_AXBS_MGPCR0_AULB (0U) //!< Bit position for AXBS_MGPCR0_AULB.
+#define BM_AXBS_MGPCR0_AULB (0x00000007U) //!< Bit mask for AXBS_MGPCR0_AULB.
+#define BS_AXBS_MGPCR0_AULB (3U) //!< Bit field size in bits for AXBS_MGPCR0_AULB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_MGPCR0_AULB field.
+#define BR_AXBS_MGPCR0_AULB (HW_AXBS_MGPCR0.B.AULB)
+#endif
+
+//! @brief Format value for bitfield AXBS_MGPCR0_AULB.
+#define BF_AXBS_MGPCR0_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR0_AULB), uint32_t) & BM_AXBS_MGPCR0_AULB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AULB field to a new value.
+#define BW_AXBS_MGPCR0_AULB(v) (HW_AXBS_MGPCR0_WR((HW_AXBS_MGPCR0_RD() & ~BM_AXBS_MGPCR0_AULB) | BF_AXBS_MGPCR0_AULB(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AXBS_MGPCR1 - Master General Purpose Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AXBS_MGPCR1 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+typedef union _hw_axbs_mgpcr1
+{
+ uint32_t U;
+ struct _hw_axbs_mgpcr1_bitfields
+ {
+ uint32_t AULB : 3; //!< [2:0] Arbitrates On Undefined Length Bursts
+ uint32_t RESERVED0 : 29; //!< [31:3]
+ } B;
+} hw_axbs_mgpcr1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR1 register
+ */
+//@{
+#define HW_AXBS_MGPCR1_ADDR (REGS_AXBS_BASE + 0x900U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AXBS_MGPCR1 (*(__IO hw_axbs_mgpcr1_t *) HW_AXBS_MGPCR1_ADDR)
+#define HW_AXBS_MGPCR1_RD() (HW_AXBS_MGPCR1.U)
+#define HW_AXBS_MGPCR1_WR(v) (HW_AXBS_MGPCR1.U = (v))
+#define HW_AXBS_MGPCR1_SET(v) (HW_AXBS_MGPCR1_WR(HW_AXBS_MGPCR1_RD() | (v)))
+#define HW_AXBS_MGPCR1_CLR(v) (HW_AXBS_MGPCR1_WR(HW_AXBS_MGPCR1_RD() & ~(v)))
+#define HW_AXBS_MGPCR1_TOG(v) (HW_AXBS_MGPCR1_WR(HW_AXBS_MGPCR1_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AXBS_MGPCR1 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR1, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 000 - No arbitration is allowed during an undefined length burst
+ * - 001 - Arbitration is allowed at any time during an undefined length burst
+ * - 010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 011 - Arbitration is allowed after eight beats of an undefined length burst
+ * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 101 - Reserved
+ * - 110 - Reserved
+ * - 111 - Reserved
+ */
+//@{
+#define BP_AXBS_MGPCR1_AULB (0U) //!< Bit position for AXBS_MGPCR1_AULB.
+#define BM_AXBS_MGPCR1_AULB (0x00000007U) //!< Bit mask for AXBS_MGPCR1_AULB.
+#define BS_AXBS_MGPCR1_AULB (3U) //!< Bit field size in bits for AXBS_MGPCR1_AULB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_MGPCR1_AULB field.
+#define BR_AXBS_MGPCR1_AULB (HW_AXBS_MGPCR1.B.AULB)
+#endif
+
+//! @brief Format value for bitfield AXBS_MGPCR1_AULB.
+#define BF_AXBS_MGPCR1_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR1_AULB), uint32_t) & BM_AXBS_MGPCR1_AULB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AULB field to a new value.
+#define BW_AXBS_MGPCR1_AULB(v) (HW_AXBS_MGPCR1_WR((HW_AXBS_MGPCR1_RD() & ~BM_AXBS_MGPCR1_AULB) | BF_AXBS_MGPCR1_AULB(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AXBS_MGPCR2 - Master General Purpose Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AXBS_MGPCR2 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+typedef union _hw_axbs_mgpcr2
+{
+ uint32_t U;
+ struct _hw_axbs_mgpcr2_bitfields
+ {
+ uint32_t AULB : 3; //!< [2:0] Arbitrates On Undefined Length Bursts
+ uint32_t RESERVED0 : 29; //!< [31:3]
+ } B;
+} hw_axbs_mgpcr2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR2 register
+ */
+//@{
+#define HW_AXBS_MGPCR2_ADDR (REGS_AXBS_BASE + 0xA00U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AXBS_MGPCR2 (*(__IO hw_axbs_mgpcr2_t *) HW_AXBS_MGPCR2_ADDR)
+#define HW_AXBS_MGPCR2_RD() (HW_AXBS_MGPCR2.U)
+#define HW_AXBS_MGPCR2_WR(v) (HW_AXBS_MGPCR2.U = (v))
+#define HW_AXBS_MGPCR2_SET(v) (HW_AXBS_MGPCR2_WR(HW_AXBS_MGPCR2_RD() | (v)))
+#define HW_AXBS_MGPCR2_CLR(v) (HW_AXBS_MGPCR2_WR(HW_AXBS_MGPCR2_RD() & ~(v)))
+#define HW_AXBS_MGPCR2_TOG(v) (HW_AXBS_MGPCR2_WR(HW_AXBS_MGPCR2_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AXBS_MGPCR2 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR2, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 000 - No arbitration is allowed during an undefined length burst
+ * - 001 - Arbitration is allowed at any time during an undefined length burst
+ * - 010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 011 - Arbitration is allowed after eight beats of an undefined length burst
+ * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 101 - Reserved
+ * - 110 - Reserved
+ * - 111 - Reserved
+ */
+//@{
+#define BP_AXBS_MGPCR2_AULB (0U) //!< Bit position for AXBS_MGPCR2_AULB.
+#define BM_AXBS_MGPCR2_AULB (0x00000007U) //!< Bit mask for AXBS_MGPCR2_AULB.
+#define BS_AXBS_MGPCR2_AULB (3U) //!< Bit field size in bits for AXBS_MGPCR2_AULB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_MGPCR2_AULB field.
+#define BR_AXBS_MGPCR2_AULB (HW_AXBS_MGPCR2.B.AULB)
+#endif
+
+//! @brief Format value for bitfield AXBS_MGPCR2_AULB.
+#define BF_AXBS_MGPCR2_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR2_AULB), uint32_t) & BM_AXBS_MGPCR2_AULB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AULB field to a new value.
+#define BW_AXBS_MGPCR2_AULB(v) (HW_AXBS_MGPCR2_WR((HW_AXBS_MGPCR2_RD() & ~BM_AXBS_MGPCR2_AULB) | BF_AXBS_MGPCR2_AULB(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AXBS_MGPCR3 - Master General Purpose Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AXBS_MGPCR3 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+typedef union _hw_axbs_mgpcr3
+{
+ uint32_t U;
+ struct _hw_axbs_mgpcr3_bitfields
+ {
+ uint32_t AULB : 3; //!< [2:0] Arbitrates On Undefined Length Bursts
+ uint32_t RESERVED0 : 29; //!< [31:3]
+ } B;
+} hw_axbs_mgpcr3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR3 register
+ */
+//@{
+#define HW_AXBS_MGPCR3_ADDR (REGS_AXBS_BASE + 0xB00U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AXBS_MGPCR3 (*(__IO hw_axbs_mgpcr3_t *) HW_AXBS_MGPCR3_ADDR)
+#define HW_AXBS_MGPCR3_RD() (HW_AXBS_MGPCR3.U)
+#define HW_AXBS_MGPCR3_WR(v) (HW_AXBS_MGPCR3.U = (v))
+#define HW_AXBS_MGPCR3_SET(v) (HW_AXBS_MGPCR3_WR(HW_AXBS_MGPCR3_RD() | (v)))
+#define HW_AXBS_MGPCR3_CLR(v) (HW_AXBS_MGPCR3_WR(HW_AXBS_MGPCR3_RD() & ~(v)))
+#define HW_AXBS_MGPCR3_TOG(v) (HW_AXBS_MGPCR3_WR(HW_AXBS_MGPCR3_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AXBS_MGPCR3 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR3, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 000 - No arbitration is allowed during an undefined length burst
+ * - 001 - Arbitration is allowed at any time during an undefined length burst
+ * - 010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 011 - Arbitration is allowed after eight beats of an undefined length burst
+ * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 101 - Reserved
+ * - 110 - Reserved
+ * - 111 - Reserved
+ */
+//@{
+#define BP_AXBS_MGPCR3_AULB (0U) //!< Bit position for AXBS_MGPCR3_AULB.
+#define BM_AXBS_MGPCR3_AULB (0x00000007U) //!< Bit mask for AXBS_MGPCR3_AULB.
+#define BS_AXBS_MGPCR3_AULB (3U) //!< Bit field size in bits for AXBS_MGPCR3_AULB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_MGPCR3_AULB field.
+#define BR_AXBS_MGPCR3_AULB (HW_AXBS_MGPCR3.B.AULB)
+#endif
+
+//! @brief Format value for bitfield AXBS_MGPCR3_AULB.
+#define BF_AXBS_MGPCR3_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR3_AULB), uint32_t) & BM_AXBS_MGPCR3_AULB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AULB field to a new value.
+#define BW_AXBS_MGPCR3_AULB(v) (HW_AXBS_MGPCR3_WR((HW_AXBS_MGPCR3_RD() & ~BM_AXBS_MGPCR3_AULB) | BF_AXBS_MGPCR3_AULB(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AXBS_MGPCR4 - Master General Purpose Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AXBS_MGPCR4 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+typedef union _hw_axbs_mgpcr4
+{
+ uint32_t U;
+ struct _hw_axbs_mgpcr4_bitfields
+ {
+ uint32_t AULB : 3; //!< [2:0] Arbitrates On Undefined Length Bursts
+ uint32_t RESERVED0 : 29; //!< [31:3]
+ } B;
+} hw_axbs_mgpcr4_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR4 register
+ */
+//@{
+#define HW_AXBS_MGPCR4_ADDR (REGS_AXBS_BASE + 0xC00U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AXBS_MGPCR4 (*(__IO hw_axbs_mgpcr4_t *) HW_AXBS_MGPCR4_ADDR)
+#define HW_AXBS_MGPCR4_RD() (HW_AXBS_MGPCR4.U)
+#define HW_AXBS_MGPCR4_WR(v) (HW_AXBS_MGPCR4.U = (v))
+#define HW_AXBS_MGPCR4_SET(v) (HW_AXBS_MGPCR4_WR(HW_AXBS_MGPCR4_RD() | (v)))
+#define HW_AXBS_MGPCR4_CLR(v) (HW_AXBS_MGPCR4_WR(HW_AXBS_MGPCR4_RD() & ~(v)))
+#define HW_AXBS_MGPCR4_TOG(v) (HW_AXBS_MGPCR4_WR(HW_AXBS_MGPCR4_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AXBS_MGPCR4 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR4, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 000 - No arbitration is allowed during an undefined length burst
+ * - 001 - Arbitration is allowed at any time during an undefined length burst
+ * - 010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 011 - Arbitration is allowed after eight beats of an undefined length burst
+ * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 101 - Reserved
+ * - 110 - Reserved
+ * - 111 - Reserved
+ */
+//@{
+#define BP_AXBS_MGPCR4_AULB (0U) //!< Bit position for AXBS_MGPCR4_AULB.
+#define BM_AXBS_MGPCR4_AULB (0x00000007U) //!< Bit mask for AXBS_MGPCR4_AULB.
+#define BS_AXBS_MGPCR4_AULB (3U) //!< Bit field size in bits for AXBS_MGPCR4_AULB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_MGPCR4_AULB field.
+#define BR_AXBS_MGPCR4_AULB (HW_AXBS_MGPCR4.B.AULB)
+#endif
+
+//! @brief Format value for bitfield AXBS_MGPCR4_AULB.
+#define BF_AXBS_MGPCR4_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR4_AULB), uint32_t) & BM_AXBS_MGPCR4_AULB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AULB field to a new value.
+#define BW_AXBS_MGPCR4_AULB(v) (HW_AXBS_MGPCR4_WR((HW_AXBS_MGPCR4_RD() & ~BM_AXBS_MGPCR4_AULB) | BF_AXBS_MGPCR4_AULB(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_AXBS_MGPCR5 - Master General Purpose Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_AXBS_MGPCR5 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+typedef union _hw_axbs_mgpcr5
+{
+ uint32_t U;
+ struct _hw_axbs_mgpcr5_bitfields
+ {
+ uint32_t AULB : 3; //!< [2:0] Arbitrates On Undefined Length Bursts
+ uint32_t RESERVED0 : 29; //!< [31:3]
+ } B;
+} hw_axbs_mgpcr5_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR5 register
+ */
+//@{
+#define HW_AXBS_MGPCR5_ADDR (REGS_AXBS_BASE + 0xD00U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_AXBS_MGPCR5 (*(__IO hw_axbs_mgpcr5_t *) HW_AXBS_MGPCR5_ADDR)
+#define HW_AXBS_MGPCR5_RD() (HW_AXBS_MGPCR5.U)
+#define HW_AXBS_MGPCR5_WR(v) (HW_AXBS_MGPCR5.U = (v))
+#define HW_AXBS_MGPCR5_SET(v) (HW_AXBS_MGPCR5_WR(HW_AXBS_MGPCR5_RD() | (v)))
+#define HW_AXBS_MGPCR5_CLR(v) (HW_AXBS_MGPCR5_WR(HW_AXBS_MGPCR5_RD() & ~(v)))
+#define HW_AXBS_MGPCR5_TOG(v) (HW_AXBS_MGPCR5_WR(HW_AXBS_MGPCR5_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual AXBS_MGPCR5 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR5, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 000 - No arbitration is allowed during an undefined length burst
+ * - 001 - Arbitration is allowed at any time during an undefined length burst
+ * - 010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 011 - Arbitration is allowed after eight beats of an undefined length burst
+ * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 101 - Reserved
+ * - 110 - Reserved
+ * - 111 - Reserved
+ */
+//@{
+#define BP_AXBS_MGPCR5_AULB (0U) //!< Bit position for AXBS_MGPCR5_AULB.
+#define BM_AXBS_MGPCR5_AULB (0x00000007U) //!< Bit mask for AXBS_MGPCR5_AULB.
+#define BS_AXBS_MGPCR5_AULB (3U) //!< Bit field size in bits for AXBS_MGPCR5_AULB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the AXBS_MGPCR5_AULB field.
+#define BR_AXBS_MGPCR5_AULB (HW_AXBS_MGPCR5.B.AULB)
+#endif
+
+//! @brief Format value for bitfield AXBS_MGPCR5_AULB.
+#define BF_AXBS_MGPCR5_AULB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_AXBS_MGPCR5_AULB), uint32_t) & BM_AXBS_MGPCR5_AULB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AULB field to a new value.
+#define BW_AXBS_MGPCR5_AULB(v) (HW_AXBS_MGPCR5_WR((HW_AXBS_MGPCR5_RD() & ~BM_AXBS_MGPCR5_AULB) | BF_AXBS_MGPCR5_AULB(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_axbs_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All AXBS module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_axbs
+{
+ struct {
+ __IO hw_axbs_prsn_t PRSn; //!< [0x0] Priority Registers Slave
+ uint8_t _reserved0[12];
+ __IO hw_axbs_crsn_t CRSn; //!< [0x10] Control Register
+ uint8_t _reserved1[236];
+ } SLAVE[5];
+ uint8_t _reserved0[768];
+ __IO hw_axbs_mgpcr0_t MGPCR0; //!< [0x800] Master General Purpose Control Register
+ uint8_t _reserved1[252];
+ __IO hw_axbs_mgpcr1_t MGPCR1; //!< [0x900] Master General Purpose Control Register
+ uint8_t _reserved2[252];
+ __IO hw_axbs_mgpcr2_t MGPCR2; //!< [0xA00] Master General Purpose Control Register
+ uint8_t _reserved3[252];
+ __IO hw_axbs_mgpcr3_t MGPCR3; //!< [0xB00] Master General Purpose Control Register
+ uint8_t _reserved4[252];
+ __IO hw_axbs_mgpcr4_t MGPCR4; //!< [0xC00] Master General Purpose Control Register
+ uint8_t _reserved5[252];
+ __IO hw_axbs_mgpcr5_t MGPCR5; //!< [0xD00] Master General Purpose Control Register
+} hw_axbs_t;
+#pragma pack()
+
+//! @brief Macro to access all AXBS registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_AXBS</code>.
+#define HW_AXBS (*(hw_axbs_t *) REGS_AXBS_BASE)
+#endif
+
+#endif // __HW_AXBS_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_can.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,3963 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_CAN_REGISTERS_H__
+#define __HW_CAN_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 CAN
+ *
+ * Flex Controller Area Network module
+ *
+ * Registers defined in this header file:
+ * - HW_CAN_MCR - Module Configuration Register
+ * - HW_CAN_CTRL1 - Control 1 register
+ * - HW_CAN_TIMER - Free Running Timer
+ * - HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register
+ * - HW_CAN_RX14MASK - Rx 14 Mask register
+ * - HW_CAN_RX15MASK - Rx 15 Mask register
+ * - HW_CAN_ECR - Error Counter
+ * - HW_CAN_ESR1 - Error and Status 1 register
+ * - HW_CAN_IMASK1 - Interrupt Masks 1 register
+ * - HW_CAN_IFLAG1 - Interrupt Flags 1 register
+ * - HW_CAN_CTRL2 - Control 2 register
+ * - HW_CAN_ESR2 - Error and Status 2 register
+ * - HW_CAN_CRCR - CRC Register
+ * - HW_CAN_RXFGMASK - Rx FIFO Global Mask register
+ * - HW_CAN_RXFIR - Rx FIFO Information Register
+ * - HW_CAN_CS - Message Buffer 0 CS Register
+ * - HW_CAN_ID - Message Buffer 0 ID Register
+ * - HW_CAN_WORD0 - Message Buffer 0 WORD0 Register
+ * - HW_CAN_WORD1 - Message Buffer 0 WORD1 Register
+ * - HW_CAN_RXIMRn - Rx Individual Mask Registers
+ *
+ * - hw_can_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_CAN_BASE
+#define HW_CAN_INSTANCE_COUNT (1U) //!< Number of instances of the CAN module.
+#define HW_CAN0 (0U) //!< Instance number for CAN0.
+#define REGS_CAN0_BASE (0x40024000U) //!< Base address for CAN0.
+
+//! @brief Table of base addresses for CAN instances.
+static const uint32_t __g_regs_CAN_base_addresses[] = {
+ REGS_CAN0_BASE,
+ };
+
+//! @brief Get the base address of CAN by instance number.
+//! @param x CAN instance number, from 0 through 0.
+#define REGS_CAN_BASE(x) (__g_regs_CAN_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of CAN.
+#define REGS_CAN_INSTANCE(b) ((b) == REGS_CAN0_BASE ? HW_CAN0 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_MCR - Module Configuration Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_MCR - Module Configuration Register (RW)
+ *
+ * Reset value: 0xD890000FU
+ *
+ * This register defines global system configurations, such as the module
+ * operation modes and the maximum message buffer configuration.
+ */
+typedef union _hw_can_mcr
+{
+ uint32_t U;
+ struct _hw_can_mcr_bitfields
+ {
+ uint32_t MAXMB : 7; //!< [6:0] Number Of The Last Message Buffer
+ uint32_t RESERVED0 : 1; //!< [7]
+ uint32_t IDAM : 2; //!< [9:8] ID Acceptance Mode
+ uint32_t RESERVED1 : 2; //!< [11:10]
+ uint32_t AEN : 1; //!< [12] Abort Enable
+ uint32_t LPRIOEN : 1; //!< [13] Local Priority Enable
+ uint32_t RESERVED2 : 2; //!< [15:14]
+ uint32_t IRMQ : 1; //!< [16] Individual Rx Masking And Queue Enable
+ uint32_t SRXDIS : 1; //!< [17] Self Reception Disable
+ uint32_t RESERVED3 : 1; //!< [18]
+ uint32_t WAKSRC : 1; //!< [19] Wake Up Source
+ uint32_t LPMACK : 1; //!< [20] Low-Power Mode Acknowledge
+ uint32_t WRNEN : 1; //!< [21] Warning Interrupt Enable
+ uint32_t SLFWAK : 1; //!< [22] Self Wake Up
+ uint32_t SUPV : 1; //!< [23] Supervisor Mode
+ uint32_t FRZACK : 1; //!< [24] Freeze Mode Acknowledge
+ uint32_t SOFTRST : 1; //!< [25] Soft Reset
+ uint32_t WAKMSK : 1; //!< [26] Wake Up Interrupt Mask
+ uint32_t NOTRDY : 1; //!< [27] FlexCAN Not Ready
+ uint32_t HALT : 1; //!< [28] Halt FlexCAN
+ uint32_t RFEN : 1; //!< [29] Rx FIFO Enable
+ uint32_t FRZ : 1; //!< [30] Freeze Enable
+ uint32_t MDIS : 1; //!< [31] Module Disable
+ } B;
+} hw_can_mcr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_MCR register
+ */
+//@{
+#define HW_CAN_MCR_ADDR(x) (REGS_CAN_BASE(x) + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_MCR(x) (*(__IO hw_can_mcr_t *) HW_CAN_MCR_ADDR(x))
+#define HW_CAN_MCR_RD(x) (HW_CAN_MCR(x).U)
+#define HW_CAN_MCR_WR(x, v) (HW_CAN_MCR(x).U = (v))
+#define HW_CAN_MCR_SET(x, v) (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) | (v)))
+#define HW_CAN_MCR_CLR(x, v) (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) & ~(v)))
+#define HW_CAN_MCR_TOG(x, v) (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_MCR bitfields
+ */
+
+/*!
+ * @name Register CAN_MCR, field MAXMB[6:0] (RW)
+ *
+ * This 7-bit field defines the number of the last Message Buffers that will
+ * take part in the matching and arbitration processes. The reset value (0x0F) is
+ * equivalent to a 16 MB configuration. This field can be written only in Freeze
+ * mode because it is blocked by hardware in other modes. Number of the last MB =
+ * MAXMB MAXMB must be programmed with a value smaller than the parameter
+ * NUMBER_OF_MB, otherwise the number of the last effective Message Buffer will be:
+ * (NUMBER_OF_MB - 1) Additionally, the value of MAXMB must encompass the FIFO size
+ * defined by CTRL2[RFFN]. MAXMB also impacts the definition of the minimum number
+ * of peripheral clocks per CAN bit as described in Table "Minimum Ratio Between
+ * Peripheral Clock Frequency and CAN Bit Rate" (in Section "Arbitration and
+ * Matching Timing").
+ */
+//@{
+#define BP_CAN_MCR_MAXMB (0U) //!< Bit position for CAN_MCR_MAXMB.
+#define BM_CAN_MCR_MAXMB (0x0000007FU) //!< Bit mask for CAN_MCR_MAXMB.
+#define BS_CAN_MCR_MAXMB (7U) //!< Bit field size in bits for CAN_MCR_MAXMB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_MAXMB field.
+#define BR_CAN_MCR_MAXMB(x) (HW_CAN_MCR(x).B.MAXMB)
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_MAXMB.
+#define BF_CAN_MCR_MAXMB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_MAXMB), uint32_t) & BM_CAN_MCR_MAXMB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MAXMB field to a new value.
+#define BW_CAN_MCR_MAXMB(x, v) (HW_CAN_MCR_WR(x, (HW_CAN_MCR_RD(x) & ~BM_CAN_MCR_MAXMB) | BF_CAN_MCR_MAXMB(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field IDAM[9:8] (RW)
+ *
+ * This 2-bit field identifies the format of the Rx FIFO ID Filter Table
+ * elements. Note that all elements of the table are configured at the same time by this
+ * field (they are all the same format). See Section "Rx FIFO Structure". This
+ * field can be written only in Freeze mode because it is blocked by hardware in
+ * other modes.
+ *
+ * Values:
+ * - 00 - Format A: One full ID (standard and extended) per ID Filter Table
+ * element.
+ * - 01 - Format B: Two full standard IDs or two partial 14-bit (standard and
+ * extended) IDs per ID Filter Table element.
+ * - 10 - Format C: Four partial 8-bit Standard IDs per ID Filter Table element.
+ * - 11 - Format D: All frames rejected.
+ */
+//@{
+#define BP_CAN_MCR_IDAM (8U) //!< Bit position for CAN_MCR_IDAM.
+#define BM_CAN_MCR_IDAM (0x00000300U) //!< Bit mask for CAN_MCR_IDAM.
+#define BS_CAN_MCR_IDAM (2U) //!< Bit field size in bits for CAN_MCR_IDAM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_IDAM field.
+#define BR_CAN_MCR_IDAM(x) (HW_CAN_MCR(x).B.IDAM)
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_IDAM.
+#define BF_CAN_MCR_IDAM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_IDAM), uint32_t) & BM_CAN_MCR_IDAM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IDAM field to a new value.
+#define BW_CAN_MCR_IDAM(x, v) (HW_CAN_MCR_WR(x, (HW_CAN_MCR_RD(x) & ~BM_CAN_MCR_IDAM) | BF_CAN_MCR_IDAM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field AEN[12] (RW)
+ *
+ * This bit is supplied for backwards compatibility with legacy applications.
+ * When asserted, it enables the Tx abort mechanism. This mechanism guarantees a
+ * safe procedure for aborting a pending transmission, so that no frame is sent in
+ * the CAN bus without notification. This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes. When MCR[AEN] is asserted,
+ * only the abort mechanism (see Section "Transmission Abort Mechanism") must be
+ * used for updating Mailboxes configured for transmission. Writing the Abort code
+ * into Rx Mailboxes can cause unpredictable results when the MCR[AEN] is
+ * asserted.
+ *
+ * Values:
+ * - 0 - Abort disabled.
+ * - 1 - Abort enabled.
+ */
+//@{
+#define BP_CAN_MCR_AEN (12U) //!< Bit position for CAN_MCR_AEN.
+#define BM_CAN_MCR_AEN (0x00001000U) //!< Bit mask for CAN_MCR_AEN.
+#define BS_CAN_MCR_AEN (1U) //!< Bit field size in bits for CAN_MCR_AEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_AEN field.
+#define BR_CAN_MCR_AEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_AEN))
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_AEN.
+#define BF_CAN_MCR_AEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_AEN), uint32_t) & BM_CAN_MCR_AEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AEN field to a new value.
+#define BW_CAN_MCR_AEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_AEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field LPRIOEN[13] (RW)
+ *
+ * This bit is provided for backwards compatibility with legacy applications. It
+ * controls whether the local priority feature is enabled or not. It is used to
+ * expand the ID used during the arbitration process. With this expanded ID
+ * concept, the arbitration process is done based on the full 32-bit word, but the
+ * actual transmitted ID still has 11-bit for standard frames and 29-bit for
+ * extended frames. This bit can be written only in Freeze mode because it is blocked by
+ * hardware in other modes.
+ *
+ * Values:
+ * - 0 - Local Priority disabled.
+ * - 1 - Local Priority enabled.
+ */
+//@{
+#define BP_CAN_MCR_LPRIOEN (13U) //!< Bit position for CAN_MCR_LPRIOEN.
+#define BM_CAN_MCR_LPRIOEN (0x00002000U) //!< Bit mask for CAN_MCR_LPRIOEN.
+#define BS_CAN_MCR_LPRIOEN (1U) //!< Bit field size in bits for CAN_MCR_LPRIOEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_LPRIOEN field.
+#define BR_CAN_MCR_LPRIOEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPRIOEN))
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_LPRIOEN.
+#define BF_CAN_MCR_LPRIOEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_LPRIOEN), uint32_t) & BM_CAN_MCR_LPRIOEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LPRIOEN field to a new value.
+#define BW_CAN_MCR_LPRIOEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPRIOEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field IRMQ[16] (RW)
+ *
+ * This bit indicates whether Rx matching process will be based either on
+ * individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and
+ * RX15MASK, RXFGMASK. This bit can be written only in Freeze mode because it is
+ * blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0 - Individual Rx masking and queue feature are disabled. For backward
+ * compatibility with legacy applications, the reading of C/S word locks the MB
+ * even if it is EMPTY.
+ * - 1 - Individual Rx masking and queue feature are enabled.
+ */
+//@{
+#define BP_CAN_MCR_IRMQ (16U) //!< Bit position for CAN_MCR_IRMQ.
+#define BM_CAN_MCR_IRMQ (0x00010000U) //!< Bit mask for CAN_MCR_IRMQ.
+#define BS_CAN_MCR_IRMQ (1U) //!< Bit field size in bits for CAN_MCR_IRMQ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_IRMQ field.
+#define BR_CAN_MCR_IRMQ(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_IRMQ))
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_IRMQ.
+#define BF_CAN_MCR_IRMQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_IRMQ), uint32_t) & BM_CAN_MCR_IRMQ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IRMQ field to a new value.
+#define BW_CAN_MCR_IRMQ(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_IRMQ) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field SRXDIS[17] (RW)
+ *
+ * This bit defines whether FlexCAN is allowed to receive frames transmitted by
+ * itself. If this bit is asserted, frames transmitted by the module will not be
+ * stored in any MB, regardless if the MB is programmed with an ID that matches
+ * the transmitted frame, and no interrupt flag or interrupt signal will be
+ * generated due to the frame reception. This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0 - Self reception enabled.
+ * - 1 - Self reception disabled.
+ */
+//@{
+#define BP_CAN_MCR_SRXDIS (17U) //!< Bit position for CAN_MCR_SRXDIS.
+#define BM_CAN_MCR_SRXDIS (0x00020000U) //!< Bit mask for CAN_MCR_SRXDIS.
+#define BS_CAN_MCR_SRXDIS (1U) //!< Bit field size in bits for CAN_MCR_SRXDIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_SRXDIS field.
+#define BR_CAN_MCR_SRXDIS(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SRXDIS))
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_SRXDIS.
+#define BF_CAN_MCR_SRXDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_SRXDIS), uint32_t) & BM_CAN_MCR_SRXDIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SRXDIS field to a new value.
+#define BW_CAN_MCR_SRXDIS(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SRXDIS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field WAKSRC[19] (RW)
+ *
+ * This bit defines whether the integrated low-pass filter is applied to protect
+ * the Rx CAN input from spurious wake up. This bit can be written only in
+ * Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0 - FlexCAN uses the unfiltered Rx input to detect recessive to dominant
+ * edges on the CAN bus.
+ * - 1 - FlexCAN uses the filtered Rx input to detect recessive to dominant
+ * edges on the CAN bus.
+ */
+//@{
+#define BP_CAN_MCR_WAKSRC (19U) //!< Bit position for CAN_MCR_WAKSRC.
+#define BM_CAN_MCR_WAKSRC (0x00080000U) //!< Bit mask for CAN_MCR_WAKSRC.
+#define BS_CAN_MCR_WAKSRC (1U) //!< Bit field size in bits for CAN_MCR_WAKSRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_WAKSRC field.
+#define BR_CAN_MCR_WAKSRC(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKSRC))
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_WAKSRC.
+#define BF_CAN_MCR_WAKSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_WAKSRC), uint32_t) & BM_CAN_MCR_WAKSRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WAKSRC field to a new value.
+#define BW_CAN_MCR_WAKSRC(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKSRC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field LPMACK[20] (RO)
+ *
+ * This read-only bit indicates that FlexCAN is in a low-power mode (Disable
+ * mode , Stop mode ). A low-power mode cannot be entered until all current
+ * transmission or reception processes have finished, so the CPU can poll the LPMACK bit
+ * to know when FlexCAN has actually entered low power mode. LPMACK will be
+ * asserted within 180 CAN bits from the low-power mode request by the CPU, and
+ * negated within 2 CAN bits after the low-power mode request removal (see Section
+ * "Protocol Timing").
+ *
+ * Values:
+ * - 0 - FlexCAN is not in a low-power mode.
+ * - 1 - FlexCAN is in a low-power mode.
+ */
+//@{
+#define BP_CAN_MCR_LPMACK (20U) //!< Bit position for CAN_MCR_LPMACK.
+#define BM_CAN_MCR_LPMACK (0x00100000U) //!< Bit mask for CAN_MCR_LPMACK.
+#define BS_CAN_MCR_LPMACK (1U) //!< Bit field size in bits for CAN_MCR_LPMACK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_LPMACK field.
+#define BR_CAN_MCR_LPMACK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPMACK))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field WRNEN[21] (RW)
+ *
+ * When asserted, this bit enables the generation of the TWRNINT and RWRNINT
+ * flags in the Error and Status Register. If WRNEN is negated, the TWRNINT and
+ * RWRNINT flags will always be zero, independent of the values of the error
+ * counters, and no warning interrupt will ever be generated. This bit can be written
+ * only in Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0 - TWRNINT and RWRNINT bits are zero, independent of the values in the
+ * error counters.
+ * - 1 - TWRNINT and RWRNINT bits are set when the respective error counter
+ * transitions from less than 96 to greater than or equal to 96.
+ */
+//@{
+#define BP_CAN_MCR_WRNEN (21U) //!< Bit position for CAN_MCR_WRNEN.
+#define BM_CAN_MCR_WRNEN (0x00200000U) //!< Bit mask for CAN_MCR_WRNEN.
+#define BS_CAN_MCR_WRNEN (1U) //!< Bit field size in bits for CAN_MCR_WRNEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_WRNEN field.
+#define BR_CAN_MCR_WRNEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WRNEN))
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_WRNEN.
+#define BF_CAN_MCR_WRNEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_WRNEN), uint32_t) & BM_CAN_MCR_WRNEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WRNEN field to a new value.
+#define BW_CAN_MCR_WRNEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WRNEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field SLFWAK[22] (RW)
+ *
+ * This bit enables the Self Wake Up feature when FlexCAN is in a low-power mode
+ * other than Disable mode. When this feature is enabled, the FlexCAN module
+ * monitors the bus for wake up event, that is, a recessive-to-dominant transition.
+ * If a wake up event is detected during Stop mode, then FlexCAN generates, if
+ * enabled to do so, a Wake Up interrupt to the CPU so that it can exit Stop mode
+ * globally and FlexCAN can request to resume the clocks. When FlexCAN is in a
+ * low-power mode other than Disable mode, this bit cannot be written as it is
+ * blocked by hardware.
+ *
+ * Values:
+ * - 0 - FlexCAN Self Wake Up feature is disabled.
+ * - 1 - FlexCAN Self Wake Up feature is enabled.
+ */
+//@{
+#define BP_CAN_MCR_SLFWAK (22U) //!< Bit position for CAN_MCR_SLFWAK.
+#define BM_CAN_MCR_SLFWAK (0x00400000U) //!< Bit mask for CAN_MCR_SLFWAK.
+#define BS_CAN_MCR_SLFWAK (1U) //!< Bit field size in bits for CAN_MCR_SLFWAK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_SLFWAK field.
+#define BR_CAN_MCR_SLFWAK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SLFWAK))
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_SLFWAK.
+#define BF_CAN_MCR_SLFWAK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_SLFWAK), uint32_t) & BM_CAN_MCR_SLFWAK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SLFWAK field to a new value.
+#define BW_CAN_MCR_SLFWAK(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SLFWAK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field SUPV[23] (RW)
+ *
+ * This bit configures the FlexCAN to be either in Supervisor or User mode. The
+ * registers affected by this bit are marked as S/U in the Access Type column of
+ * the module memory map. Reset value of this bit is 1, so the affected registers
+ * start with Supervisor access allowance only . This bit can be written only in
+ * Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0 - FlexCAN is in User mode. Affected registers allow both Supervisor and
+ * Unrestricted accesses .
+ * - 1 - FlexCAN is in Supervisor mode. Affected registers allow only Supervisor
+ * access. Unrestricted access behaves as though the access was done to an
+ * unimplemented register location .
+ */
+//@{
+#define BP_CAN_MCR_SUPV (23U) //!< Bit position for CAN_MCR_SUPV.
+#define BM_CAN_MCR_SUPV (0x00800000U) //!< Bit mask for CAN_MCR_SUPV.
+#define BS_CAN_MCR_SUPV (1U) //!< Bit field size in bits for CAN_MCR_SUPV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_SUPV field.
+#define BR_CAN_MCR_SUPV(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SUPV))
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_SUPV.
+#define BF_CAN_MCR_SUPV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_SUPV), uint32_t) & BM_CAN_MCR_SUPV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SUPV field to a new value.
+#define BW_CAN_MCR_SUPV(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SUPV) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field FRZACK[24] (RO)
+ *
+ * This read-only bit indicates that FlexCAN is in Freeze mode and its prescaler
+ * is stopped. The Freeze mode request cannot be granted until current
+ * transmission or reception processes have finished. Therefore the software can poll the
+ * FRZACK bit to know when FlexCAN has actually entered Freeze mode. If Freeze
+ * Mode request is negated, then this bit is negated after the FlexCAN prescaler is
+ * running again. If Freeze mode is requested while FlexCAN is in a low power
+ * mode, then the FRZACK bit will be set only when the low-power mode is exited.
+ * See Section "Freeze Mode". FRZACK will be asserted within 178 CAN bits from the
+ * freeze mode request by the CPU, and negated within 2 CAN bits after the freeze
+ * mode request removal (see Section "Protocol Timing").
+ *
+ * Values:
+ * - 0 - FlexCAN not in Freeze mode, prescaler running.
+ * - 1 - FlexCAN in Freeze mode, prescaler stopped.
+ */
+//@{
+#define BP_CAN_MCR_FRZACK (24U) //!< Bit position for CAN_MCR_FRZACK.
+#define BM_CAN_MCR_FRZACK (0x01000000U) //!< Bit mask for CAN_MCR_FRZACK.
+#define BS_CAN_MCR_FRZACK (1U) //!< Bit field size in bits for CAN_MCR_FRZACK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_FRZACK field.
+#define BR_CAN_MCR_FRZACK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZACK))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field SOFTRST[25] (RW)
+ *
+ * When this bit is asserted, FlexCAN resets its internal state machines and
+ * some of the memory mapped registers. The following registers are reset: MCR
+ * (except the MDIS bit), TIMER , ECR, ESR1, ESR2, IMASK1, IMASK2, IFLAG1, IFLAG2 and
+ * CRCR. Configuration registers that control the interface to the CAN bus are
+ * not affected by soft reset. The following registers are unaffected: CTRL1,
+ * CTRL2, all RXIMR registers, RXMGMASK, RX14MASK, RX15MASK, RXFGMASK, RXFIR, all
+ * Message Buffers . The SOFTRST bit can be asserted directly by the CPU when it
+ * writes to the MCR Register, but it is also asserted when global soft reset is
+ * requested at MCU level . Because soft reset is synchronous and has to follow a
+ * request/acknowledge procedure across clock domains, it may take some time to
+ * fully propagate its effect. The SOFTRST bit remains asserted while reset is
+ * pending, and is automatically negated when reset completes. Therefore, software can
+ * poll this bit to know when the soft reset has completed. Soft reset cannot be
+ * applied while clocks are shut down in a low power mode. The module should be
+ * first removed from low power mode, and then soft reset can be applied.
+ *
+ * Values:
+ * - 0 - No reset request.
+ * - 1 - Resets the registers affected by soft reset.
+ */
+//@{
+#define BP_CAN_MCR_SOFTRST (25U) //!< Bit position for CAN_MCR_SOFTRST.
+#define BM_CAN_MCR_SOFTRST (0x02000000U) //!< Bit mask for CAN_MCR_SOFTRST.
+#define BS_CAN_MCR_SOFTRST (1U) //!< Bit field size in bits for CAN_MCR_SOFTRST.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_SOFTRST field.
+#define BR_CAN_MCR_SOFTRST(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SOFTRST))
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_SOFTRST.
+#define BF_CAN_MCR_SOFTRST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_SOFTRST), uint32_t) & BM_CAN_MCR_SOFTRST)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SOFTRST field to a new value.
+#define BW_CAN_MCR_SOFTRST(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SOFTRST) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field WAKMSK[26] (RW)
+ *
+ * This bit enables the Wake Up Interrupt generation under Self Wake Up
+ * mechanism.
+ *
+ * Values:
+ * - 0 - Wake Up Interrupt is disabled.
+ * - 1 - Wake Up Interrupt is enabled.
+ */
+//@{
+#define BP_CAN_MCR_WAKMSK (26U) //!< Bit position for CAN_MCR_WAKMSK.
+#define BM_CAN_MCR_WAKMSK (0x04000000U) //!< Bit mask for CAN_MCR_WAKMSK.
+#define BS_CAN_MCR_WAKMSK (1U) //!< Bit field size in bits for CAN_MCR_WAKMSK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_WAKMSK field.
+#define BR_CAN_MCR_WAKMSK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKMSK))
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_WAKMSK.
+#define BF_CAN_MCR_WAKMSK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_WAKMSK), uint32_t) & BM_CAN_MCR_WAKMSK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WAKMSK field to a new value.
+#define BW_CAN_MCR_WAKMSK(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKMSK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field NOTRDY[27] (RO)
+ *
+ * This read-only bit indicates that FlexCAN is either in Disable mode , Stop
+ * mode or Freeze mode. It is negated once FlexCAN has exited these modes.
+ *
+ * Values:
+ * - 0 - FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back
+ * mode.
+ * - 1 - FlexCAN module is either in Disable mode , Stop mode or Freeze mode.
+ */
+//@{
+#define BP_CAN_MCR_NOTRDY (27U) //!< Bit position for CAN_MCR_NOTRDY.
+#define BM_CAN_MCR_NOTRDY (0x08000000U) //!< Bit mask for CAN_MCR_NOTRDY.
+#define BS_CAN_MCR_NOTRDY (1U) //!< Bit field size in bits for CAN_MCR_NOTRDY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_NOTRDY field.
+#define BR_CAN_MCR_NOTRDY(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_NOTRDY))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field HALT[28] (RW)
+ *
+ * Assertion of this bit puts the FlexCAN module into Freeze mode. The CPU
+ * should clear it after initializing the Message Buffers and Control Register. No
+ * reception or transmission is performed by FlexCAN before this bit is cleared.
+ * Freeze mode cannot be entered while FlexCAN is in a low power mode.
+ *
+ * Values:
+ * - 0 - No Freeze mode request.
+ * - 1 - Enters Freeze mode if the FRZ bit is asserted.
+ */
+//@{
+#define BP_CAN_MCR_HALT (28U) //!< Bit position for CAN_MCR_HALT.
+#define BM_CAN_MCR_HALT (0x10000000U) //!< Bit mask for CAN_MCR_HALT.
+#define BS_CAN_MCR_HALT (1U) //!< Bit field size in bits for CAN_MCR_HALT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_HALT field.
+#define BR_CAN_MCR_HALT(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_HALT))
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_HALT.
+#define BF_CAN_MCR_HALT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_HALT), uint32_t) & BM_CAN_MCR_HALT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HALT field to a new value.
+#define BW_CAN_MCR_HALT(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_HALT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field RFEN[29] (RW)
+ *
+ * This bit controls whether the Rx FIFO feature is enabled or not. When RFEN is
+ * set, MBs 0 to 5 cannot be used for normal reception and transmission because
+ * the corresponding memory region (0x80-0xDC) is used by the FIFO engine as well
+ * as additional MBs (up to 32, depending on CTRL2[RFFN] setting) which are used
+ * as Rx FIFO ID Filter Table elements. RFEN also impacts the definition of the
+ * minimum number of peripheral clocks per CAN bit as described in the table
+ * "Minimum Ratio Between Peripheral Clock Frequency and CAN Bit Rate" (in section
+ * "Arbitration and Matching Timing"). This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0 - Rx FIFO not enabled.
+ * - 1 - Rx FIFO enabled.
+ */
+//@{
+#define BP_CAN_MCR_RFEN (29U) //!< Bit position for CAN_MCR_RFEN.
+#define BM_CAN_MCR_RFEN (0x20000000U) //!< Bit mask for CAN_MCR_RFEN.
+#define BS_CAN_MCR_RFEN (1U) //!< Bit field size in bits for CAN_MCR_RFEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_RFEN field.
+#define BR_CAN_MCR_RFEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_RFEN))
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_RFEN.
+#define BF_CAN_MCR_RFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_RFEN), uint32_t) & BM_CAN_MCR_RFEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RFEN field to a new value.
+#define BW_CAN_MCR_RFEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_RFEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field FRZ[30] (RW)
+ *
+ * The FRZ bit specifies the FlexCAN behavior when the HALT bit in the MCR
+ * Register is set or when Debug mode is requested at MCU level . When FRZ is
+ * asserted, FlexCAN is enabled to enter Freeze mode. Negation of this bit field causes
+ * FlexCAN to exit from Freeze mode.
+ *
+ * Values:
+ * - 0 - Not enabled to enter Freeze mode.
+ * - 1 - Enabled to enter Freeze mode.
+ */
+//@{
+#define BP_CAN_MCR_FRZ (30U) //!< Bit position for CAN_MCR_FRZ.
+#define BM_CAN_MCR_FRZ (0x40000000U) //!< Bit mask for CAN_MCR_FRZ.
+#define BS_CAN_MCR_FRZ (1U) //!< Bit field size in bits for CAN_MCR_FRZ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_FRZ field.
+#define BR_CAN_MCR_FRZ(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZ))
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_FRZ.
+#define BF_CAN_MCR_FRZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_FRZ), uint32_t) & BM_CAN_MCR_FRZ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FRZ field to a new value.
+#define BW_CAN_MCR_FRZ(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZ) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_MCR, field MDIS[31] (RW)
+ *
+ * This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN
+ * disables the clocks to the CAN Protocol Engine and Controller Host Interface
+ * sub-modules. This is the only bit within this register not affected by soft
+ * reset.
+ *
+ * Values:
+ * - 0 - Enable the FlexCAN module.
+ * - 1 - Disable the FlexCAN module.
+ */
+//@{
+#define BP_CAN_MCR_MDIS (31U) //!< Bit position for CAN_MCR_MDIS.
+#define BM_CAN_MCR_MDIS (0x80000000U) //!< Bit mask for CAN_MCR_MDIS.
+#define BS_CAN_MCR_MDIS (1U) //!< Bit field size in bits for CAN_MCR_MDIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_MCR_MDIS field.
+#define BR_CAN_MCR_MDIS(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_MDIS))
+#endif
+
+//! @brief Format value for bitfield CAN_MCR_MDIS.
+#define BF_CAN_MCR_MDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_MCR_MDIS), uint32_t) & BM_CAN_MCR_MDIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MDIS field to a new value.
+#define BW_CAN_MCR_MDIS(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_MDIS) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_CTRL1 - Control 1 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_CTRL1 - Control 1 register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is defined for specific FlexCAN control features related to the
+ * CAN bus, such as bit-rate, programmable sampling point within an Rx bit, Loop
+ * Back mode, Listen-Only mode, Bus Off recovery behavior and interrupt enabling
+ * (Bus-Off, Error, Warning). It also determines the Division Factor for the
+ * clock prescaler.
+ */
+typedef union _hw_can_ctrl1
+{
+ uint32_t U;
+ struct _hw_can_ctrl1_bitfields
+ {
+ uint32_t PROPSEG : 3; //!< [2:0] Propagation Segment
+ uint32_t LOM : 1; //!< [3] Listen-Only Mode
+ uint32_t LBUF : 1; //!< [4] Lowest Buffer Transmitted First
+ uint32_t TSYN : 1; //!< [5] Timer Sync
+ uint32_t BOFFREC : 1; //!< [6] Bus Off Recovery
+ uint32_t SMP : 1; //!< [7] CAN Bit Sampling
+ uint32_t RESERVED0 : 2; //!< [9:8]
+ uint32_t RWRNMSK : 1; //!< [10] Rx Warning Interrupt Mask
+ uint32_t TWRNMSK : 1; //!< [11] Tx Warning Interrupt Mask
+ uint32_t LPB : 1; //!< [12] Loop Back Mode
+ uint32_t CLKSRC : 1; //!< [13] CAN Engine Clock Source
+ uint32_t ERRMSK : 1; //!< [14] Error Mask
+ uint32_t BOFFMSK : 1; //!< [15] Bus Off Mask
+ uint32_t PSEG2 : 3; //!< [18:16] Phase Segment 2
+ uint32_t PSEG1 : 3; //!< [21:19] Phase Segment 1
+ uint32_t RJW : 2; //!< [23:22] Resync Jump Width
+ uint32_t PRESDIV : 8; //!< [31:24] Prescaler Division Factor
+ } B;
+} hw_can_ctrl1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_CTRL1 register
+ */
+//@{
+#define HW_CAN_CTRL1_ADDR(x) (REGS_CAN_BASE(x) + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_CTRL1(x) (*(__IO hw_can_ctrl1_t *) HW_CAN_CTRL1_ADDR(x))
+#define HW_CAN_CTRL1_RD(x) (HW_CAN_CTRL1(x).U)
+#define HW_CAN_CTRL1_WR(x, v) (HW_CAN_CTRL1(x).U = (v))
+#define HW_CAN_CTRL1_SET(x, v) (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) | (v)))
+#define HW_CAN_CTRL1_CLR(x, v) (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) & ~(v)))
+#define HW_CAN_CTRL1_TOG(x, v) (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_CTRL1 bitfields
+ */
+
+/*!
+ * @name Register CAN_CTRL1, field PROPSEG[2:0] (RW)
+ *
+ * This 3-bit field defines the length of the Propagation Segment in the bit
+ * time. The valid programmable values are 0-7. This field can be written only in
+ * Freeze mode because it is blocked by hardware in other modes. Propagation
+ * Segment Time = (PROPSEG + 1) * Time-Quanta. Time-Quantum = one Sclock period.
+ */
+//@{
+#define BP_CAN_CTRL1_PROPSEG (0U) //!< Bit position for CAN_CTRL1_PROPSEG.
+#define BM_CAN_CTRL1_PROPSEG (0x00000007U) //!< Bit mask for CAN_CTRL1_PROPSEG.
+#define BS_CAN_CTRL1_PROPSEG (3U) //!< Bit field size in bits for CAN_CTRL1_PROPSEG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_PROPSEG field.
+#define BR_CAN_CTRL1_PROPSEG(x) (HW_CAN_CTRL1(x).B.PROPSEG)
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_PROPSEG.
+#define BF_CAN_CTRL1_PROPSEG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_PROPSEG), uint32_t) & BM_CAN_CTRL1_PROPSEG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PROPSEG field to a new value.
+#define BW_CAN_CTRL1_PROPSEG(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PROPSEG) | BF_CAN_CTRL1_PROPSEG(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field LOM[3] (RW)
+ *
+ * This bit configures FlexCAN to operate in Listen-Only mode. In this mode,
+ * transmission is disabled, all error counters are frozen and the module operates
+ * in a CAN Error Passive mode. Only messages acknowledged by another CAN station
+ * will be received. If FlexCAN detects a message that has not been acknowledged,
+ * it will flag a BIT0 error without changing the REC, as if it was trying to
+ * acknowledge the message. Listen-Only mode acknowledgement can be obtained by the
+ * state of ESR1[FLTCONF] field which is Passive Error when Listen-Only mode is
+ * entered. There can be some delay between the Listen-Only mode request and
+ * acknowledge. This bit can be written only in Freeze mode because it is blocked by
+ * hardware in other modes.
+ *
+ * Values:
+ * - 0 - Listen-Only mode is deactivated.
+ * - 1 - FlexCAN module operates in Listen-Only mode.
+ */
+//@{
+#define BP_CAN_CTRL1_LOM (3U) //!< Bit position for CAN_CTRL1_LOM.
+#define BM_CAN_CTRL1_LOM (0x00000008U) //!< Bit mask for CAN_CTRL1_LOM.
+#define BS_CAN_CTRL1_LOM (1U) //!< Bit field size in bits for CAN_CTRL1_LOM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_LOM field.
+#define BR_CAN_CTRL1_LOM(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LOM))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_LOM.
+#define BF_CAN_CTRL1_LOM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_LOM), uint32_t) & BM_CAN_CTRL1_LOM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LOM field to a new value.
+#define BW_CAN_CTRL1_LOM(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LOM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field LBUF[4] (RW)
+ *
+ * This bit defines the ordering mechanism for Message Buffer transmission. When
+ * asserted, the LPRIOEN bit does not affect the priority arbitration. This bit
+ * can be written only in Freeze mode because it is blocked by hardware in other
+ * modes.
+ *
+ * Values:
+ * - 0 - Buffer with highest priority is transmitted first.
+ * - 1 - Lowest number buffer is transmitted first.
+ */
+//@{
+#define BP_CAN_CTRL1_LBUF (4U) //!< Bit position for CAN_CTRL1_LBUF.
+#define BM_CAN_CTRL1_LBUF (0x00000010U) //!< Bit mask for CAN_CTRL1_LBUF.
+#define BS_CAN_CTRL1_LBUF (1U) //!< Bit field size in bits for CAN_CTRL1_LBUF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_LBUF field.
+#define BR_CAN_CTRL1_LBUF(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LBUF))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_LBUF.
+#define BF_CAN_CTRL1_LBUF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_LBUF), uint32_t) & BM_CAN_CTRL1_LBUF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LBUF field to a new value.
+#define BW_CAN_CTRL1_LBUF(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LBUF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field TSYN[5] (RW)
+ *
+ * This bit enables a mechanism that resets the free-running timer each time a
+ * message is received in Message Buffer 0. This feature provides means to
+ * synchronize multiple FlexCAN stations with a special "SYNC" message, that is, global
+ * network time. If the RFEN bit in MCR is set (Rx FIFO enabled), the first
+ * available Mailbox, according to CTRL2[RFFN] setting, is used for timer
+ * synchronization instead of MB0. This bit can be written only in Freeze mode because it is
+ * blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0 - Timer Sync feature disabled
+ * - 1 - Timer Sync feature enabled
+ */
+//@{
+#define BP_CAN_CTRL1_TSYN (5U) //!< Bit position for CAN_CTRL1_TSYN.
+#define BM_CAN_CTRL1_TSYN (0x00000020U) //!< Bit mask for CAN_CTRL1_TSYN.
+#define BS_CAN_CTRL1_TSYN (1U) //!< Bit field size in bits for CAN_CTRL1_TSYN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_TSYN field.
+#define BR_CAN_CTRL1_TSYN(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TSYN))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_TSYN.
+#define BF_CAN_CTRL1_TSYN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_TSYN), uint32_t) & BM_CAN_CTRL1_TSYN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TSYN field to a new value.
+#define BW_CAN_CTRL1_TSYN(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TSYN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field BOFFREC[6] (RW)
+ *
+ * This bit defines how FlexCAN recovers from Bus Off state. If this bit is
+ * negated, automatic recovering from Bus Off state occurs according to the CAN
+ * Specification 2.0B. If the bit is asserted, automatic recovering from Bus Off is
+ * disabled and the module remains in Bus Off state until the bit is negated by the
+ * user. If the negation occurs before 128 sequences of 11 recessive bits are
+ * detected on the CAN bus, then Bus Off recovery happens as if the BOFFREC bit had
+ * never been asserted. If the negation occurs after 128 sequences of 11
+ * recessive bits occurred, then FlexCAN will re-synchronize to the bus by waiting for
+ * 11 recessive bits before joining the bus. After negation, the BOFFREC bit can
+ * be re-asserted again during Bus Off, but it will be effective only the next
+ * time the module enters Bus Off. If BOFFREC was negated when the module entered
+ * Bus Off, asserting it during Bus Off will not be effective for the current Bus
+ * Off recovery.
+ *
+ * Values:
+ * - 0 - Automatic recovering from Bus Off state enabled, according to CAN Spec
+ * 2.0 part B.
+ * - 1 - Automatic recovering from Bus Off state disabled.
+ */
+//@{
+#define BP_CAN_CTRL1_BOFFREC (6U) //!< Bit position for CAN_CTRL1_BOFFREC.
+#define BM_CAN_CTRL1_BOFFREC (0x00000040U) //!< Bit mask for CAN_CTRL1_BOFFREC.
+#define BS_CAN_CTRL1_BOFFREC (1U) //!< Bit field size in bits for CAN_CTRL1_BOFFREC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_BOFFREC field.
+#define BR_CAN_CTRL1_BOFFREC(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFREC))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_BOFFREC.
+#define BF_CAN_CTRL1_BOFFREC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_BOFFREC), uint32_t) & BM_CAN_CTRL1_BOFFREC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BOFFREC field to a new value.
+#define BW_CAN_CTRL1_BOFFREC(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFREC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field SMP[7] (RW)
+ *
+ * This bit defines the sampling mode of CAN bits at the Rx input. This bit can
+ * be written only in Freeze mode because it is blocked by hardware in other
+ * modes.
+ *
+ * Values:
+ * - 0 - Just one sample is used to determine the bit value.
+ * - 1 - Three samples are used to determine the value of the received bit: the
+ * regular one (sample point) and 2 preceding samples; a majority rule is
+ * used.
+ */
+//@{
+#define BP_CAN_CTRL1_SMP (7U) //!< Bit position for CAN_CTRL1_SMP.
+#define BM_CAN_CTRL1_SMP (0x00000080U) //!< Bit mask for CAN_CTRL1_SMP.
+#define BS_CAN_CTRL1_SMP (1U) //!< Bit field size in bits for CAN_CTRL1_SMP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_SMP field.
+#define BR_CAN_CTRL1_SMP(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_SMP))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_SMP.
+#define BF_CAN_CTRL1_SMP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_SMP), uint32_t) & BM_CAN_CTRL1_SMP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SMP field to a new value.
+#define BW_CAN_CTRL1_SMP(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_SMP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field RWRNMSK[10] (RW)
+ *
+ * This bit provides a mask for the Rx Warning Interrupt associated with the
+ * RWRNINT flag in the Error and Status Register. This bit is read as zero when
+ * MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
+ * asserted.
+ *
+ * Values:
+ * - 0 - Rx Warning Interrupt disabled.
+ * - 1 - Rx Warning Interrupt enabled.
+ */
+//@{
+#define BP_CAN_CTRL1_RWRNMSK (10U) //!< Bit position for CAN_CTRL1_RWRNMSK.
+#define BM_CAN_CTRL1_RWRNMSK (0x00000400U) //!< Bit mask for CAN_CTRL1_RWRNMSK.
+#define BS_CAN_CTRL1_RWRNMSK (1U) //!< Bit field size in bits for CAN_CTRL1_RWRNMSK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_RWRNMSK field.
+#define BR_CAN_CTRL1_RWRNMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_RWRNMSK))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_RWRNMSK.
+#define BF_CAN_CTRL1_RWRNMSK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_RWRNMSK), uint32_t) & BM_CAN_CTRL1_RWRNMSK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RWRNMSK field to a new value.
+#define BW_CAN_CTRL1_RWRNMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_RWRNMSK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field TWRNMSK[11] (RW)
+ *
+ * This bit provides a mask for the Tx Warning Interrupt associated with the
+ * TWRNINT flag in the Error and Status Register. This bit is read as zero when
+ * MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
+ * asserted.
+ *
+ * Values:
+ * - 0 - Tx Warning Interrupt disabled.
+ * - 1 - Tx Warning Interrupt enabled.
+ */
+//@{
+#define BP_CAN_CTRL1_TWRNMSK (11U) //!< Bit position for CAN_CTRL1_TWRNMSK.
+#define BM_CAN_CTRL1_TWRNMSK (0x00000800U) //!< Bit mask for CAN_CTRL1_TWRNMSK.
+#define BS_CAN_CTRL1_TWRNMSK (1U) //!< Bit field size in bits for CAN_CTRL1_TWRNMSK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_TWRNMSK field.
+#define BR_CAN_CTRL1_TWRNMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TWRNMSK))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_TWRNMSK.
+#define BF_CAN_CTRL1_TWRNMSK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_TWRNMSK), uint32_t) & BM_CAN_CTRL1_TWRNMSK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TWRNMSK field to a new value.
+#define BW_CAN_CTRL1_TWRNMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TWRNMSK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field LPB[12] (RW)
+ *
+ * This bit configures FlexCAN to operate in Loop-Back mode. In this mode,
+ * FlexCAN performs an internal loop back that can be used for self test operation.
+ * The bit stream output of the transmitter is fed back internally to the receiver
+ * input. The Rx CAN input pin is ignored and the Tx CAN output goes to the
+ * recessive state (logic 1). FlexCAN behaves as it normally does when transmitting,
+ * and treats its own transmitted message as a message received from a remote
+ * node. In this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN
+ * frame acknowledge field, generating an internal acknowledge bit to ensure proper
+ * reception of its own message. Both transmit and receive interrupts are
+ * generated. This bit can be written only in Freeze mode because it is blocked by
+ * hardware in other modes. In this mode, the MCR[SRXDIS] cannot be asserted because
+ * this will impede the self reception of a transmitted message.
+ *
+ * Values:
+ * - 0 - Loop Back disabled.
+ * - 1 - Loop Back enabled.
+ */
+//@{
+#define BP_CAN_CTRL1_LPB (12U) //!< Bit position for CAN_CTRL1_LPB.
+#define BM_CAN_CTRL1_LPB (0x00001000U) //!< Bit mask for CAN_CTRL1_LPB.
+#define BS_CAN_CTRL1_LPB (1U) //!< Bit field size in bits for CAN_CTRL1_LPB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_LPB field.
+#define BR_CAN_CTRL1_LPB(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LPB))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_LPB.
+#define BF_CAN_CTRL1_LPB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_LPB), uint32_t) & BM_CAN_CTRL1_LPB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LPB field to a new value.
+#define BW_CAN_CTRL1_LPB(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LPB) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field CLKSRC[13] (RW)
+ *
+ * This bit selects the clock source to the CAN Protocol Engine (PE) to be
+ * either the peripheral clock (driven by the PLL) or the crystal oscillator clock.
+ * The selected clock is the one fed to the prescaler to generate the Serial Clock
+ * (Sclock). In order to guarantee reliable operation, this bit can be written
+ * only in Disable mode because it is blocked by hardware in other modes. See
+ * Section "Protocol Timing".
+ *
+ * Values:
+ * - 0 - The CAN engine clock source is the oscillator clock. Under this
+ * condition, the oscillator clock frequency must be lower than the bus clock.
+ * - 1 - The CAN engine clock source is the peripheral clock.
+ */
+//@{
+#define BP_CAN_CTRL1_CLKSRC (13U) //!< Bit position for CAN_CTRL1_CLKSRC.
+#define BM_CAN_CTRL1_CLKSRC (0x00002000U) //!< Bit mask for CAN_CTRL1_CLKSRC.
+#define BS_CAN_CTRL1_CLKSRC (1U) //!< Bit field size in bits for CAN_CTRL1_CLKSRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_CLKSRC field.
+#define BR_CAN_CTRL1_CLKSRC(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_CLKSRC))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_CLKSRC.
+#define BF_CAN_CTRL1_CLKSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_CLKSRC), uint32_t) & BM_CAN_CTRL1_CLKSRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLKSRC field to a new value.
+#define BW_CAN_CTRL1_CLKSRC(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_CLKSRC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field ERRMSK[14] (RW)
+ *
+ * This bit provides a mask for the Error Interrupt.
+ *
+ * Values:
+ * - 0 - Error interrupt disabled.
+ * - 1 - Error interrupt enabled.
+ */
+//@{
+#define BP_CAN_CTRL1_ERRMSK (14U) //!< Bit position for CAN_CTRL1_ERRMSK.
+#define BM_CAN_CTRL1_ERRMSK (0x00004000U) //!< Bit mask for CAN_CTRL1_ERRMSK.
+#define BS_CAN_CTRL1_ERRMSK (1U) //!< Bit field size in bits for CAN_CTRL1_ERRMSK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_ERRMSK field.
+#define BR_CAN_CTRL1_ERRMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_ERRMSK))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_ERRMSK.
+#define BF_CAN_CTRL1_ERRMSK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_ERRMSK), uint32_t) & BM_CAN_CTRL1_ERRMSK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERRMSK field to a new value.
+#define BW_CAN_CTRL1_ERRMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_ERRMSK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field BOFFMSK[15] (RW)
+ *
+ * This bit provides a mask for the Bus Off Interrupt.
+ *
+ * Values:
+ * - 0 - Bus Off interrupt disabled.
+ * - 1 - Bus Off interrupt enabled.
+ */
+//@{
+#define BP_CAN_CTRL1_BOFFMSK (15U) //!< Bit position for CAN_CTRL1_BOFFMSK.
+#define BM_CAN_CTRL1_BOFFMSK (0x00008000U) //!< Bit mask for CAN_CTRL1_BOFFMSK.
+#define BS_CAN_CTRL1_BOFFMSK (1U) //!< Bit field size in bits for CAN_CTRL1_BOFFMSK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_BOFFMSK field.
+#define BR_CAN_CTRL1_BOFFMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFMSK))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_BOFFMSK.
+#define BF_CAN_CTRL1_BOFFMSK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_BOFFMSK), uint32_t) & BM_CAN_CTRL1_BOFFMSK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BOFFMSK field to a new value.
+#define BW_CAN_CTRL1_BOFFMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFMSK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field PSEG2[18:16] (RW)
+ *
+ * This 3-bit field defines the length of Phase Buffer Segment 2 in the bit
+ * time. The valid programmable values are 1-7. This field can be written only in
+ * Freeze mode because it is blocked by hardware in other modes. Phase Buffer
+ * Segment 2 = (PSEG2 + 1) * Time-Quanta.
+ */
+//@{
+#define BP_CAN_CTRL1_PSEG2 (16U) //!< Bit position for CAN_CTRL1_PSEG2.
+#define BM_CAN_CTRL1_PSEG2 (0x00070000U) //!< Bit mask for CAN_CTRL1_PSEG2.
+#define BS_CAN_CTRL1_PSEG2 (3U) //!< Bit field size in bits for CAN_CTRL1_PSEG2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_PSEG2 field.
+#define BR_CAN_CTRL1_PSEG2(x) (HW_CAN_CTRL1(x).B.PSEG2)
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_PSEG2.
+#define BF_CAN_CTRL1_PSEG2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_PSEG2), uint32_t) & BM_CAN_CTRL1_PSEG2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PSEG2 field to a new value.
+#define BW_CAN_CTRL1_PSEG2(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PSEG2) | BF_CAN_CTRL1_PSEG2(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field PSEG1[21:19] (RW)
+ *
+ * This 3-bit field defines the length of Phase Buffer Segment 1 in the bit
+ * time. The valid programmable values are 0-7. This field can be written only in
+ * Freeze mode because it is blocked by hardware in other modes. Phase Buffer
+ * Segment 1 = (PSEG1 + 1) * Time-Quanta.
+ */
+//@{
+#define BP_CAN_CTRL1_PSEG1 (19U) //!< Bit position for CAN_CTRL1_PSEG1.
+#define BM_CAN_CTRL1_PSEG1 (0x00380000U) //!< Bit mask for CAN_CTRL1_PSEG1.
+#define BS_CAN_CTRL1_PSEG1 (3U) //!< Bit field size in bits for CAN_CTRL1_PSEG1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_PSEG1 field.
+#define BR_CAN_CTRL1_PSEG1(x) (HW_CAN_CTRL1(x).B.PSEG1)
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_PSEG1.
+#define BF_CAN_CTRL1_PSEG1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_PSEG1), uint32_t) & BM_CAN_CTRL1_PSEG1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PSEG1 field to a new value.
+#define BW_CAN_CTRL1_PSEG1(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PSEG1) | BF_CAN_CTRL1_PSEG1(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field RJW[23:22] (RW)
+ *
+ * This 2-bit field defines the maximum number of time quanta that a bit time
+ * can be changed by one re-synchronization. One time quantum is equal to the
+ * Sclock period. The valid programmable values are 0-3. This field can be written
+ * only in Freeze mode because it is blocked by hardware in other modes. Resync Jump
+ * Width = RJW + 1.
+ */
+//@{
+#define BP_CAN_CTRL1_RJW (22U) //!< Bit position for CAN_CTRL1_RJW.
+#define BM_CAN_CTRL1_RJW (0x00C00000U) //!< Bit mask for CAN_CTRL1_RJW.
+#define BS_CAN_CTRL1_RJW (2U) //!< Bit field size in bits for CAN_CTRL1_RJW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_RJW field.
+#define BR_CAN_CTRL1_RJW(x) (HW_CAN_CTRL1(x).B.RJW)
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_RJW.
+#define BF_CAN_CTRL1_RJW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_RJW), uint32_t) & BM_CAN_CTRL1_RJW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RJW field to a new value.
+#define BW_CAN_CTRL1_RJW(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_RJW) | BF_CAN_CTRL1_RJW(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL1, field PRESDIV[31:24] (RW)
+ *
+ * This 8-bit field defines the ratio between the PE clock frequency and the
+ * Serial Clock (Sclock) frequency. The Sclock period defines the time quantum of
+ * the CAN protocol. For the reset value, the Sclock frequency is equal to the PE
+ * clock frequency. The Maximum value of this field is 0xFF, that gives a minimum
+ * Sclock frequency equal to the PE clock frequency divided by 256. See Section
+ * "Protocol Timing". This field can be written only in Freeze mode because it is
+ * blocked by hardware in other modes. Sclock frequency = PE clock frequency /
+ * (PRESDIV + 1)
+ */
+//@{
+#define BP_CAN_CTRL1_PRESDIV (24U) //!< Bit position for CAN_CTRL1_PRESDIV.
+#define BM_CAN_CTRL1_PRESDIV (0xFF000000U) //!< Bit mask for CAN_CTRL1_PRESDIV.
+#define BS_CAN_CTRL1_PRESDIV (8U) //!< Bit field size in bits for CAN_CTRL1_PRESDIV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL1_PRESDIV field.
+#define BR_CAN_CTRL1_PRESDIV(x) (HW_CAN_CTRL1(x).B.PRESDIV)
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL1_PRESDIV.
+#define BF_CAN_CTRL1_PRESDIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL1_PRESDIV), uint32_t) & BM_CAN_CTRL1_PRESDIV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PRESDIV field to a new value.
+#define BW_CAN_CTRL1_PRESDIV(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PRESDIV) | BF_CAN_CTRL1_PRESDIV(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_TIMER - Free Running Timer
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_TIMER - Free Running Timer (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register represents a 16-bit free running counter that can be read and
+ * written by the CPU. The timer starts from 0x0 after Reset, counts linearly to
+ * 0xFFFF, and wraps around. The timer is clocked by the FlexCAN bit-clock, which
+ * defines the baud rate on the CAN bus. During a message transmission/reception,
+ * it increments by one for each bit that is received or transmitted. When there
+ * is no message on the bus, it counts using the previously programmed baud
+ * rate. The timer is not incremented during Disable , Stop, and Freeze modes. The
+ * timer value is captured when the second bit of the identifier field of any frame
+ * is on the CAN bus. This captured value is written into the Time Stamp entry
+ * in a message buffer after a successful reception or transmission of a message.
+ * If bit CTRL1[TSYN] is asserted, the Timer is reset whenever a message is
+ * received in the first available Mailbox, according to CTRL2[RFFN] setting. The CPU
+ * can write to this register anytime. However, if the write occurs at the same
+ * time that the Timer is being reset by a reception in the first Mailbox, then
+ * the write value is discarded. Reading this register affects the Mailbox
+ * Unlocking procedure; see Section "Mailbox Lock Mechanism".
+ */
+typedef union _hw_can_timer
+{
+ uint32_t U;
+ struct _hw_can_timer_bitfields
+ {
+ uint32_t TIMER : 16; //!< [15:0] Timer Value
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_can_timer_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_TIMER register
+ */
+//@{
+#define HW_CAN_TIMER_ADDR(x) (REGS_CAN_BASE(x) + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_TIMER(x) (*(__IO hw_can_timer_t *) HW_CAN_TIMER_ADDR(x))
+#define HW_CAN_TIMER_RD(x) (HW_CAN_TIMER(x).U)
+#define HW_CAN_TIMER_WR(x, v) (HW_CAN_TIMER(x).U = (v))
+#define HW_CAN_TIMER_SET(x, v) (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) | (v)))
+#define HW_CAN_TIMER_CLR(x, v) (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) & ~(v)))
+#define HW_CAN_TIMER_TOG(x, v) (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_TIMER bitfields
+ */
+
+/*!
+ * @name Register CAN_TIMER, field TIMER[15:0] (RW)
+ *
+ * Contains the free-running counter value.
+ */
+//@{
+#define BP_CAN_TIMER_TIMER (0U) //!< Bit position for CAN_TIMER_TIMER.
+#define BM_CAN_TIMER_TIMER (0x0000FFFFU) //!< Bit mask for CAN_TIMER_TIMER.
+#define BS_CAN_TIMER_TIMER (16U) //!< Bit field size in bits for CAN_TIMER_TIMER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_TIMER_TIMER field.
+#define BR_CAN_TIMER_TIMER(x) (HW_CAN_TIMER(x).B.TIMER)
+#endif
+
+//! @brief Format value for bitfield CAN_TIMER_TIMER.
+#define BF_CAN_TIMER_TIMER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_TIMER_TIMER), uint32_t) & BM_CAN_TIMER_TIMER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TIMER field to a new value.
+#define BW_CAN_TIMER_TIMER(x, v) (HW_CAN_TIMER_WR(x, (HW_CAN_TIMER_RD(x) & ~BM_CAN_TIMER_TIMER) | BF_CAN_TIMER_TIMER(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. RXMGMASK is provided for legacy application
+ * support. When the MCR[IRMQ] bit is negated, RXMGMASK is always in effect. When
+ * the MCR[IRMQ] bit is asserted, RXMGMASK has no effect. RXMGMASK is used to
+ * mask the filter fields of all Rx MBs, excluding MBs 14-15, which have individual
+ * mask registers. This register can only be written in Freeze mode as it is
+ * blocked by hardware in other modes.
+ */
+typedef union _hw_can_rxmgmask
+{
+ uint32_t U;
+ struct _hw_can_rxmgmask_bitfields
+ {
+ uint32_t MG : 32; //!< [31:0] Rx Mailboxes Global Mask Bits
+ } B;
+} hw_can_rxmgmask_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_RXMGMASK register
+ */
+//@{
+#define HW_CAN_RXMGMASK_ADDR(x) (REGS_CAN_BASE(x) + 0x10U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_RXMGMASK(x) (*(__IO hw_can_rxmgmask_t *) HW_CAN_RXMGMASK_ADDR(x))
+#define HW_CAN_RXMGMASK_RD(x) (HW_CAN_RXMGMASK(x).U)
+#define HW_CAN_RXMGMASK_WR(x, v) (HW_CAN_RXMGMASK(x).U = (v))
+#define HW_CAN_RXMGMASK_SET(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) | (v)))
+#define HW_CAN_RXMGMASK_CLR(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) & ~(v)))
+#define HW_CAN_RXMGMASK_TOG(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_RXMGMASK bitfields
+ */
+
+/*!
+ * @name Register CAN_RXMGMASK, field MG[31:0] (RW)
+ *
+ * These bits mask the Mailbox filter bits. Note that the alignment with the ID
+ * word of the Mailbox is not perfect as the two most significant MG bits affect
+ * the fields RTR and IDE, which are located in the Control and Status word of
+ * the Mailbox. The following table shows in detail which MG bits mask each Mailbox
+ * filter field. SMB[RTR] RTR bit of the Incoming Frame. It is saved into an
+ * auxiliary MB called Rx Serial Message Buffer (Rx SMB). CTRL2[RRS] CTRL2[EACEN]
+ * Mailbox filter fields MB[RTR] MB[IDE] MB[ID] Reserved 0 - 0 note If the
+ * CTRL2[EACEN] bit is negated, the RTR bit of Mailbox is never compared with the RTR bit
+ * of the incoming frame. note If the CTRL2[EACEN] bit is negated, the IDE bit
+ * of Mailbox is always compared with the IDE bit of the incoming frame. MG[28:0]
+ * MG[31:29] 0 - 1 MG[31] MG[30] MG[28:0] MG[29] 1 0 - - - - MG[31:0] 1 1 0 - -
+ * MG[28:0] MG[31:29] 1 1 1 MG[31] MG[30] MG[28:0] MG[29]
+ *
+ * Values:
+ * - 0 - The corresponding bit in the filter is "don't care."
+ * - 1 - The corresponding bit in the filter is checked.
+ */
+//@{
+#define BP_CAN_RXMGMASK_MG (0U) //!< Bit position for CAN_RXMGMASK_MG.
+#define BM_CAN_RXMGMASK_MG (0xFFFFFFFFU) //!< Bit mask for CAN_RXMGMASK_MG.
+#define BS_CAN_RXMGMASK_MG (32U) //!< Bit field size in bits for CAN_RXMGMASK_MG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_RXMGMASK_MG field.
+#define BR_CAN_RXMGMASK_MG(x) (HW_CAN_RXMGMASK(x).U)
+#endif
+
+//! @brief Format value for bitfield CAN_RXMGMASK_MG.
+#define BF_CAN_RXMGMASK_MG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_RXMGMASK_MG), uint32_t) & BM_CAN_RXMGMASK_MG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MG field to a new value.
+#define BW_CAN_RXMGMASK_MG(x, v) (HW_CAN_RXMGMASK_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_RX14MASK - Rx 14 Mask register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_RX14MASK - Rx 14 Mask register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. RX14MASK is provided for legacy application
+ * support. When the MCR[IRMQ] bit is asserted, RX14MASK has no effect. RX14MASK
+ * is used to mask the filter fields of Message Buffer 14. This register can only
+ * be programmed while the module is in Freeze mode as it is blocked by hardware
+ * in other modes.
+ */
+typedef union _hw_can_rx14mask
+{
+ uint32_t U;
+ struct _hw_can_rx14mask_bitfields
+ {
+ uint32_t RX14M : 32; //!< [31:0] Rx Buffer 14 Mask Bits
+ } B;
+} hw_can_rx14mask_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_RX14MASK register
+ */
+//@{
+#define HW_CAN_RX14MASK_ADDR(x) (REGS_CAN_BASE(x) + 0x14U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_RX14MASK(x) (*(__IO hw_can_rx14mask_t *) HW_CAN_RX14MASK_ADDR(x))
+#define HW_CAN_RX14MASK_RD(x) (HW_CAN_RX14MASK(x).U)
+#define HW_CAN_RX14MASK_WR(x, v) (HW_CAN_RX14MASK(x).U = (v))
+#define HW_CAN_RX14MASK_SET(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) | (v)))
+#define HW_CAN_RX14MASK_CLR(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) & ~(v)))
+#define HW_CAN_RX14MASK_TOG(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_RX14MASK bitfields
+ */
+
+/*!
+ * @name Register CAN_RX14MASK, field RX14M[31:0] (RW)
+ *
+ * Each mask bit masks the corresponding Mailbox 14 filter field in the same way
+ * that RXMGMASK masks other Mailboxes' filters. See the description of the
+ * CAN_RXMGMASK register.
+ *
+ * Values:
+ * - 0 - The corresponding bit in the filter is "don't care."
+ * - 1 - The corresponding bit in the filter is checked.
+ */
+//@{
+#define BP_CAN_RX14MASK_RX14M (0U) //!< Bit position for CAN_RX14MASK_RX14M.
+#define BM_CAN_RX14MASK_RX14M (0xFFFFFFFFU) //!< Bit mask for CAN_RX14MASK_RX14M.
+#define BS_CAN_RX14MASK_RX14M (32U) //!< Bit field size in bits for CAN_RX14MASK_RX14M.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_RX14MASK_RX14M field.
+#define BR_CAN_RX14MASK_RX14M(x) (HW_CAN_RX14MASK(x).U)
+#endif
+
+//! @brief Format value for bitfield CAN_RX14MASK_RX14M.
+#define BF_CAN_RX14MASK_RX14M(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_RX14MASK_RX14M), uint32_t) & BM_CAN_RX14MASK_RX14M)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RX14M field to a new value.
+#define BW_CAN_RX14MASK_RX14M(x, v) (HW_CAN_RX14MASK_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_RX15MASK - Rx 15 Mask register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_RX15MASK - Rx 15 Mask register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. RX15MASK is provided for legacy application
+ * support. When the MCR[IRMQ] bit is asserted, RX15MASK has no effect. RX15MASK
+ * is used to mask the filter fields of Message Buffer 15. This register can be
+ * programmed only while the module is in Freeze mode because it is blocked by
+ * hardware in other modes.
+ */
+typedef union _hw_can_rx15mask
+{
+ uint32_t U;
+ struct _hw_can_rx15mask_bitfields
+ {
+ uint32_t RX15M : 32; //!< [31:0] Rx Buffer 15 Mask Bits
+ } B;
+} hw_can_rx15mask_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_RX15MASK register
+ */
+//@{
+#define HW_CAN_RX15MASK_ADDR(x) (REGS_CAN_BASE(x) + 0x18U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_RX15MASK(x) (*(__IO hw_can_rx15mask_t *) HW_CAN_RX15MASK_ADDR(x))
+#define HW_CAN_RX15MASK_RD(x) (HW_CAN_RX15MASK(x).U)
+#define HW_CAN_RX15MASK_WR(x, v) (HW_CAN_RX15MASK(x).U = (v))
+#define HW_CAN_RX15MASK_SET(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) | (v)))
+#define HW_CAN_RX15MASK_CLR(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) & ~(v)))
+#define HW_CAN_RX15MASK_TOG(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_RX15MASK bitfields
+ */
+
+/*!
+ * @name Register CAN_RX15MASK, field RX15M[31:0] (RW)
+ *
+ * Each mask bit masks the corresponding Mailbox 15 filter field in the same way
+ * that RXMGMASK masks other Mailboxes' filters. See the description of the
+ * CAN_RXMGMASK register.
+ *
+ * Values:
+ * - 0 - The corresponding bit in the filter is "don't care."
+ * - 1 - The corresponding bit in the filter is checked.
+ */
+//@{
+#define BP_CAN_RX15MASK_RX15M (0U) //!< Bit position for CAN_RX15MASK_RX15M.
+#define BM_CAN_RX15MASK_RX15M (0xFFFFFFFFU) //!< Bit mask for CAN_RX15MASK_RX15M.
+#define BS_CAN_RX15MASK_RX15M (32U) //!< Bit field size in bits for CAN_RX15MASK_RX15M.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_RX15MASK_RX15M field.
+#define BR_CAN_RX15MASK_RX15M(x) (HW_CAN_RX15MASK(x).U)
+#endif
+
+//! @brief Format value for bitfield CAN_RX15MASK_RX15M.
+#define BF_CAN_RX15MASK_RX15M(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_RX15MASK_RX15M), uint32_t) & BM_CAN_RX15MASK_RX15M)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RX15M field to a new value.
+#define BW_CAN_RX15MASK_RX15M(x, v) (HW_CAN_RX15MASK_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_ECR - Error Counter
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_ECR - Error Counter (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register has two 8-bit fields reflecting the value of two FlexCAN error
+ * counters: Transmit Error Counter (TXERRCNT field) and Receive Error Counter
+ * (RXERRCNT field). The rules for increasing and decreasing these counters are
+ * described in the CAN protocol and are completely implemented in the FlexCAN
+ * module. Both counters are read-only except in Freeze mode, where they can be
+ * written by the CPU. FlexCAN responds to any bus state as described in the protocol,
+ * for example, transmit Error Active or Error Passive flag, delay its
+ * transmission start time (Error Passive) and avoid any influence on the bus when in Bus
+ * Off state. The following are the basic rules for FlexCAN bus state transitions:
+ * If the value of TXERRCNT or RXERRCNT increases to be greater than or equal to
+ * 128, the FLTCONF field in the Error and Status Register is updated to reflect
+ * 'Error Passive' state. If the FlexCAN state is 'Error Passive', and either
+ * TXERRCNT or RXERRCNT decrements to a value less than or equal to 127 while the
+ * other already satisfies this condition, the FLTCONF field in the Error and
+ * Status Register is updated to reflect 'Error Active' state. If the value of
+ * TXERRCNT increases to be greater than 255, the FLTCONF field in the Error and Status
+ * Register is updated to reflect 'Bus Off' state, and an interrupt may be
+ * issued. The value of TXERRCNT is then reset to zero. If FlexCAN is in 'Bus Off'
+ * state, then TXERRCNT is cascaded together with another internal counter to count
+ * the 128th occurrences of 11 consecutive recessive bits on the bus. Hence,
+ * TXERRCNT is reset to zero and counts in a manner where the internal counter counts
+ * 11 such bits and then wraps around while incrementing the TXERRCNT. When
+ * TXERRCNT reaches the value of 128, the FLTCONF field in the Error and Status
+ * Register is updated to be 'Error Active' and both error counters are reset to zero.
+ * At any instance of dominant bit following a stream of less than 11
+ * consecutive recessive bits, the internal counter resets itself to zero without affecting
+ * the TXERRCNT value. If during system start-up, only one node is operating,
+ * then its TXERRCNT increases in each message it is trying to transmit, as a
+ * result of acknowledge errors (indicated by the ACKERR bit in the Error and Status
+ * Register). After the transition to 'Error Passive' state, the TXERRCNT does not
+ * increment anymore by acknowledge errors. Therefore the device never goes to
+ * the 'Bus Off' state. If the RXERRCNT increases to a value greater than 127, it
+ * is not incremented further, even if more errors are detected while being a
+ * receiver. At the next successful message reception, the counter is set to a value
+ * between 119 and 127 to resume to 'Error Active' state.
+ */
+typedef union _hw_can_ecr
+{
+ uint32_t U;
+ struct _hw_can_ecr_bitfields
+ {
+ uint32_t TXERRCNT : 8; //!< [7:0] Transmit Error Counter
+ uint32_t RXERRCNT : 8; //!< [15:8] Receive Error Counter
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_can_ecr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_ECR register
+ */
+//@{
+#define HW_CAN_ECR_ADDR(x) (REGS_CAN_BASE(x) + 0x1CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_ECR(x) (*(__IO hw_can_ecr_t *) HW_CAN_ECR_ADDR(x))
+#define HW_CAN_ECR_RD(x) (HW_CAN_ECR(x).U)
+#define HW_CAN_ECR_WR(x, v) (HW_CAN_ECR(x).U = (v))
+#define HW_CAN_ECR_SET(x, v) (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) | (v)))
+#define HW_CAN_ECR_CLR(x, v) (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) & ~(v)))
+#define HW_CAN_ECR_TOG(x, v) (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_ECR bitfields
+ */
+
+/*!
+ * @name Register CAN_ECR, field TXERRCNT[7:0] (RW)
+ */
+//@{
+#define BP_CAN_ECR_TXERRCNT (0U) //!< Bit position for CAN_ECR_TXERRCNT.
+#define BM_CAN_ECR_TXERRCNT (0x000000FFU) //!< Bit mask for CAN_ECR_TXERRCNT.
+#define BS_CAN_ECR_TXERRCNT (8U) //!< Bit field size in bits for CAN_ECR_TXERRCNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ECR_TXERRCNT field.
+#define BR_CAN_ECR_TXERRCNT(x) (HW_CAN_ECR(x).B.TXERRCNT)
+#endif
+
+//! @brief Format value for bitfield CAN_ECR_TXERRCNT.
+#define BF_CAN_ECR_TXERRCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ECR_TXERRCNT), uint32_t) & BM_CAN_ECR_TXERRCNT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXERRCNT field to a new value.
+#define BW_CAN_ECR_TXERRCNT(x, v) (HW_CAN_ECR_WR(x, (HW_CAN_ECR_RD(x) & ~BM_CAN_ECR_TXERRCNT) | BF_CAN_ECR_TXERRCNT(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ECR, field RXERRCNT[15:8] (RW)
+ */
+//@{
+#define BP_CAN_ECR_RXERRCNT (8U) //!< Bit position for CAN_ECR_RXERRCNT.
+#define BM_CAN_ECR_RXERRCNT (0x0000FF00U) //!< Bit mask for CAN_ECR_RXERRCNT.
+#define BS_CAN_ECR_RXERRCNT (8U) //!< Bit field size in bits for CAN_ECR_RXERRCNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ECR_RXERRCNT field.
+#define BR_CAN_ECR_RXERRCNT(x) (HW_CAN_ECR(x).B.RXERRCNT)
+#endif
+
+//! @brief Format value for bitfield CAN_ECR_RXERRCNT.
+#define BF_CAN_ECR_RXERRCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ECR_RXERRCNT), uint32_t) & BM_CAN_ECR_RXERRCNT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXERRCNT field to a new value.
+#define BW_CAN_ECR_RXERRCNT(x, v) (HW_CAN_ECR_WR(x, (HW_CAN_ECR_RD(x) & ~BM_CAN_ECR_RXERRCNT) | BF_CAN_ECR_RXERRCNT(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_ESR1 - Error and Status 1 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_ESR1 - Error and Status 1 register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register reflects various error conditions, some general status of the
+ * device and it is the source of interrupts to the CPU. The CPU read action
+ * clears bits 15-10. Therefore the reported error conditions (bits 15-10) are those
+ * that occurred since the last time the CPU read this register. Bits 9-3 are
+ * status bits. The following table shows the FlexCAN state variables and their
+ * meanings. Other combinations not shown in the table are reserved. SYNCH IDLE TX RX
+ * FlexCAN State 0 0 0 0 Not synchronized to CAN bus 1 1 x x Idle 1 0 1 0
+ * Transmitting 1 0 0 1 Receiving
+ */
+typedef union _hw_can_esr1
+{
+ uint32_t U;
+ struct _hw_can_esr1_bitfields
+ {
+ uint32_t WAKINT : 1; //!< [0] Wake-Up Interrupt
+ uint32_t ERRINT : 1; //!< [1] Error Interrupt
+ uint32_t BOFFINT : 1; //!< [2] Bus Off Interrupt
+ uint32_t RX : 1; //!< [3] FlexCAN In Reception
+ uint32_t FLTCONF : 2; //!< [5:4] Fault Confinement State
+ uint32_t TX : 1; //!< [6] FlexCAN In Transmission
+ uint32_t IDLE : 1; //!< [7]
+ uint32_t RXWRN : 1; //!< [8] Rx Error Warning
+ uint32_t TXWRN : 1; //!< [9] TX Error Warning
+ uint32_t STFERR : 1; //!< [10] Stuffing Error
+ uint32_t FRMERR : 1; //!< [11] Form Error
+ uint32_t CRCERR : 1; //!< [12] Cyclic Redundancy Check Error
+ uint32_t ACKERR : 1; //!< [13] Acknowledge Error
+ uint32_t BIT0ERR : 1; //!< [14] Bit0 Error
+ uint32_t BIT1ERR : 1; //!< [15] Bit1 Error
+ uint32_t RWRNINT : 1; //!< [16] Rx Warning Interrupt Flag
+ uint32_t TWRNINT : 1; //!< [17] Tx Warning Interrupt Flag
+ uint32_t SYNCH : 1; //!< [18] CAN Synchronization Status
+ uint32_t RESERVED0 : 13; //!< [31:19]
+ } B;
+} hw_can_esr1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_ESR1 register
+ */
+//@{
+#define HW_CAN_ESR1_ADDR(x) (REGS_CAN_BASE(x) + 0x20U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_ESR1(x) (*(__IO hw_can_esr1_t *) HW_CAN_ESR1_ADDR(x))
+#define HW_CAN_ESR1_RD(x) (HW_CAN_ESR1(x).U)
+#define HW_CAN_ESR1_WR(x, v) (HW_CAN_ESR1(x).U = (v))
+#define HW_CAN_ESR1_SET(x, v) (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) | (v)))
+#define HW_CAN_ESR1_CLR(x, v) (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) & ~(v)))
+#define HW_CAN_ESR1_TOG(x, v) (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_ESR1 bitfields
+ */
+
+/*!
+ * @name Register CAN_ESR1, field WAKINT[0] (W1C)
+ *
+ * This field applies when FlexCAN is in low-power mode under Self Wake Up
+ * mechanism: Stop mode When a recessive-to-dominant transition is detected on the CAN
+ * bus and if the MCR[WAKMSK] bit is set, an interrupt is generated to the CPU.
+ * This bit is cleared by writing it to 1. When MCR[SLFWAK] is negated, this flag
+ * is masked. The CPU must clear this flag before disabling the bit. Otherwise
+ * it will be set when the SLFWAK is set again. Writing 0 has no effect.
+ *
+ * Values:
+ * - 0 - No such occurrence.
+ * - 1 - Indicates a recessive to dominant transition was received on the CAN
+ * bus.
+ */
+//@{
+#define BP_CAN_ESR1_WAKINT (0U) //!< Bit position for CAN_ESR1_WAKINT.
+#define BM_CAN_ESR1_WAKINT (0x00000001U) //!< Bit mask for CAN_ESR1_WAKINT.
+#define BS_CAN_ESR1_WAKINT (1U) //!< Bit field size in bits for CAN_ESR1_WAKINT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_WAKINT field.
+#define BR_CAN_ESR1_WAKINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_WAKINT))
+#endif
+
+//! @brief Format value for bitfield CAN_ESR1_WAKINT.
+#define BF_CAN_ESR1_WAKINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ESR1_WAKINT), uint32_t) & BM_CAN_ESR1_WAKINT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WAKINT field to a new value.
+#define BW_CAN_ESR1_WAKINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_WAKINT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field ERRINT[1] (W1C)
+ *
+ * This bit indicates that at least one of the Error Bits (bits 15-10) is set.
+ * If the corresponding mask bit CTRL1[ERRMSK] is set, an interrupt is generated
+ * to the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
+ *
+ * Values:
+ * - 0 - No such occurrence.
+ * - 1 - Indicates setting of any Error Bit in the Error and Status Register.
+ */
+//@{
+#define BP_CAN_ESR1_ERRINT (1U) //!< Bit position for CAN_ESR1_ERRINT.
+#define BM_CAN_ESR1_ERRINT (0x00000002U) //!< Bit mask for CAN_ESR1_ERRINT.
+#define BS_CAN_ESR1_ERRINT (1U) //!< Bit field size in bits for CAN_ESR1_ERRINT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_ERRINT field.
+#define BR_CAN_ESR1_ERRINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ERRINT))
+#endif
+
+//! @brief Format value for bitfield CAN_ESR1_ERRINT.
+#define BF_CAN_ESR1_ERRINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ESR1_ERRINT), uint32_t) & BM_CAN_ESR1_ERRINT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERRINT field to a new value.
+#define BW_CAN_ESR1_ERRINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ERRINT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field BOFFINT[2] (W1C)
+ *
+ * This bit is set when FlexCAN enters 'Bus Off' state. If the corresponding
+ * mask bit in the Control Register (BOFFMSK) is set, an interrupt is generated to
+ * the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
+ *
+ * Values:
+ * - 0 - No such occurrence.
+ * - 1 - FlexCAN module entered Bus Off state.
+ */
+//@{
+#define BP_CAN_ESR1_BOFFINT (2U) //!< Bit position for CAN_ESR1_BOFFINT.
+#define BM_CAN_ESR1_BOFFINT (0x00000004U) //!< Bit mask for CAN_ESR1_BOFFINT.
+#define BS_CAN_ESR1_BOFFINT (1U) //!< Bit field size in bits for CAN_ESR1_BOFFINT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_BOFFINT field.
+#define BR_CAN_ESR1_BOFFINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BOFFINT))
+#endif
+
+//! @brief Format value for bitfield CAN_ESR1_BOFFINT.
+#define BF_CAN_ESR1_BOFFINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ESR1_BOFFINT), uint32_t) & BM_CAN_ESR1_BOFFINT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BOFFINT field to a new value.
+#define BW_CAN_ESR1_BOFFINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BOFFINT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field RX[3] (RO)
+ *
+ * This bit indicates if FlexCAN is receiving a message. See the table in the
+ * overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0 - FlexCAN is not receiving a message.
+ * - 1 - FlexCAN is receiving a message.
+ */
+//@{
+#define BP_CAN_ESR1_RX (3U) //!< Bit position for CAN_ESR1_RX.
+#define BM_CAN_ESR1_RX (0x00000008U) //!< Bit mask for CAN_ESR1_RX.
+#define BS_CAN_ESR1_RX (1U) //!< Bit field size in bits for CAN_ESR1_RX.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_RX field.
+#define BR_CAN_ESR1_RX(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RX))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field FLTCONF[5:4] (RO)
+ *
+ * This 2-bit field indicates the Confinement State of the FlexCAN module. If
+ * the LOM bit in the Control Register is asserted, after some delay that depends
+ * on the CAN bit timing the FLTCONF field will indicate "Error Passive". The very
+ * same delay affects the way how FLTCONF reflects an update to ECR register by
+ * the CPU. It may be necessary up to one CAN bit time to get them coherent
+ * again. Because the Control Register is not affected by soft reset, the FLTCONF
+ * field will not be affected by soft reset if the LOM bit is asserted.
+ *
+ * Values:
+ * - 00 - Error Active
+ * - 01 - Error Passive
+ * - 1x - Bus Off
+ */
+//@{
+#define BP_CAN_ESR1_FLTCONF (4U) //!< Bit position for CAN_ESR1_FLTCONF.
+#define BM_CAN_ESR1_FLTCONF (0x00000030U) //!< Bit mask for CAN_ESR1_FLTCONF.
+#define BS_CAN_ESR1_FLTCONF (2U) //!< Bit field size in bits for CAN_ESR1_FLTCONF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_FLTCONF field.
+#define BR_CAN_ESR1_FLTCONF(x) (HW_CAN_ESR1(x).B.FLTCONF)
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field TX[6] (RO)
+ *
+ * This bit indicates if FlexCAN is transmitting a message. See the table in the
+ * overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0 - FlexCAN is not transmitting a message.
+ * - 1 - FlexCAN is transmitting a message.
+ */
+//@{
+#define BP_CAN_ESR1_TX (6U) //!< Bit position for CAN_ESR1_TX.
+#define BM_CAN_ESR1_TX (0x00000040U) //!< Bit mask for CAN_ESR1_TX.
+#define BS_CAN_ESR1_TX (1U) //!< Bit field size in bits for CAN_ESR1_TX.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_TX field.
+#define BR_CAN_ESR1_TX(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TX))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field IDLE[7] (RO)
+ *
+ * This bit indicates when CAN bus is in IDLE state. See the table in the
+ * overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0 - No such occurrence.
+ * - 1 - CAN bus is now IDLE.
+ */
+//@{
+#define BP_CAN_ESR1_IDLE (7U) //!< Bit position for CAN_ESR1_IDLE.
+#define BM_CAN_ESR1_IDLE (0x00000080U) //!< Bit mask for CAN_ESR1_IDLE.
+#define BS_CAN_ESR1_IDLE (1U) //!< Bit field size in bits for CAN_ESR1_IDLE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_IDLE field.
+#define BR_CAN_ESR1_IDLE(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_IDLE))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field RXWRN[8] (RO)
+ *
+ * This bit indicates when repetitive errors are occurring during message
+ * reception. This bit is not updated during Freeze mode.
+ *
+ * Values:
+ * - 0 - No such occurrence.
+ * - 1 - RXERRCNT is greater than or equal to 96.
+ */
+//@{
+#define BP_CAN_ESR1_RXWRN (8U) //!< Bit position for CAN_ESR1_RXWRN.
+#define BM_CAN_ESR1_RXWRN (0x00000100U) //!< Bit mask for CAN_ESR1_RXWRN.
+#define BS_CAN_ESR1_RXWRN (1U) //!< Bit field size in bits for CAN_ESR1_RXWRN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_RXWRN field.
+#define BR_CAN_ESR1_RXWRN(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RXWRN))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field TXWRN[9] (RO)
+ *
+ * This bit indicates when repetitive errors are occurring during message
+ * transmission. This bit is not updated during Freeze mode.
+ *
+ * Values:
+ * - 0 - No such occurrence.
+ * - 1 - TXERRCNT is greater than or equal to 96.
+ */
+//@{
+#define BP_CAN_ESR1_TXWRN (9U) //!< Bit position for CAN_ESR1_TXWRN.
+#define BM_CAN_ESR1_TXWRN (0x00000200U) //!< Bit mask for CAN_ESR1_TXWRN.
+#define BS_CAN_ESR1_TXWRN (1U) //!< Bit field size in bits for CAN_ESR1_TXWRN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_TXWRN field.
+#define BR_CAN_ESR1_TXWRN(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TXWRN))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field STFERR[10] (RO)
+ *
+ * This bit indicates that a Stuffing Error has been etected.
+ *
+ * Values:
+ * - 0 - No such occurrence.
+ * - 1 - A Stuffing Error occurred since last read of this register.
+ */
+//@{
+#define BP_CAN_ESR1_STFERR (10U) //!< Bit position for CAN_ESR1_STFERR.
+#define BM_CAN_ESR1_STFERR (0x00000400U) //!< Bit mask for CAN_ESR1_STFERR.
+#define BS_CAN_ESR1_STFERR (1U) //!< Bit field size in bits for CAN_ESR1_STFERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_STFERR field.
+#define BR_CAN_ESR1_STFERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_STFERR))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field FRMERR[11] (RO)
+ *
+ * This bit indicates that a Form Error has been detected by the receiver node,
+ * that is, a fixed-form bit field contains at least one illegal bit.
+ *
+ * Values:
+ * - 0 - No such occurrence.
+ * - 1 - A Form Error occurred since last read of this register.
+ */
+//@{
+#define BP_CAN_ESR1_FRMERR (11U) //!< Bit position for CAN_ESR1_FRMERR.
+#define BM_CAN_ESR1_FRMERR (0x00000800U) //!< Bit mask for CAN_ESR1_FRMERR.
+#define BS_CAN_ESR1_FRMERR (1U) //!< Bit field size in bits for CAN_ESR1_FRMERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_FRMERR field.
+#define BR_CAN_ESR1_FRMERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_FRMERR))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field CRCERR[12] (RO)
+ *
+ * This bit indicates that a CRC Error has been detected by the receiver node,
+ * that is, the calculated CRC is different from the received.
+ *
+ * Values:
+ * - 0 - No such occurrence.
+ * - 1 - A CRC error occurred since last read of this register.
+ */
+//@{
+#define BP_CAN_ESR1_CRCERR (12U) //!< Bit position for CAN_ESR1_CRCERR.
+#define BM_CAN_ESR1_CRCERR (0x00001000U) //!< Bit mask for CAN_ESR1_CRCERR.
+#define BS_CAN_ESR1_CRCERR (1U) //!< Bit field size in bits for CAN_ESR1_CRCERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_CRCERR field.
+#define BR_CAN_ESR1_CRCERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_CRCERR))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field ACKERR[13] (RO)
+ *
+ * This bit indicates that an Acknowledge Error has been detected by the
+ * transmitter node, that is, a dominant bit has not been detected during the ACK SLOT.
+ *
+ * Values:
+ * - 0 - No such occurrence.
+ * - 1 - An ACK error occurred since last read of this register.
+ */
+//@{
+#define BP_CAN_ESR1_ACKERR (13U) //!< Bit position for CAN_ESR1_ACKERR.
+#define BM_CAN_ESR1_ACKERR (0x00002000U) //!< Bit mask for CAN_ESR1_ACKERR.
+#define BS_CAN_ESR1_ACKERR (1U) //!< Bit field size in bits for CAN_ESR1_ACKERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_ACKERR field.
+#define BR_CAN_ESR1_ACKERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ACKERR))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field BIT0ERR[14] (RO)
+ *
+ * This bit indicates when an inconsistency occurs between the transmitted and
+ * the received bit in a message.
+ *
+ * Values:
+ * - 0 - No such occurrence.
+ * - 1 - At least one bit sent as dominant is received as recessive.
+ */
+//@{
+#define BP_CAN_ESR1_BIT0ERR (14U) //!< Bit position for CAN_ESR1_BIT0ERR.
+#define BM_CAN_ESR1_BIT0ERR (0x00004000U) //!< Bit mask for CAN_ESR1_BIT0ERR.
+#define BS_CAN_ESR1_BIT0ERR (1U) //!< Bit field size in bits for CAN_ESR1_BIT0ERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_BIT0ERR field.
+#define BR_CAN_ESR1_BIT0ERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BIT0ERR))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field BIT1ERR[15] (RO)
+ *
+ * This bit indicates when an inconsistency occurs between the transmitted and
+ * the received bit in a message. This bit is not set by a transmitter in case of
+ * arbitration field or ACK slot, or in case of a node sending a passive error
+ * flag that detects dominant bits.
+ *
+ * Values:
+ * - 0 - No such occurrence.
+ * - 1 - At least one bit sent as recessive is received as dominant.
+ */
+//@{
+#define BP_CAN_ESR1_BIT1ERR (15U) //!< Bit position for CAN_ESR1_BIT1ERR.
+#define BM_CAN_ESR1_BIT1ERR (0x00008000U) //!< Bit mask for CAN_ESR1_BIT1ERR.
+#define BS_CAN_ESR1_BIT1ERR (1U) //!< Bit field size in bits for CAN_ESR1_BIT1ERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_BIT1ERR field.
+#define BR_CAN_ESR1_BIT1ERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BIT1ERR))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field RWRNINT[16] (W1C)
+ *
+ * If the WRNEN bit in MCR is asserted, the RWRNINT bit is set when the RXWRN
+ * flag transitions from 0 to 1, meaning that the Rx error counters reached 96. If
+ * the corresponding mask bit in the Control Register (RWRNMSK) is set, an
+ * interrupt is generated to the CPU. This bit is cleared by writing it to 1. When
+ * WRNEN is negated, this flag is masked. CPU must clear this flag before disabling
+ * the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
+ * effect. This bit is not updated during Freeze mode.
+ *
+ * Values:
+ * - 0 - No such occurrence.
+ * - 1 - The Rx error counter transitioned from less than 96 to greater than or
+ * equal to 96.
+ */
+//@{
+#define BP_CAN_ESR1_RWRNINT (16U) //!< Bit position for CAN_ESR1_RWRNINT.
+#define BM_CAN_ESR1_RWRNINT (0x00010000U) //!< Bit mask for CAN_ESR1_RWRNINT.
+#define BS_CAN_ESR1_RWRNINT (1U) //!< Bit field size in bits for CAN_ESR1_RWRNINT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_RWRNINT field.
+#define BR_CAN_ESR1_RWRNINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RWRNINT))
+#endif
+
+//! @brief Format value for bitfield CAN_ESR1_RWRNINT.
+#define BF_CAN_ESR1_RWRNINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ESR1_RWRNINT), uint32_t) & BM_CAN_ESR1_RWRNINT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RWRNINT field to a new value.
+#define BW_CAN_ESR1_RWRNINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RWRNINT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field TWRNINT[17] (W1C)
+ *
+ * If the WRNEN bit in MCR is asserted, the TWRNINT bit is set when the TXWRN
+ * flag transitions from 0 to 1, meaning that the Tx error counter reached 96. If
+ * the corresponding mask bit in the Control Register (TWRNMSK) is set, an
+ * interrupt is generated to the CPU. This bit is cleared by writing it to 1. When WRNEN
+ * is negated, this flag is masked. CPU must clear this flag before disabling
+ * the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
+ * effect. This flag is not generated during Bus Off state. This bit is not
+ * updated during Freeze mode.
+ *
+ * Values:
+ * - 0 - No such occurrence.
+ * - 1 - The Tx error counter transitioned from less than 96 to greater than or
+ * equal to 96.
+ */
+//@{
+#define BP_CAN_ESR1_TWRNINT (17U) //!< Bit position for CAN_ESR1_TWRNINT.
+#define BM_CAN_ESR1_TWRNINT (0x00020000U) //!< Bit mask for CAN_ESR1_TWRNINT.
+#define BS_CAN_ESR1_TWRNINT (1U) //!< Bit field size in bits for CAN_ESR1_TWRNINT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_TWRNINT field.
+#define BR_CAN_ESR1_TWRNINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TWRNINT))
+#endif
+
+//! @brief Format value for bitfield CAN_ESR1_TWRNINT.
+#define BF_CAN_ESR1_TWRNINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ESR1_TWRNINT), uint32_t) & BM_CAN_ESR1_TWRNINT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TWRNINT field to a new value.
+#define BW_CAN_ESR1_TWRNINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TWRNINT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR1, field SYNCH[18] (RO)
+ *
+ * This read-only flag indicates whether the FlexCAN is synchronized to the CAN
+ * bus and able to participate in the communication process. It is set and
+ * cleared by the FlexCAN. See the table in the overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0 - FlexCAN is not synchronized to the CAN bus.
+ * - 1 - FlexCAN is synchronized to the CAN bus.
+ */
+//@{
+#define BP_CAN_ESR1_SYNCH (18U) //!< Bit position for CAN_ESR1_SYNCH.
+#define BM_CAN_ESR1_SYNCH (0x00040000U) //!< Bit mask for CAN_ESR1_SYNCH.
+#define BS_CAN_ESR1_SYNCH (1U) //!< Bit field size in bits for CAN_ESR1_SYNCH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR1_SYNCH field.
+#define BR_CAN_ESR1_SYNCH(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_SYNCH))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_IMASK1 - Interrupt Masks 1 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_IMASK1 - Interrupt Masks 1 register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register allows any number of a range of the 32 Message Buffer
+ * Interrupts to be enabled or disabled for MB31 to MB0. It contains one interrupt mask
+ * bit per buffer, enabling the CPU to determine which buffer generates an
+ * interrupt after a successful transmission or reception, that is, when the
+ * corresponding IFLAG1 bit is set.
+ */
+typedef union _hw_can_imask1
+{
+ uint32_t U;
+ struct _hw_can_imask1_bitfields
+ {
+ uint32_t BUFLM : 32; //!< [31:0] Buffer MB i Mask
+ } B;
+} hw_can_imask1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_IMASK1 register
+ */
+//@{
+#define HW_CAN_IMASK1_ADDR(x) (REGS_CAN_BASE(x) + 0x28U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_IMASK1(x) (*(__IO hw_can_imask1_t *) HW_CAN_IMASK1_ADDR(x))
+#define HW_CAN_IMASK1_RD(x) (HW_CAN_IMASK1(x).U)
+#define HW_CAN_IMASK1_WR(x, v) (HW_CAN_IMASK1(x).U = (v))
+#define HW_CAN_IMASK1_SET(x, v) (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) | (v)))
+#define HW_CAN_IMASK1_CLR(x, v) (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) & ~(v)))
+#define HW_CAN_IMASK1_TOG(x, v) (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_IMASK1 bitfields
+ */
+
+/*!
+ * @name Register CAN_IMASK1, field BUFLM[31:0] (RW)
+ *
+ * Each bit enables or disables the corresponding FlexCAN Message Buffer
+ * Interrupt for MB31 to MB0. Setting or clearing a bit in the IMASK1 Register can
+ * assert or negate an interrupt request, if the corresponding IFLAG1 bit is set.
+ *
+ * Values:
+ * - 0 - The corresponding buffer Interrupt is disabled.
+ * - 1 - The corresponding buffer Interrupt is enabled.
+ */
+//@{
+#define BP_CAN_IMASK1_BUFLM (0U) //!< Bit position for CAN_IMASK1_BUFLM.
+#define BM_CAN_IMASK1_BUFLM (0xFFFFFFFFU) //!< Bit mask for CAN_IMASK1_BUFLM.
+#define BS_CAN_IMASK1_BUFLM (32U) //!< Bit field size in bits for CAN_IMASK1_BUFLM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_IMASK1_BUFLM field.
+#define BR_CAN_IMASK1_BUFLM(x) (HW_CAN_IMASK1(x).U)
+#endif
+
+//! @brief Format value for bitfield CAN_IMASK1_BUFLM.
+#define BF_CAN_IMASK1_BUFLM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IMASK1_BUFLM), uint32_t) & BM_CAN_IMASK1_BUFLM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BUFLM field to a new value.
+#define BW_CAN_IMASK1_BUFLM(x, v) (HW_CAN_IMASK1_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_IFLAG1 - Interrupt Flags 1 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_IFLAG1 - Interrupt Flags 1 register (W1C)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register defines the flags for the 32 Message Buffer interrupts for MB31
+ * to MB0. It contains one interrupt flag bit per buffer. Each successful
+ * transmission or reception sets the corresponding IFLAG1 bit. If the corresponding
+ * IMASK1 bit is set, an interrupt will be generated. The interrupt flag must be
+ * cleared by writing 1 to it. Writing 0 has no effect. The BUF7I to BUF5I flags
+ * are also used to represent FIFO interrupts when the Rx FIFO is enabled. When the
+ * bit MCR[RFEN] is set, the function of the 8 least significant interrupt flags
+ * BUF[7:0]I changes: BUF7I, BUF6I and BUF5I indicate operating conditions of
+ * the FIFO, and the BUF4TO0I field is reserved. Before enabling the RFEN, the CPU
+ * must service the IFLAG bits asserted in the Rx FIFO region; see Section "Rx
+ * FIFO". Otherwise, these IFLAG bits will mistakenly show the related MBs now
+ * belonging to FIFO as having contents to be serviced. When the RFEN bit is negated,
+ * the FIFO flags must be cleared. The same care must be taken when an RFFN
+ * value is selected extending Rx FIFO filters beyond MB7. For example, when RFFN is
+ * 0x8, the MB0-23 range is occupied by Rx FIFO filters and related IFLAG bits
+ * must be cleared. Before updating MCR[MAXMB] field, CPU must service the IFLAG1
+ * bits whose MB value is greater than the MCR[MAXMB] to be updated; otherwise,
+ * they will remain set and be inconsistent with the number of MBs available.
+ */
+typedef union _hw_can_iflag1
+{
+ uint32_t U;
+ struct _hw_can_iflag1_bitfields
+ {
+ uint32_t BUF0I : 1; //!< [0] Buffer MB0 Interrupt Or "reserved"
+ uint32_t BUF4TO1I : 4; //!< [4:1] Buffer MB i Interrupt Or "reserved"
+ uint32_t BUF5I : 1; //!< [5] Buffer MB5 Interrupt Or "Frames
+ //! available in Rx FIFO"
+ uint32_t BUF6I : 1; //!< [6] Buffer MB6 Interrupt Or "Rx FIFO Warning"
+ uint32_t BUF7I : 1; //!< [7] Buffer MB7 Interrupt Or "Rx FIFO
+ //! Overflow"
+ uint32_t BUF31TO8I : 24; //!< [31:8] Buffer MBi Interrupt
+ } B;
+} hw_can_iflag1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_IFLAG1 register
+ */
+//@{
+#define HW_CAN_IFLAG1_ADDR(x) (REGS_CAN_BASE(x) + 0x30U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_IFLAG1(x) (*(__IO hw_can_iflag1_t *) HW_CAN_IFLAG1_ADDR(x))
+#define HW_CAN_IFLAG1_RD(x) (HW_CAN_IFLAG1(x).U)
+#define HW_CAN_IFLAG1_WR(x, v) (HW_CAN_IFLAG1(x).U = (v))
+#define HW_CAN_IFLAG1_SET(x, v) (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) | (v)))
+#define HW_CAN_IFLAG1_CLR(x, v) (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) & ~(v)))
+#define HW_CAN_IFLAG1_TOG(x, v) (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_IFLAG1 bitfields
+ */
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF0I[0] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB0. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF0I flag is reserved when MCR[RFEN] is
+ * set.
+ *
+ * Values:
+ * - 0 - The corresponding buffer has no occurrence of successfully completed
+ * transmission or reception when MCR[RFEN]=0.
+ * - 1 - The corresponding buffer has successfully completed transmission or
+ * reception when MCR[RFEN]=0.
+ */
+//@{
+#define BP_CAN_IFLAG1_BUF0I (0U) //!< Bit position for CAN_IFLAG1_BUF0I.
+#define BM_CAN_IFLAG1_BUF0I (0x00000001U) //!< Bit mask for CAN_IFLAG1_BUF0I.
+#define BS_CAN_IFLAG1_BUF0I (1U) //!< Bit field size in bits for CAN_IFLAG1_BUF0I.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_IFLAG1_BUF0I field.
+#define BR_CAN_IFLAG1_BUF0I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF0I))
+#endif
+
+//! @brief Format value for bitfield CAN_IFLAG1_BUF0I.
+#define BF_CAN_IFLAG1_BUF0I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF0I), uint32_t) & BM_CAN_IFLAG1_BUF0I)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BUF0I field to a new value.
+#define BW_CAN_IFLAG1_BUF0I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF0I) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF4TO1I[4:1] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), these bits flag
+ * the interrupts for MB4 to MB1. These flags are cleared by the FlexCAN whenever
+ * the bit MCR[RFEN] is changed by CPU writes. The BUF4TO1I flags are reserved
+ * when MCR[RFEN] is set.
+ *
+ * Values:
+ * - 0 - The corresponding buffer has no occurrence of successfully completed
+ * transmission or reception when MCR[RFEN]=0.
+ * - 1 - The corresponding buffer has successfully completed transmission or
+ * reception when MCR[RFEN]=0.
+ */
+//@{
+#define BP_CAN_IFLAG1_BUF4TO1I (1U) //!< Bit position for CAN_IFLAG1_BUF4TO1I.
+#define BM_CAN_IFLAG1_BUF4TO1I (0x0000001EU) //!< Bit mask for CAN_IFLAG1_BUF4TO1I.
+#define BS_CAN_IFLAG1_BUF4TO1I (4U) //!< Bit field size in bits for CAN_IFLAG1_BUF4TO1I.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_IFLAG1_BUF4TO1I field.
+#define BR_CAN_IFLAG1_BUF4TO1I(x) (HW_CAN_IFLAG1(x).B.BUF4TO1I)
+#endif
+
+//! @brief Format value for bitfield CAN_IFLAG1_BUF4TO1I.
+#define BF_CAN_IFLAG1_BUF4TO1I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF4TO1I), uint32_t) & BM_CAN_IFLAG1_BUF4TO1I)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BUF4TO1I field to a new value.
+#define BW_CAN_IFLAG1_BUF4TO1I(x, v) (HW_CAN_IFLAG1_WR(x, (HW_CAN_IFLAG1_RD(x) & ~BM_CAN_IFLAG1_BUF4TO1I) | BF_CAN_IFLAG1_BUF4TO1I(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF5I[5] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB5. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF5I flag represents "Frames available in
+ * Rx FIFO" when MCR[RFEN] is set. In this case, the flag indicates that at
+ * least one frame is available to be read from the Rx FIFO.
+ *
+ * Values:
+ * - 0 - No occurrence of MB5 completing transmission/reception when
+ * MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
+ * - 1 - MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s)
+ * available in the Rx FIFO when MCR[RFEN]=1
+ */
+//@{
+#define BP_CAN_IFLAG1_BUF5I (5U) //!< Bit position for CAN_IFLAG1_BUF5I.
+#define BM_CAN_IFLAG1_BUF5I (0x00000020U) //!< Bit mask for CAN_IFLAG1_BUF5I.
+#define BS_CAN_IFLAG1_BUF5I (1U) //!< Bit field size in bits for CAN_IFLAG1_BUF5I.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_IFLAG1_BUF5I field.
+#define BR_CAN_IFLAG1_BUF5I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF5I))
+#endif
+
+//! @brief Format value for bitfield CAN_IFLAG1_BUF5I.
+#define BF_CAN_IFLAG1_BUF5I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF5I), uint32_t) & BM_CAN_IFLAG1_BUF5I)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BUF5I field to a new value.
+#define BW_CAN_IFLAG1_BUF5I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF5I) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF6I[6] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB6. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF6I flag represents "Rx FIFO Warning"
+ * when MCR[RFEN] is set. In this case, the flag indicates when the number of
+ * unread messages within the Rx FIFO is increased to 5 from 4 due to the reception of
+ * a new one, meaning that the Rx FIFO is almost full. Note that if the flag is
+ * cleared while the number of unread messages is greater than 4, it does not
+ * assert again until the number of unread messages within the Rx FIFO is decreased
+ * to be equal to or less than 4.
+ *
+ * Values:
+ * - 0 - No occurrence of MB6 completing transmission/reception when
+ * MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
+ * - 1 - MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
+ * almost full when MCR[RFEN]=1
+ */
+//@{
+#define BP_CAN_IFLAG1_BUF6I (6U) //!< Bit position for CAN_IFLAG1_BUF6I.
+#define BM_CAN_IFLAG1_BUF6I (0x00000040U) //!< Bit mask for CAN_IFLAG1_BUF6I.
+#define BS_CAN_IFLAG1_BUF6I (1U) //!< Bit field size in bits for CAN_IFLAG1_BUF6I.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_IFLAG1_BUF6I field.
+#define BR_CAN_IFLAG1_BUF6I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF6I))
+#endif
+
+//! @brief Format value for bitfield CAN_IFLAG1_BUF6I.
+#define BF_CAN_IFLAG1_BUF6I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF6I), uint32_t) & BM_CAN_IFLAG1_BUF6I)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BUF6I field to a new value.
+#define BW_CAN_IFLAG1_BUF6I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF6I) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF7I[7] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB7. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF7I flag represents "Rx FIFO Overflow"
+ * when MCR[RFEN] is set. In this case, the flag indicates that a message was lost
+ * because the Rx FIFO is full. Note that the flag will not be asserted when the
+ * Rx FIFO is full and the message was captured by a Mailbox.
+ *
+ * Values:
+ * - 0 - No occurrence of MB7 completing transmission/reception when
+ * MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
+ * - 1 - MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
+ * overflow when MCR[RFEN]=1
+ */
+//@{
+#define BP_CAN_IFLAG1_BUF7I (7U) //!< Bit position for CAN_IFLAG1_BUF7I.
+#define BM_CAN_IFLAG1_BUF7I (0x00000080U) //!< Bit mask for CAN_IFLAG1_BUF7I.
+#define BS_CAN_IFLAG1_BUF7I (1U) //!< Bit field size in bits for CAN_IFLAG1_BUF7I.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_IFLAG1_BUF7I field.
+#define BR_CAN_IFLAG1_BUF7I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF7I))
+#endif
+
+//! @brief Format value for bitfield CAN_IFLAG1_BUF7I.
+#define BF_CAN_IFLAG1_BUF7I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF7I), uint32_t) & BM_CAN_IFLAG1_BUF7I)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BUF7I field to a new value.
+#define BW_CAN_IFLAG1_BUF7I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF7I) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF31TO8I[31:8] (W1C)
+ *
+ * Each bit flags the corresponding FlexCAN Message Buffer interrupt for MB31 to
+ * MB8.
+ *
+ * Values:
+ * - 0 - The corresponding buffer has no occurrence of successfully completed
+ * transmission or reception.
+ * - 1 - The corresponding buffer has successfully completed transmission or
+ * reception.
+ */
+//@{
+#define BP_CAN_IFLAG1_BUF31TO8I (8U) //!< Bit position for CAN_IFLAG1_BUF31TO8I.
+#define BM_CAN_IFLAG1_BUF31TO8I (0xFFFFFF00U) //!< Bit mask for CAN_IFLAG1_BUF31TO8I.
+#define BS_CAN_IFLAG1_BUF31TO8I (24U) //!< Bit field size in bits for CAN_IFLAG1_BUF31TO8I.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_IFLAG1_BUF31TO8I field.
+#define BR_CAN_IFLAG1_BUF31TO8I(x) (HW_CAN_IFLAG1(x).B.BUF31TO8I)
+#endif
+
+//! @brief Format value for bitfield CAN_IFLAG1_BUF31TO8I.
+#define BF_CAN_IFLAG1_BUF31TO8I(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_IFLAG1_BUF31TO8I), uint32_t) & BM_CAN_IFLAG1_BUF31TO8I)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BUF31TO8I field to a new value.
+#define BW_CAN_IFLAG1_BUF31TO8I(x, v) (HW_CAN_IFLAG1_WR(x, (HW_CAN_IFLAG1_RD(x) & ~BM_CAN_IFLAG1_BUF31TO8I) | BF_CAN_IFLAG1_BUF31TO8I(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_CTRL2 - Control 2 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_CTRL2 - Control 2 register (RW)
+ *
+ * Reset value: 0x00B00000U
+ *
+ * This register contains control bits for CAN errors, FIFO features, and mode
+ * selection.
+ */
+typedef union _hw_can_ctrl2
+{
+ uint32_t U;
+ struct _hw_can_ctrl2_bitfields
+ {
+ uint32_t RESERVED0 : 16; //!< [15:0]
+ uint32_t EACEN : 1; //!< [16] Entire Frame Arbitration Field
+ //! Comparison Enable For Rx Mailboxes
+ uint32_t RRS : 1; //!< [17] Remote Request Storing
+ uint32_t MRP : 1; //!< [18] Mailboxes Reception Priority
+ uint32_t TASD : 5; //!< [23:19] Tx Arbitration Start Delay
+ uint32_t RFFN : 4; //!< [27:24] Number Of Rx FIFO Filters
+ uint32_t WRMFRZ : 1; //!< [28] Write-Access To Memory In Freeze Mode
+ uint32_t RESERVED1 : 3; //!< [31:29]
+ } B;
+} hw_can_ctrl2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_CTRL2 register
+ */
+//@{
+#define HW_CAN_CTRL2_ADDR(x) (REGS_CAN_BASE(x) + 0x34U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_CTRL2(x) (*(__IO hw_can_ctrl2_t *) HW_CAN_CTRL2_ADDR(x))
+#define HW_CAN_CTRL2_RD(x) (HW_CAN_CTRL2(x).U)
+#define HW_CAN_CTRL2_WR(x, v) (HW_CAN_CTRL2(x).U = (v))
+#define HW_CAN_CTRL2_SET(x, v) (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) | (v)))
+#define HW_CAN_CTRL2_CLR(x, v) (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) & ~(v)))
+#define HW_CAN_CTRL2_TOG(x, v) (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_CTRL2 bitfields
+ */
+
+/*!
+ * @name Register CAN_CTRL2, field EACEN[16] (RW)
+ *
+ * This bit controls the comparison of IDE and RTR bits whithin Rx Mailboxes
+ * filters with their corresponding bits in the incoming frame by the matching
+ * process. This bit does not affect matching for Rx FIFO. This bit can be written
+ * only in Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0 - Rx Mailbox filter's IDE bit is always compared and RTR is never
+ * compared despite mask bits.
+ * - 1 - Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with
+ * their corresponding bits within the incoming frame. Mask bits do apply.
+ */
+//@{
+#define BP_CAN_CTRL2_EACEN (16U) //!< Bit position for CAN_CTRL2_EACEN.
+#define BM_CAN_CTRL2_EACEN (0x00010000U) //!< Bit mask for CAN_CTRL2_EACEN.
+#define BS_CAN_CTRL2_EACEN (1U) //!< Bit field size in bits for CAN_CTRL2_EACEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL2_EACEN field.
+#define BR_CAN_CTRL2_EACEN(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_EACEN))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL2_EACEN.
+#define BF_CAN_CTRL2_EACEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_EACEN), uint32_t) & BM_CAN_CTRL2_EACEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EACEN field to a new value.
+#define BW_CAN_CTRL2_EACEN(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_EACEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL2, field RRS[17] (RW)
+ *
+ * If this bit is asserted Remote Request Frame is submitted to a matching
+ * process and stored in the corresponding Message Buffer in the same fashion of a
+ * Data Frame. No automatic Remote Response Frame will be generated. If this bit is
+ * negated the Remote Request Frame is submitted to a matching process and an
+ * automatic Remote Response Frame is generated if a Message Buffer with CODE=0b1010
+ * is found with the same ID. This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0 - Remote Response Frame is generated.
+ * - 1 - Remote Request Frame is stored.
+ */
+//@{
+#define BP_CAN_CTRL2_RRS (17U) //!< Bit position for CAN_CTRL2_RRS.
+#define BM_CAN_CTRL2_RRS (0x00020000U) //!< Bit mask for CAN_CTRL2_RRS.
+#define BS_CAN_CTRL2_RRS (1U) //!< Bit field size in bits for CAN_CTRL2_RRS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL2_RRS field.
+#define BR_CAN_CTRL2_RRS(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_RRS))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL2_RRS.
+#define BF_CAN_CTRL2_RRS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_RRS), uint32_t) & BM_CAN_CTRL2_RRS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RRS field to a new value.
+#define BW_CAN_CTRL2_RRS(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_RRS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL2, field MRP[18] (RW)
+ *
+ * If this bit is set the matching process starts from the Mailboxes and if no
+ * match occurs the matching continues on the Rx FIFO. This bit can be written
+ * only in Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0 - Matching starts from Rx FIFO and continues on Mailboxes.
+ * - 1 - Matching starts from Mailboxes and continues on Rx FIFO.
+ */
+//@{
+#define BP_CAN_CTRL2_MRP (18U) //!< Bit position for CAN_CTRL2_MRP.
+#define BM_CAN_CTRL2_MRP (0x00040000U) //!< Bit mask for CAN_CTRL2_MRP.
+#define BS_CAN_CTRL2_MRP (1U) //!< Bit field size in bits for CAN_CTRL2_MRP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL2_MRP field.
+#define BR_CAN_CTRL2_MRP(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_MRP))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL2_MRP.
+#define BF_CAN_CTRL2_MRP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_MRP), uint32_t) & BM_CAN_CTRL2_MRP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MRP field to a new value.
+#define BW_CAN_CTRL2_MRP(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_MRP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL2, field TASD[23:19] (RW)
+ *
+ * This 5-bit field indicates how many CAN bits the Tx arbitration process start
+ * point can be delayed from the first bit of CRC field on CAN bus. This field
+ * can be written only in Freeze mode because it is blocked by hardware in other
+ * modes. This field is useful to optimize the transmit performance based on
+ * factors such as: peripheral/serial clock ratio, CAN bit timing and number of MBs.
+ * The duration of an arbitration process, in terms of CAN bits, is directly
+ * proportional to the number of available MBs and CAN baud rate and inversely
+ * proportional to the peripheral clock frequency. The optimal arbitration timing is
+ * that in which the last MB is scanned right before the first bit of the
+ * Intermission field of a CAN frame. Therefore, if there are few MBs and the system/serial
+ * clock ratio is high and the CAN baud rate is low then the arbitration can be
+ * delayed and vice-versa. If TASD is 0 then the arbitration start is not
+ * delayed, thus the CPU has less time to configure a Tx MB for the next arbitration,
+ * but more time is reserved for arbitration. On the other hand, if TASD is 24 then
+ * the CPU can configure a Tx MB later and less time is reserved for
+ * arbitration. If too little time is reserved for arbitration the FlexCAN may be not able
+ * to find winner MBs in time to compete with other nodes for the CAN bus. If the
+ * arbitration ends too much time before the first bit of Intermission field then
+ * there is a chance that the CPU reconfigures some Tx MBs and the winner MB is
+ * not the best to be transmitted. The optimal configuration for TASD can be
+ * calculated as: TASD = 25 - {f CANCLK * [MAXMB + 3 - (RFEN * 8) - (RFEN * RFFN *
+ * 2)] * 2} / {f SYS * [1+(PSEG1+1)+(PSEG2+1)+(PROPSEG+1)] * (PRESDIV+1)} where: f
+ * CANCLK is the Protocol Engine (PE) Clock (see section "Protocol Timing"), in
+ * Hz f SYS is the peripheral clock, in Hz MAXMB is the value in CTRL1[MAXMB]
+ * field RFEN is the value in CTRL1[RFEN] bit RFFN is the value in CTRL2[RFFN] field
+ * PSEG1 is the value in CTRL1[PSEG1] field PSEG2 is the value in CTRL1[PSEG2]
+ * field PROPSEG is the value in CTRL1[PROPSEG] field PRESDIV is the value in
+ * CTRL1[PRESDIV] field See Section "Arbitration process" and Section "Protocol
+ * Timing" for more details.
+ */
+//@{
+#define BP_CAN_CTRL2_TASD (19U) //!< Bit position for CAN_CTRL2_TASD.
+#define BM_CAN_CTRL2_TASD (0x00F80000U) //!< Bit mask for CAN_CTRL2_TASD.
+#define BS_CAN_CTRL2_TASD (5U) //!< Bit field size in bits for CAN_CTRL2_TASD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL2_TASD field.
+#define BR_CAN_CTRL2_TASD(x) (HW_CAN_CTRL2(x).B.TASD)
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL2_TASD.
+#define BF_CAN_CTRL2_TASD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_TASD), uint32_t) & BM_CAN_CTRL2_TASD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TASD field to a new value.
+#define BW_CAN_CTRL2_TASD(x, v) (HW_CAN_CTRL2_WR(x, (HW_CAN_CTRL2_RD(x) & ~BM_CAN_CTRL2_TASD) | BF_CAN_CTRL2_TASD(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL2, field RFFN[27:24] (RW)
+ *
+ * This 4-bit field defines the number of Rx FIFO filters, as shown in the
+ * following table. The maximum selectable number of filters is determined by the MCU.
+ * This field can only be written in Freeze mode as it is blocked by hardware in
+ * other modes. This field must not be programmed with values that make the
+ * number of Message Buffers occupied by Rx FIFO and ID Filter exceed the number of
+ * Mailboxes present, defined by MCR[MAXMB]. Each group of eight filters occupies
+ * a memory space equivalent to two Message Buffers which means that the more
+ * filters are implemented the less Mailboxes will be available. Considering that
+ * the Rx FIFO occupies the memory space originally reserved for MB0-5, RFFN should
+ * be programmed with a value correponding to a number of filters not greater
+ * than the number of available memory words which can be calculated as follows:
+ * (SETUP_MB - 6) * 4 where SETUP_MB is the least between NUMBER_OF_MB and MAXMB.
+ * The number of remaining Mailboxes available will be: (SETUP_MB - 8) - (RFFN *
+ * 2) If the Number of Rx FIFO Filters programmed through RFFN exceeds the
+ * SETUP_MB value (memory space available) the exceeding ones will not be functional.
+ * RFFN[3:0] Number of Rx FIFO filters Message Buffers occupied by Rx FIFO and ID
+ * Filter Table Remaining Available MailboxesThe number of the last remaining
+ * available mailboxes is defined by the least value between the parameter
+ * NUMBER_OF_MB minus 1 and the MCR[MAXMB] field. Rx FIFO ID Filter Table Elements Affected
+ * by Rx Individual MasksIf Rx Individual Mask Registers are not enabled then
+ * all Rx FIFO filters are affected by the Rx FIFO Global Mask. Rx FIFO ID Filter
+ * Table Elements Affected by Rx FIFO Global Mask #rxfgmask-note 0x0 8 MB 0-7 MB
+ * 8-63 Elements 0-7 none 0x1 16 MB 0-9 MB 10-63 Elements 0-9 Elements 10-15 0x2
+ * 24 MB 0-11 MB 12-63 Elements 0-11 Elements 12-23 0x3 32 MB 0-13 MB 14-63
+ * Elements 0-13 Elements 14-31 0x4 40 MB 0-15 MB 16-63 Elements 0-15 Elements 16-39
+ * 0x5 48 MB 0-17 MB 18-63 Elements 0-17 Elements 18-47 0x6 56 MB 0-19 MB 20-63
+ * Elements 0-19 Elements 20-55 0x7 64 MB 0-21 MB 22-63 Elements 0-21 Elements 22-63
+ * 0x8 72 MB 0-23 MB 24-63 Elements 0-23 Elements 24-71 0x9 80 MB 0-25 MB 26-63
+ * Elements 0-25 Elements 26-79 0xA 88 MB 0-27 MB 28-63 Elements 0-27 Elements
+ * 28-87 0xB 96 MB 0-29 MB 30-63 Elements 0-29 Elements 30-95 0xC 104 MB 0-31 MB
+ * 32-63 Elements 0-31 Elements 32-103 0xD 112 MB 0-33 MB 34-63 Elements 0-31
+ * Elements 32-111 0xE 120 MB 0-35 MB 36-63 Elements 0-31 Elements 32-119 0xF 128 MB
+ * 0-37 MB 38-63 Elements 0-31 Elements 32-127
+ */
+//@{
+#define BP_CAN_CTRL2_RFFN (24U) //!< Bit position for CAN_CTRL2_RFFN.
+#define BM_CAN_CTRL2_RFFN (0x0F000000U) //!< Bit mask for CAN_CTRL2_RFFN.
+#define BS_CAN_CTRL2_RFFN (4U) //!< Bit field size in bits for CAN_CTRL2_RFFN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL2_RFFN field.
+#define BR_CAN_CTRL2_RFFN(x) (HW_CAN_CTRL2(x).B.RFFN)
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL2_RFFN.
+#define BF_CAN_CTRL2_RFFN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_RFFN), uint32_t) & BM_CAN_CTRL2_RFFN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RFFN field to a new value.
+#define BW_CAN_CTRL2_RFFN(x, v) (HW_CAN_CTRL2_WR(x, (HW_CAN_CTRL2_RD(x) & ~BM_CAN_CTRL2_RFFN) | BF_CAN_CTRL2_RFFN(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CTRL2, field WRMFRZ[28] (RW)
+ *
+ * Enable unrestricted write access to FlexCAN memory in Freeze mode. This bit
+ * can only be written in Freeze mode and has no effect out of Freeze mode.
+ *
+ * Values:
+ * - 0 - Maintain the write access restrictions.
+ * - 1 - Enable unrestricted write access to FlexCAN memory.
+ */
+//@{
+#define BP_CAN_CTRL2_WRMFRZ (28U) //!< Bit position for CAN_CTRL2_WRMFRZ.
+#define BM_CAN_CTRL2_WRMFRZ (0x10000000U) //!< Bit mask for CAN_CTRL2_WRMFRZ.
+#define BS_CAN_CTRL2_WRMFRZ (1U) //!< Bit field size in bits for CAN_CTRL2_WRMFRZ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CTRL2_WRMFRZ field.
+#define BR_CAN_CTRL2_WRMFRZ(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_WRMFRZ))
+#endif
+
+//! @brief Format value for bitfield CAN_CTRL2_WRMFRZ.
+#define BF_CAN_CTRL2_WRMFRZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CTRL2_WRMFRZ), uint32_t) & BM_CAN_CTRL2_WRMFRZ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WRMFRZ field to a new value.
+#define BW_CAN_CTRL2_WRMFRZ(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_WRMFRZ) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_ESR2 - Error and Status 2 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_ESR2 - Error and Status 2 register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register reflects various interrupt flags and some general status.
+ */
+typedef union _hw_can_esr2
+{
+ uint32_t U;
+ struct _hw_can_esr2_bitfields
+ {
+ uint32_t RESERVED0 : 13; //!< [12:0]
+ uint32_t IMB : 1; //!< [13] Inactive Mailbox
+ uint32_t VPS : 1; //!< [14] Valid Priority Status
+ uint32_t RESERVED1 : 1; //!< [15]
+ uint32_t LPTM : 7; //!< [22:16] Lowest Priority Tx Mailbox
+ uint32_t RESERVED2 : 9; //!< [31:23]
+ } B;
+} hw_can_esr2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_ESR2 register
+ */
+//@{
+#define HW_CAN_ESR2_ADDR(x) (REGS_CAN_BASE(x) + 0x38U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_ESR2(x) (*(__I hw_can_esr2_t *) HW_CAN_ESR2_ADDR(x))
+#define HW_CAN_ESR2_RD(x) (HW_CAN_ESR2(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_ESR2 bitfields
+ */
+
+/*!
+ * @name Register CAN_ESR2, field IMB[13] (RO)
+ *
+ * If ESR2[VPS] is asserted, this bit indicates whether there is any inactive
+ * Mailbox (CODE field is either 0b1000 or 0b0000). This bit is asserted in the
+ * following cases: During arbitration, if an LPTM is found and it is inactive. If
+ * IMB is not asserted and a frame is transmitted successfully. This bit is
+ * cleared in all start of arbitration (see Section "Arbitration process"). LPTM
+ * mechanism have the following behavior: if an MB is successfully transmitted and
+ * ESR2[IMB]=0 (no inactive Mailbox), then ESR2[VPS] and ESR2[IMB] are asserted and
+ * the index related to the MB just transmitted is loaded into ESR2[LPTM].
+ *
+ * Values:
+ * - 0 - If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
+ * - 1 - If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM
+ * content is the number of the first one.
+ */
+//@{
+#define BP_CAN_ESR2_IMB (13U) //!< Bit position for CAN_ESR2_IMB.
+#define BM_CAN_ESR2_IMB (0x00002000U) //!< Bit mask for CAN_ESR2_IMB.
+#define BS_CAN_ESR2_IMB (1U) //!< Bit field size in bits for CAN_ESR2_IMB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR2_IMB field.
+#define BR_CAN_ESR2_IMB(x) (BITBAND_ACCESS32(HW_CAN_ESR2_ADDR(x), BP_CAN_ESR2_IMB))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR2, field VPS[14] (RO)
+ *
+ * This bit indicates whether IMB and LPTM contents are currently valid or not.
+ * VPS is asserted upon every complete Tx arbitration process unless the CPU
+ * writes to Control and Status word of a Mailbox that has already been scanned, that
+ * is, it is behind Tx Arbitration Pointer, during the Tx arbitration process.
+ * If there is no inactive Mailbox and only one Tx Mailbox that is being
+ * transmitted then VPS is not asserted. VPS is negated upon the start of every Tx
+ * arbitration process or upon a write to Control and Status word of any Mailbox.
+ * ESR2[VPS] is not affected by any CPU write into Control Status (C/S) of a MB that is
+ * blocked by abort mechanism. When MCR[AEN] is asserted, the abort code write
+ * in C/S of a MB that is being transmitted (pending abort), or any write attempt
+ * into a Tx MB with IFLAG set is blocked.
+ *
+ * Values:
+ * - 0 - Contents of IMB and LPTM are invalid.
+ * - 1 - Contents of IMB and LPTM are valid.
+ */
+//@{
+#define BP_CAN_ESR2_VPS (14U) //!< Bit position for CAN_ESR2_VPS.
+#define BM_CAN_ESR2_VPS (0x00004000U) //!< Bit mask for CAN_ESR2_VPS.
+#define BS_CAN_ESR2_VPS (1U) //!< Bit field size in bits for CAN_ESR2_VPS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR2_VPS field.
+#define BR_CAN_ESR2_VPS(x) (BITBAND_ACCESS32(HW_CAN_ESR2_ADDR(x), BP_CAN_ESR2_VPS))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ESR2, field LPTM[22:16] (RO)
+ *
+ * If ESR2[VPS] is asserted, this field indicates the lowest number inactive
+ * Mailbox (see the IMB bit description). If there is no inactive Mailbox then the
+ * Mailbox indicated depends on CTRL1[LBUF] bit value. If CTRL1[LBUF] bit is
+ * negated then the Mailbox indicated is the one that has the greatest arbitration
+ * value (see the "Highest priority Mailbox first" section). If CTRL1[LBUF] bit is
+ * asserted then the Mailbox indicated is the highest number active Tx Mailbox. If
+ * a Tx Mailbox is being transmitted it is not considered in LPTM calculation.
+ * If ESR2[IMB] is not asserted and a frame is transmitted successfully, LPTM is
+ * updated with its Mailbox number.
+ */
+//@{
+#define BP_CAN_ESR2_LPTM (16U) //!< Bit position for CAN_ESR2_LPTM.
+#define BM_CAN_ESR2_LPTM (0x007F0000U) //!< Bit mask for CAN_ESR2_LPTM.
+#define BS_CAN_ESR2_LPTM (7U) //!< Bit field size in bits for CAN_ESR2_LPTM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ESR2_LPTM field.
+#define BR_CAN_ESR2_LPTM(x) (HW_CAN_ESR2(x).B.LPTM)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_CRCR - CRC Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_CRCR - CRC Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register provides information about the CRC of transmitted messages.
+ */
+typedef union _hw_can_crcr
+{
+ uint32_t U;
+ struct _hw_can_crcr_bitfields
+ {
+ uint32_t TXCRC : 15; //!< [14:0] CRC Transmitted
+ uint32_t RESERVED0 : 1; //!< [15]
+ uint32_t MBCRC : 7; //!< [22:16] CRC Mailbox
+ uint32_t RESERVED1 : 9; //!< [31:23]
+ } B;
+} hw_can_crcr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_CRCR register
+ */
+//@{
+#define HW_CAN_CRCR_ADDR(x) (REGS_CAN_BASE(x) + 0x44U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_CRCR(x) (*(__I hw_can_crcr_t *) HW_CAN_CRCR_ADDR(x))
+#define HW_CAN_CRCR_RD(x) (HW_CAN_CRCR(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_CRCR bitfields
+ */
+
+/*!
+ * @name Register CAN_CRCR, field TXCRC[14:0] (RO)
+ *
+ * This field indicates the CRC value of the last message transmitted. This
+ * field is updated at the same time the Tx Interrupt Flag is asserted.
+ */
+//@{
+#define BP_CAN_CRCR_TXCRC (0U) //!< Bit position for CAN_CRCR_TXCRC.
+#define BM_CAN_CRCR_TXCRC (0x00007FFFU) //!< Bit mask for CAN_CRCR_TXCRC.
+#define BS_CAN_CRCR_TXCRC (15U) //!< Bit field size in bits for CAN_CRCR_TXCRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CRCR_TXCRC field.
+#define BR_CAN_CRCR_TXCRC(x) (HW_CAN_CRCR(x).B.TXCRC)
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CRCR, field MBCRC[22:16] (RO)
+ *
+ * This field indicates the number of the Mailbox corresponding to the value in
+ * TXCRC field.
+ */
+//@{
+#define BP_CAN_CRCR_MBCRC (16U) //!< Bit position for CAN_CRCR_MBCRC.
+#define BM_CAN_CRCR_MBCRC (0x007F0000U) //!< Bit mask for CAN_CRCR_MBCRC.
+#define BS_CAN_CRCR_MBCRC (7U) //!< Bit field size in bits for CAN_CRCR_MBCRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CRCR_MBCRC field.
+#define BR_CAN_CRCR_MBCRC(x) (HW_CAN_CRCR(x).B.MBCRC)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_RXFGMASK - Rx FIFO Global Mask register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_RXFGMASK - Rx FIFO Global Mask register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. If Rx FIFO is enabled RXFGMASK is used to
+ * mask the Rx FIFO ID Filter Table elements that do not have a corresponding RXIMR
+ * according to CTRL2[RFFN] field setting. This register can only be written in
+ * Freeze mode as it is blocked by hardware in other modes.
+ */
+typedef union _hw_can_rxfgmask
+{
+ uint32_t U;
+ struct _hw_can_rxfgmask_bitfields
+ {
+ uint32_t FGM : 32; //!< [31:0] Rx FIFO Global Mask Bits
+ } B;
+} hw_can_rxfgmask_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_RXFGMASK register
+ */
+//@{
+#define HW_CAN_RXFGMASK_ADDR(x) (REGS_CAN_BASE(x) + 0x48U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_RXFGMASK(x) (*(__IO hw_can_rxfgmask_t *) HW_CAN_RXFGMASK_ADDR(x))
+#define HW_CAN_RXFGMASK_RD(x) (HW_CAN_RXFGMASK(x).U)
+#define HW_CAN_RXFGMASK_WR(x, v) (HW_CAN_RXFGMASK(x).U = (v))
+#define HW_CAN_RXFGMASK_SET(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) | (v)))
+#define HW_CAN_RXFGMASK_CLR(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) & ~(v)))
+#define HW_CAN_RXFGMASK_TOG(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_RXFGMASK bitfields
+ */
+
+/*!
+ * @name Register CAN_RXFGMASK, field FGM[31:0] (RW)
+ *
+ * These bits mask the ID Filter Table elements bits in a perfect alignment. The
+ * following table shows how the FGM bits correspond to each IDAF field. Rx FIFO
+ * ID Filter Table Elements Format (MCR[IDAM]) Identifier Acceptance Filter
+ * Fields RTR IDE RXIDA RXIDB If MCR[IDAM] field is equivalent to the format B only
+ * the fourteen most significant bits of the Identifier of the incoming frame are
+ * compared with the Rx FIFO filter. RXIDC If MCR[IDAM] field is equivalent to
+ * the format C only the eight most significant bits of the Identifier of the
+ * incoming frame are compared with the Rx FIFO filter. Reserved A FGM[31] FGM[30]
+ * FGM[29:1] - - FGM[0] B FGM[31], FGM[15] FGM[30], FGM[14] - FGM[29:16], FGM[13:0]
+ * - C - - - FGM[31:24], FGM[23:16], FGM[15:8], FGM[7:0]
+ *
+ * Values:
+ * - 0 - The corresponding bit in the filter is "don't care."
+ * - 1 - The corresponding bit in the filter is checked.
+ */
+//@{
+#define BP_CAN_RXFGMASK_FGM (0U) //!< Bit position for CAN_RXFGMASK_FGM.
+#define BM_CAN_RXFGMASK_FGM (0xFFFFFFFFU) //!< Bit mask for CAN_RXFGMASK_FGM.
+#define BS_CAN_RXFGMASK_FGM (32U) //!< Bit field size in bits for CAN_RXFGMASK_FGM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_RXFGMASK_FGM field.
+#define BR_CAN_RXFGMASK_FGM(x) (HW_CAN_RXFGMASK(x).U)
+#endif
+
+//! @brief Format value for bitfield CAN_RXFGMASK_FGM.
+#define BF_CAN_RXFGMASK_FGM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_RXFGMASK_FGM), uint32_t) & BM_CAN_RXFGMASK_FGM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FGM field to a new value.
+#define BW_CAN_RXFGMASK_FGM(x, v) (HW_CAN_RXFGMASK_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_RXFIR - Rx FIFO Information Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_RXFIR - Rx FIFO Information Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFIR provides information on Rx FIFO. This register is the port through
+ * which the CPU accesses the output of the RXFIR FIFO located in RAM. The RXFIR FIFO
+ * is written by the FlexCAN whenever a new message is moved into the Rx FIFO as
+ * well as its output is updated whenever the output of the Rx FIFO is updated
+ * with the next message. See Section "Rx FIFO" for instructions on reading this
+ * register.
+ */
+typedef union _hw_can_rxfir
+{
+ uint32_t U;
+ struct _hw_can_rxfir_bitfields
+ {
+ uint32_t IDHIT : 9; //!< [8:0] Identifier Acceptance Filter Hit
+ //! Indicator
+ uint32_t RESERVED0 : 23; //!< [31:9]
+ } B;
+} hw_can_rxfir_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_RXFIR register
+ */
+//@{
+#define HW_CAN_RXFIR_ADDR(x) (REGS_CAN_BASE(x) + 0x4CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_RXFIR(x) (*(__I hw_can_rxfir_t *) HW_CAN_RXFIR_ADDR(x))
+#define HW_CAN_RXFIR_RD(x) (HW_CAN_RXFIR(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_RXFIR bitfields
+ */
+
+/*!
+ * @name Register CAN_RXFIR, field IDHIT[8:0] (RO)
+ *
+ * This field indicates which Identifier Acceptance Filter was hit by the
+ * received message that is in the output of the Rx FIFO. If multiple filters match the
+ * incoming message ID then the first matching IDAF found (lowest number) by the
+ * matching process is indicated. This field is valid only while the
+ * IFLAG[BUF5I] is asserted.
+ */
+//@{
+#define BP_CAN_RXFIR_IDHIT (0U) //!< Bit position for CAN_RXFIR_IDHIT.
+#define BM_CAN_RXFIR_IDHIT (0x000001FFU) //!< Bit mask for CAN_RXFIR_IDHIT.
+#define BS_CAN_RXFIR_IDHIT (9U) //!< Bit field size in bits for CAN_RXFIR_IDHIT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_RXFIR_IDHIT field.
+#define BR_CAN_RXFIR_IDHIT(x) (HW_CAN_RXFIR(x).B.IDHIT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_CS - Message Buffer 0 CS Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_CS - Message Buffer 0 CS Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_can_cs
+{
+ uint32_t U;
+ struct _hw_can_cs_bitfields
+ {
+ uint32_t TIME_STAMP : 16; //!< [15:0] Free-Running Counter Time
+ //! stamp. This 16-bit field is a copy of the Free-Running Timer, captured for
+ //! Tx and Rx frames at the time when the beginning of the Identifier
+ //! field appears on the CAN bus.
+ uint32_t DLC : 4; //!< [19:16] Length of the data to be
+ //! stored/transmitted.
+ uint32_t RTR : 1; //!< [20] Remote Transmission Request. One/zero for
+ //! remote/data frame.
+ uint32_t IDE : 1; //!< [21] ID Extended. One/zero for
+ //! extended/standard format frame.
+ uint32_t SRR : 1; //!< [22] Substitute Remote Request. Contains a
+ //! fixed recessive bit.
+ uint32_t RESERVED0 : 1; //!< [23] Reserved
+ uint32_t CODE : 4; //!< [27:24] Reserved
+ uint32_t RESERVED1 : 4; //!< [31:28] Reserved
+ } B;
+} hw_can_cs_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_CS register
+ */
+//@{
+#define HW_CAN_CS_COUNT (16U)
+
+#define HW_CAN_CS_ADDR(x, n) (REGS_CAN_BASE(x) + 0x80U + (0x10U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_CS(x, n) (*(__IO hw_can_cs_t *) HW_CAN_CS_ADDR(x, n))
+#define HW_CAN_CS_RD(x, n) (HW_CAN_CS(x, n).U)
+#define HW_CAN_CS_WR(x, n, v) (HW_CAN_CS(x, n).U = (v))
+#define HW_CAN_CS_SET(x, n, v) (HW_CAN_CS_WR(x, n, HW_CAN_CS_RD(x, n) | (v)))
+#define HW_CAN_CS_CLR(x, n, v) (HW_CAN_CS_WR(x, n, HW_CAN_CS_RD(x, n) & ~(v)))
+#define HW_CAN_CS_TOG(x, n, v) (HW_CAN_CS_WR(x, n, HW_CAN_CS_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_CS bitfields
+ */
+
+/*!
+ * @name Register CAN_CS, field TIME_STAMP[15:0] (RW)
+ */
+//@{
+#define BP_CAN_CS_TIME_STAMP (0U) //!< Bit position for CAN_CS_TIME_STAMP.
+#define BM_CAN_CS_TIME_STAMP (0x0000FFFFU) //!< Bit mask for CAN_CS_TIME_STAMP.
+#define BS_CAN_CS_TIME_STAMP (16U) //!< Bit field size in bits for CAN_CS_TIME_STAMP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CS_TIME_STAMP field.
+#define BR_CAN_CS_TIME_STAMP(x, n) (HW_CAN_CS(x, n).B.TIME_STAMP)
+#endif
+
+//! @brief Format value for bitfield CAN_CS_TIME_STAMP.
+#define BF_CAN_CS_TIME_STAMP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_TIME_STAMP), uint32_t) & BM_CAN_CS_TIME_STAMP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TIME_STAMP field to a new value.
+#define BW_CAN_CS_TIME_STAMP(x, n, v) (HW_CAN_CS_WR(x, n, (HW_CAN_CS_RD(x, n) & ~BM_CAN_CS_TIME_STAMP) | BF_CAN_CS_TIME_STAMP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CS, field DLC[19:16] (RW)
+ */
+//@{
+#define BP_CAN_CS_DLC (16U) //!< Bit position for CAN_CS_DLC.
+#define BM_CAN_CS_DLC (0x000F0000U) //!< Bit mask for CAN_CS_DLC.
+#define BS_CAN_CS_DLC (4U) //!< Bit field size in bits for CAN_CS_DLC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CS_DLC field.
+#define BR_CAN_CS_DLC(x, n) (HW_CAN_CS(x, n).B.DLC)
+#endif
+
+//! @brief Format value for bitfield CAN_CS_DLC.
+#define BF_CAN_CS_DLC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_DLC), uint32_t) & BM_CAN_CS_DLC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DLC field to a new value.
+#define BW_CAN_CS_DLC(x, n, v) (HW_CAN_CS_WR(x, n, (HW_CAN_CS_RD(x, n) & ~BM_CAN_CS_DLC) | BF_CAN_CS_DLC(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CS, field RTR[20] (RW)
+ */
+//@{
+#define BP_CAN_CS_RTR (20U) //!< Bit position for CAN_CS_RTR.
+#define BM_CAN_CS_RTR (0x00100000U) //!< Bit mask for CAN_CS_RTR.
+#define BS_CAN_CS_RTR (1U) //!< Bit field size in bits for CAN_CS_RTR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CS_RTR field.
+#define BR_CAN_CS_RTR(x, n) (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_RTR))
+#endif
+
+//! @brief Format value for bitfield CAN_CS_RTR.
+#define BF_CAN_CS_RTR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_RTR), uint32_t) & BM_CAN_CS_RTR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RTR field to a new value.
+#define BW_CAN_CS_RTR(x, n, v) (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_RTR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CS, field IDE[21] (RW)
+ */
+//@{
+#define BP_CAN_CS_IDE (21U) //!< Bit position for CAN_CS_IDE.
+#define BM_CAN_CS_IDE (0x00200000U) //!< Bit mask for CAN_CS_IDE.
+#define BS_CAN_CS_IDE (1U) //!< Bit field size in bits for CAN_CS_IDE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CS_IDE field.
+#define BR_CAN_CS_IDE(x, n) (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_IDE))
+#endif
+
+//! @brief Format value for bitfield CAN_CS_IDE.
+#define BF_CAN_CS_IDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_IDE), uint32_t) & BM_CAN_CS_IDE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IDE field to a new value.
+#define BW_CAN_CS_IDE(x, n, v) (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_IDE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CS, field SRR[22] (RW)
+ */
+//@{
+#define BP_CAN_CS_SRR (22U) //!< Bit position for CAN_CS_SRR.
+#define BM_CAN_CS_SRR (0x00400000U) //!< Bit mask for CAN_CS_SRR.
+#define BS_CAN_CS_SRR (1U) //!< Bit field size in bits for CAN_CS_SRR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CS_SRR field.
+#define BR_CAN_CS_SRR(x, n) (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_SRR))
+#endif
+
+//! @brief Format value for bitfield CAN_CS_SRR.
+#define BF_CAN_CS_SRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_SRR), uint32_t) & BM_CAN_CS_SRR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SRR field to a new value.
+#define BW_CAN_CS_SRR(x, n, v) (BITBAND_ACCESS32(HW_CAN_CS_ADDR(x, n), BP_CAN_CS_SRR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_CS, field CODE[27:24] (RW)
+ */
+//@{
+#define BP_CAN_CS_CODE (24U) //!< Bit position for CAN_CS_CODE.
+#define BM_CAN_CS_CODE (0x0F000000U) //!< Bit mask for CAN_CS_CODE.
+#define BS_CAN_CS_CODE (4U) //!< Bit field size in bits for CAN_CS_CODE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_CS_CODE field.
+#define BR_CAN_CS_CODE(x, n) (HW_CAN_CS(x, n).B.CODE)
+#endif
+
+//! @brief Format value for bitfield CAN_CS_CODE.
+#define BF_CAN_CS_CODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_CS_CODE), uint32_t) & BM_CAN_CS_CODE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CODE field to a new value.
+#define BW_CAN_CS_CODE(x, n, v) (HW_CAN_CS_WR(x, n, (HW_CAN_CS_RD(x, n) & ~BM_CAN_CS_CODE) | BF_CAN_CS_CODE(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CAN_ID - Message Buffer 0 ID Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_ID - Message Buffer 0 ID Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_can_id
+{
+ uint32_t U;
+ struct _hw_can_id_bitfields
+ {
+ uint32_t EXT : 18; //!< [17:0] Contains extended (LOW word)
+ //! identifier of message buffer.
+ uint32_t STD : 11; //!< [28:18] Contains standard/extended (HIGH
+ //! word) identifier of message buffer.
+ uint32_t PRIO : 3; //!< [31:29] Local priority. This 3-bit fieldis
+ //! only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx
+ //! buffers. These bits are not transmitted. They are appended to the
+ //! regular ID to define the transmission priority.
+ } B;
+} hw_can_id_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_ID register
+ */
+//@{
+#define HW_CAN_ID_COUNT (16U)
+
+#define HW_CAN_ID_ADDR(x, n) (REGS_CAN_BASE(x) + 0x84U + (0x10U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_ID(x, n) (*(__IO hw_can_id_t *) HW_CAN_ID_ADDR(x, n))
+#define HW_CAN_ID_RD(x, n) (HW_CAN_ID(x, n).U)
+#define HW_CAN_ID_WR(x, n, v) (HW_CAN_ID(x, n).U = (v))
+#define HW_CAN_ID_SET(x, n, v) (HW_CAN_ID_WR(x, n, HW_CAN_ID_RD(x, n) | (v)))
+#define HW_CAN_ID_CLR(x, n, v) (HW_CAN_ID_WR(x, n, HW_CAN_ID_RD(x, n) & ~(v)))
+#define HW_CAN_ID_TOG(x, n, v) (HW_CAN_ID_WR(x, n, HW_CAN_ID_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_ID bitfields
+ */
+
+/*!
+ * @name Register CAN_ID, field EXT[17:0] (RW)
+ */
+//@{
+#define BP_CAN_ID_EXT (0U) //!< Bit position for CAN_ID_EXT.
+#define BM_CAN_ID_EXT (0x0003FFFFU) //!< Bit mask for CAN_ID_EXT.
+#define BS_CAN_ID_EXT (18U) //!< Bit field size in bits for CAN_ID_EXT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ID_EXT field.
+#define BR_CAN_ID_EXT(x, n) (HW_CAN_ID(x, n).B.EXT)
+#endif
+
+//! @brief Format value for bitfield CAN_ID_EXT.
+#define BF_CAN_ID_EXT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ID_EXT), uint32_t) & BM_CAN_ID_EXT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EXT field to a new value.
+#define BW_CAN_ID_EXT(x, n, v) (HW_CAN_ID_WR(x, n, (HW_CAN_ID_RD(x, n) & ~BM_CAN_ID_EXT) | BF_CAN_ID_EXT(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ID, field STD[28:18] (RW)
+ */
+//@{
+#define BP_CAN_ID_STD (18U) //!< Bit position for CAN_ID_STD.
+#define BM_CAN_ID_STD (0x1FFC0000U) //!< Bit mask for CAN_ID_STD.
+#define BS_CAN_ID_STD (11U) //!< Bit field size in bits for CAN_ID_STD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ID_STD field.
+#define BR_CAN_ID_STD(x, n) (HW_CAN_ID(x, n).B.STD)
+#endif
+
+//! @brief Format value for bitfield CAN_ID_STD.
+#define BF_CAN_ID_STD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ID_STD), uint32_t) & BM_CAN_ID_STD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the STD field to a new value.
+#define BW_CAN_ID_STD(x, n, v) (HW_CAN_ID_WR(x, n, (HW_CAN_ID_RD(x, n) & ~BM_CAN_ID_STD) | BF_CAN_ID_STD(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_ID, field PRIO[31:29] (RW)
+ */
+//@{
+#define BP_CAN_ID_PRIO (29U) //!< Bit position for CAN_ID_PRIO.
+#define BM_CAN_ID_PRIO (0xE0000000U) //!< Bit mask for CAN_ID_PRIO.
+#define BS_CAN_ID_PRIO (3U) //!< Bit field size in bits for CAN_ID_PRIO.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_ID_PRIO field.
+#define BR_CAN_ID_PRIO(x, n) (HW_CAN_ID(x, n).B.PRIO)
+#endif
+
+//! @brief Format value for bitfield CAN_ID_PRIO.
+#define BF_CAN_ID_PRIO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_ID_PRIO), uint32_t) & BM_CAN_ID_PRIO)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PRIO field to a new value.
+#define BW_CAN_ID_PRIO(x, n, v) (HW_CAN_ID_WR(x, n, (HW_CAN_ID_RD(x, n) & ~BM_CAN_ID_PRIO) | BF_CAN_ID_PRIO(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CAN_WORD0 - Message Buffer 0 WORD0 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_WORD0 - Message Buffer 0 WORD0 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_can_word0
+{
+ uint32_t U;
+ struct _hw_can_word0_bitfields
+ {
+ uint32_t DATA_BYTE_3 : 8; //!< [7:0] Data byte 3 of Rx/Tx frame.
+ uint32_t DATA_BYTE_2 : 8; //!< [15:8] Data byte 2 of Rx/Tx frame.
+ uint32_t DATA_BYTE_1 : 8; //!< [23:16] Data byte 1 of Rx/Tx frame.
+ uint32_t DATA_BYTE_0 : 8; //!< [31:24] Data byte 0 of Rx/Tx frame.
+ } B;
+} hw_can_word0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_WORD0 register
+ */
+//@{
+#define HW_CAN_WORD0_COUNT (16U)
+
+#define HW_CAN_WORD0_ADDR(x, n) (REGS_CAN_BASE(x) + 0x88U + (0x10U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_WORD0(x, n) (*(__IO hw_can_word0_t *) HW_CAN_WORD0_ADDR(x, n))
+#define HW_CAN_WORD0_RD(x, n) (HW_CAN_WORD0(x, n).U)
+#define HW_CAN_WORD0_WR(x, n, v) (HW_CAN_WORD0(x, n).U = (v))
+#define HW_CAN_WORD0_SET(x, n, v) (HW_CAN_WORD0_WR(x, n, HW_CAN_WORD0_RD(x, n) | (v)))
+#define HW_CAN_WORD0_CLR(x, n, v) (HW_CAN_WORD0_WR(x, n, HW_CAN_WORD0_RD(x, n) & ~(v)))
+#define HW_CAN_WORD0_TOG(x, n, v) (HW_CAN_WORD0_WR(x, n, HW_CAN_WORD0_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_WORD0 bitfields
+ */
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_3[7:0] (RW)
+ */
+//@{
+#define BP_CAN_WORD0_DATA_BYTE_3 (0U) //!< Bit position for CAN_WORD0_DATA_BYTE_3.
+#define BM_CAN_WORD0_DATA_BYTE_3 (0x000000FFU) //!< Bit mask for CAN_WORD0_DATA_BYTE_3.
+#define BS_CAN_WORD0_DATA_BYTE_3 (8U) //!< Bit field size in bits for CAN_WORD0_DATA_BYTE_3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_WORD0_DATA_BYTE_3 field.
+#define BR_CAN_WORD0_DATA_BYTE_3(x, n) (HW_CAN_WORD0(x, n).B.DATA_BYTE_3)
+#endif
+
+//! @brief Format value for bitfield CAN_WORD0_DATA_BYTE_3.
+#define BF_CAN_WORD0_DATA_BYTE_3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD0_DATA_BYTE_3), uint32_t) & BM_CAN_WORD0_DATA_BYTE_3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATA_BYTE_3 field to a new value.
+#define BW_CAN_WORD0_DATA_BYTE_3(x, n, v) (HW_CAN_WORD0_WR(x, n, (HW_CAN_WORD0_RD(x, n) & ~BM_CAN_WORD0_DATA_BYTE_3) | BF_CAN_WORD0_DATA_BYTE_3(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_2[15:8] (RW)
+ */
+//@{
+#define BP_CAN_WORD0_DATA_BYTE_2 (8U) //!< Bit position for CAN_WORD0_DATA_BYTE_2.
+#define BM_CAN_WORD0_DATA_BYTE_2 (0x0000FF00U) //!< Bit mask for CAN_WORD0_DATA_BYTE_2.
+#define BS_CAN_WORD0_DATA_BYTE_2 (8U) //!< Bit field size in bits for CAN_WORD0_DATA_BYTE_2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_WORD0_DATA_BYTE_2 field.
+#define BR_CAN_WORD0_DATA_BYTE_2(x, n) (HW_CAN_WORD0(x, n).B.DATA_BYTE_2)
+#endif
+
+//! @brief Format value for bitfield CAN_WORD0_DATA_BYTE_2.
+#define BF_CAN_WORD0_DATA_BYTE_2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD0_DATA_BYTE_2), uint32_t) & BM_CAN_WORD0_DATA_BYTE_2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATA_BYTE_2 field to a new value.
+#define BW_CAN_WORD0_DATA_BYTE_2(x, n, v) (HW_CAN_WORD0_WR(x, n, (HW_CAN_WORD0_RD(x, n) & ~BM_CAN_WORD0_DATA_BYTE_2) | BF_CAN_WORD0_DATA_BYTE_2(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_1[23:16] (RW)
+ */
+//@{
+#define BP_CAN_WORD0_DATA_BYTE_1 (16U) //!< Bit position for CAN_WORD0_DATA_BYTE_1.
+#define BM_CAN_WORD0_DATA_BYTE_1 (0x00FF0000U) //!< Bit mask for CAN_WORD0_DATA_BYTE_1.
+#define BS_CAN_WORD0_DATA_BYTE_1 (8U) //!< Bit field size in bits for CAN_WORD0_DATA_BYTE_1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_WORD0_DATA_BYTE_1 field.
+#define BR_CAN_WORD0_DATA_BYTE_1(x, n) (HW_CAN_WORD0(x, n).B.DATA_BYTE_1)
+#endif
+
+//! @brief Format value for bitfield CAN_WORD0_DATA_BYTE_1.
+#define BF_CAN_WORD0_DATA_BYTE_1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD0_DATA_BYTE_1), uint32_t) & BM_CAN_WORD0_DATA_BYTE_1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATA_BYTE_1 field to a new value.
+#define BW_CAN_WORD0_DATA_BYTE_1(x, n, v) (HW_CAN_WORD0_WR(x, n, (HW_CAN_WORD0_RD(x, n) & ~BM_CAN_WORD0_DATA_BYTE_1) | BF_CAN_WORD0_DATA_BYTE_1(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_0[31:24] (RW)
+ */
+//@{
+#define BP_CAN_WORD0_DATA_BYTE_0 (24U) //!< Bit position for CAN_WORD0_DATA_BYTE_0.
+#define BM_CAN_WORD0_DATA_BYTE_0 (0xFF000000U) //!< Bit mask for CAN_WORD0_DATA_BYTE_0.
+#define BS_CAN_WORD0_DATA_BYTE_0 (8U) //!< Bit field size in bits for CAN_WORD0_DATA_BYTE_0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_WORD0_DATA_BYTE_0 field.
+#define BR_CAN_WORD0_DATA_BYTE_0(x, n) (HW_CAN_WORD0(x, n).B.DATA_BYTE_0)
+#endif
+
+//! @brief Format value for bitfield CAN_WORD0_DATA_BYTE_0.
+#define BF_CAN_WORD0_DATA_BYTE_0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD0_DATA_BYTE_0), uint32_t) & BM_CAN_WORD0_DATA_BYTE_0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATA_BYTE_0 field to a new value.
+#define BW_CAN_WORD0_DATA_BYTE_0(x, n, v) (HW_CAN_WORD0_WR(x, n, (HW_CAN_WORD0_RD(x, n) & ~BM_CAN_WORD0_DATA_BYTE_0) | BF_CAN_WORD0_DATA_BYTE_0(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CAN_WORD1 - Message Buffer 0 WORD1 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_WORD1 - Message Buffer 0 WORD1 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_can_word1
+{
+ uint32_t U;
+ struct _hw_can_word1_bitfields
+ {
+ uint32_t DATA_BYTE_7 : 8; //!< [7:0] Data byte 7 of Rx/Tx frame.
+ uint32_t DATA_BYTE_6 : 8; //!< [15:8] Data byte 6 of Rx/Tx frame.
+ uint32_t DATA_BYTE_5 : 8; //!< [23:16] Data byte 5 of Rx/Tx frame.
+ uint32_t DATA_BYTE_4 : 8; //!< [31:24] Data byte 4 of Rx/Tx frame.
+ } B;
+} hw_can_word1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_WORD1 register
+ */
+//@{
+#define HW_CAN_WORD1_COUNT (16U)
+
+#define HW_CAN_WORD1_ADDR(x, n) (REGS_CAN_BASE(x) + 0x8CU + (0x10U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_WORD1(x, n) (*(__IO hw_can_word1_t *) HW_CAN_WORD1_ADDR(x, n))
+#define HW_CAN_WORD1_RD(x, n) (HW_CAN_WORD1(x, n).U)
+#define HW_CAN_WORD1_WR(x, n, v) (HW_CAN_WORD1(x, n).U = (v))
+#define HW_CAN_WORD1_SET(x, n, v) (HW_CAN_WORD1_WR(x, n, HW_CAN_WORD1_RD(x, n) | (v)))
+#define HW_CAN_WORD1_CLR(x, n, v) (HW_CAN_WORD1_WR(x, n, HW_CAN_WORD1_RD(x, n) & ~(v)))
+#define HW_CAN_WORD1_TOG(x, n, v) (HW_CAN_WORD1_WR(x, n, HW_CAN_WORD1_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_WORD1 bitfields
+ */
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_7[7:0] (RW)
+ */
+//@{
+#define BP_CAN_WORD1_DATA_BYTE_7 (0U) //!< Bit position for CAN_WORD1_DATA_BYTE_7.
+#define BM_CAN_WORD1_DATA_BYTE_7 (0x000000FFU) //!< Bit mask for CAN_WORD1_DATA_BYTE_7.
+#define BS_CAN_WORD1_DATA_BYTE_7 (8U) //!< Bit field size in bits for CAN_WORD1_DATA_BYTE_7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_WORD1_DATA_BYTE_7 field.
+#define BR_CAN_WORD1_DATA_BYTE_7(x, n) (HW_CAN_WORD1(x, n).B.DATA_BYTE_7)
+#endif
+
+//! @brief Format value for bitfield CAN_WORD1_DATA_BYTE_7.
+#define BF_CAN_WORD1_DATA_BYTE_7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD1_DATA_BYTE_7), uint32_t) & BM_CAN_WORD1_DATA_BYTE_7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATA_BYTE_7 field to a new value.
+#define BW_CAN_WORD1_DATA_BYTE_7(x, n, v) (HW_CAN_WORD1_WR(x, n, (HW_CAN_WORD1_RD(x, n) & ~BM_CAN_WORD1_DATA_BYTE_7) | BF_CAN_WORD1_DATA_BYTE_7(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_6[15:8] (RW)
+ */
+//@{
+#define BP_CAN_WORD1_DATA_BYTE_6 (8U) //!< Bit position for CAN_WORD1_DATA_BYTE_6.
+#define BM_CAN_WORD1_DATA_BYTE_6 (0x0000FF00U) //!< Bit mask for CAN_WORD1_DATA_BYTE_6.
+#define BS_CAN_WORD1_DATA_BYTE_6 (8U) //!< Bit field size in bits for CAN_WORD1_DATA_BYTE_6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_WORD1_DATA_BYTE_6 field.
+#define BR_CAN_WORD1_DATA_BYTE_6(x, n) (HW_CAN_WORD1(x, n).B.DATA_BYTE_6)
+#endif
+
+//! @brief Format value for bitfield CAN_WORD1_DATA_BYTE_6.
+#define BF_CAN_WORD1_DATA_BYTE_6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD1_DATA_BYTE_6), uint32_t) & BM_CAN_WORD1_DATA_BYTE_6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATA_BYTE_6 field to a new value.
+#define BW_CAN_WORD1_DATA_BYTE_6(x, n, v) (HW_CAN_WORD1_WR(x, n, (HW_CAN_WORD1_RD(x, n) & ~BM_CAN_WORD1_DATA_BYTE_6) | BF_CAN_WORD1_DATA_BYTE_6(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_5[23:16] (RW)
+ */
+//@{
+#define BP_CAN_WORD1_DATA_BYTE_5 (16U) //!< Bit position for CAN_WORD1_DATA_BYTE_5.
+#define BM_CAN_WORD1_DATA_BYTE_5 (0x00FF0000U) //!< Bit mask for CAN_WORD1_DATA_BYTE_5.
+#define BS_CAN_WORD1_DATA_BYTE_5 (8U) //!< Bit field size in bits for CAN_WORD1_DATA_BYTE_5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_WORD1_DATA_BYTE_5 field.
+#define BR_CAN_WORD1_DATA_BYTE_5(x, n) (HW_CAN_WORD1(x, n).B.DATA_BYTE_5)
+#endif
+
+//! @brief Format value for bitfield CAN_WORD1_DATA_BYTE_5.
+#define BF_CAN_WORD1_DATA_BYTE_5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD1_DATA_BYTE_5), uint32_t) & BM_CAN_WORD1_DATA_BYTE_5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATA_BYTE_5 field to a new value.
+#define BW_CAN_WORD1_DATA_BYTE_5(x, n, v) (HW_CAN_WORD1_WR(x, n, (HW_CAN_WORD1_RD(x, n) & ~BM_CAN_WORD1_DATA_BYTE_5) | BF_CAN_WORD1_DATA_BYTE_5(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_4[31:24] (RW)
+ */
+//@{
+#define BP_CAN_WORD1_DATA_BYTE_4 (24U) //!< Bit position for CAN_WORD1_DATA_BYTE_4.
+#define BM_CAN_WORD1_DATA_BYTE_4 (0xFF000000U) //!< Bit mask for CAN_WORD1_DATA_BYTE_4.
+#define BS_CAN_WORD1_DATA_BYTE_4 (8U) //!< Bit field size in bits for CAN_WORD1_DATA_BYTE_4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_WORD1_DATA_BYTE_4 field.
+#define BR_CAN_WORD1_DATA_BYTE_4(x, n) (HW_CAN_WORD1(x, n).B.DATA_BYTE_4)
+#endif
+
+//! @brief Format value for bitfield CAN_WORD1_DATA_BYTE_4.
+#define BF_CAN_WORD1_DATA_BYTE_4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_WORD1_DATA_BYTE_4), uint32_t) & BM_CAN_WORD1_DATA_BYTE_4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATA_BYTE_4 field to a new value.
+#define BW_CAN_WORD1_DATA_BYTE_4(x, n, v) (HW_CAN_WORD1_WR(x, n, (HW_CAN_WORD1_RD(x, n) & ~BM_CAN_WORD1_DATA_BYTE_4) | BF_CAN_WORD1_DATA_BYTE_4(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAN_RXIMRn - Rx Individual Mask Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAN_RXIMRn - Rx Individual Mask Registers (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers are located in RAM. RXIMR are used as acceptance masks for ID
+ * filtering in Rx MBs and the Rx FIFO. If the Rx FIFO is not enabled, one mask
+ * register is provided for each available Mailbox, providing ID masking
+ * capability on a per Mailbox basis. When the Rx FIFO is enabled (MCR[RFEN] bit is
+ * asserted), up to 32 Rx Individual Mask Registers can apply to the Rx FIFO ID Filter
+ * Table elements on a one-to-one correspondence depending on the setting of
+ * CTRL2[RFFN]. RXIMR can only be written by the CPU while the module is in Freeze
+ * mode; otherwise, they are blocked by hardware. The Individual Rx Mask Registers
+ * are not affected by reset and must be explicitly initialized prior to any
+ * reception.
+ */
+typedef union _hw_can_rximrn
+{
+ uint32_t U;
+ struct _hw_can_rximrn_bitfields
+ {
+ uint32_t MI : 32; //!< [31:0] Individual Mask Bits
+ } B;
+} hw_can_rximrn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAN_RXIMRn register
+ */
+//@{
+#define HW_CAN_RXIMRn_COUNT (16U)
+
+#define HW_CAN_RXIMRn_ADDR(x, n) (REGS_CAN_BASE(x) + 0x880U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAN_RXIMRn(x, n) (*(__IO hw_can_rximrn_t *) HW_CAN_RXIMRn_ADDR(x, n))
+#define HW_CAN_RXIMRn_RD(x, n) (HW_CAN_RXIMRn(x, n).U)
+#define HW_CAN_RXIMRn_WR(x, n, v) (HW_CAN_RXIMRn(x, n).U = (v))
+#define HW_CAN_RXIMRn_SET(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) | (v)))
+#define HW_CAN_RXIMRn_CLR(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) & ~(v)))
+#define HW_CAN_RXIMRn_TOG(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAN_RXIMRn bitfields
+ */
+
+/*!
+ * @name Register CAN_RXIMRn, field MI[31:0] (RW)
+ *
+ * Each Individual Mask Bit masks the corresponding bit in both the Mailbox
+ * filter and Rx FIFO ID Filter Table element in distinct ways. For Mailbox filters,
+ * see the RXMGMASK register description. For Rx FIFO ID Filter Table elements,
+ * see the RXFGMASK register description.
+ *
+ * Values:
+ * - 0 - The corresponding bit in the filter is "don't care."
+ * - 1 - The corresponding bit in the filter is checked.
+ */
+//@{
+#define BP_CAN_RXIMRn_MI (0U) //!< Bit position for CAN_RXIMRn_MI.
+#define BM_CAN_RXIMRn_MI (0xFFFFFFFFU) //!< Bit mask for CAN_RXIMRn_MI.
+#define BS_CAN_RXIMRn_MI (32U) //!< Bit field size in bits for CAN_RXIMRn_MI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAN_RXIMRn_MI field.
+#define BR_CAN_RXIMRn_MI(x, n) (HW_CAN_RXIMRn(x, n).U)
+#endif
+
+//! @brief Format value for bitfield CAN_RXIMRn_MI.
+#define BF_CAN_RXIMRn_MI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAN_RXIMRn_MI), uint32_t) & BM_CAN_RXIMRn_MI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MI field to a new value.
+#define BW_CAN_RXIMRn_MI(x, n, v) (HW_CAN_RXIMRn_WR(x, n, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_can_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All CAN module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_can
+{
+ __IO hw_can_mcr_t MCR; //!< [0x0] Module Configuration Register
+ __IO hw_can_ctrl1_t CTRL1; //!< [0x4] Control 1 register
+ __IO hw_can_timer_t TIMER; //!< [0x8] Free Running Timer
+ uint8_t _reserved0[4];
+ __IO hw_can_rxmgmask_t RXMGMASK; //!< [0x10] Rx Mailboxes Global Mask Register
+ __IO hw_can_rx14mask_t RX14MASK; //!< [0x14] Rx 14 Mask register
+ __IO hw_can_rx15mask_t RX15MASK; //!< [0x18] Rx 15 Mask register
+ __IO hw_can_ecr_t ECR; //!< [0x1C] Error Counter
+ __IO hw_can_esr1_t ESR1; //!< [0x20] Error and Status 1 register
+ uint8_t _reserved1[4];
+ __IO hw_can_imask1_t IMASK1; //!< [0x28] Interrupt Masks 1 register
+ uint8_t _reserved2[4];
+ __IO hw_can_iflag1_t IFLAG1; //!< [0x30] Interrupt Flags 1 register
+ __IO hw_can_ctrl2_t CTRL2; //!< [0x34] Control 2 register
+ __I hw_can_esr2_t ESR2; //!< [0x38] Error and Status 2 register
+ uint8_t _reserved3[8];
+ __I hw_can_crcr_t CRCR; //!< [0x44] CRC Register
+ __IO hw_can_rxfgmask_t RXFGMASK; //!< [0x48] Rx FIFO Global Mask register
+ __I hw_can_rxfir_t RXFIR; //!< [0x4C] Rx FIFO Information Register
+ uint8_t _reserved4[48];
+ struct {
+ __IO hw_can_cs_t CS; //!< [0x80] Message Buffer 0 CS Register
+ __IO hw_can_id_t ID; //!< [0x84] Message Buffer 0 ID Register
+ __IO hw_can_word0_t WORD0; //!< [0x88] Message Buffer 0 WORD0 Register
+ __IO hw_can_word1_t WORD1; //!< [0x8C] Message Buffer 0 WORD1 Register
+ } MB[16];
+ uint8_t _reserved5[1792];
+ __IO hw_can_rximrn_t RXIMRn[16]; //!< [0x880] Rx Individual Mask Registers
+} hw_can_t;
+#pragma pack()
+
+//! @brief Macro to access all CAN registers.
+//! @param x CAN instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_CAN(0)</code>.
+#define HW_CAN(x) (*(hw_can_t *) REGS_CAN_BASE(x))
+#endif
+
+#endif // __HW_CAN_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_cau.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,1463 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_CAU_REGISTERS_H__
+#define __HW_CAU_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 CAU
+ *
+ * Memory Mapped Cryptographic Acceleration Unit (MMCAU)
+ *
+ * Registers defined in this header file:
+ * - HW_CAU_DIRECT - Direct access register 0
+ * - HW_CAU_LDR_CASR - Status register - Load Register command
+ * - HW_CAU_LDR_CAA - Accumulator register - Load Register command
+ * - HW_CAU_LDR_CA - General Purpose Register 0 - Load Register command
+ * - HW_CAU_STR_CASR - Status register - Store Register command
+ * - HW_CAU_STR_CAA - Accumulator register - Store Register command
+ * - HW_CAU_STR_CA - General Purpose Register 0 - Store Register command
+ * - HW_CAU_ADR_CASR - Status register - Add Register command
+ * - HW_CAU_ADR_CAA - Accumulator register - Add to register command
+ * - HW_CAU_ADR_CA - General Purpose Register 0 - Add to register command
+ * - HW_CAU_RADR_CASR - Status register - Reverse and Add to Register command
+ * - HW_CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command
+ * - HW_CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command
+ * - HW_CAU_XOR_CASR - Status register - Exclusive Or command
+ * - HW_CAU_XOR_CAA - Accumulator register - Exclusive Or command
+ * - HW_CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command
+ * - HW_CAU_ROTL_CASR - Status register - Rotate Left command
+ * - HW_CAU_ROTL_CAA - Accumulator register - Rotate Left command
+ * - HW_CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command
+ * - HW_CAU_AESC_CASR - Status register - AES Column Operation command
+ * - HW_CAU_AESC_CAA - Accumulator register - AES Column Operation command
+ * - HW_CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command
+ * - HW_CAU_AESIC_CASR - Status register - AES Inverse Column Operation command
+ * - HW_CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command
+ * - HW_CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command
+ *
+ * - hw_cau_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_CAU_BASE
+#define HW_CAU_INSTANCE_COUNT (1U) //!< Number of instances of the CAU module.
+#define REGS_CAU_BASE (0xE0081000U) //!< Base address for CAU.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_DIRECT - Direct access register 0
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_DIRECT - Direct access register 0 (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_direct
+{
+ uint32_t U;
+ struct _hw_cau_direct_bitfields
+ {
+ uint32_t RESERVED0 : 32; //!< [31:0]
+ } B;
+} hw_cau_direct_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_DIRECT register
+ */
+//@{
+#define HW_CAU_DIRECT_COUNT (16U)
+
+#define HW_CAU_DIRECT_ADDR(n) (REGS_CAU_BASE + 0x0U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_DIRECT(n) (*(__O hw_cau_direct_t *) HW_CAU_DIRECT_ADDR(n))
+#define HW_CAU_DIRECT_WR(n, v) (HW_CAU_DIRECT(n).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_DIRECT bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_LDR_CASR - Status register - Load Register command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_LDR_CASR - Status register - Load Register command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+typedef union _hw_cau_ldr_casr
+{
+ uint32_t U;
+ struct _hw_cau_ldr_casr_bitfields
+ {
+ uint32_t IC : 1; //!< [0]
+ uint32_t DPE : 1; //!< [1]
+ uint32_t RESERVED0 : 26; //!< [27:2]
+ uint32_t VER : 4; //!< [31:28] CAU version
+ } B;
+} hw_cau_ldr_casr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_LDR_CASR register
+ */
+//@{
+#define HW_CAU_LDR_CASR_ADDR (REGS_CAU_BASE + 0x840U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_LDR_CASR (*(__O hw_cau_ldr_casr_t *) HW_CAU_LDR_CASR_ADDR)
+#define HW_CAU_LDR_CASR_WR(v) (HW_CAU_LDR_CASR.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_LDR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_LDR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0 - No illegal commands issued
+ * - 1 - Illegal command issued
+ */
+//@{
+#define BP_CAU_LDR_CASR_IC (0U) //!< Bit position for CAU_LDR_CASR_IC.
+#define BM_CAU_LDR_CASR_IC (0x00000001U) //!< Bit mask for CAU_LDR_CASR_IC.
+#define BS_CAU_LDR_CASR_IC (1U) //!< Bit field size in bits for CAU_LDR_CASR_IC.
+
+//! @brief Format value for bitfield CAU_LDR_CASR_IC.
+#define BF_CAU_LDR_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_LDR_CASR_IC), uint32_t) & BM_CAU_LDR_CASR_IC)
+//@}
+
+/*!
+ * @name Register CAU_LDR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0 - No error detected
+ * - 1 - DES key parity error detected
+ */
+//@{
+#define BP_CAU_LDR_CASR_DPE (1U) //!< Bit position for CAU_LDR_CASR_DPE.
+#define BM_CAU_LDR_CASR_DPE (0x00000002U) //!< Bit mask for CAU_LDR_CASR_DPE.
+#define BS_CAU_LDR_CASR_DPE (1U) //!< Bit field size in bits for CAU_LDR_CASR_DPE.
+
+//! @brief Format value for bitfield CAU_LDR_CASR_DPE.
+#define BF_CAU_LDR_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_LDR_CASR_DPE), uint32_t) & BM_CAU_LDR_CASR_DPE)
+//@}
+
+/*!
+ * @name Register CAU_LDR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0001 - Initial CAU version
+ * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
+ * value on this device)
+ */
+//@{
+#define BP_CAU_LDR_CASR_VER (28U) //!< Bit position for CAU_LDR_CASR_VER.
+#define BM_CAU_LDR_CASR_VER (0xF0000000U) //!< Bit mask for CAU_LDR_CASR_VER.
+#define BS_CAU_LDR_CASR_VER (4U) //!< Bit field size in bits for CAU_LDR_CASR_VER.
+
+//! @brief Format value for bitfield CAU_LDR_CASR_VER.
+#define BF_CAU_LDR_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_LDR_CASR_VER), uint32_t) & BM_CAU_LDR_CASR_VER)
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_LDR_CAA - Accumulator register - Load Register command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_LDR_CAA - Accumulator register - Load Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_ldr_caa
+{
+ uint32_t U;
+ struct _hw_cau_ldr_caa_bitfields
+ {
+ uint32_t RESERVED0 : 32; //!< [31:0]
+ } B;
+} hw_cau_ldr_caa_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_LDR_CAA register
+ */
+//@{
+#define HW_CAU_LDR_CAA_ADDR (REGS_CAU_BASE + 0x844U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_LDR_CAA (*(__O hw_cau_ldr_caa_t *) HW_CAU_LDR_CAA_ADDR)
+#define HW_CAU_LDR_CAA_WR(v) (HW_CAU_LDR_CAA.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_LDR_CAA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_LDR_CA - General Purpose Register 0 - Load Register command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_LDR_CA - General Purpose Register 0 - Load Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_ldr_ca
+{
+ uint32_t U;
+ struct _hw_cau_ldr_ca_bitfields
+ {
+ uint32_t RESERVED0 : 32; //!< [31:0]
+ } B;
+} hw_cau_ldr_ca_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_LDR_CA register
+ */
+//@{
+#define HW_CAU_LDR_CA_COUNT (9U)
+
+#define HW_CAU_LDR_CA_ADDR(n) (REGS_CAU_BASE + 0x848U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_LDR_CA(n) (*(__O hw_cau_ldr_ca_t *) HW_CAU_LDR_CA_ADDR(n))
+#define HW_CAU_LDR_CA_WR(n, v) (HW_CAU_LDR_CA(n).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_LDR_CA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_STR_CASR - Status register - Store Register command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_STR_CASR - Status register - Store Register command (RO)
+ *
+ * Reset value: 0x20000000U
+ */
+typedef union _hw_cau_str_casr
+{
+ uint32_t U;
+ struct _hw_cau_str_casr_bitfields
+ {
+ uint32_t IC : 1; //!< [0]
+ uint32_t DPE : 1; //!< [1]
+ uint32_t RESERVED0 : 26; //!< [27:2]
+ uint32_t VER : 4; //!< [31:28] CAU version
+ } B;
+} hw_cau_str_casr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_STR_CASR register
+ */
+//@{
+#define HW_CAU_STR_CASR_ADDR (REGS_CAU_BASE + 0x880U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_STR_CASR (*(__I hw_cau_str_casr_t *) HW_CAU_STR_CASR_ADDR)
+#define HW_CAU_STR_CASR_RD() (HW_CAU_STR_CASR.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_STR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_STR_CASR, field IC[0] (RO)
+ *
+ * Values:
+ * - 0 - No illegal commands issued
+ * - 1 - Illegal command issued
+ */
+//@{
+#define BP_CAU_STR_CASR_IC (0U) //!< Bit position for CAU_STR_CASR_IC.
+#define BM_CAU_STR_CASR_IC (0x00000001U) //!< Bit mask for CAU_STR_CASR_IC.
+#define BS_CAU_STR_CASR_IC (1U) //!< Bit field size in bits for CAU_STR_CASR_IC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAU_STR_CASR_IC field.
+#define BR_CAU_STR_CASR_IC (BITBAND_ACCESS32(HW_CAU_STR_CASR_ADDR, BP_CAU_STR_CASR_IC))
+#endif
+//@}
+
+/*!
+ * @name Register CAU_STR_CASR, field DPE[1] (RO)
+ *
+ * Values:
+ * - 0 - No error detected
+ * - 1 - DES key parity error detected
+ */
+//@{
+#define BP_CAU_STR_CASR_DPE (1U) //!< Bit position for CAU_STR_CASR_DPE.
+#define BM_CAU_STR_CASR_DPE (0x00000002U) //!< Bit mask for CAU_STR_CASR_DPE.
+#define BS_CAU_STR_CASR_DPE (1U) //!< Bit field size in bits for CAU_STR_CASR_DPE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAU_STR_CASR_DPE field.
+#define BR_CAU_STR_CASR_DPE (BITBAND_ACCESS32(HW_CAU_STR_CASR_ADDR, BP_CAU_STR_CASR_DPE))
+#endif
+//@}
+
+/*!
+ * @name Register CAU_STR_CASR, field VER[31:28] (RO)
+ *
+ * Values:
+ * - 0001 - Initial CAU version
+ * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
+ * value on this device)
+ */
+//@{
+#define BP_CAU_STR_CASR_VER (28U) //!< Bit position for CAU_STR_CASR_VER.
+#define BM_CAU_STR_CASR_VER (0xF0000000U) //!< Bit mask for CAU_STR_CASR_VER.
+#define BS_CAU_STR_CASR_VER (4U) //!< Bit field size in bits for CAU_STR_CASR_VER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CAU_STR_CASR_VER field.
+#define BR_CAU_STR_CASR_VER (HW_CAU_STR_CASR.B.VER)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_STR_CAA - Accumulator register - Store Register command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_STR_CAA - Accumulator register - Store Register command (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_str_caa
+{
+ uint32_t U;
+ struct _hw_cau_str_caa_bitfields
+ {
+ uint32_t RESERVED0 : 32; //!< [31:0]
+ } B;
+} hw_cau_str_caa_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_STR_CAA register
+ */
+//@{
+#define HW_CAU_STR_CAA_ADDR (REGS_CAU_BASE + 0x884U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_STR_CAA (*(__I hw_cau_str_caa_t *) HW_CAU_STR_CAA_ADDR)
+#define HW_CAU_STR_CAA_RD() (HW_CAU_STR_CAA.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_STR_CAA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_STR_CA - General Purpose Register 0 - Store Register command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_STR_CA - General Purpose Register 0 - Store Register command (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_str_ca
+{
+ uint32_t U;
+ struct _hw_cau_str_ca_bitfields
+ {
+ uint32_t RESERVED0 : 32; //!< [31:0]
+ } B;
+} hw_cau_str_ca_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_STR_CA register
+ */
+//@{
+#define HW_CAU_STR_CA_COUNT (9U)
+
+#define HW_CAU_STR_CA_ADDR(n) (REGS_CAU_BASE + 0x888U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_STR_CA(n) (*(__I hw_cau_str_ca_t *) HW_CAU_STR_CA_ADDR(n))
+#define HW_CAU_STR_CA_RD(n) (HW_CAU_STR_CA(n).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_STR_CA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_ADR_CASR - Status register - Add Register command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_ADR_CASR - Status register - Add Register command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+typedef union _hw_cau_adr_casr
+{
+ uint32_t U;
+ struct _hw_cau_adr_casr_bitfields
+ {
+ uint32_t IC : 1; //!< [0]
+ uint32_t DPE : 1; //!< [1]
+ uint32_t RESERVED0 : 26; //!< [27:2]
+ uint32_t VER : 4; //!< [31:28] CAU version
+ } B;
+} hw_cau_adr_casr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_ADR_CASR register
+ */
+//@{
+#define HW_CAU_ADR_CASR_ADDR (REGS_CAU_BASE + 0x8C0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_ADR_CASR (*(__O hw_cau_adr_casr_t *) HW_CAU_ADR_CASR_ADDR)
+#define HW_CAU_ADR_CASR_WR(v) (HW_CAU_ADR_CASR.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_ADR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_ADR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0 - No illegal commands issued
+ * - 1 - Illegal command issued
+ */
+//@{
+#define BP_CAU_ADR_CASR_IC (0U) //!< Bit position for CAU_ADR_CASR_IC.
+#define BM_CAU_ADR_CASR_IC (0x00000001U) //!< Bit mask for CAU_ADR_CASR_IC.
+#define BS_CAU_ADR_CASR_IC (1U) //!< Bit field size in bits for CAU_ADR_CASR_IC.
+
+//! @brief Format value for bitfield CAU_ADR_CASR_IC.
+#define BF_CAU_ADR_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ADR_CASR_IC), uint32_t) & BM_CAU_ADR_CASR_IC)
+//@}
+
+/*!
+ * @name Register CAU_ADR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0 - No error detected
+ * - 1 - DES key parity error detected
+ */
+//@{
+#define BP_CAU_ADR_CASR_DPE (1U) //!< Bit position for CAU_ADR_CASR_DPE.
+#define BM_CAU_ADR_CASR_DPE (0x00000002U) //!< Bit mask for CAU_ADR_CASR_DPE.
+#define BS_CAU_ADR_CASR_DPE (1U) //!< Bit field size in bits for CAU_ADR_CASR_DPE.
+
+//! @brief Format value for bitfield CAU_ADR_CASR_DPE.
+#define BF_CAU_ADR_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ADR_CASR_DPE), uint32_t) & BM_CAU_ADR_CASR_DPE)
+//@}
+
+/*!
+ * @name Register CAU_ADR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0001 - Initial CAU version
+ * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
+ * value on this device)
+ */
+//@{
+#define BP_CAU_ADR_CASR_VER (28U) //!< Bit position for CAU_ADR_CASR_VER.
+#define BM_CAU_ADR_CASR_VER (0xF0000000U) //!< Bit mask for CAU_ADR_CASR_VER.
+#define BS_CAU_ADR_CASR_VER (4U) //!< Bit field size in bits for CAU_ADR_CASR_VER.
+
+//! @brief Format value for bitfield CAU_ADR_CASR_VER.
+#define BF_CAU_ADR_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ADR_CASR_VER), uint32_t) & BM_CAU_ADR_CASR_VER)
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_ADR_CAA - Accumulator register - Add to register command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_ADR_CAA - Accumulator register - Add to register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_adr_caa
+{
+ uint32_t U;
+ struct _hw_cau_adr_caa_bitfields
+ {
+ uint32_t RESERVED0 : 32; //!< [31:0]
+ } B;
+} hw_cau_adr_caa_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_ADR_CAA register
+ */
+//@{
+#define HW_CAU_ADR_CAA_ADDR (REGS_CAU_BASE + 0x8C4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_ADR_CAA (*(__O hw_cau_adr_caa_t *) HW_CAU_ADR_CAA_ADDR)
+#define HW_CAU_ADR_CAA_WR(v) (HW_CAU_ADR_CAA.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_ADR_CAA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_ADR_CA - General Purpose Register 0 - Add to register command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_ADR_CA - General Purpose Register 0 - Add to register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_adr_ca
+{
+ uint32_t U;
+ struct _hw_cau_adr_ca_bitfields
+ {
+ uint32_t RESERVED0 : 32; //!< [31:0]
+ } B;
+} hw_cau_adr_ca_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_ADR_CA register
+ */
+//@{
+#define HW_CAU_ADR_CA_COUNT (9U)
+
+#define HW_CAU_ADR_CA_ADDR(n) (REGS_CAU_BASE + 0x8C8U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_ADR_CA(n) (*(__O hw_cau_adr_ca_t *) HW_CAU_ADR_CA_ADDR(n))
+#define HW_CAU_ADR_CA_WR(n, v) (HW_CAU_ADR_CA(n).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_ADR_CA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_RADR_CASR - Status register - Reverse and Add to Register command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_RADR_CASR - Status register - Reverse and Add to Register command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+typedef union _hw_cau_radr_casr
+{
+ uint32_t U;
+ struct _hw_cau_radr_casr_bitfields
+ {
+ uint32_t IC : 1; //!< [0]
+ uint32_t DPE : 1; //!< [1]
+ uint32_t RESERVED0 : 26; //!< [27:2]
+ uint32_t VER : 4; //!< [31:28] CAU version
+ } B;
+} hw_cau_radr_casr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_RADR_CASR register
+ */
+//@{
+#define HW_CAU_RADR_CASR_ADDR (REGS_CAU_BASE + 0x900U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_RADR_CASR (*(__O hw_cau_radr_casr_t *) HW_CAU_RADR_CASR_ADDR)
+#define HW_CAU_RADR_CASR_WR(v) (HW_CAU_RADR_CASR.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_RADR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_RADR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0 - No illegal commands issued
+ * - 1 - Illegal command issued
+ */
+//@{
+#define BP_CAU_RADR_CASR_IC (0U) //!< Bit position for CAU_RADR_CASR_IC.
+#define BM_CAU_RADR_CASR_IC (0x00000001U) //!< Bit mask for CAU_RADR_CASR_IC.
+#define BS_CAU_RADR_CASR_IC (1U) //!< Bit field size in bits for CAU_RADR_CASR_IC.
+
+//! @brief Format value for bitfield CAU_RADR_CASR_IC.
+#define BF_CAU_RADR_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_RADR_CASR_IC), uint32_t) & BM_CAU_RADR_CASR_IC)
+//@}
+
+/*!
+ * @name Register CAU_RADR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0 - No error detected
+ * - 1 - DES key parity error detected
+ */
+//@{
+#define BP_CAU_RADR_CASR_DPE (1U) //!< Bit position for CAU_RADR_CASR_DPE.
+#define BM_CAU_RADR_CASR_DPE (0x00000002U) //!< Bit mask for CAU_RADR_CASR_DPE.
+#define BS_CAU_RADR_CASR_DPE (1U) //!< Bit field size in bits for CAU_RADR_CASR_DPE.
+
+//! @brief Format value for bitfield CAU_RADR_CASR_DPE.
+#define BF_CAU_RADR_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_RADR_CASR_DPE), uint32_t) & BM_CAU_RADR_CASR_DPE)
+//@}
+
+/*!
+ * @name Register CAU_RADR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0001 - Initial CAU version
+ * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
+ * value on this device)
+ */
+//@{
+#define BP_CAU_RADR_CASR_VER (28U) //!< Bit position for CAU_RADR_CASR_VER.
+#define BM_CAU_RADR_CASR_VER (0xF0000000U) //!< Bit mask for CAU_RADR_CASR_VER.
+#define BS_CAU_RADR_CASR_VER (4U) //!< Bit field size in bits for CAU_RADR_CASR_VER.
+
+//! @brief Format value for bitfield CAU_RADR_CASR_VER.
+#define BF_CAU_RADR_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_RADR_CASR_VER), uint32_t) & BM_CAU_RADR_CASR_VER)
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_radr_caa
+{
+ uint32_t U;
+ struct _hw_cau_radr_caa_bitfields
+ {
+ uint32_t RESERVED0 : 32; //!< [31:0]
+ } B;
+} hw_cau_radr_caa_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_RADR_CAA register
+ */
+//@{
+#define HW_CAU_RADR_CAA_ADDR (REGS_CAU_BASE + 0x904U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_RADR_CAA (*(__O hw_cau_radr_caa_t *) HW_CAU_RADR_CAA_ADDR)
+#define HW_CAU_RADR_CAA_WR(v) (HW_CAU_RADR_CAA.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_RADR_CAA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_radr_ca
+{
+ uint32_t U;
+ struct _hw_cau_radr_ca_bitfields
+ {
+ uint32_t RESERVED0 : 32; //!< [31:0]
+ } B;
+} hw_cau_radr_ca_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_RADR_CA register
+ */
+//@{
+#define HW_CAU_RADR_CA_COUNT (9U)
+
+#define HW_CAU_RADR_CA_ADDR(n) (REGS_CAU_BASE + 0x908U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_RADR_CA(n) (*(__O hw_cau_radr_ca_t *) HW_CAU_RADR_CA_ADDR(n))
+#define HW_CAU_RADR_CA_WR(n, v) (HW_CAU_RADR_CA(n).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_RADR_CA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_XOR_CASR - Status register - Exclusive Or command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_XOR_CASR - Status register - Exclusive Or command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+typedef union _hw_cau_xor_casr
+{
+ uint32_t U;
+ struct _hw_cau_xor_casr_bitfields
+ {
+ uint32_t IC : 1; //!< [0]
+ uint32_t DPE : 1; //!< [1]
+ uint32_t RESERVED0 : 26; //!< [27:2]
+ uint32_t VER : 4; //!< [31:28] CAU version
+ } B;
+} hw_cau_xor_casr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_XOR_CASR register
+ */
+//@{
+#define HW_CAU_XOR_CASR_ADDR (REGS_CAU_BASE + 0x980U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_XOR_CASR (*(__O hw_cau_xor_casr_t *) HW_CAU_XOR_CASR_ADDR)
+#define HW_CAU_XOR_CASR_WR(v) (HW_CAU_XOR_CASR.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_XOR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_XOR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0 - No illegal commands issued
+ * - 1 - Illegal command issued
+ */
+//@{
+#define BP_CAU_XOR_CASR_IC (0U) //!< Bit position for CAU_XOR_CASR_IC.
+#define BM_CAU_XOR_CASR_IC (0x00000001U) //!< Bit mask for CAU_XOR_CASR_IC.
+#define BS_CAU_XOR_CASR_IC (1U) //!< Bit field size in bits for CAU_XOR_CASR_IC.
+
+//! @brief Format value for bitfield CAU_XOR_CASR_IC.
+#define BF_CAU_XOR_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_XOR_CASR_IC), uint32_t) & BM_CAU_XOR_CASR_IC)
+//@}
+
+/*!
+ * @name Register CAU_XOR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0 - No error detected
+ * - 1 - DES key parity error detected
+ */
+//@{
+#define BP_CAU_XOR_CASR_DPE (1U) //!< Bit position for CAU_XOR_CASR_DPE.
+#define BM_CAU_XOR_CASR_DPE (0x00000002U) //!< Bit mask for CAU_XOR_CASR_DPE.
+#define BS_CAU_XOR_CASR_DPE (1U) //!< Bit field size in bits for CAU_XOR_CASR_DPE.
+
+//! @brief Format value for bitfield CAU_XOR_CASR_DPE.
+#define BF_CAU_XOR_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_XOR_CASR_DPE), uint32_t) & BM_CAU_XOR_CASR_DPE)
+//@}
+
+/*!
+ * @name Register CAU_XOR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0001 - Initial CAU version
+ * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
+ * value on this device)
+ */
+//@{
+#define BP_CAU_XOR_CASR_VER (28U) //!< Bit position for CAU_XOR_CASR_VER.
+#define BM_CAU_XOR_CASR_VER (0xF0000000U) //!< Bit mask for CAU_XOR_CASR_VER.
+#define BS_CAU_XOR_CASR_VER (4U) //!< Bit field size in bits for CAU_XOR_CASR_VER.
+
+//! @brief Format value for bitfield CAU_XOR_CASR_VER.
+#define BF_CAU_XOR_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_XOR_CASR_VER), uint32_t) & BM_CAU_XOR_CASR_VER)
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_XOR_CAA - Accumulator register - Exclusive Or command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_XOR_CAA - Accumulator register - Exclusive Or command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_xor_caa
+{
+ uint32_t U;
+ struct _hw_cau_xor_caa_bitfields
+ {
+ uint32_t RESERVED0 : 32; //!< [31:0]
+ } B;
+} hw_cau_xor_caa_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_XOR_CAA register
+ */
+//@{
+#define HW_CAU_XOR_CAA_ADDR (REGS_CAU_BASE + 0x984U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_XOR_CAA (*(__O hw_cau_xor_caa_t *) HW_CAU_XOR_CAA_ADDR)
+#define HW_CAU_XOR_CAA_WR(v) (HW_CAU_XOR_CAA.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_XOR_CAA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_xor_ca
+{
+ uint32_t U;
+ struct _hw_cau_xor_ca_bitfields
+ {
+ uint32_t RESERVED0 : 32; //!< [31:0]
+ } B;
+} hw_cau_xor_ca_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_XOR_CA register
+ */
+//@{
+#define HW_CAU_XOR_CA_COUNT (9U)
+
+#define HW_CAU_XOR_CA_ADDR(n) (REGS_CAU_BASE + 0x988U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_XOR_CA(n) (*(__O hw_cau_xor_ca_t *) HW_CAU_XOR_CA_ADDR(n))
+#define HW_CAU_XOR_CA_WR(n, v) (HW_CAU_XOR_CA(n).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_XOR_CA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_ROTL_CASR - Status register - Rotate Left command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_ROTL_CASR - Status register - Rotate Left command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+typedef union _hw_cau_rotl_casr
+{
+ uint32_t U;
+ struct _hw_cau_rotl_casr_bitfields
+ {
+ uint32_t IC : 1; //!< [0]
+ uint32_t DPE : 1; //!< [1]
+ uint32_t RESERVED0 : 26; //!< [27:2]
+ uint32_t VER : 4; //!< [31:28] CAU version
+ } B;
+} hw_cau_rotl_casr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_ROTL_CASR register
+ */
+//@{
+#define HW_CAU_ROTL_CASR_ADDR (REGS_CAU_BASE + 0x9C0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_ROTL_CASR (*(__O hw_cau_rotl_casr_t *) HW_CAU_ROTL_CASR_ADDR)
+#define HW_CAU_ROTL_CASR_WR(v) (HW_CAU_ROTL_CASR.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_ROTL_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_ROTL_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0 - No illegal commands issued
+ * - 1 - Illegal command issued
+ */
+//@{
+#define BP_CAU_ROTL_CASR_IC (0U) //!< Bit position for CAU_ROTL_CASR_IC.
+#define BM_CAU_ROTL_CASR_IC (0x00000001U) //!< Bit mask for CAU_ROTL_CASR_IC.
+#define BS_CAU_ROTL_CASR_IC (1U) //!< Bit field size in bits for CAU_ROTL_CASR_IC.
+
+//! @brief Format value for bitfield CAU_ROTL_CASR_IC.
+#define BF_CAU_ROTL_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ROTL_CASR_IC), uint32_t) & BM_CAU_ROTL_CASR_IC)
+//@}
+
+/*!
+ * @name Register CAU_ROTL_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0 - No error detected
+ * - 1 - DES key parity error detected
+ */
+//@{
+#define BP_CAU_ROTL_CASR_DPE (1U) //!< Bit position for CAU_ROTL_CASR_DPE.
+#define BM_CAU_ROTL_CASR_DPE (0x00000002U) //!< Bit mask for CAU_ROTL_CASR_DPE.
+#define BS_CAU_ROTL_CASR_DPE (1U) //!< Bit field size in bits for CAU_ROTL_CASR_DPE.
+
+//! @brief Format value for bitfield CAU_ROTL_CASR_DPE.
+#define BF_CAU_ROTL_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ROTL_CASR_DPE), uint32_t) & BM_CAU_ROTL_CASR_DPE)
+//@}
+
+/*!
+ * @name Register CAU_ROTL_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0001 - Initial CAU version
+ * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
+ * value on this device)
+ */
+//@{
+#define BP_CAU_ROTL_CASR_VER (28U) //!< Bit position for CAU_ROTL_CASR_VER.
+#define BM_CAU_ROTL_CASR_VER (0xF0000000U) //!< Bit mask for CAU_ROTL_CASR_VER.
+#define BS_CAU_ROTL_CASR_VER (4U) //!< Bit field size in bits for CAU_ROTL_CASR_VER.
+
+//! @brief Format value for bitfield CAU_ROTL_CASR_VER.
+#define BF_CAU_ROTL_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_ROTL_CASR_VER), uint32_t) & BM_CAU_ROTL_CASR_VER)
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_ROTL_CAA - Accumulator register - Rotate Left command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_ROTL_CAA - Accumulator register - Rotate Left command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_rotl_caa
+{
+ uint32_t U;
+ struct _hw_cau_rotl_caa_bitfields
+ {
+ uint32_t RESERVED0 : 32; //!< [31:0]
+ } B;
+} hw_cau_rotl_caa_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_ROTL_CAA register
+ */
+//@{
+#define HW_CAU_ROTL_CAA_ADDR (REGS_CAU_BASE + 0x9C4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_ROTL_CAA (*(__O hw_cau_rotl_caa_t *) HW_CAU_ROTL_CAA_ADDR)
+#define HW_CAU_ROTL_CAA_WR(v) (HW_CAU_ROTL_CAA.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_ROTL_CAA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_rotl_ca
+{
+ uint32_t U;
+ struct _hw_cau_rotl_ca_bitfields
+ {
+ uint32_t RESERVED0 : 32; //!< [31:0]
+ } B;
+} hw_cau_rotl_ca_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_ROTL_CA register
+ */
+//@{
+#define HW_CAU_ROTL_CA_COUNT (9U)
+
+#define HW_CAU_ROTL_CA_ADDR(n) (REGS_CAU_BASE + 0x9C8U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_ROTL_CA(n) (*(__O hw_cau_rotl_ca_t *) HW_CAU_ROTL_CA_ADDR(n))
+#define HW_CAU_ROTL_CA_WR(n, v) (HW_CAU_ROTL_CA(n).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_ROTL_CA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_AESC_CASR - Status register - AES Column Operation command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_AESC_CASR - Status register - AES Column Operation command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+typedef union _hw_cau_aesc_casr
+{
+ uint32_t U;
+ struct _hw_cau_aesc_casr_bitfields
+ {
+ uint32_t IC : 1; //!< [0]
+ uint32_t DPE : 1; //!< [1]
+ uint32_t RESERVED0 : 26; //!< [27:2]
+ uint32_t VER : 4; //!< [31:28] CAU version
+ } B;
+} hw_cau_aesc_casr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_AESC_CASR register
+ */
+//@{
+#define HW_CAU_AESC_CASR_ADDR (REGS_CAU_BASE + 0xB00U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_AESC_CASR (*(__O hw_cau_aesc_casr_t *) HW_CAU_AESC_CASR_ADDR)
+#define HW_CAU_AESC_CASR_WR(v) (HW_CAU_AESC_CASR.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_AESC_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_AESC_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0 - No illegal commands issued
+ * - 1 - Illegal command issued
+ */
+//@{
+#define BP_CAU_AESC_CASR_IC (0U) //!< Bit position for CAU_AESC_CASR_IC.
+#define BM_CAU_AESC_CASR_IC (0x00000001U) //!< Bit mask for CAU_AESC_CASR_IC.
+#define BS_CAU_AESC_CASR_IC (1U) //!< Bit field size in bits for CAU_AESC_CASR_IC.
+
+//! @brief Format value for bitfield CAU_AESC_CASR_IC.
+#define BF_CAU_AESC_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESC_CASR_IC), uint32_t) & BM_CAU_AESC_CASR_IC)
+//@}
+
+/*!
+ * @name Register CAU_AESC_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0 - No error detected
+ * - 1 - DES key parity error detected
+ */
+//@{
+#define BP_CAU_AESC_CASR_DPE (1U) //!< Bit position for CAU_AESC_CASR_DPE.
+#define BM_CAU_AESC_CASR_DPE (0x00000002U) //!< Bit mask for CAU_AESC_CASR_DPE.
+#define BS_CAU_AESC_CASR_DPE (1U) //!< Bit field size in bits for CAU_AESC_CASR_DPE.
+
+//! @brief Format value for bitfield CAU_AESC_CASR_DPE.
+#define BF_CAU_AESC_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESC_CASR_DPE), uint32_t) & BM_CAU_AESC_CASR_DPE)
+//@}
+
+/*!
+ * @name Register CAU_AESC_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0001 - Initial CAU version
+ * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
+ * value on this device)
+ */
+//@{
+#define BP_CAU_AESC_CASR_VER (28U) //!< Bit position for CAU_AESC_CASR_VER.
+#define BM_CAU_AESC_CASR_VER (0xF0000000U) //!< Bit mask for CAU_AESC_CASR_VER.
+#define BS_CAU_AESC_CASR_VER (4U) //!< Bit field size in bits for CAU_AESC_CASR_VER.
+
+//! @brief Format value for bitfield CAU_AESC_CASR_VER.
+#define BF_CAU_AESC_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESC_CASR_VER), uint32_t) & BM_CAU_AESC_CASR_VER)
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_AESC_CAA - Accumulator register - AES Column Operation command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_AESC_CAA - Accumulator register - AES Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_aesc_caa
+{
+ uint32_t U;
+ struct _hw_cau_aesc_caa_bitfields
+ {
+ uint32_t RESERVED0 : 32; //!< [31:0]
+ } B;
+} hw_cau_aesc_caa_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_AESC_CAA register
+ */
+//@{
+#define HW_CAU_AESC_CAA_ADDR (REGS_CAU_BASE + 0xB04U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_AESC_CAA (*(__O hw_cau_aesc_caa_t *) HW_CAU_AESC_CAA_ADDR)
+#define HW_CAU_AESC_CAA_WR(v) (HW_CAU_AESC_CAA.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_AESC_CAA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_aesc_ca
+{
+ uint32_t U;
+ struct _hw_cau_aesc_ca_bitfields
+ {
+ uint32_t RESERVED0 : 32; //!< [31:0]
+ } B;
+} hw_cau_aesc_ca_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_AESC_CA register
+ */
+//@{
+#define HW_CAU_AESC_CA_COUNT (9U)
+
+#define HW_CAU_AESC_CA_ADDR(n) (REGS_CAU_BASE + 0xB08U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_AESC_CA(n) (*(__O hw_cau_aesc_ca_t *) HW_CAU_AESC_CA_ADDR(n))
+#define HW_CAU_AESC_CA_WR(n, v) (HW_CAU_AESC_CA(n).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_AESC_CA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_AESIC_CASR - Status register - AES Inverse Column Operation command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_AESIC_CASR - Status register - AES Inverse Column Operation command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+typedef union _hw_cau_aesic_casr
+{
+ uint32_t U;
+ struct _hw_cau_aesic_casr_bitfields
+ {
+ uint32_t IC : 1; //!< [0]
+ uint32_t DPE : 1; //!< [1]
+ uint32_t RESERVED0 : 26; //!< [27:2]
+ uint32_t VER : 4; //!< [31:28] CAU version
+ } B;
+} hw_cau_aesic_casr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_AESIC_CASR register
+ */
+//@{
+#define HW_CAU_AESIC_CASR_ADDR (REGS_CAU_BASE + 0xB40U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_AESIC_CASR (*(__O hw_cau_aesic_casr_t *) HW_CAU_AESIC_CASR_ADDR)
+#define HW_CAU_AESIC_CASR_WR(v) (HW_CAU_AESIC_CASR.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_AESIC_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_AESIC_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0 - No illegal commands issued
+ * - 1 - Illegal command issued
+ */
+//@{
+#define BP_CAU_AESIC_CASR_IC (0U) //!< Bit position for CAU_AESIC_CASR_IC.
+#define BM_CAU_AESIC_CASR_IC (0x00000001U) //!< Bit mask for CAU_AESIC_CASR_IC.
+#define BS_CAU_AESIC_CASR_IC (1U) //!< Bit field size in bits for CAU_AESIC_CASR_IC.
+
+//! @brief Format value for bitfield CAU_AESIC_CASR_IC.
+#define BF_CAU_AESIC_CASR_IC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESIC_CASR_IC), uint32_t) & BM_CAU_AESIC_CASR_IC)
+//@}
+
+/*!
+ * @name Register CAU_AESIC_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0 - No error detected
+ * - 1 - DES key parity error detected
+ */
+//@{
+#define BP_CAU_AESIC_CASR_DPE (1U) //!< Bit position for CAU_AESIC_CASR_DPE.
+#define BM_CAU_AESIC_CASR_DPE (0x00000002U) //!< Bit mask for CAU_AESIC_CASR_DPE.
+#define BS_CAU_AESIC_CASR_DPE (1U) //!< Bit field size in bits for CAU_AESIC_CASR_DPE.
+
+//! @brief Format value for bitfield CAU_AESIC_CASR_DPE.
+#define BF_CAU_AESIC_CASR_DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESIC_CASR_DPE), uint32_t) & BM_CAU_AESIC_CASR_DPE)
+//@}
+
+/*!
+ * @name Register CAU_AESIC_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0001 - Initial CAU version
+ * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
+ * value on this device)
+ */
+//@{
+#define BP_CAU_AESIC_CASR_VER (28U) //!< Bit position for CAU_AESIC_CASR_VER.
+#define BM_CAU_AESIC_CASR_VER (0xF0000000U) //!< Bit mask for CAU_AESIC_CASR_VER.
+#define BS_CAU_AESIC_CASR_VER (4U) //!< Bit field size in bits for CAU_AESIC_CASR_VER.
+
+//! @brief Format value for bitfield CAU_AESIC_CASR_VER.
+#define BF_CAU_AESIC_CASR_VER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CAU_AESIC_CASR_VER), uint32_t) & BM_CAU_AESIC_CASR_VER)
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_aesic_caa
+{
+ uint32_t U;
+ struct _hw_cau_aesic_caa_bitfields
+ {
+ uint32_t RESERVED0 : 32; //!< [31:0]
+ } B;
+} hw_cau_aesic_caa_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_AESIC_CAA register
+ */
+//@{
+#define HW_CAU_AESIC_CAA_ADDR (REGS_CAU_BASE + 0xB44U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_AESIC_CAA (*(__O hw_cau_aesic_caa_t *) HW_CAU_AESIC_CAA_ADDR)
+#define HW_CAU_AESIC_CAA_WR(v) (HW_CAU_AESIC_CAA.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_AESIC_CAA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// HW_CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_cau_aesic_ca
+{
+ uint32_t U;
+ struct _hw_cau_aesic_ca_bitfields
+ {
+ uint32_t RESERVED0 : 32; //!< [31:0]
+ } B;
+} hw_cau_aesic_ca_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CAU_AESIC_CA register
+ */
+//@{
+#define HW_CAU_AESIC_CA_COUNT (9U)
+
+#define HW_CAU_AESIC_CA_ADDR(n) (REGS_CAU_BASE + 0xB48U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CAU_AESIC_CA(n) (*(__O hw_cau_aesic_ca_t *) HW_CAU_AESIC_CA_ADDR(n))
+#define HW_CAU_AESIC_CA_WR(n, v) (HW_CAU_AESIC_CA(n).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CAU_AESIC_CA bitfields
+ */
+
+//-------------------------------------------------------------------------------------------
+// hw_cau_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All CAU module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_cau
+{
+ __O hw_cau_direct_t DIRECT[16]; //!< [0x0] Direct access register 0
+ uint8_t _reserved0[2048];
+ __O hw_cau_ldr_casr_t LDR_CASR; //!< [0x840] Status register - Load Register command
+ __O hw_cau_ldr_caa_t LDR_CAA; //!< [0x844] Accumulator register - Load Register command
+ __O hw_cau_ldr_ca_t LDR_CA[9]; //!< [0x848] General Purpose Register 0 - Load Register command
+ uint8_t _reserved1[20];
+ __I hw_cau_str_casr_t STR_CASR; //!< [0x880] Status register - Store Register command
+ __I hw_cau_str_caa_t STR_CAA; //!< [0x884] Accumulator register - Store Register command
+ __I hw_cau_str_ca_t STR_CA[9]; //!< [0x888] General Purpose Register 0 - Store Register command
+ uint8_t _reserved2[20];
+ __O hw_cau_adr_casr_t ADR_CASR; //!< [0x8C0] Status register - Add Register command
+ __O hw_cau_adr_caa_t ADR_CAA; //!< [0x8C4] Accumulator register - Add to register command
+ __O hw_cau_adr_ca_t ADR_CA[9]; //!< [0x8C8] General Purpose Register 0 - Add to register command
+ uint8_t _reserved3[20];
+ __O hw_cau_radr_casr_t RADR_CASR; //!< [0x900] Status register - Reverse and Add to Register command
+ __O hw_cau_radr_caa_t RADR_CAA; //!< [0x904] Accumulator register - Reverse and Add to Register command
+ __O hw_cau_radr_ca_t RADR_CA[9]; //!< [0x908] General Purpose Register 0 - Reverse and Add to Register command
+ uint8_t _reserved4[84];
+ __O hw_cau_xor_casr_t XOR_CASR; //!< [0x980] Status register - Exclusive Or command
+ __O hw_cau_xor_caa_t XOR_CAA; //!< [0x984] Accumulator register - Exclusive Or command
+ __O hw_cau_xor_ca_t XOR_CA[9]; //!< [0x988] General Purpose Register 0 - Exclusive Or command
+ uint8_t _reserved5[20];
+ __O hw_cau_rotl_casr_t ROTL_CASR; //!< [0x9C0] Status register - Rotate Left command
+ __O hw_cau_rotl_caa_t ROTL_CAA; //!< [0x9C4] Accumulator register - Rotate Left command
+ __O hw_cau_rotl_ca_t ROTL_CA[9]; //!< [0x9C8] General Purpose Register 0 - Rotate Left command
+ uint8_t _reserved6[276];
+ __O hw_cau_aesc_casr_t AESC_CASR; //!< [0xB00] Status register - AES Column Operation command
+ __O hw_cau_aesc_caa_t AESC_CAA; //!< [0xB04] Accumulator register - AES Column Operation command
+ __O hw_cau_aesc_ca_t AESC_CA[9]; //!< [0xB08] General Purpose Register 0 - AES Column Operation command
+ uint8_t _reserved7[20];
+ __O hw_cau_aesic_casr_t AESIC_CASR; //!< [0xB40] Status register - AES Inverse Column Operation command
+ __O hw_cau_aesic_caa_t AESIC_CAA; //!< [0xB44] Accumulator register - AES Inverse Column Operation command
+ __O hw_cau_aesic_ca_t AESIC_CA[9]; //!< [0xB48] General Purpose Register 0 - AES Inverse Column Operation command
+} hw_cau_t;
+#pragma pack()
+
+//! @brief Macro to access all CAU registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_CAU</code>.
+#define HW_CAU (*(hw_cau_t *) REGS_CAU_BASE)
+#endif
+
+#endif // __HW_CAU_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_cmp.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,1018 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_CMP_REGISTERS_H__
+#define __HW_CMP_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 CMP
+ *
+ * High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
+ *
+ * Registers defined in this header file:
+ * - HW_CMP_CR0 - CMP Control Register 0
+ * - HW_CMP_CR1 - CMP Control Register 1
+ * - HW_CMP_FPR - CMP Filter Period Register
+ * - HW_CMP_SCR - CMP Status and Control Register
+ * - HW_CMP_DACCR - DAC Control Register
+ * - HW_CMP_MUXCR - MUX Control Register
+ *
+ * - hw_cmp_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_CMP_BASE
+#define HW_CMP_INSTANCE_COUNT (3U) //!< Number of instances of the CMP module.
+#define HW_CMP0 (0U) //!< Instance number for CMP0.
+#define HW_CMP1 (1U) //!< Instance number for CMP1.
+#define HW_CMP2 (2U) //!< Instance number for CMP2.
+#define REGS_CMP0_BASE (0x40073000U) //!< Base address for CMP0.
+#define REGS_CMP1_BASE (0x40073008U) //!< Base address for CMP1.
+#define REGS_CMP2_BASE (0x40073010U) //!< Base address for CMP2.
+
+//! @brief Table of base addresses for CMP instances.
+static const uint32_t __g_regs_CMP_base_addresses[] = {
+ REGS_CMP0_BASE,
+ REGS_CMP1_BASE,
+ REGS_CMP2_BASE,
+ };
+
+//! @brief Get the base address of CMP by instance number.
+//! @param x CMP instance number, from 0 through 2.
+#define REGS_CMP_BASE(x) (__g_regs_CMP_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of CMP.
+#define REGS_CMP_INSTANCE(b) ((b) == REGS_CMP0_BASE ? HW_CMP0 : (b) == REGS_CMP1_BASE ? HW_CMP1 : (b) == REGS_CMP2_BASE ? HW_CMP2 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMP_CR0 - CMP Control Register 0
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMP_CR0 - CMP Control Register 0 (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_cmp_cr0
+{
+ uint8_t U;
+ struct _hw_cmp_cr0_bitfields
+ {
+ uint8_t HYSTCTR : 2; //!< [1:0] Comparator hard block hysteresis
+ //! control
+ uint8_t RESERVED0 : 2; //!< [3:2]
+ uint8_t FILTER_CNT : 3; //!< [6:4] Filter Sample Count
+ uint8_t RESERVED1 : 1; //!< [7]
+ } B;
+} hw_cmp_cr0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMP_CR0 register
+ */
+//@{
+#define HW_CMP_CR0_ADDR(x) (REGS_CMP_BASE(x) + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMP_CR0(x) (*(__IO hw_cmp_cr0_t *) HW_CMP_CR0_ADDR(x))
+#define HW_CMP_CR0_RD(x) (HW_CMP_CR0(x).U)
+#define HW_CMP_CR0_WR(x, v) (HW_CMP_CR0(x).U = (v))
+#define HW_CMP_CR0_SET(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) | (v)))
+#define HW_CMP_CR0_CLR(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) & ~(v)))
+#define HW_CMP_CR0_TOG(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMP_CR0 bitfields
+ */
+
+/*!
+ * @name Register CMP_CR0, field HYSTCTR[1:0] (RW)
+ *
+ * Defines the programmable hysteresis level. The hysteresis values associated
+ * with each level are device-specific. See the Data Sheet of the device for the
+ * exact values.
+ *
+ * Values:
+ * - 00 - Level 0
+ * - 01 - Level 1
+ * - 10 - Level 2
+ * - 11 - Level 3
+ */
+//@{
+#define BP_CMP_CR0_HYSTCTR (0U) //!< Bit position for CMP_CR0_HYSTCTR.
+#define BM_CMP_CR0_HYSTCTR (0x03U) //!< Bit mask for CMP_CR0_HYSTCTR.
+#define BS_CMP_CR0_HYSTCTR (2U) //!< Bit field size in bits for CMP_CR0_HYSTCTR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_CR0_HYSTCTR field.
+#define BR_CMP_CR0_HYSTCTR(x) (HW_CMP_CR0(x).B.HYSTCTR)
+#endif
+
+//! @brief Format value for bitfield CMP_CR0_HYSTCTR.
+#define BF_CMP_CR0_HYSTCTR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR0_HYSTCTR), uint8_t) & BM_CMP_CR0_HYSTCTR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HYSTCTR field to a new value.
+#define BW_CMP_CR0_HYSTCTR(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_HYSTCTR) | BF_CMP_CR0_HYSTCTR(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_CR0, field FILTER_CNT[6:4] (RW)
+ *
+ * Represents the number of consecutive samples that must agree prior to the
+ * comparator ouput filter accepting a new output state. For information regarding
+ * filter programming and latency, see the Functional descriptionThe CMP module
+ * can be used to compare two analog input voltages applied to INP and INM. .
+ *
+ * Values:
+ * - 000 - Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a
+ * legal state, and is not recommended. If SE = 0, COUT = COUTA.
+ * - 001 - One sample must agree. The comparator output is simply sampled.
+ * - 010 - 2 consecutive samples must agree.
+ * - 011 - 3 consecutive samples must agree.
+ * - 100 - 4 consecutive samples must agree.
+ * - 101 - 5 consecutive samples must agree.
+ * - 110 - 6 consecutive samples must agree.
+ * - 111 - 7 consecutive samples must agree.
+ */
+//@{
+#define BP_CMP_CR0_FILTER_CNT (4U) //!< Bit position for CMP_CR0_FILTER_CNT.
+#define BM_CMP_CR0_FILTER_CNT (0x70U) //!< Bit mask for CMP_CR0_FILTER_CNT.
+#define BS_CMP_CR0_FILTER_CNT (3U) //!< Bit field size in bits for CMP_CR0_FILTER_CNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_CR0_FILTER_CNT field.
+#define BR_CMP_CR0_FILTER_CNT(x) (HW_CMP_CR0(x).B.FILTER_CNT)
+#endif
+
+//! @brief Format value for bitfield CMP_CR0_FILTER_CNT.
+#define BF_CMP_CR0_FILTER_CNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR0_FILTER_CNT), uint8_t) & BM_CMP_CR0_FILTER_CNT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FILTER_CNT field to a new value.
+#define BW_CMP_CR0_FILTER_CNT(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_FILTER_CNT) | BF_CMP_CR0_FILTER_CNT(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMP_CR1 - CMP Control Register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMP_CR1 - CMP Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_cmp_cr1
+{
+ uint8_t U;
+ struct _hw_cmp_cr1_bitfields
+ {
+ uint8_t EN : 1; //!< [0] Comparator Module Enable
+ uint8_t OPE : 1; //!< [1] Comparator Output Pin Enable
+ uint8_t COS : 1; //!< [2] Comparator Output Select
+ uint8_t INV : 1; //!< [3] Comparator INVERT
+ uint8_t PMODE : 1; //!< [4] Power Mode Select
+ uint8_t RESERVED0 : 1; //!< [5]
+ uint8_t WE : 1; //!< [6] Windowing Enable
+ uint8_t SE : 1; //!< [7] Sample Enable
+ } B;
+} hw_cmp_cr1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMP_CR1 register
+ */
+//@{
+#define HW_CMP_CR1_ADDR(x) (REGS_CMP_BASE(x) + 0x1U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMP_CR1(x) (*(__IO hw_cmp_cr1_t *) HW_CMP_CR1_ADDR(x))
+#define HW_CMP_CR1_RD(x) (HW_CMP_CR1(x).U)
+#define HW_CMP_CR1_WR(x, v) (HW_CMP_CR1(x).U = (v))
+#define HW_CMP_CR1_SET(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) | (v)))
+#define HW_CMP_CR1_CLR(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) & ~(v)))
+#define HW_CMP_CR1_TOG(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMP_CR1 bitfields
+ */
+
+/*!
+ * @name Register CMP_CR1, field EN[0] (RW)
+ *
+ * Enables the Analog Comparator module. When the module is not enabled, it
+ * remains in the off state, and consumes no power. When the user selects the same
+ * input from analog mux to the positive and negative port, the comparator is
+ * disabled automatically.
+ *
+ * Values:
+ * - 0 - Analog Comparator is disabled.
+ * - 1 - Analog Comparator is enabled.
+ */
+//@{
+#define BP_CMP_CR1_EN (0U) //!< Bit position for CMP_CR1_EN.
+#define BM_CMP_CR1_EN (0x01U) //!< Bit mask for CMP_CR1_EN.
+#define BS_CMP_CR1_EN (1U) //!< Bit field size in bits for CMP_CR1_EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_CR1_EN field.
+#define BR_CMP_CR1_EN(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN))
+#endif
+
+//! @brief Format value for bitfield CMP_CR1_EN.
+#define BF_CMP_CR1_EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_EN), uint8_t) & BM_CMP_CR1_EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EN field to a new value.
+#define BW_CMP_CR1_EN(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_CR1, field OPE[1] (RW)
+ *
+ * Values:
+ * - 0 - CMPO is not available on the associated CMPO output pin. If the
+ * comparator does not own the pin, this field has no effect.
+ * - 1 - CMPO is available on the associated CMPO output pin. The comparator
+ * output (CMPO) is driven out on the associated CMPO output pin if the
+ * comparator owns the pin. If the comparator does not own the field, this bit has no
+ * effect.
+ */
+//@{
+#define BP_CMP_CR1_OPE (1U) //!< Bit position for CMP_CR1_OPE.
+#define BM_CMP_CR1_OPE (0x02U) //!< Bit mask for CMP_CR1_OPE.
+#define BS_CMP_CR1_OPE (1U) //!< Bit field size in bits for CMP_CR1_OPE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_CR1_OPE field.
+#define BR_CMP_CR1_OPE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE))
+#endif
+
+//! @brief Format value for bitfield CMP_CR1_OPE.
+#define BF_CMP_CR1_OPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_OPE), uint8_t) & BM_CMP_CR1_OPE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OPE field to a new value.
+#define BW_CMP_CR1_OPE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_CR1, field COS[2] (RW)
+ *
+ * Values:
+ * - 0 - Set the filtered comparator output (CMPO) to equal COUT.
+ * - 1 - Set the unfiltered comparator output (CMPO) to equal COUTA.
+ */
+//@{
+#define BP_CMP_CR1_COS (2U) //!< Bit position for CMP_CR1_COS.
+#define BM_CMP_CR1_COS (0x04U) //!< Bit mask for CMP_CR1_COS.
+#define BS_CMP_CR1_COS (1U) //!< Bit field size in bits for CMP_CR1_COS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_CR1_COS field.
+#define BR_CMP_CR1_COS(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS))
+#endif
+
+//! @brief Format value for bitfield CMP_CR1_COS.
+#define BF_CMP_CR1_COS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_COS), uint8_t) & BM_CMP_CR1_COS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COS field to a new value.
+#define BW_CMP_CR1_COS(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_CR1, field INV[3] (RW)
+ *
+ * Allows selection of the polarity of the analog comparator function. It is
+ * also driven to the COUT output, on both the device pin and as SCR[COUT], when
+ * OPE=0.
+ *
+ * Values:
+ * - 0 - Does not invert the comparator output.
+ * - 1 - Inverts the comparator output.
+ */
+//@{
+#define BP_CMP_CR1_INV (3U) //!< Bit position for CMP_CR1_INV.
+#define BM_CMP_CR1_INV (0x08U) //!< Bit mask for CMP_CR1_INV.
+#define BS_CMP_CR1_INV (1U) //!< Bit field size in bits for CMP_CR1_INV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_CR1_INV field.
+#define BR_CMP_CR1_INV(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV))
+#endif
+
+//! @brief Format value for bitfield CMP_CR1_INV.
+#define BF_CMP_CR1_INV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_INV), uint8_t) & BM_CMP_CR1_INV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INV field to a new value.
+#define BW_CMP_CR1_INV(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_CR1, field PMODE[4] (RW)
+ *
+ * See the electrical specifications table in the device Data Sheet for details.
+ *
+ * Values:
+ * - 0 - Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower
+ * output propagation delay and lower current consumption.
+ * - 1 - High-Speed (HS) Comparison mode selected. In this mode, CMP has faster
+ * output propagation delay and higher current consumption.
+ */
+//@{
+#define BP_CMP_CR1_PMODE (4U) //!< Bit position for CMP_CR1_PMODE.
+#define BM_CMP_CR1_PMODE (0x10U) //!< Bit mask for CMP_CR1_PMODE.
+#define BS_CMP_CR1_PMODE (1U) //!< Bit field size in bits for CMP_CR1_PMODE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_CR1_PMODE field.
+#define BR_CMP_CR1_PMODE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE))
+#endif
+
+//! @brief Format value for bitfield CMP_CR1_PMODE.
+#define BF_CMP_CR1_PMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_PMODE), uint8_t) & BM_CMP_CR1_PMODE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PMODE field to a new value.
+#define BW_CMP_CR1_PMODE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_CR1, field WE[6] (RW)
+ *
+ * At any given time, either SE or WE can be set. If a write to this register
+ * attempts to set both, then SE is set and WE is cleared. However, avoid writing
+ * 1s to both field locations because this "11" case is reserved and may change in
+ * future implementations.
+ *
+ * Values:
+ * - 0 - Windowing mode is not selected.
+ * - 1 - Windowing mode is selected.
+ */
+//@{
+#define BP_CMP_CR1_WE (6U) //!< Bit position for CMP_CR1_WE.
+#define BM_CMP_CR1_WE (0x40U) //!< Bit mask for CMP_CR1_WE.
+#define BS_CMP_CR1_WE (1U) //!< Bit field size in bits for CMP_CR1_WE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_CR1_WE field.
+#define BR_CMP_CR1_WE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE))
+#endif
+
+//! @brief Format value for bitfield CMP_CR1_WE.
+#define BF_CMP_CR1_WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_WE), uint8_t) & BM_CMP_CR1_WE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WE field to a new value.
+#define BW_CMP_CR1_WE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_CR1, field SE[7] (RW)
+ *
+ * At any given time, either SE or WE can be set. If a write to this register
+ * attempts to set both, then SE is set and WE is cleared. However, avoid writing
+ * 1s to both field locations because this "11" case is reserved and may change in
+ * future implementations.
+ *
+ * Values:
+ * - 0 - Sampling mode is not selected.
+ * - 1 - Sampling mode is selected.
+ */
+//@{
+#define BP_CMP_CR1_SE (7U) //!< Bit position for CMP_CR1_SE.
+#define BM_CMP_CR1_SE (0x80U) //!< Bit mask for CMP_CR1_SE.
+#define BS_CMP_CR1_SE (1U) //!< Bit field size in bits for CMP_CR1_SE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_CR1_SE field.
+#define BR_CMP_CR1_SE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE))
+#endif
+
+//! @brief Format value for bitfield CMP_CR1_SE.
+#define BF_CMP_CR1_SE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_SE), uint8_t) & BM_CMP_CR1_SE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SE field to a new value.
+#define BW_CMP_CR1_SE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMP_FPR - CMP Filter Period Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMP_FPR - CMP Filter Period Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_cmp_fpr
+{
+ uint8_t U;
+ struct _hw_cmp_fpr_bitfields
+ {
+ uint8_t FILT_PER : 8; //!< [7:0] Filter Sample Period
+ } B;
+} hw_cmp_fpr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMP_FPR register
+ */
+//@{
+#define HW_CMP_FPR_ADDR(x) (REGS_CMP_BASE(x) + 0x2U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMP_FPR(x) (*(__IO hw_cmp_fpr_t *) HW_CMP_FPR_ADDR(x))
+#define HW_CMP_FPR_RD(x) (HW_CMP_FPR(x).U)
+#define HW_CMP_FPR_WR(x, v) (HW_CMP_FPR(x).U = (v))
+#define HW_CMP_FPR_SET(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) | (v)))
+#define HW_CMP_FPR_CLR(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) & ~(v)))
+#define HW_CMP_FPR_TOG(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMP_FPR bitfields
+ */
+
+/*!
+ * @name Register CMP_FPR, field FILT_PER[7:0] (RW)
+ *
+ * Specifies the sampling period, in bus clock cycles, of the comparator output
+ * filter, when CR1[SE]=0. Setting FILT_PER to 0x0 disables the filter. Filter
+ * programming and latency details appear in the Functional descriptionThe CMP
+ * module can be used to compare two analog input voltages applied to INP and INM. .
+ * This field has no effect when CR1[SE]=1. In that case, the external SAMPLE
+ * signal is used to determine the sampling period.
+ */
+//@{
+#define BP_CMP_FPR_FILT_PER (0U) //!< Bit position for CMP_FPR_FILT_PER.
+#define BM_CMP_FPR_FILT_PER (0xFFU) //!< Bit mask for CMP_FPR_FILT_PER.
+#define BS_CMP_FPR_FILT_PER (8U) //!< Bit field size in bits for CMP_FPR_FILT_PER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_FPR_FILT_PER field.
+#define BR_CMP_FPR_FILT_PER(x) (HW_CMP_FPR(x).U)
+#endif
+
+//! @brief Format value for bitfield CMP_FPR_FILT_PER.
+#define BF_CMP_FPR_FILT_PER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_FPR_FILT_PER), uint8_t) & BM_CMP_FPR_FILT_PER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FILT_PER field to a new value.
+#define BW_CMP_FPR_FILT_PER(x, v) (HW_CMP_FPR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMP_SCR - CMP Status and Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMP_SCR - CMP Status and Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_cmp_scr
+{
+ uint8_t U;
+ struct _hw_cmp_scr_bitfields
+ {
+ uint8_t COUT : 1; //!< [0] Analog Comparator Output
+ uint8_t CFF : 1; //!< [1] Analog Comparator Flag Falling
+ uint8_t CFR : 1; //!< [2] Analog Comparator Flag Rising
+ uint8_t IEF : 1; //!< [3] Comparator Interrupt Enable Falling
+ uint8_t IER : 1; //!< [4] Comparator Interrupt Enable Rising
+ uint8_t RESERVED0 : 1; //!< [5]
+ uint8_t DMAEN : 1; //!< [6] DMA Enable Control
+ uint8_t RESERVED1 : 1; //!< [7]
+ } B;
+} hw_cmp_scr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMP_SCR register
+ */
+//@{
+#define HW_CMP_SCR_ADDR(x) (REGS_CMP_BASE(x) + 0x3U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMP_SCR(x) (*(__IO hw_cmp_scr_t *) HW_CMP_SCR_ADDR(x))
+#define HW_CMP_SCR_RD(x) (HW_CMP_SCR(x).U)
+#define HW_CMP_SCR_WR(x, v) (HW_CMP_SCR(x).U = (v))
+#define HW_CMP_SCR_SET(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) | (v)))
+#define HW_CMP_SCR_CLR(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) & ~(v)))
+#define HW_CMP_SCR_TOG(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMP_SCR bitfields
+ */
+
+/*!
+ * @name Register CMP_SCR, field COUT[0] (RO)
+ *
+ * Returns the current value of the Analog Comparator output, when read. The
+ * field is reset to 0 and will read as CR1[INV] when the Analog Comparator module
+ * is disabled, that is, when CR1[EN] = 0. Writes to this field are ignored.
+ */
+//@{
+#define BP_CMP_SCR_COUT (0U) //!< Bit position for CMP_SCR_COUT.
+#define BM_CMP_SCR_COUT (0x01U) //!< Bit mask for CMP_SCR_COUT.
+#define BS_CMP_SCR_COUT (1U) //!< Bit field size in bits for CMP_SCR_COUT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_SCR_COUT field.
+#define BR_CMP_SCR_COUT(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_COUT))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_SCR, field CFF[1] (W1C)
+ *
+ * Detects a falling-edge on COUT, when set, during normal operation. CFF is
+ * cleared by writing 1 to it. During Stop modes, CFF is level sensitive is edge
+ * sensitive .
+ *
+ * Values:
+ * - 0 - Falling-edge on COUT has not been detected.
+ * - 1 - Falling-edge on COUT has occurred.
+ */
+//@{
+#define BP_CMP_SCR_CFF (1U) //!< Bit position for CMP_SCR_CFF.
+#define BM_CMP_SCR_CFF (0x02U) //!< Bit mask for CMP_SCR_CFF.
+#define BS_CMP_SCR_CFF (1U) //!< Bit field size in bits for CMP_SCR_CFF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_SCR_CFF field.
+#define BR_CMP_SCR_CFF(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF))
+#endif
+
+//! @brief Format value for bitfield CMP_SCR_CFF.
+#define BF_CMP_SCR_CFF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_SCR_CFF), uint8_t) & BM_CMP_SCR_CFF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CFF field to a new value.
+#define BW_CMP_SCR_CFF(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_SCR, field CFR[2] (W1C)
+ *
+ * Detects a rising-edge on COUT, when set, during normal operation. CFR is
+ * cleared by writing 1 to it. During Stop modes, CFR is level sensitive is edge
+ * sensitive .
+ *
+ * Values:
+ * - 0 - Rising-edge on COUT has not been detected.
+ * - 1 - Rising-edge on COUT has occurred.
+ */
+//@{
+#define BP_CMP_SCR_CFR (2U) //!< Bit position for CMP_SCR_CFR.
+#define BM_CMP_SCR_CFR (0x04U) //!< Bit mask for CMP_SCR_CFR.
+#define BS_CMP_SCR_CFR (1U) //!< Bit field size in bits for CMP_SCR_CFR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_SCR_CFR field.
+#define BR_CMP_SCR_CFR(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR))
+#endif
+
+//! @brief Format value for bitfield CMP_SCR_CFR.
+#define BF_CMP_SCR_CFR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_SCR_CFR), uint8_t) & BM_CMP_SCR_CFR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CFR field to a new value.
+#define BW_CMP_SCR_CFR(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_SCR, field IEF[3] (RW)
+ *
+ * Enables the CFF interrupt from the CMP. When this field is set, an interrupt
+ * will be asserted when CFF is set.
+ *
+ * Values:
+ * - 0 - Interrupt is disabled.
+ * - 1 - Interrupt is enabled.
+ */
+//@{
+#define BP_CMP_SCR_IEF (3U) //!< Bit position for CMP_SCR_IEF.
+#define BM_CMP_SCR_IEF (0x08U) //!< Bit mask for CMP_SCR_IEF.
+#define BS_CMP_SCR_IEF (1U) //!< Bit field size in bits for CMP_SCR_IEF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_SCR_IEF field.
+#define BR_CMP_SCR_IEF(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF))
+#endif
+
+//! @brief Format value for bitfield CMP_SCR_IEF.
+#define BF_CMP_SCR_IEF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_SCR_IEF), uint8_t) & BM_CMP_SCR_IEF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IEF field to a new value.
+#define BW_CMP_SCR_IEF(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_SCR, field IER[4] (RW)
+ *
+ * Enables the CFR interrupt from the CMP. When this field is set, an interrupt
+ * will be asserted when CFR is set.
+ *
+ * Values:
+ * - 0 - Interrupt is disabled.
+ * - 1 - Interrupt is enabled.
+ */
+//@{
+#define BP_CMP_SCR_IER (4U) //!< Bit position for CMP_SCR_IER.
+#define BM_CMP_SCR_IER (0x10U) //!< Bit mask for CMP_SCR_IER.
+#define BS_CMP_SCR_IER (1U) //!< Bit field size in bits for CMP_SCR_IER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_SCR_IER field.
+#define BR_CMP_SCR_IER(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER))
+#endif
+
+//! @brief Format value for bitfield CMP_SCR_IER.
+#define BF_CMP_SCR_IER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_SCR_IER), uint8_t) & BM_CMP_SCR_IER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IER field to a new value.
+#define BW_CMP_SCR_IER(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_SCR, field DMAEN[6] (RW)
+ *
+ * Enables the DMA transfer triggered from the CMP module. When this field is
+ * set, a DMA request is asserted when CFR or CFF is set.
+ *
+ * Values:
+ * - 0 - DMA is disabled.
+ * - 1 - DMA is enabled.
+ */
+//@{
+#define BP_CMP_SCR_DMAEN (6U) //!< Bit position for CMP_SCR_DMAEN.
+#define BM_CMP_SCR_DMAEN (0x40U) //!< Bit mask for CMP_SCR_DMAEN.
+#define BS_CMP_SCR_DMAEN (1U) //!< Bit field size in bits for CMP_SCR_DMAEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_SCR_DMAEN field.
+#define BR_CMP_SCR_DMAEN(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN))
+#endif
+
+//! @brief Format value for bitfield CMP_SCR_DMAEN.
+#define BF_CMP_SCR_DMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_SCR_DMAEN), uint8_t) & BM_CMP_SCR_DMAEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMAEN field to a new value.
+#define BW_CMP_SCR_DMAEN(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMP_DACCR - DAC Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMP_DACCR - DAC Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_cmp_daccr
+{
+ uint8_t U;
+ struct _hw_cmp_daccr_bitfields
+ {
+ uint8_t VOSEL : 6; //!< [5:0] DAC Output Voltage Select
+ uint8_t VRSEL : 1; //!< [6] Supply Voltage Reference Source Select
+ uint8_t DACEN : 1; //!< [7] DAC Enable
+ } B;
+} hw_cmp_daccr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMP_DACCR register
+ */
+//@{
+#define HW_CMP_DACCR_ADDR(x) (REGS_CMP_BASE(x) + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMP_DACCR(x) (*(__IO hw_cmp_daccr_t *) HW_CMP_DACCR_ADDR(x))
+#define HW_CMP_DACCR_RD(x) (HW_CMP_DACCR(x).U)
+#define HW_CMP_DACCR_WR(x, v) (HW_CMP_DACCR(x).U = (v))
+#define HW_CMP_DACCR_SET(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) | (v)))
+#define HW_CMP_DACCR_CLR(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) & ~(v)))
+#define HW_CMP_DACCR_TOG(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMP_DACCR bitfields
+ */
+
+/*!
+ * @name Register CMP_DACCR, field VOSEL[5:0] (RW)
+ *
+ * Selects an output voltage from one of 64 distinct levels. DACO = (V in /64) *
+ * (VOSEL[5:0] + 1) , so the DACO range is from V in /64 to V in .
+ */
+//@{
+#define BP_CMP_DACCR_VOSEL (0U) //!< Bit position for CMP_DACCR_VOSEL.
+#define BM_CMP_DACCR_VOSEL (0x3FU) //!< Bit mask for CMP_DACCR_VOSEL.
+#define BS_CMP_DACCR_VOSEL (6U) //!< Bit field size in bits for CMP_DACCR_VOSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_DACCR_VOSEL field.
+#define BR_CMP_DACCR_VOSEL(x) (HW_CMP_DACCR(x).B.VOSEL)
+#endif
+
+//! @brief Format value for bitfield CMP_DACCR_VOSEL.
+#define BF_CMP_DACCR_VOSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_DACCR_VOSEL), uint8_t) & BM_CMP_DACCR_VOSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the VOSEL field to a new value.
+#define BW_CMP_DACCR_VOSEL(x, v) (HW_CMP_DACCR_WR(x, (HW_CMP_DACCR_RD(x) & ~BM_CMP_DACCR_VOSEL) | BF_CMP_DACCR_VOSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_DACCR, field VRSEL[6] (RW)
+ *
+ * Values:
+ * - 0 - V is selected as resistor ladder network supply reference V. in1 in
+ * - 1 - V is selected as resistor ladder network supply reference V. in2 in
+ */
+//@{
+#define BP_CMP_DACCR_VRSEL (6U) //!< Bit position for CMP_DACCR_VRSEL.
+#define BM_CMP_DACCR_VRSEL (0x40U) //!< Bit mask for CMP_DACCR_VRSEL.
+#define BS_CMP_DACCR_VRSEL (1U) //!< Bit field size in bits for CMP_DACCR_VRSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_DACCR_VRSEL field.
+#define BR_CMP_DACCR_VRSEL(x) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL))
+#endif
+
+//! @brief Format value for bitfield CMP_DACCR_VRSEL.
+#define BF_CMP_DACCR_VRSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_DACCR_VRSEL), uint8_t) & BM_CMP_DACCR_VRSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the VRSEL field to a new value.
+#define BW_CMP_DACCR_VRSEL(x, v) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_DACCR, field DACEN[7] (RW)
+ *
+ * Enables the DAC. When the DAC is disabled, it is powered down to conserve
+ * power.
+ *
+ * Values:
+ * - 0 - DAC is disabled.
+ * - 1 - DAC is enabled.
+ */
+//@{
+#define BP_CMP_DACCR_DACEN (7U) //!< Bit position for CMP_DACCR_DACEN.
+#define BM_CMP_DACCR_DACEN (0x80U) //!< Bit mask for CMP_DACCR_DACEN.
+#define BS_CMP_DACCR_DACEN (1U) //!< Bit field size in bits for CMP_DACCR_DACEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_DACCR_DACEN field.
+#define BR_CMP_DACCR_DACEN(x) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN))
+#endif
+
+//! @brief Format value for bitfield CMP_DACCR_DACEN.
+#define BF_CMP_DACCR_DACEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_DACCR_DACEN), uint8_t) & BM_CMP_DACCR_DACEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACEN field to a new value.
+#define BW_CMP_DACCR_DACEN(x, v) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMP_MUXCR - MUX Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMP_MUXCR - MUX Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_cmp_muxcr
+{
+ uint8_t U;
+ struct _hw_cmp_muxcr_bitfields
+ {
+ uint8_t MSEL : 3; //!< [2:0] Minus Input Mux Control
+ uint8_t PSEL : 3; //!< [5:3] Plus Input Mux Control
+ uint8_t RESERVED0 : 1; //!< [6]
+ uint8_t PSTM : 1; //!< [7] Pass Through Mode Enable
+ } B;
+} hw_cmp_muxcr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMP_MUXCR register
+ */
+//@{
+#define HW_CMP_MUXCR_ADDR(x) (REGS_CMP_BASE(x) + 0x5U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMP_MUXCR(x) (*(__IO hw_cmp_muxcr_t *) HW_CMP_MUXCR_ADDR(x))
+#define HW_CMP_MUXCR_RD(x) (HW_CMP_MUXCR(x).U)
+#define HW_CMP_MUXCR_WR(x, v) (HW_CMP_MUXCR(x).U = (v))
+#define HW_CMP_MUXCR_SET(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) | (v)))
+#define HW_CMP_MUXCR_CLR(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) & ~(v)))
+#define HW_CMP_MUXCR_TOG(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMP_MUXCR bitfields
+ */
+
+/*!
+ * @name Register CMP_MUXCR, field MSEL[2:0] (RW)
+ *
+ * Determines which input is selected for the minus input of the comparator. For
+ * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
+ * operation selects the same input for both muxes, the comparator automatically
+ * shuts down to prevent itself from becoming a noise generator.
+ *
+ * Values:
+ * - 000 - IN0
+ * - 001 - IN1
+ * - 010 - IN2
+ * - 011 - IN3
+ * - 100 - IN4
+ * - 101 - IN5
+ * - 110 - IN6
+ * - 111 - IN7
+ */
+//@{
+#define BP_CMP_MUXCR_MSEL (0U) //!< Bit position for CMP_MUXCR_MSEL.
+#define BM_CMP_MUXCR_MSEL (0x07U) //!< Bit mask for CMP_MUXCR_MSEL.
+#define BS_CMP_MUXCR_MSEL (3U) //!< Bit field size in bits for CMP_MUXCR_MSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_MUXCR_MSEL field.
+#define BR_CMP_MUXCR_MSEL(x) (HW_CMP_MUXCR(x).B.MSEL)
+#endif
+
+//! @brief Format value for bitfield CMP_MUXCR_MSEL.
+#define BF_CMP_MUXCR_MSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_MUXCR_MSEL), uint8_t) & BM_CMP_MUXCR_MSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MSEL field to a new value.
+#define BW_CMP_MUXCR_MSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_MSEL) | BF_CMP_MUXCR_MSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_MUXCR, field PSEL[5:3] (RW)
+ *
+ * Determines which input is selected for the plus input of the comparator. For
+ * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
+ * operation selects the same input for both muxes, the comparator automatically
+ * shuts down to prevent itself from becoming a noise generator.
+ *
+ * Values:
+ * - 000 - IN0
+ * - 001 - IN1
+ * - 010 - IN2
+ * - 011 - IN3
+ * - 100 - IN4
+ * - 101 - IN5
+ * - 110 - IN6
+ * - 111 - IN7
+ */
+//@{
+#define BP_CMP_MUXCR_PSEL (3U) //!< Bit position for CMP_MUXCR_PSEL.
+#define BM_CMP_MUXCR_PSEL (0x38U) //!< Bit mask for CMP_MUXCR_PSEL.
+#define BS_CMP_MUXCR_PSEL (3U) //!< Bit field size in bits for CMP_MUXCR_PSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_MUXCR_PSEL field.
+#define BR_CMP_MUXCR_PSEL(x) (HW_CMP_MUXCR(x).B.PSEL)
+#endif
+
+//! @brief Format value for bitfield CMP_MUXCR_PSEL.
+#define BF_CMP_MUXCR_PSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_MUXCR_PSEL), uint8_t) & BM_CMP_MUXCR_PSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PSEL field to a new value.
+#define BW_CMP_MUXCR_PSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_PSEL) | BF_CMP_MUXCR_PSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CMP_MUXCR, field PSTM[7] (RW)
+ *
+ * This bit is used to enable to MUX pass through mode. Pass through mode is
+ * always available but for some devices this feature must be always disabled due to
+ * the lack of package pins.
+ *
+ * Values:
+ * - 0 - Pass Through Mode is disabled.
+ * - 1 - Pass Through Mode is enabled.
+ */
+//@{
+#define BP_CMP_MUXCR_PSTM (7U) //!< Bit position for CMP_MUXCR_PSTM.
+#define BM_CMP_MUXCR_PSTM (0x80U) //!< Bit mask for CMP_MUXCR_PSTM.
+#define BS_CMP_MUXCR_PSTM (1U) //!< Bit field size in bits for CMP_MUXCR_PSTM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMP_MUXCR_PSTM field.
+#define BR_CMP_MUXCR_PSTM(x) (BITBAND_ACCESS8(HW_CMP_MUXCR_ADDR(x), BP_CMP_MUXCR_PSTM))
+#endif
+
+//! @brief Format value for bitfield CMP_MUXCR_PSTM.
+#define BF_CMP_MUXCR_PSTM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_MUXCR_PSTM), uint8_t) & BM_CMP_MUXCR_PSTM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PSTM field to a new value.
+#define BW_CMP_MUXCR_PSTM(x, v) (BITBAND_ACCESS8(HW_CMP_MUXCR_ADDR(x), BP_CMP_MUXCR_PSTM) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_cmp_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All CMP module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_cmp
+{
+ __IO hw_cmp_cr0_t CR0; //!< [0x0] CMP Control Register 0
+ __IO hw_cmp_cr1_t CR1; //!< [0x1] CMP Control Register 1
+ __IO hw_cmp_fpr_t FPR; //!< [0x2] CMP Filter Period Register
+ __IO hw_cmp_scr_t SCR; //!< [0x3] CMP Status and Control Register
+ __IO hw_cmp_daccr_t DACCR; //!< [0x4] DAC Control Register
+ __IO hw_cmp_muxcr_t MUXCR; //!< [0x5] MUX Control Register
+} hw_cmp_t;
+#pragma pack()
+
+//! @brief Macro to access all CMP registers.
+//! @param x CMP instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_CMP(0)</code>.
+#define HW_CMP(x) (*(hw_cmp_t *) REGS_CMP_BASE(x))
+#endif
+
+#endif // __HW_CMP_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_cmt.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,1194 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_CMT_REGISTERS_H__
+#define __HW_CMT_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 CMT
+ *
+ * Carrier Modulator Transmitter
+ *
+ * Registers defined in this header file:
+ * - HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1
+ * - HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1
+ * - HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2
+ * - HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2
+ * - HW_CMT_OC - CMT Output Control Register
+ * - HW_CMT_MSC - CMT Modulator Status and Control Register
+ * - HW_CMT_CMD1 - CMT Modulator Data Register Mark High
+ * - HW_CMT_CMD2 - CMT Modulator Data Register Mark Low
+ * - HW_CMT_CMD3 - CMT Modulator Data Register Space High
+ * - HW_CMT_CMD4 - CMT Modulator Data Register Space Low
+ * - HW_CMT_PPS - CMT Primary Prescaler Register
+ * - HW_CMT_DMA - CMT Direct Memory Access Register
+ *
+ * - hw_cmt_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_CMT_BASE
+#define HW_CMT_INSTANCE_COUNT (1U) //!< Number of instances of the CMT module.
+#define REGS_CMT_BASE (0x40062000U) //!< Base address for CMT.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the primary high value for generating the carrier
+ * output.
+ */
+typedef union _hw_cmt_cgh1
+{
+ uint8_t U;
+ struct _hw_cmt_cgh1_bitfields
+ {
+ uint8_t PH : 8; //!< [7:0] Primary Carrier High Time Data Value
+ } B;
+} hw_cmt_cgh1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMT_CGH1 register
+ */
+//@{
+#define HW_CMT_CGH1_ADDR (REGS_CMT_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMT_CGH1 (*(__IO hw_cmt_cgh1_t *) HW_CMT_CGH1_ADDR)
+#define HW_CMT_CGH1_RD() (HW_CMT_CGH1.U)
+#define HW_CMT_CGH1_WR(v) (HW_CMT_CGH1.U = (v))
+#define HW_CMT_CGH1_SET(v) (HW_CMT_CGH1_WR(HW_CMT_CGH1_RD() | (v)))
+#define HW_CMT_CGH1_CLR(v) (HW_CMT_CGH1_WR(HW_CMT_CGH1_RD() & ~(v)))
+#define HW_CMT_CGH1_TOG(v) (HW_CMT_CGH1_WR(HW_CMT_CGH1_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMT_CGH1 bitfields
+ */
+
+/*!
+ * @name Register CMT_CGH1, field PH[7:0] (RW)
+ *
+ * Contains the number of input clocks required to generate the carrier high
+ * time period. When operating in Time mode, this register is always selected. When
+ * operating in FSK mode, this register and the secondary register pair are
+ * alternately selected under the control of the modulator. The primary carrier high
+ * time value is undefined out of reset. This register must be written to nonzero
+ * values before the carrier generator is enabled to avoid spurious results.
+ */
+//@{
+#define BP_CMT_CGH1_PH (0U) //!< Bit position for CMT_CGH1_PH.
+#define BM_CMT_CGH1_PH (0xFFU) //!< Bit mask for CMT_CGH1_PH.
+#define BS_CMT_CGH1_PH (8U) //!< Bit field size in bits for CMT_CGH1_PH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_CGH1_PH field.
+#define BR_CMT_CGH1_PH (HW_CMT_CGH1.U)
+#endif
+
+//! @brief Format value for bitfield CMT_CGH1_PH.
+#define BF_CMT_CGH1_PH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CGH1_PH), uint8_t) & BM_CMT_CGH1_PH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PH field to a new value.
+#define BW_CMT_CGH1_PH(v) (HW_CMT_CGH1_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the primary low value for generating the carrier
+ * output.
+ */
+typedef union _hw_cmt_cgl1
+{
+ uint8_t U;
+ struct _hw_cmt_cgl1_bitfields
+ {
+ uint8_t PL : 8; //!< [7:0] Primary Carrier Low Time Data Value
+ } B;
+} hw_cmt_cgl1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMT_CGL1 register
+ */
+//@{
+#define HW_CMT_CGL1_ADDR (REGS_CMT_BASE + 0x1U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMT_CGL1 (*(__IO hw_cmt_cgl1_t *) HW_CMT_CGL1_ADDR)
+#define HW_CMT_CGL1_RD() (HW_CMT_CGL1.U)
+#define HW_CMT_CGL1_WR(v) (HW_CMT_CGL1.U = (v))
+#define HW_CMT_CGL1_SET(v) (HW_CMT_CGL1_WR(HW_CMT_CGL1_RD() | (v)))
+#define HW_CMT_CGL1_CLR(v) (HW_CMT_CGL1_WR(HW_CMT_CGL1_RD() & ~(v)))
+#define HW_CMT_CGL1_TOG(v) (HW_CMT_CGL1_WR(HW_CMT_CGL1_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMT_CGL1 bitfields
+ */
+
+/*!
+ * @name Register CMT_CGL1, field PL[7:0] (RW)
+ *
+ * Contains the number of input clocks required to generate the carrier low time
+ * period. When operating in Time mode, this register is always selected. When
+ * operating in FSK mode, this register and the secondary register pair are
+ * alternately selected under the control of the modulator. The primary carrier low
+ * time value is undefined out of reset. This register must be written to nonzero
+ * values before the carrier generator is enabled to avoid spurious results.
+ */
+//@{
+#define BP_CMT_CGL1_PL (0U) //!< Bit position for CMT_CGL1_PL.
+#define BM_CMT_CGL1_PL (0xFFU) //!< Bit mask for CMT_CGL1_PL.
+#define BS_CMT_CGL1_PL (8U) //!< Bit field size in bits for CMT_CGL1_PL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_CGL1_PL field.
+#define BR_CMT_CGL1_PL (HW_CMT_CGL1.U)
+#endif
+
+//! @brief Format value for bitfield CMT_CGL1_PL.
+#define BF_CMT_CGL1_PL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CGL1_PL), uint8_t) & BM_CMT_CGL1_PL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PL field to a new value.
+#define BW_CMT_CGL1_PL(v) (HW_CMT_CGL1_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the secondary high value for generating the
+ * carrier output.
+ */
+typedef union _hw_cmt_cgh2
+{
+ uint8_t U;
+ struct _hw_cmt_cgh2_bitfields
+ {
+ uint8_t SH : 8; //!< [7:0] Secondary Carrier High Time Data Value
+ } B;
+} hw_cmt_cgh2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMT_CGH2 register
+ */
+//@{
+#define HW_CMT_CGH2_ADDR (REGS_CMT_BASE + 0x2U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMT_CGH2 (*(__IO hw_cmt_cgh2_t *) HW_CMT_CGH2_ADDR)
+#define HW_CMT_CGH2_RD() (HW_CMT_CGH2.U)
+#define HW_CMT_CGH2_WR(v) (HW_CMT_CGH2.U = (v))
+#define HW_CMT_CGH2_SET(v) (HW_CMT_CGH2_WR(HW_CMT_CGH2_RD() | (v)))
+#define HW_CMT_CGH2_CLR(v) (HW_CMT_CGH2_WR(HW_CMT_CGH2_RD() & ~(v)))
+#define HW_CMT_CGH2_TOG(v) (HW_CMT_CGH2_WR(HW_CMT_CGH2_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMT_CGH2 bitfields
+ */
+
+/*!
+ * @name Register CMT_CGH2, field SH[7:0] (RW)
+ *
+ * Contains the number of input clocks required to generate the carrier high
+ * time period. When operating in Time mode, this register is never selected. When
+ * operating in FSK mode, this register and the primary register pair are
+ * alternately selected under control of the modulator. The secondary carrier high time
+ * value is undefined out of reset. This register must be written to nonzero
+ * values before the carrier generator is enabled when operating in FSK mode.
+ */
+//@{
+#define BP_CMT_CGH2_SH (0U) //!< Bit position for CMT_CGH2_SH.
+#define BM_CMT_CGH2_SH (0xFFU) //!< Bit mask for CMT_CGH2_SH.
+#define BS_CMT_CGH2_SH (8U) //!< Bit field size in bits for CMT_CGH2_SH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_CGH2_SH field.
+#define BR_CMT_CGH2_SH (HW_CMT_CGH2.U)
+#endif
+
+//! @brief Format value for bitfield CMT_CGH2_SH.
+#define BF_CMT_CGH2_SH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CGH2_SH), uint8_t) & BM_CMT_CGH2_SH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SH field to a new value.
+#define BW_CMT_CGH2_SH(v) (HW_CMT_CGH2_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the secondary low value for generating the
+ * carrier output.
+ */
+typedef union _hw_cmt_cgl2
+{
+ uint8_t U;
+ struct _hw_cmt_cgl2_bitfields
+ {
+ uint8_t SL : 8; //!< [7:0] Secondary Carrier Low Time Data Value
+ } B;
+} hw_cmt_cgl2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMT_CGL2 register
+ */
+//@{
+#define HW_CMT_CGL2_ADDR (REGS_CMT_BASE + 0x3U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMT_CGL2 (*(__IO hw_cmt_cgl2_t *) HW_CMT_CGL2_ADDR)
+#define HW_CMT_CGL2_RD() (HW_CMT_CGL2.U)
+#define HW_CMT_CGL2_WR(v) (HW_CMT_CGL2.U = (v))
+#define HW_CMT_CGL2_SET(v) (HW_CMT_CGL2_WR(HW_CMT_CGL2_RD() | (v)))
+#define HW_CMT_CGL2_CLR(v) (HW_CMT_CGL2_WR(HW_CMT_CGL2_RD() & ~(v)))
+#define HW_CMT_CGL2_TOG(v) (HW_CMT_CGL2_WR(HW_CMT_CGL2_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMT_CGL2 bitfields
+ */
+
+/*!
+ * @name Register CMT_CGL2, field SL[7:0] (RW)
+ *
+ * Contains the number of input clocks required to generate the carrier low time
+ * period. When operating in Time mode, this register is never selected. When
+ * operating in FSK mode, this register and the primary register pair are
+ * alternately selected under the control of the modulator. The secondary carrier low time
+ * value is undefined out of reset. This register must be written to nonzero
+ * values before the carrier generator is enabled when operating in FSK mode.
+ */
+//@{
+#define BP_CMT_CGL2_SL (0U) //!< Bit position for CMT_CGL2_SL.
+#define BM_CMT_CGL2_SL (0xFFU) //!< Bit mask for CMT_CGL2_SL.
+#define BS_CMT_CGL2_SL (8U) //!< Bit field size in bits for CMT_CGL2_SL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_CGL2_SL field.
+#define BR_CMT_CGL2_SL (HW_CMT_CGL2.U)
+#endif
+
+//! @brief Format value for bitfield CMT_CGL2_SL.
+#define BF_CMT_CGL2_SL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CGL2_SL), uint8_t) & BM_CMT_CGL2_SL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SL field to a new value.
+#define BW_CMT_CGL2_SL(v) (HW_CMT_CGL2_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMT_OC - CMT Output Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMT_OC - CMT Output Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is used to control the IRO signal of the CMT module.
+ */
+typedef union _hw_cmt_oc
+{
+ uint8_t U;
+ struct _hw_cmt_oc_bitfields
+ {
+ uint8_t RESERVED0 : 5; //!< [4:0]
+ uint8_t IROPEN : 1; //!< [5] IRO Pin Enable
+ uint8_t CMTPOL : 1; //!< [6] CMT Output Polarity
+ uint8_t IROL : 1; //!< [7] IRO Latch Control
+ } B;
+} hw_cmt_oc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMT_OC register
+ */
+//@{
+#define HW_CMT_OC_ADDR (REGS_CMT_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMT_OC (*(__IO hw_cmt_oc_t *) HW_CMT_OC_ADDR)
+#define HW_CMT_OC_RD() (HW_CMT_OC.U)
+#define HW_CMT_OC_WR(v) (HW_CMT_OC.U = (v))
+#define HW_CMT_OC_SET(v) (HW_CMT_OC_WR(HW_CMT_OC_RD() | (v)))
+#define HW_CMT_OC_CLR(v) (HW_CMT_OC_WR(HW_CMT_OC_RD() & ~(v)))
+#define HW_CMT_OC_TOG(v) (HW_CMT_OC_WR(HW_CMT_OC_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMT_OC bitfields
+ */
+
+/*!
+ * @name Register CMT_OC, field IROPEN[5] (RW)
+ *
+ * Enables and disables the IRO signal. When the IRO signal is enabled, it is an
+ * output that drives out either the CMT transmitter output or the state of IROL
+ * depending on whether MSC[MCGEN] is set or not. Also, the state of output is
+ * either inverted or non-inverted, depending on the state of CMTPOL. When the IRO
+ * signal is disabled, it is in a high-impedance state and is unable to draw any
+ * current. This signal is disabled during reset.
+ *
+ * Values:
+ * - 0 - The IRO signal is disabled.
+ * - 1 - The IRO signal is enabled as output.
+ */
+//@{
+#define BP_CMT_OC_IROPEN (5U) //!< Bit position for CMT_OC_IROPEN.
+#define BM_CMT_OC_IROPEN (0x20U) //!< Bit mask for CMT_OC_IROPEN.
+#define BS_CMT_OC_IROPEN (1U) //!< Bit field size in bits for CMT_OC_IROPEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_OC_IROPEN field.
+#define BR_CMT_OC_IROPEN (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_IROPEN))
+#endif
+
+//! @brief Format value for bitfield CMT_OC_IROPEN.
+#define BF_CMT_OC_IROPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_OC_IROPEN), uint8_t) & BM_CMT_OC_IROPEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IROPEN field to a new value.
+#define BW_CMT_OC_IROPEN(v) (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_IROPEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMT_OC, field CMTPOL[6] (RW)
+ *
+ * Controls the polarity of the IRO signal.
+ *
+ * Values:
+ * - 0 - The IRO signal is active-low.
+ * - 1 - The IRO signal is active-high.
+ */
+//@{
+#define BP_CMT_OC_CMTPOL (6U) //!< Bit position for CMT_OC_CMTPOL.
+#define BM_CMT_OC_CMTPOL (0x40U) //!< Bit mask for CMT_OC_CMTPOL.
+#define BS_CMT_OC_CMTPOL (1U) //!< Bit field size in bits for CMT_OC_CMTPOL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_OC_CMTPOL field.
+#define BR_CMT_OC_CMTPOL (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_CMTPOL))
+#endif
+
+//! @brief Format value for bitfield CMT_OC_CMTPOL.
+#define BF_CMT_OC_CMTPOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_OC_CMTPOL), uint8_t) & BM_CMT_OC_CMTPOL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CMTPOL field to a new value.
+#define BW_CMT_OC_CMTPOL(v) (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_CMTPOL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMT_OC, field IROL[7] (RW)
+ *
+ * Reads the state of the IRO latch. Writing to IROL changes the state of the
+ * IRO signal when MSC[MCGEN] is cleared and IROPEN is set.
+ */
+//@{
+#define BP_CMT_OC_IROL (7U) //!< Bit position for CMT_OC_IROL.
+#define BM_CMT_OC_IROL (0x80U) //!< Bit mask for CMT_OC_IROL.
+#define BS_CMT_OC_IROL (1U) //!< Bit field size in bits for CMT_OC_IROL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_OC_IROL field.
+#define BR_CMT_OC_IROL (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_IROL))
+#endif
+
+//! @brief Format value for bitfield CMT_OC_IROL.
+#define BF_CMT_OC_IROL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_OC_IROL), uint8_t) & BM_CMT_OC_IROL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IROL field to a new value.
+#define BW_CMT_OC_IROL(v) (BITBAND_ACCESS8(HW_CMT_OC_ADDR, BP_CMT_OC_IROL) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMT_MSC - CMT Modulator Status and Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMT_MSC - CMT Modulator Status and Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains the modulator and carrier generator enable (MCGEN),
+ * end of cycle interrupt enable (EOCIE), FSK mode select (FSK), baseband enable
+ * (BASE), extended space (EXSPC), prescaler (CMTDIV) bits, and the end of cycle
+ * (EOCF) status bit.
+ */
+typedef union _hw_cmt_msc
+{
+ uint8_t U;
+ struct _hw_cmt_msc_bitfields
+ {
+ uint8_t MCGEN : 1; //!< [0] Modulator and Carrier Generator Enable
+ uint8_t EOCIE : 1; //!< [1] End of Cycle Interrupt Enable
+ uint8_t FSK : 1; //!< [2] FSK Mode Select
+ uint8_t BASE : 1; //!< [3] Baseband Enable
+ uint8_t EXSPC : 1; //!< [4] Extended Space Enable
+ uint8_t CMTDIV : 2; //!< [6:5] CMT Clock Divide Prescaler
+ uint8_t EOCF : 1; //!< [7] End Of Cycle Status Flag
+ } B;
+} hw_cmt_msc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMT_MSC register
+ */
+//@{
+#define HW_CMT_MSC_ADDR (REGS_CMT_BASE + 0x5U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMT_MSC (*(__IO hw_cmt_msc_t *) HW_CMT_MSC_ADDR)
+#define HW_CMT_MSC_RD() (HW_CMT_MSC.U)
+#define HW_CMT_MSC_WR(v) (HW_CMT_MSC.U = (v))
+#define HW_CMT_MSC_SET(v) (HW_CMT_MSC_WR(HW_CMT_MSC_RD() | (v)))
+#define HW_CMT_MSC_CLR(v) (HW_CMT_MSC_WR(HW_CMT_MSC_RD() & ~(v)))
+#define HW_CMT_MSC_TOG(v) (HW_CMT_MSC_WR(HW_CMT_MSC_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMT_MSC bitfields
+ */
+
+/*!
+ * @name Register CMT_MSC, field MCGEN[0] (RW)
+ *
+ * Setting MCGEN will initialize the carrier generator and modulator and will
+ * enable all clocks. When enabled, the carrier generator and modulator will
+ * function continuously. When MCGEN is cleared, the current modulator cycle will be
+ * allowed to expire before all carrier and modulator clocks are disabled to save
+ * power and the modulator output is forced low. To prevent spurious operation,
+ * the user should initialize all data and control registers before enabling the
+ * system.
+ *
+ * Values:
+ * - 0 - Modulator and carrier generator disabled
+ * - 1 - Modulator and carrier generator enabled
+ */
+//@{
+#define BP_CMT_MSC_MCGEN (0U) //!< Bit position for CMT_MSC_MCGEN.
+#define BM_CMT_MSC_MCGEN (0x01U) //!< Bit mask for CMT_MSC_MCGEN.
+#define BS_CMT_MSC_MCGEN (1U) //!< Bit field size in bits for CMT_MSC_MCGEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_MSC_MCGEN field.
+#define BR_CMT_MSC_MCGEN (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_MCGEN))
+#endif
+
+//! @brief Format value for bitfield CMT_MSC_MCGEN.
+#define BF_CMT_MSC_MCGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_MCGEN), uint8_t) & BM_CMT_MSC_MCGEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MCGEN field to a new value.
+#define BW_CMT_MSC_MCGEN(v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_MCGEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMT_MSC, field EOCIE[1] (RW)
+ *
+ * Requests to enable a CPU interrupt when EOCF is set if EOCIE is high.
+ *
+ * Values:
+ * - 0 - CPU interrupt is disabled.
+ * - 1 - CPU interrupt is enabled.
+ */
+//@{
+#define BP_CMT_MSC_EOCIE (1U) //!< Bit position for CMT_MSC_EOCIE.
+#define BM_CMT_MSC_EOCIE (0x02U) //!< Bit mask for CMT_MSC_EOCIE.
+#define BS_CMT_MSC_EOCIE (1U) //!< Bit field size in bits for CMT_MSC_EOCIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_MSC_EOCIE field.
+#define BR_CMT_MSC_EOCIE (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_EOCIE))
+#endif
+
+//! @brief Format value for bitfield CMT_MSC_EOCIE.
+#define BF_CMT_MSC_EOCIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_EOCIE), uint8_t) & BM_CMT_MSC_EOCIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EOCIE field to a new value.
+#define BW_CMT_MSC_EOCIE(v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_EOCIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMT_MSC, field FSK[2] (RW)
+ *
+ * Enables FSK operation.
+ *
+ * Values:
+ * - 0 - The CMT operates in Time or Baseband mode.
+ * - 1 - The CMT operates in FSK mode.
+ */
+//@{
+#define BP_CMT_MSC_FSK (2U) //!< Bit position for CMT_MSC_FSK.
+#define BM_CMT_MSC_FSK (0x04U) //!< Bit mask for CMT_MSC_FSK.
+#define BS_CMT_MSC_FSK (1U) //!< Bit field size in bits for CMT_MSC_FSK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_MSC_FSK field.
+#define BR_CMT_MSC_FSK (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_FSK))
+#endif
+
+//! @brief Format value for bitfield CMT_MSC_FSK.
+#define BF_CMT_MSC_FSK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_FSK), uint8_t) & BM_CMT_MSC_FSK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FSK field to a new value.
+#define BW_CMT_MSC_FSK(v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_FSK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMT_MSC, field BASE[3] (RW)
+ *
+ * When set, BASE disables the carrier generator and forces the carrier output
+ * high for generation of baseband protocols. When BASE is cleared, the carrier
+ * generator is enabled and the carrier output toggles at the frequency determined
+ * by values stored in the carrier data registers. This field is cleared by
+ * reset. This field is not double-buffered and must not be written to during a
+ * transmission.
+ *
+ * Values:
+ * - 0 - Baseband mode is disabled.
+ * - 1 - Baseband mode is enabled.
+ */
+//@{
+#define BP_CMT_MSC_BASE (3U) //!< Bit position for CMT_MSC_BASE.
+#define BM_CMT_MSC_BASE (0x08U) //!< Bit mask for CMT_MSC_BASE.
+#define BS_CMT_MSC_BASE (1U) //!< Bit field size in bits for CMT_MSC_BASE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_MSC_BASE field.
+#define BR_CMT_MSC_BASE (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_BASE))
+#endif
+
+//! @brief Format value for bitfield CMT_MSC_BASE.
+#define BF_CMT_MSC_BASE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_BASE), uint8_t) & BM_CMT_MSC_BASE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BASE field to a new value.
+#define BW_CMT_MSC_BASE(v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_BASE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMT_MSC, field EXSPC[4] (RW)
+ *
+ * Enables the extended space operation.
+ *
+ * Values:
+ * - 0 - Extended space is disabled.
+ * - 1 - Extended space is enabled.
+ */
+//@{
+#define BP_CMT_MSC_EXSPC (4U) //!< Bit position for CMT_MSC_EXSPC.
+#define BM_CMT_MSC_EXSPC (0x10U) //!< Bit mask for CMT_MSC_EXSPC.
+#define BS_CMT_MSC_EXSPC (1U) //!< Bit field size in bits for CMT_MSC_EXSPC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_MSC_EXSPC field.
+#define BR_CMT_MSC_EXSPC (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_EXSPC))
+#endif
+
+//! @brief Format value for bitfield CMT_MSC_EXSPC.
+#define BF_CMT_MSC_EXSPC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_EXSPC), uint8_t) & BM_CMT_MSC_EXSPC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EXSPC field to a new value.
+#define BW_CMT_MSC_EXSPC(v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_EXSPC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CMT_MSC, field CMTDIV[6:5] (RW)
+ *
+ * Causes the CMT to be clocked at the IF signal frequency, or the IF frequency
+ * divided by 2 ,4, or 8 . This field must not be changed during a transmission
+ * because it is not double-buffered.
+ *
+ * Values:
+ * - 00 - IF * 1
+ * - 01 - IF * 2
+ * - 10 - IF * 4
+ * - 11 - IF * 8
+ */
+//@{
+#define BP_CMT_MSC_CMTDIV (5U) //!< Bit position for CMT_MSC_CMTDIV.
+#define BM_CMT_MSC_CMTDIV (0x60U) //!< Bit mask for CMT_MSC_CMTDIV.
+#define BS_CMT_MSC_CMTDIV (2U) //!< Bit field size in bits for CMT_MSC_CMTDIV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_MSC_CMTDIV field.
+#define BR_CMT_MSC_CMTDIV (HW_CMT_MSC.B.CMTDIV)
+#endif
+
+//! @brief Format value for bitfield CMT_MSC_CMTDIV.
+#define BF_CMT_MSC_CMTDIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_MSC_CMTDIV), uint8_t) & BM_CMT_MSC_CMTDIV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CMTDIV field to a new value.
+#define BW_CMT_MSC_CMTDIV(v) (HW_CMT_MSC_WR((HW_CMT_MSC_RD() & ~BM_CMT_MSC_CMTDIV) | BF_CMT_MSC_CMTDIV(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CMT_MSC, field EOCF[7] (RO)
+ *
+ * Sets when: The modulator is not currently active and MCGEN is set to begin
+ * the initial CMT transmission. At the end of each modulation cycle while MCGEN is
+ * set. This is recognized when a match occurs between the contents of the space
+ * period register and the down counter. At this time, the counter is
+ * initialized with, possibly new contents of the mark period buffer, CMD1 and CMD2, and
+ * the space period register is loaded with, possibly new contents of the space
+ * period buffer, CMD3 and CMD4. This flag is cleared by reading MSC followed by an
+ * access of CMD2 or CMD4, or by the DMA transfer.
+ *
+ * Values:
+ * - 0 - End of modulation cycle has not occured since the flag last cleared.
+ * - 1 - End of modulator cycle has occurred.
+ */
+//@{
+#define BP_CMT_MSC_EOCF (7U) //!< Bit position for CMT_MSC_EOCF.
+#define BM_CMT_MSC_EOCF (0x80U) //!< Bit mask for CMT_MSC_EOCF.
+#define BS_CMT_MSC_EOCF (1U) //!< Bit field size in bits for CMT_MSC_EOCF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_MSC_EOCF field.
+#define BR_CMT_MSC_EOCF (BITBAND_ACCESS8(HW_CMT_MSC_ADDR, BP_CMT_MSC_EOCF))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMT_CMD1 - CMT Modulator Data Register Mark High
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMT_CMD1 - CMT Modulator Data Register Mark High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the modulator down counter
+ * upon the completion of a modulation period.
+ */
+typedef union _hw_cmt_cmd1
+{
+ uint8_t U;
+ struct _hw_cmt_cmd1_bitfields
+ {
+ uint8_t MB : 8; //!< [7:0]
+ } B;
+} hw_cmt_cmd1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMT_CMD1 register
+ */
+//@{
+#define HW_CMT_CMD1_ADDR (REGS_CMT_BASE + 0x6U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMT_CMD1 (*(__IO hw_cmt_cmd1_t *) HW_CMT_CMD1_ADDR)
+#define HW_CMT_CMD1_RD() (HW_CMT_CMD1.U)
+#define HW_CMT_CMD1_WR(v) (HW_CMT_CMD1.U = (v))
+#define HW_CMT_CMD1_SET(v) (HW_CMT_CMD1_WR(HW_CMT_CMD1_RD() | (v)))
+#define HW_CMT_CMD1_CLR(v) (HW_CMT_CMD1_WR(HW_CMT_CMD1_RD() & ~(v)))
+#define HW_CMT_CMD1_TOG(v) (HW_CMT_CMD1_WR(HW_CMT_CMD1_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMT_CMD1 bitfields
+ */
+
+/*!
+ * @name Register CMT_CMD1, field MB[7:0] (RW)
+ *
+ * Controls the upper mark periods of the modulator for all modes.
+ */
+//@{
+#define BP_CMT_CMD1_MB (0U) //!< Bit position for CMT_CMD1_MB.
+#define BM_CMT_CMD1_MB (0xFFU) //!< Bit mask for CMT_CMD1_MB.
+#define BS_CMT_CMD1_MB (8U) //!< Bit field size in bits for CMT_CMD1_MB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_CMD1_MB field.
+#define BR_CMT_CMD1_MB (HW_CMT_CMD1.U)
+#endif
+
+//! @brief Format value for bitfield CMT_CMD1_MB.
+#define BF_CMT_CMD1_MB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CMD1_MB), uint8_t) & BM_CMT_CMD1_MB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MB field to a new value.
+#define BW_CMT_CMD1_MB(v) (HW_CMT_CMD1_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMT_CMD2 - CMT Modulator Data Register Mark Low
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMT_CMD2 - CMT Modulator Data Register Mark Low (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the modulator down counter
+ * upon the completion of a modulation period.
+ */
+typedef union _hw_cmt_cmd2
+{
+ uint8_t U;
+ struct _hw_cmt_cmd2_bitfields
+ {
+ uint8_t MB : 8; //!< [7:0]
+ } B;
+} hw_cmt_cmd2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMT_CMD2 register
+ */
+//@{
+#define HW_CMT_CMD2_ADDR (REGS_CMT_BASE + 0x7U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMT_CMD2 (*(__IO hw_cmt_cmd2_t *) HW_CMT_CMD2_ADDR)
+#define HW_CMT_CMD2_RD() (HW_CMT_CMD2.U)
+#define HW_CMT_CMD2_WR(v) (HW_CMT_CMD2.U = (v))
+#define HW_CMT_CMD2_SET(v) (HW_CMT_CMD2_WR(HW_CMT_CMD2_RD() | (v)))
+#define HW_CMT_CMD2_CLR(v) (HW_CMT_CMD2_WR(HW_CMT_CMD2_RD() & ~(v)))
+#define HW_CMT_CMD2_TOG(v) (HW_CMT_CMD2_WR(HW_CMT_CMD2_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMT_CMD2 bitfields
+ */
+
+/*!
+ * @name Register CMT_CMD2, field MB[7:0] (RW)
+ *
+ * Controls the lower mark periods of the modulator for all modes.
+ */
+//@{
+#define BP_CMT_CMD2_MB (0U) //!< Bit position for CMT_CMD2_MB.
+#define BM_CMT_CMD2_MB (0xFFU) //!< Bit mask for CMT_CMD2_MB.
+#define BS_CMT_CMD2_MB (8U) //!< Bit field size in bits for CMT_CMD2_MB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_CMD2_MB field.
+#define BR_CMT_CMD2_MB (HW_CMT_CMD2.U)
+#endif
+
+//! @brief Format value for bitfield CMT_CMD2_MB.
+#define BF_CMT_CMD2_MB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CMD2_MB), uint8_t) & BM_CMT_CMD2_MB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MB field to a new value.
+#define BW_CMT_CMD2_MB(v) (HW_CMT_CMD2_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMT_CMD3 - CMT Modulator Data Register Space High
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMT_CMD3 - CMT Modulator Data Register Space High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the space period register
+ * upon the completion of a modulation period.
+ */
+typedef union _hw_cmt_cmd3
+{
+ uint8_t U;
+ struct _hw_cmt_cmd3_bitfields
+ {
+ uint8_t SB : 8; //!< [7:0]
+ } B;
+} hw_cmt_cmd3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMT_CMD3 register
+ */
+//@{
+#define HW_CMT_CMD3_ADDR (REGS_CMT_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMT_CMD3 (*(__IO hw_cmt_cmd3_t *) HW_CMT_CMD3_ADDR)
+#define HW_CMT_CMD3_RD() (HW_CMT_CMD3.U)
+#define HW_CMT_CMD3_WR(v) (HW_CMT_CMD3.U = (v))
+#define HW_CMT_CMD3_SET(v) (HW_CMT_CMD3_WR(HW_CMT_CMD3_RD() | (v)))
+#define HW_CMT_CMD3_CLR(v) (HW_CMT_CMD3_WR(HW_CMT_CMD3_RD() & ~(v)))
+#define HW_CMT_CMD3_TOG(v) (HW_CMT_CMD3_WR(HW_CMT_CMD3_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMT_CMD3 bitfields
+ */
+
+/*!
+ * @name Register CMT_CMD3, field SB[7:0] (RW)
+ *
+ * Controls the upper space periods of the modulator for all modes.
+ */
+//@{
+#define BP_CMT_CMD3_SB (0U) //!< Bit position for CMT_CMD3_SB.
+#define BM_CMT_CMD3_SB (0xFFU) //!< Bit mask for CMT_CMD3_SB.
+#define BS_CMT_CMD3_SB (8U) //!< Bit field size in bits for CMT_CMD3_SB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_CMD3_SB field.
+#define BR_CMT_CMD3_SB (HW_CMT_CMD3.U)
+#endif
+
+//! @brief Format value for bitfield CMT_CMD3_SB.
+#define BF_CMT_CMD3_SB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CMD3_SB), uint8_t) & BM_CMT_CMD3_SB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SB field to a new value.
+#define BW_CMT_CMD3_SB(v) (HW_CMT_CMD3_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMT_CMD4 - CMT Modulator Data Register Space Low
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMT_CMD4 - CMT Modulator Data Register Space Low (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the space period register
+ * upon the completion of a modulation period.
+ */
+typedef union _hw_cmt_cmd4
+{
+ uint8_t U;
+ struct _hw_cmt_cmd4_bitfields
+ {
+ uint8_t SB : 8; //!< [7:0]
+ } B;
+} hw_cmt_cmd4_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMT_CMD4 register
+ */
+//@{
+#define HW_CMT_CMD4_ADDR (REGS_CMT_BASE + 0x9U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMT_CMD4 (*(__IO hw_cmt_cmd4_t *) HW_CMT_CMD4_ADDR)
+#define HW_CMT_CMD4_RD() (HW_CMT_CMD4.U)
+#define HW_CMT_CMD4_WR(v) (HW_CMT_CMD4.U = (v))
+#define HW_CMT_CMD4_SET(v) (HW_CMT_CMD4_WR(HW_CMT_CMD4_RD() | (v)))
+#define HW_CMT_CMD4_CLR(v) (HW_CMT_CMD4_WR(HW_CMT_CMD4_RD() & ~(v)))
+#define HW_CMT_CMD4_TOG(v) (HW_CMT_CMD4_WR(HW_CMT_CMD4_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMT_CMD4 bitfields
+ */
+
+/*!
+ * @name Register CMT_CMD4, field SB[7:0] (RW)
+ *
+ * Controls the lower space periods of the modulator for all modes.
+ */
+//@{
+#define BP_CMT_CMD4_SB (0U) //!< Bit position for CMT_CMD4_SB.
+#define BM_CMT_CMD4_SB (0xFFU) //!< Bit mask for CMT_CMD4_SB.
+#define BS_CMT_CMD4_SB (8U) //!< Bit field size in bits for CMT_CMD4_SB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_CMD4_SB field.
+#define BR_CMT_CMD4_SB (HW_CMT_CMD4.U)
+#endif
+
+//! @brief Format value for bitfield CMT_CMD4_SB.
+#define BF_CMT_CMD4_SB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_CMD4_SB), uint8_t) & BM_CMT_CMD4_SB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SB field to a new value.
+#define BW_CMT_CMD4_SB(v) (HW_CMT_CMD4_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMT_PPS - CMT Primary Prescaler Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMT_PPS - CMT Primary Prescaler Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is used to set the Primary Prescaler Divider field (PPSDIV).
+ */
+typedef union _hw_cmt_pps
+{
+ uint8_t U;
+ struct _hw_cmt_pps_bitfields
+ {
+ uint8_t PPSDIV : 4; //!< [3:0] Primary Prescaler Divider
+ uint8_t RESERVED0 : 4; //!< [7:4]
+ } B;
+} hw_cmt_pps_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMT_PPS register
+ */
+//@{
+#define HW_CMT_PPS_ADDR (REGS_CMT_BASE + 0xAU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMT_PPS (*(__IO hw_cmt_pps_t *) HW_CMT_PPS_ADDR)
+#define HW_CMT_PPS_RD() (HW_CMT_PPS.U)
+#define HW_CMT_PPS_WR(v) (HW_CMT_PPS.U = (v))
+#define HW_CMT_PPS_SET(v) (HW_CMT_PPS_WR(HW_CMT_PPS_RD() | (v)))
+#define HW_CMT_PPS_CLR(v) (HW_CMT_PPS_WR(HW_CMT_PPS_RD() & ~(v)))
+#define HW_CMT_PPS_TOG(v) (HW_CMT_PPS_WR(HW_CMT_PPS_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMT_PPS bitfields
+ */
+
+/*!
+ * @name Register CMT_PPS, field PPSDIV[3:0] (RW)
+ *
+ * Divides the CMT clock to generate the Intermediate Frequency clock enable to
+ * the secondary prescaler.
+ *
+ * Values:
+ * - 0000 - Bus clock * 1
+ * - 0001 - Bus clock * 2
+ * - 0010 - Bus clock * 3
+ * - 0011 - Bus clock * 4
+ * - 0100 - Bus clock * 5
+ * - 0101 - Bus clock * 6
+ * - 0110 - Bus clock * 7
+ * - 0111 - Bus clock * 8
+ * - 1000 - Bus clock * 9
+ * - 1001 - Bus clock * 10
+ * - 1010 - Bus clock * 11
+ * - 1011 - Bus clock * 12
+ * - 1100 - Bus clock * 13
+ * - 1101 - Bus clock * 14
+ * - 1110 - Bus clock * 15
+ * - 1111 - Bus clock * 16
+ */
+//@{
+#define BP_CMT_PPS_PPSDIV (0U) //!< Bit position for CMT_PPS_PPSDIV.
+#define BM_CMT_PPS_PPSDIV (0x0FU) //!< Bit mask for CMT_PPS_PPSDIV.
+#define BS_CMT_PPS_PPSDIV (4U) //!< Bit field size in bits for CMT_PPS_PPSDIV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_PPS_PPSDIV field.
+#define BR_CMT_PPS_PPSDIV (HW_CMT_PPS.B.PPSDIV)
+#endif
+
+//! @brief Format value for bitfield CMT_PPS_PPSDIV.
+#define BF_CMT_PPS_PPSDIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_PPS_PPSDIV), uint8_t) & BM_CMT_PPS_PPSDIV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PPSDIV field to a new value.
+#define BW_CMT_PPS_PPSDIV(v) (HW_CMT_PPS_WR((HW_CMT_PPS_RD() & ~BM_CMT_PPS_PPSDIV) | BF_CMT_PPS_PPSDIV(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CMT_DMA - CMT Direct Memory Access Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CMT_DMA - CMT Direct Memory Access Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is used to enable/disable direct memory access (DMA).
+ */
+typedef union _hw_cmt_dma
+{
+ uint8_t U;
+ struct _hw_cmt_dma_bitfields
+ {
+ uint8_t DMAb : 1; //!< [0] DMA Enable
+ uint8_t RESERVED0 : 7; //!< [7:1]
+ } B;
+} hw_cmt_dma_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CMT_DMA register
+ */
+//@{
+#define HW_CMT_DMA_ADDR (REGS_CMT_BASE + 0xBU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CMT_DMA (*(__IO hw_cmt_dma_t *) HW_CMT_DMA_ADDR)
+#define HW_CMT_DMA_RD() (HW_CMT_DMA.U)
+#define HW_CMT_DMA_WR(v) (HW_CMT_DMA.U = (v))
+#define HW_CMT_DMA_SET(v) (HW_CMT_DMA_WR(HW_CMT_DMA_RD() | (v)))
+#define HW_CMT_DMA_CLR(v) (HW_CMT_DMA_WR(HW_CMT_DMA_RD() & ~(v)))
+#define HW_CMT_DMA_TOG(v) (HW_CMT_DMA_WR(HW_CMT_DMA_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CMT_DMA bitfields
+ */
+
+/*!
+ * @name Register CMT_DMA, field DMA[0] (RW)
+ *
+ * Enables the DMA protocol.
+ *
+ * Values:
+ * - 0 - DMA transfer request and done are disabled.
+ * - 1 - DMA transfer request and done are enabled.
+ */
+//@{
+#define BP_CMT_DMA_DMA (0U) //!< Bit position for CMT_DMA_DMA.
+#define BM_CMT_DMA_DMA (0x01U) //!< Bit mask for CMT_DMA_DMA.
+#define BS_CMT_DMA_DMA (1U) //!< Bit field size in bits for CMT_DMA_DMA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CMT_DMA_DMA field.
+#define BR_CMT_DMA_DMA (BITBAND_ACCESS8(HW_CMT_DMA_ADDR, BP_CMT_DMA_DMA))
+#endif
+
+//! @brief Format value for bitfield CMT_DMA_DMA.
+#define BF_CMT_DMA_DMA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMT_DMA_DMA), uint8_t) & BM_CMT_DMA_DMA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMA field to a new value.
+#define BW_CMT_DMA_DMA(v) (BITBAND_ACCESS8(HW_CMT_DMA_ADDR, BP_CMT_DMA_DMA) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_cmt_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All CMT module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_cmt
+{
+ __IO hw_cmt_cgh1_t CGH1; //!< [0x0] CMT Carrier Generator High Data Register 1
+ __IO hw_cmt_cgl1_t CGL1; //!< [0x1] CMT Carrier Generator Low Data Register 1
+ __IO hw_cmt_cgh2_t CGH2; //!< [0x2] CMT Carrier Generator High Data Register 2
+ __IO hw_cmt_cgl2_t CGL2; //!< [0x3] CMT Carrier Generator Low Data Register 2
+ __IO hw_cmt_oc_t OC; //!< [0x4] CMT Output Control Register
+ __IO hw_cmt_msc_t MSC; //!< [0x5] CMT Modulator Status and Control Register
+ __IO hw_cmt_cmd1_t CMD1; //!< [0x6] CMT Modulator Data Register Mark High
+ __IO hw_cmt_cmd2_t CMD2; //!< [0x7] CMT Modulator Data Register Mark Low
+ __IO hw_cmt_cmd3_t CMD3; //!< [0x8] CMT Modulator Data Register Space High
+ __IO hw_cmt_cmd4_t CMD4; //!< [0x9] CMT Modulator Data Register Space Low
+ __IO hw_cmt_pps_t PPS; //!< [0xA] CMT Primary Prescaler Register
+ __IO hw_cmt_dma_t DMA; //!< [0xB] CMT Direct Memory Access Register
+} hw_cmt_t;
+#pragma pack()
+
+//! @brief Macro to access all CMT registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_CMT</code>.
+#define HW_CMT (*(hw_cmt_t *) REGS_CMT_BASE)
+#endif
+
+#endif // __HW_CMT_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_crc.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,1499 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_CRC_REGISTERS_H__
+#define __HW_CRC_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 CRC
+ *
+ * Cyclic Redundancy Check
+ *
+ * Registers defined in this header file:
+ * - HW_CRC_DATAL - CRC_DATAL register.
+ * - HW_CRC_DATAH - CRC_DATAH register.
+ * - HW_CRC_DATALL - CRC_DATALL register.
+ * - HW_CRC_DATALU - CRC_DATALU register.
+ * - HW_CRC_DATAHL - CRC_DATAHL register.
+ * - HW_CRC_DATAHU - CRC_DATAHU register.
+ * - HW_CRC_DATA - CRC Data register
+ * - HW_CRC_GPOLY - CRC Polynomial register
+ * - HW_CRC_GPOLYL - CRC_GPOLYL register.
+ * - HW_CRC_GPOLYH - CRC_GPOLYH register.
+ * - HW_CRC_GPOLYLL - CRC_GPOLYLL register.
+ * - HW_CRC_GPOLYLU - CRC_GPOLYLU register.
+ * - HW_CRC_GPOLYHL - CRC_GPOLYHL register.
+ * - HW_CRC_GPOLYHU - CRC_GPOLYHU register.
+ * - HW_CRC_CTRL - CRC Control register
+ * - HW_CRC_CTRLHU - CRC_CTRLHU register.
+ *
+ * - hw_crc_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_CRC_BASE
+#define HW_CRC_INSTANCE_COUNT (1U) //!< Number of instances of the CRC module.
+#define REGS_CRC_BASE (0x40032000U) //!< Base address for CRC.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CRC_DATAL - CRC_DATAL register.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_DATAL - CRC_DATAL register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+typedef union _hw_crc_datal
+{
+ uint16_t U;
+ struct _hw_crc_datal_bitfields
+ {
+ uint16_t DATAL : 16; //!< [15:0] DATAL stores the lower 16 bits of
+ //! the 16/32 bit CRC
+ } B;
+} hw_crc_datal_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_DATAL register
+ */
+//@{
+#define HW_CRC_DATAL_ADDR (REGS_CRC_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_DATAL (*(__IO hw_crc_datal_t *) HW_CRC_DATAL_ADDR)
+#define HW_CRC_DATAL_RD() (HW_CRC_DATAL.U)
+#define HW_CRC_DATAL_WR(v) (HW_CRC_DATAL.U = (v))
+#define HW_CRC_DATAL_SET(v) (HW_CRC_DATAL_WR(HW_CRC_DATAL_RD() | (v)))
+#define HW_CRC_DATAL_CLR(v) (HW_CRC_DATAL_WR(HW_CRC_DATAL_RD() & ~(v)))
+#define HW_CRC_DATAL_TOG(v) (HW_CRC_DATAL_WR(HW_CRC_DATAL_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_DATAL bitfields
+ */
+
+/*!
+ * @name Register CRC_DATAL, field DATAL[15:0] (RW)
+ */
+//@{
+#define BP_CRC_DATAL_DATAL (0U) //!< Bit position for CRC_DATAL_DATAL.
+#define BM_CRC_DATAL_DATAL (0xFFFFU) //!< Bit mask for CRC_DATAL_DATAL.
+#define BS_CRC_DATAL_DATAL (16U) //!< Bit field size in bits for CRC_DATAL_DATAL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_DATAL_DATAL field.
+#define BR_CRC_DATAL_DATAL (HW_CRC_DATAL.U)
+#endif
+
+//! @brief Format value for bitfield CRC_DATAL_DATAL.
+#define BF_CRC_DATAL_DATAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_CRC_DATAL_DATAL), uint16_t) & BM_CRC_DATAL_DATAL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATAL field to a new value.
+#define BW_CRC_DATAL_DATAL(v) (HW_CRC_DATAL_WR(v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CRC_DATAH - CRC_DATAH register.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_DATAH - CRC_DATAH register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+typedef union _hw_crc_datah
+{
+ uint16_t U;
+ struct _hw_crc_datah_bitfields
+ {
+ uint16_t DATAH : 16; //!< [15:0] DATAH stores the high 16 bits of the
+ //! 16/32 bit CRC
+ } B;
+} hw_crc_datah_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_DATAH register
+ */
+//@{
+#define HW_CRC_DATAH_ADDR (REGS_CRC_BASE + 0x2U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_DATAH (*(__IO hw_crc_datah_t *) HW_CRC_DATAH_ADDR)
+#define HW_CRC_DATAH_RD() (HW_CRC_DATAH.U)
+#define HW_CRC_DATAH_WR(v) (HW_CRC_DATAH.U = (v))
+#define HW_CRC_DATAH_SET(v) (HW_CRC_DATAH_WR(HW_CRC_DATAH_RD() | (v)))
+#define HW_CRC_DATAH_CLR(v) (HW_CRC_DATAH_WR(HW_CRC_DATAH_RD() & ~(v)))
+#define HW_CRC_DATAH_TOG(v) (HW_CRC_DATAH_WR(HW_CRC_DATAH_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_DATAH bitfields
+ */
+
+/*!
+ * @name Register CRC_DATAH, field DATAH[15:0] (RW)
+ */
+//@{
+#define BP_CRC_DATAH_DATAH (0U) //!< Bit position for CRC_DATAH_DATAH.
+#define BM_CRC_DATAH_DATAH (0xFFFFU) //!< Bit mask for CRC_DATAH_DATAH.
+#define BS_CRC_DATAH_DATAH (16U) //!< Bit field size in bits for CRC_DATAH_DATAH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_DATAH_DATAH field.
+#define BR_CRC_DATAH_DATAH (HW_CRC_DATAH.U)
+#endif
+
+//! @brief Format value for bitfield CRC_DATAH_DATAH.
+#define BF_CRC_DATAH_DATAH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_CRC_DATAH_DATAH), uint16_t) & BM_CRC_DATAH_DATAH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATAH field to a new value.
+#define BW_CRC_DATAH_DATAH(v) (HW_CRC_DATAH_WR(v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CRC_DATALL - CRC_DATALL register.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_DATALL - CRC_DATALL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_crc_datall
+{
+ uint8_t U;
+ struct _hw_crc_datall_bitfields
+ {
+ uint8_t DATALL : 8; //!< [7:0] CRCLL stores the first 8 bits of the
+ //! 32 bit DATA
+ } B;
+} hw_crc_datall_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_DATALL register
+ */
+//@{
+#define HW_CRC_DATALL_ADDR (REGS_CRC_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_DATALL (*(__IO hw_crc_datall_t *) HW_CRC_DATALL_ADDR)
+#define HW_CRC_DATALL_RD() (HW_CRC_DATALL.U)
+#define HW_CRC_DATALL_WR(v) (HW_CRC_DATALL.U = (v))
+#define HW_CRC_DATALL_SET(v) (HW_CRC_DATALL_WR(HW_CRC_DATALL_RD() | (v)))
+#define HW_CRC_DATALL_CLR(v) (HW_CRC_DATALL_WR(HW_CRC_DATALL_RD() & ~(v)))
+#define HW_CRC_DATALL_TOG(v) (HW_CRC_DATALL_WR(HW_CRC_DATALL_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_DATALL bitfields
+ */
+
+/*!
+ * @name Register CRC_DATALL, field DATALL[7:0] (RW)
+ */
+//@{
+#define BP_CRC_DATALL_DATALL (0U) //!< Bit position for CRC_DATALL_DATALL.
+#define BM_CRC_DATALL_DATALL (0xFFU) //!< Bit mask for CRC_DATALL_DATALL.
+#define BS_CRC_DATALL_DATALL (8U) //!< Bit field size in bits for CRC_DATALL_DATALL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_DATALL_DATALL field.
+#define BR_CRC_DATALL_DATALL (HW_CRC_DATALL.U)
+#endif
+
+//! @brief Format value for bitfield CRC_DATALL_DATALL.
+#define BF_CRC_DATALL_DATALL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_DATALL_DATALL), uint8_t) & BM_CRC_DATALL_DATALL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATALL field to a new value.
+#define BW_CRC_DATALL_DATALL(v) (HW_CRC_DATALL_WR(v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CRC_DATALU - CRC_DATALU register.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_DATALU - CRC_DATALU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_crc_datalu
+{
+ uint8_t U;
+ struct _hw_crc_datalu_bitfields
+ {
+ uint8_t DATALU : 8; //!< [7:0] DATALL stores the second 8 bits of the
+ //! 32 bit CRC
+ } B;
+} hw_crc_datalu_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_DATALU register
+ */
+//@{
+#define HW_CRC_DATALU_ADDR (REGS_CRC_BASE + 0x1U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_DATALU (*(__IO hw_crc_datalu_t *) HW_CRC_DATALU_ADDR)
+#define HW_CRC_DATALU_RD() (HW_CRC_DATALU.U)
+#define HW_CRC_DATALU_WR(v) (HW_CRC_DATALU.U = (v))
+#define HW_CRC_DATALU_SET(v) (HW_CRC_DATALU_WR(HW_CRC_DATALU_RD() | (v)))
+#define HW_CRC_DATALU_CLR(v) (HW_CRC_DATALU_WR(HW_CRC_DATALU_RD() & ~(v)))
+#define HW_CRC_DATALU_TOG(v) (HW_CRC_DATALU_WR(HW_CRC_DATALU_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_DATALU bitfields
+ */
+
+/*!
+ * @name Register CRC_DATALU, field DATALU[7:0] (RW)
+ */
+//@{
+#define BP_CRC_DATALU_DATALU (0U) //!< Bit position for CRC_DATALU_DATALU.
+#define BM_CRC_DATALU_DATALU (0xFFU) //!< Bit mask for CRC_DATALU_DATALU.
+#define BS_CRC_DATALU_DATALU (8U) //!< Bit field size in bits for CRC_DATALU_DATALU.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_DATALU_DATALU field.
+#define BR_CRC_DATALU_DATALU (HW_CRC_DATALU.U)
+#endif
+
+//! @brief Format value for bitfield CRC_DATALU_DATALU.
+#define BF_CRC_DATALU_DATALU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_DATALU_DATALU), uint8_t) & BM_CRC_DATALU_DATALU)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATALU field to a new value.
+#define BW_CRC_DATALU_DATALU(v) (HW_CRC_DATALU_WR(v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CRC_DATAHL - CRC_DATAHL register.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_DATAHL - CRC_DATAHL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_crc_datahl
+{
+ uint8_t U;
+ struct _hw_crc_datahl_bitfields
+ {
+ uint8_t DATAHL : 8; //!< [7:0] DATAHL stores the third 8 bits of the
+ //! 32 bit CRC
+ } B;
+} hw_crc_datahl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_DATAHL register
+ */
+//@{
+#define HW_CRC_DATAHL_ADDR (REGS_CRC_BASE + 0x2U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_DATAHL (*(__IO hw_crc_datahl_t *) HW_CRC_DATAHL_ADDR)
+#define HW_CRC_DATAHL_RD() (HW_CRC_DATAHL.U)
+#define HW_CRC_DATAHL_WR(v) (HW_CRC_DATAHL.U = (v))
+#define HW_CRC_DATAHL_SET(v) (HW_CRC_DATAHL_WR(HW_CRC_DATAHL_RD() | (v)))
+#define HW_CRC_DATAHL_CLR(v) (HW_CRC_DATAHL_WR(HW_CRC_DATAHL_RD() & ~(v)))
+#define HW_CRC_DATAHL_TOG(v) (HW_CRC_DATAHL_WR(HW_CRC_DATAHL_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_DATAHL bitfields
+ */
+
+/*!
+ * @name Register CRC_DATAHL, field DATAHL[7:0] (RW)
+ */
+//@{
+#define BP_CRC_DATAHL_DATAHL (0U) //!< Bit position for CRC_DATAHL_DATAHL.
+#define BM_CRC_DATAHL_DATAHL (0xFFU) //!< Bit mask for CRC_DATAHL_DATAHL.
+#define BS_CRC_DATAHL_DATAHL (8U) //!< Bit field size in bits for CRC_DATAHL_DATAHL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_DATAHL_DATAHL field.
+#define BR_CRC_DATAHL_DATAHL (HW_CRC_DATAHL.U)
+#endif
+
+//! @brief Format value for bitfield CRC_DATAHL_DATAHL.
+#define BF_CRC_DATAHL_DATAHL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_DATAHL_DATAHL), uint8_t) & BM_CRC_DATAHL_DATAHL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATAHL field to a new value.
+#define BW_CRC_DATAHL_DATAHL(v) (HW_CRC_DATAHL_WR(v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CRC_DATAHU - CRC_DATAHU register.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_DATAHU - CRC_DATAHU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_crc_datahu
+{
+ uint8_t U;
+ struct _hw_crc_datahu_bitfields
+ {
+ uint8_t DATAHU : 8; //!< [7:0] DATAHU stores the fourth 8 bits of the
+ //! 32 bit CRC
+ } B;
+} hw_crc_datahu_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_DATAHU register
+ */
+//@{
+#define HW_CRC_DATAHU_ADDR (REGS_CRC_BASE + 0x3U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_DATAHU (*(__IO hw_crc_datahu_t *) HW_CRC_DATAHU_ADDR)
+#define HW_CRC_DATAHU_RD() (HW_CRC_DATAHU.U)
+#define HW_CRC_DATAHU_WR(v) (HW_CRC_DATAHU.U = (v))
+#define HW_CRC_DATAHU_SET(v) (HW_CRC_DATAHU_WR(HW_CRC_DATAHU_RD() | (v)))
+#define HW_CRC_DATAHU_CLR(v) (HW_CRC_DATAHU_WR(HW_CRC_DATAHU_RD() & ~(v)))
+#define HW_CRC_DATAHU_TOG(v) (HW_CRC_DATAHU_WR(HW_CRC_DATAHU_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_DATAHU bitfields
+ */
+
+/*!
+ * @name Register CRC_DATAHU, field DATAHU[7:0] (RW)
+ */
+//@{
+#define BP_CRC_DATAHU_DATAHU (0U) //!< Bit position for CRC_DATAHU_DATAHU.
+#define BM_CRC_DATAHU_DATAHU (0xFFU) //!< Bit mask for CRC_DATAHU_DATAHU.
+#define BS_CRC_DATAHU_DATAHU (8U) //!< Bit field size in bits for CRC_DATAHU_DATAHU.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_DATAHU_DATAHU field.
+#define BR_CRC_DATAHU_DATAHU (HW_CRC_DATAHU.U)
+#endif
+
+//! @brief Format value for bitfield CRC_DATAHU_DATAHU.
+#define BF_CRC_DATAHU_DATAHU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_DATAHU_DATAHU), uint8_t) & BM_CRC_DATAHU_DATAHU)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATAHU field to a new value.
+#define BW_CRC_DATAHU_DATAHU(v) (HW_CRC_DATAHU_WR(v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CRC_DATA - CRC Data register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_DATA - CRC Data register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * The CRC Data register contains the value of the seed, data, and checksum.
+ * When CTRL[WAS] is set, any write to the data register is regarded as the seed
+ * value. When CTRL[WAS] is cleared, any write to the data register is regarded as
+ * data for general CRC computation. In 16-bit CRC mode, the HU and HL fields are
+ * not used for programming the seed value, and reads of these fields return an
+ * indeterminate value. In 32-bit CRC mode, all fields are used for programming
+ * the seed value. When programming data values, the values can be written 8 bits,
+ * 16 bits, or 32 bits at a time, provided all bytes are contiguous; with MSB of
+ * data value written first. After all data values are written, the CRC result
+ * can be read from this data register. In 16-bit CRC mode, the CRC result is
+ * available in the LU and LL fields. In 32-bit CRC mode, all fields contain the
+ * result. Reads of this register at any time return the intermediate CRC value,
+ * provided the CRC module is configured.
+ */
+typedef union _hw_crc_data
+{
+ uint32_t U;
+ struct _hw_crc_data_bitfields
+ {
+ uint32_t LL : 8; //!< [7:0] CRC Low Lower Byte
+ uint32_t LU : 8; //!< [15:8] CRC Low Upper Byte
+ uint32_t HL : 8; //!< [23:16] CRC High Lower Byte
+ uint32_t HU : 8; //!< [31:24] CRC High Upper Byte
+ } B;
+} hw_crc_data_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_DATA register
+ */
+//@{
+#define HW_CRC_DATA_ADDR (REGS_CRC_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_DATA (*(__IO hw_crc_data_t *) HW_CRC_DATA_ADDR)
+#define HW_CRC_DATA_RD() (HW_CRC_DATA.U)
+#define HW_CRC_DATA_WR(v) (HW_CRC_DATA.U = (v))
+#define HW_CRC_DATA_SET(v) (HW_CRC_DATA_WR(HW_CRC_DATA_RD() | (v)))
+#define HW_CRC_DATA_CLR(v) (HW_CRC_DATA_WR(HW_CRC_DATA_RD() & ~(v)))
+#define HW_CRC_DATA_TOG(v) (HW_CRC_DATA_WR(HW_CRC_DATA_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_DATA bitfields
+ */
+
+/*!
+ * @name Register CRC_DATA, field LL[7:0] (RW)
+ *
+ * When CTRL[WAS] is 1, values written to this field are part of the seed value.
+ * When CTRL[WAS] is 0, data written to this field is used for CRC checksum
+ * generation.
+ */
+//@{
+#define BP_CRC_DATA_LL (0U) //!< Bit position for CRC_DATA_LL.
+#define BM_CRC_DATA_LL (0x000000FFU) //!< Bit mask for CRC_DATA_LL.
+#define BS_CRC_DATA_LL (8U) //!< Bit field size in bits for CRC_DATA_LL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_DATA_LL field.
+#define BR_CRC_DATA_LL (HW_CRC_DATA.B.LL)
+#endif
+
+//! @brief Format value for bitfield CRC_DATA_LL.
+#define BF_CRC_DATA_LL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_DATA_LL), uint32_t) & BM_CRC_DATA_LL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LL field to a new value.
+#define BW_CRC_DATA_LL(v) (HW_CRC_DATA_WR((HW_CRC_DATA_RD() & ~BM_CRC_DATA_LL) | BF_CRC_DATA_LL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CRC_DATA, field LU[15:8] (RW)
+ *
+ * When CTRL[WAS] is 1, values written to this field are part of the seed value.
+ * When CTRL[WAS] is 0, data written to this field is used for CRC checksum
+ * generation.
+ */
+//@{
+#define BP_CRC_DATA_LU (8U) //!< Bit position for CRC_DATA_LU.
+#define BM_CRC_DATA_LU (0x0000FF00U) //!< Bit mask for CRC_DATA_LU.
+#define BS_CRC_DATA_LU (8U) //!< Bit field size in bits for CRC_DATA_LU.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_DATA_LU field.
+#define BR_CRC_DATA_LU (HW_CRC_DATA.B.LU)
+#endif
+
+//! @brief Format value for bitfield CRC_DATA_LU.
+#define BF_CRC_DATA_LU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_DATA_LU), uint32_t) & BM_CRC_DATA_LU)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LU field to a new value.
+#define BW_CRC_DATA_LU(v) (HW_CRC_DATA_WR((HW_CRC_DATA_RD() & ~BM_CRC_DATA_LU) | BF_CRC_DATA_LU(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CRC_DATA, field HL[23:16] (RW)
+ *
+ * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming
+ * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this
+ * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data
+ * written to this field is used for CRC checksum generation in both 16-bit and
+ * 32-bit CRC modes.
+ */
+//@{
+#define BP_CRC_DATA_HL (16U) //!< Bit position for CRC_DATA_HL.
+#define BM_CRC_DATA_HL (0x00FF0000U) //!< Bit mask for CRC_DATA_HL.
+#define BS_CRC_DATA_HL (8U) //!< Bit field size in bits for CRC_DATA_HL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_DATA_HL field.
+#define BR_CRC_DATA_HL (HW_CRC_DATA.B.HL)
+#endif
+
+//! @brief Format value for bitfield CRC_DATA_HL.
+#define BF_CRC_DATA_HL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_DATA_HL), uint32_t) & BM_CRC_DATA_HL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HL field to a new value.
+#define BW_CRC_DATA_HL(v) (HW_CRC_DATA_WR((HW_CRC_DATA_RD() & ~BM_CRC_DATA_HL) | BF_CRC_DATA_HL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CRC_DATA, field HU[31:24] (RW)
+ *
+ * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming
+ * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this
+ * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data
+ * written to this field is used for CRC checksum generation in both 16-bit and
+ * 32-bit CRC modes.
+ */
+//@{
+#define BP_CRC_DATA_HU (24U) //!< Bit position for CRC_DATA_HU.
+#define BM_CRC_DATA_HU (0xFF000000U) //!< Bit mask for CRC_DATA_HU.
+#define BS_CRC_DATA_HU (8U) //!< Bit field size in bits for CRC_DATA_HU.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_DATA_HU field.
+#define BR_CRC_DATA_HU (HW_CRC_DATA.B.HU)
+#endif
+
+//! @brief Format value for bitfield CRC_DATA_HU.
+#define BF_CRC_DATA_HU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_DATA_HU), uint32_t) & BM_CRC_DATA_HU)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HU field to a new value.
+#define BW_CRC_DATA_HU(v) (HW_CRC_DATA_WR((HW_CRC_DATA_RD() & ~BM_CRC_DATA_HU) | BF_CRC_DATA_HU(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CRC_GPOLY - CRC Polynomial register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_GPOLY - CRC Polynomial register (RW)
+ *
+ * Reset value: 0x00001021U
+ *
+ * This register contains the value of the polynomial for the CRC calculation.
+ * The HIGH field contains the upper 16 bits of the CRC polynomial, which are used
+ * only in 32-bit CRC mode. Writes to the HIGH field are ignored in 16-bit CRC
+ * mode. The LOW field contains the lower 16 bits of the CRC polynomial, which are
+ * used in both 16- and 32-bit CRC modes.
+ */
+typedef union _hw_crc_gpoly
+{
+ uint32_t U;
+ struct _hw_crc_gpoly_bitfields
+ {
+ uint32_t LOW : 16; //!< [15:0] Low Polynominal Half-word
+ uint32_t HIGH : 16; //!< [31:16] High Polynominal Half-word
+ } B;
+} hw_crc_gpoly_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_GPOLY register
+ */
+//@{
+#define HW_CRC_GPOLY_ADDR (REGS_CRC_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_GPOLY (*(__IO hw_crc_gpoly_t *) HW_CRC_GPOLY_ADDR)
+#define HW_CRC_GPOLY_RD() (HW_CRC_GPOLY.U)
+#define HW_CRC_GPOLY_WR(v) (HW_CRC_GPOLY.U = (v))
+#define HW_CRC_GPOLY_SET(v) (HW_CRC_GPOLY_WR(HW_CRC_GPOLY_RD() | (v)))
+#define HW_CRC_GPOLY_CLR(v) (HW_CRC_GPOLY_WR(HW_CRC_GPOLY_RD() & ~(v)))
+#define HW_CRC_GPOLY_TOG(v) (HW_CRC_GPOLY_WR(HW_CRC_GPOLY_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_GPOLY bitfields
+ */
+
+/*!
+ * @name Register CRC_GPOLY, field LOW[15:0] (RW)
+ *
+ * Writable and readable in both 32-bit and 16-bit CRC modes.
+ */
+//@{
+#define BP_CRC_GPOLY_LOW (0U) //!< Bit position for CRC_GPOLY_LOW.
+#define BM_CRC_GPOLY_LOW (0x0000FFFFU) //!< Bit mask for CRC_GPOLY_LOW.
+#define BS_CRC_GPOLY_LOW (16U) //!< Bit field size in bits for CRC_GPOLY_LOW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_GPOLY_LOW field.
+#define BR_CRC_GPOLY_LOW (HW_CRC_GPOLY.B.LOW)
+#endif
+
+//! @brief Format value for bitfield CRC_GPOLY_LOW.
+#define BF_CRC_GPOLY_LOW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_GPOLY_LOW), uint32_t) & BM_CRC_GPOLY_LOW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LOW field to a new value.
+#define BW_CRC_GPOLY_LOW(v) (HW_CRC_GPOLY_WR((HW_CRC_GPOLY_RD() & ~BM_CRC_GPOLY_LOW) | BF_CRC_GPOLY_LOW(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CRC_GPOLY, field HIGH[31:16] (RW)
+ *
+ * Writable and readable in 32-bit CRC mode (CTRL[TCRC] is 1). This field is not
+ * writable in 16-bit CRC mode (CTRL[TCRC] is 0).
+ */
+//@{
+#define BP_CRC_GPOLY_HIGH (16U) //!< Bit position for CRC_GPOLY_HIGH.
+#define BM_CRC_GPOLY_HIGH (0xFFFF0000U) //!< Bit mask for CRC_GPOLY_HIGH.
+#define BS_CRC_GPOLY_HIGH (16U) //!< Bit field size in bits for CRC_GPOLY_HIGH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_GPOLY_HIGH field.
+#define BR_CRC_GPOLY_HIGH (HW_CRC_GPOLY.B.HIGH)
+#endif
+
+//! @brief Format value for bitfield CRC_GPOLY_HIGH.
+#define BF_CRC_GPOLY_HIGH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_GPOLY_HIGH), uint32_t) & BM_CRC_GPOLY_HIGH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HIGH field to a new value.
+#define BW_CRC_GPOLY_HIGH(v) (HW_CRC_GPOLY_WR((HW_CRC_GPOLY_RD() & ~BM_CRC_GPOLY_HIGH) | BF_CRC_GPOLY_HIGH(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CRC_GPOLYL - CRC_GPOLYL register.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_GPOLYL - CRC_GPOLYL register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+typedef union _hw_crc_gpolyl
+{
+ uint16_t U;
+ struct _hw_crc_gpolyl_bitfields
+ {
+ uint16_t GPOLYL : 16; //!< [15:0] POLYL stores the lower 16 bits of
+ //! the 16/32 bit CRC polynomial value
+ } B;
+} hw_crc_gpolyl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_GPOLYL register
+ */
+//@{
+#define HW_CRC_GPOLYL_ADDR (REGS_CRC_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_GPOLYL (*(__IO hw_crc_gpolyl_t *) HW_CRC_GPOLYL_ADDR)
+#define HW_CRC_GPOLYL_RD() (HW_CRC_GPOLYL.U)
+#define HW_CRC_GPOLYL_WR(v) (HW_CRC_GPOLYL.U = (v))
+#define HW_CRC_GPOLYL_SET(v) (HW_CRC_GPOLYL_WR(HW_CRC_GPOLYL_RD() | (v)))
+#define HW_CRC_GPOLYL_CLR(v) (HW_CRC_GPOLYL_WR(HW_CRC_GPOLYL_RD() & ~(v)))
+#define HW_CRC_GPOLYL_TOG(v) (HW_CRC_GPOLYL_WR(HW_CRC_GPOLYL_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_GPOLYL bitfields
+ */
+
+/*!
+ * @name Register CRC_GPOLYL, field GPOLYL[15:0] (RW)
+ */
+//@{
+#define BP_CRC_GPOLYL_GPOLYL (0U) //!< Bit position for CRC_GPOLYL_GPOLYL.
+#define BM_CRC_GPOLYL_GPOLYL (0xFFFFU) //!< Bit mask for CRC_GPOLYL_GPOLYL.
+#define BS_CRC_GPOLYL_GPOLYL (16U) //!< Bit field size in bits for CRC_GPOLYL_GPOLYL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_GPOLYL_GPOLYL field.
+#define BR_CRC_GPOLYL_GPOLYL (HW_CRC_GPOLYL.U)
+#endif
+
+//! @brief Format value for bitfield CRC_GPOLYL_GPOLYL.
+#define BF_CRC_GPOLYL_GPOLYL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_CRC_GPOLYL_GPOLYL), uint16_t) & BM_CRC_GPOLYL_GPOLYL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GPOLYL field to a new value.
+#define BW_CRC_GPOLYL_GPOLYL(v) (HW_CRC_GPOLYL_WR(v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CRC_GPOLYH - CRC_GPOLYH register.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_GPOLYH - CRC_GPOLYH register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+typedef union _hw_crc_gpolyh
+{
+ uint16_t U;
+ struct _hw_crc_gpolyh_bitfields
+ {
+ uint16_t GPOLYH : 16; //!< [15:0] POLYH stores the high 16 bits of
+ //! the 16/32 bit CRC polynomial value
+ } B;
+} hw_crc_gpolyh_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_GPOLYH register
+ */
+//@{
+#define HW_CRC_GPOLYH_ADDR (REGS_CRC_BASE + 0x6U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_GPOLYH (*(__IO hw_crc_gpolyh_t *) HW_CRC_GPOLYH_ADDR)
+#define HW_CRC_GPOLYH_RD() (HW_CRC_GPOLYH.U)
+#define HW_CRC_GPOLYH_WR(v) (HW_CRC_GPOLYH.U = (v))
+#define HW_CRC_GPOLYH_SET(v) (HW_CRC_GPOLYH_WR(HW_CRC_GPOLYH_RD() | (v)))
+#define HW_CRC_GPOLYH_CLR(v) (HW_CRC_GPOLYH_WR(HW_CRC_GPOLYH_RD() & ~(v)))
+#define HW_CRC_GPOLYH_TOG(v) (HW_CRC_GPOLYH_WR(HW_CRC_GPOLYH_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_GPOLYH bitfields
+ */
+
+/*!
+ * @name Register CRC_GPOLYH, field GPOLYH[15:0] (RW)
+ */
+//@{
+#define BP_CRC_GPOLYH_GPOLYH (0U) //!< Bit position for CRC_GPOLYH_GPOLYH.
+#define BM_CRC_GPOLYH_GPOLYH (0xFFFFU) //!< Bit mask for CRC_GPOLYH_GPOLYH.
+#define BS_CRC_GPOLYH_GPOLYH (16U) //!< Bit field size in bits for CRC_GPOLYH_GPOLYH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_GPOLYH_GPOLYH field.
+#define BR_CRC_GPOLYH_GPOLYH (HW_CRC_GPOLYH.U)
+#endif
+
+//! @brief Format value for bitfield CRC_GPOLYH_GPOLYH.
+#define BF_CRC_GPOLYH_GPOLYH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_CRC_GPOLYH_GPOLYH), uint16_t) & BM_CRC_GPOLYH_GPOLYH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GPOLYH field to a new value.
+#define BW_CRC_GPOLYH_GPOLYH(v) (HW_CRC_GPOLYH_WR(v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CRC_GPOLYLL - CRC_GPOLYLL register.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_GPOLYLL - CRC_GPOLYLL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_crc_gpolyll
+{
+ uint8_t U;
+ struct _hw_crc_gpolyll_bitfields
+ {
+ uint8_t GPOLYLL : 8; //!< [7:0] POLYLL stores the first 8 bits of the
+ //! 32 bit CRC
+ } B;
+} hw_crc_gpolyll_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_GPOLYLL register
+ */
+//@{
+#define HW_CRC_GPOLYLL_ADDR (REGS_CRC_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_GPOLYLL (*(__IO hw_crc_gpolyll_t *) HW_CRC_GPOLYLL_ADDR)
+#define HW_CRC_GPOLYLL_RD() (HW_CRC_GPOLYLL.U)
+#define HW_CRC_GPOLYLL_WR(v) (HW_CRC_GPOLYLL.U = (v))
+#define HW_CRC_GPOLYLL_SET(v) (HW_CRC_GPOLYLL_WR(HW_CRC_GPOLYLL_RD() | (v)))
+#define HW_CRC_GPOLYLL_CLR(v) (HW_CRC_GPOLYLL_WR(HW_CRC_GPOLYLL_RD() & ~(v)))
+#define HW_CRC_GPOLYLL_TOG(v) (HW_CRC_GPOLYLL_WR(HW_CRC_GPOLYLL_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_GPOLYLL bitfields
+ */
+
+/*!
+ * @name Register CRC_GPOLYLL, field GPOLYLL[7:0] (RW)
+ */
+//@{
+#define BP_CRC_GPOLYLL_GPOLYLL (0U) //!< Bit position for CRC_GPOLYLL_GPOLYLL.
+#define BM_CRC_GPOLYLL_GPOLYLL (0xFFU) //!< Bit mask for CRC_GPOLYLL_GPOLYLL.
+#define BS_CRC_GPOLYLL_GPOLYLL (8U) //!< Bit field size in bits for CRC_GPOLYLL_GPOLYLL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_GPOLYLL_GPOLYLL field.
+#define BR_CRC_GPOLYLL_GPOLYLL (HW_CRC_GPOLYLL.U)
+#endif
+
+//! @brief Format value for bitfield CRC_GPOLYLL_GPOLYLL.
+#define BF_CRC_GPOLYLL_GPOLYLL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_GPOLYLL_GPOLYLL), uint8_t) & BM_CRC_GPOLYLL_GPOLYLL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GPOLYLL field to a new value.
+#define BW_CRC_GPOLYLL_GPOLYLL(v) (HW_CRC_GPOLYLL_WR(v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CRC_GPOLYLU - CRC_GPOLYLU register.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_GPOLYLU - CRC_GPOLYLU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_crc_gpolylu
+{
+ uint8_t U;
+ struct _hw_crc_gpolylu_bitfields
+ {
+ uint8_t GPOLYLU : 8; //!< [7:0] POLYLL stores the second 8 bits of
+ //! the 32 bit CRC
+ } B;
+} hw_crc_gpolylu_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_GPOLYLU register
+ */
+//@{
+#define HW_CRC_GPOLYLU_ADDR (REGS_CRC_BASE + 0x5U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_GPOLYLU (*(__IO hw_crc_gpolylu_t *) HW_CRC_GPOLYLU_ADDR)
+#define HW_CRC_GPOLYLU_RD() (HW_CRC_GPOLYLU.U)
+#define HW_CRC_GPOLYLU_WR(v) (HW_CRC_GPOLYLU.U = (v))
+#define HW_CRC_GPOLYLU_SET(v) (HW_CRC_GPOLYLU_WR(HW_CRC_GPOLYLU_RD() | (v)))
+#define HW_CRC_GPOLYLU_CLR(v) (HW_CRC_GPOLYLU_WR(HW_CRC_GPOLYLU_RD() & ~(v)))
+#define HW_CRC_GPOLYLU_TOG(v) (HW_CRC_GPOLYLU_WR(HW_CRC_GPOLYLU_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_GPOLYLU bitfields
+ */
+
+/*!
+ * @name Register CRC_GPOLYLU, field GPOLYLU[7:0] (RW)
+ */
+//@{
+#define BP_CRC_GPOLYLU_GPOLYLU (0U) //!< Bit position for CRC_GPOLYLU_GPOLYLU.
+#define BM_CRC_GPOLYLU_GPOLYLU (0xFFU) //!< Bit mask for CRC_GPOLYLU_GPOLYLU.
+#define BS_CRC_GPOLYLU_GPOLYLU (8U) //!< Bit field size in bits for CRC_GPOLYLU_GPOLYLU.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_GPOLYLU_GPOLYLU field.
+#define BR_CRC_GPOLYLU_GPOLYLU (HW_CRC_GPOLYLU.U)
+#endif
+
+//! @brief Format value for bitfield CRC_GPOLYLU_GPOLYLU.
+#define BF_CRC_GPOLYLU_GPOLYLU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_GPOLYLU_GPOLYLU), uint8_t) & BM_CRC_GPOLYLU_GPOLYLU)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GPOLYLU field to a new value.
+#define BW_CRC_GPOLYLU_GPOLYLU(v) (HW_CRC_GPOLYLU_WR(v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CRC_GPOLYHL - CRC_GPOLYHL register.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_GPOLYHL - CRC_GPOLYHL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_crc_gpolyhl
+{
+ uint8_t U;
+ struct _hw_crc_gpolyhl_bitfields
+ {
+ uint8_t GPOLYHL : 8; //!< [7:0] POLYHL stores the third 8 bits of the
+ //! 32 bit CRC
+ } B;
+} hw_crc_gpolyhl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_GPOLYHL register
+ */
+//@{
+#define HW_CRC_GPOLYHL_ADDR (REGS_CRC_BASE + 0x6U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_GPOLYHL (*(__IO hw_crc_gpolyhl_t *) HW_CRC_GPOLYHL_ADDR)
+#define HW_CRC_GPOLYHL_RD() (HW_CRC_GPOLYHL.U)
+#define HW_CRC_GPOLYHL_WR(v) (HW_CRC_GPOLYHL.U = (v))
+#define HW_CRC_GPOLYHL_SET(v) (HW_CRC_GPOLYHL_WR(HW_CRC_GPOLYHL_RD() | (v)))
+#define HW_CRC_GPOLYHL_CLR(v) (HW_CRC_GPOLYHL_WR(HW_CRC_GPOLYHL_RD() & ~(v)))
+#define HW_CRC_GPOLYHL_TOG(v) (HW_CRC_GPOLYHL_WR(HW_CRC_GPOLYHL_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_GPOLYHL bitfields
+ */
+
+/*!
+ * @name Register CRC_GPOLYHL, field GPOLYHL[7:0] (RW)
+ */
+//@{
+#define BP_CRC_GPOLYHL_GPOLYHL (0U) //!< Bit position for CRC_GPOLYHL_GPOLYHL.
+#define BM_CRC_GPOLYHL_GPOLYHL (0xFFU) //!< Bit mask for CRC_GPOLYHL_GPOLYHL.
+#define BS_CRC_GPOLYHL_GPOLYHL (8U) //!< Bit field size in bits for CRC_GPOLYHL_GPOLYHL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_GPOLYHL_GPOLYHL field.
+#define BR_CRC_GPOLYHL_GPOLYHL (HW_CRC_GPOLYHL.U)
+#endif
+
+//! @brief Format value for bitfield CRC_GPOLYHL_GPOLYHL.
+#define BF_CRC_GPOLYHL_GPOLYHL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_GPOLYHL_GPOLYHL), uint8_t) & BM_CRC_GPOLYHL_GPOLYHL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GPOLYHL field to a new value.
+#define BW_CRC_GPOLYHL_GPOLYHL(v) (HW_CRC_GPOLYHL_WR(v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CRC_GPOLYHU - CRC_GPOLYHU register.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_GPOLYHU - CRC_GPOLYHU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_crc_gpolyhu
+{
+ uint8_t U;
+ struct _hw_crc_gpolyhu_bitfields
+ {
+ uint8_t GPOLYHU : 8; //!< [7:0] POLYHU stores the fourth 8 bits of
+ //! the 32 bit CRC
+ } B;
+} hw_crc_gpolyhu_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_GPOLYHU register
+ */
+//@{
+#define HW_CRC_GPOLYHU_ADDR (REGS_CRC_BASE + 0x7U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_GPOLYHU (*(__IO hw_crc_gpolyhu_t *) HW_CRC_GPOLYHU_ADDR)
+#define HW_CRC_GPOLYHU_RD() (HW_CRC_GPOLYHU.U)
+#define HW_CRC_GPOLYHU_WR(v) (HW_CRC_GPOLYHU.U = (v))
+#define HW_CRC_GPOLYHU_SET(v) (HW_CRC_GPOLYHU_WR(HW_CRC_GPOLYHU_RD() | (v)))
+#define HW_CRC_GPOLYHU_CLR(v) (HW_CRC_GPOLYHU_WR(HW_CRC_GPOLYHU_RD() & ~(v)))
+#define HW_CRC_GPOLYHU_TOG(v) (HW_CRC_GPOLYHU_WR(HW_CRC_GPOLYHU_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_GPOLYHU bitfields
+ */
+
+/*!
+ * @name Register CRC_GPOLYHU, field GPOLYHU[7:0] (RW)
+ */
+//@{
+#define BP_CRC_GPOLYHU_GPOLYHU (0U) //!< Bit position for CRC_GPOLYHU_GPOLYHU.
+#define BM_CRC_GPOLYHU_GPOLYHU (0xFFU) //!< Bit mask for CRC_GPOLYHU_GPOLYHU.
+#define BS_CRC_GPOLYHU_GPOLYHU (8U) //!< Bit field size in bits for CRC_GPOLYHU_GPOLYHU.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_GPOLYHU_GPOLYHU field.
+#define BR_CRC_GPOLYHU_GPOLYHU (HW_CRC_GPOLYHU.U)
+#endif
+
+//! @brief Format value for bitfield CRC_GPOLYHU_GPOLYHU.
+#define BF_CRC_GPOLYHU_GPOLYHU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_GPOLYHU_GPOLYHU), uint8_t) & BM_CRC_GPOLYHU_GPOLYHU)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GPOLYHU field to a new value.
+#define BW_CRC_GPOLYHU_GPOLYHU(v) (HW_CRC_GPOLYHU_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_CRC_CTRL - CRC Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_CTRL - CRC Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register controls the configuration and working of the CRC module.
+ * Appropriate bits must be set before starting a new CRC calculation. A new CRC
+ * calculation is initialized by asserting CTRL[WAS] and then writing the seed into
+ * the CRC data register.
+ */
+typedef union _hw_crc_ctrl
+{
+ uint32_t U;
+ struct _hw_crc_ctrl_bitfields
+ {
+ uint32_t RESERVED0 : 24; //!< [23:0]
+ uint32_t TCRC : 1; //!< [24]
+ uint32_t WAS : 1; //!< [25] Write CRC Data Register As Seed
+ uint32_t FXOR : 1; //!< [26] Complement Read Of CRC Data Register
+ uint32_t RESERVED1 : 1; //!< [27]
+ uint32_t TOTR : 2; //!< [29:28] Type Of Transpose For Read
+ uint32_t TOT : 2; //!< [31:30] Type Of Transpose For Writes
+ } B;
+} hw_crc_ctrl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_CTRL register
+ */
+//@{
+#define HW_CRC_CTRL_ADDR (REGS_CRC_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_CTRL (*(__IO hw_crc_ctrl_t *) HW_CRC_CTRL_ADDR)
+#define HW_CRC_CTRL_RD() (HW_CRC_CTRL.U)
+#define HW_CRC_CTRL_WR(v) (HW_CRC_CTRL.U = (v))
+#define HW_CRC_CTRL_SET(v) (HW_CRC_CTRL_WR(HW_CRC_CTRL_RD() | (v)))
+#define HW_CRC_CTRL_CLR(v) (HW_CRC_CTRL_WR(HW_CRC_CTRL_RD() & ~(v)))
+#define HW_CRC_CTRL_TOG(v) (HW_CRC_CTRL_WR(HW_CRC_CTRL_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_CTRL bitfields
+ */
+
+/*!
+ * @name Register CRC_CTRL, field TCRC[24] (RW)
+ *
+ * Width of CRC protocol.
+ *
+ * Values:
+ * - 0 - 16-bit CRC protocol.
+ * - 1 - 32-bit CRC protocol.
+ */
+//@{
+#define BP_CRC_CTRL_TCRC (24U) //!< Bit position for CRC_CTRL_TCRC.
+#define BM_CRC_CTRL_TCRC (0x01000000U) //!< Bit mask for CRC_CTRL_TCRC.
+#define BS_CRC_CTRL_TCRC (1U) //!< Bit field size in bits for CRC_CTRL_TCRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_CTRL_TCRC field.
+#define BR_CRC_CTRL_TCRC (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR, BP_CRC_CTRL_TCRC))
+#endif
+
+//! @brief Format value for bitfield CRC_CTRL_TCRC.
+#define BF_CRC_CTRL_TCRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_CTRL_TCRC), uint32_t) & BM_CRC_CTRL_TCRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCRC field to a new value.
+#define BW_CRC_CTRL_TCRC(v) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR, BP_CRC_CTRL_TCRC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CRC_CTRL, field WAS[25] (RW)
+ *
+ * When asserted, a value written to the CRC data register is considered a seed
+ * value. When deasserted, a value written to the CRC data register is taken as
+ * data for CRC computation.
+ *
+ * Values:
+ * - 0 - Writes to the CRC data register are data values.
+ * - 1 - Writes to the CRC data register are seed values.
+ */
+//@{
+#define BP_CRC_CTRL_WAS (25U) //!< Bit position for CRC_CTRL_WAS.
+#define BM_CRC_CTRL_WAS (0x02000000U) //!< Bit mask for CRC_CTRL_WAS.
+#define BS_CRC_CTRL_WAS (1U) //!< Bit field size in bits for CRC_CTRL_WAS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_CTRL_WAS field.
+#define BR_CRC_CTRL_WAS (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR, BP_CRC_CTRL_WAS))
+#endif
+
+//! @brief Format value for bitfield CRC_CTRL_WAS.
+#define BF_CRC_CTRL_WAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_CTRL_WAS), uint32_t) & BM_CRC_CTRL_WAS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WAS field to a new value.
+#define BW_CRC_CTRL_WAS(v) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR, BP_CRC_CTRL_WAS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CRC_CTRL, field FXOR[26] (RW)
+ *
+ * Some CRC protocols require the final checksum to be XORed with 0xFFFFFFFF or
+ * 0xFFFF. Asserting this bit enables on the fly complementing of read data.
+ *
+ * Values:
+ * - 0 - No XOR on reading.
+ * - 1 - Invert or complement the read value of the CRC Data register.
+ */
+//@{
+#define BP_CRC_CTRL_FXOR (26U) //!< Bit position for CRC_CTRL_FXOR.
+#define BM_CRC_CTRL_FXOR (0x04000000U) //!< Bit mask for CRC_CTRL_FXOR.
+#define BS_CRC_CTRL_FXOR (1U) //!< Bit field size in bits for CRC_CTRL_FXOR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_CTRL_FXOR field.
+#define BR_CRC_CTRL_FXOR (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR, BP_CRC_CTRL_FXOR))
+#endif
+
+//! @brief Format value for bitfield CRC_CTRL_FXOR.
+#define BF_CRC_CTRL_FXOR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_CTRL_FXOR), uint32_t) & BM_CRC_CTRL_FXOR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FXOR field to a new value.
+#define BW_CRC_CTRL_FXOR(v) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR, BP_CRC_CTRL_FXOR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CRC_CTRL, field TOTR[29:28] (RW)
+ *
+ * Identifies the transpose configuration of the value read from the CRC Data
+ * register. See the description of the transpose feature for the available
+ * transpose options.
+ *
+ * Values:
+ * - 00 - No transposition.
+ * - 01 - Bits in bytes are transposed; bytes are not transposed.
+ * - 10 - Both bits in bytes and bytes are transposed.
+ * - 11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+//@{
+#define BP_CRC_CTRL_TOTR (28U) //!< Bit position for CRC_CTRL_TOTR.
+#define BM_CRC_CTRL_TOTR (0x30000000U) //!< Bit mask for CRC_CTRL_TOTR.
+#define BS_CRC_CTRL_TOTR (2U) //!< Bit field size in bits for CRC_CTRL_TOTR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_CTRL_TOTR field.
+#define BR_CRC_CTRL_TOTR (HW_CRC_CTRL.B.TOTR)
+#endif
+
+//! @brief Format value for bitfield CRC_CTRL_TOTR.
+#define BF_CRC_CTRL_TOTR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_CTRL_TOTR), uint32_t) & BM_CRC_CTRL_TOTR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TOTR field to a new value.
+#define BW_CRC_CTRL_TOTR(v) (HW_CRC_CTRL_WR((HW_CRC_CTRL_RD() & ~BM_CRC_CTRL_TOTR) | BF_CRC_CTRL_TOTR(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CRC_CTRL, field TOT[31:30] (RW)
+ *
+ * Defines the transpose configuration of the data written to the CRC data
+ * register. See the description of the transpose feature for the available transpose
+ * options.
+ *
+ * Values:
+ * - 00 - No transposition.
+ * - 01 - Bits in bytes are transposed; bytes are not transposed.
+ * - 10 - Both bits in bytes and bytes are transposed.
+ * - 11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+//@{
+#define BP_CRC_CTRL_TOT (30U) //!< Bit position for CRC_CTRL_TOT.
+#define BM_CRC_CTRL_TOT (0xC0000000U) //!< Bit mask for CRC_CTRL_TOT.
+#define BS_CRC_CTRL_TOT (2U) //!< Bit field size in bits for CRC_CTRL_TOT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_CTRL_TOT field.
+#define BR_CRC_CTRL_TOT (HW_CRC_CTRL.B.TOT)
+#endif
+
+//! @brief Format value for bitfield CRC_CTRL_TOT.
+#define BF_CRC_CTRL_TOT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_CRC_CTRL_TOT), uint32_t) & BM_CRC_CTRL_TOT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TOT field to a new value.
+#define BW_CRC_CTRL_TOT(v) (HW_CRC_CTRL_WR((HW_CRC_CTRL_RD() & ~BM_CRC_CTRL_TOT) | BF_CRC_CTRL_TOT(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_CRC_CTRLHU - CRC_CTRLHU register.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_CRC_CTRLHU - CRC_CTRLHU register. (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_crc_ctrlhu
+{
+ uint8_t U;
+ struct _hw_crc_ctrlhu_bitfields
+ {
+ uint8_t TCRC : 1; //!< [0]
+ uint8_t WAS : 1; //!< [1]
+ uint8_t FXOR : 1; //!< [2]
+ uint8_t RESERVED0 : 1; //!< [3]
+ uint8_t TOTR : 2; //!< [5:4]
+ uint8_t TOT : 2; //!< [7:6]
+ } B;
+} hw_crc_ctrlhu_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire CRC_CTRLHU register
+ */
+//@{
+#define HW_CRC_CTRLHU_ADDR (REGS_CRC_BASE + 0xBU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_CRC_CTRLHU (*(__IO hw_crc_ctrlhu_t *) HW_CRC_CTRLHU_ADDR)
+#define HW_CRC_CTRLHU_RD() (HW_CRC_CTRLHU.U)
+#define HW_CRC_CTRLHU_WR(v) (HW_CRC_CTRLHU.U = (v))
+#define HW_CRC_CTRLHU_SET(v) (HW_CRC_CTRLHU_WR(HW_CRC_CTRLHU_RD() | (v)))
+#define HW_CRC_CTRLHU_CLR(v) (HW_CRC_CTRLHU_WR(HW_CRC_CTRLHU_RD() & ~(v)))
+#define HW_CRC_CTRLHU_TOG(v) (HW_CRC_CTRLHU_WR(HW_CRC_CTRLHU_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual CRC_CTRLHU bitfields
+ */
+
+/*!
+ * @name Register CRC_CTRLHU, field TCRC[0] (RW)
+ *
+ * Values:
+ * - 0 - 16-bit CRC protocol.
+ * - 1 - 32-bit CRC protocol.
+ */
+//@{
+#define BP_CRC_CTRLHU_TCRC (0U) //!< Bit position for CRC_CTRLHU_TCRC.
+#define BM_CRC_CTRLHU_TCRC (0x01U) //!< Bit mask for CRC_CTRLHU_TCRC.
+#define BS_CRC_CTRLHU_TCRC (1U) //!< Bit field size in bits for CRC_CTRLHU_TCRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_CTRLHU_TCRC field.
+#define BR_CRC_CTRLHU_TCRC (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR, BP_CRC_CTRLHU_TCRC))
+#endif
+
+//! @brief Format value for bitfield CRC_CTRLHU_TCRC.
+#define BF_CRC_CTRLHU_TCRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_CTRLHU_TCRC), uint8_t) & BM_CRC_CTRLHU_TCRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCRC field to a new value.
+#define BW_CRC_CTRLHU_TCRC(v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR, BP_CRC_CTRLHU_TCRC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CRC_CTRLHU, field WAS[1] (RW)
+ *
+ * Values:
+ * - 0 - Writes to CRC data register are data values.
+ * - 1 - Writes to CRC data reguster are seed values.
+ */
+//@{
+#define BP_CRC_CTRLHU_WAS (1U) //!< Bit position for CRC_CTRLHU_WAS.
+#define BM_CRC_CTRLHU_WAS (0x02U) //!< Bit mask for CRC_CTRLHU_WAS.
+#define BS_CRC_CTRLHU_WAS (1U) //!< Bit field size in bits for CRC_CTRLHU_WAS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_CTRLHU_WAS field.
+#define BR_CRC_CTRLHU_WAS (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR, BP_CRC_CTRLHU_WAS))
+#endif
+
+//! @brief Format value for bitfield CRC_CTRLHU_WAS.
+#define BF_CRC_CTRLHU_WAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_CTRLHU_WAS), uint8_t) & BM_CRC_CTRLHU_WAS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WAS field to a new value.
+#define BW_CRC_CTRLHU_WAS(v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR, BP_CRC_CTRLHU_WAS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CRC_CTRLHU, field FXOR[2] (RW)
+ *
+ * Values:
+ * - 0 - No XOR on reading.
+ * - 1 - Invert or complement the read value of CRC data register.
+ */
+//@{
+#define BP_CRC_CTRLHU_FXOR (2U) //!< Bit position for CRC_CTRLHU_FXOR.
+#define BM_CRC_CTRLHU_FXOR (0x04U) //!< Bit mask for CRC_CTRLHU_FXOR.
+#define BS_CRC_CTRLHU_FXOR (1U) //!< Bit field size in bits for CRC_CTRLHU_FXOR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_CTRLHU_FXOR field.
+#define BR_CRC_CTRLHU_FXOR (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR, BP_CRC_CTRLHU_FXOR))
+#endif
+
+//! @brief Format value for bitfield CRC_CTRLHU_FXOR.
+#define BF_CRC_CTRLHU_FXOR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_CTRLHU_FXOR), uint8_t) & BM_CRC_CTRLHU_FXOR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FXOR field to a new value.
+#define BW_CRC_CTRLHU_FXOR(v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR, BP_CRC_CTRLHU_FXOR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register CRC_CTRLHU, field TOTR[5:4] (RW)
+ *
+ * Values:
+ * - 00 - No Transposition.
+ * - 01 - Bits in bytes are transposed, bytes are not transposed.
+ * - 10 - Both bits in bytes and bytes are transposed.
+ * - 11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+//@{
+#define BP_CRC_CTRLHU_TOTR (4U) //!< Bit position for CRC_CTRLHU_TOTR.
+#define BM_CRC_CTRLHU_TOTR (0x30U) //!< Bit mask for CRC_CTRLHU_TOTR.
+#define BS_CRC_CTRLHU_TOTR (2U) //!< Bit field size in bits for CRC_CTRLHU_TOTR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_CTRLHU_TOTR field.
+#define BR_CRC_CTRLHU_TOTR (HW_CRC_CTRLHU.B.TOTR)
+#endif
+
+//! @brief Format value for bitfield CRC_CTRLHU_TOTR.
+#define BF_CRC_CTRLHU_TOTR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_CTRLHU_TOTR), uint8_t) & BM_CRC_CTRLHU_TOTR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TOTR field to a new value.
+#define BW_CRC_CTRLHU_TOTR(v) (HW_CRC_CTRLHU_WR((HW_CRC_CTRLHU_RD() & ~BM_CRC_CTRLHU_TOTR) | BF_CRC_CTRLHU_TOTR(v)))
+#endif
+//@}
+
+/*!
+ * @name Register CRC_CTRLHU, field TOT[7:6] (RW)
+ *
+ * Values:
+ * - 00 - No Transposition.
+ * - 01 - Bits in bytes are transposed, bytes are not transposed.
+ * - 10 - Both bits in bytes and bytes are transposed.
+ * - 11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+//@{
+#define BP_CRC_CTRLHU_TOT (6U) //!< Bit position for CRC_CTRLHU_TOT.
+#define BM_CRC_CTRLHU_TOT (0xC0U) //!< Bit mask for CRC_CTRLHU_TOT.
+#define BS_CRC_CTRLHU_TOT (2U) //!< Bit field size in bits for CRC_CTRLHU_TOT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the CRC_CTRLHU_TOT field.
+#define BR_CRC_CTRLHU_TOT (HW_CRC_CTRLHU.B.TOT)
+#endif
+
+//! @brief Format value for bitfield CRC_CTRLHU_TOT.
+#define BF_CRC_CTRLHU_TOT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CRC_CTRLHU_TOT), uint8_t) & BM_CRC_CTRLHU_TOT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TOT field to a new value.
+#define BW_CRC_CTRLHU_TOT(v) (HW_CRC_CTRLHU_WR((HW_CRC_CTRLHU_RD() & ~BM_CRC_CTRLHU_TOT) | BF_CRC_CTRLHU_TOT(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_crc_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All CRC module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_crc
+{
+ union {
+ struct {
+ __IO hw_crc_datal_t DATAL; //!< [0x0] CRC_DATAL register.
+ __IO hw_crc_datah_t DATAH; //!< [0x2] CRC_DATAH register.
+ } ACCESS16BIT;
+ struct {
+ __IO hw_crc_datall_t DATALL; //!< [0x0] CRC_DATALL register.
+ __IO hw_crc_datalu_t DATALU; //!< [0x1] CRC_DATALU register.
+ __IO hw_crc_datahl_t DATAHL; //!< [0x2] CRC_DATAHL register.
+ __IO hw_crc_datahu_t DATAHU; //!< [0x3] CRC_DATAHU register.
+ } ACCESS8BIT;
+ __IO hw_crc_data_t DATA; //!< [0x0] CRC Data register
+ };
+ union {
+ __IO hw_crc_gpoly_t GPOLY; //!< [0x4] CRC Polynomial register
+ struct {
+ __IO hw_crc_gpolyl_t GPOLYL; //!< [0x4] CRC_GPOLYL register.
+ __IO hw_crc_gpolyh_t GPOLYH; //!< [0x6] CRC_GPOLYH register.
+ } GPOLY_ACCESS16BIT;
+ struct {
+ __IO hw_crc_gpolyll_t GPOLYLL; //!< [0x4] CRC_GPOLYLL register.
+ __IO hw_crc_gpolylu_t GPOLYLU; //!< [0x5] CRC_GPOLYLU register.
+ __IO hw_crc_gpolyhl_t GPOLYHL; //!< [0x6] CRC_GPOLYHL register.
+ __IO hw_crc_gpolyhu_t GPOLYHU; //!< [0x7] CRC_GPOLYHU register.
+ } GPOLY_ACCESS8BIT;
+ };
+ union {
+ __IO hw_crc_ctrl_t CTRL; //!< [0x8] CRC Control register
+ struct {
+ uint8_t _reserved0[3];
+ __IO hw_crc_ctrlhu_t CTRLHU; //!< [0xB] CRC_CTRLHU register.
+ } CTRL_ACCESS8BIT;
+ };
+} hw_crc_t;
+#pragma pack()
+
+//! @brief Macro to access all CRC registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_CRC</code>.
+#define HW_CRC (*(hw_crc_t *) REGS_CRC_BASE)
+#endif
+
+#endif // __HW_CRC_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_dac.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,879 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_DAC_REGISTERS_H__
+#define __HW_DAC_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 DAC
+ *
+ * 12-Bit Digital-to-Analog Converter
+ *
+ * Registers defined in this header file:
+ * - HW_DAC_DATnL - DAC Data Low Register
+ * - HW_DAC_DATnH - DAC Data High Register
+ * - HW_DAC_SR - DAC Status Register
+ * - HW_DAC_C0 - DAC Control Register
+ * - HW_DAC_C1 - DAC Control Register 1
+ * - HW_DAC_C2 - DAC Control Register 2
+ *
+ * - hw_dac_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_DAC_BASE
+#define HW_DAC_INSTANCE_COUNT (2U) //!< Number of instances of the DAC module.
+#define HW_DAC0 (0U) //!< Instance number for DAC0.
+#define HW_DAC1 (1U) //!< Instance number for DAC1.
+#define REGS_DAC0_BASE (0x400CC000U) //!< Base address for DAC0.
+#define REGS_DAC1_BASE (0x400CD000U) //!< Base address for DAC1.
+
+//! @brief Table of base addresses for DAC instances.
+static const uint32_t __g_regs_DAC_base_addresses[] = {
+ REGS_DAC0_BASE,
+ REGS_DAC1_BASE,
+ };
+
+//! @brief Get the base address of DAC by instance number.
+//! @param x DAC instance number, from 0 through 1.
+#define REGS_DAC_BASE(x) (__g_regs_DAC_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of DAC.
+#define REGS_DAC_INSTANCE(b) ((b) == REGS_DAC0_BASE ? HW_DAC0 : (b) == REGS_DAC1_BASE ? HW_DAC1 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DAC_DATnL - DAC Data Low Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DAC_DATnL - DAC Data Low Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_dac_datnl
+{
+ uint8_t U;
+ struct _hw_dac_datnl_bitfields
+ {
+ uint8_t DATA0 : 8; //!< [7:0]
+ } B;
+} hw_dac_datnl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DAC_DATnL register
+ */
+//@{
+#define HW_DAC_DATnL_COUNT (16U)
+
+#define HW_DAC_DATnL_ADDR(x, n) (REGS_DAC_BASE(x) + 0x0U + (0x2U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DAC_DATnL(x, n) (*(__IO hw_dac_datnl_t *) HW_DAC_DATnL_ADDR(x, n))
+#define HW_DAC_DATnL_RD(x, n) (HW_DAC_DATnL(x, n).U)
+#define HW_DAC_DATnL_WR(x, n, v) (HW_DAC_DATnL(x, n).U = (v))
+#define HW_DAC_DATnL_SET(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) | (v)))
+#define HW_DAC_DATnL_CLR(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) & ~(v)))
+#define HW_DAC_DATnL_TOG(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DAC_DATnL bitfields
+ */
+
+/*!
+ * @name Register DAC_DATnL, field DATA0[7:0] (RW)
+ *
+ * When the DAC buffer is not enabled, DATA[11:0] controls the output voltage
+ * based on the following formula: V out = V in * (1 + DACDAT0[11:0])/4096 When the
+ * DAC buffer is enabled, DATA is mapped to the 16-word buffer.
+ */
+//@{
+#define BP_DAC_DATnL_DATA0 (0U) //!< Bit position for DAC_DATnL_DATA0.
+#define BM_DAC_DATnL_DATA0 (0xFFU) //!< Bit mask for DAC_DATnL_DATA0.
+#define BS_DAC_DATnL_DATA0 (8U) //!< Bit field size in bits for DAC_DATnL_DATA0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_DATnL_DATA0 field.
+#define BR_DAC_DATnL_DATA0(x, n) (HW_DAC_DATnL(x, n).U)
+#endif
+
+//! @brief Format value for bitfield DAC_DATnL_DATA0.
+#define BF_DAC_DATnL_DATA0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_DATnL_DATA0), uint8_t) & BM_DAC_DATnL_DATA0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATA0 field to a new value.
+#define BW_DAC_DATnL_DATA0(x, n, v) (HW_DAC_DATnL_WR(x, n, v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DAC_DATnH - DAC Data High Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DAC_DATnH - DAC Data High Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_dac_datnh
+{
+ uint8_t U;
+ struct _hw_dac_datnh_bitfields
+ {
+ uint8_t DATA1 : 4; //!< [3:0]
+ uint8_t RESERVED0 : 4; //!< [7:4]
+ } B;
+} hw_dac_datnh_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DAC_DATnH register
+ */
+//@{
+#define HW_DAC_DATnH_COUNT (16U)
+
+#define HW_DAC_DATnH_ADDR(x, n) (REGS_DAC_BASE(x) + 0x1U + (0x2U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DAC_DATnH(x, n) (*(__IO hw_dac_datnh_t *) HW_DAC_DATnH_ADDR(x, n))
+#define HW_DAC_DATnH_RD(x, n) (HW_DAC_DATnH(x, n).U)
+#define HW_DAC_DATnH_WR(x, n, v) (HW_DAC_DATnH(x, n).U = (v))
+#define HW_DAC_DATnH_SET(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) | (v)))
+#define HW_DAC_DATnH_CLR(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) & ~(v)))
+#define HW_DAC_DATnH_TOG(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DAC_DATnH bitfields
+ */
+
+/*!
+ * @name Register DAC_DATnH, field DATA1[3:0] (RW)
+ *
+ * When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage
+ * based on the following formula. V out = V in * (1 + DACDAT0[11:0])/4096 When the
+ * DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer.
+ */
+//@{
+#define BP_DAC_DATnH_DATA1 (0U) //!< Bit position for DAC_DATnH_DATA1.
+#define BM_DAC_DATnH_DATA1 (0x0FU) //!< Bit mask for DAC_DATnH_DATA1.
+#define BS_DAC_DATnH_DATA1 (4U) //!< Bit field size in bits for DAC_DATnH_DATA1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_DATnH_DATA1 field.
+#define BR_DAC_DATnH_DATA1(x, n) (HW_DAC_DATnH(x, n).B.DATA1)
+#endif
+
+//! @brief Format value for bitfield DAC_DATnH_DATA1.
+#define BF_DAC_DATnH_DATA1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_DATnH_DATA1), uint8_t) & BM_DAC_DATnH_DATA1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATA1 field to a new value.
+#define BW_DAC_DATnH_DATA1(x, n, v) (HW_DAC_DATnH_WR(x, n, (HW_DAC_DATnH_RD(x, n) & ~BM_DAC_DATnH_DATA1) | BF_DAC_DATnH_DATA1(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DAC_SR - DAC Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DAC_SR - DAC Status Register (RW)
+ *
+ * Reset value: 0x02U
+ *
+ * If DMA is enabled, the flags can be cleared automatically by DMA when the DMA
+ * request is done. Writing 0 to a field clears it whereas writing 1 has no
+ * effect. After reset, DACBFRPTF is set and can be cleared by software, if needed.
+ * The flags are set only when the data buffer status is changed. Do not use
+ * 32/16-bit accesses to this register.
+ */
+typedef union _hw_dac_sr
+{
+ uint8_t U;
+ struct _hw_dac_sr_bitfields
+ {
+ uint8_t DACBFRPBF : 1; //!< [0] DAC Buffer Read Pointer Bottom
+ //! Position Flag
+ uint8_t DACBFRPTF : 1; //!< [1] DAC Buffer Read Pointer Top Position
+ //! Flag
+ uint8_t DACBFWMF : 1; //!< [2] DAC Buffer Watermark Flag
+ uint8_t RESERVED0 : 5; //!< [7:3]
+ } B;
+} hw_dac_sr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DAC_SR register
+ */
+//@{
+#define HW_DAC_SR_ADDR(x) (REGS_DAC_BASE(x) + 0x20U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DAC_SR(x) (*(__IO hw_dac_sr_t *) HW_DAC_SR_ADDR(x))
+#define HW_DAC_SR_RD(x) (HW_DAC_SR(x).U)
+#define HW_DAC_SR_WR(x, v) (HW_DAC_SR(x).U = (v))
+#define HW_DAC_SR_SET(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) | (v)))
+#define HW_DAC_SR_CLR(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) & ~(v)))
+#define HW_DAC_SR_TOG(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DAC_SR bitfields
+ */
+
+/*!
+ * @name Register DAC_SR, field DACBFRPBF[0] (RW)
+ *
+ * Values:
+ * - 0 - The DAC buffer read pointer is not equal to C2[DACBFUP].
+ * - 1 - The DAC buffer read pointer is equal to C2[DACBFUP].
+ */
+//@{
+#define BP_DAC_SR_DACBFRPBF (0U) //!< Bit position for DAC_SR_DACBFRPBF.
+#define BM_DAC_SR_DACBFRPBF (0x01U) //!< Bit mask for DAC_SR_DACBFRPBF.
+#define BS_DAC_SR_DACBFRPBF (1U) //!< Bit field size in bits for DAC_SR_DACBFRPBF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_SR_DACBFRPBF field.
+#define BR_DAC_SR_DACBFRPBF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF))
+#endif
+
+//! @brief Format value for bitfield DAC_SR_DACBFRPBF.
+#define BF_DAC_SR_DACBFRPBF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_SR_DACBFRPBF), uint8_t) & BM_DAC_SR_DACBFRPBF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACBFRPBF field to a new value.
+#define BW_DAC_SR_DACBFRPBF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DAC_SR, field DACBFRPTF[1] (RW)
+ *
+ * Values:
+ * - 0 - The DAC buffer read pointer is not zero.
+ * - 1 - The DAC buffer read pointer is zero.
+ */
+//@{
+#define BP_DAC_SR_DACBFRPTF (1U) //!< Bit position for DAC_SR_DACBFRPTF.
+#define BM_DAC_SR_DACBFRPTF (0x02U) //!< Bit mask for DAC_SR_DACBFRPTF.
+#define BS_DAC_SR_DACBFRPTF (1U) //!< Bit field size in bits for DAC_SR_DACBFRPTF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_SR_DACBFRPTF field.
+#define BR_DAC_SR_DACBFRPTF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF))
+#endif
+
+//! @brief Format value for bitfield DAC_SR_DACBFRPTF.
+#define BF_DAC_SR_DACBFRPTF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_SR_DACBFRPTF), uint8_t) & BM_DAC_SR_DACBFRPTF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACBFRPTF field to a new value.
+#define BW_DAC_SR_DACBFRPTF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DAC_SR, field DACBFWMF[2] (RW)
+ *
+ * Values:
+ * - 0 - The DAC buffer read pointer has not reached the watermark level.
+ * - 1 - The DAC buffer read pointer has reached the watermark level.
+ */
+//@{
+#define BP_DAC_SR_DACBFWMF (2U) //!< Bit position for DAC_SR_DACBFWMF.
+#define BM_DAC_SR_DACBFWMF (0x04U) //!< Bit mask for DAC_SR_DACBFWMF.
+#define BS_DAC_SR_DACBFWMF (1U) //!< Bit field size in bits for DAC_SR_DACBFWMF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_SR_DACBFWMF field.
+#define BR_DAC_SR_DACBFWMF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF))
+#endif
+
+//! @brief Format value for bitfield DAC_SR_DACBFWMF.
+#define BF_DAC_SR_DACBFWMF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_SR_DACBFWMF), uint8_t) & BM_DAC_SR_DACBFWMF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACBFWMF field to a new value.
+#define BW_DAC_SR_DACBFWMF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DAC_C0 - DAC Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DAC_C0 - DAC Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Do not use 32- or 16-bit accesses to this register.
+ */
+typedef union _hw_dac_c0
+{
+ uint8_t U;
+ struct _hw_dac_c0_bitfields
+ {
+ uint8_t DACBBIEN : 1; //!< [0] DAC Buffer Read Pointer Bottom Flag
+ //! Interrupt Enable
+ uint8_t DACBTIEN : 1; //!< [1] DAC Buffer Read Pointer Top Flag
+ //! Interrupt Enable
+ uint8_t DACBWIEN : 1; //!< [2] DAC Buffer Watermark Interrupt Enable
+ uint8_t LPEN : 1; //!< [3] DAC Low Power Control
+ uint8_t DACSWTRG : 1; //!< [4] DAC Software Trigger
+ uint8_t DACTRGSEL : 1; //!< [5] DAC Trigger Select
+ uint8_t DACRFS : 1; //!< [6] DAC Reference Select
+ uint8_t DACEN : 1; //!< [7] DAC Enable
+ } B;
+} hw_dac_c0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DAC_C0 register
+ */
+//@{
+#define HW_DAC_C0_ADDR(x) (REGS_DAC_BASE(x) + 0x21U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DAC_C0(x) (*(__IO hw_dac_c0_t *) HW_DAC_C0_ADDR(x))
+#define HW_DAC_C0_RD(x) (HW_DAC_C0(x).U)
+#define HW_DAC_C0_WR(x, v) (HW_DAC_C0(x).U = (v))
+#define HW_DAC_C0_SET(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) | (v)))
+#define HW_DAC_C0_CLR(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) & ~(v)))
+#define HW_DAC_C0_TOG(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DAC_C0 bitfields
+ */
+
+/*!
+ * @name Register DAC_C0, field DACBBIEN[0] (RW)
+ *
+ * Values:
+ * - 0 - The DAC buffer read pointer bottom flag interrupt is disabled.
+ * - 1 - The DAC buffer read pointer bottom flag interrupt is enabled.
+ */
+//@{
+#define BP_DAC_C0_DACBBIEN (0U) //!< Bit position for DAC_C0_DACBBIEN.
+#define BM_DAC_C0_DACBBIEN (0x01U) //!< Bit mask for DAC_C0_DACBBIEN.
+#define BS_DAC_C0_DACBBIEN (1U) //!< Bit field size in bits for DAC_C0_DACBBIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_C0_DACBBIEN field.
+#define BR_DAC_C0_DACBBIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN))
+#endif
+
+//! @brief Format value for bitfield DAC_C0_DACBBIEN.
+#define BF_DAC_C0_DACBBIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACBBIEN), uint8_t) & BM_DAC_C0_DACBBIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACBBIEN field to a new value.
+#define BW_DAC_C0_DACBBIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DAC_C0, field DACBTIEN[1] (RW)
+ *
+ * Values:
+ * - 0 - The DAC buffer read pointer top flag interrupt is disabled.
+ * - 1 - The DAC buffer read pointer top flag interrupt is enabled.
+ */
+//@{
+#define BP_DAC_C0_DACBTIEN (1U) //!< Bit position for DAC_C0_DACBTIEN.
+#define BM_DAC_C0_DACBTIEN (0x02U) //!< Bit mask for DAC_C0_DACBTIEN.
+#define BS_DAC_C0_DACBTIEN (1U) //!< Bit field size in bits for DAC_C0_DACBTIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_C0_DACBTIEN field.
+#define BR_DAC_C0_DACBTIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN))
+#endif
+
+//! @brief Format value for bitfield DAC_C0_DACBTIEN.
+#define BF_DAC_C0_DACBTIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACBTIEN), uint8_t) & BM_DAC_C0_DACBTIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACBTIEN field to a new value.
+#define BW_DAC_C0_DACBTIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DAC_C0, field DACBWIEN[2] (RW)
+ *
+ * Values:
+ * - 0 - The DAC buffer watermark interrupt is disabled.
+ * - 1 - The DAC buffer watermark interrupt is enabled.
+ */
+//@{
+#define BP_DAC_C0_DACBWIEN (2U) //!< Bit position for DAC_C0_DACBWIEN.
+#define BM_DAC_C0_DACBWIEN (0x04U) //!< Bit mask for DAC_C0_DACBWIEN.
+#define BS_DAC_C0_DACBWIEN (1U) //!< Bit field size in bits for DAC_C0_DACBWIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_C0_DACBWIEN field.
+#define BR_DAC_C0_DACBWIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN))
+#endif
+
+//! @brief Format value for bitfield DAC_C0_DACBWIEN.
+#define BF_DAC_C0_DACBWIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACBWIEN), uint8_t) & BM_DAC_C0_DACBWIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACBWIEN field to a new value.
+#define BW_DAC_C0_DACBWIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DAC_C0, field LPEN[3] (RW)
+ *
+ * See the 12-bit DAC electrical characteristics of the device data sheet for
+ * details on the impact of the modes below.
+ *
+ * Values:
+ * - 0 - High-Power mode
+ * - 1 - Low-Power mode
+ */
+//@{
+#define BP_DAC_C0_LPEN (3U) //!< Bit position for DAC_C0_LPEN.
+#define BM_DAC_C0_LPEN (0x08U) //!< Bit mask for DAC_C0_LPEN.
+#define BS_DAC_C0_LPEN (1U) //!< Bit field size in bits for DAC_C0_LPEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_C0_LPEN field.
+#define BR_DAC_C0_LPEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN))
+#endif
+
+//! @brief Format value for bitfield DAC_C0_LPEN.
+#define BF_DAC_C0_LPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_LPEN), uint8_t) & BM_DAC_C0_LPEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LPEN field to a new value.
+#define BW_DAC_C0_LPEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DAC_C0, field DACSWTRG[4] (WORZ)
+ *
+ * Active high. This is a write-only field, which always reads 0. If DAC
+ * software trigger is selected and buffer is enabled, writing 1 to this field will
+ * advance the buffer read pointer once.
+ *
+ * Values:
+ * - 0 - The DAC soft trigger is not valid.
+ * - 1 - The DAC soft trigger is valid.
+ */
+//@{
+#define BP_DAC_C0_DACSWTRG (4U) //!< Bit position for DAC_C0_DACSWTRG.
+#define BM_DAC_C0_DACSWTRG (0x10U) //!< Bit mask for DAC_C0_DACSWTRG.
+#define BS_DAC_C0_DACSWTRG (1U) //!< Bit field size in bits for DAC_C0_DACSWTRG.
+
+//! @brief Format value for bitfield DAC_C0_DACSWTRG.
+#define BF_DAC_C0_DACSWTRG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACSWTRG), uint8_t) & BM_DAC_C0_DACSWTRG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACSWTRG field to a new value.
+#define BW_DAC_C0_DACSWTRG(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACSWTRG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DAC_C0, field DACTRGSEL[5] (RW)
+ *
+ * Values:
+ * - 0 - The DAC hardware trigger is selected.
+ * - 1 - The DAC software trigger is selected.
+ */
+//@{
+#define BP_DAC_C0_DACTRGSEL (5U) //!< Bit position for DAC_C0_DACTRGSEL.
+#define BM_DAC_C0_DACTRGSEL (0x20U) //!< Bit mask for DAC_C0_DACTRGSEL.
+#define BS_DAC_C0_DACTRGSEL (1U) //!< Bit field size in bits for DAC_C0_DACTRGSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_C0_DACTRGSEL field.
+#define BR_DAC_C0_DACTRGSEL(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL))
+#endif
+
+//! @brief Format value for bitfield DAC_C0_DACTRGSEL.
+#define BF_DAC_C0_DACTRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACTRGSEL), uint8_t) & BM_DAC_C0_DACTRGSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACTRGSEL field to a new value.
+#define BW_DAC_C0_DACTRGSEL(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DAC_C0, field DACRFS[6] (RW)
+ *
+ * Values:
+ * - 0 - The DAC selects DACREF_1 as the reference voltage.
+ * - 1 - The DAC selects DACREF_2 as the reference voltage.
+ */
+//@{
+#define BP_DAC_C0_DACRFS (6U) //!< Bit position for DAC_C0_DACRFS.
+#define BM_DAC_C0_DACRFS (0x40U) //!< Bit mask for DAC_C0_DACRFS.
+#define BS_DAC_C0_DACRFS (1U) //!< Bit field size in bits for DAC_C0_DACRFS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_C0_DACRFS field.
+#define BR_DAC_C0_DACRFS(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS))
+#endif
+
+//! @brief Format value for bitfield DAC_C0_DACRFS.
+#define BF_DAC_C0_DACRFS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACRFS), uint8_t) & BM_DAC_C0_DACRFS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACRFS field to a new value.
+#define BW_DAC_C0_DACRFS(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DAC_C0, field DACEN[7] (RW)
+ *
+ * Starts the Programmable Reference Generator operation.
+ *
+ * Values:
+ * - 0 - The DAC system is disabled.
+ * - 1 - The DAC system is enabled.
+ */
+//@{
+#define BP_DAC_C0_DACEN (7U) //!< Bit position for DAC_C0_DACEN.
+#define BM_DAC_C0_DACEN (0x80U) //!< Bit mask for DAC_C0_DACEN.
+#define BS_DAC_C0_DACEN (1U) //!< Bit field size in bits for DAC_C0_DACEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_C0_DACEN field.
+#define BR_DAC_C0_DACEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN))
+#endif
+
+//! @brief Format value for bitfield DAC_C0_DACEN.
+#define BF_DAC_C0_DACEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C0_DACEN), uint8_t) & BM_DAC_C0_DACEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACEN field to a new value.
+#define BW_DAC_C0_DACEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DAC_C1 - DAC Control Register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DAC_C1 - DAC Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Do not use 32- or 16-bit accesses to this register.
+ */
+typedef union _hw_dac_c1
+{
+ uint8_t U;
+ struct _hw_dac_c1_bitfields
+ {
+ uint8_t DACBFEN : 1; //!< [0] DAC Buffer Enable
+ uint8_t DACBFMD : 2; //!< [2:1] DAC Buffer Work Mode Select
+ uint8_t DACBFWM : 2; //!< [4:3] DAC Buffer Watermark Select
+ uint8_t RESERVED0 : 2; //!< [6:5]
+ uint8_t DMAEN : 1; //!< [7] DMA Enable Select
+ } B;
+} hw_dac_c1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DAC_C1 register
+ */
+//@{
+#define HW_DAC_C1_ADDR(x) (REGS_DAC_BASE(x) + 0x22U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DAC_C1(x) (*(__IO hw_dac_c1_t *) HW_DAC_C1_ADDR(x))
+#define HW_DAC_C1_RD(x) (HW_DAC_C1(x).U)
+#define HW_DAC_C1_WR(x, v) (HW_DAC_C1(x).U = (v))
+#define HW_DAC_C1_SET(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) | (v)))
+#define HW_DAC_C1_CLR(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) & ~(v)))
+#define HW_DAC_C1_TOG(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DAC_C1 bitfields
+ */
+
+/*!
+ * @name Register DAC_C1, field DACBFEN[0] (RW)
+ *
+ * Values:
+ * - 0 - Buffer read pointer is disabled. The converted data is always the first
+ * word of the buffer.
+ * - 1 - Buffer read pointer is enabled. The converted data is the word that the
+ * read pointer points to. It means converted data can be from any word of
+ * the buffer.
+ */
+//@{
+#define BP_DAC_C1_DACBFEN (0U) //!< Bit position for DAC_C1_DACBFEN.
+#define BM_DAC_C1_DACBFEN (0x01U) //!< Bit mask for DAC_C1_DACBFEN.
+#define BS_DAC_C1_DACBFEN (1U) //!< Bit field size in bits for DAC_C1_DACBFEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_C1_DACBFEN field.
+#define BR_DAC_C1_DACBFEN(x) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN))
+#endif
+
+//! @brief Format value for bitfield DAC_C1_DACBFEN.
+#define BF_DAC_C1_DACBFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C1_DACBFEN), uint8_t) & BM_DAC_C1_DACBFEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACBFEN field to a new value.
+#define BW_DAC_C1_DACBFEN(x, v) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DAC_C1, field DACBFMD[2:1] (RW)
+ *
+ * Values:
+ * - 00 - Normal mode
+ * - 01 - Swing mode
+ * - 10 - One-Time Scan mode
+ * - 11 - Reserved
+ */
+//@{
+#define BP_DAC_C1_DACBFMD (1U) //!< Bit position for DAC_C1_DACBFMD.
+#define BM_DAC_C1_DACBFMD (0x06U) //!< Bit mask for DAC_C1_DACBFMD.
+#define BS_DAC_C1_DACBFMD (2U) //!< Bit field size in bits for DAC_C1_DACBFMD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_C1_DACBFMD field.
+#define BR_DAC_C1_DACBFMD(x) (HW_DAC_C1(x).B.DACBFMD)
+#endif
+
+//! @brief Format value for bitfield DAC_C1_DACBFMD.
+#define BF_DAC_C1_DACBFMD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C1_DACBFMD), uint8_t) & BM_DAC_C1_DACBFMD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACBFMD field to a new value.
+#define BW_DAC_C1_DACBFMD(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFMD) | BF_DAC_C1_DACBFMD(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DAC_C1, field DACBFWM[4:3] (RW)
+ *
+ * Controls when SR[DACBFWMF] is set. When the DAC buffer read pointer reaches
+ * the word defined by this field, which is 1-4 words away from the upper limit
+ * (DACBUP), SR[DACBFWMF] will be set. This allows user configuration of the
+ * watermark interrupt.
+ *
+ * Values:
+ * - 00 - 1 word
+ * - 01 - 2 words
+ * - 10 - 3 words
+ * - 11 - 4 words
+ */
+//@{
+#define BP_DAC_C1_DACBFWM (3U) //!< Bit position for DAC_C1_DACBFWM.
+#define BM_DAC_C1_DACBFWM (0x18U) //!< Bit mask for DAC_C1_DACBFWM.
+#define BS_DAC_C1_DACBFWM (2U) //!< Bit field size in bits for DAC_C1_DACBFWM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_C1_DACBFWM field.
+#define BR_DAC_C1_DACBFWM(x) (HW_DAC_C1(x).B.DACBFWM)
+#endif
+
+//! @brief Format value for bitfield DAC_C1_DACBFWM.
+#define BF_DAC_C1_DACBFWM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C1_DACBFWM), uint8_t) & BM_DAC_C1_DACBFWM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACBFWM field to a new value.
+#define BW_DAC_C1_DACBFWM(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFWM) | BF_DAC_C1_DACBFWM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DAC_C1, field DMAEN[7] (RW)
+ *
+ * Values:
+ * - 0 - DMA is disabled.
+ * - 1 - DMA is enabled. When DMA is enabled, the DMA request will be generated
+ * by original interrupts. The interrupts will not be presented on this
+ * module at the same time.
+ */
+//@{
+#define BP_DAC_C1_DMAEN (7U) //!< Bit position for DAC_C1_DMAEN.
+#define BM_DAC_C1_DMAEN (0x80U) //!< Bit mask for DAC_C1_DMAEN.
+#define BS_DAC_C1_DMAEN (1U) //!< Bit field size in bits for DAC_C1_DMAEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_C1_DMAEN field.
+#define BR_DAC_C1_DMAEN(x) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN))
+#endif
+
+//! @brief Format value for bitfield DAC_C1_DMAEN.
+#define BF_DAC_C1_DMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C1_DMAEN), uint8_t) & BM_DAC_C1_DMAEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMAEN field to a new value.
+#define BW_DAC_C1_DMAEN(x, v) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DAC_C2 - DAC Control Register 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DAC_C2 - DAC Control Register 2 (RW)
+ *
+ * Reset value: 0x0FU
+ */
+typedef union _hw_dac_c2
+{
+ uint8_t U;
+ struct _hw_dac_c2_bitfields
+ {
+ uint8_t DACBFUP : 4; //!< [3:0] DAC Buffer Upper Limit
+ uint8_t DACBFRP : 4; //!< [7:4] DAC Buffer Read Pointer
+ } B;
+} hw_dac_c2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DAC_C2 register
+ */
+//@{
+#define HW_DAC_C2_ADDR(x) (REGS_DAC_BASE(x) + 0x23U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DAC_C2(x) (*(__IO hw_dac_c2_t *) HW_DAC_C2_ADDR(x))
+#define HW_DAC_C2_RD(x) (HW_DAC_C2(x).U)
+#define HW_DAC_C2_WR(x, v) (HW_DAC_C2(x).U = (v))
+#define HW_DAC_C2_SET(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) | (v)))
+#define HW_DAC_C2_CLR(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) & ~(v)))
+#define HW_DAC_C2_TOG(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DAC_C2 bitfields
+ */
+
+/*!
+ * @name Register DAC_C2, field DACBFUP[3:0] (RW)
+ *
+ * Selects the upper limit of the DAC buffer. The buffer read pointer cannot
+ * exceed it.
+ */
+//@{
+#define BP_DAC_C2_DACBFUP (0U) //!< Bit position for DAC_C2_DACBFUP.
+#define BM_DAC_C2_DACBFUP (0x0FU) //!< Bit mask for DAC_C2_DACBFUP.
+#define BS_DAC_C2_DACBFUP (4U) //!< Bit field size in bits for DAC_C2_DACBFUP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_C2_DACBFUP field.
+#define BR_DAC_C2_DACBFUP(x) (HW_DAC_C2(x).B.DACBFUP)
+#endif
+
+//! @brief Format value for bitfield DAC_C2_DACBFUP.
+#define BF_DAC_C2_DACBFUP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C2_DACBFUP), uint8_t) & BM_DAC_C2_DACBFUP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACBFUP field to a new value.
+#define BW_DAC_C2_DACBFUP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFUP) | BF_DAC_C2_DACBFUP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DAC_C2, field DACBFRP[7:4] (RW)
+ *
+ * Keeps the current value of the buffer read pointer.
+ */
+//@{
+#define BP_DAC_C2_DACBFRP (4U) //!< Bit position for DAC_C2_DACBFRP.
+#define BM_DAC_C2_DACBFRP (0xF0U) //!< Bit mask for DAC_C2_DACBFRP.
+#define BS_DAC_C2_DACBFRP (4U) //!< Bit field size in bits for DAC_C2_DACBFRP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DAC_C2_DACBFRP field.
+#define BR_DAC_C2_DACBFRP(x) (HW_DAC_C2(x).B.DACBFRP)
+#endif
+
+//! @brief Format value for bitfield DAC_C2_DACBFRP.
+#define BF_DAC_C2_DACBFRP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DAC_C2_DACBFRP), uint8_t) & BM_DAC_C2_DACBFRP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DACBFRP field to a new value.
+#define BW_DAC_C2_DACBFRP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFRP) | BF_DAC_C2_DACBFRP(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_dac_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All DAC module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_dac
+{
+ struct {
+ __IO hw_dac_datnl_t DATnL; //!< [0x0] DAC Data Low Register
+ __IO hw_dac_datnh_t DATnH; //!< [0x1] DAC Data High Register
+ } DAT[16];
+ __IO hw_dac_sr_t SR; //!< [0x20] DAC Status Register
+ __IO hw_dac_c0_t C0; //!< [0x21] DAC Control Register
+ __IO hw_dac_c1_t C1; //!< [0x22] DAC Control Register 1
+ __IO hw_dac_c2_t C2; //!< [0x23] DAC Control Register 2
+} hw_dac_t;
+#pragma pack()
+
+//! @brief Macro to access all DAC registers.
+//! @param x DAC instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_DAC(0)</code>.
+#define HW_DAC(x) (*(hw_dac_t *) REGS_DAC_BASE(x))
+#endif
+
+#endif // __HW_DAC_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_dma.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,5973 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_DMA_REGISTERS_H__
+#define __HW_DMA_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 DMA
+ *
+ * Enhanced direct memory access controller
+ *
+ * Registers defined in this header file:
+ * - HW_DMA_CR - Control Register
+ * - HW_DMA_ES - Error Status Register
+ * - HW_DMA_ERQ - Enable Request Register
+ * - HW_DMA_EEI - Enable Error Interrupt Register
+ * - HW_DMA_CEEI - Clear Enable Error Interrupt Register
+ * - HW_DMA_SEEI - Set Enable Error Interrupt Register
+ * - HW_DMA_CERQ - Clear Enable Request Register
+ * - HW_DMA_SERQ - Set Enable Request Register
+ * - HW_DMA_CDNE - Clear DONE Status Bit Register
+ * - HW_DMA_SSRT - Set START Bit Register
+ * - HW_DMA_CERR - Clear Error Register
+ * - HW_DMA_CINT - Clear Interrupt Request Register
+ * - HW_DMA_INT - Interrupt Request Register
+ * - HW_DMA_ERR - Error Register
+ * - HW_DMA_HRS - Hardware Request Status Register
+ * - HW_DMA_DCHPRIn - Channel n Priority Register
+ * - HW_DMA_TCDn_SADDR - TCD Source Address
+ * - HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset
+ * - HW_DMA_TCDn_ATTR - TCD Transfer Attributes
+ * - HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
+ * - HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
+ * - HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
+ * - HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment
+ * - HW_DMA_TCDn_DADDR - TCD Destination Address
+ * - HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset
+ * - HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ * - HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ * - HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address
+ * - HW_DMA_TCDn_CSR - TCD Control and Status
+ * - HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ * - HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ *
+ * - hw_dma_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_DMA_BASE
+#define HW_DMA_INSTANCE_COUNT (1U) //!< Number of instances of the DMA module.
+#define HW_DMA0 (0U) //!< Instance number for DMA.
+#define REGS_DMA0_BASE (0x40008000U) //!< Base address for DMA.
+
+//! @brief Table of base addresses for DMA instances.
+static const uint32_t __g_regs_DMA_base_addresses[] = {
+ REGS_DMA0_BASE,
+ };
+
+//! @brief Get the base address of DMA by instance number.
+//! @param x DMA instance number, from 0 through 0.
+#define REGS_DMA_BASE(x) (__g_regs_DMA_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of DMA.
+#define REGS_DMA_INSTANCE(b) ((b) == REGS_DMA0_BASE ? HW_DMA0 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_CR - Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_CR - Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The CR defines the basic operating configuration of the DMA. Arbitration can
+ * be configured to use either a fixed-priority or a round-robin scheme. For
+ * fixed-priority arbitration, the highest priority channel requesting service is
+ * selected to execute. The channel priority registers assign the priorities; see
+ * the DCHPRIn registers. For round-robin arbitration, the channel priorities are
+ * ignored and channels are cycled through (from high to low channel number)
+ * without regard to priority. For correct operation, writes to the CR register must
+ * be performed only when the DMA channels are inactive; that is, when
+ * TCDn_CSR[ACTIVE] bits are cleared. Minor loop offsets are address offset values added to
+ * the final source address (TCDn_SADDR) or destination address (TCDn_DADDR) upon
+ * minor loop completion. When minor loop offsets are enabled, the minor loop
+ * offset (MLOFF) is added to the final source address (TCDn_SADDR), to the final
+ * destination address (TCDn_DADDR), or to both prior to the addresses being
+ * written back into the TCD. If the major loop is complete, the minor loop offset is
+ * ignored and the major loop address offsets (TCDn_SLAST and TCDn_DLAST_SGA) are
+ * used to compute the next TCDn_SADDR and TCDn_DADDR values. When minor loop
+ * mapping is enabled (EMLM is 1), TCDn word2 is redefined. A portion of TCDn word2
+ * is used to specify multiple fields: a source enable bit (SMLOE) to specify
+ * the minor loop offset should be applied to the source address (TCDn_SADDR) upon
+ * minor loop completion, a destination enable bit (DMLOE) to specify the minor
+ * loop offset should be applied to the destination address (TCDn_DADDR) upon
+ * minor loop completion, and the sign extended minor loop offset value (MLOFF). The
+ * same offset value (MLOFF) is used for both source and destination minor loop
+ * offsets. When either minor loop offset is enabled (SMLOE set or DMLOE set), the
+ * NBYTES field is reduced to 10 bits. When both minor loop offsets are disabled
+ * (SMLOE cleared and DMLOE cleared), the NBYTES field is a 30-bit vector. When
+ * minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are
+ * assigned to the NBYTES field.
+ */
+typedef union _hw_dma_cr
+{
+ uint32_t U;
+ struct _hw_dma_cr_bitfields
+ {
+ uint32_t RESERVED0 : 1; //!< [0] Reserved.
+ uint32_t EDBG : 1; //!< [1] Enable Debug
+ uint32_t ERCA : 1; //!< [2] Enable Round Robin Channel Arbitration
+ uint32_t RESERVED1 : 1; //!< [3] Reserved.
+ uint32_t HOE : 1; //!< [4] Halt On Error
+ uint32_t HALT : 1; //!< [5] Halt DMA Operations
+ uint32_t CLM : 1; //!< [6] Continuous Link Mode
+ uint32_t EMLM : 1; //!< [7] Enable Minor Loop Mapping
+ uint32_t RESERVED2 : 8; //!< [15:8]
+ uint32_t ECX : 1; //!< [16] Error Cancel Transfer
+ uint32_t CX : 1; //!< [17] Cancel Transfer
+ uint32_t RESERVED3 : 14; //!< [31:18]
+ } B;
+} hw_dma_cr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_CR register
+ */
+//@{
+#define HW_DMA_CR_ADDR(x) (REGS_DMA_BASE(x) + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_CR(x) (*(__IO hw_dma_cr_t *) HW_DMA_CR_ADDR(x))
+#define HW_DMA_CR_RD(x) (HW_DMA_CR(x).U)
+#define HW_DMA_CR_WR(x, v) (HW_DMA_CR(x).U = (v))
+#define HW_DMA_CR_SET(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) | (v)))
+#define HW_DMA_CR_CLR(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) & ~(v)))
+#define HW_DMA_CR_TOG(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_CR bitfields
+ */
+
+/*!
+ * @name Register DMA_CR, field EDBG[1] (RW)
+ *
+ * Values:
+ * - 0 - When in debug mode, the DMA continues to operate.
+ * - 1 - When in debug mode, the DMA stalls the start of a new channel.
+ * Executing channels are allowed to complete. Channel execution resumes when the
+ * system exits debug mode or the EDBG bit is cleared.
+ */
+//@{
+#define BP_DMA_CR_EDBG (1U) //!< Bit position for DMA_CR_EDBG.
+#define BM_DMA_CR_EDBG (0x00000002U) //!< Bit mask for DMA_CR_EDBG.
+#define BS_DMA_CR_EDBG (1U) //!< Bit field size in bits for DMA_CR_EDBG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_CR_EDBG field.
+#define BR_DMA_CR_EDBG(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EDBG))
+#endif
+
+//! @brief Format value for bitfield DMA_CR_EDBG.
+#define BF_DMA_CR_EDBG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_EDBG), uint32_t) & BM_DMA_CR_EDBG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EDBG field to a new value.
+#define BW_DMA_CR_EDBG(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EDBG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CR, field ERCA[2] (RW)
+ *
+ * Values:
+ * - 0 - Fixed priority arbitration is used for channel selection .
+ * - 1 - Round robin arbitration is used for channel selection .
+ */
+//@{
+#define BP_DMA_CR_ERCA (2U) //!< Bit position for DMA_CR_ERCA.
+#define BM_DMA_CR_ERCA (0x00000004U) //!< Bit mask for DMA_CR_ERCA.
+#define BS_DMA_CR_ERCA (1U) //!< Bit field size in bits for DMA_CR_ERCA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_CR_ERCA field.
+#define BR_DMA_CR_ERCA(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ERCA))
+#endif
+
+//! @brief Format value for bitfield DMA_CR_ERCA.
+#define BF_DMA_CR_ERCA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_ERCA), uint32_t) & BM_DMA_CR_ERCA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERCA field to a new value.
+#define BW_DMA_CR_ERCA(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ERCA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CR, field HOE[4] (RW)
+ *
+ * Values:
+ * - 0 - Normal operation
+ * - 1 - Any error causes the HALT bit to set. Subsequently, all service
+ * requests are ignored until the HALT bit is cleared.
+ */
+//@{
+#define BP_DMA_CR_HOE (4U) //!< Bit position for DMA_CR_HOE.
+#define BM_DMA_CR_HOE (0x00000010U) //!< Bit mask for DMA_CR_HOE.
+#define BS_DMA_CR_HOE (1U) //!< Bit field size in bits for DMA_CR_HOE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_CR_HOE field.
+#define BR_DMA_CR_HOE(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HOE))
+#endif
+
+//! @brief Format value for bitfield DMA_CR_HOE.
+#define BF_DMA_CR_HOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_HOE), uint32_t) & BM_DMA_CR_HOE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HOE field to a new value.
+#define BW_DMA_CR_HOE(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HOE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CR, field HALT[5] (RW)
+ *
+ * Values:
+ * - 0 - Normal operation
+ * - 1 - Stall the start of any new channels. Executing channels are allowed to
+ * complete. Channel execution resumes when this bit is cleared.
+ */
+//@{
+#define BP_DMA_CR_HALT (5U) //!< Bit position for DMA_CR_HALT.
+#define BM_DMA_CR_HALT (0x00000020U) //!< Bit mask for DMA_CR_HALT.
+#define BS_DMA_CR_HALT (1U) //!< Bit field size in bits for DMA_CR_HALT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_CR_HALT field.
+#define BR_DMA_CR_HALT(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HALT))
+#endif
+
+//! @brief Format value for bitfield DMA_CR_HALT.
+#define BF_DMA_CR_HALT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_HALT), uint32_t) & BM_DMA_CR_HALT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HALT field to a new value.
+#define BW_DMA_CR_HALT(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HALT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CR, field CLM[6] (RW)
+ *
+ * Values:
+ * - 0 - A minor loop channel link made to itself goes through channel
+ * arbitration before being activated again.
+ * - 1 - A minor loop channel link made to itself does not go through channel
+ * arbitration before being activated again. Upon minor loop completion, the
+ * channel activates again if that channel has a minor loop channel link
+ * enabled and the link channel is itself. This effectively applies the minor loop
+ * offsets and restarts the next minor loop.
+ */
+//@{
+#define BP_DMA_CR_CLM (6U) //!< Bit position for DMA_CR_CLM.
+#define BM_DMA_CR_CLM (0x00000040U) //!< Bit mask for DMA_CR_CLM.
+#define BS_DMA_CR_CLM (1U) //!< Bit field size in bits for DMA_CR_CLM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_CR_CLM field.
+#define BR_DMA_CR_CLM(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CLM))
+#endif
+
+//! @brief Format value for bitfield DMA_CR_CLM.
+#define BF_DMA_CR_CLM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_CLM), uint32_t) & BM_DMA_CR_CLM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLM field to a new value.
+#define BW_DMA_CR_CLM(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CLM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CR, field EMLM[7] (RW)
+ *
+ * Values:
+ * - 0 - Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
+ * - 1 - Enabled. TCDn.word2 is redefined to include individual enable fields,
+ * an offset field, and the NBYTES field. The individual enable fields allow
+ * the minor loop offset to be applied to the source address, the destination
+ * address, or both. The NBYTES field is reduced when either offset is
+ * enabled.
+ */
+//@{
+#define BP_DMA_CR_EMLM (7U) //!< Bit position for DMA_CR_EMLM.
+#define BM_DMA_CR_EMLM (0x00000080U) //!< Bit mask for DMA_CR_EMLM.
+#define BS_DMA_CR_EMLM (1U) //!< Bit field size in bits for DMA_CR_EMLM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_CR_EMLM field.
+#define BR_DMA_CR_EMLM(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EMLM))
+#endif
+
+//! @brief Format value for bitfield DMA_CR_EMLM.
+#define BF_DMA_CR_EMLM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_EMLM), uint32_t) & BM_DMA_CR_EMLM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EMLM field to a new value.
+#define BW_DMA_CR_EMLM(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EMLM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CR, field ECX[16] (RW)
+ *
+ * Values:
+ * - 0 - Normal operation
+ * - 1 - Cancel the remaining data transfer in the same fashion as the CX bit.
+ * Stop the executing channel and force the minor loop to finish. The cancel
+ * takes effect after the last write of the current read/write sequence. The
+ * ECX bit clears itself after the cancel is honored. In addition to
+ * cancelling the transfer, ECX treats the cancel as an error condition, thus updating
+ * the Error Status register (DMAx_ES) and generating an optional error
+ * interrupt.
+ */
+//@{
+#define BP_DMA_CR_ECX (16U) //!< Bit position for DMA_CR_ECX.
+#define BM_DMA_CR_ECX (0x00010000U) //!< Bit mask for DMA_CR_ECX.
+#define BS_DMA_CR_ECX (1U) //!< Bit field size in bits for DMA_CR_ECX.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_CR_ECX field.
+#define BR_DMA_CR_ECX(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ECX))
+#endif
+
+//! @brief Format value for bitfield DMA_CR_ECX.
+#define BF_DMA_CR_ECX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_ECX), uint32_t) & BM_DMA_CR_ECX)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ECX field to a new value.
+#define BW_DMA_CR_ECX(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ECX) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CR, field CX[17] (RW)
+ *
+ * Values:
+ * - 0 - Normal operation
+ * - 1 - Cancel the remaining data transfer. Stop the executing channel and
+ * force the minor loop to finish. The cancel takes effect after the last write
+ * of the current read/write sequence. The CX bit clears itself after the
+ * cancel has been honored. This cancel retires the channel normally as if the
+ * minor loop was completed.
+ */
+//@{
+#define BP_DMA_CR_CX (17U) //!< Bit position for DMA_CR_CX.
+#define BM_DMA_CR_CX (0x00020000U) //!< Bit mask for DMA_CR_CX.
+#define BS_DMA_CR_CX (1U) //!< Bit field size in bits for DMA_CR_CX.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_CR_CX field.
+#define BR_DMA_CR_CX(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CX))
+#endif
+
+//! @brief Format value for bitfield DMA_CR_CX.
+#define BF_DMA_CR_CX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_CX), uint32_t) & BM_DMA_CR_CX)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CX field to a new value.
+#define BW_DMA_CR_CX(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CX) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_ES - Error Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_ES - Error Status Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The ES provides information concerning the last recorded channel error.
+ * Channel errors can be caused by: A configuration error, that is: An illegal setting
+ * in the transfer-control descriptor, or An illegal priority register setting
+ * in fixed-arbitration An error termination to a bus master read or write cycle
+ * See the Error Reporting and Handling section for more details.
+ */
+typedef union _hw_dma_es
+{
+ uint32_t U;
+ struct _hw_dma_es_bitfields
+ {
+ uint32_t DBE : 1; //!< [0] Destination Bus Error
+ uint32_t SBE : 1; //!< [1] Source Bus Error
+ uint32_t SGE : 1; //!< [2] Scatter/Gather Configuration Error
+ uint32_t NCE : 1; //!< [3] NBYTES/CITER Configuration Error
+ uint32_t DOE : 1; //!< [4] Destination Offset Error
+ uint32_t DAE : 1; //!< [5] Destination Address Error
+ uint32_t SOE : 1; //!< [6] Source Offset Error
+ uint32_t SAE : 1; //!< [7] Source Address Error
+ uint32_t ERRCHN : 4; //!< [11:8] Error Channel Number or Canceled
+ //! Channel Number
+ uint32_t RESERVED0 : 2; //!< [13:12]
+ uint32_t CPE : 1; //!< [14] Channel Priority Error
+ uint32_t RESERVED1 : 1; //!< [15]
+ uint32_t ECX : 1; //!< [16] Transfer Canceled
+ uint32_t RESERVED2 : 14; //!< [30:17]
+ uint32_t VLD : 1; //!< [31]
+ } B;
+} hw_dma_es_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_ES register
+ */
+//@{
+#define HW_DMA_ES_ADDR(x) (REGS_DMA_BASE(x) + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_ES(x) (*(__I hw_dma_es_t *) HW_DMA_ES_ADDR(x))
+#define HW_DMA_ES_RD(x) (HW_DMA_ES(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_ES bitfields
+ */
+
+/*!
+ * @name Register DMA_ES, field DBE[0] (RO)
+ *
+ * Values:
+ * - 0 - No destination bus error
+ * - 1 - The last recorded error was a bus error on a destination write
+ */
+//@{
+#define BP_DMA_ES_DBE (0U) //!< Bit position for DMA_ES_DBE.
+#define BM_DMA_ES_DBE (0x00000001U) //!< Bit mask for DMA_ES_DBE.
+#define BS_DMA_ES_DBE (1U) //!< Bit field size in bits for DMA_ES_DBE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ES_DBE field.
+#define BR_DMA_ES_DBE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DBE))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ES, field SBE[1] (RO)
+ *
+ * Values:
+ * - 0 - No source bus error
+ * - 1 - The last recorded error was a bus error on a source read
+ */
+//@{
+#define BP_DMA_ES_SBE (1U) //!< Bit position for DMA_ES_SBE.
+#define BM_DMA_ES_SBE (0x00000002U) //!< Bit mask for DMA_ES_SBE.
+#define BS_DMA_ES_SBE (1U) //!< Bit field size in bits for DMA_ES_SBE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ES_SBE field.
+#define BR_DMA_ES_SBE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SBE))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ES, field SGE[2] (RO)
+ *
+ * Values:
+ * - 0 - No scatter/gather configuration error
+ * - 1 - The last recorded error was a configuration error detected in the
+ * TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather
+ * operation after major loop completion if TCDn_CSR[ESG] is enabled.
+ * TCDn_DLASTSGA is not on a 32 byte boundary.
+ */
+//@{
+#define BP_DMA_ES_SGE (2U) //!< Bit position for DMA_ES_SGE.
+#define BM_DMA_ES_SGE (0x00000004U) //!< Bit mask for DMA_ES_SGE.
+#define BS_DMA_ES_SGE (1U) //!< Bit field size in bits for DMA_ES_SGE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ES_SGE field.
+#define BR_DMA_ES_SGE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SGE))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ES, field NCE[3] (RO)
+ *
+ * Values:
+ * - 0 - No NBYTES/CITER configuration error
+ * - 1 - The last recorded error was a configuration error detected in the
+ * TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of
+ * TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or
+ * TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
+ */
+//@{
+#define BP_DMA_ES_NCE (3U) //!< Bit position for DMA_ES_NCE.
+#define BM_DMA_ES_NCE (0x00000008U) //!< Bit mask for DMA_ES_NCE.
+#define BS_DMA_ES_NCE (1U) //!< Bit field size in bits for DMA_ES_NCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ES_NCE field.
+#define BR_DMA_ES_NCE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_NCE))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ES, field DOE[4] (RO)
+ *
+ * Values:
+ * - 0 - No destination offset configuration error
+ * - 1 - The last recorded error was a configuration error detected in the
+ * TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
+ */
+//@{
+#define BP_DMA_ES_DOE (4U) //!< Bit position for DMA_ES_DOE.
+#define BM_DMA_ES_DOE (0x00000010U) //!< Bit mask for DMA_ES_DOE.
+#define BS_DMA_ES_DOE (1U) //!< Bit field size in bits for DMA_ES_DOE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ES_DOE field.
+#define BR_DMA_ES_DOE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DOE))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ES, field DAE[5] (RO)
+ *
+ * Values:
+ * - 0 - No destination address configuration error
+ * - 1 - The last recorded error was a configuration error detected in the
+ * TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
+ */
+//@{
+#define BP_DMA_ES_DAE (5U) //!< Bit position for DMA_ES_DAE.
+#define BM_DMA_ES_DAE (0x00000020U) //!< Bit mask for DMA_ES_DAE.
+#define BS_DMA_ES_DAE (1U) //!< Bit field size in bits for DMA_ES_DAE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ES_DAE field.
+#define BR_DMA_ES_DAE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DAE))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ES, field SOE[6] (RO)
+ *
+ * Values:
+ * - 0 - No source offset configuration error
+ * - 1 - The last recorded error was a configuration error detected in the
+ * TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
+ */
+//@{
+#define BP_DMA_ES_SOE (6U) //!< Bit position for DMA_ES_SOE.
+#define BM_DMA_ES_SOE (0x00000040U) //!< Bit mask for DMA_ES_SOE.
+#define BS_DMA_ES_SOE (1U) //!< Bit field size in bits for DMA_ES_SOE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ES_SOE field.
+#define BR_DMA_ES_SOE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SOE))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ES, field SAE[7] (RO)
+ *
+ * Values:
+ * - 0 - No source address configuration error.
+ * - 1 - The last recorded error was a configuration error detected in the
+ * TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
+ */
+//@{
+#define BP_DMA_ES_SAE (7U) //!< Bit position for DMA_ES_SAE.
+#define BM_DMA_ES_SAE (0x00000080U) //!< Bit mask for DMA_ES_SAE.
+#define BS_DMA_ES_SAE (1U) //!< Bit field size in bits for DMA_ES_SAE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ES_SAE field.
+#define BR_DMA_ES_SAE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SAE))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ES, field ERRCHN[11:8] (RO)
+ *
+ * The channel number of the last recorded error (excluding CPE errors) or last
+ * recorded error canceled transfer.
+ */
+//@{
+#define BP_DMA_ES_ERRCHN (8U) //!< Bit position for DMA_ES_ERRCHN.
+#define BM_DMA_ES_ERRCHN (0x00000F00U) //!< Bit mask for DMA_ES_ERRCHN.
+#define BS_DMA_ES_ERRCHN (4U) //!< Bit field size in bits for DMA_ES_ERRCHN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ES_ERRCHN field.
+#define BR_DMA_ES_ERRCHN(x) (HW_DMA_ES(x).B.ERRCHN)
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ES, field CPE[14] (RO)
+ *
+ * Values:
+ * - 0 - No channel priority error
+ * - 1 - The last recorded error was a configuration error in the channel
+ * priorities . Channel priorities are not unique.
+ */
+//@{
+#define BP_DMA_ES_CPE (14U) //!< Bit position for DMA_ES_CPE.
+#define BM_DMA_ES_CPE (0x00004000U) //!< Bit mask for DMA_ES_CPE.
+#define BS_DMA_ES_CPE (1U) //!< Bit field size in bits for DMA_ES_CPE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ES_CPE field.
+#define BR_DMA_ES_CPE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_CPE))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ES, field ECX[16] (RO)
+ *
+ * Values:
+ * - 0 - No canceled transfers
+ * - 1 - The last recorded entry was a canceled transfer by the error cancel
+ * transfer input
+ */
+//@{
+#define BP_DMA_ES_ECX (16U) //!< Bit position for DMA_ES_ECX.
+#define BM_DMA_ES_ECX (0x00010000U) //!< Bit mask for DMA_ES_ECX.
+#define BS_DMA_ES_ECX (1U) //!< Bit field size in bits for DMA_ES_ECX.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ES_ECX field.
+#define BR_DMA_ES_ECX(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_ECX))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ES, field VLD[31] (RO)
+ *
+ * Logical OR of all ERR status bits
+ *
+ * Values:
+ * - 0 - No ERR bits are set
+ * - 1 - At least one ERR bit is set indicating a valid error exists that has
+ * not been cleared
+ */
+//@{
+#define BP_DMA_ES_VLD (31U) //!< Bit position for DMA_ES_VLD.
+#define BM_DMA_ES_VLD (0x80000000U) //!< Bit mask for DMA_ES_VLD.
+#define BS_DMA_ES_VLD (1U) //!< Bit field size in bits for DMA_ES_VLD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ES_VLD field.
+#define BR_DMA_ES_VLD(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_VLD))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_ERQ - Enable Request Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_ERQ - Enable Request Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The ERQ register provides a bit map for the 16 implemented channels to enable
+ * the request signal for each channel. The state of any given channel enable is
+ * directly affected by writes to this register; it is also affected by writes
+ * to the SERQ and CERQ. The {S,C}ERQ registers are provided so the request enable
+ * for a single channel can easily be modified without needing to perform a
+ * read-modify-write sequence to the ERQ. DMA request input signals and this enable
+ * request flag must be asserted before a channel's hardware service request is
+ * accepted. The state of the DMA enable request flag does not affect a channel
+ * service request made explicitly through software or a linked channel request.
+ */
+typedef union _hw_dma_erq
+{
+ uint32_t U;
+ struct _hw_dma_erq_bitfields
+ {
+ uint32_t ERQ0 : 1; //!< [0] Enable DMA Request 0
+ uint32_t ERQ1 : 1; //!< [1] Enable DMA Request 1
+ uint32_t ERQ2 : 1; //!< [2] Enable DMA Request 2
+ uint32_t ERQ3 : 1; //!< [3] Enable DMA Request 3
+ uint32_t ERQ4 : 1; //!< [4] Enable DMA Request 4
+ uint32_t ERQ5 : 1; //!< [5] Enable DMA Request 5
+ uint32_t ERQ6 : 1; //!< [6] Enable DMA Request 6
+ uint32_t ERQ7 : 1; //!< [7] Enable DMA Request 7
+ uint32_t ERQ8 : 1; //!< [8] Enable DMA Request 8
+ uint32_t ERQ9 : 1; //!< [9] Enable DMA Request 9
+ uint32_t ERQ10 : 1; //!< [10] Enable DMA Request 10
+ uint32_t ERQ11 : 1; //!< [11] Enable DMA Request 11
+ uint32_t ERQ12 : 1; //!< [12] Enable DMA Request 12
+ uint32_t ERQ13 : 1; //!< [13] Enable DMA Request 13
+ uint32_t ERQ14 : 1; //!< [14] Enable DMA Request 14
+ uint32_t ERQ15 : 1; //!< [15] Enable DMA Request 15
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_dma_erq_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_ERQ register
+ */
+//@{
+#define HW_DMA_ERQ_ADDR(x) (REGS_DMA_BASE(x) + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_ERQ(x) (*(__IO hw_dma_erq_t *) HW_DMA_ERQ_ADDR(x))
+#define HW_DMA_ERQ_RD(x) (HW_DMA_ERQ(x).U)
+#define HW_DMA_ERQ_WR(x, v) (HW_DMA_ERQ(x).U = (v))
+#define HW_DMA_ERQ_SET(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) | (v)))
+#define HW_DMA_ERQ_CLR(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) & ~(v)))
+#define HW_DMA_ERQ_TOG(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_ERQ bitfields
+ */
+
+/*!
+ * @name Register DMA_ERQ, field ERQ0[0] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ0 (0U) //!< Bit position for DMA_ERQ_ERQ0.
+#define BM_DMA_ERQ_ERQ0 (0x00000001U) //!< Bit mask for DMA_ERQ_ERQ0.
+#define BS_DMA_ERQ_ERQ0 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ0 field.
+#define BR_DMA_ERQ_ERQ0(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ0))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ0.
+#define BF_DMA_ERQ_ERQ0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ0), uint32_t) & BM_DMA_ERQ_ERQ0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ0 field to a new value.
+#define BW_DMA_ERQ_ERQ0(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ1[1] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ1 (1U) //!< Bit position for DMA_ERQ_ERQ1.
+#define BM_DMA_ERQ_ERQ1 (0x00000002U) //!< Bit mask for DMA_ERQ_ERQ1.
+#define BS_DMA_ERQ_ERQ1 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ1 field.
+#define BR_DMA_ERQ_ERQ1(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ1))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ1.
+#define BF_DMA_ERQ_ERQ1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ1), uint32_t) & BM_DMA_ERQ_ERQ1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ1 field to a new value.
+#define BW_DMA_ERQ_ERQ1(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ2[2] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ2 (2U) //!< Bit position for DMA_ERQ_ERQ2.
+#define BM_DMA_ERQ_ERQ2 (0x00000004U) //!< Bit mask for DMA_ERQ_ERQ2.
+#define BS_DMA_ERQ_ERQ2 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ2 field.
+#define BR_DMA_ERQ_ERQ2(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ2))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ2.
+#define BF_DMA_ERQ_ERQ2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ2), uint32_t) & BM_DMA_ERQ_ERQ2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ2 field to a new value.
+#define BW_DMA_ERQ_ERQ2(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ3[3] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ3 (3U) //!< Bit position for DMA_ERQ_ERQ3.
+#define BM_DMA_ERQ_ERQ3 (0x00000008U) //!< Bit mask for DMA_ERQ_ERQ3.
+#define BS_DMA_ERQ_ERQ3 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ3 field.
+#define BR_DMA_ERQ_ERQ3(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ3))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ3.
+#define BF_DMA_ERQ_ERQ3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ3), uint32_t) & BM_DMA_ERQ_ERQ3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ3 field to a new value.
+#define BW_DMA_ERQ_ERQ3(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ4[4] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ4 (4U) //!< Bit position for DMA_ERQ_ERQ4.
+#define BM_DMA_ERQ_ERQ4 (0x00000010U) //!< Bit mask for DMA_ERQ_ERQ4.
+#define BS_DMA_ERQ_ERQ4 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ4 field.
+#define BR_DMA_ERQ_ERQ4(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ4))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ4.
+#define BF_DMA_ERQ_ERQ4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ4), uint32_t) & BM_DMA_ERQ_ERQ4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ4 field to a new value.
+#define BW_DMA_ERQ_ERQ4(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ5[5] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ5 (5U) //!< Bit position for DMA_ERQ_ERQ5.
+#define BM_DMA_ERQ_ERQ5 (0x00000020U) //!< Bit mask for DMA_ERQ_ERQ5.
+#define BS_DMA_ERQ_ERQ5 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ5 field.
+#define BR_DMA_ERQ_ERQ5(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ5))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ5.
+#define BF_DMA_ERQ_ERQ5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ5), uint32_t) & BM_DMA_ERQ_ERQ5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ5 field to a new value.
+#define BW_DMA_ERQ_ERQ5(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ6[6] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ6 (6U) //!< Bit position for DMA_ERQ_ERQ6.
+#define BM_DMA_ERQ_ERQ6 (0x00000040U) //!< Bit mask for DMA_ERQ_ERQ6.
+#define BS_DMA_ERQ_ERQ6 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ6 field.
+#define BR_DMA_ERQ_ERQ6(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ6))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ6.
+#define BF_DMA_ERQ_ERQ6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ6), uint32_t) & BM_DMA_ERQ_ERQ6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ6 field to a new value.
+#define BW_DMA_ERQ_ERQ6(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ7[7] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ7 (7U) //!< Bit position for DMA_ERQ_ERQ7.
+#define BM_DMA_ERQ_ERQ7 (0x00000080U) //!< Bit mask for DMA_ERQ_ERQ7.
+#define BS_DMA_ERQ_ERQ7 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ7 field.
+#define BR_DMA_ERQ_ERQ7(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ7))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ7.
+#define BF_DMA_ERQ_ERQ7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ7), uint32_t) & BM_DMA_ERQ_ERQ7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ7 field to a new value.
+#define BW_DMA_ERQ_ERQ7(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ8[8] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ8 (8U) //!< Bit position for DMA_ERQ_ERQ8.
+#define BM_DMA_ERQ_ERQ8 (0x00000100U) //!< Bit mask for DMA_ERQ_ERQ8.
+#define BS_DMA_ERQ_ERQ8 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ8.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ8 field.
+#define BR_DMA_ERQ_ERQ8(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ8))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ8.
+#define BF_DMA_ERQ_ERQ8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ8), uint32_t) & BM_DMA_ERQ_ERQ8)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ8 field to a new value.
+#define BW_DMA_ERQ_ERQ8(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ8) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ9[9] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ9 (9U) //!< Bit position for DMA_ERQ_ERQ9.
+#define BM_DMA_ERQ_ERQ9 (0x00000200U) //!< Bit mask for DMA_ERQ_ERQ9.
+#define BS_DMA_ERQ_ERQ9 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ9.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ9 field.
+#define BR_DMA_ERQ_ERQ9(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ9))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ9.
+#define BF_DMA_ERQ_ERQ9(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ9), uint32_t) & BM_DMA_ERQ_ERQ9)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ9 field to a new value.
+#define BW_DMA_ERQ_ERQ9(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ9) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ10[10] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ10 (10U) //!< Bit position for DMA_ERQ_ERQ10.
+#define BM_DMA_ERQ_ERQ10 (0x00000400U) //!< Bit mask for DMA_ERQ_ERQ10.
+#define BS_DMA_ERQ_ERQ10 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ10.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ10 field.
+#define BR_DMA_ERQ_ERQ10(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ10))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ10.
+#define BF_DMA_ERQ_ERQ10(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ10), uint32_t) & BM_DMA_ERQ_ERQ10)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ10 field to a new value.
+#define BW_DMA_ERQ_ERQ10(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ10) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ11[11] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ11 (11U) //!< Bit position for DMA_ERQ_ERQ11.
+#define BM_DMA_ERQ_ERQ11 (0x00000800U) //!< Bit mask for DMA_ERQ_ERQ11.
+#define BS_DMA_ERQ_ERQ11 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ11.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ11 field.
+#define BR_DMA_ERQ_ERQ11(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ11))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ11.
+#define BF_DMA_ERQ_ERQ11(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ11), uint32_t) & BM_DMA_ERQ_ERQ11)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ11 field to a new value.
+#define BW_DMA_ERQ_ERQ11(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ11) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ12[12] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ12 (12U) //!< Bit position for DMA_ERQ_ERQ12.
+#define BM_DMA_ERQ_ERQ12 (0x00001000U) //!< Bit mask for DMA_ERQ_ERQ12.
+#define BS_DMA_ERQ_ERQ12 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ12.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ12 field.
+#define BR_DMA_ERQ_ERQ12(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ12))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ12.
+#define BF_DMA_ERQ_ERQ12(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ12), uint32_t) & BM_DMA_ERQ_ERQ12)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ12 field to a new value.
+#define BW_DMA_ERQ_ERQ12(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ12) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ13[13] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ13 (13U) //!< Bit position for DMA_ERQ_ERQ13.
+#define BM_DMA_ERQ_ERQ13 (0x00002000U) //!< Bit mask for DMA_ERQ_ERQ13.
+#define BS_DMA_ERQ_ERQ13 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ13.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ13 field.
+#define BR_DMA_ERQ_ERQ13(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ13))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ13.
+#define BF_DMA_ERQ_ERQ13(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ13), uint32_t) & BM_DMA_ERQ_ERQ13)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ13 field to a new value.
+#define BW_DMA_ERQ_ERQ13(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ13) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ14[14] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ14 (14U) //!< Bit position for DMA_ERQ_ERQ14.
+#define BM_DMA_ERQ_ERQ14 (0x00004000U) //!< Bit mask for DMA_ERQ_ERQ14.
+#define BS_DMA_ERQ_ERQ14 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ14.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ14 field.
+#define BR_DMA_ERQ_ERQ14(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ14))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ14.
+#define BF_DMA_ERQ_ERQ14(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ14), uint32_t) & BM_DMA_ERQ_ERQ14)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ14 field to a new value.
+#define BW_DMA_ERQ_ERQ14(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ14) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERQ, field ERQ15[15] (RW)
+ *
+ * Values:
+ * - 0 - The DMA request signal for the corresponding channel is disabled
+ * - 1 - The DMA request signal for the corresponding channel is enabled
+ */
+//@{
+#define BP_DMA_ERQ_ERQ15 (15U) //!< Bit position for DMA_ERQ_ERQ15.
+#define BM_DMA_ERQ_ERQ15 (0x00008000U) //!< Bit mask for DMA_ERQ_ERQ15.
+#define BS_DMA_ERQ_ERQ15 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ15.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERQ_ERQ15 field.
+#define BR_DMA_ERQ_ERQ15(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ15))
+#endif
+
+//! @brief Format value for bitfield DMA_ERQ_ERQ15.
+#define BF_DMA_ERQ_ERQ15(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ15), uint32_t) & BM_DMA_ERQ_ERQ15)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERQ15 field to a new value.
+#define BW_DMA_ERQ_ERQ15(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ15) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_EEI - Enable Error Interrupt Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_EEI - Enable Error Interrupt Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The EEI register provides a bit map for the 16 channels to enable the error
+ * interrupt signal for each channel. The state of any given channel's error
+ * interrupt enable is directly affected by writes to this register; it is also
+ * affected by writes to the SEEI and CEEI. The {S,C}EEI are provided so the error
+ * interrupt enable for a single channel can easily be modified without the need to
+ * perform a read-modify-write sequence to the EEI register. The DMA error
+ * indicator and the error interrupt enable flag must be asserted before an error
+ * interrupt request for a given channel is asserted to the interrupt controller.
+ */
+typedef union _hw_dma_eei
+{
+ uint32_t U;
+ struct _hw_dma_eei_bitfields
+ {
+ uint32_t EEI0 : 1; //!< [0] Enable Error Interrupt 0
+ uint32_t EEI1 : 1; //!< [1] Enable Error Interrupt 1
+ uint32_t EEI2 : 1; //!< [2] Enable Error Interrupt 2
+ uint32_t EEI3 : 1; //!< [3] Enable Error Interrupt 3
+ uint32_t EEI4 : 1; //!< [4] Enable Error Interrupt 4
+ uint32_t EEI5 : 1; //!< [5] Enable Error Interrupt 5
+ uint32_t EEI6 : 1; //!< [6] Enable Error Interrupt 6
+ uint32_t EEI7 : 1; //!< [7] Enable Error Interrupt 7
+ uint32_t EEI8 : 1; //!< [8] Enable Error Interrupt 8
+ uint32_t EEI9 : 1; //!< [9] Enable Error Interrupt 9
+ uint32_t EEI10 : 1; //!< [10] Enable Error Interrupt 10
+ uint32_t EEI11 : 1; //!< [11] Enable Error Interrupt 11
+ uint32_t EEI12 : 1; //!< [12] Enable Error Interrupt 12
+ uint32_t EEI13 : 1; //!< [13] Enable Error Interrupt 13
+ uint32_t EEI14 : 1; //!< [14] Enable Error Interrupt 14
+ uint32_t EEI15 : 1; //!< [15] Enable Error Interrupt 15
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_dma_eei_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_EEI register
+ */
+//@{
+#define HW_DMA_EEI_ADDR(x) (REGS_DMA_BASE(x) + 0x14U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_EEI(x) (*(__IO hw_dma_eei_t *) HW_DMA_EEI_ADDR(x))
+#define HW_DMA_EEI_RD(x) (HW_DMA_EEI(x).U)
+#define HW_DMA_EEI_WR(x, v) (HW_DMA_EEI(x).U = (v))
+#define HW_DMA_EEI_SET(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) | (v)))
+#define HW_DMA_EEI_CLR(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) & ~(v)))
+#define HW_DMA_EEI_TOG(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_EEI bitfields
+ */
+
+/*!
+ * @name Register DMA_EEI, field EEI0[0] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ * interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ * an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI0 (0U) //!< Bit position for DMA_EEI_EEI0.
+#define BM_DMA_EEI_EEI0 (0x00000001U) //!< Bit mask for DMA_EEI_EEI0.
+#define BS_DMA_EEI_EEI0 (1U) //!< Bit field size in bits for DMA_EEI_EEI0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI0 field.
+#define BR_DMA_EEI_EEI0(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI0))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI0.
+#define BF_DMA_EEI_EEI0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI0), uint32_t) & BM_DMA_EEI_EEI0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI0 field to a new value.
+#define BW_DMA_EEI_EEI0(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI1[1] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ * interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ * an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI1 (1U) //!< Bit position for DMA_EEI_EEI1.
+#define BM_DMA_EEI_EEI1 (0x00000002U) //!< Bit mask for DMA_EEI_EEI1.
+#define BS_DMA_EEI_EEI1 (1U) //!< Bit field size in bits for DMA_EEI_EEI1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI1 field.
+#define BR_DMA_EEI_EEI1(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI1))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI1.
+#define BF_DMA_EEI_EEI1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI1), uint32_t) & BM_DMA_EEI_EEI1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI1 field to a new value.
+#define BW_DMA_EEI_EEI1(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI2[2] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ * interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ * an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI2 (2U) //!< Bit position for DMA_EEI_EEI2.
+#define BM_DMA_EEI_EEI2 (0x00000004U) //!< Bit mask for DMA_EEI_EEI2.
+#define BS_DMA_EEI_EEI2 (1U) //!< Bit field size in bits for DMA_EEI_EEI2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI2 field.
+#define BR_DMA_EEI_EEI2(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI2))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI2.
+#define BF_DMA_EEI_EEI2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI2), uint32_t) & BM_DMA_EEI_EEI2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI2 field to a new value.
+#define BW_DMA_EEI_EEI2(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI3[3] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ * interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ * an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI3 (3U) //!< Bit position for DMA_EEI_EEI3.
+#define BM_DMA_EEI_EEI3 (0x00000008U) //!< Bit mask for DMA_EEI_EEI3.
+#define BS_DMA_EEI_EEI3 (1U) //!< Bit field size in bits for DMA_EEI_EEI3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI3 field.
+#define BR_DMA_EEI_EEI3(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI3))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI3.
+#define BF_DMA_EEI_EEI3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI3), uint32_t) & BM_DMA_EEI_EEI3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI3 field to a new value.
+#define BW_DMA_EEI_EEI3(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI4[4] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ * interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ * an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI4 (4U) //!< Bit position for DMA_EEI_EEI4.
+#define BM_DMA_EEI_EEI4 (0x00000010U) //!< Bit mask for DMA_EEI_EEI4.
+#define BS_DMA_EEI_EEI4 (1U) //!< Bit field size in bits for DMA_EEI_EEI4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI4 field.
+#define BR_DMA_EEI_EEI4(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI4))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI4.
+#define BF_DMA_EEI_EEI4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI4), uint32_t) & BM_DMA_EEI_EEI4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI4 field to a new value.
+#define BW_DMA_EEI_EEI4(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI5[5] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ * interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ * an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI5 (5U) //!< Bit position for DMA_EEI_EEI5.
+#define BM_DMA_EEI_EEI5 (0x00000020U) //!< Bit mask for DMA_EEI_EEI5.
+#define BS_DMA_EEI_EEI5 (1U) //!< Bit field size in bits for DMA_EEI_EEI5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI5 field.
+#define BR_DMA_EEI_EEI5(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI5))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI5.
+#define BF_DMA_EEI_EEI5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI5), uint32_t) & BM_DMA_EEI_EEI5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI5 field to a new value.
+#define BW_DMA_EEI_EEI5(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI6[6] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ * interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ * an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI6 (6U) //!< Bit position for DMA_EEI_EEI6.
+#define BM_DMA_EEI_EEI6 (0x00000040U) //!< Bit mask for DMA_EEI_EEI6.
+#define BS_DMA_EEI_EEI6 (1U) //!< Bit field size in bits for DMA_EEI_EEI6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI6 field.
+#define BR_DMA_EEI_EEI6(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI6))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI6.
+#define BF_DMA_EEI_EEI6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI6), uint32_t) & BM_DMA_EEI_EEI6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI6 field to a new value.
+#define BW_DMA_EEI_EEI6(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI7[7] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ * interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ * an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI7 (7U) //!< Bit position for DMA_EEI_EEI7.
+#define BM_DMA_EEI_EEI7 (0x00000080U) //!< Bit mask for DMA_EEI_EEI7.
+#define BS_DMA_EEI_EEI7 (1U) //!< Bit field size in bits for DMA_EEI_EEI7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI7 field.
+#define BR_DMA_EEI_EEI7(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI7))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI7.
+#define BF_DMA_EEI_EEI7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI7), uint32_t) & BM_DMA_EEI_EEI7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI7 field to a new value.
+#define BW_DMA_EEI_EEI7(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI8[8] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ * interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ * an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI8 (8U) //!< Bit position for DMA_EEI_EEI8.
+#define BM_DMA_EEI_EEI8 (0x00000100U) //!< Bit mask for DMA_EEI_EEI8.
+#define BS_DMA_EEI_EEI8 (1U) //!< Bit field size in bits for DMA_EEI_EEI8.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI8 field.
+#define BR_DMA_EEI_EEI8(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI8))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI8.
+#define BF_DMA_EEI_EEI8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI8), uint32_t) & BM_DMA_EEI_EEI8)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI8 field to a new value.
+#define BW_DMA_EEI_EEI8(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI8) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI9[9] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ * interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ * an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI9 (9U) //!< Bit position for DMA_EEI_EEI9.
+#define BM_DMA_EEI_EEI9 (0x00000200U) //!< Bit mask for DMA_EEI_EEI9.
+#define BS_DMA_EEI_EEI9 (1U) //!< Bit field size in bits for DMA_EEI_EEI9.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI9 field.
+#define BR_DMA_EEI_EEI9(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI9))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI9.
+#define BF_DMA_EEI_EEI9(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI9), uint32_t) & BM_DMA_EEI_EEI9)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI9 field to a new value.
+#define BW_DMA_EEI_EEI9(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI9) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI10[10] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ * interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ * an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI10 (10U) //!< Bit position for DMA_EEI_EEI10.
+#define BM_DMA_EEI_EEI10 (0x00000400U) //!< Bit mask for DMA_EEI_EEI10.
+#define BS_DMA_EEI_EEI10 (1U) //!< Bit field size in bits for DMA_EEI_EEI10.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI10 field.
+#define BR_DMA_EEI_EEI10(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI10))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI10.
+#define BF_DMA_EEI_EEI10(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI10), uint32_t) & BM_DMA_EEI_EEI10)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI10 field to a new value.
+#define BW_DMA_EEI_EEI10(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI10) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI11[11] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ * interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ * an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI11 (11U) //!< Bit position for DMA_EEI_EEI11.
+#define BM_DMA_EEI_EEI11 (0x00000800U) //!< Bit mask for DMA_EEI_EEI11.
+#define BS_DMA_EEI_EEI11 (1U) //!< Bit field size in bits for DMA_EEI_EEI11.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI11 field.
+#define BR_DMA_EEI_EEI11(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI11))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI11.
+#define BF_DMA_EEI_EEI11(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI11), uint32_t) & BM_DMA_EEI_EEI11)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI11 field to a new value.
+#define BW_DMA_EEI_EEI11(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI11) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI12[12] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ * interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ * an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI12 (12U) //!< Bit position for DMA_EEI_EEI12.
+#define BM_DMA_EEI_EEI12 (0x00001000U) //!< Bit mask for DMA_EEI_EEI12.
+#define BS_DMA_EEI_EEI12 (1U) //!< Bit field size in bits for DMA_EEI_EEI12.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI12 field.
+#define BR_DMA_EEI_EEI12(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI12))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI12.
+#define BF_DMA_EEI_EEI12(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI12), uint32_t) & BM_DMA_EEI_EEI12)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI12 field to a new value.
+#define BW_DMA_EEI_EEI12(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI12) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI13[13] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ * interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ * an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI13 (13U) //!< Bit position for DMA_EEI_EEI13.
+#define BM_DMA_EEI_EEI13 (0x00002000U) //!< Bit mask for DMA_EEI_EEI13.
+#define BS_DMA_EEI_EEI13 (1U) //!< Bit field size in bits for DMA_EEI_EEI13.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI13 field.
+#define BR_DMA_EEI_EEI13(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI13))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI13.
+#define BF_DMA_EEI_EEI13(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI13), uint32_t) & BM_DMA_EEI_EEI13)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI13 field to a new value.
+#define BW_DMA_EEI_EEI13(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI13) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI14[14] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ * interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ * an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI14 (14U) //!< Bit position for DMA_EEI_EEI14.
+#define BM_DMA_EEI_EEI14 (0x00004000U) //!< Bit mask for DMA_EEI_EEI14.
+#define BS_DMA_EEI_EEI14 (1U) //!< Bit field size in bits for DMA_EEI_EEI14.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI14 field.
+#define BR_DMA_EEI_EEI14(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI14))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI14.
+#define BF_DMA_EEI_EEI14(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI14), uint32_t) & BM_DMA_EEI_EEI14)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI14 field to a new value.
+#define BW_DMA_EEI_EEI14(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI14) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_EEI, field EEI15[15] (RW)
+ *
+ * Values:
+ * - 0 - The error signal for corresponding channel does not generate an error
+ * interrupt
+ * - 1 - The assertion of the error signal for corresponding channel generates
+ * an error interrupt request
+ */
+//@{
+#define BP_DMA_EEI_EEI15 (15U) //!< Bit position for DMA_EEI_EEI15.
+#define BM_DMA_EEI_EEI15 (0x00008000U) //!< Bit mask for DMA_EEI_EEI15.
+#define BS_DMA_EEI_EEI15 (1U) //!< Bit field size in bits for DMA_EEI_EEI15.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_EEI_EEI15 field.
+#define BR_DMA_EEI_EEI15(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI15))
+#endif
+
+//! @brief Format value for bitfield DMA_EEI_EEI15.
+#define BF_DMA_EEI_EEI15(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI15), uint32_t) & BM_DMA_EEI_EEI15)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EEI15 field to a new value.
+#define BW_DMA_EEI_EEI15(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI15) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_CEEI - Clear Enable Error Interrupt Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_CEEI - Clear Enable Error Interrupt Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CEEI provides a simple memory-mapped mechanism to clear a given bit in
+ * the EEI to disable the error interrupt for a given channel. The data value on a
+ * register write causes the corresponding bit in the EEI to be cleared. Setting
+ * the CAEE bit provides a global clear function, forcing the EEI contents to be
+ * cleared, disabling all DMA request inputs. If the NOP bit is set, the command
+ * is ignored. This allows you to write multiple-byte registers as a 32-bit word.
+ * Reads of this register return all zeroes.
+ */
+typedef union _hw_dma_ceei
+{
+ uint8_t U;
+ struct _hw_dma_ceei_bitfields
+ {
+ uint8_t CEEI : 4; //!< [3:0] Clear Enable Error Interrupt
+ uint8_t RESERVED0 : 2; //!< [5:4]
+ uint8_t CAEE : 1; //!< [6] Clear All Enable Error Interrupts
+ uint8_t NOP : 1; //!< [7] No Op enable
+ } B;
+} hw_dma_ceei_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_CEEI register
+ */
+//@{
+#define HW_DMA_CEEI_ADDR(x) (REGS_DMA_BASE(x) + 0x18U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_CEEI(x) (*(__O hw_dma_ceei_t *) HW_DMA_CEEI_ADDR(x))
+#define HW_DMA_CEEI_RD(x) (HW_DMA_CEEI(x).U)
+#define HW_DMA_CEEI_WR(x, v) (HW_DMA_CEEI(x).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_CEEI bitfields
+ */
+
+/*!
+ * @name Register DMA_CEEI, field CEEI[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in EEI
+ */
+//@{
+#define BP_DMA_CEEI_CEEI (0U) //!< Bit position for DMA_CEEI_CEEI.
+#define BM_DMA_CEEI_CEEI (0x0FU) //!< Bit mask for DMA_CEEI_CEEI.
+#define BS_DMA_CEEI_CEEI (4U) //!< Bit field size in bits for DMA_CEEI_CEEI.
+
+//! @brief Format value for bitfield DMA_CEEI_CEEI.
+#define BF_DMA_CEEI_CEEI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CEEI_CEEI), uint8_t) & BM_DMA_CEEI_CEEI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CEEI field to a new value.
+#define BW_DMA_CEEI_CEEI(x, v) (HW_DMA_CEEI_WR(x, (HW_DMA_CEEI_RD(x) & ~BM_DMA_CEEI_CEEI) | BF_DMA_CEEI_CEEI(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CEEI, field CAEE[6] (WORZ)
+ *
+ * Values:
+ * - 0 - Clear only the EEI bit specified in the CEEI field
+ * - 1 - Clear all bits in EEI
+ */
+//@{
+#define BP_DMA_CEEI_CAEE (6U) //!< Bit position for DMA_CEEI_CAEE.
+#define BM_DMA_CEEI_CAEE (0x40U) //!< Bit mask for DMA_CEEI_CAEE.
+#define BS_DMA_CEEI_CAEE (1U) //!< Bit field size in bits for DMA_CEEI_CAEE.
+
+//! @brief Format value for bitfield DMA_CEEI_CAEE.
+#define BF_DMA_CEEI_CAEE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CEEI_CAEE), uint8_t) & BM_DMA_CEEI_CAEE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CAEE field to a new value.
+#define BW_DMA_CEEI_CAEE(x, v) (BITBAND_ACCESS8(HW_DMA_CEEI_ADDR(x), BP_DMA_CEEI_CAEE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CEEI, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0 - Normal operation
+ * - 1 - No operation, ignore the other bits in this register
+ */
+//@{
+#define BP_DMA_CEEI_NOP (7U) //!< Bit position for DMA_CEEI_NOP.
+#define BM_DMA_CEEI_NOP (0x80U) //!< Bit mask for DMA_CEEI_NOP.
+#define BS_DMA_CEEI_NOP (1U) //!< Bit field size in bits for DMA_CEEI_NOP.
+
+//! @brief Format value for bitfield DMA_CEEI_NOP.
+#define BF_DMA_CEEI_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CEEI_NOP), uint8_t) & BM_DMA_CEEI_NOP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NOP field to a new value.
+#define BW_DMA_CEEI_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CEEI_ADDR(x), BP_DMA_CEEI_NOP) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_SEEI - Set Enable Error Interrupt Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_SEEI - Set Enable Error Interrupt Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The SEEI provides a simple memory-mapped mechanism to set a given bit in the
+ * EEI to enable the error interrupt for a given channel. The data value on a
+ * register write causes the corresponding bit in the EEI to be set. Setting the
+ * SAEE bit provides a global set function, forcing the entire EEI contents to be
+ * set. If the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all
+ * zeroes.
+ */
+typedef union _hw_dma_seei
+{
+ uint8_t U;
+ struct _hw_dma_seei_bitfields
+ {
+ uint8_t SEEI : 4; //!< [3:0] Set Enable Error Interrupt
+ uint8_t RESERVED0 : 2; //!< [5:4]
+ uint8_t SAEE : 1; //!< [6] Sets All Enable Error Interrupts
+ uint8_t NOP : 1; //!< [7] No Op enable
+ } B;
+} hw_dma_seei_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_SEEI register
+ */
+//@{
+#define HW_DMA_SEEI_ADDR(x) (REGS_DMA_BASE(x) + 0x19U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_SEEI(x) (*(__O hw_dma_seei_t *) HW_DMA_SEEI_ADDR(x))
+#define HW_DMA_SEEI_RD(x) (HW_DMA_SEEI(x).U)
+#define HW_DMA_SEEI_WR(x, v) (HW_DMA_SEEI(x).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_SEEI bitfields
+ */
+
+/*!
+ * @name Register DMA_SEEI, field SEEI[3:0] (WORZ)
+ *
+ * Sets the corresponding bit in EEI
+ */
+//@{
+#define BP_DMA_SEEI_SEEI (0U) //!< Bit position for DMA_SEEI_SEEI.
+#define BM_DMA_SEEI_SEEI (0x0FU) //!< Bit mask for DMA_SEEI_SEEI.
+#define BS_DMA_SEEI_SEEI (4U) //!< Bit field size in bits for DMA_SEEI_SEEI.
+
+//! @brief Format value for bitfield DMA_SEEI_SEEI.
+#define BF_DMA_SEEI_SEEI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SEEI_SEEI), uint8_t) & BM_DMA_SEEI_SEEI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SEEI field to a new value.
+#define BW_DMA_SEEI_SEEI(x, v) (HW_DMA_SEEI_WR(x, (HW_DMA_SEEI_RD(x) & ~BM_DMA_SEEI_SEEI) | BF_DMA_SEEI_SEEI(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_SEEI, field SAEE[6] (WORZ)
+ *
+ * Values:
+ * - 0 - Set only the EEI bit specified in the SEEI field.
+ * - 1 - Sets all bits in EEI
+ */
+//@{
+#define BP_DMA_SEEI_SAEE (6U) //!< Bit position for DMA_SEEI_SAEE.
+#define BM_DMA_SEEI_SAEE (0x40U) //!< Bit mask for DMA_SEEI_SAEE.
+#define BS_DMA_SEEI_SAEE (1U) //!< Bit field size in bits for DMA_SEEI_SAEE.
+
+//! @brief Format value for bitfield DMA_SEEI_SAEE.
+#define BF_DMA_SEEI_SAEE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SEEI_SAEE), uint8_t) & BM_DMA_SEEI_SAEE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SAEE field to a new value.
+#define BW_DMA_SEEI_SAEE(x, v) (BITBAND_ACCESS8(HW_DMA_SEEI_ADDR(x), BP_DMA_SEEI_SAEE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_SEEI, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0 - Normal operation
+ * - 1 - No operation, ignore the other bits in this register
+ */
+//@{
+#define BP_DMA_SEEI_NOP (7U) //!< Bit position for DMA_SEEI_NOP.
+#define BM_DMA_SEEI_NOP (0x80U) //!< Bit mask for DMA_SEEI_NOP.
+#define BS_DMA_SEEI_NOP (1U) //!< Bit field size in bits for DMA_SEEI_NOP.
+
+//! @brief Format value for bitfield DMA_SEEI_NOP.
+#define BF_DMA_SEEI_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SEEI_NOP), uint8_t) & BM_DMA_SEEI_NOP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NOP field to a new value.
+#define BW_DMA_SEEI_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SEEI_ADDR(x), BP_DMA_SEEI_NOP) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_CERQ - Clear Enable Request Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_CERQ - Clear Enable Request Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CERQ provides a simple memory-mapped mechanism to clear a given bit in
+ * the ERQ to disable the DMA request for a given channel. The data value on a
+ * register write causes the corresponding bit in the ERQ to be cleared. Setting the
+ * CAER bit provides a global clear function, forcing the entire contents of the
+ * ERQ to be cleared, disabling all DMA request inputs. If NOP is set, the
+ * command is ignored. This allows you to write multiple-byte registers as a 32-bit
+ * word. Reads of this register return all zeroes.
+ */
+typedef union _hw_dma_cerq
+{
+ uint8_t U;
+ struct _hw_dma_cerq_bitfields
+ {
+ uint8_t CERQ : 4; //!< [3:0] Clear Enable Request
+ uint8_t RESERVED0 : 2; //!< [5:4]
+ uint8_t CAER : 1; //!< [6] Clear All Enable Requests
+ uint8_t NOP : 1; //!< [7] No Op enable
+ } B;
+} hw_dma_cerq_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_CERQ register
+ */
+//@{
+#define HW_DMA_CERQ_ADDR(x) (REGS_DMA_BASE(x) + 0x1AU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_CERQ(x) (*(__O hw_dma_cerq_t *) HW_DMA_CERQ_ADDR(x))
+#define HW_DMA_CERQ_RD(x) (HW_DMA_CERQ(x).U)
+#define HW_DMA_CERQ_WR(x, v) (HW_DMA_CERQ(x).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_CERQ bitfields
+ */
+
+/*!
+ * @name Register DMA_CERQ, field CERQ[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in ERQ
+ */
+//@{
+#define BP_DMA_CERQ_CERQ (0U) //!< Bit position for DMA_CERQ_CERQ.
+#define BM_DMA_CERQ_CERQ (0x0FU) //!< Bit mask for DMA_CERQ_CERQ.
+#define BS_DMA_CERQ_CERQ (4U) //!< Bit field size in bits for DMA_CERQ_CERQ.
+
+//! @brief Format value for bitfield DMA_CERQ_CERQ.
+#define BF_DMA_CERQ_CERQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERQ_CERQ), uint8_t) & BM_DMA_CERQ_CERQ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CERQ field to a new value.
+#define BW_DMA_CERQ_CERQ(x, v) (HW_DMA_CERQ_WR(x, (HW_DMA_CERQ_RD(x) & ~BM_DMA_CERQ_CERQ) | BF_DMA_CERQ_CERQ(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CERQ, field CAER[6] (WORZ)
+ *
+ * Values:
+ * - 0 - Clear only the ERQ bit specified in the CERQ field
+ * - 1 - Clear all bits in ERQ
+ */
+//@{
+#define BP_DMA_CERQ_CAER (6U) //!< Bit position for DMA_CERQ_CAER.
+#define BM_DMA_CERQ_CAER (0x40U) //!< Bit mask for DMA_CERQ_CAER.
+#define BS_DMA_CERQ_CAER (1U) //!< Bit field size in bits for DMA_CERQ_CAER.
+
+//! @brief Format value for bitfield DMA_CERQ_CAER.
+#define BF_DMA_CERQ_CAER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERQ_CAER), uint8_t) & BM_DMA_CERQ_CAER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CAER field to a new value.
+#define BW_DMA_CERQ_CAER(x, v) (BITBAND_ACCESS8(HW_DMA_CERQ_ADDR(x), BP_DMA_CERQ_CAER) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CERQ, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0 - Normal operation
+ * - 1 - No operation, ignore the other bits in this register
+ */
+//@{
+#define BP_DMA_CERQ_NOP (7U) //!< Bit position for DMA_CERQ_NOP.
+#define BM_DMA_CERQ_NOP (0x80U) //!< Bit mask for DMA_CERQ_NOP.
+#define BS_DMA_CERQ_NOP (1U) //!< Bit field size in bits for DMA_CERQ_NOP.
+
+//! @brief Format value for bitfield DMA_CERQ_NOP.
+#define BF_DMA_CERQ_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERQ_NOP), uint8_t) & BM_DMA_CERQ_NOP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NOP field to a new value.
+#define BW_DMA_CERQ_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CERQ_ADDR(x), BP_DMA_CERQ_NOP) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_SERQ - Set Enable Request Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_SERQ - Set Enable Request Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The SERQ provides a simple memory-mapped mechanism to set a given bit in the
+ * ERQ to enable the DMA request for a given channel. The data value on a
+ * register write causes the corresponding bit in the ERQ to be set. Setting the SAER
+ * bit provides a global set function, forcing the entire contents of ERQ to be
+ * set. If the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
+ */
+typedef union _hw_dma_serq
+{
+ uint8_t U;
+ struct _hw_dma_serq_bitfields
+ {
+ uint8_t SERQ : 4; //!< [3:0] Set enable request
+ uint8_t RESERVED0 : 2; //!< [5:4]
+ uint8_t SAER : 1; //!< [6] Set All Enable Requests
+ uint8_t NOP : 1; //!< [7] No Op enable
+ } B;
+} hw_dma_serq_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_SERQ register
+ */
+//@{
+#define HW_DMA_SERQ_ADDR(x) (REGS_DMA_BASE(x) + 0x1BU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_SERQ(x) (*(__O hw_dma_serq_t *) HW_DMA_SERQ_ADDR(x))
+#define HW_DMA_SERQ_RD(x) (HW_DMA_SERQ(x).U)
+#define HW_DMA_SERQ_WR(x, v) (HW_DMA_SERQ(x).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_SERQ bitfields
+ */
+
+/*!
+ * @name Register DMA_SERQ, field SERQ[3:0] (WORZ)
+ *
+ * Sets the corresponding bit in ERQ
+ */
+//@{
+#define BP_DMA_SERQ_SERQ (0U) //!< Bit position for DMA_SERQ_SERQ.
+#define BM_DMA_SERQ_SERQ (0x0FU) //!< Bit mask for DMA_SERQ_SERQ.
+#define BS_DMA_SERQ_SERQ (4U) //!< Bit field size in bits for DMA_SERQ_SERQ.
+
+//! @brief Format value for bitfield DMA_SERQ_SERQ.
+#define BF_DMA_SERQ_SERQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SERQ_SERQ), uint8_t) & BM_DMA_SERQ_SERQ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SERQ field to a new value.
+#define BW_DMA_SERQ_SERQ(x, v) (HW_DMA_SERQ_WR(x, (HW_DMA_SERQ_RD(x) & ~BM_DMA_SERQ_SERQ) | BF_DMA_SERQ_SERQ(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_SERQ, field SAER[6] (WORZ)
+ *
+ * Values:
+ * - 0 - Set only the ERQ bit specified in the SERQ field
+ * - 1 - Set all bits in ERQ
+ */
+//@{
+#define BP_DMA_SERQ_SAER (6U) //!< Bit position for DMA_SERQ_SAER.
+#define BM_DMA_SERQ_SAER (0x40U) //!< Bit mask for DMA_SERQ_SAER.
+#define BS_DMA_SERQ_SAER (1U) //!< Bit field size in bits for DMA_SERQ_SAER.
+
+//! @brief Format value for bitfield DMA_SERQ_SAER.
+#define BF_DMA_SERQ_SAER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SERQ_SAER), uint8_t) & BM_DMA_SERQ_SAER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SAER field to a new value.
+#define BW_DMA_SERQ_SAER(x, v) (BITBAND_ACCESS8(HW_DMA_SERQ_ADDR(x), BP_DMA_SERQ_SAER) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_SERQ, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0 - Normal operation
+ * - 1 - No operation, ignore the other bits in this register
+ */
+//@{
+#define BP_DMA_SERQ_NOP (7U) //!< Bit position for DMA_SERQ_NOP.
+#define BM_DMA_SERQ_NOP (0x80U) //!< Bit mask for DMA_SERQ_NOP.
+#define BS_DMA_SERQ_NOP (1U) //!< Bit field size in bits for DMA_SERQ_NOP.
+
+//! @brief Format value for bitfield DMA_SERQ_NOP.
+#define BF_DMA_SERQ_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SERQ_NOP), uint8_t) & BM_DMA_SERQ_NOP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NOP field to a new value.
+#define BW_DMA_SERQ_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SERQ_ADDR(x), BP_DMA_SERQ_NOP) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_CDNE - Clear DONE Status Bit Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_CDNE - Clear DONE Status Bit Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in
+ * the TCD of the given channel. The data value on a register write causes the
+ * DONE bit in the corresponding transfer control descriptor to be cleared. Setting
+ * the CADN bit provides a global clear function, forcing all DONE bits to be
+ * cleared. If the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all
+ * zeroes.
+ */
+typedef union _hw_dma_cdne
+{
+ uint8_t U;
+ struct _hw_dma_cdne_bitfields
+ {
+ uint8_t CDNE : 4; //!< [3:0] Clear DONE Bit
+ uint8_t RESERVED0 : 2; //!< [5:4]
+ uint8_t CADN : 1; //!< [6] Clears All DONE Bits
+ uint8_t NOP : 1; //!< [7] No Op enable
+ } B;
+} hw_dma_cdne_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_CDNE register
+ */
+//@{
+#define HW_DMA_CDNE_ADDR(x) (REGS_DMA_BASE(x) + 0x1CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_CDNE(x) (*(__O hw_dma_cdne_t *) HW_DMA_CDNE_ADDR(x))
+#define HW_DMA_CDNE_RD(x) (HW_DMA_CDNE(x).U)
+#define HW_DMA_CDNE_WR(x, v) (HW_DMA_CDNE(x).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_CDNE bitfields
+ */
+
+/*!
+ * @name Register DMA_CDNE, field CDNE[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in TCDn_CSR[DONE]
+ */
+//@{
+#define BP_DMA_CDNE_CDNE (0U) //!< Bit position for DMA_CDNE_CDNE.
+#define BM_DMA_CDNE_CDNE (0x0FU) //!< Bit mask for DMA_CDNE_CDNE.
+#define BS_DMA_CDNE_CDNE (4U) //!< Bit field size in bits for DMA_CDNE_CDNE.
+
+//! @brief Format value for bitfield DMA_CDNE_CDNE.
+#define BF_DMA_CDNE_CDNE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CDNE_CDNE), uint8_t) & BM_DMA_CDNE_CDNE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CDNE field to a new value.
+#define BW_DMA_CDNE_CDNE(x, v) (HW_DMA_CDNE_WR(x, (HW_DMA_CDNE_RD(x) & ~BM_DMA_CDNE_CDNE) | BF_DMA_CDNE_CDNE(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CDNE, field CADN[6] (WORZ)
+ *
+ * Values:
+ * - 0 - Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
+ * - 1 - Clears all bits in TCDn_CSR[DONE]
+ */
+//@{
+#define BP_DMA_CDNE_CADN (6U) //!< Bit position for DMA_CDNE_CADN.
+#define BM_DMA_CDNE_CADN (0x40U) //!< Bit mask for DMA_CDNE_CADN.
+#define BS_DMA_CDNE_CADN (1U) //!< Bit field size in bits for DMA_CDNE_CADN.
+
+//! @brief Format value for bitfield DMA_CDNE_CADN.
+#define BF_DMA_CDNE_CADN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CDNE_CADN), uint8_t) & BM_DMA_CDNE_CADN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CADN field to a new value.
+#define BW_DMA_CDNE_CADN(x, v) (BITBAND_ACCESS8(HW_DMA_CDNE_ADDR(x), BP_DMA_CDNE_CADN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CDNE, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0 - Normal operation
+ * - 1 - No operation, ignore the other bits in this register
+ */
+//@{
+#define BP_DMA_CDNE_NOP (7U) //!< Bit position for DMA_CDNE_NOP.
+#define BM_DMA_CDNE_NOP (0x80U) //!< Bit mask for DMA_CDNE_NOP.
+#define BS_DMA_CDNE_NOP (1U) //!< Bit field size in bits for DMA_CDNE_NOP.
+
+//! @brief Format value for bitfield DMA_CDNE_NOP.
+#define BF_DMA_CDNE_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CDNE_NOP), uint8_t) & BM_DMA_CDNE_NOP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NOP field to a new value.
+#define BW_DMA_CDNE_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CDNE_ADDR(x), BP_DMA_CDNE_NOP) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_SSRT - Set START Bit Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_SSRT - Set START Bit Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The SSRT provides a simple memory-mapped mechanism to set the START bit in
+ * the TCD of the given channel. The data value on a register write causes the
+ * START bit in the corresponding transfer control descriptor to be set. Setting the
+ * SAST bit provides a global set function, forcing all START bits to be set. If
+ * the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
+ */
+typedef union _hw_dma_ssrt
+{
+ uint8_t U;
+ struct _hw_dma_ssrt_bitfields
+ {
+ uint8_t SSRT : 4; //!< [3:0] Set START Bit
+ uint8_t RESERVED0 : 2; //!< [5:4]
+ uint8_t SAST : 1; //!< [6] Set All START Bits (activates all channels)
+ uint8_t NOP : 1; //!< [7] No Op enable
+ } B;
+} hw_dma_ssrt_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_SSRT register
+ */
+//@{
+#define HW_DMA_SSRT_ADDR(x) (REGS_DMA_BASE(x) + 0x1DU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_SSRT(x) (*(__O hw_dma_ssrt_t *) HW_DMA_SSRT_ADDR(x))
+#define HW_DMA_SSRT_RD(x) (HW_DMA_SSRT(x).U)
+#define HW_DMA_SSRT_WR(x, v) (HW_DMA_SSRT(x).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_SSRT bitfields
+ */
+
+/*!
+ * @name Register DMA_SSRT, field SSRT[3:0] (WORZ)
+ *
+ * Sets the corresponding bit in TCDn_CSR[START]
+ */
+//@{
+#define BP_DMA_SSRT_SSRT (0U) //!< Bit position for DMA_SSRT_SSRT.
+#define BM_DMA_SSRT_SSRT (0x0FU) //!< Bit mask for DMA_SSRT_SSRT.
+#define BS_DMA_SSRT_SSRT (4U) //!< Bit field size in bits for DMA_SSRT_SSRT.
+
+//! @brief Format value for bitfield DMA_SSRT_SSRT.
+#define BF_DMA_SSRT_SSRT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SSRT_SSRT), uint8_t) & BM_DMA_SSRT_SSRT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SSRT field to a new value.
+#define BW_DMA_SSRT_SSRT(x, v) (HW_DMA_SSRT_WR(x, (HW_DMA_SSRT_RD(x) & ~BM_DMA_SSRT_SSRT) | BF_DMA_SSRT_SSRT(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_SSRT, field SAST[6] (WORZ)
+ *
+ * Values:
+ * - 0 - Set only the TCDn_CSR[START] bit specified in the SSRT field
+ * - 1 - Set all bits in TCDn_CSR[START]
+ */
+//@{
+#define BP_DMA_SSRT_SAST (6U) //!< Bit position for DMA_SSRT_SAST.
+#define BM_DMA_SSRT_SAST (0x40U) //!< Bit mask for DMA_SSRT_SAST.
+#define BS_DMA_SSRT_SAST (1U) //!< Bit field size in bits for DMA_SSRT_SAST.
+
+//! @brief Format value for bitfield DMA_SSRT_SAST.
+#define BF_DMA_SSRT_SAST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SSRT_SAST), uint8_t) & BM_DMA_SSRT_SAST)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SAST field to a new value.
+#define BW_DMA_SSRT_SAST(x, v) (BITBAND_ACCESS8(HW_DMA_SSRT_ADDR(x), BP_DMA_SSRT_SAST) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_SSRT, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0 - Normal operation
+ * - 1 - No operation, ignore the other bits in this register
+ */
+//@{
+#define BP_DMA_SSRT_NOP (7U) //!< Bit position for DMA_SSRT_NOP.
+#define BM_DMA_SSRT_NOP (0x80U) //!< Bit mask for DMA_SSRT_NOP.
+#define BS_DMA_SSRT_NOP (1U) //!< Bit field size in bits for DMA_SSRT_NOP.
+
+//! @brief Format value for bitfield DMA_SSRT_NOP.
+#define BF_DMA_SSRT_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SSRT_NOP), uint8_t) & BM_DMA_SSRT_NOP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NOP field to a new value.
+#define BW_DMA_SSRT_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SSRT_ADDR(x), BP_DMA_SSRT_NOP) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_CERR - Clear Error Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_CERR - Clear Error Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CERR provides a simple memory-mapped mechanism to clear a given bit in
+ * the ERR to disable the error condition flag for a given channel. The given value
+ * on a register write causes the corresponding bit in the ERR to be cleared.
+ * Setting the CAEI bit provides a global clear function, forcing the ERR contents
+ * to be cleared, clearing all channel error indicators. If the NOP bit is set,
+ * the command is ignored. This allows you to write multiple-byte registers as a
+ * 32-bit word. Reads of this register return all zeroes.
+ */
+typedef union _hw_dma_cerr
+{
+ uint8_t U;
+ struct _hw_dma_cerr_bitfields
+ {
+ uint8_t CERR : 4; //!< [3:0] Clear Error Indicator
+ uint8_t RESERVED0 : 2; //!< [5:4]
+ uint8_t CAEI : 1; //!< [6] Clear All Error Indicators
+ uint8_t NOP : 1; //!< [7] No Op enable
+ } B;
+} hw_dma_cerr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_CERR register
+ */
+//@{
+#define HW_DMA_CERR_ADDR(x) (REGS_DMA_BASE(x) + 0x1EU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_CERR(x) (*(__O hw_dma_cerr_t *) HW_DMA_CERR_ADDR(x))
+#define HW_DMA_CERR_RD(x) (HW_DMA_CERR(x).U)
+#define HW_DMA_CERR_WR(x, v) (HW_DMA_CERR(x).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_CERR bitfields
+ */
+
+/*!
+ * @name Register DMA_CERR, field CERR[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in ERR
+ */
+//@{
+#define BP_DMA_CERR_CERR (0U) //!< Bit position for DMA_CERR_CERR.
+#define BM_DMA_CERR_CERR (0x0FU) //!< Bit mask for DMA_CERR_CERR.
+#define BS_DMA_CERR_CERR (4U) //!< Bit field size in bits for DMA_CERR_CERR.
+
+//! @brief Format value for bitfield DMA_CERR_CERR.
+#define BF_DMA_CERR_CERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERR_CERR), uint8_t) & BM_DMA_CERR_CERR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CERR field to a new value.
+#define BW_DMA_CERR_CERR(x, v) (HW_DMA_CERR_WR(x, (HW_DMA_CERR_RD(x) & ~BM_DMA_CERR_CERR) | BF_DMA_CERR_CERR(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CERR, field CAEI[6] (WORZ)
+ *
+ * Values:
+ * - 0 - Clear only the ERR bit specified in the CERR field
+ * - 1 - Clear all bits in ERR
+ */
+//@{
+#define BP_DMA_CERR_CAEI (6U) //!< Bit position for DMA_CERR_CAEI.
+#define BM_DMA_CERR_CAEI (0x40U) //!< Bit mask for DMA_CERR_CAEI.
+#define BS_DMA_CERR_CAEI (1U) //!< Bit field size in bits for DMA_CERR_CAEI.
+
+//! @brief Format value for bitfield DMA_CERR_CAEI.
+#define BF_DMA_CERR_CAEI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERR_CAEI), uint8_t) & BM_DMA_CERR_CAEI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CAEI field to a new value.
+#define BW_DMA_CERR_CAEI(x, v) (BITBAND_ACCESS8(HW_DMA_CERR_ADDR(x), BP_DMA_CERR_CAEI) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CERR, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0 - Normal operation
+ * - 1 - No operation, ignore the other bits in this register
+ */
+//@{
+#define BP_DMA_CERR_NOP (7U) //!< Bit position for DMA_CERR_NOP.
+#define BM_DMA_CERR_NOP (0x80U) //!< Bit mask for DMA_CERR_NOP.
+#define BS_DMA_CERR_NOP (1U) //!< Bit field size in bits for DMA_CERR_NOP.
+
+//! @brief Format value for bitfield DMA_CERR_NOP.
+#define BF_DMA_CERR_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERR_NOP), uint8_t) & BM_DMA_CERR_NOP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NOP field to a new value.
+#define BW_DMA_CERR_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CERR_ADDR(x), BP_DMA_CERR_NOP) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_CINT - Clear Interrupt Request Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_CINT - Clear Interrupt Request Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CINT provides a simple, memory-mapped mechanism to clear a given bit in
+ * the INT to disable the interrupt request for a given channel. The given value
+ * on a register write causes the corresponding bit in the INT to be cleared.
+ * Setting the CAIR bit provides a global clear function, forcing the entire contents
+ * of the INT to be cleared, disabling all DMA interrupt requests. If the NOP
+ * bit is set, the command is ignored. This allows you to write multiple-byte
+ * registers as a 32-bit word. Reads of this register return all zeroes.
+ */
+typedef union _hw_dma_cint
+{
+ uint8_t U;
+ struct _hw_dma_cint_bitfields
+ {
+ uint8_t CINT : 4; //!< [3:0] Clear Interrupt Request
+ uint8_t RESERVED0 : 2; //!< [5:4]
+ uint8_t CAIR : 1; //!< [6] Clear All Interrupt Requests
+ uint8_t NOP : 1; //!< [7] No Op enable
+ } B;
+} hw_dma_cint_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_CINT register
+ */
+//@{
+#define HW_DMA_CINT_ADDR(x) (REGS_DMA_BASE(x) + 0x1FU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_CINT(x) (*(__O hw_dma_cint_t *) HW_DMA_CINT_ADDR(x))
+#define HW_DMA_CINT_RD(x) (HW_DMA_CINT(x).U)
+#define HW_DMA_CINT_WR(x, v) (HW_DMA_CINT(x).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_CINT bitfields
+ */
+
+/*!
+ * @name Register DMA_CINT, field CINT[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in INT
+ */
+//@{
+#define BP_DMA_CINT_CINT (0U) //!< Bit position for DMA_CINT_CINT.
+#define BM_DMA_CINT_CINT (0x0FU) //!< Bit mask for DMA_CINT_CINT.
+#define BS_DMA_CINT_CINT (4U) //!< Bit field size in bits for DMA_CINT_CINT.
+
+//! @brief Format value for bitfield DMA_CINT_CINT.
+#define BF_DMA_CINT_CINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CINT_CINT), uint8_t) & BM_DMA_CINT_CINT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CINT field to a new value.
+#define BW_DMA_CINT_CINT(x, v) (HW_DMA_CINT_WR(x, (HW_DMA_CINT_RD(x) & ~BM_DMA_CINT_CINT) | BF_DMA_CINT_CINT(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CINT, field CAIR[6] (WORZ)
+ *
+ * Values:
+ * - 0 - Clear only the INT bit specified in the CINT field
+ * - 1 - Clear all bits in INT
+ */
+//@{
+#define BP_DMA_CINT_CAIR (6U) //!< Bit position for DMA_CINT_CAIR.
+#define BM_DMA_CINT_CAIR (0x40U) //!< Bit mask for DMA_CINT_CAIR.
+#define BS_DMA_CINT_CAIR (1U) //!< Bit field size in bits for DMA_CINT_CAIR.
+
+//! @brief Format value for bitfield DMA_CINT_CAIR.
+#define BF_DMA_CINT_CAIR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CINT_CAIR), uint8_t) & BM_DMA_CINT_CAIR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CAIR field to a new value.
+#define BW_DMA_CINT_CAIR(x, v) (BITBAND_ACCESS8(HW_DMA_CINT_ADDR(x), BP_DMA_CINT_CAIR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_CINT, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0 - Normal operation
+ * - 1 - No operation, ignore the other bits in this register
+ */
+//@{
+#define BP_DMA_CINT_NOP (7U) //!< Bit position for DMA_CINT_NOP.
+#define BM_DMA_CINT_NOP (0x80U) //!< Bit mask for DMA_CINT_NOP.
+#define BS_DMA_CINT_NOP (1U) //!< Bit field size in bits for DMA_CINT_NOP.
+
+//! @brief Format value for bitfield DMA_CINT_NOP.
+#define BF_DMA_CINT_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CINT_NOP), uint8_t) & BM_DMA_CINT_NOP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NOP field to a new value.
+#define BW_DMA_CINT_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CINT_ADDR(x), BP_DMA_CINT_NOP) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_INT - Interrupt Request Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_INT - Interrupt Request Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The INT register provides a bit map for the 16 channels signaling the
+ * presence of an interrupt request for each channel. Depending on the appropriate bit
+ * setting in the transfer-control descriptors, the eDMA engine generates an
+ * interrupt on data transfer completion. The outputs of this register are directly
+ * routed to the interrupt controller (INTC). During the interrupt-service routine
+ * associated with any given channel, it is the software's responsibility to
+ * clear the appropriate bit, negating the interrupt request. Typically, a write to
+ * the CINT register in the interrupt service routine is used for this purpose.
+ * The state of any given channel's interrupt request is directly affected by
+ * writes to this register; it is also affected by writes to the CINT register. On
+ * writes to INT, a 1 in any bit position clears the corresponding channel's
+ * interrupt request. A zero in any bit position has no affect on the corresponding
+ * channel's current interrupt status. The CINT register is provided so the interrupt
+ * request for a single channel can easily be cleared without the need to
+ * perform a read-modify-write sequence to the INT register.
+ */
+typedef union _hw_dma_int
+{
+ uint32_t U;
+ struct _hw_dma_int_bitfields
+ {
+ uint32_t INT0 : 1; //!< [0] Interrupt Request 0
+ uint32_t INT1 : 1; //!< [1] Interrupt Request 1
+ uint32_t INT2 : 1; //!< [2] Interrupt Request 2
+ uint32_t INT3 : 1; //!< [3] Interrupt Request 3
+ uint32_t INT4 : 1; //!< [4] Interrupt Request 4
+ uint32_t INT5 : 1; //!< [5] Interrupt Request 5
+ uint32_t INT6 : 1; //!< [6] Interrupt Request 6
+ uint32_t INT7 : 1; //!< [7] Interrupt Request 7
+ uint32_t INT8 : 1; //!< [8] Interrupt Request 8
+ uint32_t INT9 : 1; //!< [9] Interrupt Request 9
+ uint32_t INT10 : 1; //!< [10] Interrupt Request 10
+ uint32_t INT11 : 1; //!< [11] Interrupt Request 11
+ uint32_t INT12 : 1; //!< [12] Interrupt Request 12
+ uint32_t INT13 : 1; //!< [13] Interrupt Request 13
+ uint32_t INT14 : 1; //!< [14] Interrupt Request 14
+ uint32_t INT15 : 1; //!< [15] Interrupt Request 15
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_dma_int_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_INT register
+ */
+//@{
+#define HW_DMA_INT_ADDR(x) (REGS_DMA_BASE(x) + 0x24U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_INT(x) (*(__IO hw_dma_int_t *) HW_DMA_INT_ADDR(x))
+#define HW_DMA_INT_RD(x) (HW_DMA_INT(x).U)
+#define HW_DMA_INT_WR(x, v) (HW_DMA_INT(x).U = (v))
+#define HW_DMA_INT_SET(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) | (v)))
+#define HW_DMA_INT_CLR(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) & ~(v)))
+#define HW_DMA_INT_TOG(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_INT bitfields
+ */
+
+/*!
+ * @name Register DMA_INT, field INT0[0] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT0 (0U) //!< Bit position for DMA_INT_INT0.
+#define BM_DMA_INT_INT0 (0x00000001U) //!< Bit mask for DMA_INT_INT0.
+#define BS_DMA_INT_INT0 (1U) //!< Bit field size in bits for DMA_INT_INT0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT0 field.
+#define BR_DMA_INT_INT0(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT0))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT0.
+#define BF_DMA_INT_INT0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT0), uint32_t) & BM_DMA_INT_INT0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT0 field to a new value.
+#define BW_DMA_INT_INT0(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT1[1] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT1 (1U) //!< Bit position for DMA_INT_INT1.
+#define BM_DMA_INT_INT1 (0x00000002U) //!< Bit mask for DMA_INT_INT1.
+#define BS_DMA_INT_INT1 (1U) //!< Bit field size in bits for DMA_INT_INT1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT1 field.
+#define BR_DMA_INT_INT1(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT1))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT1.
+#define BF_DMA_INT_INT1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT1), uint32_t) & BM_DMA_INT_INT1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT1 field to a new value.
+#define BW_DMA_INT_INT1(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT2[2] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT2 (2U) //!< Bit position for DMA_INT_INT2.
+#define BM_DMA_INT_INT2 (0x00000004U) //!< Bit mask for DMA_INT_INT2.
+#define BS_DMA_INT_INT2 (1U) //!< Bit field size in bits for DMA_INT_INT2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT2 field.
+#define BR_DMA_INT_INT2(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT2))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT2.
+#define BF_DMA_INT_INT2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT2), uint32_t) & BM_DMA_INT_INT2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT2 field to a new value.
+#define BW_DMA_INT_INT2(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT3[3] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT3 (3U) //!< Bit position for DMA_INT_INT3.
+#define BM_DMA_INT_INT3 (0x00000008U) //!< Bit mask for DMA_INT_INT3.
+#define BS_DMA_INT_INT3 (1U) //!< Bit field size in bits for DMA_INT_INT3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT3 field.
+#define BR_DMA_INT_INT3(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT3))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT3.
+#define BF_DMA_INT_INT3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT3), uint32_t) & BM_DMA_INT_INT3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT3 field to a new value.
+#define BW_DMA_INT_INT3(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT4[4] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT4 (4U) //!< Bit position for DMA_INT_INT4.
+#define BM_DMA_INT_INT4 (0x00000010U) //!< Bit mask for DMA_INT_INT4.
+#define BS_DMA_INT_INT4 (1U) //!< Bit field size in bits for DMA_INT_INT4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT4 field.
+#define BR_DMA_INT_INT4(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT4))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT4.
+#define BF_DMA_INT_INT4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT4), uint32_t) & BM_DMA_INT_INT4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT4 field to a new value.
+#define BW_DMA_INT_INT4(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT5[5] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT5 (5U) //!< Bit position for DMA_INT_INT5.
+#define BM_DMA_INT_INT5 (0x00000020U) //!< Bit mask for DMA_INT_INT5.
+#define BS_DMA_INT_INT5 (1U) //!< Bit field size in bits for DMA_INT_INT5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT5 field.
+#define BR_DMA_INT_INT5(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT5))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT5.
+#define BF_DMA_INT_INT5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT5), uint32_t) & BM_DMA_INT_INT5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT5 field to a new value.
+#define BW_DMA_INT_INT5(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT6[6] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT6 (6U) //!< Bit position for DMA_INT_INT6.
+#define BM_DMA_INT_INT6 (0x00000040U) //!< Bit mask for DMA_INT_INT6.
+#define BS_DMA_INT_INT6 (1U) //!< Bit field size in bits for DMA_INT_INT6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT6 field.
+#define BR_DMA_INT_INT6(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT6))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT6.
+#define BF_DMA_INT_INT6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT6), uint32_t) & BM_DMA_INT_INT6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT6 field to a new value.
+#define BW_DMA_INT_INT6(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT7[7] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT7 (7U) //!< Bit position for DMA_INT_INT7.
+#define BM_DMA_INT_INT7 (0x00000080U) //!< Bit mask for DMA_INT_INT7.
+#define BS_DMA_INT_INT7 (1U) //!< Bit field size in bits for DMA_INT_INT7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT7 field.
+#define BR_DMA_INT_INT7(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT7))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT7.
+#define BF_DMA_INT_INT7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT7), uint32_t) & BM_DMA_INT_INT7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT7 field to a new value.
+#define BW_DMA_INT_INT7(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT8[8] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT8 (8U) //!< Bit position for DMA_INT_INT8.
+#define BM_DMA_INT_INT8 (0x00000100U) //!< Bit mask for DMA_INT_INT8.
+#define BS_DMA_INT_INT8 (1U) //!< Bit field size in bits for DMA_INT_INT8.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT8 field.
+#define BR_DMA_INT_INT8(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT8))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT8.
+#define BF_DMA_INT_INT8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT8), uint32_t) & BM_DMA_INT_INT8)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT8 field to a new value.
+#define BW_DMA_INT_INT8(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT8) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT9[9] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT9 (9U) //!< Bit position for DMA_INT_INT9.
+#define BM_DMA_INT_INT9 (0x00000200U) //!< Bit mask for DMA_INT_INT9.
+#define BS_DMA_INT_INT9 (1U) //!< Bit field size in bits for DMA_INT_INT9.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT9 field.
+#define BR_DMA_INT_INT9(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT9))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT9.
+#define BF_DMA_INT_INT9(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT9), uint32_t) & BM_DMA_INT_INT9)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT9 field to a new value.
+#define BW_DMA_INT_INT9(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT9) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT10[10] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT10 (10U) //!< Bit position for DMA_INT_INT10.
+#define BM_DMA_INT_INT10 (0x00000400U) //!< Bit mask for DMA_INT_INT10.
+#define BS_DMA_INT_INT10 (1U) //!< Bit field size in bits for DMA_INT_INT10.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT10 field.
+#define BR_DMA_INT_INT10(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT10))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT10.
+#define BF_DMA_INT_INT10(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT10), uint32_t) & BM_DMA_INT_INT10)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT10 field to a new value.
+#define BW_DMA_INT_INT10(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT10) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT11[11] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT11 (11U) //!< Bit position for DMA_INT_INT11.
+#define BM_DMA_INT_INT11 (0x00000800U) //!< Bit mask for DMA_INT_INT11.
+#define BS_DMA_INT_INT11 (1U) //!< Bit field size in bits for DMA_INT_INT11.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT11 field.
+#define BR_DMA_INT_INT11(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT11))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT11.
+#define BF_DMA_INT_INT11(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT11), uint32_t) & BM_DMA_INT_INT11)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT11 field to a new value.
+#define BW_DMA_INT_INT11(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT11) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT12[12] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT12 (12U) //!< Bit position for DMA_INT_INT12.
+#define BM_DMA_INT_INT12 (0x00001000U) //!< Bit mask for DMA_INT_INT12.
+#define BS_DMA_INT_INT12 (1U) //!< Bit field size in bits for DMA_INT_INT12.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT12 field.
+#define BR_DMA_INT_INT12(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT12))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT12.
+#define BF_DMA_INT_INT12(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT12), uint32_t) & BM_DMA_INT_INT12)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT12 field to a new value.
+#define BW_DMA_INT_INT12(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT12) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT13[13] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT13 (13U) //!< Bit position for DMA_INT_INT13.
+#define BM_DMA_INT_INT13 (0x00002000U) //!< Bit mask for DMA_INT_INT13.
+#define BS_DMA_INT_INT13 (1U) //!< Bit field size in bits for DMA_INT_INT13.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT13 field.
+#define BR_DMA_INT_INT13(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT13))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT13.
+#define BF_DMA_INT_INT13(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT13), uint32_t) & BM_DMA_INT_INT13)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT13 field to a new value.
+#define BW_DMA_INT_INT13(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT13) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT14[14] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT14 (14U) //!< Bit position for DMA_INT_INT14.
+#define BM_DMA_INT_INT14 (0x00004000U) //!< Bit mask for DMA_INT_INT14.
+#define BS_DMA_INT_INT14 (1U) //!< Bit field size in bits for DMA_INT_INT14.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT14 field.
+#define BR_DMA_INT_INT14(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT14))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT14.
+#define BF_DMA_INT_INT14(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT14), uint32_t) & BM_DMA_INT_INT14)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT14 field to a new value.
+#define BW_DMA_INT_INT14(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT14) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_INT, field INT15[15] (W1C)
+ *
+ * Values:
+ * - 0 - The interrupt request for corresponding channel is cleared
+ * - 1 - The interrupt request for corresponding channel is active
+ */
+//@{
+#define BP_DMA_INT_INT15 (15U) //!< Bit position for DMA_INT_INT15.
+#define BM_DMA_INT_INT15 (0x00008000U) //!< Bit mask for DMA_INT_INT15.
+#define BS_DMA_INT_INT15 (1U) //!< Bit field size in bits for DMA_INT_INT15.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_INT_INT15 field.
+#define BR_DMA_INT_INT15(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT15))
+#endif
+
+//! @brief Format value for bitfield DMA_INT_INT15.
+#define BF_DMA_INT_INT15(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT15), uint32_t) & BM_DMA_INT_INT15)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT15 field to a new value.
+#define BW_DMA_INT_INT15(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT15) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_ERR - Error Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_ERR - Error Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The ERR provides a bit map for the 16 channels, signaling the presence of an
+ * error for each channel. The eDMA engine signals the occurrence of an error
+ * condition by setting the appropriate bit in this register. The outputs of this
+ * register are enabled by the contents of the EEI, and then routed to the
+ * interrupt controller. During the execution of the interrupt-service routine associated
+ * with any DMA errors, it is software's responsibility to clear the appropriate
+ * bit, negating the error-interrupt request. Typically, a write to the CERR in
+ * the interrupt-service routine is used for this purpose. The normal DMA channel
+ * completion indicators (setting the transfer control descriptor DONE flag and
+ * the possible assertion of an interrupt request) are not affected when an error
+ * is detected. The contents of this register can also be polled because a
+ * non-zero value indicates the presence of a channel error regardless of the state of
+ * the EEI. The state of any given channel's error indicators is affected by
+ * writes to this register; it is also affected by writes to the CERR. On writes to
+ * the ERR, a one in any bit position clears the corresponding channel's error
+ * status. A zero in any bit position has no affect on the corresponding channel's
+ * current error status. The CERR is provided so the error indicator for a single
+ * channel can easily be cleared.
+ */
+typedef union _hw_dma_err
+{
+ uint32_t U;
+ struct _hw_dma_err_bitfields
+ {
+ uint32_t ERR0 : 1; //!< [0] Error In Channel 0
+ uint32_t ERR1 : 1; //!< [1] Error In Channel 1
+ uint32_t ERR2 : 1; //!< [2] Error In Channel 2
+ uint32_t ERR3 : 1; //!< [3] Error In Channel 3
+ uint32_t ERR4 : 1; //!< [4] Error In Channel 4
+ uint32_t ERR5 : 1; //!< [5] Error In Channel 5
+ uint32_t ERR6 : 1; //!< [6] Error In Channel 6
+ uint32_t ERR7 : 1; //!< [7] Error In Channel 7
+ uint32_t ERR8 : 1; //!< [8] Error In Channel 8
+ uint32_t ERR9 : 1; //!< [9] Error In Channel 9
+ uint32_t ERR10 : 1; //!< [10] Error In Channel 10
+ uint32_t ERR11 : 1; //!< [11] Error In Channel 11
+ uint32_t ERR12 : 1; //!< [12] Error In Channel 12
+ uint32_t ERR13 : 1; //!< [13] Error In Channel 13
+ uint32_t ERR14 : 1; //!< [14] Error In Channel 14
+ uint32_t ERR15 : 1; //!< [15] Error In Channel 15
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_dma_err_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_ERR register
+ */
+//@{
+#define HW_DMA_ERR_ADDR(x) (REGS_DMA_BASE(x) + 0x2CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_ERR(x) (*(__IO hw_dma_err_t *) HW_DMA_ERR_ADDR(x))
+#define HW_DMA_ERR_RD(x) (HW_DMA_ERR(x).U)
+#define HW_DMA_ERR_WR(x, v) (HW_DMA_ERR(x).U = (v))
+#define HW_DMA_ERR_SET(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) | (v)))
+#define HW_DMA_ERR_CLR(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) & ~(v)))
+#define HW_DMA_ERR_TOG(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_ERR bitfields
+ */
+
+/*!
+ * @name Register DMA_ERR, field ERR0[0] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR0 (0U) //!< Bit position for DMA_ERR_ERR0.
+#define BM_DMA_ERR_ERR0 (0x00000001U) //!< Bit mask for DMA_ERR_ERR0.
+#define BS_DMA_ERR_ERR0 (1U) //!< Bit field size in bits for DMA_ERR_ERR0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR0 field.
+#define BR_DMA_ERR_ERR0(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR0))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR0.
+#define BF_DMA_ERR_ERR0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR0), uint32_t) & BM_DMA_ERR_ERR0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR0 field to a new value.
+#define BW_DMA_ERR_ERR0(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR1[1] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR1 (1U) //!< Bit position for DMA_ERR_ERR1.
+#define BM_DMA_ERR_ERR1 (0x00000002U) //!< Bit mask for DMA_ERR_ERR1.
+#define BS_DMA_ERR_ERR1 (1U) //!< Bit field size in bits for DMA_ERR_ERR1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR1 field.
+#define BR_DMA_ERR_ERR1(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR1))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR1.
+#define BF_DMA_ERR_ERR1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR1), uint32_t) & BM_DMA_ERR_ERR1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR1 field to a new value.
+#define BW_DMA_ERR_ERR1(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR2[2] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR2 (2U) //!< Bit position for DMA_ERR_ERR2.
+#define BM_DMA_ERR_ERR2 (0x00000004U) //!< Bit mask for DMA_ERR_ERR2.
+#define BS_DMA_ERR_ERR2 (1U) //!< Bit field size in bits for DMA_ERR_ERR2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR2 field.
+#define BR_DMA_ERR_ERR2(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR2))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR2.
+#define BF_DMA_ERR_ERR2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR2), uint32_t) & BM_DMA_ERR_ERR2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR2 field to a new value.
+#define BW_DMA_ERR_ERR2(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR3[3] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR3 (3U) //!< Bit position for DMA_ERR_ERR3.
+#define BM_DMA_ERR_ERR3 (0x00000008U) //!< Bit mask for DMA_ERR_ERR3.
+#define BS_DMA_ERR_ERR3 (1U) //!< Bit field size in bits for DMA_ERR_ERR3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR3 field.
+#define BR_DMA_ERR_ERR3(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR3))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR3.
+#define BF_DMA_ERR_ERR3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR3), uint32_t) & BM_DMA_ERR_ERR3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR3 field to a new value.
+#define BW_DMA_ERR_ERR3(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR4[4] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR4 (4U) //!< Bit position for DMA_ERR_ERR4.
+#define BM_DMA_ERR_ERR4 (0x00000010U) //!< Bit mask for DMA_ERR_ERR4.
+#define BS_DMA_ERR_ERR4 (1U) //!< Bit field size in bits for DMA_ERR_ERR4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR4 field.
+#define BR_DMA_ERR_ERR4(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR4))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR4.
+#define BF_DMA_ERR_ERR4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR4), uint32_t) & BM_DMA_ERR_ERR4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR4 field to a new value.
+#define BW_DMA_ERR_ERR4(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR5[5] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR5 (5U) //!< Bit position for DMA_ERR_ERR5.
+#define BM_DMA_ERR_ERR5 (0x00000020U) //!< Bit mask for DMA_ERR_ERR5.
+#define BS_DMA_ERR_ERR5 (1U) //!< Bit field size in bits for DMA_ERR_ERR5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR5 field.
+#define BR_DMA_ERR_ERR5(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR5))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR5.
+#define BF_DMA_ERR_ERR5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR5), uint32_t) & BM_DMA_ERR_ERR5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR5 field to a new value.
+#define BW_DMA_ERR_ERR5(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR6[6] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR6 (6U) //!< Bit position for DMA_ERR_ERR6.
+#define BM_DMA_ERR_ERR6 (0x00000040U) //!< Bit mask for DMA_ERR_ERR6.
+#define BS_DMA_ERR_ERR6 (1U) //!< Bit field size in bits for DMA_ERR_ERR6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR6 field.
+#define BR_DMA_ERR_ERR6(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR6))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR6.
+#define BF_DMA_ERR_ERR6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR6), uint32_t) & BM_DMA_ERR_ERR6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR6 field to a new value.
+#define BW_DMA_ERR_ERR6(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR7[7] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR7 (7U) //!< Bit position for DMA_ERR_ERR7.
+#define BM_DMA_ERR_ERR7 (0x00000080U) //!< Bit mask for DMA_ERR_ERR7.
+#define BS_DMA_ERR_ERR7 (1U) //!< Bit field size in bits for DMA_ERR_ERR7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR7 field.
+#define BR_DMA_ERR_ERR7(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR7))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR7.
+#define BF_DMA_ERR_ERR7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR7), uint32_t) & BM_DMA_ERR_ERR7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR7 field to a new value.
+#define BW_DMA_ERR_ERR7(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR7) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR8[8] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR8 (8U) //!< Bit position for DMA_ERR_ERR8.
+#define BM_DMA_ERR_ERR8 (0x00000100U) //!< Bit mask for DMA_ERR_ERR8.
+#define BS_DMA_ERR_ERR8 (1U) //!< Bit field size in bits for DMA_ERR_ERR8.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR8 field.
+#define BR_DMA_ERR_ERR8(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR8))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR8.
+#define BF_DMA_ERR_ERR8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR8), uint32_t) & BM_DMA_ERR_ERR8)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR8 field to a new value.
+#define BW_DMA_ERR_ERR8(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR8) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR9[9] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR9 (9U) //!< Bit position for DMA_ERR_ERR9.
+#define BM_DMA_ERR_ERR9 (0x00000200U) //!< Bit mask for DMA_ERR_ERR9.
+#define BS_DMA_ERR_ERR9 (1U) //!< Bit field size in bits for DMA_ERR_ERR9.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR9 field.
+#define BR_DMA_ERR_ERR9(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR9))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR9.
+#define BF_DMA_ERR_ERR9(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR9), uint32_t) & BM_DMA_ERR_ERR9)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR9 field to a new value.
+#define BW_DMA_ERR_ERR9(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR9) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR10[10] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR10 (10U) //!< Bit position for DMA_ERR_ERR10.
+#define BM_DMA_ERR_ERR10 (0x00000400U) //!< Bit mask for DMA_ERR_ERR10.
+#define BS_DMA_ERR_ERR10 (1U) //!< Bit field size in bits for DMA_ERR_ERR10.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR10 field.
+#define BR_DMA_ERR_ERR10(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR10))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR10.
+#define BF_DMA_ERR_ERR10(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR10), uint32_t) & BM_DMA_ERR_ERR10)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR10 field to a new value.
+#define BW_DMA_ERR_ERR10(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR10) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR11[11] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR11 (11U) //!< Bit position for DMA_ERR_ERR11.
+#define BM_DMA_ERR_ERR11 (0x00000800U) //!< Bit mask for DMA_ERR_ERR11.
+#define BS_DMA_ERR_ERR11 (1U) //!< Bit field size in bits for DMA_ERR_ERR11.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR11 field.
+#define BR_DMA_ERR_ERR11(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR11))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR11.
+#define BF_DMA_ERR_ERR11(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR11), uint32_t) & BM_DMA_ERR_ERR11)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR11 field to a new value.
+#define BW_DMA_ERR_ERR11(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR11) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR12[12] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR12 (12U) //!< Bit position for DMA_ERR_ERR12.
+#define BM_DMA_ERR_ERR12 (0x00001000U) //!< Bit mask for DMA_ERR_ERR12.
+#define BS_DMA_ERR_ERR12 (1U) //!< Bit field size in bits for DMA_ERR_ERR12.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR12 field.
+#define BR_DMA_ERR_ERR12(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR12))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR12.
+#define BF_DMA_ERR_ERR12(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR12), uint32_t) & BM_DMA_ERR_ERR12)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR12 field to a new value.
+#define BW_DMA_ERR_ERR12(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR12) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR13[13] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR13 (13U) //!< Bit position for DMA_ERR_ERR13.
+#define BM_DMA_ERR_ERR13 (0x00002000U) //!< Bit mask for DMA_ERR_ERR13.
+#define BS_DMA_ERR_ERR13 (1U) //!< Bit field size in bits for DMA_ERR_ERR13.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR13 field.
+#define BR_DMA_ERR_ERR13(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR13))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR13.
+#define BF_DMA_ERR_ERR13(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR13), uint32_t) & BM_DMA_ERR_ERR13)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR13 field to a new value.
+#define BW_DMA_ERR_ERR13(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR13) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR14[14] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR14 (14U) //!< Bit position for DMA_ERR_ERR14.
+#define BM_DMA_ERR_ERR14 (0x00004000U) //!< Bit mask for DMA_ERR_ERR14.
+#define BS_DMA_ERR_ERR14 (1U) //!< Bit field size in bits for DMA_ERR_ERR14.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR14 field.
+#define BR_DMA_ERR_ERR14(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR14))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR14.
+#define BF_DMA_ERR_ERR14(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR14), uint32_t) & BM_DMA_ERR_ERR14)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR14 field to a new value.
+#define BW_DMA_ERR_ERR14(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR14) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_ERR, field ERR15[15] (W1C)
+ *
+ * Values:
+ * - 0 - An error in the corresponding channel has not occurred
+ * - 1 - An error in the corresponding channel has occurred
+ */
+//@{
+#define BP_DMA_ERR_ERR15 (15U) //!< Bit position for DMA_ERR_ERR15.
+#define BM_DMA_ERR_ERR15 (0x00008000U) //!< Bit mask for DMA_ERR_ERR15.
+#define BS_DMA_ERR_ERR15 (1U) //!< Bit field size in bits for DMA_ERR_ERR15.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_ERR_ERR15 field.
+#define BR_DMA_ERR_ERR15(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR15))
+#endif
+
+//! @brief Format value for bitfield DMA_ERR_ERR15.
+#define BF_DMA_ERR_ERR15(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR15), uint32_t) & BM_DMA_ERR_ERR15)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR15 field to a new value.
+#define BW_DMA_ERR_ERR15(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR15) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_HRS - Hardware Request Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_HRS - Hardware Request Status Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The HRS register provides a bit map for the DMA channels, signaling the
+ * presence of a hardware request for each channel. The hardware request status bits
+ * reflect the current state of the register and qualified (via the ERQ fields)
+ * DMA request signals as seen by the DMA's arbitration logic. This view into the
+ * hardware request signals may be used for debug purposes. These bits reflect the
+ * state of the request as seen by the arbitration logic. Therefore, this status
+ * is affected by the ERQ bits.
+ */
+typedef union _hw_dma_hrs
+{
+ uint32_t U;
+ struct _hw_dma_hrs_bitfields
+ {
+ uint32_t HRS0 : 1; //!< [0] Hardware Request Status Channel 0
+ uint32_t HRS1 : 1; //!< [1] Hardware Request Status Channel 1
+ uint32_t HRS2 : 1; //!< [2] Hardware Request Status Channel 2
+ uint32_t HRS3 : 1; //!< [3] Hardware Request Status Channel 3
+ uint32_t HRS4 : 1; //!< [4] Hardware Request Status Channel 4
+ uint32_t HRS5 : 1; //!< [5] Hardware Request Status Channel 5
+ uint32_t HRS6 : 1; //!< [6] Hardware Request Status Channel 6
+ uint32_t HRS7 : 1; //!< [7] Hardware Request Status Channel 7
+ uint32_t HRS8 : 1; //!< [8] Hardware Request Status Channel 8
+ uint32_t HRS9 : 1; //!< [9] Hardware Request Status Channel 9
+ uint32_t HRS10 : 1; //!< [10] Hardware Request Status Channel 10
+ uint32_t HRS11 : 1; //!< [11] Hardware Request Status Channel 11
+ uint32_t HRS12 : 1; //!< [12] Hardware Request Status Channel 12
+ uint32_t HRS13 : 1; //!< [13] Hardware Request Status Channel 13
+ uint32_t HRS14 : 1; //!< [14] Hardware Request Status Channel 14
+ uint32_t HRS15 : 1; //!< [15] Hardware Request Status Channel 15
+ uint32_t RESERVED0 : 16; //!< [31:16] Reserved
+ } B;
+} hw_dma_hrs_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_HRS register
+ */
+//@{
+#define HW_DMA_HRS_ADDR(x) (REGS_DMA_BASE(x) + 0x34U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_HRS(x) (*(__I hw_dma_hrs_t *) HW_DMA_HRS_ADDR(x))
+#define HW_DMA_HRS_RD(x) (HW_DMA_HRS(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_HRS bitfields
+ */
+
+/*!
+ * @name Register DMA_HRS, field HRS0[0] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 0 is not present
+ * - 1 - A hardware service request for channel 0 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS0 (0U) //!< Bit position for DMA_HRS_HRS0.
+#define BM_DMA_HRS_HRS0 (0x00000001U) //!< Bit mask for DMA_HRS_HRS0.
+#define BS_DMA_HRS_HRS0 (1U) //!< Bit field size in bits for DMA_HRS_HRS0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS0 field.
+#define BR_DMA_HRS_HRS0(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS0))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS1[1] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 1 is not present
+ * - 1 - A hardware service request for channel 1 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS1 (1U) //!< Bit position for DMA_HRS_HRS1.
+#define BM_DMA_HRS_HRS1 (0x00000002U) //!< Bit mask for DMA_HRS_HRS1.
+#define BS_DMA_HRS_HRS1 (1U) //!< Bit field size in bits for DMA_HRS_HRS1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS1 field.
+#define BR_DMA_HRS_HRS1(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS1))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS2[2] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 2 is not present
+ * - 1 - A hardware service request for channel 2 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS2 (2U) //!< Bit position for DMA_HRS_HRS2.
+#define BM_DMA_HRS_HRS2 (0x00000004U) //!< Bit mask for DMA_HRS_HRS2.
+#define BS_DMA_HRS_HRS2 (1U) //!< Bit field size in bits for DMA_HRS_HRS2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS2 field.
+#define BR_DMA_HRS_HRS2(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS2))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS3[3] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 3 is not present
+ * - 1 - A hardware service request for channel 3 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS3 (3U) //!< Bit position for DMA_HRS_HRS3.
+#define BM_DMA_HRS_HRS3 (0x00000008U) //!< Bit mask for DMA_HRS_HRS3.
+#define BS_DMA_HRS_HRS3 (1U) //!< Bit field size in bits for DMA_HRS_HRS3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS3 field.
+#define BR_DMA_HRS_HRS3(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS3))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS4[4] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 4 is not present
+ * - 1 - A hardware service request for channel 4 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS4 (4U) //!< Bit position for DMA_HRS_HRS4.
+#define BM_DMA_HRS_HRS4 (0x00000010U) //!< Bit mask for DMA_HRS_HRS4.
+#define BS_DMA_HRS_HRS4 (1U) //!< Bit field size in bits for DMA_HRS_HRS4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS4 field.
+#define BR_DMA_HRS_HRS4(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS4))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS5[5] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 5 is not present
+ * - 1 - A hardware service request for channel 5 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS5 (5U) //!< Bit position for DMA_HRS_HRS5.
+#define BM_DMA_HRS_HRS5 (0x00000020U) //!< Bit mask for DMA_HRS_HRS5.
+#define BS_DMA_HRS_HRS5 (1U) //!< Bit field size in bits for DMA_HRS_HRS5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS5 field.
+#define BR_DMA_HRS_HRS5(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS5))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS6[6] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 6 is not present
+ * - 1 - A hardware service request for channel 6 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS6 (6U) //!< Bit position for DMA_HRS_HRS6.
+#define BM_DMA_HRS_HRS6 (0x00000040U) //!< Bit mask for DMA_HRS_HRS6.
+#define BS_DMA_HRS_HRS6 (1U) //!< Bit field size in bits for DMA_HRS_HRS6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS6 field.
+#define BR_DMA_HRS_HRS6(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS6))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS7[7] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 7 is not present
+ * - 1 - A hardware service request for channel 7 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS7 (7U) //!< Bit position for DMA_HRS_HRS7.
+#define BM_DMA_HRS_HRS7 (0x00000080U) //!< Bit mask for DMA_HRS_HRS7.
+#define BS_DMA_HRS_HRS7 (1U) //!< Bit field size in bits for DMA_HRS_HRS7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS7 field.
+#define BR_DMA_HRS_HRS7(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS7))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS8[8] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 8 is not present
+ * - 1 - A hardware service request for channel 8 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS8 (8U) //!< Bit position for DMA_HRS_HRS8.
+#define BM_DMA_HRS_HRS8 (0x00000100U) //!< Bit mask for DMA_HRS_HRS8.
+#define BS_DMA_HRS_HRS8 (1U) //!< Bit field size in bits for DMA_HRS_HRS8.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS8 field.
+#define BR_DMA_HRS_HRS8(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS8))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS9[9] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 9 is not present
+ * - 1 - A hardware service request for channel 9 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS9 (9U) //!< Bit position for DMA_HRS_HRS9.
+#define BM_DMA_HRS_HRS9 (0x00000200U) //!< Bit mask for DMA_HRS_HRS9.
+#define BS_DMA_HRS_HRS9 (1U) //!< Bit field size in bits for DMA_HRS_HRS9.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS9 field.
+#define BR_DMA_HRS_HRS9(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS9))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS10[10] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 10 is not present
+ * - 1 - A hardware service request for channel 10 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS10 (10U) //!< Bit position for DMA_HRS_HRS10.
+#define BM_DMA_HRS_HRS10 (0x00000400U) //!< Bit mask for DMA_HRS_HRS10.
+#define BS_DMA_HRS_HRS10 (1U) //!< Bit field size in bits for DMA_HRS_HRS10.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS10 field.
+#define BR_DMA_HRS_HRS10(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS10))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS11[11] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 11 is not present
+ * - 1 - A hardware service request for channel 11 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS11 (11U) //!< Bit position for DMA_HRS_HRS11.
+#define BM_DMA_HRS_HRS11 (0x00000800U) //!< Bit mask for DMA_HRS_HRS11.
+#define BS_DMA_HRS_HRS11 (1U) //!< Bit field size in bits for DMA_HRS_HRS11.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS11 field.
+#define BR_DMA_HRS_HRS11(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS11))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS12[12] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 12 is not present
+ * - 1 - A hardware service request for channel 12 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS12 (12U) //!< Bit position for DMA_HRS_HRS12.
+#define BM_DMA_HRS_HRS12 (0x00001000U) //!< Bit mask for DMA_HRS_HRS12.
+#define BS_DMA_HRS_HRS12 (1U) //!< Bit field size in bits for DMA_HRS_HRS12.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS12 field.
+#define BR_DMA_HRS_HRS12(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS12))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS13[13] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 13 is not present
+ * - 1 - A hardware service request for channel 13 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS13 (13U) //!< Bit position for DMA_HRS_HRS13.
+#define BM_DMA_HRS_HRS13 (0x00002000U) //!< Bit mask for DMA_HRS_HRS13.
+#define BS_DMA_HRS_HRS13 (1U) //!< Bit field size in bits for DMA_HRS_HRS13.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS13 field.
+#define BR_DMA_HRS_HRS13(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS13))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS14[14] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 14 is not present
+ * - 1 - A hardware service request for channel 14 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS14 (14U) //!< Bit position for DMA_HRS_HRS14.
+#define BM_DMA_HRS_HRS14 (0x00004000U) //!< Bit mask for DMA_HRS_HRS14.
+#define BS_DMA_HRS_HRS14 (1U) //!< Bit field size in bits for DMA_HRS_HRS14.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS14 field.
+#define BR_DMA_HRS_HRS14(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS14))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_HRS, field HRS15[15] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0 - A hardware service request for channel 15 is not present
+ * - 1 - A hardware service request for channel 15 is present
+ */
+//@{
+#define BP_DMA_HRS_HRS15 (15U) //!< Bit position for DMA_HRS_HRS15.
+#define BM_DMA_HRS_HRS15 (0x00008000U) //!< Bit mask for DMA_HRS_HRS15.
+#define BS_DMA_HRS_HRS15 (1U) //!< Bit field size in bits for DMA_HRS_HRS15.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_HRS_HRS15 field.
+#define BR_DMA_HRS_HRS15(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS15))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_DCHPRIn - Channel n Priority Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_DCHPRIn - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+typedef union _hw_dma_dchprin
+{
+ uint8_t U;
+ struct _hw_dma_dchprin_bitfields
+ {
+ uint8_t CHPRI : 4; //!< [3:0] Channel n Arbitration Priority
+ uint8_t RESERVED0 : 2; //!< [5:4]
+ uint8_t DPA : 1; //!< [6] Disable Preempt Ability
+ uint8_t ECP : 1; //!< [7] Enable Channel Preemption
+ } B;
+} hw_dma_dchprin_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_DCHPRIn register
+ */
+//@{
+#define HW_DMA_DCHPRIn_COUNT (16U)
+
+#define HW_DMA_DCHPRIn_ADDR(x, n) (REGS_DMA_BASE(x) + 0x100U + (0x1U * n))
+
+/* DMA channel index to DMA channel priority register array index conversion macro */
+#define HW_DMA_DCHPRIn_CHANNEL(n) (((n) & ~0x03U) | (3 - ((n) & 0x03U)))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_DCHPRIn(x, n) (*(__IO hw_dma_dchprin_t *) HW_DMA_DCHPRIn_ADDR(x, n))
+#define HW_DMA_DCHPRIn_RD(x, n) (HW_DMA_DCHPRIn(x, n).U)
+#define HW_DMA_DCHPRIn_WR(x, n, v) (HW_DMA_DCHPRIn(x, n).U = (v))
+#define HW_DMA_DCHPRIn_SET(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) | (v)))
+#define HW_DMA_DCHPRIn_CLR(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) & ~(v)))
+#define HW_DMA_DCHPRIn_TOG(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_DCHPRIn bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRIn, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+//@{
+#define BP_DMA_DCHPRIn_CHPRI (0U) //!< Bit position for DMA_DCHPRIn_CHPRI.
+#define BM_DMA_DCHPRIn_CHPRI (0x0FU) //!< Bit mask for DMA_DCHPRIn_CHPRI.
+#define BS_DMA_DCHPRIn_CHPRI (4U) //!< Bit field size in bits for DMA_DCHPRIn_CHPRI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_DCHPRIn_CHPRI field.
+#define BR_DMA_DCHPRIn_CHPRI(x, n) (HW_DMA_DCHPRIn(x, n).B.CHPRI)
+#endif
+
+//! @brief Format value for bitfield DMA_DCHPRIn_CHPRI.
+#define BF_DMA_DCHPRIn_CHPRI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_DCHPRIn_CHPRI), uint8_t) & BM_DMA_DCHPRIn_CHPRI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CHPRI field to a new value.
+#define BW_DMA_DCHPRIn_CHPRI(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, (HW_DMA_DCHPRIn_RD(x, n) & ~BM_DMA_DCHPRIn_CHPRI) | BF_DMA_DCHPRIn_CHPRI(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_DCHPRIn, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0 - Channel n can suspend a lower priority channel
+ * - 1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+//@{
+#define BP_DMA_DCHPRIn_DPA (6U) //!< Bit position for DMA_DCHPRIn_DPA.
+#define BM_DMA_DCHPRIn_DPA (0x40U) //!< Bit mask for DMA_DCHPRIn_DPA.
+#define BS_DMA_DCHPRIn_DPA (1U) //!< Bit field size in bits for DMA_DCHPRIn_DPA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_DCHPRIn_DPA field.
+#define BR_DMA_DCHPRIn_DPA(x, n) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_DPA))
+#endif
+
+//! @brief Format value for bitfield DMA_DCHPRIn_DPA.
+#define BF_DMA_DCHPRIn_DPA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_DCHPRIn_DPA), uint8_t) & BM_DMA_DCHPRIn_DPA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DPA field to a new value.
+#define BW_DMA_DCHPRIn_DPA(x, n, v) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_DPA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_DCHPRIn, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0 - Channel n cannot be suspended by a higher priority channel's service
+ * request
+ * - 1 - Channel n can be temporarily suspended by the service request of a
+ * higher priority channel
+ */
+//@{
+#define BP_DMA_DCHPRIn_ECP (7U) //!< Bit position for DMA_DCHPRIn_ECP.
+#define BM_DMA_DCHPRIn_ECP (0x80U) //!< Bit mask for DMA_DCHPRIn_ECP.
+#define BS_DMA_DCHPRIn_ECP (1U) //!< Bit field size in bits for DMA_DCHPRIn_ECP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_DCHPRIn_ECP field.
+#define BR_DMA_DCHPRIn_ECP(x, n) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_ECP))
+#endif
+
+//! @brief Format value for bitfield DMA_DCHPRIn_ECP.
+#define BF_DMA_DCHPRIn_ECP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_DCHPRIn_ECP), uint8_t) & BM_DMA_DCHPRIn_ECP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ECP field to a new value.
+#define BW_DMA_DCHPRIn_ECP(x, n, v) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_ECP) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_SADDR - TCD Source Address
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_SADDR - TCD Source Address (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_dma_tcdn_saddr
+{
+ uint32_t U;
+ struct _hw_dma_tcdn_saddr_bitfields
+ {
+ uint32_t SADDR : 32; //!< [31:0] Source Address
+ } B;
+} hw_dma_tcdn_saddr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_SADDR register
+ */
+//@{
+#define HW_DMA_TCDn_SADDR_COUNT (16U)
+
+#define HW_DMA_TCDn_SADDR_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1000U + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_SADDR(x, n) (*(__IO hw_dma_tcdn_saddr_t *) HW_DMA_TCDn_SADDR_ADDR(x, n))
+#define HW_DMA_TCDn_SADDR_RD(x, n) (HW_DMA_TCDn_SADDR(x, n).U)
+#define HW_DMA_TCDn_SADDR_WR(x, n, v) (HW_DMA_TCDn_SADDR(x, n).U = (v))
+#define HW_DMA_TCDn_SADDR_SET(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) | (v)))
+#define HW_DMA_TCDn_SADDR_CLR(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_SADDR_TOG(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_SADDR bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_SADDR, field SADDR[31:0] (RW)
+ *
+ * Memory address pointing to the source data.
+ */
+//@{
+#define BP_DMA_TCDn_SADDR_SADDR (0U) //!< Bit position for DMA_TCDn_SADDR_SADDR.
+#define BM_DMA_TCDn_SADDR_SADDR (0xFFFFFFFFU) //!< Bit mask for DMA_TCDn_SADDR_SADDR.
+#define BS_DMA_TCDn_SADDR_SADDR (32U) //!< Bit field size in bits for DMA_TCDn_SADDR_SADDR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_SADDR_SADDR field.
+#define BR_DMA_TCDn_SADDR_SADDR(x, n) (HW_DMA_TCDn_SADDR(x, n).U)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_SADDR_SADDR.
+#define BF_DMA_TCDn_SADDR_SADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_SADDR_SADDR), uint32_t) & BM_DMA_TCDn_SADDR_SADDR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SADDR field to a new value.
+#define BW_DMA_TCDn_SADDR_SADDR(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset (RW)
+ *
+ * Reset value: 0x0000U
+ */
+typedef union _hw_dma_tcdn_soff
+{
+ uint16_t U;
+ struct _hw_dma_tcdn_soff_bitfields
+ {
+ uint16_t SOFF : 16; //!< [15:0] Source address signed offset
+ } B;
+} hw_dma_tcdn_soff_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_SOFF register
+ */
+//@{
+#define HW_DMA_TCDn_SOFF_COUNT (16U)
+
+#define HW_DMA_TCDn_SOFF_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1004U + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_SOFF(x, n) (*(__IO hw_dma_tcdn_soff_t *) HW_DMA_TCDn_SOFF_ADDR(x, n))
+#define HW_DMA_TCDn_SOFF_RD(x, n) (HW_DMA_TCDn_SOFF(x, n).U)
+#define HW_DMA_TCDn_SOFF_WR(x, n, v) (HW_DMA_TCDn_SOFF(x, n).U = (v))
+#define HW_DMA_TCDn_SOFF_SET(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) | (v)))
+#define HW_DMA_TCDn_SOFF_CLR(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_SOFF_TOG(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_SOFF bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_SOFF, field SOFF[15:0] (RW)
+ *
+ * Sign-extended offset applied to the current source address to form the
+ * next-state value as each source read is completed.
+ */
+//@{
+#define BP_DMA_TCDn_SOFF_SOFF (0U) //!< Bit position for DMA_TCDn_SOFF_SOFF.
+#define BM_DMA_TCDn_SOFF_SOFF (0xFFFFU) //!< Bit mask for DMA_TCDn_SOFF_SOFF.
+#define BS_DMA_TCDn_SOFF_SOFF (16U) //!< Bit field size in bits for DMA_TCDn_SOFF_SOFF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_SOFF_SOFF field.
+#define BR_DMA_TCDn_SOFF_SOFF(x, n) (HW_DMA_TCDn_SOFF(x, n).U)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_SOFF_SOFF.
+#define BF_DMA_TCDn_SOFF_SOFF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_SOFF_SOFF), uint16_t) & BM_DMA_TCDn_SOFF_SOFF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SOFF field to a new value.
+#define BW_DMA_TCDn_SOFF_SOFF(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_ATTR - TCD Transfer Attributes
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_ATTR - TCD Transfer Attributes (RW)
+ *
+ * Reset value: 0x0000U
+ */
+typedef union _hw_dma_tcdn_attr
+{
+ uint16_t U;
+ struct _hw_dma_tcdn_attr_bitfields
+ {
+ uint16_t DSIZE : 3; //!< [2:0] Destination Data Transfer Size
+ uint16_t DMOD : 5; //!< [7:3] Destination Address Modulo
+ uint16_t SSIZE : 3; //!< [10:8] Source data transfer size
+ uint16_t SMOD : 5; //!< [15:11] Source Address Modulo.
+ } B;
+} hw_dma_tcdn_attr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_ATTR register
+ */
+//@{
+#define HW_DMA_TCDn_ATTR_COUNT (16U)
+
+#define HW_DMA_TCDn_ATTR_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1006U + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_ATTR(x, n) (*(__IO hw_dma_tcdn_attr_t *) HW_DMA_TCDn_ATTR_ADDR(x, n))
+#define HW_DMA_TCDn_ATTR_RD(x, n) (HW_DMA_TCDn_ATTR(x, n).U)
+#define HW_DMA_TCDn_ATTR_WR(x, n, v) (HW_DMA_TCDn_ATTR(x, n).U = (v))
+#define HW_DMA_TCDn_ATTR_SET(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) | (v)))
+#define HW_DMA_TCDn_ATTR_CLR(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_ATTR_TOG(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_ATTR bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_ATTR, field DSIZE[2:0] (RW)
+ *
+ * See the SSIZE definition
+ */
+//@{
+#define BP_DMA_TCDn_ATTR_DSIZE (0U) //!< Bit position for DMA_TCDn_ATTR_DSIZE.
+#define BM_DMA_TCDn_ATTR_DSIZE (0x0007U) //!< Bit mask for DMA_TCDn_ATTR_DSIZE.
+#define BS_DMA_TCDn_ATTR_DSIZE (3U) //!< Bit field size in bits for DMA_TCDn_ATTR_DSIZE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_ATTR_DSIZE field.
+#define BR_DMA_TCDn_ATTR_DSIZE(x, n) (HW_DMA_TCDn_ATTR(x, n).B.DSIZE)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_ATTR_DSIZE.
+#define BF_DMA_TCDn_ATTR_DSIZE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_ATTR_DSIZE), uint16_t) & BM_DMA_TCDn_ATTR_DSIZE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DSIZE field to a new value.
+#define BW_DMA_TCDn_ATTR_DSIZE(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_DSIZE) | BF_DMA_TCDn_ATTR_DSIZE(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_ATTR, field DMOD[7:3] (RW)
+ *
+ * See the SMOD definition
+ */
+//@{
+#define BP_DMA_TCDn_ATTR_DMOD (3U) //!< Bit position for DMA_TCDn_ATTR_DMOD.
+#define BM_DMA_TCDn_ATTR_DMOD (0x00F8U) //!< Bit mask for DMA_TCDn_ATTR_DMOD.
+#define BS_DMA_TCDn_ATTR_DMOD (5U) //!< Bit field size in bits for DMA_TCDn_ATTR_DMOD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_ATTR_DMOD field.
+#define BR_DMA_TCDn_ATTR_DMOD(x, n) (HW_DMA_TCDn_ATTR(x, n).B.DMOD)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_ATTR_DMOD.
+#define BF_DMA_TCDn_ATTR_DMOD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_ATTR_DMOD), uint16_t) & BM_DMA_TCDn_ATTR_DMOD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMOD field to a new value.
+#define BW_DMA_TCDn_ATTR_DMOD(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_DMOD) | BF_DMA_TCDn_ATTR_DMOD(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_ATTR, field SSIZE[10:8] (RW)
+ *
+ * The attempted use of a Reserved encoding causes a configuration error.
+ *
+ * Values:
+ * - 000 - 8-bit
+ * - 001 - 16-bit
+ * - 010 - 32-bit
+ * - 011 - Reserved
+ * - 100 - 16-byte
+ * - 101 - 32-byte
+ * - 110 - Reserved
+ * - 111 - Reserved
+ */
+//@{
+#define BP_DMA_TCDn_ATTR_SSIZE (8U) //!< Bit position for DMA_TCDn_ATTR_SSIZE.
+#define BM_DMA_TCDn_ATTR_SSIZE (0x0700U) //!< Bit mask for DMA_TCDn_ATTR_SSIZE.
+#define BS_DMA_TCDn_ATTR_SSIZE (3U) //!< Bit field size in bits for DMA_TCDn_ATTR_SSIZE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_ATTR_SSIZE field.
+#define BR_DMA_TCDn_ATTR_SSIZE(x, n) (HW_DMA_TCDn_ATTR(x, n).B.SSIZE)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_ATTR_SSIZE.
+#define BF_DMA_TCDn_ATTR_SSIZE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_ATTR_SSIZE), uint16_t) & BM_DMA_TCDn_ATTR_SSIZE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SSIZE field to a new value.
+#define BW_DMA_TCDn_ATTR_SSIZE(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_SSIZE) | BF_DMA_TCDn_ATTR_SSIZE(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_ATTR, field SMOD[15:11] (RW)
+ *
+ * Values:
+ * - 0 - Source address modulo feature is disabled
+ */
+//@{
+#define BP_DMA_TCDn_ATTR_SMOD (11U) //!< Bit position for DMA_TCDn_ATTR_SMOD.
+#define BM_DMA_TCDn_ATTR_SMOD (0xF800U) //!< Bit mask for DMA_TCDn_ATTR_SMOD.
+#define BS_DMA_TCDn_ATTR_SMOD (5U) //!< Bit field size in bits for DMA_TCDn_ATTR_SMOD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_ATTR_SMOD field.
+#define BR_DMA_TCDn_ATTR_SMOD(x, n) (HW_DMA_TCDn_ATTR(x, n).B.SMOD)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_ATTR_SMOD.
+#define BF_DMA_TCDn_ATTR_SMOD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_ATTR_SMOD), uint16_t) & BM_DMA_TCDn_ATTR_SMOD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SMOD field to a new value.
+#define BW_DMA_TCDn_ATTR_SMOD(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_SMOD) | BF_DMA_TCDn_ATTR_SMOD(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register, or one of the next two registers (TCD_NBYTES_MLOFFNO,
+ * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which
+ * register to use depends on whether minor loop mapping is disabled, enabled but not
+ * used for this channel, or enabled and used. TCD word 2 is defined as follows
+ * if: Minor loop mapping is disabled (CR[EMLM] = 0) If minor loop mapping is
+ * enabled, see the TCD_NBYTES_MLOFFNO and TCD_NBYTES_MLOFFYES register descriptions
+ * for TCD word 2's definition.
+ */
+typedef union _hw_dma_tcdn_nbytes_mlno
+{
+ uint32_t U;
+ struct _hw_dma_tcdn_nbytes_mlno_bitfields
+ {
+ uint32_t NBYTES : 32; //!< [31:0] Minor Byte Transfer Count
+ } B;
+} hw_dma_tcdn_nbytes_mlno_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_NBYTES_MLNO register
+ */
+//@{
+#define HW_DMA_TCDn_NBYTES_MLNO_COUNT (16U)
+
+#define HW_DMA_TCDn_NBYTES_MLNO_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1008U + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_NBYTES_MLNO(x, n) (*(__IO hw_dma_tcdn_nbytes_mlno_t *) HW_DMA_TCDn_NBYTES_MLNO_ADDR(x, n))
+#define HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U)
+#define HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U = (v))
+#define HW_DMA_TCDn_NBYTES_MLNO_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) | (v)))
+#define HW_DMA_TCDn_NBYTES_MLNO_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_NBYTES_MLNO_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_NBYTES_MLNO bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_NBYTES_MLNO, field NBYTES[31:0] (RW)
+ *
+ * Number of bytes to be transferred in each service request of the channel. As
+ * a channel activates, the appropriate TCD contents load into the eDMA engine,
+ * and the appropriate reads and writes perform until the minor byte transfer
+ * count has transferred. This is an indivisible operation and cannot be halted.
+ * (Although, it may be stalled by using the bandwidth control field, or via
+ * preemption.) After the minor count is exhausted, the SADDR and DADDR values are
+ * written back into the TCD memory, the major iteration count is decremented and
+ * restored to the TCD memory. If the major iteration count is completed, additional
+ * processing is performed. An NBYTES value of 0x0000_0000 is interpreted as a 4
+ * GB transfer.
+ */
+//@{
+#define BP_DMA_TCDn_NBYTES_MLNO_NBYTES (0U) //!< Bit position for DMA_TCDn_NBYTES_MLNO_NBYTES.
+#define BM_DMA_TCDn_NBYTES_MLNO_NBYTES (0xFFFFFFFFU) //!< Bit mask for DMA_TCDn_NBYTES_MLNO_NBYTES.
+#define BS_DMA_TCDn_NBYTES_MLNO_NBYTES (32U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLNO_NBYTES.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_NBYTES_MLNO_NBYTES field.
+#define BR_DMA_TCDn_NBYTES_MLNO_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLNO_NBYTES.
+#define BF_DMA_TCDn_NBYTES_MLNO_NBYTES(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLNO_NBYTES), uint32_t) & BM_DMA_TCDn_NBYTES_MLNO_NBYTES)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NBYTES field to a new value.
+#define BW_DMA_TCDn_NBYTES_MLNO_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * One of three registers (this register, TCD_NBYTES_MLNO, or
+ * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which register to use
+ * depends on whether minor loop mapping is disabled, enabled but not used for
+ * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
+ * loop mapping is enabled (CR[EMLM] = 1) and SMLOE = 0 and DMLOE = 0 If minor
+ * loop mapping is enabled and SMLOE or DMLOE is set, then refer to the
+ * TCD_NBYTES_MLOFFYES register description. If minor loop mapping is disabled, then refer to
+ * the TCD_NBYTES_MLNO register description.
+ */
+typedef union _hw_dma_tcdn_nbytes_mloffno
+{
+ uint32_t U;
+ struct _hw_dma_tcdn_nbytes_mloffno_bitfields
+ {
+ uint32_t NBYTES : 30; //!< [29:0] Minor Byte Transfer Count
+ uint32_t DMLOE : 1; //!< [30] Destination Minor Loop Offset enable
+ uint32_t SMLOE : 1; //!< [31] Source Minor Loop Offset Enable
+ } B;
+} hw_dma_tcdn_nbytes_mloffno_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_NBYTES_MLOFFNO register
+ */
+//@{
+#define HW_DMA_TCDn_NBYTES_MLOFFNO_COUNT (16U)
+
+#define HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1008U + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_NBYTES_MLOFFNO(x, n) (*(__IO hw_dma_tcdn_nbytes_mloffno_t *) HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n))
+#define HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).U)
+#define HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).U = (v))
+#define HW_DMA_TCDn_NBYTES_MLOFFNO_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) | (v)))
+#define HW_DMA_TCDn_NBYTES_MLOFFNO_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_NBYTES_MLOFFNO_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_NBYTES_MLOFFNO bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_NBYTES_MLOFFNO, field NBYTES[29:0] (RW)
+ *
+ * Number of bytes to be transferred in each service request of the channel. As
+ * a channel activates, the appropriate TCD contents load into the eDMA engine,
+ * and the appropriate reads and writes perform until the minor byte transfer
+ * count has transferred. This is an indivisible operation and cannot be halted;
+ * although, it may be stalled by using the bandwidth control field, or via
+ * preemption. After the minor count is exhausted, the SADDR and DADDR values are written
+ * back into the TCD memory, the major iteration count is decremented and
+ * restored to the TCD memory. If the major iteration count is completed, additional
+ * processing is performed.
+ */
+//@{
+#define BP_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (0U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_NBYTES.
+#define BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (0x3FFFFFFFU) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_NBYTES.
+#define BS_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (30U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_NBYTES.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_NBYTES field.
+#define BR_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).B.NBYTES)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_NBYTES.
+#define BF_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFNO_NBYTES), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NBYTES field to a new value.
+#define BW_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES) | BF_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_NBYTES_MLOFFNO, field DMLOE[30] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the destination address
+ * upon minor loop completion.
+ *
+ * Values:
+ * - 0 - The minor loop offset is not applied to the DADDR
+ * - 1 - The minor loop offset is applied to the DADDR
+ */
+//@{
+#define BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (30U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_DMLOE.
+#define BM_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (0x40000000U) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_DMLOE.
+#define BS_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (1U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_DMLOE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_DMLOE field.
+#define BR_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_DMLOE.
+#define BF_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFNO_DMLOE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMLOE field to a new value.
+#define BW_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_NBYTES_MLOFFNO, field SMLOE[31] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the source address upon
+ * minor loop completion.
+ *
+ * Values:
+ * - 0 - The minor loop offset is not applied to the SADDR
+ * - 1 - The minor loop offset is applied to the SADDR
+ */
+//@{
+#define BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (31U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_SMLOE.
+#define BM_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (0x80000000U) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_SMLOE.
+#define BS_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (1U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_SMLOE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_SMLOE field.
+#define BR_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_SMLOE.
+#define BF_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFNO_SMLOE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SMLOE field to a new value.
+#define BW_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE) = (v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * One of three registers (this register, TCD_NBYTES_MLNO, or
+ * TCD_NBYTES_MLOFFNO), defines the number of bytes to transfer per request. Which register to use
+ * depends on whether minor loop mapping is disabled, enabled but not used for
+ * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
+ * loop mapping is enabled (CR[EMLM] = 1) and Minor loop offset is enabled (SMLOE
+ * or DMLOE = 1) If minor loop mapping is enabled and SMLOE and DMLOE are cleared,
+ * then refer to the TCD_NBYTES_MLOFFNO register description. If minor loop
+ * mapping is disabled, then refer to the TCD_NBYTES_MLNO register description.
+ */
+typedef union _hw_dma_tcdn_nbytes_mloffyes
+{
+ uint32_t U;
+ struct _hw_dma_tcdn_nbytes_mloffyes_bitfields
+ {
+ uint32_t NBYTES : 10; //!< [9:0] Minor Byte Transfer Count
+ uint32_t MLOFF : 20; //!< [29:10] If SMLOE or DMLOE is set, this
+ //! field represents a sign-extended offset applied to the source or
+ //! destination address to form the next-state value after the minor loop completes.
+ uint32_t DMLOE : 1; //!< [30] Destination Minor Loop Offset enable
+ uint32_t SMLOE : 1; //!< [31] Source Minor Loop Offset Enable
+ } B;
+} hw_dma_tcdn_nbytes_mloffyes_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_NBYTES_MLOFFYES register
+ */
+//@{
+#define HW_DMA_TCDn_NBYTES_MLOFFYES_COUNT (16U)
+
+#define HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1008U + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_NBYTES_MLOFFYES(x, n) (*(__IO hw_dma_tcdn_nbytes_mloffyes_t *) HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n))
+#define HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).U)
+#define HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).U = (v))
+#define HW_DMA_TCDn_NBYTES_MLOFFYES_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) | (v)))
+#define HW_DMA_TCDn_NBYTES_MLOFFYES_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_NBYTES_MLOFFYES_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_NBYTES_MLOFFYES bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_NBYTES_MLOFFYES, field NBYTES[9:0] (RW)
+ *
+ * Number of bytes to be transferred in each service request of the channel. As
+ * a channel activates, the appropriate TCD contents load into the eDMA engine,
+ * and the appropriate reads and writes perform until the minor byte transfer
+ * count has transferred. This is an indivisible operation and cannot be halted.
+ * (Although, it may be stalled by using the bandwidth control field, or via
+ * preemption.) After the minor count is exhausted, the SADDR and DADDR values are
+ * written back into the TCD memory, the major iteration count is decremented and
+ * restored to the TCD memory. If the major iteration count is completed, additional
+ * processing is performed.
+ */
+//@{
+#define BP_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (0U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_NBYTES.
+#define BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (0x000003FFU) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_NBYTES.
+#define BS_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (10U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_NBYTES.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_NBYTES field.
+#define BR_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).B.NBYTES)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_NBYTES.
+#define BF_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFYES_NBYTES), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NBYTES field to a new value.
+#define BW_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES) | BF_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_NBYTES_MLOFFYES, field MLOFF[29:10] (RW)
+ */
+//@{
+#define BP_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (10U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_MLOFF.
+#define BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (0x3FFFFC00U) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_MLOFF.
+#define BS_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (20U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_MLOFF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_MLOFF field.
+#define BR_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).B.MLOFF)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_MLOFF.
+#define BF_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFYES_MLOFF), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MLOFF field to a new value.
+#define BW_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF) | BF_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_NBYTES_MLOFFYES, field DMLOE[30] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the destination address
+ * upon minor loop completion.
+ *
+ * Values:
+ * - 0 - The minor loop offset is not applied to the DADDR
+ * - 1 - The minor loop offset is applied to the DADDR
+ */
+//@{
+#define BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (30U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_DMLOE.
+#define BM_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (0x40000000U) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_DMLOE.
+#define BS_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (1U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_DMLOE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_DMLOE field.
+#define BR_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_DMLOE.
+#define BF_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFYES_DMLOE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMLOE field to a new value.
+#define BW_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_NBYTES_MLOFFYES, field SMLOE[31] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the source address upon
+ * minor loop completion.
+ *
+ * Values:
+ * - 0 - The minor loop offset is not applied to the SADDR
+ * - 1 - The minor loop offset is applied to the SADDR
+ */
+//@{
+#define BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (31U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_SMLOE.
+#define BM_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (0x80000000U) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_SMLOE.
+#define BS_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (1U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_SMLOE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_SMLOE field.
+#define BR_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_SMLOE.
+#define BF_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFYES_SMLOE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SMLOE field to a new value.
+#define BW_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE) = (v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_dma_tcdn_slast
+{
+ uint32_t U;
+ struct _hw_dma_tcdn_slast_bitfields
+ {
+ uint32_t SLAST : 32; //!< [31:0] Last source Address Adjustment
+ } B;
+} hw_dma_tcdn_slast_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_SLAST register
+ */
+//@{
+#define HW_DMA_TCDn_SLAST_COUNT (16U)
+
+#define HW_DMA_TCDn_SLAST_ADDR(x, n) (REGS_DMA_BASE(x) + 0x100CU + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_SLAST(x, n) (*(__IO hw_dma_tcdn_slast_t *) HW_DMA_TCDn_SLAST_ADDR(x, n))
+#define HW_DMA_TCDn_SLAST_RD(x, n) (HW_DMA_TCDn_SLAST(x, n).U)
+#define HW_DMA_TCDn_SLAST_WR(x, n, v) (HW_DMA_TCDn_SLAST(x, n).U = (v))
+#define HW_DMA_TCDn_SLAST_SET(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) | (v)))
+#define HW_DMA_TCDn_SLAST_CLR(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_SLAST_TOG(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_SLAST bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_SLAST, field SLAST[31:0] (RW)
+ *
+ * Adjustment value added to the source address at the completion of the major
+ * iteration count. This value can be applied to restore the source address to the
+ * initial value, or adjust the address to reference the next data structure.
+ * This register uses two's complement notation; the overflow bit is discarded.
+ */
+//@{
+#define BP_DMA_TCDn_SLAST_SLAST (0U) //!< Bit position for DMA_TCDn_SLAST_SLAST.
+#define BM_DMA_TCDn_SLAST_SLAST (0xFFFFFFFFU) //!< Bit mask for DMA_TCDn_SLAST_SLAST.
+#define BS_DMA_TCDn_SLAST_SLAST (32U) //!< Bit field size in bits for DMA_TCDn_SLAST_SLAST.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_SLAST_SLAST field.
+#define BR_DMA_TCDn_SLAST_SLAST(x, n) (HW_DMA_TCDn_SLAST(x, n).U)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_SLAST_SLAST.
+#define BF_DMA_TCDn_SLAST_SLAST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_SLAST_SLAST), uint32_t) & BM_DMA_TCDn_SLAST_SLAST)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SLAST field to a new value.
+#define BW_DMA_TCDn_SLAST_SLAST(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_DADDR - TCD Destination Address
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_DADDR - TCD Destination Address (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_dma_tcdn_daddr
+{
+ uint32_t U;
+ struct _hw_dma_tcdn_daddr_bitfields
+ {
+ uint32_t DADDR : 32; //!< [31:0] Destination Address
+ } B;
+} hw_dma_tcdn_daddr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_DADDR register
+ */
+//@{
+#define HW_DMA_TCDn_DADDR_COUNT (16U)
+
+#define HW_DMA_TCDn_DADDR_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1010U + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_DADDR(x, n) (*(__IO hw_dma_tcdn_daddr_t *) HW_DMA_TCDn_DADDR_ADDR(x, n))
+#define HW_DMA_TCDn_DADDR_RD(x, n) (HW_DMA_TCDn_DADDR(x, n).U)
+#define HW_DMA_TCDn_DADDR_WR(x, n, v) (HW_DMA_TCDn_DADDR(x, n).U = (v))
+#define HW_DMA_TCDn_DADDR_SET(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) | (v)))
+#define HW_DMA_TCDn_DADDR_CLR(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_DADDR_TOG(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_DADDR bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_DADDR, field DADDR[31:0] (RW)
+ *
+ * Memory address pointing to the destination data.
+ */
+//@{
+#define BP_DMA_TCDn_DADDR_DADDR (0U) //!< Bit position for DMA_TCDn_DADDR_DADDR.
+#define BM_DMA_TCDn_DADDR_DADDR (0xFFFFFFFFU) //!< Bit mask for DMA_TCDn_DADDR_DADDR.
+#define BS_DMA_TCDn_DADDR_DADDR (32U) //!< Bit field size in bits for DMA_TCDn_DADDR_DADDR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_DADDR_DADDR field.
+#define BR_DMA_TCDn_DADDR_DADDR(x, n) (HW_DMA_TCDn_DADDR(x, n).U)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_DADDR_DADDR.
+#define BF_DMA_TCDn_DADDR_DADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_DADDR_DADDR), uint32_t) & BM_DMA_TCDn_DADDR_DADDR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DADDR field to a new value.
+#define BW_DMA_TCDn_DADDR_DADDR(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset (RW)
+ *
+ * Reset value: 0x0000U
+ */
+typedef union _hw_dma_tcdn_doff
+{
+ uint16_t U;
+ struct _hw_dma_tcdn_doff_bitfields
+ {
+ uint16_t DOFF : 16; //!< [15:0] Destination Address Signed offset
+ } B;
+} hw_dma_tcdn_doff_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_DOFF register
+ */
+//@{
+#define HW_DMA_TCDn_DOFF_COUNT (16U)
+
+#define HW_DMA_TCDn_DOFF_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1014U + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_DOFF(x, n) (*(__IO hw_dma_tcdn_doff_t *) HW_DMA_TCDn_DOFF_ADDR(x, n))
+#define HW_DMA_TCDn_DOFF_RD(x, n) (HW_DMA_TCDn_DOFF(x, n).U)
+#define HW_DMA_TCDn_DOFF_WR(x, n, v) (HW_DMA_TCDn_DOFF(x, n).U = (v))
+#define HW_DMA_TCDn_DOFF_SET(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) | (v)))
+#define HW_DMA_TCDn_DOFF_CLR(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_DOFF_TOG(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_DOFF bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_DOFF, field DOFF[15:0] (RW)
+ *
+ * Sign-extended offset applied to the current destination address to form the
+ * next-state value as each destination write is completed.
+ */
+//@{
+#define BP_DMA_TCDn_DOFF_DOFF (0U) //!< Bit position for DMA_TCDn_DOFF_DOFF.
+#define BM_DMA_TCDn_DOFF_DOFF (0xFFFFU) //!< Bit mask for DMA_TCDn_DOFF_DOFF.
+#define BS_DMA_TCDn_DOFF_DOFF (16U) //!< Bit field size in bits for DMA_TCDn_DOFF_DOFF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_DOFF_DOFF field.
+#define BR_DMA_TCDn_DOFF_DOFF(x, n) (HW_DMA_TCDn_DOFF(x, n).U)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_DOFF_DOFF.
+#define BF_DMA_TCDn_DOFF_DOFF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_DOFF_DOFF), uint16_t) & BM_DMA_TCDn_DOFF_DOFF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DOFF field to a new value.
+#define BW_DMA_TCDn_DOFF_DOFF(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If TCDn_CITER[ELINK] is cleared, the TCDn_CITER register is defined as
+ * follows.
+ */
+typedef union _hw_dma_tcdn_citer_elinkno
+{
+ uint16_t U;
+ struct _hw_dma_tcdn_citer_elinkno_bitfields
+ {
+ uint16_t CITER : 15; //!< [14:0] Current Major Iteration Count
+ uint16_t ELINK : 1; //!< [15] Enable channel-to-channel linking on
+ //! minor-loop complete
+ } B;
+} hw_dma_tcdn_citer_elinkno_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_CITER_ELINKNO register
+ */
+//@{
+#define HW_DMA_TCDn_CITER_ELINKNO_COUNT (16U)
+
+#define HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1016U + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_CITER_ELINKNO(x, n) (*(__IO hw_dma_tcdn_citer_elinkno_t *) HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n))
+#define HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) (HW_DMA_TCDn_CITER_ELINKNO(x, n).U)
+#define HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO(x, n).U = (v))
+#define HW_DMA_TCDn_CITER_ELINKNO_SET(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) | (v)))
+#define HW_DMA_TCDn_CITER_ELINKNO_CLR(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_CITER_ELINKNO_TOG(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_CITER_ELINKNO bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_CITER_ELINKNO, field CITER[14:0] (RW)
+ *
+ * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
+ * major loop count for the channel. It is decremented each time the minor loop is
+ * completed and updated in the transfer control descriptor memory. After the
+ * major iteration count is exhausted, the channel performs a number of operations
+ * (e.g., final source and destination address calculations), optionally generating
+ * an interrupt to signal channel completion before reloading the CITER field
+ * from the beginning iteration count (BITER) field. When the CITER field is
+ * initially loaded by software, it must be set to the same value as that contained in
+ * the BITER field. If the channel is configured to execute a single service
+ * request, the initial values of BITER and CITER should be 0x0001.
+ */
+//@{
+#define BP_DMA_TCDn_CITER_ELINKNO_CITER (0U) //!< Bit position for DMA_TCDn_CITER_ELINKNO_CITER.
+#define BM_DMA_TCDn_CITER_ELINKNO_CITER (0x7FFFU) //!< Bit mask for DMA_TCDn_CITER_ELINKNO_CITER.
+#define BS_DMA_TCDn_CITER_ELINKNO_CITER (15U) //!< Bit field size in bits for DMA_TCDn_CITER_ELINKNO_CITER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CITER_ELINKNO_CITER field.
+#define BR_DMA_TCDn_CITER_ELINKNO_CITER(x, n) (HW_DMA_TCDn_CITER_ELINKNO(x, n).B.CITER)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CITER_ELINKNO_CITER.
+#define BF_DMA_TCDn_CITER_ELINKNO_CITER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CITER_ELINKNO_CITER), uint16_t) & BM_DMA_TCDn_CITER_ELINKNO_CITER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CITER field to a new value.
+#define BW_DMA_TCDn_CITER_ELINKNO_CITER(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, (HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKNO_CITER) | BF_DMA_TCDn_CITER_ELINKNO_CITER(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_CITER_ELINKNO, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables linking to another
+ * channel, defined by the LINKCH field. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking is disabled, the CITER value
+ * is extended to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK
+ * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
+ * configuration error is reported.
+ *
+ * Values:
+ * - 0 - The channel-to-channel linking is disabled
+ * - 1 - The channel-to-channel linking is enabled
+ */
+//@{
+#define BP_DMA_TCDn_CITER_ELINKNO_ELINK (15U) //!< Bit position for DMA_TCDn_CITER_ELINKNO_ELINK.
+#define BM_DMA_TCDn_CITER_ELINKNO_ELINK (0x8000U) //!< Bit mask for DMA_TCDn_CITER_ELINKNO_ELINK.
+#define BS_DMA_TCDn_CITER_ELINKNO_ELINK (1U) //!< Bit field size in bits for DMA_TCDn_CITER_ELINKNO_ELINK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CITER_ELINKNO_ELINK field.
+#define BR_DMA_TCDn_CITER_ELINKNO_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKNO_ELINK))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CITER_ELINKNO_ELINK.
+#define BF_DMA_TCDn_CITER_ELINKNO_ELINK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CITER_ELINKNO_ELINK), uint16_t) & BM_DMA_TCDn_CITER_ELINKNO_ELINK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ELINK field to a new value.
+#define BW_DMA_TCDn_CITER_ELINKNO_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKNO_ELINK) = (v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If TCDn_CITER[ELINK] is set, the TCDn_CITER register is defined as follows.
+ */
+typedef union _hw_dma_tcdn_citer_elinkyes
+{
+ uint16_t U;
+ struct _hw_dma_tcdn_citer_elinkyes_bitfields
+ {
+ uint16_t CITER : 9; //!< [8:0] Current Major Iteration Count
+ uint16_t LINKCH : 4; //!< [12:9] Link Channel Number
+ uint16_t RESERVED0 : 2; //!< [14:13]
+ uint16_t ELINK : 1; //!< [15] Enable channel-to-channel linking on
+ //! minor-loop complete
+ } B;
+} hw_dma_tcdn_citer_elinkyes_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_CITER_ELINKYES register
+ */
+//@{
+#define HW_DMA_TCDn_CITER_ELINKYES_COUNT (16U)
+
+#define HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1016U + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_CITER_ELINKYES(x, n) (*(__IO hw_dma_tcdn_citer_elinkyes_t *) HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n))
+#define HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).U)
+#define HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES(x, n).U = (v))
+#define HW_DMA_TCDn_CITER_ELINKYES_SET(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) | (v)))
+#define HW_DMA_TCDn_CITER_ELINKYES_CLR(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_CITER_ELINKYES_TOG(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_CITER_ELINKYES bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_CITER_ELINKYES, field CITER[8:0] (RW)
+ *
+ * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
+ * major loop count for the channel. It is decremented each time the minor loop is
+ * completed and updated in the transfer control descriptor memory. After the
+ * major iteration count is exhausted, the channel performs a number of operations
+ * (e.g., final source and destination address calculations), optionally generating
+ * an interrupt to signal channel completion before reloading the CITER field
+ * from the beginning iteration count (BITER) field. When the CITER field is
+ * initially loaded by software, it must be set to the same value as that contained in
+ * the BITER field. If the channel is configured to execute a single service
+ * request, the initial values of BITER and CITER should be 0x0001.
+ */
+//@{
+#define BP_DMA_TCDn_CITER_ELINKYES_CITER (0U) //!< Bit position for DMA_TCDn_CITER_ELINKYES_CITER.
+#define BM_DMA_TCDn_CITER_ELINKYES_CITER (0x01FFU) //!< Bit mask for DMA_TCDn_CITER_ELINKYES_CITER.
+#define BS_DMA_TCDn_CITER_ELINKYES_CITER (9U) //!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_CITER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_CITER field.
+#define BR_DMA_TCDn_CITER_ELINKYES_CITER(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).B.CITER)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_CITER.
+#define BF_DMA_TCDn_CITER_ELINKYES_CITER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CITER_ELINKYES_CITER), uint16_t) & BM_DMA_TCDn_CITER_ELINKYES_CITER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CITER field to a new value.
+#define BW_DMA_TCDn_CITER_ELINKYES_CITER(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKYES_CITER) | BF_DMA_TCDn_CITER_ELINKYES_CITER(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_CITER_ELINKYES, field LINKCH[12:9] (RW)
+ *
+ * If channel-to-channel linking is enabled (ELINK = 1), then after the minor
+ * loop is exhausted, the eDMA engine initiates a channel service request to the
+ * channel defined by these four bits by setting that channel's TCDn_CSR[START] bit.
+ */
+//@{
+#define BP_DMA_TCDn_CITER_ELINKYES_LINKCH (9U) //!< Bit position for DMA_TCDn_CITER_ELINKYES_LINKCH.
+#define BM_DMA_TCDn_CITER_ELINKYES_LINKCH (0x1E00U) //!< Bit mask for DMA_TCDn_CITER_ELINKYES_LINKCH.
+#define BS_DMA_TCDn_CITER_ELINKYES_LINKCH (4U) //!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_LINKCH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_LINKCH field.
+#define BR_DMA_TCDn_CITER_ELINKYES_LINKCH(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).B.LINKCH)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_LINKCH.
+#define BF_DMA_TCDn_CITER_ELINKYES_LINKCH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CITER_ELINKYES_LINKCH), uint16_t) & BM_DMA_TCDn_CITER_ELINKYES_LINKCH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LINKCH field to a new value.
+#define BW_DMA_TCDn_CITER_ELINKYES_LINKCH(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKYES_LINKCH) | BF_DMA_TCDn_CITER_ELINKYES_LINKCH(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_CITER_ELINKYES, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables linking to another
+ * channel, defined by the LINKCH field. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking is disabled, the CITER value
+ * is extended to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK
+ * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
+ * configuration error is reported.
+ *
+ * Values:
+ * - 0 - The channel-to-channel linking is disabled
+ * - 1 - The channel-to-channel linking is enabled
+ */
+//@{
+#define BP_DMA_TCDn_CITER_ELINKYES_ELINK (15U) //!< Bit position for DMA_TCDn_CITER_ELINKYES_ELINK.
+#define BM_DMA_TCDn_CITER_ELINKYES_ELINK (0x8000U) //!< Bit mask for DMA_TCDn_CITER_ELINKYES_ELINK.
+#define BS_DMA_TCDn_CITER_ELINKYES_ELINK (1U) //!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_ELINK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_ELINK field.
+#define BR_DMA_TCDn_CITER_ELINKYES_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKYES_ELINK))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_ELINK.
+#define BF_DMA_TCDn_CITER_ELINKYES_ELINK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CITER_ELINKYES_ELINK), uint16_t) & BM_DMA_TCDn_CITER_ELINKYES_ELINK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ELINK field to a new value.
+#define BW_DMA_TCDn_CITER_ELINKYES_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKYES_ELINK) = (v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_dma_tcdn_dlastsga
+{
+ uint32_t U;
+ struct _hw_dma_tcdn_dlastsga_bitfields
+ {
+ uint32_t DLASTSGA : 32; //!< [31:0]
+ } B;
+} hw_dma_tcdn_dlastsga_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_DLASTSGA register
+ */
+//@{
+#define HW_DMA_TCDn_DLASTSGA_COUNT (16U)
+
+#define HW_DMA_TCDn_DLASTSGA_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1018U + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_DLASTSGA(x, n) (*(__IO hw_dma_tcdn_dlastsga_t *) HW_DMA_TCDn_DLASTSGA_ADDR(x, n))
+#define HW_DMA_TCDn_DLASTSGA_RD(x, n) (HW_DMA_TCDn_DLASTSGA(x, n).U)
+#define HW_DMA_TCDn_DLASTSGA_WR(x, n, v) (HW_DMA_TCDn_DLASTSGA(x, n).U = (v))
+#define HW_DMA_TCDn_DLASTSGA_SET(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) | (v)))
+#define HW_DMA_TCDn_DLASTSGA_CLR(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_DLASTSGA_TOG(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_DLASTSGA bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_DLASTSGA, field DLASTSGA[31:0] (RW)
+ *
+ * Destination last address adjustment or the memory address for the next
+ * transfer control descriptor to be loaded into this channel (scatter/gather). If
+ * (TCDn_CSR[ESG] = 0), then: Adjustment value added to the destination address at
+ * the completion of the major iteration count. This value can apply to restore the
+ * destination address to the initial value or adjust the address to reference
+ * the next data structure. This field uses two's complement notation for the
+ * final destination address adjustment. Otherwise: This address points to the
+ * beginning of a 0-modulo-32-byte region containing the next transfer control
+ * descriptor to be loaded into this channel. This channel reload is performed as the
+ * major iteration count completes. The scatter/gather address must be
+ * 0-modulo-32-byte, else a configuration error is reported.
+ */
+//@{
+#define BP_DMA_TCDn_DLASTSGA_DLASTSGA (0U) //!< Bit position for DMA_TCDn_DLASTSGA_DLASTSGA.
+#define BM_DMA_TCDn_DLASTSGA_DLASTSGA (0xFFFFFFFFU) //!< Bit mask for DMA_TCDn_DLASTSGA_DLASTSGA.
+#define BS_DMA_TCDn_DLASTSGA_DLASTSGA (32U) //!< Bit field size in bits for DMA_TCDn_DLASTSGA_DLASTSGA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_DLASTSGA_DLASTSGA field.
+#define BR_DMA_TCDn_DLASTSGA_DLASTSGA(x, n) (HW_DMA_TCDn_DLASTSGA(x, n).U)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_DLASTSGA_DLASTSGA.
+#define BF_DMA_TCDn_DLASTSGA_DLASTSGA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_DLASTSGA_DLASTSGA), uint32_t) & BM_DMA_TCDn_DLASTSGA_DLASTSGA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DLASTSGA field to a new value.
+#define BW_DMA_TCDn_DLASTSGA_DLASTSGA(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_CSR - TCD Control and Status
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_CSR - TCD Control and Status (RW)
+ *
+ * Reset value: 0x0000U
+ */
+typedef union _hw_dma_tcdn_csr
+{
+ uint16_t U;
+ struct _hw_dma_tcdn_csr_bitfields
+ {
+ uint16_t START : 1; //!< [0] Channel Start
+ uint16_t INTMAJOR : 1; //!< [1] Enable an interrupt when major
+ //! iteration count completes
+ uint16_t INTHALF : 1; //!< [2] Enable an interrupt when major counter
+ //! is half complete.
+ uint16_t DREQ : 1; //!< [3] Disable Request
+ uint16_t ESG : 1; //!< [4] Enable Scatter/Gather Processing
+ uint16_t MAJORELINK : 1; //!< [5] Enable channel-to-channel linking
+ //! on major loop complete
+ uint16_t ACTIVE : 1; //!< [6] Channel Active
+ uint16_t DONE : 1; //!< [7] Channel Done
+ uint16_t MAJORLINKCH : 4; //!< [11:8] Link Channel Number
+ uint16_t RESERVED0 : 2; //!< [13:12]
+ uint16_t BWC : 2; //!< [15:14] Bandwidth Control
+ } B;
+} hw_dma_tcdn_csr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_CSR register
+ */
+//@{
+#define HW_DMA_TCDn_CSR_COUNT (16U)
+
+#define HW_DMA_TCDn_CSR_ADDR(x, n) (REGS_DMA_BASE(x) + 0x101CU + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_CSR(x, n) (*(__IO hw_dma_tcdn_csr_t *) HW_DMA_TCDn_CSR_ADDR(x, n))
+#define HW_DMA_TCDn_CSR_RD(x, n) (HW_DMA_TCDn_CSR(x, n).U)
+#define HW_DMA_TCDn_CSR_WR(x, n, v) (HW_DMA_TCDn_CSR(x, n).U = (v))
+#define HW_DMA_TCDn_CSR_SET(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) | (v)))
+#define HW_DMA_TCDn_CSR_CLR(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_CSR_TOG(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_CSR bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_CSR, field START[0] (RW)
+ *
+ * If this flag is set, the channel is requesting service. The eDMA hardware
+ * automatically clears this flag after the channel begins execution.
+ *
+ * Values:
+ * - 0 - The channel is not explicitly started
+ * - 1 - The channel is explicitly started via a software initiated service
+ * request
+ */
+//@{
+#define BP_DMA_TCDn_CSR_START (0U) //!< Bit position for DMA_TCDn_CSR_START.
+#define BM_DMA_TCDn_CSR_START (0x0001U) //!< Bit mask for DMA_TCDn_CSR_START.
+#define BS_DMA_TCDn_CSR_START (1U) //!< Bit field size in bits for DMA_TCDn_CSR_START.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CSR_START field.
+#define BR_DMA_TCDn_CSR_START(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_START))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CSR_START.
+#define BF_DMA_TCDn_CSR_START(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_START), uint16_t) & BM_DMA_TCDn_CSR_START)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the START field to a new value.
+#define BW_DMA_TCDn_CSR_START(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_START) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_CSR, field INTMAJOR[1] (RW)
+ *
+ * If this flag is set, the channel generates an interrupt request by setting
+ * the appropriate bit in the INT when the current major iteration count reaches
+ * zero.
+ *
+ * Values:
+ * - 0 - The end-of-major loop interrupt is disabled
+ * - 1 - The end-of-major loop interrupt is enabled
+ */
+//@{
+#define BP_DMA_TCDn_CSR_INTMAJOR (1U) //!< Bit position for DMA_TCDn_CSR_INTMAJOR.
+#define BM_DMA_TCDn_CSR_INTMAJOR (0x0002U) //!< Bit mask for DMA_TCDn_CSR_INTMAJOR.
+#define BS_DMA_TCDn_CSR_INTMAJOR (1U) //!< Bit field size in bits for DMA_TCDn_CSR_INTMAJOR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CSR_INTMAJOR field.
+#define BR_DMA_TCDn_CSR_INTMAJOR(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTMAJOR))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CSR_INTMAJOR.
+#define BF_DMA_TCDn_CSR_INTMAJOR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_INTMAJOR), uint16_t) & BM_DMA_TCDn_CSR_INTMAJOR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INTMAJOR field to a new value.
+#define BW_DMA_TCDn_CSR_INTMAJOR(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTMAJOR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_CSR, field INTHALF[2] (RW)
+ *
+ * If this flag is set, the channel generates an interrupt request by setting
+ * the appropriate bit in the INT register when the current major iteration count
+ * reaches the halfway point. Specifically, the comparison performed by the eDMA
+ * engine is (CITER == (BITER >> 1)). This halfway point interrupt request is
+ * provided to support double-buffered (aka ping-pong) schemes or other types of data
+ * movement where the processor needs an early indication of the transfer's
+ * progress. If BITER is set, do not use INTHALF. Use INTMAJOR instead.
+ *
+ * Values:
+ * - 0 - The half-point interrupt is disabled
+ * - 1 - The half-point interrupt is enabled
+ */
+//@{
+#define BP_DMA_TCDn_CSR_INTHALF (2U) //!< Bit position for DMA_TCDn_CSR_INTHALF.
+#define BM_DMA_TCDn_CSR_INTHALF (0x0004U) //!< Bit mask for DMA_TCDn_CSR_INTHALF.
+#define BS_DMA_TCDn_CSR_INTHALF (1U) //!< Bit field size in bits for DMA_TCDn_CSR_INTHALF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CSR_INTHALF field.
+#define BR_DMA_TCDn_CSR_INTHALF(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTHALF))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CSR_INTHALF.
+#define BF_DMA_TCDn_CSR_INTHALF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_INTHALF), uint16_t) & BM_DMA_TCDn_CSR_INTHALF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INTHALF field to a new value.
+#define BW_DMA_TCDn_CSR_INTHALF(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTHALF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_CSR, field DREQ[3] (RW)
+ *
+ * If this flag is set, the eDMA hardware automatically clears the corresponding
+ * ERQ bit when the current major iteration count reaches zero.
+ *
+ * Values:
+ * - 0 - The channel's ERQ bit is not affected
+ * - 1 - The channel's ERQ bit is cleared when the major loop is complete
+ */
+//@{
+#define BP_DMA_TCDn_CSR_DREQ (3U) //!< Bit position for DMA_TCDn_CSR_DREQ.
+#define BM_DMA_TCDn_CSR_DREQ (0x0008U) //!< Bit mask for DMA_TCDn_CSR_DREQ.
+#define BS_DMA_TCDn_CSR_DREQ (1U) //!< Bit field size in bits for DMA_TCDn_CSR_DREQ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CSR_DREQ field.
+#define BR_DMA_TCDn_CSR_DREQ(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DREQ))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CSR_DREQ.
+#define BF_DMA_TCDn_CSR_DREQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_DREQ), uint16_t) & BM_DMA_TCDn_CSR_DREQ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DREQ field to a new value.
+#define BW_DMA_TCDn_CSR_DREQ(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DREQ) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_CSR, field ESG[4] (RW)
+ *
+ * As the channel completes the major loop, this flag enables scatter/gather
+ * processing in the current channel. If enabled, the eDMA engine uses DLASTSGA as a
+ * memory pointer to a 0-modulo-32 address containing a 32-byte data structure
+ * loaded as the transfer control descriptor into the local memory. To support the
+ * dynamic scatter/gather coherency model, this field is forced to zero when
+ * written to while the TCDn_CSR[DONE] bit is set.
+ *
+ * Values:
+ * - 0 - The current channel's TCD is normal format.
+ * - 1 - The current channel's TCD specifies a scatter gather format. The
+ * DLASTSGA field provides a memory pointer to the next TCD to be loaded into this
+ * channel after the major loop completes its execution.
+ */
+//@{
+#define BP_DMA_TCDn_CSR_ESG (4U) //!< Bit position for DMA_TCDn_CSR_ESG.
+#define BM_DMA_TCDn_CSR_ESG (0x0010U) //!< Bit mask for DMA_TCDn_CSR_ESG.
+#define BS_DMA_TCDn_CSR_ESG (1U) //!< Bit field size in bits for DMA_TCDn_CSR_ESG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CSR_ESG field.
+#define BR_DMA_TCDn_CSR_ESG(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ESG))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CSR_ESG.
+#define BF_DMA_TCDn_CSR_ESG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_ESG), uint16_t) & BM_DMA_TCDn_CSR_ESG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ESG field to a new value.
+#define BW_DMA_TCDn_CSR_ESG(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ESG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_CSR, field MAJORELINK[5] (RW)
+ *
+ * As the channel completes the major loop, this flag enables the linking to
+ * another channel, defined by MAJORLINKCH. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. To support the dynamic linking coherency model,
+ * this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set.
+ *
+ * Values:
+ * - 0 - The channel-to-channel linking is disabled
+ * - 1 - The channel-to-channel linking is enabled
+ */
+//@{
+#define BP_DMA_TCDn_CSR_MAJORELINK (5U) //!< Bit position for DMA_TCDn_CSR_MAJORELINK.
+#define BM_DMA_TCDn_CSR_MAJORELINK (0x0020U) //!< Bit mask for DMA_TCDn_CSR_MAJORELINK.
+#define BS_DMA_TCDn_CSR_MAJORELINK (1U) //!< Bit field size in bits for DMA_TCDn_CSR_MAJORELINK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CSR_MAJORELINK field.
+#define BR_DMA_TCDn_CSR_MAJORELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_MAJORELINK))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CSR_MAJORELINK.
+#define BF_DMA_TCDn_CSR_MAJORELINK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_MAJORELINK), uint16_t) & BM_DMA_TCDn_CSR_MAJORELINK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MAJORELINK field to a new value.
+#define BW_DMA_TCDn_CSR_MAJORELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_MAJORELINK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_CSR, field ACTIVE[6] (RW)
+ *
+ * This flag signals the channel is currently in execution. It is set when
+ * channel service begins, and the eDMA clears it as the minor loop completes or if
+ * any error condition is detected. This bit resets to zero.
+ */
+//@{
+#define BP_DMA_TCDn_CSR_ACTIVE (6U) //!< Bit position for DMA_TCDn_CSR_ACTIVE.
+#define BM_DMA_TCDn_CSR_ACTIVE (0x0040U) //!< Bit mask for DMA_TCDn_CSR_ACTIVE.
+#define BS_DMA_TCDn_CSR_ACTIVE (1U) //!< Bit field size in bits for DMA_TCDn_CSR_ACTIVE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CSR_ACTIVE field.
+#define BR_DMA_TCDn_CSR_ACTIVE(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ACTIVE))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CSR_ACTIVE.
+#define BF_DMA_TCDn_CSR_ACTIVE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_ACTIVE), uint16_t) & BM_DMA_TCDn_CSR_ACTIVE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ACTIVE field to a new value.
+#define BW_DMA_TCDn_CSR_ACTIVE(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ACTIVE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_CSR, field DONE[7] (RW)
+ *
+ * This flag indicates the eDMA has completed the major loop. The eDMA engine
+ * sets it as the CITER count reaches zero; The software clears it, or the hardware
+ * when the channel is activated. This bit must be cleared to write the
+ * MAJORELINK or ESG bits.
+ */
+//@{
+#define BP_DMA_TCDn_CSR_DONE (7U) //!< Bit position for DMA_TCDn_CSR_DONE.
+#define BM_DMA_TCDn_CSR_DONE (0x0080U) //!< Bit mask for DMA_TCDn_CSR_DONE.
+#define BS_DMA_TCDn_CSR_DONE (1U) //!< Bit field size in bits for DMA_TCDn_CSR_DONE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CSR_DONE field.
+#define BR_DMA_TCDn_CSR_DONE(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DONE))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CSR_DONE.
+#define BF_DMA_TCDn_CSR_DONE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_DONE), uint16_t) & BM_DMA_TCDn_CSR_DONE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DONE field to a new value.
+#define BW_DMA_TCDn_CSR_DONE(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DONE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_CSR, field MAJORLINKCH[11:8] (RW)
+ *
+ * If (MAJORELINK = 0) then No channel-to-channel linking (or chaining) is
+ * performed after the major loop counter is exhausted. else After the major loop
+ * counter is exhausted, the eDMA engine initiates a channel service request at the
+ * channel defined by these six bits by setting that channel's TCDn_CSR[START] bit.
+ */
+//@{
+#define BP_DMA_TCDn_CSR_MAJORLINKCH (8U) //!< Bit position for DMA_TCDn_CSR_MAJORLINKCH.
+#define BM_DMA_TCDn_CSR_MAJORLINKCH (0x0F00U) //!< Bit mask for DMA_TCDn_CSR_MAJORLINKCH.
+#define BS_DMA_TCDn_CSR_MAJORLINKCH (4U) //!< Bit field size in bits for DMA_TCDn_CSR_MAJORLINKCH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CSR_MAJORLINKCH field.
+#define BR_DMA_TCDn_CSR_MAJORLINKCH(x, n) (HW_DMA_TCDn_CSR(x, n).B.MAJORLINKCH)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CSR_MAJORLINKCH.
+#define BF_DMA_TCDn_CSR_MAJORLINKCH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_MAJORLINKCH), uint16_t) & BM_DMA_TCDn_CSR_MAJORLINKCH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MAJORLINKCH field to a new value.
+#define BW_DMA_TCDn_CSR_MAJORLINKCH(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, (HW_DMA_TCDn_CSR_RD(x, n) & ~BM_DMA_TCDn_CSR_MAJORLINKCH) | BF_DMA_TCDn_CSR_MAJORLINKCH(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_CSR, field BWC[15:14] (RW)
+ *
+ * Throttles the amount of bus bandwidth consumed by the eDMA. In general, as
+ * the eDMA processes the minor loop, it continuously generates read/write
+ * sequences until the minor count is exhausted. This field forces the eDMA to stall
+ * after the completion of each read/write access to control the bus request
+ * bandwidth seen by the crossbar switch. If the source and destination sizes are equal,
+ * this field is ignored between the first and second transfers and after the
+ * last write of each minor loop. This behavior is a side effect of reducing
+ * start-up latency.
+ *
+ * Values:
+ * - 00 - No eDMA engine stalls
+ * - 01 - Reserved
+ * - 10 - eDMA engine stalls for 4 cycles after each r/w
+ * - 11 - eDMA engine stalls for 8 cycles after each r/w
+ */
+//@{
+#define BP_DMA_TCDn_CSR_BWC (14U) //!< Bit position for DMA_TCDn_CSR_BWC.
+#define BM_DMA_TCDn_CSR_BWC (0xC000U) //!< Bit mask for DMA_TCDn_CSR_BWC.
+#define BS_DMA_TCDn_CSR_BWC (2U) //!< Bit field size in bits for DMA_TCDn_CSR_BWC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_CSR_BWC field.
+#define BR_DMA_TCDn_CSR_BWC(x, n) (HW_DMA_TCDn_CSR(x, n).B.BWC)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_CSR_BWC.
+#define BF_DMA_TCDn_CSR_BWC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_BWC), uint16_t) & BM_DMA_TCDn_CSR_BWC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BWC field to a new value.
+#define BW_DMA_TCDn_CSR_BWC(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, (HW_DMA_TCDn_CSR_RD(x, n) & ~BM_DMA_TCDn_CSR_BWC) | BF_DMA_TCDn_CSR_BWC(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If the TCDn_BITER[ELINK] bit is cleared, the TCDn_BITER register is defined
+ * as follows.
+ */
+typedef union _hw_dma_tcdn_biter_elinkno
+{
+ uint16_t U;
+ struct _hw_dma_tcdn_biter_elinkno_bitfields
+ {
+ uint16_t BITER : 15; //!< [14:0] Starting Major Iteration Count
+ uint16_t ELINK : 1; //!< [15] Enables channel-to-channel linking on
+ //! minor loop complete
+ } B;
+} hw_dma_tcdn_biter_elinkno_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_BITER_ELINKNO register
+ */
+//@{
+#define HW_DMA_TCDn_BITER_ELINKNO_COUNT (16U)
+
+#define HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n) (REGS_DMA_BASE(x) + 0x101EU + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_BITER_ELINKNO(x, n) (*(__IO hw_dma_tcdn_biter_elinkno_t *) HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n))
+#define HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) (HW_DMA_TCDn_BITER_ELINKNO(x, n).U)
+#define HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO(x, n).U = (v))
+#define HW_DMA_TCDn_BITER_ELINKNO_SET(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) | (v)))
+#define HW_DMA_TCDn_BITER_ELINKNO_CLR(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_BITER_ELINKNO_TOG(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_BITER_ELINKNO bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_BITER_ELINKNO, field BITER[14:0] (RW)
+ *
+ * As the transfer control descriptor is first loaded by software, this 9-bit
+ * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
+ * field. As the major iteration count is exhausted, the contents of this field
+ * are reloaded into the CITER field. When the software loads the TCD, this field
+ * must be set equal to the corresponding CITER field; otherwise, a configuration
+ * error is reported. As the major iteration count is exhausted, the contents of
+ * this field is reloaded into the CITER field. If the channel is configured to
+ * execute a single service request, the initial values of BITER and CITER should
+ * be 0x0001.
+ */
+//@{
+#define BP_DMA_TCDn_BITER_ELINKNO_BITER (0U) //!< Bit position for DMA_TCDn_BITER_ELINKNO_BITER.
+#define BM_DMA_TCDn_BITER_ELINKNO_BITER (0x7FFFU) //!< Bit mask for DMA_TCDn_BITER_ELINKNO_BITER.
+#define BS_DMA_TCDn_BITER_ELINKNO_BITER (15U) //!< Bit field size in bits for DMA_TCDn_BITER_ELINKNO_BITER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_BITER_ELINKNO_BITER field.
+#define BR_DMA_TCDn_BITER_ELINKNO_BITER(x, n) (HW_DMA_TCDn_BITER_ELINKNO(x, n).B.BITER)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_BITER_ELINKNO_BITER.
+#define BF_DMA_TCDn_BITER_ELINKNO_BITER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_BITER_ELINKNO_BITER), uint16_t) & BM_DMA_TCDn_BITER_ELINKNO_BITER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BITER field to a new value.
+#define BW_DMA_TCDn_BITER_ELINKNO_BITER(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, (HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKNO_BITER) | BF_DMA_TCDn_BITER_ELINKNO_BITER(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_BITER_ELINKNO, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables the linking to
+ * another channel, defined by BITER[LINKCH]. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking is disabled, the BITER value
+ * extends to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
+ * linking. When the software loads the TCD, this field must be set equal to the
+ * corresponding CITER field; otherwise, a configuration error is reported. As the
+ * major iteration count is exhausted, the contents of this field is reloaded
+ * into the CITER field.
+ *
+ * Values:
+ * - 0 - The channel-to-channel linking is disabled
+ * - 1 - The channel-to-channel linking is enabled
+ */
+//@{
+#define BP_DMA_TCDn_BITER_ELINKNO_ELINK (15U) //!< Bit position for DMA_TCDn_BITER_ELINKNO_ELINK.
+#define BM_DMA_TCDn_BITER_ELINKNO_ELINK (0x8000U) //!< Bit mask for DMA_TCDn_BITER_ELINKNO_ELINK.
+#define BS_DMA_TCDn_BITER_ELINKNO_ELINK (1U) //!< Bit field size in bits for DMA_TCDn_BITER_ELINKNO_ELINK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_BITER_ELINKNO_ELINK field.
+#define BR_DMA_TCDn_BITER_ELINKNO_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKNO_ELINK))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_BITER_ELINKNO_ELINK.
+#define BF_DMA_TCDn_BITER_ELINKNO_ELINK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_BITER_ELINKNO_ELINK), uint16_t) & BM_DMA_TCDn_BITER_ELINKNO_ELINK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ELINK field to a new value.
+#define BW_DMA_TCDn_BITER_ELINKNO_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKNO_ELINK) = (v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If the TCDn_BITER[ELINK] bit is set, the TCDn_BITER register is defined as
+ * follows.
+ */
+typedef union _hw_dma_tcdn_biter_elinkyes
+{
+ uint16_t U;
+ struct _hw_dma_tcdn_biter_elinkyes_bitfields
+ {
+ uint16_t BITER : 9; //!< [8:0] Starting Major Iteration Count
+ uint16_t LINKCH : 4; //!< [12:9] Link Channel Number
+ uint16_t RESERVED0 : 2; //!< [14:13]
+ uint16_t ELINK : 1; //!< [15] Enables channel-to-channel linking on
+ //! minor loop complete
+ } B;
+} hw_dma_tcdn_biter_elinkyes_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMA_TCDn_BITER_ELINKYES register
+ */
+//@{
+#define HW_DMA_TCDn_BITER_ELINKYES_COUNT (16U)
+
+#define HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n) (REGS_DMA_BASE(x) + 0x101EU + (0x20U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMA_TCDn_BITER_ELINKYES(x, n) (*(__IO hw_dma_tcdn_biter_elinkyes_t *) HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n))
+#define HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).U)
+#define HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES(x, n).U = (v))
+#define HW_DMA_TCDn_BITER_ELINKYES_SET(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) | (v)))
+#define HW_DMA_TCDn_BITER_ELINKYES_CLR(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~(v)))
+#define HW_DMA_TCDn_BITER_ELINKYES_TOG(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMA_TCDn_BITER_ELINKYES bitfields
+ */
+
+/*!
+ * @name Register DMA_TCDn_BITER_ELINKYES, field BITER[8:0] (RW)
+ *
+ * As the transfer control descriptor is first loaded by software, this 9-bit
+ * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
+ * field. As the major iteration count is exhausted, the contents of this field
+ * are reloaded into the CITER field. When the software loads the TCD, this field
+ * must be set equal to the corresponding CITER field; otherwise, a configuration
+ * error is reported. As the major iteration count is exhausted, the contents of
+ * this field is reloaded into the CITER field. If the channel is configured to
+ * execute a single service request, the initial values of BITER and CITER should
+ * be 0x0001.
+ */
+//@{
+#define BP_DMA_TCDn_BITER_ELINKYES_BITER (0U) //!< Bit position for DMA_TCDn_BITER_ELINKYES_BITER.
+#define BM_DMA_TCDn_BITER_ELINKYES_BITER (0x01FFU) //!< Bit mask for DMA_TCDn_BITER_ELINKYES_BITER.
+#define BS_DMA_TCDn_BITER_ELINKYES_BITER (9U) //!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_BITER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_BITER field.
+#define BR_DMA_TCDn_BITER_ELINKYES_BITER(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).B.BITER)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_BITER.
+#define BF_DMA_TCDn_BITER_ELINKYES_BITER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_BITER_ELINKYES_BITER), uint16_t) & BM_DMA_TCDn_BITER_ELINKYES_BITER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BITER field to a new value.
+#define BW_DMA_TCDn_BITER_ELINKYES_BITER(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKYES_BITER) | BF_DMA_TCDn_BITER_ELINKYES_BITER(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_BITER_ELINKYES, field LINKCH[12:9] (RW)
+ *
+ * If channel-to-channel linking is enabled (ELINK = 1), then after the minor
+ * loop is exhausted, the eDMA engine initiates a channel service request at the
+ * channel defined by these four bits by setting that channel's TCDn_CSR[START]
+ * bit. When the software loads the TCD, this field must be set equal to the
+ * corresponding CITER field; otherwise, a configuration error is reported. As the major
+ * iteration count is exhausted, the contents of this field is reloaded into the
+ * CITER field.
+ */
+//@{
+#define BP_DMA_TCDn_BITER_ELINKYES_LINKCH (9U) //!< Bit position for DMA_TCDn_BITER_ELINKYES_LINKCH.
+#define BM_DMA_TCDn_BITER_ELINKYES_LINKCH (0x1E00U) //!< Bit mask for DMA_TCDn_BITER_ELINKYES_LINKCH.
+#define BS_DMA_TCDn_BITER_ELINKYES_LINKCH (4U) //!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_LINKCH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_LINKCH field.
+#define BR_DMA_TCDn_BITER_ELINKYES_LINKCH(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).B.LINKCH)
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_LINKCH.
+#define BF_DMA_TCDn_BITER_ELINKYES_LINKCH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_BITER_ELINKYES_LINKCH), uint16_t) & BM_DMA_TCDn_BITER_ELINKYES_LINKCH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LINKCH field to a new value.
+#define BW_DMA_TCDn_BITER_ELINKYES_LINKCH(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKYES_LINKCH) | BF_DMA_TCDn_BITER_ELINKYES_LINKCH(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMA_TCDn_BITER_ELINKYES, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables the linking to
+ * another channel, defined by BITER[LINKCH]. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking disables, the BITER value
+ * extends to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
+ * linking. When the software loads the TCD, this field must be set equal to the
+ * corresponding CITER field; otherwise, a configuration error is reported. As the
+ * major iteration count is exhausted, the contents of this field is reloaded into
+ * the CITER field.
+ *
+ * Values:
+ * - 0 - The channel-to-channel linking is disabled
+ * - 1 - The channel-to-channel linking is enabled
+ */
+//@{
+#define BP_DMA_TCDn_BITER_ELINKYES_ELINK (15U) //!< Bit position for DMA_TCDn_BITER_ELINKYES_ELINK.
+#define BM_DMA_TCDn_BITER_ELINKYES_ELINK (0x8000U) //!< Bit mask for DMA_TCDn_BITER_ELINKYES_ELINK.
+#define BS_DMA_TCDn_BITER_ELINKYES_ELINK (1U) //!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_ELINK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_ELINK field.
+#define BR_DMA_TCDn_BITER_ELINKYES_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKYES_ELINK))
+#endif
+
+//! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_ELINK.
+#define BF_DMA_TCDn_BITER_ELINKYES_ELINK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_BITER_ELINKYES_ELINK), uint16_t) & BM_DMA_TCDn_BITER_ELINKYES_ELINK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ELINK field to a new value.
+#define BW_DMA_TCDn_BITER_ELINKYES_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKYES_ELINK) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_dma_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All DMA module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_dma
+{
+ __IO hw_dma_cr_t CR; //!< [0x0] Control Register
+ __I hw_dma_es_t ES; //!< [0x4] Error Status Register
+ uint8_t _reserved0[4];
+ __IO hw_dma_erq_t ERQ; //!< [0xC] Enable Request Register
+ uint8_t _reserved1[4];
+ __IO hw_dma_eei_t EEI; //!< [0x14] Enable Error Interrupt Register
+ __O hw_dma_ceei_t CEEI; //!< [0x18] Clear Enable Error Interrupt Register
+ __O hw_dma_seei_t SEEI; //!< [0x19] Set Enable Error Interrupt Register
+ __O hw_dma_cerq_t CERQ; //!< [0x1A] Clear Enable Request Register
+ __O hw_dma_serq_t SERQ; //!< [0x1B] Set Enable Request Register
+ __O hw_dma_cdne_t CDNE; //!< [0x1C] Clear DONE Status Bit Register
+ __O hw_dma_ssrt_t SSRT; //!< [0x1D] Set START Bit Register
+ __O hw_dma_cerr_t CERR; //!< [0x1E] Clear Error Register
+ __O hw_dma_cint_t CINT; //!< [0x1F] Clear Interrupt Request Register
+ uint8_t _reserved2[4];
+ __IO hw_dma_int_t INT; //!< [0x24] Interrupt Request Register
+ uint8_t _reserved3[4];
+ __IO hw_dma_err_t ERR; //!< [0x2C] Error Register
+ uint8_t _reserved4[4];
+ __I hw_dma_hrs_t HRS; //!< [0x34] Hardware Request Status Register
+ uint8_t _reserved5[200];
+ __IO hw_dma_dchprin_t DCHPRIn[16]; //!< [0x100] Channel n Priority Register
+ uint8_t _reserved6[3824];
+ struct {
+ __IO hw_dma_tcdn_saddr_t TCDn_SADDR; //!< [0x1000] TCD Source Address
+ __IO hw_dma_tcdn_soff_t TCDn_SOFF; //!< [0x1004] TCD Signed Source Address Offset
+ __IO hw_dma_tcdn_attr_t TCDn_ATTR; //!< [0x1006] TCD Transfer Attributes
+ union {
+ __IO hw_dma_tcdn_nbytes_mlno_t TCDn_NBYTES_MLNO; //!< [0x1008] TCD Minor Byte Count (Minor Loop Disabled)
+ __IO hw_dma_tcdn_nbytes_mloffno_t TCDn_NBYTES_MLOFFNO; //!< [0x1008] TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
+ __IO hw_dma_tcdn_nbytes_mloffyes_t TCDn_NBYTES_MLOFFYES; //!< [0x1008] TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
+ };
+ __IO hw_dma_tcdn_slast_t TCDn_SLAST; //!< [0x100C] TCD Last Source Address Adjustment
+ __IO hw_dma_tcdn_daddr_t TCDn_DADDR; //!< [0x1010] TCD Destination Address
+ __IO hw_dma_tcdn_doff_t TCDn_DOFF; //!< [0x1014] TCD Signed Destination Address Offset
+ union {
+ __IO hw_dma_tcdn_citer_elinkno_t TCDn_CITER_ELINKNO; //!< [0x1016] TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ __IO hw_dma_tcdn_citer_elinkyes_t TCDn_CITER_ELINKYES; //!< [0x1016] TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ };
+ __IO hw_dma_tcdn_dlastsga_t TCDn_DLASTSGA; //!< [0x1018] TCD Last Destination Address Adjustment/Scatter Gather Address
+ __IO hw_dma_tcdn_csr_t TCDn_CSR; //!< [0x101C] TCD Control and Status
+ union {
+ __IO hw_dma_tcdn_biter_elinkno_t TCDn_BITER_ELINKNO; //!< [0x101E] TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ __IO hw_dma_tcdn_biter_elinkyes_t TCDn_BITER_ELINKYES; //!< [0x101E] TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ };
+ } TCD[16];
+} hw_dma_t;
+#pragma pack()
+
+//! @brief Macro to access all DMA registers.
+//! @param x DMA instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_DMA(0)</code>.
+#define HW_DMA(x) (*(hw_dma_t *) REGS_DMA_BASE(x))
+#endif
+
+#endif // __HW_DMA_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_dmamux.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,220 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_DMAMUX_REGISTERS_H__
+#define __HW_DMAMUX_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 DMAMUX
+ *
+ * DMA channel multiplexor
+ *
+ * Registers defined in this header file:
+ * - HW_DMAMUX_CHCFGn - Channel Configuration register
+ *
+ * - hw_dmamux_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_DMAMUX_BASE
+#define HW_DMAMUX_INSTANCE_COUNT (1U) //!< Number of instances of the DMAMUX module.
+#define HW_DMAMUX0 (0U) //!< Instance number for DMAMUX.
+#define REGS_DMAMUX0_BASE (0x40021000U) //!< Base address for DMAMUX.
+
+//! @brief Table of base addresses for DMAMUX instances.
+static const uint32_t __g_regs_DMAMUX_base_addresses[] = {
+ REGS_DMAMUX0_BASE,
+ };
+
+//! @brief Get the base address of DMAMUX by instance number.
+//! @param x DMAMUX instance number, from 0 through 0.
+#define REGS_DMAMUX_BASE(x) (__g_regs_DMAMUX_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of DMAMUX.
+#define REGS_DMAMUX_INSTANCE(b) ((b) == REGS_DMAMUX0_BASE ? HW_DMAMUX0 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_DMAMUX_CHCFGn - Channel Configuration register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_DMAMUX_CHCFGn - Channel Configuration register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Each of the DMA channels can be independently enabled/disabled and associated
+ * with one of the DMA slots (peripheral slots or always-on slots) in the
+ * system. Setting multiple CHCFG registers with the same source value will result in
+ * unpredictable behavior. This is true, even if a channel is disabled (ENBL==0).
+ * Before changing the trigger or source settings, a DMA channel must be disabled
+ * via CHCFGn[ENBL].
+ */
+typedef union _hw_dmamux_chcfgn
+{
+ uint8_t U;
+ struct _hw_dmamux_chcfgn_bitfields
+ {
+ uint8_t SOURCE : 6; //!< [5:0] DMA Channel Source (Slot)
+ uint8_t TRIG : 1; //!< [6] DMA Channel Trigger Enable
+ uint8_t ENBL : 1; //!< [7] DMA Channel Enable
+ } B;
+} hw_dmamux_chcfgn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire DMAMUX_CHCFGn register
+ */
+//@{
+#define HW_DMAMUX_CHCFGn_COUNT (16U)
+
+#define HW_DMAMUX_CHCFGn_ADDR(x, n) (REGS_DMAMUX_BASE(x) + 0x0U + (0x1U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_DMAMUX_CHCFGn(x, n) (*(__IO hw_dmamux_chcfgn_t *) HW_DMAMUX_CHCFGn_ADDR(x, n))
+#define HW_DMAMUX_CHCFGn_RD(x, n) (HW_DMAMUX_CHCFGn(x, n).U)
+#define HW_DMAMUX_CHCFGn_WR(x, n, v) (HW_DMAMUX_CHCFGn(x, n).U = (v))
+#define HW_DMAMUX_CHCFGn_SET(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) | (v)))
+#define HW_DMAMUX_CHCFGn_CLR(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) & ~(v)))
+#define HW_DMAMUX_CHCFGn_TOG(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual DMAMUX_CHCFGn bitfields
+ */
+
+/*!
+ * @name Register DMAMUX_CHCFGn, field SOURCE[5:0] (RW)
+ *
+ * Specifies which DMA source, if any, is routed to a particular DMA channel.
+ * See your device's chip configuration details for information about the
+ * peripherals and their slot numbers.
+ */
+//@{
+#define BP_DMAMUX_CHCFGn_SOURCE (0U) //!< Bit position for DMAMUX_CHCFGn_SOURCE.
+#define BM_DMAMUX_CHCFGn_SOURCE (0x3FU) //!< Bit mask for DMAMUX_CHCFGn_SOURCE.
+#define BS_DMAMUX_CHCFGn_SOURCE (6U) //!< Bit field size in bits for DMAMUX_CHCFGn_SOURCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMAMUX_CHCFGn_SOURCE field.
+#define BR_DMAMUX_CHCFGn_SOURCE(x, n) (HW_DMAMUX_CHCFGn(x, n).B.SOURCE)
+#endif
+
+//! @brief Format value for bitfield DMAMUX_CHCFGn_SOURCE.
+#define BF_DMAMUX_CHCFGn_SOURCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMAMUX_CHCFGn_SOURCE), uint8_t) & BM_DMAMUX_CHCFGn_SOURCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SOURCE field to a new value.
+#define BW_DMAMUX_CHCFGn_SOURCE(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, (HW_DMAMUX_CHCFGn_RD(x, n) & ~BM_DMAMUX_CHCFGn_SOURCE) | BF_DMAMUX_CHCFGn_SOURCE(v)))
+#endif
+//@}
+
+/*!
+ * @name Register DMAMUX_CHCFGn, field TRIG[6] (RW)
+ *
+ * Enables the periodic trigger capability for the triggered DMA channel.
+ *
+ * Values:
+ * - 0 - Triggering is disabled. If triggering is disabled and ENBL is set, the
+ * DMA Channel will simply route the specified source to the DMA channel.
+ * (Normal mode)
+ * - 1 - Triggering is enabled. If triggering is enabled and ENBL is set, the
+ * DMAMUX is in Periodic Trigger mode.
+ */
+//@{
+#define BP_DMAMUX_CHCFGn_TRIG (6U) //!< Bit position for DMAMUX_CHCFGn_TRIG.
+#define BM_DMAMUX_CHCFGn_TRIG (0x40U) //!< Bit mask for DMAMUX_CHCFGn_TRIG.
+#define BS_DMAMUX_CHCFGn_TRIG (1U) //!< Bit field size in bits for DMAMUX_CHCFGn_TRIG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMAMUX_CHCFGn_TRIG field.
+#define BR_DMAMUX_CHCFGn_TRIG(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG))
+#endif
+
+//! @brief Format value for bitfield DMAMUX_CHCFGn_TRIG.
+#define BF_DMAMUX_CHCFGn_TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMAMUX_CHCFGn_TRIG), uint8_t) & BM_DMAMUX_CHCFGn_TRIG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TRIG field to a new value.
+#define BW_DMAMUX_CHCFGn_TRIG(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register DMAMUX_CHCFGn, field ENBL[7] (RW)
+ *
+ * Enables the DMA channel.
+ *
+ * Values:
+ * - 0 - DMA channel is disabled. This mode is primarily used during
+ * configuration of the DMAMux. The DMA has separate channel enables/disables, which
+ * should be used to disable or reconfigure a DMA channel.
+ * - 1 - DMA channel is enabled
+ */
+//@{
+#define BP_DMAMUX_CHCFGn_ENBL (7U) //!< Bit position for DMAMUX_CHCFGn_ENBL.
+#define BM_DMAMUX_CHCFGn_ENBL (0x80U) //!< Bit mask for DMAMUX_CHCFGn_ENBL.
+#define BS_DMAMUX_CHCFGn_ENBL (1U) //!< Bit field size in bits for DMAMUX_CHCFGn_ENBL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the DMAMUX_CHCFGn_ENBL field.
+#define BR_DMAMUX_CHCFGn_ENBL(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL))
+#endif
+
+//! @brief Format value for bitfield DMAMUX_CHCFGn_ENBL.
+#define BF_DMAMUX_CHCFGn_ENBL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMAMUX_CHCFGn_ENBL), uint8_t) & BM_DMAMUX_CHCFGn_ENBL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ENBL field to a new value.
+#define BW_DMAMUX_CHCFGn_ENBL(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_dmamux_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All DMAMUX module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_dmamux
+{
+ __IO hw_dmamux_chcfgn_t CHCFGn[16]; //!< [0x0] Channel Configuration register
+} hw_dmamux_t;
+#pragma pack()
+
+//! @brief Macro to access all DMAMUX registers.
+//! @param x DMAMUX instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_DMAMUX(0)</code>.
+#define HW_DMAMUX(x) (*(hw_dmamux_t *) REGS_DMAMUX_BASE(x))
+#endif
+
+#endif // __HW_DMAMUX_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_enet.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,8441 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_ENET_REGISTERS_H__
+#define __HW_ENET_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 ENET
+ *
+ * Ethernet MAC-NET Core
+ *
+ * Registers defined in this header file:
+ * - HW_ENET_EIR - Interrupt Event Register
+ * - HW_ENET_EIMR - Interrupt Mask Register
+ * - HW_ENET_RDAR - Receive Descriptor Active Register
+ * - HW_ENET_TDAR - Transmit Descriptor Active Register
+ * - HW_ENET_ECR - Ethernet Control Register
+ * - HW_ENET_MMFR - MII Management Frame Register
+ * - HW_ENET_MSCR - MII Speed Control Register
+ * - HW_ENET_MIBC - MIB Control Register
+ * - HW_ENET_RCR - Receive Control Register
+ * - HW_ENET_TCR - Transmit Control Register
+ * - HW_ENET_PALR - Physical Address Lower Register
+ * - HW_ENET_PAUR - Physical Address Upper Register
+ * - HW_ENET_OPD - Opcode/Pause Duration Register
+ * - HW_ENET_IAUR - Descriptor Individual Upper Address Register
+ * - HW_ENET_IALR - Descriptor Individual Lower Address Register
+ * - HW_ENET_GAUR - Descriptor Group Upper Address Register
+ * - HW_ENET_GALR - Descriptor Group Lower Address Register
+ * - HW_ENET_TFWR - Transmit FIFO Watermark Register
+ * - HW_ENET_RDSR - Receive Descriptor Ring Start Register
+ * - HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
+ * - HW_ENET_MRBR - Maximum Receive Buffer Size Register
+ * - HW_ENET_RSFL - Receive FIFO Section Full Threshold
+ * - HW_ENET_RSEM - Receive FIFO Section Empty Threshold
+ * - HW_ENET_RAEM - Receive FIFO Almost Empty Threshold
+ * - HW_ENET_RAFL - Receive FIFO Almost Full Threshold
+ * - HW_ENET_TSEM - Transmit FIFO Section Empty Threshold
+ * - HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold
+ * - HW_ENET_TAFL - Transmit FIFO Almost Full Threshold
+ * - HW_ENET_TIPG - Transmit Inter-Packet Gap
+ * - HW_ENET_FTRL - Frame Truncation Length
+ * - HW_ENET_TACC - Transmit Accelerator Function Configuration
+ * - HW_ENET_RACC - Receive Accelerator Function Configuration
+ * - HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
+ * - HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
+ * - HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
+ * - HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
+ * - HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
+ * - HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
+ * - HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ * - HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
+ * - HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register
+ * - HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
+ * - HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
+ * - HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
+ * - HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
+ * - HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
+ * - HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
+ * - HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
+ * - HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register
+ * - HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
+ * - HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
+ * - HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
+ * - HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
+ * - HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
+ * - HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
+ * - HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
+ * - HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
+ * - HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
+ * - HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
+ * - HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
+ * - HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
+ * - HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
+ * - HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
+ * - HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
+ * - HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
+ * - HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ * - HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
+ * - HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
+ * - HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
+ * - HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
+ * - HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
+ * - HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
+ * - HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
+ * - HW_ENET_RMON_R_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
+ * - HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register
+ * - HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
+ * - HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
+ * - HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
+ * - HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
+ * - HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
+ * - HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
+ * - HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
+ * - HW_ENET_ATCR - Adjustable Timer Control Register
+ * - HW_ENET_ATVR - Timer Value Register
+ * - HW_ENET_ATOFF - Timer Offset Register
+ * - HW_ENET_ATPER - Timer Period Register
+ * - HW_ENET_ATCOR - Timer Correction Register
+ * - HW_ENET_ATINC - Time-Stamping Clock Period Register
+ * - HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame
+ * - HW_ENET_TGSR - Timer Global Status Register
+ * - HW_ENET_TCSRn - Timer Control Status Register
+ * - HW_ENET_TCCRn - Timer Compare Capture Register
+ *
+ * - hw_enet_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_ENET_BASE
+#define HW_ENET_INSTANCE_COUNT (1U) //!< Number of instances of the ENET module.
+#define HW_ENET0 (0U) //!< Instance number for ENET.
+#define REGS_ENET0_BASE (0x400C0000U) //!< Base address for ENET.
+
+//! @brief Table of base addresses for ENET instances.
+static const uint32_t __g_regs_ENET_base_addresses[] = {
+ REGS_ENET0_BASE,
+ };
+
+//! @brief Get the base address of ENET by instance number.
+//! @param x ENET instance number, from 0 through 0.
+#define REGS_ENET_BASE(x) (__g_regs_ENET_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of ENET.
+#define REGS_ENET_INSTANCE(b) ((b) == REGS_ENET0_BASE ? HW_ENET0 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_EIR - Interrupt Event Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_EIR - Interrupt Event Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When an event occurs that sets a bit in EIR, an interrupt occurs if the
+ * corresponding bit in the interrupt mask register (EIMR) is also set. Writing a 1 to
+ * an EIR bit clears it; writing 0 has no effect. This register is cleared upon
+ * hardware reset. TxBD[INT] and RxBD[INT] must be set to 1 to allow setting the
+ * corresponding EIR register flags in enhanced mode, ENET_ECR[EN1588] = 1.
+ * Legacy mode does not require these flags to be enabled.
+ */
+typedef union _hw_enet_eir
+{
+ uint32_t U;
+ struct _hw_enet_eir_bitfields
+ {
+ uint32_t RESERVED0 : 15; //!< [14:0]
+ uint32_t TS_TIMER : 1; //!< [15] Timestamp Timer
+ uint32_t TS_AVAIL : 1; //!< [16] Transmit Timestamp Available
+ uint32_t WAKEUP : 1; //!< [17] Node Wakeup Request Indication
+ uint32_t PLR : 1; //!< [18] Payload Receive Error
+ uint32_t UN : 1; //!< [19] Transmit FIFO Underrun
+ uint32_t RL : 1; //!< [20] Collision Retry Limit
+ uint32_t LC : 1; //!< [21] Late Collision
+ uint32_t EBERR : 1; //!< [22] Ethernet Bus Error
+ uint32_t MII : 1; //!< [23] MII Interrupt.
+ uint32_t RXB : 1; //!< [24] Receive Buffer Interrupt
+ uint32_t RXF : 1; //!< [25] Receive Frame Interrupt
+ uint32_t TXB : 1; //!< [26] Transmit Buffer Interrupt
+ uint32_t TXF : 1; //!< [27] Transmit Frame Interrupt
+ uint32_t GRA : 1; //!< [28] Graceful Stop Complete
+ uint32_t BABT : 1; //!< [29] Babbling Transmit Error
+ uint32_t BABR : 1; //!< [30] Babbling Receive Error
+ uint32_t RESERVED1 : 1; //!< [31]
+ } B;
+} hw_enet_eir_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_EIR register
+ */
+//@{
+#define HW_ENET_EIR_ADDR(x) (REGS_ENET_BASE(x) + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_EIR(x) (*(__IO hw_enet_eir_t *) HW_ENET_EIR_ADDR(x))
+#define HW_ENET_EIR_RD(x) (HW_ENET_EIR(x).U)
+#define HW_ENET_EIR_WR(x, v) (HW_ENET_EIR(x).U = (v))
+#define HW_ENET_EIR_SET(x, v) (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) | (v)))
+#define HW_ENET_EIR_CLR(x, v) (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) & ~(v)))
+#define HW_ENET_EIR_TOG(x, v) (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_EIR bitfields
+ */
+
+/*!
+ * @name Register ENET_EIR, field TS_TIMER[15] (W1C)
+ *
+ * The adjustable timer reached the period event. A period event interrupt can
+ * be generated if ATCR[PEREN] is set and the timer wraps according to the
+ * periodic setting in the ATPER register. Set the timer period value before setting
+ * ATCR[PEREN].
+ */
+//@{
+#define BP_ENET_EIR_TS_TIMER (15U) //!< Bit position for ENET_EIR_TS_TIMER.
+#define BM_ENET_EIR_TS_TIMER (0x00008000U) //!< Bit mask for ENET_EIR_TS_TIMER.
+#define BS_ENET_EIR_TS_TIMER (1U) //!< Bit field size in bits for ENET_EIR_TS_TIMER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_TS_TIMER field.
+#define BR_ENET_EIR_TS_TIMER(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_TIMER))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_TS_TIMER.
+#define BF_ENET_EIR_TS_TIMER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_TS_TIMER), uint32_t) & BM_ENET_EIR_TS_TIMER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TS_TIMER field to a new value.
+#define BW_ENET_EIR_TS_TIMER(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_TIMER) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field TS_AVAIL[16] (W1C)
+ *
+ * Indicates that the timestamp of the last transmitted timing frame is
+ * available in the ATSTMP register.
+ */
+//@{
+#define BP_ENET_EIR_TS_AVAIL (16U) //!< Bit position for ENET_EIR_TS_AVAIL.
+#define BM_ENET_EIR_TS_AVAIL (0x00010000U) //!< Bit mask for ENET_EIR_TS_AVAIL.
+#define BS_ENET_EIR_TS_AVAIL (1U) //!< Bit field size in bits for ENET_EIR_TS_AVAIL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_TS_AVAIL field.
+#define BR_ENET_EIR_TS_AVAIL(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_AVAIL))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_TS_AVAIL.
+#define BF_ENET_EIR_TS_AVAIL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_TS_AVAIL), uint32_t) & BM_ENET_EIR_TS_AVAIL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TS_AVAIL field to a new value.
+#define BW_ENET_EIR_TS_AVAIL(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_AVAIL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field WAKEUP[17] (W1C)
+ *
+ * Read-only status bit to indicate that a magic packet has been detected. Will
+ * act only if ECR[MAGICEN] is set.
+ */
+//@{
+#define BP_ENET_EIR_WAKEUP (17U) //!< Bit position for ENET_EIR_WAKEUP.
+#define BM_ENET_EIR_WAKEUP (0x00020000U) //!< Bit mask for ENET_EIR_WAKEUP.
+#define BS_ENET_EIR_WAKEUP (1U) //!< Bit field size in bits for ENET_EIR_WAKEUP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_WAKEUP field.
+#define BR_ENET_EIR_WAKEUP(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_WAKEUP))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_WAKEUP.
+#define BF_ENET_EIR_WAKEUP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_WAKEUP), uint32_t) & BM_ENET_EIR_WAKEUP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WAKEUP field to a new value.
+#define BW_ENET_EIR_WAKEUP(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_WAKEUP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field PLR[18] (W1C)
+ *
+ * Indicates a frame was received with a payload length error. See Frame
+ * Length/Type Verification: Payload Length Check for more information.
+ */
+//@{
+#define BP_ENET_EIR_PLR (18U) //!< Bit position for ENET_EIR_PLR.
+#define BM_ENET_EIR_PLR (0x00040000U) //!< Bit mask for ENET_EIR_PLR.
+#define BS_ENET_EIR_PLR (1U) //!< Bit field size in bits for ENET_EIR_PLR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_PLR field.
+#define BR_ENET_EIR_PLR(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_PLR))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_PLR.
+#define BF_ENET_EIR_PLR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_PLR), uint32_t) & BM_ENET_EIR_PLR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PLR field to a new value.
+#define BW_ENET_EIR_PLR(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_PLR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field UN[19] (W1C)
+ *
+ * Indicates the transmit FIFO became empty before the complete frame was
+ * transmitted. A bad CRC is appended to the frame fragment and the remainder of the
+ * frame is discarded.
+ */
+//@{
+#define BP_ENET_EIR_UN (19U) //!< Bit position for ENET_EIR_UN.
+#define BM_ENET_EIR_UN (0x00080000U) //!< Bit mask for ENET_EIR_UN.
+#define BS_ENET_EIR_UN (1U) //!< Bit field size in bits for ENET_EIR_UN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_UN field.
+#define BR_ENET_EIR_UN(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_UN))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_UN.
+#define BF_ENET_EIR_UN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_UN), uint32_t) & BM_ENET_EIR_UN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UN field to a new value.
+#define BW_ENET_EIR_UN(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_UN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field RL[20] (W1C)
+ *
+ * Indicates a collision occurred on each of 16 successive attempts to transmit
+ * the frame. The frame is discarded without being transmitted and transmission
+ * of the next frame commences. This error can only occur in half-duplex mode.
+ */
+//@{
+#define BP_ENET_EIR_RL (20U) //!< Bit position for ENET_EIR_RL.
+#define BM_ENET_EIR_RL (0x00100000U) //!< Bit mask for ENET_EIR_RL.
+#define BS_ENET_EIR_RL (1U) //!< Bit field size in bits for ENET_EIR_RL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_RL field.
+#define BR_ENET_EIR_RL(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RL))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_RL.
+#define BF_ENET_EIR_RL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_RL), uint32_t) & BM_ENET_EIR_RL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RL field to a new value.
+#define BW_ENET_EIR_RL(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field LC[21] (W1C)
+ *
+ * Indicates a collision occurred beyond the collision window (slot time) in
+ * half-duplex mode. The frame truncates with a bad CRC and the remainder of the
+ * frame is discarded.
+ */
+//@{
+#define BP_ENET_EIR_LC (21U) //!< Bit position for ENET_EIR_LC.
+#define BM_ENET_EIR_LC (0x00200000U) //!< Bit mask for ENET_EIR_LC.
+#define BS_ENET_EIR_LC (1U) //!< Bit field size in bits for ENET_EIR_LC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_LC field.
+#define BR_ENET_EIR_LC(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_LC))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_LC.
+#define BF_ENET_EIR_LC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_LC), uint32_t) & BM_ENET_EIR_LC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LC field to a new value.
+#define BW_ENET_EIR_LC(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_LC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field EBERR[22] (W1C)
+ *
+ * Indicates a system bus error occurred when a uDMA transaction is underway.
+ * When this bit is set, ECR[ETHEREN] is cleared, halting frame processing by the
+ * MAC. When this occurs, software must ensure proper actions, possibly resetting
+ * the system, to resume normal operation.
+ */
+//@{
+#define BP_ENET_EIR_EBERR (22U) //!< Bit position for ENET_EIR_EBERR.
+#define BM_ENET_EIR_EBERR (0x00400000U) //!< Bit mask for ENET_EIR_EBERR.
+#define BS_ENET_EIR_EBERR (1U) //!< Bit field size in bits for ENET_EIR_EBERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_EBERR field.
+#define BR_ENET_EIR_EBERR(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_EBERR))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_EBERR.
+#define BF_ENET_EIR_EBERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_EBERR), uint32_t) & BM_ENET_EIR_EBERR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EBERR field to a new value.
+#define BW_ENET_EIR_EBERR(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_EBERR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field MII[23] (W1C)
+ *
+ * Indicates that the MII has completed the data transfer requested.
+ */
+//@{
+#define BP_ENET_EIR_MII (23U) //!< Bit position for ENET_EIR_MII.
+#define BM_ENET_EIR_MII (0x00800000U) //!< Bit mask for ENET_EIR_MII.
+#define BS_ENET_EIR_MII (1U) //!< Bit field size in bits for ENET_EIR_MII.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_MII field.
+#define BR_ENET_EIR_MII(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_MII))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_MII.
+#define BF_ENET_EIR_MII(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_MII), uint32_t) & BM_ENET_EIR_MII)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MII field to a new value.
+#define BW_ENET_EIR_MII(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_MII) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field RXB[24] (W1C)
+ *
+ * Indicates a receive buffer descriptor is not the last in the frame has been
+ * updated.
+ */
+//@{
+#define BP_ENET_EIR_RXB (24U) //!< Bit position for ENET_EIR_RXB.
+#define BM_ENET_EIR_RXB (0x01000000U) //!< Bit mask for ENET_EIR_RXB.
+#define BS_ENET_EIR_RXB (1U) //!< Bit field size in bits for ENET_EIR_RXB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_RXB field.
+#define BR_ENET_EIR_RXB(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXB))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_RXB.
+#define BF_ENET_EIR_RXB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_RXB), uint32_t) & BM_ENET_EIR_RXB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXB field to a new value.
+#define BW_ENET_EIR_RXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXB) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field RXF[25] (W1C)
+ *
+ * Indicates a frame has been received and the last corresponding buffer
+ * descriptor has been updated.
+ */
+//@{
+#define BP_ENET_EIR_RXF (25U) //!< Bit position for ENET_EIR_RXF.
+#define BM_ENET_EIR_RXF (0x02000000U) //!< Bit mask for ENET_EIR_RXF.
+#define BS_ENET_EIR_RXF (1U) //!< Bit field size in bits for ENET_EIR_RXF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_RXF field.
+#define BR_ENET_EIR_RXF(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXF))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_RXF.
+#define BF_ENET_EIR_RXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_RXF), uint32_t) & BM_ENET_EIR_RXF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXF field to a new value.
+#define BW_ENET_EIR_RXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field TXB[26] (W1C)
+ *
+ * Indicates a transmit buffer descriptor has been updated.
+ */
+//@{
+#define BP_ENET_EIR_TXB (26U) //!< Bit position for ENET_EIR_TXB.
+#define BM_ENET_EIR_TXB (0x04000000U) //!< Bit mask for ENET_EIR_TXB.
+#define BS_ENET_EIR_TXB (1U) //!< Bit field size in bits for ENET_EIR_TXB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_TXB field.
+#define BR_ENET_EIR_TXB(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXB))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_TXB.
+#define BF_ENET_EIR_TXB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_TXB), uint32_t) & BM_ENET_EIR_TXB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXB field to a new value.
+#define BW_ENET_EIR_TXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXB) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field TXF[27] (W1C)
+ *
+ * Indicates a frame has been transmitted and the last corresponding buffer
+ * descriptor has been updated.
+ */
+//@{
+#define BP_ENET_EIR_TXF (27U) //!< Bit position for ENET_EIR_TXF.
+#define BM_ENET_EIR_TXF (0x08000000U) //!< Bit mask for ENET_EIR_TXF.
+#define BS_ENET_EIR_TXF (1U) //!< Bit field size in bits for ENET_EIR_TXF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_TXF field.
+#define BR_ENET_EIR_TXF(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXF))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_TXF.
+#define BF_ENET_EIR_TXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_TXF), uint32_t) & BM_ENET_EIR_TXF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXF field to a new value.
+#define BW_ENET_EIR_TXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field GRA[28] (W1C)
+ *
+ * This interrupt is asserted after the transmitter is put into a pause state
+ * after completion of the frame currently being transmitted. See Graceful Transmit
+ * Stop (GTS) for conditions that lead to graceful stop. The GRA interrupt is
+ * asserted only when the TX transitions into the stopped state. If this bit is
+ * cleared by writing 1 and the TX is still stopped, the bit is not set again.
+ */
+//@{
+#define BP_ENET_EIR_GRA (28U) //!< Bit position for ENET_EIR_GRA.
+#define BM_ENET_EIR_GRA (0x10000000U) //!< Bit mask for ENET_EIR_GRA.
+#define BS_ENET_EIR_GRA (1U) //!< Bit field size in bits for ENET_EIR_GRA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_GRA field.
+#define BR_ENET_EIR_GRA(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_GRA))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_GRA.
+#define BF_ENET_EIR_GRA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_GRA), uint32_t) & BM_ENET_EIR_GRA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GRA field to a new value.
+#define BW_ENET_EIR_GRA(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_GRA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field BABT[29] (W1C)
+ *
+ * Indicates the transmitted frame length exceeds RCR[MAX_FL] bytes. Usually
+ * this condition is caused when a frame that is too long is placed into the
+ * transmit data buffer(s). Truncation does not occur.
+ */
+//@{
+#define BP_ENET_EIR_BABT (29U) //!< Bit position for ENET_EIR_BABT.
+#define BM_ENET_EIR_BABT (0x20000000U) //!< Bit mask for ENET_EIR_BABT.
+#define BS_ENET_EIR_BABT (1U) //!< Bit field size in bits for ENET_EIR_BABT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_BABT field.
+#define BR_ENET_EIR_BABT(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABT))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_BABT.
+#define BF_ENET_EIR_BABT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_BABT), uint32_t) & BM_ENET_EIR_BABT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BABT field to a new value.
+#define BW_ENET_EIR_BABT(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIR, field BABR[30] (W1C)
+ *
+ * Indicates a frame was received with length in excess of RCR[MAX_FL] bytes.
+ */
+//@{
+#define BP_ENET_EIR_BABR (30U) //!< Bit position for ENET_EIR_BABR.
+#define BM_ENET_EIR_BABR (0x40000000U) //!< Bit mask for ENET_EIR_BABR.
+#define BS_ENET_EIR_BABR (1U) //!< Bit field size in bits for ENET_EIR_BABR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIR_BABR field.
+#define BR_ENET_EIR_BABR(x) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABR))
+#endif
+
+//! @brief Format value for bitfield ENET_EIR_BABR.
+#define BF_ENET_EIR_BABR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIR_BABR), uint32_t) & BM_ENET_EIR_BABR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BABR field to a new value.
+#define BW_ENET_EIR_BABR(x, v) (BITBAND_ACCESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABR) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_EIMR - Interrupt Mask Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_EIMR - Interrupt Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * EIMR controls which interrupt events are allowed to generate actual
+ * interrupts. A hardware reset clears this register. If the corresponding bits in the EIR
+ * and EIMR registers are set, an interrupt is generated. The interrupt signal
+ * remains asserted until a 1 is written to the EIR field (write 1 to clear) or a
+ * 0 is written to the EIMR field.
+ */
+typedef union _hw_enet_eimr
+{
+ uint32_t U;
+ struct _hw_enet_eimr_bitfields
+ {
+ uint32_t RESERVED0 : 15; //!< [14:0]
+ uint32_t TS_TIMER : 1; //!< [15] TS_TIMER Interrupt Mask
+ uint32_t TS_AVAIL : 1; //!< [16] TS_AVAIL Interrupt Mask
+ uint32_t WAKEUP : 1; //!< [17] WAKEUP Interrupt Mask
+ uint32_t PLR : 1; //!< [18] PLR Interrupt Mask
+ uint32_t UN : 1; //!< [19] UN Interrupt Mask
+ uint32_t RL : 1; //!< [20] RL Interrupt Mask
+ uint32_t LC : 1; //!< [21] LC Interrupt Mask
+ uint32_t EBERR : 1; //!< [22] EBERR Interrupt Mask
+ uint32_t MII : 1; //!< [23] MII Interrupt Mask
+ uint32_t RXB : 1; //!< [24] RXB Interrupt Mask
+ uint32_t RXF : 1; //!< [25] RXF Interrupt Mask
+ uint32_t TXB : 1; //!< [26] TXB Interrupt Mask
+ uint32_t TXF : 1; //!< [27] TXF Interrupt Mask
+ uint32_t GRA : 1; //!< [28] GRA Interrupt Mask
+ uint32_t BABT : 1; //!< [29] BABT Interrupt Mask
+ uint32_t BABR : 1; //!< [30] BABR Interrupt Mask
+ uint32_t RESERVED1 : 1; //!< [31]
+ } B;
+} hw_enet_eimr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_EIMR register
+ */
+//@{
+#define HW_ENET_EIMR_ADDR(x) (REGS_ENET_BASE(x) + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_EIMR(x) (*(__IO hw_enet_eimr_t *) HW_ENET_EIMR_ADDR(x))
+#define HW_ENET_EIMR_RD(x) (HW_ENET_EIMR(x).U)
+#define HW_ENET_EIMR_WR(x, v) (HW_ENET_EIMR(x).U = (v))
+#define HW_ENET_EIMR_SET(x, v) (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) | (v)))
+#define HW_ENET_EIMR_CLR(x, v) (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) & ~(v)))
+#define HW_ENET_EIMR_TOG(x, v) (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_EIMR bitfields
+ */
+
+/*!
+ * @name Register ENET_EIMR, field TS_TIMER[15] (RW)
+ *
+ * Corresponds to interrupt source EIR[TS_TIMER] register and determines whether
+ * an interrupt condition can generate an interrupt. At every module clock, the
+ * EIR samples the signal generated by the interrupting source. The corresponding
+ * EIR TS_TIMER field reflects the state of the interrupt signal even if the
+ * corresponding EIMR field is cleared.
+ */
+//@{
+#define BP_ENET_EIMR_TS_TIMER (15U) //!< Bit position for ENET_EIMR_TS_TIMER.
+#define BM_ENET_EIMR_TS_TIMER (0x00008000U) //!< Bit mask for ENET_EIMR_TS_TIMER.
+#define BS_ENET_EIMR_TS_TIMER (1U) //!< Bit field size in bits for ENET_EIMR_TS_TIMER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_TS_TIMER field.
+#define BR_ENET_EIMR_TS_TIMER(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_TIMER))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_TS_TIMER.
+#define BF_ENET_EIMR_TS_TIMER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_TS_TIMER), uint32_t) & BM_ENET_EIMR_TS_TIMER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TS_TIMER field to a new value.
+#define BW_ENET_EIMR_TS_TIMER(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_TIMER) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field TS_AVAIL[16] (RW)
+ *
+ * Corresponds to interrupt source EIR[TS_AVAIL] register and determines whether
+ * an interrupt condition can generate an interrupt. At every module clock, the
+ * EIR samples the signal generated by the interrupting source. The corresponding
+ * EIR TS_AVAIL field reflects the state of the interrupt signal even if the
+ * corresponding EIMR field is cleared.
+ */
+//@{
+#define BP_ENET_EIMR_TS_AVAIL (16U) //!< Bit position for ENET_EIMR_TS_AVAIL.
+#define BM_ENET_EIMR_TS_AVAIL (0x00010000U) //!< Bit mask for ENET_EIMR_TS_AVAIL.
+#define BS_ENET_EIMR_TS_AVAIL (1U) //!< Bit field size in bits for ENET_EIMR_TS_AVAIL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_TS_AVAIL field.
+#define BR_ENET_EIMR_TS_AVAIL(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_AVAIL))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_TS_AVAIL.
+#define BF_ENET_EIMR_TS_AVAIL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_TS_AVAIL), uint32_t) & BM_ENET_EIMR_TS_AVAIL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TS_AVAIL field to a new value.
+#define BW_ENET_EIMR_TS_AVAIL(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_AVAIL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field WAKEUP[17] (RW)
+ *
+ * Corresponds to interrupt source EIR[WAKEUP] register and determines whether
+ * an interrupt condition can generate an interrupt. At every module clock, the
+ * EIR samples the signal generated by the interrupting source. The corresponding
+ * EIR WAKEUP field reflects the state of the interrupt signal even if the
+ * corresponding EIMR field is cleared.
+ */
+//@{
+#define BP_ENET_EIMR_WAKEUP (17U) //!< Bit position for ENET_EIMR_WAKEUP.
+#define BM_ENET_EIMR_WAKEUP (0x00020000U) //!< Bit mask for ENET_EIMR_WAKEUP.
+#define BS_ENET_EIMR_WAKEUP (1U) //!< Bit field size in bits for ENET_EIMR_WAKEUP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_WAKEUP field.
+#define BR_ENET_EIMR_WAKEUP(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_WAKEUP))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_WAKEUP.
+#define BF_ENET_EIMR_WAKEUP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_WAKEUP), uint32_t) & BM_ENET_EIMR_WAKEUP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WAKEUP field to a new value.
+#define BW_ENET_EIMR_WAKEUP(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_WAKEUP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field PLR[18] (RW)
+ *
+ * Corresponds to interrupt source EIR[PLR] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR PLR field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+//@{
+#define BP_ENET_EIMR_PLR (18U) //!< Bit position for ENET_EIMR_PLR.
+#define BM_ENET_EIMR_PLR (0x00040000U) //!< Bit mask for ENET_EIMR_PLR.
+#define BS_ENET_EIMR_PLR (1U) //!< Bit field size in bits for ENET_EIMR_PLR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_PLR field.
+#define BR_ENET_EIMR_PLR(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_PLR))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_PLR.
+#define BF_ENET_EIMR_PLR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_PLR), uint32_t) & BM_ENET_EIMR_PLR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PLR field to a new value.
+#define BW_ENET_EIMR_PLR(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_PLR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field UN[19] (RW)
+ *
+ * Corresponds to interrupt source EIR[UN] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples the
+ * signal generated by the interrupting source. The corresponding EIR UN field
+ * reflects the state of the interrupt signal even if the corresponding EIMR field
+ * is cleared.
+ */
+//@{
+#define BP_ENET_EIMR_UN (19U) //!< Bit position for ENET_EIMR_UN.
+#define BM_ENET_EIMR_UN (0x00080000U) //!< Bit mask for ENET_EIMR_UN.
+#define BS_ENET_EIMR_UN (1U) //!< Bit field size in bits for ENET_EIMR_UN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_UN field.
+#define BR_ENET_EIMR_UN(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_UN))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_UN.
+#define BF_ENET_EIMR_UN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_UN), uint32_t) & BM_ENET_EIMR_UN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UN field to a new value.
+#define BW_ENET_EIMR_UN(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_UN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field RL[20] (RW)
+ *
+ * Corresponds to interrupt source EIR[RL] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples the
+ * signal generated by the interrupting source. The corresponding EIR RL field
+ * reflects the state of the interrupt signal even if the corresponding EIMR field
+ * is cleared.
+ */
+//@{
+#define BP_ENET_EIMR_RL (20U) //!< Bit position for ENET_EIMR_RL.
+#define BM_ENET_EIMR_RL (0x00100000U) //!< Bit mask for ENET_EIMR_RL.
+#define BS_ENET_EIMR_RL (1U) //!< Bit field size in bits for ENET_EIMR_RL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_RL field.
+#define BR_ENET_EIMR_RL(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RL))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_RL.
+#define BF_ENET_EIMR_RL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_RL), uint32_t) & BM_ENET_EIMR_RL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RL field to a new value.
+#define BW_ENET_EIMR_RL(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field LC[21] (RW)
+ *
+ * Corresponds to interrupt source EIR[LC] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples the
+ * signal generated by the interrupting source. The corresponding EIR LC field
+ * reflects the state of the interrupt signal even if the corresponding EIMR field
+ * is cleared.
+ */
+//@{
+#define BP_ENET_EIMR_LC (21U) //!< Bit position for ENET_EIMR_LC.
+#define BM_ENET_EIMR_LC (0x00200000U) //!< Bit mask for ENET_EIMR_LC.
+#define BS_ENET_EIMR_LC (1U) //!< Bit field size in bits for ENET_EIMR_LC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_LC field.
+#define BR_ENET_EIMR_LC(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_LC))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_LC.
+#define BF_ENET_EIMR_LC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_LC), uint32_t) & BM_ENET_EIMR_LC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LC field to a new value.
+#define BW_ENET_EIMR_LC(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_LC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field EBERR[22] (RW)
+ *
+ * Corresponds to interrupt source EIR[EBERR] and determines whether an
+ * interrupt condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR EBERR
+ * field reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+//@{
+#define BP_ENET_EIMR_EBERR (22U) //!< Bit position for ENET_EIMR_EBERR.
+#define BM_ENET_EIMR_EBERR (0x00400000U) //!< Bit mask for ENET_EIMR_EBERR.
+#define BS_ENET_EIMR_EBERR (1U) //!< Bit field size in bits for ENET_EIMR_EBERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_EBERR field.
+#define BR_ENET_EIMR_EBERR(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_EBERR))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_EBERR.
+#define BF_ENET_EIMR_EBERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_EBERR), uint32_t) & BM_ENET_EIMR_EBERR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EBERR field to a new value.
+#define BW_ENET_EIMR_EBERR(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_EBERR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field MII[23] (RW)
+ *
+ * Corresponds to interrupt source EIR[MII] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR MII field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+//@{
+#define BP_ENET_EIMR_MII (23U) //!< Bit position for ENET_EIMR_MII.
+#define BM_ENET_EIMR_MII (0x00800000U) //!< Bit mask for ENET_EIMR_MII.
+#define BS_ENET_EIMR_MII (1U) //!< Bit field size in bits for ENET_EIMR_MII.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_MII field.
+#define BR_ENET_EIMR_MII(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_MII))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_MII.
+#define BF_ENET_EIMR_MII(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_MII), uint32_t) & BM_ENET_EIMR_MII)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MII field to a new value.
+#define BW_ENET_EIMR_MII(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_MII) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field RXB[24] (RW)
+ *
+ * Corresponds to interrupt source EIR[RXB] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR RXB field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+//@{
+#define BP_ENET_EIMR_RXB (24U) //!< Bit position for ENET_EIMR_RXB.
+#define BM_ENET_EIMR_RXB (0x01000000U) //!< Bit mask for ENET_EIMR_RXB.
+#define BS_ENET_EIMR_RXB (1U) //!< Bit field size in bits for ENET_EIMR_RXB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_RXB field.
+#define BR_ENET_EIMR_RXB(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXB))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_RXB.
+#define BF_ENET_EIMR_RXB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_RXB), uint32_t) & BM_ENET_EIMR_RXB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXB field to a new value.
+#define BW_ENET_EIMR_RXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXB) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field RXF[25] (RW)
+ *
+ * Corresponds to interrupt source EIR[RXF] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR RXF field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+//@{
+#define BP_ENET_EIMR_RXF (25U) //!< Bit position for ENET_EIMR_RXF.
+#define BM_ENET_EIMR_RXF (0x02000000U) //!< Bit mask for ENET_EIMR_RXF.
+#define BS_ENET_EIMR_RXF (1U) //!< Bit field size in bits for ENET_EIMR_RXF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_RXF field.
+#define BR_ENET_EIMR_RXF(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXF))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_RXF.
+#define BF_ENET_EIMR_RXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_RXF), uint32_t) & BM_ENET_EIMR_RXF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXF field to a new value.
+#define BW_ENET_EIMR_RXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field TXB[26] (RW)
+ *
+ * Corresponds to interrupt source EIR[TXB] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR TXF field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0 - The corresponding interrupt source is masked.
+ * - 1 - The corresponding interrupt source is not masked.
+ */
+//@{
+#define BP_ENET_EIMR_TXB (26U) //!< Bit position for ENET_EIMR_TXB.
+#define BM_ENET_EIMR_TXB (0x04000000U) //!< Bit mask for ENET_EIMR_TXB.
+#define BS_ENET_EIMR_TXB (1U) //!< Bit field size in bits for ENET_EIMR_TXB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_TXB field.
+#define BR_ENET_EIMR_TXB(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXB))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_TXB.
+#define BF_ENET_EIMR_TXB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_TXB), uint32_t) & BM_ENET_EIMR_TXB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXB field to a new value.
+#define BW_ENET_EIMR_TXB(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXB) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field TXF[27] (RW)
+ *
+ * Corresponds to interrupt source EIR[TXF] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR TXF field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0 - The corresponding interrupt source is masked.
+ * - 1 - The corresponding interrupt source is not masked.
+ */
+//@{
+#define BP_ENET_EIMR_TXF (27U) //!< Bit position for ENET_EIMR_TXF.
+#define BM_ENET_EIMR_TXF (0x08000000U) //!< Bit mask for ENET_EIMR_TXF.
+#define BS_ENET_EIMR_TXF (1U) //!< Bit field size in bits for ENET_EIMR_TXF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_TXF field.
+#define BR_ENET_EIMR_TXF(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXF))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_TXF.
+#define BF_ENET_EIMR_TXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_TXF), uint32_t) & BM_ENET_EIMR_TXF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXF field to a new value.
+#define BW_ENET_EIMR_TXF(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field GRA[28] (RW)
+ *
+ * Corresponds to interrupt source EIR[GRA] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR GRA field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0 - The corresponding interrupt source is masked.
+ * - 1 - The corresponding interrupt source is not masked.
+ */
+//@{
+#define BP_ENET_EIMR_GRA (28U) //!< Bit position for ENET_EIMR_GRA.
+#define BM_ENET_EIMR_GRA (0x10000000U) //!< Bit mask for ENET_EIMR_GRA.
+#define BS_ENET_EIMR_GRA (1U) //!< Bit field size in bits for ENET_EIMR_GRA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_GRA field.
+#define BR_ENET_EIMR_GRA(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_GRA))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_GRA.
+#define BF_ENET_EIMR_GRA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_GRA), uint32_t) & BM_ENET_EIMR_GRA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GRA field to a new value.
+#define BW_ENET_EIMR_GRA(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_GRA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field BABT[29] (RW)
+ *
+ * Corresponds to interrupt source EIR[BABT] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR BABT
+ * field reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0 - The corresponding interrupt source is masked.
+ * - 1 - The corresponding interrupt source is not masked.
+ */
+//@{
+#define BP_ENET_EIMR_BABT (29U) //!< Bit position for ENET_EIMR_BABT.
+#define BM_ENET_EIMR_BABT (0x20000000U) //!< Bit mask for ENET_EIMR_BABT.
+#define BS_ENET_EIMR_BABT (1U) //!< Bit field size in bits for ENET_EIMR_BABT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_BABT field.
+#define BR_ENET_EIMR_BABT(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABT))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_BABT.
+#define BF_ENET_EIMR_BABT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_BABT), uint32_t) & BM_ENET_EIMR_BABT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BABT field to a new value.
+#define BW_ENET_EIMR_BABT(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_EIMR, field BABR[30] (RW)
+ *
+ * Corresponds to interrupt source EIR[BABR] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR BABR
+ * field reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0 - The corresponding interrupt source is masked.
+ * - 1 - The corresponding interrupt source is not masked.
+ */
+//@{
+#define BP_ENET_EIMR_BABR (30U) //!< Bit position for ENET_EIMR_BABR.
+#define BM_ENET_EIMR_BABR (0x40000000U) //!< Bit mask for ENET_EIMR_BABR.
+#define BS_ENET_EIMR_BABR (1U) //!< Bit field size in bits for ENET_EIMR_BABR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_EIMR_BABR field.
+#define BR_ENET_EIMR_BABR(x) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABR))
+#endif
+
+//! @brief Format value for bitfield ENET_EIMR_BABR.
+#define BF_ENET_EIMR_BABR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_EIMR_BABR), uint32_t) & BM_ENET_EIMR_BABR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BABR field to a new value.
+#define BW_ENET_EIMR_BABR(x, v) (BITBAND_ACCESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABR) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RDAR - Receive Descriptor Active Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RDAR - Receive Descriptor Active Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RDAR is a command register, written by the user, to indicate that the receive
+ * descriptor ring has been updated, that is, that the driver produced empty
+ * receive buffers with the empty bit set.
+ */
+typedef union _hw_enet_rdar
+{
+ uint32_t U;
+ struct _hw_enet_rdar_bitfields
+ {
+ uint32_t RESERVED0 : 24; //!< [23:0]
+ uint32_t RDAR : 1; //!< [24] Receive Descriptor Active
+ uint32_t RESERVED1 : 7; //!< [31:25]
+ } B;
+} hw_enet_rdar_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RDAR register
+ */
+//@{
+#define HW_ENET_RDAR_ADDR(x) (REGS_ENET_BASE(x) + 0x10U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RDAR(x) (*(__IO hw_enet_rdar_t *) HW_ENET_RDAR_ADDR(x))
+#define HW_ENET_RDAR_RD(x) (HW_ENET_RDAR(x).U)
+#define HW_ENET_RDAR_WR(x, v) (HW_ENET_RDAR(x).U = (v))
+#define HW_ENET_RDAR_SET(x, v) (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) | (v)))
+#define HW_ENET_RDAR_CLR(x, v) (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) & ~(v)))
+#define HW_ENET_RDAR_TOG(x, v) (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RDAR bitfields
+ */
+
+/*!
+ * @name Register ENET_RDAR, field RDAR[24] (RW)
+ *
+ * Always set to 1 when this register is written, regardless of the value
+ * written. This field is cleared by the MAC device when no additional empty
+ * descriptors remain in the receive ring. It is also cleared when ECR[ETHEREN] transitions
+ * from set to cleared or when ECR[RESET] is set.
+ */
+//@{
+#define BP_ENET_RDAR_RDAR (24U) //!< Bit position for ENET_RDAR_RDAR.
+#define BM_ENET_RDAR_RDAR (0x01000000U) //!< Bit mask for ENET_RDAR_RDAR.
+#define BS_ENET_RDAR_RDAR (1U) //!< Bit field size in bits for ENET_RDAR_RDAR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RDAR_RDAR field.
+#define BR_ENET_RDAR_RDAR(x) (BITBAND_ACCESS32(HW_ENET_RDAR_ADDR(x), BP_ENET_RDAR_RDAR))
+#endif
+
+//! @brief Format value for bitfield ENET_RDAR_RDAR.
+#define BF_ENET_RDAR_RDAR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RDAR_RDAR), uint32_t) & BM_ENET_RDAR_RDAR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RDAR field to a new value.
+#define BW_ENET_RDAR_RDAR(x, v) (BITBAND_ACCESS32(HW_ENET_RDAR_ADDR(x), BP_ENET_RDAR_RDAR) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_TDAR - Transmit Descriptor Active Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_TDAR - Transmit Descriptor Active Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The TDAR is a command register that the user writes to indicate that the
+ * transmit descriptor ring has been updated, that is, that transmit buffers have
+ * been produced by the driver with the ready bit set in the buffer descriptor. The
+ * TDAR register is cleared at reset, when ECR[ETHEREN] transitions from set to
+ * cleared, or when ECR[RESET] is set.
+ */
+typedef union _hw_enet_tdar
+{
+ uint32_t U;
+ struct _hw_enet_tdar_bitfields
+ {
+ uint32_t RESERVED0 : 24; //!< [23:0]
+ uint32_t TDAR : 1; //!< [24] Transmit Descriptor Active
+ uint32_t RESERVED1 : 7; //!< [31:25]
+ } B;
+} hw_enet_tdar_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_TDAR register
+ */
+//@{
+#define HW_ENET_TDAR_ADDR(x) (REGS_ENET_BASE(x) + 0x14U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_TDAR(x) (*(__IO hw_enet_tdar_t *) HW_ENET_TDAR_ADDR(x))
+#define HW_ENET_TDAR_RD(x) (HW_ENET_TDAR(x).U)
+#define HW_ENET_TDAR_WR(x, v) (HW_ENET_TDAR(x).U = (v))
+#define HW_ENET_TDAR_SET(x, v) (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) | (v)))
+#define HW_ENET_TDAR_CLR(x, v) (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) & ~(v)))
+#define HW_ENET_TDAR_TOG(x, v) (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_TDAR bitfields
+ */
+
+/*!
+ * @name Register ENET_TDAR, field TDAR[24] (RW)
+ *
+ * Always set to 1 when this register is written, regardless of the value
+ * written. This bit is cleared by the MAC device when no additional ready descriptors
+ * remain in the transmit ring. Also cleared when ECR[ETHEREN] transitions from
+ * set to cleared or when ECR[RESET] is set.
+ */
+//@{
+#define BP_ENET_TDAR_TDAR (24U) //!< Bit position for ENET_TDAR_TDAR.
+#define BM_ENET_TDAR_TDAR (0x01000000U) //!< Bit mask for ENET_TDAR_TDAR.
+#define BS_ENET_TDAR_TDAR (1U) //!< Bit field size in bits for ENET_TDAR_TDAR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TDAR_TDAR field.
+#define BR_ENET_TDAR_TDAR(x) (BITBAND_ACCESS32(HW_ENET_TDAR_ADDR(x), BP_ENET_TDAR_TDAR))
+#endif
+
+//! @brief Format value for bitfield ENET_TDAR_TDAR.
+#define BF_ENET_TDAR_TDAR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TDAR_TDAR), uint32_t) & BM_ENET_TDAR_TDAR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TDAR field to a new value.
+#define BW_ENET_TDAR_TDAR(x, v) (BITBAND_ACCESS32(HW_ENET_TDAR_ADDR(x), BP_ENET_TDAR_TDAR) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_ECR - Ethernet Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_ECR - Ethernet Control Register (RW)
+ *
+ * Reset value: 0xF0000000U
+ *
+ * ECR is a read/write user register, though hardware may also alter fields in
+ * this register. It controls many of the high level features of the Ethernet MAC,
+ * including legacy FEC support through the EN1588 field.
+ */
+typedef union _hw_enet_ecr
+{
+ uint32_t U;
+ struct _hw_enet_ecr_bitfields
+ {
+ uint32_t RESET : 1; //!< [0] Ethernet MAC Reset
+ uint32_t ETHEREN : 1; //!< [1] Ethernet Enable
+ uint32_t MAGICEN : 1; //!< [2] Magic Packet Detection Enable
+ uint32_t SLEEP : 1; //!< [3] Sleep Mode Enable
+ uint32_t EN1588 : 1; //!< [4] EN1588 Enable
+ uint32_t RESERVED0 : 1; //!< [5]
+ uint32_t DBGEN : 1; //!< [6] Debug Enable
+ uint32_t STOPEN : 1; //!< [7] STOPEN Signal Control
+ uint32_t DBSWP : 1; //!< [8] Descriptor Byte Swapping Enable
+ uint32_t RESERVED1 : 23; //!< [31:9]
+ } B;
+} hw_enet_ecr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_ECR register
+ */
+//@{
+#define HW_ENET_ECR_ADDR(x) (REGS_ENET_BASE(x) + 0x24U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_ECR(x) (*(__IO hw_enet_ecr_t *) HW_ENET_ECR_ADDR(x))
+#define HW_ENET_ECR_RD(x) (HW_ENET_ECR(x).U)
+#define HW_ENET_ECR_WR(x, v) (HW_ENET_ECR(x).U = (v))
+#define HW_ENET_ECR_SET(x, v) (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) | (v)))
+#define HW_ENET_ECR_CLR(x, v) (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) & ~(v)))
+#define HW_ENET_ECR_TOG(x, v) (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_ECR bitfields
+ */
+
+/*!
+ * @name Register ENET_ECR, field RESET[0] (RW)
+ *
+ * When this field is set, it clears the ETHEREN field.
+ */
+//@{
+#define BP_ENET_ECR_RESET (0U) //!< Bit position for ENET_ECR_RESET.
+#define BM_ENET_ECR_RESET (0x00000001U) //!< Bit mask for ENET_ECR_RESET.
+#define BS_ENET_ECR_RESET (1U) //!< Bit field size in bits for ENET_ECR_RESET.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ECR_RESET field.
+#define BR_ENET_ECR_RESET(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_RESET))
+#endif
+
+//! @brief Format value for bitfield ENET_ECR_RESET.
+#define BF_ENET_ECR_RESET(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_RESET), uint32_t) & BM_ENET_ECR_RESET)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RESET field to a new value.
+#define BW_ENET_ECR_RESET(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_RESET) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ECR, field ETHEREN[1] (RW)
+ *
+ * Enables/disables the Ethernet MAC. When the MAC is disabled, the buffer
+ * descriptors for an aborted transmit frame are not updated. The uDMA, buffer
+ * descriptor, and FIFO control logic are reset, including the buffer descriptor and
+ * FIFO pointers. Hardware clears this field under the following conditions: RESET
+ * is set by software An error condition causes the EBERR field to set. ETHEREN
+ * must be set at the very last step during ENET
+ * configuration/setup/initialization, only after all other ENET-related registers have been configured. If ETHEREN
+ * is cleared to 0 by software then then next time ETHEREN is set, the EIR
+ * interrupts must cleared to 0 due to previous pending interrupts.
+ *
+ * Values:
+ * - 0 - Reception immediately stops and transmission stops after a bad CRC is
+ * appended to any currently transmitted frame.
+ * - 1 - MAC is enabled, and reception and transmission are possible.
+ */
+//@{
+#define BP_ENET_ECR_ETHEREN (1U) //!< Bit position for ENET_ECR_ETHEREN.
+#define BM_ENET_ECR_ETHEREN (0x00000002U) //!< Bit mask for ENET_ECR_ETHEREN.
+#define BS_ENET_ECR_ETHEREN (1U) //!< Bit field size in bits for ENET_ECR_ETHEREN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ECR_ETHEREN field.
+#define BR_ENET_ECR_ETHEREN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_ETHEREN))
+#endif
+
+//! @brief Format value for bitfield ENET_ECR_ETHEREN.
+#define BF_ENET_ECR_ETHEREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_ETHEREN), uint32_t) & BM_ENET_ECR_ETHEREN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ETHEREN field to a new value.
+#define BW_ENET_ECR_ETHEREN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_ETHEREN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ECR, field MAGICEN[2] (RW)
+ *
+ * Enables/disables magic packet detection. MAGICEN is relevant only if the
+ * SLEEP field is set. If MAGICEN is set, changing the SLEEP field enables/disables
+ * sleep mode and magic packet detection.
+ *
+ * Values:
+ * - 0 - Magic detection logic disabled.
+ * - 1 - The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame
+ * is detected.
+ */
+//@{
+#define BP_ENET_ECR_MAGICEN (2U) //!< Bit position for ENET_ECR_MAGICEN.
+#define BM_ENET_ECR_MAGICEN (0x00000004U) //!< Bit mask for ENET_ECR_MAGICEN.
+#define BS_ENET_ECR_MAGICEN (1U) //!< Bit field size in bits for ENET_ECR_MAGICEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ECR_MAGICEN field.
+#define BR_ENET_ECR_MAGICEN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_MAGICEN))
+#endif
+
+//! @brief Format value for bitfield ENET_ECR_MAGICEN.
+#define BF_ENET_ECR_MAGICEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_MAGICEN), uint32_t) & BM_ENET_ECR_MAGICEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MAGICEN field to a new value.
+#define BW_ENET_ECR_MAGICEN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_MAGICEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ECR, field SLEEP[3] (RW)
+ *
+ * Values:
+ * - 0 - Normal operating mode.
+ * - 1 - Sleep mode.
+ */
+//@{
+#define BP_ENET_ECR_SLEEP (3U) //!< Bit position for ENET_ECR_SLEEP.
+#define BM_ENET_ECR_SLEEP (0x00000008U) //!< Bit mask for ENET_ECR_SLEEP.
+#define BS_ENET_ECR_SLEEP (1U) //!< Bit field size in bits for ENET_ECR_SLEEP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ECR_SLEEP field.
+#define BR_ENET_ECR_SLEEP(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_SLEEP))
+#endif
+
+//! @brief Format value for bitfield ENET_ECR_SLEEP.
+#define BF_ENET_ECR_SLEEP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_SLEEP), uint32_t) & BM_ENET_ECR_SLEEP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SLEEP field to a new value.
+#define BW_ENET_ECR_SLEEP(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_SLEEP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ECR, field EN1588[4] (RW)
+ *
+ * Enables enhanced functionality of the MAC.
+ *
+ * Values:
+ * - 0 - Legacy FEC buffer descriptors and functions enabled.
+ * - 1 - Enhanced frame time-stamping functions enabled.
+ */
+//@{
+#define BP_ENET_ECR_EN1588 (4U) //!< Bit position for ENET_ECR_EN1588.
+#define BM_ENET_ECR_EN1588 (0x00000010U) //!< Bit mask for ENET_ECR_EN1588.
+#define BS_ENET_ECR_EN1588 (1U) //!< Bit field size in bits for ENET_ECR_EN1588.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ECR_EN1588 field.
+#define BR_ENET_ECR_EN1588(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_EN1588))
+#endif
+
+//! @brief Format value for bitfield ENET_ECR_EN1588.
+#define BF_ENET_ECR_EN1588(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_EN1588), uint32_t) & BM_ENET_ECR_EN1588)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EN1588 field to a new value.
+#define BW_ENET_ECR_EN1588(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_EN1588) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ECR, field DBGEN[6] (RW)
+ *
+ * Enables the MAC to enter hardware freeze mode when the device enters debug
+ * mode.
+ *
+ * Values:
+ * - 0 - MAC continues operation in debug mode.
+ * - 1 - MAC enters hardware freeze mode when the processor is in debug mode.
+ */
+//@{
+#define BP_ENET_ECR_DBGEN (6U) //!< Bit position for ENET_ECR_DBGEN.
+#define BM_ENET_ECR_DBGEN (0x00000040U) //!< Bit mask for ENET_ECR_DBGEN.
+#define BS_ENET_ECR_DBGEN (1U) //!< Bit field size in bits for ENET_ECR_DBGEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ECR_DBGEN field.
+#define BR_ENET_ECR_DBGEN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBGEN))
+#endif
+
+//! @brief Format value for bitfield ENET_ECR_DBGEN.
+#define BF_ENET_ECR_DBGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_DBGEN), uint32_t) & BM_ENET_ECR_DBGEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DBGEN field to a new value.
+#define BW_ENET_ECR_DBGEN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBGEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ECR, field STOPEN[7] (RW)
+ *
+ * Controls device behavior in doze mode. In doze mode, if this field is set
+ * then all the clocks of the ENET assembly are disabled, except the RMII /MII
+ * clock. Doze mode is similar to a conditional stop mode entry for the ENET assembly
+ * depending on ECR[STOPEN]. If module clocks are gated in this mode, the module
+ * can still wake the system after receiving a magic packet in stop mode. MAGICEN
+ * must be set prior to entering sleep/stop mode.
+ */
+//@{
+#define BP_ENET_ECR_STOPEN (7U) //!< Bit position for ENET_ECR_STOPEN.
+#define BM_ENET_ECR_STOPEN (0x00000080U) //!< Bit mask for ENET_ECR_STOPEN.
+#define BS_ENET_ECR_STOPEN (1U) //!< Bit field size in bits for ENET_ECR_STOPEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ECR_STOPEN field.
+#define BR_ENET_ECR_STOPEN(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_STOPEN))
+#endif
+
+//! @brief Format value for bitfield ENET_ECR_STOPEN.
+#define BF_ENET_ECR_STOPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_STOPEN), uint32_t) & BM_ENET_ECR_STOPEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the STOPEN field to a new value.
+#define BW_ENET_ECR_STOPEN(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_STOPEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ECR, field DBSWP[8] (RW)
+ *
+ * Swaps the byte locations of the buffer descriptors. This field must be
+ * written to 1 after reset.
+ *
+ * Values:
+ * - 0 - The buffer descriptor bytes are not swapped to support big-endian
+ * devices.
+ * - 1 - The buffer descriptor bytes are swapped to support little-endian
+ * devices.
+ */
+//@{
+#define BP_ENET_ECR_DBSWP (8U) //!< Bit position for ENET_ECR_DBSWP.
+#define BM_ENET_ECR_DBSWP (0x00000100U) //!< Bit mask for ENET_ECR_DBSWP.
+#define BS_ENET_ECR_DBSWP (1U) //!< Bit field size in bits for ENET_ECR_DBSWP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ECR_DBSWP field.
+#define BR_ENET_ECR_DBSWP(x) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBSWP))
+#endif
+
+//! @brief Format value for bitfield ENET_ECR_DBSWP.
+#define BF_ENET_ECR_DBSWP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ECR_DBSWP), uint32_t) & BM_ENET_ECR_DBSWP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DBSWP field to a new value.
+#define BW_ENET_ECR_DBSWP(x, v) (BITBAND_ACCESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBSWP) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_MMFR - MII Management Frame Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_MMFR - MII Management Frame Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Writing to MMFR triggers a management frame transaction to the PHY device
+ * unless MSCR is programmed to zero. If MSCR is changed from zero to non-zero
+ * during a write to MMFR, an MII frame is generated with the data previously written
+ * to the MMFR. This allows MMFR and MSCR to be programmed in either order if
+ * MSCR is currently zero. If the MMFR register is written while frame generation is
+ * in progress, the frame contents are altered. Software must use the EIR[MII]
+ * interrupt indication to avoid writing to the MMFR register while frame
+ * generation is in progress.
+ */
+typedef union _hw_enet_mmfr
+{
+ uint32_t U;
+ struct _hw_enet_mmfr_bitfields
+ {
+ uint32_t DATA : 16; //!< [15:0] Management Frame Data
+ uint32_t TA : 2; //!< [17:16] Turn Around
+ uint32_t RA : 5; //!< [22:18] Register Address
+ uint32_t PA : 5; //!< [27:23] PHY Address
+ uint32_t OP : 2; //!< [29:28] Operation Code
+ uint32_t ST : 2; //!< [31:30] Start Of Frame Delimiter
+ } B;
+} hw_enet_mmfr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_MMFR register
+ */
+//@{
+#define HW_ENET_MMFR_ADDR(x) (REGS_ENET_BASE(x) + 0x40U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_MMFR(x) (*(__IO hw_enet_mmfr_t *) HW_ENET_MMFR_ADDR(x))
+#define HW_ENET_MMFR_RD(x) (HW_ENET_MMFR(x).U)
+#define HW_ENET_MMFR_WR(x, v) (HW_ENET_MMFR(x).U = (v))
+#define HW_ENET_MMFR_SET(x, v) (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) | (v)))
+#define HW_ENET_MMFR_CLR(x, v) (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) & ~(v)))
+#define HW_ENET_MMFR_TOG(x, v) (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_MMFR bitfields
+ */
+
+/*!
+ * @name Register ENET_MMFR, field DATA[15:0] (RW)
+ *
+ * This is the field for data to be written to or read from the PHY register.
+ */
+//@{
+#define BP_ENET_MMFR_DATA (0U) //!< Bit position for ENET_MMFR_DATA.
+#define BM_ENET_MMFR_DATA (0x0000FFFFU) //!< Bit mask for ENET_MMFR_DATA.
+#define BS_ENET_MMFR_DATA (16U) //!< Bit field size in bits for ENET_MMFR_DATA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_MMFR_DATA field.
+#define BR_ENET_MMFR_DATA(x) (HW_ENET_MMFR(x).B.DATA)
+#endif
+
+//! @brief Format value for bitfield ENET_MMFR_DATA.
+#define BF_ENET_MMFR_DATA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_DATA), uint32_t) & BM_ENET_MMFR_DATA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATA field to a new value.
+#define BW_ENET_MMFR_DATA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_DATA) | BF_ENET_MMFR_DATA(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_MMFR, field TA[17:16] (RW)
+ *
+ * This field must be programmed to 10 to generate a valid MII management frame.
+ */
+//@{
+#define BP_ENET_MMFR_TA (16U) //!< Bit position for ENET_MMFR_TA.
+#define BM_ENET_MMFR_TA (0x00030000U) //!< Bit mask for ENET_MMFR_TA.
+#define BS_ENET_MMFR_TA (2U) //!< Bit field size in bits for ENET_MMFR_TA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_MMFR_TA field.
+#define BR_ENET_MMFR_TA(x) (HW_ENET_MMFR(x).B.TA)
+#endif
+
+//! @brief Format value for bitfield ENET_MMFR_TA.
+#define BF_ENET_MMFR_TA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_TA), uint32_t) & BM_ENET_MMFR_TA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TA field to a new value.
+#define BW_ENET_MMFR_TA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_TA) | BF_ENET_MMFR_TA(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_MMFR, field RA[22:18] (RW)
+ *
+ * Specifies one of up to 32 registers within the specified PHY device.
+ */
+//@{
+#define BP_ENET_MMFR_RA (18U) //!< Bit position for ENET_MMFR_RA.
+#define BM_ENET_MMFR_RA (0x007C0000U) //!< Bit mask for ENET_MMFR_RA.
+#define BS_ENET_MMFR_RA (5U) //!< Bit field size in bits for ENET_MMFR_RA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_MMFR_RA field.
+#define BR_ENET_MMFR_RA(x) (HW_ENET_MMFR(x).B.RA)
+#endif
+
+//! @brief Format value for bitfield ENET_MMFR_RA.
+#define BF_ENET_MMFR_RA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_RA), uint32_t) & BM_ENET_MMFR_RA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RA field to a new value.
+#define BW_ENET_MMFR_RA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_RA) | BF_ENET_MMFR_RA(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_MMFR, field PA[27:23] (RW)
+ *
+ * Specifies one of up to 32 attached PHY devices.
+ */
+//@{
+#define BP_ENET_MMFR_PA (23U) //!< Bit position for ENET_MMFR_PA.
+#define BM_ENET_MMFR_PA (0x0F800000U) //!< Bit mask for ENET_MMFR_PA.
+#define BS_ENET_MMFR_PA (5U) //!< Bit field size in bits for ENET_MMFR_PA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_MMFR_PA field.
+#define BR_ENET_MMFR_PA(x) (HW_ENET_MMFR(x).B.PA)
+#endif
+
+//! @brief Format value for bitfield ENET_MMFR_PA.
+#define BF_ENET_MMFR_PA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_PA), uint32_t) & BM_ENET_MMFR_PA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PA field to a new value.
+#define BW_ENET_MMFR_PA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_PA) | BF_ENET_MMFR_PA(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_MMFR, field OP[29:28] (RW)
+ *
+ * Determines the frame operation.
+ *
+ * Values:
+ * - 00 - Write frame operation, but not MII compliant.
+ * - 01 - Write frame operation for a valid MII management frame.
+ * - 10 - Read frame operation for a valid MII management frame.
+ * - 11 - Read frame operation, but not MII compliant.
+ */
+//@{
+#define BP_ENET_MMFR_OP (28U) //!< Bit position for ENET_MMFR_OP.
+#define BM_ENET_MMFR_OP (0x30000000U) //!< Bit mask for ENET_MMFR_OP.
+#define BS_ENET_MMFR_OP (2U) //!< Bit field size in bits for ENET_MMFR_OP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_MMFR_OP field.
+#define BR_ENET_MMFR_OP(x) (HW_ENET_MMFR(x).B.OP)
+#endif
+
+//! @brief Format value for bitfield ENET_MMFR_OP.
+#define BF_ENET_MMFR_OP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_OP), uint32_t) & BM_ENET_MMFR_OP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OP field to a new value.
+#define BW_ENET_MMFR_OP(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_OP) | BF_ENET_MMFR_OP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_MMFR, field ST[31:30] (RW)
+ *
+ * These fields must be programmed to 01 for a valid MII management frame.
+ */
+//@{
+#define BP_ENET_MMFR_ST (30U) //!< Bit position for ENET_MMFR_ST.
+#define BM_ENET_MMFR_ST (0xC0000000U) //!< Bit mask for ENET_MMFR_ST.
+#define BS_ENET_MMFR_ST (2U) //!< Bit field size in bits for ENET_MMFR_ST.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_MMFR_ST field.
+#define BR_ENET_MMFR_ST(x) (HW_ENET_MMFR(x).B.ST)
+#endif
+
+//! @brief Format value for bitfield ENET_MMFR_ST.
+#define BF_ENET_MMFR_ST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MMFR_ST), uint32_t) & BM_ENET_MMFR_ST)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ST field to a new value.
+#define BW_ENET_MMFR_ST(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_ST) | BF_ENET_MMFR_ST(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_MSCR - MII Speed Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_MSCR - MII Speed Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * MSCR provides control of the MII clock (MDC pin) frequency and allows a
+ * preamble drop on the MII management frame. The MII_SPEED field must be programmed
+ * with a value to provide an MDC frequency of less than or equal to 2.5 MHz to be
+ * compliant with the IEEE 802.3 MII specification. The MII_SPEED must be set to
+ * a non-zero value to source a read or write management frame. After the
+ * management frame is complete, the MSCR register may optionally be cleared to turn
+ * off MDC. The MDC signal generated has a 50% duty cycle except when MII_SPEED
+ * changes during operation. This change takes effect following a rising or falling
+ * edge of MDC. If the internal module clock is 25 MHz, programming this register
+ * to 0x0000_0004 results in an MDC as stated in the following equation: 25 MHz
+ * / ((4 + 1) x 2) = 2.5 MHz The following table shows the optimum values for
+ * MII_SPEED as a function of internal module clock frequency. Programming Examples
+ * for MSCR Internal MAC clock frequency MSCR [MII_SPEED] MDC frequency 25 MHz
+ * 0x4 2.50 MHz 33 MHz 0x6 2.36 MHz 40 MHz 0x7 2.50 MHz 50 MHz 0x9 2.50 MHz 66 MHz
+ * 0xD 2.36 MHz
+ */
+typedef union _hw_enet_mscr
+{
+ uint32_t U;
+ struct _hw_enet_mscr_bitfields
+ {
+ uint32_t RESERVED0 : 1; //!< [0]
+ uint32_t MII_SPEED : 6; //!< [6:1] MII Speed
+ uint32_t DIS_PRE : 1; //!< [7] Disable Preamble
+ uint32_t HOLDTIME : 3; //!< [10:8] Hold time On MDIO Output
+ uint32_t RESERVED1 : 21; //!< [31:11]
+ } B;
+} hw_enet_mscr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_MSCR register
+ */
+//@{
+#define HW_ENET_MSCR_ADDR(x) (REGS_ENET_BASE(x) + 0x44U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_MSCR(x) (*(__IO hw_enet_mscr_t *) HW_ENET_MSCR_ADDR(x))
+#define HW_ENET_MSCR_RD(x) (HW_ENET_MSCR(x).U)
+#define HW_ENET_MSCR_WR(x, v) (HW_ENET_MSCR(x).U = (v))
+#define HW_ENET_MSCR_SET(x, v) (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) | (v)))
+#define HW_ENET_MSCR_CLR(x, v) (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) & ~(v)))
+#define HW_ENET_MSCR_TOG(x, v) (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_MSCR bitfields
+ */
+
+/*!
+ * @name Register ENET_MSCR, field MII_SPEED[6:1] (RW)
+ *
+ * Controls the frequency of the MII management interface clock (MDC) relative
+ * to the internal module clock. A value of 0 in this field turns off MDC and
+ * leaves it in low voltage state. Any non-zero value results in the MDC frequency
+ * of: 1/((MII_SPEED + 1) x 2) of the internal module clock frequency
+ */
+//@{
+#define BP_ENET_MSCR_MII_SPEED (1U) //!< Bit position for ENET_MSCR_MII_SPEED.
+#define BM_ENET_MSCR_MII_SPEED (0x0000007EU) //!< Bit mask for ENET_MSCR_MII_SPEED.
+#define BS_ENET_MSCR_MII_SPEED (6U) //!< Bit field size in bits for ENET_MSCR_MII_SPEED.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_MSCR_MII_SPEED field.
+#define BR_ENET_MSCR_MII_SPEED(x) (HW_ENET_MSCR(x).B.MII_SPEED)
+#endif
+
+//! @brief Format value for bitfield ENET_MSCR_MII_SPEED.
+#define BF_ENET_MSCR_MII_SPEED(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MSCR_MII_SPEED), uint32_t) & BM_ENET_MSCR_MII_SPEED)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MII_SPEED field to a new value.
+#define BW_ENET_MSCR_MII_SPEED(x, v) (HW_ENET_MSCR_WR(x, (HW_ENET_MSCR_RD(x) & ~BM_ENET_MSCR_MII_SPEED) | BF_ENET_MSCR_MII_SPEED(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_MSCR, field DIS_PRE[7] (RW)
+ *
+ * Enables/disables prepending a preamble to the MII management frame. The MII
+ * standard allows the preamble to be dropped if the attached PHY devices do not
+ * require it.
+ *
+ * Values:
+ * - 0 - Preamble enabled.
+ * - 1 - Preamble (32 ones) is not prepended to the MII management frame.
+ */
+//@{
+#define BP_ENET_MSCR_DIS_PRE (7U) //!< Bit position for ENET_MSCR_DIS_PRE.
+#define BM_ENET_MSCR_DIS_PRE (0x00000080U) //!< Bit mask for ENET_MSCR_DIS_PRE.
+#define BS_ENET_MSCR_DIS_PRE (1U) //!< Bit field size in bits for ENET_MSCR_DIS_PRE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_MSCR_DIS_PRE field.
+#define BR_ENET_MSCR_DIS_PRE(x) (BITBAND_ACCESS32(HW_ENET_MSCR_ADDR(x), BP_ENET_MSCR_DIS_PRE))
+#endif
+
+//! @brief Format value for bitfield ENET_MSCR_DIS_PRE.
+#define BF_ENET_MSCR_DIS_PRE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MSCR_DIS_PRE), uint32_t) & BM_ENET_MSCR_DIS_PRE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DIS_PRE field to a new value.
+#define BW_ENET_MSCR_DIS_PRE(x, v) (BITBAND_ACCESS32(HW_ENET_MSCR_ADDR(x), BP_ENET_MSCR_DIS_PRE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_MSCR, field HOLDTIME[10:8] (RW)
+ *
+ * IEEE802.3 clause 22 defines a minimum of 10 ns for the hold time on the MDIO
+ * output. Depending on the host bus frequency, the setting may need to be
+ * increased.
+ *
+ * Values:
+ * - 000 - 1 internal module clock cycle
+ * - 001 - 2 internal module clock cycles
+ * - 010 - 3 internal module clock cycles
+ * - 111 - 8 internal module clock cycles
+ */
+//@{
+#define BP_ENET_MSCR_HOLDTIME (8U) //!< Bit position for ENET_MSCR_HOLDTIME.
+#define BM_ENET_MSCR_HOLDTIME (0x00000700U) //!< Bit mask for ENET_MSCR_HOLDTIME.
+#define BS_ENET_MSCR_HOLDTIME (3U) //!< Bit field size in bits for ENET_MSCR_HOLDTIME.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_MSCR_HOLDTIME field.
+#define BR_ENET_MSCR_HOLDTIME(x) (HW_ENET_MSCR(x).B.HOLDTIME)
+#endif
+
+//! @brief Format value for bitfield ENET_MSCR_HOLDTIME.
+#define BF_ENET_MSCR_HOLDTIME(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MSCR_HOLDTIME), uint32_t) & BM_ENET_MSCR_HOLDTIME)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HOLDTIME field to a new value.
+#define BW_ENET_MSCR_HOLDTIME(x, v) (HW_ENET_MSCR_WR(x, (HW_ENET_MSCR_RD(x) & ~BM_ENET_MSCR_HOLDTIME) | BF_ENET_MSCR_HOLDTIME(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_MIBC - MIB Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_MIBC - MIB Control Register (RW)
+ *
+ * Reset value: 0xC0000000U
+ *
+ * MIBC is a read/write register controlling and observing the state of the MIB
+ * block. Access this register to disable the MIB block operation or clear the
+ * MIB counters. The MIB_DIS field resets to 1.
+ */
+typedef union _hw_enet_mibc
+{
+ uint32_t U;
+ struct _hw_enet_mibc_bitfields
+ {
+ uint32_t RESERVED0 : 29; //!< [28:0]
+ uint32_t MIB_CLEAR : 1; //!< [29] MIB Clear
+ uint32_t MIB_IDLE : 1; //!< [30] MIB Idle
+ uint32_t MIB_DIS : 1; //!< [31] Disable MIB Logic
+ } B;
+} hw_enet_mibc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_MIBC register
+ */
+//@{
+#define HW_ENET_MIBC_ADDR(x) (REGS_ENET_BASE(x) + 0x64U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_MIBC(x) (*(__IO hw_enet_mibc_t *) HW_ENET_MIBC_ADDR(x))
+#define HW_ENET_MIBC_RD(x) (HW_ENET_MIBC(x).U)
+#define HW_ENET_MIBC_WR(x, v) (HW_ENET_MIBC(x).U = (v))
+#define HW_ENET_MIBC_SET(x, v) (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) | (v)))
+#define HW_ENET_MIBC_CLR(x, v) (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) & ~(v)))
+#define HW_ENET_MIBC_TOG(x, v) (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_MIBC bitfields
+ */
+
+/*!
+ * @name Register ENET_MIBC, field MIB_CLEAR[29] (RW)
+ *
+ * If set, all statistics counters are reset to 0. This field is not
+ * self-clearing. To clear the MIB counters set and then clear the field.
+ */
+//@{
+#define BP_ENET_MIBC_MIB_CLEAR (29U) //!< Bit position for ENET_MIBC_MIB_CLEAR.
+#define BM_ENET_MIBC_MIB_CLEAR (0x20000000U) //!< Bit mask for ENET_MIBC_MIB_CLEAR.
+#define BS_ENET_MIBC_MIB_CLEAR (1U) //!< Bit field size in bits for ENET_MIBC_MIB_CLEAR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_MIBC_MIB_CLEAR field.
+#define BR_ENET_MIBC_MIB_CLEAR(x) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_CLEAR))
+#endif
+
+//! @brief Format value for bitfield ENET_MIBC_MIB_CLEAR.
+#define BF_ENET_MIBC_MIB_CLEAR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MIBC_MIB_CLEAR), uint32_t) & BM_ENET_MIBC_MIB_CLEAR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MIB_CLEAR field to a new value.
+#define BW_ENET_MIBC_MIB_CLEAR(x, v) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_CLEAR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_MIBC, field MIB_IDLE[30] (RO)
+ *
+ * If this status field is set, the MIB block is not currently updating any MIB
+ * counters.
+ */
+//@{
+#define BP_ENET_MIBC_MIB_IDLE (30U) //!< Bit position for ENET_MIBC_MIB_IDLE.
+#define BM_ENET_MIBC_MIB_IDLE (0x40000000U) //!< Bit mask for ENET_MIBC_MIB_IDLE.
+#define BS_ENET_MIBC_MIB_IDLE (1U) //!< Bit field size in bits for ENET_MIBC_MIB_IDLE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_MIBC_MIB_IDLE field.
+#define BR_ENET_MIBC_MIB_IDLE(x) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_IDLE))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_MIBC, field MIB_DIS[31] (RW)
+ *
+ * If this control field is set, the MIB logic halts and does not update any MIB
+ * counters.
+ */
+//@{
+#define BP_ENET_MIBC_MIB_DIS (31U) //!< Bit position for ENET_MIBC_MIB_DIS.
+#define BM_ENET_MIBC_MIB_DIS (0x80000000U) //!< Bit mask for ENET_MIBC_MIB_DIS.
+#define BS_ENET_MIBC_MIB_DIS (1U) //!< Bit field size in bits for ENET_MIBC_MIB_DIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_MIBC_MIB_DIS field.
+#define BR_ENET_MIBC_MIB_DIS(x) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_DIS))
+#endif
+
+//! @brief Format value for bitfield ENET_MIBC_MIB_DIS.
+#define BF_ENET_MIBC_MIB_DIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MIBC_MIB_DIS), uint32_t) & BM_ENET_MIBC_MIB_DIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MIB_DIS field to a new value.
+#define BW_ENET_MIBC_MIB_DIS(x, v) (BITBAND_ACCESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_DIS) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RCR - Receive Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RCR - Receive Control Register (RW)
+ *
+ * Reset value: 0x05EE0001U
+ */
+typedef union _hw_enet_rcr
+{
+ uint32_t U;
+ struct _hw_enet_rcr_bitfields
+ {
+ uint32_t LOOP : 1; //!< [0] Internal Loopback
+ uint32_t DRT : 1; //!< [1] Disable Receive On Transmit
+ uint32_t MII_MODE : 1; //!< [2] Media Independent Interface Mode
+ uint32_t PROM : 1; //!< [3] Promiscuous Mode
+ uint32_t BC_REJ : 1; //!< [4] Broadcast Frame Reject
+ uint32_t FCE : 1; //!< [5] Flow Control Enable
+ uint32_t RESERVED0 : 2; //!< [7:6]
+ uint32_t RMII_MODE : 1; //!< [8] RMII Mode Enable
+ uint32_t RMII_10T : 1; //!< [9]
+ uint32_t RESERVED1 : 2; //!< [11:10]
+ uint32_t PADEN : 1; //!< [12] Enable Frame Padding Remove On Receive
+ uint32_t PAUFWD : 1; //!< [13] Terminate/Forward Pause Frames
+ uint32_t CRCFWD : 1; //!< [14] Terminate/Forward Received CRC
+ uint32_t CFEN : 1; //!< [15] MAC Control Frame Enable
+ uint32_t MAX_FL : 14; //!< [29:16] Maximum Frame Length
+ uint32_t NLC : 1; //!< [30] Payload Length Check Disable
+ uint32_t GRS : 1; //!< [31] Graceful Receive Stopped
+ } B;
+} hw_enet_rcr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RCR register
+ */
+//@{
+#define HW_ENET_RCR_ADDR(x) (REGS_ENET_BASE(x) + 0x84U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RCR(x) (*(__IO hw_enet_rcr_t *) HW_ENET_RCR_ADDR(x))
+#define HW_ENET_RCR_RD(x) (HW_ENET_RCR(x).U)
+#define HW_ENET_RCR_WR(x, v) (HW_ENET_RCR(x).U = (v))
+#define HW_ENET_RCR_SET(x, v) (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) | (v)))
+#define HW_ENET_RCR_CLR(x, v) (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) & ~(v)))
+#define HW_ENET_RCR_TOG(x, v) (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RCR bitfields
+ */
+
+/*!
+ * @name Register ENET_RCR, field LOOP[0] (RW)
+ *
+ * This is an MII internal loopback, therefore MII_MODE must be written to 1 and
+ * RMII_MODE must be written to 0.
+ *
+ * Values:
+ * - 0 - Loopback disabled.
+ * - 1 - Transmitted frames are looped back internal to the device and transmit
+ * MII output signals are not asserted. DRT must be cleared.
+ */
+//@{
+#define BP_ENET_RCR_LOOP (0U) //!< Bit position for ENET_RCR_LOOP.
+#define BM_ENET_RCR_LOOP (0x00000001U) //!< Bit mask for ENET_RCR_LOOP.
+#define BS_ENET_RCR_LOOP (1U) //!< Bit field size in bits for ENET_RCR_LOOP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_LOOP field.
+#define BR_ENET_RCR_LOOP(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_LOOP))
+#endif
+
+//! @brief Format value for bitfield ENET_RCR_LOOP.
+#define BF_ENET_RCR_LOOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_LOOP), uint32_t) & BM_ENET_RCR_LOOP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LOOP field to a new value.
+#define BW_ENET_RCR_LOOP(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_LOOP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RCR, field DRT[1] (RW)
+ *
+ * Values:
+ * - 0 - Receive path operates independently of transmit. Used for full-duplex
+ * or to monitor transmit activity in half-duplex mode.
+ * - 1 - Disable reception of frames while transmitting. Normally used for
+ * half-duplex mode.
+ */
+//@{
+#define BP_ENET_RCR_DRT (1U) //!< Bit position for ENET_RCR_DRT.
+#define BM_ENET_RCR_DRT (0x00000002U) //!< Bit mask for ENET_RCR_DRT.
+#define BS_ENET_RCR_DRT (1U) //!< Bit field size in bits for ENET_RCR_DRT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_DRT field.
+#define BR_ENET_RCR_DRT(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_DRT))
+#endif
+
+//! @brief Format value for bitfield ENET_RCR_DRT.
+#define BF_ENET_RCR_DRT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_DRT), uint32_t) & BM_ENET_RCR_DRT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DRT field to a new value.
+#define BW_ENET_RCR_DRT(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_DRT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RCR, field MII_MODE[2] (RW)
+ *
+ * This field must always be set.
+ *
+ * Values:
+ * - 0 - Reserved.
+ * - 1 - MII or RMII mode, as indicated by the RMII_MODE field.
+ */
+//@{
+#define BP_ENET_RCR_MII_MODE (2U) //!< Bit position for ENET_RCR_MII_MODE.
+#define BM_ENET_RCR_MII_MODE (0x00000004U) //!< Bit mask for ENET_RCR_MII_MODE.
+#define BS_ENET_RCR_MII_MODE (1U) //!< Bit field size in bits for ENET_RCR_MII_MODE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_MII_MODE field.
+#define BR_ENET_RCR_MII_MODE(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_MII_MODE))
+#endif
+
+//! @brief Format value for bitfield ENET_RCR_MII_MODE.
+#define BF_ENET_RCR_MII_MODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_MII_MODE), uint32_t) & BM_ENET_RCR_MII_MODE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MII_MODE field to a new value.
+#define BW_ENET_RCR_MII_MODE(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_MII_MODE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RCR, field PROM[3] (RW)
+ *
+ * All frames are accepted regardless of address matching.
+ *
+ * Values:
+ * - 0 - Disabled.
+ * - 1 - Enabled.
+ */
+//@{
+#define BP_ENET_RCR_PROM (3U) //!< Bit position for ENET_RCR_PROM.
+#define BM_ENET_RCR_PROM (0x00000008U) //!< Bit mask for ENET_RCR_PROM.
+#define BS_ENET_RCR_PROM (1U) //!< Bit field size in bits for ENET_RCR_PROM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_PROM field.
+#define BR_ENET_RCR_PROM(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PROM))
+#endif
+
+//! @brief Format value for bitfield ENET_RCR_PROM.
+#define BF_ENET_RCR_PROM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_PROM), uint32_t) & BM_ENET_RCR_PROM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PROM field to a new value.
+#define BW_ENET_RCR_PROM(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PROM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RCR, field BC_REJ[4] (RW)
+ *
+ * If set, frames with destination address (DA) equal to 0xFFFF_FFFF_FFFF are
+ * rejected unless the PROM field is set. If BC_REJ and PROM are set, frames with
+ * broadcast DA are accepted and the MISS (M) is set in the receive buffer
+ * descriptor.
+ */
+//@{
+#define BP_ENET_RCR_BC_REJ (4U) //!< Bit position for ENET_RCR_BC_REJ.
+#define BM_ENET_RCR_BC_REJ (0x00000010U) //!< Bit mask for ENET_RCR_BC_REJ.
+#define BS_ENET_RCR_BC_REJ (1U) //!< Bit field size in bits for ENET_RCR_BC_REJ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_BC_REJ field.
+#define BR_ENET_RCR_BC_REJ(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_BC_REJ))
+#endif
+
+//! @brief Format value for bitfield ENET_RCR_BC_REJ.
+#define BF_ENET_RCR_BC_REJ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_BC_REJ), uint32_t) & BM_ENET_RCR_BC_REJ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BC_REJ field to a new value.
+#define BW_ENET_RCR_BC_REJ(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_BC_REJ) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RCR, field FCE[5] (RW)
+ *
+ * If set, the receiver detects PAUSE frames. Upon PAUSE frame detection, the
+ * transmitter stops transmitting data frames for a given duration.
+ */
+//@{
+#define BP_ENET_RCR_FCE (5U) //!< Bit position for ENET_RCR_FCE.
+#define BM_ENET_RCR_FCE (0x00000020U) //!< Bit mask for ENET_RCR_FCE.
+#define BS_ENET_RCR_FCE (1U) //!< Bit field size in bits for ENET_RCR_FCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_FCE field.
+#define BR_ENET_RCR_FCE(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_FCE))
+#endif
+
+//! @brief Format value for bitfield ENET_RCR_FCE.
+#define BF_ENET_RCR_FCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_FCE), uint32_t) & BM_ENET_RCR_FCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FCE field to a new value.
+#define BW_ENET_RCR_FCE(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_FCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RCR, field RMII_MODE[8] (RW)
+ *
+ * Specifies whether the MAC is configured for MII mode or RMII operation .
+ *
+ * Values:
+ * - 0 - MAC configured for MII mode.
+ * - 1 - MAC configured for RMII operation.
+ */
+//@{
+#define BP_ENET_RCR_RMII_MODE (8U) //!< Bit position for ENET_RCR_RMII_MODE.
+#define BM_ENET_RCR_RMII_MODE (0x00000100U) //!< Bit mask for ENET_RCR_RMII_MODE.
+#define BS_ENET_RCR_RMII_MODE (1U) //!< Bit field size in bits for ENET_RCR_RMII_MODE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_RMII_MODE field.
+#define BR_ENET_RCR_RMII_MODE(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_MODE))
+#endif
+
+//! @brief Format value for bitfield ENET_RCR_RMII_MODE.
+#define BF_ENET_RCR_RMII_MODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_RMII_MODE), uint32_t) & BM_ENET_RCR_RMII_MODE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RMII_MODE field to a new value.
+#define BW_ENET_RCR_RMII_MODE(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_MODE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RCR, field RMII_10T[9] (RW)
+ *
+ * Enables 10-Mbps mode of the RMII .
+ *
+ * Values:
+ * - 0 - 100 Mbps operation.
+ * - 1 - 10 Mbps operation.
+ */
+//@{
+#define BP_ENET_RCR_RMII_10T (9U) //!< Bit position for ENET_RCR_RMII_10T.
+#define BM_ENET_RCR_RMII_10T (0x00000200U) //!< Bit mask for ENET_RCR_RMII_10T.
+#define BS_ENET_RCR_RMII_10T (1U) //!< Bit field size in bits for ENET_RCR_RMII_10T.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_RMII_10T field.
+#define BR_ENET_RCR_RMII_10T(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_10T))
+#endif
+
+//! @brief Format value for bitfield ENET_RCR_RMII_10T.
+#define BF_ENET_RCR_RMII_10T(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_RMII_10T), uint32_t) & BM_ENET_RCR_RMII_10T)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RMII_10T field to a new value.
+#define BW_ENET_RCR_RMII_10T(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_10T) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RCR, field PADEN[12] (RW)
+ *
+ * Specifies whether the MAC removes padding from received frames.
+ *
+ * Values:
+ * - 0 - No padding is removed on receive by the MAC.
+ * - 1 - Padding is removed from received frames.
+ */
+//@{
+#define BP_ENET_RCR_PADEN (12U) //!< Bit position for ENET_RCR_PADEN.
+#define BM_ENET_RCR_PADEN (0x00001000U) //!< Bit mask for ENET_RCR_PADEN.
+#define BS_ENET_RCR_PADEN (1U) //!< Bit field size in bits for ENET_RCR_PADEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_PADEN field.
+#define BR_ENET_RCR_PADEN(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PADEN))
+#endif
+
+//! @brief Format value for bitfield ENET_RCR_PADEN.
+#define BF_ENET_RCR_PADEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_PADEN), uint32_t) & BM_ENET_RCR_PADEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PADEN field to a new value.
+#define BW_ENET_RCR_PADEN(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PADEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RCR, field PAUFWD[13] (RW)
+ *
+ * Specifies whether pause frames are terminated or forwarded.
+ *
+ * Values:
+ * - 0 - Pause frames are terminated and discarded in the MAC.
+ * - 1 - Pause frames are forwarded to the user application.
+ */
+//@{
+#define BP_ENET_RCR_PAUFWD (13U) //!< Bit position for ENET_RCR_PAUFWD.
+#define BM_ENET_RCR_PAUFWD (0x00002000U) //!< Bit mask for ENET_RCR_PAUFWD.
+#define BS_ENET_RCR_PAUFWD (1U) //!< Bit field size in bits for ENET_RCR_PAUFWD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_PAUFWD field.
+#define BR_ENET_RCR_PAUFWD(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PAUFWD))
+#endif
+
+//! @brief Format value for bitfield ENET_RCR_PAUFWD.
+#define BF_ENET_RCR_PAUFWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_PAUFWD), uint32_t) & BM_ENET_RCR_PAUFWD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PAUFWD field to a new value.
+#define BW_ENET_RCR_PAUFWD(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PAUFWD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RCR, field CRCFWD[14] (RW)
+ *
+ * Specifies whether the CRC field of received frames is transmitted or
+ * stripped. If padding function is enabled (PADEN = 1), CRCFWD is ignored and the CRC
+ * field is checked and always terminated and removed.
+ *
+ * Values:
+ * - 0 - The CRC field of received frames is transmitted to the user application.
+ * - 1 - The CRC field is stripped from the frame.
+ */
+//@{
+#define BP_ENET_RCR_CRCFWD (14U) //!< Bit position for ENET_RCR_CRCFWD.
+#define BM_ENET_RCR_CRCFWD (0x00004000U) //!< Bit mask for ENET_RCR_CRCFWD.
+#define BS_ENET_RCR_CRCFWD (1U) //!< Bit field size in bits for ENET_RCR_CRCFWD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_CRCFWD field.
+#define BR_ENET_RCR_CRCFWD(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CRCFWD))
+#endif
+
+//! @brief Format value for bitfield ENET_RCR_CRCFWD.
+#define BF_ENET_RCR_CRCFWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_CRCFWD), uint32_t) & BM_ENET_RCR_CRCFWD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CRCFWD field to a new value.
+#define BW_ENET_RCR_CRCFWD(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CRCFWD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RCR, field CFEN[15] (RW)
+ *
+ * Enables/disables the MAC control frame.
+ *
+ * Values:
+ * - 0 - MAC control frames with any opcode other than 0x0001 (pause frame) are
+ * accepted and forwarded to the client interface.
+ * - 1 - MAC control frames with any opcode other than 0x0001 (pause frame) are
+ * silently discarded.
+ */
+//@{
+#define BP_ENET_RCR_CFEN (15U) //!< Bit position for ENET_RCR_CFEN.
+#define BM_ENET_RCR_CFEN (0x00008000U) //!< Bit mask for ENET_RCR_CFEN.
+#define BS_ENET_RCR_CFEN (1U) //!< Bit field size in bits for ENET_RCR_CFEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_CFEN field.
+#define BR_ENET_RCR_CFEN(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CFEN))
+#endif
+
+//! @brief Format value for bitfield ENET_RCR_CFEN.
+#define BF_ENET_RCR_CFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_CFEN), uint32_t) & BM_ENET_RCR_CFEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CFEN field to a new value.
+#define BW_ENET_RCR_CFEN(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CFEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RCR, field MAX_FL[29:16] (RW)
+ *
+ * Resets to decimal 1518. Length is measured starting at DA and includes the
+ * CRC at the end of the frame. Transmit frames longer than MAX_FL cause the BABT
+ * interrupt to occur. Receive frames longer than MAX_FL cause the BABR interrupt
+ * to occur and set the LG field in the end of frame receive buffer descriptor.
+ * The recommended default value to be programmed is 1518 or 1522 if VLAN tags are
+ * supported.
+ */
+//@{
+#define BP_ENET_RCR_MAX_FL (16U) //!< Bit position for ENET_RCR_MAX_FL.
+#define BM_ENET_RCR_MAX_FL (0x3FFF0000U) //!< Bit mask for ENET_RCR_MAX_FL.
+#define BS_ENET_RCR_MAX_FL (14U) //!< Bit field size in bits for ENET_RCR_MAX_FL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_MAX_FL field.
+#define BR_ENET_RCR_MAX_FL(x) (HW_ENET_RCR(x).B.MAX_FL)
+#endif
+
+//! @brief Format value for bitfield ENET_RCR_MAX_FL.
+#define BF_ENET_RCR_MAX_FL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_MAX_FL), uint32_t) & BM_ENET_RCR_MAX_FL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MAX_FL field to a new value.
+#define BW_ENET_RCR_MAX_FL(x, v) (HW_ENET_RCR_WR(x, (HW_ENET_RCR_RD(x) & ~BM_ENET_RCR_MAX_FL) | BF_ENET_RCR_MAX_FL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RCR, field NLC[30] (RW)
+ *
+ * Enables/disables a payload length check.
+ *
+ * Values:
+ * - 0 - The payload length check is disabled.
+ * - 1 - The core checks the frame's payload length with the frame length/type
+ * field. Errors are indicated in the EIR[PLC] field.
+ */
+//@{
+#define BP_ENET_RCR_NLC (30U) //!< Bit position for ENET_RCR_NLC.
+#define BM_ENET_RCR_NLC (0x40000000U) //!< Bit mask for ENET_RCR_NLC.
+#define BS_ENET_RCR_NLC (1U) //!< Bit field size in bits for ENET_RCR_NLC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_NLC field.
+#define BR_ENET_RCR_NLC(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_NLC))
+#endif
+
+//! @brief Format value for bitfield ENET_RCR_NLC.
+#define BF_ENET_RCR_NLC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RCR_NLC), uint32_t) & BM_ENET_RCR_NLC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NLC field to a new value.
+#define BW_ENET_RCR_NLC(x, v) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_NLC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RCR, field GRS[31] (RO)
+ *
+ * Read-only status indicating that the MAC receive datapath is stopped.
+ */
+//@{
+#define BP_ENET_RCR_GRS (31U) //!< Bit position for ENET_RCR_GRS.
+#define BM_ENET_RCR_GRS (0x80000000U) //!< Bit mask for ENET_RCR_GRS.
+#define BS_ENET_RCR_GRS (1U) //!< Bit field size in bits for ENET_RCR_GRS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RCR_GRS field.
+#define BR_ENET_RCR_GRS(x) (BITBAND_ACCESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_GRS))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_TCR - Transmit Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_TCR - Transmit Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TCR is read/write and configures the transmit block. This register is cleared
+ * at system reset. FDEN can only be modified when ECR[ETHEREN] is cleared.
+ */
+typedef union _hw_enet_tcr
+{
+ uint32_t U;
+ struct _hw_enet_tcr_bitfields
+ {
+ uint32_t GTS : 1; //!< [0] Graceful Transmit Stop
+ uint32_t RESERVED0 : 1; //!< [1]
+ uint32_t FDEN : 1; //!< [2] Full-Duplex Enable
+ uint32_t TFC_PAUSE : 1; //!< [3] Transmit Frame Control Pause
+ uint32_t RFC_PAUSE : 1; //!< [4] Receive Frame Control Pause
+ uint32_t ADDSEL : 3; //!< [7:5] Source MAC Address Select On Transmit
+ uint32_t ADDINS : 1; //!< [8] Set MAC Address On Transmit
+ uint32_t CRCFWD : 1; //!< [9] Forward Frame From Application With CRC
+ uint32_t RESERVED1 : 22; //!< [31:10]
+ } B;
+} hw_enet_tcr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_TCR register
+ */
+//@{
+#define HW_ENET_TCR_ADDR(x) (REGS_ENET_BASE(x) + 0xC4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_TCR(x) (*(__IO hw_enet_tcr_t *) HW_ENET_TCR_ADDR(x))
+#define HW_ENET_TCR_RD(x) (HW_ENET_TCR(x).U)
+#define HW_ENET_TCR_WR(x, v) (HW_ENET_TCR(x).U = (v))
+#define HW_ENET_TCR_SET(x, v) (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) | (v)))
+#define HW_ENET_TCR_CLR(x, v) (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) & ~(v)))
+#define HW_ENET_TCR_TOG(x, v) (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_TCR bitfields
+ */
+
+/*!
+ * @name Register ENET_TCR, field GTS[0] (RW)
+ *
+ * When this field is set, MAC stops transmission after any frame currently
+ * transmitted is complete and EIR[GRA] is set. If frame transmission is not
+ * currently underway, the GRA interrupt is asserted immediately. After transmission
+ * finishes, clear GTS to restart. The next frame in the transmit FIFO is then
+ * transmitted. If an early collision occurs during transmission when GTS is set,
+ * transmission stops after the collision. The frame is transmitted again after GTS is
+ * cleared. There may be old frames in the transmit FIFO that transmit when GTS
+ * is reasserted. To avoid this, clear ECR[ETHEREN] following the GRA interrupt.
+ */
+//@{
+#define BP_ENET_TCR_GTS (0U) //!< Bit position for ENET_TCR_GTS.
+#define BM_ENET_TCR_GTS (0x00000001U) //!< Bit mask for ENET_TCR_GTS.
+#define BS_ENET_TCR_GTS (1U) //!< Bit field size in bits for ENET_TCR_GTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TCR_GTS field.
+#define BR_ENET_TCR_GTS(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_GTS))
+#endif
+
+//! @brief Format value for bitfield ENET_TCR_GTS.
+#define BF_ENET_TCR_GTS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_GTS), uint32_t) & BM_ENET_TCR_GTS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GTS field to a new value.
+#define BW_ENET_TCR_GTS(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_GTS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TCR, field FDEN[2] (RW)
+ *
+ * If this field is set, frames transmit independent of carrier sense and
+ * collision inputs. Only modify this bit when ECR[ETHEREN] is cleared.
+ */
+//@{
+#define BP_ENET_TCR_FDEN (2U) //!< Bit position for ENET_TCR_FDEN.
+#define BM_ENET_TCR_FDEN (0x00000004U) //!< Bit mask for ENET_TCR_FDEN.
+#define BS_ENET_TCR_FDEN (1U) //!< Bit field size in bits for ENET_TCR_FDEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TCR_FDEN field.
+#define BR_ENET_TCR_FDEN(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_FDEN))
+#endif
+
+//! @brief Format value for bitfield ENET_TCR_FDEN.
+#define BF_ENET_TCR_FDEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_FDEN), uint32_t) & BM_ENET_TCR_FDEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FDEN field to a new value.
+#define BW_ENET_TCR_FDEN(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_FDEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TCR, field TFC_PAUSE[3] (RW)
+ *
+ * Pauses frame transmission. When this field is set, EIR[GRA] is set. With
+ * transmission of data frames stopped, the MAC transmits a MAC control PAUSE frame.
+ * Next, the MAC clears TFC_PAUSE and resumes transmitting data frames. If the
+ * transmitter pauses due to user assertion of GTS or reception of a PAUSE frame,
+ * the MAC may continue transmitting a MAC control PAUSE frame.
+ *
+ * Values:
+ * - 0 - No PAUSE frame transmitted.
+ * - 1 - The MAC stops transmission of data frames after the current
+ * transmission is complete.
+ */
+//@{
+#define BP_ENET_TCR_TFC_PAUSE (3U) //!< Bit position for ENET_TCR_TFC_PAUSE.
+#define BM_ENET_TCR_TFC_PAUSE (0x00000008U) //!< Bit mask for ENET_TCR_TFC_PAUSE.
+#define BS_ENET_TCR_TFC_PAUSE (1U) //!< Bit field size in bits for ENET_TCR_TFC_PAUSE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TCR_TFC_PAUSE field.
+#define BR_ENET_TCR_TFC_PAUSE(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_TFC_PAUSE))
+#endif
+
+//! @brief Format value for bitfield ENET_TCR_TFC_PAUSE.
+#define BF_ENET_TCR_TFC_PAUSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_TFC_PAUSE), uint32_t) & BM_ENET_TCR_TFC_PAUSE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TFC_PAUSE field to a new value.
+#define BW_ENET_TCR_TFC_PAUSE(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_TFC_PAUSE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TCR, field RFC_PAUSE[4] (RO)
+ *
+ * This status field is set when a full-duplex flow control pause frame is
+ * received and the transmitter pauses for the duration defined in this pause frame.
+ * This field automatically clears when the pause duration is complete.
+ */
+//@{
+#define BP_ENET_TCR_RFC_PAUSE (4U) //!< Bit position for ENET_TCR_RFC_PAUSE.
+#define BM_ENET_TCR_RFC_PAUSE (0x00000010U) //!< Bit mask for ENET_TCR_RFC_PAUSE.
+#define BS_ENET_TCR_RFC_PAUSE (1U) //!< Bit field size in bits for ENET_TCR_RFC_PAUSE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TCR_RFC_PAUSE field.
+#define BR_ENET_TCR_RFC_PAUSE(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_RFC_PAUSE))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TCR, field ADDSEL[7:5] (RW)
+ *
+ * If ADDINS is set, indicates the MAC address that overwrites the source MAC
+ * address.
+ *
+ * Values:
+ * - 000 - Node MAC address programmed on PADDR1/2 registers.
+ * - 100 - Reserved.
+ * - 101 - Reserved.
+ * - 110 - Reserved.
+ */
+//@{
+#define BP_ENET_TCR_ADDSEL (5U) //!< Bit position for ENET_TCR_ADDSEL.
+#define BM_ENET_TCR_ADDSEL (0x000000E0U) //!< Bit mask for ENET_TCR_ADDSEL.
+#define BS_ENET_TCR_ADDSEL (3U) //!< Bit field size in bits for ENET_TCR_ADDSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TCR_ADDSEL field.
+#define BR_ENET_TCR_ADDSEL(x) (HW_ENET_TCR(x).B.ADDSEL)
+#endif
+
+//! @brief Format value for bitfield ENET_TCR_ADDSEL.
+#define BF_ENET_TCR_ADDSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_ADDSEL), uint32_t) & BM_ENET_TCR_ADDSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADDSEL field to a new value.
+#define BW_ENET_TCR_ADDSEL(x, v) (HW_ENET_TCR_WR(x, (HW_ENET_TCR_RD(x) & ~BM_ENET_TCR_ADDSEL) | BF_ENET_TCR_ADDSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TCR, field ADDINS[8] (RW)
+ *
+ * Values:
+ * - 0 - The source MAC address is not modified by the MAC.
+ * - 1 - The MAC overwrites the source MAC address with the programmed MAC
+ * address according to ADDSEL.
+ */
+//@{
+#define BP_ENET_TCR_ADDINS (8U) //!< Bit position for ENET_TCR_ADDINS.
+#define BM_ENET_TCR_ADDINS (0x00000100U) //!< Bit mask for ENET_TCR_ADDINS.
+#define BS_ENET_TCR_ADDINS (1U) //!< Bit field size in bits for ENET_TCR_ADDINS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TCR_ADDINS field.
+#define BR_ENET_TCR_ADDINS(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_ADDINS))
+#endif
+
+//! @brief Format value for bitfield ENET_TCR_ADDINS.
+#define BF_ENET_TCR_ADDINS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_ADDINS), uint32_t) & BM_ENET_TCR_ADDINS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADDINS field to a new value.
+#define BW_ENET_TCR_ADDINS(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_ADDINS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TCR, field CRCFWD[9] (RW)
+ *
+ * Values:
+ * - 0 - TxBD[TC] controls whether the frame has a CRC from the application.
+ * - 1 - The transmitter does not append any CRC to transmitted frames, as it is
+ * expecting a frame with CRC from the application.
+ */
+//@{
+#define BP_ENET_TCR_CRCFWD (9U) //!< Bit position for ENET_TCR_CRCFWD.
+#define BM_ENET_TCR_CRCFWD (0x00000200U) //!< Bit mask for ENET_TCR_CRCFWD.
+#define BS_ENET_TCR_CRCFWD (1U) //!< Bit field size in bits for ENET_TCR_CRCFWD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TCR_CRCFWD field.
+#define BR_ENET_TCR_CRCFWD(x) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_CRCFWD))
+#endif
+
+//! @brief Format value for bitfield ENET_TCR_CRCFWD.
+#define BF_ENET_TCR_CRCFWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCR_CRCFWD), uint32_t) & BM_ENET_TCR_CRCFWD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CRCFWD field to a new value.
+#define BW_ENET_TCR_CRCFWD(x, v) (BITBAND_ACCESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_CRCFWD) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_PALR - Physical Address Lower Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_PALR - Physical Address Lower Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * PALR contains the lower 32 bits (bytes 0, 1, 2, 3) of the 48-bit address used
+ * in the address recognition process to compare with the destination address
+ * (DA) field of receive frames with an individual DA. In addition, this register
+ * is used in bytes 0 through 3 of the six-byte source address field when
+ * transmitting PAUSE frames. This register is not reset and you must initialize it.
+ */
+typedef union _hw_enet_palr
+{
+ uint32_t U;
+ struct _hw_enet_palr_bitfields
+ {
+ uint32_t PADDR1 : 32; //!< [31:0] Pause Address
+ } B;
+} hw_enet_palr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_PALR register
+ */
+//@{
+#define HW_ENET_PALR_ADDR(x) (REGS_ENET_BASE(x) + 0xE4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_PALR(x) (*(__IO hw_enet_palr_t *) HW_ENET_PALR_ADDR(x))
+#define HW_ENET_PALR_RD(x) (HW_ENET_PALR(x).U)
+#define HW_ENET_PALR_WR(x, v) (HW_ENET_PALR(x).U = (v))
+#define HW_ENET_PALR_SET(x, v) (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) | (v)))
+#define HW_ENET_PALR_CLR(x, v) (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) & ~(v)))
+#define HW_ENET_PALR_TOG(x, v) (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_PALR bitfields
+ */
+
+/*!
+ * @name Register ENET_PALR, field PADDR1[31:0] (RW)
+ *
+ * Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the
+ * 6-byte individual address are used for exact match and the source address
+ * field in PAUSE frames.
+ */
+//@{
+#define BP_ENET_PALR_PADDR1 (0U) //!< Bit position for ENET_PALR_PADDR1.
+#define BM_ENET_PALR_PADDR1 (0xFFFFFFFFU) //!< Bit mask for ENET_PALR_PADDR1.
+#define BS_ENET_PALR_PADDR1 (32U) //!< Bit field size in bits for ENET_PALR_PADDR1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_PALR_PADDR1 field.
+#define BR_ENET_PALR_PADDR1(x) (HW_ENET_PALR(x).U)
+#endif
+
+//! @brief Format value for bitfield ENET_PALR_PADDR1.
+#define BF_ENET_PALR_PADDR1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_PALR_PADDR1), uint32_t) & BM_ENET_PALR_PADDR1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PADDR1 field to a new value.
+#define BW_ENET_PALR_PADDR1(x, v) (HW_ENET_PALR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_PAUR - Physical Address Upper Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_PAUR - Physical Address Upper Register (RW)
+ *
+ * Reset value: 0x00008808U
+ *
+ * PAUR contains the upper 16 bits (bytes 4 and 5) of the 48-bit address used in
+ * the address recognition process to compare with the destination address (DA)
+ * field of receive frames with an individual DA. In addition, this register is
+ * used in bytes 4 and 5 of the six-byte source address field when transmitting
+ * PAUSE frames. Bits 15:0 of PAUR contain a constant type field (0x8808) for
+ * transmission of PAUSE frames. The upper 16 bits of this register are not reset and
+ * you must initialize it.
+ */
+typedef union _hw_enet_paur
+{
+ uint32_t U;
+ struct _hw_enet_paur_bitfields
+ {
+ uint32_t TYPE : 16; //!< [15:0] Type Field In PAUSE Frames
+ uint32_t PADDR2 : 16; //!< [31:16]
+ } B;
+} hw_enet_paur_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_PAUR register
+ */
+//@{
+#define HW_ENET_PAUR_ADDR(x) (REGS_ENET_BASE(x) + 0xE8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_PAUR(x) (*(__IO hw_enet_paur_t *) HW_ENET_PAUR_ADDR(x))
+#define HW_ENET_PAUR_RD(x) (HW_ENET_PAUR(x).U)
+#define HW_ENET_PAUR_WR(x, v) (HW_ENET_PAUR(x).U = (v))
+#define HW_ENET_PAUR_SET(x, v) (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) | (v)))
+#define HW_ENET_PAUR_CLR(x, v) (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) & ~(v)))
+#define HW_ENET_PAUR_TOG(x, v) (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_PAUR bitfields
+ */
+
+/*!
+ * @name Register ENET_PAUR, field TYPE[15:0] (RO)
+ *
+ * These fields have a constant value of 0x8808.
+ */
+//@{
+#define BP_ENET_PAUR_TYPE (0U) //!< Bit position for ENET_PAUR_TYPE.
+#define BM_ENET_PAUR_TYPE (0x0000FFFFU) //!< Bit mask for ENET_PAUR_TYPE.
+#define BS_ENET_PAUR_TYPE (16U) //!< Bit field size in bits for ENET_PAUR_TYPE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_PAUR_TYPE field.
+#define BR_ENET_PAUR_TYPE(x) (HW_ENET_PAUR(x).B.TYPE)
+#endif
+//@}
+
+/*!
+ * @name Register ENET_PAUR, field PADDR2[31:16] (RW)
+ *
+ * Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used
+ * for exact match, and the source address field in PAUSE frames.
+ */
+//@{
+#define BP_ENET_PAUR_PADDR2 (16U) //!< Bit position for ENET_PAUR_PADDR2.
+#define BM_ENET_PAUR_PADDR2 (0xFFFF0000U) //!< Bit mask for ENET_PAUR_PADDR2.
+#define BS_ENET_PAUR_PADDR2 (16U) //!< Bit field size in bits for ENET_PAUR_PADDR2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_PAUR_PADDR2 field.
+#define BR_ENET_PAUR_PADDR2(x) (HW_ENET_PAUR(x).B.PADDR2)
+#endif
+
+//! @brief Format value for bitfield ENET_PAUR_PADDR2.
+#define BF_ENET_PAUR_PADDR2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_PAUR_PADDR2), uint32_t) & BM_ENET_PAUR_PADDR2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PADDR2 field to a new value.
+#define BW_ENET_PAUR_PADDR2(x, v) (HW_ENET_PAUR_WR(x, (HW_ENET_PAUR_RD(x) & ~BM_ENET_PAUR_PADDR2) | BF_ENET_PAUR_PADDR2(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_OPD - Opcode/Pause Duration Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_OPD - Opcode/Pause Duration Register (RW)
+ *
+ * Reset value: 0x00010000U
+ *
+ * OPD is read/write accessible. This register contains the 16-bit opcode and
+ * 16-bit pause duration fields used in transmission of a PAUSE frame. The opcode
+ * field is a constant value, 0x0001. When another node detects a PAUSE frame,
+ * that node pauses transmission for the duration specified in the pause duration
+ * field. The lower 16 bits of this register are not reset and you must initialize
+ * it.
+ */
+typedef union _hw_enet_opd
+{
+ uint32_t U;
+ struct _hw_enet_opd_bitfields
+ {
+ uint32_t PAUSE_DUR : 16; //!< [15:0] Pause Duration
+ uint32_t OPCODE : 16; //!< [31:16] Opcode Field In PAUSE Frames
+ } B;
+} hw_enet_opd_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_OPD register
+ */
+//@{
+#define HW_ENET_OPD_ADDR(x) (REGS_ENET_BASE(x) + 0xECU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_OPD(x) (*(__IO hw_enet_opd_t *) HW_ENET_OPD_ADDR(x))
+#define HW_ENET_OPD_RD(x) (HW_ENET_OPD(x).U)
+#define HW_ENET_OPD_WR(x, v) (HW_ENET_OPD(x).U = (v))
+#define HW_ENET_OPD_SET(x, v) (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) | (v)))
+#define HW_ENET_OPD_CLR(x, v) (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) & ~(v)))
+#define HW_ENET_OPD_TOG(x, v) (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_OPD bitfields
+ */
+
+/*!
+ * @name Register ENET_OPD, field PAUSE_DUR[15:0] (RW)
+ *
+ * Pause duration field used in PAUSE frames.
+ */
+//@{
+#define BP_ENET_OPD_PAUSE_DUR (0U) //!< Bit position for ENET_OPD_PAUSE_DUR.
+#define BM_ENET_OPD_PAUSE_DUR (0x0000FFFFU) //!< Bit mask for ENET_OPD_PAUSE_DUR.
+#define BS_ENET_OPD_PAUSE_DUR (16U) //!< Bit field size in bits for ENET_OPD_PAUSE_DUR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_OPD_PAUSE_DUR field.
+#define BR_ENET_OPD_PAUSE_DUR(x) (HW_ENET_OPD(x).B.PAUSE_DUR)
+#endif
+
+//! @brief Format value for bitfield ENET_OPD_PAUSE_DUR.
+#define BF_ENET_OPD_PAUSE_DUR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_OPD_PAUSE_DUR), uint32_t) & BM_ENET_OPD_PAUSE_DUR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PAUSE_DUR field to a new value.
+#define BW_ENET_OPD_PAUSE_DUR(x, v) (HW_ENET_OPD_WR(x, (HW_ENET_OPD_RD(x) & ~BM_ENET_OPD_PAUSE_DUR) | BF_ENET_OPD_PAUSE_DUR(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_OPD, field OPCODE[31:16] (RO)
+ *
+ * These fields have a constant value of 0x0001.
+ */
+//@{
+#define BP_ENET_OPD_OPCODE (16U) //!< Bit position for ENET_OPD_OPCODE.
+#define BM_ENET_OPD_OPCODE (0xFFFF0000U) //!< Bit mask for ENET_OPD_OPCODE.
+#define BS_ENET_OPD_OPCODE (16U) //!< Bit field size in bits for ENET_OPD_OPCODE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_OPD_OPCODE field.
+#define BR_ENET_OPD_OPCODE(x) (HW_ENET_OPD(x).B.OPCODE)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IAUR - Descriptor Individual Upper Address Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IAUR - Descriptor Individual Upper Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * IAUR contains the upper 32 bits of the 64-bit individual address hash table.
+ * The address recognition process uses this table to check for a possible match
+ * with the destination address (DA) field of receive frames with an individual
+ * DA. This register is not reset and you must initialize it.
+ */
+typedef union _hw_enet_iaur
+{
+ uint32_t U;
+ struct _hw_enet_iaur_bitfields
+ {
+ uint32_t IADDR1 : 32; //!< [31:0]
+ } B;
+} hw_enet_iaur_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IAUR register
+ */
+//@{
+#define HW_ENET_IAUR_ADDR(x) (REGS_ENET_BASE(x) + 0x118U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IAUR(x) (*(__IO hw_enet_iaur_t *) HW_ENET_IAUR_ADDR(x))
+#define HW_ENET_IAUR_RD(x) (HW_ENET_IAUR(x).U)
+#define HW_ENET_IAUR_WR(x, v) (HW_ENET_IAUR(x).U = (v))
+#define HW_ENET_IAUR_SET(x, v) (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) | (v)))
+#define HW_ENET_IAUR_CLR(x, v) (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) & ~(v)))
+#define HW_ENET_IAUR_TOG(x, v) (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IAUR bitfields
+ */
+
+/*!
+ * @name Register ENET_IAUR, field IADDR1[31:0] (RW)
+ *
+ * Contains the upper 32 bits of the 64-bit hash table used in the address
+ * recognition process for receive frames with a unicast address. Bit 31 of IADDR1
+ * contains hash index bit 63. Bit 0 of IADDR1 contains hash index bit 32.
+ */
+//@{
+#define BP_ENET_IAUR_IADDR1 (0U) //!< Bit position for ENET_IAUR_IADDR1.
+#define BM_ENET_IAUR_IADDR1 (0xFFFFFFFFU) //!< Bit mask for ENET_IAUR_IADDR1.
+#define BS_ENET_IAUR_IADDR1 (32U) //!< Bit field size in bits for ENET_IAUR_IADDR1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IAUR_IADDR1 field.
+#define BR_ENET_IAUR_IADDR1(x) (HW_ENET_IAUR(x).U)
+#endif
+
+//! @brief Format value for bitfield ENET_IAUR_IADDR1.
+#define BF_ENET_IAUR_IADDR1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_IAUR_IADDR1), uint32_t) & BM_ENET_IAUR_IADDR1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IADDR1 field to a new value.
+#define BW_ENET_IAUR_IADDR1(x, v) (HW_ENET_IAUR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IALR - Descriptor Individual Lower Address Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IALR - Descriptor Individual Lower Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * IALR contains the lower 32 bits of the 64-bit individual address hash table.
+ * The address recognition process uses this table to check for a possible match
+ * with the DA field of receive frames with an individual DA. This register is
+ * not reset and you must initialize it.
+ */
+typedef union _hw_enet_ialr
+{
+ uint32_t U;
+ struct _hw_enet_ialr_bitfields
+ {
+ uint32_t IADDR2 : 32; //!< [31:0]
+ } B;
+} hw_enet_ialr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IALR register
+ */
+//@{
+#define HW_ENET_IALR_ADDR(x) (REGS_ENET_BASE(x) + 0x11CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IALR(x) (*(__IO hw_enet_ialr_t *) HW_ENET_IALR_ADDR(x))
+#define HW_ENET_IALR_RD(x) (HW_ENET_IALR(x).U)
+#define HW_ENET_IALR_WR(x, v) (HW_ENET_IALR(x).U = (v))
+#define HW_ENET_IALR_SET(x, v) (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) | (v)))
+#define HW_ENET_IALR_CLR(x, v) (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) & ~(v)))
+#define HW_ENET_IALR_TOG(x, v) (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IALR bitfields
+ */
+
+/*!
+ * @name Register ENET_IALR, field IADDR2[31:0] (RW)
+ *
+ * Contains the lower 32 bits of the 64-bit hash table used in the address
+ * recognition process for receive frames with a unicast address. Bit 31 of IADDR2
+ * contains hash index bit 31. Bit 0 of IADDR2 contains hash index bit 0.
+ */
+//@{
+#define BP_ENET_IALR_IADDR2 (0U) //!< Bit position for ENET_IALR_IADDR2.
+#define BM_ENET_IALR_IADDR2 (0xFFFFFFFFU) //!< Bit mask for ENET_IALR_IADDR2.
+#define BS_ENET_IALR_IADDR2 (32U) //!< Bit field size in bits for ENET_IALR_IADDR2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IALR_IADDR2 field.
+#define BR_ENET_IALR_IADDR2(x) (HW_ENET_IALR(x).U)
+#endif
+
+//! @brief Format value for bitfield ENET_IALR_IADDR2.
+#define BF_ENET_IALR_IADDR2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_IALR_IADDR2), uint32_t) & BM_ENET_IALR_IADDR2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IADDR2 field to a new value.
+#define BW_ENET_IALR_IADDR2(x, v) (HW_ENET_IALR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_GAUR - Descriptor Group Upper Address Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_GAUR - Descriptor Group Upper Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * GAUR contains the upper 32 bits of the 64-bit hash table used in the address
+ * recognition process for receive frames with a multicast address. You must
+ * initialize this register.
+ */
+typedef union _hw_enet_gaur
+{
+ uint32_t U;
+ struct _hw_enet_gaur_bitfields
+ {
+ uint32_t GADDR1 : 32; //!< [31:0]
+ } B;
+} hw_enet_gaur_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_GAUR register
+ */
+//@{
+#define HW_ENET_GAUR_ADDR(x) (REGS_ENET_BASE(x) + 0x120U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_GAUR(x) (*(__IO hw_enet_gaur_t *) HW_ENET_GAUR_ADDR(x))
+#define HW_ENET_GAUR_RD(x) (HW_ENET_GAUR(x).U)
+#define HW_ENET_GAUR_WR(x, v) (HW_ENET_GAUR(x).U = (v))
+#define HW_ENET_GAUR_SET(x, v) (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) | (v)))
+#define HW_ENET_GAUR_CLR(x, v) (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) & ~(v)))
+#define HW_ENET_GAUR_TOG(x, v) (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_GAUR bitfields
+ */
+
+/*!
+ * @name Register ENET_GAUR, field GADDR1[31:0] (RW)
+ *
+ * Contains the upper 32 bits of the 64-bit hash table used in the address
+ * recognition process for receive frames with a multicast address. Bit 31 of GADDR1
+ * contains hash index bit 63. Bit 0 of GADDR1 contains hash index bit 32.
+ */
+//@{
+#define BP_ENET_GAUR_GADDR1 (0U) //!< Bit position for ENET_GAUR_GADDR1.
+#define BM_ENET_GAUR_GADDR1 (0xFFFFFFFFU) //!< Bit mask for ENET_GAUR_GADDR1.
+#define BS_ENET_GAUR_GADDR1 (32U) //!< Bit field size in bits for ENET_GAUR_GADDR1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_GAUR_GADDR1 field.
+#define BR_ENET_GAUR_GADDR1(x) (HW_ENET_GAUR(x).U)
+#endif
+
+//! @brief Format value for bitfield ENET_GAUR_GADDR1.
+#define BF_ENET_GAUR_GADDR1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_GAUR_GADDR1), uint32_t) & BM_ENET_GAUR_GADDR1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GADDR1 field to a new value.
+#define BW_ENET_GAUR_GADDR1(x, v) (HW_ENET_GAUR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_GALR - Descriptor Group Lower Address Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_GALR - Descriptor Group Lower Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * GALR contains the lower 32 bits of the 64-bit hash table used in the address
+ * recognition process for receive frames with a multicast address. You must
+ * initialize this register.
+ */
+typedef union _hw_enet_galr
+{
+ uint32_t U;
+ struct _hw_enet_galr_bitfields
+ {
+ uint32_t GADDR2 : 32; //!< [31:0]
+ } B;
+} hw_enet_galr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_GALR register
+ */
+//@{
+#define HW_ENET_GALR_ADDR(x) (REGS_ENET_BASE(x) + 0x124U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_GALR(x) (*(__IO hw_enet_galr_t *) HW_ENET_GALR_ADDR(x))
+#define HW_ENET_GALR_RD(x) (HW_ENET_GALR(x).U)
+#define HW_ENET_GALR_WR(x, v) (HW_ENET_GALR(x).U = (v))
+#define HW_ENET_GALR_SET(x, v) (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) | (v)))
+#define HW_ENET_GALR_CLR(x, v) (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) & ~(v)))
+#define HW_ENET_GALR_TOG(x, v) (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_GALR bitfields
+ */
+
+/*!
+ * @name Register ENET_GALR, field GADDR2[31:0] (RW)
+ *
+ * Contains the lower 32 bits of the 64-bit hash table used in the address
+ * recognition process for receive frames with a multicast address. Bit 31 of GADDR2
+ * contains hash index bit 31. Bit 0 of GADDR2 contains hash index bit 0.
+ */
+//@{
+#define BP_ENET_GALR_GADDR2 (0U) //!< Bit position for ENET_GALR_GADDR2.
+#define BM_ENET_GALR_GADDR2 (0xFFFFFFFFU) //!< Bit mask for ENET_GALR_GADDR2.
+#define BS_ENET_GALR_GADDR2 (32U) //!< Bit field size in bits for ENET_GALR_GADDR2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_GALR_GADDR2 field.
+#define BR_ENET_GALR_GADDR2(x) (HW_ENET_GALR(x).U)
+#endif
+
+//! @brief Format value for bitfield ENET_GALR_GADDR2.
+#define BF_ENET_GALR_GADDR2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_GALR_GADDR2), uint32_t) & BM_ENET_GALR_GADDR2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GADDR2 field to a new value.
+#define BW_ENET_GALR_GADDR2(x, v) (HW_ENET_GALR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_TFWR - Transmit FIFO Watermark Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_TFWR - Transmit FIFO Watermark Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * If TFWR[STRFWD] is cleared, TFWR[TFWR] controls the amount of data required
+ * in the transmit FIFO before transmission of a frame can begin. This allows you
+ * to minimize transmit latency (TFWR = 00 or 01) or allow for larger bus access
+ * latency (TFWR = 11) due to contention for the system bus. Setting the
+ * watermark to a high value minimizes the risk of transmit FIFO underrun due to
+ * contention for the system bus. The byte counts associated with the TFWR field may need
+ * to be modified to match a given system requirement. For example, worst case
+ * bus access latency by the transmit data DMA channel. When the FIFO level
+ * reaches the value the TFWR field and when the STR_FWD is set to '0', the MAC
+ * transmit control logic starts frame transmission even before the end-of-frame is
+ * available in the FIFO (cut-through operation). If a complete frame has a size
+ * smaller than the threshold programmed with TFWR, the MAC also transmits the Frame
+ * to the line. To enable store and forward on the Transmit path, set STR_FWD to
+ * '1'. In this case, the MAC starts to transmit data only when a complete frame
+ * is stored in the Transmit FIFO.
+ */
+typedef union _hw_enet_tfwr
+{
+ uint32_t U;
+ struct _hw_enet_tfwr_bitfields
+ {
+ uint32_t TFWR : 6; //!< [5:0] Transmit FIFO Write
+ uint32_t RESERVED0 : 2; //!< [7:6]
+ uint32_t STRFWD : 1; //!< [8] Store And Forward Enable
+ uint32_t RESERVED1 : 23; //!< [31:9]
+ } B;
+} hw_enet_tfwr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_TFWR register
+ */
+//@{
+#define HW_ENET_TFWR_ADDR(x) (REGS_ENET_BASE(x) + 0x144U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_TFWR(x) (*(__IO hw_enet_tfwr_t *) HW_ENET_TFWR_ADDR(x))
+#define HW_ENET_TFWR_RD(x) (HW_ENET_TFWR(x).U)
+#define HW_ENET_TFWR_WR(x, v) (HW_ENET_TFWR(x).U = (v))
+#define HW_ENET_TFWR_SET(x, v) (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) | (v)))
+#define HW_ENET_TFWR_CLR(x, v) (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) & ~(v)))
+#define HW_ENET_TFWR_TOG(x, v) (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_TFWR bitfields
+ */
+
+/*!
+ * @name Register ENET_TFWR, field TFWR[5:0] (RW)
+ *
+ * If TFWR[STRFWD] is cleared, this field indicates the number of bytes, in
+ * steps of 64 bytes, written to the transmit FIFO before transmission of a frame
+ * begins. If a frame with less than the threshold is written, it is still sent
+ * independently of this threshold setting. The threshold is relevant only if the
+ * frame is larger than the threshold given. This chip may not support the maximum
+ * number of bytes written shown below. See the chip-specific information for the
+ * ENET module for this value.
+ *
+ * Values:
+ * - 000000 - 64 bytes written.
+ * - 000001 - 64 bytes written.
+ * - 000010 - 128 bytes written.
+ * - 000011 - 192 bytes written.
+ * - 111110 - 3968 bytes written.
+ * - 111111 - 4032 bytes written.
+ */
+//@{
+#define BP_ENET_TFWR_TFWR (0U) //!< Bit position for ENET_TFWR_TFWR.
+#define BM_ENET_TFWR_TFWR (0x0000003FU) //!< Bit mask for ENET_TFWR_TFWR.
+#define BS_ENET_TFWR_TFWR (6U) //!< Bit field size in bits for ENET_TFWR_TFWR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TFWR_TFWR field.
+#define BR_ENET_TFWR_TFWR(x) (HW_ENET_TFWR(x).B.TFWR)
+#endif
+
+//! @brief Format value for bitfield ENET_TFWR_TFWR.
+#define BF_ENET_TFWR_TFWR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TFWR_TFWR), uint32_t) & BM_ENET_TFWR_TFWR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TFWR field to a new value.
+#define BW_ENET_TFWR_TFWR(x, v) (HW_ENET_TFWR_WR(x, (HW_ENET_TFWR_RD(x) & ~BM_ENET_TFWR_TFWR) | BF_ENET_TFWR_TFWR(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TFWR, field STRFWD[8] (RW)
+ *
+ * Values:
+ * - 0 - Reset. The transmission start threshold is programmed in TFWR[TFWR].
+ * - 1 - Enabled.
+ */
+//@{
+#define BP_ENET_TFWR_STRFWD (8U) //!< Bit position for ENET_TFWR_STRFWD.
+#define BM_ENET_TFWR_STRFWD (0x00000100U) //!< Bit mask for ENET_TFWR_STRFWD.
+#define BS_ENET_TFWR_STRFWD (1U) //!< Bit field size in bits for ENET_TFWR_STRFWD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TFWR_STRFWD field.
+#define BR_ENET_TFWR_STRFWD(x) (BITBAND_ACCESS32(HW_ENET_TFWR_ADDR(x), BP_ENET_TFWR_STRFWD))
+#endif
+
+//! @brief Format value for bitfield ENET_TFWR_STRFWD.
+#define BF_ENET_TFWR_STRFWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TFWR_STRFWD), uint32_t) & BM_ENET_TFWR_STRFWD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the STRFWD field to a new value.
+#define BW_ENET_TFWR_STRFWD(x, v) (BITBAND_ACCESS32(HW_ENET_TFWR_ADDR(x), BP_ENET_TFWR_STRFWD) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RDSR - Receive Descriptor Ring Start Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RDSR - Receive Descriptor Ring Start Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RDSR points to the beginning of the circular receive buffer descriptor queue
+ * in external memory. This pointer must be 64-bit aligned (bits 2-0 must be
+ * zero); however, it is recommended to be 128-bit aligned, that is, evenly divisible
+ * by 16. This register must be initialized prior to operation
+ */
+typedef union _hw_enet_rdsr
+{
+ uint32_t U;
+ struct _hw_enet_rdsr_bitfields
+ {
+ uint32_t RESERVED0 : 3; //!< [2:0]
+ uint32_t R_DES_START : 29; //!< [31:3]
+ } B;
+} hw_enet_rdsr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RDSR register
+ */
+//@{
+#define HW_ENET_RDSR_ADDR(x) (REGS_ENET_BASE(x) + 0x180U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RDSR(x) (*(__IO hw_enet_rdsr_t *) HW_ENET_RDSR_ADDR(x))
+#define HW_ENET_RDSR_RD(x) (HW_ENET_RDSR(x).U)
+#define HW_ENET_RDSR_WR(x, v) (HW_ENET_RDSR(x).U = (v))
+#define HW_ENET_RDSR_SET(x, v) (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) | (v)))
+#define HW_ENET_RDSR_CLR(x, v) (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) & ~(v)))
+#define HW_ENET_RDSR_TOG(x, v) (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RDSR bitfields
+ */
+
+/*!
+ * @name Register ENET_RDSR, field R_DES_START[31:3] (RW)
+ *
+ * Pointer to the beginning of the receive buffer descriptor queue.
+ */
+//@{
+#define BP_ENET_RDSR_R_DES_START (3U) //!< Bit position for ENET_RDSR_R_DES_START.
+#define BM_ENET_RDSR_R_DES_START (0xFFFFFFF8U) //!< Bit mask for ENET_RDSR_R_DES_START.
+#define BS_ENET_RDSR_R_DES_START (29U) //!< Bit field size in bits for ENET_RDSR_R_DES_START.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RDSR_R_DES_START field.
+#define BR_ENET_RDSR_R_DES_START(x) (HW_ENET_RDSR(x).B.R_DES_START)
+#endif
+
+//! @brief Format value for bitfield ENET_RDSR_R_DES_START.
+#define BF_ENET_RDSR_R_DES_START(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RDSR_R_DES_START), uint32_t) & BM_ENET_RDSR_R_DES_START)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the R_DES_START field to a new value.
+#define BW_ENET_RDSR_R_DES_START(x, v) (HW_ENET_RDSR_WR(x, (HW_ENET_RDSR_RD(x) & ~BM_ENET_RDSR_R_DES_START) | BF_ENET_RDSR_R_DES_START(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TDSR provides a pointer to the beginning of the circular transmit buffer
+ * descriptor queue in external memory. This pointer must be 64-bit aligned (bits 2-0
+ * must be zero); however, it is recommended to be 128-bit aligned, that is,
+ * evenly divisible by 16. This register must be initialized prior to operation.
+ */
+typedef union _hw_enet_tdsr
+{
+ uint32_t U;
+ struct _hw_enet_tdsr_bitfields
+ {
+ uint32_t RESERVED0 : 3; //!< [2:0]
+ uint32_t X_DES_START : 29; //!< [31:3]
+ } B;
+} hw_enet_tdsr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_TDSR register
+ */
+//@{
+#define HW_ENET_TDSR_ADDR(x) (REGS_ENET_BASE(x) + 0x184U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_TDSR(x) (*(__IO hw_enet_tdsr_t *) HW_ENET_TDSR_ADDR(x))
+#define HW_ENET_TDSR_RD(x) (HW_ENET_TDSR(x).U)
+#define HW_ENET_TDSR_WR(x, v) (HW_ENET_TDSR(x).U = (v))
+#define HW_ENET_TDSR_SET(x, v) (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) | (v)))
+#define HW_ENET_TDSR_CLR(x, v) (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) & ~(v)))
+#define HW_ENET_TDSR_TOG(x, v) (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_TDSR bitfields
+ */
+
+/*!
+ * @name Register ENET_TDSR, field X_DES_START[31:3] (RW)
+ *
+ * Pointer to the beginning of the transmit buffer descriptor queue.
+ */
+//@{
+#define BP_ENET_TDSR_X_DES_START (3U) //!< Bit position for ENET_TDSR_X_DES_START.
+#define BM_ENET_TDSR_X_DES_START (0xFFFFFFF8U) //!< Bit mask for ENET_TDSR_X_DES_START.
+#define BS_ENET_TDSR_X_DES_START (29U) //!< Bit field size in bits for ENET_TDSR_X_DES_START.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TDSR_X_DES_START field.
+#define BR_ENET_TDSR_X_DES_START(x) (HW_ENET_TDSR(x).B.X_DES_START)
+#endif
+
+//! @brief Format value for bitfield ENET_TDSR_X_DES_START.
+#define BF_ENET_TDSR_X_DES_START(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TDSR_X_DES_START), uint32_t) & BM_ENET_TDSR_X_DES_START)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the X_DES_START field to a new value.
+#define BW_ENET_TDSR_X_DES_START(x, v) (HW_ENET_TDSR_WR(x, (HW_ENET_TDSR_RD(x) & ~BM_ENET_TDSR_X_DES_START) | BF_ENET_TDSR_X_DES_START(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_MRBR - Maximum Receive Buffer Size Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_MRBR - Maximum Receive Buffer Size Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MRBR is a user-programmable register that dictates the maximum size of
+ * all receive buffers. This value should take into consideration that the receive
+ * CRC is always written into the last receive buffer. To allow one maximum size
+ * frame per buffer, MRBR must be set to RCR[MAX_FL] or larger. To properly align
+ * the buffer, MRBR must be evenly divisible by 16. To ensure this, bits 3-0 are
+ * set to zero by the device. To minimize bus usage (descriptor fetches), set
+ * MRBR greater than or equal to 256 bytes. This register must be initialized
+ * before operation.
+ */
+typedef union _hw_enet_mrbr
+{
+ uint32_t U;
+ struct _hw_enet_mrbr_bitfields
+ {
+ uint32_t RESERVED0 : 4; //!< [3:0]
+ uint32_t R_BUF_SIZE : 10; //!< [13:4]
+ uint32_t RESERVED1 : 18; //!< [31:14]
+ } B;
+} hw_enet_mrbr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_MRBR register
+ */
+//@{
+#define HW_ENET_MRBR_ADDR(x) (REGS_ENET_BASE(x) + 0x188U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_MRBR(x) (*(__IO hw_enet_mrbr_t *) HW_ENET_MRBR_ADDR(x))
+#define HW_ENET_MRBR_RD(x) (HW_ENET_MRBR(x).U)
+#define HW_ENET_MRBR_WR(x, v) (HW_ENET_MRBR(x).U = (v))
+#define HW_ENET_MRBR_SET(x, v) (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) | (v)))
+#define HW_ENET_MRBR_CLR(x, v) (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) & ~(v)))
+#define HW_ENET_MRBR_TOG(x, v) (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_MRBR bitfields
+ */
+
+/*!
+ * @name Register ENET_MRBR, field R_BUF_SIZE[13:4] (RW)
+ *
+ * Receive buffer size in bytes.
+ */
+//@{
+#define BP_ENET_MRBR_R_BUF_SIZE (4U) //!< Bit position for ENET_MRBR_R_BUF_SIZE.
+#define BM_ENET_MRBR_R_BUF_SIZE (0x00003FF0U) //!< Bit mask for ENET_MRBR_R_BUF_SIZE.
+#define BS_ENET_MRBR_R_BUF_SIZE (10U) //!< Bit field size in bits for ENET_MRBR_R_BUF_SIZE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_MRBR_R_BUF_SIZE field.
+#define BR_ENET_MRBR_R_BUF_SIZE(x) (HW_ENET_MRBR(x).B.R_BUF_SIZE)
+#endif
+
+//! @brief Format value for bitfield ENET_MRBR_R_BUF_SIZE.
+#define BF_ENET_MRBR_R_BUF_SIZE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_MRBR_R_BUF_SIZE), uint32_t) & BM_ENET_MRBR_R_BUF_SIZE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the R_BUF_SIZE field to a new value.
+#define BW_ENET_MRBR_R_BUF_SIZE(x, v) (HW_ENET_MRBR_WR(x, (HW_ENET_MRBR_RD(x) & ~BM_ENET_MRBR_R_BUF_SIZE) | BF_ENET_MRBR_R_BUF_SIZE(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RSFL - Receive FIFO Section Full Threshold
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RSFL - Receive FIFO Section Full Threshold (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rsfl
+{
+ uint32_t U;
+ struct _hw_enet_rsfl_bitfields
+ {
+ uint32_t RX_SECTION_FULL : 8; //!< [7:0] Value Of Receive FIFO
+ //! Section Full Threshold
+ uint32_t RESERVED0 : 24; //!< [31:8]
+ } B;
+} hw_enet_rsfl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RSFL register
+ */
+//@{
+#define HW_ENET_RSFL_ADDR(x) (REGS_ENET_BASE(x) + 0x190U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RSFL(x) (*(__IO hw_enet_rsfl_t *) HW_ENET_RSFL_ADDR(x))
+#define HW_ENET_RSFL_RD(x) (HW_ENET_RSFL(x).U)
+#define HW_ENET_RSFL_WR(x, v) (HW_ENET_RSFL(x).U = (v))
+#define HW_ENET_RSFL_SET(x, v) (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) | (v)))
+#define HW_ENET_RSFL_CLR(x, v) (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) & ~(v)))
+#define HW_ENET_RSFL_TOG(x, v) (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RSFL bitfields
+ */
+
+/*!
+ * @name Register ENET_RSFL, field RX_SECTION_FULL[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO section full threshold. Clear
+ * this field to enable store and forward on the RX FIFO. When programming a value
+ * greater than 0 (cut-through operation), it must be greater than
+ * RAEM[RX_ALMOST_EMPTY]. When the FIFO level reaches the value in this field, data is available
+ * in the Receive FIFO (cut-through operation).
+ */
+//@{
+#define BP_ENET_RSFL_RX_SECTION_FULL (0U) //!< Bit position for ENET_RSFL_RX_SECTION_FULL.
+#define BM_ENET_RSFL_RX_SECTION_FULL (0x000000FFU) //!< Bit mask for ENET_RSFL_RX_SECTION_FULL.
+#define BS_ENET_RSFL_RX_SECTION_FULL (8U) //!< Bit field size in bits for ENET_RSFL_RX_SECTION_FULL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RSFL_RX_SECTION_FULL field.
+#define BR_ENET_RSFL_RX_SECTION_FULL(x) (HW_ENET_RSFL(x).B.RX_SECTION_FULL)
+#endif
+
+//! @brief Format value for bitfield ENET_RSFL_RX_SECTION_FULL.
+#define BF_ENET_RSFL_RX_SECTION_FULL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RSFL_RX_SECTION_FULL), uint32_t) & BM_ENET_RSFL_RX_SECTION_FULL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RX_SECTION_FULL field to a new value.
+#define BW_ENET_RSFL_RX_SECTION_FULL(x, v) (HW_ENET_RSFL_WR(x, (HW_ENET_RSFL_RD(x) & ~BM_ENET_RSFL_RX_SECTION_FULL) | BF_ENET_RSFL_RX_SECTION_FULL(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RSEM - Receive FIFO Section Empty Threshold
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RSEM - Receive FIFO Section Empty Threshold (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rsem
+{
+ uint32_t U;
+ struct _hw_enet_rsem_bitfields
+ {
+ uint32_t RX_SECTION_EMPTY : 8; //!< [7:0] Value Of The Receive FIFO
+ //! Section Empty Threshold
+ uint32_t RESERVED0 : 8; //!< [15:8]
+ uint32_t STAT_SECTION_EMPTY : 5; //!< [20:16] RX Status FIFO Section
+ //! Empty Threshold
+ uint32_t RESERVED1 : 11; //!< [31:21]
+ } B;
+} hw_enet_rsem_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RSEM register
+ */
+//@{
+#define HW_ENET_RSEM_ADDR(x) (REGS_ENET_BASE(x) + 0x194U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RSEM(x) (*(__IO hw_enet_rsem_t *) HW_ENET_RSEM_ADDR(x))
+#define HW_ENET_RSEM_RD(x) (HW_ENET_RSEM(x).U)
+#define HW_ENET_RSEM_WR(x, v) (HW_ENET_RSEM(x).U = (v))
+#define HW_ENET_RSEM_SET(x, v) (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) | (v)))
+#define HW_ENET_RSEM_CLR(x, v) (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) & ~(v)))
+#define HW_ENET_RSEM_TOG(x, v) (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RSEM bitfields
+ */
+
+/*!
+ * @name Register ENET_RSEM, field RX_SECTION_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO section empty threshold. When the
+ * FIFO has reached this level, a pause frame will be issued. A value of 0
+ * disables automatic pause frame generation. When the FIFO level goes below the value
+ * programmed in this field, an XON pause frame is issued to indicate the FIFO
+ * congestion is cleared to the remote Ethernet client. The section-empty
+ * threshold indications from both FIFOs are OR'ed to cause XOFF pause frame generation.
+ */
+//@{
+#define BP_ENET_RSEM_RX_SECTION_EMPTY (0U) //!< Bit position for ENET_RSEM_RX_SECTION_EMPTY.
+#define BM_ENET_RSEM_RX_SECTION_EMPTY (0x000000FFU) //!< Bit mask for ENET_RSEM_RX_SECTION_EMPTY.
+#define BS_ENET_RSEM_RX_SECTION_EMPTY (8U) //!< Bit field size in bits for ENET_RSEM_RX_SECTION_EMPTY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RSEM_RX_SECTION_EMPTY field.
+#define BR_ENET_RSEM_RX_SECTION_EMPTY(x) (HW_ENET_RSEM(x).B.RX_SECTION_EMPTY)
+#endif
+
+//! @brief Format value for bitfield ENET_RSEM_RX_SECTION_EMPTY.
+#define BF_ENET_RSEM_RX_SECTION_EMPTY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RSEM_RX_SECTION_EMPTY), uint32_t) & BM_ENET_RSEM_RX_SECTION_EMPTY)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RX_SECTION_EMPTY field to a new value.
+#define BW_ENET_RSEM_RX_SECTION_EMPTY(x, v) (HW_ENET_RSEM_WR(x, (HW_ENET_RSEM_RD(x) & ~BM_ENET_RSEM_RX_SECTION_EMPTY) | BF_ENET_RSEM_RX_SECTION_EMPTY(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RSEM, field STAT_SECTION_EMPTY[20:16] (RW)
+ *
+ * Defines number of frames in the receive FIFO, independent of its size, that
+ * can be accepted. If the limit is reached, reception will continue normally,
+ * however a pause frame will be triggered to indicate a possible congestion to the
+ * remote device to avoid FIFO overflow. A value of 0 disables automatic pause
+ * frame generation
+ */
+//@{
+#define BP_ENET_RSEM_STAT_SECTION_EMPTY (16U) //!< Bit position for ENET_RSEM_STAT_SECTION_EMPTY.
+#define BM_ENET_RSEM_STAT_SECTION_EMPTY (0x001F0000U) //!< Bit mask for ENET_RSEM_STAT_SECTION_EMPTY.
+#define BS_ENET_RSEM_STAT_SECTION_EMPTY (5U) //!< Bit field size in bits for ENET_RSEM_STAT_SECTION_EMPTY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RSEM_STAT_SECTION_EMPTY field.
+#define BR_ENET_RSEM_STAT_SECTION_EMPTY(x) (HW_ENET_RSEM(x).B.STAT_SECTION_EMPTY)
+#endif
+
+//! @brief Format value for bitfield ENET_RSEM_STAT_SECTION_EMPTY.
+#define BF_ENET_RSEM_STAT_SECTION_EMPTY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RSEM_STAT_SECTION_EMPTY), uint32_t) & BM_ENET_RSEM_STAT_SECTION_EMPTY)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the STAT_SECTION_EMPTY field to a new value.
+#define BW_ENET_RSEM_STAT_SECTION_EMPTY(x, v) (HW_ENET_RSEM_WR(x, (HW_ENET_RSEM_RD(x) & ~BM_ENET_RSEM_STAT_SECTION_EMPTY) | BF_ENET_RSEM_STAT_SECTION_EMPTY(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RAEM - Receive FIFO Almost Empty Threshold
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RAEM - Receive FIFO Almost Empty Threshold (RW)
+ *
+ * Reset value: 0x00000004U
+ */
+typedef union _hw_enet_raem
+{
+ uint32_t U;
+ struct _hw_enet_raem_bitfields
+ {
+ uint32_t RX_ALMOST_EMPTY : 8; //!< [7:0] Value Of The Receive FIFO
+ //! Almost Empty Threshold
+ uint32_t RESERVED0 : 24; //!< [31:8]
+ } B;
+} hw_enet_raem_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RAEM register
+ */
+//@{
+#define HW_ENET_RAEM_ADDR(x) (REGS_ENET_BASE(x) + 0x198U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RAEM(x) (*(__IO hw_enet_raem_t *) HW_ENET_RAEM_ADDR(x))
+#define HW_ENET_RAEM_RD(x) (HW_ENET_RAEM(x).U)
+#define HW_ENET_RAEM_WR(x, v) (HW_ENET_RAEM(x).U = (v))
+#define HW_ENET_RAEM_SET(x, v) (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) | (v)))
+#define HW_ENET_RAEM_CLR(x, v) (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) & ~(v)))
+#define HW_ENET_RAEM_TOG(x, v) (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RAEM bitfields
+ */
+
+/*!
+ * @name Register ENET_RAEM, field RX_ALMOST_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO almost empty threshold. When the
+ * FIFO level reaches the value programmed in this field and the end-of-frame has
+ * not been received for the frame yet, the core receive read control stops FIFO
+ * read (and subsequently stops transferring data to the MAC client
+ * application). It continues to deliver the frame, if again more data than the threshold or
+ * the end-of-frame is available in the FIFO. A minimum value of 4 should be set.
+ */
+//@{
+#define BP_ENET_RAEM_RX_ALMOST_EMPTY (0U) //!< Bit position for ENET_RAEM_RX_ALMOST_EMPTY.
+#define BM_ENET_RAEM_RX_ALMOST_EMPTY (0x000000FFU) //!< Bit mask for ENET_RAEM_RX_ALMOST_EMPTY.
+#define BS_ENET_RAEM_RX_ALMOST_EMPTY (8U) //!< Bit field size in bits for ENET_RAEM_RX_ALMOST_EMPTY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RAEM_RX_ALMOST_EMPTY field.
+#define BR_ENET_RAEM_RX_ALMOST_EMPTY(x) (HW_ENET_RAEM(x).B.RX_ALMOST_EMPTY)
+#endif
+
+//! @brief Format value for bitfield ENET_RAEM_RX_ALMOST_EMPTY.
+#define BF_ENET_RAEM_RX_ALMOST_EMPTY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RAEM_RX_ALMOST_EMPTY), uint32_t) & BM_ENET_RAEM_RX_ALMOST_EMPTY)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RX_ALMOST_EMPTY field to a new value.
+#define BW_ENET_RAEM_RX_ALMOST_EMPTY(x, v) (HW_ENET_RAEM_WR(x, (HW_ENET_RAEM_RD(x) & ~BM_ENET_RAEM_RX_ALMOST_EMPTY) | BF_ENET_RAEM_RX_ALMOST_EMPTY(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RAFL - Receive FIFO Almost Full Threshold
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RAFL - Receive FIFO Almost Full Threshold (RW)
+ *
+ * Reset value: 0x00000004U
+ */
+typedef union _hw_enet_rafl
+{
+ uint32_t U;
+ struct _hw_enet_rafl_bitfields
+ {
+ uint32_t RX_ALMOST_FULL : 8; //!< [7:0] Value Of The Receive FIFO
+ //! Almost Full Threshold
+ uint32_t RESERVED0 : 24; //!< [31:8]
+ } B;
+} hw_enet_rafl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RAFL register
+ */
+//@{
+#define HW_ENET_RAFL_ADDR(x) (REGS_ENET_BASE(x) + 0x19CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RAFL(x) (*(__IO hw_enet_rafl_t *) HW_ENET_RAFL_ADDR(x))
+#define HW_ENET_RAFL_RD(x) (HW_ENET_RAFL(x).U)
+#define HW_ENET_RAFL_WR(x, v) (HW_ENET_RAFL(x).U = (v))
+#define HW_ENET_RAFL_SET(x, v) (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) | (v)))
+#define HW_ENET_RAFL_CLR(x, v) (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) & ~(v)))
+#define HW_ENET_RAFL_TOG(x, v) (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RAFL bitfields
+ */
+
+/*!
+ * @name Register ENET_RAFL, field RX_ALMOST_FULL[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO almost full threshold. When the
+ * FIFO level comes close to the maximum, so that there is no more space for at
+ * least RX_ALMOST_FULL number of words, the MAC stops writing data in the FIFO and
+ * truncates the received frame to avoid FIFO overflow. The corresponding error
+ * status will be set when the frame is delivered to the application. A minimum
+ * value of 4 should be set.
+ */
+//@{
+#define BP_ENET_RAFL_RX_ALMOST_FULL (0U) //!< Bit position for ENET_RAFL_RX_ALMOST_FULL.
+#define BM_ENET_RAFL_RX_ALMOST_FULL (0x000000FFU) //!< Bit mask for ENET_RAFL_RX_ALMOST_FULL.
+#define BS_ENET_RAFL_RX_ALMOST_FULL (8U) //!< Bit field size in bits for ENET_RAFL_RX_ALMOST_FULL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RAFL_RX_ALMOST_FULL field.
+#define BR_ENET_RAFL_RX_ALMOST_FULL(x) (HW_ENET_RAFL(x).B.RX_ALMOST_FULL)
+#endif
+
+//! @brief Format value for bitfield ENET_RAFL_RX_ALMOST_FULL.
+#define BF_ENET_RAFL_RX_ALMOST_FULL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RAFL_RX_ALMOST_FULL), uint32_t) & BM_ENET_RAFL_RX_ALMOST_FULL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RX_ALMOST_FULL field to a new value.
+#define BW_ENET_RAFL_RX_ALMOST_FULL(x, v) (HW_ENET_RAFL_WR(x, (HW_ENET_RAFL_RD(x) & ~BM_ENET_RAFL_RX_ALMOST_FULL) | BF_ENET_RAFL_RX_ALMOST_FULL(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_TSEM - Transmit FIFO Section Empty Threshold
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_TSEM - Transmit FIFO Section Empty Threshold (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_tsem
+{
+ uint32_t U;
+ struct _hw_enet_tsem_bitfields
+ {
+ uint32_t TX_SECTION_EMPTY : 8; //!< [7:0] Value Of The Transmit FIFO
+ //! Section Empty Threshold
+ uint32_t RESERVED0 : 24; //!< [31:8]
+ } B;
+} hw_enet_tsem_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_TSEM register
+ */
+//@{
+#define HW_ENET_TSEM_ADDR(x) (REGS_ENET_BASE(x) + 0x1A0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_TSEM(x) (*(__IO hw_enet_tsem_t *) HW_ENET_TSEM_ADDR(x))
+#define HW_ENET_TSEM_RD(x) (HW_ENET_TSEM(x).U)
+#define HW_ENET_TSEM_WR(x, v) (HW_ENET_TSEM(x).U = (v))
+#define HW_ENET_TSEM_SET(x, v) (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) | (v)))
+#define HW_ENET_TSEM_CLR(x, v) (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) & ~(v)))
+#define HW_ENET_TSEM_TOG(x, v) (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_TSEM bitfields
+ */
+
+/*!
+ * @name Register ENET_TSEM, field TX_SECTION_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the transmit FIFO section empty threshold. See
+ * Transmit FIFOFour programmable thresholds are available which control the core
+ * operation. for more information.
+ */
+//@{
+#define BP_ENET_TSEM_TX_SECTION_EMPTY (0U) //!< Bit position for ENET_TSEM_TX_SECTION_EMPTY.
+#define BM_ENET_TSEM_TX_SECTION_EMPTY (0x000000FFU) //!< Bit mask for ENET_TSEM_TX_SECTION_EMPTY.
+#define BS_ENET_TSEM_TX_SECTION_EMPTY (8U) //!< Bit field size in bits for ENET_TSEM_TX_SECTION_EMPTY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TSEM_TX_SECTION_EMPTY field.
+#define BR_ENET_TSEM_TX_SECTION_EMPTY(x) (HW_ENET_TSEM(x).B.TX_SECTION_EMPTY)
+#endif
+
+//! @brief Format value for bitfield ENET_TSEM_TX_SECTION_EMPTY.
+#define BF_ENET_TSEM_TX_SECTION_EMPTY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TSEM_TX_SECTION_EMPTY), uint32_t) & BM_ENET_TSEM_TX_SECTION_EMPTY)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TX_SECTION_EMPTY field to a new value.
+#define BW_ENET_TSEM_TX_SECTION_EMPTY(x, v) (HW_ENET_TSEM_WR(x, (HW_ENET_TSEM_RD(x) & ~BM_ENET_TSEM_TX_SECTION_EMPTY) | BF_ENET_TSEM_TX_SECTION_EMPTY(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold (RW)
+ *
+ * Reset value: 0x00000004U
+ */
+typedef union _hw_enet_taem
+{
+ uint32_t U;
+ struct _hw_enet_taem_bitfields
+ {
+ uint32_t TX_ALMOST_EMPTY : 8; //!< [7:0] Value of Transmit FIFO
+ //! Almost Empty Threshold
+ uint32_t RESERVED0 : 24; //!< [31:8]
+ } B;
+} hw_enet_taem_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_TAEM register
+ */
+//@{
+#define HW_ENET_TAEM_ADDR(x) (REGS_ENET_BASE(x) + 0x1A4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_TAEM(x) (*(__IO hw_enet_taem_t *) HW_ENET_TAEM_ADDR(x))
+#define HW_ENET_TAEM_RD(x) (HW_ENET_TAEM(x).U)
+#define HW_ENET_TAEM_WR(x, v) (HW_ENET_TAEM(x).U = (v))
+#define HW_ENET_TAEM_SET(x, v) (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) | (v)))
+#define HW_ENET_TAEM_CLR(x, v) (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) & ~(v)))
+#define HW_ENET_TAEM_TOG(x, v) (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_TAEM bitfields
+ */
+
+/*!
+ * @name Register ENET_TAEM, field TX_ALMOST_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the transmit FIFO almost empty threshold. When the
+ * FIFO level reaches the value programmed in this field, and no end-of-frame is
+ * available for the frame, the MAC transmit logic, to avoid FIFO underflow,
+ * stops reading the FIFO and transmits a frame with an MII error indication. See
+ * Transmit FIFOFour programmable thresholds are available which control the core
+ * operation. for more information. A minimum value of 4 should be set.
+ */
+//@{
+#define BP_ENET_TAEM_TX_ALMOST_EMPTY (0U) //!< Bit position for ENET_TAEM_TX_ALMOST_EMPTY.
+#define BM_ENET_TAEM_TX_ALMOST_EMPTY (0x000000FFU) //!< Bit mask for ENET_TAEM_TX_ALMOST_EMPTY.
+#define BS_ENET_TAEM_TX_ALMOST_EMPTY (8U) //!< Bit field size in bits for ENET_TAEM_TX_ALMOST_EMPTY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TAEM_TX_ALMOST_EMPTY field.
+#define BR_ENET_TAEM_TX_ALMOST_EMPTY(x) (HW_ENET_TAEM(x).B.TX_ALMOST_EMPTY)
+#endif
+
+//! @brief Format value for bitfield ENET_TAEM_TX_ALMOST_EMPTY.
+#define BF_ENET_TAEM_TX_ALMOST_EMPTY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TAEM_TX_ALMOST_EMPTY), uint32_t) & BM_ENET_TAEM_TX_ALMOST_EMPTY)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TX_ALMOST_EMPTY field to a new value.
+#define BW_ENET_TAEM_TX_ALMOST_EMPTY(x, v) (HW_ENET_TAEM_WR(x, (HW_ENET_TAEM_RD(x) & ~BM_ENET_TAEM_TX_ALMOST_EMPTY) | BF_ENET_TAEM_TX_ALMOST_EMPTY(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_TAFL - Transmit FIFO Almost Full Threshold
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_TAFL - Transmit FIFO Almost Full Threshold (RW)
+ *
+ * Reset value: 0x00000008U
+ */
+typedef union _hw_enet_tafl
+{
+ uint32_t U;
+ struct _hw_enet_tafl_bitfields
+ {
+ uint32_t TX_ALMOST_FULL : 8; //!< [7:0] Value Of The Transmit FIFO
+ //! Almost Full Threshold
+ uint32_t RESERVED0 : 24; //!< [31:8]
+ } B;
+} hw_enet_tafl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_TAFL register
+ */
+//@{
+#define HW_ENET_TAFL_ADDR(x) (REGS_ENET_BASE(x) + 0x1A8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_TAFL(x) (*(__IO hw_enet_tafl_t *) HW_ENET_TAFL_ADDR(x))
+#define HW_ENET_TAFL_RD(x) (HW_ENET_TAFL(x).U)
+#define HW_ENET_TAFL_WR(x, v) (HW_ENET_TAFL(x).U = (v))
+#define HW_ENET_TAFL_SET(x, v) (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) | (v)))
+#define HW_ENET_TAFL_CLR(x, v) (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) & ~(v)))
+#define HW_ENET_TAFL_TOG(x, v) (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_TAFL bitfields
+ */
+
+/*!
+ * @name Register ENET_TAFL, field TX_ALMOST_FULL[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the transmit FIFO almost full threshold. A minimum
+ * value of six is required . A recommended value of at least 8 should be set
+ * allowing a latency of two clock cycles to the application. If more latency is
+ * required the value can be increased as necessary (latency = TAFL - 5). When the
+ * FIFO level comes close to the maximum, so that there is no more space for at
+ * least TX_ALMOST_FULL number of words, the pin ff_tx_rdy is deasserted. If the
+ * application does not react on this signal, the FIFO write control logic, to
+ * avoid FIFO overflow, truncates the current frame and sets the error status. As a
+ * result, the frame will be transmitted with an GMII/MII error indication. See
+ * Transmit FIFOFour programmable thresholds are available which control the core
+ * operation. for more information. A FIFO overflow is a fatal error and requires
+ * a global reset on the transmit datapath or at least deassertion of ETHEREN.
+ */
+//@{
+#define BP_ENET_TAFL_TX_ALMOST_FULL (0U) //!< Bit position for ENET_TAFL_TX_ALMOST_FULL.
+#define BM_ENET_TAFL_TX_ALMOST_FULL (0x000000FFU) //!< Bit mask for ENET_TAFL_TX_ALMOST_FULL.
+#define BS_ENET_TAFL_TX_ALMOST_FULL (8U) //!< Bit field size in bits for ENET_TAFL_TX_ALMOST_FULL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TAFL_TX_ALMOST_FULL field.
+#define BR_ENET_TAFL_TX_ALMOST_FULL(x) (HW_ENET_TAFL(x).B.TX_ALMOST_FULL)
+#endif
+
+//! @brief Format value for bitfield ENET_TAFL_TX_ALMOST_FULL.
+#define BF_ENET_TAFL_TX_ALMOST_FULL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TAFL_TX_ALMOST_FULL), uint32_t) & BM_ENET_TAFL_TX_ALMOST_FULL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TX_ALMOST_FULL field to a new value.
+#define BW_ENET_TAFL_TX_ALMOST_FULL(x, v) (HW_ENET_TAFL_WR(x, (HW_ENET_TAFL_RD(x) & ~BM_ENET_TAFL_TX_ALMOST_FULL) | BF_ENET_TAFL_TX_ALMOST_FULL(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_TIPG - Transmit Inter-Packet Gap
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_TIPG - Transmit Inter-Packet Gap (RW)
+ *
+ * Reset value: 0x0000000CU
+ */
+typedef union _hw_enet_tipg
+{
+ uint32_t U;
+ struct _hw_enet_tipg_bitfields
+ {
+ uint32_t IPG : 5; //!< [4:0] Transmit Inter-Packet Gap
+ uint32_t RESERVED0 : 27; //!< [31:5]
+ } B;
+} hw_enet_tipg_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_TIPG register
+ */
+//@{
+#define HW_ENET_TIPG_ADDR(x) (REGS_ENET_BASE(x) + 0x1ACU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_TIPG(x) (*(__IO hw_enet_tipg_t *) HW_ENET_TIPG_ADDR(x))
+#define HW_ENET_TIPG_RD(x) (HW_ENET_TIPG(x).U)
+#define HW_ENET_TIPG_WR(x, v) (HW_ENET_TIPG(x).U = (v))
+#define HW_ENET_TIPG_SET(x, v) (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) | (v)))
+#define HW_ENET_TIPG_CLR(x, v) (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) & ~(v)))
+#define HW_ENET_TIPG_TOG(x, v) (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_TIPG bitfields
+ */
+
+/*!
+ * @name Register ENET_TIPG, field IPG[4:0] (RW)
+ *
+ * Indicates the IPG, in bytes, between transmitted frames. Valid values range
+ * from 8 to 27. If value is less than 8, the IPG is 8. If value is greater than
+ * 27, the IPG is 27.
+ */
+//@{
+#define BP_ENET_TIPG_IPG (0U) //!< Bit position for ENET_TIPG_IPG.
+#define BM_ENET_TIPG_IPG (0x0000001FU) //!< Bit mask for ENET_TIPG_IPG.
+#define BS_ENET_TIPG_IPG (5U) //!< Bit field size in bits for ENET_TIPG_IPG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TIPG_IPG field.
+#define BR_ENET_TIPG_IPG(x) (HW_ENET_TIPG(x).B.IPG)
+#endif
+
+//! @brief Format value for bitfield ENET_TIPG_IPG.
+#define BF_ENET_TIPG_IPG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TIPG_IPG), uint32_t) & BM_ENET_TIPG_IPG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IPG field to a new value.
+#define BW_ENET_TIPG_IPG(x, v) (HW_ENET_TIPG_WR(x, (HW_ENET_TIPG_RD(x) & ~BM_ENET_TIPG_IPG) | BF_ENET_TIPG_IPG(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_FTRL - Frame Truncation Length
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_FTRL - Frame Truncation Length (RW)
+ *
+ * Reset value: 0x000007FFU
+ */
+typedef union _hw_enet_ftrl
+{
+ uint32_t U;
+ struct _hw_enet_ftrl_bitfields
+ {
+ uint32_t TRUNC_FL : 14; //!< [13:0] Frame Truncation Length
+ uint32_t RESERVED0 : 18; //!< [31:14]
+ } B;
+} hw_enet_ftrl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_FTRL register
+ */
+//@{
+#define HW_ENET_FTRL_ADDR(x) (REGS_ENET_BASE(x) + 0x1B0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_FTRL(x) (*(__IO hw_enet_ftrl_t *) HW_ENET_FTRL_ADDR(x))
+#define HW_ENET_FTRL_RD(x) (HW_ENET_FTRL(x).U)
+#define HW_ENET_FTRL_WR(x, v) (HW_ENET_FTRL(x).U = (v))
+#define HW_ENET_FTRL_SET(x, v) (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) | (v)))
+#define HW_ENET_FTRL_CLR(x, v) (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) & ~(v)))
+#define HW_ENET_FTRL_TOG(x, v) (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_FTRL bitfields
+ */
+
+/*!
+ * @name Register ENET_FTRL, field TRUNC_FL[13:0] (RW)
+ *
+ * Indicates the value a receive frame is truncated, if it is greater than this
+ * value. Must be greater than or equal to RCR[MAX_FL]. Truncation happens at
+ * TRUNC_FL. However, when truncation occurs, the application (FIFO) may receive
+ * less data, guaranteeing that it never receives more than the set limit.
+ */
+//@{
+#define BP_ENET_FTRL_TRUNC_FL (0U) //!< Bit position for ENET_FTRL_TRUNC_FL.
+#define BM_ENET_FTRL_TRUNC_FL (0x00003FFFU) //!< Bit mask for ENET_FTRL_TRUNC_FL.
+#define BS_ENET_FTRL_TRUNC_FL (14U) //!< Bit field size in bits for ENET_FTRL_TRUNC_FL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_FTRL_TRUNC_FL field.
+#define BR_ENET_FTRL_TRUNC_FL(x) (HW_ENET_FTRL(x).B.TRUNC_FL)
+#endif
+
+//! @brief Format value for bitfield ENET_FTRL_TRUNC_FL.
+#define BF_ENET_FTRL_TRUNC_FL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_FTRL_TRUNC_FL), uint32_t) & BM_ENET_FTRL_TRUNC_FL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TRUNC_FL field to a new value.
+#define BW_ENET_FTRL_TRUNC_FL(x, v) (HW_ENET_FTRL_WR(x, (HW_ENET_FTRL_RD(x) & ~BM_ENET_FTRL_TRUNC_FL) | BF_ENET_FTRL_TRUNC_FL(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_TACC - Transmit Accelerator Function Configuration
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_TACC - Transmit Accelerator Function Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TACC controls accelerator actions when sending frames. The register can be
+ * changed before or after each frame, but it must remain unmodified during frame
+ * writes into the transmit FIFO. The TFWR[STRFWD] field must be set to use the
+ * checksum feature.
+ */
+typedef union _hw_enet_tacc
+{
+ uint32_t U;
+ struct _hw_enet_tacc_bitfields
+ {
+ uint32_t SHIFT16 : 1; //!< [0] TX FIFO Shift-16
+ uint32_t RESERVED0 : 2; //!< [2:1]
+ uint32_t IPCHK : 1; //!< [3]
+ uint32_t PROCHK : 1; //!< [4]
+ uint32_t RESERVED1 : 27; //!< [31:5]
+ } B;
+} hw_enet_tacc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_TACC register
+ */
+//@{
+#define HW_ENET_TACC_ADDR(x) (REGS_ENET_BASE(x) + 0x1C0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_TACC(x) (*(__IO hw_enet_tacc_t *) HW_ENET_TACC_ADDR(x))
+#define HW_ENET_TACC_RD(x) (HW_ENET_TACC(x).U)
+#define HW_ENET_TACC_WR(x, v) (HW_ENET_TACC(x).U = (v))
+#define HW_ENET_TACC_SET(x, v) (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) | (v)))
+#define HW_ENET_TACC_CLR(x, v) (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) & ~(v)))
+#define HW_ENET_TACC_TOG(x, v) (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_TACC bitfields
+ */
+
+/*!
+ * @name Register ENET_TACC, field SHIFT16[0] (RW)
+ *
+ * Values:
+ * - 0 - Disabled.
+ * - 1 - Indicates to the transmit data FIFO that the written frames contain two
+ * additional octets before the frame data. This means the actual frame
+ * begins at bit 16 of the first word written into the FIFO. This function allows
+ * putting the frame payload on a 32-bit boundary in memory, as the 14-byte
+ * Ethernet header is extended to a 16-byte header.
+ */
+//@{
+#define BP_ENET_TACC_SHIFT16 (0U) //!< Bit position for ENET_TACC_SHIFT16.
+#define BM_ENET_TACC_SHIFT16 (0x00000001U) //!< Bit mask for ENET_TACC_SHIFT16.
+#define BS_ENET_TACC_SHIFT16 (1U) //!< Bit field size in bits for ENET_TACC_SHIFT16.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TACC_SHIFT16 field.
+#define BR_ENET_TACC_SHIFT16(x) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_SHIFT16))
+#endif
+
+//! @brief Format value for bitfield ENET_TACC_SHIFT16.
+#define BF_ENET_TACC_SHIFT16(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TACC_SHIFT16), uint32_t) & BM_ENET_TACC_SHIFT16)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SHIFT16 field to a new value.
+#define BW_ENET_TACC_SHIFT16(x, v) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_SHIFT16) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TACC, field IPCHK[3] (RW)
+ *
+ * Enables insertion of IP header checksum.
+ *
+ * Values:
+ * - 0 - Checksum is not inserted.
+ * - 1 - If an IP frame is transmitted, the checksum is inserted automatically.
+ * The IP header checksum field must be cleared. If a non-IP frame is
+ * transmitted the frame is not modified.
+ */
+//@{
+#define BP_ENET_TACC_IPCHK (3U) //!< Bit position for ENET_TACC_IPCHK.
+#define BM_ENET_TACC_IPCHK (0x00000008U) //!< Bit mask for ENET_TACC_IPCHK.
+#define BS_ENET_TACC_IPCHK (1U) //!< Bit field size in bits for ENET_TACC_IPCHK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TACC_IPCHK field.
+#define BR_ENET_TACC_IPCHK(x) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_IPCHK))
+#endif
+
+//! @brief Format value for bitfield ENET_TACC_IPCHK.
+#define BF_ENET_TACC_IPCHK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TACC_IPCHK), uint32_t) & BM_ENET_TACC_IPCHK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IPCHK field to a new value.
+#define BW_ENET_TACC_IPCHK(x, v) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_IPCHK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TACC, field PROCHK[4] (RW)
+ *
+ * Enables insertion of protocol checksum.
+ *
+ * Values:
+ * - 0 - Checksum not inserted.
+ * - 1 - If an IP frame with a known protocol is transmitted, the checksum is
+ * inserted automatically into the frame. The checksum field must be cleared.
+ * The other frames are not modified.
+ */
+//@{
+#define BP_ENET_TACC_PROCHK (4U) //!< Bit position for ENET_TACC_PROCHK.
+#define BM_ENET_TACC_PROCHK (0x00000010U) //!< Bit mask for ENET_TACC_PROCHK.
+#define BS_ENET_TACC_PROCHK (1U) //!< Bit field size in bits for ENET_TACC_PROCHK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TACC_PROCHK field.
+#define BR_ENET_TACC_PROCHK(x) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_PROCHK))
+#endif
+
+//! @brief Format value for bitfield ENET_TACC_PROCHK.
+#define BF_ENET_TACC_PROCHK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TACC_PROCHK), uint32_t) & BM_ENET_TACC_PROCHK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PROCHK field to a new value.
+#define BW_ENET_TACC_PROCHK(x, v) (BITBAND_ACCESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_PROCHK) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RACC - Receive Accelerator Function Configuration
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RACC - Receive Accelerator Function Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_racc
+{
+ uint32_t U;
+ struct _hw_enet_racc_bitfields
+ {
+ uint32_t PADREM : 1; //!< [0] Enable Padding Removal For Short IP
+ //! Frames
+ uint32_t IPDIS : 1; //!< [1] Enable Discard Of Frames With Wrong IPv4
+ //! Header Checksum
+ uint32_t PRODIS : 1; //!< [2] Enable Discard Of Frames With Wrong
+ //! Protocol Checksum
+ uint32_t RESERVED0 : 3; //!< [5:3]
+ uint32_t LINEDIS : 1; //!< [6] Enable Discard Of Frames With MAC
+ //! Layer Errors
+ uint32_t SHIFT16 : 1; //!< [7] RX FIFO Shift-16
+ uint32_t RESERVED1 : 24; //!< [31:8]
+ } B;
+} hw_enet_racc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RACC register
+ */
+//@{
+#define HW_ENET_RACC_ADDR(x) (REGS_ENET_BASE(x) + 0x1C4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RACC(x) (*(__IO hw_enet_racc_t *) HW_ENET_RACC_ADDR(x))
+#define HW_ENET_RACC_RD(x) (HW_ENET_RACC(x).U)
+#define HW_ENET_RACC_WR(x, v) (HW_ENET_RACC(x).U = (v))
+#define HW_ENET_RACC_SET(x, v) (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) | (v)))
+#define HW_ENET_RACC_CLR(x, v) (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) & ~(v)))
+#define HW_ENET_RACC_TOG(x, v) (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RACC bitfields
+ */
+
+/*!
+ * @name Register ENET_RACC, field PADREM[0] (RW)
+ *
+ * Values:
+ * - 0 - Padding not removed.
+ * - 1 - Any bytes following the IP payload section of the frame are removed
+ * from the frame.
+ */
+//@{
+#define BP_ENET_RACC_PADREM (0U) //!< Bit position for ENET_RACC_PADREM.
+#define BM_ENET_RACC_PADREM (0x00000001U) //!< Bit mask for ENET_RACC_PADREM.
+#define BS_ENET_RACC_PADREM (1U) //!< Bit field size in bits for ENET_RACC_PADREM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RACC_PADREM field.
+#define BR_ENET_RACC_PADREM(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PADREM))
+#endif
+
+//! @brief Format value for bitfield ENET_RACC_PADREM.
+#define BF_ENET_RACC_PADREM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RACC_PADREM), uint32_t) & BM_ENET_RACC_PADREM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PADREM field to a new value.
+#define BW_ENET_RACC_PADREM(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PADREM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RACC, field IPDIS[1] (RW)
+ *
+ * Values:
+ * - 0 - Frames with wrong IPv4 header checksum are not discarded.
+ * - 1 - If an IPv4 frame is received with a mismatching header checksum, the
+ * frame is discarded. IPv6 has no header checksum and is not affected by this
+ * setting. Discarding is only available when the RX FIFO operates in store
+ * and forward mode (RSFL cleared).
+ */
+//@{
+#define BP_ENET_RACC_IPDIS (1U) //!< Bit position for ENET_RACC_IPDIS.
+#define BM_ENET_RACC_IPDIS (0x00000002U) //!< Bit mask for ENET_RACC_IPDIS.
+#define BS_ENET_RACC_IPDIS (1U) //!< Bit field size in bits for ENET_RACC_IPDIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RACC_IPDIS field.
+#define BR_ENET_RACC_IPDIS(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_IPDIS))
+#endif
+
+//! @brief Format value for bitfield ENET_RACC_IPDIS.
+#define BF_ENET_RACC_IPDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RACC_IPDIS), uint32_t) & BM_ENET_RACC_IPDIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IPDIS field to a new value.
+#define BW_ENET_RACC_IPDIS(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_IPDIS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RACC, field PRODIS[2] (RW)
+ *
+ * Values:
+ * - 0 - Frames with wrong checksum are not discarded.
+ * - 1 - If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP,
+ * UDP, or ICMP checksum, the frame is discarded. Discarding is only
+ * available when the RX FIFO operates in store and forward mode (RSFL cleared).
+ */
+//@{
+#define BP_ENET_RACC_PRODIS (2U) //!< Bit position for ENET_RACC_PRODIS.
+#define BM_ENET_RACC_PRODIS (0x00000004U) //!< Bit mask for ENET_RACC_PRODIS.
+#define BS_ENET_RACC_PRODIS (1U) //!< Bit field size in bits for ENET_RACC_PRODIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RACC_PRODIS field.
+#define BR_ENET_RACC_PRODIS(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PRODIS))
+#endif
+
+//! @brief Format value for bitfield ENET_RACC_PRODIS.
+#define BF_ENET_RACC_PRODIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RACC_PRODIS), uint32_t) & BM_ENET_RACC_PRODIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PRODIS field to a new value.
+#define BW_ENET_RACC_PRODIS(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PRODIS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RACC, field LINEDIS[6] (RW)
+ *
+ * Values:
+ * - 0 - Frames with errors are not discarded.
+ * - 1 - Any frame received with a CRC, length, or PHY error is automatically
+ * discarded and not forwarded to the user application interface.
+ */
+//@{
+#define BP_ENET_RACC_LINEDIS (6U) //!< Bit position for ENET_RACC_LINEDIS.
+#define BM_ENET_RACC_LINEDIS (0x00000040U) //!< Bit mask for ENET_RACC_LINEDIS.
+#define BS_ENET_RACC_LINEDIS (1U) //!< Bit field size in bits for ENET_RACC_LINEDIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RACC_LINEDIS field.
+#define BR_ENET_RACC_LINEDIS(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_LINEDIS))
+#endif
+
+//! @brief Format value for bitfield ENET_RACC_LINEDIS.
+#define BF_ENET_RACC_LINEDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RACC_LINEDIS), uint32_t) & BM_ENET_RACC_LINEDIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LINEDIS field to a new value.
+#define BW_ENET_RACC_LINEDIS(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_LINEDIS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_RACC, field SHIFT16[7] (RW)
+ *
+ * When this field is set, the actual frame data starts at bit 16 of the first
+ * word read from the RX FIFO aligning the Ethernet payload on a 32-bit boundary.
+ * This function only affects the FIFO storage and has no influence on the
+ * statistics, which use the actual length of the frame received.
+ *
+ * Values:
+ * - 0 - Disabled.
+ * - 1 - Instructs the MAC to write two additional bytes in front of each frame
+ * received into the RX FIFO.
+ */
+//@{
+#define BP_ENET_RACC_SHIFT16 (7U) //!< Bit position for ENET_RACC_SHIFT16.
+#define BM_ENET_RACC_SHIFT16 (0x00000080U) //!< Bit mask for ENET_RACC_SHIFT16.
+#define BS_ENET_RACC_SHIFT16 (1U) //!< Bit field size in bits for ENET_RACC_SHIFT16.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RACC_SHIFT16 field.
+#define BR_ENET_RACC_SHIFT16(x) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_SHIFT16))
+#endif
+
+//! @brief Format value for bitfield ENET_RACC_SHIFT16.
+#define BF_ENET_RACC_SHIFT16(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_RACC_SHIFT16), uint32_t) & BM_ENET_RACC_SHIFT16)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SHIFT16 field to a new value.
+#define BW_ENET_RACC_SHIFT16(x, v) (BITBAND_ACCESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_SHIFT16) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_t_packets
+{
+ uint32_t U;
+ struct _hw_enet_rmon_t_packets_bitfields
+ {
+ uint32_t TXPKTS : 16; //!< [15:0] Packet count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_t_packets_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_PACKETS register
+ */
+//@{
+#define HW_ENET_RMON_T_PACKETS_ADDR(x) (REGS_ENET_BASE(x) + 0x204U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_PACKETS(x) (*(__I hw_enet_rmon_t_packets_t *) HW_ENET_RMON_T_PACKETS_ADDR(x))
+#define HW_ENET_RMON_T_PACKETS_RD(x) (HW_ENET_RMON_T_PACKETS(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_PACKETS bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_PACKETS, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_PACKETS_TXPKTS (0U) //!< Bit position for ENET_RMON_T_PACKETS_TXPKTS.
+#define BM_ENET_RMON_T_PACKETS_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_PACKETS_TXPKTS.
+#define BS_ENET_RMON_T_PACKETS_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_PACKETS_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_PACKETS_TXPKTS field.
+#define BR_ENET_RMON_T_PACKETS_TXPKTS(x) (HW_ENET_RMON_T_PACKETS(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RMON Tx Broadcast Packets
+ */
+typedef union _hw_enet_rmon_t_bc_pkt
+{
+ uint32_t U;
+ struct _hw_enet_rmon_t_bc_pkt_bitfields
+ {
+ uint32_t TXPKTS : 16; //!< [15:0] Broadcast packets
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_t_bc_pkt_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_BC_PKT register
+ */
+//@{
+#define HW_ENET_RMON_T_BC_PKT_ADDR(x) (REGS_ENET_BASE(x) + 0x208U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_BC_PKT(x) (*(__I hw_enet_rmon_t_bc_pkt_t *) HW_ENET_RMON_T_BC_PKT_ADDR(x))
+#define HW_ENET_RMON_T_BC_PKT_RD(x) (HW_ENET_RMON_T_BC_PKT(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_BC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_BC_PKT, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_BC_PKT_TXPKTS (0U) //!< Bit position for ENET_RMON_T_BC_PKT_TXPKTS.
+#define BM_ENET_RMON_T_BC_PKT_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_BC_PKT_TXPKTS.
+#define BS_ENET_RMON_T_BC_PKT_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_BC_PKT_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_BC_PKT_TXPKTS field.
+#define BR_ENET_RMON_T_BC_PKT_TXPKTS(x) (HW_ENET_RMON_T_BC_PKT(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_t_mc_pkt
+{
+ uint32_t U;
+ struct _hw_enet_rmon_t_mc_pkt_bitfields
+ {
+ uint32_t TXPKTS : 16; //!< [15:0] Multicast packets
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_t_mc_pkt_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_MC_PKT register
+ */
+//@{
+#define HW_ENET_RMON_T_MC_PKT_ADDR(x) (REGS_ENET_BASE(x) + 0x20CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_MC_PKT(x) (*(__I hw_enet_rmon_t_mc_pkt_t *) HW_ENET_RMON_T_MC_PKT_ADDR(x))
+#define HW_ENET_RMON_T_MC_PKT_RD(x) (HW_ENET_RMON_T_MC_PKT(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_MC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_MC_PKT, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_MC_PKT_TXPKTS (0U) //!< Bit position for ENET_RMON_T_MC_PKT_TXPKTS.
+#define BM_ENET_RMON_T_MC_PKT_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_MC_PKT_TXPKTS.
+#define BS_ENET_RMON_T_MC_PKT_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_MC_PKT_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_MC_PKT_TXPKTS field.
+#define BR_ENET_RMON_T_MC_PKT_TXPKTS(x) (HW_ENET_RMON_T_MC_PKT(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_t_crc_align
+{
+ uint32_t U;
+ struct _hw_enet_rmon_t_crc_align_bitfields
+ {
+ uint32_t TXPKTS : 16; //!< [15:0] Packets with CRC/align error
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_t_crc_align_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_CRC_ALIGN register
+ */
+//@{
+#define HW_ENET_RMON_T_CRC_ALIGN_ADDR(x) (REGS_ENET_BASE(x) + 0x210U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_CRC_ALIGN(x) (*(__I hw_enet_rmon_t_crc_align_t *) HW_ENET_RMON_T_CRC_ALIGN_ADDR(x))
+#define HW_ENET_RMON_T_CRC_ALIGN_RD(x) (HW_ENET_RMON_T_CRC_ALIGN(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_CRC_ALIGN bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_CRC_ALIGN, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_CRC_ALIGN_TXPKTS (0U) //!< Bit position for ENET_RMON_T_CRC_ALIGN_TXPKTS.
+#define BM_ENET_RMON_T_CRC_ALIGN_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_CRC_ALIGN_TXPKTS.
+#define BS_ENET_RMON_T_CRC_ALIGN_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_CRC_ALIGN_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_CRC_ALIGN_TXPKTS field.
+#define BR_ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (HW_ENET_RMON_T_CRC_ALIGN(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_t_undersize
+{
+ uint32_t U;
+ struct _hw_enet_rmon_t_undersize_bitfields
+ {
+ uint32_t TXPKTS : 16; //!< [15:0] Packet count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_t_undersize_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_UNDERSIZE register
+ */
+//@{
+#define HW_ENET_RMON_T_UNDERSIZE_ADDR(x) (REGS_ENET_BASE(x) + 0x214U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_UNDERSIZE(x) (*(__I hw_enet_rmon_t_undersize_t *) HW_ENET_RMON_T_UNDERSIZE_ADDR(x))
+#define HW_ENET_RMON_T_UNDERSIZE_RD(x) (HW_ENET_RMON_T_UNDERSIZE(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_UNDERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_UNDERSIZE, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_UNDERSIZE_TXPKTS (0U) //!< Bit position for ENET_RMON_T_UNDERSIZE_TXPKTS.
+#define BM_ENET_RMON_T_UNDERSIZE_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_UNDERSIZE_TXPKTS.
+#define BS_ENET_RMON_T_UNDERSIZE_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_UNDERSIZE_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_UNDERSIZE_TXPKTS field.
+#define BR_ENET_RMON_T_UNDERSIZE_TXPKTS(x) (HW_ENET_RMON_T_UNDERSIZE(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_t_oversize
+{
+ uint32_t U;
+ struct _hw_enet_rmon_t_oversize_bitfields
+ {
+ uint32_t TXPKTS : 16; //!< [15:0] Packet count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_t_oversize_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_OVERSIZE register
+ */
+//@{
+#define HW_ENET_RMON_T_OVERSIZE_ADDR(x) (REGS_ENET_BASE(x) + 0x218U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_OVERSIZE(x) (*(__I hw_enet_rmon_t_oversize_t *) HW_ENET_RMON_T_OVERSIZE_ADDR(x))
+#define HW_ENET_RMON_T_OVERSIZE_RD(x) (HW_ENET_RMON_T_OVERSIZE(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_OVERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_OVERSIZE, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_OVERSIZE_TXPKTS (0U) //!< Bit position for ENET_RMON_T_OVERSIZE_TXPKTS.
+#define BM_ENET_RMON_T_OVERSIZE_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_OVERSIZE_TXPKTS.
+#define BS_ENET_RMON_T_OVERSIZE_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_OVERSIZE_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_OVERSIZE_TXPKTS field.
+#define BR_ENET_RMON_T_OVERSIZE_TXPKTS(x) (HW_ENET_RMON_T_OVERSIZE(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+typedef union _hw_enet_rmon_t_frag
+{
+ uint32_t U;
+ struct _hw_enet_rmon_t_frag_bitfields
+ {
+ uint32_t TXPKTS : 16; //!< [15:0] Packet count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_t_frag_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_FRAG register
+ */
+//@{
+#define HW_ENET_RMON_T_FRAG_ADDR(x) (REGS_ENET_BASE(x) + 0x21CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_FRAG(x) (*(__I hw_enet_rmon_t_frag_t *) HW_ENET_RMON_T_FRAG_ADDR(x))
+#define HW_ENET_RMON_T_FRAG_RD(x) (HW_ENET_RMON_T_FRAG(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_FRAG bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_FRAG, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_FRAG_TXPKTS (0U) //!< Bit position for ENET_RMON_T_FRAG_TXPKTS.
+#define BM_ENET_RMON_T_FRAG_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_FRAG_TXPKTS.
+#define BS_ENET_RMON_T_FRAG_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_FRAG_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_FRAG_TXPKTS field.
+#define BR_ENET_RMON_T_FRAG_TXPKTS(x) (HW_ENET_RMON_T_FRAG(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_t_jab
+{
+ uint32_t U;
+ struct _hw_enet_rmon_t_jab_bitfields
+ {
+ uint32_t TXPKTS : 16; //!< [15:0] Packet count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_t_jab_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_JAB register
+ */
+//@{
+#define HW_ENET_RMON_T_JAB_ADDR(x) (REGS_ENET_BASE(x) + 0x220U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_JAB(x) (*(__I hw_enet_rmon_t_jab_t *) HW_ENET_RMON_T_JAB_ADDR(x))
+#define HW_ENET_RMON_T_JAB_RD(x) (HW_ENET_RMON_T_JAB(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_JAB bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_JAB, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_JAB_TXPKTS (0U) //!< Bit position for ENET_RMON_T_JAB_TXPKTS.
+#define BM_ENET_RMON_T_JAB_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_JAB_TXPKTS.
+#define BS_ENET_RMON_T_JAB_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_JAB_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_JAB_TXPKTS field.
+#define BR_ENET_RMON_T_JAB_TXPKTS(x) (HW_ENET_RMON_T_JAB(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_t_col
+{
+ uint32_t U;
+ struct _hw_enet_rmon_t_col_bitfields
+ {
+ uint32_t TXPKTS : 16; //!< [15:0] Packet count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_t_col_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_COL register
+ */
+//@{
+#define HW_ENET_RMON_T_COL_ADDR(x) (REGS_ENET_BASE(x) + 0x224U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_COL(x) (*(__I hw_enet_rmon_t_col_t *) HW_ENET_RMON_T_COL_ADDR(x))
+#define HW_ENET_RMON_T_COL_RD(x) (HW_ENET_RMON_T_COL(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_COL bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_COL, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_COL_TXPKTS (0U) //!< Bit position for ENET_RMON_T_COL_TXPKTS.
+#define BM_ENET_RMON_T_COL_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_COL_TXPKTS.
+#define BS_ENET_RMON_T_COL_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_COL_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_COL_TXPKTS field.
+#define BR_ENET_RMON_T_COL_TXPKTS(x) (HW_ENET_RMON_T_COL(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+typedef union _hw_enet_rmon_t_p64
+{
+ uint32_t U;
+ struct _hw_enet_rmon_t_p64_bitfields
+ {
+ uint32_t TXPKTS : 16; //!< [15:0] Packet count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_t_p64_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P64 register
+ */
+//@{
+#define HW_ENET_RMON_T_P64_ADDR(x) (REGS_ENET_BASE(x) + 0x228U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_P64(x) (*(__I hw_enet_rmon_t_p64_t *) HW_ENET_RMON_T_P64_ADDR(x))
+#define HW_ENET_RMON_T_P64_RD(x) (HW_ENET_RMON_T_P64(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P64 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P64, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_P64_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P64_TXPKTS.
+#define BM_ENET_RMON_T_P64_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P64_TXPKTS.
+#define BS_ENET_RMON_T_P64_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P64_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_P64_TXPKTS field.
+#define BR_ENET_RMON_T_P64_TXPKTS(x) (HW_ENET_RMON_T_P64(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_t_p65to127
+{
+ uint32_t U;
+ struct _hw_enet_rmon_t_p65to127_bitfields
+ {
+ uint32_t TXPKTS : 16; //!< [15:0] Packet count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_t_p65to127_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P65TO127 register
+ */
+//@{
+#define HW_ENET_RMON_T_P65TO127_ADDR(x) (REGS_ENET_BASE(x) + 0x22CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_P65TO127(x) (*(__I hw_enet_rmon_t_p65to127_t *) HW_ENET_RMON_T_P65TO127_ADDR(x))
+#define HW_ENET_RMON_T_P65TO127_RD(x) (HW_ENET_RMON_T_P65TO127(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P65TO127 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P65TO127, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_P65TO127_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P65TO127_TXPKTS.
+#define BM_ENET_RMON_T_P65TO127_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P65TO127_TXPKTS.
+#define BS_ENET_RMON_T_P65TO127_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P65TO127_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_P65TO127_TXPKTS field.
+#define BR_ENET_RMON_T_P65TO127_TXPKTS(x) (HW_ENET_RMON_T_P65TO127(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_t_p128to255
+{
+ uint32_t U;
+ struct _hw_enet_rmon_t_p128to255_bitfields
+ {
+ uint32_t TXPKTS : 16; //!< [15:0] Packet count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_t_p128to255_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P128TO255 register
+ */
+//@{
+#define HW_ENET_RMON_T_P128TO255_ADDR(x) (REGS_ENET_BASE(x) + 0x230U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_P128TO255(x) (*(__I hw_enet_rmon_t_p128to255_t *) HW_ENET_RMON_T_P128TO255_ADDR(x))
+#define HW_ENET_RMON_T_P128TO255_RD(x) (HW_ENET_RMON_T_P128TO255(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P128TO255 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P128TO255, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_P128TO255_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P128TO255_TXPKTS.
+#define BM_ENET_RMON_T_P128TO255_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P128TO255_TXPKTS.
+#define BS_ENET_RMON_T_P128TO255_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P128TO255_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_P128TO255_TXPKTS field.
+#define BR_ENET_RMON_T_P128TO255_TXPKTS(x) (HW_ENET_RMON_T_P128TO255(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_t_p256to511
+{
+ uint32_t U;
+ struct _hw_enet_rmon_t_p256to511_bitfields
+ {
+ uint32_t TXPKTS : 16; //!< [15:0] Packet count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_t_p256to511_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P256TO511 register
+ */
+//@{
+#define HW_ENET_RMON_T_P256TO511_ADDR(x) (REGS_ENET_BASE(x) + 0x234U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_P256TO511(x) (*(__I hw_enet_rmon_t_p256to511_t *) HW_ENET_RMON_T_P256TO511_ADDR(x))
+#define HW_ENET_RMON_T_P256TO511_RD(x) (HW_ENET_RMON_T_P256TO511(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P256TO511 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P256TO511, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_P256TO511_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P256TO511_TXPKTS.
+#define BM_ENET_RMON_T_P256TO511_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P256TO511_TXPKTS.
+#define BS_ENET_RMON_T_P256TO511_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P256TO511_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_P256TO511_TXPKTS field.
+#define BR_ENET_RMON_T_P256TO511_TXPKTS(x) (HW_ENET_RMON_T_P256TO511(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+typedef union _hw_enet_rmon_t_p512to1023
+{
+ uint32_t U;
+ struct _hw_enet_rmon_t_p512to1023_bitfields
+ {
+ uint32_t TXPKTS : 16; //!< [15:0] Packet count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_t_p512to1023_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P512TO1023 register
+ */
+//@{
+#define HW_ENET_RMON_T_P512TO1023_ADDR(x) (REGS_ENET_BASE(x) + 0x238U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_P512TO1023(x) (*(__I hw_enet_rmon_t_p512to1023_t *) HW_ENET_RMON_T_P512TO1023_ADDR(x))
+#define HW_ENET_RMON_T_P512TO1023_RD(x) (HW_ENET_RMON_T_P512TO1023(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P512TO1023 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P512TO1023, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_P512TO1023_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P512TO1023_TXPKTS.
+#define BM_ENET_RMON_T_P512TO1023_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P512TO1023_TXPKTS.
+#define BS_ENET_RMON_T_P512TO1023_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P512TO1023_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_P512TO1023_TXPKTS field.
+#define BR_ENET_RMON_T_P512TO1023_TXPKTS(x) (HW_ENET_RMON_T_P512TO1023(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_t_p1024to2047
+{
+ uint32_t U;
+ struct _hw_enet_rmon_t_p1024to2047_bitfields
+ {
+ uint32_t TXPKTS : 16; //!< [15:0] Packet count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_t_p1024to2047_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P1024TO2047 register
+ */
+//@{
+#define HW_ENET_RMON_T_P1024TO2047_ADDR(x) (REGS_ENET_BASE(x) + 0x23CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_P1024TO2047(x) (*(__I hw_enet_rmon_t_p1024to2047_t *) HW_ENET_RMON_T_P1024TO2047_ADDR(x))
+#define HW_ENET_RMON_T_P1024TO2047_RD(x) (HW_ENET_RMON_T_P1024TO2047(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P1024TO2047 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P1024TO2047, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_P1024TO2047_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P1024TO2047_TXPKTS.
+#define BM_ENET_RMON_T_P1024TO2047_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P1024TO2047_TXPKTS.
+#define BS_ENET_RMON_T_P1024TO2047_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P1024TO2047_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_P1024TO2047_TXPKTS field.
+#define BR_ENET_RMON_T_P1024TO2047_TXPKTS(x) (HW_ENET_RMON_T_P1024TO2047(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_t_p_gte2048
+{
+ uint32_t U;
+ struct _hw_enet_rmon_t_p_gte2048_bitfields
+ {
+ uint32_t TXPKTS : 16; //!< [15:0] Packet count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_t_p_gte2048_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P_GTE2048 register
+ */
+//@{
+#define HW_ENET_RMON_T_P_GTE2048_ADDR(x) (REGS_ENET_BASE(x) + 0x240U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_P_GTE2048(x) (*(__I hw_enet_rmon_t_p_gte2048_t *) HW_ENET_RMON_T_P_GTE2048_ADDR(x))
+#define HW_ENET_RMON_T_P_GTE2048_RD(x) (HW_ENET_RMON_T_P_GTE2048(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P_GTE2048 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P_GTE2048, field TXPKTS[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_P_GTE2048_TXPKTS (0U) //!< Bit position for ENET_RMON_T_P_GTE2048_TXPKTS.
+#define BM_ENET_RMON_T_P_GTE2048_TXPKTS (0x0000FFFFU) //!< Bit mask for ENET_RMON_T_P_GTE2048_TXPKTS.
+#define BS_ENET_RMON_T_P_GTE2048_TXPKTS (16U) //!< Bit field size in bits for ENET_RMON_T_P_GTE2048_TXPKTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_P_GTE2048_TXPKTS field.
+#define BR_ENET_RMON_T_P_GTE2048_TXPKTS(x) (HW_ENET_RMON_T_P_GTE2048(x).B.TXPKTS)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_t_octets
+{
+ uint32_t U;
+ struct _hw_enet_rmon_t_octets_bitfields
+ {
+ uint32_t TXOCTS : 32; //!< [31:0] Octet count
+ } B;
+} hw_enet_rmon_t_octets_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_OCTETS register
+ */
+//@{
+#define HW_ENET_RMON_T_OCTETS_ADDR(x) (REGS_ENET_BASE(x) + 0x244U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_T_OCTETS(x) (*(__I hw_enet_rmon_t_octets_t *) HW_ENET_RMON_T_OCTETS_ADDR(x))
+#define HW_ENET_RMON_T_OCTETS_RD(x) (HW_ENET_RMON_T_OCTETS(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_T_OCTETS bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_OCTETS, field TXOCTS[31:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_T_OCTETS_TXOCTS (0U) //!< Bit position for ENET_RMON_T_OCTETS_TXOCTS.
+#define BM_ENET_RMON_T_OCTETS_TXOCTS (0xFFFFFFFFU) //!< Bit mask for ENET_RMON_T_OCTETS_TXOCTS.
+#define BS_ENET_RMON_T_OCTETS_TXOCTS (32U) //!< Bit field size in bits for ENET_RMON_T_OCTETS_TXOCTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_T_OCTETS_TXOCTS field.
+#define BR_ENET_RMON_T_OCTETS_TXOCTS(x) (HW_ENET_RMON_T_OCTETS(x).U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_t_frame_ok
+{
+ uint32_t U;
+ struct _hw_enet_ieee_t_frame_ok_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Frame count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_ieee_t_frame_ok_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_FRAME_OK register
+ */
+//@{
+#define HW_ENET_IEEE_T_FRAME_OK_ADDR(x) (REGS_ENET_BASE(x) + 0x24CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_T_FRAME_OK(x) (*(__I hw_enet_ieee_t_frame_ok_t *) HW_ENET_IEEE_T_FRAME_OK_ADDR(x))
+#define HW_ENET_IEEE_T_FRAME_OK_RD(x) (HW_ENET_IEEE_T_FRAME_OK(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_FRAME_OK bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_FRAME_OK, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_T_FRAME_OK_COUNT (0U) //!< Bit position for ENET_IEEE_T_FRAME_OK_COUNT.
+#define BM_ENET_IEEE_T_FRAME_OK_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_FRAME_OK_COUNT.
+#define BS_ENET_IEEE_T_FRAME_OK_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_FRAME_OK_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_T_FRAME_OK_COUNT field.
+#define BR_ENET_IEEE_T_FRAME_OK_COUNT(x) (HW_ENET_IEEE_T_FRAME_OK(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_t_1col
+{
+ uint32_t U;
+ struct _hw_enet_ieee_t_1col_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Frame count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_ieee_t_1col_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_1COL register
+ */
+//@{
+#define HW_ENET_IEEE_T_1COL_ADDR(x) (REGS_ENET_BASE(x) + 0x250U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_T_1COL(x) (*(__I hw_enet_ieee_t_1col_t *) HW_ENET_IEEE_T_1COL_ADDR(x))
+#define HW_ENET_IEEE_T_1COL_RD(x) (HW_ENET_IEEE_T_1COL(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_1COL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_1COL, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_T_1COL_COUNT (0U) //!< Bit position for ENET_IEEE_T_1COL_COUNT.
+#define BM_ENET_IEEE_T_1COL_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_1COL_COUNT.
+#define BS_ENET_IEEE_T_1COL_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_1COL_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_T_1COL_COUNT field.
+#define BR_ENET_IEEE_T_1COL_COUNT(x) (HW_ENET_IEEE_T_1COL(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_t_mcol
+{
+ uint32_t U;
+ struct _hw_enet_ieee_t_mcol_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Frame count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_ieee_t_mcol_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_MCOL register
+ */
+//@{
+#define HW_ENET_IEEE_T_MCOL_ADDR(x) (REGS_ENET_BASE(x) + 0x254U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_T_MCOL(x) (*(__I hw_enet_ieee_t_mcol_t *) HW_ENET_IEEE_T_MCOL_ADDR(x))
+#define HW_ENET_IEEE_T_MCOL_RD(x) (HW_ENET_IEEE_T_MCOL(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_MCOL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_MCOL, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_T_MCOL_COUNT (0U) //!< Bit position for ENET_IEEE_T_MCOL_COUNT.
+#define BM_ENET_IEEE_T_MCOL_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_MCOL_COUNT.
+#define BS_ENET_IEEE_T_MCOL_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_MCOL_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_T_MCOL_COUNT field.
+#define BR_ENET_IEEE_T_MCOL_COUNT(x) (HW_ENET_IEEE_T_MCOL(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_t_def
+{
+ uint32_t U;
+ struct _hw_enet_ieee_t_def_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Frame count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_ieee_t_def_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_DEF register
+ */
+//@{
+#define HW_ENET_IEEE_T_DEF_ADDR(x) (REGS_ENET_BASE(x) + 0x258U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_T_DEF(x) (*(__I hw_enet_ieee_t_def_t *) HW_ENET_IEEE_T_DEF_ADDR(x))
+#define HW_ENET_IEEE_T_DEF_RD(x) (HW_ENET_IEEE_T_DEF(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_DEF bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_DEF, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_T_DEF_COUNT (0U) //!< Bit position for ENET_IEEE_T_DEF_COUNT.
+#define BM_ENET_IEEE_T_DEF_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_DEF_COUNT.
+#define BS_ENET_IEEE_T_DEF_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_DEF_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_T_DEF_COUNT field.
+#define BR_ENET_IEEE_T_DEF_COUNT(x) (HW_ENET_IEEE_T_DEF(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_t_lcol
+{
+ uint32_t U;
+ struct _hw_enet_ieee_t_lcol_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Frame count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_ieee_t_lcol_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_LCOL register
+ */
+//@{
+#define HW_ENET_IEEE_T_LCOL_ADDR(x) (REGS_ENET_BASE(x) + 0x25CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_T_LCOL(x) (*(__I hw_enet_ieee_t_lcol_t *) HW_ENET_IEEE_T_LCOL_ADDR(x))
+#define HW_ENET_IEEE_T_LCOL_RD(x) (HW_ENET_IEEE_T_LCOL(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_LCOL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_LCOL, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_T_LCOL_COUNT (0U) //!< Bit position for ENET_IEEE_T_LCOL_COUNT.
+#define BM_ENET_IEEE_T_LCOL_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_LCOL_COUNT.
+#define BS_ENET_IEEE_T_LCOL_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_LCOL_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_T_LCOL_COUNT field.
+#define BR_ENET_IEEE_T_LCOL_COUNT(x) (HW_ENET_IEEE_T_LCOL(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_t_excol
+{
+ uint32_t U;
+ struct _hw_enet_ieee_t_excol_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Frame count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_ieee_t_excol_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_EXCOL register
+ */
+//@{
+#define HW_ENET_IEEE_T_EXCOL_ADDR(x) (REGS_ENET_BASE(x) + 0x260U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_T_EXCOL(x) (*(__I hw_enet_ieee_t_excol_t *) HW_ENET_IEEE_T_EXCOL_ADDR(x))
+#define HW_ENET_IEEE_T_EXCOL_RD(x) (HW_ENET_IEEE_T_EXCOL(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_EXCOL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_EXCOL, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_T_EXCOL_COUNT (0U) //!< Bit position for ENET_IEEE_T_EXCOL_COUNT.
+#define BM_ENET_IEEE_T_EXCOL_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_EXCOL_COUNT.
+#define BS_ENET_IEEE_T_EXCOL_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_EXCOL_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_T_EXCOL_COUNT field.
+#define BR_ENET_IEEE_T_EXCOL_COUNT(x) (HW_ENET_IEEE_T_EXCOL(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_t_macerr
+{
+ uint32_t U;
+ struct _hw_enet_ieee_t_macerr_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Frame count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_ieee_t_macerr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_MACERR register
+ */
+//@{
+#define HW_ENET_IEEE_T_MACERR_ADDR(x) (REGS_ENET_BASE(x) + 0x264U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_T_MACERR(x) (*(__I hw_enet_ieee_t_macerr_t *) HW_ENET_IEEE_T_MACERR_ADDR(x))
+#define HW_ENET_IEEE_T_MACERR_RD(x) (HW_ENET_IEEE_T_MACERR(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_MACERR bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_MACERR, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_T_MACERR_COUNT (0U) //!< Bit position for ENET_IEEE_T_MACERR_COUNT.
+#define BM_ENET_IEEE_T_MACERR_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_MACERR_COUNT.
+#define BS_ENET_IEEE_T_MACERR_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_MACERR_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_T_MACERR_COUNT field.
+#define BR_ENET_IEEE_T_MACERR_COUNT(x) (HW_ENET_IEEE_T_MACERR(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_t_cserr
+{
+ uint32_t U;
+ struct _hw_enet_ieee_t_cserr_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Frame count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_ieee_t_cserr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_CSERR register
+ */
+//@{
+#define HW_ENET_IEEE_T_CSERR_ADDR(x) (REGS_ENET_BASE(x) + 0x268U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_T_CSERR(x) (*(__I hw_enet_ieee_t_cserr_t *) HW_ENET_IEEE_T_CSERR_ADDR(x))
+#define HW_ENET_IEEE_T_CSERR_RD(x) (HW_ENET_IEEE_T_CSERR(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_CSERR bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_CSERR, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_T_CSERR_COUNT (0U) //!< Bit position for ENET_IEEE_T_CSERR_COUNT.
+#define BM_ENET_IEEE_T_CSERR_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_CSERR_COUNT.
+#define BS_ENET_IEEE_T_CSERR_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_CSERR_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_T_CSERR_COUNT field.
+#define BR_ENET_IEEE_T_CSERR_COUNT(x) (HW_ENET_IEEE_T_CSERR(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_t_fdxfc
+{
+ uint32_t U;
+ struct _hw_enet_ieee_t_fdxfc_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Frame count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_ieee_t_fdxfc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_FDXFC register
+ */
+//@{
+#define HW_ENET_IEEE_T_FDXFC_ADDR(x) (REGS_ENET_BASE(x) + 0x270U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_T_FDXFC(x) (*(__I hw_enet_ieee_t_fdxfc_t *) HW_ENET_IEEE_T_FDXFC_ADDR(x))
+#define HW_ENET_IEEE_T_FDXFC_RD(x) (HW_ENET_IEEE_T_FDXFC(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_FDXFC bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_FDXFC, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_T_FDXFC_COUNT (0U) //!< Bit position for ENET_IEEE_T_FDXFC_COUNT.
+#define BM_ENET_IEEE_T_FDXFC_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_T_FDXFC_COUNT.
+#define BS_ENET_IEEE_T_FDXFC_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_T_FDXFC_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_T_FDXFC_COUNT field.
+#define BR_ENET_IEEE_T_FDXFC_COUNT(x) (HW_ENET_IEEE_T_FDXFC(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Counts total octets (includes header and FCS fields).
+ */
+typedef union _hw_enet_ieee_t_octets_ok
+{
+ uint32_t U;
+ struct _hw_enet_ieee_t_octets_ok_bitfields
+ {
+ uint32_t COUNT : 32; //!< [31:0] Octet count
+ } B;
+} hw_enet_ieee_t_octets_ok_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_OCTETS_OK register
+ */
+//@{
+#define HW_ENET_IEEE_T_OCTETS_OK_ADDR(x) (REGS_ENET_BASE(x) + 0x274U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_T_OCTETS_OK(x) (*(__I hw_enet_ieee_t_octets_ok_t *) HW_ENET_IEEE_T_OCTETS_OK_ADDR(x))
+#define HW_ENET_IEEE_T_OCTETS_OK_RD(x) (HW_ENET_IEEE_T_OCTETS_OK(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_OCTETS_OK bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_OCTETS_OK, field COUNT[31:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_T_OCTETS_OK_COUNT (0U) //!< Bit position for ENET_IEEE_T_OCTETS_OK_COUNT.
+#define BM_ENET_IEEE_T_OCTETS_OK_COUNT (0xFFFFFFFFU) //!< Bit mask for ENET_IEEE_T_OCTETS_OK_COUNT.
+#define BS_ENET_IEEE_T_OCTETS_OK_COUNT (32U) //!< Bit field size in bits for ENET_IEEE_T_OCTETS_OK_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_T_OCTETS_OK_COUNT field.
+#define BR_ENET_IEEE_T_OCTETS_OK_COUNT(x) (HW_ENET_IEEE_T_OCTETS_OK(x).U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_packets
+{
+ uint32_t U;
+ struct _hw_enet_rmon_r_packets_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Packet count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_r_packets_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_PACKETS register
+ */
+//@{
+#define HW_ENET_RMON_R_PACKETS_ADDR(x) (REGS_ENET_BASE(x) + 0x284U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_PACKETS(x) (*(__I hw_enet_rmon_r_packets_t *) HW_ENET_RMON_R_PACKETS_ADDR(x))
+#define HW_ENET_RMON_R_PACKETS_RD(x) (HW_ENET_RMON_R_PACKETS(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_PACKETS bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_PACKETS, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_PACKETS_COUNT (0U) //!< Bit position for ENET_RMON_R_PACKETS_COUNT.
+#define BM_ENET_RMON_R_PACKETS_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_PACKETS_COUNT.
+#define BS_ENET_RMON_R_PACKETS_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_PACKETS_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_PACKETS_COUNT field.
+#define BR_ENET_RMON_R_PACKETS_COUNT(x) (HW_ENET_RMON_R_PACKETS(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_bc_pkt
+{
+ uint32_t U;
+ struct _hw_enet_rmon_r_bc_pkt_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Packet count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_r_bc_pkt_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_BC_PKT register
+ */
+//@{
+#define HW_ENET_RMON_R_BC_PKT_ADDR(x) (REGS_ENET_BASE(x) + 0x288U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_BC_PKT(x) (*(__I hw_enet_rmon_r_bc_pkt_t *) HW_ENET_RMON_R_BC_PKT_ADDR(x))
+#define HW_ENET_RMON_R_BC_PKT_RD(x) (HW_ENET_RMON_R_BC_PKT(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_BC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_BC_PKT, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_BC_PKT_COUNT (0U) //!< Bit position for ENET_RMON_R_BC_PKT_COUNT.
+#define BM_ENET_RMON_R_BC_PKT_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_BC_PKT_COUNT.
+#define BS_ENET_RMON_R_BC_PKT_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_BC_PKT_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_BC_PKT_COUNT field.
+#define BR_ENET_RMON_R_BC_PKT_COUNT(x) (HW_ENET_RMON_R_BC_PKT(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_mc_pkt
+{
+ uint32_t U;
+ struct _hw_enet_rmon_r_mc_pkt_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Packet count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_r_mc_pkt_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_MC_PKT register
+ */
+//@{
+#define HW_ENET_RMON_R_MC_PKT_ADDR(x) (REGS_ENET_BASE(x) + 0x28CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_MC_PKT(x) (*(__I hw_enet_rmon_r_mc_pkt_t *) HW_ENET_RMON_R_MC_PKT_ADDR(x))
+#define HW_ENET_RMON_R_MC_PKT_RD(x) (HW_ENET_RMON_R_MC_PKT(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_MC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_MC_PKT, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_MC_PKT_COUNT (0U) //!< Bit position for ENET_RMON_R_MC_PKT_COUNT.
+#define BM_ENET_RMON_R_MC_PKT_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_MC_PKT_COUNT.
+#define BS_ENET_RMON_R_MC_PKT_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_MC_PKT_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_MC_PKT_COUNT field.
+#define BR_ENET_RMON_R_MC_PKT_COUNT(x) (HW_ENET_RMON_R_MC_PKT(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_crc_align
+{
+ uint32_t U;
+ struct _hw_enet_rmon_r_crc_align_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Packet count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_r_crc_align_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_CRC_ALIGN register
+ */
+//@{
+#define HW_ENET_RMON_R_CRC_ALIGN_ADDR(x) (REGS_ENET_BASE(x) + 0x290U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_CRC_ALIGN(x) (*(__I hw_enet_rmon_r_crc_align_t *) HW_ENET_RMON_R_CRC_ALIGN_ADDR(x))
+#define HW_ENET_RMON_R_CRC_ALIGN_RD(x) (HW_ENET_RMON_R_CRC_ALIGN(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_CRC_ALIGN bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_CRC_ALIGN, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_CRC_ALIGN_COUNT (0U) //!< Bit position for ENET_RMON_R_CRC_ALIGN_COUNT.
+#define BM_ENET_RMON_R_CRC_ALIGN_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_CRC_ALIGN_COUNT.
+#define BS_ENET_RMON_R_CRC_ALIGN_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_CRC_ALIGN_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_CRC_ALIGN_COUNT field.
+#define BR_ENET_RMON_R_CRC_ALIGN_COUNT(x) (HW_ENET_RMON_R_CRC_ALIGN(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_undersize
+{
+ uint32_t U;
+ struct _hw_enet_rmon_r_undersize_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Packet count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_r_undersize_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_UNDERSIZE register
+ */
+//@{
+#define HW_ENET_RMON_R_UNDERSIZE_ADDR(x) (REGS_ENET_BASE(x) + 0x294U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_UNDERSIZE(x) (*(__I hw_enet_rmon_r_undersize_t *) HW_ENET_RMON_R_UNDERSIZE_ADDR(x))
+#define HW_ENET_RMON_R_UNDERSIZE_RD(x) (HW_ENET_RMON_R_UNDERSIZE(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_UNDERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_UNDERSIZE, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_UNDERSIZE_COUNT (0U) //!< Bit position for ENET_RMON_R_UNDERSIZE_COUNT.
+#define BM_ENET_RMON_R_UNDERSIZE_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_UNDERSIZE_COUNT.
+#define BS_ENET_RMON_R_UNDERSIZE_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_UNDERSIZE_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_UNDERSIZE_COUNT field.
+#define BR_ENET_RMON_R_UNDERSIZE_COUNT(x) (HW_ENET_RMON_R_UNDERSIZE(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_oversize
+{
+ uint32_t U;
+ struct _hw_enet_rmon_r_oversize_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Packet count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_r_oversize_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_OVERSIZE register
+ */
+//@{
+#define HW_ENET_RMON_R_OVERSIZE_ADDR(x) (REGS_ENET_BASE(x) + 0x298U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_OVERSIZE(x) (*(__I hw_enet_rmon_r_oversize_t *) HW_ENET_RMON_R_OVERSIZE_ADDR(x))
+#define HW_ENET_RMON_R_OVERSIZE_RD(x) (HW_ENET_RMON_R_OVERSIZE(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_OVERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_OVERSIZE, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_OVERSIZE_COUNT (0U) //!< Bit position for ENET_RMON_R_OVERSIZE_COUNT.
+#define BM_ENET_RMON_R_OVERSIZE_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_OVERSIZE_COUNT.
+#define BS_ENET_RMON_R_OVERSIZE_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_OVERSIZE_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_OVERSIZE_COUNT field.
+#define BR_ENET_RMON_R_OVERSIZE_COUNT(x) (HW_ENET_RMON_R_OVERSIZE(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_frag
+{
+ uint32_t U;
+ struct _hw_enet_rmon_r_frag_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Packet count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_r_frag_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_FRAG register
+ */
+//@{
+#define HW_ENET_RMON_R_FRAG_ADDR(x) (REGS_ENET_BASE(x) + 0x29CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_FRAG(x) (*(__I hw_enet_rmon_r_frag_t *) HW_ENET_RMON_R_FRAG_ADDR(x))
+#define HW_ENET_RMON_R_FRAG_RD(x) (HW_ENET_RMON_R_FRAG(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_FRAG bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_FRAG, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_FRAG_COUNT (0U) //!< Bit position for ENET_RMON_R_FRAG_COUNT.
+#define BM_ENET_RMON_R_FRAG_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_FRAG_COUNT.
+#define BS_ENET_RMON_R_FRAG_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_FRAG_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_FRAG_COUNT field.
+#define BR_ENET_RMON_R_FRAG_COUNT(x) (HW_ENET_RMON_R_FRAG(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_jab
+{
+ uint32_t U;
+ struct _hw_enet_rmon_r_jab_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Packet count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_r_jab_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_JAB register
+ */
+//@{
+#define HW_ENET_RMON_R_JAB_ADDR(x) (REGS_ENET_BASE(x) + 0x2A0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_JAB(x) (*(__I hw_enet_rmon_r_jab_t *) HW_ENET_RMON_R_JAB_ADDR(x))
+#define HW_ENET_RMON_R_JAB_RD(x) (HW_ENET_RMON_R_JAB(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_JAB bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_JAB, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_JAB_COUNT (0U) //!< Bit position for ENET_RMON_R_JAB_COUNT.
+#define BM_ENET_RMON_R_JAB_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_JAB_COUNT.
+#define BS_ENET_RMON_R_JAB_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_JAB_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_JAB_COUNT field.
+#define BR_ENET_RMON_R_JAB_COUNT(x) (HW_ENET_RMON_R_JAB(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_p64
+{
+ uint32_t U;
+ struct _hw_enet_rmon_r_p64_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Packet count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_r_p64_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P64 register
+ */
+//@{
+#define HW_ENET_RMON_R_P64_ADDR(x) (REGS_ENET_BASE(x) + 0x2A8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_P64(x) (*(__I hw_enet_rmon_r_p64_t *) HW_ENET_RMON_R_P64_ADDR(x))
+#define HW_ENET_RMON_R_P64_RD(x) (HW_ENET_RMON_R_P64(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P64 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P64, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_P64_COUNT (0U) //!< Bit position for ENET_RMON_R_P64_COUNT.
+#define BM_ENET_RMON_R_P64_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P64_COUNT.
+#define BS_ENET_RMON_R_P64_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_P64_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_P64_COUNT field.
+#define BR_ENET_RMON_R_P64_COUNT(x) (HW_ENET_RMON_R_P64(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_p65to127
+{
+ uint32_t U;
+ struct _hw_enet_rmon_r_p65to127_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Packet count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_r_p65to127_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P65TO127 register
+ */
+//@{
+#define HW_ENET_RMON_R_P65TO127_ADDR(x) (REGS_ENET_BASE(x) + 0x2ACU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_P65TO127(x) (*(__I hw_enet_rmon_r_p65to127_t *) HW_ENET_RMON_R_P65TO127_ADDR(x))
+#define HW_ENET_RMON_R_P65TO127_RD(x) (HW_ENET_RMON_R_P65TO127(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P65TO127 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P65TO127, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_P65TO127_COUNT (0U) //!< Bit position for ENET_RMON_R_P65TO127_COUNT.
+#define BM_ENET_RMON_R_P65TO127_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P65TO127_COUNT.
+#define BS_ENET_RMON_R_P65TO127_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_P65TO127_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_P65TO127_COUNT field.
+#define BR_ENET_RMON_R_P65TO127_COUNT(x) (HW_ENET_RMON_R_P65TO127(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_p128to255
+{
+ uint32_t U;
+ struct _hw_enet_rmon_r_p128to255_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Packet count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_r_p128to255_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P128TO255 register
+ */
+//@{
+#define HW_ENET_RMON_R_P128TO255_ADDR(x) (REGS_ENET_BASE(x) + 0x2B0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_P128TO255(x) (*(__I hw_enet_rmon_r_p128to255_t *) HW_ENET_RMON_R_P128TO255_ADDR(x))
+#define HW_ENET_RMON_R_P128TO255_RD(x) (HW_ENET_RMON_R_P128TO255(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P128TO255 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P128TO255, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_P128TO255_COUNT (0U) //!< Bit position for ENET_RMON_R_P128TO255_COUNT.
+#define BM_ENET_RMON_R_P128TO255_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P128TO255_COUNT.
+#define BS_ENET_RMON_R_P128TO255_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_P128TO255_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_P128TO255_COUNT field.
+#define BR_ENET_RMON_R_P128TO255_COUNT(x) (HW_ENET_RMON_R_P128TO255(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_p256to511
+{
+ uint32_t U;
+ struct _hw_enet_rmon_r_p256to511_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Packet count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_r_p256to511_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P256TO511 register
+ */
+//@{
+#define HW_ENET_RMON_R_P256TO511_ADDR(x) (REGS_ENET_BASE(x) + 0x2B4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_P256TO511(x) (*(__I hw_enet_rmon_r_p256to511_t *) HW_ENET_RMON_R_P256TO511_ADDR(x))
+#define HW_ENET_RMON_R_P256TO511_RD(x) (HW_ENET_RMON_R_P256TO511(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P256TO511 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P256TO511, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_P256TO511_COUNT (0U) //!< Bit position for ENET_RMON_R_P256TO511_COUNT.
+#define BM_ENET_RMON_R_P256TO511_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P256TO511_COUNT.
+#define BS_ENET_RMON_R_P256TO511_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_P256TO511_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_P256TO511_COUNT field.
+#define BR_ENET_RMON_R_P256TO511_COUNT(x) (HW_ENET_RMON_R_P256TO511(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_p512to1023
+{
+ uint32_t U;
+ struct _hw_enet_rmon_r_p512to1023_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Packet count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_r_p512to1023_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P512TO1023 register
+ */
+//@{
+#define HW_ENET_RMON_R_P512TO1023_ADDR(x) (REGS_ENET_BASE(x) + 0x2B8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_P512TO1023(x) (*(__I hw_enet_rmon_r_p512to1023_t *) HW_ENET_RMON_R_P512TO1023_ADDR(x))
+#define HW_ENET_RMON_R_P512TO1023_RD(x) (HW_ENET_RMON_R_P512TO1023(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P512TO1023 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P512TO1023, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_P512TO1023_COUNT (0U) //!< Bit position for ENET_RMON_R_P512TO1023_COUNT.
+#define BM_ENET_RMON_R_P512TO1023_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P512TO1023_COUNT.
+#define BS_ENET_RMON_R_P512TO1023_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_P512TO1023_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_P512TO1023_COUNT field.
+#define BR_ENET_RMON_R_P512TO1023_COUNT(x) (HW_ENET_RMON_R_P512TO1023(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_p1024to2047
+{
+ uint32_t U;
+ struct _hw_enet_rmon_r_p1024to2047_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Packet count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_r_p1024to2047_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P1024TO2047 register
+ */
+//@{
+#define HW_ENET_RMON_R_P1024TO2047_ADDR(x) (REGS_ENET_BASE(x) + 0x2BCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_P1024TO2047(x) (*(__I hw_enet_rmon_r_p1024to2047_t *) HW_ENET_RMON_R_P1024TO2047_ADDR(x))
+#define HW_ENET_RMON_R_P1024TO2047_RD(x) (HW_ENET_RMON_R_P1024TO2047(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P1024TO2047 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P1024TO2047, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_P1024TO2047_COUNT (0U) //!< Bit position for ENET_RMON_R_P1024TO2047_COUNT.
+#define BM_ENET_RMON_R_P1024TO2047_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_P1024TO2047_COUNT.
+#define BS_ENET_RMON_R_P1024TO2047_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_P1024TO2047_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_P1024TO2047_COUNT field.
+#define BR_ENET_RMON_R_P1024TO2047_COUNT(x) (HW_ENET_RMON_R_P1024TO2047(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_gte2048
+{
+ uint32_t U;
+ struct _hw_enet_rmon_r_gte2048_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Packet count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_rmon_r_gte2048_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_GTE2048 register
+ */
+//@{
+#define HW_ENET_RMON_R_GTE2048_ADDR(x) (REGS_ENET_BASE(x) + 0x2C0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_GTE2048(x) (*(__I hw_enet_rmon_r_gte2048_t *) HW_ENET_RMON_R_GTE2048_ADDR(x))
+#define HW_ENET_RMON_R_GTE2048_RD(x) (HW_ENET_RMON_R_GTE2048(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_GTE2048 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_GTE2048, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_GTE2048_COUNT (0U) //!< Bit position for ENET_RMON_R_GTE2048_COUNT.
+#define BM_ENET_RMON_R_GTE2048_COUNT (0x0000FFFFU) //!< Bit mask for ENET_RMON_R_GTE2048_COUNT.
+#define BS_ENET_RMON_R_GTE2048_COUNT (16U) //!< Bit field size in bits for ENET_RMON_R_GTE2048_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_GTE2048_COUNT field.
+#define BR_ENET_RMON_R_GTE2048_COUNT(x) (HW_ENET_RMON_R_GTE2048(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_rmon_r_octets
+{
+ uint32_t U;
+ struct _hw_enet_rmon_r_octets_bitfields
+ {
+ uint32_t COUNT : 32; //!< [31:0] Octet count
+ } B;
+} hw_enet_rmon_r_octets_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_OCTETS register
+ */
+//@{
+#define HW_ENET_RMON_R_OCTETS_ADDR(x) (REGS_ENET_BASE(x) + 0x2C4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_RMON_R_OCTETS(x) (*(__I hw_enet_rmon_r_octets_t *) HW_ENET_RMON_R_OCTETS_ADDR(x))
+#define HW_ENET_RMON_R_OCTETS_RD(x) (HW_ENET_RMON_R_OCTETS(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_RMON_R_OCTETS bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_OCTETS, field COUNT[31:0] (RO)
+ */
+//@{
+#define BP_ENET_RMON_R_OCTETS_COUNT (0U) //!< Bit position for ENET_RMON_R_OCTETS_COUNT.
+#define BM_ENET_RMON_R_OCTETS_COUNT (0xFFFFFFFFU) //!< Bit mask for ENET_RMON_R_OCTETS_COUNT.
+#define BS_ENET_RMON_R_OCTETS_COUNT (32U) //!< Bit field size in bits for ENET_RMON_R_OCTETS_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_RMON_R_OCTETS_COUNT field.
+#define BR_ENET_RMON_R_OCTETS_COUNT(x) (HW_ENET_RMON_R_OCTETS(x).U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Counter increments if a frame with invalid or missing SFD character is
+ * detected and has been dropped. None of the other counters increments if this counter
+ * increments.
+ */
+typedef union _hw_enet_ieee_r_drop
+{
+ uint32_t U;
+ struct _hw_enet_ieee_r_drop_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Frame count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_ieee_r_drop_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_DROP register
+ */
+//@{
+#define HW_ENET_IEEE_R_DROP_ADDR(x) (REGS_ENET_BASE(x) + 0x2C8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_R_DROP(x) (*(__I hw_enet_ieee_r_drop_t *) HW_ENET_IEEE_R_DROP_ADDR(x))
+#define HW_ENET_IEEE_R_DROP_RD(x) (HW_ENET_IEEE_R_DROP(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_DROP bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_DROP, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_R_DROP_COUNT (0U) //!< Bit position for ENET_IEEE_R_DROP_COUNT.
+#define BM_ENET_IEEE_R_DROP_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_DROP_COUNT.
+#define BS_ENET_IEEE_R_DROP_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_R_DROP_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_R_DROP_COUNT field.
+#define BR_ENET_IEEE_R_DROP_COUNT(x) (HW_ENET_IEEE_R_DROP(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_r_frame_ok
+{
+ uint32_t U;
+ struct _hw_enet_ieee_r_frame_ok_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Frame count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_ieee_r_frame_ok_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_FRAME_OK register
+ */
+//@{
+#define HW_ENET_IEEE_R_FRAME_OK_ADDR(x) (REGS_ENET_BASE(x) + 0x2CCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_R_FRAME_OK(x) (*(__I hw_enet_ieee_r_frame_ok_t *) HW_ENET_IEEE_R_FRAME_OK_ADDR(x))
+#define HW_ENET_IEEE_R_FRAME_OK_RD(x) (HW_ENET_IEEE_R_FRAME_OK(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_FRAME_OK bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_FRAME_OK, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_R_FRAME_OK_COUNT (0U) //!< Bit position for ENET_IEEE_R_FRAME_OK_COUNT.
+#define BM_ENET_IEEE_R_FRAME_OK_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_FRAME_OK_COUNT.
+#define BS_ENET_IEEE_R_FRAME_OK_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_R_FRAME_OK_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_R_FRAME_OK_COUNT field.
+#define BR_ENET_IEEE_R_FRAME_OK_COUNT(x) (HW_ENET_IEEE_R_FRAME_OK(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_r_crc
+{
+ uint32_t U;
+ struct _hw_enet_ieee_r_crc_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Frame count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_ieee_r_crc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_CRC register
+ */
+//@{
+#define HW_ENET_IEEE_R_CRC_ADDR(x) (REGS_ENET_BASE(x) + 0x2D0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_R_CRC(x) (*(__I hw_enet_ieee_r_crc_t *) HW_ENET_IEEE_R_CRC_ADDR(x))
+#define HW_ENET_IEEE_R_CRC_RD(x) (HW_ENET_IEEE_R_CRC(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_CRC bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_CRC, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_R_CRC_COUNT (0U) //!< Bit position for ENET_IEEE_R_CRC_COUNT.
+#define BM_ENET_IEEE_R_CRC_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_CRC_COUNT.
+#define BS_ENET_IEEE_R_CRC_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_R_CRC_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_R_CRC_COUNT field.
+#define BR_ENET_IEEE_R_CRC_COUNT(x) (HW_ENET_IEEE_R_CRC(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_r_align
+{
+ uint32_t U;
+ struct _hw_enet_ieee_r_align_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Frame count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_ieee_r_align_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_ALIGN register
+ */
+//@{
+#define HW_ENET_IEEE_R_ALIGN_ADDR(x) (REGS_ENET_BASE(x) + 0x2D4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_R_ALIGN(x) (*(__I hw_enet_ieee_r_align_t *) HW_ENET_IEEE_R_ALIGN_ADDR(x))
+#define HW_ENET_IEEE_R_ALIGN_RD(x) (HW_ENET_IEEE_R_ALIGN(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_ALIGN bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_ALIGN, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_R_ALIGN_COUNT (0U) //!< Bit position for ENET_IEEE_R_ALIGN_COUNT.
+#define BM_ENET_IEEE_R_ALIGN_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_ALIGN_COUNT.
+#define BS_ENET_IEEE_R_ALIGN_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_R_ALIGN_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_R_ALIGN_COUNT field.
+#define BR_ENET_IEEE_R_ALIGN_COUNT(x) (HW_ENET_IEEE_R_ALIGN(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_r_macerr
+{
+ uint32_t U;
+ struct _hw_enet_ieee_r_macerr_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_ieee_r_macerr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_MACERR register
+ */
+//@{
+#define HW_ENET_IEEE_R_MACERR_ADDR(x) (REGS_ENET_BASE(x) + 0x2D8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_R_MACERR(x) (*(__I hw_enet_ieee_r_macerr_t *) HW_ENET_IEEE_R_MACERR_ADDR(x))
+#define HW_ENET_IEEE_R_MACERR_RD(x) (HW_ENET_IEEE_R_MACERR(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_MACERR bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_MACERR, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_R_MACERR_COUNT (0U) //!< Bit position for ENET_IEEE_R_MACERR_COUNT.
+#define BM_ENET_IEEE_R_MACERR_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_MACERR_COUNT.
+#define BS_ENET_IEEE_R_MACERR_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_R_MACERR_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_R_MACERR_COUNT field.
+#define BR_ENET_IEEE_R_MACERR_COUNT(x) (HW_ENET_IEEE_R_MACERR(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_r_fdxfc
+{
+ uint32_t U;
+ struct _hw_enet_ieee_r_fdxfc_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Pause frame count
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_enet_ieee_r_fdxfc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_FDXFC register
+ */
+//@{
+#define HW_ENET_IEEE_R_FDXFC_ADDR(x) (REGS_ENET_BASE(x) + 0x2DCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_R_FDXFC(x) (*(__I hw_enet_ieee_r_fdxfc_t *) HW_ENET_IEEE_R_FDXFC_ADDR(x))
+#define HW_ENET_IEEE_R_FDXFC_RD(x) (HW_ENET_IEEE_R_FDXFC(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_FDXFC bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_FDXFC, field COUNT[15:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_R_FDXFC_COUNT (0U) //!< Bit position for ENET_IEEE_R_FDXFC_COUNT.
+#define BM_ENET_IEEE_R_FDXFC_COUNT (0x0000FFFFU) //!< Bit mask for ENET_IEEE_R_FDXFC_COUNT.
+#define BS_ENET_IEEE_R_FDXFC_COUNT (16U) //!< Bit field size in bits for ENET_IEEE_R_FDXFC_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_R_FDXFC_COUNT field.
+#define BR_ENET_IEEE_R_FDXFC_COUNT(x) (HW_ENET_IEEE_R_FDXFC(x).B.COUNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_ieee_r_octets_ok
+{
+ uint32_t U;
+ struct _hw_enet_ieee_r_octets_ok_bitfields
+ {
+ uint32_t COUNT : 32; //!< [31:0] Octet count
+ } B;
+} hw_enet_ieee_r_octets_ok_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_OCTETS_OK register
+ */
+//@{
+#define HW_ENET_IEEE_R_OCTETS_OK_ADDR(x) (REGS_ENET_BASE(x) + 0x2E0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_IEEE_R_OCTETS_OK(x) (*(__I hw_enet_ieee_r_octets_ok_t *) HW_ENET_IEEE_R_OCTETS_OK_ADDR(x))
+#define HW_ENET_IEEE_R_OCTETS_OK_RD(x) (HW_ENET_IEEE_R_OCTETS_OK(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_OCTETS_OK bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_OCTETS_OK, field COUNT[31:0] (RO)
+ */
+//@{
+#define BP_ENET_IEEE_R_OCTETS_OK_COUNT (0U) //!< Bit position for ENET_IEEE_R_OCTETS_OK_COUNT.
+#define BM_ENET_IEEE_R_OCTETS_OK_COUNT (0xFFFFFFFFU) //!< Bit mask for ENET_IEEE_R_OCTETS_OK_COUNT.
+#define BS_ENET_IEEE_R_OCTETS_OK_COUNT (32U) //!< Bit field size in bits for ENET_IEEE_R_OCTETS_OK_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_IEEE_R_OCTETS_OK_COUNT field.
+#define BR_ENET_IEEE_R_OCTETS_OK_COUNT(x) (HW_ENET_IEEE_R_OCTETS_OK(x).U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_ATCR - Adjustable Timer Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_ATCR - Adjustable Timer Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * ATCR command fields can trigger the corresponding events directly. It is not
+ * necessary to preserve any of the configuration fields when a command field is
+ * set in the register, that is, no read-modify-write is required. The fields are
+ * automatically cleared after the command completes.
+ */
+typedef union _hw_enet_atcr
+{
+ uint32_t U;
+ struct _hw_enet_atcr_bitfields
+ {
+ uint32_t EN : 1; //!< [0] Enable Timer
+ uint32_t RESERVED0 : 1; //!< [1]
+ uint32_t OFFEN : 1; //!< [2] Enable One-Shot Offset Event
+ uint32_t OFFRST : 1; //!< [3] Reset Timer On Offset Event
+ uint32_t PEREN : 1; //!< [4] Enable Periodical Event
+ uint32_t RESERVED1 : 2; //!< [6:5]
+ uint32_t PINPER : 1; //!< [7]
+ uint32_t RESERVED2 : 1; //!< [8]
+ uint32_t RESTART : 1; //!< [9] Reset Timer
+ uint32_t RESERVED3 : 1; //!< [10]
+ uint32_t CAPTURE : 1; //!< [11] Capture Timer Value
+ uint32_t RESERVED4 : 1; //!< [12]
+ uint32_t SLAVE : 1; //!< [13] Enable Timer Slave Mode
+ uint32_t RESERVED5 : 18; //!< [31:14]
+ } B;
+} hw_enet_atcr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_ATCR register
+ */
+//@{
+#define HW_ENET_ATCR_ADDR(x) (REGS_ENET_BASE(x) + 0x400U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_ATCR(x) (*(__IO hw_enet_atcr_t *) HW_ENET_ATCR_ADDR(x))
+#define HW_ENET_ATCR_RD(x) (HW_ENET_ATCR(x).U)
+#define HW_ENET_ATCR_WR(x, v) (HW_ENET_ATCR(x).U = (v))
+#define HW_ENET_ATCR_SET(x, v) (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) | (v)))
+#define HW_ENET_ATCR_CLR(x, v) (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) & ~(v)))
+#define HW_ENET_ATCR_TOG(x, v) (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_ATCR bitfields
+ */
+
+/*!
+ * @name Register ENET_ATCR, field EN[0] (RW)
+ *
+ * Values:
+ * - 0 - The timer stops at the current value.
+ * - 1 - The timer starts incrementing.
+ */
+//@{
+#define BP_ENET_ATCR_EN (0U) //!< Bit position for ENET_ATCR_EN.
+#define BM_ENET_ATCR_EN (0x00000001U) //!< Bit mask for ENET_ATCR_EN.
+#define BS_ENET_ATCR_EN (1U) //!< Bit field size in bits for ENET_ATCR_EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATCR_EN field.
+#define BR_ENET_ATCR_EN(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_EN))
+#endif
+
+//! @brief Format value for bitfield ENET_ATCR_EN.
+#define BF_ENET_ATCR_EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_EN), uint32_t) & BM_ENET_ATCR_EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EN field to a new value.
+#define BW_ENET_ATCR_EN(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ATCR, field OFFEN[2] (RW)
+ *
+ * Values:
+ * - 0 - Disable.
+ * - 1 - The timer can be reset to zero when the given offset time is reached
+ * (offset event). The field is cleared when the offset event is reached, so no
+ * further event occurs until the field is set again. The timer offset value
+ * must be set before setting this field.
+ */
+//@{
+#define BP_ENET_ATCR_OFFEN (2U) //!< Bit position for ENET_ATCR_OFFEN.
+#define BM_ENET_ATCR_OFFEN (0x00000004U) //!< Bit mask for ENET_ATCR_OFFEN.
+#define BS_ENET_ATCR_OFFEN (1U) //!< Bit field size in bits for ENET_ATCR_OFFEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATCR_OFFEN field.
+#define BR_ENET_ATCR_OFFEN(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFEN))
+#endif
+
+//! @brief Format value for bitfield ENET_ATCR_OFFEN.
+#define BF_ENET_ATCR_OFFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_OFFEN), uint32_t) & BM_ENET_ATCR_OFFEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OFFEN field to a new value.
+#define BW_ENET_ATCR_OFFEN(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ATCR, field OFFRST[3] (RW)
+ *
+ * Values:
+ * - 0 - The timer is not affected and no action occurs, besides clearing OFFEN,
+ * when the offset is reached.
+ * - 1 - If OFFEN is set, the timer resets to zero when the offset setting is
+ * reached. The offset event does not cause a timer interrupt.
+ */
+//@{
+#define BP_ENET_ATCR_OFFRST (3U) //!< Bit position for ENET_ATCR_OFFRST.
+#define BM_ENET_ATCR_OFFRST (0x00000008U) //!< Bit mask for ENET_ATCR_OFFRST.
+#define BS_ENET_ATCR_OFFRST (1U) //!< Bit field size in bits for ENET_ATCR_OFFRST.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATCR_OFFRST field.
+#define BR_ENET_ATCR_OFFRST(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFRST))
+#endif
+
+//! @brief Format value for bitfield ENET_ATCR_OFFRST.
+#define BF_ENET_ATCR_OFFRST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_OFFRST), uint32_t) & BM_ENET_ATCR_OFFRST)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OFFRST field to a new value.
+#define BW_ENET_ATCR_OFFRST(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFRST) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ATCR, field PEREN[4] (RW)
+ *
+ * Values:
+ * - 0 - Disable.
+ * - 1 - A period event interrupt can be generated (EIR[TS_TIMER]) and the event
+ * signal output is asserted when the timer wraps around according to the
+ * periodic setting ATPER. The timer period value must be set before setting
+ * this bit. Not all devices contain the event signal output. See the chip
+ * configuration details.
+ */
+//@{
+#define BP_ENET_ATCR_PEREN (4U) //!< Bit position for ENET_ATCR_PEREN.
+#define BM_ENET_ATCR_PEREN (0x00000010U) //!< Bit mask for ENET_ATCR_PEREN.
+#define BS_ENET_ATCR_PEREN (1U) //!< Bit field size in bits for ENET_ATCR_PEREN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATCR_PEREN field.
+#define BR_ENET_ATCR_PEREN(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PEREN))
+#endif
+
+//! @brief Format value for bitfield ENET_ATCR_PEREN.
+#define BF_ENET_ATCR_PEREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_PEREN), uint32_t) & BM_ENET_ATCR_PEREN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PEREN field to a new value.
+#define BW_ENET_ATCR_PEREN(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PEREN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ATCR, field PINPER[7] (RW)
+ *
+ * Enables event signal output assertion on period event. Not all devices
+ * contain the event signal output. See the chip configuration details.
+ *
+ * Values:
+ * - 0 - Disable.
+ * - 1 - Enable.
+ */
+//@{
+#define BP_ENET_ATCR_PINPER (7U) //!< Bit position for ENET_ATCR_PINPER.
+#define BM_ENET_ATCR_PINPER (0x00000080U) //!< Bit mask for ENET_ATCR_PINPER.
+#define BS_ENET_ATCR_PINPER (1U) //!< Bit field size in bits for ENET_ATCR_PINPER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATCR_PINPER field.
+#define BR_ENET_ATCR_PINPER(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PINPER))
+#endif
+
+//! @brief Format value for bitfield ENET_ATCR_PINPER.
+#define BF_ENET_ATCR_PINPER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_PINPER), uint32_t) & BM_ENET_ATCR_PINPER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PINPER field to a new value.
+#define BW_ENET_ATCR_PINPER(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PINPER) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ATCR, field RESTART[9] (RW)
+ *
+ * Resets the timer to zero. This has no effect on the counter enable. If the
+ * counter is enabled when this field is set, the timer is reset to zero and starts
+ * counting from there. When set, all other fields are ignored during a write.
+ */
+//@{
+#define BP_ENET_ATCR_RESTART (9U) //!< Bit position for ENET_ATCR_RESTART.
+#define BM_ENET_ATCR_RESTART (0x00000200U) //!< Bit mask for ENET_ATCR_RESTART.
+#define BS_ENET_ATCR_RESTART (1U) //!< Bit field size in bits for ENET_ATCR_RESTART.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATCR_RESTART field.
+#define BR_ENET_ATCR_RESTART(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_RESTART))
+#endif
+
+//! @brief Format value for bitfield ENET_ATCR_RESTART.
+#define BF_ENET_ATCR_RESTART(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_RESTART), uint32_t) & BM_ENET_ATCR_RESTART)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RESTART field to a new value.
+#define BW_ENET_ATCR_RESTART(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_RESTART) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ATCR, field CAPTURE[11] (RW)
+ *
+ * Values:
+ * - 0 - No effect.
+ * - 1 - The current time is captured and can be read from the ATVR register.
+ */
+//@{
+#define BP_ENET_ATCR_CAPTURE (11U) //!< Bit position for ENET_ATCR_CAPTURE.
+#define BM_ENET_ATCR_CAPTURE (0x00000800U) //!< Bit mask for ENET_ATCR_CAPTURE.
+#define BS_ENET_ATCR_CAPTURE (1U) //!< Bit field size in bits for ENET_ATCR_CAPTURE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATCR_CAPTURE field.
+#define BR_ENET_ATCR_CAPTURE(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_CAPTURE))
+#endif
+
+//! @brief Format value for bitfield ENET_ATCR_CAPTURE.
+#define BF_ENET_ATCR_CAPTURE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_CAPTURE), uint32_t) & BM_ENET_ATCR_CAPTURE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CAPTURE field to a new value.
+#define BW_ENET_ATCR_CAPTURE(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_CAPTURE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ATCR, field SLAVE[13] (RW)
+ *
+ * Values:
+ * - 0 - The timer is active and all configuration fields in this register are
+ * relevant.
+ * - 1 - The internal timer is disabled and the externally provided timer value
+ * is used. All other fields, except CAPTURE, in this register have no
+ * effect. CAPTURE can still be used to capture the current timer value.
+ */
+//@{
+#define BP_ENET_ATCR_SLAVE (13U) //!< Bit position for ENET_ATCR_SLAVE.
+#define BM_ENET_ATCR_SLAVE (0x00002000U) //!< Bit mask for ENET_ATCR_SLAVE.
+#define BS_ENET_ATCR_SLAVE (1U) //!< Bit field size in bits for ENET_ATCR_SLAVE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATCR_SLAVE field.
+#define BR_ENET_ATCR_SLAVE(x) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_SLAVE))
+#endif
+
+//! @brief Format value for bitfield ENET_ATCR_SLAVE.
+#define BF_ENET_ATCR_SLAVE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCR_SLAVE), uint32_t) & BM_ENET_ATCR_SLAVE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SLAVE field to a new value.
+#define BW_ENET_ATCR_SLAVE(x, v) (BITBAND_ACCESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_SLAVE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_ATVR - Timer Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_ATVR - Timer Value Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_atvr
+{
+ uint32_t U;
+ struct _hw_enet_atvr_bitfields
+ {
+ uint32_t ATIME : 32; //!< [31:0]
+ } B;
+} hw_enet_atvr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_ATVR register
+ */
+//@{
+#define HW_ENET_ATVR_ADDR(x) (REGS_ENET_BASE(x) + 0x404U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_ATVR(x) (*(__IO hw_enet_atvr_t *) HW_ENET_ATVR_ADDR(x))
+#define HW_ENET_ATVR_RD(x) (HW_ENET_ATVR(x).U)
+#define HW_ENET_ATVR_WR(x, v) (HW_ENET_ATVR(x).U = (v))
+#define HW_ENET_ATVR_SET(x, v) (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) | (v)))
+#define HW_ENET_ATVR_CLR(x, v) (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) & ~(v)))
+#define HW_ENET_ATVR_TOG(x, v) (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_ATVR bitfields
+ */
+
+/*!
+ * @name Register ENET_ATVR, field ATIME[31:0] (RW)
+ *
+ * A write sets the timer. A read returns the last captured value. To read the
+ * current value, issue a capture command (set ATCR[CAPTURE]) prior to reading
+ * this register.
+ */
+//@{
+#define BP_ENET_ATVR_ATIME (0U) //!< Bit position for ENET_ATVR_ATIME.
+#define BM_ENET_ATVR_ATIME (0xFFFFFFFFU) //!< Bit mask for ENET_ATVR_ATIME.
+#define BS_ENET_ATVR_ATIME (32U) //!< Bit field size in bits for ENET_ATVR_ATIME.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATVR_ATIME field.
+#define BR_ENET_ATVR_ATIME(x) (HW_ENET_ATVR(x).U)
+#endif
+
+//! @brief Format value for bitfield ENET_ATVR_ATIME.
+#define BF_ENET_ATVR_ATIME(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATVR_ATIME), uint32_t) & BM_ENET_ATVR_ATIME)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ATIME field to a new value.
+#define BW_ENET_ATVR_ATIME(x, v) (HW_ENET_ATVR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_ATOFF - Timer Offset Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_ATOFF - Timer Offset Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_atoff
+{
+ uint32_t U;
+ struct _hw_enet_atoff_bitfields
+ {
+ uint32_t OFFSET : 32; //!< [31:0]
+ } B;
+} hw_enet_atoff_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_ATOFF register
+ */
+//@{
+#define HW_ENET_ATOFF_ADDR(x) (REGS_ENET_BASE(x) + 0x408U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_ATOFF(x) (*(__IO hw_enet_atoff_t *) HW_ENET_ATOFF_ADDR(x))
+#define HW_ENET_ATOFF_RD(x) (HW_ENET_ATOFF(x).U)
+#define HW_ENET_ATOFF_WR(x, v) (HW_ENET_ATOFF(x).U = (v))
+#define HW_ENET_ATOFF_SET(x, v) (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) | (v)))
+#define HW_ENET_ATOFF_CLR(x, v) (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) & ~(v)))
+#define HW_ENET_ATOFF_TOG(x, v) (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_ATOFF bitfields
+ */
+
+/*!
+ * @name Register ENET_ATOFF, field OFFSET[31:0] (RW)
+ *
+ * Offset value for one-shot event generation. When the timer reaches the value,
+ * an event can be generated to reset the counter. If the increment value in
+ * ATINC is given in true nanoseconds, this value is also given in true nanoseconds.
+ */
+//@{
+#define BP_ENET_ATOFF_OFFSET (0U) //!< Bit position for ENET_ATOFF_OFFSET.
+#define BM_ENET_ATOFF_OFFSET (0xFFFFFFFFU) //!< Bit mask for ENET_ATOFF_OFFSET.
+#define BS_ENET_ATOFF_OFFSET (32U) //!< Bit field size in bits for ENET_ATOFF_OFFSET.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATOFF_OFFSET field.
+#define BR_ENET_ATOFF_OFFSET(x) (HW_ENET_ATOFF(x).U)
+#endif
+
+//! @brief Format value for bitfield ENET_ATOFF_OFFSET.
+#define BF_ENET_ATOFF_OFFSET(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATOFF_OFFSET), uint32_t) & BM_ENET_ATOFF_OFFSET)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OFFSET field to a new value.
+#define BW_ENET_ATOFF_OFFSET(x, v) (HW_ENET_ATOFF_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_ATPER - Timer Period Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_ATPER - Timer Period Register (RW)
+ *
+ * Reset value: 0x3B9ACA00U
+ */
+typedef union _hw_enet_atper
+{
+ uint32_t U;
+ struct _hw_enet_atper_bitfields
+ {
+ uint32_t PERIOD : 32; //!< [31:0]
+ } B;
+} hw_enet_atper_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_ATPER register
+ */
+//@{
+#define HW_ENET_ATPER_ADDR(x) (REGS_ENET_BASE(x) + 0x40CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_ATPER(x) (*(__IO hw_enet_atper_t *) HW_ENET_ATPER_ADDR(x))
+#define HW_ENET_ATPER_RD(x) (HW_ENET_ATPER(x).U)
+#define HW_ENET_ATPER_WR(x, v) (HW_ENET_ATPER(x).U = (v))
+#define HW_ENET_ATPER_SET(x, v) (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) | (v)))
+#define HW_ENET_ATPER_CLR(x, v) (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) & ~(v)))
+#define HW_ENET_ATPER_TOG(x, v) (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_ATPER bitfields
+ */
+
+/*!
+ * @name Register ENET_ATPER, field PERIOD[31:0] (RW)
+ *
+ * Value for generating periodic events. Each instance the timer reaches this
+ * value, the period event occurs and the timer restarts. If the increment value in
+ * ATINC is given in true nanoseconds, this value is also given in true
+ * nanoseconds. The value should be initialized to 1,000,000,000 (1 x 10 9 ) to represent
+ * a timer wrap around of one second. The increment value set in ATINC should be
+ * set to the true nanoseconds of the period of clock ts_clk, hence implementing
+ * a true 1 second counter.
+ */
+//@{
+#define BP_ENET_ATPER_PERIOD (0U) //!< Bit position for ENET_ATPER_PERIOD.
+#define BM_ENET_ATPER_PERIOD (0xFFFFFFFFU) //!< Bit mask for ENET_ATPER_PERIOD.
+#define BS_ENET_ATPER_PERIOD (32U) //!< Bit field size in bits for ENET_ATPER_PERIOD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATPER_PERIOD field.
+#define BR_ENET_ATPER_PERIOD(x) (HW_ENET_ATPER(x).U)
+#endif
+
+//! @brief Format value for bitfield ENET_ATPER_PERIOD.
+#define BF_ENET_ATPER_PERIOD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATPER_PERIOD), uint32_t) & BM_ENET_ATPER_PERIOD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PERIOD field to a new value.
+#define BW_ENET_ATPER_PERIOD(x, v) (HW_ENET_ATPER_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_ATCOR - Timer Correction Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_ATCOR - Timer Correction Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_atcor
+{
+ uint32_t U;
+ struct _hw_enet_atcor_bitfields
+ {
+ uint32_t COR : 31; //!< [30:0] Correction Counter Wrap-Around Value
+ uint32_t RESERVED0 : 1; //!< [31]
+ } B;
+} hw_enet_atcor_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_ATCOR register
+ */
+//@{
+#define HW_ENET_ATCOR_ADDR(x) (REGS_ENET_BASE(x) + 0x410U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_ATCOR(x) (*(__IO hw_enet_atcor_t *) HW_ENET_ATCOR_ADDR(x))
+#define HW_ENET_ATCOR_RD(x) (HW_ENET_ATCOR(x).U)
+#define HW_ENET_ATCOR_WR(x, v) (HW_ENET_ATCOR(x).U = (v))
+#define HW_ENET_ATCOR_SET(x, v) (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) | (v)))
+#define HW_ENET_ATCOR_CLR(x, v) (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) & ~(v)))
+#define HW_ENET_ATCOR_TOG(x, v) (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_ATCOR bitfields
+ */
+
+/*!
+ * @name Register ENET_ATCOR, field COR[30:0] (RW)
+ *
+ * Defines after how many timer clock cycles (ts_clk) the correction counter
+ * should be reset and trigger a correction increment on the timer. The amount of
+ * correction is defined in ATINC[INC_CORR]. A value of 0 disables the correction
+ * counter and no corrections occur. This value is given in clock cycles, not in
+ * nanoseconds as all other values.
+ */
+//@{
+#define BP_ENET_ATCOR_COR (0U) //!< Bit position for ENET_ATCOR_COR.
+#define BM_ENET_ATCOR_COR (0x7FFFFFFFU) //!< Bit mask for ENET_ATCOR_COR.
+#define BS_ENET_ATCOR_COR (31U) //!< Bit field size in bits for ENET_ATCOR_COR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATCOR_COR field.
+#define BR_ENET_ATCOR_COR(x) (HW_ENET_ATCOR(x).B.COR)
+#endif
+
+//! @brief Format value for bitfield ENET_ATCOR_COR.
+#define BF_ENET_ATCOR_COR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATCOR_COR), uint32_t) & BM_ENET_ATCOR_COR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COR field to a new value.
+#define BW_ENET_ATCOR_COR(x, v) (HW_ENET_ATCOR_WR(x, (HW_ENET_ATCOR_RD(x) & ~BM_ENET_ATCOR_COR) | BF_ENET_ATCOR_COR(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_ATINC - Time-Stamping Clock Period Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_ATINC - Time-Stamping Clock Period Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_atinc
+{
+ uint32_t U;
+ struct _hw_enet_atinc_bitfields
+ {
+ uint32_t INC : 7; //!< [6:0] Clock Period Of The Timestamping Clock
+ //! (ts_clk) In Nanoseconds
+ uint32_t RESERVED0 : 1; //!< [7]
+ uint32_t INC_CORR : 7; //!< [14:8] Correction Increment Value
+ uint32_t RESERVED1 : 17; //!< [31:15]
+ } B;
+} hw_enet_atinc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_ATINC register
+ */
+//@{
+#define HW_ENET_ATINC_ADDR(x) (REGS_ENET_BASE(x) + 0x414U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_ATINC(x) (*(__IO hw_enet_atinc_t *) HW_ENET_ATINC_ADDR(x))
+#define HW_ENET_ATINC_RD(x) (HW_ENET_ATINC(x).U)
+#define HW_ENET_ATINC_WR(x, v) (HW_ENET_ATINC(x).U = (v))
+#define HW_ENET_ATINC_SET(x, v) (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) | (v)))
+#define HW_ENET_ATINC_CLR(x, v) (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) & ~(v)))
+#define HW_ENET_ATINC_TOG(x, v) (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_ATINC bitfields
+ */
+
+/*!
+ * @name Register ENET_ATINC, field INC[6:0] (RW)
+ *
+ * The timer increments by this amount each clock cycle. For example, set to 10
+ * for 100 MHz, 8 for 125 MHz, 5 for 200 MHz. For highest precision, use a value
+ * that is an integer fraction of the period set in ATPER.
+ */
+//@{
+#define BP_ENET_ATINC_INC (0U) //!< Bit position for ENET_ATINC_INC.
+#define BM_ENET_ATINC_INC (0x0000007FU) //!< Bit mask for ENET_ATINC_INC.
+#define BS_ENET_ATINC_INC (7U) //!< Bit field size in bits for ENET_ATINC_INC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATINC_INC field.
+#define BR_ENET_ATINC_INC(x) (HW_ENET_ATINC(x).B.INC)
+#endif
+
+//! @brief Format value for bitfield ENET_ATINC_INC.
+#define BF_ENET_ATINC_INC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATINC_INC), uint32_t) & BM_ENET_ATINC_INC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INC field to a new value.
+#define BW_ENET_ATINC_INC(x, v) (HW_ENET_ATINC_WR(x, (HW_ENET_ATINC_RD(x) & ~BM_ENET_ATINC_INC) | BF_ENET_ATINC_INC(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_ATINC, field INC_CORR[14:8] (RW)
+ *
+ * This value is added every time the correction timer expires (every clock
+ * cycle given in ATCOR). A value less than INC slows down the timer. A value greater
+ * than INC speeds up the timer.
+ */
+//@{
+#define BP_ENET_ATINC_INC_CORR (8U) //!< Bit position for ENET_ATINC_INC_CORR.
+#define BM_ENET_ATINC_INC_CORR (0x00007F00U) //!< Bit mask for ENET_ATINC_INC_CORR.
+#define BS_ENET_ATINC_INC_CORR (7U) //!< Bit field size in bits for ENET_ATINC_INC_CORR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATINC_INC_CORR field.
+#define BR_ENET_ATINC_INC_CORR(x) (HW_ENET_ATINC(x).B.INC_CORR)
+#endif
+
+//! @brief Format value for bitfield ENET_ATINC_INC_CORR.
+#define BF_ENET_ATINC_INC_CORR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_ATINC_INC_CORR), uint32_t) & BM_ENET_ATINC_INC_CORR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INC_CORR field to a new value.
+#define BW_ENET_ATINC_INC_CORR(x, v) (HW_ENET_ATINC_WR(x, (HW_ENET_ATINC_RD(x) & ~BM_ENET_ATINC_INC_CORR) | BF_ENET_ATINC_INC_CORR(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_atstmp
+{
+ uint32_t U;
+ struct _hw_enet_atstmp_bitfields
+ {
+ uint32_t TIMESTAMP : 32; //!< [31:0]
+ } B;
+} hw_enet_atstmp_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_ATSTMP register
+ */
+//@{
+#define HW_ENET_ATSTMP_ADDR(x) (REGS_ENET_BASE(x) + 0x418U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_ATSTMP(x) (*(__I hw_enet_atstmp_t *) HW_ENET_ATSTMP_ADDR(x))
+#define HW_ENET_ATSTMP_RD(x) (HW_ENET_ATSTMP(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_ATSTMP bitfields
+ */
+
+/*!
+ * @name Register ENET_ATSTMP, field TIMESTAMP[31:0] (RO)
+ *
+ * Timestamp of the last frame transmitted by the core that had TxBD[TS] set .
+ * This register is only valid when EIR[TS_AVAIL] is set.
+ */
+//@{
+#define BP_ENET_ATSTMP_TIMESTAMP (0U) //!< Bit position for ENET_ATSTMP_TIMESTAMP.
+#define BM_ENET_ATSTMP_TIMESTAMP (0xFFFFFFFFU) //!< Bit mask for ENET_ATSTMP_TIMESTAMP.
+#define BS_ENET_ATSTMP_TIMESTAMP (32U) //!< Bit field size in bits for ENET_ATSTMP_TIMESTAMP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_ATSTMP_TIMESTAMP field.
+#define BR_ENET_ATSTMP_TIMESTAMP(x) (HW_ENET_ATSTMP(x).U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_TGSR - Timer Global Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_TGSR - Timer Global Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_tgsr
+{
+ uint32_t U;
+ struct _hw_enet_tgsr_bitfields
+ {
+ uint32_t TF0 : 1; //!< [0] Copy Of Timer Flag For Channel 0
+ uint32_t TF1 : 1; //!< [1] Copy Of Timer Flag For Channel 1
+ uint32_t TF2 : 1; //!< [2] Copy Of Timer Flag For Channel 2
+ uint32_t TF3 : 1; //!< [3] Copy Of Timer Flag For Channel 3
+ uint32_t RESERVED0 : 28; //!< [31:4]
+ } B;
+} hw_enet_tgsr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_TGSR register
+ */
+//@{
+#define HW_ENET_TGSR_ADDR(x) (REGS_ENET_BASE(x) + 0x604U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_TGSR(x) (*(__IO hw_enet_tgsr_t *) HW_ENET_TGSR_ADDR(x))
+#define HW_ENET_TGSR_RD(x) (HW_ENET_TGSR(x).U)
+#define HW_ENET_TGSR_WR(x, v) (HW_ENET_TGSR(x).U = (v))
+#define HW_ENET_TGSR_SET(x, v) (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) | (v)))
+#define HW_ENET_TGSR_CLR(x, v) (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) & ~(v)))
+#define HW_ENET_TGSR_TOG(x, v) (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_TGSR bitfields
+ */
+
+/*!
+ * @name Register ENET_TGSR, field TF0[0] (W1C)
+ *
+ * Values:
+ * - 0 - Timer Flag for Channel 0 is clear
+ * - 1 - Timer Flag for Channel 0 is set
+ */
+//@{
+#define BP_ENET_TGSR_TF0 (0U) //!< Bit position for ENET_TGSR_TF0.
+#define BM_ENET_TGSR_TF0 (0x00000001U) //!< Bit mask for ENET_TGSR_TF0.
+#define BS_ENET_TGSR_TF0 (1U) //!< Bit field size in bits for ENET_TGSR_TF0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TGSR_TF0 field.
+#define BR_ENET_TGSR_TF0(x) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF0))
+#endif
+
+//! @brief Format value for bitfield ENET_TGSR_TF0.
+#define BF_ENET_TGSR_TF0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TGSR_TF0), uint32_t) & BM_ENET_TGSR_TF0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TF0 field to a new value.
+#define BW_ENET_TGSR_TF0(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TGSR, field TF1[1] (W1C)
+ *
+ * Values:
+ * - 0 - Timer Flag for Channel 1 is clear
+ * - 1 - Timer Flag for Channel 1 is set
+ */
+//@{
+#define BP_ENET_TGSR_TF1 (1U) //!< Bit position for ENET_TGSR_TF1.
+#define BM_ENET_TGSR_TF1 (0x00000002U) //!< Bit mask for ENET_TGSR_TF1.
+#define BS_ENET_TGSR_TF1 (1U) //!< Bit field size in bits for ENET_TGSR_TF1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TGSR_TF1 field.
+#define BR_ENET_TGSR_TF1(x) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF1))
+#endif
+
+//! @brief Format value for bitfield ENET_TGSR_TF1.
+#define BF_ENET_TGSR_TF1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TGSR_TF1), uint32_t) & BM_ENET_TGSR_TF1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TF1 field to a new value.
+#define BW_ENET_TGSR_TF1(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TGSR, field TF2[2] (W1C)
+ *
+ * Values:
+ * - 0 - Timer Flag for Channel 2 is clear
+ * - 1 - Timer Flag for Channel 2 is set
+ */
+//@{
+#define BP_ENET_TGSR_TF2 (2U) //!< Bit position for ENET_TGSR_TF2.
+#define BM_ENET_TGSR_TF2 (0x00000004U) //!< Bit mask for ENET_TGSR_TF2.
+#define BS_ENET_TGSR_TF2 (1U) //!< Bit field size in bits for ENET_TGSR_TF2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TGSR_TF2 field.
+#define BR_ENET_TGSR_TF2(x) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF2))
+#endif
+
+//! @brief Format value for bitfield ENET_TGSR_TF2.
+#define BF_ENET_TGSR_TF2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TGSR_TF2), uint32_t) & BM_ENET_TGSR_TF2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TF2 field to a new value.
+#define BW_ENET_TGSR_TF2(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TGSR, field TF3[3] (W1C)
+ *
+ * Values:
+ * - 0 - Timer Flag for Channel 3 is clear
+ * - 1 - Timer Flag for Channel 3 is set
+ */
+//@{
+#define BP_ENET_TGSR_TF3 (3U) //!< Bit position for ENET_TGSR_TF3.
+#define BM_ENET_TGSR_TF3 (0x00000008U) //!< Bit mask for ENET_TGSR_TF3.
+#define BS_ENET_TGSR_TF3 (1U) //!< Bit field size in bits for ENET_TGSR_TF3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TGSR_TF3 field.
+#define BR_ENET_TGSR_TF3(x) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF3))
+#endif
+
+//! @brief Format value for bitfield ENET_TGSR_TF3.
+#define BF_ENET_TGSR_TF3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TGSR_TF3), uint32_t) & BM_ENET_TGSR_TF3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TF3 field to a new value.
+#define BW_ENET_TGSR_TF3(x, v) (BITBAND_ACCESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF3) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_ENET_TCSRn - Timer Control Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_TCSRn - Timer Control Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_tcsrn
+{
+ uint32_t U;
+ struct _hw_enet_tcsrn_bitfields
+ {
+ uint32_t TDRE : 1; //!< [0] Timer DMA Request Enable
+ uint32_t RESERVED0 : 1; //!< [1]
+ uint32_t TMODE : 4; //!< [5:2] Timer Mode
+ uint32_t TIE : 1; //!< [6] Timer Interrupt Enable
+ uint32_t TF : 1; //!< [7] Timer Flag
+ uint32_t RESERVED1 : 24; //!< [31:8]
+ } B;
+} hw_enet_tcsrn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_TCSRn register
+ */
+//@{
+#define HW_ENET_TCSRn_COUNT (4U)
+
+#define HW_ENET_TCSRn_ADDR(x, n) (REGS_ENET_BASE(x) + 0x608U + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_TCSRn(x, n) (*(__IO hw_enet_tcsrn_t *) HW_ENET_TCSRn_ADDR(x, n))
+#define HW_ENET_TCSRn_RD(x, n) (HW_ENET_TCSRn(x, n).U)
+#define HW_ENET_TCSRn_WR(x, n, v) (HW_ENET_TCSRn(x, n).U = (v))
+#define HW_ENET_TCSRn_SET(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) | (v)))
+#define HW_ENET_TCSRn_CLR(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) & ~(v)))
+#define HW_ENET_TCSRn_TOG(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_TCSRn bitfields
+ */
+
+/*!
+ * @name Register ENET_TCSRn, field TDRE[0] (RW)
+ *
+ * Values:
+ * - 0 - DMA request is disabled
+ * - 1 - DMA request is enabled
+ */
+//@{
+#define BP_ENET_TCSRn_TDRE (0U) //!< Bit position for ENET_TCSRn_TDRE.
+#define BM_ENET_TCSRn_TDRE (0x00000001U) //!< Bit mask for ENET_TCSRn_TDRE.
+#define BS_ENET_TCSRn_TDRE (1U) //!< Bit field size in bits for ENET_TCSRn_TDRE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TCSRn_TDRE field.
+#define BR_ENET_TCSRn_TDRE(x, n) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TDRE))
+#endif
+
+//! @brief Format value for bitfield ENET_TCSRn_TDRE.
+#define BF_ENET_TCSRn_TDRE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCSRn_TDRE), uint32_t) & BM_ENET_TCSRn_TDRE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TDRE field to a new value.
+#define BW_ENET_TCSRn_TDRE(x, n, v) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TDRE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TCSRn, field TMODE[5:2] (RW)
+ *
+ * Updating the Timer Mode field takes a few cycles to register because it is
+ * synchronized to the 1588 clock. The version of Timer Mode returned on a read is
+ * from the 1588 clock domain. When changing Timer Mode, always disable the
+ * channel and read this register to verify the channel is disabled first.
+ *
+ * Values:
+ * - 0000 - Timer Channel is disabled.
+ * - 0001 - Timer Channel is configured for Input Capture on rising edge
+ * - 0010 - Timer Channel is configured for Input Capture on falling edge
+ * - 0011 - Timer Channel is configured for Input Capture on both edges
+ * - 0100 - Timer Channel is configured for Output Compare - software only
+ * - 0101 - Timer Channel is configured for Output Compare - toggle output on
+ * compare
+ * - 0110 - Timer Channel is configured for Output Compare - clear output on
+ * compare
+ * - 0111 - Timer Channel is configured for Output Compare - set output on
+ * compare
+ * - 1000 - Reserved
+ * - 1010 - Timer Channel is configured for Output Compare - clear output on
+ * compare, set output on overflow
+ * - 10x1 - Timer Channel is configured for Output Compare - set output on
+ * compare, clear output on overflow
+ * - 1100 - Reserved
+ * - 1110 - Timer Channel is configured for Output Compare - pulse output low on
+ * compare for one 1588 clock cycle
+ * - 1111 - Timer Channel is configured for Output Compare - pulse output high
+ * on compare for one 1588 clock cycle
+ */
+//@{
+#define BP_ENET_TCSRn_TMODE (2U) //!< Bit position for ENET_TCSRn_TMODE.
+#define BM_ENET_TCSRn_TMODE (0x0000003CU) //!< Bit mask for ENET_TCSRn_TMODE.
+#define BS_ENET_TCSRn_TMODE (4U) //!< Bit field size in bits for ENET_TCSRn_TMODE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TCSRn_TMODE field.
+#define BR_ENET_TCSRn_TMODE(x, n) (HW_ENET_TCSRn(x, n).B.TMODE)
+#endif
+
+//! @brief Format value for bitfield ENET_TCSRn_TMODE.
+#define BF_ENET_TCSRn_TMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCSRn_TMODE), uint32_t) & BM_ENET_TCSRn_TMODE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TMODE field to a new value.
+#define BW_ENET_TCSRn_TMODE(x, n, v) (HW_ENET_TCSRn_WR(x, n, (HW_ENET_TCSRn_RD(x, n) & ~BM_ENET_TCSRn_TMODE) | BF_ENET_TCSRn_TMODE(v)))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TCSRn, field TIE[6] (RW)
+ *
+ * Values:
+ * - 0 - Interrupt is disabled
+ * - 1 - Interrupt is enabled
+ */
+//@{
+#define BP_ENET_TCSRn_TIE (6U) //!< Bit position for ENET_TCSRn_TIE.
+#define BM_ENET_TCSRn_TIE (0x00000040U) //!< Bit mask for ENET_TCSRn_TIE.
+#define BS_ENET_TCSRn_TIE (1U) //!< Bit field size in bits for ENET_TCSRn_TIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TCSRn_TIE field.
+#define BR_ENET_TCSRn_TIE(x, n) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TIE))
+#endif
+
+//! @brief Format value for bitfield ENET_TCSRn_TIE.
+#define BF_ENET_TCSRn_TIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCSRn_TIE), uint32_t) & BM_ENET_TCSRn_TIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TIE field to a new value.
+#define BW_ENET_TCSRn_TIE(x, n, v) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register ENET_TCSRn, field TF[7] (W1C)
+ *
+ * Sets when input capture or output compare occurs. This flag is double
+ * buffered between the module clock and 1588 clock domains. When this field is 1, it
+ * can be cleared to 0 by writing 1 to it.
+ *
+ * Values:
+ * - 0 - Input Capture or Output Compare has not occurred
+ * - 1 - Input Capture or Output Compare has occurred
+ */
+//@{
+#define BP_ENET_TCSRn_TF (7U) //!< Bit position for ENET_TCSRn_TF.
+#define BM_ENET_TCSRn_TF (0x00000080U) //!< Bit mask for ENET_TCSRn_TF.
+#define BS_ENET_TCSRn_TF (1U) //!< Bit field size in bits for ENET_TCSRn_TF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TCSRn_TF field.
+#define BR_ENET_TCSRn_TF(x, n) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TF))
+#endif
+
+//! @brief Format value for bitfield ENET_TCSRn_TF.
+#define BF_ENET_TCSRn_TF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCSRn_TF), uint32_t) & BM_ENET_TCSRn_TF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TF field to a new value.
+#define BW_ENET_TCSRn_TF(x, n, v) (BITBAND_ACCESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TF) = (v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_ENET_TCCRn - Timer Compare Capture Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ENET_TCCRn - Timer Compare Capture Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_enet_tccrn
+{
+ uint32_t U;
+ struct _hw_enet_tccrn_bitfields
+ {
+ uint32_t TCC : 32; //!< [31:0] Timer Capture Compare
+ } B;
+} hw_enet_tccrn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ENET_TCCRn register
+ */
+//@{
+#define HW_ENET_TCCRn_COUNT (4U)
+
+#define HW_ENET_TCCRn_ADDR(x, n) (REGS_ENET_BASE(x) + 0x60CU + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ENET_TCCRn(x, n) (*(__IO hw_enet_tccrn_t *) HW_ENET_TCCRn_ADDR(x, n))
+#define HW_ENET_TCCRn_RD(x, n) (HW_ENET_TCCRn(x, n).U)
+#define HW_ENET_TCCRn_WR(x, n, v) (HW_ENET_TCCRn(x, n).U = (v))
+#define HW_ENET_TCCRn_SET(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) | (v)))
+#define HW_ENET_TCCRn_CLR(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) & ~(v)))
+#define HW_ENET_TCCRn_TOG(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual ENET_TCCRn bitfields
+ */
+
+/*!
+ * @name Register ENET_TCCRn, field TCC[31:0] (RW)
+ *
+ * This register is double buffered between the module clock and 1588 clock
+ * domains. When configured for compare, the 1588 clock domain updates with the value
+ * in the module clock domain whenever the Timer Channel is first enabled and on
+ * each subsequent compare. Write to this register with the first compare value
+ * before enabling the Timer Channel. When the Timer Channel is enabled, write
+ * the second compare value either immediately, or at least before the first
+ * compare occurs. After each compare, write the next compare value before the previous
+ * compare occurs and before clearing the Timer Flag. The compare occurs one
+ * 1588 clock cycle after the IEEE 1588 Counter increments past the compare value in
+ * the 1588 clock domain. If the compare value is less than the value of the
+ * 1588 Counter when the Timer Channel is first enabled, then the compare does not
+ * occur until following the next overflow of the 1588 Counter. If the compare
+ * value is greater than the IEEE 1588 Counter when the 1588 Counter overflows, or
+ * the compare value is less than the value of the IEEE 1588 Counter after the
+ * overflow, then the compare occurs one 1588 clock cycle following the overflow.
+ * When configured for Capture, the value of the IEEE 1588 Counter is captured into
+ * the 1588 clock domain and then updated into the module clock domain, provided
+ * the Timer Flag is clear. Always read the capture value before clearing the
+ * Timer Flag.
+ */
+//@{
+#define BP_ENET_TCCRn_TCC (0U) //!< Bit position for ENET_TCCRn_TCC.
+#define BM_ENET_TCCRn_TCC (0xFFFFFFFFU) //!< Bit mask for ENET_TCCRn_TCC.
+#define BS_ENET_TCCRn_TCC (32U) //!< Bit field size in bits for ENET_TCCRn_TCC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the ENET_TCCRn_TCC field.
+#define BR_ENET_TCCRn_TCC(x, n) (HW_ENET_TCCRn(x, n).U)
+#endif
+
+//! @brief Format value for bitfield ENET_TCCRn_TCC.
+#define BF_ENET_TCCRn_TCC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_ENET_TCCRn_TCC), uint32_t) & BM_ENET_TCCRn_TCC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCC field to a new value.
+#define BW_ENET_TCCRn_TCC(x, n, v) (HW_ENET_TCCRn_WR(x, n, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_enet_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All ENET module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_enet
+{
+ uint8_t _reserved0[4];
+ __IO hw_enet_eir_t EIR; //!< [0x4] Interrupt Event Register
+ __IO hw_enet_eimr_t EIMR; //!< [0x8] Interrupt Mask Register
+ uint8_t _reserved1[4];
+ __IO hw_enet_rdar_t RDAR; //!< [0x10] Receive Descriptor Active Register
+ __IO hw_enet_tdar_t TDAR; //!< [0x14] Transmit Descriptor Active Register
+ uint8_t _reserved2[12];
+ __IO hw_enet_ecr_t ECR; //!< [0x24] Ethernet Control Register
+ uint8_t _reserved3[24];
+ __IO hw_enet_mmfr_t MMFR; //!< [0x40] MII Management Frame Register
+ __IO hw_enet_mscr_t MSCR; //!< [0x44] MII Speed Control Register
+ uint8_t _reserved4[28];
+ __IO hw_enet_mibc_t MIBC; //!< [0x64] MIB Control Register
+ uint8_t _reserved5[28];
+ __IO hw_enet_rcr_t RCR; //!< [0x84] Receive Control Register
+ uint8_t _reserved6[60];
+ __IO hw_enet_tcr_t TCR; //!< [0xC4] Transmit Control Register
+ uint8_t _reserved7[28];
+ __IO hw_enet_palr_t PALR; //!< [0xE4] Physical Address Lower Register
+ __IO hw_enet_paur_t PAUR; //!< [0xE8] Physical Address Upper Register
+ __IO hw_enet_opd_t OPD; //!< [0xEC] Opcode/Pause Duration Register
+ uint8_t _reserved8[40];
+ __IO hw_enet_iaur_t IAUR; //!< [0x118] Descriptor Individual Upper Address Register
+ __IO hw_enet_ialr_t IALR; //!< [0x11C] Descriptor Individual Lower Address Register
+ __IO hw_enet_gaur_t GAUR; //!< [0x120] Descriptor Group Upper Address Register
+ __IO hw_enet_galr_t GALR; //!< [0x124] Descriptor Group Lower Address Register
+ uint8_t _reserved9[28];
+ __IO hw_enet_tfwr_t TFWR; //!< [0x144] Transmit FIFO Watermark Register
+ uint8_t _reserved10[56];
+ __IO hw_enet_rdsr_t RDSR; //!< [0x180] Receive Descriptor Ring Start Register
+ __IO hw_enet_tdsr_t TDSR; //!< [0x184] Transmit Buffer Descriptor Ring Start Register
+ __IO hw_enet_mrbr_t MRBR; //!< [0x188] Maximum Receive Buffer Size Register
+ uint8_t _reserved11[4];
+ __IO hw_enet_rsfl_t RSFL; //!< [0x190] Receive FIFO Section Full Threshold
+ __IO hw_enet_rsem_t RSEM; //!< [0x194] Receive FIFO Section Empty Threshold
+ __IO hw_enet_raem_t RAEM; //!< [0x198] Receive FIFO Almost Empty Threshold
+ __IO hw_enet_rafl_t RAFL; //!< [0x19C] Receive FIFO Almost Full Threshold
+ __IO hw_enet_tsem_t TSEM; //!< [0x1A0] Transmit FIFO Section Empty Threshold
+ __IO hw_enet_taem_t TAEM; //!< [0x1A4] Transmit FIFO Almost Empty Threshold
+ __IO hw_enet_tafl_t TAFL; //!< [0x1A8] Transmit FIFO Almost Full Threshold
+ __IO hw_enet_tipg_t TIPG; //!< [0x1AC] Transmit Inter-Packet Gap
+ __IO hw_enet_ftrl_t FTRL; //!< [0x1B0] Frame Truncation Length
+ uint8_t _reserved12[12];
+ __IO hw_enet_tacc_t TACC; //!< [0x1C0] Transmit Accelerator Function Configuration
+ __IO hw_enet_racc_t RACC; //!< [0x1C4] Receive Accelerator Function Configuration
+ uint8_t _reserved13[60];
+ __I hw_enet_rmon_t_packets_t RMON_T_PACKETS; //!< [0x204] Tx Packet Count Statistic Register
+ __I hw_enet_rmon_t_bc_pkt_t RMON_T_BC_PKT; //!< [0x208] Tx Broadcast Packets Statistic Register
+ __I hw_enet_rmon_t_mc_pkt_t RMON_T_MC_PKT; //!< [0x20C] Tx Multicast Packets Statistic Register
+ __I hw_enet_rmon_t_crc_align_t RMON_T_CRC_ALIGN; //!< [0x210] Tx Packets with CRC/Align Error Statistic Register
+ __I hw_enet_rmon_t_undersize_t RMON_T_UNDERSIZE; //!< [0x214] Tx Packets Less Than Bytes and Good CRC Statistic Register
+ __I hw_enet_rmon_t_oversize_t RMON_T_OVERSIZE; //!< [0x218] Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
+ __I hw_enet_rmon_t_frag_t RMON_T_FRAG; //!< [0x21C] Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ __I hw_enet_rmon_t_jab_t RMON_T_JAB; //!< [0x220] Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
+ __I hw_enet_rmon_t_col_t RMON_T_COL; //!< [0x224] Tx Collision Count Statistic Register
+ __I hw_enet_rmon_t_p64_t RMON_T_P64; //!< [0x228] Tx 64-Byte Packets Statistic Register
+ __I hw_enet_rmon_t_p65to127_t RMON_T_P65TO127; //!< [0x22C] Tx 65- to 127-byte Packets Statistic Register
+ __I hw_enet_rmon_t_p128to255_t RMON_T_P128TO255; //!< [0x230] Tx 128- to 255-byte Packets Statistic Register
+ __I hw_enet_rmon_t_p256to511_t RMON_T_P256TO511; //!< [0x234] Tx 256- to 511-byte Packets Statistic Register
+ __I hw_enet_rmon_t_p512to1023_t RMON_T_P512TO1023; //!< [0x238] Tx 512- to 1023-byte Packets Statistic Register
+ __I hw_enet_rmon_t_p1024to2047_t RMON_T_P1024TO2047; //!< [0x23C] Tx 1024- to 2047-byte Packets Statistic Register
+ __I hw_enet_rmon_t_p_gte2048_t RMON_T_P_GTE2048; //!< [0x240] Tx Packets Greater Than 2048 Bytes Statistic Register
+ __I hw_enet_rmon_t_octets_t RMON_T_OCTETS; //!< [0x244] Tx Octets Statistic Register
+ uint8_t _reserved14[4];
+ __I hw_enet_ieee_t_frame_ok_t IEEE_T_FRAME_OK; //!< [0x24C] Frames Transmitted OK Statistic Register
+ __I hw_enet_ieee_t_1col_t IEEE_T_1COL; //!< [0x250] Frames Transmitted with Single Collision Statistic Register
+ __I hw_enet_ieee_t_mcol_t IEEE_T_MCOL; //!< [0x254] Frames Transmitted with Multiple Collisions Statistic Register
+ __I hw_enet_ieee_t_def_t IEEE_T_DEF; //!< [0x258] Frames Transmitted after Deferral Delay Statistic Register
+ __I hw_enet_ieee_t_lcol_t IEEE_T_LCOL; //!< [0x25C] Frames Transmitted with Late Collision Statistic Register
+ __I hw_enet_ieee_t_excol_t IEEE_T_EXCOL; //!< [0x260] Frames Transmitted with Excessive Collisions Statistic Register
+ __I hw_enet_ieee_t_macerr_t IEEE_T_MACERR; //!< [0x264] Frames Transmitted with Tx FIFO Underrun Statistic Register
+ __I hw_enet_ieee_t_cserr_t IEEE_T_CSERR; //!< [0x268] Frames Transmitted with Carrier Sense Error Statistic Register
+ uint8_t _reserved15[4];
+ __I hw_enet_ieee_t_fdxfc_t IEEE_T_FDXFC; //!< [0x270] Flow Control Pause Frames Transmitted Statistic Register
+ __I hw_enet_ieee_t_octets_ok_t IEEE_T_OCTETS_OK; //!< [0x274] Octet Count for Frames Transmitted w/o Error Statistic Register
+ uint8_t _reserved16[12];
+ __I hw_enet_rmon_r_packets_t RMON_R_PACKETS; //!< [0x284] Rx Packet Count Statistic Register
+ __I hw_enet_rmon_r_bc_pkt_t RMON_R_BC_PKT; //!< [0x288] Rx Broadcast Packets Statistic Register
+ __I hw_enet_rmon_r_mc_pkt_t RMON_R_MC_PKT; //!< [0x28C] Rx Multicast Packets Statistic Register
+ __I hw_enet_rmon_r_crc_align_t RMON_R_CRC_ALIGN; //!< [0x290] Rx Packets with CRC/Align Error Statistic Register
+ __I hw_enet_rmon_r_undersize_t RMON_R_UNDERSIZE; //!< [0x294] Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
+ __I hw_enet_rmon_r_oversize_t RMON_R_OVERSIZE; //!< [0x298] Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
+ __I hw_enet_rmon_r_frag_t RMON_R_FRAG; //!< [0x29C] Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ __I hw_enet_rmon_r_jab_t RMON_R_JAB; //!< [0x2A0] Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
+ uint8_t _reserved17[4];
+ __I hw_enet_rmon_r_p64_t RMON_R_P64; //!< [0x2A8] Rx 64-Byte Packets Statistic Register
+ __I hw_enet_rmon_r_p65to127_t RMON_R_P65TO127; //!< [0x2AC] Rx 65- to 127-Byte Packets Statistic Register
+ __I hw_enet_rmon_r_p128to255_t RMON_R_P128TO255; //!< [0x2B0] Rx 128- to 255-Byte Packets Statistic Register
+ __I hw_enet_rmon_r_p256to511_t RMON_R_P256TO511; //!< [0x2B4] Rx 256- to 511-Byte Packets Statistic Register
+ __I hw_enet_rmon_r_p512to1023_t RMON_R_P512TO1023; //!< [0x2B8] Rx 512- to 1023-Byte Packets Statistic Register
+ __I hw_enet_rmon_r_p1024to2047_t RMON_R_P1024TO2047; //!< [0x2BC] Rx 1024- to 2047-Byte Packets Statistic Register
+ __I hw_enet_rmon_r_gte2048_t RMON_R_GTE2048; //!< [0x2C0] Rx Packets Greater than 2048 Bytes Statistic Register
+ __I hw_enet_rmon_r_octets_t RMON_R_OCTETS; //!< [0x2C4] Rx Octets Statistic Register
+ __I hw_enet_ieee_r_drop_t IEEE_R_DROP; //!< [0x2C8] Frames not Counted Correctly Statistic Register
+ __I hw_enet_ieee_r_frame_ok_t IEEE_R_FRAME_OK; //!< [0x2CC] Frames Received OK Statistic Register
+ __I hw_enet_ieee_r_crc_t IEEE_R_CRC; //!< [0x2D0] Frames Received with CRC Error Statistic Register
+ __I hw_enet_ieee_r_align_t IEEE_R_ALIGN; //!< [0x2D4] Frames Received with Alignment Error Statistic Register
+ __I hw_enet_ieee_r_macerr_t IEEE_R_MACERR; //!< [0x2D8] Receive FIFO Overflow Count Statistic Register
+ __I hw_enet_ieee_r_fdxfc_t IEEE_R_FDXFC; //!< [0x2DC] Flow Control Pause Frames Received Statistic Register
+ __I hw_enet_ieee_r_octets_ok_t IEEE_R_OCTETS_OK; //!< [0x2E0] Octet Count for Frames Received without Error Statistic Register
+ uint8_t _reserved18[284];
+ __IO hw_enet_atcr_t ATCR; //!< [0x400] Adjustable Timer Control Register
+ __IO hw_enet_atvr_t ATVR; //!< [0x404] Timer Value Register
+ __IO hw_enet_atoff_t ATOFF; //!< [0x408] Timer Offset Register
+ __IO hw_enet_atper_t ATPER; //!< [0x40C] Timer Period Register
+ __IO hw_enet_atcor_t ATCOR; //!< [0x410] Timer Correction Register
+ __IO hw_enet_atinc_t ATINC; //!< [0x414] Time-Stamping Clock Period Register
+ __I hw_enet_atstmp_t ATSTMP; //!< [0x418] Timestamp of Last Transmitted Frame
+ uint8_t _reserved19[488];
+ __IO hw_enet_tgsr_t TGSR; //!< [0x604] Timer Global Status Register
+ struct {
+ __IO hw_enet_tcsrn_t TCSRn; //!< [0x608] Timer Control Status Register
+ __IO hw_enet_tccrn_t TCCRn; //!< [0x60C] Timer Compare Capture Register
+ } CHANNEL[4];
+} hw_enet_t;
+#pragma pack()
+
+//! @brief Macro to access all ENET registers.
+//! @param x ENET instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_ENET(0)</code>.
+#define HW_ENET(x) (*(hw_enet_t *) REGS_ENET_BASE(x))
+#endif
+
+#endif // __HW_ENET_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_ewm.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,430 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_EWM_REGISTERS_H__
+#define __HW_EWM_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 EWM
+ *
+ * External Watchdog Monitor
+ *
+ * Registers defined in this header file:
+ * - HW_EWM_CTRL - Control Register
+ * - HW_EWM_SERV - Service Register
+ * - HW_EWM_CMPL - Compare Low Register
+ * - HW_EWM_CMPH - Compare High Register
+ *
+ * - hw_ewm_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_EWM_BASE
+#define HW_EWM_INSTANCE_COUNT (1U) //!< Number of instances of the EWM module.
+#define REGS_EWM_BASE (0x40061000U) //!< Base address for EWM.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_EWM_CTRL - Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_EWM_CTRL - Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The CTRL register is cleared by any reset. INEN, ASSIN and EWMEN bits can be
+ * written once after a CPU reset. Modifying these bits more than once, generates
+ * a bus transfer error.
+ */
+typedef union _hw_ewm_ctrl
+{
+ uint8_t U;
+ struct _hw_ewm_ctrl_bitfields
+ {
+ uint8_t EWMEN : 1; //!< [0] EWM enable.
+ uint8_t ASSIN : 1; //!< [1] EWM_in's Assertion State Select.
+ uint8_t INEN : 1; //!< [2] Input Enable.
+ uint8_t INTEN : 1; //!< [3] Interrupt Enable.
+ uint8_t RESERVED0 : 4; //!< [7:4]
+ } B;
+} hw_ewm_ctrl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire EWM_CTRL register
+ */
+//@{
+#define HW_EWM_CTRL_ADDR (REGS_EWM_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_EWM_CTRL (*(__IO hw_ewm_ctrl_t *) HW_EWM_CTRL_ADDR)
+#define HW_EWM_CTRL_RD() (HW_EWM_CTRL.U)
+#define HW_EWM_CTRL_WR(v) (HW_EWM_CTRL.U = (v))
+#define HW_EWM_CTRL_SET(v) (HW_EWM_CTRL_WR(HW_EWM_CTRL_RD() | (v)))
+#define HW_EWM_CTRL_CLR(v) (HW_EWM_CTRL_WR(HW_EWM_CTRL_RD() & ~(v)))
+#define HW_EWM_CTRL_TOG(v) (HW_EWM_CTRL_WR(HW_EWM_CTRL_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual EWM_CTRL bitfields
+ */
+
+/*!
+ * @name Register EWM_CTRL, field EWMEN[0] (RW)
+ *
+ * This bit when set, enables the EWM module. This resets the EWM counter to
+ * zero and deasserts the EWM_out signal. Clearing EWMEN bit disables the EWM, and
+ * therefore it cannot be enabled until a reset occurs, due to the write-once
+ * nature of this bit.
+ */
+//@{
+#define BP_EWM_CTRL_EWMEN (0U) //!< Bit position for EWM_CTRL_EWMEN.
+#define BM_EWM_CTRL_EWMEN (0x01U) //!< Bit mask for EWM_CTRL_EWMEN.
+#define BS_EWM_CTRL_EWMEN (1U) //!< Bit field size in bits for EWM_CTRL_EWMEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the EWM_CTRL_EWMEN field.
+#define BR_EWM_CTRL_EWMEN (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_EWMEN))
+#endif
+
+//! @brief Format value for bitfield EWM_CTRL_EWMEN.
+#define BF_EWM_CTRL_EWMEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CTRL_EWMEN), uint8_t) & BM_EWM_CTRL_EWMEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EWMEN field to a new value.
+#define BW_EWM_CTRL_EWMEN(v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_EWMEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register EWM_CTRL, field ASSIN[1] (RW)
+ *
+ * Default assert state of the EWM_in signal is logic zero. Setting ASSIN bit
+ * inverts the assert state to a logic one.
+ */
+//@{
+#define BP_EWM_CTRL_ASSIN (1U) //!< Bit position for EWM_CTRL_ASSIN.
+#define BM_EWM_CTRL_ASSIN (0x02U) //!< Bit mask for EWM_CTRL_ASSIN.
+#define BS_EWM_CTRL_ASSIN (1U) //!< Bit field size in bits for EWM_CTRL_ASSIN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the EWM_CTRL_ASSIN field.
+#define BR_EWM_CTRL_ASSIN (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_ASSIN))
+#endif
+
+//! @brief Format value for bitfield EWM_CTRL_ASSIN.
+#define BF_EWM_CTRL_ASSIN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CTRL_ASSIN), uint8_t) & BM_EWM_CTRL_ASSIN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ASSIN field to a new value.
+#define BW_EWM_CTRL_ASSIN(v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_ASSIN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register EWM_CTRL, field INEN[2] (RW)
+ *
+ * This bit when set, enables the EWM_in port.
+ */
+//@{
+#define BP_EWM_CTRL_INEN (2U) //!< Bit position for EWM_CTRL_INEN.
+#define BM_EWM_CTRL_INEN (0x04U) //!< Bit mask for EWM_CTRL_INEN.
+#define BS_EWM_CTRL_INEN (1U) //!< Bit field size in bits for EWM_CTRL_INEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the EWM_CTRL_INEN field.
+#define BR_EWM_CTRL_INEN (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_INEN))
+#endif
+
+//! @brief Format value for bitfield EWM_CTRL_INEN.
+#define BF_EWM_CTRL_INEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CTRL_INEN), uint8_t) & BM_EWM_CTRL_INEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INEN field to a new value.
+#define BW_EWM_CTRL_INEN(v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_INEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register EWM_CTRL, field INTEN[3] (RW)
+ *
+ * This bit when set and EWM_out is asserted, an interrupt request is generated.
+ * To de-assert interrupt request, user should clear this bit by writing 0.
+ */
+//@{
+#define BP_EWM_CTRL_INTEN (3U) //!< Bit position for EWM_CTRL_INTEN.
+#define BM_EWM_CTRL_INTEN (0x08U) //!< Bit mask for EWM_CTRL_INTEN.
+#define BS_EWM_CTRL_INTEN (1U) //!< Bit field size in bits for EWM_CTRL_INTEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the EWM_CTRL_INTEN field.
+#define BR_EWM_CTRL_INTEN (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_INTEN))
+#endif
+
+//! @brief Format value for bitfield EWM_CTRL_INTEN.
+#define BF_EWM_CTRL_INTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CTRL_INTEN), uint8_t) & BM_EWM_CTRL_INTEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INTEN field to a new value.
+#define BW_EWM_CTRL_INTEN(v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR, BP_EWM_CTRL_INTEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_EWM_SERV - Service Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_EWM_SERV - Service Register (WORZ)
+ *
+ * Reset value: 0x00U
+ *
+ * The SERV register provides the interface from the CPU to the EWM module. It
+ * is write-only and reads of this register return zero.
+ */
+typedef union _hw_ewm_serv
+{
+ uint8_t U;
+ struct _hw_ewm_serv_bitfields
+ {
+ uint8_t SERVICE : 8; //!< [7:0]
+ } B;
+} hw_ewm_serv_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire EWM_SERV register
+ */
+//@{
+#define HW_EWM_SERV_ADDR (REGS_EWM_BASE + 0x1U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_EWM_SERV (*(__O hw_ewm_serv_t *) HW_EWM_SERV_ADDR)
+#define HW_EWM_SERV_RD() (HW_EWM_SERV.U)
+#define HW_EWM_SERV_WR(v) (HW_EWM_SERV.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual EWM_SERV bitfields
+ */
+
+/*!
+ * @name Register EWM_SERV, field SERVICE[7:0] (WORZ)
+ *
+ * The EWM service mechanism requires the CPU to write two values to the SERV
+ * register: a first data byte of 0xB4, followed by a second data byte of 0x2C. The
+ * EWM service is illegal if either of the following conditions is true. The
+ * first or second data byte is not written correctly. The second data byte is not
+ * written within a fixed number of peripheral bus cycles of the first data byte.
+ * This fixed number of cycles is called EWM_service_time.
+ */
+//@{
+#define BP_EWM_SERV_SERVICE (0U) //!< Bit position for EWM_SERV_SERVICE.
+#define BM_EWM_SERV_SERVICE (0xFFU) //!< Bit mask for EWM_SERV_SERVICE.
+#define BS_EWM_SERV_SERVICE (8U) //!< Bit field size in bits for EWM_SERV_SERVICE.
+
+//! @brief Format value for bitfield EWM_SERV_SERVICE.
+#define BF_EWM_SERV_SERVICE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_SERV_SERVICE), uint8_t) & BM_EWM_SERV_SERVICE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SERVICE field to a new value.
+#define BW_EWM_SERV_SERVICE(v) (HW_EWM_SERV_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_EWM_CMPL - Compare Low Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_EWM_CMPL - Compare Low Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The CMPL register is reset to zero after a CPU reset. This provides no
+ * minimum time for the CPU to service the EWM counter. This register can be written
+ * only once after a CPU reset. Writing this register more than once generates a
+ * bus transfer error.
+ */
+typedef union _hw_ewm_cmpl
+{
+ uint8_t U;
+ struct _hw_ewm_cmpl_bitfields
+ {
+ uint8_t COMPAREL : 8; //!< [7:0]
+ } B;
+} hw_ewm_cmpl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire EWM_CMPL register
+ */
+//@{
+#define HW_EWM_CMPL_ADDR (REGS_EWM_BASE + 0x2U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_EWM_CMPL (*(__IO hw_ewm_cmpl_t *) HW_EWM_CMPL_ADDR)
+#define HW_EWM_CMPL_RD() (HW_EWM_CMPL.U)
+#define HW_EWM_CMPL_WR(v) (HW_EWM_CMPL.U = (v))
+#define HW_EWM_CMPL_SET(v) (HW_EWM_CMPL_WR(HW_EWM_CMPL_RD() | (v)))
+#define HW_EWM_CMPL_CLR(v) (HW_EWM_CMPL_WR(HW_EWM_CMPL_RD() & ~(v)))
+#define HW_EWM_CMPL_TOG(v) (HW_EWM_CMPL_WR(HW_EWM_CMPL_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual EWM_CMPL bitfields
+ */
+
+/*!
+ * @name Register EWM_CMPL, field COMPAREL[7:0] (RW)
+ *
+ * To prevent runaway code from changing this field, software should write to
+ * this field after a CPU reset even if the (default) minimum service time is
+ * required.
+ */
+//@{
+#define BP_EWM_CMPL_COMPAREL (0U) //!< Bit position for EWM_CMPL_COMPAREL.
+#define BM_EWM_CMPL_COMPAREL (0xFFU) //!< Bit mask for EWM_CMPL_COMPAREL.
+#define BS_EWM_CMPL_COMPAREL (8U) //!< Bit field size in bits for EWM_CMPL_COMPAREL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the EWM_CMPL_COMPAREL field.
+#define BR_EWM_CMPL_COMPAREL (HW_EWM_CMPL.U)
+#endif
+
+//! @brief Format value for bitfield EWM_CMPL_COMPAREL.
+#define BF_EWM_CMPL_COMPAREL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CMPL_COMPAREL), uint8_t) & BM_EWM_CMPL_COMPAREL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COMPAREL field to a new value.
+#define BW_EWM_CMPL_COMPAREL(v) (HW_EWM_CMPL_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_EWM_CMPH - Compare High Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_EWM_CMPH - Compare High Register (RW)
+ *
+ * Reset value: 0xFFU
+ *
+ * The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum
+ * of 256 clocks time, for the CPU to service the EWM counter. This register can
+ * be written only once after a CPU reset. Writing this register more than once
+ * generates a bus transfer error. The valid values for CMPH are up to 0xFE
+ * because the EWM counter never expires when CMPH = 0xFF. The expiration happens only
+ * if EWM counter is greater than CMPH.
+ */
+typedef union _hw_ewm_cmph
+{
+ uint8_t U;
+ struct _hw_ewm_cmph_bitfields
+ {
+ uint8_t COMPAREH : 8; //!< [7:0]
+ } B;
+} hw_ewm_cmph_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire EWM_CMPH register
+ */
+//@{
+#define HW_EWM_CMPH_ADDR (REGS_EWM_BASE + 0x3U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_EWM_CMPH (*(__IO hw_ewm_cmph_t *) HW_EWM_CMPH_ADDR)
+#define HW_EWM_CMPH_RD() (HW_EWM_CMPH.U)
+#define HW_EWM_CMPH_WR(v) (HW_EWM_CMPH.U = (v))
+#define HW_EWM_CMPH_SET(v) (HW_EWM_CMPH_WR(HW_EWM_CMPH_RD() | (v)))
+#define HW_EWM_CMPH_CLR(v) (HW_EWM_CMPH_WR(HW_EWM_CMPH_RD() & ~(v)))
+#define HW_EWM_CMPH_TOG(v) (HW_EWM_CMPH_WR(HW_EWM_CMPH_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual EWM_CMPH bitfields
+ */
+
+/*!
+ * @name Register EWM_CMPH, field COMPAREH[7:0] (RW)
+ *
+ * To prevent runaway code from changing this field, software should write to
+ * this field after a CPU reset even if the (default) maximum service time is
+ * required.
+ */
+//@{
+#define BP_EWM_CMPH_COMPAREH (0U) //!< Bit position for EWM_CMPH_COMPAREH.
+#define BM_EWM_CMPH_COMPAREH (0xFFU) //!< Bit mask for EWM_CMPH_COMPAREH.
+#define BS_EWM_CMPH_COMPAREH (8U) //!< Bit field size in bits for EWM_CMPH_COMPAREH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the EWM_CMPH_COMPAREH field.
+#define BR_EWM_CMPH_COMPAREH (HW_EWM_CMPH.U)
+#endif
+
+//! @brief Format value for bitfield EWM_CMPH_COMPAREH.
+#define BF_EWM_CMPH_COMPAREH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_EWM_CMPH_COMPAREH), uint8_t) & BM_EWM_CMPH_COMPAREH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COMPAREH field to a new value.
+#define BW_EWM_CMPH_COMPAREH(v) (HW_EWM_CMPH_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_ewm_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All EWM module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_ewm
+{
+ __IO hw_ewm_ctrl_t CTRL; //!< [0x0] Control Register
+ __O hw_ewm_serv_t SERV; //!< [0x1] Service Register
+ __IO hw_ewm_cmpl_t CMPL; //!< [0x2] Compare Low Register
+ __IO hw_ewm_cmph_t CMPH; //!< [0x3] Compare High Register
+} hw_ewm_t;
+#pragma pack()
+
+//! @brief Macro to access all EWM registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_EWM</code>.
+#define HW_EWM (*(hw_ewm_t *) REGS_EWM_BASE)
+#endif
+
+#endif // __HW_EWM_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_fb.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,959 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_FB_REGISTERS_H__
+#define __HW_FB_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 FB
+ *
+ * FlexBus external bus interface
+ *
+ * Registers defined in this header file:
+ * - HW_FB_CSARn - Chip Select Address Register
+ * - HW_FB_CSMRn - Chip Select Mask Register
+ * - HW_FB_CSCRn - Chip Select Control Register
+ * - HW_FB_CSPMCR - Chip Select port Multiplexing Control Register
+ *
+ * - hw_fb_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_FB_BASE
+#define HW_FB_INSTANCE_COUNT (1U) //!< Number of instances of the FB module.
+#define REGS_FB_BASE (0x4000C000U) //!< Base address for FB.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FB_CSARn - Chip Select Address Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FB_CSARn - Chip Select Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies the associated chip-select's base address.
+ */
+typedef union _hw_fb_csarn
+{
+ uint32_t U;
+ struct _hw_fb_csarn_bitfields
+ {
+ uint32_t RESERVED0 : 16; //!< [15:0]
+ uint32_t BA : 16; //!< [31:16] Base Address
+ } B;
+} hw_fb_csarn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FB_CSARn register
+ */
+//@{
+#define HW_FB_CSARn_COUNT (6U)
+
+#define HW_FB_CSARn_ADDR(n) (REGS_FB_BASE + 0x0U + (0xCU * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FB_CSARn(n) (*(__IO hw_fb_csarn_t *) HW_FB_CSARn_ADDR(n))
+#define HW_FB_CSARn_RD(n) (HW_FB_CSARn(n).U)
+#define HW_FB_CSARn_WR(n, v) (HW_FB_CSARn(n).U = (v))
+#define HW_FB_CSARn_SET(n, v) (HW_FB_CSARn_WR(n, HW_FB_CSARn_RD(n) | (v)))
+#define HW_FB_CSARn_CLR(n, v) (HW_FB_CSARn_WR(n, HW_FB_CSARn_RD(n) & ~(v)))
+#define HW_FB_CSARn_TOG(n, v) (HW_FB_CSARn_WR(n, HW_FB_CSARn_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FB_CSARn bitfields
+ */
+
+/*!
+ * @name Register FB_CSARn, field BA[31:16] (RW)
+ *
+ * Defines the base address for memory dedicated to the associated chip-select.
+ * BA is compared to bits 31-16 on the internal address bus to determine if the
+ * associated chip-select's memory is being accessed. Because the FlexBus module
+ * is one of the slaves connected to the crossbar switch, it is only accessible
+ * within a certain memory range. See the chip memory map for the applicable
+ * FlexBus "expansion" address range for which the chip-selects can be active. Set the
+ * CSARn and CSMRn registers appropriately before accessing this region.
+ */
+//@{
+#define BP_FB_CSARn_BA (16U) //!< Bit position for FB_CSARn_BA.
+#define BM_FB_CSARn_BA (0xFFFF0000U) //!< Bit mask for FB_CSARn_BA.
+#define BS_FB_CSARn_BA (16U) //!< Bit field size in bits for FB_CSARn_BA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSARn_BA field.
+#define BR_FB_CSARn_BA(n) (HW_FB_CSARn(n).B.BA)
+#endif
+
+//! @brief Format value for bitfield FB_CSARn_BA.
+#define BF_FB_CSARn_BA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSARn_BA), uint32_t) & BM_FB_CSARn_BA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BA field to a new value.
+#define BW_FB_CSARn_BA(n, v) (HW_FB_CSARn_WR(n, (HW_FB_CSARn_RD(n) & ~BM_FB_CSARn_BA) | BF_FB_CSARn_BA(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_FB_CSMRn - Chip Select Mask Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FB_CSMRn - Chip Select Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies the address mask and allowable access types for the associated
+ * chip-select.
+ */
+typedef union _hw_fb_csmrn
+{
+ uint32_t U;
+ struct _hw_fb_csmrn_bitfields
+ {
+ uint32_t V : 1; //!< [0] Valid
+ uint32_t RESERVED0 : 7; //!< [7:1]
+ uint32_t WP : 1; //!< [8] Write Protect
+ uint32_t RESERVED1 : 7; //!< [15:9]
+ uint32_t BAM : 16; //!< [31:16] Base Address Mask
+ } B;
+} hw_fb_csmrn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FB_CSMRn register
+ */
+//@{
+#define HW_FB_CSMRn_COUNT (6U)
+
+#define HW_FB_CSMRn_ADDR(n) (REGS_FB_BASE + 0x4U + (0xCU * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FB_CSMRn(n) (*(__IO hw_fb_csmrn_t *) HW_FB_CSMRn_ADDR(n))
+#define HW_FB_CSMRn_RD(n) (HW_FB_CSMRn(n).U)
+#define HW_FB_CSMRn_WR(n, v) (HW_FB_CSMRn(n).U = (v))
+#define HW_FB_CSMRn_SET(n, v) (HW_FB_CSMRn_WR(n, HW_FB_CSMRn_RD(n) | (v)))
+#define HW_FB_CSMRn_CLR(n, v) (HW_FB_CSMRn_WR(n, HW_FB_CSMRn_RD(n) & ~(v)))
+#define HW_FB_CSMRn_TOG(n, v) (HW_FB_CSMRn_WR(n, HW_FB_CSMRn_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FB_CSMRn bitfields
+ */
+
+/*!
+ * @name Register FB_CSMRn, field V[0] (RW)
+ *
+ * Specifies whether the corresponding CSAR, CSMR, and CSCR contents are valid.
+ * Programmed chip-selects do not assert until the V bit is 1b (except for
+ * FB_CS0, which acts as the global chip-select). At reset, FB_CS0 will fire for any
+ * access to the FlexBus memory region. CSMR0[V] must be set as part of the chip
+ * select initialization sequence to allow other chip selects to function as
+ * programmed.
+ *
+ * Values:
+ * - 0 - Chip-select is invalid.
+ * - 1 - Chip-select is valid.
+ */
+//@{
+#define BP_FB_CSMRn_V (0U) //!< Bit position for FB_CSMRn_V.
+#define BM_FB_CSMRn_V (0x00000001U) //!< Bit mask for FB_CSMRn_V.
+#define BS_FB_CSMRn_V (1U) //!< Bit field size in bits for FB_CSMRn_V.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSMRn_V field.
+#define BR_FB_CSMRn_V(n) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(n), BP_FB_CSMRn_V))
+#endif
+
+//! @brief Format value for bitfield FB_CSMRn_V.
+#define BF_FB_CSMRn_V(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSMRn_V), uint32_t) & BM_FB_CSMRn_V)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the V field to a new value.
+#define BW_FB_CSMRn_V(n, v) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(n), BP_FB_CSMRn_V) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSMRn, field WP[8] (RW)
+ *
+ * Controls write accesses to the address range in the corresponding CSAR.
+ *
+ * Values:
+ * - 0 - Write accesses are allowed.
+ * - 1 - Write accesses are not allowed. Attempting to write to the range of
+ * addresses for which the WP bit is set results in a bus error termination of
+ * the internal cycle and no external cycle.
+ */
+//@{
+#define BP_FB_CSMRn_WP (8U) //!< Bit position for FB_CSMRn_WP.
+#define BM_FB_CSMRn_WP (0x00000100U) //!< Bit mask for FB_CSMRn_WP.
+#define BS_FB_CSMRn_WP (1U) //!< Bit field size in bits for FB_CSMRn_WP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSMRn_WP field.
+#define BR_FB_CSMRn_WP(n) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(n), BP_FB_CSMRn_WP))
+#endif
+
+//! @brief Format value for bitfield FB_CSMRn_WP.
+#define BF_FB_CSMRn_WP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSMRn_WP), uint32_t) & BM_FB_CSMRn_WP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WP field to a new value.
+#define BW_FB_CSMRn_WP(n, v) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(n), BP_FB_CSMRn_WP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSMRn, field BAM[31:16] (RW)
+ *
+ * Defines the associated chip-select's block size by masking address bits.
+ *
+ * Values:
+ * - 0 - The corresponding address bit in CSAR is used in the chip-select decode.
+ * - 1 - The corresponding address bit in CSAR is a don't care in the
+ * chip-select decode.
+ */
+//@{
+#define BP_FB_CSMRn_BAM (16U) //!< Bit position for FB_CSMRn_BAM.
+#define BM_FB_CSMRn_BAM (0xFFFF0000U) //!< Bit mask for FB_CSMRn_BAM.
+#define BS_FB_CSMRn_BAM (16U) //!< Bit field size in bits for FB_CSMRn_BAM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSMRn_BAM field.
+#define BR_FB_CSMRn_BAM(n) (HW_FB_CSMRn(n).B.BAM)
+#endif
+
+//! @brief Format value for bitfield FB_CSMRn_BAM.
+#define BF_FB_CSMRn_BAM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSMRn_BAM), uint32_t) & BM_FB_CSMRn_BAM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BAM field to a new value.
+#define BW_FB_CSMRn_BAM(n, v) (HW_FB_CSMRn_WR(n, (HW_FB_CSMRn_RD(n) & ~BM_FB_CSMRn_BAM) | BF_FB_CSMRn_BAM(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_FB_CSCRn - Chip Select Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FB_CSCRn - Chip Select Control Register (RW)
+ *
+ * Reset value: 0x003FFC00U
+ *
+ * Controls the auto-acknowledge, address setup and hold times, port size, burst
+ * capability, and number of wait states for the associated chip select. To
+ * support the global chip-select (FB_CS0), the CSCR0 reset values differ from the
+ * other CSCRs. The reset value of CSCR0 is as follows: Bits 31-24 are 0b Bit 23-3
+ * are chip-dependent Bits 3-0 are 0b See the chip configuration details for your
+ * particular chip for information on the exact CSCR0 reset value.
+ */
+typedef union _hw_fb_cscrn
+{
+ uint32_t U;
+ struct _hw_fb_cscrn_bitfields
+ {
+ uint32_t RESERVED0 : 3; //!< [2:0]
+ uint32_t BSTW : 1; //!< [3] Burst-Write Enable
+ uint32_t BSTR : 1; //!< [4] Burst-Read Enable
+ uint32_t BEM : 1; //!< [5] Byte-Enable Mode
+ uint32_t PS : 2; //!< [7:6] Port Size
+ uint32_t AA : 1; //!< [8] Auto-Acknowledge Enable
+ uint32_t BLS : 1; //!< [9] Byte-Lane Shift
+ uint32_t WS : 6; //!< [15:10] Wait States
+ uint32_t WRAH : 2; //!< [17:16] Write Address Hold or Deselect
+ uint32_t RDAH : 2; //!< [19:18] Read Address Hold or Deselect
+ uint32_t ASET : 2; //!< [21:20] Address Setup
+ uint32_t EXTS : 1; //!< [22]
+ uint32_t SWSEN : 1; //!< [23] Secondary Wait State Enable
+ uint32_t RESERVED1 : 2; //!< [25:24]
+ uint32_t SWS : 6; //!< [31:26] Secondary Wait States
+ } B;
+} hw_fb_cscrn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FB_CSCRn register
+ */
+//@{
+#define HW_FB_CSCRn_COUNT (6U)
+
+#define HW_FB_CSCRn_ADDR(n) (REGS_FB_BASE + 0x8U + (0xCU * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FB_CSCRn(n) (*(__IO hw_fb_cscrn_t *) HW_FB_CSCRn_ADDR(n))
+#define HW_FB_CSCRn_RD(n) (HW_FB_CSCRn(n).U)
+#define HW_FB_CSCRn_WR(n, v) (HW_FB_CSCRn(n).U = (v))
+#define HW_FB_CSCRn_SET(n, v) (HW_FB_CSCRn_WR(n, HW_FB_CSCRn_RD(n) | (v)))
+#define HW_FB_CSCRn_CLR(n, v) (HW_FB_CSCRn_WR(n, HW_FB_CSCRn_RD(n) & ~(v)))
+#define HW_FB_CSCRn_TOG(n, v) (HW_FB_CSCRn_WR(n, HW_FB_CSCRn_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FB_CSCRn bitfields
+ */
+
+/*!
+ * @name Register FB_CSCRn, field BSTW[3] (RW)
+ *
+ * Specifies whether burst writes are enabled for memory associated with each
+ * chip select.
+ *
+ * Values:
+ * - 0 - Disabled. Data exceeding the specified port size is broken into
+ * individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit
+ * port takes four byte writes.
+ * - 1 - Enabled. Enables burst write of data larger than the specified port
+ * size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit
+ * ports, and line writes to 8-, 16-, and 32-bit ports.
+ */
+//@{
+#define BP_FB_CSCRn_BSTW (3U) //!< Bit position for FB_CSCRn_BSTW.
+#define BM_FB_CSCRn_BSTW (0x00000008U) //!< Bit mask for FB_CSCRn_BSTW.
+#define BS_FB_CSCRn_BSTW (1U) //!< Bit field size in bits for FB_CSCRn_BSTW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSCRn_BSTW field.
+#define BR_FB_CSCRn_BSTW(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BSTW))
+#endif
+
+//! @brief Format value for bitfield FB_CSCRn_BSTW.
+#define BF_FB_CSCRn_BSTW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_BSTW), uint32_t) & BM_FB_CSCRn_BSTW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BSTW field to a new value.
+#define BW_FB_CSCRn_BSTW(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BSTW) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSCRn, field BSTR[4] (RW)
+ *
+ * Specifies whether burst reads are enabled for memory associated with each
+ * chip select.
+ *
+ * Values:
+ * - 0 - Disabled. Data exceeding the specified port size is broken into
+ * individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit
+ * port is broken into four 8-bit reads.
+ * - 1 - Enabled. Enables data burst reads larger than the specified port size,
+ * including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit
+ * ports, and line reads from 8-, 16-, and 32-bit ports.
+ */
+//@{
+#define BP_FB_CSCRn_BSTR (4U) //!< Bit position for FB_CSCRn_BSTR.
+#define BM_FB_CSCRn_BSTR (0x00000010U) //!< Bit mask for FB_CSCRn_BSTR.
+#define BS_FB_CSCRn_BSTR (1U) //!< Bit field size in bits for FB_CSCRn_BSTR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSCRn_BSTR field.
+#define BR_FB_CSCRn_BSTR(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BSTR))
+#endif
+
+//! @brief Format value for bitfield FB_CSCRn_BSTR.
+#define BF_FB_CSCRn_BSTR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_BSTR), uint32_t) & BM_FB_CSCRn_BSTR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BSTR field to a new value.
+#define BW_FB_CSCRn_BSTR(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BSTR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSCRn, field BEM[5] (RW)
+ *
+ * Specifies whether the corresponding FB_BE is asserted for read accesses.
+ * Certain memories have byte enables that must be asserted during reads and writes.
+ * Write 1b to the BEM bit in the relevant CSCR to provide the appropriate mode
+ * of byte enable support for these SRAMs.
+ *
+ * Values:
+ * - 0 - FB_BE is asserted for data write only.
+ * - 1 - FB_BE is asserted for data read and write accesses.
+ */
+//@{
+#define BP_FB_CSCRn_BEM (5U) //!< Bit position for FB_CSCRn_BEM.
+#define BM_FB_CSCRn_BEM (0x00000020U) //!< Bit mask for FB_CSCRn_BEM.
+#define BS_FB_CSCRn_BEM (1U) //!< Bit field size in bits for FB_CSCRn_BEM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSCRn_BEM field.
+#define BR_FB_CSCRn_BEM(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BEM))
+#endif
+
+//! @brief Format value for bitfield FB_CSCRn_BEM.
+#define BF_FB_CSCRn_BEM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_BEM), uint32_t) & BM_FB_CSCRn_BEM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BEM field to a new value.
+#define BW_FB_CSCRn_BEM(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BEM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSCRn, field PS[7:6] (RW)
+ *
+ * Specifies the data port width of the associated chip-select, and determines
+ * where data is driven during write cycles and where data is sampled during read
+ * cycles.
+ *
+ * Values:
+ * - 00 - 32-bit port size. Valid data is sampled and driven on FB_D[31:0].
+ * - 01 - 8-bit port size. Valid data is sampled and driven on FB_D[31:24] when
+ * BLS is 0b, or FB_D[7:0] when BLS is 1b.
+ */
+//@{
+#define BP_FB_CSCRn_PS (6U) //!< Bit position for FB_CSCRn_PS.
+#define BM_FB_CSCRn_PS (0x000000C0U) //!< Bit mask for FB_CSCRn_PS.
+#define BS_FB_CSCRn_PS (2U) //!< Bit field size in bits for FB_CSCRn_PS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSCRn_PS field.
+#define BR_FB_CSCRn_PS(n) (HW_FB_CSCRn(n).B.PS)
+#endif
+
+//! @brief Format value for bitfield FB_CSCRn_PS.
+#define BF_FB_CSCRn_PS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_PS), uint32_t) & BM_FB_CSCRn_PS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PS field to a new value.
+#define BW_FB_CSCRn_PS(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_PS) | BF_FB_CSCRn_PS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSCRn, field AA[8] (RW)
+ *
+ * Asserts the internal transfer acknowledge for accesses specified by the
+ * chip-select address. If AA is 1b for a corresponding FB_CSn and the external system
+ * asserts an external FB_TA before the wait-state countdown asserts the
+ * internal FB_TA, the cycle is terminated. Burst cycles increment the address bus
+ * between each internal termination. This field must be 1b if CSPMCR disables FB_TA.
+ *
+ * Values:
+ * - 0 - Disabled. No internal transfer acknowledge is asserted and the cycle is
+ * terminated externally.
+ * - 1 - Enabled. Internal transfer acknowledge is asserted as specified by WS.
+ */
+//@{
+#define BP_FB_CSCRn_AA (8U) //!< Bit position for FB_CSCRn_AA.
+#define BM_FB_CSCRn_AA (0x00000100U) //!< Bit mask for FB_CSCRn_AA.
+#define BS_FB_CSCRn_AA (1U) //!< Bit field size in bits for FB_CSCRn_AA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSCRn_AA field.
+#define BR_FB_CSCRn_AA(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_AA))
+#endif
+
+//! @brief Format value for bitfield FB_CSCRn_AA.
+#define BF_FB_CSCRn_AA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_AA), uint32_t) & BM_FB_CSCRn_AA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AA field to a new value.
+#define BW_FB_CSCRn_AA(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_AA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSCRn, field BLS[9] (RW)
+ *
+ * Specifies if data on FB_AD appears left-aligned or right-aligned during the
+ * data phase of a FlexBus access.
+ *
+ * Values:
+ * - 0 - Not shifted. Data is left-aligned on FB_AD.
+ * - 1 - Shifted. Data is right-aligned on FB_AD.
+ */
+//@{
+#define BP_FB_CSCRn_BLS (9U) //!< Bit position for FB_CSCRn_BLS.
+#define BM_FB_CSCRn_BLS (0x00000200U) //!< Bit mask for FB_CSCRn_BLS.
+#define BS_FB_CSCRn_BLS (1U) //!< Bit field size in bits for FB_CSCRn_BLS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSCRn_BLS field.
+#define BR_FB_CSCRn_BLS(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BLS))
+#endif
+
+//! @brief Format value for bitfield FB_CSCRn_BLS.
+#define BF_FB_CSCRn_BLS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_BLS), uint32_t) & BM_FB_CSCRn_BLS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BLS field to a new value.
+#define BW_FB_CSCRn_BLS(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BLS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSCRn, field WS[15:10] (RW)
+ *
+ * Specifies the number of wait states inserted after FlexBus asserts the
+ * associated chip-select and before an internal transfer acknowledge is generated (WS
+ * = 00h inserts 0 wait states, ..., WS = 3Fh inserts 63 wait states).
+ */
+//@{
+#define BP_FB_CSCRn_WS (10U) //!< Bit position for FB_CSCRn_WS.
+#define BM_FB_CSCRn_WS (0x0000FC00U) //!< Bit mask for FB_CSCRn_WS.
+#define BS_FB_CSCRn_WS (6U) //!< Bit field size in bits for FB_CSCRn_WS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSCRn_WS field.
+#define BR_FB_CSCRn_WS(n) (HW_FB_CSCRn(n).B.WS)
+#endif
+
+//! @brief Format value for bitfield FB_CSCRn_WS.
+#define BF_FB_CSCRn_WS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_WS), uint32_t) & BM_FB_CSCRn_WS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WS field to a new value.
+#define BW_FB_CSCRn_WS(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_WS) | BF_FB_CSCRn_WS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSCRn, field WRAH[17:16] (RW)
+ *
+ * Controls the address, data, and attribute hold time after the termination of
+ * a write cycle that hits in the associated chip-select's address space. The
+ * hold time applies only at the end of a transfer. Therefore, during a burst
+ * transfer or a transfer to a port size smaller than the transfer size, the hold time
+ * is only added after the last bus cycle.
+ *
+ * Values:
+ * - 00 - 1 cycle (default for all but FB_CS0 )
+ * - 01 - 2 cycles
+ * - 10 - 3 cycles
+ * - 11 - 4 cycles (default for FB_CS0 )
+ */
+//@{
+#define BP_FB_CSCRn_WRAH (16U) //!< Bit position for FB_CSCRn_WRAH.
+#define BM_FB_CSCRn_WRAH (0x00030000U) //!< Bit mask for FB_CSCRn_WRAH.
+#define BS_FB_CSCRn_WRAH (2U) //!< Bit field size in bits for FB_CSCRn_WRAH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSCRn_WRAH field.
+#define BR_FB_CSCRn_WRAH(n) (HW_FB_CSCRn(n).B.WRAH)
+#endif
+
+//! @brief Format value for bitfield FB_CSCRn_WRAH.
+#define BF_FB_CSCRn_WRAH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_WRAH), uint32_t) & BM_FB_CSCRn_WRAH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WRAH field to a new value.
+#define BW_FB_CSCRn_WRAH(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_WRAH) | BF_FB_CSCRn_WRAH(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSCRn, field RDAH[19:18] (RW)
+ *
+ * Controls the address and attribute hold time after the termination during a
+ * read cycle that hits in the associated chip-select's address space. The hold
+ * time applies only at the end of a transfer. Therefore, during a burst transfer
+ * or a transfer to a port size smaller than the transfer size, the hold time is
+ * only added after the last bus cycle. The number of cycles the address and
+ * attributes are held after FB_CSn deassertion depends on the value of the AA bit.
+ *
+ * Values:
+ * - 00 - When AA is 0b, 1 cycle. When AA is 1b, 0 cycles.
+ * - 01 - When AA is 0b, 2 cycles. When AA is 1b, 1 cycle.
+ * - 10 - When AA is 0b, 3 cycles. When AA is 1b, 2 cycles.
+ * - 11 - When AA is 0b, 4 cycles. When AA is 1b, 3 cycles.
+ */
+//@{
+#define BP_FB_CSCRn_RDAH (18U) //!< Bit position for FB_CSCRn_RDAH.
+#define BM_FB_CSCRn_RDAH (0x000C0000U) //!< Bit mask for FB_CSCRn_RDAH.
+#define BS_FB_CSCRn_RDAH (2U) //!< Bit field size in bits for FB_CSCRn_RDAH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSCRn_RDAH field.
+#define BR_FB_CSCRn_RDAH(n) (HW_FB_CSCRn(n).B.RDAH)
+#endif
+
+//! @brief Format value for bitfield FB_CSCRn_RDAH.
+#define BF_FB_CSCRn_RDAH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_RDAH), uint32_t) & BM_FB_CSCRn_RDAH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RDAH field to a new value.
+#define BW_FB_CSCRn_RDAH(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_RDAH) | BF_FB_CSCRn_RDAH(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSCRn, field ASET[21:20] (RW)
+ *
+ * Controls when the chip-select is asserted with respect to assertion of a
+ * valid address and attributes.
+ *
+ * Values:
+ * - 00 - Assert FB_CSn on the first rising clock edge after the address is
+ * asserted (default for all but FB_CS0 ).
+ * - 01 - Assert FB_CSn on the second rising clock edge after the address is
+ * asserted.
+ * - 10 - Assert FB_CSn on the third rising clock edge after the address is
+ * asserted.
+ * - 11 - Assert FB_CSn on the fourth rising clock edge after the address is
+ * asserted (default for FB_CS0 ).
+ */
+//@{
+#define BP_FB_CSCRn_ASET (20U) //!< Bit position for FB_CSCRn_ASET.
+#define BM_FB_CSCRn_ASET (0x00300000U) //!< Bit mask for FB_CSCRn_ASET.
+#define BS_FB_CSCRn_ASET (2U) //!< Bit field size in bits for FB_CSCRn_ASET.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSCRn_ASET field.
+#define BR_FB_CSCRn_ASET(n) (HW_FB_CSCRn(n).B.ASET)
+#endif
+
+//! @brief Format value for bitfield FB_CSCRn_ASET.
+#define BF_FB_CSCRn_ASET(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_ASET), uint32_t) & BM_FB_CSCRn_ASET)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ASET field to a new value.
+#define BW_FB_CSCRn_ASET(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_ASET) | BF_FB_CSCRn_ASET(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSCRn, field EXTS[22] (RW)
+ *
+ * Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS
+ * /FB_ALE is asserted.
+ *
+ * Values:
+ * - 0 - Disabled. FB_TS /FB_ALE asserts for one bus clock cycle.
+ * - 1 - Enabled. FB_TS /FB_ALE remains asserted until the first positive clock
+ * edge after FB_CSn asserts.
+ */
+//@{
+#define BP_FB_CSCRn_EXTS (22U) //!< Bit position for FB_CSCRn_EXTS.
+#define BM_FB_CSCRn_EXTS (0x00400000U) //!< Bit mask for FB_CSCRn_EXTS.
+#define BS_FB_CSCRn_EXTS (1U) //!< Bit field size in bits for FB_CSCRn_EXTS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSCRn_EXTS field.
+#define BR_FB_CSCRn_EXTS(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_EXTS))
+#endif
+
+//! @brief Format value for bitfield FB_CSCRn_EXTS.
+#define BF_FB_CSCRn_EXTS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_EXTS), uint32_t) & BM_FB_CSCRn_EXTS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EXTS field to a new value.
+#define BW_FB_CSCRn_EXTS(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_EXTS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSCRn, field SWSEN[23] (RW)
+ *
+ * Values:
+ * - 0 - Disabled. A number of wait states (specified by WS) are inserted before
+ * an internal transfer acknowledge is generated for all transfers.
+ * - 1 - Enabled. A number of wait states (specified by SWS) are inserted before
+ * an internal transfer acknowledge is generated for burst transfer
+ * secondary terminations.
+ */
+//@{
+#define BP_FB_CSCRn_SWSEN (23U) //!< Bit position for FB_CSCRn_SWSEN.
+#define BM_FB_CSCRn_SWSEN (0x00800000U) //!< Bit mask for FB_CSCRn_SWSEN.
+#define BS_FB_CSCRn_SWSEN (1U) //!< Bit field size in bits for FB_CSCRn_SWSEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSCRn_SWSEN field.
+#define BR_FB_CSCRn_SWSEN(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_SWSEN))
+#endif
+
+//! @brief Format value for bitfield FB_CSCRn_SWSEN.
+#define BF_FB_CSCRn_SWSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_SWSEN), uint32_t) & BM_FB_CSCRn_SWSEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SWSEN field to a new value.
+#define BW_FB_CSCRn_SWSEN(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_SWSEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSCRn, field SWS[31:26] (RW)
+ *
+ * Used only when the SWSEN bit is 1b. Specifies the number of wait states
+ * inserted before an internal transfer acknowledge is generated for a burst transfer
+ * (except for the first termination, which is controlled by WS).
+ */
+//@{
+#define BP_FB_CSCRn_SWS (26U) //!< Bit position for FB_CSCRn_SWS.
+#define BM_FB_CSCRn_SWS (0xFC000000U) //!< Bit mask for FB_CSCRn_SWS.
+#define BS_FB_CSCRn_SWS (6U) //!< Bit field size in bits for FB_CSCRn_SWS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSCRn_SWS field.
+#define BR_FB_CSCRn_SWS(n) (HW_FB_CSCRn(n).B.SWS)
+#endif
+
+//! @brief Format value for bitfield FB_CSCRn_SWS.
+#define BF_FB_CSCRn_SWS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_SWS), uint32_t) & BM_FB_CSCRn_SWS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SWS field to a new value.
+#define BW_FB_CSCRn_SWS(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_SWS) | BF_FB_CSCRn_SWS(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FB_CSPMCR - Chip Select port Multiplexing Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FB_CSPMCR - Chip Select port Multiplexing Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Controls the multiplexing of the FlexBus signals. A bus error occurs when you
+ * do any of the following: Write to a reserved address Write to a reserved
+ * field in this register, or Access this register using a size other than 32 bits.
+ */
+typedef union _hw_fb_cspmcr
+{
+ uint32_t U;
+ struct _hw_fb_cspmcr_bitfields
+ {
+ uint32_t RESERVED0 : 12; //!< [11:0]
+ uint32_t GROUP5 : 4; //!< [15:12] FlexBus Signal Group 5 Multiplex
+ //! control
+ uint32_t GROUP4 : 4; //!< [19:16] FlexBus Signal Group 4 Multiplex
+ //! control
+ uint32_t GROUP3 : 4; //!< [23:20] FlexBus Signal Group 3 Multiplex
+ //! control
+ uint32_t GROUP2 : 4; //!< [27:24] FlexBus Signal Group 2 Multiplex
+ //! control
+ uint32_t GROUP1 : 4; //!< [31:28] FlexBus Signal Group 1 Multiplex
+ //! control
+ } B;
+} hw_fb_cspmcr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FB_CSPMCR register
+ */
+//@{
+#define HW_FB_CSPMCR_ADDR (REGS_FB_BASE + 0x60U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FB_CSPMCR (*(__IO hw_fb_cspmcr_t *) HW_FB_CSPMCR_ADDR)
+#define HW_FB_CSPMCR_RD() (HW_FB_CSPMCR.U)
+#define HW_FB_CSPMCR_WR(v) (HW_FB_CSPMCR.U = (v))
+#define HW_FB_CSPMCR_SET(v) (HW_FB_CSPMCR_WR(HW_FB_CSPMCR_RD() | (v)))
+#define HW_FB_CSPMCR_CLR(v) (HW_FB_CSPMCR_WR(HW_FB_CSPMCR_RD() & ~(v)))
+#define HW_FB_CSPMCR_TOG(v) (HW_FB_CSPMCR_WR(HW_FB_CSPMCR_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FB_CSPMCR bitfields
+ */
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP5[15:12] (RW)
+ *
+ * Controls the multiplexing of the FB_TA , FB_CS3 , and FB_BE_7_0 signals. When
+ * GROUP5 is not 0000b, you must write 1b to the CSCR[AA] bit. Otherwise, the
+ * bus hangs during a transfer.
+ *
+ * Values:
+ * - 0000 - FB_TA
+ * - 0001 - FB_CS3 . You must also write 1b to CSCR[AA].
+ * - 0010 - FB_BE_7_0 . You must also write 1b to CSCR[AA].
+ */
+//@{
+#define BP_FB_CSPMCR_GROUP5 (12U) //!< Bit position for FB_CSPMCR_GROUP5.
+#define BM_FB_CSPMCR_GROUP5 (0x0000F000U) //!< Bit mask for FB_CSPMCR_GROUP5.
+#define BS_FB_CSPMCR_GROUP5 (4U) //!< Bit field size in bits for FB_CSPMCR_GROUP5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSPMCR_GROUP5 field.
+#define BR_FB_CSPMCR_GROUP5 (HW_FB_CSPMCR.B.GROUP5)
+#endif
+
+//! @brief Format value for bitfield FB_CSPMCR_GROUP5.
+#define BF_FB_CSPMCR_GROUP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP5), uint32_t) & BM_FB_CSPMCR_GROUP5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GROUP5 field to a new value.
+#define BW_FB_CSPMCR_GROUP5(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP5) | BF_FB_CSPMCR_GROUP5(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP4[19:16] (RW)
+ *
+ * Controls the multiplexing of the FB_TBST , FB_CS2 , and FB_BE_15_8 signals.
+ *
+ * Values:
+ * - 0000 - FB_TBST
+ * - 0001 - FB_CS2
+ * - 0010 - FB_BE_15_8
+ */
+//@{
+#define BP_FB_CSPMCR_GROUP4 (16U) //!< Bit position for FB_CSPMCR_GROUP4.
+#define BM_FB_CSPMCR_GROUP4 (0x000F0000U) //!< Bit mask for FB_CSPMCR_GROUP4.
+#define BS_FB_CSPMCR_GROUP4 (4U) //!< Bit field size in bits for FB_CSPMCR_GROUP4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSPMCR_GROUP4 field.
+#define BR_FB_CSPMCR_GROUP4 (HW_FB_CSPMCR.B.GROUP4)
+#endif
+
+//! @brief Format value for bitfield FB_CSPMCR_GROUP4.
+#define BF_FB_CSPMCR_GROUP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP4), uint32_t) & BM_FB_CSPMCR_GROUP4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GROUP4 field to a new value.
+#define BW_FB_CSPMCR_GROUP4(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP4) | BF_FB_CSPMCR_GROUP4(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP3[23:20] (RW)
+ *
+ * Controls the multiplexing of the FB_CS5 , FB_TSIZ1, and FB_BE_23_16 signals.
+ *
+ * Values:
+ * - 0000 - FB_CS5
+ * - 0001 - FB_TSIZ1
+ * - 0010 - FB_BE_23_16
+ */
+//@{
+#define BP_FB_CSPMCR_GROUP3 (20U) //!< Bit position for FB_CSPMCR_GROUP3.
+#define BM_FB_CSPMCR_GROUP3 (0x00F00000U) //!< Bit mask for FB_CSPMCR_GROUP3.
+#define BS_FB_CSPMCR_GROUP3 (4U) //!< Bit field size in bits for FB_CSPMCR_GROUP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSPMCR_GROUP3 field.
+#define BR_FB_CSPMCR_GROUP3 (HW_FB_CSPMCR.B.GROUP3)
+#endif
+
+//! @brief Format value for bitfield FB_CSPMCR_GROUP3.
+#define BF_FB_CSPMCR_GROUP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP3), uint32_t) & BM_FB_CSPMCR_GROUP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GROUP3 field to a new value.
+#define BW_FB_CSPMCR_GROUP3(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP3) | BF_FB_CSPMCR_GROUP3(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP2[27:24] (RW)
+ *
+ * Controls the multiplexing of the FB_CS4 , FB_TSIZ0, and FB_BE_31_24 signals.
+ *
+ * Values:
+ * - 0000 - FB_CS4
+ * - 0001 - FB_TSIZ0
+ * - 0010 - FB_BE_31_24
+ */
+//@{
+#define BP_FB_CSPMCR_GROUP2 (24U) //!< Bit position for FB_CSPMCR_GROUP2.
+#define BM_FB_CSPMCR_GROUP2 (0x0F000000U) //!< Bit mask for FB_CSPMCR_GROUP2.
+#define BS_FB_CSPMCR_GROUP2 (4U) //!< Bit field size in bits for FB_CSPMCR_GROUP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSPMCR_GROUP2 field.
+#define BR_FB_CSPMCR_GROUP2 (HW_FB_CSPMCR.B.GROUP2)
+#endif
+
+//! @brief Format value for bitfield FB_CSPMCR_GROUP2.
+#define BF_FB_CSPMCR_GROUP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP2), uint32_t) & BM_FB_CSPMCR_GROUP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GROUP2 field to a new value.
+#define BW_FB_CSPMCR_GROUP2(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP2) | BF_FB_CSPMCR_GROUP2(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP1[31:28] (RW)
+ *
+ * Controls the multiplexing of the FB_ALE, FB_CS1 , and FB_TS signals.
+ *
+ * Values:
+ * - 0000 - FB_ALE
+ * - 0001 - FB_CS1
+ * - 0010 - FB_TS
+ */
+//@{
+#define BP_FB_CSPMCR_GROUP1 (28U) //!< Bit position for FB_CSPMCR_GROUP1.
+#define BM_FB_CSPMCR_GROUP1 (0xF0000000U) //!< Bit mask for FB_CSPMCR_GROUP1.
+#define BS_FB_CSPMCR_GROUP1 (4U) //!< Bit field size in bits for FB_CSPMCR_GROUP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FB_CSPMCR_GROUP1 field.
+#define BR_FB_CSPMCR_GROUP1 (HW_FB_CSPMCR.B.GROUP1)
+#endif
+
+//! @brief Format value for bitfield FB_CSPMCR_GROUP1.
+#define BF_FB_CSPMCR_GROUP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP1), uint32_t) & BM_FB_CSPMCR_GROUP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GROUP1 field to a new value.
+#define BW_FB_CSPMCR_GROUP1(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP1) | BF_FB_CSPMCR_GROUP1(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_fb_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All FB module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_fb
+{
+ struct {
+ __IO hw_fb_csarn_t CSARn; //!< [0x0] Chip Select Address Register
+ __IO hw_fb_csmrn_t CSMRn; //!< [0x4] Chip Select Mask Register
+ __IO hw_fb_cscrn_t CSCRn; //!< [0x8] Chip Select Control Register
+ } CS[6];
+ uint8_t _reserved0[24];
+ __IO hw_fb_cspmcr_t CSPMCR; //!< [0x60] Chip Select port Multiplexing Control Register
+} hw_fb_t;
+#pragma pack()
+
+//! @brief Macro to access all FB registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_FB</code>.
+#define HW_FB (*(hw_fb_t *) REGS_FB_BASE)
+#endif
+
+#endif // __HW_FB_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_fmc.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,2177 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_FMC_REGISTERS_H__
+#define __HW_FMC_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 FMC
+ *
+ * Flash Memory Controller
+ *
+ * Registers defined in this header file:
+ * - HW_FMC_PFAPR - Flash Access Protection Register
+ * - HW_FMC_PFB0CR - Flash Bank 0 Control Register
+ * - HW_FMC_PFB1CR - Flash Bank 1 Control Register
+ * - HW_FMC_TAGVDW0Sn - Cache Tag Storage
+ * - HW_FMC_TAGVDW1Sn - Cache Tag Storage
+ * - HW_FMC_TAGVDW2Sn - Cache Tag Storage
+ * - HW_FMC_TAGVDW3Sn - Cache Tag Storage
+ * - HW_FMC_DATAW0SnU - Cache Data Storage (upper word)
+ * - HW_FMC_DATAW0SnL - Cache Data Storage (lower word)
+ * - HW_FMC_DATAW1SnU - Cache Data Storage (upper word)
+ * - HW_FMC_DATAW1SnL - Cache Data Storage (lower word)
+ * - HW_FMC_DATAW2SnU - Cache Data Storage (upper word)
+ * - HW_FMC_DATAW2SnL - Cache Data Storage (lower word)
+ * - HW_FMC_DATAW3SnU - Cache Data Storage (upper word)
+ * - HW_FMC_DATAW3SnL - Cache Data Storage (lower word)
+ *
+ * - hw_fmc_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_FMC_BASE
+#define HW_FMC_INSTANCE_COUNT (1U) //!< Number of instances of the FMC module.
+#define REGS_FMC_BASE (0x4001F000U) //!< Base address for FMC.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FMC_PFAPR - Flash Access Protection Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_PFAPR - Flash Access Protection Register (RW)
+ *
+ * Reset value: 0x00F8003FU
+ */
+typedef union _hw_fmc_pfapr
+{
+ uint32_t U;
+ struct _hw_fmc_pfapr_bitfields
+ {
+ uint32_t M0AP : 2; //!< [1:0] Master 0 Access Protection
+ uint32_t M1AP : 2; //!< [3:2] Master 1 Access Protection
+ uint32_t M2AP : 2; //!< [5:4] Master 2 Access Protection
+ uint32_t M3AP : 2; //!< [7:6] Master 3 Access Protection
+ uint32_t M4AP : 2; //!< [9:8] Master 4 Access Protection
+ uint32_t M5AP : 2; //!< [11:10] Master 5 Access Protection
+ uint32_t M6AP : 2; //!< [13:12] Master 6 Access Protection
+ uint32_t M7AP : 2; //!< [15:14] Master 7 Access Protection
+ uint32_t M0PFD : 1; //!< [16] Master 0 Prefetch Disable
+ uint32_t M1PFD : 1; //!< [17] Master 1 Prefetch Disable
+ uint32_t M2PFD : 1; //!< [18] Master 2 Prefetch Disable
+ uint32_t M3PFD : 1; //!< [19] Master 3 Prefetch Disable
+ uint32_t M4PFD : 1; //!< [20] Master 4 Prefetch Disable
+ uint32_t M5PFD : 1; //!< [21] Master 5 Prefetch Disable
+ uint32_t M6PFD : 1; //!< [22] Master 6 Prefetch Disable
+ uint32_t M7PFD : 1; //!< [23] Master 7 Prefetch Disable
+ uint32_t RESERVED0 : 8; //!< [31:24]
+ } B;
+} hw_fmc_pfapr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_PFAPR register
+ */
+//@{
+#define HW_FMC_PFAPR_ADDR (REGS_FMC_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_PFAPR (*(__IO hw_fmc_pfapr_t *) HW_FMC_PFAPR_ADDR)
+#define HW_FMC_PFAPR_RD() (HW_FMC_PFAPR.U)
+#define HW_FMC_PFAPR_WR(v) (HW_FMC_PFAPR.U = (v))
+#define HW_FMC_PFAPR_SET(v) (HW_FMC_PFAPR_WR(HW_FMC_PFAPR_RD() | (v)))
+#define HW_FMC_PFAPR_CLR(v) (HW_FMC_PFAPR_WR(HW_FMC_PFAPR_RD() & ~(v)))
+#define HW_FMC_PFAPR_TOG(v) (HW_FMC_PFAPR_WR(HW_FMC_PFAPR_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_PFAPR bitfields
+ */
+
+/*!
+ * @name Register FMC_PFAPR, field M0AP[1:0] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 00 - No access may be performed by this master
+ * - 01 - Only read accesses may be performed by this master
+ * - 10 - Only write accesses may be performed by this master
+ * - 11 - Both read and write accesses may be performed by this master
+ */
+//@{
+#define BP_FMC_PFAPR_M0AP (0U) //!< Bit position for FMC_PFAPR_M0AP.
+#define BM_FMC_PFAPR_M0AP (0x00000003U) //!< Bit mask for FMC_PFAPR_M0AP.
+#define BS_FMC_PFAPR_M0AP (2U) //!< Bit field size in bits for FMC_PFAPR_M0AP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M0AP field.
+#define BR_FMC_PFAPR_M0AP (HW_FMC_PFAPR.B.M0AP)
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M0AP.
+#define BF_FMC_PFAPR_M0AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M0AP), uint32_t) & BM_FMC_PFAPR_M0AP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M0AP field to a new value.
+#define BW_FMC_PFAPR_M0AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M0AP) | BF_FMC_PFAPR_M0AP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M1AP[3:2] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 00 - No access may be performed by this master
+ * - 01 - Only read accesses may be performed by this master
+ * - 10 - Only write accesses may be performed by this master
+ * - 11 - Both read and write accesses may be performed by this master
+ */
+//@{
+#define BP_FMC_PFAPR_M1AP (2U) //!< Bit position for FMC_PFAPR_M1AP.
+#define BM_FMC_PFAPR_M1AP (0x0000000CU) //!< Bit mask for FMC_PFAPR_M1AP.
+#define BS_FMC_PFAPR_M1AP (2U) //!< Bit field size in bits for FMC_PFAPR_M1AP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M1AP field.
+#define BR_FMC_PFAPR_M1AP (HW_FMC_PFAPR.B.M1AP)
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M1AP.
+#define BF_FMC_PFAPR_M1AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M1AP), uint32_t) & BM_FMC_PFAPR_M1AP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M1AP field to a new value.
+#define BW_FMC_PFAPR_M1AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M1AP) | BF_FMC_PFAPR_M1AP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M2AP[5:4] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 00 - No access may be performed by this master
+ * - 01 - Only read accesses may be performed by this master
+ * - 10 - Only write accesses may be performed by this master
+ * - 11 - Both read and write accesses may be performed by this master
+ */
+//@{
+#define BP_FMC_PFAPR_M2AP (4U) //!< Bit position for FMC_PFAPR_M2AP.
+#define BM_FMC_PFAPR_M2AP (0x00000030U) //!< Bit mask for FMC_PFAPR_M2AP.
+#define BS_FMC_PFAPR_M2AP (2U) //!< Bit field size in bits for FMC_PFAPR_M2AP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M2AP field.
+#define BR_FMC_PFAPR_M2AP (HW_FMC_PFAPR.B.M2AP)
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M2AP.
+#define BF_FMC_PFAPR_M2AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M2AP), uint32_t) & BM_FMC_PFAPR_M2AP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M2AP field to a new value.
+#define BW_FMC_PFAPR_M2AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M2AP) | BF_FMC_PFAPR_M2AP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M3AP[7:6] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 00 - No access may be performed by this master
+ * - 01 - Only read accesses may be performed by this master
+ * - 10 - Only write accesses may be performed by this master
+ * - 11 - Both read and write accesses may be performed by this master
+ */
+//@{
+#define BP_FMC_PFAPR_M3AP (6U) //!< Bit position for FMC_PFAPR_M3AP.
+#define BM_FMC_PFAPR_M3AP (0x000000C0U) //!< Bit mask for FMC_PFAPR_M3AP.
+#define BS_FMC_PFAPR_M3AP (2U) //!< Bit field size in bits for FMC_PFAPR_M3AP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M3AP field.
+#define BR_FMC_PFAPR_M3AP (HW_FMC_PFAPR.B.M3AP)
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M3AP.
+#define BF_FMC_PFAPR_M3AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M3AP), uint32_t) & BM_FMC_PFAPR_M3AP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M3AP field to a new value.
+#define BW_FMC_PFAPR_M3AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M3AP) | BF_FMC_PFAPR_M3AP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M4AP[9:8] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 00 - No access may be performed by this master
+ * - 01 - Only read accesses may be performed by this master
+ * - 10 - Only write accesses may be performed by this master
+ * - 11 - Both read and write accesses may be performed by this master
+ */
+//@{
+#define BP_FMC_PFAPR_M4AP (8U) //!< Bit position for FMC_PFAPR_M4AP.
+#define BM_FMC_PFAPR_M4AP (0x00000300U) //!< Bit mask for FMC_PFAPR_M4AP.
+#define BS_FMC_PFAPR_M4AP (2U) //!< Bit field size in bits for FMC_PFAPR_M4AP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M4AP field.
+#define BR_FMC_PFAPR_M4AP (HW_FMC_PFAPR.B.M4AP)
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M4AP.
+#define BF_FMC_PFAPR_M4AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M4AP), uint32_t) & BM_FMC_PFAPR_M4AP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M4AP field to a new value.
+#define BW_FMC_PFAPR_M4AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M4AP) | BF_FMC_PFAPR_M4AP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M5AP[11:10] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 00 - No access may be performed by this master
+ * - 01 - Only read accesses may be performed by this master
+ * - 10 - Only write accesses may be performed by this master
+ * - 11 - Both read and write accesses may be performed by this master
+ */
+//@{
+#define BP_FMC_PFAPR_M5AP (10U) //!< Bit position for FMC_PFAPR_M5AP.
+#define BM_FMC_PFAPR_M5AP (0x00000C00U) //!< Bit mask for FMC_PFAPR_M5AP.
+#define BS_FMC_PFAPR_M5AP (2U) //!< Bit field size in bits for FMC_PFAPR_M5AP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M5AP field.
+#define BR_FMC_PFAPR_M5AP (HW_FMC_PFAPR.B.M5AP)
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M5AP.
+#define BF_FMC_PFAPR_M5AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M5AP), uint32_t) & BM_FMC_PFAPR_M5AP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M5AP field to a new value.
+#define BW_FMC_PFAPR_M5AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M5AP) | BF_FMC_PFAPR_M5AP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M6AP[13:12] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 00 - No access may be performed by this master
+ * - 01 - Only read accesses may be performed by this master
+ * - 10 - Only write accesses may be performed by this master
+ * - 11 - Both read and write accesses may be performed by this master
+ */
+//@{
+#define BP_FMC_PFAPR_M6AP (12U) //!< Bit position for FMC_PFAPR_M6AP.
+#define BM_FMC_PFAPR_M6AP (0x00003000U) //!< Bit mask for FMC_PFAPR_M6AP.
+#define BS_FMC_PFAPR_M6AP (2U) //!< Bit field size in bits for FMC_PFAPR_M6AP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M6AP field.
+#define BR_FMC_PFAPR_M6AP (HW_FMC_PFAPR.B.M6AP)
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M6AP.
+#define BF_FMC_PFAPR_M6AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M6AP), uint32_t) & BM_FMC_PFAPR_M6AP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M6AP field to a new value.
+#define BW_FMC_PFAPR_M6AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M6AP) | BF_FMC_PFAPR_M6AP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M7AP[15:14] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 00 - No access may be performed by this master.
+ * - 01 - Only read accesses may be performed by this master.
+ * - 10 - Only write accesses may be performed by this master.
+ * - 11 - Both read and write accesses may be performed by this master.
+ */
+//@{
+#define BP_FMC_PFAPR_M7AP (14U) //!< Bit position for FMC_PFAPR_M7AP.
+#define BM_FMC_PFAPR_M7AP (0x0000C000U) //!< Bit mask for FMC_PFAPR_M7AP.
+#define BS_FMC_PFAPR_M7AP (2U) //!< Bit field size in bits for FMC_PFAPR_M7AP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M7AP field.
+#define BR_FMC_PFAPR_M7AP (HW_FMC_PFAPR.B.M7AP)
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M7AP.
+#define BF_FMC_PFAPR_M7AP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M7AP), uint32_t) & BM_FMC_PFAPR_M7AP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M7AP field to a new value.
+#define BW_FMC_PFAPR_M7AP(v) (HW_FMC_PFAPR_WR((HW_FMC_PFAPR_RD() & ~BM_FMC_PFAPR_M7AP) | BF_FMC_PFAPR_M7AP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M0PFD[16] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0 - Prefetching for this master is enabled.
+ * - 1 - Prefetching for this master is disabled.
+ */
+//@{
+#define BP_FMC_PFAPR_M0PFD (16U) //!< Bit position for FMC_PFAPR_M0PFD.
+#define BM_FMC_PFAPR_M0PFD (0x00010000U) //!< Bit mask for FMC_PFAPR_M0PFD.
+#define BS_FMC_PFAPR_M0PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M0PFD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M0PFD field.
+#define BR_FMC_PFAPR_M0PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M0PFD))
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M0PFD.
+#define BF_FMC_PFAPR_M0PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M0PFD), uint32_t) & BM_FMC_PFAPR_M0PFD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M0PFD field to a new value.
+#define BW_FMC_PFAPR_M0PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M0PFD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M1PFD[17] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0 - Prefetching for this master is enabled.
+ * - 1 - Prefetching for this master is disabled.
+ */
+//@{
+#define BP_FMC_PFAPR_M1PFD (17U) //!< Bit position for FMC_PFAPR_M1PFD.
+#define BM_FMC_PFAPR_M1PFD (0x00020000U) //!< Bit mask for FMC_PFAPR_M1PFD.
+#define BS_FMC_PFAPR_M1PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M1PFD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M1PFD field.
+#define BR_FMC_PFAPR_M1PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M1PFD))
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M1PFD.
+#define BF_FMC_PFAPR_M1PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M1PFD), uint32_t) & BM_FMC_PFAPR_M1PFD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M1PFD field to a new value.
+#define BW_FMC_PFAPR_M1PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M1PFD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M2PFD[18] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0 - Prefetching for this master is enabled.
+ * - 1 - Prefetching for this master is disabled.
+ */
+//@{
+#define BP_FMC_PFAPR_M2PFD (18U) //!< Bit position for FMC_PFAPR_M2PFD.
+#define BM_FMC_PFAPR_M2PFD (0x00040000U) //!< Bit mask for FMC_PFAPR_M2PFD.
+#define BS_FMC_PFAPR_M2PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M2PFD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M2PFD field.
+#define BR_FMC_PFAPR_M2PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M2PFD))
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M2PFD.
+#define BF_FMC_PFAPR_M2PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M2PFD), uint32_t) & BM_FMC_PFAPR_M2PFD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M2PFD field to a new value.
+#define BW_FMC_PFAPR_M2PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M2PFD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M3PFD[19] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0 - Prefetching for this master is enabled.
+ * - 1 - Prefetching for this master is disabled.
+ */
+//@{
+#define BP_FMC_PFAPR_M3PFD (19U) //!< Bit position for FMC_PFAPR_M3PFD.
+#define BM_FMC_PFAPR_M3PFD (0x00080000U) //!< Bit mask for FMC_PFAPR_M3PFD.
+#define BS_FMC_PFAPR_M3PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M3PFD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M3PFD field.
+#define BR_FMC_PFAPR_M3PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M3PFD))
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M3PFD.
+#define BF_FMC_PFAPR_M3PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M3PFD), uint32_t) & BM_FMC_PFAPR_M3PFD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M3PFD field to a new value.
+#define BW_FMC_PFAPR_M3PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M3PFD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M4PFD[20] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0 - Prefetching for this master is enabled.
+ * - 1 - Prefetching for this master is disabled.
+ */
+//@{
+#define BP_FMC_PFAPR_M4PFD (20U) //!< Bit position for FMC_PFAPR_M4PFD.
+#define BM_FMC_PFAPR_M4PFD (0x00100000U) //!< Bit mask for FMC_PFAPR_M4PFD.
+#define BS_FMC_PFAPR_M4PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M4PFD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M4PFD field.
+#define BR_FMC_PFAPR_M4PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M4PFD))
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M4PFD.
+#define BF_FMC_PFAPR_M4PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M4PFD), uint32_t) & BM_FMC_PFAPR_M4PFD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M4PFD field to a new value.
+#define BW_FMC_PFAPR_M4PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M4PFD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M5PFD[21] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0 - Prefetching for this master is enabled.
+ * - 1 - Prefetching for this master is disabled.
+ */
+//@{
+#define BP_FMC_PFAPR_M5PFD (21U) //!< Bit position for FMC_PFAPR_M5PFD.
+#define BM_FMC_PFAPR_M5PFD (0x00200000U) //!< Bit mask for FMC_PFAPR_M5PFD.
+#define BS_FMC_PFAPR_M5PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M5PFD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M5PFD field.
+#define BR_FMC_PFAPR_M5PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M5PFD))
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M5PFD.
+#define BF_FMC_PFAPR_M5PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M5PFD), uint32_t) & BM_FMC_PFAPR_M5PFD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M5PFD field to a new value.
+#define BW_FMC_PFAPR_M5PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M5PFD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M6PFD[22] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0 - Prefetching for this master is enabled.
+ * - 1 - Prefetching for this master is disabled.
+ */
+//@{
+#define BP_FMC_PFAPR_M6PFD (22U) //!< Bit position for FMC_PFAPR_M6PFD.
+#define BM_FMC_PFAPR_M6PFD (0x00400000U) //!< Bit mask for FMC_PFAPR_M6PFD.
+#define BS_FMC_PFAPR_M6PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M6PFD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M6PFD field.
+#define BR_FMC_PFAPR_M6PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M6PFD))
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M6PFD.
+#define BF_FMC_PFAPR_M6PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M6PFD), uint32_t) & BM_FMC_PFAPR_M6PFD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M6PFD field to a new value.
+#define BW_FMC_PFAPR_M6PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M6PFD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFAPR, field M7PFD[23] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0 - Prefetching for this master is enabled.
+ * - 1 - Prefetching for this master is disabled.
+ */
+//@{
+#define BP_FMC_PFAPR_M7PFD (23U) //!< Bit position for FMC_PFAPR_M7PFD.
+#define BM_FMC_PFAPR_M7PFD (0x00800000U) //!< Bit mask for FMC_PFAPR_M7PFD.
+#define BS_FMC_PFAPR_M7PFD (1U) //!< Bit field size in bits for FMC_PFAPR_M7PFD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFAPR_M7PFD field.
+#define BR_FMC_PFAPR_M7PFD (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M7PFD))
+#endif
+
+//! @brief Format value for bitfield FMC_PFAPR_M7PFD.
+#define BF_FMC_PFAPR_M7PFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFAPR_M7PFD), uint32_t) & BM_FMC_PFAPR_M7PFD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M7PFD field to a new value.
+#define BW_FMC_PFAPR_M7PFD(v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR, BP_FMC_PFAPR_M7PFD) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FMC_PFB0CR - Flash Bank 0 Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_PFB0CR - Flash Bank 0 Control Register (RW)
+ *
+ * Reset value: 0x3004001FU
+ */
+typedef union _hw_fmc_pfb0cr
+{
+ uint32_t U;
+ struct _hw_fmc_pfb0cr_bitfields
+ {
+ uint32_t B0SEBE : 1; //!< [0] Bank 0 Single Entry Buffer Enable
+ uint32_t B0IPE : 1; //!< [1] Bank 0 Instruction Prefetch Enable
+ uint32_t B0DPE : 1; //!< [2] Bank 0 Data Prefetch Enable
+ uint32_t B0ICE : 1; //!< [3] Bank 0 Instruction Cache Enable
+ uint32_t B0DCE : 1; //!< [4] Bank 0 Data Cache Enable
+ uint32_t CRCb : 3; //!< [7:5] Cache Replacement Control
+ uint32_t RESERVED0 : 9; //!< [16:8]
+ uint32_t B0MW : 2; //!< [18:17] Bank 0 Memory Width
+ uint32_t S_B_INV : 1; //!< [19] Invalidate Prefetch Speculation Buffer
+ uint32_t CINV_WAY : 4; //!< [23:20] Cache Invalidate Way x
+ uint32_t CLCK_WAY : 4; //!< [27:24] Cache Lock Way x
+ uint32_t B0RWSC : 4; //!< [31:28] Bank 0 Read Wait State Control
+ } B;
+} hw_fmc_pfb0cr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_PFB0CR register
+ */
+//@{
+#define HW_FMC_PFB0CR_ADDR (REGS_FMC_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_PFB0CR (*(__IO hw_fmc_pfb0cr_t *) HW_FMC_PFB0CR_ADDR)
+#define HW_FMC_PFB0CR_RD() (HW_FMC_PFB0CR.U)
+#define HW_FMC_PFB0CR_WR(v) (HW_FMC_PFB0CR.U = (v))
+#define HW_FMC_PFB0CR_SET(v) (HW_FMC_PFB0CR_WR(HW_FMC_PFB0CR_RD() | (v)))
+#define HW_FMC_PFB0CR_CLR(v) (HW_FMC_PFB0CR_WR(HW_FMC_PFB0CR_RD() & ~(v)))
+#define HW_FMC_PFB0CR_TOG(v) (HW_FMC_PFB0CR_WR(HW_FMC_PFB0CR_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_PFB0CR bitfields
+ */
+
+/*!
+ * @name Register FMC_PFB0CR, field B0SEBE[0] (RW)
+ *
+ * This bit controls whether the single entry page buffer is enabled in response
+ * to flash read accesses. Its operation is independent from bank 1's cache. A
+ * high-to-low transition of this enable forces the page buffer to be invalidated.
+ *
+ * Values:
+ * - 0 - Single entry buffer is disabled.
+ * - 1 - Single entry buffer is enabled.
+ */
+//@{
+#define BP_FMC_PFB0CR_B0SEBE (0U) //!< Bit position for FMC_PFB0CR_B0SEBE.
+#define BM_FMC_PFB0CR_B0SEBE (0x00000001U) //!< Bit mask for FMC_PFB0CR_B0SEBE.
+#define BS_FMC_PFB0CR_B0SEBE (1U) //!< Bit field size in bits for FMC_PFB0CR_B0SEBE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB0CR_B0SEBE field.
+#define BR_FMC_PFB0CR_B0SEBE (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0SEBE))
+#endif
+
+//! @brief Format value for bitfield FMC_PFB0CR_B0SEBE.
+#define BF_FMC_PFB0CR_B0SEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_B0SEBE), uint32_t) & BM_FMC_PFB0CR_B0SEBE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the B0SEBE field to a new value.
+#define BW_FMC_PFB0CR_B0SEBE(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0SEBE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB0CR, field B0IPE[1] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to instruction fetches.
+ *
+ * Values:
+ * - 0 - Do not prefetch in response to instruction fetches.
+ * - 1 - Enable prefetches in response to instruction fetches.
+ */
+//@{
+#define BP_FMC_PFB0CR_B0IPE (1U) //!< Bit position for FMC_PFB0CR_B0IPE.
+#define BM_FMC_PFB0CR_B0IPE (0x00000002U) //!< Bit mask for FMC_PFB0CR_B0IPE.
+#define BS_FMC_PFB0CR_B0IPE (1U) //!< Bit field size in bits for FMC_PFB0CR_B0IPE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB0CR_B0IPE field.
+#define BR_FMC_PFB0CR_B0IPE (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0IPE))
+#endif
+
+//! @brief Format value for bitfield FMC_PFB0CR_B0IPE.
+#define BF_FMC_PFB0CR_B0IPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_B0IPE), uint32_t) & BM_FMC_PFB0CR_B0IPE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the B0IPE field to a new value.
+#define BW_FMC_PFB0CR_B0IPE(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0IPE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB0CR, field B0DPE[2] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to data references.
+ *
+ * Values:
+ * - 0 - Do not prefetch in response to data references.
+ * - 1 - Enable prefetches in response to data references.
+ */
+//@{
+#define BP_FMC_PFB0CR_B0DPE (2U) //!< Bit position for FMC_PFB0CR_B0DPE.
+#define BM_FMC_PFB0CR_B0DPE (0x00000004U) //!< Bit mask for FMC_PFB0CR_B0DPE.
+#define BS_FMC_PFB0CR_B0DPE (1U) //!< Bit field size in bits for FMC_PFB0CR_B0DPE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB0CR_B0DPE field.
+#define BR_FMC_PFB0CR_B0DPE (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0DPE))
+#endif
+
+//! @brief Format value for bitfield FMC_PFB0CR_B0DPE.
+#define BF_FMC_PFB0CR_B0DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_B0DPE), uint32_t) & BM_FMC_PFB0CR_B0DPE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the B0DPE field to a new value.
+#define BW_FMC_PFB0CR_B0DPE(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0DPE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB0CR, field B0ICE[3] (RW)
+ *
+ * This bit controls whether instruction fetches are loaded into the cache.
+ *
+ * Values:
+ * - 0 - Do not cache instruction fetches.
+ * - 1 - Cache instruction fetches.
+ */
+//@{
+#define BP_FMC_PFB0CR_B0ICE (3U) //!< Bit position for FMC_PFB0CR_B0ICE.
+#define BM_FMC_PFB0CR_B0ICE (0x00000008U) //!< Bit mask for FMC_PFB0CR_B0ICE.
+#define BS_FMC_PFB0CR_B0ICE (1U) //!< Bit field size in bits for FMC_PFB0CR_B0ICE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB0CR_B0ICE field.
+#define BR_FMC_PFB0CR_B0ICE (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0ICE))
+#endif
+
+//! @brief Format value for bitfield FMC_PFB0CR_B0ICE.
+#define BF_FMC_PFB0CR_B0ICE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_B0ICE), uint32_t) & BM_FMC_PFB0CR_B0ICE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the B0ICE field to a new value.
+#define BW_FMC_PFB0CR_B0ICE(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0ICE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB0CR, field B0DCE[4] (RW)
+ *
+ * This bit controls whether data references are loaded into the cache.
+ *
+ * Values:
+ * - 0 - Do not cache data references.
+ * - 1 - Cache data references.
+ */
+//@{
+#define BP_FMC_PFB0CR_B0DCE (4U) //!< Bit position for FMC_PFB0CR_B0DCE.
+#define BM_FMC_PFB0CR_B0DCE (0x00000010U) //!< Bit mask for FMC_PFB0CR_B0DCE.
+#define BS_FMC_PFB0CR_B0DCE (1U) //!< Bit field size in bits for FMC_PFB0CR_B0DCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB0CR_B0DCE field.
+#define BR_FMC_PFB0CR_B0DCE (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0DCE))
+#endif
+
+//! @brief Format value for bitfield FMC_PFB0CR_B0DCE.
+#define BF_FMC_PFB0CR_B0DCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_B0DCE), uint32_t) & BM_FMC_PFB0CR_B0DCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the B0DCE field to a new value.
+#define BW_FMC_PFB0CR_B0DCE(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_B0DCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB0CR, field CRC[7:5] (RW)
+ *
+ * This 3-bit field defines the replacement algorithm for accesses that are
+ * cached.
+ *
+ * Values:
+ * - 000 - LRU replacement algorithm per set across all four ways
+ * - 001 - Reserved
+ * - 010 - Independent LRU with ways [0-1] for ifetches, [2-3] for data
+ * - 011 - Independent LRU with ways [0-2] for ifetches, [3] for data
+ * - 1xx - Reserved
+ */
+//@{
+#define BP_FMC_PFB0CR_CRC (5U) //!< Bit position for FMC_PFB0CR_CRC.
+#define BM_FMC_PFB0CR_CRC (0x000000E0U) //!< Bit mask for FMC_PFB0CR_CRC.
+#define BS_FMC_PFB0CR_CRC (3U) //!< Bit field size in bits for FMC_PFB0CR_CRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB0CR_CRC field.
+#define BR_FMC_PFB0CR_CRC (HW_FMC_PFB0CR.B.CRC)
+#endif
+
+//! @brief Format value for bitfield FMC_PFB0CR_CRC.
+#define BF_FMC_PFB0CR_CRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_CRC), uint32_t) & BM_FMC_PFB0CR_CRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CRC field to a new value.
+#define BW_FMC_PFB0CR_CRC(v) (HW_FMC_PFB0CR_WR((HW_FMC_PFB0CR_RD() & ~BM_FMC_PFB0CR_CRC) | BF_FMC_PFB0CR_CRC(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB0CR, field B0MW[18:17] (RO)
+ *
+ * This read-only field defines the width of the bank 0 memory.
+ *
+ * Values:
+ * - 00 - 32 bits
+ * - 01 - 64 bits
+ * - 10 - 128 bits
+ * - 11 - Reserved
+ */
+//@{
+#define BP_FMC_PFB0CR_B0MW (17U) //!< Bit position for FMC_PFB0CR_B0MW.
+#define BM_FMC_PFB0CR_B0MW (0x00060000U) //!< Bit mask for FMC_PFB0CR_B0MW.
+#define BS_FMC_PFB0CR_B0MW (2U) //!< Bit field size in bits for FMC_PFB0CR_B0MW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB0CR_B0MW field.
+#define BR_FMC_PFB0CR_B0MW (HW_FMC_PFB0CR.B.B0MW)
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB0CR, field S_B_INV[19] (WORZ)
+ *
+ * This bit determines if the FMC's prefetch speculation buffer and the single
+ * entry page buffer are to be invalidated (cleared). When this bit is written,
+ * the speculation buffer and single entry buffer are immediately cleared. This bit
+ * always reads as zero.
+ *
+ * Values:
+ * - 0 - Speculation buffer and single entry buffer are not affected.
+ * - 1 - Invalidate (clear) speculation buffer and single entry buffer.
+ */
+//@{
+#define BP_FMC_PFB0CR_S_B_INV (19U) //!< Bit position for FMC_PFB0CR_S_B_INV.
+#define BM_FMC_PFB0CR_S_B_INV (0x00080000U) //!< Bit mask for FMC_PFB0CR_S_B_INV.
+#define BS_FMC_PFB0CR_S_B_INV (1U) //!< Bit field size in bits for FMC_PFB0CR_S_B_INV.
+
+//! @brief Format value for bitfield FMC_PFB0CR_S_B_INV.
+#define BF_FMC_PFB0CR_S_B_INV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_S_B_INV), uint32_t) & BM_FMC_PFB0CR_S_B_INV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the S_B_INV field to a new value.
+#define BW_FMC_PFB0CR_S_B_INV(v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR, BP_FMC_PFB0CR_S_B_INV) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB0CR, field CINV_WAY[23:20] (WORZ)
+ *
+ * These bits determine if the given cache way is to be invalidated (cleared).
+ * When a bit within this field is written, the corresponding cache way is
+ * immediately invalidated: the way's tag, data, and valid contents are cleared. This
+ * field always reads as zero. Cache invalidation takes precedence over locking.
+ * The cache is invalidated by system reset. System software is required to
+ * maintain memory coherency when any segment of the flash memory is programmed or
+ * erased. Accordingly, cache invalidations must occur after a programming or erase
+ * event is completed and before the new memory image is accessed. The bit setting
+ * definitions are for each bit in the field.
+ *
+ * Values:
+ * - 0 - No cache way invalidation for the corresponding cache
+ * - 1 - Invalidate cache way for the corresponding cache: clear the tag, data,
+ * and vld bits of ways selected
+ */
+//@{
+#define BP_FMC_PFB0CR_CINV_WAY (20U) //!< Bit position for FMC_PFB0CR_CINV_WAY.
+#define BM_FMC_PFB0CR_CINV_WAY (0x00F00000U) //!< Bit mask for FMC_PFB0CR_CINV_WAY.
+#define BS_FMC_PFB0CR_CINV_WAY (4U) //!< Bit field size in bits for FMC_PFB0CR_CINV_WAY.
+
+//! @brief Format value for bitfield FMC_PFB0CR_CINV_WAY.
+#define BF_FMC_PFB0CR_CINV_WAY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_CINV_WAY), uint32_t) & BM_FMC_PFB0CR_CINV_WAY)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CINV_WAY field to a new value.
+#define BW_FMC_PFB0CR_CINV_WAY(v) (HW_FMC_PFB0CR_WR((HW_FMC_PFB0CR_RD() & ~BM_FMC_PFB0CR_CINV_WAY) | BF_FMC_PFB0CR_CINV_WAY(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB0CR, field CLCK_WAY[27:24] (RW)
+ *
+ * These bits determine if the given cache way is locked such that its contents
+ * will not be displaced by future misses. The bit setting definitions are for
+ * each bit in the field.
+ *
+ * Values:
+ * - 0 - Cache way is unlocked and may be displaced
+ * - 1 - Cache way is locked and its contents are not displaced
+ */
+//@{
+#define BP_FMC_PFB0CR_CLCK_WAY (24U) //!< Bit position for FMC_PFB0CR_CLCK_WAY.
+#define BM_FMC_PFB0CR_CLCK_WAY (0x0F000000U) //!< Bit mask for FMC_PFB0CR_CLCK_WAY.
+#define BS_FMC_PFB0CR_CLCK_WAY (4U) //!< Bit field size in bits for FMC_PFB0CR_CLCK_WAY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB0CR_CLCK_WAY field.
+#define BR_FMC_PFB0CR_CLCK_WAY (HW_FMC_PFB0CR.B.CLCK_WAY)
+#endif
+
+//! @brief Format value for bitfield FMC_PFB0CR_CLCK_WAY.
+#define BF_FMC_PFB0CR_CLCK_WAY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB0CR_CLCK_WAY), uint32_t) & BM_FMC_PFB0CR_CLCK_WAY)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLCK_WAY field to a new value.
+#define BW_FMC_PFB0CR_CLCK_WAY(v) (HW_FMC_PFB0CR_WR((HW_FMC_PFB0CR_RD() & ~BM_FMC_PFB0CR_CLCK_WAY) | BF_FMC_PFB0CR_CLCK_WAY(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB0CR, field B0RWSC[31:28] (RO)
+ *
+ * This read-only field defines the number of wait states required to access the
+ * bank 0 flash memory. The relationship between the read access time of the
+ * flash array (expressed in system clock cycles) and RWSC is defined as: Access
+ * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
+ * this value based on the ratio of the system clock speed to the flash clock
+ * speed. For example, when this ratio is 4:1, the field's value is 3h.
+ */
+//@{
+#define BP_FMC_PFB0CR_B0RWSC (28U) //!< Bit position for FMC_PFB0CR_B0RWSC.
+#define BM_FMC_PFB0CR_B0RWSC (0xF0000000U) //!< Bit mask for FMC_PFB0CR_B0RWSC.
+#define BS_FMC_PFB0CR_B0RWSC (4U) //!< Bit field size in bits for FMC_PFB0CR_B0RWSC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB0CR_B0RWSC field.
+#define BR_FMC_PFB0CR_B0RWSC (HW_FMC_PFB0CR.B.B0RWSC)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FMC_PFB1CR - Flash Bank 1 Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_PFB1CR - Flash Bank 1 Control Register (RW)
+ *
+ * Reset value: 0x3004001FU
+ *
+ * This register has a format similar to that for PFB0CR, except it controls the
+ * operation of flash bank 1, and the "global" cache control fields are empty.
+ */
+typedef union _hw_fmc_pfb1cr
+{
+ uint32_t U;
+ struct _hw_fmc_pfb1cr_bitfields
+ {
+ uint32_t B1SEBE : 1; //!< [0] Bank 1 Single Entry Buffer Enable
+ uint32_t B1IPE : 1; //!< [1] Bank 1 Instruction Prefetch Enable
+ uint32_t B1DPE : 1; //!< [2] Bank 1 Data Prefetch Enable
+ uint32_t B1ICE : 1; //!< [3] Bank 1 Instruction Cache Enable
+ uint32_t B1DCE : 1; //!< [4] Bank 1 Data Cache Enable
+ uint32_t RESERVED0 : 12; //!< [16:5]
+ uint32_t B1MW : 2; //!< [18:17] Bank 1 Memory Width
+ uint32_t RESERVED1 : 9; //!< [27:19]
+ uint32_t B1RWSC : 4; //!< [31:28] Bank 1 Read Wait State Control
+ } B;
+} hw_fmc_pfb1cr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_PFB1CR register
+ */
+//@{
+#define HW_FMC_PFB1CR_ADDR (REGS_FMC_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_PFB1CR (*(__IO hw_fmc_pfb1cr_t *) HW_FMC_PFB1CR_ADDR)
+#define HW_FMC_PFB1CR_RD() (HW_FMC_PFB1CR.U)
+#define HW_FMC_PFB1CR_WR(v) (HW_FMC_PFB1CR.U = (v))
+#define HW_FMC_PFB1CR_SET(v) (HW_FMC_PFB1CR_WR(HW_FMC_PFB1CR_RD() | (v)))
+#define HW_FMC_PFB1CR_CLR(v) (HW_FMC_PFB1CR_WR(HW_FMC_PFB1CR_RD() & ~(v)))
+#define HW_FMC_PFB1CR_TOG(v) (HW_FMC_PFB1CR_WR(HW_FMC_PFB1CR_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_PFB1CR bitfields
+ */
+
+/*!
+ * @name Register FMC_PFB1CR, field B1SEBE[0] (RW)
+ *
+ * This bit controls whether the single entry buffer is enabled in response to
+ * flash read accesses. Its operation is independent from bank 0's cache. A
+ * high-to-low transition of this enable forces the page buffer to be invalidated.
+ *
+ * Values:
+ * - 0 - Single entry buffer is disabled.
+ * - 1 - Single entry buffer is enabled.
+ */
+//@{
+#define BP_FMC_PFB1CR_B1SEBE (0U) //!< Bit position for FMC_PFB1CR_B1SEBE.
+#define BM_FMC_PFB1CR_B1SEBE (0x00000001U) //!< Bit mask for FMC_PFB1CR_B1SEBE.
+#define BS_FMC_PFB1CR_B1SEBE (1U) //!< Bit field size in bits for FMC_PFB1CR_B1SEBE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB1CR_B1SEBE field.
+#define BR_FMC_PFB1CR_B1SEBE (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1SEBE))
+#endif
+
+//! @brief Format value for bitfield FMC_PFB1CR_B1SEBE.
+#define BF_FMC_PFB1CR_B1SEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB1CR_B1SEBE), uint32_t) & BM_FMC_PFB1CR_B1SEBE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the B1SEBE field to a new value.
+#define BW_FMC_PFB1CR_B1SEBE(v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1SEBE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB1CR, field B1IPE[1] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to instruction fetches.
+ *
+ * Values:
+ * - 0 - Do not prefetch in response to instruction fetches.
+ * - 1 - Enable prefetches in response to instruction fetches.
+ */
+//@{
+#define BP_FMC_PFB1CR_B1IPE (1U) //!< Bit position for FMC_PFB1CR_B1IPE.
+#define BM_FMC_PFB1CR_B1IPE (0x00000002U) //!< Bit mask for FMC_PFB1CR_B1IPE.
+#define BS_FMC_PFB1CR_B1IPE (1U) //!< Bit field size in bits for FMC_PFB1CR_B1IPE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB1CR_B1IPE field.
+#define BR_FMC_PFB1CR_B1IPE (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1IPE))
+#endif
+
+//! @brief Format value for bitfield FMC_PFB1CR_B1IPE.
+#define BF_FMC_PFB1CR_B1IPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB1CR_B1IPE), uint32_t) & BM_FMC_PFB1CR_B1IPE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the B1IPE field to a new value.
+#define BW_FMC_PFB1CR_B1IPE(v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1IPE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB1CR, field B1DPE[2] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to data references.
+ *
+ * Values:
+ * - 0 - Do not prefetch in response to data references.
+ * - 1 - Enable prefetches in response to data references.
+ */
+//@{
+#define BP_FMC_PFB1CR_B1DPE (2U) //!< Bit position for FMC_PFB1CR_B1DPE.
+#define BM_FMC_PFB1CR_B1DPE (0x00000004U) //!< Bit mask for FMC_PFB1CR_B1DPE.
+#define BS_FMC_PFB1CR_B1DPE (1U) //!< Bit field size in bits for FMC_PFB1CR_B1DPE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB1CR_B1DPE field.
+#define BR_FMC_PFB1CR_B1DPE (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1DPE))
+#endif
+
+//! @brief Format value for bitfield FMC_PFB1CR_B1DPE.
+#define BF_FMC_PFB1CR_B1DPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB1CR_B1DPE), uint32_t) & BM_FMC_PFB1CR_B1DPE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the B1DPE field to a new value.
+#define BW_FMC_PFB1CR_B1DPE(v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1DPE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB1CR, field B1ICE[3] (RW)
+ *
+ * This bit controls whether instruction fetches are loaded into the cache.
+ *
+ * Values:
+ * - 0 - Do not cache instruction fetches.
+ * - 1 - Cache instruction fetches.
+ */
+//@{
+#define BP_FMC_PFB1CR_B1ICE (3U) //!< Bit position for FMC_PFB1CR_B1ICE.
+#define BM_FMC_PFB1CR_B1ICE (0x00000008U) //!< Bit mask for FMC_PFB1CR_B1ICE.
+#define BS_FMC_PFB1CR_B1ICE (1U) //!< Bit field size in bits for FMC_PFB1CR_B1ICE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB1CR_B1ICE field.
+#define BR_FMC_PFB1CR_B1ICE (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1ICE))
+#endif
+
+//! @brief Format value for bitfield FMC_PFB1CR_B1ICE.
+#define BF_FMC_PFB1CR_B1ICE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB1CR_B1ICE), uint32_t) & BM_FMC_PFB1CR_B1ICE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the B1ICE field to a new value.
+#define BW_FMC_PFB1CR_B1ICE(v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1ICE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB1CR, field B1DCE[4] (RW)
+ *
+ * This bit controls whether data references are loaded into the cache.
+ *
+ * Values:
+ * - 0 - Do not cache data references.
+ * - 1 - Cache data references.
+ */
+//@{
+#define BP_FMC_PFB1CR_B1DCE (4U) //!< Bit position for FMC_PFB1CR_B1DCE.
+#define BM_FMC_PFB1CR_B1DCE (0x00000010U) //!< Bit mask for FMC_PFB1CR_B1DCE.
+#define BS_FMC_PFB1CR_B1DCE (1U) //!< Bit field size in bits for FMC_PFB1CR_B1DCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB1CR_B1DCE field.
+#define BR_FMC_PFB1CR_B1DCE (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1DCE))
+#endif
+
+//! @brief Format value for bitfield FMC_PFB1CR_B1DCE.
+#define BF_FMC_PFB1CR_B1DCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_PFB1CR_B1DCE), uint32_t) & BM_FMC_PFB1CR_B1DCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the B1DCE field to a new value.
+#define BW_FMC_PFB1CR_B1DCE(v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR, BP_FMC_PFB1CR_B1DCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB1CR, field B1MW[18:17] (RO)
+ *
+ * This read-only field defines the width of the bank 1 memory.
+ *
+ * Values:
+ * - 00 - 32 bits
+ * - 01 - 64 bits
+ * - 10 - 128 bits
+ * - 11 - Reserved
+ */
+//@{
+#define BP_FMC_PFB1CR_B1MW (17U) //!< Bit position for FMC_PFB1CR_B1MW.
+#define BM_FMC_PFB1CR_B1MW (0x00060000U) //!< Bit mask for FMC_PFB1CR_B1MW.
+#define BS_FMC_PFB1CR_B1MW (2U) //!< Bit field size in bits for FMC_PFB1CR_B1MW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB1CR_B1MW field.
+#define BR_FMC_PFB1CR_B1MW (HW_FMC_PFB1CR.B.B1MW)
+#endif
+//@}
+
+/*!
+ * @name Register FMC_PFB1CR, field B1RWSC[31:28] (RO)
+ *
+ * This read-only field defines the number of wait states required to access the
+ * bank 1 flash memory. The relationship between the read access time of the
+ * flash array (expressed in system clock cycles) and RWSC is defined as: Access
+ * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
+ * this value based on the ratio of the system clock speed to the flash clock
+ * speed. For example, when this ratio is 4:1, the field's value is 3h.
+ */
+//@{
+#define BP_FMC_PFB1CR_B1RWSC (28U) //!< Bit position for FMC_PFB1CR_B1RWSC.
+#define BM_FMC_PFB1CR_B1RWSC (0xF0000000U) //!< Bit mask for FMC_PFB1CR_B1RWSC.
+#define BS_FMC_PFB1CR_B1RWSC (4U) //!< Bit field size in bits for FMC_PFB1CR_B1RWSC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_PFB1CR_B1RWSC field.
+#define BR_FMC_PFB1CR_B1RWSC (HW_FMC_PFB1CR.B.B1RWSC)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FMC_TAGVDW0Sn - Cache Tag Storage
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_TAGVDW0Sn - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+typedef union _hw_fmc_tagvdw0sn
+{
+ uint32_t U;
+ struct _hw_fmc_tagvdw0sn_bitfields
+ {
+ uint32_t valid : 1; //!< [0] 1-bit valid for cache entry
+ uint32_t RESERVED0 : 4; //!< [4:1]
+ uint32_t tag : 14; //!< [18:5] 14-bit tag for cache entry
+ uint32_t RESERVED1 : 13; //!< [31:19]
+ } B;
+} hw_fmc_tagvdw0sn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW0Sn register
+ */
+//@{
+#define HW_FMC_TAGVDW0Sn_COUNT (4U)
+
+#define HW_FMC_TAGVDW0Sn_ADDR(n) (REGS_FMC_BASE + 0x100U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_TAGVDW0Sn(n) (*(__IO hw_fmc_tagvdw0sn_t *) HW_FMC_TAGVDW0Sn_ADDR(n))
+#define HW_FMC_TAGVDW0Sn_RD(n) (HW_FMC_TAGVDW0Sn(n).U)
+#define HW_FMC_TAGVDW0Sn_WR(n, v) (HW_FMC_TAGVDW0Sn(n).U = (v))
+#define HW_FMC_TAGVDW0Sn_SET(n, v) (HW_FMC_TAGVDW0Sn_WR(n, HW_FMC_TAGVDW0Sn_RD(n) | (v)))
+#define HW_FMC_TAGVDW0Sn_CLR(n, v) (HW_FMC_TAGVDW0Sn_WR(n, HW_FMC_TAGVDW0Sn_RD(n) & ~(v)))
+#define HW_FMC_TAGVDW0Sn_TOG(n, v) (HW_FMC_TAGVDW0Sn_WR(n, HW_FMC_TAGVDW0Sn_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_TAGVDW0Sn bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW0Sn, field valid[0] (RW)
+ */
+//@{
+#define BP_FMC_TAGVDW0Sn_valid (0U) //!< Bit position for FMC_TAGVDW0Sn_valid.
+#define BM_FMC_TAGVDW0Sn_valid (0x00000001U) //!< Bit mask for FMC_TAGVDW0Sn_valid.
+#define BS_FMC_TAGVDW0Sn_valid (1U) //!< Bit field size in bits for FMC_TAGVDW0Sn_valid.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_TAGVDW0Sn_valid field.
+#define BR_FMC_TAGVDW0Sn_valid(n) (BITBAND_ACCESS32(HW_FMC_TAGVDW0Sn_ADDR(n), BP_FMC_TAGVDW0Sn_valid))
+#endif
+
+//! @brief Format value for bitfield FMC_TAGVDW0Sn_valid.
+#define BF_FMC_TAGVDW0Sn_valid(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW0Sn_valid), uint32_t) & BM_FMC_TAGVDW0Sn_valid)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the valid field to a new value.
+#define BW_FMC_TAGVDW0Sn_valid(n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW0Sn_ADDR(n), BP_FMC_TAGVDW0Sn_valid) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_TAGVDW0Sn, field tag[18:5] (RW)
+ */
+//@{
+#define BP_FMC_TAGVDW0Sn_tag (5U) //!< Bit position for FMC_TAGVDW0Sn_tag.
+#define BM_FMC_TAGVDW0Sn_tag (0x0007FFE0U) //!< Bit mask for FMC_TAGVDW0Sn_tag.
+#define BS_FMC_TAGVDW0Sn_tag (14U) //!< Bit field size in bits for FMC_TAGVDW0Sn_tag.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_TAGVDW0Sn_tag field.
+#define BR_FMC_TAGVDW0Sn_tag(n) (HW_FMC_TAGVDW0Sn(n).B.tag)
+#endif
+
+//! @brief Format value for bitfield FMC_TAGVDW0Sn_tag.
+#define BF_FMC_TAGVDW0Sn_tag(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW0Sn_tag), uint32_t) & BM_FMC_TAGVDW0Sn_tag)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the tag field to a new value.
+#define BW_FMC_TAGVDW0Sn_tag(n, v) (HW_FMC_TAGVDW0Sn_WR(n, (HW_FMC_TAGVDW0Sn_RD(n) & ~BM_FMC_TAGVDW0Sn_tag) | BF_FMC_TAGVDW0Sn_tag(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FMC_TAGVDW1Sn - Cache Tag Storage
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_TAGVDW1Sn - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+typedef union _hw_fmc_tagvdw1sn
+{
+ uint32_t U;
+ struct _hw_fmc_tagvdw1sn_bitfields
+ {
+ uint32_t valid : 1; //!< [0] 1-bit valid for cache entry
+ uint32_t RESERVED0 : 4; //!< [4:1]
+ uint32_t tag : 14; //!< [18:5] 14-bit tag for cache entry
+ uint32_t RESERVED1 : 13; //!< [31:19]
+ } B;
+} hw_fmc_tagvdw1sn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW1Sn register
+ */
+//@{
+#define HW_FMC_TAGVDW1Sn_COUNT (4U)
+
+#define HW_FMC_TAGVDW1Sn_ADDR(n) (REGS_FMC_BASE + 0x110U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_TAGVDW1Sn(n) (*(__IO hw_fmc_tagvdw1sn_t *) HW_FMC_TAGVDW1Sn_ADDR(n))
+#define HW_FMC_TAGVDW1Sn_RD(n) (HW_FMC_TAGVDW1Sn(n).U)
+#define HW_FMC_TAGVDW1Sn_WR(n, v) (HW_FMC_TAGVDW1Sn(n).U = (v))
+#define HW_FMC_TAGVDW1Sn_SET(n, v) (HW_FMC_TAGVDW1Sn_WR(n, HW_FMC_TAGVDW1Sn_RD(n) | (v)))
+#define HW_FMC_TAGVDW1Sn_CLR(n, v) (HW_FMC_TAGVDW1Sn_WR(n, HW_FMC_TAGVDW1Sn_RD(n) & ~(v)))
+#define HW_FMC_TAGVDW1Sn_TOG(n, v) (HW_FMC_TAGVDW1Sn_WR(n, HW_FMC_TAGVDW1Sn_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_TAGVDW1Sn bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW1Sn, field valid[0] (RW)
+ */
+//@{
+#define BP_FMC_TAGVDW1Sn_valid (0U) //!< Bit position for FMC_TAGVDW1Sn_valid.
+#define BM_FMC_TAGVDW1Sn_valid (0x00000001U) //!< Bit mask for FMC_TAGVDW1Sn_valid.
+#define BS_FMC_TAGVDW1Sn_valid (1U) //!< Bit field size in bits for FMC_TAGVDW1Sn_valid.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_TAGVDW1Sn_valid field.
+#define BR_FMC_TAGVDW1Sn_valid(n) (BITBAND_ACCESS32(HW_FMC_TAGVDW1Sn_ADDR(n), BP_FMC_TAGVDW1Sn_valid))
+#endif
+
+//! @brief Format value for bitfield FMC_TAGVDW1Sn_valid.
+#define BF_FMC_TAGVDW1Sn_valid(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW1Sn_valid), uint32_t) & BM_FMC_TAGVDW1Sn_valid)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the valid field to a new value.
+#define BW_FMC_TAGVDW1Sn_valid(n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW1Sn_ADDR(n), BP_FMC_TAGVDW1Sn_valid) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_TAGVDW1Sn, field tag[18:5] (RW)
+ */
+//@{
+#define BP_FMC_TAGVDW1Sn_tag (5U) //!< Bit position for FMC_TAGVDW1Sn_tag.
+#define BM_FMC_TAGVDW1Sn_tag (0x0007FFE0U) //!< Bit mask for FMC_TAGVDW1Sn_tag.
+#define BS_FMC_TAGVDW1Sn_tag (14U) //!< Bit field size in bits for FMC_TAGVDW1Sn_tag.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_TAGVDW1Sn_tag field.
+#define BR_FMC_TAGVDW1Sn_tag(n) (HW_FMC_TAGVDW1Sn(n).B.tag)
+#endif
+
+//! @brief Format value for bitfield FMC_TAGVDW1Sn_tag.
+#define BF_FMC_TAGVDW1Sn_tag(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW1Sn_tag), uint32_t) & BM_FMC_TAGVDW1Sn_tag)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the tag field to a new value.
+#define BW_FMC_TAGVDW1Sn_tag(n, v) (HW_FMC_TAGVDW1Sn_WR(n, (HW_FMC_TAGVDW1Sn_RD(n) & ~BM_FMC_TAGVDW1Sn_tag) | BF_FMC_TAGVDW1Sn_tag(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FMC_TAGVDW2Sn - Cache Tag Storage
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_TAGVDW2Sn - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+typedef union _hw_fmc_tagvdw2sn
+{
+ uint32_t U;
+ struct _hw_fmc_tagvdw2sn_bitfields
+ {
+ uint32_t valid : 1; //!< [0] 1-bit valid for cache entry
+ uint32_t RESERVED0 : 4; //!< [4:1]
+ uint32_t tag : 14; //!< [18:5] 14-bit tag for cache entry
+ uint32_t RESERVED1 : 13; //!< [31:19]
+ } B;
+} hw_fmc_tagvdw2sn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW2Sn register
+ */
+//@{
+#define HW_FMC_TAGVDW2Sn_COUNT (4U)
+
+#define HW_FMC_TAGVDW2Sn_ADDR(n) (REGS_FMC_BASE + 0x120U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_TAGVDW2Sn(n) (*(__IO hw_fmc_tagvdw2sn_t *) HW_FMC_TAGVDW2Sn_ADDR(n))
+#define HW_FMC_TAGVDW2Sn_RD(n) (HW_FMC_TAGVDW2Sn(n).U)
+#define HW_FMC_TAGVDW2Sn_WR(n, v) (HW_FMC_TAGVDW2Sn(n).U = (v))
+#define HW_FMC_TAGVDW2Sn_SET(n, v) (HW_FMC_TAGVDW2Sn_WR(n, HW_FMC_TAGVDW2Sn_RD(n) | (v)))
+#define HW_FMC_TAGVDW2Sn_CLR(n, v) (HW_FMC_TAGVDW2Sn_WR(n, HW_FMC_TAGVDW2Sn_RD(n) & ~(v)))
+#define HW_FMC_TAGVDW2Sn_TOG(n, v) (HW_FMC_TAGVDW2Sn_WR(n, HW_FMC_TAGVDW2Sn_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_TAGVDW2Sn bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW2Sn, field valid[0] (RW)
+ */
+//@{
+#define BP_FMC_TAGVDW2Sn_valid (0U) //!< Bit position for FMC_TAGVDW2Sn_valid.
+#define BM_FMC_TAGVDW2Sn_valid (0x00000001U) //!< Bit mask for FMC_TAGVDW2Sn_valid.
+#define BS_FMC_TAGVDW2Sn_valid (1U) //!< Bit field size in bits for FMC_TAGVDW2Sn_valid.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_TAGVDW2Sn_valid field.
+#define BR_FMC_TAGVDW2Sn_valid(n) (BITBAND_ACCESS32(HW_FMC_TAGVDW2Sn_ADDR(n), BP_FMC_TAGVDW2Sn_valid))
+#endif
+
+//! @brief Format value for bitfield FMC_TAGVDW2Sn_valid.
+#define BF_FMC_TAGVDW2Sn_valid(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW2Sn_valid), uint32_t) & BM_FMC_TAGVDW2Sn_valid)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the valid field to a new value.
+#define BW_FMC_TAGVDW2Sn_valid(n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW2Sn_ADDR(n), BP_FMC_TAGVDW2Sn_valid) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_TAGVDW2Sn, field tag[18:5] (RW)
+ */
+//@{
+#define BP_FMC_TAGVDW2Sn_tag (5U) //!< Bit position for FMC_TAGVDW2Sn_tag.
+#define BM_FMC_TAGVDW2Sn_tag (0x0007FFE0U) //!< Bit mask for FMC_TAGVDW2Sn_tag.
+#define BS_FMC_TAGVDW2Sn_tag (14U) //!< Bit field size in bits for FMC_TAGVDW2Sn_tag.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_TAGVDW2Sn_tag field.
+#define BR_FMC_TAGVDW2Sn_tag(n) (HW_FMC_TAGVDW2Sn(n).B.tag)
+#endif
+
+//! @brief Format value for bitfield FMC_TAGVDW2Sn_tag.
+#define BF_FMC_TAGVDW2Sn_tag(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW2Sn_tag), uint32_t) & BM_FMC_TAGVDW2Sn_tag)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the tag field to a new value.
+#define BW_FMC_TAGVDW2Sn_tag(n, v) (HW_FMC_TAGVDW2Sn_WR(n, (HW_FMC_TAGVDW2Sn_RD(n) & ~BM_FMC_TAGVDW2Sn_tag) | BF_FMC_TAGVDW2Sn_tag(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FMC_TAGVDW3Sn - Cache Tag Storage
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_TAGVDW3Sn - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+typedef union _hw_fmc_tagvdw3sn
+{
+ uint32_t U;
+ struct _hw_fmc_tagvdw3sn_bitfields
+ {
+ uint32_t valid : 1; //!< [0] 1-bit valid for cache entry
+ uint32_t RESERVED0 : 4; //!< [4:1]
+ uint32_t tag : 14; //!< [18:5] 14-bit tag for cache entry
+ uint32_t RESERVED1 : 13; //!< [31:19]
+ } B;
+} hw_fmc_tagvdw3sn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW3Sn register
+ */
+//@{
+#define HW_FMC_TAGVDW3Sn_COUNT (4U)
+
+#define HW_FMC_TAGVDW3Sn_ADDR(n) (REGS_FMC_BASE + 0x130U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_TAGVDW3Sn(n) (*(__IO hw_fmc_tagvdw3sn_t *) HW_FMC_TAGVDW3Sn_ADDR(n))
+#define HW_FMC_TAGVDW3Sn_RD(n) (HW_FMC_TAGVDW3Sn(n).U)
+#define HW_FMC_TAGVDW3Sn_WR(n, v) (HW_FMC_TAGVDW3Sn(n).U = (v))
+#define HW_FMC_TAGVDW3Sn_SET(n, v) (HW_FMC_TAGVDW3Sn_WR(n, HW_FMC_TAGVDW3Sn_RD(n) | (v)))
+#define HW_FMC_TAGVDW3Sn_CLR(n, v) (HW_FMC_TAGVDW3Sn_WR(n, HW_FMC_TAGVDW3Sn_RD(n) & ~(v)))
+#define HW_FMC_TAGVDW3Sn_TOG(n, v) (HW_FMC_TAGVDW3Sn_WR(n, HW_FMC_TAGVDW3Sn_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_TAGVDW3Sn bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW3Sn, field valid[0] (RW)
+ */
+//@{
+#define BP_FMC_TAGVDW3Sn_valid (0U) //!< Bit position for FMC_TAGVDW3Sn_valid.
+#define BM_FMC_TAGVDW3Sn_valid (0x00000001U) //!< Bit mask for FMC_TAGVDW3Sn_valid.
+#define BS_FMC_TAGVDW3Sn_valid (1U) //!< Bit field size in bits for FMC_TAGVDW3Sn_valid.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_TAGVDW3Sn_valid field.
+#define BR_FMC_TAGVDW3Sn_valid(n) (BITBAND_ACCESS32(HW_FMC_TAGVDW3Sn_ADDR(n), BP_FMC_TAGVDW3Sn_valid))
+#endif
+
+//! @brief Format value for bitfield FMC_TAGVDW3Sn_valid.
+#define BF_FMC_TAGVDW3Sn_valid(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW3Sn_valid), uint32_t) & BM_FMC_TAGVDW3Sn_valid)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the valid field to a new value.
+#define BW_FMC_TAGVDW3Sn_valid(n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW3Sn_ADDR(n), BP_FMC_TAGVDW3Sn_valid) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FMC_TAGVDW3Sn, field tag[18:5] (RW)
+ */
+//@{
+#define BP_FMC_TAGVDW3Sn_tag (5U) //!< Bit position for FMC_TAGVDW3Sn_tag.
+#define BM_FMC_TAGVDW3Sn_tag (0x0007FFE0U) //!< Bit mask for FMC_TAGVDW3Sn_tag.
+#define BS_FMC_TAGVDW3Sn_tag (14U) //!< Bit field size in bits for FMC_TAGVDW3Sn_tag.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_TAGVDW3Sn_tag field.
+#define BR_FMC_TAGVDW3Sn_tag(n) (HW_FMC_TAGVDW3Sn(n).B.tag)
+#endif
+
+//! @brief Format value for bitfield FMC_TAGVDW3Sn_tag.
+#define BF_FMC_TAGVDW3Sn_tag(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_TAGVDW3Sn_tag), uint32_t) & BM_FMC_TAGVDW3Sn_tag)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the tag field to a new value.
+#define BW_FMC_TAGVDW3Sn_tag(n, v) (HW_FMC_TAGVDW3Sn_WR(n, (HW_FMC_TAGVDW3Sn_RD(n) & ~BM_FMC_TAGVDW3Sn_tag) | BF_FMC_TAGVDW3Sn_tag(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FMC_DATAW0SnU - Cache Data Storage (upper word)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_DATAW0SnU - Cache Data Storage (upper word) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
+ * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
+ * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
+ * lower word, respectively. This section represents data for the upper word (bits
+ * [63:32]) of all sets in the indicated way.
+ */
+typedef union _hw_fmc_dataw0snu
+{
+ uint32_t U;
+ struct _hw_fmc_dataw0snu_bitfields
+ {
+ uint32_t data : 32; //!< [31:0] Bits [63:32] of data entry
+ } B;
+} hw_fmc_dataw0snu_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_DATAW0SnU register
+ */
+//@{
+#define HW_FMC_DATAW0SnU_COUNT (4U)
+
+#define HW_FMC_DATAW0SnU_ADDR(n) (REGS_FMC_BASE + 0x200U + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_DATAW0SnU(n) (*(__IO hw_fmc_dataw0snu_t *) HW_FMC_DATAW0SnU_ADDR(n))
+#define HW_FMC_DATAW0SnU_RD(n) (HW_FMC_DATAW0SnU(n).U)
+#define HW_FMC_DATAW0SnU_WR(n, v) (HW_FMC_DATAW0SnU(n).U = (v))
+#define HW_FMC_DATAW0SnU_SET(n, v) (HW_FMC_DATAW0SnU_WR(n, HW_FMC_DATAW0SnU_RD(n) | (v)))
+#define HW_FMC_DATAW0SnU_CLR(n, v) (HW_FMC_DATAW0SnU_WR(n, HW_FMC_DATAW0SnU_RD(n) & ~(v)))
+#define HW_FMC_DATAW0SnU_TOG(n, v) (HW_FMC_DATAW0SnU_WR(n, HW_FMC_DATAW0SnU_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_DATAW0SnU bitfields
+ */
+
+/*!
+ * @name Register FMC_DATAW0SnU, field data[31:0] (RW)
+ */
+//@{
+#define BP_FMC_DATAW0SnU_data (0U) //!< Bit position for FMC_DATAW0SnU_data.
+#define BM_FMC_DATAW0SnU_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW0SnU_data.
+#define BS_FMC_DATAW0SnU_data (32U) //!< Bit field size in bits for FMC_DATAW0SnU_data.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_DATAW0SnU_data field.
+#define BR_FMC_DATAW0SnU_data(n) (HW_FMC_DATAW0SnU(n).U)
+#endif
+
+//! @brief Format value for bitfield FMC_DATAW0SnU_data.
+#define BF_FMC_DATAW0SnU_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW0SnU_data), uint32_t) & BM_FMC_DATAW0SnU_data)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the data field to a new value.
+#define BW_FMC_DATAW0SnU_data(n, v) (HW_FMC_DATAW0SnU_WR(n, v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_FMC_DATAW0SnL - Cache Data Storage (lower word)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_DATAW0SnL - Cache Data Storage (lower word) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
+ * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
+ * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
+ * lower word, respectively. This section represents data for the lower word (bits
+ * [31:0]) of all sets in the indicated way.
+ */
+typedef union _hw_fmc_dataw0snl
+{
+ uint32_t U;
+ struct _hw_fmc_dataw0snl_bitfields
+ {
+ uint32_t data : 32; //!< [31:0] Bits [31:0] of data entry
+ } B;
+} hw_fmc_dataw0snl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_DATAW0SnL register
+ */
+//@{
+#define HW_FMC_DATAW0SnL_COUNT (4U)
+
+#define HW_FMC_DATAW0SnL_ADDR(n) (REGS_FMC_BASE + 0x204U + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_DATAW0SnL(n) (*(__IO hw_fmc_dataw0snl_t *) HW_FMC_DATAW0SnL_ADDR(n))
+#define HW_FMC_DATAW0SnL_RD(n) (HW_FMC_DATAW0SnL(n).U)
+#define HW_FMC_DATAW0SnL_WR(n, v) (HW_FMC_DATAW0SnL(n).U = (v))
+#define HW_FMC_DATAW0SnL_SET(n, v) (HW_FMC_DATAW0SnL_WR(n, HW_FMC_DATAW0SnL_RD(n) | (v)))
+#define HW_FMC_DATAW0SnL_CLR(n, v) (HW_FMC_DATAW0SnL_WR(n, HW_FMC_DATAW0SnL_RD(n) & ~(v)))
+#define HW_FMC_DATAW0SnL_TOG(n, v) (HW_FMC_DATAW0SnL_WR(n, HW_FMC_DATAW0SnL_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_DATAW0SnL bitfields
+ */
+
+/*!
+ * @name Register FMC_DATAW0SnL, field data[31:0] (RW)
+ */
+//@{
+#define BP_FMC_DATAW0SnL_data (0U) //!< Bit position for FMC_DATAW0SnL_data.
+#define BM_FMC_DATAW0SnL_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW0SnL_data.
+#define BS_FMC_DATAW0SnL_data (32U) //!< Bit field size in bits for FMC_DATAW0SnL_data.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_DATAW0SnL_data field.
+#define BR_FMC_DATAW0SnL_data(n) (HW_FMC_DATAW0SnL(n).U)
+#endif
+
+//! @brief Format value for bitfield FMC_DATAW0SnL_data.
+#define BF_FMC_DATAW0SnL_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW0SnL_data), uint32_t) & BM_FMC_DATAW0SnL_data)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the data field to a new value.
+#define BW_FMC_DATAW0SnL_data(n, v) (HW_FMC_DATAW0SnL_WR(n, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FMC_DATAW1SnU - Cache Data Storage (upper word)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_DATAW1SnU - Cache Data Storage (upper word) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
+ * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
+ * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
+ * lower word, respectively. This section represents data for the upper word (bits
+ * [63:32]) of all sets in the indicated way.
+ */
+typedef union _hw_fmc_dataw1snu
+{
+ uint32_t U;
+ struct _hw_fmc_dataw1snu_bitfields
+ {
+ uint32_t data : 32; //!< [31:0] Bits [63:32] of data entry
+ } B;
+} hw_fmc_dataw1snu_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_DATAW1SnU register
+ */
+//@{
+#define HW_FMC_DATAW1SnU_COUNT (4U)
+
+#define HW_FMC_DATAW1SnU_ADDR(n) (REGS_FMC_BASE + 0x220U + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_DATAW1SnU(n) (*(__IO hw_fmc_dataw1snu_t *) HW_FMC_DATAW1SnU_ADDR(n))
+#define HW_FMC_DATAW1SnU_RD(n) (HW_FMC_DATAW1SnU(n).U)
+#define HW_FMC_DATAW1SnU_WR(n, v) (HW_FMC_DATAW1SnU(n).U = (v))
+#define HW_FMC_DATAW1SnU_SET(n, v) (HW_FMC_DATAW1SnU_WR(n, HW_FMC_DATAW1SnU_RD(n) | (v)))
+#define HW_FMC_DATAW1SnU_CLR(n, v) (HW_FMC_DATAW1SnU_WR(n, HW_FMC_DATAW1SnU_RD(n) & ~(v)))
+#define HW_FMC_DATAW1SnU_TOG(n, v) (HW_FMC_DATAW1SnU_WR(n, HW_FMC_DATAW1SnU_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_DATAW1SnU bitfields
+ */
+
+/*!
+ * @name Register FMC_DATAW1SnU, field data[31:0] (RW)
+ */
+//@{
+#define BP_FMC_DATAW1SnU_data (0U) //!< Bit position for FMC_DATAW1SnU_data.
+#define BM_FMC_DATAW1SnU_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW1SnU_data.
+#define BS_FMC_DATAW1SnU_data (32U) //!< Bit field size in bits for FMC_DATAW1SnU_data.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_DATAW1SnU_data field.
+#define BR_FMC_DATAW1SnU_data(n) (HW_FMC_DATAW1SnU(n).U)
+#endif
+
+//! @brief Format value for bitfield FMC_DATAW1SnU_data.
+#define BF_FMC_DATAW1SnU_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW1SnU_data), uint32_t) & BM_FMC_DATAW1SnU_data)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the data field to a new value.
+#define BW_FMC_DATAW1SnU_data(n, v) (HW_FMC_DATAW1SnU_WR(n, v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_FMC_DATAW1SnL - Cache Data Storage (lower word)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_DATAW1SnL - Cache Data Storage (lower word) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
+ * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
+ * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
+ * lower word, respectively. This section represents data for the lower word (bits
+ * [31:0]) of all sets in the indicated way.
+ */
+typedef union _hw_fmc_dataw1snl
+{
+ uint32_t U;
+ struct _hw_fmc_dataw1snl_bitfields
+ {
+ uint32_t data : 32; //!< [31:0] Bits [31:0] of data entry
+ } B;
+} hw_fmc_dataw1snl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_DATAW1SnL register
+ */
+//@{
+#define HW_FMC_DATAW1SnL_COUNT (4U)
+
+#define HW_FMC_DATAW1SnL_ADDR(n) (REGS_FMC_BASE + 0x224U + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_DATAW1SnL(n) (*(__IO hw_fmc_dataw1snl_t *) HW_FMC_DATAW1SnL_ADDR(n))
+#define HW_FMC_DATAW1SnL_RD(n) (HW_FMC_DATAW1SnL(n).U)
+#define HW_FMC_DATAW1SnL_WR(n, v) (HW_FMC_DATAW1SnL(n).U = (v))
+#define HW_FMC_DATAW1SnL_SET(n, v) (HW_FMC_DATAW1SnL_WR(n, HW_FMC_DATAW1SnL_RD(n) | (v)))
+#define HW_FMC_DATAW1SnL_CLR(n, v) (HW_FMC_DATAW1SnL_WR(n, HW_FMC_DATAW1SnL_RD(n) & ~(v)))
+#define HW_FMC_DATAW1SnL_TOG(n, v) (HW_FMC_DATAW1SnL_WR(n, HW_FMC_DATAW1SnL_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_DATAW1SnL bitfields
+ */
+
+/*!
+ * @name Register FMC_DATAW1SnL, field data[31:0] (RW)
+ */
+//@{
+#define BP_FMC_DATAW1SnL_data (0U) //!< Bit position for FMC_DATAW1SnL_data.
+#define BM_FMC_DATAW1SnL_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW1SnL_data.
+#define BS_FMC_DATAW1SnL_data (32U) //!< Bit field size in bits for FMC_DATAW1SnL_data.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_DATAW1SnL_data field.
+#define BR_FMC_DATAW1SnL_data(n) (HW_FMC_DATAW1SnL(n).U)
+#endif
+
+//! @brief Format value for bitfield FMC_DATAW1SnL_data.
+#define BF_FMC_DATAW1SnL_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW1SnL_data), uint32_t) & BM_FMC_DATAW1SnL_data)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the data field to a new value.
+#define BW_FMC_DATAW1SnL_data(n, v) (HW_FMC_DATAW1SnL_WR(n, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FMC_DATAW2SnU - Cache Data Storage (upper word)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_DATAW2SnU - Cache Data Storage (upper word) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
+ * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
+ * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
+ * lower word, respectively. This section represents data for the upper word (bits
+ * [63:32]) of all sets in the indicated way.
+ */
+typedef union _hw_fmc_dataw2snu
+{
+ uint32_t U;
+ struct _hw_fmc_dataw2snu_bitfields
+ {
+ uint32_t data : 32; //!< [31:0] Bits [63:32] of data entry
+ } B;
+} hw_fmc_dataw2snu_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_DATAW2SnU register
+ */
+//@{
+#define HW_FMC_DATAW2SnU_COUNT (4U)
+
+#define HW_FMC_DATAW2SnU_ADDR(n) (REGS_FMC_BASE + 0x240U + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_DATAW2SnU(n) (*(__IO hw_fmc_dataw2snu_t *) HW_FMC_DATAW2SnU_ADDR(n))
+#define HW_FMC_DATAW2SnU_RD(n) (HW_FMC_DATAW2SnU(n).U)
+#define HW_FMC_DATAW2SnU_WR(n, v) (HW_FMC_DATAW2SnU(n).U = (v))
+#define HW_FMC_DATAW2SnU_SET(n, v) (HW_FMC_DATAW2SnU_WR(n, HW_FMC_DATAW2SnU_RD(n) | (v)))
+#define HW_FMC_DATAW2SnU_CLR(n, v) (HW_FMC_DATAW2SnU_WR(n, HW_FMC_DATAW2SnU_RD(n) & ~(v)))
+#define HW_FMC_DATAW2SnU_TOG(n, v) (HW_FMC_DATAW2SnU_WR(n, HW_FMC_DATAW2SnU_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_DATAW2SnU bitfields
+ */
+
+/*!
+ * @name Register FMC_DATAW2SnU, field data[31:0] (RW)
+ */
+//@{
+#define BP_FMC_DATAW2SnU_data (0U) //!< Bit position for FMC_DATAW2SnU_data.
+#define BM_FMC_DATAW2SnU_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW2SnU_data.
+#define BS_FMC_DATAW2SnU_data (32U) //!< Bit field size in bits for FMC_DATAW2SnU_data.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_DATAW2SnU_data field.
+#define BR_FMC_DATAW2SnU_data(n) (HW_FMC_DATAW2SnU(n).U)
+#endif
+
+//! @brief Format value for bitfield FMC_DATAW2SnU_data.
+#define BF_FMC_DATAW2SnU_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW2SnU_data), uint32_t) & BM_FMC_DATAW2SnU_data)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the data field to a new value.
+#define BW_FMC_DATAW2SnU_data(n, v) (HW_FMC_DATAW2SnU_WR(n, v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_FMC_DATAW2SnL - Cache Data Storage (lower word)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_DATAW2SnL - Cache Data Storage (lower word) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
+ * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
+ * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
+ * lower word, respectively. This section represents data for the lower word (bits
+ * [31:0]) of all sets in the indicated way.
+ */
+typedef union _hw_fmc_dataw2snl
+{
+ uint32_t U;
+ struct _hw_fmc_dataw2snl_bitfields
+ {
+ uint32_t data : 32; //!< [31:0] Bits [31:0] of data entry
+ } B;
+} hw_fmc_dataw2snl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_DATAW2SnL register
+ */
+//@{
+#define HW_FMC_DATAW2SnL_COUNT (4U)
+
+#define HW_FMC_DATAW2SnL_ADDR(n) (REGS_FMC_BASE + 0x244U + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_DATAW2SnL(n) (*(__IO hw_fmc_dataw2snl_t *) HW_FMC_DATAW2SnL_ADDR(n))
+#define HW_FMC_DATAW2SnL_RD(n) (HW_FMC_DATAW2SnL(n).U)
+#define HW_FMC_DATAW2SnL_WR(n, v) (HW_FMC_DATAW2SnL(n).U = (v))
+#define HW_FMC_DATAW2SnL_SET(n, v) (HW_FMC_DATAW2SnL_WR(n, HW_FMC_DATAW2SnL_RD(n) | (v)))
+#define HW_FMC_DATAW2SnL_CLR(n, v) (HW_FMC_DATAW2SnL_WR(n, HW_FMC_DATAW2SnL_RD(n) & ~(v)))
+#define HW_FMC_DATAW2SnL_TOG(n, v) (HW_FMC_DATAW2SnL_WR(n, HW_FMC_DATAW2SnL_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_DATAW2SnL bitfields
+ */
+
+/*!
+ * @name Register FMC_DATAW2SnL, field data[31:0] (RW)
+ */
+//@{
+#define BP_FMC_DATAW2SnL_data (0U) //!< Bit position for FMC_DATAW2SnL_data.
+#define BM_FMC_DATAW2SnL_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW2SnL_data.
+#define BS_FMC_DATAW2SnL_data (32U) //!< Bit field size in bits for FMC_DATAW2SnL_data.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_DATAW2SnL_data field.
+#define BR_FMC_DATAW2SnL_data(n) (HW_FMC_DATAW2SnL(n).U)
+#endif
+
+//! @brief Format value for bitfield FMC_DATAW2SnL_data.
+#define BF_FMC_DATAW2SnL_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW2SnL_data), uint32_t) & BM_FMC_DATAW2SnL_data)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the data field to a new value.
+#define BW_FMC_DATAW2SnL_data(n, v) (HW_FMC_DATAW2SnL_WR(n, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FMC_DATAW3SnU - Cache Data Storage (upper word)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_DATAW3SnU - Cache Data Storage (upper word) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
+ * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
+ * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
+ * lower word, respectively. This section represents data for the upper word (bits
+ * [63:32]) of all sets in the indicated way.
+ */
+typedef union _hw_fmc_dataw3snu
+{
+ uint32_t U;
+ struct _hw_fmc_dataw3snu_bitfields
+ {
+ uint32_t data : 32; //!< [31:0] Bits [63:32] of data entry
+ } B;
+} hw_fmc_dataw3snu_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_DATAW3SnU register
+ */
+//@{
+#define HW_FMC_DATAW3SnU_COUNT (4U)
+
+#define HW_FMC_DATAW3SnU_ADDR(n) (REGS_FMC_BASE + 0x260U + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_DATAW3SnU(n) (*(__IO hw_fmc_dataw3snu_t *) HW_FMC_DATAW3SnU_ADDR(n))
+#define HW_FMC_DATAW3SnU_RD(n) (HW_FMC_DATAW3SnU(n).U)
+#define HW_FMC_DATAW3SnU_WR(n, v) (HW_FMC_DATAW3SnU(n).U = (v))
+#define HW_FMC_DATAW3SnU_SET(n, v) (HW_FMC_DATAW3SnU_WR(n, HW_FMC_DATAW3SnU_RD(n) | (v)))
+#define HW_FMC_DATAW3SnU_CLR(n, v) (HW_FMC_DATAW3SnU_WR(n, HW_FMC_DATAW3SnU_RD(n) & ~(v)))
+#define HW_FMC_DATAW3SnU_TOG(n, v) (HW_FMC_DATAW3SnU_WR(n, HW_FMC_DATAW3SnU_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_DATAW3SnU bitfields
+ */
+
+/*!
+ * @name Register FMC_DATAW3SnU, field data[31:0] (RW)
+ */
+//@{
+#define BP_FMC_DATAW3SnU_data (0U) //!< Bit position for FMC_DATAW3SnU_data.
+#define BM_FMC_DATAW3SnU_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW3SnU_data.
+#define BS_FMC_DATAW3SnU_data (32U) //!< Bit field size in bits for FMC_DATAW3SnU_data.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_DATAW3SnU_data field.
+#define BR_FMC_DATAW3SnU_data(n) (HW_FMC_DATAW3SnU(n).U)
+#endif
+
+//! @brief Format value for bitfield FMC_DATAW3SnU_data.
+#define BF_FMC_DATAW3SnU_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW3SnU_data), uint32_t) & BM_FMC_DATAW3SnU_data)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the data field to a new value.
+#define BW_FMC_DATAW3SnU_data(n, v) (HW_FMC_DATAW3SnU_WR(n, v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_FMC_DATAW3SnL - Cache Data Storage (lower word)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FMC_DATAW3SnL - Cache Data Storage (lower word) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
+ * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
+ * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
+ * lower word, respectively. This section represents data for the lower word (bits
+ * [31:0]) of all sets in the indicated way.
+ */
+typedef union _hw_fmc_dataw3snl
+{
+ uint32_t U;
+ struct _hw_fmc_dataw3snl_bitfields
+ {
+ uint32_t data : 32; //!< [31:0] Bits [31:0] of data entry
+ } B;
+} hw_fmc_dataw3snl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FMC_DATAW3SnL register
+ */
+//@{
+#define HW_FMC_DATAW3SnL_COUNT (4U)
+
+#define HW_FMC_DATAW3SnL_ADDR(n) (REGS_FMC_BASE + 0x264U + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FMC_DATAW3SnL(n) (*(__IO hw_fmc_dataw3snl_t *) HW_FMC_DATAW3SnL_ADDR(n))
+#define HW_FMC_DATAW3SnL_RD(n) (HW_FMC_DATAW3SnL(n).U)
+#define HW_FMC_DATAW3SnL_WR(n, v) (HW_FMC_DATAW3SnL(n).U = (v))
+#define HW_FMC_DATAW3SnL_SET(n, v) (HW_FMC_DATAW3SnL_WR(n, HW_FMC_DATAW3SnL_RD(n) | (v)))
+#define HW_FMC_DATAW3SnL_CLR(n, v) (HW_FMC_DATAW3SnL_WR(n, HW_FMC_DATAW3SnL_RD(n) & ~(v)))
+#define HW_FMC_DATAW3SnL_TOG(n, v) (HW_FMC_DATAW3SnL_WR(n, HW_FMC_DATAW3SnL_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FMC_DATAW3SnL bitfields
+ */
+
+/*!
+ * @name Register FMC_DATAW3SnL, field data[31:0] (RW)
+ */
+//@{
+#define BP_FMC_DATAW3SnL_data (0U) //!< Bit position for FMC_DATAW3SnL_data.
+#define BM_FMC_DATAW3SnL_data (0xFFFFFFFFU) //!< Bit mask for FMC_DATAW3SnL_data.
+#define BS_FMC_DATAW3SnL_data (32U) //!< Bit field size in bits for FMC_DATAW3SnL_data.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FMC_DATAW3SnL_data field.
+#define BR_FMC_DATAW3SnL_data(n) (HW_FMC_DATAW3SnL(n).U)
+#endif
+
+//! @brief Format value for bitfield FMC_DATAW3SnL_data.
+#define BF_FMC_DATAW3SnL_data(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FMC_DATAW3SnL_data), uint32_t) & BM_FMC_DATAW3SnL_data)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the data field to a new value.
+#define BW_FMC_DATAW3SnL_data(n, v) (HW_FMC_DATAW3SnL_WR(n, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_fmc_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All FMC module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_fmc
+{
+ __IO hw_fmc_pfapr_t PFAPR; //!< [0x0] Flash Access Protection Register
+ __IO hw_fmc_pfb0cr_t PFB0CR; //!< [0x4] Flash Bank 0 Control Register
+ __IO hw_fmc_pfb1cr_t PFB1CR; //!< [0x8] Flash Bank 1 Control Register
+ uint8_t _reserved0[244];
+ __IO hw_fmc_tagvdw0sn_t TAGVDW0Sn[4]; //!< [0x100] Cache Tag Storage
+ __IO hw_fmc_tagvdw1sn_t TAGVDW1Sn[4]; //!< [0x110] Cache Tag Storage
+ __IO hw_fmc_tagvdw2sn_t TAGVDW2Sn[4]; //!< [0x120] Cache Tag Storage
+ __IO hw_fmc_tagvdw3sn_t TAGVDW3Sn[4]; //!< [0x130] Cache Tag Storage
+ uint8_t _reserved1[192];
+ struct {
+ __IO hw_fmc_dataw0snu_t DATAW0SnU; //!< [0x200] Cache Data Storage (upper word)
+ __IO hw_fmc_dataw0snl_t DATAW0SnL; //!< [0x204] Cache Data Storage (lower word)
+ } DATAW0Sn[4];
+ struct {
+ __IO hw_fmc_dataw1snu_t DATAW1SnU; //!< [0x220] Cache Data Storage (upper word)
+ __IO hw_fmc_dataw1snl_t DATAW1SnL; //!< [0x224] Cache Data Storage (lower word)
+ } DATAW1Sn[4];
+ struct {
+ __IO hw_fmc_dataw2snu_t DATAW2SnU; //!< [0x240] Cache Data Storage (upper word)
+ __IO hw_fmc_dataw2snl_t DATAW2SnL; //!< [0x244] Cache Data Storage (lower word)
+ } DATAW2Sn[4];
+ struct {
+ __IO hw_fmc_dataw3snu_t DATAW3SnU; //!< [0x260] Cache Data Storage (upper word)
+ __IO hw_fmc_dataw3snl_t DATAW3SnL; //!< [0x264] Cache Data Storage (lower word)
+ } DATAW3Sn[4];
+} hw_fmc_t;
+#pragma pack()
+
+//! @brief Macro to access all FMC registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_FMC</code>.
+#define HW_FMC (*(hw_fmc_t *) REGS_FMC_BASE)
+#endif
+
+#endif // __HW_FMC_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_ftfe.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,2500 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_FTFE_REGISTERS_H__
+#define __HW_FTFE_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 FTFE
+ *
+ * Flash Memory Interface
+ *
+ * Registers defined in this header file:
+ * - HW_FTFE_FSTAT - Flash Status Register
+ * - HW_FTFE_FCNFG - Flash Configuration Register
+ * - HW_FTFE_FSEC - Flash Security Register
+ * - HW_FTFE_FOPT - Flash Option Register
+ * - HW_FTFE_FCCOB3 - Flash Common Command Object Registers
+ * - HW_FTFE_FCCOB2 - Flash Common Command Object Registers
+ * - HW_FTFE_FCCOB1 - Flash Common Command Object Registers
+ * - HW_FTFE_FCCOB0 - Flash Common Command Object Registers
+ * - HW_FTFE_FCCOB7 - Flash Common Command Object Registers
+ * - HW_FTFE_FCCOB6 - Flash Common Command Object Registers
+ * - HW_FTFE_FCCOB5 - Flash Common Command Object Registers
+ * - HW_FTFE_FCCOB4 - Flash Common Command Object Registers
+ * - HW_FTFE_FCCOBB - Flash Common Command Object Registers
+ * - HW_FTFE_FCCOBA - Flash Common Command Object Registers
+ * - HW_FTFE_FCCOB9 - Flash Common Command Object Registers
+ * - HW_FTFE_FCCOB8 - Flash Common Command Object Registers
+ * - HW_FTFE_FPROT3 - Program Flash Protection Registers
+ * - HW_FTFE_FPROT2 - Program Flash Protection Registers
+ * - HW_FTFE_FPROT1 - Program Flash Protection Registers
+ * - HW_FTFE_FPROT0 - Program Flash Protection Registers
+ * - HW_FTFE_FEPROT - EEPROM Protection Register
+ * - HW_FTFE_FDPROT - Data Flash Protection Register
+ *
+ * - hw_ftfe_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_FTFE_BASE
+#define HW_FTFE_INSTANCE_COUNT (1U) //!< Number of instances of the FTFE module.
+#define REGS_FTFE_BASE (0x40020000U) //!< Base address for FTFE.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FSTAT - Flash Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FSTAT - Flash Status Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FSTAT register reports the operational status of the FTFE module. The
+ * CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The MGSTAT0
+ * bit is read only. The unassigned bits read 0 and are not writable. When set, the
+ * Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in this
+ * register prevent the launch of any more commands or writes to the FlexRAM (when
+ * EEERDY is set) until the flag is cleared (by writing a one to it).
+ */
+typedef union _hw_ftfe_fstat
+{
+ uint8_t U;
+ struct _hw_ftfe_fstat_bitfields
+ {
+ uint8_t MGSTAT0 : 1; //!< [0] Memory Controller Command Completion
+ //! Status Flag
+ uint8_t RESERVED0 : 3; //!< [3:1]
+ uint8_t FPVIOL : 1; //!< [4] Flash Protection Violation Flag
+ uint8_t ACCERR : 1; //!< [5] Flash Access Error Flag
+ uint8_t RDCOLERR : 1; //!< [6] FTFE Read Collision Error Flag
+ uint8_t CCIF : 1; //!< [7] Command Complete Interrupt Flag
+ } B;
+} hw_ftfe_fstat_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FSTAT register
+ */
+//@{
+#define HW_FTFE_FSTAT_ADDR (REGS_FTFE_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FSTAT (*(__IO hw_ftfe_fstat_t *) HW_FTFE_FSTAT_ADDR)
+#define HW_FTFE_FSTAT_RD() (HW_FTFE_FSTAT.U)
+#define HW_FTFE_FSTAT_WR(v) (HW_FTFE_FSTAT.U = (v))
+#define HW_FTFE_FSTAT_SET(v) (HW_FTFE_FSTAT_WR(HW_FTFE_FSTAT_RD() | (v)))
+#define HW_FTFE_FSTAT_CLR(v) (HW_FTFE_FSTAT_WR(HW_FTFE_FSTAT_RD() & ~(v)))
+#define HW_FTFE_FSTAT_TOG(v) (HW_FTFE_FSTAT_WR(HW_FTFE_FSTAT_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FSTAT bitfields
+ */
+
+/*!
+ * @name Register FTFE_FSTAT, field MGSTAT0[0] (RO)
+ *
+ * The MGSTAT0 status flag is set if an error is detected during execution of an
+ * FTFE command or during the flash reset sequence. As a status flag, this bit
+ * cannot (and need not) be cleared by the user like the other error flags in this
+ * register. The value of the MGSTAT0 bit for "command-N" is valid only at the
+ * end of the "command-N" execution when CCIF=1 and before the next command has
+ * been launched. At some point during the execution of "command-N+1," the previous
+ * result is discarded and any previous error is cleared.
+ */
+//@{
+#define BP_FTFE_FSTAT_MGSTAT0 (0U) //!< Bit position for FTFE_FSTAT_MGSTAT0.
+#define BM_FTFE_FSTAT_MGSTAT0 (0x01U) //!< Bit mask for FTFE_FSTAT_MGSTAT0.
+#define BS_FTFE_FSTAT_MGSTAT0 (1U) //!< Bit field size in bits for FTFE_FSTAT_MGSTAT0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FSTAT_MGSTAT0 field.
+#define BR_FTFE_FSTAT_MGSTAT0 (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_MGSTAT0))
+#endif
+//@}
+
+/*!
+ * @name Register FTFE_FSTAT, field FPVIOL[4] (W1C)
+ *
+ * The FPVIOL error bit indicates an attempt was made to program or erase an
+ * address in a protected area of program flash or data flash memory during a
+ * command write sequence or a write was attempted to a protected area of the FlexRAM
+ * while enabled for EEPROM. While FPVIOL is set, the CCIF flag cannot be cleared
+ * to launch a command. The FPVIOL bit is cleared by writing a 1 to it. Writing a
+ * 0 to the FPVIOL bit has no effect.
+ *
+ * Values:
+ * - 0 - No protection violation detected
+ * - 1 - Protection violation detected
+ */
+//@{
+#define BP_FTFE_FSTAT_FPVIOL (4U) //!< Bit position for FTFE_FSTAT_FPVIOL.
+#define BM_FTFE_FSTAT_FPVIOL (0x10U) //!< Bit mask for FTFE_FSTAT_FPVIOL.
+#define BS_FTFE_FSTAT_FPVIOL (1U) //!< Bit field size in bits for FTFE_FSTAT_FPVIOL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FSTAT_FPVIOL field.
+#define BR_FTFE_FSTAT_FPVIOL (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_FPVIOL))
+#endif
+
+//! @brief Format value for bitfield FTFE_FSTAT_FPVIOL.
+#define BF_FTFE_FSTAT_FPVIOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FSTAT_FPVIOL), uint8_t) & BM_FTFE_FSTAT_FPVIOL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FPVIOL field to a new value.
+#define BW_FTFE_FSTAT_FPVIOL(v) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_FPVIOL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTFE_FSTAT, field ACCERR[5] (W1C)
+ *
+ * The ACCERR error bit indicates an illegal access has occurred to an FTFE
+ * resource caused by a violation of the command write sequence or issuing an illegal
+ * FTFE command. While ACCERR is set, the CCIF flag cannot be cleared to launch
+ * a command. The ACCERR bit is cleared by writing a 1 to it. Writing a 0 to the
+ * ACCERR bit has no effect.
+ *
+ * Values:
+ * - 0 - No access error detected
+ * - 1 - Access error detected
+ */
+//@{
+#define BP_FTFE_FSTAT_ACCERR (5U) //!< Bit position for FTFE_FSTAT_ACCERR.
+#define BM_FTFE_FSTAT_ACCERR (0x20U) //!< Bit mask for FTFE_FSTAT_ACCERR.
+#define BS_FTFE_FSTAT_ACCERR (1U) //!< Bit field size in bits for FTFE_FSTAT_ACCERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FSTAT_ACCERR field.
+#define BR_FTFE_FSTAT_ACCERR (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_ACCERR))
+#endif
+
+//! @brief Format value for bitfield FTFE_FSTAT_ACCERR.
+#define BF_FTFE_FSTAT_ACCERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FSTAT_ACCERR), uint8_t) & BM_FTFE_FSTAT_ACCERR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ACCERR field to a new value.
+#define BW_FTFE_FSTAT_ACCERR(v) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_ACCERR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTFE_FSTAT, field RDCOLERR[6] (W1C)
+ *
+ * The RDCOLERR error bit indicates that the MCU attempted a read from an FTFE
+ * resource that was being manipulated by an FTFE command (CCIF=0). Any
+ * simultaneous access is detected as a collision error by the block arbitration logic. The
+ * read data in this case cannot be guaranteed. The RDCOLERR bit is cleared by
+ * writing a 1 to it. Writing a 0 to RDCOLERR has no effect.
+ *
+ * Values:
+ * - 0 - No collision error detected
+ * - 1 - Collision error detected
+ */
+//@{
+#define BP_FTFE_FSTAT_RDCOLERR (6U) //!< Bit position for FTFE_FSTAT_RDCOLERR.
+#define BM_FTFE_FSTAT_RDCOLERR (0x40U) //!< Bit mask for FTFE_FSTAT_RDCOLERR.
+#define BS_FTFE_FSTAT_RDCOLERR (1U) //!< Bit field size in bits for FTFE_FSTAT_RDCOLERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FSTAT_RDCOLERR field.
+#define BR_FTFE_FSTAT_RDCOLERR (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_RDCOLERR))
+#endif
+
+//! @brief Format value for bitfield FTFE_FSTAT_RDCOLERR.
+#define BF_FTFE_FSTAT_RDCOLERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FSTAT_RDCOLERR), uint8_t) & BM_FTFE_FSTAT_RDCOLERR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RDCOLERR field to a new value.
+#define BW_FTFE_FSTAT_RDCOLERR(v) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_RDCOLERR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTFE_FSTAT, field CCIF[7] (W1C)
+ *
+ * The CCIF flag indicates that a FTFE command or EEPROM file system operation
+ * has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a
+ * command, and CCIF stays low until command completion or command violation. The
+ * CCIF flag is also cleared by a successful write to FlexRAM while enabled for EEE,
+ * and CCIF stays low until the EEPROM file system has created the associated
+ * EEPROM data record. The CCIF bit is reset to 0 but is set to 1 by the memory
+ * controller at the end of the reset initialization sequence. Depending on how
+ * quickly the read occurs after reset release, the user may or may not see the 0
+ * hardware reset value.
+ *
+ * Values:
+ * - 0 - FTFE command or EEPROM file system operation in progress
+ * - 1 - FTFE command or EEPROM file system operation has completed
+ */
+//@{
+#define BP_FTFE_FSTAT_CCIF (7U) //!< Bit position for FTFE_FSTAT_CCIF.
+#define BM_FTFE_FSTAT_CCIF (0x80U) //!< Bit mask for FTFE_FSTAT_CCIF.
+#define BS_FTFE_FSTAT_CCIF (1U) //!< Bit field size in bits for FTFE_FSTAT_CCIF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FSTAT_CCIF field.
+#define BR_FTFE_FSTAT_CCIF (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_CCIF))
+#endif
+
+//! @brief Format value for bitfield FTFE_FSTAT_CCIF.
+#define BF_FTFE_FSTAT_CCIF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FSTAT_CCIF), uint8_t) & BM_FTFE_FSTAT_CCIF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCIF field to a new value.
+#define BW_FTFE_FSTAT_CCIF(v) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR, BP_FTFE_FSTAT_CCIF) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FCNFG - Flash Configuration Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FCNFG - Flash Configuration Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides information on the current functional state of the
+ * FTFE module. The erase control bits (ERSAREQ and ERSSUSP) have write
+ * restrictions. SWAP, PFLSH, RAMRDY, and EEERDY are read-only status bits. The unassigned
+ * bits read as noted and are not writable. The reset values for the SWAP, PFLSH,
+ * RAMRDY, and EEERDY bits are determined during the reset sequence.
+ */
+typedef union _hw_ftfe_fcnfg
+{
+ uint8_t U;
+ struct _hw_ftfe_fcnfg_bitfields
+ {
+ uint8_t EEERDY : 1; //!< [0]
+ uint8_t RAMRDY : 1; //!< [1] RAM Ready
+ uint8_t PFLSH : 1; //!< [2] FTFE configuration
+ uint8_t SWAP : 1; //!< [3] Swap
+ uint8_t ERSSUSP : 1; //!< [4] Erase Suspend
+ uint8_t ERSAREQ : 1; //!< [5] Erase All Request
+ uint8_t RDCOLLIE : 1; //!< [6] Read Collision Error Interrupt Enable
+ uint8_t CCIE : 1; //!< [7] Command Complete Interrupt Enable
+ } B;
+} hw_ftfe_fcnfg_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FCNFG register
+ */
+//@{
+#define HW_FTFE_FCNFG_ADDR (REGS_FTFE_BASE + 0x1U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FCNFG (*(__IO hw_ftfe_fcnfg_t *) HW_FTFE_FCNFG_ADDR)
+#define HW_FTFE_FCNFG_RD() (HW_FTFE_FCNFG.U)
+#define HW_FTFE_FCNFG_WR(v) (HW_FTFE_FCNFG.U = (v))
+#define HW_FTFE_FCNFG_SET(v) (HW_FTFE_FCNFG_WR(HW_FTFE_FCNFG_RD() | (v)))
+#define HW_FTFE_FCNFG_CLR(v) (HW_FTFE_FCNFG_WR(HW_FTFE_FCNFG_RD() & ~(v)))
+#define HW_FTFE_FCNFG_TOG(v) (HW_FTFE_FCNFG_WR(HW_FTFE_FCNFG_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FCNFG bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCNFG, field EEERDY[0] (RO)
+ *
+ * For devices with FlexNVM: This flag indicates if the EEPROM backup data has
+ * been copied to the FlexRAM and is therefore available for read access. During
+ * the reset sequence, the EEERDY flag remains clear while CCIF=0 and only sets if
+ * the FlexNVM block is partitioned for EEPROM. For devices without FlexNVM:
+ * This bit is reserved.
+ *
+ * Values:
+ * - 0 - For devices with FlexNVM: FlexRAM is not available for EEPROM operation.
+ * - 1 - For devices with FlexNVM: FlexRAM is available for EEPROM operations
+ * where: reads from the FlexRAM return data previously written to the FlexRAM
+ * in EEPROM mode and writes launch an EEPROM operation to store the written
+ * data in the FlexRAM and EEPROM backup.
+ */
+//@{
+#define BP_FTFE_FCNFG_EEERDY (0U) //!< Bit position for FTFE_FCNFG_EEERDY.
+#define BM_FTFE_FCNFG_EEERDY (0x01U) //!< Bit mask for FTFE_FCNFG_EEERDY.
+#define BS_FTFE_FCNFG_EEERDY (1U) //!< Bit field size in bits for FTFE_FCNFG_EEERDY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCNFG_EEERDY field.
+#define BR_FTFE_FCNFG_EEERDY (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_EEERDY))
+#endif
+//@}
+
+/*!
+ * @name Register FTFE_FCNFG, field RAMRDY[1] (RO)
+ *
+ * This flag indicates the current status of the FlexRAM/ programming
+ * acceleration RAM. For devices with FlexNVM: The state of the RAMRDY flag is normally
+ * controlled by the Set FlexRAM Function command. During the reset sequence, the
+ * RAMRDY flag is cleared if the FlexNVM block is partitioned for EEPROM and will
+ * be set if the FlexNVM block is not partitioned for EEPROM . The RAMRDY flag is
+ * cleared if the Program Partition command is run to partition the FlexNVM block
+ * for EEPROM. The RAMRDY flag sets after completion of the Erase All Blocks
+ * command or execution of the erase-all operation triggered external to the FTFE.
+ * For devices without FlexNVM: This bit should always be set.
+ *
+ * Values:
+ * - 0 - For devices with FlexNVM: FlexRAM is not available for traditional RAM
+ * access. For devices without FlexNVM: Programming acceleration RAM is not
+ * available.
+ * - 1 - For devices with FlexNVM: FlexRAM is available as traditional RAM only;
+ * writes to the FlexRAM do not trigger EEPROM operations. For devices
+ * without FlexNVM: Programming acceleration RAM is available.
+ */
+//@{
+#define BP_FTFE_FCNFG_RAMRDY (1U) //!< Bit position for FTFE_FCNFG_RAMRDY.
+#define BM_FTFE_FCNFG_RAMRDY (0x02U) //!< Bit mask for FTFE_FCNFG_RAMRDY.
+#define BS_FTFE_FCNFG_RAMRDY (1U) //!< Bit field size in bits for FTFE_FCNFG_RAMRDY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCNFG_RAMRDY field.
+#define BR_FTFE_FCNFG_RAMRDY (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_RAMRDY))
+#endif
+//@}
+
+/*!
+ * @name Register FTFE_FCNFG, field PFLSH[2] (RO)
+ *
+ * Values:
+ * - 0 - For devices with FlexNVM: FTFE configuration supports two program flash
+ * blocks and two FlexNVM blocks For devices with program flash only:
+ * Reserved
+ * - 1 - For devices with FlexNVM: Reserved For devices with program flash only:
+ * FTFE configuration supports four program flash blocks
+ */
+//@{
+#define BP_FTFE_FCNFG_PFLSH (2U) //!< Bit position for FTFE_FCNFG_PFLSH.
+#define BM_FTFE_FCNFG_PFLSH (0x04U) //!< Bit mask for FTFE_FCNFG_PFLSH.
+#define BS_FTFE_FCNFG_PFLSH (1U) //!< Bit field size in bits for FTFE_FCNFG_PFLSH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCNFG_PFLSH field.
+#define BR_FTFE_FCNFG_PFLSH (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_PFLSH))
+#endif
+//@}
+
+/*!
+ * @name Register FTFE_FCNFG, field SWAP[3] (RO)
+ *
+ * The SWAP flag indicates which half of the program flash space is located at
+ * relative address 0x0000. The state of the SWAP flag is set by the FTFE during
+ * the reset sequence. See for information on swap management.
+ *
+ * Values:
+ * - 0 - For devices with FlexNVM: Program flash 0 block is located at relative
+ * address 0x0000 For devices with program flash only: Program flash 0 block
+ * is located at relative address 0x0000
+ * - 1 - For devices with FlexNVM: Reserved For devices with program flash only:
+ * Program flash 1 block is located at relative address 0x0000
+ */
+//@{
+#define BP_FTFE_FCNFG_SWAP (3U) //!< Bit position for FTFE_FCNFG_SWAP.
+#define BM_FTFE_FCNFG_SWAP (0x08U) //!< Bit mask for FTFE_FCNFG_SWAP.
+#define BS_FTFE_FCNFG_SWAP (1U) //!< Bit field size in bits for FTFE_FCNFG_SWAP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCNFG_SWAP field.
+#define BR_FTFE_FCNFG_SWAP (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_SWAP))
+#endif
+//@}
+
+/*!
+ * @name Register FTFE_FCNFG, field ERSSUSP[4] (RW)
+ *
+ * The ERSSUSP bit allows the user to suspend (interrupt) the Erase Flash Sector
+ * command while it is executing.
+ *
+ * Values:
+ * - 0 - No suspend requested
+ * - 1 - Suspend the current Erase Flash Sector command execution.
+ */
+//@{
+#define BP_FTFE_FCNFG_ERSSUSP (4U) //!< Bit position for FTFE_FCNFG_ERSSUSP.
+#define BM_FTFE_FCNFG_ERSSUSP (0x10U) //!< Bit mask for FTFE_FCNFG_ERSSUSP.
+#define BS_FTFE_FCNFG_ERSSUSP (1U) //!< Bit field size in bits for FTFE_FCNFG_ERSSUSP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCNFG_ERSSUSP field.
+#define BR_FTFE_FCNFG_ERSSUSP (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_ERSSUSP))
+#endif
+
+//! @brief Format value for bitfield FTFE_FCNFG_ERSSUSP.
+#define BF_FTFE_FCNFG_ERSSUSP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCNFG_ERSSUSP), uint8_t) & BM_FTFE_FCNFG_ERSSUSP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERSSUSP field to a new value.
+#define BW_FTFE_FCNFG_ERSSUSP(v) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_ERSSUSP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTFE_FCNFG, field ERSAREQ[5] (RO)
+ *
+ * This bit issues a request to the memory controller to execute the Erase All
+ * Blocks command and release security. ERSAREQ is not directly writable but is
+ * under indirect user control. Refer to the device's Chip Configuration details on
+ * how to request this command. The ERSAREQ bit sets when an erase all request
+ * is triggered external to the FTFE and CCIF is set (no command is currently
+ * being executed). ERSAREQ is cleared by the FTFE when the operation completes.
+ *
+ * Values:
+ * - 0 - No request or request complete
+ * - 1 - Request to: run the Erase All Blocks command, verify the erased state,
+ * program the security byte in the Flash Configuration Field to the unsecure
+ * state, and release MCU security by setting the FSEC[SEC] field to the
+ * unsecure state.
+ */
+//@{
+#define BP_FTFE_FCNFG_ERSAREQ (5U) //!< Bit position for FTFE_FCNFG_ERSAREQ.
+#define BM_FTFE_FCNFG_ERSAREQ (0x20U) //!< Bit mask for FTFE_FCNFG_ERSAREQ.
+#define BS_FTFE_FCNFG_ERSAREQ (1U) //!< Bit field size in bits for FTFE_FCNFG_ERSAREQ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCNFG_ERSAREQ field.
+#define BR_FTFE_FCNFG_ERSAREQ (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_ERSAREQ))
+#endif
+//@}
+
+/*!
+ * @name Register FTFE_FCNFG, field RDCOLLIE[6] (RW)
+ *
+ * The RDCOLLIE bit controls interrupt generation when an FTFE read collision
+ * error occurs.
+ *
+ * Values:
+ * - 0 - Read collision error interrupt disabled
+ * - 1 - Read collision error interrupt enabled. An interrupt request is
+ * generated whenever an FTFE read collision error is detected (see the description
+ * of FSTAT[RDCOLERR]).
+ */
+//@{
+#define BP_FTFE_FCNFG_RDCOLLIE (6U) //!< Bit position for FTFE_FCNFG_RDCOLLIE.
+#define BM_FTFE_FCNFG_RDCOLLIE (0x40U) //!< Bit mask for FTFE_FCNFG_RDCOLLIE.
+#define BS_FTFE_FCNFG_RDCOLLIE (1U) //!< Bit field size in bits for FTFE_FCNFG_RDCOLLIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCNFG_RDCOLLIE field.
+#define BR_FTFE_FCNFG_RDCOLLIE (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_RDCOLLIE))
+#endif
+
+//! @brief Format value for bitfield FTFE_FCNFG_RDCOLLIE.
+#define BF_FTFE_FCNFG_RDCOLLIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCNFG_RDCOLLIE), uint8_t) & BM_FTFE_FCNFG_RDCOLLIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RDCOLLIE field to a new value.
+#define BW_FTFE_FCNFG_RDCOLLIE(v) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_RDCOLLIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTFE_FCNFG, field CCIE[7] (RW)
+ *
+ * The CCIE bit controls interrupt generation when an FTFE command completes.
+ *
+ * Values:
+ * - 0 - Command complete interrupt disabled
+ * - 1 - Command complete interrupt enabled. An interrupt request is generated
+ * whenever the FSTAT[CCIF] flag is set.
+ */
+//@{
+#define BP_FTFE_FCNFG_CCIE (7U) //!< Bit position for FTFE_FCNFG_CCIE.
+#define BM_FTFE_FCNFG_CCIE (0x80U) //!< Bit mask for FTFE_FCNFG_CCIE.
+#define BS_FTFE_FCNFG_CCIE (1U) //!< Bit field size in bits for FTFE_FCNFG_CCIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCNFG_CCIE field.
+#define BR_FTFE_FCNFG_CCIE (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_CCIE))
+#endif
+
+//! @brief Format value for bitfield FTFE_FCNFG_CCIE.
+#define BF_FTFE_FCNFG_CCIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCNFG_CCIE), uint8_t) & BM_FTFE_FCNFG_CCIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCIE field to a new value.
+#define BW_FTFE_FCNFG_CCIE(v) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR, BP_FTFE_FCNFG_CCIE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FSEC - Flash Security Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FSEC - Flash Security Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This read-only register holds all bits associated with the security of the
+ * MCU and FTFE module. During the reset sequence, the register is loaded with the
+ * contents of the flash security byte in the Flash Configuration Field located
+ * in program flash memory. The Flash basis for the values is signified by X in
+ * the reset value.
+ */
+typedef union _hw_ftfe_fsec
+{
+ uint8_t U;
+ struct _hw_ftfe_fsec_bitfields
+ {
+ uint8_t SEC : 2; //!< [1:0] Flash Security
+ uint8_t FSLACC : 2; //!< [3:2] Freescale Failure Analysis Access Code
+ uint8_t MEEN : 2; //!< [5:4] Mass Erase Enable Bits
+ uint8_t KEYEN : 2; //!< [7:6] Backdoor Key Security Enable
+ } B;
+} hw_ftfe_fsec_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FSEC register
+ */
+//@{
+#define HW_FTFE_FSEC_ADDR (REGS_FTFE_BASE + 0x2U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FSEC (*(__I hw_ftfe_fsec_t *) HW_FTFE_FSEC_ADDR)
+#define HW_FTFE_FSEC_RD() (HW_FTFE_FSEC.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FSEC bitfields
+ */
+
+/*!
+ * @name Register FTFE_FSEC, field SEC[1:0] (RO)
+ *
+ * These bits define the security state of the MCU. In the secure state, the MCU
+ * limits access to FTFE module resources. The limitations are defined per
+ * device and are detailed in the Chip Configuration details. If the FTFE module is
+ * unsecured using backdoor key access, the SEC bits are forced to 10b.
+ *
+ * Values:
+ * - 00 - MCU security status is secure
+ * - 01 - MCU security status is secure
+ * - 10 - MCU security status is unsecure (The standard shipping condition of
+ * the FTFE is unsecure.)
+ * - 11 - MCU security status is secure
+ */
+//@{
+#define BP_FTFE_FSEC_SEC (0U) //!< Bit position for FTFE_FSEC_SEC.
+#define BM_FTFE_FSEC_SEC (0x03U) //!< Bit mask for FTFE_FSEC_SEC.
+#define BS_FTFE_FSEC_SEC (2U) //!< Bit field size in bits for FTFE_FSEC_SEC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FSEC_SEC field.
+#define BR_FTFE_FSEC_SEC (HW_FTFE_FSEC.B.SEC)
+#endif
+//@}
+
+/*!
+ * @name Register FTFE_FSEC, field FSLACC[3:2] (RO)
+ *
+ * These bits enable or disable access to the flash memory contents during
+ * returned part failure analysis at Freescale. When SEC is secure and FSLACC is
+ * denied, access to the program flash contents is denied and any failure analysis
+ * performed by Freescale factory test must begin with a full erase to unsecure the
+ * part. When access is granted (SEC is unsecure, or SEC is secure and FSLACC is
+ * granted), Freescale factory testing has visibility of the current flash
+ * contents. The state of the FSLACC bits is only relevant when the SEC bits are set to
+ * secure. When the SEC field is set to unsecure, the FSLACC setting does not
+ * matter.
+ *
+ * Values:
+ * - 00 - Freescale factory access granted
+ * - 01 - Freescale factory access denied
+ * - 10 - Freescale factory access denied
+ * - 11 - Freescale factory access granted
+ */
+//@{
+#define BP_FTFE_FSEC_FSLACC (2U) //!< Bit position for FTFE_FSEC_FSLACC.
+#define BM_FTFE_FSEC_FSLACC (0x0CU) //!< Bit mask for FTFE_FSEC_FSLACC.
+#define BS_FTFE_FSEC_FSLACC (2U) //!< Bit field size in bits for FTFE_FSEC_FSLACC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FSEC_FSLACC field.
+#define BR_FTFE_FSEC_FSLACC (HW_FTFE_FSEC.B.FSLACC)
+#endif
+//@}
+
+/*!
+ * @name Register FTFE_FSEC, field MEEN[5:4] (RO)
+ *
+ * Enables and disables mass erase capability of the FTFE module. The state of
+ * the MEEN bits is only relevant when the SEC bits are set to secure outside of
+ * NVM Normal Mode. When the SEC field is set to unsecure, the MEEN setting does
+ * not matter.
+ *
+ * Values:
+ * - 00 - Mass erase is enabled
+ * - 01 - Mass erase is enabled
+ * - 10 - Mass erase is disabled
+ * - 11 - Mass erase is enabled
+ */
+//@{
+#define BP_FTFE_FSEC_MEEN (4U) //!< Bit position for FTFE_FSEC_MEEN.
+#define BM_FTFE_FSEC_MEEN (0x30U) //!< Bit mask for FTFE_FSEC_MEEN.
+#define BS_FTFE_FSEC_MEEN (2U) //!< Bit field size in bits for FTFE_FSEC_MEEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FSEC_MEEN field.
+#define BR_FTFE_FSEC_MEEN (HW_FTFE_FSEC.B.MEEN)
+#endif
+//@}
+
+/*!
+ * @name Register FTFE_FSEC, field KEYEN[7:6] (RO)
+ *
+ * These bits enable and disable backdoor key access to the FTFE module.
+ *
+ * Values:
+ * - 00 - Backdoor key access disabled
+ * - 01 - Backdoor key access disabled (preferred KEYEN state to disable
+ * backdoor key access)
+ * - 10 - Backdoor key access enabled
+ * - 11 - Backdoor key access disabled
+ */
+//@{
+#define BP_FTFE_FSEC_KEYEN (6U) //!< Bit position for FTFE_FSEC_KEYEN.
+#define BM_FTFE_FSEC_KEYEN (0xC0U) //!< Bit mask for FTFE_FSEC_KEYEN.
+#define BS_FTFE_FSEC_KEYEN (2U) //!< Bit field size in bits for FTFE_FSEC_KEYEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FSEC_KEYEN field.
+#define BR_FTFE_FSEC_KEYEN (HW_FTFE_FSEC.B.KEYEN)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FOPT - Flash Option Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FOPT - Flash Option Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * The flash option register allows the MCU to customize its operations by
+ * examining the state of these read-only bits, which are loaded from NVM at reset.
+ * The function of the bits is defined in the device's Chip Configuration details.
+ * All bits in the register are read-only. During the reset sequence, the
+ * register is loaded from the flash nonvolatile option byte in the Flash Configuration
+ * Field located in program flash memory. The flash basis for the values is
+ * signified by X in the reset value.
+ */
+typedef union _hw_ftfe_fopt
+{
+ uint8_t U;
+ struct _hw_ftfe_fopt_bitfields
+ {
+ uint8_t OPT : 8; //!< [7:0] Nonvolatile Option
+ } B;
+} hw_ftfe_fopt_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FOPT register
+ */
+//@{
+#define HW_FTFE_FOPT_ADDR (REGS_FTFE_BASE + 0x3U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FOPT (*(__I hw_ftfe_fopt_t *) HW_FTFE_FOPT_ADDR)
+#define HW_FTFE_FOPT_RD() (HW_FTFE_FOPT.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FOPT bitfields
+ */
+
+/*!
+ * @name Register FTFE_FOPT, field OPT[7:0] (RO)
+ *
+ * These bits are loaded from flash to this register at reset. Refer to the
+ * device's Chip Configuration details for the definition and use of these bits.
+ */
+//@{
+#define BP_FTFE_FOPT_OPT (0U) //!< Bit position for FTFE_FOPT_OPT.
+#define BM_FTFE_FOPT_OPT (0xFFU) //!< Bit mask for FTFE_FOPT_OPT.
+#define BS_FTFE_FOPT_OPT (8U) //!< Bit field size in bits for FTFE_FOPT_OPT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FOPT_OPT field.
+#define BR_FTFE_FOPT_OPT (HW_FTFE_FOPT.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FCCOB3 - Flash Common Command Object Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FCCOB3 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+typedef union _hw_ftfe_fccob3
+{
+ uint8_t U;
+ struct _hw_ftfe_fccob3_bitfields
+ {
+ uint8_t CCOBn : 8; //!< [7:0]
+ } B;
+} hw_ftfe_fccob3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB3 register
+ */
+//@{
+#define HW_FTFE_FCCOB3_ADDR (REGS_FTFE_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FCCOB3 (*(__IO hw_ftfe_fccob3_t *) HW_FTFE_FCCOB3_ADDR)
+#define HW_FTFE_FCCOB3_RD() (HW_FTFE_FCCOB3.U)
+#define HW_FTFE_FCCOB3_WR(v) (HW_FTFE_FCCOB3.U = (v))
+#define HW_FTFE_FCCOB3_SET(v) (HW_FTFE_FCCOB3_WR(HW_FTFE_FCCOB3_RD() | (v)))
+#define HW_FTFE_FCCOB3_CLR(v) (HW_FTFE_FCCOB3_WR(HW_FTFE_FCCOB3_RD() & ~(v)))
+#define HW_FTFE_FCCOB3_TOG(v) (HW_FTFE_FCCOB3_WR(HW_FTFE_FCCOB3_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FCCOB3 bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCCOB3, field CCOBn[7:0] (RW)
+ *
+ * The FCCOB register provides a command code and relevant parameters to the
+ * memory controller. The individual registers that compose the FCCOB data set can
+ * be written in any order, but you must provide all needed values, which vary
+ * from command to command. First, set up all required FCCOB fields and then
+ * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
+ * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
+ * by the user until the command completes (CCIF returns to 1). No command
+ * buffering or queueing is provided; the next command can be loaded only after the
+ * current command completes. Some commands return information to the FCCOB
+ * registers. Any values returned to FCCOB are available for reading after the
+ * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
+ * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
+ * the command code. This 8-bit value defines the command to be executed. The
+ * command code is followed by the parameters required for this specific FTFE command,
+ * typically an address and/or data values. The command parameter table is
+ * written in terms of FCCOB Number (which is equivalent to the byte number). This
+ * number is a reference to the FCCOB register name and is not the register address.
+ * FCCOB NumberRefers to FCCOB register name, not register address Typical
+ * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
+ * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
+ * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
+ * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
+ * register group uses a big endian addressing convention. For all command parameter
+ * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
+ * register number. The FCCOB register group may be read and written as
+ * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
+ */
+//@{
+#define BP_FTFE_FCCOB3_CCOBn (0U) //!< Bit position for FTFE_FCCOB3_CCOBn.
+#define BM_FTFE_FCCOB3_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB3_CCOBn.
+#define BS_FTFE_FCCOB3_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB3_CCOBn.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCCOB3_CCOBn field.
+#define BR_FTFE_FCCOB3_CCOBn (HW_FTFE_FCCOB3.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FCCOB3_CCOBn.
+#define BF_FTFE_FCCOB3_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB3_CCOBn), uint8_t) & BM_FTFE_FCCOB3_CCOBn)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCOBn field to a new value.
+#define BW_FTFE_FCCOB3_CCOBn(v) (HW_FTFE_FCCOB3_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FCCOB2 - Flash Common Command Object Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FCCOB2 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+typedef union _hw_ftfe_fccob2
+{
+ uint8_t U;
+ struct _hw_ftfe_fccob2_bitfields
+ {
+ uint8_t CCOBn : 8; //!< [7:0]
+ } B;
+} hw_ftfe_fccob2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB2 register
+ */
+//@{
+#define HW_FTFE_FCCOB2_ADDR (REGS_FTFE_BASE + 0x5U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FCCOB2 (*(__IO hw_ftfe_fccob2_t *) HW_FTFE_FCCOB2_ADDR)
+#define HW_FTFE_FCCOB2_RD() (HW_FTFE_FCCOB2.U)
+#define HW_FTFE_FCCOB2_WR(v) (HW_FTFE_FCCOB2.U = (v))
+#define HW_FTFE_FCCOB2_SET(v) (HW_FTFE_FCCOB2_WR(HW_FTFE_FCCOB2_RD() | (v)))
+#define HW_FTFE_FCCOB2_CLR(v) (HW_FTFE_FCCOB2_WR(HW_FTFE_FCCOB2_RD() & ~(v)))
+#define HW_FTFE_FCCOB2_TOG(v) (HW_FTFE_FCCOB2_WR(HW_FTFE_FCCOB2_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FCCOB2 bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCCOB2, field CCOBn[7:0] (RW)
+ *
+ * The FCCOB register provides a command code and relevant parameters to the
+ * memory controller. The individual registers that compose the FCCOB data set can
+ * be written in any order, but you must provide all needed values, which vary
+ * from command to command. First, set up all required FCCOB fields and then
+ * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
+ * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
+ * by the user until the command completes (CCIF returns to 1). No command
+ * buffering or queueing is provided; the next command can be loaded only after the
+ * current command completes. Some commands return information to the FCCOB
+ * registers. Any values returned to FCCOB are available for reading after the
+ * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
+ * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
+ * the command code. This 8-bit value defines the command to be executed. The
+ * command code is followed by the parameters required for this specific FTFE command,
+ * typically an address and/or data values. The command parameter table is
+ * written in terms of FCCOB Number (which is equivalent to the byte number). This
+ * number is a reference to the FCCOB register name and is not the register address.
+ * FCCOB NumberRefers to FCCOB register name, not register address Typical
+ * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
+ * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
+ * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
+ * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
+ * register group uses a big endian addressing convention. For all command parameter
+ * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
+ * register number. The FCCOB register group may be read and written as
+ * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
+ */
+//@{
+#define BP_FTFE_FCCOB2_CCOBn (0U) //!< Bit position for FTFE_FCCOB2_CCOBn.
+#define BM_FTFE_FCCOB2_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB2_CCOBn.
+#define BS_FTFE_FCCOB2_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB2_CCOBn.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCCOB2_CCOBn field.
+#define BR_FTFE_FCCOB2_CCOBn (HW_FTFE_FCCOB2.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FCCOB2_CCOBn.
+#define BF_FTFE_FCCOB2_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB2_CCOBn), uint8_t) & BM_FTFE_FCCOB2_CCOBn)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCOBn field to a new value.
+#define BW_FTFE_FCCOB2_CCOBn(v) (HW_FTFE_FCCOB2_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FCCOB1 - Flash Common Command Object Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FCCOB1 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+typedef union _hw_ftfe_fccob1
+{
+ uint8_t U;
+ struct _hw_ftfe_fccob1_bitfields
+ {
+ uint8_t CCOBn : 8; //!< [7:0]
+ } B;
+} hw_ftfe_fccob1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB1 register
+ */
+//@{
+#define HW_FTFE_FCCOB1_ADDR (REGS_FTFE_BASE + 0x6U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FCCOB1 (*(__IO hw_ftfe_fccob1_t *) HW_FTFE_FCCOB1_ADDR)
+#define HW_FTFE_FCCOB1_RD() (HW_FTFE_FCCOB1.U)
+#define HW_FTFE_FCCOB1_WR(v) (HW_FTFE_FCCOB1.U = (v))
+#define HW_FTFE_FCCOB1_SET(v) (HW_FTFE_FCCOB1_WR(HW_FTFE_FCCOB1_RD() | (v)))
+#define HW_FTFE_FCCOB1_CLR(v) (HW_FTFE_FCCOB1_WR(HW_FTFE_FCCOB1_RD() & ~(v)))
+#define HW_FTFE_FCCOB1_TOG(v) (HW_FTFE_FCCOB1_WR(HW_FTFE_FCCOB1_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FCCOB1 bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCCOB1, field CCOBn[7:0] (RW)
+ *
+ * The FCCOB register provides a command code and relevant parameters to the
+ * memory controller. The individual registers that compose the FCCOB data set can
+ * be written in any order, but you must provide all needed values, which vary
+ * from command to command. First, set up all required FCCOB fields and then
+ * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
+ * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
+ * by the user until the command completes (CCIF returns to 1). No command
+ * buffering or queueing is provided; the next command can be loaded only after the
+ * current command completes. Some commands return information to the FCCOB
+ * registers. Any values returned to FCCOB are available for reading after the
+ * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
+ * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
+ * the command code. This 8-bit value defines the command to be executed. The
+ * command code is followed by the parameters required for this specific FTFE command,
+ * typically an address and/or data values. The command parameter table is
+ * written in terms of FCCOB Number (which is equivalent to the byte number). This
+ * number is a reference to the FCCOB register name and is not the register address.
+ * FCCOB NumberRefers to FCCOB register name, not register address Typical
+ * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
+ * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
+ * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
+ * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
+ * register group uses a big endian addressing convention. For all command parameter
+ * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
+ * register number. The FCCOB register group may be read and written as
+ * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
+ */
+//@{
+#define BP_FTFE_FCCOB1_CCOBn (0U) //!< Bit position for FTFE_FCCOB1_CCOBn.
+#define BM_FTFE_FCCOB1_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB1_CCOBn.
+#define BS_FTFE_FCCOB1_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB1_CCOBn.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCCOB1_CCOBn field.
+#define BR_FTFE_FCCOB1_CCOBn (HW_FTFE_FCCOB1.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FCCOB1_CCOBn.
+#define BF_FTFE_FCCOB1_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB1_CCOBn), uint8_t) & BM_FTFE_FCCOB1_CCOBn)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCOBn field to a new value.
+#define BW_FTFE_FCCOB1_CCOBn(v) (HW_FTFE_FCCOB1_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FCCOB0 - Flash Common Command Object Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FCCOB0 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+typedef union _hw_ftfe_fccob0
+{
+ uint8_t U;
+ struct _hw_ftfe_fccob0_bitfields
+ {
+ uint8_t CCOBn : 8; //!< [7:0]
+ } B;
+} hw_ftfe_fccob0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB0 register
+ */
+//@{
+#define HW_FTFE_FCCOB0_ADDR (REGS_FTFE_BASE + 0x7U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FCCOB0 (*(__IO hw_ftfe_fccob0_t *) HW_FTFE_FCCOB0_ADDR)
+#define HW_FTFE_FCCOB0_RD() (HW_FTFE_FCCOB0.U)
+#define HW_FTFE_FCCOB0_WR(v) (HW_FTFE_FCCOB0.U = (v))
+#define HW_FTFE_FCCOB0_SET(v) (HW_FTFE_FCCOB0_WR(HW_FTFE_FCCOB0_RD() | (v)))
+#define HW_FTFE_FCCOB0_CLR(v) (HW_FTFE_FCCOB0_WR(HW_FTFE_FCCOB0_RD() & ~(v)))
+#define HW_FTFE_FCCOB0_TOG(v) (HW_FTFE_FCCOB0_WR(HW_FTFE_FCCOB0_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FCCOB0 bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCCOB0, field CCOBn[7:0] (RW)
+ *
+ * The FCCOB register provides a command code and relevant parameters to the
+ * memory controller. The individual registers that compose the FCCOB data set can
+ * be written in any order, but you must provide all needed values, which vary
+ * from command to command. First, set up all required FCCOB fields and then
+ * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
+ * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
+ * by the user until the command completes (CCIF returns to 1). No command
+ * buffering or queueing is provided; the next command can be loaded only after the
+ * current command completes. Some commands return information to the FCCOB
+ * registers. Any values returned to FCCOB are available for reading after the
+ * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
+ * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
+ * the command code. This 8-bit value defines the command to be executed. The
+ * command code is followed by the parameters required for this specific FTFE command,
+ * typically an address and/or data values. The command parameter table is
+ * written in terms of FCCOB Number (which is equivalent to the byte number). This
+ * number is a reference to the FCCOB register name and is not the register address.
+ * FCCOB NumberRefers to FCCOB register name, not register address Typical
+ * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
+ * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
+ * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
+ * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
+ * register group uses a big endian addressing convention. For all command parameter
+ * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
+ * register number. The FCCOB register group may be read and written as
+ * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
+ */
+//@{
+#define BP_FTFE_FCCOB0_CCOBn (0U) //!< Bit position for FTFE_FCCOB0_CCOBn.
+#define BM_FTFE_FCCOB0_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB0_CCOBn.
+#define BS_FTFE_FCCOB0_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB0_CCOBn.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCCOB0_CCOBn field.
+#define BR_FTFE_FCCOB0_CCOBn (HW_FTFE_FCCOB0.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FCCOB0_CCOBn.
+#define BF_FTFE_FCCOB0_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB0_CCOBn), uint8_t) & BM_FTFE_FCCOB0_CCOBn)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCOBn field to a new value.
+#define BW_FTFE_FCCOB0_CCOBn(v) (HW_FTFE_FCCOB0_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FCCOB7 - Flash Common Command Object Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FCCOB7 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+typedef union _hw_ftfe_fccob7
+{
+ uint8_t U;
+ struct _hw_ftfe_fccob7_bitfields
+ {
+ uint8_t CCOBn : 8; //!< [7:0]
+ } B;
+} hw_ftfe_fccob7_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB7 register
+ */
+//@{
+#define HW_FTFE_FCCOB7_ADDR (REGS_FTFE_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FCCOB7 (*(__IO hw_ftfe_fccob7_t *) HW_FTFE_FCCOB7_ADDR)
+#define HW_FTFE_FCCOB7_RD() (HW_FTFE_FCCOB7.U)
+#define HW_FTFE_FCCOB7_WR(v) (HW_FTFE_FCCOB7.U = (v))
+#define HW_FTFE_FCCOB7_SET(v) (HW_FTFE_FCCOB7_WR(HW_FTFE_FCCOB7_RD() | (v)))
+#define HW_FTFE_FCCOB7_CLR(v) (HW_FTFE_FCCOB7_WR(HW_FTFE_FCCOB7_RD() & ~(v)))
+#define HW_FTFE_FCCOB7_TOG(v) (HW_FTFE_FCCOB7_WR(HW_FTFE_FCCOB7_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FCCOB7 bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCCOB7, field CCOBn[7:0] (RW)
+ *
+ * The FCCOB register provides a command code and relevant parameters to the
+ * memory controller. The individual registers that compose the FCCOB data set can
+ * be written in any order, but you must provide all needed values, which vary
+ * from command to command. First, set up all required FCCOB fields and then
+ * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
+ * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
+ * by the user until the command completes (CCIF returns to 1). No command
+ * buffering or queueing is provided; the next command can be loaded only after the
+ * current command completes. Some commands return information to the FCCOB
+ * registers. Any values returned to FCCOB are available for reading after the
+ * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
+ * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
+ * the command code. This 8-bit value defines the command to be executed. The
+ * command code is followed by the parameters required for this specific FTFE command,
+ * typically an address and/or data values. The command parameter table is
+ * written in terms of FCCOB Number (which is equivalent to the byte number). This
+ * number is a reference to the FCCOB register name and is not the register address.
+ * FCCOB NumberRefers to FCCOB register name, not register address Typical
+ * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
+ * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
+ * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
+ * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
+ * register group uses a big endian addressing convention. For all command parameter
+ * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
+ * register number. The FCCOB register group may be read and written as
+ * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
+ */
+//@{
+#define BP_FTFE_FCCOB7_CCOBn (0U) //!< Bit position for FTFE_FCCOB7_CCOBn.
+#define BM_FTFE_FCCOB7_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB7_CCOBn.
+#define BS_FTFE_FCCOB7_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB7_CCOBn.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCCOB7_CCOBn field.
+#define BR_FTFE_FCCOB7_CCOBn (HW_FTFE_FCCOB7.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FCCOB7_CCOBn.
+#define BF_FTFE_FCCOB7_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB7_CCOBn), uint8_t) & BM_FTFE_FCCOB7_CCOBn)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCOBn field to a new value.
+#define BW_FTFE_FCCOB7_CCOBn(v) (HW_FTFE_FCCOB7_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FCCOB6 - Flash Common Command Object Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FCCOB6 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+typedef union _hw_ftfe_fccob6
+{
+ uint8_t U;
+ struct _hw_ftfe_fccob6_bitfields
+ {
+ uint8_t CCOBn : 8; //!< [7:0]
+ } B;
+} hw_ftfe_fccob6_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB6 register
+ */
+//@{
+#define HW_FTFE_FCCOB6_ADDR (REGS_FTFE_BASE + 0x9U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FCCOB6 (*(__IO hw_ftfe_fccob6_t *) HW_FTFE_FCCOB6_ADDR)
+#define HW_FTFE_FCCOB6_RD() (HW_FTFE_FCCOB6.U)
+#define HW_FTFE_FCCOB6_WR(v) (HW_FTFE_FCCOB6.U = (v))
+#define HW_FTFE_FCCOB6_SET(v) (HW_FTFE_FCCOB6_WR(HW_FTFE_FCCOB6_RD() | (v)))
+#define HW_FTFE_FCCOB6_CLR(v) (HW_FTFE_FCCOB6_WR(HW_FTFE_FCCOB6_RD() & ~(v)))
+#define HW_FTFE_FCCOB6_TOG(v) (HW_FTFE_FCCOB6_WR(HW_FTFE_FCCOB6_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FCCOB6 bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCCOB6, field CCOBn[7:0] (RW)
+ *
+ * The FCCOB register provides a command code and relevant parameters to the
+ * memory controller. The individual registers that compose the FCCOB data set can
+ * be written in any order, but you must provide all needed values, which vary
+ * from command to command. First, set up all required FCCOB fields and then
+ * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
+ * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
+ * by the user until the command completes (CCIF returns to 1). No command
+ * buffering or queueing is provided; the next command can be loaded only after the
+ * current command completes. Some commands return information to the FCCOB
+ * registers. Any values returned to FCCOB are available for reading after the
+ * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
+ * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
+ * the command code. This 8-bit value defines the command to be executed. The
+ * command code is followed by the parameters required for this specific FTFE command,
+ * typically an address and/or data values. The command parameter table is
+ * written in terms of FCCOB Number (which is equivalent to the byte number). This
+ * number is a reference to the FCCOB register name and is not the register address.
+ * FCCOB NumberRefers to FCCOB register name, not register address Typical
+ * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
+ * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
+ * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
+ * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
+ * register group uses a big endian addressing convention. For all command parameter
+ * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
+ * register number. The FCCOB register group may be read and written as
+ * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
+ */
+//@{
+#define BP_FTFE_FCCOB6_CCOBn (0U) //!< Bit position for FTFE_FCCOB6_CCOBn.
+#define BM_FTFE_FCCOB6_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB6_CCOBn.
+#define BS_FTFE_FCCOB6_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB6_CCOBn.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCCOB6_CCOBn field.
+#define BR_FTFE_FCCOB6_CCOBn (HW_FTFE_FCCOB6.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FCCOB6_CCOBn.
+#define BF_FTFE_FCCOB6_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB6_CCOBn), uint8_t) & BM_FTFE_FCCOB6_CCOBn)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCOBn field to a new value.
+#define BW_FTFE_FCCOB6_CCOBn(v) (HW_FTFE_FCCOB6_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FCCOB5 - Flash Common Command Object Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FCCOB5 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+typedef union _hw_ftfe_fccob5
+{
+ uint8_t U;
+ struct _hw_ftfe_fccob5_bitfields
+ {
+ uint8_t CCOBn : 8; //!< [7:0]
+ } B;
+} hw_ftfe_fccob5_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB5 register
+ */
+//@{
+#define HW_FTFE_FCCOB5_ADDR (REGS_FTFE_BASE + 0xAU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FCCOB5 (*(__IO hw_ftfe_fccob5_t *) HW_FTFE_FCCOB5_ADDR)
+#define HW_FTFE_FCCOB5_RD() (HW_FTFE_FCCOB5.U)
+#define HW_FTFE_FCCOB5_WR(v) (HW_FTFE_FCCOB5.U = (v))
+#define HW_FTFE_FCCOB5_SET(v) (HW_FTFE_FCCOB5_WR(HW_FTFE_FCCOB5_RD() | (v)))
+#define HW_FTFE_FCCOB5_CLR(v) (HW_FTFE_FCCOB5_WR(HW_FTFE_FCCOB5_RD() & ~(v)))
+#define HW_FTFE_FCCOB5_TOG(v) (HW_FTFE_FCCOB5_WR(HW_FTFE_FCCOB5_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FCCOB5 bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCCOB5, field CCOBn[7:0] (RW)
+ *
+ * The FCCOB register provides a command code and relevant parameters to the
+ * memory controller. The individual registers that compose the FCCOB data set can
+ * be written in any order, but you must provide all needed values, which vary
+ * from command to command. First, set up all required FCCOB fields and then
+ * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
+ * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
+ * by the user until the command completes (CCIF returns to 1). No command
+ * buffering or queueing is provided; the next command can be loaded only after the
+ * current command completes. Some commands return information to the FCCOB
+ * registers. Any values returned to FCCOB are available for reading after the
+ * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
+ * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
+ * the command code. This 8-bit value defines the command to be executed. The
+ * command code is followed by the parameters required for this specific FTFE command,
+ * typically an address and/or data values. The command parameter table is
+ * written in terms of FCCOB Number (which is equivalent to the byte number). This
+ * number is a reference to the FCCOB register name and is not the register address.
+ * FCCOB NumberRefers to FCCOB register name, not register address Typical
+ * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
+ * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
+ * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
+ * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
+ * register group uses a big endian addressing convention. For all command parameter
+ * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
+ * register number. The FCCOB register group may be read and written as
+ * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
+ */
+//@{
+#define BP_FTFE_FCCOB5_CCOBn (0U) //!< Bit position for FTFE_FCCOB5_CCOBn.
+#define BM_FTFE_FCCOB5_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB5_CCOBn.
+#define BS_FTFE_FCCOB5_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB5_CCOBn.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCCOB5_CCOBn field.
+#define BR_FTFE_FCCOB5_CCOBn (HW_FTFE_FCCOB5.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FCCOB5_CCOBn.
+#define BF_FTFE_FCCOB5_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB5_CCOBn), uint8_t) & BM_FTFE_FCCOB5_CCOBn)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCOBn field to a new value.
+#define BW_FTFE_FCCOB5_CCOBn(v) (HW_FTFE_FCCOB5_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FCCOB4 - Flash Common Command Object Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FCCOB4 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+typedef union _hw_ftfe_fccob4
+{
+ uint8_t U;
+ struct _hw_ftfe_fccob4_bitfields
+ {
+ uint8_t CCOBn : 8; //!< [7:0]
+ } B;
+} hw_ftfe_fccob4_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB4 register
+ */
+//@{
+#define HW_FTFE_FCCOB4_ADDR (REGS_FTFE_BASE + 0xBU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FCCOB4 (*(__IO hw_ftfe_fccob4_t *) HW_FTFE_FCCOB4_ADDR)
+#define HW_FTFE_FCCOB4_RD() (HW_FTFE_FCCOB4.U)
+#define HW_FTFE_FCCOB4_WR(v) (HW_FTFE_FCCOB4.U = (v))
+#define HW_FTFE_FCCOB4_SET(v) (HW_FTFE_FCCOB4_WR(HW_FTFE_FCCOB4_RD() | (v)))
+#define HW_FTFE_FCCOB4_CLR(v) (HW_FTFE_FCCOB4_WR(HW_FTFE_FCCOB4_RD() & ~(v)))
+#define HW_FTFE_FCCOB4_TOG(v) (HW_FTFE_FCCOB4_WR(HW_FTFE_FCCOB4_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FCCOB4 bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCCOB4, field CCOBn[7:0] (RW)
+ *
+ * The FCCOB register provides a command code and relevant parameters to the
+ * memory controller. The individual registers that compose the FCCOB data set can
+ * be written in any order, but you must provide all needed values, which vary
+ * from command to command. First, set up all required FCCOB fields and then
+ * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
+ * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
+ * by the user until the command completes (CCIF returns to 1). No command
+ * buffering or queueing is provided; the next command can be loaded only after the
+ * current command completes. Some commands return information to the FCCOB
+ * registers. Any values returned to FCCOB are available for reading after the
+ * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
+ * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
+ * the command code. This 8-bit value defines the command to be executed. The
+ * command code is followed by the parameters required for this specific FTFE command,
+ * typically an address and/or data values. The command parameter table is
+ * written in terms of FCCOB Number (which is equivalent to the byte number). This
+ * number is a reference to the FCCOB register name and is not the register address.
+ * FCCOB NumberRefers to FCCOB register name, not register address Typical
+ * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
+ * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
+ * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
+ * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
+ * register group uses a big endian addressing convention. For all command parameter
+ * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
+ * register number. The FCCOB register group may be read and written as
+ * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
+ */
+//@{
+#define BP_FTFE_FCCOB4_CCOBn (0U) //!< Bit position for FTFE_FCCOB4_CCOBn.
+#define BM_FTFE_FCCOB4_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB4_CCOBn.
+#define BS_FTFE_FCCOB4_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB4_CCOBn.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCCOB4_CCOBn field.
+#define BR_FTFE_FCCOB4_CCOBn (HW_FTFE_FCCOB4.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FCCOB4_CCOBn.
+#define BF_FTFE_FCCOB4_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB4_CCOBn), uint8_t) & BM_FTFE_FCCOB4_CCOBn)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCOBn field to a new value.
+#define BW_FTFE_FCCOB4_CCOBn(v) (HW_FTFE_FCCOB4_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FCCOBB - Flash Common Command Object Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FCCOBB - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+typedef union _hw_ftfe_fccobb
+{
+ uint8_t U;
+ struct _hw_ftfe_fccobb_bitfields
+ {
+ uint8_t CCOBn : 8; //!< [7:0]
+ } B;
+} hw_ftfe_fccobb_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FCCOBB register
+ */
+//@{
+#define HW_FTFE_FCCOBB_ADDR (REGS_FTFE_BASE + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FCCOBB (*(__IO hw_ftfe_fccobb_t *) HW_FTFE_FCCOBB_ADDR)
+#define HW_FTFE_FCCOBB_RD() (HW_FTFE_FCCOBB.U)
+#define HW_FTFE_FCCOBB_WR(v) (HW_FTFE_FCCOBB.U = (v))
+#define HW_FTFE_FCCOBB_SET(v) (HW_FTFE_FCCOBB_WR(HW_FTFE_FCCOBB_RD() | (v)))
+#define HW_FTFE_FCCOBB_CLR(v) (HW_FTFE_FCCOBB_WR(HW_FTFE_FCCOBB_RD() & ~(v)))
+#define HW_FTFE_FCCOBB_TOG(v) (HW_FTFE_FCCOBB_WR(HW_FTFE_FCCOBB_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FCCOBB bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCCOBB, field CCOBn[7:0] (RW)
+ *
+ * The FCCOB register provides a command code and relevant parameters to the
+ * memory controller. The individual registers that compose the FCCOB data set can
+ * be written in any order, but you must provide all needed values, which vary
+ * from command to command. First, set up all required FCCOB fields and then
+ * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
+ * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
+ * by the user until the command completes (CCIF returns to 1). No command
+ * buffering or queueing is provided; the next command can be loaded only after the
+ * current command completes. Some commands return information to the FCCOB
+ * registers. Any values returned to FCCOB are available for reading after the
+ * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
+ * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
+ * the command code. This 8-bit value defines the command to be executed. The
+ * command code is followed by the parameters required for this specific FTFE command,
+ * typically an address and/or data values. The command parameter table is
+ * written in terms of FCCOB Number (which is equivalent to the byte number). This
+ * number is a reference to the FCCOB register name and is not the register address.
+ * FCCOB NumberRefers to FCCOB register name, not register address Typical
+ * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
+ * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
+ * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
+ * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
+ * register group uses a big endian addressing convention. For all command parameter
+ * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
+ * register number. The FCCOB register group may be read and written as
+ * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
+ */
+//@{
+#define BP_FTFE_FCCOBB_CCOBn (0U) //!< Bit position for FTFE_FCCOBB_CCOBn.
+#define BM_FTFE_FCCOBB_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOBB_CCOBn.
+#define BS_FTFE_FCCOBB_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOBB_CCOBn.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCCOBB_CCOBn field.
+#define BR_FTFE_FCCOBB_CCOBn (HW_FTFE_FCCOBB.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FCCOBB_CCOBn.
+#define BF_FTFE_FCCOBB_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOBB_CCOBn), uint8_t) & BM_FTFE_FCCOBB_CCOBn)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCOBn field to a new value.
+#define BW_FTFE_FCCOBB_CCOBn(v) (HW_FTFE_FCCOBB_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FCCOBA - Flash Common Command Object Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FCCOBA - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+typedef union _hw_ftfe_fccoba
+{
+ uint8_t U;
+ struct _hw_ftfe_fccoba_bitfields
+ {
+ uint8_t CCOBn : 8; //!< [7:0]
+ } B;
+} hw_ftfe_fccoba_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FCCOBA register
+ */
+//@{
+#define HW_FTFE_FCCOBA_ADDR (REGS_FTFE_BASE + 0xDU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FCCOBA (*(__IO hw_ftfe_fccoba_t *) HW_FTFE_FCCOBA_ADDR)
+#define HW_FTFE_FCCOBA_RD() (HW_FTFE_FCCOBA.U)
+#define HW_FTFE_FCCOBA_WR(v) (HW_FTFE_FCCOBA.U = (v))
+#define HW_FTFE_FCCOBA_SET(v) (HW_FTFE_FCCOBA_WR(HW_FTFE_FCCOBA_RD() | (v)))
+#define HW_FTFE_FCCOBA_CLR(v) (HW_FTFE_FCCOBA_WR(HW_FTFE_FCCOBA_RD() & ~(v)))
+#define HW_FTFE_FCCOBA_TOG(v) (HW_FTFE_FCCOBA_WR(HW_FTFE_FCCOBA_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FCCOBA bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCCOBA, field CCOBn[7:0] (RW)
+ *
+ * The FCCOB register provides a command code and relevant parameters to the
+ * memory controller. The individual registers that compose the FCCOB data set can
+ * be written in any order, but you must provide all needed values, which vary
+ * from command to command. First, set up all required FCCOB fields and then
+ * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
+ * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
+ * by the user until the command completes (CCIF returns to 1). No command
+ * buffering or queueing is provided; the next command can be loaded only after the
+ * current command completes. Some commands return information to the FCCOB
+ * registers. Any values returned to FCCOB are available for reading after the
+ * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
+ * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
+ * the command code. This 8-bit value defines the command to be executed. The
+ * command code is followed by the parameters required for this specific FTFE command,
+ * typically an address and/or data values. The command parameter table is
+ * written in terms of FCCOB Number (which is equivalent to the byte number). This
+ * number is a reference to the FCCOB register name and is not the register address.
+ * FCCOB NumberRefers to FCCOB register name, not register address Typical
+ * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
+ * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
+ * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
+ * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
+ * register group uses a big endian addressing convention. For all command parameter
+ * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
+ * register number. The FCCOB register group may be read and written as
+ * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
+ */
+//@{
+#define BP_FTFE_FCCOBA_CCOBn (0U) //!< Bit position for FTFE_FCCOBA_CCOBn.
+#define BM_FTFE_FCCOBA_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOBA_CCOBn.
+#define BS_FTFE_FCCOBA_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOBA_CCOBn.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCCOBA_CCOBn field.
+#define BR_FTFE_FCCOBA_CCOBn (HW_FTFE_FCCOBA.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FCCOBA_CCOBn.
+#define BF_FTFE_FCCOBA_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOBA_CCOBn), uint8_t) & BM_FTFE_FCCOBA_CCOBn)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCOBn field to a new value.
+#define BW_FTFE_FCCOBA_CCOBn(v) (HW_FTFE_FCCOBA_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FCCOB9 - Flash Common Command Object Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FCCOB9 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+typedef union _hw_ftfe_fccob9
+{
+ uint8_t U;
+ struct _hw_ftfe_fccob9_bitfields
+ {
+ uint8_t CCOBn : 8; //!< [7:0]
+ } B;
+} hw_ftfe_fccob9_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB9 register
+ */
+//@{
+#define HW_FTFE_FCCOB9_ADDR (REGS_FTFE_BASE + 0xEU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FCCOB9 (*(__IO hw_ftfe_fccob9_t *) HW_FTFE_FCCOB9_ADDR)
+#define HW_FTFE_FCCOB9_RD() (HW_FTFE_FCCOB9.U)
+#define HW_FTFE_FCCOB9_WR(v) (HW_FTFE_FCCOB9.U = (v))
+#define HW_FTFE_FCCOB9_SET(v) (HW_FTFE_FCCOB9_WR(HW_FTFE_FCCOB9_RD() | (v)))
+#define HW_FTFE_FCCOB9_CLR(v) (HW_FTFE_FCCOB9_WR(HW_FTFE_FCCOB9_RD() & ~(v)))
+#define HW_FTFE_FCCOB9_TOG(v) (HW_FTFE_FCCOB9_WR(HW_FTFE_FCCOB9_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FCCOB9 bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCCOB9, field CCOBn[7:0] (RW)
+ *
+ * The FCCOB register provides a command code and relevant parameters to the
+ * memory controller. The individual registers that compose the FCCOB data set can
+ * be written in any order, but you must provide all needed values, which vary
+ * from command to command. First, set up all required FCCOB fields and then
+ * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
+ * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
+ * by the user until the command completes (CCIF returns to 1). No command
+ * buffering or queueing is provided; the next command can be loaded only after the
+ * current command completes. Some commands return information to the FCCOB
+ * registers. Any values returned to FCCOB are available for reading after the
+ * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
+ * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
+ * the command code. This 8-bit value defines the command to be executed. The
+ * command code is followed by the parameters required for this specific FTFE command,
+ * typically an address and/or data values. The command parameter table is
+ * written in terms of FCCOB Number (which is equivalent to the byte number). This
+ * number is a reference to the FCCOB register name and is not the register address.
+ * FCCOB NumberRefers to FCCOB register name, not register address Typical
+ * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
+ * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
+ * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
+ * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
+ * register group uses a big endian addressing convention. For all command parameter
+ * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
+ * register number. The FCCOB register group may be read and written as
+ * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
+ */
+//@{
+#define BP_FTFE_FCCOB9_CCOBn (0U) //!< Bit position for FTFE_FCCOB9_CCOBn.
+#define BM_FTFE_FCCOB9_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB9_CCOBn.
+#define BS_FTFE_FCCOB9_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB9_CCOBn.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCCOB9_CCOBn field.
+#define BR_FTFE_FCCOB9_CCOBn (HW_FTFE_FCCOB9.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FCCOB9_CCOBn.
+#define BF_FTFE_FCCOB9_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB9_CCOBn), uint8_t) & BM_FTFE_FCCOB9_CCOBn)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCOBn field to a new value.
+#define BW_FTFE_FCCOB9_CCOBn(v) (HW_FTFE_FCCOB9_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FCCOB8 - Flash Common Command Object Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FCCOB8 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+typedef union _hw_ftfe_fccob8
+{
+ uint8_t U;
+ struct _hw_ftfe_fccob8_bitfields
+ {
+ uint8_t CCOBn : 8; //!< [7:0]
+ } B;
+} hw_ftfe_fccob8_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB8 register
+ */
+//@{
+#define HW_FTFE_FCCOB8_ADDR (REGS_FTFE_BASE + 0xFU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FCCOB8 (*(__IO hw_ftfe_fccob8_t *) HW_FTFE_FCCOB8_ADDR)
+#define HW_FTFE_FCCOB8_RD() (HW_FTFE_FCCOB8.U)
+#define HW_FTFE_FCCOB8_WR(v) (HW_FTFE_FCCOB8.U = (v))
+#define HW_FTFE_FCCOB8_SET(v) (HW_FTFE_FCCOB8_WR(HW_FTFE_FCCOB8_RD() | (v)))
+#define HW_FTFE_FCCOB8_CLR(v) (HW_FTFE_FCCOB8_WR(HW_FTFE_FCCOB8_RD() & ~(v)))
+#define HW_FTFE_FCCOB8_TOG(v) (HW_FTFE_FCCOB8_WR(HW_FTFE_FCCOB8_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FCCOB8 bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCCOB8, field CCOBn[7:0] (RW)
+ *
+ * The FCCOB register provides a command code and relevant parameters to the
+ * memory controller. The individual registers that compose the FCCOB data set can
+ * be written in any order, but you must provide all needed values, which vary
+ * from command to command. First, set up all required FCCOB fields and then
+ * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
+ * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
+ * by the user until the command completes (CCIF returns to 1). No command
+ * buffering or queueing is provided; the next command can be loaded only after the
+ * current command completes. Some commands return information to the FCCOB
+ * registers. Any values returned to FCCOB are available for reading after the
+ * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
+ * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
+ * the command code. This 8-bit value defines the command to be executed. The
+ * command code is followed by the parameters required for this specific FTFE command,
+ * typically an address and/or data values. The command parameter table is
+ * written in terms of FCCOB Number (which is equivalent to the byte number). This
+ * number is a reference to the FCCOB register name and is not the register address.
+ * FCCOB NumberRefers to FCCOB register name, not register address Typical
+ * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
+ * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
+ * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
+ * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
+ * register group uses a big endian addressing convention. For all command parameter
+ * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
+ * register number. The FCCOB register group may be read and written as
+ * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
+ */
+//@{
+#define BP_FTFE_FCCOB8_CCOBn (0U) //!< Bit position for FTFE_FCCOB8_CCOBn.
+#define BM_FTFE_FCCOB8_CCOBn (0xFFU) //!< Bit mask for FTFE_FCCOB8_CCOBn.
+#define BS_FTFE_FCCOB8_CCOBn (8U) //!< Bit field size in bits for FTFE_FCCOB8_CCOBn.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FCCOB8_CCOBn field.
+#define BR_FTFE_FCCOB8_CCOBn (HW_FTFE_FCCOB8.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FCCOB8_CCOBn.
+#define BF_FTFE_FCCOB8_CCOBn(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FCCOB8_CCOBn), uint8_t) & BM_FTFE_FCCOB8_CCOBn)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCOBn field to a new value.
+#define BW_FTFE_FCCOB8_CCOBn(v) (HW_FTFE_FCCOB8_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FPROT3 - Program Flash Protection Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FPROT3 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+typedef union _hw_ftfe_fprot3
+{
+ uint8_t U;
+ struct _hw_ftfe_fprot3_bitfields
+ {
+ uint8_t PROT : 8; //!< [7:0] Program Flash Region Protect
+ } B;
+} hw_ftfe_fprot3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FPROT3 register
+ */
+//@{
+#define HW_FTFE_FPROT3_ADDR (REGS_FTFE_BASE + 0x10U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FPROT3 (*(__IO hw_ftfe_fprot3_t *) HW_FTFE_FPROT3_ADDR)
+#define HW_FTFE_FPROT3_RD() (HW_FTFE_FPROT3.U)
+#define HW_FTFE_FPROT3_WR(v) (HW_FTFE_FPROT3.U = (v))
+#define HW_FTFE_FPROT3_SET(v) (HW_FTFE_FPROT3_WR(HW_FTFE_FPROT3_RD() | (v)))
+#define HW_FTFE_FPROT3_CLR(v) (HW_FTFE_FPROT3_WR(HW_FTFE_FPROT3_RD() & ~(v)))
+#define HW_FTFE_FPROT3_TOG(v) (HW_FTFE_FPROT3_WR(HW_FTFE_FPROT3_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FPROT3 bitfields
+ */
+
+/*!
+ * @name Register FTFE_FPROT3, field PROT[7:0] (RW)
+ *
+ * Each program flash region can be protected from program and erase operations
+ * by setting the associated PROT bit. In NVM Normal mode: The protection can
+ * only be increased, meaning that currently unprotected memory can be protected,
+ * but currently protected memory cannot be unprotected. Since unprotected regions
+ * are marked with a 1 and protected regions use a 0, only writes changing 1s to
+ * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
+ * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
+ * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
+ * writable without restriction. Unprotected areas can be protected and protected
+ * areas can be unprotected. The user must never write to any FPROT register while
+ * a command is running (CCIF=0). Trying to alter data in any protected area in
+ * the program flash memory results in a protection violation error and sets the
+ * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
+ * if it contains any protected region.
+ *
+ * Values:
+ * - 0 - Program flash region is protected.
+ * - 1 - Program flash region is not protected
+ */
+//@{
+#define BP_FTFE_FPROT3_PROT (0U) //!< Bit position for FTFE_FPROT3_PROT.
+#define BM_FTFE_FPROT3_PROT (0xFFU) //!< Bit mask for FTFE_FPROT3_PROT.
+#define BS_FTFE_FPROT3_PROT (8U) //!< Bit field size in bits for FTFE_FPROT3_PROT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FPROT3_PROT field.
+#define BR_FTFE_FPROT3_PROT (HW_FTFE_FPROT3.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FPROT3_PROT.
+#define BF_FTFE_FPROT3_PROT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FPROT3_PROT), uint8_t) & BM_FTFE_FPROT3_PROT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PROT field to a new value.
+#define BW_FTFE_FPROT3_PROT(v) (HW_FTFE_FPROT3_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FPROT2 - Program Flash Protection Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FPROT2 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+typedef union _hw_ftfe_fprot2
+{
+ uint8_t U;
+ struct _hw_ftfe_fprot2_bitfields
+ {
+ uint8_t PROT : 8; //!< [7:0] Program Flash Region Protect
+ } B;
+} hw_ftfe_fprot2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FPROT2 register
+ */
+//@{
+#define HW_FTFE_FPROT2_ADDR (REGS_FTFE_BASE + 0x11U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FPROT2 (*(__IO hw_ftfe_fprot2_t *) HW_FTFE_FPROT2_ADDR)
+#define HW_FTFE_FPROT2_RD() (HW_FTFE_FPROT2.U)
+#define HW_FTFE_FPROT2_WR(v) (HW_FTFE_FPROT2.U = (v))
+#define HW_FTFE_FPROT2_SET(v) (HW_FTFE_FPROT2_WR(HW_FTFE_FPROT2_RD() | (v)))
+#define HW_FTFE_FPROT2_CLR(v) (HW_FTFE_FPROT2_WR(HW_FTFE_FPROT2_RD() & ~(v)))
+#define HW_FTFE_FPROT2_TOG(v) (HW_FTFE_FPROT2_WR(HW_FTFE_FPROT2_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FPROT2 bitfields
+ */
+
+/*!
+ * @name Register FTFE_FPROT2, field PROT[7:0] (RW)
+ *
+ * Each program flash region can be protected from program and erase operations
+ * by setting the associated PROT bit. In NVM Normal mode: The protection can
+ * only be increased, meaning that currently unprotected memory can be protected,
+ * but currently protected memory cannot be unprotected. Since unprotected regions
+ * are marked with a 1 and protected regions use a 0, only writes changing 1s to
+ * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
+ * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
+ * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
+ * writable without restriction. Unprotected areas can be protected and protected
+ * areas can be unprotected. The user must never write to any FPROT register while
+ * a command is running (CCIF=0). Trying to alter data in any protected area in
+ * the program flash memory results in a protection violation error and sets the
+ * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
+ * if it contains any protected region.
+ *
+ * Values:
+ * - 0 - Program flash region is protected.
+ * - 1 - Program flash region is not protected
+ */
+//@{
+#define BP_FTFE_FPROT2_PROT (0U) //!< Bit position for FTFE_FPROT2_PROT.
+#define BM_FTFE_FPROT2_PROT (0xFFU) //!< Bit mask for FTFE_FPROT2_PROT.
+#define BS_FTFE_FPROT2_PROT (8U) //!< Bit field size in bits for FTFE_FPROT2_PROT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FPROT2_PROT field.
+#define BR_FTFE_FPROT2_PROT (HW_FTFE_FPROT2.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FPROT2_PROT.
+#define BF_FTFE_FPROT2_PROT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FPROT2_PROT), uint8_t) & BM_FTFE_FPROT2_PROT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PROT field to a new value.
+#define BW_FTFE_FPROT2_PROT(v) (HW_FTFE_FPROT2_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FPROT1 - Program Flash Protection Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FPROT1 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+typedef union _hw_ftfe_fprot1
+{
+ uint8_t U;
+ struct _hw_ftfe_fprot1_bitfields
+ {
+ uint8_t PROT : 8; //!< [7:0] Program Flash Region Protect
+ } B;
+} hw_ftfe_fprot1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FPROT1 register
+ */
+//@{
+#define HW_FTFE_FPROT1_ADDR (REGS_FTFE_BASE + 0x12U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FPROT1 (*(__IO hw_ftfe_fprot1_t *) HW_FTFE_FPROT1_ADDR)
+#define HW_FTFE_FPROT1_RD() (HW_FTFE_FPROT1.U)
+#define HW_FTFE_FPROT1_WR(v) (HW_FTFE_FPROT1.U = (v))
+#define HW_FTFE_FPROT1_SET(v) (HW_FTFE_FPROT1_WR(HW_FTFE_FPROT1_RD() | (v)))
+#define HW_FTFE_FPROT1_CLR(v) (HW_FTFE_FPROT1_WR(HW_FTFE_FPROT1_RD() & ~(v)))
+#define HW_FTFE_FPROT1_TOG(v) (HW_FTFE_FPROT1_WR(HW_FTFE_FPROT1_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FPROT1 bitfields
+ */
+
+/*!
+ * @name Register FTFE_FPROT1, field PROT[7:0] (RW)
+ *
+ * Each program flash region can be protected from program and erase operations
+ * by setting the associated PROT bit. In NVM Normal mode: The protection can
+ * only be increased, meaning that currently unprotected memory can be protected,
+ * but currently protected memory cannot be unprotected. Since unprotected regions
+ * are marked with a 1 and protected regions use a 0, only writes changing 1s to
+ * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
+ * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
+ * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
+ * writable without restriction. Unprotected areas can be protected and protected
+ * areas can be unprotected. The user must never write to any FPROT register while
+ * a command is running (CCIF=0). Trying to alter data in any protected area in
+ * the program flash memory results in a protection violation error and sets the
+ * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
+ * if it contains any protected region.
+ *
+ * Values:
+ * - 0 - Program flash region is protected.
+ * - 1 - Program flash region is not protected
+ */
+//@{
+#define BP_FTFE_FPROT1_PROT (0U) //!< Bit position for FTFE_FPROT1_PROT.
+#define BM_FTFE_FPROT1_PROT (0xFFU) //!< Bit mask for FTFE_FPROT1_PROT.
+#define BS_FTFE_FPROT1_PROT (8U) //!< Bit field size in bits for FTFE_FPROT1_PROT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FPROT1_PROT field.
+#define BR_FTFE_FPROT1_PROT (HW_FTFE_FPROT1.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FPROT1_PROT.
+#define BF_FTFE_FPROT1_PROT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FPROT1_PROT), uint8_t) & BM_FTFE_FPROT1_PROT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PROT field to a new value.
+#define BW_FTFE_FPROT1_PROT(v) (HW_FTFE_FPROT1_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FPROT0 - Program Flash Protection Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FPROT0 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+typedef union _hw_ftfe_fprot0
+{
+ uint8_t U;
+ struct _hw_ftfe_fprot0_bitfields
+ {
+ uint8_t PROT : 8; //!< [7:0] Program Flash Region Protect
+ } B;
+} hw_ftfe_fprot0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FPROT0 register
+ */
+//@{
+#define HW_FTFE_FPROT0_ADDR (REGS_FTFE_BASE + 0x13U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FPROT0 (*(__IO hw_ftfe_fprot0_t *) HW_FTFE_FPROT0_ADDR)
+#define HW_FTFE_FPROT0_RD() (HW_FTFE_FPROT0.U)
+#define HW_FTFE_FPROT0_WR(v) (HW_FTFE_FPROT0.U = (v))
+#define HW_FTFE_FPROT0_SET(v) (HW_FTFE_FPROT0_WR(HW_FTFE_FPROT0_RD() | (v)))
+#define HW_FTFE_FPROT0_CLR(v) (HW_FTFE_FPROT0_WR(HW_FTFE_FPROT0_RD() & ~(v)))
+#define HW_FTFE_FPROT0_TOG(v) (HW_FTFE_FPROT0_WR(HW_FTFE_FPROT0_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FPROT0 bitfields
+ */
+
+/*!
+ * @name Register FTFE_FPROT0, field PROT[7:0] (RW)
+ *
+ * Each program flash region can be protected from program and erase operations
+ * by setting the associated PROT bit. In NVM Normal mode: The protection can
+ * only be increased, meaning that currently unprotected memory can be protected,
+ * but currently protected memory cannot be unprotected. Since unprotected regions
+ * are marked with a 1 and protected regions use a 0, only writes changing 1s to
+ * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
+ * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
+ * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
+ * writable without restriction. Unprotected areas can be protected and protected
+ * areas can be unprotected. The user must never write to any FPROT register while
+ * a command is running (CCIF=0). Trying to alter data in any protected area in
+ * the program flash memory results in a protection violation error and sets the
+ * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
+ * if it contains any protected region.
+ *
+ * Values:
+ * - 0 - Program flash region is protected.
+ * - 1 - Program flash region is not protected
+ */
+//@{
+#define BP_FTFE_FPROT0_PROT (0U) //!< Bit position for FTFE_FPROT0_PROT.
+#define BM_FTFE_FPROT0_PROT (0xFFU) //!< Bit mask for FTFE_FPROT0_PROT.
+#define BS_FTFE_FPROT0_PROT (8U) //!< Bit field size in bits for FTFE_FPROT0_PROT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FPROT0_PROT field.
+#define BR_FTFE_FPROT0_PROT (HW_FTFE_FPROT0.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FPROT0_PROT.
+#define BF_FTFE_FPROT0_PROT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FPROT0_PROT), uint8_t) & BM_FTFE_FPROT0_PROT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PROT field to a new value.
+#define BW_FTFE_FPROT0_PROT(v) (HW_FTFE_FPROT0_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FEPROT - EEPROM Protection Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FEPROT - EEPROM Protection Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * For devices with FlexNVM: The FEPROT register defines which EEPROM regions of
+ * the FlexRAM are protected against program and erase operations. Protected
+ * EEPROM regions cannot have their content changed by writing to it. Unprotected
+ * regions can be changed by writing to the FlexRAM. For devices with program flash
+ * only: This register is reserved and not used.
+ */
+typedef union _hw_ftfe_feprot
+{
+ uint8_t U;
+ struct _hw_ftfe_feprot_bitfields
+ {
+ uint8_t EPROT : 8; //!< [7:0] EEPROM Region Protect
+ } B;
+} hw_ftfe_feprot_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FEPROT register
+ */
+//@{
+#define HW_FTFE_FEPROT_ADDR (REGS_FTFE_BASE + 0x16U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FEPROT (*(__IO hw_ftfe_feprot_t *) HW_FTFE_FEPROT_ADDR)
+#define HW_FTFE_FEPROT_RD() (HW_FTFE_FEPROT.U)
+#define HW_FTFE_FEPROT_WR(v) (HW_FTFE_FEPROT.U = (v))
+#define HW_FTFE_FEPROT_SET(v) (HW_FTFE_FEPROT_WR(HW_FTFE_FEPROT_RD() | (v)))
+#define HW_FTFE_FEPROT_CLR(v) (HW_FTFE_FEPROT_WR(HW_FTFE_FEPROT_RD() & ~(v)))
+#define HW_FTFE_FEPROT_TOG(v) (HW_FTFE_FEPROT_WR(HW_FTFE_FEPROT_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FEPROT bitfields
+ */
+
+/*!
+ * @name Register FTFE_FEPROT, field EPROT[7:0] (RW)
+ *
+ * For devices with program flash only: Reserved For devices with FlexNVM:
+ * Individual EEPROM regions can be protected from alteration by setting the
+ * associated EPROT bit. The EPROT bits are not used when the FlexNVM Partition Code is
+ * set to data flash only. When the FlexNVM Partition Code is set to data flash and
+ * EEPROM or EEPROM only, each EPROT bit covers one-eighth of the configured
+ * EEPROM data (see the EEPROM Data Set Size parameter description). In NVM Normal
+ * mode: The protection can only be increased. This means that
+ * currently-unprotected memory can be protected, but currently-protected memory cannot be
+ * unprotected. Since unprotected regions are marked with a 1 and protected regions use a
+ * 0, only writes changing 1s to 0s are accepted. This 1-to-0 transition check is
+ * performed on a bit-by-bit basis. Those FEPROT bits with 1-to-0 transitions
+ * are accepted while all bits with 0-to-1 transitions are ignored. In NVM Special
+ * mode: All bits of the FEPROT register are writable without restriction.
+ * Unprotected areas can be protected and protected areas can be unprotected. Never
+ * write to the FEPROT register while a command is running (CCIF=0). Reset: During
+ * the reset sequence, the FEPROT register is loaded with the contents of the
+ * FlexRAM protection byte in the Flash Configuration Field located in program flash.
+ * The flash basis for the reset values is signified by X in the register
+ * diagram. To change the EEPROM protection that will be loaded during the reset
+ * sequence, the sector of program flash that contains the Flash Configuration Field
+ * must be unprotected; then the EEPROM protection byte must be erased and
+ * reprogrammed. Trying to alter data by writing to any protected area in the EEPROM
+ * results in a protection violation error and sets the FSTAT[FPVIOL] bit.
+ *
+ * Values:
+ * - 0 - For devices with program flash only: Reserved For devices with FlexNVM:
+ * EEPROM region is protected
+ * - 1 - For devices with program flash only: Reserved For devices with FlexNVM:
+ * EEPROM region is not protected
+ */
+//@{
+#define BP_FTFE_FEPROT_EPROT (0U) //!< Bit position for FTFE_FEPROT_EPROT.
+#define BM_FTFE_FEPROT_EPROT (0xFFU) //!< Bit mask for FTFE_FEPROT_EPROT.
+#define BS_FTFE_FEPROT_EPROT (8U) //!< Bit field size in bits for FTFE_FEPROT_EPROT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FEPROT_EPROT field.
+#define BR_FTFE_FEPROT_EPROT (HW_FTFE_FEPROT.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FEPROT_EPROT.
+#define BF_FTFE_FEPROT_EPROT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FEPROT_EPROT), uint8_t) & BM_FTFE_FEPROT_EPROT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EPROT field to a new value.
+#define BW_FTFE_FEPROT_EPROT(v) (HW_FTFE_FEPROT_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTFE_FDPROT - Data Flash Protection Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTFE_FDPROT - Data Flash Protection Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FDPROT register defines which data flash regions are protected against
+ * program and erase operations. Protected Flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by both program and erase
+ * operations.
+ */
+typedef union _hw_ftfe_fdprot
+{
+ uint8_t U;
+ struct _hw_ftfe_fdprot_bitfields
+ {
+ uint8_t DPROT : 8; //!< [7:0] Data Flash Region Protect
+ } B;
+} hw_ftfe_fdprot_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTFE_FDPROT register
+ */
+//@{
+#define HW_FTFE_FDPROT_ADDR (REGS_FTFE_BASE + 0x17U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTFE_FDPROT (*(__IO hw_ftfe_fdprot_t *) HW_FTFE_FDPROT_ADDR)
+#define HW_FTFE_FDPROT_RD() (HW_FTFE_FDPROT.U)
+#define HW_FTFE_FDPROT_WR(v) (HW_FTFE_FDPROT.U = (v))
+#define HW_FTFE_FDPROT_SET(v) (HW_FTFE_FDPROT_WR(HW_FTFE_FDPROT_RD() | (v)))
+#define HW_FTFE_FDPROT_CLR(v) (HW_FTFE_FDPROT_WR(HW_FTFE_FDPROT_RD() & ~(v)))
+#define HW_FTFE_FDPROT_TOG(v) (HW_FTFE_FDPROT_WR(HW_FTFE_FDPROT_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTFE_FDPROT bitfields
+ */
+
+/*!
+ * @name Register FTFE_FDPROT, field DPROT[7:0] (RW)
+ *
+ * Individual data flash regions can be protected from program and erase
+ * operations by setting the associated DPROT bit. Each DPROT bit protects one-eighth of
+ * the partitioned data flash memory space. The granularity of data flash
+ * protection cannot be less than the data flash sector size. If an unused DPROT bit is
+ * set, the Erase all Blocks command does not execute and sets the FSTAT[FPVIOL]
+ * bit. In NVM Normal mode: The protection can only be increased, meaning that
+ * currently unprotected memory can be protected but currently protected memory
+ * cannot be unprotected. Since unprotected regions are marked with a 1 and
+ * protected regions use a 0, only writes changing 1s to 0s are accepted. This 1-to-0
+ * transition check is performed on a bit-by-bit basis. Those FDPROT bits with
+ * 1-to-0 transitions are accepted while all bits with 0-to-1 transitions are
+ * ignored. In NVM Special mode: All bits of the FDPROT register are writable without
+ * restriction. Unprotected areas can be protected and protected areas can be
+ * unprotected. The user must never write to the FDPROT register while a command is
+ * running (CCIF=0). Reset: During the reset sequence, the FDPROT register is
+ * loaded with the contents of the data flash protection byte in the Flash
+ * Configuration Field located in program flash memory. The flash basis for the reset values
+ * is signified by X in the register diagram. To change the data flash
+ * protection that will be loaded during the reset sequence, unprotect the sector of
+ * program flash that contains the Flash Configuration Field. Then, erase and
+ * reprogram the data flash protection byte. Trying to alter data with the program and
+ * erase commands in any protected area in the data flash memory results in a
+ * protection violation error and sets the FSTAT[FPVIOL] bit. A block erase of any
+ * data flash memory block (see the Erase Flash Block command description) is not
+ * possible if the data flash block contains any protected region or if the FlexNVM
+ * memory has been partitioned for EEPROM.
+ *
+ * Values:
+ * - 0 - Data Flash region is protected
+ * - 1 - Data Flash region is not protected
+ */
+//@{
+#define BP_FTFE_FDPROT_DPROT (0U) //!< Bit position for FTFE_FDPROT_DPROT.
+#define BM_FTFE_FDPROT_DPROT (0xFFU) //!< Bit mask for FTFE_FDPROT_DPROT.
+#define BS_FTFE_FDPROT_DPROT (8U) //!< Bit field size in bits for FTFE_FDPROT_DPROT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTFE_FDPROT_DPROT field.
+#define BR_FTFE_FDPROT_DPROT (HW_FTFE_FDPROT.U)
+#endif
+
+//! @brief Format value for bitfield FTFE_FDPROT_DPROT.
+#define BF_FTFE_FDPROT_DPROT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_FTFE_FDPROT_DPROT), uint8_t) & BM_FTFE_FDPROT_DPROT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DPROT field to a new value.
+#define BW_FTFE_FDPROT_DPROT(v) (HW_FTFE_FDPROT_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_ftfe_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All FTFE module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_ftfe
+{
+ __IO hw_ftfe_fstat_t FSTAT; //!< [0x0] Flash Status Register
+ __IO hw_ftfe_fcnfg_t FCNFG; //!< [0x1] Flash Configuration Register
+ __I hw_ftfe_fsec_t FSEC; //!< [0x2] Flash Security Register
+ __I hw_ftfe_fopt_t FOPT; //!< [0x3] Flash Option Register
+ __IO hw_ftfe_fccob3_t FCCOB3; //!< [0x4] Flash Common Command Object Registers
+ __IO hw_ftfe_fccob2_t FCCOB2; //!< [0x5] Flash Common Command Object Registers
+ __IO hw_ftfe_fccob1_t FCCOB1; //!< [0x6] Flash Common Command Object Registers
+ __IO hw_ftfe_fccob0_t FCCOB0; //!< [0x7] Flash Common Command Object Registers
+ __IO hw_ftfe_fccob7_t FCCOB7; //!< [0x8] Flash Common Command Object Registers
+ __IO hw_ftfe_fccob6_t FCCOB6; //!< [0x9] Flash Common Command Object Registers
+ __IO hw_ftfe_fccob5_t FCCOB5; //!< [0xA] Flash Common Command Object Registers
+ __IO hw_ftfe_fccob4_t FCCOB4; //!< [0xB] Flash Common Command Object Registers
+ __IO hw_ftfe_fccobb_t FCCOBB; //!< [0xC] Flash Common Command Object Registers
+ __IO hw_ftfe_fccoba_t FCCOBA; //!< [0xD] Flash Common Command Object Registers
+ __IO hw_ftfe_fccob9_t FCCOB9; //!< [0xE] Flash Common Command Object Registers
+ __IO hw_ftfe_fccob8_t FCCOB8; //!< [0xF] Flash Common Command Object Registers
+ __IO hw_ftfe_fprot3_t FPROT3; //!< [0x10] Program Flash Protection Registers
+ __IO hw_ftfe_fprot2_t FPROT2; //!< [0x11] Program Flash Protection Registers
+ __IO hw_ftfe_fprot1_t FPROT1; //!< [0x12] Program Flash Protection Registers
+ __IO hw_ftfe_fprot0_t FPROT0; //!< [0x13] Program Flash Protection Registers
+ uint8_t _reserved0[2];
+ __IO hw_ftfe_feprot_t FEPROT; //!< [0x16] EEPROM Protection Register
+ __IO hw_ftfe_fdprot_t FDPROT; //!< [0x17] Data Flash Protection Register
+} hw_ftfe_t;
+#pragma pack()
+
+//! @brief Macro to access all FTFE registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_FTFE</code>.
+#define HW_FTFE (*(hw_ftfe_t *) REGS_FTFE_BASE)
+#endif
+
+#endif // __HW_FTFE_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_ftm.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,6616 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_FTM_REGISTERS_H__
+#define __HW_FTM_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 FTM
+ *
+ * FlexTimer Module
+ *
+ * Registers defined in this header file:
+ * - HW_FTM_SC - Status And Control
+ * - HW_FTM_CNT - Counter
+ * - HW_FTM_MOD - Modulo
+ * - HW_FTM_CnSC - Channel (n) Status And Control
+ * - HW_FTM_CnV - Channel (n) Value
+ * - HW_FTM_CNTIN - Counter Initial Value
+ * - HW_FTM_STATUS - Capture And Compare Status
+ * - HW_FTM_MODE - Features Mode Selection
+ * - HW_FTM_SYNC - Synchronization
+ * - HW_FTM_OUTINIT - Initial State For Channels Output
+ * - HW_FTM_OUTMASK - Output Mask
+ * - HW_FTM_COMBINE - Function For Linked Channels
+ * - HW_FTM_DEADTIME - Deadtime Insertion Control
+ * - HW_FTM_EXTTRIG - FTM External Trigger
+ * - HW_FTM_POL - Channels Polarity
+ * - HW_FTM_FMS - Fault Mode Status
+ * - HW_FTM_FILTER - Input Capture Filter Control
+ * - HW_FTM_FLTCTRL - Fault Control
+ * - HW_FTM_QDCTRL - Quadrature Decoder Control And Status
+ * - HW_FTM_CONF - Configuration
+ * - HW_FTM_FLTPOL - FTM Fault Input Polarity
+ * - HW_FTM_SYNCONF - Synchronization Configuration
+ * - HW_FTM_INVCTRL - FTM Inverting Control
+ * - HW_FTM_SWOCTRL - FTM Software Output Control
+ * - HW_FTM_PWMLOAD - FTM PWM Load
+ *
+ * - hw_ftm_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_FTM_BASE
+#define HW_FTM_INSTANCE_COUNT (4U) //!< Number of instances of the FTM module.
+#define HW_FTM0 (0U) //!< Instance number for FTM0.
+#define HW_FTM1 (1U) //!< Instance number for FTM1.
+#define HW_FTM2 (2U) //!< Instance number for FTM2.
+#define HW_FTM3 (3U) //!< Instance number for FTM3.
+#define REGS_FTM0_BASE (0x40038000U) //!< Base address for FTM0.
+#define REGS_FTM1_BASE (0x40039000U) //!< Base address for FTM1.
+#define REGS_FTM2_BASE (0x4003A000U) //!< Base address for FTM2.
+#define REGS_FTM3_BASE (0x400B9000U) //!< Base address for FTM3.
+
+//! @brief Table of base addresses for FTM instances.
+static const uint32_t __g_regs_FTM_base_addresses[] = {
+ REGS_FTM0_BASE,
+ REGS_FTM1_BASE,
+ REGS_FTM2_BASE,
+ REGS_FTM3_BASE,
+ };
+
+//! @brief Get the base address of FTM by instance number.
+//! @param x FTM instance number, from 0 through 3.
+#define REGS_FTM_BASE(x) (__g_regs_FTM_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of FTM.
+#define REGS_FTM_INSTANCE(b) ((b) == REGS_FTM0_BASE ? HW_FTM0 : (b) == REGS_FTM1_BASE ? HW_FTM1 : (b) == REGS_FTM2_BASE ? HW_FTM2 : (b) == REGS_FTM3_BASE ? HW_FTM3 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_SC - Status And Control
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_SC - Status And Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * SC contains the overflow status flag and control bits used to configure the
+ * interrupt enable, FTM configuration, clock source, and prescaler factor. These
+ * controls relate to all channels within this module.
+ */
+typedef union _hw_ftm_sc
+{
+ uint32_t U;
+ struct _hw_ftm_sc_bitfields
+ {
+ uint32_t PS : 3; //!< [2:0] Prescale Factor Selection
+ uint32_t CLKS : 2; //!< [4:3] Clock Source Selection
+ uint32_t CPWMS : 1; //!< [5] Center-Aligned PWM Select
+ uint32_t TOIE : 1; //!< [6] Timer Overflow Interrupt Enable
+ uint32_t TOF : 1; //!< [7] Timer Overflow Flag
+ uint32_t RESERVED0 : 24; //!< [31:8]
+ } B;
+} hw_ftm_sc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_SC register
+ */
+//@{
+#define HW_FTM_SC_ADDR(x) (REGS_FTM_BASE(x) + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_SC(x) (*(__IO hw_ftm_sc_t *) HW_FTM_SC_ADDR(x))
+#define HW_FTM_SC_RD(x) (HW_FTM_SC(x).U)
+#define HW_FTM_SC_WR(x, v) (HW_FTM_SC(x).U = (v))
+#define HW_FTM_SC_SET(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) | (v)))
+#define HW_FTM_SC_CLR(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) & ~(v)))
+#define HW_FTM_SC_TOG(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_SC bitfields
+ */
+
+/*!
+ * @name Register FTM_SC, field PS[2:0] (RW)
+ *
+ * Selects one of 8 division factors for the clock source selected by CLKS. The
+ * new prescaler factor affects the clock source on the next system clock cycle
+ * after the new value is updated into the register bits. This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 000 - Divide by 1
+ * - 001 - Divide by 2
+ * - 010 - Divide by 4
+ * - 011 - Divide by 8
+ * - 100 - Divide by 16
+ * - 101 - Divide by 32
+ * - 110 - Divide by 64
+ * - 111 - Divide by 128
+ */
+//@{
+#define BP_FTM_SC_PS (0U) //!< Bit position for FTM_SC_PS.
+#define BM_FTM_SC_PS (0x00000007U) //!< Bit mask for FTM_SC_PS.
+#define BS_FTM_SC_PS (3U) //!< Bit field size in bits for FTM_SC_PS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SC_PS field.
+#define BR_FTM_SC_PS(x) (HW_FTM_SC(x).B.PS)
+#endif
+
+//! @brief Format value for bitfield FTM_SC_PS.
+#define BF_FTM_SC_PS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SC_PS), uint32_t) & BM_FTM_SC_PS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PS field to a new value.
+#define BW_FTM_SC_PS(x, v) (HW_FTM_SC_WR(x, (HW_FTM_SC_RD(x) & ~BM_FTM_SC_PS) | BF_FTM_SC_PS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SC, field CLKS[4:3] (RW)
+ *
+ * Selects one of the three FTM counter clock sources. This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 00 - No clock selected. This in effect disables the FTM counter.
+ * - 01 - System clock
+ * - 10 - Fixed frequency clock
+ * - 11 - External clock
+ */
+//@{
+#define BP_FTM_SC_CLKS (3U) //!< Bit position for FTM_SC_CLKS.
+#define BM_FTM_SC_CLKS (0x00000018U) //!< Bit mask for FTM_SC_CLKS.
+#define BS_FTM_SC_CLKS (2U) //!< Bit field size in bits for FTM_SC_CLKS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SC_CLKS field.
+#define BR_FTM_SC_CLKS(x) (HW_FTM_SC(x).B.CLKS)
+#endif
+
+//! @brief Format value for bitfield FTM_SC_CLKS.
+#define BF_FTM_SC_CLKS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SC_CLKS), uint32_t) & BM_FTM_SC_CLKS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLKS field to a new value.
+#define BW_FTM_SC_CLKS(x, v) (HW_FTM_SC_WR(x, (HW_FTM_SC_RD(x) & ~BM_FTM_SC_CLKS) | BF_FTM_SC_CLKS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SC, field CPWMS[5] (RW)
+ *
+ * Selects CPWM mode. This mode configures the FTM to operate in Up-Down
+ * Counting mode. This field is write protected. It can be written only when MODE[WPDIS]
+ * = 1.
+ *
+ * Values:
+ * - 0 - FTM counter operates in Up Counting mode.
+ * - 1 - FTM counter operates in Up-Down Counting mode.
+ */
+//@{
+#define BP_FTM_SC_CPWMS (5U) //!< Bit position for FTM_SC_CPWMS.
+#define BM_FTM_SC_CPWMS (0x00000020U) //!< Bit mask for FTM_SC_CPWMS.
+#define BS_FTM_SC_CPWMS (1U) //!< Bit field size in bits for FTM_SC_CPWMS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SC_CPWMS field.
+#define BR_FTM_SC_CPWMS(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_CPWMS))
+#endif
+
+//! @brief Format value for bitfield FTM_SC_CPWMS.
+#define BF_FTM_SC_CPWMS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SC_CPWMS), uint32_t) & BM_FTM_SC_CPWMS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CPWMS field to a new value.
+#define BW_FTM_SC_CPWMS(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_CPWMS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SC, field TOIE[6] (RW)
+ *
+ * Enables FTM overflow interrupts.
+ *
+ * Values:
+ * - 0 - Disable TOF interrupts. Use software polling.
+ * - 1 - Enable TOF interrupts. An interrupt is generated when TOF equals one.
+ */
+//@{
+#define BP_FTM_SC_TOIE (6U) //!< Bit position for FTM_SC_TOIE.
+#define BM_FTM_SC_TOIE (0x00000040U) //!< Bit mask for FTM_SC_TOIE.
+#define BS_FTM_SC_TOIE (1U) //!< Bit field size in bits for FTM_SC_TOIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SC_TOIE field.
+#define BR_FTM_SC_TOIE(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOIE))
+#endif
+
+//! @brief Format value for bitfield FTM_SC_TOIE.
+#define BF_FTM_SC_TOIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SC_TOIE), uint32_t) & BM_FTM_SC_TOIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TOIE field to a new value.
+#define BW_FTM_SC_TOIE(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SC, field TOF[7] (ROWZ)
+ *
+ * Set by hardware when the FTM counter passes the value in the MOD register.
+ * The TOF bit is cleared by reading the SC register while TOF is set and then
+ * writing a 0 to TOF bit. Writing a 1 to TOF has no effect. If another FTM overflow
+ * occurs between the read and write operations, the write operation has no
+ * effect; therefore, TOF remains set indicating an overflow has occurred. In this
+ * case, a TOF interrupt request is not lost due to the clearing sequence for a
+ * previous TOF.
+ *
+ * Values:
+ * - 0 - FTM counter has not overflowed.
+ * - 1 - FTM counter has overflowed.
+ */
+//@{
+#define BP_FTM_SC_TOF (7U) //!< Bit position for FTM_SC_TOF.
+#define BM_FTM_SC_TOF (0x00000080U) //!< Bit mask for FTM_SC_TOF.
+#define BS_FTM_SC_TOF (1U) //!< Bit field size in bits for FTM_SC_TOF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SC_TOF field.
+#define BR_FTM_SC_TOF(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOF))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_CNT - Counter
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_CNT - Counter (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The CNT register contains the FTM counter value. Reset clears the CNT
+ * register. Writing any value to COUNT updates the counter with its initial value,
+ * CNTIN. When BDM is active, the FTM counter is frozen. This is the value that you
+ * may read.
+ */
+typedef union _hw_ftm_cnt
+{
+ uint32_t U;
+ struct _hw_ftm_cnt_bitfields
+ {
+ uint32_t COUNT : 16; //!< [15:0] Counter Value
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_ftm_cnt_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_CNT register
+ */
+//@{
+#define HW_FTM_CNT_ADDR(x) (REGS_FTM_BASE(x) + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_CNT(x) (*(__IO hw_ftm_cnt_t *) HW_FTM_CNT_ADDR(x))
+#define HW_FTM_CNT_RD(x) (HW_FTM_CNT(x).U)
+#define HW_FTM_CNT_WR(x, v) (HW_FTM_CNT(x).U = (v))
+#define HW_FTM_CNT_SET(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) | (v)))
+#define HW_FTM_CNT_CLR(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) & ~(v)))
+#define HW_FTM_CNT_TOG(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_CNT bitfields
+ */
+
+/*!
+ * @name Register FTM_CNT, field COUNT[15:0] (RW)
+ */
+//@{
+#define BP_FTM_CNT_COUNT (0U) //!< Bit position for FTM_CNT_COUNT.
+#define BM_FTM_CNT_COUNT (0x0000FFFFU) //!< Bit mask for FTM_CNT_COUNT.
+#define BS_FTM_CNT_COUNT (16U) //!< Bit field size in bits for FTM_CNT_COUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_CNT_COUNT field.
+#define BR_FTM_CNT_COUNT(x) (HW_FTM_CNT(x).B.COUNT)
+#endif
+
+//! @brief Format value for bitfield FTM_CNT_COUNT.
+#define BF_FTM_CNT_COUNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CNT_COUNT), uint32_t) & BM_FTM_CNT_COUNT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COUNT field to a new value.
+#define BW_FTM_CNT_COUNT(x, v) (HW_FTM_CNT_WR(x, (HW_FTM_CNT_RD(x) & ~BM_FTM_CNT_COUNT) | BF_FTM_CNT_COUNT(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_MOD - Modulo
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_MOD - Modulo (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Modulo register contains the modulo value for the FTM counter. After the
+ * FTM counter reaches the modulo value, the overflow flag (TOF) becomes set at
+ * the next clock, and the next value of FTM counter depends on the selected
+ * counting method; see Counter. Writing to the MOD register latches the value into a
+ * buffer. The MOD register is updated with the value of its write buffer
+ * according to Registers updated from write buffers. If FTMEN = 0, this write coherency
+ * mechanism may be manually reset by writing to the SC register whether BDM is
+ * active or not. Initialize the FTM counter, by writing to CNT, before writing
+ * to the MOD register to avoid confusion about when the first counter overflow
+ * will occur.
+ */
+typedef union _hw_ftm_mod
+{
+ uint32_t U;
+ struct _hw_ftm_mod_bitfields
+ {
+ uint32_t MOD : 16; //!< [15:0]
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_ftm_mod_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_MOD register
+ */
+//@{
+#define HW_FTM_MOD_ADDR(x) (REGS_FTM_BASE(x) + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_MOD(x) (*(__IO hw_ftm_mod_t *) HW_FTM_MOD_ADDR(x))
+#define HW_FTM_MOD_RD(x) (HW_FTM_MOD(x).U)
+#define HW_FTM_MOD_WR(x, v) (HW_FTM_MOD(x).U = (v))
+#define HW_FTM_MOD_SET(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) | (v)))
+#define HW_FTM_MOD_CLR(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) & ~(v)))
+#define HW_FTM_MOD_TOG(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_MOD bitfields
+ */
+
+/*!
+ * @name Register FTM_MOD, field MOD[15:0] (RW)
+ *
+ * Modulo Value
+ */
+//@{
+#define BP_FTM_MOD_MOD (0U) //!< Bit position for FTM_MOD_MOD.
+#define BM_FTM_MOD_MOD (0x0000FFFFU) //!< Bit mask for FTM_MOD_MOD.
+#define BS_FTM_MOD_MOD (16U) //!< Bit field size in bits for FTM_MOD_MOD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_MOD_MOD field.
+#define BR_FTM_MOD_MOD(x) (HW_FTM_MOD(x).B.MOD)
+#endif
+
+//! @brief Format value for bitfield FTM_MOD_MOD.
+#define BF_FTM_MOD_MOD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MOD_MOD), uint32_t) & BM_FTM_MOD_MOD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MOD field to a new value.
+#define BW_FTM_MOD_MOD(x, v) (HW_FTM_MOD_WR(x, (HW_FTM_MOD_RD(x) & ~BM_FTM_MOD_MOD) | BF_FTM_MOD_MOD(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_CnSC - Channel (n) Status And Control
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_CnSC - Channel (n) Status And Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * CnSC contains the channel-interrupt-status flag and control bits used to
+ * configure the interrupt enable, channel configuration, and pin function. Mode,
+ * edge, and level selection DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode
+ * Configuration X X X XX 0 Pin not used for FTM-revert the channel pin to general
+ * purpose I/O or other peripheral control 0 0 0 0 1 Input Capture Capture on Rising
+ * Edge Only 10 Capture on Falling Edge Only 11 Capture on Rising or Falling Edge
+ * 1 1 Output Compare Toggle Output on match 10 Clear Output on match 11 Set
+ * Output on match 1X 10 Edge-Aligned PWM High-true pulses (clear Output on match)
+ * X1 Low-true pulses (set Output on match) 1 XX 10 Center-Aligned PWM High-true
+ * pulses (clear Output on match-up) X1 Low-true pulses (set Output on match-up) 1
+ * 0 XX 10 Combine PWM High-true pulses (set on channel (n) match, and clear on
+ * channel (n+1) match) X1 Low-true pulses (clear on channel (n) match, and set
+ * on channel (n+1) match) 1 0 0 X0 See the following table (#ModeSel2Table). Dual
+ * Edge Capture One-Shot Capture mode X1 Continuous Capture mode Dual Edge
+ * Capture mode - edge polarity selection ELSnB ELSnA Channel Port Enable Detected
+ * Edges 0 0 Disabled No edge 0 1 Enabled Rising edge 1 0 Enabled Falling edge 1 1
+ * Enabled Rising and falling edges
+ */
+typedef union _hw_ftm_cnsc
+{
+ uint32_t U;
+ struct _hw_ftm_cnsc_bitfields
+ {
+ uint32_t DMAb : 1; //!< [0] DMA Enable
+ uint32_t RESERVED0 : 1; //!< [1]
+ uint32_t ELSA : 1; //!< [2] Edge or Level Select
+ uint32_t ELSB : 1; //!< [3] Edge or Level Select
+ uint32_t MSA : 1; //!< [4] Channel Mode Select
+ uint32_t MSB : 1; //!< [5] Channel Mode Select
+ uint32_t CHIE : 1; //!< [6] Channel Interrupt Enable
+ uint32_t CHF : 1; //!< [7] Channel Flag
+ uint32_t RESERVED1 : 24; //!< [31:8]
+ } B;
+} hw_ftm_cnsc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_CnSC register
+ */
+//@{
+#define HW_FTM_CnSC_COUNT (8U)
+
+#define HW_FTM_CnSC_ADDR(x, n) (REGS_FTM_BASE(x) + 0xCU + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_CnSC(x, n) (*(__IO hw_ftm_cnsc_t *) HW_FTM_CnSC_ADDR(x, n))
+#define HW_FTM_CnSC_RD(x, n) (HW_FTM_CnSC(x, n).U)
+#define HW_FTM_CnSC_WR(x, n, v) (HW_FTM_CnSC(x, n).U = (v))
+#define HW_FTM_CnSC_SET(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) | (v)))
+#define HW_FTM_CnSC_CLR(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) & ~(v)))
+#define HW_FTM_CnSC_TOG(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_CnSC bitfields
+ */
+
+/*!
+ * @name Register FTM_CnSC, field DMA[0] (RW)
+ *
+ * Enables DMA transfers for the channel.
+ *
+ * Values:
+ * - 0 - Disable DMA transfers.
+ * - 1 - Enable DMA transfers.
+ */
+//@{
+#define BP_FTM_CnSC_DMA (0U) //!< Bit position for FTM_CnSC_DMA.
+#define BM_FTM_CnSC_DMA (0x00000001U) //!< Bit mask for FTM_CnSC_DMA.
+#define BS_FTM_CnSC_DMA (1U) //!< Bit field size in bits for FTM_CnSC_DMA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_CnSC_DMA field.
+#define BR_FTM_CnSC_DMA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_DMA))
+#endif
+
+//! @brief Format value for bitfield FTM_CnSC_DMA.
+#define BF_FTM_CnSC_DMA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_DMA), uint32_t) & BM_FTM_CnSC_DMA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMA field to a new value.
+#define BW_FTM_CnSC_DMA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_DMA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_CnSC, field ELSA[2] (RW)
+ *
+ * The functionality of ELSB and ELSA depends on the channel mode. See
+ * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
+ * = 1.
+ */
+//@{
+#define BP_FTM_CnSC_ELSA (2U) //!< Bit position for FTM_CnSC_ELSA.
+#define BM_FTM_CnSC_ELSA (0x00000004U) //!< Bit mask for FTM_CnSC_ELSA.
+#define BS_FTM_CnSC_ELSA (1U) //!< Bit field size in bits for FTM_CnSC_ELSA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_CnSC_ELSA field.
+#define BR_FTM_CnSC_ELSA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSA))
+#endif
+
+//! @brief Format value for bitfield FTM_CnSC_ELSA.
+#define BF_FTM_CnSC_ELSA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_ELSA), uint32_t) & BM_FTM_CnSC_ELSA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ELSA field to a new value.
+#define BW_FTM_CnSC_ELSA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_CnSC, field ELSB[3] (RW)
+ *
+ * The functionality of ELSB and ELSA depends on the channel mode. See
+ * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
+ * = 1.
+ */
+//@{
+#define BP_FTM_CnSC_ELSB (3U) //!< Bit position for FTM_CnSC_ELSB.
+#define BM_FTM_CnSC_ELSB (0x00000008U) //!< Bit mask for FTM_CnSC_ELSB.
+#define BS_FTM_CnSC_ELSB (1U) //!< Bit field size in bits for FTM_CnSC_ELSB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_CnSC_ELSB field.
+#define BR_FTM_CnSC_ELSB(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSB))
+#endif
+
+//! @brief Format value for bitfield FTM_CnSC_ELSB.
+#define BF_FTM_CnSC_ELSB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_ELSB), uint32_t) & BM_FTM_CnSC_ELSB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ELSB field to a new value.
+#define BW_FTM_CnSC_ELSB(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSB) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_CnSC, field MSA[4] (RW)
+ *
+ * Used for further selections in the channel logic. Its functionality is
+ * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ */
+//@{
+#define BP_FTM_CnSC_MSA (4U) //!< Bit position for FTM_CnSC_MSA.
+#define BM_FTM_CnSC_MSA (0x00000010U) //!< Bit mask for FTM_CnSC_MSA.
+#define BS_FTM_CnSC_MSA (1U) //!< Bit field size in bits for FTM_CnSC_MSA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_CnSC_MSA field.
+#define BR_FTM_CnSC_MSA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSA))
+#endif
+
+//! @brief Format value for bitfield FTM_CnSC_MSA.
+#define BF_FTM_CnSC_MSA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_MSA), uint32_t) & BM_FTM_CnSC_MSA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MSA field to a new value.
+#define BW_FTM_CnSC_MSA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_CnSC, field MSB[5] (RW)
+ *
+ * Used for further selections in the channel logic. Its functionality is
+ * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ */
+//@{
+#define BP_FTM_CnSC_MSB (5U) //!< Bit position for FTM_CnSC_MSB.
+#define BM_FTM_CnSC_MSB (0x00000020U) //!< Bit mask for FTM_CnSC_MSB.
+#define BS_FTM_CnSC_MSB (1U) //!< Bit field size in bits for FTM_CnSC_MSB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_CnSC_MSB field.
+#define BR_FTM_CnSC_MSB(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSB))
+#endif
+
+//! @brief Format value for bitfield FTM_CnSC_MSB.
+#define BF_FTM_CnSC_MSB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_MSB), uint32_t) & BM_FTM_CnSC_MSB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MSB field to a new value.
+#define BW_FTM_CnSC_MSB(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSB) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_CnSC, field CHIE[6] (RW)
+ *
+ * Enables channel interrupts.
+ *
+ * Values:
+ * - 0 - Disable channel interrupts. Use software polling.
+ * - 1 - Enable channel interrupts.
+ */
+//@{
+#define BP_FTM_CnSC_CHIE (6U) //!< Bit position for FTM_CnSC_CHIE.
+#define BM_FTM_CnSC_CHIE (0x00000040U) //!< Bit mask for FTM_CnSC_CHIE.
+#define BS_FTM_CnSC_CHIE (1U) //!< Bit field size in bits for FTM_CnSC_CHIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_CnSC_CHIE field.
+#define BR_FTM_CnSC_CHIE(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHIE))
+#endif
+
+//! @brief Format value for bitfield FTM_CnSC_CHIE.
+#define BF_FTM_CnSC_CHIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnSC_CHIE), uint32_t) & BM_FTM_CnSC_CHIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CHIE field to a new value.
+#define BW_FTM_CnSC_CHIE(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_CnSC, field CHF[7] (ROWZ)
+ *
+ * Set by hardware when an event occurs on the channel. CHF is cleared by
+ * reading the CSC register while CHnF is set and then writing a 0 to the CHF bit.
+ * Writing a 1 to CHF has no effect. If another event occurs between the read and
+ * write operations, the write operation has no effect; therefore, CHF remains set
+ * indicating an event has occurred. In this case a CHF interrupt request is not
+ * lost due to the clearing sequence for a previous CHF.
+ *
+ * Values:
+ * - 0 - No channel event has occurred.
+ * - 1 - A channel event has occurred.
+ */
+//@{
+#define BP_FTM_CnSC_CHF (7U) //!< Bit position for FTM_CnSC_CHF.
+#define BM_FTM_CnSC_CHF (0x00000080U) //!< Bit mask for FTM_CnSC_CHF.
+#define BS_FTM_CnSC_CHF (1U) //!< Bit field size in bits for FTM_CnSC_CHF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_CnSC_CHF field.
+#define BR_FTM_CnSC_CHF(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHF))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_FTM_CnV - Channel (n) Value
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_CnV - Channel (n) Value (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers contain the captured FTM counter value for the input modes or
+ * the match value for the output modes. In Input Capture, Capture Test, and
+ * Dual Edge Capture modes, any write to a CnV register is ignored. In output modes,
+ * writing to a CnV register latches the value into a buffer. A CnV register is
+ * updated with the value of its write buffer according to Registers updated from
+ * write buffers. If FTMEN = 0, this write coherency mechanism may be manually
+ * reset by writing to the CnSC register whether BDM mode is active or not.
+ */
+typedef union _hw_ftm_cnv
+{
+ uint32_t U;
+ struct _hw_ftm_cnv_bitfields
+ {
+ uint32_t VAL : 16; //!< [15:0] Channel Value
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_ftm_cnv_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_CnV register
+ */
+//@{
+#define HW_FTM_CnV_COUNT (8U)
+
+#define HW_FTM_CnV_ADDR(x, n) (REGS_FTM_BASE(x) + 0x10U + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_CnV(x, n) (*(__IO hw_ftm_cnv_t *) HW_FTM_CnV_ADDR(x, n))
+#define HW_FTM_CnV_RD(x, n) (HW_FTM_CnV(x, n).U)
+#define HW_FTM_CnV_WR(x, n, v) (HW_FTM_CnV(x, n).U = (v))
+#define HW_FTM_CnV_SET(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) | (v)))
+#define HW_FTM_CnV_CLR(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) & ~(v)))
+#define HW_FTM_CnV_TOG(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_CnV bitfields
+ */
+
+/*!
+ * @name Register FTM_CnV, field VAL[15:0] (RW)
+ *
+ * Captured FTM counter value of the input modes or the match value for the
+ * output modes
+ */
+//@{
+#define BP_FTM_CnV_VAL (0U) //!< Bit position for FTM_CnV_VAL.
+#define BM_FTM_CnV_VAL (0x0000FFFFU) //!< Bit mask for FTM_CnV_VAL.
+#define BS_FTM_CnV_VAL (16U) //!< Bit field size in bits for FTM_CnV_VAL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_CnV_VAL field.
+#define BR_FTM_CnV_VAL(x, n) (HW_FTM_CnV(x, n).B.VAL)
+#endif
+
+//! @brief Format value for bitfield FTM_CnV_VAL.
+#define BF_FTM_CnV_VAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CnV_VAL), uint32_t) & BM_FTM_CnV_VAL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the VAL field to a new value.
+#define BW_FTM_CnV_VAL(x, n, v) (HW_FTM_CnV_WR(x, n, (HW_FTM_CnV_RD(x, n) & ~BM_FTM_CnV_VAL) | BF_FTM_CnV_VAL(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_CNTIN - Counter Initial Value
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_CNTIN - Counter Initial Value (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Counter Initial Value register contains the initial value for the FTM
+ * counter. Writing to the CNTIN register latches the value into a buffer. The CNTIN
+ * register is updated with the value of its write buffer according to Registers
+ * updated from write buffers. When the FTM clock is initially selected, by
+ * writing a non-zero value to the CLKS bits, the FTM counter starts with the value
+ * 0x0000. To avoid this behavior, before the first write to select the FTM clock,
+ * write the new value to the the CNTIN register and then initialize the FTM
+ * counter by writing any value to the CNT register.
+ */
+typedef union _hw_ftm_cntin
+{
+ uint32_t U;
+ struct _hw_ftm_cntin_bitfields
+ {
+ uint32_t INIT : 16; //!< [15:0]
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_ftm_cntin_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_CNTIN register
+ */
+//@{
+#define HW_FTM_CNTIN_ADDR(x) (REGS_FTM_BASE(x) + 0x4CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_CNTIN(x) (*(__IO hw_ftm_cntin_t *) HW_FTM_CNTIN_ADDR(x))
+#define HW_FTM_CNTIN_RD(x) (HW_FTM_CNTIN(x).U)
+#define HW_FTM_CNTIN_WR(x, v) (HW_FTM_CNTIN(x).U = (v))
+#define HW_FTM_CNTIN_SET(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) | (v)))
+#define HW_FTM_CNTIN_CLR(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) & ~(v)))
+#define HW_FTM_CNTIN_TOG(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_CNTIN bitfields
+ */
+
+/*!
+ * @name Register FTM_CNTIN, field INIT[15:0] (RW)
+ *
+ * Initial Value Of The FTM Counter
+ */
+//@{
+#define BP_FTM_CNTIN_INIT (0U) //!< Bit position for FTM_CNTIN_INIT.
+#define BM_FTM_CNTIN_INIT (0x0000FFFFU) //!< Bit mask for FTM_CNTIN_INIT.
+#define BS_FTM_CNTIN_INIT (16U) //!< Bit field size in bits for FTM_CNTIN_INIT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_CNTIN_INIT field.
+#define BR_FTM_CNTIN_INIT(x) (HW_FTM_CNTIN(x).B.INIT)
+#endif
+
+//! @brief Format value for bitfield FTM_CNTIN_INIT.
+#define BF_FTM_CNTIN_INIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CNTIN_INIT), uint32_t) & BM_FTM_CNTIN_INIT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INIT field to a new value.
+#define BW_FTM_CNTIN_INIT(x, v) (HW_FTM_CNTIN_WR(x, (HW_FTM_CNTIN_RD(x) & ~BM_FTM_CNTIN_INIT) | BF_FTM_CNTIN_INIT(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_STATUS - Capture And Compare Status
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_STATUS - Capture And Compare Status (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The STATUS register contains a copy of the status flag CHnF bit in CnSC for
+ * each FTM channel for software convenience. Each CHnF bit in STATUS is a mirror
+ * of CHnF bit in CnSC. All CHnF bits can be checked using only one read of
+ * STATUS. All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to
+ * STATUS. Hardware sets the individual channel flags when an event occurs on the
+ * channel. CHnF is cleared by reading STATUS while CHnF is set and then writing
+ * a 0 to the CHnF bit. Writing a 1 to CHnF has no effect. If another event
+ * occurs between the read and write operations, the write operation has no effect;
+ * therefore, CHnF remains set indicating an event has occurred. In this case, a
+ * CHnF interrupt request is not lost due to the clearing sequence for a previous
+ * CHnF. The STATUS register should be used only in Combine mode.
+ */
+typedef union _hw_ftm_status
+{
+ uint32_t U;
+ struct _hw_ftm_status_bitfields
+ {
+ uint32_t CH0F : 1; //!< [0] Channel 0 Flag
+ uint32_t CH1F : 1; //!< [1] Channel 1 Flag
+ uint32_t CH2F : 1; //!< [2] Channel 2 Flag
+ uint32_t CH3F : 1; //!< [3] Channel 3 Flag
+ uint32_t CH4F : 1; //!< [4] Channel 4 Flag
+ uint32_t CH5F : 1; //!< [5] Channel 5 Flag
+ uint32_t CH6F : 1; //!< [6] Channel 6 Flag
+ uint32_t CH7F : 1; //!< [7] Channel 7 Flag
+ uint32_t RESERVED0 : 24; //!< [31:8]
+ } B;
+} hw_ftm_status_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_STATUS register
+ */
+//@{
+#define HW_FTM_STATUS_ADDR(x) (REGS_FTM_BASE(x) + 0x50U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_STATUS(x) (*(__IO hw_ftm_status_t *) HW_FTM_STATUS_ADDR(x))
+#define HW_FTM_STATUS_RD(x) (HW_FTM_STATUS(x).U)
+#define HW_FTM_STATUS_WR(x, v) (HW_FTM_STATUS(x).U = (v))
+#define HW_FTM_STATUS_SET(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) | (v)))
+#define HW_FTM_STATUS_CLR(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) & ~(v)))
+#define HW_FTM_STATUS_TOG(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_STATUS bitfields
+ */
+
+/*!
+ * @name Register FTM_STATUS, field CH0F[0] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0 - No channel event has occurred.
+ * - 1 - A channel event has occurred.
+ */
+//@{
+#define BP_FTM_STATUS_CH0F (0U) //!< Bit position for FTM_STATUS_CH0F.
+#define BM_FTM_STATUS_CH0F (0x00000001U) //!< Bit mask for FTM_STATUS_CH0F.
+#define BS_FTM_STATUS_CH0F (1U) //!< Bit field size in bits for FTM_STATUS_CH0F.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_STATUS_CH0F field.
+#define BR_FTM_STATUS_CH0F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH0F))
+#endif
+
+//! @brief Format value for bitfield FTM_STATUS_CH0F.
+#define BF_FTM_STATUS_CH0F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH0F), uint32_t) & BM_FTM_STATUS_CH0F)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH0F field to a new value.
+#define BW_FTM_STATUS_CH0F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH0F) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_STATUS, field CH1F[1] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0 - No channel event has occurred.
+ * - 1 - A channel event has occurred.
+ */
+//@{
+#define BP_FTM_STATUS_CH1F (1U) //!< Bit position for FTM_STATUS_CH1F.
+#define BM_FTM_STATUS_CH1F (0x00000002U) //!< Bit mask for FTM_STATUS_CH1F.
+#define BS_FTM_STATUS_CH1F (1U) //!< Bit field size in bits for FTM_STATUS_CH1F.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_STATUS_CH1F field.
+#define BR_FTM_STATUS_CH1F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH1F))
+#endif
+
+//! @brief Format value for bitfield FTM_STATUS_CH1F.
+#define BF_FTM_STATUS_CH1F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH1F), uint32_t) & BM_FTM_STATUS_CH1F)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH1F field to a new value.
+#define BW_FTM_STATUS_CH1F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH1F) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_STATUS, field CH2F[2] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0 - No channel event has occurred.
+ * - 1 - A channel event has occurred.
+ */
+//@{
+#define BP_FTM_STATUS_CH2F (2U) //!< Bit position for FTM_STATUS_CH2F.
+#define BM_FTM_STATUS_CH2F (0x00000004U) //!< Bit mask for FTM_STATUS_CH2F.
+#define BS_FTM_STATUS_CH2F (1U) //!< Bit field size in bits for FTM_STATUS_CH2F.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_STATUS_CH2F field.
+#define BR_FTM_STATUS_CH2F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH2F))
+#endif
+
+//! @brief Format value for bitfield FTM_STATUS_CH2F.
+#define BF_FTM_STATUS_CH2F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH2F), uint32_t) & BM_FTM_STATUS_CH2F)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH2F field to a new value.
+#define BW_FTM_STATUS_CH2F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH2F) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_STATUS, field CH3F[3] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0 - No channel event has occurred.
+ * - 1 - A channel event has occurred.
+ */
+//@{
+#define BP_FTM_STATUS_CH3F (3U) //!< Bit position for FTM_STATUS_CH3F.
+#define BM_FTM_STATUS_CH3F (0x00000008U) //!< Bit mask for FTM_STATUS_CH3F.
+#define BS_FTM_STATUS_CH3F (1U) //!< Bit field size in bits for FTM_STATUS_CH3F.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_STATUS_CH3F field.
+#define BR_FTM_STATUS_CH3F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH3F))
+#endif
+
+//! @brief Format value for bitfield FTM_STATUS_CH3F.
+#define BF_FTM_STATUS_CH3F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH3F), uint32_t) & BM_FTM_STATUS_CH3F)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH3F field to a new value.
+#define BW_FTM_STATUS_CH3F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH3F) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_STATUS, field CH4F[4] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0 - No channel event has occurred.
+ * - 1 - A channel event has occurred.
+ */
+//@{
+#define BP_FTM_STATUS_CH4F (4U) //!< Bit position for FTM_STATUS_CH4F.
+#define BM_FTM_STATUS_CH4F (0x00000010U) //!< Bit mask for FTM_STATUS_CH4F.
+#define BS_FTM_STATUS_CH4F (1U) //!< Bit field size in bits for FTM_STATUS_CH4F.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_STATUS_CH4F field.
+#define BR_FTM_STATUS_CH4F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH4F))
+#endif
+
+//! @brief Format value for bitfield FTM_STATUS_CH4F.
+#define BF_FTM_STATUS_CH4F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH4F), uint32_t) & BM_FTM_STATUS_CH4F)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH4F field to a new value.
+#define BW_FTM_STATUS_CH4F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH4F) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_STATUS, field CH5F[5] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0 - No channel event has occurred.
+ * - 1 - A channel event has occurred.
+ */
+//@{
+#define BP_FTM_STATUS_CH5F (5U) //!< Bit position for FTM_STATUS_CH5F.
+#define BM_FTM_STATUS_CH5F (0x00000020U) //!< Bit mask for FTM_STATUS_CH5F.
+#define BS_FTM_STATUS_CH5F (1U) //!< Bit field size in bits for FTM_STATUS_CH5F.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_STATUS_CH5F field.
+#define BR_FTM_STATUS_CH5F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH5F))
+#endif
+
+//! @brief Format value for bitfield FTM_STATUS_CH5F.
+#define BF_FTM_STATUS_CH5F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH5F), uint32_t) & BM_FTM_STATUS_CH5F)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH5F field to a new value.
+#define BW_FTM_STATUS_CH5F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH5F) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_STATUS, field CH6F[6] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0 - No channel event has occurred.
+ * - 1 - A channel event has occurred.
+ */
+//@{
+#define BP_FTM_STATUS_CH6F (6U) //!< Bit position for FTM_STATUS_CH6F.
+#define BM_FTM_STATUS_CH6F (0x00000040U) //!< Bit mask for FTM_STATUS_CH6F.
+#define BS_FTM_STATUS_CH6F (1U) //!< Bit field size in bits for FTM_STATUS_CH6F.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_STATUS_CH6F field.
+#define BR_FTM_STATUS_CH6F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH6F))
+#endif
+
+//! @brief Format value for bitfield FTM_STATUS_CH6F.
+#define BF_FTM_STATUS_CH6F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH6F), uint32_t) & BM_FTM_STATUS_CH6F)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH6F field to a new value.
+#define BW_FTM_STATUS_CH6F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH6F) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_STATUS, field CH7F[7] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0 - No channel event has occurred.
+ * - 1 - A channel event has occurred.
+ */
+//@{
+#define BP_FTM_STATUS_CH7F (7U) //!< Bit position for FTM_STATUS_CH7F.
+#define BM_FTM_STATUS_CH7F (0x00000080U) //!< Bit mask for FTM_STATUS_CH7F.
+#define BS_FTM_STATUS_CH7F (1U) //!< Bit field size in bits for FTM_STATUS_CH7F.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_STATUS_CH7F field.
+#define BR_FTM_STATUS_CH7F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH7F))
+#endif
+
+//! @brief Format value for bitfield FTM_STATUS_CH7F.
+#define BF_FTM_STATUS_CH7F(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_STATUS_CH7F), uint32_t) & BM_FTM_STATUS_CH7F)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH7F field to a new value.
+#define BW_FTM_STATUS_CH7F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH7F) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_MODE - Features Mode Selection
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_MODE - Features Mode Selection (RW)
+ *
+ * Reset value: 0x00000004U
+ *
+ * This register contains the global enable bit for FTM-specific features and
+ * the control bits used to configure: Fault control mode and interrupt Capture
+ * Test mode PWM synchronization Write protection Channel output initialization
+ * These controls relate to all channels within this module.
+ */
+typedef union _hw_ftm_mode
+{
+ uint32_t U;
+ struct _hw_ftm_mode_bitfields
+ {
+ uint32_t FTMEN : 1; //!< [0] FTM Enable
+ uint32_t INIT : 1; //!< [1] Initialize The Channels Output
+ uint32_t WPDIS : 1; //!< [2] Write Protection Disable
+ uint32_t PWMSYNC : 1; //!< [3] PWM Synchronization Mode
+ uint32_t CAPTEST : 1; //!< [4] Capture Test Mode Enable
+ uint32_t FAULTM : 2; //!< [6:5] Fault Control Mode
+ uint32_t FAULTIE : 1; //!< [7] Fault Interrupt Enable
+ uint32_t RESERVED0 : 24; //!< [31:8]
+ } B;
+} hw_ftm_mode_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_MODE register
+ */
+//@{
+#define HW_FTM_MODE_ADDR(x) (REGS_FTM_BASE(x) + 0x54U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_MODE(x) (*(__IO hw_ftm_mode_t *) HW_FTM_MODE_ADDR(x))
+#define HW_FTM_MODE_RD(x) (HW_FTM_MODE(x).U)
+#define HW_FTM_MODE_WR(x, v) (HW_FTM_MODE(x).U = (v))
+#define HW_FTM_MODE_SET(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) | (v)))
+#define HW_FTM_MODE_CLR(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) & ~(v)))
+#define HW_FTM_MODE_TOG(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_MODE bitfields
+ */
+
+/*!
+ * @name Register FTM_MODE, field FTMEN[0] (RW)
+ *
+ * This field is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Only the TPM-compatible registers (first set of registers) can be used
+ * without any restriction. Do not use the FTM-specific registers.
+ * - 1 - All registers including the FTM-specific registers (second set of
+ * registers) are available for use with no restrictions.
+ */
+//@{
+#define BP_FTM_MODE_FTMEN (0U) //!< Bit position for FTM_MODE_FTMEN.
+#define BM_FTM_MODE_FTMEN (0x00000001U) //!< Bit mask for FTM_MODE_FTMEN.
+#define BS_FTM_MODE_FTMEN (1U) //!< Bit field size in bits for FTM_MODE_FTMEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_MODE_FTMEN field.
+#define BR_FTM_MODE_FTMEN(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FTMEN))
+#endif
+
+//! @brief Format value for bitfield FTM_MODE_FTMEN.
+#define BF_FTM_MODE_FTMEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_FTMEN), uint32_t) & BM_FTM_MODE_FTMEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTMEN field to a new value.
+#define BW_FTM_MODE_FTMEN(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FTMEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_MODE, field INIT[1] (RW)
+ *
+ * When a 1 is written to INIT bit the channels output is initialized according
+ * to the state of their corresponding bit in the OUTINIT register. Writing a 0
+ * to INIT bit has no effect. The INIT bit is always read as 0.
+ */
+//@{
+#define BP_FTM_MODE_INIT (1U) //!< Bit position for FTM_MODE_INIT.
+#define BM_FTM_MODE_INIT (0x00000002U) //!< Bit mask for FTM_MODE_INIT.
+#define BS_FTM_MODE_INIT (1U) //!< Bit field size in bits for FTM_MODE_INIT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_MODE_INIT field.
+#define BR_FTM_MODE_INIT(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_INIT))
+#endif
+
+//! @brief Format value for bitfield FTM_MODE_INIT.
+#define BF_FTM_MODE_INIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_INIT), uint32_t) & BM_FTM_MODE_INIT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INIT field to a new value.
+#define BW_FTM_MODE_INIT(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_INIT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_MODE, field WPDIS[2] (RW)
+ *
+ * When write protection is enabled (WPDIS = 0), write protected bits cannot be
+ * written. When write protection is disabled (WPDIS = 1), write protected bits
+ * can be written. The WPDIS bit is the negation of the WPEN bit. WPDIS is cleared
+ * when 1 is written to WPEN. WPDIS is set when WPEN bit is read as a 1 and then
+ * 1 is written to WPDIS. Writing 0 to WPDIS has no effect.
+ *
+ * Values:
+ * - 0 - Write protection is enabled.
+ * - 1 - Write protection is disabled.
+ */
+//@{
+#define BP_FTM_MODE_WPDIS (2U) //!< Bit position for FTM_MODE_WPDIS.
+#define BM_FTM_MODE_WPDIS (0x00000004U) //!< Bit mask for FTM_MODE_WPDIS.
+#define BS_FTM_MODE_WPDIS (1U) //!< Bit field size in bits for FTM_MODE_WPDIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_MODE_WPDIS field.
+#define BR_FTM_MODE_WPDIS(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_WPDIS))
+#endif
+
+//! @brief Format value for bitfield FTM_MODE_WPDIS.
+#define BF_FTM_MODE_WPDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_WPDIS), uint32_t) & BM_FTM_MODE_WPDIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WPDIS field to a new value.
+#define BW_FTM_MODE_WPDIS(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_WPDIS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_MODE, field PWMSYNC[3] (RW)
+ *
+ * Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM counter
+ * synchronization. See PWM synchronization. The PWMSYNC bit configures the
+ * synchronization when SYNCMODE is 0.
+ *
+ * Values:
+ * - 0 - No restrictions. Software and hardware triggers can be used by MOD,
+ * CnV, OUTMASK, and FTM counter synchronization.
+ * - 1 - Software trigger can only be used by MOD and CnV synchronization, and
+ * hardware triggers can only be used by OUTMASK and FTM counter
+ * synchronization.
+ */
+//@{
+#define BP_FTM_MODE_PWMSYNC (3U) //!< Bit position for FTM_MODE_PWMSYNC.
+#define BM_FTM_MODE_PWMSYNC (0x00000008U) //!< Bit mask for FTM_MODE_PWMSYNC.
+#define BS_FTM_MODE_PWMSYNC (1U) //!< Bit field size in bits for FTM_MODE_PWMSYNC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_MODE_PWMSYNC field.
+#define BR_FTM_MODE_PWMSYNC(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_PWMSYNC))
+#endif
+
+//! @brief Format value for bitfield FTM_MODE_PWMSYNC.
+#define BF_FTM_MODE_PWMSYNC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_PWMSYNC), uint32_t) & BM_FTM_MODE_PWMSYNC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PWMSYNC field to a new value.
+#define BW_FTM_MODE_PWMSYNC(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_PWMSYNC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_MODE, field CAPTEST[4] (RW)
+ *
+ * Enables the capture test mode. This field is write protected. It can be
+ * written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Capture test mode is disabled.
+ * - 1 - Capture test mode is enabled.
+ */
+//@{
+#define BP_FTM_MODE_CAPTEST (4U) //!< Bit position for FTM_MODE_CAPTEST.
+#define BM_FTM_MODE_CAPTEST (0x00000010U) //!< Bit mask for FTM_MODE_CAPTEST.
+#define BS_FTM_MODE_CAPTEST (1U) //!< Bit field size in bits for FTM_MODE_CAPTEST.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_MODE_CAPTEST field.
+#define BR_FTM_MODE_CAPTEST(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_CAPTEST))
+#endif
+
+//! @brief Format value for bitfield FTM_MODE_CAPTEST.
+#define BF_FTM_MODE_CAPTEST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_CAPTEST), uint32_t) & BM_FTM_MODE_CAPTEST)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CAPTEST field to a new value.
+#define BW_FTM_MODE_CAPTEST(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_CAPTEST) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_MODE, field FAULTM[6:5] (RW)
+ *
+ * Defines the FTM fault control mode. This field is write protected. It can be
+ * written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 00 - Fault control is disabled for all channels.
+ * - 01 - Fault control is enabled for even channels only (channels 0, 2, 4, and
+ * 6), and the selected mode is the manual fault clearing.
+ * - 10 - Fault control is enabled for all channels, and the selected mode is
+ * the manual fault clearing.
+ * - 11 - Fault control is enabled for all channels, and the selected mode is
+ * the automatic fault clearing.
+ */
+//@{
+#define BP_FTM_MODE_FAULTM (5U) //!< Bit position for FTM_MODE_FAULTM.
+#define BM_FTM_MODE_FAULTM (0x00000060U) //!< Bit mask for FTM_MODE_FAULTM.
+#define BS_FTM_MODE_FAULTM (2U) //!< Bit field size in bits for FTM_MODE_FAULTM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_MODE_FAULTM field.
+#define BR_FTM_MODE_FAULTM(x) (HW_FTM_MODE(x).B.FAULTM)
+#endif
+
+//! @brief Format value for bitfield FTM_MODE_FAULTM.
+#define BF_FTM_MODE_FAULTM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_FAULTM), uint32_t) & BM_FTM_MODE_FAULTM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FAULTM field to a new value.
+#define BW_FTM_MODE_FAULTM(x, v) (HW_FTM_MODE_WR(x, (HW_FTM_MODE_RD(x) & ~BM_FTM_MODE_FAULTM) | BF_FTM_MODE_FAULTM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_MODE, field FAULTIE[7] (RW)
+ *
+ * Enables the generation of an interrupt when a fault is detected by FTM and
+ * the FTM fault control is enabled.
+ *
+ * Values:
+ * - 0 - Fault control interrupt is disabled.
+ * - 1 - Fault control interrupt is enabled.
+ */
+//@{
+#define BP_FTM_MODE_FAULTIE (7U) //!< Bit position for FTM_MODE_FAULTIE.
+#define BM_FTM_MODE_FAULTIE (0x00000080U) //!< Bit mask for FTM_MODE_FAULTIE.
+#define BS_FTM_MODE_FAULTIE (1U) //!< Bit field size in bits for FTM_MODE_FAULTIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_MODE_FAULTIE field.
+#define BR_FTM_MODE_FAULTIE(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FAULTIE))
+#endif
+
+//! @brief Format value for bitfield FTM_MODE_FAULTIE.
+#define BF_FTM_MODE_FAULTIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_MODE_FAULTIE), uint32_t) & BM_FTM_MODE_FAULTIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FAULTIE field to a new value.
+#define BW_FTM_MODE_FAULTIE(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FAULTIE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_SYNC - Synchronization
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_SYNC - Synchronization (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures the PWM synchronization. A synchronization event can
+ * perform the synchronized update of MOD, CV, and OUTMASK registers with the
+ * value of their write buffer and the FTM counter initialization. The software
+ * trigger, SWSYNC bit, and hardware triggers TRIG0, TRIG1, and TRIG2 bits have a
+ * potential conflict if used together when SYNCMODE = 0. Use only hardware or
+ * software triggers but not both at the same time, otherwise unpredictable behavior
+ * is likely to happen. The selection of the loading point, CNTMAX and CNTMIN
+ * bits, is intended to provide the update of MOD, CNTIN, and CnV registers across
+ * all enabled channels simultaneously. The use of the loading point selection
+ * together with SYNCMODE = 0 and hardware trigger selection, TRIG0, TRIG1, or TRIG2
+ * bits, is likely to result in unpredictable behavior. The synchronization
+ * event selection also depends on the PWMSYNC (MODE register) and SYNCMODE (SYNCONF
+ * register) bits. See PWM synchronization.
+ */
+typedef union _hw_ftm_sync
+{
+ uint32_t U;
+ struct _hw_ftm_sync_bitfields
+ {
+ uint32_t CNTMIN : 1; //!< [0] Minimum Loading Point Enable
+ uint32_t CNTMAX : 1; //!< [1] Maximum Loading Point Enable
+ uint32_t REINIT : 1; //!< [2] FTM Counter Reinitialization By
+ //! Synchronization (FTM counter synchronization)
+ uint32_t SYNCHOM : 1; //!< [3] Output Mask Synchronization
+ uint32_t TRIG0 : 1; //!< [4] PWM Synchronization Hardware Trigger 0
+ uint32_t TRIG1 : 1; //!< [5] PWM Synchronization Hardware Trigger 1
+ uint32_t TRIG2 : 1; //!< [6] PWM Synchronization Hardware Trigger 2
+ uint32_t SWSYNC : 1; //!< [7] PWM Synchronization Software Trigger
+ uint32_t RESERVED0 : 24; //!< [31:8]
+ } B;
+} hw_ftm_sync_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_SYNC register
+ */
+//@{
+#define HW_FTM_SYNC_ADDR(x) (REGS_FTM_BASE(x) + 0x58U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_SYNC(x) (*(__IO hw_ftm_sync_t *) HW_FTM_SYNC_ADDR(x))
+#define HW_FTM_SYNC_RD(x) (HW_FTM_SYNC(x).U)
+#define HW_FTM_SYNC_WR(x, v) (HW_FTM_SYNC(x).U = (v))
+#define HW_FTM_SYNC_SET(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) | (v)))
+#define HW_FTM_SYNC_CLR(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) & ~(v)))
+#define HW_FTM_SYNC_TOG(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_SYNC bitfields
+ */
+
+/*!
+ * @name Register FTM_SYNC, field CNTMIN[0] (RW)
+ *
+ * Selects the minimum loading point to PWM synchronization. See Boundary cycle
+ * and loading points. If CNTMIN is one, the selected loading point is when the
+ * FTM counter reaches its minimum value (CNTIN register).
+ *
+ * Values:
+ * - 0 - The minimum loading point is disabled.
+ * - 1 - The minimum loading point is enabled.
+ */
+//@{
+#define BP_FTM_SYNC_CNTMIN (0U) //!< Bit position for FTM_SYNC_CNTMIN.
+#define BM_FTM_SYNC_CNTMIN (0x00000001U) //!< Bit mask for FTM_SYNC_CNTMIN.
+#define BS_FTM_SYNC_CNTMIN (1U) //!< Bit field size in bits for FTM_SYNC_CNTMIN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNC_CNTMIN field.
+#define BR_FTM_SYNC_CNTMIN(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMIN))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNC_CNTMIN.
+#define BF_FTM_SYNC_CNTMIN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_CNTMIN), uint32_t) & BM_FTM_SYNC_CNTMIN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CNTMIN field to a new value.
+#define BW_FTM_SYNC_CNTMIN(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMIN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNC, field CNTMAX[1] (RW)
+ *
+ * Selects the maximum loading point to PWM synchronization. See Boundary cycle
+ * and loading points. If CNTMAX is 1, the selected loading point is when the FTM
+ * counter reaches its maximum value (MOD register).
+ *
+ * Values:
+ * - 0 - The maximum loading point is disabled.
+ * - 1 - The maximum loading point is enabled.
+ */
+//@{
+#define BP_FTM_SYNC_CNTMAX (1U) //!< Bit position for FTM_SYNC_CNTMAX.
+#define BM_FTM_SYNC_CNTMAX (0x00000002U) //!< Bit mask for FTM_SYNC_CNTMAX.
+#define BS_FTM_SYNC_CNTMAX (1U) //!< Bit field size in bits for FTM_SYNC_CNTMAX.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNC_CNTMAX field.
+#define BR_FTM_SYNC_CNTMAX(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMAX))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNC_CNTMAX.
+#define BF_FTM_SYNC_CNTMAX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_CNTMAX), uint32_t) & BM_FTM_SYNC_CNTMAX)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CNTMAX field to a new value.
+#define BW_FTM_SYNC_CNTMAX(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMAX) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNC, field REINIT[2] (RW)
+ *
+ * Determines if the FTM counter is reinitialized when the selected trigger for
+ * the synchronization is detected. The REINIT bit configures the synchronization
+ * when SYNCMODE is zero.
+ *
+ * Values:
+ * - 0 - FTM counter continues to count normally.
+ * - 1 - FTM counter is updated with its initial value when the selected trigger
+ * is detected.
+ */
+//@{
+#define BP_FTM_SYNC_REINIT (2U) //!< Bit position for FTM_SYNC_REINIT.
+#define BM_FTM_SYNC_REINIT (0x00000004U) //!< Bit mask for FTM_SYNC_REINIT.
+#define BS_FTM_SYNC_REINIT (1U) //!< Bit field size in bits for FTM_SYNC_REINIT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNC_REINIT field.
+#define BR_FTM_SYNC_REINIT(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_REINIT))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNC_REINIT.
+#define BF_FTM_SYNC_REINIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_REINIT), uint32_t) & BM_FTM_SYNC_REINIT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the REINIT field to a new value.
+#define BW_FTM_SYNC_REINIT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_REINIT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNC, field SYNCHOM[3] (RW)
+ *
+ * Selects when the OUTMASK register is updated with the value of its buffer.
+ *
+ * Values:
+ * - 0 - OUTMASK register is updated with the value of its buffer in all rising
+ * edges of the system clock.
+ * - 1 - OUTMASK register is updated with the value of its buffer only by the
+ * PWM synchronization.
+ */
+//@{
+#define BP_FTM_SYNC_SYNCHOM (3U) //!< Bit position for FTM_SYNC_SYNCHOM.
+#define BM_FTM_SYNC_SYNCHOM (0x00000008U) //!< Bit mask for FTM_SYNC_SYNCHOM.
+#define BS_FTM_SYNC_SYNCHOM (1U) //!< Bit field size in bits for FTM_SYNC_SYNCHOM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNC_SYNCHOM field.
+#define BR_FTM_SYNC_SYNCHOM(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SYNCHOM))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNC_SYNCHOM.
+#define BF_FTM_SYNC_SYNCHOM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_SYNCHOM), uint32_t) & BM_FTM_SYNC_SYNCHOM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SYNCHOM field to a new value.
+#define BW_FTM_SYNC_SYNCHOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SYNCHOM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNC, field TRIG0[4] (RW)
+ *
+ * Enables hardware trigger 0 to the PWM synchronization. Hardware trigger 0
+ * occurs when a rising edge is detected at the trigger 0 input signal.
+ *
+ * Values:
+ * - 0 - Trigger is disabled.
+ * - 1 - Trigger is enabled.
+ */
+//@{
+#define BP_FTM_SYNC_TRIG0 (4U) //!< Bit position for FTM_SYNC_TRIG0.
+#define BM_FTM_SYNC_TRIG0 (0x00000010U) //!< Bit mask for FTM_SYNC_TRIG0.
+#define BS_FTM_SYNC_TRIG0 (1U) //!< Bit field size in bits for FTM_SYNC_TRIG0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNC_TRIG0 field.
+#define BR_FTM_SYNC_TRIG0(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG0))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNC_TRIG0.
+#define BF_FTM_SYNC_TRIG0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_TRIG0), uint32_t) & BM_FTM_SYNC_TRIG0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TRIG0 field to a new value.
+#define BW_FTM_SYNC_TRIG0(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNC, field TRIG1[5] (RW)
+ *
+ * Enables hardware trigger 1 to the PWM synchronization. Hardware trigger 1
+ * happens when a rising edge is detected at the trigger 1 input signal.
+ *
+ * Values:
+ * - 0 - Trigger is disabled.
+ * - 1 - Trigger is enabled.
+ */
+//@{
+#define BP_FTM_SYNC_TRIG1 (5U) //!< Bit position for FTM_SYNC_TRIG1.
+#define BM_FTM_SYNC_TRIG1 (0x00000020U) //!< Bit mask for FTM_SYNC_TRIG1.
+#define BS_FTM_SYNC_TRIG1 (1U) //!< Bit field size in bits for FTM_SYNC_TRIG1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNC_TRIG1 field.
+#define BR_FTM_SYNC_TRIG1(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG1))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNC_TRIG1.
+#define BF_FTM_SYNC_TRIG1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_TRIG1), uint32_t) & BM_FTM_SYNC_TRIG1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TRIG1 field to a new value.
+#define BW_FTM_SYNC_TRIG1(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNC, field TRIG2[6] (RW)
+ *
+ * Enables hardware trigger 2 to the PWM synchronization. Hardware trigger 2
+ * happens when a rising edge is detected at the trigger 2 input signal.
+ *
+ * Values:
+ * - 0 - Trigger is disabled.
+ * - 1 - Trigger is enabled.
+ */
+//@{
+#define BP_FTM_SYNC_TRIG2 (6U) //!< Bit position for FTM_SYNC_TRIG2.
+#define BM_FTM_SYNC_TRIG2 (0x00000040U) //!< Bit mask for FTM_SYNC_TRIG2.
+#define BS_FTM_SYNC_TRIG2 (1U) //!< Bit field size in bits for FTM_SYNC_TRIG2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNC_TRIG2 field.
+#define BR_FTM_SYNC_TRIG2(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG2))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNC_TRIG2.
+#define BF_FTM_SYNC_TRIG2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_TRIG2), uint32_t) & BM_FTM_SYNC_TRIG2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TRIG2 field to a new value.
+#define BW_FTM_SYNC_TRIG2(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNC, field SWSYNC[7] (RW)
+ *
+ * Selects the software trigger as the PWM synchronization trigger. The software
+ * trigger happens when a 1 is written to SWSYNC bit.
+ *
+ * Values:
+ * - 0 - Software trigger is not selected.
+ * - 1 - Software trigger is selected.
+ */
+//@{
+#define BP_FTM_SYNC_SWSYNC (7U) //!< Bit position for FTM_SYNC_SWSYNC.
+#define BM_FTM_SYNC_SWSYNC (0x00000080U) //!< Bit mask for FTM_SYNC_SWSYNC.
+#define BS_FTM_SYNC_SWSYNC (1U) //!< Bit field size in bits for FTM_SYNC_SWSYNC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNC_SWSYNC field.
+#define BR_FTM_SYNC_SWSYNC(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SWSYNC))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNC_SWSYNC.
+#define BF_FTM_SYNC_SWSYNC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNC_SWSYNC), uint32_t) & BM_FTM_SYNC_SWSYNC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SWSYNC field to a new value.
+#define BW_FTM_SYNC_SWSYNC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SWSYNC) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_OUTINIT - Initial State For Channels Output
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_OUTINIT - Initial State For Channels Output (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_ftm_outinit
+{
+ uint32_t U;
+ struct _hw_ftm_outinit_bitfields
+ {
+ uint32_t CH0OI : 1; //!< [0] Channel 0 Output Initialization Value
+ uint32_t CH1OI : 1; //!< [1] Channel 1 Output Initialization Value
+ uint32_t CH2OI : 1; //!< [2] Channel 2 Output Initialization Value
+ uint32_t CH3OI : 1; //!< [3] Channel 3 Output Initialization Value
+ uint32_t CH4OI : 1; //!< [4] Channel 4 Output Initialization Value
+ uint32_t CH5OI : 1; //!< [5] Channel 5 Output Initialization Value
+ uint32_t CH6OI : 1; //!< [6] Channel 6 Output Initialization Value
+ uint32_t CH7OI : 1; //!< [7] Channel 7 Output Initialization Value
+ uint32_t RESERVED0 : 24; //!< [31:8]
+ } B;
+} hw_ftm_outinit_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_OUTINIT register
+ */
+//@{
+#define HW_FTM_OUTINIT_ADDR(x) (REGS_FTM_BASE(x) + 0x5CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_OUTINIT(x) (*(__IO hw_ftm_outinit_t *) HW_FTM_OUTINIT_ADDR(x))
+#define HW_FTM_OUTINIT_RD(x) (HW_FTM_OUTINIT(x).U)
+#define HW_FTM_OUTINIT_WR(x, v) (HW_FTM_OUTINIT(x).U = (v))
+#define HW_FTM_OUTINIT_SET(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) | (v)))
+#define HW_FTM_OUTINIT_CLR(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) & ~(v)))
+#define HW_FTM_OUTINIT_TOG(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_OUTINIT bitfields
+ */
+
+/*!
+ * @name Register FTM_OUTINIT, field CH0OI[0] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0 - The initialization value is 0.
+ * - 1 - The initialization value is 1.
+ */
+//@{
+#define BP_FTM_OUTINIT_CH0OI (0U) //!< Bit position for FTM_OUTINIT_CH0OI.
+#define BM_FTM_OUTINIT_CH0OI (0x00000001U) //!< Bit mask for FTM_OUTINIT_CH0OI.
+#define BS_FTM_OUTINIT_CH0OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH0OI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTINIT_CH0OI field.
+#define BR_FTM_OUTINIT_CH0OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH0OI))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTINIT_CH0OI.
+#define BF_FTM_OUTINIT_CH0OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH0OI), uint32_t) & BM_FTM_OUTINIT_CH0OI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH0OI field to a new value.
+#define BW_FTM_OUTINIT_CH0OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH0OI) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_OUTINIT, field CH1OI[1] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0 - The initialization value is 0.
+ * - 1 - The initialization value is 1.
+ */
+//@{
+#define BP_FTM_OUTINIT_CH1OI (1U) //!< Bit position for FTM_OUTINIT_CH1OI.
+#define BM_FTM_OUTINIT_CH1OI (0x00000002U) //!< Bit mask for FTM_OUTINIT_CH1OI.
+#define BS_FTM_OUTINIT_CH1OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH1OI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTINIT_CH1OI field.
+#define BR_FTM_OUTINIT_CH1OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH1OI))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTINIT_CH1OI.
+#define BF_FTM_OUTINIT_CH1OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH1OI), uint32_t) & BM_FTM_OUTINIT_CH1OI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH1OI field to a new value.
+#define BW_FTM_OUTINIT_CH1OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH1OI) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_OUTINIT, field CH2OI[2] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0 - The initialization value is 0.
+ * - 1 - The initialization value is 1.
+ */
+//@{
+#define BP_FTM_OUTINIT_CH2OI (2U) //!< Bit position for FTM_OUTINIT_CH2OI.
+#define BM_FTM_OUTINIT_CH2OI (0x00000004U) //!< Bit mask for FTM_OUTINIT_CH2OI.
+#define BS_FTM_OUTINIT_CH2OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH2OI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTINIT_CH2OI field.
+#define BR_FTM_OUTINIT_CH2OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH2OI))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTINIT_CH2OI.
+#define BF_FTM_OUTINIT_CH2OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH2OI), uint32_t) & BM_FTM_OUTINIT_CH2OI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH2OI field to a new value.
+#define BW_FTM_OUTINIT_CH2OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH2OI) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_OUTINIT, field CH3OI[3] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0 - The initialization value is 0.
+ * - 1 - The initialization value is 1.
+ */
+//@{
+#define BP_FTM_OUTINIT_CH3OI (3U) //!< Bit position for FTM_OUTINIT_CH3OI.
+#define BM_FTM_OUTINIT_CH3OI (0x00000008U) //!< Bit mask for FTM_OUTINIT_CH3OI.
+#define BS_FTM_OUTINIT_CH3OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH3OI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTINIT_CH3OI field.
+#define BR_FTM_OUTINIT_CH3OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH3OI))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTINIT_CH3OI.
+#define BF_FTM_OUTINIT_CH3OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH3OI), uint32_t) & BM_FTM_OUTINIT_CH3OI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH3OI field to a new value.
+#define BW_FTM_OUTINIT_CH3OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH3OI) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_OUTINIT, field CH4OI[4] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0 - The initialization value is 0.
+ * - 1 - The initialization value is 1.
+ */
+//@{
+#define BP_FTM_OUTINIT_CH4OI (4U) //!< Bit position for FTM_OUTINIT_CH4OI.
+#define BM_FTM_OUTINIT_CH4OI (0x00000010U) //!< Bit mask for FTM_OUTINIT_CH4OI.
+#define BS_FTM_OUTINIT_CH4OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH4OI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTINIT_CH4OI field.
+#define BR_FTM_OUTINIT_CH4OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH4OI))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTINIT_CH4OI.
+#define BF_FTM_OUTINIT_CH4OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH4OI), uint32_t) & BM_FTM_OUTINIT_CH4OI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH4OI field to a new value.
+#define BW_FTM_OUTINIT_CH4OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH4OI) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_OUTINIT, field CH5OI[5] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0 - The initialization value is 0.
+ * - 1 - The initialization value is 1.
+ */
+//@{
+#define BP_FTM_OUTINIT_CH5OI (5U) //!< Bit position for FTM_OUTINIT_CH5OI.
+#define BM_FTM_OUTINIT_CH5OI (0x00000020U) //!< Bit mask for FTM_OUTINIT_CH5OI.
+#define BS_FTM_OUTINIT_CH5OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH5OI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTINIT_CH5OI field.
+#define BR_FTM_OUTINIT_CH5OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH5OI))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTINIT_CH5OI.
+#define BF_FTM_OUTINIT_CH5OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH5OI), uint32_t) & BM_FTM_OUTINIT_CH5OI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH5OI field to a new value.
+#define BW_FTM_OUTINIT_CH5OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH5OI) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_OUTINIT, field CH6OI[6] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0 - The initialization value is 0.
+ * - 1 - The initialization value is 1.
+ */
+//@{
+#define BP_FTM_OUTINIT_CH6OI (6U) //!< Bit position for FTM_OUTINIT_CH6OI.
+#define BM_FTM_OUTINIT_CH6OI (0x00000040U) //!< Bit mask for FTM_OUTINIT_CH6OI.
+#define BS_FTM_OUTINIT_CH6OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH6OI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTINIT_CH6OI field.
+#define BR_FTM_OUTINIT_CH6OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH6OI))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTINIT_CH6OI.
+#define BF_FTM_OUTINIT_CH6OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH6OI), uint32_t) & BM_FTM_OUTINIT_CH6OI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH6OI field to a new value.
+#define BW_FTM_OUTINIT_CH6OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH6OI) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_OUTINIT, field CH7OI[7] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0 - The initialization value is 0.
+ * - 1 - The initialization value is 1.
+ */
+//@{
+#define BP_FTM_OUTINIT_CH7OI (7U) //!< Bit position for FTM_OUTINIT_CH7OI.
+#define BM_FTM_OUTINIT_CH7OI (0x00000080U) //!< Bit mask for FTM_OUTINIT_CH7OI.
+#define BS_FTM_OUTINIT_CH7OI (1U) //!< Bit field size in bits for FTM_OUTINIT_CH7OI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTINIT_CH7OI field.
+#define BR_FTM_OUTINIT_CH7OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH7OI))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTINIT_CH7OI.
+#define BF_FTM_OUTINIT_CH7OI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTINIT_CH7OI), uint32_t) & BM_FTM_OUTINIT_CH7OI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH7OI field to a new value.
+#define BW_FTM_OUTINIT_CH7OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH7OI) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_OUTMASK - Output Mask
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_OUTMASK - Output Mask (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register provides a mask for each FTM channel. The mask of a channel
+ * determines if its output responds, that is, it is masked or not, when a match
+ * occurs. This feature is used for BLDC control where the PWM signal is presented
+ * to an electric motor at specific times to provide electronic commutation. Any
+ * write to the OUTMASK register, stores the value in its write buffer. The
+ * register is updated with the value of its write buffer according to PWM
+ * synchronization.
+ */
+typedef union _hw_ftm_outmask
+{
+ uint32_t U;
+ struct _hw_ftm_outmask_bitfields
+ {
+ uint32_t CH0OM : 1; //!< [0] Channel 0 Output Mask
+ uint32_t CH1OM : 1; //!< [1] Channel 1 Output Mask
+ uint32_t CH2OM : 1; //!< [2] Channel 2 Output Mask
+ uint32_t CH3OM : 1; //!< [3] Channel 3 Output Mask
+ uint32_t CH4OM : 1; //!< [4] Channel 4 Output Mask
+ uint32_t CH5OM : 1; //!< [5] Channel 5 Output Mask
+ uint32_t CH6OM : 1; //!< [6] Channel 6 Output Mask
+ uint32_t CH7OM : 1; //!< [7] Channel 7 Output Mask
+ uint32_t RESERVED0 : 24; //!< [31:8]
+ } B;
+} hw_ftm_outmask_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_OUTMASK register
+ */
+//@{
+#define HW_FTM_OUTMASK_ADDR(x) (REGS_FTM_BASE(x) + 0x60U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_OUTMASK(x) (*(__IO hw_ftm_outmask_t *) HW_FTM_OUTMASK_ADDR(x))
+#define HW_FTM_OUTMASK_RD(x) (HW_FTM_OUTMASK(x).U)
+#define HW_FTM_OUTMASK_WR(x, v) (HW_FTM_OUTMASK(x).U = (v))
+#define HW_FTM_OUTMASK_SET(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) | (v)))
+#define HW_FTM_OUTMASK_CLR(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) & ~(v)))
+#define HW_FTM_OUTMASK_TOG(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_OUTMASK bitfields
+ */
+
+/*!
+ * @name Register FTM_OUTMASK, field CH0OM[0] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0 - Channel output is not masked. It continues to operate normally.
+ * - 1 - Channel output is masked. It is forced to its inactive state.
+ */
+//@{
+#define BP_FTM_OUTMASK_CH0OM (0U) //!< Bit position for FTM_OUTMASK_CH0OM.
+#define BM_FTM_OUTMASK_CH0OM (0x00000001U) //!< Bit mask for FTM_OUTMASK_CH0OM.
+#define BS_FTM_OUTMASK_CH0OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH0OM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTMASK_CH0OM field.
+#define BR_FTM_OUTMASK_CH0OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH0OM))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTMASK_CH0OM.
+#define BF_FTM_OUTMASK_CH0OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH0OM), uint32_t) & BM_FTM_OUTMASK_CH0OM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH0OM field to a new value.
+#define BW_FTM_OUTMASK_CH0OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH0OM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_OUTMASK, field CH1OM[1] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0 - Channel output is not masked. It continues to operate normally.
+ * - 1 - Channel output is masked. It is forced to its inactive state.
+ */
+//@{
+#define BP_FTM_OUTMASK_CH1OM (1U) //!< Bit position for FTM_OUTMASK_CH1OM.
+#define BM_FTM_OUTMASK_CH1OM (0x00000002U) //!< Bit mask for FTM_OUTMASK_CH1OM.
+#define BS_FTM_OUTMASK_CH1OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH1OM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTMASK_CH1OM field.
+#define BR_FTM_OUTMASK_CH1OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH1OM))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTMASK_CH1OM.
+#define BF_FTM_OUTMASK_CH1OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH1OM), uint32_t) & BM_FTM_OUTMASK_CH1OM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH1OM field to a new value.
+#define BW_FTM_OUTMASK_CH1OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH1OM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_OUTMASK, field CH2OM[2] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0 - Channel output is not masked. It continues to operate normally.
+ * - 1 - Channel output is masked. It is forced to its inactive state.
+ */
+//@{
+#define BP_FTM_OUTMASK_CH2OM (2U) //!< Bit position for FTM_OUTMASK_CH2OM.
+#define BM_FTM_OUTMASK_CH2OM (0x00000004U) //!< Bit mask for FTM_OUTMASK_CH2OM.
+#define BS_FTM_OUTMASK_CH2OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH2OM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTMASK_CH2OM field.
+#define BR_FTM_OUTMASK_CH2OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH2OM))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTMASK_CH2OM.
+#define BF_FTM_OUTMASK_CH2OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH2OM), uint32_t) & BM_FTM_OUTMASK_CH2OM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH2OM field to a new value.
+#define BW_FTM_OUTMASK_CH2OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH2OM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_OUTMASK, field CH3OM[3] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0 - Channel output is not masked. It continues to operate normally.
+ * - 1 - Channel output is masked. It is forced to its inactive state.
+ */
+//@{
+#define BP_FTM_OUTMASK_CH3OM (3U) //!< Bit position for FTM_OUTMASK_CH3OM.
+#define BM_FTM_OUTMASK_CH3OM (0x00000008U) //!< Bit mask for FTM_OUTMASK_CH3OM.
+#define BS_FTM_OUTMASK_CH3OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH3OM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTMASK_CH3OM field.
+#define BR_FTM_OUTMASK_CH3OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH3OM))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTMASK_CH3OM.
+#define BF_FTM_OUTMASK_CH3OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH3OM), uint32_t) & BM_FTM_OUTMASK_CH3OM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH3OM field to a new value.
+#define BW_FTM_OUTMASK_CH3OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH3OM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_OUTMASK, field CH4OM[4] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0 - Channel output is not masked. It continues to operate normally.
+ * - 1 - Channel output is masked. It is forced to its inactive state.
+ */
+//@{
+#define BP_FTM_OUTMASK_CH4OM (4U) //!< Bit position for FTM_OUTMASK_CH4OM.
+#define BM_FTM_OUTMASK_CH4OM (0x00000010U) //!< Bit mask for FTM_OUTMASK_CH4OM.
+#define BS_FTM_OUTMASK_CH4OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH4OM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTMASK_CH4OM field.
+#define BR_FTM_OUTMASK_CH4OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH4OM))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTMASK_CH4OM.
+#define BF_FTM_OUTMASK_CH4OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH4OM), uint32_t) & BM_FTM_OUTMASK_CH4OM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH4OM field to a new value.
+#define BW_FTM_OUTMASK_CH4OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH4OM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_OUTMASK, field CH5OM[5] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0 - Channel output is not masked. It continues to operate normally.
+ * - 1 - Channel output is masked. It is forced to its inactive state.
+ */
+//@{
+#define BP_FTM_OUTMASK_CH5OM (5U) //!< Bit position for FTM_OUTMASK_CH5OM.
+#define BM_FTM_OUTMASK_CH5OM (0x00000020U) //!< Bit mask for FTM_OUTMASK_CH5OM.
+#define BS_FTM_OUTMASK_CH5OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH5OM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTMASK_CH5OM field.
+#define BR_FTM_OUTMASK_CH5OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH5OM))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTMASK_CH5OM.
+#define BF_FTM_OUTMASK_CH5OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH5OM), uint32_t) & BM_FTM_OUTMASK_CH5OM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH5OM field to a new value.
+#define BW_FTM_OUTMASK_CH5OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH5OM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_OUTMASK, field CH6OM[6] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0 - Channel output is not masked. It continues to operate normally.
+ * - 1 - Channel output is masked. It is forced to its inactive state.
+ */
+//@{
+#define BP_FTM_OUTMASK_CH6OM (6U) //!< Bit position for FTM_OUTMASK_CH6OM.
+#define BM_FTM_OUTMASK_CH6OM (0x00000040U) //!< Bit mask for FTM_OUTMASK_CH6OM.
+#define BS_FTM_OUTMASK_CH6OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH6OM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTMASK_CH6OM field.
+#define BR_FTM_OUTMASK_CH6OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH6OM))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTMASK_CH6OM.
+#define BF_FTM_OUTMASK_CH6OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH6OM), uint32_t) & BM_FTM_OUTMASK_CH6OM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH6OM field to a new value.
+#define BW_FTM_OUTMASK_CH6OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH6OM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_OUTMASK, field CH7OM[7] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0 - Channel output is not masked. It continues to operate normally.
+ * - 1 - Channel output is masked. It is forced to its inactive state.
+ */
+//@{
+#define BP_FTM_OUTMASK_CH7OM (7U) //!< Bit position for FTM_OUTMASK_CH7OM.
+#define BM_FTM_OUTMASK_CH7OM (0x00000080U) //!< Bit mask for FTM_OUTMASK_CH7OM.
+#define BS_FTM_OUTMASK_CH7OM (1U) //!< Bit field size in bits for FTM_OUTMASK_CH7OM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_OUTMASK_CH7OM field.
+#define BR_FTM_OUTMASK_CH7OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH7OM))
+#endif
+
+//! @brief Format value for bitfield FTM_OUTMASK_CH7OM.
+#define BF_FTM_OUTMASK_CH7OM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_OUTMASK_CH7OM), uint32_t) & BM_FTM_OUTMASK_CH7OM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH7OM field to a new value.
+#define BW_FTM_OUTMASK_CH7OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH7OM) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_COMBINE - Function For Linked Channels
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_COMBINE - Function For Linked Channels (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the control bits used to configure the fault control,
+ * synchronization, deadtime insertion, Dual Edge Capture mode, Complementary,
+ * and Combine mode for each pair of channels (n) and (n+1), where n equals 0, 2,
+ * 4, and 6.
+ */
+typedef union _hw_ftm_combine
+{
+ uint32_t U;
+ struct _hw_ftm_combine_bitfields
+ {
+ uint32_t COMBINE0 : 1; //!< [0] Combine Channels For n = 0
+ uint32_t COMP0 : 1; //!< [1] Complement Of Channel (n) For n = 0
+ uint32_t DECAPEN0 : 1; //!< [2] Dual Edge Capture Mode Enable For n =
+ //! 0
+ uint32_t DECAP0 : 1; //!< [3] Dual Edge Capture Mode Captures For n =
+ //! 0
+ uint32_t DTEN0 : 1; //!< [4] Deadtime Enable For n = 0
+ uint32_t SYNCEN0 : 1; //!< [5] Synchronization Enable For n = 0
+ uint32_t FAULTEN0 : 1; //!< [6] Fault Control Enable For n = 0
+ uint32_t RESERVED0 : 1; //!< [7]
+ uint32_t COMBINE1 : 1; //!< [8] Combine Channels For n = 2
+ uint32_t COMP1 : 1; //!< [9] Complement Of Channel (n) For n = 2
+ uint32_t DECAPEN1 : 1; //!< [10] Dual Edge Capture Mode Enable For n
+ //! = 2
+ uint32_t DECAP1 : 1; //!< [11] Dual Edge Capture Mode Captures For n
+ //! = 2
+ uint32_t DTEN1 : 1; //!< [12] Deadtime Enable For n = 2
+ uint32_t SYNCEN1 : 1; //!< [13] Synchronization Enable For n = 2
+ uint32_t FAULTEN1 : 1; //!< [14] Fault Control Enable For n = 2
+ uint32_t RESERVED1 : 1; //!< [15]
+ uint32_t COMBINE2 : 1; //!< [16] Combine Channels For n = 4
+ uint32_t COMP2 : 1; //!< [17] Complement Of Channel (n) For n = 4
+ uint32_t DECAPEN2 : 1; //!< [18] Dual Edge Capture Mode Enable For n
+ //! = 4
+ uint32_t DECAP2 : 1; //!< [19] Dual Edge Capture Mode Captures For n
+ //! = 4
+ uint32_t DTEN2 : 1; //!< [20] Deadtime Enable For n = 4
+ uint32_t SYNCEN2 : 1; //!< [21] Synchronization Enable For n = 4
+ uint32_t FAULTEN2 : 1; //!< [22] Fault Control Enable For n = 4
+ uint32_t RESERVED2 : 1; //!< [23]
+ uint32_t COMBINE3 : 1; //!< [24] Combine Channels For n = 6
+ uint32_t COMP3 : 1; //!< [25] Complement Of Channel (n) for n = 6
+ uint32_t DECAPEN3 : 1; //!< [26] Dual Edge Capture Mode Enable For n
+ //! = 6
+ uint32_t DECAP3 : 1; //!< [27] Dual Edge Capture Mode Captures For n
+ //! = 6
+ uint32_t DTEN3 : 1; //!< [28] Deadtime Enable For n = 6
+ uint32_t SYNCEN3 : 1; //!< [29] Synchronization Enable For n = 6
+ uint32_t FAULTEN3 : 1; //!< [30] Fault Control Enable For n = 6
+ uint32_t RESERVED3 : 1; //!< [31]
+ } B;
+} hw_ftm_combine_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_COMBINE register
+ */
+//@{
+#define HW_FTM_COMBINE_ADDR(x) (REGS_FTM_BASE(x) + 0x64U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_COMBINE(x) (*(__IO hw_ftm_combine_t *) HW_FTM_COMBINE_ADDR(x))
+#define HW_FTM_COMBINE_RD(x) (HW_FTM_COMBINE(x).U)
+#define HW_FTM_COMBINE_WR(x, v) (HW_FTM_COMBINE(x).U = (v))
+#define HW_FTM_COMBINE_SET(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) | (v)))
+#define HW_FTM_COMBINE_CLR(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) & ~(v)))
+#define HW_FTM_COMBINE_TOG(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_COMBINE bitfields
+ */
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE0[0] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Channels (n) and (n+1) are independent.
+ * - 1 - Channels (n) and (n+1) are combined.
+ */
+//@{
+#define BP_FTM_COMBINE_COMBINE0 (0U) //!< Bit position for FTM_COMBINE_COMBINE0.
+#define BM_FTM_COMBINE_COMBINE0 (0x00000001U) //!< Bit mask for FTM_COMBINE_COMBINE0.
+#define BS_FTM_COMBINE_COMBINE0 (1U) //!< Bit field size in bits for FTM_COMBINE_COMBINE0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_COMBINE0 field.
+#define BR_FTM_COMBINE_COMBINE0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE0))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_COMBINE0.
+#define BF_FTM_COMBINE_COMBINE0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMBINE0), uint32_t) & BM_FTM_COMBINE_COMBINE0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COMBINE0 field to a new value.
+#define BW_FTM_COMBINE_COMBINE0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field COMP0[1] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+//@{
+#define BP_FTM_COMBINE_COMP0 (1U) //!< Bit position for FTM_COMBINE_COMP0.
+#define BM_FTM_COMBINE_COMP0 (0x00000002U) //!< Bit mask for FTM_COMBINE_COMP0.
+#define BS_FTM_COMBINE_COMP0 (1U) //!< Bit field size in bits for FTM_COMBINE_COMP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_COMP0 field.
+#define BR_FTM_COMBINE_COMP0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP0))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_COMP0.
+#define BF_FTM_COMBINE_COMP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMP0), uint32_t) & BM_FTM_COMBINE_COMP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COMP0 field to a new value.
+#define BW_FTM_COMBINE_COMP0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN0[2] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_DECAPEN0 (2U) //!< Bit position for FTM_COMBINE_DECAPEN0.
+#define BM_FTM_COMBINE_DECAPEN0 (0x00000004U) //!< Bit mask for FTM_COMBINE_DECAPEN0.
+#define BS_FTM_COMBINE_DECAPEN0 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAPEN0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_DECAPEN0 field.
+#define BR_FTM_COMBINE_DECAPEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN0))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_DECAPEN0.
+#define BF_FTM_COMBINE_DECAPEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAPEN0), uint32_t) & BM_FTM_COMBINE_DECAPEN0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DECAPEN0 field to a new value.
+#define BW_FTM_COMBINE_DECAPEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP0[3] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if dual edge capture - one-shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0 - The dual edge captures are inactive.
+ * - 1 - The dual edge captures are active.
+ */
+//@{
+#define BP_FTM_COMBINE_DECAP0 (3U) //!< Bit position for FTM_COMBINE_DECAP0.
+#define BM_FTM_COMBINE_DECAP0 (0x00000008U) //!< Bit mask for FTM_COMBINE_DECAP0.
+#define BS_FTM_COMBINE_DECAP0 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_DECAP0 field.
+#define BR_FTM_COMBINE_DECAP0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP0))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_DECAP0.
+#define BF_FTM_COMBINE_DECAP0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAP0), uint32_t) & BM_FTM_COMBINE_DECAP0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DECAP0 field to a new value.
+#define BW_FTM_COMBINE_DECAP0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN0[4] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The deadtime insertion in this pair of channels is disabled.
+ * - 1 - The deadtime insertion in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_DTEN0 (4U) //!< Bit position for FTM_COMBINE_DTEN0.
+#define BM_FTM_COMBINE_DTEN0 (0x00000010U) //!< Bit mask for FTM_COMBINE_DTEN0.
+#define BS_FTM_COMBINE_DTEN0 (1U) //!< Bit field size in bits for FTM_COMBINE_DTEN0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_DTEN0 field.
+#define BR_FTM_COMBINE_DTEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN0))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_DTEN0.
+#define BF_FTM_COMBINE_DTEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DTEN0), uint32_t) & BM_FTM_COMBINE_DTEN0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DTEN0 field to a new value.
+#define BW_FTM_COMBINE_DTEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN0[5] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0 - The PWM synchronization in this pair of channels is disabled.
+ * - 1 - The PWM synchronization in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_SYNCEN0 (5U) //!< Bit position for FTM_COMBINE_SYNCEN0.
+#define BM_FTM_COMBINE_SYNCEN0 (0x00000020U) //!< Bit mask for FTM_COMBINE_SYNCEN0.
+#define BS_FTM_COMBINE_SYNCEN0 (1U) //!< Bit field size in bits for FTM_COMBINE_SYNCEN0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_SYNCEN0 field.
+#define BR_FTM_COMBINE_SYNCEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN0))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_SYNCEN0.
+#define BF_FTM_COMBINE_SYNCEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_SYNCEN0), uint32_t) & BM_FTM_COMBINE_SYNCEN0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SYNCEN0 field to a new value.
+#define BW_FTM_COMBINE_SYNCEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN0[6] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The fault control in this pair of channels is disabled.
+ * - 1 - The fault control in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_FAULTEN0 (6U) //!< Bit position for FTM_COMBINE_FAULTEN0.
+#define BM_FTM_COMBINE_FAULTEN0 (0x00000040U) //!< Bit mask for FTM_COMBINE_FAULTEN0.
+#define BS_FTM_COMBINE_FAULTEN0 (1U) //!< Bit field size in bits for FTM_COMBINE_FAULTEN0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_FAULTEN0 field.
+#define BR_FTM_COMBINE_FAULTEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN0))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_FAULTEN0.
+#define BF_FTM_COMBINE_FAULTEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_FAULTEN0), uint32_t) & BM_FTM_COMBINE_FAULTEN0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FAULTEN0 field to a new value.
+#define BW_FTM_COMBINE_FAULTEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE1[8] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Channels (n) and (n+1) are independent.
+ * - 1 - Channels (n) and (n+1) are combined.
+ */
+//@{
+#define BP_FTM_COMBINE_COMBINE1 (8U) //!< Bit position for FTM_COMBINE_COMBINE1.
+#define BM_FTM_COMBINE_COMBINE1 (0x00000100U) //!< Bit mask for FTM_COMBINE_COMBINE1.
+#define BS_FTM_COMBINE_COMBINE1 (1U) //!< Bit field size in bits for FTM_COMBINE_COMBINE1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_COMBINE1 field.
+#define BR_FTM_COMBINE_COMBINE1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE1))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_COMBINE1.
+#define BF_FTM_COMBINE_COMBINE1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMBINE1), uint32_t) & BM_FTM_COMBINE_COMBINE1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COMBINE1 field to a new value.
+#define BW_FTM_COMBINE_COMBINE1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field COMP1[9] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+//@{
+#define BP_FTM_COMBINE_COMP1 (9U) //!< Bit position for FTM_COMBINE_COMP1.
+#define BM_FTM_COMBINE_COMP1 (0x00000200U) //!< Bit mask for FTM_COMBINE_COMP1.
+#define BS_FTM_COMBINE_COMP1 (1U) //!< Bit field size in bits for FTM_COMBINE_COMP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_COMP1 field.
+#define BR_FTM_COMBINE_COMP1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP1))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_COMP1.
+#define BF_FTM_COMBINE_COMP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMP1), uint32_t) & BM_FTM_COMBINE_COMP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COMP1 field to a new value.
+#define BW_FTM_COMBINE_COMP1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN1[10] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_DECAPEN1 (10U) //!< Bit position for FTM_COMBINE_DECAPEN1.
+#define BM_FTM_COMBINE_DECAPEN1 (0x00000400U) //!< Bit mask for FTM_COMBINE_DECAPEN1.
+#define BS_FTM_COMBINE_DECAPEN1 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAPEN1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_DECAPEN1 field.
+#define BR_FTM_COMBINE_DECAPEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN1))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_DECAPEN1.
+#define BF_FTM_COMBINE_DECAPEN1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAPEN1), uint32_t) & BM_FTM_COMBINE_DECAPEN1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DECAPEN1 field to a new value.
+#define BW_FTM_COMBINE_DECAPEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP1[11] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if Dual Edge Capture - One-Shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0 - The dual edge captures are inactive.
+ * - 1 - The dual edge captures are active.
+ */
+//@{
+#define BP_FTM_COMBINE_DECAP1 (11U) //!< Bit position for FTM_COMBINE_DECAP1.
+#define BM_FTM_COMBINE_DECAP1 (0x00000800U) //!< Bit mask for FTM_COMBINE_DECAP1.
+#define BS_FTM_COMBINE_DECAP1 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_DECAP1 field.
+#define BR_FTM_COMBINE_DECAP1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP1))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_DECAP1.
+#define BF_FTM_COMBINE_DECAP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAP1), uint32_t) & BM_FTM_COMBINE_DECAP1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DECAP1 field to a new value.
+#define BW_FTM_COMBINE_DECAP1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN1[12] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The deadtime insertion in this pair of channels is disabled.
+ * - 1 - The deadtime insertion in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_DTEN1 (12U) //!< Bit position for FTM_COMBINE_DTEN1.
+#define BM_FTM_COMBINE_DTEN1 (0x00001000U) //!< Bit mask for FTM_COMBINE_DTEN1.
+#define BS_FTM_COMBINE_DTEN1 (1U) //!< Bit field size in bits for FTM_COMBINE_DTEN1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_DTEN1 field.
+#define BR_FTM_COMBINE_DTEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN1))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_DTEN1.
+#define BF_FTM_COMBINE_DTEN1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DTEN1), uint32_t) & BM_FTM_COMBINE_DTEN1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DTEN1 field to a new value.
+#define BW_FTM_COMBINE_DTEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN1[13] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0 - The PWM synchronization in this pair of channels is disabled.
+ * - 1 - The PWM synchronization in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_SYNCEN1 (13U) //!< Bit position for FTM_COMBINE_SYNCEN1.
+#define BM_FTM_COMBINE_SYNCEN1 (0x00002000U) //!< Bit mask for FTM_COMBINE_SYNCEN1.
+#define BS_FTM_COMBINE_SYNCEN1 (1U) //!< Bit field size in bits for FTM_COMBINE_SYNCEN1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_SYNCEN1 field.
+#define BR_FTM_COMBINE_SYNCEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN1))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_SYNCEN1.
+#define BF_FTM_COMBINE_SYNCEN1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_SYNCEN1), uint32_t) & BM_FTM_COMBINE_SYNCEN1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SYNCEN1 field to a new value.
+#define BW_FTM_COMBINE_SYNCEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN1[14] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The fault control in this pair of channels is disabled.
+ * - 1 - The fault control in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_FAULTEN1 (14U) //!< Bit position for FTM_COMBINE_FAULTEN1.
+#define BM_FTM_COMBINE_FAULTEN1 (0x00004000U) //!< Bit mask for FTM_COMBINE_FAULTEN1.
+#define BS_FTM_COMBINE_FAULTEN1 (1U) //!< Bit field size in bits for FTM_COMBINE_FAULTEN1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_FAULTEN1 field.
+#define BR_FTM_COMBINE_FAULTEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN1))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_FAULTEN1.
+#define BF_FTM_COMBINE_FAULTEN1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_FAULTEN1), uint32_t) & BM_FTM_COMBINE_FAULTEN1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FAULTEN1 field to a new value.
+#define BW_FTM_COMBINE_FAULTEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE2[16] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Channels (n) and (n+1) are independent.
+ * - 1 - Channels (n) and (n+1) are combined.
+ */
+//@{
+#define BP_FTM_COMBINE_COMBINE2 (16U) //!< Bit position for FTM_COMBINE_COMBINE2.
+#define BM_FTM_COMBINE_COMBINE2 (0x00010000U) //!< Bit mask for FTM_COMBINE_COMBINE2.
+#define BS_FTM_COMBINE_COMBINE2 (1U) //!< Bit field size in bits for FTM_COMBINE_COMBINE2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_COMBINE2 field.
+#define BR_FTM_COMBINE_COMBINE2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE2))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_COMBINE2.
+#define BF_FTM_COMBINE_COMBINE2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMBINE2), uint32_t) & BM_FTM_COMBINE_COMBINE2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COMBINE2 field to a new value.
+#define BW_FTM_COMBINE_COMBINE2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field COMP2[17] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+//@{
+#define BP_FTM_COMBINE_COMP2 (17U) //!< Bit position for FTM_COMBINE_COMP2.
+#define BM_FTM_COMBINE_COMP2 (0x00020000U) //!< Bit mask for FTM_COMBINE_COMP2.
+#define BS_FTM_COMBINE_COMP2 (1U) //!< Bit field size in bits for FTM_COMBINE_COMP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_COMP2 field.
+#define BR_FTM_COMBINE_COMP2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP2))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_COMP2.
+#define BF_FTM_COMBINE_COMP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMP2), uint32_t) & BM_FTM_COMBINE_COMP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COMP2 field to a new value.
+#define BW_FTM_COMBINE_COMP2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN2[18] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_DECAPEN2 (18U) //!< Bit position for FTM_COMBINE_DECAPEN2.
+#define BM_FTM_COMBINE_DECAPEN2 (0x00040000U) //!< Bit mask for FTM_COMBINE_DECAPEN2.
+#define BS_FTM_COMBINE_DECAPEN2 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAPEN2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_DECAPEN2 field.
+#define BR_FTM_COMBINE_DECAPEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN2))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_DECAPEN2.
+#define BF_FTM_COMBINE_DECAPEN2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAPEN2), uint32_t) & BM_FTM_COMBINE_DECAPEN2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DECAPEN2 field to a new value.
+#define BW_FTM_COMBINE_DECAPEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP2[19] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if dual edge capture - one-shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0 - The dual edge captures are inactive.
+ * - 1 - The dual edge captures are active.
+ */
+//@{
+#define BP_FTM_COMBINE_DECAP2 (19U) //!< Bit position for FTM_COMBINE_DECAP2.
+#define BM_FTM_COMBINE_DECAP2 (0x00080000U) //!< Bit mask for FTM_COMBINE_DECAP2.
+#define BS_FTM_COMBINE_DECAP2 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_DECAP2 field.
+#define BR_FTM_COMBINE_DECAP2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP2))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_DECAP2.
+#define BF_FTM_COMBINE_DECAP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAP2), uint32_t) & BM_FTM_COMBINE_DECAP2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DECAP2 field to a new value.
+#define BW_FTM_COMBINE_DECAP2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN2[20] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The deadtime insertion in this pair of channels is disabled.
+ * - 1 - The deadtime insertion in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_DTEN2 (20U) //!< Bit position for FTM_COMBINE_DTEN2.
+#define BM_FTM_COMBINE_DTEN2 (0x00100000U) //!< Bit mask for FTM_COMBINE_DTEN2.
+#define BS_FTM_COMBINE_DTEN2 (1U) //!< Bit field size in bits for FTM_COMBINE_DTEN2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_DTEN2 field.
+#define BR_FTM_COMBINE_DTEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN2))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_DTEN2.
+#define BF_FTM_COMBINE_DTEN2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DTEN2), uint32_t) & BM_FTM_COMBINE_DTEN2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DTEN2 field to a new value.
+#define BW_FTM_COMBINE_DTEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN2[21] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0 - The PWM synchronization in this pair of channels is disabled.
+ * - 1 - The PWM synchronization in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_SYNCEN2 (21U) //!< Bit position for FTM_COMBINE_SYNCEN2.
+#define BM_FTM_COMBINE_SYNCEN2 (0x00200000U) //!< Bit mask for FTM_COMBINE_SYNCEN2.
+#define BS_FTM_COMBINE_SYNCEN2 (1U) //!< Bit field size in bits for FTM_COMBINE_SYNCEN2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_SYNCEN2 field.
+#define BR_FTM_COMBINE_SYNCEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN2))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_SYNCEN2.
+#define BF_FTM_COMBINE_SYNCEN2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_SYNCEN2), uint32_t) & BM_FTM_COMBINE_SYNCEN2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SYNCEN2 field to a new value.
+#define BW_FTM_COMBINE_SYNCEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN2[22] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The fault control in this pair of channels is disabled.
+ * - 1 - The fault control in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_FAULTEN2 (22U) //!< Bit position for FTM_COMBINE_FAULTEN2.
+#define BM_FTM_COMBINE_FAULTEN2 (0x00400000U) //!< Bit mask for FTM_COMBINE_FAULTEN2.
+#define BS_FTM_COMBINE_FAULTEN2 (1U) //!< Bit field size in bits for FTM_COMBINE_FAULTEN2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_FAULTEN2 field.
+#define BR_FTM_COMBINE_FAULTEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN2))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_FAULTEN2.
+#define BF_FTM_COMBINE_FAULTEN2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_FAULTEN2), uint32_t) & BM_FTM_COMBINE_FAULTEN2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FAULTEN2 field to a new value.
+#define BW_FTM_COMBINE_FAULTEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE3[24] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Channels (n) and (n+1) are independent.
+ * - 1 - Channels (n) and (n+1) are combined.
+ */
+//@{
+#define BP_FTM_COMBINE_COMBINE3 (24U) //!< Bit position for FTM_COMBINE_COMBINE3.
+#define BM_FTM_COMBINE_COMBINE3 (0x01000000U) //!< Bit mask for FTM_COMBINE_COMBINE3.
+#define BS_FTM_COMBINE_COMBINE3 (1U) //!< Bit field size in bits for FTM_COMBINE_COMBINE3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_COMBINE3 field.
+#define BR_FTM_COMBINE_COMBINE3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE3))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_COMBINE3.
+#define BF_FTM_COMBINE_COMBINE3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMBINE3), uint32_t) & BM_FTM_COMBINE_COMBINE3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COMBINE3 field to a new value.
+#define BW_FTM_COMBINE_COMBINE3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field COMP3[25] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+//@{
+#define BP_FTM_COMBINE_COMP3 (25U) //!< Bit position for FTM_COMBINE_COMP3.
+#define BM_FTM_COMBINE_COMP3 (0x02000000U) //!< Bit mask for FTM_COMBINE_COMP3.
+#define BS_FTM_COMBINE_COMP3 (1U) //!< Bit field size in bits for FTM_COMBINE_COMP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_COMP3 field.
+#define BR_FTM_COMBINE_COMP3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP3))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_COMP3.
+#define BF_FTM_COMBINE_COMP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_COMP3), uint32_t) & BM_FTM_COMBINE_COMP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COMP3 field to a new value.
+#define BW_FTM_COMBINE_COMP3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN3[26] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_DECAPEN3 (26U) //!< Bit position for FTM_COMBINE_DECAPEN3.
+#define BM_FTM_COMBINE_DECAPEN3 (0x04000000U) //!< Bit mask for FTM_COMBINE_DECAPEN3.
+#define BS_FTM_COMBINE_DECAPEN3 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAPEN3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_DECAPEN3 field.
+#define BR_FTM_COMBINE_DECAPEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN3))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_DECAPEN3.
+#define BF_FTM_COMBINE_DECAPEN3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAPEN3), uint32_t) & BM_FTM_COMBINE_DECAPEN3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DECAPEN3 field to a new value.
+#define BW_FTM_COMBINE_DECAPEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP3[27] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if dual edge capture - one-shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0 - The dual edge captures are inactive.
+ * - 1 - The dual edge captures are active.
+ */
+//@{
+#define BP_FTM_COMBINE_DECAP3 (27U) //!< Bit position for FTM_COMBINE_DECAP3.
+#define BM_FTM_COMBINE_DECAP3 (0x08000000U) //!< Bit mask for FTM_COMBINE_DECAP3.
+#define BS_FTM_COMBINE_DECAP3 (1U) //!< Bit field size in bits for FTM_COMBINE_DECAP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_DECAP3 field.
+#define BR_FTM_COMBINE_DECAP3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP3))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_DECAP3.
+#define BF_FTM_COMBINE_DECAP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DECAP3), uint32_t) & BM_FTM_COMBINE_DECAP3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DECAP3 field to a new value.
+#define BW_FTM_COMBINE_DECAP3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN3[28] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The deadtime insertion in this pair of channels is disabled.
+ * - 1 - The deadtime insertion in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_DTEN3 (28U) //!< Bit position for FTM_COMBINE_DTEN3.
+#define BM_FTM_COMBINE_DTEN3 (0x10000000U) //!< Bit mask for FTM_COMBINE_DTEN3.
+#define BS_FTM_COMBINE_DTEN3 (1U) //!< Bit field size in bits for FTM_COMBINE_DTEN3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_DTEN3 field.
+#define BR_FTM_COMBINE_DTEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN3))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_DTEN3.
+#define BF_FTM_COMBINE_DTEN3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_DTEN3), uint32_t) & BM_FTM_COMBINE_DTEN3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DTEN3 field to a new value.
+#define BW_FTM_COMBINE_DTEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN3[29] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0 - The PWM synchronization in this pair of channels is disabled.
+ * - 1 - The PWM synchronization in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_SYNCEN3 (29U) //!< Bit position for FTM_COMBINE_SYNCEN3.
+#define BM_FTM_COMBINE_SYNCEN3 (0x20000000U) //!< Bit mask for FTM_COMBINE_SYNCEN3.
+#define BS_FTM_COMBINE_SYNCEN3 (1U) //!< Bit field size in bits for FTM_COMBINE_SYNCEN3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_SYNCEN3 field.
+#define BR_FTM_COMBINE_SYNCEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN3))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_SYNCEN3.
+#define BF_FTM_COMBINE_SYNCEN3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_SYNCEN3), uint32_t) & BM_FTM_COMBINE_SYNCEN3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SYNCEN3 field to a new value.
+#define BW_FTM_COMBINE_SYNCEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN3[30] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The fault control in this pair of channels is disabled.
+ * - 1 - The fault control in this pair of channels is enabled.
+ */
+//@{
+#define BP_FTM_COMBINE_FAULTEN3 (30U) //!< Bit position for FTM_COMBINE_FAULTEN3.
+#define BM_FTM_COMBINE_FAULTEN3 (0x40000000U) //!< Bit mask for FTM_COMBINE_FAULTEN3.
+#define BS_FTM_COMBINE_FAULTEN3 (1U) //!< Bit field size in bits for FTM_COMBINE_FAULTEN3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_COMBINE_FAULTEN3 field.
+#define BR_FTM_COMBINE_FAULTEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN3))
+#endif
+
+//! @brief Format value for bitfield FTM_COMBINE_FAULTEN3.
+#define BF_FTM_COMBINE_FAULTEN3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_COMBINE_FAULTEN3), uint32_t) & BM_FTM_COMBINE_FAULTEN3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FAULTEN3 field to a new value.
+#define BW_FTM_COMBINE_FAULTEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN3) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_DEADTIME - Deadtime Insertion Control
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_DEADTIME - Deadtime Insertion Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the deadtime prescaler factor and deadtime value. All
+ * FTM channels use this clock prescaler and this deadtime value for the deadtime
+ * insertion.
+ */
+typedef union _hw_ftm_deadtime
+{
+ uint32_t U;
+ struct _hw_ftm_deadtime_bitfields
+ {
+ uint32_t DTVAL : 6; //!< [5:0] Deadtime Value
+ uint32_t DTPS : 2; //!< [7:6] Deadtime Prescaler Value
+ uint32_t RESERVED0 : 24; //!< [31:8]
+ } B;
+} hw_ftm_deadtime_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_DEADTIME register
+ */
+//@{
+#define HW_FTM_DEADTIME_ADDR(x) (REGS_FTM_BASE(x) + 0x68U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_DEADTIME(x) (*(__IO hw_ftm_deadtime_t *) HW_FTM_DEADTIME_ADDR(x))
+#define HW_FTM_DEADTIME_RD(x) (HW_FTM_DEADTIME(x).U)
+#define HW_FTM_DEADTIME_WR(x, v) (HW_FTM_DEADTIME(x).U = (v))
+#define HW_FTM_DEADTIME_SET(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) | (v)))
+#define HW_FTM_DEADTIME_CLR(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) & ~(v)))
+#define HW_FTM_DEADTIME_TOG(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_DEADTIME bitfields
+ */
+
+/*!
+ * @name Register FTM_DEADTIME, field DTVAL[5:0] (RW)
+ *
+ * Selects the deadtime insertion value for the deadtime counter. The deadtime
+ * counter is clocked by a scaled version of the system clock. See the description
+ * of DTPS. Deadtime insert value = (DTPS * DTVAL). DTVAL selects the number of
+ * deadtime counts inserted as follows: When DTVAL is 0, no counts are inserted.
+ * When DTVAL is 1, 1 count is inserted. When DTVAL is 2, 2 counts are inserted.
+ * This pattern continues up to a possible 63 counts. This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ */
+//@{
+#define BP_FTM_DEADTIME_DTVAL (0U) //!< Bit position for FTM_DEADTIME_DTVAL.
+#define BM_FTM_DEADTIME_DTVAL (0x0000003FU) //!< Bit mask for FTM_DEADTIME_DTVAL.
+#define BS_FTM_DEADTIME_DTVAL (6U) //!< Bit field size in bits for FTM_DEADTIME_DTVAL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_DEADTIME_DTVAL field.
+#define BR_FTM_DEADTIME_DTVAL(x) (HW_FTM_DEADTIME(x).B.DTVAL)
+#endif
+
+//! @brief Format value for bitfield FTM_DEADTIME_DTVAL.
+#define BF_FTM_DEADTIME_DTVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_DEADTIME_DTVAL), uint32_t) & BM_FTM_DEADTIME_DTVAL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DTVAL field to a new value.
+#define BW_FTM_DEADTIME_DTVAL(x, v) (HW_FTM_DEADTIME_WR(x, (HW_FTM_DEADTIME_RD(x) & ~BM_FTM_DEADTIME_DTVAL) | BF_FTM_DEADTIME_DTVAL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_DEADTIME, field DTPS[7:6] (RW)
+ *
+ * Selects the division factor of the system clock. This prescaled clock is used
+ * by the deadtime counter. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0x - Divide the system clock by 1.
+ * - 10 - Divide the system clock by 4.
+ * - 11 - Divide the system clock by 16.
+ */
+//@{
+#define BP_FTM_DEADTIME_DTPS (6U) //!< Bit position for FTM_DEADTIME_DTPS.
+#define BM_FTM_DEADTIME_DTPS (0x000000C0U) //!< Bit mask for FTM_DEADTIME_DTPS.
+#define BS_FTM_DEADTIME_DTPS (2U) //!< Bit field size in bits for FTM_DEADTIME_DTPS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_DEADTIME_DTPS field.
+#define BR_FTM_DEADTIME_DTPS(x) (HW_FTM_DEADTIME(x).B.DTPS)
+#endif
+
+//! @brief Format value for bitfield FTM_DEADTIME_DTPS.
+#define BF_FTM_DEADTIME_DTPS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_DEADTIME_DTPS), uint32_t) & BM_FTM_DEADTIME_DTPS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DTPS field to a new value.
+#define BW_FTM_DEADTIME_DTPS(x, v) (HW_FTM_DEADTIME_WR(x, (HW_FTM_DEADTIME_RD(x) & ~BM_FTM_DEADTIME_DTPS) | BF_FTM_DEADTIME_DTPS(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_EXTTRIG - FTM External Trigger
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_EXTTRIG - FTM External Trigger (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register: Indicates when a channel trigger was generated Enables the
+ * generation of a trigger when the FTM counter is equal to its initial value
+ * Selects which channels are used in the generation of the channel triggers Several
+ * channels can be selected to generate multiple triggers in one PWM period.
+ * Channels 6 and 7 are not used to generate channel triggers.
+ */
+typedef union _hw_ftm_exttrig
+{
+ uint32_t U;
+ struct _hw_ftm_exttrig_bitfields
+ {
+ uint32_t CH2TRIG : 1; //!< [0] Channel 2 Trigger Enable
+ uint32_t CH3TRIG : 1; //!< [1] Channel 3 Trigger Enable
+ uint32_t CH4TRIG : 1; //!< [2] Channel 4 Trigger Enable
+ uint32_t CH5TRIG : 1; //!< [3] Channel 5 Trigger Enable
+ uint32_t CH0TRIG : 1; //!< [4] Channel 0 Trigger Enable
+ uint32_t CH1TRIG : 1; //!< [5] Channel 1 Trigger Enable
+ uint32_t INITTRIGEN : 1; //!< [6] Initialization Trigger Enable
+ uint32_t TRIGF : 1; //!< [7] Channel Trigger Flag
+ uint32_t RESERVED0 : 24; //!< [31:8]
+ } B;
+} hw_ftm_exttrig_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_EXTTRIG register
+ */
+//@{
+#define HW_FTM_EXTTRIG_ADDR(x) (REGS_FTM_BASE(x) + 0x6CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_EXTTRIG(x) (*(__IO hw_ftm_exttrig_t *) HW_FTM_EXTTRIG_ADDR(x))
+#define HW_FTM_EXTTRIG_RD(x) (HW_FTM_EXTTRIG(x).U)
+#define HW_FTM_EXTTRIG_WR(x, v) (HW_FTM_EXTTRIG(x).U = (v))
+#define HW_FTM_EXTTRIG_SET(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) | (v)))
+#define HW_FTM_EXTTRIG_CLR(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) & ~(v)))
+#define HW_FTM_EXTTRIG_TOG(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_EXTTRIG bitfields
+ */
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH2TRIG[0] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0 - The generation of the channel trigger is disabled.
+ * - 1 - The generation of the channel trigger is enabled.
+ */
+//@{
+#define BP_FTM_EXTTRIG_CH2TRIG (0U) //!< Bit position for FTM_EXTTRIG_CH2TRIG.
+#define BM_FTM_EXTTRIG_CH2TRIG (0x00000001U) //!< Bit mask for FTM_EXTTRIG_CH2TRIG.
+#define BS_FTM_EXTTRIG_CH2TRIG (1U) //!< Bit field size in bits for FTM_EXTTRIG_CH2TRIG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_EXTTRIG_CH2TRIG field.
+#define BR_FTM_EXTTRIG_CH2TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH2TRIG))
+#endif
+
+//! @brief Format value for bitfield FTM_EXTTRIG_CH2TRIG.
+#define BF_FTM_EXTTRIG_CH2TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH2TRIG), uint32_t) & BM_FTM_EXTTRIG_CH2TRIG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH2TRIG field to a new value.
+#define BW_FTM_EXTTRIG_CH2TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH2TRIG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH3TRIG[1] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0 - The generation of the channel trigger is disabled.
+ * - 1 - The generation of the channel trigger is enabled.
+ */
+//@{
+#define BP_FTM_EXTTRIG_CH3TRIG (1U) //!< Bit position for FTM_EXTTRIG_CH3TRIG.
+#define BM_FTM_EXTTRIG_CH3TRIG (0x00000002U) //!< Bit mask for FTM_EXTTRIG_CH3TRIG.
+#define BS_FTM_EXTTRIG_CH3TRIG (1U) //!< Bit field size in bits for FTM_EXTTRIG_CH3TRIG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_EXTTRIG_CH3TRIG field.
+#define BR_FTM_EXTTRIG_CH3TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH3TRIG))
+#endif
+
+//! @brief Format value for bitfield FTM_EXTTRIG_CH3TRIG.
+#define BF_FTM_EXTTRIG_CH3TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH3TRIG), uint32_t) & BM_FTM_EXTTRIG_CH3TRIG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH3TRIG field to a new value.
+#define BW_FTM_EXTTRIG_CH3TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH3TRIG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH4TRIG[2] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0 - The generation of the channel trigger is disabled.
+ * - 1 - The generation of the channel trigger is enabled.
+ */
+//@{
+#define BP_FTM_EXTTRIG_CH4TRIG (2U) //!< Bit position for FTM_EXTTRIG_CH4TRIG.
+#define BM_FTM_EXTTRIG_CH4TRIG (0x00000004U) //!< Bit mask for FTM_EXTTRIG_CH4TRIG.
+#define BS_FTM_EXTTRIG_CH4TRIG (1U) //!< Bit field size in bits for FTM_EXTTRIG_CH4TRIG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_EXTTRIG_CH4TRIG field.
+#define BR_FTM_EXTTRIG_CH4TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH4TRIG))
+#endif
+
+//! @brief Format value for bitfield FTM_EXTTRIG_CH4TRIG.
+#define BF_FTM_EXTTRIG_CH4TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH4TRIG), uint32_t) & BM_FTM_EXTTRIG_CH4TRIG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH4TRIG field to a new value.
+#define BW_FTM_EXTTRIG_CH4TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH4TRIG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH5TRIG[3] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0 - The generation of the channel trigger is disabled.
+ * - 1 - The generation of the channel trigger is enabled.
+ */
+//@{
+#define BP_FTM_EXTTRIG_CH5TRIG (3U) //!< Bit position for FTM_EXTTRIG_CH5TRIG.
+#define BM_FTM_EXTTRIG_CH5TRIG (0x00000008U) //!< Bit mask for FTM_EXTTRIG_CH5TRIG.
+#define BS_FTM_EXTTRIG_CH5TRIG (1U) //!< Bit field size in bits for FTM_EXTTRIG_CH5TRIG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_EXTTRIG_CH5TRIG field.
+#define BR_FTM_EXTTRIG_CH5TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH5TRIG))
+#endif
+
+//! @brief Format value for bitfield FTM_EXTTRIG_CH5TRIG.
+#define BF_FTM_EXTTRIG_CH5TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH5TRIG), uint32_t) & BM_FTM_EXTTRIG_CH5TRIG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH5TRIG field to a new value.
+#define BW_FTM_EXTTRIG_CH5TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH5TRIG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH0TRIG[4] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0 - The generation of the channel trigger is disabled.
+ * - 1 - The generation of the channel trigger is enabled.
+ */
+//@{
+#define BP_FTM_EXTTRIG_CH0TRIG (4U) //!< Bit position for FTM_EXTTRIG_CH0TRIG.
+#define BM_FTM_EXTTRIG_CH0TRIG (0x00000010U) //!< Bit mask for FTM_EXTTRIG_CH0TRIG.
+#define BS_FTM_EXTTRIG_CH0TRIG (1U) //!< Bit field size in bits for FTM_EXTTRIG_CH0TRIG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_EXTTRIG_CH0TRIG field.
+#define BR_FTM_EXTTRIG_CH0TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH0TRIG))
+#endif
+
+//! @brief Format value for bitfield FTM_EXTTRIG_CH0TRIG.
+#define BF_FTM_EXTTRIG_CH0TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH0TRIG), uint32_t) & BM_FTM_EXTTRIG_CH0TRIG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH0TRIG field to a new value.
+#define BW_FTM_EXTTRIG_CH0TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH0TRIG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH1TRIG[5] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0 - The generation of the channel trigger is disabled.
+ * - 1 - The generation of the channel trigger is enabled.
+ */
+//@{
+#define BP_FTM_EXTTRIG_CH1TRIG (5U) //!< Bit position for FTM_EXTTRIG_CH1TRIG.
+#define BM_FTM_EXTTRIG_CH1TRIG (0x00000020U) //!< Bit mask for FTM_EXTTRIG_CH1TRIG.
+#define BS_FTM_EXTTRIG_CH1TRIG (1U) //!< Bit field size in bits for FTM_EXTTRIG_CH1TRIG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_EXTTRIG_CH1TRIG field.
+#define BR_FTM_EXTTRIG_CH1TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH1TRIG))
+#endif
+
+//! @brief Format value for bitfield FTM_EXTTRIG_CH1TRIG.
+#define BF_FTM_EXTTRIG_CH1TRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_CH1TRIG), uint32_t) & BM_FTM_EXTTRIG_CH1TRIG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH1TRIG field to a new value.
+#define BW_FTM_EXTTRIG_CH1TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH1TRIG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_EXTTRIG, field INITTRIGEN[6] (RW)
+ *
+ * Enables the generation of the trigger when the FTM counter is equal to the
+ * CNTIN register.
+ *
+ * Values:
+ * - 0 - The generation of initialization trigger is disabled.
+ * - 1 - The generation of initialization trigger is enabled.
+ */
+//@{
+#define BP_FTM_EXTTRIG_INITTRIGEN (6U) //!< Bit position for FTM_EXTTRIG_INITTRIGEN.
+#define BM_FTM_EXTTRIG_INITTRIGEN (0x00000040U) //!< Bit mask for FTM_EXTTRIG_INITTRIGEN.
+#define BS_FTM_EXTTRIG_INITTRIGEN (1U) //!< Bit field size in bits for FTM_EXTTRIG_INITTRIGEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_EXTTRIG_INITTRIGEN field.
+#define BR_FTM_EXTTRIG_INITTRIGEN(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_INITTRIGEN))
+#endif
+
+//! @brief Format value for bitfield FTM_EXTTRIG_INITTRIGEN.
+#define BF_FTM_EXTTRIG_INITTRIGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_EXTTRIG_INITTRIGEN), uint32_t) & BM_FTM_EXTTRIG_INITTRIGEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INITTRIGEN field to a new value.
+#define BW_FTM_EXTTRIG_INITTRIGEN(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_INITTRIGEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_EXTTRIG, field TRIGF[7] (ROWZ)
+ *
+ * Set by hardware when a channel trigger is generated. Clear TRIGF by reading
+ * EXTTRIG while TRIGF is set and then writing a 0 to TRIGF. Writing a 1 to TRIGF
+ * has no effect. If another channel trigger is generated before the clearing
+ * sequence is completed, the sequence is reset so TRIGF remains set after the clear
+ * sequence is completed for the earlier TRIGF.
+ *
+ * Values:
+ * - 0 - No channel trigger was generated.
+ * - 1 - A channel trigger was generated.
+ */
+//@{
+#define BP_FTM_EXTTRIG_TRIGF (7U) //!< Bit position for FTM_EXTTRIG_TRIGF.
+#define BM_FTM_EXTTRIG_TRIGF (0x00000080U) //!< Bit mask for FTM_EXTTRIG_TRIGF.
+#define BS_FTM_EXTTRIG_TRIGF (1U) //!< Bit field size in bits for FTM_EXTTRIG_TRIGF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_EXTTRIG_TRIGF field.
+#define BR_FTM_EXTTRIG_TRIGF(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_TRIGF))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_POL - Channels Polarity
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_POL - Channels Polarity (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register defines the output polarity of the FTM channels. The safe value
+ * that is driven in a channel output when the fault control is enabled and a
+ * fault condition is detected is the inactive state of the channel. That is, the
+ * safe value of a channel is the value of its POL bit.
+ */
+typedef union _hw_ftm_pol
+{
+ uint32_t U;
+ struct _hw_ftm_pol_bitfields
+ {
+ uint32_t POL0 : 1; //!< [0] Channel 0 Polarity
+ uint32_t POL1 : 1; //!< [1] Channel 1 Polarity
+ uint32_t POL2 : 1; //!< [2] Channel 2 Polarity
+ uint32_t POL3 : 1; //!< [3] Channel 3 Polarity
+ uint32_t POL4 : 1; //!< [4] Channel 4 Polarity
+ uint32_t POL5 : 1; //!< [5] Channel 5 Polarity
+ uint32_t POL6 : 1; //!< [6] Channel 6 Polarity
+ uint32_t POL7 : 1; //!< [7] Channel 7 Polarity
+ uint32_t RESERVED0 : 24; //!< [31:8]
+ } B;
+} hw_ftm_pol_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_POL register
+ */
+//@{
+#define HW_FTM_POL_ADDR(x) (REGS_FTM_BASE(x) + 0x70U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_POL(x) (*(__IO hw_ftm_pol_t *) HW_FTM_POL_ADDR(x))
+#define HW_FTM_POL_RD(x) (HW_FTM_POL(x).U)
+#define HW_FTM_POL_WR(x, v) (HW_FTM_POL(x).U = (v))
+#define HW_FTM_POL_SET(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) | (v)))
+#define HW_FTM_POL_CLR(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) & ~(v)))
+#define HW_FTM_POL_TOG(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_POL bitfields
+ */
+
+/*!
+ * @name Register FTM_POL, field POL0[0] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The channel polarity is active high.
+ * - 1 - The channel polarity is active low.
+ */
+//@{
+#define BP_FTM_POL_POL0 (0U) //!< Bit position for FTM_POL_POL0.
+#define BM_FTM_POL_POL0 (0x00000001U) //!< Bit mask for FTM_POL_POL0.
+#define BS_FTM_POL_POL0 (1U) //!< Bit field size in bits for FTM_POL_POL0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_POL_POL0 field.
+#define BR_FTM_POL_POL0(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL0))
+#endif
+
+//! @brief Format value for bitfield FTM_POL_POL0.
+#define BF_FTM_POL_POL0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL0), uint32_t) & BM_FTM_POL_POL0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the POL0 field to a new value.
+#define BW_FTM_POL_POL0(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_POL, field POL1[1] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The channel polarity is active high.
+ * - 1 - The channel polarity is active low.
+ */
+//@{
+#define BP_FTM_POL_POL1 (1U) //!< Bit position for FTM_POL_POL1.
+#define BM_FTM_POL_POL1 (0x00000002U) //!< Bit mask for FTM_POL_POL1.
+#define BS_FTM_POL_POL1 (1U) //!< Bit field size in bits for FTM_POL_POL1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_POL_POL1 field.
+#define BR_FTM_POL_POL1(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL1))
+#endif
+
+//! @brief Format value for bitfield FTM_POL_POL1.
+#define BF_FTM_POL_POL1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL1), uint32_t) & BM_FTM_POL_POL1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the POL1 field to a new value.
+#define BW_FTM_POL_POL1(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_POL, field POL2[2] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The channel polarity is active high.
+ * - 1 - The channel polarity is active low.
+ */
+//@{
+#define BP_FTM_POL_POL2 (2U) //!< Bit position for FTM_POL_POL2.
+#define BM_FTM_POL_POL2 (0x00000004U) //!< Bit mask for FTM_POL_POL2.
+#define BS_FTM_POL_POL2 (1U) //!< Bit field size in bits for FTM_POL_POL2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_POL_POL2 field.
+#define BR_FTM_POL_POL2(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL2))
+#endif
+
+//! @brief Format value for bitfield FTM_POL_POL2.
+#define BF_FTM_POL_POL2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL2), uint32_t) & BM_FTM_POL_POL2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the POL2 field to a new value.
+#define BW_FTM_POL_POL2(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_POL, field POL3[3] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The channel polarity is active high.
+ * - 1 - The channel polarity is active low.
+ */
+//@{
+#define BP_FTM_POL_POL3 (3U) //!< Bit position for FTM_POL_POL3.
+#define BM_FTM_POL_POL3 (0x00000008U) //!< Bit mask for FTM_POL_POL3.
+#define BS_FTM_POL_POL3 (1U) //!< Bit field size in bits for FTM_POL_POL3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_POL_POL3 field.
+#define BR_FTM_POL_POL3(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL3))
+#endif
+
+//! @brief Format value for bitfield FTM_POL_POL3.
+#define BF_FTM_POL_POL3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL3), uint32_t) & BM_FTM_POL_POL3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the POL3 field to a new value.
+#define BW_FTM_POL_POL3(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_POL, field POL4[4] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The channel polarity is active high.
+ * - 1 - The channel polarity is active low.
+ */
+//@{
+#define BP_FTM_POL_POL4 (4U) //!< Bit position for FTM_POL_POL4.
+#define BM_FTM_POL_POL4 (0x00000010U) //!< Bit mask for FTM_POL_POL4.
+#define BS_FTM_POL_POL4 (1U) //!< Bit field size in bits for FTM_POL_POL4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_POL_POL4 field.
+#define BR_FTM_POL_POL4(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL4))
+#endif
+
+//! @brief Format value for bitfield FTM_POL_POL4.
+#define BF_FTM_POL_POL4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL4), uint32_t) & BM_FTM_POL_POL4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the POL4 field to a new value.
+#define BW_FTM_POL_POL4(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_POL, field POL5[5] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The channel polarity is active high.
+ * - 1 - The channel polarity is active low.
+ */
+//@{
+#define BP_FTM_POL_POL5 (5U) //!< Bit position for FTM_POL_POL5.
+#define BM_FTM_POL_POL5 (0x00000020U) //!< Bit mask for FTM_POL_POL5.
+#define BS_FTM_POL_POL5 (1U) //!< Bit field size in bits for FTM_POL_POL5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_POL_POL5 field.
+#define BR_FTM_POL_POL5(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL5))
+#endif
+
+//! @brief Format value for bitfield FTM_POL_POL5.
+#define BF_FTM_POL_POL5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL5), uint32_t) & BM_FTM_POL_POL5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the POL5 field to a new value.
+#define BW_FTM_POL_POL5(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_POL, field POL6[6] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The channel polarity is active high.
+ * - 1 - The channel polarity is active low.
+ */
+//@{
+#define BP_FTM_POL_POL6 (6U) //!< Bit position for FTM_POL_POL6.
+#define BM_FTM_POL_POL6 (0x00000040U) //!< Bit mask for FTM_POL_POL6.
+#define BS_FTM_POL_POL6 (1U) //!< Bit field size in bits for FTM_POL_POL6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_POL_POL6 field.
+#define BR_FTM_POL_POL6(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL6))
+#endif
+
+//! @brief Format value for bitfield FTM_POL_POL6.
+#define BF_FTM_POL_POL6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL6), uint32_t) & BM_FTM_POL_POL6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the POL6 field to a new value.
+#define BW_FTM_POL_POL6(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_POL, field POL7[7] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The channel polarity is active high.
+ * - 1 - The channel polarity is active low.
+ */
+//@{
+#define BP_FTM_POL_POL7 (7U) //!< Bit position for FTM_POL_POL7.
+#define BM_FTM_POL_POL7 (0x00000080U) //!< Bit mask for FTM_POL_POL7.
+#define BS_FTM_POL_POL7 (1U) //!< Bit field size in bits for FTM_POL_POL7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_POL_POL7 field.
+#define BR_FTM_POL_POL7(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL7))
+#endif
+
+//! @brief Format value for bitfield FTM_POL_POL7.
+#define BF_FTM_POL_POL7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_POL_POL7), uint32_t) & BM_FTM_POL_POL7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the POL7 field to a new value.
+#define BW_FTM_POL_POL7(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL7) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_FMS - Fault Mode Status
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_FMS - Fault Mode Status (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the fault detection flags, write protection enable
+ * bit, and the logic OR of the enabled fault inputs.
+ */
+typedef union _hw_ftm_fms
+{
+ uint32_t U;
+ struct _hw_ftm_fms_bitfields
+ {
+ uint32_t FAULTF0 : 1; //!< [0] Fault Detection Flag 0
+ uint32_t FAULTF1 : 1; //!< [1] Fault Detection Flag 1
+ uint32_t FAULTF2 : 1; //!< [2] Fault Detection Flag 2
+ uint32_t FAULTF3 : 1; //!< [3] Fault Detection Flag 3
+ uint32_t RESERVED0 : 1; //!< [4]
+ uint32_t FAULTIN : 1; //!< [5] Fault Inputs
+ uint32_t WPEN : 1; //!< [6] Write Protection Enable
+ uint32_t FAULTF : 1; //!< [7] Fault Detection Flag
+ uint32_t RESERVED1 : 24; //!< [31:8]
+ } B;
+} hw_ftm_fms_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_FMS register
+ */
+//@{
+#define HW_FTM_FMS_ADDR(x) (REGS_FTM_BASE(x) + 0x74U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_FMS(x) (*(__IO hw_ftm_fms_t *) HW_FTM_FMS_ADDR(x))
+#define HW_FTM_FMS_RD(x) (HW_FTM_FMS(x).U)
+#define HW_FTM_FMS_WR(x, v) (HW_FTM_FMS(x).U = (v))
+#define HW_FTM_FMS_SET(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) | (v)))
+#define HW_FTM_FMS_CLR(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) & ~(v)))
+#define HW_FTM_FMS_TOG(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_FMS bitfields
+ */
+
+/*!
+ * @name Register FTM_FMS, field FAULTF0[0] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF0
+ * by reading the FMS register while FAULTF0 is set and then writing a 0 to
+ * FAULTF0 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF0 has no effect. FAULTF0 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF0 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0 - No fault condition was detected at the fault input.
+ * - 1 - A fault condition was detected at the fault input.
+ */
+//@{
+#define BP_FTM_FMS_FAULTF0 (0U) //!< Bit position for FTM_FMS_FAULTF0.
+#define BM_FTM_FMS_FAULTF0 (0x00000001U) //!< Bit mask for FTM_FMS_FAULTF0.
+#define BS_FTM_FMS_FAULTF0 (1U) //!< Bit field size in bits for FTM_FMS_FAULTF0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FMS_FAULTF0 field.
+#define BR_FTM_FMS_FAULTF0(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF0))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FMS, field FAULTF1[1] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF1
+ * by reading the FMS register while FAULTF1 is set and then writing a 0 to
+ * FAULTF1 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF1 has no effect. FAULTF1 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF1 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0 - No fault condition was detected at the fault input.
+ * - 1 - A fault condition was detected at the fault input.
+ */
+//@{
+#define BP_FTM_FMS_FAULTF1 (1U) //!< Bit position for FTM_FMS_FAULTF1.
+#define BM_FTM_FMS_FAULTF1 (0x00000002U) //!< Bit mask for FTM_FMS_FAULTF1.
+#define BS_FTM_FMS_FAULTF1 (1U) //!< Bit field size in bits for FTM_FMS_FAULTF1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FMS_FAULTF1 field.
+#define BR_FTM_FMS_FAULTF1(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF1))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FMS, field FAULTF2[2] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF2
+ * by reading the FMS register while FAULTF2 is set and then writing a 0 to
+ * FAULTF2 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF2 has no effect. FAULTF2 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF2 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0 - No fault condition was detected at the fault input.
+ * - 1 - A fault condition was detected at the fault input.
+ */
+//@{
+#define BP_FTM_FMS_FAULTF2 (2U) //!< Bit position for FTM_FMS_FAULTF2.
+#define BM_FTM_FMS_FAULTF2 (0x00000004U) //!< Bit mask for FTM_FMS_FAULTF2.
+#define BS_FTM_FMS_FAULTF2 (1U) //!< Bit field size in bits for FTM_FMS_FAULTF2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FMS_FAULTF2 field.
+#define BR_FTM_FMS_FAULTF2(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF2))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FMS, field FAULTF3[3] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF3
+ * by reading the FMS register while FAULTF3 is set and then writing a 0 to
+ * FAULTF3 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF3 has no effect. FAULTF3 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF3 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0 - No fault condition was detected at the fault input.
+ * - 1 - A fault condition was detected at the fault input.
+ */
+//@{
+#define BP_FTM_FMS_FAULTF3 (3U) //!< Bit position for FTM_FMS_FAULTF3.
+#define BM_FTM_FMS_FAULTF3 (0x00000008U) //!< Bit mask for FTM_FMS_FAULTF3.
+#define BS_FTM_FMS_FAULTF3 (1U) //!< Bit field size in bits for FTM_FMS_FAULTF3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FMS_FAULTF3 field.
+#define BR_FTM_FMS_FAULTF3(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF3))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FMS, field FAULTIN[5] (RO)
+ *
+ * Represents the logic OR of the enabled fault inputs after their filter (if
+ * their filter is enabled) when fault control is enabled.
+ *
+ * Values:
+ * - 0 - The logic OR of the enabled fault inputs is 0.
+ * - 1 - The logic OR of the enabled fault inputs is 1.
+ */
+//@{
+#define BP_FTM_FMS_FAULTIN (5U) //!< Bit position for FTM_FMS_FAULTIN.
+#define BM_FTM_FMS_FAULTIN (0x00000020U) //!< Bit mask for FTM_FMS_FAULTIN.
+#define BS_FTM_FMS_FAULTIN (1U) //!< Bit field size in bits for FTM_FMS_FAULTIN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FMS_FAULTIN field.
+#define BR_FTM_FMS_FAULTIN(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTIN))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FMS, field WPEN[6] (RW)
+ *
+ * The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written
+ * to it. WPEN is cleared when WPEN bit is read as a 1 and then 1 is written to
+ * WPDIS. Writing 0 to WPEN has no effect.
+ *
+ * Values:
+ * - 0 - Write protection is disabled. Write protected bits can be written.
+ * - 1 - Write protection is enabled. Write protected bits cannot be written.
+ */
+//@{
+#define BP_FTM_FMS_WPEN (6U) //!< Bit position for FTM_FMS_WPEN.
+#define BM_FTM_FMS_WPEN (0x00000040U) //!< Bit mask for FTM_FMS_WPEN.
+#define BS_FTM_FMS_WPEN (1U) //!< Bit field size in bits for FTM_FMS_WPEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FMS_WPEN field.
+#define BR_FTM_FMS_WPEN(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_WPEN))
+#endif
+
+//! @brief Format value for bitfield FTM_FMS_WPEN.
+#define BF_FTM_FMS_WPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FMS_WPEN), uint32_t) & BM_FTM_FMS_WPEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WPEN field to a new value.
+#define BW_FTM_FMS_WPEN(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_WPEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FMS, field FAULTF[7] (ROWZ)
+ *
+ * Represents the logic OR of the individual FAULTFj bits where j = 3, 2, 1, 0.
+ * Clear FAULTF by reading the FMS register while FAULTF is set and then writing
+ * a 0 to FAULTF while there is no existing fault condition at the enabled fault
+ * inputs. Writing a 1 to FAULTF has no effect. If another fault condition is
+ * detected in an enabled fault input before the clearing sequence is completed, the
+ * sequence is reset so FAULTF remains set after the clearing sequence is
+ * completed for the earlier fault condition. FAULTF is also cleared when FAULTFj bits
+ * are cleared individually.
+ *
+ * Values:
+ * - 0 - No fault condition was detected.
+ * - 1 - A fault condition was detected.
+ */
+//@{
+#define BP_FTM_FMS_FAULTF (7U) //!< Bit position for FTM_FMS_FAULTF.
+#define BM_FTM_FMS_FAULTF (0x00000080U) //!< Bit mask for FTM_FMS_FAULTF.
+#define BS_FTM_FMS_FAULTF (1U) //!< Bit field size in bits for FTM_FMS_FAULTF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FMS_FAULTF field.
+#define BR_FTM_FMS_FAULTF(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_FILTER - Input Capture Filter Control
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_FILTER - Input Capture Filter Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the filter value for the inputs of channels. Channels
+ * 4, 5, 6 and 7 do not have an input filter. Writing to the FILTER register has
+ * immediate effect and must be done only when the channels 0, 1, 2, and 3 are not
+ * in input modes. Failure to do this could result in a missing valid signal.
+ */
+typedef union _hw_ftm_filter
+{
+ uint32_t U;
+ struct _hw_ftm_filter_bitfields
+ {
+ uint32_t CH0FVAL : 4; //!< [3:0] Channel 0 Input Filter
+ uint32_t CH1FVAL : 4; //!< [7:4] Channel 1 Input Filter
+ uint32_t CH2FVAL : 4; //!< [11:8] Channel 2 Input Filter
+ uint32_t CH3FVAL : 4; //!< [15:12] Channel 3 Input Filter
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_ftm_filter_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_FILTER register
+ */
+//@{
+#define HW_FTM_FILTER_ADDR(x) (REGS_FTM_BASE(x) + 0x78U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_FILTER(x) (*(__IO hw_ftm_filter_t *) HW_FTM_FILTER_ADDR(x))
+#define HW_FTM_FILTER_RD(x) (HW_FTM_FILTER(x).U)
+#define HW_FTM_FILTER_WR(x, v) (HW_FTM_FILTER(x).U = (v))
+#define HW_FTM_FILTER_SET(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) | (v)))
+#define HW_FTM_FILTER_CLR(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) & ~(v)))
+#define HW_FTM_FILTER_TOG(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_FILTER bitfields
+ */
+
+/*!
+ * @name Register FTM_FILTER, field CH0FVAL[3:0] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+//@{
+#define BP_FTM_FILTER_CH0FVAL (0U) //!< Bit position for FTM_FILTER_CH0FVAL.
+#define BM_FTM_FILTER_CH0FVAL (0x0000000FU) //!< Bit mask for FTM_FILTER_CH0FVAL.
+#define BS_FTM_FILTER_CH0FVAL (4U) //!< Bit field size in bits for FTM_FILTER_CH0FVAL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FILTER_CH0FVAL field.
+#define BR_FTM_FILTER_CH0FVAL(x) (HW_FTM_FILTER(x).B.CH0FVAL)
+#endif
+
+//! @brief Format value for bitfield FTM_FILTER_CH0FVAL.
+#define BF_FTM_FILTER_CH0FVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FILTER_CH0FVAL), uint32_t) & BM_FTM_FILTER_CH0FVAL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH0FVAL field to a new value.
+#define BW_FTM_FILTER_CH0FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH0FVAL) | BF_FTM_FILTER_CH0FVAL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FILTER, field CH1FVAL[7:4] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+//@{
+#define BP_FTM_FILTER_CH1FVAL (4U) //!< Bit position for FTM_FILTER_CH1FVAL.
+#define BM_FTM_FILTER_CH1FVAL (0x000000F0U) //!< Bit mask for FTM_FILTER_CH1FVAL.
+#define BS_FTM_FILTER_CH1FVAL (4U) //!< Bit field size in bits for FTM_FILTER_CH1FVAL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FILTER_CH1FVAL field.
+#define BR_FTM_FILTER_CH1FVAL(x) (HW_FTM_FILTER(x).B.CH1FVAL)
+#endif
+
+//! @brief Format value for bitfield FTM_FILTER_CH1FVAL.
+#define BF_FTM_FILTER_CH1FVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FILTER_CH1FVAL), uint32_t) & BM_FTM_FILTER_CH1FVAL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH1FVAL field to a new value.
+#define BW_FTM_FILTER_CH1FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH1FVAL) | BF_FTM_FILTER_CH1FVAL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FILTER, field CH2FVAL[11:8] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+//@{
+#define BP_FTM_FILTER_CH2FVAL (8U) //!< Bit position for FTM_FILTER_CH2FVAL.
+#define BM_FTM_FILTER_CH2FVAL (0x00000F00U) //!< Bit mask for FTM_FILTER_CH2FVAL.
+#define BS_FTM_FILTER_CH2FVAL (4U) //!< Bit field size in bits for FTM_FILTER_CH2FVAL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FILTER_CH2FVAL field.
+#define BR_FTM_FILTER_CH2FVAL(x) (HW_FTM_FILTER(x).B.CH2FVAL)
+#endif
+
+//! @brief Format value for bitfield FTM_FILTER_CH2FVAL.
+#define BF_FTM_FILTER_CH2FVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FILTER_CH2FVAL), uint32_t) & BM_FTM_FILTER_CH2FVAL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH2FVAL field to a new value.
+#define BW_FTM_FILTER_CH2FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH2FVAL) | BF_FTM_FILTER_CH2FVAL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FILTER, field CH3FVAL[15:12] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+//@{
+#define BP_FTM_FILTER_CH3FVAL (12U) //!< Bit position for FTM_FILTER_CH3FVAL.
+#define BM_FTM_FILTER_CH3FVAL (0x0000F000U) //!< Bit mask for FTM_FILTER_CH3FVAL.
+#define BS_FTM_FILTER_CH3FVAL (4U) //!< Bit field size in bits for FTM_FILTER_CH3FVAL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FILTER_CH3FVAL field.
+#define BR_FTM_FILTER_CH3FVAL(x) (HW_FTM_FILTER(x).B.CH3FVAL)
+#endif
+
+//! @brief Format value for bitfield FTM_FILTER_CH3FVAL.
+#define BF_FTM_FILTER_CH3FVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FILTER_CH3FVAL), uint32_t) & BM_FTM_FILTER_CH3FVAL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH3FVAL field to a new value.
+#define BW_FTM_FILTER_CH3FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH3FVAL) | BF_FTM_FILTER_CH3FVAL(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_FLTCTRL - Fault Control
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_FLTCTRL - Fault Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the filter value for the fault inputs, enables the
+ * fault inputs and the fault inputs filter.
+ */
+typedef union _hw_ftm_fltctrl
+{
+ uint32_t U;
+ struct _hw_ftm_fltctrl_bitfields
+ {
+ uint32_t FAULT0EN : 1; //!< [0] Fault Input 0 Enable
+ uint32_t FAULT1EN : 1; //!< [1] Fault Input 1 Enable
+ uint32_t FAULT2EN : 1; //!< [2] Fault Input 2 Enable
+ uint32_t FAULT3EN : 1; //!< [3] Fault Input 3 Enable
+ uint32_t FFLTR0EN : 1; //!< [4] Fault Input 0 Filter Enable
+ uint32_t FFLTR1EN : 1; //!< [5] Fault Input 1 Filter Enable
+ uint32_t FFLTR2EN : 1; //!< [6] Fault Input 2 Filter Enable
+ uint32_t FFLTR3EN : 1; //!< [7] Fault Input 3 Filter Enable
+ uint32_t FFVAL : 4; //!< [11:8] Fault Input Filter
+ uint32_t RESERVED0 : 20; //!< [31:12]
+ } B;
+} hw_ftm_fltctrl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_FLTCTRL register
+ */
+//@{
+#define HW_FTM_FLTCTRL_ADDR(x) (REGS_FTM_BASE(x) + 0x7CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_FLTCTRL(x) (*(__IO hw_ftm_fltctrl_t *) HW_FTM_FLTCTRL_ADDR(x))
+#define HW_FTM_FLTCTRL_RD(x) (HW_FTM_FLTCTRL(x).U)
+#define HW_FTM_FLTCTRL_WR(x, v) (HW_FTM_FLTCTRL(x).U = (v))
+#define HW_FTM_FLTCTRL_SET(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) | (v)))
+#define HW_FTM_FLTCTRL_CLR(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) & ~(v)))
+#define HW_FTM_FLTCTRL_TOG(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_FLTCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT0EN[0] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Fault input is disabled.
+ * - 1 - Fault input is enabled.
+ */
+//@{
+#define BP_FTM_FLTCTRL_FAULT0EN (0U) //!< Bit position for FTM_FLTCTRL_FAULT0EN.
+#define BM_FTM_FLTCTRL_FAULT0EN (0x00000001U) //!< Bit mask for FTM_FLTCTRL_FAULT0EN.
+#define BS_FTM_FLTCTRL_FAULT0EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FAULT0EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FLTCTRL_FAULT0EN field.
+#define BR_FTM_FLTCTRL_FAULT0EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT0EN))
+#endif
+
+//! @brief Format value for bitfield FTM_FLTCTRL_FAULT0EN.
+#define BF_FTM_FLTCTRL_FAULT0EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FAULT0EN), uint32_t) & BM_FTM_FLTCTRL_FAULT0EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FAULT0EN field to a new value.
+#define BW_FTM_FLTCTRL_FAULT0EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT0EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT1EN[1] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Fault input is disabled.
+ * - 1 - Fault input is enabled.
+ */
+//@{
+#define BP_FTM_FLTCTRL_FAULT1EN (1U) //!< Bit position for FTM_FLTCTRL_FAULT1EN.
+#define BM_FTM_FLTCTRL_FAULT1EN (0x00000002U) //!< Bit mask for FTM_FLTCTRL_FAULT1EN.
+#define BS_FTM_FLTCTRL_FAULT1EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FAULT1EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FLTCTRL_FAULT1EN field.
+#define BR_FTM_FLTCTRL_FAULT1EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT1EN))
+#endif
+
+//! @brief Format value for bitfield FTM_FLTCTRL_FAULT1EN.
+#define BF_FTM_FLTCTRL_FAULT1EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FAULT1EN), uint32_t) & BM_FTM_FLTCTRL_FAULT1EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FAULT1EN field to a new value.
+#define BW_FTM_FLTCTRL_FAULT1EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT1EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT2EN[2] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Fault input is disabled.
+ * - 1 - Fault input is enabled.
+ */
+//@{
+#define BP_FTM_FLTCTRL_FAULT2EN (2U) //!< Bit position for FTM_FLTCTRL_FAULT2EN.
+#define BM_FTM_FLTCTRL_FAULT2EN (0x00000004U) //!< Bit mask for FTM_FLTCTRL_FAULT2EN.
+#define BS_FTM_FLTCTRL_FAULT2EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FAULT2EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FLTCTRL_FAULT2EN field.
+#define BR_FTM_FLTCTRL_FAULT2EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT2EN))
+#endif
+
+//! @brief Format value for bitfield FTM_FLTCTRL_FAULT2EN.
+#define BF_FTM_FLTCTRL_FAULT2EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FAULT2EN), uint32_t) & BM_FTM_FLTCTRL_FAULT2EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FAULT2EN field to a new value.
+#define BW_FTM_FLTCTRL_FAULT2EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT2EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT3EN[3] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Fault input is disabled.
+ * - 1 - Fault input is enabled.
+ */
+//@{
+#define BP_FTM_FLTCTRL_FAULT3EN (3U) //!< Bit position for FTM_FLTCTRL_FAULT3EN.
+#define BM_FTM_FLTCTRL_FAULT3EN (0x00000008U) //!< Bit mask for FTM_FLTCTRL_FAULT3EN.
+#define BS_FTM_FLTCTRL_FAULT3EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FAULT3EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FLTCTRL_FAULT3EN field.
+#define BR_FTM_FLTCTRL_FAULT3EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT3EN))
+#endif
+
+//! @brief Format value for bitfield FTM_FLTCTRL_FAULT3EN.
+#define BF_FTM_FLTCTRL_FAULT3EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FAULT3EN), uint32_t) & BM_FTM_FLTCTRL_FAULT3EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FAULT3EN field to a new value.
+#define BW_FTM_FLTCTRL_FAULT3EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT3EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR0EN[4] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Fault input filter is disabled.
+ * - 1 - Fault input filter is enabled.
+ */
+//@{
+#define BP_FTM_FLTCTRL_FFLTR0EN (4U) //!< Bit position for FTM_FLTCTRL_FFLTR0EN.
+#define BM_FTM_FLTCTRL_FFLTR0EN (0x00000010U) //!< Bit mask for FTM_FLTCTRL_FFLTR0EN.
+#define BS_FTM_FLTCTRL_FFLTR0EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FFLTR0EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FLTCTRL_FFLTR0EN field.
+#define BR_FTM_FLTCTRL_FFLTR0EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR0EN))
+#endif
+
+//! @brief Format value for bitfield FTM_FLTCTRL_FFLTR0EN.
+#define BF_FTM_FLTCTRL_FFLTR0EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FFLTR0EN), uint32_t) & BM_FTM_FLTCTRL_FFLTR0EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FFLTR0EN field to a new value.
+#define BW_FTM_FLTCTRL_FFLTR0EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR0EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR1EN[5] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Fault input filter is disabled.
+ * - 1 - Fault input filter is enabled.
+ */
+//@{
+#define BP_FTM_FLTCTRL_FFLTR1EN (5U) //!< Bit position for FTM_FLTCTRL_FFLTR1EN.
+#define BM_FTM_FLTCTRL_FFLTR1EN (0x00000020U) //!< Bit mask for FTM_FLTCTRL_FFLTR1EN.
+#define BS_FTM_FLTCTRL_FFLTR1EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FFLTR1EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FLTCTRL_FFLTR1EN field.
+#define BR_FTM_FLTCTRL_FFLTR1EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR1EN))
+#endif
+
+//! @brief Format value for bitfield FTM_FLTCTRL_FFLTR1EN.
+#define BF_FTM_FLTCTRL_FFLTR1EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FFLTR1EN), uint32_t) & BM_FTM_FLTCTRL_FFLTR1EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FFLTR1EN field to a new value.
+#define BW_FTM_FLTCTRL_FFLTR1EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR1EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR2EN[6] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Fault input filter is disabled.
+ * - 1 - Fault input filter is enabled.
+ */
+//@{
+#define BP_FTM_FLTCTRL_FFLTR2EN (6U) //!< Bit position for FTM_FLTCTRL_FFLTR2EN.
+#define BM_FTM_FLTCTRL_FFLTR2EN (0x00000040U) //!< Bit mask for FTM_FLTCTRL_FFLTR2EN.
+#define BS_FTM_FLTCTRL_FFLTR2EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FFLTR2EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FLTCTRL_FFLTR2EN field.
+#define BR_FTM_FLTCTRL_FFLTR2EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR2EN))
+#endif
+
+//! @brief Format value for bitfield FTM_FLTCTRL_FFLTR2EN.
+#define BF_FTM_FLTCTRL_FFLTR2EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FFLTR2EN), uint32_t) & BM_FTM_FLTCTRL_FFLTR2EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FFLTR2EN field to a new value.
+#define BW_FTM_FLTCTRL_FFLTR2EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR2EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR3EN[7] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Fault input filter is disabled.
+ * - 1 - Fault input filter is enabled.
+ */
+//@{
+#define BP_FTM_FLTCTRL_FFLTR3EN (7U) //!< Bit position for FTM_FLTCTRL_FFLTR3EN.
+#define BM_FTM_FLTCTRL_FFLTR3EN (0x00000080U) //!< Bit mask for FTM_FLTCTRL_FFLTR3EN.
+#define BS_FTM_FLTCTRL_FFLTR3EN (1U) //!< Bit field size in bits for FTM_FLTCTRL_FFLTR3EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FLTCTRL_FFLTR3EN field.
+#define BR_FTM_FLTCTRL_FFLTR3EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR3EN))
+#endif
+
+//! @brief Format value for bitfield FTM_FLTCTRL_FFLTR3EN.
+#define BF_FTM_FLTCTRL_FFLTR3EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FFLTR3EN), uint32_t) & BM_FTM_FLTCTRL_FFLTR3EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FFLTR3EN field to a new value.
+#define BW_FTM_FLTCTRL_FFLTR3EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR3EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFVAL[11:8] (RW)
+ *
+ * Selects the filter value for the fault inputs. The fault filter is disabled
+ * when the value is zero. Writing to this field has immediate effect and must be
+ * done only when the fault control or all fault inputs are disabled. Failure to
+ * do this could result in a missing fault detection.
+ */
+//@{
+#define BP_FTM_FLTCTRL_FFVAL (8U) //!< Bit position for FTM_FLTCTRL_FFVAL.
+#define BM_FTM_FLTCTRL_FFVAL (0x00000F00U) //!< Bit mask for FTM_FLTCTRL_FFVAL.
+#define BS_FTM_FLTCTRL_FFVAL (4U) //!< Bit field size in bits for FTM_FLTCTRL_FFVAL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FLTCTRL_FFVAL field.
+#define BR_FTM_FLTCTRL_FFVAL(x) (HW_FTM_FLTCTRL(x).B.FFVAL)
+#endif
+
+//! @brief Format value for bitfield FTM_FLTCTRL_FFVAL.
+#define BF_FTM_FLTCTRL_FFVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTCTRL_FFVAL), uint32_t) & BM_FTM_FLTCTRL_FFVAL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FFVAL field to a new value.
+#define BW_FTM_FLTCTRL_FFVAL(x, v) (HW_FTM_FLTCTRL_WR(x, (HW_FTM_FLTCTRL_RD(x) & ~BM_FTM_FLTCTRL_FFVAL) | BF_FTM_FLTCTRL_FFVAL(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_QDCTRL - Quadrature Decoder Control And Status
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_QDCTRL - Quadrature Decoder Control And Status (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register has the control and status bits for the Quadrature Decoder mode.
+ */
+typedef union _hw_ftm_qdctrl
+{
+ uint32_t U;
+ struct _hw_ftm_qdctrl_bitfields
+ {
+ uint32_t QUADEN : 1; //!< [0] Quadrature Decoder Mode Enable
+ uint32_t TOFDIR : 1; //!< [1] Timer Overflow Direction In Quadrature
+ //! Decoder Mode
+ uint32_t QUADIR : 1; //!< [2] FTM Counter Direction In Quadrature
+ //! Decoder Mode
+ uint32_t QUADMODE : 1; //!< [3] Quadrature Decoder Mode
+ uint32_t PHBPOL : 1; //!< [4] Phase B Input Polarity
+ uint32_t PHAPOL : 1; //!< [5] Phase A Input Polarity
+ uint32_t PHBFLTREN : 1; //!< [6] Phase B Input Filter Enable
+ uint32_t PHAFLTREN : 1; //!< [7] Phase A Input Filter Enable
+ uint32_t RESERVED0 : 24; //!< [31:8]
+ } B;
+} hw_ftm_qdctrl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_QDCTRL register
+ */
+//@{
+#define HW_FTM_QDCTRL_ADDR(x) (REGS_FTM_BASE(x) + 0x80U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_QDCTRL(x) (*(__IO hw_ftm_qdctrl_t *) HW_FTM_QDCTRL_ADDR(x))
+#define HW_FTM_QDCTRL_RD(x) (HW_FTM_QDCTRL(x).U)
+#define HW_FTM_QDCTRL_WR(x, v) (HW_FTM_QDCTRL(x).U = (v))
+#define HW_FTM_QDCTRL_SET(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) | (v)))
+#define HW_FTM_QDCTRL_CLR(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) & ~(v)))
+#define HW_FTM_QDCTRL_TOG(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_QDCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_QDCTRL, field QUADEN[0] (RW)
+ *
+ * Enables the Quadrature Decoder mode. In this mode, the phase A and B input
+ * signals control the FTM counter direction. The Quadrature Decoder mode has
+ * precedence over the other modes. See #ModeSel1Table. This field is write protected.
+ * It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - Quadrature Decoder mode is disabled.
+ * - 1 - Quadrature Decoder mode is enabled.
+ */
+//@{
+#define BP_FTM_QDCTRL_QUADEN (0U) //!< Bit position for FTM_QDCTRL_QUADEN.
+#define BM_FTM_QDCTRL_QUADEN (0x00000001U) //!< Bit mask for FTM_QDCTRL_QUADEN.
+#define BS_FTM_QDCTRL_QUADEN (1U) //!< Bit field size in bits for FTM_QDCTRL_QUADEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_QDCTRL_QUADEN field.
+#define BR_FTM_QDCTRL_QUADEN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADEN))
+#endif
+
+//! @brief Format value for bitfield FTM_QDCTRL_QUADEN.
+#define BF_FTM_QDCTRL_QUADEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_QUADEN), uint32_t) & BM_FTM_QDCTRL_QUADEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the QUADEN field to a new value.
+#define BW_FTM_QDCTRL_QUADEN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_QDCTRL, field TOFDIR[1] (RO)
+ *
+ * Indicates if the TOF bit was set on the top or the bottom of counting.
+ *
+ * Values:
+ * - 0 - TOF bit was set on the bottom of counting. There was an FTM counter
+ * decrement and FTM counter changes from its minimum value (CNTIN register) to
+ * its maximum value (MOD register).
+ * - 1 - TOF bit was set on the top of counting. There was an FTM counter
+ * increment and FTM counter changes from its maximum value (MOD register) to its
+ * minimum value (CNTIN register).
+ */
+//@{
+#define BP_FTM_QDCTRL_TOFDIR (1U) //!< Bit position for FTM_QDCTRL_TOFDIR.
+#define BM_FTM_QDCTRL_TOFDIR (0x00000002U) //!< Bit mask for FTM_QDCTRL_TOFDIR.
+#define BS_FTM_QDCTRL_TOFDIR (1U) //!< Bit field size in bits for FTM_QDCTRL_TOFDIR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_QDCTRL_TOFDIR field.
+#define BR_FTM_QDCTRL_TOFDIR(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_TOFDIR))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_QDCTRL, field QUADIR[2] (RO)
+ *
+ * Indicates the counting direction.
+ *
+ * Values:
+ * - 0 - Counting direction is decreasing (FTM counter decrement).
+ * - 1 - Counting direction is increasing (FTM counter increment).
+ */
+//@{
+#define BP_FTM_QDCTRL_QUADIR (2U) //!< Bit position for FTM_QDCTRL_QUADIR.
+#define BM_FTM_QDCTRL_QUADIR (0x00000004U) //!< Bit mask for FTM_QDCTRL_QUADIR.
+#define BS_FTM_QDCTRL_QUADIR (1U) //!< Bit field size in bits for FTM_QDCTRL_QUADIR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_QDCTRL_QUADIR field.
+#define BR_FTM_QDCTRL_QUADIR(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADIR))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_QDCTRL, field QUADMODE[3] (RW)
+ *
+ * Selects the encoding mode used in the Quadrature Decoder mode.
+ *
+ * Values:
+ * - 0 - Phase A and phase B encoding mode.
+ * - 1 - Count and direction encoding mode.
+ */
+//@{
+#define BP_FTM_QDCTRL_QUADMODE (3U) //!< Bit position for FTM_QDCTRL_QUADMODE.
+#define BM_FTM_QDCTRL_QUADMODE (0x00000008U) //!< Bit mask for FTM_QDCTRL_QUADMODE.
+#define BS_FTM_QDCTRL_QUADMODE (1U) //!< Bit field size in bits for FTM_QDCTRL_QUADMODE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_QDCTRL_QUADMODE field.
+#define BR_FTM_QDCTRL_QUADMODE(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADMODE))
+#endif
+
+//! @brief Format value for bitfield FTM_QDCTRL_QUADMODE.
+#define BF_FTM_QDCTRL_QUADMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_QUADMODE), uint32_t) & BM_FTM_QDCTRL_QUADMODE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the QUADMODE field to a new value.
+#define BW_FTM_QDCTRL_QUADMODE(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADMODE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_QDCTRL, field PHBPOL[4] (RW)
+ *
+ * Selects the polarity for the quadrature decoder phase B input.
+ *
+ * Values:
+ * - 0 - Normal polarity. Phase B input signal is not inverted before
+ * identifying the rising and falling edges of this signal.
+ * - 1 - Inverted polarity. Phase B input signal is inverted before identifying
+ * the rising and falling edges of this signal.
+ */
+//@{
+#define BP_FTM_QDCTRL_PHBPOL (4U) //!< Bit position for FTM_QDCTRL_PHBPOL.
+#define BM_FTM_QDCTRL_PHBPOL (0x00000010U) //!< Bit mask for FTM_QDCTRL_PHBPOL.
+#define BS_FTM_QDCTRL_PHBPOL (1U) //!< Bit field size in bits for FTM_QDCTRL_PHBPOL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_QDCTRL_PHBPOL field.
+#define BR_FTM_QDCTRL_PHBPOL(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBPOL))
+#endif
+
+//! @brief Format value for bitfield FTM_QDCTRL_PHBPOL.
+#define BF_FTM_QDCTRL_PHBPOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_PHBPOL), uint32_t) & BM_FTM_QDCTRL_PHBPOL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PHBPOL field to a new value.
+#define BW_FTM_QDCTRL_PHBPOL(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBPOL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_QDCTRL, field PHAPOL[5] (RW)
+ *
+ * Selects the polarity for the quadrature decoder phase A input.
+ *
+ * Values:
+ * - 0 - Normal polarity. Phase A input signal is not inverted before
+ * identifying the rising and falling edges of this signal.
+ * - 1 - Inverted polarity. Phase A input signal is inverted before identifying
+ * the rising and falling edges of this signal.
+ */
+//@{
+#define BP_FTM_QDCTRL_PHAPOL (5U) //!< Bit position for FTM_QDCTRL_PHAPOL.
+#define BM_FTM_QDCTRL_PHAPOL (0x00000020U) //!< Bit mask for FTM_QDCTRL_PHAPOL.
+#define BS_FTM_QDCTRL_PHAPOL (1U) //!< Bit field size in bits for FTM_QDCTRL_PHAPOL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_QDCTRL_PHAPOL field.
+#define BR_FTM_QDCTRL_PHAPOL(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAPOL))
+#endif
+
+//! @brief Format value for bitfield FTM_QDCTRL_PHAPOL.
+#define BF_FTM_QDCTRL_PHAPOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_PHAPOL), uint32_t) & BM_FTM_QDCTRL_PHAPOL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PHAPOL field to a new value.
+#define BW_FTM_QDCTRL_PHAPOL(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAPOL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_QDCTRL, field PHBFLTREN[6] (RW)
+ *
+ * Enables the filter for the quadrature decoder phase B input. The filter value
+ * for the phase B input is defined by the CH1FVAL field of FILTER. The phase B
+ * filter is also disabled when CH1FVAL is zero.
+ *
+ * Values:
+ * - 0 - Phase B input filter is disabled.
+ * - 1 - Phase B input filter is enabled.
+ */
+//@{
+#define BP_FTM_QDCTRL_PHBFLTREN (6U) //!< Bit position for FTM_QDCTRL_PHBFLTREN.
+#define BM_FTM_QDCTRL_PHBFLTREN (0x00000040U) //!< Bit mask for FTM_QDCTRL_PHBFLTREN.
+#define BS_FTM_QDCTRL_PHBFLTREN (1U) //!< Bit field size in bits for FTM_QDCTRL_PHBFLTREN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_QDCTRL_PHBFLTREN field.
+#define BR_FTM_QDCTRL_PHBFLTREN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBFLTREN))
+#endif
+
+//! @brief Format value for bitfield FTM_QDCTRL_PHBFLTREN.
+#define BF_FTM_QDCTRL_PHBFLTREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_PHBFLTREN), uint32_t) & BM_FTM_QDCTRL_PHBFLTREN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PHBFLTREN field to a new value.
+#define BW_FTM_QDCTRL_PHBFLTREN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBFLTREN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_QDCTRL, field PHAFLTREN[7] (RW)
+ *
+ * Enables the filter for the quadrature decoder phase A input. The filter value
+ * for the phase A input is defined by the CH0FVAL field of FILTER. The phase A
+ * filter is also disabled when CH0FVAL is zero.
+ *
+ * Values:
+ * - 0 - Phase A input filter is disabled.
+ * - 1 - Phase A input filter is enabled.
+ */
+//@{
+#define BP_FTM_QDCTRL_PHAFLTREN (7U) //!< Bit position for FTM_QDCTRL_PHAFLTREN.
+#define BM_FTM_QDCTRL_PHAFLTREN (0x00000080U) //!< Bit mask for FTM_QDCTRL_PHAFLTREN.
+#define BS_FTM_QDCTRL_PHAFLTREN (1U) //!< Bit field size in bits for FTM_QDCTRL_PHAFLTREN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_QDCTRL_PHAFLTREN field.
+#define BR_FTM_QDCTRL_PHAFLTREN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAFLTREN))
+#endif
+
+//! @brief Format value for bitfield FTM_QDCTRL_PHAFLTREN.
+#define BF_FTM_QDCTRL_PHAFLTREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_QDCTRL_PHAFLTREN), uint32_t) & BM_FTM_QDCTRL_PHAFLTREN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PHAFLTREN field to a new value.
+#define BW_FTM_QDCTRL_PHAFLTREN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAFLTREN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_CONF - Configuration
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_CONF - Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the number of times that the FTM counter overflow
+ * should occur before the TOF bit to be set, the FTM behavior in BDM modes, the use
+ * of an external global time base, and the global time base signal generation.
+ */
+typedef union _hw_ftm_conf
+{
+ uint32_t U;
+ struct _hw_ftm_conf_bitfields
+ {
+ uint32_t NUMTOF : 5; //!< [4:0] TOF Frequency
+ uint32_t RESERVED0 : 1; //!< [5]
+ uint32_t BDMMODE : 2; //!< [7:6] BDM Mode
+ uint32_t RESERVED1 : 1; //!< [8]
+ uint32_t GTBEEN : 1; //!< [9] Global Time Base Enable
+ uint32_t GTBEOUT : 1; //!< [10] Global Time Base Output
+ uint32_t RESERVED2 : 21; //!< [31:11]
+ } B;
+} hw_ftm_conf_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_CONF register
+ */
+//@{
+#define HW_FTM_CONF_ADDR(x) (REGS_FTM_BASE(x) + 0x84U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_CONF(x) (*(__IO hw_ftm_conf_t *) HW_FTM_CONF_ADDR(x))
+#define HW_FTM_CONF_RD(x) (HW_FTM_CONF(x).U)
+#define HW_FTM_CONF_WR(x, v) (HW_FTM_CONF(x).U = (v))
+#define HW_FTM_CONF_SET(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) | (v)))
+#define HW_FTM_CONF_CLR(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) & ~(v)))
+#define HW_FTM_CONF_TOG(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_CONF bitfields
+ */
+
+/*!
+ * @name Register FTM_CONF, field NUMTOF[4:0] (RW)
+ *
+ * Selects the ratio between the number of counter overflows to the number of
+ * times the TOF bit is set. NUMTOF = 0: The TOF bit is set for each counter
+ * overflow. NUMTOF = 1: The TOF bit is set for the first counter overflow but not for
+ * the next overflow. NUMTOF = 2: The TOF bit is set for the first counter
+ * overflow but not for the next 2 overflows. NUMTOF = 3: The TOF bit is set for the
+ * first counter overflow but not for the next 3 overflows. This pattern continues
+ * up to a maximum of 31.
+ */
+//@{
+#define BP_FTM_CONF_NUMTOF (0U) //!< Bit position for FTM_CONF_NUMTOF.
+#define BM_FTM_CONF_NUMTOF (0x0000001FU) //!< Bit mask for FTM_CONF_NUMTOF.
+#define BS_FTM_CONF_NUMTOF (5U) //!< Bit field size in bits for FTM_CONF_NUMTOF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_CONF_NUMTOF field.
+#define BR_FTM_CONF_NUMTOF(x) (HW_FTM_CONF(x).B.NUMTOF)
+#endif
+
+//! @brief Format value for bitfield FTM_CONF_NUMTOF.
+#define BF_FTM_CONF_NUMTOF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CONF_NUMTOF), uint32_t) & BM_FTM_CONF_NUMTOF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NUMTOF field to a new value.
+#define BW_FTM_CONF_NUMTOF(x, v) (HW_FTM_CONF_WR(x, (HW_FTM_CONF_RD(x) & ~BM_FTM_CONF_NUMTOF) | BF_FTM_CONF_NUMTOF(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_CONF, field BDMMODE[7:6] (RW)
+ *
+ * Selects the FTM behavior in BDM mode. See BDM mode.
+ */
+//@{
+#define BP_FTM_CONF_BDMMODE (6U) //!< Bit position for FTM_CONF_BDMMODE.
+#define BM_FTM_CONF_BDMMODE (0x000000C0U) //!< Bit mask for FTM_CONF_BDMMODE.
+#define BS_FTM_CONF_BDMMODE (2U) //!< Bit field size in bits for FTM_CONF_BDMMODE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_CONF_BDMMODE field.
+#define BR_FTM_CONF_BDMMODE(x) (HW_FTM_CONF(x).B.BDMMODE)
+#endif
+
+//! @brief Format value for bitfield FTM_CONF_BDMMODE.
+#define BF_FTM_CONF_BDMMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CONF_BDMMODE), uint32_t) & BM_FTM_CONF_BDMMODE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BDMMODE field to a new value.
+#define BW_FTM_CONF_BDMMODE(x, v) (HW_FTM_CONF_WR(x, (HW_FTM_CONF_RD(x) & ~BM_FTM_CONF_BDMMODE) | BF_FTM_CONF_BDMMODE(v)))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_CONF, field GTBEEN[9] (RW)
+ *
+ * Configures the FTM to use an external global time base signal that is
+ * generated by another FTM.
+ *
+ * Values:
+ * - 0 - Use of an external global time base is disabled.
+ * - 1 - Use of an external global time base is enabled.
+ */
+//@{
+#define BP_FTM_CONF_GTBEEN (9U) //!< Bit position for FTM_CONF_GTBEEN.
+#define BM_FTM_CONF_GTBEEN (0x00000200U) //!< Bit mask for FTM_CONF_GTBEEN.
+#define BS_FTM_CONF_GTBEEN (1U) //!< Bit field size in bits for FTM_CONF_GTBEEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_CONF_GTBEEN field.
+#define BR_FTM_CONF_GTBEEN(x) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEEN))
+#endif
+
+//! @brief Format value for bitfield FTM_CONF_GTBEEN.
+#define BF_FTM_CONF_GTBEEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CONF_GTBEEN), uint32_t) & BM_FTM_CONF_GTBEEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GTBEEN field to a new value.
+#define BW_FTM_CONF_GTBEEN(x, v) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_CONF, field GTBEOUT[10] (RW)
+ *
+ * Enables the global time base signal generation to other FTMs.
+ *
+ * Values:
+ * - 0 - A global time base signal generation is disabled.
+ * - 1 - A global time base signal generation is enabled.
+ */
+//@{
+#define BP_FTM_CONF_GTBEOUT (10U) //!< Bit position for FTM_CONF_GTBEOUT.
+#define BM_FTM_CONF_GTBEOUT (0x00000400U) //!< Bit mask for FTM_CONF_GTBEOUT.
+#define BS_FTM_CONF_GTBEOUT (1U) //!< Bit field size in bits for FTM_CONF_GTBEOUT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_CONF_GTBEOUT field.
+#define BR_FTM_CONF_GTBEOUT(x) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEOUT))
+#endif
+
+//! @brief Format value for bitfield FTM_CONF_GTBEOUT.
+#define BF_FTM_CONF_GTBEOUT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_CONF_GTBEOUT), uint32_t) & BM_FTM_CONF_GTBEOUT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GTBEOUT field to a new value.
+#define BW_FTM_CONF_GTBEOUT(x, v) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEOUT) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_FLTPOL - FTM Fault Input Polarity
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_FLTPOL - FTM Fault Input Polarity (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register defines the fault inputs polarity.
+ */
+typedef union _hw_ftm_fltpol
+{
+ uint32_t U;
+ struct _hw_ftm_fltpol_bitfields
+ {
+ uint32_t FLT0POL : 1; //!< [0] Fault Input 0 Polarity
+ uint32_t FLT1POL : 1; //!< [1] Fault Input 1 Polarity
+ uint32_t FLT2POL : 1; //!< [2] Fault Input 2 Polarity
+ uint32_t FLT3POL : 1; //!< [3] Fault Input 3 Polarity
+ uint32_t RESERVED0 : 28; //!< [31:4]
+ } B;
+} hw_ftm_fltpol_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_FLTPOL register
+ */
+//@{
+#define HW_FTM_FLTPOL_ADDR(x) (REGS_FTM_BASE(x) + 0x88U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_FLTPOL(x) (*(__IO hw_ftm_fltpol_t *) HW_FTM_FLTPOL_ADDR(x))
+#define HW_FTM_FLTPOL_RD(x) (HW_FTM_FLTPOL(x).U)
+#define HW_FTM_FLTPOL_WR(x, v) (HW_FTM_FLTPOL(x).U = (v))
+#define HW_FTM_FLTPOL_SET(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) | (v)))
+#define HW_FTM_FLTPOL_CLR(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) & ~(v)))
+#define HW_FTM_FLTPOL_TOG(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_FLTPOL bitfields
+ */
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT0POL[0] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The fault input polarity is active high. A 1 at the fault input
+ * indicates a fault.
+ * - 1 - The fault input polarity is active low. A 0 at the fault input
+ * indicates a fault.
+ */
+//@{
+#define BP_FTM_FLTPOL_FLT0POL (0U) //!< Bit position for FTM_FLTPOL_FLT0POL.
+#define BM_FTM_FLTPOL_FLT0POL (0x00000001U) //!< Bit mask for FTM_FLTPOL_FLT0POL.
+#define BS_FTM_FLTPOL_FLT0POL (1U) //!< Bit field size in bits for FTM_FLTPOL_FLT0POL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FLTPOL_FLT0POL field.
+#define BR_FTM_FLTPOL_FLT0POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT0POL))
+#endif
+
+//! @brief Format value for bitfield FTM_FLTPOL_FLT0POL.
+#define BF_FTM_FLTPOL_FLT0POL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTPOL_FLT0POL), uint32_t) & BM_FTM_FLTPOL_FLT0POL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FLT0POL field to a new value.
+#define BW_FTM_FLTPOL_FLT0POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT0POL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT1POL[1] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The fault input polarity is active high. A 1 at the fault input
+ * indicates a fault.
+ * - 1 - The fault input polarity is active low. A 0 at the fault input
+ * indicates a fault.
+ */
+//@{
+#define BP_FTM_FLTPOL_FLT1POL (1U) //!< Bit position for FTM_FLTPOL_FLT1POL.
+#define BM_FTM_FLTPOL_FLT1POL (0x00000002U) //!< Bit mask for FTM_FLTPOL_FLT1POL.
+#define BS_FTM_FLTPOL_FLT1POL (1U) //!< Bit field size in bits for FTM_FLTPOL_FLT1POL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FLTPOL_FLT1POL field.
+#define BR_FTM_FLTPOL_FLT1POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT1POL))
+#endif
+
+//! @brief Format value for bitfield FTM_FLTPOL_FLT1POL.
+#define BF_FTM_FLTPOL_FLT1POL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTPOL_FLT1POL), uint32_t) & BM_FTM_FLTPOL_FLT1POL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FLT1POL field to a new value.
+#define BW_FTM_FLTPOL_FLT1POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT1POL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT2POL[2] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The fault input polarity is active high. A 1 at the fault input
+ * indicates a fault.
+ * - 1 - The fault input polarity is active low. A 0 at the fault input
+ * indicates a fault.
+ */
+//@{
+#define BP_FTM_FLTPOL_FLT2POL (2U) //!< Bit position for FTM_FLTPOL_FLT2POL.
+#define BM_FTM_FLTPOL_FLT2POL (0x00000004U) //!< Bit mask for FTM_FLTPOL_FLT2POL.
+#define BS_FTM_FLTPOL_FLT2POL (1U) //!< Bit field size in bits for FTM_FLTPOL_FLT2POL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FLTPOL_FLT2POL field.
+#define BR_FTM_FLTPOL_FLT2POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT2POL))
+#endif
+
+//! @brief Format value for bitfield FTM_FLTPOL_FLT2POL.
+#define BF_FTM_FLTPOL_FLT2POL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTPOL_FLT2POL), uint32_t) & BM_FTM_FLTPOL_FLT2POL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FLT2POL field to a new value.
+#define BW_FTM_FLTPOL_FLT2POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT2POL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT3POL[3] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0 - The fault input polarity is active high. A 1 at the fault input
+ * indicates a fault.
+ * - 1 - The fault input polarity is active low. A 0 at the fault input
+ * indicates a fault.
+ */
+//@{
+#define BP_FTM_FLTPOL_FLT3POL (3U) //!< Bit position for FTM_FLTPOL_FLT3POL.
+#define BM_FTM_FLTPOL_FLT3POL (0x00000008U) //!< Bit mask for FTM_FLTPOL_FLT3POL.
+#define BS_FTM_FLTPOL_FLT3POL (1U) //!< Bit field size in bits for FTM_FLTPOL_FLT3POL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_FLTPOL_FLT3POL field.
+#define BR_FTM_FLTPOL_FLT3POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT3POL))
+#endif
+
+//! @brief Format value for bitfield FTM_FLTPOL_FLT3POL.
+#define BF_FTM_FLTPOL_FLT3POL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_FLTPOL_FLT3POL), uint32_t) & BM_FTM_FLTPOL_FLT3POL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FLT3POL field to a new value.
+#define BW_FTM_FLTPOL_FLT3POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT3POL) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_SYNCONF - Synchronization Configuration
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_SYNCONF - Synchronization Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the PWM synchronization configuration, SWOCTRL, INVCTRL
+ * and CNTIN registers synchronization, if FTM clears the TRIGj bit, where j =
+ * 0, 1, 2, when the hardware trigger j is detected.
+ */
+typedef union _hw_ftm_synconf
+{
+ uint32_t U;
+ struct _hw_ftm_synconf_bitfields
+ {
+ uint32_t HWTRIGMODE : 1; //!< [0] Hardware Trigger Mode
+ uint32_t RESERVED0 : 1; //!< [1]
+ uint32_t CNTINC : 1; //!< [2] CNTIN Register Synchronization
+ uint32_t RESERVED1 : 1; //!< [3]
+ uint32_t INVC : 1; //!< [4] INVCTRL Register Synchronization
+ uint32_t SWOC : 1; //!< [5] SWOCTRL Register Synchronization
+ uint32_t RESERVED2 : 1; //!< [6]
+ uint32_t SYNCMODE : 1; //!< [7] Synchronization Mode
+ uint32_t SWRSTCNT : 1; //!< [8]
+ uint32_t SWWRBUF : 1; //!< [9]
+ uint32_t SWOM : 1; //!< [10]
+ uint32_t SWINVC : 1; //!< [11]
+ uint32_t SWSOC : 1; //!< [12]
+ uint32_t RESERVED3 : 3; //!< [15:13]
+ uint32_t HWRSTCNT : 1; //!< [16]
+ uint32_t HWWRBUF : 1; //!< [17]
+ uint32_t HWOM : 1; //!< [18]
+ uint32_t HWINVC : 1; //!< [19]
+ uint32_t HWSOC : 1; //!< [20]
+ uint32_t RESERVED4 : 11; //!< [31:21]
+ } B;
+} hw_ftm_synconf_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_SYNCONF register
+ */
+//@{
+#define HW_FTM_SYNCONF_ADDR(x) (REGS_FTM_BASE(x) + 0x8CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_SYNCONF(x) (*(__IO hw_ftm_synconf_t *) HW_FTM_SYNCONF_ADDR(x))
+#define HW_FTM_SYNCONF_RD(x) (HW_FTM_SYNCONF(x).U)
+#define HW_FTM_SYNCONF_WR(x, v) (HW_FTM_SYNCONF(x).U = (v))
+#define HW_FTM_SYNCONF_SET(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) | (v)))
+#define HW_FTM_SYNCONF_CLR(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) & ~(v)))
+#define HW_FTM_SYNCONF_TOG(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_SYNCONF bitfields
+ */
+
+/*!
+ * @name Register FTM_SYNCONF, field HWTRIGMODE[0] (RW)
+ *
+ * Values:
+ * - 0 - FTM clears the TRIGj bit when the hardware trigger j is detected, where
+ * j = 0, 1,2.
+ * - 1 - FTM does not clear the TRIGj bit when the hardware trigger j is
+ * detected, where j = 0, 1,2.
+ */
+//@{
+#define BP_FTM_SYNCONF_HWTRIGMODE (0U) //!< Bit position for FTM_SYNCONF_HWTRIGMODE.
+#define BM_FTM_SYNCONF_HWTRIGMODE (0x00000001U) //!< Bit mask for FTM_SYNCONF_HWTRIGMODE.
+#define BS_FTM_SYNCONF_HWTRIGMODE (1U) //!< Bit field size in bits for FTM_SYNCONF_HWTRIGMODE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_HWTRIGMODE field.
+#define BR_FTM_SYNCONF_HWTRIGMODE(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWTRIGMODE))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_HWTRIGMODE.
+#define BF_FTM_SYNCONF_HWTRIGMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWTRIGMODE), uint32_t) & BM_FTM_SYNCONF_HWTRIGMODE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HWTRIGMODE field to a new value.
+#define BW_FTM_SYNCONF_HWTRIGMODE(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWTRIGMODE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNCONF, field CNTINC[2] (RW)
+ *
+ * Values:
+ * - 0 - CNTIN register is updated with its buffer value at all rising edges of
+ * system clock.
+ * - 1 - CNTIN register is updated with its buffer value by the PWM
+ * synchronization.
+ */
+//@{
+#define BP_FTM_SYNCONF_CNTINC (2U) //!< Bit position for FTM_SYNCONF_CNTINC.
+#define BM_FTM_SYNCONF_CNTINC (0x00000004U) //!< Bit mask for FTM_SYNCONF_CNTINC.
+#define BS_FTM_SYNCONF_CNTINC (1U) //!< Bit field size in bits for FTM_SYNCONF_CNTINC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_CNTINC field.
+#define BR_FTM_SYNCONF_CNTINC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_CNTINC))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_CNTINC.
+#define BF_FTM_SYNCONF_CNTINC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_CNTINC), uint32_t) & BM_FTM_SYNCONF_CNTINC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CNTINC field to a new value.
+#define BW_FTM_SYNCONF_CNTINC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_CNTINC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNCONF, field INVC[4] (RW)
+ *
+ * Values:
+ * - 0 - INVCTRL register is updated with its buffer value at all rising edges
+ * of system clock.
+ * - 1 - INVCTRL register is updated with its buffer value by the PWM
+ * synchronization.
+ */
+//@{
+#define BP_FTM_SYNCONF_INVC (4U) //!< Bit position for FTM_SYNCONF_INVC.
+#define BM_FTM_SYNCONF_INVC (0x00000010U) //!< Bit mask for FTM_SYNCONF_INVC.
+#define BS_FTM_SYNCONF_INVC (1U) //!< Bit field size in bits for FTM_SYNCONF_INVC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_INVC field.
+#define BR_FTM_SYNCONF_INVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_INVC))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_INVC.
+#define BF_FTM_SYNCONF_INVC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_INVC), uint32_t) & BM_FTM_SYNCONF_INVC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INVC field to a new value.
+#define BW_FTM_SYNCONF_INVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_INVC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNCONF, field SWOC[5] (RW)
+ *
+ * Values:
+ * - 0 - SWOCTRL register is updated with its buffer value at all rising edges
+ * of system clock.
+ * - 1 - SWOCTRL register is updated with its buffer value by the PWM
+ * synchronization.
+ */
+//@{
+#define BP_FTM_SYNCONF_SWOC (5U) //!< Bit position for FTM_SYNCONF_SWOC.
+#define BM_FTM_SYNCONF_SWOC (0x00000020U) //!< Bit mask for FTM_SYNCONF_SWOC.
+#define BS_FTM_SYNCONF_SWOC (1U) //!< Bit field size in bits for FTM_SYNCONF_SWOC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_SWOC field.
+#define BR_FTM_SYNCONF_SWOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOC))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_SWOC.
+#define BF_FTM_SYNCONF_SWOC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWOC), uint32_t) & BM_FTM_SYNCONF_SWOC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SWOC field to a new value.
+#define BW_FTM_SYNCONF_SWOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNCONF, field SYNCMODE[7] (RW)
+ *
+ * Selects the PWM Synchronization mode.
+ *
+ * Values:
+ * - 0 - Legacy PWM synchronization is selected.
+ * - 1 - Enhanced PWM synchronization is selected.
+ */
+//@{
+#define BP_FTM_SYNCONF_SYNCMODE (7U) //!< Bit position for FTM_SYNCONF_SYNCMODE.
+#define BM_FTM_SYNCONF_SYNCMODE (0x00000080U) //!< Bit mask for FTM_SYNCONF_SYNCMODE.
+#define BS_FTM_SYNCONF_SYNCMODE (1U) //!< Bit field size in bits for FTM_SYNCONF_SYNCMODE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_SYNCMODE field.
+#define BR_FTM_SYNCONF_SYNCMODE(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SYNCMODE))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_SYNCMODE.
+#define BF_FTM_SYNCONF_SYNCMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SYNCMODE), uint32_t) & BM_FTM_SYNCONF_SYNCMODE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SYNCMODE field to a new value.
+#define BW_FTM_SYNCONF_SYNCMODE(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SYNCMODE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNCONF, field SWRSTCNT[8] (RW)
+ *
+ * FTM counter synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0 - The software trigger does not activate the FTM counter synchronization.
+ * - 1 - The software trigger activates the FTM counter synchronization.
+ */
+//@{
+#define BP_FTM_SYNCONF_SWRSTCNT (8U) //!< Bit position for FTM_SYNCONF_SWRSTCNT.
+#define BM_FTM_SYNCONF_SWRSTCNT (0x00000100U) //!< Bit mask for FTM_SYNCONF_SWRSTCNT.
+#define BS_FTM_SYNCONF_SWRSTCNT (1U) //!< Bit field size in bits for FTM_SYNCONF_SWRSTCNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_SWRSTCNT field.
+#define BR_FTM_SYNCONF_SWRSTCNT(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWRSTCNT))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_SWRSTCNT.
+#define BF_FTM_SYNCONF_SWRSTCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWRSTCNT), uint32_t) & BM_FTM_SYNCONF_SWRSTCNT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SWRSTCNT field to a new value.
+#define BW_FTM_SYNCONF_SWRSTCNT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWRSTCNT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNCONF, field SWWRBUF[9] (RW)
+ *
+ * MOD, CNTIN, and CV registers synchronization is activated by the software
+ * trigger.
+ *
+ * Values:
+ * - 0 - The software trigger does not activate MOD, CNTIN, and CV registers
+ * synchronization.
+ * - 1 - The software trigger activates MOD, CNTIN, and CV registers
+ * synchronization.
+ */
+//@{
+#define BP_FTM_SYNCONF_SWWRBUF (9U) //!< Bit position for FTM_SYNCONF_SWWRBUF.
+#define BM_FTM_SYNCONF_SWWRBUF (0x00000200U) //!< Bit mask for FTM_SYNCONF_SWWRBUF.
+#define BS_FTM_SYNCONF_SWWRBUF (1U) //!< Bit field size in bits for FTM_SYNCONF_SWWRBUF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_SWWRBUF field.
+#define BR_FTM_SYNCONF_SWWRBUF(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWWRBUF))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_SWWRBUF.
+#define BF_FTM_SYNCONF_SWWRBUF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWWRBUF), uint32_t) & BM_FTM_SYNCONF_SWWRBUF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SWWRBUF field to a new value.
+#define BW_FTM_SYNCONF_SWWRBUF(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWWRBUF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNCONF, field SWOM[10] (RW)
+ *
+ * Output mask synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0 - The software trigger does not activate the OUTMASK register
+ * synchronization.
+ * - 1 - The software trigger activates the OUTMASK register synchronization.
+ */
+//@{
+#define BP_FTM_SYNCONF_SWOM (10U) //!< Bit position for FTM_SYNCONF_SWOM.
+#define BM_FTM_SYNCONF_SWOM (0x00000400U) //!< Bit mask for FTM_SYNCONF_SWOM.
+#define BS_FTM_SYNCONF_SWOM (1U) //!< Bit field size in bits for FTM_SYNCONF_SWOM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_SWOM field.
+#define BR_FTM_SYNCONF_SWOM(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOM))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_SWOM.
+#define BF_FTM_SYNCONF_SWOM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWOM), uint32_t) & BM_FTM_SYNCONF_SWOM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SWOM field to a new value.
+#define BW_FTM_SYNCONF_SWOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNCONF, field SWINVC[11] (RW)
+ *
+ * Inverting control synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0 - The software trigger does not activate the INVCTRL register
+ * synchronization.
+ * - 1 - The software trigger activates the INVCTRL register synchronization.
+ */
+//@{
+#define BP_FTM_SYNCONF_SWINVC (11U) //!< Bit position for FTM_SYNCONF_SWINVC.
+#define BM_FTM_SYNCONF_SWINVC (0x00000800U) //!< Bit mask for FTM_SYNCONF_SWINVC.
+#define BS_FTM_SYNCONF_SWINVC (1U) //!< Bit field size in bits for FTM_SYNCONF_SWINVC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_SWINVC field.
+#define BR_FTM_SYNCONF_SWINVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWINVC))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_SWINVC.
+#define BF_FTM_SYNCONF_SWINVC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWINVC), uint32_t) & BM_FTM_SYNCONF_SWINVC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SWINVC field to a new value.
+#define BW_FTM_SYNCONF_SWINVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWINVC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNCONF, field SWSOC[12] (RW)
+ *
+ * Software output control synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0 - The software trigger does not activate the SWOCTRL register
+ * synchronization.
+ * - 1 - The software trigger activates the SWOCTRL register synchronization.
+ */
+//@{
+#define BP_FTM_SYNCONF_SWSOC (12U) //!< Bit position for FTM_SYNCONF_SWSOC.
+#define BM_FTM_SYNCONF_SWSOC (0x00001000U) //!< Bit mask for FTM_SYNCONF_SWSOC.
+#define BS_FTM_SYNCONF_SWSOC (1U) //!< Bit field size in bits for FTM_SYNCONF_SWSOC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_SWSOC field.
+#define BR_FTM_SYNCONF_SWSOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWSOC))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_SWSOC.
+#define BF_FTM_SYNCONF_SWSOC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_SWSOC), uint32_t) & BM_FTM_SYNCONF_SWSOC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SWSOC field to a new value.
+#define BW_FTM_SYNCONF_SWSOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWSOC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNCONF, field HWRSTCNT[16] (RW)
+ *
+ * FTM counter synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0 - A hardware trigger does not activate the FTM counter synchronization.
+ * - 1 - A hardware trigger activates the FTM counter synchronization.
+ */
+//@{
+#define BP_FTM_SYNCONF_HWRSTCNT (16U) //!< Bit position for FTM_SYNCONF_HWRSTCNT.
+#define BM_FTM_SYNCONF_HWRSTCNT (0x00010000U) //!< Bit mask for FTM_SYNCONF_HWRSTCNT.
+#define BS_FTM_SYNCONF_HWRSTCNT (1U) //!< Bit field size in bits for FTM_SYNCONF_HWRSTCNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_HWRSTCNT field.
+#define BR_FTM_SYNCONF_HWRSTCNT(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWRSTCNT))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_HWRSTCNT.
+#define BF_FTM_SYNCONF_HWRSTCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWRSTCNT), uint32_t) & BM_FTM_SYNCONF_HWRSTCNT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HWRSTCNT field to a new value.
+#define BW_FTM_SYNCONF_HWRSTCNT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWRSTCNT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNCONF, field HWWRBUF[17] (RW)
+ *
+ * MOD, CNTIN, and CV registers synchronization is activated by a hardware
+ * trigger.
+ *
+ * Values:
+ * - 0 - A hardware trigger does not activate MOD, CNTIN, and CV registers
+ * synchronization.
+ * - 1 - A hardware trigger activates MOD, CNTIN, and CV registers
+ * synchronization.
+ */
+//@{
+#define BP_FTM_SYNCONF_HWWRBUF (17U) //!< Bit position for FTM_SYNCONF_HWWRBUF.
+#define BM_FTM_SYNCONF_HWWRBUF (0x00020000U) //!< Bit mask for FTM_SYNCONF_HWWRBUF.
+#define BS_FTM_SYNCONF_HWWRBUF (1U) //!< Bit field size in bits for FTM_SYNCONF_HWWRBUF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_HWWRBUF field.
+#define BR_FTM_SYNCONF_HWWRBUF(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWWRBUF))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_HWWRBUF.
+#define BF_FTM_SYNCONF_HWWRBUF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWWRBUF), uint32_t) & BM_FTM_SYNCONF_HWWRBUF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HWWRBUF field to a new value.
+#define BW_FTM_SYNCONF_HWWRBUF(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWWRBUF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNCONF, field HWOM[18] (RW)
+ *
+ * Output mask synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0 - A hardware trigger does not activate the OUTMASK register
+ * synchronization.
+ * - 1 - A hardware trigger activates the OUTMASK register synchronization.
+ */
+//@{
+#define BP_FTM_SYNCONF_HWOM (18U) //!< Bit position for FTM_SYNCONF_HWOM.
+#define BM_FTM_SYNCONF_HWOM (0x00040000U) //!< Bit mask for FTM_SYNCONF_HWOM.
+#define BS_FTM_SYNCONF_HWOM (1U) //!< Bit field size in bits for FTM_SYNCONF_HWOM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_HWOM field.
+#define BR_FTM_SYNCONF_HWOM(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWOM))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_HWOM.
+#define BF_FTM_SYNCONF_HWOM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWOM), uint32_t) & BM_FTM_SYNCONF_HWOM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HWOM field to a new value.
+#define BW_FTM_SYNCONF_HWOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWOM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNCONF, field HWINVC[19] (RW)
+ *
+ * Inverting control synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0 - A hardware trigger does not activate the INVCTRL register
+ * synchronization.
+ * - 1 - A hardware trigger activates the INVCTRL register synchronization.
+ */
+//@{
+#define BP_FTM_SYNCONF_HWINVC (19U) //!< Bit position for FTM_SYNCONF_HWINVC.
+#define BM_FTM_SYNCONF_HWINVC (0x00080000U) //!< Bit mask for FTM_SYNCONF_HWINVC.
+#define BS_FTM_SYNCONF_HWINVC (1U) //!< Bit field size in bits for FTM_SYNCONF_HWINVC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_HWINVC field.
+#define BR_FTM_SYNCONF_HWINVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWINVC))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_HWINVC.
+#define BF_FTM_SYNCONF_HWINVC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWINVC), uint32_t) & BM_FTM_SYNCONF_HWINVC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HWINVC field to a new value.
+#define BW_FTM_SYNCONF_HWINVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWINVC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SYNCONF, field HWSOC[20] (RW)
+ *
+ * Software output control synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0 - A hardware trigger does not activate the SWOCTRL register
+ * synchronization.
+ * - 1 - A hardware trigger activates the SWOCTRL register synchronization.
+ */
+//@{
+#define BP_FTM_SYNCONF_HWSOC (20U) //!< Bit position for FTM_SYNCONF_HWSOC.
+#define BM_FTM_SYNCONF_HWSOC (0x00100000U) //!< Bit mask for FTM_SYNCONF_HWSOC.
+#define BS_FTM_SYNCONF_HWSOC (1U) //!< Bit field size in bits for FTM_SYNCONF_HWSOC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SYNCONF_HWSOC field.
+#define BR_FTM_SYNCONF_HWSOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWSOC))
+#endif
+
+//! @brief Format value for bitfield FTM_SYNCONF_HWSOC.
+#define BF_FTM_SYNCONF_HWSOC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SYNCONF_HWSOC), uint32_t) & BM_FTM_SYNCONF_HWSOC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HWSOC field to a new value.
+#define BW_FTM_SYNCONF_HWSOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWSOC) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_INVCTRL - FTM Inverting Control
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_INVCTRL - FTM Inverting Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register controls when the channel (n) output becomes the channel (n+1)
+ * output, and channel (n+1) output becomes the channel (n) output. Each INVmEN
+ * bit enables the inverting operation for the corresponding pair channels m. This
+ * register has a write buffer. The INVmEN bit is updated by the INVCTRL
+ * register synchronization.
+ */
+typedef union _hw_ftm_invctrl
+{
+ uint32_t U;
+ struct _hw_ftm_invctrl_bitfields
+ {
+ uint32_t INV0EN : 1; //!< [0] Pair Channels 0 Inverting Enable
+ uint32_t INV1EN : 1; //!< [1] Pair Channels 1 Inverting Enable
+ uint32_t INV2EN : 1; //!< [2] Pair Channels 2 Inverting Enable
+ uint32_t INV3EN : 1; //!< [3] Pair Channels 3 Inverting Enable
+ uint32_t RESERVED0 : 28; //!< [31:4]
+ } B;
+} hw_ftm_invctrl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_INVCTRL register
+ */
+//@{
+#define HW_FTM_INVCTRL_ADDR(x) (REGS_FTM_BASE(x) + 0x90U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_INVCTRL(x) (*(__IO hw_ftm_invctrl_t *) HW_FTM_INVCTRL_ADDR(x))
+#define HW_FTM_INVCTRL_RD(x) (HW_FTM_INVCTRL(x).U)
+#define HW_FTM_INVCTRL_WR(x, v) (HW_FTM_INVCTRL(x).U = (v))
+#define HW_FTM_INVCTRL_SET(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) | (v)))
+#define HW_FTM_INVCTRL_CLR(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) & ~(v)))
+#define HW_FTM_INVCTRL_TOG(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_INVCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_INVCTRL, field INV0EN[0] (RW)
+ *
+ * Values:
+ * - 0 - Inverting is disabled.
+ * - 1 - Inverting is enabled.
+ */
+//@{
+#define BP_FTM_INVCTRL_INV0EN (0U) //!< Bit position for FTM_INVCTRL_INV0EN.
+#define BM_FTM_INVCTRL_INV0EN (0x00000001U) //!< Bit mask for FTM_INVCTRL_INV0EN.
+#define BS_FTM_INVCTRL_INV0EN (1U) //!< Bit field size in bits for FTM_INVCTRL_INV0EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_INVCTRL_INV0EN field.
+#define BR_FTM_INVCTRL_INV0EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV0EN))
+#endif
+
+//! @brief Format value for bitfield FTM_INVCTRL_INV0EN.
+#define BF_FTM_INVCTRL_INV0EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_INVCTRL_INV0EN), uint32_t) & BM_FTM_INVCTRL_INV0EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INV0EN field to a new value.
+#define BW_FTM_INVCTRL_INV0EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV0EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_INVCTRL, field INV1EN[1] (RW)
+ *
+ * Values:
+ * - 0 - Inverting is disabled.
+ * - 1 - Inverting is enabled.
+ */
+//@{
+#define BP_FTM_INVCTRL_INV1EN (1U) //!< Bit position for FTM_INVCTRL_INV1EN.
+#define BM_FTM_INVCTRL_INV1EN (0x00000002U) //!< Bit mask for FTM_INVCTRL_INV1EN.
+#define BS_FTM_INVCTRL_INV1EN (1U) //!< Bit field size in bits for FTM_INVCTRL_INV1EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_INVCTRL_INV1EN field.
+#define BR_FTM_INVCTRL_INV1EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV1EN))
+#endif
+
+//! @brief Format value for bitfield FTM_INVCTRL_INV1EN.
+#define BF_FTM_INVCTRL_INV1EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_INVCTRL_INV1EN), uint32_t) & BM_FTM_INVCTRL_INV1EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INV1EN field to a new value.
+#define BW_FTM_INVCTRL_INV1EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV1EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_INVCTRL, field INV2EN[2] (RW)
+ *
+ * Values:
+ * - 0 - Inverting is disabled.
+ * - 1 - Inverting is enabled.
+ */
+//@{
+#define BP_FTM_INVCTRL_INV2EN (2U) //!< Bit position for FTM_INVCTRL_INV2EN.
+#define BM_FTM_INVCTRL_INV2EN (0x00000004U) //!< Bit mask for FTM_INVCTRL_INV2EN.
+#define BS_FTM_INVCTRL_INV2EN (1U) //!< Bit field size in bits for FTM_INVCTRL_INV2EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_INVCTRL_INV2EN field.
+#define BR_FTM_INVCTRL_INV2EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV2EN))
+#endif
+
+//! @brief Format value for bitfield FTM_INVCTRL_INV2EN.
+#define BF_FTM_INVCTRL_INV2EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_INVCTRL_INV2EN), uint32_t) & BM_FTM_INVCTRL_INV2EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INV2EN field to a new value.
+#define BW_FTM_INVCTRL_INV2EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV2EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_INVCTRL, field INV3EN[3] (RW)
+ *
+ * Values:
+ * - 0 - Inverting is disabled.
+ * - 1 - Inverting is enabled.
+ */
+//@{
+#define BP_FTM_INVCTRL_INV3EN (3U) //!< Bit position for FTM_INVCTRL_INV3EN.
+#define BM_FTM_INVCTRL_INV3EN (0x00000008U) //!< Bit mask for FTM_INVCTRL_INV3EN.
+#define BS_FTM_INVCTRL_INV3EN (1U) //!< Bit field size in bits for FTM_INVCTRL_INV3EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_INVCTRL_INV3EN field.
+#define BR_FTM_INVCTRL_INV3EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV3EN))
+#endif
+
+//! @brief Format value for bitfield FTM_INVCTRL_INV3EN.
+#define BF_FTM_INVCTRL_INV3EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_INVCTRL_INV3EN), uint32_t) & BM_FTM_INVCTRL_INV3EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INV3EN field to a new value.
+#define BW_FTM_INVCTRL_INV3EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV3EN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_SWOCTRL - FTM Software Output Control
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_SWOCTRL - FTM Software Output Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register enables software control of channel (n) output and defines the
+ * value forced to the channel (n) output: The CHnOC bits enable the control of
+ * the corresponding channel (n) output by software. The CHnOCV bits select the
+ * value that is forced at the corresponding channel (n) output. This register has
+ * a write buffer. The fields are updated by the SWOCTRL register synchronization.
+ */
+typedef union _hw_ftm_swoctrl
+{
+ uint32_t U;
+ struct _hw_ftm_swoctrl_bitfields
+ {
+ uint32_t CH0OC : 1; //!< [0] Channel 0 Software Output Control Enable
+ uint32_t CH1OC : 1; //!< [1] Channel 1 Software Output Control Enable
+ uint32_t CH2OC : 1; //!< [2] Channel 2 Software Output Control Enable
+ uint32_t CH3OC : 1; //!< [3] Channel 3 Software Output Control Enable
+ uint32_t CH4OC : 1; //!< [4] Channel 4 Software Output Control Enable
+ uint32_t CH5OC : 1; //!< [5] Channel 5 Software Output Control Enable
+ uint32_t CH6OC : 1; //!< [6] Channel 6 Software Output Control Enable
+ uint32_t CH7OC : 1; //!< [7] Channel 7 Software Output Control Enable
+ uint32_t CH0OCV : 1; //!< [8] Channel 0 Software Output Control Value
+ uint32_t CH1OCV : 1; //!< [9] Channel 1 Software Output Control Value
+ uint32_t CH2OCV : 1; //!< [10] Channel 2 Software Output Control Value
+ uint32_t CH3OCV : 1; //!< [11] Channel 3 Software Output Control Value
+ uint32_t CH4OCV : 1; //!< [12] Channel 4 Software Output Control Value
+ uint32_t CH5OCV : 1; //!< [13] Channel 5 Software Output Control Value
+ uint32_t CH6OCV : 1; //!< [14] Channel 6 Software Output Control Value
+ uint32_t CH7OCV : 1; //!< [15] Channel 7 Software Output Control Value
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_ftm_swoctrl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_SWOCTRL register
+ */
+//@{
+#define HW_FTM_SWOCTRL_ADDR(x) (REGS_FTM_BASE(x) + 0x94U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_SWOCTRL(x) (*(__IO hw_ftm_swoctrl_t *) HW_FTM_SWOCTRL_ADDR(x))
+#define HW_FTM_SWOCTRL_RD(x) (HW_FTM_SWOCTRL(x).U)
+#define HW_FTM_SWOCTRL_WR(x, v) (HW_FTM_SWOCTRL(x).U = (v))
+#define HW_FTM_SWOCTRL_SET(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) | (v)))
+#define HW_FTM_SWOCTRL_CLR(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) & ~(v)))
+#define HW_FTM_SWOCTRL_TOG(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_SWOCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH0OC[0] (RW)
+ *
+ * Values:
+ * - 0 - The channel output is not affected by software output control.
+ * - 1 - The channel output is affected by software output control.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH0OC (0U) //!< Bit position for FTM_SWOCTRL_CH0OC.
+#define BM_FTM_SWOCTRL_CH0OC (0x00000001U) //!< Bit mask for FTM_SWOCTRL_CH0OC.
+#define BS_FTM_SWOCTRL_CH0OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH0OC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH0OC field.
+#define BR_FTM_SWOCTRL_CH0OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OC))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH0OC.
+#define BF_FTM_SWOCTRL_CH0OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH0OC), uint32_t) & BM_FTM_SWOCTRL_CH0OC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH0OC field to a new value.
+#define BW_FTM_SWOCTRL_CH0OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH1OC[1] (RW)
+ *
+ * Values:
+ * - 0 - The channel output is not affected by software output control.
+ * - 1 - The channel output is affected by software output control.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH1OC (1U) //!< Bit position for FTM_SWOCTRL_CH1OC.
+#define BM_FTM_SWOCTRL_CH1OC (0x00000002U) //!< Bit mask for FTM_SWOCTRL_CH1OC.
+#define BS_FTM_SWOCTRL_CH1OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH1OC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH1OC field.
+#define BR_FTM_SWOCTRL_CH1OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OC))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH1OC.
+#define BF_FTM_SWOCTRL_CH1OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH1OC), uint32_t) & BM_FTM_SWOCTRL_CH1OC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH1OC field to a new value.
+#define BW_FTM_SWOCTRL_CH1OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH2OC[2] (RW)
+ *
+ * Values:
+ * - 0 - The channel output is not affected by software output control.
+ * - 1 - The channel output is affected by software output control.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH2OC (2U) //!< Bit position for FTM_SWOCTRL_CH2OC.
+#define BM_FTM_SWOCTRL_CH2OC (0x00000004U) //!< Bit mask for FTM_SWOCTRL_CH2OC.
+#define BS_FTM_SWOCTRL_CH2OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH2OC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH2OC field.
+#define BR_FTM_SWOCTRL_CH2OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OC))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH2OC.
+#define BF_FTM_SWOCTRL_CH2OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH2OC), uint32_t) & BM_FTM_SWOCTRL_CH2OC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH2OC field to a new value.
+#define BW_FTM_SWOCTRL_CH2OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH3OC[3] (RW)
+ *
+ * Values:
+ * - 0 - The channel output is not affected by software output control.
+ * - 1 - The channel output is affected by software output control.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH3OC (3U) //!< Bit position for FTM_SWOCTRL_CH3OC.
+#define BM_FTM_SWOCTRL_CH3OC (0x00000008U) //!< Bit mask for FTM_SWOCTRL_CH3OC.
+#define BS_FTM_SWOCTRL_CH3OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH3OC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH3OC field.
+#define BR_FTM_SWOCTRL_CH3OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OC))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH3OC.
+#define BF_FTM_SWOCTRL_CH3OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH3OC), uint32_t) & BM_FTM_SWOCTRL_CH3OC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH3OC field to a new value.
+#define BW_FTM_SWOCTRL_CH3OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH4OC[4] (RW)
+ *
+ * Values:
+ * - 0 - The channel output is not affected by software output control.
+ * - 1 - The channel output is affected by software output control.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH4OC (4U) //!< Bit position for FTM_SWOCTRL_CH4OC.
+#define BM_FTM_SWOCTRL_CH4OC (0x00000010U) //!< Bit mask for FTM_SWOCTRL_CH4OC.
+#define BS_FTM_SWOCTRL_CH4OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH4OC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH4OC field.
+#define BR_FTM_SWOCTRL_CH4OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OC))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH4OC.
+#define BF_FTM_SWOCTRL_CH4OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH4OC), uint32_t) & BM_FTM_SWOCTRL_CH4OC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH4OC field to a new value.
+#define BW_FTM_SWOCTRL_CH4OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH5OC[5] (RW)
+ *
+ * Values:
+ * - 0 - The channel output is not affected by software output control.
+ * - 1 - The channel output is affected by software output control.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH5OC (5U) //!< Bit position for FTM_SWOCTRL_CH5OC.
+#define BM_FTM_SWOCTRL_CH5OC (0x00000020U) //!< Bit mask for FTM_SWOCTRL_CH5OC.
+#define BS_FTM_SWOCTRL_CH5OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH5OC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH5OC field.
+#define BR_FTM_SWOCTRL_CH5OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OC))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH5OC.
+#define BF_FTM_SWOCTRL_CH5OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH5OC), uint32_t) & BM_FTM_SWOCTRL_CH5OC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH5OC field to a new value.
+#define BW_FTM_SWOCTRL_CH5OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH6OC[6] (RW)
+ *
+ * Values:
+ * - 0 - The channel output is not affected by software output control.
+ * - 1 - The channel output is affected by software output control.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH6OC (6U) //!< Bit position for FTM_SWOCTRL_CH6OC.
+#define BM_FTM_SWOCTRL_CH6OC (0x00000040U) //!< Bit mask for FTM_SWOCTRL_CH6OC.
+#define BS_FTM_SWOCTRL_CH6OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH6OC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH6OC field.
+#define BR_FTM_SWOCTRL_CH6OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OC))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH6OC.
+#define BF_FTM_SWOCTRL_CH6OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH6OC), uint32_t) & BM_FTM_SWOCTRL_CH6OC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH6OC field to a new value.
+#define BW_FTM_SWOCTRL_CH6OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH7OC[7] (RW)
+ *
+ * Values:
+ * - 0 - The channel output is not affected by software output control.
+ * - 1 - The channel output is affected by software output control.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH7OC (7U) //!< Bit position for FTM_SWOCTRL_CH7OC.
+#define BM_FTM_SWOCTRL_CH7OC (0x00000080U) //!< Bit mask for FTM_SWOCTRL_CH7OC.
+#define BS_FTM_SWOCTRL_CH7OC (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH7OC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH7OC field.
+#define BR_FTM_SWOCTRL_CH7OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OC))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH7OC.
+#define BF_FTM_SWOCTRL_CH7OC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH7OC), uint32_t) & BM_FTM_SWOCTRL_CH7OC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH7OC field to a new value.
+#define BW_FTM_SWOCTRL_CH7OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH0OCV[8] (RW)
+ *
+ * Values:
+ * - 0 - The software output control forces 0 to the channel output.
+ * - 1 - The software output control forces 1 to the channel output.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH0OCV (8U) //!< Bit position for FTM_SWOCTRL_CH0OCV.
+#define BM_FTM_SWOCTRL_CH0OCV (0x00000100U) //!< Bit mask for FTM_SWOCTRL_CH0OCV.
+#define BS_FTM_SWOCTRL_CH0OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH0OCV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH0OCV field.
+#define BR_FTM_SWOCTRL_CH0OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OCV))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH0OCV.
+#define BF_FTM_SWOCTRL_CH0OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH0OCV), uint32_t) & BM_FTM_SWOCTRL_CH0OCV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH0OCV field to a new value.
+#define BW_FTM_SWOCTRL_CH0OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OCV) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH1OCV[9] (RW)
+ *
+ * Values:
+ * - 0 - The software output control forces 0 to the channel output.
+ * - 1 - The software output control forces 1 to the channel output.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH1OCV (9U) //!< Bit position for FTM_SWOCTRL_CH1OCV.
+#define BM_FTM_SWOCTRL_CH1OCV (0x00000200U) //!< Bit mask for FTM_SWOCTRL_CH1OCV.
+#define BS_FTM_SWOCTRL_CH1OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH1OCV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH1OCV field.
+#define BR_FTM_SWOCTRL_CH1OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OCV))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH1OCV.
+#define BF_FTM_SWOCTRL_CH1OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH1OCV), uint32_t) & BM_FTM_SWOCTRL_CH1OCV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH1OCV field to a new value.
+#define BW_FTM_SWOCTRL_CH1OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OCV) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH2OCV[10] (RW)
+ *
+ * Values:
+ * - 0 - The software output control forces 0 to the channel output.
+ * - 1 - The software output control forces 1 to the channel output.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH2OCV (10U) //!< Bit position for FTM_SWOCTRL_CH2OCV.
+#define BM_FTM_SWOCTRL_CH2OCV (0x00000400U) //!< Bit mask for FTM_SWOCTRL_CH2OCV.
+#define BS_FTM_SWOCTRL_CH2OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH2OCV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH2OCV field.
+#define BR_FTM_SWOCTRL_CH2OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OCV))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH2OCV.
+#define BF_FTM_SWOCTRL_CH2OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH2OCV), uint32_t) & BM_FTM_SWOCTRL_CH2OCV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH2OCV field to a new value.
+#define BW_FTM_SWOCTRL_CH2OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OCV) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH3OCV[11] (RW)
+ *
+ * Values:
+ * - 0 - The software output control forces 0 to the channel output.
+ * - 1 - The software output control forces 1 to the channel output.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH3OCV (11U) //!< Bit position for FTM_SWOCTRL_CH3OCV.
+#define BM_FTM_SWOCTRL_CH3OCV (0x00000800U) //!< Bit mask for FTM_SWOCTRL_CH3OCV.
+#define BS_FTM_SWOCTRL_CH3OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH3OCV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH3OCV field.
+#define BR_FTM_SWOCTRL_CH3OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OCV))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH3OCV.
+#define BF_FTM_SWOCTRL_CH3OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH3OCV), uint32_t) & BM_FTM_SWOCTRL_CH3OCV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH3OCV field to a new value.
+#define BW_FTM_SWOCTRL_CH3OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OCV) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH4OCV[12] (RW)
+ *
+ * Values:
+ * - 0 - The software output control forces 0 to the channel output.
+ * - 1 - The software output control forces 1 to the channel output.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH4OCV (12U) //!< Bit position for FTM_SWOCTRL_CH4OCV.
+#define BM_FTM_SWOCTRL_CH4OCV (0x00001000U) //!< Bit mask for FTM_SWOCTRL_CH4OCV.
+#define BS_FTM_SWOCTRL_CH4OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH4OCV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH4OCV field.
+#define BR_FTM_SWOCTRL_CH4OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OCV))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH4OCV.
+#define BF_FTM_SWOCTRL_CH4OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH4OCV), uint32_t) & BM_FTM_SWOCTRL_CH4OCV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH4OCV field to a new value.
+#define BW_FTM_SWOCTRL_CH4OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OCV) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH5OCV[13] (RW)
+ *
+ * Values:
+ * - 0 - The software output control forces 0 to the channel output.
+ * - 1 - The software output control forces 1 to the channel output.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH5OCV (13U) //!< Bit position for FTM_SWOCTRL_CH5OCV.
+#define BM_FTM_SWOCTRL_CH5OCV (0x00002000U) //!< Bit mask for FTM_SWOCTRL_CH5OCV.
+#define BS_FTM_SWOCTRL_CH5OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH5OCV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH5OCV field.
+#define BR_FTM_SWOCTRL_CH5OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OCV))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH5OCV.
+#define BF_FTM_SWOCTRL_CH5OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH5OCV), uint32_t) & BM_FTM_SWOCTRL_CH5OCV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH5OCV field to a new value.
+#define BW_FTM_SWOCTRL_CH5OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OCV) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH6OCV[14] (RW)
+ *
+ * Values:
+ * - 0 - The software output control forces 0 to the channel output.
+ * - 1 - The software output control forces 1 to the channel output.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH6OCV (14U) //!< Bit position for FTM_SWOCTRL_CH6OCV.
+#define BM_FTM_SWOCTRL_CH6OCV (0x00004000U) //!< Bit mask for FTM_SWOCTRL_CH6OCV.
+#define BS_FTM_SWOCTRL_CH6OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH6OCV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH6OCV field.
+#define BR_FTM_SWOCTRL_CH6OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OCV))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH6OCV.
+#define BF_FTM_SWOCTRL_CH6OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH6OCV), uint32_t) & BM_FTM_SWOCTRL_CH6OCV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH6OCV field to a new value.
+#define BW_FTM_SWOCTRL_CH6OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OCV) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH7OCV[15] (RW)
+ *
+ * Values:
+ * - 0 - The software output control forces 0 to the channel output.
+ * - 1 - The software output control forces 1 to the channel output.
+ */
+//@{
+#define BP_FTM_SWOCTRL_CH7OCV (15U) //!< Bit position for FTM_SWOCTRL_CH7OCV.
+#define BM_FTM_SWOCTRL_CH7OCV (0x00008000U) //!< Bit mask for FTM_SWOCTRL_CH7OCV.
+#define BS_FTM_SWOCTRL_CH7OCV (1U) //!< Bit field size in bits for FTM_SWOCTRL_CH7OCV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_SWOCTRL_CH7OCV field.
+#define BR_FTM_SWOCTRL_CH7OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OCV))
+#endif
+
+//! @brief Format value for bitfield FTM_SWOCTRL_CH7OCV.
+#define BF_FTM_SWOCTRL_CH7OCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_SWOCTRL_CH7OCV), uint32_t) & BM_FTM_SWOCTRL_CH7OCV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH7OCV field to a new value.
+#define BW_FTM_SWOCTRL_CH7OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OCV) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_FTM_PWMLOAD - FTM PWM Load
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_FTM_PWMLOAD - FTM PWM Load (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Enables the loading of the MOD, CNTIN, C(n)V, and C(n+1)V registers with the
+ * values of their write buffers when the FTM counter changes from the MOD
+ * register value to its next value or when a channel (j) match occurs. A match occurs
+ * for the channel (j) when FTM counter = C(j)V.
+ */
+typedef union _hw_ftm_pwmload
+{
+ uint32_t U;
+ struct _hw_ftm_pwmload_bitfields
+ {
+ uint32_t CH0SEL : 1; //!< [0] Channel 0 Select
+ uint32_t CH1SEL : 1; //!< [1] Channel 1 Select
+ uint32_t CH2SEL : 1; //!< [2] Channel 2 Select
+ uint32_t CH3SEL : 1; //!< [3] Channel 3 Select
+ uint32_t CH4SEL : 1; //!< [4] Channel 4 Select
+ uint32_t CH5SEL : 1; //!< [5] Channel 5 Select
+ uint32_t CH6SEL : 1; //!< [6] Channel 6 Select
+ uint32_t CH7SEL : 1; //!< [7] Channel 7 Select
+ uint32_t RESERVED0 : 1; //!< [8]
+ uint32_t LDOK : 1; //!< [9] Load Enable
+ uint32_t RESERVED1 : 22; //!< [31:10]
+ } B;
+} hw_ftm_pwmload_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire FTM_PWMLOAD register
+ */
+//@{
+#define HW_FTM_PWMLOAD_ADDR(x) (REGS_FTM_BASE(x) + 0x98U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_FTM_PWMLOAD(x) (*(__IO hw_ftm_pwmload_t *) HW_FTM_PWMLOAD_ADDR(x))
+#define HW_FTM_PWMLOAD_RD(x) (HW_FTM_PWMLOAD(x).U)
+#define HW_FTM_PWMLOAD_WR(x, v) (HW_FTM_PWMLOAD(x).U = (v))
+#define HW_FTM_PWMLOAD_SET(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) | (v)))
+#define HW_FTM_PWMLOAD_CLR(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) & ~(v)))
+#define HW_FTM_PWMLOAD_TOG(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual FTM_PWMLOAD bitfields
+ */
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH0SEL[0] (RW)
+ *
+ * Values:
+ * - 0 - Do not include the channel in the matching process.
+ * - 1 - Include the channel in the matching process.
+ */
+//@{
+#define BP_FTM_PWMLOAD_CH0SEL (0U) //!< Bit position for FTM_PWMLOAD_CH0SEL.
+#define BM_FTM_PWMLOAD_CH0SEL (0x00000001U) //!< Bit mask for FTM_PWMLOAD_CH0SEL.
+#define BS_FTM_PWMLOAD_CH0SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH0SEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_PWMLOAD_CH0SEL field.
+#define BR_FTM_PWMLOAD_CH0SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH0SEL))
+#endif
+
+//! @brief Format value for bitfield FTM_PWMLOAD_CH0SEL.
+#define BF_FTM_PWMLOAD_CH0SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH0SEL), uint32_t) & BM_FTM_PWMLOAD_CH0SEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH0SEL field to a new value.
+#define BW_FTM_PWMLOAD_CH0SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH0SEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH1SEL[1] (RW)
+ *
+ * Values:
+ * - 0 - Do not include the channel in the matching process.
+ * - 1 - Include the channel in the matching process.
+ */
+//@{
+#define BP_FTM_PWMLOAD_CH1SEL (1U) //!< Bit position for FTM_PWMLOAD_CH1SEL.
+#define BM_FTM_PWMLOAD_CH1SEL (0x00000002U) //!< Bit mask for FTM_PWMLOAD_CH1SEL.
+#define BS_FTM_PWMLOAD_CH1SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH1SEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_PWMLOAD_CH1SEL field.
+#define BR_FTM_PWMLOAD_CH1SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH1SEL))
+#endif
+
+//! @brief Format value for bitfield FTM_PWMLOAD_CH1SEL.
+#define BF_FTM_PWMLOAD_CH1SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH1SEL), uint32_t) & BM_FTM_PWMLOAD_CH1SEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH1SEL field to a new value.
+#define BW_FTM_PWMLOAD_CH1SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH1SEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH2SEL[2] (RW)
+ *
+ * Values:
+ * - 0 - Do not include the channel in the matching process.
+ * - 1 - Include the channel in the matching process.
+ */
+//@{
+#define BP_FTM_PWMLOAD_CH2SEL (2U) //!< Bit position for FTM_PWMLOAD_CH2SEL.
+#define BM_FTM_PWMLOAD_CH2SEL (0x00000004U) //!< Bit mask for FTM_PWMLOAD_CH2SEL.
+#define BS_FTM_PWMLOAD_CH2SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH2SEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_PWMLOAD_CH2SEL field.
+#define BR_FTM_PWMLOAD_CH2SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH2SEL))
+#endif
+
+//! @brief Format value for bitfield FTM_PWMLOAD_CH2SEL.
+#define BF_FTM_PWMLOAD_CH2SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH2SEL), uint32_t) & BM_FTM_PWMLOAD_CH2SEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH2SEL field to a new value.
+#define BW_FTM_PWMLOAD_CH2SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH2SEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH3SEL[3] (RW)
+ *
+ * Values:
+ * - 0 - Do not include the channel in the matching process.
+ * - 1 - Include the channel in the matching process.
+ */
+//@{
+#define BP_FTM_PWMLOAD_CH3SEL (3U) //!< Bit position for FTM_PWMLOAD_CH3SEL.
+#define BM_FTM_PWMLOAD_CH3SEL (0x00000008U) //!< Bit mask for FTM_PWMLOAD_CH3SEL.
+#define BS_FTM_PWMLOAD_CH3SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH3SEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_PWMLOAD_CH3SEL field.
+#define BR_FTM_PWMLOAD_CH3SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH3SEL))
+#endif
+
+//! @brief Format value for bitfield FTM_PWMLOAD_CH3SEL.
+#define BF_FTM_PWMLOAD_CH3SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH3SEL), uint32_t) & BM_FTM_PWMLOAD_CH3SEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH3SEL field to a new value.
+#define BW_FTM_PWMLOAD_CH3SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH3SEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH4SEL[4] (RW)
+ *
+ * Values:
+ * - 0 - Do not include the channel in the matching process.
+ * - 1 - Include the channel in the matching process.
+ */
+//@{
+#define BP_FTM_PWMLOAD_CH4SEL (4U) //!< Bit position for FTM_PWMLOAD_CH4SEL.
+#define BM_FTM_PWMLOAD_CH4SEL (0x00000010U) //!< Bit mask for FTM_PWMLOAD_CH4SEL.
+#define BS_FTM_PWMLOAD_CH4SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH4SEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_PWMLOAD_CH4SEL field.
+#define BR_FTM_PWMLOAD_CH4SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH4SEL))
+#endif
+
+//! @brief Format value for bitfield FTM_PWMLOAD_CH4SEL.
+#define BF_FTM_PWMLOAD_CH4SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH4SEL), uint32_t) & BM_FTM_PWMLOAD_CH4SEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH4SEL field to a new value.
+#define BW_FTM_PWMLOAD_CH4SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH4SEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH5SEL[5] (RW)
+ *
+ * Values:
+ * - 0 - Do not include the channel in the matching process.
+ * - 1 - Include the channel in the matching process.
+ */
+//@{
+#define BP_FTM_PWMLOAD_CH5SEL (5U) //!< Bit position for FTM_PWMLOAD_CH5SEL.
+#define BM_FTM_PWMLOAD_CH5SEL (0x00000020U) //!< Bit mask for FTM_PWMLOAD_CH5SEL.
+#define BS_FTM_PWMLOAD_CH5SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH5SEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_PWMLOAD_CH5SEL field.
+#define BR_FTM_PWMLOAD_CH5SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH5SEL))
+#endif
+
+//! @brief Format value for bitfield FTM_PWMLOAD_CH5SEL.
+#define BF_FTM_PWMLOAD_CH5SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH5SEL), uint32_t) & BM_FTM_PWMLOAD_CH5SEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH5SEL field to a new value.
+#define BW_FTM_PWMLOAD_CH5SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH5SEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH6SEL[6] (RW)
+ *
+ * Values:
+ * - 0 - Do not include the channel in the matching process.
+ * - 1 - Include the channel in the matching process.
+ */
+//@{
+#define BP_FTM_PWMLOAD_CH6SEL (6U) //!< Bit position for FTM_PWMLOAD_CH6SEL.
+#define BM_FTM_PWMLOAD_CH6SEL (0x00000040U) //!< Bit mask for FTM_PWMLOAD_CH6SEL.
+#define BS_FTM_PWMLOAD_CH6SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH6SEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_PWMLOAD_CH6SEL field.
+#define BR_FTM_PWMLOAD_CH6SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH6SEL))
+#endif
+
+//! @brief Format value for bitfield FTM_PWMLOAD_CH6SEL.
+#define BF_FTM_PWMLOAD_CH6SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH6SEL), uint32_t) & BM_FTM_PWMLOAD_CH6SEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH6SEL field to a new value.
+#define BW_FTM_PWMLOAD_CH6SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH6SEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH7SEL[7] (RW)
+ *
+ * Values:
+ * - 0 - Do not include the channel in the matching process.
+ * - 1 - Include the channel in the matching process.
+ */
+//@{
+#define BP_FTM_PWMLOAD_CH7SEL (7U) //!< Bit position for FTM_PWMLOAD_CH7SEL.
+#define BM_FTM_PWMLOAD_CH7SEL (0x00000080U) //!< Bit mask for FTM_PWMLOAD_CH7SEL.
+#define BS_FTM_PWMLOAD_CH7SEL (1U) //!< Bit field size in bits for FTM_PWMLOAD_CH7SEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_PWMLOAD_CH7SEL field.
+#define BR_FTM_PWMLOAD_CH7SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH7SEL))
+#endif
+
+//! @brief Format value for bitfield FTM_PWMLOAD_CH7SEL.
+#define BF_FTM_PWMLOAD_CH7SEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_CH7SEL), uint32_t) & BM_FTM_PWMLOAD_CH7SEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CH7SEL field to a new value.
+#define BW_FTM_PWMLOAD_CH7SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH7SEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register FTM_PWMLOAD, field LDOK[9] (RW)
+ *
+ * Enables the loading of the MOD, CNTIN, and CV registers with the values of
+ * their write buffers.
+ *
+ * Values:
+ * - 0 - Loading updated values is disabled.
+ * - 1 - Loading updated values is enabled.
+ */
+//@{
+#define BP_FTM_PWMLOAD_LDOK (9U) //!< Bit position for FTM_PWMLOAD_LDOK.
+#define BM_FTM_PWMLOAD_LDOK (0x00000200U) //!< Bit mask for FTM_PWMLOAD_LDOK.
+#define BS_FTM_PWMLOAD_LDOK (1U) //!< Bit field size in bits for FTM_PWMLOAD_LDOK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the FTM_PWMLOAD_LDOK field.
+#define BR_FTM_PWMLOAD_LDOK(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_LDOK))
+#endif
+
+//! @brief Format value for bitfield FTM_PWMLOAD_LDOK.
+#define BF_FTM_PWMLOAD_LDOK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FTM_PWMLOAD_LDOK), uint32_t) & BM_FTM_PWMLOAD_LDOK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LDOK field to a new value.
+#define BW_FTM_PWMLOAD_LDOK(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_LDOK) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_ftm_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All FTM module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_ftm
+{
+ __IO hw_ftm_sc_t SC; //!< [0x0] Status And Control
+ __IO hw_ftm_cnt_t CNT; //!< [0x4] Counter
+ __IO hw_ftm_mod_t MOD; //!< [0x8] Modulo
+ struct {
+ __IO hw_ftm_cnsc_t CnSC; //!< [0xC] Channel (n) Status And Control
+ __IO hw_ftm_cnv_t CnV; //!< [0x10] Channel (n) Value
+ } CONTROLS[8];
+ __IO hw_ftm_cntin_t CNTIN; //!< [0x4C] Counter Initial Value
+ __IO hw_ftm_status_t STATUS; //!< [0x50] Capture And Compare Status
+ __IO hw_ftm_mode_t MODE; //!< [0x54] Features Mode Selection
+ __IO hw_ftm_sync_t SYNC; //!< [0x58] Synchronization
+ __IO hw_ftm_outinit_t OUTINIT; //!< [0x5C] Initial State For Channels Output
+ __IO hw_ftm_outmask_t OUTMASK; //!< [0x60] Output Mask
+ __IO hw_ftm_combine_t COMBINE; //!< [0x64] Function For Linked Channels
+ __IO hw_ftm_deadtime_t DEADTIME; //!< [0x68] Deadtime Insertion Control
+ __IO hw_ftm_exttrig_t EXTTRIG; //!< [0x6C] FTM External Trigger
+ __IO hw_ftm_pol_t POL; //!< [0x70] Channels Polarity
+ __IO hw_ftm_fms_t FMS; //!< [0x74] Fault Mode Status
+ __IO hw_ftm_filter_t FILTER; //!< [0x78] Input Capture Filter Control
+ __IO hw_ftm_fltctrl_t FLTCTRL; //!< [0x7C] Fault Control
+ __IO hw_ftm_qdctrl_t QDCTRL; //!< [0x80] Quadrature Decoder Control And Status
+ __IO hw_ftm_conf_t CONF; //!< [0x84] Configuration
+ __IO hw_ftm_fltpol_t FLTPOL; //!< [0x88] FTM Fault Input Polarity
+ __IO hw_ftm_synconf_t SYNCONF; //!< [0x8C] Synchronization Configuration
+ __IO hw_ftm_invctrl_t INVCTRL; //!< [0x90] FTM Inverting Control
+ __IO hw_ftm_swoctrl_t SWOCTRL; //!< [0x94] FTM Software Output Control
+ __IO hw_ftm_pwmload_t PWMLOAD; //!< [0x98] FTM PWM Load
+} hw_ftm_t;
+#pragma pack()
+
+//! @brief Macro to access all FTM registers.
+//! @param x FTM instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_FTM(0)</code>.
+#define HW_FTM(x) (*(hw_ftm_t *) REGS_FTM_BASE(x))
+#endif
+
+#endif // __HW_FTM_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_gpio.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,500 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_GPIO_REGISTERS_H__
+#define __HW_GPIO_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 GPIO
+ *
+ * General Purpose Input/Output
+ *
+ * Registers defined in this header file:
+ * - HW_GPIO_PDOR - Port Data Output Register
+ * - HW_GPIO_PSOR - Port Set Output Register
+ * - HW_GPIO_PCOR - Port Clear Output Register
+ * - HW_GPIO_PTOR - Port Toggle Output Register
+ * - HW_GPIO_PDIR - Port Data Input Register
+ * - HW_GPIO_PDDR - Port Data Direction Register
+ *
+ * - hw_gpio_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_GPIO_BASE
+#define HW_GPIO_INSTANCE_COUNT (5U) //!< Number of instances of the GPIO module.
+#define HW_GPIOA (0U) //!< Instance number for GPIOA.
+#define HW_GPIOB (1U) //!< Instance number for GPIOB.
+#define HW_GPIOC (2U) //!< Instance number for GPIOC.
+#define HW_GPIOD (3U) //!< Instance number for GPIOD.
+#define HW_GPIOE (4U) //!< Instance number for GPIOE.
+#define REGS_GPIOA_BASE (0x400FF000U) //!< Base address for GPIOA.
+#define REGS_GPIOB_BASE (0x400FF040U) //!< Base address for GPIOB.
+#define REGS_GPIOC_BASE (0x400FF080U) //!< Base address for GPIOC.
+#define REGS_GPIOD_BASE (0x400FF0C0U) //!< Base address for GPIOD.
+#define REGS_GPIOE_BASE (0x400FF100U) //!< Base address for GPIOE.
+
+//! @brief Table of base addresses for GPIO instances.
+static const uint32_t __g_regs_GPIO_base_addresses[] = {
+ REGS_GPIOA_BASE,
+ REGS_GPIOB_BASE,
+ REGS_GPIOC_BASE,
+ REGS_GPIOD_BASE,
+ REGS_GPIOE_BASE,
+ };
+
+//! @brief Get the base address of GPIO by instance number.
+//! @param x GPIO instance number, from 0 through 4.
+#define REGS_GPIO_BASE(x) (__g_regs_GPIO_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of GPIO.
+#define REGS_GPIO_INSTANCE(b) ((b) == REGS_GPIOA_BASE ? HW_GPIOA : (b) == REGS_GPIOB_BASE ? HW_GPIOB : (b) == REGS_GPIOC_BASE ? HW_GPIOC : (b) == REGS_GPIOD_BASE ? HW_GPIOD : (b) == REGS_GPIOE_BASE ? HW_GPIOE : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_GPIO_PDOR - Port Data Output Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_GPIO_PDOR - Port Data Output Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures the logic levels that are driven on each
+ * general-purpose output pins. Do not modify pin configuration registers associated with
+ * pins not available in your selected package. All unbonded pins not available in
+ * your package will default to DISABLE state for lowest power consumption.
+ */
+typedef union _hw_gpio_pdor
+{
+ uint32_t U;
+ struct _hw_gpio_pdor_bitfields
+ {
+ uint32_t PDO : 32; //!< [31:0] Port Data Output
+ } B;
+} hw_gpio_pdor_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire GPIO_PDOR register
+ */
+//@{
+#define HW_GPIO_PDOR_ADDR(x) (REGS_GPIO_BASE(x) + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_GPIO_PDOR(x) (*(__IO hw_gpio_pdor_t *) HW_GPIO_PDOR_ADDR(x))
+#define HW_GPIO_PDOR_RD(x) (HW_GPIO_PDOR(x).U)
+#define HW_GPIO_PDOR_WR(x, v) (HW_GPIO_PDOR(x).U = (v))
+#define HW_GPIO_PDOR_SET(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) | (v)))
+#define HW_GPIO_PDOR_CLR(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) & ~(v)))
+#define HW_GPIO_PDOR_TOG(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual GPIO_PDOR bitfields
+ */
+
+/*!
+ * @name Register GPIO_PDOR, field PDO[31:0] (RW)
+ *
+ * Register bits for unbonded pins return a undefined value when read.
+ *
+ * Values:
+ * - 0 - Logic level 0 is driven on pin, provided pin is configured for
+ * general-purpose output.
+ * - 1 - Logic level 1 is driven on pin, provided pin is configured for
+ * general-purpose output.
+ */
+//@{
+#define BP_GPIO_PDOR_PDO (0U) //!< Bit position for GPIO_PDOR_PDO.
+#define BM_GPIO_PDOR_PDO (0xFFFFFFFFU) //!< Bit mask for GPIO_PDOR_PDO.
+#define BS_GPIO_PDOR_PDO (32U) //!< Bit field size in bits for GPIO_PDOR_PDO.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the GPIO_PDOR_PDO field.
+#define BR_GPIO_PDOR_PDO(x) (HW_GPIO_PDOR(x).U)
+#endif
+
+//! @brief Format value for bitfield GPIO_PDOR_PDO.
+#define BF_GPIO_PDOR_PDO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PDOR_PDO), uint32_t) & BM_GPIO_PDOR_PDO)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PDO field to a new value.
+#define BW_GPIO_PDOR_PDO(x, v) (HW_GPIO_PDOR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_GPIO_PSOR - Port Set Output Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_GPIO_PSOR - Port Set Output Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures whether to set the fields of the PDOR.
+ */
+typedef union _hw_gpio_psor
+{
+ uint32_t U;
+ struct _hw_gpio_psor_bitfields
+ {
+ uint32_t PTSO : 32; //!< [31:0] Port Set Output
+ } B;
+} hw_gpio_psor_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire GPIO_PSOR register
+ */
+//@{
+#define HW_GPIO_PSOR_ADDR(x) (REGS_GPIO_BASE(x) + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_GPIO_PSOR(x) (*(__O hw_gpio_psor_t *) HW_GPIO_PSOR_ADDR(x))
+#define HW_GPIO_PSOR_RD(x) (HW_GPIO_PSOR(x).U)
+#define HW_GPIO_PSOR_WR(x, v) (HW_GPIO_PSOR(x).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual GPIO_PSOR bitfields
+ */
+
+/*!
+ * @name Register GPIO_PSOR, field PTSO[31:0] (WORZ)
+ *
+ * Writing to this register will update the contents of the corresponding bit in
+ * the PDOR as follows:
+ *
+ * Values:
+ * - 0 - Corresponding bit in PDORn does not change.
+ * - 1 - Corresponding bit in PDORn is set to logic 1.
+ */
+//@{
+#define BP_GPIO_PSOR_PTSO (0U) //!< Bit position for GPIO_PSOR_PTSO.
+#define BM_GPIO_PSOR_PTSO (0xFFFFFFFFU) //!< Bit mask for GPIO_PSOR_PTSO.
+#define BS_GPIO_PSOR_PTSO (32U) //!< Bit field size in bits for GPIO_PSOR_PTSO.
+
+//! @brief Format value for bitfield GPIO_PSOR_PTSO.
+#define BF_GPIO_PSOR_PTSO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PSOR_PTSO), uint32_t) & BM_GPIO_PSOR_PTSO)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PTSO field to a new value.
+#define BW_GPIO_PSOR_PTSO(x, v) (HW_GPIO_PSOR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_GPIO_PCOR - Port Clear Output Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_GPIO_PCOR - Port Clear Output Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures whether to clear the fields of PDOR.
+ */
+typedef union _hw_gpio_pcor
+{
+ uint32_t U;
+ struct _hw_gpio_pcor_bitfields
+ {
+ uint32_t PTCO : 32; //!< [31:0] Port Clear Output
+ } B;
+} hw_gpio_pcor_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire GPIO_PCOR register
+ */
+//@{
+#define HW_GPIO_PCOR_ADDR(x) (REGS_GPIO_BASE(x) + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_GPIO_PCOR(x) (*(__O hw_gpio_pcor_t *) HW_GPIO_PCOR_ADDR(x))
+#define HW_GPIO_PCOR_RD(x) (HW_GPIO_PCOR(x).U)
+#define HW_GPIO_PCOR_WR(x, v) (HW_GPIO_PCOR(x).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual GPIO_PCOR bitfields
+ */
+
+/*!
+ * @name Register GPIO_PCOR, field PTCO[31:0] (WORZ)
+ *
+ * Writing to this register will update the contents of the corresponding bit in
+ * the Port Data Output Register (PDOR) as follows:
+ *
+ * Values:
+ * - 0 - Corresponding bit in PDORn does not change.
+ * - 1 - Corresponding bit in PDORn is cleared to logic 0.
+ */
+//@{
+#define BP_GPIO_PCOR_PTCO (0U) //!< Bit position for GPIO_PCOR_PTCO.
+#define BM_GPIO_PCOR_PTCO (0xFFFFFFFFU) //!< Bit mask for GPIO_PCOR_PTCO.
+#define BS_GPIO_PCOR_PTCO (32U) //!< Bit field size in bits for GPIO_PCOR_PTCO.
+
+//! @brief Format value for bitfield GPIO_PCOR_PTCO.
+#define BF_GPIO_PCOR_PTCO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PCOR_PTCO), uint32_t) & BM_GPIO_PCOR_PTCO)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PTCO field to a new value.
+#define BW_GPIO_PCOR_PTCO(x, v) (HW_GPIO_PCOR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_GPIO_PTOR - Port Toggle Output Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_GPIO_PTOR - Port Toggle Output Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_gpio_ptor
+{
+ uint32_t U;
+ struct _hw_gpio_ptor_bitfields
+ {
+ uint32_t PTTO : 32; //!< [31:0] Port Toggle Output
+ } B;
+} hw_gpio_ptor_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire GPIO_PTOR register
+ */
+//@{
+#define HW_GPIO_PTOR_ADDR(x) (REGS_GPIO_BASE(x) + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_GPIO_PTOR(x) (*(__O hw_gpio_ptor_t *) HW_GPIO_PTOR_ADDR(x))
+#define HW_GPIO_PTOR_RD(x) (HW_GPIO_PTOR(x).U)
+#define HW_GPIO_PTOR_WR(x, v) (HW_GPIO_PTOR(x).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual GPIO_PTOR bitfields
+ */
+
+/*!
+ * @name Register GPIO_PTOR, field PTTO[31:0] (WORZ)
+ *
+ * Writing to this register will update the contents of the corresponding bit in
+ * the PDOR as follows:
+ *
+ * Values:
+ * - 0 - Corresponding bit in PDORn does not change.
+ * - 1 - Corresponding bit in PDORn is set to the inverse of its existing logic
+ * state.
+ */
+//@{
+#define BP_GPIO_PTOR_PTTO (0U) //!< Bit position for GPIO_PTOR_PTTO.
+#define BM_GPIO_PTOR_PTTO (0xFFFFFFFFU) //!< Bit mask for GPIO_PTOR_PTTO.
+#define BS_GPIO_PTOR_PTTO (32U) //!< Bit field size in bits for GPIO_PTOR_PTTO.
+
+//! @brief Format value for bitfield GPIO_PTOR_PTTO.
+#define BF_GPIO_PTOR_PTTO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PTOR_PTTO), uint32_t) & BM_GPIO_PTOR_PTTO)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PTTO field to a new value.
+#define BW_GPIO_PTOR_PTTO(x, v) (HW_GPIO_PTOR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_GPIO_PDIR - Port Data Input Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_GPIO_PDIR - Port Data Input Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Do not modify pin configuration registers associated with pins not available
+ * in your selected package. All unbonded pins not available in your package will
+ * default to DISABLE state for lowest power consumption.
+ */
+typedef union _hw_gpio_pdir
+{
+ uint32_t U;
+ struct _hw_gpio_pdir_bitfields
+ {
+ uint32_t PDI : 32; //!< [31:0] Port Data Input
+ } B;
+} hw_gpio_pdir_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire GPIO_PDIR register
+ */
+//@{
+#define HW_GPIO_PDIR_ADDR(x) (REGS_GPIO_BASE(x) + 0x10U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_GPIO_PDIR(x) (*(__I hw_gpio_pdir_t *) HW_GPIO_PDIR_ADDR(x))
+#define HW_GPIO_PDIR_RD(x) (HW_GPIO_PDIR(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual GPIO_PDIR bitfields
+ */
+
+/*!
+ * @name Register GPIO_PDIR, field PDI[31:0] (RO)
+ *
+ * Reads 0 at the unimplemented pins for a particular device. Pins that are not
+ * configured for a digital function read 0. If the Port Control and Interrupt
+ * module is disabled, then the corresponding bit in PDIR does not update.
+ *
+ * Values:
+ * - 0 - Pin logic level is logic 0, or is not configured for use by digital
+ * function.
+ * - 1 - Pin logic level is logic 1.
+ */
+//@{
+#define BP_GPIO_PDIR_PDI (0U) //!< Bit position for GPIO_PDIR_PDI.
+#define BM_GPIO_PDIR_PDI (0xFFFFFFFFU) //!< Bit mask for GPIO_PDIR_PDI.
+#define BS_GPIO_PDIR_PDI (32U) //!< Bit field size in bits for GPIO_PDIR_PDI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the GPIO_PDIR_PDI field.
+#define BR_GPIO_PDIR_PDI(x) (HW_GPIO_PDIR(x).U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_GPIO_PDDR - Port Data Direction Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_GPIO_PDDR - Port Data Direction Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The PDDR configures the individual port pins for input or output.
+ */
+typedef union _hw_gpio_pddr
+{
+ uint32_t U;
+ struct _hw_gpio_pddr_bitfields
+ {
+ uint32_t PDD : 32; //!< [31:0] Port Data Direction
+ } B;
+} hw_gpio_pddr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire GPIO_PDDR register
+ */
+//@{
+#define HW_GPIO_PDDR_ADDR(x) (REGS_GPIO_BASE(x) + 0x14U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_GPIO_PDDR(x) (*(__IO hw_gpio_pddr_t *) HW_GPIO_PDDR_ADDR(x))
+#define HW_GPIO_PDDR_RD(x) (HW_GPIO_PDDR(x).U)
+#define HW_GPIO_PDDR_WR(x, v) (HW_GPIO_PDDR(x).U = (v))
+#define HW_GPIO_PDDR_SET(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) | (v)))
+#define HW_GPIO_PDDR_CLR(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) & ~(v)))
+#define HW_GPIO_PDDR_TOG(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual GPIO_PDDR bitfields
+ */
+
+/*!
+ * @name Register GPIO_PDDR, field PDD[31:0] (RW)
+ *
+ * Configures individual port pins for input or output.
+ *
+ * Values:
+ * - 0 - Pin is configured as general-purpose input, for the GPIO function.
+ * - 1 - Pin is configured as general-purpose output, for the GPIO function.
+ */
+//@{
+#define BP_GPIO_PDDR_PDD (0U) //!< Bit position for GPIO_PDDR_PDD.
+#define BM_GPIO_PDDR_PDD (0xFFFFFFFFU) //!< Bit mask for GPIO_PDDR_PDD.
+#define BS_GPIO_PDDR_PDD (32U) //!< Bit field size in bits for GPIO_PDDR_PDD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the GPIO_PDDR_PDD field.
+#define BR_GPIO_PDDR_PDD(x) (HW_GPIO_PDDR(x).U)
+#endif
+
+//! @brief Format value for bitfield GPIO_PDDR_PDD.
+#define BF_GPIO_PDDR_PDD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PDDR_PDD), uint32_t) & BM_GPIO_PDDR_PDD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PDD field to a new value.
+#define BW_GPIO_PDDR_PDD(x, v) (HW_GPIO_PDDR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_gpio_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All GPIO module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_gpio
+{
+ __IO hw_gpio_pdor_t PDOR; //!< [0x0] Port Data Output Register
+ __O hw_gpio_psor_t PSOR; //!< [0x4] Port Set Output Register
+ __O hw_gpio_pcor_t PCOR; //!< [0x8] Port Clear Output Register
+ __O hw_gpio_ptor_t PTOR; //!< [0xC] Port Toggle Output Register
+ __I hw_gpio_pdir_t PDIR; //!< [0x10] Port Data Input Register
+ __IO hw_gpio_pddr_t PDDR; //!< [0x14] Port Data Direction Register
+} hw_gpio_t;
+#pragma pack()
+
+//! @brief Macro to access all GPIO registers.
+//! @param x GPIO instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_GPIO(0)</code>.
+#define HW_GPIO(x) (*(hw_gpio_t *) REGS_GPIO_BASE(x))
+#endif
+
+#endif // __HW_GPIO_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_i2c.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,1902 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_I2C_REGISTERS_H__
+#define __HW_I2C_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 I2C
+ *
+ * Inter-Integrated Circuit
+ *
+ * Registers defined in this header file:
+ * - HW_I2C_A1 - I2C Address Register 1
+ * - HW_I2C_F - I2C Frequency Divider register
+ * - HW_I2C_C1 - I2C Control Register 1
+ * - HW_I2C_S - I2C Status register
+ * - HW_I2C_D - I2C Data I/O register
+ * - HW_I2C_C2 - I2C Control Register 2
+ * - HW_I2C_FLT - I2C Programmable Input Glitch Filter register
+ * - HW_I2C_RA - I2C Range Address register
+ * - HW_I2C_SMB - I2C SMBus Control and Status register
+ * - HW_I2C_A2 - I2C Address Register 2
+ * - HW_I2C_SLTH - I2C SCL Low Timeout Register High
+ * - HW_I2C_SLTL - I2C SCL Low Timeout Register Low
+ *
+ * - hw_i2c_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_I2C_BASE
+#define HW_I2C_INSTANCE_COUNT (3U) //!< Number of instances of the I2C module.
+#define HW_I2C0 (0U) //!< Instance number for I2C0.
+#define HW_I2C1 (1U) //!< Instance number for I2C1.
+#define HW_I2C2 (2U) //!< Instance number for I2C2.
+#define REGS_I2C0_BASE (0x40066000U) //!< Base address for I2C0.
+#define REGS_I2C1_BASE (0x40067000U) //!< Base address for I2C1.
+#define REGS_I2C2_BASE (0x400E6000U) //!< Base address for I2C2.
+
+//! @brief Table of base addresses for I2C instances.
+static const uint32_t __g_regs_I2C_base_addresses[] = {
+ REGS_I2C0_BASE,
+ REGS_I2C1_BASE,
+ REGS_I2C2_BASE,
+ };
+
+//! @brief Get the base address of I2C by instance number.
+//! @param x I2C instance number, from 0 through 2.
+#define REGS_I2C_BASE(x) (__g_regs_I2C_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of I2C.
+#define REGS_I2C_INSTANCE(b) ((b) == REGS_I2C0_BASE ? HW_I2C0 : (b) == REGS_I2C1_BASE ? HW_I2C1 : (b) == REGS_I2C2_BASE ? HW_I2C2 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2C_A1 - I2C Address Register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2C_A1 - I2C Address Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains the slave address to be used by the I2C module.
+ */
+typedef union _hw_i2c_a1
+{
+ uint8_t U;
+ struct _hw_i2c_a1_bitfields
+ {
+ uint8_t RESERVED0 : 1; //!< [0]
+ uint8_t AD : 7; //!< [7:1] Address
+ } B;
+} hw_i2c_a1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2C_A1 register
+ */
+//@{
+#define HW_I2C_A1_ADDR(x) (REGS_I2C_BASE(x) + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2C_A1(x) (*(__IO hw_i2c_a1_t *) HW_I2C_A1_ADDR(x))
+#define HW_I2C_A1_RD(x) (HW_I2C_A1(x).U)
+#define HW_I2C_A1_WR(x, v) (HW_I2C_A1(x).U = (v))
+#define HW_I2C_A1_SET(x, v) (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) | (v)))
+#define HW_I2C_A1_CLR(x, v) (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) & ~(v)))
+#define HW_I2C_A1_TOG(x, v) (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2C_A1 bitfields
+ */
+
+/*!
+ * @name Register I2C_A1, field AD[7:1] (RW)
+ *
+ * Contains the primary slave address used by the I2C module when it is
+ * addressed as a slave. This field is used in the 7-bit address scheme and the lower
+ * seven bits in the 10-bit address scheme.
+ */
+//@{
+#define BP_I2C_A1_AD (1U) //!< Bit position for I2C_A1_AD.
+#define BM_I2C_A1_AD (0xFEU) //!< Bit mask for I2C_A1_AD.
+#define BS_I2C_A1_AD (7U) //!< Bit field size in bits for I2C_A1_AD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_A1_AD field.
+#define BR_I2C_A1_AD(x) (HW_I2C_A1(x).B.AD)
+#endif
+
+//! @brief Format value for bitfield I2C_A1_AD.
+#define BF_I2C_A1_AD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_A1_AD), uint8_t) & BM_I2C_A1_AD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AD field to a new value.
+#define BW_I2C_A1_AD(x, v) (HW_I2C_A1_WR(x, (HW_I2C_A1_RD(x) & ~BM_I2C_A1_AD) | BF_I2C_A1_AD(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2C_F - I2C Frequency Divider register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2C_F - I2C Frequency Divider register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_i2c_f
+{
+ uint8_t U;
+ struct _hw_i2c_f_bitfields
+ {
+ uint8_t ICR : 6; //!< [5:0] ClockRate
+ uint8_t MULT : 2; //!< [7:6] Multiplier Factor
+ } B;
+} hw_i2c_f_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2C_F register
+ */
+//@{
+#define HW_I2C_F_ADDR(x) (REGS_I2C_BASE(x) + 0x1U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2C_F(x) (*(__IO hw_i2c_f_t *) HW_I2C_F_ADDR(x))
+#define HW_I2C_F_RD(x) (HW_I2C_F(x).U)
+#define HW_I2C_F_WR(x, v) (HW_I2C_F(x).U = (v))
+#define HW_I2C_F_SET(x, v) (HW_I2C_F_WR(x, HW_I2C_F_RD(x) | (v)))
+#define HW_I2C_F_CLR(x, v) (HW_I2C_F_WR(x, HW_I2C_F_RD(x) & ~(v)))
+#define HW_I2C_F_TOG(x, v) (HW_I2C_F_WR(x, HW_I2C_F_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2C_F bitfields
+ */
+
+/*!
+ * @name Register I2C_F, field ICR[5:0] (RW)
+ *
+ * Prescales the I2C module clock for bit rate selection. This field and the
+ * MULT field determine the I2C baud rate, the SDA hold time, the SCL start hold
+ * time, and the SCL stop hold time. For a list of values corresponding to each ICR
+ * setting, see I2C divider and hold values. The SCL divider multiplied by
+ * multiplier factor (mul) determines the I2C baud rate. I2C baud rate = I2C module
+ * clock speed (Hz)/(mul * SCL divider) The SDA hold time is the delay from the
+ * falling edge of SCL (I2C clock) to the changing of SDA (I2C data). SDA hold time =
+ * I2C module clock period (s) * mul * SDA hold value The SCL start hold time is
+ * the delay from the falling edge of SDA (I2C data) while SCL is high (start
+ * condition) to the falling edge of SCL (I2C clock). SCL start hold time = I2C
+ * module clock period (s) * mul * SCL start hold value The SCL stop hold time is
+ * the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C
+ * data) while SCL is high (stop condition). SCL stop hold time = I2C module
+ * clock period (s) * mul * SCL stop hold value For example, if the I2C module clock
+ * speed is 8 MHz, the following table shows the possible hold time values with
+ * different ICR and MULT selections to achieve an I2C baud rate of 100 kbit/s.
+ * MULT ICR Hold times (μs) SDA SCL Start SCL Stop 2h 00h 3.500 3.000 5.500 1h
+ * 07h 2.500 4.000 5.250 1h 0Bh 2.250 4.000 5.250 0h 14h 2.125 4.250 5.125 0h 18h
+ * 1.125 4.750 5.125
+ */
+//@{
+#define BP_I2C_F_ICR (0U) //!< Bit position for I2C_F_ICR.
+#define BM_I2C_F_ICR (0x3FU) //!< Bit mask for I2C_F_ICR.
+#define BS_I2C_F_ICR (6U) //!< Bit field size in bits for I2C_F_ICR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_F_ICR field.
+#define BR_I2C_F_ICR(x) (HW_I2C_F(x).B.ICR)
+#endif
+
+//! @brief Format value for bitfield I2C_F_ICR.
+#define BF_I2C_F_ICR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_F_ICR), uint8_t) & BM_I2C_F_ICR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ICR field to a new value.
+#define BW_I2C_F_ICR(x, v) (HW_I2C_F_WR(x, (HW_I2C_F_RD(x) & ~BM_I2C_F_ICR) | BF_I2C_F_ICR(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_F, field MULT[7:6] (RW)
+ *
+ * Defines the multiplier factor (mul). This factor is used along with the SCL
+ * divider to generate the I2C baud rate.
+ *
+ * Values:
+ * - 00 - mul = 1
+ * - 01 - mul = 2
+ * - 10 - mul = 4
+ * - 11 - Reserved
+ */
+//@{
+#define BP_I2C_F_MULT (6U) //!< Bit position for I2C_F_MULT.
+#define BM_I2C_F_MULT (0xC0U) //!< Bit mask for I2C_F_MULT.
+#define BS_I2C_F_MULT (2U) //!< Bit field size in bits for I2C_F_MULT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_F_MULT field.
+#define BR_I2C_F_MULT(x) (HW_I2C_F(x).B.MULT)
+#endif
+
+//! @brief Format value for bitfield I2C_F_MULT.
+#define BF_I2C_F_MULT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_F_MULT), uint8_t) & BM_I2C_F_MULT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MULT field to a new value.
+#define BW_I2C_F_MULT(x, v) (HW_I2C_F_WR(x, (HW_I2C_F_RD(x) & ~BM_I2C_F_MULT) | BF_I2C_F_MULT(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2C_C1 - I2C Control Register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2C_C1 - I2C Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_i2c_c1
+{
+ uint8_t U;
+ struct _hw_i2c_c1_bitfields
+ {
+ uint8_t DMAEN : 1; //!< [0] DMA Enable
+ uint8_t WUEN : 1; //!< [1] Wakeup Enable
+ uint8_t RSTA : 1; //!< [2] Repeat START
+ uint8_t TXAK : 1; //!< [3] Transmit Acknowledge Enable
+ uint8_t TX : 1; //!< [4] Transmit Mode Select
+ uint8_t MST : 1; //!< [5] Master Mode Select
+ uint8_t IICIE : 1; //!< [6] I2C Interrupt Enable
+ uint8_t IICEN : 1; //!< [7] I2C Enable
+ } B;
+} hw_i2c_c1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2C_C1 register
+ */
+//@{
+#define HW_I2C_C1_ADDR(x) (REGS_I2C_BASE(x) + 0x2U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2C_C1(x) (*(__IO hw_i2c_c1_t *) HW_I2C_C1_ADDR(x))
+#define HW_I2C_C1_RD(x) (HW_I2C_C1(x).U)
+#define HW_I2C_C1_WR(x, v) (HW_I2C_C1(x).U = (v))
+#define HW_I2C_C1_SET(x, v) (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) | (v)))
+#define HW_I2C_C1_CLR(x, v) (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) & ~(v)))
+#define HW_I2C_C1_TOG(x, v) (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2C_C1 bitfields
+ */
+
+/*!
+ * @name Register I2C_C1, field DMAEN[0] (RW)
+ *
+ * Enables or disables the DMA function.
+ *
+ * Values:
+ * - 0 - All DMA signalling disabled.
+ * - 1 - DMA transfer is enabled. While SMB[FACK] = 0, the following conditions
+ * trigger the DMA request: a data byte is received, and either address or
+ * data is transmitted. (ACK/NACK is automatic) the first byte received matches
+ * the A1 register or is a general call address. If any address matching
+ * occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known
+ * from master to slave, then it is not required to check S[SRW]. With this
+ * assumption, DMA can also be used in this case. In other cases, if the master
+ * reads data from the slave, then it is required to rewrite the C1 register
+ * operation. With this assumption, DMA cannot be used. When FACK = 1, an
+ * address or a data byte is transmitted.
+ */
+//@{
+#define BP_I2C_C1_DMAEN (0U) //!< Bit position for I2C_C1_DMAEN.
+#define BM_I2C_C1_DMAEN (0x01U) //!< Bit mask for I2C_C1_DMAEN.
+#define BS_I2C_C1_DMAEN (1U) //!< Bit field size in bits for I2C_C1_DMAEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_C1_DMAEN field.
+#define BR_I2C_C1_DMAEN(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_DMAEN))
+#endif
+
+//! @brief Format value for bitfield I2C_C1_DMAEN.
+#define BF_I2C_C1_DMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_DMAEN), uint8_t) & BM_I2C_C1_DMAEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMAEN field to a new value.
+#define BW_I2C_C1_DMAEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_DMAEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_C1, field WUEN[1] (RW)
+ *
+ * The I2C module can wake the MCU from low power mode with no peripheral bus
+ * running when slave address matching occurs.
+ *
+ * Values:
+ * - 0 - Normal operation. No interrupt generated when address matching in low
+ * power mode.
+ * - 1 - Enables the wakeup function in low power mode.
+ */
+//@{
+#define BP_I2C_C1_WUEN (1U) //!< Bit position for I2C_C1_WUEN.
+#define BM_I2C_C1_WUEN (0x02U) //!< Bit mask for I2C_C1_WUEN.
+#define BS_I2C_C1_WUEN (1U) //!< Bit field size in bits for I2C_C1_WUEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_C1_WUEN field.
+#define BR_I2C_C1_WUEN(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_WUEN))
+#endif
+
+//! @brief Format value for bitfield I2C_C1_WUEN.
+#define BF_I2C_C1_WUEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_WUEN), uint8_t) & BM_I2C_C1_WUEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUEN field to a new value.
+#define BW_I2C_C1_WUEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_WUEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_C1, field RSTA[2] (WORZ)
+ *
+ * Writing 1 to this bit generates a repeated START condition provided it is the
+ * current master. This bit will always be read as 0. Attempting a repeat at the
+ * wrong time results in loss of arbitration.
+ */
+//@{
+#define BP_I2C_C1_RSTA (2U) //!< Bit position for I2C_C1_RSTA.
+#define BM_I2C_C1_RSTA (0x04U) //!< Bit mask for I2C_C1_RSTA.
+#define BS_I2C_C1_RSTA (1U) //!< Bit field size in bits for I2C_C1_RSTA.
+
+//! @brief Format value for bitfield I2C_C1_RSTA.
+#define BF_I2C_C1_RSTA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_RSTA), uint8_t) & BM_I2C_C1_RSTA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RSTA field to a new value.
+#define BW_I2C_C1_RSTA(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_RSTA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_C1, field TXAK[3] (RW)
+ *
+ * Specifies the value driven onto the SDA during data acknowledge cycles for
+ * both master and slave receivers. The value of SMB[FACK] affects NACK/ACK
+ * generation. SCL is held low until TXAK is written.
+ *
+ * Values:
+ * - 0 - An acknowledge signal is sent to the bus on the following receiving
+ * byte (if FACK is cleared) or the current receiving byte (if FACK is set).
+ * - 1 - No acknowledge signal is sent to the bus on the following receiving
+ * data byte (if FACK is cleared) or the current receiving data byte (if FACK is
+ * set).
+ */
+//@{
+#define BP_I2C_C1_TXAK (3U) //!< Bit position for I2C_C1_TXAK.
+#define BM_I2C_C1_TXAK (0x08U) //!< Bit mask for I2C_C1_TXAK.
+#define BS_I2C_C1_TXAK (1U) //!< Bit field size in bits for I2C_C1_TXAK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_C1_TXAK field.
+#define BR_I2C_C1_TXAK(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TXAK))
+#endif
+
+//! @brief Format value for bitfield I2C_C1_TXAK.
+#define BF_I2C_C1_TXAK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_TXAK), uint8_t) & BM_I2C_C1_TXAK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXAK field to a new value.
+#define BW_I2C_C1_TXAK(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TXAK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_C1, field TX[4] (RW)
+ *
+ * Selects the direction of master and slave transfers. In master mode this bit
+ * must be set according to the type of transfer required. Therefore, for address
+ * cycles, this bit is always set. When addressed as a slave this bit must be
+ * set by software according to the SRW bit in the status register.
+ *
+ * Values:
+ * - 0 - Receive
+ * - 1 - Transmit
+ */
+//@{
+#define BP_I2C_C1_TX (4U) //!< Bit position for I2C_C1_TX.
+#define BM_I2C_C1_TX (0x10U) //!< Bit mask for I2C_C1_TX.
+#define BS_I2C_C1_TX (1U) //!< Bit field size in bits for I2C_C1_TX.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_C1_TX field.
+#define BR_I2C_C1_TX(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TX))
+#endif
+
+//! @brief Format value for bitfield I2C_C1_TX.
+#define BF_I2C_C1_TX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_TX), uint8_t) & BM_I2C_C1_TX)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TX field to a new value.
+#define BW_I2C_C1_TX(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TX) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_C1, field MST[5] (RW)
+ *
+ * When MST is changed from 0 to 1, a START signal is generated on the bus and
+ * master mode is selected. When this bit changes from 1 to 0, a STOP signal is
+ * generated and the mode of operation changes from master to slave.
+ *
+ * Values:
+ * - 0 - Slave mode
+ * - 1 - Master mode
+ */
+//@{
+#define BP_I2C_C1_MST (5U) //!< Bit position for I2C_C1_MST.
+#define BM_I2C_C1_MST (0x20U) //!< Bit mask for I2C_C1_MST.
+#define BS_I2C_C1_MST (1U) //!< Bit field size in bits for I2C_C1_MST.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_C1_MST field.
+#define BR_I2C_C1_MST(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_MST))
+#endif
+
+//! @brief Format value for bitfield I2C_C1_MST.
+#define BF_I2C_C1_MST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_MST), uint8_t) & BM_I2C_C1_MST)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MST field to a new value.
+#define BW_I2C_C1_MST(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_MST) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_C1, field IICIE[6] (RW)
+ *
+ * Enables I2C interrupt requests.
+ *
+ * Values:
+ * - 0 - Disabled
+ * - 1 - Enabled
+ */
+//@{
+#define BP_I2C_C1_IICIE (6U) //!< Bit position for I2C_C1_IICIE.
+#define BM_I2C_C1_IICIE (0x40U) //!< Bit mask for I2C_C1_IICIE.
+#define BS_I2C_C1_IICIE (1U) //!< Bit field size in bits for I2C_C1_IICIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_C1_IICIE field.
+#define BR_I2C_C1_IICIE(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICIE))
+#endif
+
+//! @brief Format value for bitfield I2C_C1_IICIE.
+#define BF_I2C_C1_IICIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_IICIE), uint8_t) & BM_I2C_C1_IICIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IICIE field to a new value.
+#define BW_I2C_C1_IICIE(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_C1, field IICEN[7] (RW)
+ *
+ * Enables I2C module operation.
+ *
+ * Values:
+ * - 0 - Disabled
+ * - 1 - Enabled
+ */
+//@{
+#define BP_I2C_C1_IICEN (7U) //!< Bit position for I2C_C1_IICEN.
+#define BM_I2C_C1_IICEN (0x80U) //!< Bit mask for I2C_C1_IICEN.
+#define BS_I2C_C1_IICEN (1U) //!< Bit field size in bits for I2C_C1_IICEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_C1_IICEN field.
+#define BR_I2C_C1_IICEN(x) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICEN))
+#endif
+
+//! @brief Format value for bitfield I2C_C1_IICEN.
+#define BF_I2C_C1_IICEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C1_IICEN), uint8_t) & BM_I2C_C1_IICEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IICEN field to a new value.
+#define BW_I2C_C1_IICEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2C_S - I2C Status register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2C_S - I2C Status register (RW)
+ *
+ * Reset value: 0x80U
+ */
+typedef union _hw_i2c_s
+{
+ uint8_t U;
+ struct _hw_i2c_s_bitfields
+ {
+ uint8_t RXAK : 1; //!< [0] Receive Acknowledge
+ uint8_t IICIF : 1; //!< [1] Interrupt Flag
+ uint8_t SRW : 1; //!< [2] Slave Read/Write
+ uint8_t RAM : 1; //!< [3] Range Address Match
+ uint8_t ARBL : 1; //!< [4] Arbitration Lost
+ uint8_t BUSY : 1; //!< [5] Bus Busy
+ uint8_t IAAS : 1; //!< [6] Addressed As A Slave
+ uint8_t TCF : 1; //!< [7] Transfer Complete Flag
+ } B;
+} hw_i2c_s_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2C_S register
+ */
+//@{
+#define HW_I2C_S_ADDR(x) (REGS_I2C_BASE(x) + 0x3U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2C_S(x) (*(__IO hw_i2c_s_t *) HW_I2C_S_ADDR(x))
+#define HW_I2C_S_RD(x) (HW_I2C_S(x).U)
+#define HW_I2C_S_WR(x, v) (HW_I2C_S(x).U = (v))
+#define HW_I2C_S_SET(x, v) (HW_I2C_S_WR(x, HW_I2C_S_RD(x) | (v)))
+#define HW_I2C_S_CLR(x, v) (HW_I2C_S_WR(x, HW_I2C_S_RD(x) & ~(v)))
+#define HW_I2C_S_TOG(x, v) (HW_I2C_S_WR(x, HW_I2C_S_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2C_S bitfields
+ */
+
+/*!
+ * @name Register I2C_S, field RXAK[0] (RO)
+ *
+ * Values:
+ * - 0 - Acknowledge signal was received after the completion of one byte of
+ * data transmission on the bus
+ * - 1 - No acknowledge signal detected
+ */
+//@{
+#define BP_I2C_S_RXAK (0U) //!< Bit position for I2C_S_RXAK.
+#define BM_I2C_S_RXAK (0x01U) //!< Bit mask for I2C_S_RXAK.
+#define BS_I2C_S_RXAK (1U) //!< Bit field size in bits for I2C_S_RXAK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_S_RXAK field.
+#define BR_I2C_S_RXAK(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RXAK))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_S, field IICIF[1] (W1C)
+ *
+ * This bit sets when an interrupt is pending. This bit must be cleared by
+ * software by writing 1 to it, such as in the interrupt routine. One of the following
+ * events can set this bit: One byte transfer, including ACK/NACK bit, completes
+ * if FACK is 0. An ACK or NACK is sent on the bus by writing 0 or 1 to TXAK
+ * after this bit is set in receive mode. One byte transfer, excluding ACK/NACK bit,
+ * completes if FACK is 1. Match of slave address to calling address including
+ * primary slave address, range slave address , alert response address, second
+ * slave address, or general call address. Arbitration lost In SMBus mode, any
+ * timeouts except SCL and SDA high timeouts I2C bus stop or start detection if the
+ * SSIE bit in the Input Glitch Filter register is 1 To clear the I2C bus stop or
+ * start detection interrupt: In the interrupt service routine, first clear the
+ * STOPF or STARTF bit in the Input Glitch Filter register by writing 1 to it, and
+ * then clear the IICIF bit. If this sequence is reversed, the IICIF bit is
+ * asserted again.
+ *
+ * Values:
+ * - 0 - No interrupt pending
+ * - 1 - Interrupt pending
+ */
+//@{
+#define BP_I2C_S_IICIF (1U) //!< Bit position for I2C_S_IICIF.
+#define BM_I2C_S_IICIF (0x02U) //!< Bit mask for I2C_S_IICIF.
+#define BS_I2C_S_IICIF (1U) //!< Bit field size in bits for I2C_S_IICIF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_S_IICIF field.
+#define BR_I2C_S_IICIF(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IICIF))
+#endif
+
+//! @brief Format value for bitfield I2C_S_IICIF.
+#define BF_I2C_S_IICIF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_S_IICIF), uint8_t) & BM_I2C_S_IICIF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IICIF field to a new value.
+#define BW_I2C_S_IICIF(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IICIF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_S, field SRW[2] (RO)
+ *
+ * When addressed as a slave, SRW indicates the value of the R/W command bit of
+ * the calling address sent to the master.
+ *
+ * Values:
+ * - 0 - Slave receive, master writing to slave
+ * - 1 - Slave transmit, master reading from slave
+ */
+//@{
+#define BP_I2C_S_SRW (2U) //!< Bit position for I2C_S_SRW.
+#define BM_I2C_S_SRW (0x04U) //!< Bit mask for I2C_S_SRW.
+#define BS_I2C_S_SRW (1U) //!< Bit field size in bits for I2C_S_SRW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_S_SRW field.
+#define BR_I2C_S_SRW(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_SRW))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_S, field RAM[3] (RW)
+ *
+ * This bit is set to 1 by any of the following conditions, if I2C_C2[RMEN] = 1:
+ * Any nonzero calling address is received that matches the address in the RA
+ * register. The calling address is within the range of values of the A1 and RA
+ * registers. For the RAM bit to be set to 1 correctly, C1[IICIE] must be set to 1.
+ * Writing the C1 register with any value clears this bit to 0.
+ *
+ * Values:
+ * - 0 - Not addressed
+ * - 1 - Addressed as a slave
+ */
+//@{
+#define BP_I2C_S_RAM (3U) //!< Bit position for I2C_S_RAM.
+#define BM_I2C_S_RAM (0x08U) //!< Bit mask for I2C_S_RAM.
+#define BS_I2C_S_RAM (1U) //!< Bit field size in bits for I2C_S_RAM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_S_RAM field.
+#define BR_I2C_S_RAM(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RAM))
+#endif
+
+//! @brief Format value for bitfield I2C_S_RAM.
+#define BF_I2C_S_RAM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_S_RAM), uint8_t) & BM_I2C_S_RAM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RAM field to a new value.
+#define BW_I2C_S_RAM(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RAM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_S, field ARBL[4] (W1C)
+ *
+ * This bit is set by hardware when the arbitration procedure is lost. The ARBL
+ * bit must be cleared by software, by writing 1 to it.
+ *
+ * Values:
+ * - 0 - Standard bus operation.
+ * - 1 - Loss of arbitration.
+ */
+//@{
+#define BP_I2C_S_ARBL (4U) //!< Bit position for I2C_S_ARBL.
+#define BM_I2C_S_ARBL (0x10U) //!< Bit mask for I2C_S_ARBL.
+#define BS_I2C_S_ARBL (1U) //!< Bit field size in bits for I2C_S_ARBL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_S_ARBL field.
+#define BR_I2C_S_ARBL(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_ARBL))
+#endif
+
+//! @brief Format value for bitfield I2C_S_ARBL.
+#define BF_I2C_S_ARBL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_S_ARBL), uint8_t) & BM_I2C_S_ARBL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ARBL field to a new value.
+#define BW_I2C_S_ARBL(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_ARBL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_S, field BUSY[5] (RO)
+ *
+ * Indicates the status of the bus regardless of slave or master mode. This bit
+ * is set when a START signal is detected and cleared when a STOP signal is
+ * detected.
+ *
+ * Values:
+ * - 0 - Bus is idle
+ * - 1 - Bus is busy
+ */
+//@{
+#define BP_I2C_S_BUSY (5U) //!< Bit position for I2C_S_BUSY.
+#define BM_I2C_S_BUSY (0x20U) //!< Bit mask for I2C_S_BUSY.
+#define BS_I2C_S_BUSY (1U) //!< Bit field size in bits for I2C_S_BUSY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_S_BUSY field.
+#define BR_I2C_S_BUSY(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_BUSY))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_S, field IAAS[6] (RW)
+ *
+ * This bit is set by one of the following conditions: The calling address
+ * matches the programmed primary slave address in the A1 register, or matches the
+ * range address in the RA register (which must be set to a nonzero value and under
+ * the condition I2C_C2[RMEN] = 1). C2[GCAEN] is set and a general call is
+ * received. SMB[SIICAEN] is set and the calling address matches the second programmed
+ * slave address. ALERTEN is set and an SMBus alert response address is received
+ * RMEN is set and an address is received that is within the range between the
+ * values of the A1 and RA registers. IAAS sets before the ACK bit. The CPU must
+ * check the SRW bit and set TX/RX accordingly. Writing the C1 register with any
+ * value clears this bit.
+ *
+ * Values:
+ * - 0 - Not addressed
+ * - 1 - Addressed as a slave
+ */
+//@{
+#define BP_I2C_S_IAAS (6U) //!< Bit position for I2C_S_IAAS.
+#define BM_I2C_S_IAAS (0x40U) //!< Bit mask for I2C_S_IAAS.
+#define BS_I2C_S_IAAS (1U) //!< Bit field size in bits for I2C_S_IAAS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_S_IAAS field.
+#define BR_I2C_S_IAAS(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IAAS))
+#endif
+
+//! @brief Format value for bitfield I2C_S_IAAS.
+#define BF_I2C_S_IAAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_S_IAAS), uint8_t) & BM_I2C_S_IAAS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IAAS field to a new value.
+#define BW_I2C_S_IAAS(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IAAS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_S, field TCF[7] (RO)
+ *
+ * Acknowledges a byte transfer; TCF sets on the completion of a byte transfer.
+ * This bit is valid only during or immediately following a transfer to or from
+ * the I2C module. TCF is cleared by reading the I2C data register in receive mode
+ * or by writing to the I2C data register in transmit mode.
+ *
+ * Values:
+ * - 0 - Transfer in progress
+ * - 1 - Transfer complete
+ */
+//@{
+#define BP_I2C_S_TCF (7U) //!< Bit position for I2C_S_TCF.
+#define BM_I2C_S_TCF (0x80U) //!< Bit mask for I2C_S_TCF.
+#define BS_I2C_S_TCF (1U) //!< Bit field size in bits for I2C_S_TCF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_S_TCF field.
+#define BR_I2C_S_TCF(x) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_TCF))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2C_D - I2C Data I/O register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2C_D - I2C Data I/O register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_i2c_d
+{
+ uint8_t U;
+ struct _hw_i2c_d_bitfields
+ {
+ uint8_t DATA : 8; //!< [7:0] Data
+ } B;
+} hw_i2c_d_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2C_D register
+ */
+//@{
+#define HW_I2C_D_ADDR(x) (REGS_I2C_BASE(x) + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2C_D(x) (*(__IO hw_i2c_d_t *) HW_I2C_D_ADDR(x))
+#define HW_I2C_D_RD(x) (HW_I2C_D(x).U)
+#define HW_I2C_D_WR(x, v) (HW_I2C_D(x).U = (v))
+#define HW_I2C_D_SET(x, v) (HW_I2C_D_WR(x, HW_I2C_D_RD(x) | (v)))
+#define HW_I2C_D_CLR(x, v) (HW_I2C_D_WR(x, HW_I2C_D_RD(x) & ~(v)))
+#define HW_I2C_D_TOG(x, v) (HW_I2C_D_WR(x, HW_I2C_D_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2C_D bitfields
+ */
+
+/*!
+ * @name Register I2C_D, field DATA[7:0] (RW)
+ *
+ * In master transmit mode, when data is written to this register, a data
+ * transfer is initiated. The most significant bit is sent first. In master receive
+ * mode, reading this register initiates receiving of the next byte of data. When
+ * making the transition out of master receive mode, switch the I2C mode before
+ * reading the Data register to prevent an inadvertent initiation of a master
+ * receive data transfer. In slave mode, the same functions are available after an
+ * address match occurs. The C1[TX] bit must correctly reflect the desired direction
+ * of transfer in master and slave modes for the transmission to begin. For
+ * example, if the I2C module is configured for master transmit but a master receive
+ * is desired, reading the Data register does not initiate the receive. Reading
+ * the Data register returns the last byte received while the I2C module is
+ * configured in master receive or slave receive mode. The Data register does not
+ * reflect every byte that is transmitted on the I2C bus, and neither can software
+ * verify that a byte has been written to the Data register correctly by reading it
+ * back. In master transmit mode, the first byte of data written to the Data
+ * register following assertion of MST (start bit) or assertion of RSTA (repeated
+ * start bit) is used for the address transfer and must consist of the calling
+ * address (in bits 7-1) concatenated with the required R/W bit (in position bit 0).
+ */
+//@{
+#define BP_I2C_D_DATA (0U) //!< Bit position for I2C_D_DATA.
+#define BM_I2C_D_DATA (0xFFU) //!< Bit mask for I2C_D_DATA.
+#define BS_I2C_D_DATA (8U) //!< Bit field size in bits for I2C_D_DATA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_D_DATA field.
+#define BR_I2C_D_DATA(x) (HW_I2C_D(x).U)
+#endif
+
+//! @brief Format value for bitfield I2C_D_DATA.
+#define BF_I2C_D_DATA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_D_DATA), uint8_t) & BM_I2C_D_DATA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATA field to a new value.
+#define BW_I2C_D_DATA(x, v) (HW_I2C_D_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2C_C2 - I2C Control Register 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2C_C2 - I2C Control Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_i2c_c2
+{
+ uint8_t U;
+ struct _hw_i2c_c2_bitfields
+ {
+ uint8_t AD : 3; //!< [2:0] Slave Address
+ uint8_t RMEN : 1; //!< [3] Range Address Matching Enable
+ uint8_t SBRC : 1; //!< [4] Slave Baud Rate Control
+ uint8_t HDRS : 1; //!< [5] High Drive Select
+ uint8_t ADEXT : 1; //!< [6] Address Extension
+ uint8_t GCAEN : 1; //!< [7] General Call Address Enable
+ } B;
+} hw_i2c_c2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2C_C2 register
+ */
+//@{
+#define HW_I2C_C2_ADDR(x) (REGS_I2C_BASE(x) + 0x5U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2C_C2(x) (*(__IO hw_i2c_c2_t *) HW_I2C_C2_ADDR(x))
+#define HW_I2C_C2_RD(x) (HW_I2C_C2(x).U)
+#define HW_I2C_C2_WR(x, v) (HW_I2C_C2(x).U = (v))
+#define HW_I2C_C2_SET(x, v) (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) | (v)))
+#define HW_I2C_C2_CLR(x, v) (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) & ~(v)))
+#define HW_I2C_C2_TOG(x, v) (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2C_C2 bitfields
+ */
+
+/*!
+ * @name Register I2C_C2, field AD[2:0] (RW)
+ *
+ * Contains the upper three bits of the slave address in the 10-bit address
+ * scheme. This field is valid only while the ADEXT bit is set.
+ */
+//@{
+#define BP_I2C_C2_AD (0U) //!< Bit position for I2C_C2_AD.
+#define BM_I2C_C2_AD (0x07U) //!< Bit mask for I2C_C2_AD.
+#define BS_I2C_C2_AD (3U) //!< Bit field size in bits for I2C_C2_AD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_C2_AD field.
+#define BR_I2C_C2_AD(x) (HW_I2C_C2(x).B.AD)
+#endif
+
+//! @brief Format value for bitfield I2C_C2_AD.
+#define BF_I2C_C2_AD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_AD), uint8_t) & BM_I2C_C2_AD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AD field to a new value.
+#define BW_I2C_C2_AD(x, v) (HW_I2C_C2_WR(x, (HW_I2C_C2_RD(x) & ~BM_I2C_C2_AD) | BF_I2C_C2_AD(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_C2, field RMEN[3] (RW)
+ *
+ * This bit controls the slave address matching for addresses between the values
+ * of the A1 and RA registers. When this bit is set, a slave address matching
+ * occurs for any address greater than the value of the A1 register and less than
+ * or equal to the value of the RA register.
+ *
+ * Values:
+ * - 0 - Range mode disabled. No address matching occurs for an address within
+ * the range of values of the A1 and RA registers.
+ * - 1 - Range mode enabled. Address matching occurs when a slave receives an
+ * address within the range of values of the A1 and RA registers.
+ */
+//@{
+#define BP_I2C_C2_RMEN (3U) //!< Bit position for I2C_C2_RMEN.
+#define BM_I2C_C2_RMEN (0x08U) //!< Bit mask for I2C_C2_RMEN.
+#define BS_I2C_C2_RMEN (1U) //!< Bit field size in bits for I2C_C2_RMEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_C2_RMEN field.
+#define BR_I2C_C2_RMEN(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_RMEN))
+#endif
+
+//! @brief Format value for bitfield I2C_C2_RMEN.
+#define BF_I2C_C2_RMEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_RMEN), uint8_t) & BM_I2C_C2_RMEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RMEN field to a new value.
+#define BW_I2C_C2_RMEN(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_RMEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_C2, field SBRC[4] (RW)
+ *
+ * Enables independent slave mode baud rate at maximum frequency, which forces
+ * clock stretching on SCL in very fast I2C modes. To a slave, an example of a
+ * "very fast" mode is when the master transfers at 40 kbit/s but the slave can
+ * capture the master's data at only 10 kbit/s.
+ *
+ * Values:
+ * - 0 - The slave baud rate follows the master baud rate and clock stretching
+ * may occur
+ * - 1 - Slave baud rate is independent of the master baud rate
+ */
+//@{
+#define BP_I2C_C2_SBRC (4U) //!< Bit position for I2C_C2_SBRC.
+#define BM_I2C_C2_SBRC (0x10U) //!< Bit mask for I2C_C2_SBRC.
+#define BS_I2C_C2_SBRC (1U) //!< Bit field size in bits for I2C_C2_SBRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_C2_SBRC field.
+#define BR_I2C_C2_SBRC(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_SBRC))
+#endif
+
+//! @brief Format value for bitfield I2C_C2_SBRC.
+#define BF_I2C_C2_SBRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_SBRC), uint8_t) & BM_I2C_C2_SBRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SBRC field to a new value.
+#define BW_I2C_C2_SBRC(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_SBRC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_C2, field HDRS[5] (RW)
+ *
+ * Controls the drive capability of the I2C pads.
+ *
+ * Values:
+ * - 0 - Normal drive mode
+ * - 1 - High drive mode
+ */
+//@{
+#define BP_I2C_C2_HDRS (5U) //!< Bit position for I2C_C2_HDRS.
+#define BM_I2C_C2_HDRS (0x20U) //!< Bit mask for I2C_C2_HDRS.
+#define BS_I2C_C2_HDRS (1U) //!< Bit field size in bits for I2C_C2_HDRS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_C2_HDRS field.
+#define BR_I2C_C2_HDRS(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_HDRS))
+#endif
+
+//! @brief Format value for bitfield I2C_C2_HDRS.
+#define BF_I2C_C2_HDRS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_HDRS), uint8_t) & BM_I2C_C2_HDRS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HDRS field to a new value.
+#define BW_I2C_C2_HDRS(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_HDRS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_C2, field ADEXT[6] (RW)
+ *
+ * Controls the number of bits used for the slave address.
+ *
+ * Values:
+ * - 0 - 7-bit address scheme
+ * - 1 - 10-bit address scheme
+ */
+//@{
+#define BP_I2C_C2_ADEXT (6U) //!< Bit position for I2C_C2_ADEXT.
+#define BM_I2C_C2_ADEXT (0x40U) //!< Bit mask for I2C_C2_ADEXT.
+#define BS_I2C_C2_ADEXT (1U) //!< Bit field size in bits for I2C_C2_ADEXT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_C2_ADEXT field.
+#define BR_I2C_C2_ADEXT(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_ADEXT))
+#endif
+
+//! @brief Format value for bitfield I2C_C2_ADEXT.
+#define BF_I2C_C2_ADEXT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_ADEXT), uint8_t) & BM_I2C_C2_ADEXT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADEXT field to a new value.
+#define BW_I2C_C2_ADEXT(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_ADEXT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_C2, field GCAEN[7] (RW)
+ *
+ * Enables general call address.
+ *
+ * Values:
+ * - 0 - Disabled
+ * - 1 - Enabled
+ */
+//@{
+#define BP_I2C_C2_GCAEN (7U) //!< Bit position for I2C_C2_GCAEN.
+#define BM_I2C_C2_GCAEN (0x80U) //!< Bit mask for I2C_C2_GCAEN.
+#define BS_I2C_C2_GCAEN (1U) //!< Bit field size in bits for I2C_C2_GCAEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_C2_GCAEN field.
+#define BR_I2C_C2_GCAEN(x) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_GCAEN))
+#endif
+
+//! @brief Format value for bitfield I2C_C2_GCAEN.
+#define BF_I2C_C2_GCAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_C2_GCAEN), uint8_t) & BM_I2C_C2_GCAEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GCAEN field to a new value.
+#define BW_I2C_C2_GCAEN(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_GCAEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2C_FLT - I2C Programmable Input Glitch Filter register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2C_FLT - I2C Programmable Input Glitch Filter register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_i2c_flt
+{
+ uint8_t U;
+ struct _hw_i2c_flt_bitfields
+ {
+ uint8_t FLT : 4; //!< [3:0] I2C Programmable Filter Factor
+ uint8_t STARTF : 1; //!< [4] I2C Bus Start Detect Flag
+ uint8_t SSIE : 1; //!< [5] I2C Bus Stop or Start Interrupt Enable
+ uint8_t STOPF : 1; //!< [6] I2C Bus Stop Detect Flag
+ uint8_t SHEN : 1; //!< [7] Stop Hold Enable
+ } B;
+} hw_i2c_flt_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2C_FLT register
+ */
+//@{
+#define HW_I2C_FLT_ADDR(x) (REGS_I2C_BASE(x) + 0x6U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2C_FLT(x) (*(__IO hw_i2c_flt_t *) HW_I2C_FLT_ADDR(x))
+#define HW_I2C_FLT_RD(x) (HW_I2C_FLT(x).U)
+#define HW_I2C_FLT_WR(x, v) (HW_I2C_FLT(x).U = (v))
+#define HW_I2C_FLT_SET(x, v) (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) | (v)))
+#define HW_I2C_FLT_CLR(x, v) (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) & ~(v)))
+#define HW_I2C_FLT_TOG(x, v) (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2C_FLT bitfields
+ */
+
+/*!
+ * @name Register I2C_FLT, field FLT[3:0] (RW)
+ *
+ * Controls the width of the glitch, in terms of I2C module clock cycles, that
+ * the filter must absorb. For any glitch whose size is less than or equal to this
+ * width setting, the filter does not allow the glitch to pass.
+ *
+ * Values:
+ * - 0 - No filter/bypass
+ */
+//@{
+#define BP_I2C_FLT_FLT (0U) //!< Bit position for I2C_FLT_FLT.
+#define BM_I2C_FLT_FLT (0x0FU) //!< Bit mask for I2C_FLT_FLT.
+#define BS_I2C_FLT_FLT (4U) //!< Bit field size in bits for I2C_FLT_FLT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_FLT_FLT field.
+#define BR_I2C_FLT_FLT(x) (HW_I2C_FLT(x).B.FLT)
+#endif
+
+//! @brief Format value for bitfield I2C_FLT_FLT.
+#define BF_I2C_FLT_FLT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_FLT_FLT), uint8_t) & BM_I2C_FLT_FLT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FLT field to a new value.
+#define BW_I2C_FLT_FLT(x, v) (HW_I2C_FLT_WR(x, (HW_I2C_FLT_RD(x) & ~BM_I2C_FLT_FLT) | BF_I2C_FLT_FLT(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_FLT, field STARTF[4] (W1C)
+ *
+ * Hardware sets this bit when the I2C bus's start status is detected. The
+ * STARTF bit must be cleared by writing 1 to it.
+ *
+ * Values:
+ * - 0 - No start happens on I2C bus
+ * - 1 - Start detected on I2C bus
+ */
+//@{
+#define BP_I2C_FLT_STARTF (4U) //!< Bit position for I2C_FLT_STARTF.
+#define BM_I2C_FLT_STARTF (0x10U) //!< Bit mask for I2C_FLT_STARTF.
+#define BS_I2C_FLT_STARTF (1U) //!< Bit field size in bits for I2C_FLT_STARTF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_FLT_STARTF field.
+#define BR_I2C_FLT_STARTF(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STARTF))
+#endif
+
+//! @brief Format value for bitfield I2C_FLT_STARTF.
+#define BF_I2C_FLT_STARTF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_FLT_STARTF), uint8_t) & BM_I2C_FLT_STARTF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the STARTF field to a new value.
+#define BW_I2C_FLT_STARTF(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STARTF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_FLT, field SSIE[5] (RW)
+ *
+ * This bit enables the interrupt for I2C bus stop or start detection. To clear
+ * the I2C bus stop or start detection interrupt: In the interrupt service
+ * routine, first clear the STOPF or STARTF bit by writing 1 to it, and then clear the
+ * IICIF bit in the status register. If this sequence is reversed, the IICIF bit
+ * is asserted again.
+ *
+ * Values:
+ * - 0 - Stop or start detection interrupt is disabled
+ * - 1 - Stop or start detection interrupt is enabled
+ */
+//@{
+#define BP_I2C_FLT_SSIE (5U) //!< Bit position for I2C_FLT_SSIE.
+#define BM_I2C_FLT_SSIE (0x20U) //!< Bit mask for I2C_FLT_SSIE.
+#define BS_I2C_FLT_SSIE (1U) //!< Bit field size in bits for I2C_FLT_SSIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_FLT_SSIE field.
+#define BR_I2C_FLT_SSIE(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SSIE))
+#endif
+
+//! @brief Format value for bitfield I2C_FLT_SSIE.
+#define BF_I2C_FLT_SSIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_FLT_SSIE), uint8_t) & BM_I2C_FLT_SSIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SSIE field to a new value.
+#define BW_I2C_FLT_SSIE(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SSIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_FLT, field STOPF[6] (W1C)
+ *
+ * Hardware sets this bit when the I2C bus's stop status is detected. The STOPF
+ * bit must be cleared by writing 1 to it.
+ *
+ * Values:
+ * - 0 - No stop happens on I2C bus
+ * - 1 - Stop detected on I2C bus
+ */
+//@{
+#define BP_I2C_FLT_STOPF (6U) //!< Bit position for I2C_FLT_STOPF.
+#define BM_I2C_FLT_STOPF (0x40U) //!< Bit mask for I2C_FLT_STOPF.
+#define BS_I2C_FLT_STOPF (1U) //!< Bit field size in bits for I2C_FLT_STOPF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_FLT_STOPF field.
+#define BR_I2C_FLT_STOPF(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STOPF))
+#endif
+
+//! @brief Format value for bitfield I2C_FLT_STOPF.
+#define BF_I2C_FLT_STOPF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_FLT_STOPF), uint8_t) & BM_I2C_FLT_STOPF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the STOPF field to a new value.
+#define BW_I2C_FLT_STOPF(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STOPF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_FLT, field SHEN[7] (RW)
+ *
+ * Set this bit to hold off entry to stop mode when any data transmission or
+ * reception is occurring. The following scenario explains the holdoff
+ * functionality: The I2C module is configured for a basic transfer, and the SHEN bit is set
+ * to 1. A transfer begins. The MCU signals the I2C module to enter stop mode. The
+ * byte currently being transferred, including both address and data, completes
+ * its transfer. The I2C slave or master acknowledges that the in-transfer byte
+ * completed its transfer and acknowledges the request to enter stop mode. After
+ * receiving the I2C module's acknowledgment of the request to enter stop mode,
+ * the MCU determines whether to shut off the I2C module's clock. If the SHEN bit
+ * is set to 1 and the I2C module is in an idle or disabled state when the MCU
+ * signals to enter stop mode, the module immediately acknowledges the request to
+ * enter stop mode. If SHEN is cleared to 0 and the overall data transmission or
+ * reception that was suspended by stop mode entry was incomplete: To resume the
+ * overall transmission or reception after the MCU exits stop mode, software must
+ * reinitialize the transfer by resending the address of the slave. If the I2C
+ * Control Register 1's IICIE bit was set to 1 before the MCU entered stop mode,
+ * system software will receive the interrupt triggered by the I2C Status Register's
+ * TCF bit after the MCU wakes from the stop mode.
+ *
+ * Values:
+ * - 0 - Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
+ * - 1 - Stop holdoff is enabled.
+ */
+//@{
+#define BP_I2C_FLT_SHEN (7U) //!< Bit position for I2C_FLT_SHEN.
+#define BM_I2C_FLT_SHEN (0x80U) //!< Bit mask for I2C_FLT_SHEN.
+#define BS_I2C_FLT_SHEN (1U) //!< Bit field size in bits for I2C_FLT_SHEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_FLT_SHEN field.
+#define BR_I2C_FLT_SHEN(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SHEN))
+#endif
+
+//! @brief Format value for bitfield I2C_FLT_SHEN.
+#define BF_I2C_FLT_SHEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_FLT_SHEN), uint8_t) & BM_I2C_FLT_SHEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SHEN field to a new value.
+#define BW_I2C_FLT_SHEN(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SHEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2C_RA - I2C Range Address register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2C_RA - I2C Range Address register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_i2c_ra
+{
+ uint8_t U;
+ struct _hw_i2c_ra_bitfields
+ {
+ uint8_t RESERVED0 : 1; //!< [0]
+ uint8_t RAD : 7; //!< [7:1] Range Slave Address
+ } B;
+} hw_i2c_ra_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2C_RA register
+ */
+//@{
+#define HW_I2C_RA_ADDR(x) (REGS_I2C_BASE(x) + 0x7U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2C_RA(x) (*(__IO hw_i2c_ra_t *) HW_I2C_RA_ADDR(x))
+#define HW_I2C_RA_RD(x) (HW_I2C_RA(x).U)
+#define HW_I2C_RA_WR(x, v) (HW_I2C_RA(x).U = (v))
+#define HW_I2C_RA_SET(x, v) (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) | (v)))
+#define HW_I2C_RA_CLR(x, v) (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) & ~(v)))
+#define HW_I2C_RA_TOG(x, v) (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2C_RA bitfields
+ */
+
+/*!
+ * @name Register I2C_RA, field RAD[7:1] (RW)
+ *
+ * This field contains the slave address to be used by the I2C module. The field
+ * is used in the 7-bit address scheme. If I2C_C2[RMEN] is set to 1, any nonzero
+ * value write enables this register. This register value can be considered as a
+ * maximum boundary in the range matching mode.
+ */
+//@{
+#define BP_I2C_RA_RAD (1U) //!< Bit position for I2C_RA_RAD.
+#define BM_I2C_RA_RAD (0xFEU) //!< Bit mask for I2C_RA_RAD.
+#define BS_I2C_RA_RAD (7U) //!< Bit field size in bits for I2C_RA_RAD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_RA_RAD field.
+#define BR_I2C_RA_RAD(x) (HW_I2C_RA(x).B.RAD)
+#endif
+
+//! @brief Format value for bitfield I2C_RA_RAD.
+#define BF_I2C_RA_RAD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_RA_RAD), uint8_t) & BM_I2C_RA_RAD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RAD field to a new value.
+#define BW_I2C_RA_RAD(x, v) (HW_I2C_RA_WR(x, (HW_I2C_RA_RD(x) & ~BM_I2C_RA_RAD) | BF_I2C_RA_RAD(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2C_SMB - I2C SMBus Control and Status register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2C_SMB - I2C SMBus Control and Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When the SCL and SDA signals are held high for a length of time greater than
+ * the high timeout period, the SHTF1 flag sets. Before reaching this threshold,
+ * while the system is detecting how long these signals are being held high, a
+ * master assumes that the bus is free. However, the SHTF1 bit is set to 1 in the
+ * bus transmission process with the idle bus state. When the TCKSEL bit is set,
+ * there is no need to monitor the SHTF1 bit because the bus speed is too high to
+ * match the protocol of SMBus.
+ */
+typedef union _hw_i2c_smb
+{
+ uint8_t U;
+ struct _hw_i2c_smb_bitfields
+ {
+ uint8_t SHTF2IE : 1; //!< [0] SHTF2 Interrupt Enable
+ uint8_t SHTF2 : 1; //!< [1] SCL High Timeout Flag 2
+ uint8_t SHTF1 : 1; //!< [2] SCL High Timeout Flag 1
+ uint8_t SLTF : 1; //!< [3] SCL Low Timeout Flag
+ uint8_t TCKSEL : 1; //!< [4] Timeout Counter Clock Select
+ uint8_t SIICAEN : 1; //!< [5] Second I2C Address Enable
+ uint8_t ALERTEN : 1; //!< [6] SMBus Alert Response Address Enable
+ uint8_t FACK : 1; //!< [7] Fast NACK/ACK Enable
+ } B;
+} hw_i2c_smb_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2C_SMB register
+ */
+//@{
+#define HW_I2C_SMB_ADDR(x) (REGS_I2C_BASE(x) + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2C_SMB(x) (*(__IO hw_i2c_smb_t *) HW_I2C_SMB_ADDR(x))
+#define HW_I2C_SMB_RD(x) (HW_I2C_SMB(x).U)
+#define HW_I2C_SMB_WR(x, v) (HW_I2C_SMB(x).U = (v))
+#define HW_I2C_SMB_SET(x, v) (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) | (v)))
+#define HW_I2C_SMB_CLR(x, v) (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) & ~(v)))
+#define HW_I2C_SMB_TOG(x, v) (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2C_SMB bitfields
+ */
+
+/*!
+ * @name Register I2C_SMB, field SHTF2IE[0] (RW)
+ *
+ * Enables SCL high and SDA low timeout interrupt.
+ *
+ * Values:
+ * - 0 - SHTF2 interrupt is disabled
+ * - 1 - SHTF2 interrupt is enabled
+ */
+//@{
+#define BP_I2C_SMB_SHTF2IE (0U) //!< Bit position for I2C_SMB_SHTF2IE.
+#define BM_I2C_SMB_SHTF2IE (0x01U) //!< Bit mask for I2C_SMB_SHTF2IE.
+#define BS_I2C_SMB_SHTF2IE (1U) //!< Bit field size in bits for I2C_SMB_SHTF2IE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_SMB_SHTF2IE field.
+#define BR_I2C_SMB_SHTF2IE(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2IE))
+#endif
+
+//! @brief Format value for bitfield I2C_SMB_SHTF2IE.
+#define BF_I2C_SMB_SHTF2IE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_SHTF2IE), uint8_t) & BM_I2C_SMB_SHTF2IE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SHTF2IE field to a new value.
+#define BW_I2C_SMB_SHTF2IE(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2IE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_SMB, field SHTF2[1] (W1C)
+ *
+ * This bit sets when SCL is held high and SDA is held low more than clock *
+ * LoValue / 512. Software clears this bit by writing 1 to it.
+ *
+ * Values:
+ * - 0 - No SCL high and SDA low timeout occurs
+ * - 1 - SCL high and SDA low timeout occurs
+ */
+//@{
+#define BP_I2C_SMB_SHTF2 (1U) //!< Bit position for I2C_SMB_SHTF2.
+#define BM_I2C_SMB_SHTF2 (0x02U) //!< Bit mask for I2C_SMB_SHTF2.
+#define BS_I2C_SMB_SHTF2 (1U) //!< Bit field size in bits for I2C_SMB_SHTF2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_SMB_SHTF2 field.
+#define BR_I2C_SMB_SHTF2(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2))
+#endif
+
+//! @brief Format value for bitfield I2C_SMB_SHTF2.
+#define BF_I2C_SMB_SHTF2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_SHTF2), uint8_t) & BM_I2C_SMB_SHTF2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SHTF2 field to a new value.
+#define BW_I2C_SMB_SHTF2(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_SMB, field SHTF1[2] (RO)
+ *
+ * This read-only bit sets when SCL and SDA are held high more than clock *
+ * LoValue / 512, which indicates the bus is free. This bit is cleared automatically.
+ *
+ * Values:
+ * - 0 - No SCL high and SDA high timeout occurs
+ * - 1 - SCL high and SDA high timeout occurs
+ */
+//@{
+#define BP_I2C_SMB_SHTF1 (2U) //!< Bit position for I2C_SMB_SHTF1.
+#define BM_I2C_SMB_SHTF1 (0x04U) //!< Bit mask for I2C_SMB_SHTF1.
+#define BS_I2C_SMB_SHTF1 (1U) //!< Bit field size in bits for I2C_SMB_SHTF1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_SMB_SHTF1 field.
+#define BR_I2C_SMB_SHTF1(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF1))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_SMB, field SLTF[3] (W1C)
+ *
+ * This bit is set when the SLT register (consisting of the SLTH and SLTL
+ * registers) is loaded with a non-zero value (LoValue) and an SCL low timeout occurs.
+ * Software clears this bit by writing a logic 1 to it. The low timeout function
+ * is disabled when the SLT register's value is 0.
+ *
+ * Values:
+ * - 0 - No low timeout occurs
+ * - 1 - Low timeout occurs
+ */
+//@{
+#define BP_I2C_SMB_SLTF (3U) //!< Bit position for I2C_SMB_SLTF.
+#define BM_I2C_SMB_SLTF (0x08U) //!< Bit mask for I2C_SMB_SLTF.
+#define BS_I2C_SMB_SLTF (1U) //!< Bit field size in bits for I2C_SMB_SLTF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_SMB_SLTF field.
+#define BR_I2C_SMB_SLTF(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SLTF))
+#endif
+
+//! @brief Format value for bitfield I2C_SMB_SLTF.
+#define BF_I2C_SMB_SLTF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_SLTF), uint8_t) & BM_I2C_SMB_SLTF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SLTF field to a new value.
+#define BW_I2C_SMB_SLTF(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SLTF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_SMB, field TCKSEL[4] (RW)
+ *
+ * Selects the clock source of the timeout counter.
+ *
+ * Values:
+ * - 0 - Timeout counter counts at the frequency of the I2C module clock / 64
+ * - 1 - Timeout counter counts at the frequency of the I2C module clock
+ */
+//@{
+#define BP_I2C_SMB_TCKSEL (4U) //!< Bit position for I2C_SMB_TCKSEL.
+#define BM_I2C_SMB_TCKSEL (0x10U) //!< Bit mask for I2C_SMB_TCKSEL.
+#define BS_I2C_SMB_TCKSEL (1U) //!< Bit field size in bits for I2C_SMB_TCKSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_SMB_TCKSEL field.
+#define BR_I2C_SMB_TCKSEL(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_TCKSEL))
+#endif
+
+//! @brief Format value for bitfield I2C_SMB_TCKSEL.
+#define BF_I2C_SMB_TCKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_TCKSEL), uint8_t) & BM_I2C_SMB_TCKSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCKSEL field to a new value.
+#define BW_I2C_SMB_TCKSEL(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_TCKSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_SMB, field SIICAEN[5] (RW)
+ *
+ * Enables or disables SMBus device default address.
+ *
+ * Values:
+ * - 0 - I2C address register 2 matching is disabled
+ * - 1 - I2C address register 2 matching is enabled
+ */
+//@{
+#define BP_I2C_SMB_SIICAEN (5U) //!< Bit position for I2C_SMB_SIICAEN.
+#define BM_I2C_SMB_SIICAEN (0x20U) //!< Bit mask for I2C_SMB_SIICAEN.
+#define BS_I2C_SMB_SIICAEN (1U) //!< Bit field size in bits for I2C_SMB_SIICAEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_SMB_SIICAEN field.
+#define BR_I2C_SMB_SIICAEN(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SIICAEN))
+#endif
+
+//! @brief Format value for bitfield I2C_SMB_SIICAEN.
+#define BF_I2C_SMB_SIICAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_SIICAEN), uint8_t) & BM_I2C_SMB_SIICAEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SIICAEN field to a new value.
+#define BW_I2C_SMB_SIICAEN(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SIICAEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_SMB, field ALERTEN[6] (RW)
+ *
+ * Enables or disables SMBus alert response address matching. After the host
+ * responds to a device that used the alert response address, you must use software
+ * to put the device's address on the bus. The alert protocol is described in the
+ * SMBus specification.
+ *
+ * Values:
+ * - 0 - SMBus alert response address matching is disabled
+ * - 1 - SMBus alert response address matching is enabled
+ */
+//@{
+#define BP_I2C_SMB_ALERTEN (6U) //!< Bit position for I2C_SMB_ALERTEN.
+#define BM_I2C_SMB_ALERTEN (0x40U) //!< Bit mask for I2C_SMB_ALERTEN.
+#define BS_I2C_SMB_ALERTEN (1U) //!< Bit field size in bits for I2C_SMB_ALERTEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_SMB_ALERTEN field.
+#define BR_I2C_SMB_ALERTEN(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_ALERTEN))
+#endif
+
+//! @brief Format value for bitfield I2C_SMB_ALERTEN.
+#define BF_I2C_SMB_ALERTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_ALERTEN), uint8_t) & BM_I2C_SMB_ALERTEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ALERTEN field to a new value.
+#define BW_I2C_SMB_ALERTEN(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_ALERTEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2C_SMB, field FACK[7] (RW)
+ *
+ * For SMBus packet error checking, the CPU must be able to issue an ACK or NACK
+ * according to the result of receiving data byte.
+ *
+ * Values:
+ * - 0 - An ACK or NACK is sent on the following receiving data byte
+ * - 1 - Writing 0 to TXAK after receiving a data byte generates an ACK. Writing
+ * 1 to TXAK after receiving a data byte generates a NACK.
+ */
+//@{
+#define BP_I2C_SMB_FACK (7U) //!< Bit position for I2C_SMB_FACK.
+#define BM_I2C_SMB_FACK (0x80U) //!< Bit mask for I2C_SMB_FACK.
+#define BS_I2C_SMB_FACK (1U) //!< Bit field size in bits for I2C_SMB_FACK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_SMB_FACK field.
+#define BR_I2C_SMB_FACK(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_FACK))
+#endif
+
+//! @brief Format value for bitfield I2C_SMB_FACK.
+#define BF_I2C_SMB_FACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SMB_FACK), uint8_t) & BM_I2C_SMB_FACK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FACK field to a new value.
+#define BW_I2C_SMB_FACK(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_FACK) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2C_A2 - I2C Address Register 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2C_A2 - I2C Address Register 2 (RW)
+ *
+ * Reset value: 0xC2U
+ */
+typedef union _hw_i2c_a2
+{
+ uint8_t U;
+ struct _hw_i2c_a2_bitfields
+ {
+ uint8_t RESERVED0 : 1; //!< [0]
+ uint8_t SAD : 7; //!< [7:1] SMBus Address
+ } B;
+} hw_i2c_a2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2C_A2 register
+ */
+//@{
+#define HW_I2C_A2_ADDR(x) (REGS_I2C_BASE(x) + 0x9U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2C_A2(x) (*(__IO hw_i2c_a2_t *) HW_I2C_A2_ADDR(x))
+#define HW_I2C_A2_RD(x) (HW_I2C_A2(x).U)
+#define HW_I2C_A2_WR(x, v) (HW_I2C_A2(x).U = (v))
+#define HW_I2C_A2_SET(x, v) (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) | (v)))
+#define HW_I2C_A2_CLR(x, v) (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) & ~(v)))
+#define HW_I2C_A2_TOG(x, v) (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2C_A2 bitfields
+ */
+
+/*!
+ * @name Register I2C_A2, field SAD[7:1] (RW)
+ *
+ * Contains the slave address used by the SMBus. This field is used on the
+ * device default address or other related addresses.
+ */
+//@{
+#define BP_I2C_A2_SAD (1U) //!< Bit position for I2C_A2_SAD.
+#define BM_I2C_A2_SAD (0xFEU) //!< Bit mask for I2C_A2_SAD.
+#define BS_I2C_A2_SAD (7U) //!< Bit field size in bits for I2C_A2_SAD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_A2_SAD field.
+#define BR_I2C_A2_SAD(x) (HW_I2C_A2(x).B.SAD)
+#endif
+
+//! @brief Format value for bitfield I2C_A2_SAD.
+#define BF_I2C_A2_SAD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_A2_SAD), uint8_t) & BM_I2C_A2_SAD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SAD field to a new value.
+#define BW_I2C_A2_SAD(x, v) (HW_I2C_A2_WR(x, (HW_I2C_A2_RD(x) & ~BM_I2C_A2_SAD) | BF_I2C_A2_SAD(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2C_SLTH - I2C SCL Low Timeout Register High
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2C_SLTH - I2C SCL Low Timeout Register High (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_i2c_slth
+{
+ uint8_t U;
+ struct _hw_i2c_slth_bitfields
+ {
+ uint8_t SSLT : 8; //!< [7:0]
+ } B;
+} hw_i2c_slth_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2C_SLTH register
+ */
+//@{
+#define HW_I2C_SLTH_ADDR(x) (REGS_I2C_BASE(x) + 0xAU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2C_SLTH(x) (*(__IO hw_i2c_slth_t *) HW_I2C_SLTH_ADDR(x))
+#define HW_I2C_SLTH_RD(x) (HW_I2C_SLTH(x).U)
+#define HW_I2C_SLTH_WR(x, v) (HW_I2C_SLTH(x).U = (v))
+#define HW_I2C_SLTH_SET(x, v) (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) | (v)))
+#define HW_I2C_SLTH_CLR(x, v) (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) & ~(v)))
+#define HW_I2C_SLTH_TOG(x, v) (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2C_SLTH bitfields
+ */
+
+/*!
+ * @name Register I2C_SLTH, field SSLT[7:0] (RW)
+ *
+ * Most significant byte of SCL low timeout value that determines the timeout
+ * period of SCL low.
+ */
+//@{
+#define BP_I2C_SLTH_SSLT (0U) //!< Bit position for I2C_SLTH_SSLT.
+#define BM_I2C_SLTH_SSLT (0xFFU) //!< Bit mask for I2C_SLTH_SSLT.
+#define BS_I2C_SLTH_SSLT (8U) //!< Bit field size in bits for I2C_SLTH_SSLT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_SLTH_SSLT field.
+#define BR_I2C_SLTH_SSLT(x) (HW_I2C_SLTH(x).U)
+#endif
+
+//! @brief Format value for bitfield I2C_SLTH_SSLT.
+#define BF_I2C_SLTH_SSLT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SLTH_SSLT), uint8_t) & BM_I2C_SLTH_SSLT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SSLT field to a new value.
+#define BW_I2C_SLTH_SSLT(x, v) (HW_I2C_SLTH_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2C_SLTL - I2C SCL Low Timeout Register Low
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2C_SLTL - I2C SCL Low Timeout Register Low (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_i2c_sltl
+{
+ uint8_t U;
+ struct _hw_i2c_sltl_bitfields
+ {
+ uint8_t SSLT : 8; //!< [7:0]
+ } B;
+} hw_i2c_sltl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2C_SLTL register
+ */
+//@{
+#define HW_I2C_SLTL_ADDR(x) (REGS_I2C_BASE(x) + 0xBU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2C_SLTL(x) (*(__IO hw_i2c_sltl_t *) HW_I2C_SLTL_ADDR(x))
+#define HW_I2C_SLTL_RD(x) (HW_I2C_SLTL(x).U)
+#define HW_I2C_SLTL_WR(x, v) (HW_I2C_SLTL(x).U = (v))
+#define HW_I2C_SLTL_SET(x, v) (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) | (v)))
+#define HW_I2C_SLTL_CLR(x, v) (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) & ~(v)))
+#define HW_I2C_SLTL_TOG(x, v) (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2C_SLTL bitfields
+ */
+
+/*!
+ * @name Register I2C_SLTL, field SSLT[7:0] (RW)
+ *
+ * Least significant byte of SCL low timeout value that determines the timeout
+ * period of SCL low.
+ */
+//@{
+#define BP_I2C_SLTL_SSLT (0U) //!< Bit position for I2C_SLTL_SSLT.
+#define BM_I2C_SLTL_SSLT (0xFFU) //!< Bit mask for I2C_SLTL_SSLT.
+#define BS_I2C_SLTL_SSLT (8U) //!< Bit field size in bits for I2C_SLTL_SSLT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2C_SLTL_SSLT field.
+#define BR_I2C_SLTL_SSLT(x) (HW_I2C_SLTL(x).U)
+#endif
+
+//! @brief Format value for bitfield I2C_SLTL_SSLT.
+#define BF_I2C_SLTL_SSLT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_I2C_SLTL_SSLT), uint8_t) & BM_I2C_SLTL_SSLT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SSLT field to a new value.
+#define BW_I2C_SLTL_SSLT(x, v) (HW_I2C_SLTL_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_i2c_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All I2C module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_i2c
+{
+ __IO hw_i2c_a1_t A1; //!< [0x0] I2C Address Register 1
+ __IO hw_i2c_f_t F; //!< [0x1] I2C Frequency Divider register
+ __IO hw_i2c_c1_t C1; //!< [0x2] I2C Control Register 1
+ __IO hw_i2c_s_t S; //!< [0x3] I2C Status register
+ __IO hw_i2c_d_t D; //!< [0x4] I2C Data I/O register
+ __IO hw_i2c_c2_t C2; //!< [0x5] I2C Control Register 2
+ __IO hw_i2c_flt_t FLT; //!< [0x6] I2C Programmable Input Glitch Filter register
+ __IO hw_i2c_ra_t RA; //!< [0x7] I2C Range Address register
+ __IO hw_i2c_smb_t SMB; //!< [0x8] I2C SMBus Control and Status register
+ __IO hw_i2c_a2_t A2; //!< [0x9] I2C Address Register 2
+ __IO hw_i2c_slth_t SLTH; //!< [0xA] I2C SCL Low Timeout Register High
+ __IO hw_i2c_sltl_t SLTL; //!< [0xB] I2C SCL Low Timeout Register Low
+} hw_i2c_t;
+#pragma pack()
+
+//! @brief Macro to access all I2C registers.
+//! @param x I2C instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_I2C(0)</code>.
+#define HW_I2C(x) (*(hw_i2c_t *) REGS_I2C_BASE(x))
+#endif
+
+#endif // __HW_I2C_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_i2s.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,3463 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_I2S_REGISTERS_H__
+#define __HW_I2S_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 I2S
+ *
+ * Inter-IC Sound / Synchronous Audio Interface
+ *
+ * Registers defined in this header file:
+ * - HW_I2S_TCSR - SAI Transmit Control Register
+ * - HW_I2S_TCR1 - SAI Transmit Configuration 1 Register
+ * - HW_I2S_TCR2 - SAI Transmit Configuration 2 Register
+ * - HW_I2S_TCR3 - SAI Transmit Configuration 3 Register
+ * - HW_I2S_TCR4 - SAI Transmit Configuration 4 Register
+ * - HW_I2S_TCR5 - SAI Transmit Configuration 5 Register
+ * - HW_I2S_TDRn - SAI Transmit Data Register
+ * - HW_I2S_TFRn - SAI Transmit FIFO Register
+ * - HW_I2S_TMR - SAI Transmit Mask Register
+ * - HW_I2S_RCSR - SAI Receive Control Register
+ * - HW_I2S_RCR1 - SAI Receive Configuration 1 Register
+ * - HW_I2S_RCR2 - SAI Receive Configuration 2 Register
+ * - HW_I2S_RCR3 - SAI Receive Configuration 3 Register
+ * - HW_I2S_RCR4 - SAI Receive Configuration 4 Register
+ * - HW_I2S_RCR5 - SAI Receive Configuration 5 Register
+ * - HW_I2S_RDRn - SAI Receive Data Register
+ * - HW_I2S_RFRn - SAI Receive FIFO Register
+ * - HW_I2S_RMR - SAI Receive Mask Register
+ * - HW_I2S_MCR - SAI MCLK Control Register
+ * - HW_I2S_MDR - SAI MCLK Divide Register
+ *
+ * - hw_i2s_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_I2S_BASE
+#define HW_I2S_INSTANCE_COUNT (1U) //!< Number of instances of the I2S module.
+#define HW_I2S0 (0U) //!< Instance number for I2S0.
+#define REGS_I2S0_BASE (0x4002F000U) //!< Base address for I2S0.
+
+//! @brief Table of base addresses for I2S instances.
+static const uint32_t __g_regs_I2S_base_addresses[] = {
+ REGS_I2S0_BASE,
+ };
+
+//! @brief Get the base address of I2S by instance number.
+//! @param x I2S instance number, from 0 through 0.
+#define REGS_I2S_BASE(x) (__g_regs_I2S_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of I2S.
+#define REGS_I2S_INSTANCE(b) ((b) == REGS_I2S0_BASE ? HW_I2S0 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_TCSR - SAI Transmit Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_TCSR - SAI Transmit Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_i2s_tcsr
+{
+ uint32_t U;
+ struct _hw_i2s_tcsr_bitfields
+ {
+ uint32_t FRDE : 1; //!< [0] FIFO Request DMA Enable
+ uint32_t FWDE : 1; //!< [1] FIFO Warning DMA Enable
+ uint32_t RESERVED0 : 6; //!< [7:2]
+ uint32_t FRIE : 1; //!< [8] FIFO Request Interrupt Enable
+ uint32_t FWIE : 1; //!< [9] FIFO Warning Interrupt Enable
+ uint32_t FEIE : 1; //!< [10] FIFO Error Interrupt Enable
+ uint32_t SEIE : 1; //!< [11] Sync Error Interrupt Enable
+ uint32_t WSIE : 1; //!< [12] Word Start Interrupt Enable
+ uint32_t RESERVED1 : 3; //!< [15:13]
+ uint32_t FRF : 1; //!< [16] FIFO Request Flag
+ uint32_t FWF : 1; //!< [17] FIFO Warning Flag
+ uint32_t FEF : 1; //!< [18] FIFO Error Flag
+ uint32_t SEF : 1; //!< [19] Sync Error Flag
+ uint32_t WSF : 1; //!< [20] Word Start Flag
+ uint32_t RESERVED2 : 3; //!< [23:21]
+ uint32_t SR : 1; //!< [24] Software Reset
+ uint32_t FR : 1; //!< [25] FIFO Reset
+ uint32_t RESERVED3 : 2; //!< [27:26]
+ uint32_t BCE : 1; //!< [28] Bit Clock Enable
+ uint32_t DBGE : 1; //!< [29] Debug Enable
+ uint32_t STOPE : 1; //!< [30] Stop Enable
+ uint32_t TE : 1; //!< [31] Transmitter Enable
+ } B;
+} hw_i2s_tcsr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_TCSR register
+ */
+//@{
+#define HW_I2S_TCSR_ADDR(x) (REGS_I2S_BASE(x) + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_TCSR(x) (*(__IO hw_i2s_tcsr_t *) HW_I2S_TCSR_ADDR(x))
+#define HW_I2S_TCSR_RD(x) (HW_I2S_TCSR(x).U)
+#define HW_I2S_TCSR_WR(x, v) (HW_I2S_TCSR(x).U = (v))
+#define HW_I2S_TCSR_SET(x, v) (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) | (v)))
+#define HW_I2S_TCSR_CLR(x, v) (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) & ~(v)))
+#define HW_I2S_TCSR_TOG(x, v) (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_TCSR bitfields
+ */
+
+/*!
+ * @name Register I2S_TCSR, field FRDE[0] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0 - Disables the DMA request.
+ * - 1 - Enables the DMA request.
+ */
+//@{
+#define BP_I2S_TCSR_FRDE (0U) //!< Bit position for I2S_TCSR_FRDE.
+#define BM_I2S_TCSR_FRDE (0x00000001U) //!< Bit mask for I2S_TCSR_FRDE.
+#define BS_I2S_TCSR_FRDE (1U) //!< Bit field size in bits for I2S_TCSR_FRDE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_FRDE field.
+#define BR_I2S_TCSR_FRDE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRDE))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_FRDE.
+#define BF_I2S_TCSR_FRDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FRDE), uint32_t) & BM_I2S_TCSR_FRDE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FRDE field to a new value.
+#define BW_I2S_TCSR_FRDE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRDE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field FWDE[1] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0 - Disables the DMA request.
+ * - 1 - Enables the DMA request.
+ */
+//@{
+#define BP_I2S_TCSR_FWDE (1U) //!< Bit position for I2S_TCSR_FWDE.
+#define BM_I2S_TCSR_FWDE (0x00000002U) //!< Bit mask for I2S_TCSR_FWDE.
+#define BS_I2S_TCSR_FWDE (1U) //!< Bit field size in bits for I2S_TCSR_FWDE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_FWDE field.
+#define BR_I2S_TCSR_FWDE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWDE))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_FWDE.
+#define BF_I2S_TCSR_FWDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FWDE), uint32_t) & BM_I2S_TCSR_FWDE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FWDE field to a new value.
+#define BW_I2S_TCSR_FWDE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWDE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field FRIE[8] (RW)
+ *
+ * Enables/disables FIFO request interrupts.
+ *
+ * Values:
+ * - 0 - Disables the interrupt.
+ * - 1 - Enables the interrupt.
+ */
+//@{
+#define BP_I2S_TCSR_FRIE (8U) //!< Bit position for I2S_TCSR_FRIE.
+#define BM_I2S_TCSR_FRIE (0x00000100U) //!< Bit mask for I2S_TCSR_FRIE.
+#define BS_I2S_TCSR_FRIE (1U) //!< Bit field size in bits for I2S_TCSR_FRIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_FRIE field.
+#define BR_I2S_TCSR_FRIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRIE))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_FRIE.
+#define BF_I2S_TCSR_FRIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FRIE), uint32_t) & BM_I2S_TCSR_FRIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FRIE field to a new value.
+#define BW_I2S_TCSR_FRIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field FWIE[9] (RW)
+ *
+ * Enables/disables FIFO warning interrupts.
+ *
+ * Values:
+ * - 0 - Disables the interrupt.
+ * - 1 - Enables the interrupt.
+ */
+//@{
+#define BP_I2S_TCSR_FWIE (9U) //!< Bit position for I2S_TCSR_FWIE.
+#define BM_I2S_TCSR_FWIE (0x00000200U) //!< Bit mask for I2S_TCSR_FWIE.
+#define BS_I2S_TCSR_FWIE (1U) //!< Bit field size in bits for I2S_TCSR_FWIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_FWIE field.
+#define BR_I2S_TCSR_FWIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWIE))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_FWIE.
+#define BF_I2S_TCSR_FWIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FWIE), uint32_t) & BM_I2S_TCSR_FWIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FWIE field to a new value.
+#define BW_I2S_TCSR_FWIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field FEIE[10] (RW)
+ *
+ * Enables/disables FIFO error interrupts.
+ *
+ * Values:
+ * - 0 - Disables the interrupt.
+ * - 1 - Enables the interrupt.
+ */
+//@{
+#define BP_I2S_TCSR_FEIE (10U) //!< Bit position for I2S_TCSR_FEIE.
+#define BM_I2S_TCSR_FEIE (0x00000400U) //!< Bit mask for I2S_TCSR_FEIE.
+#define BS_I2S_TCSR_FEIE (1U) //!< Bit field size in bits for I2S_TCSR_FEIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_FEIE field.
+#define BR_I2S_TCSR_FEIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEIE))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_FEIE.
+#define BF_I2S_TCSR_FEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FEIE), uint32_t) & BM_I2S_TCSR_FEIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FEIE field to a new value.
+#define BW_I2S_TCSR_FEIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field SEIE[11] (RW)
+ *
+ * Enables/disables sync error interrupts.
+ *
+ * Values:
+ * - 0 - Disables interrupt.
+ * - 1 - Enables interrupt.
+ */
+//@{
+#define BP_I2S_TCSR_SEIE (11U) //!< Bit position for I2S_TCSR_SEIE.
+#define BM_I2S_TCSR_SEIE (0x00000800U) //!< Bit mask for I2S_TCSR_SEIE.
+#define BS_I2S_TCSR_SEIE (1U) //!< Bit field size in bits for I2S_TCSR_SEIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_SEIE field.
+#define BR_I2S_TCSR_SEIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEIE))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_SEIE.
+#define BF_I2S_TCSR_SEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_SEIE), uint32_t) & BM_I2S_TCSR_SEIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SEIE field to a new value.
+#define BW_I2S_TCSR_SEIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field WSIE[12] (RW)
+ *
+ * Enables/disables word start interrupts.
+ *
+ * Values:
+ * - 0 - Disables interrupt.
+ * - 1 - Enables interrupt.
+ */
+//@{
+#define BP_I2S_TCSR_WSIE (12U) //!< Bit position for I2S_TCSR_WSIE.
+#define BM_I2S_TCSR_WSIE (0x00001000U) //!< Bit mask for I2S_TCSR_WSIE.
+#define BS_I2S_TCSR_WSIE (1U) //!< Bit field size in bits for I2S_TCSR_WSIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_WSIE field.
+#define BR_I2S_TCSR_WSIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSIE))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_WSIE.
+#define BF_I2S_TCSR_WSIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_WSIE), uint32_t) & BM_I2S_TCSR_WSIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WSIE field to a new value.
+#define BW_I2S_TCSR_WSIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field FRF[16] (RO)
+ *
+ * Indicates that the number of words in an enabled transmit channel FIFO is
+ * less than or equal to the transmit FIFO watermark.
+ *
+ * Values:
+ * - 0 - Transmit FIFO watermark has not been reached.
+ * - 1 - Transmit FIFO watermark has been reached.
+ */
+//@{
+#define BP_I2S_TCSR_FRF (16U) //!< Bit position for I2S_TCSR_FRF.
+#define BM_I2S_TCSR_FRF (0x00010000U) //!< Bit mask for I2S_TCSR_FRF.
+#define BS_I2S_TCSR_FRF (1U) //!< Bit field size in bits for I2S_TCSR_FRF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_FRF field.
+#define BR_I2S_TCSR_FRF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRF))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field FWF[17] (RO)
+ *
+ * Indicates that an enabled transmit FIFO is empty.
+ *
+ * Values:
+ * - 0 - No enabled transmit FIFO is empty.
+ * - 1 - Enabled transmit FIFO is empty.
+ */
+//@{
+#define BP_I2S_TCSR_FWF (17U) //!< Bit position for I2S_TCSR_FWF.
+#define BM_I2S_TCSR_FWF (0x00020000U) //!< Bit mask for I2S_TCSR_FWF.
+#define BS_I2S_TCSR_FWF (1U) //!< Bit field size in bits for I2S_TCSR_FWF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_FWF field.
+#define BR_I2S_TCSR_FWF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWF))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field FEF[18] (W1C)
+ *
+ * Indicates that an enabled transmit FIFO has underrun. Write a logic 1 to this
+ * field to clear this flag.
+ *
+ * Values:
+ * - 0 - Transmit underrun not detected.
+ * - 1 - Transmit underrun detected.
+ */
+//@{
+#define BP_I2S_TCSR_FEF (18U) //!< Bit position for I2S_TCSR_FEF.
+#define BM_I2S_TCSR_FEF (0x00040000U) //!< Bit mask for I2S_TCSR_FEF.
+#define BS_I2S_TCSR_FEF (1U) //!< Bit field size in bits for I2S_TCSR_FEF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_FEF field.
+#define BR_I2S_TCSR_FEF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEF))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_FEF.
+#define BF_I2S_TCSR_FEF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FEF), uint32_t) & BM_I2S_TCSR_FEF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FEF field to a new value.
+#define BW_I2S_TCSR_FEF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field SEF[19] (W1C)
+ *
+ * Indicates that an error in the externally-generated frame sync has been
+ * detected. Write a logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0 - Sync error not detected.
+ * - 1 - Frame sync error detected.
+ */
+//@{
+#define BP_I2S_TCSR_SEF (19U) //!< Bit position for I2S_TCSR_SEF.
+#define BM_I2S_TCSR_SEF (0x00080000U) //!< Bit mask for I2S_TCSR_SEF.
+#define BS_I2S_TCSR_SEF (1U) //!< Bit field size in bits for I2S_TCSR_SEF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_SEF field.
+#define BR_I2S_TCSR_SEF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEF))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_SEF.
+#define BF_I2S_TCSR_SEF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_SEF), uint32_t) & BM_I2S_TCSR_SEF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SEF field to a new value.
+#define BW_I2S_TCSR_SEF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field WSF[20] (W1C)
+ *
+ * Indicates that the start of the configured word has been detected. Write a
+ * logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0 - Start of word not detected.
+ * - 1 - Start of word detected.
+ */
+//@{
+#define BP_I2S_TCSR_WSF (20U) //!< Bit position for I2S_TCSR_WSF.
+#define BM_I2S_TCSR_WSF (0x00100000U) //!< Bit mask for I2S_TCSR_WSF.
+#define BS_I2S_TCSR_WSF (1U) //!< Bit field size in bits for I2S_TCSR_WSF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_WSF field.
+#define BR_I2S_TCSR_WSF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSF))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_WSF.
+#define BF_I2S_TCSR_WSF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_WSF), uint32_t) & BM_I2S_TCSR_WSF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WSF field to a new value.
+#define BW_I2S_TCSR_WSF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field SR[24] (RW)
+ *
+ * When set, resets the internal transmitter logic including the FIFO pointers.
+ * Software-visible registers are not affected, except for the status registers.
+ *
+ * Values:
+ * - 0 - No effect.
+ * - 1 - Software reset.
+ */
+//@{
+#define BP_I2S_TCSR_SR (24U) //!< Bit position for I2S_TCSR_SR.
+#define BM_I2S_TCSR_SR (0x01000000U) //!< Bit mask for I2S_TCSR_SR.
+#define BS_I2S_TCSR_SR (1U) //!< Bit field size in bits for I2S_TCSR_SR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_SR field.
+#define BR_I2S_TCSR_SR(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SR))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_SR.
+#define BF_I2S_TCSR_SR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_SR), uint32_t) & BM_I2S_TCSR_SR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SR field to a new value.
+#define BW_I2S_TCSR_SR(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field FR[25] (WORZ)
+ *
+ * Resets the FIFO pointers. Reading this field will always return zero. FIFO
+ * pointers should only be reset when the transmitter is disabled or the FIFO error
+ * flag is set.
+ *
+ * Values:
+ * - 0 - No effect.
+ * - 1 - FIFO reset.
+ */
+//@{
+#define BP_I2S_TCSR_FR (25U) //!< Bit position for I2S_TCSR_FR.
+#define BM_I2S_TCSR_FR (0x02000000U) //!< Bit mask for I2S_TCSR_FR.
+#define BS_I2S_TCSR_FR (1U) //!< Bit field size in bits for I2S_TCSR_FR.
+
+//! @brief Format value for bitfield I2S_TCSR_FR.
+#define BF_I2S_TCSR_FR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_FR), uint32_t) & BM_I2S_TCSR_FR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FR field to a new value.
+#define BW_I2S_TCSR_FR(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field BCE[28] (RW)
+ *
+ * Enables the transmit bit clock, separately from the TE. This field is
+ * automatically set whenever TE is set. When software clears this field, the transmit
+ * bit clock remains enabled, and this bit remains set, until the end of the
+ * current frame.
+ *
+ * Values:
+ * - 0 - Transmit bit clock is disabled.
+ * - 1 - Transmit bit clock is enabled.
+ */
+//@{
+#define BP_I2S_TCSR_BCE (28U) //!< Bit position for I2S_TCSR_BCE.
+#define BM_I2S_TCSR_BCE (0x10000000U) //!< Bit mask for I2S_TCSR_BCE.
+#define BS_I2S_TCSR_BCE (1U) //!< Bit field size in bits for I2S_TCSR_BCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_BCE field.
+#define BR_I2S_TCSR_BCE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_BCE))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_BCE.
+#define BF_I2S_TCSR_BCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_BCE), uint32_t) & BM_I2S_TCSR_BCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BCE field to a new value.
+#define BW_I2S_TCSR_BCE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_BCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field DBGE[29] (RW)
+ *
+ * Enables/disables transmitter operation in Debug mode. The transmit bit clock
+ * is not affected by debug mode.
+ *
+ * Values:
+ * - 0 - Transmitter is disabled in Debug mode, after completing the current
+ * frame.
+ * - 1 - Transmitter is enabled in Debug mode.
+ */
+//@{
+#define BP_I2S_TCSR_DBGE (29U) //!< Bit position for I2S_TCSR_DBGE.
+#define BM_I2S_TCSR_DBGE (0x20000000U) //!< Bit mask for I2S_TCSR_DBGE.
+#define BS_I2S_TCSR_DBGE (1U) //!< Bit field size in bits for I2S_TCSR_DBGE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_DBGE field.
+#define BR_I2S_TCSR_DBGE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_DBGE))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_DBGE.
+#define BF_I2S_TCSR_DBGE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_DBGE), uint32_t) & BM_I2S_TCSR_DBGE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DBGE field to a new value.
+#define BW_I2S_TCSR_DBGE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_DBGE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field STOPE[30] (RW)
+ *
+ * Configures transmitter operation in Stop mode. This field is ignored and the
+ * transmitter is disabled in all low-leakage stop modes.
+ *
+ * Values:
+ * - 0 - Transmitter disabled in Stop mode.
+ * - 1 - Transmitter enabled in Stop mode.
+ */
+//@{
+#define BP_I2S_TCSR_STOPE (30U) //!< Bit position for I2S_TCSR_STOPE.
+#define BM_I2S_TCSR_STOPE (0x40000000U) //!< Bit mask for I2S_TCSR_STOPE.
+#define BS_I2S_TCSR_STOPE (1U) //!< Bit field size in bits for I2S_TCSR_STOPE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_STOPE field.
+#define BR_I2S_TCSR_STOPE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_STOPE))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_STOPE.
+#define BF_I2S_TCSR_STOPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_STOPE), uint32_t) & BM_I2S_TCSR_STOPE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the STOPE field to a new value.
+#define BW_I2S_TCSR_STOPE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_STOPE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCSR, field TE[31] (RW)
+ *
+ * Enables/disables the transmitter. When software clears this field, the
+ * transmitter remains enabled, and this bit remains set, until the end of the current
+ * frame.
+ *
+ * Values:
+ * - 0 - Transmitter is disabled.
+ * - 1 - Transmitter is enabled, or transmitter has been disabled and has not
+ * yet reached end of frame.
+ */
+//@{
+#define BP_I2S_TCSR_TE (31U) //!< Bit position for I2S_TCSR_TE.
+#define BM_I2S_TCSR_TE (0x80000000U) //!< Bit mask for I2S_TCSR_TE.
+#define BS_I2S_TCSR_TE (1U) //!< Bit field size in bits for I2S_TCSR_TE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCSR_TE field.
+#define BR_I2S_TCSR_TE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_TE))
+#endif
+
+//! @brief Format value for bitfield I2S_TCSR_TE.
+#define BF_I2S_TCSR_TE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCSR_TE), uint32_t) & BM_I2S_TCSR_TE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TE field to a new value.
+#define BW_I2S_TCSR_TE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_TE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_TCR1 - SAI Transmit Configuration 1 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_TCR1 - SAI Transmit Configuration 1 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_i2s_tcr1
+{
+ uint32_t U;
+ struct _hw_i2s_tcr1_bitfields
+ {
+ uint32_t TFW : 3; //!< [2:0] Transmit FIFO Watermark
+ uint32_t RESERVED0 : 29; //!< [31:3]
+ } B;
+} hw_i2s_tcr1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_TCR1 register
+ */
+//@{
+#define HW_I2S_TCR1_ADDR(x) (REGS_I2S_BASE(x) + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_TCR1(x) (*(__IO hw_i2s_tcr1_t *) HW_I2S_TCR1_ADDR(x))
+#define HW_I2S_TCR1_RD(x) (HW_I2S_TCR1(x).U)
+#define HW_I2S_TCR1_WR(x, v) (HW_I2S_TCR1(x).U = (v))
+#define HW_I2S_TCR1_SET(x, v) (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) | (v)))
+#define HW_I2S_TCR1_CLR(x, v) (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) & ~(v)))
+#define HW_I2S_TCR1_TOG(x, v) (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_TCR1 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR1, field TFW[2:0] (RW)
+ *
+ * Configures the watermark level for all enabled transmit channels.
+ */
+//@{
+#define BP_I2S_TCR1_TFW (0U) //!< Bit position for I2S_TCR1_TFW.
+#define BM_I2S_TCR1_TFW (0x00000007U) //!< Bit mask for I2S_TCR1_TFW.
+#define BS_I2S_TCR1_TFW (3U) //!< Bit field size in bits for I2S_TCR1_TFW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR1_TFW field.
+#define BR_I2S_TCR1_TFW(x) (HW_I2S_TCR1(x).B.TFW)
+#endif
+
+//! @brief Format value for bitfield I2S_TCR1_TFW.
+#define BF_I2S_TCR1_TFW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR1_TFW), uint32_t) & BM_I2S_TCR1_TFW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TFW field to a new value.
+#define BW_I2S_TCR1_TFW(x, v) (HW_I2S_TCR1_WR(x, (HW_I2S_TCR1_RD(x) & ~BM_I2S_TCR1_TFW) | BF_I2S_TCR1_TFW(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_TCR2 - SAI Transmit Configuration 2 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_TCR2 - SAI Transmit Configuration 2 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+typedef union _hw_i2s_tcr2
+{
+ uint32_t U;
+ struct _hw_i2s_tcr2_bitfields
+ {
+ uint32_t DIV : 8; //!< [7:0] Bit Clock Divide
+ uint32_t RESERVED0 : 16; //!< [23:8]
+ uint32_t BCD : 1; //!< [24] Bit Clock Direction
+ uint32_t BCP : 1; //!< [25] Bit Clock Polarity
+ uint32_t MSEL : 2; //!< [27:26] MCLK Select
+ uint32_t BCI : 1; //!< [28] Bit Clock Input
+ uint32_t BCS : 1; //!< [29] Bit Clock Swap
+ uint32_t SYNC : 2; //!< [31:30] Synchronous Mode
+ } B;
+} hw_i2s_tcr2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_TCR2 register
+ */
+//@{
+#define HW_I2S_TCR2_ADDR(x) (REGS_I2S_BASE(x) + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_TCR2(x) (*(__IO hw_i2s_tcr2_t *) HW_I2S_TCR2_ADDR(x))
+#define HW_I2S_TCR2_RD(x) (HW_I2S_TCR2(x).U)
+#define HW_I2S_TCR2_WR(x, v) (HW_I2S_TCR2(x).U = (v))
+#define HW_I2S_TCR2_SET(x, v) (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) | (v)))
+#define HW_I2S_TCR2_CLR(x, v) (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) & ~(v)))
+#define HW_I2S_TCR2_TOG(x, v) (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_TCR2 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR2, field DIV[7:0] (RW)
+ *
+ * Divides down the audio master clock to generate the bit clock when configured
+ * for an internal bit clock. The division value is (DIV + 1) * 2.
+ */
+//@{
+#define BP_I2S_TCR2_DIV (0U) //!< Bit position for I2S_TCR2_DIV.
+#define BM_I2S_TCR2_DIV (0x000000FFU) //!< Bit mask for I2S_TCR2_DIV.
+#define BS_I2S_TCR2_DIV (8U) //!< Bit field size in bits for I2S_TCR2_DIV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR2_DIV field.
+#define BR_I2S_TCR2_DIV(x) (HW_I2S_TCR2(x).B.DIV)
+#endif
+
+//! @brief Format value for bitfield I2S_TCR2_DIV.
+#define BF_I2S_TCR2_DIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_DIV), uint32_t) & BM_I2S_TCR2_DIV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DIV field to a new value.
+#define BW_I2S_TCR2_DIV(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_DIV) | BF_I2S_TCR2_DIV(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCR2, field BCD[24] (RW)
+ *
+ * Configures the direction of the bit clock.
+ *
+ * Values:
+ * - 0 - Bit clock is generated externally in Slave mode.
+ * - 1 - Bit clock is generated internally in Master mode.
+ */
+//@{
+#define BP_I2S_TCR2_BCD (24U) //!< Bit position for I2S_TCR2_BCD.
+#define BM_I2S_TCR2_BCD (0x01000000U) //!< Bit mask for I2S_TCR2_BCD.
+#define BS_I2S_TCR2_BCD (1U) //!< Bit field size in bits for I2S_TCR2_BCD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR2_BCD field.
+#define BR_I2S_TCR2_BCD(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCD))
+#endif
+
+//! @brief Format value for bitfield I2S_TCR2_BCD.
+#define BF_I2S_TCR2_BCD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_BCD), uint32_t) & BM_I2S_TCR2_BCD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BCD field to a new value.
+#define BW_I2S_TCR2_BCD(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCR2, field BCP[25] (RW)
+ *
+ * Configures the polarity of the bit clock.
+ *
+ * Values:
+ * - 0 - Bit clock is active high with drive outputs on rising edge and sample
+ * inputs on falling edge.
+ * - 1 - Bit clock is active low with drive outputs on falling edge and sample
+ * inputs on rising edge.
+ */
+//@{
+#define BP_I2S_TCR2_BCP (25U) //!< Bit position for I2S_TCR2_BCP.
+#define BM_I2S_TCR2_BCP (0x02000000U) //!< Bit mask for I2S_TCR2_BCP.
+#define BS_I2S_TCR2_BCP (1U) //!< Bit field size in bits for I2S_TCR2_BCP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR2_BCP field.
+#define BR_I2S_TCR2_BCP(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCP))
+#endif
+
+//! @brief Format value for bitfield I2S_TCR2_BCP.
+#define BF_I2S_TCR2_BCP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_BCP), uint32_t) & BM_I2S_TCR2_BCP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BCP field to a new value.
+#define BW_I2S_TCR2_BCP(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCR2, field MSEL[27:26] (RW)
+ *
+ * Selects the audio Master Clock option used to generate an internally
+ * generated bit clock. This field has no effect when configured for an externally
+ * generated bit clock. Depending on the device, some Master Clock options might not be
+ * available. See the chip configuration details for the availability and
+ * chip-specific meaning of each option.
+ *
+ * Values:
+ * - 00 - Bus Clock selected.
+ * - 01 - Master Clock (MCLK) 1 option selected.
+ * - 10 - Master Clock (MCLK) 2 option selected.
+ * - 11 - Master Clock (MCLK) 3 option selected.
+ */
+//@{
+#define BP_I2S_TCR2_MSEL (26U) //!< Bit position for I2S_TCR2_MSEL.
+#define BM_I2S_TCR2_MSEL (0x0C000000U) //!< Bit mask for I2S_TCR2_MSEL.
+#define BS_I2S_TCR2_MSEL (2U) //!< Bit field size in bits for I2S_TCR2_MSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR2_MSEL field.
+#define BR_I2S_TCR2_MSEL(x) (HW_I2S_TCR2(x).B.MSEL)
+#endif
+
+//! @brief Format value for bitfield I2S_TCR2_MSEL.
+#define BF_I2S_TCR2_MSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_MSEL), uint32_t) & BM_I2S_TCR2_MSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MSEL field to a new value.
+#define BW_I2S_TCR2_MSEL(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_MSEL) | BF_I2S_TCR2_MSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCR2, field BCI[28] (RW)
+ *
+ * When this field is set and using an internally generated bit clock in either
+ * synchronous or asynchronous mode, the bit clock actually used by the
+ * transmitter is delayed by the pad output delay (the transmitter is clocked by the pad
+ * input as if the clock was externally generated). This has the effect of
+ * decreasing the data input setup time, but increasing the data output valid time. The
+ * slave mode timing from the datasheet should be used for the transmitter when
+ * this bit is set. In synchronous mode, this bit allows the transmitter to use
+ * the slave mode timing from the datasheet, while the receiver uses the master
+ * mode timing. This field has no effect when configured for an externally generated
+ * bit clock or when synchronous to another SAI peripheral .
+ *
+ * Values:
+ * - 0 - No effect.
+ * - 1 - Internal logic is clocked as if bit clock was externally generated.
+ */
+//@{
+#define BP_I2S_TCR2_BCI (28U) //!< Bit position for I2S_TCR2_BCI.
+#define BM_I2S_TCR2_BCI (0x10000000U) //!< Bit mask for I2S_TCR2_BCI.
+#define BS_I2S_TCR2_BCI (1U) //!< Bit field size in bits for I2S_TCR2_BCI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR2_BCI field.
+#define BR_I2S_TCR2_BCI(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCI))
+#endif
+
+//! @brief Format value for bitfield I2S_TCR2_BCI.
+#define BF_I2S_TCR2_BCI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_BCI), uint32_t) & BM_I2S_TCR2_BCI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BCI field to a new value.
+#define BW_I2S_TCR2_BCI(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCI) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCR2, field BCS[29] (RW)
+ *
+ * This field swaps the bit clock used by the transmitter. When the transmitter
+ * is configured in asynchronous mode and this bit is set, the transmitter is
+ * clocked by the receiver bit clock (SAI_RX_BCLK). This allows the transmitter and
+ * receiver to share the same bit clock, but the transmitter continues to use the
+ * transmit frame sync (SAI_TX_SYNC). When the transmitter is configured in
+ * synchronous mode, the transmitter BCS field and receiver BCS field must be set to
+ * the same value. When both are set, the transmitter and receiver are both
+ * clocked by the transmitter bit clock (SAI_TX_BCLK) but use the receiver frame sync
+ * (SAI_RX_SYNC). This field has no effect when synchronous to another SAI
+ * peripheral.
+ *
+ * Values:
+ * - 0 - Use the normal bit clock source.
+ * - 1 - Swap the bit clock source.
+ */
+//@{
+#define BP_I2S_TCR2_BCS (29U) //!< Bit position for I2S_TCR2_BCS.
+#define BM_I2S_TCR2_BCS (0x20000000U) //!< Bit mask for I2S_TCR2_BCS.
+#define BS_I2S_TCR2_BCS (1U) //!< Bit field size in bits for I2S_TCR2_BCS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR2_BCS field.
+#define BR_I2S_TCR2_BCS(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCS))
+#endif
+
+//! @brief Format value for bitfield I2S_TCR2_BCS.
+#define BF_I2S_TCR2_BCS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_BCS), uint32_t) & BM_I2S_TCR2_BCS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BCS field to a new value.
+#define BW_I2S_TCR2_BCS(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCR2, field SYNC[31:30] (RW)
+ *
+ * Configures between asynchronous and synchronous modes of operation. When
+ * configured for a synchronous mode of operation, the receiver or other SAI
+ * peripheral must be configured for asynchronous operation.
+ *
+ * Values:
+ * - 00 - Asynchronous mode.
+ * - 01 - Synchronous with receiver.
+ * - 10 - Synchronous with another SAI transmitter.
+ * - 11 - Synchronous with another SAI receiver.
+ */
+//@{
+#define BP_I2S_TCR2_SYNC (30U) //!< Bit position for I2S_TCR2_SYNC.
+#define BM_I2S_TCR2_SYNC (0xC0000000U) //!< Bit mask for I2S_TCR2_SYNC.
+#define BS_I2S_TCR2_SYNC (2U) //!< Bit field size in bits for I2S_TCR2_SYNC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR2_SYNC field.
+#define BR_I2S_TCR2_SYNC(x) (HW_I2S_TCR2(x).B.SYNC)
+#endif
+
+//! @brief Format value for bitfield I2S_TCR2_SYNC.
+#define BF_I2S_TCR2_SYNC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR2_SYNC), uint32_t) & BM_I2S_TCR2_SYNC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SYNC field to a new value.
+#define BW_I2S_TCR2_SYNC(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_SYNC) | BF_I2S_TCR2_SYNC(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_TCR3 - SAI Transmit Configuration 3 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_TCR3 - SAI Transmit Configuration 3 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+typedef union _hw_i2s_tcr3
+{
+ uint32_t U;
+ struct _hw_i2s_tcr3_bitfields
+ {
+ uint32_t WDFL : 5; //!< [4:0] Word Flag Configuration
+ uint32_t RESERVED0 : 11; //!< [15:5]
+ uint32_t TCE : 2; //!< [17:16] Transmit Channel Enable
+ uint32_t RESERVED1 : 14; //!< [31:18]
+ } B;
+} hw_i2s_tcr3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_TCR3 register
+ */
+//@{
+#define HW_I2S_TCR3_ADDR(x) (REGS_I2S_BASE(x) + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_TCR3(x) (*(__IO hw_i2s_tcr3_t *) HW_I2S_TCR3_ADDR(x))
+#define HW_I2S_TCR3_RD(x) (HW_I2S_TCR3(x).U)
+#define HW_I2S_TCR3_WR(x, v) (HW_I2S_TCR3(x).U = (v))
+#define HW_I2S_TCR3_SET(x, v) (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) | (v)))
+#define HW_I2S_TCR3_CLR(x, v) (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) & ~(v)))
+#define HW_I2S_TCR3_TOG(x, v) (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_TCR3 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR3, field WDFL[4:0] (RW)
+ *
+ * Configures which word sets the start of word flag. The value written must be
+ * one less than the word number. For example, writing 0 configures the first
+ * word in the frame. When configured to a value greater than TCR4[FRSZ], then the
+ * start of word flag is never set.
+ */
+//@{
+#define BP_I2S_TCR3_WDFL (0U) //!< Bit position for I2S_TCR3_WDFL.
+#define BM_I2S_TCR3_WDFL (0x0000001FU) //!< Bit mask for I2S_TCR3_WDFL.
+#define BS_I2S_TCR3_WDFL (5U) //!< Bit field size in bits for I2S_TCR3_WDFL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR3_WDFL field.
+#define BR_I2S_TCR3_WDFL(x) (HW_I2S_TCR3(x).B.WDFL)
+#endif
+
+//! @brief Format value for bitfield I2S_TCR3_WDFL.
+#define BF_I2S_TCR3_WDFL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR3_WDFL), uint32_t) & BM_I2S_TCR3_WDFL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WDFL field to a new value.
+#define BW_I2S_TCR3_WDFL(x, v) (HW_I2S_TCR3_WR(x, (HW_I2S_TCR3_RD(x) & ~BM_I2S_TCR3_WDFL) | BF_I2S_TCR3_WDFL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCR3, field TCE[17:16] (RW)
+ *
+ * Enables the corresponding data channel for transmit operation. A channel must
+ * be enabled before its FIFO is accessed.
+ *
+ * Values:
+ * - 0 - Transmit data channel N is disabled.
+ * - 1 - Transmit data channel N is enabled.
+ */
+//@{
+#define BP_I2S_TCR3_TCE (16U) //!< Bit position for I2S_TCR3_TCE.
+#define BM_I2S_TCR3_TCE (0x00030000U) //!< Bit mask for I2S_TCR3_TCE.
+#define BS_I2S_TCR3_TCE (2U) //!< Bit field size in bits for I2S_TCR3_TCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR3_TCE field.
+#define BR_I2S_TCR3_TCE(x) (HW_I2S_TCR3(x).B.TCE)
+#endif
+
+//! @brief Format value for bitfield I2S_TCR3_TCE.
+#define BF_I2S_TCR3_TCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR3_TCE), uint32_t) & BM_I2S_TCR3_TCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCE field to a new value.
+#define BW_I2S_TCR3_TCE(x, v) (HW_I2S_TCR3_WR(x, (HW_I2S_TCR3_RD(x) & ~BM_I2S_TCR3_TCE) | BF_I2S_TCR3_TCE(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_TCR4 - SAI Transmit Configuration 4 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_TCR4 - SAI Transmit Configuration 4 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+typedef union _hw_i2s_tcr4
+{
+ uint32_t U;
+ struct _hw_i2s_tcr4_bitfields
+ {
+ uint32_t FSD : 1; //!< [0] Frame Sync Direction
+ uint32_t FSP : 1; //!< [1] Frame Sync Polarity
+ uint32_t RESERVED0 : 1; //!< [2]
+ uint32_t FSE : 1; //!< [3] Frame Sync Early
+ uint32_t MF : 1; //!< [4] MSB First
+ uint32_t RESERVED1 : 3; //!< [7:5]
+ uint32_t SYWD : 5; //!< [12:8] Sync Width
+ uint32_t RESERVED2 : 3; //!< [15:13]
+ uint32_t FRSZ : 5; //!< [20:16] Frame size
+ uint32_t RESERVED3 : 11; //!< [31:21]
+ } B;
+} hw_i2s_tcr4_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_TCR4 register
+ */
+//@{
+#define HW_I2S_TCR4_ADDR(x) (REGS_I2S_BASE(x) + 0x10U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_TCR4(x) (*(__IO hw_i2s_tcr4_t *) HW_I2S_TCR4_ADDR(x))
+#define HW_I2S_TCR4_RD(x) (HW_I2S_TCR4(x).U)
+#define HW_I2S_TCR4_WR(x, v) (HW_I2S_TCR4(x).U = (v))
+#define HW_I2S_TCR4_SET(x, v) (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) | (v)))
+#define HW_I2S_TCR4_CLR(x, v) (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) & ~(v)))
+#define HW_I2S_TCR4_TOG(x, v) (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_TCR4 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR4, field FSD[0] (RW)
+ *
+ * Configures the direction of the frame sync.
+ *
+ * Values:
+ * - 0 - Frame sync is generated externally in Slave mode.
+ * - 1 - Frame sync is generated internally in Master mode.
+ */
+//@{
+#define BP_I2S_TCR4_FSD (0U) //!< Bit position for I2S_TCR4_FSD.
+#define BM_I2S_TCR4_FSD (0x00000001U) //!< Bit mask for I2S_TCR4_FSD.
+#define BS_I2S_TCR4_FSD (1U) //!< Bit field size in bits for I2S_TCR4_FSD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR4_FSD field.
+#define BR_I2S_TCR4_FSD(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSD))
+#endif
+
+//! @brief Format value for bitfield I2S_TCR4_FSD.
+#define BF_I2S_TCR4_FSD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_FSD), uint32_t) & BM_I2S_TCR4_FSD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FSD field to a new value.
+#define BW_I2S_TCR4_FSD(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCR4, field FSP[1] (RW)
+ *
+ * Configures the polarity of the frame sync.
+ *
+ * Values:
+ * - 0 - Frame sync is active high.
+ * - 1 - Frame sync is active low.
+ */
+//@{
+#define BP_I2S_TCR4_FSP (1U) //!< Bit position for I2S_TCR4_FSP.
+#define BM_I2S_TCR4_FSP (0x00000002U) //!< Bit mask for I2S_TCR4_FSP.
+#define BS_I2S_TCR4_FSP (1U) //!< Bit field size in bits for I2S_TCR4_FSP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR4_FSP field.
+#define BR_I2S_TCR4_FSP(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSP))
+#endif
+
+//! @brief Format value for bitfield I2S_TCR4_FSP.
+#define BF_I2S_TCR4_FSP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_FSP), uint32_t) & BM_I2S_TCR4_FSP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FSP field to a new value.
+#define BW_I2S_TCR4_FSP(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCR4, field FSE[3] (RW)
+ *
+ * Values:
+ * - 0 - Frame sync asserts with the first bit of the frame.
+ * - 1 - Frame sync asserts one bit before the first bit of the frame.
+ */
+//@{
+#define BP_I2S_TCR4_FSE (3U) //!< Bit position for I2S_TCR4_FSE.
+#define BM_I2S_TCR4_FSE (0x00000008U) //!< Bit mask for I2S_TCR4_FSE.
+#define BS_I2S_TCR4_FSE (1U) //!< Bit field size in bits for I2S_TCR4_FSE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR4_FSE field.
+#define BR_I2S_TCR4_FSE(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSE))
+#endif
+
+//! @brief Format value for bitfield I2S_TCR4_FSE.
+#define BF_I2S_TCR4_FSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_FSE), uint32_t) & BM_I2S_TCR4_FSE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FSE field to a new value.
+#define BW_I2S_TCR4_FSE(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCR4, field MF[4] (RW)
+ *
+ * Configures whether the LSB or the MSB is transmitted first.
+ *
+ * Values:
+ * - 0 - LSB is transmitted first.
+ * - 1 - MSB is transmitted first.
+ */
+//@{
+#define BP_I2S_TCR4_MF (4U) //!< Bit position for I2S_TCR4_MF.
+#define BM_I2S_TCR4_MF (0x00000010U) //!< Bit mask for I2S_TCR4_MF.
+#define BS_I2S_TCR4_MF (1U) //!< Bit field size in bits for I2S_TCR4_MF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR4_MF field.
+#define BR_I2S_TCR4_MF(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_MF))
+#endif
+
+//! @brief Format value for bitfield I2S_TCR4_MF.
+#define BF_I2S_TCR4_MF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_MF), uint32_t) & BM_I2S_TCR4_MF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MF field to a new value.
+#define BW_I2S_TCR4_MF(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_MF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCR4, field SYWD[12:8] (RW)
+ *
+ * Configures the length of the frame sync in number of bit clocks. The value
+ * written must be one less than the number of bit clocks. For example, write 0 for
+ * the frame sync to assert for one bit clock only. The sync width cannot be
+ * configured longer than the first word of the frame.
+ */
+//@{
+#define BP_I2S_TCR4_SYWD (8U) //!< Bit position for I2S_TCR4_SYWD.
+#define BM_I2S_TCR4_SYWD (0x00001F00U) //!< Bit mask for I2S_TCR4_SYWD.
+#define BS_I2S_TCR4_SYWD (5U) //!< Bit field size in bits for I2S_TCR4_SYWD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR4_SYWD field.
+#define BR_I2S_TCR4_SYWD(x) (HW_I2S_TCR4(x).B.SYWD)
+#endif
+
+//! @brief Format value for bitfield I2S_TCR4_SYWD.
+#define BF_I2S_TCR4_SYWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_SYWD), uint32_t) & BM_I2S_TCR4_SYWD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SYWD field to a new value.
+#define BW_I2S_TCR4_SYWD(x, v) (HW_I2S_TCR4_WR(x, (HW_I2S_TCR4_RD(x) & ~BM_I2S_TCR4_SYWD) | BF_I2S_TCR4_SYWD(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCR4, field FRSZ[20:16] (RW)
+ *
+ * Configures the number of words in each frame. The value written must be one
+ * less than the number of words in the frame. For example, write 0 for one word
+ * per frame. The maximum supported frame size is 32 words.
+ */
+//@{
+#define BP_I2S_TCR4_FRSZ (16U) //!< Bit position for I2S_TCR4_FRSZ.
+#define BM_I2S_TCR4_FRSZ (0x001F0000U) //!< Bit mask for I2S_TCR4_FRSZ.
+#define BS_I2S_TCR4_FRSZ (5U) //!< Bit field size in bits for I2S_TCR4_FRSZ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR4_FRSZ field.
+#define BR_I2S_TCR4_FRSZ(x) (HW_I2S_TCR4(x).B.FRSZ)
+#endif
+
+//! @brief Format value for bitfield I2S_TCR4_FRSZ.
+#define BF_I2S_TCR4_FRSZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR4_FRSZ), uint32_t) & BM_I2S_TCR4_FRSZ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FRSZ field to a new value.
+#define BW_I2S_TCR4_FRSZ(x, v) (HW_I2S_TCR4_WR(x, (HW_I2S_TCR4_RD(x) & ~BM_I2S_TCR4_FRSZ) | BF_I2S_TCR4_FRSZ(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_TCR5 - SAI Transmit Configuration 5 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_TCR5 - SAI Transmit Configuration 5 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+typedef union _hw_i2s_tcr5
+{
+ uint32_t U;
+ struct _hw_i2s_tcr5_bitfields
+ {
+ uint32_t RESERVED0 : 8; //!< [7:0]
+ uint32_t FBT : 5; //!< [12:8] First Bit Shifted
+ uint32_t RESERVED1 : 3; //!< [15:13]
+ uint32_t W0W : 5; //!< [20:16] Word 0 Width
+ uint32_t RESERVED2 : 3; //!< [23:21]
+ uint32_t WNW : 5; //!< [28:24] Word N Width
+ uint32_t RESERVED3 : 3; //!< [31:29]
+ } B;
+} hw_i2s_tcr5_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_TCR5 register
+ */
+//@{
+#define HW_I2S_TCR5_ADDR(x) (REGS_I2S_BASE(x) + 0x14U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_TCR5(x) (*(__IO hw_i2s_tcr5_t *) HW_I2S_TCR5_ADDR(x))
+#define HW_I2S_TCR5_RD(x) (HW_I2S_TCR5(x).U)
+#define HW_I2S_TCR5_WR(x, v) (HW_I2S_TCR5(x).U = (v))
+#define HW_I2S_TCR5_SET(x, v) (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) | (v)))
+#define HW_I2S_TCR5_CLR(x, v) (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) & ~(v)))
+#define HW_I2S_TCR5_TOG(x, v) (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_TCR5 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR5, field FBT[12:8] (RW)
+ *
+ * Configures the bit index for the first bit transmitted for each word in the
+ * frame. If configured for MSB First, the index of the next bit transmitted is
+ * one less than the current bit transmitted. If configured for LSB First, the
+ * index of the next bit transmitted is one more than the current bit transmitted.
+ * The value written must be greater than or equal to the word width when
+ * configured for MSB First. The value written must be less than or equal to 31-word width
+ * when configured for LSB First.
+ */
+//@{
+#define BP_I2S_TCR5_FBT (8U) //!< Bit position for I2S_TCR5_FBT.
+#define BM_I2S_TCR5_FBT (0x00001F00U) //!< Bit mask for I2S_TCR5_FBT.
+#define BS_I2S_TCR5_FBT (5U) //!< Bit field size in bits for I2S_TCR5_FBT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR5_FBT field.
+#define BR_I2S_TCR5_FBT(x) (HW_I2S_TCR5(x).B.FBT)
+#endif
+
+//! @brief Format value for bitfield I2S_TCR5_FBT.
+#define BF_I2S_TCR5_FBT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR5_FBT), uint32_t) & BM_I2S_TCR5_FBT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FBT field to a new value.
+#define BW_I2S_TCR5_FBT(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_FBT) | BF_I2S_TCR5_FBT(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCR5, field W0W[20:16] (RW)
+ *
+ * Configures the number of bits in the first word in each frame. The value
+ * written must be one less than the number of bits in the first word. Word width of
+ * less than 8 bits is not supported if there is only one word per frame.
+ */
+//@{
+#define BP_I2S_TCR5_W0W (16U) //!< Bit position for I2S_TCR5_W0W.
+#define BM_I2S_TCR5_W0W (0x001F0000U) //!< Bit mask for I2S_TCR5_W0W.
+#define BS_I2S_TCR5_W0W (5U) //!< Bit field size in bits for I2S_TCR5_W0W.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR5_W0W field.
+#define BR_I2S_TCR5_W0W(x) (HW_I2S_TCR5(x).B.W0W)
+#endif
+
+//! @brief Format value for bitfield I2S_TCR5_W0W.
+#define BF_I2S_TCR5_W0W(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR5_W0W), uint32_t) & BM_I2S_TCR5_W0W)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the W0W field to a new value.
+#define BW_I2S_TCR5_W0W(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_W0W) | BF_I2S_TCR5_W0W(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TCR5, field WNW[28:24] (RW)
+ *
+ * Configures the number of bits in each word, for each word except the first in
+ * the frame. The value written must be one less than the number of bits per
+ * word. Word width of less than 8 bits is not supported.
+ */
+//@{
+#define BP_I2S_TCR5_WNW (24U) //!< Bit position for I2S_TCR5_WNW.
+#define BM_I2S_TCR5_WNW (0x1F000000U) //!< Bit mask for I2S_TCR5_WNW.
+#define BS_I2S_TCR5_WNW (5U) //!< Bit field size in bits for I2S_TCR5_WNW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TCR5_WNW field.
+#define BR_I2S_TCR5_WNW(x) (HW_I2S_TCR5(x).B.WNW)
+#endif
+
+//! @brief Format value for bitfield I2S_TCR5_WNW.
+#define BF_I2S_TCR5_WNW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TCR5_WNW), uint32_t) & BM_I2S_TCR5_WNW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WNW field to a new value.
+#define BW_I2S_TCR5_WNW(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_WNW) | BF_I2S_TCR5_WNW(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_TDRn - SAI Transmit Data Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_TDRn - SAI Transmit Data Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_i2s_tdrn
+{
+ uint32_t U;
+ struct _hw_i2s_tdrn_bitfields
+ {
+ uint32_t TDR : 32; //!< [31:0] Transmit Data Register
+ } B;
+} hw_i2s_tdrn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_TDRn register
+ */
+//@{
+#define HW_I2S_TDRn_COUNT (2U)
+
+#define HW_I2S_TDRn_ADDR(x, n) (REGS_I2S_BASE(x) + 0x20U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_TDRn(x, n) (*(__O hw_i2s_tdrn_t *) HW_I2S_TDRn_ADDR(x, n))
+#define HW_I2S_TDRn_RD(x, n) (HW_I2S_TDRn(x, n).U)
+#define HW_I2S_TDRn_WR(x, n, v) (HW_I2S_TDRn(x, n).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_TDRn bitfields
+ */
+
+/*!
+ * @name Register I2S_TDRn, field TDR[31:0] (WORZ)
+ *
+ * The corresponding TCR3[TCE] bit must be set before accessing the channel's
+ * transmit data register. Writes to this register when the transmit FIFO is not
+ * full will push the data written into the transmit data FIFO. Writes to this
+ * register when the transmit FIFO is full are ignored.
+ */
+//@{
+#define BP_I2S_TDRn_TDR (0U) //!< Bit position for I2S_TDRn_TDR.
+#define BM_I2S_TDRn_TDR (0xFFFFFFFFU) //!< Bit mask for I2S_TDRn_TDR.
+#define BS_I2S_TDRn_TDR (32U) //!< Bit field size in bits for I2S_TDRn_TDR.
+
+//! @brief Format value for bitfield I2S_TDRn_TDR.
+#define BF_I2S_TDRn_TDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TDRn_TDR), uint32_t) & BM_I2S_TDRn_TDR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TDR field to a new value.
+#define BW_I2S_TDRn_TDR(x, n, v) (HW_I2S_TDRn_WR(x, n, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_TFRn - SAI Transmit FIFO Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_TFRn - SAI Transmit FIFO Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MSB of the read and write pointers is used to distinguish between FIFO
+ * full and empty conditions. If the read and write pointers are identical, then
+ * the FIFO is empty. If the read and write pointers are identical except for the
+ * MSB, then the FIFO is full.
+ */
+typedef union _hw_i2s_tfrn
+{
+ uint32_t U;
+ struct _hw_i2s_tfrn_bitfields
+ {
+ uint32_t RFP : 4; //!< [3:0] Read FIFO Pointer
+ uint32_t RESERVED0 : 12; //!< [15:4]
+ uint32_t WFP : 4; //!< [19:16] Write FIFO Pointer
+ uint32_t RESERVED1 : 12; //!< [31:20]
+ } B;
+} hw_i2s_tfrn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_TFRn register
+ */
+//@{
+#define HW_I2S_TFRn_COUNT (2U)
+
+#define HW_I2S_TFRn_ADDR(x, n) (REGS_I2S_BASE(x) + 0x40U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_TFRn(x, n) (*(__I hw_i2s_tfrn_t *) HW_I2S_TFRn_ADDR(x, n))
+#define HW_I2S_TFRn_RD(x, n) (HW_I2S_TFRn(x, n).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_TFRn bitfields
+ */
+
+/*!
+ * @name Register I2S_TFRn, field RFP[3:0] (RO)
+ *
+ * FIFO read pointer for transmit data channel.
+ */
+//@{
+#define BP_I2S_TFRn_RFP (0U) //!< Bit position for I2S_TFRn_RFP.
+#define BM_I2S_TFRn_RFP (0x0000000FU) //!< Bit mask for I2S_TFRn_RFP.
+#define BS_I2S_TFRn_RFP (4U) //!< Bit field size in bits for I2S_TFRn_RFP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TFRn_RFP field.
+#define BR_I2S_TFRn_RFP(x, n) (HW_I2S_TFRn(x, n).B.RFP)
+#endif
+//@}
+
+/*!
+ * @name Register I2S_TFRn, field WFP[19:16] (RO)
+ *
+ * FIFO write pointer for transmit data channel.
+ */
+//@{
+#define BP_I2S_TFRn_WFP (16U) //!< Bit position for I2S_TFRn_WFP.
+#define BM_I2S_TFRn_WFP (0x000F0000U) //!< Bit mask for I2S_TFRn_WFP.
+#define BS_I2S_TFRn_WFP (4U) //!< Bit field size in bits for I2S_TFRn_WFP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TFRn_WFP field.
+#define BR_I2S_TFRn_WFP(x, n) (HW_I2S_TFRn(x, n).B.WFP)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_TMR - SAI Transmit Mask Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_TMR - SAI Transmit Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is double-buffered and updates: When TCSR[TE] is first set At
+ * the end of each frame. This allows the masked words in each frame to change
+ * from frame to frame.
+ */
+typedef union _hw_i2s_tmr
+{
+ uint32_t U;
+ struct _hw_i2s_tmr_bitfields
+ {
+ uint32_t TWM : 32; //!< [31:0] Transmit Word Mask
+ } B;
+} hw_i2s_tmr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_TMR register
+ */
+//@{
+#define HW_I2S_TMR_ADDR(x) (REGS_I2S_BASE(x) + 0x60U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_TMR(x) (*(__IO hw_i2s_tmr_t *) HW_I2S_TMR_ADDR(x))
+#define HW_I2S_TMR_RD(x) (HW_I2S_TMR(x).U)
+#define HW_I2S_TMR_WR(x, v) (HW_I2S_TMR(x).U = (v))
+#define HW_I2S_TMR_SET(x, v) (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) | (v)))
+#define HW_I2S_TMR_CLR(x, v) (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) & ~(v)))
+#define HW_I2S_TMR_TOG(x, v) (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_TMR bitfields
+ */
+
+/*!
+ * @name Register I2S_TMR, field TWM[31:0] (RW)
+ *
+ * Configures whether the transmit word is masked (transmit data pin tristated
+ * and transmit data not read from FIFO) for the corresponding word in the frame.
+ *
+ * Values:
+ * - 0 - Word N is enabled.
+ * - 1 - Word N is masked. The transmit data pins are tri-stated when masked.
+ */
+//@{
+#define BP_I2S_TMR_TWM (0U) //!< Bit position for I2S_TMR_TWM.
+#define BM_I2S_TMR_TWM (0xFFFFFFFFU) //!< Bit mask for I2S_TMR_TWM.
+#define BS_I2S_TMR_TWM (32U) //!< Bit field size in bits for I2S_TMR_TWM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_TMR_TWM field.
+#define BR_I2S_TMR_TWM(x) (HW_I2S_TMR(x).U)
+#endif
+
+//! @brief Format value for bitfield I2S_TMR_TWM.
+#define BF_I2S_TMR_TWM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_TMR_TWM), uint32_t) & BM_I2S_TMR_TWM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TWM field to a new value.
+#define BW_I2S_TMR_TWM(x, v) (HW_I2S_TMR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_RCSR - SAI Receive Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_RCSR - SAI Receive Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_i2s_rcsr
+{
+ uint32_t U;
+ struct _hw_i2s_rcsr_bitfields
+ {
+ uint32_t FRDE : 1; //!< [0] FIFO Request DMA Enable
+ uint32_t FWDE : 1; //!< [1] FIFO Warning DMA Enable
+ uint32_t RESERVED0 : 6; //!< [7:2]
+ uint32_t FRIE : 1; //!< [8] FIFO Request Interrupt Enable
+ uint32_t FWIE : 1; //!< [9] FIFO Warning Interrupt Enable
+ uint32_t FEIE : 1; //!< [10] FIFO Error Interrupt Enable
+ uint32_t SEIE : 1; //!< [11] Sync Error Interrupt Enable
+ uint32_t WSIE : 1; //!< [12] Word Start Interrupt Enable
+ uint32_t RESERVED1 : 3; //!< [15:13]
+ uint32_t FRF : 1; //!< [16] FIFO Request Flag
+ uint32_t FWF : 1; //!< [17] FIFO Warning Flag
+ uint32_t FEF : 1; //!< [18] FIFO Error Flag
+ uint32_t SEF : 1; //!< [19] Sync Error Flag
+ uint32_t WSF : 1; //!< [20] Word Start Flag
+ uint32_t RESERVED2 : 3; //!< [23:21]
+ uint32_t SR : 1; //!< [24] Software Reset
+ uint32_t FR : 1; //!< [25] FIFO Reset
+ uint32_t RESERVED3 : 2; //!< [27:26]
+ uint32_t BCE : 1; //!< [28] Bit Clock Enable
+ uint32_t DBGE : 1; //!< [29] Debug Enable
+ uint32_t STOPE : 1; //!< [30] Stop Enable
+ uint32_t RE : 1; //!< [31] Receiver Enable
+ } B;
+} hw_i2s_rcsr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_RCSR register
+ */
+//@{
+#define HW_I2S_RCSR_ADDR(x) (REGS_I2S_BASE(x) + 0x80U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_RCSR(x) (*(__IO hw_i2s_rcsr_t *) HW_I2S_RCSR_ADDR(x))
+#define HW_I2S_RCSR_RD(x) (HW_I2S_RCSR(x).U)
+#define HW_I2S_RCSR_WR(x, v) (HW_I2S_RCSR(x).U = (v))
+#define HW_I2S_RCSR_SET(x, v) (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) | (v)))
+#define HW_I2S_RCSR_CLR(x, v) (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) & ~(v)))
+#define HW_I2S_RCSR_TOG(x, v) (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_RCSR bitfields
+ */
+
+/*!
+ * @name Register I2S_RCSR, field FRDE[0] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0 - Disables the DMA request.
+ * - 1 - Enables the DMA request.
+ */
+//@{
+#define BP_I2S_RCSR_FRDE (0U) //!< Bit position for I2S_RCSR_FRDE.
+#define BM_I2S_RCSR_FRDE (0x00000001U) //!< Bit mask for I2S_RCSR_FRDE.
+#define BS_I2S_RCSR_FRDE (1U) //!< Bit field size in bits for I2S_RCSR_FRDE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_FRDE field.
+#define BR_I2S_RCSR_FRDE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRDE))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_FRDE.
+#define BF_I2S_RCSR_FRDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FRDE), uint32_t) & BM_I2S_RCSR_FRDE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FRDE field to a new value.
+#define BW_I2S_RCSR_FRDE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRDE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field FWDE[1] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0 - Disables the DMA request.
+ * - 1 - Enables the DMA request.
+ */
+//@{
+#define BP_I2S_RCSR_FWDE (1U) //!< Bit position for I2S_RCSR_FWDE.
+#define BM_I2S_RCSR_FWDE (0x00000002U) //!< Bit mask for I2S_RCSR_FWDE.
+#define BS_I2S_RCSR_FWDE (1U) //!< Bit field size in bits for I2S_RCSR_FWDE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_FWDE field.
+#define BR_I2S_RCSR_FWDE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWDE))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_FWDE.
+#define BF_I2S_RCSR_FWDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FWDE), uint32_t) & BM_I2S_RCSR_FWDE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FWDE field to a new value.
+#define BW_I2S_RCSR_FWDE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWDE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field FRIE[8] (RW)
+ *
+ * Enables/disables FIFO request interrupts.
+ *
+ * Values:
+ * - 0 - Disables the interrupt.
+ * - 1 - Enables the interrupt.
+ */
+//@{
+#define BP_I2S_RCSR_FRIE (8U) //!< Bit position for I2S_RCSR_FRIE.
+#define BM_I2S_RCSR_FRIE (0x00000100U) //!< Bit mask for I2S_RCSR_FRIE.
+#define BS_I2S_RCSR_FRIE (1U) //!< Bit field size in bits for I2S_RCSR_FRIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_FRIE field.
+#define BR_I2S_RCSR_FRIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRIE))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_FRIE.
+#define BF_I2S_RCSR_FRIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FRIE), uint32_t) & BM_I2S_RCSR_FRIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FRIE field to a new value.
+#define BW_I2S_RCSR_FRIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field FWIE[9] (RW)
+ *
+ * Enables/disables FIFO warning interrupts.
+ *
+ * Values:
+ * - 0 - Disables the interrupt.
+ * - 1 - Enables the interrupt.
+ */
+//@{
+#define BP_I2S_RCSR_FWIE (9U) //!< Bit position for I2S_RCSR_FWIE.
+#define BM_I2S_RCSR_FWIE (0x00000200U) //!< Bit mask for I2S_RCSR_FWIE.
+#define BS_I2S_RCSR_FWIE (1U) //!< Bit field size in bits for I2S_RCSR_FWIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_FWIE field.
+#define BR_I2S_RCSR_FWIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWIE))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_FWIE.
+#define BF_I2S_RCSR_FWIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FWIE), uint32_t) & BM_I2S_RCSR_FWIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FWIE field to a new value.
+#define BW_I2S_RCSR_FWIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field FEIE[10] (RW)
+ *
+ * Enables/disables FIFO error interrupts.
+ *
+ * Values:
+ * - 0 - Disables the interrupt.
+ * - 1 - Enables the interrupt.
+ */
+//@{
+#define BP_I2S_RCSR_FEIE (10U) //!< Bit position for I2S_RCSR_FEIE.
+#define BM_I2S_RCSR_FEIE (0x00000400U) //!< Bit mask for I2S_RCSR_FEIE.
+#define BS_I2S_RCSR_FEIE (1U) //!< Bit field size in bits for I2S_RCSR_FEIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_FEIE field.
+#define BR_I2S_RCSR_FEIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEIE))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_FEIE.
+#define BF_I2S_RCSR_FEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FEIE), uint32_t) & BM_I2S_RCSR_FEIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FEIE field to a new value.
+#define BW_I2S_RCSR_FEIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field SEIE[11] (RW)
+ *
+ * Enables/disables sync error interrupts.
+ *
+ * Values:
+ * - 0 - Disables interrupt.
+ * - 1 - Enables interrupt.
+ */
+//@{
+#define BP_I2S_RCSR_SEIE (11U) //!< Bit position for I2S_RCSR_SEIE.
+#define BM_I2S_RCSR_SEIE (0x00000800U) //!< Bit mask for I2S_RCSR_SEIE.
+#define BS_I2S_RCSR_SEIE (1U) //!< Bit field size in bits for I2S_RCSR_SEIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_SEIE field.
+#define BR_I2S_RCSR_SEIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEIE))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_SEIE.
+#define BF_I2S_RCSR_SEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_SEIE), uint32_t) & BM_I2S_RCSR_SEIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SEIE field to a new value.
+#define BW_I2S_RCSR_SEIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field WSIE[12] (RW)
+ *
+ * Enables/disables word start interrupts.
+ *
+ * Values:
+ * - 0 - Disables interrupt.
+ * - 1 - Enables interrupt.
+ */
+//@{
+#define BP_I2S_RCSR_WSIE (12U) //!< Bit position for I2S_RCSR_WSIE.
+#define BM_I2S_RCSR_WSIE (0x00001000U) //!< Bit mask for I2S_RCSR_WSIE.
+#define BS_I2S_RCSR_WSIE (1U) //!< Bit field size in bits for I2S_RCSR_WSIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_WSIE field.
+#define BR_I2S_RCSR_WSIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSIE))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_WSIE.
+#define BF_I2S_RCSR_WSIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_WSIE), uint32_t) & BM_I2S_RCSR_WSIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WSIE field to a new value.
+#define BW_I2S_RCSR_WSIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field FRF[16] (RO)
+ *
+ * Indicates that the number of words in an enabled receive channel FIFO is
+ * greater than the receive FIFO watermark.
+ *
+ * Values:
+ * - 0 - Receive FIFO watermark not reached.
+ * - 1 - Receive FIFO watermark has been reached.
+ */
+//@{
+#define BP_I2S_RCSR_FRF (16U) //!< Bit position for I2S_RCSR_FRF.
+#define BM_I2S_RCSR_FRF (0x00010000U) //!< Bit mask for I2S_RCSR_FRF.
+#define BS_I2S_RCSR_FRF (1U) //!< Bit field size in bits for I2S_RCSR_FRF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_FRF field.
+#define BR_I2S_RCSR_FRF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRF))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field FWF[17] (RO)
+ *
+ * Indicates that an enabled receive FIFO is full.
+ *
+ * Values:
+ * - 0 - No enabled receive FIFO is full.
+ * - 1 - Enabled receive FIFO is full.
+ */
+//@{
+#define BP_I2S_RCSR_FWF (17U) //!< Bit position for I2S_RCSR_FWF.
+#define BM_I2S_RCSR_FWF (0x00020000U) //!< Bit mask for I2S_RCSR_FWF.
+#define BS_I2S_RCSR_FWF (1U) //!< Bit field size in bits for I2S_RCSR_FWF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_FWF field.
+#define BR_I2S_RCSR_FWF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWF))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field FEF[18] (W1C)
+ *
+ * Indicates that an enabled receive FIFO has overflowed. Write a logic 1 to
+ * this field to clear this flag.
+ *
+ * Values:
+ * - 0 - Receive overflow not detected.
+ * - 1 - Receive overflow detected.
+ */
+//@{
+#define BP_I2S_RCSR_FEF (18U) //!< Bit position for I2S_RCSR_FEF.
+#define BM_I2S_RCSR_FEF (0x00040000U) //!< Bit mask for I2S_RCSR_FEF.
+#define BS_I2S_RCSR_FEF (1U) //!< Bit field size in bits for I2S_RCSR_FEF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_FEF field.
+#define BR_I2S_RCSR_FEF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEF))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_FEF.
+#define BF_I2S_RCSR_FEF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FEF), uint32_t) & BM_I2S_RCSR_FEF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FEF field to a new value.
+#define BW_I2S_RCSR_FEF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field SEF[19] (W1C)
+ *
+ * Indicates that an error in the externally-generated frame sync has been
+ * detected. Write a logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0 - Sync error not detected.
+ * - 1 - Frame sync error detected.
+ */
+//@{
+#define BP_I2S_RCSR_SEF (19U) //!< Bit position for I2S_RCSR_SEF.
+#define BM_I2S_RCSR_SEF (0x00080000U) //!< Bit mask for I2S_RCSR_SEF.
+#define BS_I2S_RCSR_SEF (1U) //!< Bit field size in bits for I2S_RCSR_SEF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_SEF field.
+#define BR_I2S_RCSR_SEF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEF))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_SEF.
+#define BF_I2S_RCSR_SEF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_SEF), uint32_t) & BM_I2S_RCSR_SEF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SEF field to a new value.
+#define BW_I2S_RCSR_SEF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field WSF[20] (W1C)
+ *
+ * Indicates that the start of the configured word has been detected. Write a
+ * logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0 - Start of word not detected.
+ * - 1 - Start of word detected.
+ */
+//@{
+#define BP_I2S_RCSR_WSF (20U) //!< Bit position for I2S_RCSR_WSF.
+#define BM_I2S_RCSR_WSF (0x00100000U) //!< Bit mask for I2S_RCSR_WSF.
+#define BS_I2S_RCSR_WSF (1U) //!< Bit field size in bits for I2S_RCSR_WSF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_WSF field.
+#define BR_I2S_RCSR_WSF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSF))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_WSF.
+#define BF_I2S_RCSR_WSF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_WSF), uint32_t) & BM_I2S_RCSR_WSF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WSF field to a new value.
+#define BW_I2S_RCSR_WSF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field SR[24] (RW)
+ *
+ * Resets the internal receiver logic including the FIFO pointers.
+ * Software-visible registers are not affected, except for the status registers.
+ *
+ * Values:
+ * - 0 - No effect.
+ * - 1 - Software reset.
+ */
+//@{
+#define BP_I2S_RCSR_SR (24U) //!< Bit position for I2S_RCSR_SR.
+#define BM_I2S_RCSR_SR (0x01000000U) //!< Bit mask for I2S_RCSR_SR.
+#define BS_I2S_RCSR_SR (1U) //!< Bit field size in bits for I2S_RCSR_SR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_SR field.
+#define BR_I2S_RCSR_SR(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SR))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_SR.
+#define BF_I2S_RCSR_SR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_SR), uint32_t) & BM_I2S_RCSR_SR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SR field to a new value.
+#define BW_I2S_RCSR_SR(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field FR[25] (WORZ)
+ *
+ * Resets the FIFO pointers. Reading this field will always return zero. FIFO
+ * pointers should only be reset when the receiver is disabled or the FIFO error
+ * flag is set.
+ *
+ * Values:
+ * - 0 - No effect.
+ * - 1 - FIFO reset.
+ */
+//@{
+#define BP_I2S_RCSR_FR (25U) //!< Bit position for I2S_RCSR_FR.
+#define BM_I2S_RCSR_FR (0x02000000U) //!< Bit mask for I2S_RCSR_FR.
+#define BS_I2S_RCSR_FR (1U) //!< Bit field size in bits for I2S_RCSR_FR.
+
+//! @brief Format value for bitfield I2S_RCSR_FR.
+#define BF_I2S_RCSR_FR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_FR), uint32_t) & BM_I2S_RCSR_FR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FR field to a new value.
+#define BW_I2S_RCSR_FR(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field BCE[28] (RW)
+ *
+ * Enables the receive bit clock, separately from RE. This field is
+ * automatically set whenever RE is set. When software clears this field, the receive bit
+ * clock remains enabled, and this field remains set, until the end of the current
+ * frame.
+ *
+ * Values:
+ * - 0 - Receive bit clock is disabled.
+ * - 1 - Receive bit clock is enabled.
+ */
+//@{
+#define BP_I2S_RCSR_BCE (28U) //!< Bit position for I2S_RCSR_BCE.
+#define BM_I2S_RCSR_BCE (0x10000000U) //!< Bit mask for I2S_RCSR_BCE.
+#define BS_I2S_RCSR_BCE (1U) //!< Bit field size in bits for I2S_RCSR_BCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_BCE field.
+#define BR_I2S_RCSR_BCE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_BCE))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_BCE.
+#define BF_I2S_RCSR_BCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_BCE), uint32_t) & BM_I2S_RCSR_BCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BCE field to a new value.
+#define BW_I2S_RCSR_BCE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_BCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field DBGE[29] (RW)
+ *
+ * Enables/disables receiver operation in Debug mode. The receive bit clock is
+ * not affected by Debug mode.
+ *
+ * Values:
+ * - 0 - Receiver is disabled in Debug mode, after completing the current frame.
+ * - 1 - Receiver is enabled in Debug mode.
+ */
+//@{
+#define BP_I2S_RCSR_DBGE (29U) //!< Bit position for I2S_RCSR_DBGE.
+#define BM_I2S_RCSR_DBGE (0x20000000U) //!< Bit mask for I2S_RCSR_DBGE.
+#define BS_I2S_RCSR_DBGE (1U) //!< Bit field size in bits for I2S_RCSR_DBGE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_DBGE field.
+#define BR_I2S_RCSR_DBGE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_DBGE))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_DBGE.
+#define BF_I2S_RCSR_DBGE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_DBGE), uint32_t) & BM_I2S_RCSR_DBGE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DBGE field to a new value.
+#define BW_I2S_RCSR_DBGE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_DBGE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field STOPE[30] (RW)
+ *
+ * Configures receiver operation in Stop mode. This bit is ignored and the
+ * receiver is disabled in all low-leakage stop modes.
+ *
+ * Values:
+ * - 0 - Receiver disabled in Stop mode.
+ * - 1 - Receiver enabled in Stop mode.
+ */
+//@{
+#define BP_I2S_RCSR_STOPE (30U) //!< Bit position for I2S_RCSR_STOPE.
+#define BM_I2S_RCSR_STOPE (0x40000000U) //!< Bit mask for I2S_RCSR_STOPE.
+#define BS_I2S_RCSR_STOPE (1U) //!< Bit field size in bits for I2S_RCSR_STOPE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_STOPE field.
+#define BR_I2S_RCSR_STOPE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_STOPE))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_STOPE.
+#define BF_I2S_RCSR_STOPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_STOPE), uint32_t) & BM_I2S_RCSR_STOPE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the STOPE field to a new value.
+#define BW_I2S_RCSR_STOPE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_STOPE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCSR, field RE[31] (RW)
+ *
+ * Enables/disables the receiver. When software clears this field, the receiver
+ * remains enabled, and this bit remains set, until the end of the current frame.
+ *
+ * Values:
+ * - 0 - Receiver is disabled.
+ * - 1 - Receiver is enabled, or receiver has been disabled and has not yet
+ * reached end of frame.
+ */
+//@{
+#define BP_I2S_RCSR_RE (31U) //!< Bit position for I2S_RCSR_RE.
+#define BM_I2S_RCSR_RE (0x80000000U) //!< Bit mask for I2S_RCSR_RE.
+#define BS_I2S_RCSR_RE (1U) //!< Bit field size in bits for I2S_RCSR_RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCSR_RE field.
+#define BR_I2S_RCSR_RE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_RE))
+#endif
+
+//! @brief Format value for bitfield I2S_RCSR_RE.
+#define BF_I2S_RCSR_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCSR_RE), uint32_t) & BM_I2S_RCSR_RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RE field to a new value.
+#define BW_I2S_RCSR_RE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_RE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_RCR1 - SAI Receive Configuration 1 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_RCR1 - SAI Receive Configuration 1 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_i2s_rcr1
+{
+ uint32_t U;
+ struct _hw_i2s_rcr1_bitfields
+ {
+ uint32_t RFW : 3; //!< [2:0] Receive FIFO Watermark
+ uint32_t RESERVED0 : 29; //!< [31:3]
+ } B;
+} hw_i2s_rcr1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_RCR1 register
+ */
+//@{
+#define HW_I2S_RCR1_ADDR(x) (REGS_I2S_BASE(x) + 0x84U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_RCR1(x) (*(__IO hw_i2s_rcr1_t *) HW_I2S_RCR1_ADDR(x))
+#define HW_I2S_RCR1_RD(x) (HW_I2S_RCR1(x).U)
+#define HW_I2S_RCR1_WR(x, v) (HW_I2S_RCR1(x).U = (v))
+#define HW_I2S_RCR1_SET(x, v) (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) | (v)))
+#define HW_I2S_RCR1_CLR(x, v) (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) & ~(v)))
+#define HW_I2S_RCR1_TOG(x, v) (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_RCR1 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR1, field RFW[2:0] (RW)
+ *
+ * Configures the watermark level for all enabled receiver channels.
+ */
+//@{
+#define BP_I2S_RCR1_RFW (0U) //!< Bit position for I2S_RCR1_RFW.
+#define BM_I2S_RCR1_RFW (0x00000007U) //!< Bit mask for I2S_RCR1_RFW.
+#define BS_I2S_RCR1_RFW (3U) //!< Bit field size in bits for I2S_RCR1_RFW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR1_RFW field.
+#define BR_I2S_RCR1_RFW(x) (HW_I2S_RCR1(x).B.RFW)
+#endif
+
+//! @brief Format value for bitfield I2S_RCR1_RFW.
+#define BF_I2S_RCR1_RFW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR1_RFW), uint32_t) & BM_I2S_RCR1_RFW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RFW field to a new value.
+#define BW_I2S_RCR1_RFW(x, v) (HW_I2S_RCR1_WR(x, (HW_I2S_RCR1_RD(x) & ~BM_I2S_RCR1_RFW) | BF_I2S_RCR1_RFW(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_RCR2 - SAI Receive Configuration 2 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_RCR2 - SAI Receive Configuration 2 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+typedef union _hw_i2s_rcr2
+{
+ uint32_t U;
+ struct _hw_i2s_rcr2_bitfields
+ {
+ uint32_t DIV : 8; //!< [7:0] Bit Clock Divide
+ uint32_t RESERVED0 : 16; //!< [23:8]
+ uint32_t BCD : 1; //!< [24] Bit Clock Direction
+ uint32_t BCP : 1; //!< [25] Bit Clock Polarity
+ uint32_t MSEL : 2; //!< [27:26] MCLK Select
+ uint32_t BCI : 1; //!< [28] Bit Clock Input
+ uint32_t BCS : 1; //!< [29] Bit Clock Swap
+ uint32_t SYNC : 2; //!< [31:30] Synchronous Mode
+ } B;
+} hw_i2s_rcr2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_RCR2 register
+ */
+//@{
+#define HW_I2S_RCR2_ADDR(x) (REGS_I2S_BASE(x) + 0x88U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_RCR2(x) (*(__IO hw_i2s_rcr2_t *) HW_I2S_RCR2_ADDR(x))
+#define HW_I2S_RCR2_RD(x) (HW_I2S_RCR2(x).U)
+#define HW_I2S_RCR2_WR(x, v) (HW_I2S_RCR2(x).U = (v))
+#define HW_I2S_RCR2_SET(x, v) (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) | (v)))
+#define HW_I2S_RCR2_CLR(x, v) (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) & ~(v)))
+#define HW_I2S_RCR2_TOG(x, v) (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_RCR2 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR2, field DIV[7:0] (RW)
+ *
+ * Divides down the audio master clock to generate the bit clock when configured
+ * for an internal bit clock. The division value is (DIV + 1) * 2.
+ */
+//@{
+#define BP_I2S_RCR2_DIV (0U) //!< Bit position for I2S_RCR2_DIV.
+#define BM_I2S_RCR2_DIV (0x000000FFU) //!< Bit mask for I2S_RCR2_DIV.
+#define BS_I2S_RCR2_DIV (8U) //!< Bit field size in bits for I2S_RCR2_DIV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR2_DIV field.
+#define BR_I2S_RCR2_DIV(x) (HW_I2S_RCR2(x).B.DIV)
+#endif
+
+//! @brief Format value for bitfield I2S_RCR2_DIV.
+#define BF_I2S_RCR2_DIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_DIV), uint32_t) & BM_I2S_RCR2_DIV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DIV field to a new value.
+#define BW_I2S_RCR2_DIV(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_DIV) | BF_I2S_RCR2_DIV(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCR2, field BCD[24] (RW)
+ *
+ * Configures the direction of the bit clock.
+ *
+ * Values:
+ * - 0 - Bit clock is generated externally in Slave mode.
+ * - 1 - Bit clock is generated internally in Master mode.
+ */
+//@{
+#define BP_I2S_RCR2_BCD (24U) //!< Bit position for I2S_RCR2_BCD.
+#define BM_I2S_RCR2_BCD (0x01000000U) //!< Bit mask for I2S_RCR2_BCD.
+#define BS_I2S_RCR2_BCD (1U) //!< Bit field size in bits for I2S_RCR2_BCD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR2_BCD field.
+#define BR_I2S_RCR2_BCD(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCD))
+#endif
+
+//! @brief Format value for bitfield I2S_RCR2_BCD.
+#define BF_I2S_RCR2_BCD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_BCD), uint32_t) & BM_I2S_RCR2_BCD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BCD field to a new value.
+#define BW_I2S_RCR2_BCD(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCR2, field BCP[25] (RW)
+ *
+ * Configures the polarity of the bit clock.
+ *
+ * Values:
+ * - 0 - Bit Clock is active high with drive outputs on rising edge and sample
+ * inputs on falling edge.
+ * - 1 - Bit Clock is active low with drive outputs on falling edge and sample
+ * inputs on rising edge.
+ */
+//@{
+#define BP_I2S_RCR2_BCP (25U) //!< Bit position for I2S_RCR2_BCP.
+#define BM_I2S_RCR2_BCP (0x02000000U) //!< Bit mask for I2S_RCR2_BCP.
+#define BS_I2S_RCR2_BCP (1U) //!< Bit field size in bits for I2S_RCR2_BCP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR2_BCP field.
+#define BR_I2S_RCR2_BCP(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCP))
+#endif
+
+//! @brief Format value for bitfield I2S_RCR2_BCP.
+#define BF_I2S_RCR2_BCP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_BCP), uint32_t) & BM_I2S_RCR2_BCP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BCP field to a new value.
+#define BW_I2S_RCR2_BCP(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCR2, field MSEL[27:26] (RW)
+ *
+ * Selects the audio Master Clock option used to generate an internally
+ * generated bit clock. This field has no effect when configured for an externally
+ * generated bit clock. Depending on the device, some Master Clock options might not be
+ * available. See the chip configuration details for the availability and
+ * chip-specific meaning of each option.
+ *
+ * Values:
+ * - 00 - Bus Clock selected.
+ * - 01 - Master Clock (MCLK) 1 option selected.
+ * - 10 - Master Clock (MCLK) 2 option selected.
+ * - 11 - Master Clock (MCLK) 3 option selected.
+ */
+//@{
+#define BP_I2S_RCR2_MSEL (26U) //!< Bit position for I2S_RCR2_MSEL.
+#define BM_I2S_RCR2_MSEL (0x0C000000U) //!< Bit mask for I2S_RCR2_MSEL.
+#define BS_I2S_RCR2_MSEL (2U) //!< Bit field size in bits for I2S_RCR2_MSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR2_MSEL field.
+#define BR_I2S_RCR2_MSEL(x) (HW_I2S_RCR2(x).B.MSEL)
+#endif
+
+//! @brief Format value for bitfield I2S_RCR2_MSEL.
+#define BF_I2S_RCR2_MSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_MSEL), uint32_t) & BM_I2S_RCR2_MSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MSEL field to a new value.
+#define BW_I2S_RCR2_MSEL(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_MSEL) | BF_I2S_RCR2_MSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCR2, field BCI[28] (RW)
+ *
+ * When this field is set and using an internally generated bit clock in either
+ * synchronous or asynchronous mode, the bit clock actually used by the receiver
+ * is delayed by the pad output delay (the receiver is clocked by the pad input
+ * as if the clock was externally generated). This has the effect of decreasing
+ * the data input setup time, but increasing the data output valid time. The slave
+ * mode timing from the datasheet should be used for the receiver when this bit
+ * is set. In synchronous mode, this bit allows the receiver to use the slave mode
+ * timing from the datasheet, while the transmitter uses the master mode timing.
+ * This field has no effect when configured for an externally generated bit
+ * clock or when synchronous to another SAI peripheral .
+ *
+ * Values:
+ * - 0 - No effect.
+ * - 1 - Internal logic is clocked as if bit clock was externally generated.
+ */
+//@{
+#define BP_I2S_RCR2_BCI (28U) //!< Bit position for I2S_RCR2_BCI.
+#define BM_I2S_RCR2_BCI (0x10000000U) //!< Bit mask for I2S_RCR2_BCI.
+#define BS_I2S_RCR2_BCI (1U) //!< Bit field size in bits for I2S_RCR2_BCI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR2_BCI field.
+#define BR_I2S_RCR2_BCI(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCI))
+#endif
+
+//! @brief Format value for bitfield I2S_RCR2_BCI.
+#define BF_I2S_RCR2_BCI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_BCI), uint32_t) & BM_I2S_RCR2_BCI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BCI field to a new value.
+#define BW_I2S_RCR2_BCI(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCI) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCR2, field BCS[29] (RW)
+ *
+ * This field swaps the bit clock used by the receiver. When the receiver is
+ * configured in asynchronous mode and this bit is set, the receiver is clocked by
+ * the transmitter bit clock (SAI_TX_BCLK). This allows the transmitter and
+ * receiver to share the same bit clock, but the receiver continues to use the receiver
+ * frame sync (SAI_RX_SYNC). When the receiver is configured in synchronous
+ * mode, the transmitter BCS field and receiver BCS field must be set to the same
+ * value. When both are set, the transmitter and receiver are both clocked by the
+ * receiver bit clock (SAI_RX_BCLK) but use the transmitter frame sync
+ * (SAI_TX_SYNC). This field has no effect when synchronous to another SAI peripheral.
+ *
+ * Values:
+ * - 0 - Use the normal bit clock source.
+ * - 1 - Swap the bit clock source.
+ */
+//@{
+#define BP_I2S_RCR2_BCS (29U) //!< Bit position for I2S_RCR2_BCS.
+#define BM_I2S_RCR2_BCS (0x20000000U) //!< Bit mask for I2S_RCR2_BCS.
+#define BS_I2S_RCR2_BCS (1U) //!< Bit field size in bits for I2S_RCR2_BCS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR2_BCS field.
+#define BR_I2S_RCR2_BCS(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCS))
+#endif
+
+//! @brief Format value for bitfield I2S_RCR2_BCS.
+#define BF_I2S_RCR2_BCS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_BCS), uint32_t) & BM_I2S_RCR2_BCS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BCS field to a new value.
+#define BW_I2S_RCR2_BCS(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCR2, field SYNC[31:30] (RW)
+ *
+ * Configures between asynchronous and synchronous modes of operation. When
+ * configured for a synchronous mode of operation, the transmitter or other SAI
+ * peripheral must be configured for asynchronous operation.
+ *
+ * Values:
+ * - 00 - Asynchronous mode.
+ * - 01 - Synchronous with transmitter.
+ * - 10 - Synchronous with another SAI receiver.
+ * - 11 - Synchronous with another SAI transmitter.
+ */
+//@{
+#define BP_I2S_RCR2_SYNC (30U) //!< Bit position for I2S_RCR2_SYNC.
+#define BM_I2S_RCR2_SYNC (0xC0000000U) //!< Bit mask for I2S_RCR2_SYNC.
+#define BS_I2S_RCR2_SYNC (2U) //!< Bit field size in bits for I2S_RCR2_SYNC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR2_SYNC field.
+#define BR_I2S_RCR2_SYNC(x) (HW_I2S_RCR2(x).B.SYNC)
+#endif
+
+//! @brief Format value for bitfield I2S_RCR2_SYNC.
+#define BF_I2S_RCR2_SYNC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR2_SYNC), uint32_t) & BM_I2S_RCR2_SYNC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SYNC field to a new value.
+#define BW_I2S_RCR2_SYNC(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_SYNC) | BF_I2S_RCR2_SYNC(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_RCR3 - SAI Receive Configuration 3 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_RCR3 - SAI Receive Configuration 3 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+typedef union _hw_i2s_rcr3
+{
+ uint32_t U;
+ struct _hw_i2s_rcr3_bitfields
+ {
+ uint32_t WDFL : 5; //!< [4:0] Word Flag Configuration
+ uint32_t RESERVED0 : 11; //!< [15:5]
+ uint32_t RCE : 2; //!< [17:16] Receive Channel Enable
+ uint32_t RESERVED1 : 14; //!< [31:18]
+ } B;
+} hw_i2s_rcr3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_RCR3 register
+ */
+//@{
+#define HW_I2S_RCR3_ADDR(x) (REGS_I2S_BASE(x) + 0x8CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_RCR3(x) (*(__IO hw_i2s_rcr3_t *) HW_I2S_RCR3_ADDR(x))
+#define HW_I2S_RCR3_RD(x) (HW_I2S_RCR3(x).U)
+#define HW_I2S_RCR3_WR(x, v) (HW_I2S_RCR3(x).U = (v))
+#define HW_I2S_RCR3_SET(x, v) (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) | (v)))
+#define HW_I2S_RCR3_CLR(x, v) (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) & ~(v)))
+#define HW_I2S_RCR3_TOG(x, v) (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_RCR3 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR3, field WDFL[4:0] (RW)
+ *
+ * Configures which word the start of word flag is set. The value written should
+ * be one less than the word number (for example, write zero to configure for
+ * the first word in the frame). When configured to a value greater than the Frame
+ * Size field, then the start of word flag is never set.
+ */
+//@{
+#define BP_I2S_RCR3_WDFL (0U) //!< Bit position for I2S_RCR3_WDFL.
+#define BM_I2S_RCR3_WDFL (0x0000001FU) //!< Bit mask for I2S_RCR3_WDFL.
+#define BS_I2S_RCR3_WDFL (5U) //!< Bit field size in bits for I2S_RCR3_WDFL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR3_WDFL field.
+#define BR_I2S_RCR3_WDFL(x) (HW_I2S_RCR3(x).B.WDFL)
+#endif
+
+//! @brief Format value for bitfield I2S_RCR3_WDFL.
+#define BF_I2S_RCR3_WDFL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR3_WDFL), uint32_t) & BM_I2S_RCR3_WDFL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WDFL field to a new value.
+#define BW_I2S_RCR3_WDFL(x, v) (HW_I2S_RCR3_WR(x, (HW_I2S_RCR3_RD(x) & ~BM_I2S_RCR3_WDFL) | BF_I2S_RCR3_WDFL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCR3, field RCE[17:16] (RW)
+ *
+ * Enables the corresponding data channel for receive operation. A channel must
+ * be enabled before its FIFO is accessed.
+ *
+ * Values:
+ * - 0 - Receive data channel N is disabled.
+ * - 1 - Receive data channel N is enabled.
+ */
+//@{
+#define BP_I2S_RCR3_RCE (16U) //!< Bit position for I2S_RCR3_RCE.
+#define BM_I2S_RCR3_RCE (0x00030000U) //!< Bit mask for I2S_RCR3_RCE.
+#define BS_I2S_RCR3_RCE (2U) //!< Bit field size in bits for I2S_RCR3_RCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR3_RCE field.
+#define BR_I2S_RCR3_RCE(x) (HW_I2S_RCR3(x).B.RCE)
+#endif
+
+//! @brief Format value for bitfield I2S_RCR3_RCE.
+#define BF_I2S_RCR3_RCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR3_RCE), uint32_t) & BM_I2S_RCR3_RCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RCE field to a new value.
+#define BW_I2S_RCR3_RCE(x, v) (HW_I2S_RCR3_WR(x, (HW_I2S_RCR3_RD(x) & ~BM_I2S_RCR3_RCE) | BF_I2S_RCR3_RCE(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_RCR4 - SAI Receive Configuration 4 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_RCR4 - SAI Receive Configuration 4 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+typedef union _hw_i2s_rcr4
+{
+ uint32_t U;
+ struct _hw_i2s_rcr4_bitfields
+ {
+ uint32_t FSD : 1; //!< [0] Frame Sync Direction
+ uint32_t FSP : 1; //!< [1] Frame Sync Polarity
+ uint32_t RESERVED0 : 1; //!< [2]
+ uint32_t FSE : 1; //!< [3] Frame Sync Early
+ uint32_t MF : 1; //!< [4] MSB First
+ uint32_t RESERVED1 : 3; //!< [7:5]
+ uint32_t SYWD : 5; //!< [12:8] Sync Width
+ uint32_t RESERVED2 : 3; //!< [15:13]
+ uint32_t FRSZ : 5; //!< [20:16] Frame Size
+ uint32_t RESERVED3 : 11; //!< [31:21]
+ } B;
+} hw_i2s_rcr4_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_RCR4 register
+ */
+//@{
+#define HW_I2S_RCR4_ADDR(x) (REGS_I2S_BASE(x) + 0x90U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_RCR4(x) (*(__IO hw_i2s_rcr4_t *) HW_I2S_RCR4_ADDR(x))
+#define HW_I2S_RCR4_RD(x) (HW_I2S_RCR4(x).U)
+#define HW_I2S_RCR4_WR(x, v) (HW_I2S_RCR4(x).U = (v))
+#define HW_I2S_RCR4_SET(x, v) (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) | (v)))
+#define HW_I2S_RCR4_CLR(x, v) (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) & ~(v)))
+#define HW_I2S_RCR4_TOG(x, v) (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_RCR4 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR4, field FSD[0] (RW)
+ *
+ * Configures the direction of the frame sync.
+ *
+ * Values:
+ * - 0 - Frame Sync is generated externally in Slave mode.
+ * - 1 - Frame Sync is generated internally in Master mode.
+ */
+//@{
+#define BP_I2S_RCR4_FSD (0U) //!< Bit position for I2S_RCR4_FSD.
+#define BM_I2S_RCR4_FSD (0x00000001U) //!< Bit mask for I2S_RCR4_FSD.
+#define BS_I2S_RCR4_FSD (1U) //!< Bit field size in bits for I2S_RCR4_FSD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR4_FSD field.
+#define BR_I2S_RCR4_FSD(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSD))
+#endif
+
+//! @brief Format value for bitfield I2S_RCR4_FSD.
+#define BF_I2S_RCR4_FSD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_FSD), uint32_t) & BM_I2S_RCR4_FSD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FSD field to a new value.
+#define BW_I2S_RCR4_FSD(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCR4, field FSP[1] (RW)
+ *
+ * Configures the polarity of the frame sync.
+ *
+ * Values:
+ * - 0 - Frame sync is active high.
+ * - 1 - Frame sync is active low.
+ */
+//@{
+#define BP_I2S_RCR4_FSP (1U) //!< Bit position for I2S_RCR4_FSP.
+#define BM_I2S_RCR4_FSP (0x00000002U) //!< Bit mask for I2S_RCR4_FSP.
+#define BS_I2S_RCR4_FSP (1U) //!< Bit field size in bits for I2S_RCR4_FSP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR4_FSP field.
+#define BR_I2S_RCR4_FSP(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSP))
+#endif
+
+//! @brief Format value for bitfield I2S_RCR4_FSP.
+#define BF_I2S_RCR4_FSP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_FSP), uint32_t) & BM_I2S_RCR4_FSP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FSP field to a new value.
+#define BW_I2S_RCR4_FSP(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCR4, field FSE[3] (RW)
+ *
+ * Values:
+ * - 0 - Frame sync asserts with the first bit of the frame.
+ * - 1 - Frame sync asserts one bit before the first bit of the frame.
+ */
+//@{
+#define BP_I2S_RCR4_FSE (3U) //!< Bit position for I2S_RCR4_FSE.
+#define BM_I2S_RCR4_FSE (0x00000008U) //!< Bit mask for I2S_RCR4_FSE.
+#define BS_I2S_RCR4_FSE (1U) //!< Bit field size in bits for I2S_RCR4_FSE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR4_FSE field.
+#define BR_I2S_RCR4_FSE(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSE))
+#endif
+
+//! @brief Format value for bitfield I2S_RCR4_FSE.
+#define BF_I2S_RCR4_FSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_FSE), uint32_t) & BM_I2S_RCR4_FSE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FSE field to a new value.
+#define BW_I2S_RCR4_FSE(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCR4, field MF[4] (RW)
+ *
+ * Configures whether the LSB or the MSB is received first.
+ *
+ * Values:
+ * - 0 - LSB is received first.
+ * - 1 - MSB is received first.
+ */
+//@{
+#define BP_I2S_RCR4_MF (4U) //!< Bit position for I2S_RCR4_MF.
+#define BM_I2S_RCR4_MF (0x00000010U) //!< Bit mask for I2S_RCR4_MF.
+#define BS_I2S_RCR4_MF (1U) //!< Bit field size in bits for I2S_RCR4_MF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR4_MF field.
+#define BR_I2S_RCR4_MF(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_MF))
+#endif
+
+//! @brief Format value for bitfield I2S_RCR4_MF.
+#define BF_I2S_RCR4_MF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_MF), uint32_t) & BM_I2S_RCR4_MF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MF field to a new value.
+#define BW_I2S_RCR4_MF(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_MF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCR4, field SYWD[12:8] (RW)
+ *
+ * Configures the length of the frame sync in number of bit clocks. The value
+ * written must be one less than the number of bit clocks. For example, write 0 for
+ * the frame sync to assert for one bit clock only. The sync width cannot be
+ * configured longer than the first word of the frame.
+ */
+//@{
+#define BP_I2S_RCR4_SYWD (8U) //!< Bit position for I2S_RCR4_SYWD.
+#define BM_I2S_RCR4_SYWD (0x00001F00U) //!< Bit mask for I2S_RCR4_SYWD.
+#define BS_I2S_RCR4_SYWD (5U) //!< Bit field size in bits for I2S_RCR4_SYWD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR4_SYWD field.
+#define BR_I2S_RCR4_SYWD(x) (HW_I2S_RCR4(x).B.SYWD)
+#endif
+
+//! @brief Format value for bitfield I2S_RCR4_SYWD.
+#define BF_I2S_RCR4_SYWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_SYWD), uint32_t) & BM_I2S_RCR4_SYWD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SYWD field to a new value.
+#define BW_I2S_RCR4_SYWD(x, v) (HW_I2S_RCR4_WR(x, (HW_I2S_RCR4_RD(x) & ~BM_I2S_RCR4_SYWD) | BF_I2S_RCR4_SYWD(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCR4, field FRSZ[20:16] (RW)
+ *
+ * Configures the number of words in each frame. The value written must be one
+ * less than the number of words in the frame. For example, write 0 for one word
+ * per frame. The maximum supported frame size is 32 words.
+ */
+//@{
+#define BP_I2S_RCR4_FRSZ (16U) //!< Bit position for I2S_RCR4_FRSZ.
+#define BM_I2S_RCR4_FRSZ (0x001F0000U) //!< Bit mask for I2S_RCR4_FRSZ.
+#define BS_I2S_RCR4_FRSZ (5U) //!< Bit field size in bits for I2S_RCR4_FRSZ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR4_FRSZ field.
+#define BR_I2S_RCR4_FRSZ(x) (HW_I2S_RCR4(x).B.FRSZ)
+#endif
+
+//! @brief Format value for bitfield I2S_RCR4_FRSZ.
+#define BF_I2S_RCR4_FRSZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR4_FRSZ), uint32_t) & BM_I2S_RCR4_FRSZ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FRSZ field to a new value.
+#define BW_I2S_RCR4_FRSZ(x, v) (HW_I2S_RCR4_WR(x, (HW_I2S_RCR4_RD(x) & ~BM_I2S_RCR4_FRSZ) | BF_I2S_RCR4_FRSZ(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_RCR5 - SAI Receive Configuration 5 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_RCR5 - SAI Receive Configuration 5 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+typedef union _hw_i2s_rcr5
+{
+ uint32_t U;
+ struct _hw_i2s_rcr5_bitfields
+ {
+ uint32_t RESERVED0 : 8; //!< [7:0]
+ uint32_t FBT : 5; //!< [12:8] First Bit Shifted
+ uint32_t RESERVED1 : 3; //!< [15:13]
+ uint32_t W0W : 5; //!< [20:16] Word 0 Width
+ uint32_t RESERVED2 : 3; //!< [23:21]
+ uint32_t WNW : 5; //!< [28:24] Word N Width
+ uint32_t RESERVED3 : 3; //!< [31:29]
+ } B;
+} hw_i2s_rcr5_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_RCR5 register
+ */
+//@{
+#define HW_I2S_RCR5_ADDR(x) (REGS_I2S_BASE(x) + 0x94U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_RCR5(x) (*(__IO hw_i2s_rcr5_t *) HW_I2S_RCR5_ADDR(x))
+#define HW_I2S_RCR5_RD(x) (HW_I2S_RCR5(x).U)
+#define HW_I2S_RCR5_WR(x, v) (HW_I2S_RCR5(x).U = (v))
+#define HW_I2S_RCR5_SET(x, v) (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) | (v)))
+#define HW_I2S_RCR5_CLR(x, v) (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) & ~(v)))
+#define HW_I2S_RCR5_TOG(x, v) (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_RCR5 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR5, field FBT[12:8] (RW)
+ *
+ * Configures the bit index for the first bit received for each word in the
+ * frame. If configured for MSB First, the index of the next bit received is one less
+ * than the current bit received. If configured for LSB First, the index of the
+ * next bit received is one more than the current bit received. The value written
+ * must be greater than or equal to the word width when configured for MSB
+ * First. The value written must be less than or equal to 31-word width when
+ * configured for LSB First.
+ */
+//@{
+#define BP_I2S_RCR5_FBT (8U) //!< Bit position for I2S_RCR5_FBT.
+#define BM_I2S_RCR5_FBT (0x00001F00U) //!< Bit mask for I2S_RCR5_FBT.
+#define BS_I2S_RCR5_FBT (5U) //!< Bit field size in bits for I2S_RCR5_FBT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR5_FBT field.
+#define BR_I2S_RCR5_FBT(x) (HW_I2S_RCR5(x).B.FBT)
+#endif
+
+//! @brief Format value for bitfield I2S_RCR5_FBT.
+#define BF_I2S_RCR5_FBT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR5_FBT), uint32_t) & BM_I2S_RCR5_FBT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FBT field to a new value.
+#define BW_I2S_RCR5_FBT(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_FBT) | BF_I2S_RCR5_FBT(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCR5, field W0W[20:16] (RW)
+ *
+ * Configures the number of bits in the first word in each frame. The value
+ * written must be one less than the number of bits in the first word. Word width of
+ * less than 8 bits is not supported if there is only one word per frame.
+ */
+//@{
+#define BP_I2S_RCR5_W0W (16U) //!< Bit position for I2S_RCR5_W0W.
+#define BM_I2S_RCR5_W0W (0x001F0000U) //!< Bit mask for I2S_RCR5_W0W.
+#define BS_I2S_RCR5_W0W (5U) //!< Bit field size in bits for I2S_RCR5_W0W.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR5_W0W field.
+#define BR_I2S_RCR5_W0W(x) (HW_I2S_RCR5(x).B.W0W)
+#endif
+
+//! @brief Format value for bitfield I2S_RCR5_W0W.
+#define BF_I2S_RCR5_W0W(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR5_W0W), uint32_t) & BM_I2S_RCR5_W0W)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the W0W field to a new value.
+#define BW_I2S_RCR5_W0W(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_W0W) | BF_I2S_RCR5_W0W(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RCR5, field WNW[28:24] (RW)
+ *
+ * Configures the number of bits in each word, for each word except the first in
+ * the frame. The value written must be one less than the number of bits per
+ * word. Word width of less than 8 bits is not supported.
+ */
+//@{
+#define BP_I2S_RCR5_WNW (24U) //!< Bit position for I2S_RCR5_WNW.
+#define BM_I2S_RCR5_WNW (0x1F000000U) //!< Bit mask for I2S_RCR5_WNW.
+#define BS_I2S_RCR5_WNW (5U) //!< Bit field size in bits for I2S_RCR5_WNW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RCR5_WNW field.
+#define BR_I2S_RCR5_WNW(x) (HW_I2S_RCR5(x).B.WNW)
+#endif
+
+//! @brief Format value for bitfield I2S_RCR5_WNW.
+#define BF_I2S_RCR5_WNW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RCR5_WNW), uint32_t) & BM_I2S_RCR5_WNW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WNW field to a new value.
+#define BW_I2S_RCR5_WNW(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_WNW) | BF_I2S_RCR5_WNW(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_RDRn - SAI Receive Data Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_RDRn - SAI Receive Data Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Reading this register introduces one additional peripheral clock wait state
+ * on each read.
+ */
+typedef union _hw_i2s_rdrn
+{
+ uint32_t U;
+ struct _hw_i2s_rdrn_bitfields
+ {
+ uint32_t RDR : 32; //!< [31:0] Receive Data Register
+ } B;
+} hw_i2s_rdrn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_RDRn register
+ */
+//@{
+#define HW_I2S_RDRn_COUNT (2U)
+
+#define HW_I2S_RDRn_ADDR(x, n) (REGS_I2S_BASE(x) + 0xA0U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_RDRn(x, n) (*(__I hw_i2s_rdrn_t *) HW_I2S_RDRn_ADDR(x, n))
+#define HW_I2S_RDRn_RD(x, n) (HW_I2S_RDRn(x, n).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_RDRn bitfields
+ */
+
+/*!
+ * @name Register I2S_RDRn, field RDR[31:0] (RO)
+ *
+ * The corresponding RCR3[RCE] bit must be set before accessing the channel's
+ * receive data register. Reads from this register when the receive FIFO is not
+ * empty will return the data from the top of the receive FIFO. Reads from this
+ * register when the receive FIFO is empty are ignored.
+ */
+//@{
+#define BP_I2S_RDRn_RDR (0U) //!< Bit position for I2S_RDRn_RDR.
+#define BM_I2S_RDRn_RDR (0xFFFFFFFFU) //!< Bit mask for I2S_RDRn_RDR.
+#define BS_I2S_RDRn_RDR (32U) //!< Bit field size in bits for I2S_RDRn_RDR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RDRn_RDR field.
+#define BR_I2S_RDRn_RDR(x, n) (HW_I2S_RDRn(x, n).U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_RFRn - SAI Receive FIFO Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_RFRn - SAI Receive FIFO Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MSB of the read and write pointers is used to distinguish between FIFO
+ * full and empty conditions. If the read and write pointers are identical, then
+ * the FIFO is empty. If the read and write pointers are identical except for the
+ * MSB, then the FIFO is full.
+ */
+typedef union _hw_i2s_rfrn
+{
+ uint32_t U;
+ struct _hw_i2s_rfrn_bitfields
+ {
+ uint32_t RFP : 4; //!< [3:0] Read FIFO Pointer
+ uint32_t RESERVED0 : 12; //!< [15:4]
+ uint32_t WFP : 4; //!< [19:16] Write FIFO Pointer
+ uint32_t RESERVED1 : 12; //!< [31:20]
+ } B;
+} hw_i2s_rfrn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_RFRn register
+ */
+//@{
+#define HW_I2S_RFRn_COUNT (2U)
+
+#define HW_I2S_RFRn_ADDR(x, n) (REGS_I2S_BASE(x) + 0xC0U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_RFRn(x, n) (*(__I hw_i2s_rfrn_t *) HW_I2S_RFRn_ADDR(x, n))
+#define HW_I2S_RFRn_RD(x, n) (HW_I2S_RFRn(x, n).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_RFRn bitfields
+ */
+
+/*!
+ * @name Register I2S_RFRn, field RFP[3:0] (RO)
+ *
+ * FIFO read pointer for receive data channel.
+ */
+//@{
+#define BP_I2S_RFRn_RFP (0U) //!< Bit position for I2S_RFRn_RFP.
+#define BM_I2S_RFRn_RFP (0x0000000FU) //!< Bit mask for I2S_RFRn_RFP.
+#define BS_I2S_RFRn_RFP (4U) //!< Bit field size in bits for I2S_RFRn_RFP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RFRn_RFP field.
+#define BR_I2S_RFRn_RFP(x, n) (HW_I2S_RFRn(x, n).B.RFP)
+#endif
+//@}
+
+/*!
+ * @name Register I2S_RFRn, field WFP[19:16] (RO)
+ *
+ * FIFO write pointer for receive data channel.
+ */
+//@{
+#define BP_I2S_RFRn_WFP (16U) //!< Bit position for I2S_RFRn_WFP.
+#define BM_I2S_RFRn_WFP (0x000F0000U) //!< Bit mask for I2S_RFRn_WFP.
+#define BS_I2S_RFRn_WFP (4U) //!< Bit field size in bits for I2S_RFRn_WFP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RFRn_WFP field.
+#define BR_I2S_RFRn_WFP(x, n) (HW_I2S_RFRn(x, n).B.WFP)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_RMR - SAI Receive Mask Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_RMR - SAI Receive Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is double-buffered and updates: When RCSR[RE] is first set At
+ * the end of each frame This allows the masked words in each frame to change from
+ * frame to frame.
+ */
+typedef union _hw_i2s_rmr
+{
+ uint32_t U;
+ struct _hw_i2s_rmr_bitfields
+ {
+ uint32_t RWM : 32; //!< [31:0] Receive Word Mask
+ } B;
+} hw_i2s_rmr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_RMR register
+ */
+//@{
+#define HW_I2S_RMR_ADDR(x) (REGS_I2S_BASE(x) + 0xE0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_RMR(x) (*(__IO hw_i2s_rmr_t *) HW_I2S_RMR_ADDR(x))
+#define HW_I2S_RMR_RD(x) (HW_I2S_RMR(x).U)
+#define HW_I2S_RMR_WR(x, v) (HW_I2S_RMR(x).U = (v))
+#define HW_I2S_RMR_SET(x, v) (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) | (v)))
+#define HW_I2S_RMR_CLR(x, v) (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) & ~(v)))
+#define HW_I2S_RMR_TOG(x, v) (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_RMR bitfields
+ */
+
+/*!
+ * @name Register I2S_RMR, field RWM[31:0] (RW)
+ *
+ * Configures whether the receive word is masked (received data ignored and not
+ * written to receive FIFO) for the corresponding word in the frame.
+ *
+ * Values:
+ * - 0 - Word N is enabled.
+ * - 1 - Word N is masked.
+ */
+//@{
+#define BP_I2S_RMR_RWM (0U) //!< Bit position for I2S_RMR_RWM.
+#define BM_I2S_RMR_RWM (0xFFFFFFFFU) //!< Bit mask for I2S_RMR_RWM.
+#define BS_I2S_RMR_RWM (32U) //!< Bit field size in bits for I2S_RMR_RWM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_RMR_RWM field.
+#define BR_I2S_RMR_RWM(x) (HW_I2S_RMR(x).U)
+#endif
+
+//! @brief Format value for bitfield I2S_RMR_RWM.
+#define BF_I2S_RMR_RWM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_RMR_RWM), uint32_t) & BM_I2S_RMR_RWM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RWM field to a new value.
+#define BW_I2S_RMR_RWM(x, v) (HW_I2S_RMR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_MCR - SAI MCLK Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_MCR - SAI MCLK Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MCLK Control Register (MCR) controls the clock source and direction of
+ * the audio master clock.
+ */
+typedef union _hw_i2s_mcr
+{
+ uint32_t U;
+ struct _hw_i2s_mcr_bitfields
+ {
+ uint32_t RESERVED0 : 24; //!< [23:0]
+ uint32_t MICS : 2; //!< [25:24] MCLK Input Clock Select
+ uint32_t RESERVED1 : 4; //!< [29:26]
+ uint32_t MOE : 1; //!< [30] MCLK Output Enable
+ uint32_t DUF : 1; //!< [31] Divider Update Flag
+ } B;
+} hw_i2s_mcr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_MCR register
+ */
+//@{
+#define HW_I2S_MCR_ADDR(x) (REGS_I2S_BASE(x) + 0x100U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_MCR(x) (*(__IO hw_i2s_mcr_t *) HW_I2S_MCR_ADDR(x))
+#define HW_I2S_MCR_RD(x) (HW_I2S_MCR(x).U)
+#define HW_I2S_MCR_WR(x, v) (HW_I2S_MCR(x).U = (v))
+#define HW_I2S_MCR_SET(x, v) (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) | (v)))
+#define HW_I2S_MCR_CLR(x, v) (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) & ~(v)))
+#define HW_I2S_MCR_TOG(x, v) (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_MCR bitfields
+ */
+
+/*!
+ * @name Register I2S_MCR, field MICS[25:24] (RW)
+ *
+ * Selects the clock input to the MCLK divider. This field cannot be changed
+ * while the MCLK divider is enabled. See the chip configuration details for
+ * information about the connections to these inputs.
+ *
+ * Values:
+ * - 00 - MCLK divider input clock 0 selected.
+ * - 01 - MCLK divider input clock 1 selected.
+ * - 10 - MCLK divider input clock 2 selected.
+ * - 11 - MCLK divider input clock 3 selected.
+ */
+//@{
+#define BP_I2S_MCR_MICS (24U) //!< Bit position for I2S_MCR_MICS.
+#define BM_I2S_MCR_MICS (0x03000000U) //!< Bit mask for I2S_MCR_MICS.
+#define BS_I2S_MCR_MICS (2U) //!< Bit field size in bits for I2S_MCR_MICS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_MCR_MICS field.
+#define BR_I2S_MCR_MICS(x) (HW_I2S_MCR(x).B.MICS)
+#endif
+
+//! @brief Format value for bitfield I2S_MCR_MICS.
+#define BF_I2S_MCR_MICS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_MCR_MICS), uint32_t) & BM_I2S_MCR_MICS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MICS field to a new value.
+#define BW_I2S_MCR_MICS(x, v) (HW_I2S_MCR_WR(x, (HW_I2S_MCR_RD(x) & ~BM_I2S_MCR_MICS) | BF_I2S_MCR_MICS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_MCR, field MOE[30] (RW)
+ *
+ * Enables the MCLK divider and configures the MCLK signal pin as an output.
+ * When software clears this field, it remains set until the MCLK divider is fully
+ * disabled.
+ *
+ * Values:
+ * - 0 - MCLK signal pin is configured as an input that bypasses the MCLK
+ * divider.
+ * - 1 - MCLK signal pin is configured as an output from the MCLK divider and
+ * the MCLK divider is enabled.
+ */
+//@{
+#define BP_I2S_MCR_MOE (30U) //!< Bit position for I2S_MCR_MOE.
+#define BM_I2S_MCR_MOE (0x40000000U) //!< Bit mask for I2S_MCR_MOE.
+#define BS_I2S_MCR_MOE (1U) //!< Bit field size in bits for I2S_MCR_MOE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_MCR_MOE field.
+#define BR_I2S_MCR_MOE(x) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_MOE))
+#endif
+
+//! @brief Format value for bitfield I2S_MCR_MOE.
+#define BF_I2S_MCR_MOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_MCR_MOE), uint32_t) & BM_I2S_MCR_MOE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MOE field to a new value.
+#define BW_I2S_MCR_MOE(x, v) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_MOE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_MCR, field DUF[31] (RO)
+ *
+ * Provides the status of on-the-fly updates to the MCLK divider ratio.
+ *
+ * Values:
+ * - 0 - MCLK divider ratio is not being updated currently.
+ * - 1 - MCLK divider ratio is updating on-the-fly. Further updates to the MCLK
+ * divider ratio are blocked while this flag remains set.
+ */
+//@{
+#define BP_I2S_MCR_DUF (31U) //!< Bit position for I2S_MCR_DUF.
+#define BM_I2S_MCR_DUF (0x80000000U) //!< Bit mask for I2S_MCR_DUF.
+#define BS_I2S_MCR_DUF (1U) //!< Bit field size in bits for I2S_MCR_DUF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_MCR_DUF field.
+#define BR_I2S_MCR_DUF(x) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_DUF))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2S_MDR - SAI MCLK Divide Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2S_MDR - SAI MCLK Divide Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MCLK Divide Register (MDR) configures the MCLK divide ratio. Although the
+ * MDR can be changed when the MCLK divider clock is enabled, additional writes
+ * to the MDR are blocked while MCR[DUF] is set. Writes to the MDR when the MCLK
+ * divided clock is disabled do not set MCR[DUF].
+ */
+typedef union _hw_i2s_mdr
+{
+ uint32_t U;
+ struct _hw_i2s_mdr_bitfields
+ {
+ uint32_t DIVIDE : 12; //!< [11:0] MCLK Divide
+ uint32_t FRACT : 8; //!< [19:12] MCLK Fraction
+ uint32_t RESERVED0 : 12; //!< [31:20]
+ } B;
+} hw_i2s_mdr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2S_MDR register
+ */
+//@{
+#define HW_I2S_MDR_ADDR(x) (REGS_I2S_BASE(x) + 0x104U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2S_MDR(x) (*(__IO hw_i2s_mdr_t *) HW_I2S_MDR_ADDR(x))
+#define HW_I2S_MDR_RD(x) (HW_I2S_MDR(x).U)
+#define HW_I2S_MDR_WR(x, v) (HW_I2S_MDR(x).U = (v))
+#define HW_I2S_MDR_SET(x, v) (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) | (v)))
+#define HW_I2S_MDR_CLR(x, v) (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) & ~(v)))
+#define HW_I2S_MDR_TOG(x, v) (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual I2S_MDR bitfields
+ */
+
+/*!
+ * @name Register I2S_MDR, field DIVIDE[11:0] (RW)
+ *
+ * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
+ * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
+ * DIVIDE field.
+ */
+//@{
+#define BP_I2S_MDR_DIVIDE (0U) //!< Bit position for I2S_MDR_DIVIDE.
+#define BM_I2S_MDR_DIVIDE (0x00000FFFU) //!< Bit mask for I2S_MDR_DIVIDE.
+#define BS_I2S_MDR_DIVIDE (12U) //!< Bit field size in bits for I2S_MDR_DIVIDE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_MDR_DIVIDE field.
+#define BR_I2S_MDR_DIVIDE(x) (HW_I2S_MDR(x).B.DIVIDE)
+#endif
+
+//! @brief Format value for bitfield I2S_MDR_DIVIDE.
+#define BF_I2S_MDR_DIVIDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_MDR_DIVIDE), uint32_t) & BM_I2S_MDR_DIVIDE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DIVIDE field to a new value.
+#define BW_I2S_MDR_DIVIDE(x, v) (HW_I2S_MDR_WR(x, (HW_I2S_MDR_RD(x) & ~BM_I2S_MDR_DIVIDE) | BF_I2S_MDR_DIVIDE(v)))
+#endif
+//@}
+
+/*!
+ * @name Register I2S_MDR, field FRACT[19:12] (RW)
+ *
+ * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
+ * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
+ * DIVIDE field.
+ */
+//@{
+#define BP_I2S_MDR_FRACT (12U) //!< Bit position for I2S_MDR_FRACT.
+#define BM_I2S_MDR_FRACT (0x000FF000U) //!< Bit mask for I2S_MDR_FRACT.
+#define BS_I2S_MDR_FRACT (8U) //!< Bit field size in bits for I2S_MDR_FRACT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the I2S_MDR_FRACT field.
+#define BR_I2S_MDR_FRACT(x) (HW_I2S_MDR(x).B.FRACT)
+#endif
+
+//! @brief Format value for bitfield I2S_MDR_FRACT.
+#define BF_I2S_MDR_FRACT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_I2S_MDR_FRACT), uint32_t) & BM_I2S_MDR_FRACT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FRACT field to a new value.
+#define BW_I2S_MDR_FRACT(x, v) (HW_I2S_MDR_WR(x, (HW_I2S_MDR_RD(x) & ~BM_I2S_MDR_FRACT) | BF_I2S_MDR_FRACT(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_i2s_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All I2S module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_i2s
+{
+ __IO hw_i2s_tcsr_t TCSR; //!< [0x0] SAI Transmit Control Register
+ __IO hw_i2s_tcr1_t TCR1; //!< [0x4] SAI Transmit Configuration 1 Register
+ __IO hw_i2s_tcr2_t TCR2; //!< [0x8] SAI Transmit Configuration 2 Register
+ __IO hw_i2s_tcr3_t TCR3; //!< [0xC] SAI Transmit Configuration 3 Register
+ __IO hw_i2s_tcr4_t TCR4; //!< [0x10] SAI Transmit Configuration 4 Register
+ __IO hw_i2s_tcr5_t TCR5; //!< [0x14] SAI Transmit Configuration 5 Register
+ uint8_t _reserved0[8];
+ __O hw_i2s_tdrn_t TDRn[2]; //!< [0x20] SAI Transmit Data Register
+ uint8_t _reserved1[24];
+ __I hw_i2s_tfrn_t TFRn[2]; //!< [0x40] SAI Transmit FIFO Register
+ uint8_t _reserved2[24];
+ __IO hw_i2s_tmr_t TMR; //!< [0x60] SAI Transmit Mask Register
+ uint8_t _reserved3[28];
+ __IO hw_i2s_rcsr_t RCSR; //!< [0x80] SAI Receive Control Register
+ __IO hw_i2s_rcr1_t RCR1; //!< [0x84] SAI Receive Configuration 1 Register
+ __IO hw_i2s_rcr2_t RCR2; //!< [0x88] SAI Receive Configuration 2 Register
+ __IO hw_i2s_rcr3_t RCR3; //!< [0x8C] SAI Receive Configuration 3 Register
+ __IO hw_i2s_rcr4_t RCR4; //!< [0x90] SAI Receive Configuration 4 Register
+ __IO hw_i2s_rcr5_t RCR5; //!< [0x94] SAI Receive Configuration 5 Register
+ uint8_t _reserved4[8];
+ __I hw_i2s_rdrn_t RDRn[2]; //!< [0xA0] SAI Receive Data Register
+ uint8_t _reserved5[24];
+ __I hw_i2s_rfrn_t RFRn[2]; //!< [0xC0] SAI Receive FIFO Register
+ uint8_t _reserved6[24];
+ __IO hw_i2s_rmr_t RMR; //!< [0xE0] SAI Receive Mask Register
+ uint8_t _reserved7[28];
+ __IO hw_i2s_mcr_t MCR; //!< [0x100] SAI MCLK Control Register
+ __IO hw_i2s_mdr_t MDR; //!< [0x104] SAI MCLK Divide Register
+} hw_i2s_t;
+#pragma pack()
+
+//! @brief Macro to access all I2S registers.
+//! @param x I2S instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_I2S(0)</code>.
+#define HW_I2S(x) (*(hw_i2s_t *) REGS_I2S_BASE(x))
+#endif
+
+#endif // __HW_I2S_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_llwu.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,2252 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_LLWU_REGISTERS_H__
+#define __HW_LLWU_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 LLWU
+ *
+ * Low leakage wakeup unit
+ *
+ * Registers defined in this header file:
+ * - HW_LLWU_PE1 - LLWU Pin Enable 1 register
+ * - HW_LLWU_PE2 - LLWU Pin Enable 2 register
+ * - HW_LLWU_PE3 - LLWU Pin Enable 3 register
+ * - HW_LLWU_PE4 - LLWU Pin Enable 4 register
+ * - HW_LLWU_ME - LLWU Module Enable register
+ * - HW_LLWU_F1 - LLWU Flag 1 register
+ * - HW_LLWU_F2 - LLWU Flag 2 register
+ * - HW_LLWU_F3 - LLWU Flag 3 register
+ * - HW_LLWU_FILT1 - LLWU Pin Filter 1 register
+ * - HW_LLWU_FILT2 - LLWU Pin Filter 2 register
+ * - HW_LLWU_RST - LLWU Reset Enable register
+ *
+ * - hw_llwu_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_LLWU_BASE
+#define HW_LLWU_INSTANCE_COUNT (1U) //!< Number of instances of the LLWU module.
+#define REGS_LLWU_BASE (0x4007C000U) //!< Base address for LLWU.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LLWU_PE1 - LLWU Pin Enable 1 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LLWU_PE1 - LLWU Pin Enable 1 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE1 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P3-LLWU_P0. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module
+ * (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+typedef union _hw_llwu_pe1
+{
+ uint8_t U;
+ struct _hw_llwu_pe1_bitfields
+ {
+ uint8_t WUPE0 : 2; //!< [1:0] Wakeup Pin Enable For LLWU_P0
+ uint8_t WUPE1 : 2; //!< [3:2] Wakeup Pin Enable For LLWU_P1
+ uint8_t WUPE2 : 2; //!< [5:4] Wakeup Pin Enable For LLWU_P2
+ uint8_t WUPE3 : 2; //!< [7:6] Wakeup Pin Enable For LLWU_P3
+ } B;
+} hw_llwu_pe1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LLWU_PE1 register
+ */
+//@{
+#define HW_LLWU_PE1_ADDR (REGS_LLWU_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LLWU_PE1 (*(__IO hw_llwu_pe1_t *) HW_LLWU_PE1_ADDR)
+#define HW_LLWU_PE1_RD() (HW_LLWU_PE1.U)
+#define HW_LLWU_PE1_WR(v) (HW_LLWU_PE1.U = (v))
+#define HW_LLWU_PE1_SET(v) (HW_LLWU_PE1_WR(HW_LLWU_PE1_RD() | (v)))
+#define HW_LLWU_PE1_CLR(v) (HW_LLWU_PE1_WR(HW_LLWU_PE1_RD() & ~(v)))
+#define HW_LLWU_PE1_TOG(v) (HW_LLWU_PE1_WR(HW_LLWU_PE1_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LLWU_PE1 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE1, field WUPE0[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE1_WUPE0 (0U) //!< Bit position for LLWU_PE1_WUPE0.
+#define BM_LLWU_PE1_WUPE0 (0x03U) //!< Bit mask for LLWU_PE1_WUPE0.
+#define BS_LLWU_PE1_WUPE0 (2U) //!< Bit field size in bits for LLWU_PE1_WUPE0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE1_WUPE0 field.
+#define BR_LLWU_PE1_WUPE0 (HW_LLWU_PE1.B.WUPE0)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE1_WUPE0.
+#define BF_LLWU_PE1_WUPE0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE1_WUPE0), uint8_t) & BM_LLWU_PE1_WUPE0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE0 field to a new value.
+#define BW_LLWU_PE1_WUPE0(v) (HW_LLWU_PE1_WR((HW_LLWU_PE1_RD() & ~BM_LLWU_PE1_WUPE0) | BF_LLWU_PE1_WUPE0(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_PE1, field WUPE1[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE1_WUPE1 (2U) //!< Bit position for LLWU_PE1_WUPE1.
+#define BM_LLWU_PE1_WUPE1 (0x0CU) //!< Bit mask for LLWU_PE1_WUPE1.
+#define BS_LLWU_PE1_WUPE1 (2U) //!< Bit field size in bits for LLWU_PE1_WUPE1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE1_WUPE1 field.
+#define BR_LLWU_PE1_WUPE1 (HW_LLWU_PE1.B.WUPE1)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE1_WUPE1.
+#define BF_LLWU_PE1_WUPE1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE1_WUPE1), uint8_t) & BM_LLWU_PE1_WUPE1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE1 field to a new value.
+#define BW_LLWU_PE1_WUPE1(v) (HW_LLWU_PE1_WR((HW_LLWU_PE1_RD() & ~BM_LLWU_PE1_WUPE1) | BF_LLWU_PE1_WUPE1(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_PE1, field WUPE2[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE1_WUPE2 (4U) //!< Bit position for LLWU_PE1_WUPE2.
+#define BM_LLWU_PE1_WUPE2 (0x30U) //!< Bit mask for LLWU_PE1_WUPE2.
+#define BS_LLWU_PE1_WUPE2 (2U) //!< Bit field size in bits for LLWU_PE1_WUPE2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE1_WUPE2 field.
+#define BR_LLWU_PE1_WUPE2 (HW_LLWU_PE1.B.WUPE2)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE1_WUPE2.
+#define BF_LLWU_PE1_WUPE2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE1_WUPE2), uint8_t) & BM_LLWU_PE1_WUPE2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE2 field to a new value.
+#define BW_LLWU_PE1_WUPE2(v) (HW_LLWU_PE1_WR((HW_LLWU_PE1_RD() & ~BM_LLWU_PE1_WUPE2) | BF_LLWU_PE1_WUPE2(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_PE1, field WUPE3[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE1_WUPE3 (6U) //!< Bit position for LLWU_PE1_WUPE3.
+#define BM_LLWU_PE1_WUPE3 (0xC0U) //!< Bit mask for LLWU_PE1_WUPE3.
+#define BS_LLWU_PE1_WUPE3 (2U) //!< Bit field size in bits for LLWU_PE1_WUPE3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE1_WUPE3 field.
+#define BR_LLWU_PE1_WUPE3 (HW_LLWU_PE1.B.WUPE3)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE1_WUPE3.
+#define BF_LLWU_PE1_WUPE3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE1_WUPE3), uint8_t) & BM_LLWU_PE1_WUPE3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE3 field to a new value.
+#define BW_LLWU_PE1_WUPE3(v) (HW_LLWU_PE1_WR((HW_LLWU_PE1_RD() & ~BM_LLWU_PE1_WUPE3) | BF_LLWU_PE1_WUPE3(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LLWU_PE2 - LLWU Pin Enable 2 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LLWU_PE2 - LLWU Pin Enable 2 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE2 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P7-LLWU_P4. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module
+ * (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+typedef union _hw_llwu_pe2
+{
+ uint8_t U;
+ struct _hw_llwu_pe2_bitfields
+ {
+ uint8_t WUPE4 : 2; //!< [1:0] Wakeup Pin Enable For LLWU_P4
+ uint8_t WUPE5 : 2; //!< [3:2] Wakeup Pin Enable For LLWU_P5
+ uint8_t WUPE6 : 2; //!< [5:4] Wakeup Pin Enable For LLWU_P6
+ uint8_t WUPE7 : 2; //!< [7:6] Wakeup Pin Enable For LLWU_P7
+ } B;
+} hw_llwu_pe2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LLWU_PE2 register
+ */
+//@{
+#define HW_LLWU_PE2_ADDR (REGS_LLWU_BASE + 0x1U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LLWU_PE2 (*(__IO hw_llwu_pe2_t *) HW_LLWU_PE2_ADDR)
+#define HW_LLWU_PE2_RD() (HW_LLWU_PE2.U)
+#define HW_LLWU_PE2_WR(v) (HW_LLWU_PE2.U = (v))
+#define HW_LLWU_PE2_SET(v) (HW_LLWU_PE2_WR(HW_LLWU_PE2_RD() | (v)))
+#define HW_LLWU_PE2_CLR(v) (HW_LLWU_PE2_WR(HW_LLWU_PE2_RD() & ~(v)))
+#define HW_LLWU_PE2_TOG(v) (HW_LLWU_PE2_WR(HW_LLWU_PE2_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LLWU_PE2 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE2, field WUPE4[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE2_WUPE4 (0U) //!< Bit position for LLWU_PE2_WUPE4.
+#define BM_LLWU_PE2_WUPE4 (0x03U) //!< Bit mask for LLWU_PE2_WUPE4.
+#define BS_LLWU_PE2_WUPE4 (2U) //!< Bit field size in bits for LLWU_PE2_WUPE4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE2_WUPE4 field.
+#define BR_LLWU_PE2_WUPE4 (HW_LLWU_PE2.B.WUPE4)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE2_WUPE4.
+#define BF_LLWU_PE2_WUPE4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE2_WUPE4), uint8_t) & BM_LLWU_PE2_WUPE4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE4 field to a new value.
+#define BW_LLWU_PE2_WUPE4(v) (HW_LLWU_PE2_WR((HW_LLWU_PE2_RD() & ~BM_LLWU_PE2_WUPE4) | BF_LLWU_PE2_WUPE4(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_PE2, field WUPE5[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE2_WUPE5 (2U) //!< Bit position for LLWU_PE2_WUPE5.
+#define BM_LLWU_PE2_WUPE5 (0x0CU) //!< Bit mask for LLWU_PE2_WUPE5.
+#define BS_LLWU_PE2_WUPE5 (2U) //!< Bit field size in bits for LLWU_PE2_WUPE5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE2_WUPE5 field.
+#define BR_LLWU_PE2_WUPE5 (HW_LLWU_PE2.B.WUPE5)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE2_WUPE5.
+#define BF_LLWU_PE2_WUPE5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE2_WUPE5), uint8_t) & BM_LLWU_PE2_WUPE5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE5 field to a new value.
+#define BW_LLWU_PE2_WUPE5(v) (HW_LLWU_PE2_WR((HW_LLWU_PE2_RD() & ~BM_LLWU_PE2_WUPE5) | BF_LLWU_PE2_WUPE5(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_PE2, field WUPE6[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE2_WUPE6 (4U) //!< Bit position for LLWU_PE2_WUPE6.
+#define BM_LLWU_PE2_WUPE6 (0x30U) //!< Bit mask for LLWU_PE2_WUPE6.
+#define BS_LLWU_PE2_WUPE6 (2U) //!< Bit field size in bits for LLWU_PE2_WUPE6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE2_WUPE6 field.
+#define BR_LLWU_PE2_WUPE6 (HW_LLWU_PE2.B.WUPE6)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE2_WUPE6.
+#define BF_LLWU_PE2_WUPE6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE2_WUPE6), uint8_t) & BM_LLWU_PE2_WUPE6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE6 field to a new value.
+#define BW_LLWU_PE2_WUPE6(v) (HW_LLWU_PE2_WR((HW_LLWU_PE2_RD() & ~BM_LLWU_PE2_WUPE6) | BF_LLWU_PE2_WUPE6(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_PE2, field WUPE7[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE2_WUPE7 (6U) //!< Bit position for LLWU_PE2_WUPE7.
+#define BM_LLWU_PE2_WUPE7 (0xC0U) //!< Bit mask for LLWU_PE2_WUPE7.
+#define BS_LLWU_PE2_WUPE7 (2U) //!< Bit field size in bits for LLWU_PE2_WUPE7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE2_WUPE7 field.
+#define BR_LLWU_PE2_WUPE7 (HW_LLWU_PE2.B.WUPE7)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE2_WUPE7.
+#define BF_LLWU_PE2_WUPE7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE2_WUPE7), uint8_t) & BM_LLWU_PE2_WUPE7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE7 field to a new value.
+#define BW_LLWU_PE2_WUPE7(v) (HW_LLWU_PE2_WR((HW_LLWU_PE2_RD() & ~BM_LLWU_PE2_WUPE7) | BF_LLWU_PE2_WUPE7(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LLWU_PE3 - LLWU Pin Enable 3 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LLWU_PE3 - LLWU Pin Enable 3 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE3 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P11-LLWU_P8. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module
+ * (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+typedef union _hw_llwu_pe3
+{
+ uint8_t U;
+ struct _hw_llwu_pe3_bitfields
+ {
+ uint8_t WUPE8 : 2; //!< [1:0] Wakeup Pin Enable For LLWU_P8
+ uint8_t WUPE9 : 2; //!< [3:2] Wakeup Pin Enable For LLWU_P9
+ uint8_t WUPE10 : 2; //!< [5:4] Wakeup Pin Enable For LLWU_P10
+ uint8_t WUPE11 : 2; //!< [7:6] Wakeup Pin Enable For LLWU_P11
+ } B;
+} hw_llwu_pe3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LLWU_PE3 register
+ */
+//@{
+#define HW_LLWU_PE3_ADDR (REGS_LLWU_BASE + 0x2U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LLWU_PE3 (*(__IO hw_llwu_pe3_t *) HW_LLWU_PE3_ADDR)
+#define HW_LLWU_PE3_RD() (HW_LLWU_PE3.U)
+#define HW_LLWU_PE3_WR(v) (HW_LLWU_PE3.U = (v))
+#define HW_LLWU_PE3_SET(v) (HW_LLWU_PE3_WR(HW_LLWU_PE3_RD() | (v)))
+#define HW_LLWU_PE3_CLR(v) (HW_LLWU_PE3_WR(HW_LLWU_PE3_RD() & ~(v)))
+#define HW_LLWU_PE3_TOG(v) (HW_LLWU_PE3_WR(HW_LLWU_PE3_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LLWU_PE3 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE3, field WUPE8[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE3_WUPE8 (0U) //!< Bit position for LLWU_PE3_WUPE8.
+#define BM_LLWU_PE3_WUPE8 (0x03U) //!< Bit mask for LLWU_PE3_WUPE8.
+#define BS_LLWU_PE3_WUPE8 (2U) //!< Bit field size in bits for LLWU_PE3_WUPE8.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE3_WUPE8 field.
+#define BR_LLWU_PE3_WUPE8 (HW_LLWU_PE3.B.WUPE8)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE3_WUPE8.
+#define BF_LLWU_PE3_WUPE8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE3_WUPE8), uint8_t) & BM_LLWU_PE3_WUPE8)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE8 field to a new value.
+#define BW_LLWU_PE3_WUPE8(v) (HW_LLWU_PE3_WR((HW_LLWU_PE3_RD() & ~BM_LLWU_PE3_WUPE8) | BF_LLWU_PE3_WUPE8(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_PE3, field WUPE9[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE3_WUPE9 (2U) //!< Bit position for LLWU_PE3_WUPE9.
+#define BM_LLWU_PE3_WUPE9 (0x0CU) //!< Bit mask for LLWU_PE3_WUPE9.
+#define BS_LLWU_PE3_WUPE9 (2U) //!< Bit field size in bits for LLWU_PE3_WUPE9.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE3_WUPE9 field.
+#define BR_LLWU_PE3_WUPE9 (HW_LLWU_PE3.B.WUPE9)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE3_WUPE9.
+#define BF_LLWU_PE3_WUPE9(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE3_WUPE9), uint8_t) & BM_LLWU_PE3_WUPE9)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE9 field to a new value.
+#define BW_LLWU_PE3_WUPE9(v) (HW_LLWU_PE3_WR((HW_LLWU_PE3_RD() & ~BM_LLWU_PE3_WUPE9) | BF_LLWU_PE3_WUPE9(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_PE3, field WUPE10[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE3_WUPE10 (4U) //!< Bit position for LLWU_PE3_WUPE10.
+#define BM_LLWU_PE3_WUPE10 (0x30U) //!< Bit mask for LLWU_PE3_WUPE10.
+#define BS_LLWU_PE3_WUPE10 (2U) //!< Bit field size in bits for LLWU_PE3_WUPE10.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE3_WUPE10 field.
+#define BR_LLWU_PE3_WUPE10 (HW_LLWU_PE3.B.WUPE10)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE3_WUPE10.
+#define BF_LLWU_PE3_WUPE10(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE3_WUPE10), uint8_t) & BM_LLWU_PE3_WUPE10)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE10 field to a new value.
+#define BW_LLWU_PE3_WUPE10(v) (HW_LLWU_PE3_WR((HW_LLWU_PE3_RD() & ~BM_LLWU_PE3_WUPE10) | BF_LLWU_PE3_WUPE10(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_PE3, field WUPE11[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE3_WUPE11 (6U) //!< Bit position for LLWU_PE3_WUPE11.
+#define BM_LLWU_PE3_WUPE11 (0xC0U) //!< Bit mask for LLWU_PE3_WUPE11.
+#define BS_LLWU_PE3_WUPE11 (2U) //!< Bit field size in bits for LLWU_PE3_WUPE11.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE3_WUPE11 field.
+#define BR_LLWU_PE3_WUPE11 (HW_LLWU_PE3.B.WUPE11)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE3_WUPE11.
+#define BF_LLWU_PE3_WUPE11(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE3_WUPE11), uint8_t) & BM_LLWU_PE3_WUPE11)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE11 field to a new value.
+#define BW_LLWU_PE3_WUPE11(v) (HW_LLWU_PE3_WR((HW_LLWU_PE3_RD() & ~BM_LLWU_PE3_WUPE11) | BF_LLWU_PE3_WUPE11(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LLWU_PE4 - LLWU Pin Enable 4 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LLWU_PE4 - LLWU Pin Enable 4 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE4 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P15-LLWU_P12. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+typedef union _hw_llwu_pe4
+{
+ uint8_t U;
+ struct _hw_llwu_pe4_bitfields
+ {
+ uint8_t WUPE12 : 2; //!< [1:0] Wakeup Pin Enable For LLWU_P12
+ uint8_t WUPE13 : 2; //!< [3:2] Wakeup Pin Enable For LLWU_P13
+ uint8_t WUPE14 : 2; //!< [5:4] Wakeup Pin Enable For LLWU_P14
+ uint8_t WUPE15 : 2; //!< [7:6] Wakeup Pin Enable For LLWU_P15
+ } B;
+} hw_llwu_pe4_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LLWU_PE4 register
+ */
+//@{
+#define HW_LLWU_PE4_ADDR (REGS_LLWU_BASE + 0x3U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LLWU_PE4 (*(__IO hw_llwu_pe4_t *) HW_LLWU_PE4_ADDR)
+#define HW_LLWU_PE4_RD() (HW_LLWU_PE4.U)
+#define HW_LLWU_PE4_WR(v) (HW_LLWU_PE4.U = (v))
+#define HW_LLWU_PE4_SET(v) (HW_LLWU_PE4_WR(HW_LLWU_PE4_RD() | (v)))
+#define HW_LLWU_PE4_CLR(v) (HW_LLWU_PE4_WR(HW_LLWU_PE4_RD() & ~(v)))
+#define HW_LLWU_PE4_TOG(v) (HW_LLWU_PE4_WR(HW_LLWU_PE4_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LLWU_PE4 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE4, field WUPE12[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE4_WUPE12 (0U) //!< Bit position for LLWU_PE4_WUPE12.
+#define BM_LLWU_PE4_WUPE12 (0x03U) //!< Bit mask for LLWU_PE4_WUPE12.
+#define BS_LLWU_PE4_WUPE12 (2U) //!< Bit field size in bits for LLWU_PE4_WUPE12.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE4_WUPE12 field.
+#define BR_LLWU_PE4_WUPE12 (HW_LLWU_PE4.B.WUPE12)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE4_WUPE12.
+#define BF_LLWU_PE4_WUPE12(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE4_WUPE12), uint8_t) & BM_LLWU_PE4_WUPE12)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE12 field to a new value.
+#define BW_LLWU_PE4_WUPE12(v) (HW_LLWU_PE4_WR((HW_LLWU_PE4_RD() & ~BM_LLWU_PE4_WUPE12) | BF_LLWU_PE4_WUPE12(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_PE4, field WUPE13[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE4_WUPE13 (2U) //!< Bit position for LLWU_PE4_WUPE13.
+#define BM_LLWU_PE4_WUPE13 (0x0CU) //!< Bit mask for LLWU_PE4_WUPE13.
+#define BS_LLWU_PE4_WUPE13 (2U) //!< Bit field size in bits for LLWU_PE4_WUPE13.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE4_WUPE13 field.
+#define BR_LLWU_PE4_WUPE13 (HW_LLWU_PE4.B.WUPE13)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE4_WUPE13.
+#define BF_LLWU_PE4_WUPE13(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE4_WUPE13), uint8_t) & BM_LLWU_PE4_WUPE13)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE13 field to a new value.
+#define BW_LLWU_PE4_WUPE13(v) (HW_LLWU_PE4_WR((HW_LLWU_PE4_RD() & ~BM_LLWU_PE4_WUPE13) | BF_LLWU_PE4_WUPE13(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_PE4, field WUPE14[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE4_WUPE14 (4U) //!< Bit position for LLWU_PE4_WUPE14.
+#define BM_LLWU_PE4_WUPE14 (0x30U) //!< Bit mask for LLWU_PE4_WUPE14.
+#define BS_LLWU_PE4_WUPE14 (2U) //!< Bit field size in bits for LLWU_PE4_WUPE14.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE4_WUPE14 field.
+#define BR_LLWU_PE4_WUPE14 (HW_LLWU_PE4.B.WUPE14)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE4_WUPE14.
+#define BF_LLWU_PE4_WUPE14(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE4_WUPE14), uint8_t) & BM_LLWU_PE4_WUPE14)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE14 field to a new value.
+#define BW_LLWU_PE4_WUPE14(v) (HW_LLWU_PE4_WR((HW_LLWU_PE4_RD() & ~BM_LLWU_PE4_WUPE14) | BF_LLWU_PE4_WUPE14(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_PE4, field WUPE15[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 00 - External input pin disabled as wakeup input
+ * - 01 - External input pin enabled with rising edge detection
+ * - 10 - External input pin enabled with falling edge detection
+ * - 11 - External input pin enabled with any change detection
+ */
+//@{
+#define BP_LLWU_PE4_WUPE15 (6U) //!< Bit position for LLWU_PE4_WUPE15.
+#define BM_LLWU_PE4_WUPE15 (0xC0U) //!< Bit mask for LLWU_PE4_WUPE15.
+#define BS_LLWU_PE4_WUPE15 (2U) //!< Bit field size in bits for LLWU_PE4_WUPE15.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_PE4_WUPE15 field.
+#define BR_LLWU_PE4_WUPE15 (HW_LLWU_PE4.B.WUPE15)
+#endif
+
+//! @brief Format value for bitfield LLWU_PE4_WUPE15.
+#define BF_LLWU_PE4_WUPE15(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_PE4_WUPE15), uint8_t) & BM_LLWU_PE4_WUPE15)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUPE15 field to a new value.
+#define BW_LLWU_PE4_WUPE15(v) (HW_LLWU_PE4_WR((HW_LLWU_PE4_RD() & ~BM_LLWU_PE4_WUPE15) | BF_LLWU_PE4_WUPE15(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LLWU_ME - LLWU Module Enable register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LLWU_ME - LLWU Module Enable register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_ME contains the bits to enable the internal module flag as a wakeup
+ * input source for inputs MWUF7-MWUF0. This register is reset on Chip Reset not VLLS
+ * and by reset types that trigger Chip Reset not VLLS. It is unaffected by
+ * reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module (RCM). The
+ * RCM implements many of the reset functions for the chip. See the chip's reset
+ * chapter for more information. details for more information.
+ */
+typedef union _hw_llwu_me
+{
+ uint8_t U;
+ struct _hw_llwu_me_bitfields
+ {
+ uint8_t WUME0 : 1; //!< [0] Wakeup Module Enable For Module 0
+ uint8_t WUME1 : 1; //!< [1] Wakeup Module Enable for Module 1
+ uint8_t WUME2 : 1; //!< [2] Wakeup Module Enable For Module 2
+ uint8_t WUME3 : 1; //!< [3] Wakeup Module Enable For Module 3
+ uint8_t WUME4 : 1; //!< [4] Wakeup Module Enable For Module 4
+ uint8_t WUME5 : 1; //!< [5] Wakeup Module Enable For Module 5
+ uint8_t WUME6 : 1; //!< [6] Wakeup Module Enable For Module 6
+ uint8_t WUME7 : 1; //!< [7] Wakeup Module Enable For Module 7
+ } B;
+} hw_llwu_me_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LLWU_ME register
+ */
+//@{
+#define HW_LLWU_ME_ADDR (REGS_LLWU_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LLWU_ME (*(__IO hw_llwu_me_t *) HW_LLWU_ME_ADDR)
+#define HW_LLWU_ME_RD() (HW_LLWU_ME.U)
+#define HW_LLWU_ME_WR(v) (HW_LLWU_ME.U = (v))
+#define HW_LLWU_ME_SET(v) (HW_LLWU_ME_WR(HW_LLWU_ME_RD() | (v)))
+#define HW_LLWU_ME_CLR(v) (HW_LLWU_ME_WR(HW_LLWU_ME_RD() & ~(v)))
+#define HW_LLWU_ME_TOG(v) (HW_LLWU_ME_WR(HW_LLWU_ME_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LLWU_ME bitfields
+ */
+
+/*!
+ * @name Register LLWU_ME, field WUME0[0] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0 - Internal module flag not used as wakeup source
+ * - 1 - Internal module flag used as wakeup source
+ */
+//@{
+#define BP_LLWU_ME_WUME0 (0U) //!< Bit position for LLWU_ME_WUME0.
+#define BM_LLWU_ME_WUME0 (0x01U) //!< Bit mask for LLWU_ME_WUME0.
+#define BS_LLWU_ME_WUME0 (1U) //!< Bit field size in bits for LLWU_ME_WUME0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_ME_WUME0 field.
+#define BR_LLWU_ME_WUME0 (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME0))
+#endif
+
+//! @brief Format value for bitfield LLWU_ME_WUME0.
+#define BF_LLWU_ME_WUME0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME0), uint8_t) & BM_LLWU_ME_WUME0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUME0 field to a new value.
+#define BW_LLWU_ME_WUME0(v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_ME, field WUME1[1] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0 - Internal module flag not used as wakeup source
+ * - 1 - Internal module flag used as wakeup source
+ */
+//@{
+#define BP_LLWU_ME_WUME1 (1U) //!< Bit position for LLWU_ME_WUME1.
+#define BM_LLWU_ME_WUME1 (0x02U) //!< Bit mask for LLWU_ME_WUME1.
+#define BS_LLWU_ME_WUME1 (1U) //!< Bit field size in bits for LLWU_ME_WUME1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_ME_WUME1 field.
+#define BR_LLWU_ME_WUME1 (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME1))
+#endif
+
+//! @brief Format value for bitfield LLWU_ME_WUME1.
+#define BF_LLWU_ME_WUME1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME1), uint8_t) & BM_LLWU_ME_WUME1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUME1 field to a new value.
+#define BW_LLWU_ME_WUME1(v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_ME, field WUME2[2] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0 - Internal module flag not used as wakeup source
+ * - 1 - Internal module flag used as wakeup source
+ */
+//@{
+#define BP_LLWU_ME_WUME2 (2U) //!< Bit position for LLWU_ME_WUME2.
+#define BM_LLWU_ME_WUME2 (0x04U) //!< Bit mask for LLWU_ME_WUME2.
+#define BS_LLWU_ME_WUME2 (1U) //!< Bit field size in bits for LLWU_ME_WUME2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_ME_WUME2 field.
+#define BR_LLWU_ME_WUME2 (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME2))
+#endif
+
+//! @brief Format value for bitfield LLWU_ME_WUME2.
+#define BF_LLWU_ME_WUME2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME2), uint8_t) & BM_LLWU_ME_WUME2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUME2 field to a new value.
+#define BW_LLWU_ME_WUME2(v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_ME, field WUME3[3] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0 - Internal module flag not used as wakeup source
+ * - 1 - Internal module flag used as wakeup source
+ */
+//@{
+#define BP_LLWU_ME_WUME3 (3U) //!< Bit position for LLWU_ME_WUME3.
+#define BM_LLWU_ME_WUME3 (0x08U) //!< Bit mask for LLWU_ME_WUME3.
+#define BS_LLWU_ME_WUME3 (1U) //!< Bit field size in bits for LLWU_ME_WUME3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_ME_WUME3 field.
+#define BR_LLWU_ME_WUME3 (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME3))
+#endif
+
+//! @brief Format value for bitfield LLWU_ME_WUME3.
+#define BF_LLWU_ME_WUME3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME3), uint8_t) & BM_LLWU_ME_WUME3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUME3 field to a new value.
+#define BW_LLWU_ME_WUME3(v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_ME, field WUME4[4] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0 - Internal module flag not used as wakeup source
+ * - 1 - Internal module flag used as wakeup source
+ */
+//@{
+#define BP_LLWU_ME_WUME4 (4U) //!< Bit position for LLWU_ME_WUME4.
+#define BM_LLWU_ME_WUME4 (0x10U) //!< Bit mask for LLWU_ME_WUME4.
+#define BS_LLWU_ME_WUME4 (1U) //!< Bit field size in bits for LLWU_ME_WUME4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_ME_WUME4 field.
+#define BR_LLWU_ME_WUME4 (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME4))
+#endif
+
+//! @brief Format value for bitfield LLWU_ME_WUME4.
+#define BF_LLWU_ME_WUME4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME4), uint8_t) & BM_LLWU_ME_WUME4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUME4 field to a new value.
+#define BW_LLWU_ME_WUME4(v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_ME, field WUME5[5] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0 - Internal module flag not used as wakeup source
+ * - 1 - Internal module flag used as wakeup source
+ */
+//@{
+#define BP_LLWU_ME_WUME5 (5U) //!< Bit position for LLWU_ME_WUME5.
+#define BM_LLWU_ME_WUME5 (0x20U) //!< Bit mask for LLWU_ME_WUME5.
+#define BS_LLWU_ME_WUME5 (1U) //!< Bit field size in bits for LLWU_ME_WUME5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_ME_WUME5 field.
+#define BR_LLWU_ME_WUME5 (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME5))
+#endif
+
+//! @brief Format value for bitfield LLWU_ME_WUME5.
+#define BF_LLWU_ME_WUME5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME5), uint8_t) & BM_LLWU_ME_WUME5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUME5 field to a new value.
+#define BW_LLWU_ME_WUME5(v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_ME, field WUME6[6] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0 - Internal module flag not used as wakeup source
+ * - 1 - Internal module flag used as wakeup source
+ */
+//@{
+#define BP_LLWU_ME_WUME6 (6U) //!< Bit position for LLWU_ME_WUME6.
+#define BM_LLWU_ME_WUME6 (0x40U) //!< Bit mask for LLWU_ME_WUME6.
+#define BS_LLWU_ME_WUME6 (1U) //!< Bit field size in bits for LLWU_ME_WUME6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_ME_WUME6 field.
+#define BR_LLWU_ME_WUME6 (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME6))
+#endif
+
+//! @brief Format value for bitfield LLWU_ME_WUME6.
+#define BF_LLWU_ME_WUME6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME6), uint8_t) & BM_LLWU_ME_WUME6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUME6 field to a new value.
+#define BW_LLWU_ME_WUME6(v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_ME, field WUME7[7] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0 - Internal module flag not used as wakeup source
+ * - 1 - Internal module flag used as wakeup source
+ */
+//@{
+#define BP_LLWU_ME_WUME7 (7U) //!< Bit position for LLWU_ME_WUME7.
+#define BM_LLWU_ME_WUME7 (0x80U) //!< Bit mask for LLWU_ME_WUME7.
+#define BS_LLWU_ME_WUME7 (1U) //!< Bit field size in bits for LLWU_ME_WUME7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_ME_WUME7 field.
+#define BR_LLWU_ME_WUME7 (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME7))
+#endif
+
+//! @brief Format value for bitfield LLWU_ME_WUME7.
+#define BF_LLWU_ME_WUME7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_ME_WUME7), uint8_t) & BM_LLWU_ME_WUME7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUME7 field to a new value.
+#define BW_LLWU_ME_WUME7(v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR, BP_LLWU_ME_WUME7) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LLWU_F1 - LLWU Flag 1 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LLWU_F1 - LLWU Flag 1 register (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_F1 contains the wakeup flags indicating which wakeup source caused the
+ * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
+ * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
+ * external wakeup flags are read-only and clearing a flag is accomplished by a write
+ * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
+ * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+typedef union _hw_llwu_f1
+{
+ uint8_t U;
+ struct _hw_llwu_f1_bitfields
+ {
+ uint8_t WUF0 : 1; //!< [0] Wakeup Flag For LLWU_P0
+ uint8_t WUF1 : 1; //!< [1] Wakeup Flag For LLWU_P1
+ uint8_t WUF2 : 1; //!< [2] Wakeup Flag For LLWU_P2
+ uint8_t WUF3 : 1; //!< [3] Wakeup Flag For LLWU_P3
+ uint8_t WUF4 : 1; //!< [4] Wakeup Flag For LLWU_P4
+ uint8_t WUF5 : 1; //!< [5] Wakeup Flag For LLWU_P5
+ uint8_t WUF6 : 1; //!< [6] Wakeup Flag For LLWU_P6
+ uint8_t WUF7 : 1; //!< [7] Wakeup Flag For LLWU_P7
+ } B;
+} hw_llwu_f1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LLWU_F1 register
+ */
+//@{
+#define HW_LLWU_F1_ADDR (REGS_LLWU_BASE + 0x5U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LLWU_F1 (*(__IO hw_llwu_f1_t *) HW_LLWU_F1_ADDR)
+#define HW_LLWU_F1_RD() (HW_LLWU_F1.U)
+#define HW_LLWU_F1_WR(v) (HW_LLWU_F1.U = (v))
+#define HW_LLWU_F1_SET(v) (HW_LLWU_F1_WR(HW_LLWU_F1_RD() | (v)))
+#define HW_LLWU_F1_CLR(v) (HW_LLWU_F1_WR(HW_LLWU_F1_RD() & ~(v)))
+#define HW_LLWU_F1_TOG(v) (HW_LLWU_F1_WR(HW_LLWU_F1_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LLWU_F1 bitfields
+ */
+
+/*!
+ * @name Register LLWU_F1, field WUF0[0] (W1C)
+ *
+ * Indicates that an enabled external wake-up pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF0.
+ *
+ * Values:
+ * - 0 - LLWU_P0 input was not a wakeup source
+ * - 1 - LLWU_P0 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F1_WUF0 (0U) //!< Bit position for LLWU_F1_WUF0.
+#define BM_LLWU_F1_WUF0 (0x01U) //!< Bit mask for LLWU_F1_WUF0.
+#define BS_LLWU_F1_WUF0 (1U) //!< Bit field size in bits for LLWU_F1_WUF0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F1_WUF0 field.
+#define BR_LLWU_F1_WUF0 (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF0))
+#endif
+
+//! @brief Format value for bitfield LLWU_F1_WUF0.
+#define BF_LLWU_F1_WUF0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF0), uint8_t) & BM_LLWU_F1_WUF0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF0 field to a new value.
+#define BW_LLWU_F1_WUF0(v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F1, field WUF1[1] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF1.
+ *
+ * Values:
+ * - 0 - LLWU_P1 input was not a wakeup source
+ * - 1 - LLWU_P1 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F1_WUF1 (1U) //!< Bit position for LLWU_F1_WUF1.
+#define BM_LLWU_F1_WUF1 (0x02U) //!< Bit mask for LLWU_F1_WUF1.
+#define BS_LLWU_F1_WUF1 (1U) //!< Bit field size in bits for LLWU_F1_WUF1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F1_WUF1 field.
+#define BR_LLWU_F1_WUF1 (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF1))
+#endif
+
+//! @brief Format value for bitfield LLWU_F1_WUF1.
+#define BF_LLWU_F1_WUF1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF1), uint8_t) & BM_LLWU_F1_WUF1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF1 field to a new value.
+#define BW_LLWU_F1_WUF1(v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F1, field WUF2[2] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF2.
+ *
+ * Values:
+ * - 0 - LLWU_P2 input was not a wakeup source
+ * - 1 - LLWU_P2 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F1_WUF2 (2U) //!< Bit position for LLWU_F1_WUF2.
+#define BM_LLWU_F1_WUF2 (0x04U) //!< Bit mask for LLWU_F1_WUF2.
+#define BS_LLWU_F1_WUF2 (1U) //!< Bit field size in bits for LLWU_F1_WUF2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F1_WUF2 field.
+#define BR_LLWU_F1_WUF2 (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF2))
+#endif
+
+//! @brief Format value for bitfield LLWU_F1_WUF2.
+#define BF_LLWU_F1_WUF2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF2), uint8_t) & BM_LLWU_F1_WUF2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF2 field to a new value.
+#define BW_LLWU_F1_WUF2(v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F1, field WUF3[3] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF3.
+ *
+ * Values:
+ * - 0 - LLWU_P3 input was not a wake-up source
+ * - 1 - LLWU_P3 input was a wake-up source
+ */
+//@{
+#define BP_LLWU_F1_WUF3 (3U) //!< Bit position for LLWU_F1_WUF3.
+#define BM_LLWU_F1_WUF3 (0x08U) //!< Bit mask for LLWU_F1_WUF3.
+#define BS_LLWU_F1_WUF3 (1U) //!< Bit field size in bits for LLWU_F1_WUF3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F1_WUF3 field.
+#define BR_LLWU_F1_WUF3 (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF3))
+#endif
+
+//! @brief Format value for bitfield LLWU_F1_WUF3.
+#define BF_LLWU_F1_WUF3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF3), uint8_t) & BM_LLWU_F1_WUF3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF3 field to a new value.
+#define BW_LLWU_F1_WUF3(v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F1, field WUF4[4] (W1C)
+ *
+ * Indicates that an enabled external wake-up pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF4.
+ *
+ * Values:
+ * - 0 - LLWU_P4 input was not a wakeup source
+ * - 1 - LLWU_P4 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F1_WUF4 (4U) //!< Bit position for LLWU_F1_WUF4.
+#define BM_LLWU_F1_WUF4 (0x10U) //!< Bit mask for LLWU_F1_WUF4.
+#define BS_LLWU_F1_WUF4 (1U) //!< Bit field size in bits for LLWU_F1_WUF4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F1_WUF4 field.
+#define BR_LLWU_F1_WUF4 (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF4))
+#endif
+
+//! @brief Format value for bitfield LLWU_F1_WUF4.
+#define BF_LLWU_F1_WUF4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF4), uint8_t) & BM_LLWU_F1_WUF4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF4 field to a new value.
+#define BW_LLWU_F1_WUF4(v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F1, field WUF5[5] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF5.
+ *
+ * Values:
+ * - 0 - LLWU_P5 input was not a wakeup source
+ * - 1 - LLWU_P5 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F1_WUF5 (5U) //!< Bit position for LLWU_F1_WUF5.
+#define BM_LLWU_F1_WUF5 (0x20U) //!< Bit mask for LLWU_F1_WUF5.
+#define BS_LLWU_F1_WUF5 (1U) //!< Bit field size in bits for LLWU_F1_WUF5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F1_WUF5 field.
+#define BR_LLWU_F1_WUF5 (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF5))
+#endif
+
+//! @brief Format value for bitfield LLWU_F1_WUF5.
+#define BF_LLWU_F1_WUF5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF5), uint8_t) & BM_LLWU_F1_WUF5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF5 field to a new value.
+#define BW_LLWU_F1_WUF5(v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF5) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F1, field WUF6[6] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF6.
+ *
+ * Values:
+ * - 0 - LLWU_P6 input was not a wakeup source
+ * - 1 - LLWU_P6 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F1_WUF6 (6U) //!< Bit position for LLWU_F1_WUF6.
+#define BM_LLWU_F1_WUF6 (0x40U) //!< Bit mask for LLWU_F1_WUF6.
+#define BS_LLWU_F1_WUF6 (1U) //!< Bit field size in bits for LLWU_F1_WUF6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F1_WUF6 field.
+#define BR_LLWU_F1_WUF6 (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF6))
+#endif
+
+//! @brief Format value for bitfield LLWU_F1_WUF6.
+#define BF_LLWU_F1_WUF6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF6), uint8_t) & BM_LLWU_F1_WUF6)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF6 field to a new value.
+#define BW_LLWU_F1_WUF6(v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF6) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F1, field WUF7[7] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF7.
+ *
+ * Values:
+ * - 0 - LLWU_P7 input was not a wakeup source
+ * - 1 - LLWU_P7 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F1_WUF7 (7U) //!< Bit position for LLWU_F1_WUF7.
+#define BM_LLWU_F1_WUF7 (0x80U) //!< Bit mask for LLWU_F1_WUF7.
+#define BS_LLWU_F1_WUF7 (1U) //!< Bit field size in bits for LLWU_F1_WUF7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F1_WUF7 field.
+#define BR_LLWU_F1_WUF7 (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF7))
+#endif
+
+//! @brief Format value for bitfield LLWU_F1_WUF7.
+#define BF_LLWU_F1_WUF7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F1_WUF7), uint8_t) & BM_LLWU_F1_WUF7)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF7 field to a new value.
+#define BW_LLWU_F1_WUF7(v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR, BP_LLWU_F1_WUF7) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LLWU_F2 - LLWU Flag 2 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LLWU_F2 - LLWU Flag 2 register (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_F2 contains the wakeup flags indicating which wakeup source caused the
+ * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
+ * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
+ * external wakeup flags are read-only and clearing a flag is accomplished by a write
+ * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
+ * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+typedef union _hw_llwu_f2
+{
+ uint8_t U;
+ struct _hw_llwu_f2_bitfields
+ {
+ uint8_t WUF8 : 1; //!< [0] Wakeup Flag For LLWU_P8
+ uint8_t WUF9 : 1; //!< [1] Wakeup Flag For LLWU_P9
+ uint8_t WUF10 : 1; //!< [2] Wakeup Flag For LLWU_P10
+ uint8_t WUF11 : 1; //!< [3] Wakeup Flag For LLWU_P11
+ uint8_t WUF12 : 1; //!< [4] Wakeup Flag For LLWU_P12
+ uint8_t WUF13 : 1; //!< [5] Wakeup Flag For LLWU_P13
+ uint8_t WUF14 : 1; //!< [6] Wakeup Flag For LLWU_P14
+ uint8_t WUF15 : 1; //!< [7] Wakeup Flag For LLWU_P15
+ } B;
+} hw_llwu_f2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LLWU_F2 register
+ */
+//@{
+#define HW_LLWU_F2_ADDR (REGS_LLWU_BASE + 0x6U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LLWU_F2 (*(__IO hw_llwu_f2_t *) HW_LLWU_F2_ADDR)
+#define HW_LLWU_F2_RD() (HW_LLWU_F2.U)
+#define HW_LLWU_F2_WR(v) (HW_LLWU_F2.U = (v))
+#define HW_LLWU_F2_SET(v) (HW_LLWU_F2_WR(HW_LLWU_F2_RD() | (v)))
+#define HW_LLWU_F2_CLR(v) (HW_LLWU_F2_WR(HW_LLWU_F2_RD() & ~(v)))
+#define HW_LLWU_F2_TOG(v) (HW_LLWU_F2_WR(HW_LLWU_F2_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LLWU_F2 bitfields
+ */
+
+/*!
+ * @name Register LLWU_F2, field WUF8[0] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF8.
+ *
+ * Values:
+ * - 0 - LLWU_P8 input was not a wakeup source
+ * - 1 - LLWU_P8 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F2_WUF8 (0U) //!< Bit position for LLWU_F2_WUF8.
+#define BM_LLWU_F2_WUF8 (0x01U) //!< Bit mask for LLWU_F2_WUF8.
+#define BS_LLWU_F2_WUF8 (1U) //!< Bit field size in bits for LLWU_F2_WUF8.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F2_WUF8 field.
+#define BR_LLWU_F2_WUF8 (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF8))
+#endif
+
+//! @brief Format value for bitfield LLWU_F2_WUF8.
+#define BF_LLWU_F2_WUF8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF8), uint8_t) & BM_LLWU_F2_WUF8)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF8 field to a new value.
+#define BW_LLWU_F2_WUF8(v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF8) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F2, field WUF9[1] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF9.
+ *
+ * Values:
+ * - 0 - LLWU_P9 input was not a wakeup source
+ * - 1 - LLWU_P9 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F2_WUF9 (1U) //!< Bit position for LLWU_F2_WUF9.
+#define BM_LLWU_F2_WUF9 (0x02U) //!< Bit mask for LLWU_F2_WUF9.
+#define BS_LLWU_F2_WUF9 (1U) //!< Bit field size in bits for LLWU_F2_WUF9.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F2_WUF9 field.
+#define BR_LLWU_F2_WUF9 (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF9))
+#endif
+
+//! @brief Format value for bitfield LLWU_F2_WUF9.
+#define BF_LLWU_F2_WUF9(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF9), uint8_t) & BM_LLWU_F2_WUF9)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF9 field to a new value.
+#define BW_LLWU_F2_WUF9(v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF9) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F2, field WUF10[2] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF10.
+ *
+ * Values:
+ * - 0 - LLWU_P10 input was not a wakeup source
+ * - 1 - LLWU_P10 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F2_WUF10 (2U) //!< Bit position for LLWU_F2_WUF10.
+#define BM_LLWU_F2_WUF10 (0x04U) //!< Bit mask for LLWU_F2_WUF10.
+#define BS_LLWU_F2_WUF10 (1U) //!< Bit field size in bits for LLWU_F2_WUF10.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F2_WUF10 field.
+#define BR_LLWU_F2_WUF10 (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF10))
+#endif
+
+//! @brief Format value for bitfield LLWU_F2_WUF10.
+#define BF_LLWU_F2_WUF10(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF10), uint8_t) & BM_LLWU_F2_WUF10)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF10 field to a new value.
+#define BW_LLWU_F2_WUF10(v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF10) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F2, field WUF11[3] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF11.
+ *
+ * Values:
+ * - 0 - LLWU_P11 input was not a wakeup source
+ * - 1 - LLWU_P11 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F2_WUF11 (3U) //!< Bit position for LLWU_F2_WUF11.
+#define BM_LLWU_F2_WUF11 (0x08U) //!< Bit mask for LLWU_F2_WUF11.
+#define BS_LLWU_F2_WUF11 (1U) //!< Bit field size in bits for LLWU_F2_WUF11.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F2_WUF11 field.
+#define BR_LLWU_F2_WUF11 (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF11))
+#endif
+
+//! @brief Format value for bitfield LLWU_F2_WUF11.
+#define BF_LLWU_F2_WUF11(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF11), uint8_t) & BM_LLWU_F2_WUF11)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF11 field to a new value.
+#define BW_LLWU_F2_WUF11(v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF11) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F2, field WUF12[4] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF12.
+ *
+ * Values:
+ * - 0 - LLWU_P12 input was not a wakeup source
+ * - 1 - LLWU_P12 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F2_WUF12 (4U) //!< Bit position for LLWU_F2_WUF12.
+#define BM_LLWU_F2_WUF12 (0x10U) //!< Bit mask for LLWU_F2_WUF12.
+#define BS_LLWU_F2_WUF12 (1U) //!< Bit field size in bits for LLWU_F2_WUF12.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F2_WUF12 field.
+#define BR_LLWU_F2_WUF12 (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF12))
+#endif
+
+//! @brief Format value for bitfield LLWU_F2_WUF12.
+#define BF_LLWU_F2_WUF12(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF12), uint8_t) & BM_LLWU_F2_WUF12)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF12 field to a new value.
+#define BW_LLWU_F2_WUF12(v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF12) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F2, field WUF13[5] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF13.
+ *
+ * Values:
+ * - 0 - LLWU_P13 input was not a wakeup source
+ * - 1 - LLWU_P13 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F2_WUF13 (5U) //!< Bit position for LLWU_F2_WUF13.
+#define BM_LLWU_F2_WUF13 (0x20U) //!< Bit mask for LLWU_F2_WUF13.
+#define BS_LLWU_F2_WUF13 (1U) //!< Bit field size in bits for LLWU_F2_WUF13.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F2_WUF13 field.
+#define BR_LLWU_F2_WUF13 (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF13))
+#endif
+
+//! @brief Format value for bitfield LLWU_F2_WUF13.
+#define BF_LLWU_F2_WUF13(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF13), uint8_t) & BM_LLWU_F2_WUF13)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF13 field to a new value.
+#define BW_LLWU_F2_WUF13(v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF13) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F2, field WUF14[6] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF14.
+ *
+ * Values:
+ * - 0 - LLWU_P14 input was not a wakeup source
+ * - 1 - LLWU_P14 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F2_WUF14 (6U) //!< Bit position for LLWU_F2_WUF14.
+#define BM_LLWU_F2_WUF14 (0x40U) //!< Bit mask for LLWU_F2_WUF14.
+#define BS_LLWU_F2_WUF14 (1U) //!< Bit field size in bits for LLWU_F2_WUF14.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F2_WUF14 field.
+#define BR_LLWU_F2_WUF14 (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF14))
+#endif
+
+//! @brief Format value for bitfield LLWU_F2_WUF14.
+#define BF_LLWU_F2_WUF14(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF14), uint8_t) & BM_LLWU_F2_WUF14)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF14 field to a new value.
+#define BW_LLWU_F2_WUF14(v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF14) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F2, field WUF15[7] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF15.
+ *
+ * Values:
+ * - 0 - LLWU_P15 input was not a wakeup source
+ * - 1 - LLWU_P15 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F2_WUF15 (7U) //!< Bit position for LLWU_F2_WUF15.
+#define BM_LLWU_F2_WUF15 (0x80U) //!< Bit mask for LLWU_F2_WUF15.
+#define BS_LLWU_F2_WUF15 (1U) //!< Bit field size in bits for LLWU_F2_WUF15.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F2_WUF15 field.
+#define BR_LLWU_F2_WUF15 (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF15))
+#endif
+
+//! @brief Format value for bitfield LLWU_F2_WUF15.
+#define BF_LLWU_F2_WUF15(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_F2_WUF15), uint8_t) & BM_LLWU_F2_WUF15)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WUF15 field to a new value.
+#define BW_LLWU_F2_WUF15(v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR, BP_LLWU_F2_WUF15) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LLWU_F3 - LLWU Flag 3 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LLWU_F3 - LLWU Flag 3 register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_F3 contains the wakeup flags indicating which internal wakeup source
+ * caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the
+ * CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow.
+ * For internal peripherals that are capable of running in a low-leakage power
+ * mode, such as a real time clock module or CMP module, the flag from the
+ * associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared
+ * in the peripheral instead of writing a 1 to the MWUFx bit. This register is
+ * reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not
+ * VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See
+ * the IntroductionInformation found here describes the registers of the Reset
+ * Control Module (RCM). The RCM implements many of the reset functions for the
+ * chip. See the chip's reset chapter for more information. details for more
+ * information.
+ */
+typedef union _hw_llwu_f3
+{
+ uint8_t U;
+ struct _hw_llwu_f3_bitfields
+ {
+ uint8_t MWUF0 : 1; //!< [0] Wakeup flag For module 0
+ uint8_t MWUF1 : 1; //!< [1] Wakeup flag For module 1
+ uint8_t MWUF2 : 1; //!< [2] Wakeup flag For module 2
+ uint8_t MWUF3 : 1; //!< [3] Wakeup flag For module 3
+ uint8_t MWUF4 : 1; //!< [4] Wakeup flag For module 4
+ uint8_t MWUF5 : 1; //!< [5] Wakeup flag For module 5
+ uint8_t MWUF6 : 1; //!< [6] Wakeup flag For module 6
+ uint8_t MWUF7 : 1; //!< [7] Wakeup flag For module 7
+ } B;
+} hw_llwu_f3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LLWU_F3 register
+ */
+//@{
+#define HW_LLWU_F3_ADDR (REGS_LLWU_BASE + 0x7U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LLWU_F3 (*(__I hw_llwu_f3_t *) HW_LLWU_F3_ADDR)
+#define HW_LLWU_F3_RD() (HW_LLWU_F3.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LLWU_F3 bitfields
+ */
+
+/*!
+ * @name Register LLWU_F3, field MWUF0[0] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0 - Module 0 input was not a wakeup source
+ * - 1 - Module 0 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F3_MWUF0 (0U) //!< Bit position for LLWU_F3_MWUF0.
+#define BM_LLWU_F3_MWUF0 (0x01U) //!< Bit mask for LLWU_F3_MWUF0.
+#define BS_LLWU_F3_MWUF0 (1U) //!< Bit field size in bits for LLWU_F3_MWUF0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F3_MWUF0 field.
+#define BR_LLWU_F3_MWUF0 (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF0))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F3, field MWUF1[1] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0 - Module 1 input was not a wakeup source
+ * - 1 - Module 1 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F3_MWUF1 (1U) //!< Bit position for LLWU_F3_MWUF1.
+#define BM_LLWU_F3_MWUF1 (0x02U) //!< Bit mask for LLWU_F3_MWUF1.
+#define BS_LLWU_F3_MWUF1 (1U) //!< Bit field size in bits for LLWU_F3_MWUF1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F3_MWUF1 field.
+#define BR_LLWU_F3_MWUF1 (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF1))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F3, field MWUF2[2] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0 - Module 2 input was not a wakeup source
+ * - 1 - Module 2 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F3_MWUF2 (2U) //!< Bit position for LLWU_F3_MWUF2.
+#define BM_LLWU_F3_MWUF2 (0x04U) //!< Bit mask for LLWU_F3_MWUF2.
+#define BS_LLWU_F3_MWUF2 (1U) //!< Bit field size in bits for LLWU_F3_MWUF2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F3_MWUF2 field.
+#define BR_LLWU_F3_MWUF2 (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF2))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F3, field MWUF3[3] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0 - Module 3 input was not a wakeup source
+ * - 1 - Module 3 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F3_MWUF3 (3U) //!< Bit position for LLWU_F3_MWUF3.
+#define BM_LLWU_F3_MWUF3 (0x08U) //!< Bit mask for LLWU_F3_MWUF3.
+#define BS_LLWU_F3_MWUF3 (1U) //!< Bit field size in bits for LLWU_F3_MWUF3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F3_MWUF3 field.
+#define BR_LLWU_F3_MWUF3 (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF3))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F3, field MWUF4[4] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0 - Module 4 input was not a wakeup source
+ * - 1 - Module 4 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F3_MWUF4 (4U) //!< Bit position for LLWU_F3_MWUF4.
+#define BM_LLWU_F3_MWUF4 (0x10U) //!< Bit mask for LLWU_F3_MWUF4.
+#define BS_LLWU_F3_MWUF4 (1U) //!< Bit field size in bits for LLWU_F3_MWUF4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F3_MWUF4 field.
+#define BR_LLWU_F3_MWUF4 (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF4))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F3, field MWUF5[5] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0 - Module 5 input was not a wakeup source
+ * - 1 - Module 5 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F3_MWUF5 (5U) //!< Bit position for LLWU_F3_MWUF5.
+#define BM_LLWU_F3_MWUF5 (0x20U) //!< Bit mask for LLWU_F3_MWUF5.
+#define BS_LLWU_F3_MWUF5 (1U) //!< Bit field size in bits for LLWU_F3_MWUF5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F3_MWUF5 field.
+#define BR_LLWU_F3_MWUF5 (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF5))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F3, field MWUF6[6] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0 - Module 6 input was not a wakeup source
+ * - 1 - Module 6 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F3_MWUF6 (6U) //!< Bit position for LLWU_F3_MWUF6.
+#define BM_LLWU_F3_MWUF6 (0x40U) //!< Bit mask for LLWU_F3_MWUF6.
+#define BS_LLWU_F3_MWUF6 (1U) //!< Bit field size in bits for LLWU_F3_MWUF6.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F3_MWUF6 field.
+#define BR_LLWU_F3_MWUF6 (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF6))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_F3, field MWUF7[7] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0 - Module 7 input was not a wakeup source
+ * - 1 - Module 7 input was a wakeup source
+ */
+//@{
+#define BP_LLWU_F3_MWUF7 (7U) //!< Bit position for LLWU_F3_MWUF7.
+#define BM_LLWU_F3_MWUF7 (0x80U) //!< Bit mask for LLWU_F3_MWUF7.
+#define BS_LLWU_F3_MWUF7 (1U) //!< Bit field size in bits for LLWU_F3_MWUF7.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_F3_MWUF7 field.
+#define BR_LLWU_F3_MWUF7 (BITBAND_ACCESS8(HW_LLWU_F3_ADDR, BP_LLWU_F3_MWUF7))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LLWU_FILT1 - LLWU Pin Filter 1 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LLWU_FILT1 - LLWU Pin Filter 1 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_FILT1 is a control and status register that is used to enable/disable
+ * the digital filter 1 features for an external pin. This register is reset on
+ * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See
+ * the chip's reset chapter for more information. details for more information.
+ */
+typedef union _hw_llwu_filt1
+{
+ uint8_t U;
+ struct _hw_llwu_filt1_bitfields
+ {
+ uint8_t FILTSEL : 4; //!< [3:0] Filter Pin Select
+ uint8_t RESERVED0 : 1; //!< [4]
+ uint8_t FILTE : 2; //!< [6:5] Digital Filter On External Pin
+ uint8_t FILTF : 1; //!< [7] Filter Detect Flag
+ } B;
+} hw_llwu_filt1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LLWU_FILT1 register
+ */
+//@{
+#define HW_LLWU_FILT1_ADDR (REGS_LLWU_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LLWU_FILT1 (*(__IO hw_llwu_filt1_t *) HW_LLWU_FILT1_ADDR)
+#define HW_LLWU_FILT1_RD() (HW_LLWU_FILT1.U)
+#define HW_LLWU_FILT1_WR(v) (HW_LLWU_FILT1.U = (v))
+#define HW_LLWU_FILT1_SET(v) (HW_LLWU_FILT1_WR(HW_LLWU_FILT1_RD() | (v)))
+#define HW_LLWU_FILT1_CLR(v) (HW_LLWU_FILT1_WR(HW_LLWU_FILT1_RD() & ~(v)))
+#define HW_LLWU_FILT1_TOG(v) (HW_LLWU_FILT1_WR(HW_LLWU_FILT1_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LLWU_FILT1 bitfields
+ */
+
+/*!
+ * @name Register LLWU_FILT1, field FILTSEL[3:0] (RW)
+ *
+ * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
+ *
+ * Values:
+ * - 0000 - Select LLWU_P0 for filter
+ * - 1111 - Select LLWU_P15 for filter
+ */
+//@{
+#define BP_LLWU_FILT1_FILTSEL (0U) //!< Bit position for LLWU_FILT1_FILTSEL.
+#define BM_LLWU_FILT1_FILTSEL (0x0FU) //!< Bit mask for LLWU_FILT1_FILTSEL.
+#define BS_LLWU_FILT1_FILTSEL (4U) //!< Bit field size in bits for LLWU_FILT1_FILTSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_FILT1_FILTSEL field.
+#define BR_LLWU_FILT1_FILTSEL (HW_LLWU_FILT1.B.FILTSEL)
+#endif
+
+//! @brief Format value for bitfield LLWU_FILT1_FILTSEL.
+#define BF_LLWU_FILT1_FILTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_FILT1_FILTSEL), uint8_t) & BM_LLWU_FILT1_FILTSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FILTSEL field to a new value.
+#define BW_LLWU_FILT1_FILTSEL(v) (HW_LLWU_FILT1_WR((HW_LLWU_FILT1_RD() & ~BM_LLWU_FILT1_FILTSEL) | BF_LLWU_FILT1_FILTSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_FILT1, field FILTE[6:5] (RW)
+ *
+ * Controls the digital filter options for the external pin detect.
+ *
+ * Values:
+ * - 00 - Filter disabled
+ * - 01 - Filter posedge detect enabled
+ * - 10 - Filter negedge detect enabled
+ * - 11 - Filter any edge detect enabled
+ */
+//@{
+#define BP_LLWU_FILT1_FILTE (5U) //!< Bit position for LLWU_FILT1_FILTE.
+#define BM_LLWU_FILT1_FILTE (0x60U) //!< Bit mask for LLWU_FILT1_FILTE.
+#define BS_LLWU_FILT1_FILTE (2U) //!< Bit field size in bits for LLWU_FILT1_FILTE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_FILT1_FILTE field.
+#define BR_LLWU_FILT1_FILTE (HW_LLWU_FILT1.B.FILTE)
+#endif
+
+//! @brief Format value for bitfield LLWU_FILT1_FILTE.
+#define BF_LLWU_FILT1_FILTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_FILT1_FILTE), uint8_t) & BM_LLWU_FILT1_FILTE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FILTE field to a new value.
+#define BW_LLWU_FILT1_FILTE(v) (HW_LLWU_FILT1_WR((HW_LLWU_FILT1_RD() & ~BM_LLWU_FILT1_FILTE) | BF_LLWU_FILT1_FILTE(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_FILT1, field FILTF[7] (W1C)
+ *
+ * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
+ * source of exiting a low-leakage power mode. To clear the flag write a one to
+ * FILTF.
+ *
+ * Values:
+ * - 0 - Pin Filter 1 was not a wakeup source
+ * - 1 - Pin Filter 1 was a wakeup source
+ */
+//@{
+#define BP_LLWU_FILT1_FILTF (7U) //!< Bit position for LLWU_FILT1_FILTF.
+#define BM_LLWU_FILT1_FILTF (0x80U) //!< Bit mask for LLWU_FILT1_FILTF.
+#define BS_LLWU_FILT1_FILTF (1U) //!< Bit field size in bits for LLWU_FILT1_FILTF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_FILT1_FILTF field.
+#define BR_LLWU_FILT1_FILTF (BITBAND_ACCESS8(HW_LLWU_FILT1_ADDR, BP_LLWU_FILT1_FILTF))
+#endif
+
+//! @brief Format value for bitfield LLWU_FILT1_FILTF.
+#define BF_LLWU_FILT1_FILTF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_FILT1_FILTF), uint8_t) & BM_LLWU_FILT1_FILTF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FILTF field to a new value.
+#define BW_LLWU_FILT1_FILTF(v) (BITBAND_ACCESS8(HW_LLWU_FILT1_ADDR, BP_LLWU_FILT1_FILTF) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LLWU_FILT2 - LLWU Pin Filter 2 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LLWU_FILT2 - LLWU Pin Filter 2 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_FILT2 is a control and status register that is used to enable/disable
+ * the digital filter 2 features for an external pin. This register is reset on
+ * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See
+ * the chip's reset chapter for more information. details for more information.
+ */
+typedef union _hw_llwu_filt2
+{
+ uint8_t U;
+ struct _hw_llwu_filt2_bitfields
+ {
+ uint8_t FILTSEL : 4; //!< [3:0] Filter Pin Select
+ uint8_t RESERVED0 : 1; //!< [4]
+ uint8_t FILTE : 2; //!< [6:5] Digital Filter On External Pin
+ uint8_t FILTF : 1; //!< [7] Filter Detect Flag
+ } B;
+} hw_llwu_filt2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LLWU_FILT2 register
+ */
+//@{
+#define HW_LLWU_FILT2_ADDR (REGS_LLWU_BASE + 0x9U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LLWU_FILT2 (*(__IO hw_llwu_filt2_t *) HW_LLWU_FILT2_ADDR)
+#define HW_LLWU_FILT2_RD() (HW_LLWU_FILT2.U)
+#define HW_LLWU_FILT2_WR(v) (HW_LLWU_FILT2.U = (v))
+#define HW_LLWU_FILT2_SET(v) (HW_LLWU_FILT2_WR(HW_LLWU_FILT2_RD() | (v)))
+#define HW_LLWU_FILT2_CLR(v) (HW_LLWU_FILT2_WR(HW_LLWU_FILT2_RD() & ~(v)))
+#define HW_LLWU_FILT2_TOG(v) (HW_LLWU_FILT2_WR(HW_LLWU_FILT2_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LLWU_FILT2 bitfields
+ */
+
+/*!
+ * @name Register LLWU_FILT2, field FILTSEL[3:0] (RW)
+ *
+ * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
+ *
+ * Values:
+ * - 0000 - Select LLWU_P0 for filter
+ * - 1111 - Select LLWU_P15 for filter
+ */
+//@{
+#define BP_LLWU_FILT2_FILTSEL (0U) //!< Bit position for LLWU_FILT2_FILTSEL.
+#define BM_LLWU_FILT2_FILTSEL (0x0FU) //!< Bit mask for LLWU_FILT2_FILTSEL.
+#define BS_LLWU_FILT2_FILTSEL (4U) //!< Bit field size in bits for LLWU_FILT2_FILTSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_FILT2_FILTSEL field.
+#define BR_LLWU_FILT2_FILTSEL (HW_LLWU_FILT2.B.FILTSEL)
+#endif
+
+//! @brief Format value for bitfield LLWU_FILT2_FILTSEL.
+#define BF_LLWU_FILT2_FILTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_FILT2_FILTSEL), uint8_t) & BM_LLWU_FILT2_FILTSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FILTSEL field to a new value.
+#define BW_LLWU_FILT2_FILTSEL(v) (HW_LLWU_FILT2_WR((HW_LLWU_FILT2_RD() & ~BM_LLWU_FILT2_FILTSEL) | BF_LLWU_FILT2_FILTSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_FILT2, field FILTE[6:5] (RW)
+ *
+ * Controls the digital filter options for the external pin detect.
+ *
+ * Values:
+ * - 00 - Filter disabled
+ * - 01 - Filter posedge detect enabled
+ * - 10 - Filter negedge detect enabled
+ * - 11 - Filter any edge detect enabled
+ */
+//@{
+#define BP_LLWU_FILT2_FILTE (5U) //!< Bit position for LLWU_FILT2_FILTE.
+#define BM_LLWU_FILT2_FILTE (0x60U) //!< Bit mask for LLWU_FILT2_FILTE.
+#define BS_LLWU_FILT2_FILTE (2U) //!< Bit field size in bits for LLWU_FILT2_FILTE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_FILT2_FILTE field.
+#define BR_LLWU_FILT2_FILTE (HW_LLWU_FILT2.B.FILTE)
+#endif
+
+//! @brief Format value for bitfield LLWU_FILT2_FILTE.
+#define BF_LLWU_FILT2_FILTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_FILT2_FILTE), uint8_t) & BM_LLWU_FILT2_FILTE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FILTE field to a new value.
+#define BW_LLWU_FILT2_FILTE(v) (HW_LLWU_FILT2_WR((HW_LLWU_FILT2_RD() & ~BM_LLWU_FILT2_FILTE) | BF_LLWU_FILT2_FILTE(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_FILT2, field FILTF[7] (W1C)
+ *
+ * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
+ * source of exiting a low-leakage power mode. To clear the flag write a one to
+ * FILTF.
+ *
+ * Values:
+ * - 0 - Pin Filter 2 was not a wakeup source
+ * - 1 - Pin Filter 2 was a wakeup source
+ */
+//@{
+#define BP_LLWU_FILT2_FILTF (7U) //!< Bit position for LLWU_FILT2_FILTF.
+#define BM_LLWU_FILT2_FILTF (0x80U) //!< Bit mask for LLWU_FILT2_FILTF.
+#define BS_LLWU_FILT2_FILTF (1U) //!< Bit field size in bits for LLWU_FILT2_FILTF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_FILT2_FILTF field.
+#define BR_LLWU_FILT2_FILTF (BITBAND_ACCESS8(HW_LLWU_FILT2_ADDR, BP_LLWU_FILT2_FILTF))
+#endif
+
+//! @brief Format value for bitfield LLWU_FILT2_FILTF.
+#define BF_LLWU_FILT2_FILTF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_FILT2_FILTF), uint8_t) & BM_LLWU_FILT2_FILTF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FILTF field to a new value.
+#define BW_LLWU_FILT2_FILTF(v) (BITBAND_ACCESS8(HW_LLWU_FILT2_ADDR, BP_LLWU_FILT2_FILTF) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LLWU_RST - LLWU Reset Enable register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LLWU_RST - LLWU Reset Enable register (RW)
+ *
+ * Reset value: 0x02U
+ *
+ * LLWU_RST is a control register that is used to enable/disable the digital
+ * filter for the external pin detect and RESET pin. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+typedef union _hw_llwu_rst
+{
+ uint8_t U;
+ struct _hw_llwu_rst_bitfields
+ {
+ uint8_t RSTFILT : 1; //!< [0] Digital Filter On RESET Pin
+ uint8_t LLRSTE : 1; //!< [1] Low-Leakage Mode RESET Enable
+ uint8_t RESERVED0 : 6; //!< [7:2]
+ } B;
+} hw_llwu_rst_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LLWU_RST register
+ */
+//@{
+#define HW_LLWU_RST_ADDR (REGS_LLWU_BASE + 0xAU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LLWU_RST (*(__IO hw_llwu_rst_t *) HW_LLWU_RST_ADDR)
+#define HW_LLWU_RST_RD() (HW_LLWU_RST.U)
+#define HW_LLWU_RST_WR(v) (HW_LLWU_RST.U = (v))
+#define HW_LLWU_RST_SET(v) (HW_LLWU_RST_WR(HW_LLWU_RST_RD() | (v)))
+#define HW_LLWU_RST_CLR(v) (HW_LLWU_RST_WR(HW_LLWU_RST_RD() & ~(v)))
+#define HW_LLWU_RST_TOG(v) (HW_LLWU_RST_WR(HW_LLWU_RST_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LLWU_RST bitfields
+ */
+
+/*!
+ * @name Register LLWU_RST, field RSTFILT[0] (RW)
+ *
+ * Enables the digital filter for the RESET pin during LLS, VLLS3, VLLS2, or
+ * VLLS1 modes.
+ *
+ * Values:
+ * - 0 - Filter not enabled
+ * - 1 - Filter enabled
+ */
+//@{
+#define BP_LLWU_RST_RSTFILT (0U) //!< Bit position for LLWU_RST_RSTFILT.
+#define BM_LLWU_RST_RSTFILT (0x01U) //!< Bit mask for LLWU_RST_RSTFILT.
+#define BS_LLWU_RST_RSTFILT (1U) //!< Bit field size in bits for LLWU_RST_RSTFILT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_RST_RSTFILT field.
+#define BR_LLWU_RST_RSTFILT (BITBAND_ACCESS8(HW_LLWU_RST_ADDR, BP_LLWU_RST_RSTFILT))
+#endif
+
+//! @brief Format value for bitfield LLWU_RST_RSTFILT.
+#define BF_LLWU_RST_RSTFILT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_RST_RSTFILT), uint8_t) & BM_LLWU_RST_RSTFILT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RSTFILT field to a new value.
+#define BW_LLWU_RST_RSTFILT(v) (BITBAND_ACCESS8(HW_LLWU_RST_ADDR, BP_LLWU_RST_RSTFILT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LLWU_RST, field LLRSTE[1] (RW)
+ *
+ * This bit must be set to allow the device to be reset while in a low-leakage
+ * power mode. On devices where Reset is not a dedicated pin, the RESET pin must
+ * also be enabled in the explicit port mux control.
+ *
+ * Values:
+ * - 0 - RESET pin not enabled as a leakage mode exit source
+ * - 1 - RESET pin enabled as a low leakage mode exit source
+ */
+//@{
+#define BP_LLWU_RST_LLRSTE (1U) //!< Bit position for LLWU_RST_LLRSTE.
+#define BM_LLWU_RST_LLRSTE (0x02U) //!< Bit mask for LLWU_RST_LLRSTE.
+#define BS_LLWU_RST_LLRSTE (1U) //!< Bit field size in bits for LLWU_RST_LLRSTE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LLWU_RST_LLRSTE field.
+#define BR_LLWU_RST_LLRSTE (BITBAND_ACCESS8(HW_LLWU_RST_ADDR, BP_LLWU_RST_LLRSTE))
+#endif
+
+//! @brief Format value for bitfield LLWU_RST_LLRSTE.
+#define BF_LLWU_RST_LLRSTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_LLWU_RST_LLRSTE), uint8_t) & BM_LLWU_RST_LLRSTE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LLRSTE field to a new value.
+#define BW_LLWU_RST_LLRSTE(v) (BITBAND_ACCESS8(HW_LLWU_RST_ADDR, BP_LLWU_RST_LLRSTE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_llwu_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All LLWU module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_llwu
+{
+ __IO hw_llwu_pe1_t PE1; //!< [0x0] LLWU Pin Enable 1 register
+ __IO hw_llwu_pe2_t PE2; //!< [0x1] LLWU Pin Enable 2 register
+ __IO hw_llwu_pe3_t PE3; //!< [0x2] LLWU Pin Enable 3 register
+ __IO hw_llwu_pe4_t PE4; //!< [0x3] LLWU Pin Enable 4 register
+ __IO hw_llwu_me_t ME; //!< [0x4] LLWU Module Enable register
+ __IO hw_llwu_f1_t F1; //!< [0x5] LLWU Flag 1 register
+ __IO hw_llwu_f2_t F2; //!< [0x6] LLWU Flag 2 register
+ __I hw_llwu_f3_t F3; //!< [0x7] LLWU Flag 3 register
+ __IO hw_llwu_filt1_t FILT1; //!< [0x8] LLWU Pin Filter 1 register
+ __IO hw_llwu_filt2_t FILT2; //!< [0x9] LLWU Pin Filter 2 register
+ __IO hw_llwu_rst_t RST; //!< [0xA] LLWU Reset Enable register
+} hw_llwu_t;
+#pragma pack()
+
+//! @brief Macro to access all LLWU registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_LLWU</code>.
+#define HW_LLWU (*(hw_llwu_t *) REGS_LLWU_BASE)
+#endif
+
+#endif // __HW_LLWU_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_lptmr.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,629 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_LPTMR_REGISTERS_H__
+#define __HW_LPTMR_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 LPTMR
+ *
+ * Low Power Timer
+ *
+ * Registers defined in this header file:
+ * - HW_LPTMR_CSR - Low Power Timer Control Status Register
+ * - HW_LPTMR_PSR - Low Power Timer Prescale Register
+ * - HW_LPTMR_CMR - Low Power Timer Compare Register
+ * - HW_LPTMR_CNR - Low Power Timer Counter Register
+ *
+ * - hw_lptmr_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_LPTMR_BASE
+#define HW_LPTMR_INSTANCE_COUNT (1U) //!< Number of instances of the LPTMR module.
+#define REGS_LPTMR_BASE (0x40040000U) //!< Base address for LPTMR0.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LPTMR_CSR - Low Power Timer Control Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LPTMR_CSR - Low Power Timer Control Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_lptmr_csr
+{
+ uint32_t U;
+ struct _hw_lptmr_csr_bitfields
+ {
+ uint32_t TEN : 1; //!< [0] Timer Enable
+ uint32_t TMS : 1; //!< [1] Timer Mode Select
+ uint32_t TFC : 1; //!< [2] Timer Free-Running Counter
+ uint32_t TPP : 1; //!< [3] Timer Pin Polarity
+ uint32_t TPS : 2; //!< [5:4] Timer Pin Select
+ uint32_t TIE : 1; //!< [6] Timer Interrupt Enable
+ uint32_t TCF : 1; //!< [7] Timer Compare Flag
+ uint32_t RESERVED0 : 24; //!< [31:8]
+ } B;
+} hw_lptmr_csr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LPTMR_CSR register
+ */
+//@{
+#define HW_LPTMR_CSR_ADDR (REGS_LPTMR_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LPTMR_CSR (*(__IO hw_lptmr_csr_t *) HW_LPTMR_CSR_ADDR)
+#define HW_LPTMR_CSR_RD() (HW_LPTMR_CSR.U)
+#define HW_LPTMR_CSR_WR(v) (HW_LPTMR_CSR.U = (v))
+#define HW_LPTMR_CSR_SET(v) (HW_LPTMR_CSR_WR(HW_LPTMR_CSR_RD() | (v)))
+#define HW_LPTMR_CSR_CLR(v) (HW_LPTMR_CSR_WR(HW_LPTMR_CSR_RD() & ~(v)))
+#define HW_LPTMR_CSR_TOG(v) (HW_LPTMR_CSR_WR(HW_LPTMR_CSR_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LPTMR_CSR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_CSR, field TEN[0] (RW)
+ *
+ * When TEN is clear, it resets the LPTMR internal logic, including the CNR and
+ * TCF. When TEN is set, the LPTMR is enabled. While writing 1 to this field,
+ * CSR[5:1] must not be altered.
+ *
+ * Values:
+ * - 0 - LPTMR is disabled and internal logic is reset.
+ * - 1 - LPTMR is enabled.
+ */
+//@{
+#define BP_LPTMR_CSR_TEN (0U) //!< Bit position for LPTMR_CSR_TEN.
+#define BM_LPTMR_CSR_TEN (0x00000001U) //!< Bit mask for LPTMR_CSR_TEN.
+#define BS_LPTMR_CSR_TEN (1U) //!< Bit field size in bits for LPTMR_CSR_TEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LPTMR_CSR_TEN field.
+#define BR_LPTMR_CSR_TEN (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TEN))
+#endif
+
+//! @brief Format value for bitfield LPTMR_CSR_TEN.
+#define BF_LPTMR_CSR_TEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TEN), uint32_t) & BM_LPTMR_CSR_TEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TEN field to a new value.
+#define BW_LPTMR_CSR_TEN(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LPTMR_CSR, field TMS[1] (RW)
+ *
+ * Configures the mode of the LPTMR. TMS must be altered only when the LPTMR is
+ * disabled.
+ *
+ * Values:
+ * - 0 - Time Counter mode.
+ * - 1 - Pulse Counter mode.
+ */
+//@{
+#define BP_LPTMR_CSR_TMS (1U) //!< Bit position for LPTMR_CSR_TMS.
+#define BM_LPTMR_CSR_TMS (0x00000002U) //!< Bit mask for LPTMR_CSR_TMS.
+#define BS_LPTMR_CSR_TMS (1U) //!< Bit field size in bits for LPTMR_CSR_TMS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LPTMR_CSR_TMS field.
+#define BR_LPTMR_CSR_TMS (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TMS))
+#endif
+
+//! @brief Format value for bitfield LPTMR_CSR_TMS.
+#define BF_LPTMR_CSR_TMS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TMS), uint32_t) & BM_LPTMR_CSR_TMS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TMS field to a new value.
+#define BW_LPTMR_CSR_TMS(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TMS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LPTMR_CSR, field TFC[2] (RW)
+ *
+ * When clear, TFC configures the CNR to reset whenever TCF is set. When set,
+ * TFC configures the CNR to reset on overflow. TFC must be altered only when the
+ * LPTMR is disabled.
+ *
+ * Values:
+ * - 0 - CNR is reset whenever TCF is set.
+ * - 1 - CNR is reset on overflow.
+ */
+//@{
+#define BP_LPTMR_CSR_TFC (2U) //!< Bit position for LPTMR_CSR_TFC.
+#define BM_LPTMR_CSR_TFC (0x00000004U) //!< Bit mask for LPTMR_CSR_TFC.
+#define BS_LPTMR_CSR_TFC (1U) //!< Bit field size in bits for LPTMR_CSR_TFC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LPTMR_CSR_TFC field.
+#define BR_LPTMR_CSR_TFC (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TFC))
+#endif
+
+//! @brief Format value for bitfield LPTMR_CSR_TFC.
+#define BF_LPTMR_CSR_TFC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TFC), uint32_t) & BM_LPTMR_CSR_TFC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TFC field to a new value.
+#define BW_LPTMR_CSR_TFC(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TFC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LPTMR_CSR, field TPP[3] (RW)
+ *
+ * Configures the polarity of the input source in Pulse Counter mode. TPP must
+ * be changed only when the LPTMR is disabled.
+ *
+ * Values:
+ * - 0 - Pulse Counter input source is active-high, and the CNR will increment
+ * on the rising-edge.
+ * - 1 - Pulse Counter input source is active-low, and the CNR will increment on
+ * the falling-edge.
+ */
+//@{
+#define BP_LPTMR_CSR_TPP (3U) //!< Bit position for LPTMR_CSR_TPP.
+#define BM_LPTMR_CSR_TPP (0x00000008U) //!< Bit mask for LPTMR_CSR_TPP.
+#define BS_LPTMR_CSR_TPP (1U) //!< Bit field size in bits for LPTMR_CSR_TPP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LPTMR_CSR_TPP field.
+#define BR_LPTMR_CSR_TPP (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TPP))
+#endif
+
+//! @brief Format value for bitfield LPTMR_CSR_TPP.
+#define BF_LPTMR_CSR_TPP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TPP), uint32_t) & BM_LPTMR_CSR_TPP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TPP field to a new value.
+#define BW_LPTMR_CSR_TPP(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TPP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LPTMR_CSR, field TPS[5:4] (RW)
+ *
+ * Configures the input source to be used in Pulse Counter mode. TPS must be
+ * altered only when the LPTMR is disabled. The input connections vary by device.
+ * See the chip configuration details for information on the connections to these
+ * inputs.
+ *
+ * Values:
+ * - 00 - Pulse counter input 0 is selected.
+ * - 01 - Pulse counter input 1 is selected.
+ * - 10 - Pulse counter input 2 is selected.
+ * - 11 - Pulse counter input 3 is selected.
+ */
+//@{
+#define BP_LPTMR_CSR_TPS (4U) //!< Bit position for LPTMR_CSR_TPS.
+#define BM_LPTMR_CSR_TPS (0x00000030U) //!< Bit mask for LPTMR_CSR_TPS.
+#define BS_LPTMR_CSR_TPS (2U) //!< Bit field size in bits for LPTMR_CSR_TPS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LPTMR_CSR_TPS field.
+#define BR_LPTMR_CSR_TPS (HW_LPTMR_CSR.B.TPS)
+#endif
+
+//! @brief Format value for bitfield LPTMR_CSR_TPS.
+#define BF_LPTMR_CSR_TPS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TPS), uint32_t) & BM_LPTMR_CSR_TPS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TPS field to a new value.
+#define BW_LPTMR_CSR_TPS(v) (HW_LPTMR_CSR_WR((HW_LPTMR_CSR_RD() & ~BM_LPTMR_CSR_TPS) | BF_LPTMR_CSR_TPS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LPTMR_CSR, field TIE[6] (RW)
+ *
+ * When TIE is set, the LPTMR Interrupt is generated whenever TCF is also set.
+ *
+ * Values:
+ * - 0 - Timer interrupt disabled.
+ * - 1 - Timer interrupt enabled.
+ */
+//@{
+#define BP_LPTMR_CSR_TIE (6U) //!< Bit position for LPTMR_CSR_TIE.
+#define BM_LPTMR_CSR_TIE (0x00000040U) //!< Bit mask for LPTMR_CSR_TIE.
+#define BS_LPTMR_CSR_TIE (1U) //!< Bit field size in bits for LPTMR_CSR_TIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LPTMR_CSR_TIE field.
+#define BR_LPTMR_CSR_TIE (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TIE))
+#endif
+
+//! @brief Format value for bitfield LPTMR_CSR_TIE.
+#define BF_LPTMR_CSR_TIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TIE), uint32_t) & BM_LPTMR_CSR_TIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TIE field to a new value.
+#define BW_LPTMR_CSR_TIE(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LPTMR_CSR, field TCF[7] (W1C)
+ *
+ * TCF is set when the LPTMR is enabled and the CNR equals the CMR and
+ * increments. TCF is cleared when the LPTMR is disabled or a logic 1 is written to it.
+ *
+ * Values:
+ * - 0 - The value of CNR is not equal to CMR and increments.
+ * - 1 - The value of CNR is equal to CMR and increments.
+ */
+//@{
+#define BP_LPTMR_CSR_TCF (7U) //!< Bit position for LPTMR_CSR_TCF.
+#define BM_LPTMR_CSR_TCF (0x00000080U) //!< Bit mask for LPTMR_CSR_TCF.
+#define BS_LPTMR_CSR_TCF (1U) //!< Bit field size in bits for LPTMR_CSR_TCF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LPTMR_CSR_TCF field.
+#define BR_LPTMR_CSR_TCF (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TCF))
+#endif
+
+//! @brief Format value for bitfield LPTMR_CSR_TCF.
+#define BF_LPTMR_CSR_TCF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CSR_TCF), uint32_t) & BM_LPTMR_CSR_TCF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCF field to a new value.
+#define BW_LPTMR_CSR_TCF(v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR, BP_LPTMR_CSR_TCF) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LPTMR_PSR - Low Power Timer Prescale Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LPTMR_PSR - Low Power Timer Prescale Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_lptmr_psr
+{
+ uint32_t U;
+ struct _hw_lptmr_psr_bitfields
+ {
+ uint32_t PCS : 2; //!< [1:0] Prescaler Clock Select
+ uint32_t PBYP : 1; //!< [2] Prescaler Bypass
+ uint32_t PRESCALE : 4; //!< [6:3] Prescale Value
+ uint32_t RESERVED0 : 25; //!< [31:7]
+ } B;
+} hw_lptmr_psr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LPTMR_PSR register
+ */
+//@{
+#define HW_LPTMR_PSR_ADDR (REGS_LPTMR_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LPTMR_PSR (*(__IO hw_lptmr_psr_t *) HW_LPTMR_PSR_ADDR)
+#define HW_LPTMR_PSR_RD() (HW_LPTMR_PSR.U)
+#define HW_LPTMR_PSR_WR(v) (HW_LPTMR_PSR.U = (v))
+#define HW_LPTMR_PSR_SET(v) (HW_LPTMR_PSR_WR(HW_LPTMR_PSR_RD() | (v)))
+#define HW_LPTMR_PSR_CLR(v) (HW_LPTMR_PSR_WR(HW_LPTMR_PSR_RD() & ~(v)))
+#define HW_LPTMR_PSR_TOG(v) (HW_LPTMR_PSR_WR(HW_LPTMR_PSR_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LPTMR_PSR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_PSR, field PCS[1:0] (RW)
+ *
+ * Selects the clock to be used by the LPTMR prescaler/glitch filter. PCS must
+ * be altered only when the LPTMR is disabled. The clock connections vary by
+ * device. See the chip configuration details for information on the connections to
+ * these inputs.
+ *
+ * Values:
+ * - 00 - Prescaler/glitch filter clock 0 selected.
+ * - 01 - Prescaler/glitch filter clock 1 selected.
+ * - 10 - Prescaler/glitch filter clock 2 selected.
+ * - 11 - Prescaler/glitch filter clock 3 selected.
+ */
+//@{
+#define BP_LPTMR_PSR_PCS (0U) //!< Bit position for LPTMR_PSR_PCS.
+#define BM_LPTMR_PSR_PCS (0x00000003U) //!< Bit mask for LPTMR_PSR_PCS.
+#define BS_LPTMR_PSR_PCS (2U) //!< Bit field size in bits for LPTMR_PSR_PCS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LPTMR_PSR_PCS field.
+#define BR_LPTMR_PSR_PCS (HW_LPTMR_PSR.B.PCS)
+#endif
+
+//! @brief Format value for bitfield LPTMR_PSR_PCS.
+#define BF_LPTMR_PSR_PCS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_PSR_PCS), uint32_t) & BM_LPTMR_PSR_PCS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PCS field to a new value.
+#define BW_LPTMR_PSR_PCS(v) (HW_LPTMR_PSR_WR((HW_LPTMR_PSR_RD() & ~BM_LPTMR_PSR_PCS) | BF_LPTMR_PSR_PCS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register LPTMR_PSR, field PBYP[2] (RW)
+ *
+ * When PBYP is set, the selected prescaler clock in Time Counter mode or
+ * selected input source in Pulse Counter mode directly clocks the CNR. When PBYP is
+ * clear, the CNR is clocked by the output of the prescaler/glitch filter. PBYP
+ * must be altered only when the LPTMR is disabled.
+ *
+ * Values:
+ * - 0 - Prescaler/glitch filter is enabled.
+ * - 1 - Prescaler/glitch filter is bypassed.
+ */
+//@{
+#define BP_LPTMR_PSR_PBYP (2U) //!< Bit position for LPTMR_PSR_PBYP.
+#define BM_LPTMR_PSR_PBYP (0x00000004U) //!< Bit mask for LPTMR_PSR_PBYP.
+#define BS_LPTMR_PSR_PBYP (1U) //!< Bit field size in bits for LPTMR_PSR_PBYP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LPTMR_PSR_PBYP field.
+#define BR_LPTMR_PSR_PBYP (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR, BP_LPTMR_PSR_PBYP))
+#endif
+
+//! @brief Format value for bitfield LPTMR_PSR_PBYP.
+#define BF_LPTMR_PSR_PBYP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_PSR_PBYP), uint32_t) & BM_LPTMR_PSR_PBYP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PBYP field to a new value.
+#define BW_LPTMR_PSR_PBYP(v) (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR, BP_LPTMR_PSR_PBYP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register LPTMR_PSR, field PRESCALE[6:3] (RW)
+ *
+ * Configures the size of the Prescaler in Time Counter mode or width of the
+ * glitch filter in Pulse Counter mode. PRESCALE must be altered only when the LPTMR
+ * is disabled.
+ *
+ * Values:
+ * - 0000 - Prescaler divides the prescaler clock by 2; glitch filter does not
+ * support this configuration.
+ * - 0001 - Prescaler divides the prescaler clock by 4; glitch filter recognizes
+ * change on input pin after 2 rising clock edges.
+ * - 0010 - Prescaler divides the prescaler clock by 8; glitch filter recognizes
+ * change on input pin after 4 rising clock edges.
+ * - 0011 - Prescaler divides the prescaler clock by 16; glitch filter
+ * recognizes change on input pin after 8 rising clock edges.
+ * - 0100 - Prescaler divides the prescaler clock by 32; glitch filter
+ * recognizes change on input pin after 16 rising clock edges.
+ * - 0101 - Prescaler divides the prescaler clock by 64; glitch filter
+ * recognizes change on input pin after 32 rising clock edges.
+ * - 0110 - Prescaler divides the prescaler clock by 128; glitch filter
+ * recognizes change on input pin after 64 rising clock edges.
+ * - 0111 - Prescaler divides the prescaler clock by 256; glitch filter
+ * recognizes change on input pin after 128 rising clock edges.
+ * - 1000 - Prescaler divides the prescaler clock by 512; glitch filter
+ * recognizes change on input pin after 256 rising clock edges.
+ * - 1001 - Prescaler divides the prescaler clock by 1024; glitch filter
+ * recognizes change on input pin after 512 rising clock edges.
+ * - 1010 - Prescaler divides the prescaler clock by 2048; glitch filter
+ * recognizes change on input pin after 1024 rising clock edges.
+ * - 1011 - Prescaler divides the prescaler clock by 4096; glitch filter
+ * recognizes change on input pin after 2048 rising clock edges.
+ * - 1100 - Prescaler divides the prescaler clock by 8192; glitch filter
+ * recognizes change on input pin after 4096 rising clock edges.
+ * - 1101 - Prescaler divides the prescaler clock by 16,384; glitch filter
+ * recognizes change on input pin after 8192 rising clock edges.
+ * - 1110 - Prescaler divides the prescaler clock by 32,768; glitch filter
+ * recognizes change on input pin after 16,384 rising clock edges.
+ * - 1111 - Prescaler divides the prescaler clock by 65,536; glitch filter
+ * recognizes change on input pin after 32,768 rising clock edges.
+ */
+//@{
+#define BP_LPTMR_PSR_PRESCALE (3U) //!< Bit position for LPTMR_PSR_PRESCALE.
+#define BM_LPTMR_PSR_PRESCALE (0x00000078U) //!< Bit mask for LPTMR_PSR_PRESCALE.
+#define BS_LPTMR_PSR_PRESCALE (4U) //!< Bit field size in bits for LPTMR_PSR_PRESCALE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LPTMR_PSR_PRESCALE field.
+#define BR_LPTMR_PSR_PRESCALE (HW_LPTMR_PSR.B.PRESCALE)
+#endif
+
+//! @brief Format value for bitfield LPTMR_PSR_PRESCALE.
+#define BF_LPTMR_PSR_PRESCALE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_PSR_PRESCALE), uint32_t) & BM_LPTMR_PSR_PRESCALE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PRESCALE field to a new value.
+#define BW_LPTMR_PSR_PRESCALE(v) (HW_LPTMR_PSR_WR((HW_LPTMR_PSR_RD() & ~BM_LPTMR_PSR_PRESCALE) | BF_LPTMR_PSR_PRESCALE(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LPTMR_CMR - Low Power Timer Compare Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LPTMR_CMR - Low Power Timer Compare Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_lptmr_cmr
+{
+ uint32_t U;
+ struct _hw_lptmr_cmr_bitfields
+ {
+ uint32_t COMPARE : 16; //!< [15:0] Compare Value
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_lptmr_cmr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LPTMR_CMR register
+ */
+//@{
+#define HW_LPTMR_CMR_ADDR (REGS_LPTMR_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LPTMR_CMR (*(__IO hw_lptmr_cmr_t *) HW_LPTMR_CMR_ADDR)
+#define HW_LPTMR_CMR_RD() (HW_LPTMR_CMR.U)
+#define HW_LPTMR_CMR_WR(v) (HW_LPTMR_CMR.U = (v))
+#define HW_LPTMR_CMR_SET(v) (HW_LPTMR_CMR_WR(HW_LPTMR_CMR_RD() | (v)))
+#define HW_LPTMR_CMR_CLR(v) (HW_LPTMR_CMR_WR(HW_LPTMR_CMR_RD() & ~(v)))
+#define HW_LPTMR_CMR_TOG(v) (HW_LPTMR_CMR_WR(HW_LPTMR_CMR_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LPTMR_CMR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_CMR, field COMPARE[15:0] (RW)
+ *
+ * When the LPTMR is enabled and the CNR equals the value in the CMR and
+ * increments, TCF is set and the hardware trigger asserts until the next time the CNR
+ * increments. If the CMR is 0, the hardware trigger will remain asserted until
+ * the LPTMR is disabled. If the LPTMR is enabled, the CMR must be altered only
+ * when TCF is set.
+ */
+//@{
+#define BP_LPTMR_CMR_COMPARE (0U) //!< Bit position for LPTMR_CMR_COMPARE.
+#define BM_LPTMR_CMR_COMPARE (0x0000FFFFU) //!< Bit mask for LPTMR_CMR_COMPARE.
+#define BS_LPTMR_CMR_COMPARE (16U) //!< Bit field size in bits for LPTMR_CMR_COMPARE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LPTMR_CMR_COMPARE field.
+#define BR_LPTMR_CMR_COMPARE (HW_LPTMR_CMR.B.COMPARE)
+#endif
+
+//! @brief Format value for bitfield LPTMR_CMR_COMPARE.
+#define BF_LPTMR_CMR_COMPARE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CMR_COMPARE), uint32_t) & BM_LPTMR_CMR_COMPARE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COMPARE field to a new value.
+#define BW_LPTMR_CMR_COMPARE(v) (HW_LPTMR_CMR_WR((HW_LPTMR_CMR_RD() & ~BM_LPTMR_CMR_COMPARE) | BF_LPTMR_CMR_COMPARE(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_LPTMR_CNR - Low Power Timer Counter Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_LPTMR_CNR - Low Power Timer Counter Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_lptmr_cnr
+{
+ uint32_t U;
+ struct _hw_lptmr_cnr_bitfields
+ {
+ uint32_t COUNTER : 16; //!< [15:0] Counter Value
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_lptmr_cnr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire LPTMR_CNR register
+ */
+//@{
+#define HW_LPTMR_CNR_ADDR (REGS_LPTMR_BASE + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_LPTMR_CNR (*(__IO hw_lptmr_cnr_t *) HW_LPTMR_CNR_ADDR)
+#define HW_LPTMR_CNR_RD() (HW_LPTMR_CNR.U)
+#define HW_LPTMR_CNR_WR(v) (HW_LPTMR_CNR.U = (v))
+#define HW_LPTMR_CNR_SET(v) (HW_LPTMR_CNR_WR(HW_LPTMR_CNR_RD() | (v)))
+#define HW_LPTMR_CNR_CLR(v) (HW_LPTMR_CNR_WR(HW_LPTMR_CNR_RD() & ~(v)))
+#define HW_LPTMR_CNR_TOG(v) (HW_LPTMR_CNR_WR(HW_LPTMR_CNR_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual LPTMR_CNR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_CNR, field COUNTER[15:0] (RW)
+ */
+//@{
+#define BP_LPTMR_CNR_COUNTER (0U) //!< Bit position for LPTMR_CNR_COUNTER.
+#define BM_LPTMR_CNR_COUNTER (0x0000FFFFU) //!< Bit mask for LPTMR_CNR_COUNTER.
+#define BS_LPTMR_CNR_COUNTER (16U) //!< Bit field size in bits for LPTMR_CNR_COUNTER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the LPTMR_CNR_COUNTER field.
+#define BR_LPTMR_CNR_COUNTER (HW_LPTMR_CNR.B.COUNTER)
+#endif
+
+//! @brief Format value for bitfield LPTMR_CNR_COUNTER.
+#define BF_LPTMR_CNR_COUNTER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_LPTMR_CNR_COUNTER), uint32_t) & BM_LPTMR_CNR_COUNTER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COUNTER field to a new value.
+#define BW_LPTMR_CNR_COUNTER(v) (HW_LPTMR_CNR_WR((HW_LPTMR_CNR_RD() & ~BM_LPTMR_CNR_COUNTER) | BF_LPTMR_CNR_COUNTER(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_lptmr_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All LPTMR module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_lptmr
+{
+ __IO hw_lptmr_csr_t CSR; //!< [0x0] Low Power Timer Control Status Register
+ __IO hw_lptmr_psr_t PSR; //!< [0x4] Low Power Timer Prescale Register
+ __IO hw_lptmr_cmr_t CMR; //!< [0x8] Low Power Timer Compare Register
+ __IO hw_lptmr_cnr_t CNR; //!< [0xC] Low Power Timer Counter Register
+} hw_lptmr_t;
+#pragma pack()
+
+//! @brief Macro to access all LPTMR registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_LPTMR</code>.
+#define HW_LPTMR (*(hw_lptmr_t *) REGS_LPTMR_BASE)
+#endif
+
+#endif // __HW_LPTMR_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_mcg.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,1939 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_MCG_REGISTERS_H__
+#define __HW_MCG_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 MCG
+ *
+ * Multipurpose Clock Generator module
+ *
+ * Registers defined in this header file:
+ * - HW_MCG_C1 - MCG Control 1 Register
+ * - HW_MCG_C2 - MCG Control 2 Register
+ * - HW_MCG_C3 - MCG Control 3 Register
+ * - HW_MCG_C4 - MCG Control 4 Register
+ * - HW_MCG_C5 - MCG Control 5 Register
+ * - HW_MCG_C6 - MCG Control 6 Register
+ * - HW_MCG_S - MCG Status Register
+ * - HW_MCG_SC - MCG Status and Control Register
+ * - HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register
+ * - HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register
+ * - HW_MCG_C7 - MCG Control 7 Register
+ * - HW_MCG_C8 - MCG Control 8 Register
+ *
+ * - hw_mcg_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_MCG_BASE
+#define HW_MCG_INSTANCE_COUNT (1U) //!< Number of instances of the MCG module.
+#define REGS_MCG_BASE (0x40064000U) //!< Base address for MCG.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCG_C1 - MCG Control 1 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCG_C1 - MCG Control 1 Register (RW)
+ *
+ * Reset value: 0x04U
+ */
+typedef union _hw_mcg_c1
+{
+ uint8_t U;
+ struct _hw_mcg_c1_bitfields
+ {
+ uint8_t IREFSTEN : 1; //!< [0] Internal Reference Stop Enable
+ uint8_t IRCLKEN : 1; //!< [1] Internal Reference Clock Enable
+ uint8_t IREFS : 1; //!< [2] Internal Reference Select
+ uint8_t FRDIV : 3; //!< [5:3] FLL External Reference Divider
+ uint8_t CLKS : 2; //!< [7:6] Clock Source Select
+ } B;
+} hw_mcg_c1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCG_C1 register
+ */
+//@{
+#define HW_MCG_C1_ADDR (REGS_MCG_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCG_C1 (*(__IO hw_mcg_c1_t *) HW_MCG_C1_ADDR)
+#define HW_MCG_C1_RD() (HW_MCG_C1.U)
+#define HW_MCG_C1_WR(v) (HW_MCG_C1.U = (v))
+#define HW_MCG_C1_SET(v) (HW_MCG_C1_WR(HW_MCG_C1_RD() | (v)))
+#define HW_MCG_C1_CLR(v) (HW_MCG_C1_WR(HW_MCG_C1_RD() & ~(v)))
+#define HW_MCG_C1_TOG(v) (HW_MCG_C1_WR(HW_MCG_C1_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCG_C1 bitfields
+ */
+
+/*!
+ * @name Register MCG_C1, field IREFSTEN[0] (RW)
+ *
+ * Controls whether or not the internal reference clock remains enabled when the
+ * MCG enters Stop mode.
+ *
+ * Values:
+ * - 0 - Internal reference clock is disabled in Stop mode.
+ * - 1 - Internal reference clock is enabled in Stop mode if IRCLKEN is set or
+ * if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
+ */
+//@{
+#define BP_MCG_C1_IREFSTEN (0U) //!< Bit position for MCG_C1_IREFSTEN.
+#define BM_MCG_C1_IREFSTEN (0x01U) //!< Bit mask for MCG_C1_IREFSTEN.
+#define BS_MCG_C1_IREFSTEN (1U) //!< Bit field size in bits for MCG_C1_IREFSTEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C1_IREFSTEN field.
+#define BR_MCG_C1_IREFSTEN (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IREFSTEN))
+#endif
+
+//! @brief Format value for bitfield MCG_C1_IREFSTEN.
+#define BF_MCG_C1_IREFSTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C1_IREFSTEN), uint8_t) & BM_MCG_C1_IREFSTEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IREFSTEN field to a new value.
+#define BW_MCG_C1_IREFSTEN(v) (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IREFSTEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C1, field IRCLKEN[1] (RW)
+ *
+ * Enables the internal reference clock for use as MCGIRCLK.
+ *
+ * Values:
+ * - 0 - MCGIRCLK inactive.
+ * - 1 - MCGIRCLK active.
+ */
+//@{
+#define BP_MCG_C1_IRCLKEN (1U) //!< Bit position for MCG_C1_IRCLKEN.
+#define BM_MCG_C1_IRCLKEN (0x02U) //!< Bit mask for MCG_C1_IRCLKEN.
+#define BS_MCG_C1_IRCLKEN (1U) //!< Bit field size in bits for MCG_C1_IRCLKEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C1_IRCLKEN field.
+#define BR_MCG_C1_IRCLKEN (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IRCLKEN))
+#endif
+
+//! @brief Format value for bitfield MCG_C1_IRCLKEN.
+#define BF_MCG_C1_IRCLKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C1_IRCLKEN), uint8_t) & BM_MCG_C1_IRCLKEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IRCLKEN field to a new value.
+#define BW_MCG_C1_IRCLKEN(v) (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IRCLKEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C1, field IREFS[2] (RW)
+ *
+ * Selects the reference clock source for the FLL.
+ *
+ * Values:
+ * - 0 - External reference clock is selected.
+ * - 1 - The slow internal reference clock is selected.
+ */
+//@{
+#define BP_MCG_C1_IREFS (2U) //!< Bit position for MCG_C1_IREFS.
+#define BM_MCG_C1_IREFS (0x04U) //!< Bit mask for MCG_C1_IREFS.
+#define BS_MCG_C1_IREFS (1U) //!< Bit field size in bits for MCG_C1_IREFS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C1_IREFS field.
+#define BR_MCG_C1_IREFS (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IREFS))
+#endif
+
+//! @brief Format value for bitfield MCG_C1_IREFS.
+#define BF_MCG_C1_IREFS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C1_IREFS), uint8_t) & BM_MCG_C1_IREFS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IREFS field to a new value.
+#define BW_MCG_C1_IREFS(v) (BITBAND_ACCESS8(HW_MCG_C1_ADDR, BP_MCG_C1_IREFS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C1, field FRDIV[5:3] (RW)
+ *
+ * Selects the amount to divide down the external reference clock for the FLL.
+ * The resulting frequency must be in the range 31.25 kHz to 39.0625 kHz (This is
+ * required when FLL/DCO is the clock source for MCGOUTCLK . In FBE mode, it is
+ * not required to meet this range, but it is recommended in the cases when trying
+ * to enter a FLL mode from FBE).
+ *
+ * Values:
+ * - 000 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE
+ * values, Divide Factor is 32.
+ * - 001 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE
+ * values, Divide Factor is 64.
+ * - 010 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE
+ * values, Divide Factor is 128.
+ * - 011 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE
+ * values, Divide Factor is 256.
+ * - 100 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE
+ * values, Divide Factor is 512.
+ * - 101 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE
+ * values, Divide Factor is 1024.
+ * - 110 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE
+ * values, Divide Factor is 1280 .
+ * - 111 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE
+ * values, Divide Factor is 1536 .
+ */
+//@{
+#define BP_MCG_C1_FRDIV (3U) //!< Bit position for MCG_C1_FRDIV.
+#define BM_MCG_C1_FRDIV (0x38U) //!< Bit mask for MCG_C1_FRDIV.
+#define BS_MCG_C1_FRDIV (3U) //!< Bit field size in bits for MCG_C1_FRDIV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C1_FRDIV field.
+#define BR_MCG_C1_FRDIV (HW_MCG_C1.B.FRDIV)
+#endif
+
+//! @brief Format value for bitfield MCG_C1_FRDIV.
+#define BF_MCG_C1_FRDIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C1_FRDIV), uint8_t) & BM_MCG_C1_FRDIV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FRDIV field to a new value.
+#define BW_MCG_C1_FRDIV(v) (HW_MCG_C1_WR((HW_MCG_C1_RD() & ~BM_MCG_C1_FRDIV) | BF_MCG_C1_FRDIV(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C1, field CLKS[7:6] (RW)
+ *
+ * Selects the clock source for MCGOUTCLK .
+ *
+ * Values:
+ * - 00 - Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control
+ * bit).
+ * - 01 - Encoding 1 - Internal reference clock is selected.
+ * - 10 - Encoding 2 - External reference clock is selected.
+ * - 11 - Encoding 3 - Reserved.
+ */
+//@{
+#define BP_MCG_C1_CLKS (6U) //!< Bit position for MCG_C1_CLKS.
+#define BM_MCG_C1_CLKS (0xC0U) //!< Bit mask for MCG_C1_CLKS.
+#define BS_MCG_C1_CLKS (2U) //!< Bit field size in bits for MCG_C1_CLKS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C1_CLKS field.
+#define BR_MCG_C1_CLKS (HW_MCG_C1.B.CLKS)
+#endif
+
+//! @brief Format value for bitfield MCG_C1_CLKS.
+#define BF_MCG_C1_CLKS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C1_CLKS), uint8_t) & BM_MCG_C1_CLKS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLKS field to a new value.
+#define BW_MCG_C1_CLKS(v) (HW_MCG_C1_WR((HW_MCG_C1_RD() & ~BM_MCG_C1_CLKS) | BF_MCG_C1_CLKS(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCG_C2 - MCG Control 2 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCG_C2 - MCG Control 2 Register (RW)
+ *
+ * Reset value: 0x80U
+ */
+typedef union _hw_mcg_c2
+{
+ uint8_t U;
+ struct _hw_mcg_c2_bitfields
+ {
+ uint8_t IRCS : 1; //!< [0] Internal Reference Clock Select
+ uint8_t LP : 1; //!< [1] Low Power Select
+ uint8_t EREFS : 1; //!< [2] External Reference Select
+ uint8_t HGO : 1; //!< [3] High Gain Oscillator Select
+ uint8_t RANGE : 2; //!< [5:4] Frequency Range Select
+ uint8_t FCFTRIM : 1; //!< [6] Fast Internal Reference Clock Fine Trim
+ uint8_t LOCRE0 : 1; //!< [7] Loss of Clock Reset Enable
+ } B;
+} hw_mcg_c2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCG_C2 register
+ */
+//@{
+#define HW_MCG_C2_ADDR (REGS_MCG_BASE + 0x1U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCG_C2 (*(__IO hw_mcg_c2_t *) HW_MCG_C2_ADDR)
+#define HW_MCG_C2_RD() (HW_MCG_C2.U)
+#define HW_MCG_C2_WR(v) (HW_MCG_C2.U = (v))
+#define HW_MCG_C2_SET(v) (HW_MCG_C2_WR(HW_MCG_C2_RD() | (v)))
+#define HW_MCG_C2_CLR(v) (HW_MCG_C2_WR(HW_MCG_C2_RD() & ~(v)))
+#define HW_MCG_C2_TOG(v) (HW_MCG_C2_WR(HW_MCG_C2_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCG_C2 bitfields
+ */
+
+/*!
+ * @name Register MCG_C2, field IRCS[0] (RW)
+ *
+ * Selects between the fast or slow internal reference clock source.
+ *
+ * Values:
+ * - 0 - Slow internal reference clock selected.
+ * - 1 - Fast internal reference clock selected.
+ */
+//@{
+#define BP_MCG_C2_IRCS (0U) //!< Bit position for MCG_C2_IRCS.
+#define BM_MCG_C2_IRCS (0x01U) //!< Bit mask for MCG_C2_IRCS.
+#define BS_MCG_C2_IRCS (1U) //!< Bit field size in bits for MCG_C2_IRCS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C2_IRCS field.
+#define BR_MCG_C2_IRCS (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_IRCS))
+#endif
+
+//! @brief Format value for bitfield MCG_C2_IRCS.
+#define BF_MCG_C2_IRCS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_IRCS), uint8_t) & BM_MCG_C2_IRCS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IRCS field to a new value.
+#define BW_MCG_C2_IRCS(v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_IRCS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C2, field LP[1] (RW)
+ *
+ * Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. In FBE or
+ * PBE modes, setting this bit to 1 will transition the MCG into BLPE mode; in
+ * FBI mode, setting this bit to 1 will transition the MCG into BLPI mode. In any
+ * other MCG mode, LP bit has no affect.
+ *
+ * Values:
+ * - 0 - FLL or PLL is not disabled in bypass modes.
+ * - 1 - FLL or PLL is disabled in bypass modes (lower power)
+ */
+//@{
+#define BP_MCG_C2_LP (1U) //!< Bit position for MCG_C2_LP.
+#define BM_MCG_C2_LP (0x02U) //!< Bit mask for MCG_C2_LP.
+#define BS_MCG_C2_LP (1U) //!< Bit field size in bits for MCG_C2_LP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C2_LP field.
+#define BR_MCG_C2_LP (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_LP))
+#endif
+
+//! @brief Format value for bitfield MCG_C2_LP.
+#define BF_MCG_C2_LP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_LP), uint8_t) & BM_MCG_C2_LP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LP field to a new value.
+#define BW_MCG_C2_LP(v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_LP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C2, field EREFS[2] (RW)
+ *
+ * Selects the source for the external reference clock. See the Oscillator (OSC)
+ * chapter for more details.
+ *
+ * Values:
+ * - 0 - External reference clock requested.
+ * - 1 - Oscillator requested.
+ */
+//@{
+#define BP_MCG_C2_EREFS (2U) //!< Bit position for MCG_C2_EREFS.
+#define BM_MCG_C2_EREFS (0x04U) //!< Bit mask for MCG_C2_EREFS.
+#define BS_MCG_C2_EREFS (1U) //!< Bit field size in bits for MCG_C2_EREFS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C2_EREFS field.
+#define BR_MCG_C2_EREFS (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_EREFS))
+#endif
+
+//! @brief Format value for bitfield MCG_C2_EREFS.
+#define BF_MCG_C2_EREFS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_EREFS), uint8_t) & BM_MCG_C2_EREFS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EREFS field to a new value.
+#define BW_MCG_C2_EREFS(v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_EREFS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C2, field HGO[3] (RW)
+ *
+ * Controls the crystal oscillator mode of operation. See the Oscillator (OSC)
+ * chapter for more details.
+ *
+ * Values:
+ * - 0 - Configure crystal oscillator for low-power operation.
+ * - 1 - Configure crystal oscillator for high-gain operation.
+ */
+//@{
+#define BP_MCG_C2_HGO (3U) //!< Bit position for MCG_C2_HGO.
+#define BM_MCG_C2_HGO (0x08U) //!< Bit mask for MCG_C2_HGO.
+#define BS_MCG_C2_HGO (1U) //!< Bit field size in bits for MCG_C2_HGO.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C2_HGO field.
+#define BR_MCG_C2_HGO (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_HGO))
+#endif
+
+//! @brief Format value for bitfield MCG_C2_HGO.
+#define BF_MCG_C2_HGO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_HGO), uint8_t) & BM_MCG_C2_HGO)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HGO field to a new value.
+#define BW_MCG_C2_HGO(v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_HGO) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C2, field RANGE[5:4] (RW)
+ *
+ * Selects the frequency range for the crystal oscillator or external clock
+ * source. See the Oscillator (OSC) chapter for more details and the device data
+ * sheet for the frequency ranges used.
+ *
+ * Values:
+ * - 00 - Encoding 0 - Low frequency range selected for the crystal oscillator .
+ * - 01 - Encoding 1 - High frequency range selected for the crystal oscillator .
+ */
+//@{
+#define BP_MCG_C2_RANGE (4U) //!< Bit position for MCG_C2_RANGE.
+#define BM_MCG_C2_RANGE (0x30U) //!< Bit mask for MCG_C2_RANGE.
+#define BS_MCG_C2_RANGE (2U) //!< Bit field size in bits for MCG_C2_RANGE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C2_RANGE field.
+#define BR_MCG_C2_RANGE (HW_MCG_C2.B.RANGE)
+#endif
+
+//! @brief Format value for bitfield MCG_C2_RANGE.
+#define BF_MCG_C2_RANGE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_RANGE), uint8_t) & BM_MCG_C2_RANGE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RANGE field to a new value.
+#define BW_MCG_C2_RANGE(v) (HW_MCG_C2_WR((HW_MCG_C2_RD() & ~BM_MCG_C2_RANGE) | BF_MCG_C2_RANGE(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C2, field FCFTRIM[6] (RW)
+ *
+ * FCFTRIM controls the smallest adjustment of the fast internal reference clock
+ * frequency. Setting FCFTRIM increases the period and clearing FCFTRIM
+ * decreases the period by the smallest amount possible. If an FCFTRIM value stored in
+ * nonvolatile memory is to be used, it is your responsibility to copy that value
+ * from the nonvolatile memory location to this bit.
+ */
+//@{
+#define BP_MCG_C2_FCFTRIM (6U) //!< Bit position for MCG_C2_FCFTRIM.
+#define BM_MCG_C2_FCFTRIM (0x40U) //!< Bit mask for MCG_C2_FCFTRIM.
+#define BS_MCG_C2_FCFTRIM (1U) //!< Bit field size in bits for MCG_C2_FCFTRIM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C2_FCFTRIM field.
+#define BR_MCG_C2_FCFTRIM (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_FCFTRIM))
+#endif
+
+//! @brief Format value for bitfield MCG_C2_FCFTRIM.
+#define BF_MCG_C2_FCFTRIM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_FCFTRIM), uint8_t) & BM_MCG_C2_FCFTRIM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FCFTRIM field to a new value.
+#define BW_MCG_C2_FCFTRIM(v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_FCFTRIM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C2, field LOCRE0[7] (RW)
+ *
+ * Determines whether an interrupt or a reset request is made following a loss
+ * of OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is
+ * set.
+ *
+ * Values:
+ * - 0 - Interrupt request is generated on a loss of OSC0 external reference
+ * clock.
+ * - 1 - Generate a reset request on a loss of OSC0 external reference clock.
+ */
+//@{
+#define BP_MCG_C2_LOCRE0 (7U) //!< Bit position for MCG_C2_LOCRE0.
+#define BM_MCG_C2_LOCRE0 (0x80U) //!< Bit mask for MCG_C2_LOCRE0.
+#define BS_MCG_C2_LOCRE0 (1U) //!< Bit field size in bits for MCG_C2_LOCRE0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C2_LOCRE0 field.
+#define BR_MCG_C2_LOCRE0 (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_LOCRE0))
+#endif
+
+//! @brief Format value for bitfield MCG_C2_LOCRE0.
+#define BF_MCG_C2_LOCRE0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C2_LOCRE0), uint8_t) & BM_MCG_C2_LOCRE0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LOCRE0 field to a new value.
+#define BW_MCG_C2_LOCRE0(v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR, BP_MCG_C2_LOCRE0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCG_C3 - MCG Control 3 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCG_C3 - MCG Control 3 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_mcg_c3
+{
+ uint8_t U;
+ struct _hw_mcg_c3_bitfields
+ {
+ uint8_t SCTRIM : 8; //!< [7:0] Slow Internal Reference Clock Trim
+ //! Setting
+ } B;
+} hw_mcg_c3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCG_C3 register
+ */
+//@{
+#define HW_MCG_C3_ADDR (REGS_MCG_BASE + 0x2U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCG_C3 (*(__IO hw_mcg_c3_t *) HW_MCG_C3_ADDR)
+#define HW_MCG_C3_RD() (HW_MCG_C3.U)
+#define HW_MCG_C3_WR(v) (HW_MCG_C3.U = (v))
+#define HW_MCG_C3_SET(v) (HW_MCG_C3_WR(HW_MCG_C3_RD() | (v)))
+#define HW_MCG_C3_CLR(v) (HW_MCG_C3_WR(HW_MCG_C3_RD() & ~(v)))
+#define HW_MCG_C3_TOG(v) (HW_MCG_C3_WR(HW_MCG_C3_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCG_C3 bitfields
+ */
+
+/*!
+ * @name Register MCG_C3, field SCTRIM[7:0] (RW)
+ *
+ * SCTRIM A value for SCTRIM is loaded during reset from a factory programmed
+ * location. controls the slow internal reference clock frequency by controlling
+ * the slow internal reference clock period. The SCTRIM bits are binary weighted,
+ * that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value
+ * increases the period, and decreasing the value decreases the period. An additional
+ * fine trim bit is available in C4 register as the SCFTRIM bit. Upon reset,
+ * this value is loaded with a factory trim value. If an SCTRIM value stored in
+ * nonvolatile memory is to be used, it is your responsibility to copy that value
+ * from the nonvolatile memory location to this register.
+ */
+//@{
+#define BP_MCG_C3_SCTRIM (0U) //!< Bit position for MCG_C3_SCTRIM.
+#define BM_MCG_C3_SCTRIM (0xFFU) //!< Bit mask for MCG_C3_SCTRIM.
+#define BS_MCG_C3_SCTRIM (8U) //!< Bit field size in bits for MCG_C3_SCTRIM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C3_SCTRIM field.
+#define BR_MCG_C3_SCTRIM (HW_MCG_C3.U)
+#endif
+
+//! @brief Format value for bitfield MCG_C3_SCTRIM.
+#define BF_MCG_C3_SCTRIM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C3_SCTRIM), uint8_t) & BM_MCG_C3_SCTRIM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SCTRIM field to a new value.
+#define BW_MCG_C3_SCTRIM(v) (HW_MCG_C3_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCG_C4 - MCG Control 4 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCG_C4 - MCG Control 4 Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Reset values for DRST and DMX32 bits are 0.
+ */
+typedef union _hw_mcg_c4
+{
+ uint8_t U;
+ struct _hw_mcg_c4_bitfields
+ {
+ uint8_t SCFTRIM : 1; //!< [0] Slow Internal Reference Clock Fine Trim
+ uint8_t FCTRIM : 4; //!< [4:1] Fast Internal Reference Clock Trim
+ //! Setting
+ uint8_t DRST_DRS : 2; //!< [6:5] DCO Range Select
+ uint8_t DMX32 : 1; //!< [7] DCO Maximum Frequency with 32.768 kHz
+ //! Reference
+ } B;
+} hw_mcg_c4_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCG_C4 register
+ */
+//@{
+#define HW_MCG_C4_ADDR (REGS_MCG_BASE + 0x3U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCG_C4 (*(__IO hw_mcg_c4_t *) HW_MCG_C4_ADDR)
+#define HW_MCG_C4_RD() (HW_MCG_C4.U)
+#define HW_MCG_C4_WR(v) (HW_MCG_C4.U = (v))
+#define HW_MCG_C4_SET(v) (HW_MCG_C4_WR(HW_MCG_C4_RD() | (v)))
+#define HW_MCG_C4_CLR(v) (HW_MCG_C4_WR(HW_MCG_C4_RD() & ~(v)))
+#define HW_MCG_C4_TOG(v) (HW_MCG_C4_WR(HW_MCG_C4_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCG_C4 bitfields
+ */
+
+/*!
+ * @name Register MCG_C4, field SCFTRIM[0] (RW)
+ *
+ * SCFTRIM A value for SCFTRIM is loaded during reset from a factory programmed
+ * location . controls the smallest adjustment of the slow internal reference
+ * clock frequency. Setting SCFTRIM increases the period and clearing SCFTRIM
+ * decreases the period by the smallest amount possible. If an SCFTRIM value stored in
+ * nonvolatile memory is to be used, it is your responsibility to copy that value
+ * from the nonvolatile memory location to this bit.
+ */
+//@{
+#define BP_MCG_C4_SCFTRIM (0U) //!< Bit position for MCG_C4_SCFTRIM.
+#define BM_MCG_C4_SCFTRIM (0x01U) //!< Bit mask for MCG_C4_SCFTRIM.
+#define BS_MCG_C4_SCFTRIM (1U) //!< Bit field size in bits for MCG_C4_SCFTRIM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C4_SCFTRIM field.
+#define BR_MCG_C4_SCFTRIM (BITBAND_ACCESS8(HW_MCG_C4_ADDR, BP_MCG_C4_SCFTRIM))
+#endif
+
+//! @brief Format value for bitfield MCG_C4_SCFTRIM.
+#define BF_MCG_C4_SCFTRIM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C4_SCFTRIM), uint8_t) & BM_MCG_C4_SCFTRIM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SCFTRIM field to a new value.
+#define BW_MCG_C4_SCFTRIM(v) (BITBAND_ACCESS8(HW_MCG_C4_ADDR, BP_MCG_C4_SCFTRIM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C4, field FCTRIM[4:1] (RW)
+ *
+ * FCTRIM A value for FCTRIM is loaded during reset from a factory programmed
+ * location. controls the fast internal reference clock frequency by controlling
+ * the fast internal reference clock period. The FCTRIM bits are binary weighted,
+ * that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value
+ * increases the period, and decreasing the value decreases the period. If an
+ * FCTRIM[3:0] value stored in nonvolatile memory is to be used, it is your
+ * responsibility to copy that value from the nonvolatile memory location to this register.
+ */
+//@{
+#define BP_MCG_C4_FCTRIM (1U) //!< Bit position for MCG_C4_FCTRIM.
+#define BM_MCG_C4_FCTRIM (0x1EU) //!< Bit mask for MCG_C4_FCTRIM.
+#define BS_MCG_C4_FCTRIM (4U) //!< Bit field size in bits for MCG_C4_FCTRIM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C4_FCTRIM field.
+#define BR_MCG_C4_FCTRIM (HW_MCG_C4.B.FCTRIM)
+#endif
+
+//! @brief Format value for bitfield MCG_C4_FCTRIM.
+#define BF_MCG_C4_FCTRIM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C4_FCTRIM), uint8_t) & BM_MCG_C4_FCTRIM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FCTRIM field to a new value.
+#define BW_MCG_C4_FCTRIM(v) (HW_MCG_C4_WR((HW_MCG_C4_RD() & ~BM_MCG_C4_FCTRIM) | BF_MCG_C4_FCTRIM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C4, field DRST_DRS[6:5] (RW)
+ *
+ * The DRS bits select the frequency range for the FLL output, DCOOUT. When the
+ * LP bit is set, writes to the DRS bits are ignored. The DRST read field
+ * indicates the current frequency range for DCOOUT. The DRST field does not update
+ * immediately after a write to the DRS field due to internal synchronization between
+ * clock domains. See the DCO Frequency Range table for more details.
+ *
+ * Values:
+ * - 00 - Encoding 0 - Low range (reset default).
+ * - 01 - Encoding 1 - Mid range.
+ * - 10 - Encoding 2 - Mid-high range.
+ * - 11 - Encoding 3 - High range.
+ */
+//@{
+#define BP_MCG_C4_DRST_DRS (5U) //!< Bit position for MCG_C4_DRST_DRS.
+#define BM_MCG_C4_DRST_DRS (0x60U) //!< Bit mask for MCG_C4_DRST_DRS.
+#define BS_MCG_C4_DRST_DRS (2U) //!< Bit field size in bits for MCG_C4_DRST_DRS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C4_DRST_DRS field.
+#define BR_MCG_C4_DRST_DRS (HW_MCG_C4.B.DRST_DRS)
+#endif
+
+//! @brief Format value for bitfield MCG_C4_DRST_DRS.
+#define BF_MCG_C4_DRST_DRS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C4_DRST_DRS), uint8_t) & BM_MCG_C4_DRST_DRS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DRST_DRS field to a new value.
+#define BW_MCG_C4_DRST_DRS(v) (HW_MCG_C4_WR((HW_MCG_C4_RD() & ~BM_MCG_C4_DRST_DRS) | BF_MCG_C4_DRST_DRS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C4, field DMX32[7] (RW)
+ *
+ * The DMX32 bit controls whether the DCO frequency range is narrowed to its
+ * maximum frequency with a 32.768 kHz reference. The following table identifies
+ * settings for the DCO frequency range. The system clocks derived from this source
+ * should not exceed their specified maximums. DRST_DRS DMX32 Reference Range FLL
+ * Factor DCO Range 00 0 31.25-39.0625 kHz 640 20-25 MHz 1 32.768 kHz 732 24 MHz
+ * 01 0 31.25-39.0625 kHz 1280 40-50 MHz 1 32.768 kHz 1464 48 MHz 10 0
+ * 31.25-39.0625 kHz 1920 60-75 MHz 1 32.768 kHz 2197 72 MHz 11 0 31.25-39.0625 kHz 2560
+ * 80-100 MHz 1 32.768 kHz 2929 96 MHz
+ *
+ * Values:
+ * - 0 - DCO has a default range of 25%.
+ * - 1 - DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
+ */
+//@{
+#define BP_MCG_C4_DMX32 (7U) //!< Bit position for MCG_C4_DMX32.
+#define BM_MCG_C4_DMX32 (0x80U) //!< Bit mask for MCG_C4_DMX32.
+#define BS_MCG_C4_DMX32 (1U) //!< Bit field size in bits for MCG_C4_DMX32.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C4_DMX32 field.
+#define BR_MCG_C4_DMX32 (BITBAND_ACCESS8(HW_MCG_C4_ADDR, BP_MCG_C4_DMX32))
+#endif
+
+//! @brief Format value for bitfield MCG_C4_DMX32.
+#define BF_MCG_C4_DMX32(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C4_DMX32), uint8_t) & BM_MCG_C4_DMX32)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMX32 field to a new value.
+#define BW_MCG_C4_DMX32(v) (BITBAND_ACCESS8(HW_MCG_C4_ADDR, BP_MCG_C4_DMX32) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCG_C5 - MCG Control 5 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCG_C5 - MCG Control 5 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_mcg_c5
+{
+ uint8_t U;
+ struct _hw_mcg_c5_bitfields
+ {
+ uint8_t PRDIV0 : 5; //!< [4:0] PLL External Reference Divider
+ uint8_t PLLSTEN0 : 1; //!< [5] PLL Stop Enable
+ uint8_t PLLCLKEN0 : 1; //!< [6] PLL Clock Enable
+ uint8_t RESERVED0 : 1; //!< [7]
+ } B;
+} hw_mcg_c5_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCG_C5 register
+ */
+//@{
+#define HW_MCG_C5_ADDR (REGS_MCG_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCG_C5 (*(__IO hw_mcg_c5_t *) HW_MCG_C5_ADDR)
+#define HW_MCG_C5_RD() (HW_MCG_C5.U)
+#define HW_MCG_C5_WR(v) (HW_MCG_C5.U = (v))
+#define HW_MCG_C5_SET(v) (HW_MCG_C5_WR(HW_MCG_C5_RD() | (v)))
+#define HW_MCG_C5_CLR(v) (HW_MCG_C5_WR(HW_MCG_C5_RD() & ~(v)))
+#define HW_MCG_C5_TOG(v) (HW_MCG_C5_WR(HW_MCG_C5_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCG_C5 bitfields
+ */
+
+/*!
+ * @name Register MCG_C5, field PRDIV0[4:0] (RW)
+ *
+ * Selects the amount to divide down the external reference clock for the PLL.
+ * The resulting frequency must be in the range of 2 MHz to 4 MHz. After the PLL
+ * is enabled (by setting either PLLCLKEN 0 or PLLS), the PRDIV 0 value must not
+ * be changed when LOCK0 is zero. PLL External Reference Divide Factor PRDIV 0
+ * Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor
+ * 00000 1 01000 9 10000 17 11000 25 00001 2 01001 10 10001 18 11001 Reserved
+ * 00010 3 01010 11 10010 19 11010 Reserved 00011 4 01011 12 10011 20 11011 Reserved
+ * 00100 5 01100 13 10100 21 11100 Reserved 00101 6 01101 14 10101 22 11101
+ * Reserved 00110 7 01110 15 10110 23 11110 Reserved 00111 8 01111 16 10111 24 11111
+ * Reserved
+ */
+//@{
+#define BP_MCG_C5_PRDIV0 (0U) //!< Bit position for MCG_C5_PRDIV0.
+#define BM_MCG_C5_PRDIV0 (0x1FU) //!< Bit mask for MCG_C5_PRDIV0.
+#define BS_MCG_C5_PRDIV0 (5U) //!< Bit field size in bits for MCG_C5_PRDIV0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C5_PRDIV0 field.
+#define BR_MCG_C5_PRDIV0 (HW_MCG_C5.B.PRDIV0)
+#endif
+
+//! @brief Format value for bitfield MCG_C5_PRDIV0.
+#define BF_MCG_C5_PRDIV0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C5_PRDIV0), uint8_t) & BM_MCG_C5_PRDIV0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PRDIV0 field to a new value.
+#define BW_MCG_C5_PRDIV0(v) (HW_MCG_C5_WR((HW_MCG_C5_RD() & ~BM_MCG_C5_PRDIV0) | BF_MCG_C5_PRDIV0(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C5, field PLLSTEN0[5] (RW)
+ *
+ * Enables the PLL Clock during Normal Stop. In Low Power Stop mode, the PLL
+ * clock gets disabled even if PLLSTEN 0 =1. All other power modes, PLLSTEN 0 bit
+ * has no affect and does not enable the PLL Clock to run if it is written to 1.
+ *
+ * Values:
+ * - 0 - MCGPLLCLK is disabled in any of the Stop modes.
+ * - 1 - MCGPLLCLK is enabled if system is in Normal Stop mode.
+ */
+//@{
+#define BP_MCG_C5_PLLSTEN0 (5U) //!< Bit position for MCG_C5_PLLSTEN0.
+#define BM_MCG_C5_PLLSTEN0 (0x20U) //!< Bit mask for MCG_C5_PLLSTEN0.
+#define BS_MCG_C5_PLLSTEN0 (1U) //!< Bit field size in bits for MCG_C5_PLLSTEN0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C5_PLLSTEN0 field.
+#define BR_MCG_C5_PLLSTEN0 (BITBAND_ACCESS8(HW_MCG_C5_ADDR, BP_MCG_C5_PLLSTEN0))
+#endif
+
+//! @brief Format value for bitfield MCG_C5_PLLSTEN0.
+#define BF_MCG_C5_PLLSTEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C5_PLLSTEN0), uint8_t) & BM_MCG_C5_PLLSTEN0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PLLSTEN0 field to a new value.
+#define BW_MCG_C5_PLLSTEN0(v) (BITBAND_ACCESS8(HW_MCG_C5_ADDR, BP_MCG_C5_PLLSTEN0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C5, field PLLCLKEN0[6] (RW)
+ *
+ * Enables the PLL independent of PLLS and enables the PLL clock for use as
+ * MCGPLLCLK. (PRDIV 0 needs to be programmed to the correct divider to generate a
+ * PLL reference clock in the range of 2 - 4 MHz range prior to setting the
+ * PLLCLKEN 0 bit). Setting PLLCLKEN 0 will enable the external oscillator if not
+ * already enabled. Whenever the PLL is being enabled by means of the PLLCLKEN 0 bit,
+ * and the external oscillator is being used as the reference clock, the OSCINIT 0
+ * bit should be checked to make sure it is set.
+ *
+ * Values:
+ * - 0 - MCGPLLCLK is inactive.
+ * - 1 - MCGPLLCLK is active.
+ */
+//@{
+#define BP_MCG_C5_PLLCLKEN0 (6U) //!< Bit position for MCG_C5_PLLCLKEN0.
+#define BM_MCG_C5_PLLCLKEN0 (0x40U) //!< Bit mask for MCG_C5_PLLCLKEN0.
+#define BS_MCG_C5_PLLCLKEN0 (1U) //!< Bit field size in bits for MCG_C5_PLLCLKEN0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C5_PLLCLKEN0 field.
+#define BR_MCG_C5_PLLCLKEN0 (BITBAND_ACCESS8(HW_MCG_C5_ADDR, BP_MCG_C5_PLLCLKEN0))
+#endif
+
+//! @brief Format value for bitfield MCG_C5_PLLCLKEN0.
+#define BF_MCG_C5_PLLCLKEN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C5_PLLCLKEN0), uint8_t) & BM_MCG_C5_PLLCLKEN0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PLLCLKEN0 field to a new value.
+#define BW_MCG_C5_PLLCLKEN0(v) (BITBAND_ACCESS8(HW_MCG_C5_ADDR, BP_MCG_C5_PLLCLKEN0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCG_C6 - MCG Control 6 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCG_C6 - MCG Control 6 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_mcg_c6
+{
+ uint8_t U;
+ struct _hw_mcg_c6_bitfields
+ {
+ uint8_t VDIV0 : 5; //!< [4:0] VCO 0 Divider
+ uint8_t CME0 : 1; //!< [5] Clock Monitor Enable
+ uint8_t PLLS : 1; //!< [6] PLL Select
+ uint8_t LOLIE0 : 1; //!< [7] Loss of Lock Interrrupt Enable
+ } B;
+} hw_mcg_c6_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCG_C6 register
+ */
+//@{
+#define HW_MCG_C6_ADDR (REGS_MCG_BASE + 0x5U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCG_C6 (*(__IO hw_mcg_c6_t *) HW_MCG_C6_ADDR)
+#define HW_MCG_C6_RD() (HW_MCG_C6.U)
+#define HW_MCG_C6_WR(v) (HW_MCG_C6.U = (v))
+#define HW_MCG_C6_SET(v) (HW_MCG_C6_WR(HW_MCG_C6_RD() | (v)))
+#define HW_MCG_C6_CLR(v) (HW_MCG_C6_WR(HW_MCG_C6_RD() & ~(v)))
+#define HW_MCG_C6_TOG(v) (HW_MCG_C6_WR(HW_MCG_C6_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCG_C6 bitfields
+ */
+
+/*!
+ * @name Register MCG_C6, field VDIV0[4:0] (RW)
+ *
+ * Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits
+ * establish the multiplication factor (M) applied to the reference clock frequency.
+ * After the PLL is enabled (by setting either PLLCLKEN 0 or PLLS), the VDIV 0
+ * value must not be changed when LOCK 0 is zero. PLL VCO Divide Factor VDIV 0
+ * Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply
+ * Factor 00000 24 01000 32 10000 40 11000 48 00001 25 01001 33 10001 41 11001 49
+ * 00010 26 01010 34 10010 42 11010 50 00011 27 01011 35 10011 43 11011 51 00100 28
+ * 01100 36 10100 44 11100 52 00101 29 01101 37 10101 45 11101 53 00110 30 01110
+ * 38 10110 46 11110 54 00111 31 01111 39 10111 47 11111 55
+ */
+//@{
+#define BP_MCG_C6_VDIV0 (0U) //!< Bit position for MCG_C6_VDIV0.
+#define BM_MCG_C6_VDIV0 (0x1FU) //!< Bit mask for MCG_C6_VDIV0.
+#define BS_MCG_C6_VDIV0 (5U) //!< Bit field size in bits for MCG_C6_VDIV0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C6_VDIV0 field.
+#define BR_MCG_C6_VDIV0 (HW_MCG_C6.B.VDIV0)
+#endif
+
+//! @brief Format value for bitfield MCG_C6_VDIV0.
+#define BF_MCG_C6_VDIV0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C6_VDIV0), uint8_t) & BM_MCG_C6_VDIV0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the VDIV0 field to a new value.
+#define BW_MCG_C6_VDIV0(v) (HW_MCG_C6_WR((HW_MCG_C6_RD() & ~BM_MCG_C6_VDIV0) | BF_MCG_C6_VDIV0(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C6, field CME0[5] (RW)
+ *
+ * Enables the loss of clock monitoring circuit for the OSC0 external reference
+ * mux select. The LOCRE0 bit will determine if a interrupt or a reset request is
+ * generated following a loss of OSC0 indication. The CME0 bit must only be set
+ * to a logic 1 when the MCG is in an operational mode that uses the external
+ * clock (FEE, FBE, PEE, PBE, or BLPE) . Whenever the CME0 bit is set to a logic 1,
+ * the value of the RANGE0 bits in the C2 register should not be changed. CME0
+ * bit should be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
+ * reset request may occur while in Stop mode. CME0 should also be set to a
+ * logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode.
+ *
+ * Values:
+ * - 0 - External clock monitor is disabled for OSC0.
+ * - 1 - External clock monitor is enabled for OSC0.
+ */
+//@{
+#define BP_MCG_C6_CME0 (5U) //!< Bit position for MCG_C6_CME0.
+#define BM_MCG_C6_CME0 (0x20U) //!< Bit mask for MCG_C6_CME0.
+#define BS_MCG_C6_CME0 (1U) //!< Bit field size in bits for MCG_C6_CME0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C6_CME0 field.
+#define BR_MCG_C6_CME0 (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_CME0))
+#endif
+
+//! @brief Format value for bitfield MCG_C6_CME0.
+#define BF_MCG_C6_CME0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C6_CME0), uint8_t) & BM_MCG_C6_CME0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CME0 field to a new value.
+#define BW_MCG_C6_CME0(v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_CME0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C6, field PLLS[6] (RW)
+ *
+ * Controls whether the PLL or FLL output is selected as the MCG source when
+ * CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN 0 is not set, the PLL is
+ * disabled in all modes. If the PLLS is set, the FLL is disabled in all modes.
+ *
+ * Values:
+ * - 0 - FLL is selected.
+ * - 1 - PLL is selected (PRDIV 0 need to be programmed to the correct divider
+ * to generate a PLL reference clock in the range of 2-4 MHz prior to setting
+ * the PLLS bit).
+ */
+//@{
+#define BP_MCG_C6_PLLS (6U) //!< Bit position for MCG_C6_PLLS.
+#define BM_MCG_C6_PLLS (0x40U) //!< Bit mask for MCG_C6_PLLS.
+#define BS_MCG_C6_PLLS (1U) //!< Bit field size in bits for MCG_C6_PLLS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C6_PLLS field.
+#define BR_MCG_C6_PLLS (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_PLLS))
+#endif
+
+//! @brief Format value for bitfield MCG_C6_PLLS.
+#define BF_MCG_C6_PLLS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C6_PLLS), uint8_t) & BM_MCG_C6_PLLS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PLLS field to a new value.
+#define BW_MCG_C6_PLLS(v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_PLLS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C6, field LOLIE0[7] (RW)
+ *
+ * Determines if an interrupt request is made following a loss of lock
+ * indication. This bit only has an effect when LOLS 0 is set.
+ *
+ * Values:
+ * - 0 - No interrupt request is generated on loss of lock.
+ * - 1 - Generate an interrupt request on loss of lock.
+ */
+//@{
+#define BP_MCG_C6_LOLIE0 (7U) //!< Bit position for MCG_C6_LOLIE0.
+#define BM_MCG_C6_LOLIE0 (0x80U) //!< Bit mask for MCG_C6_LOLIE0.
+#define BS_MCG_C6_LOLIE0 (1U) //!< Bit field size in bits for MCG_C6_LOLIE0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C6_LOLIE0 field.
+#define BR_MCG_C6_LOLIE0 (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_LOLIE0))
+#endif
+
+//! @brief Format value for bitfield MCG_C6_LOLIE0.
+#define BF_MCG_C6_LOLIE0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C6_LOLIE0), uint8_t) & BM_MCG_C6_LOLIE0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LOLIE0 field to a new value.
+#define BW_MCG_C6_LOLIE0(v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR, BP_MCG_C6_LOLIE0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCG_S - MCG Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCG_S - MCG Status Register (RW)
+ *
+ * Reset value: 0x10U
+ */
+typedef union _hw_mcg_s
+{
+ uint8_t U;
+ struct _hw_mcg_s_bitfields
+ {
+ uint8_t IRCST : 1; //!< [0] Internal Reference Clock Status
+ uint8_t OSCINIT0 : 1; //!< [1] OSC Initialization
+ uint8_t CLKST : 2; //!< [3:2] Clock Mode Status
+ uint8_t IREFST : 1; //!< [4] Internal Reference Status
+ uint8_t PLLST : 1; //!< [5] PLL Select Status
+ uint8_t LOCK0 : 1; //!< [6] Lock Status
+ uint8_t LOLS0 : 1; //!< [7] Loss of Lock Status
+ } B;
+} hw_mcg_s_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCG_S register
+ */
+//@{
+#define HW_MCG_S_ADDR (REGS_MCG_BASE + 0x6U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCG_S (*(__IO hw_mcg_s_t *) HW_MCG_S_ADDR)
+#define HW_MCG_S_RD() (HW_MCG_S.U)
+#define HW_MCG_S_WR(v) (HW_MCG_S.U = (v))
+#define HW_MCG_S_SET(v) (HW_MCG_S_WR(HW_MCG_S_RD() | (v)))
+#define HW_MCG_S_CLR(v) (HW_MCG_S_WR(HW_MCG_S_RD() & ~(v)))
+#define HW_MCG_S_TOG(v) (HW_MCG_S_WR(HW_MCG_S_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCG_S bitfields
+ */
+
+/*!
+ * @name Register MCG_S, field IRCST[0] (RO)
+ *
+ * The IRCST bit indicates the current source for the internal reference clock
+ * select clock (IRCSCLK). The IRCST bit does not update immediately after a write
+ * to the IRCS bit due to internal synchronization between clock domains. The
+ * IRCST bit will only be updated if the internal reference clock is enabled,
+ * either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN]
+ * bit .
+ *
+ * Values:
+ * - 0 - Source of internal reference clock is the slow clock (32 kHz IRC).
+ * - 1 - Source of internal reference clock is the fast clock (4 MHz IRC).
+ */
+//@{
+#define BP_MCG_S_IRCST (0U) //!< Bit position for MCG_S_IRCST.
+#define BM_MCG_S_IRCST (0x01U) //!< Bit mask for MCG_S_IRCST.
+#define BS_MCG_S_IRCST (1U) //!< Bit field size in bits for MCG_S_IRCST.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_S_IRCST field.
+#define BR_MCG_S_IRCST (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_IRCST))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_S, field OSCINIT0[1] (RO)
+ *
+ * This bit, which resets to 0, is set to 1 after the initialization cycles of
+ * the crystal oscillator clock have completed. After being set, the bit is
+ * cleared to 0 if the OSC is subsequently disabled. See the OSC module's detailed
+ * description for more information.
+ */
+//@{
+#define BP_MCG_S_OSCINIT0 (1U) //!< Bit position for MCG_S_OSCINIT0.
+#define BM_MCG_S_OSCINIT0 (0x02U) //!< Bit mask for MCG_S_OSCINIT0.
+#define BS_MCG_S_OSCINIT0 (1U) //!< Bit field size in bits for MCG_S_OSCINIT0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_S_OSCINIT0 field.
+#define BR_MCG_S_OSCINIT0 (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_OSCINIT0))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_S, field CLKST[3:2] (RO)
+ *
+ * These bits indicate the current clock mode. The CLKST bits do not update
+ * immediately after a write to the CLKS bits due to internal synchronization between
+ * clock domains.
+ *
+ * Values:
+ * - 00 - Encoding 0 - Output of the FLL is selected (reset default).
+ * - 01 - Encoding 1 - Internal reference clock is selected.
+ * - 10 - Encoding 2 - External reference clock is selected.
+ * - 11 - Encoding 3 - Output of the PLL is selected.
+ */
+//@{
+#define BP_MCG_S_CLKST (2U) //!< Bit position for MCG_S_CLKST.
+#define BM_MCG_S_CLKST (0x0CU) //!< Bit mask for MCG_S_CLKST.
+#define BS_MCG_S_CLKST (2U) //!< Bit field size in bits for MCG_S_CLKST.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_S_CLKST field.
+#define BR_MCG_S_CLKST (HW_MCG_S.B.CLKST)
+#endif
+//@}
+
+/*!
+ * @name Register MCG_S, field IREFST[4] (RO)
+ *
+ * This bit indicates the current source for the FLL reference clock. The IREFST
+ * bit does not update immediately after a write to the IREFS bit due to
+ * internal synchronization between clock domains.
+ *
+ * Values:
+ * - 0 - Source of FLL reference clock is the external reference clock.
+ * - 1 - Source of FLL reference clock is the internal reference clock.
+ */
+//@{
+#define BP_MCG_S_IREFST (4U) //!< Bit position for MCG_S_IREFST.
+#define BM_MCG_S_IREFST (0x10U) //!< Bit mask for MCG_S_IREFST.
+#define BS_MCG_S_IREFST (1U) //!< Bit field size in bits for MCG_S_IREFST.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_S_IREFST field.
+#define BR_MCG_S_IREFST (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_IREFST))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_S, field PLLST[5] (RO)
+ *
+ * This bit indicates the clock source selected by PLLS . The PLLST bit does not
+ * update immediately after a write to the PLLS bit due to internal
+ * synchronization between clock domains.
+ *
+ * Values:
+ * - 0 - Source of PLLS clock is FLL clock.
+ * - 1 - Source of PLLS clock is PLL output clock.
+ */
+//@{
+#define BP_MCG_S_PLLST (5U) //!< Bit position for MCG_S_PLLST.
+#define BM_MCG_S_PLLST (0x20U) //!< Bit mask for MCG_S_PLLST.
+#define BS_MCG_S_PLLST (1U) //!< Bit field size in bits for MCG_S_PLLST.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_S_PLLST field.
+#define BR_MCG_S_PLLST (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_PLLST))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_S, field LOCK0[6] (RO)
+ *
+ * This bit indicates whether the PLL has acquired lock. Lock detection is only
+ * enabled when the PLL is enabled (either through clock mode selection or
+ * PLLCLKEN0=1 setting). While the PLL clock is locking to the desired frequency, the
+ * MCG PLL clock (MCGPLLCLK) will be gated off until the LOCK bit gets asserted.
+ * If the lock status bit is set, changing the value of the PRDIV0 [4:0] bits in
+ * the C5 register or the VDIV0[4:0] bits in the C6 register causes the lock
+ * status bit to clear and stay cleared until the PLL has reacquired lock. Loss of PLL
+ * reference clock will also cause the LOCK0 bit to clear until the PLL has
+ * reacquired lock. Entry into LLS, VLPS, or regular Stop with PLLSTEN=0 also causes
+ * the lock status bit to clear and stay cleared until the Stop mode is exited
+ * and the PLL has reacquired lock. Any time the PLL is enabled and the LOCK0 bit
+ * is cleared, the MCGPLLCLK will be gated off until the LOCK0 bit is asserted
+ * again.
+ *
+ * Values:
+ * - 0 - PLL is currently unlocked.
+ * - 1 - PLL is currently locked.
+ */
+//@{
+#define BP_MCG_S_LOCK0 (6U) //!< Bit position for MCG_S_LOCK0.
+#define BM_MCG_S_LOCK0 (0x40U) //!< Bit mask for MCG_S_LOCK0.
+#define BS_MCG_S_LOCK0 (1U) //!< Bit field size in bits for MCG_S_LOCK0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_S_LOCK0 field.
+#define BR_MCG_S_LOCK0 (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_LOCK0))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_S, field LOLS0[7] (W1C)
+ *
+ * This bit is a sticky bit indicating the lock status for the PLL. LOLS is set
+ * if after acquiring lock, the PLL output frequency has fallen outside the lock
+ * exit frequency tolerance, D unl . LOLIE determines whether an interrupt
+ * request is made when LOLS is set. LOLRE determines whether a reset request is made
+ * when LOLS is set. This bit is cleared by reset or by writing a logic 1 to it
+ * when set. Writing a logic 0 to this bit has no effect.
+ *
+ * Values:
+ * - 0 - PLL has not lost lock since LOLS 0 was last cleared.
+ * - 1 - PLL has lost lock since LOLS 0 was last cleared.
+ */
+//@{
+#define BP_MCG_S_LOLS0 (7U) //!< Bit position for MCG_S_LOLS0.
+#define BM_MCG_S_LOLS0 (0x80U) //!< Bit mask for MCG_S_LOLS0.
+#define BS_MCG_S_LOLS0 (1U) //!< Bit field size in bits for MCG_S_LOLS0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_S_LOLS0 field.
+#define BR_MCG_S_LOLS0 (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_LOLS0))
+#endif
+
+//! @brief Format value for bitfield MCG_S_LOLS0.
+#define BF_MCG_S_LOLS0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_S_LOLS0), uint8_t) & BM_MCG_S_LOLS0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LOLS0 field to a new value.
+#define BW_MCG_S_LOLS0(v) (BITBAND_ACCESS8(HW_MCG_S_ADDR, BP_MCG_S_LOLS0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCG_SC - MCG Status and Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCG_SC - MCG Status and Control Register (RW)
+ *
+ * Reset value: 0x02U
+ */
+typedef union _hw_mcg_sc
+{
+ uint8_t U;
+ struct _hw_mcg_sc_bitfields
+ {
+ uint8_t LOCS0 : 1; //!< [0] OSC0 Loss of Clock Status
+ uint8_t FCRDIV : 3; //!< [3:1] Fast Clock Internal Reference Divider
+ uint8_t FLTPRSRV : 1; //!< [4] FLL Filter Preserve Enable
+ uint8_t ATMF : 1; //!< [5] Automatic Trim Machine Fail Flag
+ uint8_t ATMS : 1; //!< [6] Automatic Trim Machine Select
+ uint8_t ATME : 1; //!< [7] Automatic Trim Machine Enable
+ } B;
+} hw_mcg_sc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCG_SC register
+ */
+//@{
+#define HW_MCG_SC_ADDR (REGS_MCG_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCG_SC (*(__IO hw_mcg_sc_t *) HW_MCG_SC_ADDR)
+#define HW_MCG_SC_RD() (HW_MCG_SC.U)
+#define HW_MCG_SC_WR(v) (HW_MCG_SC.U = (v))
+#define HW_MCG_SC_SET(v) (HW_MCG_SC_WR(HW_MCG_SC_RD() | (v)))
+#define HW_MCG_SC_CLR(v) (HW_MCG_SC_WR(HW_MCG_SC_RD() & ~(v)))
+#define HW_MCG_SC_TOG(v) (HW_MCG_SC_WR(HW_MCG_SC_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCG_SC bitfields
+ */
+
+/*!
+ * @name Register MCG_SC, field LOCS0[0] (W1C)
+ *
+ * The LOCS0 indicates when a loss of OSC0 reference clock has occurred. The
+ * LOCS0 bit only has an effect when CME0 is set. This bit is cleared by writing a
+ * logic 1 to it when set.
+ *
+ * Values:
+ * - 0 - Loss of OSC0 has not occurred.
+ * - 1 - Loss of OSC0 has occurred.
+ */
+//@{
+#define BP_MCG_SC_LOCS0 (0U) //!< Bit position for MCG_SC_LOCS0.
+#define BM_MCG_SC_LOCS0 (0x01U) //!< Bit mask for MCG_SC_LOCS0.
+#define BS_MCG_SC_LOCS0 (1U) //!< Bit field size in bits for MCG_SC_LOCS0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_SC_LOCS0 field.
+#define BR_MCG_SC_LOCS0 (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_LOCS0))
+#endif
+
+//! @brief Format value for bitfield MCG_SC_LOCS0.
+#define BF_MCG_SC_LOCS0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_LOCS0), uint8_t) & BM_MCG_SC_LOCS0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LOCS0 field to a new value.
+#define BW_MCG_SC_LOCS0(v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_LOCS0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_SC, field FCRDIV[3:1] (RW)
+ *
+ * Selects the amount to divide down the fast internal reference clock. The
+ * resulting frequency will be in the range 31.25 kHz to 4 MHz (Note: Changing the
+ * divider when the Fast IRC is enabled is not supported).
+ *
+ * Values:
+ * - 000 - Divide Factor is 1
+ * - 001 - Divide Factor is 2.
+ * - 010 - Divide Factor is 4.
+ * - 011 - Divide Factor is 8.
+ * - 100 - Divide Factor is 16
+ * - 101 - Divide Factor is 32
+ * - 110 - Divide Factor is 64
+ * - 111 - Divide Factor is 128.
+ */
+//@{
+#define BP_MCG_SC_FCRDIV (1U) //!< Bit position for MCG_SC_FCRDIV.
+#define BM_MCG_SC_FCRDIV (0x0EU) //!< Bit mask for MCG_SC_FCRDIV.
+#define BS_MCG_SC_FCRDIV (3U) //!< Bit field size in bits for MCG_SC_FCRDIV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_SC_FCRDIV field.
+#define BR_MCG_SC_FCRDIV (HW_MCG_SC.B.FCRDIV)
+#endif
+
+//! @brief Format value for bitfield MCG_SC_FCRDIV.
+#define BF_MCG_SC_FCRDIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_FCRDIV), uint8_t) & BM_MCG_SC_FCRDIV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FCRDIV field to a new value.
+#define BW_MCG_SC_FCRDIV(v) (HW_MCG_SC_WR((HW_MCG_SC_RD() & ~BM_MCG_SC_FCRDIV) | BF_MCG_SC_FCRDIV(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_SC, field FLTPRSRV[4] (RW)
+ *
+ * This bit will prevent the FLL filter values from resetting allowing the FLL
+ * output frequency to remain the same during clock mode changes where the FLL/DCO
+ * output is still valid. (Note: This requires that the FLL reference frequency
+ * to remain the same as what it was prior to the new clock mode switch.
+ * Otherwise FLL filter and frequency values will change.)
+ *
+ * Values:
+ * - 0 - FLL filter and FLL frequency will reset on changes to currect clock
+ * mode.
+ * - 1 - Fll filter and FLL frequency retain their previous values during new
+ * clock mode change.
+ */
+//@{
+#define BP_MCG_SC_FLTPRSRV (4U) //!< Bit position for MCG_SC_FLTPRSRV.
+#define BM_MCG_SC_FLTPRSRV (0x10U) //!< Bit mask for MCG_SC_FLTPRSRV.
+#define BS_MCG_SC_FLTPRSRV (1U) //!< Bit field size in bits for MCG_SC_FLTPRSRV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_SC_FLTPRSRV field.
+#define BR_MCG_SC_FLTPRSRV (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_FLTPRSRV))
+#endif
+
+//! @brief Format value for bitfield MCG_SC_FLTPRSRV.
+#define BF_MCG_SC_FLTPRSRV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_FLTPRSRV), uint8_t) & BM_MCG_SC_FLTPRSRV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FLTPRSRV field to a new value.
+#define BW_MCG_SC_FLTPRSRV(v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_FLTPRSRV) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_SC, field ATMF[5] (RW)
+ *
+ * Fail flag for the Automatic Trim Machine (ATM). This bit asserts when the
+ * Automatic Trim Machine is enabled, ATME=1, and a write to the C1, C3, C4, and SC
+ * registers is detected or the MCG enters into any Stop mode. A write to ATMF
+ * clears the flag.
+ *
+ * Values:
+ * - 0 - Automatic Trim Machine completed normally.
+ * - 1 - Automatic Trim Machine failed.
+ */
+//@{
+#define BP_MCG_SC_ATMF (5U) //!< Bit position for MCG_SC_ATMF.
+#define BM_MCG_SC_ATMF (0x20U) //!< Bit mask for MCG_SC_ATMF.
+#define BS_MCG_SC_ATMF (1U) //!< Bit field size in bits for MCG_SC_ATMF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_SC_ATMF field.
+#define BR_MCG_SC_ATMF (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATMF))
+#endif
+
+//! @brief Format value for bitfield MCG_SC_ATMF.
+#define BF_MCG_SC_ATMF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_ATMF), uint8_t) & BM_MCG_SC_ATMF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ATMF field to a new value.
+#define BW_MCG_SC_ATMF(v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATMF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_SC, field ATMS[6] (RW)
+ *
+ * Selects the IRCS clock for Auto Trim Test.
+ *
+ * Values:
+ * - 0 - 32 kHz Internal Reference Clock selected.
+ * - 1 - 4 MHz Internal Reference Clock selected.
+ */
+//@{
+#define BP_MCG_SC_ATMS (6U) //!< Bit position for MCG_SC_ATMS.
+#define BM_MCG_SC_ATMS (0x40U) //!< Bit mask for MCG_SC_ATMS.
+#define BS_MCG_SC_ATMS (1U) //!< Bit field size in bits for MCG_SC_ATMS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_SC_ATMS field.
+#define BR_MCG_SC_ATMS (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATMS))
+#endif
+
+//! @brief Format value for bitfield MCG_SC_ATMS.
+#define BF_MCG_SC_ATMS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_ATMS), uint8_t) & BM_MCG_SC_ATMS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ATMS field to a new value.
+#define BW_MCG_SC_ATMS(v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATMS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_SC, field ATME[7] (RW)
+ *
+ * Enables the Auto Trim Machine to start automatically trimming the selected
+ * Internal Reference Clock. ATME deasserts after the Auto Trim Machine has
+ * completed trimming all trim bits of the IRCS clock selected by the ATMS bit. Writing
+ * to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim
+ * operation and clears this bit.
+ *
+ * Values:
+ * - 0 - Auto Trim Machine disabled.
+ * - 1 - Auto Trim Machine enabled.
+ */
+//@{
+#define BP_MCG_SC_ATME (7U) //!< Bit position for MCG_SC_ATME.
+#define BM_MCG_SC_ATME (0x80U) //!< Bit mask for MCG_SC_ATME.
+#define BS_MCG_SC_ATME (1U) //!< Bit field size in bits for MCG_SC_ATME.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_SC_ATME field.
+#define BR_MCG_SC_ATME (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATME))
+#endif
+
+//! @brief Format value for bitfield MCG_SC_ATME.
+#define BF_MCG_SC_ATME(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_SC_ATME), uint8_t) & BM_MCG_SC_ATME)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ATME field to a new value.
+#define BW_MCG_SC_ATME(v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR, BP_MCG_SC_ATME) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_mcg_atcvh
+{
+ uint8_t U;
+ struct _hw_mcg_atcvh_bitfields
+ {
+ uint8_t ATCVH : 8; //!< [7:0] ATM Compare Value High
+ } B;
+} hw_mcg_atcvh_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCG_ATCVH register
+ */
+//@{
+#define HW_MCG_ATCVH_ADDR (REGS_MCG_BASE + 0xAU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCG_ATCVH (*(__IO hw_mcg_atcvh_t *) HW_MCG_ATCVH_ADDR)
+#define HW_MCG_ATCVH_RD() (HW_MCG_ATCVH.U)
+#define HW_MCG_ATCVH_WR(v) (HW_MCG_ATCVH.U = (v))
+#define HW_MCG_ATCVH_SET(v) (HW_MCG_ATCVH_WR(HW_MCG_ATCVH_RD() | (v)))
+#define HW_MCG_ATCVH_CLR(v) (HW_MCG_ATCVH_WR(HW_MCG_ATCVH_RD() & ~(v)))
+#define HW_MCG_ATCVH_TOG(v) (HW_MCG_ATCVH_WR(HW_MCG_ATCVH_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCG_ATCVH bitfields
+ */
+
+/*!
+ * @name Register MCG_ATCVH, field ATCVH[7:0] (RW)
+ *
+ * Values are used by Auto Trim Machine to compare and adjust Internal Reference
+ * trim values during ATM SAR conversion.
+ */
+//@{
+#define BP_MCG_ATCVH_ATCVH (0U) //!< Bit position for MCG_ATCVH_ATCVH.
+#define BM_MCG_ATCVH_ATCVH (0xFFU) //!< Bit mask for MCG_ATCVH_ATCVH.
+#define BS_MCG_ATCVH_ATCVH (8U) //!< Bit field size in bits for MCG_ATCVH_ATCVH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_ATCVH_ATCVH field.
+#define BR_MCG_ATCVH_ATCVH (HW_MCG_ATCVH.U)
+#endif
+
+//! @brief Format value for bitfield MCG_ATCVH_ATCVH.
+#define BF_MCG_ATCVH_ATCVH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_ATCVH_ATCVH), uint8_t) & BM_MCG_ATCVH_ATCVH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ATCVH field to a new value.
+#define BW_MCG_ATCVH_ATCVH(v) (HW_MCG_ATCVH_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_mcg_atcvl
+{
+ uint8_t U;
+ struct _hw_mcg_atcvl_bitfields
+ {
+ uint8_t ATCVL : 8; //!< [7:0] ATM Compare Value Low
+ } B;
+} hw_mcg_atcvl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCG_ATCVL register
+ */
+//@{
+#define HW_MCG_ATCVL_ADDR (REGS_MCG_BASE + 0xBU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCG_ATCVL (*(__IO hw_mcg_atcvl_t *) HW_MCG_ATCVL_ADDR)
+#define HW_MCG_ATCVL_RD() (HW_MCG_ATCVL.U)
+#define HW_MCG_ATCVL_WR(v) (HW_MCG_ATCVL.U = (v))
+#define HW_MCG_ATCVL_SET(v) (HW_MCG_ATCVL_WR(HW_MCG_ATCVL_RD() | (v)))
+#define HW_MCG_ATCVL_CLR(v) (HW_MCG_ATCVL_WR(HW_MCG_ATCVL_RD() & ~(v)))
+#define HW_MCG_ATCVL_TOG(v) (HW_MCG_ATCVL_WR(HW_MCG_ATCVL_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCG_ATCVL bitfields
+ */
+
+/*!
+ * @name Register MCG_ATCVL, field ATCVL[7:0] (RW)
+ *
+ * Values are used by Auto Trim Machine to compare and adjust Internal Reference
+ * trim values during ATM SAR conversion.
+ */
+//@{
+#define BP_MCG_ATCVL_ATCVL (0U) //!< Bit position for MCG_ATCVL_ATCVL.
+#define BM_MCG_ATCVL_ATCVL (0xFFU) //!< Bit mask for MCG_ATCVL_ATCVL.
+#define BS_MCG_ATCVL_ATCVL (8U) //!< Bit field size in bits for MCG_ATCVL_ATCVL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_ATCVL_ATCVL field.
+#define BR_MCG_ATCVL_ATCVL (HW_MCG_ATCVL.U)
+#endif
+
+//! @brief Format value for bitfield MCG_ATCVL_ATCVL.
+#define BF_MCG_ATCVL_ATCVL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_ATCVL_ATCVL), uint8_t) & BM_MCG_ATCVL_ATCVL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ATCVL field to a new value.
+#define BW_MCG_ATCVL_ATCVL(v) (HW_MCG_ATCVL_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCG_C7 - MCG Control 7 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCG_C7 - MCG Control 7 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_mcg_c7
+{
+ uint8_t U;
+ struct _hw_mcg_c7_bitfields
+ {
+ uint8_t OSCSEL : 2; //!< [1:0] MCG OSC Clock Select
+ uint8_t RESERVED0 : 6; //!< [7:2]
+ } B;
+} hw_mcg_c7_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCG_C7 register
+ */
+//@{
+#define HW_MCG_C7_ADDR (REGS_MCG_BASE + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCG_C7 (*(__IO hw_mcg_c7_t *) HW_MCG_C7_ADDR)
+#define HW_MCG_C7_RD() (HW_MCG_C7.U)
+#define HW_MCG_C7_WR(v) (HW_MCG_C7.U = (v))
+#define HW_MCG_C7_SET(v) (HW_MCG_C7_WR(HW_MCG_C7_RD() | (v)))
+#define HW_MCG_C7_CLR(v) (HW_MCG_C7_WR(HW_MCG_C7_RD() & ~(v)))
+#define HW_MCG_C7_TOG(v) (HW_MCG_C7_WR(HW_MCG_C7_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCG_C7 bitfields
+ */
+
+/*!
+ * @name Register MCG_C7, field OSCSEL[1:0] (RW)
+ *
+ * Selects the MCG FLL external reference clock
+ *
+ * Values:
+ * - 00 - Selects Oscillator (OSCCLK0).
+ * - 01 - Selects 32 kHz RTC Oscillator.
+ * - 10 - Selects Oscillator (OSCCLK1).
+ * - 11 - RESERVED
+ */
+//@{
+#define BP_MCG_C7_OSCSEL (0U) //!< Bit position for MCG_C7_OSCSEL.
+#define BM_MCG_C7_OSCSEL (0x03U) //!< Bit mask for MCG_C7_OSCSEL.
+#define BS_MCG_C7_OSCSEL (2U) //!< Bit field size in bits for MCG_C7_OSCSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C7_OSCSEL field.
+#define BR_MCG_C7_OSCSEL (HW_MCG_C7.B.OSCSEL)
+#endif
+
+//! @brief Format value for bitfield MCG_C7_OSCSEL.
+#define BF_MCG_C7_OSCSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C7_OSCSEL), uint8_t) & BM_MCG_C7_OSCSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OSCSEL field to a new value.
+#define BW_MCG_C7_OSCSEL(v) (HW_MCG_C7_WR((HW_MCG_C7_RD() & ~BM_MCG_C7_OSCSEL) | BF_MCG_C7_OSCSEL(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCG_C8 - MCG Control 8 Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCG_C8 - MCG Control 8 Register (RW)
+ *
+ * Reset value: 0x80U
+ */
+typedef union _hw_mcg_c8
+{
+ uint8_t U;
+ struct _hw_mcg_c8_bitfields
+ {
+ uint8_t LOCS1 : 1; //!< [0] RTC Loss of Clock Status
+ uint8_t RESERVED0 : 4; //!< [4:1]
+ uint8_t CME1 : 1; //!< [5] Clock Monitor Enable1
+ uint8_t LOLRE : 1; //!< [6] PLL Loss of Lock Reset Enable
+ uint8_t LOCRE1 : 1; //!< [7] Loss of Clock Reset Enable
+ } B;
+} hw_mcg_c8_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCG_C8 register
+ */
+//@{
+#define HW_MCG_C8_ADDR (REGS_MCG_BASE + 0xDU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCG_C8 (*(__IO hw_mcg_c8_t *) HW_MCG_C8_ADDR)
+#define HW_MCG_C8_RD() (HW_MCG_C8.U)
+#define HW_MCG_C8_WR(v) (HW_MCG_C8.U = (v))
+#define HW_MCG_C8_SET(v) (HW_MCG_C8_WR(HW_MCG_C8_RD() | (v)))
+#define HW_MCG_C8_CLR(v) (HW_MCG_C8_WR(HW_MCG_C8_RD() & ~(v)))
+#define HW_MCG_C8_TOG(v) (HW_MCG_C8_WR(HW_MCG_C8_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCG_C8 bitfields
+ */
+
+/*!
+ * @name Register MCG_C8, field LOCS1[0] (W1C)
+ *
+ * This bit indicates when a loss of clock has occurred. This bit is cleared by
+ * writing a logic 1 to it when set.
+ *
+ * Values:
+ * - 0 - Loss of RTC has not occur.
+ * - 1 - Loss of RTC has occur
+ */
+//@{
+#define BP_MCG_C8_LOCS1 (0U) //!< Bit position for MCG_C8_LOCS1.
+#define BM_MCG_C8_LOCS1 (0x01U) //!< Bit mask for MCG_C8_LOCS1.
+#define BS_MCG_C8_LOCS1 (1U) //!< Bit field size in bits for MCG_C8_LOCS1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C8_LOCS1 field.
+#define BR_MCG_C8_LOCS1 (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOCS1))
+#endif
+
+//! @brief Format value for bitfield MCG_C8_LOCS1.
+#define BF_MCG_C8_LOCS1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C8_LOCS1), uint8_t) & BM_MCG_C8_LOCS1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LOCS1 field to a new value.
+#define BW_MCG_C8_LOCS1(v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOCS1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C8, field CME1[5] (RW)
+ *
+ * Enables the loss of clock monitoring circuit for the output of the RTC
+ * external reference clock. The LOCRE1 bit will determine whether an interrupt or a
+ * reset request is generated following a loss of RTC clock indication. The CME1
+ * bit should be set to a logic 1 when the MCG is in an operational mode that uses
+ * the RTC as its external reference clock or if the RTC is operational. CME1 bit
+ * must be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
+ * reset request may occur when in Stop mode. CME1 should also be set to a logic 0
+ * before entering VLPR or VLPW power modes.
+ *
+ * Values:
+ * - 0 - External clock monitor is disabled for RTC clock.
+ * - 1 - External clock monitor is enabled for RTC clock.
+ */
+//@{
+#define BP_MCG_C8_CME1 (5U) //!< Bit position for MCG_C8_CME1.
+#define BM_MCG_C8_CME1 (0x20U) //!< Bit mask for MCG_C8_CME1.
+#define BS_MCG_C8_CME1 (1U) //!< Bit field size in bits for MCG_C8_CME1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C8_CME1 field.
+#define BR_MCG_C8_CME1 (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_CME1))
+#endif
+
+//! @brief Format value for bitfield MCG_C8_CME1.
+#define BF_MCG_C8_CME1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C8_CME1), uint8_t) & BM_MCG_C8_CME1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CME1 field to a new value.
+#define BW_MCG_C8_CME1(v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_CME1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C8, field LOLRE[6] (RW)
+ *
+ * Determines if an interrupt or a reset request is made following a PLL loss of
+ * lock.
+ *
+ * Values:
+ * - 0 - Interrupt request is generated on a PLL loss of lock indication. The
+ * PLL loss of lock interrupt enable bit must also be set to generate the
+ * interrupt request.
+ * - 1 - Generate a reset request on a PLL loss of lock indication.
+ */
+//@{
+#define BP_MCG_C8_LOLRE (6U) //!< Bit position for MCG_C8_LOLRE.
+#define BM_MCG_C8_LOLRE (0x40U) //!< Bit mask for MCG_C8_LOLRE.
+#define BS_MCG_C8_LOLRE (1U) //!< Bit field size in bits for MCG_C8_LOLRE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C8_LOLRE field.
+#define BR_MCG_C8_LOLRE (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOLRE))
+#endif
+
+//! @brief Format value for bitfield MCG_C8_LOLRE.
+#define BF_MCG_C8_LOLRE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C8_LOLRE), uint8_t) & BM_MCG_C8_LOLRE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LOLRE field to a new value.
+#define BW_MCG_C8_LOLRE(v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOLRE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCG_C8, field LOCRE1[7] (RW)
+ *
+ * Determines if a interrupt or a reset request is made following a loss of RTC
+ * external reference clock. The LOCRE1 only has an affect when CME1 is set.
+ *
+ * Values:
+ * - 0 - Interrupt request is generated on a loss of RTC external reference
+ * clock.
+ * - 1 - Generate a reset request on a loss of RTC external reference clock
+ */
+//@{
+#define BP_MCG_C8_LOCRE1 (7U) //!< Bit position for MCG_C8_LOCRE1.
+#define BM_MCG_C8_LOCRE1 (0x80U) //!< Bit mask for MCG_C8_LOCRE1.
+#define BS_MCG_C8_LOCRE1 (1U) //!< Bit field size in bits for MCG_C8_LOCRE1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCG_C8_LOCRE1 field.
+#define BR_MCG_C8_LOCRE1 (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOCRE1))
+#endif
+
+//! @brief Format value for bitfield MCG_C8_LOCRE1.
+#define BF_MCG_C8_LOCRE1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_MCG_C8_LOCRE1), uint8_t) & BM_MCG_C8_LOCRE1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LOCRE1 field to a new value.
+#define BW_MCG_C8_LOCRE1(v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR, BP_MCG_C8_LOCRE1) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_mcg_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All MCG module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_mcg
+{
+ __IO hw_mcg_c1_t C1; //!< [0x0] MCG Control 1 Register
+ __IO hw_mcg_c2_t C2; //!< [0x1] MCG Control 2 Register
+ __IO hw_mcg_c3_t C3; //!< [0x2] MCG Control 3 Register
+ __IO hw_mcg_c4_t C4; //!< [0x3] MCG Control 4 Register
+ __IO hw_mcg_c5_t C5; //!< [0x4] MCG Control 5 Register
+ __IO hw_mcg_c6_t C6; //!< [0x5] MCG Control 6 Register
+ __IO hw_mcg_s_t S; //!< [0x6] MCG Status Register
+ uint8_t _reserved0[1];
+ __IO hw_mcg_sc_t SC; //!< [0x8] MCG Status and Control Register
+ uint8_t _reserved1[1];
+ __IO hw_mcg_atcvh_t ATCVH; //!< [0xA] MCG Auto Trim Compare Value High Register
+ __IO hw_mcg_atcvl_t ATCVL; //!< [0xB] MCG Auto Trim Compare Value Low Register
+ __IO hw_mcg_c7_t C7; //!< [0xC] MCG Control 7 Register
+ __IO hw_mcg_c8_t C8; //!< [0xD] MCG Control 8 Register
+} hw_mcg_t;
+#pragma pack()
+
+//! @brief Macro to access all MCG registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_MCG</code>.
+#define HW_MCG (*(hw_mcg_t *) REGS_MCG_BASE)
+#endif
+
+#endif // __HW_MCG_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_mcm.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,1164 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_MCM_REGISTERS_H__
+#define __HW_MCM_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 MCM
+ *
+ * Core Platform Miscellaneous Control Module
+ *
+ * Registers defined in this header file:
+ * - HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
+ * - HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
+ * - HW_MCM_CR - Control Register
+ * - HW_MCM_ISR - Interrupt Status Register
+ * - HW_MCM_ETBCC - ETB Counter Control register
+ * - HW_MCM_ETBRL - ETB Reload register
+ * - HW_MCM_ETBCNT - ETB Counter Value register
+ * - HW_MCM_PID - Process ID register
+ *
+ * - hw_mcm_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_MCM_BASE
+#define HW_MCM_INSTANCE_COUNT (1U) //!< Number of instances of the MCM module.
+#define REGS_MCM_BASE (0xE0080000U) //!< Base address for MCM.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration (RO)
+ *
+ * Reset value: 0x001FU
+ *
+ * PLASC is a 16-bit read-only register identifying the presence/absence of bus
+ * slave connections to the device's crossbar switch.
+ */
+typedef union _hw_mcm_plasc
+{
+ uint16_t U;
+ struct _hw_mcm_plasc_bitfields
+ {
+ uint16_t ASC : 8; //!< [7:0] Each bit in the ASC field indicates
+ //! whether there is a corresponding connection to the crossbar switch's slave
+ //! input port.
+ uint16_t RESERVED0 : 8; //!< [15:8]
+ } B;
+} hw_mcm_plasc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCM_PLASC register
+ */
+//@{
+#define HW_MCM_PLASC_ADDR (REGS_MCM_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCM_PLASC (*(__I hw_mcm_plasc_t *) HW_MCM_PLASC_ADDR)
+#define HW_MCM_PLASC_RD() (HW_MCM_PLASC.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCM_PLASC bitfields
+ */
+
+/*!
+ * @name Register MCM_PLASC, field ASC[7:0] (RO)
+ *
+ * Values:
+ * - 0 - A bus slave connection to AXBS input port n is absent
+ * - 1 - A bus slave connection to AXBS input port n is present
+ */
+//@{
+#define BP_MCM_PLASC_ASC (0U) //!< Bit position for MCM_PLASC_ASC.
+#define BM_MCM_PLASC_ASC (0x00FFU) //!< Bit mask for MCM_PLASC_ASC.
+#define BS_MCM_PLASC_ASC (8U) //!< Bit field size in bits for MCM_PLASC_ASC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_PLASC_ASC field.
+#define BR_MCM_PLASC_ASC (HW_MCM_PLASC.B.ASC)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration (RO)
+ *
+ * Reset value: 0x0037U
+ *
+ * PLAMC is a 16-bit read-only register identifying the presence/absence of bus
+ * master connections to the device's crossbar switch.
+ */
+typedef union _hw_mcm_plamc
+{
+ uint16_t U;
+ struct _hw_mcm_plamc_bitfields
+ {
+ uint16_t AMC : 8; //!< [7:0] Each bit in the AMC field indicates
+ //! whether there is a corresponding connection to the AXBS master input port.
+ uint16_t RESERVED0 : 8; //!< [15:8]
+ } B;
+} hw_mcm_plamc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCM_PLAMC register
+ */
+//@{
+#define HW_MCM_PLAMC_ADDR (REGS_MCM_BASE + 0xAU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCM_PLAMC (*(__I hw_mcm_plamc_t *) HW_MCM_PLAMC_ADDR)
+#define HW_MCM_PLAMC_RD() (HW_MCM_PLAMC.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCM_PLAMC bitfields
+ */
+
+/*!
+ * @name Register MCM_PLAMC, field AMC[7:0] (RO)
+ *
+ * Values:
+ * - 0 - A bus master connection to AXBS input port n is absent
+ * - 1 - A bus master connection to AXBS input port n is present
+ */
+//@{
+#define BP_MCM_PLAMC_AMC (0U) //!< Bit position for MCM_PLAMC_AMC.
+#define BM_MCM_PLAMC_AMC (0x00FFU) //!< Bit mask for MCM_PLAMC_AMC.
+#define BS_MCM_PLAMC_AMC (8U) //!< Bit field size in bits for MCM_PLAMC_AMC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_PLAMC_AMC field.
+#define BR_MCM_PLAMC_AMC (HW_MCM_PLAMC.B.AMC)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCM_CR - Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCM_CR - Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * CR defines the arbitration and protection schemes for the two system RAM
+ * arrays.
+ */
+typedef union _hw_mcm_cr
+{
+ uint32_t U;
+ struct _hw_mcm_cr_bitfields
+ {
+ uint32_t RESERVED0 : 24; //!< [23:0]
+ uint32_t SRAMUAP : 2; //!< [25:24] SRAM_U arbitration priority
+ uint32_t SRAMUWP : 1; //!< [26] SRAM_U write protect
+ uint32_t RESERVED1 : 1; //!< [27]
+ uint32_t SRAMLAP : 2; //!< [29:28] SRAM_L arbitration priority
+ uint32_t SRAMLWP : 1; //!< [30] SRAM_L Write Protect
+ uint32_t RESERVED2 : 1; //!< [31]
+ } B;
+} hw_mcm_cr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCM_CR register
+ */
+//@{
+#define HW_MCM_CR_ADDR (REGS_MCM_BASE + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCM_CR (*(__IO hw_mcm_cr_t *) HW_MCM_CR_ADDR)
+#define HW_MCM_CR_RD() (HW_MCM_CR.U)
+#define HW_MCM_CR_WR(v) (HW_MCM_CR.U = (v))
+#define HW_MCM_CR_SET(v) (HW_MCM_CR_WR(HW_MCM_CR_RD() | (v)))
+#define HW_MCM_CR_CLR(v) (HW_MCM_CR_WR(HW_MCM_CR_RD() & ~(v)))
+#define HW_MCM_CR_TOG(v) (HW_MCM_CR_WR(HW_MCM_CR_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCM_CR bitfields
+ */
+
+/*!
+ * @name Register MCM_CR, field SRAMUAP[25:24] (RW)
+ *
+ * Defines the arbitration scheme and priority for the processor and SRAM
+ * backdoor accesses to the SRAM_U array.
+ *
+ * Values:
+ * - 00 - Round robin
+ * - 01 - Special round robin (favors SRAM backoor accesses over the processor)
+ * - 10 - Fixed priority. Processor has highest, backdoor has lowest
+ * - 11 - Fixed priority. Backdoor has highest, processor has lowest
+ */
+//@{
+#define BP_MCM_CR_SRAMUAP (24U) //!< Bit position for MCM_CR_SRAMUAP.
+#define BM_MCM_CR_SRAMUAP (0x03000000U) //!< Bit mask for MCM_CR_SRAMUAP.
+#define BS_MCM_CR_SRAMUAP (2U) //!< Bit field size in bits for MCM_CR_SRAMUAP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_CR_SRAMUAP field.
+#define BR_MCM_CR_SRAMUAP (HW_MCM_CR.B.SRAMUAP)
+#endif
+
+//! @brief Format value for bitfield MCM_CR_SRAMUAP.
+#define BF_MCM_CR_SRAMUAP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_CR_SRAMUAP), uint32_t) & BM_MCM_CR_SRAMUAP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SRAMUAP field to a new value.
+#define BW_MCM_CR_SRAMUAP(v) (HW_MCM_CR_WR((HW_MCM_CR_RD() & ~BM_MCM_CR_SRAMUAP) | BF_MCM_CR_SRAMUAP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_CR, field SRAMUWP[26] (RW)
+ *
+ * When this bit is set, writes to SRAM_U array generates a bus error.
+ */
+//@{
+#define BP_MCM_CR_SRAMUWP (26U) //!< Bit position for MCM_CR_SRAMUWP.
+#define BM_MCM_CR_SRAMUWP (0x04000000U) //!< Bit mask for MCM_CR_SRAMUWP.
+#define BS_MCM_CR_SRAMUWP (1U) //!< Bit field size in bits for MCM_CR_SRAMUWP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_CR_SRAMUWP field.
+#define BR_MCM_CR_SRAMUWP (BITBAND_ACCESS32(HW_MCM_CR_ADDR, BP_MCM_CR_SRAMUWP))
+#endif
+
+//! @brief Format value for bitfield MCM_CR_SRAMUWP.
+#define BF_MCM_CR_SRAMUWP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_CR_SRAMUWP), uint32_t) & BM_MCM_CR_SRAMUWP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SRAMUWP field to a new value.
+#define BW_MCM_CR_SRAMUWP(v) (BITBAND_ACCESS32(HW_MCM_CR_ADDR, BP_MCM_CR_SRAMUWP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_CR, field SRAMLAP[29:28] (RW)
+ *
+ * Defines the arbitration scheme and priority for the processor and SRAM
+ * backdoor accesses to the SRAM_L array.
+ *
+ * Values:
+ * - 00 - Round robin
+ * - 01 - Special round robin (favors SRAM backoor accesses over the processor)
+ * - 10 - Fixed priority. Processor has highest, backdoor has lowest
+ * - 11 - Fixed priority. Backdoor has highest, processor has lowest
+ */
+//@{
+#define BP_MCM_CR_SRAMLAP (28U) //!< Bit position for MCM_CR_SRAMLAP.
+#define BM_MCM_CR_SRAMLAP (0x30000000U) //!< Bit mask for MCM_CR_SRAMLAP.
+#define BS_MCM_CR_SRAMLAP (2U) //!< Bit field size in bits for MCM_CR_SRAMLAP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_CR_SRAMLAP field.
+#define BR_MCM_CR_SRAMLAP (HW_MCM_CR.B.SRAMLAP)
+#endif
+
+//! @brief Format value for bitfield MCM_CR_SRAMLAP.
+#define BF_MCM_CR_SRAMLAP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_CR_SRAMLAP), uint32_t) & BM_MCM_CR_SRAMLAP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SRAMLAP field to a new value.
+#define BW_MCM_CR_SRAMLAP(v) (HW_MCM_CR_WR((HW_MCM_CR_RD() & ~BM_MCM_CR_SRAMLAP) | BF_MCM_CR_SRAMLAP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_CR, field SRAMLWP[30] (RW)
+ *
+ * When this bit is set, writes to SRAM_L array generates a bus error.
+ */
+//@{
+#define BP_MCM_CR_SRAMLWP (30U) //!< Bit position for MCM_CR_SRAMLWP.
+#define BM_MCM_CR_SRAMLWP (0x40000000U) //!< Bit mask for MCM_CR_SRAMLWP.
+#define BS_MCM_CR_SRAMLWP (1U) //!< Bit field size in bits for MCM_CR_SRAMLWP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_CR_SRAMLWP field.
+#define BR_MCM_CR_SRAMLWP (BITBAND_ACCESS32(HW_MCM_CR_ADDR, BP_MCM_CR_SRAMLWP))
+#endif
+
+//! @brief Format value for bitfield MCM_CR_SRAMLWP.
+#define BF_MCM_CR_SRAMLWP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_CR_SRAMLWP), uint32_t) & BM_MCM_CR_SRAMLWP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SRAMLWP field to a new value.
+#define BW_MCM_CR_SRAMLWP(v) (BITBAND_ACCESS32(HW_MCM_CR_ADDR, BP_MCM_CR_SRAMLWP) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCM_ISR - Interrupt Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCM_ISR - Interrupt Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_mcm_isr
+{
+ uint32_t U;
+ struct _hw_mcm_isr_bitfields
+ {
+ uint32_t RESERVED0 : 1; //!< [0]
+ uint32_t IRQ : 1; //!< [1] Normal Interrupt Pending
+ uint32_t NMI : 1; //!< [2] Non-maskable Interrupt Pending
+ uint32_t DHREQ : 1; //!< [3] Debug Halt Request Indicator
+ uint32_t RESERVED1 : 4; //!< [7:4]
+ uint32_t FIOC : 1; //!< [8] FPU invalid operation interrupt status
+ uint32_t FDZC : 1; //!< [9] FPU divide-by-zero interrupt status
+ uint32_t FOFC : 1; //!< [10] FPU overflow interrupt status
+ uint32_t FUFC : 1; //!< [11] FPU underflow interrupt status
+ uint32_t FIXC : 1; //!< [12] FPU inexact interrupt status
+ uint32_t RESERVED2 : 2; //!< [14:13]
+ uint32_t FIDC : 1; //!< [15] FPU input denormal interrupt status
+ uint32_t RESERVED3 : 8; //!< [23:16]
+ uint32_t FIOCE : 1; //!< [24] FPU invalid operation interrupt enable
+ uint32_t FDZCE : 1; //!< [25] FPU divide-by-zero interrupt enable
+ uint32_t FOFCE : 1; //!< [26] FPU overflow interrupt enable
+ uint32_t FUFCE : 1; //!< [27] FPU underflow interrupt enable
+ uint32_t FIXCE : 1; //!< [28] FPU inexact interrupt enable
+ uint32_t RESERVED4 : 2; //!< [30:29]
+ uint32_t FIDCE : 1; //!< [31] FPU input denormal interrupt enable
+ } B;
+} hw_mcm_isr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCM_ISR register
+ */
+//@{
+#define HW_MCM_ISR_ADDR (REGS_MCM_BASE + 0x10U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCM_ISR (*(__IO hw_mcm_isr_t *) HW_MCM_ISR_ADDR)
+#define HW_MCM_ISR_RD() (HW_MCM_ISR.U)
+#define HW_MCM_ISR_WR(v) (HW_MCM_ISR.U = (v))
+#define HW_MCM_ISR_SET(v) (HW_MCM_ISR_WR(HW_MCM_ISR_RD() | (v)))
+#define HW_MCM_ISR_CLR(v) (HW_MCM_ISR_WR(HW_MCM_ISR_RD() & ~(v)))
+#define HW_MCM_ISR_TOG(v) (HW_MCM_ISR_WR(HW_MCM_ISR_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCM_ISR bitfields
+ */
+
+/*!
+ * @name Register MCM_ISR, field IRQ[1] (W1C)
+ *
+ * If ETBCC[RSPT] is set to 01b, this bit is set when the ETB counter expires.
+ *
+ * Values:
+ * - 0 - No pending interrupt
+ * - 1 - Due to the ETB counter expiring, a normal interrupt is pending
+ */
+//@{
+#define BP_MCM_ISR_IRQ (1U) //!< Bit position for MCM_ISR_IRQ.
+#define BM_MCM_ISR_IRQ (0x00000002U) //!< Bit mask for MCM_ISR_IRQ.
+#define BS_MCM_ISR_IRQ (1U) //!< Bit field size in bits for MCM_ISR_IRQ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_IRQ field.
+#define BR_MCM_ISR_IRQ (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_IRQ))
+#endif
+
+//! @brief Format value for bitfield MCM_ISR_IRQ.
+#define BF_MCM_ISR_IRQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_IRQ), uint32_t) & BM_MCM_ISR_IRQ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IRQ field to a new value.
+#define BW_MCM_ISR_IRQ(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_IRQ) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ISR, field NMI[2] (W1C)
+ *
+ * If ETBCC[RSPT] is set to 10b, this bit is set when the ETB counter expires.
+ *
+ * Values:
+ * - 0 - No pending NMI
+ * - 1 - Due to the ETB counter expiring, an NMI is pending
+ */
+//@{
+#define BP_MCM_ISR_NMI (2U) //!< Bit position for MCM_ISR_NMI.
+#define BM_MCM_ISR_NMI (0x00000004U) //!< Bit mask for MCM_ISR_NMI.
+#define BS_MCM_ISR_NMI (1U) //!< Bit field size in bits for MCM_ISR_NMI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_NMI field.
+#define BR_MCM_ISR_NMI (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_NMI))
+#endif
+
+//! @brief Format value for bitfield MCM_ISR_NMI.
+#define BF_MCM_ISR_NMI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_NMI), uint32_t) & BM_MCM_ISR_NMI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NMI field to a new value.
+#define BW_MCM_ISR_NMI(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_NMI) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ISR, field DHREQ[3] (RO)
+ *
+ * Indicates that a debug halt request is initiated due to a ETB counter
+ * expiration, ETBCC[2:0] = 3b111 & ETBCV[10:0] = 11h0. This bit is cleared when the
+ * counter is disabled or when the ETB counter is reloaded.
+ *
+ * Values:
+ * - 0 - No debug halt request
+ * - 1 - Debug halt request initiated
+ */
+//@{
+#define BP_MCM_ISR_DHREQ (3U) //!< Bit position for MCM_ISR_DHREQ.
+#define BM_MCM_ISR_DHREQ (0x00000008U) //!< Bit mask for MCM_ISR_DHREQ.
+#define BS_MCM_ISR_DHREQ (1U) //!< Bit field size in bits for MCM_ISR_DHREQ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_DHREQ field.
+#define BR_MCM_ISR_DHREQ (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_DHREQ))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ISR, field FIOC[8] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[IOC] bit and signals an
+ * illegal operation has been detected in the processor's FPU. Once set, this bit
+ * remains set until software clears the FPSCR[IOC] bit.
+ *
+ * Values:
+ * - 0 - No interrupt
+ * - 1 - Interrupt occurred
+ */
+//@{
+#define BP_MCM_ISR_FIOC (8U) //!< Bit position for MCM_ISR_FIOC.
+#define BM_MCM_ISR_FIOC (0x00000100U) //!< Bit mask for MCM_ISR_FIOC.
+#define BS_MCM_ISR_FIOC (1U) //!< Bit field size in bits for MCM_ISR_FIOC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_FIOC field.
+#define BR_MCM_ISR_FIOC (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIOC))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ISR, field FDZC[9] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[DZC] bit and signals a
+ * divide by zero has been detected in the processor's FPU. Once set, this bit remains
+ * set until software clears the FPSCR[DZC] bit.
+ *
+ * Values:
+ * - 0 - No interrupt
+ * - 1 - Interrupt occurred
+ */
+//@{
+#define BP_MCM_ISR_FDZC (9U) //!< Bit position for MCM_ISR_FDZC.
+#define BM_MCM_ISR_FDZC (0x00000200U) //!< Bit mask for MCM_ISR_FDZC.
+#define BS_MCM_ISR_FDZC (1U) //!< Bit field size in bits for MCM_ISR_FDZC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_FDZC field.
+#define BR_MCM_ISR_FDZC (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FDZC))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ISR, field FOFC[10] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[OFC] bit and signals an
+ * overflow has been detected in the processor's FPU. Once set, this bit remains set
+ * until software clears the FPSCR[OFC] bit.
+ *
+ * Values:
+ * - 0 - No interrupt
+ * - 1 - Interrupt occurred
+ */
+//@{
+#define BP_MCM_ISR_FOFC (10U) //!< Bit position for MCM_ISR_FOFC.
+#define BM_MCM_ISR_FOFC (0x00000400U) //!< Bit mask for MCM_ISR_FOFC.
+#define BS_MCM_ISR_FOFC (1U) //!< Bit field size in bits for MCM_ISR_FOFC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_FOFC field.
+#define BR_MCM_ISR_FOFC (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FOFC))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ISR, field FUFC[11] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[UFC] bit and signals an
+ * underflow has been detected in the processor's FPU. Once set, this bit remains set
+ * until software clears the FPSCR[UFC] bit.
+ *
+ * Values:
+ * - 0 - No interrupt
+ * - 1 - Interrupt occurred
+ */
+//@{
+#define BP_MCM_ISR_FUFC (11U) //!< Bit position for MCM_ISR_FUFC.
+#define BM_MCM_ISR_FUFC (0x00000800U) //!< Bit mask for MCM_ISR_FUFC.
+#define BS_MCM_ISR_FUFC (1U) //!< Bit field size in bits for MCM_ISR_FUFC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_FUFC field.
+#define BR_MCM_ISR_FUFC (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FUFC))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ISR, field FIXC[12] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[IXC] bit and signals an
+ * inexact number has been detected in the processor's FPU. Once set, this bit
+ * remains set until software clears the FPSCR[IXC] bit.
+ *
+ * Values:
+ * - 0 - No interrupt
+ * - 1 - Interrupt occurred
+ */
+//@{
+#define BP_MCM_ISR_FIXC (12U) //!< Bit position for MCM_ISR_FIXC.
+#define BM_MCM_ISR_FIXC (0x00001000U) //!< Bit mask for MCM_ISR_FIXC.
+#define BS_MCM_ISR_FIXC (1U) //!< Bit field size in bits for MCM_ISR_FIXC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_FIXC field.
+#define BR_MCM_ISR_FIXC (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIXC))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ISR, field FIDC[15] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[IDC] bit and signals input
+ * denormalized number has been detected in the processor's FPU. Once set, this
+ * bit remains set until software clears the FPSCR[IDC] bit.
+ *
+ * Values:
+ * - 0 - No interrupt
+ * - 1 - Interrupt occurred
+ */
+//@{
+#define BP_MCM_ISR_FIDC (15U) //!< Bit position for MCM_ISR_FIDC.
+#define BM_MCM_ISR_FIDC (0x00008000U) //!< Bit mask for MCM_ISR_FIDC.
+#define BS_MCM_ISR_FIDC (1U) //!< Bit field size in bits for MCM_ISR_FIDC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_FIDC field.
+#define BR_MCM_ISR_FIDC (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIDC))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ISR, field FIOCE[24] (RW)
+ *
+ * Values:
+ * - 0 - Disable interrupt
+ * - 1 - Enable interrupt
+ */
+//@{
+#define BP_MCM_ISR_FIOCE (24U) //!< Bit position for MCM_ISR_FIOCE.
+#define BM_MCM_ISR_FIOCE (0x01000000U) //!< Bit mask for MCM_ISR_FIOCE.
+#define BS_MCM_ISR_FIOCE (1U) //!< Bit field size in bits for MCM_ISR_FIOCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_FIOCE field.
+#define BR_MCM_ISR_FIOCE (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIOCE))
+#endif
+
+//! @brief Format value for bitfield MCM_ISR_FIOCE.
+#define BF_MCM_ISR_FIOCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FIOCE), uint32_t) & BM_MCM_ISR_FIOCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FIOCE field to a new value.
+#define BW_MCM_ISR_FIOCE(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIOCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ISR, field FDZCE[25] (RW)
+ *
+ * Values:
+ * - 0 - Disable interrupt
+ * - 1 - Enable interrupt
+ */
+//@{
+#define BP_MCM_ISR_FDZCE (25U) //!< Bit position for MCM_ISR_FDZCE.
+#define BM_MCM_ISR_FDZCE (0x02000000U) //!< Bit mask for MCM_ISR_FDZCE.
+#define BS_MCM_ISR_FDZCE (1U) //!< Bit field size in bits for MCM_ISR_FDZCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_FDZCE field.
+#define BR_MCM_ISR_FDZCE (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FDZCE))
+#endif
+
+//! @brief Format value for bitfield MCM_ISR_FDZCE.
+#define BF_MCM_ISR_FDZCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FDZCE), uint32_t) & BM_MCM_ISR_FDZCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FDZCE field to a new value.
+#define BW_MCM_ISR_FDZCE(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FDZCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ISR, field FOFCE[26] (RW)
+ *
+ * Values:
+ * - 0 - Disable interrupt
+ * - 1 - Enable interrupt
+ */
+//@{
+#define BP_MCM_ISR_FOFCE (26U) //!< Bit position for MCM_ISR_FOFCE.
+#define BM_MCM_ISR_FOFCE (0x04000000U) //!< Bit mask for MCM_ISR_FOFCE.
+#define BS_MCM_ISR_FOFCE (1U) //!< Bit field size in bits for MCM_ISR_FOFCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_FOFCE field.
+#define BR_MCM_ISR_FOFCE (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FOFCE))
+#endif
+
+//! @brief Format value for bitfield MCM_ISR_FOFCE.
+#define BF_MCM_ISR_FOFCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FOFCE), uint32_t) & BM_MCM_ISR_FOFCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FOFCE field to a new value.
+#define BW_MCM_ISR_FOFCE(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FOFCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ISR, field FUFCE[27] (RW)
+ *
+ * Values:
+ * - 0 - Disable interrupt
+ * - 1 - Enable interrupt
+ */
+//@{
+#define BP_MCM_ISR_FUFCE (27U) //!< Bit position for MCM_ISR_FUFCE.
+#define BM_MCM_ISR_FUFCE (0x08000000U) //!< Bit mask for MCM_ISR_FUFCE.
+#define BS_MCM_ISR_FUFCE (1U) //!< Bit field size in bits for MCM_ISR_FUFCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_FUFCE field.
+#define BR_MCM_ISR_FUFCE (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FUFCE))
+#endif
+
+//! @brief Format value for bitfield MCM_ISR_FUFCE.
+#define BF_MCM_ISR_FUFCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FUFCE), uint32_t) & BM_MCM_ISR_FUFCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FUFCE field to a new value.
+#define BW_MCM_ISR_FUFCE(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FUFCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ISR, field FIXCE[28] (RW)
+ *
+ * Values:
+ * - 0 - Disable interrupt
+ * - 1 - Enable interrupt
+ */
+//@{
+#define BP_MCM_ISR_FIXCE (28U) //!< Bit position for MCM_ISR_FIXCE.
+#define BM_MCM_ISR_FIXCE (0x10000000U) //!< Bit mask for MCM_ISR_FIXCE.
+#define BS_MCM_ISR_FIXCE (1U) //!< Bit field size in bits for MCM_ISR_FIXCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_FIXCE field.
+#define BR_MCM_ISR_FIXCE (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIXCE))
+#endif
+
+//! @brief Format value for bitfield MCM_ISR_FIXCE.
+#define BF_MCM_ISR_FIXCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FIXCE), uint32_t) & BM_MCM_ISR_FIXCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FIXCE field to a new value.
+#define BW_MCM_ISR_FIXCE(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIXCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ISR, field FIDCE[31] (RW)
+ *
+ * Values:
+ * - 0 - Disable interrupt
+ * - 1 - Enable interrupt
+ */
+//@{
+#define BP_MCM_ISR_FIDCE (31U) //!< Bit position for MCM_ISR_FIDCE.
+#define BM_MCM_ISR_FIDCE (0x80000000U) //!< Bit mask for MCM_ISR_FIDCE.
+#define BS_MCM_ISR_FIDCE (1U) //!< Bit field size in bits for MCM_ISR_FIDCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ISR_FIDCE field.
+#define BR_MCM_ISR_FIDCE (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIDCE))
+#endif
+
+//! @brief Format value for bitfield MCM_ISR_FIDCE.
+#define BF_MCM_ISR_FIDCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FIDCE), uint32_t) & BM_MCM_ISR_FIDCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FIDCE field to a new value.
+#define BW_MCM_ISR_FIDCE(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIDCE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCM_ETBCC - ETB Counter Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCM_ETBCC - ETB Counter Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_mcm_etbcc
+{
+ uint32_t U;
+ struct _hw_mcm_etbcc_bitfields
+ {
+ uint32_t CNTEN : 1; //!< [0] Counter Enable
+ uint32_t RSPT : 2; //!< [2:1] Response Type
+ uint32_t RLRQ : 1; //!< [3] Reload Request
+ uint32_t ETDIS : 1; //!< [4] ETM-To-TPIU Disable
+ uint32_t ITDIS : 1; //!< [5] ITM-To-TPIU Disable
+ uint32_t RESERVED0 : 26; //!< [31:6]
+ } B;
+} hw_mcm_etbcc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCM_ETBCC register
+ */
+//@{
+#define HW_MCM_ETBCC_ADDR (REGS_MCM_BASE + 0x14U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCM_ETBCC (*(__IO hw_mcm_etbcc_t *) HW_MCM_ETBCC_ADDR)
+#define HW_MCM_ETBCC_RD() (HW_MCM_ETBCC.U)
+#define HW_MCM_ETBCC_WR(v) (HW_MCM_ETBCC.U = (v))
+#define HW_MCM_ETBCC_SET(v) (HW_MCM_ETBCC_WR(HW_MCM_ETBCC_RD() | (v)))
+#define HW_MCM_ETBCC_CLR(v) (HW_MCM_ETBCC_WR(HW_MCM_ETBCC_RD() & ~(v)))
+#define HW_MCM_ETBCC_TOG(v) (HW_MCM_ETBCC_WR(HW_MCM_ETBCC_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCM_ETBCC bitfields
+ */
+
+/*!
+ * @name Register MCM_ETBCC, field CNTEN[0] (RW)
+ *
+ * Enables the ETB counter.
+ *
+ * Values:
+ * - 0 - ETB counter disabled
+ * - 1 - ETB counter enabled
+ */
+//@{
+#define BP_MCM_ETBCC_CNTEN (0U) //!< Bit position for MCM_ETBCC_CNTEN.
+#define BM_MCM_ETBCC_CNTEN (0x00000001U) //!< Bit mask for MCM_ETBCC_CNTEN.
+#define BS_MCM_ETBCC_CNTEN (1U) //!< Bit field size in bits for MCM_ETBCC_CNTEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ETBCC_CNTEN field.
+#define BR_MCM_ETBCC_CNTEN (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_CNTEN))
+#endif
+
+//! @brief Format value for bitfield MCM_ETBCC_CNTEN.
+#define BF_MCM_ETBCC_CNTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBCC_CNTEN), uint32_t) & BM_MCM_ETBCC_CNTEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CNTEN field to a new value.
+#define BW_MCM_ETBCC_CNTEN(v) (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_CNTEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ETBCC, field RSPT[2:1] (RW)
+ *
+ * Values:
+ * - 00 - No response when the ETB count expires
+ * - 01 - Generate a normal interrupt when the ETB count expires
+ * - 10 - Generate an NMI when the ETB count expires
+ * - 11 - Generate a debug halt when the ETB count expires
+ */
+//@{
+#define BP_MCM_ETBCC_RSPT (1U) //!< Bit position for MCM_ETBCC_RSPT.
+#define BM_MCM_ETBCC_RSPT (0x00000006U) //!< Bit mask for MCM_ETBCC_RSPT.
+#define BS_MCM_ETBCC_RSPT (2U) //!< Bit field size in bits for MCM_ETBCC_RSPT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ETBCC_RSPT field.
+#define BR_MCM_ETBCC_RSPT (HW_MCM_ETBCC.B.RSPT)
+#endif
+
+//! @brief Format value for bitfield MCM_ETBCC_RSPT.
+#define BF_MCM_ETBCC_RSPT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBCC_RSPT), uint32_t) & BM_MCM_ETBCC_RSPT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RSPT field to a new value.
+#define BW_MCM_ETBCC_RSPT(v) (HW_MCM_ETBCC_WR((HW_MCM_ETBCC_RD() & ~BM_MCM_ETBCC_RSPT) | BF_MCM_ETBCC_RSPT(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ETBCC, field RLRQ[3] (RW)
+ *
+ * Reloads the ETB packet counter with the MCM_ETBRL RELOAD value. If IRQ or NMI
+ * interrupts were enabled and an NMI or IRQ interrupt was generated on counter
+ * expiration, setting this bit clears the pending NMI or IRQ interrupt request.
+ * If debug halt was enabled and a debug halt request was asserted on counter
+ * expiration, setting this bit clears the debug halt request.
+ *
+ * Values:
+ * - 0 - No effect
+ * - 1 - Clears pending debug halt, NMI, or IRQ interrupt requests
+ */
+//@{
+#define BP_MCM_ETBCC_RLRQ (3U) //!< Bit position for MCM_ETBCC_RLRQ.
+#define BM_MCM_ETBCC_RLRQ (0x00000008U) //!< Bit mask for MCM_ETBCC_RLRQ.
+#define BS_MCM_ETBCC_RLRQ (1U) //!< Bit field size in bits for MCM_ETBCC_RLRQ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ETBCC_RLRQ field.
+#define BR_MCM_ETBCC_RLRQ (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_RLRQ))
+#endif
+
+//! @brief Format value for bitfield MCM_ETBCC_RLRQ.
+#define BF_MCM_ETBCC_RLRQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBCC_RLRQ), uint32_t) & BM_MCM_ETBCC_RLRQ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RLRQ field to a new value.
+#define BW_MCM_ETBCC_RLRQ(v) (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_RLRQ) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ETBCC, field ETDIS[4] (RW)
+ *
+ * Disables the trace path from ETM to TPIU.
+ *
+ * Values:
+ * - 0 - ETM-to-TPIU trace path enabled
+ * - 1 - ETM-to-TPIU trace path disabled
+ */
+//@{
+#define BP_MCM_ETBCC_ETDIS (4U) //!< Bit position for MCM_ETBCC_ETDIS.
+#define BM_MCM_ETBCC_ETDIS (0x00000010U) //!< Bit mask for MCM_ETBCC_ETDIS.
+#define BS_MCM_ETBCC_ETDIS (1U) //!< Bit field size in bits for MCM_ETBCC_ETDIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ETBCC_ETDIS field.
+#define BR_MCM_ETBCC_ETDIS (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_ETDIS))
+#endif
+
+//! @brief Format value for bitfield MCM_ETBCC_ETDIS.
+#define BF_MCM_ETBCC_ETDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBCC_ETDIS), uint32_t) & BM_MCM_ETBCC_ETDIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ETDIS field to a new value.
+#define BW_MCM_ETBCC_ETDIS(v) (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_ETDIS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MCM_ETBCC, field ITDIS[5] (RW)
+ *
+ * Disables the trace path from ITM to TPIU.
+ *
+ * Values:
+ * - 0 - ITM-to-TPIU trace path enabled
+ * - 1 - ITM-to-TPIU trace path disabled
+ */
+//@{
+#define BP_MCM_ETBCC_ITDIS (5U) //!< Bit position for MCM_ETBCC_ITDIS.
+#define BM_MCM_ETBCC_ITDIS (0x00000020U) //!< Bit mask for MCM_ETBCC_ITDIS.
+#define BS_MCM_ETBCC_ITDIS (1U) //!< Bit field size in bits for MCM_ETBCC_ITDIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ETBCC_ITDIS field.
+#define BR_MCM_ETBCC_ITDIS (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_ITDIS))
+#endif
+
+//! @brief Format value for bitfield MCM_ETBCC_ITDIS.
+#define BF_MCM_ETBCC_ITDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBCC_ITDIS), uint32_t) & BM_MCM_ETBCC_ITDIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ITDIS field to a new value.
+#define BW_MCM_ETBCC_ITDIS(v) (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_ITDIS) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCM_ETBRL - ETB Reload register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCM_ETBRL - ETB Reload register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_mcm_etbrl
+{
+ uint32_t U;
+ struct _hw_mcm_etbrl_bitfields
+ {
+ uint32_t RELOAD : 11; //!< [10:0] Byte Count Reload Value
+ uint32_t RESERVED0 : 21; //!< [31:11]
+ } B;
+} hw_mcm_etbrl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCM_ETBRL register
+ */
+//@{
+#define HW_MCM_ETBRL_ADDR (REGS_MCM_BASE + 0x18U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCM_ETBRL (*(__IO hw_mcm_etbrl_t *) HW_MCM_ETBRL_ADDR)
+#define HW_MCM_ETBRL_RD() (HW_MCM_ETBRL.U)
+#define HW_MCM_ETBRL_WR(v) (HW_MCM_ETBRL.U = (v))
+#define HW_MCM_ETBRL_SET(v) (HW_MCM_ETBRL_WR(HW_MCM_ETBRL_RD() | (v)))
+#define HW_MCM_ETBRL_CLR(v) (HW_MCM_ETBRL_WR(HW_MCM_ETBRL_RD() & ~(v)))
+#define HW_MCM_ETBRL_TOG(v) (HW_MCM_ETBRL_WR(HW_MCM_ETBRL_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCM_ETBRL bitfields
+ */
+
+/*!
+ * @name Register MCM_ETBRL, field RELOAD[10:0] (RW)
+ *
+ * Indicates the 0-mod-4 value the counter reloads to. Writing a non-0-mod-4
+ * value to this field results in a bus error.
+ */
+//@{
+#define BP_MCM_ETBRL_RELOAD (0U) //!< Bit position for MCM_ETBRL_RELOAD.
+#define BM_MCM_ETBRL_RELOAD (0x000007FFU) //!< Bit mask for MCM_ETBRL_RELOAD.
+#define BS_MCM_ETBRL_RELOAD (11U) //!< Bit field size in bits for MCM_ETBRL_RELOAD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ETBRL_RELOAD field.
+#define BR_MCM_ETBRL_RELOAD (HW_MCM_ETBRL.B.RELOAD)
+#endif
+
+//! @brief Format value for bitfield MCM_ETBRL_RELOAD.
+#define BF_MCM_ETBRL_RELOAD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBRL_RELOAD), uint32_t) & BM_MCM_ETBRL_RELOAD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RELOAD field to a new value.
+#define BW_MCM_ETBRL_RELOAD(v) (HW_MCM_ETBRL_WR((HW_MCM_ETBRL_RD() & ~BM_MCM_ETBRL_RELOAD) | BF_MCM_ETBRL_RELOAD(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCM_ETBCNT - ETB Counter Value register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCM_ETBCNT - ETB Counter Value register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_mcm_etbcnt
+{
+ uint32_t U;
+ struct _hw_mcm_etbcnt_bitfields
+ {
+ uint32_t COUNTER : 11; //!< [10:0] Byte Count Counter Value
+ uint32_t RESERVED0 : 21; //!< [31:11]
+ } B;
+} hw_mcm_etbcnt_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCM_ETBCNT register
+ */
+//@{
+#define HW_MCM_ETBCNT_ADDR (REGS_MCM_BASE + 0x1CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCM_ETBCNT (*(__I hw_mcm_etbcnt_t *) HW_MCM_ETBCNT_ADDR)
+#define HW_MCM_ETBCNT_RD() (HW_MCM_ETBCNT.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCM_ETBCNT bitfields
+ */
+
+/*!
+ * @name Register MCM_ETBCNT, field COUNTER[10:0] (RO)
+ *
+ * Indicates the current 0-mod-4 value of the counter.
+ */
+//@{
+#define BP_MCM_ETBCNT_COUNTER (0U) //!< Bit position for MCM_ETBCNT_COUNTER.
+#define BM_MCM_ETBCNT_COUNTER (0x000007FFU) //!< Bit mask for MCM_ETBCNT_COUNTER.
+#define BS_MCM_ETBCNT_COUNTER (11U) //!< Bit field size in bits for MCM_ETBCNT_COUNTER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_ETBCNT_COUNTER field.
+#define BR_MCM_ETBCNT_COUNTER (HW_MCM_ETBCNT.B.COUNTER)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MCM_PID - Process ID register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MCM_PID - Process ID register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register drives the M0_PID and M1_PID values in the Memory Protection
+ * Unit(MPU). System software loads this register before passing control to a given
+ * user mode process. If the PID of the process does not match the value in this
+ * register, a bus error occurs. See the MPU chapter for more details.
+ */
+typedef union _hw_mcm_pid
+{
+ uint32_t U;
+ struct _hw_mcm_pid_bitfields
+ {
+ uint32_t PID : 8; //!< [7:0] M0_PID And M1_PID For MPU
+ uint32_t RESERVED0 : 24; //!< [31:8]
+ } B;
+} hw_mcm_pid_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MCM_PID register
+ */
+//@{
+#define HW_MCM_PID_ADDR (REGS_MCM_BASE + 0x30U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MCM_PID (*(__IO hw_mcm_pid_t *) HW_MCM_PID_ADDR)
+#define HW_MCM_PID_RD() (HW_MCM_PID.U)
+#define HW_MCM_PID_WR(v) (HW_MCM_PID.U = (v))
+#define HW_MCM_PID_SET(v) (HW_MCM_PID_WR(HW_MCM_PID_RD() | (v)))
+#define HW_MCM_PID_CLR(v) (HW_MCM_PID_WR(HW_MCM_PID_RD() & ~(v)))
+#define HW_MCM_PID_TOG(v) (HW_MCM_PID_WR(HW_MCM_PID_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MCM_PID bitfields
+ */
+
+/*!
+ * @name Register MCM_PID, field PID[7:0] (RW)
+ *
+ * Drives the M0_PID and M1_PID values in the MPU.
+ */
+//@{
+#define BP_MCM_PID_PID (0U) //!< Bit position for MCM_PID_PID.
+#define BM_MCM_PID_PID (0x000000FFU) //!< Bit mask for MCM_PID_PID.
+#define BS_MCM_PID_PID (8U) //!< Bit field size in bits for MCM_PID_PID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MCM_PID_PID field.
+#define BR_MCM_PID_PID (HW_MCM_PID.B.PID)
+#endif
+
+//! @brief Format value for bitfield MCM_PID_PID.
+#define BF_MCM_PID_PID(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_PID_PID), uint32_t) & BM_MCM_PID_PID)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PID field to a new value.
+#define BW_MCM_PID_PID(v) (HW_MCM_PID_WR((HW_MCM_PID_RD() & ~BM_MCM_PID_PID) | BF_MCM_PID_PID(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_mcm_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All MCM module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_mcm
+{
+ uint8_t _reserved0[8];
+ __I hw_mcm_plasc_t PLASC; //!< [0x8] Crossbar Switch (AXBS) Slave Configuration
+ __I hw_mcm_plamc_t PLAMC; //!< [0xA] Crossbar Switch (AXBS) Master Configuration
+ __IO hw_mcm_cr_t CR; //!< [0xC] Control Register
+ __IO hw_mcm_isr_t ISR; //!< [0x10] Interrupt Status Register
+ __IO hw_mcm_etbcc_t ETBCC; //!< [0x14] ETB Counter Control register
+ __IO hw_mcm_etbrl_t ETBRL; //!< [0x18] ETB Reload register
+ __I hw_mcm_etbcnt_t ETBCNT; //!< [0x1C] ETB Counter Value register
+ uint8_t _reserved1[16];
+ __IO hw_mcm_pid_t PID; //!< [0x30] Process ID register
+} hw_mcm_t;
+#pragma pack()
+
+//! @brief Macro to access all MCM registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_MCM</code>.
+#define HW_MCM (*(hw_mcm_t *) REGS_MCM_BASE)
+#endif
+
+#endif // __HW_MCM_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_mpu.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,1923 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_MPU_REGISTERS_H__
+#define __HW_MPU_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 MPU
+ *
+ * Memory protection unit
+ *
+ * Registers defined in this header file:
+ * - HW_MPU_CESR - Control/Error Status Register
+ * - HW_MPU_EARn - Error Address Register, slave port n
+ * - HW_MPU_EDRn - Error Detail Register, slave port n
+ * - HW_MPU_RGDn_WORD0 - Region Descriptor n, Word 0
+ * - HW_MPU_RGDn_WORD1 - Region Descriptor n, Word 1
+ * - HW_MPU_RGDn_WORD2 - Region Descriptor n, Word 2
+ * - HW_MPU_RGDn_WORD3 - Region Descriptor n, Word 3
+ * - HW_MPU_RGDAACn - Region Descriptor Alternate Access Control n
+ *
+ * - hw_mpu_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_MPU_BASE
+#define HW_MPU_INSTANCE_COUNT (1U) //!< Number of instances of the MPU module.
+#define REGS_MPU_BASE (0x4000D000U) //!< Base address for MPU.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MPU_CESR - Control/Error Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MPU_CESR - Control/Error Status Register (RW)
+ *
+ * Reset value: 0x00815101U
+ */
+typedef union _hw_mpu_cesr
+{
+ uint32_t U;
+ struct _hw_mpu_cesr_bitfields
+ {
+ uint32_t VLD : 1; //!< [0] Valid
+ uint32_t RESERVED0 : 7; //!< [7:1]
+ uint32_t NRGD : 4; //!< [11:8] Number Of Region Descriptors
+ uint32_t NSP : 4; //!< [15:12] Number Of Slave Ports
+ uint32_t HRL : 4; //!< [19:16] Hardware Revision Level
+ uint32_t RESERVED1 : 7; //!< [26:20]
+ uint32_t SPERR : 5; //!< [31:27] Slave Port n Error
+ } B;
+} hw_mpu_cesr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MPU_CESR register
+ */
+//@{
+#define HW_MPU_CESR_ADDR (REGS_MPU_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MPU_CESR (*(__IO hw_mpu_cesr_t *) HW_MPU_CESR_ADDR)
+#define HW_MPU_CESR_RD() (HW_MPU_CESR.U)
+#define HW_MPU_CESR_WR(v) (HW_MPU_CESR.U = (v))
+#define HW_MPU_CESR_SET(v) (HW_MPU_CESR_WR(HW_MPU_CESR_RD() | (v)))
+#define HW_MPU_CESR_CLR(v) (HW_MPU_CESR_WR(HW_MPU_CESR_RD() & ~(v)))
+#define HW_MPU_CESR_TOG(v) (HW_MPU_CESR_WR(HW_MPU_CESR_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MPU_CESR bitfields
+ */
+
+/*!
+ * @name Register MPU_CESR, field VLD[0] (RW)
+ *
+ * Global enable/disable for the MPU.
+ *
+ * Values:
+ * - 0 - MPU is disabled. All accesses from all bus masters are allowed.
+ * - 1 - MPU is enabled
+ */
+//@{
+#define BP_MPU_CESR_VLD (0U) //!< Bit position for MPU_CESR_VLD.
+#define BM_MPU_CESR_VLD (0x00000001U) //!< Bit mask for MPU_CESR_VLD.
+#define BS_MPU_CESR_VLD (1U) //!< Bit field size in bits for MPU_CESR_VLD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_CESR_VLD field.
+#define BR_MPU_CESR_VLD (BITBAND_ACCESS32(HW_MPU_CESR_ADDR, BP_MPU_CESR_VLD))
+#endif
+
+//! @brief Format value for bitfield MPU_CESR_VLD.
+#define BF_MPU_CESR_VLD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_CESR_VLD), uint32_t) & BM_MPU_CESR_VLD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the VLD field to a new value.
+#define BW_MPU_CESR_VLD(v) (BITBAND_ACCESS32(HW_MPU_CESR_ADDR, BP_MPU_CESR_VLD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_CESR, field NRGD[11:8] (RO)
+ *
+ * Indicates the number of region descriptors implemented in the MPU.
+ *
+ * Values:
+ * - 0000 - 8 region descriptors
+ * - 0001 - 12 region descriptors
+ * - 0010 - 16 region descriptors
+ */
+//@{
+#define BP_MPU_CESR_NRGD (8U) //!< Bit position for MPU_CESR_NRGD.
+#define BM_MPU_CESR_NRGD (0x00000F00U) //!< Bit mask for MPU_CESR_NRGD.
+#define BS_MPU_CESR_NRGD (4U) //!< Bit field size in bits for MPU_CESR_NRGD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_CESR_NRGD field.
+#define BR_MPU_CESR_NRGD (HW_MPU_CESR.B.NRGD)
+#endif
+//@}
+
+/*!
+ * @name Register MPU_CESR, field NSP[15:12] (RO)
+ *
+ * Specifies the number of slave ports connected to the MPU.
+ */
+//@{
+#define BP_MPU_CESR_NSP (12U) //!< Bit position for MPU_CESR_NSP.
+#define BM_MPU_CESR_NSP (0x0000F000U) //!< Bit mask for MPU_CESR_NSP.
+#define BS_MPU_CESR_NSP (4U) //!< Bit field size in bits for MPU_CESR_NSP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_CESR_NSP field.
+#define BR_MPU_CESR_NSP (HW_MPU_CESR.B.NSP)
+#endif
+//@}
+
+/*!
+ * @name Register MPU_CESR, field HRL[19:16] (RO)
+ *
+ * Specifies the MPU's hardware and definition revision level. It can be read by
+ * software to determine the functional definition of the module.
+ */
+//@{
+#define BP_MPU_CESR_HRL (16U) //!< Bit position for MPU_CESR_HRL.
+#define BM_MPU_CESR_HRL (0x000F0000U) //!< Bit mask for MPU_CESR_HRL.
+#define BS_MPU_CESR_HRL (4U) //!< Bit field size in bits for MPU_CESR_HRL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_CESR_HRL field.
+#define BR_MPU_CESR_HRL (HW_MPU_CESR.B.HRL)
+#endif
+//@}
+
+/*!
+ * @name Register MPU_CESR, field SPERR[31:27] (W1C)
+ *
+ * Indicates a captured error in EARn and EDRn. This bit is set when the
+ * hardware detects an error and records the faulting address and attributes. It is
+ * cleared by writing one to it. If another error is captured at the exact same cycle
+ * as the write, the flag remains set. A find-first-one instruction or
+ * equivalent can detect the presence of a captured error. The following shows the
+ * correspondence between the bit number and slave port number: Bit 31 corresponds to
+ * slave port 0. Bit 30 corresponds to slave port 1. Bit 29 corresponds to slave
+ * port 2. Bit 28 corresponds to slave port 3. Bit 27 corresponds to slave port 4.
+ *
+ * Values:
+ * - 0 - No error has occurred for slave port n.
+ * - 1 - An error has occurred for slave port n.
+ */
+//@{
+#define BP_MPU_CESR_SPERR (27U) //!< Bit position for MPU_CESR_SPERR.
+#define BM_MPU_CESR_SPERR (0xF8000000U) //!< Bit mask for MPU_CESR_SPERR.
+#define BS_MPU_CESR_SPERR (5U) //!< Bit field size in bits for MPU_CESR_SPERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_CESR_SPERR field.
+#define BR_MPU_CESR_SPERR (HW_MPU_CESR.B.SPERR)
+#endif
+
+//! @brief Format value for bitfield MPU_CESR_SPERR.
+#define BF_MPU_CESR_SPERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_CESR_SPERR), uint32_t) & BM_MPU_CESR_SPERR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SPERR field to a new value.
+#define BW_MPU_CESR_SPERR(v) (HW_MPU_CESR_WR((HW_MPU_CESR_RD() & ~BM_MPU_CESR_SPERR) | BF_MPU_CESR_SPERR(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MPU_EARn - Error Address Register, slave port n
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MPU_EARn - Error Address Register, slave port n (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When the MPU detects an access error on slave port n, the 32-bit reference
+ * address is captured in this read-only register and the corresponding bit in
+ * CESR[SPERR] set. Additional information about the faulting access is captured in
+ * the corresponding EDRn at the same time. This register and the corresponding
+ * EDRn contain the most recent access error; there are no hardware interlocks with
+ * CESR[SPERR], as the error registers are always loaded upon the occurrence of
+ * each protection violation.
+ */
+typedef union _hw_mpu_earn
+{
+ uint32_t U;
+ struct _hw_mpu_earn_bitfields
+ {
+ uint32_t EADDR : 32; //!< [31:0] Error Address
+ } B;
+} hw_mpu_earn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MPU_EARn register
+ */
+//@{
+#define HW_MPU_EARn_COUNT (5U)
+
+#define HW_MPU_EARn_ADDR(n) (REGS_MPU_BASE + 0x10U + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MPU_EARn(n) (*(__I hw_mpu_earn_t *) HW_MPU_EARn_ADDR(n))
+#define HW_MPU_EARn_RD(n) (HW_MPU_EARn(n).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MPU_EARn bitfields
+ */
+
+/*!
+ * @name Register MPU_EARn, field EADDR[31:0] (RO)
+ *
+ * Indicates the reference address from slave port n that generated the access
+ * error
+ */
+//@{
+#define BP_MPU_EARn_EADDR (0U) //!< Bit position for MPU_EARn_EADDR.
+#define BM_MPU_EARn_EADDR (0xFFFFFFFFU) //!< Bit mask for MPU_EARn_EADDR.
+#define BS_MPU_EARn_EADDR (32U) //!< Bit field size in bits for MPU_EARn_EADDR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_EARn_EADDR field.
+#define BR_MPU_EARn_EADDR(n) (HW_MPU_EARn(n).U)
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_MPU_EDRn - Error Detail Register, slave port n
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MPU_EDRn - Error Detail Register, slave port n (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When the MPU detects an access error on slave port n, 32 bits of error detail
+ * are captured in this read-only register and the corresponding bit in
+ * CESR[SPERR] is set. Information on the faulting address is captured in the
+ * corresponding EARn register at the same time. This register and the corresponding EARn
+ * register contain the most recent access error; there are no hardware interlocks
+ * with CESR[SPERR] as the error registers are always loaded upon the occurrence
+ * of each protection violation.
+ */
+typedef union _hw_mpu_edrn
+{
+ uint32_t U;
+ struct _hw_mpu_edrn_bitfields
+ {
+ uint32_t ERW : 1; //!< [0] Error Read/Write
+ uint32_t EATTR : 3; //!< [3:1] Error Attributes
+ uint32_t EMN : 4; //!< [7:4] Error Master Number
+ uint32_t EPID : 8; //!< [15:8] Error Process Identification
+ uint32_t EACD : 16; //!< [31:16] Error Access Control Detail
+ } B;
+} hw_mpu_edrn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MPU_EDRn register
+ */
+//@{
+#define HW_MPU_EDRn_COUNT (5U)
+
+#define HW_MPU_EDRn_ADDR(n) (REGS_MPU_BASE + 0x14U + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MPU_EDRn(n) (*(__I hw_mpu_edrn_t *) HW_MPU_EDRn_ADDR(n))
+#define HW_MPU_EDRn_RD(n) (HW_MPU_EDRn(n).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MPU_EDRn bitfields
+ */
+
+/*!
+ * @name Register MPU_EDRn, field ERW[0] (RO)
+ *
+ * Indicates the access type of the faulting reference.
+ *
+ * Values:
+ * - 0 - Read
+ * - 1 - Write
+ */
+//@{
+#define BP_MPU_EDRn_ERW (0U) //!< Bit position for MPU_EDRn_ERW.
+#define BM_MPU_EDRn_ERW (0x00000001U) //!< Bit mask for MPU_EDRn_ERW.
+#define BS_MPU_EDRn_ERW (1U) //!< Bit field size in bits for MPU_EDRn_ERW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_EDRn_ERW field.
+#define BR_MPU_EDRn_ERW(n) (BITBAND_ACCESS32(HW_MPU_EDRn_ADDR(n), BP_MPU_EDRn_ERW))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_EDRn, field EATTR[3:1] (RO)
+ *
+ * Indicates attribute information about the faulting reference. All other
+ * encodings are reserved.
+ *
+ * Values:
+ * - 000 - User mode, instruction access
+ * - 001 - User mode, data access
+ * - 010 - Supervisor mode, instruction access
+ * - 011 - Supervisor mode, data access
+ */
+//@{
+#define BP_MPU_EDRn_EATTR (1U) //!< Bit position for MPU_EDRn_EATTR.
+#define BM_MPU_EDRn_EATTR (0x0000000EU) //!< Bit mask for MPU_EDRn_EATTR.
+#define BS_MPU_EDRn_EATTR (3U) //!< Bit field size in bits for MPU_EDRn_EATTR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_EDRn_EATTR field.
+#define BR_MPU_EDRn_EATTR(n) (HW_MPU_EDRn(n).B.EATTR)
+#endif
+//@}
+
+/*!
+ * @name Register MPU_EDRn, field EMN[7:4] (RO)
+ *
+ * Indicates the bus master that generated the access error.
+ */
+//@{
+#define BP_MPU_EDRn_EMN (4U) //!< Bit position for MPU_EDRn_EMN.
+#define BM_MPU_EDRn_EMN (0x000000F0U) //!< Bit mask for MPU_EDRn_EMN.
+#define BS_MPU_EDRn_EMN (4U) //!< Bit field size in bits for MPU_EDRn_EMN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_EDRn_EMN field.
+#define BR_MPU_EDRn_EMN(n) (HW_MPU_EDRn(n).B.EMN)
+#endif
+//@}
+
+/*!
+ * @name Register MPU_EDRn, field EPID[15:8] (RO)
+ *
+ * Records the process identifier of the faulting reference. The process
+ * identifier is typically driven only by processor cores; for other bus masters, this
+ * field is cleared.
+ */
+//@{
+#define BP_MPU_EDRn_EPID (8U) //!< Bit position for MPU_EDRn_EPID.
+#define BM_MPU_EDRn_EPID (0x0000FF00U) //!< Bit mask for MPU_EDRn_EPID.
+#define BS_MPU_EDRn_EPID (8U) //!< Bit field size in bits for MPU_EDRn_EPID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_EDRn_EPID field.
+#define BR_MPU_EDRn_EPID(n) (HW_MPU_EDRn(n).B.EPID)
+#endif
+//@}
+
+/*!
+ * @name Register MPU_EDRn, field EACD[31:16] (RO)
+ *
+ * Indicates the region descriptor with the access error. If EDRn contains a
+ * captured error and EACD is cleared, an access did not hit in any region
+ * descriptor. If only a single EACD bit is set, the protection error was caused by a
+ * single non-overlapping region descriptor. If two or more EACD bits are set, the
+ * protection error was caused by an overlapping set of region descriptors.
+ */
+//@{
+#define BP_MPU_EDRn_EACD (16U) //!< Bit position for MPU_EDRn_EACD.
+#define BM_MPU_EDRn_EACD (0xFFFF0000U) //!< Bit mask for MPU_EDRn_EACD.
+#define BS_MPU_EDRn_EACD (16U) //!< Bit field size in bits for MPU_EDRn_EACD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_EDRn_EACD field.
+#define BR_MPU_EDRn_EACD(n) (HW_MPU_EDRn(n).B.EACD)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MPU_RGDn_WORD0 - Region Descriptor n, Word 0
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MPU_RGDn_WORD0 - Region Descriptor n, Word 0 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The first word of the region descriptor defines the 0-modulo-32 byte start
+ * address of the memory region. Writes to this register clear the region
+ * descriptor's valid bit (RGDn_WORD3[VLD]).
+ */
+typedef union _hw_mpu_rgdn_word0
+{
+ uint32_t U;
+ struct _hw_mpu_rgdn_word0_bitfields
+ {
+ uint32_t RESERVED0 : 5; //!< [4:0]
+ uint32_t SRTADDR : 27; //!< [31:5] Start Address
+ } B;
+} hw_mpu_rgdn_word0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MPU_RGDn_WORD0 register
+ */
+//@{
+#define HW_MPU_RGDn_WORD0_COUNT (12U)
+
+#define HW_MPU_RGDn_WORD0_ADDR(n) (REGS_MPU_BASE + 0x400U + (0x10U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MPU_RGDn_WORD0(n) (*(__IO hw_mpu_rgdn_word0_t *) HW_MPU_RGDn_WORD0_ADDR(n))
+#define HW_MPU_RGDn_WORD0_RD(n) (HW_MPU_RGDn_WORD0(n).U)
+#define HW_MPU_RGDn_WORD0_WR(n, v) (HW_MPU_RGDn_WORD0(n).U = (v))
+#define HW_MPU_RGDn_WORD0_SET(n, v) (HW_MPU_RGDn_WORD0_WR(n, HW_MPU_RGDn_WORD0_RD(n) | (v)))
+#define HW_MPU_RGDn_WORD0_CLR(n, v) (HW_MPU_RGDn_WORD0_WR(n, HW_MPU_RGDn_WORD0_RD(n) & ~(v)))
+#define HW_MPU_RGDn_WORD0_TOG(n, v) (HW_MPU_RGDn_WORD0_WR(n, HW_MPU_RGDn_WORD0_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MPU_RGDn_WORD0 bitfields
+ */
+
+/*!
+ * @name Register MPU_RGDn_WORD0, field SRTADDR[31:5] (RW)
+ *
+ * Defines the most significant bits of the 0-modulo-32 byte start address of
+ * the memory region.
+ */
+//@{
+#define BP_MPU_RGDn_WORD0_SRTADDR (5U) //!< Bit position for MPU_RGDn_WORD0_SRTADDR.
+#define BM_MPU_RGDn_WORD0_SRTADDR (0xFFFFFFE0U) //!< Bit mask for MPU_RGDn_WORD0_SRTADDR.
+#define BS_MPU_RGDn_WORD0_SRTADDR (27U) //!< Bit field size in bits for MPU_RGDn_WORD0_SRTADDR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD0_SRTADDR field.
+#define BR_MPU_RGDn_WORD0_SRTADDR(n) (HW_MPU_RGDn_WORD0(n).B.SRTADDR)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD0_SRTADDR.
+#define BF_MPU_RGDn_WORD0_SRTADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD0_SRTADDR), uint32_t) & BM_MPU_RGDn_WORD0_SRTADDR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SRTADDR field to a new value.
+#define BW_MPU_RGDn_WORD0_SRTADDR(n, v) (HW_MPU_RGDn_WORD0_WR(n, (HW_MPU_RGDn_WORD0_RD(n) & ~BM_MPU_RGDn_WORD0_SRTADDR) | BF_MPU_RGDn_WORD0_SRTADDR(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_MPU_RGDn_WORD1 - Region Descriptor n, Word 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MPU_RGDn_WORD1 - Region Descriptor n, Word 1 (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * The second word of the region descriptor defines the 31-modulo-32 byte end
+ * address of the memory region. Writes to this register clear the region
+ * descriptor's valid bit (RGDn_WORD3[VLD]).
+ */
+typedef union _hw_mpu_rgdn_word1
+{
+ uint32_t U;
+ struct _hw_mpu_rgdn_word1_bitfields
+ {
+ uint32_t RESERVED0 : 5; //!< [4:0]
+ uint32_t ENDADDR : 27; //!< [31:5] End Address
+ } B;
+} hw_mpu_rgdn_word1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MPU_RGDn_WORD1 register
+ */
+//@{
+#define HW_MPU_RGDn_WORD1_COUNT (12U)
+
+#define HW_MPU_RGDn_WORD1_ADDR(n) (REGS_MPU_BASE + 0x404U + (0x10U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MPU_RGDn_WORD1(n) (*(__IO hw_mpu_rgdn_word1_t *) HW_MPU_RGDn_WORD1_ADDR(n))
+#define HW_MPU_RGDn_WORD1_RD(n) (HW_MPU_RGDn_WORD1(n).U)
+#define HW_MPU_RGDn_WORD1_WR(n, v) (HW_MPU_RGDn_WORD1(n).U = (v))
+#define HW_MPU_RGDn_WORD1_SET(n, v) (HW_MPU_RGDn_WORD1_WR(n, HW_MPU_RGDn_WORD1_RD(n) | (v)))
+#define HW_MPU_RGDn_WORD1_CLR(n, v) (HW_MPU_RGDn_WORD1_WR(n, HW_MPU_RGDn_WORD1_RD(n) & ~(v)))
+#define HW_MPU_RGDn_WORD1_TOG(n, v) (HW_MPU_RGDn_WORD1_WR(n, HW_MPU_RGDn_WORD1_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MPU_RGDn_WORD1 bitfields
+ */
+
+/*!
+ * @name Register MPU_RGDn_WORD1, field ENDADDR[31:5] (RW)
+ *
+ * Defines the most significant bits of the 31-modulo-32 byte end address of the
+ * memory region. The MPU does not verify that ENDADDR >= SRTADDR.
+ */
+//@{
+#define BP_MPU_RGDn_WORD1_ENDADDR (5U) //!< Bit position for MPU_RGDn_WORD1_ENDADDR.
+#define BM_MPU_RGDn_WORD1_ENDADDR (0xFFFFFFE0U) //!< Bit mask for MPU_RGDn_WORD1_ENDADDR.
+#define BS_MPU_RGDn_WORD1_ENDADDR (27U) //!< Bit field size in bits for MPU_RGDn_WORD1_ENDADDR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD1_ENDADDR field.
+#define BR_MPU_RGDn_WORD1_ENDADDR(n) (HW_MPU_RGDn_WORD1(n).B.ENDADDR)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD1_ENDADDR.
+#define BF_MPU_RGDn_WORD1_ENDADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD1_ENDADDR), uint32_t) & BM_MPU_RGDn_WORD1_ENDADDR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ENDADDR field to a new value.
+#define BW_MPU_RGDn_WORD1_ENDADDR(n, v) (HW_MPU_RGDn_WORD1_WR(n, (HW_MPU_RGDn_WORD1_RD(n) & ~BM_MPU_RGDn_WORD1_ENDADDR) | BF_MPU_RGDn_WORD1_ENDADDR(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_MPU_RGDn_WORD2 - Region Descriptor n, Word 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MPU_RGDn_WORD2 - Region Descriptor n, Word 2 (RW)
+ *
+ * Reset value: 0x0061F7DFU
+ *
+ * The third word of the region descriptor defines the access control rights of
+ * the memory region. The access control privileges depend on two broad
+ * classifications of bus masters: Bus masters 0-3 have a 5-bit field defining separate
+ * privilege rights for user and supervisor mode accesses, as well as the optional
+ * inclusion of a process identification field within the definition. Bus masters
+ * 4-7 are limited to separate read and write permissions. For the privilege
+ * rights of bus masters 0-3, there are three flags associated with this function:
+ * Read (r) refers to accessing the referenced memory address using an operand
+ * (data) fetch Write (w) refers to updating the referenced memory address using a
+ * store (data) instruction Execute (x) refers to reading the referenced memory
+ * address using an instruction fetch Writes to RGDn_WORD2 clear the region
+ * descriptor's valid bit (RGDn_WORD3[VLD]). If only updating the access controls, write
+ * to RGDAACn instead because stores to these locations do not affect the
+ * descriptor's valid bit.
+ */
+typedef union _hw_mpu_rgdn_word2
+{
+ uint32_t U;
+ struct _hw_mpu_rgdn_word2_bitfields
+ {
+ uint32_t M0UM : 3; //!< [2:0] Bus Master 0 User Mode Access Control
+ uint32_t M0SM : 2; //!< [4:3] Bus Master 0 Supervisor Mode Access
+ //! Control
+ uint32_t M0PE : 1; //!< [5] Bus Master 0 Process Identifier enable
+ uint32_t M1UM : 3; //!< [8:6] Bus Master 1 User Mode Access Control
+ uint32_t M1SM : 2; //!< [10:9] Bus Master 1 Supervisor Mode Access
+ //! Control
+ uint32_t M1PE : 1; //!< [11] Bus Master 1 Process Identifier enable
+ uint32_t M2UM : 3; //!< [14:12] Bus Master 2 User Mode Access control
+ uint32_t M2SM : 2; //!< [16:15] Bus Master 2 Supervisor Mode Access
+ //! Control
+ uint32_t M2PE : 1; //!< [17] Bus Master 2 Process Identifier Enable
+ uint32_t M3UM : 3; //!< [20:18] Bus Master 3 User Mode Access Control
+ uint32_t M3SM : 2; //!< [22:21] Bus Master 3 Supervisor Mode Access
+ //! Control
+ uint32_t M3PE : 1; //!< [23] Bus Master 3 Process Identifier Enable
+ uint32_t M4WE : 1; //!< [24] Bus Master 4 Write Enable
+ uint32_t M4RE : 1; //!< [25] Bus Master 4 Read Enable
+ uint32_t M5WE : 1; //!< [26] Bus Master 5 Write Enable
+ uint32_t M5RE : 1; //!< [27] Bus Master 5 Read Enable
+ uint32_t M6WE : 1; //!< [28] Bus Master 6 Write Enable
+ uint32_t M6RE : 1; //!< [29] Bus Master 6 Read Enable
+ uint32_t M7WE : 1; //!< [30] Bus Master 7 Write Enable
+ uint32_t M7RE : 1; //!< [31] Bus Master 7 Read Enable
+ } B;
+} hw_mpu_rgdn_word2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MPU_RGDn_WORD2 register
+ */
+//@{
+#define HW_MPU_RGDn_WORD2_COUNT (12U)
+
+#define HW_MPU_RGDn_WORD2_ADDR(n) (REGS_MPU_BASE + 0x408U + (0x10U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MPU_RGDn_WORD2(n) (*(__IO hw_mpu_rgdn_word2_t *) HW_MPU_RGDn_WORD2_ADDR(n))
+#define HW_MPU_RGDn_WORD2_RD(n) (HW_MPU_RGDn_WORD2(n).U)
+#define HW_MPU_RGDn_WORD2_WR(n, v) (HW_MPU_RGDn_WORD2(n).U = (v))
+#define HW_MPU_RGDn_WORD2_SET(n, v) (HW_MPU_RGDn_WORD2_WR(n, HW_MPU_RGDn_WORD2_RD(n) | (v)))
+#define HW_MPU_RGDn_WORD2_CLR(n, v) (HW_MPU_RGDn_WORD2_WR(n, HW_MPU_RGDn_WORD2_RD(n) & ~(v)))
+#define HW_MPU_RGDn_WORD2_TOG(n, v) (HW_MPU_RGDn_WORD2_WR(n, HW_MPU_RGDn_WORD2_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MPU_RGDn_WORD2 bitfields
+ */
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M0UM[2:0] (RW)
+ *
+ * See M3UM description.
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M0UM (0U) //!< Bit position for MPU_RGDn_WORD2_M0UM.
+#define BM_MPU_RGDn_WORD2_M0UM (0x00000007U) //!< Bit mask for MPU_RGDn_WORD2_M0UM.
+#define BS_MPU_RGDn_WORD2_M0UM (3U) //!< Bit field size in bits for MPU_RGDn_WORD2_M0UM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M0UM field.
+#define BR_MPU_RGDn_WORD2_M0UM(n) (HW_MPU_RGDn_WORD2(n).B.M0UM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M0UM.
+#define BF_MPU_RGDn_WORD2_M0UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M0UM), uint32_t) & BM_MPU_RGDn_WORD2_M0UM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M0UM field to a new value.
+#define BW_MPU_RGDn_WORD2_M0UM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M0UM) | BF_MPU_RGDn_WORD2_M0UM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M0SM[4:3] (RW)
+ *
+ * See M3SM description.
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M0SM (3U) //!< Bit position for MPU_RGDn_WORD2_M0SM.
+#define BM_MPU_RGDn_WORD2_M0SM (0x00000018U) //!< Bit mask for MPU_RGDn_WORD2_M0SM.
+#define BS_MPU_RGDn_WORD2_M0SM (2U) //!< Bit field size in bits for MPU_RGDn_WORD2_M0SM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M0SM field.
+#define BR_MPU_RGDn_WORD2_M0SM(n) (HW_MPU_RGDn_WORD2(n).B.M0SM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M0SM.
+#define BF_MPU_RGDn_WORD2_M0SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M0SM), uint32_t) & BM_MPU_RGDn_WORD2_M0SM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M0SM field to a new value.
+#define BW_MPU_RGDn_WORD2_M0SM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M0SM) | BF_MPU_RGDn_WORD2_M0SM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M0PE[5] (RW)
+ *
+ * See M0PE description.
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M0PE (5U) //!< Bit position for MPU_RGDn_WORD2_M0PE.
+#define BM_MPU_RGDn_WORD2_M0PE (0x00000020U) //!< Bit mask for MPU_RGDn_WORD2_M0PE.
+#define BS_MPU_RGDn_WORD2_M0PE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M0PE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M0PE field.
+#define BR_MPU_RGDn_WORD2_M0PE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M0PE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M0PE.
+#define BF_MPU_RGDn_WORD2_M0PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M0PE), uint32_t) & BM_MPU_RGDn_WORD2_M0PE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M0PE field to a new value.
+#define BW_MPU_RGDn_WORD2_M0PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M0PE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M1UM[8:6] (RW)
+ *
+ * See M3UM description.
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M1UM (6U) //!< Bit position for MPU_RGDn_WORD2_M1UM.
+#define BM_MPU_RGDn_WORD2_M1UM (0x000001C0U) //!< Bit mask for MPU_RGDn_WORD2_M1UM.
+#define BS_MPU_RGDn_WORD2_M1UM (3U) //!< Bit field size in bits for MPU_RGDn_WORD2_M1UM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M1UM field.
+#define BR_MPU_RGDn_WORD2_M1UM(n) (HW_MPU_RGDn_WORD2(n).B.M1UM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M1UM.
+#define BF_MPU_RGDn_WORD2_M1UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M1UM), uint32_t) & BM_MPU_RGDn_WORD2_M1UM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M1UM field to a new value.
+#define BW_MPU_RGDn_WORD2_M1UM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M1UM) | BF_MPU_RGDn_WORD2_M1UM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M1SM[10:9] (RW)
+ *
+ * See M3SM description.
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M1SM (9U) //!< Bit position for MPU_RGDn_WORD2_M1SM.
+#define BM_MPU_RGDn_WORD2_M1SM (0x00000600U) //!< Bit mask for MPU_RGDn_WORD2_M1SM.
+#define BS_MPU_RGDn_WORD2_M1SM (2U) //!< Bit field size in bits for MPU_RGDn_WORD2_M1SM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M1SM field.
+#define BR_MPU_RGDn_WORD2_M1SM(n) (HW_MPU_RGDn_WORD2(n).B.M1SM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M1SM.
+#define BF_MPU_RGDn_WORD2_M1SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M1SM), uint32_t) & BM_MPU_RGDn_WORD2_M1SM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M1SM field to a new value.
+#define BW_MPU_RGDn_WORD2_M1SM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M1SM) | BF_MPU_RGDn_WORD2_M1SM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M1PE[11] (RW)
+ *
+ * See M3PE description.
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M1PE (11U) //!< Bit position for MPU_RGDn_WORD2_M1PE.
+#define BM_MPU_RGDn_WORD2_M1PE (0x00000800U) //!< Bit mask for MPU_RGDn_WORD2_M1PE.
+#define BS_MPU_RGDn_WORD2_M1PE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M1PE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M1PE field.
+#define BR_MPU_RGDn_WORD2_M1PE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M1PE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M1PE.
+#define BF_MPU_RGDn_WORD2_M1PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M1PE), uint32_t) & BM_MPU_RGDn_WORD2_M1PE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M1PE field to a new value.
+#define BW_MPU_RGDn_WORD2_M1PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M1PE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M2UM[14:12] (RW)
+ *
+ * See M3UM description.
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M2UM (12U) //!< Bit position for MPU_RGDn_WORD2_M2UM.
+#define BM_MPU_RGDn_WORD2_M2UM (0x00007000U) //!< Bit mask for MPU_RGDn_WORD2_M2UM.
+#define BS_MPU_RGDn_WORD2_M2UM (3U) //!< Bit field size in bits for MPU_RGDn_WORD2_M2UM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M2UM field.
+#define BR_MPU_RGDn_WORD2_M2UM(n) (HW_MPU_RGDn_WORD2(n).B.M2UM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M2UM.
+#define BF_MPU_RGDn_WORD2_M2UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M2UM), uint32_t) & BM_MPU_RGDn_WORD2_M2UM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M2UM field to a new value.
+#define BW_MPU_RGDn_WORD2_M2UM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M2UM) | BF_MPU_RGDn_WORD2_M2UM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M2SM[16:15] (RW)
+ *
+ * See M3SM description.
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M2SM (15U) //!< Bit position for MPU_RGDn_WORD2_M2SM.
+#define BM_MPU_RGDn_WORD2_M2SM (0x00018000U) //!< Bit mask for MPU_RGDn_WORD2_M2SM.
+#define BS_MPU_RGDn_WORD2_M2SM (2U) //!< Bit field size in bits for MPU_RGDn_WORD2_M2SM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M2SM field.
+#define BR_MPU_RGDn_WORD2_M2SM(n) (HW_MPU_RGDn_WORD2(n).B.M2SM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M2SM.
+#define BF_MPU_RGDn_WORD2_M2SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M2SM), uint32_t) & BM_MPU_RGDn_WORD2_M2SM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M2SM field to a new value.
+#define BW_MPU_RGDn_WORD2_M2SM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M2SM) | BF_MPU_RGDn_WORD2_M2SM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M2PE[17] (RW)
+ *
+ * See M3PE description.
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M2PE (17U) //!< Bit position for MPU_RGDn_WORD2_M2PE.
+#define BM_MPU_RGDn_WORD2_M2PE (0x00020000U) //!< Bit mask for MPU_RGDn_WORD2_M2PE.
+#define BS_MPU_RGDn_WORD2_M2PE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M2PE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M2PE field.
+#define BR_MPU_RGDn_WORD2_M2PE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M2PE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M2PE.
+#define BF_MPU_RGDn_WORD2_M2PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M2PE), uint32_t) & BM_MPU_RGDn_WORD2_M2PE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M2PE field to a new value.
+#define BW_MPU_RGDn_WORD2_M2PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M2PE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M3UM[20:18] (RW)
+ *
+ * Defines the access controls for bus master 3 in User mode. M3UM consists of
+ * three independent bits, enabling read (r), write (w), and execute (x)
+ * permissions.
+ *
+ * Values:
+ * - 0 - An attempted access of that mode may be terminated with an access error
+ * (if not allowed by another descriptor) and the access not performed.
+ * - 1 - Allows the given access type to occur
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M3UM (18U) //!< Bit position for MPU_RGDn_WORD2_M3UM.
+#define BM_MPU_RGDn_WORD2_M3UM (0x001C0000U) //!< Bit mask for MPU_RGDn_WORD2_M3UM.
+#define BS_MPU_RGDn_WORD2_M3UM (3U) //!< Bit field size in bits for MPU_RGDn_WORD2_M3UM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M3UM field.
+#define BR_MPU_RGDn_WORD2_M3UM(n) (HW_MPU_RGDn_WORD2(n).B.M3UM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M3UM.
+#define BF_MPU_RGDn_WORD2_M3UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M3UM), uint32_t) & BM_MPU_RGDn_WORD2_M3UM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M3UM field to a new value.
+#define BW_MPU_RGDn_WORD2_M3UM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M3UM) | BF_MPU_RGDn_WORD2_M3UM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M3SM[22:21] (RW)
+ *
+ * Defines the access controls for bus master 3 in Supervisor mode.
+ *
+ * Values:
+ * - 00 - r/w/x; read, write and execute allowed
+ * - 01 - r/x; read and execute allowed, but no write
+ * - 10 - r/w; read and write allowed, but no execute
+ * - 11 - Same as User mode defined in M3UM
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M3SM (21U) //!< Bit position for MPU_RGDn_WORD2_M3SM.
+#define BM_MPU_RGDn_WORD2_M3SM (0x00600000U) //!< Bit mask for MPU_RGDn_WORD2_M3SM.
+#define BS_MPU_RGDn_WORD2_M3SM (2U) //!< Bit field size in bits for MPU_RGDn_WORD2_M3SM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M3SM field.
+#define BR_MPU_RGDn_WORD2_M3SM(n) (HW_MPU_RGDn_WORD2(n).B.M3SM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M3SM.
+#define BF_MPU_RGDn_WORD2_M3SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M3SM), uint32_t) & BM_MPU_RGDn_WORD2_M3SM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M3SM field to a new value.
+#define BW_MPU_RGDn_WORD2_M3SM(n, v) (HW_MPU_RGDn_WORD2_WR(n, (HW_MPU_RGDn_WORD2_RD(n) & ~BM_MPU_RGDn_WORD2_M3SM) | BF_MPU_RGDn_WORD2_M3SM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M3PE[23] (RW)
+ *
+ * Values:
+ * - 0 - Do not include the process identifier in the evaluation
+ * - 1 - Include the process identifier and mask (RGDn_WORD3) in the region hit
+ * evaluation
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M3PE (23U) //!< Bit position for MPU_RGDn_WORD2_M3PE.
+#define BM_MPU_RGDn_WORD2_M3PE (0x00800000U) //!< Bit mask for MPU_RGDn_WORD2_M3PE.
+#define BS_MPU_RGDn_WORD2_M3PE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M3PE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M3PE field.
+#define BR_MPU_RGDn_WORD2_M3PE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M3PE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M3PE.
+#define BF_MPU_RGDn_WORD2_M3PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M3PE), uint32_t) & BM_MPU_RGDn_WORD2_M3PE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M3PE field to a new value.
+#define BW_MPU_RGDn_WORD2_M3PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M3PE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M4WE[24] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 4 writes terminate with an access error and the write is not
+ * performed
+ * - 1 - Bus master 4 writes allowed
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M4WE (24U) //!< Bit position for MPU_RGDn_WORD2_M4WE.
+#define BM_MPU_RGDn_WORD2_M4WE (0x01000000U) //!< Bit mask for MPU_RGDn_WORD2_M4WE.
+#define BS_MPU_RGDn_WORD2_M4WE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M4WE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M4WE field.
+#define BR_MPU_RGDn_WORD2_M4WE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M4WE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M4WE.
+#define BF_MPU_RGDn_WORD2_M4WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M4WE), uint32_t) & BM_MPU_RGDn_WORD2_M4WE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M4WE field to a new value.
+#define BW_MPU_RGDn_WORD2_M4WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M4WE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M4RE[25] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 4 reads terminate with an access error and the read is not
+ * performed
+ * - 1 - Bus master 4 reads allowed
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M4RE (25U) //!< Bit position for MPU_RGDn_WORD2_M4RE.
+#define BM_MPU_RGDn_WORD2_M4RE (0x02000000U) //!< Bit mask for MPU_RGDn_WORD2_M4RE.
+#define BS_MPU_RGDn_WORD2_M4RE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M4RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M4RE field.
+#define BR_MPU_RGDn_WORD2_M4RE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M4RE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M4RE.
+#define BF_MPU_RGDn_WORD2_M4RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M4RE), uint32_t) & BM_MPU_RGDn_WORD2_M4RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M4RE field to a new value.
+#define BW_MPU_RGDn_WORD2_M4RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M4RE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M5WE[26] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 5 writes terminate with an access error and the write is not
+ * performed
+ * - 1 - Bus master 5 writes allowed
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M5WE (26U) //!< Bit position for MPU_RGDn_WORD2_M5WE.
+#define BM_MPU_RGDn_WORD2_M5WE (0x04000000U) //!< Bit mask for MPU_RGDn_WORD2_M5WE.
+#define BS_MPU_RGDn_WORD2_M5WE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M5WE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M5WE field.
+#define BR_MPU_RGDn_WORD2_M5WE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M5WE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M5WE.
+#define BF_MPU_RGDn_WORD2_M5WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M5WE), uint32_t) & BM_MPU_RGDn_WORD2_M5WE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M5WE field to a new value.
+#define BW_MPU_RGDn_WORD2_M5WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M5WE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M5RE[27] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 5 reads terminate with an access error and the read is not
+ * performed
+ * - 1 - Bus master 5 reads allowed
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M5RE (27U) //!< Bit position for MPU_RGDn_WORD2_M5RE.
+#define BM_MPU_RGDn_WORD2_M5RE (0x08000000U) //!< Bit mask for MPU_RGDn_WORD2_M5RE.
+#define BS_MPU_RGDn_WORD2_M5RE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M5RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M5RE field.
+#define BR_MPU_RGDn_WORD2_M5RE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M5RE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M5RE.
+#define BF_MPU_RGDn_WORD2_M5RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M5RE), uint32_t) & BM_MPU_RGDn_WORD2_M5RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M5RE field to a new value.
+#define BW_MPU_RGDn_WORD2_M5RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M5RE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M6WE[28] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 6 writes terminate with an access error and the write is not
+ * performed
+ * - 1 - Bus master 6 writes allowed
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M6WE (28U) //!< Bit position for MPU_RGDn_WORD2_M6WE.
+#define BM_MPU_RGDn_WORD2_M6WE (0x10000000U) //!< Bit mask for MPU_RGDn_WORD2_M6WE.
+#define BS_MPU_RGDn_WORD2_M6WE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M6WE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M6WE field.
+#define BR_MPU_RGDn_WORD2_M6WE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M6WE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M6WE.
+#define BF_MPU_RGDn_WORD2_M6WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M6WE), uint32_t) & BM_MPU_RGDn_WORD2_M6WE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M6WE field to a new value.
+#define BW_MPU_RGDn_WORD2_M6WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M6WE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M6RE[29] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 6 reads terminate with an access error and the read is not
+ * performed
+ * - 1 - Bus master 6 reads allowed
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M6RE (29U) //!< Bit position for MPU_RGDn_WORD2_M6RE.
+#define BM_MPU_RGDn_WORD2_M6RE (0x20000000U) //!< Bit mask for MPU_RGDn_WORD2_M6RE.
+#define BS_MPU_RGDn_WORD2_M6RE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M6RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M6RE field.
+#define BR_MPU_RGDn_WORD2_M6RE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M6RE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M6RE.
+#define BF_MPU_RGDn_WORD2_M6RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M6RE), uint32_t) & BM_MPU_RGDn_WORD2_M6RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M6RE field to a new value.
+#define BW_MPU_RGDn_WORD2_M6RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M6RE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M7WE[30] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 7 writes terminate with an access error and the write is not
+ * performed
+ * - 1 - Bus master 7 writes allowed
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M7WE (30U) //!< Bit position for MPU_RGDn_WORD2_M7WE.
+#define BM_MPU_RGDn_WORD2_M7WE (0x40000000U) //!< Bit mask for MPU_RGDn_WORD2_M7WE.
+#define BS_MPU_RGDn_WORD2_M7WE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M7WE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M7WE field.
+#define BR_MPU_RGDn_WORD2_M7WE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M7WE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M7WE.
+#define BF_MPU_RGDn_WORD2_M7WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M7WE), uint32_t) & BM_MPU_RGDn_WORD2_M7WE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M7WE field to a new value.
+#define BW_MPU_RGDn_WORD2_M7WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M7WE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD2, field M7RE[31] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 7 reads terminate with an access error and the read is not
+ * performed
+ * - 1 - Bus master 7 reads allowed
+ */
+//@{
+#define BP_MPU_RGDn_WORD2_M7RE (31U) //!< Bit position for MPU_RGDn_WORD2_M7RE.
+#define BM_MPU_RGDn_WORD2_M7RE (0x80000000U) //!< Bit mask for MPU_RGDn_WORD2_M7RE.
+#define BS_MPU_RGDn_WORD2_M7RE (1U) //!< Bit field size in bits for MPU_RGDn_WORD2_M7RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD2_M7RE field.
+#define BR_MPU_RGDn_WORD2_M7RE(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M7RE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD2_M7RE.
+#define BF_MPU_RGDn_WORD2_M7RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD2_M7RE), uint32_t) & BM_MPU_RGDn_WORD2_M7RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M7RE field to a new value.
+#define BW_MPU_RGDn_WORD2_M7RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(n), BP_MPU_RGDn_WORD2_M7RE) = (v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_MPU_RGDn_WORD3 - Region Descriptor n, Word 3
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MPU_RGDn_WORD3 - Region Descriptor n, Word 3 (RW)
+ *
+ * Reset value: 0x00000001U
+ *
+ * The fourth word of the region descriptor contains the optional process
+ * identifier and mask, plus the region descriptor's valid bit.
+ */
+typedef union _hw_mpu_rgdn_word3
+{
+ uint32_t U;
+ struct _hw_mpu_rgdn_word3_bitfields
+ {
+ uint32_t VLD : 1; //!< [0] Valid
+ uint32_t RESERVED0 : 15; //!< [15:1]
+ uint32_t PIDMASK : 8; //!< [23:16] Process Identifier Mask
+ uint32_t PID : 8; //!< [31:24] Process Identifier
+ } B;
+} hw_mpu_rgdn_word3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MPU_RGDn_WORD3 register
+ */
+//@{
+#define HW_MPU_RGDn_WORD3_COUNT (12U)
+
+#define HW_MPU_RGDn_WORD3_ADDR(n) (REGS_MPU_BASE + 0x40CU + (0x10U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MPU_RGDn_WORD3(n) (*(__IO hw_mpu_rgdn_word3_t *) HW_MPU_RGDn_WORD3_ADDR(n))
+#define HW_MPU_RGDn_WORD3_RD(n) (HW_MPU_RGDn_WORD3(n).U)
+#define HW_MPU_RGDn_WORD3_WR(n, v) (HW_MPU_RGDn_WORD3(n).U = (v))
+#define HW_MPU_RGDn_WORD3_SET(n, v) (HW_MPU_RGDn_WORD3_WR(n, HW_MPU_RGDn_WORD3_RD(n) | (v)))
+#define HW_MPU_RGDn_WORD3_CLR(n, v) (HW_MPU_RGDn_WORD3_WR(n, HW_MPU_RGDn_WORD3_RD(n) & ~(v)))
+#define HW_MPU_RGDn_WORD3_TOG(n, v) (HW_MPU_RGDn_WORD3_WR(n, HW_MPU_RGDn_WORD3_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MPU_RGDn_WORD3 bitfields
+ */
+
+/*!
+ * @name Register MPU_RGDn_WORD3, field VLD[0] (RW)
+ *
+ * Signals the region descriptor is valid. Any write to RGDn_WORD0-2 clears this
+ * bit.
+ *
+ * Values:
+ * - 0 - Region descriptor is invalid
+ * - 1 - Region descriptor is valid
+ */
+//@{
+#define BP_MPU_RGDn_WORD3_VLD (0U) //!< Bit position for MPU_RGDn_WORD3_VLD.
+#define BM_MPU_RGDn_WORD3_VLD (0x00000001U) //!< Bit mask for MPU_RGDn_WORD3_VLD.
+#define BS_MPU_RGDn_WORD3_VLD (1U) //!< Bit field size in bits for MPU_RGDn_WORD3_VLD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD3_VLD field.
+#define BR_MPU_RGDn_WORD3_VLD(n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD3_ADDR(n), BP_MPU_RGDn_WORD3_VLD))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD3_VLD.
+#define BF_MPU_RGDn_WORD3_VLD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD3_VLD), uint32_t) & BM_MPU_RGDn_WORD3_VLD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the VLD field to a new value.
+#define BW_MPU_RGDn_WORD3_VLD(n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD3_ADDR(n), BP_MPU_RGDn_WORD3_VLD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD3, field PIDMASK[23:16] (RW)
+ *
+ * Provides a masking capability so that multiple process identifiers can be
+ * included as part of the region hit determination. If a bit in PIDMASK is set,
+ * then the corresponding PID bit is ignored in the comparison. This field and PID
+ * are included in the region hit determination if RGDn_WORD2[MxPE] is set. For
+ * more information on the handling of the PID and PIDMASK, see "Access Evaluation
+ * - Hit Determination."
+ */
+//@{
+#define BP_MPU_RGDn_WORD3_PIDMASK (16U) //!< Bit position for MPU_RGDn_WORD3_PIDMASK.
+#define BM_MPU_RGDn_WORD3_PIDMASK (0x00FF0000U) //!< Bit mask for MPU_RGDn_WORD3_PIDMASK.
+#define BS_MPU_RGDn_WORD3_PIDMASK (8U) //!< Bit field size in bits for MPU_RGDn_WORD3_PIDMASK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD3_PIDMASK field.
+#define BR_MPU_RGDn_WORD3_PIDMASK(n) (HW_MPU_RGDn_WORD3(n).B.PIDMASK)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD3_PIDMASK.
+#define BF_MPU_RGDn_WORD3_PIDMASK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD3_PIDMASK), uint32_t) & BM_MPU_RGDn_WORD3_PIDMASK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PIDMASK field to a new value.
+#define BW_MPU_RGDn_WORD3_PIDMASK(n, v) (HW_MPU_RGDn_WORD3_WR(n, (HW_MPU_RGDn_WORD3_RD(n) & ~BM_MPU_RGDn_WORD3_PIDMASK) | BF_MPU_RGDn_WORD3_PIDMASK(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDn_WORD3, field PID[31:24] (RW)
+ *
+ * Specifies the process identifier that is included in the region hit
+ * determination if RGDn_WORD2[MxPE] is set. PIDMASK can mask individual bits in this
+ * field.
+ */
+//@{
+#define BP_MPU_RGDn_WORD3_PID (24U) //!< Bit position for MPU_RGDn_WORD3_PID.
+#define BM_MPU_RGDn_WORD3_PID (0xFF000000U) //!< Bit mask for MPU_RGDn_WORD3_PID.
+#define BS_MPU_RGDn_WORD3_PID (8U) //!< Bit field size in bits for MPU_RGDn_WORD3_PID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDn_WORD3_PID field.
+#define BR_MPU_RGDn_WORD3_PID(n) (HW_MPU_RGDn_WORD3(n).B.PID)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDn_WORD3_PID.
+#define BF_MPU_RGDn_WORD3_PID(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDn_WORD3_PID), uint32_t) & BM_MPU_RGDn_WORD3_PID)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PID field to a new value.
+#define BW_MPU_RGDn_WORD3_PID(n, v) (HW_MPU_RGDn_WORD3_WR(n, (HW_MPU_RGDn_WORD3_RD(n) & ~BM_MPU_RGDn_WORD3_PID) | BF_MPU_RGDn_WORD3_PID(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_MPU_RGDAACn - Region Descriptor Alternate Access Control n
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_MPU_RGDAACn - Region Descriptor Alternate Access Control n (RW)
+ *
+ * Reset value: 0x0061F7DFU
+ *
+ * Because software may adjust only the access controls within a region
+ * descriptor (RGDn_WORD2) as different tasks execute, an alternate programming view of
+ * this 32-bit entity is available. Writing to this register does not affect the
+ * descriptor's valid bit.
+ */
+typedef union _hw_mpu_rgdaacn
+{
+ uint32_t U;
+ struct _hw_mpu_rgdaacn_bitfields
+ {
+ uint32_t M0UM : 3; //!< [2:0] Bus Master 0 User Mode Access Control
+ uint32_t M0SM : 2; //!< [4:3] Bus Master 0 Supervisor Mode Access
+ //! Control
+ uint32_t M0PE : 1; //!< [5] Bus Master 0 Process Identifier Enable
+ uint32_t M1UM : 3; //!< [8:6] Bus Master 1 User Mode Access Control
+ uint32_t M1SM : 2; //!< [10:9] Bus Master 1 Supervisor Mode Access
+ //! Control
+ uint32_t M1PE : 1; //!< [11] Bus Master 1 Process Identifier Enable
+ uint32_t M2UM : 3; //!< [14:12] Bus Master 2 User Mode Access Control
+ uint32_t M2SM : 2; //!< [16:15] Bus Master 2 Supervisor Mode Access
+ //! Control
+ uint32_t M2PE : 1; //!< [17] Bus Master 2 Process Identifier Enable
+ uint32_t M3UM : 3; //!< [20:18] Bus Master 3 User Mode Access Control
+ uint32_t M3SM : 2; //!< [22:21] Bus Master 3 Supervisor Mode Access
+ //! Control
+ uint32_t M3PE : 1; //!< [23] Bus Master 3 Process Identifier Enable
+ uint32_t M4WE : 1; //!< [24] Bus Master 4 Write Enable
+ uint32_t M4RE : 1; //!< [25] Bus Master 4 Read Enable
+ uint32_t M5WE : 1; //!< [26] Bus Master 5 Write Enable
+ uint32_t M5RE : 1; //!< [27] Bus Master 5 Read Enable
+ uint32_t M6WE : 1; //!< [28] Bus Master 6 Write Enable
+ uint32_t M6RE : 1; //!< [29] Bus Master 6 Read Enable
+ uint32_t M7WE : 1; //!< [30] Bus Master 7 Write Enable
+ uint32_t M7RE : 1; //!< [31] Bus Master 7 Read Enable
+ } B;
+} hw_mpu_rgdaacn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire MPU_RGDAACn register
+ */
+//@{
+#define HW_MPU_RGDAACn_COUNT (12U)
+
+#define HW_MPU_RGDAACn_ADDR(n) (REGS_MPU_BASE + 0x800U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_MPU_RGDAACn(n) (*(__IO hw_mpu_rgdaacn_t *) HW_MPU_RGDAACn_ADDR(n))
+#define HW_MPU_RGDAACn_RD(n) (HW_MPU_RGDAACn(n).U)
+#define HW_MPU_RGDAACn_WR(n, v) (HW_MPU_RGDAACn(n).U = (v))
+#define HW_MPU_RGDAACn_SET(n, v) (HW_MPU_RGDAACn_WR(n, HW_MPU_RGDAACn_RD(n) | (v)))
+#define HW_MPU_RGDAACn_CLR(n, v) (HW_MPU_RGDAACn_WR(n, HW_MPU_RGDAACn_RD(n) & ~(v)))
+#define HW_MPU_RGDAACn_TOG(n, v) (HW_MPU_RGDAACn_WR(n, HW_MPU_RGDAACn_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual MPU_RGDAACn bitfields
+ */
+
+/*!
+ * @name Register MPU_RGDAACn, field M0UM[2:0] (RW)
+ *
+ * See M3UM description.
+ */
+//@{
+#define BP_MPU_RGDAACn_M0UM (0U) //!< Bit position for MPU_RGDAACn_M0UM.
+#define BM_MPU_RGDAACn_M0UM (0x00000007U) //!< Bit mask for MPU_RGDAACn_M0UM.
+#define BS_MPU_RGDAACn_M0UM (3U) //!< Bit field size in bits for MPU_RGDAACn_M0UM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M0UM field.
+#define BR_MPU_RGDAACn_M0UM(n) (HW_MPU_RGDAACn(n).B.M0UM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M0UM.
+#define BF_MPU_RGDAACn_M0UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M0UM), uint32_t) & BM_MPU_RGDAACn_M0UM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M0UM field to a new value.
+#define BW_MPU_RGDAACn_M0UM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M0UM) | BF_MPU_RGDAACn_M0UM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M0SM[4:3] (RW)
+ *
+ * See M3SM description.
+ */
+//@{
+#define BP_MPU_RGDAACn_M0SM (3U) //!< Bit position for MPU_RGDAACn_M0SM.
+#define BM_MPU_RGDAACn_M0SM (0x00000018U) //!< Bit mask for MPU_RGDAACn_M0SM.
+#define BS_MPU_RGDAACn_M0SM (2U) //!< Bit field size in bits for MPU_RGDAACn_M0SM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M0SM field.
+#define BR_MPU_RGDAACn_M0SM(n) (HW_MPU_RGDAACn(n).B.M0SM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M0SM.
+#define BF_MPU_RGDAACn_M0SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M0SM), uint32_t) & BM_MPU_RGDAACn_M0SM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M0SM field to a new value.
+#define BW_MPU_RGDAACn_M0SM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M0SM) | BF_MPU_RGDAACn_M0SM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M0PE[5] (RW)
+ *
+ * See M3PE description.
+ */
+//@{
+#define BP_MPU_RGDAACn_M0PE (5U) //!< Bit position for MPU_RGDAACn_M0PE.
+#define BM_MPU_RGDAACn_M0PE (0x00000020U) //!< Bit mask for MPU_RGDAACn_M0PE.
+#define BS_MPU_RGDAACn_M0PE (1U) //!< Bit field size in bits for MPU_RGDAACn_M0PE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M0PE field.
+#define BR_MPU_RGDAACn_M0PE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M0PE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M0PE.
+#define BF_MPU_RGDAACn_M0PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M0PE), uint32_t) & BM_MPU_RGDAACn_M0PE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M0PE field to a new value.
+#define BW_MPU_RGDAACn_M0PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M0PE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M1UM[8:6] (RW)
+ *
+ * See M3UM description.
+ */
+//@{
+#define BP_MPU_RGDAACn_M1UM (6U) //!< Bit position for MPU_RGDAACn_M1UM.
+#define BM_MPU_RGDAACn_M1UM (0x000001C0U) //!< Bit mask for MPU_RGDAACn_M1UM.
+#define BS_MPU_RGDAACn_M1UM (3U) //!< Bit field size in bits for MPU_RGDAACn_M1UM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M1UM field.
+#define BR_MPU_RGDAACn_M1UM(n) (HW_MPU_RGDAACn(n).B.M1UM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M1UM.
+#define BF_MPU_RGDAACn_M1UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M1UM), uint32_t) & BM_MPU_RGDAACn_M1UM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M1UM field to a new value.
+#define BW_MPU_RGDAACn_M1UM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M1UM) | BF_MPU_RGDAACn_M1UM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M1SM[10:9] (RW)
+ *
+ * See M3SM description.
+ */
+//@{
+#define BP_MPU_RGDAACn_M1SM (9U) //!< Bit position for MPU_RGDAACn_M1SM.
+#define BM_MPU_RGDAACn_M1SM (0x00000600U) //!< Bit mask for MPU_RGDAACn_M1SM.
+#define BS_MPU_RGDAACn_M1SM (2U) //!< Bit field size in bits for MPU_RGDAACn_M1SM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M1SM field.
+#define BR_MPU_RGDAACn_M1SM(n) (HW_MPU_RGDAACn(n).B.M1SM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M1SM.
+#define BF_MPU_RGDAACn_M1SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M1SM), uint32_t) & BM_MPU_RGDAACn_M1SM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M1SM field to a new value.
+#define BW_MPU_RGDAACn_M1SM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M1SM) | BF_MPU_RGDAACn_M1SM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M1PE[11] (RW)
+ *
+ * See M3PE description.
+ */
+//@{
+#define BP_MPU_RGDAACn_M1PE (11U) //!< Bit position for MPU_RGDAACn_M1PE.
+#define BM_MPU_RGDAACn_M1PE (0x00000800U) //!< Bit mask for MPU_RGDAACn_M1PE.
+#define BS_MPU_RGDAACn_M1PE (1U) //!< Bit field size in bits for MPU_RGDAACn_M1PE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M1PE field.
+#define BR_MPU_RGDAACn_M1PE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M1PE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M1PE.
+#define BF_MPU_RGDAACn_M1PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M1PE), uint32_t) & BM_MPU_RGDAACn_M1PE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M1PE field to a new value.
+#define BW_MPU_RGDAACn_M1PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M1PE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M2UM[14:12] (RW)
+ *
+ * See M3UM description.
+ */
+//@{
+#define BP_MPU_RGDAACn_M2UM (12U) //!< Bit position for MPU_RGDAACn_M2UM.
+#define BM_MPU_RGDAACn_M2UM (0x00007000U) //!< Bit mask for MPU_RGDAACn_M2UM.
+#define BS_MPU_RGDAACn_M2UM (3U) //!< Bit field size in bits for MPU_RGDAACn_M2UM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M2UM field.
+#define BR_MPU_RGDAACn_M2UM(n) (HW_MPU_RGDAACn(n).B.M2UM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M2UM.
+#define BF_MPU_RGDAACn_M2UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M2UM), uint32_t) & BM_MPU_RGDAACn_M2UM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M2UM field to a new value.
+#define BW_MPU_RGDAACn_M2UM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M2UM) | BF_MPU_RGDAACn_M2UM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M2SM[16:15] (RW)
+ *
+ * See M3SM description.
+ */
+//@{
+#define BP_MPU_RGDAACn_M2SM (15U) //!< Bit position for MPU_RGDAACn_M2SM.
+#define BM_MPU_RGDAACn_M2SM (0x00018000U) //!< Bit mask for MPU_RGDAACn_M2SM.
+#define BS_MPU_RGDAACn_M2SM (2U) //!< Bit field size in bits for MPU_RGDAACn_M2SM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M2SM field.
+#define BR_MPU_RGDAACn_M2SM(n) (HW_MPU_RGDAACn(n).B.M2SM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M2SM.
+#define BF_MPU_RGDAACn_M2SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M2SM), uint32_t) & BM_MPU_RGDAACn_M2SM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M2SM field to a new value.
+#define BW_MPU_RGDAACn_M2SM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M2SM) | BF_MPU_RGDAACn_M2SM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M2PE[17] (RW)
+ *
+ * See M3PE description.
+ */
+//@{
+#define BP_MPU_RGDAACn_M2PE (17U) //!< Bit position for MPU_RGDAACn_M2PE.
+#define BM_MPU_RGDAACn_M2PE (0x00020000U) //!< Bit mask for MPU_RGDAACn_M2PE.
+#define BS_MPU_RGDAACn_M2PE (1U) //!< Bit field size in bits for MPU_RGDAACn_M2PE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M2PE field.
+#define BR_MPU_RGDAACn_M2PE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M2PE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M2PE.
+#define BF_MPU_RGDAACn_M2PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M2PE), uint32_t) & BM_MPU_RGDAACn_M2PE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M2PE field to a new value.
+#define BW_MPU_RGDAACn_M2PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M2PE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M3UM[20:18] (RW)
+ *
+ * Defines the access controls for bus master 3 in user mode. M3UM consists of
+ * three independent bits, enabling read (r), write (w), and execute (x)
+ * permissions.
+ *
+ * Values:
+ * - 0 - An attempted access of that mode may be terminated with an access error
+ * (if not allowed by another descriptor) and the access not performed.
+ * - 1 - Allows the given access type to occur
+ */
+//@{
+#define BP_MPU_RGDAACn_M3UM (18U) //!< Bit position for MPU_RGDAACn_M3UM.
+#define BM_MPU_RGDAACn_M3UM (0x001C0000U) //!< Bit mask for MPU_RGDAACn_M3UM.
+#define BS_MPU_RGDAACn_M3UM (3U) //!< Bit field size in bits for MPU_RGDAACn_M3UM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M3UM field.
+#define BR_MPU_RGDAACn_M3UM(n) (HW_MPU_RGDAACn(n).B.M3UM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M3UM.
+#define BF_MPU_RGDAACn_M3UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M3UM), uint32_t) & BM_MPU_RGDAACn_M3UM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M3UM field to a new value.
+#define BW_MPU_RGDAACn_M3UM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M3UM) | BF_MPU_RGDAACn_M3UM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M3SM[22:21] (RW)
+ *
+ * Defines the access controls for bus master 3 in Supervisor mode.
+ *
+ * Values:
+ * - 00 - r/w/x; read, write and execute allowed
+ * - 01 - r/x; read and execute allowed, but no write
+ * - 10 - r/w; read and write allowed, but no execute
+ * - 11 - Same as User mode defined in M3UM
+ */
+//@{
+#define BP_MPU_RGDAACn_M3SM (21U) //!< Bit position for MPU_RGDAACn_M3SM.
+#define BM_MPU_RGDAACn_M3SM (0x00600000U) //!< Bit mask for MPU_RGDAACn_M3SM.
+#define BS_MPU_RGDAACn_M3SM (2U) //!< Bit field size in bits for MPU_RGDAACn_M3SM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M3SM field.
+#define BR_MPU_RGDAACn_M3SM(n) (HW_MPU_RGDAACn(n).B.M3SM)
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M3SM.
+#define BF_MPU_RGDAACn_M3SM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M3SM), uint32_t) & BM_MPU_RGDAACn_M3SM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M3SM field to a new value.
+#define BW_MPU_RGDAACn_M3SM(n, v) (HW_MPU_RGDAACn_WR(n, (HW_MPU_RGDAACn_RD(n) & ~BM_MPU_RGDAACn_M3SM) | BF_MPU_RGDAACn_M3SM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M3PE[23] (RW)
+ *
+ * Values:
+ * - 0 - Do not include the process identifier in the evaluation
+ * - 1 - Include the process identifier and mask (RGDn.RGDAAC) in the region hit
+ * evaluation
+ */
+//@{
+#define BP_MPU_RGDAACn_M3PE (23U) //!< Bit position for MPU_RGDAACn_M3PE.
+#define BM_MPU_RGDAACn_M3PE (0x00800000U) //!< Bit mask for MPU_RGDAACn_M3PE.
+#define BS_MPU_RGDAACn_M3PE (1U) //!< Bit field size in bits for MPU_RGDAACn_M3PE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M3PE field.
+#define BR_MPU_RGDAACn_M3PE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M3PE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M3PE.
+#define BF_MPU_RGDAACn_M3PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M3PE), uint32_t) & BM_MPU_RGDAACn_M3PE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M3PE field to a new value.
+#define BW_MPU_RGDAACn_M3PE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M3PE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M4WE[24] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 4 writes terminate with an access error and the write is not
+ * performed
+ * - 1 - Bus master 4 writes allowed
+ */
+//@{
+#define BP_MPU_RGDAACn_M4WE (24U) //!< Bit position for MPU_RGDAACn_M4WE.
+#define BM_MPU_RGDAACn_M4WE (0x01000000U) //!< Bit mask for MPU_RGDAACn_M4WE.
+#define BS_MPU_RGDAACn_M4WE (1U) //!< Bit field size in bits for MPU_RGDAACn_M4WE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M4WE field.
+#define BR_MPU_RGDAACn_M4WE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M4WE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M4WE.
+#define BF_MPU_RGDAACn_M4WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M4WE), uint32_t) & BM_MPU_RGDAACn_M4WE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M4WE field to a new value.
+#define BW_MPU_RGDAACn_M4WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M4WE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M4RE[25] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 4 reads terminate with an access error and the read is not
+ * performed
+ * - 1 - Bus master 4 reads allowed
+ */
+//@{
+#define BP_MPU_RGDAACn_M4RE (25U) //!< Bit position for MPU_RGDAACn_M4RE.
+#define BM_MPU_RGDAACn_M4RE (0x02000000U) //!< Bit mask for MPU_RGDAACn_M4RE.
+#define BS_MPU_RGDAACn_M4RE (1U) //!< Bit field size in bits for MPU_RGDAACn_M4RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M4RE field.
+#define BR_MPU_RGDAACn_M4RE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M4RE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M4RE.
+#define BF_MPU_RGDAACn_M4RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M4RE), uint32_t) & BM_MPU_RGDAACn_M4RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M4RE field to a new value.
+#define BW_MPU_RGDAACn_M4RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M4RE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M5WE[26] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 5 writes terminate with an access error and the write is not
+ * performed
+ * - 1 - Bus master 5 writes allowed
+ */
+//@{
+#define BP_MPU_RGDAACn_M5WE (26U) //!< Bit position for MPU_RGDAACn_M5WE.
+#define BM_MPU_RGDAACn_M5WE (0x04000000U) //!< Bit mask for MPU_RGDAACn_M5WE.
+#define BS_MPU_RGDAACn_M5WE (1U) //!< Bit field size in bits for MPU_RGDAACn_M5WE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M5WE field.
+#define BR_MPU_RGDAACn_M5WE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M5WE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M5WE.
+#define BF_MPU_RGDAACn_M5WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M5WE), uint32_t) & BM_MPU_RGDAACn_M5WE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M5WE field to a new value.
+#define BW_MPU_RGDAACn_M5WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M5WE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M5RE[27] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 5 reads terminate with an access error and the read is not
+ * performed
+ * - 1 - Bus master 5 reads allowed
+ */
+//@{
+#define BP_MPU_RGDAACn_M5RE (27U) //!< Bit position for MPU_RGDAACn_M5RE.
+#define BM_MPU_RGDAACn_M5RE (0x08000000U) //!< Bit mask for MPU_RGDAACn_M5RE.
+#define BS_MPU_RGDAACn_M5RE (1U) //!< Bit field size in bits for MPU_RGDAACn_M5RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M5RE field.
+#define BR_MPU_RGDAACn_M5RE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M5RE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M5RE.
+#define BF_MPU_RGDAACn_M5RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M5RE), uint32_t) & BM_MPU_RGDAACn_M5RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M5RE field to a new value.
+#define BW_MPU_RGDAACn_M5RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M5RE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M6WE[28] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 6 writes terminate with an access error and the write is not
+ * performed
+ * - 1 - Bus master 6 writes allowed
+ */
+//@{
+#define BP_MPU_RGDAACn_M6WE (28U) //!< Bit position for MPU_RGDAACn_M6WE.
+#define BM_MPU_RGDAACn_M6WE (0x10000000U) //!< Bit mask for MPU_RGDAACn_M6WE.
+#define BS_MPU_RGDAACn_M6WE (1U) //!< Bit field size in bits for MPU_RGDAACn_M6WE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M6WE field.
+#define BR_MPU_RGDAACn_M6WE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M6WE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M6WE.
+#define BF_MPU_RGDAACn_M6WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M6WE), uint32_t) & BM_MPU_RGDAACn_M6WE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M6WE field to a new value.
+#define BW_MPU_RGDAACn_M6WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M6WE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M6RE[29] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 6 reads terminate with an access error and the read is not
+ * performed
+ * - 1 - Bus master 6 reads allowed
+ */
+//@{
+#define BP_MPU_RGDAACn_M6RE (29U) //!< Bit position for MPU_RGDAACn_M6RE.
+#define BM_MPU_RGDAACn_M6RE (0x20000000U) //!< Bit mask for MPU_RGDAACn_M6RE.
+#define BS_MPU_RGDAACn_M6RE (1U) //!< Bit field size in bits for MPU_RGDAACn_M6RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M6RE field.
+#define BR_MPU_RGDAACn_M6RE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M6RE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M6RE.
+#define BF_MPU_RGDAACn_M6RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M6RE), uint32_t) & BM_MPU_RGDAACn_M6RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M6RE field to a new value.
+#define BW_MPU_RGDAACn_M6RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M6RE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M7WE[30] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 7 writes terminate with an access error and the write is not
+ * performed
+ * - 1 - Bus master 7 writes allowed
+ */
+//@{
+#define BP_MPU_RGDAACn_M7WE (30U) //!< Bit position for MPU_RGDAACn_M7WE.
+#define BM_MPU_RGDAACn_M7WE (0x40000000U) //!< Bit mask for MPU_RGDAACn_M7WE.
+#define BS_MPU_RGDAACn_M7WE (1U) //!< Bit field size in bits for MPU_RGDAACn_M7WE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M7WE field.
+#define BR_MPU_RGDAACn_M7WE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M7WE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M7WE.
+#define BF_MPU_RGDAACn_M7WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M7WE), uint32_t) & BM_MPU_RGDAACn_M7WE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M7WE field to a new value.
+#define BW_MPU_RGDAACn_M7WE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M7WE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register MPU_RGDAACn, field M7RE[31] (RW)
+ *
+ * Values:
+ * - 0 - Bus master 7 reads terminate with an access error and the read is not
+ * performed
+ * - 1 - Bus master 7 reads allowed
+ */
+//@{
+#define BP_MPU_RGDAACn_M7RE (31U) //!< Bit position for MPU_RGDAACn_M7RE.
+#define BM_MPU_RGDAACn_M7RE (0x80000000U) //!< Bit mask for MPU_RGDAACn_M7RE.
+#define BS_MPU_RGDAACn_M7RE (1U) //!< Bit field size in bits for MPU_RGDAACn_M7RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the MPU_RGDAACn_M7RE field.
+#define BR_MPU_RGDAACn_M7RE(n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M7RE))
+#endif
+
+//! @brief Format value for bitfield MPU_RGDAACn_M7RE.
+#define BF_MPU_RGDAACn_M7RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MPU_RGDAACn_M7RE), uint32_t) & BM_MPU_RGDAACn_M7RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M7RE field to a new value.
+#define BW_MPU_RGDAACn_M7RE(n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(n), BP_MPU_RGDAACn_M7RE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_mpu_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All MPU module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_mpu
+{
+ __IO hw_mpu_cesr_t CESR; //!< [0x0] Control/Error Status Register
+ uint8_t _reserved0[12];
+ struct {
+ __I hw_mpu_earn_t EARn; //!< [0x10] Error Address Register, slave port n
+ __I hw_mpu_edrn_t EDRn; //!< [0x14] Error Detail Register, slave port n
+ } SP[5];
+ uint8_t _reserved1[968];
+ struct {
+ __IO hw_mpu_rgdn_word0_t RGDn_WORD0; //!< [0x400] Region Descriptor n, Word 0
+ __IO hw_mpu_rgdn_word1_t RGDn_WORD1; //!< [0x404] Region Descriptor n, Word 1
+ __IO hw_mpu_rgdn_word2_t RGDn_WORD2; //!< [0x408] Region Descriptor n, Word 2
+ __IO hw_mpu_rgdn_word3_t RGDn_WORD3; //!< [0x40C] Region Descriptor n, Word 3
+ } RGD[12];
+ uint8_t _reserved2[832];
+ __IO hw_mpu_rgdaacn_t RGDAACn[12]; //!< [0x800] Region Descriptor Alternate Access Control n
+} hw_mpu_t;
+#pragma pack()
+
+//! @brief Macro to access all MPU registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_MPU</code>.
+#define HW_MPU (*(hw_mpu_t *) REGS_MPU_BASE)
+#endif
+
+#endif // __HW_MPU_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_nv.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,958 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_NV_REGISTERS_H__
+#define __HW_NV_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 NV
+ *
+ * Flash configuration field
+ *
+ * Registers defined in this header file:
+ * - HW_NV_BACKKEY3 - Backdoor Comparison Key 3.
+ * - HW_NV_BACKKEY2 - Backdoor Comparison Key 2.
+ * - HW_NV_BACKKEY1 - Backdoor Comparison Key 1.
+ * - HW_NV_BACKKEY0 - Backdoor Comparison Key 0.
+ * - HW_NV_BACKKEY7 - Backdoor Comparison Key 7.
+ * - HW_NV_BACKKEY6 - Backdoor Comparison Key 6.
+ * - HW_NV_BACKKEY5 - Backdoor Comparison Key 5.
+ * - HW_NV_BACKKEY4 - Backdoor Comparison Key 4.
+ * - HW_NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register
+ * - HW_NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register
+ * - HW_NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register
+ * - HW_NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register
+ * - HW_NV_FSEC - Non-volatile Flash Security Register
+ * - HW_NV_FOPT - Non-volatile Flash Option Register
+ * - HW_NV_FEPROT - Non-volatile EERAM Protection Register
+ * - HW_NV_FDPROT - Non-volatile D-Flash Protection Register
+ *
+ * - hw_nv_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_NV_BASE
+#define HW_NV_INSTANCE_COUNT (1U) //!< Number of instances of the NV module.
+#define REGS_NV_BASE (0x400U) //!< Base address for FTFE_FlashConfig.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_BACKKEY3 - Backdoor Comparison Key 3.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_BACKKEY3 - Backdoor Comparison Key 3. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_backkey3
+{
+ uint8_t U;
+ struct _hw_nv_backkey3_bitfields
+ {
+ uint8_t KEY : 8; //!< [7:0] Backdoor Comparison Key.
+ } B;
+} hw_nv_backkey3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_BACKKEY3 register
+ */
+//@{
+#define HW_NV_BACKKEY3_ADDR (REGS_NV_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_BACKKEY3 (*(__I hw_nv_backkey3_t *) HW_NV_BACKKEY3_ADDR)
+#define HW_NV_BACKKEY3_RD() (HW_NV_BACKKEY3.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_BACKKEY3 bitfields
+ */
+
+/*!
+ * @name Register NV_BACKKEY3, field KEY[7:0] (RO)
+ */
+//@{
+#define BP_NV_BACKKEY3_KEY (0U) //!< Bit position for NV_BACKKEY3_KEY.
+#define BM_NV_BACKKEY3_KEY (0xFFU) //!< Bit mask for NV_BACKKEY3_KEY.
+#define BS_NV_BACKKEY3_KEY (8U) //!< Bit field size in bits for NV_BACKKEY3_KEY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_BACKKEY3_KEY field.
+#define BR_NV_BACKKEY3_KEY (HW_NV_BACKKEY3.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_BACKKEY2 - Backdoor Comparison Key 2.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_BACKKEY2 - Backdoor Comparison Key 2. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_backkey2
+{
+ uint8_t U;
+ struct _hw_nv_backkey2_bitfields
+ {
+ uint8_t KEY : 8; //!< [7:0] Backdoor Comparison Key.
+ } B;
+} hw_nv_backkey2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_BACKKEY2 register
+ */
+//@{
+#define HW_NV_BACKKEY2_ADDR (REGS_NV_BASE + 0x1U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_BACKKEY2 (*(__I hw_nv_backkey2_t *) HW_NV_BACKKEY2_ADDR)
+#define HW_NV_BACKKEY2_RD() (HW_NV_BACKKEY2.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_BACKKEY2 bitfields
+ */
+
+/*!
+ * @name Register NV_BACKKEY2, field KEY[7:0] (RO)
+ */
+//@{
+#define BP_NV_BACKKEY2_KEY (0U) //!< Bit position for NV_BACKKEY2_KEY.
+#define BM_NV_BACKKEY2_KEY (0xFFU) //!< Bit mask for NV_BACKKEY2_KEY.
+#define BS_NV_BACKKEY2_KEY (8U) //!< Bit field size in bits for NV_BACKKEY2_KEY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_BACKKEY2_KEY field.
+#define BR_NV_BACKKEY2_KEY (HW_NV_BACKKEY2.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_BACKKEY1 - Backdoor Comparison Key 1.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_BACKKEY1 - Backdoor Comparison Key 1. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_backkey1
+{
+ uint8_t U;
+ struct _hw_nv_backkey1_bitfields
+ {
+ uint8_t KEY : 8; //!< [7:0] Backdoor Comparison Key.
+ } B;
+} hw_nv_backkey1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_BACKKEY1 register
+ */
+//@{
+#define HW_NV_BACKKEY1_ADDR (REGS_NV_BASE + 0x2U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_BACKKEY1 (*(__I hw_nv_backkey1_t *) HW_NV_BACKKEY1_ADDR)
+#define HW_NV_BACKKEY1_RD() (HW_NV_BACKKEY1.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_BACKKEY1 bitfields
+ */
+
+/*!
+ * @name Register NV_BACKKEY1, field KEY[7:0] (RO)
+ */
+//@{
+#define BP_NV_BACKKEY1_KEY (0U) //!< Bit position for NV_BACKKEY1_KEY.
+#define BM_NV_BACKKEY1_KEY (0xFFU) //!< Bit mask for NV_BACKKEY1_KEY.
+#define BS_NV_BACKKEY1_KEY (8U) //!< Bit field size in bits for NV_BACKKEY1_KEY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_BACKKEY1_KEY field.
+#define BR_NV_BACKKEY1_KEY (HW_NV_BACKKEY1.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_BACKKEY0 - Backdoor Comparison Key 0.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_BACKKEY0 - Backdoor Comparison Key 0. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_backkey0
+{
+ uint8_t U;
+ struct _hw_nv_backkey0_bitfields
+ {
+ uint8_t KEY : 8; //!< [7:0] Backdoor Comparison Key.
+ } B;
+} hw_nv_backkey0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_BACKKEY0 register
+ */
+//@{
+#define HW_NV_BACKKEY0_ADDR (REGS_NV_BASE + 0x3U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_BACKKEY0 (*(__I hw_nv_backkey0_t *) HW_NV_BACKKEY0_ADDR)
+#define HW_NV_BACKKEY0_RD() (HW_NV_BACKKEY0.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_BACKKEY0 bitfields
+ */
+
+/*!
+ * @name Register NV_BACKKEY0, field KEY[7:0] (RO)
+ */
+//@{
+#define BP_NV_BACKKEY0_KEY (0U) //!< Bit position for NV_BACKKEY0_KEY.
+#define BM_NV_BACKKEY0_KEY (0xFFU) //!< Bit mask for NV_BACKKEY0_KEY.
+#define BS_NV_BACKKEY0_KEY (8U) //!< Bit field size in bits for NV_BACKKEY0_KEY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_BACKKEY0_KEY field.
+#define BR_NV_BACKKEY0_KEY (HW_NV_BACKKEY0.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_BACKKEY7 - Backdoor Comparison Key 7.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_BACKKEY7 - Backdoor Comparison Key 7. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_backkey7
+{
+ uint8_t U;
+ struct _hw_nv_backkey7_bitfields
+ {
+ uint8_t KEY : 8; //!< [7:0] Backdoor Comparison Key.
+ } B;
+} hw_nv_backkey7_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_BACKKEY7 register
+ */
+//@{
+#define HW_NV_BACKKEY7_ADDR (REGS_NV_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_BACKKEY7 (*(__I hw_nv_backkey7_t *) HW_NV_BACKKEY7_ADDR)
+#define HW_NV_BACKKEY7_RD() (HW_NV_BACKKEY7.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_BACKKEY7 bitfields
+ */
+
+/*!
+ * @name Register NV_BACKKEY7, field KEY[7:0] (RO)
+ */
+//@{
+#define BP_NV_BACKKEY7_KEY (0U) //!< Bit position for NV_BACKKEY7_KEY.
+#define BM_NV_BACKKEY7_KEY (0xFFU) //!< Bit mask for NV_BACKKEY7_KEY.
+#define BS_NV_BACKKEY7_KEY (8U) //!< Bit field size in bits for NV_BACKKEY7_KEY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_BACKKEY7_KEY field.
+#define BR_NV_BACKKEY7_KEY (HW_NV_BACKKEY7.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_BACKKEY6 - Backdoor Comparison Key 6.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_BACKKEY6 - Backdoor Comparison Key 6. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_backkey6
+{
+ uint8_t U;
+ struct _hw_nv_backkey6_bitfields
+ {
+ uint8_t KEY : 8; //!< [7:0] Backdoor Comparison Key.
+ } B;
+} hw_nv_backkey6_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_BACKKEY6 register
+ */
+//@{
+#define HW_NV_BACKKEY6_ADDR (REGS_NV_BASE + 0x5U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_BACKKEY6 (*(__I hw_nv_backkey6_t *) HW_NV_BACKKEY6_ADDR)
+#define HW_NV_BACKKEY6_RD() (HW_NV_BACKKEY6.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_BACKKEY6 bitfields
+ */
+
+/*!
+ * @name Register NV_BACKKEY6, field KEY[7:0] (RO)
+ */
+//@{
+#define BP_NV_BACKKEY6_KEY (0U) //!< Bit position for NV_BACKKEY6_KEY.
+#define BM_NV_BACKKEY6_KEY (0xFFU) //!< Bit mask for NV_BACKKEY6_KEY.
+#define BS_NV_BACKKEY6_KEY (8U) //!< Bit field size in bits for NV_BACKKEY6_KEY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_BACKKEY6_KEY field.
+#define BR_NV_BACKKEY6_KEY (HW_NV_BACKKEY6.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_BACKKEY5 - Backdoor Comparison Key 5.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_BACKKEY5 - Backdoor Comparison Key 5. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_backkey5
+{
+ uint8_t U;
+ struct _hw_nv_backkey5_bitfields
+ {
+ uint8_t KEY : 8; //!< [7:0] Backdoor Comparison Key.
+ } B;
+} hw_nv_backkey5_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_BACKKEY5 register
+ */
+//@{
+#define HW_NV_BACKKEY5_ADDR (REGS_NV_BASE + 0x6U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_BACKKEY5 (*(__I hw_nv_backkey5_t *) HW_NV_BACKKEY5_ADDR)
+#define HW_NV_BACKKEY5_RD() (HW_NV_BACKKEY5.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_BACKKEY5 bitfields
+ */
+
+/*!
+ * @name Register NV_BACKKEY5, field KEY[7:0] (RO)
+ */
+//@{
+#define BP_NV_BACKKEY5_KEY (0U) //!< Bit position for NV_BACKKEY5_KEY.
+#define BM_NV_BACKKEY5_KEY (0xFFU) //!< Bit mask for NV_BACKKEY5_KEY.
+#define BS_NV_BACKKEY5_KEY (8U) //!< Bit field size in bits for NV_BACKKEY5_KEY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_BACKKEY5_KEY field.
+#define BR_NV_BACKKEY5_KEY (HW_NV_BACKKEY5.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_BACKKEY4 - Backdoor Comparison Key 4.
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_BACKKEY4 - Backdoor Comparison Key 4. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_backkey4
+{
+ uint8_t U;
+ struct _hw_nv_backkey4_bitfields
+ {
+ uint8_t KEY : 8; //!< [7:0] Backdoor Comparison Key.
+ } B;
+} hw_nv_backkey4_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_BACKKEY4 register
+ */
+//@{
+#define HW_NV_BACKKEY4_ADDR (REGS_NV_BASE + 0x7U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_BACKKEY4 (*(__I hw_nv_backkey4_t *) HW_NV_BACKKEY4_ADDR)
+#define HW_NV_BACKKEY4_RD() (HW_NV_BACKKEY4.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_BACKKEY4 bitfields
+ */
+
+/*!
+ * @name Register NV_BACKKEY4, field KEY[7:0] (RO)
+ */
+//@{
+#define BP_NV_BACKKEY4_KEY (0U) //!< Bit position for NV_BACKKEY4_KEY.
+#define BM_NV_BACKKEY4_KEY (0xFFU) //!< Bit mask for NV_BACKKEY4_KEY.
+#define BS_NV_BACKKEY4_KEY (8U) //!< Bit field size in bits for NV_BACKKEY4_KEY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_BACKKEY4_KEY field.
+#define BR_NV_BACKKEY4_KEY (HW_NV_BACKKEY4.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_fprot3
+{
+ uint8_t U;
+ struct _hw_nv_fprot3_bitfields
+ {
+ uint8_t PROT : 8; //!< [7:0] P-Flash Region Protect
+ } B;
+} hw_nv_fprot3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_FPROT3 register
+ */
+//@{
+#define HW_NV_FPROT3_ADDR (REGS_NV_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_FPROT3 (*(__I hw_nv_fprot3_t *) HW_NV_FPROT3_ADDR)
+#define HW_NV_FPROT3_RD() (HW_NV_FPROT3.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_FPROT3 bitfields
+ */
+
+/*!
+ * @name Register NV_FPROT3, field PROT[7:0] (RO)
+ */
+//@{
+#define BP_NV_FPROT3_PROT (0U) //!< Bit position for NV_FPROT3_PROT.
+#define BM_NV_FPROT3_PROT (0xFFU) //!< Bit mask for NV_FPROT3_PROT.
+#define BS_NV_FPROT3_PROT (8U) //!< Bit field size in bits for NV_FPROT3_PROT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_FPROT3_PROT field.
+#define BR_NV_FPROT3_PROT (HW_NV_FPROT3.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_fprot2
+{
+ uint8_t U;
+ struct _hw_nv_fprot2_bitfields
+ {
+ uint8_t PROT : 8; //!< [7:0] P-Flash Region Protect
+ } B;
+} hw_nv_fprot2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_FPROT2 register
+ */
+//@{
+#define HW_NV_FPROT2_ADDR (REGS_NV_BASE + 0x9U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_FPROT2 (*(__I hw_nv_fprot2_t *) HW_NV_FPROT2_ADDR)
+#define HW_NV_FPROT2_RD() (HW_NV_FPROT2.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_FPROT2 bitfields
+ */
+
+/*!
+ * @name Register NV_FPROT2, field PROT[7:0] (RO)
+ */
+//@{
+#define BP_NV_FPROT2_PROT (0U) //!< Bit position for NV_FPROT2_PROT.
+#define BM_NV_FPROT2_PROT (0xFFU) //!< Bit mask for NV_FPROT2_PROT.
+#define BS_NV_FPROT2_PROT (8U) //!< Bit field size in bits for NV_FPROT2_PROT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_FPROT2_PROT field.
+#define BR_NV_FPROT2_PROT (HW_NV_FPROT2.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_fprot1
+{
+ uint8_t U;
+ struct _hw_nv_fprot1_bitfields
+ {
+ uint8_t PROT : 8; //!< [7:0] P-Flash Region Protect
+ } B;
+} hw_nv_fprot1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_FPROT1 register
+ */
+//@{
+#define HW_NV_FPROT1_ADDR (REGS_NV_BASE + 0xAU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_FPROT1 (*(__I hw_nv_fprot1_t *) HW_NV_FPROT1_ADDR)
+#define HW_NV_FPROT1_RD() (HW_NV_FPROT1.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_FPROT1 bitfields
+ */
+
+/*!
+ * @name Register NV_FPROT1, field PROT[7:0] (RO)
+ */
+//@{
+#define BP_NV_FPROT1_PROT (0U) //!< Bit position for NV_FPROT1_PROT.
+#define BM_NV_FPROT1_PROT (0xFFU) //!< Bit mask for NV_FPROT1_PROT.
+#define BS_NV_FPROT1_PROT (8U) //!< Bit field size in bits for NV_FPROT1_PROT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_FPROT1_PROT field.
+#define BR_NV_FPROT1_PROT (HW_NV_FPROT1.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_fprot0
+{
+ uint8_t U;
+ struct _hw_nv_fprot0_bitfields
+ {
+ uint8_t PROT : 8; //!< [7:0] P-Flash Region Protect
+ } B;
+} hw_nv_fprot0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_FPROT0 register
+ */
+//@{
+#define HW_NV_FPROT0_ADDR (REGS_NV_BASE + 0xBU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_FPROT0 (*(__I hw_nv_fprot0_t *) HW_NV_FPROT0_ADDR)
+#define HW_NV_FPROT0_RD() (HW_NV_FPROT0.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_FPROT0 bitfields
+ */
+
+/*!
+ * @name Register NV_FPROT0, field PROT[7:0] (RO)
+ */
+//@{
+#define BP_NV_FPROT0_PROT (0U) //!< Bit position for NV_FPROT0_PROT.
+#define BM_NV_FPROT0_PROT (0xFFU) //!< Bit mask for NV_FPROT0_PROT.
+#define BS_NV_FPROT0_PROT (8U) //!< Bit field size in bits for NV_FPROT0_PROT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_FPROT0_PROT field.
+#define BR_NV_FPROT0_PROT (HW_NV_FPROT0.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_FSEC - Non-volatile Flash Security Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_FSEC - Non-volatile Flash Security Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_fsec
+{
+ uint8_t U;
+ struct _hw_nv_fsec_bitfields
+ {
+ uint8_t SEC : 2; //!< [1:0] Flash Security
+ uint8_t FSLACC : 2; //!< [3:2] Freescale Failure Analysis Access Code
+ uint8_t MEEN : 2; //!< [5:4]
+ uint8_t KEYEN : 2; //!< [7:6] Backdoor Key Security Enable
+ } B;
+} hw_nv_fsec_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_FSEC register
+ */
+//@{
+#define HW_NV_FSEC_ADDR (REGS_NV_BASE + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_FSEC (*(__I hw_nv_fsec_t *) HW_NV_FSEC_ADDR)
+#define HW_NV_FSEC_RD() (HW_NV_FSEC.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_FSEC bitfields
+ */
+
+/*!
+ * @name Register NV_FSEC, field SEC[1:0] (RO)
+ */
+//@{
+#define BP_NV_FSEC_SEC (0U) //!< Bit position for NV_FSEC_SEC.
+#define BM_NV_FSEC_SEC (0x03U) //!< Bit mask for NV_FSEC_SEC.
+#define BS_NV_FSEC_SEC (2U) //!< Bit field size in bits for NV_FSEC_SEC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_FSEC_SEC field.
+#define BR_NV_FSEC_SEC (HW_NV_FSEC.B.SEC)
+#endif
+//@}
+
+/*!
+ * @name Register NV_FSEC, field FSLACC[3:2] (RO)
+ */
+//@{
+#define BP_NV_FSEC_FSLACC (2U) //!< Bit position for NV_FSEC_FSLACC.
+#define BM_NV_FSEC_FSLACC (0x0CU) //!< Bit mask for NV_FSEC_FSLACC.
+#define BS_NV_FSEC_FSLACC (2U) //!< Bit field size in bits for NV_FSEC_FSLACC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_FSEC_FSLACC field.
+#define BR_NV_FSEC_FSLACC (HW_NV_FSEC.B.FSLACC)
+#endif
+//@}
+
+/*!
+ * @name Register NV_FSEC, field MEEN[5:4] (RO)
+ */
+//@{
+#define BP_NV_FSEC_MEEN (4U) //!< Bit position for NV_FSEC_MEEN.
+#define BM_NV_FSEC_MEEN (0x30U) //!< Bit mask for NV_FSEC_MEEN.
+#define BS_NV_FSEC_MEEN (2U) //!< Bit field size in bits for NV_FSEC_MEEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_FSEC_MEEN field.
+#define BR_NV_FSEC_MEEN (HW_NV_FSEC.B.MEEN)
+#endif
+//@}
+
+/*!
+ * @name Register NV_FSEC, field KEYEN[7:6] (RO)
+ */
+//@{
+#define BP_NV_FSEC_KEYEN (6U) //!< Bit position for NV_FSEC_KEYEN.
+#define BM_NV_FSEC_KEYEN (0xC0U) //!< Bit mask for NV_FSEC_KEYEN.
+#define BS_NV_FSEC_KEYEN (2U) //!< Bit field size in bits for NV_FSEC_KEYEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_FSEC_KEYEN field.
+#define BR_NV_FSEC_KEYEN (HW_NV_FSEC.B.KEYEN)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_FOPT - Non-volatile Flash Option Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_FOPT - Non-volatile Flash Option Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_fopt
+{
+ uint8_t U;
+ struct _hw_nv_fopt_bitfields
+ {
+ uint8_t LPBOOT : 1; //!< [0]
+ uint8_t EZPORT_DIS : 1; //!< [1]
+ uint8_t RESERVED0 : 6; //!< [7:2]
+ } B;
+} hw_nv_fopt_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_FOPT register
+ */
+//@{
+#define HW_NV_FOPT_ADDR (REGS_NV_BASE + 0xDU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_FOPT (*(__I hw_nv_fopt_t *) HW_NV_FOPT_ADDR)
+#define HW_NV_FOPT_RD() (HW_NV_FOPT.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_FOPT bitfields
+ */
+
+/*!
+ * @name Register NV_FOPT, field LPBOOT[0] (RO)
+ */
+//@{
+#define BP_NV_FOPT_LPBOOT (0U) //!< Bit position for NV_FOPT_LPBOOT.
+#define BM_NV_FOPT_LPBOOT (0x01U) //!< Bit mask for NV_FOPT_LPBOOT.
+#define BS_NV_FOPT_LPBOOT (1U) //!< Bit field size in bits for NV_FOPT_LPBOOT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_FOPT_LPBOOT field.
+#define BR_NV_FOPT_LPBOOT (BITBAND_ACCESS8(HW_NV_FOPT_ADDR, BP_NV_FOPT_LPBOOT))
+#endif
+//@}
+
+/*!
+ * @name Register NV_FOPT, field EZPORT_DIS[1] (RO)
+ */
+//@{
+#define BP_NV_FOPT_EZPORT_DIS (1U) //!< Bit position for NV_FOPT_EZPORT_DIS.
+#define BM_NV_FOPT_EZPORT_DIS (0x02U) //!< Bit mask for NV_FOPT_EZPORT_DIS.
+#define BS_NV_FOPT_EZPORT_DIS (1U) //!< Bit field size in bits for NV_FOPT_EZPORT_DIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_FOPT_EZPORT_DIS field.
+#define BR_NV_FOPT_EZPORT_DIS (BITBAND_ACCESS8(HW_NV_FOPT_ADDR, BP_NV_FOPT_EZPORT_DIS))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_FEPROT - Non-volatile EERAM Protection Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_FEPROT - Non-volatile EERAM Protection Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_feprot
+{
+ uint8_t U;
+ struct _hw_nv_feprot_bitfields
+ {
+ uint8_t EPROT : 8; //!< [7:0]
+ } B;
+} hw_nv_feprot_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_FEPROT register
+ */
+//@{
+#define HW_NV_FEPROT_ADDR (REGS_NV_BASE + 0xEU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_FEPROT (*(__I hw_nv_feprot_t *) HW_NV_FEPROT_ADDR)
+#define HW_NV_FEPROT_RD() (HW_NV_FEPROT.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_FEPROT bitfields
+ */
+
+/*!
+ * @name Register NV_FEPROT, field EPROT[7:0] (RO)
+ */
+//@{
+#define BP_NV_FEPROT_EPROT (0U) //!< Bit position for NV_FEPROT_EPROT.
+#define BM_NV_FEPROT_EPROT (0xFFU) //!< Bit mask for NV_FEPROT_EPROT.
+#define BS_NV_FEPROT_EPROT (8U) //!< Bit field size in bits for NV_FEPROT_EPROT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_FEPROT_EPROT field.
+#define BR_NV_FEPROT_EPROT (HW_NV_FEPROT.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_NV_FDPROT - Non-volatile D-Flash Protection Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_NV_FDPROT - Non-volatile D-Flash Protection Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+typedef union _hw_nv_fdprot
+{
+ uint8_t U;
+ struct _hw_nv_fdprot_bitfields
+ {
+ uint8_t DPROT : 8; //!< [7:0] D-Flash Region Protect
+ } B;
+} hw_nv_fdprot_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire NV_FDPROT register
+ */
+//@{
+#define HW_NV_FDPROT_ADDR (REGS_NV_BASE + 0xFU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_NV_FDPROT (*(__I hw_nv_fdprot_t *) HW_NV_FDPROT_ADDR)
+#define HW_NV_FDPROT_RD() (HW_NV_FDPROT.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual NV_FDPROT bitfields
+ */
+
+/*!
+ * @name Register NV_FDPROT, field DPROT[7:0] (RO)
+ */
+//@{
+#define BP_NV_FDPROT_DPROT (0U) //!< Bit position for NV_FDPROT_DPROT.
+#define BM_NV_FDPROT_DPROT (0xFFU) //!< Bit mask for NV_FDPROT_DPROT.
+#define BS_NV_FDPROT_DPROT (8U) //!< Bit field size in bits for NV_FDPROT_DPROT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the NV_FDPROT_DPROT field.
+#define BR_NV_FDPROT_DPROT (HW_NV_FDPROT.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_nv_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All NV module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_nv
+{
+ __I hw_nv_backkey3_t BACKKEY3; //!< [0x0] Backdoor Comparison Key 3.
+ __I hw_nv_backkey2_t BACKKEY2; //!< [0x1] Backdoor Comparison Key 2.
+ __I hw_nv_backkey1_t BACKKEY1; //!< [0x2] Backdoor Comparison Key 1.
+ __I hw_nv_backkey0_t BACKKEY0; //!< [0x3] Backdoor Comparison Key 0.
+ __I hw_nv_backkey7_t BACKKEY7; //!< [0x4] Backdoor Comparison Key 7.
+ __I hw_nv_backkey6_t BACKKEY6; //!< [0x5] Backdoor Comparison Key 6.
+ __I hw_nv_backkey5_t BACKKEY5; //!< [0x6] Backdoor Comparison Key 5.
+ __I hw_nv_backkey4_t BACKKEY4; //!< [0x7] Backdoor Comparison Key 4.
+ __I hw_nv_fprot3_t FPROT3; //!< [0x8] Non-volatile P-Flash Protection 1 - Low Register
+ __I hw_nv_fprot2_t FPROT2; //!< [0x9] Non-volatile P-Flash Protection 1 - High Register
+ __I hw_nv_fprot1_t FPROT1; //!< [0xA] Non-volatile P-Flash Protection 0 - Low Register
+ __I hw_nv_fprot0_t FPROT0; //!< [0xB] Non-volatile P-Flash Protection 0 - High Register
+ __I hw_nv_fsec_t FSEC; //!< [0xC] Non-volatile Flash Security Register
+ __I hw_nv_fopt_t FOPT; //!< [0xD] Non-volatile Flash Option Register
+ __I hw_nv_feprot_t FEPROT; //!< [0xE] Non-volatile EERAM Protection Register
+ __I hw_nv_fdprot_t FDPROT; //!< [0xF] Non-volatile D-Flash Protection Register
+} hw_nv_t;
+#pragma pack()
+
+//! @brief Macro to access all NV registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_NV</code>.
+#define HW_NV (*(hw_nv_t *) REGS_NV_BASE)
+#endif
+
+#endif // __HW_NV_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_osc.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,302 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_OSC_REGISTERS_H__
+#define __HW_OSC_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 OSC
+ *
+ * Oscillator
+ *
+ * Registers defined in this header file:
+ * - HW_OSC_CR - OSC Control Register
+ *
+ * - hw_osc_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_OSC_BASE
+#define HW_OSC_INSTANCE_COUNT (1U) //!< Number of instances of the OSC module.
+#define HW_OSC0 (0U) //!< Instance number for OSC.
+#define REGS_OSC0_BASE (0x40065000U) //!< Base address for OSC.
+
+//! @brief Table of base addresses for OSC instances.
+static const uint32_t __g_regs_OSC_base_addresses[] = {
+ REGS_OSC0_BASE,
+ };
+
+//! @brief Get the base address of OSC by instance number.
+//! @param x OSC instance number, from 0 through 0.
+#define REGS_OSC_BASE(x) (__g_regs_OSC_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of OSC.
+#define REGS_OSC_INSTANCE(b) ((b) == REGS_OSC0_BASE ? HW_OSC0 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_OSC_CR - OSC Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_OSC_CR - OSC Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * After OSC is enabled and starts generating the clocks, the configurations
+ * such as low power and frequency range, must not be changed.
+ */
+typedef union _hw_osc_cr
+{
+ uint8_t U;
+ struct _hw_osc_cr_bitfields
+ {
+ uint8_t SC16P : 1; //!< [0] Oscillator 16 pF Capacitor Load Configure
+ uint8_t SC8P : 1; //!< [1] Oscillator 8 pF Capacitor Load Configure
+ uint8_t SC4P : 1; //!< [2] Oscillator 4 pF Capacitor Load Configure
+ uint8_t SC2P : 1; //!< [3] Oscillator 2 pF Capacitor Load Configure
+ uint8_t RESERVED0 : 1; //!< [4]
+ uint8_t EREFSTEN : 1; //!< [5] External Reference Stop Enable
+ uint8_t RESERVED1 : 1; //!< [6]
+ uint8_t ERCLKEN : 1; //!< [7] External Reference Enable
+ } B;
+} hw_osc_cr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire OSC_CR register
+ */
+//@{
+#define HW_OSC_CR_ADDR(x) (REGS_OSC_BASE(x) + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_OSC_CR(x) (*(__IO hw_osc_cr_t *) HW_OSC_CR_ADDR(x))
+#define HW_OSC_CR_RD(x) (HW_OSC_CR(x).U)
+#define HW_OSC_CR_WR(x, v) (HW_OSC_CR(x).U = (v))
+#define HW_OSC_CR_SET(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) | (v)))
+#define HW_OSC_CR_CLR(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) & ~(v)))
+#define HW_OSC_CR_TOG(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual OSC_CR bitfields
+ */
+
+/*!
+ * @name Register OSC_CR, field SC16P[0] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0 - Disable the selection.
+ * - 1 - Add 16 pF capacitor to the oscillator load.
+ */
+//@{
+#define BP_OSC_CR_SC16P (0U) //!< Bit position for OSC_CR_SC16P.
+#define BM_OSC_CR_SC16P (0x01U) //!< Bit mask for OSC_CR_SC16P.
+#define BS_OSC_CR_SC16P (1U) //!< Bit field size in bits for OSC_CR_SC16P.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the OSC_CR_SC16P field.
+#define BR_OSC_CR_SC16P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC16P))
+#endif
+
+//! @brief Format value for bitfield OSC_CR_SC16P.
+#define BF_OSC_CR_SC16P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_SC16P), uint8_t) & BM_OSC_CR_SC16P)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SC16P field to a new value.
+#define BW_OSC_CR_SC16P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC16P) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register OSC_CR, field SC8P[1] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0 - Disable the selection.
+ * - 1 - Add 8 pF capacitor to the oscillator load.
+ */
+//@{
+#define BP_OSC_CR_SC8P (1U) //!< Bit position for OSC_CR_SC8P.
+#define BM_OSC_CR_SC8P (0x02U) //!< Bit mask for OSC_CR_SC8P.
+#define BS_OSC_CR_SC8P (1U) //!< Bit field size in bits for OSC_CR_SC8P.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the OSC_CR_SC8P field.
+#define BR_OSC_CR_SC8P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC8P))
+#endif
+
+//! @brief Format value for bitfield OSC_CR_SC8P.
+#define BF_OSC_CR_SC8P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_SC8P), uint8_t) & BM_OSC_CR_SC8P)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SC8P field to a new value.
+#define BW_OSC_CR_SC8P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC8P) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register OSC_CR, field SC4P[2] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0 - Disable the selection.
+ * - 1 - Add 4 pF capacitor to the oscillator load.
+ */
+//@{
+#define BP_OSC_CR_SC4P (2U) //!< Bit position for OSC_CR_SC4P.
+#define BM_OSC_CR_SC4P (0x04U) //!< Bit mask for OSC_CR_SC4P.
+#define BS_OSC_CR_SC4P (1U) //!< Bit field size in bits for OSC_CR_SC4P.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the OSC_CR_SC4P field.
+#define BR_OSC_CR_SC4P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC4P))
+#endif
+
+//! @brief Format value for bitfield OSC_CR_SC4P.
+#define BF_OSC_CR_SC4P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_SC4P), uint8_t) & BM_OSC_CR_SC4P)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SC4P field to a new value.
+#define BW_OSC_CR_SC4P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC4P) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register OSC_CR, field SC2P[3] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0 - Disable the selection.
+ * - 1 - Add 2 pF capacitor to the oscillator load.
+ */
+//@{
+#define BP_OSC_CR_SC2P (3U) //!< Bit position for OSC_CR_SC2P.
+#define BM_OSC_CR_SC2P (0x08U) //!< Bit mask for OSC_CR_SC2P.
+#define BS_OSC_CR_SC2P (1U) //!< Bit field size in bits for OSC_CR_SC2P.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the OSC_CR_SC2P field.
+#define BR_OSC_CR_SC2P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC2P))
+#endif
+
+//! @brief Format value for bitfield OSC_CR_SC2P.
+#define BF_OSC_CR_SC2P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_SC2P), uint8_t) & BM_OSC_CR_SC2P)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SC2P field to a new value.
+#define BW_OSC_CR_SC2P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC2P) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register OSC_CR, field EREFSTEN[5] (RW)
+ *
+ * Controls whether or not the external reference clock (OSCERCLK) remains
+ * enabled when MCU enters Stop mode.
+ *
+ * Values:
+ * - 0 - External reference clock is disabled in Stop mode.
+ * - 1 - External reference clock stays enabled in Stop mode if ERCLKEN is set
+ * before entering Stop mode.
+ */
+//@{
+#define BP_OSC_CR_EREFSTEN (5U) //!< Bit position for OSC_CR_EREFSTEN.
+#define BM_OSC_CR_EREFSTEN (0x20U) //!< Bit mask for OSC_CR_EREFSTEN.
+#define BS_OSC_CR_EREFSTEN (1U) //!< Bit field size in bits for OSC_CR_EREFSTEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the OSC_CR_EREFSTEN field.
+#define BR_OSC_CR_EREFSTEN(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_EREFSTEN))
+#endif
+
+//! @brief Format value for bitfield OSC_CR_EREFSTEN.
+#define BF_OSC_CR_EREFSTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_EREFSTEN), uint8_t) & BM_OSC_CR_EREFSTEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EREFSTEN field to a new value.
+#define BW_OSC_CR_EREFSTEN(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_EREFSTEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register OSC_CR, field ERCLKEN[7] (RW)
+ *
+ * Enables external reference clock (OSCERCLK).
+ *
+ * Values:
+ * - 0 - External reference clock is inactive.
+ * - 1 - External reference clock is enabled.
+ */
+//@{
+#define BP_OSC_CR_ERCLKEN (7U) //!< Bit position for OSC_CR_ERCLKEN.
+#define BM_OSC_CR_ERCLKEN (0x80U) //!< Bit mask for OSC_CR_ERCLKEN.
+#define BS_OSC_CR_ERCLKEN (1U) //!< Bit field size in bits for OSC_CR_ERCLKEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the OSC_CR_ERCLKEN field.
+#define BR_OSC_CR_ERCLKEN(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_ERCLKEN))
+#endif
+
+//! @brief Format value for bitfield OSC_CR_ERCLKEN.
+#define BF_OSC_CR_ERCLKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_ERCLKEN), uint8_t) & BM_OSC_CR_ERCLKEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERCLKEN field to a new value.
+#define BW_OSC_CR_ERCLKEN(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_ERCLKEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_osc_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All OSC module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_osc
+{
+ __IO hw_osc_cr_t CR; //!< [0x0] OSC Control Register
+} hw_osc_t;
+#pragma pack()
+
+//! @brief Macro to access all OSC registers.
+//! @param x OSC instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_OSC(0)</code>.
+#define HW_OSC(x) (*(hw_osc_t *) REGS_OSC_BASE(x))
+#endif
+
+#endif // __HW_OSC_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_pdb.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,1433 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_PDB_REGISTERS_H__
+#define __HW_PDB_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 PDB
+ *
+ * Programmable Delay Block
+ *
+ * Registers defined in this header file:
+ * - HW_PDB_SC - Status and Control register
+ * - HW_PDB_MOD - Modulus register
+ * - HW_PDB_CNT - Counter register
+ * - HW_PDB_IDLY - Interrupt Delay register
+ * - HW_PDB_CHnC1 - Channel n Control register 1
+ * - HW_PDB_CHnS - Channel n Status register
+ * - HW_PDB_CHnDLY0 - Channel n Delay 0 register
+ * - HW_PDB_CHnDLY1 - Channel n Delay 1 register
+ * - HW_PDB_DACINTCn - DAC Interval Trigger n Control register
+ * - HW_PDB_DACINTn - DAC Interval n register
+ * - HW_PDB_POEN - Pulse-Out n Enable register
+ * - HW_PDB_POnDLY - Pulse-Out n Delay register
+ *
+ * - hw_pdb_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_PDB_BASE
+#define HW_PDB_INSTANCE_COUNT (1U) //!< Number of instances of the PDB module.
+#define REGS_PDB_BASE (0x40036000U) //!< Base address for PDB0.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PDB_SC - Status and Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PDB_SC - Status and Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_pdb_sc
+{
+ uint32_t U;
+ struct _hw_pdb_sc_bitfields
+ {
+ uint32_t LDOK : 1; //!< [0] Load OK
+ uint32_t CONT : 1; //!< [1] Continuous Mode Enable
+ uint32_t MULT : 2; //!< [3:2] Multiplication Factor Select for
+ //! Prescaler
+ uint32_t RESERVED0 : 1; //!< [4]
+ uint32_t PDBIE : 1; //!< [5] PDB Interrupt Enable
+ uint32_t PDBIF : 1; //!< [6] PDB Interrupt Flag
+ uint32_t PDBEN : 1; //!< [7] PDB Enable
+ uint32_t TRGSEL : 4; //!< [11:8] Trigger Input Source Select
+ uint32_t PRESCALER : 3; //!< [14:12] Prescaler Divider Select
+ uint32_t DMAEN : 1; //!< [15] DMA Enable
+ uint32_t SWTRIG : 1; //!< [16] Software Trigger
+ uint32_t PDBEIE : 1; //!< [17] PDB Sequence Error Interrupt Enable
+ uint32_t LDMOD : 2; //!< [19:18] Load Mode Select
+ uint32_t RESERVED1 : 12; //!< [31:20]
+ } B;
+} hw_pdb_sc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PDB_SC register
+ */
+//@{
+#define HW_PDB_SC_ADDR (REGS_PDB_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PDB_SC (*(__IO hw_pdb_sc_t *) HW_PDB_SC_ADDR)
+#define HW_PDB_SC_RD() (HW_PDB_SC.U)
+#define HW_PDB_SC_WR(v) (HW_PDB_SC.U = (v))
+#define HW_PDB_SC_SET(v) (HW_PDB_SC_WR(HW_PDB_SC_RD() | (v)))
+#define HW_PDB_SC_CLR(v) (HW_PDB_SC_WR(HW_PDB_SC_RD() & ~(v)))
+#define HW_PDB_SC_TOG(v) (HW_PDB_SC_WR(HW_PDB_SC_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PDB_SC bitfields
+ */
+
+/*!
+ * @name Register PDB_SC, field LDOK[0] (RW)
+ *
+ * Writing 1 to this bit updates the internal registers of MOD, IDLY, CHnDLYm,
+ * DACINTx,and POyDLY with the values written to their buffers. The MOD, IDLY,
+ * CHnDLYm, DACINTx, and POyDLY will take effect according to the LDMOD. After 1 is
+ * written to the LDOK field, the values in the buffers of above registers are
+ * not effective and the buffers cannot be written until the values in buffers are
+ * loaded into their internal registers. LDOK can be written only when PDBEN is
+ * set or it can be written at the same time with PDBEN being written to 1. It is
+ * automatically cleared when the values in buffers are loaded into the internal
+ * registers or the PDBEN is cleared. Writing 0 to it has no effect.
+ */
+//@{
+#define BP_PDB_SC_LDOK (0U) //!< Bit position for PDB_SC_LDOK.
+#define BM_PDB_SC_LDOK (0x00000001U) //!< Bit mask for PDB_SC_LDOK.
+#define BS_PDB_SC_LDOK (1U) //!< Bit field size in bits for PDB_SC_LDOK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_SC_LDOK field.
+#define BR_PDB_SC_LDOK (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_LDOK))
+#endif
+
+//! @brief Format value for bitfield PDB_SC_LDOK.
+#define BF_PDB_SC_LDOK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_LDOK), uint32_t) & BM_PDB_SC_LDOK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LDOK field to a new value.
+#define BW_PDB_SC_LDOK(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_LDOK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_SC, field CONT[1] (RW)
+ *
+ * Enables the PDB operation in Continuous mode.
+ *
+ * Values:
+ * - 0 - PDB operation in One-Shot mode
+ * - 1 - PDB operation in Continuous mode
+ */
+//@{
+#define BP_PDB_SC_CONT (1U) //!< Bit position for PDB_SC_CONT.
+#define BM_PDB_SC_CONT (0x00000002U) //!< Bit mask for PDB_SC_CONT.
+#define BS_PDB_SC_CONT (1U) //!< Bit field size in bits for PDB_SC_CONT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_SC_CONT field.
+#define BR_PDB_SC_CONT (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_CONT))
+#endif
+
+//! @brief Format value for bitfield PDB_SC_CONT.
+#define BF_PDB_SC_CONT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_CONT), uint32_t) & BM_PDB_SC_CONT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CONT field to a new value.
+#define BW_PDB_SC_CONT(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_CONT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_SC, field MULT[3:2] (RW)
+ *
+ * Selects the multiplication factor of the prescaler divider for the counter
+ * clock.
+ *
+ * Values:
+ * - 00 - Multiplication factor is 1.
+ * - 01 - Multiplication factor is 10.
+ * - 10 - Multiplication factor is 20.
+ * - 11 - Multiplication factor is 40.
+ */
+//@{
+#define BP_PDB_SC_MULT (2U) //!< Bit position for PDB_SC_MULT.
+#define BM_PDB_SC_MULT (0x0000000CU) //!< Bit mask for PDB_SC_MULT.
+#define BS_PDB_SC_MULT (2U) //!< Bit field size in bits for PDB_SC_MULT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_SC_MULT field.
+#define BR_PDB_SC_MULT (HW_PDB_SC.B.MULT)
+#endif
+
+//! @brief Format value for bitfield PDB_SC_MULT.
+#define BF_PDB_SC_MULT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_MULT), uint32_t) & BM_PDB_SC_MULT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MULT field to a new value.
+#define BW_PDB_SC_MULT(v) (HW_PDB_SC_WR((HW_PDB_SC_RD() & ~BM_PDB_SC_MULT) | BF_PDB_SC_MULT(v)))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_SC, field PDBIE[5] (RW)
+ *
+ * Enables the PDB interrupt. When this field is set and DMAEN is cleared, PDBIF
+ * generates a PDB interrupt.
+ *
+ * Values:
+ * - 0 - PDB interrupt disabled.
+ * - 1 - PDB interrupt enabled.
+ */
+//@{
+#define BP_PDB_SC_PDBIE (5U) //!< Bit position for PDB_SC_PDBIE.
+#define BM_PDB_SC_PDBIE (0x00000020U) //!< Bit mask for PDB_SC_PDBIE.
+#define BS_PDB_SC_PDBIE (1U) //!< Bit field size in bits for PDB_SC_PDBIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_SC_PDBIE field.
+#define BR_PDB_SC_PDBIE (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBIE))
+#endif
+
+//! @brief Format value for bitfield PDB_SC_PDBIE.
+#define BF_PDB_SC_PDBIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_PDBIE), uint32_t) & BM_PDB_SC_PDBIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PDBIE field to a new value.
+#define BW_PDB_SC_PDBIE(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_SC, field PDBIF[6] (RW)
+ *
+ * This field is set when the counter value is equal to the IDLY register.
+ * Writing zero clears this field.
+ */
+//@{
+#define BP_PDB_SC_PDBIF (6U) //!< Bit position for PDB_SC_PDBIF.
+#define BM_PDB_SC_PDBIF (0x00000040U) //!< Bit mask for PDB_SC_PDBIF.
+#define BS_PDB_SC_PDBIF (1U) //!< Bit field size in bits for PDB_SC_PDBIF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_SC_PDBIF field.
+#define BR_PDB_SC_PDBIF (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBIF))
+#endif
+
+//! @brief Format value for bitfield PDB_SC_PDBIF.
+#define BF_PDB_SC_PDBIF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_PDBIF), uint32_t) & BM_PDB_SC_PDBIF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PDBIF field to a new value.
+#define BW_PDB_SC_PDBIF(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBIF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_SC, field PDBEN[7] (RW)
+ *
+ * Values:
+ * - 0 - PDB disabled. Counter is off.
+ * - 1 - PDB enabled.
+ */
+//@{
+#define BP_PDB_SC_PDBEN (7U) //!< Bit position for PDB_SC_PDBEN.
+#define BM_PDB_SC_PDBEN (0x00000080U) //!< Bit mask for PDB_SC_PDBEN.
+#define BS_PDB_SC_PDBEN (1U) //!< Bit field size in bits for PDB_SC_PDBEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_SC_PDBEN field.
+#define BR_PDB_SC_PDBEN (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBEN))
+#endif
+
+//! @brief Format value for bitfield PDB_SC_PDBEN.
+#define BF_PDB_SC_PDBEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_PDBEN), uint32_t) & BM_PDB_SC_PDBEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PDBEN field to a new value.
+#define BW_PDB_SC_PDBEN(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_SC, field TRGSEL[11:8] (RW)
+ *
+ * Selects the trigger input source for the PDB. The trigger input source can be
+ * internal or external (EXTRG pin), or the software trigger. Refer to chip
+ * configuration details for the actual PDB input trigger connections.
+ *
+ * Values:
+ * - 0000 - Trigger-In 0 is selected.
+ * - 0001 - Trigger-In 1 is selected.
+ * - 0010 - Trigger-In 2 is selected.
+ * - 0011 - Trigger-In 3 is selected.
+ * - 0100 - Trigger-In 4 is selected.
+ * - 0101 - Trigger-In 5 is selected.
+ * - 0110 - Trigger-In 6 is selected.
+ * - 0111 - Trigger-In 7 is selected.
+ * - 1000 - Trigger-In 8 is selected.
+ * - 1001 - Trigger-In 9 is selected.
+ * - 1010 - Trigger-In 10 is selected.
+ * - 1011 - Trigger-In 11 is selected.
+ * - 1100 - Trigger-In 12 is selected.
+ * - 1101 - Trigger-In 13 is selected.
+ * - 1110 - Trigger-In 14 is selected.
+ * - 1111 - Software trigger is selected.
+ */
+//@{
+#define BP_PDB_SC_TRGSEL (8U) //!< Bit position for PDB_SC_TRGSEL.
+#define BM_PDB_SC_TRGSEL (0x00000F00U) //!< Bit mask for PDB_SC_TRGSEL.
+#define BS_PDB_SC_TRGSEL (4U) //!< Bit field size in bits for PDB_SC_TRGSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_SC_TRGSEL field.
+#define BR_PDB_SC_TRGSEL (HW_PDB_SC.B.TRGSEL)
+#endif
+
+//! @brief Format value for bitfield PDB_SC_TRGSEL.
+#define BF_PDB_SC_TRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_TRGSEL), uint32_t) & BM_PDB_SC_TRGSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TRGSEL field to a new value.
+#define BW_PDB_SC_TRGSEL(v) (HW_PDB_SC_WR((HW_PDB_SC_RD() & ~BM_PDB_SC_TRGSEL) | BF_PDB_SC_TRGSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_SC, field PRESCALER[14:12] (RW)
+ *
+ * Values:
+ * - 000 - Counting uses the peripheral clock divided by multiplication factor
+ * selected by MULT.
+ * - 001 - Counting uses the peripheral clock divided by twice of the
+ * multiplication factor selected by MULT.
+ * - 010 - Counting uses the peripheral clock divided by four times of the
+ * multiplication factor selected by MULT.
+ * - 011 - Counting uses the peripheral clock divided by eight times of the
+ * multiplication factor selected by MULT.
+ * - 100 - Counting uses the peripheral clock divided by 16 times of the
+ * multiplication factor selected by MULT.
+ * - 101 - Counting uses the peripheral clock divided by 32 times of the
+ * multiplication factor selected by MULT.
+ * - 110 - Counting uses the peripheral clock divided by 64 times of the
+ * multiplication factor selected by MULT.
+ * - 111 - Counting uses the peripheral clock divided by 128 times of the
+ * multiplication factor selected by MULT.
+ */
+//@{
+#define BP_PDB_SC_PRESCALER (12U) //!< Bit position for PDB_SC_PRESCALER.
+#define BM_PDB_SC_PRESCALER (0x00007000U) //!< Bit mask for PDB_SC_PRESCALER.
+#define BS_PDB_SC_PRESCALER (3U) //!< Bit field size in bits for PDB_SC_PRESCALER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_SC_PRESCALER field.
+#define BR_PDB_SC_PRESCALER (HW_PDB_SC.B.PRESCALER)
+#endif
+
+//! @brief Format value for bitfield PDB_SC_PRESCALER.
+#define BF_PDB_SC_PRESCALER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_PRESCALER), uint32_t) & BM_PDB_SC_PRESCALER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PRESCALER field to a new value.
+#define BW_PDB_SC_PRESCALER(v) (HW_PDB_SC_WR((HW_PDB_SC_RD() & ~BM_PDB_SC_PRESCALER) | BF_PDB_SC_PRESCALER(v)))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_SC, field DMAEN[15] (RW)
+ *
+ * When DMA is enabled, the PDBIF flag generates a DMA request instead of an
+ * interrupt.
+ *
+ * Values:
+ * - 0 - DMA disabled.
+ * - 1 - DMA enabled.
+ */
+//@{
+#define BP_PDB_SC_DMAEN (15U) //!< Bit position for PDB_SC_DMAEN.
+#define BM_PDB_SC_DMAEN (0x00008000U) //!< Bit mask for PDB_SC_DMAEN.
+#define BS_PDB_SC_DMAEN (1U) //!< Bit field size in bits for PDB_SC_DMAEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_SC_DMAEN field.
+#define BR_PDB_SC_DMAEN (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_DMAEN))
+#endif
+
+//! @brief Format value for bitfield PDB_SC_DMAEN.
+#define BF_PDB_SC_DMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_DMAEN), uint32_t) & BM_PDB_SC_DMAEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMAEN field to a new value.
+#define BW_PDB_SC_DMAEN(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_DMAEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_SC, field SWTRIG[16] (WORZ)
+ *
+ * When PDB is enabled and the software trigger is selected as the trigger input
+ * source, writing 1 to this field resets and restarts the counter. Writing 0 to
+ * this field has no effect. Reading this field results 0.
+ */
+//@{
+#define BP_PDB_SC_SWTRIG (16U) //!< Bit position for PDB_SC_SWTRIG.
+#define BM_PDB_SC_SWTRIG (0x00010000U) //!< Bit mask for PDB_SC_SWTRIG.
+#define BS_PDB_SC_SWTRIG (1U) //!< Bit field size in bits for PDB_SC_SWTRIG.
+
+//! @brief Format value for bitfield PDB_SC_SWTRIG.
+#define BF_PDB_SC_SWTRIG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_SWTRIG), uint32_t) & BM_PDB_SC_SWTRIG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SWTRIG field to a new value.
+#define BW_PDB_SC_SWTRIG(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_SWTRIG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_SC, field PDBEIE[17] (RW)
+ *
+ * Enables the PDB sequence error interrupt. When this field is set, any of the
+ * PDB channel sequence error flags generates a PDB sequence error interrupt.
+ *
+ * Values:
+ * - 0 - PDB sequence error interrupt disabled.
+ * - 1 - PDB sequence error interrupt enabled.
+ */
+//@{
+#define BP_PDB_SC_PDBEIE (17U) //!< Bit position for PDB_SC_PDBEIE.
+#define BM_PDB_SC_PDBEIE (0x00020000U) //!< Bit mask for PDB_SC_PDBEIE.
+#define BS_PDB_SC_PDBEIE (1U) //!< Bit field size in bits for PDB_SC_PDBEIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_SC_PDBEIE field.
+#define BR_PDB_SC_PDBEIE (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBEIE))
+#endif
+
+//! @brief Format value for bitfield PDB_SC_PDBEIE.
+#define BF_PDB_SC_PDBEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_PDBEIE), uint32_t) & BM_PDB_SC_PDBEIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PDBEIE field to a new value.
+#define BW_PDB_SC_PDBEIE(v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR, BP_PDB_SC_PDBEIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_SC, field LDMOD[19:18] (RW)
+ *
+ * Selects the mode to load the MOD, IDLY, CHnDLYm, INTx, and POyDLY registers,
+ * after 1 is written to LDOK.
+ *
+ * Values:
+ * - 00 - The internal registers are loaded with the values from their buffers
+ * immediately after 1 is written to LDOK.
+ * - 01 - The internal registers are loaded with the values from their buffers
+ * when the PDB counter reaches the MOD register value after 1 is written to
+ * LDOK.
+ * - 10 - The internal registers are loaded with the values from their buffers
+ * when a trigger input event is detected after 1 is written to LDOK.
+ * - 11 - The internal registers are loaded with the values from their buffers
+ * when either the PDB counter reaches the MOD register value or a trigger
+ * input event is detected, after 1 is written to LDOK.
+ */
+//@{
+#define BP_PDB_SC_LDMOD (18U) //!< Bit position for PDB_SC_LDMOD.
+#define BM_PDB_SC_LDMOD (0x000C0000U) //!< Bit mask for PDB_SC_LDMOD.
+#define BS_PDB_SC_LDMOD (2U) //!< Bit field size in bits for PDB_SC_LDMOD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_SC_LDMOD field.
+#define BR_PDB_SC_LDMOD (HW_PDB_SC.B.LDMOD)
+#endif
+
+//! @brief Format value for bitfield PDB_SC_LDMOD.
+#define BF_PDB_SC_LDMOD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_SC_LDMOD), uint32_t) & BM_PDB_SC_LDMOD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LDMOD field to a new value.
+#define BW_PDB_SC_LDMOD(v) (HW_PDB_SC_WR((HW_PDB_SC_RD() & ~BM_PDB_SC_LDMOD) | BF_PDB_SC_LDMOD(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PDB_MOD - Modulus register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PDB_MOD - Modulus register (RW)
+ *
+ * Reset value: 0x0000FFFFU
+ */
+typedef union _hw_pdb_mod
+{
+ uint32_t U;
+ struct _hw_pdb_mod_bitfields
+ {
+ uint32_t MOD : 16; //!< [15:0] PDB Modulus
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_pdb_mod_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PDB_MOD register
+ */
+//@{
+#define HW_PDB_MOD_ADDR (REGS_PDB_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PDB_MOD (*(__IO hw_pdb_mod_t *) HW_PDB_MOD_ADDR)
+#define HW_PDB_MOD_RD() (HW_PDB_MOD.U)
+#define HW_PDB_MOD_WR(v) (HW_PDB_MOD.U = (v))
+#define HW_PDB_MOD_SET(v) (HW_PDB_MOD_WR(HW_PDB_MOD_RD() | (v)))
+#define HW_PDB_MOD_CLR(v) (HW_PDB_MOD_WR(HW_PDB_MOD_RD() & ~(v)))
+#define HW_PDB_MOD_TOG(v) (HW_PDB_MOD_WR(HW_PDB_MOD_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PDB_MOD bitfields
+ */
+
+/*!
+ * @name Register PDB_MOD, field MOD[15:0] (RW)
+ *
+ * Specifies the period of the counter. When the counter reaches this value, it
+ * will be reset back to zero. If the PDB is in Continuous mode, the count begins
+ * anew. Reading this field returns the value of the internal register that is
+ * effective for the current cycle of PDB.
+ */
+//@{
+#define BP_PDB_MOD_MOD (0U) //!< Bit position for PDB_MOD_MOD.
+#define BM_PDB_MOD_MOD (0x0000FFFFU) //!< Bit mask for PDB_MOD_MOD.
+#define BS_PDB_MOD_MOD (16U) //!< Bit field size in bits for PDB_MOD_MOD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_MOD_MOD field.
+#define BR_PDB_MOD_MOD (HW_PDB_MOD.B.MOD)
+#endif
+
+//! @brief Format value for bitfield PDB_MOD_MOD.
+#define BF_PDB_MOD_MOD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_MOD_MOD), uint32_t) & BM_PDB_MOD_MOD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MOD field to a new value.
+#define BW_PDB_MOD_MOD(v) (HW_PDB_MOD_WR((HW_PDB_MOD_RD() & ~BM_PDB_MOD_MOD) | BF_PDB_MOD_MOD(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PDB_CNT - Counter register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PDB_CNT - Counter register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_pdb_cnt
+{
+ uint32_t U;
+ struct _hw_pdb_cnt_bitfields
+ {
+ uint32_t CNT : 16; //!< [15:0] PDB Counter
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_pdb_cnt_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PDB_CNT register
+ */
+//@{
+#define HW_PDB_CNT_ADDR (REGS_PDB_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PDB_CNT (*(__I hw_pdb_cnt_t *) HW_PDB_CNT_ADDR)
+#define HW_PDB_CNT_RD() (HW_PDB_CNT.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PDB_CNT bitfields
+ */
+
+/*!
+ * @name Register PDB_CNT, field CNT[15:0] (RO)
+ *
+ * Contains the current value of the counter.
+ */
+//@{
+#define BP_PDB_CNT_CNT (0U) //!< Bit position for PDB_CNT_CNT.
+#define BM_PDB_CNT_CNT (0x0000FFFFU) //!< Bit mask for PDB_CNT_CNT.
+#define BS_PDB_CNT_CNT (16U) //!< Bit field size in bits for PDB_CNT_CNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_CNT_CNT field.
+#define BR_PDB_CNT_CNT (HW_PDB_CNT.B.CNT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PDB_IDLY - Interrupt Delay register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PDB_IDLY - Interrupt Delay register (RW)
+ *
+ * Reset value: 0x0000FFFFU
+ */
+typedef union _hw_pdb_idly
+{
+ uint32_t U;
+ struct _hw_pdb_idly_bitfields
+ {
+ uint32_t IDLY : 16; //!< [15:0] PDB Interrupt Delay
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_pdb_idly_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PDB_IDLY register
+ */
+//@{
+#define HW_PDB_IDLY_ADDR (REGS_PDB_BASE + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PDB_IDLY (*(__IO hw_pdb_idly_t *) HW_PDB_IDLY_ADDR)
+#define HW_PDB_IDLY_RD() (HW_PDB_IDLY.U)
+#define HW_PDB_IDLY_WR(v) (HW_PDB_IDLY.U = (v))
+#define HW_PDB_IDLY_SET(v) (HW_PDB_IDLY_WR(HW_PDB_IDLY_RD() | (v)))
+#define HW_PDB_IDLY_CLR(v) (HW_PDB_IDLY_WR(HW_PDB_IDLY_RD() & ~(v)))
+#define HW_PDB_IDLY_TOG(v) (HW_PDB_IDLY_WR(HW_PDB_IDLY_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PDB_IDLY bitfields
+ */
+
+/*!
+ * @name Register PDB_IDLY, field IDLY[15:0] (RW)
+ *
+ * Specifies the delay value to schedule the PDB interrupt. It can be used to
+ * schedule an independent interrupt at some point in the PDB cycle. If enabled, a
+ * PDB interrupt is generated, when the counter is equal to the IDLY. Reading
+ * this field returns the value of internal register that is effective for the
+ * current cycle of the PDB.
+ */
+//@{
+#define BP_PDB_IDLY_IDLY (0U) //!< Bit position for PDB_IDLY_IDLY.
+#define BM_PDB_IDLY_IDLY (0x0000FFFFU) //!< Bit mask for PDB_IDLY_IDLY.
+#define BS_PDB_IDLY_IDLY (16U) //!< Bit field size in bits for PDB_IDLY_IDLY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_IDLY_IDLY field.
+#define BR_PDB_IDLY_IDLY (HW_PDB_IDLY.B.IDLY)
+#endif
+
+//! @brief Format value for bitfield PDB_IDLY_IDLY.
+#define BF_PDB_IDLY_IDLY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_IDLY_IDLY), uint32_t) & BM_PDB_IDLY_IDLY)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IDLY field to a new value.
+#define BW_PDB_IDLY_IDLY(v) (HW_PDB_IDLY_WR((HW_PDB_IDLY_RD() & ~BM_PDB_IDLY_IDLY) | BF_PDB_IDLY_IDLY(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PDB_CHnC1 - Channel n Control register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PDB_CHnC1 - Channel n Control register 1 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each PDB channel has one control register, CHnC1. The bits in this register
+ * control the functionality of each PDB channel operation.
+ */
+typedef union _hw_pdb_chnc1
+{
+ uint32_t U;
+ struct _hw_pdb_chnc1_bitfields
+ {
+ uint32_t EN : 8; //!< [7:0] PDB Channel Pre-Trigger Enable
+ uint32_t TOS : 8; //!< [15:8] PDB Channel Pre-Trigger Output Select
+ uint32_t BB : 8; //!< [23:16] PDB Channel Pre-Trigger Back-to-Back
+ //! Operation Enable
+ uint32_t RESERVED0 : 8; //!< [31:24]
+ } B;
+} hw_pdb_chnc1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PDB_CHnC1 register
+ */
+//@{
+#define HW_PDB_CHnC1_COUNT (2U)
+
+#define HW_PDB_CHnC1_ADDR(n) (REGS_PDB_BASE + 0x10U + (0x28U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PDB_CHnC1(n) (*(__IO hw_pdb_chnc1_t *) HW_PDB_CHnC1_ADDR(n))
+#define HW_PDB_CHnC1_RD(n) (HW_PDB_CHnC1(n).U)
+#define HW_PDB_CHnC1_WR(n, v) (HW_PDB_CHnC1(n).U = (v))
+#define HW_PDB_CHnC1_SET(n, v) (HW_PDB_CHnC1_WR(n, HW_PDB_CHnC1_RD(n) | (v)))
+#define HW_PDB_CHnC1_CLR(n, v) (HW_PDB_CHnC1_WR(n, HW_PDB_CHnC1_RD(n) & ~(v)))
+#define HW_PDB_CHnC1_TOG(n, v) (HW_PDB_CHnC1_WR(n, HW_PDB_CHnC1_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PDB_CHnC1 bitfields
+ */
+
+/*!
+ * @name Register PDB_CHnC1, field EN[7:0] (RW)
+ *
+ * These bits enable the PDB ADC pre-trigger outputs. Only lower M pre-trigger
+ * bits are implemented in this MCU.
+ *
+ * Values:
+ * - 0 - PDB channel's corresponding pre-trigger disabled.
+ * - 1 - PDB channel's corresponding pre-trigger enabled.
+ */
+//@{
+#define BP_PDB_CHnC1_EN (0U) //!< Bit position for PDB_CHnC1_EN.
+#define BM_PDB_CHnC1_EN (0x000000FFU) //!< Bit mask for PDB_CHnC1_EN.
+#define BS_PDB_CHnC1_EN (8U) //!< Bit field size in bits for PDB_CHnC1_EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_CHnC1_EN field.
+#define BR_PDB_CHnC1_EN(n) (HW_PDB_CHnC1(n).B.EN)
+#endif
+
+//! @brief Format value for bitfield PDB_CHnC1_EN.
+#define BF_PDB_CHnC1_EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnC1_EN), uint32_t) & BM_PDB_CHnC1_EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EN field to a new value.
+#define BW_PDB_CHnC1_EN(n, v) (HW_PDB_CHnC1_WR(n, (HW_PDB_CHnC1_RD(n) & ~BM_PDB_CHnC1_EN) | BF_PDB_CHnC1_EN(v)))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_CHnC1, field TOS[15:8] (RW)
+ *
+ * Selects the PDB ADC pre-trigger outputs. Only lower M pre-trigger fields are
+ * implemented in this MCU.
+ *
+ * Values:
+ * - 0 - PDB channel's corresponding pre-trigger is in bypassed mode. The
+ * pre-trigger asserts one peripheral clock cycle after a rising edge is detected
+ * on selected trigger input source or software trigger is selected and SWTRIG
+ * is written with 1.
+ * - 1 - PDB channel's corresponding pre-trigger asserts when the counter
+ * reaches the channel delay register and one peripheral clock cycle after a rising
+ * edge is detected on selected trigger input source or software trigger is
+ * selected and SETRIG is written with 1.
+ */
+//@{
+#define BP_PDB_CHnC1_TOS (8U) //!< Bit position for PDB_CHnC1_TOS.
+#define BM_PDB_CHnC1_TOS (0x0000FF00U) //!< Bit mask for PDB_CHnC1_TOS.
+#define BS_PDB_CHnC1_TOS (8U) //!< Bit field size in bits for PDB_CHnC1_TOS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_CHnC1_TOS field.
+#define BR_PDB_CHnC1_TOS(n) (HW_PDB_CHnC1(n).B.TOS)
+#endif
+
+//! @brief Format value for bitfield PDB_CHnC1_TOS.
+#define BF_PDB_CHnC1_TOS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnC1_TOS), uint32_t) & BM_PDB_CHnC1_TOS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TOS field to a new value.
+#define BW_PDB_CHnC1_TOS(n, v) (HW_PDB_CHnC1_WR(n, (HW_PDB_CHnC1_RD(n) & ~BM_PDB_CHnC1_TOS) | BF_PDB_CHnC1_TOS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_CHnC1, field BB[23:16] (RW)
+ *
+ * These bits enable the PDB ADC pre-trigger operation as back-to-back mode.
+ * Only lower M pre-trigger bits are implemented in this MCU. Back-to-back operation
+ * enables the ADC conversions complete to trigger the next PDB channel
+ * pre-trigger and trigger output, so that the ADC conversions can be triggered on next
+ * set of configuration and results registers. Application code must only enable
+ * the back-to-back operation of the PDB pre-triggers at the leading of the
+ * back-to-back connection chain.
+ *
+ * Values:
+ * - 0 - PDB channel's corresponding pre-trigger back-to-back operation disabled.
+ * - 1 - PDB channel's corresponding pre-trigger back-to-back operation enabled.
+ */
+//@{
+#define BP_PDB_CHnC1_BB (16U) //!< Bit position for PDB_CHnC1_BB.
+#define BM_PDB_CHnC1_BB (0x00FF0000U) //!< Bit mask for PDB_CHnC1_BB.
+#define BS_PDB_CHnC1_BB (8U) //!< Bit field size in bits for PDB_CHnC1_BB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_CHnC1_BB field.
+#define BR_PDB_CHnC1_BB(n) (HW_PDB_CHnC1(n).B.BB)
+#endif
+
+//! @brief Format value for bitfield PDB_CHnC1_BB.
+#define BF_PDB_CHnC1_BB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnC1_BB), uint32_t) & BM_PDB_CHnC1_BB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BB field to a new value.
+#define BW_PDB_CHnC1_BB(n, v) (HW_PDB_CHnC1_WR(n, (HW_PDB_CHnC1_RD(n) & ~BM_PDB_CHnC1_BB) | BF_PDB_CHnC1_BB(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_PDB_CHnS - Channel n Status register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PDB_CHnS - Channel n Status register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_pdb_chns
+{
+ uint32_t U;
+ struct _hw_pdb_chns_bitfields
+ {
+ uint32_t ERR : 8; //!< [7:0] PDB Channel Sequence Error Flags
+ uint32_t RESERVED0 : 8; //!< [15:8]
+ uint32_t CF : 8; //!< [23:16] PDB Channel Flags
+ uint32_t RESERVED1 : 8; //!< [31:24]
+ } B;
+} hw_pdb_chns_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PDB_CHnS register
+ */
+//@{
+#define HW_PDB_CHnS_COUNT (2U)
+
+#define HW_PDB_CHnS_ADDR(n) (REGS_PDB_BASE + 0x14U + (0x28U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PDB_CHnS(n) (*(__IO hw_pdb_chns_t *) HW_PDB_CHnS_ADDR(n))
+#define HW_PDB_CHnS_RD(n) (HW_PDB_CHnS(n).U)
+#define HW_PDB_CHnS_WR(n, v) (HW_PDB_CHnS(n).U = (v))
+#define HW_PDB_CHnS_SET(n, v) (HW_PDB_CHnS_WR(n, HW_PDB_CHnS_RD(n) | (v)))
+#define HW_PDB_CHnS_CLR(n, v) (HW_PDB_CHnS_WR(n, HW_PDB_CHnS_RD(n) & ~(v)))
+#define HW_PDB_CHnS_TOG(n, v) (HW_PDB_CHnS_WR(n, HW_PDB_CHnS_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PDB_CHnS bitfields
+ */
+
+/*!
+ * @name Register PDB_CHnS, field ERR[7:0] (RW)
+ *
+ * Only the lower M bits are implemented in this MCU.
+ *
+ * Values:
+ * - 0 - Sequence error not detected on PDB channel's corresponding pre-trigger.
+ * - 1 - Sequence error detected on PDB channel's corresponding pre-trigger.
+ * ADCn block can be triggered for a conversion by one pre-trigger from PDB
+ * channel n. When one conversion, which is triggered by one of the pre-triggers
+ * from PDB channel n, is in progress, new trigger from PDB channel's
+ * corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set.
+ * Writing 0's to clear the sequence error flags.
+ */
+//@{
+#define BP_PDB_CHnS_ERR (0U) //!< Bit position for PDB_CHnS_ERR.
+#define BM_PDB_CHnS_ERR (0x000000FFU) //!< Bit mask for PDB_CHnS_ERR.
+#define BS_PDB_CHnS_ERR (8U) //!< Bit field size in bits for PDB_CHnS_ERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_CHnS_ERR field.
+#define BR_PDB_CHnS_ERR(n) (HW_PDB_CHnS(n).B.ERR)
+#endif
+
+//! @brief Format value for bitfield PDB_CHnS_ERR.
+#define BF_PDB_CHnS_ERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnS_ERR), uint32_t) & BM_PDB_CHnS_ERR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERR field to a new value.
+#define BW_PDB_CHnS_ERR(n, v) (HW_PDB_CHnS_WR(n, (HW_PDB_CHnS_RD(n) & ~BM_PDB_CHnS_ERR) | BF_PDB_CHnS_ERR(v)))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_CHnS, field CF[23:16] (RW)
+ *
+ * The CF[m] bit is set when the PDB counter matches the CHnDLYm. Write 0 to
+ * clear these bits.
+ */
+//@{
+#define BP_PDB_CHnS_CF (16U) //!< Bit position for PDB_CHnS_CF.
+#define BM_PDB_CHnS_CF (0x00FF0000U) //!< Bit mask for PDB_CHnS_CF.
+#define BS_PDB_CHnS_CF (8U) //!< Bit field size in bits for PDB_CHnS_CF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_CHnS_CF field.
+#define BR_PDB_CHnS_CF(n) (HW_PDB_CHnS(n).B.CF)
+#endif
+
+//! @brief Format value for bitfield PDB_CHnS_CF.
+#define BF_PDB_CHnS_CF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnS_CF), uint32_t) & BM_PDB_CHnS_CF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CF field to a new value.
+#define BW_PDB_CHnS_CF(n, v) (HW_PDB_CHnS_WR(n, (HW_PDB_CHnS_RD(n) & ~BM_PDB_CHnS_CF) | BF_PDB_CHnS_CF(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_PDB_CHnDLY0 - Channel n Delay 0 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PDB_CHnDLY0 - Channel n Delay 0 register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_pdb_chndly0
+{
+ uint32_t U;
+ struct _hw_pdb_chndly0_bitfields
+ {
+ uint32_t DLY : 16; //!< [15:0] PDB Channel Delay
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_pdb_chndly0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PDB_CHnDLY0 register
+ */
+//@{
+#define HW_PDB_CHnDLY0_COUNT (2U)
+
+#define HW_PDB_CHnDLY0_ADDR(n) (REGS_PDB_BASE + 0x18U + (0x28U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PDB_CHnDLY0(n) (*(__IO hw_pdb_chndly0_t *) HW_PDB_CHnDLY0_ADDR(n))
+#define HW_PDB_CHnDLY0_RD(n) (HW_PDB_CHnDLY0(n).U)
+#define HW_PDB_CHnDLY0_WR(n, v) (HW_PDB_CHnDLY0(n).U = (v))
+#define HW_PDB_CHnDLY0_SET(n, v) (HW_PDB_CHnDLY0_WR(n, HW_PDB_CHnDLY0_RD(n) | (v)))
+#define HW_PDB_CHnDLY0_CLR(n, v) (HW_PDB_CHnDLY0_WR(n, HW_PDB_CHnDLY0_RD(n) & ~(v)))
+#define HW_PDB_CHnDLY0_TOG(n, v) (HW_PDB_CHnDLY0_WR(n, HW_PDB_CHnDLY0_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PDB_CHnDLY0 bitfields
+ */
+
+/*!
+ * @name Register PDB_CHnDLY0, field DLY[15:0] (RW)
+ *
+ * Specifies the delay value for the channel's corresponding pre-trigger. The
+ * pre-trigger asserts when the counter is equal to DLY. Reading this field returns
+ * the value of internal register that is effective for the current PDB cycle.
+ */
+//@{
+#define BP_PDB_CHnDLY0_DLY (0U) //!< Bit position for PDB_CHnDLY0_DLY.
+#define BM_PDB_CHnDLY0_DLY (0x0000FFFFU) //!< Bit mask for PDB_CHnDLY0_DLY.
+#define BS_PDB_CHnDLY0_DLY (16U) //!< Bit field size in bits for PDB_CHnDLY0_DLY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_CHnDLY0_DLY field.
+#define BR_PDB_CHnDLY0_DLY(n) (HW_PDB_CHnDLY0(n).B.DLY)
+#endif
+
+//! @brief Format value for bitfield PDB_CHnDLY0_DLY.
+#define BF_PDB_CHnDLY0_DLY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnDLY0_DLY), uint32_t) & BM_PDB_CHnDLY0_DLY)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DLY field to a new value.
+#define BW_PDB_CHnDLY0_DLY(n, v) (HW_PDB_CHnDLY0_WR(n, (HW_PDB_CHnDLY0_RD(n) & ~BM_PDB_CHnDLY0_DLY) | BF_PDB_CHnDLY0_DLY(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_PDB_CHnDLY1 - Channel n Delay 1 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PDB_CHnDLY1 - Channel n Delay 1 register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_pdb_chndly1
+{
+ uint32_t U;
+ struct _hw_pdb_chndly1_bitfields
+ {
+ uint32_t DLY : 16; //!< [15:0] PDB Channel Delay
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_pdb_chndly1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PDB_CHnDLY1 register
+ */
+//@{
+#define HW_PDB_CHnDLY1_COUNT (2U)
+
+#define HW_PDB_CHnDLY1_ADDR(n) (REGS_PDB_BASE + 0x1CU + (0x28U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PDB_CHnDLY1(n) (*(__IO hw_pdb_chndly1_t *) HW_PDB_CHnDLY1_ADDR(n))
+#define HW_PDB_CHnDLY1_RD(n) (HW_PDB_CHnDLY1(n).U)
+#define HW_PDB_CHnDLY1_WR(n, v) (HW_PDB_CHnDLY1(n).U = (v))
+#define HW_PDB_CHnDLY1_SET(n, v) (HW_PDB_CHnDLY1_WR(n, HW_PDB_CHnDLY1_RD(n) | (v)))
+#define HW_PDB_CHnDLY1_CLR(n, v) (HW_PDB_CHnDLY1_WR(n, HW_PDB_CHnDLY1_RD(n) & ~(v)))
+#define HW_PDB_CHnDLY1_TOG(n, v) (HW_PDB_CHnDLY1_WR(n, HW_PDB_CHnDLY1_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PDB_CHnDLY1 bitfields
+ */
+
+/*!
+ * @name Register PDB_CHnDLY1, field DLY[15:0] (RW)
+ *
+ * These bits specify the delay value for the channel's corresponding
+ * pre-trigger. The pre-trigger asserts when the counter is equal to DLY. Reading these
+ * bits returns the value of internal register that is effective for the current PDB
+ * cycle.
+ */
+//@{
+#define BP_PDB_CHnDLY1_DLY (0U) //!< Bit position for PDB_CHnDLY1_DLY.
+#define BM_PDB_CHnDLY1_DLY (0x0000FFFFU) //!< Bit mask for PDB_CHnDLY1_DLY.
+#define BS_PDB_CHnDLY1_DLY (16U) //!< Bit field size in bits for PDB_CHnDLY1_DLY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_CHnDLY1_DLY field.
+#define BR_PDB_CHnDLY1_DLY(n) (HW_PDB_CHnDLY1(n).B.DLY)
+#endif
+
+//! @brief Format value for bitfield PDB_CHnDLY1_DLY.
+#define BF_PDB_CHnDLY1_DLY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_CHnDLY1_DLY), uint32_t) & BM_PDB_CHnDLY1_DLY)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DLY field to a new value.
+#define BW_PDB_CHnDLY1_DLY(n, v) (HW_PDB_CHnDLY1_WR(n, (HW_PDB_CHnDLY1_RD(n) & ~BM_PDB_CHnDLY1_DLY) | BF_PDB_CHnDLY1_DLY(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PDB_DACINTCn - DAC Interval Trigger n Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PDB_DACINTCn - DAC Interval Trigger n Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_pdb_dacintcn
+{
+ uint32_t U;
+ struct _hw_pdb_dacintcn_bitfields
+ {
+ uint32_t TOE : 1; //!< [0] DAC Interval Trigger Enable
+ uint32_t EXT : 1; //!< [1] DAC External Trigger Input Enable
+ uint32_t RESERVED0 : 30; //!< [31:2]
+ } B;
+} hw_pdb_dacintcn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PDB_DACINTCn register
+ */
+//@{
+#define HW_PDB_DACINTCn_COUNT (2U)
+
+#define HW_PDB_DACINTCn_ADDR(n) (REGS_PDB_BASE + 0x150U + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PDB_DACINTCn(n) (*(__IO hw_pdb_dacintcn_t *) HW_PDB_DACINTCn_ADDR(n))
+#define HW_PDB_DACINTCn_RD(n) (HW_PDB_DACINTCn(n).U)
+#define HW_PDB_DACINTCn_WR(n, v) (HW_PDB_DACINTCn(n).U = (v))
+#define HW_PDB_DACINTCn_SET(n, v) (HW_PDB_DACINTCn_WR(n, HW_PDB_DACINTCn_RD(n) | (v)))
+#define HW_PDB_DACINTCn_CLR(n, v) (HW_PDB_DACINTCn_WR(n, HW_PDB_DACINTCn_RD(n) & ~(v)))
+#define HW_PDB_DACINTCn_TOG(n, v) (HW_PDB_DACINTCn_WR(n, HW_PDB_DACINTCn_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PDB_DACINTCn bitfields
+ */
+
+/*!
+ * @name Register PDB_DACINTCn, field TOE[0] (RW)
+ *
+ * This bit enables the DAC interval trigger.
+ *
+ * Values:
+ * - 0 - DAC interval trigger disabled.
+ * - 1 - DAC interval trigger enabled.
+ */
+//@{
+#define BP_PDB_DACINTCn_TOE (0U) //!< Bit position for PDB_DACINTCn_TOE.
+#define BM_PDB_DACINTCn_TOE (0x00000001U) //!< Bit mask for PDB_DACINTCn_TOE.
+#define BS_PDB_DACINTCn_TOE (1U) //!< Bit field size in bits for PDB_DACINTCn_TOE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_DACINTCn_TOE field.
+#define BR_PDB_DACINTCn_TOE(n) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(n), BP_PDB_DACINTCn_TOE))
+#endif
+
+//! @brief Format value for bitfield PDB_DACINTCn_TOE.
+#define BF_PDB_DACINTCn_TOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_DACINTCn_TOE), uint32_t) & BM_PDB_DACINTCn_TOE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TOE field to a new value.
+#define BW_PDB_DACINTCn_TOE(n, v) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(n), BP_PDB_DACINTCn_TOE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_DACINTCn, field EXT[1] (RW)
+ *
+ * Enables the external trigger for DAC interval counter.
+ *
+ * Values:
+ * - 0 - DAC external trigger input disabled. DAC interval counter is reset and
+ * counting starts when a rising edge is detected on selected trigger input
+ * source or software trigger is selected and SWTRIG is written with 1.
+ * - 1 - DAC external trigger input enabled. DAC interval counter is bypassed
+ * and DAC external trigger input triggers the DAC interval trigger.
+ */
+//@{
+#define BP_PDB_DACINTCn_EXT (1U) //!< Bit position for PDB_DACINTCn_EXT.
+#define BM_PDB_DACINTCn_EXT (0x00000002U) //!< Bit mask for PDB_DACINTCn_EXT.
+#define BS_PDB_DACINTCn_EXT (1U) //!< Bit field size in bits for PDB_DACINTCn_EXT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_DACINTCn_EXT field.
+#define BR_PDB_DACINTCn_EXT(n) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(n), BP_PDB_DACINTCn_EXT))
+#endif
+
+//! @brief Format value for bitfield PDB_DACINTCn_EXT.
+#define BF_PDB_DACINTCn_EXT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_DACINTCn_EXT), uint32_t) & BM_PDB_DACINTCn_EXT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EXT field to a new value.
+#define BW_PDB_DACINTCn_EXT(n, v) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(n), BP_PDB_DACINTCn_EXT) = (v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_PDB_DACINTn - DAC Interval n register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PDB_DACINTn - DAC Interval n register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_pdb_dacintn
+{
+ uint32_t U;
+ struct _hw_pdb_dacintn_bitfields
+ {
+ uint32_t INT : 16; //!< [15:0] DAC Interval
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_pdb_dacintn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PDB_DACINTn register
+ */
+//@{
+#define HW_PDB_DACINTn_COUNT (2U)
+
+#define HW_PDB_DACINTn_ADDR(n) (REGS_PDB_BASE + 0x154U + (0x8U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PDB_DACINTn(n) (*(__IO hw_pdb_dacintn_t *) HW_PDB_DACINTn_ADDR(n))
+#define HW_PDB_DACINTn_RD(n) (HW_PDB_DACINTn(n).U)
+#define HW_PDB_DACINTn_WR(n, v) (HW_PDB_DACINTn(n).U = (v))
+#define HW_PDB_DACINTn_SET(n, v) (HW_PDB_DACINTn_WR(n, HW_PDB_DACINTn_RD(n) | (v)))
+#define HW_PDB_DACINTn_CLR(n, v) (HW_PDB_DACINTn_WR(n, HW_PDB_DACINTn_RD(n) & ~(v)))
+#define HW_PDB_DACINTn_TOG(n, v) (HW_PDB_DACINTn_WR(n, HW_PDB_DACINTn_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PDB_DACINTn bitfields
+ */
+
+/*!
+ * @name Register PDB_DACINTn, field INT[15:0] (RW)
+ *
+ * Specifies the interval value for DAC interval trigger. DAC interval trigger
+ * triggers DAC[1:0] update when the DAC interval counter is equal to the DACINT.
+ * Reading this field returns the value of internal register that is effective
+ * for the current PDB cycle.
+ */
+//@{
+#define BP_PDB_DACINTn_INT (0U) //!< Bit position for PDB_DACINTn_INT.
+#define BM_PDB_DACINTn_INT (0x0000FFFFU) //!< Bit mask for PDB_DACINTn_INT.
+#define BS_PDB_DACINTn_INT (16U) //!< Bit field size in bits for PDB_DACINTn_INT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_DACINTn_INT field.
+#define BR_PDB_DACINTn_INT(n) (HW_PDB_DACINTn(n).B.INT)
+#endif
+
+//! @brief Format value for bitfield PDB_DACINTn_INT.
+#define BF_PDB_DACINTn_INT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_DACINTn_INT), uint32_t) & BM_PDB_DACINTn_INT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INT field to a new value.
+#define BW_PDB_DACINTn_INT(n, v) (HW_PDB_DACINTn_WR(n, (HW_PDB_DACINTn_RD(n) & ~BM_PDB_DACINTn_INT) | BF_PDB_DACINTn_INT(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PDB_POEN - Pulse-Out n Enable register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PDB_POEN - Pulse-Out n Enable register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_pdb_poen
+{
+ uint32_t U;
+ struct _hw_pdb_poen_bitfields
+ {
+ uint32_t POEN : 8; //!< [7:0] PDB Pulse-Out Enable
+ uint32_t RESERVED0 : 24; //!< [31:8]
+ } B;
+} hw_pdb_poen_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PDB_POEN register
+ */
+//@{
+#define HW_PDB_POEN_ADDR (REGS_PDB_BASE + 0x190U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PDB_POEN (*(__IO hw_pdb_poen_t *) HW_PDB_POEN_ADDR)
+#define HW_PDB_POEN_RD() (HW_PDB_POEN.U)
+#define HW_PDB_POEN_WR(v) (HW_PDB_POEN.U = (v))
+#define HW_PDB_POEN_SET(v) (HW_PDB_POEN_WR(HW_PDB_POEN_RD() | (v)))
+#define HW_PDB_POEN_CLR(v) (HW_PDB_POEN_WR(HW_PDB_POEN_RD() & ~(v)))
+#define HW_PDB_POEN_TOG(v) (HW_PDB_POEN_WR(HW_PDB_POEN_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PDB_POEN bitfields
+ */
+
+/*!
+ * @name Register PDB_POEN, field POEN[7:0] (RW)
+ *
+ * Enables the pulse output. Only lower Y bits are implemented in this MCU.
+ *
+ * Values:
+ * - 0 - PDB Pulse-Out disabled
+ * - 1 - PDB Pulse-Out enabled
+ */
+//@{
+#define BP_PDB_POEN_POEN (0U) //!< Bit position for PDB_POEN_POEN.
+#define BM_PDB_POEN_POEN (0x000000FFU) //!< Bit mask for PDB_POEN_POEN.
+#define BS_PDB_POEN_POEN (8U) //!< Bit field size in bits for PDB_POEN_POEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_POEN_POEN field.
+#define BR_PDB_POEN_POEN (HW_PDB_POEN.B.POEN)
+#endif
+
+//! @brief Format value for bitfield PDB_POEN_POEN.
+#define BF_PDB_POEN_POEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_POEN_POEN), uint32_t) & BM_PDB_POEN_POEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the POEN field to a new value.
+#define BW_PDB_POEN_POEN(v) (HW_PDB_POEN_WR((HW_PDB_POEN_RD() & ~BM_PDB_POEN_POEN) | BF_PDB_POEN_POEN(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PDB_POnDLY - Pulse-Out n Delay register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PDB_POnDLY - Pulse-Out n Delay register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_pdb_pondly
+{
+ uint32_t U;
+ struct _hw_pdb_pondly_bitfields
+ {
+ uint32_t DLY2 : 16; //!< [15:0] PDB Pulse-Out Delay 2
+ uint32_t DLY1 : 16; //!< [31:16] PDB Pulse-Out Delay 1
+ } B;
+} hw_pdb_pondly_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PDB_POnDLY register
+ */
+//@{
+#define HW_PDB_POnDLY_COUNT (3U)
+
+#define HW_PDB_POnDLY_ADDR(n) (REGS_PDB_BASE + 0x194U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PDB_POnDLY(n) (*(__IO hw_pdb_pondly_t *) HW_PDB_POnDLY_ADDR(n))
+#define HW_PDB_POnDLY_RD(n) (HW_PDB_POnDLY(n).U)
+#define HW_PDB_POnDLY_WR(n, v) (HW_PDB_POnDLY(n).U = (v))
+#define HW_PDB_POnDLY_SET(n, v) (HW_PDB_POnDLY_WR(n, HW_PDB_POnDLY_RD(n) | (v)))
+#define HW_PDB_POnDLY_CLR(n, v) (HW_PDB_POnDLY_WR(n, HW_PDB_POnDLY_RD(n) & ~(v)))
+#define HW_PDB_POnDLY_TOG(n, v) (HW_PDB_POnDLY_WR(n, HW_PDB_POnDLY_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PDB_POnDLY bitfields
+ */
+
+/*!
+ * @name Register PDB_POnDLY, field DLY2[15:0] (RW)
+ *
+ * These bits specify the delay 2 value for the PDB Pulse-Out. Pulse-Out goes
+ * low when the PDB counter is equal to the DLY2. Reading these bits returns the
+ * value of internal register that is effective for the current PDB cycle.
+ */
+//@{
+#define BP_PDB_POnDLY_DLY2 (0U) //!< Bit position for PDB_POnDLY_DLY2.
+#define BM_PDB_POnDLY_DLY2 (0x0000FFFFU) //!< Bit mask for PDB_POnDLY_DLY2.
+#define BS_PDB_POnDLY_DLY2 (16U) //!< Bit field size in bits for PDB_POnDLY_DLY2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_POnDLY_DLY2 field.
+#define BR_PDB_POnDLY_DLY2(n) (HW_PDB_POnDLY(n).B.DLY2)
+#endif
+
+//! @brief Format value for bitfield PDB_POnDLY_DLY2.
+#define BF_PDB_POnDLY_DLY2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_POnDLY_DLY2), uint32_t) & BM_PDB_POnDLY_DLY2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DLY2 field to a new value.
+#define BW_PDB_POnDLY_DLY2(n, v) (HW_PDB_POnDLY_WR(n, (HW_PDB_POnDLY_RD(n) & ~BM_PDB_POnDLY_DLY2) | BF_PDB_POnDLY_DLY2(v)))
+#endif
+//@}
+
+/*!
+ * @name Register PDB_POnDLY, field DLY1[31:16] (RW)
+ *
+ * These bits specify the delay 1 value for the PDB Pulse-Out. Pulse-Out goes
+ * high when the PDB counter is equal to the DLY1. Reading these bits returns the
+ * value of internal register that is effective for the current PDB cycle.
+ */
+//@{
+#define BP_PDB_POnDLY_DLY1 (16U) //!< Bit position for PDB_POnDLY_DLY1.
+#define BM_PDB_POnDLY_DLY1 (0xFFFF0000U) //!< Bit mask for PDB_POnDLY_DLY1.
+#define BS_PDB_POnDLY_DLY1 (16U) //!< Bit field size in bits for PDB_POnDLY_DLY1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PDB_POnDLY_DLY1 field.
+#define BR_PDB_POnDLY_DLY1(n) (HW_PDB_POnDLY(n).B.DLY1)
+#endif
+
+//! @brief Format value for bitfield PDB_POnDLY_DLY1.
+#define BF_PDB_POnDLY_DLY1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PDB_POnDLY_DLY1), uint32_t) & BM_PDB_POnDLY_DLY1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DLY1 field to a new value.
+#define BW_PDB_POnDLY_DLY1(n, v) (HW_PDB_POnDLY_WR(n, (HW_PDB_POnDLY_RD(n) & ~BM_PDB_POnDLY_DLY1) | BF_PDB_POnDLY_DLY1(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_pdb_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All PDB module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_pdb
+{
+ __IO hw_pdb_sc_t SC; //!< [0x0] Status and Control register
+ __IO hw_pdb_mod_t MOD; //!< [0x4] Modulus register
+ __I hw_pdb_cnt_t CNT; //!< [0x8] Counter register
+ __IO hw_pdb_idly_t IDLY; //!< [0xC] Interrupt Delay register
+ struct {
+ __IO hw_pdb_chnc1_t CHnC1; //!< [0x10] Channel n Control register 1
+ __IO hw_pdb_chns_t CHnS; //!< [0x14] Channel n Status register
+ __IO hw_pdb_chndly0_t CHnDLY0; //!< [0x18] Channel n Delay 0 register
+ __IO hw_pdb_chndly1_t CHnDLY1; //!< [0x1C] Channel n Delay 1 register
+ uint8_t _reserved0[24];
+ } CH[2];
+ uint8_t _reserved0[240];
+ struct {
+ __IO hw_pdb_dacintcn_t DACINTCn; //!< [0x150] DAC Interval Trigger n Control register
+ __IO hw_pdb_dacintn_t DACINTn; //!< [0x154] DAC Interval n register
+ } DAC[2];
+ uint8_t _reserved1[48];
+ __IO hw_pdb_poen_t POEN; //!< [0x190] Pulse-Out n Enable register
+ __IO hw_pdb_pondly_t POnDLY[3]; //!< [0x194] Pulse-Out n Delay register
+} hw_pdb_t;
+#pragma pack()
+
+//! @brief Macro to access all PDB registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_PDB</code>.
+#define HW_PDB (*(hw_pdb_t *) REGS_PDB_BASE)
+#endif
+
+#endif // __HW_PDB_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_pit.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,517 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_PIT_REGISTERS_H__
+#define __HW_PIT_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 PIT
+ *
+ * Periodic Interrupt Timer
+ *
+ * Registers defined in this header file:
+ * - HW_PIT_MCR - PIT Module Control Register
+ * - HW_PIT_LDVALn - Timer Load Value Register
+ * - HW_PIT_CVALn - Current Timer Value Register
+ * - HW_PIT_TCTRLn - Timer Control Register
+ * - HW_PIT_TFLGn - Timer Flag Register
+ *
+ * - hw_pit_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_PIT_BASE
+#define HW_PIT_INSTANCE_COUNT (1U) //!< Number of instances of the PIT module.
+#define REGS_PIT_BASE (0x40037000U) //!< Base address for PIT.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PIT_MCR - PIT Module Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PIT_MCR - PIT Module Control Register (RW)
+ *
+ * Reset value: 0x00000006U
+ *
+ * This register enables or disables the PIT timer clocks and controls the
+ * timers when the PIT enters the Debug mode.
+ */
+typedef union _hw_pit_mcr
+{
+ uint32_t U;
+ struct _hw_pit_mcr_bitfields
+ {
+ uint32_t FRZ : 1; //!< [0] Freeze
+ uint32_t MDIS : 1; //!< [1] Module Disable - (PIT section)
+ uint32_t RESERVED0 : 30; //!< [31:2]
+ } B;
+} hw_pit_mcr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PIT_MCR register
+ */
+//@{
+#define HW_PIT_MCR_ADDR (REGS_PIT_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PIT_MCR (*(__IO hw_pit_mcr_t *) HW_PIT_MCR_ADDR)
+#define HW_PIT_MCR_RD() (HW_PIT_MCR.U)
+#define HW_PIT_MCR_WR(v) (HW_PIT_MCR.U = (v))
+#define HW_PIT_MCR_SET(v) (HW_PIT_MCR_WR(HW_PIT_MCR_RD() | (v)))
+#define HW_PIT_MCR_CLR(v) (HW_PIT_MCR_WR(HW_PIT_MCR_RD() & ~(v)))
+#define HW_PIT_MCR_TOG(v) (HW_PIT_MCR_WR(HW_PIT_MCR_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PIT_MCR bitfields
+ */
+
+/*!
+ * @name Register PIT_MCR, field FRZ[0] (RW)
+ *
+ * Allows the timers to be stopped when the device enters the Debug mode.
+ *
+ * Values:
+ * - 0 - Timers continue to run in Debug mode.
+ * - 1 - Timers are stopped in Debug mode.
+ */
+//@{
+#define BP_PIT_MCR_FRZ (0U) //!< Bit position for PIT_MCR_FRZ.
+#define BM_PIT_MCR_FRZ (0x00000001U) //!< Bit mask for PIT_MCR_FRZ.
+#define BS_PIT_MCR_FRZ (1U) //!< Bit field size in bits for PIT_MCR_FRZ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PIT_MCR_FRZ field.
+#define BR_PIT_MCR_FRZ (BITBAND_ACCESS32(HW_PIT_MCR_ADDR, BP_PIT_MCR_FRZ))
+#endif
+
+//! @brief Format value for bitfield PIT_MCR_FRZ.
+#define BF_PIT_MCR_FRZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_MCR_FRZ), uint32_t) & BM_PIT_MCR_FRZ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FRZ field to a new value.
+#define BW_PIT_MCR_FRZ(v) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR, BP_PIT_MCR_FRZ) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PIT_MCR, field MDIS[1] (RW)
+ *
+ * Disables the standard timers. This field must be enabled before any other
+ * setup is done.
+ *
+ * Values:
+ * - 0 - Clock for standard PIT timers is enabled.
+ * - 1 - Clock for standard PIT timers is disabled.
+ */
+//@{
+#define BP_PIT_MCR_MDIS (1U) //!< Bit position for PIT_MCR_MDIS.
+#define BM_PIT_MCR_MDIS (0x00000002U) //!< Bit mask for PIT_MCR_MDIS.
+#define BS_PIT_MCR_MDIS (1U) //!< Bit field size in bits for PIT_MCR_MDIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PIT_MCR_MDIS field.
+#define BR_PIT_MCR_MDIS (BITBAND_ACCESS32(HW_PIT_MCR_ADDR, BP_PIT_MCR_MDIS))
+#endif
+
+//! @brief Format value for bitfield PIT_MCR_MDIS.
+#define BF_PIT_MCR_MDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_MCR_MDIS), uint32_t) & BM_PIT_MCR_MDIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MDIS field to a new value.
+#define BW_PIT_MCR_MDIS(v) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR, BP_PIT_MCR_MDIS) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PIT_LDVALn - Timer Load Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PIT_LDVALn - Timer Load Value Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers select the timeout period for the timer interrupts.
+ */
+typedef union _hw_pit_ldvaln
+{
+ uint32_t U;
+ struct _hw_pit_ldvaln_bitfields
+ {
+ uint32_t TSV : 32; //!< [31:0] Timer Start Value
+ } B;
+} hw_pit_ldvaln_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PIT_LDVALn register
+ */
+//@{
+#define HW_PIT_LDVALn_COUNT (4U)
+
+#define HW_PIT_LDVALn_ADDR(n) (REGS_PIT_BASE + 0x100U + (0x10U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PIT_LDVALn(n) (*(__IO hw_pit_ldvaln_t *) HW_PIT_LDVALn_ADDR(n))
+#define HW_PIT_LDVALn_RD(n) (HW_PIT_LDVALn(n).U)
+#define HW_PIT_LDVALn_WR(n, v) (HW_PIT_LDVALn(n).U = (v))
+#define HW_PIT_LDVALn_SET(n, v) (HW_PIT_LDVALn_WR(n, HW_PIT_LDVALn_RD(n) | (v)))
+#define HW_PIT_LDVALn_CLR(n, v) (HW_PIT_LDVALn_WR(n, HW_PIT_LDVALn_RD(n) & ~(v)))
+#define HW_PIT_LDVALn_TOG(n, v) (HW_PIT_LDVALn_WR(n, HW_PIT_LDVALn_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PIT_LDVALn bitfields
+ */
+
+/*!
+ * @name Register PIT_LDVALn, field TSV[31:0] (RW)
+ *
+ * Sets the timer start value. The timer will count down until it reaches 0,
+ * then it will generate an interrupt and load this register value again. Writing a
+ * new value to this register will not restart the timer; instead the value will
+ * be loaded after the timer expires. To abort the current cycle and start a
+ * timer period with the new value, the timer must be disabled and enabled again.
+ */
+//@{
+#define BP_PIT_LDVALn_TSV (0U) //!< Bit position for PIT_LDVALn_TSV.
+#define BM_PIT_LDVALn_TSV (0xFFFFFFFFU) //!< Bit mask for PIT_LDVALn_TSV.
+#define BS_PIT_LDVALn_TSV (32U) //!< Bit field size in bits for PIT_LDVALn_TSV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PIT_LDVALn_TSV field.
+#define BR_PIT_LDVALn_TSV(n) (HW_PIT_LDVALn(n).U)
+#endif
+
+//! @brief Format value for bitfield PIT_LDVALn_TSV.
+#define BF_PIT_LDVALn_TSV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_LDVALn_TSV), uint32_t) & BM_PIT_LDVALn_TSV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TSV field to a new value.
+#define BW_PIT_LDVALn_TSV(n, v) (HW_PIT_LDVALn_WR(n, v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_PIT_CVALn - Current Timer Value Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PIT_CVALn - Current Timer Value Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers indicate the current timer position.
+ */
+typedef union _hw_pit_cvaln
+{
+ uint32_t U;
+ struct _hw_pit_cvaln_bitfields
+ {
+ uint32_t TVL : 32; //!< [31:0] Current Timer Value
+ } B;
+} hw_pit_cvaln_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PIT_CVALn register
+ */
+//@{
+#define HW_PIT_CVALn_COUNT (4U)
+
+#define HW_PIT_CVALn_ADDR(n) (REGS_PIT_BASE + 0x104U + (0x10U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PIT_CVALn(n) (*(__I hw_pit_cvaln_t *) HW_PIT_CVALn_ADDR(n))
+#define HW_PIT_CVALn_RD(n) (HW_PIT_CVALn(n).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PIT_CVALn bitfields
+ */
+
+/*!
+ * @name Register PIT_CVALn, field TVL[31:0] (RO)
+ *
+ * Represents the current timer value, if the timer is enabled. If the timer is
+ * disabled, do not use this field as its value is unreliable. The timer uses a
+ * downcounter. The timer values are frozen in Debug mode if MCR[FRZ] is set.
+ */
+//@{
+#define BP_PIT_CVALn_TVL (0U) //!< Bit position for PIT_CVALn_TVL.
+#define BM_PIT_CVALn_TVL (0xFFFFFFFFU) //!< Bit mask for PIT_CVALn_TVL.
+#define BS_PIT_CVALn_TVL (32U) //!< Bit field size in bits for PIT_CVALn_TVL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PIT_CVALn_TVL field.
+#define BR_PIT_CVALn_TVL(n) (HW_PIT_CVALn(n).U)
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_PIT_TCTRLn - Timer Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PIT_TCTRLn - Timer Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers contain the control bits for each timer.
+ */
+typedef union _hw_pit_tctrln
+{
+ uint32_t U;
+ struct _hw_pit_tctrln_bitfields
+ {
+ uint32_t TEN : 1; //!< [0] Timer Enable
+ uint32_t TIE : 1; //!< [1] Timer Interrupt Enable
+ uint32_t CHN : 1; //!< [2] Chain Mode
+ uint32_t RESERVED0 : 29; //!< [31:3]
+ } B;
+} hw_pit_tctrln_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PIT_TCTRLn register
+ */
+//@{
+#define HW_PIT_TCTRLn_COUNT (4U)
+
+#define HW_PIT_TCTRLn_ADDR(n) (REGS_PIT_BASE + 0x108U + (0x10U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PIT_TCTRLn(n) (*(__IO hw_pit_tctrln_t *) HW_PIT_TCTRLn_ADDR(n))
+#define HW_PIT_TCTRLn_RD(n) (HW_PIT_TCTRLn(n).U)
+#define HW_PIT_TCTRLn_WR(n, v) (HW_PIT_TCTRLn(n).U = (v))
+#define HW_PIT_TCTRLn_SET(n, v) (HW_PIT_TCTRLn_WR(n, HW_PIT_TCTRLn_RD(n) | (v)))
+#define HW_PIT_TCTRLn_CLR(n, v) (HW_PIT_TCTRLn_WR(n, HW_PIT_TCTRLn_RD(n) & ~(v)))
+#define HW_PIT_TCTRLn_TOG(n, v) (HW_PIT_TCTRLn_WR(n, HW_PIT_TCTRLn_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PIT_TCTRLn bitfields
+ */
+
+/*!
+ * @name Register PIT_TCTRLn, field TEN[0] (RW)
+ *
+ * Enables or disables the timer.
+ *
+ * Values:
+ * - 0 - Timer n is disabled.
+ * - 1 - Timer n is enabled.
+ */
+//@{
+#define BP_PIT_TCTRLn_TEN (0U) //!< Bit position for PIT_TCTRLn_TEN.
+#define BM_PIT_TCTRLn_TEN (0x00000001U) //!< Bit mask for PIT_TCTRLn_TEN.
+#define BS_PIT_TCTRLn_TEN (1U) //!< Bit field size in bits for PIT_TCTRLn_TEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PIT_TCTRLn_TEN field.
+#define BR_PIT_TCTRLn_TEN(n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_TEN))
+#endif
+
+//! @brief Format value for bitfield PIT_TCTRLn_TEN.
+#define BF_PIT_TCTRLn_TEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_TCTRLn_TEN), uint32_t) & BM_PIT_TCTRLn_TEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TEN field to a new value.
+#define BW_PIT_TCTRLn_TEN(n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_TEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PIT_TCTRLn, field TIE[1] (RW)
+ *
+ * When an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt
+ * will immediately cause an interrupt event. To avoid this, the associated
+ * TFLGn[TIF] must be cleared first.
+ *
+ * Values:
+ * - 0 - Interrupt requests from Timer n are disabled.
+ * - 1 - Interrupt will be requested whenever TIF is set.
+ */
+//@{
+#define BP_PIT_TCTRLn_TIE (1U) //!< Bit position for PIT_TCTRLn_TIE.
+#define BM_PIT_TCTRLn_TIE (0x00000002U) //!< Bit mask for PIT_TCTRLn_TIE.
+#define BS_PIT_TCTRLn_TIE (1U) //!< Bit field size in bits for PIT_TCTRLn_TIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PIT_TCTRLn_TIE field.
+#define BR_PIT_TCTRLn_TIE(n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_TIE))
+#endif
+
+//! @brief Format value for bitfield PIT_TCTRLn_TIE.
+#define BF_PIT_TCTRLn_TIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_TCTRLn_TIE), uint32_t) & BM_PIT_TCTRLn_TIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TIE field to a new value.
+#define BW_PIT_TCTRLn_TIE(n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_TIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PIT_TCTRLn, field CHN[2] (RW)
+ *
+ * When activated, Timer n-1 needs to expire before timer n can decrement by 1.
+ * Timer 0 cannot be chained.
+ *
+ * Values:
+ * - 0 - Timer is not chained.
+ * - 1 - Timer is chained to previous timer. For example, for Channel 2, if this
+ * field is set, Timer 2 is chained to Timer 1.
+ */
+//@{
+#define BP_PIT_TCTRLn_CHN (2U) //!< Bit position for PIT_TCTRLn_CHN.
+#define BM_PIT_TCTRLn_CHN (0x00000004U) //!< Bit mask for PIT_TCTRLn_CHN.
+#define BS_PIT_TCTRLn_CHN (1U) //!< Bit field size in bits for PIT_TCTRLn_CHN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PIT_TCTRLn_CHN field.
+#define BR_PIT_TCTRLn_CHN(n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_CHN))
+#endif
+
+//! @brief Format value for bitfield PIT_TCTRLn_CHN.
+#define BF_PIT_TCTRLn_CHN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_TCTRLn_CHN), uint32_t) & BM_PIT_TCTRLn_CHN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CHN field to a new value.
+#define BW_PIT_TCTRLn_CHN(n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_CHN) = (v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_PIT_TFLGn - Timer Flag Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PIT_TFLGn - Timer Flag Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers hold the PIT interrupt flags.
+ */
+typedef union _hw_pit_tflgn
+{
+ uint32_t U;
+ struct _hw_pit_tflgn_bitfields
+ {
+ uint32_t TIF : 1; //!< [0] Timer Interrupt Flag
+ uint32_t RESERVED0 : 31; //!< [31:1]
+ } B;
+} hw_pit_tflgn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PIT_TFLGn register
+ */
+//@{
+#define HW_PIT_TFLGn_COUNT (4U)
+
+#define HW_PIT_TFLGn_ADDR(n) (REGS_PIT_BASE + 0x10CU + (0x10U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PIT_TFLGn(n) (*(__IO hw_pit_tflgn_t *) HW_PIT_TFLGn_ADDR(n))
+#define HW_PIT_TFLGn_RD(n) (HW_PIT_TFLGn(n).U)
+#define HW_PIT_TFLGn_WR(n, v) (HW_PIT_TFLGn(n).U = (v))
+#define HW_PIT_TFLGn_SET(n, v) (HW_PIT_TFLGn_WR(n, HW_PIT_TFLGn_RD(n) | (v)))
+#define HW_PIT_TFLGn_CLR(n, v) (HW_PIT_TFLGn_WR(n, HW_PIT_TFLGn_RD(n) & ~(v)))
+#define HW_PIT_TFLGn_TOG(n, v) (HW_PIT_TFLGn_WR(n, HW_PIT_TFLGn_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PIT_TFLGn bitfields
+ */
+
+/*!
+ * @name Register PIT_TFLGn, field TIF[0] (W1C)
+ *
+ * Sets to 1 at the end of the timer period. Writing 1 to this flag clears it.
+ * Writing 0 has no effect. If enabled, or, when TCTRLn[TIE] = 1, TIF causes an
+ * interrupt request.
+ *
+ * Values:
+ * - 0 - Timeout has not yet occurred.
+ * - 1 - Timeout has occurred.
+ */
+//@{
+#define BP_PIT_TFLGn_TIF (0U) //!< Bit position for PIT_TFLGn_TIF.
+#define BM_PIT_TFLGn_TIF (0x00000001U) //!< Bit mask for PIT_TFLGn_TIF.
+#define BS_PIT_TFLGn_TIF (1U) //!< Bit field size in bits for PIT_TFLGn_TIF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PIT_TFLGn_TIF field.
+#define BR_PIT_TFLGn_TIF(n) (BITBAND_ACCESS32(HW_PIT_TFLGn_ADDR(n), BP_PIT_TFLGn_TIF))
+#endif
+
+//! @brief Format value for bitfield PIT_TFLGn_TIF.
+#define BF_PIT_TFLGn_TIF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_TFLGn_TIF), uint32_t) & BM_PIT_TFLGn_TIF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TIF field to a new value.
+#define BW_PIT_TFLGn_TIF(n, v) (BITBAND_ACCESS32(HW_PIT_TFLGn_ADDR(n), BP_PIT_TFLGn_TIF) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_pit_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All PIT module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_pit
+{
+ __IO hw_pit_mcr_t MCR; //!< [0x0] PIT Module Control Register
+ uint8_t _reserved0[252];
+ struct {
+ __IO hw_pit_ldvaln_t LDVALn; //!< [0x100] Timer Load Value Register
+ __I hw_pit_cvaln_t CVALn; //!< [0x104] Current Timer Value Register
+ __IO hw_pit_tctrln_t TCTRLn; //!< [0x108] Timer Control Register
+ __IO hw_pit_tflgn_t TFLGn; //!< [0x10C] Timer Flag Register
+ } CHANNEL[4];
+} hw_pit_t;
+#pragma pack()
+
+//! @brief Macro to access all PIT registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_PIT</code>.
+#define HW_PIT (*(hw_pit_t *) REGS_PIT_BASE)
+#endif
+
+#endif // __HW_PIT_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_pmc.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,577 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_PMC_REGISTERS_H__
+#define __HW_PMC_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 PMC
+ *
+ * Power Management Controller
+ *
+ * Registers defined in this header file:
+ * - HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
+ * - HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
+ * - HW_PMC_REGSC - Regulator Status And Control register
+ *
+ * - hw_pmc_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_PMC_BASE
+#define HW_PMC_INSTANCE_COUNT (1U) //!< Number of instances of the PMC module.
+#define REGS_PMC_BASE (0x4007D000U) //!< Base address for PMC.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register (RW)
+ *
+ * Reset value: 0x10U
+ *
+ * This register contains status and control bits to support the low voltage
+ * detect function. This register should be written during the reset initialization
+ * program to set the desired controls even if the desired settings are the same
+ * as the reset settings. While the device is in the very low power or low
+ * leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect
+ * systems that must have LVD always on, configure the Power Mode Protection
+ * (PMPROT) register of the SMC module (SMC_PMPROT) to disallow any very low power or
+ * low leakage modes from being enabled. See the device's data sheet for the
+ * exact LVD trip voltages. The LVDV bits are reset solely on a POR Only event. The
+ * register's other bits are reset on Chip Reset Not VLLS. For more information
+ * about these reset types, refer to the Reset section details.
+ */
+typedef union _hw_pmc_lvdsc1
+{
+ uint8_t U;
+ struct _hw_pmc_lvdsc1_bitfields
+ {
+ uint8_t LVDV : 2; //!< [1:0] Low-Voltage Detect Voltage Select
+ uint8_t RESERVED0 : 2; //!< [3:2]
+ uint8_t LVDRE : 1; //!< [4] Low-Voltage Detect Reset Enable
+ uint8_t LVDIE : 1; //!< [5] Low-Voltage Detect Interrupt Enable
+ uint8_t LVDACK : 1; //!< [6] Low-Voltage Detect Acknowledge
+ uint8_t LVDF : 1; //!< [7] Low-Voltage Detect Flag
+ } B;
+} hw_pmc_lvdsc1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PMC_LVDSC1 register
+ */
+//@{
+#define HW_PMC_LVDSC1_ADDR (REGS_PMC_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PMC_LVDSC1 (*(__IO hw_pmc_lvdsc1_t *) HW_PMC_LVDSC1_ADDR)
+#define HW_PMC_LVDSC1_RD() (HW_PMC_LVDSC1.U)
+#define HW_PMC_LVDSC1_WR(v) (HW_PMC_LVDSC1.U = (v))
+#define HW_PMC_LVDSC1_SET(v) (HW_PMC_LVDSC1_WR(HW_PMC_LVDSC1_RD() | (v)))
+#define HW_PMC_LVDSC1_CLR(v) (HW_PMC_LVDSC1_WR(HW_PMC_LVDSC1_RD() & ~(v)))
+#define HW_PMC_LVDSC1_TOG(v) (HW_PMC_LVDSC1_WR(HW_PMC_LVDSC1_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PMC_LVDSC1 bitfields
+ */
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDV[1:0] (RW)
+ *
+ * Selects the LVD trip point voltage (V LVD ).
+ *
+ * Values:
+ * - 00 - Low trip point selected (V LVD = V LVDL )
+ * - 01 - High trip point selected (V LVD = V LVDH )
+ * - 10 - Reserved
+ * - 11 - Reserved
+ */
+//@{
+#define BP_PMC_LVDSC1_LVDV (0U) //!< Bit position for PMC_LVDSC1_LVDV.
+#define BM_PMC_LVDSC1_LVDV (0x03U) //!< Bit mask for PMC_LVDSC1_LVDV.
+#define BS_PMC_LVDSC1_LVDV (2U) //!< Bit field size in bits for PMC_LVDSC1_LVDV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PMC_LVDSC1_LVDV field.
+#define BR_PMC_LVDSC1_LVDV (HW_PMC_LVDSC1.B.LVDV)
+#endif
+
+//! @brief Format value for bitfield PMC_LVDSC1_LVDV.
+#define BF_PMC_LVDSC1_LVDV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC1_LVDV), uint8_t) & BM_PMC_LVDSC1_LVDV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LVDV field to a new value.
+#define BW_PMC_LVDSC1_LVDV(v) (HW_PMC_LVDSC1_WR((HW_PMC_LVDSC1_RD() & ~BM_PMC_LVDSC1_LVDV) | BF_PMC_LVDSC1_LVDV(v)))
+#endif
+//@}
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDRE[4] (RW)
+ *
+ * This write-once bit enables LVDF events to generate a hardware reset.
+ * Additional writes are ignored.
+ *
+ * Values:
+ * - 0 - LVDF does not generate hardware resets
+ * - 1 - Force an MCU reset when LVDF = 1
+ */
+//@{
+#define BP_PMC_LVDSC1_LVDRE (4U) //!< Bit position for PMC_LVDSC1_LVDRE.
+#define BM_PMC_LVDSC1_LVDRE (0x10U) //!< Bit mask for PMC_LVDSC1_LVDRE.
+#define BS_PMC_LVDSC1_LVDRE (1U) //!< Bit field size in bits for PMC_LVDSC1_LVDRE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PMC_LVDSC1_LVDRE field.
+#define BR_PMC_LVDSC1_LVDRE (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDRE))
+#endif
+
+//! @brief Format value for bitfield PMC_LVDSC1_LVDRE.
+#define BF_PMC_LVDSC1_LVDRE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC1_LVDRE), uint8_t) & BM_PMC_LVDSC1_LVDRE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LVDRE field to a new value.
+#define BW_PMC_LVDSC1_LVDRE(v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDRE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDIE[5] (RW)
+ *
+ * Enables hardware interrupt requests for LVDF.
+ *
+ * Values:
+ * - 0 - Hardware interrupt disabled (use polling)
+ * - 1 - Request a hardware interrupt when LVDF = 1
+ */
+//@{
+#define BP_PMC_LVDSC1_LVDIE (5U) //!< Bit position for PMC_LVDSC1_LVDIE.
+#define BM_PMC_LVDSC1_LVDIE (0x20U) //!< Bit mask for PMC_LVDSC1_LVDIE.
+#define BS_PMC_LVDSC1_LVDIE (1U) //!< Bit field size in bits for PMC_LVDSC1_LVDIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PMC_LVDSC1_LVDIE field.
+#define BR_PMC_LVDSC1_LVDIE (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDIE))
+#endif
+
+//! @brief Format value for bitfield PMC_LVDSC1_LVDIE.
+#define BF_PMC_LVDSC1_LVDIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC1_LVDIE), uint8_t) & BM_PMC_LVDSC1_LVDIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LVDIE field to a new value.
+#define BW_PMC_LVDSC1_LVDIE(v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDACK[6] (WORZ)
+ *
+ * This write-only field is used to acknowledge low voltage detection errors.
+ * Write 1 to clear LVDF. Reads always return 0.
+ */
+//@{
+#define BP_PMC_LVDSC1_LVDACK (6U) //!< Bit position for PMC_LVDSC1_LVDACK.
+#define BM_PMC_LVDSC1_LVDACK (0x40U) //!< Bit mask for PMC_LVDSC1_LVDACK.
+#define BS_PMC_LVDSC1_LVDACK (1U) //!< Bit field size in bits for PMC_LVDSC1_LVDACK.
+
+//! @brief Format value for bitfield PMC_LVDSC1_LVDACK.
+#define BF_PMC_LVDSC1_LVDACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC1_LVDACK), uint8_t) & BM_PMC_LVDSC1_LVDACK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LVDACK field to a new value.
+#define BW_PMC_LVDSC1_LVDACK(v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDACK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDF[7] (RO)
+ *
+ * This read-only status field indicates a low-voltage detect event.
+ *
+ * Values:
+ * - 0 - Low-voltage event not detected
+ * - 1 - Low-voltage event detected
+ */
+//@{
+#define BP_PMC_LVDSC1_LVDF (7U) //!< Bit position for PMC_LVDSC1_LVDF.
+#define BM_PMC_LVDSC1_LVDF (0x80U) //!< Bit mask for PMC_LVDSC1_LVDF.
+#define BS_PMC_LVDSC1_LVDF (1U) //!< Bit field size in bits for PMC_LVDSC1_LVDF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PMC_LVDSC1_LVDF field.
+#define BR_PMC_LVDSC1_LVDF (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR, BP_PMC_LVDSC1_LVDF))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains status and control bits to support the low voltage
+ * warning function. While the device is in the very low power or low leakage modes,
+ * the LVD system is disabled regardless of LVDSC2 settings. See the device's
+ * data sheet for the exact LVD trip voltages. The LVW trip voltages depend on LVWV
+ * and LVDV. LVWV is reset solely on a POR Only event. The other fields of the
+ * register are reset on Chip Reset Not VLLS. For more information about these
+ * reset types, refer to the Reset section details.
+ */
+typedef union _hw_pmc_lvdsc2
+{
+ uint8_t U;
+ struct _hw_pmc_lvdsc2_bitfields
+ {
+ uint8_t LVWV : 2; //!< [1:0] Low-Voltage Warning Voltage Select
+ uint8_t RESERVED0 : 3; //!< [4:2]
+ uint8_t LVWIE : 1; //!< [5] Low-Voltage Warning Interrupt Enable
+ uint8_t LVWACK : 1; //!< [6] Low-Voltage Warning Acknowledge
+ uint8_t LVWF : 1; //!< [7] Low-Voltage Warning Flag
+ } B;
+} hw_pmc_lvdsc2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PMC_LVDSC2 register
+ */
+//@{
+#define HW_PMC_LVDSC2_ADDR (REGS_PMC_BASE + 0x1U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PMC_LVDSC2 (*(__IO hw_pmc_lvdsc2_t *) HW_PMC_LVDSC2_ADDR)
+#define HW_PMC_LVDSC2_RD() (HW_PMC_LVDSC2.U)
+#define HW_PMC_LVDSC2_WR(v) (HW_PMC_LVDSC2.U = (v))
+#define HW_PMC_LVDSC2_SET(v) (HW_PMC_LVDSC2_WR(HW_PMC_LVDSC2_RD() | (v)))
+#define HW_PMC_LVDSC2_CLR(v) (HW_PMC_LVDSC2_WR(HW_PMC_LVDSC2_RD() & ~(v)))
+#define HW_PMC_LVDSC2_TOG(v) (HW_PMC_LVDSC2_WR(HW_PMC_LVDSC2_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PMC_LVDSC2 bitfields
+ */
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWV[1:0] (RW)
+ *
+ * Selects the LVW trip point voltage (VLVW). The actual voltage for the warning
+ * depends on LVDSC1[LVDV].
+ *
+ * Values:
+ * - 00 - Low trip point selected (VLVW = VLVW1)
+ * - 01 - Mid 1 trip point selected (VLVW = VLVW2)
+ * - 10 - Mid 2 trip point selected (VLVW = VLVW3)
+ * - 11 - High trip point selected (VLVW = VLVW4)
+ */
+//@{
+#define BP_PMC_LVDSC2_LVWV (0U) //!< Bit position for PMC_LVDSC2_LVWV.
+#define BM_PMC_LVDSC2_LVWV (0x03U) //!< Bit mask for PMC_LVDSC2_LVWV.
+#define BS_PMC_LVDSC2_LVWV (2U) //!< Bit field size in bits for PMC_LVDSC2_LVWV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PMC_LVDSC2_LVWV field.
+#define BR_PMC_LVDSC2_LVWV (HW_PMC_LVDSC2.B.LVWV)
+#endif
+
+//! @brief Format value for bitfield PMC_LVDSC2_LVWV.
+#define BF_PMC_LVDSC2_LVWV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC2_LVWV), uint8_t) & BM_PMC_LVDSC2_LVWV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LVWV field to a new value.
+#define BW_PMC_LVDSC2_LVWV(v) (HW_PMC_LVDSC2_WR((HW_PMC_LVDSC2_RD() & ~BM_PMC_LVDSC2_LVWV) | BF_PMC_LVDSC2_LVWV(v)))
+#endif
+//@}
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWIE[5] (RW)
+ *
+ * Enables hardware interrupt requests for LVWF.
+ *
+ * Values:
+ * - 0 - Hardware interrupt disabled (use polling)
+ * - 1 - Request a hardware interrupt when LVWF = 1
+ */
+//@{
+#define BP_PMC_LVDSC2_LVWIE (5U) //!< Bit position for PMC_LVDSC2_LVWIE.
+#define BM_PMC_LVDSC2_LVWIE (0x20U) //!< Bit mask for PMC_LVDSC2_LVWIE.
+#define BS_PMC_LVDSC2_LVWIE (1U) //!< Bit field size in bits for PMC_LVDSC2_LVWIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PMC_LVDSC2_LVWIE field.
+#define BR_PMC_LVDSC2_LVWIE (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR, BP_PMC_LVDSC2_LVWIE))
+#endif
+
+//! @brief Format value for bitfield PMC_LVDSC2_LVWIE.
+#define BF_PMC_LVDSC2_LVWIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC2_LVWIE), uint8_t) & BM_PMC_LVDSC2_LVWIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LVWIE field to a new value.
+#define BW_PMC_LVDSC2_LVWIE(v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR, BP_PMC_LVDSC2_LVWIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWACK[6] (WORZ)
+ *
+ * This write-only field is used to acknowledge low voltage warning errors.
+ * Write 1 to clear LVWF. Reads always return 0.
+ */
+//@{
+#define BP_PMC_LVDSC2_LVWACK (6U) //!< Bit position for PMC_LVDSC2_LVWACK.
+#define BM_PMC_LVDSC2_LVWACK (0x40U) //!< Bit mask for PMC_LVDSC2_LVWACK.
+#define BS_PMC_LVDSC2_LVWACK (1U) //!< Bit field size in bits for PMC_LVDSC2_LVWACK.
+
+//! @brief Format value for bitfield PMC_LVDSC2_LVWACK.
+#define BF_PMC_LVDSC2_LVWACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_LVDSC2_LVWACK), uint8_t) & BM_PMC_LVDSC2_LVWACK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LVWACK field to a new value.
+#define BW_PMC_LVDSC2_LVWACK(v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR, BP_PMC_LVDSC2_LVWACK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWF[7] (RO)
+ *
+ * This read-only status field indicates a low-voltage warning event. LVWF is
+ * set when VSupply transitions below the trip point, or after reset and VSupply is
+ * already below VLVW. LVWF may be 1 after power-on reset, therefore, to use LVW
+ * interrupt function, before enabling LVWIE, LVWF must be cleared by writing
+ * LVWACK first.
+ *
+ * Values:
+ * - 0 - Low-voltage warning event not detected
+ * - 1 - Low-voltage warning event detected
+ */
+//@{
+#define BP_PMC_LVDSC2_LVWF (7U) //!< Bit position for PMC_LVDSC2_LVWF.
+#define BM_PMC_LVDSC2_LVWF (0x80U) //!< Bit mask for PMC_LVDSC2_LVWF.
+#define BS_PMC_LVDSC2_LVWF (1U) //!< Bit field size in bits for PMC_LVDSC2_LVWF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PMC_LVDSC2_LVWF field.
+#define BR_PMC_LVDSC2_LVWF (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR, BP_PMC_LVDSC2_LVWF))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PMC_REGSC - Regulator Status And Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PMC_REGSC - Regulator Status And Control register (RW)
+ *
+ * Reset value: 0x04U
+ *
+ * The PMC contains an internal voltage regulator. The voltage regulator design
+ * uses a bandgap reference that is also available through a buffer as input to
+ * certain internal peripherals, such as the CMP and ADC. The internal regulator
+ * provides a status bit (REGONS) indicating the regulator is in run regulation.
+ * This register is reset on Chip Reset Not VLLS and by reset types that trigger
+ * Chip Reset not VLLS. See the Reset section details for more information.
+ */
+typedef union _hw_pmc_regsc
+{
+ uint8_t U;
+ struct _hw_pmc_regsc_bitfields
+ {
+ uint8_t BGBE : 1; //!< [0] Bandgap Buffer Enable
+ uint8_t RESERVED0 : 1; //!< [1]
+ uint8_t REGONS : 1; //!< [2] Regulator In Run Regulation Status
+ uint8_t ACKISO : 1; //!< [3] Acknowledge Isolation
+ uint8_t BGEN : 1; //!< [4] Bandgap Enable In VLPx Operation
+ uint8_t RESERVED1 : 3; //!< [7:5]
+ } B;
+} hw_pmc_regsc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PMC_REGSC register
+ */
+//@{
+#define HW_PMC_REGSC_ADDR (REGS_PMC_BASE + 0x2U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PMC_REGSC (*(__IO hw_pmc_regsc_t *) HW_PMC_REGSC_ADDR)
+#define HW_PMC_REGSC_RD() (HW_PMC_REGSC.U)
+#define HW_PMC_REGSC_WR(v) (HW_PMC_REGSC.U = (v))
+#define HW_PMC_REGSC_SET(v) (HW_PMC_REGSC_WR(HW_PMC_REGSC_RD() | (v)))
+#define HW_PMC_REGSC_CLR(v) (HW_PMC_REGSC_WR(HW_PMC_REGSC_RD() & ~(v)))
+#define HW_PMC_REGSC_TOG(v) (HW_PMC_REGSC_WR(HW_PMC_REGSC_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PMC_REGSC bitfields
+ */
+
+/*!
+ * @name Register PMC_REGSC, field BGBE[0] (RW)
+ *
+ * Enables the bandgap buffer.
+ *
+ * Values:
+ * - 0 - Bandgap buffer not enabled
+ * - 1 - Bandgap buffer enabled
+ */
+//@{
+#define BP_PMC_REGSC_BGBE (0U) //!< Bit position for PMC_REGSC_BGBE.
+#define BM_PMC_REGSC_BGBE (0x01U) //!< Bit mask for PMC_REGSC_BGBE.
+#define BS_PMC_REGSC_BGBE (1U) //!< Bit field size in bits for PMC_REGSC_BGBE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PMC_REGSC_BGBE field.
+#define BR_PMC_REGSC_BGBE (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_BGBE))
+#endif
+
+//! @brief Format value for bitfield PMC_REGSC_BGBE.
+#define BF_PMC_REGSC_BGBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_REGSC_BGBE), uint8_t) & BM_PMC_REGSC_BGBE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BGBE field to a new value.
+#define BW_PMC_REGSC_BGBE(v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_BGBE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PMC_REGSC, field REGONS[2] (RO)
+ *
+ * This read-only field provides the current status of the internal voltage
+ * regulator.
+ *
+ * Values:
+ * - 0 - Regulator is in stop regulation or in transition to/from it
+ * - 1 - Regulator is in run regulation
+ */
+//@{
+#define BP_PMC_REGSC_REGONS (2U) //!< Bit position for PMC_REGSC_REGONS.
+#define BM_PMC_REGSC_REGONS (0x04U) //!< Bit mask for PMC_REGSC_REGONS.
+#define BS_PMC_REGSC_REGONS (1U) //!< Bit field size in bits for PMC_REGSC_REGONS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PMC_REGSC_REGONS field.
+#define BR_PMC_REGSC_REGONS (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_REGONS))
+#endif
+//@}
+
+/*!
+ * @name Register PMC_REGSC, field ACKISO[3] (W1C)
+ *
+ * Reading this field indicates whether certain peripherals and the I/O pads are
+ * in a latched state as a result of having been in a VLLS mode. Writing 1 to
+ * this field when it is set releases the I/O pads and certain peripherals to their
+ * normal run mode state. After recovering from a VLLS mode, user should restore
+ * chip configuration before clearing ACKISO. In particular, pin configuration
+ * for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from
+ * being falsely set when ACKISO is cleared.
+ *
+ * Values:
+ * - 0 - Peripherals and I/O pads are in normal run state.
+ * - 1 - Certain peripherals and I/O pads are in an isolated and latched state.
+ */
+//@{
+#define BP_PMC_REGSC_ACKISO (3U) //!< Bit position for PMC_REGSC_ACKISO.
+#define BM_PMC_REGSC_ACKISO (0x08U) //!< Bit mask for PMC_REGSC_ACKISO.
+#define BS_PMC_REGSC_ACKISO (1U) //!< Bit field size in bits for PMC_REGSC_ACKISO.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PMC_REGSC_ACKISO field.
+#define BR_PMC_REGSC_ACKISO (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_ACKISO))
+#endif
+
+//! @brief Format value for bitfield PMC_REGSC_ACKISO.
+#define BF_PMC_REGSC_ACKISO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_REGSC_ACKISO), uint8_t) & BM_PMC_REGSC_ACKISO)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ACKISO field to a new value.
+#define BW_PMC_REGSC_ACKISO(v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_ACKISO) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PMC_REGSC, field BGEN[4] (RW)
+ *
+ * BGEN controls whether the bandgap is enabled in lower power modes of
+ * operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage
+ * reference in low power modes of operation, set BGEN to continue to enable the
+ * bandgap operation. When the bandgap voltage reference is not needed in low
+ * power modes, clear BGEN to avoid excess power consumption.
+ *
+ * Values:
+ * - 0 - Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
+ * - 1 - Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
+ */
+//@{
+#define BP_PMC_REGSC_BGEN (4U) //!< Bit position for PMC_REGSC_BGEN.
+#define BM_PMC_REGSC_BGEN (0x10U) //!< Bit mask for PMC_REGSC_BGEN.
+#define BS_PMC_REGSC_BGEN (1U) //!< Bit field size in bits for PMC_REGSC_BGEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PMC_REGSC_BGEN field.
+#define BR_PMC_REGSC_BGEN (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_BGEN))
+#endif
+
+//! @brief Format value for bitfield PMC_REGSC_BGEN.
+#define BF_PMC_REGSC_BGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_PMC_REGSC_BGEN), uint8_t) & BM_PMC_REGSC_BGEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BGEN field to a new value.
+#define BW_PMC_REGSC_BGEN(v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR, BP_PMC_REGSC_BGEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_pmc_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All PMC module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_pmc
+{
+ __IO hw_pmc_lvdsc1_t LVDSC1; //!< [0x0] Low Voltage Detect Status And Control 1 register
+ __IO hw_pmc_lvdsc2_t LVDSC2; //!< [0x1] Low Voltage Detect Status And Control 2 register
+ __IO hw_pmc_regsc_t REGSC; //!< [0x2] Regulator Status And Control register
+} hw_pmc_t;
+#pragma pack()
+
+//! @brief Macro to access all PMC registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_PMC</code>.
+#define HW_PMC (*(hw_pmc_t *) REGS_PMC_BASE)
+#endif
+
+#endif // __HW_PMC_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_port.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,957 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_PORT_REGISTERS_H__
+#define __HW_PORT_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 PORT
+ *
+ * Pin Control and Interrupts
+ *
+ * Registers defined in this header file:
+ * - HW_PORT_PCRn - Pin Control Register n
+ * - HW_PORT_GPCLR - Global Pin Control Low Register
+ * - HW_PORT_GPCHR - Global Pin Control High Register
+ * - HW_PORT_ISFR - Interrupt Status Flag Register
+ * - HW_PORT_DFER - Digital Filter Enable Register
+ * - HW_PORT_DFCR - Digital Filter Clock Register
+ * - HW_PORT_DFWR - Digital Filter Width Register
+ *
+ * - hw_port_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_PORT_BASE
+#define HW_PORT_INSTANCE_COUNT (5U) //!< Number of instances of the PORT module.
+#define HW_PORTA (0U) //!< Instance number for PORTA.
+#define HW_PORTB (1U) //!< Instance number for PORTB.
+#define HW_PORTC (2U) //!< Instance number for PORTC.
+#define HW_PORTD (3U) //!< Instance number for PORTD.
+#define HW_PORTE (4U) //!< Instance number for PORTE.
+#define REGS_PORTA_BASE (0x40049000U) //!< Base address for PORTA.
+#define REGS_PORTB_BASE (0x4004A000U) //!< Base address for PORTB.
+#define REGS_PORTC_BASE (0x4004B000U) //!< Base address for PORTC.
+#define REGS_PORTD_BASE (0x4004C000U) //!< Base address for PORTD.
+#define REGS_PORTE_BASE (0x4004D000U) //!< Base address for PORTE.
+
+//! @brief Table of base addresses for PORT instances.
+static const uint32_t __g_regs_PORT_base_addresses[] = {
+ REGS_PORTA_BASE,
+ REGS_PORTB_BASE,
+ REGS_PORTC_BASE,
+ REGS_PORTD_BASE,
+ REGS_PORTE_BASE,
+ };
+
+//! @brief Get the base address of PORT by instance number.
+//! @param x PORT instance number, from 0 through 4.
+#define REGS_PORT_BASE(x) (__g_regs_PORT_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of PORT.
+#define REGS_PORT_INSTANCE(b) ((b) == REGS_PORTA_BASE ? HW_PORTA : (b) == REGS_PORTB_BASE ? HW_PORTB : (b) == REGS_PORTC_BASE ? HW_PORTC : (b) == REGS_PORTD_BASE ? HW_PORTD : (b) == REGS_PORTE_BASE ? HW_PORTE : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PORT_PCRn - Pin Control Register n
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PORT_PCRn - Pin Control Register n (RW)
+ *
+ * Reset value: 0x00000742U
+ *
+ * See the Signal Multiplexing and Pin Assignment chapter for the reset value of
+ * this device. See the GPIO Configuration section for details on the available
+ * functions for each pin. Do not modify pin configuration registers associated
+ * with pins not available in your selected package. All unbonded pins not
+ * available in your package will default to DISABLE state for lowest power consumption.
+ */
+typedef union _hw_port_pcrn
+{
+ uint32_t U;
+ struct _hw_port_pcrn_bitfields
+ {
+ uint32_t PS : 1; //!< [0] Pull Select
+ uint32_t PE : 1; //!< [1] Pull Enable
+ uint32_t SRE : 1; //!< [2] Slew Rate Enable
+ uint32_t RESERVED0 : 1; //!< [3]
+ uint32_t PFE : 1; //!< [4] Passive Filter Enable
+ uint32_t ODE : 1; //!< [5] Open Drain Enable
+ uint32_t DSE : 1; //!< [6] Drive Strength Enable
+ uint32_t RESERVED1 : 1; //!< [7]
+ uint32_t MUX : 3; //!< [10:8] Pin Mux Control
+ uint32_t RESERVED2 : 4; //!< [14:11]
+ uint32_t LK : 1; //!< [15] Lock Register
+ uint32_t IRQC : 4; //!< [19:16] Interrupt Configuration
+ uint32_t RESERVED3 : 4; //!< [23:20]
+ uint32_t ISF : 1; //!< [24] Interrupt Status Flag
+ uint32_t RESERVED4 : 7; //!< [31:25]
+ } B;
+} hw_port_pcrn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PORT_PCRn register
+ */
+//@{
+#define HW_PORT_PCRn_COUNT (32U)
+
+#define HW_PORT_PCRn_ADDR(x, n) (REGS_PORT_BASE(x) + 0x0U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PORT_PCRn(x, n) (*(__IO hw_port_pcrn_t *) HW_PORT_PCRn_ADDR(x, n))
+#define HW_PORT_PCRn_RD(x, n) (HW_PORT_PCRn(x, n).U)
+#define HW_PORT_PCRn_WR(x, n, v) (HW_PORT_PCRn(x, n).U = (v))
+#define HW_PORT_PCRn_SET(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) | (v)))
+#define HW_PORT_PCRn_CLR(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) & ~(v)))
+#define HW_PORT_PCRn_TOG(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PORT_PCRn bitfields
+ */
+
+/*!
+ * @name Register PORT_PCRn, field PS[0] (RW)
+ *
+ * Pull configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0 - Internal pulldown resistor is enabled on the corresponding pin, if the
+ * corresponding PE field is set.
+ * - 1 - Internal pullup resistor is enabled on the corresponding pin, if the
+ * corresponding PE field is set.
+ */
+//@{
+#define BP_PORT_PCRn_PS (0U) //!< Bit position for PORT_PCRn_PS.
+#define BM_PORT_PCRn_PS (0x00000001U) //!< Bit mask for PORT_PCRn_PS.
+#define BS_PORT_PCRn_PS (1U) //!< Bit field size in bits for PORT_PCRn_PS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PORT_PCRn_PS field.
+#define BR_PORT_PCRn_PS(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS))
+#endif
+
+//! @brief Format value for bitfield PORT_PCRn_PS.
+#define BF_PORT_PCRn_PS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_PS), uint32_t) & BM_PORT_PCRn_PS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PS field to a new value.
+#define BW_PORT_PCRn_PS(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PORT_PCRn, field PE[1] (RW)
+ *
+ * Pull configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0 - Internal pullup or pulldown resistor is not enabled on the
+ * corresponding pin.
+ * - 1 - Internal pullup or pulldown resistor is enabled on the corresponding
+ * pin, if the pin is configured as a digital input.
+ */
+//@{
+#define BP_PORT_PCRn_PE (1U) //!< Bit position for PORT_PCRn_PE.
+#define BM_PORT_PCRn_PE (0x00000002U) //!< Bit mask for PORT_PCRn_PE.
+#define BS_PORT_PCRn_PE (1U) //!< Bit field size in bits for PORT_PCRn_PE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PORT_PCRn_PE field.
+#define BR_PORT_PCRn_PE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE))
+#endif
+
+//! @brief Format value for bitfield PORT_PCRn_PE.
+#define BF_PORT_PCRn_PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_PE), uint32_t) & BM_PORT_PCRn_PE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PE field to a new value.
+#define BW_PORT_PCRn_PE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PORT_PCRn, field SRE[2] (RW)
+ *
+ * Slew rate configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0 - Fast slew rate is configured on the corresponding pin, if the pin is
+ * configured as a digital output.
+ * - 1 - Slow slew rate is configured on the corresponding pin, if the pin is
+ * configured as a digital output.
+ */
+//@{
+#define BP_PORT_PCRn_SRE (2U) //!< Bit position for PORT_PCRn_SRE.
+#define BM_PORT_PCRn_SRE (0x00000004U) //!< Bit mask for PORT_PCRn_SRE.
+#define BS_PORT_PCRn_SRE (1U) //!< Bit field size in bits for PORT_PCRn_SRE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PORT_PCRn_SRE field.
+#define BR_PORT_PCRn_SRE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE))
+#endif
+
+//! @brief Format value for bitfield PORT_PCRn_SRE.
+#define BF_PORT_PCRn_SRE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_SRE), uint32_t) & BM_PORT_PCRn_SRE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SRE field to a new value.
+#define BW_PORT_PCRn_SRE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PORT_PCRn, field PFE[4] (RW)
+ *
+ * Passive filter configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0 - Passive input filter is disabled on the corresponding pin.
+ * - 1 - Passive input filter is enabled on the corresponding pin, if the pin is
+ * configured as a digital input. Refer to the device data sheet for filter
+ * characteristics.
+ */
+//@{
+#define BP_PORT_PCRn_PFE (4U) //!< Bit position for PORT_PCRn_PFE.
+#define BM_PORT_PCRn_PFE (0x00000010U) //!< Bit mask for PORT_PCRn_PFE.
+#define BS_PORT_PCRn_PFE (1U) //!< Bit field size in bits for PORT_PCRn_PFE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PORT_PCRn_PFE field.
+#define BR_PORT_PCRn_PFE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE))
+#endif
+
+//! @brief Format value for bitfield PORT_PCRn_PFE.
+#define BF_PORT_PCRn_PFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_PFE), uint32_t) & BM_PORT_PCRn_PFE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PFE field to a new value.
+#define BW_PORT_PCRn_PFE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PORT_PCRn, field ODE[5] (RW)
+ *
+ * Open drain configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0 - Open drain output is disabled on the corresponding pin.
+ * - 1 - Open drain output is enabled on the corresponding pin, if the pin is
+ * configured as a digital output.
+ */
+//@{
+#define BP_PORT_PCRn_ODE (5U) //!< Bit position for PORT_PCRn_ODE.
+#define BM_PORT_PCRn_ODE (0x00000020U) //!< Bit mask for PORT_PCRn_ODE.
+#define BS_PORT_PCRn_ODE (1U) //!< Bit field size in bits for PORT_PCRn_ODE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PORT_PCRn_ODE field.
+#define BR_PORT_PCRn_ODE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE))
+#endif
+
+//! @brief Format value for bitfield PORT_PCRn_ODE.
+#define BF_PORT_PCRn_ODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_ODE), uint32_t) & BM_PORT_PCRn_ODE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ODE field to a new value.
+#define BW_PORT_PCRn_ODE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PORT_PCRn, field DSE[6] (RW)
+ *
+ * Drive strength configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0 - Low drive strength is configured on the corresponding pin, if pin is
+ * configured as a digital output.
+ * - 1 - High drive strength is configured on the corresponding pin, if pin is
+ * configured as a digital output.
+ */
+//@{
+#define BP_PORT_PCRn_DSE (6U) //!< Bit position for PORT_PCRn_DSE.
+#define BM_PORT_PCRn_DSE (0x00000040U) //!< Bit mask for PORT_PCRn_DSE.
+#define BS_PORT_PCRn_DSE (1U) //!< Bit field size in bits for PORT_PCRn_DSE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PORT_PCRn_DSE field.
+#define BR_PORT_PCRn_DSE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE))
+#endif
+
+//! @brief Format value for bitfield PORT_PCRn_DSE.
+#define BF_PORT_PCRn_DSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_DSE), uint32_t) & BM_PORT_PCRn_DSE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DSE field to a new value.
+#define BW_PORT_PCRn_DSE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PORT_PCRn, field MUX[10:8] (RW)
+ *
+ * Not all pins support all pin muxing slots. Unimplemented pin muxing slots are
+ * reserved and may result in configuring the pin for a different pin muxing
+ * slot. The corresponding pin is configured in the following pin muxing slot as
+ * follows:
+ *
+ * Values:
+ * - 000 - Pin disabled (analog).
+ * - 001 - Alternative 1 (GPIO).
+ * - 010 - Alternative 2 (chip-specific).
+ * - 011 - Alternative 3 (chip-specific).
+ * - 100 - Alternative 4 (chip-specific).
+ * - 101 - Alternative 5 (chip-specific).
+ * - 110 - Alternative 6 (chip-specific).
+ * - 111 - Alternative 7 (chip-specific).
+ */
+//@{
+#define BP_PORT_PCRn_MUX (8U) //!< Bit position for PORT_PCRn_MUX.
+#define BM_PORT_PCRn_MUX (0x00000700U) //!< Bit mask for PORT_PCRn_MUX.
+#define BS_PORT_PCRn_MUX (3U) //!< Bit field size in bits for PORT_PCRn_MUX.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PORT_PCRn_MUX field.
+#define BR_PORT_PCRn_MUX(x, n) (HW_PORT_PCRn(x, n).B.MUX)
+#endif
+
+//! @brief Format value for bitfield PORT_PCRn_MUX.
+#define BF_PORT_PCRn_MUX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_MUX), uint32_t) & BM_PORT_PCRn_MUX)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MUX field to a new value.
+#define BW_PORT_PCRn_MUX(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_MUX) | BF_PORT_PCRn_MUX(v)))
+#endif
+//@}
+
+/*!
+ * @name Register PORT_PCRn, field LK[15] (RW)
+ *
+ * Values:
+ * - 0 - Pin Control Register fields [15:0] are not locked.
+ * - 1 - Pin Control Register fields [15:0] are locked and cannot be updated
+ * until the next system reset.
+ */
+//@{
+#define BP_PORT_PCRn_LK (15U) //!< Bit position for PORT_PCRn_LK.
+#define BM_PORT_PCRn_LK (0x00008000U) //!< Bit mask for PORT_PCRn_LK.
+#define BS_PORT_PCRn_LK (1U) //!< Bit field size in bits for PORT_PCRn_LK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PORT_PCRn_LK field.
+#define BR_PORT_PCRn_LK(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK))
+#endif
+
+//! @brief Format value for bitfield PORT_PCRn_LK.
+#define BF_PORT_PCRn_LK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_LK), uint32_t) & BM_PORT_PCRn_LK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LK field to a new value.
+#define BW_PORT_PCRn_LK(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register PORT_PCRn, field IRQC[19:16] (RW)
+ *
+ * The pin interrupt configuration is valid in all digital pin muxing modes. The
+ * corresponding pin is configured to generate interrupt/DMA request as follows:
+ *
+ * Values:
+ * - 0000 - Interrupt/DMA request disabled.
+ * - 0001 - DMA request on rising edge.
+ * - 0010 - DMA request on falling edge.
+ * - 0011 - DMA request on either edge.
+ * - 1000 - Interrupt when logic 0.
+ * - 1001 - Interrupt on rising-edge.
+ * - 1010 - Interrupt on falling-edge.
+ * - 1011 - Interrupt on either edge.
+ * - 1100 - Interrupt when logic 1.
+ */
+//@{
+#define BP_PORT_PCRn_IRQC (16U) //!< Bit position for PORT_PCRn_IRQC.
+#define BM_PORT_PCRn_IRQC (0x000F0000U) //!< Bit mask for PORT_PCRn_IRQC.
+#define BS_PORT_PCRn_IRQC (4U) //!< Bit field size in bits for PORT_PCRn_IRQC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PORT_PCRn_IRQC field.
+#define BR_PORT_PCRn_IRQC(x, n) (HW_PORT_PCRn(x, n).B.IRQC)
+#endif
+
+//! @brief Format value for bitfield PORT_PCRn_IRQC.
+#define BF_PORT_PCRn_IRQC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_IRQC), uint32_t) & BM_PORT_PCRn_IRQC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IRQC field to a new value.
+#define BW_PORT_PCRn_IRQC(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_IRQC) | BF_PORT_PCRn_IRQC(v)))
+#endif
+//@}
+
+/*!
+ * @name Register PORT_PCRn, field ISF[24] (W1C)
+ *
+ * The pin interrupt configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0 - Configured interrupt is not detected.
+ * - 1 - Configured interrupt is detected. If the pin is configured to generate
+ * a DMA request, then the corresponding flag will be cleared automatically
+ * at the completion of the requested DMA transfer. Otherwise, the flag
+ * remains set until a logic 1 is written to the flag. If the pin is configured for
+ * a level sensitive interrupt and the pin remains asserted, then the flag
+ * is set again immediately after it is cleared.
+ */
+//@{
+#define BP_PORT_PCRn_ISF (24U) //!< Bit position for PORT_PCRn_ISF.
+#define BM_PORT_PCRn_ISF (0x01000000U) //!< Bit mask for PORT_PCRn_ISF.
+#define BS_PORT_PCRn_ISF (1U) //!< Bit field size in bits for PORT_PCRn_ISF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PORT_PCRn_ISF field.
+#define BR_PORT_PCRn_ISF(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF))
+#endif
+
+//! @brief Format value for bitfield PORT_PCRn_ISF.
+#define BF_PORT_PCRn_ISF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_PCRn_ISF), uint32_t) & BM_PORT_PCRn_ISF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ISF field to a new value.
+#define BW_PORT_PCRn_ISF(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PORT_GPCLR - Global Pin Control Low Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PORT_GPCLR - Global Pin Control Low Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Only 32-bit writes are supported to this register.
+ */
+typedef union _hw_port_gpclr
+{
+ uint32_t U;
+ struct _hw_port_gpclr_bitfields
+ {
+ uint32_t GPWD : 16; //!< [15:0] Global Pin Write Data
+ uint32_t GPWE : 16; //!< [31:16] Global Pin Write Enable
+ } B;
+} hw_port_gpclr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PORT_GPCLR register
+ */
+//@{
+#define HW_PORT_GPCLR_ADDR(x) (REGS_PORT_BASE(x) + 0x80U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PORT_GPCLR(x) (*(__O hw_port_gpclr_t *) HW_PORT_GPCLR_ADDR(x))
+#define HW_PORT_GPCLR_RD(x) (HW_PORT_GPCLR(x).U)
+#define HW_PORT_GPCLR_WR(x, v) (HW_PORT_GPCLR(x).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PORT_GPCLR bitfields
+ */
+
+/*!
+ * @name Register PORT_GPCLR, field GPWD[15:0] (WORZ)
+ *
+ * Write value that is written to all Pin Control Registers bits [15:0] that are
+ * selected by GPWE.
+ */
+//@{
+#define BP_PORT_GPCLR_GPWD (0U) //!< Bit position for PORT_GPCLR_GPWD.
+#define BM_PORT_GPCLR_GPWD (0x0000FFFFU) //!< Bit mask for PORT_GPCLR_GPWD.
+#define BS_PORT_GPCLR_GPWD (16U) //!< Bit field size in bits for PORT_GPCLR_GPWD.
+
+//! @brief Format value for bitfield PORT_GPCLR_GPWD.
+#define BF_PORT_GPCLR_GPWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_GPCLR_GPWD), uint32_t) & BM_PORT_GPCLR_GPWD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GPWD field to a new value.
+#define BW_PORT_GPCLR_GPWD(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWD) | BF_PORT_GPCLR_GPWD(v)))
+#endif
+//@}
+
+/*!
+ * @name Register PORT_GPCLR, field GPWE[31:16] (WORZ)
+ *
+ * Selects which Pin Control Registers (15 through 0) bits [15:0] update with
+ * the value in GPWD. If a selected Pin Control Register is locked then the write
+ * to that register is ignored.
+ *
+ * Values:
+ * - 0 - Corresponding Pin Control Register is not updated with the value in
+ * GPWD.
+ * - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
+ */
+//@{
+#define BP_PORT_GPCLR_GPWE (16U) //!< Bit position for PORT_GPCLR_GPWE.
+#define BM_PORT_GPCLR_GPWE (0xFFFF0000U) //!< Bit mask for PORT_GPCLR_GPWE.
+#define BS_PORT_GPCLR_GPWE (16U) //!< Bit field size in bits for PORT_GPCLR_GPWE.
+
+//! @brief Format value for bitfield PORT_GPCLR_GPWE.
+#define BF_PORT_GPCLR_GPWE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_GPCLR_GPWE), uint32_t) & BM_PORT_GPCLR_GPWE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GPWE field to a new value.
+#define BW_PORT_GPCLR_GPWE(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWE) | BF_PORT_GPCLR_GPWE(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PORT_GPCHR - Global Pin Control High Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PORT_GPCHR - Global Pin Control High Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Only 32-bit writes are supported to this register.
+ */
+typedef union _hw_port_gpchr
+{
+ uint32_t U;
+ struct _hw_port_gpchr_bitfields
+ {
+ uint32_t GPWD : 16; //!< [15:0] Global Pin Write Data
+ uint32_t GPWE : 16; //!< [31:16] Global Pin Write Enable
+ } B;
+} hw_port_gpchr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PORT_GPCHR register
+ */
+//@{
+#define HW_PORT_GPCHR_ADDR(x) (REGS_PORT_BASE(x) + 0x84U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PORT_GPCHR(x) (*(__O hw_port_gpchr_t *) HW_PORT_GPCHR_ADDR(x))
+#define HW_PORT_GPCHR_RD(x) (HW_PORT_GPCHR(x).U)
+#define HW_PORT_GPCHR_WR(x, v) (HW_PORT_GPCHR(x).U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PORT_GPCHR bitfields
+ */
+
+/*!
+ * @name Register PORT_GPCHR, field GPWD[15:0] (WORZ)
+ *
+ * Write value that is written to all Pin Control Registers bits [15:0] that are
+ * selected by GPWE.
+ */
+//@{
+#define BP_PORT_GPCHR_GPWD (0U) //!< Bit position for PORT_GPCHR_GPWD.
+#define BM_PORT_GPCHR_GPWD (0x0000FFFFU) //!< Bit mask for PORT_GPCHR_GPWD.
+#define BS_PORT_GPCHR_GPWD (16U) //!< Bit field size in bits for PORT_GPCHR_GPWD.
+
+//! @brief Format value for bitfield PORT_GPCHR_GPWD.
+#define BF_PORT_GPCHR_GPWD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_GPCHR_GPWD), uint32_t) & BM_PORT_GPCHR_GPWD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GPWD field to a new value.
+#define BW_PORT_GPCHR_GPWD(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWD) | BF_PORT_GPCHR_GPWD(v)))
+#endif
+//@}
+
+/*!
+ * @name Register PORT_GPCHR, field GPWE[31:16] (WORZ)
+ *
+ * Selects which Pin Control Registers (31 through 16) bits [15:0] update with
+ * the value in GPWD. If a selected Pin Control Register is locked then the write
+ * to that register is ignored.
+ *
+ * Values:
+ * - 0 - Corresponding Pin Control Register is not updated with the value in
+ * GPWD.
+ * - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
+ */
+//@{
+#define BP_PORT_GPCHR_GPWE (16U) //!< Bit position for PORT_GPCHR_GPWE.
+#define BM_PORT_GPCHR_GPWE (0xFFFF0000U) //!< Bit mask for PORT_GPCHR_GPWE.
+#define BS_PORT_GPCHR_GPWE (16U) //!< Bit field size in bits for PORT_GPCHR_GPWE.
+
+//! @brief Format value for bitfield PORT_GPCHR_GPWE.
+#define BF_PORT_GPCHR_GPWE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_GPCHR_GPWE), uint32_t) & BM_PORT_GPCHR_GPWE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GPWE field to a new value.
+#define BW_PORT_GPCHR_GPWE(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWE) | BF_PORT_GPCHR_GPWE(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PORT_ISFR - Interrupt Status Flag Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PORT_ISFR - Interrupt Status Flag Register (W1C)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The pin interrupt configuration is valid in all digital pin muxing modes. The
+ * Interrupt Status Flag for each pin is also visible in the corresponding Pin
+ * Control Register, and each flag can be cleared in either location.
+ */
+typedef union _hw_port_isfr
+{
+ uint32_t U;
+ struct _hw_port_isfr_bitfields
+ {
+ uint32_t ISF : 32; //!< [31:0] Interrupt Status Flag
+ } B;
+} hw_port_isfr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PORT_ISFR register
+ */
+//@{
+#define HW_PORT_ISFR_ADDR(x) (REGS_PORT_BASE(x) + 0xA0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PORT_ISFR(x) (*(__IO hw_port_isfr_t *) HW_PORT_ISFR_ADDR(x))
+#define HW_PORT_ISFR_RD(x) (HW_PORT_ISFR(x).U)
+#define HW_PORT_ISFR_WR(x, v) (HW_PORT_ISFR(x).U = (v))
+#define HW_PORT_ISFR_SET(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) | (v)))
+#define HW_PORT_ISFR_CLR(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) & ~(v)))
+#define HW_PORT_ISFR_TOG(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PORT_ISFR bitfields
+ */
+
+/*!
+ * @name Register PORT_ISFR, field ISF[31:0] (W1C)
+ *
+ * Each bit in the field indicates the detection of the configured interrupt of
+ * the same number as the field.
+ *
+ * Values:
+ * - 0 - Configured interrupt is not detected.
+ * - 1 - Configured interrupt is detected. If the pin is configured to generate
+ * a DMA request, then the corresponding flag will be cleared automatically
+ * at the completion of the requested DMA transfer. Otherwise, the flag
+ * remains set until a logic 1 is written to the flag. If the pin is configured for
+ * a level sensitive interrupt and the pin remains asserted, then the flag
+ * is set again immediately after it is cleared.
+ */
+//@{
+#define BP_PORT_ISFR_ISF (0U) //!< Bit position for PORT_ISFR_ISF.
+#define BM_PORT_ISFR_ISF (0xFFFFFFFFU) //!< Bit mask for PORT_ISFR_ISF.
+#define BS_PORT_ISFR_ISF (32U) //!< Bit field size in bits for PORT_ISFR_ISF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PORT_ISFR_ISF field.
+#define BR_PORT_ISFR_ISF(x) (HW_PORT_ISFR(x).U)
+#endif
+
+//! @brief Format value for bitfield PORT_ISFR_ISF.
+#define BF_PORT_ISFR_ISF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_ISFR_ISF), uint32_t) & BM_PORT_ISFR_ISF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ISF field to a new value.
+#define BW_PORT_ISFR_ISF(x, v) (HW_PORT_ISFR_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PORT_DFER - Digital Filter Enable Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PORT_DFER - Digital Filter Enable Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The corresponding bit is read only for pins that do not support a digital
+ * filter. Refer to the Chapter of Signal Multiplexing and Signal Descriptions for
+ * the pins that support digital filter. The digital filter configuration is valid
+ * in all digital pin muxing modes.
+ */
+typedef union _hw_port_dfer
+{
+ uint32_t U;
+ struct _hw_port_dfer_bitfields
+ {
+ uint32_t DFE : 32; //!< [31:0] Digital Filter Enable
+ } B;
+} hw_port_dfer_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PORT_DFER register
+ */
+//@{
+#define HW_PORT_DFER_ADDR(x) (REGS_PORT_BASE(x) + 0xC0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PORT_DFER(x) (*(__IO hw_port_dfer_t *) HW_PORT_DFER_ADDR(x))
+#define HW_PORT_DFER_RD(x) (HW_PORT_DFER(x).U)
+#define HW_PORT_DFER_WR(x, v) (HW_PORT_DFER(x).U = (v))
+#define HW_PORT_DFER_SET(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) | (v)))
+#define HW_PORT_DFER_CLR(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) & ~(v)))
+#define HW_PORT_DFER_TOG(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PORT_DFER bitfields
+ */
+
+/*!
+ * @name Register PORT_DFER, field DFE[31:0] (RW)
+ *
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ * The output of each digital filter is reset to zero at system reset and whenever
+ * the digital filter is disabled. Each bit in the field enables the digital
+ * filter of the same number as the field.
+ *
+ * Values:
+ * - 0 - Digital filter is disabled on the corresponding pin and output of the
+ * digital filter is reset to zero.
+ * - 1 - Digital filter is enabled on the corresponding pin, if the pin is
+ * configured as a digital input.
+ */
+//@{
+#define BP_PORT_DFER_DFE (0U) //!< Bit position for PORT_DFER_DFE.
+#define BM_PORT_DFER_DFE (0xFFFFFFFFU) //!< Bit mask for PORT_DFER_DFE.
+#define BS_PORT_DFER_DFE (32U) //!< Bit field size in bits for PORT_DFER_DFE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PORT_DFER_DFE field.
+#define BR_PORT_DFER_DFE(x) (HW_PORT_DFER(x).U)
+#endif
+
+//! @brief Format value for bitfield PORT_DFER_DFE.
+#define BF_PORT_DFER_DFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_DFER_DFE), uint32_t) & BM_PORT_DFER_DFE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DFE field to a new value.
+#define BW_PORT_DFER_DFE(x, v) (HW_PORT_DFER_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PORT_DFCR - Digital Filter Clock Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PORT_DFCR - Digital Filter Clock Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is read only for ports that do not support a digital filter.
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ */
+typedef union _hw_port_dfcr
+{
+ uint32_t U;
+ struct _hw_port_dfcr_bitfields
+ {
+ uint32_t CS : 1; //!< [0] Clock Source
+ uint32_t RESERVED0 : 31; //!< [31:1]
+ } B;
+} hw_port_dfcr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PORT_DFCR register
+ */
+//@{
+#define HW_PORT_DFCR_ADDR(x) (REGS_PORT_BASE(x) + 0xC4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PORT_DFCR(x) (*(__IO hw_port_dfcr_t *) HW_PORT_DFCR_ADDR(x))
+#define HW_PORT_DFCR_RD(x) (HW_PORT_DFCR(x).U)
+#define HW_PORT_DFCR_WR(x, v) (HW_PORT_DFCR(x).U = (v))
+#define HW_PORT_DFCR_SET(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) | (v)))
+#define HW_PORT_DFCR_CLR(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) & ~(v)))
+#define HW_PORT_DFCR_TOG(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PORT_DFCR bitfields
+ */
+
+/*!
+ * @name Register PORT_DFCR, field CS[0] (RW)
+ *
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ * Configures the clock source for the digital input filters. Changing the filter
+ * clock source must be done only when all digital filters are disabled.
+ *
+ * Values:
+ * - 0 - Digital filters are clocked by the bus clock.
+ * - 1 - Digital filters are clocked by the 1 kHz LPO clock.
+ */
+//@{
+#define BP_PORT_DFCR_CS (0U) //!< Bit position for PORT_DFCR_CS.
+#define BM_PORT_DFCR_CS (0x00000001U) //!< Bit mask for PORT_DFCR_CS.
+#define BS_PORT_DFCR_CS (1U) //!< Bit field size in bits for PORT_DFCR_CS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PORT_DFCR_CS field.
+#define BR_PORT_DFCR_CS(x) (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS))
+#endif
+
+//! @brief Format value for bitfield PORT_DFCR_CS.
+#define BF_PORT_DFCR_CS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_DFCR_CS), uint32_t) & BM_PORT_DFCR_CS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CS field to a new value.
+#define BW_PORT_DFCR_CS(x, v) (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_PORT_DFWR - Digital Filter Width Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_PORT_DFWR - Digital Filter Width Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is read only for ports that do not support a digital filter.
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ */
+typedef union _hw_port_dfwr
+{
+ uint32_t U;
+ struct _hw_port_dfwr_bitfields
+ {
+ uint32_t FILT : 5; //!< [4:0] Filter Length
+ uint32_t RESERVED0 : 27; //!< [31:5]
+ } B;
+} hw_port_dfwr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire PORT_DFWR register
+ */
+//@{
+#define HW_PORT_DFWR_ADDR(x) (REGS_PORT_BASE(x) + 0xC8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_PORT_DFWR(x) (*(__IO hw_port_dfwr_t *) HW_PORT_DFWR_ADDR(x))
+#define HW_PORT_DFWR_RD(x) (HW_PORT_DFWR(x).U)
+#define HW_PORT_DFWR_WR(x, v) (HW_PORT_DFWR(x).U = (v))
+#define HW_PORT_DFWR_SET(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) | (v)))
+#define HW_PORT_DFWR_CLR(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) & ~(v)))
+#define HW_PORT_DFWR_TOG(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual PORT_DFWR bitfields
+ */
+
+/*!
+ * @name Register PORT_DFWR, field FILT[4:0] (RW)
+ *
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ * Configures the maximum size of the glitches, in clock cycles, that the digital
+ * filter absorbs for the enabled digital filters. Glitches that are longer than
+ * this register setting will pass through the digital filter, and glitches that
+ * are equal to or less than this register setting are filtered. Changing the
+ * filter length must be done only after all filters are disabled.
+ */
+//@{
+#define BP_PORT_DFWR_FILT (0U) //!< Bit position for PORT_DFWR_FILT.
+#define BM_PORT_DFWR_FILT (0x0000001FU) //!< Bit mask for PORT_DFWR_FILT.
+#define BS_PORT_DFWR_FILT (5U) //!< Bit field size in bits for PORT_DFWR_FILT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the PORT_DFWR_FILT field.
+#define BR_PORT_DFWR_FILT(x) (HW_PORT_DFWR(x).B.FILT)
+#endif
+
+//! @brief Format value for bitfield PORT_DFWR_FILT.
+#define BF_PORT_DFWR_FILT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PORT_DFWR_FILT), uint32_t) & BM_PORT_DFWR_FILT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FILT field to a new value.
+#define BW_PORT_DFWR_FILT(x, v) (HW_PORT_DFWR_WR(x, (HW_PORT_DFWR_RD(x) & ~BM_PORT_DFWR_FILT) | BF_PORT_DFWR_FILT(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_port_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All PORT module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_port
+{
+ __IO hw_port_pcrn_t PCRn[32]; //!< [0x0] Pin Control Register n
+ __O hw_port_gpclr_t GPCLR; //!< [0x80] Global Pin Control Low Register
+ __O hw_port_gpchr_t GPCHR; //!< [0x84] Global Pin Control High Register
+ uint8_t _reserved0[24];
+ __IO hw_port_isfr_t ISFR; //!< [0xA0] Interrupt Status Flag Register
+ uint8_t _reserved1[28];
+ __IO hw_port_dfer_t DFER; //!< [0xC0] Digital Filter Enable Register
+ __IO hw_port_dfcr_t DFCR; //!< [0xC4] Digital Filter Clock Register
+ __IO hw_port_dfwr_t DFWR; //!< [0xC8] Digital Filter Width Register
+} hw_port_t;
+#pragma pack()
+
+//! @brief Macro to access all PORT registers.
+//! @param x PORT instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_PORT(0)</code>.
+#define HW_PORT(x) (*(hw_port_t *) REGS_PORT_BASE(x))
+#endif
+
+#endif // __HW_PORT_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_rcm.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,730 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_RCM_REGISTERS_H__
+#define __HW_RCM_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 RCM
+ *
+ * Reset Control Module
+ *
+ * Registers defined in this header file:
+ * - HW_RCM_SRS0 - System Reset Status Register 0
+ * - HW_RCM_SRS1 - System Reset Status Register 1
+ * - HW_RCM_RPFC - Reset Pin Filter Control register
+ * - HW_RCM_RPFW - Reset Pin Filter Width register
+ * - HW_RCM_MR - Mode Register
+ *
+ * - hw_rcm_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_RCM_BASE
+#define HW_RCM_INSTANCE_COUNT (1U) //!< Number of instances of the RCM module.
+#define REGS_RCM_BASE (0x4007F000U) //!< Base address for RCM.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RCM_SRS0 - System Reset Status Register 0
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RCM_SRS0 - System Reset Status Register 0 (RO)
+ *
+ * Reset value: 0x82U
+ *
+ * This register includes read-only status flags to indicate the source of the
+ * most recent reset. The reset state of these bits depends on what caused the MCU
+ * to reset. The reset value of this register depends on the reset source: POR
+ * (including LVD) - 0x82 LVD (without POR) - 0x02 VLLS mode wakeup due to RESET
+ * pin assertion - 0x41 VLLS mode wakeup due to other wakeup sources - 0x01 Other
+ * reset - a bit is set if its corresponding reset source caused the reset
+ */
+typedef union _hw_rcm_srs0
+{
+ uint8_t U;
+ struct _hw_rcm_srs0_bitfields
+ {
+ uint8_t WAKEUP : 1; //!< [0] Low Leakage Wakeup Reset
+ uint8_t LVD : 1; //!< [1] Low-Voltage Detect Reset
+ uint8_t LOC : 1; //!< [2] Loss-of-Clock Reset
+ uint8_t LOL : 1; //!< [3] Loss-of-Lock Reset
+ uint8_t RESERVED0 : 1; //!< [4]
+ uint8_t WDOGb : 1; //!< [5] Watchdog
+ uint8_t PIN : 1; //!< [6] External Reset Pin
+ uint8_t POR : 1; //!< [7] Power-On Reset
+ } B;
+} hw_rcm_srs0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RCM_SRS0 register
+ */
+//@{
+#define HW_RCM_SRS0_ADDR (REGS_RCM_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RCM_SRS0 (*(__I hw_rcm_srs0_t *) HW_RCM_SRS0_ADDR)
+#define HW_RCM_SRS0_RD() (HW_RCM_SRS0.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RCM_SRS0 bitfields
+ */
+
+/*!
+ * @name Register RCM_SRS0, field WAKEUP[0] (RO)
+ *
+ * Indicates a reset has been caused by an enabled LLWU module wakeup source
+ * while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only
+ * wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx
+ * mode causes a reset. This bit is cleared by any reset except WAKEUP.
+ *
+ * Values:
+ * - 0 - Reset not caused by LLWU module wakeup source
+ * - 1 - Reset caused by LLWU module wakeup source
+ */
+//@{
+#define BP_RCM_SRS0_WAKEUP (0U) //!< Bit position for RCM_SRS0_WAKEUP.
+#define BM_RCM_SRS0_WAKEUP (0x01U) //!< Bit mask for RCM_SRS0_WAKEUP.
+#define BS_RCM_SRS0_WAKEUP (1U) //!< Bit field size in bits for RCM_SRS0_WAKEUP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_SRS0_WAKEUP field.
+#define BR_RCM_SRS0_WAKEUP (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_WAKEUP))
+#endif
+//@}
+
+/*!
+ * @name Register RCM_SRS0, field LVD[1] (RO)
+ *
+ * If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage,
+ * an LVD reset occurs. This field is also set by POR.
+ *
+ * Values:
+ * - 0 - Reset not caused by LVD trip or POR
+ * - 1 - Reset caused by LVD trip or POR
+ */
+//@{
+#define BP_RCM_SRS0_LVD (1U) //!< Bit position for RCM_SRS0_LVD.
+#define BM_RCM_SRS0_LVD (0x02U) //!< Bit mask for RCM_SRS0_LVD.
+#define BS_RCM_SRS0_LVD (1U) //!< Bit field size in bits for RCM_SRS0_LVD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_SRS0_LVD field.
+#define BR_RCM_SRS0_LVD (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_LVD))
+#endif
+//@}
+
+/*!
+ * @name Register RCM_SRS0, field LOC[2] (RO)
+ *
+ * Indicates a reset has been caused by a loss of external clock. The MCG clock
+ * monitor must be enabled for a loss of clock to be detected. Refer to the
+ * detailed MCG description for information on enabling the clock monitor.
+ *
+ * Values:
+ * - 0 - Reset not caused by a loss of external clock.
+ * - 1 - Reset caused by a loss of external clock.
+ */
+//@{
+#define BP_RCM_SRS0_LOC (2U) //!< Bit position for RCM_SRS0_LOC.
+#define BM_RCM_SRS0_LOC (0x04U) //!< Bit mask for RCM_SRS0_LOC.
+#define BS_RCM_SRS0_LOC (1U) //!< Bit field size in bits for RCM_SRS0_LOC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_SRS0_LOC field.
+#define BR_RCM_SRS0_LOC (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_LOC))
+#endif
+//@}
+
+/*!
+ * @name Register RCM_SRS0, field LOL[3] (RO)
+ *
+ * Indicates a reset has been caused by a loss of lock in the MCG PLL. See the
+ * MCG description for information on the loss-of-clock event.
+ *
+ * Values:
+ * - 0 - Reset not caused by a loss of lock in the PLL
+ * - 1 - Reset caused by a loss of lock in the PLL
+ */
+//@{
+#define BP_RCM_SRS0_LOL (3U) //!< Bit position for RCM_SRS0_LOL.
+#define BM_RCM_SRS0_LOL (0x08U) //!< Bit mask for RCM_SRS0_LOL.
+#define BS_RCM_SRS0_LOL (1U) //!< Bit field size in bits for RCM_SRS0_LOL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_SRS0_LOL field.
+#define BR_RCM_SRS0_LOL (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_LOL))
+#endif
+//@}
+
+/*!
+ * @name Register RCM_SRS0, field WDOG[5] (RO)
+ *
+ * Indicates a reset has been caused by the watchdog timer Computer Operating
+ * Properly (COP) timing out. This reset source can be blocked by disabling the COP
+ * watchdog: write 00 to SIM_COPCTRL[COPT].
+ *
+ * Values:
+ * - 0 - Reset not caused by watchdog timeout
+ * - 1 - Reset caused by watchdog timeout
+ */
+//@{
+#define BP_RCM_SRS0_WDOG (5U) //!< Bit position for RCM_SRS0_WDOG.
+#define BM_RCM_SRS0_WDOG (0x20U) //!< Bit mask for RCM_SRS0_WDOG.
+#define BS_RCM_SRS0_WDOG (1U) //!< Bit field size in bits for RCM_SRS0_WDOG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_SRS0_WDOG field.
+#define BR_RCM_SRS0_WDOG (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_WDOG))
+#endif
+//@}
+
+/*!
+ * @name Register RCM_SRS0, field PIN[6] (RO)
+ *
+ * Indicates a reset has been caused by an active-low level on the external
+ * RESET pin.
+ *
+ * Values:
+ * - 0 - Reset not caused by external reset pin
+ * - 1 - Reset caused by external reset pin
+ */
+//@{
+#define BP_RCM_SRS0_PIN (6U) //!< Bit position for RCM_SRS0_PIN.
+#define BM_RCM_SRS0_PIN (0x40U) //!< Bit mask for RCM_SRS0_PIN.
+#define BS_RCM_SRS0_PIN (1U) //!< Bit field size in bits for RCM_SRS0_PIN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_SRS0_PIN field.
+#define BR_RCM_SRS0_PIN (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_PIN))
+#endif
+//@}
+
+/*!
+ * @name Register RCM_SRS0, field POR[7] (RO)
+ *
+ * Indicates a reset has been caused by the power-on detection logic. Because
+ * the internal supply voltage was ramping up at the time, the low-voltage reset
+ * (LVD) status bit is also set to indicate that the reset occurred while the
+ * internal supply was below the LVD threshold.
+ *
+ * Values:
+ * - 0 - Reset not caused by POR
+ * - 1 - Reset caused by POR
+ */
+//@{
+#define BP_RCM_SRS0_POR (7U) //!< Bit position for RCM_SRS0_POR.
+#define BM_RCM_SRS0_POR (0x80U) //!< Bit mask for RCM_SRS0_POR.
+#define BS_RCM_SRS0_POR (1U) //!< Bit field size in bits for RCM_SRS0_POR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_SRS0_POR field.
+#define BR_RCM_SRS0_POR (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR, BP_RCM_SRS0_POR))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RCM_SRS1 - System Reset Status Register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RCM_SRS1 - System Reset Status Register 1 (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This register includes read-only status flags to indicate the source of the
+ * most recent reset. The reset state of these bits depends on what caused the MCU
+ * to reset. The reset value of this register depends on the reset source: POR
+ * (including LVD) - 0x00 LVD (without POR) - 0x00 VLLS mode wakeup - 0x00 Other
+ * reset - a bit is set if its corresponding reset source caused the reset
+ */
+typedef union _hw_rcm_srs1
+{
+ uint8_t U;
+ struct _hw_rcm_srs1_bitfields
+ {
+ uint8_t JTAG : 1; //!< [0] JTAG Generated Reset
+ uint8_t LOCKUP : 1; //!< [1] Core Lockup
+ uint8_t SW : 1; //!< [2] Software
+ uint8_t MDM_AP : 1; //!< [3] MDM-AP System Reset Request
+ uint8_t EZPT : 1; //!< [4] EzPort Reset
+ uint8_t SACKERR : 1; //!< [5] Stop Mode Acknowledge Error Reset
+ uint8_t RESERVED0 : 2; //!< [7:6]
+ } B;
+} hw_rcm_srs1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RCM_SRS1 register
+ */
+//@{
+#define HW_RCM_SRS1_ADDR (REGS_RCM_BASE + 0x1U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RCM_SRS1 (*(__I hw_rcm_srs1_t *) HW_RCM_SRS1_ADDR)
+#define HW_RCM_SRS1_RD() (HW_RCM_SRS1.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RCM_SRS1 bitfields
+ */
+
+/*!
+ * @name Register RCM_SRS1, field JTAG[0] (RO)
+ *
+ * Indicates a reset has been caused by JTAG selection of certain IR codes:
+ * EZPORT, EXTEST, HIGHZ, and CLAMP.
+ *
+ * Values:
+ * - 0 - Reset not caused by JTAG
+ * - 1 - Reset caused by JTAG
+ */
+//@{
+#define BP_RCM_SRS1_JTAG (0U) //!< Bit position for RCM_SRS1_JTAG.
+#define BM_RCM_SRS1_JTAG (0x01U) //!< Bit mask for RCM_SRS1_JTAG.
+#define BS_RCM_SRS1_JTAG (1U) //!< Bit field size in bits for RCM_SRS1_JTAG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_SRS1_JTAG field.
+#define BR_RCM_SRS1_JTAG (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_JTAG))
+#endif
+//@}
+
+/*!
+ * @name Register RCM_SRS1, field LOCKUP[1] (RO)
+ *
+ * Indicates a reset has been caused by the ARM core indication of a LOCKUP
+ * event.
+ *
+ * Values:
+ * - 0 - Reset not caused by core LOCKUP event
+ * - 1 - Reset caused by core LOCKUP event
+ */
+//@{
+#define BP_RCM_SRS1_LOCKUP (1U) //!< Bit position for RCM_SRS1_LOCKUP.
+#define BM_RCM_SRS1_LOCKUP (0x02U) //!< Bit mask for RCM_SRS1_LOCKUP.
+#define BS_RCM_SRS1_LOCKUP (1U) //!< Bit field size in bits for RCM_SRS1_LOCKUP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_SRS1_LOCKUP field.
+#define BR_RCM_SRS1_LOCKUP (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_LOCKUP))
+#endif
+//@}
+
+/*!
+ * @name Register RCM_SRS1, field SW[2] (RO)
+ *
+ * Indicates a reset has been caused by software setting of SYSRESETREQ bit in
+ * Application Interrupt and Reset Control Register in the ARM core.
+ *
+ * Values:
+ * - 0 - Reset not caused by software setting of SYSRESETREQ bit
+ * - 1 - Reset caused by software setting of SYSRESETREQ bit
+ */
+//@{
+#define BP_RCM_SRS1_SW (2U) //!< Bit position for RCM_SRS1_SW.
+#define BM_RCM_SRS1_SW (0x04U) //!< Bit mask for RCM_SRS1_SW.
+#define BS_RCM_SRS1_SW (1U) //!< Bit field size in bits for RCM_SRS1_SW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_SRS1_SW field.
+#define BR_RCM_SRS1_SW (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_SW))
+#endif
+//@}
+
+/*!
+ * @name Register RCM_SRS1, field MDM_AP[3] (RO)
+ *
+ * Indicates a reset has been caused by the host debugger system setting of the
+ * System Reset Request bit in the MDM-AP Control Register.
+ *
+ * Values:
+ * - 0 - Reset not caused by host debugger system setting of the System Reset
+ * Request bit
+ * - 1 - Reset caused by host debugger system setting of the System Reset
+ * Request bit
+ */
+//@{
+#define BP_RCM_SRS1_MDM_AP (3U) //!< Bit position for RCM_SRS1_MDM_AP.
+#define BM_RCM_SRS1_MDM_AP (0x08U) //!< Bit mask for RCM_SRS1_MDM_AP.
+#define BS_RCM_SRS1_MDM_AP (1U) //!< Bit field size in bits for RCM_SRS1_MDM_AP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_SRS1_MDM_AP field.
+#define BR_RCM_SRS1_MDM_AP (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_MDM_AP))
+#endif
+//@}
+
+/*!
+ * @name Register RCM_SRS1, field EZPT[4] (RO)
+ *
+ * Indicates a reset has been caused by EzPort receiving the RESET command while
+ * the device is in EzPort mode.
+ *
+ * Values:
+ * - 0 - Reset not caused by EzPort receiving the RESET command while the device
+ * is in EzPort mode
+ * - 1 - Reset caused by EzPort receiving the RESET command while the device is
+ * in EzPort mode
+ */
+//@{
+#define BP_RCM_SRS1_EZPT (4U) //!< Bit position for RCM_SRS1_EZPT.
+#define BM_RCM_SRS1_EZPT (0x10U) //!< Bit mask for RCM_SRS1_EZPT.
+#define BS_RCM_SRS1_EZPT (1U) //!< Bit field size in bits for RCM_SRS1_EZPT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_SRS1_EZPT field.
+#define BR_RCM_SRS1_EZPT (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_EZPT))
+#endif
+//@}
+
+/*!
+ * @name Register RCM_SRS1, field SACKERR[5] (RO)
+ *
+ * Indicates that after an attempt to enter Stop mode, a reset has been caused
+ * by a failure of one or more peripherals to acknowledge within approximately one
+ * second to enter stop mode.
+ *
+ * Values:
+ * - 0 - Reset not caused by peripheral failure to acknowledge attempt to enter
+ * stop mode
+ * - 1 - Reset caused by peripheral failure to acknowledge attempt to enter stop
+ * mode
+ */
+//@{
+#define BP_RCM_SRS1_SACKERR (5U) //!< Bit position for RCM_SRS1_SACKERR.
+#define BM_RCM_SRS1_SACKERR (0x20U) //!< Bit mask for RCM_SRS1_SACKERR.
+#define BS_RCM_SRS1_SACKERR (1U) //!< Bit field size in bits for RCM_SRS1_SACKERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_SRS1_SACKERR field.
+#define BR_RCM_SRS1_SACKERR (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR, BP_RCM_SRS1_SACKERR))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RCM_RPFC - Reset Pin Filter Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RCM_RPFC - Reset Pin Filter Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The reset values of bits 2-0 are for Chip POR only. They are unaffected by
+ * other reset types. The bus clock filter is reset when disabled or when entering
+ * stop mode. The LPO filter is reset when disabled or when entering any low
+ * leakage stop mode .
+ */
+typedef union _hw_rcm_rpfc
+{
+ uint8_t U;
+ struct _hw_rcm_rpfc_bitfields
+ {
+ uint8_t RSTFLTSRW : 2; //!< [1:0] Reset Pin Filter Select in Run and
+ //! Wait Modes
+ uint8_t RSTFLTSS : 1; //!< [2] Reset Pin Filter Select in Stop Mode
+ uint8_t RESERVED0 : 5; //!< [7:3]
+ } B;
+} hw_rcm_rpfc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RCM_RPFC register
+ */
+//@{
+#define HW_RCM_RPFC_ADDR (REGS_RCM_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RCM_RPFC (*(__IO hw_rcm_rpfc_t *) HW_RCM_RPFC_ADDR)
+#define HW_RCM_RPFC_RD() (HW_RCM_RPFC.U)
+#define HW_RCM_RPFC_WR(v) (HW_RCM_RPFC.U = (v))
+#define HW_RCM_RPFC_SET(v) (HW_RCM_RPFC_WR(HW_RCM_RPFC_RD() | (v)))
+#define HW_RCM_RPFC_CLR(v) (HW_RCM_RPFC_WR(HW_RCM_RPFC_RD() & ~(v)))
+#define HW_RCM_RPFC_TOG(v) (HW_RCM_RPFC_WR(HW_RCM_RPFC_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RCM_RPFC bitfields
+ */
+
+/*!
+ * @name Register RCM_RPFC, field RSTFLTSRW[1:0] (RW)
+ *
+ * Selects how the reset pin filter is enabled in run and wait modes.
+ *
+ * Values:
+ * - 00 - All filtering disabled
+ * - 01 - Bus clock filter enabled for normal operation
+ * - 10 - LPO clock filter enabled for normal operation
+ * - 11 - Reserved
+ */
+//@{
+#define BP_RCM_RPFC_RSTFLTSRW (0U) //!< Bit position for RCM_RPFC_RSTFLTSRW.
+#define BM_RCM_RPFC_RSTFLTSRW (0x03U) //!< Bit mask for RCM_RPFC_RSTFLTSRW.
+#define BS_RCM_RPFC_RSTFLTSRW (2U) //!< Bit field size in bits for RCM_RPFC_RSTFLTSRW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_RPFC_RSTFLTSRW field.
+#define BR_RCM_RPFC_RSTFLTSRW (HW_RCM_RPFC.B.RSTFLTSRW)
+#endif
+
+//! @brief Format value for bitfield RCM_RPFC_RSTFLTSRW.
+#define BF_RCM_RPFC_RSTFLTSRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_RCM_RPFC_RSTFLTSRW), uint8_t) & BM_RCM_RPFC_RSTFLTSRW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RSTFLTSRW field to a new value.
+#define BW_RCM_RPFC_RSTFLTSRW(v) (HW_RCM_RPFC_WR((HW_RCM_RPFC_RD() & ~BM_RCM_RPFC_RSTFLTSRW) | BF_RCM_RPFC_RSTFLTSRW(v)))
+#endif
+//@}
+
+/*!
+ * @name Register RCM_RPFC, field RSTFLTSS[2] (RW)
+ *
+ * Selects how the reset pin filter is enabled in Stop and VLPS modes
+ *
+ * Values:
+ * - 0 - All filtering disabled
+ * - 1 - LPO clock filter enabled
+ */
+//@{
+#define BP_RCM_RPFC_RSTFLTSS (2U) //!< Bit position for RCM_RPFC_RSTFLTSS.
+#define BM_RCM_RPFC_RSTFLTSS (0x04U) //!< Bit mask for RCM_RPFC_RSTFLTSS.
+#define BS_RCM_RPFC_RSTFLTSS (1U) //!< Bit field size in bits for RCM_RPFC_RSTFLTSS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_RPFC_RSTFLTSS field.
+#define BR_RCM_RPFC_RSTFLTSS (BITBAND_ACCESS8(HW_RCM_RPFC_ADDR, BP_RCM_RPFC_RSTFLTSS))
+#endif
+
+//! @brief Format value for bitfield RCM_RPFC_RSTFLTSS.
+#define BF_RCM_RPFC_RSTFLTSS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_RCM_RPFC_RSTFLTSS), uint8_t) & BM_RCM_RPFC_RSTFLTSS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RSTFLTSS field to a new value.
+#define BW_RCM_RPFC_RSTFLTSS(v) (BITBAND_ACCESS8(HW_RCM_RPFC_ADDR, BP_RCM_RPFC_RSTFLTSS) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RCM_RPFW - Reset Pin Filter Width register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RCM_RPFW - Reset Pin Filter Width register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The reset values of the bits in the RSTFLTSEL field are for Chip POR only.
+ * They are unaffected by other reset types.
+ */
+typedef union _hw_rcm_rpfw
+{
+ uint8_t U;
+ struct _hw_rcm_rpfw_bitfields
+ {
+ uint8_t RSTFLTSEL : 5; //!< [4:0] Reset Pin Filter Bus Clock Select
+ uint8_t RESERVED0 : 3; //!< [7:5]
+ } B;
+} hw_rcm_rpfw_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RCM_RPFW register
+ */
+//@{
+#define HW_RCM_RPFW_ADDR (REGS_RCM_BASE + 0x5U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RCM_RPFW (*(__IO hw_rcm_rpfw_t *) HW_RCM_RPFW_ADDR)
+#define HW_RCM_RPFW_RD() (HW_RCM_RPFW.U)
+#define HW_RCM_RPFW_WR(v) (HW_RCM_RPFW.U = (v))
+#define HW_RCM_RPFW_SET(v) (HW_RCM_RPFW_WR(HW_RCM_RPFW_RD() | (v)))
+#define HW_RCM_RPFW_CLR(v) (HW_RCM_RPFW_WR(HW_RCM_RPFW_RD() & ~(v)))
+#define HW_RCM_RPFW_TOG(v) (HW_RCM_RPFW_WR(HW_RCM_RPFW_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RCM_RPFW bitfields
+ */
+
+/*!
+ * @name Register RCM_RPFW, field RSTFLTSEL[4:0] (RW)
+ *
+ * Selects the reset pin bus clock filter width.
+ *
+ * Values:
+ * - 00000 - Bus clock filter count is 1
+ * - 00001 - Bus clock filter count is 2
+ * - 00010 - Bus clock filter count is 3
+ * - 00011 - Bus clock filter count is 4
+ * - 00100 - Bus clock filter count is 5
+ * - 00101 - Bus clock filter count is 6
+ * - 00110 - Bus clock filter count is 7
+ * - 00111 - Bus clock filter count is 8
+ * - 01000 - Bus clock filter count is 9
+ * - 01001 - Bus clock filter count is 10
+ * - 01010 - Bus clock filter count is 11
+ * - 01011 - Bus clock filter count is 12
+ * - 01100 - Bus clock filter count is 13
+ * - 01101 - Bus clock filter count is 14
+ * - 01110 - Bus clock filter count is 15
+ * - 01111 - Bus clock filter count is 16
+ * - 10000 - Bus clock filter count is 17
+ * - 10001 - Bus clock filter count is 18
+ * - 10010 - Bus clock filter count is 19
+ * - 10011 - Bus clock filter count is 20
+ * - 10100 - Bus clock filter count is 21
+ * - 10101 - Bus clock filter count is 22
+ * - 10110 - Bus clock filter count is 23
+ * - 10111 - Bus clock filter count is 24
+ * - 11000 - Bus clock filter count is 25
+ * - 11001 - Bus clock filter count is 26
+ * - 11010 - Bus clock filter count is 27
+ * - 11011 - Bus clock filter count is 28
+ * - 11100 - Bus clock filter count is 29
+ * - 11101 - Bus clock filter count is 30
+ * - 11110 - Bus clock filter count is 31
+ * - 11111 - Bus clock filter count is 32
+ */
+//@{
+#define BP_RCM_RPFW_RSTFLTSEL (0U) //!< Bit position for RCM_RPFW_RSTFLTSEL.
+#define BM_RCM_RPFW_RSTFLTSEL (0x1FU) //!< Bit mask for RCM_RPFW_RSTFLTSEL.
+#define BS_RCM_RPFW_RSTFLTSEL (5U) //!< Bit field size in bits for RCM_RPFW_RSTFLTSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_RPFW_RSTFLTSEL field.
+#define BR_RCM_RPFW_RSTFLTSEL (HW_RCM_RPFW.B.RSTFLTSEL)
+#endif
+
+//! @brief Format value for bitfield RCM_RPFW_RSTFLTSEL.
+#define BF_RCM_RPFW_RSTFLTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_RCM_RPFW_RSTFLTSEL), uint8_t) & BM_RCM_RPFW_RSTFLTSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RSTFLTSEL field to a new value.
+#define BW_RCM_RPFW_RSTFLTSEL(v) (HW_RCM_RPFW_WR((HW_RCM_RPFW_RD() & ~BM_RCM_RPFW_RSTFLTSEL) | BF_RCM_RPFW_RSTFLTSEL(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RCM_MR - Mode Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RCM_MR - Mode Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This register includes read-only status flags to indicate the state of the
+ * mode pins during the last Chip Reset.
+ */
+typedef union _hw_rcm_mr
+{
+ uint8_t U;
+ struct _hw_rcm_mr_bitfields
+ {
+ uint8_t RESERVED0 : 1; //!< [0]
+ uint8_t EZP_MS : 1; //!< [1] EZP_MS_B pin state
+ uint8_t RESERVED1 : 6; //!< [7:2]
+ } B;
+} hw_rcm_mr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RCM_MR register
+ */
+//@{
+#define HW_RCM_MR_ADDR (REGS_RCM_BASE + 0x7U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RCM_MR (*(__I hw_rcm_mr_t *) HW_RCM_MR_ADDR)
+#define HW_RCM_MR_RD() (HW_RCM_MR.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RCM_MR bitfields
+ */
+
+/*!
+ * @name Register RCM_MR, field EZP_MS[1] (RO)
+ *
+ * Reflects the state of the EZP_MS pin during the last Chip Reset
+ *
+ * Values:
+ * - 0 - Pin deasserted (logic 1)
+ * - 1 - Pin asserted (logic 0)
+ */
+//@{
+#define BP_RCM_MR_EZP_MS (1U) //!< Bit position for RCM_MR_EZP_MS.
+#define BM_RCM_MR_EZP_MS (0x02U) //!< Bit mask for RCM_MR_EZP_MS.
+#define BS_RCM_MR_EZP_MS (1U) //!< Bit field size in bits for RCM_MR_EZP_MS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RCM_MR_EZP_MS field.
+#define BR_RCM_MR_EZP_MS (BITBAND_ACCESS8(HW_RCM_MR_ADDR, BP_RCM_MR_EZP_MS))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_rcm_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All RCM module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_rcm
+{
+ __I hw_rcm_srs0_t SRS0; //!< [0x0] System Reset Status Register 0
+ __I hw_rcm_srs1_t SRS1; //!< [0x1] System Reset Status Register 1
+ uint8_t _reserved0[2];
+ __IO hw_rcm_rpfc_t RPFC; //!< [0x4] Reset Pin Filter Control register
+ __IO hw_rcm_rpfw_t RPFW; //!< [0x5] Reset Pin Filter Width register
+ uint8_t _reserved1[1];
+ __I hw_rcm_mr_t MR; //!< [0x7] Mode Register
+} hw_rcm_t;
+#pragma pack()
+
+//! @brief Macro to access all RCM registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_RCM</code>.
+#define HW_RCM (*(hw_rcm_t *) REGS_RCM_BASE)
+#endif
+
+#endif // __HW_RCM_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_rfsys.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,210 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_RFSYS_REGISTERS_H__
+#define __HW_RFSYS_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 RFSYS
+ *
+ * System register file
+ *
+ * Registers defined in this header file:
+ * - HW_RFSYS_REGn - Register file register
+ *
+ * - hw_rfsys_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_RFSYS_BASE
+#define HW_RFSYS_INSTANCE_COUNT (1U) //!< Number of instances of the RFSYS module.
+#define REGS_RFSYS_BASE (0x40041000U) //!< Base address for RFSYS.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RFSYS_REGn - Register file register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RFSYS_REGn - Register file register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each register can be accessed as 8-, 16-, or 32-bits.
+ */
+typedef union _hw_rfsys_regn
+{
+ uint32_t U;
+ struct _hw_rfsys_regn_bitfields
+ {
+ uint32_t LL : 8; //!< [7:0]
+ uint32_t LH : 8; //!< [15:8]
+ uint32_t HL : 8; //!< [23:16]
+ uint32_t HH : 8; //!< [31:24]
+ } B;
+} hw_rfsys_regn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RFSYS_REGn register
+ */
+//@{
+#define HW_RFSYS_REGn_COUNT (8U)
+
+#define HW_RFSYS_REGn_ADDR(n) (REGS_RFSYS_BASE + 0x0U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RFSYS_REGn(n) (*(__IO hw_rfsys_regn_t *) HW_RFSYS_REGn_ADDR(n))
+#define HW_RFSYS_REGn_RD(n) (HW_RFSYS_REGn(n).U)
+#define HW_RFSYS_REGn_WR(n, v) (HW_RFSYS_REGn(n).U = (v))
+#define HW_RFSYS_REGn_SET(n, v) (HW_RFSYS_REGn_WR(n, HW_RFSYS_REGn_RD(n) | (v)))
+#define HW_RFSYS_REGn_CLR(n, v) (HW_RFSYS_REGn_WR(n, HW_RFSYS_REGn_RD(n) & ~(v)))
+#define HW_RFSYS_REGn_TOG(n, v) (HW_RFSYS_REGn_WR(n, HW_RFSYS_REGn_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RFSYS_REGn bitfields
+ */
+
+/*!
+ * @name Register RFSYS_REGn, field LL[7:0] (RW)
+ *
+ * Low lower byte
+ */
+//@{
+#define BP_RFSYS_REGn_LL (0U) //!< Bit position for RFSYS_REGn_LL.
+#define BM_RFSYS_REGn_LL (0x000000FFU) //!< Bit mask for RFSYS_REGn_LL.
+#define BS_RFSYS_REGn_LL (8U) //!< Bit field size in bits for RFSYS_REGn_LL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RFSYS_REGn_LL field.
+#define BR_RFSYS_REGn_LL(n) (HW_RFSYS_REGn(n).B.LL)
+#endif
+
+//! @brief Format value for bitfield RFSYS_REGn_LL.
+#define BF_RFSYS_REGn_LL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFSYS_REGn_LL), uint32_t) & BM_RFSYS_REGn_LL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LL field to a new value.
+#define BW_RFSYS_REGn_LL(n, v) (HW_RFSYS_REGn_WR(n, (HW_RFSYS_REGn_RD(n) & ~BM_RFSYS_REGn_LL) | BF_RFSYS_REGn_LL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register RFSYS_REGn, field LH[15:8] (RW)
+ *
+ * Low higher byte
+ */
+//@{
+#define BP_RFSYS_REGn_LH (8U) //!< Bit position for RFSYS_REGn_LH.
+#define BM_RFSYS_REGn_LH (0x0000FF00U) //!< Bit mask for RFSYS_REGn_LH.
+#define BS_RFSYS_REGn_LH (8U) //!< Bit field size in bits for RFSYS_REGn_LH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RFSYS_REGn_LH field.
+#define BR_RFSYS_REGn_LH(n) (HW_RFSYS_REGn(n).B.LH)
+#endif
+
+//! @brief Format value for bitfield RFSYS_REGn_LH.
+#define BF_RFSYS_REGn_LH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFSYS_REGn_LH), uint32_t) & BM_RFSYS_REGn_LH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LH field to a new value.
+#define BW_RFSYS_REGn_LH(n, v) (HW_RFSYS_REGn_WR(n, (HW_RFSYS_REGn_RD(n) & ~BM_RFSYS_REGn_LH) | BF_RFSYS_REGn_LH(v)))
+#endif
+//@}
+
+/*!
+ * @name Register RFSYS_REGn, field HL[23:16] (RW)
+ *
+ * High lower byte
+ */
+//@{
+#define BP_RFSYS_REGn_HL (16U) //!< Bit position for RFSYS_REGn_HL.
+#define BM_RFSYS_REGn_HL (0x00FF0000U) //!< Bit mask for RFSYS_REGn_HL.
+#define BS_RFSYS_REGn_HL (8U) //!< Bit field size in bits for RFSYS_REGn_HL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RFSYS_REGn_HL field.
+#define BR_RFSYS_REGn_HL(n) (HW_RFSYS_REGn(n).B.HL)
+#endif
+
+//! @brief Format value for bitfield RFSYS_REGn_HL.
+#define BF_RFSYS_REGn_HL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFSYS_REGn_HL), uint32_t) & BM_RFSYS_REGn_HL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HL field to a new value.
+#define BW_RFSYS_REGn_HL(n, v) (HW_RFSYS_REGn_WR(n, (HW_RFSYS_REGn_RD(n) & ~BM_RFSYS_REGn_HL) | BF_RFSYS_REGn_HL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register RFSYS_REGn, field HH[31:24] (RW)
+ *
+ * High higher byte
+ */
+//@{
+#define BP_RFSYS_REGn_HH (24U) //!< Bit position for RFSYS_REGn_HH.
+#define BM_RFSYS_REGn_HH (0xFF000000U) //!< Bit mask for RFSYS_REGn_HH.
+#define BS_RFSYS_REGn_HH (8U) //!< Bit field size in bits for RFSYS_REGn_HH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RFSYS_REGn_HH field.
+#define BR_RFSYS_REGn_HH(n) (HW_RFSYS_REGn(n).B.HH)
+#endif
+
+//! @brief Format value for bitfield RFSYS_REGn_HH.
+#define BF_RFSYS_REGn_HH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFSYS_REGn_HH), uint32_t) & BM_RFSYS_REGn_HH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HH field to a new value.
+#define BW_RFSYS_REGn_HH(n, v) (HW_RFSYS_REGn_WR(n, (HW_RFSYS_REGn_RD(n) & ~BM_RFSYS_REGn_HH) | BF_RFSYS_REGn_HH(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_rfsys_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All RFSYS module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_rfsys
+{
+ __IO hw_rfsys_regn_t REGn[8]; //!< [0x0] Register file register
+} hw_rfsys_t;
+#pragma pack()
+
+//! @brief Macro to access all RFSYS registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_RFSYS</code>.
+#define HW_RFSYS (*(hw_rfsys_t *) REGS_RFSYS_BASE)
+#endif
+
+#endif // __HW_RFSYS_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_rfvbat.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,210 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_RFVBAT_REGISTERS_H__
+#define __HW_RFVBAT_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 RFVBAT
+ *
+ * VBAT register file
+ *
+ * Registers defined in this header file:
+ * - HW_RFVBAT_REGn - VBAT register file register
+ *
+ * - hw_rfvbat_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_RFVBAT_BASE
+#define HW_RFVBAT_INSTANCE_COUNT (1U) //!< Number of instances of the RFVBAT module.
+#define REGS_RFVBAT_BASE (0x4003E000U) //!< Base address for RFVBAT.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RFVBAT_REGn - VBAT register file register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RFVBAT_REGn - VBAT register file register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each register can be accessed as 8-, 16-, or 32-bits.
+ */
+typedef union _hw_rfvbat_regn
+{
+ uint32_t U;
+ struct _hw_rfvbat_regn_bitfields
+ {
+ uint32_t LL : 8; //!< [7:0]
+ uint32_t LH : 8; //!< [15:8]
+ uint32_t HL : 8; //!< [23:16]
+ uint32_t HH : 8; //!< [31:24]
+ } B;
+} hw_rfvbat_regn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RFVBAT_REGn register
+ */
+//@{
+#define HW_RFVBAT_REGn_COUNT (8U)
+
+#define HW_RFVBAT_REGn_ADDR(n) (REGS_RFVBAT_BASE + 0x0U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RFVBAT_REGn(n) (*(__IO hw_rfvbat_regn_t *) HW_RFVBAT_REGn_ADDR(n))
+#define HW_RFVBAT_REGn_RD(n) (HW_RFVBAT_REGn(n).U)
+#define HW_RFVBAT_REGn_WR(n, v) (HW_RFVBAT_REGn(n).U = (v))
+#define HW_RFVBAT_REGn_SET(n, v) (HW_RFVBAT_REGn_WR(n, HW_RFVBAT_REGn_RD(n) | (v)))
+#define HW_RFVBAT_REGn_CLR(n, v) (HW_RFVBAT_REGn_WR(n, HW_RFVBAT_REGn_RD(n) & ~(v)))
+#define HW_RFVBAT_REGn_TOG(n, v) (HW_RFVBAT_REGn_WR(n, HW_RFVBAT_REGn_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RFVBAT_REGn bitfields
+ */
+
+/*!
+ * @name Register RFVBAT_REGn, field LL[7:0] (RW)
+ *
+ * Low lower byte
+ */
+//@{
+#define BP_RFVBAT_REGn_LL (0U) //!< Bit position for RFVBAT_REGn_LL.
+#define BM_RFVBAT_REGn_LL (0x000000FFU) //!< Bit mask for RFVBAT_REGn_LL.
+#define BS_RFVBAT_REGn_LL (8U) //!< Bit field size in bits for RFVBAT_REGn_LL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RFVBAT_REGn_LL field.
+#define BR_RFVBAT_REGn_LL(n) (HW_RFVBAT_REGn(n).B.LL)
+#endif
+
+//! @brief Format value for bitfield RFVBAT_REGn_LL.
+#define BF_RFVBAT_REGn_LL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFVBAT_REGn_LL), uint32_t) & BM_RFVBAT_REGn_LL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LL field to a new value.
+#define BW_RFVBAT_REGn_LL(n, v) (HW_RFVBAT_REGn_WR(n, (HW_RFVBAT_REGn_RD(n) & ~BM_RFVBAT_REGn_LL) | BF_RFVBAT_REGn_LL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register RFVBAT_REGn, field LH[15:8] (RW)
+ *
+ * Low higher byte
+ */
+//@{
+#define BP_RFVBAT_REGn_LH (8U) //!< Bit position for RFVBAT_REGn_LH.
+#define BM_RFVBAT_REGn_LH (0x0000FF00U) //!< Bit mask for RFVBAT_REGn_LH.
+#define BS_RFVBAT_REGn_LH (8U) //!< Bit field size in bits for RFVBAT_REGn_LH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RFVBAT_REGn_LH field.
+#define BR_RFVBAT_REGn_LH(n) (HW_RFVBAT_REGn(n).B.LH)
+#endif
+
+//! @brief Format value for bitfield RFVBAT_REGn_LH.
+#define BF_RFVBAT_REGn_LH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFVBAT_REGn_LH), uint32_t) & BM_RFVBAT_REGn_LH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LH field to a new value.
+#define BW_RFVBAT_REGn_LH(n, v) (HW_RFVBAT_REGn_WR(n, (HW_RFVBAT_REGn_RD(n) & ~BM_RFVBAT_REGn_LH) | BF_RFVBAT_REGn_LH(v)))
+#endif
+//@}
+
+/*!
+ * @name Register RFVBAT_REGn, field HL[23:16] (RW)
+ *
+ * High lower byte
+ */
+//@{
+#define BP_RFVBAT_REGn_HL (16U) //!< Bit position for RFVBAT_REGn_HL.
+#define BM_RFVBAT_REGn_HL (0x00FF0000U) //!< Bit mask for RFVBAT_REGn_HL.
+#define BS_RFVBAT_REGn_HL (8U) //!< Bit field size in bits for RFVBAT_REGn_HL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RFVBAT_REGn_HL field.
+#define BR_RFVBAT_REGn_HL(n) (HW_RFVBAT_REGn(n).B.HL)
+#endif
+
+//! @brief Format value for bitfield RFVBAT_REGn_HL.
+#define BF_RFVBAT_REGn_HL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFVBAT_REGn_HL), uint32_t) & BM_RFVBAT_REGn_HL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HL field to a new value.
+#define BW_RFVBAT_REGn_HL(n, v) (HW_RFVBAT_REGn_WR(n, (HW_RFVBAT_REGn_RD(n) & ~BM_RFVBAT_REGn_HL) | BF_RFVBAT_REGn_HL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register RFVBAT_REGn, field HH[31:24] (RW)
+ *
+ * High higher byte
+ */
+//@{
+#define BP_RFVBAT_REGn_HH (24U) //!< Bit position for RFVBAT_REGn_HH.
+#define BM_RFVBAT_REGn_HH (0xFF000000U) //!< Bit mask for RFVBAT_REGn_HH.
+#define BS_RFVBAT_REGn_HH (8U) //!< Bit field size in bits for RFVBAT_REGn_HH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RFVBAT_REGn_HH field.
+#define BR_RFVBAT_REGn_HH(n) (HW_RFVBAT_REGn(n).B.HH)
+#endif
+
+//! @brief Format value for bitfield RFVBAT_REGn_HH.
+#define BF_RFVBAT_REGn_HH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RFVBAT_REGn_HH), uint32_t) & BM_RFVBAT_REGn_HH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HH field to a new value.
+#define BW_RFVBAT_REGn_HH(n, v) (HW_RFVBAT_REGn_WR(n, (HW_RFVBAT_REGn_RD(n) & ~BM_RFVBAT_REGn_HH) | BF_RFVBAT_REGn_HH(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_rfvbat_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All RFVBAT module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_rfvbat
+{
+ __IO hw_rfvbat_regn_t REGn[8]; //!< [0x0] VBAT register file register
+} hw_rfvbat_t;
+#pragma pack()
+
+//! @brief Macro to access all RFVBAT registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_RFVBAT</code>.
+#define HW_RFVBAT (*(hw_rfvbat_t *) REGS_RFVBAT_BASE)
+#endif
+
+#endif // __HW_RFVBAT_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_rng.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,590 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_RNG_REGISTERS_H__
+#define __HW_RNG_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 RNG
+ *
+ * Random Number Generator Accelerator
+ *
+ * Registers defined in this header file:
+ * - HW_RNG_CR - RNGA Control Register
+ * - HW_RNG_SR - RNGA Status Register
+ * - HW_RNG_ER - RNGA Entropy Register
+ * - HW_RNG_OR - RNGA Output Register
+ *
+ * - hw_rng_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_RNG_BASE
+#define HW_RNG_INSTANCE_COUNT (1U) //!< Number of instances of the RNG module.
+#define REGS_RNG_BASE (0x40029000U) //!< Base address for RNG.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RNG_CR - RNGA Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RNG_CR - RNGA Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Controls the operation of RNGA.
+ */
+typedef union _hw_rng_cr
+{
+ uint32_t U;
+ struct _hw_rng_cr_bitfields
+ {
+ uint32_t GO : 1; //!< [0] Go
+ uint32_t HA : 1; //!< [1] High Assurance
+ uint32_t INTM : 1; //!< [2] Interrupt Mask
+ uint32_t CLRI : 1; //!< [3] Clear Interrupt
+ uint32_t SLP : 1; //!< [4] Sleep
+ uint32_t RESERVED0 : 27; //!< [31:5]
+ } B;
+} hw_rng_cr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RNG_CR register
+ */
+//@{
+#define HW_RNG_CR_ADDR (REGS_RNG_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RNG_CR (*(__IO hw_rng_cr_t *) HW_RNG_CR_ADDR)
+#define HW_RNG_CR_RD() (HW_RNG_CR.U)
+#define HW_RNG_CR_WR(v) (HW_RNG_CR.U = (v))
+#define HW_RNG_CR_SET(v) (HW_RNG_CR_WR(HW_RNG_CR_RD() | (v)))
+#define HW_RNG_CR_CLR(v) (HW_RNG_CR_WR(HW_RNG_CR_RD() & ~(v)))
+#define HW_RNG_CR_TOG(v) (HW_RNG_CR_WR(HW_RNG_CR_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RNG_CR bitfields
+ */
+
+/*!
+ * @name Register RNG_CR, field GO[0] (RW)
+ *
+ * Specifies whether random-data generation and loading (into OR[RANDOUT]) is
+ * enabled.This field is sticky. You must reset RNGA to stop RNGA from loading
+ * OR[RANDOUT] with data.
+ *
+ * Values:
+ * - 0 - Disabled
+ * - 1 - Enabled
+ */
+//@{
+#define BP_RNG_CR_GO (0U) //!< Bit position for RNG_CR_GO.
+#define BM_RNG_CR_GO (0x00000001U) //!< Bit mask for RNG_CR_GO.
+#define BS_RNG_CR_GO (1U) //!< Bit field size in bits for RNG_CR_GO.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RNG_CR_GO field.
+#define BR_RNG_CR_GO (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_GO))
+#endif
+
+//! @brief Format value for bitfield RNG_CR_GO.
+#define BF_RNG_CR_GO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_GO), uint32_t) & BM_RNG_CR_GO)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GO field to a new value.
+#define BW_RNG_CR_GO(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_GO) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RNG_CR, field HA[1] (RW)
+ *
+ * Enables notification of security violations (via SR[SECV]). A security
+ * violation occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0. This field is sticky.
+ * After enabling notification of security violations, you must reset RNGA to
+ * disable them again.
+ *
+ * Values:
+ * - 0 - Disabled
+ * - 1 - Enabled
+ */
+//@{
+#define BP_RNG_CR_HA (1U) //!< Bit position for RNG_CR_HA.
+#define BM_RNG_CR_HA (0x00000002U) //!< Bit mask for RNG_CR_HA.
+#define BS_RNG_CR_HA (1U) //!< Bit field size in bits for RNG_CR_HA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RNG_CR_HA field.
+#define BR_RNG_CR_HA (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_HA))
+#endif
+
+//! @brief Format value for bitfield RNG_CR_HA.
+#define BF_RNG_CR_HA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_HA), uint32_t) & BM_RNG_CR_HA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HA field to a new value.
+#define BW_RNG_CR_HA(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_HA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RNG_CR, field INTM[2] (RW)
+ *
+ * Masks the triggering of an error interrupt to the interrupt controller when
+ * an OR underflow condition occurs. An OR underflow condition occurs when you
+ * read OR[RANDOUT] and SR[OREG_LVL]=0. See the Output Register (OR) description.
+ *
+ * Values:
+ * - 0 - Not masked
+ * - 1 - Masked
+ */
+//@{
+#define BP_RNG_CR_INTM (2U) //!< Bit position for RNG_CR_INTM.
+#define BM_RNG_CR_INTM (0x00000004U) //!< Bit mask for RNG_CR_INTM.
+#define BS_RNG_CR_INTM (1U) //!< Bit field size in bits for RNG_CR_INTM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RNG_CR_INTM field.
+#define BR_RNG_CR_INTM (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_INTM))
+#endif
+
+//! @brief Format value for bitfield RNG_CR_INTM.
+#define BF_RNG_CR_INTM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_INTM), uint32_t) & BM_RNG_CR_INTM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INTM field to a new value.
+#define BW_RNG_CR_INTM(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_INTM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RNG_CR, field CLRI[3] (WORZ)
+ *
+ * Clears the interrupt by resetting the error-interrupt indicator (SR[ERRI]).
+ *
+ * Values:
+ * - 0 - Do not clear the interrupt.
+ * - 1 - Clear the interrupt. When you write 1 to this field, RNGA then resets
+ * the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.
+ */
+//@{
+#define BP_RNG_CR_CLRI (3U) //!< Bit position for RNG_CR_CLRI.
+#define BM_RNG_CR_CLRI (0x00000008U) //!< Bit mask for RNG_CR_CLRI.
+#define BS_RNG_CR_CLRI (1U) //!< Bit field size in bits for RNG_CR_CLRI.
+
+//! @brief Format value for bitfield RNG_CR_CLRI.
+#define BF_RNG_CR_CLRI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_CLRI), uint32_t) & BM_RNG_CR_CLRI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLRI field to a new value.
+#define BW_RNG_CR_CLRI(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_CLRI) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RNG_CR, field SLP[4] (RW)
+ *
+ * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
+ * mode by asserting the DOZE signal.
+ *
+ * Values:
+ * - 0 - Normal mode
+ * - 1 - Sleep (low-power) mode
+ */
+//@{
+#define BP_RNG_CR_SLP (4U) //!< Bit position for RNG_CR_SLP.
+#define BM_RNG_CR_SLP (0x00000010U) //!< Bit mask for RNG_CR_SLP.
+#define BS_RNG_CR_SLP (1U) //!< Bit field size in bits for RNG_CR_SLP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RNG_CR_SLP field.
+#define BR_RNG_CR_SLP (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_SLP))
+#endif
+
+//! @brief Format value for bitfield RNG_CR_SLP.
+#define BF_RNG_CR_SLP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_SLP), uint32_t) & BM_RNG_CR_SLP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SLP field to a new value.
+#define BW_RNG_CR_SLP(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_SLP) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RNG_SR - RNGA Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RNG_SR - RNGA Status Register (RO)
+ *
+ * Reset value: 0x00010000U
+ *
+ * Indicates the status of RNGA. This register is read-only.
+ */
+typedef union _hw_rng_sr
+{
+ uint32_t U;
+ struct _hw_rng_sr_bitfields
+ {
+ uint32_t SECV : 1; //!< [0] Security Violation
+ uint32_t LRS : 1; //!< [1] Last Read Status
+ uint32_t ORU : 1; //!< [2] Output Register Underflow
+ uint32_t ERRI : 1; //!< [3] Error Interrupt
+ uint32_t SLP : 1; //!< [4] Sleep
+ uint32_t RESERVED0 : 3; //!< [7:5]
+ uint32_t OREG_LVL : 8; //!< [15:8] Output Register Level
+ uint32_t OREG_SIZE : 8; //!< [23:16] Output Register Size
+ uint32_t RESERVED1 : 8; //!< [31:24]
+ } B;
+} hw_rng_sr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RNG_SR register
+ */
+//@{
+#define HW_RNG_SR_ADDR (REGS_RNG_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RNG_SR (*(__I hw_rng_sr_t *) HW_RNG_SR_ADDR)
+#define HW_RNG_SR_RD() (HW_RNG_SR.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RNG_SR bitfields
+ */
+
+/*!
+ * @name Register RNG_SR, field SECV[0] (RO)
+ *
+ * Used only when high assurance is enabled (CR[HA]). Indicates that a security
+ * violation has occurred.This field is sticky. To clear SR[SECV], you must reset
+ * RNGA.
+ *
+ * Values:
+ * - 0 - No security violation
+ * - 1 - Security violation
+ */
+//@{
+#define BP_RNG_SR_SECV (0U) //!< Bit position for RNG_SR_SECV.
+#define BM_RNG_SR_SECV (0x00000001U) //!< Bit mask for RNG_SR_SECV.
+#define BS_RNG_SR_SECV (1U) //!< Bit field size in bits for RNG_SR_SECV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RNG_SR_SECV field.
+#define BR_RNG_SR_SECV (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_SECV))
+#endif
+//@}
+
+/*!
+ * @name Register RNG_SR, field LRS[1] (RO)
+ *
+ * Indicates whether the most recent read of OR[RANDOUT] caused an OR underflow
+ * condition, regardless of whether the error interrupt is masked (CR[INTM]). An
+ * OR underflow condition occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0.
+ * After you read this register, RNGA writes 0 to this field.
+ *
+ * Values:
+ * - 0 - No underflow
+ * - 1 - Underflow
+ */
+//@{
+#define BP_RNG_SR_LRS (1U) //!< Bit position for RNG_SR_LRS.
+#define BM_RNG_SR_LRS (0x00000002U) //!< Bit mask for RNG_SR_LRS.
+#define BS_RNG_SR_LRS (1U) //!< Bit field size in bits for RNG_SR_LRS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RNG_SR_LRS field.
+#define BR_RNG_SR_LRS (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_LRS))
+#endif
+//@}
+
+/*!
+ * @name Register RNG_SR, field ORU[2] (RO)
+ *
+ * Indicates whether an OR underflow condition has occurred since you last read
+ * this register (SR) or RNGA was reset, regardless of whether the error
+ * interrupt is masked (CR[INTM]). An OR underflow condition occurs when you read
+ * OR[RANDOUT] and SR[OREG_LVL]=0. After you read this register, RNGA writes 0 to this
+ * field.
+ *
+ * Values:
+ * - 0 - No underflow
+ * - 1 - Underflow
+ */
+//@{
+#define BP_RNG_SR_ORU (2U) //!< Bit position for RNG_SR_ORU.
+#define BM_RNG_SR_ORU (0x00000004U) //!< Bit mask for RNG_SR_ORU.
+#define BS_RNG_SR_ORU (1U) //!< Bit field size in bits for RNG_SR_ORU.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RNG_SR_ORU field.
+#define BR_RNG_SR_ORU (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_ORU))
+#endif
+//@}
+
+/*!
+ * @name Register RNG_SR, field ERRI[3] (RO)
+ *
+ * Indicates whether an OR underflow condition has occurred since you last
+ * cleared the error interrupt (CR[CLRI]) or RNGA was reset, regardless of whether the
+ * error interrupt is masked (CR[INTM]). An OR underflow condition occurs when
+ * you read OR[RANDOUT] and SR[OREG_LVL]=0. After you reset the error-interrupt
+ * indicator (via CR[CLRI]), RNGA writes 0 to this field.
+ *
+ * Values:
+ * - 0 - No underflow
+ * - 1 - Underflow
+ */
+//@{
+#define BP_RNG_SR_ERRI (3U) //!< Bit position for RNG_SR_ERRI.
+#define BM_RNG_SR_ERRI (0x00000008U) //!< Bit mask for RNG_SR_ERRI.
+#define BS_RNG_SR_ERRI (1U) //!< Bit field size in bits for RNG_SR_ERRI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RNG_SR_ERRI field.
+#define BR_RNG_SR_ERRI (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_ERRI))
+#endif
+//@}
+
+/*!
+ * @name Register RNG_SR, field SLP[4] (RO)
+ *
+ * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
+ * mode by asserting the DOZE signal.
+ *
+ * Values:
+ * - 0 - Normal mode
+ * - 1 - Sleep (low-power) mode
+ */
+//@{
+#define BP_RNG_SR_SLP (4U) //!< Bit position for RNG_SR_SLP.
+#define BM_RNG_SR_SLP (0x00000010U) //!< Bit mask for RNG_SR_SLP.
+#define BS_RNG_SR_SLP (1U) //!< Bit field size in bits for RNG_SR_SLP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RNG_SR_SLP field.
+#define BR_RNG_SR_SLP (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_SLP))
+#endif
+//@}
+
+/*!
+ * @name Register RNG_SR, field OREG_LVL[15:8] (RO)
+ *
+ * Indicates the number of random-data words that are in OR[RANDOUT], which
+ * indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL]
+ * is not 0, then the contents of a random number contained in OR[RANDOUT] are
+ * returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL].
+ *
+ * Values:
+ * - 0 - No words (empty)
+ * - 1 - One word (valid)
+ */
+//@{
+#define BP_RNG_SR_OREG_LVL (8U) //!< Bit position for RNG_SR_OREG_LVL.
+#define BM_RNG_SR_OREG_LVL (0x0000FF00U) //!< Bit mask for RNG_SR_OREG_LVL.
+#define BS_RNG_SR_OREG_LVL (8U) //!< Bit field size in bits for RNG_SR_OREG_LVL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RNG_SR_OREG_LVL field.
+#define BR_RNG_SR_OREG_LVL (HW_RNG_SR.B.OREG_LVL)
+#endif
+//@}
+
+/*!
+ * @name Register RNG_SR, field OREG_SIZE[23:16] (RO)
+ *
+ * Indicates the size of the Output (OR) register in terms of the number of
+ * 32-bit random-data words it can hold.
+ *
+ * Values:
+ * - 1 - One word (this value is fixed)
+ */
+//@{
+#define BP_RNG_SR_OREG_SIZE (16U) //!< Bit position for RNG_SR_OREG_SIZE.
+#define BM_RNG_SR_OREG_SIZE (0x00FF0000U) //!< Bit mask for RNG_SR_OREG_SIZE.
+#define BS_RNG_SR_OREG_SIZE (8U) //!< Bit field size in bits for RNG_SR_OREG_SIZE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RNG_SR_OREG_SIZE field.
+#define BR_RNG_SR_OREG_SIZE (HW_RNG_SR.B.OREG_SIZE)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RNG_ER - RNGA Entropy Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RNG_ER - RNGA Entropy Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies an entropy value that RNGA uses in addition to its ring oscillators
+ * to seed its pseudorandom algorithm. This is a write-only register; reads
+ * return all zeros.
+ */
+typedef union _hw_rng_er
+{
+ uint32_t U;
+ struct _hw_rng_er_bitfields
+ {
+ uint32_t EXT_ENT : 32; //!< [31:0] External Entropy
+ } B;
+} hw_rng_er_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RNG_ER register
+ */
+//@{
+#define HW_RNG_ER_ADDR (REGS_RNG_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RNG_ER (*(__O hw_rng_er_t *) HW_RNG_ER_ADDR)
+#define HW_RNG_ER_RD() (HW_RNG_ER.U)
+#define HW_RNG_ER_WR(v) (HW_RNG_ER.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RNG_ER bitfields
+ */
+
+/*!
+ * @name Register RNG_ER, field EXT_ENT[31:0] (WORZ)
+ *
+ * Specifies an entropy value that RNGA uses in addition to its ring oscillators
+ * to seed its pseudorandom algorithm.Specifying a value for this field is
+ * optional but recommended. You can write to this field at any time during operation.
+ */
+//@{
+#define BP_RNG_ER_EXT_ENT (0U) //!< Bit position for RNG_ER_EXT_ENT.
+#define BM_RNG_ER_EXT_ENT (0xFFFFFFFFU) //!< Bit mask for RNG_ER_EXT_ENT.
+#define BS_RNG_ER_EXT_ENT (32U) //!< Bit field size in bits for RNG_ER_EXT_ENT.
+
+//! @brief Format value for bitfield RNG_ER_EXT_ENT.
+#define BF_RNG_ER_EXT_ENT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_ER_EXT_ENT), uint32_t) & BM_RNG_ER_EXT_ENT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EXT_ENT field to a new value.
+#define BW_RNG_ER_EXT_ENT(v) (HW_RNG_ER_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RNG_OR - RNGA Output Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RNG_OR - RNGA Output Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Stores a random-data word generated by RNGA.
+ */
+typedef union _hw_rng_or
+{
+ uint32_t U;
+ struct _hw_rng_or_bitfields
+ {
+ uint32_t RANDOUT : 32; //!< [31:0] Random Output
+ } B;
+} hw_rng_or_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RNG_OR register
+ */
+//@{
+#define HW_RNG_OR_ADDR (REGS_RNG_BASE + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RNG_OR (*(__I hw_rng_or_t *) HW_RNG_OR_ADDR)
+#define HW_RNG_OR_RD() (HW_RNG_OR.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RNG_OR bitfields
+ */
+
+/*!
+ * @name Register RNG_OR, field RANDOUT[31:0] (RO)
+ *
+ * Stores a random-data word generated by RNGA. This is a read-only field.Before
+ * reading RANDOUT, be sure it is valid (SR[OREG_LVL]=1).
+ *
+ * Values:
+ * - 0 - Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is
+ * 0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error
+ * interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt
+ * request to the interrupt controller).
+ */
+//@{
+#define BP_RNG_OR_RANDOUT (0U) //!< Bit position for RNG_OR_RANDOUT.
+#define BM_RNG_OR_RANDOUT (0xFFFFFFFFU) //!< Bit mask for RNG_OR_RANDOUT.
+#define BS_RNG_OR_RANDOUT (32U) //!< Bit field size in bits for RNG_OR_RANDOUT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RNG_OR_RANDOUT field.
+#define BR_RNG_OR_RANDOUT (HW_RNG_OR.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_rng_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All RNG module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_rng
+{
+ __IO hw_rng_cr_t CR; //!< [0x0] RNGA Control Register
+ __I hw_rng_sr_t SR; //!< [0x4] RNGA Status Register
+ __O hw_rng_er_t ER; //!< [0x8] RNGA Entropy Register
+ __I hw_rng_or_t OR; //!< [0xC] RNGA Output Register
+} hw_rng_t;
+#pragma pack()
+
+//! @brief Macro to access all RNG registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_RNG</code>.
+#define HW_RNG (*(hw_rng_t *) REGS_RNG_BASE)
+#endif
+
+#endif // __HW_RNG_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_rtc.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,1828 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_RTC_REGISTERS_H__
+#define __HW_RTC_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 RTC
+ *
+ * Secure Real Time Clock
+ *
+ * Registers defined in this header file:
+ * - HW_RTC_TSR - RTC Time Seconds Register
+ * - HW_RTC_TPR - RTC Time Prescaler Register
+ * - HW_RTC_TAR - RTC Time Alarm Register
+ * - HW_RTC_TCR - RTC Time Compensation Register
+ * - HW_RTC_CR - RTC Control Register
+ * - HW_RTC_SR - RTC Status Register
+ * - HW_RTC_LR - RTC Lock Register
+ * - HW_RTC_IER - RTC Interrupt Enable Register
+ * - HW_RTC_WAR - RTC Write Access Register
+ * - HW_RTC_RAR - RTC Read Access Register
+ *
+ * - hw_rtc_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_RTC_BASE
+#define HW_RTC_INSTANCE_COUNT (1U) //!< Number of instances of the RTC module.
+#define REGS_RTC_BASE (0x4003D000U) //!< Base address for RTC.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RTC_TSR - RTC Time Seconds Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RTC_TSR - RTC Time Seconds Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_rtc_tsr
+{
+ uint32_t U;
+ struct _hw_rtc_tsr_bitfields
+ {
+ uint32_t TSR : 32; //!< [31:0] Time Seconds Register
+ } B;
+} hw_rtc_tsr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RTC_TSR register
+ */
+//@{
+#define HW_RTC_TSR_ADDR (REGS_RTC_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RTC_TSR (*(__IO hw_rtc_tsr_t *) HW_RTC_TSR_ADDR)
+#define HW_RTC_TSR_RD() (HW_RTC_TSR.U)
+#define HW_RTC_TSR_WR(v) (HW_RTC_TSR.U = (v))
+#define HW_RTC_TSR_SET(v) (HW_RTC_TSR_WR(HW_RTC_TSR_RD() | (v)))
+#define HW_RTC_TSR_CLR(v) (HW_RTC_TSR_WR(HW_RTC_TSR_RD() & ~(v)))
+#define HW_RTC_TSR_TOG(v) (HW_RTC_TSR_WR(HW_RTC_TSR_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RTC_TSR bitfields
+ */
+
+/*!
+ * @name Register RTC_TSR, field TSR[31:0] (RW)
+ *
+ * When the time counter is enabled, the TSR is read only and increments once a
+ * second provided SR[TOF] or SR[TIF] are not set. The time counter will read as
+ * zero when SR[TOF] or SR[TIF] are set. When the time counter is disabled, the
+ * TSR can be read or written. Writing to the TSR when the time counter is
+ * disabled will clear the SR[TOF] and/or the SR[TIF]. Writing to TSR with zero is
+ * supported, but not recommended because TSR will read as zero when SR[TIF] or
+ * SR[TOF] are set (indicating the time is invalid).
+ */
+//@{
+#define BP_RTC_TSR_TSR (0U) //!< Bit position for RTC_TSR_TSR.
+#define BM_RTC_TSR_TSR (0xFFFFFFFFU) //!< Bit mask for RTC_TSR_TSR.
+#define BS_RTC_TSR_TSR (32U) //!< Bit field size in bits for RTC_TSR_TSR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_TSR_TSR field.
+#define BR_RTC_TSR_TSR (HW_RTC_TSR.U)
+#endif
+
+//! @brief Format value for bitfield RTC_TSR_TSR.
+#define BF_RTC_TSR_TSR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_TSR_TSR), uint32_t) & BM_RTC_TSR_TSR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TSR field to a new value.
+#define BW_RTC_TSR_TSR(v) (HW_RTC_TSR_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RTC_TPR - RTC Time Prescaler Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RTC_TPR - RTC Time Prescaler Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_rtc_tpr
+{
+ uint32_t U;
+ struct _hw_rtc_tpr_bitfields
+ {
+ uint32_t TPR : 16; //!< [15:0] Time Prescaler Register
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_rtc_tpr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RTC_TPR register
+ */
+//@{
+#define HW_RTC_TPR_ADDR (REGS_RTC_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RTC_TPR (*(__IO hw_rtc_tpr_t *) HW_RTC_TPR_ADDR)
+#define HW_RTC_TPR_RD() (HW_RTC_TPR.U)
+#define HW_RTC_TPR_WR(v) (HW_RTC_TPR.U = (v))
+#define HW_RTC_TPR_SET(v) (HW_RTC_TPR_WR(HW_RTC_TPR_RD() | (v)))
+#define HW_RTC_TPR_CLR(v) (HW_RTC_TPR_WR(HW_RTC_TPR_RD() & ~(v)))
+#define HW_RTC_TPR_TOG(v) (HW_RTC_TPR_WR(HW_RTC_TPR_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RTC_TPR bitfields
+ */
+
+/*!
+ * @name Register RTC_TPR, field TPR[15:0] (RW)
+ *
+ * When the time counter is enabled, the TPR is read only and increments every
+ * 32.768 kHz clock cycle. The time counter will read as zero when SR[TOF] or
+ * SR[TIF] are set. When the time counter is disabled, the TPR can be read or
+ * written. The TSR[TSR] increments when bit 14 of the TPR transitions from a logic one
+ * to a logic zero.
+ */
+//@{
+#define BP_RTC_TPR_TPR (0U) //!< Bit position for RTC_TPR_TPR.
+#define BM_RTC_TPR_TPR (0x0000FFFFU) //!< Bit mask for RTC_TPR_TPR.
+#define BS_RTC_TPR_TPR (16U) //!< Bit field size in bits for RTC_TPR_TPR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_TPR_TPR field.
+#define BR_RTC_TPR_TPR (HW_RTC_TPR.B.TPR)
+#endif
+
+//! @brief Format value for bitfield RTC_TPR_TPR.
+#define BF_RTC_TPR_TPR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_TPR_TPR), uint32_t) & BM_RTC_TPR_TPR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TPR field to a new value.
+#define BW_RTC_TPR_TPR(v) (HW_RTC_TPR_WR((HW_RTC_TPR_RD() & ~BM_RTC_TPR_TPR) | BF_RTC_TPR_TPR(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RTC_TAR - RTC Time Alarm Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RTC_TAR - RTC Time Alarm Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_rtc_tar
+{
+ uint32_t U;
+ struct _hw_rtc_tar_bitfields
+ {
+ uint32_t TAR : 32; //!< [31:0] Time Alarm Register
+ } B;
+} hw_rtc_tar_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RTC_TAR register
+ */
+//@{
+#define HW_RTC_TAR_ADDR (REGS_RTC_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RTC_TAR (*(__IO hw_rtc_tar_t *) HW_RTC_TAR_ADDR)
+#define HW_RTC_TAR_RD() (HW_RTC_TAR.U)
+#define HW_RTC_TAR_WR(v) (HW_RTC_TAR.U = (v))
+#define HW_RTC_TAR_SET(v) (HW_RTC_TAR_WR(HW_RTC_TAR_RD() | (v)))
+#define HW_RTC_TAR_CLR(v) (HW_RTC_TAR_WR(HW_RTC_TAR_RD() & ~(v)))
+#define HW_RTC_TAR_TOG(v) (HW_RTC_TAR_WR(HW_RTC_TAR_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RTC_TAR bitfields
+ */
+
+/*!
+ * @name Register RTC_TAR, field TAR[31:0] (RW)
+ *
+ * When the time counter is enabled, the SR[TAF] is set whenever the TAR[TAR]
+ * equals the TSR[TSR] and the TSR[TSR] increments. Writing to the TAR clears the
+ * SR[TAF].
+ */
+//@{
+#define BP_RTC_TAR_TAR (0U) //!< Bit position for RTC_TAR_TAR.
+#define BM_RTC_TAR_TAR (0xFFFFFFFFU) //!< Bit mask for RTC_TAR_TAR.
+#define BS_RTC_TAR_TAR (32U) //!< Bit field size in bits for RTC_TAR_TAR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_TAR_TAR field.
+#define BR_RTC_TAR_TAR (HW_RTC_TAR.U)
+#endif
+
+//! @brief Format value for bitfield RTC_TAR_TAR.
+#define BF_RTC_TAR_TAR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_TAR_TAR), uint32_t) & BM_RTC_TAR_TAR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TAR field to a new value.
+#define BW_RTC_TAR_TAR(v) (HW_RTC_TAR_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RTC_TCR - RTC Time Compensation Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RTC_TCR - RTC Time Compensation Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_rtc_tcr
+{
+ uint32_t U;
+ struct _hw_rtc_tcr_bitfields
+ {
+ uint32_t TCR : 8; //!< [7:0] Time Compensation Register
+ uint32_t CIR : 8; //!< [15:8] Compensation Interval Register
+ uint32_t TCV : 8; //!< [23:16] Time Compensation Value
+ uint32_t CIC : 8; //!< [31:24] Compensation Interval Counter
+ } B;
+} hw_rtc_tcr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RTC_TCR register
+ */
+//@{
+#define HW_RTC_TCR_ADDR (REGS_RTC_BASE + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RTC_TCR (*(__IO hw_rtc_tcr_t *) HW_RTC_TCR_ADDR)
+#define HW_RTC_TCR_RD() (HW_RTC_TCR.U)
+#define HW_RTC_TCR_WR(v) (HW_RTC_TCR.U = (v))
+#define HW_RTC_TCR_SET(v) (HW_RTC_TCR_WR(HW_RTC_TCR_RD() | (v)))
+#define HW_RTC_TCR_CLR(v) (HW_RTC_TCR_WR(HW_RTC_TCR_RD() & ~(v)))
+#define HW_RTC_TCR_TOG(v) (HW_RTC_TCR_WR(HW_RTC_TCR_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RTC_TCR bitfields
+ */
+
+/*!
+ * @name Register RTC_TCR, field TCR[7:0] (RW)
+ *
+ * Configures the number of 32.768 kHz clock cycles in each second. This
+ * register is double buffered and writes do not take affect until the end of the
+ * current compensation interval.
+ *
+ * Values:
+ * - 10000000 - Time Prescaler Register overflows every 32896 clock cycles.
+ * - 11111111 - Time Prescaler Register overflows every 32769 clock cycles.
+ * - 0 - Time Prescaler Register overflows every 32768 clock cycles.
+ * - 1 - Time Prescaler Register overflows every 32767 clock cycles.
+ * - 1111111 - Time Prescaler Register overflows every 32641 clock cycles.
+ */
+//@{
+#define BP_RTC_TCR_TCR (0U) //!< Bit position for RTC_TCR_TCR.
+#define BM_RTC_TCR_TCR (0x000000FFU) //!< Bit mask for RTC_TCR_TCR.
+#define BS_RTC_TCR_TCR (8U) //!< Bit field size in bits for RTC_TCR_TCR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_TCR_TCR field.
+#define BR_RTC_TCR_TCR (HW_RTC_TCR.B.TCR)
+#endif
+
+//! @brief Format value for bitfield RTC_TCR_TCR.
+#define BF_RTC_TCR_TCR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_TCR_TCR), uint32_t) & BM_RTC_TCR_TCR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCR field to a new value.
+#define BW_RTC_TCR_TCR(v) (HW_RTC_TCR_WR((HW_RTC_TCR_RD() & ~BM_RTC_TCR_TCR) | BF_RTC_TCR_TCR(v)))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_TCR, field CIR[15:8] (RW)
+ *
+ * Configures the compensation interval in seconds from 1 to 256 to control how
+ * frequently the TCR should adjust the number of 32.768 kHz cycles in each
+ * second. The value written should be one less than the number of seconds. For
+ * example, write zero to configure for a compensation interval of one second. This
+ * register is double buffered and writes do not take affect until the end of the
+ * current compensation interval.
+ */
+//@{
+#define BP_RTC_TCR_CIR (8U) //!< Bit position for RTC_TCR_CIR.
+#define BM_RTC_TCR_CIR (0x0000FF00U) //!< Bit mask for RTC_TCR_CIR.
+#define BS_RTC_TCR_CIR (8U) //!< Bit field size in bits for RTC_TCR_CIR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_TCR_CIR field.
+#define BR_RTC_TCR_CIR (HW_RTC_TCR.B.CIR)
+#endif
+
+//! @brief Format value for bitfield RTC_TCR_CIR.
+#define BF_RTC_TCR_CIR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_TCR_CIR), uint32_t) & BM_RTC_TCR_CIR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CIR field to a new value.
+#define BW_RTC_TCR_CIR(v) (HW_RTC_TCR_WR((HW_RTC_TCR_RD() & ~BM_RTC_TCR_CIR) | BF_RTC_TCR_CIR(v)))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_TCR, field TCV[23:16] (RO)
+ *
+ * Current value used by the compensation logic for the present second interval.
+ * Updated once a second if the CIC equals 0 with the contents of the TCR field.
+ * If the CIC does not equal zero then it is loaded with zero (compensation is
+ * not enabled for that second increment).
+ */
+//@{
+#define BP_RTC_TCR_TCV (16U) //!< Bit position for RTC_TCR_TCV.
+#define BM_RTC_TCR_TCV (0x00FF0000U) //!< Bit mask for RTC_TCR_TCV.
+#define BS_RTC_TCR_TCV (8U) //!< Bit field size in bits for RTC_TCR_TCV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_TCR_TCV field.
+#define BR_RTC_TCR_TCV (HW_RTC_TCR.B.TCV)
+#endif
+//@}
+
+/*!
+ * @name Register RTC_TCR, field CIC[31:24] (RO)
+ *
+ * Current value of the compensation interval counter. If the compensation
+ * interval counter equals zero then it is loaded with the contents of the CIR. If the
+ * CIC does not equal zero then it is decremented once a second.
+ */
+//@{
+#define BP_RTC_TCR_CIC (24U) //!< Bit position for RTC_TCR_CIC.
+#define BM_RTC_TCR_CIC (0xFF000000U) //!< Bit mask for RTC_TCR_CIC.
+#define BS_RTC_TCR_CIC (8U) //!< Bit field size in bits for RTC_TCR_CIC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_TCR_CIC field.
+#define BR_RTC_TCR_CIC (HW_RTC_TCR.B.CIC)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RTC_CR - RTC Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RTC_CR - RTC Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_rtc_cr
+{
+ uint32_t U;
+ struct _hw_rtc_cr_bitfields
+ {
+ uint32_t SWR : 1; //!< [0] Software Reset
+ uint32_t WPE : 1; //!< [1] Wakeup Pin Enable
+ uint32_t SUP : 1; //!< [2] Supervisor Access
+ uint32_t UM : 1; //!< [3] Update Mode
+ uint32_t WPS : 1; //!< [4] Wakeup Pin Select
+ uint32_t RESERVED0 : 3; //!< [7:5]
+ uint32_t OSCE : 1; //!< [8] Oscillator Enable
+ uint32_t CLKO : 1; //!< [9] Clock Output
+ uint32_t SC16P : 1; //!< [10] Oscillator 16pF Load Configure
+ uint32_t SC8P : 1; //!< [11] Oscillator 8pF Load Configure
+ uint32_t SC4P : 1; //!< [12] Oscillator 4pF Load Configure
+ uint32_t SC2P : 1; //!< [13] Oscillator 2pF Load Configure
+ uint32_t RESERVED1 : 18; //!< [31:14]
+ } B;
+} hw_rtc_cr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RTC_CR register
+ */
+//@{
+#define HW_RTC_CR_ADDR (REGS_RTC_BASE + 0x10U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RTC_CR (*(__IO hw_rtc_cr_t *) HW_RTC_CR_ADDR)
+#define HW_RTC_CR_RD() (HW_RTC_CR.U)
+#define HW_RTC_CR_WR(v) (HW_RTC_CR.U = (v))
+#define HW_RTC_CR_SET(v) (HW_RTC_CR_WR(HW_RTC_CR_RD() | (v)))
+#define HW_RTC_CR_CLR(v) (HW_RTC_CR_WR(HW_RTC_CR_RD() & ~(v)))
+#define HW_RTC_CR_TOG(v) (HW_RTC_CR_WR(HW_RTC_CR_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RTC_CR bitfields
+ */
+
+/*!
+ * @name Register RTC_CR, field SWR[0] (RW)
+ *
+ * Values:
+ * - 0 - No effect.
+ * - 1 - Resets all RTC registers except for the SWR bit and the RTC_WAR and
+ * RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software
+ * explicitly clearing it.
+ */
+//@{
+#define BP_RTC_CR_SWR (0U) //!< Bit position for RTC_CR_SWR.
+#define BM_RTC_CR_SWR (0x00000001U) //!< Bit mask for RTC_CR_SWR.
+#define BS_RTC_CR_SWR (1U) //!< Bit field size in bits for RTC_CR_SWR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_CR_SWR field.
+#define BR_RTC_CR_SWR (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SWR))
+#endif
+
+//! @brief Format value for bitfield RTC_CR_SWR.
+#define BF_RTC_CR_SWR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SWR), uint32_t) & BM_RTC_CR_SWR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SWR field to a new value.
+#define BW_RTC_CR_SWR(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SWR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_CR, field WPE[1] (RW)
+ *
+ * The wakeup pin is optional and not available on all devices.
+ *
+ * Values:
+ * - 0 - Wakeup pin is disabled.
+ * - 1 - Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt
+ * asserts or the wakeup pin is turned on.
+ */
+//@{
+#define BP_RTC_CR_WPE (1U) //!< Bit position for RTC_CR_WPE.
+#define BM_RTC_CR_WPE (0x00000002U) //!< Bit mask for RTC_CR_WPE.
+#define BS_RTC_CR_WPE (1U) //!< Bit field size in bits for RTC_CR_WPE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_CR_WPE field.
+#define BR_RTC_CR_WPE (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_WPE))
+#endif
+
+//! @brief Format value for bitfield RTC_CR_WPE.
+#define BF_RTC_CR_WPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_WPE), uint32_t) & BM_RTC_CR_WPE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WPE field to a new value.
+#define BW_RTC_CR_WPE(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_WPE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_CR, field SUP[2] (RW)
+ *
+ * Values:
+ * - 0 - Non-supervisor mode write accesses are not supported and generate a bus
+ * error.
+ * - 1 - Non-supervisor mode write accesses are supported.
+ */
+//@{
+#define BP_RTC_CR_SUP (2U) //!< Bit position for RTC_CR_SUP.
+#define BM_RTC_CR_SUP (0x00000004U) //!< Bit mask for RTC_CR_SUP.
+#define BS_RTC_CR_SUP (1U) //!< Bit field size in bits for RTC_CR_SUP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_CR_SUP field.
+#define BR_RTC_CR_SUP (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SUP))
+#endif
+
+//! @brief Format value for bitfield RTC_CR_SUP.
+#define BF_RTC_CR_SUP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SUP), uint32_t) & BM_RTC_CR_SUP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SUP field to a new value.
+#define BW_RTC_CR_SUP(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SUP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_CR, field UM[3] (RW)
+ *
+ * Allows SR[TCE] to be written even when the Status Register is locked. When
+ * set, the SR[TCE] can always be written if the SR[TIF] or SR[TOF] are set or if
+ * the SR[TCE] is clear.
+ *
+ * Values:
+ * - 0 - Registers cannot be written when locked.
+ * - 1 - Registers can be written when locked under limited conditions.
+ */
+//@{
+#define BP_RTC_CR_UM (3U) //!< Bit position for RTC_CR_UM.
+#define BM_RTC_CR_UM (0x00000008U) //!< Bit mask for RTC_CR_UM.
+#define BS_RTC_CR_UM (1U) //!< Bit field size in bits for RTC_CR_UM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_CR_UM field.
+#define BR_RTC_CR_UM (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_UM))
+#endif
+
+//! @brief Format value for bitfield RTC_CR_UM.
+#define BF_RTC_CR_UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_UM), uint32_t) & BM_RTC_CR_UM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UM field to a new value.
+#define BW_RTC_CR_UM(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_UM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_CR, field WPS[4] (RW)
+ *
+ * The wakeup pin is optional and not available on all devices.
+ *
+ * Values:
+ * - 0 - Wakeup pin asserts (active low, open drain) if the RTC interrupt
+ * asserts or the wakeup pin is turned on.
+ * - 1 - Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin
+ * is turned on and the 32kHz clock is output to other peripherals.
+ */
+//@{
+#define BP_RTC_CR_WPS (4U) //!< Bit position for RTC_CR_WPS.
+#define BM_RTC_CR_WPS (0x00000010U) //!< Bit mask for RTC_CR_WPS.
+#define BS_RTC_CR_WPS (1U) //!< Bit field size in bits for RTC_CR_WPS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_CR_WPS field.
+#define BR_RTC_CR_WPS (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_WPS))
+#endif
+
+//! @brief Format value for bitfield RTC_CR_WPS.
+#define BF_RTC_CR_WPS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_WPS), uint32_t) & BM_RTC_CR_WPS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WPS field to a new value.
+#define BW_RTC_CR_WPS(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_WPS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_CR, field OSCE[8] (RW)
+ *
+ * Values:
+ * - 0 - 32.768 kHz oscillator is disabled.
+ * - 1 - 32.768 kHz oscillator is enabled. After setting this bit, wait the
+ * oscillator startup time before enabling the time counter to allow the 32.768
+ * kHz clock time to stabilize.
+ */
+//@{
+#define BP_RTC_CR_OSCE (8U) //!< Bit position for RTC_CR_OSCE.
+#define BM_RTC_CR_OSCE (0x00000100U) //!< Bit mask for RTC_CR_OSCE.
+#define BS_RTC_CR_OSCE (1U) //!< Bit field size in bits for RTC_CR_OSCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_CR_OSCE field.
+#define BR_RTC_CR_OSCE (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_OSCE))
+#endif
+
+//! @brief Format value for bitfield RTC_CR_OSCE.
+#define BF_RTC_CR_OSCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_OSCE), uint32_t) & BM_RTC_CR_OSCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OSCE field to a new value.
+#define BW_RTC_CR_OSCE(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_OSCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_CR, field CLKO[9] (RW)
+ *
+ * Values:
+ * - 0 - The 32 kHz clock is output to other peripherals.
+ * - 1 - The 32 kHz clock is not output to other peripherals.
+ */
+//@{
+#define BP_RTC_CR_CLKO (9U) //!< Bit position for RTC_CR_CLKO.
+#define BM_RTC_CR_CLKO (0x00000200U) //!< Bit mask for RTC_CR_CLKO.
+#define BS_RTC_CR_CLKO (1U) //!< Bit field size in bits for RTC_CR_CLKO.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_CR_CLKO field.
+#define BR_RTC_CR_CLKO (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_CLKO))
+#endif
+
+//! @brief Format value for bitfield RTC_CR_CLKO.
+#define BF_RTC_CR_CLKO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_CLKO), uint32_t) & BM_RTC_CR_CLKO)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLKO field to a new value.
+#define BW_RTC_CR_CLKO(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_CLKO) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_CR, field SC16P[10] (RW)
+ *
+ * Values:
+ * - 0 - Disable the load.
+ * - 1 - Enable the additional load.
+ */
+//@{
+#define BP_RTC_CR_SC16P (10U) //!< Bit position for RTC_CR_SC16P.
+#define BM_RTC_CR_SC16P (0x00000400U) //!< Bit mask for RTC_CR_SC16P.
+#define BS_RTC_CR_SC16P (1U) //!< Bit field size in bits for RTC_CR_SC16P.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_CR_SC16P field.
+#define BR_RTC_CR_SC16P (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC16P))
+#endif
+
+//! @brief Format value for bitfield RTC_CR_SC16P.
+#define BF_RTC_CR_SC16P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SC16P), uint32_t) & BM_RTC_CR_SC16P)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SC16P field to a new value.
+#define BW_RTC_CR_SC16P(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC16P) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_CR, field SC8P[11] (RW)
+ *
+ * Values:
+ * - 0 - Disable the load.
+ * - 1 - Enable the additional load.
+ */
+//@{
+#define BP_RTC_CR_SC8P (11U) //!< Bit position for RTC_CR_SC8P.
+#define BM_RTC_CR_SC8P (0x00000800U) //!< Bit mask for RTC_CR_SC8P.
+#define BS_RTC_CR_SC8P (1U) //!< Bit field size in bits for RTC_CR_SC8P.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_CR_SC8P field.
+#define BR_RTC_CR_SC8P (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC8P))
+#endif
+
+//! @brief Format value for bitfield RTC_CR_SC8P.
+#define BF_RTC_CR_SC8P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SC8P), uint32_t) & BM_RTC_CR_SC8P)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SC8P field to a new value.
+#define BW_RTC_CR_SC8P(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC8P) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_CR, field SC4P[12] (RW)
+ *
+ * Values:
+ * - 0 - Disable the load.
+ * - 1 - Enable the additional load.
+ */
+//@{
+#define BP_RTC_CR_SC4P (12U) //!< Bit position for RTC_CR_SC4P.
+#define BM_RTC_CR_SC4P (0x00001000U) //!< Bit mask for RTC_CR_SC4P.
+#define BS_RTC_CR_SC4P (1U) //!< Bit field size in bits for RTC_CR_SC4P.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_CR_SC4P field.
+#define BR_RTC_CR_SC4P (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC4P))
+#endif
+
+//! @brief Format value for bitfield RTC_CR_SC4P.
+#define BF_RTC_CR_SC4P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SC4P), uint32_t) & BM_RTC_CR_SC4P)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SC4P field to a new value.
+#define BW_RTC_CR_SC4P(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC4P) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_CR, field SC2P[13] (RW)
+ *
+ * Values:
+ * - 0 - Disable the load.
+ * - 1 - Enable the additional load.
+ */
+//@{
+#define BP_RTC_CR_SC2P (13U) //!< Bit position for RTC_CR_SC2P.
+#define BM_RTC_CR_SC2P (0x00002000U) //!< Bit mask for RTC_CR_SC2P.
+#define BS_RTC_CR_SC2P (1U) //!< Bit field size in bits for RTC_CR_SC2P.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_CR_SC2P field.
+#define BR_RTC_CR_SC2P (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC2P))
+#endif
+
+//! @brief Format value for bitfield RTC_CR_SC2P.
+#define BF_RTC_CR_SC2P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SC2P), uint32_t) & BM_RTC_CR_SC2P)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SC2P field to a new value.
+#define BW_RTC_CR_SC2P(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC2P) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RTC_SR - RTC Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RTC_SR - RTC Status Register (RW)
+ *
+ * Reset value: 0x00000001U
+ */
+typedef union _hw_rtc_sr
+{
+ uint32_t U;
+ struct _hw_rtc_sr_bitfields
+ {
+ uint32_t TIF : 1; //!< [0] Time Invalid Flag
+ uint32_t TOF : 1; //!< [1] Time Overflow Flag
+ uint32_t TAF : 1; //!< [2] Time Alarm Flag
+ uint32_t RESERVED0 : 1; //!< [3]
+ uint32_t TCE : 1; //!< [4] Time Counter Enable
+ uint32_t RESERVED1 : 27; //!< [31:5]
+ } B;
+} hw_rtc_sr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RTC_SR register
+ */
+//@{
+#define HW_RTC_SR_ADDR (REGS_RTC_BASE + 0x14U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RTC_SR (*(__IO hw_rtc_sr_t *) HW_RTC_SR_ADDR)
+#define HW_RTC_SR_RD() (HW_RTC_SR.U)
+#define HW_RTC_SR_WR(v) (HW_RTC_SR.U = (v))
+#define HW_RTC_SR_SET(v) (HW_RTC_SR_WR(HW_RTC_SR_RD() | (v)))
+#define HW_RTC_SR_CLR(v) (HW_RTC_SR_WR(HW_RTC_SR_RD() & ~(v)))
+#define HW_RTC_SR_TOG(v) (HW_RTC_SR_WR(HW_RTC_SR_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RTC_SR bitfields
+ */
+
+/*!
+ * @name Register RTC_SR, field TIF[0] (RO)
+ *
+ * The time invalid flag is set on VBAT POR or software reset. The TSR and TPR
+ * do not increment and read as zero when this bit is set. This bit is cleared by
+ * writing the TSR register when the time counter is disabled.
+ *
+ * Values:
+ * - 0 - Time is valid.
+ * - 1 - Time is invalid and time counter is read as zero.
+ */
+//@{
+#define BP_RTC_SR_TIF (0U) //!< Bit position for RTC_SR_TIF.
+#define BM_RTC_SR_TIF (0x00000001U) //!< Bit mask for RTC_SR_TIF.
+#define BS_RTC_SR_TIF (1U) //!< Bit field size in bits for RTC_SR_TIF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_SR_TIF field.
+#define BR_RTC_SR_TIF (BITBAND_ACCESS32(HW_RTC_SR_ADDR, BP_RTC_SR_TIF))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_SR, field TOF[1] (RO)
+ *
+ * Time overflow flag is set when the time counter is enabled and overflows. The
+ * TSR and TPR do not increment and read as zero when this bit is set. This bit
+ * is cleared by writing the TSR register when the time counter is disabled.
+ *
+ * Values:
+ * - 0 - Time overflow has not occurred.
+ * - 1 - Time overflow has occurred and time counter is read as zero.
+ */
+//@{
+#define BP_RTC_SR_TOF (1U) //!< Bit position for RTC_SR_TOF.
+#define BM_RTC_SR_TOF (0x00000002U) //!< Bit mask for RTC_SR_TOF.
+#define BS_RTC_SR_TOF (1U) //!< Bit field size in bits for RTC_SR_TOF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_SR_TOF field.
+#define BR_RTC_SR_TOF (BITBAND_ACCESS32(HW_RTC_SR_ADDR, BP_RTC_SR_TOF))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_SR, field TAF[2] (RO)
+ *
+ * Time alarm flag is set when the TAR[TAR] equals the TSR[TSR] and the TSR[TSR]
+ * increments. This bit is cleared by writing the TAR register.
+ *
+ * Values:
+ * - 0 - Time alarm has not occurred.
+ * - 1 - Time alarm has occurred.
+ */
+//@{
+#define BP_RTC_SR_TAF (2U) //!< Bit position for RTC_SR_TAF.
+#define BM_RTC_SR_TAF (0x00000004U) //!< Bit mask for RTC_SR_TAF.
+#define BS_RTC_SR_TAF (1U) //!< Bit field size in bits for RTC_SR_TAF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_SR_TAF field.
+#define BR_RTC_SR_TAF (BITBAND_ACCESS32(HW_RTC_SR_ADDR, BP_RTC_SR_TAF))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_SR, field TCE[4] (RW)
+ *
+ * When time counter is disabled the TSR register and TPR register are
+ * writeable, but do not increment. When time counter is enabled the TSR register and TPR
+ * register are not writeable, but increment.
+ *
+ * Values:
+ * - 0 - Time counter is disabled.
+ * - 1 - Time counter is enabled.
+ */
+//@{
+#define BP_RTC_SR_TCE (4U) //!< Bit position for RTC_SR_TCE.
+#define BM_RTC_SR_TCE (0x00000010U) //!< Bit mask for RTC_SR_TCE.
+#define BS_RTC_SR_TCE (1U) //!< Bit field size in bits for RTC_SR_TCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_SR_TCE field.
+#define BR_RTC_SR_TCE (BITBAND_ACCESS32(HW_RTC_SR_ADDR, BP_RTC_SR_TCE))
+#endif
+
+//! @brief Format value for bitfield RTC_SR_TCE.
+#define BF_RTC_SR_TCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_SR_TCE), uint32_t) & BM_RTC_SR_TCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCE field to a new value.
+#define BW_RTC_SR_TCE(v) (BITBAND_ACCESS32(HW_RTC_SR_ADDR, BP_RTC_SR_TCE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RTC_LR - RTC Lock Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RTC_LR - RTC Lock Register (RW)
+ *
+ * Reset value: 0x000000FFU
+ */
+typedef union _hw_rtc_lr
+{
+ uint32_t U;
+ struct _hw_rtc_lr_bitfields
+ {
+ uint32_t RESERVED0 : 3; //!< [2:0]
+ uint32_t TCL : 1; //!< [3] Time Compensation Lock
+ uint32_t CRL : 1; //!< [4] Control Register Lock
+ uint32_t SRL : 1; //!< [5] Status Register Lock
+ uint32_t LRL : 1; //!< [6] Lock Register Lock
+ uint32_t RESERVED1 : 25; //!< [31:7]
+ } B;
+} hw_rtc_lr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RTC_LR register
+ */
+//@{
+#define HW_RTC_LR_ADDR (REGS_RTC_BASE + 0x18U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RTC_LR (*(__IO hw_rtc_lr_t *) HW_RTC_LR_ADDR)
+#define HW_RTC_LR_RD() (HW_RTC_LR.U)
+#define HW_RTC_LR_WR(v) (HW_RTC_LR.U = (v))
+#define HW_RTC_LR_SET(v) (HW_RTC_LR_WR(HW_RTC_LR_RD() | (v)))
+#define HW_RTC_LR_CLR(v) (HW_RTC_LR_WR(HW_RTC_LR_RD() & ~(v)))
+#define HW_RTC_LR_TOG(v) (HW_RTC_LR_WR(HW_RTC_LR_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RTC_LR bitfields
+ */
+
+/*!
+ * @name Register RTC_LR, field TCL[3] (RW)
+ *
+ * After being cleared, this bit can be set only by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Time Compensation Register is locked and writes are ignored.
+ * - 1 - Time Compensation Register is not locked and writes complete as normal.
+ */
+//@{
+#define BP_RTC_LR_TCL (3U) //!< Bit position for RTC_LR_TCL.
+#define BM_RTC_LR_TCL (0x00000008U) //!< Bit mask for RTC_LR_TCL.
+#define BS_RTC_LR_TCL (1U) //!< Bit field size in bits for RTC_LR_TCL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_LR_TCL field.
+#define BR_RTC_LR_TCL (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_TCL))
+#endif
+
+//! @brief Format value for bitfield RTC_LR_TCL.
+#define BF_RTC_LR_TCL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_LR_TCL), uint32_t) & BM_RTC_LR_TCL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCL field to a new value.
+#define BW_RTC_LR_TCL(v) (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_TCL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_LR, field CRL[4] (RW)
+ *
+ * After being cleared, this bit can only be set by VBAT POR.
+ *
+ * Values:
+ * - 0 - Control Register is locked and writes are ignored.
+ * - 1 - Control Register is not locked and writes complete as normal.
+ */
+//@{
+#define BP_RTC_LR_CRL (4U) //!< Bit position for RTC_LR_CRL.
+#define BM_RTC_LR_CRL (0x00000010U) //!< Bit mask for RTC_LR_CRL.
+#define BS_RTC_LR_CRL (1U) //!< Bit field size in bits for RTC_LR_CRL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_LR_CRL field.
+#define BR_RTC_LR_CRL (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_CRL))
+#endif
+
+//! @brief Format value for bitfield RTC_LR_CRL.
+#define BF_RTC_LR_CRL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_LR_CRL), uint32_t) & BM_RTC_LR_CRL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CRL field to a new value.
+#define BW_RTC_LR_CRL(v) (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_CRL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_LR, field SRL[5] (RW)
+ *
+ * After being cleared, this bit can be set only by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Status Register is locked and writes are ignored.
+ * - 1 - Status Register is not locked and writes complete as normal.
+ */
+//@{
+#define BP_RTC_LR_SRL (5U) //!< Bit position for RTC_LR_SRL.
+#define BM_RTC_LR_SRL (0x00000020U) //!< Bit mask for RTC_LR_SRL.
+#define BS_RTC_LR_SRL (1U) //!< Bit field size in bits for RTC_LR_SRL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_LR_SRL field.
+#define BR_RTC_LR_SRL (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_SRL))
+#endif
+
+//! @brief Format value for bitfield RTC_LR_SRL.
+#define BF_RTC_LR_SRL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_LR_SRL), uint32_t) & BM_RTC_LR_SRL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SRL field to a new value.
+#define BW_RTC_LR_SRL(v) (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_SRL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_LR, field LRL[6] (RW)
+ *
+ * After being cleared, this bit can be set only by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Lock Register is locked and writes are ignored.
+ * - 1 - Lock Register is not locked and writes complete as normal.
+ */
+//@{
+#define BP_RTC_LR_LRL (6U) //!< Bit position for RTC_LR_LRL.
+#define BM_RTC_LR_LRL (0x00000040U) //!< Bit mask for RTC_LR_LRL.
+#define BS_RTC_LR_LRL (1U) //!< Bit field size in bits for RTC_LR_LRL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_LR_LRL field.
+#define BR_RTC_LR_LRL (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_LRL))
+#endif
+
+//! @brief Format value for bitfield RTC_LR_LRL.
+#define BF_RTC_LR_LRL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_LR_LRL), uint32_t) & BM_RTC_LR_LRL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LRL field to a new value.
+#define BW_RTC_LR_LRL(v) (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_LRL) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RTC_IER - RTC Interrupt Enable Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RTC_IER - RTC Interrupt Enable Register (RW)
+ *
+ * Reset value: 0x00000007U
+ */
+typedef union _hw_rtc_ier
+{
+ uint32_t U;
+ struct _hw_rtc_ier_bitfields
+ {
+ uint32_t TIIE : 1; //!< [0] Time Invalid Interrupt Enable
+ uint32_t TOIE : 1; //!< [1] Time Overflow Interrupt Enable
+ uint32_t TAIE : 1; //!< [2] Time Alarm Interrupt Enable
+ uint32_t RESERVED0 : 1; //!< [3]
+ uint32_t TSIE : 1; //!< [4] Time Seconds Interrupt Enable
+ uint32_t RESERVED1 : 2; //!< [6:5]
+ uint32_t WPON : 1; //!< [7] Wakeup Pin On
+ uint32_t RESERVED2 : 24; //!< [31:8]
+ } B;
+} hw_rtc_ier_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RTC_IER register
+ */
+//@{
+#define HW_RTC_IER_ADDR (REGS_RTC_BASE + 0x1CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RTC_IER (*(__IO hw_rtc_ier_t *) HW_RTC_IER_ADDR)
+#define HW_RTC_IER_RD() (HW_RTC_IER.U)
+#define HW_RTC_IER_WR(v) (HW_RTC_IER.U = (v))
+#define HW_RTC_IER_SET(v) (HW_RTC_IER_WR(HW_RTC_IER_RD() | (v)))
+#define HW_RTC_IER_CLR(v) (HW_RTC_IER_WR(HW_RTC_IER_RD() & ~(v)))
+#define HW_RTC_IER_TOG(v) (HW_RTC_IER_WR(HW_RTC_IER_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RTC_IER bitfields
+ */
+
+/*!
+ * @name Register RTC_IER, field TIIE[0] (RW)
+ *
+ * Values:
+ * - 0 - Time invalid flag does not generate an interrupt.
+ * - 1 - Time invalid flag does generate an interrupt.
+ */
+//@{
+#define BP_RTC_IER_TIIE (0U) //!< Bit position for RTC_IER_TIIE.
+#define BM_RTC_IER_TIIE (0x00000001U) //!< Bit mask for RTC_IER_TIIE.
+#define BS_RTC_IER_TIIE (1U) //!< Bit field size in bits for RTC_IER_TIIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_IER_TIIE field.
+#define BR_RTC_IER_TIIE (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TIIE))
+#endif
+
+//! @brief Format value for bitfield RTC_IER_TIIE.
+#define BF_RTC_IER_TIIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_IER_TIIE), uint32_t) & BM_RTC_IER_TIIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TIIE field to a new value.
+#define BW_RTC_IER_TIIE(v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TIIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_IER, field TOIE[1] (RW)
+ *
+ * Values:
+ * - 0 - Time overflow flag does not generate an interrupt.
+ * - 1 - Time overflow flag does generate an interrupt.
+ */
+//@{
+#define BP_RTC_IER_TOIE (1U) //!< Bit position for RTC_IER_TOIE.
+#define BM_RTC_IER_TOIE (0x00000002U) //!< Bit mask for RTC_IER_TOIE.
+#define BS_RTC_IER_TOIE (1U) //!< Bit field size in bits for RTC_IER_TOIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_IER_TOIE field.
+#define BR_RTC_IER_TOIE (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TOIE))
+#endif
+
+//! @brief Format value for bitfield RTC_IER_TOIE.
+#define BF_RTC_IER_TOIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_IER_TOIE), uint32_t) & BM_RTC_IER_TOIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TOIE field to a new value.
+#define BW_RTC_IER_TOIE(v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TOIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_IER, field TAIE[2] (RW)
+ *
+ * Values:
+ * - 0 - Time alarm flag does not generate an interrupt.
+ * - 1 - Time alarm flag does generate an interrupt.
+ */
+//@{
+#define BP_RTC_IER_TAIE (2U) //!< Bit position for RTC_IER_TAIE.
+#define BM_RTC_IER_TAIE (0x00000004U) //!< Bit mask for RTC_IER_TAIE.
+#define BS_RTC_IER_TAIE (1U) //!< Bit field size in bits for RTC_IER_TAIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_IER_TAIE field.
+#define BR_RTC_IER_TAIE (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TAIE))
+#endif
+
+//! @brief Format value for bitfield RTC_IER_TAIE.
+#define BF_RTC_IER_TAIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_IER_TAIE), uint32_t) & BM_RTC_IER_TAIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TAIE field to a new value.
+#define BW_RTC_IER_TAIE(v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TAIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_IER, field TSIE[4] (RW)
+ *
+ * The seconds interrupt is an edge-sensitive interrupt with a dedicated
+ * interrupt vector. It is generated once a second and requires no software overhead
+ * (there is no corresponding status flag to clear).
+ *
+ * Values:
+ * - 0 - Seconds interrupt is disabled.
+ * - 1 - Seconds interrupt is enabled.
+ */
+//@{
+#define BP_RTC_IER_TSIE (4U) //!< Bit position for RTC_IER_TSIE.
+#define BM_RTC_IER_TSIE (0x00000010U) //!< Bit mask for RTC_IER_TSIE.
+#define BS_RTC_IER_TSIE (1U) //!< Bit field size in bits for RTC_IER_TSIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_IER_TSIE field.
+#define BR_RTC_IER_TSIE (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TSIE))
+#endif
+
+//! @brief Format value for bitfield RTC_IER_TSIE.
+#define BF_RTC_IER_TSIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_IER_TSIE), uint32_t) & BM_RTC_IER_TSIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TSIE field to a new value.
+#define BW_RTC_IER_TSIE(v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TSIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_IER, field WPON[7] (RW)
+ *
+ * The wakeup pin is optional and not available on all devices. Whenever the
+ * wakeup pin is enabled and this bit is set, the wakeup pin will assert.
+ *
+ * Values:
+ * - 0 - No effect.
+ * - 1 - If the wakeup pin is enabled, then the wakeup pin will assert.
+ */
+//@{
+#define BP_RTC_IER_WPON (7U) //!< Bit position for RTC_IER_WPON.
+#define BM_RTC_IER_WPON (0x00000080U) //!< Bit mask for RTC_IER_WPON.
+#define BS_RTC_IER_WPON (1U) //!< Bit field size in bits for RTC_IER_WPON.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_IER_WPON field.
+#define BR_RTC_IER_WPON (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_WPON))
+#endif
+
+//! @brief Format value for bitfield RTC_IER_WPON.
+#define BF_RTC_IER_WPON(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_IER_WPON), uint32_t) & BM_RTC_IER_WPON)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WPON field to a new value.
+#define BW_RTC_IER_WPON(v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_WPON) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RTC_WAR - RTC Write Access Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RTC_WAR - RTC Write Access Register (RW)
+ *
+ * Reset value: 0x000000FFU
+ */
+typedef union _hw_rtc_war
+{
+ uint32_t U;
+ struct _hw_rtc_war_bitfields
+ {
+ uint32_t TSRW : 1; //!< [0] Time Seconds Register Write
+ uint32_t TPRW : 1; //!< [1] Time Prescaler Register Write
+ uint32_t TARW : 1; //!< [2] Time Alarm Register Write
+ uint32_t TCRW : 1; //!< [3] Time Compensation Register Write
+ uint32_t CRW : 1; //!< [4] Control Register Write
+ uint32_t SRW : 1; //!< [5] Status Register Write
+ uint32_t LRW : 1; //!< [6] Lock Register Write
+ uint32_t IERW : 1; //!< [7] Interrupt Enable Register Write
+ uint32_t RESERVED0 : 24; //!< [31:8]
+ } B;
+} hw_rtc_war_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RTC_WAR register
+ */
+//@{
+#define HW_RTC_WAR_ADDR (REGS_RTC_BASE + 0x800U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RTC_WAR (*(__IO hw_rtc_war_t *) HW_RTC_WAR_ADDR)
+#define HW_RTC_WAR_RD() (HW_RTC_WAR.U)
+#define HW_RTC_WAR_WR(v) (HW_RTC_WAR.U = (v))
+#define HW_RTC_WAR_SET(v) (HW_RTC_WAR_WR(HW_RTC_WAR_RD() | (v)))
+#define HW_RTC_WAR_CLR(v) (HW_RTC_WAR_WR(HW_RTC_WAR_RD() & ~(v)))
+#define HW_RTC_WAR_TOG(v) (HW_RTC_WAR_WR(HW_RTC_WAR_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RTC_WAR bitfields
+ */
+
+/*!
+ * @name Register RTC_WAR, field TSRW[0] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Writes to the Time Seconds Register are ignored.
+ * - 1 - Writes to the Time Seconds Register complete as normal.
+ */
+//@{
+#define BP_RTC_WAR_TSRW (0U) //!< Bit position for RTC_WAR_TSRW.
+#define BM_RTC_WAR_TSRW (0x00000001U) //!< Bit mask for RTC_WAR_TSRW.
+#define BS_RTC_WAR_TSRW (1U) //!< Bit field size in bits for RTC_WAR_TSRW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_WAR_TSRW field.
+#define BR_RTC_WAR_TSRW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TSRW))
+#endif
+
+//! @brief Format value for bitfield RTC_WAR_TSRW.
+#define BF_RTC_WAR_TSRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_TSRW), uint32_t) & BM_RTC_WAR_TSRW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TSRW field to a new value.
+#define BW_RTC_WAR_TSRW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TSRW) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_WAR, field TPRW[1] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Writes to the Time Prescaler Register are ignored.
+ * - 1 - Writes to the Time Prescaler Register complete as normal.
+ */
+//@{
+#define BP_RTC_WAR_TPRW (1U) //!< Bit position for RTC_WAR_TPRW.
+#define BM_RTC_WAR_TPRW (0x00000002U) //!< Bit mask for RTC_WAR_TPRW.
+#define BS_RTC_WAR_TPRW (1U) //!< Bit field size in bits for RTC_WAR_TPRW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_WAR_TPRW field.
+#define BR_RTC_WAR_TPRW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TPRW))
+#endif
+
+//! @brief Format value for bitfield RTC_WAR_TPRW.
+#define BF_RTC_WAR_TPRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_TPRW), uint32_t) & BM_RTC_WAR_TPRW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TPRW field to a new value.
+#define BW_RTC_WAR_TPRW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TPRW) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_WAR, field TARW[2] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Writes to the Time Alarm Register are ignored.
+ * - 1 - Writes to the Time Alarm Register complete as normal.
+ */
+//@{
+#define BP_RTC_WAR_TARW (2U) //!< Bit position for RTC_WAR_TARW.
+#define BM_RTC_WAR_TARW (0x00000004U) //!< Bit mask for RTC_WAR_TARW.
+#define BS_RTC_WAR_TARW (1U) //!< Bit field size in bits for RTC_WAR_TARW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_WAR_TARW field.
+#define BR_RTC_WAR_TARW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TARW))
+#endif
+
+//! @brief Format value for bitfield RTC_WAR_TARW.
+#define BF_RTC_WAR_TARW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_TARW), uint32_t) & BM_RTC_WAR_TARW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TARW field to a new value.
+#define BW_RTC_WAR_TARW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TARW) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_WAR, field TCRW[3] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Writes to the Time Compensation Register are ignored.
+ * - 1 - Writes to the Time Compensation Register complete as normal.
+ */
+//@{
+#define BP_RTC_WAR_TCRW (3U) //!< Bit position for RTC_WAR_TCRW.
+#define BM_RTC_WAR_TCRW (0x00000008U) //!< Bit mask for RTC_WAR_TCRW.
+#define BS_RTC_WAR_TCRW (1U) //!< Bit field size in bits for RTC_WAR_TCRW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_WAR_TCRW field.
+#define BR_RTC_WAR_TCRW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TCRW))
+#endif
+
+//! @brief Format value for bitfield RTC_WAR_TCRW.
+#define BF_RTC_WAR_TCRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_TCRW), uint32_t) & BM_RTC_WAR_TCRW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCRW field to a new value.
+#define BW_RTC_WAR_TCRW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TCRW) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_WAR, field CRW[4] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Writes to the Control Register are ignored.
+ * - 1 - Writes to the Control Register complete as normal.
+ */
+//@{
+#define BP_RTC_WAR_CRW (4U) //!< Bit position for RTC_WAR_CRW.
+#define BM_RTC_WAR_CRW (0x00000010U) //!< Bit mask for RTC_WAR_CRW.
+#define BS_RTC_WAR_CRW (1U) //!< Bit field size in bits for RTC_WAR_CRW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_WAR_CRW field.
+#define BR_RTC_WAR_CRW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_CRW))
+#endif
+
+//! @brief Format value for bitfield RTC_WAR_CRW.
+#define BF_RTC_WAR_CRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_CRW), uint32_t) & BM_RTC_WAR_CRW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CRW field to a new value.
+#define BW_RTC_WAR_CRW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_CRW) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_WAR, field SRW[5] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Writes to the Status Register are ignored.
+ * - 1 - Writes to the Status Register complete as normal.
+ */
+//@{
+#define BP_RTC_WAR_SRW (5U) //!< Bit position for RTC_WAR_SRW.
+#define BM_RTC_WAR_SRW (0x00000020U) //!< Bit mask for RTC_WAR_SRW.
+#define BS_RTC_WAR_SRW (1U) //!< Bit field size in bits for RTC_WAR_SRW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_WAR_SRW field.
+#define BR_RTC_WAR_SRW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_SRW))
+#endif
+
+//! @brief Format value for bitfield RTC_WAR_SRW.
+#define BF_RTC_WAR_SRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_SRW), uint32_t) & BM_RTC_WAR_SRW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SRW field to a new value.
+#define BW_RTC_WAR_SRW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_SRW) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_WAR, field LRW[6] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Writes to the Lock Register are ignored.
+ * - 1 - Writes to the Lock Register complete as normal.
+ */
+//@{
+#define BP_RTC_WAR_LRW (6U) //!< Bit position for RTC_WAR_LRW.
+#define BM_RTC_WAR_LRW (0x00000040U) //!< Bit mask for RTC_WAR_LRW.
+#define BS_RTC_WAR_LRW (1U) //!< Bit field size in bits for RTC_WAR_LRW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_WAR_LRW field.
+#define BR_RTC_WAR_LRW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_LRW))
+#endif
+
+//! @brief Format value for bitfield RTC_WAR_LRW.
+#define BF_RTC_WAR_LRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_LRW), uint32_t) & BM_RTC_WAR_LRW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LRW field to a new value.
+#define BW_RTC_WAR_LRW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_LRW) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_WAR, field IERW[7] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Writes to the Interupt Enable Register are ignored.
+ * - 1 - Writes to the Interrupt Enable Register complete as normal.
+ */
+//@{
+#define BP_RTC_WAR_IERW (7U) //!< Bit position for RTC_WAR_IERW.
+#define BM_RTC_WAR_IERW (0x00000080U) //!< Bit mask for RTC_WAR_IERW.
+#define BS_RTC_WAR_IERW (1U) //!< Bit field size in bits for RTC_WAR_IERW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_WAR_IERW field.
+#define BR_RTC_WAR_IERW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_IERW))
+#endif
+
+//! @brief Format value for bitfield RTC_WAR_IERW.
+#define BF_RTC_WAR_IERW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_IERW), uint32_t) & BM_RTC_WAR_IERW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IERW field to a new value.
+#define BW_RTC_WAR_IERW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_IERW) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_RTC_RAR - RTC Read Access Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_RTC_RAR - RTC Read Access Register (RW)
+ *
+ * Reset value: 0x000000FFU
+ */
+typedef union _hw_rtc_rar
+{
+ uint32_t U;
+ struct _hw_rtc_rar_bitfields
+ {
+ uint32_t TSRR : 1; //!< [0] Time Seconds Register Read
+ uint32_t TPRR : 1; //!< [1] Time Prescaler Register Read
+ uint32_t TARR : 1; //!< [2] Time Alarm Register Read
+ uint32_t TCRR : 1; //!< [3] Time Compensation Register Read
+ uint32_t CRR : 1; //!< [4] Control Register Read
+ uint32_t SRR : 1; //!< [5] Status Register Read
+ uint32_t LRR : 1; //!< [6] Lock Register Read
+ uint32_t IERR : 1; //!< [7] Interrupt Enable Register Read
+ uint32_t RESERVED0 : 24; //!< [31:8]
+ } B;
+} hw_rtc_rar_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire RTC_RAR register
+ */
+//@{
+#define HW_RTC_RAR_ADDR (REGS_RTC_BASE + 0x804U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_RTC_RAR (*(__IO hw_rtc_rar_t *) HW_RTC_RAR_ADDR)
+#define HW_RTC_RAR_RD() (HW_RTC_RAR.U)
+#define HW_RTC_RAR_WR(v) (HW_RTC_RAR.U = (v))
+#define HW_RTC_RAR_SET(v) (HW_RTC_RAR_WR(HW_RTC_RAR_RD() | (v)))
+#define HW_RTC_RAR_CLR(v) (HW_RTC_RAR_WR(HW_RTC_RAR_RD() & ~(v)))
+#define HW_RTC_RAR_TOG(v) (HW_RTC_RAR_WR(HW_RTC_RAR_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual RTC_RAR bitfields
+ */
+
+/*!
+ * @name Register RTC_RAR, field TSRR[0] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Reads to the Time Seconds Register are ignored.
+ * - 1 - Reads to the Time Seconds Register complete as normal.
+ */
+//@{
+#define BP_RTC_RAR_TSRR (0U) //!< Bit position for RTC_RAR_TSRR.
+#define BM_RTC_RAR_TSRR (0x00000001U) //!< Bit mask for RTC_RAR_TSRR.
+#define BS_RTC_RAR_TSRR (1U) //!< Bit field size in bits for RTC_RAR_TSRR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_RAR_TSRR field.
+#define BR_RTC_RAR_TSRR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TSRR))
+#endif
+
+//! @brief Format value for bitfield RTC_RAR_TSRR.
+#define BF_RTC_RAR_TSRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_TSRR), uint32_t) & BM_RTC_RAR_TSRR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TSRR field to a new value.
+#define BW_RTC_RAR_TSRR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TSRR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_RAR, field TPRR[1] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Reads to the Time Pprescaler Register are ignored.
+ * - 1 - Reads to the Time Prescaler Register complete as normal.
+ */
+//@{
+#define BP_RTC_RAR_TPRR (1U) //!< Bit position for RTC_RAR_TPRR.
+#define BM_RTC_RAR_TPRR (0x00000002U) //!< Bit mask for RTC_RAR_TPRR.
+#define BS_RTC_RAR_TPRR (1U) //!< Bit field size in bits for RTC_RAR_TPRR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_RAR_TPRR field.
+#define BR_RTC_RAR_TPRR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TPRR))
+#endif
+
+//! @brief Format value for bitfield RTC_RAR_TPRR.
+#define BF_RTC_RAR_TPRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_TPRR), uint32_t) & BM_RTC_RAR_TPRR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TPRR field to a new value.
+#define BW_RTC_RAR_TPRR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TPRR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_RAR, field TARR[2] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Reads to the Time Alarm Register are ignored.
+ * - 1 - Reads to the Time Alarm Register complete as normal.
+ */
+//@{
+#define BP_RTC_RAR_TARR (2U) //!< Bit position for RTC_RAR_TARR.
+#define BM_RTC_RAR_TARR (0x00000004U) //!< Bit mask for RTC_RAR_TARR.
+#define BS_RTC_RAR_TARR (1U) //!< Bit field size in bits for RTC_RAR_TARR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_RAR_TARR field.
+#define BR_RTC_RAR_TARR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TARR))
+#endif
+
+//! @brief Format value for bitfield RTC_RAR_TARR.
+#define BF_RTC_RAR_TARR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_TARR), uint32_t) & BM_RTC_RAR_TARR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TARR field to a new value.
+#define BW_RTC_RAR_TARR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TARR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_RAR, field TCRR[3] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Reads to the Time Compensation Register are ignored.
+ * - 1 - Reads to the Time Compensation Register complete as normal.
+ */
+//@{
+#define BP_RTC_RAR_TCRR (3U) //!< Bit position for RTC_RAR_TCRR.
+#define BM_RTC_RAR_TCRR (0x00000008U) //!< Bit mask for RTC_RAR_TCRR.
+#define BS_RTC_RAR_TCRR (1U) //!< Bit field size in bits for RTC_RAR_TCRR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_RAR_TCRR field.
+#define BR_RTC_RAR_TCRR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TCRR))
+#endif
+
+//! @brief Format value for bitfield RTC_RAR_TCRR.
+#define BF_RTC_RAR_TCRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_TCRR), uint32_t) & BM_RTC_RAR_TCRR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCRR field to a new value.
+#define BW_RTC_RAR_TCRR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TCRR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_RAR, field CRR[4] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Reads to the Control Register are ignored.
+ * - 1 - Reads to the Control Register complete as normal.
+ */
+//@{
+#define BP_RTC_RAR_CRR (4U) //!< Bit position for RTC_RAR_CRR.
+#define BM_RTC_RAR_CRR (0x00000010U) //!< Bit mask for RTC_RAR_CRR.
+#define BS_RTC_RAR_CRR (1U) //!< Bit field size in bits for RTC_RAR_CRR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_RAR_CRR field.
+#define BR_RTC_RAR_CRR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_CRR))
+#endif
+
+//! @brief Format value for bitfield RTC_RAR_CRR.
+#define BF_RTC_RAR_CRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_CRR), uint32_t) & BM_RTC_RAR_CRR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CRR field to a new value.
+#define BW_RTC_RAR_CRR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_CRR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_RAR, field SRR[5] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Reads to the Status Register are ignored.
+ * - 1 - Reads to the Status Register complete as normal.
+ */
+//@{
+#define BP_RTC_RAR_SRR (5U) //!< Bit position for RTC_RAR_SRR.
+#define BM_RTC_RAR_SRR (0x00000020U) //!< Bit mask for RTC_RAR_SRR.
+#define BS_RTC_RAR_SRR (1U) //!< Bit field size in bits for RTC_RAR_SRR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_RAR_SRR field.
+#define BR_RTC_RAR_SRR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_SRR))
+#endif
+
+//! @brief Format value for bitfield RTC_RAR_SRR.
+#define BF_RTC_RAR_SRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_SRR), uint32_t) & BM_RTC_RAR_SRR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SRR field to a new value.
+#define BW_RTC_RAR_SRR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_SRR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_RAR, field LRR[6] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Reads to the Lock Register are ignored.
+ * - 1 - Reads to the Lock Register complete as normal.
+ */
+//@{
+#define BP_RTC_RAR_LRR (6U) //!< Bit position for RTC_RAR_LRR.
+#define BM_RTC_RAR_LRR (0x00000040U) //!< Bit mask for RTC_RAR_LRR.
+#define BS_RTC_RAR_LRR (1U) //!< Bit field size in bits for RTC_RAR_LRR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_RAR_LRR field.
+#define BR_RTC_RAR_LRR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_LRR))
+#endif
+
+//! @brief Format value for bitfield RTC_RAR_LRR.
+#define BF_RTC_RAR_LRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_LRR), uint32_t) & BM_RTC_RAR_LRR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LRR field to a new value.
+#define BW_RTC_RAR_LRR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_LRR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register RTC_RAR, field IERR[7] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0 - Reads to the Interrupt Enable Register are ignored.
+ * - 1 - Reads to the Interrupt Enable Register complete as normal.
+ */
+//@{
+#define BP_RTC_RAR_IERR (7U) //!< Bit position for RTC_RAR_IERR.
+#define BM_RTC_RAR_IERR (0x00000080U) //!< Bit mask for RTC_RAR_IERR.
+#define BS_RTC_RAR_IERR (1U) //!< Bit field size in bits for RTC_RAR_IERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the RTC_RAR_IERR field.
+#define BR_RTC_RAR_IERR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_IERR))
+#endif
+
+//! @brief Format value for bitfield RTC_RAR_IERR.
+#define BF_RTC_RAR_IERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_IERR), uint32_t) & BM_RTC_RAR_IERR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IERR field to a new value.
+#define BW_RTC_RAR_IERR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_IERR) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_rtc_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All RTC module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_rtc
+{
+ __IO hw_rtc_tsr_t TSR; //!< [0x0] RTC Time Seconds Register
+ __IO hw_rtc_tpr_t TPR; //!< [0x4] RTC Time Prescaler Register
+ __IO hw_rtc_tar_t TAR; //!< [0x8] RTC Time Alarm Register
+ __IO hw_rtc_tcr_t TCR; //!< [0xC] RTC Time Compensation Register
+ __IO hw_rtc_cr_t CR; //!< [0x10] RTC Control Register
+ __IO hw_rtc_sr_t SR; //!< [0x14] RTC Status Register
+ __IO hw_rtc_lr_t LR; //!< [0x18] RTC Lock Register
+ __IO hw_rtc_ier_t IER; //!< [0x1C] RTC Interrupt Enable Register
+ uint8_t _reserved0[2016];
+ __IO hw_rtc_war_t WAR; //!< [0x800] RTC Write Access Register
+ __IO hw_rtc_rar_t RAR; //!< [0x804] RTC Read Access Register
+} hw_rtc_t;
+#pragma pack()
+
+//! @brief Macro to access all RTC registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_RTC</code>.
+#define HW_RTC (*(hw_rtc_t *) REGS_RTC_BASE)
+#endif
+
+#endif // __HW_RTC_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_sdhc.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,5761 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_SDHC_REGISTERS_H__
+#define __HW_SDHC_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 SDHC
+ *
+ * Secured Digital Host Controller
+ *
+ * Registers defined in this header file:
+ * - HW_SDHC_DSADDR - DMA System Address register
+ * - HW_SDHC_BLKATTR - Block Attributes register
+ * - HW_SDHC_CMDARG - Command Argument register
+ * - HW_SDHC_XFERTYP - Transfer Type register
+ * - HW_SDHC_CMDRSP0 - Command Response 0
+ * - HW_SDHC_CMDRSP1 - Command Response 1
+ * - HW_SDHC_CMDRSP2 - Command Response 2
+ * - HW_SDHC_CMDRSP3 - Command Response 3
+ * - HW_SDHC_DATPORT - Buffer Data Port register
+ * - HW_SDHC_PRSSTAT - Present State register
+ * - HW_SDHC_PROCTL - Protocol Control register
+ * - HW_SDHC_SYSCTL - System Control register
+ * - HW_SDHC_IRQSTAT - Interrupt Status register
+ * - HW_SDHC_IRQSTATEN - Interrupt Status Enable register
+ * - HW_SDHC_IRQSIGEN - Interrupt Signal Enable register
+ * - HW_SDHC_AC12ERR - Auto CMD12 Error Status Register
+ * - HW_SDHC_HTCAPBLT - Host Controller Capabilities
+ * - HW_SDHC_WML - Watermark Level Register
+ * - HW_SDHC_FEVT - Force Event register
+ * - HW_SDHC_ADMAES - ADMA Error Status register
+ * - HW_SDHC_ADSADDR - ADMA System Addressregister
+ * - HW_SDHC_VENDOR - Vendor Specific register
+ * - HW_SDHC_MMCBOOT - MMC Boot register
+ * - HW_SDHC_HOSTVER - Host Controller Version
+ *
+ * - hw_sdhc_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_SDHC_BASE
+#define HW_SDHC_INSTANCE_COUNT (1U) //!< Number of instances of the SDHC module.
+#define REGS_SDHC_BASE (0x400B1000U) //!< Base address for SDHC.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_DSADDR - DMA System Address register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_DSADDR - DMA System Address register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the physical system memory address used for DMA
+ * transfers.
+ */
+typedef union _hw_sdhc_dsaddr
+{
+ uint32_t U;
+ struct _hw_sdhc_dsaddr_bitfields
+ {
+ uint32_t RESERVED0 : 2; //!< [1:0]
+ uint32_t DSADDR : 30; //!< [31:2] DMA System Address
+ } B;
+} hw_sdhc_dsaddr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_DSADDR register
+ */
+//@{
+#define HW_SDHC_DSADDR_ADDR (REGS_SDHC_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_DSADDR (*(__IO hw_sdhc_dsaddr_t *) HW_SDHC_DSADDR_ADDR)
+#define HW_SDHC_DSADDR_RD() (HW_SDHC_DSADDR.U)
+#define HW_SDHC_DSADDR_WR(v) (HW_SDHC_DSADDR.U = (v))
+#define HW_SDHC_DSADDR_SET(v) (HW_SDHC_DSADDR_WR(HW_SDHC_DSADDR_RD() | (v)))
+#define HW_SDHC_DSADDR_CLR(v) (HW_SDHC_DSADDR_WR(HW_SDHC_DSADDR_RD() & ~(v)))
+#define HW_SDHC_DSADDR_TOG(v) (HW_SDHC_DSADDR_WR(HW_SDHC_DSADDR_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_DSADDR bitfields
+ */
+
+/*!
+ * @name Register SDHC_DSADDR, field DSADDR[31:2] (RW)
+ *
+ * Contains the 32-bit system memory address for a DMA transfer. Because the
+ * address must be word (4 bytes) align, the least 2 bits are reserved, always 0.
+ * When the SDHC stops a DMA transfer, this register points to the system address
+ * of the next contiguous data position. It can be accessed only when no
+ * transaction is executing, that is, after a transaction has stopped. Read operation
+ * during transfers may return an invalid value. The host driver shall initialize
+ * this register before starting a DMA transaction. After DMA has stopped, the
+ * system address of the next contiguous data position can be read from this register.
+ * This register is protected during a data transfer. When data lines are
+ * active, write to this register is ignored. The host driver shall wait, until
+ * PRSSTAT[DLA] is cleared, before writing to this register. The SDHC internal DMA does
+ * not support a virtual memory system. It supports only continuous physical
+ * memory access. And due to AHB burst limitations, if the burst must cross the 1 KB
+ * boundary, SDHC will automatically change SEQ burst type to NSEQ. Because this
+ * register supports dynamic address reflecting, when IRQSTAT[TC] bit is set, it
+ * automatically alters the value of internal address counter, so SW cannot
+ * change this register when IRQSTAT[TC] is set.
+ */
+//@{
+#define BP_SDHC_DSADDR_DSADDR (2U) //!< Bit position for SDHC_DSADDR_DSADDR.
+#define BM_SDHC_DSADDR_DSADDR (0xFFFFFFFCU) //!< Bit mask for SDHC_DSADDR_DSADDR.
+#define BS_SDHC_DSADDR_DSADDR (30U) //!< Bit field size in bits for SDHC_DSADDR_DSADDR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_DSADDR_DSADDR field.
+#define BR_SDHC_DSADDR_DSADDR (HW_SDHC_DSADDR.B.DSADDR)
+#endif
+
+//! @brief Format value for bitfield SDHC_DSADDR_DSADDR.
+#define BF_SDHC_DSADDR_DSADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_DSADDR_DSADDR), uint32_t) & BM_SDHC_DSADDR_DSADDR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DSADDR field to a new value.
+#define BW_SDHC_DSADDR_DSADDR(v) (HW_SDHC_DSADDR_WR((HW_SDHC_DSADDR_RD() & ~BM_SDHC_DSADDR_DSADDR) | BF_SDHC_DSADDR_DSADDR(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_BLKATTR - Block Attributes register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_BLKATTR - Block Attributes register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to configure the number of data blocks and the number
+ * of bytes in each block.
+ */
+typedef union _hw_sdhc_blkattr
+{
+ uint32_t U;
+ struct _hw_sdhc_blkattr_bitfields
+ {
+ uint32_t BLKSIZE : 13; //!< [12:0] Transfer Block Size
+ uint32_t RESERVED0 : 3; //!< [15:13]
+ uint32_t BLKCNT : 16; //!< [31:16] Blocks Count For Current Transfer
+ } B;
+} hw_sdhc_blkattr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_BLKATTR register
+ */
+//@{
+#define HW_SDHC_BLKATTR_ADDR (REGS_SDHC_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_BLKATTR (*(__IO hw_sdhc_blkattr_t *) HW_SDHC_BLKATTR_ADDR)
+#define HW_SDHC_BLKATTR_RD() (HW_SDHC_BLKATTR.U)
+#define HW_SDHC_BLKATTR_WR(v) (HW_SDHC_BLKATTR.U = (v))
+#define HW_SDHC_BLKATTR_SET(v) (HW_SDHC_BLKATTR_WR(HW_SDHC_BLKATTR_RD() | (v)))
+#define HW_SDHC_BLKATTR_CLR(v) (HW_SDHC_BLKATTR_WR(HW_SDHC_BLKATTR_RD() & ~(v)))
+#define HW_SDHC_BLKATTR_TOG(v) (HW_SDHC_BLKATTR_WR(HW_SDHC_BLKATTR_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_BLKATTR bitfields
+ */
+
+/*!
+ * @name Register SDHC_BLKATTR, field BLKSIZE[12:0] (RW)
+ *
+ * Specifies the block size for block data transfers. Values ranging from 1 byte
+ * up to the maximum buffer size can be set. It can be accessed only when no
+ * transaction is executing, that is, after a transaction has stopped. Read
+ * operations during transfers may return an invalid value, and write operations will be
+ * ignored.
+ *
+ * Values:
+ * - 0 - No data transfer.
+ * - 1 - 1 Byte
+ * - 10 - 2 Bytes
+ * - 11 - 3 Bytes
+ * - 100 - 4 Bytes
+ * - 111111111 - 511 Bytes
+ * - 1000000000 - 512 Bytes
+ * - 100000000000 - 2048 Bytes
+ * - 1000000000000 - 4096 Bytes
+ */
+//@{
+#define BP_SDHC_BLKATTR_BLKSIZE (0U) //!< Bit position for SDHC_BLKATTR_BLKSIZE.
+#define BM_SDHC_BLKATTR_BLKSIZE (0x00001FFFU) //!< Bit mask for SDHC_BLKATTR_BLKSIZE.
+#define BS_SDHC_BLKATTR_BLKSIZE (13U) //!< Bit field size in bits for SDHC_BLKATTR_BLKSIZE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_BLKATTR_BLKSIZE field.
+#define BR_SDHC_BLKATTR_BLKSIZE (HW_SDHC_BLKATTR.B.BLKSIZE)
+#endif
+
+//! @brief Format value for bitfield SDHC_BLKATTR_BLKSIZE.
+#define BF_SDHC_BLKATTR_BLKSIZE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_BLKATTR_BLKSIZE), uint32_t) & BM_SDHC_BLKATTR_BLKSIZE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BLKSIZE field to a new value.
+#define BW_SDHC_BLKATTR_BLKSIZE(v) (HW_SDHC_BLKATTR_WR((HW_SDHC_BLKATTR_RD() & ~BM_SDHC_BLKATTR_BLKSIZE) | BF_SDHC_BLKATTR_BLKSIZE(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_BLKATTR, field BLKCNT[31:16] (RW)
+ *
+ * This register is enabled when XFERTYP[BCEN] is set to 1 and is valid only for
+ * multiple block transfers. For single block transfer, this register will
+ * always read as 1. The host driver shall set this register to a value between 1 and
+ * the maximum block count. The SDHC decrements the block count after each block
+ * transfer and stops when the count reaches zero. Setting the block count to 0
+ * results in no data blocks being transferred. This register must be accessed
+ * only when no transaction is executing, that is, after transactions are stopped.
+ * During data transfer, read operations on this register may return an invalid
+ * value and write operations are ignored. When saving transfer content as a result
+ * of a suspend command, the number of blocks yet to be transferred can be
+ * determined by reading this register. The reading of this register must be applied
+ * after transfer is paused by stop at block gap operation and before sending the
+ * command marked as suspend. This is because when suspend command is sent out,
+ * SDHC will regard the current transfer as aborted and change BLKCNT back to its
+ * original value instead of keeping the dynamical indicator of remained block
+ * count. When restoring transfer content prior to issuing a resume command, the
+ * host driver shall restore the previously saved block count. Although the BLKCNT
+ * field is 0 after reset, the read of reset value is 0x1. This is because when
+ * XFERTYP[MSBSEL] is 0, indicating a single block transfer, the read value of
+ * BLKCNT is always 1.
+ *
+ * Values:
+ * - 0 - Stop count.
+ * - 1 - 1 block
+ * - 10 - 2 blocks
+ * - 1111111111111111 - 65535 blocks
+ */
+//@{
+#define BP_SDHC_BLKATTR_BLKCNT (16U) //!< Bit position for SDHC_BLKATTR_BLKCNT.
+#define BM_SDHC_BLKATTR_BLKCNT (0xFFFF0000U) //!< Bit mask for SDHC_BLKATTR_BLKCNT.
+#define BS_SDHC_BLKATTR_BLKCNT (16U) //!< Bit field size in bits for SDHC_BLKATTR_BLKCNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_BLKATTR_BLKCNT field.
+#define BR_SDHC_BLKATTR_BLKCNT (HW_SDHC_BLKATTR.B.BLKCNT)
+#endif
+
+//! @brief Format value for bitfield SDHC_BLKATTR_BLKCNT.
+#define BF_SDHC_BLKATTR_BLKCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_BLKATTR_BLKCNT), uint32_t) & BM_SDHC_BLKATTR_BLKCNT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BLKCNT field to a new value.
+#define BW_SDHC_BLKATTR_BLKCNT(v) (HW_SDHC_BLKATTR_WR((HW_SDHC_BLKATTR_RD() & ~BM_SDHC_BLKATTR_BLKCNT) | BF_SDHC_BLKATTR_BLKCNT(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_CMDARG - Command Argument register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_CMDARG - Command Argument register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the SD/MMC command argument.
+ */
+typedef union _hw_sdhc_cmdarg
+{
+ uint32_t U;
+ struct _hw_sdhc_cmdarg_bitfields
+ {
+ uint32_t CMDARG : 32; //!< [31:0] Command Argument
+ } B;
+} hw_sdhc_cmdarg_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_CMDARG register
+ */
+//@{
+#define HW_SDHC_CMDARG_ADDR (REGS_SDHC_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_CMDARG (*(__IO hw_sdhc_cmdarg_t *) HW_SDHC_CMDARG_ADDR)
+#define HW_SDHC_CMDARG_RD() (HW_SDHC_CMDARG.U)
+#define HW_SDHC_CMDARG_WR(v) (HW_SDHC_CMDARG.U = (v))
+#define HW_SDHC_CMDARG_SET(v) (HW_SDHC_CMDARG_WR(HW_SDHC_CMDARG_RD() | (v)))
+#define HW_SDHC_CMDARG_CLR(v) (HW_SDHC_CMDARG_WR(HW_SDHC_CMDARG_RD() & ~(v)))
+#define HW_SDHC_CMDARG_TOG(v) (HW_SDHC_CMDARG_WR(HW_SDHC_CMDARG_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_CMDARG bitfields
+ */
+
+/*!
+ * @name Register SDHC_CMDARG, field CMDARG[31:0] (RW)
+ *
+ * The SD/MMC command argument is specified as bits 39-8 of the command format
+ * in the SD or MMC specification. This register is write protected when
+ * PRSSTAT[CDIHB0] is set.
+ */
+//@{
+#define BP_SDHC_CMDARG_CMDARG (0U) //!< Bit position for SDHC_CMDARG_CMDARG.
+#define BM_SDHC_CMDARG_CMDARG (0xFFFFFFFFU) //!< Bit mask for SDHC_CMDARG_CMDARG.
+#define BS_SDHC_CMDARG_CMDARG (32U) //!< Bit field size in bits for SDHC_CMDARG_CMDARG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_CMDARG_CMDARG field.
+#define BR_SDHC_CMDARG_CMDARG (HW_SDHC_CMDARG.U)
+#endif
+
+//! @brief Format value for bitfield SDHC_CMDARG_CMDARG.
+#define BF_SDHC_CMDARG_CMDARG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_CMDARG_CMDARG), uint32_t) & BM_SDHC_CMDARG_CMDARG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CMDARG field to a new value.
+#define BW_SDHC_CMDARG_CMDARG(v) (HW_SDHC_CMDARG_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_XFERTYP - Transfer Type register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_XFERTYP - Transfer Type register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to control the operation of data transfers. The host
+ * driver shall set this register before issuing a command followed by a data
+ * transfer, or before issuing a resume command. To prevent data loss, the SDHC
+ * prevents writing to the bits that are involved in the data transfer of this
+ * register, when data transfer is active. These bits are DPSEL, MBSEL, DTDSEL, AC12EN,
+ * BCEN, and DMAEN. The host driver shall check PRSSTAT[CDIHB] and PRSSTAT[CIHB]
+ * before writing to this register. When PRSSTAT[CDIHB] is set, any attempt to
+ * send a command with data by writing to this register is ignored; when
+ * PRSSTAT[CIHB] bit is set, any write to this register is ignored. On sending commands with
+ * data transfer involved, it is mandatory that the block size is nonzero.
+ * Besides, block count must also be nonzero, or indicated as single block transfer
+ * (bit 5 of this register is 0 when written), or block count is disabled (bit 1 of
+ * this register is 0 when written), otherwise SDHC will ignore the sending of
+ * this command and do nothing. For write command, with all above restrictions, it
+ * is also mandatory that the write protect switch is not active (WPSPL bit of
+ * Present State Register is 1), otherwise SDHC will also ignore the command. If
+ * the commands with data transfer does not receive the response in 64 clock
+ * cycles, that is, response time-out, SDHC will regard the external device does not
+ * accept the command and abort the data transfer. In this scenario, the driver
+ * must issue the command again to retry the transfer. It is also possible that,
+ * for some reason, the card responds to the command but SDHC does not receive the
+ * response, and if it is internal DMA (either simple DMA or ADMA) read
+ * operation, the external system memory is over-written by the internal DMA with data
+ * sent back from the card. The following table shows the summary of how register
+ * settings determine the type of data transfer. Transfer Type register setting for
+ * various transfer types Multi/Single block select Block count enable Block
+ * count Function 0 Don't care Don't care Single transfer 1 0 Don't care Infinite
+ * transfer 1 1 Positive number Multiple transfer 1 1 Zero No data transfer The
+ * following table shows the relationship between XFERTYP[CICEN] and XFERTYP[CCCEN],
+ * in regards to XFERTYP[RSPTYP] as well as the name of the response type.
+ * Relationship between parameters and the name of the response type Response type
+ * (RSPTYP) Index check enable (CICEN) CRC check enable (CCCEN) Name of response
+ * type 00 0 0 No Response 01 0 1 IR2 10 0 0 R3,R4 10 1 1 R1,R5,R6 11 1 1 R1b,R5b In
+ * the SDIO specification, response type notation for R5b is not defined. R5
+ * includes R5b in the SDIO specification. But R5b is defined in this specification
+ * to specify that the SDHC will check the busy status after receiving a
+ * response. For example, usually CMD52 is used with R5, but the I/O abort command shall
+ * be used with R5b. The CRC field for R3 and R4 is expected to be all 1 bits.
+ * The CRC check shall be disabled for these response types.
+ */
+typedef union _hw_sdhc_xfertyp
+{
+ uint32_t U;
+ struct _hw_sdhc_xfertyp_bitfields
+ {
+ uint32_t DMAEN : 1; //!< [0] DMA Enable
+ uint32_t BCEN : 1; //!< [1] Block Count Enable
+ uint32_t AC12EN : 1; //!< [2] Auto CMD12 Enable
+ uint32_t RESERVED0 : 1; //!< [3]
+ uint32_t DTDSEL : 1; //!< [4] Data Transfer Direction Select
+ uint32_t MSBSEL : 1; //!< [5] Multi/Single Block Select
+ uint32_t RESERVED1 : 10; //!< [15:6]
+ uint32_t RSPTYP : 2; //!< [17:16] Response Type Select
+ uint32_t RESERVED2 : 1; //!< [18]
+ uint32_t CCCEN : 1; //!< [19] Command CRC Check Enable
+ uint32_t CICEN : 1; //!< [20] Command Index Check Enable
+ uint32_t DPSEL : 1; //!< [21] Data Present Select
+ uint32_t CMDTYP : 2; //!< [23:22] Command Type
+ uint32_t CMDINX : 6; //!< [29:24] Command Index
+ uint32_t RESERVED3 : 2; //!< [31:30]
+ } B;
+} hw_sdhc_xfertyp_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_XFERTYP register
+ */
+//@{
+#define HW_SDHC_XFERTYP_ADDR (REGS_SDHC_BASE + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_XFERTYP (*(__IO hw_sdhc_xfertyp_t *) HW_SDHC_XFERTYP_ADDR)
+#define HW_SDHC_XFERTYP_RD() (HW_SDHC_XFERTYP.U)
+#define HW_SDHC_XFERTYP_WR(v) (HW_SDHC_XFERTYP.U = (v))
+#define HW_SDHC_XFERTYP_SET(v) (HW_SDHC_XFERTYP_WR(HW_SDHC_XFERTYP_RD() | (v)))
+#define HW_SDHC_XFERTYP_CLR(v) (HW_SDHC_XFERTYP_WR(HW_SDHC_XFERTYP_RD() & ~(v)))
+#define HW_SDHC_XFERTYP_TOG(v) (HW_SDHC_XFERTYP_WR(HW_SDHC_XFERTYP_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_XFERTYP bitfields
+ */
+
+/*!
+ * @name Register SDHC_XFERTYP, field DMAEN[0] (RW)
+ *
+ * Enables DMA functionality. If this bit is set to 1, a DMA operation shall
+ * begin when the host driver sets the DPSEL bit of this register. Whether the
+ * simple DMA, or the advanced DMA, is active depends on PROCTL[DMAS].
+ *
+ * Values:
+ * - 0 - Disable
+ * - 1 - Enable
+ */
+//@{
+#define BP_SDHC_XFERTYP_DMAEN (0U) //!< Bit position for SDHC_XFERTYP_DMAEN.
+#define BM_SDHC_XFERTYP_DMAEN (0x00000001U) //!< Bit mask for SDHC_XFERTYP_DMAEN.
+#define BS_SDHC_XFERTYP_DMAEN (1U) //!< Bit field size in bits for SDHC_XFERTYP_DMAEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_XFERTYP_DMAEN field.
+#define BR_SDHC_XFERTYP_DMAEN (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DMAEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_XFERTYP_DMAEN.
+#define BF_SDHC_XFERTYP_DMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_DMAEN), uint32_t) & BM_SDHC_XFERTYP_DMAEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMAEN field to a new value.
+#define BW_SDHC_XFERTYP_DMAEN(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DMAEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_XFERTYP, field BCEN[1] (RW)
+ *
+ * Used to enable the Block Count register, which is only relevant for multiple
+ * block transfers. When this bit is 0, the internal counter for block is
+ * disabled, which is useful in executing an infinite transfer.
+ *
+ * Values:
+ * - 0 - Disable
+ * - 1 - Enable
+ */
+//@{
+#define BP_SDHC_XFERTYP_BCEN (1U) //!< Bit position for SDHC_XFERTYP_BCEN.
+#define BM_SDHC_XFERTYP_BCEN (0x00000002U) //!< Bit mask for SDHC_XFERTYP_BCEN.
+#define BS_SDHC_XFERTYP_BCEN (1U) //!< Bit field size in bits for SDHC_XFERTYP_BCEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_XFERTYP_BCEN field.
+#define BR_SDHC_XFERTYP_BCEN (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_BCEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_XFERTYP_BCEN.
+#define BF_SDHC_XFERTYP_BCEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_BCEN), uint32_t) & BM_SDHC_XFERTYP_BCEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BCEN field to a new value.
+#define BW_SDHC_XFERTYP_BCEN(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_BCEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_XFERTYP, field AC12EN[2] (RW)
+ *
+ * Multiple block transfers for memory require a CMD12 to stop the transaction.
+ * When this bit is set to 1, the SDHC will issue a CMD12 automatically when the
+ * last block transfer has completed. The host driver shall not set this bit to
+ * issue commands that do not require CMD12 to stop a multiple block data
+ * transfer. In particular, secure commands defined in File Security Specification (see
+ * reference list) do not require CMD12. In single block transfer, the SDHC will
+ * ignore this bit whether it is set or not.
+ *
+ * Values:
+ * - 0 - Disable
+ * - 1 - Enable
+ */
+//@{
+#define BP_SDHC_XFERTYP_AC12EN (2U) //!< Bit position for SDHC_XFERTYP_AC12EN.
+#define BM_SDHC_XFERTYP_AC12EN (0x00000004U) //!< Bit mask for SDHC_XFERTYP_AC12EN.
+#define BS_SDHC_XFERTYP_AC12EN (1U) //!< Bit field size in bits for SDHC_XFERTYP_AC12EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_XFERTYP_AC12EN field.
+#define BR_SDHC_XFERTYP_AC12EN (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_AC12EN))
+#endif
+
+//! @brief Format value for bitfield SDHC_XFERTYP_AC12EN.
+#define BF_SDHC_XFERTYP_AC12EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_AC12EN), uint32_t) & BM_SDHC_XFERTYP_AC12EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AC12EN field to a new value.
+#define BW_SDHC_XFERTYP_AC12EN(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_AC12EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_XFERTYP, field DTDSEL[4] (RW)
+ *
+ * Defines the direction of DAT line data transfers. The bit is set to 1 by the
+ * host driver to transfer data from the SD card to the SDHC and is set to 0 for
+ * all other commands.
+ *
+ * Values:
+ * - 0 - Write host to card.
+ * - 1 - Read card to host.
+ */
+//@{
+#define BP_SDHC_XFERTYP_DTDSEL (4U) //!< Bit position for SDHC_XFERTYP_DTDSEL.
+#define BM_SDHC_XFERTYP_DTDSEL (0x00000010U) //!< Bit mask for SDHC_XFERTYP_DTDSEL.
+#define BS_SDHC_XFERTYP_DTDSEL (1U) //!< Bit field size in bits for SDHC_XFERTYP_DTDSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_XFERTYP_DTDSEL field.
+#define BR_SDHC_XFERTYP_DTDSEL (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DTDSEL))
+#endif
+
+//! @brief Format value for bitfield SDHC_XFERTYP_DTDSEL.
+#define BF_SDHC_XFERTYP_DTDSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_DTDSEL), uint32_t) & BM_SDHC_XFERTYP_DTDSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DTDSEL field to a new value.
+#define BW_SDHC_XFERTYP_DTDSEL(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DTDSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_XFERTYP, field MSBSEL[5] (RW)
+ *
+ * Enables multiple block DAT line data transfers. For any other commands, this
+ * bit shall be set to 0. If this bit is 0, it is not necessary to set the block
+ * count register.
+ *
+ * Values:
+ * - 0 - Single block.
+ * - 1 - Multiple blocks.
+ */
+//@{
+#define BP_SDHC_XFERTYP_MSBSEL (5U) //!< Bit position for SDHC_XFERTYP_MSBSEL.
+#define BM_SDHC_XFERTYP_MSBSEL (0x00000020U) //!< Bit mask for SDHC_XFERTYP_MSBSEL.
+#define BS_SDHC_XFERTYP_MSBSEL (1U) //!< Bit field size in bits for SDHC_XFERTYP_MSBSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_XFERTYP_MSBSEL field.
+#define BR_SDHC_XFERTYP_MSBSEL (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_MSBSEL))
+#endif
+
+//! @brief Format value for bitfield SDHC_XFERTYP_MSBSEL.
+#define BF_SDHC_XFERTYP_MSBSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_MSBSEL), uint32_t) & BM_SDHC_XFERTYP_MSBSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MSBSEL field to a new value.
+#define BW_SDHC_XFERTYP_MSBSEL(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_MSBSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_XFERTYP, field RSPTYP[17:16] (RW)
+ *
+ * Values:
+ * - 00 - No response.
+ * - 01 - Response length 136.
+ * - 10 - Response length 48.
+ * - 11 - Response length 48, check busy after response.
+ */
+//@{
+#define BP_SDHC_XFERTYP_RSPTYP (16U) //!< Bit position for SDHC_XFERTYP_RSPTYP.
+#define BM_SDHC_XFERTYP_RSPTYP (0x00030000U) //!< Bit mask for SDHC_XFERTYP_RSPTYP.
+#define BS_SDHC_XFERTYP_RSPTYP (2U) //!< Bit field size in bits for SDHC_XFERTYP_RSPTYP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_XFERTYP_RSPTYP field.
+#define BR_SDHC_XFERTYP_RSPTYP (HW_SDHC_XFERTYP.B.RSPTYP)
+#endif
+
+//! @brief Format value for bitfield SDHC_XFERTYP_RSPTYP.
+#define BF_SDHC_XFERTYP_RSPTYP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_RSPTYP), uint32_t) & BM_SDHC_XFERTYP_RSPTYP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RSPTYP field to a new value.
+#define BW_SDHC_XFERTYP_RSPTYP(v) (HW_SDHC_XFERTYP_WR((HW_SDHC_XFERTYP_RD() & ~BM_SDHC_XFERTYP_RSPTYP) | BF_SDHC_XFERTYP_RSPTYP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_XFERTYP, field CCCEN[19] (RW)
+ *
+ * If this bit is set to 1, the SDHC shall check the CRC field in the response.
+ * If an error is detected, it is reported as a Command CRC Error. If this bit is
+ * set to 0, the CRC field is not checked. The number of bits checked by the CRC
+ * field value changes according to the length of the response.
+ *
+ * Values:
+ * - 0 - Disable
+ * - 1 - Enable
+ */
+//@{
+#define BP_SDHC_XFERTYP_CCCEN (19U) //!< Bit position for SDHC_XFERTYP_CCCEN.
+#define BM_SDHC_XFERTYP_CCCEN (0x00080000U) //!< Bit mask for SDHC_XFERTYP_CCCEN.
+#define BS_SDHC_XFERTYP_CCCEN (1U) //!< Bit field size in bits for SDHC_XFERTYP_CCCEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_XFERTYP_CCCEN field.
+#define BR_SDHC_XFERTYP_CCCEN (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_CCCEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_XFERTYP_CCCEN.
+#define BF_SDHC_XFERTYP_CCCEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_CCCEN), uint32_t) & BM_SDHC_XFERTYP_CCCEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCCEN field to a new value.
+#define BW_SDHC_XFERTYP_CCCEN(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_CCCEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_XFERTYP, field CICEN[20] (RW)
+ *
+ * If this bit is set to 1, the SDHC will check the index field in the response
+ * to see if it has the same value as the command index. If it is not, it is
+ * reported as a command index error. If this bit is set to 0, the index field is not
+ * checked.
+ *
+ * Values:
+ * - 0 - Disable
+ * - 1 - Enable
+ */
+//@{
+#define BP_SDHC_XFERTYP_CICEN (20U) //!< Bit position for SDHC_XFERTYP_CICEN.
+#define BM_SDHC_XFERTYP_CICEN (0x00100000U) //!< Bit mask for SDHC_XFERTYP_CICEN.
+#define BS_SDHC_XFERTYP_CICEN (1U) //!< Bit field size in bits for SDHC_XFERTYP_CICEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_XFERTYP_CICEN field.
+#define BR_SDHC_XFERTYP_CICEN (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_CICEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_XFERTYP_CICEN.
+#define BF_SDHC_XFERTYP_CICEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_CICEN), uint32_t) & BM_SDHC_XFERTYP_CICEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CICEN field to a new value.
+#define BW_SDHC_XFERTYP_CICEN(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_CICEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_XFERTYP, field DPSEL[21] (RW)
+ *
+ * This bit is set to 1 to indicate that data is present and shall be
+ * transferred using the DAT line. It is set to 0 for the following: Commands using only
+ * the CMD line, for example: CMD52. Commands with no data transfer, but using the
+ * busy signal on DAT[0] line, R1b or R5b, for example: CMD38. In resume command,
+ * this bit shall be set, and other bits in this register shall be set the same
+ * as when the transfer was initially launched. When the Write Protect switch is
+ * on, that is, the WPSPL bit is active as 0, any command with a write operation
+ * will be ignored. That is to say, when this bit is set, while the DTDSEL bit is
+ * 0, writes to the register Transfer Type are ignored.
+ *
+ * Values:
+ * - 0 - No data present.
+ * - 1 - Data present.
+ */
+//@{
+#define BP_SDHC_XFERTYP_DPSEL (21U) //!< Bit position for SDHC_XFERTYP_DPSEL.
+#define BM_SDHC_XFERTYP_DPSEL (0x00200000U) //!< Bit mask for SDHC_XFERTYP_DPSEL.
+#define BS_SDHC_XFERTYP_DPSEL (1U) //!< Bit field size in bits for SDHC_XFERTYP_DPSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_XFERTYP_DPSEL field.
+#define BR_SDHC_XFERTYP_DPSEL (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DPSEL))
+#endif
+
+//! @brief Format value for bitfield SDHC_XFERTYP_DPSEL.
+#define BF_SDHC_XFERTYP_DPSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_DPSEL), uint32_t) & BM_SDHC_XFERTYP_DPSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DPSEL field to a new value.
+#define BW_SDHC_XFERTYP_DPSEL(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DPSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_XFERTYP, field CMDTYP[23:22] (RW)
+ *
+ * There are three types of special commands: suspend, resume, and abort. These
+ * bits shall be set to 00b for all other commands. Suspend command: If the
+ * suspend command succeeds, the SDHC shall assume that the card bus has been released
+ * and that it is possible to issue the next command which uses the DAT line.
+ * Because the SDHC does not monitor the content of command response, it does not
+ * know if the suspend command succeeded or not. It is the host driver's
+ * responsibility to check the status of the suspend command and send another command
+ * marked as suspend to inform the SDHC that a suspend command was successfully
+ * issued. After the end bit of command is sent, the SDHC deasserts read wait for read
+ * transactions and stops checking busy for write transactions. In 4-bit mode,
+ * the interrupt cycle starts. If the suspend command fails, the SDHC will
+ * maintain its current state, and the host driver shall restart the transfer by setting
+ * PROCTL[CREQ]. Resume command: The host driver restarts the data transfer by
+ * restoring the registers saved before sending the suspend command and then sends
+ * the resume command. The SDHC will check for a pending busy state before
+ * starting write transfers. Abort command: If this command is set when executing a
+ * read transfer, the SDHC will stop reads to the buffer. If this command is set
+ * when executing a write transfer, the SDHC will stop driving the DAT line. After
+ * issuing the abort command, the host driver must issue a software reset (abort
+ * transaction).
+ *
+ * Values:
+ * - 00 - Normal other commands.
+ * - 01 - Suspend CMD52 for writing bus suspend in CCCR.
+ * - 10 - Resume CMD52 for writing function select in CCCR.
+ * - 11 - Abort CMD12, CMD52 for writing I/O abort in CCCR.
+ */
+//@{
+#define BP_SDHC_XFERTYP_CMDTYP (22U) //!< Bit position for SDHC_XFERTYP_CMDTYP.
+#define BM_SDHC_XFERTYP_CMDTYP (0x00C00000U) //!< Bit mask for SDHC_XFERTYP_CMDTYP.
+#define BS_SDHC_XFERTYP_CMDTYP (2U) //!< Bit field size in bits for SDHC_XFERTYP_CMDTYP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_XFERTYP_CMDTYP field.
+#define BR_SDHC_XFERTYP_CMDTYP (HW_SDHC_XFERTYP.B.CMDTYP)
+#endif
+
+//! @brief Format value for bitfield SDHC_XFERTYP_CMDTYP.
+#define BF_SDHC_XFERTYP_CMDTYP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_CMDTYP), uint32_t) & BM_SDHC_XFERTYP_CMDTYP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CMDTYP field to a new value.
+#define BW_SDHC_XFERTYP_CMDTYP(v) (HW_SDHC_XFERTYP_WR((HW_SDHC_XFERTYP_RD() & ~BM_SDHC_XFERTYP_CMDTYP) | BF_SDHC_XFERTYP_CMDTYP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_XFERTYP, field CMDINX[29:24] (RW)
+ *
+ * These bits shall be set to the command number that is specified in bits 45-40
+ * of the command-format in the SD Memory Card Physical Layer Specification and
+ * SDIO Card Specification.
+ */
+//@{
+#define BP_SDHC_XFERTYP_CMDINX (24U) //!< Bit position for SDHC_XFERTYP_CMDINX.
+#define BM_SDHC_XFERTYP_CMDINX (0x3F000000U) //!< Bit mask for SDHC_XFERTYP_CMDINX.
+#define BS_SDHC_XFERTYP_CMDINX (6U) //!< Bit field size in bits for SDHC_XFERTYP_CMDINX.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_XFERTYP_CMDINX field.
+#define BR_SDHC_XFERTYP_CMDINX (HW_SDHC_XFERTYP.B.CMDINX)
+#endif
+
+//! @brief Format value for bitfield SDHC_XFERTYP_CMDINX.
+#define BF_SDHC_XFERTYP_CMDINX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_CMDINX), uint32_t) & BM_SDHC_XFERTYP_CMDINX)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CMDINX field to a new value.
+#define BW_SDHC_XFERTYP_CMDINX(v) (HW_SDHC_XFERTYP_WR((HW_SDHC_XFERTYP_RD() & ~BM_SDHC_XFERTYP_CMDINX) | BF_SDHC_XFERTYP_CMDINX(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_CMDRSP0 - Command Response 0
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_CMDRSP0 - Command Response 0 (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to store part 0 of the response bits from the card.
+ */
+typedef union _hw_sdhc_cmdrsp0
+{
+ uint32_t U;
+ struct _hw_sdhc_cmdrsp0_bitfields
+ {
+ uint32_t CMDRSP0 : 32; //!< [31:0] Command Response 0
+ } B;
+} hw_sdhc_cmdrsp0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_CMDRSP0 register
+ */
+//@{
+#define HW_SDHC_CMDRSP0_ADDR (REGS_SDHC_BASE + 0x10U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_CMDRSP0 (*(__I hw_sdhc_cmdrsp0_t *) HW_SDHC_CMDRSP0_ADDR)
+#define HW_SDHC_CMDRSP0_RD() (HW_SDHC_CMDRSP0.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_CMDRSP0 bitfields
+ */
+
+/*!
+ * @name Register SDHC_CMDRSP0, field CMDRSP0[31:0] (RO)
+ */
+//@{
+#define BP_SDHC_CMDRSP0_CMDRSP0 (0U) //!< Bit position for SDHC_CMDRSP0_CMDRSP0.
+#define BM_SDHC_CMDRSP0_CMDRSP0 (0xFFFFFFFFU) //!< Bit mask for SDHC_CMDRSP0_CMDRSP0.
+#define BS_SDHC_CMDRSP0_CMDRSP0 (32U) //!< Bit field size in bits for SDHC_CMDRSP0_CMDRSP0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_CMDRSP0_CMDRSP0 field.
+#define BR_SDHC_CMDRSP0_CMDRSP0 (HW_SDHC_CMDRSP0.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_CMDRSP1 - Command Response 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_CMDRSP1 - Command Response 1 (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to store part 1 of the response bits from the card.
+ */
+typedef union _hw_sdhc_cmdrsp1
+{
+ uint32_t U;
+ struct _hw_sdhc_cmdrsp1_bitfields
+ {
+ uint32_t CMDRSP1 : 32; //!< [31:0] Command Response 1
+ } B;
+} hw_sdhc_cmdrsp1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_CMDRSP1 register
+ */
+//@{
+#define HW_SDHC_CMDRSP1_ADDR (REGS_SDHC_BASE + 0x14U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_CMDRSP1 (*(__I hw_sdhc_cmdrsp1_t *) HW_SDHC_CMDRSP1_ADDR)
+#define HW_SDHC_CMDRSP1_RD() (HW_SDHC_CMDRSP1.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_CMDRSP1 bitfields
+ */
+
+/*!
+ * @name Register SDHC_CMDRSP1, field CMDRSP1[31:0] (RO)
+ */
+//@{
+#define BP_SDHC_CMDRSP1_CMDRSP1 (0U) //!< Bit position for SDHC_CMDRSP1_CMDRSP1.
+#define BM_SDHC_CMDRSP1_CMDRSP1 (0xFFFFFFFFU) //!< Bit mask for SDHC_CMDRSP1_CMDRSP1.
+#define BS_SDHC_CMDRSP1_CMDRSP1 (32U) //!< Bit field size in bits for SDHC_CMDRSP1_CMDRSP1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_CMDRSP1_CMDRSP1 field.
+#define BR_SDHC_CMDRSP1_CMDRSP1 (HW_SDHC_CMDRSP1.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_CMDRSP2 - Command Response 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_CMDRSP2 - Command Response 2 (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to store part 2 of the response bits from the card.
+ */
+typedef union _hw_sdhc_cmdrsp2
+{
+ uint32_t U;
+ struct _hw_sdhc_cmdrsp2_bitfields
+ {
+ uint32_t CMDRSP2 : 32; //!< [31:0] Command Response 2
+ } B;
+} hw_sdhc_cmdrsp2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_CMDRSP2 register
+ */
+//@{
+#define HW_SDHC_CMDRSP2_ADDR (REGS_SDHC_BASE + 0x18U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_CMDRSP2 (*(__I hw_sdhc_cmdrsp2_t *) HW_SDHC_CMDRSP2_ADDR)
+#define HW_SDHC_CMDRSP2_RD() (HW_SDHC_CMDRSP2.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_CMDRSP2 bitfields
+ */
+
+/*!
+ * @name Register SDHC_CMDRSP2, field CMDRSP2[31:0] (RO)
+ */
+//@{
+#define BP_SDHC_CMDRSP2_CMDRSP2 (0U) //!< Bit position for SDHC_CMDRSP2_CMDRSP2.
+#define BM_SDHC_CMDRSP2_CMDRSP2 (0xFFFFFFFFU) //!< Bit mask for SDHC_CMDRSP2_CMDRSP2.
+#define BS_SDHC_CMDRSP2_CMDRSP2 (32U) //!< Bit field size in bits for SDHC_CMDRSP2_CMDRSP2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_CMDRSP2_CMDRSP2 field.
+#define BR_SDHC_CMDRSP2_CMDRSP2 (HW_SDHC_CMDRSP2.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_CMDRSP3 - Command Response 3
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_CMDRSP3 - Command Response 3 (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to store part 3 of the response bits from the card. The
+ * following table describes the mapping of command responses from the SD bus to
+ * command response registers for each response type. In the table, R[ ] refers
+ * to a bit range within the response data as transmitted on the SD bus. Response
+ * bit definition for each response type Response type Meaning of response
+ * Response field Response register R1,R1b (normal response) Card status R[39:8]
+ * CMDRSP0 R1b (Auto CMD12 response) Card status for auto CMD12 R[39:8] CMDRSP3 R2
+ * (CID, CSD register) CID/CSD register [127:8] R[127:8] {CMDRSP3[23:0], CMDRSP2,
+ * CMDRSP1, CMDRSP0} R3 (OCR register) OCR register for memory R[39:8] CMDRSP0 R4
+ * (OCR register) OCR register for I/O etc. R[39:8] CMDRSP0 R5, R5b SDIO response
+ * R[39:8] CMDRSP0 R6 (Publish RCA) New published RCA[31:16] and card
+ * status[15:0] R[39:9] CMDRSP0 This table shows that most responses with a length of 48
+ * (R[47:0]) have 32-bit of the response data (R[39:8]) stored in the CMDRSP0
+ * register. Responses of type R1b (auto CMD12 responses) have response data bits
+ * (R[39:8]) stored in the CMDRSP3 register. Responses with length 136 (R[135:0]) have
+ * 120-bit of the response data (R[127:8]) stored in the CMDRSP0, 1, 2, and 3
+ * registers. To be able to read the response status efficiently, the SDHC stores
+ * only a part of the response data in the command response registers. This
+ * enables the host driver to efficiently read 32-bit of response data in one read
+ * cycle on a 32-bit bus system. Parts of the response, the index field and the CRC,
+ * are checked by the SDHC, as specified by XFERTYP[CICEN] and XFERTYP[CCCEN],
+ * and generate an error interrupt if any error is detected. The bit range for the
+ * CRC check depends on the response length. If the response length is 48, the
+ * SDHC will check R[47:1], and if the response length is 136 the SDHC will check
+ * R[119:1]. Because the SDHC may have a multiple block data transfer executing
+ * concurrently with a CMD_wo_DAT command, the SDHC stores the auto CMD12 response
+ * in the CMDRSP3 register. The CMD_wo_DAT response is stored in CMDRSP0. This
+ * allows the SDHC to avoid overwriting the Auto CMD12 response with the CMD_wo_DAT
+ * and vice versa. When the SDHC modifies part of the command response
+ * registers, as shown in the table above, it preserves the unmodified bits.
+ */
+typedef union _hw_sdhc_cmdrsp3
+{
+ uint32_t U;
+ struct _hw_sdhc_cmdrsp3_bitfields
+ {
+ uint32_t CMDRSP3 : 32; //!< [31:0] Command Response 3
+ } B;
+} hw_sdhc_cmdrsp3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_CMDRSP3 register
+ */
+//@{
+#define HW_SDHC_CMDRSP3_ADDR (REGS_SDHC_BASE + 0x1CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_CMDRSP3 (*(__I hw_sdhc_cmdrsp3_t *) HW_SDHC_CMDRSP3_ADDR)
+#define HW_SDHC_CMDRSP3_RD() (HW_SDHC_CMDRSP3.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_CMDRSP3 bitfields
+ */
+
+/*!
+ * @name Register SDHC_CMDRSP3, field CMDRSP3[31:0] (RO)
+ */
+//@{
+#define BP_SDHC_CMDRSP3_CMDRSP3 (0U) //!< Bit position for SDHC_CMDRSP3_CMDRSP3.
+#define BM_SDHC_CMDRSP3_CMDRSP3 (0xFFFFFFFFU) //!< Bit mask for SDHC_CMDRSP3_CMDRSP3.
+#define BS_SDHC_CMDRSP3_CMDRSP3 (32U) //!< Bit field size in bits for SDHC_CMDRSP3_CMDRSP3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_CMDRSP3_CMDRSP3 field.
+#define BR_SDHC_CMDRSP3_CMDRSP3 (HW_SDHC_CMDRSP3.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_DATPORT - Buffer Data Port register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_DATPORT - Buffer Data Port register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This is a 32-bit data port register used to access the internal buffer and it
+ * cannot be updated in Idle mode.
+ */
+typedef union _hw_sdhc_datport
+{
+ uint32_t U;
+ struct _hw_sdhc_datport_bitfields
+ {
+ uint32_t DATCONT : 32; //!< [31:0] Data Content
+ } B;
+} hw_sdhc_datport_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_DATPORT register
+ */
+//@{
+#define HW_SDHC_DATPORT_ADDR (REGS_SDHC_BASE + 0x20U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_DATPORT (*(__IO hw_sdhc_datport_t *) HW_SDHC_DATPORT_ADDR)
+#define HW_SDHC_DATPORT_RD() (HW_SDHC_DATPORT.U)
+#define HW_SDHC_DATPORT_WR(v) (HW_SDHC_DATPORT.U = (v))
+#define HW_SDHC_DATPORT_SET(v) (HW_SDHC_DATPORT_WR(HW_SDHC_DATPORT_RD() | (v)))
+#define HW_SDHC_DATPORT_CLR(v) (HW_SDHC_DATPORT_WR(HW_SDHC_DATPORT_RD() & ~(v)))
+#define HW_SDHC_DATPORT_TOG(v) (HW_SDHC_DATPORT_WR(HW_SDHC_DATPORT_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_DATPORT bitfields
+ */
+
+/*!
+ * @name Register SDHC_DATPORT, field DATCONT[31:0] (RW)
+ *
+ * The Buffer Data Port register is for 32-bit data access by the CPU or the
+ * external DMA. When the internal DMA is enabled, any write to this register is
+ * ignored, and any read from this register will always yield 0s.
+ */
+//@{
+#define BP_SDHC_DATPORT_DATCONT (0U) //!< Bit position for SDHC_DATPORT_DATCONT.
+#define BM_SDHC_DATPORT_DATCONT (0xFFFFFFFFU) //!< Bit mask for SDHC_DATPORT_DATCONT.
+#define BS_SDHC_DATPORT_DATCONT (32U) //!< Bit field size in bits for SDHC_DATPORT_DATCONT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_DATPORT_DATCONT field.
+#define BR_SDHC_DATPORT_DATCONT (HW_SDHC_DATPORT.U)
+#endif
+
+//! @brief Format value for bitfield SDHC_DATPORT_DATCONT.
+#define BF_SDHC_DATPORT_DATCONT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_DATPORT_DATCONT), uint32_t) & BM_SDHC_DATPORT_DATCONT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATCONT field to a new value.
+#define BW_SDHC_DATPORT_DATCONT(v) (HW_SDHC_DATPORT_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_PRSSTAT - Present State register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_PRSSTAT - Present State register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The host driver can get status of the SDHC from this 32-bit read-only
+ * register. The host driver can issue CMD0, CMD12, CMD13 (for memory) and CMD52 (for
+ * SDIO) when the DAT lines are busy during a data transfer. These commands can be
+ * issued when Command Inhibit (CIHB) is set to zero. Other commands shall be
+ * issued when Command Inhibit (CDIHB) is set to zero. Possible changes to the SD
+ * Physical Specification may add other commands to this list in the future.
+ */
+typedef union _hw_sdhc_prsstat
+{
+ uint32_t U;
+ struct _hw_sdhc_prsstat_bitfields
+ {
+ uint32_t CIHB : 1; //!< [0] Command Inhibit (CMD)
+ uint32_t CDIHB : 1; //!< [1] Command Inhibit (DAT)
+ uint32_t DLA : 1; //!< [2] Data Line Active
+ uint32_t SDSTB : 1; //!< [3] SD Clock Stable
+ uint32_t IPGOFF : 1; //!< [4] Bus Clock Gated Off Internally
+ uint32_t HCKOFF : 1; //!< [5] System Clock Gated Off Internally
+ uint32_t PEROFF : 1; //!< [6] SDHC clock Gated Off Internally
+ uint32_t SDOFF : 1; //!< [7] SD Clock Gated Off Internally
+ uint32_t WTA : 1; //!< [8] Write Transfer Active
+ uint32_t RTA : 1; //!< [9] Read Transfer Active
+ uint32_t BWEN : 1; //!< [10] Buffer Write Enable
+ uint32_t BREN : 1; //!< [11] Buffer Read Enable
+ uint32_t RESERVED0 : 4; //!< [15:12]
+ uint32_t CINS : 1; //!< [16] Card Inserted
+ uint32_t RESERVED1 : 6; //!< [22:17]
+ uint32_t CLSL : 1; //!< [23] CMD Line Signal Level
+ uint32_t DLSL : 8; //!< [31:24] DAT Line Signal Level
+ } B;
+} hw_sdhc_prsstat_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_PRSSTAT register
+ */
+//@{
+#define HW_SDHC_PRSSTAT_ADDR (REGS_SDHC_BASE + 0x24U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_PRSSTAT (*(__I hw_sdhc_prsstat_t *) HW_SDHC_PRSSTAT_ADDR)
+#define HW_SDHC_PRSSTAT_RD() (HW_SDHC_PRSSTAT.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_PRSSTAT bitfields
+ */
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CIHB[0] (RO)
+ *
+ * If this status bit is 0, it indicates that the CMD line is not in use and the
+ * SDHC can issue a SD/MMC Command using the CMD line. This bit is set also
+ * immediately after the Transfer Type register is written. This bit is cleared when
+ * the command response is received. Even if the CDIHB bit is set to 1, Commands
+ * using only the CMD line can be issued if this bit is 0. Changing from 1 to 0
+ * generates a command complete interrupt in the interrupt status register. If the
+ * SDHC cannot issue the command because of a command conflict error (see
+ * command CRC error) or because of a command not issued by auto CMD12 error, this bit
+ * will remain 1 and the command complete is not set. The status of issuing an
+ * auto CMD12 does not show on this bit.
+ *
+ * Values:
+ * - 0 - Can issue command using only CMD line.
+ * - 1 - Cannot issue command.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_CIHB (0U) //!< Bit position for SDHC_PRSSTAT_CIHB.
+#define BM_SDHC_PRSSTAT_CIHB (0x00000001U) //!< Bit mask for SDHC_PRSSTAT_CIHB.
+#define BS_SDHC_PRSSTAT_CIHB (1U) //!< Bit field size in bits for SDHC_PRSSTAT_CIHB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_CIHB field.
+#define BR_SDHC_PRSSTAT_CIHB (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_CIHB))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CDIHB[1] (RO)
+ *
+ * This status bit is generated if either the DLA or the RTA is set to 1. If
+ * this bit is 0, it indicates that the SDHC can issue the next SD/MMC Command.
+ * Commands with a busy signal belong to CDIHB, for example, R1b, R5b type. Except in
+ * the case when the command busy is finished, changing from 1 to 0 generates a
+ * transfer complete interrupt in the Interrupt Status register. The SD host
+ * driver can save registers for a suspend transaction after this bit has changed
+ * from 1 to 0.
+ *
+ * Values:
+ * - 0 - Can issue command which uses the DAT line.
+ * - 1 - Cannot issue command which uses the DAT line.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_CDIHB (1U) //!< Bit position for SDHC_PRSSTAT_CDIHB.
+#define BM_SDHC_PRSSTAT_CDIHB (0x00000002U) //!< Bit mask for SDHC_PRSSTAT_CDIHB.
+#define BS_SDHC_PRSSTAT_CDIHB (1U) //!< Bit field size in bits for SDHC_PRSSTAT_CDIHB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_CDIHB field.
+#define BR_SDHC_PRSSTAT_CDIHB (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_CDIHB))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PRSSTAT, field DLA[2] (RO)
+ *
+ * Indicates whether one of the DAT lines on the SD bus is in use. In the case
+ * of read transactions: This status indicates whether a read transfer is
+ * executing on the SD bus. Changes in this value from 1 to 0, between data blocks,
+ * generates a block gap event interrupt in the Interrupt Status register. This bit
+ * will be set in either of the following cases: After the end bit of the read
+ * command. When writing a 1 to PROCTL[CREQ] to restart a read transfer. This bit
+ * will be cleared in either of the following cases: When the end bit of the last
+ * data block is sent from the SD bus to the SDHC. When the read wait state is
+ * stopped by a suspend command and the DAT2 line is released. The SDHC will wait at
+ * the next block gap by driving read wait at the start of the interrupt cycle.
+ * If the read wait signal is already driven (data buffer cannot receive data),
+ * the SDHC can wait for a current block gap by continuing to drive the read wait
+ * signal. It is necessary to support read wait to use the suspend / resume
+ * function. This bit will remain 1 during read wait. In the case of write
+ * transactions: This status indicates that a write transfer is executing on the SD bus.
+ * Changes in this value from 1 to 0 generate a transfer complete interrupt in the
+ * interrupt status register. This bit will be set in either of the following
+ * cases: After the end bit of the write command. When writing to 1 to PROCTL[CREQ] to
+ * continue a write transfer. This bit will be cleared in either of the
+ * following cases: When the SD card releases write busy of the last data block, the SDHC
+ * will also detect if the output is not busy. If the SD card does not drive the
+ * busy signal after the CRC status is received, the SDHC shall assume the card
+ * drive "Not busy". When the SD card releases write busy, prior to waiting for
+ * write transfer, and as a result of a stop at block gap request. In the case of
+ * command with busy pending: This status indicates that a busy state follows the
+ * command and the data line is in use. This bit will be cleared when the DAT0
+ * line is released.
+ *
+ * Values:
+ * - 0 - DAT line inactive.
+ * - 1 - DAT line active.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_DLA (2U) //!< Bit position for SDHC_PRSSTAT_DLA.
+#define BM_SDHC_PRSSTAT_DLA (0x00000004U) //!< Bit mask for SDHC_PRSSTAT_DLA.
+#define BS_SDHC_PRSSTAT_DLA (1U) //!< Bit field size in bits for SDHC_PRSSTAT_DLA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_DLA field.
+#define BR_SDHC_PRSSTAT_DLA (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_DLA))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PRSSTAT, field SDSTB[3] (RO)
+ *
+ * Indicates that the internal card clock is stable. This bit is for the host
+ * driver to poll clock status when changing the clock frequency. It is recommended
+ * to clear SYSCTL[SDCLKEN] to remove glitch on the card clock when the
+ * frequency is changing.
+ *
+ * Values:
+ * - 0 - Clock is changing frequency and not stable.
+ * - 1 - Clock is stable.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_SDSTB (3U) //!< Bit position for SDHC_PRSSTAT_SDSTB.
+#define BM_SDHC_PRSSTAT_SDSTB (0x00000008U) //!< Bit mask for SDHC_PRSSTAT_SDSTB.
+#define BS_SDHC_PRSSTAT_SDSTB (1U) //!< Bit field size in bits for SDHC_PRSSTAT_SDSTB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_SDSTB field.
+#define BR_SDHC_PRSSTAT_SDSTB (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_SDSTB))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PRSSTAT, field IPGOFF[4] (RO)
+ *
+ * Indicates that the bus clock is internally gated off. This bit is for the
+ * host driver to debug.
+ *
+ * Values:
+ * - 0 - Bus clock is active.
+ * - 1 - Bus clock is gated off.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_IPGOFF (4U) //!< Bit position for SDHC_PRSSTAT_IPGOFF.
+#define BM_SDHC_PRSSTAT_IPGOFF (0x00000010U) //!< Bit mask for SDHC_PRSSTAT_IPGOFF.
+#define BS_SDHC_PRSSTAT_IPGOFF (1U) //!< Bit field size in bits for SDHC_PRSSTAT_IPGOFF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_IPGOFF field.
+#define BR_SDHC_PRSSTAT_IPGOFF (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_IPGOFF))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PRSSTAT, field HCKOFF[5] (RO)
+ *
+ * Indicates that the system clock is internally gated off. This bit is for the
+ * host driver to debug during a data transfer.
+ *
+ * Values:
+ * - 0 - System clock is active.
+ * - 1 - System clock is gated off.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_HCKOFF (5U) //!< Bit position for SDHC_PRSSTAT_HCKOFF.
+#define BM_SDHC_PRSSTAT_HCKOFF (0x00000020U) //!< Bit mask for SDHC_PRSSTAT_HCKOFF.
+#define BS_SDHC_PRSSTAT_HCKOFF (1U) //!< Bit field size in bits for SDHC_PRSSTAT_HCKOFF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_HCKOFF field.
+#define BR_SDHC_PRSSTAT_HCKOFF (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_HCKOFF))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PRSSTAT, field PEROFF[6] (RO)
+ *
+ * Indicates that the is internally gated off. This bit is for the host driver
+ * to debug transaction on the SD bus. When INITA bit is set, SDHC sending 80
+ * clock cycles to the card, SDCLKEN must be 1 to enable the output card clock,
+ * otherwise the will never be gate off, so and will be always active. SDHC clock SDHC
+ * clock SDHC clock bus clock
+ *
+ * Values:
+ * - 0 - SDHC clock is active.
+ * - 1 - SDHC clock is gated off.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_PEROFF (6U) //!< Bit position for SDHC_PRSSTAT_PEROFF.
+#define BM_SDHC_PRSSTAT_PEROFF (0x00000040U) //!< Bit mask for SDHC_PRSSTAT_PEROFF.
+#define BS_SDHC_PRSSTAT_PEROFF (1U) //!< Bit field size in bits for SDHC_PRSSTAT_PEROFF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_PEROFF field.
+#define BR_SDHC_PRSSTAT_PEROFF (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_PEROFF))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PRSSTAT, field SDOFF[7] (RO)
+ *
+ * Indicates that the SD clock is internally gated off, because of buffer
+ * over/under-run or read pause without read wait assertion, or the driver has cleared
+ * SYSCTL[SDCLKEN] to stop the SD clock. This bit is for the host driver to debug
+ * data transaction on the SD bus.
+ *
+ * Values:
+ * - 0 - SD clock is active.
+ * - 1 - SD clock is gated off.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_SDOFF (7U) //!< Bit position for SDHC_PRSSTAT_SDOFF.
+#define BM_SDHC_PRSSTAT_SDOFF (0x00000080U) //!< Bit mask for SDHC_PRSSTAT_SDOFF.
+#define BS_SDHC_PRSSTAT_SDOFF (1U) //!< Bit field size in bits for SDHC_PRSSTAT_SDOFF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_SDOFF field.
+#define BR_SDHC_PRSSTAT_SDOFF (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_SDOFF))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PRSSTAT, field WTA[8] (RO)
+ *
+ * Indicates that a write transfer is active. If this bit is 0, it means no
+ * valid write data exists in the SDHC. This bit is set in either of the following
+ * cases: After the end bit of the write command. When writing 1 to PROCTL[CREQ] to
+ * restart a write transfer. This bit is cleared in either of the following
+ * cases: After getting the CRC status of the last data block as specified by the
+ * transfer count (single and multiple). After getting the CRC status of any block
+ * where data transmission is about to be stopped by a stop at block gap request.
+ * During a write transaction, a block gap event interrupt is generated when this
+ * bit is changed to 0, as result of the stop at block gap request being set.
+ * This status is useful for the host driver in determining when to issue commands
+ * during write busy state.
+ *
+ * Values:
+ * - 0 - No valid data.
+ * - 1 - Transferring data.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_WTA (8U) //!< Bit position for SDHC_PRSSTAT_WTA.
+#define BM_SDHC_PRSSTAT_WTA (0x00000100U) //!< Bit mask for SDHC_PRSSTAT_WTA.
+#define BS_SDHC_PRSSTAT_WTA (1U) //!< Bit field size in bits for SDHC_PRSSTAT_WTA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_WTA field.
+#define BR_SDHC_PRSSTAT_WTA (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_WTA))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PRSSTAT, field RTA[9] (RO)
+ *
+ * Used for detecting completion of a read transfer. This bit is set for either
+ * of the following conditions: After the end bit of the read command. When
+ * writing a 1 to PROCTL[CREQ] to restart a read transfer. A transfer complete
+ * interrupt is generated when this bit changes to 0. This bit is cleared for either of
+ * the following conditions: When the last data block as specified by block
+ * length is transferred to the system, that is, all data are read away from SDHC
+ * internal buffer. When all valid data blocks have been transferred from SDHC
+ * internal buffer to the system and no current block transfers are being sent as a
+ * result of the stop at block gap request being set to 1.
+ *
+ * Values:
+ * - 0 - No valid data.
+ * - 1 - Transferring data.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_RTA (9U) //!< Bit position for SDHC_PRSSTAT_RTA.
+#define BM_SDHC_PRSSTAT_RTA (0x00000200U) //!< Bit mask for SDHC_PRSSTAT_RTA.
+#define BS_SDHC_PRSSTAT_RTA (1U) //!< Bit field size in bits for SDHC_PRSSTAT_RTA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_RTA field.
+#define BR_SDHC_PRSSTAT_RTA (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_RTA))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PRSSTAT, field BWEN[10] (RO)
+ *
+ * Used for non-DMA write transfers. The SDHC can implement multiple buffers to
+ * transfer data efficiently. This read-only flag indicates whether space is
+ * available for write data. If this bit is 1, valid data greater than the watermark
+ * level can be written to the buffer. This read-only flag indicates whether
+ * space is available for write data.
+ *
+ * Values:
+ * - 0 - Write disable, the buffer can hold valid data less than the write
+ * watermark level.
+ * - 1 - Write enable, the buffer can hold valid data greater than the write
+ * watermark level.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_BWEN (10U) //!< Bit position for SDHC_PRSSTAT_BWEN.
+#define BM_SDHC_PRSSTAT_BWEN (0x00000400U) //!< Bit mask for SDHC_PRSSTAT_BWEN.
+#define BS_SDHC_PRSSTAT_BWEN (1U) //!< Bit field size in bits for SDHC_PRSSTAT_BWEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_BWEN field.
+#define BR_SDHC_PRSSTAT_BWEN (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_BWEN))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PRSSTAT, field BREN[11] (RO)
+ *
+ * Used for non-DMA read transfers. The SDHC may implement multiple buffers to
+ * transfer data efficiently. This read-only flag indicates that valid data exists
+ * in the host side buffer. If this bit is high, valid data greater than the
+ * watermark level exist in the buffer. This read-only flag indicates that valid
+ * data exists in the host side buffer.
+ *
+ * Values:
+ * - 0 - Read disable, valid data less than the watermark level exist in the
+ * buffer.
+ * - 1 - Read enable, valid data greater than the watermark level exist in the
+ * buffer.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_BREN (11U) //!< Bit position for SDHC_PRSSTAT_BREN.
+#define BM_SDHC_PRSSTAT_BREN (0x00000800U) //!< Bit mask for SDHC_PRSSTAT_BREN.
+#define BS_SDHC_PRSSTAT_BREN (1U) //!< Bit field size in bits for SDHC_PRSSTAT_BREN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_BREN field.
+#define BR_SDHC_PRSSTAT_BREN (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_BREN))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CINS[16] (RO)
+ *
+ * Indicates whether a card has been inserted. The SDHC debounces this signal so
+ * that the host driver will not need to wait for it to stabilize. Changing from
+ * a 0 to 1 generates a card insertion interrupt in the Interrupt Status
+ * register. Changing from a 1 to 0 generates a card removal interrupt in the Interrupt
+ * Status register. A write to the force event register does not effect this bit.
+ * SYSCTL[RSTA] does not effect this bit. A software reset does not effect this
+ * bit.
+ *
+ * Values:
+ * - 0 - Power on reset or no card.
+ * - 1 - Card inserted.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_CINS (16U) //!< Bit position for SDHC_PRSSTAT_CINS.
+#define BM_SDHC_PRSSTAT_CINS (0x00010000U) //!< Bit mask for SDHC_PRSSTAT_CINS.
+#define BS_SDHC_PRSSTAT_CINS (1U) //!< Bit field size in bits for SDHC_PRSSTAT_CINS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_CINS field.
+#define BR_SDHC_PRSSTAT_CINS (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_CINS))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CLSL[23] (RO)
+ *
+ * Used to check the CMD line level to recover from errors, and for debugging.
+ * The reset value is effected by the external pullup/pulldown resistor, by
+ * default, the read value of this bit after reset is 1b, when the command line is
+ * pulled up.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_CLSL (23U) //!< Bit position for SDHC_PRSSTAT_CLSL.
+#define BM_SDHC_PRSSTAT_CLSL (0x00800000U) //!< Bit mask for SDHC_PRSSTAT_CLSL.
+#define BS_SDHC_PRSSTAT_CLSL (1U) //!< Bit field size in bits for SDHC_PRSSTAT_CLSL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_CLSL field.
+#define BR_SDHC_PRSSTAT_CLSL (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_CLSL))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PRSSTAT, field DLSL[31:24] (RO)
+ *
+ * Used to check the DAT line level to recover from errors, and for debugging.
+ * This is especially useful in detecting the busy signal level from DAT[0]. The
+ * reset value is effected by the external pullup/pulldown resistors. By default,
+ * the read value of this field after reset is 8'b11110111, when DAT[3] is pulled
+ * down and the other lines are pulled up.
+ */
+//@{
+#define BP_SDHC_PRSSTAT_DLSL (24U) //!< Bit position for SDHC_PRSSTAT_DLSL.
+#define BM_SDHC_PRSSTAT_DLSL (0xFF000000U) //!< Bit mask for SDHC_PRSSTAT_DLSL.
+#define BS_SDHC_PRSSTAT_DLSL (8U) //!< Bit field size in bits for SDHC_PRSSTAT_DLSL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PRSSTAT_DLSL field.
+#define BR_SDHC_PRSSTAT_DLSL (HW_SDHC_PRSSTAT.B.DLSL)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_PROCTL - Protocol Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_PROCTL - Protocol Control register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * There are three cases to restart the transfer after stop at the block gap.
+ * Which case is appropriate depends on whether the SDHC issues a suspend command
+ * or the SD card accepts the suspend command: If the host driver does not issue a
+ * suspend command, the continue request shall be used to restart the transfer.
+ * If the host driver issues a suspend command and the SD card accepts it, a
+ * resume command shall be used to restart the transfer. If the host driver issues a
+ * suspend command and the SD card does not accept it, the continue request shall
+ * be used to restart the transfer. Any time stop at block gap request stops the
+ * data transfer, the host driver shall wait for a transfer complete (in the
+ * interrupt status register), before attempting to restart the transfer. When
+ * restarting the data transfer by continue request, the host driver shall clear the
+ * stop at block gap request before or simultaneously.
+ */
+typedef union _hw_sdhc_proctl
+{
+ uint32_t U;
+ struct _hw_sdhc_proctl_bitfields
+ {
+ uint32_t LCTL : 1; //!< [0] LED Control
+ uint32_t DTW : 2; //!< [2:1] Data Transfer Width
+ uint32_t D3CD : 1; //!< [3] DAT3 As Card Detection Pin
+ uint32_t EMODE : 2; //!< [5:4] Endian Mode
+ uint32_t CDTL : 1; //!< [6] Card Detect Test Level
+ uint32_t CDSS : 1; //!< [7] Card Detect Signal Selection
+ uint32_t DMAS : 2; //!< [9:8] DMA Select
+ uint32_t RESERVED0 : 6; //!< [15:10]
+ uint32_t SABGREQ : 1; //!< [16] Stop At Block Gap Request
+ uint32_t CREQ : 1; //!< [17] Continue Request
+ uint32_t RWCTL : 1; //!< [18] Read Wait Control
+ uint32_t IABG : 1; //!< [19] Interrupt At Block Gap
+ uint32_t RESERVED1 : 4; //!< [23:20]
+ uint32_t WECINT : 1; //!< [24] Wakeup Event Enable On Card Interrupt
+ uint32_t WECINS : 1; //!< [25] Wakeup Event Enable On SD Card
+ //! Insertion
+ uint32_t WECRM : 1; //!< [26] Wakeup Event Enable On SD Card Removal
+ uint32_t RESERVED2 : 5; //!< [31:27]
+ } B;
+} hw_sdhc_proctl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_PROCTL register
+ */
+//@{
+#define HW_SDHC_PROCTL_ADDR (REGS_SDHC_BASE + 0x28U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_PROCTL (*(__IO hw_sdhc_proctl_t *) HW_SDHC_PROCTL_ADDR)
+#define HW_SDHC_PROCTL_RD() (HW_SDHC_PROCTL.U)
+#define HW_SDHC_PROCTL_WR(v) (HW_SDHC_PROCTL.U = (v))
+#define HW_SDHC_PROCTL_SET(v) (HW_SDHC_PROCTL_WR(HW_SDHC_PROCTL_RD() | (v)))
+#define HW_SDHC_PROCTL_CLR(v) (HW_SDHC_PROCTL_WR(HW_SDHC_PROCTL_RD() & ~(v)))
+#define HW_SDHC_PROCTL_TOG(v) (HW_SDHC_PROCTL_WR(HW_SDHC_PROCTL_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_PROCTL bitfields
+ */
+
+/*!
+ * @name Register SDHC_PROCTL, field LCTL[0] (RW)
+ *
+ * This bit, fully controlled by the host driver, is used to caution the user
+ * not to remove the card while the card is being accessed. If the software is
+ * going to issue multiple SD commands, this bit can be set during all these
+ * transactions. It is not necessary to change for each transaction. When the software
+ * issues multiple SD commands, setting the bit once before the first command is
+ * sufficient: it is not necessary to reset the bit between commands.
+ *
+ * Values:
+ * - 0 - LED off.
+ * - 1 - LED on.
+ */
+//@{
+#define BP_SDHC_PROCTL_LCTL (0U) //!< Bit position for SDHC_PROCTL_LCTL.
+#define BM_SDHC_PROCTL_LCTL (0x00000001U) //!< Bit mask for SDHC_PROCTL_LCTL.
+#define BS_SDHC_PROCTL_LCTL (1U) //!< Bit field size in bits for SDHC_PROCTL_LCTL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PROCTL_LCTL field.
+#define BR_SDHC_PROCTL_LCTL (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_LCTL))
+#endif
+
+//! @brief Format value for bitfield SDHC_PROCTL_LCTL.
+#define BF_SDHC_PROCTL_LCTL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_LCTL), uint32_t) & BM_SDHC_PROCTL_LCTL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LCTL field to a new value.
+#define BW_SDHC_PROCTL_LCTL(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_LCTL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PROCTL, field DTW[2:1] (RW)
+ *
+ * Selects the data width of the SD bus for a data transfer. The host driver
+ * shall set it to match the data width of the card. Possible data transfer width is
+ * 1-bit, 4-bits or 8-bits.
+ *
+ * Values:
+ * - 00 - 1-bit mode
+ * - 01 - 4-bit mode
+ * - 10 - 8-bit mode
+ * - 11 - Reserved
+ */
+//@{
+#define BP_SDHC_PROCTL_DTW (1U) //!< Bit position for SDHC_PROCTL_DTW.
+#define BM_SDHC_PROCTL_DTW (0x00000006U) //!< Bit mask for SDHC_PROCTL_DTW.
+#define BS_SDHC_PROCTL_DTW (2U) //!< Bit field size in bits for SDHC_PROCTL_DTW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PROCTL_DTW field.
+#define BR_SDHC_PROCTL_DTW (HW_SDHC_PROCTL.B.DTW)
+#endif
+
+//! @brief Format value for bitfield SDHC_PROCTL_DTW.
+#define BF_SDHC_PROCTL_DTW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_DTW), uint32_t) & BM_SDHC_PROCTL_DTW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DTW field to a new value.
+#define BW_SDHC_PROCTL_DTW(v) (HW_SDHC_PROCTL_WR((HW_SDHC_PROCTL_RD() & ~BM_SDHC_PROCTL_DTW) | BF_SDHC_PROCTL_DTW(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PROCTL, field D3CD[3] (RW)
+ *
+ * If this bit is set, DAT3 should be pulled down to act as a card detection
+ * pin. Be cautious when using this feature, because DAT3 is also a chip-select for
+ * the SPI mode. A pulldown on this pin and CMD0 may set the card into the SPI
+ * mode, which the SDHC does not support. Note: Keep this bit set if SDIO interrupt
+ * is used.
+ *
+ * Values:
+ * - 0 - DAT3 does not monitor card Insertion.
+ * - 1 - DAT3 as card detection pin.
+ */
+//@{
+#define BP_SDHC_PROCTL_D3CD (3U) //!< Bit position for SDHC_PROCTL_D3CD.
+#define BM_SDHC_PROCTL_D3CD (0x00000008U) //!< Bit mask for SDHC_PROCTL_D3CD.
+#define BS_SDHC_PROCTL_D3CD (1U) //!< Bit field size in bits for SDHC_PROCTL_D3CD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PROCTL_D3CD field.
+#define BR_SDHC_PROCTL_D3CD (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_D3CD))
+#endif
+
+//! @brief Format value for bitfield SDHC_PROCTL_D3CD.
+#define BF_SDHC_PROCTL_D3CD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_D3CD), uint32_t) & BM_SDHC_PROCTL_D3CD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the D3CD field to a new value.
+#define BW_SDHC_PROCTL_D3CD(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_D3CD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PROCTL, field EMODE[5:4] (RW)
+ *
+ * The SDHC supports all four endian modes in data transfer.
+ *
+ * Values:
+ * - 00 - Big endian mode
+ * - 01 - Half word big endian mode
+ * - 10 - Little endian mode
+ * - 11 - Reserved
+ */
+//@{
+#define BP_SDHC_PROCTL_EMODE (4U) //!< Bit position for SDHC_PROCTL_EMODE.
+#define BM_SDHC_PROCTL_EMODE (0x00000030U) //!< Bit mask for SDHC_PROCTL_EMODE.
+#define BS_SDHC_PROCTL_EMODE (2U) //!< Bit field size in bits for SDHC_PROCTL_EMODE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PROCTL_EMODE field.
+#define BR_SDHC_PROCTL_EMODE (HW_SDHC_PROCTL.B.EMODE)
+#endif
+
+//! @brief Format value for bitfield SDHC_PROCTL_EMODE.
+#define BF_SDHC_PROCTL_EMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_EMODE), uint32_t) & BM_SDHC_PROCTL_EMODE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EMODE field to a new value.
+#define BW_SDHC_PROCTL_EMODE(v) (HW_SDHC_PROCTL_WR((HW_SDHC_PROCTL_RD() & ~BM_SDHC_PROCTL_EMODE) | BF_SDHC_PROCTL_EMODE(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PROCTL, field CDTL[6] (RW)
+ *
+ * Enabled while the CDSS is set to 1 and it indicates card insertion.
+ *
+ * Values:
+ * - 0 - Card detect test level is 0, no card inserted.
+ * - 1 - Card detect test level is 1, card inserted.
+ */
+//@{
+#define BP_SDHC_PROCTL_CDTL (6U) //!< Bit position for SDHC_PROCTL_CDTL.
+#define BM_SDHC_PROCTL_CDTL (0x00000040U) //!< Bit mask for SDHC_PROCTL_CDTL.
+#define BS_SDHC_PROCTL_CDTL (1U) //!< Bit field size in bits for SDHC_PROCTL_CDTL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PROCTL_CDTL field.
+#define BR_SDHC_PROCTL_CDTL (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CDTL))
+#endif
+
+//! @brief Format value for bitfield SDHC_PROCTL_CDTL.
+#define BF_SDHC_PROCTL_CDTL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_CDTL), uint32_t) & BM_SDHC_PROCTL_CDTL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CDTL field to a new value.
+#define BW_SDHC_PROCTL_CDTL(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CDTL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PROCTL, field CDSS[7] (RW)
+ *
+ * Selects the source for the card detection.
+ *
+ * Values:
+ * - 0 - Card detection level is selected for normal purpose.
+ * - 1 - Card detection test level is selected for test purpose.
+ */
+//@{
+#define BP_SDHC_PROCTL_CDSS (7U) //!< Bit position for SDHC_PROCTL_CDSS.
+#define BM_SDHC_PROCTL_CDSS (0x00000080U) //!< Bit mask for SDHC_PROCTL_CDSS.
+#define BS_SDHC_PROCTL_CDSS (1U) //!< Bit field size in bits for SDHC_PROCTL_CDSS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PROCTL_CDSS field.
+#define BR_SDHC_PROCTL_CDSS (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CDSS))
+#endif
+
+//! @brief Format value for bitfield SDHC_PROCTL_CDSS.
+#define BF_SDHC_PROCTL_CDSS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_CDSS), uint32_t) & BM_SDHC_PROCTL_CDSS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CDSS field to a new value.
+#define BW_SDHC_PROCTL_CDSS(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CDSS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PROCTL, field DMAS[9:8] (RW)
+ *
+ * This field is valid while DMA (SDMA or ADMA) is enabled and selects the DMA
+ * operation.
+ *
+ * Values:
+ * - 00 - No DMA or simple DMA is selected.
+ * - 01 - ADMA1 is selected.
+ * - 10 - ADMA2 is selected.
+ * - 11 - Reserved
+ */
+//@{
+#define BP_SDHC_PROCTL_DMAS (8U) //!< Bit position for SDHC_PROCTL_DMAS.
+#define BM_SDHC_PROCTL_DMAS (0x00000300U) //!< Bit mask for SDHC_PROCTL_DMAS.
+#define BS_SDHC_PROCTL_DMAS (2U) //!< Bit field size in bits for SDHC_PROCTL_DMAS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PROCTL_DMAS field.
+#define BR_SDHC_PROCTL_DMAS (HW_SDHC_PROCTL.B.DMAS)
+#endif
+
+//! @brief Format value for bitfield SDHC_PROCTL_DMAS.
+#define BF_SDHC_PROCTL_DMAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_DMAS), uint32_t) & BM_SDHC_PROCTL_DMAS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMAS field to a new value.
+#define BW_SDHC_PROCTL_DMAS(v) (HW_SDHC_PROCTL_WR((HW_SDHC_PROCTL_RD() & ~BM_SDHC_PROCTL_DMAS) | BF_SDHC_PROCTL_DMAS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PROCTL, field SABGREQ[16] (RW)
+ *
+ * Used to stop executing a transaction at the next block gap for both DMA and
+ * non-DMA transfers. Until the IRQSTATEN[TCSEN] is set to 1, indicating a
+ * transfer completion, the host driver shall leave this bit set to 1. Clearing both
+ * PROCTL[SABGREQ] and PROCTL[CREQ] does not cause the transaction to restart. Read
+ * Wait is used to stop the read transaction at the block gap. The SDHC will
+ * honor the PROCTL[SABGREQ] for write transfers, but for read transfers it requires
+ * that SDIO card support read wait. Therefore, the host driver shall not set
+ * this bit during read transfers unless the SDIO card supports read wait and has
+ * set PROCTL[RWCTL] to 1, otherwise the SDHC will stop the SD bus clock to pause
+ * the read operation during block gap. In the case of write transfers in which
+ * the host driver writes data to the data port register, the host driver shall set
+ * this bit after all block data is written. If this bit is set to 1, the host
+ * driver shall not write data to the Data Port register after a block is sent.
+ * Once this bit is set, the host driver shall not clear this bit before
+ * IRQSTATEN[TCSEN] is set, otherwise the SDHC's behavior is undefined. This bit effects
+ * PRSSTAT[RTA], PRSSTAT[WTA], and PRSSTAT[CDIHB].
+ *
+ * Values:
+ * - 0 - Transfer
+ * - 1 - Stop
+ */
+//@{
+#define BP_SDHC_PROCTL_SABGREQ (16U) //!< Bit position for SDHC_PROCTL_SABGREQ.
+#define BM_SDHC_PROCTL_SABGREQ (0x00010000U) //!< Bit mask for SDHC_PROCTL_SABGREQ.
+#define BS_SDHC_PROCTL_SABGREQ (1U) //!< Bit field size in bits for SDHC_PROCTL_SABGREQ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PROCTL_SABGREQ field.
+#define BR_SDHC_PROCTL_SABGREQ (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_SABGREQ))
+#endif
+
+//! @brief Format value for bitfield SDHC_PROCTL_SABGREQ.
+#define BF_SDHC_PROCTL_SABGREQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_SABGREQ), uint32_t) & BM_SDHC_PROCTL_SABGREQ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SABGREQ field to a new value.
+#define BW_SDHC_PROCTL_SABGREQ(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_SABGREQ) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PROCTL, field CREQ[17] (RW)
+ *
+ * Used to restart a transaction which was stopped using the PROCTL[SABGREQ].
+ * When a suspend operation is not accepted by the card, it is also by setting this
+ * bit to restart the paused transfer. To cancel stop at the block gap, set
+ * PROCTL[SABGREQ] to 0 and set this bit to 1 to restart the transfer. The SDHC
+ * automatically clears this bit, therefore it is not necessary for the host driver to
+ * set this bit to 0. If both PROCTL[SABGREQ] and this bit are 1, the continue
+ * request is ignored.
+ *
+ * Values:
+ * - 0 - No effect.
+ * - 1 - Restart
+ */
+//@{
+#define BP_SDHC_PROCTL_CREQ (17U) //!< Bit position for SDHC_PROCTL_CREQ.
+#define BM_SDHC_PROCTL_CREQ (0x00020000U) //!< Bit mask for SDHC_PROCTL_CREQ.
+#define BS_SDHC_PROCTL_CREQ (1U) //!< Bit field size in bits for SDHC_PROCTL_CREQ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PROCTL_CREQ field.
+#define BR_SDHC_PROCTL_CREQ (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CREQ))
+#endif
+
+//! @brief Format value for bitfield SDHC_PROCTL_CREQ.
+#define BF_SDHC_PROCTL_CREQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_CREQ), uint32_t) & BM_SDHC_PROCTL_CREQ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CREQ field to a new value.
+#define BW_SDHC_PROCTL_CREQ(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CREQ) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PROCTL, field RWCTL[18] (RW)
+ *
+ * The read wait function is optional for SDIO cards. If the card supports read
+ * wait, set this bit to enable use of the read wait protocol to stop read data
+ * using the DAT[2] line. Otherwise, the SDHC has to stop the SD Clock to hold
+ * read data, which restricts commands generation. When the host driver detects an
+ * SDIO card insertion, it shall set this bit according to the CCCR of the card.
+ * If the card does not support read wait, this bit shall never be set to 1,
+ * otherwise DAT line conflicts may occur. If this bit is set to 0, stop at block gap
+ * during read operation is also supported, but the SDHC will stop the SD Clock
+ * to pause reading operation.
+ *
+ * Values:
+ * - 0 - Disable read wait control, and stop SD clock at block gap when SABGREQ
+ * is set.
+ * - 1 - Enable read wait control, and assert read wait without stopping SD
+ * clock at block gap when SABGREQ bit is set.
+ */
+//@{
+#define BP_SDHC_PROCTL_RWCTL (18U) //!< Bit position for SDHC_PROCTL_RWCTL.
+#define BM_SDHC_PROCTL_RWCTL (0x00040000U) //!< Bit mask for SDHC_PROCTL_RWCTL.
+#define BS_SDHC_PROCTL_RWCTL (1U) //!< Bit field size in bits for SDHC_PROCTL_RWCTL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PROCTL_RWCTL field.
+#define BR_SDHC_PROCTL_RWCTL (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_RWCTL))
+#endif
+
+//! @brief Format value for bitfield SDHC_PROCTL_RWCTL.
+#define BF_SDHC_PROCTL_RWCTL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_RWCTL), uint32_t) & BM_SDHC_PROCTL_RWCTL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RWCTL field to a new value.
+#define BW_SDHC_PROCTL_RWCTL(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_RWCTL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PROCTL, field IABG[19] (RW)
+ *
+ * Valid only in 4-bit mode, of the SDIO card, and selects a sample point in the
+ * interrupt cycle. Setting to 1 enables interrupt detection at the block gap
+ * for a multiple block transfer. Setting to 0 disables interrupt detection during
+ * a multiple block transfer. If the SDIO card can't signal an interrupt during a
+ * multiple block transfer, this bit must be set to 0 to avoid an inadvertent
+ * interrupt. When the host driver detects an SDIO card insertion, it shall set
+ * this bit according to the CCCR of the card.
+ *
+ * Values:
+ * - 0 - Disabled
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_PROCTL_IABG (19U) //!< Bit position for SDHC_PROCTL_IABG.
+#define BM_SDHC_PROCTL_IABG (0x00080000U) //!< Bit mask for SDHC_PROCTL_IABG.
+#define BS_SDHC_PROCTL_IABG (1U) //!< Bit field size in bits for SDHC_PROCTL_IABG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PROCTL_IABG field.
+#define BR_SDHC_PROCTL_IABG (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_IABG))
+#endif
+
+//! @brief Format value for bitfield SDHC_PROCTL_IABG.
+#define BF_SDHC_PROCTL_IABG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_IABG), uint32_t) & BM_SDHC_PROCTL_IABG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IABG field to a new value.
+#define BW_SDHC_PROCTL_IABG(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_IABG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PROCTL, field WECINT[24] (RW)
+ *
+ * Enables a wakeup event, via IRQSTAT[CINT]. This bit can be set to 1 if FN_WUS
+ * (Wake Up Support) in CIS is set to 1. When this bit is set, the card
+ * interrupt status and the SDHC interrupt can be asserted without SD_CLK toggling. When
+ * the wakeup feature is not enabled, the SD_CLK must be active to assert the
+ * card interrupt status and the SDHC interrupt.
+ *
+ * Values:
+ * - 0 - Disabled
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_PROCTL_WECINT (24U) //!< Bit position for SDHC_PROCTL_WECINT.
+#define BM_SDHC_PROCTL_WECINT (0x01000000U) //!< Bit mask for SDHC_PROCTL_WECINT.
+#define BS_SDHC_PROCTL_WECINT (1U) //!< Bit field size in bits for SDHC_PROCTL_WECINT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PROCTL_WECINT field.
+#define BR_SDHC_PROCTL_WECINT (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECINT))
+#endif
+
+//! @brief Format value for bitfield SDHC_PROCTL_WECINT.
+#define BF_SDHC_PROCTL_WECINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_WECINT), uint32_t) & BM_SDHC_PROCTL_WECINT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WECINT field to a new value.
+#define BW_SDHC_PROCTL_WECINT(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECINT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PROCTL, field WECINS[25] (RW)
+ *
+ * Enables a wakeup event, via IRQSTAT[CINS]. FN_WUS (Wake Up Support) in CIS
+ * does not effect this bit. When this bit is set, IRQSTATEN[CINSEN] and the SDHC
+ * interrupt can be asserted without SD_CLK toggling. When the wakeup feature is
+ * not enabled, the SD_CLK must be active to assert IRQSTATEN[CINSEN] and the SDHC
+ * interrupt.
+ *
+ * Values:
+ * - 0 - Disabled
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_PROCTL_WECINS (25U) //!< Bit position for SDHC_PROCTL_WECINS.
+#define BM_SDHC_PROCTL_WECINS (0x02000000U) //!< Bit mask for SDHC_PROCTL_WECINS.
+#define BS_SDHC_PROCTL_WECINS (1U) //!< Bit field size in bits for SDHC_PROCTL_WECINS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PROCTL_WECINS field.
+#define BR_SDHC_PROCTL_WECINS (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECINS))
+#endif
+
+//! @brief Format value for bitfield SDHC_PROCTL_WECINS.
+#define BF_SDHC_PROCTL_WECINS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_WECINS), uint32_t) & BM_SDHC_PROCTL_WECINS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WECINS field to a new value.
+#define BW_SDHC_PROCTL_WECINS(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECINS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_PROCTL, field WECRM[26] (RW)
+ *
+ * Enables a wakeup event, via IRQSTAT[CRM]. FN_WUS (Wake Up Support) in CIS
+ * does not effect this bit. When this bit is set, IRQSTAT[CRM] and the SDHC
+ * interrupt can be asserted without SD_CLK toggling. When the wakeup feature is not
+ * enabled, the SD_CLK must be active to assert IRQSTAT[CRM] and the SDHC interrupt.
+ *
+ * Values:
+ * - 0 - Disabled
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_PROCTL_WECRM (26U) //!< Bit position for SDHC_PROCTL_WECRM.
+#define BM_SDHC_PROCTL_WECRM (0x04000000U) //!< Bit mask for SDHC_PROCTL_WECRM.
+#define BS_SDHC_PROCTL_WECRM (1U) //!< Bit field size in bits for SDHC_PROCTL_WECRM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_PROCTL_WECRM field.
+#define BR_SDHC_PROCTL_WECRM (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECRM))
+#endif
+
+//! @brief Format value for bitfield SDHC_PROCTL_WECRM.
+#define BF_SDHC_PROCTL_WECRM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_WECRM), uint32_t) & BM_SDHC_PROCTL_WECRM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WECRM field to a new value.
+#define BW_SDHC_PROCTL_WECRM(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECRM) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_SYSCTL - System Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_SYSCTL - System Control register (RW)
+ *
+ * Reset value: 0x00008008U
+ */
+typedef union _hw_sdhc_sysctl
+{
+ uint32_t U;
+ struct _hw_sdhc_sysctl_bitfields
+ {
+ uint32_t IPGEN : 1; //!< [0] IPG Clock Enable
+ uint32_t HCKEN : 1; //!< [1] System Clock Enable
+ uint32_t PEREN : 1; //!< [2] Peripheral Clock Enable
+ uint32_t SDCLKEN : 1; //!< [3] SD Clock Enable
+ uint32_t DVS : 4; //!< [7:4] Divisor
+ uint32_t SDCLKFS : 8; //!< [15:8] SDCLK Frequency Select
+ uint32_t DTOCV : 4; //!< [19:16] Data Timeout Counter Value
+ uint32_t RESERVED0 : 4; //!< [23:20]
+ uint32_t RSTA : 1; //!< [24] Software Reset For ALL
+ uint32_t RSTC : 1; //!< [25] Software Reset For CMD Line
+ uint32_t RSTD : 1; //!< [26] Software Reset For DAT Line
+ uint32_t INITA : 1; //!< [27] Initialization Active
+ uint32_t RESERVED1 : 4; //!< [31:28]
+ } B;
+} hw_sdhc_sysctl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_SYSCTL register
+ */
+//@{
+#define HW_SDHC_SYSCTL_ADDR (REGS_SDHC_BASE + 0x2CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_SYSCTL (*(__IO hw_sdhc_sysctl_t *) HW_SDHC_SYSCTL_ADDR)
+#define HW_SDHC_SYSCTL_RD() (HW_SDHC_SYSCTL.U)
+#define HW_SDHC_SYSCTL_WR(v) (HW_SDHC_SYSCTL.U = (v))
+#define HW_SDHC_SYSCTL_SET(v) (HW_SDHC_SYSCTL_WR(HW_SDHC_SYSCTL_RD() | (v)))
+#define HW_SDHC_SYSCTL_CLR(v) (HW_SDHC_SYSCTL_WR(HW_SDHC_SYSCTL_RD() & ~(v)))
+#define HW_SDHC_SYSCTL_TOG(v) (HW_SDHC_SYSCTL_WR(HW_SDHC_SYSCTL_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_SYSCTL bitfields
+ */
+
+/*!
+ * @name Register SDHC_SYSCTL, field IPGEN[0] (RW)
+ *
+ * If this bit is set, bus clock will always be active and no automatic gating
+ * is applied. The bus clock will be internally gated off, if none of the
+ * following factors are met: The cmd part is reset, or Data part is reset, or Soft
+ * reset, or The cmd is about to send, or Clock divisor is just updated, or Continue
+ * request is just set, or This bit is set, or Card insertion is detected, or Card
+ * removal is detected, or Card external interrupt is detected, or The SDHC
+ * clock is not gated off The bus clock will not be auto gated off if the SDHC clock
+ * is not gated off. So clearing only this bit has no effect unless the PEREN bit
+ * is also cleared.
+ *
+ * Values:
+ * - 0 - Bus clock will be internally gated off.
+ * - 1 - Bus clock will not be automatically gated off.
+ */
+//@{
+#define BP_SDHC_SYSCTL_IPGEN (0U) //!< Bit position for SDHC_SYSCTL_IPGEN.
+#define BM_SDHC_SYSCTL_IPGEN (0x00000001U) //!< Bit mask for SDHC_SYSCTL_IPGEN.
+#define BS_SDHC_SYSCTL_IPGEN (1U) //!< Bit field size in bits for SDHC_SYSCTL_IPGEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_SYSCTL_IPGEN field.
+#define BR_SDHC_SYSCTL_IPGEN (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_IPGEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_SYSCTL_IPGEN.
+#define BF_SDHC_SYSCTL_IPGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_IPGEN), uint32_t) & BM_SDHC_SYSCTL_IPGEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IPGEN field to a new value.
+#define BW_SDHC_SYSCTL_IPGEN(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_IPGEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_SYSCTL, field HCKEN[1] (RW)
+ *
+ * If this bit is set, system clock will always be active and no automatic
+ * gating is applied. When this bit is cleared, system clock will be automatically off
+ * when no data transfer is on the SD bus.
+ *
+ * Values:
+ * - 0 - System clock will be internally gated off.
+ * - 1 - System clock will not be automatically gated off.
+ */
+//@{
+#define BP_SDHC_SYSCTL_HCKEN (1U) //!< Bit position for SDHC_SYSCTL_HCKEN.
+#define BM_SDHC_SYSCTL_HCKEN (0x00000002U) //!< Bit mask for SDHC_SYSCTL_HCKEN.
+#define BS_SDHC_SYSCTL_HCKEN (1U) //!< Bit field size in bits for SDHC_SYSCTL_HCKEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_SYSCTL_HCKEN field.
+#define BR_SDHC_SYSCTL_HCKEN (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_HCKEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_SYSCTL_HCKEN.
+#define BF_SDHC_SYSCTL_HCKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_HCKEN), uint32_t) & BM_SDHC_SYSCTL_HCKEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HCKEN field to a new value.
+#define BW_SDHC_SYSCTL_HCKEN(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_HCKEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_SYSCTL, field PEREN[2] (RW)
+ *
+ * If this bit is set, SDHC clock will always be active and no automatic gating
+ * is applied. Thus the SDCLK is active except for when auto gating-off during
+ * buffer danger (buffer about to over-run or under-run). When this bit is cleared,
+ * the SDHC clock will be automatically off whenever there is no transaction on
+ * the SD bus. Because this bit is only a feature enabling bit, clearing this bit
+ * does not stop SDCLK immediately. The SDHC clock will be internally gated off,
+ * if none of the following factors are met: The cmd part is reset, or Data part
+ * is reset, or A soft reset, or The cmd is about to send, or Clock divisor is
+ * just updated, or Continue request is just set, or This bit is set, or Card
+ * insertion is detected, or Card removal is detected, or Card external interrupt is
+ * detected, or 80 clocks for initialization phase is ongoing
+ *
+ * Values:
+ * - 0 - SDHC clock will be internally gated off.
+ * - 1 - SDHC clock will not be automatically gated off.
+ */
+//@{
+#define BP_SDHC_SYSCTL_PEREN (2U) //!< Bit position for SDHC_SYSCTL_PEREN.
+#define BM_SDHC_SYSCTL_PEREN (0x00000004U) //!< Bit mask for SDHC_SYSCTL_PEREN.
+#define BS_SDHC_SYSCTL_PEREN (1U) //!< Bit field size in bits for SDHC_SYSCTL_PEREN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_SYSCTL_PEREN field.
+#define BR_SDHC_SYSCTL_PEREN (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_PEREN))
+#endif
+
+//! @brief Format value for bitfield SDHC_SYSCTL_PEREN.
+#define BF_SDHC_SYSCTL_PEREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_PEREN), uint32_t) & BM_SDHC_SYSCTL_PEREN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PEREN field to a new value.
+#define BW_SDHC_SYSCTL_PEREN(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_PEREN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_SYSCTL, field SDCLKEN[3] (RW)
+ *
+ * The host controller shall stop SDCLK when writing this bit to 0. SDCLK
+ * frequency can be changed when this bit is 0. Then, the host controller shall
+ * maintain the same clock frequency until SDCLK is stopped (stop at SDCLK = 0). If the
+ * IRQSTAT[CINS] is cleared, this bit must be cleared by the host driver to save
+ * power.
+ */
+//@{
+#define BP_SDHC_SYSCTL_SDCLKEN (3U) //!< Bit position for SDHC_SYSCTL_SDCLKEN.
+#define BM_SDHC_SYSCTL_SDCLKEN (0x00000008U) //!< Bit mask for SDHC_SYSCTL_SDCLKEN.
+#define BS_SDHC_SYSCTL_SDCLKEN (1U) //!< Bit field size in bits for SDHC_SYSCTL_SDCLKEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_SYSCTL_SDCLKEN field.
+#define BR_SDHC_SYSCTL_SDCLKEN (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_SDCLKEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_SYSCTL_SDCLKEN.
+#define BF_SDHC_SYSCTL_SDCLKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_SDCLKEN), uint32_t) & BM_SDHC_SYSCTL_SDCLKEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SDCLKEN field to a new value.
+#define BW_SDHC_SYSCTL_SDCLKEN(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_SDCLKEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_SYSCTL, field DVS[7:4] (RW)
+ *
+ * Used to provide a more exact divisor to generate the desired SD clock
+ * frequency. Note the divider can even support odd divisor without deterioration of
+ * duty cycle. The setting are as following:
+ *
+ * Values:
+ * - 0 - Divisor by 1.
+ * - 1 - Divisor by 2.
+ * - 1110 - Divisor by 15.
+ * - 1111 - Divisor by 16.
+ */
+//@{
+#define BP_SDHC_SYSCTL_DVS (4U) //!< Bit position for SDHC_SYSCTL_DVS.
+#define BM_SDHC_SYSCTL_DVS (0x000000F0U) //!< Bit mask for SDHC_SYSCTL_DVS.
+#define BS_SDHC_SYSCTL_DVS (4U) //!< Bit field size in bits for SDHC_SYSCTL_DVS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_SYSCTL_DVS field.
+#define BR_SDHC_SYSCTL_DVS (HW_SDHC_SYSCTL.B.DVS)
+#endif
+
+//! @brief Format value for bitfield SDHC_SYSCTL_DVS.
+#define BF_SDHC_SYSCTL_DVS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_DVS), uint32_t) & BM_SDHC_SYSCTL_DVS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DVS field to a new value.
+#define BW_SDHC_SYSCTL_DVS(v) (HW_SDHC_SYSCTL_WR((HW_SDHC_SYSCTL_RD() & ~BM_SDHC_SYSCTL_DVS) | BF_SDHC_SYSCTL_DVS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_SYSCTL, field SDCLKFS[15:8] (RW)
+ *
+ * Used to select the frequency of the SDCLK pin. The frequency is not
+ * programmed directly. Rather this register holds the prescaler (this register) and
+ * divisor (next register) of the base clock frequency register. Setting 00h bypasses
+ * the frequency prescaler of the SD Clock. Multiple bits must not be set, or the
+ * behavior of this prescaler is undefined. The two default divider values can
+ * be calculated by the frequency of SDHC clock and the following divisor bits.
+ * The frequency of SDCLK is set by the following formula: Clock frequency = (Base
+ * clock) / (prescaler x divisor) For example, if the base clock frequency is 96
+ * MHz, and the target frequency is 25 MHz, then choosing the prescaler value of
+ * 01h and divisor value of 1h will yield 24 MHz, which is the nearest frequency
+ * less than or equal to the target. Similarly, to approach a clock value of 400
+ * kHz, the prescaler value of 08h and divisor value of eh yields the exact clock
+ * value of 400 kHz. The reset value of this field is 80h, so if the input base
+ * clock ( SDHC clock ) is about 96 MHz, the default SD clock after reset is 375
+ * kHz. According to the SD Physical Specification Version 1.1 and the SDIO Card
+ * Specification Version 1.2, the maximum SD clock frequency is 50 MHz and shall
+ * never exceed this limit. Only the following settings are allowed:
+ *
+ * Values:
+ * - 1 - Base clock divided by 2.
+ * - 10 - Base clock divided by 4.
+ * - 100 - Base clock divided by 8.
+ * - 1000 - Base clock divided by 16.
+ * - 10000 - Base clock divided by 32.
+ * - 100000 - Base clock divided by 64.
+ * - 1000000 - Base clock divided by 128.
+ * - 10000000 - Base clock divided by 256.
+ */
+//@{
+#define BP_SDHC_SYSCTL_SDCLKFS (8U) //!< Bit position for SDHC_SYSCTL_SDCLKFS.
+#define BM_SDHC_SYSCTL_SDCLKFS (0x0000FF00U) //!< Bit mask for SDHC_SYSCTL_SDCLKFS.
+#define BS_SDHC_SYSCTL_SDCLKFS (8U) //!< Bit field size in bits for SDHC_SYSCTL_SDCLKFS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_SYSCTL_SDCLKFS field.
+#define BR_SDHC_SYSCTL_SDCLKFS (HW_SDHC_SYSCTL.B.SDCLKFS)
+#endif
+
+//! @brief Format value for bitfield SDHC_SYSCTL_SDCLKFS.
+#define BF_SDHC_SYSCTL_SDCLKFS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_SDCLKFS), uint32_t) & BM_SDHC_SYSCTL_SDCLKFS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SDCLKFS field to a new value.
+#define BW_SDHC_SYSCTL_SDCLKFS(v) (HW_SDHC_SYSCTL_WR((HW_SDHC_SYSCTL_RD() & ~BM_SDHC_SYSCTL_SDCLKFS) | BF_SDHC_SYSCTL_SDCLKFS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_SYSCTL, field DTOCV[19:16] (RW)
+ *
+ * Determines the interval by which DAT line timeouts are detected. See
+ * IRQSTAT[DTOE] for information on factors that dictate time-out generation. Time-out
+ * clock frequency will be generated by dividing the base clock SDCLK value by this
+ * value. The host driver can clear IRQSTATEN[DTOESEN] to prevent inadvertent
+ * time-out events.
+ *
+ * Values:
+ * - 0000 - SDCLK x 2 13
+ * - 0001 - SDCLK x 2 14
+ * - 1110 - SDCLK x 2 27
+ * - 1111 - Reserved
+ */
+//@{
+#define BP_SDHC_SYSCTL_DTOCV (16U) //!< Bit position for SDHC_SYSCTL_DTOCV.
+#define BM_SDHC_SYSCTL_DTOCV (0x000F0000U) //!< Bit mask for SDHC_SYSCTL_DTOCV.
+#define BS_SDHC_SYSCTL_DTOCV (4U) //!< Bit field size in bits for SDHC_SYSCTL_DTOCV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_SYSCTL_DTOCV field.
+#define BR_SDHC_SYSCTL_DTOCV (HW_SDHC_SYSCTL.B.DTOCV)
+#endif
+
+//! @brief Format value for bitfield SDHC_SYSCTL_DTOCV.
+#define BF_SDHC_SYSCTL_DTOCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_DTOCV), uint32_t) & BM_SDHC_SYSCTL_DTOCV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DTOCV field to a new value.
+#define BW_SDHC_SYSCTL_DTOCV(v) (HW_SDHC_SYSCTL_WR((HW_SDHC_SYSCTL_RD() & ~BM_SDHC_SYSCTL_DTOCV) | BF_SDHC_SYSCTL_DTOCV(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_SYSCTL, field RSTA[24] (WORZ)
+ *
+ * Effects the entire host controller except for the card detection circuit.
+ * Register bits of type ROC, RW, RW1C, RWAC are cleared. During its initialization,
+ * the host driver shall set this bit to 1 to reset the SDHC. The SDHC shall
+ * reset this bit to 0 when the capabilities registers are valid and the host driver
+ * can read them. Additional use of software reset for all does not affect the
+ * value of the capabilities registers. After this bit is set, it is recommended
+ * that the host driver reset the external card and reinitialize it.
+ *
+ * Values:
+ * - 0 - No reset.
+ * - 1 - Reset.
+ */
+//@{
+#define BP_SDHC_SYSCTL_RSTA (24U) //!< Bit position for SDHC_SYSCTL_RSTA.
+#define BM_SDHC_SYSCTL_RSTA (0x01000000U) //!< Bit mask for SDHC_SYSCTL_RSTA.
+#define BS_SDHC_SYSCTL_RSTA (1U) //!< Bit field size in bits for SDHC_SYSCTL_RSTA.
+
+//! @brief Format value for bitfield SDHC_SYSCTL_RSTA.
+#define BF_SDHC_SYSCTL_RSTA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_RSTA), uint32_t) & BM_SDHC_SYSCTL_RSTA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RSTA field to a new value.
+#define BW_SDHC_SYSCTL_RSTA(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_RSTA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_SYSCTL, field RSTC[25] (WORZ)
+ *
+ * Only part of the command circuit is reset. The following registers and bits
+ * are cleared by this bit: PRSSTAT[CIHB] IRQSTAT[CC]
+ *
+ * Values:
+ * - 0 - No reset.
+ * - 1 - Reset.
+ */
+//@{
+#define BP_SDHC_SYSCTL_RSTC (25U) //!< Bit position for SDHC_SYSCTL_RSTC.
+#define BM_SDHC_SYSCTL_RSTC (0x02000000U) //!< Bit mask for SDHC_SYSCTL_RSTC.
+#define BS_SDHC_SYSCTL_RSTC (1U) //!< Bit field size in bits for SDHC_SYSCTL_RSTC.
+
+//! @brief Format value for bitfield SDHC_SYSCTL_RSTC.
+#define BF_SDHC_SYSCTL_RSTC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_RSTC), uint32_t) & BM_SDHC_SYSCTL_RSTC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RSTC field to a new value.
+#define BW_SDHC_SYSCTL_RSTC(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_RSTC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_SYSCTL, field RSTD[26] (WORZ)
+ *
+ * Only part of the data circuit is reset. DMA circuit is also reset. The
+ * following registers and bits are cleared by this bit: Data Port register Buffer Is
+ * Cleared And Initialized.Present State register Buffer Read Enable Buffer Write
+ * Enable Read Transfer Active Write Transfer Active DAT Line Active Command
+ * Inhibit (DAT) Protocol Control register Continue Request Stop At Block Gap Request
+ * Interrupt Status register Buffer Read Ready Buffer Write Ready DMA Interrupt
+ * Block Gap Event Transfer Complete
+ *
+ * Values:
+ * - 0 - No reset.
+ * - 1 - Reset.
+ */
+//@{
+#define BP_SDHC_SYSCTL_RSTD (26U) //!< Bit position for SDHC_SYSCTL_RSTD.
+#define BM_SDHC_SYSCTL_RSTD (0x04000000U) //!< Bit mask for SDHC_SYSCTL_RSTD.
+#define BS_SDHC_SYSCTL_RSTD (1U) //!< Bit field size in bits for SDHC_SYSCTL_RSTD.
+
+//! @brief Format value for bitfield SDHC_SYSCTL_RSTD.
+#define BF_SDHC_SYSCTL_RSTD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_RSTD), uint32_t) & BM_SDHC_SYSCTL_RSTD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RSTD field to a new value.
+#define BW_SDHC_SYSCTL_RSTD(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_RSTD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_SYSCTL, field INITA[27] (RW)
+ *
+ * When this bit is set, 80 SD-clocks are sent to the card. After the 80 clocks
+ * are sent, this bit is self-cleared. This bit is very useful during the card
+ * power-up period when 74 SD-clocks are needed and the clock auto gating feature
+ * is enabled. Writing 1 to this bit when this bit is already 1 has no effect.
+ * Writing 0 to this bit at any time has no effect. When either of the PRSSTAT[CIHB]
+ * and PRSSTAT[CDIHB] bits are set, writing 1 to this bit is ignored, that is,
+ * when command line or data lines are active, write to this bit is not allowed.
+ * On the otherhand, when this bit is set, that is, during intialization active
+ * period, it is allowed to issue command, and the command bit stream will appear
+ * on the CMD pad after all 80 clock cycles are done. So when this command ends,
+ * the driver can make sure the 80 clock cycles are sent out. This is very useful
+ * when the driver needs send 80 cycles to the card and does not want to wait
+ * till this bit is self-cleared.
+ */
+//@{
+#define BP_SDHC_SYSCTL_INITA (27U) //!< Bit position for SDHC_SYSCTL_INITA.
+#define BM_SDHC_SYSCTL_INITA (0x08000000U) //!< Bit mask for SDHC_SYSCTL_INITA.
+#define BS_SDHC_SYSCTL_INITA (1U) //!< Bit field size in bits for SDHC_SYSCTL_INITA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_SYSCTL_INITA field.
+#define BR_SDHC_SYSCTL_INITA (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_INITA))
+#endif
+
+//! @brief Format value for bitfield SDHC_SYSCTL_INITA.
+#define BF_SDHC_SYSCTL_INITA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_INITA), uint32_t) & BM_SDHC_SYSCTL_INITA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INITA field to a new value.
+#define BW_SDHC_SYSCTL_INITA(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_INITA) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_IRQSTAT - Interrupt Status register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_IRQSTAT - Interrupt Status register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * An interrupt is generated when the Normal Interrupt Signal Enable is enabled
+ * and at least one of the status bits is set to 1. For all bits, writing 1 to a
+ * bit clears it; writing to 0 keeps the bit unchanged. More than one status can
+ * be cleared with a single register write. For Card Interrupt, before writing 1
+ * to clear, it is required that the card stops asserting the interrupt, meaning
+ * that when the Card Driver services the interrupt condition, otherwise the CINT
+ * bit will be asserted again. The table below shows the relationship between
+ * the CTOE and the CC bits. SDHC status for CTOE/CC bit combinations Command
+ * complete Command timeout error Meaning of the status 0 0 X X 1 Response not
+ * received within 64 SDCLK cycles 1 0 Response received The table below shows the
+ * relationship between the Transfer Complete and the Data Timeout Error. SDHC status
+ * for data timeout error/transfer complete bit combinations Transfer complete
+ * Data timeout error Meaning of the status 0 0 X 0 1 Timeout occurred during
+ * transfer 1 X Data transfer complete The table below shows the relationship between
+ * the command CRC Error (CCE) and Command Timeout Error (CTOE). SDHC status for
+ * CCE/CTOE Bit Combinations Command complete Command timeout error Meaning of
+ * the status 0 0 No error 0 1 Response timeout error 1 0 Response CRC error 1 1
+ * CMD line conflict
+ */
+typedef union _hw_sdhc_irqstat
+{
+ uint32_t U;
+ struct _hw_sdhc_irqstat_bitfields
+ {
+ uint32_t CC : 1; //!< [0] Command Complete
+ uint32_t TC : 1; //!< [1] Transfer Complete
+ uint32_t BGE : 1; //!< [2] Block Gap Event
+ uint32_t DINT : 1; //!< [3] DMA Interrupt
+ uint32_t BWR : 1; //!< [4] Buffer Write Ready
+ uint32_t BRR : 1; //!< [5] Buffer Read Ready
+ uint32_t CINS : 1; //!< [6] Card Insertion
+ uint32_t CRM : 1; //!< [7] Card Removal
+ uint32_t CINT : 1; //!< [8] Card Interrupt
+ uint32_t RESERVED0 : 7; //!< [15:9]
+ uint32_t CTOE : 1; //!< [16] Command Timeout Error
+ uint32_t CCE : 1; //!< [17] Command CRC Error
+ uint32_t CEBE : 1; //!< [18] Command End Bit Error
+ uint32_t CIE : 1; //!< [19] Command Index Error
+ uint32_t DTOE : 1; //!< [20] Data Timeout Error
+ uint32_t DCE : 1; //!< [21] Data CRC Error
+ uint32_t DEBE : 1; //!< [22] Data End Bit Error
+ uint32_t RESERVED1 : 1; //!< [23]
+ uint32_t AC12E : 1; //!< [24] Auto CMD12 Error
+ uint32_t RESERVED2 : 3; //!< [27:25]
+ uint32_t DMAE : 1; //!< [28] DMA Error
+ uint32_t RESERVED3 : 3; //!< [31:29]
+ } B;
+} hw_sdhc_irqstat_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_IRQSTAT register
+ */
+//@{
+#define HW_SDHC_IRQSTAT_ADDR (REGS_SDHC_BASE + 0x30U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_IRQSTAT (*(__IO hw_sdhc_irqstat_t *) HW_SDHC_IRQSTAT_ADDR)
+#define HW_SDHC_IRQSTAT_RD() (HW_SDHC_IRQSTAT.U)
+#define HW_SDHC_IRQSTAT_WR(v) (HW_SDHC_IRQSTAT.U = (v))
+#define HW_SDHC_IRQSTAT_SET(v) (HW_SDHC_IRQSTAT_WR(HW_SDHC_IRQSTAT_RD() | (v)))
+#define HW_SDHC_IRQSTAT_CLR(v) (HW_SDHC_IRQSTAT_WR(HW_SDHC_IRQSTAT_RD() & ~(v)))
+#define HW_SDHC_IRQSTAT_TOG(v) (HW_SDHC_IRQSTAT_WR(HW_SDHC_IRQSTAT_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_IRQSTAT bitfields
+ */
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CC[0] (W1C)
+ *
+ * This bit is set when you receive the end bit of the command response, except
+ * Auto CMD12. See PRSSTAT[CIHB].
+ *
+ * Values:
+ * - 0 - Command not complete.
+ * - 1 - Command complete.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_CC (0U) //!< Bit position for SDHC_IRQSTAT_CC.
+#define BM_SDHC_IRQSTAT_CC (0x00000001U) //!< Bit mask for SDHC_IRQSTAT_CC.
+#define BS_SDHC_IRQSTAT_CC (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_CC field.
+#define BR_SDHC_IRQSTAT_CC (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CC))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_CC.
+#define BF_SDHC_IRQSTAT_CC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CC), uint32_t) & BM_SDHC_IRQSTAT_CC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CC field to a new value.
+#define BW_SDHC_IRQSTAT_CC(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field TC[1] (W1C)
+ *
+ * This bit is set when a read or write transfer is completed. In the case of a
+ * read transaction: This bit is set at the falling edge of the read transfer
+ * active status. There are two cases in which this interrupt is generated. The
+ * first is when a data transfer is completed as specified by the data length, after
+ * the last data has been read to the host system. The second is when data has
+ * stopped at the block gap and completed the data transfer by setting
+ * PROCTL[SABGREQ], after valid data has been read to the host system. In the case of a write
+ * transaction: This bit is set at the falling edge of the DAT line active
+ * status. There are two cases in which this interrupt is generated. The first is when
+ * the last data is written to the SD card as specified by the data length and
+ * the busy signal is released. The second is when data transfers are stopped at
+ * the block gap, by setting PROCTL[SABGREQ], and the data transfers are
+ * completed,after valid data is written to the SD card and the busy signal released.
+ *
+ * Values:
+ * - 0 - Transfer not complete.
+ * - 1 - Transfer complete.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_TC (1U) //!< Bit position for SDHC_IRQSTAT_TC.
+#define BM_SDHC_IRQSTAT_TC (0x00000002U) //!< Bit mask for SDHC_IRQSTAT_TC.
+#define BS_SDHC_IRQSTAT_TC (1U) //!< Bit field size in bits for SDHC_IRQSTAT_TC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_TC field.
+#define BR_SDHC_IRQSTAT_TC (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_TC))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_TC.
+#define BF_SDHC_IRQSTAT_TC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_TC), uint32_t) & BM_SDHC_IRQSTAT_TC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TC field to a new value.
+#define BW_SDHC_IRQSTAT_TC(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_TC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field BGE[2] (W1C)
+ *
+ * If PROCTL[SABGREQ] is set, this bit is set when a read or write transaction
+ * is stopped at a block gap. If PROCTL[SABGREQ] is not set to 1, this bit is not
+ * set to 1. In the case of a read transaction: This bit is set at the falling
+ * edge of the DAT line active status, when the transaction is stopped at SD Bus
+ * timing. The read wait must be supported in order to use this function. In the
+ * case of write transaction: This bit is set at the falling edge of write transfer
+ * active status, after getting CRC status at SD bus timing.
+ *
+ * Values:
+ * - 0 - No block gap event.
+ * - 1 - Transaction stopped at block gap.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_BGE (2U) //!< Bit position for SDHC_IRQSTAT_BGE.
+#define BM_SDHC_IRQSTAT_BGE (0x00000004U) //!< Bit mask for SDHC_IRQSTAT_BGE.
+#define BS_SDHC_IRQSTAT_BGE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_BGE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_BGE field.
+#define BR_SDHC_IRQSTAT_BGE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BGE))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_BGE.
+#define BF_SDHC_IRQSTAT_BGE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_BGE), uint32_t) & BM_SDHC_IRQSTAT_BGE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BGE field to a new value.
+#define BW_SDHC_IRQSTAT_BGE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BGE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DINT[3] (W1C)
+ *
+ * Occurs only when the internal DMA finishes the data transfer successfully.
+ * Whenever errors occur during data transfer, this bit will not be set. Instead,
+ * the DMAE bit will be set. Either Simple DMA or ADMA finishes data transferring,
+ * this bit will be set.
+ *
+ * Values:
+ * - 0 - No DMA Interrupt.
+ * - 1 - DMA Interrupt is generated.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_DINT (3U) //!< Bit position for SDHC_IRQSTAT_DINT.
+#define BM_SDHC_IRQSTAT_DINT (0x00000008U) //!< Bit mask for SDHC_IRQSTAT_DINT.
+#define BS_SDHC_IRQSTAT_DINT (1U) //!< Bit field size in bits for SDHC_IRQSTAT_DINT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_DINT field.
+#define BR_SDHC_IRQSTAT_DINT (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DINT))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_DINT.
+#define BF_SDHC_IRQSTAT_DINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_DINT), uint32_t) & BM_SDHC_IRQSTAT_DINT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DINT field to a new value.
+#define BW_SDHC_IRQSTAT_DINT(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DINT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field BWR[4] (W1C)
+ *
+ * This status bit is set if the Buffer Write Enable bit, in the Present State
+ * register, changes from 0 to 1. See the Buffer Write Enable bit in the Present
+ * State register for additional information.
+ *
+ * Values:
+ * - 0 - Not ready to write buffer.
+ * - 1 - Ready to write buffer.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_BWR (4U) //!< Bit position for SDHC_IRQSTAT_BWR.
+#define BM_SDHC_IRQSTAT_BWR (0x00000010U) //!< Bit mask for SDHC_IRQSTAT_BWR.
+#define BS_SDHC_IRQSTAT_BWR (1U) //!< Bit field size in bits for SDHC_IRQSTAT_BWR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_BWR field.
+#define BR_SDHC_IRQSTAT_BWR (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BWR))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_BWR.
+#define BF_SDHC_IRQSTAT_BWR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_BWR), uint32_t) & BM_SDHC_IRQSTAT_BWR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BWR field to a new value.
+#define BW_SDHC_IRQSTAT_BWR(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BWR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field BRR[5] (W1C)
+ *
+ * This status bit is set if the Buffer Read Enable bit, in the Present State
+ * register, changes from 0 to 1. See the Buffer Read Enable bit in the Present
+ * State register for additional information.
+ *
+ * Values:
+ * - 0 - Not ready to read buffer.
+ * - 1 - Ready to read buffer.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_BRR (5U) //!< Bit position for SDHC_IRQSTAT_BRR.
+#define BM_SDHC_IRQSTAT_BRR (0x00000020U) //!< Bit mask for SDHC_IRQSTAT_BRR.
+#define BS_SDHC_IRQSTAT_BRR (1U) //!< Bit field size in bits for SDHC_IRQSTAT_BRR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_BRR field.
+#define BR_SDHC_IRQSTAT_BRR (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BRR))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_BRR.
+#define BF_SDHC_IRQSTAT_BRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_BRR), uint32_t) & BM_SDHC_IRQSTAT_BRR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BRR field to a new value.
+#define BW_SDHC_IRQSTAT_BRR(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BRR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CINS[6] (W1C)
+ *
+ * This status bit is set if the Card Inserted bit in the Present State register
+ * changes from 0 to 1. When the host driver writes this bit to 1 to clear this
+ * status, the status of the Card Inserted in the Present State register must be
+ * confirmed. Because the card state may possibly be changed when the host driver
+ * clears this bit and the interrupt event may not be generated. When this bit
+ * is cleared, it will be set again if a card is inserted. To leave it cleared,
+ * clear the Card Inserted Status Enable bit in Interrupt Status Enable register.
+ *
+ * Values:
+ * - 0 - Card state unstable or removed.
+ * - 1 - Card inserted.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_CINS (6U) //!< Bit position for SDHC_IRQSTAT_CINS.
+#define BM_SDHC_IRQSTAT_CINS (0x00000040U) //!< Bit mask for SDHC_IRQSTAT_CINS.
+#define BS_SDHC_IRQSTAT_CINS (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CINS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_CINS field.
+#define BR_SDHC_IRQSTAT_CINS (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CINS))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_CINS.
+#define BF_SDHC_IRQSTAT_CINS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CINS), uint32_t) & BM_SDHC_IRQSTAT_CINS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CINS field to a new value.
+#define BW_SDHC_IRQSTAT_CINS(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CINS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CRM[7] (W1C)
+ *
+ * This status bit is set if the Card Inserted bit in the Present State register
+ * changes from 1 to 0. When the host driver writes this bit to 1 to clear this
+ * status, the status of the Card Inserted in the Present State register must be
+ * confirmed. Because the card state may possibly be changed when the host driver
+ * clears this bit and the interrupt event may not be generated. When this bit
+ * is cleared, it will be set again if no card is inserted. To leave it cleared,
+ * clear the Card Removal Status Enable bit in Interrupt Status Enable register.
+ *
+ * Values:
+ * - 0 - Card state unstable or inserted.
+ * - 1 - Card removed.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_CRM (7U) //!< Bit position for SDHC_IRQSTAT_CRM.
+#define BM_SDHC_IRQSTAT_CRM (0x00000080U) //!< Bit mask for SDHC_IRQSTAT_CRM.
+#define BS_SDHC_IRQSTAT_CRM (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CRM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_CRM field.
+#define BR_SDHC_IRQSTAT_CRM (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CRM))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_CRM.
+#define BF_SDHC_IRQSTAT_CRM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CRM), uint32_t) & BM_SDHC_IRQSTAT_CRM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CRM field to a new value.
+#define BW_SDHC_IRQSTAT_CRM(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CRM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CINT[8] (W1C)
+ *
+ * This status bit is set when an interrupt signal is detected from the external
+ * card. In 1-bit mode, the SDHC will detect the Card Interrupt without the SD
+ * Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled
+ * during the interrupt cycle, so the interrupt from card can only be sampled
+ * during interrupt cycle, introducing some delay between the interrupt signal from
+ * the SDIO card and the interrupt to the host system. Writing this bit to 1 can
+ * clear this bit, but as the interrupt factor from the SDIO card does not clear,
+ * this bit is set again. To clear this bit, it is required to reset the interrupt
+ * factor from the external card followed by a writing 1 to this bit. When this
+ * status has been set, and the host driver needs to service this interrupt, the
+ * Card Interrupt Signal Enable in the Interrupt Signal Enable register should be
+ * 0 to stop driving the interrupt signal to the host system. After completion
+ * of the card interrupt service (it must reset the interrupt factors in the SDIO
+ * card and the interrupt signal may not be asserted), write 1 to clear this bit,
+ * set the Card Interrupt Signal Enable to 1, and start sampling the interrupt
+ * signal again.
+ *
+ * Values:
+ * - 0 - No Card Interrupt.
+ * - 1 - Generate Card Interrupt.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_CINT (8U) //!< Bit position for SDHC_IRQSTAT_CINT.
+#define BM_SDHC_IRQSTAT_CINT (0x00000100U) //!< Bit mask for SDHC_IRQSTAT_CINT.
+#define BS_SDHC_IRQSTAT_CINT (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CINT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_CINT field.
+#define BR_SDHC_IRQSTAT_CINT (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CINT))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_CINT.
+#define BF_SDHC_IRQSTAT_CINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CINT), uint32_t) & BM_SDHC_IRQSTAT_CINT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CINT field to a new value.
+#define BW_SDHC_IRQSTAT_CINT(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CINT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CTOE[16] (W1C)
+ *
+ * Occurs only if no response is returned within 64 SDCLK cycles from the end
+ * bit of the command. If the SDHC detects a CMD line conflict, in which case a
+ * Command CRC Error shall also be set, this bit shall be set without waiting for 64
+ * SDCLK cycles. This is because the command will be aborted by the SDHC.
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - Time out.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_CTOE (16U) //!< Bit position for SDHC_IRQSTAT_CTOE.
+#define BM_SDHC_IRQSTAT_CTOE (0x00010000U) //!< Bit mask for SDHC_IRQSTAT_CTOE.
+#define BS_SDHC_IRQSTAT_CTOE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CTOE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_CTOE field.
+#define BR_SDHC_IRQSTAT_CTOE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CTOE))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_CTOE.
+#define BF_SDHC_IRQSTAT_CTOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CTOE), uint32_t) & BM_SDHC_IRQSTAT_CTOE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CTOE field to a new value.
+#define BW_SDHC_IRQSTAT_CTOE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CTOE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CCE[17] (W1C)
+ *
+ * Command CRC Error is generated in two cases. If a response is returned and
+ * the Command Timeout Error is set to 0, indicating no time-out, this bit is set
+ * when detecting a CRC error in the command response. The SDHC detects a CMD line
+ * conflict by monitoring the CMD line when a command is issued. If the SDHC
+ * drives the CMD line to 1, but detects 0 on the CMD line at the next SDCLK edge,
+ * then the SDHC shall abort the command (Stop driving CMD line) and set this bit
+ * to 1. The Command Timeout Error shall also be set to 1 to distinguish CMD line
+ * conflict.
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - CRC Error generated.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_CCE (17U) //!< Bit position for SDHC_IRQSTAT_CCE.
+#define BM_SDHC_IRQSTAT_CCE (0x00020000U) //!< Bit mask for SDHC_IRQSTAT_CCE.
+#define BS_SDHC_IRQSTAT_CCE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_CCE field.
+#define BR_SDHC_IRQSTAT_CCE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CCE))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_CCE.
+#define BF_SDHC_IRQSTAT_CCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CCE), uint32_t) & BM_SDHC_IRQSTAT_CCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCE field to a new value.
+#define BW_SDHC_IRQSTAT_CCE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CEBE[18] (W1C)
+ *
+ * Occurs when detecting that the end bit of a command response is 0.
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - End Bit Error generated.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_CEBE (18U) //!< Bit position for SDHC_IRQSTAT_CEBE.
+#define BM_SDHC_IRQSTAT_CEBE (0x00040000U) //!< Bit mask for SDHC_IRQSTAT_CEBE.
+#define BS_SDHC_IRQSTAT_CEBE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CEBE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_CEBE field.
+#define BR_SDHC_IRQSTAT_CEBE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CEBE))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_CEBE.
+#define BF_SDHC_IRQSTAT_CEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CEBE), uint32_t) & BM_SDHC_IRQSTAT_CEBE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CEBE field to a new value.
+#define BW_SDHC_IRQSTAT_CEBE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CEBE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CIE[19] (W1C)
+ *
+ * Occurs if a Command Index error occurs in the command response.
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - Error.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_CIE (19U) //!< Bit position for SDHC_IRQSTAT_CIE.
+#define BM_SDHC_IRQSTAT_CIE (0x00080000U) //!< Bit mask for SDHC_IRQSTAT_CIE.
+#define BS_SDHC_IRQSTAT_CIE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_CIE field.
+#define BR_SDHC_IRQSTAT_CIE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CIE))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_CIE.
+#define BF_SDHC_IRQSTAT_CIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CIE), uint32_t) & BM_SDHC_IRQSTAT_CIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CIE field to a new value.
+#define BW_SDHC_IRQSTAT_CIE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DTOE[20] (W1C)
+ *
+ * Occurs when detecting one of following time-out conditions. Busy time-out for
+ * R1b,R5b type Busy time-out after Write CRC status Read Data time-out
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - Time out.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_DTOE (20U) //!< Bit position for SDHC_IRQSTAT_DTOE.
+#define BM_SDHC_IRQSTAT_DTOE (0x00100000U) //!< Bit mask for SDHC_IRQSTAT_DTOE.
+#define BS_SDHC_IRQSTAT_DTOE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_DTOE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_DTOE field.
+#define BR_SDHC_IRQSTAT_DTOE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DTOE))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_DTOE.
+#define BF_SDHC_IRQSTAT_DTOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_DTOE), uint32_t) & BM_SDHC_IRQSTAT_DTOE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DTOE field to a new value.
+#define BW_SDHC_IRQSTAT_DTOE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DTOE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DCE[21] (W1C)
+ *
+ * Occurs when detecting a CRC error when transferring read data, which uses the
+ * DAT line, or when detecting the Write CRC status having a value other than
+ * 010.
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - Error.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_DCE (21U) //!< Bit position for SDHC_IRQSTAT_DCE.
+#define BM_SDHC_IRQSTAT_DCE (0x00200000U) //!< Bit mask for SDHC_IRQSTAT_DCE.
+#define BS_SDHC_IRQSTAT_DCE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_DCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_DCE field.
+#define BR_SDHC_IRQSTAT_DCE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DCE))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_DCE.
+#define BF_SDHC_IRQSTAT_DCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_DCE), uint32_t) & BM_SDHC_IRQSTAT_DCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DCE field to a new value.
+#define BW_SDHC_IRQSTAT_DCE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DEBE[22] (W1C)
+ *
+ * Occurs either when detecting 0 at the end bit position of read data, which
+ * uses the DAT line, or at the end bit position of the CRC.
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - Error.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_DEBE (22U) //!< Bit position for SDHC_IRQSTAT_DEBE.
+#define BM_SDHC_IRQSTAT_DEBE (0x00400000U) //!< Bit mask for SDHC_IRQSTAT_DEBE.
+#define BS_SDHC_IRQSTAT_DEBE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_DEBE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_DEBE field.
+#define BR_SDHC_IRQSTAT_DEBE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DEBE))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_DEBE.
+#define BF_SDHC_IRQSTAT_DEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_DEBE), uint32_t) & BM_SDHC_IRQSTAT_DEBE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DEBE field to a new value.
+#define BW_SDHC_IRQSTAT_DEBE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DEBE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field AC12E[24] (W1C)
+ *
+ * Occurs when detecting that one of the bits in the Auto CMD12 Error Status
+ * register has changed from 0 to 1. This bit is set to 1, not only when the errors
+ * in Auto CMD12 occur, but also when the Auto CMD12 is not executed due to the
+ * previous command error.
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - Error.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_AC12E (24U) //!< Bit position for SDHC_IRQSTAT_AC12E.
+#define BM_SDHC_IRQSTAT_AC12E (0x01000000U) //!< Bit mask for SDHC_IRQSTAT_AC12E.
+#define BS_SDHC_IRQSTAT_AC12E (1U) //!< Bit field size in bits for SDHC_IRQSTAT_AC12E.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_AC12E field.
+#define BR_SDHC_IRQSTAT_AC12E (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_AC12E))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_AC12E.
+#define BF_SDHC_IRQSTAT_AC12E(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_AC12E), uint32_t) & BM_SDHC_IRQSTAT_AC12E)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AC12E field to a new value.
+#define BW_SDHC_IRQSTAT_AC12E(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_AC12E) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DMAE[28] (W1C)
+ *
+ * Occurs when an Internal DMA transfer has failed. This bit is set to 1, when
+ * some error occurs in the data transfer. This error can be caused by either
+ * Simple DMA or ADMA, depending on which DMA is in use. The value in DMA System
+ * Address register is the next fetch address where the error occurs. Because any
+ * error corrupts the whole data block, the host driver shall restart the transfer
+ * from the corrupted block boundary. The address of the block boundary can be
+ * calculated either from the current DSADDR value or from the remaining number of
+ * blocks and the block size.
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - Error.
+ */
+//@{
+#define BP_SDHC_IRQSTAT_DMAE (28U) //!< Bit position for SDHC_IRQSTAT_DMAE.
+#define BM_SDHC_IRQSTAT_DMAE (0x10000000U) //!< Bit mask for SDHC_IRQSTAT_DMAE.
+#define BS_SDHC_IRQSTAT_DMAE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_DMAE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTAT_DMAE field.
+#define BR_SDHC_IRQSTAT_DMAE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DMAE))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTAT_DMAE.
+#define BF_SDHC_IRQSTAT_DMAE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_DMAE), uint32_t) & BM_SDHC_IRQSTAT_DMAE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMAE field to a new value.
+#define BW_SDHC_IRQSTAT_DMAE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DMAE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_IRQSTATEN - Interrupt Status Enable register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_IRQSTATEN - Interrupt Status Enable register (RW)
+ *
+ * Reset value: 0x117F013FU
+ *
+ * Setting the bits in this register to 1 enables the corresponding interrupt
+ * status to be set by the specified event. If any bit is cleared, the
+ * corresponding interrupt status bit is also cleared, that is, when the bit in this register
+ * is cleared, the corresponding bit in interrupt status register is always 0.
+ * Depending on PROCTL[IABG] bit setting, SDHC may be programmed to sample the
+ * card interrupt signal during the interrupt period and hold its value in the
+ * flip-flop. There will be some delays on the card interrupt, asserted from the card,
+ * to the time the host system is informed. To detect a CMD line conflict, the
+ * host driver must set both IRQSTATEN[CTOESEN] and IRQSTATEN[CCESEN] to 1.
+ */
+typedef union _hw_sdhc_irqstaten
+{
+ uint32_t U;
+ struct _hw_sdhc_irqstaten_bitfields
+ {
+ uint32_t CCSEN : 1; //!< [0] Command Complete Status Enable
+ uint32_t TCSEN : 1; //!< [1] Transfer Complete Status Enable
+ uint32_t BGESEN : 1; //!< [2] Block Gap Event Status Enable
+ uint32_t DINTSEN : 1; //!< [3] DMA Interrupt Status Enable
+ uint32_t BWRSEN : 1; //!< [4] Buffer Write Ready Status Enable
+ uint32_t BRRSEN : 1; //!< [5] Buffer Read Ready Status Enable
+ uint32_t CINSEN : 1; //!< [6] Card Insertion Status Enable
+ uint32_t CRMSEN : 1; //!< [7] Card Removal Status Enable
+ uint32_t CINTSEN : 1; //!< [8] Card Interrupt Status Enable
+ uint32_t RESERVED0 : 7; //!< [15:9]
+ uint32_t CTOESEN : 1; //!< [16] Command Timeout Error Status Enable
+ uint32_t CCESEN : 1; //!< [17] Command CRC Error Status Enable
+ uint32_t CEBESEN : 1; //!< [18] Command End Bit Error Status Enable
+ uint32_t CIESEN : 1; //!< [19] Command Index Error Status Enable
+ uint32_t DTOESEN : 1; //!< [20] Data Timeout Error Status Enable
+ uint32_t DCESEN : 1; //!< [21] Data CRC Error Status Enable
+ uint32_t DEBESEN : 1; //!< [22] Data End Bit Error Status Enable
+ uint32_t RESERVED1 : 1; //!< [23]
+ uint32_t AC12ESEN : 1; //!< [24] Auto CMD12 Error Status Enable
+ uint32_t RESERVED2 : 3; //!< [27:25]
+ uint32_t DMAESEN : 1; //!< [28] DMA Error Status Enable
+ uint32_t RESERVED3 : 3; //!< [31:29]
+ } B;
+} hw_sdhc_irqstaten_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_IRQSTATEN register
+ */
+//@{
+#define HW_SDHC_IRQSTATEN_ADDR (REGS_SDHC_BASE + 0x34U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_IRQSTATEN (*(__IO hw_sdhc_irqstaten_t *) HW_SDHC_IRQSTATEN_ADDR)
+#define HW_SDHC_IRQSTATEN_RD() (HW_SDHC_IRQSTATEN.U)
+#define HW_SDHC_IRQSTATEN_WR(v) (HW_SDHC_IRQSTATEN.U = (v))
+#define HW_SDHC_IRQSTATEN_SET(v) (HW_SDHC_IRQSTATEN_WR(HW_SDHC_IRQSTATEN_RD() | (v)))
+#define HW_SDHC_IRQSTATEN_CLR(v) (HW_SDHC_IRQSTATEN_WR(HW_SDHC_IRQSTATEN_RD() & ~(v)))
+#define HW_SDHC_IRQSTATEN_TOG(v) (HW_SDHC_IRQSTATEN_WR(HW_SDHC_IRQSTATEN_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_IRQSTATEN bitfields
+ */
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CCSEN[0] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_CCSEN (0U) //!< Bit position for SDHC_IRQSTATEN_CCSEN.
+#define BM_SDHC_IRQSTATEN_CCSEN (0x00000001U) //!< Bit mask for SDHC_IRQSTATEN_CCSEN.
+#define BS_SDHC_IRQSTATEN_CCSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CCSEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_CCSEN field.
+#define BR_SDHC_IRQSTATEN_CCSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CCSEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_CCSEN.
+#define BF_SDHC_IRQSTATEN_CCSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CCSEN), uint32_t) & BM_SDHC_IRQSTATEN_CCSEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCSEN field to a new value.
+#define BW_SDHC_IRQSTATEN_CCSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CCSEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field TCSEN[1] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_TCSEN (1U) //!< Bit position for SDHC_IRQSTATEN_TCSEN.
+#define BM_SDHC_IRQSTATEN_TCSEN (0x00000002U) //!< Bit mask for SDHC_IRQSTATEN_TCSEN.
+#define BS_SDHC_IRQSTATEN_TCSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_TCSEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_TCSEN field.
+#define BR_SDHC_IRQSTATEN_TCSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_TCSEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_TCSEN.
+#define BF_SDHC_IRQSTATEN_TCSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_TCSEN), uint32_t) & BM_SDHC_IRQSTATEN_TCSEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCSEN field to a new value.
+#define BW_SDHC_IRQSTATEN_TCSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_TCSEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field BGESEN[2] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_BGESEN (2U) //!< Bit position for SDHC_IRQSTATEN_BGESEN.
+#define BM_SDHC_IRQSTATEN_BGESEN (0x00000004U) //!< Bit mask for SDHC_IRQSTATEN_BGESEN.
+#define BS_SDHC_IRQSTATEN_BGESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_BGESEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_BGESEN field.
+#define BR_SDHC_IRQSTATEN_BGESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BGESEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_BGESEN.
+#define BF_SDHC_IRQSTATEN_BGESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_BGESEN), uint32_t) & BM_SDHC_IRQSTATEN_BGESEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BGESEN field to a new value.
+#define BW_SDHC_IRQSTATEN_BGESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BGESEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DINTSEN[3] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_DINTSEN (3U) //!< Bit position for SDHC_IRQSTATEN_DINTSEN.
+#define BM_SDHC_IRQSTATEN_DINTSEN (0x00000008U) //!< Bit mask for SDHC_IRQSTATEN_DINTSEN.
+#define BS_SDHC_IRQSTATEN_DINTSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_DINTSEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_DINTSEN field.
+#define BR_SDHC_IRQSTATEN_DINTSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DINTSEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_DINTSEN.
+#define BF_SDHC_IRQSTATEN_DINTSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_DINTSEN), uint32_t) & BM_SDHC_IRQSTATEN_DINTSEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DINTSEN field to a new value.
+#define BW_SDHC_IRQSTATEN_DINTSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DINTSEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field BWRSEN[4] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_BWRSEN (4U) //!< Bit position for SDHC_IRQSTATEN_BWRSEN.
+#define BM_SDHC_IRQSTATEN_BWRSEN (0x00000010U) //!< Bit mask for SDHC_IRQSTATEN_BWRSEN.
+#define BS_SDHC_IRQSTATEN_BWRSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_BWRSEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_BWRSEN field.
+#define BR_SDHC_IRQSTATEN_BWRSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BWRSEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_BWRSEN.
+#define BF_SDHC_IRQSTATEN_BWRSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_BWRSEN), uint32_t) & BM_SDHC_IRQSTATEN_BWRSEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BWRSEN field to a new value.
+#define BW_SDHC_IRQSTATEN_BWRSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BWRSEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field BRRSEN[5] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_BRRSEN (5U) //!< Bit position for SDHC_IRQSTATEN_BRRSEN.
+#define BM_SDHC_IRQSTATEN_BRRSEN (0x00000020U) //!< Bit mask for SDHC_IRQSTATEN_BRRSEN.
+#define BS_SDHC_IRQSTATEN_BRRSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_BRRSEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_BRRSEN field.
+#define BR_SDHC_IRQSTATEN_BRRSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BRRSEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_BRRSEN.
+#define BF_SDHC_IRQSTATEN_BRRSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_BRRSEN), uint32_t) & BM_SDHC_IRQSTATEN_BRRSEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BRRSEN field to a new value.
+#define BW_SDHC_IRQSTATEN_BRRSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BRRSEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CINSEN[6] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_CINSEN (6U) //!< Bit position for SDHC_IRQSTATEN_CINSEN.
+#define BM_SDHC_IRQSTATEN_CINSEN (0x00000040U) //!< Bit mask for SDHC_IRQSTATEN_CINSEN.
+#define BS_SDHC_IRQSTATEN_CINSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CINSEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_CINSEN field.
+#define BR_SDHC_IRQSTATEN_CINSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CINSEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_CINSEN.
+#define BF_SDHC_IRQSTATEN_CINSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CINSEN), uint32_t) & BM_SDHC_IRQSTATEN_CINSEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CINSEN field to a new value.
+#define BW_SDHC_IRQSTATEN_CINSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CINSEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CRMSEN[7] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_CRMSEN (7U) //!< Bit position for SDHC_IRQSTATEN_CRMSEN.
+#define BM_SDHC_IRQSTATEN_CRMSEN (0x00000080U) //!< Bit mask for SDHC_IRQSTATEN_CRMSEN.
+#define BS_SDHC_IRQSTATEN_CRMSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CRMSEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_CRMSEN field.
+#define BR_SDHC_IRQSTATEN_CRMSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CRMSEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_CRMSEN.
+#define BF_SDHC_IRQSTATEN_CRMSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CRMSEN), uint32_t) & BM_SDHC_IRQSTATEN_CRMSEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CRMSEN field to a new value.
+#define BW_SDHC_IRQSTATEN_CRMSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CRMSEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CINTSEN[8] (RW)
+ *
+ * If this bit is set to 0, the SDHC will clear the interrupt request to the
+ * system. The card interrupt detection is stopped when this bit is cleared and
+ * restarted when this bit is set to 1. The host driver must clear the this bit
+ * before servicing the card interrupt and must set this bit again after all interrupt
+ * requests from the card are cleared to prevent inadvertent interrupts.
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_CINTSEN (8U) //!< Bit position for SDHC_IRQSTATEN_CINTSEN.
+#define BM_SDHC_IRQSTATEN_CINTSEN (0x00000100U) //!< Bit mask for SDHC_IRQSTATEN_CINTSEN.
+#define BS_SDHC_IRQSTATEN_CINTSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CINTSEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_CINTSEN field.
+#define BR_SDHC_IRQSTATEN_CINTSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CINTSEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_CINTSEN.
+#define BF_SDHC_IRQSTATEN_CINTSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CINTSEN), uint32_t) & BM_SDHC_IRQSTATEN_CINTSEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CINTSEN field to a new value.
+#define BW_SDHC_IRQSTATEN_CINTSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CINTSEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CTOESEN[16] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_CTOESEN (16U) //!< Bit position for SDHC_IRQSTATEN_CTOESEN.
+#define BM_SDHC_IRQSTATEN_CTOESEN (0x00010000U) //!< Bit mask for SDHC_IRQSTATEN_CTOESEN.
+#define BS_SDHC_IRQSTATEN_CTOESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CTOESEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_CTOESEN field.
+#define BR_SDHC_IRQSTATEN_CTOESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CTOESEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_CTOESEN.
+#define BF_SDHC_IRQSTATEN_CTOESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CTOESEN), uint32_t) & BM_SDHC_IRQSTATEN_CTOESEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CTOESEN field to a new value.
+#define BW_SDHC_IRQSTATEN_CTOESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CTOESEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CCESEN[17] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_CCESEN (17U) //!< Bit position for SDHC_IRQSTATEN_CCESEN.
+#define BM_SDHC_IRQSTATEN_CCESEN (0x00020000U) //!< Bit mask for SDHC_IRQSTATEN_CCESEN.
+#define BS_SDHC_IRQSTATEN_CCESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CCESEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_CCESEN field.
+#define BR_SDHC_IRQSTATEN_CCESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CCESEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_CCESEN.
+#define BF_SDHC_IRQSTATEN_CCESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CCESEN), uint32_t) & BM_SDHC_IRQSTATEN_CCESEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCESEN field to a new value.
+#define BW_SDHC_IRQSTATEN_CCESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CCESEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CEBESEN[18] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_CEBESEN (18U) //!< Bit position for SDHC_IRQSTATEN_CEBESEN.
+#define BM_SDHC_IRQSTATEN_CEBESEN (0x00040000U) //!< Bit mask for SDHC_IRQSTATEN_CEBESEN.
+#define BS_SDHC_IRQSTATEN_CEBESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CEBESEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_CEBESEN field.
+#define BR_SDHC_IRQSTATEN_CEBESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CEBESEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_CEBESEN.
+#define BF_SDHC_IRQSTATEN_CEBESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CEBESEN), uint32_t) & BM_SDHC_IRQSTATEN_CEBESEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CEBESEN field to a new value.
+#define BW_SDHC_IRQSTATEN_CEBESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CEBESEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CIESEN[19] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_CIESEN (19U) //!< Bit position for SDHC_IRQSTATEN_CIESEN.
+#define BM_SDHC_IRQSTATEN_CIESEN (0x00080000U) //!< Bit mask for SDHC_IRQSTATEN_CIESEN.
+#define BS_SDHC_IRQSTATEN_CIESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CIESEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_CIESEN field.
+#define BR_SDHC_IRQSTATEN_CIESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CIESEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_CIESEN.
+#define BF_SDHC_IRQSTATEN_CIESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CIESEN), uint32_t) & BM_SDHC_IRQSTATEN_CIESEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CIESEN field to a new value.
+#define BW_SDHC_IRQSTATEN_CIESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CIESEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DTOESEN[20] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_DTOESEN (20U) //!< Bit position for SDHC_IRQSTATEN_DTOESEN.
+#define BM_SDHC_IRQSTATEN_DTOESEN (0x00100000U) //!< Bit mask for SDHC_IRQSTATEN_DTOESEN.
+#define BS_SDHC_IRQSTATEN_DTOESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_DTOESEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_DTOESEN field.
+#define BR_SDHC_IRQSTATEN_DTOESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DTOESEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_DTOESEN.
+#define BF_SDHC_IRQSTATEN_DTOESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_DTOESEN), uint32_t) & BM_SDHC_IRQSTATEN_DTOESEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DTOESEN field to a new value.
+#define BW_SDHC_IRQSTATEN_DTOESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DTOESEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DCESEN[21] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_DCESEN (21U) //!< Bit position for SDHC_IRQSTATEN_DCESEN.
+#define BM_SDHC_IRQSTATEN_DCESEN (0x00200000U) //!< Bit mask for SDHC_IRQSTATEN_DCESEN.
+#define BS_SDHC_IRQSTATEN_DCESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_DCESEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_DCESEN field.
+#define BR_SDHC_IRQSTATEN_DCESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DCESEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_DCESEN.
+#define BF_SDHC_IRQSTATEN_DCESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_DCESEN), uint32_t) & BM_SDHC_IRQSTATEN_DCESEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DCESEN field to a new value.
+#define BW_SDHC_IRQSTATEN_DCESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DCESEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DEBESEN[22] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_DEBESEN (22U) //!< Bit position for SDHC_IRQSTATEN_DEBESEN.
+#define BM_SDHC_IRQSTATEN_DEBESEN (0x00400000U) //!< Bit mask for SDHC_IRQSTATEN_DEBESEN.
+#define BS_SDHC_IRQSTATEN_DEBESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_DEBESEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_DEBESEN field.
+#define BR_SDHC_IRQSTATEN_DEBESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DEBESEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_DEBESEN.
+#define BF_SDHC_IRQSTATEN_DEBESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_DEBESEN), uint32_t) & BM_SDHC_IRQSTATEN_DEBESEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DEBESEN field to a new value.
+#define BW_SDHC_IRQSTATEN_DEBESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DEBESEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field AC12ESEN[24] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_AC12ESEN (24U) //!< Bit position for SDHC_IRQSTATEN_AC12ESEN.
+#define BM_SDHC_IRQSTATEN_AC12ESEN (0x01000000U) //!< Bit mask for SDHC_IRQSTATEN_AC12ESEN.
+#define BS_SDHC_IRQSTATEN_AC12ESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_AC12ESEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_AC12ESEN field.
+#define BR_SDHC_IRQSTATEN_AC12ESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_AC12ESEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_AC12ESEN.
+#define BF_SDHC_IRQSTATEN_AC12ESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_AC12ESEN), uint32_t) & BM_SDHC_IRQSTATEN_AC12ESEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AC12ESEN field to a new value.
+#define BW_SDHC_IRQSTATEN_AC12ESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_AC12ESEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DMAESEN[28] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSTATEN_DMAESEN (28U) //!< Bit position for SDHC_IRQSTATEN_DMAESEN.
+#define BM_SDHC_IRQSTATEN_DMAESEN (0x10000000U) //!< Bit mask for SDHC_IRQSTATEN_DMAESEN.
+#define BS_SDHC_IRQSTATEN_DMAESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_DMAESEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSTATEN_DMAESEN field.
+#define BR_SDHC_IRQSTATEN_DMAESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DMAESEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSTATEN_DMAESEN.
+#define BF_SDHC_IRQSTATEN_DMAESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_DMAESEN), uint32_t) & BM_SDHC_IRQSTATEN_DMAESEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMAESEN field to a new value.
+#define BW_SDHC_IRQSTATEN_DMAESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DMAESEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_IRQSIGEN - Interrupt Signal Enable register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_IRQSIGEN - Interrupt Signal Enable register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to select which interrupt status is indicated to the
+ * host system as the interrupt. All of these status bits share the same interrupt
+ * line. Setting any of these bits to 1 enables interrupt generation. The
+ * corresponding status register bit will generate an interrupt when the corresponding
+ * interrupt signal enable bit is set.
+ */
+typedef union _hw_sdhc_irqsigen
+{
+ uint32_t U;
+ struct _hw_sdhc_irqsigen_bitfields
+ {
+ uint32_t CCIEN : 1; //!< [0] Command Complete Interrupt Enable
+ uint32_t TCIEN : 1; //!< [1] Transfer Complete Interrupt Enable
+ uint32_t BGEIEN : 1; //!< [2] Block Gap Event Interrupt Enable
+ uint32_t DINTIEN : 1; //!< [3] DMA Interrupt Enable
+ uint32_t BWRIEN : 1; //!< [4] Buffer Write Ready Interrupt Enable
+ uint32_t BRRIEN : 1; //!< [5] Buffer Read Ready Interrupt Enable
+ uint32_t CINSIEN : 1; //!< [6] Card Insertion Interrupt Enable
+ uint32_t CRMIEN : 1; //!< [7] Card Removal Interrupt Enable
+ uint32_t CINTIEN : 1; //!< [8] Card Interrupt Enable
+ uint32_t RESERVED0 : 7; //!< [15:9]
+ uint32_t CTOEIEN : 1; //!< [16] Command Timeout Error Interrupt Enable
+ uint32_t CCEIEN : 1; //!< [17] Command CRC Error Interrupt Enable
+ uint32_t CEBEIEN : 1; //!< [18] Command End Bit Error Interrupt Enable
+ uint32_t CIEIEN : 1; //!< [19] Command Index Error Interrupt Enable
+ uint32_t DTOEIEN : 1; //!< [20] Data Timeout Error Interrupt Enable
+ uint32_t DCEIEN : 1; //!< [21] Data CRC Error Interrupt Enable
+ uint32_t DEBEIEN : 1; //!< [22] Data End Bit Error Interrupt Enable
+ uint32_t RESERVED1 : 1; //!< [23]
+ uint32_t AC12EIEN : 1; //!< [24] Auto CMD12 Error Interrupt Enable
+ uint32_t RESERVED2 : 3; //!< [27:25]
+ uint32_t DMAEIEN : 1; //!< [28] DMA Error Interrupt Enable
+ uint32_t RESERVED3 : 3; //!< [31:29]
+ } B;
+} hw_sdhc_irqsigen_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_IRQSIGEN register
+ */
+//@{
+#define HW_SDHC_IRQSIGEN_ADDR (REGS_SDHC_BASE + 0x38U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_IRQSIGEN (*(__IO hw_sdhc_irqsigen_t *) HW_SDHC_IRQSIGEN_ADDR)
+#define HW_SDHC_IRQSIGEN_RD() (HW_SDHC_IRQSIGEN.U)
+#define HW_SDHC_IRQSIGEN_WR(v) (HW_SDHC_IRQSIGEN.U = (v))
+#define HW_SDHC_IRQSIGEN_SET(v) (HW_SDHC_IRQSIGEN_WR(HW_SDHC_IRQSIGEN_RD() | (v)))
+#define HW_SDHC_IRQSIGEN_CLR(v) (HW_SDHC_IRQSIGEN_WR(HW_SDHC_IRQSIGEN_RD() & ~(v)))
+#define HW_SDHC_IRQSIGEN_TOG(v) (HW_SDHC_IRQSIGEN_WR(HW_SDHC_IRQSIGEN_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_IRQSIGEN bitfields
+ */
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CCIEN[0] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_CCIEN (0U) //!< Bit position for SDHC_IRQSIGEN_CCIEN.
+#define BM_SDHC_IRQSIGEN_CCIEN (0x00000001U) //!< Bit mask for SDHC_IRQSIGEN_CCIEN.
+#define BS_SDHC_IRQSIGEN_CCIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CCIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_CCIEN field.
+#define BR_SDHC_IRQSIGEN_CCIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CCIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_CCIEN.
+#define BF_SDHC_IRQSIGEN_CCIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CCIEN), uint32_t) & BM_SDHC_IRQSIGEN_CCIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_CCIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CCIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field TCIEN[1] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_TCIEN (1U) //!< Bit position for SDHC_IRQSIGEN_TCIEN.
+#define BM_SDHC_IRQSIGEN_TCIEN (0x00000002U) //!< Bit mask for SDHC_IRQSIGEN_TCIEN.
+#define BS_SDHC_IRQSIGEN_TCIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_TCIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_TCIEN field.
+#define BR_SDHC_IRQSIGEN_TCIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_TCIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_TCIEN.
+#define BF_SDHC_IRQSIGEN_TCIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_TCIEN), uint32_t) & BM_SDHC_IRQSIGEN_TCIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_TCIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_TCIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field BGEIEN[2] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_BGEIEN (2U) //!< Bit position for SDHC_IRQSIGEN_BGEIEN.
+#define BM_SDHC_IRQSIGEN_BGEIEN (0x00000004U) //!< Bit mask for SDHC_IRQSIGEN_BGEIEN.
+#define BS_SDHC_IRQSIGEN_BGEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_BGEIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_BGEIEN field.
+#define BR_SDHC_IRQSIGEN_BGEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BGEIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_BGEIEN.
+#define BF_SDHC_IRQSIGEN_BGEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_BGEIEN), uint32_t) & BM_SDHC_IRQSIGEN_BGEIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BGEIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_BGEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BGEIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DINTIEN[3] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_DINTIEN (3U) //!< Bit position for SDHC_IRQSIGEN_DINTIEN.
+#define BM_SDHC_IRQSIGEN_DINTIEN (0x00000008U) //!< Bit mask for SDHC_IRQSIGEN_DINTIEN.
+#define BS_SDHC_IRQSIGEN_DINTIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_DINTIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_DINTIEN field.
+#define BR_SDHC_IRQSIGEN_DINTIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DINTIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_DINTIEN.
+#define BF_SDHC_IRQSIGEN_DINTIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_DINTIEN), uint32_t) & BM_SDHC_IRQSIGEN_DINTIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DINTIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_DINTIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DINTIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field BWRIEN[4] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_BWRIEN (4U) //!< Bit position for SDHC_IRQSIGEN_BWRIEN.
+#define BM_SDHC_IRQSIGEN_BWRIEN (0x00000010U) //!< Bit mask for SDHC_IRQSIGEN_BWRIEN.
+#define BS_SDHC_IRQSIGEN_BWRIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_BWRIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_BWRIEN field.
+#define BR_SDHC_IRQSIGEN_BWRIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BWRIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_BWRIEN.
+#define BF_SDHC_IRQSIGEN_BWRIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_BWRIEN), uint32_t) & BM_SDHC_IRQSIGEN_BWRIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BWRIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_BWRIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BWRIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field BRRIEN[5] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_BRRIEN (5U) //!< Bit position for SDHC_IRQSIGEN_BRRIEN.
+#define BM_SDHC_IRQSIGEN_BRRIEN (0x00000020U) //!< Bit mask for SDHC_IRQSIGEN_BRRIEN.
+#define BS_SDHC_IRQSIGEN_BRRIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_BRRIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_BRRIEN field.
+#define BR_SDHC_IRQSIGEN_BRRIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BRRIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_BRRIEN.
+#define BF_SDHC_IRQSIGEN_BRRIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_BRRIEN), uint32_t) & BM_SDHC_IRQSIGEN_BRRIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BRRIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_BRRIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BRRIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CINSIEN[6] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_CINSIEN (6U) //!< Bit position for SDHC_IRQSIGEN_CINSIEN.
+#define BM_SDHC_IRQSIGEN_CINSIEN (0x00000040U) //!< Bit mask for SDHC_IRQSIGEN_CINSIEN.
+#define BS_SDHC_IRQSIGEN_CINSIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CINSIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_CINSIEN field.
+#define BR_SDHC_IRQSIGEN_CINSIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CINSIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_CINSIEN.
+#define BF_SDHC_IRQSIGEN_CINSIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CINSIEN), uint32_t) & BM_SDHC_IRQSIGEN_CINSIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CINSIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_CINSIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CINSIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CRMIEN[7] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_CRMIEN (7U) //!< Bit position for SDHC_IRQSIGEN_CRMIEN.
+#define BM_SDHC_IRQSIGEN_CRMIEN (0x00000080U) //!< Bit mask for SDHC_IRQSIGEN_CRMIEN.
+#define BS_SDHC_IRQSIGEN_CRMIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CRMIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_CRMIEN field.
+#define BR_SDHC_IRQSIGEN_CRMIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CRMIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_CRMIEN.
+#define BF_SDHC_IRQSIGEN_CRMIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CRMIEN), uint32_t) & BM_SDHC_IRQSIGEN_CRMIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CRMIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_CRMIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CRMIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CINTIEN[8] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_CINTIEN (8U) //!< Bit position for SDHC_IRQSIGEN_CINTIEN.
+#define BM_SDHC_IRQSIGEN_CINTIEN (0x00000100U) //!< Bit mask for SDHC_IRQSIGEN_CINTIEN.
+#define BS_SDHC_IRQSIGEN_CINTIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CINTIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_CINTIEN field.
+#define BR_SDHC_IRQSIGEN_CINTIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CINTIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_CINTIEN.
+#define BF_SDHC_IRQSIGEN_CINTIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CINTIEN), uint32_t) & BM_SDHC_IRQSIGEN_CINTIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CINTIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_CINTIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CINTIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CTOEIEN[16] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_CTOEIEN (16U) //!< Bit position for SDHC_IRQSIGEN_CTOEIEN.
+#define BM_SDHC_IRQSIGEN_CTOEIEN (0x00010000U) //!< Bit mask for SDHC_IRQSIGEN_CTOEIEN.
+#define BS_SDHC_IRQSIGEN_CTOEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CTOEIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_CTOEIEN field.
+#define BR_SDHC_IRQSIGEN_CTOEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CTOEIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_CTOEIEN.
+#define BF_SDHC_IRQSIGEN_CTOEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CTOEIEN), uint32_t) & BM_SDHC_IRQSIGEN_CTOEIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CTOEIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_CTOEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CTOEIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CCEIEN[17] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_CCEIEN (17U) //!< Bit position for SDHC_IRQSIGEN_CCEIEN.
+#define BM_SDHC_IRQSIGEN_CCEIEN (0x00020000U) //!< Bit mask for SDHC_IRQSIGEN_CCEIEN.
+#define BS_SDHC_IRQSIGEN_CCEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CCEIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_CCEIEN field.
+#define BR_SDHC_IRQSIGEN_CCEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CCEIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_CCEIEN.
+#define BF_SDHC_IRQSIGEN_CCEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CCEIEN), uint32_t) & BM_SDHC_IRQSIGEN_CCEIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCEIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_CCEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CCEIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CEBEIEN[18] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_CEBEIEN (18U) //!< Bit position for SDHC_IRQSIGEN_CEBEIEN.
+#define BM_SDHC_IRQSIGEN_CEBEIEN (0x00040000U) //!< Bit mask for SDHC_IRQSIGEN_CEBEIEN.
+#define BS_SDHC_IRQSIGEN_CEBEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CEBEIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_CEBEIEN field.
+#define BR_SDHC_IRQSIGEN_CEBEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CEBEIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_CEBEIEN.
+#define BF_SDHC_IRQSIGEN_CEBEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CEBEIEN), uint32_t) & BM_SDHC_IRQSIGEN_CEBEIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CEBEIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_CEBEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CEBEIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CIEIEN[19] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_CIEIEN (19U) //!< Bit position for SDHC_IRQSIGEN_CIEIEN.
+#define BM_SDHC_IRQSIGEN_CIEIEN (0x00080000U) //!< Bit mask for SDHC_IRQSIGEN_CIEIEN.
+#define BS_SDHC_IRQSIGEN_CIEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CIEIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_CIEIEN field.
+#define BR_SDHC_IRQSIGEN_CIEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CIEIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_CIEIEN.
+#define BF_SDHC_IRQSIGEN_CIEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CIEIEN), uint32_t) & BM_SDHC_IRQSIGEN_CIEIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CIEIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_CIEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CIEIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DTOEIEN[20] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_DTOEIEN (20U) //!< Bit position for SDHC_IRQSIGEN_DTOEIEN.
+#define BM_SDHC_IRQSIGEN_DTOEIEN (0x00100000U) //!< Bit mask for SDHC_IRQSIGEN_DTOEIEN.
+#define BS_SDHC_IRQSIGEN_DTOEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_DTOEIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_DTOEIEN field.
+#define BR_SDHC_IRQSIGEN_DTOEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DTOEIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_DTOEIEN.
+#define BF_SDHC_IRQSIGEN_DTOEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_DTOEIEN), uint32_t) & BM_SDHC_IRQSIGEN_DTOEIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DTOEIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_DTOEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DTOEIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DCEIEN[21] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_DCEIEN (21U) //!< Bit position for SDHC_IRQSIGEN_DCEIEN.
+#define BM_SDHC_IRQSIGEN_DCEIEN (0x00200000U) //!< Bit mask for SDHC_IRQSIGEN_DCEIEN.
+#define BS_SDHC_IRQSIGEN_DCEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_DCEIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_DCEIEN field.
+#define BR_SDHC_IRQSIGEN_DCEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DCEIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_DCEIEN.
+#define BF_SDHC_IRQSIGEN_DCEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_DCEIEN), uint32_t) & BM_SDHC_IRQSIGEN_DCEIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DCEIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_DCEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DCEIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DEBEIEN[22] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_DEBEIEN (22U) //!< Bit position for SDHC_IRQSIGEN_DEBEIEN.
+#define BM_SDHC_IRQSIGEN_DEBEIEN (0x00400000U) //!< Bit mask for SDHC_IRQSIGEN_DEBEIEN.
+#define BS_SDHC_IRQSIGEN_DEBEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_DEBEIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_DEBEIEN field.
+#define BR_SDHC_IRQSIGEN_DEBEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DEBEIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_DEBEIEN.
+#define BF_SDHC_IRQSIGEN_DEBEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_DEBEIEN), uint32_t) & BM_SDHC_IRQSIGEN_DEBEIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DEBEIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_DEBEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DEBEIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field AC12EIEN[24] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_AC12EIEN (24U) //!< Bit position for SDHC_IRQSIGEN_AC12EIEN.
+#define BM_SDHC_IRQSIGEN_AC12EIEN (0x01000000U) //!< Bit mask for SDHC_IRQSIGEN_AC12EIEN.
+#define BS_SDHC_IRQSIGEN_AC12EIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_AC12EIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_AC12EIEN field.
+#define BR_SDHC_IRQSIGEN_AC12EIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_AC12EIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_AC12EIEN.
+#define BF_SDHC_IRQSIGEN_AC12EIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_AC12EIEN), uint32_t) & BM_SDHC_IRQSIGEN_AC12EIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AC12EIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_AC12EIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_AC12EIEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DMAEIEN[28] (RW)
+ *
+ * Values:
+ * - 0 - Masked
+ * - 1 - Enabled
+ */
+//@{
+#define BP_SDHC_IRQSIGEN_DMAEIEN (28U) //!< Bit position for SDHC_IRQSIGEN_DMAEIEN.
+#define BM_SDHC_IRQSIGEN_DMAEIEN (0x10000000U) //!< Bit mask for SDHC_IRQSIGEN_DMAEIEN.
+#define BS_SDHC_IRQSIGEN_DMAEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_DMAEIEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_IRQSIGEN_DMAEIEN field.
+#define BR_SDHC_IRQSIGEN_DMAEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DMAEIEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_IRQSIGEN_DMAEIEN.
+#define BF_SDHC_IRQSIGEN_DMAEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_DMAEIEN), uint32_t) & BM_SDHC_IRQSIGEN_DMAEIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMAEIEN field to a new value.
+#define BW_SDHC_IRQSIGEN_DMAEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DMAEIEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_AC12ERR - Auto CMD12 Error Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_AC12ERR - Auto CMD12 Error Status Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When the AC12ESEN bit in the Status register is set, the host driver shall
+ * check this register to identify what kind of error the Auto CMD12 indicated.
+ * This register is valid only when the Auto CMD12 Error status bit is set. The
+ * following table shows the relationship between the Auto CMGD12 CRC error and the
+ * Auto CMD12 command timeout error. Relationship between Command CRC Error and
+ * Command Timeout Error For Auto CMD12 Auto CMD12 CRC error Auto CMD12 timeout
+ * error Type of error 0 0 No error 0 1 Response timeout error 1 0 Response CRC
+ * error 1 1 CMD line conflict Changes in Auto CMD12 Error Status register can be
+ * classified in three scenarios: When the SDHC is going to issue an Auto CMD12: Set
+ * bit 0 to 1 if the Auto CMD12 can't be issued due to an error in the previous
+ * command. Set bit 0 to 0 if the auto CMD12 is issued. At the end bit of an auto
+ * CMD12 response: Check errors corresponding to bits 1-4. Set bits 1-4
+ * corresponding to detected errors. Clear bits 1-4 corresponding to detected errors.
+ * Before reading the Auto CMD12 error status bit 7: Set bit 7 to 1 if there is a
+ * command that can't be issued. Clear bit 7 if there is no command to issue. The
+ * timing for generating the auto CMD12 error and writing to the command register
+ * are asynchronous. After that, bit 7 shall be sampled when the driver is not
+ * writing to the command register. So it is suggested to read this register only
+ * when IRQSTAT[AC12E] is set. An Auto CMD12 error interrupt is generated when one
+ * of the error bits (0-4) is set to 1. The command not issued by auto CMD12
+ * error does not generate an interrupt.
+ */
+typedef union _hw_sdhc_ac12err
+{
+ uint32_t U;
+ struct _hw_sdhc_ac12err_bitfields
+ {
+ uint32_t AC12NE : 1; //!< [0] Auto CMD12 Not Executed
+ uint32_t AC12TOE : 1; //!< [1] Auto CMD12 Timeout Error
+ uint32_t AC12EBE : 1; //!< [2] Auto CMD12 End Bit Error
+ uint32_t AC12CE : 1; //!< [3] Auto CMD12 CRC Error
+ uint32_t AC12IE : 1; //!< [4] Auto CMD12 Index Error
+ uint32_t RESERVED0 : 2; //!< [6:5]
+ uint32_t CNIBAC12E : 1; //!< [7] Command Not Issued By Auto CMD12
+ //! Error
+ uint32_t RESERVED1 : 24; //!< [31:8]
+ } B;
+} hw_sdhc_ac12err_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_AC12ERR register
+ */
+//@{
+#define HW_SDHC_AC12ERR_ADDR (REGS_SDHC_BASE + 0x3CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_AC12ERR (*(__I hw_sdhc_ac12err_t *) HW_SDHC_AC12ERR_ADDR)
+#define HW_SDHC_AC12ERR_RD() (HW_SDHC_AC12ERR.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_AC12ERR bitfields
+ */
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12NE[0] (RO)
+ *
+ * If memory multiple block data transfer is not started, due to a command
+ * error, this bit is not set because it is not necessary to issue an auto CMD12.
+ * Setting this bit to 1 means the SDHC cannot issue the auto CMD12 to stop a memory
+ * multiple block data transfer due to some error. If this bit is set to 1, other
+ * error status bits (1-4) have no meaning.
+ *
+ * Values:
+ * - 0 - Executed.
+ * - 1 - Not executed.
+ */
+//@{
+#define BP_SDHC_AC12ERR_AC12NE (0U) //!< Bit position for SDHC_AC12ERR_AC12NE.
+#define BM_SDHC_AC12ERR_AC12NE (0x00000001U) //!< Bit mask for SDHC_AC12ERR_AC12NE.
+#define BS_SDHC_AC12ERR_AC12NE (1U) //!< Bit field size in bits for SDHC_AC12ERR_AC12NE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_AC12ERR_AC12NE field.
+#define BR_SDHC_AC12ERR_AC12NE (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_AC12NE))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12TOE[1] (RO)
+ *
+ * Occurs if no response is returned within 64 SDCLK cycles from the end bit of
+ * the command. If this bit is set to 1, the other error status bits (2-4) have
+ * no meaning.
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - Time out.
+ */
+//@{
+#define BP_SDHC_AC12ERR_AC12TOE (1U) //!< Bit position for SDHC_AC12ERR_AC12TOE.
+#define BM_SDHC_AC12ERR_AC12TOE (0x00000002U) //!< Bit mask for SDHC_AC12ERR_AC12TOE.
+#define BS_SDHC_AC12ERR_AC12TOE (1U) //!< Bit field size in bits for SDHC_AC12ERR_AC12TOE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_AC12ERR_AC12TOE field.
+#define BR_SDHC_AC12ERR_AC12TOE (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_AC12TOE))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12EBE[2] (RO)
+ *
+ * Occurs when detecting that the end bit of command response is 0 which must be
+ * 1.
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - End bit error generated.
+ */
+//@{
+#define BP_SDHC_AC12ERR_AC12EBE (2U) //!< Bit position for SDHC_AC12ERR_AC12EBE.
+#define BM_SDHC_AC12ERR_AC12EBE (0x00000004U) //!< Bit mask for SDHC_AC12ERR_AC12EBE.
+#define BS_SDHC_AC12ERR_AC12EBE (1U) //!< Bit field size in bits for SDHC_AC12ERR_AC12EBE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_AC12ERR_AC12EBE field.
+#define BR_SDHC_AC12ERR_AC12EBE (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_AC12EBE))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12CE[3] (RO)
+ *
+ * Occurs when detecting a CRC error in the command response.
+ *
+ * Values:
+ * - 0 - No CRC error.
+ * - 1 - CRC error met in Auto CMD12 response.
+ */
+//@{
+#define BP_SDHC_AC12ERR_AC12CE (3U) //!< Bit position for SDHC_AC12ERR_AC12CE.
+#define BM_SDHC_AC12ERR_AC12CE (0x00000008U) //!< Bit mask for SDHC_AC12ERR_AC12CE.
+#define BS_SDHC_AC12ERR_AC12CE (1U) //!< Bit field size in bits for SDHC_AC12ERR_AC12CE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_AC12ERR_AC12CE field.
+#define BR_SDHC_AC12ERR_AC12CE (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_AC12CE))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12IE[4] (RO)
+ *
+ * Occurs if the command index error occurs in response to a command.
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - Error, the CMD index in response is not CMD12.
+ */
+//@{
+#define BP_SDHC_AC12ERR_AC12IE (4U) //!< Bit position for SDHC_AC12ERR_AC12IE.
+#define BM_SDHC_AC12ERR_AC12IE (0x00000010U) //!< Bit mask for SDHC_AC12ERR_AC12IE.
+#define BS_SDHC_AC12ERR_AC12IE (1U) //!< Bit field size in bits for SDHC_AC12ERR_AC12IE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_AC12ERR_AC12IE field.
+#define BR_SDHC_AC12ERR_AC12IE (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_AC12IE))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_AC12ERR, field CNIBAC12E[7] (RO)
+ *
+ * Setting this bit to 1 means CMD_wo_DAT is not executed due to an auto CMD12
+ * error (D04-D01) in this register.
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - Not issued.
+ */
+//@{
+#define BP_SDHC_AC12ERR_CNIBAC12E (7U) //!< Bit position for SDHC_AC12ERR_CNIBAC12E.
+#define BM_SDHC_AC12ERR_CNIBAC12E (0x00000080U) //!< Bit mask for SDHC_AC12ERR_CNIBAC12E.
+#define BS_SDHC_AC12ERR_CNIBAC12E (1U) //!< Bit field size in bits for SDHC_AC12ERR_CNIBAC12E.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_AC12ERR_CNIBAC12E field.
+#define BR_SDHC_AC12ERR_CNIBAC12E (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_CNIBAC12E))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_HTCAPBLT - Host Controller Capabilities
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_HTCAPBLT - Host Controller Capabilities (RO)
+ *
+ * Reset value: 0x07F30000U
+ *
+ * This register provides the host driver with information specific to the SDHC
+ * implementation. The value in this register is the power-on-reset value, and
+ * does not change with a software reset. Any write to this register is ignored.
+ */
+typedef union _hw_sdhc_htcapblt
+{
+ uint32_t U;
+ struct _hw_sdhc_htcapblt_bitfields
+ {
+ uint32_t RESERVED0 : 16; //!< [15:0]
+ uint32_t MBL : 3; //!< [18:16] Max Block Length
+ uint32_t RESERVED1 : 1; //!< [19]
+ uint32_t ADMAS : 1; //!< [20] ADMA Support
+ uint32_t HSS : 1; //!< [21] High Speed Support
+ uint32_t DMAS : 1; //!< [22] DMA Support
+ uint32_t SRS : 1; //!< [23] Suspend/Resume Support
+ uint32_t VS33 : 1; //!< [24] Voltage Support 3.3 V
+ uint32_t RESERVED2 : 7; //!< [31:25]
+ } B;
+} hw_sdhc_htcapblt_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_HTCAPBLT register
+ */
+//@{
+#define HW_SDHC_HTCAPBLT_ADDR (REGS_SDHC_BASE + 0x40U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_HTCAPBLT (*(__I hw_sdhc_htcapblt_t *) HW_SDHC_HTCAPBLT_ADDR)
+#define HW_SDHC_HTCAPBLT_RD() (HW_SDHC_HTCAPBLT.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_HTCAPBLT bitfields
+ */
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field MBL[18:16] (RO)
+ *
+ * This value indicates the maximum block size that the host driver can read and
+ * write to the buffer in the SDHC. The buffer shall transfer block size without
+ * wait cycles.
+ *
+ * Values:
+ * - 000 - 512 bytes
+ * - 001 - 1024 bytes
+ * - 010 - 2048 bytes
+ * - 011 - 4096 bytes
+ */
+//@{
+#define BP_SDHC_HTCAPBLT_MBL (16U) //!< Bit position for SDHC_HTCAPBLT_MBL.
+#define BM_SDHC_HTCAPBLT_MBL (0x00070000U) //!< Bit mask for SDHC_HTCAPBLT_MBL.
+#define BS_SDHC_HTCAPBLT_MBL (3U) //!< Bit field size in bits for SDHC_HTCAPBLT_MBL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_HTCAPBLT_MBL field.
+#define BR_SDHC_HTCAPBLT_MBL (HW_SDHC_HTCAPBLT.B.MBL)
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field ADMAS[20] (RO)
+ *
+ * This bit indicates whether the SDHC supports the ADMA feature.
+ *
+ * Values:
+ * - 0 - Advanced DMA not supported.
+ * - 1 - Advanced DMA supported.
+ */
+//@{
+#define BP_SDHC_HTCAPBLT_ADMAS (20U) //!< Bit position for SDHC_HTCAPBLT_ADMAS.
+#define BM_SDHC_HTCAPBLT_ADMAS (0x00100000U) //!< Bit mask for SDHC_HTCAPBLT_ADMAS.
+#define BS_SDHC_HTCAPBLT_ADMAS (1U) //!< Bit field size in bits for SDHC_HTCAPBLT_ADMAS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_HTCAPBLT_ADMAS field.
+#define BR_SDHC_HTCAPBLT_ADMAS (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR, BP_SDHC_HTCAPBLT_ADMAS))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field HSS[21] (RO)
+ *
+ * This bit indicates whether the SDHC supports high speed mode and the host
+ * system can supply a SD Clock frequency from 25 MHz to 50 MHz.
+ *
+ * Values:
+ * - 0 - High speed not supported.
+ * - 1 - High speed supported.
+ */
+//@{
+#define BP_SDHC_HTCAPBLT_HSS (21U) //!< Bit position for SDHC_HTCAPBLT_HSS.
+#define BM_SDHC_HTCAPBLT_HSS (0x00200000U) //!< Bit mask for SDHC_HTCAPBLT_HSS.
+#define BS_SDHC_HTCAPBLT_HSS (1U) //!< Bit field size in bits for SDHC_HTCAPBLT_HSS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_HTCAPBLT_HSS field.
+#define BR_SDHC_HTCAPBLT_HSS (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR, BP_SDHC_HTCAPBLT_HSS))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field DMAS[22] (RO)
+ *
+ * This bit indicates whether the SDHC is capable of using the internal DMA to
+ * transfer data between system memory and the data buffer directly.
+ *
+ * Values:
+ * - 0 - DMA not supported.
+ * - 1 - DMA supported.
+ */
+//@{
+#define BP_SDHC_HTCAPBLT_DMAS (22U) //!< Bit position for SDHC_HTCAPBLT_DMAS.
+#define BM_SDHC_HTCAPBLT_DMAS (0x00400000U) //!< Bit mask for SDHC_HTCAPBLT_DMAS.
+#define BS_SDHC_HTCAPBLT_DMAS (1U) //!< Bit field size in bits for SDHC_HTCAPBLT_DMAS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_HTCAPBLT_DMAS field.
+#define BR_SDHC_HTCAPBLT_DMAS (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR, BP_SDHC_HTCAPBLT_DMAS))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field SRS[23] (RO)
+ *
+ * This bit indicates whether the SDHC supports suspend / resume functionality.
+ * If this bit is 0, the suspend and resume mechanism, as well as the read Wwait,
+ * are not supported, and the host driver shall not issue either suspend or
+ * resume commands.
+ *
+ * Values:
+ * - 0 - Not supported.
+ * - 1 - Supported.
+ */
+//@{
+#define BP_SDHC_HTCAPBLT_SRS (23U) //!< Bit position for SDHC_HTCAPBLT_SRS.
+#define BM_SDHC_HTCAPBLT_SRS (0x00800000U) //!< Bit mask for SDHC_HTCAPBLT_SRS.
+#define BS_SDHC_HTCAPBLT_SRS (1U) //!< Bit field size in bits for SDHC_HTCAPBLT_SRS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_HTCAPBLT_SRS field.
+#define BR_SDHC_HTCAPBLT_SRS (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR, BP_SDHC_HTCAPBLT_SRS))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field VS33[24] (RO)
+ *
+ * This bit shall depend on the host system ability.
+ *
+ * Values:
+ * - 0 - 3.3 V not supported.
+ * - 1 - 3.3 V supported.
+ */
+//@{
+#define BP_SDHC_HTCAPBLT_VS33 (24U) //!< Bit position for SDHC_HTCAPBLT_VS33.
+#define BM_SDHC_HTCAPBLT_VS33 (0x01000000U) //!< Bit mask for SDHC_HTCAPBLT_VS33.
+#define BS_SDHC_HTCAPBLT_VS33 (1U) //!< Bit field size in bits for SDHC_HTCAPBLT_VS33.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_HTCAPBLT_VS33 field.
+#define BR_SDHC_HTCAPBLT_VS33 (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR, BP_SDHC_HTCAPBLT_VS33))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_WML - Watermark Level Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_WML - Watermark Level Register (RW)
+ *
+ * Reset value: 0x00100010U
+ *
+ * Both write and read watermark levels (FIFO threshold) are configurable. There
+ * value can range from 1 to 128 words. Both write and read burst lengths are
+ * also configurable. There value can range from 1 to 31 words.
+ */
+typedef union _hw_sdhc_wml
+{
+ uint32_t U;
+ struct _hw_sdhc_wml_bitfields
+ {
+ uint32_t RDWML : 8; //!< [7:0] Read Watermark Level
+ uint32_t RESERVED0 : 8; //!< [15:8]
+ uint32_t WRWML : 8; //!< [23:16] Write Watermark Level
+ uint32_t RESERVED1 : 8; //!< [31:24]
+ } B;
+} hw_sdhc_wml_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_WML register
+ */
+//@{
+#define HW_SDHC_WML_ADDR (REGS_SDHC_BASE + 0x44U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_WML (*(__IO hw_sdhc_wml_t *) HW_SDHC_WML_ADDR)
+#define HW_SDHC_WML_RD() (HW_SDHC_WML.U)
+#define HW_SDHC_WML_WR(v) (HW_SDHC_WML.U = (v))
+#define HW_SDHC_WML_SET(v) (HW_SDHC_WML_WR(HW_SDHC_WML_RD() | (v)))
+#define HW_SDHC_WML_CLR(v) (HW_SDHC_WML_WR(HW_SDHC_WML_RD() & ~(v)))
+#define HW_SDHC_WML_TOG(v) (HW_SDHC_WML_WR(HW_SDHC_WML_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_WML bitfields
+ */
+
+/*!
+ * @name Register SDHC_WML, field RDWML[7:0] (RW)
+ *
+ * The number of words used as the watermark level (FIFO threshold) in a DMA
+ * read operation. Also the number of words as a sequence of read bursts in
+ * back-to-back mode. The maximum legal value for the read water mark level is 128.
+ */
+//@{
+#define BP_SDHC_WML_RDWML (0U) //!< Bit position for SDHC_WML_RDWML.
+#define BM_SDHC_WML_RDWML (0x000000FFU) //!< Bit mask for SDHC_WML_RDWML.
+#define BS_SDHC_WML_RDWML (8U) //!< Bit field size in bits for SDHC_WML_RDWML.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_WML_RDWML field.
+#define BR_SDHC_WML_RDWML (HW_SDHC_WML.B.RDWML)
+#endif
+
+//! @brief Format value for bitfield SDHC_WML_RDWML.
+#define BF_SDHC_WML_RDWML(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_WML_RDWML), uint32_t) & BM_SDHC_WML_RDWML)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RDWML field to a new value.
+#define BW_SDHC_WML_RDWML(v) (HW_SDHC_WML_WR((HW_SDHC_WML_RD() & ~BM_SDHC_WML_RDWML) | BF_SDHC_WML_RDWML(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_WML, field WRWML[23:16] (RW)
+ *
+ * The number of words used as the watermark level (FIFO threshold) in a DMA
+ * write operation. Also the number of words as a sequence of write bursts in
+ * back-to-back mode. The maximum legal value for the write watermark level is 128.
+ */
+//@{
+#define BP_SDHC_WML_WRWML (16U) //!< Bit position for SDHC_WML_WRWML.
+#define BM_SDHC_WML_WRWML (0x00FF0000U) //!< Bit mask for SDHC_WML_WRWML.
+#define BS_SDHC_WML_WRWML (8U) //!< Bit field size in bits for SDHC_WML_WRWML.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_WML_WRWML field.
+#define BR_SDHC_WML_WRWML (HW_SDHC_WML.B.WRWML)
+#endif
+
+//! @brief Format value for bitfield SDHC_WML_WRWML.
+#define BF_SDHC_WML_WRWML(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_WML_WRWML), uint32_t) & BM_SDHC_WML_WRWML)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WRWML field to a new value.
+#define BW_SDHC_WML_WRWML(v) (HW_SDHC_WML_WR((HW_SDHC_WML_RD() & ~BM_SDHC_WML_WRWML) | BF_SDHC_WML_WRWML(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_FEVT - Force Event register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_FEVT - Force Event register (WO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Force Event (FEVT) register is not a physically implemented register.
+ * Rather, it is an address at which the Interrupt Status register can be written if
+ * the corresponding bit of the Interrupt Status Enable register is set. This
+ * register is a write only register and writing 0 to it has no effect. Writing 1
+ * to this register actually sets the corresponding bit of Interrupt Status
+ * register. A read from this register always results in 0's. To change the
+ * corresponding status bits in the interrupt status register, make sure to set
+ * SYSCTL[IPGEN] so that bus clock is always active. Forcing a card interrupt will generate a
+ * short pulse on the DAT[1] line, and the driver may treat this interrupt as a
+ * normal interrupt. The interrupt service routine may skip polling the card
+ * interrupt factor as the interrupt is selfcleared.
+ */
+typedef union _hw_sdhc_fevt
+{
+ uint32_t U;
+ struct _hw_sdhc_fevt_bitfields
+ {
+ uint32_t AC12NE : 1; //!< [0] Force Event Auto Command 12 Not Executed
+ uint32_t AC12TOE : 1; //!< [1] Force Event Auto Command 12 Time Out
+ //! Error
+ uint32_t AC12CE : 1; //!< [2] Force Event Auto Command 12 CRC Error
+ uint32_t AC12EBE : 1; //!< [3] Force Event Auto Command 12 End Bit
+ //! Error
+ uint32_t AC12IE : 1; //!< [4] Force Event Auto Command 12 Index Error
+ uint32_t RESERVED0 : 2; //!< [6:5]
+ uint32_t CNIBAC12E : 1; //!< [7] Force Event Command Not Executed By
+ //! Auto Command 12 Error
+ uint32_t RESERVED1 : 8; //!< [15:8]
+ uint32_t CTOE : 1; //!< [16] Force Event Command Time Out Error
+ uint32_t CCE : 1; //!< [17] Force Event Command CRC Error
+ uint32_t CEBE : 1; //!< [18] Force Event Command End Bit Error
+ uint32_t CIE : 1; //!< [19] Force Event Command Index Error
+ uint32_t DTOE : 1; //!< [20] Force Event Data Time Out Error
+ uint32_t DCE : 1; //!< [21] Force Event Data CRC Error
+ uint32_t DEBE : 1; //!< [22] Force Event Data End Bit Error
+ uint32_t RESERVED2 : 1; //!< [23]
+ uint32_t AC12E : 1; //!< [24] Force Event Auto Command 12 Error
+ uint32_t RESERVED3 : 3; //!< [27:25]
+ uint32_t DMAE : 1; //!< [28] Force Event DMA Error
+ uint32_t RESERVED4 : 2; //!< [30:29]
+ uint32_t CINT : 1; //!< [31] Force Event Card Interrupt
+ } B;
+} hw_sdhc_fevt_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_FEVT register
+ */
+//@{
+#define HW_SDHC_FEVT_ADDR (REGS_SDHC_BASE + 0x50U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_FEVT (*(__O hw_sdhc_fevt_t *) HW_SDHC_FEVT_ADDR)
+#define HW_SDHC_FEVT_RD() (HW_SDHC_FEVT.U)
+#define HW_SDHC_FEVT_WR(v) (HW_SDHC_FEVT.U = (v))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_FEVT bitfields
+ */
+
+/*!
+ * @name Register SDHC_FEVT, field AC12NE[0] (WORZ)
+ *
+ * Forces AC12ERR[AC12NE] to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_AC12NE (0U) //!< Bit position for SDHC_FEVT_AC12NE.
+#define BM_SDHC_FEVT_AC12NE (0x00000001U) //!< Bit mask for SDHC_FEVT_AC12NE.
+#define BS_SDHC_FEVT_AC12NE (1U) //!< Bit field size in bits for SDHC_FEVT_AC12NE.
+
+//! @brief Format value for bitfield SDHC_FEVT_AC12NE.
+#define BF_SDHC_FEVT_AC12NE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12NE), uint32_t) & BM_SDHC_FEVT_AC12NE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AC12NE field to a new value.
+#define BW_SDHC_FEVT_AC12NE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12NE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field AC12TOE[1] (WORZ)
+ *
+ * Forces AC12ERR[AC12TOE] to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_AC12TOE (1U) //!< Bit position for SDHC_FEVT_AC12TOE.
+#define BM_SDHC_FEVT_AC12TOE (0x00000002U) //!< Bit mask for SDHC_FEVT_AC12TOE.
+#define BS_SDHC_FEVT_AC12TOE (1U) //!< Bit field size in bits for SDHC_FEVT_AC12TOE.
+
+//! @brief Format value for bitfield SDHC_FEVT_AC12TOE.
+#define BF_SDHC_FEVT_AC12TOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12TOE), uint32_t) & BM_SDHC_FEVT_AC12TOE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AC12TOE field to a new value.
+#define BW_SDHC_FEVT_AC12TOE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12TOE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field AC12CE[2] (WORZ)
+ *
+ * Forces AC12ERR[AC12CE] to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_AC12CE (2U) //!< Bit position for SDHC_FEVT_AC12CE.
+#define BM_SDHC_FEVT_AC12CE (0x00000004U) //!< Bit mask for SDHC_FEVT_AC12CE.
+#define BS_SDHC_FEVT_AC12CE (1U) //!< Bit field size in bits for SDHC_FEVT_AC12CE.
+
+//! @brief Format value for bitfield SDHC_FEVT_AC12CE.
+#define BF_SDHC_FEVT_AC12CE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12CE), uint32_t) & BM_SDHC_FEVT_AC12CE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AC12CE field to a new value.
+#define BW_SDHC_FEVT_AC12CE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12CE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field AC12EBE[3] (WORZ)
+ *
+ * Forces AC12ERR[AC12EBE] to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_AC12EBE (3U) //!< Bit position for SDHC_FEVT_AC12EBE.
+#define BM_SDHC_FEVT_AC12EBE (0x00000008U) //!< Bit mask for SDHC_FEVT_AC12EBE.
+#define BS_SDHC_FEVT_AC12EBE (1U) //!< Bit field size in bits for SDHC_FEVT_AC12EBE.
+
+//! @brief Format value for bitfield SDHC_FEVT_AC12EBE.
+#define BF_SDHC_FEVT_AC12EBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12EBE), uint32_t) & BM_SDHC_FEVT_AC12EBE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AC12EBE field to a new value.
+#define BW_SDHC_FEVT_AC12EBE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12EBE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field AC12IE[4] (WORZ)
+ *
+ * Forces AC12ERR[AC12IE] to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_AC12IE (4U) //!< Bit position for SDHC_FEVT_AC12IE.
+#define BM_SDHC_FEVT_AC12IE (0x00000010U) //!< Bit mask for SDHC_FEVT_AC12IE.
+#define BS_SDHC_FEVT_AC12IE (1U) //!< Bit field size in bits for SDHC_FEVT_AC12IE.
+
+//! @brief Format value for bitfield SDHC_FEVT_AC12IE.
+#define BF_SDHC_FEVT_AC12IE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12IE), uint32_t) & BM_SDHC_FEVT_AC12IE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AC12IE field to a new value.
+#define BW_SDHC_FEVT_AC12IE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12IE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field CNIBAC12E[7] (WORZ)
+ *
+ * Forces AC12ERR[CNIBAC12E] to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_CNIBAC12E (7U) //!< Bit position for SDHC_FEVT_CNIBAC12E.
+#define BM_SDHC_FEVT_CNIBAC12E (0x00000080U) //!< Bit mask for SDHC_FEVT_CNIBAC12E.
+#define BS_SDHC_FEVT_CNIBAC12E (1U) //!< Bit field size in bits for SDHC_FEVT_CNIBAC12E.
+
+//! @brief Format value for bitfield SDHC_FEVT_CNIBAC12E.
+#define BF_SDHC_FEVT_CNIBAC12E(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CNIBAC12E), uint32_t) & BM_SDHC_FEVT_CNIBAC12E)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CNIBAC12E field to a new value.
+#define BW_SDHC_FEVT_CNIBAC12E(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CNIBAC12E) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field CTOE[16] (WORZ)
+ *
+ * Forces IRQSTAT[CTOE] to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_CTOE (16U) //!< Bit position for SDHC_FEVT_CTOE.
+#define BM_SDHC_FEVT_CTOE (0x00010000U) //!< Bit mask for SDHC_FEVT_CTOE.
+#define BS_SDHC_FEVT_CTOE (1U) //!< Bit field size in bits for SDHC_FEVT_CTOE.
+
+//! @brief Format value for bitfield SDHC_FEVT_CTOE.
+#define BF_SDHC_FEVT_CTOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CTOE), uint32_t) & BM_SDHC_FEVT_CTOE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CTOE field to a new value.
+#define BW_SDHC_FEVT_CTOE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CTOE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field CCE[17] (WORZ)
+ *
+ * Forces IRQSTAT[CCE] to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_CCE (17U) //!< Bit position for SDHC_FEVT_CCE.
+#define BM_SDHC_FEVT_CCE (0x00020000U) //!< Bit mask for SDHC_FEVT_CCE.
+#define BS_SDHC_FEVT_CCE (1U) //!< Bit field size in bits for SDHC_FEVT_CCE.
+
+//! @brief Format value for bitfield SDHC_FEVT_CCE.
+#define BF_SDHC_FEVT_CCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CCE), uint32_t) & BM_SDHC_FEVT_CCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CCE field to a new value.
+#define BW_SDHC_FEVT_CCE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field CEBE[18] (WORZ)
+ *
+ * Forces IRQSTAT[CEBE] to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_CEBE (18U) //!< Bit position for SDHC_FEVT_CEBE.
+#define BM_SDHC_FEVT_CEBE (0x00040000U) //!< Bit mask for SDHC_FEVT_CEBE.
+#define BS_SDHC_FEVT_CEBE (1U) //!< Bit field size in bits for SDHC_FEVT_CEBE.
+
+//! @brief Format value for bitfield SDHC_FEVT_CEBE.
+#define BF_SDHC_FEVT_CEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CEBE), uint32_t) & BM_SDHC_FEVT_CEBE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CEBE field to a new value.
+#define BW_SDHC_FEVT_CEBE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CEBE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field CIE[19] (WORZ)
+ *
+ * Forces IRQSTAT[CCE] to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_CIE (19U) //!< Bit position for SDHC_FEVT_CIE.
+#define BM_SDHC_FEVT_CIE (0x00080000U) //!< Bit mask for SDHC_FEVT_CIE.
+#define BS_SDHC_FEVT_CIE (1U) //!< Bit field size in bits for SDHC_FEVT_CIE.
+
+//! @brief Format value for bitfield SDHC_FEVT_CIE.
+#define BF_SDHC_FEVT_CIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CIE), uint32_t) & BM_SDHC_FEVT_CIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CIE field to a new value.
+#define BW_SDHC_FEVT_CIE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field DTOE[20] (WORZ)
+ *
+ * Forces IRQSTAT[DTOE] to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_DTOE (20U) //!< Bit position for SDHC_FEVT_DTOE.
+#define BM_SDHC_FEVT_DTOE (0x00100000U) //!< Bit mask for SDHC_FEVT_DTOE.
+#define BS_SDHC_FEVT_DTOE (1U) //!< Bit field size in bits for SDHC_FEVT_DTOE.
+
+//! @brief Format value for bitfield SDHC_FEVT_DTOE.
+#define BF_SDHC_FEVT_DTOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_DTOE), uint32_t) & BM_SDHC_FEVT_DTOE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DTOE field to a new value.
+#define BW_SDHC_FEVT_DTOE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_DTOE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field DCE[21] (WORZ)
+ *
+ * Forces IRQSTAT[DCE] to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_DCE (21U) //!< Bit position for SDHC_FEVT_DCE.
+#define BM_SDHC_FEVT_DCE (0x00200000U) //!< Bit mask for SDHC_FEVT_DCE.
+#define BS_SDHC_FEVT_DCE (1U) //!< Bit field size in bits for SDHC_FEVT_DCE.
+
+//! @brief Format value for bitfield SDHC_FEVT_DCE.
+#define BF_SDHC_FEVT_DCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_DCE), uint32_t) & BM_SDHC_FEVT_DCE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DCE field to a new value.
+#define BW_SDHC_FEVT_DCE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_DCE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field DEBE[22] (WORZ)
+ *
+ * Forces IRQSTAT[DEBE] to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_DEBE (22U) //!< Bit position for SDHC_FEVT_DEBE.
+#define BM_SDHC_FEVT_DEBE (0x00400000U) //!< Bit mask for SDHC_FEVT_DEBE.
+#define BS_SDHC_FEVT_DEBE (1U) //!< Bit field size in bits for SDHC_FEVT_DEBE.
+
+//! @brief Format value for bitfield SDHC_FEVT_DEBE.
+#define BF_SDHC_FEVT_DEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_DEBE), uint32_t) & BM_SDHC_FEVT_DEBE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DEBE field to a new value.
+#define BW_SDHC_FEVT_DEBE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_DEBE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field AC12E[24] (WORZ)
+ *
+ * Forces IRQSTAT[AC12E] to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_AC12E (24U) //!< Bit position for SDHC_FEVT_AC12E.
+#define BM_SDHC_FEVT_AC12E (0x01000000U) //!< Bit mask for SDHC_FEVT_AC12E.
+#define BS_SDHC_FEVT_AC12E (1U) //!< Bit field size in bits for SDHC_FEVT_AC12E.
+
+//! @brief Format value for bitfield SDHC_FEVT_AC12E.
+#define BF_SDHC_FEVT_AC12E(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12E), uint32_t) & BM_SDHC_FEVT_AC12E)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AC12E field to a new value.
+#define BW_SDHC_FEVT_AC12E(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12E) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field DMAE[28] (WORZ)
+ *
+ * Forces the DMAE bit of Interrupt Status Register to be set.
+ */
+//@{
+#define BP_SDHC_FEVT_DMAE (28U) //!< Bit position for SDHC_FEVT_DMAE.
+#define BM_SDHC_FEVT_DMAE (0x10000000U) //!< Bit mask for SDHC_FEVT_DMAE.
+#define BS_SDHC_FEVT_DMAE (1U) //!< Bit field size in bits for SDHC_FEVT_DMAE.
+
+//! @brief Format value for bitfield SDHC_FEVT_DMAE.
+#define BF_SDHC_FEVT_DMAE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_DMAE), uint32_t) & BM_SDHC_FEVT_DMAE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMAE field to a new value.
+#define BW_SDHC_FEVT_DMAE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_DMAE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_FEVT, field CINT[31] (WORZ)
+ *
+ * Writing 1 to this bit generates a short low-level pulse on the internal
+ * DAT[1] line, as if a self-clearing interrupt was received from the external card.
+ * If enabled, the CINT bit will be set and the interrupt service routine may
+ * treat this interrupt as a normal interrupt from the external card.
+ */
+//@{
+#define BP_SDHC_FEVT_CINT (31U) //!< Bit position for SDHC_FEVT_CINT.
+#define BM_SDHC_FEVT_CINT (0x80000000U) //!< Bit mask for SDHC_FEVT_CINT.
+#define BS_SDHC_FEVT_CINT (1U) //!< Bit field size in bits for SDHC_FEVT_CINT.
+
+//! @brief Format value for bitfield SDHC_FEVT_CINT.
+#define BF_SDHC_FEVT_CINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CINT), uint32_t) & BM_SDHC_FEVT_CINT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CINT field to a new value.
+#define BW_SDHC_FEVT_CINT(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CINT) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_ADMAES - ADMA Error Status register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_ADMAES - ADMA Error Status register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When an ADMA error interrupt has occurred, the ADMA Error States field in
+ * this register holds the ADMA state and the ADMA System Address register holds the
+ * address around the error descriptor. For recovering from this error, the host
+ * driver requires the ADMA state to identify the error descriptor address as
+ * follows: ST_STOP: Previous location set in the ADMA System Address register is
+ * the error descriptor address. ST_FDS: Current location set in the ADMA System
+ * Address register is the error descriptor address. ST_CADR: This state is never
+ * set because it only increments the descriptor pointer and doesn't generate an
+ * ADMA error. ST_TFR: Previous location set in the ADMA System Address register
+ * is the error descriptor address. In case of a write operation, the host driver
+ * must use the ACMD22 to get the number of the written block, rather than using
+ * this information, because unwritten data may exist in the host controller.
+ * The host controller generates the ADMA error interrupt when it detects invalid
+ * descriptor data (valid = 0) in the ST_FDS state. The host driver can
+ * distinguish this error by reading the valid bit of the error descriptor. ADMA Error
+ * State coding D01-D00 ADMA Error State when error has occurred Contents of ADMA
+ * System Address register 00 ST_STOP (Stop DMA) Holds the address of the next
+ * executable descriptor command 01 ST_FDS (fetch descriptor) Holds the valid
+ * descriptor address 10 ST_CADR (change address) No ADMA error is generated 11 ST_TFR
+ * (Transfer Data) Holds the address of the next executable descriptor command
+ */
+typedef union _hw_sdhc_admaes
+{
+ uint32_t U;
+ struct _hw_sdhc_admaes_bitfields
+ {
+ uint32_t ADMAES : 2; //!< [1:0] ADMA Error State (When ADMA Error Is
+ //! Occurred.)
+ uint32_t ADMALME : 1; //!< [2] ADMA Length Mismatch Error
+ uint32_t ADMADCE : 1; //!< [3] ADMA Descriptor Error
+ uint32_t RESERVED0 : 28; //!< [31:4]
+ } B;
+} hw_sdhc_admaes_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_ADMAES register
+ */
+//@{
+#define HW_SDHC_ADMAES_ADDR (REGS_SDHC_BASE + 0x54U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_ADMAES (*(__I hw_sdhc_admaes_t *) HW_SDHC_ADMAES_ADDR)
+#define HW_SDHC_ADMAES_RD() (HW_SDHC_ADMAES.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_ADMAES bitfields
+ */
+
+/*!
+ * @name Register SDHC_ADMAES, field ADMAES[1:0] (RO)
+ *
+ * Indicates the state of the ADMA when an error has occurred during an ADMA
+ * data transfer.
+ */
+//@{
+#define BP_SDHC_ADMAES_ADMAES (0U) //!< Bit position for SDHC_ADMAES_ADMAES.
+#define BM_SDHC_ADMAES_ADMAES (0x00000003U) //!< Bit mask for SDHC_ADMAES_ADMAES.
+#define BS_SDHC_ADMAES_ADMAES (2U) //!< Bit field size in bits for SDHC_ADMAES_ADMAES.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_ADMAES_ADMAES field.
+#define BR_SDHC_ADMAES_ADMAES (HW_SDHC_ADMAES.B.ADMAES)
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_ADMAES, field ADMALME[2] (RO)
+ *
+ * This error occurs in the following 2 cases: While the block count enable is
+ * being set, the total data length specified by the descriptor table is different
+ * from that specified by the block count and block length. Total data length
+ * can not be divided by the block length.
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - Error.
+ */
+//@{
+#define BP_SDHC_ADMAES_ADMALME (2U) //!< Bit position for SDHC_ADMAES_ADMALME.
+#define BM_SDHC_ADMAES_ADMALME (0x00000004U) //!< Bit mask for SDHC_ADMAES_ADMALME.
+#define BS_SDHC_ADMAES_ADMALME (1U) //!< Bit field size in bits for SDHC_ADMAES_ADMALME.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_ADMAES_ADMALME field.
+#define BR_SDHC_ADMAES_ADMALME (BITBAND_ACCESS32(HW_SDHC_ADMAES_ADDR, BP_SDHC_ADMAES_ADMALME))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_ADMAES, field ADMADCE[3] (RO)
+ *
+ * This error occurs when an invalid descriptor is fetched by ADMA.
+ *
+ * Values:
+ * - 0 - No error.
+ * - 1 - Error.
+ */
+//@{
+#define BP_SDHC_ADMAES_ADMADCE (3U) //!< Bit position for SDHC_ADMAES_ADMADCE.
+#define BM_SDHC_ADMAES_ADMADCE (0x00000008U) //!< Bit mask for SDHC_ADMAES_ADMADCE.
+#define BS_SDHC_ADMAES_ADMADCE (1U) //!< Bit field size in bits for SDHC_ADMAES_ADMADCE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_ADMAES_ADMADCE field.
+#define BR_SDHC_ADMAES_ADMADCE (BITBAND_ACCESS32(HW_SDHC_ADMAES_ADDR, BP_SDHC_ADMAES_ADMADCE))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_ADSADDR - ADMA System Addressregister
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_ADSADDR - ADMA System Addressregister (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the physical system memory address used for ADMA
+ * transfers.
+ */
+typedef union _hw_sdhc_adsaddr
+{
+ uint32_t U;
+ struct _hw_sdhc_adsaddr_bitfields
+ {
+ uint32_t RESERVED0 : 2; //!< [1:0]
+ uint32_t ADSADDR : 30; //!< [31:2] ADMA System Address
+ } B;
+} hw_sdhc_adsaddr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_ADSADDR register
+ */
+//@{
+#define HW_SDHC_ADSADDR_ADDR (REGS_SDHC_BASE + 0x58U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_ADSADDR (*(__IO hw_sdhc_adsaddr_t *) HW_SDHC_ADSADDR_ADDR)
+#define HW_SDHC_ADSADDR_RD() (HW_SDHC_ADSADDR.U)
+#define HW_SDHC_ADSADDR_WR(v) (HW_SDHC_ADSADDR.U = (v))
+#define HW_SDHC_ADSADDR_SET(v) (HW_SDHC_ADSADDR_WR(HW_SDHC_ADSADDR_RD() | (v)))
+#define HW_SDHC_ADSADDR_CLR(v) (HW_SDHC_ADSADDR_WR(HW_SDHC_ADSADDR_RD() & ~(v)))
+#define HW_SDHC_ADSADDR_TOG(v) (HW_SDHC_ADSADDR_WR(HW_SDHC_ADSADDR_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_ADSADDR bitfields
+ */
+
+/*!
+ * @name Register SDHC_ADSADDR, field ADSADDR[31:2] (RW)
+ *
+ * Holds the word address of the executing command in the descriptor table. At
+ * the start of ADMA, the host driver shall set the start address of the
+ * Descriptor table. The ADMA engine increments this register address whenever fetching a
+ * descriptor command. When the ADMA is stopped at the block gap, this register
+ * indicates the address of the next executable descriptor command. When the ADMA
+ * error interrupt is generated, this register shall hold the valid descriptor
+ * address depending on the ADMA state. The lower 2 bits of this register is tied
+ * to '0' so the ADMA address is always word-aligned. Because this register
+ * supports dynamic address reflecting, when TC bit is set, it automatically alters the
+ * value of internal address counter, so SW cannot change this register when TC
+ * bit is set.
+ */
+//@{
+#define BP_SDHC_ADSADDR_ADSADDR (2U) //!< Bit position for SDHC_ADSADDR_ADSADDR.
+#define BM_SDHC_ADSADDR_ADSADDR (0xFFFFFFFCU) //!< Bit mask for SDHC_ADSADDR_ADSADDR.
+#define BS_SDHC_ADSADDR_ADSADDR (30U) //!< Bit field size in bits for SDHC_ADSADDR_ADSADDR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_ADSADDR_ADSADDR field.
+#define BR_SDHC_ADSADDR_ADSADDR (HW_SDHC_ADSADDR.B.ADSADDR)
+#endif
+
+//! @brief Format value for bitfield SDHC_ADSADDR_ADSADDR.
+#define BF_SDHC_ADSADDR_ADSADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_ADSADDR_ADSADDR), uint32_t) & BM_SDHC_ADSADDR_ADSADDR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADSADDR field to a new value.
+#define BW_SDHC_ADSADDR_ADSADDR(v) (HW_SDHC_ADSADDR_WR((HW_SDHC_ADSADDR_RD() & ~BM_SDHC_ADSADDR_ADSADDR) | BF_SDHC_ADSADDR_ADSADDR(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_VENDOR - Vendor Specific register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_VENDOR - Vendor Specific register (RW)
+ *
+ * Reset value: 0x00000001U
+ *
+ * This register contains the vendor-specific control/status register.
+ */
+typedef union _hw_sdhc_vendor
+{
+ uint32_t U;
+ struct _hw_sdhc_vendor_bitfields
+ {
+ uint32_t EXTDMAEN : 1; //!< [0] External DMA Request Enable
+ uint32_t EXBLKNU : 1; //!< [1] Exact Block Number Block Read Enable
+ //! For SDIO CMD53
+ uint32_t RESERVED0 : 14; //!< [15:2]
+ uint32_t INTSTVAL : 8; //!< [23:16] Internal State Value
+ uint32_t RESERVED1 : 8; //!< [31:24]
+ } B;
+} hw_sdhc_vendor_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_VENDOR register
+ */
+//@{
+#define HW_SDHC_VENDOR_ADDR (REGS_SDHC_BASE + 0xC0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_VENDOR (*(__IO hw_sdhc_vendor_t *) HW_SDHC_VENDOR_ADDR)
+#define HW_SDHC_VENDOR_RD() (HW_SDHC_VENDOR.U)
+#define HW_SDHC_VENDOR_WR(v) (HW_SDHC_VENDOR.U = (v))
+#define HW_SDHC_VENDOR_SET(v) (HW_SDHC_VENDOR_WR(HW_SDHC_VENDOR_RD() | (v)))
+#define HW_SDHC_VENDOR_CLR(v) (HW_SDHC_VENDOR_WR(HW_SDHC_VENDOR_RD() & ~(v)))
+#define HW_SDHC_VENDOR_TOG(v) (HW_SDHC_VENDOR_WR(HW_SDHC_VENDOR_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_VENDOR bitfields
+ */
+
+/*!
+ * @name Register SDHC_VENDOR, field EXTDMAEN[0] (RW)
+ *
+ * Enables the request to external DMA. When the internal DMA (either simple DMA
+ * or advanced DMA) is not in use, and this bit is set, SDHC will send out DMA
+ * request when the internal buffer is ready. This bit is particularly useful when
+ * transferring data by CPU polling mode, and it is not allowed to send out the
+ * external DMA request. By default, this bit is set.
+ *
+ * Values:
+ * - 0 - In any scenario, SDHC does not send out the external DMA request.
+ * - 1 - When internal DMA is not active, the external DMA request will be sent
+ * out.
+ */
+//@{
+#define BP_SDHC_VENDOR_EXTDMAEN (0U) //!< Bit position for SDHC_VENDOR_EXTDMAEN.
+#define BM_SDHC_VENDOR_EXTDMAEN (0x00000001U) //!< Bit mask for SDHC_VENDOR_EXTDMAEN.
+#define BS_SDHC_VENDOR_EXTDMAEN (1U) //!< Bit field size in bits for SDHC_VENDOR_EXTDMAEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_VENDOR_EXTDMAEN field.
+#define BR_SDHC_VENDOR_EXTDMAEN (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR, BP_SDHC_VENDOR_EXTDMAEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_VENDOR_EXTDMAEN.
+#define BF_SDHC_VENDOR_EXTDMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_VENDOR_EXTDMAEN), uint32_t) & BM_SDHC_VENDOR_EXTDMAEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EXTDMAEN field to a new value.
+#define BW_SDHC_VENDOR_EXTDMAEN(v) (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR, BP_SDHC_VENDOR_EXTDMAEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_VENDOR, field EXBLKNU[1] (RW)
+ *
+ * This bit must be set before S/W issues CMD53 multi-block read with exact
+ * block number. This bit must not be set if the CMD53 multi-block read is not exact
+ * block number.
+ *
+ * Values:
+ * - 0 - None exact block read.
+ * - 1 - Exact block read for SDIO CMD53.
+ */
+//@{
+#define BP_SDHC_VENDOR_EXBLKNU (1U) //!< Bit position for SDHC_VENDOR_EXBLKNU.
+#define BM_SDHC_VENDOR_EXBLKNU (0x00000002U) //!< Bit mask for SDHC_VENDOR_EXBLKNU.
+#define BS_SDHC_VENDOR_EXBLKNU (1U) //!< Bit field size in bits for SDHC_VENDOR_EXBLKNU.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_VENDOR_EXBLKNU field.
+#define BR_SDHC_VENDOR_EXBLKNU (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR, BP_SDHC_VENDOR_EXBLKNU))
+#endif
+
+//! @brief Format value for bitfield SDHC_VENDOR_EXBLKNU.
+#define BF_SDHC_VENDOR_EXBLKNU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_VENDOR_EXBLKNU), uint32_t) & BM_SDHC_VENDOR_EXBLKNU)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EXBLKNU field to a new value.
+#define BW_SDHC_VENDOR_EXBLKNU(v) (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR, BP_SDHC_VENDOR_EXBLKNU) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_VENDOR, field INTSTVAL[23:16] (RO)
+ *
+ * Internal state value, reflecting the corresponding state value selected by
+ * Debug Select field. This field is read-only and write to this field does not
+ * have effect.
+ */
+//@{
+#define BP_SDHC_VENDOR_INTSTVAL (16U) //!< Bit position for SDHC_VENDOR_INTSTVAL.
+#define BM_SDHC_VENDOR_INTSTVAL (0x00FF0000U) //!< Bit mask for SDHC_VENDOR_INTSTVAL.
+#define BS_SDHC_VENDOR_INTSTVAL (8U) //!< Bit field size in bits for SDHC_VENDOR_INTSTVAL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_VENDOR_INTSTVAL field.
+#define BR_SDHC_VENDOR_INTSTVAL (HW_SDHC_VENDOR.B.INTSTVAL)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_MMCBOOT - MMC Boot register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_MMCBOOT - MMC Boot register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the MMC fast boot control register.
+ */
+typedef union _hw_sdhc_mmcboot
+{
+ uint32_t U;
+ struct _hw_sdhc_mmcboot_bitfields
+ {
+ uint32_t DTOCVACK : 4; //!< [3:0] Boot ACK Time Out Counter Value
+ uint32_t BOOTACK : 1; //!< [4] Boot Ack Mode Select
+ uint32_t BOOTMODE : 1; //!< [5] Boot Mode Select
+ uint32_t BOOTEN : 1; //!< [6] Boot Mode Enable
+ uint32_t AUTOSABGEN : 1; //!< [7]
+ uint32_t RESERVED0 : 8; //!< [15:8]
+ uint32_t BOOTBLKCNT : 16; //!< [31:16]
+ } B;
+} hw_sdhc_mmcboot_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_MMCBOOT register
+ */
+//@{
+#define HW_SDHC_MMCBOOT_ADDR (REGS_SDHC_BASE + 0xC4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_MMCBOOT (*(__IO hw_sdhc_mmcboot_t *) HW_SDHC_MMCBOOT_ADDR)
+#define HW_SDHC_MMCBOOT_RD() (HW_SDHC_MMCBOOT.U)
+#define HW_SDHC_MMCBOOT_WR(v) (HW_SDHC_MMCBOOT.U = (v))
+#define HW_SDHC_MMCBOOT_SET(v) (HW_SDHC_MMCBOOT_WR(HW_SDHC_MMCBOOT_RD() | (v)))
+#define HW_SDHC_MMCBOOT_CLR(v) (HW_SDHC_MMCBOOT_WR(HW_SDHC_MMCBOOT_RD() & ~(v)))
+#define HW_SDHC_MMCBOOT_TOG(v) (HW_SDHC_MMCBOOT_WR(HW_SDHC_MMCBOOT_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_MMCBOOT bitfields
+ */
+
+/*!
+ * @name Register SDHC_MMCBOOT, field DTOCVACK[3:0] (RW)
+ *
+ * Values:
+ * - 0000 - SDCLK x 2^8
+ * - 0001 - SDCLK x 2^9
+ * - 0010 - SDCLK x 2^10
+ * - 0011 - SDCLK x 2^11
+ * - 0100 - SDCLK x 2^12
+ * - 0101 - SDCLK x 2^13
+ * - 0110 - SDCLK x 2^14
+ * - 0111 - SDCLK x 2^15
+ * - 1110 - SDCLK x 2^22
+ * - 1111 - Reserved
+ */
+//@{
+#define BP_SDHC_MMCBOOT_DTOCVACK (0U) //!< Bit position for SDHC_MMCBOOT_DTOCVACK.
+#define BM_SDHC_MMCBOOT_DTOCVACK (0x0000000FU) //!< Bit mask for SDHC_MMCBOOT_DTOCVACK.
+#define BS_SDHC_MMCBOOT_DTOCVACK (4U) //!< Bit field size in bits for SDHC_MMCBOOT_DTOCVACK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_MMCBOOT_DTOCVACK field.
+#define BR_SDHC_MMCBOOT_DTOCVACK (HW_SDHC_MMCBOOT.B.DTOCVACK)
+#endif
+
+//! @brief Format value for bitfield SDHC_MMCBOOT_DTOCVACK.
+#define BF_SDHC_MMCBOOT_DTOCVACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_DTOCVACK), uint32_t) & BM_SDHC_MMCBOOT_DTOCVACK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DTOCVACK field to a new value.
+#define BW_SDHC_MMCBOOT_DTOCVACK(v) (HW_SDHC_MMCBOOT_WR((HW_SDHC_MMCBOOT_RD() & ~BM_SDHC_MMCBOOT_DTOCVACK) | BF_SDHC_MMCBOOT_DTOCVACK(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTACK[4] (RW)
+ *
+ * Values:
+ * - 0 - No ack.
+ * - 1 - Ack.
+ */
+//@{
+#define BP_SDHC_MMCBOOT_BOOTACK (4U) //!< Bit position for SDHC_MMCBOOT_BOOTACK.
+#define BM_SDHC_MMCBOOT_BOOTACK (0x00000010U) //!< Bit mask for SDHC_MMCBOOT_BOOTACK.
+#define BS_SDHC_MMCBOOT_BOOTACK (1U) //!< Bit field size in bits for SDHC_MMCBOOT_BOOTACK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_MMCBOOT_BOOTACK field.
+#define BR_SDHC_MMCBOOT_BOOTACK (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTACK))
+#endif
+
+//! @brief Format value for bitfield SDHC_MMCBOOT_BOOTACK.
+#define BF_SDHC_MMCBOOT_BOOTACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_BOOTACK), uint32_t) & BM_SDHC_MMCBOOT_BOOTACK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BOOTACK field to a new value.
+#define BW_SDHC_MMCBOOT_BOOTACK(v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTACK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTMODE[5] (RW)
+ *
+ * Values:
+ * - 0 - Normal boot.
+ * - 1 - Alternative boot.
+ */
+//@{
+#define BP_SDHC_MMCBOOT_BOOTMODE (5U) //!< Bit position for SDHC_MMCBOOT_BOOTMODE.
+#define BM_SDHC_MMCBOOT_BOOTMODE (0x00000020U) //!< Bit mask for SDHC_MMCBOOT_BOOTMODE.
+#define BS_SDHC_MMCBOOT_BOOTMODE (1U) //!< Bit field size in bits for SDHC_MMCBOOT_BOOTMODE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_MMCBOOT_BOOTMODE field.
+#define BR_SDHC_MMCBOOT_BOOTMODE (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTMODE))
+#endif
+
+//! @brief Format value for bitfield SDHC_MMCBOOT_BOOTMODE.
+#define BF_SDHC_MMCBOOT_BOOTMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_BOOTMODE), uint32_t) & BM_SDHC_MMCBOOT_BOOTMODE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BOOTMODE field to a new value.
+#define BW_SDHC_MMCBOOT_BOOTMODE(v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTMODE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTEN[6] (RW)
+ *
+ * Values:
+ * - 0 - Fast boot disable.
+ * - 1 - Fast boot enable.
+ */
+//@{
+#define BP_SDHC_MMCBOOT_BOOTEN (6U) //!< Bit position for SDHC_MMCBOOT_BOOTEN.
+#define BM_SDHC_MMCBOOT_BOOTEN (0x00000040U) //!< Bit mask for SDHC_MMCBOOT_BOOTEN.
+#define BS_SDHC_MMCBOOT_BOOTEN (1U) //!< Bit field size in bits for SDHC_MMCBOOT_BOOTEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_MMCBOOT_BOOTEN field.
+#define BR_SDHC_MMCBOOT_BOOTEN (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_MMCBOOT_BOOTEN.
+#define BF_SDHC_MMCBOOT_BOOTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_BOOTEN), uint32_t) & BM_SDHC_MMCBOOT_BOOTEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BOOTEN field to a new value.
+#define BW_SDHC_MMCBOOT_BOOTEN(v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_MMCBOOT, field AUTOSABGEN[7] (RW)
+ *
+ * When boot, enable auto stop at block gap function. This function will be
+ * triggered, and host will stop at block gap when received card block cnt is equal
+ * to BOOTBLKCNT.
+ */
+//@{
+#define BP_SDHC_MMCBOOT_AUTOSABGEN (7U) //!< Bit position for SDHC_MMCBOOT_AUTOSABGEN.
+#define BM_SDHC_MMCBOOT_AUTOSABGEN (0x00000080U) //!< Bit mask for SDHC_MMCBOOT_AUTOSABGEN.
+#define BS_SDHC_MMCBOOT_AUTOSABGEN (1U) //!< Bit field size in bits for SDHC_MMCBOOT_AUTOSABGEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_MMCBOOT_AUTOSABGEN field.
+#define BR_SDHC_MMCBOOT_AUTOSABGEN (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_AUTOSABGEN))
+#endif
+
+//! @brief Format value for bitfield SDHC_MMCBOOT_AUTOSABGEN.
+#define BF_SDHC_MMCBOOT_AUTOSABGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_AUTOSABGEN), uint32_t) & BM_SDHC_MMCBOOT_AUTOSABGEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AUTOSABGEN field to a new value.
+#define BW_SDHC_MMCBOOT_AUTOSABGEN(v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_AUTOSABGEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTBLKCNT[31:16] (RW)
+ *
+ * Defines the stop at block gap value of automatic mode. When received card
+ * block cnt is equal to BOOTBLKCNT and AUTOSABGEN is 1, then stop at block gap.
+ */
+//@{
+#define BP_SDHC_MMCBOOT_BOOTBLKCNT (16U) //!< Bit position for SDHC_MMCBOOT_BOOTBLKCNT.
+#define BM_SDHC_MMCBOOT_BOOTBLKCNT (0xFFFF0000U) //!< Bit mask for SDHC_MMCBOOT_BOOTBLKCNT.
+#define BS_SDHC_MMCBOOT_BOOTBLKCNT (16U) //!< Bit field size in bits for SDHC_MMCBOOT_BOOTBLKCNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_MMCBOOT_BOOTBLKCNT field.
+#define BR_SDHC_MMCBOOT_BOOTBLKCNT (HW_SDHC_MMCBOOT.B.BOOTBLKCNT)
+#endif
+
+//! @brief Format value for bitfield SDHC_MMCBOOT_BOOTBLKCNT.
+#define BF_SDHC_MMCBOOT_BOOTBLKCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_BOOTBLKCNT), uint32_t) & BM_SDHC_MMCBOOT_BOOTBLKCNT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BOOTBLKCNT field to a new value.
+#define BW_SDHC_MMCBOOT_BOOTBLKCNT(v) (HW_SDHC_MMCBOOT_WR((HW_SDHC_MMCBOOT_RD() & ~BM_SDHC_MMCBOOT_BOOTBLKCNT) | BF_SDHC_MMCBOOT_BOOTBLKCNT(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SDHC_HOSTVER - Host Controller Version
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SDHC_HOSTVER - Host Controller Version (RO)
+ *
+ * Reset value: 0x00001201U
+ *
+ * This register contains the vendor host controller version information. All
+ * bits are read only and will read the same as the power-reset value.
+ */
+typedef union _hw_sdhc_hostver
+{
+ uint32_t U;
+ struct _hw_sdhc_hostver_bitfields
+ {
+ uint32_t SVN : 8; //!< [7:0] Specification Version Number
+ uint32_t VVN : 8; //!< [15:8] Vendor Version Number
+ uint32_t RESERVED0 : 16; //!< [31:16]
+ } B;
+} hw_sdhc_hostver_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SDHC_HOSTVER register
+ */
+//@{
+#define HW_SDHC_HOSTVER_ADDR (REGS_SDHC_BASE + 0xFCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SDHC_HOSTVER (*(__I hw_sdhc_hostver_t *) HW_SDHC_HOSTVER_ADDR)
+#define HW_SDHC_HOSTVER_RD() (HW_SDHC_HOSTVER.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SDHC_HOSTVER bitfields
+ */
+
+/*!
+ * @name Register SDHC_HOSTVER, field SVN[7:0] (RO)
+ *
+ * These status bits indicate the host controller specification version.
+ *
+ * Values:
+ * - 1 - SD host specification version 2.0, supports test event register and
+ * ADMA.
+ */
+//@{
+#define BP_SDHC_HOSTVER_SVN (0U) //!< Bit position for SDHC_HOSTVER_SVN.
+#define BM_SDHC_HOSTVER_SVN (0x000000FFU) //!< Bit mask for SDHC_HOSTVER_SVN.
+#define BS_SDHC_HOSTVER_SVN (8U) //!< Bit field size in bits for SDHC_HOSTVER_SVN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_HOSTVER_SVN field.
+#define BR_SDHC_HOSTVER_SVN (HW_SDHC_HOSTVER.B.SVN)
+#endif
+//@}
+
+/*!
+ * @name Register SDHC_HOSTVER, field VVN[15:8] (RO)
+ *
+ * These status bits are reserved for the vendor version number. The host driver
+ * shall not use this status.
+ *
+ * Values:
+ * - 0 - Freescale SDHC version 1.0
+ * - 10000 - Freescale SDHC version 2.0
+ * - 10001 - Freescale SDHC version 2.1
+ * - 10010 - Freescale SDHC version 2.2
+ */
+//@{
+#define BP_SDHC_HOSTVER_VVN (8U) //!< Bit position for SDHC_HOSTVER_VVN.
+#define BM_SDHC_HOSTVER_VVN (0x0000FF00U) //!< Bit mask for SDHC_HOSTVER_VVN.
+#define BS_SDHC_HOSTVER_VVN (8U) //!< Bit field size in bits for SDHC_HOSTVER_VVN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SDHC_HOSTVER_VVN field.
+#define BR_SDHC_HOSTVER_VVN (HW_SDHC_HOSTVER.B.VVN)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_sdhc_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All SDHC module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_sdhc
+{
+ __IO hw_sdhc_dsaddr_t DSADDR; //!< [0x0] DMA System Address register
+ __IO hw_sdhc_blkattr_t BLKATTR; //!< [0x4] Block Attributes register
+ __IO hw_sdhc_cmdarg_t CMDARG; //!< [0x8] Command Argument register
+ __IO hw_sdhc_xfertyp_t XFERTYP; //!< [0xC] Transfer Type register
+ __I hw_sdhc_cmdrsp0_t CMDRSP0; //!< [0x10] Command Response 0
+ __I hw_sdhc_cmdrsp1_t CMDRSP1; //!< [0x14] Command Response 1
+ __I hw_sdhc_cmdrsp2_t CMDRSP2; //!< [0x18] Command Response 2
+ __I hw_sdhc_cmdrsp3_t CMDRSP3; //!< [0x1C] Command Response 3
+ __IO hw_sdhc_datport_t DATPORT; //!< [0x20] Buffer Data Port register
+ __I hw_sdhc_prsstat_t PRSSTAT; //!< [0x24] Present State register
+ __IO hw_sdhc_proctl_t PROCTL; //!< [0x28] Protocol Control register
+ __IO hw_sdhc_sysctl_t SYSCTL; //!< [0x2C] System Control register
+ __IO hw_sdhc_irqstat_t IRQSTAT; //!< [0x30] Interrupt Status register
+ __IO hw_sdhc_irqstaten_t IRQSTATEN; //!< [0x34] Interrupt Status Enable register
+ __IO hw_sdhc_irqsigen_t IRQSIGEN; //!< [0x38] Interrupt Signal Enable register
+ __I hw_sdhc_ac12err_t AC12ERR; //!< [0x3C] Auto CMD12 Error Status Register
+ __I hw_sdhc_htcapblt_t HTCAPBLT; //!< [0x40] Host Controller Capabilities
+ __IO hw_sdhc_wml_t WML; //!< [0x44] Watermark Level Register
+ uint8_t _reserved0[8];
+ __O hw_sdhc_fevt_t FEVT; //!< [0x50] Force Event register
+ __I hw_sdhc_admaes_t ADMAES; //!< [0x54] ADMA Error Status register
+ __IO hw_sdhc_adsaddr_t ADSADDR; //!< [0x58] ADMA System Addressregister
+ uint8_t _reserved1[100];
+ __IO hw_sdhc_vendor_t VENDOR; //!< [0xC0] Vendor Specific register
+ __IO hw_sdhc_mmcboot_t MMCBOOT; //!< [0xC4] MMC Boot register
+ uint8_t _reserved2[52];
+ __I hw_sdhc_hostver_t HOSTVER; //!< [0xFC] Host Controller Version
+} hw_sdhc_t;
+#pragma pack()
+
+//! @brief Macro to access all SDHC registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_SDHC</code>.
+#define HW_SDHC (*(hw_sdhc_t *) REGS_SDHC_BASE)
+#endif
+
+#endif // __HW_SDHC_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_sim.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,4553 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_SIM_REGISTERS_H__
+#define __HW_SIM_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 SIM
+ *
+ * System Integration Module
+ *
+ * Registers defined in this header file:
+ * - HW_SIM_SOPT1 - System Options Register 1
+ * - HW_SIM_SOPT1CFG - SOPT1 Configuration Register
+ * - HW_SIM_SOPT2 - System Options Register 2
+ * - HW_SIM_SOPT4 - System Options Register 4
+ * - HW_SIM_SOPT5 - System Options Register 5
+ * - HW_SIM_SOPT7 - System Options Register 7
+ * - HW_SIM_SDID - System Device Identification Register
+ * - HW_SIM_SCGC1 - System Clock Gating Control Register 1
+ * - HW_SIM_SCGC2 - System Clock Gating Control Register 2
+ * - HW_SIM_SCGC3 - System Clock Gating Control Register 3
+ * - HW_SIM_SCGC4 - System Clock Gating Control Register 4
+ * - HW_SIM_SCGC5 - System Clock Gating Control Register 5
+ * - HW_SIM_SCGC6 - System Clock Gating Control Register 6
+ * - HW_SIM_SCGC7 - System Clock Gating Control Register 7
+ * - HW_SIM_CLKDIV1 - System Clock Divider Register 1
+ * - HW_SIM_CLKDIV2 - System Clock Divider Register 2
+ * - HW_SIM_FCFG1 - Flash Configuration Register 1
+ * - HW_SIM_FCFG2 - Flash Configuration Register 2
+ * - HW_SIM_UIDH - Unique Identification Register High
+ * - HW_SIM_UIDMH - Unique Identification Register Mid-High
+ * - HW_SIM_UIDML - Unique Identification Register Mid Low
+ * - HW_SIM_UIDL - Unique Identification Register Low
+ *
+ * - hw_sim_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_SIM_BASE
+#define HW_SIM_INSTANCE_COUNT (1U) //!< Number of instances of the SIM module.
+#define REGS_SIM_BASE (0x40047000U) //!< Base address for SIM.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_SOPT1 - System Options Register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_SOPT1 - System Options Register 1 (RW)
+ *
+ * Reset value: 0x80000000U
+ *
+ * The SOPT1 register is only reset on POR or LVD.
+ */
+typedef union _hw_sim_sopt1
+{
+ uint32_t U;
+ struct _hw_sim_sopt1_bitfields
+ {
+ uint32_t RESERVED0 : 12; //!< [11:0]
+ uint32_t RAMSIZE : 4; //!< [15:12] RAM size
+ uint32_t RESERVED1 : 2; //!< [17:16]
+ uint32_t OSC32KSEL : 2; //!< [19:18] 32K oscillator clock select
+ uint32_t RESERVED2 : 9; //!< [28:20]
+ uint32_t USBVSTBY : 1; //!< [29] USB voltage regulator in standby
+ //! mode during VLPR and VLPW modes
+ uint32_t USBSSTBY : 1; //!< [30] USB voltage regulator in standby
+ //! mode during Stop, VLPS, LLS and VLLS modes.
+ uint32_t USBREGEN : 1; //!< [31] USB voltage regulator enable
+ } B;
+} hw_sim_sopt1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_SOPT1 register
+ */
+//@{
+#define HW_SIM_SOPT1_ADDR (REGS_SIM_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_SOPT1 (*(__IO hw_sim_sopt1_t *) HW_SIM_SOPT1_ADDR)
+#define HW_SIM_SOPT1_RD() (HW_SIM_SOPT1.U)
+#define HW_SIM_SOPT1_WR(v) (HW_SIM_SOPT1.U = (v))
+#define HW_SIM_SOPT1_SET(v) (HW_SIM_SOPT1_WR(HW_SIM_SOPT1_RD() | (v)))
+#define HW_SIM_SOPT1_CLR(v) (HW_SIM_SOPT1_WR(HW_SIM_SOPT1_RD() & ~(v)))
+#define HW_SIM_SOPT1_TOG(v) (HW_SIM_SOPT1_WR(HW_SIM_SOPT1_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_SOPT1 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT1, field RAMSIZE[15:12] (RO)
+ *
+ * This field specifies the amount of system RAM available on the device.
+ *
+ * Values:
+ * - 0001 - 8 KB
+ * - 0011 - 16 KB
+ * - 0100 - 24 KB
+ * - 0101 - 32 KB
+ * - 0110 - 48 KB
+ * - 0111 - 64 KB
+ * - 1000 - 96 KB
+ * - 1001 - 128 KB
+ * - 1011 - 256 KB
+ */
+//@{
+#define BP_SIM_SOPT1_RAMSIZE (12U) //!< Bit position for SIM_SOPT1_RAMSIZE.
+#define BM_SIM_SOPT1_RAMSIZE (0x0000F000U) //!< Bit mask for SIM_SOPT1_RAMSIZE.
+#define BS_SIM_SOPT1_RAMSIZE (4U) //!< Bit field size in bits for SIM_SOPT1_RAMSIZE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT1_RAMSIZE field.
+#define BR_SIM_SOPT1_RAMSIZE (HW_SIM_SOPT1.B.RAMSIZE)
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT1, field OSC32KSEL[19:18] (RW)
+ *
+ * Selects the 32 kHz clock source (ERCLK32K) for LPTMR. This field is reset
+ * only on POR/LVD.
+ *
+ * Values:
+ * - 00 - System oscillator (OSC32KCLK)
+ * - 01 - Reserved
+ * - 10 - RTC 32.768kHz oscillator
+ * - 11 - LPO 1 kHz
+ */
+//@{
+#define BP_SIM_SOPT1_OSC32KSEL (18U) //!< Bit position for SIM_SOPT1_OSC32KSEL.
+#define BM_SIM_SOPT1_OSC32KSEL (0x000C0000U) //!< Bit mask for SIM_SOPT1_OSC32KSEL.
+#define BS_SIM_SOPT1_OSC32KSEL (2U) //!< Bit field size in bits for SIM_SOPT1_OSC32KSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT1_OSC32KSEL field.
+#define BR_SIM_SOPT1_OSC32KSEL (HW_SIM_SOPT1.B.OSC32KSEL)
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT1_OSC32KSEL.
+#define BF_SIM_SOPT1_OSC32KSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1_OSC32KSEL), uint32_t) & BM_SIM_SOPT1_OSC32KSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OSC32KSEL field to a new value.
+#define BW_SIM_SOPT1_OSC32KSEL(v) (HW_SIM_SOPT1_WR((HW_SIM_SOPT1_RD() & ~BM_SIM_SOPT1_OSC32KSEL) | BF_SIM_SOPT1_OSC32KSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT1, field USBVSTBY[29] (RW)
+ *
+ * Controls whether the USB voltage regulator is placed in standby mode during
+ * VLPR and VLPW modes.
+ *
+ * Values:
+ * - 0 - USB voltage regulator not in standby during VLPR and VLPW modes.
+ * - 1 - USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+//@{
+#define BP_SIM_SOPT1_USBVSTBY (29U) //!< Bit position for SIM_SOPT1_USBVSTBY.
+#define BM_SIM_SOPT1_USBVSTBY (0x20000000U) //!< Bit mask for SIM_SOPT1_USBVSTBY.
+#define BS_SIM_SOPT1_USBVSTBY (1U) //!< Bit field size in bits for SIM_SOPT1_USBVSTBY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT1_USBVSTBY field.
+#define BR_SIM_SOPT1_USBVSTBY (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBVSTBY))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT1_USBVSTBY.
+#define BF_SIM_SOPT1_USBVSTBY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1_USBVSTBY), uint32_t) & BM_SIM_SOPT1_USBVSTBY)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the USBVSTBY field to a new value.
+#define BW_SIM_SOPT1_USBVSTBY(v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBVSTBY) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT1, field USBSSTBY[30] (RW)
+ *
+ * Controls whether the USB voltage regulator is placed in standby mode during
+ * Stop, VLPS, LLS and VLLS modes.
+ *
+ * Values:
+ * - 0 - USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS
+ * modes.
+ * - 1 - USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes.
+ */
+//@{
+#define BP_SIM_SOPT1_USBSSTBY (30U) //!< Bit position for SIM_SOPT1_USBSSTBY.
+#define BM_SIM_SOPT1_USBSSTBY (0x40000000U) //!< Bit mask for SIM_SOPT1_USBSSTBY.
+#define BS_SIM_SOPT1_USBSSTBY (1U) //!< Bit field size in bits for SIM_SOPT1_USBSSTBY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT1_USBSSTBY field.
+#define BR_SIM_SOPT1_USBSSTBY (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBSSTBY))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT1_USBSSTBY.
+#define BF_SIM_SOPT1_USBSSTBY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1_USBSSTBY), uint32_t) & BM_SIM_SOPT1_USBSSTBY)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the USBSSTBY field to a new value.
+#define BW_SIM_SOPT1_USBSSTBY(v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBSSTBY) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT1, field USBREGEN[31] (RW)
+ *
+ * Controls whether the USB voltage regulator is enabled.
+ *
+ * Values:
+ * - 0 - USB voltage regulator is disabled.
+ * - 1 - USB voltage regulator is enabled.
+ */
+//@{
+#define BP_SIM_SOPT1_USBREGEN (31U) //!< Bit position for SIM_SOPT1_USBREGEN.
+#define BM_SIM_SOPT1_USBREGEN (0x80000000U) //!< Bit mask for SIM_SOPT1_USBREGEN.
+#define BS_SIM_SOPT1_USBREGEN (1U) //!< Bit field size in bits for SIM_SOPT1_USBREGEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT1_USBREGEN field.
+#define BR_SIM_SOPT1_USBREGEN (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBREGEN))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT1_USBREGEN.
+#define BF_SIM_SOPT1_USBREGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1_USBREGEN), uint32_t) & BM_SIM_SOPT1_USBREGEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the USBREGEN field to a new value.
+#define BW_SIM_SOPT1_USBREGEN(v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBREGEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_SOPT1CFG - SOPT1 Configuration Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_SOPT1CFG - SOPT1 Configuration Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The SOPT1CFG register is reset on System Reset not VLLS.
+ */
+typedef union _hw_sim_sopt1cfg
+{
+ uint32_t U;
+ struct _hw_sim_sopt1cfg_bitfields
+ {
+ uint32_t RESERVED0 : 24; //!< [23:0]
+ uint32_t URWE : 1; //!< [24] USB voltage regulator enable write enable
+ uint32_t UVSWE : 1; //!< [25] USB voltage regulator VLP standby write
+ //! enable
+ uint32_t USSWE : 1; //!< [26] USB voltage regulator stop standby
+ //! write enable
+ uint32_t RESERVED1 : 5; //!< [31:27]
+ } B;
+} hw_sim_sopt1cfg_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_SOPT1CFG register
+ */
+//@{
+#define HW_SIM_SOPT1CFG_ADDR (REGS_SIM_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_SOPT1CFG (*(__IO hw_sim_sopt1cfg_t *) HW_SIM_SOPT1CFG_ADDR)
+#define HW_SIM_SOPT1CFG_RD() (HW_SIM_SOPT1CFG.U)
+#define HW_SIM_SOPT1CFG_WR(v) (HW_SIM_SOPT1CFG.U = (v))
+#define HW_SIM_SOPT1CFG_SET(v) (HW_SIM_SOPT1CFG_WR(HW_SIM_SOPT1CFG_RD() | (v)))
+#define HW_SIM_SOPT1CFG_CLR(v) (HW_SIM_SOPT1CFG_WR(HW_SIM_SOPT1CFG_RD() & ~(v)))
+#define HW_SIM_SOPT1CFG_TOG(v) (HW_SIM_SOPT1CFG_WR(HW_SIM_SOPT1CFG_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_SOPT1CFG bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT1CFG, field URWE[24] (RW)
+ *
+ * Writing one to the URWE bit allows the SOPT1 USBREGEN bit to be written. This
+ * register bit clears after a write to USBREGEN.
+ *
+ * Values:
+ * - 0 - SOPT1 USBREGEN cannot be written.
+ * - 1 - SOPT1 USBREGEN can be written.
+ */
+//@{
+#define BP_SIM_SOPT1CFG_URWE (24U) //!< Bit position for SIM_SOPT1CFG_URWE.
+#define BM_SIM_SOPT1CFG_URWE (0x01000000U) //!< Bit mask for SIM_SOPT1CFG_URWE.
+#define BS_SIM_SOPT1CFG_URWE (1U) //!< Bit field size in bits for SIM_SOPT1CFG_URWE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT1CFG_URWE field.
+#define BR_SIM_SOPT1CFG_URWE (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_URWE))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT1CFG_URWE.
+#define BF_SIM_SOPT1CFG_URWE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1CFG_URWE), uint32_t) & BM_SIM_SOPT1CFG_URWE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the URWE field to a new value.
+#define BW_SIM_SOPT1CFG_URWE(v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_URWE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT1CFG, field UVSWE[25] (RW)
+ *
+ * Writing one to the UVSWE bit allows the SOPT1 USBVSTBY bit to be written.
+ * This register bit clears after a write to USBVSTBY.
+ *
+ * Values:
+ * - 0 - SOPT1 USBVSTBY cannot be written.
+ * - 1 - SOPT1 USBVSTBY can be written.
+ */
+//@{
+#define BP_SIM_SOPT1CFG_UVSWE (25U) //!< Bit position for SIM_SOPT1CFG_UVSWE.
+#define BM_SIM_SOPT1CFG_UVSWE (0x02000000U) //!< Bit mask for SIM_SOPT1CFG_UVSWE.
+#define BS_SIM_SOPT1CFG_UVSWE (1U) //!< Bit field size in bits for SIM_SOPT1CFG_UVSWE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT1CFG_UVSWE field.
+#define BR_SIM_SOPT1CFG_UVSWE (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_UVSWE))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT1CFG_UVSWE.
+#define BF_SIM_SOPT1CFG_UVSWE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1CFG_UVSWE), uint32_t) & BM_SIM_SOPT1CFG_UVSWE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UVSWE field to a new value.
+#define BW_SIM_SOPT1CFG_UVSWE(v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_UVSWE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT1CFG, field USSWE[26] (RW)
+ *
+ * Writing one to the USSWE bit allows the SOPT1 USBSSTBY bit to be written.
+ * This register bit clears after a write to USBSSTBY.
+ *
+ * Values:
+ * - 0 - SOPT1 USBSSTBY cannot be written.
+ * - 1 - SOPT1 USBSSTBY can be written.
+ */
+//@{
+#define BP_SIM_SOPT1CFG_USSWE (26U) //!< Bit position for SIM_SOPT1CFG_USSWE.
+#define BM_SIM_SOPT1CFG_USSWE (0x04000000U) //!< Bit mask for SIM_SOPT1CFG_USSWE.
+#define BS_SIM_SOPT1CFG_USSWE (1U) //!< Bit field size in bits for SIM_SOPT1CFG_USSWE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT1CFG_USSWE field.
+#define BR_SIM_SOPT1CFG_USSWE (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_USSWE))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT1CFG_USSWE.
+#define BF_SIM_SOPT1CFG_USSWE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1CFG_USSWE), uint32_t) & BM_SIM_SOPT1CFG_USSWE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the USSWE field to a new value.
+#define BW_SIM_SOPT1CFG_USSWE(v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_USSWE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_SOPT2 - System Options Register 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_SOPT2 - System Options Register 2 (RW)
+ *
+ * Reset value: 0x00001000U
+ *
+ * SOPT2 contains the controls for selecting many of the module clock source
+ * options on this device. See the Clock Distribution chapter for more information
+ * including clocking diagrams and definitions of device clocks.
+ */
+typedef union _hw_sim_sopt2
+{
+ uint32_t U;
+ struct _hw_sim_sopt2_bitfields
+ {
+ uint32_t RESERVED0 : 4; //!< [3:0]
+ uint32_t RTCCLKOUTSEL : 1; //!< [4] RTC clock out select
+ uint32_t CLKOUTSEL : 3; //!< [7:5] CLKOUT select
+ uint32_t FBSL : 2; //!< [9:8] FlexBus security level
+ uint32_t RESERVED1 : 1; //!< [10]
+ uint32_t PTD7PAD : 1; //!< [11] PTD7 pad drive strength
+ uint32_t TRACECLKSEL : 1; //!< [12] Debug trace clock select
+ uint32_t RESERVED2 : 3; //!< [15:13]
+ uint32_t PLLFLLSEL : 2; //!< [17:16] PLL/FLL clock select
+ uint32_t USBSRC : 1; //!< [18] USB clock source select
+ uint32_t RMIISRC : 1; //!< [19] RMII clock source select
+ uint32_t TIMESRC : 2; //!< [21:20] IEEE 1588 timestamp clock source
+ //! select
+ uint32_t RESERVED3 : 6; //!< [27:22]
+ uint32_t SDHCSRC : 2; //!< [29:28] SDHC clock source select
+ uint32_t RESERVED4 : 2; //!< [31:30]
+ } B;
+} hw_sim_sopt2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_SOPT2 register
+ */
+//@{
+#define HW_SIM_SOPT2_ADDR (REGS_SIM_BASE + 0x1004U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_SOPT2 (*(__IO hw_sim_sopt2_t *) HW_SIM_SOPT2_ADDR)
+#define HW_SIM_SOPT2_RD() (HW_SIM_SOPT2.U)
+#define HW_SIM_SOPT2_WR(v) (HW_SIM_SOPT2.U = (v))
+#define HW_SIM_SOPT2_SET(v) (HW_SIM_SOPT2_WR(HW_SIM_SOPT2_RD() | (v)))
+#define HW_SIM_SOPT2_CLR(v) (HW_SIM_SOPT2_WR(HW_SIM_SOPT2_RD() & ~(v)))
+#define HW_SIM_SOPT2_TOG(v) (HW_SIM_SOPT2_WR(HW_SIM_SOPT2_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_SOPT2 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT2, field RTCCLKOUTSEL[4] (RW)
+ *
+ * Selects either the RTC 1 Hz clock or the 32.768kHz clock to be output on the
+ * RTC_CLKOUT pin.
+ *
+ * Values:
+ * - 0 - RTC 1 Hz clock is output on the RTC_CLKOUT pin.
+ * - 1 - RTC 32.768kHz clock is output on the RTC_CLKOUT pin.
+ */
+//@{
+#define BP_SIM_SOPT2_RTCCLKOUTSEL (4U) //!< Bit position for SIM_SOPT2_RTCCLKOUTSEL.
+#define BM_SIM_SOPT2_RTCCLKOUTSEL (0x00000010U) //!< Bit mask for SIM_SOPT2_RTCCLKOUTSEL.
+#define BS_SIM_SOPT2_RTCCLKOUTSEL (1U) //!< Bit field size in bits for SIM_SOPT2_RTCCLKOUTSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT2_RTCCLKOUTSEL field.
+#define BR_SIM_SOPT2_RTCCLKOUTSEL (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_RTCCLKOUTSEL))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT2_RTCCLKOUTSEL.
+#define BF_SIM_SOPT2_RTCCLKOUTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_RTCCLKOUTSEL), uint32_t) & BM_SIM_SOPT2_RTCCLKOUTSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RTCCLKOUTSEL field to a new value.
+#define BW_SIM_SOPT2_RTCCLKOUTSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_RTCCLKOUTSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT2, field CLKOUTSEL[7:5] (RW)
+ *
+ * Selects the clock to output on the CLKOUT pin.
+ *
+ * Values:
+ * - 000 - FlexBus CLKOUT
+ * - 001 - Reserved
+ * - 010 - Flash clock
+ * - 011 - LPO clock (1 kHz)
+ * - 100 - MCGIRCLK
+ * - 101 - RTC 32.768kHz clock
+ * - 110 - OSCERCLK0
+ * - 111 - IRC 48 MHz clock
+ */
+//@{
+#define BP_SIM_SOPT2_CLKOUTSEL (5U) //!< Bit position for SIM_SOPT2_CLKOUTSEL.
+#define BM_SIM_SOPT2_CLKOUTSEL (0x000000E0U) //!< Bit mask for SIM_SOPT2_CLKOUTSEL.
+#define BS_SIM_SOPT2_CLKOUTSEL (3U) //!< Bit field size in bits for SIM_SOPT2_CLKOUTSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT2_CLKOUTSEL field.
+#define BR_SIM_SOPT2_CLKOUTSEL (HW_SIM_SOPT2.B.CLKOUTSEL)
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT2_CLKOUTSEL.
+#define BF_SIM_SOPT2_CLKOUTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_CLKOUTSEL), uint32_t) & BM_SIM_SOPT2_CLKOUTSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLKOUTSEL field to a new value.
+#define BW_SIM_SOPT2_CLKOUTSEL(v) (HW_SIM_SOPT2_WR((HW_SIM_SOPT2_RD() & ~BM_SIM_SOPT2_CLKOUTSEL) | BF_SIM_SOPT2_CLKOUTSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT2, field FBSL[9:8] (RW)
+ *
+ * If flash security is enabled, then this field affects what CPU operations can
+ * access off-chip via the FlexBus interface. This field has no effect if flash
+ * security is not enabled.
+ *
+ * Values:
+ * - 00 - All off-chip accesses (instruction and data) via the FlexBus are
+ * disallowed.
+ * - 01 - All off-chip accesses (instruction and data) via the FlexBus are
+ * disallowed.
+ * - 10 - Off-chip instruction accesses are disallowed. Data accesses are
+ * allowed.
+ * - 11 - Off-chip instruction accesses and data accesses are allowed.
+ */
+//@{
+#define BP_SIM_SOPT2_FBSL (8U) //!< Bit position for SIM_SOPT2_FBSL.
+#define BM_SIM_SOPT2_FBSL (0x00000300U) //!< Bit mask for SIM_SOPT2_FBSL.
+#define BS_SIM_SOPT2_FBSL (2U) //!< Bit field size in bits for SIM_SOPT2_FBSL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT2_FBSL field.
+#define BR_SIM_SOPT2_FBSL (HW_SIM_SOPT2.B.FBSL)
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT2_FBSL.
+#define BF_SIM_SOPT2_FBSL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_FBSL), uint32_t) & BM_SIM_SOPT2_FBSL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FBSL field to a new value.
+#define BW_SIM_SOPT2_FBSL(v) (HW_SIM_SOPT2_WR((HW_SIM_SOPT2_RD() & ~BM_SIM_SOPT2_FBSL) | BF_SIM_SOPT2_FBSL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT2, field PTD7PAD[11] (RW)
+ *
+ * Controls the output drive strength of the PTD7 pin by selecting either one or
+ * two pads to drive it.
+ *
+ * Values:
+ * - 0 - Single-pad drive strength for PTD7.
+ * - 1 - Double pad drive strength for PTD7.
+ */
+//@{
+#define BP_SIM_SOPT2_PTD7PAD (11U) //!< Bit position for SIM_SOPT2_PTD7PAD.
+#define BM_SIM_SOPT2_PTD7PAD (0x00000800U) //!< Bit mask for SIM_SOPT2_PTD7PAD.
+#define BS_SIM_SOPT2_PTD7PAD (1U) //!< Bit field size in bits for SIM_SOPT2_PTD7PAD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT2_PTD7PAD field.
+#define BR_SIM_SOPT2_PTD7PAD (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_PTD7PAD))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT2_PTD7PAD.
+#define BF_SIM_SOPT2_PTD7PAD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_PTD7PAD), uint32_t) & BM_SIM_SOPT2_PTD7PAD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PTD7PAD field to a new value.
+#define BW_SIM_SOPT2_PTD7PAD(v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_PTD7PAD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT2, field TRACECLKSEL[12] (RW)
+ *
+ * Selects the core/system clock or MCG output clock (MCGOUTCLK) as the trace
+ * clock source.
+ *
+ * Values:
+ * - 0 - MCGOUTCLK
+ * - 1 - Core/system clock
+ */
+//@{
+#define BP_SIM_SOPT2_TRACECLKSEL (12U) //!< Bit position for SIM_SOPT2_TRACECLKSEL.
+#define BM_SIM_SOPT2_TRACECLKSEL (0x00001000U) //!< Bit mask for SIM_SOPT2_TRACECLKSEL.
+#define BS_SIM_SOPT2_TRACECLKSEL (1U) //!< Bit field size in bits for SIM_SOPT2_TRACECLKSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT2_TRACECLKSEL field.
+#define BR_SIM_SOPT2_TRACECLKSEL (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_TRACECLKSEL))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT2_TRACECLKSEL.
+#define BF_SIM_SOPT2_TRACECLKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_TRACECLKSEL), uint32_t) & BM_SIM_SOPT2_TRACECLKSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TRACECLKSEL field to a new value.
+#define BW_SIM_SOPT2_TRACECLKSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_TRACECLKSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT2, field PLLFLLSEL[17:16] (RW)
+ *
+ * Selects the high frequency clock for various peripheral clocking options.
+ *
+ * Values:
+ * - 00 - MCGFLLCLK clock
+ * - 01 - MCGPLLCLK clock
+ * - 10 - Reserved
+ * - 11 - IRC48 MHz clock
+ */
+//@{
+#define BP_SIM_SOPT2_PLLFLLSEL (16U) //!< Bit position for SIM_SOPT2_PLLFLLSEL.
+#define BM_SIM_SOPT2_PLLFLLSEL (0x00030000U) //!< Bit mask for SIM_SOPT2_PLLFLLSEL.
+#define BS_SIM_SOPT2_PLLFLLSEL (2U) //!< Bit field size in bits for SIM_SOPT2_PLLFLLSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT2_PLLFLLSEL field.
+#define BR_SIM_SOPT2_PLLFLLSEL (HW_SIM_SOPT2.B.PLLFLLSEL)
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT2_PLLFLLSEL.
+#define BF_SIM_SOPT2_PLLFLLSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_PLLFLLSEL), uint32_t) & BM_SIM_SOPT2_PLLFLLSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PLLFLLSEL field to a new value.
+#define BW_SIM_SOPT2_PLLFLLSEL(v) (HW_SIM_SOPT2_WR((HW_SIM_SOPT2_RD() & ~BM_SIM_SOPT2_PLLFLLSEL) | BF_SIM_SOPT2_PLLFLLSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT2, field USBSRC[18] (RW)
+ *
+ * Selects the clock source for the USB 48 MHz clock.
+ *
+ * Values:
+ * - 0 - External bypass clock (USB_CLKIN).
+ * - 1 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
+ * SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by
+ * SIM_CLKDIV2[USBFRAC, USBDIV].
+ */
+//@{
+#define BP_SIM_SOPT2_USBSRC (18U) //!< Bit position for SIM_SOPT2_USBSRC.
+#define BM_SIM_SOPT2_USBSRC (0x00040000U) //!< Bit mask for SIM_SOPT2_USBSRC.
+#define BS_SIM_SOPT2_USBSRC (1U) //!< Bit field size in bits for SIM_SOPT2_USBSRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT2_USBSRC field.
+#define BR_SIM_SOPT2_USBSRC (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_USBSRC))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT2_USBSRC.
+#define BF_SIM_SOPT2_USBSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_USBSRC), uint32_t) & BM_SIM_SOPT2_USBSRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the USBSRC field to a new value.
+#define BW_SIM_SOPT2_USBSRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_USBSRC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT2, field RMIISRC[19] (RW)
+ *
+ * Selects the clock source for the Ethernet RMII interface
+ *
+ * Values:
+ * - 0 - EXTAL clock
+ * - 1 - External bypass clock (ENET_1588_CLKIN).
+ */
+//@{
+#define BP_SIM_SOPT2_RMIISRC (19U) //!< Bit position for SIM_SOPT2_RMIISRC.
+#define BM_SIM_SOPT2_RMIISRC (0x00080000U) //!< Bit mask for SIM_SOPT2_RMIISRC.
+#define BS_SIM_SOPT2_RMIISRC (1U) //!< Bit field size in bits for SIM_SOPT2_RMIISRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT2_RMIISRC field.
+#define BR_SIM_SOPT2_RMIISRC (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_RMIISRC))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT2_RMIISRC.
+#define BF_SIM_SOPT2_RMIISRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_RMIISRC), uint32_t) & BM_SIM_SOPT2_RMIISRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RMIISRC field to a new value.
+#define BW_SIM_SOPT2_RMIISRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_RMIISRC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT2, field TIMESRC[21:20] (RW)
+ *
+ * Selects the clock source for the Ethernet timestamp clock.
+ *
+ * Values:
+ * - 00 - Core/system clock.
+ * - 01 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
+ * SOPT2[PLLFLLSEL].
+ * - 10 - OSCERCLK clock
+ * - 11 - External bypass clock (ENET_1588_CLKIN).
+ */
+//@{
+#define BP_SIM_SOPT2_TIMESRC (20U) //!< Bit position for SIM_SOPT2_TIMESRC.
+#define BM_SIM_SOPT2_TIMESRC (0x00300000U) //!< Bit mask for SIM_SOPT2_TIMESRC.
+#define BS_SIM_SOPT2_TIMESRC (2U) //!< Bit field size in bits for SIM_SOPT2_TIMESRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT2_TIMESRC field.
+#define BR_SIM_SOPT2_TIMESRC (HW_SIM_SOPT2.B.TIMESRC)
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT2_TIMESRC.
+#define BF_SIM_SOPT2_TIMESRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_TIMESRC), uint32_t) & BM_SIM_SOPT2_TIMESRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TIMESRC field to a new value.
+#define BW_SIM_SOPT2_TIMESRC(v) (HW_SIM_SOPT2_WR((HW_SIM_SOPT2_RD() & ~BM_SIM_SOPT2_TIMESRC) | BF_SIM_SOPT2_TIMESRC(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT2, field SDHCSRC[29:28] (RW)
+ *
+ * Selects the clock source for the SDHC clock .
+ *
+ * Values:
+ * - 00 - Core/system clock.
+ * - 01 - MCGFLLCLK, or MCGPLLCLK , or IRC48M clock as selected by
+ * SOPT2[PLLFLLSEL].
+ * - 10 - OSCERCLK clock
+ * - 11 - External bypass clock (SDHC0_CLKIN)
+ */
+//@{
+#define BP_SIM_SOPT2_SDHCSRC (28U) //!< Bit position for SIM_SOPT2_SDHCSRC.
+#define BM_SIM_SOPT2_SDHCSRC (0x30000000U) //!< Bit mask for SIM_SOPT2_SDHCSRC.
+#define BS_SIM_SOPT2_SDHCSRC (2U) //!< Bit field size in bits for SIM_SOPT2_SDHCSRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT2_SDHCSRC field.
+#define BR_SIM_SOPT2_SDHCSRC (HW_SIM_SOPT2.B.SDHCSRC)
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT2_SDHCSRC.
+#define BF_SIM_SOPT2_SDHCSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_SDHCSRC), uint32_t) & BM_SIM_SOPT2_SDHCSRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SDHCSRC field to a new value.
+#define BW_SIM_SOPT2_SDHCSRC(v) (HW_SIM_SOPT2_WR((HW_SIM_SOPT2_RD() & ~BM_SIM_SOPT2_SDHCSRC) | BF_SIM_SOPT2_SDHCSRC(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_SOPT4 - System Options Register 4
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_SOPT4 - System Options Register 4 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_sim_sopt4
+{
+ uint32_t U;
+ struct _hw_sim_sopt4_bitfields
+ {
+ uint32_t FTM0FLT0 : 1; //!< [0] FTM0 Fault 0 Select
+ uint32_t FTM0FLT1 : 1; //!< [1] FTM0 Fault 1 Select
+ uint32_t FTM0FLT2 : 1; //!< [2] FTM0 Fault 2 Select
+ uint32_t RESERVED0 : 1; //!< [3]
+ uint32_t FTM1FLT0 : 1; //!< [4] FTM1 Fault 0 Select
+ uint32_t RESERVED1 : 3; //!< [7:5]
+ uint32_t FTM2FLT0 : 1; //!< [8] FTM2 Fault 0 Select
+ uint32_t RESERVED2 : 3; //!< [11:9]
+ uint32_t FTM3FLT0 : 1; //!< [12] FTM3 Fault 0 Select
+ uint32_t RESERVED3 : 5; //!< [17:13]
+ uint32_t FTM1CH0SRC : 2; //!< [19:18] FTM1 channel 0 input capture
+ //! source select
+ uint32_t FTM2CH0SRC : 2; //!< [21:20] FTM2 channel 0 input capture
+ //! source select
+ uint32_t RESERVED4 : 2; //!< [23:22]
+ uint32_t FTM0CLKSEL : 1; //!< [24] FlexTimer 0 External Clock Pin
+ //! Select
+ uint32_t FTM1CLKSEL : 1; //!< [25] FTM1 External Clock Pin Select
+ uint32_t FTM2CLKSEL : 1; //!< [26] FlexTimer 2 External Clock Pin
+ //! Select
+ uint32_t FTM3CLKSEL : 1; //!< [27] FlexTimer 3 External Clock Pin
+ //! Select
+ uint32_t FTM0TRG0SRC : 1; //!< [28] FlexTimer 0 Hardware Trigger 0
+ //! Source Select
+ uint32_t FTM0TRG1SRC : 1; //!< [29] FlexTimer 0 Hardware Trigger 1
+ //! Source Select
+ uint32_t FTM3TRG0SRC : 1; //!< [30] FlexTimer 3 Hardware Trigger 0
+ //! Source Select
+ uint32_t FTM3TRG1SRC : 1; //!< [31] FlexTimer 3 Hardware Trigger 1
+ //! Source Select
+ } B;
+} hw_sim_sopt4_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_SOPT4 register
+ */
+//@{
+#define HW_SIM_SOPT4_ADDR (REGS_SIM_BASE + 0x100CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_SOPT4 (*(__IO hw_sim_sopt4_t *) HW_SIM_SOPT4_ADDR)
+#define HW_SIM_SOPT4_RD() (HW_SIM_SOPT4.U)
+#define HW_SIM_SOPT4_WR(v) (HW_SIM_SOPT4.U = (v))
+#define HW_SIM_SOPT4_SET(v) (HW_SIM_SOPT4_WR(HW_SIM_SOPT4_RD() | (v)))
+#define HW_SIM_SOPT4_CLR(v) (HW_SIM_SOPT4_WR(HW_SIM_SOPT4_RD() & ~(v)))
+#define HW_SIM_SOPT4_TOG(v) (HW_SIM_SOPT4_WR(HW_SIM_SOPT4_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_SOPT4 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0FLT0[0] (RW)
+ *
+ * Selects the source of FTM0 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0 - FTM0_FLT0 pin
+ * - 1 - CMP0 out
+ */
+//@{
+#define BP_SIM_SOPT4_FTM0FLT0 (0U) //!< Bit position for SIM_SOPT4_FTM0FLT0.
+#define BM_SIM_SOPT4_FTM0FLT0 (0x00000001U) //!< Bit mask for SIM_SOPT4_FTM0FLT0.
+#define BS_SIM_SOPT4_FTM0FLT0 (1U) //!< Bit field size in bits for SIM_SOPT4_FTM0FLT0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM0FLT0 field.
+#define BR_SIM_SOPT4_FTM0FLT0 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT0))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM0FLT0.
+#define BF_SIM_SOPT4_FTM0FLT0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0FLT0), uint32_t) & BM_SIM_SOPT4_FTM0FLT0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM0FLT0 field to a new value.
+#define BW_SIM_SOPT4_FTM0FLT0(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0FLT1[1] (RW)
+ *
+ * Selects the source of FTM0 fault 1. The pin source for fault 1 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0 - FTM0_FLT1 pin
+ * - 1 - CMP1 out
+ */
+//@{
+#define BP_SIM_SOPT4_FTM0FLT1 (1U) //!< Bit position for SIM_SOPT4_FTM0FLT1.
+#define BM_SIM_SOPT4_FTM0FLT1 (0x00000002U) //!< Bit mask for SIM_SOPT4_FTM0FLT1.
+#define BS_SIM_SOPT4_FTM0FLT1 (1U) //!< Bit field size in bits for SIM_SOPT4_FTM0FLT1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM0FLT1 field.
+#define BR_SIM_SOPT4_FTM0FLT1 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT1))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM0FLT1.
+#define BF_SIM_SOPT4_FTM0FLT1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0FLT1), uint32_t) & BM_SIM_SOPT4_FTM0FLT1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM0FLT1 field to a new value.
+#define BW_SIM_SOPT4_FTM0FLT1(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0FLT2[2] (RW)
+ *
+ * Selects the source of FTM0 fault 2. The pin source for fault 2 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0 - FTM0_FLT2 pin
+ * - 1 - CMP2 out
+ */
+//@{
+#define BP_SIM_SOPT4_FTM0FLT2 (2U) //!< Bit position for SIM_SOPT4_FTM0FLT2.
+#define BM_SIM_SOPT4_FTM0FLT2 (0x00000004U) //!< Bit mask for SIM_SOPT4_FTM0FLT2.
+#define BS_SIM_SOPT4_FTM0FLT2 (1U) //!< Bit field size in bits for SIM_SOPT4_FTM0FLT2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM0FLT2 field.
+#define BR_SIM_SOPT4_FTM0FLT2 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT2))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM0FLT2.
+#define BF_SIM_SOPT4_FTM0FLT2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0FLT2), uint32_t) & BM_SIM_SOPT4_FTM0FLT2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM0FLT2 field to a new value.
+#define BW_SIM_SOPT4_FTM0FLT2(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM1FLT0[4] (RW)
+ *
+ * Selects the source of FTM1 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0 - FTM1_FLT0 pin
+ * - 1 - CMP0 out
+ */
+//@{
+#define BP_SIM_SOPT4_FTM1FLT0 (4U) //!< Bit position for SIM_SOPT4_FTM1FLT0.
+#define BM_SIM_SOPT4_FTM1FLT0 (0x00000010U) //!< Bit mask for SIM_SOPT4_FTM1FLT0.
+#define BS_SIM_SOPT4_FTM1FLT0 (1U) //!< Bit field size in bits for SIM_SOPT4_FTM1FLT0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM1FLT0 field.
+#define BR_SIM_SOPT4_FTM1FLT0 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM1FLT0))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM1FLT0.
+#define BF_SIM_SOPT4_FTM1FLT0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM1FLT0), uint32_t) & BM_SIM_SOPT4_FTM1FLT0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM1FLT0 field to a new value.
+#define BW_SIM_SOPT4_FTM1FLT0(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM1FLT0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM2FLT0[8] (RW)
+ *
+ * Selects the source of FTM2 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate PORTx pin
+ * control register.
+ *
+ * Values:
+ * - 0 - FTM2_FLT0 pin
+ * - 1 - CMP0 out
+ */
+//@{
+#define BP_SIM_SOPT4_FTM2FLT0 (8U) //!< Bit position for SIM_SOPT4_FTM2FLT0.
+#define BM_SIM_SOPT4_FTM2FLT0 (0x00000100U) //!< Bit mask for SIM_SOPT4_FTM2FLT0.
+#define BS_SIM_SOPT4_FTM2FLT0 (1U) //!< Bit field size in bits for SIM_SOPT4_FTM2FLT0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM2FLT0 field.
+#define BR_SIM_SOPT4_FTM2FLT0 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM2FLT0))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM2FLT0.
+#define BF_SIM_SOPT4_FTM2FLT0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM2FLT0), uint32_t) & BM_SIM_SOPT4_FTM2FLT0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM2FLT0 field to a new value.
+#define BW_SIM_SOPT4_FTM2FLT0(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM2FLT0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3FLT0[12] (RW)
+ *
+ * Selects the source of FTM3 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate PORTx pin
+ * control register.
+ *
+ * Values:
+ * - 0 - FTM3_FLT0 pin
+ * - 1 - CMP0 out
+ */
+//@{
+#define BP_SIM_SOPT4_FTM3FLT0 (12U) //!< Bit position for SIM_SOPT4_FTM3FLT0.
+#define BM_SIM_SOPT4_FTM3FLT0 (0x00001000U) //!< Bit mask for SIM_SOPT4_FTM3FLT0.
+#define BS_SIM_SOPT4_FTM3FLT0 (1U) //!< Bit field size in bits for SIM_SOPT4_FTM3FLT0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM3FLT0 field.
+#define BR_SIM_SOPT4_FTM3FLT0 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3FLT0))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM3FLT0.
+#define BF_SIM_SOPT4_FTM3FLT0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM3FLT0), uint32_t) & BM_SIM_SOPT4_FTM3FLT0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM3FLT0 field to a new value.
+#define BW_SIM_SOPT4_FTM3FLT0(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3FLT0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM1CH0SRC[19:18] (RW)
+ *
+ * Selects the source for FTM1 channel 0 input capture. When the FTM is not in
+ * input capture mode, clear this field.
+ *
+ * Values:
+ * - 00 - FTM1_CH0 signal
+ * - 01 - CMP0 output
+ * - 10 - CMP1 output
+ * - 11 - USB start of frame pulse
+ */
+//@{
+#define BP_SIM_SOPT4_FTM1CH0SRC (18U) //!< Bit position for SIM_SOPT4_FTM1CH0SRC.
+#define BM_SIM_SOPT4_FTM1CH0SRC (0x000C0000U) //!< Bit mask for SIM_SOPT4_FTM1CH0SRC.
+#define BS_SIM_SOPT4_FTM1CH0SRC (2U) //!< Bit field size in bits for SIM_SOPT4_FTM1CH0SRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM1CH0SRC field.
+#define BR_SIM_SOPT4_FTM1CH0SRC (HW_SIM_SOPT4.B.FTM1CH0SRC)
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM1CH0SRC.
+#define BF_SIM_SOPT4_FTM1CH0SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM1CH0SRC), uint32_t) & BM_SIM_SOPT4_FTM1CH0SRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM1CH0SRC field to a new value.
+#define BW_SIM_SOPT4_FTM1CH0SRC(v) (HW_SIM_SOPT4_WR((HW_SIM_SOPT4_RD() & ~BM_SIM_SOPT4_FTM1CH0SRC) | BF_SIM_SOPT4_FTM1CH0SRC(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM2CH0SRC[21:20] (RW)
+ *
+ * Selects the source for FTM2 channel 0 input capture. When the FTM is not in
+ * input capture mode, clear this field.
+ *
+ * Values:
+ * - 00 - FTM2_CH0 signal
+ * - 01 - CMP0 output
+ * - 10 - CMP1 output
+ * - 11 - Reserved
+ */
+//@{
+#define BP_SIM_SOPT4_FTM2CH0SRC (20U) //!< Bit position for SIM_SOPT4_FTM2CH0SRC.
+#define BM_SIM_SOPT4_FTM2CH0SRC (0x00300000U) //!< Bit mask for SIM_SOPT4_FTM2CH0SRC.
+#define BS_SIM_SOPT4_FTM2CH0SRC (2U) //!< Bit field size in bits for SIM_SOPT4_FTM2CH0SRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM2CH0SRC field.
+#define BR_SIM_SOPT4_FTM2CH0SRC (HW_SIM_SOPT4.B.FTM2CH0SRC)
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM2CH0SRC.
+#define BF_SIM_SOPT4_FTM2CH0SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM2CH0SRC), uint32_t) & BM_SIM_SOPT4_FTM2CH0SRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM2CH0SRC field to a new value.
+#define BW_SIM_SOPT4_FTM2CH0SRC(v) (HW_SIM_SOPT4_WR((HW_SIM_SOPT4_RD() & ~BM_SIM_SOPT4_FTM2CH0SRC) | BF_SIM_SOPT4_FTM2CH0SRC(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0CLKSEL[24] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM0 module. The
+ * selected pin must also be configured for the FTM external clock function through
+ * the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0 - FTM_CLK0 pin
+ * - 1 - FTM_CLK1 pin
+ */
+//@{
+#define BP_SIM_SOPT4_FTM0CLKSEL (24U) //!< Bit position for SIM_SOPT4_FTM0CLKSEL.
+#define BM_SIM_SOPT4_FTM0CLKSEL (0x01000000U) //!< Bit mask for SIM_SOPT4_FTM0CLKSEL.
+#define BS_SIM_SOPT4_FTM0CLKSEL (1U) //!< Bit field size in bits for SIM_SOPT4_FTM0CLKSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM0CLKSEL field.
+#define BR_SIM_SOPT4_FTM0CLKSEL (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0CLKSEL))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM0CLKSEL.
+#define BF_SIM_SOPT4_FTM0CLKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0CLKSEL), uint32_t) & BM_SIM_SOPT4_FTM0CLKSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM0CLKSEL field to a new value.
+#define BW_SIM_SOPT4_FTM0CLKSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0CLKSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM1CLKSEL[25] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM1 module. The
+ * selected pin must also be configured for the FTM external clock function through
+ * the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0 - FTM_CLK0 pin
+ * - 1 - FTM_CLK1 pin
+ */
+//@{
+#define BP_SIM_SOPT4_FTM1CLKSEL (25U) //!< Bit position for SIM_SOPT4_FTM1CLKSEL.
+#define BM_SIM_SOPT4_FTM1CLKSEL (0x02000000U) //!< Bit mask for SIM_SOPT4_FTM1CLKSEL.
+#define BS_SIM_SOPT4_FTM1CLKSEL (1U) //!< Bit field size in bits for SIM_SOPT4_FTM1CLKSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM1CLKSEL field.
+#define BR_SIM_SOPT4_FTM1CLKSEL (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM1CLKSEL))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM1CLKSEL.
+#define BF_SIM_SOPT4_FTM1CLKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM1CLKSEL), uint32_t) & BM_SIM_SOPT4_FTM1CLKSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM1CLKSEL field to a new value.
+#define BW_SIM_SOPT4_FTM1CLKSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM1CLKSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM2CLKSEL[26] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM2 module. The
+ * selected pin must also be configured for the FTM2 module external clock function
+ * through the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0 - FTM2 external clock driven by FTM_CLK0 pin.
+ * - 1 - FTM2 external clock driven by FTM_CLK1 pin.
+ */
+//@{
+#define BP_SIM_SOPT4_FTM2CLKSEL (26U) //!< Bit position for SIM_SOPT4_FTM2CLKSEL.
+#define BM_SIM_SOPT4_FTM2CLKSEL (0x04000000U) //!< Bit mask for SIM_SOPT4_FTM2CLKSEL.
+#define BS_SIM_SOPT4_FTM2CLKSEL (1U) //!< Bit field size in bits for SIM_SOPT4_FTM2CLKSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM2CLKSEL field.
+#define BR_SIM_SOPT4_FTM2CLKSEL (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM2CLKSEL))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM2CLKSEL.
+#define BF_SIM_SOPT4_FTM2CLKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM2CLKSEL), uint32_t) & BM_SIM_SOPT4_FTM2CLKSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM2CLKSEL field to a new value.
+#define BW_SIM_SOPT4_FTM2CLKSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM2CLKSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3CLKSEL[27] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM3 module. The
+ * selected pin must also be configured for the FTM3 module external clock function
+ * through the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0 - FTM3 external clock driven by FTM_CLK0 pin.
+ * - 1 - FTM3 external clock driven by FTM_CLK1 pin.
+ */
+//@{
+#define BP_SIM_SOPT4_FTM3CLKSEL (27U) //!< Bit position for SIM_SOPT4_FTM3CLKSEL.
+#define BM_SIM_SOPT4_FTM3CLKSEL (0x08000000U) //!< Bit mask for SIM_SOPT4_FTM3CLKSEL.
+#define BS_SIM_SOPT4_FTM3CLKSEL (1U) //!< Bit field size in bits for SIM_SOPT4_FTM3CLKSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM3CLKSEL field.
+#define BR_SIM_SOPT4_FTM3CLKSEL (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3CLKSEL))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM3CLKSEL.
+#define BF_SIM_SOPT4_FTM3CLKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM3CLKSEL), uint32_t) & BM_SIM_SOPT4_FTM3CLKSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM3CLKSEL field to a new value.
+#define BW_SIM_SOPT4_FTM3CLKSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3CLKSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0TRG0SRC[28] (RW)
+ *
+ * Selects the source of FTM0 hardware trigger 0.
+ *
+ * Values:
+ * - 0 - HSCMP0 output drives FTM0 hardware trigger 0
+ * - 1 - FTM1 channel match drives FTM0 hardware trigger 0
+ */
+//@{
+#define BP_SIM_SOPT4_FTM0TRG0SRC (28U) //!< Bit position for SIM_SOPT4_FTM0TRG0SRC.
+#define BM_SIM_SOPT4_FTM0TRG0SRC (0x10000000U) //!< Bit mask for SIM_SOPT4_FTM0TRG0SRC.
+#define BS_SIM_SOPT4_FTM0TRG0SRC (1U) //!< Bit field size in bits for SIM_SOPT4_FTM0TRG0SRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM0TRG0SRC field.
+#define BR_SIM_SOPT4_FTM0TRG0SRC (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0TRG0SRC))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM0TRG0SRC.
+#define BF_SIM_SOPT4_FTM0TRG0SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0TRG0SRC), uint32_t) & BM_SIM_SOPT4_FTM0TRG0SRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM0TRG0SRC field to a new value.
+#define BW_SIM_SOPT4_FTM0TRG0SRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0TRG0SRC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0TRG1SRC[29] (RW)
+ *
+ * Selects the source of FTM0 hardware trigger 1.
+ *
+ * Values:
+ * - 0 - PDB output trigger 1 drives FTM0 hardware trigger 1
+ * - 1 - FTM2 channel match drives FTM0 hardware trigger 1
+ */
+//@{
+#define BP_SIM_SOPT4_FTM0TRG1SRC (29U) //!< Bit position for SIM_SOPT4_FTM0TRG1SRC.
+#define BM_SIM_SOPT4_FTM0TRG1SRC (0x20000000U) //!< Bit mask for SIM_SOPT4_FTM0TRG1SRC.
+#define BS_SIM_SOPT4_FTM0TRG1SRC (1U) //!< Bit field size in bits for SIM_SOPT4_FTM0TRG1SRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM0TRG1SRC field.
+#define BR_SIM_SOPT4_FTM0TRG1SRC (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0TRG1SRC))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM0TRG1SRC.
+#define BF_SIM_SOPT4_FTM0TRG1SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0TRG1SRC), uint32_t) & BM_SIM_SOPT4_FTM0TRG1SRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM0TRG1SRC field to a new value.
+#define BW_SIM_SOPT4_FTM0TRG1SRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0TRG1SRC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3TRG0SRC[30] (RW)
+ *
+ * Selects the source of FTM3 hardware trigger 0.
+ *
+ * Values:
+ * - 0 - Reserved
+ * - 1 - FTM1 channel match drives FTM3 hardware trigger 0
+ */
+//@{
+#define BP_SIM_SOPT4_FTM3TRG0SRC (30U) //!< Bit position for SIM_SOPT4_FTM3TRG0SRC.
+#define BM_SIM_SOPT4_FTM3TRG0SRC (0x40000000U) //!< Bit mask for SIM_SOPT4_FTM3TRG0SRC.
+#define BS_SIM_SOPT4_FTM3TRG0SRC (1U) //!< Bit field size in bits for SIM_SOPT4_FTM3TRG0SRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM3TRG0SRC field.
+#define BR_SIM_SOPT4_FTM3TRG0SRC (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3TRG0SRC))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM3TRG0SRC.
+#define BF_SIM_SOPT4_FTM3TRG0SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM3TRG0SRC), uint32_t) & BM_SIM_SOPT4_FTM3TRG0SRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM3TRG0SRC field to a new value.
+#define BW_SIM_SOPT4_FTM3TRG0SRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3TRG0SRC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3TRG1SRC[31] (RW)
+ *
+ * Selects the source of FTM3 hardware trigger 1.
+ *
+ * Values:
+ * - 0 - Reserved
+ * - 1 - FTM2 channel match drives FTM3 hardware trigger 1
+ */
+//@{
+#define BP_SIM_SOPT4_FTM3TRG1SRC (31U) //!< Bit position for SIM_SOPT4_FTM3TRG1SRC.
+#define BM_SIM_SOPT4_FTM3TRG1SRC (0x80000000U) //!< Bit mask for SIM_SOPT4_FTM3TRG1SRC.
+#define BS_SIM_SOPT4_FTM3TRG1SRC (1U) //!< Bit field size in bits for SIM_SOPT4_FTM3TRG1SRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT4_FTM3TRG1SRC field.
+#define BR_SIM_SOPT4_FTM3TRG1SRC (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3TRG1SRC))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT4_FTM3TRG1SRC.
+#define BF_SIM_SOPT4_FTM3TRG1SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM3TRG1SRC), uint32_t) & BM_SIM_SOPT4_FTM3TRG1SRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM3TRG1SRC field to a new value.
+#define BW_SIM_SOPT4_FTM3TRG1SRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3TRG1SRC) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_SOPT5 - System Options Register 5
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_SOPT5 - System Options Register 5 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_sim_sopt5
+{
+ uint32_t U;
+ struct _hw_sim_sopt5_bitfields
+ {
+ uint32_t UART0TXSRC : 2; //!< [1:0] UART 0 transmit data source select
+ uint32_t UART0RXSRC : 2; //!< [3:2] UART 0 receive data source select
+ uint32_t UART1TXSRC : 2; //!< [5:4] UART 1 transmit data source select
+ uint32_t UART1RXSRC : 2; //!< [7:6] UART 1 receive data source select
+ uint32_t RESERVED0 : 24; //!< [31:8]
+ } B;
+} hw_sim_sopt5_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_SOPT5 register
+ */
+//@{
+#define HW_SIM_SOPT5_ADDR (REGS_SIM_BASE + 0x1010U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_SOPT5 (*(__IO hw_sim_sopt5_t *) HW_SIM_SOPT5_ADDR)
+#define HW_SIM_SOPT5_RD() (HW_SIM_SOPT5.U)
+#define HW_SIM_SOPT5_WR(v) (HW_SIM_SOPT5.U = (v))
+#define HW_SIM_SOPT5_SET(v) (HW_SIM_SOPT5_WR(HW_SIM_SOPT5_RD() | (v)))
+#define HW_SIM_SOPT5_CLR(v) (HW_SIM_SOPT5_WR(HW_SIM_SOPT5_RD() & ~(v)))
+#define HW_SIM_SOPT5_TOG(v) (HW_SIM_SOPT5_WR(HW_SIM_SOPT5_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_SOPT5 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT5, field UART0TXSRC[1:0] (RW)
+ *
+ * Selects the source for the UART 0 transmit data.
+ *
+ * Values:
+ * - 00 - UART0_TX pin
+ * - 01 - UART0_TX pin modulated with FTM1 channel 0 output
+ * - 10 - UART0_TX pin modulated with FTM2 channel 0 output
+ * - 11 - Reserved
+ */
+//@{
+#define BP_SIM_SOPT5_UART0TXSRC (0U) //!< Bit position for SIM_SOPT5_UART0TXSRC.
+#define BM_SIM_SOPT5_UART0TXSRC (0x00000003U) //!< Bit mask for SIM_SOPT5_UART0TXSRC.
+#define BS_SIM_SOPT5_UART0TXSRC (2U) //!< Bit field size in bits for SIM_SOPT5_UART0TXSRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT5_UART0TXSRC field.
+#define BR_SIM_SOPT5_UART0TXSRC (HW_SIM_SOPT5.B.UART0TXSRC)
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT5_UART0TXSRC.
+#define BF_SIM_SOPT5_UART0TXSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT5_UART0TXSRC), uint32_t) & BM_SIM_SOPT5_UART0TXSRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UART0TXSRC field to a new value.
+#define BW_SIM_SOPT5_UART0TXSRC(v) (HW_SIM_SOPT5_WR((HW_SIM_SOPT5_RD() & ~BM_SIM_SOPT5_UART0TXSRC) | BF_SIM_SOPT5_UART0TXSRC(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT5, field UART0RXSRC[3:2] (RW)
+ *
+ * Selects the source for the UART 0 receive data.
+ *
+ * Values:
+ * - 00 - UART0_RX pin
+ * - 01 - CMP0
+ * - 10 - CMP1
+ * - 11 - Reserved
+ */
+//@{
+#define BP_SIM_SOPT5_UART0RXSRC (2U) //!< Bit position for SIM_SOPT5_UART0RXSRC.
+#define BM_SIM_SOPT5_UART0RXSRC (0x0000000CU) //!< Bit mask for SIM_SOPT5_UART0RXSRC.
+#define BS_SIM_SOPT5_UART0RXSRC (2U) //!< Bit field size in bits for SIM_SOPT5_UART0RXSRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT5_UART0RXSRC field.
+#define BR_SIM_SOPT5_UART0RXSRC (HW_SIM_SOPT5.B.UART0RXSRC)
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT5_UART0RXSRC.
+#define BF_SIM_SOPT5_UART0RXSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT5_UART0RXSRC), uint32_t) & BM_SIM_SOPT5_UART0RXSRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UART0RXSRC field to a new value.
+#define BW_SIM_SOPT5_UART0RXSRC(v) (HW_SIM_SOPT5_WR((HW_SIM_SOPT5_RD() & ~BM_SIM_SOPT5_UART0RXSRC) | BF_SIM_SOPT5_UART0RXSRC(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT5, field UART1TXSRC[5:4] (RW)
+ *
+ * Selects the source for the UART 1 transmit data.
+ *
+ * Values:
+ * - 00 - UART1_TX pin
+ * - 01 - UART1_TX pin modulated with FTM1 channel 0 output
+ * - 10 - UART1_TX pin modulated with FTM2 channel 0 output
+ * - 11 - Reserved
+ */
+//@{
+#define BP_SIM_SOPT5_UART1TXSRC (4U) //!< Bit position for SIM_SOPT5_UART1TXSRC.
+#define BM_SIM_SOPT5_UART1TXSRC (0x00000030U) //!< Bit mask for SIM_SOPT5_UART1TXSRC.
+#define BS_SIM_SOPT5_UART1TXSRC (2U) //!< Bit field size in bits for SIM_SOPT5_UART1TXSRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT5_UART1TXSRC field.
+#define BR_SIM_SOPT5_UART1TXSRC (HW_SIM_SOPT5.B.UART1TXSRC)
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT5_UART1TXSRC.
+#define BF_SIM_SOPT5_UART1TXSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT5_UART1TXSRC), uint32_t) & BM_SIM_SOPT5_UART1TXSRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UART1TXSRC field to a new value.
+#define BW_SIM_SOPT5_UART1TXSRC(v) (HW_SIM_SOPT5_WR((HW_SIM_SOPT5_RD() & ~BM_SIM_SOPT5_UART1TXSRC) | BF_SIM_SOPT5_UART1TXSRC(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT5, field UART1RXSRC[7:6] (RW)
+ *
+ * Selects the source for the UART 1 receive data.
+ *
+ * Values:
+ * - 00 - UART1_RX pin
+ * - 01 - CMP0
+ * - 10 - CMP1
+ * - 11 - Reserved
+ */
+//@{
+#define BP_SIM_SOPT5_UART1RXSRC (6U) //!< Bit position for SIM_SOPT5_UART1RXSRC.
+#define BM_SIM_SOPT5_UART1RXSRC (0x000000C0U) //!< Bit mask for SIM_SOPT5_UART1RXSRC.
+#define BS_SIM_SOPT5_UART1RXSRC (2U) //!< Bit field size in bits for SIM_SOPT5_UART1RXSRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT5_UART1RXSRC field.
+#define BR_SIM_SOPT5_UART1RXSRC (HW_SIM_SOPT5.B.UART1RXSRC)
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT5_UART1RXSRC.
+#define BF_SIM_SOPT5_UART1RXSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT5_UART1RXSRC), uint32_t) & BM_SIM_SOPT5_UART1RXSRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UART1RXSRC field to a new value.
+#define BW_SIM_SOPT5_UART1RXSRC(v) (HW_SIM_SOPT5_WR((HW_SIM_SOPT5_RD() & ~BM_SIM_SOPT5_UART1RXSRC) | BF_SIM_SOPT5_UART1RXSRC(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_SOPT7 - System Options Register 7
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_SOPT7 - System Options Register 7 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_sim_sopt7
+{
+ uint32_t U;
+ struct _hw_sim_sopt7_bitfields
+ {
+ uint32_t ADC0TRGSEL : 4; //!< [3:0] ADC0 trigger select
+ uint32_t ADC0PRETRGSEL : 1; //!< [4] ADC0 pretrigger select
+ uint32_t RESERVED0 : 2; //!< [6:5]
+ uint32_t ADC0ALTTRGEN : 1; //!< [7] ADC0 alternate trigger enable
+ uint32_t ADC1TRGSEL : 4; //!< [11:8] ADC1 trigger select
+ uint32_t ADC1PRETRGSEL : 1; //!< [12] ADC1 pre-trigger select
+ uint32_t RESERVED1 : 2; //!< [14:13]
+ uint32_t ADC1ALTTRGEN : 1; //!< [15] ADC1 alternate trigger enable
+ uint32_t RESERVED2 : 16; //!< [31:16]
+ } B;
+} hw_sim_sopt7_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_SOPT7 register
+ */
+//@{
+#define HW_SIM_SOPT7_ADDR (REGS_SIM_BASE + 0x1018U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_SOPT7 (*(__IO hw_sim_sopt7_t *) HW_SIM_SOPT7_ADDR)
+#define HW_SIM_SOPT7_RD() (HW_SIM_SOPT7.U)
+#define HW_SIM_SOPT7_WR(v) (HW_SIM_SOPT7.U = (v))
+#define HW_SIM_SOPT7_SET(v) (HW_SIM_SOPT7_WR(HW_SIM_SOPT7_RD() | (v)))
+#define HW_SIM_SOPT7_CLR(v) (HW_SIM_SOPT7_WR(HW_SIM_SOPT7_RD() & ~(v)))
+#define HW_SIM_SOPT7_TOG(v) (HW_SIM_SOPT7_WR(HW_SIM_SOPT7_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_SOPT7 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT7, field ADC0TRGSEL[3:0] (RW)
+ *
+ * Selects the ADC0 trigger source when alternative triggers are functional in
+ * stop and VLPS modes. .
+ *
+ * Values:
+ * - 0000 - PDB external trigger pin input (PDB0_EXTRG)
+ * - 0001 - High speed comparator 0 output
+ * - 0010 - High speed comparator 1 output
+ * - 0011 - High speed comparator 2 output
+ * - 0100 - PIT trigger 0
+ * - 0101 - PIT trigger 1
+ * - 0110 - PIT trigger 2
+ * - 0111 - PIT trigger 3
+ * - 1000 - FTM0 trigger
+ * - 1001 - FTM1 trigger
+ * - 1010 - FTM2 trigger
+ * - 1011 - FTM3 trigger
+ * - 1100 - RTC alarm
+ * - 1101 - RTC seconds
+ * - 1110 - Low-power timer (LPTMR) trigger
+ * - 1111 - Reserved
+ */
+//@{
+#define BP_SIM_SOPT7_ADC0TRGSEL (0U) //!< Bit position for SIM_SOPT7_ADC0TRGSEL.
+#define BM_SIM_SOPT7_ADC0TRGSEL (0x0000000FU) //!< Bit mask for SIM_SOPT7_ADC0TRGSEL.
+#define BS_SIM_SOPT7_ADC0TRGSEL (4U) //!< Bit field size in bits for SIM_SOPT7_ADC0TRGSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT7_ADC0TRGSEL field.
+#define BR_SIM_SOPT7_ADC0TRGSEL (HW_SIM_SOPT7.B.ADC0TRGSEL)
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT7_ADC0TRGSEL.
+#define BF_SIM_SOPT7_ADC0TRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC0TRGSEL), uint32_t) & BM_SIM_SOPT7_ADC0TRGSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADC0TRGSEL field to a new value.
+#define BW_SIM_SOPT7_ADC0TRGSEL(v) (HW_SIM_SOPT7_WR((HW_SIM_SOPT7_RD() & ~BM_SIM_SOPT7_ADC0TRGSEL) | BF_SIM_SOPT7_ADC0TRGSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT7, field ADC0PRETRGSEL[4] (RW)
+ *
+ * Selects the ADC0 pre-trigger source when alternative triggers are enabled
+ * through ADC0ALTTRGEN.
+ *
+ * Values:
+ * - 0 - Pre-trigger A
+ * - 1 - Pre-trigger B
+ */
+//@{
+#define BP_SIM_SOPT7_ADC0PRETRGSEL (4U) //!< Bit position for SIM_SOPT7_ADC0PRETRGSEL.
+#define BM_SIM_SOPT7_ADC0PRETRGSEL (0x00000010U) //!< Bit mask for SIM_SOPT7_ADC0PRETRGSEL.
+#define BS_SIM_SOPT7_ADC0PRETRGSEL (1U) //!< Bit field size in bits for SIM_SOPT7_ADC0PRETRGSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT7_ADC0PRETRGSEL field.
+#define BR_SIM_SOPT7_ADC0PRETRGSEL (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC0PRETRGSEL))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT7_ADC0PRETRGSEL.
+#define BF_SIM_SOPT7_ADC0PRETRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC0PRETRGSEL), uint32_t) & BM_SIM_SOPT7_ADC0PRETRGSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADC0PRETRGSEL field to a new value.
+#define BW_SIM_SOPT7_ADC0PRETRGSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC0PRETRGSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT7, field ADC0ALTTRGEN[7] (RW)
+ *
+ * Enable alternative conversion triggers for ADC0.
+ *
+ * Values:
+ * - 0 - PDB trigger selected for ADC0.
+ * - 1 - Alternate trigger selected for ADC0.
+ */
+//@{
+#define BP_SIM_SOPT7_ADC0ALTTRGEN (7U) //!< Bit position for SIM_SOPT7_ADC0ALTTRGEN.
+#define BM_SIM_SOPT7_ADC0ALTTRGEN (0x00000080U) //!< Bit mask for SIM_SOPT7_ADC0ALTTRGEN.
+#define BS_SIM_SOPT7_ADC0ALTTRGEN (1U) //!< Bit field size in bits for SIM_SOPT7_ADC0ALTTRGEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT7_ADC0ALTTRGEN field.
+#define BR_SIM_SOPT7_ADC0ALTTRGEN (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC0ALTTRGEN))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT7_ADC0ALTTRGEN.
+#define BF_SIM_SOPT7_ADC0ALTTRGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC0ALTTRGEN), uint32_t) & BM_SIM_SOPT7_ADC0ALTTRGEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADC0ALTTRGEN field to a new value.
+#define BW_SIM_SOPT7_ADC0ALTTRGEN(v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC0ALTTRGEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT7, field ADC1TRGSEL[11:8] (RW)
+ *
+ * Selects the ADC1 trigger source when alternative triggers are functional in
+ * stop and VLPS modes.
+ *
+ * Values:
+ * - 0000 - PDB external trigger pin input (PDB0_EXTRG)
+ * - 0001 - High speed comparator 0 output
+ * - 0010 - High speed comparator 1 output
+ * - 0011 - High speed comparator 2 output
+ * - 0100 - PIT trigger 0
+ * - 0101 - PIT trigger 1
+ * - 0110 - PIT trigger 2
+ * - 0111 - PIT trigger 3
+ * - 1000 - FTM0 trigger
+ * - 1001 - FTM1 trigger
+ * - 1010 - FTM2 trigger
+ * - 1011 - FTM3 trigger
+ * - 1100 - RTC alarm
+ * - 1101 - RTC seconds
+ * - 1110 - Low-power timer (LPTMR) trigger
+ * - 1111 - Reserved
+ */
+//@{
+#define BP_SIM_SOPT7_ADC1TRGSEL (8U) //!< Bit position for SIM_SOPT7_ADC1TRGSEL.
+#define BM_SIM_SOPT7_ADC1TRGSEL (0x00000F00U) //!< Bit mask for SIM_SOPT7_ADC1TRGSEL.
+#define BS_SIM_SOPT7_ADC1TRGSEL (4U) //!< Bit field size in bits for SIM_SOPT7_ADC1TRGSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT7_ADC1TRGSEL field.
+#define BR_SIM_SOPT7_ADC1TRGSEL (HW_SIM_SOPT7.B.ADC1TRGSEL)
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT7_ADC1TRGSEL.
+#define BF_SIM_SOPT7_ADC1TRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC1TRGSEL), uint32_t) & BM_SIM_SOPT7_ADC1TRGSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADC1TRGSEL field to a new value.
+#define BW_SIM_SOPT7_ADC1TRGSEL(v) (HW_SIM_SOPT7_WR((HW_SIM_SOPT7_RD() & ~BM_SIM_SOPT7_ADC1TRGSEL) | BF_SIM_SOPT7_ADC1TRGSEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT7, field ADC1PRETRGSEL[12] (RW)
+ *
+ * Selects the ADC1 pre-trigger source when alternative triggers are enabled
+ * through ADC1ALTTRGEN.
+ *
+ * Values:
+ * - 0 - Pre-trigger A selected for ADC1.
+ * - 1 - Pre-trigger B selected for ADC1.
+ */
+//@{
+#define BP_SIM_SOPT7_ADC1PRETRGSEL (12U) //!< Bit position for SIM_SOPT7_ADC1PRETRGSEL.
+#define BM_SIM_SOPT7_ADC1PRETRGSEL (0x00001000U) //!< Bit mask for SIM_SOPT7_ADC1PRETRGSEL.
+#define BS_SIM_SOPT7_ADC1PRETRGSEL (1U) //!< Bit field size in bits for SIM_SOPT7_ADC1PRETRGSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT7_ADC1PRETRGSEL field.
+#define BR_SIM_SOPT7_ADC1PRETRGSEL (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC1PRETRGSEL))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT7_ADC1PRETRGSEL.
+#define BF_SIM_SOPT7_ADC1PRETRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC1PRETRGSEL), uint32_t) & BM_SIM_SOPT7_ADC1PRETRGSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADC1PRETRGSEL field to a new value.
+#define BW_SIM_SOPT7_ADC1PRETRGSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC1PRETRGSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SOPT7, field ADC1ALTTRGEN[15] (RW)
+ *
+ * Enable alternative conversion triggers for ADC1.
+ *
+ * Values:
+ * - 0 - PDB trigger selected for ADC1
+ * - 1 - Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.
+ */
+//@{
+#define BP_SIM_SOPT7_ADC1ALTTRGEN (15U) //!< Bit position for SIM_SOPT7_ADC1ALTTRGEN.
+#define BM_SIM_SOPT7_ADC1ALTTRGEN (0x00008000U) //!< Bit mask for SIM_SOPT7_ADC1ALTTRGEN.
+#define BS_SIM_SOPT7_ADC1ALTTRGEN (1U) //!< Bit field size in bits for SIM_SOPT7_ADC1ALTTRGEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SOPT7_ADC1ALTTRGEN field.
+#define BR_SIM_SOPT7_ADC1ALTTRGEN (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC1ALTTRGEN))
+#endif
+
+//! @brief Format value for bitfield SIM_SOPT7_ADC1ALTTRGEN.
+#define BF_SIM_SOPT7_ADC1ALTTRGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC1ALTTRGEN), uint32_t) & BM_SIM_SOPT7_ADC1ALTTRGEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADC1ALTTRGEN field to a new value.
+#define BW_SIM_SOPT7_ADC1ALTTRGEN(v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC1ALTTRGEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_SDID - System Device Identification Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_SDID - System Device Identification Register (RO)
+ *
+ * Reset value: 0x00000380U
+ */
+typedef union _hw_sim_sdid
+{
+ uint32_t U;
+ struct _hw_sim_sdid_bitfields
+ {
+ uint32_t PINID : 4; //!< [3:0] Pincount identification
+ uint32_t FAMID : 3; //!< [6:4] Kinetis family identification
+ uint32_t DIEID : 5; //!< [11:7] Device Die ID
+ uint32_t REVID : 4; //!< [15:12] Device revision number
+ uint32_t RESERVED0 : 4; //!< [19:16]
+ uint32_t SERIESID : 4; //!< [23:20] Kinetis Series ID
+ uint32_t SUBFAMID : 4; //!< [27:24] Kinetis Sub-Family ID
+ uint32_t FAMILYID : 4; //!< [31:28] Kinetis Family ID
+ } B;
+} hw_sim_sdid_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_SDID register
+ */
+//@{
+#define HW_SIM_SDID_ADDR (REGS_SIM_BASE + 0x1024U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_SDID (*(__I hw_sim_sdid_t *) HW_SIM_SDID_ADDR)
+#define HW_SIM_SDID_RD() (HW_SIM_SDID.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_SDID bitfields
+ */
+
+/*!
+ * @name Register SIM_SDID, field PINID[3:0] (RO)
+ *
+ * Specifies the pincount of the device.
+ *
+ * Values:
+ * - 0000 - Reserved
+ * - 0001 - Reserved
+ * - 0010 - 32-pin
+ * - 0011 - Reserved
+ * - 0100 - 48-pin
+ * - 0101 - 64-pin
+ * - 0110 - 80-pin
+ * - 0111 - 81-pin or 121-pin
+ * - 1000 - 100-pin
+ * - 1001 - 121-pin
+ * - 1010 - 144-pin
+ * - 1011 - Custom pinout (WLCSP)
+ * - 1100 - 169-pin
+ * - 1101 - Reserved
+ * - 1110 - 256-pin
+ * - 1111 - Reserved
+ */
+//@{
+#define BP_SIM_SDID_PINID (0U) //!< Bit position for SIM_SDID_PINID.
+#define BM_SIM_SDID_PINID (0x0000000FU) //!< Bit mask for SIM_SDID_PINID.
+#define BS_SIM_SDID_PINID (4U) //!< Bit field size in bits for SIM_SDID_PINID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SDID_PINID field.
+#define BR_SIM_SDID_PINID (HW_SIM_SDID.B.PINID)
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SDID, field FAMID[6:4] (RO)
+ *
+ * This field is maintained for compatibility only, but has been superceded by
+ * the SERIESID, FAMILYID and SUBFAMID fields in this register.
+ *
+ * Values:
+ * - 000 - K1x Family (without tamper)
+ * - 001 - K2x Family (without tamper)
+ * - 010 - K3x Family or K1x/K6x Family (with tamper)
+ * - 011 - K4x Family or K2x Family (with tamper)
+ * - 100 - K6x Family (without tamper)
+ * - 101 - K7x Family
+ * - 110 - Reserved
+ * - 111 - Reserved
+ */
+//@{
+#define BP_SIM_SDID_FAMID (4U) //!< Bit position for SIM_SDID_FAMID.
+#define BM_SIM_SDID_FAMID (0x00000070U) //!< Bit mask for SIM_SDID_FAMID.
+#define BS_SIM_SDID_FAMID (3U) //!< Bit field size in bits for SIM_SDID_FAMID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SDID_FAMID field.
+#define BR_SIM_SDID_FAMID (HW_SIM_SDID.B.FAMID)
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SDID, field DIEID[11:7] (RO)
+ *
+ * Specifies the silicon feature set identication number for the device.
+ */
+//@{
+#define BP_SIM_SDID_DIEID (7U) //!< Bit position for SIM_SDID_DIEID.
+#define BM_SIM_SDID_DIEID (0x00000F80U) //!< Bit mask for SIM_SDID_DIEID.
+#define BS_SIM_SDID_DIEID (5U) //!< Bit field size in bits for SIM_SDID_DIEID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SDID_DIEID field.
+#define BR_SIM_SDID_DIEID (HW_SIM_SDID.B.DIEID)
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SDID, field REVID[15:12] (RO)
+ *
+ * Specifies the silicon implementation number for the device.
+ */
+//@{
+#define BP_SIM_SDID_REVID (12U) //!< Bit position for SIM_SDID_REVID.
+#define BM_SIM_SDID_REVID (0x0000F000U) //!< Bit mask for SIM_SDID_REVID.
+#define BS_SIM_SDID_REVID (4U) //!< Bit field size in bits for SIM_SDID_REVID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SDID_REVID field.
+#define BR_SIM_SDID_REVID (HW_SIM_SDID.B.REVID)
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SDID, field SERIESID[23:20] (RO)
+ *
+ * Specifies the Kinetis series of the device.
+ *
+ * Values:
+ * - 0000 - Kinetis K series
+ * - 0001 - Kinetis L series
+ * - 0101 - Kinetis W series
+ * - 0110 - Kinetis V series
+ */
+//@{
+#define BP_SIM_SDID_SERIESID (20U) //!< Bit position for SIM_SDID_SERIESID.
+#define BM_SIM_SDID_SERIESID (0x00F00000U) //!< Bit mask for SIM_SDID_SERIESID.
+#define BS_SIM_SDID_SERIESID (4U) //!< Bit field size in bits for SIM_SDID_SERIESID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SDID_SERIESID field.
+#define BR_SIM_SDID_SERIESID (HW_SIM_SDID.B.SERIESID)
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SDID, field SUBFAMID[27:24] (RO)
+ *
+ * Specifies the Kinetis sub-family of the device.
+ *
+ * Values:
+ * - 0000 - Kx0 Subfamily
+ * - 0001 - Kx1 Subfamily (tamper detect)
+ * - 0010 - Kx2 Subfamily
+ * - 0011 - Kx3 Subfamily (tamper detect)
+ * - 0100 - Kx4 Subfamily
+ * - 0101 - Kx5 Subfamily (tamper detect)
+ * - 0110 - Kx6 Subfamily
+ */
+//@{
+#define BP_SIM_SDID_SUBFAMID (24U) //!< Bit position for SIM_SDID_SUBFAMID.
+#define BM_SIM_SDID_SUBFAMID (0x0F000000U) //!< Bit mask for SIM_SDID_SUBFAMID.
+#define BS_SIM_SDID_SUBFAMID (4U) //!< Bit field size in bits for SIM_SDID_SUBFAMID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SDID_SUBFAMID field.
+#define BR_SIM_SDID_SUBFAMID (HW_SIM_SDID.B.SUBFAMID)
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SDID, field FAMILYID[31:28] (RO)
+ *
+ * Specifies the Kinetis family of the device.
+ *
+ * Values:
+ * - 0001 - K1x Family
+ * - 0010 - K2x Family
+ * - 0011 - K3x Family
+ * - 0100 - K4x Family
+ * - 0110 - K6x Family
+ * - 0111 - K7x Family
+ */
+//@{
+#define BP_SIM_SDID_FAMILYID (28U) //!< Bit position for SIM_SDID_FAMILYID.
+#define BM_SIM_SDID_FAMILYID (0xF0000000U) //!< Bit mask for SIM_SDID_FAMILYID.
+#define BS_SIM_SDID_FAMILYID (4U) //!< Bit field size in bits for SIM_SDID_FAMILYID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SDID_FAMILYID field.
+#define BR_SIM_SDID_FAMILYID (HW_SIM_SDID.B.FAMILYID)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_SCGC1 - System Clock Gating Control Register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_SCGC1 - System Clock Gating Control Register 1 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_sim_scgc1
+{
+ uint32_t U;
+ struct _hw_sim_scgc1_bitfields
+ {
+ uint32_t RESERVED0 : 6; //!< [5:0]
+ uint32_t I2C2b : 1; //!< [6] I2C2 Clock Gate Control
+ uint32_t RESERVED1 : 3; //!< [9:7]
+ uint32_t UART4b : 1; //!< [10] UART4 Clock Gate Control
+ uint32_t UART5b : 1; //!< [11] UART5 Clock Gate Control
+ uint32_t RESERVED2 : 20; //!< [31:12]
+ } B;
+} hw_sim_scgc1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_SCGC1 register
+ */
+//@{
+#define HW_SIM_SCGC1_ADDR (REGS_SIM_BASE + 0x1028U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_SCGC1 (*(__IO hw_sim_scgc1_t *) HW_SIM_SCGC1_ADDR)
+#define HW_SIM_SCGC1_RD() (HW_SIM_SCGC1.U)
+#define HW_SIM_SCGC1_WR(v) (HW_SIM_SCGC1.U = (v))
+#define HW_SIM_SCGC1_SET(v) (HW_SIM_SCGC1_WR(HW_SIM_SCGC1_RD() | (v)))
+#define HW_SIM_SCGC1_CLR(v) (HW_SIM_SCGC1_WR(HW_SIM_SCGC1_RD() & ~(v)))
+#define HW_SIM_SCGC1_TOG(v) (HW_SIM_SCGC1_WR(HW_SIM_SCGC1_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_SCGC1 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC1, field I2C2[6] (RW)
+ *
+ * This bit controls the clock gate to the I2C2 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC1_I2C2 (6U) //!< Bit position for SIM_SCGC1_I2C2.
+#define BM_SIM_SCGC1_I2C2 (0x00000040U) //!< Bit mask for SIM_SCGC1_I2C2.
+#define BS_SIM_SCGC1_I2C2 (1U) //!< Bit field size in bits for SIM_SCGC1_I2C2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC1_I2C2 field.
+#define BR_SIM_SCGC1_I2C2 (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_I2C2))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC1_I2C2.
+#define BF_SIM_SCGC1_I2C2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC1_I2C2), uint32_t) & BM_SIM_SCGC1_I2C2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the I2C2 field to a new value.
+#define BW_SIM_SCGC1_I2C2(v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_I2C2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC1, field UART4[10] (RW)
+ *
+ * This bit controls the clock gate to the UART4 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC1_UART4 (10U) //!< Bit position for SIM_SCGC1_UART4.
+#define BM_SIM_SCGC1_UART4 (0x00000400U) //!< Bit mask for SIM_SCGC1_UART4.
+#define BS_SIM_SCGC1_UART4 (1U) //!< Bit field size in bits for SIM_SCGC1_UART4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC1_UART4 field.
+#define BR_SIM_SCGC1_UART4 (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_UART4))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC1_UART4.
+#define BF_SIM_SCGC1_UART4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC1_UART4), uint32_t) & BM_SIM_SCGC1_UART4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UART4 field to a new value.
+#define BW_SIM_SCGC1_UART4(v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_UART4) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC1, field UART5[11] (RW)
+ *
+ * This bit controls the clock gate to the UART5 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC1_UART5 (11U) //!< Bit position for SIM_SCGC1_UART5.
+#define BM_SIM_SCGC1_UART5 (0x00000800U) //!< Bit mask for SIM_SCGC1_UART5.
+#define BS_SIM_SCGC1_UART5 (1U) //!< Bit field size in bits for SIM_SCGC1_UART5.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC1_UART5 field.
+#define BR_SIM_SCGC1_UART5 (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_UART5))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC1_UART5.
+#define BF_SIM_SCGC1_UART5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC1_UART5), uint32_t) & BM_SIM_SCGC1_UART5)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UART5 field to a new value.
+#define BW_SIM_SCGC1_UART5(v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_UART5) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_SCGC2 - System Clock Gating Control Register 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_SCGC2 - System Clock Gating Control Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * DAC0 can be accessed through both AIPS0 and AIPS1. When accessing through
+ * AIPS1, define the clock gate control bits in the SCGC2. When accessing through
+ * AIPS0, define the clock gate control bits in SCGC6.
+ */
+typedef union _hw_sim_scgc2
+{
+ uint32_t U;
+ struct _hw_sim_scgc2_bitfields
+ {
+ uint32_t ENETb : 1; //!< [0] ENET Clock Gate Control
+ uint32_t RESERVED0 : 11; //!< [11:1]
+ uint32_t DAC0b : 1; //!< [12] DAC0 Clock Gate Control
+ uint32_t DAC1b : 1; //!< [13] DAC1 Clock Gate Control
+ uint32_t RESERVED1 : 18; //!< [31:14]
+ } B;
+} hw_sim_scgc2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_SCGC2 register
+ */
+//@{
+#define HW_SIM_SCGC2_ADDR (REGS_SIM_BASE + 0x102CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_SCGC2 (*(__IO hw_sim_scgc2_t *) HW_SIM_SCGC2_ADDR)
+#define HW_SIM_SCGC2_RD() (HW_SIM_SCGC2.U)
+#define HW_SIM_SCGC2_WR(v) (HW_SIM_SCGC2.U = (v))
+#define HW_SIM_SCGC2_SET(v) (HW_SIM_SCGC2_WR(HW_SIM_SCGC2_RD() | (v)))
+#define HW_SIM_SCGC2_CLR(v) (HW_SIM_SCGC2_WR(HW_SIM_SCGC2_RD() & ~(v)))
+#define HW_SIM_SCGC2_TOG(v) (HW_SIM_SCGC2_WR(HW_SIM_SCGC2_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_SCGC2 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC2, field ENET[0] (RW)
+ *
+ * This bit controls the clock gate to the ENET module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC2_ENET (0U) //!< Bit position for SIM_SCGC2_ENET.
+#define BM_SIM_SCGC2_ENET (0x00000001U) //!< Bit mask for SIM_SCGC2_ENET.
+#define BS_SIM_SCGC2_ENET (1U) //!< Bit field size in bits for SIM_SCGC2_ENET.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC2_ENET field.
+#define BR_SIM_SCGC2_ENET (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_ENET))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC2_ENET.
+#define BF_SIM_SCGC2_ENET(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC2_ENET), uint32_t) & BM_SIM_SCGC2_ENET)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ENET field to a new value.
+#define BW_SIM_SCGC2_ENET(v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_ENET) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC2, field DAC0[12] (RW)
+ *
+ * This bit controls the clock gate to the DAC0 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC2_DAC0 (12U) //!< Bit position for SIM_SCGC2_DAC0.
+#define BM_SIM_SCGC2_DAC0 (0x00001000U) //!< Bit mask for SIM_SCGC2_DAC0.
+#define BS_SIM_SCGC2_DAC0 (1U) //!< Bit field size in bits for SIM_SCGC2_DAC0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC2_DAC0 field.
+#define BR_SIM_SCGC2_DAC0 (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_DAC0))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC2_DAC0.
+#define BF_SIM_SCGC2_DAC0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC2_DAC0), uint32_t) & BM_SIM_SCGC2_DAC0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DAC0 field to a new value.
+#define BW_SIM_SCGC2_DAC0(v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_DAC0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC2, field DAC1[13] (RW)
+ *
+ * This bit controls the clock gate to the DAC1 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC2_DAC1 (13U) //!< Bit position for SIM_SCGC2_DAC1.
+#define BM_SIM_SCGC2_DAC1 (0x00002000U) //!< Bit mask for SIM_SCGC2_DAC1.
+#define BS_SIM_SCGC2_DAC1 (1U) //!< Bit field size in bits for SIM_SCGC2_DAC1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC2_DAC1 field.
+#define BR_SIM_SCGC2_DAC1 (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_DAC1))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC2_DAC1.
+#define BF_SIM_SCGC2_DAC1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC2_DAC1), uint32_t) & BM_SIM_SCGC2_DAC1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DAC1 field to a new value.
+#define BW_SIM_SCGC2_DAC1(v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_DAC1) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_SCGC3 - System Clock Gating Control Register 3
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_SCGC3 - System Clock Gating Control Register 3 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * FTM2 and RNGA can be accessed through both AIPS0 and AIPS1. When accessing
+ * through AIPS1, define the clock gate control bits in the SCGC3. When accessing
+ * through AIPS0, define the clock gate control bits in SCGC6.
+ */
+typedef union _hw_sim_scgc3
+{
+ uint32_t U;
+ struct _hw_sim_scgc3_bitfields
+ {
+ uint32_t RNGA : 1; //!< [0] RNGA Clock Gate Control
+ uint32_t RESERVED0 : 11; //!< [11:1]
+ uint32_t SPI2b : 1; //!< [12] SPI2 Clock Gate Control
+ uint32_t RESERVED1 : 4; //!< [16:13]
+ uint32_t SDHCb : 1; //!< [17] SDHC Clock Gate Control
+ uint32_t RESERVED2 : 6; //!< [23:18]
+ uint32_t FTM2b : 1; //!< [24] FTM2 Clock Gate Control
+ uint32_t FTM3b : 1; //!< [25] FTM3 Clock Gate Control
+ uint32_t RESERVED3 : 1; //!< [26]
+ uint32_t ADC1b : 1; //!< [27] ADC1 Clock Gate Control
+ uint32_t RESERVED4 : 4; //!< [31:28]
+ } B;
+} hw_sim_scgc3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_SCGC3 register
+ */
+//@{
+#define HW_SIM_SCGC3_ADDR (REGS_SIM_BASE + 0x1030U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_SCGC3 (*(__IO hw_sim_scgc3_t *) HW_SIM_SCGC3_ADDR)
+#define HW_SIM_SCGC3_RD() (HW_SIM_SCGC3.U)
+#define HW_SIM_SCGC3_WR(v) (HW_SIM_SCGC3.U = (v))
+#define HW_SIM_SCGC3_SET(v) (HW_SIM_SCGC3_WR(HW_SIM_SCGC3_RD() | (v)))
+#define HW_SIM_SCGC3_CLR(v) (HW_SIM_SCGC3_WR(HW_SIM_SCGC3_RD() & ~(v)))
+#define HW_SIM_SCGC3_TOG(v) (HW_SIM_SCGC3_WR(HW_SIM_SCGC3_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_SCGC3 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC3, field RNGA[0] (RW)
+ *
+ * This bit controls the clock gate to the RNGA module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC3_RNGA (0U) //!< Bit position for SIM_SCGC3_RNGA.
+#define BM_SIM_SCGC3_RNGA (0x00000001U) //!< Bit mask for SIM_SCGC3_RNGA.
+#define BS_SIM_SCGC3_RNGA (1U) //!< Bit field size in bits for SIM_SCGC3_RNGA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC3_RNGA field.
+#define BR_SIM_SCGC3_RNGA (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_RNGA))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC3_RNGA.
+#define BF_SIM_SCGC3_RNGA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_RNGA), uint32_t) & BM_SIM_SCGC3_RNGA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RNGA field to a new value.
+#define BW_SIM_SCGC3_RNGA(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_RNGA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC3, field SPI2[12] (RW)
+ *
+ * This bit controls the clock gate to the SPI2 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC3_SPI2 (12U) //!< Bit position for SIM_SCGC3_SPI2.
+#define BM_SIM_SCGC3_SPI2 (0x00001000U) //!< Bit mask for SIM_SCGC3_SPI2.
+#define BS_SIM_SCGC3_SPI2 (1U) //!< Bit field size in bits for SIM_SCGC3_SPI2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC3_SPI2 field.
+#define BR_SIM_SCGC3_SPI2 (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_SPI2))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC3_SPI2.
+#define BF_SIM_SCGC3_SPI2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_SPI2), uint32_t) & BM_SIM_SCGC3_SPI2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SPI2 field to a new value.
+#define BW_SIM_SCGC3_SPI2(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_SPI2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC3, field SDHC[17] (RW)
+ *
+ * This bit controls the clock gate to the SDHC module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC3_SDHC (17U) //!< Bit position for SIM_SCGC3_SDHC.
+#define BM_SIM_SCGC3_SDHC (0x00020000U) //!< Bit mask for SIM_SCGC3_SDHC.
+#define BS_SIM_SCGC3_SDHC (1U) //!< Bit field size in bits for SIM_SCGC3_SDHC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC3_SDHC field.
+#define BR_SIM_SCGC3_SDHC (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_SDHC))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC3_SDHC.
+#define BF_SIM_SCGC3_SDHC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_SDHC), uint32_t) & BM_SIM_SCGC3_SDHC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SDHC field to a new value.
+#define BW_SIM_SCGC3_SDHC(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_SDHC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC3, field FTM2[24] (RW)
+ *
+ * This bit controls the clock gate to the FTM2 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC3_FTM2 (24U) //!< Bit position for SIM_SCGC3_FTM2.
+#define BM_SIM_SCGC3_FTM2 (0x01000000U) //!< Bit mask for SIM_SCGC3_FTM2.
+#define BS_SIM_SCGC3_FTM2 (1U) //!< Bit field size in bits for SIM_SCGC3_FTM2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC3_FTM2 field.
+#define BR_SIM_SCGC3_FTM2 (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_FTM2))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC3_FTM2.
+#define BF_SIM_SCGC3_FTM2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_FTM2), uint32_t) & BM_SIM_SCGC3_FTM2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM2 field to a new value.
+#define BW_SIM_SCGC3_FTM2(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_FTM2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC3, field FTM3[25] (RW)
+ *
+ * This bit controls the clock gate to the FTM3 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC3_FTM3 (25U) //!< Bit position for SIM_SCGC3_FTM3.
+#define BM_SIM_SCGC3_FTM3 (0x02000000U) //!< Bit mask for SIM_SCGC3_FTM3.
+#define BS_SIM_SCGC3_FTM3 (1U) //!< Bit field size in bits for SIM_SCGC3_FTM3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC3_FTM3 field.
+#define BR_SIM_SCGC3_FTM3 (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_FTM3))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC3_FTM3.
+#define BF_SIM_SCGC3_FTM3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_FTM3), uint32_t) & BM_SIM_SCGC3_FTM3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM3 field to a new value.
+#define BW_SIM_SCGC3_FTM3(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_FTM3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC3, field ADC1[27] (RW)
+ *
+ * This bit controls the clock gate to the ADC1 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC3_ADC1 (27U) //!< Bit position for SIM_SCGC3_ADC1.
+#define BM_SIM_SCGC3_ADC1 (0x08000000U) //!< Bit mask for SIM_SCGC3_ADC1.
+#define BS_SIM_SCGC3_ADC1 (1U) //!< Bit field size in bits for SIM_SCGC3_ADC1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC3_ADC1 field.
+#define BR_SIM_SCGC3_ADC1 (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_ADC1))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC3_ADC1.
+#define BF_SIM_SCGC3_ADC1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_ADC1), uint32_t) & BM_SIM_SCGC3_ADC1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADC1 field to a new value.
+#define BW_SIM_SCGC3_ADC1(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_ADC1) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_SCGC4 - System Clock Gating Control Register 4
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_SCGC4 - System Clock Gating Control Register 4 (RW)
+ *
+ * Reset value: 0xF0100030U
+ */
+typedef union _hw_sim_scgc4
+{
+ uint32_t U;
+ struct _hw_sim_scgc4_bitfields
+ {
+ uint32_t RESERVED0 : 1; //!< [0]
+ uint32_t EWMb : 1; //!< [1] EWM Clock Gate Control
+ uint32_t CMTb : 1; //!< [2] CMT Clock Gate Control
+ uint32_t RESERVED1 : 3; //!< [5:3]
+ uint32_t I2C0b : 1; //!< [6] I2C0 Clock Gate Control
+ uint32_t I2C1b : 1; //!< [7] I2C1 Clock Gate Control
+ uint32_t RESERVED2 : 2; //!< [9:8]
+ uint32_t UART0b : 1; //!< [10] UART0 Clock Gate Control
+ uint32_t UART1b : 1; //!< [11] UART1 Clock Gate Control
+ uint32_t UART2b : 1; //!< [12] UART2 Clock Gate Control
+ uint32_t UART3b : 1; //!< [13] UART3 Clock Gate Control
+ uint32_t RESERVED3 : 4; //!< [17:14]
+ uint32_t USBOTG : 1; //!< [18] USB Clock Gate Control
+ uint32_t CMP : 1; //!< [19] Comparator Clock Gate Control
+ uint32_t VREFb : 1; //!< [20] VREF Clock Gate Control
+ uint32_t RESERVED4 : 11; //!< [31:21]
+ } B;
+} hw_sim_scgc4_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_SCGC4 register
+ */
+//@{
+#define HW_SIM_SCGC4_ADDR (REGS_SIM_BASE + 0x1034U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_SCGC4 (*(__IO hw_sim_scgc4_t *) HW_SIM_SCGC4_ADDR)
+#define HW_SIM_SCGC4_RD() (HW_SIM_SCGC4.U)
+#define HW_SIM_SCGC4_WR(v) (HW_SIM_SCGC4.U = (v))
+#define HW_SIM_SCGC4_SET(v) (HW_SIM_SCGC4_WR(HW_SIM_SCGC4_RD() | (v)))
+#define HW_SIM_SCGC4_CLR(v) (HW_SIM_SCGC4_WR(HW_SIM_SCGC4_RD() & ~(v)))
+#define HW_SIM_SCGC4_TOG(v) (HW_SIM_SCGC4_WR(HW_SIM_SCGC4_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_SCGC4 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC4, field EWM[1] (RW)
+ *
+ * This bit controls the clock gate to the EWM module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC4_EWM (1U) //!< Bit position for SIM_SCGC4_EWM.
+#define BM_SIM_SCGC4_EWM (0x00000002U) //!< Bit mask for SIM_SCGC4_EWM.
+#define BS_SIM_SCGC4_EWM (1U) //!< Bit field size in bits for SIM_SCGC4_EWM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC4_EWM field.
+#define BR_SIM_SCGC4_EWM (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_EWM))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC4_EWM.
+#define BF_SIM_SCGC4_EWM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_EWM), uint32_t) & BM_SIM_SCGC4_EWM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EWM field to a new value.
+#define BW_SIM_SCGC4_EWM(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_EWM) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC4, field CMT[2] (RW)
+ *
+ * This bit controls the clock gate to the CMT module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC4_CMT (2U) //!< Bit position for SIM_SCGC4_CMT.
+#define BM_SIM_SCGC4_CMT (0x00000004U) //!< Bit mask for SIM_SCGC4_CMT.
+#define BS_SIM_SCGC4_CMT (1U) //!< Bit field size in bits for SIM_SCGC4_CMT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC4_CMT field.
+#define BR_SIM_SCGC4_CMT (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_CMT))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC4_CMT.
+#define BF_SIM_SCGC4_CMT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_CMT), uint32_t) & BM_SIM_SCGC4_CMT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CMT field to a new value.
+#define BW_SIM_SCGC4_CMT(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_CMT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC4, field I2C0[6] (RW)
+ *
+ * This bit controls the clock gate to the I 2 C0 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC4_I2C0 (6U) //!< Bit position for SIM_SCGC4_I2C0.
+#define BM_SIM_SCGC4_I2C0 (0x00000040U) //!< Bit mask for SIM_SCGC4_I2C0.
+#define BS_SIM_SCGC4_I2C0 (1U) //!< Bit field size in bits for SIM_SCGC4_I2C0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC4_I2C0 field.
+#define BR_SIM_SCGC4_I2C0 (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_I2C0))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC4_I2C0.
+#define BF_SIM_SCGC4_I2C0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_I2C0), uint32_t) & BM_SIM_SCGC4_I2C0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the I2C0 field to a new value.
+#define BW_SIM_SCGC4_I2C0(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_I2C0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC4, field I2C1[7] (RW)
+ *
+ * This bit controls the clock gate to the I 2 C1 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC4_I2C1 (7U) //!< Bit position for SIM_SCGC4_I2C1.
+#define BM_SIM_SCGC4_I2C1 (0x00000080U) //!< Bit mask for SIM_SCGC4_I2C1.
+#define BS_SIM_SCGC4_I2C1 (1U) //!< Bit field size in bits for SIM_SCGC4_I2C1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC4_I2C1 field.
+#define BR_SIM_SCGC4_I2C1 (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_I2C1))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC4_I2C1.
+#define BF_SIM_SCGC4_I2C1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_I2C1), uint32_t) & BM_SIM_SCGC4_I2C1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the I2C1 field to a new value.
+#define BW_SIM_SCGC4_I2C1(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_I2C1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC4, field UART0[10] (RW)
+ *
+ * This bit controls the clock gate to the UART0 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC4_UART0 (10U) //!< Bit position for SIM_SCGC4_UART0.
+#define BM_SIM_SCGC4_UART0 (0x00000400U) //!< Bit mask for SIM_SCGC4_UART0.
+#define BS_SIM_SCGC4_UART0 (1U) //!< Bit field size in bits for SIM_SCGC4_UART0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC4_UART0 field.
+#define BR_SIM_SCGC4_UART0 (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART0))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC4_UART0.
+#define BF_SIM_SCGC4_UART0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_UART0), uint32_t) & BM_SIM_SCGC4_UART0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UART0 field to a new value.
+#define BW_SIM_SCGC4_UART0(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC4, field UART1[11] (RW)
+ *
+ * This bit controls the clock gate to the UART1 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC4_UART1 (11U) //!< Bit position for SIM_SCGC4_UART1.
+#define BM_SIM_SCGC4_UART1 (0x00000800U) //!< Bit mask for SIM_SCGC4_UART1.
+#define BS_SIM_SCGC4_UART1 (1U) //!< Bit field size in bits for SIM_SCGC4_UART1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC4_UART1 field.
+#define BR_SIM_SCGC4_UART1 (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART1))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC4_UART1.
+#define BF_SIM_SCGC4_UART1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_UART1), uint32_t) & BM_SIM_SCGC4_UART1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UART1 field to a new value.
+#define BW_SIM_SCGC4_UART1(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC4, field UART2[12] (RW)
+ *
+ * This bit controls the clock gate to the UART2 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC4_UART2 (12U) //!< Bit position for SIM_SCGC4_UART2.
+#define BM_SIM_SCGC4_UART2 (0x00001000U) //!< Bit mask for SIM_SCGC4_UART2.
+#define BS_SIM_SCGC4_UART2 (1U) //!< Bit field size in bits for SIM_SCGC4_UART2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC4_UART2 field.
+#define BR_SIM_SCGC4_UART2 (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART2))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC4_UART2.
+#define BF_SIM_SCGC4_UART2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_UART2), uint32_t) & BM_SIM_SCGC4_UART2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UART2 field to a new value.
+#define BW_SIM_SCGC4_UART2(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC4, field UART3[13] (RW)
+ *
+ * This bit controls the clock gate to the UART3 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC4_UART3 (13U) //!< Bit position for SIM_SCGC4_UART3.
+#define BM_SIM_SCGC4_UART3 (0x00002000U) //!< Bit mask for SIM_SCGC4_UART3.
+#define BS_SIM_SCGC4_UART3 (1U) //!< Bit field size in bits for SIM_SCGC4_UART3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC4_UART3 field.
+#define BR_SIM_SCGC4_UART3 (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART3))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC4_UART3.
+#define BF_SIM_SCGC4_UART3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_UART3), uint32_t) & BM_SIM_SCGC4_UART3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UART3 field to a new value.
+#define BW_SIM_SCGC4_UART3(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART3) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC4, field USBOTG[18] (RW)
+ *
+ * This bit controls the clock gate to the USB module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC4_USBOTG (18U) //!< Bit position for SIM_SCGC4_USBOTG.
+#define BM_SIM_SCGC4_USBOTG (0x00040000U) //!< Bit mask for SIM_SCGC4_USBOTG.
+#define BS_SIM_SCGC4_USBOTG (1U) //!< Bit field size in bits for SIM_SCGC4_USBOTG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC4_USBOTG field.
+#define BR_SIM_SCGC4_USBOTG (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_USBOTG))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC4_USBOTG.
+#define BF_SIM_SCGC4_USBOTG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_USBOTG), uint32_t) & BM_SIM_SCGC4_USBOTG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the USBOTG field to a new value.
+#define BW_SIM_SCGC4_USBOTG(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_USBOTG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC4, field CMP[19] (RW)
+ *
+ * This bit controls the clock gate to the comparator module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC4_CMP (19U) //!< Bit position for SIM_SCGC4_CMP.
+#define BM_SIM_SCGC4_CMP (0x00080000U) //!< Bit mask for SIM_SCGC4_CMP.
+#define BS_SIM_SCGC4_CMP (1U) //!< Bit field size in bits for SIM_SCGC4_CMP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC4_CMP field.
+#define BR_SIM_SCGC4_CMP (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_CMP))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC4_CMP.
+#define BF_SIM_SCGC4_CMP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_CMP), uint32_t) & BM_SIM_SCGC4_CMP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CMP field to a new value.
+#define BW_SIM_SCGC4_CMP(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_CMP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC4, field VREF[20] (RW)
+ *
+ * This bit controls the clock gate to the VREF module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC4_VREF (20U) //!< Bit position for SIM_SCGC4_VREF.
+#define BM_SIM_SCGC4_VREF (0x00100000U) //!< Bit mask for SIM_SCGC4_VREF.
+#define BS_SIM_SCGC4_VREF (1U) //!< Bit field size in bits for SIM_SCGC4_VREF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC4_VREF field.
+#define BR_SIM_SCGC4_VREF (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_VREF))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC4_VREF.
+#define BF_SIM_SCGC4_VREF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_VREF), uint32_t) & BM_SIM_SCGC4_VREF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the VREF field to a new value.
+#define BW_SIM_SCGC4_VREF(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_VREF) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_SCGC5 - System Clock Gating Control Register 5
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_SCGC5 - System Clock Gating Control Register 5 (RW)
+ *
+ * Reset value: 0x00040182U
+ */
+typedef union _hw_sim_scgc5
+{
+ uint32_t U;
+ struct _hw_sim_scgc5_bitfields
+ {
+ uint32_t LPTMR : 1; //!< [0] Low Power Timer Access Control
+ uint32_t RESERVED0 : 8; //!< [8:1]
+ uint32_t PORTAb : 1; //!< [9] Port A Clock Gate Control
+ uint32_t PORTBb : 1; //!< [10] Port B Clock Gate Control
+ uint32_t PORTCb : 1; //!< [11] Port C Clock Gate Control
+ uint32_t PORTDb : 1; //!< [12] Port D Clock Gate Control
+ uint32_t PORTEb : 1; //!< [13] Port E Clock Gate Control
+ uint32_t RESERVED1 : 18; //!< [31:14]
+ } B;
+} hw_sim_scgc5_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_SCGC5 register
+ */
+//@{
+#define HW_SIM_SCGC5_ADDR (REGS_SIM_BASE + 0x1038U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_SCGC5 (*(__IO hw_sim_scgc5_t *) HW_SIM_SCGC5_ADDR)
+#define HW_SIM_SCGC5_RD() (HW_SIM_SCGC5.U)
+#define HW_SIM_SCGC5_WR(v) (HW_SIM_SCGC5.U = (v))
+#define HW_SIM_SCGC5_SET(v) (HW_SIM_SCGC5_WR(HW_SIM_SCGC5_RD() | (v)))
+#define HW_SIM_SCGC5_CLR(v) (HW_SIM_SCGC5_WR(HW_SIM_SCGC5_RD() & ~(v)))
+#define HW_SIM_SCGC5_TOG(v) (HW_SIM_SCGC5_WR(HW_SIM_SCGC5_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_SCGC5 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC5, field LPTMR[0] (RW)
+ *
+ * This bit controls software access to the Low Power Timer module.
+ *
+ * Values:
+ * - 0 - Access disabled
+ * - 1 - Access enabled
+ */
+//@{
+#define BP_SIM_SCGC5_LPTMR (0U) //!< Bit position for SIM_SCGC5_LPTMR.
+#define BM_SIM_SCGC5_LPTMR (0x00000001U) //!< Bit mask for SIM_SCGC5_LPTMR.
+#define BS_SIM_SCGC5_LPTMR (1U) //!< Bit field size in bits for SIM_SCGC5_LPTMR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC5_LPTMR field.
+#define BR_SIM_SCGC5_LPTMR (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_LPTMR))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC5_LPTMR.
+#define BF_SIM_SCGC5_LPTMR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_LPTMR), uint32_t) & BM_SIM_SCGC5_LPTMR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LPTMR field to a new value.
+#define BW_SIM_SCGC5_LPTMR(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_LPTMR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC5, field PORTA[9] (RW)
+ *
+ * This bit controls the clock gate to the Port A module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC5_PORTA (9U) //!< Bit position for SIM_SCGC5_PORTA.
+#define BM_SIM_SCGC5_PORTA (0x00000200U) //!< Bit mask for SIM_SCGC5_PORTA.
+#define BS_SIM_SCGC5_PORTA (1U) //!< Bit field size in bits for SIM_SCGC5_PORTA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC5_PORTA field.
+#define BR_SIM_SCGC5_PORTA (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTA))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC5_PORTA.
+#define BF_SIM_SCGC5_PORTA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_PORTA), uint32_t) & BM_SIM_SCGC5_PORTA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PORTA field to a new value.
+#define BW_SIM_SCGC5_PORTA(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC5, field PORTB[10] (RW)
+ *
+ * This bit controls the clock gate to the Port B module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC5_PORTB (10U) //!< Bit position for SIM_SCGC5_PORTB.
+#define BM_SIM_SCGC5_PORTB (0x00000400U) //!< Bit mask for SIM_SCGC5_PORTB.
+#define BS_SIM_SCGC5_PORTB (1U) //!< Bit field size in bits for SIM_SCGC5_PORTB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC5_PORTB field.
+#define BR_SIM_SCGC5_PORTB (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTB))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC5_PORTB.
+#define BF_SIM_SCGC5_PORTB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_PORTB), uint32_t) & BM_SIM_SCGC5_PORTB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PORTB field to a new value.
+#define BW_SIM_SCGC5_PORTB(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTB) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC5, field PORTC[11] (RW)
+ *
+ * This bit controls the clock gate to the Port C module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC5_PORTC (11U) //!< Bit position for SIM_SCGC5_PORTC.
+#define BM_SIM_SCGC5_PORTC (0x00000800U) //!< Bit mask for SIM_SCGC5_PORTC.
+#define BS_SIM_SCGC5_PORTC (1U) //!< Bit field size in bits for SIM_SCGC5_PORTC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC5_PORTC field.
+#define BR_SIM_SCGC5_PORTC (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTC))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC5_PORTC.
+#define BF_SIM_SCGC5_PORTC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_PORTC), uint32_t) & BM_SIM_SCGC5_PORTC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PORTC field to a new value.
+#define BW_SIM_SCGC5_PORTC(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC5, field PORTD[12] (RW)
+ *
+ * This bit controls the clock gate to the Port D module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC5_PORTD (12U) //!< Bit position for SIM_SCGC5_PORTD.
+#define BM_SIM_SCGC5_PORTD (0x00001000U) //!< Bit mask for SIM_SCGC5_PORTD.
+#define BS_SIM_SCGC5_PORTD (1U) //!< Bit field size in bits for SIM_SCGC5_PORTD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC5_PORTD field.
+#define BR_SIM_SCGC5_PORTD (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTD))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC5_PORTD.
+#define BF_SIM_SCGC5_PORTD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_PORTD), uint32_t) & BM_SIM_SCGC5_PORTD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PORTD field to a new value.
+#define BW_SIM_SCGC5_PORTD(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC5, field PORTE[13] (RW)
+ *
+ * This bit controls the clock gate to the Port E module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC5_PORTE (13U) //!< Bit position for SIM_SCGC5_PORTE.
+#define BM_SIM_SCGC5_PORTE (0x00002000U) //!< Bit mask for SIM_SCGC5_PORTE.
+#define BS_SIM_SCGC5_PORTE (1U) //!< Bit field size in bits for SIM_SCGC5_PORTE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC5_PORTE field.
+#define BR_SIM_SCGC5_PORTE (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTE))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC5_PORTE.
+#define BF_SIM_SCGC5_PORTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_PORTE), uint32_t) & BM_SIM_SCGC5_PORTE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PORTE field to a new value.
+#define BW_SIM_SCGC5_PORTE(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_SCGC6 - System Clock Gating Control Register 6
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_SCGC6 - System Clock Gating Control Register 6 (RW)
+ *
+ * Reset value: 0x40000001U
+ *
+ * DAC0, FTM2, and RNGA can be accessed through both AIPS0 and AIPS1. When
+ * accessing through AIPS1, define the clock gate control bits in the SCGC2 and SCGC3.
+ * When accessing through AIPS0, define the clock gate control bits in SCGC6.
+ */
+typedef union _hw_sim_scgc6
+{
+ uint32_t U;
+ struct _hw_sim_scgc6_bitfields
+ {
+ uint32_t FTF : 1; //!< [0] Flash Memory Clock Gate Control
+ uint32_t DMAMUXb : 1; //!< [1] DMA Mux Clock Gate Control
+ uint32_t RESERVED0 : 2; //!< [3:2]
+ uint32_t FLEXCAN0 : 1; //!< [4] FlexCAN0 Clock Gate Control
+ uint32_t RESERVED1 : 4; //!< [8:5]
+ uint32_t RNGA : 1; //!< [9] RNGA Clock Gate Control
+ uint32_t RESERVED2 : 2; //!< [11:10]
+ uint32_t SPI0b : 1; //!< [12] SPI0 Clock Gate Control
+ uint32_t SPI1b : 1; //!< [13] SPI1 Clock Gate Control
+ uint32_t RESERVED3 : 1; //!< [14]
+ uint32_t I2S : 1; //!< [15] I2S Clock Gate Control
+ uint32_t RESERVED4 : 2; //!< [17:16]
+ uint32_t CRCb : 1; //!< [18] CRC Clock Gate Control
+ uint32_t RESERVED5 : 2; //!< [20:19]
+ uint32_t USBDCDb : 1; //!< [21] USB DCD Clock Gate Control
+ uint32_t PDB : 1; //!< [22] PDB Clock Gate Control
+ uint32_t PITb : 1; //!< [23] PIT Clock Gate Control
+ uint32_t FTM0b : 1; //!< [24] FTM0 Clock Gate Control
+ uint32_t FTM1b : 1; //!< [25] FTM1 Clock Gate Control
+ uint32_t FTM2b : 1; //!< [26] FTM2 Clock Gate Control
+ uint32_t ADC0b : 1; //!< [27] ADC0 Clock Gate Control
+ uint32_t RESERVED6 : 1; //!< [28]
+ uint32_t RTCb : 1; //!< [29] RTC Access Control
+ uint32_t RESERVED7 : 1; //!< [30]
+ uint32_t DAC0b : 1; //!< [31] DAC0 Clock Gate Control
+ } B;
+} hw_sim_scgc6_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_SCGC6 register
+ */
+//@{
+#define HW_SIM_SCGC6_ADDR (REGS_SIM_BASE + 0x103CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_SCGC6 (*(__IO hw_sim_scgc6_t *) HW_SIM_SCGC6_ADDR)
+#define HW_SIM_SCGC6_RD() (HW_SIM_SCGC6.U)
+#define HW_SIM_SCGC6_WR(v) (HW_SIM_SCGC6.U = (v))
+#define HW_SIM_SCGC6_SET(v) (HW_SIM_SCGC6_WR(HW_SIM_SCGC6_RD() | (v)))
+#define HW_SIM_SCGC6_CLR(v) (HW_SIM_SCGC6_WR(HW_SIM_SCGC6_RD() & ~(v)))
+#define HW_SIM_SCGC6_TOG(v) (HW_SIM_SCGC6_WR(HW_SIM_SCGC6_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_SCGC6 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC6, field FTF[0] (RW)
+ *
+ * This bit controls the clock gate to the flash memory. Flash reads are still
+ * supported while the flash memory is clock gated, but entry into low power modes
+ * is blocked.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_FTF (0U) //!< Bit position for SIM_SCGC6_FTF.
+#define BM_SIM_SCGC6_FTF (0x00000001U) //!< Bit mask for SIM_SCGC6_FTF.
+#define BS_SIM_SCGC6_FTF (1U) //!< Bit field size in bits for SIM_SCGC6_FTF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_FTF field.
+#define BR_SIM_SCGC6_FTF (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTF))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_FTF.
+#define BF_SIM_SCGC6_FTF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_FTF), uint32_t) & BM_SIM_SCGC6_FTF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTF field to a new value.
+#define BW_SIM_SCGC6_FTF(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field DMAMUX[1] (RW)
+ *
+ * This bit controls the clock gate to the DMA Mux module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_DMAMUX (1U) //!< Bit position for SIM_SCGC6_DMAMUX.
+#define BM_SIM_SCGC6_DMAMUX (0x00000002U) //!< Bit mask for SIM_SCGC6_DMAMUX.
+#define BS_SIM_SCGC6_DMAMUX (1U) //!< Bit field size in bits for SIM_SCGC6_DMAMUX.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_DMAMUX field.
+#define BR_SIM_SCGC6_DMAMUX (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_DMAMUX))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_DMAMUX.
+#define BF_SIM_SCGC6_DMAMUX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_DMAMUX), uint32_t) & BM_SIM_SCGC6_DMAMUX)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMAMUX field to a new value.
+#define BW_SIM_SCGC6_DMAMUX(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_DMAMUX) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field FLEXCAN0[4] (RW)
+ *
+ * This bit controls the clock gate to the FlexCAN0 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_FLEXCAN0 (4U) //!< Bit position for SIM_SCGC6_FLEXCAN0.
+#define BM_SIM_SCGC6_FLEXCAN0 (0x00000010U) //!< Bit mask for SIM_SCGC6_FLEXCAN0.
+#define BS_SIM_SCGC6_FLEXCAN0 (1U) //!< Bit field size in bits for SIM_SCGC6_FLEXCAN0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_FLEXCAN0 field.
+#define BR_SIM_SCGC6_FLEXCAN0 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FLEXCAN0))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_FLEXCAN0.
+#define BF_SIM_SCGC6_FLEXCAN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_FLEXCAN0), uint32_t) & BM_SIM_SCGC6_FLEXCAN0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FLEXCAN0 field to a new value.
+#define BW_SIM_SCGC6_FLEXCAN0(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FLEXCAN0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field RNGA[9] (RW)
+ *
+ * This bit controls the clock gate to the RNGA module.
+ */
+//@{
+#define BP_SIM_SCGC6_RNGA (9U) //!< Bit position for SIM_SCGC6_RNGA.
+#define BM_SIM_SCGC6_RNGA (0x00000200U) //!< Bit mask for SIM_SCGC6_RNGA.
+#define BS_SIM_SCGC6_RNGA (1U) //!< Bit field size in bits for SIM_SCGC6_RNGA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_RNGA field.
+#define BR_SIM_SCGC6_RNGA (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_RNGA))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_RNGA.
+#define BF_SIM_SCGC6_RNGA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_RNGA), uint32_t) & BM_SIM_SCGC6_RNGA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RNGA field to a new value.
+#define BW_SIM_SCGC6_RNGA(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_RNGA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field SPI0[12] (RW)
+ *
+ * This bit controls the clock gate to the SPI0 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_SPI0 (12U) //!< Bit position for SIM_SCGC6_SPI0.
+#define BM_SIM_SCGC6_SPI0 (0x00001000U) //!< Bit mask for SIM_SCGC6_SPI0.
+#define BS_SIM_SCGC6_SPI0 (1U) //!< Bit field size in bits for SIM_SCGC6_SPI0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_SPI0 field.
+#define BR_SIM_SCGC6_SPI0 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_SPI0))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_SPI0.
+#define BF_SIM_SCGC6_SPI0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_SPI0), uint32_t) & BM_SIM_SCGC6_SPI0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SPI0 field to a new value.
+#define BW_SIM_SCGC6_SPI0(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_SPI0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field SPI1[13] (RW)
+ *
+ * This bit controls the clock gate to the SPI1 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_SPI1 (13U) //!< Bit position for SIM_SCGC6_SPI1.
+#define BM_SIM_SCGC6_SPI1 (0x00002000U) //!< Bit mask for SIM_SCGC6_SPI1.
+#define BS_SIM_SCGC6_SPI1 (1U) //!< Bit field size in bits for SIM_SCGC6_SPI1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_SPI1 field.
+#define BR_SIM_SCGC6_SPI1 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_SPI1))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_SPI1.
+#define BF_SIM_SCGC6_SPI1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_SPI1), uint32_t) & BM_SIM_SCGC6_SPI1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SPI1 field to a new value.
+#define BW_SIM_SCGC6_SPI1(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_SPI1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field I2S[15] (RW)
+ *
+ * This bit controls the clock gate to the I 2 S module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_I2S (15U) //!< Bit position for SIM_SCGC6_I2S.
+#define BM_SIM_SCGC6_I2S (0x00008000U) //!< Bit mask for SIM_SCGC6_I2S.
+#define BS_SIM_SCGC6_I2S (1U) //!< Bit field size in bits for SIM_SCGC6_I2S.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_I2S field.
+#define BR_SIM_SCGC6_I2S (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_I2S))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_I2S.
+#define BF_SIM_SCGC6_I2S(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_I2S), uint32_t) & BM_SIM_SCGC6_I2S)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the I2S field to a new value.
+#define BW_SIM_SCGC6_I2S(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_I2S) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field CRC[18] (RW)
+ *
+ * This bit controls the clock gate to the CRC module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_CRC (18U) //!< Bit position for SIM_SCGC6_CRC.
+#define BM_SIM_SCGC6_CRC (0x00040000U) //!< Bit mask for SIM_SCGC6_CRC.
+#define BS_SIM_SCGC6_CRC (1U) //!< Bit field size in bits for SIM_SCGC6_CRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_CRC field.
+#define BR_SIM_SCGC6_CRC (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_CRC))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_CRC.
+#define BF_SIM_SCGC6_CRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_CRC), uint32_t) & BM_SIM_SCGC6_CRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CRC field to a new value.
+#define BW_SIM_SCGC6_CRC(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_CRC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field USBDCD[21] (RW)
+ *
+ * This bit controls the clock gate to the USB DCD module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_USBDCD (21U) //!< Bit position for SIM_SCGC6_USBDCD.
+#define BM_SIM_SCGC6_USBDCD (0x00200000U) //!< Bit mask for SIM_SCGC6_USBDCD.
+#define BS_SIM_SCGC6_USBDCD (1U) //!< Bit field size in bits for SIM_SCGC6_USBDCD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_USBDCD field.
+#define BR_SIM_SCGC6_USBDCD (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_USBDCD))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_USBDCD.
+#define BF_SIM_SCGC6_USBDCD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_USBDCD), uint32_t) & BM_SIM_SCGC6_USBDCD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the USBDCD field to a new value.
+#define BW_SIM_SCGC6_USBDCD(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_USBDCD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field PDB[22] (RW)
+ *
+ * This bit controls the clock gate to the PDB module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_PDB (22U) //!< Bit position for SIM_SCGC6_PDB.
+#define BM_SIM_SCGC6_PDB (0x00400000U) //!< Bit mask for SIM_SCGC6_PDB.
+#define BS_SIM_SCGC6_PDB (1U) //!< Bit field size in bits for SIM_SCGC6_PDB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_PDB field.
+#define BR_SIM_SCGC6_PDB (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_PDB))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_PDB.
+#define BF_SIM_SCGC6_PDB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_PDB), uint32_t) & BM_SIM_SCGC6_PDB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PDB field to a new value.
+#define BW_SIM_SCGC6_PDB(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_PDB) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field PIT[23] (RW)
+ *
+ * This bit controls the clock gate to the PIT module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_PIT (23U) //!< Bit position for SIM_SCGC6_PIT.
+#define BM_SIM_SCGC6_PIT (0x00800000U) //!< Bit mask for SIM_SCGC6_PIT.
+#define BS_SIM_SCGC6_PIT (1U) //!< Bit field size in bits for SIM_SCGC6_PIT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_PIT field.
+#define BR_SIM_SCGC6_PIT (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_PIT))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_PIT.
+#define BF_SIM_SCGC6_PIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_PIT), uint32_t) & BM_SIM_SCGC6_PIT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PIT field to a new value.
+#define BW_SIM_SCGC6_PIT(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_PIT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field FTM0[24] (RW)
+ *
+ * This bit controls the clock gate to the FTM0 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_FTM0 (24U) //!< Bit position for SIM_SCGC6_FTM0.
+#define BM_SIM_SCGC6_FTM0 (0x01000000U) //!< Bit mask for SIM_SCGC6_FTM0.
+#define BS_SIM_SCGC6_FTM0 (1U) //!< Bit field size in bits for SIM_SCGC6_FTM0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_FTM0 field.
+#define BR_SIM_SCGC6_FTM0 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM0))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_FTM0.
+#define BF_SIM_SCGC6_FTM0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_FTM0), uint32_t) & BM_SIM_SCGC6_FTM0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM0 field to a new value.
+#define BW_SIM_SCGC6_FTM0(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field FTM1[25] (RW)
+ *
+ * This bit controls the clock gate to the FTM1 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_FTM1 (25U) //!< Bit position for SIM_SCGC6_FTM1.
+#define BM_SIM_SCGC6_FTM1 (0x02000000U) //!< Bit mask for SIM_SCGC6_FTM1.
+#define BS_SIM_SCGC6_FTM1 (1U) //!< Bit field size in bits for SIM_SCGC6_FTM1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_FTM1 field.
+#define BR_SIM_SCGC6_FTM1 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM1))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_FTM1.
+#define BF_SIM_SCGC6_FTM1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_FTM1), uint32_t) & BM_SIM_SCGC6_FTM1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM1 field to a new value.
+#define BW_SIM_SCGC6_FTM1(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM1) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field FTM2[26] (RW)
+ *
+ * This bit controls the clock gate to the FTM2 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_FTM2 (26U) //!< Bit position for SIM_SCGC6_FTM2.
+#define BM_SIM_SCGC6_FTM2 (0x04000000U) //!< Bit mask for SIM_SCGC6_FTM2.
+#define BS_SIM_SCGC6_FTM2 (1U) //!< Bit field size in bits for SIM_SCGC6_FTM2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_FTM2 field.
+#define BR_SIM_SCGC6_FTM2 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM2))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_FTM2.
+#define BF_SIM_SCGC6_FTM2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_FTM2), uint32_t) & BM_SIM_SCGC6_FTM2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FTM2 field to a new value.
+#define BW_SIM_SCGC6_FTM2(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field ADC0[27] (RW)
+ *
+ * This bit controls the clock gate to the ADC0 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_ADC0 (27U) //!< Bit position for SIM_SCGC6_ADC0.
+#define BM_SIM_SCGC6_ADC0 (0x08000000U) //!< Bit mask for SIM_SCGC6_ADC0.
+#define BS_SIM_SCGC6_ADC0 (1U) //!< Bit field size in bits for SIM_SCGC6_ADC0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_ADC0 field.
+#define BR_SIM_SCGC6_ADC0 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_ADC0))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_ADC0.
+#define BF_SIM_SCGC6_ADC0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_ADC0), uint32_t) & BM_SIM_SCGC6_ADC0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADC0 field to a new value.
+#define BW_SIM_SCGC6_ADC0(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_ADC0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field RTC[29] (RW)
+ *
+ * This bit controls software access and interrupts to the RTC module.
+ *
+ * Values:
+ * - 0 - Access and interrupts disabled
+ * - 1 - Access and interrupts enabled
+ */
+//@{
+#define BP_SIM_SCGC6_RTC (29U) //!< Bit position for SIM_SCGC6_RTC.
+#define BM_SIM_SCGC6_RTC (0x20000000U) //!< Bit mask for SIM_SCGC6_RTC.
+#define BS_SIM_SCGC6_RTC (1U) //!< Bit field size in bits for SIM_SCGC6_RTC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_RTC field.
+#define BR_SIM_SCGC6_RTC (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_RTC))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_RTC.
+#define BF_SIM_SCGC6_RTC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_RTC), uint32_t) & BM_SIM_SCGC6_RTC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RTC field to a new value.
+#define BW_SIM_SCGC6_RTC(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_RTC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC6, field DAC0[31] (RW)
+ *
+ * This bit controls the clock gate to the DAC0 module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC6_DAC0 (31U) //!< Bit position for SIM_SCGC6_DAC0.
+#define BM_SIM_SCGC6_DAC0 (0x80000000U) //!< Bit mask for SIM_SCGC6_DAC0.
+#define BS_SIM_SCGC6_DAC0 (1U) //!< Bit field size in bits for SIM_SCGC6_DAC0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC6_DAC0 field.
+#define BR_SIM_SCGC6_DAC0 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_DAC0))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC6_DAC0.
+#define BF_SIM_SCGC6_DAC0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_DAC0), uint32_t) & BM_SIM_SCGC6_DAC0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DAC0 field to a new value.
+#define BW_SIM_SCGC6_DAC0(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_DAC0) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_SCGC7 - System Clock Gating Control Register 7
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_SCGC7 - System Clock Gating Control Register 7 (RW)
+ *
+ * Reset value: 0x00000006U
+ */
+typedef union _hw_sim_scgc7
+{
+ uint32_t U;
+ struct _hw_sim_scgc7_bitfields
+ {
+ uint32_t FLEXBUS : 1; //!< [0] FlexBus Clock Gate Control
+ uint32_t DMAb : 1; //!< [1] DMA Clock Gate Control
+ uint32_t MPUb : 1; //!< [2] MPU Clock Gate Control
+ uint32_t RESERVED0 : 29; //!< [31:3]
+ } B;
+} hw_sim_scgc7_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_SCGC7 register
+ */
+//@{
+#define HW_SIM_SCGC7_ADDR (REGS_SIM_BASE + 0x1040U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_SCGC7 (*(__IO hw_sim_scgc7_t *) HW_SIM_SCGC7_ADDR)
+#define HW_SIM_SCGC7_RD() (HW_SIM_SCGC7.U)
+#define HW_SIM_SCGC7_WR(v) (HW_SIM_SCGC7.U = (v))
+#define HW_SIM_SCGC7_SET(v) (HW_SIM_SCGC7_WR(HW_SIM_SCGC7_RD() | (v)))
+#define HW_SIM_SCGC7_CLR(v) (HW_SIM_SCGC7_WR(HW_SIM_SCGC7_RD() & ~(v)))
+#define HW_SIM_SCGC7_TOG(v) (HW_SIM_SCGC7_WR(HW_SIM_SCGC7_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_SCGC7 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC7, field FLEXBUS[0] (RW)
+ *
+ * This bit controls the clock gate to the FlexBus module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC7_FLEXBUS (0U) //!< Bit position for SIM_SCGC7_FLEXBUS.
+#define BM_SIM_SCGC7_FLEXBUS (0x00000001U) //!< Bit mask for SIM_SCGC7_FLEXBUS.
+#define BS_SIM_SCGC7_FLEXBUS (1U) //!< Bit field size in bits for SIM_SCGC7_FLEXBUS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC7_FLEXBUS field.
+#define BR_SIM_SCGC7_FLEXBUS (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_FLEXBUS))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC7_FLEXBUS.
+#define BF_SIM_SCGC7_FLEXBUS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC7_FLEXBUS), uint32_t) & BM_SIM_SCGC7_FLEXBUS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FLEXBUS field to a new value.
+#define BW_SIM_SCGC7_FLEXBUS(v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_FLEXBUS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC7, field DMA[1] (RW)
+ *
+ * This bit controls the clock gate to the DMA module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC7_DMA (1U) //!< Bit position for SIM_SCGC7_DMA.
+#define BM_SIM_SCGC7_DMA (0x00000002U) //!< Bit mask for SIM_SCGC7_DMA.
+#define BS_SIM_SCGC7_DMA (1U) //!< Bit field size in bits for SIM_SCGC7_DMA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC7_DMA field.
+#define BR_SIM_SCGC7_DMA (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_DMA))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC7_DMA.
+#define BF_SIM_SCGC7_DMA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC7_DMA), uint32_t) & BM_SIM_SCGC7_DMA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMA field to a new value.
+#define BW_SIM_SCGC7_DMA(v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_DMA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_SCGC7, field MPU[2] (RW)
+ *
+ * This bit controls the clock gate to the MPU module.
+ *
+ * Values:
+ * - 0 - Clock disabled
+ * - 1 - Clock enabled
+ */
+//@{
+#define BP_SIM_SCGC7_MPU (2U) //!< Bit position for SIM_SCGC7_MPU.
+#define BM_SIM_SCGC7_MPU (0x00000004U) //!< Bit mask for SIM_SCGC7_MPU.
+#define BS_SIM_SCGC7_MPU (1U) //!< Bit field size in bits for SIM_SCGC7_MPU.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_SCGC7_MPU field.
+#define BR_SIM_SCGC7_MPU (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_MPU))
+#endif
+
+//! @brief Format value for bitfield SIM_SCGC7_MPU.
+#define BF_SIM_SCGC7_MPU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC7_MPU), uint32_t) & BM_SIM_SCGC7_MPU)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MPU field to a new value.
+#define BW_SIM_SCGC7_MPU(v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_MPU) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_CLKDIV1 - System Clock Divider Register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_CLKDIV1 - System Clock Divider Register 1 (RW)
+ *
+ * Reset value: 0x00010000U
+ *
+ * When updating CLKDIV1, update all fields using the one write command.
+ * Attempting to write an invalid clock ratio to the CLKDIV1 register will cause the
+ * write to be ignored. The maximum divide ratio that can be programmed between
+ * core/system clock and the other divided clocks is divide by 8. When OUTDIV1 equals
+ * 0000 (divide by 1), the other dividers cannot be set higher than 0111 (divide
+ * by 8). The CLKDIV1 register cannot be written to when the device is in VLPR
+ * mode.
+ */
+typedef union _hw_sim_clkdiv1
+{
+ uint32_t U;
+ struct _hw_sim_clkdiv1_bitfields
+ {
+ uint32_t RESERVED0 : 16; //!< [15:0]
+ uint32_t OUTDIV4 : 4; //!< [19:16] Clock 4 output divider value
+ uint32_t OUTDIV3 : 4; //!< [23:20] Clock 3 output divider value
+ uint32_t OUTDIV2 : 4; //!< [27:24] Clock 2 output divider value
+ uint32_t OUTDIV1 : 4; //!< [31:28] Clock 1 output divider value
+ } B;
+} hw_sim_clkdiv1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_CLKDIV1 register
+ */
+//@{
+#define HW_SIM_CLKDIV1_ADDR (REGS_SIM_BASE + 0x1044U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_CLKDIV1 (*(__IO hw_sim_clkdiv1_t *) HW_SIM_CLKDIV1_ADDR)
+#define HW_SIM_CLKDIV1_RD() (HW_SIM_CLKDIV1.U)
+#define HW_SIM_CLKDIV1_WR(v) (HW_SIM_CLKDIV1.U = (v))
+#define HW_SIM_CLKDIV1_SET(v) (HW_SIM_CLKDIV1_WR(HW_SIM_CLKDIV1_RD() | (v)))
+#define HW_SIM_CLKDIV1_CLR(v) (HW_SIM_CLKDIV1_WR(HW_SIM_CLKDIV1_RD() & ~(v)))
+#define HW_SIM_CLKDIV1_TOG(v) (HW_SIM_CLKDIV1_WR(HW_SIM_CLKDIV1_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_CLKDIV1 bitfields
+ */
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV4[19:16] (RW)
+ *
+ * This field sets the divide value for the flash clock from MCGOUTCLK. At the
+ * end of reset, it is loaded with either 0001 or 1111 depending on
+ * FTF_FOPT[LPBOOT]. The flash clock frequency must be an integer divide of the system clock
+ * frequency.
+ *
+ * Values:
+ * - 0000 - Divide-by-1.
+ * - 0001 - Divide-by-2.
+ * - 0010 - Divide-by-3.
+ * - 0011 - Divide-by-4.
+ * - 0100 - Divide-by-5.
+ * - 0101 - Divide-by-6.
+ * - 0110 - Divide-by-7.
+ * - 0111 - Divide-by-8.
+ * - 1000 - Divide-by-9.
+ * - 1001 - Divide-by-10.
+ * - 1010 - Divide-by-11.
+ * - 1011 - Divide-by-12.
+ * - 1100 - Divide-by-13.
+ * - 1101 - Divide-by-14.
+ * - 1110 - Divide-by-15.
+ * - 1111 - Divide-by-16.
+ */
+//@{
+#define BP_SIM_CLKDIV1_OUTDIV4 (16U) //!< Bit position for SIM_CLKDIV1_OUTDIV4.
+#define BM_SIM_CLKDIV1_OUTDIV4 (0x000F0000U) //!< Bit mask for SIM_CLKDIV1_OUTDIV4.
+#define BS_SIM_CLKDIV1_OUTDIV4 (4U) //!< Bit field size in bits for SIM_CLKDIV1_OUTDIV4.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_CLKDIV1_OUTDIV4 field.
+#define BR_SIM_CLKDIV1_OUTDIV4 (HW_SIM_CLKDIV1.B.OUTDIV4)
+#endif
+
+//! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV4.
+#define BF_SIM_CLKDIV1_OUTDIV4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV1_OUTDIV4), uint32_t) & BM_SIM_CLKDIV1_OUTDIV4)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OUTDIV4 field to a new value.
+#define BW_SIM_CLKDIV1_OUTDIV4(v) (HW_SIM_CLKDIV1_WR((HW_SIM_CLKDIV1_RD() & ~BM_SIM_CLKDIV1_OUTDIV4) | BF_SIM_CLKDIV1_OUTDIV4(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV3[23:20] (RW)
+ *
+ * This field sets the divide value for the FlexBus clock (external pin FB_CLK)
+ * from MCGOUTCLK. At the end of reset, it is loaded with either 0001 or 1111
+ * depending on FTF_FOPT[LPBOOT]. The FlexBus clock frequency must be an integer
+ * divide of the system clock frequency.
+ *
+ * Values:
+ * - 0000 - Divide-by-1.
+ * - 0001 - Divide-by-2.
+ * - 0010 - Divide-by-3.
+ * - 0011 - Divide-by-4.
+ * - 0100 - Divide-by-5.
+ * - 0101 - Divide-by-6.
+ * - 0110 - Divide-by-7.
+ * - 0111 - Divide-by-8.
+ * - 1000 - Divide-by-9.
+ * - 1001 - Divide-by-10.
+ * - 1010 - Divide-by-11.
+ * - 1011 - Divide-by-12.
+ * - 1100 - Divide-by-13.
+ * - 1101 - Divide-by-14.
+ * - 1110 - Divide-by-15.
+ * - 1111 - Divide-by-16.
+ */
+//@{
+#define BP_SIM_CLKDIV1_OUTDIV3 (20U) //!< Bit position for SIM_CLKDIV1_OUTDIV3.
+#define BM_SIM_CLKDIV1_OUTDIV3 (0x00F00000U) //!< Bit mask for SIM_CLKDIV1_OUTDIV3.
+#define BS_SIM_CLKDIV1_OUTDIV3 (4U) //!< Bit field size in bits for SIM_CLKDIV1_OUTDIV3.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_CLKDIV1_OUTDIV3 field.
+#define BR_SIM_CLKDIV1_OUTDIV3 (HW_SIM_CLKDIV1.B.OUTDIV3)
+#endif
+
+//! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV3.
+#define BF_SIM_CLKDIV1_OUTDIV3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV1_OUTDIV3), uint32_t) & BM_SIM_CLKDIV1_OUTDIV3)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OUTDIV3 field to a new value.
+#define BW_SIM_CLKDIV1_OUTDIV3(v) (HW_SIM_CLKDIV1_WR((HW_SIM_CLKDIV1_RD() & ~BM_SIM_CLKDIV1_OUTDIV3) | BF_SIM_CLKDIV1_OUTDIV3(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV2[27:24] (RW)
+ *
+ * This field sets the divide value for the bus clock from MCGOUTCLK. At the end
+ * of reset, it is loaded with either 0000 or 0111 depending on
+ * FTF_FOPT[LPBOOT]. The bus clock frequency must be an integer divide of the core/system clock
+ * frequency.
+ *
+ * Values:
+ * - 0000 - Divide-by-1.
+ * - 0001 - Divide-by-2.
+ * - 0010 - Divide-by-3.
+ * - 0011 - Divide-by-4.
+ * - 0100 - Divide-by-5.
+ * - 0101 - Divide-by-6.
+ * - 0110 - Divide-by-7.
+ * - 0111 - Divide-by-8.
+ * - 1000 - Divide-by-9.
+ * - 1001 - Divide-by-10.
+ * - 1010 - Divide-by-11.
+ * - 1011 - Divide-by-12.
+ * - 1100 - Divide-by-13.
+ * - 1101 - Divide-by-14.
+ * - 1110 - Divide-by-15.
+ * - 1111 - Divide-by-16.
+ */
+//@{
+#define BP_SIM_CLKDIV1_OUTDIV2 (24U) //!< Bit position for SIM_CLKDIV1_OUTDIV2.
+#define BM_SIM_CLKDIV1_OUTDIV2 (0x0F000000U) //!< Bit mask for SIM_CLKDIV1_OUTDIV2.
+#define BS_SIM_CLKDIV1_OUTDIV2 (4U) //!< Bit field size in bits for SIM_CLKDIV1_OUTDIV2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_CLKDIV1_OUTDIV2 field.
+#define BR_SIM_CLKDIV1_OUTDIV2 (HW_SIM_CLKDIV1.B.OUTDIV2)
+#endif
+
+//! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV2.
+#define BF_SIM_CLKDIV1_OUTDIV2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV1_OUTDIV2), uint32_t) & BM_SIM_CLKDIV1_OUTDIV2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OUTDIV2 field to a new value.
+#define BW_SIM_CLKDIV1_OUTDIV2(v) (HW_SIM_CLKDIV1_WR((HW_SIM_CLKDIV1_RD() & ~BM_SIM_CLKDIV1_OUTDIV2) | BF_SIM_CLKDIV1_OUTDIV2(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV1[31:28] (RW)
+ *
+ * This field sets the divide value for the core/system clock from MCGOUTCLK. At
+ * the end of reset, it is loaded with either 0000 or 0111 depending on
+ * FTF_FOPT[LPBOOT].
+ *
+ * Values:
+ * - 0000 - Divide-by-1.
+ * - 0001 - Divide-by-2.
+ * - 0010 - Divide-by-3.
+ * - 0011 - Divide-by-4.
+ * - 0100 - Divide-by-5.
+ * - 0101 - Divide-by-6.
+ * - 0110 - Divide-by-7.
+ * - 0111 - Divide-by-8.
+ * - 1000 - Divide-by-9.
+ * - 1001 - Divide-by-10.
+ * - 1010 - Divide-by-11.
+ * - 1011 - Divide-by-12.
+ * - 1100 - Divide-by-13.
+ * - 1101 - Divide-by-14.
+ * - 1110 - Divide-by-15.
+ * - 1111 - Divide-by-16.
+ */
+//@{
+#define BP_SIM_CLKDIV1_OUTDIV1 (28U) //!< Bit position for SIM_CLKDIV1_OUTDIV1.
+#define BM_SIM_CLKDIV1_OUTDIV1 (0xF0000000U) //!< Bit mask for SIM_CLKDIV1_OUTDIV1.
+#define BS_SIM_CLKDIV1_OUTDIV1 (4U) //!< Bit field size in bits for SIM_CLKDIV1_OUTDIV1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_CLKDIV1_OUTDIV1 field.
+#define BR_SIM_CLKDIV1_OUTDIV1 (HW_SIM_CLKDIV1.B.OUTDIV1)
+#endif
+
+//! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV1.
+#define BF_SIM_CLKDIV1_OUTDIV1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV1_OUTDIV1), uint32_t) & BM_SIM_CLKDIV1_OUTDIV1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OUTDIV1 field to a new value.
+#define BW_SIM_CLKDIV1_OUTDIV1(v) (HW_SIM_CLKDIV1_WR((HW_SIM_CLKDIV1_RD() & ~BM_SIM_CLKDIV1_OUTDIV1) | BF_SIM_CLKDIV1_OUTDIV1(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_CLKDIV2 - System Clock Divider Register 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_CLKDIV2 - System Clock Divider Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_sim_clkdiv2
+{
+ uint32_t U;
+ struct _hw_sim_clkdiv2_bitfields
+ {
+ uint32_t USBFRAC : 1; //!< [0] USB clock divider fraction
+ uint32_t USBDIV : 3; //!< [3:1] USB clock divider divisor
+ uint32_t RESERVED0 : 28; //!< [31:4]
+ } B;
+} hw_sim_clkdiv2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_CLKDIV2 register
+ */
+//@{
+#define HW_SIM_CLKDIV2_ADDR (REGS_SIM_BASE + 0x1048U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_CLKDIV2 (*(__IO hw_sim_clkdiv2_t *) HW_SIM_CLKDIV2_ADDR)
+#define HW_SIM_CLKDIV2_RD() (HW_SIM_CLKDIV2.U)
+#define HW_SIM_CLKDIV2_WR(v) (HW_SIM_CLKDIV2.U = (v))
+#define HW_SIM_CLKDIV2_SET(v) (HW_SIM_CLKDIV2_WR(HW_SIM_CLKDIV2_RD() | (v)))
+#define HW_SIM_CLKDIV2_CLR(v) (HW_SIM_CLKDIV2_WR(HW_SIM_CLKDIV2_RD() & ~(v)))
+#define HW_SIM_CLKDIV2_TOG(v) (HW_SIM_CLKDIV2_WR(HW_SIM_CLKDIV2_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_CLKDIV2 bitfields
+ */
+
+/*!
+ * @name Register SIM_CLKDIV2, field USBFRAC[0] (RW)
+ *
+ * This field sets the fraction multiply value for the fractional clock divider
+ * when the MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] =
+ * 1). Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ */
+//@{
+#define BP_SIM_CLKDIV2_USBFRAC (0U) //!< Bit position for SIM_CLKDIV2_USBFRAC.
+#define BM_SIM_CLKDIV2_USBFRAC (0x00000001U) //!< Bit mask for SIM_CLKDIV2_USBFRAC.
+#define BS_SIM_CLKDIV2_USBFRAC (1U) //!< Bit field size in bits for SIM_CLKDIV2_USBFRAC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_CLKDIV2_USBFRAC field.
+#define BR_SIM_CLKDIV2_USBFRAC (BITBAND_ACCESS32(HW_SIM_CLKDIV2_ADDR, BP_SIM_CLKDIV2_USBFRAC))
+#endif
+
+//! @brief Format value for bitfield SIM_CLKDIV2_USBFRAC.
+#define BF_SIM_CLKDIV2_USBFRAC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV2_USBFRAC), uint32_t) & BM_SIM_CLKDIV2_USBFRAC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the USBFRAC field to a new value.
+#define BW_SIM_CLKDIV2_USBFRAC(v) (BITBAND_ACCESS32(HW_SIM_CLKDIV2_ADDR, BP_SIM_CLKDIV2_USBFRAC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_CLKDIV2, field USBDIV[3:1] (RW)
+ *
+ * This field sets the divide value for the fractional clock divider when the
+ * MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = 1). Divider
+ * output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ */
+//@{
+#define BP_SIM_CLKDIV2_USBDIV (1U) //!< Bit position for SIM_CLKDIV2_USBDIV.
+#define BM_SIM_CLKDIV2_USBDIV (0x0000000EU) //!< Bit mask for SIM_CLKDIV2_USBDIV.
+#define BS_SIM_CLKDIV2_USBDIV (3U) //!< Bit field size in bits for SIM_CLKDIV2_USBDIV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_CLKDIV2_USBDIV field.
+#define BR_SIM_CLKDIV2_USBDIV (HW_SIM_CLKDIV2.B.USBDIV)
+#endif
+
+//! @brief Format value for bitfield SIM_CLKDIV2_USBDIV.
+#define BF_SIM_CLKDIV2_USBDIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV2_USBDIV), uint32_t) & BM_SIM_CLKDIV2_USBDIV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the USBDIV field to a new value.
+#define BW_SIM_CLKDIV2_USBDIV(v) (HW_SIM_CLKDIV2_WR((HW_SIM_CLKDIV2_RD() & ~BM_SIM_CLKDIV2_USBDIV) | BF_SIM_CLKDIV2_USBDIV(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_FCFG1 - Flash Configuration Register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_FCFG1 - Flash Configuration Register 1 (RW)
+ *
+ * Reset value: 0xFF0F0F00U
+ *
+ * For devices with FlexNVM: The reset value of EESIZE and DEPART are based on
+ * user programming in user IFR via the PGMPART flash command. For devices with
+ * program flash only:
+ */
+typedef union _hw_sim_fcfg1
+{
+ uint32_t U;
+ struct _hw_sim_fcfg1_bitfields
+ {
+ uint32_t FLASHDIS : 1; //!< [0] Flash Disable
+ uint32_t FLASHDOZE : 1; //!< [1] Flash Doze
+ uint32_t RESERVED0 : 6; //!< [7:2]
+ uint32_t DEPART : 4; //!< [11:8] FlexNVM partition
+ uint32_t RESERVED1 : 4; //!< [15:12]
+ uint32_t EESIZE : 4; //!< [19:16] EEPROM size
+ uint32_t RESERVED2 : 4; //!< [23:20]
+ uint32_t PFSIZE : 4; //!< [27:24] Program flash size
+ uint32_t NVMSIZE : 4; //!< [31:28] FlexNVM size
+ } B;
+} hw_sim_fcfg1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_FCFG1 register
+ */
+//@{
+#define HW_SIM_FCFG1_ADDR (REGS_SIM_BASE + 0x104CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_FCFG1 (*(__IO hw_sim_fcfg1_t *) HW_SIM_FCFG1_ADDR)
+#define HW_SIM_FCFG1_RD() (HW_SIM_FCFG1.U)
+#define HW_SIM_FCFG1_WR(v) (HW_SIM_FCFG1.U = (v))
+#define HW_SIM_FCFG1_SET(v) (HW_SIM_FCFG1_WR(HW_SIM_FCFG1_RD() | (v)))
+#define HW_SIM_FCFG1_CLR(v) (HW_SIM_FCFG1_WR(HW_SIM_FCFG1_RD() & ~(v)))
+#define HW_SIM_FCFG1_TOG(v) (HW_SIM_FCFG1_WR(HW_SIM_FCFG1_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_FCFG1 bitfields
+ */
+
+/*!
+ * @name Register SIM_FCFG1, field FLASHDIS[0] (RW)
+ *
+ * Flash accesses are disabled (and generate a bus error) and the Flash memory
+ * is placed in a low power state. This bit should not be changed during VLP
+ * modes. Relocate the interrupt vectors out of Flash memory before disabling the
+ * Flash.
+ *
+ * Values:
+ * - 0 - Flash is enabled
+ * - 1 - Flash is disabled
+ */
+//@{
+#define BP_SIM_FCFG1_FLASHDIS (0U) //!< Bit position for SIM_FCFG1_FLASHDIS.
+#define BM_SIM_FCFG1_FLASHDIS (0x00000001U) //!< Bit mask for SIM_FCFG1_FLASHDIS.
+#define BS_SIM_FCFG1_FLASHDIS (1U) //!< Bit field size in bits for SIM_FCFG1_FLASHDIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_FCFG1_FLASHDIS field.
+#define BR_SIM_FCFG1_FLASHDIS (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR, BP_SIM_FCFG1_FLASHDIS))
+#endif
+
+//! @brief Format value for bitfield SIM_FCFG1_FLASHDIS.
+#define BF_SIM_FCFG1_FLASHDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_FCFG1_FLASHDIS), uint32_t) & BM_SIM_FCFG1_FLASHDIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FLASHDIS field to a new value.
+#define BW_SIM_FCFG1_FLASHDIS(v) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR, BP_SIM_FCFG1_FLASHDIS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_FCFG1, field FLASHDOZE[1] (RW)
+ *
+ * When set, Flash memory is disabled for the duration of Wait mode. An attempt
+ * by the DMA or other bus master to access the Flash when the Flash is disabled
+ * will result in a bus error. This bit should be clear during VLP modes. The
+ * Flash will be automatically enabled again at the end of Wait mode so interrupt
+ * vectors do not need to be relocated out of Flash memory. The wakeup time from
+ * Wait mode is extended when this bit is set.
+ *
+ * Values:
+ * - 0 - Flash remains enabled during Wait mode
+ * - 1 - Flash is disabled for the duration of Wait mode
+ */
+//@{
+#define BP_SIM_FCFG1_FLASHDOZE (1U) //!< Bit position for SIM_FCFG1_FLASHDOZE.
+#define BM_SIM_FCFG1_FLASHDOZE (0x00000002U) //!< Bit mask for SIM_FCFG1_FLASHDOZE.
+#define BS_SIM_FCFG1_FLASHDOZE (1U) //!< Bit field size in bits for SIM_FCFG1_FLASHDOZE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_FCFG1_FLASHDOZE field.
+#define BR_SIM_FCFG1_FLASHDOZE (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR, BP_SIM_FCFG1_FLASHDOZE))
+#endif
+
+//! @brief Format value for bitfield SIM_FCFG1_FLASHDOZE.
+#define BF_SIM_FCFG1_FLASHDOZE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_FCFG1_FLASHDOZE), uint32_t) & BM_SIM_FCFG1_FLASHDOZE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FLASHDOZE field to a new value.
+#define BW_SIM_FCFG1_FLASHDOZE(v) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR, BP_SIM_FCFG1_FLASHDOZE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_FCFG1, field DEPART[11:8] (RO)
+ *
+ * For devices with FlexNVM: Data flash / EEPROM backup split . See DEPART bit
+ * description in FTFE chapter. For devices without FlexNVM: Reserved
+ */
+//@{
+#define BP_SIM_FCFG1_DEPART (8U) //!< Bit position for SIM_FCFG1_DEPART.
+#define BM_SIM_FCFG1_DEPART (0x00000F00U) //!< Bit mask for SIM_FCFG1_DEPART.
+#define BS_SIM_FCFG1_DEPART (4U) //!< Bit field size in bits for SIM_FCFG1_DEPART.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_FCFG1_DEPART field.
+#define BR_SIM_FCFG1_DEPART (HW_SIM_FCFG1.B.DEPART)
+#endif
+//@}
+
+/*!
+ * @name Register SIM_FCFG1, field EESIZE[19:16] (RO)
+ *
+ * EEPROM data size .
+ *
+ * Values:
+ * - 0000 - 16 KB
+ * - 0001 - 8 KB
+ * - 0010 - 4 KB
+ * - 0011 - 2 KB
+ * - 0100 - 1 KB
+ * - 0101 - 512 Bytes
+ * - 0110 - 256 Bytes
+ * - 0111 - 128 Bytes
+ * - 1000 - 64 Bytes
+ * - 1001 - 32 Bytes
+ * - 1111 - 0 Bytes
+ */
+//@{
+#define BP_SIM_FCFG1_EESIZE (16U) //!< Bit position for SIM_FCFG1_EESIZE.
+#define BM_SIM_FCFG1_EESIZE (0x000F0000U) //!< Bit mask for SIM_FCFG1_EESIZE.
+#define BS_SIM_FCFG1_EESIZE (4U) //!< Bit field size in bits for SIM_FCFG1_EESIZE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_FCFG1_EESIZE field.
+#define BR_SIM_FCFG1_EESIZE (HW_SIM_FCFG1.B.EESIZE)
+#endif
+//@}
+
+/*!
+ * @name Register SIM_FCFG1, field PFSIZE[27:24] (RO)
+ *
+ * This field specifies the amount of program flash memory available on the
+ * device . Undefined values are reserved.
+ *
+ * Values:
+ * - 0011 - 32 KB of program flash memory
+ * - 0101 - 64 KB of program flash memory
+ * - 0111 - 128 KB of program flash memory
+ * - 1001 - 256 KB of program flash memory
+ * - 1011 - 512 KB of program flash memory
+ * - 1101 - 1024 KB of program flash memory
+ * - 1111 - 1024 KB of program flash memory
+ */
+//@{
+#define BP_SIM_FCFG1_PFSIZE (24U) //!< Bit position for SIM_FCFG1_PFSIZE.
+#define BM_SIM_FCFG1_PFSIZE (0x0F000000U) //!< Bit mask for SIM_FCFG1_PFSIZE.
+#define BS_SIM_FCFG1_PFSIZE (4U) //!< Bit field size in bits for SIM_FCFG1_PFSIZE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_FCFG1_PFSIZE field.
+#define BR_SIM_FCFG1_PFSIZE (HW_SIM_FCFG1.B.PFSIZE)
+#endif
+//@}
+
+/*!
+ * @name Register SIM_FCFG1, field NVMSIZE[31:28] (RO)
+ *
+ * This field specifies the amount of FlexNVM memory available on the device .
+ * Undefined values are reserved.
+ *
+ * Values:
+ * - 0000 - 0 KB of FlexNVM
+ * - 0011 - 32 KB of FlexNVM
+ * - 0101 - 64 KB of FlexNVM
+ * - 0111 - 128 KB of FlexNVM
+ * - 1001 - 256 KB of FlexNVM
+ * - 1011 - 512 KB of FlexNVM
+ * - 1111 - 512 KB of FlexNVM
+ */
+//@{
+#define BP_SIM_FCFG1_NVMSIZE (28U) //!< Bit position for SIM_FCFG1_NVMSIZE.
+#define BM_SIM_FCFG1_NVMSIZE (0xF0000000U) //!< Bit mask for SIM_FCFG1_NVMSIZE.
+#define BS_SIM_FCFG1_NVMSIZE (4U) //!< Bit field size in bits for SIM_FCFG1_NVMSIZE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_FCFG1_NVMSIZE field.
+#define BR_SIM_FCFG1_NVMSIZE (HW_SIM_FCFG1.B.NVMSIZE)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_FCFG2 - Flash Configuration Register 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_FCFG2 - Flash Configuration Register 2 (RO)
+ *
+ * Reset value: 0x7F7F0000U
+ */
+typedef union _hw_sim_fcfg2
+{
+ uint32_t U;
+ struct _hw_sim_fcfg2_bitfields
+ {
+ uint32_t RESERVED0 : 16; //!< [15:0]
+ uint32_t MAXADDR1 : 7; //!< [22:16] Max address block 1
+ uint32_t PFLSH : 1; //!< [23] Program flash only
+ uint32_t MAXADDR0 : 7; //!< [30:24] Max address block 0
+ uint32_t RESERVED1 : 1; //!< [31]
+ } B;
+} hw_sim_fcfg2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_FCFG2 register
+ */
+//@{
+#define HW_SIM_FCFG2_ADDR (REGS_SIM_BASE + 0x1050U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_FCFG2 (*(__I hw_sim_fcfg2_t *) HW_SIM_FCFG2_ADDR)
+#define HW_SIM_FCFG2_RD() (HW_SIM_FCFG2.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_FCFG2 bitfields
+ */
+
+/*!
+ * @name Register SIM_FCFG2, field MAXADDR1[22:16] (RO)
+ *
+ * For devices with FlexNVM: This field concatenated with 13 trailing zeros plus
+ * the FlexNVM base address indicates the first invalid address of the FlexNVM
+ * flash block. For example, if MAXADDR1 = 0x20 the first invalid address of
+ * FlexNVM flash block is 0x4_0000 + 0x1000_0000 . This would be the MAXADDR1 value
+ * for a device with 256 KB FlexNVM. For devices with program flash only: This
+ * field equals zero if there is only one program flash block, otherwise it equals
+ * the value of the MAXADDR0 field. For example, with MAXADDR0 = MAXADDR1 = 0x20
+ * the first invalid address of flash block 1 is 0x4_0000 + 0x4_0000. This would be
+ * the MAXADDR1 value for a device with 512 KB program flash memory across two
+ * flash blocks and no FlexNVM.
+ */
+//@{
+#define BP_SIM_FCFG2_MAXADDR1 (16U) //!< Bit position for SIM_FCFG2_MAXADDR1.
+#define BM_SIM_FCFG2_MAXADDR1 (0x007F0000U) //!< Bit mask for SIM_FCFG2_MAXADDR1.
+#define BS_SIM_FCFG2_MAXADDR1 (7U) //!< Bit field size in bits for SIM_FCFG2_MAXADDR1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_FCFG2_MAXADDR1 field.
+#define BR_SIM_FCFG2_MAXADDR1 (HW_SIM_FCFG2.B.MAXADDR1)
+#endif
+//@}
+
+/*!
+ * @name Register SIM_FCFG2, field PFLSH[23] (RO)
+ *
+ * For devices with FlexNVM, this bit is always clear. For devices without
+ * FlexNVM, this bit is always set.
+ *
+ * Values:
+ * - 0 - Device supports FlexNVM
+ * - 1 - Program Flash only, device does not support FlexNVM
+ */
+//@{
+#define BP_SIM_FCFG2_PFLSH (23U) //!< Bit position for SIM_FCFG2_PFLSH.
+#define BM_SIM_FCFG2_PFLSH (0x00800000U) //!< Bit mask for SIM_FCFG2_PFLSH.
+#define BS_SIM_FCFG2_PFLSH (1U) //!< Bit field size in bits for SIM_FCFG2_PFLSH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_FCFG2_PFLSH field.
+#define BR_SIM_FCFG2_PFLSH (BITBAND_ACCESS32(HW_SIM_FCFG2_ADDR, BP_SIM_FCFG2_PFLSH))
+#endif
+//@}
+
+/*!
+ * @name Register SIM_FCFG2, field MAXADDR0[30:24] (RO)
+ *
+ * This field concatenated with 13 trailing zeros indicates the first invalid
+ * address of each program flash block. For example, if MAXADDR0 = 0x20 the first
+ * invalid address of flash block 0 is 0x0004_0000. This would be the MAXADDR0
+ * value for a device with 256 KB program flash in flash block 0.
+ */
+//@{
+#define BP_SIM_FCFG2_MAXADDR0 (24U) //!< Bit position for SIM_FCFG2_MAXADDR0.
+#define BM_SIM_FCFG2_MAXADDR0 (0x7F000000U) //!< Bit mask for SIM_FCFG2_MAXADDR0.
+#define BS_SIM_FCFG2_MAXADDR0 (7U) //!< Bit field size in bits for SIM_FCFG2_MAXADDR0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_FCFG2_MAXADDR0 field.
+#define BR_SIM_FCFG2_MAXADDR0 (HW_SIM_FCFG2.B.MAXADDR0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_UIDH - Unique Identification Register High
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_UIDH - Unique Identification Register High (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_sim_uidh
+{
+ uint32_t U;
+ struct _hw_sim_uidh_bitfields
+ {
+ uint32_t UID : 32; //!< [31:0] Unique Identification
+ } B;
+} hw_sim_uidh_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_UIDH register
+ */
+//@{
+#define HW_SIM_UIDH_ADDR (REGS_SIM_BASE + 0x1054U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_UIDH (*(__I hw_sim_uidh_t *) HW_SIM_UIDH_ADDR)
+#define HW_SIM_UIDH_RD() (HW_SIM_UIDH.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_UIDH bitfields
+ */
+
+/*!
+ * @name Register SIM_UIDH, field UID[31:0] (RO)
+ *
+ * Unique identification for the device.
+ */
+//@{
+#define BP_SIM_UIDH_UID (0U) //!< Bit position for SIM_UIDH_UID.
+#define BM_SIM_UIDH_UID (0xFFFFFFFFU) //!< Bit mask for SIM_UIDH_UID.
+#define BS_SIM_UIDH_UID (32U) //!< Bit field size in bits for SIM_UIDH_UID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_UIDH_UID field.
+#define BR_SIM_UIDH_UID (HW_SIM_UIDH.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_UIDMH - Unique Identification Register Mid-High
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_UIDMH - Unique Identification Register Mid-High (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_sim_uidmh
+{
+ uint32_t U;
+ struct _hw_sim_uidmh_bitfields
+ {
+ uint32_t UID : 32; //!< [31:0] Unique Identification
+ } B;
+} hw_sim_uidmh_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_UIDMH register
+ */
+//@{
+#define HW_SIM_UIDMH_ADDR (REGS_SIM_BASE + 0x1058U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_UIDMH (*(__I hw_sim_uidmh_t *) HW_SIM_UIDMH_ADDR)
+#define HW_SIM_UIDMH_RD() (HW_SIM_UIDMH.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_UIDMH bitfields
+ */
+
+/*!
+ * @name Register SIM_UIDMH, field UID[31:0] (RO)
+ *
+ * Unique identification for the device.
+ */
+//@{
+#define BP_SIM_UIDMH_UID (0U) //!< Bit position for SIM_UIDMH_UID.
+#define BM_SIM_UIDMH_UID (0xFFFFFFFFU) //!< Bit mask for SIM_UIDMH_UID.
+#define BS_SIM_UIDMH_UID (32U) //!< Bit field size in bits for SIM_UIDMH_UID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_UIDMH_UID field.
+#define BR_SIM_UIDMH_UID (HW_SIM_UIDMH.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_UIDML - Unique Identification Register Mid Low
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_UIDML - Unique Identification Register Mid Low (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_sim_uidml
+{
+ uint32_t U;
+ struct _hw_sim_uidml_bitfields
+ {
+ uint32_t UID : 32; //!< [31:0] Unique Identification
+ } B;
+} hw_sim_uidml_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_UIDML register
+ */
+//@{
+#define HW_SIM_UIDML_ADDR (REGS_SIM_BASE + 0x105CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_UIDML (*(__I hw_sim_uidml_t *) HW_SIM_UIDML_ADDR)
+#define HW_SIM_UIDML_RD() (HW_SIM_UIDML.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_UIDML bitfields
+ */
+
+/*!
+ * @name Register SIM_UIDML, field UID[31:0] (RO)
+ *
+ * Unique identification for the device.
+ */
+//@{
+#define BP_SIM_UIDML_UID (0U) //!< Bit position for SIM_UIDML_UID.
+#define BM_SIM_UIDML_UID (0xFFFFFFFFU) //!< Bit mask for SIM_UIDML_UID.
+#define BS_SIM_UIDML_UID (32U) //!< Bit field size in bits for SIM_UIDML_UID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_UIDML_UID field.
+#define BR_SIM_UIDML_UID (HW_SIM_UIDML.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SIM_UIDL - Unique Identification Register Low
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SIM_UIDL - Unique Identification Register Low (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+typedef union _hw_sim_uidl
+{
+ uint32_t U;
+ struct _hw_sim_uidl_bitfields
+ {
+ uint32_t UID : 32; //!< [31:0] Unique Identification
+ } B;
+} hw_sim_uidl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SIM_UIDL register
+ */
+//@{
+#define HW_SIM_UIDL_ADDR (REGS_SIM_BASE + 0x1060U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SIM_UIDL (*(__I hw_sim_uidl_t *) HW_SIM_UIDL_ADDR)
+#define HW_SIM_UIDL_RD() (HW_SIM_UIDL.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SIM_UIDL bitfields
+ */
+
+/*!
+ * @name Register SIM_UIDL, field UID[31:0] (RO)
+ *
+ * Unique identification for the device.
+ */
+//@{
+#define BP_SIM_UIDL_UID (0U) //!< Bit position for SIM_UIDL_UID.
+#define BM_SIM_UIDL_UID (0xFFFFFFFFU) //!< Bit mask for SIM_UIDL_UID.
+#define BS_SIM_UIDL_UID (32U) //!< Bit field size in bits for SIM_UIDL_UID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SIM_UIDL_UID field.
+#define BR_SIM_UIDL_UID (HW_SIM_UIDL.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_sim_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All SIM module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_sim
+{
+ __IO hw_sim_sopt1_t SOPT1; //!< [0x0] System Options Register 1
+ __IO hw_sim_sopt1cfg_t SOPT1CFG; //!< [0x4] SOPT1 Configuration Register
+ uint8_t _reserved0[4092];
+ __IO hw_sim_sopt2_t SOPT2; //!< [0x1004] System Options Register 2
+ uint8_t _reserved1[4];
+ __IO hw_sim_sopt4_t SOPT4; //!< [0x100C] System Options Register 4
+ __IO hw_sim_sopt5_t SOPT5; //!< [0x1010] System Options Register 5
+ uint8_t _reserved2[4];
+ __IO hw_sim_sopt7_t SOPT7; //!< [0x1018] System Options Register 7
+ uint8_t _reserved3[8];
+ __I hw_sim_sdid_t SDID; //!< [0x1024] System Device Identification Register
+ __IO hw_sim_scgc1_t SCGC1; //!< [0x1028] System Clock Gating Control Register 1
+ __IO hw_sim_scgc2_t SCGC2; //!< [0x102C] System Clock Gating Control Register 2
+ __IO hw_sim_scgc3_t SCGC3; //!< [0x1030] System Clock Gating Control Register 3
+ __IO hw_sim_scgc4_t SCGC4; //!< [0x1034] System Clock Gating Control Register 4
+ __IO hw_sim_scgc5_t SCGC5; //!< [0x1038] System Clock Gating Control Register 5
+ __IO hw_sim_scgc6_t SCGC6; //!< [0x103C] System Clock Gating Control Register 6
+ __IO hw_sim_scgc7_t SCGC7; //!< [0x1040] System Clock Gating Control Register 7
+ __IO hw_sim_clkdiv1_t CLKDIV1; //!< [0x1044] System Clock Divider Register 1
+ __IO hw_sim_clkdiv2_t CLKDIV2; //!< [0x1048] System Clock Divider Register 2
+ __IO hw_sim_fcfg1_t FCFG1; //!< [0x104C] Flash Configuration Register 1
+ __I hw_sim_fcfg2_t FCFG2; //!< [0x1050] Flash Configuration Register 2
+ __I hw_sim_uidh_t UIDH; //!< [0x1054] Unique Identification Register High
+ __I hw_sim_uidmh_t UIDMH; //!< [0x1058] Unique Identification Register Mid-High
+ __I hw_sim_uidml_t UIDML; //!< [0x105C] Unique Identification Register Mid Low
+ __I hw_sim_uidl_t UIDL; //!< [0x1060] Unique Identification Register Low
+} hw_sim_t;
+#pragma pack()
+
+//! @brief Macro to access all SIM registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_SIM</code>.
+#define HW_SIM (*(hw_sim_t *) REGS_SIM_BASE)
+#endif
+
+#endif // __HW_SIM_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_smc.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,566 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_SMC_REGISTERS_H__
+#define __HW_SMC_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 SMC
+ *
+ * System Mode Controller
+ *
+ * Registers defined in this header file:
+ * - HW_SMC_PMPROT - Power Mode Protection register
+ * - HW_SMC_PMCTRL - Power Mode Control register
+ * - HW_SMC_VLLSCTRL - VLLS Control register
+ * - HW_SMC_PMSTAT - Power Mode Status register
+ *
+ * - hw_smc_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_SMC_BASE
+#define HW_SMC_INSTANCE_COUNT (1U) //!< Number of instances of the SMC module.
+#define REGS_SMC_BASE (0x4007E000U) //!< Base address for SMC.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SMC_PMPROT - Power Mode Protection register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SMC_PMPROT - Power Mode Protection register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides protection for entry into any low-power run or stop
+ * mode. The enabling of the low-power run or stop mode occurs by configuring the
+ * Power Mode Control register (PMCTRL). The PMPROT register can be written only
+ * once after any system reset. If the MCU is configured for a disallowed or
+ * reserved power mode, the MCU remains in its current power mode. For example, if the
+ * MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using
+ * PMCTRL[RUNM] is blocked and PMCTRL[RUNM] remains 00b, indicating the MCU is
+ * still in Normal Run mode. This register is reset on Chip Reset not VLLS and by
+ * reset types that trigger Chip Reset not VLLS. It is unaffected by reset types
+ * that do not trigger Chip Reset not VLLS. See the Reset section details for more
+ * information.
+ */
+typedef union _hw_smc_pmprot
+{
+ uint8_t U;
+ struct _hw_smc_pmprot_bitfields
+ {
+ uint8_t RESERVED0 : 1; //!< [0]
+ uint8_t AVLLS : 1; //!< [1] Allow Very-Low-Leakage Stop Mode
+ uint8_t RESERVED1 : 1; //!< [2]
+ uint8_t ALLS : 1; //!< [3] Allow Low-Leakage Stop Mode
+ uint8_t RESERVED2 : 1; //!< [4]
+ uint8_t AVLP : 1; //!< [5] Allow Very-Low-Power Modes
+ uint8_t RESERVED3 : 2; //!< [7:6]
+ } B;
+} hw_smc_pmprot_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SMC_PMPROT register
+ */
+//@{
+#define HW_SMC_PMPROT_ADDR (REGS_SMC_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SMC_PMPROT (*(__IO hw_smc_pmprot_t *) HW_SMC_PMPROT_ADDR)
+#define HW_SMC_PMPROT_RD() (HW_SMC_PMPROT.U)
+#define HW_SMC_PMPROT_WR(v) (HW_SMC_PMPROT.U = (v))
+#define HW_SMC_PMPROT_SET(v) (HW_SMC_PMPROT_WR(HW_SMC_PMPROT_RD() | (v)))
+#define HW_SMC_PMPROT_CLR(v) (HW_SMC_PMPROT_WR(HW_SMC_PMPROT_RD() & ~(v)))
+#define HW_SMC_PMPROT_TOG(v) (HW_SMC_PMPROT_WR(HW_SMC_PMPROT_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SMC_PMPROT bitfields
+ */
+
+/*!
+ * @name Register SMC_PMPROT, field AVLLS[1] (RW)
+ *
+ * Provided the appropriate control bits are set up in PMCTRL, this write once
+ * bit allows the MCU to enter any very-low-leakage stop mode (VLLSx).
+ *
+ * Values:
+ * - 0 - Any VLLSx mode is not allowed
+ * - 1 - Any VLLSx mode is allowed
+ */
+//@{
+#define BP_SMC_PMPROT_AVLLS (1U) //!< Bit position for SMC_PMPROT_AVLLS.
+#define BM_SMC_PMPROT_AVLLS (0x02U) //!< Bit mask for SMC_PMPROT_AVLLS.
+#define BS_SMC_PMPROT_AVLLS (1U) //!< Bit field size in bits for SMC_PMPROT_AVLLS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SMC_PMPROT_AVLLS field.
+#define BR_SMC_PMPROT_AVLLS (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_AVLLS))
+#endif
+
+//! @brief Format value for bitfield SMC_PMPROT_AVLLS.
+#define BF_SMC_PMPROT_AVLLS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMPROT_AVLLS), uint8_t) & BM_SMC_PMPROT_AVLLS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AVLLS field to a new value.
+#define BW_SMC_PMPROT_AVLLS(v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_AVLLS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SMC_PMPROT, field ALLS[3] (RW)
+ *
+ * Provided the appropriate control bits are set up in PMCTRL, this write-once
+ * field allows the MCU to enter any low-leakage stop mode (LLS).
+ *
+ * Values:
+ * - 0 - LLS is not allowed
+ * - 1 - LLS is allowed
+ */
+//@{
+#define BP_SMC_PMPROT_ALLS (3U) //!< Bit position for SMC_PMPROT_ALLS.
+#define BM_SMC_PMPROT_ALLS (0x08U) //!< Bit mask for SMC_PMPROT_ALLS.
+#define BS_SMC_PMPROT_ALLS (1U) //!< Bit field size in bits for SMC_PMPROT_ALLS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SMC_PMPROT_ALLS field.
+#define BR_SMC_PMPROT_ALLS (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_ALLS))
+#endif
+
+//! @brief Format value for bitfield SMC_PMPROT_ALLS.
+#define BF_SMC_PMPROT_ALLS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMPROT_ALLS), uint8_t) & BM_SMC_PMPROT_ALLS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ALLS field to a new value.
+#define BW_SMC_PMPROT_ALLS(v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_ALLS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SMC_PMPROT, field AVLP[5] (RW)
+ *
+ * Provided the appropriate control bits are set up in PMCTRL, this write-once
+ * field allows the MCU to enter any very-low-power mode (VLPR, VLPW, and VLPS).
+ *
+ * Values:
+ * - 0 - VLPR, VLPW, and VLPS are not allowed.
+ * - 1 - VLPR, VLPW, and VLPS are allowed.
+ */
+//@{
+#define BP_SMC_PMPROT_AVLP (5U) //!< Bit position for SMC_PMPROT_AVLP.
+#define BM_SMC_PMPROT_AVLP (0x20U) //!< Bit mask for SMC_PMPROT_AVLP.
+#define BS_SMC_PMPROT_AVLP (1U) //!< Bit field size in bits for SMC_PMPROT_AVLP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SMC_PMPROT_AVLP field.
+#define BR_SMC_PMPROT_AVLP (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_AVLP))
+#endif
+
+//! @brief Format value for bitfield SMC_PMPROT_AVLP.
+#define BF_SMC_PMPROT_AVLP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMPROT_AVLP), uint8_t) & BM_SMC_PMPROT_AVLP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AVLP field to a new value.
+#define BW_SMC_PMPROT_AVLP(v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_AVLP) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SMC_PMCTRL - Power Mode Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SMC_PMCTRL - Power Mode Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The PMCTRL register controls entry into low-power Run and Stop modes,
+ * provided that the selected power mode is allowed via an appropriate setting of the
+ * protection (PMPROT) register. This register is reset on Chip POR not VLLS and by
+ * reset types that trigger Chip POR not VLLS. It is unaffected by reset types
+ * that do not trigger Chip POR not VLLS. See the Reset section details for more
+ * information.
+ */
+typedef union _hw_smc_pmctrl
+{
+ uint8_t U;
+ struct _hw_smc_pmctrl_bitfields
+ {
+ uint8_t STOPM : 3; //!< [2:0] Stop Mode Control
+ uint8_t STOPA : 1; //!< [3] Stop Aborted
+ uint8_t RESERVED0 : 1; //!< [4]
+ uint8_t RUNM : 2; //!< [6:5] Run Mode Control
+ uint8_t LPWUI : 1; //!< [7] Low-Power Wake Up On Interrupt
+ } B;
+} hw_smc_pmctrl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SMC_PMCTRL register
+ */
+//@{
+#define HW_SMC_PMCTRL_ADDR (REGS_SMC_BASE + 0x1U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SMC_PMCTRL (*(__IO hw_smc_pmctrl_t *) HW_SMC_PMCTRL_ADDR)
+#define HW_SMC_PMCTRL_RD() (HW_SMC_PMCTRL.U)
+#define HW_SMC_PMCTRL_WR(v) (HW_SMC_PMCTRL.U = (v))
+#define HW_SMC_PMCTRL_SET(v) (HW_SMC_PMCTRL_WR(HW_SMC_PMCTRL_RD() | (v)))
+#define HW_SMC_PMCTRL_CLR(v) (HW_SMC_PMCTRL_WR(HW_SMC_PMCTRL_RD() & ~(v)))
+#define HW_SMC_PMCTRL_TOG(v) (HW_SMC_PMCTRL_WR(HW_SMC_PMCTRL_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SMC_PMCTRL bitfields
+ */
+
+/*!
+ * @name Register SMC_PMCTRL, field STOPM[2:0] (RW)
+ *
+ * When written, controls entry into the selected stop mode when Sleep-Now or
+ * Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are
+ * blocked if the protection level has not been enabled using the PMPROT register.
+ * After any system reset, this field is cleared by hardware on any successful write
+ * to the PMPROT register. When set to VLLSx, the VLLSM field in the VLLSCTRL
+ * register is used to further select the particular VLLS submode which will be
+ * entered.
+ *
+ * Values:
+ * - 000 - Normal Stop (STOP)
+ * - 001 - Reserved
+ * - 010 - Very-Low-Power Stop (VLPS)
+ * - 011 - Low-Leakage Stop (LLS)
+ * - 100 - Very-Low-Leakage Stop (VLLSx)
+ * - 101 - Reserved
+ * - 110 - Reseved
+ * - 111 - Reserved
+ */
+//@{
+#define BP_SMC_PMCTRL_STOPM (0U) //!< Bit position for SMC_PMCTRL_STOPM.
+#define BM_SMC_PMCTRL_STOPM (0x07U) //!< Bit mask for SMC_PMCTRL_STOPM.
+#define BS_SMC_PMCTRL_STOPM (3U) //!< Bit field size in bits for SMC_PMCTRL_STOPM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SMC_PMCTRL_STOPM field.
+#define BR_SMC_PMCTRL_STOPM (HW_SMC_PMCTRL.B.STOPM)
+#endif
+
+//! @brief Format value for bitfield SMC_PMCTRL_STOPM.
+#define BF_SMC_PMCTRL_STOPM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMCTRL_STOPM), uint8_t) & BM_SMC_PMCTRL_STOPM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the STOPM field to a new value.
+#define BW_SMC_PMCTRL_STOPM(v) (HW_SMC_PMCTRL_WR((HW_SMC_PMCTRL_RD() & ~BM_SMC_PMCTRL_STOPM) | BF_SMC_PMCTRL_STOPM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SMC_PMCTRL, field STOPA[3] (RO)
+ *
+ * When set, this read-only status bit indicates an interrupt or reset occured
+ * during the previous stop mode entry sequence, preventing the system from
+ * entering that mode. This field is cleared by hardware at the beginning of any stop
+ * mode entry sequence and is set if the sequence was aborted.
+ *
+ * Values:
+ * - 0 - The previous stop mode entry was successsful.
+ * - 1 - The previous stop mode entry was aborted.
+ */
+//@{
+#define BP_SMC_PMCTRL_STOPA (3U) //!< Bit position for SMC_PMCTRL_STOPA.
+#define BM_SMC_PMCTRL_STOPA (0x08U) //!< Bit mask for SMC_PMCTRL_STOPA.
+#define BS_SMC_PMCTRL_STOPA (1U) //!< Bit field size in bits for SMC_PMCTRL_STOPA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SMC_PMCTRL_STOPA field.
+#define BR_SMC_PMCTRL_STOPA (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR, BP_SMC_PMCTRL_STOPA))
+#endif
+//@}
+
+/*!
+ * @name Register SMC_PMCTRL, field RUNM[6:5] (RW)
+ *
+ * When written, causes entry into the selected run mode. Writes to this field
+ * are blocked if the protection level has not been enabled using the PMPROT
+ * register. RUNM may be set to VLPR only when PMSTAT=RUN. After being written to
+ * VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR.
+ *
+ * Values:
+ * - 00 - Normal Run mode (RUN)
+ * - 01 - Reserved
+ * - 10 - Very-Low-Power Run mode (VLPR)
+ * - 11 - Reserved
+ */
+//@{
+#define BP_SMC_PMCTRL_RUNM (5U) //!< Bit position for SMC_PMCTRL_RUNM.
+#define BM_SMC_PMCTRL_RUNM (0x60U) //!< Bit mask for SMC_PMCTRL_RUNM.
+#define BS_SMC_PMCTRL_RUNM (2U) //!< Bit field size in bits for SMC_PMCTRL_RUNM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SMC_PMCTRL_RUNM field.
+#define BR_SMC_PMCTRL_RUNM (HW_SMC_PMCTRL.B.RUNM)
+#endif
+
+//! @brief Format value for bitfield SMC_PMCTRL_RUNM.
+#define BF_SMC_PMCTRL_RUNM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMCTRL_RUNM), uint8_t) & BM_SMC_PMCTRL_RUNM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RUNM field to a new value.
+#define BW_SMC_PMCTRL_RUNM(v) (HW_SMC_PMCTRL_WR((HW_SMC_PMCTRL_RD() & ~BM_SMC_PMCTRL_RUNM) | BF_SMC_PMCTRL_RUNM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SMC_PMCTRL, field LPWUI[7] (RW)
+ *
+ * Causes the SMC to exit to normal RUN mode when any active MCU interrupt
+ * occurs while in a VLP mode (VLPR, VLPW or VLPS). If VLPS mode was entered directly
+ * from RUN mode, the SMC will always exit back to normal RUN mode regardless of
+ * the LPWUI setting. LPWUI must be modified only while the system is in RUN
+ * mode, that is, when PMSTAT=RUN.
+ *
+ * Values:
+ * - 0 - The system remains in a VLP mode on an interrupt
+ * - 1 - The system exits to Normal RUN mode on an interrupt
+ */
+//@{
+#define BP_SMC_PMCTRL_LPWUI (7U) //!< Bit position for SMC_PMCTRL_LPWUI.
+#define BM_SMC_PMCTRL_LPWUI (0x80U) //!< Bit mask for SMC_PMCTRL_LPWUI.
+#define BS_SMC_PMCTRL_LPWUI (1U) //!< Bit field size in bits for SMC_PMCTRL_LPWUI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SMC_PMCTRL_LPWUI field.
+#define BR_SMC_PMCTRL_LPWUI (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR, BP_SMC_PMCTRL_LPWUI))
+#endif
+
+//! @brief Format value for bitfield SMC_PMCTRL_LPWUI.
+#define BF_SMC_PMCTRL_LPWUI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMCTRL_LPWUI), uint8_t) & BM_SMC_PMCTRL_LPWUI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LPWUI field to a new value.
+#define BW_SMC_PMCTRL_LPWUI(v) (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR, BP_SMC_PMCTRL_LPWUI) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SMC_VLLSCTRL - VLLS Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SMC_VLLSCTRL - VLLS Control register (RW)
+ *
+ * Reset value: 0x03U
+ *
+ * The VLLSCTRL register controls features related to VLLS modes. This register
+ * is reset on Chip POR not VLLS and by reset types that trigger Chip POR not
+ * VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See
+ * the Reset section details for more information.
+ */
+typedef union _hw_smc_vllsctrl
+{
+ uint8_t U;
+ struct _hw_smc_vllsctrl_bitfields
+ {
+ uint8_t VLLSM : 3; //!< [2:0] VLLS Mode Control
+ uint8_t RESERVED0 : 2; //!< [4:3]
+ uint8_t PORPO : 1; //!< [5] POR Power Option
+ uint8_t RESERVED1 : 2; //!< [7:6]
+ } B;
+} hw_smc_vllsctrl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SMC_VLLSCTRL register
+ */
+//@{
+#define HW_SMC_VLLSCTRL_ADDR (REGS_SMC_BASE + 0x2U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SMC_VLLSCTRL (*(__IO hw_smc_vllsctrl_t *) HW_SMC_VLLSCTRL_ADDR)
+#define HW_SMC_VLLSCTRL_RD() (HW_SMC_VLLSCTRL.U)
+#define HW_SMC_VLLSCTRL_WR(v) (HW_SMC_VLLSCTRL.U = (v))
+#define HW_SMC_VLLSCTRL_SET(v) (HW_SMC_VLLSCTRL_WR(HW_SMC_VLLSCTRL_RD() | (v)))
+#define HW_SMC_VLLSCTRL_CLR(v) (HW_SMC_VLLSCTRL_WR(HW_SMC_VLLSCTRL_RD() & ~(v)))
+#define HW_SMC_VLLSCTRL_TOG(v) (HW_SMC_VLLSCTRL_WR(HW_SMC_VLLSCTRL_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SMC_VLLSCTRL bitfields
+ */
+
+/*!
+ * @name Register SMC_VLLSCTRL, field VLLSM[2:0] (RW)
+ *
+ * Controls which VLLS sub-mode to enter if STOPM=VLLS.
+ *
+ * Values:
+ * - 000 - VLLS0
+ * - 001 - VLLS1
+ * - 010 - VLLS2
+ * - 011 - VLLS3
+ * - 100 - Reserved
+ * - 101 - Reserved
+ * - 110 - Reserved
+ * - 111 - Reserved
+ */
+//@{
+#define BP_SMC_VLLSCTRL_VLLSM (0U) //!< Bit position for SMC_VLLSCTRL_VLLSM.
+#define BM_SMC_VLLSCTRL_VLLSM (0x07U) //!< Bit mask for SMC_VLLSCTRL_VLLSM.
+#define BS_SMC_VLLSCTRL_VLLSM (3U) //!< Bit field size in bits for SMC_VLLSCTRL_VLLSM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SMC_VLLSCTRL_VLLSM field.
+#define BR_SMC_VLLSCTRL_VLLSM (HW_SMC_VLLSCTRL.B.VLLSM)
+#endif
+
+//! @brief Format value for bitfield SMC_VLLSCTRL_VLLSM.
+#define BF_SMC_VLLSCTRL_VLLSM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_VLLSCTRL_VLLSM), uint8_t) & BM_SMC_VLLSCTRL_VLLSM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the VLLSM field to a new value.
+#define BW_SMC_VLLSCTRL_VLLSM(v) (HW_SMC_VLLSCTRL_WR((HW_SMC_VLLSCTRL_RD() & ~BM_SMC_VLLSCTRL_VLLSM) | BF_SMC_VLLSCTRL_VLLSM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SMC_VLLSCTRL, field PORPO[5] (RW)
+ *
+ * Controls whether the POR detect circuit (for brown-out detection) is enabled
+ * in VLLS0 mode.
+ *
+ * Values:
+ * - 0 - POR detect circuit is enabled in VLLS0.
+ * - 1 - POR detect circuit is disabled in VLLS0.
+ */
+//@{
+#define BP_SMC_VLLSCTRL_PORPO (5U) //!< Bit position for SMC_VLLSCTRL_PORPO.
+#define BM_SMC_VLLSCTRL_PORPO (0x20U) //!< Bit mask for SMC_VLLSCTRL_PORPO.
+#define BS_SMC_VLLSCTRL_PORPO (1U) //!< Bit field size in bits for SMC_VLLSCTRL_PORPO.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SMC_VLLSCTRL_PORPO field.
+#define BR_SMC_VLLSCTRL_PORPO (BITBAND_ACCESS8(HW_SMC_VLLSCTRL_ADDR, BP_SMC_VLLSCTRL_PORPO))
+#endif
+
+//! @brief Format value for bitfield SMC_VLLSCTRL_PORPO.
+#define BF_SMC_VLLSCTRL_PORPO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_VLLSCTRL_PORPO), uint8_t) & BM_SMC_VLLSCTRL_PORPO)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PORPO field to a new value.
+#define BW_SMC_VLLSCTRL_PORPO(v) (BITBAND_ACCESS8(HW_SMC_VLLSCTRL_ADDR, BP_SMC_VLLSCTRL_PORPO) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SMC_PMSTAT - Power Mode Status register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SMC_PMSTAT - Power Mode Status register (RO)
+ *
+ * Reset value: 0x01U
+ *
+ * PMSTAT is a read-only, one-hot register which indicates the current power
+ * mode of the system. This register is reset on Chip POR not VLLS and by reset
+ * types that trigger Chip POR not VLLS. It is unaffected by reset types that do not
+ * trigger Chip POR not VLLS. See the Reset section details for more information.
+ */
+typedef union _hw_smc_pmstat
+{
+ uint8_t U;
+ struct _hw_smc_pmstat_bitfields
+ {
+ uint8_t PMSTAT : 7; //!< [6:0]
+ uint8_t RESERVED0 : 1; //!< [7]
+ } B;
+} hw_smc_pmstat_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SMC_PMSTAT register
+ */
+//@{
+#define HW_SMC_PMSTAT_ADDR (REGS_SMC_BASE + 0x3U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SMC_PMSTAT (*(__I hw_smc_pmstat_t *) HW_SMC_PMSTAT_ADDR)
+#define HW_SMC_PMSTAT_RD() (HW_SMC_PMSTAT.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SMC_PMSTAT bitfields
+ */
+
+/*!
+ * @name Register SMC_PMSTAT, field PMSTAT[6:0] (RO)
+ *
+ * When debug is enabled, the PMSTAT will not update to STOP or VLPS
+ */
+//@{
+#define BP_SMC_PMSTAT_PMSTAT (0U) //!< Bit position for SMC_PMSTAT_PMSTAT.
+#define BM_SMC_PMSTAT_PMSTAT (0x7FU) //!< Bit mask for SMC_PMSTAT_PMSTAT.
+#define BS_SMC_PMSTAT_PMSTAT (7U) //!< Bit field size in bits for SMC_PMSTAT_PMSTAT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SMC_PMSTAT_PMSTAT field.
+#define BR_SMC_PMSTAT_PMSTAT (HW_SMC_PMSTAT.B.PMSTAT)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_smc_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All SMC module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_smc
+{
+ __IO hw_smc_pmprot_t PMPROT; //!< [0x0] Power Mode Protection register
+ __IO hw_smc_pmctrl_t PMCTRL; //!< [0x1] Power Mode Control register
+ __IO hw_smc_vllsctrl_t VLLSCTRL; //!< [0x2] VLLS Control register
+ __I hw_smc_pmstat_t PMSTAT; //!< [0x3] Power Mode Status register
+} hw_smc_t;
+#pragma pack()
+
+//! @brief Macro to access all SMC registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_SMC</code>.
+#define HW_SMC (*(hw_smc_t *) REGS_SMC_BASE)
+#endif
+
+#endif // __HW_SMC_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_spi.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,2445 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_SPI_REGISTERS_H__
+#define __HW_SPI_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 SPI
+ *
+ * Serial Peripheral Interface
+ *
+ * Registers defined in this header file:
+ * - HW_SPI_MCR - Module Configuration Register
+ * - HW_SPI_TCR - Transfer Count Register
+ * - HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode)
+ * - HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
+ * - HW_SPI_SR - Status Register
+ * - HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register
+ * - HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode
+ * - HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
+ * - HW_SPI_POPR - POP RX FIFO Register
+ * - HW_SPI_TXFRn - Transmit FIFO Registers
+ * - HW_SPI_RXFRn - Receive FIFO Registers
+ *
+ * - hw_spi_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_SPI_BASE
+#define HW_SPI_INSTANCE_COUNT (3U) //!< Number of instances of the SPI module.
+#define HW_SPI0 (0U) //!< Instance number for SPI0.
+#define HW_SPI1 (1U) //!< Instance number for SPI1.
+#define HW_SPI2 (2U) //!< Instance number for SPI2.
+#define REGS_SPI0_BASE (0x4002C000U) //!< Base address for SPI0.
+#define REGS_SPI1_BASE (0x4002D000U) //!< Base address for SPI1.
+#define REGS_SPI2_BASE (0x400AC000U) //!< Base address for SPI2.
+
+//! @brief Table of base addresses for SPI instances.
+static const uint32_t __g_regs_SPI_base_addresses[] = {
+ REGS_SPI0_BASE,
+ REGS_SPI1_BASE,
+ REGS_SPI2_BASE,
+ };
+
+//! @brief Get the base address of SPI by instance number.
+//! @param x SPI instance number, from 0 through 2.
+#define REGS_SPI_BASE(x) (__g_regs_SPI_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of SPI.
+#define REGS_SPI_INSTANCE(b) ((b) == REGS_SPI0_BASE ? HW_SPI0 : (b) == REGS_SPI1_BASE ? HW_SPI1 : (b) == REGS_SPI2_BASE ? HW_SPI2 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SPI_MCR - Module Configuration Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SPI_MCR - Module Configuration Register (RW)
+ *
+ * Reset value: 0x00004001U
+ *
+ * Contains bits to configure various attributes associated with the module
+ * operations. The HALT and MDIS bits can be changed at any time, but the effect
+ * takes place only on the next frame boundary. Only the HALT and MDIS bits in the
+ * MCR can be changed, while the module is in the Running state.
+ */
+typedef union _hw_spi_mcr
+{
+ uint32_t U;
+ struct _hw_spi_mcr_bitfields
+ {
+ uint32_t HALT : 1; //!< [0] Halt
+ uint32_t RESERVED0 : 7; //!< [7:1]
+ uint32_t SMPL_PT : 2; //!< [9:8] Sample Point
+ uint32_t CLR_RXF : 1; //!< [10]
+ uint32_t CLR_TXF : 1; //!< [11] Clear TX FIFO
+ uint32_t DIS_RXF : 1; //!< [12] Disable Receive FIFO
+ uint32_t DIS_TXF : 1; //!< [13] Disable Transmit FIFO
+ uint32_t MDIS : 1; //!< [14] Module Disable
+ uint32_t DOZE : 1; //!< [15] Doze Enable
+ uint32_t PCSIS : 6; //!< [21:16] Peripheral Chip Select x Inactive
+ //! State
+ uint32_t RESERVED1 : 2; //!< [23:22]
+ uint32_t ROOE : 1; //!< [24] Receive FIFO Overflow Overwrite Enable
+ uint32_t PCSSE : 1; //!< [25] Peripheral Chip Select Strobe Enable
+ uint32_t MTFE : 1; //!< [26] Modified Timing Format Enable
+ uint32_t FRZ : 1; //!< [27] Freeze
+ uint32_t DCONF : 2; //!< [29:28] SPI Configuration.
+ uint32_t CONT_SCKE : 1; //!< [30] Continuous SCK Enable
+ uint32_t MSTR : 1; //!< [31] Master/Slave Mode Select
+ } B;
+} hw_spi_mcr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SPI_MCR register
+ */
+//@{
+#define HW_SPI_MCR_ADDR(x) (REGS_SPI_BASE(x) + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SPI_MCR(x) (*(__IO hw_spi_mcr_t *) HW_SPI_MCR_ADDR(x))
+#define HW_SPI_MCR_RD(x) (HW_SPI_MCR(x).U)
+#define HW_SPI_MCR_WR(x, v) (HW_SPI_MCR(x).U = (v))
+#define HW_SPI_MCR_SET(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) | (v)))
+#define HW_SPI_MCR_CLR(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) & ~(v)))
+#define HW_SPI_MCR_TOG(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SPI_MCR bitfields
+ */
+
+/*!
+ * @name Register SPI_MCR, field HALT[0] (RW)
+ *
+ * The HALT bit starts and stops frame transfers. See Start and Stop of Module
+ * transfers
+ *
+ * Values:
+ * - 0 - Start transfers.
+ * - 1 - Stop transfers.
+ */
+//@{
+#define BP_SPI_MCR_HALT (0U) //!< Bit position for SPI_MCR_HALT.
+#define BM_SPI_MCR_HALT (0x00000001U) //!< Bit mask for SPI_MCR_HALT.
+#define BS_SPI_MCR_HALT (1U) //!< Bit field size in bits for SPI_MCR_HALT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_MCR_HALT field.
+#define BR_SPI_MCR_HALT(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_HALT))
+#endif
+
+//! @brief Format value for bitfield SPI_MCR_HALT.
+#define BF_SPI_MCR_HALT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_HALT), uint32_t) & BM_SPI_MCR_HALT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HALT field to a new value.
+#define BW_SPI_MCR_HALT(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_HALT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field SMPL_PT[9:8] (RW)
+ *
+ * Controls when the module master samples SIN in Modified Transfer Format. This
+ * field is valid only when CPHA bit in CTARn[CPHA] is 0.
+ *
+ * Values:
+ * - 00 - 0 protocol clock cycles between SCK edge and SIN sample
+ * - 01 - 1 protocol clock cycle between SCK edge and SIN sample
+ * - 10 - 2 protocol clock cycles between SCK edge and SIN sample
+ * - 11 - Reserved
+ */
+//@{
+#define BP_SPI_MCR_SMPL_PT (8U) //!< Bit position for SPI_MCR_SMPL_PT.
+#define BM_SPI_MCR_SMPL_PT (0x00000300U) //!< Bit mask for SPI_MCR_SMPL_PT.
+#define BS_SPI_MCR_SMPL_PT (2U) //!< Bit field size in bits for SPI_MCR_SMPL_PT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_MCR_SMPL_PT field.
+#define BR_SPI_MCR_SMPL_PT(x) (HW_SPI_MCR(x).B.SMPL_PT)
+#endif
+
+//! @brief Format value for bitfield SPI_MCR_SMPL_PT.
+#define BF_SPI_MCR_SMPL_PT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_SMPL_PT), uint32_t) & BM_SPI_MCR_SMPL_PT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SMPL_PT field to a new value.
+#define BW_SPI_MCR_SMPL_PT(x, v) (HW_SPI_MCR_WR(x, (HW_SPI_MCR_RD(x) & ~BM_SPI_MCR_SMPL_PT) | BF_SPI_MCR_SMPL_PT(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field CLR_RXF[10] (WORZ)
+ *
+ * Flushes the RX FIFO. Writing a 1 to CLR_RXF clears the RX Counter. The
+ * CLR_RXF bit is always read as zero.
+ *
+ * Values:
+ * - 0 - Do not clear the RX FIFO counter.
+ * - 1 - Clear the RX FIFO counter.
+ */
+//@{
+#define BP_SPI_MCR_CLR_RXF (10U) //!< Bit position for SPI_MCR_CLR_RXF.
+#define BM_SPI_MCR_CLR_RXF (0x00000400U) //!< Bit mask for SPI_MCR_CLR_RXF.
+#define BS_SPI_MCR_CLR_RXF (1U) //!< Bit field size in bits for SPI_MCR_CLR_RXF.
+
+//! @brief Format value for bitfield SPI_MCR_CLR_RXF.
+#define BF_SPI_MCR_CLR_RXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_CLR_RXF), uint32_t) & BM_SPI_MCR_CLR_RXF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLR_RXF field to a new value.
+#define BW_SPI_MCR_CLR_RXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CLR_RXF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field CLR_TXF[11] (WORZ)
+ *
+ * Flushes the TX FIFO. Writing a 1 to CLR_TXF clears the TX FIFO Counter. The
+ * CLR_TXF bit is always read as zero.
+ *
+ * Values:
+ * - 0 - Do not clear the TX FIFO counter.
+ * - 1 - Clear the TX FIFO counter.
+ */
+//@{
+#define BP_SPI_MCR_CLR_TXF (11U) //!< Bit position for SPI_MCR_CLR_TXF.
+#define BM_SPI_MCR_CLR_TXF (0x00000800U) //!< Bit mask for SPI_MCR_CLR_TXF.
+#define BS_SPI_MCR_CLR_TXF (1U) //!< Bit field size in bits for SPI_MCR_CLR_TXF.
+
+//! @brief Format value for bitfield SPI_MCR_CLR_TXF.
+#define BF_SPI_MCR_CLR_TXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_CLR_TXF), uint32_t) & BM_SPI_MCR_CLR_TXF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLR_TXF field to a new value.
+#define BW_SPI_MCR_CLR_TXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CLR_TXF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field DIS_RXF[12] (RW)
+ *
+ * When the RX FIFO is disabled, the receive part of the module operates as a
+ * simplified double-buffered SPI. This bit can only be written when the MDIS bit
+ * is cleared.
+ *
+ * Values:
+ * - 0 - RX FIFO is enabled.
+ * - 1 - RX FIFO is disabled.
+ */
+//@{
+#define BP_SPI_MCR_DIS_RXF (12U) //!< Bit position for SPI_MCR_DIS_RXF.
+#define BM_SPI_MCR_DIS_RXF (0x00001000U) //!< Bit mask for SPI_MCR_DIS_RXF.
+#define BS_SPI_MCR_DIS_RXF (1U) //!< Bit field size in bits for SPI_MCR_DIS_RXF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_MCR_DIS_RXF field.
+#define BR_SPI_MCR_DIS_RXF(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_RXF))
+#endif
+
+//! @brief Format value for bitfield SPI_MCR_DIS_RXF.
+#define BF_SPI_MCR_DIS_RXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_DIS_RXF), uint32_t) & BM_SPI_MCR_DIS_RXF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DIS_RXF field to a new value.
+#define BW_SPI_MCR_DIS_RXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_RXF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field DIS_TXF[13] (RW)
+ *
+ * When the TX FIFO is disabled, the transmit part of the module operates as a
+ * simplified double-buffered SPI. This bit can be written only when the MDIS bit
+ * is cleared.
+ *
+ * Values:
+ * - 0 - TX FIFO is enabled.
+ * - 1 - TX FIFO is disabled.
+ */
+//@{
+#define BP_SPI_MCR_DIS_TXF (13U) //!< Bit position for SPI_MCR_DIS_TXF.
+#define BM_SPI_MCR_DIS_TXF (0x00002000U) //!< Bit mask for SPI_MCR_DIS_TXF.
+#define BS_SPI_MCR_DIS_TXF (1U) //!< Bit field size in bits for SPI_MCR_DIS_TXF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_MCR_DIS_TXF field.
+#define BR_SPI_MCR_DIS_TXF(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_TXF))
+#endif
+
+//! @brief Format value for bitfield SPI_MCR_DIS_TXF.
+#define BF_SPI_MCR_DIS_TXF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_DIS_TXF), uint32_t) & BM_SPI_MCR_DIS_TXF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DIS_TXF field to a new value.
+#define BW_SPI_MCR_DIS_TXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_TXF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field MDIS[14] (RW)
+ *
+ * Allows the clock to be stopped to the non-memory mapped logic in the module
+ * effectively putting it in a software-controlled power-saving state. The reset
+ * value of the MDIS bit is parameterized, with a default reset value of 0. When
+ * the module is used in Slave Mode, we recommend leaving this bit 0, because a
+ * slave doesn't have control over master transactions.
+ *
+ * Values:
+ * - 0 - Enables the module clocks.
+ * - 1 - Allows external logic to disable the module clocks.
+ */
+//@{
+#define BP_SPI_MCR_MDIS (14U) //!< Bit position for SPI_MCR_MDIS.
+#define BM_SPI_MCR_MDIS (0x00004000U) //!< Bit mask for SPI_MCR_MDIS.
+#define BS_SPI_MCR_MDIS (1U) //!< Bit field size in bits for SPI_MCR_MDIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_MCR_MDIS field.
+#define BR_SPI_MCR_MDIS(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MDIS))
+#endif
+
+//! @brief Format value for bitfield SPI_MCR_MDIS.
+#define BF_SPI_MCR_MDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_MDIS), uint32_t) & BM_SPI_MCR_MDIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MDIS field to a new value.
+#define BW_SPI_MCR_MDIS(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MDIS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field DOZE[15] (RW)
+ *
+ * Provides support for an externally controlled Doze mode power-saving
+ * mechanism.
+ *
+ * Values:
+ * - 0 - Doze mode has no effect on the module.
+ * - 1 - Doze mode disables the module.
+ */
+//@{
+#define BP_SPI_MCR_DOZE (15U) //!< Bit position for SPI_MCR_DOZE.
+#define BM_SPI_MCR_DOZE (0x00008000U) //!< Bit mask for SPI_MCR_DOZE.
+#define BS_SPI_MCR_DOZE (1U) //!< Bit field size in bits for SPI_MCR_DOZE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_MCR_DOZE field.
+#define BR_SPI_MCR_DOZE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DOZE))
+#endif
+
+//! @brief Format value for bitfield SPI_MCR_DOZE.
+#define BF_SPI_MCR_DOZE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_DOZE), uint32_t) & BM_SPI_MCR_DOZE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DOZE field to a new value.
+#define BW_SPI_MCR_DOZE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DOZE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field PCSIS[21:16] (RW)
+ *
+ * Determines the inactive state of PCSx.
+ *
+ * Values:
+ * - 0 - The inactive state of PCSx is low.
+ * - 1 - The inactive state of PCSx is high.
+ */
+//@{
+#define BP_SPI_MCR_PCSIS (16U) //!< Bit position for SPI_MCR_PCSIS.
+#define BM_SPI_MCR_PCSIS (0x003F0000U) //!< Bit mask for SPI_MCR_PCSIS.
+#define BS_SPI_MCR_PCSIS (6U) //!< Bit field size in bits for SPI_MCR_PCSIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_MCR_PCSIS field.
+#define BR_SPI_MCR_PCSIS(x) (HW_SPI_MCR(x).B.PCSIS)
+#endif
+
+//! @brief Format value for bitfield SPI_MCR_PCSIS.
+#define BF_SPI_MCR_PCSIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_PCSIS), uint32_t) & BM_SPI_MCR_PCSIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PCSIS field to a new value.
+#define BW_SPI_MCR_PCSIS(x, v) (HW_SPI_MCR_WR(x, (HW_SPI_MCR_RD(x) & ~BM_SPI_MCR_PCSIS) | BF_SPI_MCR_PCSIS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field ROOE[24] (RW)
+ *
+ * In the RX FIFO overflow condition, configures the module to ignore the
+ * incoming serial data or overwrite existing data. If the RX FIFO is full and new data
+ * is received, the data from the transfer, generating the overflow, is ignored
+ * or shifted into the shift register.
+ *
+ * Values:
+ * - 0 - Incoming data is ignored.
+ * - 1 - Incoming data is shifted into the shift register.
+ */
+//@{
+#define BP_SPI_MCR_ROOE (24U) //!< Bit position for SPI_MCR_ROOE.
+#define BM_SPI_MCR_ROOE (0x01000000U) //!< Bit mask for SPI_MCR_ROOE.
+#define BS_SPI_MCR_ROOE (1U) //!< Bit field size in bits for SPI_MCR_ROOE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_MCR_ROOE field.
+#define BR_SPI_MCR_ROOE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_ROOE))
+#endif
+
+//! @brief Format value for bitfield SPI_MCR_ROOE.
+#define BF_SPI_MCR_ROOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_ROOE), uint32_t) & BM_SPI_MCR_ROOE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ROOE field to a new value.
+#define BW_SPI_MCR_ROOE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_ROOE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field PCSSE[25] (RW)
+ *
+ * Enables the PCS5/ PCSS to operate as a PCS Strobe output signal.
+ *
+ * Values:
+ * - 0 - PCS5/ PCSS is used as the Peripheral Chip Select[5] signal.
+ * - 1 - PCS5/ PCSS is used as an active-low PCS Strobe signal.
+ */
+//@{
+#define BP_SPI_MCR_PCSSE (25U) //!< Bit position for SPI_MCR_PCSSE.
+#define BM_SPI_MCR_PCSSE (0x02000000U) //!< Bit mask for SPI_MCR_PCSSE.
+#define BS_SPI_MCR_PCSSE (1U) //!< Bit field size in bits for SPI_MCR_PCSSE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_MCR_PCSSE field.
+#define BR_SPI_MCR_PCSSE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_PCSSE))
+#endif
+
+//! @brief Format value for bitfield SPI_MCR_PCSSE.
+#define BF_SPI_MCR_PCSSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_PCSSE), uint32_t) & BM_SPI_MCR_PCSSE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PCSSE field to a new value.
+#define BW_SPI_MCR_PCSSE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_PCSSE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field MTFE[26] (RW)
+ *
+ * Enables a modified transfer format to be used.
+ *
+ * Values:
+ * - 0 - Modified SPI transfer format disabled.
+ * - 1 - Modified SPI transfer format enabled.
+ */
+//@{
+#define BP_SPI_MCR_MTFE (26U) //!< Bit position for SPI_MCR_MTFE.
+#define BM_SPI_MCR_MTFE (0x04000000U) //!< Bit mask for SPI_MCR_MTFE.
+#define BS_SPI_MCR_MTFE (1U) //!< Bit field size in bits for SPI_MCR_MTFE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_MCR_MTFE field.
+#define BR_SPI_MCR_MTFE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MTFE))
+#endif
+
+//! @brief Format value for bitfield SPI_MCR_MTFE.
+#define BF_SPI_MCR_MTFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_MTFE), uint32_t) & BM_SPI_MCR_MTFE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MTFE field to a new value.
+#define BW_SPI_MCR_MTFE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MTFE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field FRZ[27] (RW)
+ *
+ * Enables transfers to be stopped on the next frame boundary when the device
+ * enters Debug mode.
+ *
+ * Values:
+ * - 0 - Do not halt serial transfers in Debug mode.
+ * - 1 - Halt serial transfers in Debug mode.
+ */
+//@{
+#define BP_SPI_MCR_FRZ (27U) //!< Bit position for SPI_MCR_FRZ.
+#define BM_SPI_MCR_FRZ (0x08000000U) //!< Bit mask for SPI_MCR_FRZ.
+#define BS_SPI_MCR_FRZ (1U) //!< Bit field size in bits for SPI_MCR_FRZ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_MCR_FRZ field.
+#define BR_SPI_MCR_FRZ(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_FRZ))
+#endif
+
+//! @brief Format value for bitfield SPI_MCR_FRZ.
+#define BF_SPI_MCR_FRZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_FRZ), uint32_t) & BM_SPI_MCR_FRZ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FRZ field to a new value.
+#define BW_SPI_MCR_FRZ(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_FRZ) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field DCONF[29:28] (RO)
+ *
+ * Selects among the different configurations of the module.
+ *
+ * Values:
+ * - 00 - SPI
+ * - 01 - Reserved
+ * - 10 - Reserved
+ * - 11 - Reserved
+ */
+//@{
+#define BP_SPI_MCR_DCONF (28U) //!< Bit position for SPI_MCR_DCONF.
+#define BM_SPI_MCR_DCONF (0x30000000U) //!< Bit mask for SPI_MCR_DCONF.
+#define BS_SPI_MCR_DCONF (2U) //!< Bit field size in bits for SPI_MCR_DCONF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_MCR_DCONF field.
+#define BR_SPI_MCR_DCONF(x) (HW_SPI_MCR(x).B.DCONF)
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field CONT_SCKE[30] (RW)
+ *
+ * Enables the Serial Communication Clock (SCK) to run continuously.
+ *
+ * Values:
+ * - 0 - Continuous SCK disabled.
+ * - 1 - Continuous SCK enabled.
+ */
+//@{
+#define BP_SPI_MCR_CONT_SCKE (30U) //!< Bit position for SPI_MCR_CONT_SCKE.
+#define BM_SPI_MCR_CONT_SCKE (0x40000000U) //!< Bit mask for SPI_MCR_CONT_SCKE.
+#define BS_SPI_MCR_CONT_SCKE (1U) //!< Bit field size in bits for SPI_MCR_CONT_SCKE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_MCR_CONT_SCKE field.
+#define BR_SPI_MCR_CONT_SCKE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CONT_SCKE))
+#endif
+
+//! @brief Format value for bitfield SPI_MCR_CONT_SCKE.
+#define BF_SPI_MCR_CONT_SCKE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_CONT_SCKE), uint32_t) & BM_SPI_MCR_CONT_SCKE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CONT_SCKE field to a new value.
+#define BW_SPI_MCR_CONT_SCKE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CONT_SCKE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_MCR, field MSTR[31] (RW)
+ *
+ * Enables either Master mode (if supported) or Slave mode (if supported)
+ * operation.
+ *
+ * Values:
+ * - 0 - Enables Slave mode
+ * - 1 - Enables Master mode
+ */
+//@{
+#define BP_SPI_MCR_MSTR (31U) //!< Bit position for SPI_MCR_MSTR.
+#define BM_SPI_MCR_MSTR (0x80000000U) //!< Bit mask for SPI_MCR_MSTR.
+#define BS_SPI_MCR_MSTR (1U) //!< Bit field size in bits for SPI_MCR_MSTR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_MCR_MSTR field.
+#define BR_SPI_MCR_MSTR(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MSTR))
+#endif
+
+//! @brief Format value for bitfield SPI_MCR_MSTR.
+#define BF_SPI_MCR_MSTR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_MCR_MSTR), uint32_t) & BM_SPI_MCR_MSTR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MSTR field to a new value.
+#define BW_SPI_MCR_MSTR(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MSTR) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SPI_TCR - Transfer Count Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SPI_TCR - Transfer Count Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TCR contains a counter that indicates the number of SPI transfers made. The
+ * transfer counter is intended to assist in queue management. Do not write the
+ * TCR when the module is in the Running state.
+ */
+typedef union _hw_spi_tcr
+{
+ uint32_t U;
+ struct _hw_spi_tcr_bitfields
+ {
+ uint32_t RESERVED0 : 16; //!< [15:0]
+ uint32_t SPI_TCNT : 16; //!< [31:16] SPI Transfer Counter
+ } B;
+} hw_spi_tcr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SPI_TCR register
+ */
+//@{
+#define HW_SPI_TCR_ADDR(x) (REGS_SPI_BASE(x) + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SPI_TCR(x) (*(__IO hw_spi_tcr_t *) HW_SPI_TCR_ADDR(x))
+#define HW_SPI_TCR_RD(x) (HW_SPI_TCR(x).U)
+#define HW_SPI_TCR_WR(x, v) (HW_SPI_TCR(x).U = (v))
+#define HW_SPI_TCR_SET(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) | (v)))
+#define HW_SPI_TCR_CLR(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) & ~(v)))
+#define HW_SPI_TCR_TOG(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SPI_TCR bitfields
+ */
+
+/*!
+ * @name Register SPI_TCR, field SPI_TCNT[31:16] (RW)
+ *
+ * Counts the number of SPI transfers the module makes. The SPI_TCNT field
+ * increments every time the last bit of an SPI frame is transmitted. A value written
+ * to SPI_TCNT presets the counter to that value. SPI_TCNT is reset to zero at
+ * the beginning of the frame when the CTCNT field is set in the executing SPI
+ * command. The Transfer Counter wraps around; incrementing the counter past 65535
+ * resets the counter to zero.
+ */
+//@{
+#define BP_SPI_TCR_SPI_TCNT (16U) //!< Bit position for SPI_TCR_SPI_TCNT.
+#define BM_SPI_TCR_SPI_TCNT (0xFFFF0000U) //!< Bit mask for SPI_TCR_SPI_TCNT.
+#define BS_SPI_TCR_SPI_TCNT (16U) //!< Bit field size in bits for SPI_TCR_SPI_TCNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_TCR_SPI_TCNT field.
+#define BR_SPI_TCR_SPI_TCNT(x) (HW_SPI_TCR(x).B.SPI_TCNT)
+#endif
+
+//! @brief Format value for bitfield SPI_TCR_SPI_TCNT.
+#define BF_SPI_TCR_SPI_TCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_TCR_SPI_TCNT), uint32_t) & BM_SPI_TCR_SPI_TCNT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SPI_TCNT field to a new value.
+#define BW_SPI_TCR_SPI_TCNT(x, v) (HW_SPI_TCR_WR(x, (HW_SPI_TCR_RD(x) & ~BM_SPI_TCR_SPI_TCNT) | BF_SPI_TCR_SPI_TCNT(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode) (RW)
+ *
+ * Reset value: 0x78000000U
+ *
+ * CTAR registers are used to define different transfer attributes. Do not write
+ * to the CTAR registers while the module is in the Running state. In Master
+ * mode, the CTAR registers define combinations of transfer attributes such as frame
+ * size, clock phase and polarity, data bit ordering, baud rate, and various
+ * delays. In slave mode, a subset of the bitfields in CTAR0 are used to set the
+ * slave transfer attributes. When the module is configured as an SPI master, the
+ * CTAS field in the command portion of the TX FIFO entry selects which of the CTAR
+ * registers is used. When the module is configured as an SPI bus slave, it uses
+ * the CTAR0 register.
+ */
+typedef union _hw_spi_ctarn
+{
+ uint32_t U;
+ struct _hw_spi_ctarn_bitfields
+ {
+ uint32_t BR : 4; //!< [3:0] Baud Rate Scaler
+ uint32_t DT : 4; //!< [7:4] Delay After Transfer Scaler
+ uint32_t ASC : 4; //!< [11:8] After SCK Delay Scaler
+ uint32_t CSSCK : 4; //!< [15:12] PCS to SCK Delay Scaler
+ uint32_t PBR : 2; //!< [17:16] Baud Rate Prescaler
+ uint32_t PDT : 2; //!< [19:18] Delay after Transfer Prescaler
+ uint32_t PASC : 2; //!< [21:20] After SCK Delay Prescaler
+ uint32_t PCSSCK : 2; //!< [23:22] PCS to SCK Delay Prescaler
+ uint32_t LSBFE : 1; //!< [24] LSB First
+ uint32_t CPHA : 1; //!< [25] Clock Phase
+ uint32_t CPOL : 1; //!< [26] Clock Polarity
+ uint32_t FMSZ : 4; //!< [30:27] Frame Size
+ uint32_t DBR : 1; //!< [31] Double Baud Rate
+ } B;
+} hw_spi_ctarn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SPI_CTARn register
+ */
+//@{
+#define HW_SPI_CTARn_COUNT (2U)
+
+#define HW_SPI_CTARn_ADDR(x, n) (REGS_SPI_BASE(x) + 0xCU + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SPI_CTARn(x, n) (*(__IO hw_spi_ctarn_t *) HW_SPI_CTARn_ADDR(x, n))
+#define HW_SPI_CTARn_RD(x, n) (HW_SPI_CTARn(x, n).U)
+#define HW_SPI_CTARn_WR(x, n, v) (HW_SPI_CTARn(x, n).U = (v))
+#define HW_SPI_CTARn_SET(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) | (v)))
+#define HW_SPI_CTARn_CLR(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) & ~(v)))
+#define HW_SPI_CTARn_TOG(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SPI_CTARn bitfields
+ */
+
+/*!
+ * @name Register SPI_CTARn, field BR[3:0] (RW)
+ *
+ * Selects the scaler value for the baud rate. This field is used only in master
+ * mode. The prescaled protocol clock is divided by the Baud Rate Scaler to
+ * generate the frequency of the SCK. The baud rate is computed according to the
+ * following equation: SCK baud rate = (fP /PBR) x [(1+DBR)/BR] The following table
+ * lists the baud rate scaler values. Baud Rate Scaler CTARn[BR] Baud Rate Scaler
+ * Value 0000 2 0001 4 0010 6 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256
+ * 1001 512 1010 1024 1011 2048 1100 4096 1101 8192 1110 16384 1111 32768
+ */
+//@{
+#define BP_SPI_CTARn_BR (0U) //!< Bit position for SPI_CTARn_BR.
+#define BM_SPI_CTARn_BR (0x0000000FU) //!< Bit mask for SPI_CTARn_BR.
+#define BS_SPI_CTARn_BR (4U) //!< Bit field size in bits for SPI_CTARn_BR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_BR field.
+#define BR_SPI_CTARn_BR(x, n) (HW_SPI_CTARn(x, n).B.BR)
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_BR.
+#define BF_SPI_CTARn_BR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_BR), uint32_t) & BM_SPI_CTARn_BR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BR field to a new value.
+#define BW_SPI_CTARn_BR(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_BR) | BF_SPI_CTARn_BR(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_CTARn, field DT[7:4] (RW)
+ *
+ * Selects the Delay after Transfer Scaler. This field is used only in master
+ * mode. The Delay after Transfer is the time between the negation of the PCS
+ * signal at the end of a frame and the assertion of PCS at the beginning of the next
+ * frame. In the Continuous Serial Communications Clock operation, the DT value
+ * is fixed to one SCK clock period, The Delay after Transfer is a multiple of the
+ * protocol clock period, and it is computed according to the following
+ * equation: tDT = (1/fP ) x PDT x DT See Delay Scaler Encoding table in CTARn[CSSCK] bit
+ * field description for scaler values.
+ */
+//@{
+#define BP_SPI_CTARn_DT (4U) //!< Bit position for SPI_CTARn_DT.
+#define BM_SPI_CTARn_DT (0x000000F0U) //!< Bit mask for SPI_CTARn_DT.
+#define BS_SPI_CTARn_DT (4U) //!< Bit field size in bits for SPI_CTARn_DT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_DT field.
+#define BR_SPI_CTARn_DT(x, n) (HW_SPI_CTARn(x, n).B.DT)
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_DT.
+#define BF_SPI_CTARn_DT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_DT), uint32_t) & BM_SPI_CTARn_DT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DT field to a new value.
+#define BW_SPI_CTARn_DT(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_DT) | BF_SPI_CTARn_DT(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_CTARn, field ASC[11:8] (RW)
+ *
+ * Selects the scaler value for the After SCK Delay. This field is used only in
+ * master mode. The After SCK Delay is the delay between the last edge of SCK and
+ * the negation of PCS. The delay is a multiple of the protocol clock period,
+ * and it is computed according to the following equation: t ASC = (1/fP) x PASC x
+ * ASC See Delay Scaler Encoding table in CTARn[CSSCK] bit field description for
+ * scaler values. Refer After SCK Delay (tASC ) for more details.
+ */
+//@{
+#define BP_SPI_CTARn_ASC (8U) //!< Bit position for SPI_CTARn_ASC.
+#define BM_SPI_CTARn_ASC (0x00000F00U) //!< Bit mask for SPI_CTARn_ASC.
+#define BS_SPI_CTARn_ASC (4U) //!< Bit field size in bits for SPI_CTARn_ASC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_ASC field.
+#define BR_SPI_CTARn_ASC(x, n) (HW_SPI_CTARn(x, n).B.ASC)
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_ASC.
+#define BF_SPI_CTARn_ASC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_ASC), uint32_t) & BM_SPI_CTARn_ASC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ASC field to a new value.
+#define BW_SPI_CTARn_ASC(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_ASC) | BF_SPI_CTARn_ASC(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_CTARn, field CSSCK[15:12] (RW)
+ *
+ * Selects the scaler value for the PCS to SCK delay. This field is used only in
+ * master mode. The PCS to SCK Delay is the delay between the assertion of PCS
+ * and the first edge of the SCK. The delay is a multiple of the protocol clock
+ * period, and it is computed according to the following equation: t CSC = (1/fP )
+ * x PCSSCK x CSSCK. The following table lists the delay scaler values. Delay
+ * Scaler Encoding Field Value Delay Scaler Value 0000 2 0001 4 0010 8 0011 16 0100
+ * 32 0101 64 0110 128 0111 256 1000 512 1001 1024 1010 2048 1011 4096 1100 8192
+ * 1101 16384 1110 32768 1111 65536 Refer PCS to SCK Delay (tCSC ) for more
+ * details.
+ */
+//@{
+#define BP_SPI_CTARn_CSSCK (12U) //!< Bit position for SPI_CTARn_CSSCK.
+#define BM_SPI_CTARn_CSSCK (0x0000F000U) //!< Bit mask for SPI_CTARn_CSSCK.
+#define BS_SPI_CTARn_CSSCK (4U) //!< Bit field size in bits for SPI_CTARn_CSSCK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_CSSCK field.
+#define BR_SPI_CTARn_CSSCK(x, n) (HW_SPI_CTARn(x, n).B.CSSCK)
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_CSSCK.
+#define BF_SPI_CTARn_CSSCK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_CSSCK), uint32_t) & BM_SPI_CTARn_CSSCK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CSSCK field to a new value.
+#define BW_SPI_CTARn_CSSCK(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_CSSCK) | BF_SPI_CTARn_CSSCK(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_CTARn, field PBR[17:16] (RW)
+ *
+ * Selects the prescaler value for the baud rate. This field is used only in
+ * master mode. The baud rate is the frequency of the SCK. The protocol clock is
+ * divided by the prescaler value before the baud rate selection takes place. See
+ * the BR field description for details on how to compute the baud rate.
+ *
+ * Values:
+ * - 00 - Baud Rate Prescaler value is 2.
+ * - 01 - Baud Rate Prescaler value is 3.
+ * - 10 - Baud Rate Prescaler value is 5.
+ * - 11 - Baud Rate Prescaler value is 7.
+ */
+//@{
+#define BP_SPI_CTARn_PBR (16U) //!< Bit position for SPI_CTARn_PBR.
+#define BM_SPI_CTARn_PBR (0x00030000U) //!< Bit mask for SPI_CTARn_PBR.
+#define BS_SPI_CTARn_PBR (2U) //!< Bit field size in bits for SPI_CTARn_PBR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_PBR field.
+#define BR_SPI_CTARn_PBR(x, n) (HW_SPI_CTARn(x, n).B.PBR)
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_PBR.
+#define BF_SPI_CTARn_PBR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_PBR), uint32_t) & BM_SPI_CTARn_PBR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PBR field to a new value.
+#define BW_SPI_CTARn_PBR(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PBR) | BF_SPI_CTARn_PBR(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_CTARn, field PDT[19:18] (RW)
+ *
+ * Selects the prescaler value for the delay between the negation of the PCS
+ * signal at the end of a frame and the assertion of PCS at the beginning of the
+ * next frame. The PDT field is only used in master mode. See the DT field
+ * description for details on how to compute the Delay after Transfer. Refer Delay after
+ * Transfer (tDT ) for more details.
+ *
+ * Values:
+ * - 00 - Delay after Transfer Prescaler value is 1.
+ * - 01 - Delay after Transfer Prescaler value is 3.
+ * - 10 - Delay after Transfer Prescaler value is 5.
+ * - 11 - Delay after Transfer Prescaler value is 7.
+ */
+//@{
+#define BP_SPI_CTARn_PDT (18U) //!< Bit position for SPI_CTARn_PDT.
+#define BM_SPI_CTARn_PDT (0x000C0000U) //!< Bit mask for SPI_CTARn_PDT.
+#define BS_SPI_CTARn_PDT (2U) //!< Bit field size in bits for SPI_CTARn_PDT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_PDT field.
+#define BR_SPI_CTARn_PDT(x, n) (HW_SPI_CTARn(x, n).B.PDT)
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_PDT.
+#define BF_SPI_CTARn_PDT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_PDT), uint32_t) & BM_SPI_CTARn_PDT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PDT field to a new value.
+#define BW_SPI_CTARn_PDT(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PDT) | BF_SPI_CTARn_PDT(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_CTARn, field PASC[21:20] (RW)
+ *
+ * Selects the prescaler value for the delay between the last edge of SCK and
+ * the negation of PCS. See the ASC field description for information on how to
+ * compute the After SCK Delay. Refer After SCK Delay (tASC ) for more details.
+ *
+ * Values:
+ * - 00 - Delay after Transfer Prescaler value is 1.
+ * - 01 - Delay after Transfer Prescaler value is 3.
+ * - 10 - Delay after Transfer Prescaler value is 5.
+ * - 11 - Delay after Transfer Prescaler value is 7.
+ */
+//@{
+#define BP_SPI_CTARn_PASC (20U) //!< Bit position for SPI_CTARn_PASC.
+#define BM_SPI_CTARn_PASC (0x00300000U) //!< Bit mask for SPI_CTARn_PASC.
+#define BS_SPI_CTARn_PASC (2U) //!< Bit field size in bits for SPI_CTARn_PASC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_PASC field.
+#define BR_SPI_CTARn_PASC(x, n) (HW_SPI_CTARn(x, n).B.PASC)
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_PASC.
+#define BF_SPI_CTARn_PASC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_PASC), uint32_t) & BM_SPI_CTARn_PASC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PASC field to a new value.
+#define BW_SPI_CTARn_PASC(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PASC) | BF_SPI_CTARn_PASC(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_CTARn, field PCSSCK[23:22] (RW)
+ *
+ * Selects the prescaler value for the delay between assertion of PCS and the
+ * first edge of the SCK. See the CSSCK field description for information on how to
+ * compute the PCS to SCK Delay. Refer PCS to SCK Delay (tCSC ) for more details.
+ *
+ * Values:
+ * - 00 - PCS to SCK Prescaler value is 1.
+ * - 01 - PCS to SCK Prescaler value is 3.
+ * - 10 - PCS to SCK Prescaler value is 5.
+ * - 11 - PCS to SCK Prescaler value is 7.
+ */
+//@{
+#define BP_SPI_CTARn_PCSSCK (22U) //!< Bit position for SPI_CTARn_PCSSCK.
+#define BM_SPI_CTARn_PCSSCK (0x00C00000U) //!< Bit mask for SPI_CTARn_PCSSCK.
+#define BS_SPI_CTARn_PCSSCK (2U) //!< Bit field size in bits for SPI_CTARn_PCSSCK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_PCSSCK field.
+#define BR_SPI_CTARn_PCSSCK(x, n) (HW_SPI_CTARn(x, n).B.PCSSCK)
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_PCSSCK.
+#define BF_SPI_CTARn_PCSSCK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_PCSSCK), uint32_t) & BM_SPI_CTARn_PCSSCK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PCSSCK field to a new value.
+#define BW_SPI_CTARn_PCSSCK(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PCSSCK) | BF_SPI_CTARn_PCSSCK(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_CTARn, field LSBFE[24] (RW)
+ *
+ * Specifies whether the LSB or MSB of the frame is transferred first.
+ *
+ * Values:
+ * - 0 - Data is transferred MSB first.
+ * - 1 - Data is transferred LSB first.
+ */
+//@{
+#define BP_SPI_CTARn_LSBFE (24U) //!< Bit position for SPI_CTARn_LSBFE.
+#define BM_SPI_CTARn_LSBFE (0x01000000U) //!< Bit mask for SPI_CTARn_LSBFE.
+#define BS_SPI_CTARn_LSBFE (1U) //!< Bit field size in bits for SPI_CTARn_LSBFE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_LSBFE field.
+#define BR_SPI_CTARn_LSBFE(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_LSBFE))
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_LSBFE.
+#define BF_SPI_CTARn_LSBFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_LSBFE), uint32_t) & BM_SPI_CTARn_LSBFE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LSBFE field to a new value.
+#define BW_SPI_CTARn_LSBFE(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_LSBFE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_CTARn, field CPHA[25] (RW)
+ *
+ * Selects which edge of SCK causes data to change and which edge causes data to
+ * be captured. This bit is used in both master and slave mode. For successful
+ * communication between serial devices, the devices must have identical clock
+ * phase settings. In Continuous SCK mode, the bit value is ignored and the
+ * transfers are done as if the CPHA bit is set to 1.
+ *
+ * Values:
+ * - 0 - Data is captured on the leading edge of SCK and changed on the
+ * following edge.
+ * - 1 - Data is changed on the leading edge of SCK and captured on the
+ * following edge.
+ */
+//@{
+#define BP_SPI_CTARn_CPHA (25U) //!< Bit position for SPI_CTARn_CPHA.
+#define BM_SPI_CTARn_CPHA (0x02000000U) //!< Bit mask for SPI_CTARn_CPHA.
+#define BS_SPI_CTARn_CPHA (1U) //!< Bit field size in bits for SPI_CTARn_CPHA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_CPHA field.
+#define BR_SPI_CTARn_CPHA(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPHA))
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_CPHA.
+#define BF_SPI_CTARn_CPHA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_CPHA), uint32_t) & BM_SPI_CTARn_CPHA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CPHA field to a new value.
+#define BW_SPI_CTARn_CPHA(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPHA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_CTARn, field CPOL[26] (RW)
+ *
+ * Selects the inactive state of the Serial Communications Clock (SCK). This bit
+ * is used in both master and slave mode. For successful communication between
+ * serial devices, the devices must have identical clock polarities. When the
+ * Continuous Selection Format is selected, switching between clock polarities
+ * without stopping the module can cause errors in the transfer due to the peripheral
+ * device interpreting the switch of clock polarity as a valid clock edge. In case
+ * of continous sck mode, when the module goes in low power mode(disabled),
+ * inactive state of sck is not guaranted.
+ *
+ * Values:
+ * - 0 - The inactive state value of SCK is low.
+ * - 1 - The inactive state value of SCK is high.
+ */
+//@{
+#define BP_SPI_CTARn_CPOL (26U) //!< Bit position for SPI_CTARn_CPOL.
+#define BM_SPI_CTARn_CPOL (0x04000000U) //!< Bit mask for SPI_CTARn_CPOL.
+#define BS_SPI_CTARn_CPOL (1U) //!< Bit field size in bits for SPI_CTARn_CPOL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_CPOL field.
+#define BR_SPI_CTARn_CPOL(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPOL))
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_CPOL.
+#define BF_SPI_CTARn_CPOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_CPOL), uint32_t) & BM_SPI_CTARn_CPOL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CPOL field to a new value.
+#define BW_SPI_CTARn_CPOL(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPOL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_CTARn, field FMSZ[30:27] (RW)
+ *
+ * The number of bits transferred per frame is equal to the FMSZ value plus 1.
+ * Regardless of the transmission mode, the minimum valid frame size value is 4.
+ */
+//@{
+#define BP_SPI_CTARn_FMSZ (27U) //!< Bit position for SPI_CTARn_FMSZ.
+#define BM_SPI_CTARn_FMSZ (0x78000000U) //!< Bit mask for SPI_CTARn_FMSZ.
+#define BS_SPI_CTARn_FMSZ (4U) //!< Bit field size in bits for SPI_CTARn_FMSZ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_FMSZ field.
+#define BR_SPI_CTARn_FMSZ(x, n) (HW_SPI_CTARn(x, n).B.FMSZ)
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_FMSZ.
+#define BF_SPI_CTARn_FMSZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_FMSZ), uint32_t) & BM_SPI_CTARn_FMSZ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FMSZ field to a new value.
+#define BW_SPI_CTARn_FMSZ(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_FMSZ) | BF_SPI_CTARn_FMSZ(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_CTARn, field DBR[31] (RW)
+ *
+ * Doubles the effective baud rate of the Serial Communications Clock (SCK).
+ * This field is used only in master mode. It effectively halves the Baud Rate
+ * division ratio, supporting faster frequencies, and odd division ratios for the
+ * Serial Communications Clock (SCK). When the DBR bit is set, the duty cycle of the
+ * Serial Communications Clock (SCK) depends on the value in the Baud Rate
+ * Prescaler and the Clock Phase bit as listed in the following table. See the BR field
+ * description for details on how to compute the baud rate. SPI SCK Duty Cycle
+ * DBR CPHA PBR SCK Duty Cycle 0 any any 50/50 1 0 00 50/50 1 0 01 33/66 1 0 10
+ * 40/60 1 0 11 43/57 1 1 00 50/50 1 1 01 66/33 1 1 10 60/40 1 1 11 57/43
+ *
+ * Values:
+ * - 0 - The baud rate is computed normally with a 50/50 duty cycle.
+ * - 1 - The baud rate is doubled with the duty cycle depending on the Baud Rate
+ * Prescaler.
+ */
+//@{
+#define BP_SPI_CTARn_DBR (31U) //!< Bit position for SPI_CTARn_DBR.
+#define BM_SPI_CTARn_DBR (0x80000000U) //!< Bit mask for SPI_CTARn_DBR.
+#define BS_SPI_CTARn_DBR (1U) //!< Bit field size in bits for SPI_CTARn_DBR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_DBR field.
+#define BR_SPI_CTARn_DBR(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_DBR))
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_DBR.
+#define BF_SPI_CTARn_DBR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_DBR), uint32_t) & BM_SPI_CTARn_DBR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DBR field to a new value.
+#define BW_SPI_CTARn_DBR(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_DBR) = (v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) (RW)
+ *
+ * Reset value: 0x78000000U
+ *
+ * When the module is configured as an SPI bus slave, the CTAR0 register is used.
+ */
+typedef union _hw_spi_ctarn_slave
+{
+ uint32_t U;
+ struct _hw_spi_ctarn_slave_bitfields
+ {
+ uint32_t RESERVED0 : 25; //!< [24:0]
+ uint32_t CPHA : 1; //!< [25] Clock Phase
+ uint32_t CPOL : 1; //!< [26] Clock Polarity
+ uint32_t FMSZ : 5; //!< [31:27] Frame Size
+ } B;
+} hw_spi_ctarn_slave_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SPI_CTARn_SLAVE register
+ */
+//@{
+#define HW_SPI_CTARn_SLAVE_COUNT (1U)
+
+#define HW_SPI_CTARn_SLAVE_ADDR(x, n) (REGS_SPI_BASE(x) + 0xCU + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SPI_CTARn_SLAVE(x, n) (*(__IO hw_spi_ctarn_slave_t *) HW_SPI_CTARn_SLAVE_ADDR(x, n))
+#define HW_SPI_CTARn_SLAVE_RD(x, n) (HW_SPI_CTARn_SLAVE(x, n).U)
+#define HW_SPI_CTARn_SLAVE_WR(x, n, v) (HW_SPI_CTARn_SLAVE(x, n).U = (v))
+#define HW_SPI_CTARn_SLAVE_SET(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) | (v)))
+#define HW_SPI_CTARn_SLAVE_CLR(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) & ~(v)))
+#define HW_SPI_CTARn_SLAVE_TOG(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SPI_CTARn_SLAVE bitfields
+ */
+
+/*!
+ * @name Register SPI_CTARn_SLAVE, field CPHA[25] (RW)
+ *
+ * Selects which edge of SCK causes data to change and which edge causes data to
+ * be captured. This bit is used in both master and slave mode. For successful
+ * communication between serial devices, the devices must have identical clock
+ * phase settings. In Continuous SCK mode, the bit value is ignored and the
+ * transfers are done as if the CPHA bit is set to 1.
+ *
+ * Values:
+ * - 0 - Data is captured on the leading edge of SCK and changed on the
+ * following edge.
+ * - 1 - Data is changed on the leading edge of SCK and captured on the
+ * following edge.
+ */
+//@{
+#define BP_SPI_CTARn_SLAVE_CPHA (25U) //!< Bit position for SPI_CTARn_SLAVE_CPHA.
+#define BM_SPI_CTARn_SLAVE_CPHA (0x02000000U) //!< Bit mask for SPI_CTARn_SLAVE_CPHA.
+#define BS_SPI_CTARn_SLAVE_CPHA (1U) //!< Bit field size in bits for SPI_CTARn_SLAVE_CPHA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_SLAVE_CPHA field.
+#define BR_SPI_CTARn_SLAVE_CPHA(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPHA))
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_SLAVE_CPHA.
+#define BF_SPI_CTARn_SLAVE_CPHA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_SLAVE_CPHA), uint32_t) & BM_SPI_CTARn_SLAVE_CPHA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CPHA field to a new value.
+#define BW_SPI_CTARn_SLAVE_CPHA(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPHA) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_CTARn_SLAVE, field CPOL[26] (RW)
+ *
+ * Selects the inactive state of the Serial Communications Clock (SCK). In case
+ * of continous sck mode, when the module goes in low power mode(disabled),
+ * inactive state of sck is not guaranted.
+ *
+ * Values:
+ * - 0 - The inactive state value of SCK is low.
+ * - 1 - The inactive state value of SCK is high.
+ */
+//@{
+#define BP_SPI_CTARn_SLAVE_CPOL (26U) //!< Bit position for SPI_CTARn_SLAVE_CPOL.
+#define BM_SPI_CTARn_SLAVE_CPOL (0x04000000U) //!< Bit mask for SPI_CTARn_SLAVE_CPOL.
+#define BS_SPI_CTARn_SLAVE_CPOL (1U) //!< Bit field size in bits for SPI_CTARn_SLAVE_CPOL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_SLAVE_CPOL field.
+#define BR_SPI_CTARn_SLAVE_CPOL(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPOL))
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_SLAVE_CPOL.
+#define BF_SPI_CTARn_SLAVE_CPOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_SLAVE_CPOL), uint32_t) & BM_SPI_CTARn_SLAVE_CPOL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CPOL field to a new value.
+#define BW_SPI_CTARn_SLAVE_CPOL(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPOL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_CTARn_SLAVE, field FMSZ[31:27] (RW)
+ *
+ * The number of bits transfered per frame is equal to the FMSZ field value plus
+ * 1. Note that the minimum valid value of frame size is 4.
+ */
+//@{
+#define BP_SPI_CTARn_SLAVE_FMSZ (27U) //!< Bit position for SPI_CTARn_SLAVE_FMSZ.
+#define BM_SPI_CTARn_SLAVE_FMSZ (0xF8000000U) //!< Bit mask for SPI_CTARn_SLAVE_FMSZ.
+#define BS_SPI_CTARn_SLAVE_FMSZ (5U) //!< Bit field size in bits for SPI_CTARn_SLAVE_FMSZ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_CTARn_SLAVE_FMSZ field.
+#define BR_SPI_CTARn_SLAVE_FMSZ(x, n) (HW_SPI_CTARn_SLAVE(x, n).B.FMSZ)
+#endif
+
+//! @brief Format value for bitfield SPI_CTARn_SLAVE_FMSZ.
+#define BF_SPI_CTARn_SLAVE_FMSZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_CTARn_SLAVE_FMSZ), uint32_t) & BM_SPI_CTARn_SLAVE_FMSZ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FMSZ field to a new value.
+#define BW_SPI_CTARn_SLAVE_FMSZ(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, (HW_SPI_CTARn_SLAVE_RD(x, n) & ~BM_SPI_CTARn_SLAVE_FMSZ) | BF_SPI_CTARn_SLAVE_FMSZ(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SPI_SR - Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SPI_SR - Status Register (RW)
+ *
+ * Reset value: 0x02000000U
+ *
+ * SR contains status and flag bits. The bits reflect the status of the module
+ * and indicate the occurrence of events that can generate interrupt or DMA
+ * requests. Software can clear flag bits in the SR by writing a 1 to them. Writing a 0
+ * to a flag bit has no effect. This register may not be writable in Module
+ * Disable mode due to the use of power saving mechanisms.
+ */
+typedef union _hw_spi_sr
+{
+ uint32_t U;
+ struct _hw_spi_sr_bitfields
+ {
+ uint32_t POPNXTPTR : 4; //!< [3:0] Pop Next Pointer
+ uint32_t RXCTR : 4; //!< [7:4] RX FIFO Counter
+ uint32_t TXNXTPTR : 4; //!< [11:8] Transmit Next Pointer
+ uint32_t TXCTR : 4; //!< [15:12] TX FIFO Counter
+ uint32_t RESERVED0 : 1; //!< [16]
+ uint32_t RFDF : 1; //!< [17] Receive FIFO Drain Flag
+ uint32_t RESERVED1 : 1; //!< [18]
+ uint32_t RFOF : 1; //!< [19] Receive FIFO Overflow Flag
+ uint32_t RESERVED2 : 5; //!< [24:20]
+ uint32_t TFFF : 1; //!< [25] Transmit FIFO Fill Flag
+ uint32_t RESERVED3 : 1; //!< [26]
+ uint32_t TFUF : 1; //!< [27] Transmit FIFO Underflow Flag
+ uint32_t EOQF : 1; //!< [28] End of Queue Flag
+ uint32_t RESERVED4 : 1; //!< [29]
+ uint32_t TXRXS : 1; //!< [30] TX and RX Status
+ uint32_t TCF : 1; //!< [31] Transfer Complete Flag
+ } B;
+} hw_spi_sr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SPI_SR register
+ */
+//@{
+#define HW_SPI_SR_ADDR(x) (REGS_SPI_BASE(x) + 0x2CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SPI_SR(x) (*(__IO hw_spi_sr_t *) HW_SPI_SR_ADDR(x))
+#define HW_SPI_SR_RD(x) (HW_SPI_SR(x).U)
+#define HW_SPI_SR_WR(x, v) (HW_SPI_SR(x).U = (v))
+#define HW_SPI_SR_SET(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) | (v)))
+#define HW_SPI_SR_CLR(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) & ~(v)))
+#define HW_SPI_SR_TOG(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SPI_SR bitfields
+ */
+
+/*!
+ * @name Register SPI_SR, field POPNXTPTR[3:0] (RO)
+ *
+ * Contains a pointer to the RX FIFO entry to be returned when the POPR is read.
+ * The POPNXTPTR is updated when the POPR is read.
+ */
+//@{
+#define BP_SPI_SR_POPNXTPTR (0U) //!< Bit position for SPI_SR_POPNXTPTR.
+#define BM_SPI_SR_POPNXTPTR (0x0000000FU) //!< Bit mask for SPI_SR_POPNXTPTR.
+#define BS_SPI_SR_POPNXTPTR (4U) //!< Bit field size in bits for SPI_SR_POPNXTPTR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_SR_POPNXTPTR field.
+#define BR_SPI_SR_POPNXTPTR(x) (HW_SPI_SR(x).B.POPNXTPTR)
+#endif
+//@}
+
+/*!
+ * @name Register SPI_SR, field RXCTR[7:4] (RO)
+ *
+ * Indicates the number of entries in the RX FIFO. The RXCTR is decremented
+ * every time the POPR is read. The RXCTR is incremented every time data is
+ * transferred from the shift register to the RX FIFO.
+ */
+//@{
+#define BP_SPI_SR_RXCTR (4U) //!< Bit position for SPI_SR_RXCTR.
+#define BM_SPI_SR_RXCTR (0x000000F0U) //!< Bit mask for SPI_SR_RXCTR.
+#define BS_SPI_SR_RXCTR (4U) //!< Bit field size in bits for SPI_SR_RXCTR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_SR_RXCTR field.
+#define BR_SPI_SR_RXCTR(x) (HW_SPI_SR(x).B.RXCTR)
+#endif
+//@}
+
+/*!
+ * @name Register SPI_SR, field TXNXTPTR[11:8] (RO)
+ *
+ * Indicates which TX FIFO entry is transmitted during the next transfer. The
+ * TXNXTPTR field is updated every time SPI data is transferred from the TX FIFO to
+ * the shift register.
+ */
+//@{
+#define BP_SPI_SR_TXNXTPTR (8U) //!< Bit position for SPI_SR_TXNXTPTR.
+#define BM_SPI_SR_TXNXTPTR (0x00000F00U) //!< Bit mask for SPI_SR_TXNXTPTR.
+#define BS_SPI_SR_TXNXTPTR (4U) //!< Bit field size in bits for SPI_SR_TXNXTPTR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_SR_TXNXTPTR field.
+#define BR_SPI_SR_TXNXTPTR(x) (HW_SPI_SR(x).B.TXNXTPTR)
+#endif
+//@}
+
+/*!
+ * @name Register SPI_SR, field TXCTR[15:12] (RO)
+ *
+ * Indicates the number of valid entries in the TX FIFO. The TXCTR is
+ * incremented every time the PUSHR is written. The TXCTR is decremented every time an SPI
+ * command is executed and the SPI data is transferred to the shift register.
+ */
+//@{
+#define BP_SPI_SR_TXCTR (12U) //!< Bit position for SPI_SR_TXCTR.
+#define BM_SPI_SR_TXCTR (0x0000F000U) //!< Bit mask for SPI_SR_TXCTR.
+#define BS_SPI_SR_TXCTR (4U) //!< Bit field size in bits for SPI_SR_TXCTR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_SR_TXCTR field.
+#define BR_SPI_SR_TXCTR(x) (HW_SPI_SR(x).B.TXCTR)
+#endif
+//@}
+
+/*!
+ * @name Register SPI_SR, field RFDF[17] (W1C)
+ *
+ * Provides a method for the module to request that entries be removed from the
+ * RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be
+ * cleared by writing 1 to it or by acknowledgement from the DMA controller when
+ * the RX FIFO is empty.
+ *
+ * Values:
+ * - 0 - RX FIFO is empty.
+ * - 1 - RX FIFO is not empty.
+ */
+//@{
+#define BP_SPI_SR_RFDF (17U) //!< Bit position for SPI_SR_RFDF.
+#define BM_SPI_SR_RFDF (0x00020000U) //!< Bit mask for SPI_SR_RFDF.
+#define BS_SPI_SR_RFDF (1U) //!< Bit field size in bits for SPI_SR_RFDF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_SR_RFDF field.
+#define BR_SPI_SR_RFDF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFDF))
+#endif
+
+//! @brief Format value for bitfield SPI_SR_RFDF.
+#define BF_SPI_SR_RFDF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_RFDF), uint32_t) & BM_SPI_SR_RFDF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RFDF field to a new value.
+#define BW_SPI_SR_RFDF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFDF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_SR, field RFOF[19] (W1C)
+ *
+ * Indicates an overflow condition in the RX FIFO. The field is set when the RX
+ * FIFO and shift register are full and a transfer is initiated. The bit remains
+ * set until it is cleared by writing a 1 to it.
+ *
+ * Values:
+ * - 0 - No Rx FIFO overflow.
+ * - 1 - Rx FIFO overflow has occurred.
+ */
+//@{
+#define BP_SPI_SR_RFOF (19U) //!< Bit position for SPI_SR_RFOF.
+#define BM_SPI_SR_RFOF (0x00080000U) //!< Bit mask for SPI_SR_RFOF.
+#define BS_SPI_SR_RFOF (1U) //!< Bit field size in bits for SPI_SR_RFOF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_SR_RFOF field.
+#define BR_SPI_SR_RFOF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFOF))
+#endif
+
+//! @brief Format value for bitfield SPI_SR_RFOF.
+#define BF_SPI_SR_RFOF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_RFOF), uint32_t) & BM_SPI_SR_RFOF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RFOF field to a new value.
+#define BW_SPI_SR_RFOF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFOF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_SR, field TFFF[25] (W1C)
+ *
+ * Provides a method for the module to request more entries to be added to the
+ * TX FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be
+ * cleared by writing 1 to it or by acknowledgement from the DMA controller to
+ * the TX FIFO full request.
+ *
+ * Values:
+ * - 0 - TX FIFO is full.
+ * - 1 - TX FIFO is not full.
+ */
+//@{
+#define BP_SPI_SR_TFFF (25U) //!< Bit position for SPI_SR_TFFF.
+#define BM_SPI_SR_TFFF (0x02000000U) //!< Bit mask for SPI_SR_TFFF.
+#define BS_SPI_SR_TFFF (1U) //!< Bit field size in bits for SPI_SR_TFFF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_SR_TFFF field.
+#define BR_SPI_SR_TFFF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFFF))
+#endif
+
+//! @brief Format value for bitfield SPI_SR_TFFF.
+#define BF_SPI_SR_TFFF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_TFFF), uint32_t) & BM_SPI_SR_TFFF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TFFF field to a new value.
+#define BW_SPI_SR_TFFF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFFF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_SR, field TFUF[27] (W1C)
+ *
+ * Indicates an underflow condition in the TX FIFO. The transmit underflow
+ * condition is detected only for SPI blocks operating in Slave mode and SPI
+ * configuration. TFUF is set when the TX FIFO of the module operating in SPI Slave mode
+ * is empty and an external SPI master initiates a transfer. The TFUF bit remains
+ * set until cleared by writing 1 to it.
+ *
+ * Values:
+ * - 0 - No TX FIFO underflow.
+ * - 1 - TX FIFO underflow has occurred.
+ */
+//@{
+#define BP_SPI_SR_TFUF (27U) //!< Bit position for SPI_SR_TFUF.
+#define BM_SPI_SR_TFUF (0x08000000U) //!< Bit mask for SPI_SR_TFUF.
+#define BS_SPI_SR_TFUF (1U) //!< Bit field size in bits for SPI_SR_TFUF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_SR_TFUF field.
+#define BR_SPI_SR_TFUF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFUF))
+#endif
+
+//! @brief Format value for bitfield SPI_SR_TFUF.
+#define BF_SPI_SR_TFUF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_TFUF), uint32_t) & BM_SPI_SR_TFUF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TFUF field to a new value.
+#define BW_SPI_SR_TFUF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFUF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_SR, field EOQF[28] (W1C)
+ *
+ * Indicates that the last entry in a queue has been transmitted when the module
+ * is in Master mode. The EOQF bit is set when the TX FIFO entry has the EOQ bit
+ * set in the command halfword and the end of the transfer is reached. The EOQF
+ * bit remains set until cleared by writing a 1 to it. When the EOQF bit is set,
+ * the TXRXS bit is automatically cleared.
+ *
+ * Values:
+ * - 0 - EOQ is not set in the executing command.
+ * - 1 - EOQ is set in the executing SPI command.
+ */
+//@{
+#define BP_SPI_SR_EOQF (28U) //!< Bit position for SPI_SR_EOQF.
+#define BM_SPI_SR_EOQF (0x10000000U) //!< Bit mask for SPI_SR_EOQF.
+#define BS_SPI_SR_EOQF (1U) //!< Bit field size in bits for SPI_SR_EOQF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_SR_EOQF field.
+#define BR_SPI_SR_EOQF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_EOQF))
+#endif
+
+//! @brief Format value for bitfield SPI_SR_EOQF.
+#define BF_SPI_SR_EOQF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_EOQF), uint32_t) & BM_SPI_SR_EOQF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EOQF field to a new value.
+#define BW_SPI_SR_EOQF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_EOQF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_SR, field TXRXS[30] (W1C)
+ *
+ * Reflects the run status of the module.
+ *
+ * Values:
+ * - 0 - Transmit and receive operations are disabled (The module is in Stopped
+ * state).
+ * - 1 - Transmit and receive operations are enabled (The module is in Running
+ * state).
+ */
+//@{
+#define BP_SPI_SR_TXRXS (30U) //!< Bit position for SPI_SR_TXRXS.
+#define BM_SPI_SR_TXRXS (0x40000000U) //!< Bit mask for SPI_SR_TXRXS.
+#define BS_SPI_SR_TXRXS (1U) //!< Bit field size in bits for SPI_SR_TXRXS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_SR_TXRXS field.
+#define BR_SPI_SR_TXRXS(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TXRXS))
+#endif
+
+//! @brief Format value for bitfield SPI_SR_TXRXS.
+#define BF_SPI_SR_TXRXS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_TXRXS), uint32_t) & BM_SPI_SR_TXRXS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXRXS field to a new value.
+#define BW_SPI_SR_TXRXS(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TXRXS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_SR, field TCF[31] (W1C)
+ *
+ * Indicates that all bits in a frame have been shifted out. TCF remains set
+ * until it is cleared by writing a 1 to it.
+ *
+ * Values:
+ * - 0 - Transfer not complete.
+ * - 1 - Transfer complete.
+ */
+//@{
+#define BP_SPI_SR_TCF (31U) //!< Bit position for SPI_SR_TCF.
+#define BM_SPI_SR_TCF (0x80000000U) //!< Bit mask for SPI_SR_TCF.
+#define BS_SPI_SR_TCF (1U) //!< Bit field size in bits for SPI_SR_TCF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_SR_TCF field.
+#define BR_SPI_SR_TCF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TCF))
+#endif
+
+//! @brief Format value for bitfield SPI_SR_TCF.
+#define BF_SPI_SR_TCF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_SR_TCF), uint32_t) & BM_SPI_SR_TCF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCF field to a new value.
+#define BW_SPI_SR_TCF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TCF) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RSER controls DMA and interrupt requests. Do not write to the RSER while the
+ * module is in the Running state.
+ */
+typedef union _hw_spi_rser
+{
+ uint32_t U;
+ struct _hw_spi_rser_bitfields
+ {
+ uint32_t RESERVED0 : 16; //!< [15:0]
+ uint32_t RFDF_DIRS : 1; //!< [16] Receive FIFO Drain DMA or Interrupt
+ //! Request Select
+ uint32_t RFDF_RE : 1; //!< [17] Receive FIFO Drain Request Enable
+ uint32_t RESERVED1 : 1; //!< [18]
+ uint32_t RFOF_RE : 1; //!< [19] Receive FIFO Overflow Request Enable
+ uint32_t RESERVED2 : 4; //!< [23:20]
+ uint32_t TFFF_DIRS : 1; //!< [24] Transmit FIFO Fill DMA or Interrupt
+ //! Request Select
+ uint32_t TFFF_RE : 1; //!< [25] Transmit FIFO Fill Request Enable
+ uint32_t RESERVED3 : 1; //!< [26]
+ uint32_t TFUF_RE : 1; //!< [27] Transmit FIFO Underflow Request Enable
+ uint32_t EOQF_RE : 1; //!< [28] Finished Request Enable
+ uint32_t RESERVED4 : 2; //!< [30:29]
+ uint32_t TCF_RE : 1; //!< [31] Transmission Complete Request Enable
+ } B;
+} hw_spi_rser_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SPI_RSER register
+ */
+//@{
+#define HW_SPI_RSER_ADDR(x) (REGS_SPI_BASE(x) + 0x30U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SPI_RSER(x) (*(__IO hw_spi_rser_t *) HW_SPI_RSER_ADDR(x))
+#define HW_SPI_RSER_RD(x) (HW_SPI_RSER(x).U)
+#define HW_SPI_RSER_WR(x, v) (HW_SPI_RSER(x).U = (v))
+#define HW_SPI_RSER_SET(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) | (v)))
+#define HW_SPI_RSER_CLR(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) & ~(v)))
+#define HW_SPI_RSER_TOG(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SPI_RSER bitfields
+ */
+
+/*!
+ * @name Register SPI_RSER, field RFDF_DIRS[16] (RW)
+ *
+ * Selects between generating a DMA request or an interrupt request. When the
+ * RFDF flag bit in the SR is set, and the RFDF_RE bit in the RSER is set, the
+ * RFDF_DIRS bit selects between generating an interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0 - Interrupt request.
+ * - 1 - DMA request.
+ */
+//@{
+#define BP_SPI_RSER_RFDF_DIRS (16U) //!< Bit position for SPI_RSER_RFDF_DIRS.
+#define BM_SPI_RSER_RFDF_DIRS (0x00010000U) //!< Bit mask for SPI_RSER_RFDF_DIRS.
+#define BS_SPI_RSER_RFDF_DIRS (1U) //!< Bit field size in bits for SPI_RSER_RFDF_DIRS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_RSER_RFDF_DIRS field.
+#define BR_SPI_RSER_RFDF_DIRS(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_DIRS))
+#endif
+
+//! @brief Format value for bitfield SPI_RSER_RFDF_DIRS.
+#define BF_SPI_RSER_RFDF_DIRS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_RFDF_DIRS), uint32_t) & BM_SPI_RSER_RFDF_DIRS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RFDF_DIRS field to a new value.
+#define BW_SPI_RSER_RFDF_DIRS(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_DIRS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_RSER, field RFDF_RE[17] (RW)
+ *
+ * Enables the RFDF flag in the SR to generate a request. The RFDF_DIRS bit
+ * selects between generating an interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0 - RFDF interrupt or DMA requests are disabled.
+ * - 1 - RFDF interrupt or DMA requests are enabled.
+ */
+//@{
+#define BP_SPI_RSER_RFDF_RE (17U) //!< Bit position for SPI_RSER_RFDF_RE.
+#define BM_SPI_RSER_RFDF_RE (0x00020000U) //!< Bit mask for SPI_RSER_RFDF_RE.
+#define BS_SPI_RSER_RFDF_RE (1U) //!< Bit field size in bits for SPI_RSER_RFDF_RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_RSER_RFDF_RE field.
+#define BR_SPI_RSER_RFDF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_RE))
+#endif
+
+//! @brief Format value for bitfield SPI_RSER_RFDF_RE.
+#define BF_SPI_RSER_RFDF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_RFDF_RE), uint32_t) & BM_SPI_RSER_RFDF_RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RFDF_RE field to a new value.
+#define BW_SPI_RSER_RFDF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_RE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_RSER, field RFOF_RE[19] (RW)
+ *
+ * Enables the RFOF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0 - RFOF interrupt requests are disabled.
+ * - 1 - RFOF interrupt requests are enabled.
+ */
+//@{
+#define BP_SPI_RSER_RFOF_RE (19U) //!< Bit position for SPI_RSER_RFOF_RE.
+#define BM_SPI_RSER_RFOF_RE (0x00080000U) //!< Bit mask for SPI_RSER_RFOF_RE.
+#define BS_SPI_RSER_RFOF_RE (1U) //!< Bit field size in bits for SPI_RSER_RFOF_RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_RSER_RFOF_RE field.
+#define BR_SPI_RSER_RFOF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFOF_RE))
+#endif
+
+//! @brief Format value for bitfield SPI_RSER_RFOF_RE.
+#define BF_SPI_RSER_RFOF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_RFOF_RE), uint32_t) & BM_SPI_RSER_RFOF_RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RFOF_RE field to a new value.
+#define BW_SPI_RSER_RFOF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFOF_RE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_RSER, field TFFF_DIRS[24] (RW)
+ *
+ * Selects between generating a DMA request or an interrupt request. When
+ * SR[TFFF] and RSER[TFFF_RE] are set, this field selects between generating an
+ * interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0 - TFFF flag generates interrupt requests.
+ * - 1 - TFFF flag generates DMA requests.
+ */
+//@{
+#define BP_SPI_RSER_TFFF_DIRS (24U) //!< Bit position for SPI_RSER_TFFF_DIRS.
+#define BM_SPI_RSER_TFFF_DIRS (0x01000000U) //!< Bit mask for SPI_RSER_TFFF_DIRS.
+#define BS_SPI_RSER_TFFF_DIRS (1U) //!< Bit field size in bits for SPI_RSER_TFFF_DIRS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_RSER_TFFF_DIRS field.
+#define BR_SPI_RSER_TFFF_DIRS(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_DIRS))
+#endif
+
+//! @brief Format value for bitfield SPI_RSER_TFFF_DIRS.
+#define BF_SPI_RSER_TFFF_DIRS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_TFFF_DIRS), uint32_t) & BM_SPI_RSER_TFFF_DIRS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TFFF_DIRS field to a new value.
+#define BW_SPI_RSER_TFFF_DIRS(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_DIRS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_RSER, field TFFF_RE[25] (RW)
+ *
+ * Enables the TFFF flag in the SR to generate a request. The TFFF_DIRS bit
+ * selects between generating an interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0 - TFFF interrupts or DMA requests are disabled.
+ * - 1 - TFFF interrupts or DMA requests are enabled.
+ */
+//@{
+#define BP_SPI_RSER_TFFF_RE (25U) //!< Bit position for SPI_RSER_TFFF_RE.
+#define BM_SPI_RSER_TFFF_RE (0x02000000U) //!< Bit mask for SPI_RSER_TFFF_RE.
+#define BS_SPI_RSER_TFFF_RE (1U) //!< Bit field size in bits for SPI_RSER_TFFF_RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_RSER_TFFF_RE field.
+#define BR_SPI_RSER_TFFF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_RE))
+#endif
+
+//! @brief Format value for bitfield SPI_RSER_TFFF_RE.
+#define BF_SPI_RSER_TFFF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_TFFF_RE), uint32_t) & BM_SPI_RSER_TFFF_RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TFFF_RE field to a new value.
+#define BW_SPI_RSER_TFFF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_RE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_RSER, field TFUF_RE[27] (RW)
+ *
+ * Enables the TFUF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0 - TFUF interrupt requests are disabled.
+ * - 1 - TFUF interrupt requests are enabled.
+ */
+//@{
+#define BP_SPI_RSER_TFUF_RE (27U) //!< Bit position for SPI_RSER_TFUF_RE.
+#define BM_SPI_RSER_TFUF_RE (0x08000000U) //!< Bit mask for SPI_RSER_TFUF_RE.
+#define BS_SPI_RSER_TFUF_RE (1U) //!< Bit field size in bits for SPI_RSER_TFUF_RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_RSER_TFUF_RE field.
+#define BR_SPI_RSER_TFUF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFUF_RE))
+#endif
+
+//! @brief Format value for bitfield SPI_RSER_TFUF_RE.
+#define BF_SPI_RSER_TFUF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_TFUF_RE), uint32_t) & BM_SPI_RSER_TFUF_RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TFUF_RE field to a new value.
+#define BW_SPI_RSER_TFUF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFUF_RE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_RSER, field EOQF_RE[28] (RW)
+ *
+ * Enables the EOQF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0 - EOQF interrupt requests are disabled.
+ * - 1 - EOQF interrupt requests are enabled.
+ */
+//@{
+#define BP_SPI_RSER_EOQF_RE (28U) //!< Bit position for SPI_RSER_EOQF_RE.
+#define BM_SPI_RSER_EOQF_RE (0x10000000U) //!< Bit mask for SPI_RSER_EOQF_RE.
+#define BS_SPI_RSER_EOQF_RE (1U) //!< Bit field size in bits for SPI_RSER_EOQF_RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_RSER_EOQF_RE field.
+#define BR_SPI_RSER_EOQF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_EOQF_RE))
+#endif
+
+//! @brief Format value for bitfield SPI_RSER_EOQF_RE.
+#define BF_SPI_RSER_EOQF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_EOQF_RE), uint32_t) & BM_SPI_RSER_EOQF_RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EOQF_RE field to a new value.
+#define BW_SPI_RSER_EOQF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_EOQF_RE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_RSER, field TCF_RE[31] (RW)
+ *
+ * Enables TCF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0 - TCF interrupt requests are disabled.
+ * - 1 - TCF interrupt requests are enabled.
+ */
+//@{
+#define BP_SPI_RSER_TCF_RE (31U) //!< Bit position for SPI_RSER_TCF_RE.
+#define BM_SPI_RSER_TCF_RE (0x80000000U) //!< Bit mask for SPI_RSER_TCF_RE.
+#define BS_SPI_RSER_TCF_RE (1U) //!< Bit field size in bits for SPI_RSER_TCF_RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_RSER_TCF_RE field.
+#define BR_SPI_RSER_TCF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TCF_RE))
+#endif
+
+//! @brief Format value for bitfield SPI_RSER_TCF_RE.
+#define BF_SPI_RSER_TCF_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_RSER_TCF_RE), uint32_t) & BM_SPI_RSER_TCF_RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCF_RE field to a new value.
+#define BW_SPI_RSER_TCF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TCF_RE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
+ * transfers all 32 bits to the TX FIFO. In Master mode, the register transfers
+ * 16 bits of data and 16 bits of command information. In Slave mode, all 32 bits
+ * can be used as data, supporting up to 32-bit frame operation. A read access
+ * of PUSHR returns the topmost TX FIFO entry. When the module is disabled,
+ * writing to this register does not update the FIFO. Therefore, any reads performed
+ * while the module is disabled return the last PUSHR write performed while the
+ * module was still enabled.
+ */
+typedef union _hw_spi_pushr
+{
+ uint32_t U;
+ struct _hw_spi_pushr_bitfields
+ {
+ uint32_t TXDATA : 16; //!< [15:0] Transmit Data
+ uint32_t PCS : 6; //!< [21:16]
+ uint32_t RESERVED0 : 4; //!< [25:22]
+ uint32_t CTCNT : 1; //!< [26] Clear Transfer Counter
+ uint32_t EOQ : 1; //!< [27] End Of Queue
+ uint32_t CTAS : 3; //!< [30:28] Clock and Transfer Attributes Select
+ uint32_t CONT : 1; //!< [31] Continuous Peripheral Chip Select Enable
+ } B;
+} hw_spi_pushr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SPI_PUSHR register
+ */
+//@{
+#define HW_SPI_PUSHR_ADDR(x) (REGS_SPI_BASE(x) + 0x34U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SPI_PUSHR(x) (*(__IO hw_spi_pushr_t *) HW_SPI_PUSHR_ADDR(x))
+#define HW_SPI_PUSHR_RD(x) (HW_SPI_PUSHR(x).U)
+#define HW_SPI_PUSHR_WR(x, v) (HW_SPI_PUSHR(x).U = (v))
+#define HW_SPI_PUSHR_SET(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) | (v)))
+#define HW_SPI_PUSHR_CLR(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) & ~(v)))
+#define HW_SPI_PUSHR_TOG(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SPI_PUSHR bitfields
+ */
+
+/*!
+ * @name Register SPI_PUSHR, field TXDATA[15:0] (RW)
+ *
+ * Holds SPI data to be transferred according to the associated SPI command.
+ */
+//@{
+#define BP_SPI_PUSHR_TXDATA (0U) //!< Bit position for SPI_PUSHR_TXDATA.
+#define BM_SPI_PUSHR_TXDATA (0x0000FFFFU) //!< Bit mask for SPI_PUSHR_TXDATA.
+#define BS_SPI_PUSHR_TXDATA (16U) //!< Bit field size in bits for SPI_PUSHR_TXDATA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_PUSHR_TXDATA field.
+#define BR_SPI_PUSHR_TXDATA(x) (HW_SPI_PUSHR(x).B.TXDATA)
+#endif
+
+//! @brief Format value for bitfield SPI_PUSHR_TXDATA.
+#define BF_SPI_PUSHR_TXDATA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_TXDATA), uint32_t) & BM_SPI_PUSHR_TXDATA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXDATA field to a new value.
+#define BW_SPI_PUSHR_TXDATA(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_TXDATA) | BF_SPI_PUSHR_TXDATA(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_PUSHR, field PCS[21:16] (RW)
+ *
+ * Select which PCS signals are to be asserted for the transfer. Refer to the
+ * chip configuration details for the number of PCS signals used in this MCU.
+ *
+ * Values:
+ * - 0 - Negate the PCS[x] signal.
+ * - 1 - Assert the PCS[x] signal.
+ */
+//@{
+#define BP_SPI_PUSHR_PCS (16U) //!< Bit position for SPI_PUSHR_PCS.
+#define BM_SPI_PUSHR_PCS (0x003F0000U) //!< Bit mask for SPI_PUSHR_PCS.
+#define BS_SPI_PUSHR_PCS (6U) //!< Bit field size in bits for SPI_PUSHR_PCS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_PUSHR_PCS field.
+#define BR_SPI_PUSHR_PCS(x) (HW_SPI_PUSHR(x).B.PCS)
+#endif
+
+//! @brief Format value for bitfield SPI_PUSHR_PCS.
+#define BF_SPI_PUSHR_PCS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_PCS), uint32_t) & BM_SPI_PUSHR_PCS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PCS field to a new value.
+#define BW_SPI_PUSHR_PCS(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_PCS) | BF_SPI_PUSHR_PCS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_PUSHR, field CTCNT[26] (RW)
+ *
+ * Clears the TCNT field in the TCR register. The TCNT field is cleared before
+ * the module starts transmitting the current SPI frame.
+ *
+ * Values:
+ * - 0 - Do not clear the TCR[TCNT] field.
+ * - 1 - Clear the TCR[TCNT] field.
+ */
+//@{
+#define BP_SPI_PUSHR_CTCNT (26U) //!< Bit position for SPI_PUSHR_CTCNT.
+#define BM_SPI_PUSHR_CTCNT (0x04000000U) //!< Bit mask for SPI_PUSHR_CTCNT.
+#define BS_SPI_PUSHR_CTCNT (1U) //!< Bit field size in bits for SPI_PUSHR_CTCNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_PUSHR_CTCNT field.
+#define BR_SPI_PUSHR_CTCNT(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CTCNT))
+#endif
+
+//! @brief Format value for bitfield SPI_PUSHR_CTCNT.
+#define BF_SPI_PUSHR_CTCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_CTCNT), uint32_t) & BM_SPI_PUSHR_CTCNT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CTCNT field to a new value.
+#define BW_SPI_PUSHR_CTCNT(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CTCNT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_PUSHR, field EOQ[27] (RW)
+ *
+ * Host software uses this bit to signal to the module that the current SPI
+ * transfer is the last in a queue. At the end of the transfer, the EOQF bit in the
+ * SR is set.
+ *
+ * Values:
+ * - 0 - The SPI data is not the last data to transfer.
+ * - 1 - The SPI data is the last data to transfer.
+ */
+//@{
+#define BP_SPI_PUSHR_EOQ (27U) //!< Bit position for SPI_PUSHR_EOQ.
+#define BM_SPI_PUSHR_EOQ (0x08000000U) //!< Bit mask for SPI_PUSHR_EOQ.
+#define BS_SPI_PUSHR_EOQ (1U) //!< Bit field size in bits for SPI_PUSHR_EOQ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_PUSHR_EOQ field.
+#define BR_SPI_PUSHR_EOQ(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_EOQ))
+#endif
+
+//! @brief Format value for bitfield SPI_PUSHR_EOQ.
+#define BF_SPI_PUSHR_EOQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_EOQ), uint32_t) & BM_SPI_PUSHR_EOQ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EOQ field to a new value.
+#define BW_SPI_PUSHR_EOQ(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_EOQ) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_PUSHR, field CTAS[30:28] (RW)
+ *
+ * Selects which CTAR to use in master mode to specify the transfer attributes
+ * for the associated SPI frame. In SPI Slave mode, CTAR0 is used. See the chip
+ * configuration details to determine how many CTARs this device has. You should
+ * not program a value in this field for a register that is not present.
+ *
+ * Values:
+ * - 000 - CTAR0
+ * - 001 - CTAR1
+ * - 010 - Reserved
+ * - 011 - Reserved
+ * - 100 - Reserved
+ * - 101 - Reserved
+ * - 110 - Reserved
+ * - 111 - Reserved
+ */
+//@{
+#define BP_SPI_PUSHR_CTAS (28U) //!< Bit position for SPI_PUSHR_CTAS.
+#define BM_SPI_PUSHR_CTAS (0x70000000U) //!< Bit mask for SPI_PUSHR_CTAS.
+#define BS_SPI_PUSHR_CTAS (3U) //!< Bit field size in bits for SPI_PUSHR_CTAS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_PUSHR_CTAS field.
+#define BR_SPI_PUSHR_CTAS(x) (HW_SPI_PUSHR(x).B.CTAS)
+#endif
+
+//! @brief Format value for bitfield SPI_PUSHR_CTAS.
+#define BF_SPI_PUSHR_CTAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_CTAS), uint32_t) & BM_SPI_PUSHR_CTAS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CTAS field to a new value.
+#define BW_SPI_PUSHR_CTAS(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_CTAS) | BF_SPI_PUSHR_CTAS(v)))
+#endif
+//@}
+
+/*!
+ * @name Register SPI_PUSHR, field CONT[31] (RW)
+ *
+ * Selects a continuous selection format. The bit is used in SPI Master mode.
+ * The bit enables the selected PCS signals to remain asserted between transfers.
+ *
+ * Values:
+ * - 0 - Return PCSn signals to their inactive state between transfers.
+ * - 1 - Keep PCSn signals asserted between transfers.
+ */
+//@{
+#define BP_SPI_PUSHR_CONT (31U) //!< Bit position for SPI_PUSHR_CONT.
+#define BM_SPI_PUSHR_CONT (0x80000000U) //!< Bit mask for SPI_PUSHR_CONT.
+#define BS_SPI_PUSHR_CONT (1U) //!< Bit field size in bits for SPI_PUSHR_CONT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_PUSHR_CONT field.
+#define BR_SPI_PUSHR_CONT(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CONT))
+#endif
+
+//! @brief Format value for bitfield SPI_PUSHR_CONT.
+#define BF_SPI_PUSHR_CONT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_CONT), uint32_t) & BM_SPI_PUSHR_CONT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CONT field to a new value.
+#define BW_SPI_PUSHR_CONT(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CONT) = (v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
+ * to PUSHR transfers all 32 bits to the TX FIFO. In master mode, the register
+ * transfers 16 bits of data and 16 bits of command information to the TX FIFO. In
+ * slave mode, all 32 register bits can be used as data, supporting up to 32-bit
+ * SPI Frame operation.
+ */
+typedef union _hw_spi_pushr_slave
+{
+ uint32_t U;
+ struct _hw_spi_pushr_slave_bitfields
+ {
+ uint32_t TXDATA : 32; //!< [31:0] Transmit Data
+ } B;
+} hw_spi_pushr_slave_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SPI_PUSHR_SLAVE register
+ */
+//@{
+#define HW_SPI_PUSHR_SLAVE_ADDR(x) (REGS_SPI_BASE(x) + 0x34U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SPI_PUSHR_SLAVE(x) (*(__IO hw_spi_pushr_slave_t *) HW_SPI_PUSHR_SLAVE_ADDR(x))
+#define HW_SPI_PUSHR_SLAVE_RD(x) (HW_SPI_PUSHR_SLAVE(x).U)
+#define HW_SPI_PUSHR_SLAVE_WR(x, v) (HW_SPI_PUSHR_SLAVE(x).U = (v))
+#define HW_SPI_PUSHR_SLAVE_SET(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) | (v)))
+#define HW_SPI_PUSHR_SLAVE_CLR(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) & ~(v)))
+#define HW_SPI_PUSHR_SLAVE_TOG(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SPI_PUSHR_SLAVE bitfields
+ */
+
+/*!
+ * @name Register SPI_PUSHR_SLAVE, field TXDATA[31:0] (RW)
+ *
+ * Holds SPI data to be transferred according to the associated SPI command.
+ */
+//@{
+#define BP_SPI_PUSHR_SLAVE_TXDATA (0U) //!< Bit position for SPI_PUSHR_SLAVE_TXDATA.
+#define BM_SPI_PUSHR_SLAVE_TXDATA (0xFFFFFFFFU) //!< Bit mask for SPI_PUSHR_SLAVE_TXDATA.
+#define BS_SPI_PUSHR_SLAVE_TXDATA (32U) //!< Bit field size in bits for SPI_PUSHR_SLAVE_TXDATA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_PUSHR_SLAVE_TXDATA field.
+#define BR_SPI_PUSHR_SLAVE_TXDATA(x) (HW_SPI_PUSHR_SLAVE(x).U)
+#endif
+
+//! @brief Format value for bitfield SPI_PUSHR_SLAVE_TXDATA.
+#define BF_SPI_PUSHR_SLAVE_TXDATA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SPI_PUSHR_SLAVE_TXDATA), uint32_t) & BM_SPI_PUSHR_SLAVE_TXDATA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXDATA field to a new value.
+#define BW_SPI_PUSHR_SLAVE_TXDATA(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SPI_POPR - POP RX FIFO Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SPI_POPR - POP RX FIFO Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * POPR is used to read the RX FIFO. Eight- or sixteen-bit read accesses to the
+ * POPR have the same effect on the RX FIFO as 32-bit read accesses. A write to
+ * this register will generate a Transfer Error.
+ */
+typedef union _hw_spi_popr
+{
+ uint32_t U;
+ struct _hw_spi_popr_bitfields
+ {
+ uint32_t RXDATA : 32; //!< [31:0] Received Data
+ } B;
+} hw_spi_popr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SPI_POPR register
+ */
+//@{
+#define HW_SPI_POPR_ADDR(x) (REGS_SPI_BASE(x) + 0x38U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SPI_POPR(x) (*(__I hw_spi_popr_t *) HW_SPI_POPR_ADDR(x))
+#define HW_SPI_POPR_RD(x) (HW_SPI_POPR(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SPI_POPR bitfields
+ */
+
+/*!
+ * @name Register SPI_POPR, field RXDATA[31:0] (RO)
+ *
+ * Contains the SPI data from the RX FIFO entry to which the Pop Next Data
+ * Pointer points.
+ */
+//@{
+#define BP_SPI_POPR_RXDATA (0U) //!< Bit position for SPI_POPR_RXDATA.
+#define BM_SPI_POPR_RXDATA (0xFFFFFFFFU) //!< Bit mask for SPI_POPR_RXDATA.
+#define BS_SPI_POPR_RXDATA (32U) //!< Bit field size in bits for SPI_POPR_RXDATA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_POPR_RXDATA field.
+#define BR_SPI_POPR_RXDATA(x) (HW_SPI_POPR(x).U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SPI_TXFRn - Transmit FIFO Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SPI_TXFRn - Transmit FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
+ * Each register is an entry in the TX FIFO. The registers are read-only and
+ * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
+ * FIFO.
+ */
+typedef union _hw_spi_txfrn
+{
+ uint32_t U;
+ struct _hw_spi_txfrn_bitfields
+ {
+ uint32_t TXDATA : 16; //!< [15:0] Transmit Data
+ uint32_t TXCMD_TXDATA : 16; //!< [31:16] Transmit Command or Transmit
+ //! Data
+ } B;
+} hw_spi_txfrn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SPI_TXFRn register
+ */
+//@{
+#define HW_SPI_TXFRn_COUNT (4U)
+
+#define HW_SPI_TXFRn_ADDR(x, n) (REGS_SPI_BASE(x) + 0x3CU + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SPI_TXFRn(x, n) (*(__I hw_spi_txfrn_t *) HW_SPI_TXFRn_ADDR(x, n))
+#define HW_SPI_TXFRn_RD(x, n) (HW_SPI_TXFRn(x, n).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SPI_TXFRn bitfields
+ */
+
+/*!
+ * @name Register SPI_TXFRn, field TXDATA[15:0] (RO)
+ *
+ * Contains the SPI data to be shifted out.
+ */
+//@{
+#define BP_SPI_TXFRn_TXDATA (0U) //!< Bit position for SPI_TXFRn_TXDATA.
+#define BM_SPI_TXFRn_TXDATA (0x0000FFFFU) //!< Bit mask for SPI_TXFRn_TXDATA.
+#define BS_SPI_TXFRn_TXDATA (16U) //!< Bit field size in bits for SPI_TXFRn_TXDATA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_TXFRn_TXDATA field.
+#define BR_SPI_TXFRn_TXDATA(x, n) (HW_SPI_TXFRn(x, n).B.TXDATA)
+#endif
+//@}
+
+/*!
+ * @name Register SPI_TXFRn, field TXCMD_TXDATA[31:16] (RO)
+ *
+ * In Master mode the TXCMD field contains the command that sets the transfer
+ * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
+ * the SPI data to be shifted out.
+ */
+//@{
+#define BP_SPI_TXFRn_TXCMD_TXDATA (16U) //!< Bit position for SPI_TXFRn_TXCMD_TXDATA.
+#define BM_SPI_TXFRn_TXCMD_TXDATA (0xFFFF0000U) //!< Bit mask for SPI_TXFRn_TXCMD_TXDATA.
+#define BS_SPI_TXFRn_TXCMD_TXDATA (16U) //!< Bit field size in bits for SPI_TXFRn_TXCMD_TXDATA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_TXFRn_TXCMD_TXDATA field.
+#define BR_SPI_TXFRn_TXCMD_TXDATA(x, n) (HW_SPI_TXFRn(x, n).B.TXCMD_TXDATA)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SPI_RXFRn - Receive FIFO Registers
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SPI_RXFRn - Receive FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
+ * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
+ * RXFRx registers does not alter the state of the RX FIFO.
+ */
+typedef union _hw_spi_rxfrn
+{
+ uint32_t U;
+ struct _hw_spi_rxfrn_bitfields
+ {
+ uint32_t RXDATA : 32; //!< [31:0] Receive Data
+ } B;
+} hw_spi_rxfrn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SPI_RXFRn register
+ */
+//@{
+#define HW_SPI_RXFRn_COUNT (4U)
+
+#define HW_SPI_RXFRn_ADDR(x, n) (REGS_SPI_BASE(x) + 0x7CU + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SPI_RXFRn(x, n) (*(__I hw_spi_rxfrn_t *) HW_SPI_RXFRn_ADDR(x, n))
+#define HW_SPI_RXFRn_RD(x, n) (HW_SPI_RXFRn(x, n).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual SPI_RXFRn bitfields
+ */
+
+/*!
+ * @name Register SPI_RXFRn, field RXDATA[31:0] (RO)
+ *
+ * Contains the received SPI data.
+ */
+//@{
+#define BP_SPI_RXFRn_RXDATA (0U) //!< Bit position for SPI_RXFRn_RXDATA.
+#define BM_SPI_RXFRn_RXDATA (0xFFFFFFFFU) //!< Bit mask for SPI_RXFRn_RXDATA.
+#define BS_SPI_RXFRn_RXDATA (32U) //!< Bit field size in bits for SPI_RXFRn_RXDATA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the SPI_RXFRn_RXDATA field.
+#define BR_SPI_RXFRn_RXDATA(x, n) (HW_SPI_RXFRn(x, n).U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_spi_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All SPI module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_spi
+{
+ __IO hw_spi_mcr_t MCR; //!< [0x0] Module Configuration Register
+ uint8_t _reserved0[4];
+ __IO hw_spi_tcr_t TCR; //!< [0x8] Transfer Count Register
+ union {
+ __IO hw_spi_ctarn_t CTARn[2]; //!< [0xC] Clock and Transfer Attributes Register (In Master Mode)
+ __IO hw_spi_ctarn_slave_t CTARn_SLAVE[1]; //!< [0xC] Clock and Transfer Attributes Register (In Slave Mode)
+ };
+ uint8_t _reserved1[24];
+ __IO hw_spi_sr_t SR; //!< [0x2C] Status Register
+ __IO hw_spi_rser_t RSER; //!< [0x30] DMA/Interrupt Request Select and Enable Register
+ union {
+ __IO hw_spi_pushr_t PUSHR; //!< [0x34] PUSH TX FIFO Register In Master Mode
+ __IO hw_spi_pushr_slave_t PUSHR_SLAVE; //!< [0x34] PUSH TX FIFO Register In Slave Mode
+ };
+ __I hw_spi_popr_t POPR; //!< [0x38] POP RX FIFO Register
+ __I hw_spi_txfrn_t TXFRn[4]; //!< [0x3C] Transmit FIFO Registers
+ uint8_t _reserved2[48];
+ __I hw_spi_rxfrn_t RXFRn[4]; //!< [0x7C] Receive FIFO Registers
+} hw_spi_t;
+#pragma pack()
+
+//! @brief Macro to access all SPI registers.
+//! @param x SPI instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_SPI(0)</code>.
+#define HW_SPI(x) (*(hw_spi_t *) REGS_SPI_BASE(x))
+#endif
+
+#endif // __HW_SPI_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_uart.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,4933 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_UART_REGISTERS_H__
+#define __HW_UART_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 UART
+ *
+ * Serial Communication Interface
+ *
+ * Registers defined in this header file:
+ * - HW_UART_BDH - UART Baud Rate Registers: High
+ * - HW_UART_BDL - UART Baud Rate Registers: Low
+ * - HW_UART_C1 - UART Control Register 1
+ * - HW_UART_C2 - UART Control Register 2
+ * - HW_UART_S1 - UART Status Register 1
+ * - HW_UART_S2 - UART Status Register 2
+ * - HW_UART_C3 - UART Control Register 3
+ * - HW_UART_D - UART Data Register
+ * - HW_UART_MA1 - UART Match Address Registers 1
+ * - HW_UART_MA2 - UART Match Address Registers 2
+ * - HW_UART_C4 - UART Control Register 4
+ * - HW_UART_C5 - UART Control Register 5
+ * - HW_UART_ED - UART Extended Data Register
+ * - HW_UART_MODEM - UART Modem Register
+ * - HW_UART_IR - UART Infrared Register
+ * - HW_UART_PFIFO - UART FIFO Parameters
+ * - HW_UART_CFIFO - UART FIFO Control Register
+ * - HW_UART_SFIFO - UART FIFO Status Register
+ * - HW_UART_TWFIFO - UART FIFO Transmit Watermark
+ * - HW_UART_TCFIFO - UART FIFO Transmit Count
+ * - HW_UART_RWFIFO - UART FIFO Receive Watermark
+ * - HW_UART_RCFIFO - UART FIFO Receive Count
+ * - HW_UART_C7816 - UART 7816 Control Register
+ * - HW_UART_IE7816 - UART 7816 Interrupt Enable Register
+ * - HW_UART_IS7816 - UART 7816 Interrupt Status Register
+ * - HW_UART_WP7816_T_TYPE0 - UART 7816 Wait Parameter Register
+ * - HW_UART_WP7816_T_TYPE1 - UART 7816 Wait Parameter Register
+ * - HW_UART_WN7816 - UART 7816 Wait N Register
+ * - HW_UART_WF7816 - UART 7816 Wait FD Register
+ * - HW_UART_ET7816 - UART 7816 Error Threshold Register
+ * - HW_UART_TL7816 - UART 7816 Transmit Length Register
+ *
+ * - hw_uart_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_UART_BASE
+#define HW_UART_INSTANCE_COUNT (6U) //!< Number of instances of the UART module.
+#define HW_UART0 (0U) //!< Instance number for UART0.
+#define HW_UART1 (1U) //!< Instance number for UART1.
+#define HW_UART2 (2U) //!< Instance number for UART2.
+#define HW_UART3 (3U) //!< Instance number for UART3.
+#define HW_UART4 (4U) //!< Instance number for UART4.
+#define HW_UART5 (5U) //!< Instance number for UART5.
+#define REGS_UART0_BASE (0x4006A000U) //!< Base address for UART0.
+#define REGS_UART1_BASE (0x4006B000U) //!< Base address for UART1.
+#define REGS_UART2_BASE (0x4006C000U) //!< Base address for UART2.
+#define REGS_UART3_BASE (0x4006D000U) //!< Base address for UART3.
+#define REGS_UART4_BASE (0x400EA000U) //!< Base address for UART4.
+#define REGS_UART5_BASE (0x400EB000U) //!< Base address for UART5.
+
+//! @brief Table of base addresses for UART instances.
+static const uint32_t __g_regs_UART_base_addresses[] = {
+ REGS_UART0_BASE,
+ REGS_UART1_BASE,
+ REGS_UART2_BASE,
+ REGS_UART3_BASE,
+ REGS_UART4_BASE,
+ REGS_UART5_BASE,
+ };
+
+//! @brief Get the base address of UART by instance number.
+//! @param x UART instance number, from 0 through 5.
+#define REGS_UART_BASE(x) (__g_regs_UART_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of UART.
+#define REGS_UART_INSTANCE(b) ((b) == REGS_UART0_BASE ? HW_UART0 : (b) == REGS_UART1_BASE ? HW_UART1 : (b) == REGS_UART2_BASE ? HW_UART2 : (b) == REGS_UART3_BASE ? HW_UART3 : (b) == REGS_UART4_BASE ? HW_UART4 : (b) == REGS_UART5_BASE ? HW_UART5 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_BDH - UART Baud Rate Registers: High
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_BDH - UART Baud Rate Registers: High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register, along with the BDL register, controls the prescale divisor for
+ * UART baud rate generation. To update the 13-bit baud rate setting
+ * (SBR[12:0]), first write to BDH to buffer the high half of the new value and then write
+ * to BDL. The working value in BDH does not change until BDL is written. BDL is
+ * reset to a nonzero value, but after reset, the baud rate generator remains
+ * disabled until the first time the receiver or transmitter is enabled, that is,
+ * when C2[RE] or C2[TE] is set.
+ */
+typedef union _hw_uart_bdh
+{
+ uint8_t U;
+ struct _hw_uart_bdh_bitfields
+ {
+ uint8_t SBR : 5; //!< [4:0] UART Baud Rate Bits
+ uint8_t SBNS : 1; //!< [5] Stop Bit Number Select
+ uint8_t RXEDGIE : 1; //!< [6] RxD Input Active Edge Interrupt Enable
+ uint8_t LBKDIE : 1; //!< [7] LIN Break Detect Interrupt or DMA
+ //! Request Enable
+ } B;
+} hw_uart_bdh_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_BDH register
+ */
+//@{
+#define HW_UART_BDH_ADDR(x) (REGS_UART_BASE(x) + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_BDH(x) (*(__IO hw_uart_bdh_t *) HW_UART_BDH_ADDR(x))
+#define HW_UART_BDH_RD(x) (HW_UART_BDH(x).U)
+#define HW_UART_BDH_WR(x, v) (HW_UART_BDH(x).U = (v))
+#define HW_UART_BDH_SET(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) | (v)))
+#define HW_UART_BDH_CLR(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) & ~(v)))
+#define HW_UART_BDH_TOG(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_BDH bitfields
+ */
+
+/*!
+ * @name Register UART_BDH, field SBR[4:0] (RW)
+ *
+ * The baud rate for the UART is determined by the 13 SBR fields. See Baud rate
+ * generation for details. The baud rate generator is disabled until C2[TE] or
+ * C2[RE] is set for the first time after reset.The baud rate generator is disabled
+ * when SBR = 0. Writing to BDH has no effect without writing to BDL, because
+ * writing to BDH puts the data in a temporary location until BDL is written.
+ */
+//@{
+#define BP_UART_BDH_SBR (0U) //!< Bit position for UART_BDH_SBR.
+#define BM_UART_BDH_SBR (0x1FU) //!< Bit mask for UART_BDH_SBR.
+#define BS_UART_BDH_SBR (5U) //!< Bit field size in bits for UART_BDH_SBR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_BDH_SBR field.
+#define BR_UART_BDH_SBR(x) (HW_UART_BDH(x).B.SBR)
+#endif
+
+//! @brief Format value for bitfield UART_BDH_SBR.
+#define BF_UART_BDH_SBR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_BDH_SBR), uint8_t) & BM_UART_BDH_SBR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SBR field to a new value.
+#define BW_UART_BDH_SBR(x, v) (HW_UART_BDH_WR(x, (HW_UART_BDH_RD(x) & ~BM_UART_BDH_SBR) | BF_UART_BDH_SBR(v)))
+#endif
+//@}
+
+/*!
+ * @name Register UART_BDH, field SBNS[5] (RW)
+ *
+ * SBNS selects the number of stop bits present in a data frame. This field
+ * valid for all 8, 9 and 10 bit data formats available. This field is not valid when
+ * C7816[ISO7816E] is enabled.
+ *
+ * Values:
+ * - 0 - Data frame consists of a single stop bit.
+ * - 1 - Data frame consists of two stop bits.
+ */
+//@{
+#define BP_UART_BDH_SBNS (5U) //!< Bit position for UART_BDH_SBNS.
+#define BM_UART_BDH_SBNS (0x20U) //!< Bit mask for UART_BDH_SBNS.
+#define BS_UART_BDH_SBNS (1U) //!< Bit field size in bits for UART_BDH_SBNS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_BDH_SBNS field.
+#define BR_UART_BDH_SBNS(x) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_SBNS))
+#endif
+
+//! @brief Format value for bitfield UART_BDH_SBNS.
+#define BF_UART_BDH_SBNS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_BDH_SBNS), uint8_t) & BM_UART_BDH_SBNS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SBNS field to a new value.
+#define BW_UART_BDH_SBNS(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_SBNS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_BDH, field RXEDGIE[6] (RW)
+ *
+ * Enables the receive input active edge, RXEDGIF, to generate interrupt
+ * requests.
+ *
+ * Values:
+ * - 0 - Hardware interrupts from RXEDGIF disabled using polling.
+ * - 1 - RXEDGIF interrupt request enabled.
+ */
+//@{
+#define BP_UART_BDH_RXEDGIE (6U) //!< Bit position for UART_BDH_RXEDGIE.
+#define BM_UART_BDH_RXEDGIE (0x40U) //!< Bit mask for UART_BDH_RXEDGIE.
+#define BS_UART_BDH_RXEDGIE (1U) //!< Bit field size in bits for UART_BDH_RXEDGIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_BDH_RXEDGIE field.
+#define BR_UART_BDH_RXEDGIE(x) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_RXEDGIE))
+#endif
+
+//! @brief Format value for bitfield UART_BDH_RXEDGIE.
+#define BF_UART_BDH_RXEDGIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_BDH_RXEDGIE), uint8_t) & BM_UART_BDH_RXEDGIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXEDGIE field to a new value.
+#define BW_UART_BDH_RXEDGIE(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_RXEDGIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_BDH, field LBKDIE[7] (RW)
+ *
+ * Enables the LIN break detect flag, LBKDIF, to generate interrupt requests
+ * based on the state of LBKDDMAS. or DMA transfer requests,
+ *
+ * Values:
+ * - 0 - LBKDIF interrupt and DMA transfer requests disabled.
+ * - 1 - LBKDIF interrupt or DMA transfer requests enabled.
+ */
+//@{
+#define BP_UART_BDH_LBKDIE (7U) //!< Bit position for UART_BDH_LBKDIE.
+#define BM_UART_BDH_LBKDIE (0x80U) //!< Bit mask for UART_BDH_LBKDIE.
+#define BS_UART_BDH_LBKDIE (1U) //!< Bit field size in bits for UART_BDH_LBKDIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_BDH_LBKDIE field.
+#define BR_UART_BDH_LBKDIE(x) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_LBKDIE))
+#endif
+
+//! @brief Format value for bitfield UART_BDH_LBKDIE.
+#define BF_UART_BDH_LBKDIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_BDH_LBKDIE), uint8_t) & BM_UART_BDH_LBKDIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LBKDIE field to a new value.
+#define BW_UART_BDH_LBKDIE(x, v) (BITBAND_ACCESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_LBKDIE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_BDL - UART Baud Rate Registers: Low
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_BDL - UART Baud Rate Registers: Low (RW)
+ *
+ * Reset value: 0x04U
+ *
+ * This register, along with the BDH register, controls the prescale divisor for
+ * UART baud rate generation. To update the 13-bit baud rate setting, SBR[12:0],
+ * first write to BDH to buffer the high half of the new value and then write to
+ * BDL. The working value in BDH does not change until BDL is written. BDL is
+ * reset to a nonzero value, but after reset, the baud rate generator remains
+ * disabled until the first time the receiver or transmitter is enabled, that is, when
+ * C2[RE] or C2[TE] is set.
+ */
+typedef union _hw_uart_bdl
+{
+ uint8_t U;
+ struct _hw_uart_bdl_bitfields
+ {
+ uint8_t SBR : 8; //!< [7:0] UART Baud Rate Bits
+ } B;
+} hw_uart_bdl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_BDL register
+ */
+//@{
+#define HW_UART_BDL_ADDR(x) (REGS_UART_BASE(x) + 0x1U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_BDL(x) (*(__IO hw_uart_bdl_t *) HW_UART_BDL_ADDR(x))
+#define HW_UART_BDL_RD(x) (HW_UART_BDL(x).U)
+#define HW_UART_BDL_WR(x, v) (HW_UART_BDL(x).U = (v))
+#define HW_UART_BDL_SET(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) | (v)))
+#define HW_UART_BDL_CLR(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) & ~(v)))
+#define HW_UART_BDL_TOG(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_BDL bitfields
+ */
+
+/*!
+ * @name Register UART_BDL, field SBR[7:0] (RW)
+ *
+ * The baud rate for the UART is determined by the 13 SBR fields. See Baud rate
+ * generation for details. The baud rate generator is disabled until C2[TE] or
+ * C2[RE] is set for the first time after reset.The baud rate generator is disabled
+ * when SBR = 0. Writing to BDH has no effect without writing to BDL, because
+ * writing to BDH puts the data in a temporary location until BDL is written. When
+ * the 1/32 narrow pulse width is selected for infrared (IrDA), the baud rate
+ * fields must be even, the least significant bit is 0. See MODEM register for more
+ * details.
+ */
+//@{
+#define BP_UART_BDL_SBR (0U) //!< Bit position for UART_BDL_SBR.
+#define BM_UART_BDL_SBR (0xFFU) //!< Bit mask for UART_BDL_SBR.
+#define BS_UART_BDL_SBR (8U) //!< Bit field size in bits for UART_BDL_SBR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_BDL_SBR field.
+#define BR_UART_BDL_SBR(x) (HW_UART_BDL(x).U)
+#endif
+
+//! @brief Format value for bitfield UART_BDL_SBR.
+#define BF_UART_BDL_SBR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_BDL_SBR), uint8_t) & BM_UART_BDL_SBR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SBR field to a new value.
+#define BW_UART_BDL_SBR(x, v) (HW_UART_BDL_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_C1 - UART Control Register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_C1 - UART Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This read/write register controls various optional features of the UART
+ * system.
+ */
+typedef union _hw_uart_c1
+{
+ uint8_t U;
+ struct _hw_uart_c1_bitfields
+ {
+ uint8_t PT : 1; //!< [0] Parity Type
+ uint8_t PE : 1; //!< [1] Parity Enable
+ uint8_t ILT : 1; //!< [2] Idle Line Type Select
+ uint8_t WAKE : 1; //!< [3] Receiver Wakeup Method Select
+ uint8_t M : 1; //!< [4] 9-bit or 8-bit Mode Select
+ uint8_t RSRC : 1; //!< [5] Receiver Source Select
+ uint8_t UARTSWAI : 1; //!< [6] UART Stops in Wait Mode
+ uint8_t LOOPS : 1; //!< [7] Loop Mode Select
+ } B;
+} hw_uart_c1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_C1 register
+ */
+//@{
+#define HW_UART_C1_ADDR(x) (REGS_UART_BASE(x) + 0x2U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_C1(x) (*(__IO hw_uart_c1_t *) HW_UART_C1_ADDR(x))
+#define HW_UART_C1_RD(x) (HW_UART_C1(x).U)
+#define HW_UART_C1_WR(x, v) (HW_UART_C1(x).U = (v))
+#define HW_UART_C1_SET(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) | (v)))
+#define HW_UART_C1_CLR(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) & ~(v)))
+#define HW_UART_C1_TOG(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_C1 bitfields
+ */
+
+/*!
+ * @name Register UART_C1, field PT[0] (RW)
+ *
+ * Determines whether the UART generates and checks for even parity or odd
+ * parity. With even parity, an even number of 1s clears the parity bit and an odd
+ * number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the
+ * parity bit and an even number of 1s sets the parity bit. This field must be
+ * cleared when C7816[ISO_7816E] is set/enabled.
+ *
+ * Values:
+ * - 0 - Even parity.
+ * - 1 - Odd parity.
+ */
+//@{
+#define BP_UART_C1_PT (0U) //!< Bit position for UART_C1_PT.
+#define BM_UART_C1_PT (0x01U) //!< Bit mask for UART_C1_PT.
+#define BS_UART_C1_PT (1U) //!< Bit field size in bits for UART_C1_PT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C1_PT field.
+#define BR_UART_C1_PT(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PT))
+#endif
+
+//! @brief Format value for bitfield UART_C1_PT.
+#define BF_UART_C1_PT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_PT), uint8_t) & BM_UART_C1_PT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PT field to a new value.
+#define BW_UART_C1_PT(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C1, field PE[1] (RW)
+ *
+ * Enables the parity function. When parity is enabled, parity function inserts
+ * a parity bit in the bit position immediately preceding the stop bit. This
+ * field must be set when C7816[ISO_7816E] is set/enabled.
+ *
+ * Values:
+ * - 0 - Parity function disabled.
+ * - 1 - Parity function enabled.
+ */
+//@{
+#define BP_UART_C1_PE (1U) //!< Bit position for UART_C1_PE.
+#define BM_UART_C1_PE (0x02U) //!< Bit mask for UART_C1_PE.
+#define BS_UART_C1_PE (1U) //!< Bit field size in bits for UART_C1_PE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C1_PE field.
+#define BR_UART_C1_PE(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PE))
+#endif
+
+//! @brief Format value for bitfield UART_C1_PE.
+#define BF_UART_C1_PE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_PE), uint8_t) & BM_UART_C1_PE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PE field to a new value.
+#define BW_UART_C1_PE(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C1, field ILT[2] (RW)
+ *
+ * Determines when the receiver starts counting logic 1s as idle character bits.
+ * The count begins either after a valid start bit or after the stop bit. If the
+ * count begins after the start bit, then a string of logic 1s preceding the
+ * stop bit can cause false recognition of an idle character. Beginning the count
+ * after the stop bit avoids false idle character recognition, but requires
+ * properly synchronized transmissions. In case the UART is programmed with ILT = 1, a
+ * logic of 1'b0 is automatically shifted after a received stop bit, therefore
+ * resetting the idle count. In case the UART is programmed for IDLE line wakeup
+ * (RWU = 1 and WAKE = 0), ILT has no effect on when the receiver starts counting
+ * logic 1s as idle character bits. In idle line wakeup, an idle character is
+ * recognized at anytime the receiver sees 10, 11, or 12 1s depending on the M, PE,
+ * and C4[M10] fields.
+ *
+ * Values:
+ * - 0 - Idle character bit count starts after start bit.
+ * - 1 - Idle character bit count starts after stop bit.
+ */
+//@{
+#define BP_UART_C1_ILT (2U) //!< Bit position for UART_C1_ILT.
+#define BM_UART_C1_ILT (0x04U) //!< Bit mask for UART_C1_ILT.
+#define BS_UART_C1_ILT (1U) //!< Bit field size in bits for UART_C1_ILT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C1_ILT field.
+#define BR_UART_C1_ILT(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_ILT))
+#endif
+
+//! @brief Format value for bitfield UART_C1_ILT.
+#define BF_UART_C1_ILT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_ILT), uint8_t) & BM_UART_C1_ILT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ILT field to a new value.
+#define BW_UART_C1_ILT(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_ILT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C1, field WAKE[3] (RW)
+ *
+ * Determines which condition wakes the UART: Address mark in the most
+ * significant bit position of a received data character, or An idle condition on the
+ * receive pin input signal.
+ *
+ * Values:
+ * - 0 - Idle line wakeup.
+ * - 1 - Address mark wakeup.
+ */
+//@{
+#define BP_UART_C1_WAKE (3U) //!< Bit position for UART_C1_WAKE.
+#define BM_UART_C1_WAKE (0x08U) //!< Bit mask for UART_C1_WAKE.
+#define BS_UART_C1_WAKE (1U) //!< Bit field size in bits for UART_C1_WAKE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C1_WAKE field.
+#define BR_UART_C1_WAKE(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_WAKE))
+#endif
+
+//! @brief Format value for bitfield UART_C1_WAKE.
+#define BF_UART_C1_WAKE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_WAKE), uint8_t) & BM_UART_C1_WAKE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WAKE field to a new value.
+#define BW_UART_C1_WAKE(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_WAKE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C1, field M[4] (RW)
+ *
+ * This field must be set when C7816[ISO_7816E] is set/enabled.
+ *
+ * Values:
+ * - 0 - Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
+ * - 1 - Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
+ */
+//@{
+#define BP_UART_C1_M (4U) //!< Bit position for UART_C1_M.
+#define BM_UART_C1_M (0x10U) //!< Bit mask for UART_C1_M.
+#define BS_UART_C1_M (1U) //!< Bit field size in bits for UART_C1_M.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C1_M field.
+#define BR_UART_C1_M(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_M))
+#endif
+
+//! @brief Format value for bitfield UART_C1_M.
+#define BF_UART_C1_M(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_M), uint8_t) & BM_UART_C1_M)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M field to a new value.
+#define BW_UART_C1_M(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_M) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C1, field RSRC[5] (RW)
+ *
+ * This field has no meaning or effect unless the LOOPS field is set. When LOOPS
+ * is set, the RSRC field determines the source for the receiver shift register
+ * input.
+ *
+ * Values:
+ * - 0 - Selects internal loop back mode. The receiver input is internally
+ * connected to transmitter output.
+ * - 1 - Single wire UART mode where the receiver input is connected to the
+ * transmit pin input signal.
+ */
+//@{
+#define BP_UART_C1_RSRC (5U) //!< Bit position for UART_C1_RSRC.
+#define BM_UART_C1_RSRC (0x20U) //!< Bit mask for UART_C1_RSRC.
+#define BS_UART_C1_RSRC (1U) //!< Bit field size in bits for UART_C1_RSRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C1_RSRC field.
+#define BR_UART_C1_RSRC(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_RSRC))
+#endif
+
+//! @brief Format value for bitfield UART_C1_RSRC.
+#define BF_UART_C1_RSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_RSRC), uint8_t) & BM_UART_C1_RSRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RSRC field to a new value.
+#define BW_UART_C1_RSRC(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_RSRC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C1, field UARTSWAI[6] (RW)
+ *
+ * Values:
+ * - 0 - UART clock continues to run in Wait mode.
+ * - 1 - UART clock freezes while CPU is in Wait mode.
+ */
+//@{
+#define BP_UART_C1_UARTSWAI (6U) //!< Bit position for UART_C1_UARTSWAI.
+#define BM_UART_C1_UARTSWAI (0x40U) //!< Bit mask for UART_C1_UARTSWAI.
+#define BS_UART_C1_UARTSWAI (1U) //!< Bit field size in bits for UART_C1_UARTSWAI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C1_UARTSWAI field.
+#define BR_UART_C1_UARTSWAI(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_UARTSWAI))
+#endif
+
+//! @brief Format value for bitfield UART_C1_UARTSWAI.
+#define BF_UART_C1_UARTSWAI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_UARTSWAI), uint8_t) & BM_UART_C1_UARTSWAI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the UARTSWAI field to a new value.
+#define BW_UART_C1_UARTSWAI(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_UARTSWAI) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C1, field LOOPS[7] (RW)
+ *
+ * When LOOPS is set, the RxD pin is disconnected from the UART and the
+ * transmitter output is internally connected to the receiver input. The transmitter and
+ * the receiver must be enabled to use the loop function.
+ *
+ * Values:
+ * - 0 - Normal operation.
+ * - 1 - Loop mode where transmitter output is internally connected to receiver
+ * input. The receiver input is determined by RSRC.
+ */
+//@{
+#define BP_UART_C1_LOOPS (7U) //!< Bit position for UART_C1_LOOPS.
+#define BM_UART_C1_LOOPS (0x80U) //!< Bit mask for UART_C1_LOOPS.
+#define BS_UART_C1_LOOPS (1U) //!< Bit field size in bits for UART_C1_LOOPS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C1_LOOPS field.
+#define BR_UART_C1_LOOPS(x) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_LOOPS))
+#endif
+
+//! @brief Format value for bitfield UART_C1_LOOPS.
+#define BF_UART_C1_LOOPS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C1_LOOPS), uint8_t) & BM_UART_C1_LOOPS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LOOPS field to a new value.
+#define BW_UART_C1_LOOPS(x, v) (BITBAND_ACCESS8(HW_UART_C1_ADDR(x), BP_UART_C1_LOOPS) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_C2 - UART Control Register 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_C2 - UART Control Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register can be read or written at any time.
+ */
+typedef union _hw_uart_c2
+{
+ uint8_t U;
+ struct _hw_uart_c2_bitfields
+ {
+ uint8_t SBK : 1; //!< [0] Send Break
+ uint8_t RWU : 1; //!< [1] Receiver Wakeup Control
+ uint8_t RE : 1; //!< [2] Receiver Enable
+ uint8_t TE : 1; //!< [3] Transmitter Enable
+ uint8_t ILIE : 1; //!< [4] Idle Line Interrupt DMA Transfer Enable
+ uint8_t RIE : 1; //!< [5] Receiver Full Interrupt or DMA Transfer
+ //! Enable
+ uint8_t TCIE : 1; //!< [6] Transmission Complete Interrupt or DMA
+ //! Transfer Enable
+ uint8_t TIE : 1; //!< [7] Transmitter Interrupt or DMA Transfer
+ //! Enable.
+ } B;
+} hw_uart_c2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_C2 register
+ */
+//@{
+#define HW_UART_C2_ADDR(x) (REGS_UART_BASE(x) + 0x3U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_C2(x) (*(__IO hw_uart_c2_t *) HW_UART_C2_ADDR(x))
+#define HW_UART_C2_RD(x) (HW_UART_C2(x).U)
+#define HW_UART_C2_WR(x, v) (HW_UART_C2(x).U = (v))
+#define HW_UART_C2_SET(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) | (v)))
+#define HW_UART_C2_CLR(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) & ~(v)))
+#define HW_UART_C2_TOG(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_C2 bitfields
+ */
+
+/*!
+ * @name Register UART_C2, field SBK[0] (RW)
+ *
+ * Toggling SBK sends one break character from the following: See Transmitting
+ * break characters for the number of logic 0s for the different configurations.
+ * Toggling implies clearing the SBK field before the break character has finished
+ * transmitting. As long as SBK is set, the transmitter continues to send
+ * complete break characters (10, 11, or 12 bits, or 13 or 14 bits, or 15 or 16 bits).
+ * Ensure that C2[TE] is asserted atleast 1 clock before assertion of this bit.
+ * 10, 11, or 12 logic 0s if S2[BRK13] is cleared 13 or 14 logic 0s if S2[BRK13]
+ * is set. 15 or 16 logic 0s if BDH[SBNS] is set. This field must be cleared when
+ * C7816[ISO_7816E] is set.
+ *
+ * Values:
+ * - 0 - Normal transmitter operation.
+ * - 1 - Queue break characters to be sent.
+ */
+//@{
+#define BP_UART_C2_SBK (0U) //!< Bit position for UART_C2_SBK.
+#define BM_UART_C2_SBK (0x01U) //!< Bit mask for UART_C2_SBK.
+#define BS_UART_C2_SBK (1U) //!< Bit field size in bits for UART_C2_SBK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C2_SBK field.
+#define BR_UART_C2_SBK(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_SBK))
+#endif
+
+//! @brief Format value for bitfield UART_C2_SBK.
+#define BF_UART_C2_SBK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_SBK), uint8_t) & BM_UART_C2_SBK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SBK field to a new value.
+#define BW_UART_C2_SBK(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_SBK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C2, field RWU[1] (RW)
+ *
+ * This field can be set to place the UART receiver in a standby state. RWU
+ * automatically clears when an RWU event occurs, that is, an IDLE event when
+ * C1[WAKE] is clear or an address match when C1[WAKE] is set. This field must be
+ * cleared when C7816[ISO_7816E] is set. RWU must be set only with C1[WAKE] = 0 (wakeup
+ * on idle) if the channel is currently not idle. This can be determined by
+ * S2[RAF]. If the flag is set to wake up an IDLE event and the channel is already
+ * idle, it is possible that the UART will discard data. This is because the data
+ * must be received or a LIN break detected after an IDLE is detected before IDLE
+ * is allowed to reasserted.
+ *
+ * Values:
+ * - 0 - Normal operation.
+ * - 1 - RWU enables the wakeup function and inhibits further receiver interrupt
+ * requests. Normally, hardware wakes the receiver by automatically clearing
+ * RWU.
+ */
+//@{
+#define BP_UART_C2_RWU (1U) //!< Bit position for UART_C2_RWU.
+#define BM_UART_C2_RWU (0x02U) //!< Bit mask for UART_C2_RWU.
+#define BS_UART_C2_RWU (1U) //!< Bit field size in bits for UART_C2_RWU.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C2_RWU field.
+#define BR_UART_C2_RWU(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RWU))
+#endif
+
+//! @brief Format value for bitfield UART_C2_RWU.
+#define BF_UART_C2_RWU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_RWU), uint8_t) & BM_UART_C2_RWU)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RWU field to a new value.
+#define BW_UART_C2_RWU(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RWU) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C2, field RE[2] (RW)
+ *
+ * Enables the UART receiver.
+ *
+ * Values:
+ * - 0 - Receiver off.
+ * - 1 - Receiver on.
+ */
+//@{
+#define BP_UART_C2_RE (2U) //!< Bit position for UART_C2_RE.
+#define BM_UART_C2_RE (0x04U) //!< Bit mask for UART_C2_RE.
+#define BS_UART_C2_RE (1U) //!< Bit field size in bits for UART_C2_RE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C2_RE field.
+#define BR_UART_C2_RE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RE))
+#endif
+
+//! @brief Format value for bitfield UART_C2_RE.
+#define BF_UART_C2_RE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_RE), uint8_t) & BM_UART_C2_RE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RE field to a new value.
+#define BW_UART_C2_RE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C2, field TE[3] (RW)
+ *
+ * Enables the UART transmitter. TE can be used to queue an idle preamble by
+ * clearing and then setting TE. When C7816[ISO_7816E] is set/enabled and
+ * C7816[TTYPE] = 1, this field is automatically cleared after the requested block has been
+ * transmitted. This condition is detected when TL7816[TLEN] = 0 and four
+ * additional characters are transmitted.
+ *
+ * Values:
+ * - 0 - Transmitter off.
+ * - 1 - Transmitter on.
+ */
+//@{
+#define BP_UART_C2_TE (3U) //!< Bit position for UART_C2_TE.
+#define BM_UART_C2_TE (0x08U) //!< Bit mask for UART_C2_TE.
+#define BS_UART_C2_TE (1U) //!< Bit field size in bits for UART_C2_TE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C2_TE field.
+#define BR_UART_C2_TE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TE))
+#endif
+
+//! @brief Format value for bitfield UART_C2_TE.
+#define BF_UART_C2_TE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_TE), uint8_t) & BM_UART_C2_TE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TE field to a new value.
+#define BW_UART_C2_TE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C2, field ILIE[4] (RW)
+ *
+ * Enables the idle line flag, S1[IDLE], to generate interrupt requestsor DMA
+ * transfer requests based on the state of C5[ILDMAS].
+ *
+ * Values:
+ * - 0 - IDLE interrupt requests disabled. and DMA transfer
+ * - 1 - IDLE interrupt requests enabled. or DMA transfer
+ */
+//@{
+#define BP_UART_C2_ILIE (4U) //!< Bit position for UART_C2_ILIE.
+#define BM_UART_C2_ILIE (0x10U) //!< Bit mask for UART_C2_ILIE.
+#define BS_UART_C2_ILIE (1U) //!< Bit field size in bits for UART_C2_ILIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C2_ILIE field.
+#define BR_UART_C2_ILIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_ILIE))
+#endif
+
+//! @brief Format value for bitfield UART_C2_ILIE.
+#define BF_UART_C2_ILIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_ILIE), uint8_t) & BM_UART_C2_ILIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ILIE field to a new value.
+#define BW_UART_C2_ILIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_ILIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C2, field RIE[5] (RW)
+ *
+ * Enables S1[RDRF] to generate interrupt requests or DMA transfer requests,
+ * based on the state of C5[RDMAS].
+ *
+ * Values:
+ * - 0 - RDRF interrupt and DMA transfer requests disabled.
+ * - 1 - RDRF interrupt or DMA transfer requests enabled.
+ */
+//@{
+#define BP_UART_C2_RIE (5U) //!< Bit position for UART_C2_RIE.
+#define BM_UART_C2_RIE (0x20U) //!< Bit mask for UART_C2_RIE.
+#define BS_UART_C2_RIE (1U) //!< Bit field size in bits for UART_C2_RIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C2_RIE field.
+#define BR_UART_C2_RIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RIE))
+#endif
+
+//! @brief Format value for bitfield UART_C2_RIE.
+#define BF_UART_C2_RIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_RIE), uint8_t) & BM_UART_C2_RIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RIE field to a new value.
+#define BW_UART_C2_RIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C2, field TCIE[6] (RW)
+ *
+ * Enables the transmission complete flag, S1[TC], to generate interrupt
+ * requests . or DMA transfer requests based on the state of C5[TCDMAS] If C2[TCIE] and
+ * C5[TCDMAS] are both set, then TIE must be cleared, and D[D] must not be
+ * written unless servicing a DMA request.
+ *
+ * Values:
+ * - 0 - TC interrupt and DMA transfer requests disabled.
+ * - 1 - TC interrupt or DMA transfer requests enabled.
+ */
+//@{
+#define BP_UART_C2_TCIE (6U) //!< Bit position for UART_C2_TCIE.
+#define BM_UART_C2_TCIE (0x40U) //!< Bit mask for UART_C2_TCIE.
+#define BS_UART_C2_TCIE (1U) //!< Bit field size in bits for UART_C2_TCIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C2_TCIE field.
+#define BR_UART_C2_TCIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TCIE))
+#endif
+
+//! @brief Format value for bitfield UART_C2_TCIE.
+#define BF_UART_C2_TCIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_TCIE), uint8_t) & BM_UART_C2_TCIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCIE field to a new value.
+#define BW_UART_C2_TCIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TCIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C2, field TIE[7] (RW)
+ *
+ * Enables S1[TDRE] to generate interrupt requests or DMA transfer requests,
+ * based on the state of C5[TDMAS]. If C2[TIE] and C5[TDMAS] are both set, then TCIE
+ * must be cleared, and D[D] must not be written unless servicing a DMA request.
+ *
+ * Values:
+ * - 0 - TDRE interrupt and DMA transfer requests disabled.
+ * - 1 - TDRE interrupt or DMA transfer requests enabled.
+ */
+//@{
+#define BP_UART_C2_TIE (7U) //!< Bit position for UART_C2_TIE.
+#define BM_UART_C2_TIE (0x80U) //!< Bit mask for UART_C2_TIE.
+#define BS_UART_C2_TIE (1U) //!< Bit field size in bits for UART_C2_TIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C2_TIE field.
+#define BR_UART_C2_TIE(x) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TIE))
+#endif
+
+//! @brief Format value for bitfield UART_C2_TIE.
+#define BF_UART_C2_TIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C2_TIE), uint8_t) & BM_UART_C2_TIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TIE field to a new value.
+#define BW_UART_C2_TIE(x, v) (BITBAND_ACCESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TIE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_S1 - UART Status Register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_S1 - UART Status Register 1 (RO)
+ *
+ * Reset value: 0xC0U
+ *
+ * The S1 register provides inputs to the MCU for generation of UART interrupts
+ * or DMA requests. This register can also be polled by the MCU to check the
+ * status of its fields. To clear a flag, the status register should be read followed
+ * by a read or write to D register, depending on the interrupt flag type. Other
+ * instructions can be executed between the two steps as long the handling of
+ * I/O is not compromised, but the order of operations is important for flag
+ * clearing. When a flag is configured to trigger a DMA request, assertion of the
+ * associated DMA done signal from the DMA controller clears the flag. If the
+ * condition that results in the assertion of the flag, interrupt, or DMA request is not
+ * resolved prior to clearing the flag, the flag, and interrupt/DMA request,
+ * reasserts. For example, if the DMA or interrupt service routine fails to write
+ * sufficient data to the transmit buffer to raise it above the watermark level, the
+ * flag reasserts and generates another interrupt or DMA request. Reading an
+ * empty data register to clear one of the flags of the S1 register causes the FIFO
+ * pointers to become misaligned. A receive FIFO flush reinitializes the
+ * pointers. A better way to prevent this situation is to always leave one byte in FIFO
+ * and this byte will be read eventually in clearing the flag bit.
+ */
+typedef union _hw_uart_s1
+{
+ uint8_t U;
+ struct _hw_uart_s1_bitfields
+ {
+ uint8_t PF : 1; //!< [0] Parity Error Flag
+ uint8_t FE : 1; //!< [1] Framing Error Flag
+ uint8_t NF : 1; //!< [2] Noise Flag
+ uint8_t OR : 1; //!< [3] Receiver Overrun Flag
+ uint8_t IDLE : 1; //!< [4] Idle Line Flag
+ uint8_t RDRF : 1; //!< [5] Receive Data Register Full Flag
+ uint8_t TC : 1; //!< [6] Transmit Complete Flag
+ uint8_t TDRE : 1; //!< [7] Transmit Data Register Empty Flag
+ } B;
+} hw_uart_s1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_S1 register
+ */
+//@{
+#define HW_UART_S1_ADDR(x) (REGS_UART_BASE(x) + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_S1(x) (*(__I hw_uart_s1_t *) HW_UART_S1_ADDR(x))
+#define HW_UART_S1_RD(x) (HW_UART_S1(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_S1 bitfields
+ */
+
+/*!
+ * @name Register UART_S1, field PF[0] (RO)
+ *
+ * PF is set when PE is set and the parity of the received data does not match
+ * its parity bit. The PF is not set in the case of an overrun condition. When PF
+ * is set, it indicates only that a dataword was received with parity error since
+ * the last time it was cleared. There is no guarantee that the first dataword
+ * read from the receive buffer has a parity error or that there is only one
+ * dataword in the buffer that was received with a parity error, unless the receive
+ * buffer has a depth of one. To clear PF, read S1 and then read D., S2[LBKDE] is
+ * disabled, Within the receive buffer structure the received dataword is tagged
+ * if it is received with a parity error. This information is available by reading
+ * the ED register prior to reading the D register.
+ *
+ * Values:
+ * - 0 - No parity error detected since the last time this flag was cleared. If
+ * the receive buffer has a depth greater than 1, then there may be data in
+ * the receive buffer what was received with a parity error.
+ * - 1 - At least one dataword was received with a parity error since the last
+ * time this flag was cleared.
+ */
+//@{
+#define BP_UART_S1_PF (0U) //!< Bit position for UART_S1_PF.
+#define BM_UART_S1_PF (0x01U) //!< Bit mask for UART_S1_PF.
+#define BS_UART_S1_PF (1U) //!< Bit field size in bits for UART_S1_PF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S1_PF field.
+#define BR_UART_S1_PF(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_PF))
+#endif
+//@}
+
+/*!
+ * @name Register UART_S1, field FE[1] (RO)
+ *
+ * FE is set when a logic 0 is accepted as the stop bit. When BDH[SBNS] is set,
+ * then FE will set when a logic 0 is accepted for either of the two stop bits.
+ * FE does not set in the case of an overrun or while the LIN break detect feature
+ * is enabled (S2[LBKDE] = 1). FE inhibits further data reception until it is
+ * cleared. To clear FE, read S1 with FE set and then read D. The last data in the
+ * receive buffer represents the data that was received with the frame error
+ * enabled. Framing errors are not supported when 7816E is set/enabled. However, if
+ * this flag is set, data is still not received in 7816 mode.
+ *
+ * Values:
+ * - 0 - No framing error detected.
+ * - 1 - Framing error.
+ */
+//@{
+#define BP_UART_S1_FE (1U) //!< Bit position for UART_S1_FE.
+#define BM_UART_S1_FE (0x02U) //!< Bit mask for UART_S1_FE.
+#define BS_UART_S1_FE (1U) //!< Bit field size in bits for UART_S1_FE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S1_FE field.
+#define BR_UART_S1_FE(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_FE))
+#endif
+//@}
+
+/*!
+ * @name Register UART_S1, field NF[2] (RO)
+ *
+ * NF is set when the UART detects noise on the receiver input. NF does not
+ * become set in the case of an overrun or while the LIN break detect feature is
+ * enabled (S2[LBKDE] = 1). When NF is set, it indicates only that a dataword has
+ * been received with noise since the last time it was cleared. There is no
+ * guarantee that the first dataword read from the receive buffer has noise or that there
+ * is only one dataword in the buffer that was received with noise unless the
+ * receive buffer has a depth of one. To clear NF, read S1 and then read D.
+ *
+ * Values:
+ * - 0 - No noise detected since the last time this flag was cleared. If the
+ * receive buffer has a depth greater than 1 then there may be data in the
+ * receiver buffer that was received with noise.
+ * - 1 - At least one dataword was received with noise detected since the last
+ * time the flag was cleared.
+ */
+//@{
+#define BP_UART_S1_NF (2U) //!< Bit position for UART_S1_NF.
+#define BM_UART_S1_NF (0x04U) //!< Bit mask for UART_S1_NF.
+#define BS_UART_S1_NF (1U) //!< Bit field size in bits for UART_S1_NF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S1_NF field.
+#define BR_UART_S1_NF(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_NF))
+#endif
+//@}
+
+/*!
+ * @name Register UART_S1, field OR[3] (RO)
+ *
+ * OR is set when software fails to prevent the receive data register from
+ * overflowing with data. The OR bit is set immediately after the stop bit has been
+ * completely received for the dataword that overflows the buffer and all the other
+ * error flags (FE, NF, and PF) are prevented from setting. The data in the
+ * shift register is lost, but the data already in the UART data registers is not
+ * affected. If the OR flag is set, no data is stored in the data buffer even if
+ * sufficient room exists. Additionally, while the OR flag is set, the RDRF and IDLE
+ * flags are blocked from asserting, that is, transition from an inactive to an
+ * active state. To clear OR, read S1 when OR is set and then read D. See
+ * functional description for more details regarding the operation of the OR bit.If
+ * LBKDE is enabled and a LIN Break is detected, the OR field asserts if S2[LBKDIF]
+ * is not cleared before the next data character is received. In 7816 mode, it is
+ * possible to configure a NACK to be returned by programing C7816[ONACK].
+ *
+ * Values:
+ * - 0 - No overrun has occurred since the last time the flag was cleared.
+ * - 1 - Overrun has occurred or the overrun flag has not been cleared since the
+ * last overrun occured.
+ */
+//@{
+#define BP_UART_S1_OR (3U) //!< Bit position for UART_S1_OR.
+#define BM_UART_S1_OR (0x08U) //!< Bit mask for UART_S1_OR.
+#define BS_UART_S1_OR (1U) //!< Bit field size in bits for UART_S1_OR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S1_OR field.
+#define BR_UART_S1_OR(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_OR))
+#endif
+//@}
+
+/*!
+ * @name Register UART_S1, field IDLE[4] (RO)
+ *
+ * After the IDLE flag is cleared, a frame must be received (although not
+ * necessarily stored in the data buffer, for example if C2[RWU] is set), or a LIN
+ * break character must set the S2[LBKDIF] flag before an idle condition can set the
+ * IDLE flag. To clear IDLE, read UART status S1 with IDLE set and then read D.
+ * IDLE is set when either of the following appear on the receiver input: 10
+ * consecutive logic 1s if C1[M] = 0 11 consecutive logic 1s if C1[M] = 1 and C4[M10]
+ * = 0 12 consecutive logic 1s if C1[M] = 1, C4[M10] = 1, and C1[PE] = 1 Idle
+ * detection is not supported when 7816E is set/enabled and hence this flag is
+ * ignored. When RWU is set and WAKE is cleared, an idle line condition sets the IDLE
+ * flag if RWUID is set, else the IDLE flag does not become set.
+ *
+ * Values:
+ * - 0 - Receiver input is either active now or has never become active since
+ * the IDLE flag was last cleared.
+ * - 1 - Receiver input has become idle or the flag has not been cleared since
+ * it last asserted.
+ */
+//@{
+#define BP_UART_S1_IDLE (4U) //!< Bit position for UART_S1_IDLE.
+#define BM_UART_S1_IDLE (0x10U) //!< Bit mask for UART_S1_IDLE.
+#define BS_UART_S1_IDLE (1U) //!< Bit field size in bits for UART_S1_IDLE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S1_IDLE field.
+#define BR_UART_S1_IDLE(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_IDLE))
+#endif
+//@}
+
+/*!
+ * @name Register UART_S1, field RDRF[5] (RO)
+ *
+ * RDRF is set when the number of datawords in the receive buffer is equal to or
+ * more than the number indicated by RWFIFO[RXWATER]. A dataword that is in the
+ * process of being received is not included in the count. To clear RDRF, read S1
+ * when RDRF is set and then read D. For more efficient interrupt and DMA
+ * operation, read all data except the final value from the buffer, using D/C3[T8]/ED.
+ * Then read S1 and the final data value, resulting in the clearing of the RDRF
+ * flag. Even if RDRF is set, data will continue to be received until an overrun
+ * condition occurs.RDRF is prevented from setting while S2[LBKDE] is set.
+ * Additionally, when S2[LBKDE] is set, the received datawords are stored in the receive
+ * buffer but over-write each other.
+ *
+ * Values:
+ * - 0 - The number of datawords in the receive buffer is less than the number
+ * indicated by RXWATER.
+ * - 1 - The number of datawords in the receive buffer is equal to or greater
+ * than the number indicated by RXWATER at some point in time since this flag
+ * was last cleared.
+ */
+//@{
+#define BP_UART_S1_RDRF (5U) //!< Bit position for UART_S1_RDRF.
+#define BM_UART_S1_RDRF (0x20U) //!< Bit mask for UART_S1_RDRF.
+#define BS_UART_S1_RDRF (1U) //!< Bit field size in bits for UART_S1_RDRF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S1_RDRF field.
+#define BR_UART_S1_RDRF(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_RDRF))
+#endif
+//@}
+
+/*!
+ * @name Register UART_S1, field TC[6] (RO)
+ *
+ * TC is set when the transmit buffer is empty and no data, preamble, or break
+ * character is being transmitted. When TC is set, the transmit data output signal
+ * becomes idle (logic 1). TC is cleared by reading S1 with TC set and then
+ * doing one of the following: When C7816[ISO_7816E] is set/enabled, this field is
+ * set after any NACK signal has been received, but prior to any corresponding
+ * guard times expiring. Writing to D to transmit new data. Queuing a preamble by
+ * clearing and then setting C2[TE]. Queuing a break character by writing 1 to SBK
+ * in C2.
+ *
+ * Values:
+ * - 0 - Transmitter active (sending data, a preamble, or a break).
+ * - 1 - Transmitter idle (transmission activity complete).
+ */
+//@{
+#define BP_UART_S1_TC (6U) //!< Bit position for UART_S1_TC.
+#define BM_UART_S1_TC (0x40U) //!< Bit mask for UART_S1_TC.
+#define BS_UART_S1_TC (1U) //!< Bit field size in bits for UART_S1_TC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S1_TC field.
+#define BR_UART_S1_TC(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_TC))
+#endif
+//@}
+
+/*!
+ * @name Register UART_S1, field TDRE[7] (RO)
+ *
+ * TDRE will set when the number of datawords in the transmit buffer (D and
+ * C3[T8])is equal to or less than the number indicated by TWFIFO[TXWATER]. A
+ * character that is in the process of being transmitted is not included in the count.
+ * To clear TDRE, read S1 when TDRE is set and then write to the UART data
+ * register (D). For more efficient interrupt servicing, all data except the final value
+ * to be written to the buffer must be written to D/C3[T8]. Then S1 can be read
+ * before writing the final data value, resulting in the clearing of the TRDE
+ * flag. This is more efficient because the TDRE reasserts until the watermark has
+ * been exceeded. So, attempting to clear the TDRE with every write will be
+ * ineffective until sufficient data has been written.
+ *
+ * Values:
+ * - 0 - The amount of data in the transmit buffer is greater than the value
+ * indicated by TWFIFO[TXWATER].
+ * - 1 - The amount of data in the transmit buffer is less than or equal to the
+ * value indicated by TWFIFO[TXWATER] at some point in time since the flag
+ * has been cleared.
+ */
+//@{
+#define BP_UART_S1_TDRE (7U) //!< Bit position for UART_S1_TDRE.
+#define BM_UART_S1_TDRE (0x80U) //!< Bit mask for UART_S1_TDRE.
+#define BS_UART_S1_TDRE (1U) //!< Bit field size in bits for UART_S1_TDRE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S1_TDRE field.
+#define BR_UART_S1_TDRE(x) (BITBAND_ACCESS8(HW_UART_S1_ADDR(x), BP_UART_S1_TDRE))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_S2 - UART Status Register 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_S2 - UART Status Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The S2 register provides inputs to the MCU for generation of UART interrupts
+ * or DMA requests. Also, this register can be polled by the MCU to check the
+ * status of these bits. This register can be read or written at any time, with the
+ * exception of the MSBF and RXINV bits, which should be changed by the user only
+ * between transmit and receive packets.
+ */
+typedef union _hw_uart_s2
+{
+ uint8_t U;
+ struct _hw_uart_s2_bitfields
+ {
+ uint8_t RAF : 1; //!< [0] Receiver Active Flag
+ uint8_t LBKDE : 1; //!< [1] LIN Break Detection Enable
+ uint8_t BRK13 : 1; //!< [2] Break Transmit Character Length
+ uint8_t RWUID : 1; //!< [3] Receive Wakeup Idle Detect
+ uint8_t RXINV : 1; //!< [4] Receive Data Inversion
+ uint8_t MSBF : 1; //!< [5] Most Significant Bit First
+ uint8_t RXEDGIF : 1; //!< [6] RxD Pin Active Edge Interrupt Flag
+ uint8_t LBKDIF : 1; //!< [7] LIN Break Detect Interrupt Flag
+ } B;
+} hw_uart_s2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_S2 register
+ */
+//@{
+#define HW_UART_S2_ADDR(x) (REGS_UART_BASE(x) + 0x5U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_S2(x) (*(__IO hw_uart_s2_t *) HW_UART_S2_ADDR(x))
+#define HW_UART_S2_RD(x) (HW_UART_S2(x).U)
+#define HW_UART_S2_WR(x, v) (HW_UART_S2(x).U = (v))
+#define HW_UART_S2_SET(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) | (v)))
+#define HW_UART_S2_CLR(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) & ~(v)))
+#define HW_UART_S2_TOG(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_S2 bitfields
+ */
+
+/*!
+ * @name Register UART_S2, field RAF[0] (RO)
+ *
+ * RAF is set when the UART receiver detects a logic 0 during the RT1 time
+ * period of the start bit search. RAF is cleared when the receiver detects an idle
+ * character when C7816[ISO7816E] is cleared/disabled. When C7816[ISO7816E] is
+ * enabled, the RAF is cleared if the C7816[TTYPE] = 0 expires or the C7816[TTYPE] =
+ * 1 expires.In case C7816[ISO7816E] is set and C7816[TTYPE] = 0, it is possible
+ * to configure the guard time to 12. However, if a NACK is required to be
+ * transmitted, the data transfer actually takes 13 ETU with the 13th ETU slot being a
+ * inactive buffer. Therefore, in this situation, the RAF may deassert one ETU
+ * prior to actually being inactive.
+ *
+ * Values:
+ * - 0 - UART receiver idle/inactive waiting for a start bit.
+ * - 1 - UART receiver active, RxD input not idle.
+ */
+//@{
+#define BP_UART_S2_RAF (0U) //!< Bit position for UART_S2_RAF.
+#define BM_UART_S2_RAF (0x01U) //!< Bit mask for UART_S2_RAF.
+#define BS_UART_S2_RAF (1U) //!< Bit field size in bits for UART_S2_RAF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S2_RAF field.
+#define BR_UART_S2_RAF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RAF))
+#endif
+//@}
+
+/*!
+ * @name Register UART_S2, field LBKDE[1] (RW)
+ *
+ * Enables the LIN Break detection feature. While LBKDE is set, S1[RDRF],
+ * S1[NF], S1[FE], and S1[PF] are prevented from setting. When LBKDE is set, see .
+ * Overrun operation LBKDE must be cleared when C7816[ISO7816E] is set.
+ *
+ * Values:
+ * - 0 - Break character detection is disabled.
+ * - 1 - Break character is detected at length of 11 bit times if C1[M] = 0 or
+ * 12 bits time if C1[M] = 1.
+ */
+//@{
+#define BP_UART_S2_LBKDE (1U) //!< Bit position for UART_S2_LBKDE.
+#define BM_UART_S2_LBKDE (0x02U) //!< Bit mask for UART_S2_LBKDE.
+#define BS_UART_S2_LBKDE (1U) //!< Bit field size in bits for UART_S2_LBKDE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S2_LBKDE field.
+#define BR_UART_S2_LBKDE(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDE))
+#endif
+
+//! @brief Format value for bitfield UART_S2_LBKDE.
+#define BF_UART_S2_LBKDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_LBKDE), uint8_t) & BM_UART_S2_LBKDE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LBKDE field to a new value.
+#define BW_UART_S2_LBKDE(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_S2, field BRK13[2] (RW)
+ *
+ * Determines whether the transmit break character is 10, 11, or 12 bits long,
+ * or 13 or 14 bits long. See for the length of the break character for the
+ * different configurations. The detection of a framing error is not affected by this
+ * field. Transmitting break characters
+ *
+ * Values:
+ * - 0 - Break character is 10, 11, or 12 bits long.
+ * - 1 - Break character is 13 or 14 bits long.
+ */
+//@{
+#define BP_UART_S2_BRK13 (2U) //!< Bit position for UART_S2_BRK13.
+#define BM_UART_S2_BRK13 (0x04U) //!< Bit mask for UART_S2_BRK13.
+#define BS_UART_S2_BRK13 (1U) //!< Bit field size in bits for UART_S2_BRK13.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S2_BRK13 field.
+#define BR_UART_S2_BRK13(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_BRK13))
+#endif
+
+//! @brief Format value for bitfield UART_S2_BRK13.
+#define BF_UART_S2_BRK13(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_BRK13), uint8_t) & BM_UART_S2_BRK13)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BRK13 field to a new value.
+#define BW_UART_S2_BRK13(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_BRK13) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_S2, field RWUID[3] (RW)
+ *
+ * When RWU is set and WAKE is cleared, this field controls whether the idle
+ * character that wakes the receiver sets S1[IDLE]. This field must be cleared when
+ * C7816[ISO7816E] is set/enabled.
+ *
+ * Values:
+ * - 0 - S1[IDLE] is not set upon detection of an idle character.
+ * - 1 - S1[IDLE] is set upon detection of an idle character.
+ */
+//@{
+#define BP_UART_S2_RWUID (3U) //!< Bit position for UART_S2_RWUID.
+#define BM_UART_S2_RWUID (0x08U) //!< Bit mask for UART_S2_RWUID.
+#define BS_UART_S2_RWUID (1U) //!< Bit field size in bits for UART_S2_RWUID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S2_RWUID field.
+#define BR_UART_S2_RWUID(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RWUID))
+#endif
+
+//! @brief Format value for bitfield UART_S2_RWUID.
+#define BF_UART_S2_RWUID(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_RWUID), uint8_t) & BM_UART_S2_RWUID)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RWUID field to a new value.
+#define BW_UART_S2_RWUID(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RWUID) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_S2, field RXINV[4] (RW)
+ *
+ * Setting this field reverses the polarity of the received data input. In NRZ
+ * format, a one is represented by a mark and a zero is represented by a space for
+ * normal polarity, and the opposite for inverted polarity. In IrDA format, a
+ * zero is represented by short high pulse in the middle of a bit time remaining
+ * idle low for a one for normal polarity. A zero is represented by a short low
+ * pulse in the middle of a bit time remaining idle high for a one for inverted
+ * polarity. This field is automatically set when C7816[INIT] and C7816[ISO7816E] are
+ * enabled and an initial character is detected in T = 0 protocol mode. Setting
+ * RXINV inverts the RxD input for data bits, start and stop bits, break, and
+ * idle. When C7816[ISO7816E] is set/enabled, only the data bits and the parity bit
+ * are inverted.
+ *
+ * Values:
+ * - 0 - Receive data is not inverted.
+ * - 1 - Receive data is inverted.
+ */
+//@{
+#define BP_UART_S2_RXINV (4U) //!< Bit position for UART_S2_RXINV.
+#define BM_UART_S2_RXINV (0x10U) //!< Bit mask for UART_S2_RXINV.
+#define BS_UART_S2_RXINV (1U) //!< Bit field size in bits for UART_S2_RXINV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S2_RXINV field.
+#define BR_UART_S2_RXINV(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXINV))
+#endif
+
+//! @brief Format value for bitfield UART_S2_RXINV.
+#define BF_UART_S2_RXINV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_RXINV), uint8_t) & BM_UART_S2_RXINV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXINV field to a new value.
+#define BW_UART_S2_RXINV(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXINV) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_S2, field MSBF[5] (RW)
+ *
+ * Setting this field reverses the order of the bits that are transmitted and
+ * received on the wire. This field does not affect the polarity of the bits, the
+ * location of the parity bit, or the location of the start or stop bits. This
+ * field is automatically set when C7816[INIT] and C7816[ISO7816E] are enabled and
+ * an initial character is detected in T = 0 protocol mode.
+ *
+ * Values:
+ * - 0 - LSB (bit0) is the first bit that is transmitted following the start
+ * bit. Further, the first bit received after the start bit is identified as
+ * bit0.
+ * - 1 - MSB (bit8, bit7 or bit6) is the first bit that is transmitted following
+ * the start bit, depending on the setting of C1[M] and C1[PE]. Further, the
+ * first bit received after the start bit is identified as bit8, bit7, or
+ * bit6, depending on the setting of C1[M] and C1[PE].
+ */
+//@{
+#define BP_UART_S2_MSBF (5U) //!< Bit position for UART_S2_MSBF.
+#define BM_UART_S2_MSBF (0x20U) //!< Bit mask for UART_S2_MSBF.
+#define BS_UART_S2_MSBF (1U) //!< Bit field size in bits for UART_S2_MSBF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S2_MSBF field.
+#define BR_UART_S2_MSBF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_MSBF))
+#endif
+
+//! @brief Format value for bitfield UART_S2_MSBF.
+#define BF_UART_S2_MSBF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_MSBF), uint8_t) & BM_UART_S2_MSBF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MSBF field to a new value.
+#define BW_UART_S2_MSBF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_MSBF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_S2, field RXEDGIF[6] (W1C)
+ *
+ * RXEDGIF is set when an active edge occurs on the RxD pin. The active edge is
+ * falling if RXINV = 0, and rising if RXINV=1. RXEDGIF is cleared by writing a 1
+ * to it. See for additional details. RXEDGIF description The active edge is
+ * detected only in two wire mode and on receiving data coming from the RxD pin.
+ *
+ * Values:
+ * - 0 - No active edge on the receive pin has occurred.
+ * - 1 - An active edge on the receive pin has occurred.
+ */
+//@{
+#define BP_UART_S2_RXEDGIF (6U) //!< Bit position for UART_S2_RXEDGIF.
+#define BM_UART_S2_RXEDGIF (0x40U) //!< Bit mask for UART_S2_RXEDGIF.
+#define BS_UART_S2_RXEDGIF (1U) //!< Bit field size in bits for UART_S2_RXEDGIF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S2_RXEDGIF field.
+#define BR_UART_S2_RXEDGIF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXEDGIF))
+#endif
+
+//! @brief Format value for bitfield UART_S2_RXEDGIF.
+#define BF_UART_S2_RXEDGIF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_RXEDGIF), uint8_t) & BM_UART_S2_RXEDGIF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXEDGIF field to a new value.
+#define BW_UART_S2_RXEDGIF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXEDGIF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_S2, field LBKDIF[7] (W1C)
+ *
+ * LBKDIF is set when LBKDE is set and a LIN break character is detected on the
+ * receiver input. The LIN break characters are 11 consecutive logic 0s if C1[M]
+ * = 0 or 12 consecutive logic 0s if C1[M] = 1. LBKDIF is set after receiving the
+ * last LIN break character. LBKDIF is cleared by writing a 1 to it.
+ *
+ * Values:
+ * - 0 - No LIN break character detected.
+ * - 1 - LIN break character detected.
+ */
+//@{
+#define BP_UART_S2_LBKDIF (7U) //!< Bit position for UART_S2_LBKDIF.
+#define BM_UART_S2_LBKDIF (0x80U) //!< Bit mask for UART_S2_LBKDIF.
+#define BS_UART_S2_LBKDIF (1U) //!< Bit field size in bits for UART_S2_LBKDIF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_S2_LBKDIF field.
+#define BR_UART_S2_LBKDIF(x) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDIF))
+#endif
+
+//! @brief Format value for bitfield UART_S2_LBKDIF.
+#define BF_UART_S2_LBKDIF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_S2_LBKDIF), uint8_t) & BM_UART_S2_LBKDIF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LBKDIF field to a new value.
+#define BW_UART_S2_LBKDIF(x, v) (BITBAND_ACCESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDIF) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_C3 - UART Control Register 3
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_C3 - UART Control Register 3 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Writing R8 does not have any effect. TXDIR and TXINV can be changed only
+ * between transmit and receive packets.
+ */
+typedef union _hw_uart_c3
+{
+ uint8_t U;
+ struct _hw_uart_c3_bitfields
+ {
+ uint8_t PEIE : 1; //!< [0] Parity Error Interrupt Enable
+ uint8_t FEIE : 1; //!< [1] Framing Error Interrupt Enable
+ uint8_t NEIE : 1; //!< [2] Noise Error Interrupt Enable
+ uint8_t ORIE : 1; //!< [3] Overrun Error Interrupt Enable
+ uint8_t TXINV : 1; //!< [4] Transmit Data Inversion.
+ uint8_t TXDIR : 1; //!< [5] Transmitter Pin Data Direction in
+ //! Single-Wire mode
+ uint8_t T8 : 1; //!< [6] Transmit Bit 8
+ uint8_t R8 : 1; //!< [7] Received Bit 8
+ } B;
+} hw_uart_c3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_C3 register
+ */
+//@{
+#define HW_UART_C3_ADDR(x) (REGS_UART_BASE(x) + 0x6U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_C3(x) (*(__IO hw_uart_c3_t *) HW_UART_C3_ADDR(x))
+#define HW_UART_C3_RD(x) (HW_UART_C3(x).U)
+#define HW_UART_C3_WR(x, v) (HW_UART_C3(x).U = (v))
+#define HW_UART_C3_SET(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) | (v)))
+#define HW_UART_C3_CLR(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) & ~(v)))
+#define HW_UART_C3_TOG(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_C3 bitfields
+ */
+
+/*!
+ * @name Register UART_C3, field PEIE[0] (RW)
+ *
+ * Enables the parity error flag, S1[PF], to generate interrupt requests.
+ *
+ * Values:
+ * - 0 - PF interrupt requests are disabled.
+ * - 1 - PF interrupt requests are enabled.
+ */
+//@{
+#define BP_UART_C3_PEIE (0U) //!< Bit position for UART_C3_PEIE.
+#define BM_UART_C3_PEIE (0x01U) //!< Bit mask for UART_C3_PEIE.
+#define BS_UART_C3_PEIE (1U) //!< Bit field size in bits for UART_C3_PEIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C3_PEIE field.
+#define BR_UART_C3_PEIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_PEIE))
+#endif
+
+//! @brief Format value for bitfield UART_C3_PEIE.
+#define BF_UART_C3_PEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_PEIE), uint8_t) & BM_UART_C3_PEIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PEIE field to a new value.
+#define BW_UART_C3_PEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_PEIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C3, field FEIE[1] (RW)
+ *
+ * Enables the framing error flag, S1[FE], to generate interrupt requests.
+ *
+ * Values:
+ * - 0 - FE interrupt requests are disabled.
+ * - 1 - FE interrupt requests are enabled.
+ */
+//@{
+#define BP_UART_C3_FEIE (1U) //!< Bit position for UART_C3_FEIE.
+#define BM_UART_C3_FEIE (0x02U) //!< Bit mask for UART_C3_FEIE.
+#define BS_UART_C3_FEIE (1U) //!< Bit field size in bits for UART_C3_FEIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C3_FEIE field.
+#define BR_UART_C3_FEIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_FEIE))
+#endif
+
+//! @brief Format value for bitfield UART_C3_FEIE.
+#define BF_UART_C3_FEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_FEIE), uint8_t) & BM_UART_C3_FEIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FEIE field to a new value.
+#define BW_UART_C3_FEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_FEIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C3, field NEIE[2] (RW)
+ *
+ * Enables the noise flag, S1[NF], to generate interrupt requests.
+ *
+ * Values:
+ * - 0 - NF interrupt requests are disabled.
+ * - 1 - NF interrupt requests are enabled.
+ */
+//@{
+#define BP_UART_C3_NEIE (2U) //!< Bit position for UART_C3_NEIE.
+#define BM_UART_C3_NEIE (0x04U) //!< Bit mask for UART_C3_NEIE.
+#define BS_UART_C3_NEIE (1U) //!< Bit field size in bits for UART_C3_NEIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C3_NEIE field.
+#define BR_UART_C3_NEIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_NEIE))
+#endif
+
+//! @brief Format value for bitfield UART_C3_NEIE.
+#define BF_UART_C3_NEIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_NEIE), uint8_t) & BM_UART_C3_NEIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the NEIE field to a new value.
+#define BW_UART_C3_NEIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_NEIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C3, field ORIE[3] (RW)
+ *
+ * Enables the overrun error flag, S1[OR], to generate interrupt requests.
+ *
+ * Values:
+ * - 0 - OR interrupts are disabled.
+ * - 1 - OR interrupt requests are enabled.
+ */
+//@{
+#define BP_UART_C3_ORIE (3U) //!< Bit position for UART_C3_ORIE.
+#define BM_UART_C3_ORIE (0x08U) //!< Bit mask for UART_C3_ORIE.
+#define BS_UART_C3_ORIE (1U) //!< Bit field size in bits for UART_C3_ORIE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C3_ORIE field.
+#define BR_UART_C3_ORIE(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_ORIE))
+#endif
+
+//! @brief Format value for bitfield UART_C3_ORIE.
+#define BF_UART_C3_ORIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_ORIE), uint8_t) & BM_UART_C3_ORIE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ORIE field to a new value.
+#define BW_UART_C3_ORIE(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_ORIE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C3, field TXINV[4] (RW)
+ *
+ * Setting this field reverses the polarity of the transmitted data output. In
+ * NRZ format, a one is represented by a mark and a zero is represented by a space
+ * for normal polarity, and the opposite for inverted polarity. In IrDA format,
+ * a zero is represented by short high pulse in the middle of a bit time
+ * remaining idle low for a one for normal polarity, and a zero is represented by short
+ * low pulse in the middle of a bit time remaining idle high for a one for
+ * inverted polarity. This field is automatically set when C7816[INIT] and
+ * C7816[ISO7816E] are enabled and an initial character is detected in T = 0 protocol mode.
+ * Setting TXINV inverts all transmitted values, including idle, break, start, and
+ * stop bits. In loop mode, if TXINV is set, the receiver gets the transmit
+ * inversion bit when RXINV is disabled. When C7816[ISO7816E] is set/enabled then only
+ * the transmitted data bits and parity bit are inverted.
+ *
+ * Values:
+ * - 0 - Transmit data is not inverted.
+ * - 1 - Transmit data is inverted.
+ */
+//@{
+#define BP_UART_C3_TXINV (4U) //!< Bit position for UART_C3_TXINV.
+#define BM_UART_C3_TXINV (0x10U) //!< Bit mask for UART_C3_TXINV.
+#define BS_UART_C3_TXINV (1U) //!< Bit field size in bits for UART_C3_TXINV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C3_TXINV field.
+#define BR_UART_C3_TXINV(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXINV))
+#endif
+
+//! @brief Format value for bitfield UART_C3_TXINV.
+#define BF_UART_C3_TXINV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_TXINV), uint8_t) & BM_UART_C3_TXINV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXINV field to a new value.
+#define BW_UART_C3_TXINV(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXINV) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C3, field TXDIR[5] (RW)
+ *
+ * Determines whether the TXD pin is used as an input or output in the
+ * single-wire mode of operation. This field is relevant only to the single wire mode.
+ * When C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 1, this field is
+ * automatically cleared after the requested block is transmitted. This condition is
+ * detected when TL7816[TLEN] = 0 and 4 additional characters are transmitted.
+ * Additionally, if C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 0 and a NACK is
+ * being transmitted, the hardware automatically overrides this field as needed. In
+ * this situation, TXDIR does not reflect the temporary state associated with
+ * the NACK.
+ *
+ * Values:
+ * - 0 - TXD pin is an input in single wire mode.
+ * - 1 - TXD pin is an output in single wire mode.
+ */
+//@{
+#define BP_UART_C3_TXDIR (5U) //!< Bit position for UART_C3_TXDIR.
+#define BM_UART_C3_TXDIR (0x20U) //!< Bit mask for UART_C3_TXDIR.
+#define BS_UART_C3_TXDIR (1U) //!< Bit field size in bits for UART_C3_TXDIR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C3_TXDIR field.
+#define BR_UART_C3_TXDIR(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXDIR))
+#endif
+
+//! @brief Format value for bitfield UART_C3_TXDIR.
+#define BF_UART_C3_TXDIR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_TXDIR), uint8_t) & BM_UART_C3_TXDIR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXDIR field to a new value.
+#define BW_UART_C3_TXDIR(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXDIR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C3, field T8[6] (RW)
+ *
+ * T8 is the ninth data bit transmitted when the UART is configured for 9-bit
+ * data format, that is, if C1[M] = 1 or C4[M10] = 1. If the value of T8 is the
+ * same as in the previous transmission, T8 does not have to be rewritten. The same
+ * value is transmitted until T8 is rewritten. To correctly transmit the 9th bit,
+ * write UARTx_C3[T8] to the desired value, then write the UARTx_D register with
+ * the remaining data.
+ */
+//@{
+#define BP_UART_C3_T8 (6U) //!< Bit position for UART_C3_T8.
+#define BM_UART_C3_T8 (0x40U) //!< Bit mask for UART_C3_T8.
+#define BS_UART_C3_T8 (1U) //!< Bit field size in bits for UART_C3_T8.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C3_T8 field.
+#define BR_UART_C3_T8(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_T8))
+#endif
+
+//! @brief Format value for bitfield UART_C3_T8.
+#define BF_UART_C3_T8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C3_T8), uint8_t) & BM_UART_C3_T8)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the T8 field to a new value.
+#define BW_UART_C3_T8(x, v) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_T8) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C3, field R8[7] (RO)
+ *
+ * R8 is the ninth data bit received when the UART is configured for 9-bit data
+ * format, that is, if C1[M] = 1 or C4[M10] = 1. The R8 value corresponds to the
+ * current data value in the UARTx_D register. To read the 9th bit, read the
+ * value of UARTx_C3[R8], then read the UARTx_D register.
+ */
+//@{
+#define BP_UART_C3_R8 (7U) //!< Bit position for UART_C3_R8.
+#define BM_UART_C3_R8 (0x80U) //!< Bit mask for UART_C3_R8.
+#define BS_UART_C3_R8 (1U) //!< Bit field size in bits for UART_C3_R8.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C3_R8 field.
+#define BR_UART_C3_R8(x) (BITBAND_ACCESS8(HW_UART_C3_ADDR(x), BP_UART_C3_R8))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_D - UART Data Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_D - UART Data Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is actually two separate registers. Reads return the contents
+ * of the read-only receive data register and writes go to the write-only transmit
+ * data register. In 8-bit or 9-bit data format, only UART data register (D)
+ * needs to be accessed to clear the S1[RDRF] bit (assuming receiver buffer level is
+ * less than RWFIFO[RXWATER]). The C3 register needs to be read, prior to the D
+ * register, only if the ninth bit of data needs to be captured. Similarly, the
+ * ED register needs to be read, prior to the D register, only if the additional
+ * flag data for the dataword needs to be captured. In the normal 8-bit mode (M
+ * bit cleared) if the parity is enabled, you get seven data bits and one parity
+ * bit. That one parity bit is loaded into the D register. So, for the data bits,
+ * mask off the parity bit from the value you read out of this register. When
+ * transmitting in 9-bit data format and using 8-bit write instructions, write first
+ * to transmit bit 8 in UART control register 3 (C3[T8]), then D. A write to
+ * C3[T8] stores the data in a temporary register. If D register is written first,
+ * and then the new data on data bus is stored in D, the temporary value written by
+ * the last write to C3[T8] gets stored in the C3[T8] register.
+ */
+typedef union _hw_uart_d
+{
+ uint8_t U;
+ struct _hw_uart_d_bitfields
+ {
+ uint8_t RT : 8; //!< [7:0]
+ } B;
+} hw_uart_d_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_D register
+ */
+//@{
+#define HW_UART_D_ADDR(x) (REGS_UART_BASE(x) + 0x7U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_D(x) (*(__IO hw_uart_d_t *) HW_UART_D_ADDR(x))
+#define HW_UART_D_RD(x) (HW_UART_D(x).U)
+#define HW_UART_D_WR(x, v) (HW_UART_D(x).U = (v))
+#define HW_UART_D_SET(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) | (v)))
+#define HW_UART_D_CLR(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) & ~(v)))
+#define HW_UART_D_TOG(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_D bitfields
+ */
+
+/*!
+ * @name Register UART_D, field RT[7:0] (RW)
+ *
+ * Reads return the contents of the read-only receive data register and writes
+ * go to the write-only transmit data register.
+ */
+//@{
+#define BP_UART_D_RT (0U) //!< Bit position for UART_D_RT.
+#define BM_UART_D_RT (0xFFU) //!< Bit mask for UART_D_RT.
+#define BS_UART_D_RT (8U) //!< Bit field size in bits for UART_D_RT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_D_RT field.
+#define BR_UART_D_RT(x) (HW_UART_D(x).U)
+#endif
+
+//! @brief Format value for bitfield UART_D_RT.
+#define BF_UART_D_RT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_D_RT), uint8_t) & BM_UART_D_RT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RT field to a new value.
+#define BW_UART_D_RT(x, v) (HW_UART_D_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_MA1 - UART Match Address Registers 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_MA1 - UART Match Address Registers 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The MA1 and MA2 registers are compared to input data addresses when the most
+ * significant bit is set and the associated C4[MAEN] field is set. If a match
+ * occurs, the following data is transferred to the data register. If a match
+ * fails, the following data is discarded. These registers can be read and written at
+ * anytime.
+ */
+typedef union _hw_uart_ma1
+{
+ uint8_t U;
+ struct _hw_uart_ma1_bitfields
+ {
+ uint8_t MA : 8; //!< [7:0] Match Address
+ } B;
+} hw_uart_ma1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_MA1 register
+ */
+//@{
+#define HW_UART_MA1_ADDR(x) (REGS_UART_BASE(x) + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_MA1(x) (*(__IO hw_uart_ma1_t *) HW_UART_MA1_ADDR(x))
+#define HW_UART_MA1_RD(x) (HW_UART_MA1(x).U)
+#define HW_UART_MA1_WR(x, v) (HW_UART_MA1(x).U = (v))
+#define HW_UART_MA1_SET(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) | (v)))
+#define HW_UART_MA1_CLR(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) & ~(v)))
+#define HW_UART_MA1_TOG(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_MA1 bitfields
+ */
+
+/*!
+ * @name Register UART_MA1, field MA[7:0] (RW)
+ */
+//@{
+#define BP_UART_MA1_MA (0U) //!< Bit position for UART_MA1_MA.
+#define BM_UART_MA1_MA (0xFFU) //!< Bit mask for UART_MA1_MA.
+#define BS_UART_MA1_MA (8U) //!< Bit field size in bits for UART_MA1_MA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_MA1_MA field.
+#define BR_UART_MA1_MA(x) (HW_UART_MA1(x).U)
+#endif
+
+//! @brief Format value for bitfield UART_MA1_MA.
+#define BF_UART_MA1_MA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MA1_MA), uint8_t) & BM_UART_MA1_MA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MA field to a new value.
+#define BW_UART_MA1_MA(x, v) (HW_UART_MA1_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_MA2 - UART Match Address Registers 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_MA2 - UART Match Address Registers 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * These registers can be read and written at anytime. The MA1 and MA2 registers
+ * are compared to input data addresses when the most significant bit is set and
+ * the associated C4[MAEN] field is set. If a match occurs, the following data
+ * is transferred to the data register. If a match fails, the following data is
+ * discarded.
+ */
+typedef union _hw_uart_ma2
+{
+ uint8_t U;
+ struct _hw_uart_ma2_bitfields
+ {
+ uint8_t MA : 8; //!< [7:0] Match Address
+ } B;
+} hw_uart_ma2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_MA2 register
+ */
+//@{
+#define HW_UART_MA2_ADDR(x) (REGS_UART_BASE(x) + 0x9U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_MA2(x) (*(__IO hw_uart_ma2_t *) HW_UART_MA2_ADDR(x))
+#define HW_UART_MA2_RD(x) (HW_UART_MA2(x).U)
+#define HW_UART_MA2_WR(x, v) (HW_UART_MA2(x).U = (v))
+#define HW_UART_MA2_SET(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) | (v)))
+#define HW_UART_MA2_CLR(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) & ~(v)))
+#define HW_UART_MA2_TOG(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_MA2 bitfields
+ */
+
+/*!
+ * @name Register UART_MA2, field MA[7:0] (RW)
+ */
+//@{
+#define BP_UART_MA2_MA (0U) //!< Bit position for UART_MA2_MA.
+#define BM_UART_MA2_MA (0xFFU) //!< Bit mask for UART_MA2_MA.
+#define BS_UART_MA2_MA (8U) //!< Bit field size in bits for UART_MA2_MA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_MA2_MA field.
+#define BR_UART_MA2_MA(x) (HW_UART_MA2(x).U)
+#endif
+
+//! @brief Format value for bitfield UART_MA2_MA.
+#define BF_UART_MA2_MA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MA2_MA), uint8_t) & BM_UART_MA2_MA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MA field to a new value.
+#define BW_UART_MA2_MA(x, v) (HW_UART_MA2_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_C4 - UART Control Register 4
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_C4 - UART Control Register 4 (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_uart_c4
+{
+ uint8_t U;
+ struct _hw_uart_c4_bitfields
+ {
+ uint8_t BRFA : 5; //!< [4:0] Baud Rate Fine Adjust
+ uint8_t M10 : 1; //!< [5] 10-bit Mode select
+ uint8_t MAEN2 : 1; //!< [6] Match Address Mode Enable 2
+ uint8_t MAEN1 : 1; //!< [7] Match Address Mode Enable 1
+ } B;
+} hw_uart_c4_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_C4 register
+ */
+//@{
+#define HW_UART_C4_ADDR(x) (REGS_UART_BASE(x) + 0xAU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_C4(x) (*(__IO hw_uart_c4_t *) HW_UART_C4_ADDR(x))
+#define HW_UART_C4_RD(x) (HW_UART_C4(x).U)
+#define HW_UART_C4_WR(x, v) (HW_UART_C4(x).U = (v))
+#define HW_UART_C4_SET(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) | (v)))
+#define HW_UART_C4_CLR(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) & ~(v)))
+#define HW_UART_C4_TOG(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_C4 bitfields
+ */
+
+/*!
+ * @name Register UART_C4, field BRFA[4:0] (RW)
+ *
+ * This bit field is used to add more timing resolution to the average baud
+ * frequency, in increments of 1/32. See Baud rate generation for more information.
+ */
+//@{
+#define BP_UART_C4_BRFA (0U) //!< Bit position for UART_C4_BRFA.
+#define BM_UART_C4_BRFA (0x1FU) //!< Bit mask for UART_C4_BRFA.
+#define BS_UART_C4_BRFA (5U) //!< Bit field size in bits for UART_C4_BRFA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C4_BRFA field.
+#define BR_UART_C4_BRFA(x) (HW_UART_C4(x).B.BRFA)
+#endif
+
+//! @brief Format value for bitfield UART_C4_BRFA.
+#define BF_UART_C4_BRFA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C4_BRFA), uint8_t) & BM_UART_C4_BRFA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BRFA field to a new value.
+#define BW_UART_C4_BRFA(x, v) (HW_UART_C4_WR(x, (HW_UART_C4_RD(x) & ~BM_UART_C4_BRFA) | BF_UART_C4_BRFA(v)))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C4, field M10[5] (RW)
+ *
+ * Causes a tenth, non-memory mapped bit to be part of the serial transmission.
+ * This tenth bit is generated and interpreted as a parity bit. The M10 field
+ * does not affect the LIN send or detect break behavior. If M10 is set, then both
+ * C1[M] and C1[PE] must also be set. This field must be cleared when
+ * C7816[ISO7816E] is set/enabled. See Data format (non ISO-7816) for more information.
+ *
+ * Values:
+ * - 0 - The parity bit is the ninth bit in the serial transmission.
+ * - 1 - The parity bit is the tenth bit in the serial transmission.
+ */
+//@{
+#define BP_UART_C4_M10 (5U) //!< Bit position for UART_C4_M10.
+#define BM_UART_C4_M10 (0x20U) //!< Bit mask for UART_C4_M10.
+#define BS_UART_C4_M10 (1U) //!< Bit field size in bits for UART_C4_M10.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C4_M10 field.
+#define BR_UART_C4_M10(x) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_M10))
+#endif
+
+//! @brief Format value for bitfield UART_C4_M10.
+#define BF_UART_C4_M10(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C4_M10), uint8_t) & BM_UART_C4_M10)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the M10 field to a new value.
+#define BW_UART_C4_M10(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_M10) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C4, field MAEN2[6] (RW)
+ *
+ * See Match address operation for more information.
+ *
+ * Values:
+ * - 0 - All data received is transferred to the data buffer if MAEN1 is cleared.
+ * - 1 - All data received with the most significant bit cleared, is discarded.
+ * All data received with the most significant bit set, is compared with
+ * contents of MA2 register. If no match occurs, the data is discarded. If a
+ * match occurs, data is transferred to the data buffer. This field must be
+ * cleared when C7816[ISO7816E] is set/enabled.
+ */
+//@{
+#define BP_UART_C4_MAEN2 (6U) //!< Bit position for UART_C4_MAEN2.
+#define BM_UART_C4_MAEN2 (0x40U) //!< Bit mask for UART_C4_MAEN2.
+#define BS_UART_C4_MAEN2 (1U) //!< Bit field size in bits for UART_C4_MAEN2.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C4_MAEN2 field.
+#define BR_UART_C4_MAEN2(x) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN2))
+#endif
+
+//! @brief Format value for bitfield UART_C4_MAEN2.
+#define BF_UART_C4_MAEN2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C4_MAEN2), uint8_t) & BM_UART_C4_MAEN2)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MAEN2 field to a new value.
+#define BW_UART_C4_MAEN2(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN2) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C4, field MAEN1[7] (RW)
+ *
+ * See Match address operation for more information.
+ *
+ * Values:
+ * - 0 - All data received is transferred to the data buffer if MAEN2 is cleared.
+ * - 1 - All data received with the most significant bit cleared, is discarded.
+ * All data received with the most significant bit set, is compared with
+ * contents of MA1 register. If no match occurs, the data is discarded. If match
+ * occurs, data is transferred to the data buffer. This field must be cleared
+ * when C7816[ISO7816E] is set/enabled.
+ */
+//@{
+#define BP_UART_C4_MAEN1 (7U) //!< Bit position for UART_C4_MAEN1.
+#define BM_UART_C4_MAEN1 (0x80U) //!< Bit mask for UART_C4_MAEN1.
+#define BS_UART_C4_MAEN1 (1U) //!< Bit field size in bits for UART_C4_MAEN1.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C4_MAEN1 field.
+#define BR_UART_C4_MAEN1(x) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN1))
+#endif
+
+//! @brief Format value for bitfield UART_C4_MAEN1.
+#define BF_UART_C4_MAEN1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C4_MAEN1), uint8_t) & BM_UART_C4_MAEN1)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MAEN1 field to a new value.
+#define BW_UART_C4_MAEN1(x, v) (BITBAND_ACCESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN1) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_C5 - UART Control Register 5
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_C5 - UART Control Register 5 (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_uart_c5
+{
+ uint8_t U;
+ struct _hw_uart_c5_bitfields
+ {
+ uint8_t RESERVED0 : 3; //!< [2:0]
+ uint8_t LBKDDMAS : 1; //!< [3] LIN Break Detect DMA Select Bit
+ uint8_t ILDMAS : 1; //!< [4] Idle Line DMA Select
+ uint8_t RDMAS : 1; //!< [5] Receiver Full DMA Select
+ uint8_t TCDMAS : 1; //!< [6] Transmission Complete DMA Select
+ uint8_t TDMAS : 1; //!< [7] Transmitter DMA Select
+ } B;
+} hw_uart_c5_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_C5 register
+ */
+//@{
+#define HW_UART_C5_ADDR(x) (REGS_UART_BASE(x) + 0xBU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_C5(x) (*(__IO hw_uart_c5_t *) HW_UART_C5_ADDR(x))
+#define HW_UART_C5_RD(x) (HW_UART_C5(x).U)
+#define HW_UART_C5_WR(x, v) (HW_UART_C5(x).U = (v))
+#define HW_UART_C5_SET(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) | (v)))
+#define HW_UART_C5_CLR(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) & ~(v)))
+#define HW_UART_C5_TOG(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_C5 bitfields
+ */
+
+/*!
+ * @name Register UART_C5, field LBKDDMAS[3] (RW)
+ *
+ * Configures the LIN break detect flag, S2[LBKDIF], to generate interrupt or
+ * DMA requests if BDH[LBKDIE] is set. If BDH[LBKDIE] is cleared, and S2[LBKDIF] is
+ * set, the LBKDIF DMA and LBKDIF interrupt signals are not asserted, regardless
+ * of the state of LBKDDMAS.
+ *
+ * Values:
+ * - 0 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is
+ * asserted to request an interrupt service.
+ * - 1 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is
+ * asserted to request a DMA transfer.
+ */
+//@{
+#define BP_UART_C5_LBKDDMAS (3U) //!< Bit position for UART_C5_LBKDDMAS.
+#define BM_UART_C5_LBKDDMAS (0x08U) //!< Bit mask for UART_C5_LBKDDMAS.
+#define BS_UART_C5_LBKDDMAS (1U) //!< Bit field size in bits for UART_C5_LBKDDMAS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C5_LBKDDMAS field.
+#define BR_UART_C5_LBKDDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_LBKDDMAS))
+#endif
+
+//! @brief Format value for bitfield UART_C5_LBKDDMAS.
+#define BF_UART_C5_LBKDDMAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C5_LBKDDMAS), uint8_t) & BM_UART_C5_LBKDDMAS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LBKDDMAS field to a new value.
+#define BW_UART_C5_LBKDDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_LBKDDMAS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C5, field ILDMAS[4] (RW)
+ *
+ * Configures the idle line flag, S1[IDLE], to generate interrupt or DMA
+ * requests if C2[ILIE] is set. If C2[ILIE] is cleared, and S1[IDLE] is set, the IDLE
+ * DMA and IDLE interrupt request signals are not asserted, regardless of the state
+ * of ILDMAS.
+ *
+ * Values:
+ * - 0 - If C2[ILIE] and S1[IDLE] are set, the IDLE interrupt request signal is
+ * asserted to request an interrupt service.
+ * - 1 - If C2[ILIE] and S1[IDLE] are set, the IDLE DMA request signal is
+ * asserted to request a DMA transfer.
+ */
+//@{
+#define BP_UART_C5_ILDMAS (4U) //!< Bit position for UART_C5_ILDMAS.
+#define BM_UART_C5_ILDMAS (0x10U) //!< Bit mask for UART_C5_ILDMAS.
+#define BS_UART_C5_ILDMAS (1U) //!< Bit field size in bits for UART_C5_ILDMAS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C5_ILDMAS field.
+#define BR_UART_C5_ILDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_ILDMAS))
+#endif
+
+//! @brief Format value for bitfield UART_C5_ILDMAS.
+#define BF_UART_C5_ILDMAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C5_ILDMAS), uint8_t) & BM_UART_C5_ILDMAS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ILDMAS field to a new value.
+#define BW_UART_C5_ILDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_ILDMAS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C5, field RDMAS[5] (RW)
+ *
+ * Configures the receiver data register full flag, S1[RDRF], to generate
+ * interrupt or DMA requests if C2[RIE] is set. If C2[RIE] is cleared, and S1[RDRF] is
+ * set, the RDRF DMA and RDFR interrupt request signals are not asserted,
+ * regardless of the state of RDMAS.
+ *
+ * Values:
+ * - 0 - If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is
+ * asserted to request an interrupt service.
+ * - 1 - If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is
+ * asserted to request a DMA transfer.
+ */
+//@{
+#define BP_UART_C5_RDMAS (5U) //!< Bit position for UART_C5_RDMAS.
+#define BM_UART_C5_RDMAS (0x20U) //!< Bit mask for UART_C5_RDMAS.
+#define BS_UART_C5_RDMAS (1U) //!< Bit field size in bits for UART_C5_RDMAS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C5_RDMAS field.
+#define BR_UART_C5_RDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_RDMAS))
+#endif
+
+//! @brief Format value for bitfield UART_C5_RDMAS.
+#define BF_UART_C5_RDMAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C5_RDMAS), uint8_t) & BM_UART_C5_RDMAS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RDMAS field to a new value.
+#define BW_UART_C5_RDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_RDMAS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C5, field TCDMAS[6] (RW)
+ *
+ * Configures the transmission complete flag, S1[TC], to generate interrupt or
+ * DMA requests if C2[TCIE] is set. If C2[TCIE] is cleared, the TC DMA and TC
+ * interrupt request signals are not asserted when the S1[TC] flag is set, regardless
+ * of the state of TCDMAS. If C2[TCIE] and TCDMAS are both set, then C2[TIE]
+ * must be cleared, and D must not be written unless a DMA request is being serviced.
+ *
+ * Values:
+ * - 0 - If C2[TCIE] is set and the S1[TC] flag is set, the TC interrupt request
+ * signal is asserted to request an interrupt service.
+ * - 1 - If C2[TCIE] is set and the S1[TC] flag is set, the TC DMA request
+ * signal is asserted to request a DMA transfer.
+ */
+//@{
+#define BP_UART_C5_TCDMAS (6U) //!< Bit position for UART_C5_TCDMAS.
+#define BM_UART_C5_TCDMAS (0x40U) //!< Bit mask for UART_C5_TCDMAS.
+#define BS_UART_C5_TCDMAS (1U) //!< Bit field size in bits for UART_C5_TCDMAS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C5_TCDMAS field.
+#define BR_UART_C5_TCDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TCDMAS))
+#endif
+
+//! @brief Format value for bitfield UART_C5_TCDMAS.
+#define BF_UART_C5_TCDMAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C5_TCDMAS), uint8_t) & BM_UART_C5_TCDMAS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TCDMAS field to a new value.
+#define BW_UART_C5_TCDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TCDMAS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C5, field TDMAS[7] (RW)
+ *
+ * Configures the transmit data register empty flag, S1[TDRE], to generate
+ * interrupt or DMA requests if C2[TIE] is set. If C2[TIE] is cleared, TDRE DMA and
+ * TDRE interrupt request signals are not asserted when the TDRE flag is set,
+ * regardless of the state of TDMAS. If C2[TIE] and TDMAS are both set, then C2[TCIE]
+ * must be cleared, and D must not be written unless a DMA request is being
+ * serviced.
+ *
+ * Values:
+ * - 0 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt
+ * request signal is asserted to request interrupt service.
+ * - 1 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request
+ * signal is asserted to request a DMA transfer.
+ */
+//@{
+#define BP_UART_C5_TDMAS (7U) //!< Bit position for UART_C5_TDMAS.
+#define BM_UART_C5_TDMAS (0x80U) //!< Bit mask for UART_C5_TDMAS.
+#define BS_UART_C5_TDMAS (1U) //!< Bit field size in bits for UART_C5_TDMAS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C5_TDMAS field.
+#define BR_UART_C5_TDMAS(x) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TDMAS))
+#endif
+
+//! @brief Format value for bitfield UART_C5_TDMAS.
+#define BF_UART_C5_TDMAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C5_TDMAS), uint8_t) & BM_UART_C5_TDMAS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TDMAS field to a new value.
+#define BW_UART_C5_TDMAS(x, v) (BITBAND_ACCESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TDMAS) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_ED - UART Extended Data Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_ED - UART Extended Data Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains additional information flags that are stored with a
+ * received dataword. This register may be read at any time but contains valid data
+ * only if there is a dataword in the receive FIFO. The data contained in this
+ * register represents additional information regarding the conditions on which a
+ * dataword was received. The importance of this data varies with the
+ * application, and in some cases maybe completely optional. These fields automatically
+ * update to reflect the conditions of the next dataword whenever D is read. If
+ * S1[NF] and S1[PF] have not been set since the last time the receive buffer was
+ * empty, the NOISY and PARITYE fields will be zero.
+ */
+typedef union _hw_uart_ed
+{
+ uint8_t U;
+ struct _hw_uart_ed_bitfields
+ {
+ uint8_t RESERVED0 : 6; //!< [5:0]
+ uint8_t PARITYE : 1; //!< [6]
+ uint8_t NOISY : 1; //!< [7]
+ } B;
+} hw_uart_ed_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_ED register
+ */
+//@{
+#define HW_UART_ED_ADDR(x) (REGS_UART_BASE(x) + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_ED(x) (*(__I hw_uart_ed_t *) HW_UART_ED_ADDR(x))
+#define HW_UART_ED_RD(x) (HW_UART_ED(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_ED bitfields
+ */
+
+/*!
+ * @name Register UART_ED, field PARITYE[6] (RO)
+ *
+ * The current received dataword contained in D and C3[R8] was received with a
+ * parity error.
+ *
+ * Values:
+ * - 0 - The dataword was received without a parity error.
+ * - 1 - The dataword was received with a parity error.
+ */
+//@{
+#define BP_UART_ED_PARITYE (6U) //!< Bit position for UART_ED_PARITYE.
+#define BM_UART_ED_PARITYE (0x40U) //!< Bit mask for UART_ED_PARITYE.
+#define BS_UART_ED_PARITYE (1U) //!< Bit field size in bits for UART_ED_PARITYE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_ED_PARITYE field.
+#define BR_UART_ED_PARITYE(x) (BITBAND_ACCESS8(HW_UART_ED_ADDR(x), BP_UART_ED_PARITYE))
+#endif
+//@}
+
+/*!
+ * @name Register UART_ED, field NOISY[7] (RO)
+ *
+ * The current received dataword contained in D and C3[R8] was received with
+ * noise.
+ *
+ * Values:
+ * - 0 - The dataword was received without noise.
+ * - 1 - The data was received with noise.
+ */
+//@{
+#define BP_UART_ED_NOISY (7U) //!< Bit position for UART_ED_NOISY.
+#define BM_UART_ED_NOISY (0x80U) //!< Bit mask for UART_ED_NOISY.
+#define BS_UART_ED_NOISY (1U) //!< Bit field size in bits for UART_ED_NOISY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_ED_NOISY field.
+#define BR_UART_ED_NOISY(x) (BITBAND_ACCESS8(HW_UART_ED_ADDR(x), BP_UART_ED_NOISY))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_MODEM - UART Modem Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_MODEM - UART Modem Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The MODEM register controls options for setting the modem configuration.
+ * RXRTSE, TXRTSPOL, TXRTSE, and TXCTSE must all be cleared when C7816[ISO7816EN] is
+ * enabled. This will cause the RTS to deassert during ISO-7816 wait times. The
+ * ISO-7816 protocol does not use the RTS and CTS signals.
+ */
+typedef union _hw_uart_modem
+{
+ uint8_t U;
+ struct _hw_uart_modem_bitfields
+ {
+ uint8_t TXCTSE : 1; //!< [0] Transmitter clear-to-send enable
+ uint8_t TXRTSE : 1; //!< [1] Transmitter request-to-send enable
+ uint8_t TXRTSPOL : 1; //!< [2] Transmitter request-to-send polarity
+ uint8_t RXRTSE : 1; //!< [3] Receiver request-to-send enable
+ uint8_t RESERVED0 : 4; //!< [7:4]
+ } B;
+} hw_uart_modem_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_MODEM register
+ */
+//@{
+#define HW_UART_MODEM_ADDR(x) (REGS_UART_BASE(x) + 0xDU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_MODEM(x) (*(__IO hw_uart_modem_t *) HW_UART_MODEM_ADDR(x))
+#define HW_UART_MODEM_RD(x) (HW_UART_MODEM(x).U)
+#define HW_UART_MODEM_WR(x, v) (HW_UART_MODEM(x).U = (v))
+#define HW_UART_MODEM_SET(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) | (v)))
+#define HW_UART_MODEM_CLR(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) & ~(v)))
+#define HW_UART_MODEM_TOG(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_MODEM bitfields
+ */
+
+/*!
+ * @name Register UART_MODEM, field TXCTSE[0] (RW)
+ *
+ * TXCTSE controls the operation of the transmitter. TXCTSE can be set
+ * independently from the state of TXRTSE and RXRTSE.
+ *
+ * Values:
+ * - 0 - CTS has no effect on the transmitter.
+ * - 1 - Enables clear-to-send operation. The transmitter checks the state of
+ * CTS each time it is ready to send a character. If CTS is asserted, the
+ * character is sent. If CTS is deasserted, the signal TXD remains in the mark
+ * state and transmission is delayed until CTS is asserted. Changes in CTS as a
+ * character is being sent do not affect its transmission.
+ */
+//@{
+#define BP_UART_MODEM_TXCTSE (0U) //!< Bit position for UART_MODEM_TXCTSE.
+#define BM_UART_MODEM_TXCTSE (0x01U) //!< Bit mask for UART_MODEM_TXCTSE.
+#define BS_UART_MODEM_TXCTSE (1U) //!< Bit field size in bits for UART_MODEM_TXCTSE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_MODEM_TXCTSE field.
+#define BR_UART_MODEM_TXCTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXCTSE))
+#endif
+
+//! @brief Format value for bitfield UART_MODEM_TXCTSE.
+#define BF_UART_MODEM_TXCTSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MODEM_TXCTSE), uint8_t) & BM_UART_MODEM_TXCTSE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXCTSE field to a new value.
+#define BW_UART_MODEM_TXCTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXCTSE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_MODEM, field TXRTSE[1] (RW)
+ *
+ * Controls RTS before and after a transmission.
+ *
+ * Values:
+ * - 0 - The transmitter has no effect on RTS.
+ * - 1 - When a character is placed into an empty transmitter data buffer , RTS
+ * asserts one bit time before the start bit is transmitted. RTS deasserts
+ * one bit time after all characters in the transmitter data buffer and shift
+ * register are completely sent, including the last stop bit. (FIFO) (FIFO)
+ */
+//@{
+#define BP_UART_MODEM_TXRTSE (1U) //!< Bit position for UART_MODEM_TXRTSE.
+#define BM_UART_MODEM_TXRTSE (0x02U) //!< Bit mask for UART_MODEM_TXRTSE.
+#define BS_UART_MODEM_TXRTSE (1U) //!< Bit field size in bits for UART_MODEM_TXRTSE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_MODEM_TXRTSE field.
+#define BR_UART_MODEM_TXRTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSE))
+#endif
+
+//! @brief Format value for bitfield UART_MODEM_TXRTSE.
+#define BF_UART_MODEM_TXRTSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MODEM_TXRTSE), uint8_t) & BM_UART_MODEM_TXRTSE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXRTSE field to a new value.
+#define BW_UART_MODEM_TXRTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_MODEM, field TXRTSPOL[2] (RW)
+ *
+ * Controls the polarity of the transmitter RTS. TXRTSPOL does not affect the
+ * polarity of the receiver RTS. RTS will remain negated in the active low state
+ * unless TXRTSE is set.
+ *
+ * Values:
+ * - 0 - Transmitter RTS is active low.
+ * - 1 - Transmitter RTS is active high.
+ */
+//@{
+#define BP_UART_MODEM_TXRTSPOL (2U) //!< Bit position for UART_MODEM_TXRTSPOL.
+#define BM_UART_MODEM_TXRTSPOL (0x04U) //!< Bit mask for UART_MODEM_TXRTSPOL.
+#define BS_UART_MODEM_TXRTSPOL (1U) //!< Bit field size in bits for UART_MODEM_TXRTSPOL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_MODEM_TXRTSPOL field.
+#define BR_UART_MODEM_TXRTSPOL(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSPOL))
+#endif
+
+//! @brief Format value for bitfield UART_MODEM_TXRTSPOL.
+#define BF_UART_MODEM_TXRTSPOL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MODEM_TXRTSPOL), uint8_t) & BM_UART_MODEM_TXRTSPOL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXRTSPOL field to a new value.
+#define BW_UART_MODEM_TXRTSPOL(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSPOL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_MODEM, field RXRTSE[3] (RW)
+ *
+ * Allows the RTS output to control the CTS input of the transmitting device to
+ * prevent receiver overrun. Do not set both RXRTSE and TXRTSE.
+ *
+ * Values:
+ * - 0 - The receiver has no effect on RTS.
+ * - 1 - RTS is deasserted if the number of characters in the receiver data
+ * register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted
+ * when the number of characters in the receiver data register (FIFO) is less
+ * than RWFIFO[RXWATER].
+ */
+//@{
+#define BP_UART_MODEM_RXRTSE (3U) //!< Bit position for UART_MODEM_RXRTSE.
+#define BM_UART_MODEM_RXRTSE (0x08U) //!< Bit mask for UART_MODEM_RXRTSE.
+#define BS_UART_MODEM_RXRTSE (1U) //!< Bit field size in bits for UART_MODEM_RXRTSE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_MODEM_RXRTSE field.
+#define BR_UART_MODEM_RXRTSE(x) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_RXRTSE))
+#endif
+
+//! @brief Format value for bitfield UART_MODEM_RXRTSE.
+#define BF_UART_MODEM_RXRTSE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_MODEM_RXRTSE), uint8_t) & BM_UART_MODEM_RXRTSE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXRTSE field to a new value.
+#define BW_UART_MODEM_RXRTSE(x, v) (BITBAND_ACCESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_RXRTSE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_IR - UART Infrared Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_IR - UART Infrared Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The IR register controls options for setting the infrared configuration.
+ */
+typedef union _hw_uart_ir
+{
+ uint8_t U;
+ struct _hw_uart_ir_bitfields
+ {
+ uint8_t TNP : 2; //!< [1:0] Transmitter narrow pulse
+ uint8_t IREN : 1; //!< [2] Infrared enable
+ uint8_t RESERVED0 : 5; //!< [7:3]
+ } B;
+} hw_uart_ir_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_IR register
+ */
+//@{
+#define HW_UART_IR_ADDR(x) (REGS_UART_BASE(x) + 0xEU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_IR(x) (*(__IO hw_uart_ir_t *) HW_UART_IR_ADDR(x))
+#define HW_UART_IR_RD(x) (HW_UART_IR(x).U)
+#define HW_UART_IR_WR(x, v) (HW_UART_IR(x).U = (v))
+#define HW_UART_IR_SET(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) | (v)))
+#define HW_UART_IR_CLR(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) & ~(v)))
+#define HW_UART_IR_TOG(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_IR bitfields
+ */
+
+/*!
+ * @name Register UART_IR, field TNP[1:0] (RW)
+ *
+ * Enables whether the UART transmits a 1/16, 3/16, 1/32, or 1/4 narrow pulse.
+ *
+ * Values:
+ * - 00 - 3/16.
+ * - 01 - 1/16.
+ * - 10 - 1/32.
+ * - 11 - 1/4.
+ */
+//@{
+#define BP_UART_IR_TNP (0U) //!< Bit position for UART_IR_TNP.
+#define BM_UART_IR_TNP (0x03U) //!< Bit mask for UART_IR_TNP.
+#define BS_UART_IR_TNP (2U) //!< Bit field size in bits for UART_IR_TNP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IR_TNP field.
+#define BR_UART_IR_TNP(x) (HW_UART_IR(x).B.TNP)
+#endif
+
+//! @brief Format value for bitfield UART_IR_TNP.
+#define BF_UART_IR_TNP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IR_TNP), uint8_t) & BM_UART_IR_TNP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TNP field to a new value.
+#define BW_UART_IR_TNP(x, v) (HW_UART_IR_WR(x, (HW_UART_IR_RD(x) & ~BM_UART_IR_TNP) | BF_UART_IR_TNP(v)))
+#endif
+//@}
+
+/*!
+ * @name Register UART_IR, field IREN[2] (RW)
+ *
+ * Enables/disables the infrared modulation/demodulation.
+ *
+ * Values:
+ * - 0 - IR disabled.
+ * - 1 - IR enabled.
+ */
+//@{
+#define BP_UART_IR_IREN (2U) //!< Bit position for UART_IR_IREN.
+#define BM_UART_IR_IREN (0x04U) //!< Bit mask for UART_IR_IREN.
+#define BS_UART_IR_IREN (1U) //!< Bit field size in bits for UART_IR_IREN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IR_IREN field.
+#define BR_UART_IR_IREN(x) (BITBAND_ACCESS8(HW_UART_IR_ADDR(x), BP_UART_IR_IREN))
+#endif
+
+//! @brief Format value for bitfield UART_IR_IREN.
+#define BF_UART_IR_IREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IR_IREN), uint8_t) & BM_UART_IR_IREN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IREN field to a new value.
+#define BW_UART_IR_IREN(x, v) (BITBAND_ACCESS8(HW_UART_IR_ADDR(x), BP_UART_IR_IREN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_PFIFO - UART FIFO Parameters
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_PFIFO - UART FIFO Parameters (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides the ability for the programmer to turn on and off FIFO
+ * functionality. It also provides the size of the FIFO that has been
+ * implemented. This register may be read at any time. This register must be written only
+ * when C2[RE] and C2[TE] are cleared/not set and when the data buffer/FIFO is
+ * empty.
+ */
+typedef union _hw_uart_pfifo
+{
+ uint8_t U;
+ struct _hw_uart_pfifo_bitfields
+ {
+ uint8_t RXFIFOSIZE : 3; //!< [2:0] Receive FIFO. Buffer Depth
+ uint8_t RXFE : 1; //!< [3] Receive FIFO Enable
+ uint8_t TXFIFOSIZE : 3; //!< [6:4] Transmit FIFO. Buffer Depth
+ uint8_t TXFE : 1; //!< [7] Transmit FIFO Enable
+ } B;
+} hw_uart_pfifo_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_PFIFO register
+ */
+//@{
+#define HW_UART_PFIFO_ADDR(x) (REGS_UART_BASE(x) + 0x10U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_PFIFO(x) (*(__IO hw_uart_pfifo_t *) HW_UART_PFIFO_ADDR(x))
+#define HW_UART_PFIFO_RD(x) (HW_UART_PFIFO(x).U)
+#define HW_UART_PFIFO_WR(x, v) (HW_UART_PFIFO(x).U = (v))
+#define HW_UART_PFIFO_SET(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) | (v)))
+#define HW_UART_PFIFO_CLR(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) & ~(v)))
+#define HW_UART_PFIFO_TOG(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_PFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_PFIFO, field RXFIFOSIZE[2:0] (RO)
+ *
+ * The maximum number of receive datawords that can be stored in the receive
+ * buffer before an overrun occurs. This field is read only.
+ *
+ * Values:
+ * - 000 - Receive FIFO/Buffer depth = 1 dataword.
+ * - 001 - Receive FIFO/Buffer depth = 4 datawords.
+ * - 010 - Receive FIFO/Buffer depth = 8 datawords.
+ * - 011 - Receive FIFO/Buffer depth = 16 datawords.
+ * - 100 - Receive FIFO/Buffer depth = 32 datawords.
+ * - 101 - Receive FIFO/Buffer depth = 64 datawords.
+ * - 110 - Receive FIFO/Buffer depth = 128 datawords.
+ * - 111 - Reserved.
+ */
+//@{
+#define BP_UART_PFIFO_RXFIFOSIZE (0U) //!< Bit position for UART_PFIFO_RXFIFOSIZE.
+#define BM_UART_PFIFO_RXFIFOSIZE (0x07U) //!< Bit mask for UART_PFIFO_RXFIFOSIZE.
+#define BS_UART_PFIFO_RXFIFOSIZE (3U) //!< Bit field size in bits for UART_PFIFO_RXFIFOSIZE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_PFIFO_RXFIFOSIZE field.
+#define BR_UART_PFIFO_RXFIFOSIZE(x) (HW_UART_PFIFO(x).B.RXFIFOSIZE)
+#endif
+//@}
+
+/*!
+ * @name Register UART_PFIFO, field RXFE[3] (RW)
+ *
+ * When this field is set, the built in FIFO structure for the receive buffer is
+ * enabled. The size of the FIFO structure is indicated by the RXFIFOSIZE field.
+ * If this field is not set, the receive buffer operates as a FIFO of depth one
+ * dataword regardless of the value in RXFIFOSIZE. Both C2[TE] and C2[RE] must be
+ * cleared prior to changing this field. Additionally, TXFLUSH and RXFLUSH
+ * commands must be issued immediately after changing this field.
+ *
+ * Values:
+ * - 0 - Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
+ * - 1 - Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
+ */
+//@{
+#define BP_UART_PFIFO_RXFE (3U) //!< Bit position for UART_PFIFO_RXFE.
+#define BM_UART_PFIFO_RXFE (0x08U) //!< Bit mask for UART_PFIFO_RXFE.
+#define BS_UART_PFIFO_RXFE (1U) //!< Bit field size in bits for UART_PFIFO_RXFE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_PFIFO_RXFE field.
+#define BR_UART_PFIFO_RXFE(x) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_RXFE))
+#endif
+
+//! @brief Format value for bitfield UART_PFIFO_RXFE.
+#define BF_UART_PFIFO_RXFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_PFIFO_RXFE), uint8_t) & BM_UART_PFIFO_RXFE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXFE field to a new value.
+#define BW_UART_PFIFO_RXFE(x, v) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_RXFE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_PFIFO, field TXFIFOSIZE[6:4] (RO)
+ *
+ * The maximum number of transmit datawords that can be stored in the transmit
+ * buffer. This field is read only.
+ *
+ * Values:
+ * - 000 - Transmit FIFO/Buffer depth = 1 dataword.
+ * - 001 - Transmit FIFO/Buffer depth = 4 datawords.
+ * - 010 - Transmit FIFO/Buffer depth = 8 datawords.
+ * - 011 - Transmit FIFO/Buffer depth = 16 datawords.
+ * - 100 - Transmit FIFO/Buffer depth = 32 datawords.
+ * - 101 - Transmit FIFO/Buffer depth = 64 datawords.
+ * - 110 - Transmit FIFO/Buffer depth = 128 datawords.
+ * - 111 - Reserved.
+ */
+//@{
+#define BP_UART_PFIFO_TXFIFOSIZE (4U) //!< Bit position for UART_PFIFO_TXFIFOSIZE.
+#define BM_UART_PFIFO_TXFIFOSIZE (0x70U) //!< Bit mask for UART_PFIFO_TXFIFOSIZE.
+#define BS_UART_PFIFO_TXFIFOSIZE (3U) //!< Bit field size in bits for UART_PFIFO_TXFIFOSIZE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_PFIFO_TXFIFOSIZE field.
+#define BR_UART_PFIFO_TXFIFOSIZE(x) (HW_UART_PFIFO(x).B.TXFIFOSIZE)
+#endif
+//@}
+
+/*!
+ * @name Register UART_PFIFO, field TXFE[7] (RW)
+ *
+ * When this field is set, the built in FIFO structure for the transmit buffer
+ * is enabled. The size of the FIFO structure is indicated by TXFIFOSIZE. If this
+ * field is not set, the transmit buffer operates as a FIFO of depth one dataword
+ * regardless of the value in TXFIFOSIZE. Both C2[TE] and C2[RE] must be cleared
+ * prior to changing this field. Additionally, TXFLUSH and RXFLUSH commands must
+ * be issued immediately after changing this field.
+ *
+ * Values:
+ * - 0 - Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
+ * - 1 - Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
+ */
+//@{
+#define BP_UART_PFIFO_TXFE (7U) //!< Bit position for UART_PFIFO_TXFE.
+#define BM_UART_PFIFO_TXFE (0x80U) //!< Bit mask for UART_PFIFO_TXFE.
+#define BS_UART_PFIFO_TXFE (1U) //!< Bit field size in bits for UART_PFIFO_TXFE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_PFIFO_TXFE field.
+#define BR_UART_PFIFO_TXFE(x) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_TXFE))
+#endif
+
+//! @brief Format value for bitfield UART_PFIFO_TXFE.
+#define BF_UART_PFIFO_TXFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_PFIFO_TXFE), uint8_t) & BM_UART_PFIFO_TXFE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXFE field to a new value.
+#define BW_UART_PFIFO_TXFE(x, v) (BITBAND_ACCESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_TXFE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_CFIFO - UART FIFO Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_CFIFO - UART FIFO Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides the ability to program various control fields for FIFO
+ * operation. This register may be read or written at any time. Note that
+ * writing to TXFLUSH and RXFLUSH may result in data loss and requires careful action
+ * to prevent unintended/unpredictable behavior. Therefore, it is recommended that
+ * TE and RE be cleared prior to flushing the corresponding FIFO.
+ */
+typedef union _hw_uart_cfifo
+{
+ uint8_t U;
+ struct _hw_uart_cfifo_bitfields
+ {
+ uint8_t RXUFE : 1; //!< [0] Receive FIFO Underflow Interrupt Enable
+ uint8_t TXOFE : 1; //!< [1] Transmit FIFO Overflow Interrupt Enable
+ uint8_t RXOFE : 1; //!< [2] Receive FIFO Overflow Interrupt Enable
+ uint8_t RESERVED0 : 3; //!< [5:3]
+ uint8_t RXFLUSH : 1; //!< [6] Receive FIFO/Buffer Flush
+ uint8_t TXFLUSH : 1; //!< [7] Transmit FIFO/Buffer Flush
+ } B;
+} hw_uart_cfifo_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_CFIFO register
+ */
+//@{
+#define HW_UART_CFIFO_ADDR(x) (REGS_UART_BASE(x) + 0x11U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_CFIFO(x) (*(__IO hw_uart_cfifo_t *) HW_UART_CFIFO_ADDR(x))
+#define HW_UART_CFIFO_RD(x) (HW_UART_CFIFO(x).U)
+#define HW_UART_CFIFO_WR(x, v) (HW_UART_CFIFO(x).U = (v))
+#define HW_UART_CFIFO_SET(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) | (v)))
+#define HW_UART_CFIFO_CLR(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) & ~(v)))
+#define HW_UART_CFIFO_TOG(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_CFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_CFIFO, field RXUFE[0] (RW)
+ *
+ * When this field is set, the RXUF flag generates an interrupt to the host.
+ *
+ * Values:
+ * - 0 - RXUF flag does not generate an interrupt to the host.
+ * - 1 - RXUF flag generates an interrupt to the host.
+ */
+//@{
+#define BP_UART_CFIFO_RXUFE (0U) //!< Bit position for UART_CFIFO_RXUFE.
+#define BM_UART_CFIFO_RXUFE (0x01U) //!< Bit mask for UART_CFIFO_RXUFE.
+#define BS_UART_CFIFO_RXUFE (1U) //!< Bit field size in bits for UART_CFIFO_RXUFE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_CFIFO_RXUFE field.
+#define BR_UART_CFIFO_RXUFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXUFE))
+#endif
+
+//! @brief Format value for bitfield UART_CFIFO_RXUFE.
+#define BF_UART_CFIFO_RXUFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_CFIFO_RXUFE), uint8_t) & BM_UART_CFIFO_RXUFE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXUFE field to a new value.
+#define BW_UART_CFIFO_RXUFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXUFE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_CFIFO, field TXOFE[1] (RW)
+ *
+ * When this field is set, the TXOF flag generates an interrupt to the host.
+ *
+ * Values:
+ * - 0 - TXOF flag does not generate an interrupt to the host.
+ * - 1 - TXOF flag generates an interrupt to the host.
+ */
+//@{
+#define BP_UART_CFIFO_TXOFE (1U) //!< Bit position for UART_CFIFO_TXOFE.
+#define BM_UART_CFIFO_TXOFE (0x02U) //!< Bit mask for UART_CFIFO_TXOFE.
+#define BS_UART_CFIFO_TXOFE (1U) //!< Bit field size in bits for UART_CFIFO_TXOFE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_CFIFO_TXOFE field.
+#define BR_UART_CFIFO_TXOFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXOFE))
+#endif
+
+//! @brief Format value for bitfield UART_CFIFO_TXOFE.
+#define BF_UART_CFIFO_TXOFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_CFIFO_TXOFE), uint8_t) & BM_UART_CFIFO_TXOFE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXOFE field to a new value.
+#define BW_UART_CFIFO_TXOFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXOFE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_CFIFO, field RXOFE[2] (RW)
+ *
+ * When this field is set, the RXOF flag generates an interrupt to the host.
+ *
+ * Values:
+ * - 0 - RXOF flag does not generate an interrupt to the host.
+ * - 1 - RXOF flag generates an interrupt to the host.
+ */
+//@{
+#define BP_UART_CFIFO_RXOFE (2U) //!< Bit position for UART_CFIFO_RXOFE.
+#define BM_UART_CFIFO_RXOFE (0x04U) //!< Bit mask for UART_CFIFO_RXOFE.
+#define BS_UART_CFIFO_RXOFE (1U) //!< Bit field size in bits for UART_CFIFO_RXOFE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_CFIFO_RXOFE field.
+#define BR_UART_CFIFO_RXOFE(x) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXOFE))
+#endif
+
+//! @brief Format value for bitfield UART_CFIFO_RXOFE.
+#define BF_UART_CFIFO_RXOFE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_CFIFO_RXOFE), uint8_t) & BM_UART_CFIFO_RXOFE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXOFE field to a new value.
+#define BW_UART_CFIFO_RXOFE(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXOFE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_CFIFO, field RXFLUSH[6] (WORZ)
+ *
+ * Writing to this field causes all data that is stored in the receive
+ * FIFO/buffer to be flushed. This does not affect data that is in the receive shift
+ * register.
+ *
+ * Values:
+ * - 0 - No flush operation occurs.
+ * - 1 - All data in the receive FIFO/buffer is cleared out.
+ */
+//@{
+#define BP_UART_CFIFO_RXFLUSH (6U) //!< Bit position for UART_CFIFO_RXFLUSH.
+#define BM_UART_CFIFO_RXFLUSH (0x40U) //!< Bit mask for UART_CFIFO_RXFLUSH.
+#define BS_UART_CFIFO_RXFLUSH (1U) //!< Bit field size in bits for UART_CFIFO_RXFLUSH.
+
+//! @brief Format value for bitfield UART_CFIFO_RXFLUSH.
+#define BF_UART_CFIFO_RXFLUSH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_CFIFO_RXFLUSH), uint8_t) & BM_UART_CFIFO_RXFLUSH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXFLUSH field to a new value.
+#define BW_UART_CFIFO_RXFLUSH(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXFLUSH) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_CFIFO, field TXFLUSH[7] (WORZ)
+ *
+ * Writing to this field causes all data that is stored in the transmit
+ * FIFO/buffer to be flushed. This does not affect data that is in the transmit shift
+ * register.
+ *
+ * Values:
+ * - 0 - No flush operation occurs.
+ * - 1 - All data in the transmit FIFO/Buffer is cleared out.
+ */
+//@{
+#define BP_UART_CFIFO_TXFLUSH (7U) //!< Bit position for UART_CFIFO_TXFLUSH.
+#define BM_UART_CFIFO_TXFLUSH (0x80U) //!< Bit mask for UART_CFIFO_TXFLUSH.
+#define BS_UART_CFIFO_TXFLUSH (1U) //!< Bit field size in bits for UART_CFIFO_TXFLUSH.
+
+//! @brief Format value for bitfield UART_CFIFO_TXFLUSH.
+#define BF_UART_CFIFO_TXFLUSH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_CFIFO_TXFLUSH), uint8_t) & BM_UART_CFIFO_TXFLUSH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXFLUSH field to a new value.
+#define BW_UART_CFIFO_TXFLUSH(x, v) (BITBAND_ACCESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXFLUSH) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_SFIFO - UART FIFO Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_SFIFO - UART FIFO Status Register (RW)
+ *
+ * Reset value: 0xC0U
+ *
+ * This register provides status information regarding the transmit and receiver
+ * buffers/FIFOs, including interrupt information. This register may be written
+ * to or read at any time.
+ */
+typedef union _hw_uart_sfifo
+{
+ uint8_t U;
+ struct _hw_uart_sfifo_bitfields
+ {
+ uint8_t RXUF : 1; //!< [0] Receiver Buffer Underflow Flag
+ uint8_t TXOF : 1; //!< [1] Transmitter Buffer Overflow Flag
+ uint8_t RXOF : 1; //!< [2] Receiver Buffer Overflow Flag
+ uint8_t RESERVED0 : 3; //!< [5:3]
+ uint8_t RXEMPT : 1; //!< [6] Receive Buffer/FIFO Empty
+ uint8_t TXEMPT : 1; //!< [7] Transmit Buffer/FIFO Empty
+ } B;
+} hw_uart_sfifo_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_SFIFO register
+ */
+//@{
+#define HW_UART_SFIFO_ADDR(x) (REGS_UART_BASE(x) + 0x12U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_SFIFO(x) (*(__IO hw_uart_sfifo_t *) HW_UART_SFIFO_ADDR(x))
+#define HW_UART_SFIFO_RD(x) (HW_UART_SFIFO(x).U)
+#define HW_UART_SFIFO_WR(x, v) (HW_UART_SFIFO(x).U = (v))
+#define HW_UART_SFIFO_SET(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) | (v)))
+#define HW_UART_SFIFO_CLR(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) & ~(v)))
+#define HW_UART_SFIFO_TOG(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_SFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_SFIFO, field RXUF[0] (W1C)
+ *
+ * Indicates that more data has been read from the receive buffer than was
+ * present. This field will assert regardless of the value of CFIFO[RXUFE]. However,
+ * an interrupt will be issued to the host only if CFIFO[RXUFE] is set. This flag
+ * is cleared by writing a 1.
+ *
+ * Values:
+ * - 0 - No receive buffer underflow has occurred since the last time the flag
+ * was cleared.
+ * - 1 - At least one receive buffer underflow has occurred since the last time
+ * the flag was cleared.
+ */
+//@{
+#define BP_UART_SFIFO_RXUF (0U) //!< Bit position for UART_SFIFO_RXUF.
+#define BM_UART_SFIFO_RXUF (0x01U) //!< Bit mask for UART_SFIFO_RXUF.
+#define BS_UART_SFIFO_RXUF (1U) //!< Bit field size in bits for UART_SFIFO_RXUF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_SFIFO_RXUF field.
+#define BR_UART_SFIFO_RXUF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXUF))
+#endif
+
+//! @brief Format value for bitfield UART_SFIFO_RXUF.
+#define BF_UART_SFIFO_RXUF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_SFIFO_RXUF), uint8_t) & BM_UART_SFIFO_RXUF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXUF field to a new value.
+#define BW_UART_SFIFO_RXUF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXUF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_SFIFO, field TXOF[1] (W1C)
+ *
+ * Indicates that more data has been written to the transmit buffer than it can
+ * hold. This field will assert regardless of the value of CFIFO[TXOFE]. However,
+ * an interrupt will be issued to the host only if CFIFO[TXOFE] is set. This
+ * flag is cleared by writing a 1.
+ *
+ * Values:
+ * - 0 - No transmit buffer overflow has occurred since the last time the flag
+ * was cleared.
+ * - 1 - At least one transmit buffer overflow has occurred since the last time
+ * the flag was cleared.
+ */
+//@{
+#define BP_UART_SFIFO_TXOF (1U) //!< Bit position for UART_SFIFO_TXOF.
+#define BM_UART_SFIFO_TXOF (0x02U) //!< Bit mask for UART_SFIFO_TXOF.
+#define BS_UART_SFIFO_TXOF (1U) //!< Bit field size in bits for UART_SFIFO_TXOF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_SFIFO_TXOF field.
+#define BR_UART_SFIFO_TXOF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXOF))
+#endif
+
+//! @brief Format value for bitfield UART_SFIFO_TXOF.
+#define BF_UART_SFIFO_TXOF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_SFIFO_TXOF), uint8_t) & BM_UART_SFIFO_TXOF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXOF field to a new value.
+#define BW_UART_SFIFO_TXOF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXOF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_SFIFO, field RXOF[2] (W1C)
+ *
+ * Indicates that more data has been written to the receive buffer than it can
+ * hold. This field will assert regardless of the value of CFIFO[RXOFE]. However,
+ * an interrupt will be issued to the host only if CFIFO[RXOFE] is set. This flag
+ * is cleared by writing a 1.
+ *
+ * Values:
+ * - 0 - No receive buffer overflow has occurred since the last time the flag
+ * was cleared.
+ * - 1 - At least one receive buffer overflow has occurred since the last time
+ * the flag was cleared.
+ */
+//@{
+#define BP_UART_SFIFO_RXOF (2U) //!< Bit position for UART_SFIFO_RXOF.
+#define BM_UART_SFIFO_RXOF (0x04U) //!< Bit mask for UART_SFIFO_RXOF.
+#define BS_UART_SFIFO_RXOF (1U) //!< Bit field size in bits for UART_SFIFO_RXOF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_SFIFO_RXOF field.
+#define BR_UART_SFIFO_RXOF(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXOF))
+#endif
+
+//! @brief Format value for bitfield UART_SFIFO_RXOF.
+#define BF_UART_SFIFO_RXOF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_SFIFO_RXOF), uint8_t) & BM_UART_SFIFO_RXOF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXOF field to a new value.
+#define BW_UART_SFIFO_RXOF(x, v) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXOF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_SFIFO, field RXEMPT[6] (RO)
+ *
+ * Asserts when there is no data in the receive FIFO/Buffer. This field does not
+ * take into account data that is in the receive shift register.
+ *
+ * Values:
+ * - 0 - Receive buffer is not empty.
+ * - 1 - Receive buffer is empty.
+ */
+//@{
+#define BP_UART_SFIFO_RXEMPT (6U) //!< Bit position for UART_SFIFO_RXEMPT.
+#define BM_UART_SFIFO_RXEMPT (0x40U) //!< Bit mask for UART_SFIFO_RXEMPT.
+#define BS_UART_SFIFO_RXEMPT (1U) //!< Bit field size in bits for UART_SFIFO_RXEMPT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_SFIFO_RXEMPT field.
+#define BR_UART_SFIFO_RXEMPT(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXEMPT))
+#endif
+//@}
+
+/*!
+ * @name Register UART_SFIFO, field TXEMPT[7] (RO)
+ *
+ * Asserts when there is no data in the Transmit FIFO/buffer. This field does
+ * not take into account data that is in the transmit shift register.
+ *
+ * Values:
+ * - 0 - Transmit buffer is not empty.
+ * - 1 - Transmit buffer is empty.
+ */
+//@{
+#define BP_UART_SFIFO_TXEMPT (7U) //!< Bit position for UART_SFIFO_TXEMPT.
+#define BM_UART_SFIFO_TXEMPT (0x80U) //!< Bit mask for UART_SFIFO_TXEMPT.
+#define BS_UART_SFIFO_TXEMPT (1U) //!< Bit field size in bits for UART_SFIFO_TXEMPT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_SFIFO_TXEMPT field.
+#define BR_UART_SFIFO_TXEMPT(x) (BITBAND_ACCESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXEMPT))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_TWFIFO - UART FIFO Transmit Watermark
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_TWFIFO - UART FIFO Transmit Watermark (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides the ability to set a programmable threshold for
+ * notification of needing additional transmit data. This register may be read at any
+ * time but must be written only when C2[TE] is not set. Changing the value of the
+ * watermark will not clear the S1[TDRE] flag.
+ */
+typedef union _hw_uart_twfifo
+{
+ uint8_t U;
+ struct _hw_uart_twfifo_bitfields
+ {
+ uint8_t TXWATER : 8; //!< [7:0] Transmit Watermark
+ } B;
+} hw_uart_twfifo_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_TWFIFO register
+ */
+//@{
+#define HW_UART_TWFIFO_ADDR(x) (REGS_UART_BASE(x) + 0x13U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_TWFIFO(x) (*(__IO hw_uart_twfifo_t *) HW_UART_TWFIFO_ADDR(x))
+#define HW_UART_TWFIFO_RD(x) (HW_UART_TWFIFO(x).U)
+#define HW_UART_TWFIFO_WR(x, v) (HW_UART_TWFIFO(x).U = (v))
+#define HW_UART_TWFIFO_SET(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) | (v)))
+#define HW_UART_TWFIFO_CLR(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) & ~(v)))
+#define HW_UART_TWFIFO_TOG(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_TWFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_TWFIFO, field TXWATER[7:0] (RW)
+ *
+ * When the number of datawords in the transmit FIFO/buffer is equal to or less
+ * than the value in this register field, an interrupt via S1[TDRE] or a DMA
+ * request via C5[TDMAS] is generated as determined by C5[TDMAS] and C2[TIE]. For
+ * proper operation, the value in TXWATER must be set to be less than the size of
+ * the transmit buffer/FIFO size as indicated by PFIFO[TXFIFOSIZE] and PFIFO[TXFE].
+ */
+//@{
+#define BP_UART_TWFIFO_TXWATER (0U) //!< Bit position for UART_TWFIFO_TXWATER.
+#define BM_UART_TWFIFO_TXWATER (0xFFU) //!< Bit mask for UART_TWFIFO_TXWATER.
+#define BS_UART_TWFIFO_TXWATER (8U) //!< Bit field size in bits for UART_TWFIFO_TXWATER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_TWFIFO_TXWATER field.
+#define BR_UART_TWFIFO_TXWATER(x) (HW_UART_TWFIFO(x).U)
+#endif
+
+//! @brief Format value for bitfield UART_TWFIFO_TXWATER.
+#define BF_UART_TWFIFO_TXWATER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_TWFIFO_TXWATER), uint8_t) & BM_UART_TWFIFO_TXWATER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXWATER field to a new value.
+#define BW_UART_TWFIFO_TXWATER(x, v) (HW_UART_TWFIFO_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_TCFIFO - UART FIFO Transmit Count
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_TCFIFO - UART FIFO Transmit Count (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This is a read only register that indicates how many datawords are currently
+ * in the transmit buffer/FIFO. It may be read at any time.
+ */
+typedef union _hw_uart_tcfifo
+{
+ uint8_t U;
+ struct _hw_uart_tcfifo_bitfields
+ {
+ uint8_t TXCOUNT : 8; //!< [7:0] Transmit Counter
+ } B;
+} hw_uart_tcfifo_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_TCFIFO register
+ */
+//@{
+#define HW_UART_TCFIFO_ADDR(x) (REGS_UART_BASE(x) + 0x14U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_TCFIFO(x) (*(__I hw_uart_tcfifo_t *) HW_UART_TCFIFO_ADDR(x))
+#define HW_UART_TCFIFO_RD(x) (HW_UART_TCFIFO(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_TCFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_TCFIFO, field TXCOUNT[7:0] (RO)
+ *
+ * The value in this register indicates the number of datawords that are in the
+ * transmit FIFO/buffer. If a dataword is being transmitted, that is, in the
+ * transmit shift register, it is not included in the count. This value may be used
+ * in conjunction with PFIFO[TXFIFOSIZE] to calculate how much room is left in the
+ * transmit FIFO/buffer.
+ */
+//@{
+#define BP_UART_TCFIFO_TXCOUNT (0U) //!< Bit position for UART_TCFIFO_TXCOUNT.
+#define BM_UART_TCFIFO_TXCOUNT (0xFFU) //!< Bit mask for UART_TCFIFO_TXCOUNT.
+#define BS_UART_TCFIFO_TXCOUNT (8U) //!< Bit field size in bits for UART_TCFIFO_TXCOUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_TCFIFO_TXCOUNT field.
+#define BR_UART_TCFIFO_TXCOUNT(x) (HW_UART_TCFIFO(x).U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_RWFIFO - UART FIFO Receive Watermark
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_RWFIFO - UART FIFO Receive Watermark (RW)
+ *
+ * Reset value: 0x01U
+ *
+ * This register provides the ability to set a programmable threshold for
+ * notification of the need to remove data from the receiver FIFO/buffer. This register
+ * may be read at any time but must be written only when C2[RE] is not asserted.
+ * Changing the value in this register will not clear S1[RDRF].
+ */
+typedef union _hw_uart_rwfifo
+{
+ uint8_t U;
+ struct _hw_uart_rwfifo_bitfields
+ {
+ uint8_t RXWATER : 8; //!< [7:0] Receive Watermark
+ } B;
+} hw_uart_rwfifo_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_RWFIFO register
+ */
+//@{
+#define HW_UART_RWFIFO_ADDR(x) (REGS_UART_BASE(x) + 0x15U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_RWFIFO(x) (*(__IO hw_uart_rwfifo_t *) HW_UART_RWFIFO_ADDR(x))
+#define HW_UART_RWFIFO_RD(x) (HW_UART_RWFIFO(x).U)
+#define HW_UART_RWFIFO_WR(x, v) (HW_UART_RWFIFO(x).U = (v))
+#define HW_UART_RWFIFO_SET(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) | (v)))
+#define HW_UART_RWFIFO_CLR(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) & ~(v)))
+#define HW_UART_RWFIFO_TOG(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_RWFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_RWFIFO, field RXWATER[7:0] (RW)
+ *
+ * When the number of datawords in the receive FIFO/buffer is equal to or
+ * greater than the value in this register field, an interrupt via S1[RDRF] or a DMA
+ * request via C5[RDMAS] is generated as determined by C5[RDMAS] and C2[RIE]. For
+ * proper operation, the value in RXWATER must be set to be less than the receive
+ * FIFO/buffer size as indicated by PFIFO[RXFIFOSIZE] and PFIFO[RXFE] and must be
+ * greater than 0.
+ */
+//@{
+#define BP_UART_RWFIFO_RXWATER (0U) //!< Bit position for UART_RWFIFO_RXWATER.
+#define BM_UART_RWFIFO_RXWATER (0xFFU) //!< Bit mask for UART_RWFIFO_RXWATER.
+#define BS_UART_RWFIFO_RXWATER (8U) //!< Bit field size in bits for UART_RWFIFO_RXWATER.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_RWFIFO_RXWATER field.
+#define BR_UART_RWFIFO_RXWATER(x) (HW_UART_RWFIFO(x).U)
+#endif
+
+//! @brief Format value for bitfield UART_RWFIFO_RXWATER.
+#define BF_UART_RWFIFO_RXWATER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_RWFIFO_RXWATER), uint8_t) & BM_UART_RWFIFO_RXWATER)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXWATER field to a new value.
+#define BW_UART_RWFIFO_RXWATER(x, v) (HW_UART_RWFIFO_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_RCFIFO - UART FIFO Receive Count
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_RCFIFO - UART FIFO Receive Count (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This is a read only register that indicates how many datawords are currently
+ * in the receive FIFO/buffer. It may be read at any time.
+ */
+typedef union _hw_uart_rcfifo
+{
+ uint8_t U;
+ struct _hw_uart_rcfifo_bitfields
+ {
+ uint8_t RXCOUNT : 8; //!< [7:0] Receive Counter
+ } B;
+} hw_uart_rcfifo_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_RCFIFO register
+ */
+//@{
+#define HW_UART_RCFIFO_ADDR(x) (REGS_UART_BASE(x) + 0x16U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_RCFIFO(x) (*(__I hw_uart_rcfifo_t *) HW_UART_RCFIFO_ADDR(x))
+#define HW_UART_RCFIFO_RD(x) (HW_UART_RCFIFO(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_RCFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_RCFIFO, field RXCOUNT[7:0] (RO)
+ *
+ * The value in this register indicates the number of datawords that are in the
+ * receive FIFO/buffer. If a dataword is being received, that is, in the receive
+ * shift register, it is not included in the count. This value may be used in
+ * conjunction with PFIFO[RXFIFOSIZE] to calculate how much room is left in the
+ * receive FIFO/buffer.
+ */
+//@{
+#define BP_UART_RCFIFO_RXCOUNT (0U) //!< Bit position for UART_RCFIFO_RXCOUNT.
+#define BM_UART_RCFIFO_RXCOUNT (0xFFU) //!< Bit mask for UART_RCFIFO_RXCOUNT.
+#define BS_UART_RCFIFO_RXCOUNT (8U) //!< Bit field size in bits for UART_RCFIFO_RXCOUNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_RCFIFO_RXCOUNT field.
+#define BR_UART_RCFIFO_RXCOUNT(x) (HW_UART_RCFIFO(x).U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_C7816 - UART 7816 Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_C7816 - UART 7816 Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The C7816 register is the primary control register for ISO-7816 specific
+ * functionality. This register is specific to 7816 functionality and the values in
+ * this register have no effect on UART operation and should be ignored if
+ * ISO_7816E is not set/enabled. This register may be read at any time but values must
+ * be changed only when ISO_7816E is not set.
+ */
+typedef union _hw_uart_c7816
+{
+ uint8_t U;
+ struct _hw_uart_c7816_bitfields
+ {
+ uint8_t ISO_7816E : 1; //!< [0] ISO-7816 Functionality Enabled
+ uint8_t TTYPE : 1; //!< [1] Transfer Type
+ uint8_t INIT : 1; //!< [2] Detect Initial Character
+ uint8_t ANACK : 1; //!< [3] Generate NACK on Error
+ uint8_t ONACK : 1; //!< [4] Generate NACK on Overflow
+ uint8_t RESERVED0 : 3; //!< [7:5]
+ } B;
+} hw_uart_c7816_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_C7816 register
+ */
+//@{
+#define HW_UART_C7816_ADDR(x) (REGS_UART_BASE(x) + 0x18U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_C7816(x) (*(__IO hw_uart_c7816_t *) HW_UART_C7816_ADDR(x))
+#define HW_UART_C7816_RD(x) (HW_UART_C7816(x).U)
+#define HW_UART_C7816_WR(x, v) (HW_UART_C7816(x).U = (v))
+#define HW_UART_C7816_SET(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) | (v)))
+#define HW_UART_C7816_CLR(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) & ~(v)))
+#define HW_UART_C7816_TOG(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_C7816 bitfields
+ */
+
+/*!
+ * @name Register UART_C7816, field ISO_7816E[0] (RW)
+ *
+ * Indicates that the UART is operating according to the ISO-7816 protocol. This
+ * field must be modified only when no transmit or receive is occurring. If this
+ * field is changed during a data transfer, the data being transmitted or
+ * received may be transferred incorrectly.
+ *
+ * Values:
+ * - 0 - ISO-7816 functionality is turned off/not enabled.
+ * - 1 - ISO-7816 functionality is turned on/enabled.
+ */
+//@{
+#define BP_UART_C7816_ISO_7816E (0U) //!< Bit position for UART_C7816_ISO_7816E.
+#define BM_UART_C7816_ISO_7816E (0x01U) //!< Bit mask for UART_C7816_ISO_7816E.
+#define BS_UART_C7816_ISO_7816E (1U) //!< Bit field size in bits for UART_C7816_ISO_7816E.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C7816_ISO_7816E field.
+#define BR_UART_C7816_ISO_7816E(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ISO_7816E))
+#endif
+
+//! @brief Format value for bitfield UART_C7816_ISO_7816E.
+#define BF_UART_C7816_ISO_7816E(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C7816_ISO_7816E), uint8_t) & BM_UART_C7816_ISO_7816E)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ISO_7816E field to a new value.
+#define BW_UART_C7816_ISO_7816E(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ISO_7816E) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C7816, field TTYPE[1] (RW)
+ *
+ * Indicates the transfer protocol being used. See ISO-7816 / smartcard support
+ * for more details.
+ *
+ * Values:
+ * - 0 - T = 0 per the ISO-7816 specification.
+ * - 1 - T = 1 per the ISO-7816 specification.
+ */
+//@{
+#define BP_UART_C7816_TTYPE (1U) //!< Bit position for UART_C7816_TTYPE.
+#define BM_UART_C7816_TTYPE (0x02U) //!< Bit mask for UART_C7816_TTYPE.
+#define BS_UART_C7816_TTYPE (1U) //!< Bit field size in bits for UART_C7816_TTYPE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C7816_TTYPE field.
+#define BR_UART_C7816_TTYPE(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_TTYPE))
+#endif
+
+//! @brief Format value for bitfield UART_C7816_TTYPE.
+#define BF_UART_C7816_TTYPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C7816_TTYPE), uint8_t) & BM_UART_C7816_TTYPE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TTYPE field to a new value.
+#define BW_UART_C7816_TTYPE(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_TTYPE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C7816, field INIT[2] (RW)
+ *
+ * When this field is set, all received characters are searched for a valid
+ * initial character. If an invalid initial character is identified, and ANACK is
+ * set, a NACK is sent. All received data is discarded and error flags blocked
+ * (S1[NF], S1[OR], S1[FE], S1[PF], IS7816[WT], IS7816[CWT], IS7816[BWT], IS7816[GTV])
+ * until a valid initial character is detected. Upon detecting a valid initial
+ * character, the configuration values S2[MSBF], C3[TXINV], and S2[RXINV] are
+ * automatically updated to reflect the initial character that was received. The
+ * actual INIT data value is not stored in the receive buffer. Additionally, upon
+ * detection of a valid initial character, IS7816[INITD] is set and an interrupt
+ * issued as programmed by IE7816[INITDE]. When a valid initial character is
+ * detected, INIT is automatically cleared. This Initial Character Detect feature is
+ * supported only in T = 0 protocol mode.
+ *
+ * Values:
+ * - 0 - Normal operating mode. Receiver does not seek to identify initial
+ * character.
+ * - 1 - Receiver searches for initial character.
+ */
+//@{
+#define BP_UART_C7816_INIT (2U) //!< Bit position for UART_C7816_INIT.
+#define BM_UART_C7816_INIT (0x04U) //!< Bit mask for UART_C7816_INIT.
+#define BS_UART_C7816_INIT (1U) //!< Bit field size in bits for UART_C7816_INIT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C7816_INIT field.
+#define BR_UART_C7816_INIT(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_INIT))
+#endif
+
+//! @brief Format value for bitfield UART_C7816_INIT.
+#define BF_UART_C7816_INIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C7816_INIT), uint8_t) & BM_UART_C7816_INIT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INIT field to a new value.
+#define BW_UART_C7816_INIT(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_INIT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C7816, field ANACK[3] (RW)
+ *
+ * When this field is set, the receiver automatically generates a NACK response
+ * if a parity error occurs or if INIT is set and an invalid initial character is
+ * detected. A NACK is generated only if TTYPE = 0. If ANACK is set, the UART
+ * attempts to retransmit the data indefinitely. To stop retransmission attempts,
+ * clear C2[TE] or ISO_7816E and do not set until S1[TC] sets C2[TE] again.
+ *
+ * Values:
+ * - 0 - No NACK is automatically generated.
+ * - 1 - A NACK is automatically generated if a parity error is detected or if
+ * an invalid initial character is detected.
+ */
+//@{
+#define BP_UART_C7816_ANACK (3U) //!< Bit position for UART_C7816_ANACK.
+#define BM_UART_C7816_ANACK (0x08U) //!< Bit mask for UART_C7816_ANACK.
+#define BS_UART_C7816_ANACK (1U) //!< Bit field size in bits for UART_C7816_ANACK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C7816_ANACK field.
+#define BR_UART_C7816_ANACK(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ANACK))
+#endif
+
+//! @brief Format value for bitfield UART_C7816_ANACK.
+#define BF_UART_C7816_ANACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C7816_ANACK), uint8_t) & BM_UART_C7816_ANACK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ANACK field to a new value.
+#define BW_UART_C7816_ANACK(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ANACK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_C7816, field ONACK[4] (RW)
+ *
+ * When this field is set, the receiver automatically generates a NACK response
+ * if a receive buffer overrun occurs, as indicated by S1[OR]. In many systems,
+ * this results in the transmitter resending the packet that overflowed until the
+ * retransmit threshold for that transmitter is reached. A NACK is generated only
+ * if TTYPE=0. This field operates independently of ANACK. See . Overrun NACK
+ * considerations
+ *
+ * Values:
+ * - 0 - The received data does not generate a NACK when the receipt of the data
+ * results in an overflow event.
+ * - 1 - If the receiver buffer overflows, a NACK is automatically sent on a
+ * received character.
+ */
+//@{
+#define BP_UART_C7816_ONACK (4U) //!< Bit position for UART_C7816_ONACK.
+#define BM_UART_C7816_ONACK (0x10U) //!< Bit mask for UART_C7816_ONACK.
+#define BS_UART_C7816_ONACK (1U) //!< Bit field size in bits for UART_C7816_ONACK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_C7816_ONACK field.
+#define BR_UART_C7816_ONACK(x) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ONACK))
+#endif
+
+//! @brief Format value for bitfield UART_C7816_ONACK.
+#define BF_UART_C7816_ONACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_C7816_ONACK), uint8_t) & BM_UART_C7816_ONACK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ONACK field to a new value.
+#define BW_UART_C7816_ONACK(x, v) (BITBAND_ACCESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ONACK) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_IE7816 - UART 7816 Interrupt Enable Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_IE7816 - UART 7816 Interrupt Enable Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The IE7816 register controls which flags result in an interrupt being issued.
+ * This register is specific to 7816 functionality, the corresponding flags that
+ * drive the interrupts are not asserted when 7816E is not set/enabled. However,
+ * these flags may remain set if they are asserted while 7816E was set and not
+ * subsequently cleared. This register may be read or written to at any time.
+ */
+typedef union _hw_uart_ie7816
+{
+ uint8_t U;
+ struct _hw_uart_ie7816_bitfields
+ {
+ uint8_t RXTE : 1; //!< [0] Receive Threshold Exceeded Interrupt Enable
+ uint8_t TXTE : 1; //!< [1] Transmit Threshold Exceeded Interrupt
+ //! Enable
+ uint8_t GTVE : 1; //!< [2] Guard Timer Violated Interrupt Enable
+ uint8_t RESERVED0 : 1; //!< [3]
+ uint8_t INITDE : 1; //!< [4] Initial Character Detected Interrupt
+ //! Enable
+ uint8_t BWTE : 1; //!< [5] Block Wait Timer Interrupt Enable
+ uint8_t CWTE : 1; //!< [6] Character Wait Timer Interrupt Enable
+ uint8_t WTE : 1; //!< [7] Wait Timer Interrupt Enable
+ } B;
+} hw_uart_ie7816_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_IE7816 register
+ */
+//@{
+#define HW_UART_IE7816_ADDR(x) (REGS_UART_BASE(x) + 0x19U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_IE7816(x) (*(__IO hw_uart_ie7816_t *) HW_UART_IE7816_ADDR(x))
+#define HW_UART_IE7816_RD(x) (HW_UART_IE7816(x).U)
+#define HW_UART_IE7816_WR(x, v) (HW_UART_IE7816(x).U = (v))
+#define HW_UART_IE7816_SET(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) | (v)))
+#define HW_UART_IE7816_CLR(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) & ~(v)))
+#define HW_UART_IE7816_TOG(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_IE7816 bitfields
+ */
+
+/*!
+ * @name Register UART_IE7816, field RXTE[0] (RW)
+ *
+ * Values:
+ * - 0 - The assertion of IS7816[RXT] does not result in the generation of an
+ * interrupt.
+ * - 1 - The assertion of IS7816[RXT] results in the generation of an interrupt.
+ */
+//@{
+#define BP_UART_IE7816_RXTE (0U) //!< Bit position for UART_IE7816_RXTE.
+#define BM_UART_IE7816_RXTE (0x01U) //!< Bit mask for UART_IE7816_RXTE.
+#define BS_UART_IE7816_RXTE (1U) //!< Bit field size in bits for UART_IE7816_RXTE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IE7816_RXTE field.
+#define BR_UART_IE7816_RXTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_RXTE))
+#endif
+
+//! @brief Format value for bitfield UART_IE7816_RXTE.
+#define BF_UART_IE7816_RXTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_RXTE), uint8_t) & BM_UART_IE7816_RXTE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXTE field to a new value.
+#define BW_UART_IE7816_RXTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_RXTE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_IE7816, field TXTE[1] (RW)
+ *
+ * Values:
+ * - 0 - The assertion of IS7816[TXT] does not result in the generation of an
+ * interrupt.
+ * - 1 - The assertion of IS7816[TXT] results in the generation of an interrupt.
+ */
+//@{
+#define BP_UART_IE7816_TXTE (1U) //!< Bit position for UART_IE7816_TXTE.
+#define BM_UART_IE7816_TXTE (0x02U) //!< Bit mask for UART_IE7816_TXTE.
+#define BS_UART_IE7816_TXTE (1U) //!< Bit field size in bits for UART_IE7816_TXTE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IE7816_TXTE field.
+#define BR_UART_IE7816_TXTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_TXTE))
+#endif
+
+//! @brief Format value for bitfield UART_IE7816_TXTE.
+#define BF_UART_IE7816_TXTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_TXTE), uint8_t) & BM_UART_IE7816_TXTE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXTE field to a new value.
+#define BW_UART_IE7816_TXTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_TXTE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_IE7816, field GTVE[2] (RW)
+ *
+ * Values:
+ * - 0 - The assertion of IS7816[GTV] does not result in the generation of an
+ * interrupt.
+ * - 1 - The assertion of IS7816[GTV] results in the generation of an interrupt.
+ */
+//@{
+#define BP_UART_IE7816_GTVE (2U) //!< Bit position for UART_IE7816_GTVE.
+#define BM_UART_IE7816_GTVE (0x04U) //!< Bit mask for UART_IE7816_GTVE.
+#define BS_UART_IE7816_GTVE (1U) //!< Bit field size in bits for UART_IE7816_GTVE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IE7816_GTVE field.
+#define BR_UART_IE7816_GTVE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_GTVE))
+#endif
+
+//! @brief Format value for bitfield UART_IE7816_GTVE.
+#define BF_UART_IE7816_GTVE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_GTVE), uint8_t) & BM_UART_IE7816_GTVE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GTVE field to a new value.
+#define BW_UART_IE7816_GTVE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_GTVE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_IE7816, field INITDE[4] (RW)
+ *
+ * Values:
+ * - 0 - The assertion of IS7816[INITD] does not result in the generation of an
+ * interrupt.
+ * - 1 - The assertion of IS7816[INITD] results in the generation of an
+ * interrupt.
+ */
+//@{
+#define BP_UART_IE7816_INITDE (4U) //!< Bit position for UART_IE7816_INITDE.
+#define BM_UART_IE7816_INITDE (0x10U) //!< Bit mask for UART_IE7816_INITDE.
+#define BS_UART_IE7816_INITDE (1U) //!< Bit field size in bits for UART_IE7816_INITDE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IE7816_INITDE field.
+#define BR_UART_IE7816_INITDE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_INITDE))
+#endif
+
+//! @brief Format value for bitfield UART_IE7816_INITDE.
+#define BF_UART_IE7816_INITDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_INITDE), uint8_t) & BM_UART_IE7816_INITDE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INITDE field to a new value.
+#define BW_UART_IE7816_INITDE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_INITDE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_IE7816, field BWTE[5] (RW)
+ *
+ * Values:
+ * - 0 - The assertion of IS7816[BWT] does not result in the generation of an
+ * interrupt.
+ * - 1 - The assertion of IS7816[BWT] results in the generation of an interrupt.
+ */
+//@{
+#define BP_UART_IE7816_BWTE (5U) //!< Bit position for UART_IE7816_BWTE.
+#define BM_UART_IE7816_BWTE (0x20U) //!< Bit mask for UART_IE7816_BWTE.
+#define BS_UART_IE7816_BWTE (1U) //!< Bit field size in bits for UART_IE7816_BWTE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IE7816_BWTE field.
+#define BR_UART_IE7816_BWTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_BWTE))
+#endif
+
+//! @brief Format value for bitfield UART_IE7816_BWTE.
+#define BF_UART_IE7816_BWTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_BWTE), uint8_t) & BM_UART_IE7816_BWTE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BWTE field to a new value.
+#define BW_UART_IE7816_BWTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_BWTE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_IE7816, field CWTE[6] (RW)
+ *
+ * Values:
+ * - 0 - The assertion of IS7816[CWT] does not result in the generation of an
+ * interrupt.
+ * - 1 - The assertion of IS7816[CWT] results in the generation of an interrupt.
+ */
+//@{
+#define BP_UART_IE7816_CWTE (6U) //!< Bit position for UART_IE7816_CWTE.
+#define BM_UART_IE7816_CWTE (0x40U) //!< Bit mask for UART_IE7816_CWTE.
+#define BS_UART_IE7816_CWTE (1U) //!< Bit field size in bits for UART_IE7816_CWTE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IE7816_CWTE field.
+#define BR_UART_IE7816_CWTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_CWTE))
+#endif
+
+//! @brief Format value for bitfield UART_IE7816_CWTE.
+#define BF_UART_IE7816_CWTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_CWTE), uint8_t) & BM_UART_IE7816_CWTE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CWTE field to a new value.
+#define BW_UART_IE7816_CWTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_CWTE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_IE7816, field WTE[7] (RW)
+ *
+ * Values:
+ * - 0 - The assertion of IS7816[WT] does not result in the generation of an
+ * interrupt.
+ * - 1 - The assertion of IS7816[WT] results in the generation of an interrupt.
+ */
+//@{
+#define BP_UART_IE7816_WTE (7U) //!< Bit position for UART_IE7816_WTE.
+#define BM_UART_IE7816_WTE (0x80U) //!< Bit mask for UART_IE7816_WTE.
+#define BS_UART_IE7816_WTE (1U) //!< Bit field size in bits for UART_IE7816_WTE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IE7816_WTE field.
+#define BR_UART_IE7816_WTE(x) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_WTE))
+#endif
+
+//! @brief Format value for bitfield UART_IE7816_WTE.
+#define BF_UART_IE7816_WTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IE7816_WTE), uint8_t) & BM_UART_IE7816_WTE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WTE field to a new value.
+#define BW_UART_IE7816_WTE(x, v) (BITBAND_ACCESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_WTE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_IS7816 - UART 7816 Interrupt Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_IS7816 - UART 7816 Interrupt Status Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The IS7816 register provides a mechanism to read and clear the interrupt
+ * flags. All flags/interrupts are cleared by writing a 1 to the field location.
+ * Writing a 0 has no effect. All bits are "sticky", meaning they indicate that only
+ * the flag condition that occurred since the last time the bit was cleared, not
+ * that the condition currently exists. The status flags are set regardless of
+ * whether the corresponding field in the IE7816 is set or cleared. The IE7816
+ * controls only if an interrupt is issued to the host processor. This register is
+ * specific to 7816 functionality and the values in this register have no affect on
+ * UART operation and should be ignored if 7816E is not set/enabled. This
+ * register may be read or written at anytime.
+ */
+typedef union _hw_uart_is7816
+{
+ uint8_t U;
+ struct _hw_uart_is7816_bitfields
+ {
+ uint8_t RXT : 1; //!< [0] Receive Threshold Exceeded Interrupt
+ uint8_t TXT : 1; //!< [1] Transmit Threshold Exceeded Interrupt
+ uint8_t GTV : 1; //!< [2] Guard Timer Violated Interrupt
+ uint8_t RESERVED0 : 1; //!< [3]
+ uint8_t INITD : 1; //!< [4] Initial Character Detected Interrupt
+ uint8_t BWT : 1; //!< [5] Block Wait Timer Interrupt
+ uint8_t CWT : 1; //!< [6] Character Wait Timer Interrupt
+ uint8_t WT : 1; //!< [7] Wait Timer Interrupt
+ } B;
+} hw_uart_is7816_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_IS7816 register
+ */
+//@{
+#define HW_UART_IS7816_ADDR(x) (REGS_UART_BASE(x) + 0x1AU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_IS7816(x) (*(__IO hw_uart_is7816_t *) HW_UART_IS7816_ADDR(x))
+#define HW_UART_IS7816_RD(x) (HW_UART_IS7816(x).U)
+#define HW_UART_IS7816_WR(x, v) (HW_UART_IS7816(x).U = (v))
+#define HW_UART_IS7816_SET(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) | (v)))
+#define HW_UART_IS7816_CLR(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) & ~(v)))
+#define HW_UART_IS7816_TOG(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_IS7816 bitfields
+ */
+
+/*!
+ * @name Register UART_IS7816, field RXT[0] (W1C)
+ *
+ * Indicates that there are more than ET7816[RXTHRESHOLD] consecutive NACKS
+ * generated in response to parity errors on received data. This flag requires ANACK
+ * to be set. Additionally, this flag asserts only when C7816[TTYPE] = 0.
+ * Clearing this field also resets the counter keeping track of consecutive NACKS. The
+ * UART will continue to attempt to receive data regardless of whether this flag
+ * is set. If 7816E is cleared/disabled, RE is cleared/disabled, C7816[TTYPE] = 1,
+ * or packet is received without needing to issue a NACK, the internal NACK
+ * detection counter is cleared and the count restarts from zero on the next
+ * transmitted NACK. This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0 - The number of consecutive NACKS generated as a result of parity errors
+ * and buffer overruns is less than or equal to the value in
+ * ET7816[RXTHRESHOLD].
+ * - 1 - The number of consecutive NACKS generated as a result of parity errors
+ * and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].
+ */
+//@{
+#define BP_UART_IS7816_RXT (0U) //!< Bit position for UART_IS7816_RXT.
+#define BM_UART_IS7816_RXT (0x01U) //!< Bit mask for UART_IS7816_RXT.
+#define BS_UART_IS7816_RXT (1U) //!< Bit field size in bits for UART_IS7816_RXT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IS7816_RXT field.
+#define BR_UART_IS7816_RXT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_RXT))
+#endif
+
+//! @brief Format value for bitfield UART_IS7816_RXT.
+#define BF_UART_IS7816_RXT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_RXT), uint8_t) & BM_UART_IS7816_RXT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXT field to a new value.
+#define BW_UART_IS7816_RXT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_RXT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_IS7816, field TXT[1] (W1C)
+ *
+ * Indicates that the transmit NACK threshold has been exceeded as indicated by
+ * ET7816[TXTHRESHOLD]. Regardless of whether this flag is set, the UART
+ * continues to retransmit indefinitely. This flag asserts only when C7816[TTYPE] = 0. If
+ * 7816E is cleared/disabled, ANACK is cleared/disabled, C2[TE] is
+ * cleared/disabled, C7816[TTYPE] = 1, or packet is transferred without receiving a NACK, the
+ * internal NACK detection counter is cleared and the count restarts from zero on
+ * the next received NACK. This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0 - The number of retries and corresponding NACKS does not exceed the value
+ * in ET7816[TXTHRESHOLD].
+ * - 1 - The number of retries and corresponding NACKS exceeds the value in
+ * ET7816[TXTHRESHOLD].
+ */
+//@{
+#define BP_UART_IS7816_TXT (1U) //!< Bit position for UART_IS7816_TXT.
+#define BM_UART_IS7816_TXT (0x02U) //!< Bit mask for UART_IS7816_TXT.
+#define BS_UART_IS7816_TXT (1U) //!< Bit field size in bits for UART_IS7816_TXT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IS7816_TXT field.
+#define BR_UART_IS7816_TXT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_TXT))
+#endif
+
+//! @brief Format value for bitfield UART_IS7816_TXT.
+#define BF_UART_IS7816_TXT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_TXT), uint8_t) & BM_UART_IS7816_TXT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXT field to a new value.
+#define BW_UART_IS7816_TXT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_TXT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_IS7816, field GTV[2] (W1C)
+ *
+ * Indicates that one or more of the character guard time, block guard time, or
+ * guard time are violated. This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0 - A guard time (GT, CGT, or BGT) has not been violated.
+ * - 1 - A guard time (GT, CGT, or BGT) has been violated.
+ */
+//@{
+#define BP_UART_IS7816_GTV (2U) //!< Bit position for UART_IS7816_GTV.
+#define BM_UART_IS7816_GTV (0x04U) //!< Bit mask for UART_IS7816_GTV.
+#define BS_UART_IS7816_GTV (1U) //!< Bit field size in bits for UART_IS7816_GTV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IS7816_GTV field.
+#define BR_UART_IS7816_GTV(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_GTV))
+#endif
+
+//! @brief Format value for bitfield UART_IS7816_GTV.
+#define BF_UART_IS7816_GTV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_GTV), uint8_t) & BM_UART_IS7816_GTV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GTV field to a new value.
+#define BW_UART_IS7816_GTV(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_GTV) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_IS7816, field INITD[4] (W1C)
+ *
+ * Indicates that a valid initial character is received. This interrupt is
+ * cleared by writing 1.
+ *
+ * Values:
+ * - 0 - A valid initial character has not been received.
+ * - 1 - A valid initial character has been received.
+ */
+//@{
+#define BP_UART_IS7816_INITD (4U) //!< Bit position for UART_IS7816_INITD.
+#define BM_UART_IS7816_INITD (0x10U) //!< Bit mask for UART_IS7816_INITD.
+#define BS_UART_IS7816_INITD (1U) //!< Bit field size in bits for UART_IS7816_INITD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IS7816_INITD field.
+#define BR_UART_IS7816_INITD(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_INITD))
+#endif
+
+//! @brief Format value for bitfield UART_IS7816_INITD.
+#define BF_UART_IS7816_INITD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_INITD), uint8_t) & BM_UART_IS7816_INITD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INITD field to a new value.
+#define BW_UART_IS7816_INITD(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_INITD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_IS7816, field BWT[5] (W1C)
+ *
+ * Indicates that the block wait time, the time between the leading edge of
+ * first received character of a block and the leading edge of the last character the
+ * previously transmitted block, has exceeded the programmed value. This flag
+ * asserts only when C7816[TTYPE] = 1.This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0 - Block wait time (BWT) has not been violated.
+ * - 1 - Block wait time (BWT) has been violated.
+ */
+//@{
+#define BP_UART_IS7816_BWT (5U) //!< Bit position for UART_IS7816_BWT.
+#define BM_UART_IS7816_BWT (0x20U) //!< Bit mask for UART_IS7816_BWT.
+#define BS_UART_IS7816_BWT (1U) //!< Bit field size in bits for UART_IS7816_BWT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IS7816_BWT field.
+#define BR_UART_IS7816_BWT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_BWT))
+#endif
+
+//! @brief Format value for bitfield UART_IS7816_BWT.
+#define BF_UART_IS7816_BWT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_BWT), uint8_t) & BM_UART_IS7816_BWT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BWT field to a new value.
+#define BW_UART_IS7816_BWT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_BWT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_IS7816, field CWT[6] (W1C)
+ *
+ * Indicates that the character wait time, the time between the leading edges of
+ * two consecutive characters in a block, has exceeded the programmed value.
+ * This flag asserts only when C7816[TTYPE] = 1. This interrupt is cleared by
+ * writing 1.
+ *
+ * Values:
+ * - 0 - Character wait time (CWT) has not been violated.
+ * - 1 - Character wait time (CWT) has been violated.
+ */
+//@{
+#define BP_UART_IS7816_CWT (6U) //!< Bit position for UART_IS7816_CWT.
+#define BM_UART_IS7816_CWT (0x40U) //!< Bit mask for UART_IS7816_CWT.
+#define BS_UART_IS7816_CWT (1U) //!< Bit field size in bits for UART_IS7816_CWT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IS7816_CWT field.
+#define BR_UART_IS7816_CWT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_CWT))
+#endif
+
+//! @brief Format value for bitfield UART_IS7816_CWT.
+#define BF_UART_IS7816_CWT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_CWT), uint8_t) & BM_UART_IS7816_CWT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CWT field to a new value.
+#define BW_UART_IS7816_CWT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_CWT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register UART_IS7816, field WT[7] (W1C)
+ *
+ * Indicates that the wait time, the time between the leading edge of a
+ * character being transmitted and the leading edge of the next response character, has
+ * exceeded the programmed value. This flag asserts only when C7816[TTYPE] = 0.
+ * This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0 - Wait time (WT) has not been violated.
+ * - 1 - Wait time (WT) has been violated.
+ */
+//@{
+#define BP_UART_IS7816_WT (7U) //!< Bit position for UART_IS7816_WT.
+#define BM_UART_IS7816_WT (0x80U) //!< Bit mask for UART_IS7816_WT.
+#define BS_UART_IS7816_WT (1U) //!< Bit field size in bits for UART_IS7816_WT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_IS7816_WT field.
+#define BR_UART_IS7816_WT(x) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_WT))
+#endif
+
+//! @brief Format value for bitfield UART_IS7816_WT.
+#define BF_UART_IS7816_WT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_IS7816_WT), uint8_t) & BM_UART_IS7816_WT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WT field to a new value.
+#define BW_UART_IS7816_WT(x, v) (BITBAND_ACCESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_WT) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_WP7816_T_TYPE0 - UART 7816 Wait Parameter Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_WP7816_T_TYPE0 - UART 7816 Wait Parameter Register (RW)
+ *
+ * Reset value: 0x0AU
+ *
+ * The WP7816 register contains constants used in the generation of various wait
+ * timer counters. To save register space, this register is used differently
+ * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
+ * time. This register must be written to only when C7816[ISO_7816E] is not set.
+ */
+typedef union _hw_uart_wp7816_t_type0
+{
+ uint8_t U;
+ struct _hw_uart_wp7816_t_type0_bitfields
+ {
+ uint8_t WI : 8; //!< [7:0] Wait Time Integer (C7816[TTYPE] = 0)
+ } B;
+} hw_uart_wp7816_t_type0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_WP7816_T_TYPE0 register
+ */
+//@{
+#define HW_UART_WP7816_T_TYPE0_ADDR(x) (REGS_UART_BASE(x) + 0x1BU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_WP7816_T_TYPE0(x) (*(__IO hw_uart_wp7816_t_type0_t *) HW_UART_WP7816_T_TYPE0_ADDR(x))
+#define HW_UART_WP7816_T_TYPE0_RD(x) (HW_UART_WP7816_T_TYPE0(x).U)
+#define HW_UART_WP7816_T_TYPE0_WR(x, v) (HW_UART_WP7816_T_TYPE0(x).U = (v))
+#define HW_UART_WP7816_T_TYPE0_SET(x, v) (HW_UART_WP7816_T_TYPE0_WR(x, HW_UART_WP7816_T_TYPE0_RD(x) | (v)))
+#define HW_UART_WP7816_T_TYPE0_CLR(x, v) (HW_UART_WP7816_T_TYPE0_WR(x, HW_UART_WP7816_T_TYPE0_RD(x) & ~(v)))
+#define HW_UART_WP7816_T_TYPE0_TOG(x, v) (HW_UART_WP7816_T_TYPE0_WR(x, HW_UART_WP7816_T_TYPE0_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_WP7816_T_TYPE0 bitfields
+ */
+
+/*!
+ * @name Register UART_WP7816_T_TYPE0, field WI[7:0] (RW)
+ *
+ * Used to calculate the value used for the WT counter. It represents a value
+ * between 1 and 255. The value of zero is not valid. This value is used only when
+ * C7816[TTYPE] = 0. See Wait time and guard time parameters.
+ */
+//@{
+#define BP_UART_WP7816_T_TYPE0_WI (0U) //!< Bit position for UART_WP7816_T_TYPE0_WI.
+#define BM_UART_WP7816_T_TYPE0_WI (0xFFU) //!< Bit mask for UART_WP7816_T_TYPE0_WI.
+#define BS_UART_WP7816_T_TYPE0_WI (8U) //!< Bit field size in bits for UART_WP7816_T_TYPE0_WI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_WP7816_T_TYPE0_WI field.
+#define BR_UART_WP7816_T_TYPE0_WI(x) (HW_UART_WP7816_T_TYPE0(x).U)
+#endif
+
+//! @brief Format value for bitfield UART_WP7816_T_TYPE0_WI.
+#define BF_UART_WP7816_T_TYPE0_WI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_WP7816_T_TYPE0_WI), uint8_t) & BM_UART_WP7816_T_TYPE0_WI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WI field to a new value.
+#define BW_UART_WP7816_T_TYPE0_WI(x, v) (HW_UART_WP7816_T_TYPE0_WR(x, v))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_UART_WP7816_T_TYPE1 - UART 7816 Wait Parameter Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_WP7816_T_TYPE1 - UART 7816 Wait Parameter Register (RW)
+ *
+ * Reset value: 0x0AU
+ *
+ * The WP7816 register contains constants used in the generation of various wait
+ * timer counters. To save register space, this register is used differently
+ * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
+ * time. This register must be written to only when C7816[ISO_7816E] is not set.
+ */
+typedef union _hw_uart_wp7816_t_type1
+{
+ uint8_t U;
+ struct _hw_uart_wp7816_t_type1_bitfields
+ {
+ uint8_t BWI : 4; //!< [3:0] Block Wait Time Integer(C7816[TTYPE] = 1)
+ uint8_t CWI : 4; //!< [7:4] Character Wait Time Integer (C7816[TTYPE]
+ //! = 1)
+ } B;
+} hw_uart_wp7816_t_type1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_WP7816_T_TYPE1 register
+ */
+//@{
+#define HW_UART_WP7816_T_TYPE1_ADDR(x) (REGS_UART_BASE(x) + 0x1BU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_WP7816_T_TYPE1(x) (*(__IO hw_uart_wp7816_t_type1_t *) HW_UART_WP7816_T_TYPE1_ADDR(x))
+#define HW_UART_WP7816_T_TYPE1_RD(x) (HW_UART_WP7816_T_TYPE1(x).U)
+#define HW_UART_WP7816_T_TYPE1_WR(x, v) (HW_UART_WP7816_T_TYPE1(x).U = (v))
+#define HW_UART_WP7816_T_TYPE1_SET(x, v) (HW_UART_WP7816_T_TYPE1_WR(x, HW_UART_WP7816_T_TYPE1_RD(x) | (v)))
+#define HW_UART_WP7816_T_TYPE1_CLR(x, v) (HW_UART_WP7816_T_TYPE1_WR(x, HW_UART_WP7816_T_TYPE1_RD(x) & ~(v)))
+#define HW_UART_WP7816_T_TYPE1_TOG(x, v) (HW_UART_WP7816_T_TYPE1_WR(x, HW_UART_WP7816_T_TYPE1_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_WP7816_T_TYPE1 bitfields
+ */
+
+/*!
+ * @name Register UART_WP7816_T_TYPE1, field BWI[3:0] (RW)
+ *
+ * Used to calculate the value used for the BWT counter. It represent a value
+ * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
+ * and guard time parameters .
+ */
+//@{
+#define BP_UART_WP7816_T_TYPE1_BWI (0U) //!< Bit position for UART_WP7816_T_TYPE1_BWI.
+#define BM_UART_WP7816_T_TYPE1_BWI (0x0FU) //!< Bit mask for UART_WP7816_T_TYPE1_BWI.
+#define BS_UART_WP7816_T_TYPE1_BWI (4U) //!< Bit field size in bits for UART_WP7816_T_TYPE1_BWI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_WP7816_T_TYPE1_BWI field.
+#define BR_UART_WP7816_T_TYPE1_BWI(x) (HW_UART_WP7816_T_TYPE1(x).B.BWI)
+#endif
+
+//! @brief Format value for bitfield UART_WP7816_T_TYPE1_BWI.
+#define BF_UART_WP7816_T_TYPE1_BWI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_WP7816_T_TYPE1_BWI), uint8_t) & BM_UART_WP7816_T_TYPE1_BWI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BWI field to a new value.
+#define BW_UART_WP7816_T_TYPE1_BWI(x, v) (HW_UART_WP7816_T_TYPE1_WR(x, (HW_UART_WP7816_T_TYPE1_RD(x) & ~BM_UART_WP7816_T_TYPE1_BWI) | BF_UART_WP7816_T_TYPE1_BWI(v)))
+#endif
+//@}
+
+/*!
+ * @name Register UART_WP7816_T_TYPE1, field CWI[7:4] (RW)
+ *
+ * Used to calculate the value used for the CWT counter. It represents a value
+ * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
+ * and guard time parameters .
+ */
+//@{
+#define BP_UART_WP7816_T_TYPE1_CWI (4U) //!< Bit position for UART_WP7816_T_TYPE1_CWI.
+#define BM_UART_WP7816_T_TYPE1_CWI (0xF0U) //!< Bit mask for UART_WP7816_T_TYPE1_CWI.
+#define BS_UART_WP7816_T_TYPE1_CWI (4U) //!< Bit field size in bits for UART_WP7816_T_TYPE1_CWI.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_WP7816_T_TYPE1_CWI field.
+#define BR_UART_WP7816_T_TYPE1_CWI(x) (HW_UART_WP7816_T_TYPE1(x).B.CWI)
+#endif
+
+//! @brief Format value for bitfield UART_WP7816_T_TYPE1_CWI.
+#define BF_UART_WP7816_T_TYPE1_CWI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_WP7816_T_TYPE1_CWI), uint8_t) & BM_UART_WP7816_T_TYPE1_CWI)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CWI field to a new value.
+#define BW_UART_WP7816_T_TYPE1_CWI(x, v) (HW_UART_WP7816_T_TYPE1_WR(x, (HW_UART_WP7816_T_TYPE1_RD(x) & ~BM_UART_WP7816_T_TYPE1_CWI) | BF_UART_WP7816_T_TYPE1_CWI(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_WN7816 - UART 7816 Wait N Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_WN7816 - UART 7816 Wait N Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The WN7816 register contains a parameter that is used in the calculation of
+ * the guard time counter. This register may be read at any time. This register
+ * must be written to only when C7816[ISO_7816E] is not set.
+ */
+typedef union _hw_uart_wn7816
+{
+ uint8_t U;
+ struct _hw_uart_wn7816_bitfields
+ {
+ uint8_t GTN : 8; //!< [7:0] Guard Band N
+ } B;
+} hw_uart_wn7816_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_WN7816 register
+ */
+//@{
+#define HW_UART_WN7816_ADDR(x) (REGS_UART_BASE(x) + 0x1CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_WN7816(x) (*(__IO hw_uart_wn7816_t *) HW_UART_WN7816_ADDR(x))
+#define HW_UART_WN7816_RD(x) (HW_UART_WN7816(x).U)
+#define HW_UART_WN7816_WR(x, v) (HW_UART_WN7816(x).U = (v))
+#define HW_UART_WN7816_SET(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) | (v)))
+#define HW_UART_WN7816_CLR(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) & ~(v)))
+#define HW_UART_WN7816_TOG(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_WN7816 bitfields
+ */
+
+/*!
+ * @name Register UART_WN7816, field GTN[7:0] (RW)
+ *
+ * Defines a parameter used in the calculation of GT, CGT, and BGT counters. The
+ * value represents an integer number between 0 and 255. See Wait time and guard
+ * time parameters .
+ */
+//@{
+#define BP_UART_WN7816_GTN (0U) //!< Bit position for UART_WN7816_GTN.
+#define BM_UART_WN7816_GTN (0xFFU) //!< Bit mask for UART_WN7816_GTN.
+#define BS_UART_WN7816_GTN (8U) //!< Bit field size in bits for UART_WN7816_GTN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_WN7816_GTN field.
+#define BR_UART_WN7816_GTN(x) (HW_UART_WN7816(x).U)
+#endif
+
+//! @brief Format value for bitfield UART_WN7816_GTN.
+#define BF_UART_WN7816_GTN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_WN7816_GTN), uint8_t) & BM_UART_WN7816_GTN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GTN field to a new value.
+#define BW_UART_WN7816_GTN(x, v) (HW_UART_WN7816_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_WF7816 - UART 7816 Wait FD Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_WF7816 - UART 7816 Wait FD Register (RW)
+ *
+ * Reset value: 0x01U
+ *
+ * The WF7816 contains parameters that are used in the generation of various
+ * counters including GT, CGT, BGT, WT, and BWT. This register may be read at any
+ * time. This register must be written to only when C7816[ISO_7816E] is not set.
+ */
+typedef union _hw_uart_wf7816
+{
+ uint8_t U;
+ struct _hw_uart_wf7816_bitfields
+ {
+ uint8_t GTFD : 8; //!< [7:0] FD Multiplier
+ } B;
+} hw_uart_wf7816_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_WF7816 register
+ */
+//@{
+#define HW_UART_WF7816_ADDR(x) (REGS_UART_BASE(x) + 0x1DU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_WF7816(x) (*(__IO hw_uart_wf7816_t *) HW_UART_WF7816_ADDR(x))
+#define HW_UART_WF7816_RD(x) (HW_UART_WF7816(x).U)
+#define HW_UART_WF7816_WR(x, v) (HW_UART_WF7816(x).U = (v))
+#define HW_UART_WF7816_SET(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) | (v)))
+#define HW_UART_WF7816_CLR(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) & ~(v)))
+#define HW_UART_WF7816_TOG(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_WF7816 bitfields
+ */
+
+/*!
+ * @name Register UART_WF7816, field GTFD[7:0] (RW)
+ *
+ * Used as another multiplier in the calculation of WT and BWT. This value
+ * represents a number between 1 and 255. The value of 0 is invalid. This value is not
+ * used in baud rate generation. See Wait time and guard time parameters and
+ * Baud rate generation .
+ */
+//@{
+#define BP_UART_WF7816_GTFD (0U) //!< Bit position for UART_WF7816_GTFD.
+#define BM_UART_WF7816_GTFD (0xFFU) //!< Bit mask for UART_WF7816_GTFD.
+#define BS_UART_WF7816_GTFD (8U) //!< Bit field size in bits for UART_WF7816_GTFD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_WF7816_GTFD field.
+#define BR_UART_WF7816_GTFD(x) (HW_UART_WF7816(x).U)
+#endif
+
+//! @brief Format value for bitfield UART_WF7816_GTFD.
+#define BF_UART_WF7816_GTFD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_WF7816_GTFD), uint8_t) & BM_UART_WF7816_GTFD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the GTFD field to a new value.
+#define BW_UART_WF7816_GTFD(x, v) (HW_UART_WF7816_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_ET7816 - UART 7816 Error Threshold Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_ET7816 - UART 7816 Error Threshold Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The ET7816 register contains fields that determine the number of NACKs that
+ * must be received or transmitted before the host processor is notified. This
+ * register may be read at anytime. This register must be written to only when
+ * C7816[ISO_7816E] is not set.
+ */
+typedef union _hw_uart_et7816
+{
+ uint8_t U;
+ struct _hw_uart_et7816_bitfields
+ {
+ uint8_t RXTHRESHOLD : 4; //!< [3:0] Receive NACK Threshold
+ uint8_t TXTHRESHOLD : 4; //!< [7:4] Transmit NACK Threshold
+ } B;
+} hw_uart_et7816_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_ET7816 register
+ */
+//@{
+#define HW_UART_ET7816_ADDR(x) (REGS_UART_BASE(x) + 0x1EU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_ET7816(x) (*(__IO hw_uart_et7816_t *) HW_UART_ET7816_ADDR(x))
+#define HW_UART_ET7816_RD(x) (HW_UART_ET7816(x).U)
+#define HW_UART_ET7816_WR(x, v) (HW_UART_ET7816(x).U = (v))
+#define HW_UART_ET7816_SET(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) | (v)))
+#define HW_UART_ET7816_CLR(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) & ~(v)))
+#define HW_UART_ET7816_TOG(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_ET7816 bitfields
+ */
+
+/*!
+ * @name Register UART_ET7816, field RXTHRESHOLD[3:0] (RW)
+ *
+ * The value written to this field indicates the maximum number of consecutive
+ * NACKs generated as a result of a parity error or receiver buffer overruns
+ * before the host processor is notified. After the counter exceeds that value in the
+ * field, the IS7816[RXT] is asserted. This field is meaningful only when
+ * C7816[TTYPE] = 0. The value read from this field represents the number of consecutive
+ * NACKs that have been transmitted since the last successful reception. This
+ * counter saturates at 4'hF and does not wrap around. Regardless of the number of
+ * NACKs sent, the UART continues to receive valid packets indefinitely. For
+ * additional information, see IS7816[RXT] field description.
+ */
+//@{
+#define BP_UART_ET7816_RXTHRESHOLD (0U) //!< Bit position for UART_ET7816_RXTHRESHOLD.
+#define BM_UART_ET7816_RXTHRESHOLD (0x0FU) //!< Bit mask for UART_ET7816_RXTHRESHOLD.
+#define BS_UART_ET7816_RXTHRESHOLD (4U) //!< Bit field size in bits for UART_ET7816_RXTHRESHOLD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_ET7816_RXTHRESHOLD field.
+#define BR_UART_ET7816_RXTHRESHOLD(x) (HW_UART_ET7816(x).B.RXTHRESHOLD)
+#endif
+
+//! @brief Format value for bitfield UART_ET7816_RXTHRESHOLD.
+#define BF_UART_ET7816_RXTHRESHOLD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_ET7816_RXTHRESHOLD), uint8_t) & BM_UART_ET7816_RXTHRESHOLD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RXTHRESHOLD field to a new value.
+#define BW_UART_ET7816_RXTHRESHOLD(x, v) (HW_UART_ET7816_WR(x, (HW_UART_ET7816_RD(x) & ~BM_UART_ET7816_RXTHRESHOLD) | BF_UART_ET7816_RXTHRESHOLD(v)))
+#endif
+//@}
+
+/*!
+ * @name Register UART_ET7816, field TXTHRESHOLD[7:4] (RW)
+ *
+ * The value written to this field indicates the maximum number of failed
+ * attempts (NACKs) a transmitted character can have before the host processor is
+ * notified. This field is meaningful only when C7816[TTYPE] = 0 and C7816[ANACK] = 1.
+ * The value read from this field represents the number of consecutive NACKs
+ * that have been received since the last successful transmission. This counter
+ * saturates at 4'hF and does not wrap around. Regardless of how many NACKs that are
+ * received, the UART continues to retransmit indefinitely. This flag only
+ * asserts when C7816[TTYPE] = 0. For additional information see the IS7816[TXT] field
+ * description.
+ *
+ * Values:
+ * - 0 - TXT asserts on the first NACK that is received.
+ * - 1 - TXT asserts on the second NACK that is received.
+ */
+//@{
+#define BP_UART_ET7816_TXTHRESHOLD (4U) //!< Bit position for UART_ET7816_TXTHRESHOLD.
+#define BM_UART_ET7816_TXTHRESHOLD (0xF0U) //!< Bit mask for UART_ET7816_TXTHRESHOLD.
+#define BS_UART_ET7816_TXTHRESHOLD (4U) //!< Bit field size in bits for UART_ET7816_TXTHRESHOLD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_ET7816_TXTHRESHOLD field.
+#define BR_UART_ET7816_TXTHRESHOLD(x) (HW_UART_ET7816(x).B.TXTHRESHOLD)
+#endif
+
+//! @brief Format value for bitfield UART_ET7816_TXTHRESHOLD.
+#define BF_UART_ET7816_TXTHRESHOLD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_ET7816_TXTHRESHOLD), uint8_t) & BM_UART_ET7816_TXTHRESHOLD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXTHRESHOLD field to a new value.
+#define BW_UART_ET7816_TXTHRESHOLD(x, v) (HW_UART_ET7816_WR(x, (HW_UART_ET7816_RD(x) & ~BM_UART_ET7816_TXTHRESHOLD) | BF_UART_ET7816_TXTHRESHOLD(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_UART_TL7816 - UART 7816 Transmit Length Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_UART_TL7816 - UART 7816 Transmit Length Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The TL7816 register is used to indicate the number of characters contained in
+ * the block being transmitted. This register is used only when C7816[TTYPE] =
+ * 1. This register may be read at anytime. This register must be written only
+ * when C2[TE] is not enabled.
+ */
+typedef union _hw_uart_tl7816
+{
+ uint8_t U;
+ struct _hw_uart_tl7816_bitfields
+ {
+ uint8_t TLEN : 8; //!< [7:0] Transmit Length
+ } B;
+} hw_uart_tl7816_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire UART_TL7816 register
+ */
+//@{
+#define HW_UART_TL7816_ADDR(x) (REGS_UART_BASE(x) + 0x1FU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_UART_TL7816(x) (*(__IO hw_uart_tl7816_t *) HW_UART_TL7816_ADDR(x))
+#define HW_UART_TL7816_RD(x) (HW_UART_TL7816(x).U)
+#define HW_UART_TL7816_WR(x, v) (HW_UART_TL7816(x).U = (v))
+#define HW_UART_TL7816_SET(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) | (v)))
+#define HW_UART_TL7816_CLR(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) & ~(v)))
+#define HW_UART_TL7816_TOG(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual UART_TL7816 bitfields
+ */
+
+/*!
+ * @name Register UART_TL7816, field TLEN[7:0] (RW)
+ *
+ * This value plus four indicates the number of characters contained in the
+ * block being transmitted. This register is automatically decremented by 1 for each
+ * character in the information field portion of the block. Additionally, this
+ * register is automatically decremented by 1 for the first character of a CRC in
+ * the epilogue field. Therefore, this register must be programmed with the number
+ * of bytes in the data packet if an LRC is being transmitted, and the number of
+ * bytes + 1 if a CRC is being transmitted. This register is not decremented for
+ * characters that are assumed to be part of the Prologue field, that is, the
+ * first three characters transmitted in a block, or the LRC or last CRC character
+ * in the Epilogue field, that is, the last character transmitted. This field
+ * must be programed or adjusted only when C2[TE] is cleared.
+ */
+//@{
+#define BP_UART_TL7816_TLEN (0U) //!< Bit position for UART_TL7816_TLEN.
+#define BM_UART_TL7816_TLEN (0xFFU) //!< Bit mask for UART_TL7816_TLEN.
+#define BS_UART_TL7816_TLEN (8U) //!< Bit field size in bits for UART_TL7816_TLEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the UART_TL7816_TLEN field.
+#define BR_UART_TL7816_TLEN(x) (HW_UART_TL7816(x).U)
+#endif
+
+//! @brief Format value for bitfield UART_TL7816_TLEN.
+#define BF_UART_TL7816_TLEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_UART_TL7816_TLEN), uint8_t) & BM_UART_TL7816_TLEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TLEN field to a new value.
+#define BW_UART_TL7816_TLEN(x, v) (HW_UART_TL7816_WR(x, v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_uart_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All UART module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_uart
+{
+ __IO hw_uart_bdh_t BDH; //!< [0x0] UART Baud Rate Registers: High
+ __IO hw_uart_bdl_t BDL; //!< [0x1] UART Baud Rate Registers: Low
+ __IO hw_uart_c1_t C1; //!< [0x2] UART Control Register 1
+ __IO hw_uart_c2_t C2; //!< [0x3] UART Control Register 2
+ __I hw_uart_s1_t S1; //!< [0x4] UART Status Register 1
+ __IO hw_uart_s2_t S2; //!< [0x5] UART Status Register 2
+ __IO hw_uart_c3_t C3; //!< [0x6] UART Control Register 3
+ __IO hw_uart_d_t D; //!< [0x7] UART Data Register
+ __IO hw_uart_ma1_t MA1; //!< [0x8] UART Match Address Registers 1
+ __IO hw_uart_ma2_t MA2; //!< [0x9] UART Match Address Registers 2
+ __IO hw_uart_c4_t C4; //!< [0xA] UART Control Register 4
+ __IO hw_uart_c5_t C5; //!< [0xB] UART Control Register 5
+ __I hw_uart_ed_t ED; //!< [0xC] UART Extended Data Register
+ __IO hw_uart_modem_t MODEM; //!< [0xD] UART Modem Register
+ __IO hw_uart_ir_t IR; //!< [0xE] UART Infrared Register
+ uint8_t _reserved0[1];
+ __IO hw_uart_pfifo_t PFIFO; //!< [0x10] UART FIFO Parameters
+ __IO hw_uart_cfifo_t CFIFO; //!< [0x11] UART FIFO Control Register
+ __IO hw_uart_sfifo_t SFIFO; //!< [0x12] UART FIFO Status Register
+ __IO hw_uart_twfifo_t TWFIFO; //!< [0x13] UART FIFO Transmit Watermark
+ __I hw_uart_tcfifo_t TCFIFO; //!< [0x14] UART FIFO Transmit Count
+ __IO hw_uart_rwfifo_t RWFIFO; //!< [0x15] UART FIFO Receive Watermark
+ __I hw_uart_rcfifo_t RCFIFO; //!< [0x16] UART FIFO Receive Count
+ uint8_t _reserved1[1];
+ __IO hw_uart_c7816_t C7816; //!< [0x18] UART 7816 Control Register
+ __IO hw_uart_ie7816_t IE7816; //!< [0x19] UART 7816 Interrupt Enable Register
+ __IO hw_uart_is7816_t IS7816; //!< [0x1A] UART 7816 Interrupt Status Register
+ union {
+ __IO hw_uart_wp7816_t_type0_t WP7816_T_TYPE0; //!< [0x1B] UART 7816 Wait Parameter Register
+ __IO hw_uart_wp7816_t_type1_t WP7816_T_TYPE1; //!< [0x1B] UART 7816 Wait Parameter Register
+ };
+ __IO hw_uart_wn7816_t WN7816; //!< [0x1C] UART 7816 Wait N Register
+ __IO hw_uart_wf7816_t WF7816; //!< [0x1D] UART 7816 Wait FD Register
+ __IO hw_uart_et7816_t ET7816; //!< [0x1E] UART 7816 Error Threshold Register
+ __IO hw_uart_tl7816_t TL7816; //!< [0x1F] UART 7816 Transmit Length Register
+} hw_uart_t;
+#pragma pack()
+
+//! @brief Macro to access all UART registers.
+//! @param x UART instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_UART(0)</code>.
+#define HW_UART(x) (*(hw_uart_t *) REGS_UART_BASE(x))
+#endif
+
+#endif // __HW_UART_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_usb.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,4276 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_USB_REGISTERS_H__
+#define __HW_USB_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 USB
+ *
+ * Universal Serial Bus, OTG Capable Controller
+ *
+ * Registers defined in this header file:
+ * - HW_USB_PERID - Peripheral ID register
+ * - HW_USB_IDCOMP - Peripheral ID Complement register
+ * - HW_USB_REV - Peripheral Revision register
+ * - HW_USB_ADDINFO - Peripheral Additional Info register
+ * - HW_USB_OTGISTAT - OTG Interrupt Status register
+ * - HW_USB_OTGICR - OTG Interrupt Control register
+ * - HW_USB_OTGSTAT - OTG Status register
+ * - HW_USB_OTGCTL - OTG Control register
+ * - HW_USB_ISTAT - Interrupt Status register
+ * - HW_USB_INTEN - Interrupt Enable register
+ * - HW_USB_ERRSTAT - Error Interrupt Status register
+ * - HW_USB_ERREN - Error Interrupt Enable register
+ * - HW_USB_STAT - Status register
+ * - HW_USB_CTL - Control register
+ * - HW_USB_ADDR - Address register
+ * - HW_USB_BDTPAGE1 - BDT Page register 1
+ * - HW_USB_FRMNUML - Frame Number register Low
+ * - HW_USB_FRMNUMH - Frame Number register High
+ * - HW_USB_TOKEN - Token register
+ * - HW_USB_SOFTHLD - SOF Threshold register
+ * - HW_USB_BDTPAGE2 - BDT Page Register 2
+ * - HW_USB_BDTPAGE3 - BDT Page Register 3
+ * - HW_USB_ENDPTn - Endpoint Control register
+ * - HW_USB_USBCTRL - USB Control register
+ * - HW_USB_OBSERVE - USB OTG Observe register
+ * - HW_USB_CONTROL - USB OTG Control register
+ * - HW_USB_USBTRC0 - USB Transceiver Control register 0
+ * - HW_USB_USBFRMADJUST - Frame Adjust Register
+ * - HW_USB_CLK_RECOVER_CTRL - USB Clock recovery control
+ * - HW_USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register
+ * - HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status
+ *
+ * - hw_usb_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_USB_BASE
+#define HW_USB_INSTANCE_COUNT (1U) //!< Number of instances of the USB module.
+#define REGS_USB_BASE (0x40072000U) //!< Base address for USB0.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_PERID - Peripheral ID register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_PERID - Peripheral ID register (RO)
+ *
+ * Reset value: 0x04U
+ *
+ * Reads back the value of 0x04. This value is defined for the USB peripheral.
+ */
+typedef union _hw_usb_perid
+{
+ uint8_t U;
+ struct _hw_usb_perid_bitfields
+ {
+ uint8_t ID : 6; //!< [5:0] Peripheral Identification
+ uint8_t RESERVED0 : 2; //!< [7:6]
+ } B;
+} hw_usb_perid_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_PERID register
+ */
+//@{
+#define HW_USB_PERID_ADDR (REGS_USB_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_PERID (*(__I hw_usb_perid_t *) HW_USB_PERID_ADDR)
+#define HW_USB_PERID_RD() (HW_USB_PERID.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_PERID bitfields
+ */
+
+/*!
+ * @name Register USB_PERID, field ID[5:0] (RO)
+ *
+ * This field always reads 0x4h.
+ */
+//@{
+#define BP_USB_PERID_ID (0U) //!< Bit position for USB_PERID_ID.
+#define BM_USB_PERID_ID (0x3FU) //!< Bit mask for USB_PERID_ID.
+#define BS_USB_PERID_ID (6U) //!< Bit field size in bits for USB_PERID_ID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_PERID_ID field.
+#define BR_USB_PERID_ID (HW_USB_PERID.B.ID)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_IDCOMP - Peripheral ID Complement register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_IDCOMP - Peripheral ID Complement register (RO)
+ *
+ * Reset value: 0xFBU
+ *
+ * Reads back the complement of the Peripheral ID register. For the USB
+ * peripheral, the value is 0xFB.
+ */
+typedef union _hw_usb_idcomp
+{
+ uint8_t U;
+ struct _hw_usb_idcomp_bitfields
+ {
+ uint8_t NID : 6; //!< [5:0]
+ uint8_t RESERVED0 : 2; //!< [7:6]
+ } B;
+} hw_usb_idcomp_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_IDCOMP register
+ */
+//@{
+#define HW_USB_IDCOMP_ADDR (REGS_USB_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_IDCOMP (*(__I hw_usb_idcomp_t *) HW_USB_IDCOMP_ADDR)
+#define HW_USB_IDCOMP_RD() (HW_USB_IDCOMP.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_IDCOMP bitfields
+ */
+
+/*!
+ * @name Register USB_IDCOMP, field NID[5:0] (RO)
+ *
+ * Ones' complement of PERID[ID]. bits.
+ */
+//@{
+#define BP_USB_IDCOMP_NID (0U) //!< Bit position for USB_IDCOMP_NID.
+#define BM_USB_IDCOMP_NID (0x3FU) //!< Bit mask for USB_IDCOMP_NID.
+#define BS_USB_IDCOMP_NID (6U) //!< Bit field size in bits for USB_IDCOMP_NID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_IDCOMP_NID field.
+#define BR_USB_IDCOMP_NID (HW_USB_IDCOMP.B.NID)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_REV - Peripheral Revision register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_REV - Peripheral Revision register (RO)
+ *
+ * Reset value: 0x33U
+ *
+ * Contains the revision number of the USB module.
+ */
+typedef union _hw_usb_rev
+{
+ uint8_t U;
+ struct _hw_usb_rev_bitfields
+ {
+ uint8_t REV : 8; //!< [7:0] Revision
+ } B;
+} hw_usb_rev_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_REV register
+ */
+//@{
+#define HW_USB_REV_ADDR (REGS_USB_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_REV (*(__I hw_usb_rev_t *) HW_USB_REV_ADDR)
+#define HW_USB_REV_RD() (HW_USB_REV.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_REV bitfields
+ */
+
+/*!
+ * @name Register USB_REV, field REV[7:0] (RO)
+ *
+ * Indicates the revision number of the USB Core.
+ */
+//@{
+#define BP_USB_REV_REV (0U) //!< Bit position for USB_REV_REV.
+#define BM_USB_REV_REV (0xFFU) //!< Bit mask for USB_REV_REV.
+#define BS_USB_REV_REV (8U) //!< Bit field size in bits for USB_REV_REV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_REV_REV field.
+#define BR_USB_REV_REV (HW_USB_REV.U)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_ADDINFO - Peripheral Additional Info register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_ADDINFO - Peripheral Additional Info register (RO)
+ *
+ * Reset value: 0x01U
+ *
+ * Reads back the value of the fixed Interrupt Request Level (IRQNUM) along with
+ * the Host Enable bit.
+ */
+typedef union _hw_usb_addinfo
+{
+ uint8_t U;
+ struct _hw_usb_addinfo_bitfields
+ {
+ uint8_t IEHOST : 1; //!< [0]
+ uint8_t RESERVED0 : 2; //!< [2:1]
+ uint8_t IRQNUM : 5; //!< [7:3] Assigned Interrupt Request Number
+ } B;
+} hw_usb_addinfo_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_ADDINFO register
+ */
+//@{
+#define HW_USB_ADDINFO_ADDR (REGS_USB_BASE + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_ADDINFO (*(__I hw_usb_addinfo_t *) HW_USB_ADDINFO_ADDR)
+#define HW_USB_ADDINFO_RD() (HW_USB_ADDINFO.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_ADDINFO bitfields
+ */
+
+/*!
+ * @name Register USB_ADDINFO, field IEHOST[0] (RO)
+ *
+ * This bit is set if host mode is enabled.
+ */
+//@{
+#define BP_USB_ADDINFO_IEHOST (0U) //!< Bit position for USB_ADDINFO_IEHOST.
+#define BM_USB_ADDINFO_IEHOST (0x01U) //!< Bit mask for USB_ADDINFO_IEHOST.
+#define BS_USB_ADDINFO_IEHOST (1U) //!< Bit field size in bits for USB_ADDINFO_IEHOST.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ADDINFO_IEHOST field.
+#define BR_USB_ADDINFO_IEHOST (BITBAND_ACCESS8(HW_USB_ADDINFO_ADDR, BP_USB_ADDINFO_IEHOST))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ADDINFO, field IRQNUM[7:3] (RO)
+ */
+//@{
+#define BP_USB_ADDINFO_IRQNUM (3U) //!< Bit position for USB_ADDINFO_IRQNUM.
+#define BM_USB_ADDINFO_IRQNUM (0xF8U) //!< Bit mask for USB_ADDINFO_IRQNUM.
+#define BS_USB_ADDINFO_IRQNUM (5U) //!< Bit field size in bits for USB_ADDINFO_IRQNUM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ADDINFO_IRQNUM field.
+#define BR_USB_ADDINFO_IRQNUM (HW_USB_ADDINFO.B.IRQNUM)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_OTGISTAT - OTG Interrupt Status register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_OTGISTAT - OTG Interrupt Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Records changes of the ID sense and VBUS signals. Software can read this
+ * register to determine the event that triggers an interrupt. Only bits that have
+ * changed since the last software read are set. Writing a one to a bit clears the
+ * associated interrupt.
+ */
+typedef union _hw_usb_otgistat
+{
+ uint8_t U;
+ struct _hw_usb_otgistat_bitfields
+ {
+ uint8_t AVBUSCHG : 1; //!< [0]
+ uint8_t RESERVED0 : 1; //!< [1]
+ uint8_t B_SESS_CHG : 1; //!< [2]
+ uint8_t SESSVLDCHG : 1; //!< [3]
+ uint8_t RESERVED1 : 1; //!< [4]
+ uint8_t LINE_STATE_CHG : 1; //!< [5]
+ uint8_t ONEMSEC : 1; //!< [6]
+ uint8_t IDCHG : 1; //!< [7]
+ } B;
+} hw_usb_otgistat_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_OTGISTAT register
+ */
+//@{
+#define HW_USB_OTGISTAT_ADDR (REGS_USB_BASE + 0x10U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_OTGISTAT (*(__IO hw_usb_otgistat_t *) HW_USB_OTGISTAT_ADDR)
+#define HW_USB_OTGISTAT_RD() (HW_USB_OTGISTAT.U)
+#define HW_USB_OTGISTAT_WR(v) (HW_USB_OTGISTAT.U = (v))
+#define HW_USB_OTGISTAT_SET(v) (HW_USB_OTGISTAT_WR(HW_USB_OTGISTAT_RD() | (v)))
+#define HW_USB_OTGISTAT_CLR(v) (HW_USB_OTGISTAT_WR(HW_USB_OTGISTAT_RD() & ~(v)))
+#define HW_USB_OTGISTAT_TOG(v) (HW_USB_OTGISTAT_WR(HW_USB_OTGISTAT_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_OTGISTAT bitfields
+ */
+
+/*!
+ * @name Register USB_OTGISTAT, field AVBUSCHG[0] (RW)
+ *
+ * This bit is set when a change in VBUS is detected on an A device.
+ */
+//@{
+#define BP_USB_OTGISTAT_AVBUSCHG (0U) //!< Bit position for USB_OTGISTAT_AVBUSCHG.
+#define BM_USB_OTGISTAT_AVBUSCHG (0x01U) //!< Bit mask for USB_OTGISTAT_AVBUSCHG.
+#define BS_USB_OTGISTAT_AVBUSCHG (1U) //!< Bit field size in bits for USB_OTGISTAT_AVBUSCHG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGISTAT_AVBUSCHG field.
+#define BR_USB_OTGISTAT_AVBUSCHG (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_AVBUSCHG))
+#endif
+
+//! @brief Format value for bitfield USB_OTGISTAT_AVBUSCHG.
+#define BF_USB_OTGISTAT_AVBUSCHG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGISTAT_AVBUSCHG), uint8_t) & BM_USB_OTGISTAT_AVBUSCHG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AVBUSCHG field to a new value.
+#define BW_USB_OTGISTAT_AVBUSCHG(v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_AVBUSCHG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGISTAT, field B_SESS_CHG[2] (RW)
+ *
+ * This bit is set when a change in VBUS is detected on a B device.
+ */
+//@{
+#define BP_USB_OTGISTAT_B_SESS_CHG (2U) //!< Bit position for USB_OTGISTAT_B_SESS_CHG.
+#define BM_USB_OTGISTAT_B_SESS_CHG (0x04U) //!< Bit mask for USB_OTGISTAT_B_SESS_CHG.
+#define BS_USB_OTGISTAT_B_SESS_CHG (1U) //!< Bit field size in bits for USB_OTGISTAT_B_SESS_CHG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGISTAT_B_SESS_CHG field.
+#define BR_USB_OTGISTAT_B_SESS_CHG (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_B_SESS_CHG))
+#endif
+
+//! @brief Format value for bitfield USB_OTGISTAT_B_SESS_CHG.
+#define BF_USB_OTGISTAT_B_SESS_CHG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGISTAT_B_SESS_CHG), uint8_t) & BM_USB_OTGISTAT_B_SESS_CHG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the B_SESS_CHG field to a new value.
+#define BW_USB_OTGISTAT_B_SESS_CHG(v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_B_SESS_CHG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGISTAT, field SESSVLDCHG[3] (RW)
+ *
+ * This bit is set when a change in VBUS is detected indicating a session valid
+ * or a session no longer valid.
+ */
+//@{
+#define BP_USB_OTGISTAT_SESSVLDCHG (3U) //!< Bit position for USB_OTGISTAT_SESSVLDCHG.
+#define BM_USB_OTGISTAT_SESSVLDCHG (0x08U) //!< Bit mask for USB_OTGISTAT_SESSVLDCHG.
+#define BS_USB_OTGISTAT_SESSVLDCHG (1U) //!< Bit field size in bits for USB_OTGISTAT_SESSVLDCHG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGISTAT_SESSVLDCHG field.
+#define BR_USB_OTGISTAT_SESSVLDCHG (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_SESSVLDCHG))
+#endif
+
+//! @brief Format value for bitfield USB_OTGISTAT_SESSVLDCHG.
+#define BF_USB_OTGISTAT_SESSVLDCHG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGISTAT_SESSVLDCHG), uint8_t) & BM_USB_OTGISTAT_SESSVLDCHG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SESSVLDCHG field to a new value.
+#define BW_USB_OTGISTAT_SESSVLDCHG(v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_SESSVLDCHG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGISTAT, field LINE_STATE_CHG[5] (RW)
+ *
+ * This interrupt is set when the USB line state (CTL[SE0] and CTL[JSTATE] bits)
+ * are stable without change for 1 millisecond, and the value of the line state
+ * is different from the last time when the line state was stable. It is set on
+ * transitions between SE0 and J-state, SE0 and K-state, and J-state and K-state.
+ * Changes in J-state while SE0 is true do not cause an interrupt. This interrupt
+ * can be used in detecting Reset, Resume, Connect, and Data Line Pulse
+ * signaling.
+ */
+//@{
+#define BP_USB_OTGISTAT_LINE_STATE_CHG (5U) //!< Bit position for USB_OTGISTAT_LINE_STATE_CHG.
+#define BM_USB_OTGISTAT_LINE_STATE_CHG (0x20U) //!< Bit mask for USB_OTGISTAT_LINE_STATE_CHG.
+#define BS_USB_OTGISTAT_LINE_STATE_CHG (1U) //!< Bit field size in bits for USB_OTGISTAT_LINE_STATE_CHG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGISTAT_LINE_STATE_CHG field.
+#define BR_USB_OTGISTAT_LINE_STATE_CHG (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_LINE_STATE_CHG))
+#endif
+
+//! @brief Format value for bitfield USB_OTGISTAT_LINE_STATE_CHG.
+#define BF_USB_OTGISTAT_LINE_STATE_CHG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGISTAT_LINE_STATE_CHG), uint8_t) & BM_USB_OTGISTAT_LINE_STATE_CHG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LINE_STATE_CHG field to a new value.
+#define BW_USB_OTGISTAT_LINE_STATE_CHG(v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_LINE_STATE_CHG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGISTAT, field ONEMSEC[6] (RW)
+ *
+ * This bit is set when the 1 millisecond timer expires. This bit stays asserted
+ * until cleared by software. The interrupt must be serviced every millisecond
+ * to avoid losing 1msec counts.
+ */
+//@{
+#define BP_USB_OTGISTAT_ONEMSEC (6U) //!< Bit position for USB_OTGISTAT_ONEMSEC.
+#define BM_USB_OTGISTAT_ONEMSEC (0x40U) //!< Bit mask for USB_OTGISTAT_ONEMSEC.
+#define BS_USB_OTGISTAT_ONEMSEC (1U) //!< Bit field size in bits for USB_OTGISTAT_ONEMSEC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGISTAT_ONEMSEC field.
+#define BR_USB_OTGISTAT_ONEMSEC (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_ONEMSEC))
+#endif
+
+//! @brief Format value for bitfield USB_OTGISTAT_ONEMSEC.
+#define BF_USB_OTGISTAT_ONEMSEC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGISTAT_ONEMSEC), uint8_t) & BM_USB_OTGISTAT_ONEMSEC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ONEMSEC field to a new value.
+#define BW_USB_OTGISTAT_ONEMSEC(v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_ONEMSEC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGISTAT, field IDCHG[7] (RW)
+ *
+ * This bit is set when a change in the ID Signal from the USB connector is
+ * sensed.
+ */
+//@{
+#define BP_USB_OTGISTAT_IDCHG (7U) //!< Bit position for USB_OTGISTAT_IDCHG.
+#define BM_USB_OTGISTAT_IDCHG (0x80U) //!< Bit mask for USB_OTGISTAT_IDCHG.
+#define BS_USB_OTGISTAT_IDCHG (1U) //!< Bit field size in bits for USB_OTGISTAT_IDCHG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGISTAT_IDCHG field.
+#define BR_USB_OTGISTAT_IDCHG (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_IDCHG))
+#endif
+
+//! @brief Format value for bitfield USB_OTGISTAT_IDCHG.
+#define BF_USB_OTGISTAT_IDCHG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGISTAT_IDCHG), uint8_t) & BM_USB_OTGISTAT_IDCHG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IDCHG field to a new value.
+#define BW_USB_OTGISTAT_IDCHG(v) (BITBAND_ACCESS8(HW_USB_OTGISTAT_ADDR, BP_USB_OTGISTAT_IDCHG) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_OTGICR - OTG Interrupt Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_OTGICR - OTG Interrupt Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Enables the corresponding interrupt status bits defined in the OTG Interrupt
+ * Status Register.
+ */
+typedef union _hw_usb_otgicr
+{
+ uint8_t U;
+ struct _hw_usb_otgicr_bitfields
+ {
+ uint8_t AVBUSEN : 1; //!< [0] A VBUS Valid Interrupt Enable
+ uint8_t RESERVED0 : 1; //!< [1]
+ uint8_t BSESSEN : 1; //!< [2] B Session END Interrupt Enable
+ uint8_t SESSVLDEN : 1; //!< [3] Session Valid Interrupt Enable
+ uint8_t RESERVED1 : 1; //!< [4]
+ uint8_t LINESTATEEN : 1; //!< [5] Line State Change Interrupt Enable
+ uint8_t ONEMSECEN : 1; //!< [6] One Millisecond Interrupt Enable
+ uint8_t IDEN : 1; //!< [7] ID Interrupt Enable
+ } B;
+} hw_usb_otgicr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_OTGICR register
+ */
+//@{
+#define HW_USB_OTGICR_ADDR (REGS_USB_BASE + 0x14U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_OTGICR (*(__IO hw_usb_otgicr_t *) HW_USB_OTGICR_ADDR)
+#define HW_USB_OTGICR_RD() (HW_USB_OTGICR.U)
+#define HW_USB_OTGICR_WR(v) (HW_USB_OTGICR.U = (v))
+#define HW_USB_OTGICR_SET(v) (HW_USB_OTGICR_WR(HW_USB_OTGICR_RD() | (v)))
+#define HW_USB_OTGICR_CLR(v) (HW_USB_OTGICR_WR(HW_USB_OTGICR_RD() & ~(v)))
+#define HW_USB_OTGICR_TOG(v) (HW_USB_OTGICR_WR(HW_USB_OTGICR_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_OTGICR bitfields
+ */
+
+/*!
+ * @name Register USB_OTGICR, field AVBUSEN[0] (RW)
+ *
+ * Values:
+ * - 0 - Disables the AVBUSCHG interrupt.
+ * - 1 - Enables the AVBUSCHG interrupt.
+ */
+//@{
+#define BP_USB_OTGICR_AVBUSEN (0U) //!< Bit position for USB_OTGICR_AVBUSEN.
+#define BM_USB_OTGICR_AVBUSEN (0x01U) //!< Bit mask for USB_OTGICR_AVBUSEN.
+#define BS_USB_OTGICR_AVBUSEN (1U) //!< Bit field size in bits for USB_OTGICR_AVBUSEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGICR_AVBUSEN field.
+#define BR_USB_OTGICR_AVBUSEN (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_AVBUSEN))
+#endif
+
+//! @brief Format value for bitfield USB_OTGICR_AVBUSEN.
+#define BF_USB_OTGICR_AVBUSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGICR_AVBUSEN), uint8_t) & BM_USB_OTGICR_AVBUSEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AVBUSEN field to a new value.
+#define BW_USB_OTGICR_AVBUSEN(v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_AVBUSEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGICR, field BSESSEN[2] (RW)
+ *
+ * Values:
+ * - 0 - Disables the B_SESS_CHG interrupt.
+ * - 1 - Enables the B_SESS_CHG interrupt.
+ */
+//@{
+#define BP_USB_OTGICR_BSESSEN (2U) //!< Bit position for USB_OTGICR_BSESSEN.
+#define BM_USB_OTGICR_BSESSEN (0x04U) //!< Bit mask for USB_OTGICR_BSESSEN.
+#define BS_USB_OTGICR_BSESSEN (1U) //!< Bit field size in bits for USB_OTGICR_BSESSEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGICR_BSESSEN field.
+#define BR_USB_OTGICR_BSESSEN (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_BSESSEN))
+#endif
+
+//! @brief Format value for bitfield USB_OTGICR_BSESSEN.
+#define BF_USB_OTGICR_BSESSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGICR_BSESSEN), uint8_t) & BM_USB_OTGICR_BSESSEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BSESSEN field to a new value.
+#define BW_USB_OTGICR_BSESSEN(v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_BSESSEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGICR, field SESSVLDEN[3] (RW)
+ *
+ * Values:
+ * - 0 - Disables the SESSVLDCHG interrupt.
+ * - 1 - Enables the SESSVLDCHG interrupt.
+ */
+//@{
+#define BP_USB_OTGICR_SESSVLDEN (3U) //!< Bit position for USB_OTGICR_SESSVLDEN.
+#define BM_USB_OTGICR_SESSVLDEN (0x08U) //!< Bit mask for USB_OTGICR_SESSVLDEN.
+#define BS_USB_OTGICR_SESSVLDEN (1U) //!< Bit field size in bits for USB_OTGICR_SESSVLDEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGICR_SESSVLDEN field.
+#define BR_USB_OTGICR_SESSVLDEN (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_SESSVLDEN))
+#endif
+
+//! @brief Format value for bitfield USB_OTGICR_SESSVLDEN.
+#define BF_USB_OTGICR_SESSVLDEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGICR_SESSVLDEN), uint8_t) & BM_USB_OTGICR_SESSVLDEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SESSVLDEN field to a new value.
+#define BW_USB_OTGICR_SESSVLDEN(v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_SESSVLDEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGICR, field LINESTATEEN[5] (RW)
+ *
+ * Values:
+ * - 0 - Disables the LINE_STAT_CHG interrupt.
+ * - 1 - Enables the LINE_STAT_CHG interrupt.
+ */
+//@{
+#define BP_USB_OTGICR_LINESTATEEN (5U) //!< Bit position for USB_OTGICR_LINESTATEEN.
+#define BM_USB_OTGICR_LINESTATEEN (0x20U) //!< Bit mask for USB_OTGICR_LINESTATEEN.
+#define BS_USB_OTGICR_LINESTATEEN (1U) //!< Bit field size in bits for USB_OTGICR_LINESTATEEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGICR_LINESTATEEN field.
+#define BR_USB_OTGICR_LINESTATEEN (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_LINESTATEEN))
+#endif
+
+//! @brief Format value for bitfield USB_OTGICR_LINESTATEEN.
+#define BF_USB_OTGICR_LINESTATEEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGICR_LINESTATEEN), uint8_t) & BM_USB_OTGICR_LINESTATEEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LINESTATEEN field to a new value.
+#define BW_USB_OTGICR_LINESTATEEN(v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_LINESTATEEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGICR, field ONEMSECEN[6] (RW)
+ *
+ * Values:
+ * - 0 - Diables the 1ms timer interrupt.
+ * - 1 - Enables the 1ms timer interrupt.
+ */
+//@{
+#define BP_USB_OTGICR_ONEMSECEN (6U) //!< Bit position for USB_OTGICR_ONEMSECEN.
+#define BM_USB_OTGICR_ONEMSECEN (0x40U) //!< Bit mask for USB_OTGICR_ONEMSECEN.
+#define BS_USB_OTGICR_ONEMSECEN (1U) //!< Bit field size in bits for USB_OTGICR_ONEMSECEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGICR_ONEMSECEN field.
+#define BR_USB_OTGICR_ONEMSECEN (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_ONEMSECEN))
+#endif
+
+//! @brief Format value for bitfield USB_OTGICR_ONEMSECEN.
+#define BF_USB_OTGICR_ONEMSECEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGICR_ONEMSECEN), uint8_t) & BM_USB_OTGICR_ONEMSECEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ONEMSECEN field to a new value.
+#define BW_USB_OTGICR_ONEMSECEN(v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_ONEMSECEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGICR, field IDEN[7] (RW)
+ *
+ * Values:
+ * - 0 - The ID interrupt is disabled
+ * - 1 - The ID interrupt is enabled
+ */
+//@{
+#define BP_USB_OTGICR_IDEN (7U) //!< Bit position for USB_OTGICR_IDEN.
+#define BM_USB_OTGICR_IDEN (0x80U) //!< Bit mask for USB_OTGICR_IDEN.
+#define BS_USB_OTGICR_IDEN (1U) //!< Bit field size in bits for USB_OTGICR_IDEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGICR_IDEN field.
+#define BR_USB_OTGICR_IDEN (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_IDEN))
+#endif
+
+//! @brief Format value for bitfield USB_OTGICR_IDEN.
+#define BF_USB_OTGICR_IDEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGICR_IDEN), uint8_t) & BM_USB_OTGICR_IDEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IDEN field to a new value.
+#define BW_USB_OTGICR_IDEN(v) (BITBAND_ACCESS8(HW_USB_OTGICR_ADDR, BP_USB_OTGICR_IDEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_OTGSTAT - OTG Status register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_OTGSTAT - OTG Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Displays the actual value from the external comparator outputs of the ID pin
+ * and VBUS.
+ */
+typedef union _hw_usb_otgstat
+{
+ uint8_t U;
+ struct _hw_usb_otgstat_bitfields
+ {
+ uint8_t AVBUSVLD : 1; //!< [0] A VBUS Valid
+ uint8_t RESERVED0 : 1; //!< [1]
+ uint8_t BSESSEND : 1; //!< [2] B Session End
+ uint8_t SESS_VLD : 1; //!< [3] Session Valid
+ uint8_t RESERVED1 : 1; //!< [4]
+ uint8_t LINESTATESTABLE : 1; //!< [5]
+ uint8_t ONEMSECEN : 1; //!< [6]
+ uint8_t ID : 1; //!< [7]
+ } B;
+} hw_usb_otgstat_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_OTGSTAT register
+ */
+//@{
+#define HW_USB_OTGSTAT_ADDR (REGS_USB_BASE + 0x18U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_OTGSTAT (*(__IO hw_usb_otgstat_t *) HW_USB_OTGSTAT_ADDR)
+#define HW_USB_OTGSTAT_RD() (HW_USB_OTGSTAT.U)
+#define HW_USB_OTGSTAT_WR(v) (HW_USB_OTGSTAT.U = (v))
+#define HW_USB_OTGSTAT_SET(v) (HW_USB_OTGSTAT_WR(HW_USB_OTGSTAT_RD() | (v)))
+#define HW_USB_OTGSTAT_CLR(v) (HW_USB_OTGSTAT_WR(HW_USB_OTGSTAT_RD() & ~(v)))
+#define HW_USB_OTGSTAT_TOG(v) (HW_USB_OTGSTAT_WR(HW_USB_OTGSTAT_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_OTGSTAT bitfields
+ */
+
+/*!
+ * @name Register USB_OTGSTAT, field AVBUSVLD[0] (RW)
+ *
+ * Values:
+ * - 0 - The VBUS voltage is below the A VBUS Valid threshold.
+ * - 1 - The VBUS voltage is above the A VBUS Valid threshold.
+ */
+//@{
+#define BP_USB_OTGSTAT_AVBUSVLD (0U) //!< Bit position for USB_OTGSTAT_AVBUSVLD.
+#define BM_USB_OTGSTAT_AVBUSVLD (0x01U) //!< Bit mask for USB_OTGSTAT_AVBUSVLD.
+#define BS_USB_OTGSTAT_AVBUSVLD (1U) //!< Bit field size in bits for USB_OTGSTAT_AVBUSVLD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGSTAT_AVBUSVLD field.
+#define BR_USB_OTGSTAT_AVBUSVLD (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_AVBUSVLD))
+#endif
+
+//! @brief Format value for bitfield USB_OTGSTAT_AVBUSVLD.
+#define BF_USB_OTGSTAT_AVBUSVLD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGSTAT_AVBUSVLD), uint8_t) & BM_USB_OTGSTAT_AVBUSVLD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the AVBUSVLD field to a new value.
+#define BW_USB_OTGSTAT_AVBUSVLD(v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_AVBUSVLD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGSTAT, field BSESSEND[2] (RW)
+ *
+ * Values:
+ * - 0 - The VBUS voltage is above the B session end threshold.
+ * - 1 - The VBUS voltage is below the B session end threshold.
+ */
+//@{
+#define BP_USB_OTGSTAT_BSESSEND (2U) //!< Bit position for USB_OTGSTAT_BSESSEND.
+#define BM_USB_OTGSTAT_BSESSEND (0x04U) //!< Bit mask for USB_OTGSTAT_BSESSEND.
+#define BS_USB_OTGSTAT_BSESSEND (1U) //!< Bit field size in bits for USB_OTGSTAT_BSESSEND.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGSTAT_BSESSEND field.
+#define BR_USB_OTGSTAT_BSESSEND (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_BSESSEND))
+#endif
+
+//! @brief Format value for bitfield USB_OTGSTAT_BSESSEND.
+#define BF_USB_OTGSTAT_BSESSEND(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGSTAT_BSESSEND), uint8_t) & BM_USB_OTGSTAT_BSESSEND)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BSESSEND field to a new value.
+#define BW_USB_OTGSTAT_BSESSEND(v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_BSESSEND) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGSTAT, field SESS_VLD[3] (RW)
+ *
+ * Values:
+ * - 0 - The VBUS voltage is below the B session valid threshold
+ * - 1 - The VBUS voltage is above the B session valid threshold.
+ */
+//@{
+#define BP_USB_OTGSTAT_SESS_VLD (3U) //!< Bit position for USB_OTGSTAT_SESS_VLD.
+#define BM_USB_OTGSTAT_SESS_VLD (0x08U) //!< Bit mask for USB_OTGSTAT_SESS_VLD.
+#define BS_USB_OTGSTAT_SESS_VLD (1U) //!< Bit field size in bits for USB_OTGSTAT_SESS_VLD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGSTAT_SESS_VLD field.
+#define BR_USB_OTGSTAT_SESS_VLD (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_SESS_VLD))
+#endif
+
+//! @brief Format value for bitfield USB_OTGSTAT_SESS_VLD.
+#define BF_USB_OTGSTAT_SESS_VLD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGSTAT_SESS_VLD), uint8_t) & BM_USB_OTGSTAT_SESS_VLD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SESS_VLD field to a new value.
+#define BW_USB_OTGSTAT_SESS_VLD(v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_SESS_VLD) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGSTAT, field LINESTATESTABLE[5] (RW)
+ *
+ * Indicates that the internal signals that control the LINE_STATE_CHG field of
+ * OTGISTAT are stable for at least 1 millisecond. First read LINE_STATE_CHG
+ * field and then read this field. If this field reads as 1, then the value of
+ * LINE_STATE_CHG can be considered stable.
+ *
+ * Values:
+ * - 0 - The LINE_STAT_CHG bit is not yet stable.
+ * - 1 - The LINE_STAT_CHG bit has been debounced and is stable.
+ */
+//@{
+#define BP_USB_OTGSTAT_LINESTATESTABLE (5U) //!< Bit position for USB_OTGSTAT_LINESTATESTABLE.
+#define BM_USB_OTGSTAT_LINESTATESTABLE (0x20U) //!< Bit mask for USB_OTGSTAT_LINESTATESTABLE.
+#define BS_USB_OTGSTAT_LINESTATESTABLE (1U) //!< Bit field size in bits for USB_OTGSTAT_LINESTATESTABLE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGSTAT_LINESTATESTABLE field.
+#define BR_USB_OTGSTAT_LINESTATESTABLE (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_LINESTATESTABLE))
+#endif
+
+//! @brief Format value for bitfield USB_OTGSTAT_LINESTATESTABLE.
+#define BF_USB_OTGSTAT_LINESTATESTABLE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGSTAT_LINESTATESTABLE), uint8_t) & BM_USB_OTGSTAT_LINESTATESTABLE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LINESTATESTABLE field to a new value.
+#define BW_USB_OTGSTAT_LINESTATESTABLE(v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_LINESTATESTABLE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGSTAT, field ONEMSECEN[6] (RW)
+ *
+ * This bit is reserved for the 1ms count, but it is not useful to software.
+ */
+//@{
+#define BP_USB_OTGSTAT_ONEMSECEN (6U) //!< Bit position for USB_OTGSTAT_ONEMSECEN.
+#define BM_USB_OTGSTAT_ONEMSECEN (0x40U) //!< Bit mask for USB_OTGSTAT_ONEMSECEN.
+#define BS_USB_OTGSTAT_ONEMSECEN (1U) //!< Bit field size in bits for USB_OTGSTAT_ONEMSECEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGSTAT_ONEMSECEN field.
+#define BR_USB_OTGSTAT_ONEMSECEN (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_ONEMSECEN))
+#endif
+
+//! @brief Format value for bitfield USB_OTGSTAT_ONEMSECEN.
+#define BF_USB_OTGSTAT_ONEMSECEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGSTAT_ONEMSECEN), uint8_t) & BM_USB_OTGSTAT_ONEMSECEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ONEMSECEN field to a new value.
+#define BW_USB_OTGSTAT_ONEMSECEN(v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_ONEMSECEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGSTAT, field ID[7] (RW)
+ *
+ * Indicates the current state of the ID pin on the USB connector
+ *
+ * Values:
+ * - 0 - Indicates a Type A cable is plugged into the USB connector.
+ * - 1 - Indicates no cable is attached or a Type B cable is plugged into the
+ * USB connector.
+ */
+//@{
+#define BP_USB_OTGSTAT_ID (7U) //!< Bit position for USB_OTGSTAT_ID.
+#define BM_USB_OTGSTAT_ID (0x80U) //!< Bit mask for USB_OTGSTAT_ID.
+#define BS_USB_OTGSTAT_ID (1U) //!< Bit field size in bits for USB_OTGSTAT_ID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGSTAT_ID field.
+#define BR_USB_OTGSTAT_ID (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_ID))
+#endif
+
+//! @brief Format value for bitfield USB_OTGSTAT_ID.
+#define BF_USB_OTGSTAT_ID(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGSTAT_ID), uint8_t) & BM_USB_OTGSTAT_ID)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ID field to a new value.
+#define BW_USB_OTGSTAT_ID(v) (BITBAND_ACCESS8(HW_USB_OTGSTAT_ADDR, BP_USB_OTGSTAT_ID) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_OTGCTL - OTG Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_OTGCTL - OTG Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Controls the operation of VBUS and Data Line termination resistors.
+ */
+typedef union _hw_usb_otgctl
+{
+ uint8_t U;
+ struct _hw_usb_otgctl_bitfields
+ {
+ uint8_t RESERVED0 : 2; //!< [1:0]
+ uint8_t OTGEN : 1; //!< [2] On-The-Go pullup/pulldown resistor enable
+ uint8_t RESERVED1 : 1; //!< [3]
+ uint8_t DMLOW : 1; //!< [4] D- Data Line pull-down resistor enable
+ uint8_t DPLOW : 1; //!< [5] D+ Data Line pull-down resistor enable
+ uint8_t RESERVED2 : 1; //!< [6]
+ uint8_t DPHIGH : 1; //!< [7] D+ Data Line pullup resistor enable
+ } B;
+} hw_usb_otgctl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_OTGCTL register
+ */
+//@{
+#define HW_USB_OTGCTL_ADDR (REGS_USB_BASE + 0x1CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_OTGCTL (*(__IO hw_usb_otgctl_t *) HW_USB_OTGCTL_ADDR)
+#define HW_USB_OTGCTL_RD() (HW_USB_OTGCTL.U)
+#define HW_USB_OTGCTL_WR(v) (HW_USB_OTGCTL.U = (v))
+#define HW_USB_OTGCTL_SET(v) (HW_USB_OTGCTL_WR(HW_USB_OTGCTL_RD() | (v)))
+#define HW_USB_OTGCTL_CLR(v) (HW_USB_OTGCTL_WR(HW_USB_OTGCTL_RD() & ~(v)))
+#define HW_USB_OTGCTL_TOG(v) (HW_USB_OTGCTL_WR(HW_USB_OTGCTL_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_OTGCTL bitfields
+ */
+
+/*!
+ * @name Register USB_OTGCTL, field OTGEN[2] (RW)
+ *
+ * Values:
+ * - 0 - If USB_EN is 1 and HOST_MODE is 0 in the Control Register (CTL), then
+ * the D+ Data Line pull-up resistors are enabled. If HOST_MODE is 1 the D+
+ * and D- Data Line pull-down resistors are engaged.
+ * - 1 - The pull-up and pull-down controls in this register are used.
+ */
+//@{
+#define BP_USB_OTGCTL_OTGEN (2U) //!< Bit position for USB_OTGCTL_OTGEN.
+#define BM_USB_OTGCTL_OTGEN (0x04U) //!< Bit mask for USB_OTGCTL_OTGEN.
+#define BS_USB_OTGCTL_OTGEN (1U) //!< Bit field size in bits for USB_OTGCTL_OTGEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGCTL_OTGEN field.
+#define BR_USB_OTGCTL_OTGEN (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR, BP_USB_OTGCTL_OTGEN))
+#endif
+
+//! @brief Format value for bitfield USB_OTGCTL_OTGEN.
+#define BF_USB_OTGCTL_OTGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGCTL_OTGEN), uint8_t) & BM_USB_OTGCTL_OTGEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OTGEN field to a new value.
+#define BW_USB_OTGCTL_OTGEN(v) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR, BP_USB_OTGCTL_OTGEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGCTL, field DMLOW[4] (RW)
+ *
+ * Values:
+ * - 0 - D- pulldown resistor is not enabled.
+ * - 1 - D- pulldown resistor is enabled.
+ */
+//@{
+#define BP_USB_OTGCTL_DMLOW (4U) //!< Bit position for USB_OTGCTL_DMLOW.
+#define BM_USB_OTGCTL_DMLOW (0x10U) //!< Bit mask for USB_OTGCTL_DMLOW.
+#define BS_USB_OTGCTL_DMLOW (1U) //!< Bit field size in bits for USB_OTGCTL_DMLOW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGCTL_DMLOW field.
+#define BR_USB_OTGCTL_DMLOW (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR, BP_USB_OTGCTL_DMLOW))
+#endif
+
+//! @brief Format value for bitfield USB_OTGCTL_DMLOW.
+#define BF_USB_OTGCTL_DMLOW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGCTL_DMLOW), uint8_t) & BM_USB_OTGCTL_DMLOW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMLOW field to a new value.
+#define BW_USB_OTGCTL_DMLOW(v) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR, BP_USB_OTGCTL_DMLOW) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGCTL, field DPLOW[5] (RW)
+ *
+ * This bit should always be enabled together with bit 4 (DMLOW)
+ *
+ * Values:
+ * - 0 - D+ pulldown resistor is not enabled.
+ * - 1 - D+ pulldown resistor is enabled.
+ */
+//@{
+#define BP_USB_OTGCTL_DPLOW (5U) //!< Bit position for USB_OTGCTL_DPLOW.
+#define BM_USB_OTGCTL_DPLOW (0x20U) //!< Bit mask for USB_OTGCTL_DPLOW.
+#define BS_USB_OTGCTL_DPLOW (1U) //!< Bit field size in bits for USB_OTGCTL_DPLOW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGCTL_DPLOW field.
+#define BR_USB_OTGCTL_DPLOW (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR, BP_USB_OTGCTL_DPLOW))
+#endif
+
+//! @brief Format value for bitfield USB_OTGCTL_DPLOW.
+#define BF_USB_OTGCTL_DPLOW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGCTL_DPLOW), uint8_t) & BM_USB_OTGCTL_DPLOW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DPLOW field to a new value.
+#define BW_USB_OTGCTL_DPLOW(v) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR, BP_USB_OTGCTL_DPLOW) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OTGCTL, field DPHIGH[7] (RW)
+ *
+ * Values:
+ * - 0 - D+ pullup resistor is not enabled
+ * - 1 - D+ pullup resistor is enabled
+ */
+//@{
+#define BP_USB_OTGCTL_DPHIGH (7U) //!< Bit position for USB_OTGCTL_DPHIGH.
+#define BM_USB_OTGCTL_DPHIGH (0x80U) //!< Bit mask for USB_OTGCTL_DPHIGH.
+#define BS_USB_OTGCTL_DPHIGH (1U) //!< Bit field size in bits for USB_OTGCTL_DPHIGH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OTGCTL_DPHIGH field.
+#define BR_USB_OTGCTL_DPHIGH (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR, BP_USB_OTGCTL_DPHIGH))
+#endif
+
+//! @brief Format value for bitfield USB_OTGCTL_DPHIGH.
+#define BF_USB_OTGCTL_DPHIGH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_OTGCTL_DPHIGH), uint8_t) & BM_USB_OTGCTL_DPHIGH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DPHIGH field to a new value.
+#define BW_USB_OTGCTL_DPHIGH(v) (BITBAND_ACCESS8(HW_USB_OTGCTL_ADDR, BP_USB_OTGCTL_DPHIGH) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_ISTAT - Interrupt Status register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_ISTAT - Interrupt Status register (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains fields for each of the interrupt sources within the USB Module. Each
+ * of these fields are qualified with their respective interrupt enable bits.
+ * All fields of this register are logically OR'd together along with the OTG
+ * Interrupt Status Register (OTGSTAT) to form a single interrupt source for the
+ * processor's interrupt controller. After an interrupt bit has been set it may only
+ * be cleared by writing a one to the respective interrupt bit. This register
+ * contains the value of 0x00 after a reset.
+ */
+typedef union _hw_usb_istat
+{
+ uint8_t U;
+ struct _hw_usb_istat_bitfields
+ {
+ uint8_t USBRST : 1; //!< [0]
+ uint8_t ERROR : 1; //!< [1]
+ uint8_t SOFTOK : 1; //!< [2]
+ uint8_t TOKDNE : 1; //!< [3]
+ uint8_t SLEEP : 1; //!< [4]
+ uint8_t RESUME : 1; //!< [5]
+ uint8_t ATTACH : 1; //!< [6] Attach Interrupt
+ uint8_t STALL : 1; //!< [7] Stall Interrupt
+ } B;
+} hw_usb_istat_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_ISTAT register
+ */
+//@{
+#define HW_USB_ISTAT_ADDR (REGS_USB_BASE + 0x80U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_ISTAT (*(__IO hw_usb_istat_t *) HW_USB_ISTAT_ADDR)
+#define HW_USB_ISTAT_RD() (HW_USB_ISTAT.U)
+#define HW_USB_ISTAT_WR(v) (HW_USB_ISTAT.U = (v))
+#define HW_USB_ISTAT_SET(v) (HW_USB_ISTAT_WR(HW_USB_ISTAT_RD() | (v)))
+#define HW_USB_ISTAT_CLR(v) (HW_USB_ISTAT_WR(HW_USB_ISTAT_RD() & ~(v)))
+#define HW_USB_ISTAT_TOG(v) (HW_USB_ISTAT_WR(HW_USB_ISTAT_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_ISTAT bitfields
+ */
+
+/*!
+ * @name Register USB_ISTAT, field USBRST[0] (W1C)
+ *
+ * This bit is set when the USB Module has decoded a valid USB reset. This
+ * informs the processor that it should write 0x00 into the address register and
+ * enable endpoint 0. USBRST is set after a USB reset has been detected for 2.5
+ * microseconds. It is not asserted again until the USB reset condition has been
+ * removed and then reasserted.
+ */
+//@{
+#define BP_USB_ISTAT_USBRST (0U) //!< Bit position for USB_ISTAT_USBRST.
+#define BM_USB_ISTAT_USBRST (0x01U) //!< Bit mask for USB_ISTAT_USBRST.
+#define BS_USB_ISTAT_USBRST (1U) //!< Bit field size in bits for USB_ISTAT_USBRST.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ISTAT_USBRST field.
+#define BR_USB_ISTAT_USBRST (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_USBRST))
+#endif
+
+//! @brief Format value for bitfield USB_ISTAT_USBRST.
+#define BF_USB_ISTAT_USBRST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ISTAT_USBRST), uint8_t) & BM_USB_ISTAT_USBRST)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the USBRST field to a new value.
+#define BW_USB_ISTAT_USBRST(v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_USBRST) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ISTAT, field ERROR[1] (W1C)
+ *
+ * This bit is set when any of the error conditions within Error Interrupt
+ * Status (ERRSTAT) register occur. The processor must then read the ERRSTAT register
+ * to determine the source of the error.
+ */
+//@{
+#define BP_USB_ISTAT_ERROR (1U) //!< Bit position for USB_ISTAT_ERROR.
+#define BM_USB_ISTAT_ERROR (0x02U) //!< Bit mask for USB_ISTAT_ERROR.
+#define BS_USB_ISTAT_ERROR (1U) //!< Bit field size in bits for USB_ISTAT_ERROR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ISTAT_ERROR field.
+#define BR_USB_ISTAT_ERROR (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_ERROR))
+#endif
+
+//! @brief Format value for bitfield USB_ISTAT_ERROR.
+#define BF_USB_ISTAT_ERROR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ISTAT_ERROR), uint8_t) & BM_USB_ISTAT_ERROR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERROR field to a new value.
+#define BW_USB_ISTAT_ERROR(v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_ERROR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ISTAT, field SOFTOK[2] (W1C)
+ *
+ * This bit is set when the USB Module receives a Start Of Frame (SOF) token. In
+ * Host mode this field is set when the SOF threshold is reached, so that
+ * software can prepare for the next SOF.
+ */
+//@{
+#define BP_USB_ISTAT_SOFTOK (2U) //!< Bit position for USB_ISTAT_SOFTOK.
+#define BM_USB_ISTAT_SOFTOK (0x04U) //!< Bit mask for USB_ISTAT_SOFTOK.
+#define BS_USB_ISTAT_SOFTOK (1U) //!< Bit field size in bits for USB_ISTAT_SOFTOK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ISTAT_SOFTOK field.
+#define BR_USB_ISTAT_SOFTOK (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_SOFTOK))
+#endif
+
+//! @brief Format value for bitfield USB_ISTAT_SOFTOK.
+#define BF_USB_ISTAT_SOFTOK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ISTAT_SOFTOK), uint8_t) & BM_USB_ISTAT_SOFTOK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SOFTOK field to a new value.
+#define BW_USB_ISTAT_SOFTOK(v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_SOFTOK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ISTAT, field TOKDNE[3] (W1C)
+ *
+ * This bit is set when the current token being processed has completed. The
+ * processor must immediately read the STATUS (STAT) register to determine the
+ * EndPoint and BD used for this token. Clearing this bit (by writing a one) causes
+ * STAT to be cleared or the STAT holding register to be loaded into the STAT
+ * register.
+ */
+//@{
+#define BP_USB_ISTAT_TOKDNE (3U) //!< Bit position for USB_ISTAT_TOKDNE.
+#define BM_USB_ISTAT_TOKDNE (0x08U) //!< Bit mask for USB_ISTAT_TOKDNE.
+#define BS_USB_ISTAT_TOKDNE (1U) //!< Bit field size in bits for USB_ISTAT_TOKDNE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ISTAT_TOKDNE field.
+#define BR_USB_ISTAT_TOKDNE (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_TOKDNE))
+#endif
+
+//! @brief Format value for bitfield USB_ISTAT_TOKDNE.
+#define BF_USB_ISTAT_TOKDNE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ISTAT_TOKDNE), uint8_t) & BM_USB_ISTAT_TOKDNE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TOKDNE field to a new value.
+#define BW_USB_ISTAT_TOKDNE(v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_TOKDNE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ISTAT, field SLEEP[4] (W1C)
+ *
+ * This bit is set when the USB Module detects a constant idle on the USB bus
+ * for 3 ms. The sleep timer is reset by activity on the USB bus.
+ */
+//@{
+#define BP_USB_ISTAT_SLEEP (4U) //!< Bit position for USB_ISTAT_SLEEP.
+#define BM_USB_ISTAT_SLEEP (0x10U) //!< Bit mask for USB_ISTAT_SLEEP.
+#define BS_USB_ISTAT_SLEEP (1U) //!< Bit field size in bits for USB_ISTAT_SLEEP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ISTAT_SLEEP field.
+#define BR_USB_ISTAT_SLEEP (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_SLEEP))
+#endif
+
+//! @brief Format value for bitfield USB_ISTAT_SLEEP.
+#define BF_USB_ISTAT_SLEEP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ISTAT_SLEEP), uint8_t) & BM_USB_ISTAT_SLEEP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SLEEP field to a new value.
+#define BW_USB_ISTAT_SLEEP(v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_SLEEP) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ISTAT, field RESUME[5] (W1C)
+ *
+ * This bit is set when a K-state is observed on the DP/DM signals for 2.5 us.
+ * When not in suspend mode this interrupt must be disabled.
+ */
+//@{
+#define BP_USB_ISTAT_RESUME (5U) //!< Bit position for USB_ISTAT_RESUME.
+#define BM_USB_ISTAT_RESUME (0x20U) //!< Bit mask for USB_ISTAT_RESUME.
+#define BS_USB_ISTAT_RESUME (1U) //!< Bit field size in bits for USB_ISTAT_RESUME.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ISTAT_RESUME field.
+#define BR_USB_ISTAT_RESUME (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_RESUME))
+#endif
+
+//! @brief Format value for bitfield USB_ISTAT_RESUME.
+#define BF_USB_ISTAT_RESUME(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ISTAT_RESUME), uint8_t) & BM_USB_ISTAT_RESUME)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RESUME field to a new value.
+#define BW_USB_ISTAT_RESUME(v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_RESUME) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ISTAT, field ATTACH[6] (W1C)
+ *
+ * This bit is set when the USB Module detects an attach of a USB device. This
+ * signal is only valid if HOSTMODEEN is true. This interrupt signifies that a
+ * peripheral is now present and must be configured; it is asserted if there have
+ * been no transitions on the USB for 2.5 us and the current bus state is not SE0."
+ */
+//@{
+#define BP_USB_ISTAT_ATTACH (6U) //!< Bit position for USB_ISTAT_ATTACH.
+#define BM_USB_ISTAT_ATTACH (0x40U) //!< Bit mask for USB_ISTAT_ATTACH.
+#define BS_USB_ISTAT_ATTACH (1U) //!< Bit field size in bits for USB_ISTAT_ATTACH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ISTAT_ATTACH field.
+#define BR_USB_ISTAT_ATTACH (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_ATTACH))
+#endif
+
+//! @brief Format value for bitfield USB_ISTAT_ATTACH.
+#define BF_USB_ISTAT_ATTACH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ISTAT_ATTACH), uint8_t) & BM_USB_ISTAT_ATTACH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ATTACH field to a new value.
+#define BW_USB_ISTAT_ATTACH(v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_ATTACH) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ISTAT, field STALL[7] (W1C)
+ *
+ * In Target mode this bit is asserted when a STALL handshake is sent by the
+ * SIE. In Host mode this bit is set when the USB Module detects a STALL acknowledge
+ * during the handshake phase of a USB transaction.This interrupt can be used to
+ * determine whether the last USB transaction was completed successfully or
+ * stalled.
+ */
+//@{
+#define BP_USB_ISTAT_STALL (7U) //!< Bit position for USB_ISTAT_STALL.
+#define BM_USB_ISTAT_STALL (0x80U) //!< Bit mask for USB_ISTAT_STALL.
+#define BS_USB_ISTAT_STALL (1U) //!< Bit field size in bits for USB_ISTAT_STALL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ISTAT_STALL field.
+#define BR_USB_ISTAT_STALL (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_STALL))
+#endif
+
+//! @brief Format value for bitfield USB_ISTAT_STALL.
+#define BF_USB_ISTAT_STALL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ISTAT_STALL), uint8_t) & BM_USB_ISTAT_STALL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the STALL field to a new value.
+#define BW_USB_ISTAT_STALL(v) (BITBAND_ACCESS8(HW_USB_ISTAT_ADDR, BP_USB_ISTAT_STALL) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_INTEN - Interrupt Enable register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_INTEN - Interrupt Enable register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains enable fields for each of the interrupt sources within the USB
+ * Module. Setting any of these bits enables the respective interrupt source in the
+ * ISTAT register. This register contains the value of 0x00 after a reset.
+ */
+typedef union _hw_usb_inten
+{
+ uint8_t U;
+ struct _hw_usb_inten_bitfields
+ {
+ uint8_t USBRSTEN : 1; //!< [0] USBRST Interrupt Enable
+ uint8_t ERROREN : 1; //!< [1] ERROR Interrupt Enable
+ uint8_t SOFTOKEN : 1; //!< [2] SOFTOK Interrupt Enable
+ uint8_t TOKDNEEN : 1; //!< [3] TOKDNE Interrupt Enable
+ uint8_t SLEEPEN : 1; //!< [4] SLEEP Interrupt Enable
+ uint8_t RESUMEEN : 1; //!< [5] RESUME Interrupt Enable
+ uint8_t ATTACHEN : 1; //!< [6] ATTACH Interrupt Enable
+ uint8_t STALLEN : 1; //!< [7] STALL Interrupt Enable
+ } B;
+} hw_usb_inten_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_INTEN register
+ */
+//@{
+#define HW_USB_INTEN_ADDR (REGS_USB_BASE + 0x84U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_INTEN (*(__IO hw_usb_inten_t *) HW_USB_INTEN_ADDR)
+#define HW_USB_INTEN_RD() (HW_USB_INTEN.U)
+#define HW_USB_INTEN_WR(v) (HW_USB_INTEN.U = (v))
+#define HW_USB_INTEN_SET(v) (HW_USB_INTEN_WR(HW_USB_INTEN_RD() | (v)))
+#define HW_USB_INTEN_CLR(v) (HW_USB_INTEN_WR(HW_USB_INTEN_RD() & ~(v)))
+#define HW_USB_INTEN_TOG(v) (HW_USB_INTEN_WR(HW_USB_INTEN_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_INTEN bitfields
+ */
+
+/*!
+ * @name Register USB_INTEN, field USBRSTEN[0] (RW)
+ *
+ * Values:
+ * - 0 - Disables the USBRST interrupt.
+ * - 1 - Enables the USBRST interrupt.
+ */
+//@{
+#define BP_USB_INTEN_USBRSTEN (0U) //!< Bit position for USB_INTEN_USBRSTEN.
+#define BM_USB_INTEN_USBRSTEN (0x01U) //!< Bit mask for USB_INTEN_USBRSTEN.
+#define BS_USB_INTEN_USBRSTEN (1U) //!< Bit field size in bits for USB_INTEN_USBRSTEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_INTEN_USBRSTEN field.
+#define BR_USB_INTEN_USBRSTEN (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_USBRSTEN))
+#endif
+
+//! @brief Format value for bitfield USB_INTEN_USBRSTEN.
+#define BF_USB_INTEN_USBRSTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_INTEN_USBRSTEN), uint8_t) & BM_USB_INTEN_USBRSTEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the USBRSTEN field to a new value.
+#define BW_USB_INTEN_USBRSTEN(v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_USBRSTEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_INTEN, field ERROREN[1] (RW)
+ *
+ * Values:
+ * - 0 - Disables the ERROR interrupt.
+ * - 1 - Enables the ERROR interrupt.
+ */
+//@{
+#define BP_USB_INTEN_ERROREN (1U) //!< Bit position for USB_INTEN_ERROREN.
+#define BM_USB_INTEN_ERROREN (0x02U) //!< Bit mask for USB_INTEN_ERROREN.
+#define BS_USB_INTEN_ERROREN (1U) //!< Bit field size in bits for USB_INTEN_ERROREN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_INTEN_ERROREN field.
+#define BR_USB_INTEN_ERROREN (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_ERROREN))
+#endif
+
+//! @brief Format value for bitfield USB_INTEN_ERROREN.
+#define BF_USB_INTEN_ERROREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_INTEN_ERROREN), uint8_t) & BM_USB_INTEN_ERROREN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ERROREN field to a new value.
+#define BW_USB_INTEN_ERROREN(v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_ERROREN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_INTEN, field SOFTOKEN[2] (RW)
+ *
+ * Values:
+ * - 0 - Disbles the SOFTOK interrupt.
+ * - 1 - Enables the SOFTOK interrupt.
+ */
+//@{
+#define BP_USB_INTEN_SOFTOKEN (2U) //!< Bit position for USB_INTEN_SOFTOKEN.
+#define BM_USB_INTEN_SOFTOKEN (0x04U) //!< Bit mask for USB_INTEN_SOFTOKEN.
+#define BS_USB_INTEN_SOFTOKEN (1U) //!< Bit field size in bits for USB_INTEN_SOFTOKEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_INTEN_SOFTOKEN field.
+#define BR_USB_INTEN_SOFTOKEN (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_SOFTOKEN))
+#endif
+
+//! @brief Format value for bitfield USB_INTEN_SOFTOKEN.
+#define BF_USB_INTEN_SOFTOKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_INTEN_SOFTOKEN), uint8_t) & BM_USB_INTEN_SOFTOKEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SOFTOKEN field to a new value.
+#define BW_USB_INTEN_SOFTOKEN(v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_SOFTOKEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_INTEN, field TOKDNEEN[3] (RW)
+ *
+ * Values:
+ * - 0 - Disables the TOKDNE interrupt.
+ * - 1 - Enables the TOKDNE interrupt.
+ */
+//@{
+#define BP_USB_INTEN_TOKDNEEN (3U) //!< Bit position for USB_INTEN_TOKDNEEN.
+#define BM_USB_INTEN_TOKDNEEN (0x08U) //!< Bit mask for USB_INTEN_TOKDNEEN.
+#define BS_USB_INTEN_TOKDNEEN (1U) //!< Bit field size in bits for USB_INTEN_TOKDNEEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_INTEN_TOKDNEEN field.
+#define BR_USB_INTEN_TOKDNEEN (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_TOKDNEEN))
+#endif
+
+//! @brief Format value for bitfield USB_INTEN_TOKDNEEN.
+#define BF_USB_INTEN_TOKDNEEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_INTEN_TOKDNEEN), uint8_t) & BM_USB_INTEN_TOKDNEEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TOKDNEEN field to a new value.
+#define BW_USB_INTEN_TOKDNEEN(v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_TOKDNEEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_INTEN, field SLEEPEN[4] (RW)
+ *
+ * Values:
+ * - 0 - Disables the SLEEP interrupt.
+ * - 1 - Enables the SLEEP interrupt.
+ */
+//@{
+#define BP_USB_INTEN_SLEEPEN (4U) //!< Bit position for USB_INTEN_SLEEPEN.
+#define BM_USB_INTEN_SLEEPEN (0x10U) //!< Bit mask for USB_INTEN_SLEEPEN.
+#define BS_USB_INTEN_SLEEPEN (1U) //!< Bit field size in bits for USB_INTEN_SLEEPEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_INTEN_SLEEPEN field.
+#define BR_USB_INTEN_SLEEPEN (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_SLEEPEN))
+#endif
+
+//! @brief Format value for bitfield USB_INTEN_SLEEPEN.
+#define BF_USB_INTEN_SLEEPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_INTEN_SLEEPEN), uint8_t) & BM_USB_INTEN_SLEEPEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SLEEPEN field to a new value.
+#define BW_USB_INTEN_SLEEPEN(v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_SLEEPEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_INTEN, field RESUMEEN[5] (RW)
+ *
+ * Values:
+ * - 0 - Disables the RESUME interrupt.
+ * - 1 - Enables the RESUME interrupt.
+ */
+//@{
+#define BP_USB_INTEN_RESUMEEN (5U) //!< Bit position for USB_INTEN_RESUMEEN.
+#define BM_USB_INTEN_RESUMEEN (0x20U) //!< Bit mask for USB_INTEN_RESUMEEN.
+#define BS_USB_INTEN_RESUMEEN (1U) //!< Bit field size in bits for USB_INTEN_RESUMEEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_INTEN_RESUMEEN field.
+#define BR_USB_INTEN_RESUMEEN (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_RESUMEEN))
+#endif
+
+//! @brief Format value for bitfield USB_INTEN_RESUMEEN.
+#define BF_USB_INTEN_RESUMEEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_INTEN_RESUMEEN), uint8_t) & BM_USB_INTEN_RESUMEEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RESUMEEN field to a new value.
+#define BW_USB_INTEN_RESUMEEN(v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_RESUMEEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_INTEN, field ATTACHEN[6] (RW)
+ *
+ * Values:
+ * - 0 - Disables the ATTACH interrupt.
+ * - 1 - Enables the ATTACH interrupt.
+ */
+//@{
+#define BP_USB_INTEN_ATTACHEN (6U) //!< Bit position for USB_INTEN_ATTACHEN.
+#define BM_USB_INTEN_ATTACHEN (0x40U) //!< Bit mask for USB_INTEN_ATTACHEN.
+#define BS_USB_INTEN_ATTACHEN (1U) //!< Bit field size in bits for USB_INTEN_ATTACHEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_INTEN_ATTACHEN field.
+#define BR_USB_INTEN_ATTACHEN (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_ATTACHEN))
+#endif
+
+//! @brief Format value for bitfield USB_INTEN_ATTACHEN.
+#define BF_USB_INTEN_ATTACHEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_INTEN_ATTACHEN), uint8_t) & BM_USB_INTEN_ATTACHEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ATTACHEN field to a new value.
+#define BW_USB_INTEN_ATTACHEN(v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_ATTACHEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_INTEN, field STALLEN[7] (RW)
+ *
+ * Values:
+ * - 0 - Diasbles the STALL interrupt.
+ * - 1 - Enables the STALL interrupt.
+ */
+//@{
+#define BP_USB_INTEN_STALLEN (7U) //!< Bit position for USB_INTEN_STALLEN.
+#define BM_USB_INTEN_STALLEN (0x80U) //!< Bit mask for USB_INTEN_STALLEN.
+#define BS_USB_INTEN_STALLEN (1U) //!< Bit field size in bits for USB_INTEN_STALLEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_INTEN_STALLEN field.
+#define BR_USB_INTEN_STALLEN (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_STALLEN))
+#endif
+
+//! @brief Format value for bitfield USB_INTEN_STALLEN.
+#define BF_USB_INTEN_STALLEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_INTEN_STALLEN), uint8_t) & BM_USB_INTEN_STALLEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the STALLEN field to a new value.
+#define BW_USB_INTEN_STALLEN(v) (BITBAND_ACCESS8(HW_USB_INTEN_ADDR, BP_USB_INTEN_STALLEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_ERRSTAT - Error Interrupt Status register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_ERRSTAT - Error Interrupt Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains enable bits for each of the error sources within the USB Module.
+ * Each of these bits are qualified with their respective error enable bits. All
+ * bits of this register are logically OR'd together and the result placed in the
+ * ERROR bit of the ISTAT register. After an interrupt bit has been set it may only
+ * be cleared by writing a one to the respective interrupt bit. Each bit is set
+ * as soon as the error condition is detected. Therefore, the interrupt does not
+ * typically correspond with the end of a token being processed. This register
+ * contains the value of 0x00 after a reset.
+ */
+typedef union _hw_usb_errstat
+{
+ uint8_t U;
+ struct _hw_usb_errstat_bitfields
+ {
+ uint8_t PIDERR : 1; //!< [0]
+ uint8_t CRC5EOF : 1; //!< [1]
+ uint8_t CRC16 : 1; //!< [2]
+ uint8_t DFN8 : 1; //!< [3]
+ uint8_t BTOERR : 1; //!< [4]
+ uint8_t DMAERR : 1; //!< [5]
+ uint8_t RESERVED0 : 1; //!< [6]
+ uint8_t BTSERR : 1; //!< [7]
+ } B;
+} hw_usb_errstat_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_ERRSTAT register
+ */
+//@{
+#define HW_USB_ERRSTAT_ADDR (REGS_USB_BASE + 0x88U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_ERRSTAT (*(__IO hw_usb_errstat_t *) HW_USB_ERRSTAT_ADDR)
+#define HW_USB_ERRSTAT_RD() (HW_USB_ERRSTAT.U)
+#define HW_USB_ERRSTAT_WR(v) (HW_USB_ERRSTAT.U = (v))
+#define HW_USB_ERRSTAT_SET(v) (HW_USB_ERRSTAT_WR(HW_USB_ERRSTAT_RD() | (v)))
+#define HW_USB_ERRSTAT_CLR(v) (HW_USB_ERRSTAT_WR(HW_USB_ERRSTAT_RD() & ~(v)))
+#define HW_USB_ERRSTAT_TOG(v) (HW_USB_ERRSTAT_WR(HW_USB_ERRSTAT_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_ERRSTAT bitfields
+ */
+
+/*!
+ * @name Register USB_ERRSTAT, field PIDERR[0] (W1C)
+ *
+ * This bit is set when the PID check field fails.
+ */
+//@{
+#define BP_USB_ERRSTAT_PIDERR (0U) //!< Bit position for USB_ERRSTAT_PIDERR.
+#define BM_USB_ERRSTAT_PIDERR (0x01U) //!< Bit mask for USB_ERRSTAT_PIDERR.
+#define BS_USB_ERRSTAT_PIDERR (1U) //!< Bit field size in bits for USB_ERRSTAT_PIDERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ERRSTAT_PIDERR field.
+#define BR_USB_ERRSTAT_PIDERR (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_PIDERR))
+#endif
+
+//! @brief Format value for bitfield USB_ERRSTAT_PIDERR.
+#define BF_USB_ERRSTAT_PIDERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERRSTAT_PIDERR), uint8_t) & BM_USB_ERRSTAT_PIDERR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PIDERR field to a new value.
+#define BW_USB_ERRSTAT_PIDERR(v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_PIDERR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ERRSTAT, field CRC5EOF[1] (W1C)
+ *
+ * This error interrupt has two functions. When the USB Module is operating in
+ * peripheral mode (HOSTMODEEN=0), this interrupt detects CRC5 errors in the token
+ * packets generated by the host. If set the token packet was rejected due to a
+ * CRC5 error. When the USB Module is operating in host mode (HOSTMODEEN=1), this
+ * interrupt detects End Of Frame (EOF) error conditions. This occurs when the
+ * USB Module is transmitting or receiving data and the SOF counter reaches zero.
+ * This interrupt is useful when developing USB packet scheduling software to
+ * ensure that no USB transactions cross the start of the next frame.
+ */
+//@{
+#define BP_USB_ERRSTAT_CRC5EOF (1U) //!< Bit position for USB_ERRSTAT_CRC5EOF.
+#define BM_USB_ERRSTAT_CRC5EOF (0x02U) //!< Bit mask for USB_ERRSTAT_CRC5EOF.
+#define BS_USB_ERRSTAT_CRC5EOF (1U) //!< Bit field size in bits for USB_ERRSTAT_CRC5EOF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ERRSTAT_CRC5EOF field.
+#define BR_USB_ERRSTAT_CRC5EOF (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_CRC5EOF))
+#endif
+
+//! @brief Format value for bitfield USB_ERRSTAT_CRC5EOF.
+#define BF_USB_ERRSTAT_CRC5EOF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERRSTAT_CRC5EOF), uint8_t) & BM_USB_ERRSTAT_CRC5EOF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CRC5EOF field to a new value.
+#define BW_USB_ERRSTAT_CRC5EOF(v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_CRC5EOF) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ERRSTAT, field CRC16[2] (W1C)
+ *
+ * This bit is set when a data packet is rejected due to a CRC16 error.
+ */
+//@{
+#define BP_USB_ERRSTAT_CRC16 (2U) //!< Bit position for USB_ERRSTAT_CRC16.
+#define BM_USB_ERRSTAT_CRC16 (0x04U) //!< Bit mask for USB_ERRSTAT_CRC16.
+#define BS_USB_ERRSTAT_CRC16 (1U) //!< Bit field size in bits for USB_ERRSTAT_CRC16.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ERRSTAT_CRC16 field.
+#define BR_USB_ERRSTAT_CRC16 (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_CRC16))
+#endif
+
+//! @brief Format value for bitfield USB_ERRSTAT_CRC16.
+#define BF_USB_ERRSTAT_CRC16(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERRSTAT_CRC16), uint8_t) & BM_USB_ERRSTAT_CRC16)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CRC16 field to a new value.
+#define BW_USB_ERRSTAT_CRC16(v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_CRC16) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ERRSTAT, field DFN8[3] (W1C)
+ *
+ * This bit is set if the data field received was not 8 bits in length. USB
+ * Specification 1.0 requires that data fields be an integral number of bytes. If the
+ * data field was not an integral number of bytes, this bit is set.
+ */
+//@{
+#define BP_USB_ERRSTAT_DFN8 (3U) //!< Bit position for USB_ERRSTAT_DFN8.
+#define BM_USB_ERRSTAT_DFN8 (0x08U) //!< Bit mask for USB_ERRSTAT_DFN8.
+#define BS_USB_ERRSTAT_DFN8 (1U) //!< Bit field size in bits for USB_ERRSTAT_DFN8.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ERRSTAT_DFN8 field.
+#define BR_USB_ERRSTAT_DFN8 (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_DFN8))
+#endif
+
+//! @brief Format value for bitfield USB_ERRSTAT_DFN8.
+#define BF_USB_ERRSTAT_DFN8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERRSTAT_DFN8), uint8_t) & BM_USB_ERRSTAT_DFN8)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DFN8 field to a new value.
+#define BW_USB_ERRSTAT_DFN8(v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_DFN8) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ERRSTAT, field BTOERR[4] (W1C)
+ *
+ * This bit is set when a bus turnaround timeout error occurs. The USB module
+ * contains a bus turnaround timer that keeps track of the amount of time elapsed
+ * between the token and data phases of a SETUP or OUT TOKEN or the data and
+ * handshake phases of a IN TOKEN. If more than 16 bit times are counted from the
+ * previous EOP before a transition from IDLE, a bus turnaround timeout error occurs.
+ */
+//@{
+#define BP_USB_ERRSTAT_BTOERR (4U) //!< Bit position for USB_ERRSTAT_BTOERR.
+#define BM_USB_ERRSTAT_BTOERR (0x10U) //!< Bit mask for USB_ERRSTAT_BTOERR.
+#define BS_USB_ERRSTAT_BTOERR (1U) //!< Bit field size in bits for USB_ERRSTAT_BTOERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ERRSTAT_BTOERR field.
+#define BR_USB_ERRSTAT_BTOERR (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_BTOERR))
+#endif
+
+//! @brief Format value for bitfield USB_ERRSTAT_BTOERR.
+#define BF_USB_ERRSTAT_BTOERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERRSTAT_BTOERR), uint8_t) & BM_USB_ERRSTAT_BTOERR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BTOERR field to a new value.
+#define BW_USB_ERRSTAT_BTOERR(v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_BTOERR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ERRSTAT, field DMAERR[5] (W1C)
+ *
+ * This bit is set if the USB Module has requested a DMA access to read a new
+ * BDT but has not been given the bus before it needs to receive or transmit data.
+ * If processing a TX transfer this would cause a transmit data underflow
+ * condition. If processing a RX transfer this would cause a receive data overflow
+ * condition. This interrupt is useful when developing device arbitration hardware for
+ * the microprocessor and the USB module to minimize bus request and bus grant
+ * latency. This bit is also set if a data packet to or from the host is larger
+ * than the buffer size allocated in the BDT. In this case the data packet is
+ * truncated as it is put in buffer memory.
+ */
+//@{
+#define BP_USB_ERRSTAT_DMAERR (5U) //!< Bit position for USB_ERRSTAT_DMAERR.
+#define BM_USB_ERRSTAT_DMAERR (0x20U) //!< Bit mask for USB_ERRSTAT_DMAERR.
+#define BS_USB_ERRSTAT_DMAERR (1U) //!< Bit field size in bits for USB_ERRSTAT_DMAERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ERRSTAT_DMAERR field.
+#define BR_USB_ERRSTAT_DMAERR (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_DMAERR))
+#endif
+
+//! @brief Format value for bitfield USB_ERRSTAT_DMAERR.
+#define BF_USB_ERRSTAT_DMAERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERRSTAT_DMAERR), uint8_t) & BM_USB_ERRSTAT_DMAERR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMAERR field to a new value.
+#define BW_USB_ERRSTAT_DMAERR(v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_DMAERR) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ERRSTAT, field BTSERR[7] (W1C)
+ *
+ * This bit is set when a bit stuff error is detected. If set, the corresponding
+ * packet is rejected due to the error.
+ */
+//@{
+#define BP_USB_ERRSTAT_BTSERR (7U) //!< Bit position for USB_ERRSTAT_BTSERR.
+#define BM_USB_ERRSTAT_BTSERR (0x80U) //!< Bit mask for USB_ERRSTAT_BTSERR.
+#define BS_USB_ERRSTAT_BTSERR (1U) //!< Bit field size in bits for USB_ERRSTAT_BTSERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ERRSTAT_BTSERR field.
+#define BR_USB_ERRSTAT_BTSERR (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_BTSERR))
+#endif
+
+//! @brief Format value for bitfield USB_ERRSTAT_BTSERR.
+#define BF_USB_ERRSTAT_BTSERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERRSTAT_BTSERR), uint8_t) & BM_USB_ERRSTAT_BTSERR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BTSERR field to a new value.
+#define BW_USB_ERRSTAT_BTSERR(v) (BITBAND_ACCESS8(HW_USB_ERRSTAT_ADDR, BP_USB_ERRSTAT_BTSERR) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_ERREN - Error Interrupt Enable register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_ERREN - Error Interrupt Enable register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains enable bits for each of the error interrupt sources within the USB
+ * module. Setting any of these bits enables the respective interrupt source in
+ * ERRSTAT. Each bit is set as soon as the error condition is detected. Therefore,
+ * the interrupt does not typically correspond with the end of a token being
+ * processed. This register contains the value of 0x00 after a reset.
+ */
+typedef union _hw_usb_erren
+{
+ uint8_t U;
+ struct _hw_usb_erren_bitfields
+ {
+ uint8_t PIDERREN : 1; //!< [0] PIDERR Interrupt Enable
+ uint8_t CRC5EOFEN : 1; //!< [1] CRC5/EOF Interrupt Enable
+ uint8_t CRC16EN : 1; //!< [2] CRC16 Interrupt Enable
+ uint8_t DFN8EN : 1; //!< [3] DFN8 Interrupt Enable
+ uint8_t BTOERREN : 1; //!< [4] BTOERR Interrupt Enable
+ uint8_t DMAERREN : 1; //!< [5] DMAERR Interrupt Enable
+ uint8_t RESERVED0 : 1; //!< [6]
+ uint8_t BTSERREN : 1; //!< [7] BTSERR Interrupt Enable
+ } B;
+} hw_usb_erren_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_ERREN register
+ */
+//@{
+#define HW_USB_ERREN_ADDR (REGS_USB_BASE + 0x8CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_ERREN (*(__IO hw_usb_erren_t *) HW_USB_ERREN_ADDR)
+#define HW_USB_ERREN_RD() (HW_USB_ERREN.U)
+#define HW_USB_ERREN_WR(v) (HW_USB_ERREN.U = (v))
+#define HW_USB_ERREN_SET(v) (HW_USB_ERREN_WR(HW_USB_ERREN_RD() | (v)))
+#define HW_USB_ERREN_CLR(v) (HW_USB_ERREN_WR(HW_USB_ERREN_RD() & ~(v)))
+#define HW_USB_ERREN_TOG(v) (HW_USB_ERREN_WR(HW_USB_ERREN_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_ERREN bitfields
+ */
+
+/*!
+ * @name Register USB_ERREN, field PIDERREN[0] (RW)
+ *
+ * Values:
+ * - 0 - Disables the PIDERR interrupt.
+ * - 1 - Enters the PIDERR interrupt.
+ */
+//@{
+#define BP_USB_ERREN_PIDERREN (0U) //!< Bit position for USB_ERREN_PIDERREN.
+#define BM_USB_ERREN_PIDERREN (0x01U) //!< Bit mask for USB_ERREN_PIDERREN.
+#define BS_USB_ERREN_PIDERREN (1U) //!< Bit field size in bits for USB_ERREN_PIDERREN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ERREN_PIDERREN field.
+#define BR_USB_ERREN_PIDERREN (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_PIDERREN))
+#endif
+
+//! @brief Format value for bitfield USB_ERREN_PIDERREN.
+#define BF_USB_ERREN_PIDERREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERREN_PIDERREN), uint8_t) & BM_USB_ERREN_PIDERREN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PIDERREN field to a new value.
+#define BW_USB_ERREN_PIDERREN(v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_PIDERREN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ERREN, field CRC5EOFEN[1] (RW)
+ *
+ * Values:
+ * - 0 - Disables the CRC5/EOF interrupt.
+ * - 1 - Enables the CRC5/EOF interrupt.
+ */
+//@{
+#define BP_USB_ERREN_CRC5EOFEN (1U) //!< Bit position for USB_ERREN_CRC5EOFEN.
+#define BM_USB_ERREN_CRC5EOFEN (0x02U) //!< Bit mask for USB_ERREN_CRC5EOFEN.
+#define BS_USB_ERREN_CRC5EOFEN (1U) //!< Bit field size in bits for USB_ERREN_CRC5EOFEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ERREN_CRC5EOFEN field.
+#define BR_USB_ERREN_CRC5EOFEN (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_CRC5EOFEN))
+#endif
+
+//! @brief Format value for bitfield USB_ERREN_CRC5EOFEN.
+#define BF_USB_ERREN_CRC5EOFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERREN_CRC5EOFEN), uint8_t) & BM_USB_ERREN_CRC5EOFEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CRC5EOFEN field to a new value.
+#define BW_USB_ERREN_CRC5EOFEN(v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_CRC5EOFEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ERREN, field CRC16EN[2] (RW)
+ *
+ * Values:
+ * - 0 - Disables the CRC16 interrupt.
+ * - 1 - Enables the CRC16 interrupt.
+ */
+//@{
+#define BP_USB_ERREN_CRC16EN (2U) //!< Bit position for USB_ERREN_CRC16EN.
+#define BM_USB_ERREN_CRC16EN (0x04U) //!< Bit mask for USB_ERREN_CRC16EN.
+#define BS_USB_ERREN_CRC16EN (1U) //!< Bit field size in bits for USB_ERREN_CRC16EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ERREN_CRC16EN field.
+#define BR_USB_ERREN_CRC16EN (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_CRC16EN))
+#endif
+
+//! @brief Format value for bitfield USB_ERREN_CRC16EN.
+#define BF_USB_ERREN_CRC16EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERREN_CRC16EN), uint8_t) & BM_USB_ERREN_CRC16EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CRC16EN field to a new value.
+#define BW_USB_ERREN_CRC16EN(v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_CRC16EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ERREN, field DFN8EN[3] (RW)
+ *
+ * Values:
+ * - 0 - Disables the DFN8 interrupt.
+ * - 1 - Enables the DFN8 interrupt.
+ */
+//@{
+#define BP_USB_ERREN_DFN8EN (3U) //!< Bit position for USB_ERREN_DFN8EN.
+#define BM_USB_ERREN_DFN8EN (0x08U) //!< Bit mask for USB_ERREN_DFN8EN.
+#define BS_USB_ERREN_DFN8EN (1U) //!< Bit field size in bits for USB_ERREN_DFN8EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ERREN_DFN8EN field.
+#define BR_USB_ERREN_DFN8EN (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_DFN8EN))
+#endif
+
+//! @brief Format value for bitfield USB_ERREN_DFN8EN.
+#define BF_USB_ERREN_DFN8EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERREN_DFN8EN), uint8_t) & BM_USB_ERREN_DFN8EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DFN8EN field to a new value.
+#define BW_USB_ERREN_DFN8EN(v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_DFN8EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ERREN, field BTOERREN[4] (RW)
+ *
+ * Values:
+ * - 0 - Disables the BTOERR interrupt.
+ * - 1 - Enables the BTOERR interrupt.
+ */
+//@{
+#define BP_USB_ERREN_BTOERREN (4U) //!< Bit position for USB_ERREN_BTOERREN.
+#define BM_USB_ERREN_BTOERREN (0x10U) //!< Bit mask for USB_ERREN_BTOERREN.
+#define BS_USB_ERREN_BTOERREN (1U) //!< Bit field size in bits for USB_ERREN_BTOERREN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ERREN_BTOERREN field.
+#define BR_USB_ERREN_BTOERREN (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_BTOERREN))
+#endif
+
+//! @brief Format value for bitfield USB_ERREN_BTOERREN.
+#define BF_USB_ERREN_BTOERREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERREN_BTOERREN), uint8_t) & BM_USB_ERREN_BTOERREN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BTOERREN field to a new value.
+#define BW_USB_ERREN_BTOERREN(v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_BTOERREN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ERREN, field DMAERREN[5] (RW)
+ *
+ * Values:
+ * - 0 - Disables the DMAERR interrupt.
+ * - 1 - Enables the DMAERR interrupt.
+ */
+//@{
+#define BP_USB_ERREN_DMAERREN (5U) //!< Bit position for USB_ERREN_DMAERREN.
+#define BM_USB_ERREN_DMAERREN (0x20U) //!< Bit mask for USB_ERREN_DMAERREN.
+#define BS_USB_ERREN_DMAERREN (1U) //!< Bit field size in bits for USB_ERREN_DMAERREN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ERREN_DMAERREN field.
+#define BR_USB_ERREN_DMAERREN (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_DMAERREN))
+#endif
+
+//! @brief Format value for bitfield USB_ERREN_DMAERREN.
+#define BF_USB_ERREN_DMAERREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERREN_DMAERREN), uint8_t) & BM_USB_ERREN_DMAERREN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DMAERREN field to a new value.
+#define BW_USB_ERREN_DMAERREN(v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_DMAERREN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ERREN, field BTSERREN[7] (RW)
+ *
+ * Values:
+ * - 0 - Disables the BTSERR interrupt.
+ * - 1 - Enables the BTSERR interrupt.
+ */
+//@{
+#define BP_USB_ERREN_BTSERREN (7U) //!< Bit position for USB_ERREN_BTSERREN.
+#define BM_USB_ERREN_BTSERREN (0x80U) //!< Bit mask for USB_ERREN_BTSERREN.
+#define BS_USB_ERREN_BTSERREN (1U) //!< Bit field size in bits for USB_ERREN_BTSERREN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ERREN_BTSERREN field.
+#define BR_USB_ERREN_BTSERREN (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_BTSERREN))
+#endif
+
+//! @brief Format value for bitfield USB_ERREN_BTSERREN.
+#define BF_USB_ERREN_BTSERREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ERREN_BTSERREN), uint8_t) & BM_USB_ERREN_BTSERREN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BTSERREN field to a new value.
+#define BW_USB_ERREN_BTSERREN(v) (BITBAND_ACCESS8(HW_USB_ERREN_ADDR, BP_USB_ERREN_BTSERREN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_STAT - Status register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_STAT - Status register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * Reports the transaction status within the USB module. When the processor's
+ * interrupt controller has received a TOKDNE, interrupt the Status Register must
+ * be read to determine the status of the previous endpoint communication. The
+ * data in the status register is valid when TOKDNE interrupt is asserted. The
+ * Status register is actually a read window into a status FIFO maintained by the USB
+ * module. When the USB module uses a BD, it updates the Status register. If
+ * another USB transaction is performed before the TOKDNE interrupt is serviced, the
+ * USB module stores the status of the next transaction in the STAT FIFO. Thus
+ * STAT is actually a four byte FIFO that allows the processor core to process one
+ * transaction while the SIE is processing the next transaction. Clearing the
+ * TOKDNE bit in the ISTAT register causes the SIE to update STAT with the contents
+ * of the next STAT value. If the data in the STAT holding register is valid, the
+ * SIE immediately reasserts to TOKDNE interrupt.
+ */
+typedef union _hw_usb_stat
+{
+ uint8_t U;
+ struct _hw_usb_stat_bitfields
+ {
+ uint8_t RESERVED0 : 2; //!< [1:0]
+ uint8_t ODD : 1; //!< [2]
+ uint8_t TX : 1; //!< [3] Transmit Indicator
+ uint8_t ENDP : 4; //!< [7:4]
+ } B;
+} hw_usb_stat_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_STAT register
+ */
+//@{
+#define HW_USB_STAT_ADDR (REGS_USB_BASE + 0x90U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_STAT (*(__I hw_usb_stat_t *) HW_USB_STAT_ADDR)
+#define HW_USB_STAT_RD() (HW_USB_STAT.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_STAT bitfields
+ */
+
+/*!
+ * @name Register USB_STAT, field ODD[2] (RO)
+ *
+ * This bit is set if the last buffer descriptor updated was in the odd bank of
+ * the BDT.
+ */
+//@{
+#define BP_USB_STAT_ODD (2U) //!< Bit position for USB_STAT_ODD.
+#define BM_USB_STAT_ODD (0x04U) //!< Bit mask for USB_STAT_ODD.
+#define BS_USB_STAT_ODD (1U) //!< Bit field size in bits for USB_STAT_ODD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_STAT_ODD field.
+#define BR_USB_STAT_ODD (BITBAND_ACCESS8(HW_USB_STAT_ADDR, BP_USB_STAT_ODD))
+#endif
+//@}
+
+/*!
+ * @name Register USB_STAT, field TX[3] (RO)
+ *
+ * Values:
+ * - 0 - The most recent transaction was a receive operation.
+ * - 1 - The most recent transaction was a transmit operation.
+ */
+//@{
+#define BP_USB_STAT_TX (3U) //!< Bit position for USB_STAT_TX.
+#define BM_USB_STAT_TX (0x08U) //!< Bit mask for USB_STAT_TX.
+#define BS_USB_STAT_TX (1U) //!< Bit field size in bits for USB_STAT_TX.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_STAT_TX field.
+#define BR_USB_STAT_TX (BITBAND_ACCESS8(HW_USB_STAT_ADDR, BP_USB_STAT_TX))
+#endif
+//@}
+
+/*!
+ * @name Register USB_STAT, field ENDP[7:4] (RO)
+ *
+ * This four-bit field encodes the endpoint address that received or transmitted
+ * the previous token. This allows the processor core to determine the BDT entry
+ * that was updated by the last USB transaction.
+ */
+//@{
+#define BP_USB_STAT_ENDP (4U) //!< Bit position for USB_STAT_ENDP.
+#define BM_USB_STAT_ENDP (0xF0U) //!< Bit mask for USB_STAT_ENDP.
+#define BS_USB_STAT_ENDP (4U) //!< Bit field size in bits for USB_STAT_ENDP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_STAT_ENDP field.
+#define BR_USB_STAT_ENDP (HW_USB_STAT.B.ENDP)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_CTL - Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_CTL - Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Provides various control and configuration information for the USB module.
+ */
+typedef union _hw_usb_ctl
+{
+ uint8_t U;
+ struct _hw_usb_ctl_bitfields
+ {
+ uint8_t USBENSOFEN : 1; //!< [0] USB Enable
+ uint8_t ODDRST : 1; //!< [1]
+ uint8_t RESUME : 1; //!< [2]
+ uint8_t HOSTMODEEN : 1; //!< [3]
+ uint8_t RESET : 1; //!< [4]
+ uint8_t TXSUSPENDTOKENBUSY : 1; //!< [5]
+ uint8_t SE0 : 1; //!< [6] Live USB Single Ended Zero signal
+ uint8_t JSTATE : 1; //!< [7] Live USB differential receiver JSTATE
+ //! signal
+ } B;
+} hw_usb_ctl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_CTL register
+ */
+//@{
+#define HW_USB_CTL_ADDR (REGS_USB_BASE + 0x94U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_CTL (*(__IO hw_usb_ctl_t *) HW_USB_CTL_ADDR)
+#define HW_USB_CTL_RD() (HW_USB_CTL.U)
+#define HW_USB_CTL_WR(v) (HW_USB_CTL.U = (v))
+#define HW_USB_CTL_SET(v) (HW_USB_CTL_WR(HW_USB_CTL_RD() | (v)))
+#define HW_USB_CTL_CLR(v) (HW_USB_CTL_WR(HW_USB_CTL_RD() & ~(v)))
+#define HW_USB_CTL_TOG(v) (HW_USB_CTL_WR(HW_USB_CTL_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_CTL bitfields
+ */
+
+/*!
+ * @name Register USB_CTL, field USBENSOFEN[0] (RW)
+ *
+ * Setting this bit enables the USB-FS to operate; clearing it disables the
+ * USB-FS. Setting the bit causes the SIE to reset all of its ODD bits to the BDTs.
+ * Therefore, setting this bit resets much of the logic in the SIE. When host mode
+ * is enabled, clearing this bit causes the SIE to stop sending SOF tokens.
+ *
+ * Values:
+ * - 0 - Disables the USB Module.
+ * - 1 - Enables the USB Module.
+ */
+//@{
+#define BP_USB_CTL_USBENSOFEN (0U) //!< Bit position for USB_CTL_USBENSOFEN.
+#define BM_USB_CTL_USBENSOFEN (0x01U) //!< Bit mask for USB_CTL_USBENSOFEN.
+#define BS_USB_CTL_USBENSOFEN (1U) //!< Bit field size in bits for USB_CTL_USBENSOFEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CTL_USBENSOFEN field.
+#define BR_USB_CTL_USBENSOFEN (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_USBENSOFEN))
+#endif
+
+//! @brief Format value for bitfield USB_CTL_USBENSOFEN.
+#define BF_USB_CTL_USBENSOFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CTL_USBENSOFEN), uint8_t) & BM_USB_CTL_USBENSOFEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the USBENSOFEN field to a new value.
+#define BW_USB_CTL_USBENSOFEN(v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_USBENSOFEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_CTL, field ODDRST[1] (RW)
+ *
+ * Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0, which
+ * then specifies the EVEN BDT bank.
+ */
+//@{
+#define BP_USB_CTL_ODDRST (1U) //!< Bit position for USB_CTL_ODDRST.
+#define BM_USB_CTL_ODDRST (0x02U) //!< Bit mask for USB_CTL_ODDRST.
+#define BS_USB_CTL_ODDRST (1U) //!< Bit field size in bits for USB_CTL_ODDRST.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CTL_ODDRST field.
+#define BR_USB_CTL_ODDRST (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_ODDRST))
+#endif
+
+//! @brief Format value for bitfield USB_CTL_ODDRST.
+#define BF_USB_CTL_ODDRST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CTL_ODDRST), uint8_t) & BM_USB_CTL_ODDRST)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ODDRST field to a new value.
+#define BW_USB_CTL_ODDRST(v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_ODDRST) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_CTL, field RESUME[2] (RW)
+ *
+ * When set to 1 this bit enables the USB Module to execute resume signaling.
+ * This allows the USB Module to perform remote wake-up. Software must set RESUME
+ * to 1 for the required amount of time and then clear it to 0. If the HOSTMODEEN
+ * bit is set, the USB module appends a Low Speed End of Packet to the Resume
+ * signaling when the RESUME bit is cleared. For more information on RESUME
+ * signaling see Section 7.1.4.5 of the USB specification version 1.0.
+ */
+//@{
+#define BP_USB_CTL_RESUME (2U) //!< Bit position for USB_CTL_RESUME.
+#define BM_USB_CTL_RESUME (0x04U) //!< Bit mask for USB_CTL_RESUME.
+#define BS_USB_CTL_RESUME (1U) //!< Bit field size in bits for USB_CTL_RESUME.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CTL_RESUME field.
+#define BR_USB_CTL_RESUME (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_RESUME))
+#endif
+
+//! @brief Format value for bitfield USB_CTL_RESUME.
+#define BF_USB_CTL_RESUME(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CTL_RESUME), uint8_t) & BM_USB_CTL_RESUME)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RESUME field to a new value.
+#define BW_USB_CTL_RESUME(v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_RESUME) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_CTL, field HOSTMODEEN[3] (RW)
+ *
+ * When set to 1, this bit enables the USB Module to operate in Host mode. In
+ * host mode, the USB module performs USB transactions under the programmed control
+ * of the host processor.
+ */
+//@{
+#define BP_USB_CTL_HOSTMODEEN (3U) //!< Bit position for USB_CTL_HOSTMODEEN.
+#define BM_USB_CTL_HOSTMODEEN (0x08U) //!< Bit mask for USB_CTL_HOSTMODEEN.
+#define BS_USB_CTL_HOSTMODEEN (1U) //!< Bit field size in bits for USB_CTL_HOSTMODEEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CTL_HOSTMODEEN field.
+#define BR_USB_CTL_HOSTMODEEN (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_HOSTMODEEN))
+#endif
+
+//! @brief Format value for bitfield USB_CTL_HOSTMODEEN.
+#define BF_USB_CTL_HOSTMODEEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CTL_HOSTMODEEN), uint8_t) & BM_USB_CTL_HOSTMODEEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HOSTMODEEN field to a new value.
+#define BW_USB_CTL_HOSTMODEEN(v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_HOSTMODEEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_CTL, field RESET[4] (RW)
+ *
+ * Setting this bit enables the USB Module to generate USB reset signaling. This
+ * allows the USB Module to reset USB peripherals. This control signal is only
+ * valid in Host mode (HOSTMODEEN=1). Software must set RESET to 1 for the
+ * required amount of time and then clear it to 0 to end reset signaling. For more
+ * information on reset signaling see Section 7.1.4.3 of the USB specification version
+ * 1.0.
+ */
+//@{
+#define BP_USB_CTL_RESET (4U) //!< Bit position for USB_CTL_RESET.
+#define BM_USB_CTL_RESET (0x10U) //!< Bit mask for USB_CTL_RESET.
+#define BS_USB_CTL_RESET (1U) //!< Bit field size in bits for USB_CTL_RESET.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CTL_RESET field.
+#define BR_USB_CTL_RESET (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_RESET))
+#endif
+
+//! @brief Format value for bitfield USB_CTL_RESET.
+#define BF_USB_CTL_RESET(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CTL_RESET), uint8_t) & BM_USB_CTL_RESET)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RESET field to a new value.
+#define BW_USB_CTL_RESET(v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_RESET) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_CTL, field TXSUSPENDTOKENBUSY[5] (RW)
+ *
+ * In Host mode, TOKEN_BUSY is set when the USB module is busy executing a USB
+ * token. Software must not write more token commands to the Token Register when
+ * TOKEN_BUSY is set. Software should check this field before writing any tokens
+ * to the Token Register to ensure that token commands are not lost. In Target
+ * mode, TXD_SUSPEND is set when the SIE has disabled packet transmission and
+ * reception. Clearing this bit allows the SIE to continue token processing. This bit
+ * is set by the SIE when a SETUP Token is received allowing software to dequeue
+ * any pending packet transactions in the BDT before resuming token processing.
+ */
+//@{
+#define BP_USB_CTL_TXSUSPENDTOKENBUSY (5U) //!< Bit position for USB_CTL_TXSUSPENDTOKENBUSY.
+#define BM_USB_CTL_TXSUSPENDTOKENBUSY (0x20U) //!< Bit mask for USB_CTL_TXSUSPENDTOKENBUSY.
+#define BS_USB_CTL_TXSUSPENDTOKENBUSY (1U) //!< Bit field size in bits for USB_CTL_TXSUSPENDTOKENBUSY.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CTL_TXSUSPENDTOKENBUSY field.
+#define BR_USB_CTL_TXSUSPENDTOKENBUSY (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_TXSUSPENDTOKENBUSY))
+#endif
+
+//! @brief Format value for bitfield USB_CTL_TXSUSPENDTOKENBUSY.
+#define BF_USB_CTL_TXSUSPENDTOKENBUSY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CTL_TXSUSPENDTOKENBUSY), uint8_t) & BM_USB_CTL_TXSUSPENDTOKENBUSY)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXSUSPENDTOKENBUSY field to a new value.
+#define BW_USB_CTL_TXSUSPENDTOKENBUSY(v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_TXSUSPENDTOKENBUSY) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_CTL, field SE0[6] (RW)
+ */
+//@{
+#define BP_USB_CTL_SE0 (6U) //!< Bit position for USB_CTL_SE0.
+#define BM_USB_CTL_SE0 (0x40U) //!< Bit mask for USB_CTL_SE0.
+#define BS_USB_CTL_SE0 (1U) //!< Bit field size in bits for USB_CTL_SE0.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CTL_SE0 field.
+#define BR_USB_CTL_SE0 (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_SE0))
+#endif
+
+//! @brief Format value for bitfield USB_CTL_SE0.
+#define BF_USB_CTL_SE0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CTL_SE0), uint8_t) & BM_USB_CTL_SE0)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SE0 field to a new value.
+#define BW_USB_CTL_SE0(v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_SE0) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_CTL, field JSTATE[7] (RW)
+ *
+ * The polarity of this signal is affected by the current state of LSEN .
+ */
+//@{
+#define BP_USB_CTL_JSTATE (7U) //!< Bit position for USB_CTL_JSTATE.
+#define BM_USB_CTL_JSTATE (0x80U) //!< Bit mask for USB_CTL_JSTATE.
+#define BS_USB_CTL_JSTATE (1U) //!< Bit field size in bits for USB_CTL_JSTATE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CTL_JSTATE field.
+#define BR_USB_CTL_JSTATE (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_JSTATE))
+#endif
+
+//! @brief Format value for bitfield USB_CTL_JSTATE.
+#define BF_USB_CTL_JSTATE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CTL_JSTATE), uint8_t) & BM_USB_CTL_JSTATE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the JSTATE field to a new value.
+#define BW_USB_CTL_JSTATE(v) (BITBAND_ACCESS8(HW_USB_CTL_ADDR, BP_USB_CTL_JSTATE) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_ADDR - Address register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_ADDR - Address register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Holds the unique USB address that the USB module decodes when in Peripheral
+ * mode (HOSTMODEEN=0). When operating in Host mode (HOSTMODEEN=1) the USB module
+ * transmits this address with a TOKEN packet. This enables the USB module to
+ * uniquely address any USB peripheral. In either mode, CTL[USBENSOFEN] must be 1.
+ * The Address register is reset to 0x00 after the reset input becomes active or
+ * the USB module decodes a USB reset signal. This action initializes the Address
+ * register to decode address 0x00 as required by the USB specification.
+ */
+typedef union _hw_usb_addr
+{
+ uint8_t U;
+ struct _hw_usb_addr_bitfields
+ {
+ uint8_t ADDR : 7; //!< [6:0] USB Address
+ uint8_t LSEN : 1; //!< [7] Low Speed Enable bit
+ } B;
+} hw_usb_addr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_ADDR register
+ */
+//@{
+#define HW_USB_ADDR_ADDR (REGS_USB_BASE + 0x98U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_ADDR (*(__IO hw_usb_addr_t *) HW_USB_ADDR_ADDR)
+#define HW_USB_ADDR_RD() (HW_USB_ADDR.U)
+#define HW_USB_ADDR_WR(v) (HW_USB_ADDR.U = (v))
+#define HW_USB_ADDR_SET(v) (HW_USB_ADDR_WR(HW_USB_ADDR_RD() | (v)))
+#define HW_USB_ADDR_CLR(v) (HW_USB_ADDR_WR(HW_USB_ADDR_RD() & ~(v)))
+#define HW_USB_ADDR_TOG(v) (HW_USB_ADDR_WR(HW_USB_ADDR_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_ADDR bitfields
+ */
+
+/*!
+ * @name Register USB_ADDR, field ADDR[6:0] (RW)
+ *
+ * Defines the USB address that the USB module decodes in peripheral mode, or
+ * transmits when in host mode.
+ */
+//@{
+#define BP_USB_ADDR_ADDR (0U) //!< Bit position for USB_ADDR_ADDR.
+#define BM_USB_ADDR_ADDR (0x7FU) //!< Bit mask for USB_ADDR_ADDR.
+#define BS_USB_ADDR_ADDR (7U) //!< Bit field size in bits for USB_ADDR_ADDR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ADDR_ADDR field.
+#define BR_USB_ADDR_ADDR (HW_USB_ADDR.B.ADDR)
+#endif
+
+//! @brief Format value for bitfield USB_ADDR_ADDR.
+#define BF_USB_ADDR_ADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ADDR_ADDR), uint8_t) & BM_USB_ADDR_ADDR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADDR field to a new value.
+#define BW_USB_ADDR_ADDR(v) (HW_USB_ADDR_WR((HW_USB_ADDR_RD() & ~BM_USB_ADDR_ADDR) | BF_USB_ADDR_ADDR(v)))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ADDR, field LSEN[7] (RW)
+ *
+ * Informs the USB module that the next token command written to the token
+ * register must be performed at low speed. This enables the USB module to perform the
+ * necessary preamble required for low-speed data transmissions.
+ */
+//@{
+#define BP_USB_ADDR_LSEN (7U) //!< Bit position for USB_ADDR_LSEN.
+#define BM_USB_ADDR_LSEN (0x80U) //!< Bit mask for USB_ADDR_LSEN.
+#define BS_USB_ADDR_LSEN (1U) //!< Bit field size in bits for USB_ADDR_LSEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ADDR_LSEN field.
+#define BR_USB_ADDR_LSEN (BITBAND_ACCESS8(HW_USB_ADDR_ADDR, BP_USB_ADDR_LSEN))
+#endif
+
+//! @brief Format value for bitfield USB_ADDR_LSEN.
+#define BF_USB_ADDR_LSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ADDR_LSEN), uint8_t) & BM_USB_ADDR_LSEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LSEN field to a new value.
+#define BW_USB_ADDR_LSEN(v) (BITBAND_ACCESS8(HW_USB_ADDR_ADDR, BP_USB_ADDR_LSEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_BDTPAGE1 - BDT Page register 1
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_BDTPAGE1 - BDT Page register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Provides address bits 15 through 9 of the base address where the current
+ * Buffer Descriptor Table (BDT) resides in system memory. See Buffer Descriptor
+ * Table. The 32-bit BDT Base Address is always aligned on 512-byte boundaries, so
+ * bits 8 through 0 of the base address are always zero.
+ */
+typedef union _hw_usb_bdtpage1
+{
+ uint8_t U;
+ struct _hw_usb_bdtpage1_bitfields
+ {
+ uint8_t RESERVED0 : 1; //!< [0]
+ uint8_t BDTBA : 7; //!< [7:1]
+ } B;
+} hw_usb_bdtpage1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_BDTPAGE1 register
+ */
+//@{
+#define HW_USB_BDTPAGE1_ADDR (REGS_USB_BASE + 0x9CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_BDTPAGE1 (*(__IO hw_usb_bdtpage1_t *) HW_USB_BDTPAGE1_ADDR)
+#define HW_USB_BDTPAGE1_RD() (HW_USB_BDTPAGE1.U)
+#define HW_USB_BDTPAGE1_WR(v) (HW_USB_BDTPAGE1.U = (v))
+#define HW_USB_BDTPAGE1_SET(v) (HW_USB_BDTPAGE1_WR(HW_USB_BDTPAGE1_RD() | (v)))
+#define HW_USB_BDTPAGE1_CLR(v) (HW_USB_BDTPAGE1_WR(HW_USB_BDTPAGE1_RD() & ~(v)))
+#define HW_USB_BDTPAGE1_TOG(v) (HW_USB_BDTPAGE1_WR(HW_USB_BDTPAGE1_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_BDTPAGE1 bitfields
+ */
+
+/*!
+ * @name Register USB_BDTPAGE1, field BDTBA[7:1] (RW)
+ *
+ * Provides address bits 15 through 9 of the BDT base address.
+ */
+//@{
+#define BP_USB_BDTPAGE1_BDTBA (1U) //!< Bit position for USB_BDTPAGE1_BDTBA.
+#define BM_USB_BDTPAGE1_BDTBA (0xFEU) //!< Bit mask for USB_BDTPAGE1_BDTBA.
+#define BS_USB_BDTPAGE1_BDTBA (7U) //!< Bit field size in bits for USB_BDTPAGE1_BDTBA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_BDTPAGE1_BDTBA field.
+#define BR_USB_BDTPAGE1_BDTBA (HW_USB_BDTPAGE1.B.BDTBA)
+#endif
+
+//! @brief Format value for bitfield USB_BDTPAGE1_BDTBA.
+#define BF_USB_BDTPAGE1_BDTBA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_BDTPAGE1_BDTBA), uint8_t) & BM_USB_BDTPAGE1_BDTBA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BDTBA field to a new value.
+#define BW_USB_BDTPAGE1_BDTBA(v) (HW_USB_BDTPAGE1_WR((HW_USB_BDTPAGE1_RD() & ~BM_USB_BDTPAGE1_BDTBA) | BF_USB_BDTPAGE1_BDTBA(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_FRMNUML - Frame Number register Low
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_FRMNUML - Frame Number register Low (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The Frame Number registers (low and high) contain the 11-bit frame number.
+ * These registers are updated with the current frame number whenever a SOF TOKEN
+ * is received.
+ */
+typedef union _hw_usb_frmnuml
+{
+ uint8_t U;
+ struct _hw_usb_frmnuml_bitfields
+ {
+ uint8_t FRM : 8; //!< [7:0]
+ } B;
+} hw_usb_frmnuml_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_FRMNUML register
+ */
+//@{
+#define HW_USB_FRMNUML_ADDR (REGS_USB_BASE + 0xA0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_FRMNUML (*(__IO hw_usb_frmnuml_t *) HW_USB_FRMNUML_ADDR)
+#define HW_USB_FRMNUML_RD() (HW_USB_FRMNUML.U)
+#define HW_USB_FRMNUML_WR(v) (HW_USB_FRMNUML.U = (v))
+#define HW_USB_FRMNUML_SET(v) (HW_USB_FRMNUML_WR(HW_USB_FRMNUML_RD() | (v)))
+#define HW_USB_FRMNUML_CLR(v) (HW_USB_FRMNUML_WR(HW_USB_FRMNUML_RD() & ~(v)))
+#define HW_USB_FRMNUML_TOG(v) (HW_USB_FRMNUML_WR(HW_USB_FRMNUML_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_FRMNUML bitfields
+ */
+
+/*!
+ * @name Register USB_FRMNUML, field FRM[7:0] (RW)
+ *
+ * This 8-bit field and the 3-bit field in the Frame Number Register High are
+ * used to compute the address where the current Buffer Descriptor Table (BDT)
+ * resides in system memory.
+ */
+//@{
+#define BP_USB_FRMNUML_FRM (0U) //!< Bit position for USB_FRMNUML_FRM.
+#define BM_USB_FRMNUML_FRM (0xFFU) //!< Bit mask for USB_FRMNUML_FRM.
+#define BS_USB_FRMNUML_FRM (8U) //!< Bit field size in bits for USB_FRMNUML_FRM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_FRMNUML_FRM field.
+#define BR_USB_FRMNUML_FRM (HW_USB_FRMNUML.U)
+#endif
+
+//! @brief Format value for bitfield USB_FRMNUML_FRM.
+#define BF_USB_FRMNUML_FRM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_FRMNUML_FRM), uint8_t) & BM_USB_FRMNUML_FRM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FRM field to a new value.
+#define BW_USB_FRMNUML_FRM(v) (HW_USB_FRMNUML_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_FRMNUMH - Frame Number register High
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_FRMNUMH - Frame Number register High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The Frame Number registers (low and high) contain the 11-bit frame number.
+ * These registers are updated with the current frame number whenever a SOF TOKEN
+ * is received.
+ */
+typedef union _hw_usb_frmnumh
+{
+ uint8_t U;
+ struct _hw_usb_frmnumh_bitfields
+ {
+ uint8_t FRM : 3; //!< [2:0]
+ uint8_t RESERVED0 : 5; //!< [7:3]
+ } B;
+} hw_usb_frmnumh_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_FRMNUMH register
+ */
+//@{
+#define HW_USB_FRMNUMH_ADDR (REGS_USB_BASE + 0xA4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_FRMNUMH (*(__IO hw_usb_frmnumh_t *) HW_USB_FRMNUMH_ADDR)
+#define HW_USB_FRMNUMH_RD() (HW_USB_FRMNUMH.U)
+#define HW_USB_FRMNUMH_WR(v) (HW_USB_FRMNUMH.U = (v))
+#define HW_USB_FRMNUMH_SET(v) (HW_USB_FRMNUMH_WR(HW_USB_FRMNUMH_RD() | (v)))
+#define HW_USB_FRMNUMH_CLR(v) (HW_USB_FRMNUMH_WR(HW_USB_FRMNUMH_RD() & ~(v)))
+#define HW_USB_FRMNUMH_TOG(v) (HW_USB_FRMNUMH_WR(HW_USB_FRMNUMH_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_FRMNUMH bitfields
+ */
+
+/*!
+ * @name Register USB_FRMNUMH, field FRM[2:0] (RW)
+ *
+ * This 3-bit field and the 8-bit field in the Frame Number Register Low are
+ * used to compute the address where the current Buffer Descriptor Table (BDT)
+ * resides in system memory.
+ */
+//@{
+#define BP_USB_FRMNUMH_FRM (0U) //!< Bit position for USB_FRMNUMH_FRM.
+#define BM_USB_FRMNUMH_FRM (0x07U) //!< Bit mask for USB_FRMNUMH_FRM.
+#define BS_USB_FRMNUMH_FRM (3U) //!< Bit field size in bits for USB_FRMNUMH_FRM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_FRMNUMH_FRM field.
+#define BR_USB_FRMNUMH_FRM (HW_USB_FRMNUMH.B.FRM)
+#endif
+
+//! @brief Format value for bitfield USB_FRMNUMH_FRM.
+#define BF_USB_FRMNUMH_FRM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_FRMNUMH_FRM), uint8_t) & BM_USB_FRMNUMH_FRM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the FRM field to a new value.
+#define BW_USB_FRMNUMH_FRM(v) (HW_USB_FRMNUMH_WR((HW_USB_FRMNUMH_RD() & ~BM_USB_FRMNUMH_FRM) | BF_USB_FRMNUMH_FRM(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_TOKEN - Token register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_TOKEN - Token register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Used to initiate USB transactions when in host mode (HOSTMODEEN=1). When the
+ * software needs to execute a USB transaction to a peripheral, it writes the
+ * TOKEN type and endpoint to this register. After this register has been written,
+ * the USB module begins the specified USB transaction to the address contained in
+ * the address register. The processor core must always check that the
+ * TOKEN_BUSY bit in the control register is not 1 before writing to the Token Register.
+ * This ensures that the token commands are not overwritten before they can be
+ * executed. The address register and endpoint control register 0 are also used when
+ * performing a token command and therefore must also be written before the
+ * Token Register. The address register is used to select the USB peripheral address
+ * transmitted by the token command. The endpoint control register determines the
+ * handshake and retry policies used during the transfer.
+ */
+typedef union _hw_usb_token
+{
+ uint8_t U;
+ struct _hw_usb_token_bitfields
+ {
+ uint8_t TOKENENDPT : 4; //!< [3:0]
+ uint8_t TOKENPID : 4; //!< [7:4]
+ } B;
+} hw_usb_token_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_TOKEN register
+ */
+//@{
+#define HW_USB_TOKEN_ADDR (REGS_USB_BASE + 0xA8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_TOKEN (*(__IO hw_usb_token_t *) HW_USB_TOKEN_ADDR)
+#define HW_USB_TOKEN_RD() (HW_USB_TOKEN.U)
+#define HW_USB_TOKEN_WR(v) (HW_USB_TOKEN.U = (v))
+#define HW_USB_TOKEN_SET(v) (HW_USB_TOKEN_WR(HW_USB_TOKEN_RD() | (v)))
+#define HW_USB_TOKEN_CLR(v) (HW_USB_TOKEN_WR(HW_USB_TOKEN_RD() & ~(v)))
+#define HW_USB_TOKEN_TOG(v) (HW_USB_TOKEN_WR(HW_USB_TOKEN_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_TOKEN bitfields
+ */
+
+/*!
+ * @name Register USB_TOKEN, field TOKENENDPT[3:0] (RW)
+ *
+ * Holds the Endpoint address for the token command. The four bit value written
+ * must be a valid endpoint.
+ */
+//@{
+#define BP_USB_TOKEN_TOKENENDPT (0U) //!< Bit position for USB_TOKEN_TOKENENDPT.
+#define BM_USB_TOKEN_TOKENENDPT (0x0FU) //!< Bit mask for USB_TOKEN_TOKENENDPT.
+#define BS_USB_TOKEN_TOKENENDPT (4U) //!< Bit field size in bits for USB_TOKEN_TOKENENDPT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_TOKEN_TOKENENDPT field.
+#define BR_USB_TOKEN_TOKENENDPT (HW_USB_TOKEN.B.TOKENENDPT)
+#endif
+
+//! @brief Format value for bitfield USB_TOKEN_TOKENENDPT.
+#define BF_USB_TOKEN_TOKENENDPT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_TOKEN_TOKENENDPT), uint8_t) & BM_USB_TOKEN_TOKENENDPT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TOKENENDPT field to a new value.
+#define BW_USB_TOKEN_TOKENENDPT(v) (HW_USB_TOKEN_WR((HW_USB_TOKEN_RD() & ~BM_USB_TOKEN_TOKENENDPT) | BF_USB_TOKEN_TOKENENDPT(v)))
+#endif
+//@}
+
+/*!
+ * @name Register USB_TOKEN, field TOKENPID[7:4] (RW)
+ *
+ * Contains the token type executed by the USB module.
+ *
+ * Values:
+ * - 0001 - OUT Token. USB Module performs an OUT (TX) transaction.
+ * - 1001 - IN Token. USB Module performs an In (RX) transaction.
+ * - 1101 - SETUP Token. USB Module performs a SETUP (TX) transaction
+ */
+//@{
+#define BP_USB_TOKEN_TOKENPID (4U) //!< Bit position for USB_TOKEN_TOKENPID.
+#define BM_USB_TOKEN_TOKENPID (0xF0U) //!< Bit mask for USB_TOKEN_TOKENPID.
+#define BS_USB_TOKEN_TOKENPID (4U) //!< Bit field size in bits for USB_TOKEN_TOKENPID.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_TOKEN_TOKENPID field.
+#define BR_USB_TOKEN_TOKENPID (HW_USB_TOKEN.B.TOKENPID)
+#endif
+
+//! @brief Format value for bitfield USB_TOKEN_TOKENPID.
+#define BF_USB_TOKEN_TOKENPID(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_TOKEN_TOKENPID), uint8_t) & BM_USB_TOKEN_TOKENPID)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TOKENPID field to a new value.
+#define BW_USB_TOKEN_TOKENPID(v) (HW_USB_TOKEN_WR((HW_USB_TOKEN_RD() & ~BM_USB_TOKEN_TOKENPID) | BF_USB_TOKEN_TOKENPID(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_SOFTHLD - SOF Threshold register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_SOFTHLD - SOF Threshold register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The SOF Threshold Register is used only in Host mode (HOSTMODEEN=1). When in
+ * Host mode, the 14-bit SOF counter counts the interval between SOF frames. The
+ * SOF must be transmitted every 1ms so therefore the SOF counter is loaded with
+ * a value of 12000. When the SOF counter reaches zero, a Start Of Frame (SOF)
+ * token is transmitted. The SOF threshold register is used to program the number
+ * of USB byte times before the SOF to stop initiating token packet transactions.
+ * This register must be set to a value that ensures that other packets are not
+ * actively being transmitted when the SOF time counts to zero. When the SOF
+ * counter reaches the threshold value, no more tokens are transmitted until after the
+ * SOF has been transmitted. The value programmed into the threshold register
+ * must reserve enough time to ensure the worst case transaction completes. In
+ * general the worst case transaction is an IN token followed by a data packet from
+ * the target followed by the response from the host. The actual time required is
+ * a function of the maximum packet size on the bus. Typical values for the SOF
+ * threshold are: 64-byte packets=74; 32-byte packets=42; 16-byte packets=26;
+ * 8-byte packets=18.
+ */
+typedef union _hw_usb_softhld
+{
+ uint8_t U;
+ struct _hw_usb_softhld_bitfields
+ {
+ uint8_t CNT : 8; //!< [7:0]
+ } B;
+} hw_usb_softhld_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_SOFTHLD register
+ */
+//@{
+#define HW_USB_SOFTHLD_ADDR (REGS_USB_BASE + 0xACU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_SOFTHLD (*(__IO hw_usb_softhld_t *) HW_USB_SOFTHLD_ADDR)
+#define HW_USB_SOFTHLD_RD() (HW_USB_SOFTHLD.U)
+#define HW_USB_SOFTHLD_WR(v) (HW_USB_SOFTHLD.U = (v))
+#define HW_USB_SOFTHLD_SET(v) (HW_USB_SOFTHLD_WR(HW_USB_SOFTHLD_RD() | (v)))
+#define HW_USB_SOFTHLD_CLR(v) (HW_USB_SOFTHLD_WR(HW_USB_SOFTHLD_RD() & ~(v)))
+#define HW_USB_SOFTHLD_TOG(v) (HW_USB_SOFTHLD_WR(HW_USB_SOFTHLD_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_SOFTHLD bitfields
+ */
+
+/*!
+ * @name Register USB_SOFTHLD, field CNT[7:0] (RW)
+ *
+ * Represents the SOF count threshold in byte times.
+ */
+//@{
+#define BP_USB_SOFTHLD_CNT (0U) //!< Bit position for USB_SOFTHLD_CNT.
+#define BM_USB_SOFTHLD_CNT (0xFFU) //!< Bit mask for USB_SOFTHLD_CNT.
+#define BS_USB_SOFTHLD_CNT (8U) //!< Bit field size in bits for USB_SOFTHLD_CNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_SOFTHLD_CNT field.
+#define BR_USB_SOFTHLD_CNT (HW_USB_SOFTHLD.U)
+#endif
+
+//! @brief Format value for bitfield USB_SOFTHLD_CNT.
+#define BF_USB_SOFTHLD_CNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_SOFTHLD_CNT), uint8_t) & BM_USB_SOFTHLD_CNT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CNT field to a new value.
+#define BW_USB_SOFTHLD_CNT(v) (HW_USB_SOFTHLD_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_BDTPAGE2 - BDT Page Register 2
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_BDTPAGE2 - BDT Page Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains an 8-bit value used to compute the address where the current Buffer
+ * Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table.
+ */
+typedef union _hw_usb_bdtpage2
+{
+ uint8_t U;
+ struct _hw_usb_bdtpage2_bitfields
+ {
+ uint8_t BDTBA : 8; //!< [7:0]
+ } B;
+} hw_usb_bdtpage2_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_BDTPAGE2 register
+ */
+//@{
+#define HW_USB_BDTPAGE2_ADDR (REGS_USB_BASE + 0xB0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_BDTPAGE2 (*(__IO hw_usb_bdtpage2_t *) HW_USB_BDTPAGE2_ADDR)
+#define HW_USB_BDTPAGE2_RD() (HW_USB_BDTPAGE2.U)
+#define HW_USB_BDTPAGE2_WR(v) (HW_USB_BDTPAGE2.U = (v))
+#define HW_USB_BDTPAGE2_SET(v) (HW_USB_BDTPAGE2_WR(HW_USB_BDTPAGE2_RD() | (v)))
+#define HW_USB_BDTPAGE2_CLR(v) (HW_USB_BDTPAGE2_WR(HW_USB_BDTPAGE2_RD() & ~(v)))
+#define HW_USB_BDTPAGE2_TOG(v) (HW_USB_BDTPAGE2_WR(HW_USB_BDTPAGE2_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_BDTPAGE2 bitfields
+ */
+
+/*!
+ * @name Register USB_BDTPAGE2, field BDTBA[7:0] (RW)
+ *
+ * Provides address bits 23 through 16 of the BDT base address that defines the
+ * location of Buffer Descriptor Table resides in system memory.
+ */
+//@{
+#define BP_USB_BDTPAGE2_BDTBA (0U) //!< Bit position for USB_BDTPAGE2_BDTBA.
+#define BM_USB_BDTPAGE2_BDTBA (0xFFU) //!< Bit mask for USB_BDTPAGE2_BDTBA.
+#define BS_USB_BDTPAGE2_BDTBA (8U) //!< Bit field size in bits for USB_BDTPAGE2_BDTBA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_BDTPAGE2_BDTBA field.
+#define BR_USB_BDTPAGE2_BDTBA (HW_USB_BDTPAGE2.U)
+#endif
+
+//! @brief Format value for bitfield USB_BDTPAGE2_BDTBA.
+#define BF_USB_BDTPAGE2_BDTBA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_BDTPAGE2_BDTBA), uint8_t) & BM_USB_BDTPAGE2_BDTBA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BDTBA field to a new value.
+#define BW_USB_BDTPAGE2_BDTBA(v) (HW_USB_BDTPAGE2_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_BDTPAGE3 - BDT Page Register 3
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_BDTPAGE3 - BDT Page Register 3 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains an 8-bit value used to compute the address where the current Buffer
+ * Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table.
+ */
+typedef union _hw_usb_bdtpage3
+{
+ uint8_t U;
+ struct _hw_usb_bdtpage3_bitfields
+ {
+ uint8_t BDTBA : 8; //!< [7:0]
+ } B;
+} hw_usb_bdtpage3_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_BDTPAGE3 register
+ */
+//@{
+#define HW_USB_BDTPAGE3_ADDR (REGS_USB_BASE + 0xB4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_BDTPAGE3 (*(__IO hw_usb_bdtpage3_t *) HW_USB_BDTPAGE3_ADDR)
+#define HW_USB_BDTPAGE3_RD() (HW_USB_BDTPAGE3.U)
+#define HW_USB_BDTPAGE3_WR(v) (HW_USB_BDTPAGE3.U = (v))
+#define HW_USB_BDTPAGE3_SET(v) (HW_USB_BDTPAGE3_WR(HW_USB_BDTPAGE3_RD() | (v)))
+#define HW_USB_BDTPAGE3_CLR(v) (HW_USB_BDTPAGE3_WR(HW_USB_BDTPAGE3_RD() & ~(v)))
+#define HW_USB_BDTPAGE3_TOG(v) (HW_USB_BDTPAGE3_WR(HW_USB_BDTPAGE3_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_BDTPAGE3 bitfields
+ */
+
+/*!
+ * @name Register USB_BDTPAGE3, field BDTBA[7:0] (RW)
+ *
+ * Provides address bits 31 through 24 of the BDT base address that defines the
+ * location of Buffer Descriptor Table resides in system memory.
+ */
+//@{
+#define BP_USB_BDTPAGE3_BDTBA (0U) //!< Bit position for USB_BDTPAGE3_BDTBA.
+#define BM_USB_BDTPAGE3_BDTBA (0xFFU) //!< Bit mask for USB_BDTPAGE3_BDTBA.
+#define BS_USB_BDTPAGE3_BDTBA (8U) //!< Bit field size in bits for USB_BDTPAGE3_BDTBA.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_BDTPAGE3_BDTBA field.
+#define BR_USB_BDTPAGE3_BDTBA (HW_USB_BDTPAGE3.U)
+#endif
+
+//! @brief Format value for bitfield USB_BDTPAGE3_BDTBA.
+#define BF_USB_BDTPAGE3_BDTBA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_BDTPAGE3_BDTBA), uint8_t) & BM_USB_BDTPAGE3_BDTBA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BDTBA field to a new value.
+#define BW_USB_BDTPAGE3_BDTBA(v) (HW_USB_BDTPAGE3_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_ENDPTn - Endpoint Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_ENDPTn - Endpoint Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains the endpoint control bits for each of the 16 endpoints available
+ * within the USB module for a decoded address. The format for these registers is
+ * shown in the following figure. Endpoint 0 (ENDPT0) is associated with control
+ * pipe 0, which is required for all USB functions. Therefore, after a USBRST
+ * interrupt occurs the processor core should set ENDPT0 to contain 0x0D. In Host mode
+ * ENDPT0 is used to determine the handshake, retry and low speed
+ * characteristics of the host transfer. For Control, Bulk and Interrupt transfers, the EPHSHK
+ * bit should be 1. For Isochronous transfers it should be 0. Common values to
+ * use for ENDPT0 in host mode are 0x4D for Control, Bulk, and Interrupt transfers,
+ * and 0x4C for Isochronous transfers. The three bits EPCTLDIS, EPRXEN, and
+ * EPTXEN define if an endpoint is enabled and define the direction of the endpoint.
+ * The endpoint enable/direction control is defined in the following table.
+ * Endpoint enable and direction control EPCTLDIS EPRXEN EPTXEN Endpoint
+ * enable/direction control X 0 0 Disable endpoint X 0 1 Enable endpoint for Tx transfers only
+ * X 1 0 Enable endpoint for Rx transfers only 1 1 1 Enable endpoint for Rx and
+ * Tx transfers 0 1 1 Enable Endpoint for RX and TX as well as control (SETUP)
+ * transfers.
+ */
+typedef union _hw_usb_endptn
+{
+ uint8_t U;
+ struct _hw_usb_endptn_bitfields
+ {
+ uint8_t EPHSHK : 1; //!< [0]
+ uint8_t EPSTALL : 1; //!< [1]
+ uint8_t EPTXEN : 1; //!< [2]
+ uint8_t EPRXEN : 1; //!< [3]
+ uint8_t EPCTLDIS : 1; //!< [4]
+ uint8_t RESERVED0 : 1; //!< [5]
+ uint8_t RETRYDIS : 1; //!< [6]
+ uint8_t HOSTWOHUB : 1; //!< [7]
+ } B;
+} hw_usb_endptn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_ENDPTn register
+ */
+//@{
+#define HW_USB_ENDPTn_COUNT (16U)
+
+#define HW_USB_ENDPTn_ADDR(n) (REGS_USB_BASE + 0xC0U + (0x4U * n))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_ENDPTn(n) (*(__IO hw_usb_endptn_t *) HW_USB_ENDPTn_ADDR(n))
+#define HW_USB_ENDPTn_RD(n) (HW_USB_ENDPTn(n).U)
+#define HW_USB_ENDPTn_WR(n, v) (HW_USB_ENDPTn(n).U = (v))
+#define HW_USB_ENDPTn_SET(n, v) (HW_USB_ENDPTn_WR(n, HW_USB_ENDPTn_RD(n) | (v)))
+#define HW_USB_ENDPTn_CLR(n, v) (HW_USB_ENDPTn_WR(n, HW_USB_ENDPTn_RD(n) & ~(v)))
+#define HW_USB_ENDPTn_TOG(n, v) (HW_USB_ENDPTn_WR(n, HW_USB_ENDPTn_RD(n) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_ENDPTn bitfields
+ */
+
+/*!
+ * @name Register USB_ENDPTn, field EPHSHK[0] (RW)
+ *
+ * When set this bit enables an endpoint to perform handshaking during a
+ * transaction to this endpoint. This bit is generally 1 unless the endpoint is
+ * Isochronous.
+ */
+//@{
+#define BP_USB_ENDPTn_EPHSHK (0U) //!< Bit position for USB_ENDPTn_EPHSHK.
+#define BM_USB_ENDPTn_EPHSHK (0x01U) //!< Bit mask for USB_ENDPTn_EPHSHK.
+#define BS_USB_ENDPTn_EPHSHK (1U) //!< Bit field size in bits for USB_ENDPTn_EPHSHK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ENDPTn_EPHSHK field.
+#define BR_USB_ENDPTn_EPHSHK(n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPHSHK))
+#endif
+
+//! @brief Format value for bitfield USB_ENDPTn_EPHSHK.
+#define BF_USB_ENDPTn_EPHSHK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ENDPTn_EPHSHK), uint8_t) & BM_USB_ENDPTn_EPHSHK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EPHSHK field to a new value.
+#define BW_USB_ENDPTn_EPHSHK(n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPHSHK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ENDPTn, field EPSTALL[1] (RW)
+ *
+ * When set this bit indicates that the endpoint is called. This bit has
+ * priority over all other control bits in the EndPoint Enable Register, but it is only
+ * valid if EPTXEN=1 or EPRXEN=1. Any access to this endpoint causes the USB
+ * Module to return a STALL handshake. After an endpoint is stalled it requires
+ * intervention from the Host Controller.
+ */
+//@{
+#define BP_USB_ENDPTn_EPSTALL (1U) //!< Bit position for USB_ENDPTn_EPSTALL.
+#define BM_USB_ENDPTn_EPSTALL (0x02U) //!< Bit mask for USB_ENDPTn_EPSTALL.
+#define BS_USB_ENDPTn_EPSTALL (1U) //!< Bit field size in bits for USB_ENDPTn_EPSTALL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ENDPTn_EPSTALL field.
+#define BR_USB_ENDPTn_EPSTALL(n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPSTALL))
+#endif
+
+//! @brief Format value for bitfield USB_ENDPTn_EPSTALL.
+#define BF_USB_ENDPTn_EPSTALL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ENDPTn_EPSTALL), uint8_t) & BM_USB_ENDPTn_EPSTALL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EPSTALL field to a new value.
+#define BW_USB_ENDPTn_EPSTALL(n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPSTALL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ENDPTn, field EPTXEN[2] (RW)
+ *
+ * This bit, when set, enables the endpoint for TX transfers.
+ */
+//@{
+#define BP_USB_ENDPTn_EPTXEN (2U) //!< Bit position for USB_ENDPTn_EPTXEN.
+#define BM_USB_ENDPTn_EPTXEN (0x04U) //!< Bit mask for USB_ENDPTn_EPTXEN.
+#define BS_USB_ENDPTn_EPTXEN (1U) //!< Bit field size in bits for USB_ENDPTn_EPTXEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ENDPTn_EPTXEN field.
+#define BR_USB_ENDPTn_EPTXEN(n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPTXEN))
+#endif
+
+//! @brief Format value for bitfield USB_ENDPTn_EPTXEN.
+#define BF_USB_ENDPTn_EPTXEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ENDPTn_EPTXEN), uint8_t) & BM_USB_ENDPTn_EPTXEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EPTXEN field to a new value.
+#define BW_USB_ENDPTn_EPTXEN(n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPTXEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ENDPTn, field EPRXEN[3] (RW)
+ *
+ * This bit, when set, enables the endpoint for RX transfers.
+ */
+//@{
+#define BP_USB_ENDPTn_EPRXEN (3U) //!< Bit position for USB_ENDPTn_EPRXEN.
+#define BM_USB_ENDPTn_EPRXEN (0x08U) //!< Bit mask for USB_ENDPTn_EPRXEN.
+#define BS_USB_ENDPTn_EPRXEN (1U) //!< Bit field size in bits for USB_ENDPTn_EPRXEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ENDPTn_EPRXEN field.
+#define BR_USB_ENDPTn_EPRXEN(n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPRXEN))
+#endif
+
+//! @brief Format value for bitfield USB_ENDPTn_EPRXEN.
+#define BF_USB_ENDPTn_EPRXEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ENDPTn_EPRXEN), uint8_t) & BM_USB_ENDPTn_EPRXEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EPRXEN field to a new value.
+#define BW_USB_ENDPTn_EPRXEN(n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPRXEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ENDPTn, field EPCTLDIS[4] (RW)
+ *
+ * This bit, when set, disables control (SETUP) transfers. When cleared, control
+ * transfers are enabled. This applies if and only if the EPRXEN and EPTXEN bits
+ * are also set.
+ */
+//@{
+#define BP_USB_ENDPTn_EPCTLDIS (4U) //!< Bit position for USB_ENDPTn_EPCTLDIS.
+#define BM_USB_ENDPTn_EPCTLDIS (0x10U) //!< Bit mask for USB_ENDPTn_EPCTLDIS.
+#define BS_USB_ENDPTn_EPCTLDIS (1U) //!< Bit field size in bits for USB_ENDPTn_EPCTLDIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ENDPTn_EPCTLDIS field.
+#define BR_USB_ENDPTn_EPCTLDIS(n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPCTLDIS))
+#endif
+
+//! @brief Format value for bitfield USB_ENDPTn_EPCTLDIS.
+#define BF_USB_ENDPTn_EPCTLDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ENDPTn_EPCTLDIS), uint8_t) & BM_USB_ENDPTn_EPCTLDIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EPCTLDIS field to a new value.
+#define BW_USB_ENDPTn_EPCTLDIS(n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_EPCTLDIS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ENDPTn, field RETRYDIS[6] (RW)
+ *
+ * This is a Host mode only bit and is present in the control register for
+ * endpoint 0 (ENDPT0) only. When set this bit causes the host to not retry NAK'ed
+ * (Negative Acknowledgement) transactions. When a transaction is NAKed, the BDT PID
+ * field is updated with the NAK PID, and the TOKEN_DNE interrupt is set. When
+ * this bit is cleared, NAKed transactions are retried in hardware. This bit must
+ * be set when the host is attempting to poll an interrupt endpoint.
+ */
+//@{
+#define BP_USB_ENDPTn_RETRYDIS (6U) //!< Bit position for USB_ENDPTn_RETRYDIS.
+#define BM_USB_ENDPTn_RETRYDIS (0x40U) //!< Bit mask for USB_ENDPTn_RETRYDIS.
+#define BS_USB_ENDPTn_RETRYDIS (1U) //!< Bit field size in bits for USB_ENDPTn_RETRYDIS.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ENDPTn_RETRYDIS field.
+#define BR_USB_ENDPTn_RETRYDIS(n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_RETRYDIS))
+#endif
+
+//! @brief Format value for bitfield USB_ENDPTn_RETRYDIS.
+#define BF_USB_ENDPTn_RETRYDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ENDPTn_RETRYDIS), uint8_t) & BM_USB_ENDPTn_RETRYDIS)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RETRYDIS field to a new value.
+#define BW_USB_ENDPTn_RETRYDIS(n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_RETRYDIS) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_ENDPTn, field HOSTWOHUB[7] (RW)
+ *
+ * This is a Host mode only field and is present in the control register for
+ * endpoint 0 (ENDPT0) only. When set this bit allows the host to communicate to a
+ * directly connected low speed device. When cleared, the host produces the
+ * PRE_PID. It then switches to low-speed signaling when sending a token to a low speed
+ * device as required to communicate with a low speed device through a hub.
+ */
+//@{
+#define BP_USB_ENDPTn_HOSTWOHUB (7U) //!< Bit position for USB_ENDPTn_HOSTWOHUB.
+#define BM_USB_ENDPTn_HOSTWOHUB (0x80U) //!< Bit mask for USB_ENDPTn_HOSTWOHUB.
+#define BS_USB_ENDPTn_HOSTWOHUB (1U) //!< Bit field size in bits for USB_ENDPTn_HOSTWOHUB.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_ENDPTn_HOSTWOHUB field.
+#define BR_USB_ENDPTn_HOSTWOHUB(n) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_HOSTWOHUB))
+#endif
+
+//! @brief Format value for bitfield USB_ENDPTn_HOSTWOHUB.
+#define BF_USB_ENDPTn_HOSTWOHUB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_ENDPTn_HOSTWOHUB), uint8_t) & BM_USB_ENDPTn_HOSTWOHUB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the HOSTWOHUB field to a new value.
+#define BW_USB_ENDPTn_HOSTWOHUB(n, v) (BITBAND_ACCESS8(HW_USB_ENDPTn_ADDR(n), BP_USB_ENDPTn_HOSTWOHUB) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_USBCTRL - USB Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_USBCTRL - USB Control register (RW)
+ *
+ * Reset value: 0xC0U
+ */
+typedef union _hw_usb_usbctrl
+{
+ uint8_t U;
+ struct _hw_usb_usbctrl_bitfields
+ {
+ uint8_t RESERVED0 : 6; //!< [5:0]
+ uint8_t PDE : 1; //!< [6]
+ uint8_t SUSP : 1; //!< [7]
+ } B;
+} hw_usb_usbctrl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_USBCTRL register
+ */
+//@{
+#define HW_USB_USBCTRL_ADDR (REGS_USB_BASE + 0x100U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_USBCTRL (*(__IO hw_usb_usbctrl_t *) HW_USB_USBCTRL_ADDR)
+#define HW_USB_USBCTRL_RD() (HW_USB_USBCTRL.U)
+#define HW_USB_USBCTRL_WR(v) (HW_USB_USBCTRL.U = (v))
+#define HW_USB_USBCTRL_SET(v) (HW_USB_USBCTRL_WR(HW_USB_USBCTRL_RD() | (v)))
+#define HW_USB_USBCTRL_CLR(v) (HW_USB_USBCTRL_WR(HW_USB_USBCTRL_RD() & ~(v)))
+#define HW_USB_USBCTRL_TOG(v) (HW_USB_USBCTRL_WR(HW_USB_USBCTRL_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_USBCTRL bitfields
+ */
+
+/*!
+ * @name Register USB_USBCTRL, field PDE[6] (RW)
+ *
+ * Enables the weak pulldowns on the USB transceiver.
+ *
+ * Values:
+ * - 0 - Weak pulldowns are disabled on D+ and D-.
+ * - 1 - Weak pulldowns are enabled on D+ and D-.
+ */
+//@{
+#define BP_USB_USBCTRL_PDE (6U) //!< Bit position for USB_USBCTRL_PDE.
+#define BM_USB_USBCTRL_PDE (0x40U) //!< Bit mask for USB_USBCTRL_PDE.
+#define BS_USB_USBCTRL_PDE (1U) //!< Bit field size in bits for USB_USBCTRL_PDE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_USBCTRL_PDE field.
+#define BR_USB_USBCTRL_PDE (BITBAND_ACCESS8(HW_USB_USBCTRL_ADDR, BP_USB_USBCTRL_PDE))
+#endif
+
+//! @brief Format value for bitfield USB_USBCTRL_PDE.
+#define BF_USB_USBCTRL_PDE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_USBCTRL_PDE), uint8_t) & BM_USB_USBCTRL_PDE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PDE field to a new value.
+#define BW_USB_USBCTRL_PDE(v) (BITBAND_ACCESS8(HW_USB_USBCTRL_ADDR, BP_USB_USBCTRL_PDE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_USBCTRL, field SUSP[7] (RW)
+ *
+ * Places the USB transceiver into the suspend state.
+ *
+ * Values:
+ * - 0 - USB transceiver is not in suspend state.
+ * - 1 - USB transceiver is in suspend state.
+ */
+//@{
+#define BP_USB_USBCTRL_SUSP (7U) //!< Bit position for USB_USBCTRL_SUSP.
+#define BM_USB_USBCTRL_SUSP (0x80U) //!< Bit mask for USB_USBCTRL_SUSP.
+#define BS_USB_USBCTRL_SUSP (1U) //!< Bit field size in bits for USB_USBCTRL_SUSP.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_USBCTRL_SUSP field.
+#define BR_USB_USBCTRL_SUSP (BITBAND_ACCESS8(HW_USB_USBCTRL_ADDR, BP_USB_USBCTRL_SUSP))
+#endif
+
+//! @brief Format value for bitfield USB_USBCTRL_SUSP.
+#define BF_USB_USBCTRL_SUSP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_USBCTRL_SUSP), uint8_t) & BM_USB_USBCTRL_SUSP)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SUSP field to a new value.
+#define BW_USB_USBCTRL_SUSP(v) (BITBAND_ACCESS8(HW_USB_USBCTRL_ADDR, BP_USB_USBCTRL_SUSP) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_OBSERVE - USB OTG Observe register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_OBSERVE - USB OTG Observe register (RO)
+ *
+ * Reset value: 0x50U
+ *
+ * Provides visibility on the state of the pull-ups and pull-downs at the
+ * transceiver. Useful when interfacing to an external OTG control module via a serial
+ * interface.
+ */
+typedef union _hw_usb_observe
+{
+ uint8_t U;
+ struct _hw_usb_observe_bitfields
+ {
+ uint8_t RESERVED0 : 4; //!< [3:0]
+ uint8_t DMPD : 1; //!< [4]
+ uint8_t RESERVED1 : 1; //!< [5]
+ uint8_t DPPD : 1; //!< [6]
+ uint8_t DPPU : 1; //!< [7]
+ } B;
+} hw_usb_observe_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_OBSERVE register
+ */
+//@{
+#define HW_USB_OBSERVE_ADDR (REGS_USB_BASE + 0x104U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_OBSERVE (*(__I hw_usb_observe_t *) HW_USB_OBSERVE_ADDR)
+#define HW_USB_OBSERVE_RD() (HW_USB_OBSERVE.U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_OBSERVE bitfields
+ */
+
+/*!
+ * @name Register USB_OBSERVE, field DMPD[4] (RO)
+ *
+ * Provides observability of the D- Pulldown enable at the USB transceiver.
+ *
+ * Values:
+ * - 0 - D- pulldown disabled.
+ * - 1 - D- pulldown enabled.
+ */
+//@{
+#define BP_USB_OBSERVE_DMPD (4U) //!< Bit position for USB_OBSERVE_DMPD.
+#define BM_USB_OBSERVE_DMPD (0x10U) //!< Bit mask for USB_OBSERVE_DMPD.
+#define BS_USB_OBSERVE_DMPD (1U) //!< Bit field size in bits for USB_OBSERVE_DMPD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OBSERVE_DMPD field.
+#define BR_USB_OBSERVE_DMPD (BITBAND_ACCESS8(HW_USB_OBSERVE_ADDR, BP_USB_OBSERVE_DMPD))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OBSERVE, field DPPD[6] (RO)
+ *
+ * Provides observability of the D+ Pulldown enable at the USB transceiver.
+ *
+ * Values:
+ * - 0 - D+ pulldown disabled.
+ * - 1 - D+ pulldown enabled.
+ */
+//@{
+#define BP_USB_OBSERVE_DPPD (6U) //!< Bit position for USB_OBSERVE_DPPD.
+#define BM_USB_OBSERVE_DPPD (0x40U) //!< Bit mask for USB_OBSERVE_DPPD.
+#define BS_USB_OBSERVE_DPPD (1U) //!< Bit field size in bits for USB_OBSERVE_DPPD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OBSERVE_DPPD field.
+#define BR_USB_OBSERVE_DPPD (BITBAND_ACCESS8(HW_USB_OBSERVE_ADDR, BP_USB_OBSERVE_DPPD))
+#endif
+//@}
+
+/*!
+ * @name Register USB_OBSERVE, field DPPU[7] (RO)
+ *
+ * Provides observability of the D+ Pullup enable at the USB transceiver.
+ *
+ * Values:
+ * - 0 - D+ pullup disabled.
+ * - 1 - D+ pullup enabled.
+ */
+//@{
+#define BP_USB_OBSERVE_DPPU (7U) //!< Bit position for USB_OBSERVE_DPPU.
+#define BM_USB_OBSERVE_DPPU (0x80U) //!< Bit mask for USB_OBSERVE_DPPU.
+#define BS_USB_OBSERVE_DPPU (1U) //!< Bit field size in bits for USB_OBSERVE_DPPU.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_OBSERVE_DPPU field.
+#define BR_USB_OBSERVE_DPPU (BITBAND_ACCESS8(HW_USB_OBSERVE_ADDR, BP_USB_OBSERVE_DPPU))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_CONTROL - USB OTG Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_CONTROL - USB OTG Control register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_usb_control
+{
+ uint8_t U;
+ struct _hw_usb_control_bitfields
+ {
+ uint8_t RESERVED0 : 4; //!< [3:0]
+ uint8_t DPPULLUPNONOTG : 1; //!< [4]
+ uint8_t RESERVED1 : 3; //!< [7:5]
+ } B;
+} hw_usb_control_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_CONTROL register
+ */
+//@{
+#define HW_USB_CONTROL_ADDR (REGS_USB_BASE + 0x108U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_CONTROL (*(__IO hw_usb_control_t *) HW_USB_CONTROL_ADDR)
+#define HW_USB_CONTROL_RD() (HW_USB_CONTROL.U)
+#define HW_USB_CONTROL_WR(v) (HW_USB_CONTROL.U = (v))
+#define HW_USB_CONTROL_SET(v) (HW_USB_CONTROL_WR(HW_USB_CONTROL_RD() | (v)))
+#define HW_USB_CONTROL_CLR(v) (HW_USB_CONTROL_WR(HW_USB_CONTROL_RD() & ~(v)))
+#define HW_USB_CONTROL_TOG(v) (HW_USB_CONTROL_WR(HW_USB_CONTROL_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_CONTROL bitfields
+ */
+
+/*!
+ * @name Register USB_CONTROL, field DPPULLUPNONOTG[4] (RW)
+ *
+ * Provides control of the DP Pullup in USBOTG, if USB is configured in non-OTG
+ * device mode.
+ *
+ * Values:
+ * - 0 - DP Pullup in non-OTG device mode is not enabled.
+ * - 1 - DP Pullup in non-OTG device mode is enabled.
+ */
+//@{
+#define BP_USB_CONTROL_DPPULLUPNONOTG (4U) //!< Bit position for USB_CONTROL_DPPULLUPNONOTG.
+#define BM_USB_CONTROL_DPPULLUPNONOTG (0x10U) //!< Bit mask for USB_CONTROL_DPPULLUPNONOTG.
+#define BS_USB_CONTROL_DPPULLUPNONOTG (1U) //!< Bit field size in bits for USB_CONTROL_DPPULLUPNONOTG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CONTROL_DPPULLUPNONOTG field.
+#define BR_USB_CONTROL_DPPULLUPNONOTG (BITBAND_ACCESS8(HW_USB_CONTROL_ADDR, BP_USB_CONTROL_DPPULLUPNONOTG))
+#endif
+
+//! @brief Format value for bitfield USB_CONTROL_DPPULLUPNONOTG.
+#define BF_USB_CONTROL_DPPULLUPNONOTG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CONTROL_DPPULLUPNONOTG), uint8_t) & BM_USB_CONTROL_DPPULLUPNONOTG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DPPULLUPNONOTG field to a new value.
+#define BW_USB_CONTROL_DPPULLUPNONOTG(v) (BITBAND_ACCESS8(HW_USB_CONTROL_ADDR, BP_USB_CONTROL_DPPULLUPNONOTG) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_USBTRC0 - USB Transceiver Control register 0
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_USBTRC0 - USB Transceiver Control register 0 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Includes signals for basic operation of the on-chip USB Full Speed
+ * transceiver and configuration of the USB data connection that are not otherwise included
+ * in the USB Full Speed controller registers.
+ */
+typedef union _hw_usb_usbtrc0
+{
+ uint8_t U;
+ struct _hw_usb_usbtrc0_bitfields
+ {
+ uint8_t USB_RESUME_INT : 1; //!< [0] USB Asynchronous Interrupt
+ uint8_t SYNC_DET : 1; //!< [1] Synchronous USB Interrupt Detect
+ uint8_t USB_CLK_RECOVERY_INT : 1; //!< [2] Combined USB Clock
+ //! Recovery interrupt status
+ uint8_t RESERVED0 : 2; //!< [4:3]
+ uint8_t USBRESMEN : 1; //!< [5] Asynchronous Resume Interrupt Enable
+ uint8_t RESERVED1 : 1; //!< [6]
+ uint8_t USBRESET : 1; //!< [7] USB Reset
+ } B;
+} hw_usb_usbtrc0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_USBTRC0 register
+ */
+//@{
+#define HW_USB_USBTRC0_ADDR (REGS_USB_BASE + 0x10CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_USBTRC0 (*(__IO hw_usb_usbtrc0_t *) HW_USB_USBTRC0_ADDR)
+#define HW_USB_USBTRC0_RD() (HW_USB_USBTRC0.U)
+#define HW_USB_USBTRC0_WR(v) (HW_USB_USBTRC0.U = (v))
+#define HW_USB_USBTRC0_SET(v) (HW_USB_USBTRC0_WR(HW_USB_USBTRC0_RD() | (v)))
+#define HW_USB_USBTRC0_CLR(v) (HW_USB_USBTRC0_WR(HW_USB_USBTRC0_RD() & ~(v)))
+#define HW_USB_USBTRC0_TOG(v) (HW_USB_USBTRC0_WR(HW_USB_USBTRC0_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_USBTRC0 bitfields
+ */
+
+/*!
+ * @name Register USB_USBTRC0, field USB_RESUME_INT[0] (RO)
+ *
+ * Values:
+ * - 0 - No interrupt was generated.
+ * - 1 - Interrupt was generated because of the USB asynchronous interrupt.
+ */
+//@{
+#define BP_USB_USBTRC0_USB_RESUME_INT (0U) //!< Bit position for USB_USBTRC0_USB_RESUME_INT.
+#define BM_USB_USBTRC0_USB_RESUME_INT (0x01U) //!< Bit mask for USB_USBTRC0_USB_RESUME_INT.
+#define BS_USB_USBTRC0_USB_RESUME_INT (1U) //!< Bit field size in bits for USB_USBTRC0_USB_RESUME_INT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_USBTRC0_USB_RESUME_INT field.
+#define BR_USB_USBTRC0_USB_RESUME_INT (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR, BP_USB_USBTRC0_USB_RESUME_INT))
+#endif
+//@}
+
+/*!
+ * @name Register USB_USBTRC0, field SYNC_DET[1] (RO)
+ *
+ * Values:
+ * - 0 - Synchronous interrupt has not been detected.
+ * - 1 - Synchronous interrupt has been detected.
+ */
+//@{
+#define BP_USB_USBTRC0_SYNC_DET (1U) //!< Bit position for USB_USBTRC0_SYNC_DET.
+#define BM_USB_USBTRC0_SYNC_DET (0x02U) //!< Bit mask for USB_USBTRC0_SYNC_DET.
+#define BS_USB_USBTRC0_SYNC_DET (1U) //!< Bit field size in bits for USB_USBTRC0_SYNC_DET.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_USBTRC0_SYNC_DET field.
+#define BR_USB_USBTRC0_SYNC_DET (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR, BP_USB_USBTRC0_SYNC_DET))
+#endif
+//@}
+
+/*!
+ * @name Register USB_USBTRC0, field USB_CLK_RECOVERY_INT[2] (RO)
+ *
+ * This read-only field will be set to value high at 1'b1 when any of USB clock
+ * recovery interrupt conditions are detected and those interrupts are unmasked.
+ * For customer use the only unmasked USB clock recovery interrupt condition
+ * results from an overflow of the frequency trim setting values indicating that the
+ * frequency trim calculated is out of the adjustment range of the IRC48M output
+ * clock. To clear this bit after it has been set, Write 0xFF to register
+ * USB_CLK_RECOVER_INT_STATUS.
+ */
+//@{
+#define BP_USB_USBTRC0_USB_CLK_RECOVERY_INT (2U) //!< Bit position for USB_USBTRC0_USB_CLK_RECOVERY_INT.
+#define BM_USB_USBTRC0_USB_CLK_RECOVERY_INT (0x04U) //!< Bit mask for USB_USBTRC0_USB_CLK_RECOVERY_INT.
+#define BS_USB_USBTRC0_USB_CLK_RECOVERY_INT (1U) //!< Bit field size in bits for USB_USBTRC0_USB_CLK_RECOVERY_INT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_USBTRC0_USB_CLK_RECOVERY_INT field.
+#define BR_USB_USBTRC0_USB_CLK_RECOVERY_INT (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR, BP_USB_USBTRC0_USB_CLK_RECOVERY_INT))
+#endif
+//@}
+
+/*!
+ * @name Register USB_USBTRC0, field USBRESMEN[5] (RW)
+ *
+ * This bit, when set, allows the USB module to send an asynchronous wakeup
+ * event to the MCU upon detection of resume signaling on the USB bus. The MCU then
+ * re-enables clocks to the USB module. It is used for low-power suspend mode when
+ * USB module clocks are stopped or the USB transceiver is in Suspend mode.
+ * Async wakeup only works in device mode.
+ *
+ * Values:
+ * - 0 - USB asynchronous wakeup from suspend mode disabled.
+ * - 1 - USB asynchronous wakeup from suspend mode enabled. The asynchronous
+ * resume interrupt differs from the synchronous resume interrupt in that it
+ * asynchronously detects K-state using the unfiltered state of the D+ and D-
+ * pins. This interrupt should only be enabled when the Transceiver is
+ * suspended.
+ */
+//@{
+#define BP_USB_USBTRC0_USBRESMEN (5U) //!< Bit position for USB_USBTRC0_USBRESMEN.
+#define BM_USB_USBTRC0_USBRESMEN (0x20U) //!< Bit mask for USB_USBTRC0_USBRESMEN.
+#define BS_USB_USBTRC0_USBRESMEN (1U) //!< Bit field size in bits for USB_USBTRC0_USBRESMEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_USBTRC0_USBRESMEN field.
+#define BR_USB_USBTRC0_USBRESMEN (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR, BP_USB_USBTRC0_USBRESMEN))
+#endif
+
+//! @brief Format value for bitfield USB_USBTRC0_USBRESMEN.
+#define BF_USB_USBTRC0_USBRESMEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_USBTRC0_USBRESMEN), uint8_t) & BM_USB_USBTRC0_USBRESMEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the USBRESMEN field to a new value.
+#define BW_USB_USBTRC0_USBRESMEN(v) (BITBAND_ACCESS8(HW_USB_USBTRC0_ADDR, BP_USB_USBTRC0_USBRESMEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_USBTRC0, field USBRESET[7] (WO)
+ *
+ * Generates a hard reset to USBOTG. After this bit is set and the reset occurs,
+ * this bit is automatically cleared. This bit is always read as zero. Wait two
+ * USB clock cycles after setting this bit.
+ *
+ * Values:
+ * - 0 - Normal USB module operation.
+ * - 1 - Returns the USB module to its reset state.
+ */
+//@{
+#define BP_USB_USBTRC0_USBRESET (7U) //!< Bit position for USB_USBTRC0_USBRESET.
+#define BM_USB_USBTRC0_USBRESET (0x80U) //!< Bit mask for USB_USBTRC0_USBRESET.
+#define BS_USB_USBTRC0_USBRESET (1U) //!< Bit field size in bits for USB_USBTRC0_USBRESET.
+
+//! @brief Format value for bitfield USB_USBTRC0_USBRESET.
+#define BF_USB_USBTRC0_USBRESET(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_USBTRC0_USBRESET), uint8_t) & BM_USB_USBTRC0_USBRESET)
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_USBFRMADJUST - Frame Adjust Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_USBFRMADJUST - Frame Adjust Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+typedef union _hw_usb_usbfrmadjust
+{
+ uint8_t U;
+ struct _hw_usb_usbfrmadjust_bitfields
+ {
+ uint8_t ADJ : 8; //!< [7:0] Frame Adjustment
+ } B;
+} hw_usb_usbfrmadjust_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_USBFRMADJUST register
+ */
+//@{
+#define HW_USB_USBFRMADJUST_ADDR (REGS_USB_BASE + 0x114U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_USBFRMADJUST (*(__IO hw_usb_usbfrmadjust_t *) HW_USB_USBFRMADJUST_ADDR)
+#define HW_USB_USBFRMADJUST_RD() (HW_USB_USBFRMADJUST.U)
+#define HW_USB_USBFRMADJUST_WR(v) (HW_USB_USBFRMADJUST.U = (v))
+#define HW_USB_USBFRMADJUST_SET(v) (HW_USB_USBFRMADJUST_WR(HW_USB_USBFRMADJUST_RD() | (v)))
+#define HW_USB_USBFRMADJUST_CLR(v) (HW_USB_USBFRMADJUST_WR(HW_USB_USBFRMADJUST_RD() & ~(v)))
+#define HW_USB_USBFRMADJUST_TOG(v) (HW_USB_USBFRMADJUST_WR(HW_USB_USBFRMADJUST_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_USBFRMADJUST bitfields
+ */
+
+/*!
+ * @name Register USB_USBFRMADJUST, field ADJ[7:0] (RW)
+ *
+ * In Host mode, the frame adjustment is a twos complement number that adjusts
+ * the period of each USB frame in 12-MHz clock periods. A SOF is normally
+ * generated every 12,000 12-MHz clock cycles. The Frame Adjust Register can adjust this
+ * by -128 to +127 to compensate for inaccuracies in the USB 48-MHz clock.
+ * Changes to the ADJ bit take effect at the next start of the next frame.
+ */
+//@{
+#define BP_USB_USBFRMADJUST_ADJ (0U) //!< Bit position for USB_USBFRMADJUST_ADJ.
+#define BM_USB_USBFRMADJUST_ADJ (0xFFU) //!< Bit mask for USB_USBFRMADJUST_ADJ.
+#define BS_USB_USBFRMADJUST_ADJ (8U) //!< Bit field size in bits for USB_USBFRMADJUST_ADJ.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_USBFRMADJUST_ADJ field.
+#define BR_USB_USBFRMADJUST_ADJ (HW_USB_USBFRMADJUST.U)
+#endif
+
+//! @brief Format value for bitfield USB_USBFRMADJUST_ADJ.
+#define BF_USB_USBFRMADJUST_ADJ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_USBFRMADJUST_ADJ), uint8_t) & BM_USB_USBFRMADJUST_ADJ)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADJ field to a new value.
+#define BW_USB_USBFRMADJUST_ADJ(v) (HW_USB_USBFRMADJUST_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_CLK_RECOVER_CTRL - USB Clock recovery control
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_CLK_RECOVER_CTRL - USB Clock recovery control (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Signals in this register control the crystal-less USB clock mode in which the
+ * internal IRC48M oscillator is tuned to match the clock extracted from the
+ * incoming USB data stream. The IRC48M internal oscillator module must be enabled
+ * in register USB_CLK_RECOVER_IRC_EN for this mode.
+ */
+typedef union _hw_usb_clk_recover_ctrl
+{
+ uint8_t U;
+ struct _hw_usb_clk_recover_ctrl_bitfields
+ {
+ uint8_t RESERVED0 : 5; //!< [4:0]
+ uint8_t RESTART_IFRTRIM_EN : 1; //!< [5] Restart from IFR trim value
+ uint8_t RESET_RESUME_ROUGH_EN : 1; //!< [6] Reset/resume to rough
+ //! phase enable
+ uint8_t CLOCK_RECOVER_EN : 1; //!< [7] Crystal-less USB enable
+ } B;
+} hw_usb_clk_recover_ctrl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_CLK_RECOVER_CTRL register
+ */
+//@{
+#define HW_USB_CLK_RECOVER_CTRL_ADDR (REGS_USB_BASE + 0x140U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_CLK_RECOVER_CTRL (*(__IO hw_usb_clk_recover_ctrl_t *) HW_USB_CLK_RECOVER_CTRL_ADDR)
+#define HW_USB_CLK_RECOVER_CTRL_RD() (HW_USB_CLK_RECOVER_CTRL.U)
+#define HW_USB_CLK_RECOVER_CTRL_WR(v) (HW_USB_CLK_RECOVER_CTRL.U = (v))
+#define HW_USB_CLK_RECOVER_CTRL_SET(v) (HW_USB_CLK_RECOVER_CTRL_WR(HW_USB_CLK_RECOVER_CTRL_RD() | (v)))
+#define HW_USB_CLK_RECOVER_CTRL_CLR(v) (HW_USB_CLK_RECOVER_CTRL_WR(HW_USB_CLK_RECOVER_CTRL_RD() & ~(v)))
+#define HW_USB_CLK_RECOVER_CTRL_TOG(v) (HW_USB_CLK_RECOVER_CTRL_WR(HW_USB_CLK_RECOVER_CTRL_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_CLK_RECOVER_CTRL bitfields
+ */
+
+/*!
+ * @name Register USB_CLK_RECOVER_CTRL, field RESTART_IFRTRIM_EN[5] (RW)
+ *
+ * IRC48 has a default trim fine value whose default value is factory trimmed
+ * (the IFR trim value). Clock recover block tracks the accuracy of the clock 48Mhz
+ * and keeps updating the trim fine value accordingly
+ *
+ * Values:
+ * - 0 - Trim fine adjustment always works based on the previous updated trim
+ * fine value (default)
+ * - 1 - Trim fine restarts from the IFR trim value whenever
+ * bus_reset/bus_resume is detected or module enable is desasserted
+ */
+//@{
+#define BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (5U) //!< Bit position for USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN.
+#define BM_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (0x20U) //!< Bit mask for USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN.
+#define BS_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (1U) //!< Bit field size in bits for USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN field.
+#define BR_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR, BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN))
+#endif
+
+//! @brief Format value for bitfield USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN.
+#define BF_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN), uint8_t) & BM_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RESTART_IFRTRIM_EN field to a new value.
+#define BW_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR, BP_USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_CLK_RECOVER_CTRL, field RESET_RESUME_ROUGH_EN[6] (RW)
+ *
+ * The clock recovery block tracks the IRC48Mhz to get an accurate 48Mhz clock.
+ * It has two phases after user enables clock_recover_en bit, rough phase and
+ * tracking phase. The step to fine tune the IRC 48Mhz by adjusting the trim fine
+ * value is different during these two phases. The step in rough phase is larger
+ * than that in tracking phase. Switch back to rough stage whenever USB bus reset
+ * or bus resume occurs.
+ *
+ * Values:
+ * - 0 - Always works in tracking phase after the 1st time rough to track
+ * transition (default)
+ * - 1 - Go back to rough stage whenever bus reset or bus resume occurs
+ */
+//@{
+#define BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (6U) //!< Bit position for USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN.
+#define BM_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (0x40U) //!< Bit mask for USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN.
+#define BS_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (1U) //!< Bit field size in bits for USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN field.
+#define BR_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR, BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN))
+#endif
+
+//! @brief Format value for bitfield USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN.
+#define BF_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN), uint8_t) & BM_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RESET_RESUME_ROUGH_EN field to a new value.
+#define BW_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR, BP_USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_CLK_RECOVER_CTRL, field CLOCK_RECOVER_EN[7] (RW)
+ *
+ * This bit must be enabled if user wants to use the crystal-less USB mode for
+ * the Full Speed USB controller and transceiver. This bit should not be set for
+ * USB host mode or OTG.
+ *
+ * Values:
+ * - 0 - Disable clock recovery block (default)
+ * - 1 - Enable clock recovery block
+ */
+//@{
+#define BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (7U) //!< Bit position for USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN.
+#define BM_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (0x80U) //!< Bit mask for USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN.
+#define BS_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (1U) //!< Bit field size in bits for USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN field.
+#define BR_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR, BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN))
+#endif
+
+//! @brief Format value for bitfield USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN.
+#define BF_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN), uint8_t) & BM_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLOCK_RECOVER_EN field to a new value.
+#define BW_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_CTRL_ADDR, BP_USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register (RW)
+ *
+ * Reset value: 0x01U
+ *
+ * Controls basic operation of the on-chip IRC48M module used to produce nominal
+ * 48MHz clocks for USB crystal-less operation and other functions. See
+ * additional information about the IRC48M operation in the Clock Distribution chapter.
+ */
+typedef union _hw_usb_clk_recover_irc_en
+{
+ uint8_t U;
+ struct _hw_usb_clk_recover_irc_en_bitfields
+ {
+ uint8_t REG_EN : 1; //!< [0] IRC48M regulator enable
+ uint8_t IRC_EN : 1; //!< [1] IRC48M enable
+ uint8_t RESERVED0 : 6; //!< [7:2]
+ } B;
+} hw_usb_clk_recover_irc_en_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_CLK_RECOVER_IRC_EN register
+ */
+//@{
+#define HW_USB_CLK_RECOVER_IRC_EN_ADDR (REGS_USB_BASE + 0x144U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_CLK_RECOVER_IRC_EN (*(__IO hw_usb_clk_recover_irc_en_t *) HW_USB_CLK_RECOVER_IRC_EN_ADDR)
+#define HW_USB_CLK_RECOVER_IRC_EN_RD() (HW_USB_CLK_RECOVER_IRC_EN.U)
+#define HW_USB_CLK_RECOVER_IRC_EN_WR(v) (HW_USB_CLK_RECOVER_IRC_EN.U = (v))
+#define HW_USB_CLK_RECOVER_IRC_EN_SET(v) (HW_USB_CLK_RECOVER_IRC_EN_WR(HW_USB_CLK_RECOVER_IRC_EN_RD() | (v)))
+#define HW_USB_CLK_RECOVER_IRC_EN_CLR(v) (HW_USB_CLK_RECOVER_IRC_EN_WR(HW_USB_CLK_RECOVER_IRC_EN_RD() & ~(v)))
+#define HW_USB_CLK_RECOVER_IRC_EN_TOG(v) (HW_USB_CLK_RECOVER_IRC_EN_WR(HW_USB_CLK_RECOVER_IRC_EN_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_CLK_RECOVER_IRC_EN bitfields
+ */
+
+/*!
+ * @name Register USB_CLK_RECOVER_IRC_EN, field REG_EN[0] (RW)
+ *
+ * This bit is used to enable the local analog regulator for IRC48Mhz module.
+ * This bit must be set if user wants to use the crystal-less USB clock
+ * configuration.
+ *
+ * Values:
+ * - 0 - IRC48M local regulator is disabled
+ * - 1 - IRC48M local regulator is enabled (default)
+ */
+//@{
+#define BP_USB_CLK_RECOVER_IRC_EN_REG_EN (0U) //!< Bit position for USB_CLK_RECOVER_IRC_EN_REG_EN.
+#define BM_USB_CLK_RECOVER_IRC_EN_REG_EN (0x01U) //!< Bit mask for USB_CLK_RECOVER_IRC_EN_REG_EN.
+#define BS_USB_CLK_RECOVER_IRC_EN_REG_EN (1U) //!< Bit field size in bits for USB_CLK_RECOVER_IRC_EN_REG_EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CLK_RECOVER_IRC_EN_REG_EN field.
+#define BR_USB_CLK_RECOVER_IRC_EN_REG_EN (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR, BP_USB_CLK_RECOVER_IRC_EN_REG_EN))
+#endif
+
+//! @brief Format value for bitfield USB_CLK_RECOVER_IRC_EN_REG_EN.
+#define BF_USB_CLK_RECOVER_IRC_EN_REG_EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CLK_RECOVER_IRC_EN_REG_EN), uint8_t) & BM_USB_CLK_RECOVER_IRC_EN_REG_EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the REG_EN field to a new value.
+#define BW_USB_CLK_RECOVER_IRC_EN_REG_EN(v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR, BP_USB_CLK_RECOVER_IRC_EN_REG_EN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USB_CLK_RECOVER_IRC_EN, field IRC_EN[1] (RW)
+ *
+ * This bit is used to enable the on-chip IRC48Mhz module to generate clocks for
+ * crystal-less USB. It can only be used for FS USB device mode operation. This
+ * bit must be set before using the crystal-less USB clock configuration.
+ *
+ * Values:
+ * - 0 - Disable the IRC48M module (default)
+ * - 1 - Enable the IRC48M module
+ */
+//@{
+#define BP_USB_CLK_RECOVER_IRC_EN_IRC_EN (1U) //!< Bit position for USB_CLK_RECOVER_IRC_EN_IRC_EN.
+#define BM_USB_CLK_RECOVER_IRC_EN_IRC_EN (0x02U) //!< Bit mask for USB_CLK_RECOVER_IRC_EN_IRC_EN.
+#define BS_USB_CLK_RECOVER_IRC_EN_IRC_EN (1U) //!< Bit field size in bits for USB_CLK_RECOVER_IRC_EN_IRC_EN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CLK_RECOVER_IRC_EN_IRC_EN field.
+#define BR_USB_CLK_RECOVER_IRC_EN_IRC_EN (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR, BP_USB_CLK_RECOVER_IRC_EN_IRC_EN))
+#endif
+
+//! @brief Format value for bitfield USB_CLK_RECOVER_IRC_EN_IRC_EN.
+#define BF_USB_CLK_RECOVER_IRC_EN_IRC_EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CLK_RECOVER_IRC_EN_IRC_EN), uint8_t) & BM_USB_CLK_RECOVER_IRC_EN_IRC_EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IRC_EN field to a new value.
+#define BW_USB_CLK_RECOVER_IRC_EN_IRC_EN(v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_IRC_EN_ADDR, BP_USB_CLK_RECOVER_IRC_EN_IRC_EN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * A Write operation with value high at 1'b1 on any combination of individual
+ * bits will clear those bits.
+ */
+typedef union _hw_usb_clk_recover_int_status
+{
+ uint8_t U;
+ struct _hw_usb_clk_recover_int_status_bitfields
+ {
+ uint8_t RESERVED0 : 4; //!< [3:0]
+ uint8_t OVF_ERROR : 1; //!< [4]
+ uint8_t RESERVED1 : 3; //!< [7:5]
+ } B;
+} hw_usb_clk_recover_int_status_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USB_CLK_RECOVER_INT_STATUS register
+ */
+//@{
+#define HW_USB_CLK_RECOVER_INT_STATUS_ADDR (REGS_USB_BASE + 0x15CU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USB_CLK_RECOVER_INT_STATUS (*(__IO hw_usb_clk_recover_int_status_t *) HW_USB_CLK_RECOVER_INT_STATUS_ADDR)
+#define HW_USB_CLK_RECOVER_INT_STATUS_RD() (HW_USB_CLK_RECOVER_INT_STATUS.U)
+#define HW_USB_CLK_RECOVER_INT_STATUS_WR(v) (HW_USB_CLK_RECOVER_INT_STATUS.U = (v))
+#define HW_USB_CLK_RECOVER_INT_STATUS_SET(v) (HW_USB_CLK_RECOVER_INT_STATUS_WR(HW_USB_CLK_RECOVER_INT_STATUS_RD() | (v)))
+#define HW_USB_CLK_RECOVER_INT_STATUS_CLR(v) (HW_USB_CLK_RECOVER_INT_STATUS_WR(HW_USB_CLK_RECOVER_INT_STATUS_RD() & ~(v)))
+#define HW_USB_CLK_RECOVER_INT_STATUS_TOG(v) (HW_USB_CLK_RECOVER_INT_STATUS_WR(HW_USB_CLK_RECOVER_INT_STATUS_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USB_CLK_RECOVER_INT_STATUS bitfields
+ */
+
+/*!
+ * @name Register USB_CLK_RECOVER_INT_STATUS, field OVF_ERROR[4] (W1C)
+ *
+ * Indicates that the USB clock recovery algorithm has detected that the
+ * frequency trim adjustment needed for the IRC48M output clock is outside the available
+ * TRIM_FINE adjustment range for the IRC48M module.
+ *
+ * Values:
+ * - 0 - No interrupt is reported
+ * - 1 - Unmasked interrupt has been generated
+ */
+//@{
+#define BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR (4U) //!< Bit position for USB_CLK_RECOVER_INT_STATUS_OVF_ERROR.
+#define BM_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR (0x10U) //!< Bit mask for USB_CLK_RECOVER_INT_STATUS_OVF_ERROR.
+#define BS_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR (1U) //!< Bit field size in bits for USB_CLK_RECOVER_INT_STATUS_OVF_ERROR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USB_CLK_RECOVER_INT_STATUS_OVF_ERROR field.
+#define BR_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_INT_STATUS_ADDR, BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR))
+#endif
+
+//! @brief Format value for bitfield USB_CLK_RECOVER_INT_STATUS_OVF_ERROR.
+#define BF_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR), uint8_t) & BM_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OVF_ERROR field to a new value.
+#define BW_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(v) (BITBAND_ACCESS8(HW_USB_CLK_RECOVER_INT_STATUS_ADDR, BP_USB_CLK_RECOVER_INT_STATUS_OVF_ERROR) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_usb_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All USB module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_usb
+{
+ __I hw_usb_perid_t PERID; //!< [0x0] Peripheral ID register
+ uint8_t _reserved0[3];
+ __I hw_usb_idcomp_t IDCOMP; //!< [0x4] Peripheral ID Complement register
+ uint8_t _reserved1[3];
+ __I hw_usb_rev_t REV; //!< [0x8] Peripheral Revision register
+ uint8_t _reserved2[3];
+ __I hw_usb_addinfo_t ADDINFO; //!< [0xC] Peripheral Additional Info register
+ uint8_t _reserved3[3];
+ __IO hw_usb_otgistat_t OTGISTAT; //!< [0x10] OTG Interrupt Status register
+ uint8_t _reserved4[3];
+ __IO hw_usb_otgicr_t OTGICR; //!< [0x14] OTG Interrupt Control register
+ uint8_t _reserved5[3];
+ __IO hw_usb_otgstat_t OTGSTAT; //!< [0x18] OTG Status register
+ uint8_t _reserved6[3];
+ __IO hw_usb_otgctl_t OTGCTL; //!< [0x1C] OTG Control register
+ uint8_t _reserved7[99];
+ __IO hw_usb_istat_t ISTAT; //!< [0x80] Interrupt Status register
+ uint8_t _reserved8[3];
+ __IO hw_usb_inten_t INTEN; //!< [0x84] Interrupt Enable register
+ uint8_t _reserved9[3];
+ __IO hw_usb_errstat_t ERRSTAT; //!< [0x88] Error Interrupt Status register
+ uint8_t _reserved10[3];
+ __IO hw_usb_erren_t ERREN; //!< [0x8C] Error Interrupt Enable register
+ uint8_t _reserved11[3];
+ __I hw_usb_stat_t STAT; //!< [0x90] Status register
+ uint8_t _reserved12[3];
+ __IO hw_usb_ctl_t CTL; //!< [0x94] Control register
+ uint8_t _reserved13[3];
+ __IO hw_usb_addr_t ADDR; //!< [0x98] Address register
+ uint8_t _reserved14[3];
+ __IO hw_usb_bdtpage1_t BDTPAGE1; //!< [0x9C] BDT Page register 1
+ uint8_t _reserved15[3];
+ __IO hw_usb_frmnuml_t FRMNUML; //!< [0xA0] Frame Number register Low
+ uint8_t _reserved16[3];
+ __IO hw_usb_frmnumh_t FRMNUMH; //!< [0xA4] Frame Number register High
+ uint8_t _reserved17[3];
+ __IO hw_usb_token_t TOKEN; //!< [0xA8] Token register
+ uint8_t _reserved18[3];
+ __IO hw_usb_softhld_t SOFTHLD; //!< [0xAC] SOF Threshold register
+ uint8_t _reserved19[3];
+ __IO hw_usb_bdtpage2_t BDTPAGE2; //!< [0xB0] BDT Page Register 2
+ uint8_t _reserved20[3];
+ __IO hw_usb_bdtpage3_t BDTPAGE3; //!< [0xB4] BDT Page Register 3
+ uint8_t _reserved21[11];
+ struct {
+ __IO hw_usb_endptn_t ENDPTn; //!< [0xC0] Endpoint Control register
+ uint8_t _reserved0[3];
+ } ENDPOINT[16];
+ __IO hw_usb_usbctrl_t USBCTRL; //!< [0x100] USB Control register
+ uint8_t _reserved22[3];
+ __I hw_usb_observe_t OBSERVE; //!< [0x104] USB OTG Observe register
+ uint8_t _reserved23[3];
+ __IO hw_usb_control_t CONTROL; //!< [0x108] USB OTG Control register
+ uint8_t _reserved24[3];
+ __IO hw_usb_usbtrc0_t USBTRC0; //!< [0x10C] USB Transceiver Control register 0
+ uint8_t _reserved25[7];
+ __IO hw_usb_usbfrmadjust_t USBFRMADJUST; //!< [0x114] Frame Adjust Register
+ uint8_t _reserved26[43];
+ __IO hw_usb_clk_recover_ctrl_t CLK_RECOVER_CTRL; //!< [0x140] USB Clock recovery control
+ uint8_t _reserved27[3];
+ __IO hw_usb_clk_recover_irc_en_t CLK_RECOVER_IRC_EN; //!< [0x144] IRC48M oscillator enable register
+ uint8_t _reserved28[23];
+ __IO hw_usb_clk_recover_int_status_t CLK_RECOVER_INT_STATUS; //!< [0x15C] Clock recovery separated interrupt status
+} hw_usb_t;
+#pragma pack()
+
+//! @brief Macro to access all USB registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_USB</code>.
+#define HW_USB (*(hw_usb_t *) REGS_USB_BASE)
+#endif
+
+#endif // __HW_USB_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_usbdcd.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,957 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_USBDCD_REGISTERS_H__
+#define __HW_USBDCD_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 USBDCD
+ *
+ * USB Device Charger Detection module
+ *
+ * Registers defined in this header file:
+ * - HW_USBDCD_CONTROL - Control register
+ * - HW_USBDCD_CLOCK - Clock register
+ * - HW_USBDCD_STATUS - Status register
+ * - HW_USBDCD_TIMER0 - TIMER0 register
+ * - HW_USBDCD_TIMER1 - TIMER1 register
+ * - HW_USBDCD_TIMER2_BC11 - TIMER2_BC11 register
+ * - HW_USBDCD_TIMER2_BC12 - TIMER2_BC12 register
+ *
+ * - hw_usbdcd_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_USBDCD_BASE
+#define HW_USBDCD_INSTANCE_COUNT (1U) //!< Number of instances of the USBDCD module.
+#define HW_USBDCD0 (0U) //!< Instance number for USBDCD.
+#define REGS_USBDCD0_BASE (0x40035000U) //!< Base address for USBDCD.
+
+//! @brief Table of base addresses for USBDCD instances.
+static const uint32_t __g_regs_USBDCD_base_addresses[] = {
+ REGS_USBDCD0_BASE,
+ };
+
+//! @brief Get the base address of USBDCD by instance number.
+//! @param x USBDCD instance number, from 0 through 0.
+#define REGS_USBDCD_BASE(x) (__g_regs_USBDCD_base_addresses[(x)])
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of USBDCD.
+#define REGS_USBDCD_INSTANCE(b) ((b) == REGS_USBDCD0_BASE ? HW_USBDCD0 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USBDCD_CONTROL - Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USBDCD_CONTROL - Control register (RW)
+ *
+ * Reset value: 0x00010000U
+ *
+ * Contains the control and interrupt bit fields.
+ */
+typedef union _hw_usbdcd_control
+{
+ uint32_t U;
+ struct _hw_usbdcd_control_bitfields
+ {
+ uint32_t IACK : 1; //!< [0] Interrupt Acknowledge
+ uint32_t RESERVED0 : 7; //!< [7:1]
+ uint32_t IF : 1; //!< [8] Interrupt Flag
+ uint32_t RESERVED1 : 7; //!< [15:9]
+ uint32_t IE : 1; //!< [16] Interrupt Enable
+ uint32_t BC12 : 1; //!< [17]
+ uint32_t RESERVED2 : 6; //!< [23:18]
+ uint32_t START : 1; //!< [24] Start Change Detection Sequence
+ uint32_t SR : 1; //!< [25] Software Reset
+ uint32_t RESERVED3 : 6; //!< [31:26]
+ } B;
+} hw_usbdcd_control_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USBDCD_CONTROL register
+ */
+//@{
+#define HW_USBDCD_CONTROL_ADDR(x) (REGS_USBDCD_BASE(x) + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USBDCD_CONTROL(x) (*(__IO hw_usbdcd_control_t *) HW_USBDCD_CONTROL_ADDR(x))
+#define HW_USBDCD_CONTROL_RD(x) (HW_USBDCD_CONTROL(x).U)
+#define HW_USBDCD_CONTROL_WR(x, v) (HW_USBDCD_CONTROL(x).U = (v))
+#define HW_USBDCD_CONTROL_SET(x, v) (HW_USBDCD_CONTROL_WR(x, HW_USBDCD_CONTROL_RD(x) | (v)))
+#define HW_USBDCD_CONTROL_CLR(x, v) (HW_USBDCD_CONTROL_WR(x, HW_USBDCD_CONTROL_RD(x) & ~(v)))
+#define HW_USBDCD_CONTROL_TOG(x, v) (HW_USBDCD_CONTROL_WR(x, HW_USBDCD_CONTROL_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USBDCD_CONTROL bitfields
+ */
+
+/*!
+ * @name Register USBDCD_CONTROL, field IACK[0] (WORZ)
+ *
+ * Determines whether the interrupt is cleared.
+ *
+ * Values:
+ * - 0 - Do not clear the interrupt.
+ * - 1 - Clear the IF bit (interrupt flag).
+ */
+//@{
+#define BP_USBDCD_CONTROL_IACK (0U) //!< Bit position for USBDCD_CONTROL_IACK.
+#define BM_USBDCD_CONTROL_IACK (0x00000001U) //!< Bit mask for USBDCD_CONTROL_IACK.
+#define BS_USBDCD_CONTROL_IACK (1U) //!< Bit field size in bits for USBDCD_CONTROL_IACK.
+
+//! @brief Format value for bitfield USBDCD_CONTROL_IACK.
+#define BF_USBDCD_CONTROL_IACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CONTROL_IACK), uint32_t) & BM_USBDCD_CONTROL_IACK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IACK field to a new value.
+#define BW_USBDCD_CONTROL_IACK(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IACK) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USBDCD_CONTROL, field IF[8] (RO)
+ *
+ * Determines whether an interrupt is pending.
+ *
+ * Values:
+ * - 0 - No interrupt is pending.
+ * - 1 - An interrupt is pending.
+ */
+//@{
+#define BP_USBDCD_CONTROL_IF (8U) //!< Bit position for USBDCD_CONTROL_IF.
+#define BM_USBDCD_CONTROL_IF (0x00000100U) //!< Bit mask for USBDCD_CONTROL_IF.
+#define BS_USBDCD_CONTROL_IF (1U) //!< Bit field size in bits for USBDCD_CONTROL_IF.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_CONTROL_IF field.
+#define BR_USBDCD_CONTROL_IF(x) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IF))
+#endif
+//@}
+
+/*!
+ * @name Register USBDCD_CONTROL, field IE[16] (RW)
+ *
+ * Enables/disables interrupts to the system.
+ *
+ * Values:
+ * - 0 - Disable interrupts to the system.
+ * - 1 - Enable interrupts to the system.
+ */
+//@{
+#define BP_USBDCD_CONTROL_IE (16U) //!< Bit position for USBDCD_CONTROL_IE.
+#define BM_USBDCD_CONTROL_IE (0x00010000U) //!< Bit mask for USBDCD_CONTROL_IE.
+#define BS_USBDCD_CONTROL_IE (1U) //!< Bit field size in bits for USBDCD_CONTROL_IE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_CONTROL_IE field.
+#define BR_USBDCD_CONTROL_IE(x) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IE))
+#endif
+
+//! @brief Format value for bitfield USBDCD_CONTROL_IE.
+#define BF_USBDCD_CONTROL_IE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CONTROL_IE), uint32_t) & BM_USBDCD_CONTROL_IE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IE field to a new value.
+#define BW_USBDCD_CONTROL_IE(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USBDCD_CONTROL, field BC12[17] (RW)
+ *
+ * BC1.2 compatibility. This bit cannot be changed after start detection.
+ *
+ * Values:
+ * - 0 - Compatible with BC1.1 (default)
+ * - 1 - Compatible with BC1.2
+ */
+//@{
+#define BP_USBDCD_CONTROL_BC12 (17U) //!< Bit position for USBDCD_CONTROL_BC12.
+#define BM_USBDCD_CONTROL_BC12 (0x00020000U) //!< Bit mask for USBDCD_CONTROL_BC12.
+#define BS_USBDCD_CONTROL_BC12 (1U) //!< Bit field size in bits for USBDCD_CONTROL_BC12.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_CONTROL_BC12 field.
+#define BR_USBDCD_CONTROL_BC12(x) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_BC12))
+#endif
+
+//! @brief Format value for bitfield USBDCD_CONTROL_BC12.
+#define BF_USBDCD_CONTROL_BC12(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CONTROL_BC12), uint32_t) & BM_USBDCD_CONTROL_BC12)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BC12 field to a new value.
+#define BW_USBDCD_CONTROL_BC12(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_BC12) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USBDCD_CONTROL, field START[24] (WORZ)
+ *
+ * Determines whether the charger detection sequence is initiated.
+ *
+ * Values:
+ * - 0 - Do not start the sequence. Writes of this value have no effect.
+ * - 1 - Initiate the charger detection sequence. If the sequence is already
+ * running, writes of this value have no effect.
+ */
+//@{
+#define BP_USBDCD_CONTROL_START (24U) //!< Bit position for USBDCD_CONTROL_START.
+#define BM_USBDCD_CONTROL_START (0x01000000U) //!< Bit mask for USBDCD_CONTROL_START.
+#define BS_USBDCD_CONTROL_START (1U) //!< Bit field size in bits for USBDCD_CONTROL_START.
+
+//! @brief Format value for bitfield USBDCD_CONTROL_START.
+#define BF_USBDCD_CONTROL_START(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CONTROL_START), uint32_t) & BM_USBDCD_CONTROL_START)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the START field to a new value.
+#define BW_USBDCD_CONTROL_START(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_START) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USBDCD_CONTROL, field SR[25] (WORZ)
+ *
+ * Determines whether a software reset is performed.
+ *
+ * Values:
+ * - 0 - Do not perform a software reset.
+ * - 1 - Perform a software reset.
+ */
+//@{
+#define BP_USBDCD_CONTROL_SR (25U) //!< Bit position for USBDCD_CONTROL_SR.
+#define BM_USBDCD_CONTROL_SR (0x02000000U) //!< Bit mask for USBDCD_CONTROL_SR.
+#define BS_USBDCD_CONTROL_SR (1U) //!< Bit field size in bits for USBDCD_CONTROL_SR.
+
+//! @brief Format value for bitfield USBDCD_CONTROL_SR.
+#define BF_USBDCD_CONTROL_SR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CONTROL_SR), uint32_t) & BM_USBDCD_CONTROL_SR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SR field to a new value.
+#define BW_USBDCD_CONTROL_SR(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_SR) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USBDCD_CLOCK - Clock register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USBDCD_CLOCK - Clock register (RW)
+ *
+ * Reset value: 0x000000C1U
+ */
+typedef union _hw_usbdcd_clock
+{
+ uint32_t U;
+ struct _hw_usbdcd_clock_bitfields
+ {
+ uint32_t CLOCK_UNIT : 1; //!< [0] Unit of Measurement Encoding for
+ //! Clock Speed
+ uint32_t RESERVED0 : 1; //!< [1]
+ uint32_t CLOCK_SPEED : 10; //!< [11:2] Numerical Value of Clock Speed
+ //! in Binary
+ uint32_t RESERVED1 : 20; //!< [31:12]
+ } B;
+} hw_usbdcd_clock_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USBDCD_CLOCK register
+ */
+//@{
+#define HW_USBDCD_CLOCK_ADDR(x) (REGS_USBDCD_BASE(x) + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USBDCD_CLOCK(x) (*(__IO hw_usbdcd_clock_t *) HW_USBDCD_CLOCK_ADDR(x))
+#define HW_USBDCD_CLOCK_RD(x) (HW_USBDCD_CLOCK(x).U)
+#define HW_USBDCD_CLOCK_WR(x, v) (HW_USBDCD_CLOCK(x).U = (v))
+#define HW_USBDCD_CLOCK_SET(x, v) (HW_USBDCD_CLOCK_WR(x, HW_USBDCD_CLOCK_RD(x) | (v)))
+#define HW_USBDCD_CLOCK_CLR(x, v) (HW_USBDCD_CLOCK_WR(x, HW_USBDCD_CLOCK_RD(x) & ~(v)))
+#define HW_USBDCD_CLOCK_TOG(x, v) (HW_USBDCD_CLOCK_WR(x, HW_USBDCD_CLOCK_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USBDCD_CLOCK bitfields
+ */
+
+/*!
+ * @name Register USBDCD_CLOCK, field CLOCK_UNIT[0] (RW)
+ *
+ * Specifies the unit of measure for the clock speed.
+ *
+ * Values:
+ * - 0 - kHz Speed (between 1 kHz and 1023 kHz)
+ * - 1 - MHz Speed (between 1 MHz and 1023 MHz)
+ */
+//@{
+#define BP_USBDCD_CLOCK_CLOCK_UNIT (0U) //!< Bit position for USBDCD_CLOCK_CLOCK_UNIT.
+#define BM_USBDCD_CLOCK_CLOCK_UNIT (0x00000001U) //!< Bit mask for USBDCD_CLOCK_CLOCK_UNIT.
+#define BS_USBDCD_CLOCK_CLOCK_UNIT (1U) //!< Bit field size in bits for USBDCD_CLOCK_CLOCK_UNIT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_CLOCK_CLOCK_UNIT field.
+#define BR_USBDCD_CLOCK_CLOCK_UNIT(x) (BITBAND_ACCESS32(HW_USBDCD_CLOCK_ADDR(x), BP_USBDCD_CLOCK_CLOCK_UNIT))
+#endif
+
+//! @brief Format value for bitfield USBDCD_CLOCK_CLOCK_UNIT.
+#define BF_USBDCD_CLOCK_CLOCK_UNIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CLOCK_CLOCK_UNIT), uint32_t) & BM_USBDCD_CLOCK_CLOCK_UNIT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLOCK_UNIT field to a new value.
+#define BW_USBDCD_CLOCK_CLOCK_UNIT(x, v) (BITBAND_ACCESS32(HW_USBDCD_CLOCK_ADDR(x), BP_USBDCD_CLOCK_CLOCK_UNIT) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register USBDCD_CLOCK, field CLOCK_SPEED[11:2] (RW)
+ *
+ * The unit of measure is programmed in CLOCK_UNIT. The valid range is from 1 to
+ * 1023 when clock unit is MHz and 4 to 1023 when clock unit is kHz. Examples
+ * with CLOCK_UNIT = 1: For 48 MHz: 0b00_0011_0000 (48) (Default) For 24 MHz:
+ * 0b00_0001_1000 (24) Examples with CLOCK_UNIT = 0: For 100 kHz: 0b00_0110_0100 (100)
+ * For 500 kHz: 0b01_1111_0100 (500)
+ */
+//@{
+#define BP_USBDCD_CLOCK_CLOCK_SPEED (2U) //!< Bit position for USBDCD_CLOCK_CLOCK_SPEED.
+#define BM_USBDCD_CLOCK_CLOCK_SPEED (0x00000FFCU) //!< Bit mask for USBDCD_CLOCK_CLOCK_SPEED.
+#define BS_USBDCD_CLOCK_CLOCK_SPEED (10U) //!< Bit field size in bits for USBDCD_CLOCK_CLOCK_SPEED.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_CLOCK_CLOCK_SPEED field.
+#define BR_USBDCD_CLOCK_CLOCK_SPEED(x) (HW_USBDCD_CLOCK(x).B.CLOCK_SPEED)
+#endif
+
+//! @brief Format value for bitfield USBDCD_CLOCK_CLOCK_SPEED.
+#define BF_USBDCD_CLOCK_CLOCK_SPEED(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_CLOCK_CLOCK_SPEED), uint32_t) & BM_USBDCD_CLOCK_CLOCK_SPEED)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLOCK_SPEED field to a new value.
+#define BW_USBDCD_CLOCK_CLOCK_SPEED(x, v) (HW_USBDCD_CLOCK_WR(x, (HW_USBDCD_CLOCK_RD(x) & ~BM_USBDCD_CLOCK_CLOCK_SPEED) | BF_USBDCD_CLOCK_CLOCK_SPEED(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USBDCD_STATUS - Status register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USBDCD_STATUS - Status register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Provides the current state of the module for system software monitoring.
+ */
+typedef union _hw_usbdcd_status
+{
+ uint32_t U;
+ struct _hw_usbdcd_status_bitfields
+ {
+ uint32_t RESERVED0 : 16; //!< [15:0]
+ uint32_t SEQ_RES : 2; //!< [17:16] Charger Detection Sequence Results
+ uint32_t SEQ_STAT : 2; //!< [19:18] Charger Detection Sequence Status
+ uint32_t ERR : 1; //!< [20] Error Flag
+ uint32_t TO : 1; //!< [21] Timeout Flag
+ uint32_t ACTIVE : 1; //!< [22] Active Status Indicator
+ uint32_t RESERVED1 : 9; //!< [31:23]
+ } B;
+} hw_usbdcd_status_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USBDCD_STATUS register
+ */
+//@{
+#define HW_USBDCD_STATUS_ADDR(x) (REGS_USBDCD_BASE(x) + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USBDCD_STATUS(x) (*(__I hw_usbdcd_status_t *) HW_USBDCD_STATUS_ADDR(x))
+#define HW_USBDCD_STATUS_RD(x) (HW_USBDCD_STATUS(x).U)
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USBDCD_STATUS bitfields
+ */
+
+/*!
+ * @name Register USBDCD_STATUS, field SEQ_RES[17:16] (RO)
+ *
+ * Reports how the charger detection is attached.
+ *
+ * Values:
+ * - 00 - No results to report.
+ * - 01 - Attached to a standard host. Must comply with USB 2.0 by drawing only
+ * 2.5 mA (max) until connected.
+ * - 10 - Attached to a charging port. The exact meaning depends on bit 18: 0:
+ * Attached to either a charging host or a dedicated charger. The charger type
+ * detection has not completed. 1: Attached to a charging host. The charger
+ * type detection has completed.
+ * - 11 - Attached to a dedicated charger.
+ */
+//@{
+#define BP_USBDCD_STATUS_SEQ_RES (16U) //!< Bit position for USBDCD_STATUS_SEQ_RES.
+#define BM_USBDCD_STATUS_SEQ_RES (0x00030000U) //!< Bit mask for USBDCD_STATUS_SEQ_RES.
+#define BS_USBDCD_STATUS_SEQ_RES (2U) //!< Bit field size in bits for USBDCD_STATUS_SEQ_RES.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_STATUS_SEQ_RES field.
+#define BR_USBDCD_STATUS_SEQ_RES(x) (HW_USBDCD_STATUS(x).B.SEQ_RES)
+#endif
+//@}
+
+/*!
+ * @name Register USBDCD_STATUS, field SEQ_STAT[19:18] (RO)
+ *
+ * Indicates the status of the charger detection sequence.
+ *
+ * Values:
+ * - 00 - The module is either not enabled, or the module is enabled but the
+ * data pins have not yet been detected.
+ * - 01 - Data pin contact detection is complete.
+ * - 10 - Charging port detection is complete.
+ * - 11 - Charger type detection is complete.
+ */
+//@{
+#define BP_USBDCD_STATUS_SEQ_STAT (18U) //!< Bit position for USBDCD_STATUS_SEQ_STAT.
+#define BM_USBDCD_STATUS_SEQ_STAT (0x000C0000U) //!< Bit mask for USBDCD_STATUS_SEQ_STAT.
+#define BS_USBDCD_STATUS_SEQ_STAT (2U) //!< Bit field size in bits for USBDCD_STATUS_SEQ_STAT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_STATUS_SEQ_STAT field.
+#define BR_USBDCD_STATUS_SEQ_STAT(x) (HW_USBDCD_STATUS(x).B.SEQ_STAT)
+#endif
+//@}
+
+/*!
+ * @name Register USBDCD_STATUS, field ERR[20] (RO)
+ *
+ * Indicates whether there is an error in the detection sequence.
+ *
+ * Values:
+ * - 0 - No sequence errors.
+ * - 1 - Error in the detection sequence. See the SEQ_STAT field to determine
+ * the phase in which the error occurred.
+ */
+//@{
+#define BP_USBDCD_STATUS_ERR (20U) //!< Bit position for USBDCD_STATUS_ERR.
+#define BM_USBDCD_STATUS_ERR (0x00100000U) //!< Bit mask for USBDCD_STATUS_ERR.
+#define BS_USBDCD_STATUS_ERR (1U) //!< Bit field size in bits for USBDCD_STATUS_ERR.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_STATUS_ERR field.
+#define BR_USBDCD_STATUS_ERR(x) (BITBAND_ACCESS32(HW_USBDCD_STATUS_ADDR(x), BP_USBDCD_STATUS_ERR))
+#endif
+//@}
+
+/*!
+ * @name Register USBDCD_STATUS, field TO[21] (RO)
+ *
+ * Indicates whether the detection sequence has passed the timeout threshhold.
+ *
+ * Values:
+ * - 0 - The detection sequence has not been running for over 1 s.
+ * - 1 - It has been over 1 s since the data pin contact was detected and
+ * debounced.
+ */
+//@{
+#define BP_USBDCD_STATUS_TO (21U) //!< Bit position for USBDCD_STATUS_TO.
+#define BM_USBDCD_STATUS_TO (0x00200000U) //!< Bit mask for USBDCD_STATUS_TO.
+#define BS_USBDCD_STATUS_TO (1U) //!< Bit field size in bits for USBDCD_STATUS_TO.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_STATUS_TO field.
+#define BR_USBDCD_STATUS_TO(x) (BITBAND_ACCESS32(HW_USBDCD_STATUS_ADDR(x), BP_USBDCD_STATUS_TO))
+#endif
+//@}
+
+/*!
+ * @name Register USBDCD_STATUS, field ACTIVE[22] (RO)
+ *
+ * Indicates whether the sequence is running.
+ *
+ * Values:
+ * - 0 - The sequence is not running.
+ * - 1 - The sequence is running.
+ */
+//@{
+#define BP_USBDCD_STATUS_ACTIVE (22U) //!< Bit position for USBDCD_STATUS_ACTIVE.
+#define BM_USBDCD_STATUS_ACTIVE (0x00400000U) //!< Bit mask for USBDCD_STATUS_ACTIVE.
+#define BS_USBDCD_STATUS_ACTIVE (1U) //!< Bit field size in bits for USBDCD_STATUS_ACTIVE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_STATUS_ACTIVE field.
+#define BR_USBDCD_STATUS_ACTIVE(x) (BITBAND_ACCESS32(HW_USBDCD_STATUS_ADDR(x), BP_USBDCD_STATUS_ACTIVE))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USBDCD_TIMER0 - TIMER0 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USBDCD_TIMER0 - TIMER0 register (RW)
+ *
+ * Reset value: 0x00100000U
+ *
+ * TIMER0 has an TSEQ_INIT field that represents the system latency in ms.
+ * Latency is measured from the time when VBUS goes active until the time system
+ * software initiates charger detection sequence in USBDCD module. When software sets
+ * the CONTROL[START] bit, the Unit Connection Timer (TUNITCON) is initialized
+ * with the value of TSEQ_INIT. Valid values are 0-1023, however the USB Battery
+ * Charging Specification requires the entire sequence, including TSEQ_INIT, to be
+ * completed in 1s or less.
+ */
+typedef union _hw_usbdcd_timer0
+{
+ uint32_t U;
+ struct _hw_usbdcd_timer0_bitfields
+ {
+ uint32_t TUNITCON : 12; //!< [11:0] Unit Connection Timer Elapse (in
+ //! ms)
+ uint32_t RESERVED0 : 4; //!< [15:12]
+ uint32_t TSEQ_INIT : 10; //!< [25:16] Sequence Initiation Time
+ uint32_t RESERVED1 : 6; //!< [31:26]
+ } B;
+} hw_usbdcd_timer0_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER0 register
+ */
+//@{
+#define HW_USBDCD_TIMER0_ADDR(x) (REGS_USBDCD_BASE(x) + 0x10U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USBDCD_TIMER0(x) (*(__IO hw_usbdcd_timer0_t *) HW_USBDCD_TIMER0_ADDR(x))
+#define HW_USBDCD_TIMER0_RD(x) (HW_USBDCD_TIMER0(x).U)
+#define HW_USBDCD_TIMER0_WR(x, v) (HW_USBDCD_TIMER0(x).U = (v))
+#define HW_USBDCD_TIMER0_SET(x, v) (HW_USBDCD_TIMER0_WR(x, HW_USBDCD_TIMER0_RD(x) | (v)))
+#define HW_USBDCD_TIMER0_CLR(x, v) (HW_USBDCD_TIMER0_WR(x, HW_USBDCD_TIMER0_RD(x) & ~(v)))
+#define HW_USBDCD_TIMER0_TOG(x, v) (HW_USBDCD_TIMER0_WR(x, HW_USBDCD_TIMER0_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USBDCD_TIMER0 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER0, field TUNITCON[11:0] (RO)
+ *
+ * Displays the amount of elapsed time since the event of setting the START bit
+ * plus the value of TSEQ_INIT. The timer is automatically initialized with the
+ * value of TSEQ_INIT before starting to count. This timer enables compliance with
+ * the maximum time allowed to connect T UNIT_CON under the USB Battery Charging
+ * Specification. If the timer reaches the one second limit, the module triggers
+ * an interrupt and sets the error flag STATUS[ERR]. The timer continues
+ * counting throughout the charger detection sequence, even when control has been passed
+ * to software. As long as the module is active, the timer continues to count
+ * until it reaches the maximum value of 0xFFF (4095 ms). The timer does not
+ * rollover to zero. A software reset clears the timer.
+ */
+//@{
+#define BP_USBDCD_TIMER0_TUNITCON (0U) //!< Bit position for USBDCD_TIMER0_TUNITCON.
+#define BM_USBDCD_TIMER0_TUNITCON (0x00000FFFU) //!< Bit mask for USBDCD_TIMER0_TUNITCON.
+#define BS_USBDCD_TIMER0_TUNITCON (12U) //!< Bit field size in bits for USBDCD_TIMER0_TUNITCON.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_TIMER0_TUNITCON field.
+#define BR_USBDCD_TIMER0_TUNITCON(x) (HW_USBDCD_TIMER0(x).B.TUNITCON)
+#endif
+//@}
+
+/*!
+ * @name Register USBDCD_TIMER0, field TSEQ_INIT[25:16] (RW)
+ *
+ * TSEQ_INIT represents the system latency (in ms) measured from the time VBUS
+ * goes active to the time system software initiates the charger detection
+ * sequence in the USBDCD module. When software sets the CONTROL[START] bit, the Unit
+ * Connection Timer (TUNITCON) is initialized with the value of TSEQ_INIT. Valid
+ * values are 0-1023, but the USB Battery Charging Specification requires the
+ * entire sequence, including TSEQ_INIT, to be completed in 1s or less.
+ */
+//@{
+#define BP_USBDCD_TIMER0_TSEQ_INIT (16U) //!< Bit position for USBDCD_TIMER0_TSEQ_INIT.
+#define BM_USBDCD_TIMER0_TSEQ_INIT (0x03FF0000U) //!< Bit mask for USBDCD_TIMER0_TSEQ_INIT.
+#define BS_USBDCD_TIMER0_TSEQ_INIT (10U) //!< Bit field size in bits for USBDCD_TIMER0_TSEQ_INIT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_TIMER0_TSEQ_INIT field.
+#define BR_USBDCD_TIMER0_TSEQ_INIT(x) (HW_USBDCD_TIMER0(x).B.TSEQ_INIT)
+#endif
+
+//! @brief Format value for bitfield USBDCD_TIMER0_TSEQ_INIT.
+#define BF_USBDCD_TIMER0_TSEQ_INIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER0_TSEQ_INIT), uint32_t) & BM_USBDCD_TIMER0_TSEQ_INIT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TSEQ_INIT field to a new value.
+#define BW_USBDCD_TIMER0_TSEQ_INIT(x, v) (HW_USBDCD_TIMER0_WR(x, (HW_USBDCD_TIMER0_RD(x) & ~BM_USBDCD_TIMER0_TSEQ_INIT) | BF_USBDCD_TIMER0_TSEQ_INIT(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USBDCD_TIMER1 - TIMER1 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USBDCD_TIMER1 - TIMER1 register (RW)
+ *
+ * Reset value: 0x000A0028U
+ *
+ * TIMER1 contains timing parameters. Note that register values can be written
+ * that are not compliant with the USB Battery Charging Specification, so care
+ * should be taken when overwriting the default values.
+ */
+typedef union _hw_usbdcd_timer1
+{
+ uint32_t U;
+ struct _hw_usbdcd_timer1_bitfields
+ {
+ uint32_t TVDPSRC_ON : 10; //!< [9:0] Time Period Comparator Enabled
+ uint32_t RESERVED0 : 6; //!< [15:10]
+ uint32_t TDCD_DBNC : 10; //!< [25:16] Time Period to Debounce D+
+ //! Signal
+ uint32_t RESERVED1 : 6; //!< [31:26]
+ } B;
+} hw_usbdcd_timer1_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER1 register
+ */
+//@{
+#define HW_USBDCD_TIMER1_ADDR(x) (REGS_USBDCD_BASE(x) + 0x14U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USBDCD_TIMER1(x) (*(__IO hw_usbdcd_timer1_t *) HW_USBDCD_TIMER1_ADDR(x))
+#define HW_USBDCD_TIMER1_RD(x) (HW_USBDCD_TIMER1(x).U)
+#define HW_USBDCD_TIMER1_WR(x, v) (HW_USBDCD_TIMER1(x).U = (v))
+#define HW_USBDCD_TIMER1_SET(x, v) (HW_USBDCD_TIMER1_WR(x, HW_USBDCD_TIMER1_RD(x) | (v)))
+#define HW_USBDCD_TIMER1_CLR(x, v) (HW_USBDCD_TIMER1_WR(x, HW_USBDCD_TIMER1_RD(x) & ~(v)))
+#define HW_USBDCD_TIMER1_TOG(x, v) (HW_USBDCD_TIMER1_WR(x, HW_USBDCD_TIMER1_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USBDCD_TIMER1 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER1, field TVDPSRC_ON[9:0] (RW)
+ *
+ * This timing parameter is used after detection of the data pin. See "Charging
+ * Port Detection". Valid values are 1-1023, but the USB Battery Charging
+ * Specification requires a minimum value of 40 ms.
+ */
+//@{
+#define BP_USBDCD_TIMER1_TVDPSRC_ON (0U) //!< Bit position for USBDCD_TIMER1_TVDPSRC_ON.
+#define BM_USBDCD_TIMER1_TVDPSRC_ON (0x000003FFU) //!< Bit mask for USBDCD_TIMER1_TVDPSRC_ON.
+#define BS_USBDCD_TIMER1_TVDPSRC_ON (10U) //!< Bit field size in bits for USBDCD_TIMER1_TVDPSRC_ON.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_TIMER1_TVDPSRC_ON field.
+#define BR_USBDCD_TIMER1_TVDPSRC_ON(x) (HW_USBDCD_TIMER1(x).B.TVDPSRC_ON)
+#endif
+
+//! @brief Format value for bitfield USBDCD_TIMER1_TVDPSRC_ON.
+#define BF_USBDCD_TIMER1_TVDPSRC_ON(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER1_TVDPSRC_ON), uint32_t) & BM_USBDCD_TIMER1_TVDPSRC_ON)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TVDPSRC_ON field to a new value.
+#define BW_USBDCD_TIMER1_TVDPSRC_ON(x, v) (HW_USBDCD_TIMER1_WR(x, (HW_USBDCD_TIMER1_RD(x) & ~BM_USBDCD_TIMER1_TVDPSRC_ON) | BF_USBDCD_TIMER1_TVDPSRC_ON(v)))
+#endif
+//@}
+
+/*!
+ * @name Register USBDCD_TIMER1, field TDCD_DBNC[25:16] (RW)
+ *
+ * Sets the time period (ms) to debounce the D+ signal during the data pin
+ * contact detection phase. See "Debouncing the data pin contact" Valid values are
+ * 1-1023, but the USB Battery Charging Specification requires a minimum value of 10
+ * ms.
+ */
+//@{
+#define BP_USBDCD_TIMER1_TDCD_DBNC (16U) //!< Bit position for USBDCD_TIMER1_TDCD_DBNC.
+#define BM_USBDCD_TIMER1_TDCD_DBNC (0x03FF0000U) //!< Bit mask for USBDCD_TIMER1_TDCD_DBNC.
+#define BS_USBDCD_TIMER1_TDCD_DBNC (10U) //!< Bit field size in bits for USBDCD_TIMER1_TDCD_DBNC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_TIMER1_TDCD_DBNC field.
+#define BR_USBDCD_TIMER1_TDCD_DBNC(x) (HW_USBDCD_TIMER1(x).B.TDCD_DBNC)
+#endif
+
+//! @brief Format value for bitfield USBDCD_TIMER1_TDCD_DBNC.
+#define BF_USBDCD_TIMER1_TDCD_DBNC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER1_TDCD_DBNC), uint32_t) & BM_USBDCD_TIMER1_TDCD_DBNC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TDCD_DBNC field to a new value.
+#define BW_USBDCD_TIMER1_TDCD_DBNC(x, v) (HW_USBDCD_TIMER1_WR(x, (HW_USBDCD_TIMER1_RD(x) & ~BM_USBDCD_TIMER1_TDCD_DBNC) | BF_USBDCD_TIMER1_TDCD_DBNC(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_USBDCD_TIMER2_BC11 - TIMER2_BC11 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USBDCD_TIMER2_BC11 - TIMER2_BC11 register (RW)
+ *
+ * Reset value: 0x00280001U
+ *
+ * TIMER2_BC11 contains timing parameters for USB Battery Charging
+ * Specification, v1.1. Register values can be written that are not compliant with the USB
+ * Battery Charging Specification, so care should be taken when overwriting the
+ * default values.
+ */
+typedef union _hw_usbdcd_timer2_bc11
+{
+ uint32_t U;
+ struct _hw_usbdcd_timer2_bc11_bitfields
+ {
+ uint32_t CHECK_DM : 4; //!< [3:0] Time Before Check of D- Line
+ uint32_t RESERVED0 : 12; //!< [15:4]
+ uint32_t TVDPSRC_CON : 10; //!< [25:16] Time Period Before Enabling
+ //! D+ Pullup
+ uint32_t RESERVED1 : 6; //!< [31:26]
+ } B;
+} hw_usbdcd_timer2_bc11_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER2_BC11 register
+ */
+//@{
+#define HW_USBDCD_TIMER2_BC11_ADDR(x) (REGS_USBDCD_BASE(x) + 0x18U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USBDCD_TIMER2_BC11(x) (*(__IO hw_usbdcd_timer2_bc11_t *) HW_USBDCD_TIMER2_BC11_ADDR(x))
+#define HW_USBDCD_TIMER2_BC11_RD(x) (HW_USBDCD_TIMER2_BC11(x).U)
+#define HW_USBDCD_TIMER2_BC11_WR(x, v) (HW_USBDCD_TIMER2_BC11(x).U = (v))
+#define HW_USBDCD_TIMER2_BC11_SET(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, HW_USBDCD_TIMER2_BC11_RD(x) | (v)))
+#define HW_USBDCD_TIMER2_BC11_CLR(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, HW_USBDCD_TIMER2_BC11_RD(x) & ~(v)))
+#define HW_USBDCD_TIMER2_BC11_TOG(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, HW_USBDCD_TIMER2_BC11_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USBDCD_TIMER2_BC11 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER2_BC11, field CHECK_DM[3:0] (RW)
+ *
+ * Sets the amount of time (in ms) that the module waits after the device
+ * connects to the USB bus until checking the state of the D- line to determine the
+ * type of charging port. See "Charger Type Detection." Valid values are 1-15ms.
+ */
+//@{
+#define BP_USBDCD_TIMER2_BC11_CHECK_DM (0U) //!< Bit position for USBDCD_TIMER2_BC11_CHECK_DM.
+#define BM_USBDCD_TIMER2_BC11_CHECK_DM (0x0000000FU) //!< Bit mask for USBDCD_TIMER2_BC11_CHECK_DM.
+#define BS_USBDCD_TIMER2_BC11_CHECK_DM (4U) //!< Bit field size in bits for USBDCD_TIMER2_BC11_CHECK_DM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_TIMER2_BC11_CHECK_DM field.
+#define BR_USBDCD_TIMER2_BC11_CHECK_DM(x) (HW_USBDCD_TIMER2_BC11(x).B.CHECK_DM)
+#endif
+
+//! @brief Format value for bitfield USBDCD_TIMER2_BC11_CHECK_DM.
+#define BF_USBDCD_TIMER2_BC11_CHECK_DM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER2_BC11_CHECK_DM), uint32_t) & BM_USBDCD_TIMER2_BC11_CHECK_DM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CHECK_DM field to a new value.
+#define BW_USBDCD_TIMER2_BC11_CHECK_DM(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, (HW_USBDCD_TIMER2_BC11_RD(x) & ~BM_USBDCD_TIMER2_BC11_CHECK_DM) | BF_USBDCD_TIMER2_BC11_CHECK_DM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register USBDCD_TIMER2_BC11, field TVDPSRC_CON[25:16] (RW)
+ *
+ * Sets the time period (ms) that the module waits after charging port detection
+ * before system software must enable the D+ pullup to connect to the USB host.
+ * Valid values are 1-1023, but the USB Battery Charging Specification requires a
+ * minimum value of 40 ms.
+ */
+//@{
+#define BP_USBDCD_TIMER2_BC11_TVDPSRC_CON (16U) //!< Bit position for USBDCD_TIMER2_BC11_TVDPSRC_CON.
+#define BM_USBDCD_TIMER2_BC11_TVDPSRC_CON (0x03FF0000U) //!< Bit mask for USBDCD_TIMER2_BC11_TVDPSRC_CON.
+#define BS_USBDCD_TIMER2_BC11_TVDPSRC_CON (10U) //!< Bit field size in bits for USBDCD_TIMER2_BC11_TVDPSRC_CON.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_TIMER2_BC11_TVDPSRC_CON field.
+#define BR_USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (HW_USBDCD_TIMER2_BC11(x).B.TVDPSRC_CON)
+#endif
+
+//! @brief Format value for bitfield USBDCD_TIMER2_BC11_TVDPSRC_CON.
+#define BF_USBDCD_TIMER2_BC11_TVDPSRC_CON(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER2_BC11_TVDPSRC_CON), uint32_t) & BM_USBDCD_TIMER2_BC11_TVDPSRC_CON)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TVDPSRC_CON field to a new value.
+#define BW_USBDCD_TIMER2_BC11_TVDPSRC_CON(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, (HW_USBDCD_TIMER2_BC11_RD(x) & ~BM_USBDCD_TIMER2_BC11_TVDPSRC_CON) | BF_USBDCD_TIMER2_BC11_TVDPSRC_CON(v)))
+#endif
+//@}
+//-------------------------------------------------------------------------------------------
+// HW_USBDCD_TIMER2_BC12 - TIMER2_BC12 register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_USBDCD_TIMER2_BC12 - TIMER2_BC12 register (RW)
+ *
+ * Reset value: 0x00010028U
+ *
+ * TIMER2_BC12 contains timing parameters for USB Battery Charging
+ * Specification, v1.2. Register values can be written that are not compliant with the USB
+ * Battery Charging Specification, so care should be taken when overwriting the
+ * default values.
+ */
+typedef union _hw_usbdcd_timer2_bc12
+{
+ uint32_t U;
+ struct _hw_usbdcd_timer2_bc12_bitfields
+ {
+ uint32_t TVDMSRC_ON : 10; //!< [9:0]
+ uint32_t RESERVED0 : 6; //!< [15:10]
+ uint32_t TWAIT_AFTER_PRD : 10; //!< [25:16]
+ uint32_t RESERVED1 : 6; //!< [31:26]
+ } B;
+} hw_usbdcd_timer2_bc12_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER2_BC12 register
+ */
+//@{
+#define HW_USBDCD_TIMER2_BC12_ADDR(x) (REGS_USBDCD_BASE(x) + 0x18U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_USBDCD_TIMER2_BC12(x) (*(__IO hw_usbdcd_timer2_bc12_t *) HW_USBDCD_TIMER2_BC12_ADDR(x))
+#define HW_USBDCD_TIMER2_BC12_RD(x) (HW_USBDCD_TIMER2_BC12(x).U)
+#define HW_USBDCD_TIMER2_BC12_WR(x, v) (HW_USBDCD_TIMER2_BC12(x).U = (v))
+#define HW_USBDCD_TIMER2_BC12_SET(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, HW_USBDCD_TIMER2_BC12_RD(x) | (v)))
+#define HW_USBDCD_TIMER2_BC12_CLR(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, HW_USBDCD_TIMER2_BC12_RD(x) & ~(v)))
+#define HW_USBDCD_TIMER2_BC12_TOG(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, HW_USBDCD_TIMER2_BC12_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual USBDCD_TIMER2_BC12 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER2_BC12, field TVDMSRC_ON[9:0] (RW)
+ *
+ * Sets the amount of time (in ms) that the module enables the VDM_SRC. Valid
+ * values are 0-40ms.
+ */
+//@{
+#define BP_USBDCD_TIMER2_BC12_TVDMSRC_ON (0U) //!< Bit position for USBDCD_TIMER2_BC12_TVDMSRC_ON.
+#define BM_USBDCD_TIMER2_BC12_TVDMSRC_ON (0x000003FFU) //!< Bit mask for USBDCD_TIMER2_BC12_TVDMSRC_ON.
+#define BS_USBDCD_TIMER2_BC12_TVDMSRC_ON (10U) //!< Bit field size in bits for USBDCD_TIMER2_BC12_TVDMSRC_ON.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_TIMER2_BC12_TVDMSRC_ON field.
+#define BR_USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (HW_USBDCD_TIMER2_BC12(x).B.TVDMSRC_ON)
+#endif
+
+//! @brief Format value for bitfield USBDCD_TIMER2_BC12_TVDMSRC_ON.
+#define BF_USBDCD_TIMER2_BC12_TVDMSRC_ON(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER2_BC12_TVDMSRC_ON), uint32_t) & BM_USBDCD_TIMER2_BC12_TVDMSRC_ON)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TVDMSRC_ON field to a new value.
+#define BW_USBDCD_TIMER2_BC12_TVDMSRC_ON(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, (HW_USBDCD_TIMER2_BC12_RD(x) & ~BM_USBDCD_TIMER2_BC12_TVDMSRC_ON) | BF_USBDCD_TIMER2_BC12_TVDMSRC_ON(v)))
+#endif
+//@}
+
+/*!
+ * @name Register USBDCD_TIMER2_BC12, field TWAIT_AFTER_PRD[25:16] (RW)
+ *
+ * Sets the amount of time (in ms) that the module waits after primary detection
+ * before start to secondary detection. Valid values are 1-1023ms. Default is
+ * 1ms.
+ */
+//@{
+#define BP_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD (16U) //!< Bit position for USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD.
+#define BM_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD (0x03FF0000U) //!< Bit mask for USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD.
+#define BS_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD (10U) //!< Bit field size in bits for USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD field.
+#define BR_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (HW_USBDCD_TIMER2_BC12(x).B.TWAIT_AFTER_PRD)
+#endif
+
+//! @brief Format value for bitfield USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD.
+#define BF_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD), uint32_t) & BM_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TWAIT_AFTER_PRD field to a new value.
+#define BW_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, (HW_USBDCD_TIMER2_BC12_RD(x) & ~BM_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD) | BF_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_usbdcd_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All USBDCD module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_usbdcd
+{
+ __IO hw_usbdcd_control_t CONTROL; //!< [0x0] Control register
+ __IO hw_usbdcd_clock_t CLOCK; //!< [0x4] Clock register
+ __I hw_usbdcd_status_t STATUS; //!< [0x8] Status register
+ uint8_t _reserved0[4];
+ __IO hw_usbdcd_timer0_t TIMER0; //!< [0x10] TIMER0 register
+ __IO hw_usbdcd_timer1_t TIMER1; //!< [0x14] TIMER1 register
+ union {
+ __IO hw_usbdcd_timer2_bc11_t TIMER2_BC11; //!< [0x18] TIMER2_BC11 register
+ __IO hw_usbdcd_timer2_bc12_t TIMER2_BC12; //!< [0x18] TIMER2_BC12 register
+ };
+} hw_usbdcd_t;
+#pragma pack()
+
+//! @brief Macro to access all USBDCD registers.
+//! @param x USBDCD instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_USBDCD(0)</code>.
+#define HW_USBDCD(x) (*(hw_usbdcd_t *) REGS_USBDCD_BASE(x))
+#endif
+
+#endif // __HW_USBDCD_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_vref.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,369 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_VREF_REGISTERS_H__
+#define __HW_VREF_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 VREF
+ *
+ * Voltage Reference
+ *
+ * Registers defined in this header file:
+ * - HW_VREF_TRM - VREF Trim Register
+ * - HW_VREF_SC - VREF Status and Control Register
+ *
+ * - hw_vref_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_VREF_BASE
+#define HW_VREF_INSTANCE_COUNT (1U) //!< Number of instances of the VREF module.
+#define REGS_VREF_BASE (0x40074000U) //!< Base address for VREF.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_VREF_TRM - VREF Trim Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_VREF_TRM - VREF Trim Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains bits that contain the trim data for the Voltage
+ * Reference.
+ */
+typedef union _hw_vref_trm
+{
+ uint8_t U;
+ struct _hw_vref_trm_bitfields
+ {
+ uint8_t TRIM : 6; //!< [5:0] Trim bits
+ uint8_t CHOPEN : 1; //!< [6] Chop oscillator enable. When set,
+ //! internal chopping operation is enabled and the internal analog offset will
+ //! be minimized.
+ uint8_t RESERVED0 : 1; //!< [7]
+ } B;
+} hw_vref_trm_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire VREF_TRM register
+ */
+//@{
+#define HW_VREF_TRM_ADDR (REGS_VREF_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_VREF_TRM (*(__IO hw_vref_trm_t *) HW_VREF_TRM_ADDR)
+#define HW_VREF_TRM_RD() (HW_VREF_TRM.U)
+#define HW_VREF_TRM_WR(v) (HW_VREF_TRM.U = (v))
+#define HW_VREF_TRM_SET(v) (HW_VREF_TRM_WR(HW_VREF_TRM_RD() | (v)))
+#define HW_VREF_TRM_CLR(v) (HW_VREF_TRM_WR(HW_VREF_TRM_RD() & ~(v)))
+#define HW_VREF_TRM_TOG(v) (HW_VREF_TRM_WR(HW_VREF_TRM_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual VREF_TRM bitfields
+ */
+
+/*!
+ * @name Register VREF_TRM, field TRIM[5:0] (RW)
+ *
+ * These bits change the resulting VREF by approximately +/- 0.5 mV for each
+ * step. Min = minimum and max = maximum voltage reference output. For minimum and
+ * maximum voltage reference output values, refer to the Data Sheet for this chip.
+ *
+ * Values:
+ * - 000000 - Min
+ * - 111111 - Max
+ */
+//@{
+#define BP_VREF_TRM_TRIM (0U) //!< Bit position for VREF_TRM_TRIM.
+#define BM_VREF_TRM_TRIM (0x3FU) //!< Bit mask for VREF_TRM_TRIM.
+#define BS_VREF_TRM_TRIM (6U) //!< Bit field size in bits for VREF_TRM_TRIM.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the VREF_TRM_TRIM field.
+#define BR_VREF_TRM_TRIM (HW_VREF_TRM.B.TRIM)
+#endif
+
+//! @brief Format value for bitfield VREF_TRM_TRIM.
+#define BF_VREF_TRM_TRIM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_TRM_TRIM), uint8_t) & BM_VREF_TRM_TRIM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TRIM field to a new value.
+#define BW_VREF_TRM_TRIM(v) (HW_VREF_TRM_WR((HW_VREF_TRM_RD() & ~BM_VREF_TRM_TRIM) | BF_VREF_TRM_TRIM(v)))
+#endif
+//@}
+
+/*!
+ * @name Register VREF_TRM, field CHOPEN[6] (RW)
+ *
+ * This bit is set during factory trimming of the VREF voltage. This bit should
+ * be written to 1 to achieve the performance stated in the data sheet.
+ *
+ * Values:
+ * - 0 - Chop oscillator is disabled.
+ * - 1 - Chop oscillator is enabled.
+ */
+//@{
+#define BP_VREF_TRM_CHOPEN (6U) //!< Bit position for VREF_TRM_CHOPEN.
+#define BM_VREF_TRM_CHOPEN (0x40U) //!< Bit mask for VREF_TRM_CHOPEN.
+#define BS_VREF_TRM_CHOPEN (1U) //!< Bit field size in bits for VREF_TRM_CHOPEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the VREF_TRM_CHOPEN field.
+#define BR_VREF_TRM_CHOPEN (BITBAND_ACCESS8(HW_VREF_TRM_ADDR, BP_VREF_TRM_CHOPEN))
+#endif
+
+//! @brief Format value for bitfield VREF_TRM_CHOPEN.
+#define BF_VREF_TRM_CHOPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_TRM_CHOPEN), uint8_t) & BM_VREF_TRM_CHOPEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CHOPEN field to a new value.
+#define BW_VREF_TRM_CHOPEN(v) (BITBAND_ACCESS8(HW_VREF_TRM_ADDR, BP_VREF_TRM_CHOPEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_VREF_SC - VREF Status and Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_VREF_SC - VREF Status and Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains the control bits used to enable the internal voltage
+ * reference and to select the buffer mode to be used.
+ */
+typedef union _hw_vref_sc
+{
+ uint8_t U;
+ struct _hw_vref_sc_bitfields
+ {
+ uint8_t MODE_LV : 2; //!< [1:0] Buffer Mode selection
+ uint8_t VREFST : 1; //!< [2] Internal Voltage Reference stable
+ uint8_t RESERVED0 : 2; //!< [4:3]
+ uint8_t ICOMPEN : 1; //!< [5] Second order curvature compensation
+ //! enable
+ uint8_t REGEN : 1; //!< [6] Regulator enable
+ uint8_t VREFEN : 1; //!< [7] Internal Voltage Reference enable
+ } B;
+} hw_vref_sc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire VREF_SC register
+ */
+//@{
+#define HW_VREF_SC_ADDR (REGS_VREF_BASE + 0x1U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_VREF_SC (*(__IO hw_vref_sc_t *) HW_VREF_SC_ADDR)
+#define HW_VREF_SC_RD() (HW_VREF_SC.U)
+#define HW_VREF_SC_WR(v) (HW_VREF_SC.U = (v))
+#define HW_VREF_SC_SET(v) (HW_VREF_SC_WR(HW_VREF_SC_RD() | (v)))
+#define HW_VREF_SC_CLR(v) (HW_VREF_SC_WR(HW_VREF_SC_RD() & ~(v)))
+#define HW_VREF_SC_TOG(v) (HW_VREF_SC_WR(HW_VREF_SC_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual VREF_SC bitfields
+ */
+
+/*!
+ * @name Register VREF_SC, field MODE_LV[1:0] (RW)
+ *
+ * These bits select the buffer modes for the Voltage Reference module.
+ *
+ * Values:
+ * - 00 - Bandgap on only, for stabilization and startup
+ * - 01 - High power buffer mode enabled
+ * - 10 - Low-power buffer mode enabled
+ * - 11 - Reserved
+ */
+//@{
+#define BP_VREF_SC_MODE_LV (0U) //!< Bit position for VREF_SC_MODE_LV.
+#define BM_VREF_SC_MODE_LV (0x03U) //!< Bit mask for VREF_SC_MODE_LV.
+#define BS_VREF_SC_MODE_LV (2U) //!< Bit field size in bits for VREF_SC_MODE_LV.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the VREF_SC_MODE_LV field.
+#define BR_VREF_SC_MODE_LV (HW_VREF_SC.B.MODE_LV)
+#endif
+
+//! @brief Format value for bitfield VREF_SC_MODE_LV.
+#define BF_VREF_SC_MODE_LV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_SC_MODE_LV), uint8_t) & BM_VREF_SC_MODE_LV)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MODE_LV field to a new value.
+#define BW_VREF_SC_MODE_LV(v) (HW_VREF_SC_WR((HW_VREF_SC_RD() & ~BM_VREF_SC_MODE_LV) | BF_VREF_SC_MODE_LV(v)))
+#endif
+//@}
+
+/*!
+ * @name Register VREF_SC, field VREFST[2] (RO)
+ *
+ * This bit indicates that the bandgap reference within the Voltage Reference
+ * module has completed its startup and stabilization.
+ *
+ * Values:
+ * - 0 - The module is disabled or not stable.
+ * - 1 - The module is stable.
+ */
+//@{
+#define BP_VREF_SC_VREFST (2U) //!< Bit position for VREF_SC_VREFST.
+#define BM_VREF_SC_VREFST (0x04U) //!< Bit mask for VREF_SC_VREFST.
+#define BS_VREF_SC_VREFST (1U) //!< Bit field size in bits for VREF_SC_VREFST.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the VREF_SC_VREFST field.
+#define BR_VREF_SC_VREFST (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_VREFST))
+#endif
+//@}
+
+/*!
+ * @name Register VREF_SC, field ICOMPEN[5] (RW)
+ *
+ * This bit is set during factory trimming of the VREF voltage. This bit should
+ * be written to 1 to achieve the performance stated in the data sheet.
+ *
+ * Values:
+ * - 0 - Disabled
+ * - 1 - Enabled
+ */
+//@{
+#define BP_VREF_SC_ICOMPEN (5U) //!< Bit position for VREF_SC_ICOMPEN.
+#define BM_VREF_SC_ICOMPEN (0x20U) //!< Bit mask for VREF_SC_ICOMPEN.
+#define BS_VREF_SC_ICOMPEN (1U) //!< Bit field size in bits for VREF_SC_ICOMPEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the VREF_SC_ICOMPEN field.
+#define BR_VREF_SC_ICOMPEN (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_ICOMPEN))
+#endif
+
+//! @brief Format value for bitfield VREF_SC_ICOMPEN.
+#define BF_VREF_SC_ICOMPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_SC_ICOMPEN), uint8_t) & BM_VREF_SC_ICOMPEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ICOMPEN field to a new value.
+#define BW_VREF_SC_ICOMPEN(v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_ICOMPEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register VREF_SC, field REGEN[6] (RW)
+ *
+ * This bit is used to enable the internal 1.75 V regulator to produce a
+ * constant internal voltage supply in order to reduce the sensitivity to external
+ * supply noise and variation. If it is desired to keep the regulator enabled in very
+ * low power modes, refer to the Chip Configuration details for a description on
+ * how this can be achieved. This bit is set during factory trimming of the VREF
+ * voltage. This bit should be written to 1 to achieve the performance stated in
+ * the data sheet.
+ *
+ * Values:
+ * - 0 - Internal 1.75 V regulator is disabled.
+ * - 1 - Internal 1.75 V regulator is enabled.
+ */
+//@{
+#define BP_VREF_SC_REGEN (6U) //!< Bit position for VREF_SC_REGEN.
+#define BM_VREF_SC_REGEN (0x40U) //!< Bit mask for VREF_SC_REGEN.
+#define BS_VREF_SC_REGEN (1U) //!< Bit field size in bits for VREF_SC_REGEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the VREF_SC_REGEN field.
+#define BR_VREF_SC_REGEN (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_REGEN))
+#endif
+
+//! @brief Format value for bitfield VREF_SC_REGEN.
+#define BF_VREF_SC_REGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_SC_REGEN), uint8_t) & BM_VREF_SC_REGEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the REGEN field to a new value.
+#define BW_VREF_SC_REGEN(v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_REGEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register VREF_SC, field VREFEN[7] (RW)
+ *
+ * This bit is used to enable the bandgap reference within the Voltage Reference
+ * module. After the VREF is enabled, turning off the clock to the VREF module
+ * via the corresponding clock gate register will not disable the VREF. VREF must
+ * be disabled via this VREFEN bit.
+ *
+ * Values:
+ * - 0 - The module is disabled.
+ * - 1 - The module is enabled.
+ */
+//@{
+#define BP_VREF_SC_VREFEN (7U) //!< Bit position for VREF_SC_VREFEN.
+#define BM_VREF_SC_VREFEN (0x80U) //!< Bit mask for VREF_SC_VREFEN.
+#define BS_VREF_SC_VREFEN (1U) //!< Bit field size in bits for VREF_SC_VREFEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the VREF_SC_VREFEN field.
+#define BR_VREF_SC_VREFEN (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_VREFEN))
+#endif
+
+//! @brief Format value for bitfield VREF_SC_VREFEN.
+#define BF_VREF_SC_VREFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_SC_VREFEN), uint8_t) & BM_VREF_SC_VREFEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the VREFEN field to a new value.
+#define BW_VREF_SC_VREFEN(v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_VREFEN) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_vref_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All VREF module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_vref
+{
+ __IO hw_vref_trm_t TRM; //!< [0x0] VREF Trim Register
+ __IO hw_vref_sc_t SC; //!< [0x1] VREF Status and Control Register
+} hw_vref_t;
+#pragma pack()
+
+//! @brief Macro to access all VREF registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_VREF</code>.
+#define HW_VREF (*(hw_vref_t *) REGS_VREF_BASE)
+#endif
+
+#endif // __HW_VREF_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_wdog.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,1244 @@
+/*
+ * Copyright (c) 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_WDOG_REGISTERS_H__
+#define __HW_WDOG_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * MK64F12 WDOG
+ *
+ * Generation 2008 Watchdog Timer
+ *
+ * Registers defined in this header file:
+ * - HW_WDOG_STCTRLH - Watchdog Status and Control Register High
+ * - HW_WDOG_STCTRLL - Watchdog Status and Control Register Low
+ * - HW_WDOG_TOVALH - Watchdog Time-out Value Register High
+ * - HW_WDOG_TOVALL - Watchdog Time-out Value Register Low
+ * - HW_WDOG_WINH - Watchdog Window Register High
+ * - HW_WDOG_WINL - Watchdog Window Register Low
+ * - HW_WDOG_REFRESH - Watchdog Refresh register
+ * - HW_WDOG_UNLOCK - Watchdog Unlock register
+ * - HW_WDOG_TMROUTH - Watchdog Timer Output Register High
+ * - HW_WDOG_TMROUTL - Watchdog Timer Output Register Low
+ * - HW_WDOG_RSTCNT - Watchdog Reset Count register
+ * - HW_WDOG_PRESC - Watchdog Prescaler register
+ *
+ * - hw_wdog_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_WDOG_BASE
+#define HW_WDOG_INSTANCE_COUNT (1U) //!< Number of instances of the WDOG module.
+#define REGS_WDOG_BASE (0x40052000U) //!< Base address for WDOG.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_WDOG_STCTRLH - Watchdog Status and Control Register High
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_WDOG_STCTRLH - Watchdog Status and Control Register High (RW)
+ *
+ * Reset value: 0x01D3U
+ */
+typedef union _hw_wdog_stctrlh
+{
+ uint16_t U;
+ struct _hw_wdog_stctrlh_bitfields
+ {
+ uint16_t WDOGEN : 1; //!< [0]
+ uint16_t CLKSRC : 1; //!< [1]
+ uint16_t IRQRSTEN : 1; //!< [2]
+ uint16_t WINEN : 1; //!< [3]
+ uint16_t ALLOWUPDATE : 1; //!< [4]
+ uint16_t DBGEN : 1; //!< [5]
+ uint16_t STOPEN : 1; //!< [6]
+ uint16_t WAITEN : 1; //!< [7]
+ uint16_t RESERVED0 : 2; //!< [9:8]
+ uint16_t TESTWDOG : 1; //!< [10]
+ uint16_t TESTSEL : 1; //!< [11]
+ uint16_t BYTESEL : 2; //!< [13:12]
+ uint16_t DISTESTWDOG : 1; //!< [14]
+ uint16_t RESERVED1 : 1; //!< [15]
+ } B;
+} hw_wdog_stctrlh_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire WDOG_STCTRLH register
+ */
+//@{
+#define HW_WDOG_STCTRLH_ADDR (REGS_WDOG_BASE + 0x0U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_WDOG_STCTRLH (*(__IO hw_wdog_stctrlh_t *) HW_WDOG_STCTRLH_ADDR)
+#define HW_WDOG_STCTRLH_RD() (HW_WDOG_STCTRLH.U)
+#define HW_WDOG_STCTRLH_WR(v) (HW_WDOG_STCTRLH.U = (v))
+#define HW_WDOG_STCTRLH_SET(v) (HW_WDOG_STCTRLH_WR(HW_WDOG_STCTRLH_RD() | (v)))
+#define HW_WDOG_STCTRLH_CLR(v) (HW_WDOG_STCTRLH_WR(HW_WDOG_STCTRLH_RD() & ~(v)))
+#define HW_WDOG_STCTRLH_TOG(v) (HW_WDOG_STCTRLH_WR(HW_WDOG_STCTRLH_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual WDOG_STCTRLH bitfields
+ */
+
+/*!
+ * @name Register WDOG_STCTRLH, field WDOGEN[0] (RW)
+ *
+ * Enables or disables the WDOG's operation. In the disabled state, the watchdog
+ * timer is kept in the reset state, but the other exception conditions can
+ * still trigger a reset/interrupt. A change in the value of this bit must be held
+ * for more than one WDOG_CLK cycle for the WDOG to be enabled or disabled.
+ *
+ * Values:
+ * - 0 - WDOG is disabled.
+ * - 1 - WDOG is enabled.
+ */
+//@{
+#define BP_WDOG_STCTRLH_WDOGEN (0U) //!< Bit position for WDOG_STCTRLH_WDOGEN.
+#define BM_WDOG_STCTRLH_WDOGEN (0x0001U) //!< Bit mask for WDOG_STCTRLH_WDOGEN.
+#define BS_WDOG_STCTRLH_WDOGEN (1U) //!< Bit field size in bits for WDOG_STCTRLH_WDOGEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_STCTRLH_WDOGEN field.
+#define BR_WDOG_STCTRLH_WDOGEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WDOGEN))
+#endif
+
+//! @brief Format value for bitfield WDOG_STCTRLH_WDOGEN.
+#define BF_WDOG_STCTRLH_WDOGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_WDOGEN), uint16_t) & BM_WDOG_STCTRLH_WDOGEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WDOGEN field to a new value.
+#define BW_WDOG_STCTRLH_WDOGEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WDOGEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register WDOG_STCTRLH, field CLKSRC[1] (RW)
+ *
+ * Selects clock source for the WDOG timer and other internal timing operations.
+ *
+ * Values:
+ * - 0 - WDOG clock sourced from LPO .
+ * - 1 - WDOG clock sourced from alternate clock source.
+ */
+//@{
+#define BP_WDOG_STCTRLH_CLKSRC (1U) //!< Bit position for WDOG_STCTRLH_CLKSRC.
+#define BM_WDOG_STCTRLH_CLKSRC (0x0002U) //!< Bit mask for WDOG_STCTRLH_CLKSRC.
+#define BS_WDOG_STCTRLH_CLKSRC (1U) //!< Bit field size in bits for WDOG_STCTRLH_CLKSRC.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_STCTRLH_CLKSRC field.
+#define BR_WDOG_STCTRLH_CLKSRC (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_CLKSRC))
+#endif
+
+//! @brief Format value for bitfield WDOG_STCTRLH_CLKSRC.
+#define BF_WDOG_STCTRLH_CLKSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_CLKSRC), uint16_t) & BM_WDOG_STCTRLH_CLKSRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLKSRC field to a new value.
+#define BW_WDOG_STCTRLH_CLKSRC(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_CLKSRC) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register WDOG_STCTRLH, field IRQRSTEN[2] (RW)
+ *
+ * Used to enable the debug breadcrumbs feature. A change in this bit is updated
+ * immediately, as opposed to updating after WCT.
+ *
+ * Values:
+ * - 0 - WDOG time-out generates reset only.
+ * - 1 - WDOG time-out initially generates an interrupt. After WCT, it generates
+ * a reset.
+ */
+//@{
+#define BP_WDOG_STCTRLH_IRQRSTEN (2U) //!< Bit position for WDOG_STCTRLH_IRQRSTEN.
+#define BM_WDOG_STCTRLH_IRQRSTEN (0x0004U) //!< Bit mask for WDOG_STCTRLH_IRQRSTEN.
+#define BS_WDOG_STCTRLH_IRQRSTEN (1U) //!< Bit field size in bits for WDOG_STCTRLH_IRQRSTEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_STCTRLH_IRQRSTEN field.
+#define BR_WDOG_STCTRLH_IRQRSTEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_IRQRSTEN))
+#endif
+
+//! @brief Format value for bitfield WDOG_STCTRLH_IRQRSTEN.
+#define BF_WDOG_STCTRLH_IRQRSTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_IRQRSTEN), uint16_t) & BM_WDOG_STCTRLH_IRQRSTEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IRQRSTEN field to a new value.
+#define BW_WDOG_STCTRLH_IRQRSTEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_IRQRSTEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register WDOG_STCTRLH, field WINEN[3] (RW)
+ *
+ * Enables Windowing mode.
+ *
+ * Values:
+ * - 0 - Windowing mode is disabled.
+ * - 1 - Windowing mode is enabled.
+ */
+//@{
+#define BP_WDOG_STCTRLH_WINEN (3U) //!< Bit position for WDOG_STCTRLH_WINEN.
+#define BM_WDOG_STCTRLH_WINEN (0x0008U) //!< Bit mask for WDOG_STCTRLH_WINEN.
+#define BS_WDOG_STCTRLH_WINEN (1U) //!< Bit field size in bits for WDOG_STCTRLH_WINEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_STCTRLH_WINEN field.
+#define BR_WDOG_STCTRLH_WINEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WINEN))
+#endif
+
+//! @brief Format value for bitfield WDOG_STCTRLH_WINEN.
+#define BF_WDOG_STCTRLH_WINEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_WINEN), uint16_t) & BM_WDOG_STCTRLH_WINEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WINEN field to a new value.
+#define BW_WDOG_STCTRLH_WINEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WINEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register WDOG_STCTRLH, field ALLOWUPDATE[4] (RW)
+ *
+ * Enables updates to watchdog write-once registers, after the reset-triggered
+ * initial configuration window (WCT) closes, through unlock sequence.
+ *
+ * Values:
+ * - 0 - No further updates allowed to WDOG write-once registers.
+ * - 1 - WDOG write-once registers can be unlocked for updating.
+ */
+//@{
+#define BP_WDOG_STCTRLH_ALLOWUPDATE (4U) //!< Bit position for WDOG_STCTRLH_ALLOWUPDATE.
+#define BM_WDOG_STCTRLH_ALLOWUPDATE (0x0010U) //!< Bit mask for WDOG_STCTRLH_ALLOWUPDATE.
+#define BS_WDOG_STCTRLH_ALLOWUPDATE (1U) //!< Bit field size in bits for WDOG_STCTRLH_ALLOWUPDATE.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_STCTRLH_ALLOWUPDATE field.
+#define BR_WDOG_STCTRLH_ALLOWUPDATE (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_ALLOWUPDATE))
+#endif
+
+//! @brief Format value for bitfield WDOG_STCTRLH_ALLOWUPDATE.
+#define BF_WDOG_STCTRLH_ALLOWUPDATE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_ALLOWUPDATE), uint16_t) & BM_WDOG_STCTRLH_ALLOWUPDATE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ALLOWUPDATE field to a new value.
+#define BW_WDOG_STCTRLH_ALLOWUPDATE(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_ALLOWUPDATE) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register WDOG_STCTRLH, field DBGEN[5] (RW)
+ *
+ * Enables or disables WDOG in Debug mode.
+ *
+ * Values:
+ * - 0 - WDOG is disabled in CPU Debug mode.
+ * - 1 - WDOG is enabled in CPU Debug mode.
+ */
+//@{
+#define BP_WDOG_STCTRLH_DBGEN (5U) //!< Bit position for WDOG_STCTRLH_DBGEN.
+#define BM_WDOG_STCTRLH_DBGEN (0x0020U) //!< Bit mask for WDOG_STCTRLH_DBGEN.
+#define BS_WDOG_STCTRLH_DBGEN (1U) //!< Bit field size in bits for WDOG_STCTRLH_DBGEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_STCTRLH_DBGEN field.
+#define BR_WDOG_STCTRLH_DBGEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_DBGEN))
+#endif
+
+//! @brief Format value for bitfield WDOG_STCTRLH_DBGEN.
+#define BF_WDOG_STCTRLH_DBGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_DBGEN), uint16_t) & BM_WDOG_STCTRLH_DBGEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DBGEN field to a new value.
+#define BW_WDOG_STCTRLH_DBGEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_DBGEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register WDOG_STCTRLH, field STOPEN[6] (RW)
+ *
+ * Enables or disables WDOG in Stop mode.
+ *
+ * Values:
+ * - 0 - WDOG is disabled in CPU Stop mode.
+ * - 1 - WDOG is enabled in CPU Stop mode.
+ */
+//@{
+#define BP_WDOG_STCTRLH_STOPEN (6U) //!< Bit position for WDOG_STCTRLH_STOPEN.
+#define BM_WDOG_STCTRLH_STOPEN (0x0040U) //!< Bit mask for WDOG_STCTRLH_STOPEN.
+#define BS_WDOG_STCTRLH_STOPEN (1U) //!< Bit field size in bits for WDOG_STCTRLH_STOPEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_STCTRLH_STOPEN field.
+#define BR_WDOG_STCTRLH_STOPEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_STOPEN))
+#endif
+
+//! @brief Format value for bitfield WDOG_STCTRLH_STOPEN.
+#define BF_WDOG_STCTRLH_STOPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_STOPEN), uint16_t) & BM_WDOG_STCTRLH_STOPEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the STOPEN field to a new value.
+#define BW_WDOG_STCTRLH_STOPEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_STOPEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register WDOG_STCTRLH, field WAITEN[7] (RW)
+ *
+ * Enables or disables WDOG in Wait mode.
+ *
+ * Values:
+ * - 0 - WDOG is disabled in CPU Wait mode.
+ * - 1 - WDOG is enabled in CPU Wait mode.
+ */
+//@{
+#define BP_WDOG_STCTRLH_WAITEN (7U) //!< Bit position for WDOG_STCTRLH_WAITEN.
+#define BM_WDOG_STCTRLH_WAITEN (0x0080U) //!< Bit mask for WDOG_STCTRLH_WAITEN.
+#define BS_WDOG_STCTRLH_WAITEN (1U) //!< Bit field size in bits for WDOG_STCTRLH_WAITEN.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_STCTRLH_WAITEN field.
+#define BR_WDOG_STCTRLH_WAITEN (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WAITEN))
+#endif
+
+//! @brief Format value for bitfield WDOG_STCTRLH_WAITEN.
+#define BF_WDOG_STCTRLH_WAITEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_WAITEN), uint16_t) & BM_WDOG_STCTRLH_WAITEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WAITEN field to a new value.
+#define BW_WDOG_STCTRLH_WAITEN(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_WAITEN) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register WDOG_STCTRLH, field TESTWDOG[10] (RW)
+ *
+ * Puts the watchdog in the functional test mode. In this mode, the watchdog
+ * timer and the associated compare and reset generation logic is tested for correct
+ * operation. The clock for the timer is switched from the main watchdog clock
+ * to the fast clock input for watchdog functional test. The TESTSEL bit selects
+ * the test to be run.
+ */
+//@{
+#define BP_WDOG_STCTRLH_TESTWDOG (10U) //!< Bit position for WDOG_STCTRLH_TESTWDOG.
+#define BM_WDOG_STCTRLH_TESTWDOG (0x0400U) //!< Bit mask for WDOG_STCTRLH_TESTWDOG.
+#define BS_WDOG_STCTRLH_TESTWDOG (1U) //!< Bit field size in bits for WDOG_STCTRLH_TESTWDOG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_STCTRLH_TESTWDOG field.
+#define BR_WDOG_STCTRLH_TESTWDOG (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_TESTWDOG))
+#endif
+
+//! @brief Format value for bitfield WDOG_STCTRLH_TESTWDOG.
+#define BF_WDOG_STCTRLH_TESTWDOG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_TESTWDOG), uint16_t) & BM_WDOG_STCTRLH_TESTWDOG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TESTWDOG field to a new value.
+#define BW_WDOG_STCTRLH_TESTWDOG(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_TESTWDOG) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register WDOG_STCTRLH, field TESTSEL[11] (RW)
+ *
+ * Effective only if TESTWDOG is set. Selects the test to be run on the watchdog
+ * timer.
+ *
+ * Values:
+ * - 0 - Quick test. The timer runs in normal operation. You can load a small
+ * time-out value to do a quick test.
+ * - 1 - Byte test. Puts the timer in the byte test mode where individual bytes
+ * of the timer are enabled for operation and are compared for time-out
+ * against the corresponding byte of the programmed time-out value. Select the
+ * byte through BYTESEL[1:0] for testing.
+ */
+//@{
+#define BP_WDOG_STCTRLH_TESTSEL (11U) //!< Bit position for WDOG_STCTRLH_TESTSEL.
+#define BM_WDOG_STCTRLH_TESTSEL (0x0800U) //!< Bit mask for WDOG_STCTRLH_TESTSEL.
+#define BS_WDOG_STCTRLH_TESTSEL (1U) //!< Bit field size in bits for WDOG_STCTRLH_TESTSEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_STCTRLH_TESTSEL field.
+#define BR_WDOG_STCTRLH_TESTSEL (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_TESTSEL))
+#endif
+
+//! @brief Format value for bitfield WDOG_STCTRLH_TESTSEL.
+#define BF_WDOG_STCTRLH_TESTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_TESTSEL), uint16_t) & BM_WDOG_STCTRLH_TESTSEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TESTSEL field to a new value.
+#define BW_WDOG_STCTRLH_TESTSEL(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_TESTSEL) = (v))
+#endif
+//@}
+
+/*!
+ * @name Register WDOG_STCTRLH, field BYTESEL[13:12] (RW)
+ *
+ * This 2-bit field selects the byte to be tested when the watchdog is in the
+ * byte test mode.
+ *
+ * Values:
+ * - 00 - Byte 0 selected
+ * - 01 - Byte 1 selected
+ * - 10 - Byte 2 selected
+ * - 11 - Byte 3 selected
+ */
+//@{
+#define BP_WDOG_STCTRLH_BYTESEL (12U) //!< Bit position for WDOG_STCTRLH_BYTESEL.
+#define BM_WDOG_STCTRLH_BYTESEL (0x3000U) //!< Bit mask for WDOG_STCTRLH_BYTESEL.
+#define BS_WDOG_STCTRLH_BYTESEL (2U) //!< Bit field size in bits for WDOG_STCTRLH_BYTESEL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_STCTRLH_BYTESEL field.
+#define BR_WDOG_STCTRLH_BYTESEL (HW_WDOG_STCTRLH.B.BYTESEL)
+#endif
+
+//! @brief Format value for bitfield WDOG_STCTRLH_BYTESEL.
+#define BF_WDOG_STCTRLH_BYTESEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_BYTESEL), uint16_t) & BM_WDOG_STCTRLH_BYTESEL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the BYTESEL field to a new value.
+#define BW_WDOG_STCTRLH_BYTESEL(v) (HW_WDOG_STCTRLH_WR((HW_WDOG_STCTRLH_RD() & ~BM_WDOG_STCTRLH_BYTESEL) | BF_WDOG_STCTRLH_BYTESEL(v)))
+#endif
+//@}
+
+/*!
+ * @name Register WDOG_STCTRLH, field DISTESTWDOG[14] (RW)
+ *
+ * Allows the WDOG's functional test mode to be disabled permanently. After it
+ * is set, it can only be cleared by a reset. It cannot be unlocked for editing
+ * after it is set.
+ *
+ * Values:
+ * - 0 - WDOG functional test mode is not disabled.
+ * - 1 - WDOG functional test mode is disabled permanently until reset.
+ */
+//@{
+#define BP_WDOG_STCTRLH_DISTESTWDOG (14U) //!< Bit position for WDOG_STCTRLH_DISTESTWDOG.
+#define BM_WDOG_STCTRLH_DISTESTWDOG (0x4000U) //!< Bit mask for WDOG_STCTRLH_DISTESTWDOG.
+#define BS_WDOG_STCTRLH_DISTESTWDOG (1U) //!< Bit field size in bits for WDOG_STCTRLH_DISTESTWDOG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_STCTRLH_DISTESTWDOG field.
+#define BR_WDOG_STCTRLH_DISTESTWDOG (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_DISTESTWDOG))
+#endif
+
+//! @brief Format value for bitfield WDOG_STCTRLH_DISTESTWDOG.
+#define BF_WDOG_STCTRLH_DISTESTWDOG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLH_DISTESTWDOG), uint16_t) & BM_WDOG_STCTRLH_DISTESTWDOG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DISTESTWDOG field to a new value.
+#define BW_WDOG_STCTRLH_DISTESTWDOG(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR, BP_WDOG_STCTRLH_DISTESTWDOG) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_WDOG_STCTRLL - Watchdog Status and Control Register Low
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_WDOG_STCTRLL - Watchdog Status and Control Register Low (RW)
+ *
+ * Reset value: 0x0001U
+ */
+typedef union _hw_wdog_stctrll
+{
+ uint16_t U;
+ struct _hw_wdog_stctrll_bitfields
+ {
+ uint16_t RESERVED0 : 15; //!< [14:0]
+ uint16_t INTFLG : 1; //!< [15]
+ } B;
+} hw_wdog_stctrll_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire WDOG_STCTRLL register
+ */
+//@{
+#define HW_WDOG_STCTRLL_ADDR (REGS_WDOG_BASE + 0x2U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_WDOG_STCTRLL (*(__IO hw_wdog_stctrll_t *) HW_WDOG_STCTRLL_ADDR)
+#define HW_WDOG_STCTRLL_RD() (HW_WDOG_STCTRLL.U)
+#define HW_WDOG_STCTRLL_WR(v) (HW_WDOG_STCTRLL.U = (v))
+#define HW_WDOG_STCTRLL_SET(v) (HW_WDOG_STCTRLL_WR(HW_WDOG_STCTRLL_RD() | (v)))
+#define HW_WDOG_STCTRLL_CLR(v) (HW_WDOG_STCTRLL_WR(HW_WDOG_STCTRLL_RD() & ~(v)))
+#define HW_WDOG_STCTRLL_TOG(v) (HW_WDOG_STCTRLL_WR(HW_WDOG_STCTRLL_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual WDOG_STCTRLL bitfields
+ */
+
+/*!
+ * @name Register WDOG_STCTRLL, field INTFLG[15] (RW)
+ *
+ * Interrupt flag. It is set when an exception occurs. IRQRSTEN = 1 is a
+ * precondition to set this flag. INTFLG = 1 results in an interrupt being issued
+ * followed by a reset, WCT later. The interrupt can be cleared by writing 1 to this
+ * bit. It also gets cleared on a system reset.
+ */
+//@{
+#define BP_WDOG_STCTRLL_INTFLG (15U) //!< Bit position for WDOG_STCTRLL_INTFLG.
+#define BM_WDOG_STCTRLL_INTFLG (0x8000U) //!< Bit mask for WDOG_STCTRLL_INTFLG.
+#define BS_WDOG_STCTRLL_INTFLG (1U) //!< Bit field size in bits for WDOG_STCTRLL_INTFLG.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_STCTRLL_INTFLG field.
+#define BR_WDOG_STCTRLL_INTFLG (BITBAND_ACCESS16(HW_WDOG_STCTRLL_ADDR, BP_WDOG_STCTRLL_INTFLG))
+#endif
+
+//! @brief Format value for bitfield WDOG_STCTRLL_INTFLG.
+#define BF_WDOG_STCTRLL_INTFLG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_STCTRLL_INTFLG), uint16_t) & BM_WDOG_STCTRLL_INTFLG)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the INTFLG field to a new value.
+#define BW_WDOG_STCTRLL_INTFLG(v) (BITBAND_ACCESS16(HW_WDOG_STCTRLL_ADDR, BP_WDOG_STCTRLL_INTFLG) = (v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_WDOG_TOVALH - Watchdog Time-out Value Register High
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_WDOG_TOVALH - Watchdog Time-out Value Register High (RW)
+ *
+ * Reset value: 0x004CU
+ */
+typedef union _hw_wdog_tovalh
+{
+ uint16_t U;
+ struct _hw_wdog_tovalh_bitfields
+ {
+ uint16_t TOVALHIGH : 16; //!< [15:0]
+ } B;
+} hw_wdog_tovalh_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire WDOG_TOVALH register
+ */
+//@{
+#define HW_WDOG_TOVALH_ADDR (REGS_WDOG_BASE + 0x4U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_WDOG_TOVALH (*(__IO hw_wdog_tovalh_t *) HW_WDOG_TOVALH_ADDR)
+#define HW_WDOG_TOVALH_RD() (HW_WDOG_TOVALH.U)
+#define HW_WDOG_TOVALH_WR(v) (HW_WDOG_TOVALH.U = (v))
+#define HW_WDOG_TOVALH_SET(v) (HW_WDOG_TOVALH_WR(HW_WDOG_TOVALH_RD() | (v)))
+#define HW_WDOG_TOVALH_CLR(v) (HW_WDOG_TOVALH_WR(HW_WDOG_TOVALH_RD() & ~(v)))
+#define HW_WDOG_TOVALH_TOG(v) (HW_WDOG_TOVALH_WR(HW_WDOG_TOVALH_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual WDOG_TOVALH bitfields
+ */
+
+/*!
+ * @name Register WDOG_TOVALH, field TOVALHIGH[15:0] (RW)
+ *
+ * Defines the upper 16 bits of the 32-bit time-out value for the watchdog
+ * timer. It is defined in terms of cycles of the watchdog clock.
+ */
+//@{
+#define BP_WDOG_TOVALH_TOVALHIGH (0U) //!< Bit position for WDOG_TOVALH_TOVALHIGH.
+#define BM_WDOG_TOVALH_TOVALHIGH (0xFFFFU) //!< Bit mask for WDOG_TOVALH_TOVALHIGH.
+#define BS_WDOG_TOVALH_TOVALHIGH (16U) //!< Bit field size in bits for WDOG_TOVALH_TOVALHIGH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_TOVALH_TOVALHIGH field.
+#define BR_WDOG_TOVALH_TOVALHIGH (HW_WDOG_TOVALH.U)
+#endif
+
+//! @brief Format value for bitfield WDOG_TOVALH_TOVALHIGH.
+#define BF_WDOG_TOVALH_TOVALHIGH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_TOVALH_TOVALHIGH), uint16_t) & BM_WDOG_TOVALH_TOVALHIGH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TOVALHIGH field to a new value.
+#define BW_WDOG_TOVALH_TOVALHIGH(v) (HW_WDOG_TOVALH_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_WDOG_TOVALL - Watchdog Time-out Value Register Low
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_WDOG_TOVALL - Watchdog Time-out Value Register Low (RW)
+ *
+ * Reset value: 0x4B4CU
+ *
+ * The time-out value of the watchdog must be set to a minimum of four watchdog
+ * clock cycles. This is to take into account the delay in new settings taking
+ * effect in the watchdog clock domain.
+ */
+typedef union _hw_wdog_tovall
+{
+ uint16_t U;
+ struct _hw_wdog_tovall_bitfields
+ {
+ uint16_t TOVALLOW : 16; //!< [15:0]
+ } B;
+} hw_wdog_tovall_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire WDOG_TOVALL register
+ */
+//@{
+#define HW_WDOG_TOVALL_ADDR (REGS_WDOG_BASE + 0x6U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_WDOG_TOVALL (*(__IO hw_wdog_tovall_t *) HW_WDOG_TOVALL_ADDR)
+#define HW_WDOG_TOVALL_RD() (HW_WDOG_TOVALL.U)
+#define HW_WDOG_TOVALL_WR(v) (HW_WDOG_TOVALL.U = (v))
+#define HW_WDOG_TOVALL_SET(v) (HW_WDOG_TOVALL_WR(HW_WDOG_TOVALL_RD() | (v)))
+#define HW_WDOG_TOVALL_CLR(v) (HW_WDOG_TOVALL_WR(HW_WDOG_TOVALL_RD() & ~(v)))
+#define HW_WDOG_TOVALL_TOG(v) (HW_WDOG_TOVALL_WR(HW_WDOG_TOVALL_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual WDOG_TOVALL bitfields
+ */
+
+/*!
+ * @name Register WDOG_TOVALL, field TOVALLOW[15:0] (RW)
+ *
+ * Defines the lower 16 bits of the 32-bit time-out value for the watchdog
+ * timer. It is defined in terms of cycles of the watchdog clock.
+ */
+//@{
+#define BP_WDOG_TOVALL_TOVALLOW (0U) //!< Bit position for WDOG_TOVALL_TOVALLOW.
+#define BM_WDOG_TOVALL_TOVALLOW (0xFFFFU) //!< Bit mask for WDOG_TOVALL_TOVALLOW.
+#define BS_WDOG_TOVALL_TOVALLOW (16U) //!< Bit field size in bits for WDOG_TOVALL_TOVALLOW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_TOVALL_TOVALLOW field.
+#define BR_WDOG_TOVALL_TOVALLOW (HW_WDOG_TOVALL.U)
+#endif
+
+//! @brief Format value for bitfield WDOG_TOVALL_TOVALLOW.
+#define BF_WDOG_TOVALL_TOVALLOW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_TOVALL_TOVALLOW), uint16_t) & BM_WDOG_TOVALL_TOVALLOW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TOVALLOW field to a new value.
+#define BW_WDOG_TOVALL_TOVALLOW(v) (HW_WDOG_TOVALL_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_WDOG_WINH - Watchdog Window Register High
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_WDOG_WINH - Watchdog Window Register High (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * You must set the Window Register value lower than the Time-out Value Register.
+ */
+typedef union _hw_wdog_winh
+{
+ uint16_t U;
+ struct _hw_wdog_winh_bitfields
+ {
+ uint16_t WINHIGH : 16; //!< [15:0]
+ } B;
+} hw_wdog_winh_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire WDOG_WINH register
+ */
+//@{
+#define HW_WDOG_WINH_ADDR (REGS_WDOG_BASE + 0x8U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_WDOG_WINH (*(__IO hw_wdog_winh_t *) HW_WDOG_WINH_ADDR)
+#define HW_WDOG_WINH_RD() (HW_WDOG_WINH.U)
+#define HW_WDOG_WINH_WR(v) (HW_WDOG_WINH.U = (v))
+#define HW_WDOG_WINH_SET(v) (HW_WDOG_WINH_WR(HW_WDOG_WINH_RD() | (v)))
+#define HW_WDOG_WINH_CLR(v) (HW_WDOG_WINH_WR(HW_WDOG_WINH_RD() & ~(v)))
+#define HW_WDOG_WINH_TOG(v) (HW_WDOG_WINH_WR(HW_WDOG_WINH_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual WDOG_WINH bitfields
+ */
+
+/*!
+ * @name Register WDOG_WINH, field WINHIGH[15:0] (RW)
+ *
+ * Defines the upper 16 bits of the 32-bit window for the windowed mode of
+ * operation of the watchdog. It is defined in terms of cycles of the watchdog clock.
+ * In this mode, the watchdog can be refreshed only when the timer has reached a
+ * value greater than or equal to this window length. A refresh outside this
+ * window resets the system or if IRQRSTEN is set, it interrupts and then resets the
+ * system.
+ */
+//@{
+#define BP_WDOG_WINH_WINHIGH (0U) //!< Bit position for WDOG_WINH_WINHIGH.
+#define BM_WDOG_WINH_WINHIGH (0xFFFFU) //!< Bit mask for WDOG_WINH_WINHIGH.
+#define BS_WDOG_WINH_WINHIGH (16U) //!< Bit field size in bits for WDOG_WINH_WINHIGH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_WINH_WINHIGH field.
+#define BR_WDOG_WINH_WINHIGH (HW_WDOG_WINH.U)
+#endif
+
+//! @brief Format value for bitfield WDOG_WINH_WINHIGH.
+#define BF_WDOG_WINH_WINHIGH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_WINH_WINHIGH), uint16_t) & BM_WDOG_WINH_WINHIGH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WINHIGH field to a new value.
+#define BW_WDOG_WINH_WINHIGH(v) (HW_WDOG_WINH_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_WDOG_WINL - Watchdog Window Register Low
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_WDOG_WINL - Watchdog Window Register Low (RW)
+ *
+ * Reset value: 0x0010U
+ *
+ * You must set the Window Register value lower than the Time-out Value Register.
+ */
+typedef union _hw_wdog_winl
+{
+ uint16_t U;
+ struct _hw_wdog_winl_bitfields
+ {
+ uint16_t WINLOW : 16; //!< [15:0]
+ } B;
+} hw_wdog_winl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire WDOG_WINL register
+ */
+//@{
+#define HW_WDOG_WINL_ADDR (REGS_WDOG_BASE + 0xAU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_WDOG_WINL (*(__IO hw_wdog_winl_t *) HW_WDOG_WINL_ADDR)
+#define HW_WDOG_WINL_RD() (HW_WDOG_WINL.U)
+#define HW_WDOG_WINL_WR(v) (HW_WDOG_WINL.U = (v))
+#define HW_WDOG_WINL_SET(v) (HW_WDOG_WINL_WR(HW_WDOG_WINL_RD() | (v)))
+#define HW_WDOG_WINL_CLR(v) (HW_WDOG_WINL_WR(HW_WDOG_WINL_RD() & ~(v)))
+#define HW_WDOG_WINL_TOG(v) (HW_WDOG_WINL_WR(HW_WDOG_WINL_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual WDOG_WINL bitfields
+ */
+
+/*!
+ * @name Register WDOG_WINL, field WINLOW[15:0] (RW)
+ *
+ * Defines the lower 16 bits of the 32-bit window for the windowed mode of
+ * operation of the watchdog. It is defined in terms of cycles of the pre-scaled
+ * watchdog clock. In this mode, the watchdog can be refreshed only when the timer
+ * reaches a value greater than or equal to this window length value. A refresh
+ * outside of this window resets the system or if IRQRSTEN is set, it interrupts and
+ * then resets the system.
+ */
+//@{
+#define BP_WDOG_WINL_WINLOW (0U) //!< Bit position for WDOG_WINL_WINLOW.
+#define BM_WDOG_WINL_WINLOW (0xFFFFU) //!< Bit mask for WDOG_WINL_WINLOW.
+#define BS_WDOG_WINL_WINLOW (16U) //!< Bit field size in bits for WDOG_WINL_WINLOW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_WINL_WINLOW field.
+#define BR_WDOG_WINL_WINLOW (HW_WDOG_WINL.U)
+#endif
+
+//! @brief Format value for bitfield WDOG_WINL_WINLOW.
+#define BF_WDOG_WINL_WINLOW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_WINL_WINLOW), uint16_t) & BM_WDOG_WINL_WINLOW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WINLOW field to a new value.
+#define BW_WDOG_WINL_WINLOW(v) (HW_WDOG_WINL_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_WDOG_REFRESH - Watchdog Refresh register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_WDOG_REFRESH - Watchdog Refresh register (RW)
+ *
+ * Reset value: 0xB480U
+ */
+typedef union _hw_wdog_refresh
+{
+ uint16_t U;
+ struct _hw_wdog_refresh_bitfields
+ {
+ uint16_t WDOGREFRESH : 16; //!< [15:0]
+ } B;
+} hw_wdog_refresh_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire WDOG_REFRESH register
+ */
+//@{
+#define HW_WDOG_REFRESH_ADDR (REGS_WDOG_BASE + 0xCU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_WDOG_REFRESH (*(__IO hw_wdog_refresh_t *) HW_WDOG_REFRESH_ADDR)
+#define HW_WDOG_REFRESH_RD() (HW_WDOG_REFRESH.U)
+#define HW_WDOG_REFRESH_WR(v) (HW_WDOG_REFRESH.U = (v))
+#define HW_WDOG_REFRESH_SET(v) (HW_WDOG_REFRESH_WR(HW_WDOG_REFRESH_RD() | (v)))
+#define HW_WDOG_REFRESH_CLR(v) (HW_WDOG_REFRESH_WR(HW_WDOG_REFRESH_RD() & ~(v)))
+#define HW_WDOG_REFRESH_TOG(v) (HW_WDOG_REFRESH_WR(HW_WDOG_REFRESH_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual WDOG_REFRESH bitfields
+ */
+
+/*!
+ * @name Register WDOG_REFRESH, field WDOGREFRESH[15:0] (RW)
+ *
+ * Watchdog refresh register. A sequence of 0xA602 followed by 0xB480 within 20
+ * bus clock cycles written to this register refreshes the WDOG and prevents it
+ * from resetting the system. Writing a value other than the above mentioned
+ * sequence or if the sequence is longer than 20 bus cycles, resets the system, or if
+ * IRQRSTEN is set, it interrupts and then resets the system.
+ */
+//@{
+#define BP_WDOG_REFRESH_WDOGREFRESH (0U) //!< Bit position for WDOG_REFRESH_WDOGREFRESH.
+#define BM_WDOG_REFRESH_WDOGREFRESH (0xFFFFU) //!< Bit mask for WDOG_REFRESH_WDOGREFRESH.
+#define BS_WDOG_REFRESH_WDOGREFRESH (16U) //!< Bit field size in bits for WDOG_REFRESH_WDOGREFRESH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_REFRESH_WDOGREFRESH field.
+#define BR_WDOG_REFRESH_WDOGREFRESH (HW_WDOG_REFRESH.U)
+#endif
+
+//! @brief Format value for bitfield WDOG_REFRESH_WDOGREFRESH.
+#define BF_WDOG_REFRESH_WDOGREFRESH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_REFRESH_WDOGREFRESH), uint16_t) & BM_WDOG_REFRESH_WDOGREFRESH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WDOGREFRESH field to a new value.
+#define BW_WDOG_REFRESH_WDOGREFRESH(v) (HW_WDOG_REFRESH_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_WDOG_UNLOCK - Watchdog Unlock register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_WDOG_UNLOCK - Watchdog Unlock register (RW)
+ *
+ * Reset value: 0xD928U
+ */
+typedef union _hw_wdog_unlock
+{
+ uint16_t U;
+ struct _hw_wdog_unlock_bitfields
+ {
+ uint16_t WDOGUNLOCK : 16; //!< [15:0]
+ } B;
+} hw_wdog_unlock_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire WDOG_UNLOCK register
+ */
+//@{
+#define HW_WDOG_UNLOCK_ADDR (REGS_WDOG_BASE + 0xEU)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_WDOG_UNLOCK (*(__IO hw_wdog_unlock_t *) HW_WDOG_UNLOCK_ADDR)
+#define HW_WDOG_UNLOCK_RD() (HW_WDOG_UNLOCK.U)
+#define HW_WDOG_UNLOCK_WR(v) (HW_WDOG_UNLOCK.U = (v))
+#define HW_WDOG_UNLOCK_SET(v) (HW_WDOG_UNLOCK_WR(HW_WDOG_UNLOCK_RD() | (v)))
+#define HW_WDOG_UNLOCK_CLR(v) (HW_WDOG_UNLOCK_WR(HW_WDOG_UNLOCK_RD() & ~(v)))
+#define HW_WDOG_UNLOCK_TOG(v) (HW_WDOG_UNLOCK_WR(HW_WDOG_UNLOCK_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual WDOG_UNLOCK bitfields
+ */
+
+/*!
+ * @name Register WDOG_UNLOCK, field WDOGUNLOCK[15:0] (RW)
+ *
+ * Writing the unlock sequence values to this register to makes the watchdog
+ * write-once registers writable again. The required unlock sequence is 0xC520
+ * followed by 0xD928 within 20 bus clock cycles. A valid unlock sequence opens a
+ * window equal in length to the WCT within which you can update the registers.
+ * Writing a value other than the above mentioned sequence or if the sequence is
+ * longer than 20 bus cycles, resets the system or if IRQRSTEN is set, it interrupts
+ * and then resets the system. The unlock sequence is effective only if
+ * ALLOWUPDATE is set.
+ */
+//@{
+#define BP_WDOG_UNLOCK_WDOGUNLOCK (0U) //!< Bit position for WDOG_UNLOCK_WDOGUNLOCK.
+#define BM_WDOG_UNLOCK_WDOGUNLOCK (0xFFFFU) //!< Bit mask for WDOG_UNLOCK_WDOGUNLOCK.
+#define BS_WDOG_UNLOCK_WDOGUNLOCK (16U) //!< Bit field size in bits for WDOG_UNLOCK_WDOGUNLOCK.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_UNLOCK_WDOGUNLOCK field.
+#define BR_WDOG_UNLOCK_WDOGUNLOCK (HW_WDOG_UNLOCK.U)
+#endif
+
+//! @brief Format value for bitfield WDOG_UNLOCK_WDOGUNLOCK.
+#define BF_WDOG_UNLOCK_WDOGUNLOCK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_UNLOCK_WDOGUNLOCK), uint16_t) & BM_WDOG_UNLOCK_WDOGUNLOCK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WDOGUNLOCK field to a new value.
+#define BW_WDOG_UNLOCK_WDOGUNLOCK(v) (HW_WDOG_UNLOCK_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_WDOG_TMROUTH - Watchdog Timer Output Register High
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_WDOG_TMROUTH - Watchdog Timer Output Register High (RW)
+ *
+ * Reset value: 0x0000U
+ */
+typedef union _hw_wdog_tmrouth
+{
+ uint16_t U;
+ struct _hw_wdog_tmrouth_bitfields
+ {
+ uint16_t TIMEROUTHIGH : 16; //!< [15:0]
+ } B;
+} hw_wdog_tmrouth_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire WDOG_TMROUTH register
+ */
+//@{
+#define HW_WDOG_TMROUTH_ADDR (REGS_WDOG_BASE + 0x10U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_WDOG_TMROUTH (*(__IO hw_wdog_tmrouth_t *) HW_WDOG_TMROUTH_ADDR)
+#define HW_WDOG_TMROUTH_RD() (HW_WDOG_TMROUTH.U)
+#define HW_WDOG_TMROUTH_WR(v) (HW_WDOG_TMROUTH.U = (v))
+#define HW_WDOG_TMROUTH_SET(v) (HW_WDOG_TMROUTH_WR(HW_WDOG_TMROUTH_RD() | (v)))
+#define HW_WDOG_TMROUTH_CLR(v) (HW_WDOG_TMROUTH_WR(HW_WDOG_TMROUTH_RD() & ~(v)))
+#define HW_WDOG_TMROUTH_TOG(v) (HW_WDOG_TMROUTH_WR(HW_WDOG_TMROUTH_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual WDOG_TMROUTH bitfields
+ */
+
+/*!
+ * @name Register WDOG_TMROUTH, field TIMEROUTHIGH[15:0] (RW)
+ *
+ * Shows the value of the upper 16 bits of the watchdog timer.
+ */
+//@{
+#define BP_WDOG_TMROUTH_TIMEROUTHIGH (0U) //!< Bit position for WDOG_TMROUTH_TIMEROUTHIGH.
+#define BM_WDOG_TMROUTH_TIMEROUTHIGH (0xFFFFU) //!< Bit mask for WDOG_TMROUTH_TIMEROUTHIGH.
+#define BS_WDOG_TMROUTH_TIMEROUTHIGH (16U) //!< Bit field size in bits for WDOG_TMROUTH_TIMEROUTHIGH.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_TMROUTH_TIMEROUTHIGH field.
+#define BR_WDOG_TMROUTH_TIMEROUTHIGH (HW_WDOG_TMROUTH.U)
+#endif
+
+//! @brief Format value for bitfield WDOG_TMROUTH_TIMEROUTHIGH.
+#define BF_WDOG_TMROUTH_TIMEROUTHIGH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_TMROUTH_TIMEROUTHIGH), uint16_t) & BM_WDOG_TMROUTH_TIMEROUTHIGH)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TIMEROUTHIGH field to a new value.
+#define BW_WDOG_TMROUTH_TIMEROUTHIGH(v) (HW_WDOG_TMROUTH_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_WDOG_TMROUTL - Watchdog Timer Output Register Low
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_WDOG_TMROUTL - Watchdog Timer Output Register Low (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * During Stop mode, the WDOG_TIMER_OUT will be caught at the pre-stop value of
+ * the watchdog timer. After exiting Stop mode, a maximum delay of 1 WDOG_CLK
+ * cycle + 3 bus clock cycles will occur before the WDOG_TIMER_OUT starts following
+ * the watchdog timer.
+ */
+typedef union _hw_wdog_tmroutl
+{
+ uint16_t U;
+ struct _hw_wdog_tmroutl_bitfields
+ {
+ uint16_t TIMEROUTLOW : 16; //!< [15:0]
+ } B;
+} hw_wdog_tmroutl_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire WDOG_TMROUTL register
+ */
+//@{
+#define HW_WDOG_TMROUTL_ADDR (REGS_WDOG_BASE + 0x12U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_WDOG_TMROUTL (*(__IO hw_wdog_tmroutl_t *) HW_WDOG_TMROUTL_ADDR)
+#define HW_WDOG_TMROUTL_RD() (HW_WDOG_TMROUTL.U)
+#define HW_WDOG_TMROUTL_WR(v) (HW_WDOG_TMROUTL.U = (v))
+#define HW_WDOG_TMROUTL_SET(v) (HW_WDOG_TMROUTL_WR(HW_WDOG_TMROUTL_RD() | (v)))
+#define HW_WDOG_TMROUTL_CLR(v) (HW_WDOG_TMROUTL_WR(HW_WDOG_TMROUTL_RD() & ~(v)))
+#define HW_WDOG_TMROUTL_TOG(v) (HW_WDOG_TMROUTL_WR(HW_WDOG_TMROUTL_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual WDOG_TMROUTL bitfields
+ */
+
+/*!
+ * @name Register WDOG_TMROUTL, field TIMEROUTLOW[15:0] (RW)
+ *
+ * Shows the value of the lower 16 bits of the watchdog timer.
+ */
+//@{
+#define BP_WDOG_TMROUTL_TIMEROUTLOW (0U) //!< Bit position for WDOG_TMROUTL_TIMEROUTLOW.
+#define BM_WDOG_TMROUTL_TIMEROUTLOW (0xFFFFU) //!< Bit mask for WDOG_TMROUTL_TIMEROUTLOW.
+#define BS_WDOG_TMROUTL_TIMEROUTLOW (16U) //!< Bit field size in bits for WDOG_TMROUTL_TIMEROUTLOW.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_TMROUTL_TIMEROUTLOW field.
+#define BR_WDOG_TMROUTL_TIMEROUTLOW (HW_WDOG_TMROUTL.U)
+#endif
+
+//! @brief Format value for bitfield WDOG_TMROUTL_TIMEROUTLOW.
+#define BF_WDOG_TMROUTL_TIMEROUTLOW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_TMROUTL_TIMEROUTLOW), uint16_t) & BM_WDOG_TMROUTL_TIMEROUTLOW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TIMEROUTLOW field to a new value.
+#define BW_WDOG_TMROUTL_TIMEROUTLOW(v) (HW_WDOG_TMROUTL_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_WDOG_RSTCNT - Watchdog Reset Count register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_WDOG_RSTCNT - Watchdog Reset Count register (RW)
+ *
+ * Reset value: 0x0000U
+ */
+typedef union _hw_wdog_rstcnt
+{
+ uint16_t U;
+ struct _hw_wdog_rstcnt_bitfields
+ {
+ uint16_t RSTCNT : 16; //!< [15:0]
+ } B;
+} hw_wdog_rstcnt_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire WDOG_RSTCNT register
+ */
+//@{
+#define HW_WDOG_RSTCNT_ADDR (REGS_WDOG_BASE + 0x14U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_WDOG_RSTCNT (*(__IO hw_wdog_rstcnt_t *) HW_WDOG_RSTCNT_ADDR)
+#define HW_WDOG_RSTCNT_RD() (HW_WDOG_RSTCNT.U)
+#define HW_WDOG_RSTCNT_WR(v) (HW_WDOG_RSTCNT.U = (v))
+#define HW_WDOG_RSTCNT_SET(v) (HW_WDOG_RSTCNT_WR(HW_WDOG_RSTCNT_RD() | (v)))
+#define HW_WDOG_RSTCNT_CLR(v) (HW_WDOG_RSTCNT_WR(HW_WDOG_RSTCNT_RD() & ~(v)))
+#define HW_WDOG_RSTCNT_TOG(v) (HW_WDOG_RSTCNT_WR(HW_WDOG_RSTCNT_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual WDOG_RSTCNT bitfields
+ */
+
+/*!
+ * @name Register WDOG_RSTCNT, field RSTCNT[15:0] (RW)
+ *
+ * Counts the number of times the watchdog resets the system. This register is
+ * reset only on a POR. Writing 1 to the bit to be cleared enables you to clear
+ * the contents of this register.
+ */
+//@{
+#define BP_WDOG_RSTCNT_RSTCNT (0U) //!< Bit position for WDOG_RSTCNT_RSTCNT.
+#define BM_WDOG_RSTCNT_RSTCNT (0xFFFFU) //!< Bit mask for WDOG_RSTCNT_RSTCNT.
+#define BS_WDOG_RSTCNT_RSTCNT (16U) //!< Bit field size in bits for WDOG_RSTCNT_RSTCNT.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_RSTCNT_RSTCNT field.
+#define BR_WDOG_RSTCNT_RSTCNT (HW_WDOG_RSTCNT.U)
+#endif
+
+//! @brief Format value for bitfield WDOG_RSTCNT_RSTCNT.
+#define BF_WDOG_RSTCNT_RSTCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_RSTCNT_RSTCNT), uint16_t) & BM_WDOG_RSTCNT_RSTCNT)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RSTCNT field to a new value.
+#define BW_WDOG_RSTCNT_RSTCNT(v) (HW_WDOG_RSTCNT_WR(v))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_WDOG_PRESC - Watchdog Prescaler register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_WDOG_PRESC - Watchdog Prescaler register (RW)
+ *
+ * Reset value: 0x0400U
+ */
+typedef union _hw_wdog_presc
+{
+ uint16_t U;
+ struct _hw_wdog_presc_bitfields
+ {
+ uint16_t RESERVED0 : 8; //!< [7:0]
+ uint16_t PRESCVAL : 3; //!< [10:8]
+ uint16_t RESERVED1 : 5; //!< [15:11]
+ } B;
+} hw_wdog_presc_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire WDOG_PRESC register
+ */
+//@{
+#define HW_WDOG_PRESC_ADDR (REGS_WDOG_BASE + 0x16U)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_WDOG_PRESC (*(__IO hw_wdog_presc_t *) HW_WDOG_PRESC_ADDR)
+#define HW_WDOG_PRESC_RD() (HW_WDOG_PRESC.U)
+#define HW_WDOG_PRESC_WR(v) (HW_WDOG_PRESC.U = (v))
+#define HW_WDOG_PRESC_SET(v) (HW_WDOG_PRESC_WR(HW_WDOG_PRESC_RD() | (v)))
+#define HW_WDOG_PRESC_CLR(v) (HW_WDOG_PRESC_WR(HW_WDOG_PRESC_RD() & ~(v)))
+#define HW_WDOG_PRESC_TOG(v) (HW_WDOG_PRESC_WR(HW_WDOG_PRESC_RD() ^ (v)))
+#endif
+//@}
+
+/*
+ * Constants & macros for individual WDOG_PRESC bitfields
+ */
+
+/*!
+ * @name Register WDOG_PRESC, field PRESCVAL[10:8] (RW)
+ *
+ * 3-bit prescaler for the watchdog clock source. A value of zero indicates no
+ * division of the input WDOG clock. The watchdog clock is divided by (PRESCVAL +
+ * 1) to provide the prescaled WDOG_CLK.
+ */
+//@{
+#define BP_WDOG_PRESC_PRESCVAL (8U) //!< Bit position for WDOG_PRESC_PRESCVAL.
+#define BM_WDOG_PRESC_PRESCVAL (0x0700U) //!< Bit mask for WDOG_PRESC_PRESCVAL.
+#define BS_WDOG_PRESC_PRESCVAL (3U) //!< Bit field size in bits for WDOG_PRESC_PRESCVAL.
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Read current value of the WDOG_PRESC_PRESCVAL field.
+#define BR_WDOG_PRESC_PRESCVAL (HW_WDOG_PRESC.B.PRESCVAL)
+#endif
+
+//! @brief Format value for bitfield WDOG_PRESC_PRESCVAL.
+#define BF_WDOG_PRESC_PRESCVAL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_WDOG_PRESC_PRESCVAL), uint16_t) & BM_WDOG_PRESC_PRESCVAL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PRESCVAL field to a new value.
+#define BW_WDOG_PRESC_PRESCVAL(v) (HW_WDOG_PRESC_WR((HW_WDOG_PRESC_RD() & ~BM_WDOG_PRESC_PRESCVAL) | BF_WDOG_PRESC_PRESCVAL(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_wdog_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All WDOG module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_wdog
+{
+ __IO hw_wdog_stctrlh_t STCTRLH; //!< [0x0] Watchdog Status and Control Register High
+ __IO hw_wdog_stctrll_t STCTRLL; //!< [0x2] Watchdog Status and Control Register Low
+ __IO hw_wdog_tovalh_t TOVALH; //!< [0x4] Watchdog Time-out Value Register High
+ __IO hw_wdog_tovall_t TOVALL; //!< [0x6] Watchdog Time-out Value Register Low
+ __IO hw_wdog_winh_t WINH; //!< [0x8] Watchdog Window Register High
+ __IO hw_wdog_winl_t WINL; //!< [0xA] Watchdog Window Register Low
+ __IO hw_wdog_refresh_t REFRESH; //!< [0xC] Watchdog Refresh register
+ __IO hw_wdog_unlock_t UNLOCK; //!< [0xE] Watchdog Unlock register
+ __IO hw_wdog_tmrouth_t TMROUTH; //!< [0x10] Watchdog Timer Output Register High
+ __IO hw_wdog_tmroutl_t TMROUTL; //!< [0x12] Watchdog Timer Output Register Low
+ __IO hw_wdog_rstcnt_t RSTCNT; //!< [0x14] Watchdog Reset Count register
+ __IO hw_wdog_presc_t PRESC; //!< [0x16] Watchdog Prescaler register
+} hw_wdog_t;
+#pragma pack()
+
+//! @brief Macro to access all WDOG registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//! use the '&' operator, like <code>&HW_WDOG</code>.
+#define HW_WDOG (*(hw_wdog_t *) REGS_WDOG_BASE)
+#endif
+
+#endif // __HW_WDOG_REGISTERS_H__
+// v22/130726/0.9
+// EOF
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/regs.h Fri Sep 12 16:41:52 2014 +0100 @@ -0,0 +1,525 @@ +/* + * Copyright (c) 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + */ + +#ifndef _REGS_H +#define _REGS_H 1 + +#include <stdint.h> +#include <stdlib.h> + +// +// define base address of the register block only if it is not already +// defined, which allows the compiler to override at build time for +// users who've mapped their registers to locations other than the +// physical location +// + +#include <stdint.h> + +#ifndef REGS_BASE +#define REGS_BASE 0x00000000 +#endif + +// +// common register types +// + +#ifndef __LANGUAGE_ASM__ +typedef unsigned char reg8_t; +typedef unsigned short reg16_t; +typedef unsigned int reg32_t; +#endif + +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +#define BME_AND_MASK (1<<26) +#define BME_OR_MASK (1<<27) +#define BME_XOR_MASK (3<<26) +#define BME_BFI_MASK(BIT,WIDTH) (1<<28) | (BIT<<23) | ((WIDTH-1)<<19) +#define BME_UBFX_MASK(BIT,WIDTH) (1<<28) | (BIT<<23) | ((WIDTH-1)<<19) + +/** + * @brief Macro to access a single bit of a 32-bit peripheral register (bit band region + * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. + * @param Reg Register to access. + * @param Bit Bit number to access. + * @return Value of the targeted bit in the bit band region. + */ +#define BITBAND_ACCESS32(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))))) + +/** + * @brief Macro to access a single bit of a 16-bit peripheral register (bit band region + * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. + * @param Reg Register to access. + * @param Bit Bit number to access. + * @return Value of the targeted bit in the bit band region. + */ +#define BITBAND_ACCESS16(Reg,Bit) (*((uint16_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))))) + +/** + * @brief Macro to access a single bit of an 8-bit peripheral register (bit band region + * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. + * @param Reg Register to access. + * @param Bit Bit number to access. + * @return Value of the targeted bit in the bit band region. + */ +#define BITBAND_ACCESS8(Reg,Bit) (*((uint8_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))))) + +// +// Typecast macro for C or asm. In C, the cast is applied, while in asm it is excluded. This is +// used to simplify macro definitions in the module register headers. +// +#ifndef __REG_VALUE_TYPE + #ifndef __LANGUAGE_ASM__ + #define __REG_VALUE_TYPE(v, t) ((t)(v)) + #else + #define __REG_VALUE_TYPE(v, t) (v) + #endif +#endif + +// +// macros for single instance registers +// + +#define BF_SET(reg, field) HW_##reg##_SET(BM_##reg##_##field) +#define BF_CLR(reg, field) HW_##reg##_CLR(BM_##reg##_##field) +#define BF_TOG(reg, field) HW_##reg##_TOG(BM_##reg##_##field) + +#define BF_SETV(reg, field, v) HW_##reg##_SET(BF_##reg##_##field(v)) +#define BF_CLRV(reg, field, v) HW_##reg##_CLR(BF_##reg##_##field(v)) +#define BF_TOGV(reg, field, v) HW_##reg##_TOG(BF_##reg##_##field(v)) + +#define BV_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) +#define BV_VAL(reg, field, sym) BV_##reg##_##field##__##sym + +#define BF_RD(reg, field) HW_##reg.B.field +#define BF_WR(reg, field, v) BW_##reg##_##field(v) + +#define BF_CS1(reg, f1, v1) \ + (HW_##reg##_CLR(BM_##reg##_##f1), \ + HW_##reg##_SET(BF_##reg##_##f1(v1))) + +#define BF_CS2(reg, f1, v1, f2, v2) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2))) + +#define BF_CS3(reg, f1, v1, f2, v2, f3, v3) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3))) + +#define BF_CS4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4))) + +#define BF_CS5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5))) + +#define BF_CS6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6))) + +#define BF_CS7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7))) + +#define BF_CS8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ + (HW_##reg##_CLR(BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7 | \ + BM_##reg##_##f8), \ + HW_##reg##_SET(BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7) | \ + BF_##reg##_##f8(v8))) + +// +// macros for multiple instance registers +// + +#define BF_SETn(reg, n, field) HW_##reg##_SET(n, BM_##reg##_##field) +#define BF_CLRn(reg, n, field) HW_##reg##_CLR(n, BM_##reg##_##field) +#define BF_TOGn(reg, n, field) HW_##reg##_TOG(n, BM_##reg##_##field) + +#define BF_SETVn(reg, n, field, v) HW_##reg##_SET(n, BF_##reg##_##field(v)) +#define BF_CLRVn(reg, n, field, v) HW_##reg##_CLR(n, BF_##reg##_##field(v)) +#define BF_TOGVn(reg, n, field, v) HW_##reg##_TOG(n, BF_##reg##_##field(v)) + +#define BV_FLDn(reg, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) +#define BV_VALn(reg, n, field, sym) BV_##reg##_##field##__##sym + +#define BF_RDn(reg, n, field) HW_##reg(n).B.field +#define BF_WRn(reg, n, field, v) BW_##reg##_##field(n, v) + +#define BF_CS1n(reg, n, f1, v1) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1)))) + +#define BF_CS2n(reg, n, f1, v1, f2, v2) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2)))) + +#define BF_CS3n(reg, n, f1, v1, f2, v2, f3, v3) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3)))) + +#define BF_CS4n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4)))) + +#define BF_CS5n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5)))) + +#define BF_CS6n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6)))) + +#define BF_CS7n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7)))) + +#define BF_CS8n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ + (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7 | \ + BM_##reg##_##f8)), \ + HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7) | \ + BF_##reg##_##f8(v8)))) + +// +// macros for single instance MULTI-BLOCK registers +// + +#define BFn_SET(reg, blk, field) HW_##reg##_SET(blk, BM_##reg##_##field) +#define BFn_CLR(reg, blk, field) HW_##reg##_CLR(blk, BM_##reg##_##field) +#define BFn_TOG(reg, blk, field) HW_##reg##_TOG(blk, BM_##reg##_##field) + +#define BFn_SETV(reg, blk, field, v) HW_##reg##_SET(blk, BF_##reg##_##field(v)) +#define BFn_CLRV(reg, blk, field, v) HW_##reg##_CLR(blk, BF_##reg##_##field(v)) +#define BFn_TOGV(reg, blk, field, v) HW_##reg##_TOG(blk, BF_##reg##_##field(v)) + +#define BVn_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) +#define BVn_VAL(reg, field, sym) BV_##reg##_##field##__##sym + +#define BFn_RD(reg, blk, field) HW_##reg(blk).B.field +#define BFn_WR(reg, blk, field, v) BW_##reg##_##field(blk, v) + +#define BFn_CS1(reg, blk, f1, v1) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1))) + +#define BFn_CS2(reg, blk, f1, v1, f2, v2) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2))) + +#define BFn_CS3(reg, blk, f1, v1, f2, v2, f3, v3) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3))) + +#define BFn_CS4(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4))) + +#define BFn_CS5(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5))) + +#define BFn_CS6(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6))) + +#define BFn_CS7(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7))) + +#define BFn_CS8(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ + (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7 | \ + BM_##reg##_##f8), \ + HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7) | \ + BF_##reg##_##f8(v8))) + +// +// macros for MULTI-BLOCK multiple instance registers +// + +#define BFn_SETn(reg, blk, n, field) HW_##reg##_SET(blk, n, BM_##reg##_##field) +#define BFn_CLRn(reg, blk, n, field) HW_##reg##_CLR(blk, n, BM_##reg##_##field) +#define BFn_TOGn(reg, blk, n, field) HW_##reg##_TOG(blk, n, BM_##reg##_##field) + +#define BFn_SETVn(reg, blk, n, field, v) HW_##reg##_SET(blk, n, BF_##reg##_##field(v)) +#define BFn_CLRVn(reg, blk, n, field, v) HW_##reg##_CLR(blk, n, BF_##reg##_##field(v)) +#define BFn_TOGVn(reg, blk, n, field, v) HW_##reg##_TOG(blk, n, BF_##reg##_##field(v)) + +#define BVn_FLDn(reg, blk, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) +#define BVn_VALn(reg, blk, n, field, sym) BV_##reg##_##field##__##sym + +#define BFn_RDn(reg, blk, n, field) HW_##reg(n).B.field +#define BFn_WRn(reg, blk, n, field, v) BW_##reg##_##field(n, v) + +#define BFn_CS1n(reg, blk, n, f1, v1) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1)))) + +#define BFn_CS2n(reg, blk, n, f1, v1, f2, v2) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2)))) + +#define BFn_CS3n(reg, blk, n, f1, v1, f2, v2, f3, v3) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3)))) + +#define BFn_CS4n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4)))) + +#define BFn_CS5n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5)))) + +#define BFn_CS6n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6)))) + +#define BFn_CS7n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7)))) + +#define BFn_CS8n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ + (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ + BM_##reg##_##f2 | \ + BM_##reg##_##f3 | \ + BM_##reg##_##f4 | \ + BM_##reg##_##f5 | \ + BM_##reg##_##f6 | \ + BM_##reg##_##f7 | \ + BM_##reg##_##f8)), \ + HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ + BF_##reg##_##f2(v2) | \ + BF_##reg##_##f3(v3) | \ + BF_##reg##_##f4(v4) | \ + BF_##reg##_##f5(v5) | \ + BF_##reg##_##f6(v6) | \ + BF_##reg##_##f7(v7) | \ + BF_##reg##_##f8(v8)))) + +#endif // _REGS_H + +////////////////////////////////////////////////////////////////////////////////
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/system_MK64F12.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,169 @@
+/*
+** ###################################################################
+** Processor: MK64FN1M0VMD12
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** GNU C Compiler - CodeSourcery Sourcery G++
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
+** Version: rev. 2.3, 2014-01-24
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright: 2014 Freescale, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2013-08-12)
+** Initial version.
+** - rev. 2.0 (2013-10-29)
+** Register accessor macros added to the memory map.
+** Symbols for Processor Expert memory map compatibility added to the memory map.
+** Startup file for gcc has been updated according to CMSIS 3.2.
+** System initialization updated.
+** MCG - registers updated.
+** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+** - rev. 2.1 (2013-10-29)
+** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+** - rev. 2.2 (2013-12-09)
+** DMA - EARS register removed.
+** AIPS0, AIPS1 - MPRA register updated.
+** - rev. 2.3 (2014-01-24)
+** Update according to reference manual rev. 2
+** ENET, MCG, MCM, SIM, USB - registers updated
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK64F12
+ * @version 2.3
+ * @date 2014-01-24
+ * @brief Device specific configuration file for MK64F12 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MK64F12_H_
+#define SYSTEM_MK64F12_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#define DISABLE_WDOG 1
+
+#ifndef CLOCK_SETUP
+#define CLOCK_SETUP 4
+#endif
+/* Predefined clock setups
+ 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
+ Default part configuration.
+ Reference clock source for MCG module is the slow internal clock source 32.768kHz
+ Core clock = 20.97MHz, BusClock = 20.97MHz
+ 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
+ Maximum achievable clock frequency configuration.
+ Reference clock source for MCG module is an external clock source 50MHz
+ Core clock = 120MHz, BusClock = 60MHz
+ 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power Internal (BLPI) mode
+ Core clock/Bus clock derived directly from an fast internal clock 4MHz with no multiplication
+ The clock settings is ready for Very Low Power Run mode.
+ Core clock = 4MHz, BusClock = 4MHz
+ 3 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
+ Core clock/Bus clock derived directly from the RTC oscillator clock source 32.768kHz
+ The clock settings is ready for Very Low Power Run mode.
+ Core clock = 32.768kHz, BusClock = 32.768kHz
+ 4 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
+ USB clock setup
+ USB clock divider is set for USB to receive 48MHz input clock.
+ Reference clock source for MCG module is an external clock source 50MHz
+ USB clock divider is set for USB to receive 48MHz input clock.
+ Core clock = 120MHz, BusClock = 60MHz
+*/
+
+/*----------------------------------------------------------------------------
+ Define clock source values
+ *----------------------------------------------------------------------------*/
+#if (CLOCK_SETUP == 0)
+ #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 20485760u /* Default System clock value */
+#elif (CLOCK_SETUP == 1)
+ #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
+#elif (CLOCK_SETUP == 2)
+ #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
+#elif (CLOCK_SETUP == 3)
+ #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 32768u /* Default System clock value */
+#elif (CLOCK_SETUP == 4)
+ #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
+#endif /* (CLOCK_SETUP == 4) */
+
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #if !defined(SYSTEM_MK64F12_H_) */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/fsl_device_registers.h Fri Sep 12 16:41:52 2014 +0100 @@ -0,0 +1,572 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MK22FN512VDC12)) + #define K22F51212_SERIES + /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/ + #include "device/MK22F51212/MK22F51212_adc.h" + #include "device/MK22F51212/MK22F51212_aips.h" + #include "device/MK22F51212/MK22F51212_cmp.h" + #include "device/MK22F51212/MK22F51212_crc.h" + #include "device/MK22F51212/MK22F51212_dac.h" + #include "device/MK22F51212/MK22F51212_dma.h" + #include "device/MK22F51212/MK22F51212_dmamux.h" + #include "device/MK22F51212/MK22F51212_ewm.h" + #include "device/MK22F51212/MK22F51212_fb.h" + #include "device/MK22F51212/MK22F51212_fmc.h" + #include "device/MK22F51212/MK22F51212_ftfa.h" + #include "device/MK22F51212/MK22F51212_ftm.h" + #include "device/MK22F51212/MK22F51212_gpio.h" + #include "device/MK22F51212/MK22F51212_i2c.h" + #include "device/MK22F51212/MK22F51212_i2s.h" + #include "device/MK22F51212/MK22F51212_llwu.h" + #include "device/MK22F51212/MK22F51212_lptmr.h" + #include "device/MK22F51212/MK22F51212_mcg.h" + #include "device/MK22F51212/MK22F51212_mcm.h" + #include "device/MK22F51212/MK22F51212_nv.h" + #include "device/MK22F51212/MK22F51212_osc.h" + #include "device/MK22F51212/MK22F51212_pdb.h" + #include "device/MK22F51212/MK22F51212_pit.h" + #include "device/MK22F51212/MK22F51212_pmc.h" + #include "device/MK22F51212/MK22F51212_port.h" + #include "device/MK22F51212/MK22F51212_rcm.h" + #include "device/MK22F51212/MK22F51212_rfsys.h" + #include "device/MK22F51212/MK22F51212_rfvbat.h" + #include "device/MK22F51212/MK22F51212_rng.h" + #include "device/MK22F51212/MK22F51212_rtc.h" + #include "device/MK22F51212/MK22F51212_sim.h" + #include "device/MK22F51212/MK22F51212_smc.h" + #include "device/MK22F51212/MK22F51212_spi.h" + #include "device/MK22F51212/MK22F51212_uart.h" + #include "device/MK22F51212/MK22F51212_usb.h" + #include "device/MK22F51212/MK22F51212_vref.h" + #include "device/MK22F51212/MK22F51212_wdog.h" + + /* CMSIS-style register definitions*/ + #include "device/MK22F51212/MK22F51212.h" + +#elif (defined(CPU_MK24FN1M0VLQ12)) + /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/ + #include "device/MK24F12/MK24F12_adc.h" + #include "device/MK24F12/MK24F12_aips.h" + #include "device/MK24F12/MK24F12_axbs.h" + #include "device/MK24F12/MK24F12_can.h" + #include "device/MK24F12/MK24F12_cau.h" + #include "device/MK24F12/MK24F12_cmp.h" + #include "device/MK24F12/MK24F12_cmt.h" + #include "device/MK24F12/MK24F12_crc.h" + #include "device/MK24F12/MK24F12_dac.h" + #include "device/MK24F12/MK24F12_dma.h" + #include "device/MK24F12/MK24F12_dmamux.h" + #include "device/MK24F12/MK24F12_ewm.h" + #include "device/MK24F12/MK24F12_fb.h" + #include "device/MK24F12/MK24F12_fmc.h" + #include "device/MK24F12/MK24F12_ftfe.h" + #include "device/MK24F12/MK24F12_ftm.h" + #include "device/MK24F12/MK24F12_gpio.h" + #include "device/MK24F12/MK24F12_i2c.h" + #include "device/MK24F12/MK24F12_i2s.h" + #include "device/MK24F12/MK24F12_llwu.h" + #include "device/MK24F12/MK24F12_lptmr.h" + #include "device/MK24F12/MK24F12_mcg.h" + #include "device/MK24F12/MK24F12_mcm.h" + #include "device/MK24F12/MK24F12_mpu.h" + #include "device/MK24F12/MK24F12_nv.h" + #include "device/MK24F12/MK24F12_osc.h" + #include "device/MK24F12/MK24F12_pdb.h" + #include "device/MK24F12/MK24F12_pit.h" + #include "device/MK24F12/MK24F12_pmc.h" + #include "device/MK24F12/MK24F12_port.h" + #include "device/MK24F12/MK24F12_rcm.h" + #include "device/MK24F12/MK24F12_rfsys.h" + #include "device/MK24F12/MK24F12_rfvbat.h" + #include "device/MK24F12/MK24F12_rng.h" + #include "device/MK24F12/MK24F12_rtc.h" + #include "device/MK24F12/MK24F12_sdhc.h" + #include "device/MK24F12/MK24F12_sim.h" + #include "device/MK24F12/MK24F12_smc.h" + #include "device/MK24F12/MK24F12_spi.h" + #include "device/MK24F12/MK24F12_uart.h" + #include "device/MK24F12/MK24F12_usb.h" + #include "device/MK24F12/MK24F12_usbdcd.h" + #include "device/MK24F12/MK24F12_vref.h" + #include "device/MK24F12/MK24F12_wdog.h" + + /* CMSIS-style register definitions*/ + #include "device/MK24F12/MK24F12.h" + +#elif (defined(CPU_MK63FN1M0VMD12)) + /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/ + #include "device/MK63F12/MK63F12_adc.h" + #include "device/MK63F12/MK63F12_aips.h" + #include "device/MK63F12/MK63F12_axbs.h" + #include "device/MK63F12/MK63F12_can.h" + #include "device/MK63F12/MK63F12_cau.h" + #include "device/MK63F12/MK63F12_cmp.h" + #include "device/MK63F12/MK63F12_cmt.h" + #include "device/MK63F12/MK63F12_crc.h" + #include "device/MK63F12/MK63F12_dac.h" + #include "device/MK63F12/MK63F12_dma.h" + #include "device/MK63F12/MK63F12_dmamux.h" + #include "device/MK63F12/MK63F12_enet.h" + #include "device/MK63F12/MK63F12_ewm.h" + #include "device/MK63F12/MK63F12_fb.h" + #include "device/MK63F12/MK63F12_fmc.h" + #include "device/MK63F12/MK63F12_ftfe.h" + #include "device/MK63F12/MK63F12_ftm.h" + #include "device/MK63F12/MK63F12_gpio.h" + #include "device/MK63F12/MK63F12_i2c.h" + #include "device/MK63F12/MK63F12_i2s.h" + #include "device/MK63F12/MK63F12_llwu.h" + #include "device/MK63F12/MK63F12_lptmr.h" + #include "device/MK63F12/MK63F12_mcg.h" + #include "device/MK63F12/MK63F12_mcm.h" + #include "device/MK63F12/MK63F12_mpu.h" + #include "device/MK63F12/MK63F12_nv.h" + #include "device/MK63F12/MK63F12_osc.h" + #include "device/MK63F12/MK63F12_pdb.h" + #include "device/MK63F12/MK63F12_pit.h" + #include "device/MK63F12/MK63F12_pmc.h" + #include "device/MK63F12/MK63F12_port.h" + #include "device/MK63F12/MK63F12_rcm.h" + #include "device/MK63F12/MK63F12_rfsys.h" + #include "device/MK63F12/MK63F12_rfvbat.h" + #include "device/MK63F12/MK63F12_rng.h" + #include "device/MK63F12/MK63F12_rtc.h" + #include "device/MK63F12/MK63F12_sdhc.h" + #include "device/MK63F12/MK63F12_sim.h" + #include "device/MK63F12/MK63F12_smc.h" + #include "device/MK63F12/MK63F12_spi.h" + #include "device/MK63F12/MK63F12_uart.h" + #include "device/MK63F12/MK63F12_usb.h" + #include "device/MK63F12/MK63F12_usbdcd.h" + #include "device/MK63F12/MK63F12_vref.h" + #include "device/MK63F12/MK63F12_wdog.h" + + /* CMSIS-style register definitions*/ + #include "device/MK63F12/MK63F12.h" + +#elif (defined(CPU_MK63FN1M0VMD12WS)) + /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/ + #include "device/MK63F12WS/MK63F12WS_adc.h" + #include "device/MK63F12WS/MK63F12WS_aips.h" + #include "device/MK63F12WS/MK63F12WS_axbs.h" + #include "device/MK63F12WS/MK63F12WS_can.h" + #include "device/MK63F12WS/MK63F12WS_cau.h" + #include "device/MK63F12WS/MK63F12WS_cmp.h" + #include "device/MK63F12WS/MK63F12WS_cmt.h" + #include "device/MK63F12WS/MK63F12WS_crc.h" + #include "device/MK63F12WS/MK63F12WS_dac.h" + #include "device/MK63F12WS/MK63F12WS_dma.h" + #include "device/MK63F12WS/MK63F12WS_dmamux.h" + #include "device/MK63F12WS/MK63F12WS_dry.h" + #include "device/MK63F12WS/MK63F12WS_enet.h" + #include "device/MK63F12WS/MK63F12WS_ewm.h" + #include "device/MK63F12WS/MK63F12WS_fb.h" + #include "device/MK63F12WS/MK63F12WS_fmc.h" + #include "device/MK63F12WS/MK63F12WS_ftfe.h" + #include "device/MK63F12WS/MK63F12WS_ftm.h" + #include "device/MK63F12WS/MK63F12WS_gpio.h" + #include "device/MK63F12WS/MK63F12WS_i2c.h" + #include "device/MK63F12WS/MK63F12WS_i2s.h" + #include "device/MK63F12WS/MK63F12WS_llwu.h" + #include "device/MK63F12WS/MK63F12WS_lptmr.h" + #include "device/MK63F12WS/MK63F12WS_mcg.h" + #include "device/MK63F12WS/MK63F12WS_mcm.h" + #include "device/MK63F12WS/MK63F12WS_mpu.h" + #include "device/MK63F12WS/MK63F12WS_nv.h" + #include "device/MK63F12WS/MK63F12WS_osc.h" + #include "device/MK63F12WS/MK63F12WS_pdb.h" + #include "device/MK63F12WS/MK63F12WS_pit.h" + #include "device/MK63F12WS/MK63F12WS_pmc.h" + #include "device/MK63F12WS/MK63F12WS_port.h" + #include "device/MK63F12WS/MK63F12WS_rcm.h" + #include "device/MK63F12WS/MK63F12WS_rfsys.h" + #include "device/MK63F12WS/MK63F12WS_rfvbat.h" + #include "device/MK63F12WS/MK63F12WS_rng.h" + #include "device/MK63F12WS/MK63F12WS_rtc.h" + #include "device/MK63F12WS/MK63F12WS_sdhc.h" + #include "device/MK63F12WS/MK63F12WS_sim.h" + #include "device/MK63F12WS/MK63F12WS_smc.h" + #include "device/MK63F12WS/MK63F12WS_spi.h" + #include "device/MK63F12WS/MK63F12WS_uart.h" + #include "device/MK63F12WS/MK63F12WS_usb.h" + #include "device/MK63F12WS/MK63F12WS_usbdcd.h" + #include "device/MK63F12WS/MK63F12WS_vref.h" + #include "device/MK63F12WS/MK63F12WS_wdog.h" + + /* CMSIS-style register definitions*/ + #include "device/MK63F12WS/MK63F12WS.h" + +#elif (defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12)) + #define K64F12_SERIES + /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/ + #include "device/MK64F12/MK64F12_adc.h" + #include "device/MK64F12/MK64F12_aips.h" + #include "device/MK64F12/MK64F12_axbs.h" + #include "device/MK64F12/MK64F12_can.h" + #include "device/MK64F12/MK64F12_cau.h" + #include "device/MK64F12/MK64F12_cmp.h" + #include "device/MK64F12/MK64F12_cmt.h" + #include "device/MK64F12/MK64F12_crc.h" + #include "device/MK64F12/MK64F12_dac.h" + #include "device/MK64F12/MK64F12_dma.h" + #include "device/MK64F12/MK64F12_dmamux.h" + #include "device/MK64F12/MK64F12_enet.h" + #include "device/MK64F12/MK64F12_ewm.h" + #include "device/MK64F12/MK64F12_fb.h" + #include "device/MK64F12/MK64F12_fmc.h" + #include "device/MK64F12/MK64F12_ftfe.h" + #include "device/MK64F12/MK64F12_ftm.h" + #include "device/MK64F12/MK64F12_gpio.h" + #include "device/MK64F12/MK64F12_i2c.h" + #include "device/MK64F12/MK64F12_i2s.h" + #include "device/MK64F12/MK64F12_llwu.h" + #include "device/MK64F12/MK64F12_lptmr.h" + #include "device/MK64F12/MK64F12_mcg.h" + #include "device/MK64F12/MK64F12_mcm.h" + #include "device/MK64F12/MK64F12_mpu.h" + #include "device/MK64F12/MK64F12_nv.h" + #include "device/MK64F12/MK64F12_osc.h" + #include "device/MK64F12/MK64F12_pdb.h" + #include "device/MK64F12/MK64F12_pit.h" + #include "device/MK64F12/MK64F12_pmc.h" + #include "device/MK64F12/MK64F12_port.h" + #include "device/MK64F12/MK64F12_rcm.h" + #include "device/MK64F12/MK64F12_rfsys.h" + #include "device/MK64F12/MK64F12_rfvbat.h" + #include "device/MK64F12/MK64F12_rng.h" + #include "device/MK64F12/MK64F12_rtc.h" + #include "device/MK64F12/MK64F12_sdhc.h" + #include "device/MK64F12/MK64F12_sim.h" + #include "device/MK64F12/MK64F12_smc.h" + #include "device/MK64F12/MK64F12_spi.h" + #include "device/MK64F12/MK64F12_uart.h" + #include "device/MK64F12/MK64F12_usb.h" + #include "device/MK64F12/MK64F12_usbdcd.h" + #include "device/MK64F12/MK64F12_vref.h" + #include "device/MK64F12/MK64F12_wdog.h" + + /* CMSIS-style register definitions*/ + #include "device/MK64F12/MK64F12.h" + +#elif (defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \ + defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \ + defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)) + #define K70F12_SERIES + /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/ + #include "device/MK70F12/MK70F12_adc.h" + #include "device/MK70F12/MK70F12_aips.h" + #include "device/MK70F12/MK70F12_axbs.h" + #include "device/MK70F12/MK70F12_can.h" + #include "device/MK70F12/MK70F12_cau.h" + #include "device/MK70F12/MK70F12_cmp.h" + #include "device/MK70F12/MK70F12_cmt.h" + #include "device/MK70F12/MK70F12_crc.h" + #include "device/MK70F12/MK70F12_dac.h" + #include "device/MK70F12/MK70F12_ddr.h" + #include "device/MK70F12/MK70F12_dma.h" + #include "device/MK70F12/MK70F12_dmamux.h" + #include "device/MK70F12/MK70F12_enet.h" + #include "device/MK70F12/MK70F12_ewm.h" + #include "device/MK70F12/MK70F12_fb.h" + #include "device/MK70F12/MK70F12_fmc.h" + #include "device/MK70F12/MK70F12_ftfe.h" + #include "device/MK70F12/MK70F12_ftm.h" + #include "device/MK70F12/MK70F12_gpio.h" + #include "device/MK70F12/MK70F12_i2c.h" + #include "device/MK70F12/MK70F12_i2s.h" + #include "device/MK70F12/MK70F12_lcdc.h" + #include "device/MK70F12/MK70F12_llwu.h" + #include "device/MK70F12/MK70F12_lmem.h" + #include "device/MK70F12/MK70F12_lptmr.h" + #include "device/MK70F12/MK70F12_mcg.h" + #include "device/MK70F12/MK70F12_mcm.h" + #include "device/MK70F12/MK70F12_mpu.h" + #include "device/MK70F12/MK70F12_nfc.h" + #include "device/MK70F12/MK70F12_nv.h" + #include "device/MK70F12/MK70F12_osc.h" + #include "device/MK70F12/MK70F12_pdb.h" + #include "device/MK70F12/MK70F12_pit.h" + #include "device/MK70F12/MK70F12_pmc.h" + #include "device/MK70F12/MK70F12_port.h" + #include "device/MK70F12/MK70F12_rcm.h" + #include "device/MK70F12/MK70F12_rfsys.h" + #include "device/MK70F12/MK70F12_rfvbat.h" + #include "device/MK70F12/MK70F12_rng.h" + #include "device/MK70F12/MK70F12_rtc.h" + #include "device/MK70F12/MK70F12_sdhc.h" + #include "device/MK70F12/MK70F12_sim.h" + #include "device/MK70F12/MK70F12_smc.h" + #include "device/MK70F12/MK70F12_spi.h" + #include "device/MK70F12/MK70F12_tsi.h" + #include "device/MK70F12/MK70F12_uart.h" + #include "device/MK70F12/MK70F12_usb.h" + #include "device/MK70F12/MK70F12_usbdcd.h" + #include "device/MK70F12/MK70F12_usbhs.h" + #include "device/MK70F12/MK70F12_vref.h" + #include "device/MK70F12/MK70F12_wdog.h" + + /* CMSIS-style register definitions*/ + #include "device/MK70F12/MK70F12.h" + +#elif (defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || \ + defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \ + defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)) + /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/ + #include "device/MK70F15/MK70F15_adc.h" + #include "device/MK70F15/MK70F15_aips.h" + #include "device/MK70F15/MK70F15_axbs.h" + #include "device/MK70F15/MK70F15_can.h" + #include "device/MK70F15/MK70F15_cau.h" + #include "device/MK70F15/MK70F15_cmp.h" + #include "device/MK70F15/MK70F15_cmt.h" + #include "device/MK70F15/MK70F15_crc.h" + #include "device/MK70F15/MK70F15_dac.h" + #include "device/MK70F15/MK70F15_ddr.h" + #include "device/MK70F15/MK70F15_dma.h" + #include "device/MK70F15/MK70F15_dmamux.h" + #include "device/MK70F15/MK70F15_enet.h" + #include "device/MK70F15/MK70F15_ewm.h" + #include "device/MK70F15/MK70F15_fb.h" + #include "device/MK70F15/MK70F15_fmc.h" + #include "device/MK70F15/MK70F15_ftfe.h" + #include "device/MK70F15/MK70F15_ftm.h" + #include "device/MK70F15/MK70F15_gpio.h" + #include "device/MK70F15/MK70F15_i2c.h" + #include "device/MK70F15/MK70F15_i2s.h" + #include "device/MK70F15/MK70F15_lcdc.h" + #include "device/MK70F15/MK70F15_llwu.h" + #include "device/MK70F15/MK70F15_lmem.h" + #include "device/MK70F15/MK70F15_lptmr.h" + #include "device/MK70F15/MK70F15_mcg.h" + #include "device/MK70F15/MK70F15_mcm.h" + #include "device/MK70F15/MK70F15_mpu.h" + #include "device/MK70F15/MK70F15_nfc.h" + #include "device/MK70F15/MK70F15_nv.h" + #include "device/MK70F15/MK70F15_osc.h" + #include "device/MK70F15/MK70F15_pdb.h" + #include "device/MK70F15/MK70F15_pit.h" + #include "device/MK70F15/MK70F15_pmc.h" + #include "device/MK70F15/MK70F15_port.h" + #include "device/MK70F15/MK70F15_rcm.h" + #include "device/MK70F15/MK70F15_rfsys.h" + #include "device/MK70F15/MK70F15_rfvbat.h" + #include "device/MK70F15/MK70F15_rng.h" + #include "device/MK70F15/MK70F15_rtc.h" + #include "device/MK70F15/MK70F15_sdhc.h" + #include "device/MK70F15/MK70F15_sim.h" + #include "device/MK70F15/MK70F15_smc.h" + #include "device/MK70F15/MK70F15_spi.h" + #include "device/MK70F15/MK70F15_tsi.h" + #include "device/MK70F15/MK70F15_uart.h" + #include "device/MK70F15/MK70F15_usb.h" + #include "device/MK70F15/MK70F15_usbdcd.h" + #include "device/MK70F15/MK70F15_usbhs.h" + #include "device/MK70F15/MK70F15_vref.h" + #include "device/MK70F15/MK70F15_wdog.h" + + /* CMSIS-style register definitions*/ + #include "device/MK70F15/MK70F15.h" + +#elif (defined(CPU_MK70FN1M0VMJ12WS) || defined(CPU_MK70FX512VMJ12WS) || defined(CPU_MK70FN1M0VMJ15WS) || \ + defined(CPU_MK70FX512VMJ15WS)) + /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/ + #include "device/MK70F12WS/MK70F12WS_adc.h" + #include "device/MK70F12WS/MK70F12WS_aips.h" + #include "device/MK70F12WS/MK70F12WS_axbs.h" + #include "device/MK70F12WS/MK70F12WS_can.h" + #include "device/MK70F12WS/MK70F12WS_cau.h" + #include "device/MK70F12WS/MK70F12WS_cmp.h" + #include "device/MK70F12WS/MK70F12WS_cmt.h" + #include "device/MK70F12WS/MK70F12WS_crc.h" + #include "device/MK70F12WS/MK70F12WS_dac.h" + #include "device/MK70F12WS/MK70F12WS_ddr.h" + #include "device/MK70F12WS/MK70F12WS_dma.h" + #include "device/MK70F12WS/MK70F12WS_dmamux.h" + #include "device/MK70F12WS/MK70F12WS_dry.h" + #include "device/MK70F12WS/MK70F12WS_enet.h" + #include "device/MK70F12WS/MK70F12WS_ewm.h" + #include "device/MK70F12WS/MK70F12WS_fb.h" + #include "device/MK70F12WS/MK70F12WS_fmc.h" + #include "device/MK70F12WS/MK70F12WS_ftfe.h" + #include "device/MK70F12WS/MK70F12WS_ftm.h" + #include "device/MK70F12WS/MK70F12WS_gpio.h" + #include "device/MK70F12WS/MK70F12WS_i2c.h" + #include "device/MK70F12WS/MK70F12WS_i2s.h" + #include "device/MK70F12WS/MK70F12WS_lcdc.h" + #include "device/MK70F12WS/MK70F12WS_llwu.h" + #include "device/MK70F12WS/MK70F12WS_lmem.h" + #include "device/MK70F12WS/MK70F12WS_lptmr.h" + #include "device/MK70F12WS/MK70F12WS_mcg.h" + #include "device/MK70F12WS/MK70F12WS_mcm.h" + #include "device/MK70F12WS/MK70F12WS_mpu.h" + #include "device/MK70F12WS/MK70F12WS_nfc.h" + #include "device/MK70F12WS/MK70F12WS_nv.h" + #include "device/MK70F12WS/MK70F12WS_osc.h" + #include "device/MK70F12WS/MK70F12WS_pdb.h" + #include "device/MK70F12WS/MK70F12WS_pit.h" + #include "device/MK70F12WS/MK70F12WS_pmc.h" + #include "device/MK70F12WS/MK70F12WS_port.h" + #include "device/MK70F12WS/MK70F12WS_rcm.h" + #include "device/MK70F12WS/MK70F12WS_rfsys.h" + #include "device/MK70F12WS/MK70F12WS_rfvbat.h" + #include "device/MK70F12WS/MK70F12WS_rng.h" + #include "device/MK70F12WS/MK70F12WS_rtc.h" + #include "device/MK70F12WS/MK70F12WS_sdhc.h" + #include "device/MK70F12WS/MK70F12WS_sim.h" + #include "device/MK70F12WS/MK70F12WS_smc.h" + #include "device/MK70F12WS/MK70F12WS_spi.h" + #include "device/MK70F12WS/MK70F12WS_tsi.h" + #include "device/MK70F12WS/MK70F12WS_uart.h" + #include "device/MK70F12WS/MK70F12WS_usb.h" + #include "device/MK70F12WS/MK70F12WS_usbdcd.h" + #include "device/MK70F12WS/MK70F12WS_usbhs.h" + #include "device/MK70F12WS/MK70F12WS_vref.h" + #include "device/MK70F12WS/MK70F12WS_wdog.h" + + /* CMSIS-style register definitions*/ + #include "device/MK70F12WS/MK70F12WS.h" + +#elif (defined(CPU_MK70FN1M0VMJ12WS) || defined(CPU_MK70FX512VMJ12WS) || defined(CPU_MK70FN1M0VMJ15WS) || \ + defined(CPU_MK70FX512VMJ15WS)) + /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/ + #include "device/MK70F15WS/MK70F15WS_adc.h" + #include "device/MK70F15WS/MK70F15WS_aips.h" + #include "device/MK70F15WS/MK70F15WS_axbs.h" + #include "device/MK70F15WS/MK70F15WS_can.h" + #include "device/MK70F15WS/MK70F15WS_cau.h" + #include "device/MK70F15WS/MK70F15WS_cmp.h" + #include "device/MK70F15WS/MK70F15WS_cmt.h" + #include "device/MK70F15WS/MK70F15WS_crc.h" + #include "device/MK70F15WS/MK70F15WS_dac.h" + #include "device/MK70F15WS/MK70F15WS_ddr.h" + #include "device/MK70F15WS/MK70F15WS_dma.h" + #include "device/MK70F15WS/MK70F15WS_dmamux.h" + #include "device/MK70F15WS/MK70F15WS_dry.h" + #include "device/MK70F15WS/MK70F15WS_enet.h" + #include "device/MK70F15WS/MK70F15WS_ewm.h" + #include "device/MK70F15WS/MK70F15WS_fb.h" + #include "device/MK70F15WS/MK70F15WS_fmc.h" + #include "device/MK70F15WS/MK70F15WS_ftfe.h" + #include "device/MK70F15WS/MK70F15WS_ftm.h" + #include "device/MK70F15WS/MK70F15WS_gpio.h" + #include "device/MK70F15WS/MK70F15WS_i2c.h" + #include "device/MK70F15WS/MK70F15WS_i2s.h" + #include "device/MK70F15WS/MK70F15WS_lcdc.h" + #include "device/MK70F15WS/MK70F15WS_llwu.h" + #include "device/MK70F15WS/MK70F15WS_lmem.h" + #include "device/MK70F15WS/MK70F15WS_lptmr.h" + #include "device/MK70F15WS/MK70F15WS_mcg.h" + #include "device/MK70F15WS/MK70F15WS_mcm.h" + #include "device/MK70F15WS/MK70F15WS_mpu.h" + #include "device/MK70F15WS/MK70F15WS_nfc.h" + #include "device/MK70F15WS/MK70F15WS_nv.h" + #include "device/MK70F15WS/MK70F15WS_osc.h" + #include "device/MK70F15WS/MK70F15WS_pdb.h" + #include "device/MK70F15WS/MK70F15WS_pit.h" + #include "device/MK70F15WS/MK70F15WS_pmc.h" + #include "device/MK70F15WS/MK70F15WS_port.h" + #include "device/MK70F15WS/MK70F15WS_rcm.h" + #include "device/MK70F15WS/MK70F15WS_rfsys.h" + #include "device/MK70F15WS/MK70F15WS_rfvbat.h" + #include "device/MK70F15WS/MK70F15WS_rng.h" + #include "device/MK70F15WS/MK70F15WS_rtc.h" + #include "device/MK70F15WS/MK70F15WS_sdhc.h" + #include "device/MK70F15WS/MK70F15WS_sim.h" + #include "device/MK70F15WS/MK70F15WS_smc.h" + #include "device/MK70F15WS/MK70F15WS_spi.h" + #include "device/MK70F15WS/MK70F15WS_tsi.h" + #include "device/MK70F15WS/MK70F15WS_uart.h" + #include "device/MK70F15WS/MK70F15WS_usb.h" + #include "device/MK70F15WS/MK70F15WS_usbdcd.h" + #include "device/MK70F15WS/MK70F15WS_usbhs.h" + #include "device/MK70F15WS/MK70F15WS_vref.h" + #include "device/MK70F15WS/MK70F15WS_wdog.h" + + /* CMSIS-style register definitions*/ + #include "device/MK70F15WS/MK70F15WS.h" + +#elif (defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \ + defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || \ + defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \ + defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4)) + #define KL25Z4_SERIES + /* Extension register headers. (These will eventually be merged into the CMSIS-style header.)*/ + #include "device/MKL25Z4/MKL25Z4_adc.h" + #include "device/MKL25Z4/MKL25Z4_cmp.h" + #include "device/MKL25Z4/MKL25Z4_dac.h" + #include "device/MKL25Z4/MKL25Z4_dma.h" + #include "device/MKL25Z4/MKL25Z4_dmamux.h" + #include "device/MKL25Z4/MKL25Z4_fgpio.h" + #include "device/MKL25Z4/MKL25Z4_ftfa.h" + #include "device/MKL25Z4/MKL25Z4_gpio.h" + #include "device/MKL25Z4/MKL25Z4_i2c.h" + #include "device/MKL25Z4/MKL25Z4_llwu.h" + #include "device/MKL25Z4/MKL25Z4_lptmr.h" + #include "device/MKL25Z4/MKL25Z4_mcg.h" + #include "device/MKL25Z4/MKL25Z4_mcm.h" + #include "device/MKL25Z4/MKL25Z4_mtb.h" + #include "device/MKL25Z4/MKL25Z4_mtbdwt.h" + #include "device/MKL25Z4/MKL25Z4_nv.h" + #include "device/MKL25Z4/MKL25Z4_osc.h" + #include "device/MKL25Z4/MKL25Z4_pit.h" + #include "device/MKL25Z4/MKL25Z4_pmc.h" + #include "device/MKL25Z4/MKL25Z4_port.h" + #include "device/MKL25Z4/MKL25Z4_rcm.h" + #include "device/MKL25Z4/MKL25Z4_rom.h" + #include "device/MKL25Z4/MKL25Z4_rtc.h" + #include "device/MKL25Z4/MKL25Z4_sim.h" + #include "device/MKL25Z4/MKL25Z4_smc.h" + #include "device/MKL25Z4/MKL25Z4_spi.h" + #include "device/MKL25Z4/MKL25Z4_tpm.h" + #include "device/MKL25Z4/MKL25Z4_tsi.h" + #include "device/MKL25Z4/MKL25Z4_uart.h" + #include "device/MKL25Z4/MKL25Z4_uart0.h" + #include "device/MKL25Z4/MKL25Z4_usb.h" + + /* CMSIS-style register definitions*/ + #include "device/MKL25Z4/MKL25Z4.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__*/ +/******************************************************************************* + * EOF + ******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/gpio_object.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,50 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "mbed_assert.h"
+#include "fsl_gpio_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pinName;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+ MBED_ASSERT(obj->pinName != (PinName)NC);
+ uint32_t port = obj->pinName >> GPIO_PORT_SHIFT;
+ uint32_t pin = obj->pinName & 0xFF;
+
+ gpio_hal_write_pin_output(port, pin, value);
+}
+
+static inline int gpio_read(gpio_t *obj) {
+ MBED_ASSERT(obj->pinName != (PinName)NC);
+ uint32_t port = obj->pinName >> GPIO_PORT_SHIFT;
+ uint32_t pin = obj->pinName & 0xFF;
+
+ return (int)gpio_hal_read_pin_input(port, pin);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/objects.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,69 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ uint32_t port;
+ uint32_t pin;
+ uint32_t ch;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+};
+
+struct pwmout_s {
+ PWMName pwm_name;
+};
+
+struct serial_s {
+ int index;
+};
+
+struct analogin_s {
+ ADCName adc;
+};
+
+struct i2c_s {
+ uint32_t instance;
+};
+
+struct spi_s {
+ uint32_t instance;
+};
+
+struct dac_s {
+ DACName dac;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
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--- a/TARGET_LPC4088/TOOLCHAIN_ARM_STD/LPC407X_8X.sct Fri Aug 15 15:28:31 2014 +0100
+++ b/TARGET_LPC4088/TOOLCHAIN_ARM_STD/LPC407X_8X.sct Fri Sep 12 16:41:52 2014 +0100
@@ -6,7 +6,7 @@
ER_IROM1 0x00000000 0x00080000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
- *.o (+RO-CODE) ; forces all CODE to IFLASH
+ *.o (+RO-CODE) ; prioritizes CODE in IFLASH before SPIFI
.ANY2 (+RO-DATA) ; prioritizes DATA in IFLASH before SPIFI
.ANY (+RO) ; remaining RO
}
@@ -25,6 +25,7 @@
ER_IROM2 0x28000000 0x01000000 { ; load address = execution address
.ANY1 (+RO-DATA) ; all DATA not fitting in IFLASH
.ANY (SPIFI_MEM) ; DATA tagged as SPIFI_MEM
+ *.o (SPIFI_MEM) ; CODE tagged as SPIFI_MEM
}
}
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC4337/LPC43xx.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,2113 @@
+/*
+ * LPC43xx/LPC18xx MCU header
+ *
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products. This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights. NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers. This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ *
+ * Simplified version of NXP LPCOPEN LPC43XX/LPC18XX headers
+ * 05/15/13 Micromint USA <support@micromint.com>
+ */
+
+#ifndef __LPC43XX_H
+#define __LPC43XX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Treat __CORE_Mx as CORE_Mx */
+#if defined(__CORTEX_M0) && !defined(CORE_M0)
+ #define CORE_M0
+#endif
+#if defined(__CORTEX_M3) && !defined(CORE_M3)
+ #define CORE_M3
+#endif
+/* Default to M4 core if no core explicitly declared */
+#if !defined(CORE_M0) && !defined(CORE_M3)
+ #define CORE_M4
+#endif
+
+/* Define LPC18XX or LPC43XX according to core type */
+#if (defined(CORE_M4) || defined(CORE_M0)) && !defined(__LPC43XX__)
+ #define __LPC43XX__
+#endif
+#if defined(CORE_M3) && !defined(__LPC18XX__)
+ #define __LPC18XX__
+#endif
+
+/* Start of section using anonymous unions */
+#if defined(__ARMCC_VERSION)
+// Kill warning "#pragma push with no matching #pragma pop"
+ #pragma diag_suppress 2525
+ #pragma push
+ #pragma anon_unions
+#elif defined(__CWCC__)
+ #pragma push
+ #pragma cpp_extensions on
+#elif defined(__IAR_SYSTEMS_ICC__)
+ //#pragma push // FIXME not usable for IAR
+ #pragma language=extended
+#else /* defined(__GNUC__) and others */
+ /* Assume anonymous unions are enabled by default */
+#endif
+
+#if defined(CORE_M4)
+/* ---------------------------------------------------------------------------
+ * LPC43xx (M4 Core) Cortex CMSIS definitions
+ */
+
+#define __CM4_REV 0x0000 /* Cortex-M4 Core Revision */
+#define __MPU_PRESENT 1 /* MPU present or not */
+#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /* FPU present or not */
+#define CHIP_LPC43XX /* LPCOPEN compatibility */
+
+/* ---------------------------------------------------------------------------
+ * LPC43xx peripheral interrupt numbers
+ */
+
+typedef enum {
+ /* --------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
+ Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
+ BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+ UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
+ PendSV_IRQn = -2,/* 14 Pendable request for system service */
+ SysTick_IRQn = -1,/* 15 System Tick Timer */
+
+ /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
+ DAC_IRQn = 0,/* 0 DAC */
+ M0CORE_IRQn = 1,/* 1 M0a */
+ DMA_IRQn = 2,/* 2 DMA */
+ RESERVED1_IRQn = 3,/* 3 EZH/EDM */
+ RESERVED2_IRQn = 4,
+ ETHERNET_IRQn = 5,/* 5 ETHERNET */
+ SDIO_IRQn = 6,/* 6 SDIO */
+ LCD_IRQn = 7,/* 7 LCD */
+ USB0_IRQn = 8,/* 8 USB0 */
+ USB1_IRQn = 9,/* 9 USB1 */
+ SCT_IRQn = 10,/* 10 SCT */
+ RITIMER_IRQn = 11,/* 11 RITIMER */
+ TIMER0_IRQn = 12,/* 12 TIMER0 */
+ TIMER1_IRQn = 13,/* 13 TIMER1 */
+ TIMER2_IRQn = 14,/* 14 TIMER2 */
+ TIMER3_IRQn = 15,/* 15 TIMER3 */
+ MCPWM_IRQn = 16,/* 16 MCPWM */
+ ADC0_IRQn = 17,/* 17 ADC0 */
+ I2C0_IRQn = 18,/* 18 I2C0 */
+ I2C1_IRQn = 19,/* 19 I2C1 */
+ SPI_INT_IRQn = 20,/* 20 SPI_INT */
+ ADC1_IRQn = 21,/* 21 ADC1 */
+ SSP0_IRQn = 22,/* 22 SSP0 */
+ SSP1_IRQn = 23,/* 23 SSP1 */
+ USART0_IRQn = 24,/* 24 USART0 */
+ UART1_IRQn = 25,/* 25 UART1 */
+ USART2_IRQn = 26,/* 26 USART2 */
+ USART3_IRQn = 27,/* 27 USART3 */
+ I2S0_IRQn = 28,/* 28 I2S0 */
+ I2S1_IRQn = 29,/* 29 I2S1 */
+ RESERVED4_IRQn = 30,
+ SGPIO_INT_IRQn = 31,/* 31 SGPIO_IINT */
+ PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
+ PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
+ PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
+ PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
+ PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
+ PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
+ PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
+ PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
+ GINT0_IRQn = 40,/* 40 GINT0 */
+ GINT1_IRQn = 41,/* 41 GINT1 */
+ EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
+ C_CAN1_IRQn = 43,/* 43 C_CAN1 */
+ RESERVED6_IRQn = 44,
+ RESERVED7_IRQn = 45,/* 45 VADC */
+ ATIMER_IRQn = 46,/* 46 ATIMER */
+ RTC_IRQn = 47,/* 47 RTC */
+ RESERVED8_IRQn = 48,
+ WWDT_IRQn = 49,/* 49 WWDT */
+ RESERVED9_IRQn = 50,
+ C_CAN0_IRQn = 51,/* 51 C_CAN0 */
+ QEI_IRQn = 52,/* 52 QEI */
+} IRQn_Type;
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+
+#elif defined(CORE_M3)
+/* ---------------------------------------------------------------------------
+ * LPC18xx (M3 Core) Cortex CMSIS definitions
+ */
+#define __MPU_PRESENT 1 /* MPU present or not */
+#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 0 /* FPU present or not */
+#define CHIP_LPC18XX /* LPCOPEN compatibility */
+
+/* ---------------------------------------------------------------------------
+ * LPC18xx peripheral interrupt numbers
+ */
+
+typedef enum {
+ /* --------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
+ Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
+ BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+ UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
+ PendSV_IRQn = -2,/* 14 Pendable request for system service */
+ SysTick_IRQn = -1,/* 15 System Tick Timer */
+
+ /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
+ DAC_IRQn = 0,/* 0 DAC */
+ RESERVED0_IRQn = 1,
+ DMA_IRQn = 2,/* 2 DMA */
+ RESERVED1_IRQn = 3,/* 3 EZH/EDM */
+ RESERVED2_IRQn = 4,
+ ETHERNET_IRQn = 5,/* 5 ETHERNET */
+ SDIO_IRQn = 6,/* 6 SDIO */
+ LCD_IRQn = 7,/* 7 LCD */
+ USB0_IRQn = 8,/* 8 USB0 */
+ USB1_IRQn = 9,/* 9 USB1 */
+ SCT_IRQn = 10,/* 10 SCT */
+ RITIMER_IRQn = 11,/* 11 RITIMER */
+ TIMER0_IRQn = 12,/* 12 TIMER0 */
+ TIMER1_IRQn = 13,/* 13 TIMER1 */
+ TIMER2_IRQn = 14,/* 14 TIMER2 */
+ TIMER3_IRQn = 15,/* 15 TIMER3 */
+ MCPWM_IRQn = 16,/* 16 MCPWM */
+ ADC0_IRQn = 17,/* 17 ADC0 */
+ I2C0_IRQn = 18,/* 18 I2C0 */
+ I2C1_IRQn = 19,/* 19 I2C1 */
+ RESERVED3_IRQn = 20,
+ ADC1_IRQn = 21,/* 21 ADC1 */
+ SSP0_IRQn = 22,/* 22 SSP0 */
+ SSP1_IRQn = 23,/* 23 SSP1 */
+ USART0_IRQn = 24,/* 24 USART0 */
+ UART1_IRQn = 25,/* 25 UART1 */
+ USART2_IRQn = 26,/* 26 USART2 */
+ USART3_IRQn = 27,/* 27 USART3 */
+ I2S0_IRQn = 28,/* 28 I2S0 */
+ I2S1_IRQn = 29,/* 29 I2S1 */
+ RESERVED4_IRQn = 30,
+ RESERVED5_IRQn = 31,
+ PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
+ PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
+ PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
+ PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
+ PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
+ PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
+ PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
+ PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
+ GINT0_IRQn = 40,/* 40 GINT0 */
+ GINT1_IRQn = 41,/* 41 GINT1 */
+ EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
+ C_CAN1_IRQn = 43,/* 43 C_CAN1 */
+ RESERVED6_IRQn = 44,
+ RESERVED7_IRQn = 45,/* 45 VADC */
+ ATIMER_IRQn = 46,/* 46 ATIMER */
+ RTC_IRQn = 47,/* 47 RTC */
+ RESERVED8_IRQn = 48,
+ WWDT_IRQn = 49,/* 49 WWDT */
+ RESERVED9_IRQn = 50,
+ C_CAN0_IRQn = 51,/* 51 C_CAN0 */
+ QEI_IRQn = 52,/* 52 QEI */
+} IRQn_Type;
+
+#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
+
+#elif defined(CORE_M0)
+/* ---------------------------------------------------------------------------
+ * LPC43xx (M0 Core) Cortex CMSIS definitions
+ */
+
+#define __MPU_PRESENT 0 /* MPU present or not */
+#define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 0 /* FPU present or not */
+#define CHIP_LPC43XX /* LPCOPEN compatibility */
+
+/* ---------------------------------------------------------------------------
+ * LPC43xx (M0 Core) peripheral interrupt numbers
+ */
+
+typedef enum {
+ /* --------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
+ Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
+ SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
+ PendSV_IRQn = -2,/* 14 Pendable request for system service */
+ SysTick_IRQn = -1,/* 15 System Tick Timer */
+
+ /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
+ DAC_IRQn = 0,/* 0 DAC */
+ M0_M4CORE_IRQn = 1,/* 1 M0a */
+ DMA_IRQn = 2,/* 2 DMA r */
+ RESERVED1_IRQn = 3,/* 3 EZH/EDM */
+ FLASHEEPROM_IRQn = 4,/* 4 ORed Flash EEPROM Bank A, B, EEPROM */
+ ETHERNET_IRQn = 5,/* 5 ETHERNET */
+ SDIO_IRQn = 6,/* 6 SDIO */
+ LCD_IRQn = 7,/* 7 LCD */
+ USB0_IRQn = 8,/* 8 USB0 */
+ USB1_IRQn = 9,/* 9 USB1 */
+ SCT_IRQn = 10,/* 10 SCT */
+ RITIMER_IRQn = 11,/* 11 ORed RITIMER, WDT */
+ TIMER0_IRQn = 12,/* 12 TIMER0 */
+ GINT1_IRQn = 13,/* 13 GINT1 */
+ PIN_INT4_IRQn = 14,/* 14 GPIO 4 */
+ TIMER3_IRQn = 15,/* 15 TIMER3 */
+ MCPWM_IRQn = 16,/* 16 MCPWM */
+ ADC0_IRQn = 17,/* 17 ADC0 */
+ I2C0_IRQn = 18,/* 18 ORed I2C0, I2C1 */
+ SGPIO_INT_IRQn = 19,/* 19 SGPIO */
+ SPI_INT_IRQn = 20,/* 20 SPI_INT */
+ ADC1_IRQn = 21,/* 21 ADC1 */
+ SSP0_IRQn = 22,/* 22 ORed SSP0, SSP1 */
+ EVENTROUTER_IRQn = 23,/* 23 EVENTROUTER */
+ USART0_IRQn = 24,/* 24 USART0 */
+ UART1_IRQn = 25,/* 25 UART1 */
+ USART2_IRQn = 26,/* 26 USART2 */
+ USART3_IRQn = 27,/* 27 USART3 */
+ I2S0_IRQn = 28,/* 28 ORed I2S0, I2S1 */
+ C_CAN0_IRQn = 29,/* 29 C_CAN0 */
+ I2S1_IRQn = 29,/* 29 I2S1 */
+ RESERVED2_IRQn = 30,
+ RESERVED3_IRQn = 31,
+} IRQn_Type;
+
+#include "core_cm0.h" /* Cortex-M4 processor and core peripherals */
+#else
+#error Please #define CORE_M0, CORE_M3 or CORE_M4
+#endif
+
+#include "system_LPC43xx.h"
+
+/* ---------------------------------------------------------------------------
+ * State Configurable Timer register block structure
+ */
+#define LPC_SCT_BASE 0x40000000
+#define CONFIG_SCT_nEV (16) /* Number of events */
+#define CONFIG_SCT_nRG (16) /* Number of match/compare registers */
+#define CONFIG_SCT_nOU (16) /* Number of outputs */
+
+typedef struct {
+ __IO uint32_t CONFIG; /* Configuration Register */
+ union {
+ __IO uint32_t CTRL_U; /* Control Register */
+ struct {
+ __IO uint16_t CTRL_L; /* Low control register */
+ __IO uint16_t CTRL_H; /* High control register */
+ };
+
+ };
+
+ __IO uint16_t LIMIT_L; /* limit register for counter L */
+ __IO uint16_t LIMIT_H; /* limit register for counter H */
+ __IO uint16_t HALT_L; /* halt register for counter L */
+ __IO uint16_t HALT_H; /* halt register for counter H */
+ __IO uint16_t STOP_L; /* stop register for counter L */
+ __IO uint16_t STOP_H; /* stop register for counter H */
+ __IO uint16_t START_L; /* start register for counter L */
+ __IO uint16_t START_H; /* start register for counter H */
+ uint32_t RESERVED1[10]; /* 0x03C reserved */
+ union {
+ __IO uint32_t COUNT_U; /* counter register */
+ struct {
+ __IO uint16_t COUNT_L; /* counter register for counter L */
+ __IO uint16_t COUNT_H; /* counter register for counter H */
+ };
+
+ };
+
+ __IO uint16_t STATE_L; /* state register for counter L */
+ __IO uint16_t STATE_H; /* state register for counter H */
+ __I uint32_t INPUT; /* input register */
+ __IO uint16_t REGMODE_L; /* match - capture registers mode register L */
+ __IO uint16_t REGMODE_H; /* match - capture registers mode register H */
+ __IO uint32_t OUTPUT; /* output register */
+ __IO uint32_t OUTPUTDIRCTRL; /* output counter direction Control Register */
+ __IO uint32_t RES; /* conflict resolution register */
+ __IO uint32_t DMA0REQUEST; /* DMA0 Request Register */
+ __IO uint32_t DMA1REQUEST; /* DMA1 Request Register */
+ uint32_t RESERVED2[35];
+ __IO uint32_t EVEN; /* event enable register */
+ __IO uint32_t EVFLAG; /* event flag register */
+ __IO uint32_t CONEN; /* conflict enable register */
+ __IO uint32_t CONFLAG; /* conflict flag register */
+ union {
+ __IO union { /* ... Match / Capture value */
+ uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTMATCH[i].L Access to L value */
+ uint16_t H; /* SCTMATCH[i].H Access to H value */
+ };
+
+ } MATCH[CONFIG_SCT_nRG];
+
+ __I union {
+ uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTCAP[i].L Access to L value */
+ uint16_t H; /* SCTCAP[i].H Access to H value */
+ };
+
+ } CAP[CONFIG_SCT_nRG];
+
+ };
+
+ uint32_t RESERVED3[32 - CONFIG_SCT_nRG]; /* ...-0x17C reserved */
+ union {
+ __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
+ __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
+ };
+
+ uint16_t RESERVED4[32 - CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
+ union {
+ __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
+ __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
+ };
+
+ uint16_t RESERVED5[32 - CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
+ union {
+ __IO union { /* 0x200-... Match Reload / Capture Control value */
+ uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTMATCHREL[i].L Access to L value */
+ uint16_t H; /* SCTMATCHREL[i].H Access to H value */
+ };
+
+ } MATCHREL[CONFIG_SCT_nRG];
+
+ __IO union {
+ uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTCAPCTRL[i].L Access to L value */
+ uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
+ };
+
+ } CAPCTRL[CONFIG_SCT_nRG];
+
+ };
+
+ uint32_t RESERVED6[32 - CONFIG_SCT_nRG]; /* ...-0x27C reserved */
+ union {
+ __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
+ __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
+ };
+
+ uint16_t RESERVED7[32 - CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
+ union {
+ __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
+ __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
+ };
+
+ uint16_t RESERVED8[32 - CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
+ __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
+ uint32_t STATE; /* Event State Register */
+ uint32_t CTRL; /* Event Control Register */
+ } EVENT[CONFIG_SCT_nEV];
+
+ uint32_t RESERVED9[128 - 2 * CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
+ __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
+ uint32_t SET; /* Output n Set Register */
+ uint32_t CLR; /* Output n Clear Register */
+ } OUT[CONFIG_SCT_nOU];
+
+ uint32_t RESERVED10[191 - 2 * CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
+ __I uint32_t MODULECONTENT; /* 0x7FC Module Content */
+} LPC_SCT_T;
+
+/* Macro defines for SCT configuration register */
+#define SCT_CONFIG_16BIT_COUNTER 0x00000000 /* Operate as 2 16-bit counters */
+#define SCT_CONFIG_32BIT_COUNTER 0x00000001 /* Operate as 1 32-bit counter */
+
+#define SCT_CONFIG_CLKMODE_BUSCLK (0x0 << 1) /* Bus clock */
+#define SCT_CONFIG_CLKMODE_SCTCLK (0x1 << 1) /* SCT clock */
+#define SCT_CONFIG_CLKMODE_INCLK (0x2 << 1) /* Input clock selected in CLKSEL field */
+#define SCT_CONFIG_CLKMODE_INEDGECLK (0x3 << 1) /* Input clock edge selected in CLKSEL field */
+
+#define SCT_CONFIG_NORELOADL_U (0x1 << 7) /* Operate as 1 32-bit counter */
+#define SCT_CONFIG_NORELOADH (0x1 << 8) /* Operate as 1 32-bit counter */
+
+/* Macro defines for SCT control register */
+#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for low or unified counter */
+#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
+
+#define SCT_CTRL_STOP_L (1 << 1) /* Stop low counter */
+#define SCT_CTRL_HALT_L (1 << 2) /* Halt low counter */
+#define SCT_CTRL_CLRCTR_L (1 << 3) /* Clear low or unified counter */
+#define SCT_CTRL_BIDIR_L(x) (((x) & 0x01) << 4) /* Bidirectional bit */
+#define SCT_CTRL_PRE_L(x) (((x) & 0xFF) << 5) /* Prescale clock for low or unified counter */
+
+#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for high counter */
+#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
+#define SCT_CTRL_STOP_H (1 << 17) /* Stop high counter */
+#define SCT_CTRL_HALT_H (1 << 18) /* Halt high counter */
+#define SCT_CTRL_CLRCTR_H (1 << 19) /* Clear high counter */
+#define SCT_CTRL_BIDIR_H(x) (((x) & 0x01) << 20)
+#define SCT_CTRL_PRE_H(x) (((x) & 0xFF) << 21) /* Prescale clock for high counter */
+
+/* Macro defines for SCT Conflict resolution register */
+#define SCT_RES_NOCHANGE (0)
+#define SCT_RES_SET_OUTPUT (1)
+#define SCT_RES_CLEAR_OUTPUT (2)
+#define SCT_RES_TOGGLE_OUTPUT (3)
+
+/* ---------------------------------------------------------------------------
+ * GPDMA Channel register block structure
+ */
+#define LPC_GPDMA_BASE 0x40002000
+
+typedef struct {
+ __IO uint32_t SRCADDR; /* DMA Channel Source Address Register */
+ __IO uint32_t DESTADDR; /* DMA Channel Destination Address Register */
+ __IO uint32_t LLI; /* DMA Channel Linked List Item Register */
+ __IO uint32_t CONTROL; /* DMA Channel Control Register */
+ __IO uint32_t CONFIG; /* DMA Channel Configuration Register */
+ __I uint32_t RESERVED1[3];
+} LPC_GPDMA_CH_T;
+
+#define GPDMA_CHANNELS 8
+
+/* ---------------------------------------------------------------------------
+ * GPDMA register block
+ */
+typedef struct { /* GPDMA Structure */
+ __I uint32_t INTSTAT; /* DMA Interrupt Status Register */
+ __I uint32_t INTTCSTAT; /* DMA Interrupt Terminal Count Request Status Register */
+ __O uint32_t INTTCCLEAR; /* DMA Interrupt Terminal Count Request Clear Register */
+ __I uint32_t INTERRSTAT; /* DMA Interrupt Error Status Register */
+ __O uint32_t INTERRCLR; /* DMA Interrupt Error Clear Register */
+ __I uint32_t RAWINTTCSTAT; /* DMA Raw Interrupt Terminal Count Status Register */
+ __I uint32_t RAWINTERRSTAT; /* DMA Raw Error Interrupt Status Register */
+ __I uint32_t ENBLDCHNS; /* DMA Enabled Channel Register */
+ __IO uint32_t SOFTBREQ; /* DMA Software Burst Request Register */
+ __IO uint32_t SOFTSREQ; /* DMA Software Single Request Register */
+ __IO uint32_t SOFTLBREQ; /* DMA Software Last Burst Request Register */
+ __IO uint32_t SOFTLSREQ; /* DMA Software Last Single Request Register */
+ __IO uint32_t CONFIG; /* DMA Configuration Register */
+ __IO uint32_t SYNC; /* DMA Synchronization Register */
+ __I uint32_t RESERVED0[50];
+ LPC_GPDMA_CH_T CH[GPDMA_CHANNELS];
+} LPC_GPDMA_T;
+
+/* ---------------------------------------------------------------------------
+ * SPIFI register block structure
+ */
+#define LPC_SPIFI_BASE 0x40003000
+
+typedef struct { /* SPIFI Structure */
+ __IO uint32_t CTRL; /* Control register */
+ __IO uint32_t CMD; /* Command register */
+ __IO uint32_t ADDR; /* Address register */
+ __IO uint32_t IDATA; /* Intermediate data register */
+ __IO uint32_t CLIMIT; /* Cache limit register */
+ union {
+ __IO uint32_t DATA;
+ __IO uint16_t DATA_HWORD;
+ __IO uint8_t DATA_BYTE;
+ }; /* Data register */
+ __IO uint32_t MCMD; /* Memory command register */
+ __IO uint32_t STAT; /* Status register */
+} LPC_SPIFI_T;
+
+/* ---------------------------------------------------------------------------
+ * SD/MMC & SDIO register block structure
+ */
+#define LPC_SDMMC_BASE 0x40004000
+
+typedef struct { /* SDMMC Structure */
+ __IO uint32_t CTRL; /* Control Register */
+ __IO uint32_t PWREN; /* Power Enable Register */
+ __IO uint32_t CLKDIV; /* Clock Divider Register */
+ __IO uint32_t CLKSRC; /* SD Clock Source Register */
+ __IO uint32_t CLKENA; /* Clock Enable Register */
+ __IO uint32_t TMOUT; /* Timeout Register */
+ __IO uint32_t CTYPE; /* Card Type Register */
+ __IO uint32_t BLKSIZ; /* Block Size Register */
+ __IO uint32_t BYTCNT; /* Byte Count Register */
+ __IO uint32_t INTMASK; /* Interrupt Mask Register */
+ __IO uint32_t CMDARG; /* Command Argument Register */
+ __IO uint32_t CMD; /* Command Register */
+ __I uint32_t RESP0; /* Response Register 0 */
+ __I uint32_t RESP1; /* Response Register 1 */
+ __I uint32_t RESP2; /* Response Register 2 */
+ __I uint32_t RESP3; /* Response Register 3 */
+ __I uint32_t MINTSTS; /* Masked Interrupt Status Register */
+ __IO uint32_t RINTSTS; /* Raw Interrupt Status Register */
+ __I uint32_t STATUS; /* Status Register */
+ __IO uint32_t FIFOTH; /* FIFO Threshold Watermark Register */
+ __I uint32_t CDETECT; /* Card Detect Register */
+ __I uint32_t WRTPRT; /* Write Protect Register */
+ __IO uint32_t GPIO; /* General Purpose Input/Output Register */
+ __I uint32_t TCBCNT; /* Transferred CIU Card Byte Count Register */
+ __I uint32_t TBBCNT; /* Transferred Host to BIU-FIFO Byte Count Register */
+ __IO uint32_t DEBNCE; /* Debounce Count Register */
+ __IO uint32_t USRID; /* User ID Register */
+ __I uint32_t VERID; /* Version ID Register */
+ __I uint32_t RESERVED0;
+ __IO uint32_t UHS_REG; /* UHS-1 Register */
+ __IO uint32_t RST_N; /* Hardware Reset */
+ __I uint32_t RESERVED1;
+ __IO uint32_t BMOD; /* Bus Mode Register */
+ __O uint32_t PLDMND; /* Poll Demand Register */
+ __IO uint32_t DBADDR; /* Descriptor List Base Address Register */
+ __IO uint32_t IDSTS; /* Internal DMAC Status Register */
+ __IO uint32_t IDINTEN; /* Internal DMAC Interrupt Enable Register */
+ __I uint32_t DSCADDR; /* Current Host Descriptor Address Register */
+ __I uint32_t BUFADDR; /* Current Buffer Descriptor Address Register */
+} LPC_SDMMC_T;
+
+/* ---------------------------------------------------------------------------
+ * External Memory Controller (EMC) register block structure
+ */
+#define LPC_EMC_BASE 0x40005000
+
+typedef struct { /* EMC Structure */
+ __IO uint32_t CONTROL; /* Controls operation of the memory controller. */
+ __I uint32_t STATUS; /* Provides EMC status information. */
+ __IO uint32_t CONFIG; /* Configures operation of the memory controller. */
+ __I uint32_t RESERVED0[5];
+ __IO uint32_t DYNAMICCONTROL; /* Controls dynamic memory operation. */
+ __IO uint32_t DYNAMICREFRESH; /* Configures dynamic memory refresh operation. */
+ __IO uint32_t DYNAMICREADCONFIG; /* Configures the dynamic memory read strategy. */
+ __I uint32_t RESERVED1;
+ __IO uint32_t DYNAMICRP; /* Selects the precharge command period. */
+ __IO uint32_t DYNAMICRAS; /* Selects the active to precharge command period. */
+ __IO uint32_t DYNAMICSREX; /* Selects the self-refresh exit time. */
+ __IO uint32_t DYNAMICAPR; /* Selects the last-data-out to active command time. */
+ __IO uint32_t DYNAMICDAL; /* Selects the data-in to active command time. */
+ __IO uint32_t DYNAMICWR; /* Selects the write recovery time. */
+ __IO uint32_t DYNAMICRC; /* Selects the active to active command period. */
+ __IO uint32_t DYNAMICRFC; /* Selects the auto-refresh period. */
+ __IO uint32_t DYNAMICXSR; /* Selects the exit self-refresh to active command time. */
+ __IO uint32_t DYNAMICRRD; /* Selects the active bank A to active bank B latency. */
+ __IO uint32_t DYNAMICMRD; /* Selects the load mode register to active command time. */
+ __I uint32_t RESERVED2[9];
+ __IO uint32_t STATICEXTENDEDWAIT; /* Selects time for long static memory read and write transfers. */
+ __I uint32_t RESERVED3[31];
+ __IO uint32_t DYNAMICCONFIG0; /* Selects the configuration information for dynamic memory chip select n. */
+ __IO uint32_t DYNAMICRASCAS0; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
+ __I uint32_t RESERVED4[6];
+ __IO uint32_t DYNAMICCONFIG1; /* Selects the configuration information for dynamic memory chip select n. */
+ __IO uint32_t DYNAMICRASCAS1; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
+ __I uint32_t RESERVED5[6];
+ __IO uint32_t DYNAMICCONFIG2; /* Selects the configuration information for dynamic memory chip select n. */
+ __IO uint32_t DYNAMICRASCAS2; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
+ __I uint32_t RESERVED6[6];
+ __IO uint32_t DYNAMICCONFIG3; /* Selects the configuration information for dynamic memory chip select n. */
+ __IO uint32_t DYNAMICRASCAS3; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
+ __I uint32_t RESERVED7[38];
+ __IO uint32_t STATICCONFIG0; /* Selects the memory configuration for static chip select n. */
+ __IO uint32_t STATICWAITWEN0; /* Selects the delay from chip select n to write enable. */
+ __IO uint32_t STATICWAITOEN0; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
+ __IO uint32_t STATICWAITRD0; /* Selects the delay from chip select n to a read access. */
+ __IO uint32_t STATICWAITPAG0; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+ __IO uint32_t STATICWAITWR0; /* Selects the delay from chip select n to a write access. */
+ __IO uint32_t STATICWAITTURN0; /* Selects bus turnaround cycles */
+ __I uint32_t RESERVED8;
+ __IO uint32_t STATICCONFIG1; /* Selects the memory configuration for static chip select n. */
+ __IO uint32_t STATICWAITWEN1; /* Selects the delay from chip select n to write enable. */
+ __IO uint32_t STATICWAITOEN1; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
+ __IO uint32_t STATICWAITRD1; /* Selects the delay from chip select n to a read access. */
+ __IO uint32_t STATICWAITPAG1; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+ __IO uint32_t STATICWAITWR1; /* Selects the delay from chip select n to a write access. */
+ __IO uint32_t STATICWAITTURN1; /* Selects bus turnaround cycles */
+ __I uint32_t RESERVED9;
+ __IO uint32_t STATICCONFIG2; /* Selects the memory configuration for static chip select n. */
+ __IO uint32_t STATICWAITWEN2; /* Selects the delay from chip select n to write enable. */
+ __IO uint32_t STATICWAITOEN2; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
+ __IO uint32_t STATICWAITRD2; /* Selects the delay from chip select n to a read access. */
+ __IO uint32_t STATICWAITPAG2; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+ __IO uint32_t STATICWAITWR2; /* Selects the delay from chip select n to a write access. */
+ __IO uint32_t STATICWAITTURN2; /* Selects bus turnaround cycles */
+ __I uint32_t RESERVED10;
+ __IO uint32_t STATICCONFIG3; /* Selects the memory configuration for static chip select n. */
+ __IO uint32_t STATICWAITWEN3; /* Selects the delay from chip select n to write enable. */
+ __IO uint32_t STATICWAITOEN3; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
+ __IO uint32_t STATICWAITRD3; /* Selects the delay from chip select n to a read access. */
+ __IO uint32_t STATICWAITPAG3; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+ __IO uint32_t STATICWAITWR3; /* Selects the delay from chip select n to a write access. */
+ __IO uint32_t STATICWAITTURN3; /* Selects bus turnaround cycles */
+} LPC_EMC_T;
+
+/* ---------------------------------------------------------------------------
+ * USB High-Speed register block structure
+ */
+#define LPC_USB0_BASE 0x40006000
+#define LPC_USB1_BASE 0x40007000
+
+typedef struct { /* USB Structure */
+ __I uint32_t RESERVED0[64];
+ __I uint32_t CAPLENGTH; /* Capability register length */
+ __I uint32_t HCSPARAMS; /* Host controller structural parameters */
+ __I uint32_t HCCPARAMS; /* Host controller capability parameters */
+ __I uint32_t RESERVED1[5];
+ __I uint32_t DCIVERSION; /* Device interface version number */
+ __I uint32_t RESERVED2[7];
+ union {
+ __IO uint32_t USBCMD_H; /* USB command (host mode) */
+ __IO uint32_t USBCMD_D; /* USB command (device mode) */
+ };
+
+ union {
+ __IO uint32_t USBSTS_H; /* USB status (host mode) */
+ __IO uint32_t USBSTS_D; /* USB status (device mode) */
+ };
+
+ union {
+ __IO uint32_t USBINTR_H; /* USB interrupt enable (host mode) */
+ __IO uint32_t USBINTR_D; /* USB interrupt enable (device mode) */
+ };
+
+ union {
+ __IO uint32_t FRINDEX_H; /* USB frame index (host mode) */
+ __I uint32_t FRINDEX_D; /* USB frame index (device mode) */
+ };
+
+ __I uint32_t RESERVED3;
+ union {
+ __IO uint32_t PERIODICLISTBASE; /* Frame list base address */
+ __IO uint32_t DEVICEADDR; /* USB device address */
+ };
+
+ union {
+ __IO uint32_t ASYNCLISTADDR; /* Address of endpoint list in memory (host mode) */
+ __IO uint32_t ENDPOINTLISTADDR; /* Address of endpoint list in memory (device mode) */
+ };
+
+ __IO uint32_t TTCTRL; /* Asynchronous buffer status for embedded TT (host mode) */
+ __IO uint32_t BURSTSIZE; /* Programmable burst size */
+ __IO uint32_t TXFILLTUNING; /* Host transmit pre-buffer packet tuning (host mode) */
+ __I uint32_t RESERVED4[2];
+ __IO uint32_t ULPIVIEWPORT; /* ULPI viewport */
+ __IO uint32_t BINTERVAL; /* Length of virtual frame */
+ __IO uint32_t ENDPTNAK; /* Endpoint NAK (device mode) */
+ __IO uint32_t ENDPTNAKEN; /* Endpoint NAK Enable (device mode) */
+ __I uint32_t RESERVED5;
+ union {
+ __IO uint32_t PORTSC1_H; /* Port 1 status/control (host mode) */
+ __IO uint32_t PORTSC1_D; /* Port 1 status/control (device mode) */
+ };
+
+ __I uint32_t RESERVED6[7];
+ __IO uint32_t OTGSC; /* OTG status and control */
+ union {
+ __IO uint32_t USBMODE_H; /* USB mode (host mode) */
+ __IO uint32_t USBMODE_D; /* USB mode (device mode) */
+ };
+
+ __IO uint32_t ENDPTSETUPSTAT; /* Endpoint setup status */
+ __IO uint32_t ENDPTPRIME; /* Endpoint initialization */
+ __IO uint32_t ENDPTFLUSH; /* Endpoint de-initialization */
+ __I uint32_t ENDPTSTAT; /* Endpoint status */
+ __IO uint32_t ENDPTCOMPLETE; /* Endpoint complete */
+ __IO uint32_t ENDPTCTRL[6]; /* Endpoint control 0 */
+} LPC_USBHS_T;
+
+/* ---------------------------------------------------------------------------
+ * LCD Controller register block structure
+ */
+#define LPC_LCD_BASE 0x40008000
+
+typedef struct { /* LCD Structure */
+ __IO uint32_t TIMH; /* Horizontal Timing Control register */
+ __IO uint32_t TIMV; /* Vertical Timing Control register */
+ __IO uint32_t POL; /* Clock and Signal Polarity Control register */
+ __IO uint32_t LE; /* Line End Control register */
+ __IO uint32_t UPBASE; /* Upper Panel Frame Base Address register */
+ __IO uint32_t LPBASE; /* Lower Panel Frame Base Address register */
+ __IO uint32_t CTRL; /* LCD Control register */
+ __IO uint32_t INTMSK; /* Interrupt Mask register */
+ __I uint32_t INTRAW; /* Raw Interrupt Status register */
+ __I uint32_t INTSTAT; /* Masked Interrupt Status register */
+ __O uint32_t INTCLR; /* Interrupt Clear register */
+ __I uint32_t UPCURR; /* Upper Panel Current Address Value register */
+ __I uint32_t LPCURR; /* Lower Panel Current Address Value register */
+ __I uint32_t RESERVED0[115];
+ __IO uint16_t PAL[256]; /* 256x16-bit Color Palette registers */
+ __I uint32_t RESERVED1[256];
+ __IO uint32_t CRSR_IMG[256];/* Cursor Image registers */
+ __IO uint32_t CRSR_CTRL; /* Cursor Control register */
+ __IO uint32_t CRSR_CFG; /* Cursor Configuration register */
+ __IO uint32_t CRSR_PAL0; /* Cursor Palette register 0 */
+ __IO uint32_t CRSR_PAL1; /* Cursor Palette register 1 */
+ __IO uint32_t CRSR_XY; /* Cursor XY Position register */
+ __IO uint32_t CRSR_CLIP; /* Cursor Clip Position register */
+ __I uint32_t RESERVED2[2];
+ __IO uint32_t CRSR_INTMSK; /* Cursor Interrupt Mask register */
+ __O uint32_t CRSR_INTCLR; /* Cursor Interrupt Clear register */
+ __I uint32_t CRSR_INTRAW; /* Cursor Raw Interrupt Status register */
+ __I uint32_t CRSR_INTSTAT;/* Cursor Masked Interrupt Status register */
+} LPC_LCD_T;
+
+/* ---------------------------------------------------------------------------
+ * EEPROM register block structure
+ */
+#define LPC_EEPROM_BASE 0x4000E000
+
+typedef struct { /* EEPROM Structure */
+ __IO uint32_t CMD; /* EEPROM command register */
+ uint32_t RESERVED0;
+ __IO uint32_t RWSTATE; /* EEPROM read wait state register */
+ __IO uint32_t AUTOPROG; /* EEPROM auto programming register */
+ __IO uint32_t WSTATE; /* EEPROM wait state register */
+ __IO uint32_t CLKDIV; /* EEPROM clock divider register */
+ __IO uint32_t PWRDWN; /* EEPROM power-down register */
+ uint32_t RESERVED2[1007];
+ __O uint32_t INTENCLR; /* EEPROM interrupt enable clear */
+ __O uint32_t INTENSET; /* EEPROM interrupt enable set */
+ __I uint32_t INTSTAT; /* EEPROM interrupt status */
+ __I uint32_t INTEN; /* EEPROM interrupt enable */
+ __O uint32_t INTSTATCLR; /* EEPROM interrupt status clear */
+ __O uint32_t INTSTATSET; /* EEPROM interrupt status set */
+} LPC_EEPROM_T;
+
+/* ---------------------------------------------------------------------------
+ * 10/100 MII & RMII Ethernet with timestamping register block structure
+ */
+#define LPC_ETHERNET_BASE 0x40010000
+
+typedef struct { /* ETHERNET Structure */
+ __IO uint32_t MAC_CONFIG; /* MAC configuration register */
+ __IO uint32_t MAC_FRAME_FILTER; /* MAC frame filter */
+ __IO uint32_t MAC_HASHTABLE_HIGH; /* Hash table high register */
+ __IO uint32_t MAC_HASHTABLE_LOW; /* Hash table low register */
+ __IO uint32_t MAC_MII_ADDR; /* MII address register */
+ __IO uint32_t MAC_MII_DATA; /* MII data register */
+ __IO uint32_t MAC_FLOW_CTRL; /* Flow control register */
+ __IO uint32_t MAC_VLAN_TAG; /* VLAN tag register */
+ __I uint32_t RESERVED0;
+ __I uint32_t MAC_DEBUG; /* Debug register */
+ __IO uint32_t MAC_RWAKE_FRFLT; /* Remote wake-up frame filter */
+ __IO uint32_t MAC_PMT_CTRL_STAT; /* PMT control and status */
+ __I uint32_t RESERVED1[2];
+ __I uint32_t MAC_INTR; /* Interrupt status register */
+ __IO uint32_t MAC_INTR_MASK; /* Interrupt mask register */
+ __IO uint32_t MAC_ADDR0_HIGH; /* MAC address 0 high register */
+ __IO uint32_t MAC_ADDR0_LOW; /* MAC address 0 low register */
+ __I uint32_t RESERVED2[430];
+ __IO uint32_t MAC_TIMESTP_CTRL; /* Time stamp control register */
+ __IO uint32_t SUBSECOND_INCR; /* Sub-second increment register */
+ __I uint32_t SECONDS; /* System time seconds register */
+ __I uint32_t NANOSECONDS; /* System time nanoseconds register */
+ __IO uint32_t SECONDSUPDATE; /* System time seconds update register */
+ __IO uint32_t NANOSECONDSUPDATE; /* System time nanoseconds update register */
+ __IO uint32_t ADDEND; /* Time stamp addend register */
+ __IO uint32_t TARGETSECONDS; /* Target time seconds register */
+ __IO uint32_t TARGETNANOSECONDS; /* Target time nanoseconds register */
+ __IO uint32_t HIGHWORD; /* System time higher word seconds register */
+ __I uint32_t TIMESTAMPSTAT; /* Time stamp status register */
+ __IO uint32_t PPSCTRL; /* PPS control register */
+ __I uint32_t AUXNANOSECONDS; /* Auxiliary time stamp nanoseconds register */
+ __I uint32_t AUXSECONDS; /* Auxiliary time stamp seconds register */
+ __I uint32_t RESERVED3[562];
+ __IO uint32_t DMA_BUS_MODE; /* Bus Mode Register */
+ __IO uint32_t DMA_TRANS_POLL_DEMAND; /* Transmit poll demand register */
+ __IO uint32_t DMA_REC_POLL_DEMAND; /* Receive poll demand register */
+ __IO uint32_t DMA_REC_DES_ADDR; /* Receive descriptor list address register */
+ __IO uint32_t DMA_TRANS_DES_ADDR; /* Transmit descriptor list address register */
+ __IO uint32_t DMA_STAT; /* Status register */
+ __IO uint32_t DMA_OP_MODE; /* Operation mode register */
+ __IO uint32_t DMA_INT_EN; /* Interrupt enable register */
+ __I uint32_t DMA_MFRM_BUFOF; /* Missed frame and buffer overflow register */
+ __IO uint32_t DMA_REC_INT_WDT; /* Receive interrupt watchdog timer register */
+ __I uint32_t RESERVED4[8];
+ __I uint32_t DMA_CURHOST_TRANS_DES; /* Current host transmit descriptor register */
+ __I uint32_t DMA_CURHOST_REC_DES; /* Current host receive descriptor register */
+ __I uint32_t DMA_CURHOST_TRANS_BUF; /* Current host transmit buffer address register */
+ __I uint32_t DMA_CURHOST_REC_BUF; /* Current host receive buffer address register */
+} LPC_ENET_T;
+
+/* ---------------------------------------------------------------------------
+ * Alarm Timer register block structure
+ */
+#define LPC_ATIMER_BASE 0x40040000
+
+typedef struct { /* ATIMER Structure */
+ __IO uint32_t DOWNCOUNTER; /* Downcounter register */
+ __IO uint32_t PRESET; /* Preset value register */
+ __I uint32_t RESERVED0[1012];
+ __O uint32_t CLR_EN; /* Interrupt clear enable register */
+ __O uint32_t SET_EN; /* Interrupt set enable register */
+ __I uint32_t STATUS; /* Status register */
+ __I uint32_t ENABLE; /* Enable register */
+ __O uint32_t CLR_STAT; /* Clear register */
+ __O uint32_t SET_STAT; /* Set register */
+} LPC_ATIMER_T;
+
+/* ---------------------------------------------------------------------------
+ * Register File register block structure
+ */
+#define LPC_REGFILE_BASE 0x40041000
+
+typedef struct {
+ __IO uint32_t REGFILE[64]; /* General purpose storage register */
+} LPC_REGFILE_T;
+
+/* ---------------------------------------------------------------------------
+ * Power Management Controller register block structure
+ */
+#define LPC_PMC_BASE 0x40042000
+
+typedef struct { /* PMC Structure */
+ __IO uint32_t PD0_SLEEP0_HW_ENA; /* Hardware sleep event enable register */
+ __I uint32_t RESERVED0[6];
+ __IO uint32_t PD0_SLEEP0_MODE; /* Sleep power mode register */
+} LPC_PMC_T;
+
+/* ---------------------------------------------------------------------------
+ * CREG Register Block
+ */
+#define LPC_CREG_BASE 0x40043000
+
+typedef struct { /* CREG Structure */
+ __I uint32_t RESERVED0;
+ __IO uint32_t CREG0; /* Chip configuration register 32 kHz oscillator output and BOD control register. */
+ __I uint32_t RESERVED1[62];
+ __IO uint32_t MXMEMMAP; /* ARM Cortex-M3/M4 memory mapping */
+#if defined(CHIP_LPC18XX)
+ __I uint32_t RESERVED2[5];
+#else
+ __I uint32_t RESERVED2;
+ __I uint32_t CREG1; /* Configuration Register 1 */
+ __I uint32_t CREG2; /* Configuration Register 2 */
+ __I uint32_t CREG3; /* Configuration Register 3 */
+ __I uint32_t CREG4; /* Configuration Register 4 */
+#endif
+ __IO uint32_t CREG5; /* Chip configuration register 5. Controls JTAG access. */
+ __IO uint32_t DMAMUX; /* DMA muxing control */
+ __IO uint32_t FLASHCFGA; /* Flash accelerator configuration register for flash bank A */
+ __IO uint32_t FLASHCFGB; /* Flash accelerator configuration register for flash bank B */
+ __IO uint32_t ETBCFG; /* ETB RAM configuration */
+ __IO uint32_t CREG6; /* Chip configuration register 6. */
+#if defined(CHIP_LPC18XX)
+ __I uint32_t RESERVED4[52];
+#else
+ __IO uint32_t M4TXEVENT; /* M4 IPC event register */
+ __I uint32_t RESERVED4[51];
+#endif
+ __I uint32_t CHIPID; /* Part ID */
+#if defined(CHIP_LPC18XX)
+ __I uint32_t RESERVED5[191];
+#else
+ __I uint32_t RESERVED5[127];
+ __IO uint32_t M0TXEVENT; /* M0 IPC Event register */
+ __IO uint32_t M0APPMEMMAP; /* ARM Cortex M0 memory mapping */
+ __I uint32_t RESERVED6[62];
+#endif
+ __IO uint32_t USB0FLADJ; /* USB0 frame length adjust register */
+ __I uint32_t RESERVED7[63];
+ __IO uint32_t USB1FLADJ; /* USB1 frame length adjust register */
+} LPC_CREG_T;
+
+/* ---------------------------------------------------------------------------
+ * Event Router register structure
+ */
+#define LPC_EVRT_BASE 0x40044000
+
+typedef struct { /* EVENTROUTER Structure */
+ __IO uint32_t HILO; /* Level configuration register */
+ __IO uint32_t EDGE; /* Edge configuration */
+ __I uint32_t RESERVED0[1012];
+ __O uint32_t CLR_EN; /* Event clear enable register */
+ __O uint32_t SET_EN; /* Event set enable register */
+ __I uint32_t STATUS; /* Status register */
+ __I uint32_t ENABLE; /* Enable register */
+ __O uint32_t CLR_STAT; /* Clear register */
+ __O uint32_t SET_STAT; /* Set register */
+} LPC_EVRT_T;
+
+/* ---------------------------------------------------------------------------
+ * Real Time Clock register block structure
+ */
+#define LPC_RTC_BASE 0x40046000
+#define RTC_EV_SUPPORT 1 /* Event Monitor/Recorder support */
+
+typedef enum RTC_TIMEINDEX {
+ RTC_TIMETYPE_SECOND, /* Second */
+ RTC_TIMETYPE_MINUTE, /* Month */
+ RTC_TIMETYPE_HOUR, /* Hour */
+ RTC_TIMETYPE_DAYOFMONTH, /* Day of month */
+ RTC_TIMETYPE_DAYOFWEEK, /* Day of week */
+ RTC_TIMETYPE_DAYOFYEAR, /* Day of year */
+ RTC_TIMETYPE_MONTH, /* Month */
+ RTC_TIMETYPE_YEAR, /* Year */
+ RTC_TIMETYPE_LAST
+} RTC_TIMEINDEX_T;
+
+#if RTC_EV_SUPPORT
+typedef enum LPC_RTC_EV_CHANNEL {
+ RTC_EV_CHANNEL_1 = 0,
+ RTC_EV_CHANNEL_2,
+ RTC_EV_CHANNEL_3,
+ RTC_EV_CHANNEL_NUM,
+} LPC_RTC_EV_CHANNEL_T;
+#endif /*RTC_EV_SUPPORT*/
+
+typedef struct { /* RTC Structure */
+ __IO uint32_t ILR; /* Interrupt Location Register */
+ __I uint32_t RESERVED0;
+ __IO uint32_t CCR; /* Clock Control Register */
+ __IO uint32_t CIIR; /* Counter Increment Interrupt Register */
+ __IO uint32_t AMR; /* Alarm Mask Register */
+ __I uint32_t CTIME[3]; /* Consolidated Time Register 0,1,2 */
+ __IO uint32_t TIME[RTC_TIMETYPE_LAST]; /* Timer field registers */
+ __IO uint32_t CALIBRATION; /* Calibration Value Register */
+ __I uint32_t RESERVED1[7];
+ __IO uint32_t ALRM[RTC_TIMETYPE_LAST]; /* Alarm field registers */
+#if RTC_EV_SUPPORT
+ __IO uint32_t ERSTATUS; /* Event Monitor/Recorder Status register*/
+ __IO uint32_t ERCONTROL; /* Event Monitor/Recorder Control register*/
+ __I uint32_t ERCOUNTERS; /* Event Monitor/Recorder Counters register*/
+ __I uint32_t RESERVED2;
+ __I uint32_t ERFIRSTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder First Stamp registers*/
+ __I uint32_t RESERVED3;
+ __I uint32_t ERLASTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder Last Stamp registers*/
+#endif /*RTC_EV_SUPPORT*/
+} LPC_RTC_T;
+
+/* ---------------------------------------------------------------------------
+ * LPC18XX/43XX CGU register block structure
+ */
+#define LPC_CGU_BASE 0x40050000
+#define LPC_CCU1_BASE 0x40051000
+#define LPC_CCU2_BASE 0x40052000
+/*
+ * Input clocks for the CGU and can come from both external (crystal) and
+ * internal (PLL) sources. Can be routed to the base clocks.
+ */
+typedef enum CGU_CLKIN {
+ CLKIN_32K, /* External 32KHz input */
+ CLKIN_IRC, /* Internal IRC (12MHz) input */
+ CLKIN_ENET_RX, /* External ENET_RX pin input */
+ CLKIN_ENET_TX, /* External ENET_TX pin input */
+ CLKIN_CLKIN, /* External GPCLKIN pin input */
+ CLKIN_RESERVED1,
+ CLKIN_CRYSTAL, /* External (main) crystal pin input */
+ CLKIN_USBPLL, /* Internal USB PLL input */
+ CLKIN_AUDIOPLL, /* Internal Audio PLL input */
+ CLKIN_MAINPLL, /* Internal Main PLL input */
+ CLKIN_RESERVED2,
+ CLKIN_RESERVED3,
+ CLKIN_IDIVA, /* Internal divider A input */
+ CLKIN_IDIVB, /* Internal divider B input */
+ CLKIN_IDIVC, /* Internal divider C input */
+ CLKIN_IDIVD, /* Internal divider D input */
+ CLKIN_IDIVE, /* Internal divider E input */
+ CLKINPUT_PD /* External 32KHz input */
+} CGU_CLKIN_T;
+
+#define CLKIN_PLL0USB CLKIN_USBPLL
+#define CLKIN_PLL0AUDIO CLKIN_AUDIOPLL
+#define CLKIN_PLL1 CLKIN_MAINPLL
+
+/*
+ * CGU base clocks are clocks that are associated with a single input clock
+ * and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH
+ * clock can be configured to use the CLKIN_MAINPLL input clock, which will in
+ * turn route that clock to the CLK_PERIPH_BUS, CLK_PERIPH_CORE, and
+ * CLK_PERIPH_SGPIO periphral clocks.
+ */
+typedef enum CGU_BASE_CLK {
+ CLK_BASE_SAFE, /* Base clock for WDT oscillator, IRC input only */
+ CLK_BASE_USB0, /* Base USB clock for USB0, USB PLL input only */
+#if defined(CHIP_LPC43XX)
+ CLK_BASE_PERIPH, /* Base clock for SGPIO */
+#else
+ CLK_BASE_RESERVED1,
+#endif
+ CLK_BASE_USB1, /* Base USB clock for USB1 */
+ CLK_BASE_MX, /* Base clock for CPU core */
+ CLK_BASE_SPIFI, /* Base clock for SPIFI */
+#if defined(CHIP_LPC43XX)
+ CLK_BASE_SPI, /* Base clock for SPI */
+#else
+ CLK_BASE_RESERVED2,
+#endif
+ CLK_BASE_PHY_RX, /* Base clock for PHY RX */
+ CLK_BASE_PHY_TX, /* Base clock for PHY TX */
+ CLK_BASE_APB1, /* Base clock for APB1 group */
+ CLK_BASE_APB3, /* Base clock for APB3 group */
+ CLK_BASE_LCD, /* Base clock for LCD pixel clock */
+#if defined(CHIP_LPC43XX)
+ CLK_BASE_VADC, /* Base clock for VADC */
+#else
+ CLK_BASE_RESERVED3,
+#endif
+ CLK_BASE_SDIO, /* Base clock for SDIO */
+ CLK_BASE_SSP0, /* Base clock for SSP0 */
+ CLK_BASE_SSP1, /* Base clock for SSP1 */
+ CLK_BASE_UART0, /* Base clock for UART0 */
+ CLK_BASE_UART1, /* Base clock for UART1 */
+ CLK_BASE_UART2, /* Base clock for UART2 */
+ CLK_BASE_UART3, /* Base clock for UART3 */
+ CLK_BASE_OUT, /* Base clock for CLKOUT pin */
+ CLK_BASE_RESERVED4,
+ CLK_BASE_RESERVED5,
+ CLK_BASE_RESERVED6,
+ CLK_BASE_RESERVED7,
+ CLK_BASE_APLL, /* Base clock for audio PLL */
+ CLK_BASE_CGU_OUT0, /* Base clock for CGUOUT0 pin */
+ CLK_BASE_CGU_OUT1, /* Base clock for CGUOUT1 pin */
+ CLK_BASE_LAST,
+ CLK_BASE_NONE = CLK_BASE_LAST
+} CGU_BASE_CLK_T;
+
+/*
+ * CGU dividers provide an extra clock state where a specific clock can be
+ * divided before being routed to a peripheral group. A divider accepts an
+ * input clock and then divides it. To use the divided clock for a base clock
+ * group, use the divider as the input clock for the base clock (for example,
+ * use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider).
+ */
+typedef enum CGU_IDIV {
+ CLK_IDIV_A, /* CGU clock divider A */
+ CLK_IDIV_B, /* CGU clock divider B */
+ CLK_IDIV_C, /* CGU clock divider A */
+ CLK_IDIV_D, /* CGU clock divider D */
+ CLK_IDIV_E, /* CGU clock divider E */
+ CLK_IDIV_LAST
+} CGU_IDIV_T;
+
+/*
+ * Peripheral clocks are individual clocks routed to peripherals. Although
+ * multiple peripherals may share a same base clock, each peripheral's clock
+ * can be enabled or disabled individually. Some peripheral clocks also have
+ * additional dividers associated with them.
+ */
+typedef enum CCU_CLK {
+ /* CCU1 clocks */
+ CLK_APB3_BUS, /* APB3 bus clock from base clock CLK_BASE_APB3 */
+ CLK_APB3_I2C1, /* I2C1 register/perigheral clock from base clock CLK_BASE_APB3 */
+ CLK_APB3_DAC, /* DAC peripheral clock from base clock CLK_BASE_APB3 */
+ CLK_APB3_ADC0, /* ADC0 register/perigheral clock from base clock CLK_BASE_APB3 */
+ CLK_APB3_ADC1, /* ADC1 register/perigheral clock from base clock CLK_BASE_APB3 */
+ CLK_APB3_CAN0, /* CAN0 register/perigheral clock from base clock CLK_BASE_APB3 */
+ CLK_APB1_BUS = 32, /* APB1 bus clock clock from base clock CLK_BASE_APB1 */
+ CLK_APB1_MOTOCON, /* Motor controller register/perigheral clock from base clock CLK_BASE_APB1 */
+ CLK_APB1_I2C0, /* I2C0 register/perigheral clock from base clock CLK_BASE_APB1 */
+ CLK_APB1_I2S, /* I2S register/perigheral clock from base clock CLK_BASE_APB1 */
+ CLK_APB1_CAN1, /* CAN1 register/perigheral clock from base clock CLK_BASE_APB1 */
+ CLK_SPIFI = 64, /* SPIFI SCKI input clock from base clock CLK_BASE_SPIFI */
+ CLK_MX_BUS = 96, /* M3/M4 BUS core clock from base clock CLK_BASE_MX */
+ CLK_MX_SPIFI, /* SPIFI register clock from base clock CLK_BASE_MX */
+ CLK_MX_GPIO, /* GPIO register clock from base clock CLK_BASE_MX */
+ CLK_MX_LCD, /* LCD register clock from base clock CLK_BASE_MX */
+ CLK_MX_ETHERNET, /* ETHERNET register clock from base clock CLK_BASE_MX */
+ CLK_MX_USB0, /* USB0 register clock from base clock CLK_BASE_MX */
+ CLK_MX_EMC, /* EMC clock from base clock CLK_BASE_MX */
+ CLK_MX_SDIO, /* SDIO register clock from base clock CLK_BASE_MX */
+ CLK_MX_DMA, /* DMA register clock from base clock CLK_BASE_MX */
+ CLK_MX_MXCORE, /* M3/M4 CPU core clock from base clock CLK_BASE_MX */
+ RESERVED_ALIGN = CLK_MX_MXCORE + 3,
+ CLK_MX_SCT, /* SCT register clock from base clock CLK_BASE_MX */
+ CLK_MX_USB1, /* USB1 register clock from base clock CLK_BASE_MX */
+ CLK_MX_EMC_DIV, /* ENC divider clock from base clock CLK_BASE_MX */
+ CLK_MX_FLASHA, /* FLASHA bank clock from base clock CLK_BASE_MX */
+ CLK_MX_FLASHB, /* FLASHB bank clock from base clock CLK_BASE_MX */
+#if defined(CHIP_LPC43XX)
+ CLK_M4_M0APP, /* M0 app CPU core clock from base clock CLK_BASE_MX */
+ CLK_MX_VADC, /* VADC clock from base clock CLK_BASE_MX */
+#else
+ CLK_RESERVED1,
+ CLK_RESERVED2,
+#endif
+ CLK_MX_EEPROM, /* EEPROM clock from base clock CLK_BASE_MX */
+ CLK_MX_WWDT = 128, /* WWDT register clock from base clock CLK_BASE_MX */
+ CLK_MX_UART0, /* UART0 register clock from base clock CLK_BASE_MX */
+ CLK_MX_UART1, /* UART1 register clock from base clock CLK_BASE_MX */
+ CLK_MX_SSP0, /* SSP0 register clock from base clock CLK_BASE_MX */
+ CLK_MX_TIMER0, /* TIMER0 register/perigheral clock from base clock CLK_BASE_MX */
+ CLK_MX_TIMER1, /* TIMER1 register/perigheral clock from base clock CLK_BASE_MX */
+ CLK_MX_SCU, /* SCU register/perigheral clock from base clock CLK_BASE_MX */
+ CLK_MX_CREG, /* CREG clock from base clock CLK_BASE_MX */
+ CLK_MX_RITIMER = 160, /* RITIMER register/perigheral clock from base clock CLK_BASE_MX */
+ CLK_MX_UART2, /* UART3 register clock from base clock CLK_BASE_MX */
+ CLK_MX_UART3, /* UART4 register clock from base clock CLK_BASE_MX */
+ CLK_MX_TIMER2, /* TIMER2 register/perigheral clock from base clock CLK_BASE_MX */
+ CLK_MX_TIMER3, /* TIMER3 register/perigheral clock from base clock CLK_BASE_MX */
+ CLK_MX_SSP1, /* SSP1 register clock from base clock CLK_BASE_MX */
+ CLK_MX_QEI, /* QEI register/perigheral clock from base clock CLK_BASE_MX */
+#if defined(CHIP_LPC43XX)
+ CLK_PERIPH_BUS = 192, /* Peripheral bus clock from base clock CLK_BASE_PERIPH */
+ CLK_RESERVED3,
+ CLK_PERIPH_CORE, /* Peripheral core clock from base clock CLK_BASE_PERIPH */
+ CLK_PERIPH_SGPIO, /* SGPIO clock from base clock CLK_BASE_PERIPH */
+#else
+ CLK_RESERVED3 = 192,
+ CLK_RESERVED3A,
+ CLK_RESERVED4,
+ CLK_RESERVED5,
+#endif
+ CLK_USB0 = 224, /* USB0 clock from base clock CLK_BASE_USB0 */
+ CLK_USB1 = 256, /* USB1 clock from base clock CLK_BASE_USB1 */
+#if defined(CHIP_LPC43XX)
+ CLK_SPI = 288, /* SPI clock from base clock CLK_BASE_SPI */
+ CLK_VADC, /* VADC clock from base clock CLK_BASE_VADC */
+#else
+ CLK_RESERVED7 = 320,
+ CLK_RESERVED8,
+#endif
+ CLK_CCU1_LAST,
+
+ /* CCU2 clocks */
+ CLK_CCU2_START,
+ CLK_APLL = CLK_CCU2_START, /* Audio PLL clock from base clock CLK_BASE_APLL */
+ RESERVED_ALIGNB = CLK_CCU2_START + 31,
+ CLK_APB2_UART3, /* UART3 clock from base clock CLK_BASE_UART3 */
+ RESERVED_ALIGNC = CLK_CCU2_START + 63,
+ CLK_APB2_UART2, /* UART2 clock from base clock CLK_BASE_UART2 */
+ RESERVED_ALIGND = CLK_CCU2_START + 95,
+ CLK_APB0_UART1, /* UART1 clock from base clock CLK_BASE_UART1 */
+ RESERVED_ALIGNE = CLK_CCU2_START + 127,
+ CLK_APB0_UART0, /* UART0 clock from base clock CLK_BASE_UART0 */
+ RESERVED_ALIGNF = CLK_CCU2_START + 159,
+ CLK_APB2_SSP1, /* SSP1 clock from base clock CLK_BASE_SSP1 */
+ RESERVED_ALIGNG = CLK_CCU2_START + 191,
+ CLK_APB0_SSP0, /* SSP0 clock from base clock CLK_BASE_SSP0 */
+ RESERVED_ALIGNH = CLK_CCU2_START + 223,
+ CLK_APB2_SDIO, /* SDIO clock from base clock CLK_BASE_SDIO */
+ CLK_CCU2_LAST
+} CCU_CLK_T;
+
+/*
+ * Audio or USB PLL selection
+ */
+typedef enum CGU_USB_AUDIO_PLL {
+ CGU_USB_PLL,
+ CGU_AUDIO_PLL
+} CGU_USB_AUDIO_PLL_T;
+
+/*
+ * PLL register block
+ */
+typedef struct {
+ __I uint32_t PLL_STAT; /* PLL status register */
+ __IO uint32_t PLL_CTRL; /* PLL control register */
+ __IO uint32_t PLL_MDIV; /* PLL M-divider register */
+ __IO uint32_t PLL_NP_DIV; /* PLL N/P-divider register */
+} CGU_PLL_REG_T;
+
+typedef struct { /* (@ 0x40050000) CGU Structure */
+ __I uint32_t RESERVED0[5];
+ __IO uint32_t FREQ_MON; /* (@ 0x40050014) Frequency monitor register */
+ __IO uint32_t XTAL_OSC_CTRL; /* (@ 0x40050018) Crystal oscillator control register */
+ CGU_PLL_REG_T PLL[CGU_AUDIO_PLL + 1]; /* (@ 0x4005001C) USB and audio PLL blocks */
+ __IO uint32_t PLL0AUDIO_FRAC; /* (@ 0x4005003C) PLL0 (audio) */
+ __I uint32_t PLL1_STAT; /* (@ 0x40050040) PLL1 status register */
+ __IO uint32_t PLL1_CTRL; /* (@ 0x40050044) PLL1 control register */
+ __IO uint32_t IDIV_CTRL[CLK_IDIV_LAST];/* (@ 0x40050048) Integer divider A-E control registers */
+ __IO uint32_t BASE_CLK[CLK_BASE_LAST]; /* (@ 0x4005005C) Start of base clock registers */
+} LPC_CGU_T;
+
+/* ---------------------------------------------------------------------------
+ * CCU clock config/status register pair
+ */
+typedef struct {
+ __IO uint32_t CFG; /* CCU clock configuration register */
+ __I uint32_t STAT; /* CCU clock status register */
+} CCU_CFGSTAT_T;
+
+/* ---------------------------------------------------------------------------
+ * CCU1 register block structure
+ */
+typedef struct { /* (@ 0x40051000) CCU1 Structure */
+ __IO uint32_t PM; /* (@ 0x40051000) CCU1 power mode register */
+ __I uint32_t BASE_STAT; /* (@ 0x40051004) CCU1 base clocks status register */
+ __I uint32_t RESERVED0[62];
+ CCU_CFGSTAT_T CLKCCU[CLK_CCU1_LAST]; /* (@ 0x40051100) Start of CCU1 clock registers */
+} LPC_CCU1_T;
+
+/* ---------------------------------------------------------------------------
+ * CCU2 register block structure
+ */
+typedef struct { /* (@ 0x40052000) CCU2 Structure */
+ __IO uint32_t PM; /* (@ 0x40052000) Power mode register */
+ __I uint32_t BASE_STAT; /* (@ 0x40052004) CCU base clocks status register */
+ __I uint32_t RESERVED0[62];
+ CCU_CFGSTAT_T CLKCCU[CLK_CCU2_LAST - CLK_CCU1_LAST]; /* (@ 0x40052100) Start of CCU2 clock registers */
+} LPC_CCU2_T;
+
+/* ---------------------------------------------------------------------------
+ * RGU register structure
+ */
+#define LPC_RGU_BASE 0x40053000
+
+typedef enum RGU_RST {
+ RGU_CORE_RST,
+ RGU_PERIPH_RST,
+ RGU_MASTER_RST,
+ RGU_WWDT_RST = 4,
+ RGU_CREG_RST,
+ RGU_BUS_RST = 8,
+ RGU_SCU_RST,
+ RGU_M3_RST = 13,
+ RGU_LCD_RST = 16,
+ RGU_USB0_RST,
+ RGU_USB1_RST,
+ RGU_DMA_RST,
+ RGU_SDIO_RST,
+ RGU_EMC_RST,
+ RGU_ETHERNET_RST,
+ RGU_FLASHA_RST = 25,
+ RGU_EEPROM_RST = 27,
+ RGU_GPIO_RST,
+ RGU_FLASHB_RST,
+ RGU_TIMER0_RST = 32,
+ RGU_TIMER1_RST,
+ RGU_TIMER2_RST,
+ RGU_TIMER3_RST,
+ RGU_RITIMER_RST,
+ RGU_SCT_RST,
+ RGU_MOTOCONPWM_RST,
+ RGU_QEI_RST,
+ RGU_ADC0_RST,
+ RGU_ADC1_RST,
+ RGU_DAC_RST,
+ RGU_UART0_RST = 44,
+ RGU_UART1_RST,
+ RGU_UART2_RST,
+ RGU_UART3_RST,
+ RGU_I2C0_RST,
+ RGU_I2C1_RST,
+ RGU_SSP0_RST,
+ RGU_SSP1_RST,
+ RGU_I2S_RST,
+ RGU_SPIFI_RST,
+ RGU_CAN1_RST,
+ RGU_CAN0_RST,
+#ifdef CHIP_LPC43XX
+ RGU_M0APP_RST,
+ RGU_SGPIO_RST,
+ RGU_SPI_RST,
+#endif
+ RGU_LAST_RST = 63,
+} RGU_RST_T;
+
+typedef struct { /* RGU Structure */
+ __I uint32_t RESERVED0[64];
+ __O uint32_t RESET_CTRL0; /* Reset control register 0 */
+ __O uint32_t RESET_CTRL1; /* Reset control register 1 */
+ __I uint32_t RESERVED1[2];
+ __IO uint32_t RESET_STATUS0; /* Reset status register 0 */
+ __IO uint32_t RESET_STATUS1; /* Reset status register 1 */
+ __IO uint32_t RESET_STATUS2; /* Reset status register 2 */
+ __IO uint32_t RESET_STATUS3; /* Reset status register 3 */
+ __I uint32_t RESERVED2[12];
+ __I uint32_t RESET_ACTIVE_STATUS0;/* Reset active status register 0 */
+ __I uint32_t RESET_ACTIVE_STATUS1;/* Reset active status register 1 */
+ __I uint32_t RESERVED3[170];
+ __IO uint32_t RESET_EXT_STAT[RGU_LAST_RST + 1];/* Reset external status registers */
+} LPC_RGU_T;
+
+/* ---------------------------------------------------------------------------
+ * Windowed Watchdog register block structure
+ */
+#define LPC_WWDT_BASE 0x40080000
+
+typedef struct { /* WWDT Structure */
+ __IO uint32_t MOD; /* Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
+ __IO uint32_t TC; /* Watchdog timer constant register. This register determines the time-out value. */
+ __O uint32_t FEED; /* Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
+ __I uint32_t TV; /* Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
+#ifdef WATCHDOG_CLKSEL_SUPPORT
+ __IO uint32_t CLKSEL; /* Watchdog clock select register. */
+#else
+ __I uint32_t RESERVED0;
+#endif
+#ifdef WATCHDOG_WINDOW_SUPPORT
+ __IO uint32_t WARNINT; /* Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */
+ __IO uint32_t WINDOW; /* Watchdog timer window register. This register contains the Watchdog window value. */
+#endif
+} LPC_WWDT_T;
+
+/* ---------------------------------------------------------------------------
+ * USART register block structure
+ */
+#define LPC_USART0_BASE 0x40081000
+#define LPC_UART1_BASE 0x40082000
+#define LPC_USART2_BASE 0x400C1000
+#define LPC_USART3_BASE 0x400C2000
+
+typedef struct { /* USARTn Structure */
+
+ union {
+ __IO uint32_t DLL; /* Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
+ __O uint32_t THR; /* Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
+ __I uint32_t RBR; /* Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
+ };
+
+ union {
+ __IO uint32_t IER; /* Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
+ __IO uint32_t DLM; /* Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
+ };
+
+ union {
+ __O uint32_t FCR; /* FIFO Control Register. Controls UART FIFO usage and modes. */
+ __I uint32_t IIR; /* Interrupt ID Register. Identifies which interrupt(s) are pending. */
+ };
+
+ __IO uint32_t LCR; /* Line Control Register. Contains controls for frame formatting and break generation. */
+ __IO uint32_t MCR; /* Modem Control Register. Only present on USART ports with full modem support. */
+ __I uint32_t LSR; /* Line Status Register. Contains flags for transmit and receive status, including line errors. */
+ __I uint32_t MSR; /* Modem Status Register. Only present on USART ports with full modem support. */
+ __IO uint32_t SCR; /* Scratch Pad Register. Eight-bit temporary storage for software. */
+ __IO uint32_t ACR; /* Auto-baud Control Register. Contains controls for the auto-baud feature. */
+ __IO uint32_t ICR; /* IrDA control register (not all UARTS) */
+ __IO uint32_t FDR; /* Fractional Divider Register. Generates a clock input for the baud rate divider. */
+ __IO uint32_t OSR; /* Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. */
+ __IO uint32_t TER1; /* Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
+ uint32_t RESERVED0[3];
+ __IO uint32_t HDEN; /* Half-duplex enable Register- only on some UARTs */
+ __I uint32_t RESERVED1[1];
+ __IO uint32_t SCICTRL; /* Smart card interface control register- only on some UARTs */
+ __IO uint32_t RS485CTRL; /* RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
+ __IO uint32_t RS485ADRMATCH; /* RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
+ __IO uint32_t RS485DLY; /* RS-485/EIA-485 direction control delay. */
+ union {
+ __IO uint32_t SYNCCTRL; /* Synchronous mode control register. Only on USARTs. */
+ __I uint32_t FIFOLVL; /* FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
+ };
+
+ __IO uint32_t TER2; /* Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. */
+} LPC_USART_T;
+
+/* ---------------------------------------------------------------------------
+ * SSP register block structure
+ */
+#define LPC_SSP0_BASE 0x40083000
+#define LPC_SSP1_BASE 0x400C5000
+
+typedef struct { /* SSPn Structure */
+ __IO uint32_t CR0; /* Control Register 0. Selects the serial clock rate, bus type, and data size. */
+ __IO uint32_t CR1; /* Control Register 1. Selects master/slave and other modes. */
+ __IO uint32_t DR; /* Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
+ __I uint32_t SR; /* Status Register */
+ __IO uint32_t CPSR; /* Clock Prescale Register */
+ __IO uint32_t IMSC; /* Interrupt Mask Set and Clear Register */
+ __I uint32_t RIS; /* Raw Interrupt Status Register */
+ __I uint32_t MIS; /* Masked Interrupt Status Register */
+ __O uint32_t ICR; /* SSPICR Interrupt Clear Register */
+ __IO uint32_t DMACR; /* SSPn DMA control register */
+} LPC_SSP_T;
+
+/* ---------------------------------------------------------------------------
+ * 32-bit Standard timer register block structure
+ */
+#define LPC_TIMER0_BASE 0x40084000
+#define LPC_TIMER1_BASE 0x40085000
+#define LPC_TIMER2_BASE 0x400C3000
+#define LPC_TIMER3_BASE 0x400C4000
+
+typedef struct { /* TIMERn Structure */
+ __IO uint32_t IR; /* Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+ __IO uint32_t TCR; /* Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+ __IO uint32_t TC; /* Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
+ __IO uint32_t PR; /* Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
+ __IO uint32_t PC; /* Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
+ __IO uint32_t MCR; /* Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
+ __IO uint32_t MR[4]; /* Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+ __IO uint32_t CCR; /* Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+ __IO uint32_t CR[4]; /* Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
+ __IO uint32_t EMR; /* External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
+ __I uint32_t RESERVED0[12];
+ __IO uint32_t CTCR; /* Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+} LPC_TIMER_T;
+
+/* ---------------------------------------------------------------------------
+ * System Control Unit register block
+ */
+#define LPC_SCU_BASE 0x40086000
+
+typedef struct {
+ __IO uint32_t SFSP[16][32];
+ __I uint32_t RESERVED0[256];
+ __IO uint32_t SFSCLK[4]; /* Pin configuration register for pins CLK0-3 */
+ __I uint32_t RESERVED16[28];
+ __IO uint32_t SFSUSB; /* Pin configuration register for USB */
+ __IO uint32_t SFSI2C0; /* Pin configuration register for I2C0-bus pins */
+ __IO uint32_t ENAIO[3]; /* Analog function select registers */
+ __I uint32_t RESERVED17[27];
+ __IO uint32_t EMCDELAYCLK; /* EMC clock delay register */
+ __I uint32_t RESERVED18[63];
+ __IO uint32_t PINTSEL0; /* Pin interrupt select register for pin interrupts 0 to 3. */
+ __IO uint32_t PINTSEL1; /* Pin interrupt select register for pin interrupts 4 to 7. */
+} LPC_SCU_T;
+
+/*
+ * SCU function and mode selection definitions
+ * See the User Manual for specific modes and functions supoprted by the
+ * various LPC18xx/43xx devices. Functionality can vary per device.
+ */
+#define SCU_MODE_PULLUP (0x0 << 3) /* Enable pull-up resistor at pad */
+#define SCU_MODE_REPEATER (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
+#define SCU_MODE_INACT (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
+#define SCU_MODE_PULLDOWN (0x3 << 3) /* Enable pull-down resistor at pad */
+#define SCU_MODE_HIGHSPEEDSLEW_EN (0x1 << 5) /* Enable high-speed slew */
+#define SCU_MODE_INBUFF_EN (0x1 << 6) /* Enable Input buffer */
+#define SCU_MODE_ZIF_DIS (0x1 << 7) /* Disable input glitch filter */
+#define SCU_MODE_4MA_DRIVESTR (0x0 << 8) /* Normal drive: 4mA drive strength */
+#define SCU_MODE_8MA_DRIVESTR (0x1 << 8) /* Medium drive: 8mA drive strength */
+#define SCU_MODE_14MA_DRIVESTR (0x2 << 8) /* High drive: 14mA drive strength */
+#define SCU_MODE_20MA_DRIVESTR (0x3 << 8) /* Ultra high- drive: 20mA drive strength */
+
+#define SCU_MODE_FUNC0 0x0 /* Selects pin function 0 */
+#define SCU_MODE_FUNC1 0x1 /* Selects pin function 1 */
+#define SCU_MODE_FUNC2 0x2 /* Selects pin function 2 */
+#define SCU_MODE_FUNC3 0x3 /* Selects pin function 3 */
+#define SCU_MODE_FUNC4 0x4 /* Selects pin function 4 */
+#define SCU_MODE_FUNC5 0x5 /* Selects pin function 5 */
+#define SCU_MODE_FUNC6 0x6 /* Selects pin function 6 */
+#define SCU_MODE_FUNC7 0x7 /* Selects pin function 7 */
+
+/* Common SCU configurations */
+#define SCU_PINIO_FAST (SCU_MODE_INACT | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS)
+#define SCU_PINIO_PULLUP (SCU_MODE_INBUFF_EN)
+#define SCU_PINIO_PULLDOWN (SCU_MODE_PULLDOWN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN)
+#define SCU_PINIO_PULLNONE (SCU_MODE_INACT | SCU_MODE_INBUFF_EN)
+
+/* Calculate SCU offset and register address from group and pin number */
+#define SCU_OFF(group, num) ((group << 7) + (num << 2))
+#define SCU_REG(group, num) ((__IO uint32_t *)(LPC_SCU_BASE + SCU_OFF(group, num)))
+
+/**
+ * SCU function and mode selection definitions (old)
+ * For backwards compatibility.
+ */
+#define MD_PUP (0x0 << 3) /* Enable pull-up resistor at pad */
+#define MD_BUK (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
+#define MD_PLN (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
+#define MD_PDN (0x3 << 3) /* Enable pull-down resistor at pad */
+#define MD_EHS (0x1 << 5) /* Enable fast slew rate */
+#define MD_EZI (0x1 << 6) /* Input buffer enable */
+#define MD_ZI (0x1 << 7) /* Disable input glitch filter */
+#define MD_EHD0 (0x1 << 8) /* EHD driver strength low bit */
+#define MD_EHD1 (0x1 << 8) /* EHD driver strength high bit */
+#define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
+#define I2C0_STANDARD_FAST_MODE (1 << 3 | 1 << 11) /* Pin configuration for STANDARD/FAST mode I2C */
+#define I2C0_FAST_MODE_PLUS (2 << 1 | 1 << 3 | 1 << 7 | 1 << 10 | 1 << 11) /* Pin configuration for Fast-mode Plus I2C */
+
+#define FUNC0 0x0 /* Pin function 0 */
+#define FUNC1 0x1 /* Pin function 1 */
+#define FUNC2 0x2 /* Pin function 2 */
+#define FUNC3 0x3 /* Pin function 3 */
+#define FUNC4 0x4 /* Pin function 4 */
+#define FUNC5 0x5 /* Pin function 5 */
+#define FUNC6 0x6 /* Pin function 6 */
+#define FUNC7 0x7 /* Pin function 7 */
+
+#define PORT_OFFSET 0x80 /* Port offset definition */
+#define PIN_OFFSET 0x04 /* Pin offset definition */
+
+/* Returns the SFSP register address in the SCU for a pin and port,
+ recommend using (*(volatile int *) &LPC_SCU->SFSP[po][pi];) */
+#define LPC_SCU_PIN(LPC_SCU_BASE, po, pi) \
+ (*(volatile int *) ((LPC_SCU_BASE) + ((po) * 0x80) + ((pi) * 0x4))
+
+/* Returns the address in the SCU for a SFSCLK clock register,
+ recommend using (*(volatile int *) &LPC_SCU->SFSCLK[c];) */
+#define LPC_SCU_CLK(LPC_SCU_BASE, c) \
+ (*(volatile int *) ((LPC_SCU_BASE) +0xC00 + ((c) * 0x4)))
+
+/* ---------------------------------------------------------------------------
+ * GPIO pin interrupt register block structure
+ */
+#define LPC_GPIO_PIN_INT_BASE 0x40087000
+
+typedef struct { /* GPIO_PIN_INT Structure */
+ __IO uint32_t ISEL; /* Pin Interrupt Mode register */
+ __IO uint32_t IENR; /* Pin Interrupt Enable (Rising) register */
+ __O uint32_t SIENR; /* Set Pin Interrupt Enable (Rising) register */
+ __O uint32_t CIENR; /* Clear Pin Interrupt Enable (Rising) register */
+ __IO uint32_t IENF; /* Pin Interrupt Enable Falling Edge / Active Level register */
+ __O uint32_t SIENF; /* Set Pin Interrupt Enable Falling Edge / Active Level register */
+ __O uint32_t CIENF; /* Clear Pin Interrupt Enable Falling Edge / Active Level address */
+ __IO uint32_t RISE; /* Pin Interrupt Rising Edge register */
+ __IO uint32_t FALL; /* Pin Interrupt Falling Edge register */
+ __IO uint32_t IST; /* Pin Interrupt Status register */
+} LPC_GPIOPININT_T;
+
+typedef enum LPC_GPIOPININT_MODE {
+ GPIOPININT_RISING_EDGE = 0x01,
+ GPIOPININT_FALLING_EDGE = 0x02,
+ GPIOPININT_ACTIVE_HIGH_LEVEL = 0x04,
+ GPIOPININT_ACTIVE_LOW_LEVEL = 0x08
+} LPC_GPIOPININT_MODE_T;
+
+/* ---------------------------------------------------------------------------
+ * GPIO grouped interrupt register block structure
+ */
+#define LPC_GPIO_GROUP_INT0_BASE 0x40088000
+#define LPC_GPIO_GROUP_INT1_BASE 0x40089000
+
+typedef struct { /* GPIO_GROUP_INTn Structure */
+ __IO uint32_t CTRL; /* GPIO grouped interrupt control register */
+ __I uint32_t RESERVED0[7];
+ __IO uint32_t PORT_POL[8]; /* GPIO grouped interrupt port polarity register */
+ __IO uint32_t PORT_ENA[8]; /* GPIO grouped interrupt port m enable register */
+} LPC_GPIOGROUPINT_T;
+
+/* ---------------------------------------------------------------------------
+ * Motor Control PWM register block structure
+ */
+#define LPC_MCPWM_BASE 0x400A0000
+
+typedef struct { /* MCPWM Structure */
+ __I uint32_t CON; /* PWM Control read address */
+ __O uint32_t CON_SET; /* PWM Control set address */
+ __O uint32_t CON_CLR; /* PWM Control clear address */
+ __I uint32_t CAPCON; /* Capture Control read address */
+ __O uint32_t CAPCON_SET; /* Capture Control set address */
+ __O uint32_t CAPCON_CLR; /* Event Control clear address */
+ __IO uint32_t TC[3]; /* Timer Counter register */
+ __IO uint32_t LIM[3]; /* Limit register */
+ __IO uint32_t MAT[3]; /* Match register */
+ __IO uint32_t DT; /* Dead time register */
+ __IO uint32_t CCP; /* Communication Pattern register */
+ __I uint32_t CAP[3]; /* Capture register */
+ __I uint32_t INTEN; /* Interrupt Enable read address */
+ __O uint32_t INTEN_SET; /* Interrupt Enable set address */
+ __O uint32_t INTEN_CLR; /* Interrupt Enable clear address */
+ __I uint32_t CNTCON; /* Count Control read address */
+ __O uint32_t CNTCON_SET; /* Count Control set address */
+ __O uint32_t CNTCON_CLR; /* Count Control clear address */
+ __I uint32_t INTF; /* Interrupt flags read address */
+ __O uint32_t INTF_SET; /* Interrupt flags set address */
+ __O uint32_t INTF_CLR; /* Interrupt flags clear address */
+ __O uint32_t CAP_CLR; /* Capture clear address */
+} LPC_MCPWM_T;
+
+/* ---------------------------------------------------------------------------
+ * I2C register block structure
+ */
+#define LPC_I2C0_BASE 0x400A1000
+#define LPC_I2C1_BASE 0x400E0000
+
+typedef struct { /* I2C0 Structure */
+ __IO uint32_t CONSET; /* I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
+ __I uint32_t STAT; /* I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
+ __IO uint32_t DAT; /* I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
+ __IO uint32_t ADR0; /* I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+ __IO uint32_t SCLH; /* SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
+ __IO uint32_t SCLL; /* SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
+ __O uint32_t CONCLR; /* I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
+ __IO uint32_t MMCTRL; /* Monitor mode control register. */
+ __IO uint32_t ADR1; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+ __IO uint32_t ADR2; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+ __IO uint32_t ADR3; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+ __I uint32_t DATA_BUFFER; /* Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
+ __IO uint32_t MASK[4]; /* I2C Slave address mask register */
+} LPC_I2C_T;
+
+/* ---------------------------------------------------------------------------
+ * I2S register block structure
+ */
+#define LPC_I2S0_BASE 0x400A2000
+#define LPC_I2S1_BASE 0x400A3000
+
+typedef struct { /* I2S Structure */
+ __IO uint32_t DAO; /* I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel */
+ __IO uint32_t DAI; /* I2S Digital Audio Input Register. Contains control bits for the I2S receive channel */
+ __O uint32_t TXFIFO; /* I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO */
+ __I uint32_t RXFIFO; /* I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO */
+ __I uint32_t STATE; /* I2S Status Feedback Register. Contains status information about the I2S interface */
+ __IO uint32_t DMA1; /* I2S DMA Configuration Register 1. Contains control information for DMA request 1 */
+ __IO uint32_t DMA2; /* I2S DMA Configuration Register 2. Contains control information for DMA request 2 */
+ __IO uint32_t IRQ; /* I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated */
+ __IO uint32_t TXRATE; /* I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
+ __IO uint32_t RXRATE; /* I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
+ __IO uint32_t TXBITRATE; /* I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock */
+ __IO uint32_t RXBITRATE; /* I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock */
+ __IO uint32_t TXMODE; /* I2S Transmit mode control */
+ __IO uint32_t RXMODE; /* I2S Receive mode control */
+} LPC_I2S_T;
+
+/* ---------------------------------------------------------------------------
+ * CCAN Controller Area Network register block structure
+ */
+#define LPC_C_CAN1_BASE 0x400A4000
+#define LPC_C_CAN0_BASE 0x400E2000
+
+typedef struct { /* C_CAN message interface Structure */
+ __IO uint32_t IF_CMDREQ; /* Message interface command request */
+ union {
+ __IO uint32_t IF_CMDMSK_R; /* Message interface command mask (read direction) */
+ __IO uint32_t IF_CMDMSK_W; /* Message interface command mask (write direction) */
+ };
+
+ __IO uint32_t IF_MSK1; /* Message interface mask 1 */
+ __IO uint32_t IF_MSK2; /* Message interface mask 2 */
+ __IO uint32_t IF_ARB1; /* Message interface arbitration 1 */
+ __IO uint32_t IF_ARB2; /* Message interface arbitration 2 */
+ __IO uint32_t IF_MCTRL; /* Message interface message control */
+ __IO uint32_t IF_DA1; /* Message interface data A1 */
+ __IO uint32_t IF_DA2; /* Message interface data A2 */
+ __IO uint32_t IF_DB1; /* Message interface data B1 */
+ __IO uint32_t IF_DB2; /* Message interface data B2 */
+ __I uint32_t RESERVED[13];
+} LPC_CCAN_IF_T;
+
+typedef struct { /* C_CAN Structure */
+ __IO uint32_t CNTL; /* CAN control */
+ __IO uint32_t STAT; /* Status register */
+ __I uint32_t EC; /* Error counter */
+ __IO uint32_t BT; /* Bit timing register */
+ __I uint32_t INT; /* Interrupt register */
+ __IO uint32_t TEST; /* Test register */
+ __IO uint32_t BRPE; /* Baud rate prescaler extension register */
+ __I uint32_t RESERVED0;
+ LPC_CCAN_IF_T IF[2];
+ __I uint32_t RESERVED2[8];
+ __I uint32_t TXREQ1; /* Transmission request 1 */
+ __I uint32_t TXREQ2; /* Transmission request 2 */
+ __I uint32_t RESERVED3[6];
+ __I uint32_t ND1; /* New data 1 */
+ __I uint32_t ND2; /* New data 2 */
+ __I uint32_t RESERVED4[6];
+ __I uint32_t IR1; /* Interrupt pending 1 */
+ __I uint32_t IR2; /* Interrupt pending 2 */
+ __I uint32_t RESERVED5[6];
+ __I uint32_t MSGV1; /* Message valid 1 */
+ __I uint32_t MSGV2; /* Message valid 2 */
+ __I uint32_t RESERVED6[6];
+ __IO uint32_t CLKDIV; /* CAN clock divider register */
+} LPC_CCAN_T;
+
+/* ---------------------------------------------------------------------------
+ * Repetitive Interrupt Timer register block structure
+ */
+#define LPC_RITIMER_BASE 0x400C0000
+
+typedef struct { /* RITIMER Structure */
+ __IO uint32_t COMPVAL; /* Compare register */
+ __IO uint32_t MASK; /* Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */
+ __IO uint32_t CTRL; /* Control register. */
+ __IO uint32_t COUNTER; /* 32-bit counter */
+} LPC_RITIMER_T;
+
+/* ---------------------------------------------------------------------------
+ * Quadrature Encoder Interface register block structure
+ */
+#define LPC_QEI_BASE 0x400C6000
+
+typedef struct { /* QEI Structure */
+ __O uint32_t CON; /* Control register */
+ __I uint32_t STAT; /* Encoder status register */
+ __IO uint32_t CONF; /* Configuration register */
+ __I uint32_t POS; /* Position register */
+ __IO uint32_t MAXPOS; /* Maximum position register */
+ __IO uint32_t CMPOS0; /* position compare register 0 */
+ __IO uint32_t CMPOS1; /* position compare register 1 */
+ __IO uint32_t CMPOS2; /* position compare register 2 */
+ __I uint32_t INXCNT; /* Index count register */
+ __IO uint32_t INXCMP0; /* Index compare register 0 */
+ __IO uint32_t LOAD; /* Velocity timer reload register */
+ __I uint32_t TIME; /* Velocity timer register */
+ __I uint32_t VEL; /* Velocity counter register */
+ __I uint32_t CAP; /* Velocity capture register */
+ __IO uint32_t VELCOMP; /* Velocity compare register */
+ __IO uint32_t FILTERPHA; /* Digital filter register on input phase A (QEI_A) */
+ __IO uint32_t FILTERPHB; /* Digital filter register on input phase B (QEI_B) */
+ __IO uint32_t FILTERINX; /* Digital filter register on input index (QEI_IDX) */
+ __IO uint32_t WINDOW; /* Index acceptance window register */
+ __IO uint32_t INXCMP1; /* Index compare register 1 */
+ __IO uint32_t INXCMP2; /* Index compare register 2 */
+ __I uint32_t RESERVED0[993];
+ __O uint32_t IEC; /* Interrupt enable clear register */
+ __O uint32_t IES; /* Interrupt enable set register */
+ __I uint32_t INTSTAT; /* Interrupt status register */
+ __I uint32_t IE; /* Interrupt enable register */
+ __O uint32_t CLR; /* Interrupt status clear register */
+ __O uint32_t SET; /* Interrupt status set register */
+} LPC_QEI_T;
+
+/* ---------------------------------------------------------------------------
+ * Global Input Multiplexer Array (GIMA) register block structure
+ */
+#define LPC_GIMA_BASE 0x400C7000
+
+typedef struct { /* GIMA Structure */
+ __IO uint32_t CAP0_IN[4][4]; /* Timer x CAP0_y capture input multiplexer (GIMA output ((x*4)+y)) */
+ __IO uint32_t CTIN_IN[8]; /* SCT CTIN_x capture input multiplexer (GIMA output (16+x)) */
+ __IO uint32_t VADC_TRIGGER_IN; /* VADC trigger input multiplexer (GIMA output 24) */
+ __IO uint32_t EVENTROUTER_13_IN; /* Event router input 13 multiplexer (GIMA output 25) */
+ __IO uint32_t EVENTROUTER_14_IN; /* Event router input 14 multiplexer (GIMA output 26) */
+ __IO uint32_t EVENTROUTER_16_IN; /* Event router input 16 multiplexer (GIMA output 27) */
+ __IO uint32_t ADCSTART0_IN; /* ADC start0 input multiplexer (GIMA output 28) */
+ __IO uint32_t ADCSTART1_IN; /* ADC start1 input multiplexer (GIMA output 29) */
+} LPC_GIMA_T;
+
+/* ---------------------------------------------------------------------------
+ * DAC register block structure
+ */
+#define LPC_DAC_BASE 0x400E1000
+
+typedef struct { /* DAC Structure */
+ __IO uint32_t CR; /* DAC register. Holds the conversion data. */
+ __IO uint32_t CTRL; /* DAC control register. */
+ __IO uint32_t CNTVAL; /* DAC counter value register. */
+} LPC_DAC_T;
+
+/* After the selected settling time after this field is written with a
+ * new VALUE, the voltage on the AOUT pin (with respect to VSSA)
+ * is VALUE/1024 ? VREF
+ */
+#define DAC_RANGE 0x3FF
+#define DAC_SET(n) ((uint32_t) ((n & DAC_RANGE) << 6))
+#define DAC_GET(n) ((uint32_t) ((n >> 6) & DAC_RANGE))
+#define DAC_VALUE(n) DAC_SET(n)
+/* If this bit = 0: The settling time of the DAC is 1 microsecond max,
+ * and the maximum current is 700 microAmpere
+ * If this bit = 1: The settling time of the DAC is 2.5 microsecond
+ * and the maximum current is 350 microAmpere
+ */
+#define DAC_BIAS_EN ((uint32_t) (1 << 16))
+/* Value to reload interrupt DMA counter */
+#define DAC_CCNT_VALUE(n) ((uint32_t) (n & 0xffff))
+
+#define DAC_DBLBUF_ENA ((uint32_t) (1 << 1))
+#define DAC_CNT_ENA ((uint32_t) (1 << 2))
+#define DAC_DMA_ENA ((uint32_t) (1 << 3))
+#define DAC_DACCTRL_MASK ((uint32_t) (0x0F))
+
+/* Current option in DAC configuration option */
+typedef enum DAC_CURRENT_OPT {
+ DAC_MAX_UPDATE_RATE_1MHz = 0, /* Shorter settling times and higher power consumption;
+ allows for a maximum update rate of 1 MHz */
+ DAC_MAX_UPDATE_RATE_400kHz /* Longer settling times and lower power consumption;
+ allows for a maximum update rate of 400 kHz */
+} DAC_CURRENT_OPT_T;
+
+/* ---------------------------------------------------------------------------
+ * ADC register block structure
+ */
+#define LPC_ADC0_BASE 0x400E3000
+#define LPC_ADC1_BASE 0x400E4000
+#define ADC_ACC_10BITS
+
+/* ---------------------------------------------------------------------------
+ * 10 or 12-bit ADC register block structure
+ */
+typedef struct { /* ADCn Structure */
+ __IO uint32_t CR; /* A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
+ __I uint32_t GDR; /* A/D Global Data Register. Contains the result of the most recent A/D conversion. */
+ __I uint32_t RESERVED0;
+ __IO uint32_t INTEN; /* A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
+ __I uint32_t DR[8]; /* A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
+ __I uint32_t STAT; /* A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
+} LPC_ADC_T;
+
+/* ADC register support bitfields and mask */
+#define ADC_RANGE 0x3FF
+#define ADC_DR_RESULT(n) ((((n) >> 6) & 0x3FF)) /* Mask for getting the 10 bits ADC data read value */
+#define ADC_CR_BITACC(n) ((((n) & 0x7) << 17)) /* Number of ADC accuracy bits */
+#define ADC_DR_DONE(n) (((n) >> 31)) /* Mask for reading the ADC done status */
+#define ADC_DR_OVERRUN(n) ((((n) >> 30) & (1UL))) /* Mask for reading the ADC overrun status */
+#define ADC_CR_CH_SEL(n) ((1UL << (n))) /* Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
+#define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 8)) /* The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */
+#define ADC_CR_BURST ((1UL << 16)) /* Repeated conversions A/D enable bit */
+#define ADC_CR_PDN ((1UL << 21)) /* ADC convert is operational */
+#define ADC_CR_START_MASK ((7UL << 24)) /* ADC start mask bits */
+#define ADC_CR_START_MODE_SEL(SEL) ((SEL << 24)) /* Select Start Mode */
+#define ADC_CR_START_NOW ((1UL << 24)) /* Start conversion now */
+#define ADC_CR_START_CTOUT15 ((2UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
+#define ADC_CR_START_CTOUT8 ((3UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
+#define ADC_CR_START_ADCTRIG0 ((4UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
+#define ADC_CR_START_ADCTRIG1 ((5UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
+#define ADC_CR_START_MCOA2 ((6UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
+#define ADC_CR_EDGE ((1UL << 27)) /* Start conversion on a falling edge on the selected CAP/MAT signal */
+#define ADC_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x07) | ADC_CR_PDN)
+
+/* ADC status register used for IP drivers */
+typedef enum ADC_STATUS {
+ ADC_DR_DONE_STAT, /* ADC data register staus */
+ ADC_DR_OVERRUN_STAT,/* ADC data overrun staus */
+ ADC_DR_ADINT_STAT /* ADC interrupt status */
+} ADC_STATUS_T;
+
+/** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */
+typedef enum ADC_START_MODE {
+ ADC_NO_START = 0,
+ ADC_START_NOW, /* Start conversion now */
+ ADC_START_ON_CTOUT15, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
+ ADC_START_ON_CTOUT8, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
+ ADC_START_ON_ADCTRIG0, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
+ ADC_START_ON_ADCTRIG1, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
+ ADC_START_ON_MCOA2 /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
+} ADC_START_MODE_T;
+
+/* ---------------------------------------------------------------------------
+ * GPIO port register block structure
+ */
+#define LPC_GPIO_PORT_BASE 0x400F4000
+#define LPC_GPIO0_BASE (LPC_GPIO_PORT_BASE)
+#define LPC_GPIO1_BASE (LPC_GPIO_PORT_BASE + 0x04)
+#define LPC_GPIO2_BASE (LPC_GPIO_PORT_BASE + 0x08)
+#define LPC_GPIO3_BASE (LPC_GPIO_PORT_BASE + 0x0C)
+#define LPC_GPIO4_BASE (LPC_GPIO_PORT_BASE + 0x10)
+#define LPC_GPIO5_BASE (LPC_GPIO_PORT_BASE + 0x14)
+#define LPC_GPIO6_BASE (LPC_GPIO_PORT_BASE + 0x18)
+#define LPC_GPIO7_BASE (LPC_GPIO_PORT_BASE + 0x1C)
+
+typedef struct { /* GPIO_PORT Structure */
+ __IO uint8_t B[128][32]; /* Offset 0x0000: Byte pin registers ports 0 to n; pins PIOn_0 to PIOn_31 */
+ __IO uint32_t W[32][32]; /* Offset 0x1000: Word pin registers port 0 to n */
+ __IO uint32_t DIR[32]; /* Offset 0x2000: Direction registers port n */
+ __IO uint32_t MASK[32]; /* Offset 0x2080: Mask register port n */
+ __IO uint32_t PIN[32]; /* Offset 0x2100: Portpin register port n */
+ __IO uint32_t MPIN[32]; /* Offset 0x2180: Masked port register port n */
+ __IO uint32_t SET[32]; /* Offset 0x2200: Write: Set register for port n Read: output bits for port n */
+ __O uint32_t CLR[32]; /* Offset 0x2280: Clear port n */
+ __O uint32_t NOT[32]; /* Offset 0x2300: Toggle port n */
+} LPC_GPIO_T;
+
+/* Calculate GPIO offset and port register address from group and pin number */
+#define GPIO_OFF(port, pin) ((port << 5) + pin)
+#define GPIO_REG(port, pin) ((__IO uint32_t *)(LPC_GPIO_PORT_BASE + 0x2000 + GPIO_OFF(port, pin)))
+
+/* ---------------------------------------------------------------------------
+ * SPI register block structure
+ */
+#define LPC_SPI_BASE 0x40100000
+
+typedef struct { /* SPI Structure */
+ __IO uint32_t CR; /* SPI Control Register. This register controls the operation of the SPI. */
+ __I uint32_t SR; /* SPI Status Register. This register shows the status of the SPI. */
+ __IO uint32_t DR; /* SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. */
+ __IO uint32_t CCR; /* SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */
+ __I uint32_t RESERVED0[3];
+ __IO uint32_t INT; /* SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */
+} LPC_SPI_T;
+
+/* SPI CFG Register BitMask */
+#define SPI_CR_BITMASK ((uint32_t) 0xFFC)
+/* Enable of controlling the number of bits per transfer */
+#define SPI_CR_BIT_EN ((uint32_t) (1 << 2))
+/* Mask of field of bit controlling */
+#define SPI_CR_BITS_MASK ((uint32_t) 0xF00)
+/* Set the number of bits per a transfer */
+#define SPI_CR_BITS(n) ((uint32_t) ((n << 8) & 0xF00)) /* n is in range 8-16 */
+/* SPI Clock Phase Select*/
+#define SPI_CR_CPHA_FIRST ((uint32_t) (0)) /*Capture data on the first edge, Change data on the following edge*/
+#define SPI_CR_CPHA_SECOND ((uint32_t) (1 << 3)) /* Change data on the first edge, Capture data on the following edge*/
+/* SPI Clock Polarity Select*/
+#define SPI_CR_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/
+#define SPI_CR_CPOL_HI ((uint32_t) (1 << 4)) /* The rest state of the clock (between frames) is high.*/
+/* SPI Slave Mode Select */
+#define SPI_CR_SLAVE_EN ((uint32_t) 0)
+/* SPI Master Mode Select */
+#define SPI_CR_MASTER_EN ((uint32_t) (1 << 5))
+/* SPI MSB First mode enable */
+#define SPI_CR_MSB_FIRST_EN ((uint32_t) 0) /* Data will be transmitted and received in standard order (MSB first).*/
+/* SPI LSB First mode enable */
+#define SPI_CR_LSB_FIRST_EN ((uint32_t) (1 << 6)) /* Data will be transmitted and received in reverse order (LSB first).*/
+/* SPI interrupt enable */
+#define SPI_CR_INT_EN ((uint32_t) (1 << 7))
+/* SPI STAT Register BitMask */
+#define SPI_SR_BITMASK ((uint32_t) 0xF8)
+/* Slave abort Flag */
+#define SPI_SR_ABRT ((uint32_t) (1 << 3)) /* When 1, this bit indicates that a slave abort has occurred. */
+/* Mode fault Flag */
+#define SPI_SR_MODF ((uint32_t) (1 << 4)) /* when 1, this bit indicates that a Mode fault error has occurred. */
+/* Read overrun flag*/
+#define SPI_SR_ROVR ((uint32_t) (1 << 5)) /* When 1, this bit indicates that a read overrun has occurred. */
+/* Write collision flag. */
+#define SPI_SR_WCOL ((uint32_t) (1 << 6)) /* When 1, this bit indicates that a write collision has occurred.. */
+/* SPI transfer complete flag. */
+#define SPI_SR_SPIF ((uint32_t) (1 << 7)) /* When 1, this bit indicates when a SPI data transfer is complete.. */
+/* SPI error flag */
+#define SPI_SR_ERROR (SPI_SR_ABRT | SPI_SR_MODF | SPI_SR_ROVR | SPI_SR_WCOL)
+/* Enable SPI Test Mode */
+#define SPI_TCR_TEST(n) ((uint32_t) ((n & 0x3F) << 1))
+/* SPI interrupt flag */
+#define SPI_INT_SPIF ((uint32_t) (1 << 0))
+/* Receiver Data */
+#define SPI_DR_DATA(n) ((uint32_t) ((n) & 0xFFFF))
+
+/* SPI Mode*/
+typedef enum LPC_SPI_MODE {
+ SPI_MODE_MASTER = SPI_CR_MASTER_EN, /* Master Mode */
+ SPI_MODE_SLAVE = SPI_CR_SLAVE_EN, /* Slave Mode */
+} LPC_SPI_MODE_T;
+
+/* SPI Clock Mode*/
+typedef enum LPC_SPI_CLOCK_MODE {
+ SPI_CLOCK_CPHA0_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 0 */
+ SPI_CLOCK_CPHA0_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 1 */
+ SPI_CLOCK_CPHA1_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 0 */
+ SPI_CLOCK_CPHA1_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 1 */
+ SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0, /* alias */
+ SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0, /* alias */
+ SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1, /* alias */
+ SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1, /* alias */
+} LPC_SPI_CLOCK_MODE_T;
+
+/* SPI Data Order Mode*/
+typedef enum LPC_SPI_DATA_ORDER {
+ SPI_DATA_MSB_FIRST = SPI_CR_MSB_FIRST_EN, /* Standard Order */
+ SPI_DATA_LSB_FIRST = SPI_CR_LSB_FIRST_EN, /* Reverse Order */
+} LPC_SPI_DATA_ORDER_T;
+
+/* ---------------------------------------------------------------------------
+ * Serial GPIO register block structure
+ */
+#define LPC_SGPIO_BASE 0x40101000
+
+typedef struct { /* SGPIO Structure */
+ __IO uint32_t OUT_MUX_CFG[16]; /* Pin multiplexer configurationregisters. */
+ __IO uint32_t SGPIO_MUX_CFG[16]; /* SGPIO multiplexer configuration registers. */
+ __IO uint32_t SLICE_MUX_CFG[16]; /* Slice multiplexer configuration registers. */
+ __IO uint32_t REG[16]; /* Slice data registers. Eachtime COUNT0 reaches 0x0 the register shifts loading bit 31 withdata captured from DIN(n). DOUT(n) is set to REG(0) */
+ __IO uint32_t REG_SS[16]; /* Slice data shadow registers. Each time POSreaches 0x0 the contents of REG_SS is exchanged with the contentof REG */
+ __IO uint32_t PRESET[16]; /* Reload valueof COUNT0, loaded when COUNT0 reaches 0x0 */
+ __IO uint32_t COUNT[16]; /* Down counter, counts down each clock cycle. */
+ __IO uint32_t POS[16]; /* Each time COUNT0 reaches 0x0 */
+ __IO uint32_t MASK_A; /* Mask for pattern match function of slice A */
+ __IO uint32_t MASK_H; /* Mask for pattern match function of slice H */
+ __IO uint32_t MASK_I; /* Mask for pattern match function of slice I */
+ __IO uint32_t MASK_P; /* Mask for pattern match function of slice P */
+ __I uint32_t GPIO_INREG; /* GPIO input status register */
+ __IO uint32_t GPIO_OUTREG; /* GPIO output control register */
+ __IO uint32_t GPIO_OENREG; /* GPIO OE control register */
+ __IO uint32_t CTRL_ENABLED; /* Enables the slice COUNT counter */
+ __IO uint32_t CTRL_DISABLED; /* Disables the slice COUNT counter */
+ __I uint32_t RESERVED0[823];
+ __O uint32_t CLR_EN_0; /* Shift clock interrupt clear mask */
+ __O uint32_t SET_EN_0; /* Shift clock interrupt set mask */
+ __I uint32_t ENABLE_0; /* Shift clock interrupt enable */
+ __I uint32_t STATUS_0; /* Shift clock interrupt status */
+ __O uint32_t CTR_STATUS_0; /* Shift clock interrupt clear status */
+ __O uint32_t SET_STATUS_0; /* Shift clock interrupt set status */
+ __I uint32_t RESERVED1[2];
+ __O uint32_t CLR_EN_1; /* Capture clock interrupt clear mask */
+ __O uint32_t SET_EN_1; /* Capture clock interrupt set mask */
+ __I uint32_t ENABLE_1; /* Capture clock interrupt enable */
+ __I uint32_t STATUS_1; /* Capture clock interrupt status */
+ __O uint32_t CTR_STATUS_1; /* Capture clock interrupt clear status */
+ __O uint32_t SET_STATUS_1; /* Capture clock interrupt set status */
+ __I uint32_t RESERVED2[2];
+ __O uint32_t CLR_EN_2; /* Pattern match interrupt clear mask */
+ __O uint32_t SET_EN_2; /* Pattern match interrupt set mask */
+ __I uint32_t ENABLE_2; /* Pattern match interrupt enable */
+ __I uint32_t STATUS_2; /* Pattern match interrupt status */
+ __O uint32_t CTR_STATUS_2; /* Pattern match interrupt clear status */
+ __O uint32_t SET_STATUS_2; /* Pattern match interrupt set status */
+ __I uint32_t RESERVED3[2];
+ __O uint32_t CLR_EN_3; /* Input interrupt clear mask */
+ __O uint32_t SET_EN_3; /* Input bit match interrupt set mask */
+ __I uint32_t ENABLE_3; /* Input bit match interrupt enable */
+ __I uint32_t STATUS_3; /* Input bit match interrupt status */
+ __O uint32_t CTR_STATUS_3; /* Input bit match interrupt clear status */
+ __O uint32_t SET_STATUS_3; /* Shift clock interrupt set status */
+} LPC_SGPIO_T;
+
+/* End of section using anonymous unions */
+#if defined(__ARMCC_VERSION)
+ #pragma pop
+#elif defined(__CWCC__)
+ #pragma pop
+#elif defined(__IAR_SYSTEMS_ICC__)
+ //#pragma pop // FIXME not usable for IAR
+#else /* defined(__GNUC__) and others */
+ /* Leave anonymous unions enabled */
+#endif
+
+/* ---------------------------------------------------------------------------
+ * LPC43xx Peripheral register set declarations
+ */
+#define LPC_SCT ((LPC_SCT_T *) LPC_SCT_BASE)
+#define LPC_GPDMA ((LPC_GPDMA_T *) LPC_GPDMA_BASE)
+#define LPC_SPIFI ((LPC_SPIFI_T *) LPC_SPIFI_BASE)
+#define LPC_SDMMC ((LPC_SDMMC_T *) LPC_SDMMC_BASE)
+#define LPC_EMC ((LPC_EMC_T *) LPC_EMC_BASE)
+#define LPC_USB0 ((LPC_USBHS_T *) LPC_USB0_BASE)
+#define LPC_USB1 ((LPC_USBHS_T *) LPC_USB1_BASE)
+#define LPC_LCD ((LPC_LCD_T *) LPC_LCD_BASE)
+#define LPC_EEPROM ((LPC_EEPROM_T *) LPC_EEPROM_BASE)
+#define LPC_ETHERNET ((LPC_ENET_T *) LPC_ETHERNET_BASE)
+#define LPC_ATIMER ((LPC_ATIMER_T *) LPC_ATIMER_BASE)
+#define LPC_REGFILE ((LPC_REGFILE_T *) LPC_REGFILE_BASE)
+#define LPC_PMC ((LPC_PMC_T *) LPC_PMC_BASE)
+#define LPC_CREG ((LPC_CREG_T *) LPC_CREG_BASE)
+#define LPC_EVRT ((LPC_EVRT_T *) LPC_EVRT_BASE)
+#define LPC_RTC ((LPC_RTC_T *) LPC_RTC_BASE)
+#define LPC_CGU ((LPC_CGU_T *) LPC_CGU_BASE)
+#define LPC_CCU1 ((LPC_CCU1_T *) LPC_CCU1_BASE)
+#define LPC_CCU2 ((LPC_CCU2_T *) LPC_CCU2_BASE)
+#define LPC_RGU ((LPC_RGU_T *) LPC_RGU_BASE)
+#define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE)
+#define LPC_USART0 ((LPC_USART_T *) LPC_USART0_BASE)
+#define LPC_USART2 ((LPC_USART_T *) LPC_USART2_BASE)
+#define LPC_USART3 ((LPC_USART_T *) LPC_USART3_BASE)
+#define LPC_UART1 ((LPC_USART_T *) LPC_UART1_BASE)
+#define LPC_SSP0 ((LPC_SSP_T *) LPC_SSP0_BASE)
+#define LPC_SSP1 ((LPC_SSP_T *) LPC_SSP1_BASE)
+#define LPC_TIMER0 ((LPC_TIMER_T *) LPC_TIMER0_BASE)
+#define LPC_TIMER1 ((LPC_TIMER_T *) LPC_TIMER1_BASE)
+#define LPC_TIMER2 ((LPC_TIMER_T *) LPC_TIMER2_BASE)
+#define LPC_TIMER3 ((LPC_TIMER_T *) LPC_TIMER3_BASE)
+#define LPC_SCU ((LPC_SCU_T *) LPC_SCU_BASE)
+#define LPC_GPIO_PIN_INT ((LPC_GPIOPININT_T *) LPC_GPIO_PIN_INT_BASE)
+#define LPC_GPIO_GROUP_INT0 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT0_BASE)
+#define LPC_GPIO_GROUP_INT1 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT1_BASE)
+#define LPC_MCPWM ((LPC_MCPWM_T *) LPC_MCPWM_BASE)
+#define LPC_I2C0 ((LPC_I2C_T *) LPC_I2C0_BASE)
+#define LPC_I2C1 ((LPC_I2C_T *) LPC_I2C1_BASE)
+#define LPC_I2S0 ((LPC_I2S_T *) LPC_I2S0_BASE)
+#define LPC_I2S1 ((LPC_I2S_T *) LPC_I2S1_BASE)
+#define LPC_C_CAN1 ((LPC_CCAN_T *) LPC_C_CAN1_BASE)
+#define LPC_RITIMER ((LPC_RITIMER_T *) LPC_RITIMER_BASE)
+#define LPC_QEI ((LPC_QEI_T *) LPC_QEI_BASE)
+#define LPC_GIMA ((LPC_GIMA_T *) LPC_GIMA_BASE)
+#define LPC_DAC ((LPC_DAC_T *) LPC_DAC_BASE)
+#define LPC_C_CAN0 ((LPC_CCAN_T *) LPC_C_CAN0_BASE)
+#define LPC_ADC0 ((LPC_ADC_T *) LPC_ADC0_BASE)
+#define LPC_ADC1 ((LPC_ADC_T *) LPC_ADC1_BASE)
+#define LPC_GPIO_PORT ((LPC_GPIO_T *) LPC_GPIO_PORT_BASE)
+#define LPC_GPIO0 ((LPC_GPIO_T *) LPC_GPIO0_BASE)
+#define LPC_GPIO1 ((LPC_GPIO_T *) LPC_GPIO1_BASE)
+#define LPC_GPIO2 ((LPC_GPIO_T *) LPC_GPIO2_BASE)
+#define LPC_GPIO3 ((LPC_GPIO_T *) LPC_GPIO3_BASE)
+#define LPC_GPIO4 ((LPC_GPIO_T *) LPC_GPIO4_BASE)
+#define LPC_GPIO5 ((LPC_GPIO_T *) LPC_GPIO5_BASE)
+#define LPC_GPIO6 ((LPC_GPIO_T *) LPC_GPIO6_BASE)
+#define LPC_GPIO7 ((LPC_GPIO_T *) LPC_GPIO7_BASE)
+#define LPC_SPI ((LPC_SPI_T *) LPC_SPI_BASE)
+#define LPC_SGPIO ((LPC_SGPIO_T *) LPC_SGPIO_BASE)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LPC43XX_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC4337/TARGET_NXP/TARGET_LPC43XX/PeripheralNames.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,135 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ UART_0 = (int)LPC_USART0_BASE,
+ UART_1 = (int)LPC_UART1_BASE,
+ UART_2 = (int)LPC_USART2_BASE,
+ UART_3 = (int)LPC_USART3_BASE
+} UARTName;
+
+typedef enum {
+ ADC0_0 = 0,
+ ADC0_1,
+ ADC0_2,
+ ADC0_3,
+ ADC0_4,
+ ADC0_5,
+ ADC0_6,
+ ADC0_7,
+ ADC1_0,
+ ADC1_1,
+ ADC1_2,
+ ADC1_3,
+ ADC1_4,
+ ADC1_5,
+ ADC1_6,
+ ADC1_7
+} ADCName;
+
+typedef enum {
+ DAC_0 = 0
+} DACName;
+
+typedef enum {
+ SPI_0 = (int)LPC_SSP0_BASE,
+ SPI_1 = (int)LPC_SSP1_BASE
+} SPIName;
+
+typedef enum {
+ I2C_0 = (int)LPC_I2C0_BASE,
+ I2C_1 = (int)LPC_I2C1_BASE
+} I2CName;
+
+typedef enum {
+ PWM_0,
+ PWM_1,
+ PWM_2,
+ PWM_3,
+ PWM_4,
+ PWM_5,
+ PWM_6,
+ PWM_7,
+ PWM_8,
+ PWM_9,
+ PWM_10,
+ PWM_11,
+ PWM_12,
+ PWM_13,
+ PWM_14,
+ PWM_15
+} PWMName;
+
+typedef enum {
+ CAN_0 = (int)LPC_C_CAN0_BASE,
+ CAN_1 = (int)LPC_C_CAN1_BASE
+} CANName;
+
+#define STDIO_UART_TX USBTX
+#define STDIO_UART_RX USBRX
+#define STDIO_UART UART_2
+
+// Default peripherals
+#define MBED_SPI0 SPI0_MOSI, SPI0_MISO, SPI0_SCK, SPI0_SSEL
+#define MBED_SPI1 SPI1_MOSI, SPI1_MISO, SPI1_SCK, SPI1_SSEL
+
+#define MBED_UART0 UART0_TX, UART0_RX
+#define MBED_UART1 UART1_TX, UART1_RX
+#define MBED_UART2 UART2_TX, UART2_RX
+#define MBED_UART3 UART3_TX, UART3_RX
+#define MBED_UARTUSB USBTX, USBRX
+
+#define COM1 MBED_UART0
+#define COM2 MBED_UART1
+#define COM3 MBED_UART2
+#define COM4 MBED_UART3
+
+#define MBED_I2C0 I2C0_SDA, I2C0_SCL
+#define MBED_I2C1 I2C1_SDA, I2C1_SCL
+
+#define MBED_CAN0 p30, p29
+
+#define MBED_ANALOGOUT0 DAC0
+
+#define MBED_ANALOGIN0 ADC0
+#define MBED_ANALOGIN1 ADC1
+#define MBED_ANALOGIN2 ADC2
+#define MBED_ANALOGIN3 ADC3
+#define MBED_ANALOGIN4 ADC4
+#define MBED_ANALOGIN5 ADC5
+#define MBED_ANALOGIN6 ADC6
+#define MBED_ANALOGIN7 ADC7
+
+#define MBED_PWMOUT0 p26
+#define MBED_PWMOUT1 p25
+#define MBED_PWMOUT2 p24
+#define MBED_PWMOUT3 p23
+#define MBED_PWMOUT4 p22
+#define MBED_PWMOUT5 p21
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC4337/TARGET_NXP/TARGET_LPC43XX/PortNames.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,37 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ Port0 = 0,
+ Port1 = 1,
+ Port2 = 2,
+ Port3 = 3,
+ Port4 = 4,
+ Port5 = 5,
+ Port6 = 6,
+ Port7 = 7
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC4337/TARGET_NXP/TARGET_LPC43XX/TARGET_LPC4337/PinNames.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,621 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#define BOARD_REV_B
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT 5
+#define NO_GPIO 15
+
+// On the LPC43xx the MCU pin name and the GPIO pin name are not the same.
+// Encode SCU and GPIO offsets as a pin identifier
+#define MBED_PIN(group, num, port, pin) ((SCU_OFF(group,num) << 16) + GPIO_OFF(port,pin))
+
+// Decode pin identifier into register, port and pin values
+#define MBED_SCU_REG(MBED_PIN) (LPC_SCU_BASE + (MBED_PIN >> 16))
+#define MBED_GPIO_REG(MBED_PIN) (LPC_GPIO_PORT_BASE + 0x2000 + ((MBED_PIN >> (PORT_SHIFT - 2)) & 0x0000003C))
+#define MBED_GPIO_PORT(MBED_PIN) ((MBED_PIN >> PORT_SHIFT) & 0x0000000F)
+#define MBED_GPIO_PIN(MBED_PIN) (MBED_PIN & 0x0000001F)
+
+typedef enum {
+ // LPC43xx Pin Names
+ // All pins defined. Package determines which are available.
+ // LBGA256 TFBGA180 TFBGA100 LQFP208 LQFP144
+ // GPIO0 [15:0] [15:0] [15:6] [15:0] [15:0]
+ // [4:0]
+ // GPIO1 [15:0] [15:0] [15:0] [15:0] [15:0]
+ // GPIO2 [15:0] [15:0] [15:0] [15:0]
+ // GPIO3 [15:0] [15:0] [7] [15:0] [15:0]
+ // [5:3]
+ // [1:0]
+ // GPIO4 [15:0] [15:0] [15:0] [11]
+ // GPIO5 [26:0] [26:0] [11:0] [25:0] [18]
+ // [16:0]
+ // GPIO6 [30:0] [30:28] [30:20]
+ // [26:25] [5:0]
+ // GPIO7 [25:0] [4:0] [25:23]
+ // [21:17]
+ // --- --- --- --- ---
+ // Total 164 117 49 131 83
+
+ // Groups 0x00 - 0x0F : Digital pins
+ // * Digital pins support up to 8 functions
+ // Use func=0 for GPIO0-GPIO4, func=4 for GPIO5-GPIO7
+ // * High-drive pins default to 4 mA but can support 8, 14, 20 mA
+ P0_0 = MBED_PIN(0x00, 0, 0, 0), // GPIO0[0]
+ P0_1 = MBED_PIN(0x00, 1, 0, 1), // GPIO0[1]
+
+ P1_0 = MBED_PIN(0x01, 0, 0, 4), // GPIO0[4]
+ P1_1 = MBED_PIN(0x01, 1, 0, 8), // GPIO0[8]
+ P1_2 = MBED_PIN(0x01, 2, 0, 9), // GPIO0[9]
+ P1_3 = MBED_PIN(0x01, 3, 0, 10), // GPIO0[10]
+ P1_4 = MBED_PIN(0x01, 4, 0, 11), // GPIO0[11]
+ P1_5 = MBED_PIN(0x01, 5, 1, 8), // GPIO1[8]
+ P1_6 = MBED_PIN(0x01, 6, 1, 9), // GPIO1[9]
+ P1_7 = MBED_PIN(0x01, 7, 1, 0), // GPIO1[0]
+ P1_8 = MBED_PIN(0x01, 8, 1, 1), // GPIO1[1]
+ P1_9 = MBED_PIN(0x01, 9, 1, 2), // GPIO1[2]
+ P1_10 = MBED_PIN(0x01, 10, 1, 3), // GPIO1[3]
+ P1_11 = MBED_PIN(0x01, 11, 1, 4), // GPIO1[4]
+ P1_12 = MBED_PIN(0x01, 12, 1, 5), // GPIO1[5]
+ P1_13 = MBED_PIN(0x01, 13, 1, 6), // GPIO1[6]
+ P1_14 = MBED_PIN(0x01, 14, 1, 7), // GPIO1[7]
+ P1_15 = MBED_PIN(0x01, 15, 0, 2), // GPIO0[2]
+ P1_16 = MBED_PIN(0x01, 16, 0, 3), // GPIO0[3]
+ P1_17 = MBED_PIN(0x01, 17, 0, 12), // GPIO0[12] high-drive
+ P1_18 = MBED_PIN(0x01, 18, 0, 13), // GPIO0[13]
+ P1_19 = MBED_PIN(0x01, 19, NO_GPIO, 0),
+ P1_20 = MBED_PIN(0x01, 20, 0, 15), // GPIO0[15]
+
+ P2_0 = MBED_PIN(0x02, 0, 5, 0), // GPIO5[0]
+ P2_1 = MBED_PIN(0x02, 1, 5, 1), // GPIO5[1]
+ P2_2 = MBED_PIN(0x02, 2, 5, 2), // GPIO5[2]
+ P2_3 = MBED_PIN(0x02, 3, 5, 3), // GPIO5[3] high-drive
+ P2_4 = MBED_PIN(0x02, 4, 5, 4), // GPIO5[4] high-drive
+ P2_5 = MBED_PIN(0x02, 5, 5, 5), // GPIO5[5] high-drive
+ P2_6 = MBED_PIN(0x02, 6, 5, 6), // GPIO5[6]
+ P2_7 = MBED_PIN(0x02, 7, 0, 7), // GPIO0[7]
+ P2_8 = MBED_PIN(0x02, 8, 5, 7), // GPIO5[7]
+ P2_9 = MBED_PIN(0x02, 9, 1, 10), // GPIO1[10]
+ P2_10 = MBED_PIN(0x02, 10, 0, 14), // GPIO0[14]
+ P2_11 = MBED_PIN(0x02, 11, 1, 11), // GPIO1[11]
+ P2_12 = MBED_PIN(0x02, 12, 1, 12), // GPIO1[12]
+ P2_13 = MBED_PIN(0x02, 13, 1, 13), // GPIO1[13]
+
+ P3_0 = MBED_PIN(0x03, 0, NO_GPIO, 0),
+ P3_1 = MBED_PIN(0x03, 1, 5, 8), // GPIO5[8]
+ P3_2 = MBED_PIN(0x03, 2, 5, 9), // GPIO5[9]
+ P3_3 = MBED_PIN(0x03, 3, NO_GPIO, 0),
+ P3_4 = MBED_PIN(0x03, 4, 1, 14), // GPIO1[14]
+ P3_5 = MBED_PIN(0x03, 5, 1, 15), // GPIO1[15]
+ P3_6 = MBED_PIN(0x03, 6, 0, 6), // GPIO0[6]
+ P3_7 = MBED_PIN(0x03, 7, 5, 10), // GPIO5[10]
+ P3_8 = MBED_PIN(0x03, 8, 5, 11), // GPIO5[11]
+
+ P4_0 = MBED_PIN(0x04, 0, 2, 0), // GPIO2[0]
+ P4_1 = MBED_PIN(0x04, 1, 2, 1), // GPIO2[1]
+ P4_2 = MBED_PIN(0x04, 2, 2, 2), // GPIO2[2]
+ P4_3 = MBED_PIN(0x04, 3, 2, 3), // GPIO2[3]
+ P4_4 = MBED_PIN(0x04, 4, 2, 4), // GPIO2[4]
+ P4_5 = MBED_PIN(0x04, 5, 2, 5), // GPIO2[5]
+ P4_6 = MBED_PIN(0x04, 6, 2, 6), // GPIO2[6]
+ P4_7 = MBED_PIN(0x04, 7, NO_GPIO, 0),
+ P4_8 = MBED_PIN(0x04, 8, 5, 12), // GPIO5[12]
+ P4_9 = MBED_PIN(0x04, 9, 5, 13), // GPIO5[13]
+ P4_10 = MBED_PIN(0x04, 10, 5, 14), // GPIO5[14]
+
+ P5_0 = MBED_PIN(0x05, 0, 2, 9), // GPIO2[9]
+ P5_1 = MBED_PIN(0x05, 1, 2, 10), // GPIO2[10]
+ P5_2 = MBED_PIN(0x05, 2, 2, 11), // GPIO2[11]
+ P5_3 = MBED_PIN(0x05, 3, 2, 12), // GPIO2[12]
+ P5_4 = MBED_PIN(0x05, 4, 2, 13), // GPIO2[13]
+ P5_5 = MBED_PIN(0x05, 5, 2, 14), // GPIO2[14]
+ P5_6 = MBED_PIN(0x05, 6, 2, 15), // GPIO2[15]
+ P5_7 = MBED_PIN(0x05, 7, 2, 7), // GPIO2[7]
+
+ P6_0 = MBED_PIN(0x06, 0, NO_GPIO, 0),
+ P6_1 = MBED_PIN(0x06, 1, 3, 0), // GPIO3[0]
+ P6_2 = MBED_PIN(0x06, 2, 3, 1), // GPIO3[1]
+ P6_3 = MBED_PIN(0x06, 3, 3, 2), // GPIO3[2]
+ P6_4 = MBED_PIN(0x06, 4, 3, 3), // GPIO3[3]
+ P6_5 = MBED_PIN(0x06, 5, 3, 4), // GPIO3[4]
+ P6_6 = MBED_PIN(0x06, 6, 0, 5), // GPIO0[5]
+ P6_7 = MBED_PIN(0x06, 7, 5, 15), // GPIO5[15]
+ P6_8 = MBED_PIN(0x06, 8, 5, 16), // GPIO5[16]
+ P6_9 = MBED_PIN(0x06, 9, 3, 5), // GPIO3[5]
+ P6_10 = MBED_PIN(0x06, 10, 3, 6), // GPIO3[6]
+ P6_11 = MBED_PIN(0x06, 11, 3, 7), // GPIO3[7]
+ P6_12 = MBED_PIN(0x06, 12, 2, 8), // GPIO2[8]
+
+ P7_0 = MBED_PIN(0x07, 0, 3, 8), // GPIO3[8]
+ P7_1 = MBED_PIN(0x07, 1, 3, 9), // GPIO3[9]
+ P7_2 = MBED_PIN(0x07, 2, 3, 10), // GPIO3[10]
+ P7_3 = MBED_PIN(0x07, 3, 3, 11), // GPIO3[11]
+ P7_4 = MBED_PIN(0x07, 4, 3, 12), // GPIO3[12]
+ P7_5 = MBED_PIN(0x07, 5, 3, 13), // GPIO3[13]
+ P7_6 = MBED_PIN(0x07, 6, 3, 14), // GPIO3[14]
+ P7_7 = MBED_PIN(0x07, 7, 3, 15), // GPIO3[15]
+
+ P8_0 = MBED_PIN(0x08, 8, 4, 0), // GPIO4[0] high-drive
+ P8_1 = MBED_PIN(0x09, 0, 4, 1), // GPIO4[1] high-drive
+ P8_2 = MBED_PIN(0x09, 1, 4, 2), // GPIO4[2] high-drive
+ P8_3 = MBED_PIN(0x09, 2, 4, 3), // GPIO4[3]
+ P8_4 = MBED_PIN(0x08, 4, 4, 4), // GPIO4[4]
+ P8_5 = MBED_PIN(0x08, 5, 4, 5), // GPIO4[5]
+ P8_6 = MBED_PIN(0x08, 6, 4, 6), // GPIO4[6]
+ P8_7 = MBED_PIN(0x08, 7, 4, 7), // GPIO4[7]
+ P8_8 = MBED_PIN(0x08, 8, NO_GPIO, 0),
+
+ P9_0 = MBED_PIN(0x09, 0, 4, 12), // GPIO4[12]
+ P9_1 = MBED_PIN(0x09, 1, 4, 13), // GPIO4[13]
+ P9_2 = MBED_PIN(0x09, 2, 4, 14), // GPIO4[14]
+ P9_3 = MBED_PIN(0x09, 3, 4, 15), // GPIO4[15]
+ P9_4 = MBED_PIN(0x09, 4, 5, 17), // GPIO5[17]
+ P9_5 = MBED_PIN(0x09, 5, 5, 18), // GPIO5[18]
+ P9_6 = MBED_PIN(0x09, 6, 4, 11), // GPIO4[11]
+
+ PA_0 = MBED_PIN(0x0A, 0, NO_GPIO, 0),
+ PA_1 = MBED_PIN(0x0A, 1, 4, 8), // GPIO4[8] high-drive
+ PA_2 = MBED_PIN(0x0A, 2, 4, 9), // GPIO4[9] high-drive
+ PA_3 = MBED_PIN(0x0A, 3, 4, 10), // GPIO4[10] high-drive
+ PA_4 = MBED_PIN(0x0A, 4, 5, 19), // GPIO5[19]
+
+ PB_0 = MBED_PIN(0x0B, 0, 5, 20), // GPIO5[20]
+ PB_1 = MBED_PIN(0x0B, 1, 5, 21), // GPIO5[21]
+ PB_2 = MBED_PIN(0x0B, 2, 5, 22), // GPIO5[22]
+ PB_3 = MBED_PIN(0x0B, 3, 5, 23), // GPIO5[23]
+ PB_4 = MBED_PIN(0x0B, 4, 5, 24), // GPIO5[24]
+ PB_5 = MBED_PIN(0x0B, 5, 5, 25), // GPIO5[25]
+ PB_6 = MBED_PIN(0x0B, 6, 5, 26), // GPIO5[26]
+
+ PC_0 = MBED_PIN(0x0C, 0, NO_GPIO, 0),
+ PC_1 = MBED_PIN(0x0C, 1, 6, 0), // GPIO6[0]
+ PC_2 = MBED_PIN(0x0C, 2, 6, 1), // GPIO6[1]
+ PC_3 = MBED_PIN(0x0C, 3, 6, 2), // GPIO6[2]
+ PC_4 = MBED_PIN(0x0C, 4, 6, 3), // GPIO6[3]
+ PC_5 = MBED_PIN(0x0C, 5, 6, 4), // GPIO6[4]
+ PC_6 = MBED_PIN(0x0C, 6, 6, 5), // GPIO6[5]
+ PC_7 = MBED_PIN(0x0C, 7, 6, 6), // GPIO6[6]
+ PC_8 = MBED_PIN(0x0C, 8, 6, 7), // GPIO6[7]
+ PC_9 = MBED_PIN(0x0C, 9, 6, 8), // GPIO6[8]
+ PC_10 = MBED_PIN(0x0C, 10, 6, 9), // GPIO6[9]
+ PC_11 = MBED_PIN(0x0C, 11, 6, 10), // GPIO6[10]
+ PC_12 = MBED_PIN(0x0C, 12, 6, 11), // GPIO6[11]
+ PC_13 = MBED_PIN(0x0C, 13, 6, 12), // GPIO6[12]
+ PC_14 = MBED_PIN(0x0C, 14, 6, 13), // GPIO6[13]
+
+ PD_0 = MBED_PIN(0x0D, 0, 6, 14), // GPIO6[14]
+ PD_1 = MBED_PIN(0x0D, 1, 6, 15), // GPIO6[15]
+ PD_2 = MBED_PIN(0x0D, 2, 6, 16), // GPIO6[16]
+ PD_3 = MBED_PIN(0x0D, 3, 6, 17), // GPIO6[17]
+ PD_4 = MBED_PIN(0x0D, 4, 6, 18), // GPIO6[18]
+ PD_5 = MBED_PIN(0x0D, 5, 6, 19), // GPIO6[19]
+ PD_6 = MBED_PIN(0x0D, 6, 6, 20), // GPIO6[20]
+ PD_7 = MBED_PIN(0x0D, 7, 6, 21), // GPIO6[21]
+ PD_8 = MBED_PIN(0x0D, 8, 6, 22), // GPIO6[22]
+ PD_9 = MBED_PIN(0x0D, 9, 6, 23), // GPIO6[23]
+ PD_10 = MBED_PIN(0x0D, 10, 6, 24), // GPIO6[24]
+ PD_11 = MBED_PIN(0x0D, 11, 6, 25), // GPIO6[25]
+ PD_12 = MBED_PIN(0x0D, 12, 6, 26), // GPIO6[26]
+ PD_13 = MBED_PIN(0x0D, 13, 6, 27), // GPIO6[27]
+ PD_14 = MBED_PIN(0x0D, 14, 6, 28), // GPIO6[28]
+ PD_15 = MBED_PIN(0x0D, 15, 6, 29), // GPIO6[29]
+ PD_16 = MBED_PIN(0x0D, 16, 6, 30), // GPIO6[30]
+
+ PE_0 = MBED_PIN(0x0E, 0, 7, 0), // GPIO7[0]
+ PE_1 = MBED_PIN(0x0E, 1, 7, 1), // GPIO7[1]
+ PE_2 = MBED_PIN(0x0E, 2, 7, 2), // GPIO7[2]
+ PE_3 = MBED_PIN(0x0E, 3, 7, 3), // GPIO7[3]
+ PE_4 = MBED_PIN(0x0E, 4, 7, 4), // GPIO7[4]
+ PE_5 = MBED_PIN(0x0E, 5, 7, 5), // GPIO7[5]
+ PE_6 = MBED_PIN(0x0E, 6, 7, 6), // GPIO7[6]
+ PE_7 = MBED_PIN(0x0E, 7, 7, 7), // GPIO7[7]
+ PE_8 = MBED_PIN(0x0E, 8, 7, 8), // GPIO7[8]
+ PE_9 = MBED_PIN(0x0E, 9, 7, 9), // GPIO7[9]
+ PE_10 = MBED_PIN(0x0E, 10, 7, 10), // GPIO7[10]
+ PE_11 = MBED_PIN(0x0E, 11, 7, 11), // GPIO7[11]
+ PE_12 = MBED_PIN(0x0E, 12, 7, 12), // GPIO7[12]
+ PE_13 = MBED_PIN(0x0E, 13, 7, 13), // GPIO7[13]
+ PE_14 = MBED_PIN(0x0E, 14, 7, 14), // GPIO7[14]
+ PE_15 = MBED_PIN(0x0E, 15, 7, 15), // GPIO7[15]
+
+ PF_0 = MBED_PIN(0x0F, 0, NO_GPIO, 0),
+ PF_1 = MBED_PIN(0x0F, 1, 7, 16), // GPIO7[16]
+ PF_2 = MBED_PIN(0x0F, 2, 7, 17), // GPIO7[17]
+ PF_3 = MBED_PIN(0x0F, 3, 7, 18), // GPIO7[18]
+ PF_4 = MBED_PIN(0x0F, 4, NO_GPIO, 0),
+ PF_5 = MBED_PIN(0x0F, 5, 7, 19), // GPIO7[19]
+ PF_6 = MBED_PIN(0x0F, 6, 7, 20), // GPIO7[20]
+ PF_7 = MBED_PIN(0x0F, 7, 7, 21), // GPIO7[21]
+ PF_8 = MBED_PIN(0x0F, 8, 7, 22), // GPIO7[22]
+ PF_9 = MBED_PIN(0x0F, 9, 7, 23), // GPIO7[23]
+ PF_10 = MBED_PIN(0x0F, 10, 7, 24), // GPIO7[24]
+ PF_11 = MBED_PIN(0x0F, 11, 7, 25), // GPIO7[25]
+
+ // GPIO pins from MCU pins
+ GPIO0_0 = P0_0,
+ GPIO0_1 = P0_1 ,
+ GPIO0_2 = P1_15,
+ GPIO0_3 = P1_16,
+ GPIO0_4 = P1_0,
+ GPIO0_5 = P6_6,
+ GPIO0_6 = P3_6,
+ GPIO0_7 = P2_7,
+ GPIO0_8 = P1_1,
+ GPIO0_9 = P1_2,
+ GPIO0_10 = P1_3,
+ GPIO0_11 = P1_4,
+ GPIO0_12 = P1_17,
+ GPIO0_13 = P1_18,
+ GPIO0_14 = P2_10,
+ GPIO0_15 = P1_20,
+
+ GPIO1_0 = P1_7,
+ GPIO1_1 = P1_8,
+ GPIO1_2 = P1_9,
+ GPIO1_3 = P1_10,
+ GPIO1_4 = P1_11,
+ GPIO1_5 = P1_12,
+ GPIO1_6 = P1_13,
+ GPIO1_7 = P1_14,
+ GPIO1_8 = P1_5,
+ GPIO1_9 = P1_6,
+ GPIO1_10 = P2_9,
+ GPIO1_11 = P2_11,
+ GPIO1_12 = P2_12,
+ GPIO1_13 = P2_13,
+ GPIO1_14 = P3_4,
+ GPIO1_15 = P3_5,
+
+ GPIO2_0 = P4_0,
+ GPIO2_1 = P4_1,
+ GPIO2_2 = P4_2,
+ GPIO2_3 = P4_3,
+ GPIO2_4 = P4_4,
+ GPIO2_5 = P4_5,
+ GPIO2_6 = P4_6,
+ GPIO2_7 = P5_7,
+ GPIO2_8 = P6_12,
+ GPIO2_9 = P5_0,
+ GPIO2_10 = P5_1,
+ GPIO2_11 = P5_2,
+ GPIO2_12 = P5_3,
+ GPIO2_13 = P5_4,
+ GPIO2_14 = P5_5,
+ GPIO2_15 = P5_6,
+
+ GPIO3_0 = P6_1,
+ GPIO3_1 = P6_2,
+ GPIO3_2 = P6_3,
+ GPIO3_3 = P6_4,
+ GPIO3_4 = P6_5,
+ GPIO3_5 = P6_9,
+ GPIO3_6 = P6_10,
+ GPIO3_7 = P6_11,
+ GPIO3_8 = P7_0,
+ GPIO3_9 = P7_1,
+ GPIO3_10 = P7_2,
+ GPIO3_11 = P7_3,
+ GPIO3_12 = P7_4,
+ GPIO3_13 = P7_5,
+ GPIO3_14 = P7_6,
+ GPIO3_15 = P7_7,
+
+ GPIO4_0 = P8_0,
+ GPIO4_1 = P8_1,
+ GPIO4_2 = P8_2,
+ GPIO4_3 = P8_3,
+ GPIO4_4 = P8_4,
+ GPIO4_5 = P8_5,
+ GPIO4_6 = P8_6,
+ GPIO4_7 = P8_7,
+ GPIO4_8 = PA_1,
+ GPIO4_9 = PA_2,
+ GPIO4_10 = PA_3,
+ GPIO4_11 = P9_6,
+ GPIO4_12 = P9_0,
+ GPIO4_13 = P9_1,
+ GPIO4_14 = P9_2,
+ GPIO4_15 = P9_3,
+
+ GPIO5_0 = P2_0,
+ GPIO5_1 = P2_1,
+ GPIO5_2 = P2_2,
+ GPIO5_3 = P2_3,
+ GPIO5_4 = P2_4,
+ GPIO5_5 = P2_5,
+ GPIO5_6 = P2_6,
+ GPIO5_7 = P2_8,
+ GPIO5_8 = P3_1,
+ GPIO5_9 = P3_2,
+ GPIO5_10 = P3_7,
+ GPIO5_11 = P3_8,
+ GPIO5_12 = P4_8,
+ GPIO5_13 = P4_9,
+ GPIO5_14 = P4_10,
+ GPIO5_15 = P6_7,
+ GPIO5_16 = P6_8,
+ GPIO5_17 = P9_4,
+ GPIO5_18 = P9_5,
+ GPIO5_19 = PA_4,
+ GPIO5_20 = PB_0,
+ GPIO5_21 = PB_1,
+ GPIO5_22 = PB_2,
+ GPIO5_23 = PB_3,
+ GPIO5_24 = PB_4,
+ GPIO5_25 = PB_5,
+ GPIO5_26 = PB_6,
+
+ GPIO6_0 = PC_1,
+ GPIO6_1 = PC_2,
+ GPIO6_2 = PC_3,
+ GPIO6_3 = PC_4,
+ GPIO6_4 = PC_5,
+ GPIO6_5 = PC_6,
+ GPIO6_6 = PC_7,
+ GPIO6_7 = PC_8,
+ GPIO6_8 = PC_9,
+ GPIO6_9 = PC_10,
+ GPIO6_10 = PC_11,
+ GPIO6_11 = PC_12,
+ GPIO6_12 = PC_13,
+ GPIO6_13 = PC_14,
+ GPIO6_14 = PD_0,
+ GPIO6_15 = PD_1,
+ GPIO6_16 = PD_2,
+ GPIO6_17 = PD_3,
+ GPIO6_18 = PD_4,
+ GPIO6_19 = PD_5,
+ GPIO6_20 = PD_6,
+ GPIO6_21 = PD_7,
+ GPIO6_22 = PD_8,
+ GPIO6_23 = PD_9,
+ GPIO6_24 = PD_10,
+ GPIO6_25 = PD_11,
+ GPIO6_26 = PD_12,
+ GPIO6_27 = PD_13,
+ GPIO6_28 = PD_14,
+ GPIO6_29 = PD_15,
+ GPIO6_30 = PD_16,
+
+ GPIO7_0 = PE_0,
+ GPIO7_1 = PE_1,
+ GPIO7_2 = PE_2,
+ GPIO7_3 = PE_3,
+ GPIO7_4 = PE_4,
+ GPIO7_5 = PE_5,
+ GPIO7_6 = PE_5,
+ GPIO7_7 = PE_7,
+ GPIO7_8 = PE_8,
+ GPIO7_9 = PE_9,
+ GPIO7_10 = PE_10,
+ GPIO7_11 = PE_11,
+ GPIO7_12 = PE_12,
+ GPIO7_13 = PE_13,
+ GPIO7_14 = PE_14,
+ GPIO7_15 = PE_15,
+ GPIO7_16 = PF_1,
+ GPIO7_17 = PF_2,
+ GPIO7_18 = PF_3,
+ GPIO7_19 = PF_5,
+ GPIO7_20 = PF_6,
+ GPIO7_21 = PF_7,
+ GPIO7_22 = PF_8,
+ GPIO7_23 = PF_9,
+ GPIO7_24 = PF_10,
+ GPIO7_25 = PF_11,
+
+ // Map mbed pin names to LPC43xx board signals
+
+ // Group 0x18 : CLKn pins
+ SFP_CLK0 = MBED_PIN(0x18, 0, 0, 0),
+ SFP_CLK1 = MBED_PIN(0x18, 1, 0, 0),
+ SFP_CLK2 = MBED_PIN(0x18, 2, 0, 0),
+ SFP_CLK3 = MBED_PIN(0x18, 3, 0, 0),
+
+ // Group 0x19 : USB1, I2C0, ADC0, ADC1
+ SFP_USB1 = MBED_PIN(0x19, 0, 0, 0),
+ SFP_I2C0 = MBED_PIN(0x19, 1, 0, 0),
+ SFP_AIO0 = MBED_PIN(0x19, 2, 0, 0), // ADC0 function select register
+ SFP_AIO1 = MBED_PIN(0x19, 3, 0, 0), // ADC1 function select register
+ SFP_AIO2 = MBED_PIN(0x19, 4, 0, 0), // Analog function select register
+
+ SFP_EMCD = MBED_PIN(0x1A, 0, 0, 0), // EMC clock delay register
+
+ SFP_INS0 = MBED_PIN(0x1C, 0, 0, 0), // Interrupt select for pin interrupts 0 to 3
+ SFP_INS1 = MBED_PIN(0x1C, 1, 0, 0), // Interrupt select for pin interrupts 4 to 7
+
+/*
+#define MBED_ADC_NUM(MBED_PIN) ((MBED_PIN >> 5) & 0x0000000F)
+#define MBED_ADC_CHAN(MBED_PIN) (MBED_PIN & 0x0000001F)
+
+ // Use pseudo-pin ID also for ADCs, although with special handling
+ SFP_ADC0_0 = MBED_PIN(0x19, 2, 0, 0), // ADC0_0
+ SFP_ADC0_1 = MBED_PIN(0x19, 2, 0, 1), // ADC0_1
+ SFP_ADC0_2 = MBED_PIN(0x19, 2, 0, 2), // ADC0_2
+ SFP_ADC0_3 = MBED_PIN(0x19, 2, 0, 3), // ADC0_3
+ SFP_ADC0_4 = MBED_PIN(0x19, 2, 0, 4), // ADC0_4
+ SFP_ADC0_5 = MBED_PIN(0x19, 2, 0, 5), // ADC0_5
+ SFP_ADC0_6 = MBED_PIN(0x19, 2, 0, 6), // ADC0_6
+
+ SFP_ADC1_0 = MBED_PIN(0x19, 3, 1, 0), // ADC1_0
+ SFP_ADC1_1 = MBED_PIN(0x19, 3, 1, 1), // ADC1_1
+ SFP_ADC1_2 = MBED_PIN(0x19, 3, 1, 2), // ADC1_2
+ SFP_ADC1_3 = MBED_PIN(0x19, 3, 1, 3), // ADC1_3
+ SFP_ADC1_4 = MBED_PIN(0x19, 3, 1, 4), // ADC1_4
+ SFP_ADC1_5 = MBED_PIN(0x19, 3, 1, 5), // ADC1_5
+ SFP_ADC1_6 = MBED_PIN(0x19, 3, 1, 6), // ADC1_6
+ SFP_ADC1_7 = MBED_PIN(0x19, 3, 1, 7), // ADC1_7
+*/
+
+ // Dedicated pin (no GPIO)
+ P_DED = MBED_PIN(0, 0, NO_GPIO, 0),
+
+ // Not connected
+ NC = (int)0xFFFFFFFF,
+
+ // ---------- LPCXpresso 4337 pins ----------
+
+#ifdef BOARD_REV_A // for Rev.A
+ D0 = P2_1,
+ D1 = P2_0,
+ D2 = P1_20,
+ D3 = P1_18,
+ D4 = P1_16,
+ D5 = P1_15,
+ D6 = P1_4,
+ D7 = P2_2,
+ D8 = P1_0,
+ D9 = P1_3,
+ D10 = P1_5,
+ D11 = P0_1,
+ D12 = P0_0,
+ D13 = P1_19,
+ SDA = P2_3,
+ SCL = P2_4,
+
+ A0 = P4_3,
+ A1 = P4_1,
+ A2 = PF_8,
+ A3 = P7_5,
+ A4 = P1_14,
+ A5 = P2_5,
+
+ LED_GREEN = GPIO0_14,
+ LED_RED = GPIO3_7,
+ LED_BLUE = GPIO3_5,
+
+ // Serial pins
+ UART0_TX = P2_0,
+ UART0_RX = P2_1,
+ USBTX = UART0_TX,
+ USBRX = UART0_RX,
+#else // for Rev.B
+ D0 = P1_14,
+ D1 = P3_4,
+ D2 = P2_13,
+ D3 = P1_8,
+ D4 = P2_6,
+ D5 = P1_7,
+ D6 = P2_9,
+ D7 = P2_2,
+ D8 = P3_5,
+ D9 = P1_2,
+ D10 = P1_5,
+ D11 = P1_4,
+ D12 = P1_3,
+ D13 = PF_4,
+ SDA = P2_3,
+ SCL = P2_4,
+
+ A0 = P4_3,
+ A1 = P4_1,
+ A2 = PF_8,
+ A3 = P7_5,
+ A4 = P2_11,
+ A5 = P2_5,
+
+ LED_GREEN = P2_10,
+ LED_RED = P6_11,
+ LED_BLUE = P6_9,
+
+ // Serial pins
+ UART0_TX = P6_4,
+ UART0_RX = P2_1,
+ UART1_TX = D1,
+ UART1_RX = D0,
+ USBTX = UART0_TX,
+ USBRX = UART0_RX,
+#endif
+
+ I2C_SDA = SDA,
+ I2C_SDL = SCL,
+
+ LED1 = LED_RED,
+ LED2 = LED_BLUE,
+ LED3 = LED_GREEN,
+ LED4 = LED_RED,
+
+// UART1_TX = P5_6,
+// UART1_RX = P1_14,
+// UART2_TX = P2_10,
+// UART2_RX = P2_11,
+// UART3_TX = P2_3,
+// UART3_RX = P2_4,
+
+/*
+ // Analog pins
+ ADC4 = P4_3,
+ ADC2 = P4_1,
+ ADC0 = P7_4,
+ ADC1 = P7_5,
+ ADC3 = P7_7,
+ DAC0 = P4_4,
+*/
+
+ // USB pins
+ //P_USB0_TX = SFP_USB1,
+ //P_USB0_RX = SFP_USB1,
+
+
+/*
+ // PWM pins
+ // 210E 210 200E 200
+ // ---- ---- ---- ----
+ PWM1 = P1_7, // J9-3 J9-3 S2-3 S2-3
+ PWM2 = P7_6, // J9-8 J9-8 S4-6 S4-6
+ PWM3 = P6_12, // J10-1 J10-1 S10-3 n/p
+ PWM4 = P4_6, // J10-3 J10-3 S2-6 S2-6
+ PWM5 = P7_5, // J8-2 J8-2 S4-4 S4-4
+ PWM6 = P4_1, // J8-3 J8-3 S3-4 S3-4
+ PWM7 = P7_7, // J8-4 J8-4 S4-5 S4-5
+ PWM8 = P2_8, // J12-4 n/p S8-3 n/p
+ PWM9 = P2_9, // J12-6 n/p S9-3 n/p
+ PWM10 = P7_1, // J13-5 n/p S9-8 n/p
+ PWM11 = P7_0, // J13-6 n/p S9-9 n/p
+ PWM12 = P1_5, // J14-7 n/p S10-6 n/p
+*/
+
+ // ---------- End of LPCXpresso 4337 pins ----------
+} PinName;
+
+typedef enum {
+ PullUp = 0,
+ PullDown = 3,
+ PullNone = 2,
+ Repeater = 1,
+ OpenDrain = 4,
+ PullDefault = PullDown
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_LPC4337/TARGET_NXP/TARGET_LPC43XX/TARGET_LPC4337/device.h Fri Sep 12 16:41:52 2014 +0100 @@ -0,0 +1,59 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 1 + +#define DEVICE_ETHERNET 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 32 +#define DEVICE_MAC_OFFSET 20 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 1 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 1 + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC4337/TARGET_NXP/TARGET_LPC43XX/gpio_object.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,52 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "mbed_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ uint32_t mask;
+
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_set;
+ __IO uint32_t *reg_clr;
+ __I uint32_t *reg_in;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ if (value)
+ *obj->reg_set = obj->mask;
+ else
+ *obj->reg_clr = obj->mask;
+}
+
+static inline int gpio_read(gpio_t *obj) {
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC4337/TARGET_NXP/TARGET_LPC43XX/objects.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,79 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ uint32_t port;
+ uint32_t pin;
+ uint32_t ch;
+};
+
+struct port_s {
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_out;
+ __I uint32_t *reg_in;
+ PortName port;
+ uint32_t mask;
+};
+
+struct pwmout_s {
+ PWMName pwm;
+ uint8_t mr;
+};
+
+struct serial_s {
+ LPC_USART_T *uart;
+ int index;
+};
+
+struct analogin_s {
+ LPC_ADC_T *adc;
+ uint8_t num;
+ uint8_t ch;
+};
+
+struct dac_s {
+ DACName dac;
+};
+
+struct can_s {
+ LPC_CCAN_T *dev;
+};
+
+struct i2c_s {
+ LPC_I2C_T *i2c;
+};
+
+struct spi_s {
+ LPC_SSP_T *spi;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC4337/TOOLCHAIN_ARM_STD/LPC4337.sct Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,22 @@
+
+LR_IROM1 0x1A000000 0x00080000 { ; load region size_region
+ ER_IROM1 0x1A000000 0x00080000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+; ER_IROM2 0x1B000000 0x00080000 { ; load address = execution address
+; .ANY (+RO)
+; }
+
+ ; 8_byte_aligned(69 vect * 4 bytes) = 8_byte_aligned(0x0114) = 0x0118
+ RW_IRAM1 0x10000000+0x118 0x8000-0x118 {
+ .ANY (+RW +ZI)
+ }
+; RW_IRAM2 0x10080000 0xA000 { ; RW data
+; .ANY (IRAM2)
+; }
+; RW_IRAM3 0x20000000 0x10000 { ; RW data
+; .ANY (AHBSRAM)
+; }
+}
Binary file TARGET_LPC4337/TOOLCHAIN_ARM_STD/board.o has changed
Binary file TARGET_LPC4337/TOOLCHAIN_ARM_STD/cmsis_nvic.o has changed
Binary file TARGET_LPC4337/TOOLCHAIN_ARM_STD/mbed.ar has changed
Binary file TARGET_LPC4337/TOOLCHAIN_ARM_STD/retarget.o has changed
Binary file TARGET_LPC4337/TOOLCHAIN_ARM_STD/startup_LPC4337.o has changed
Binary file TARGET_LPC4337/TOOLCHAIN_ARM_STD/sys.o has changed
Binary file TARGET_LPC4337/TOOLCHAIN_ARM_STD/system_LPC43xx.o has changed
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_LPC4337/cmsis.h Fri Sep 12 16:41:52 2014 +0100 @@ -0,0 +1,15 @@ +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in LPC43xx specifics + * + * Ported to NXP LPC43XX by Micromint USA <support@micromint.com> + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "LPC43xx.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC4337/cmsis_nvic.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,26 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 53) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC4337/core_cm0.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,682 @@
+/**************************************************************************//**
+ * @file core_cm0.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+ @{
+ */
+
+/* CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+ __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0_REV
+ #define __CM0_REV 0x0000
+ #warning "__CM0_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
+ else {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC4337/core_cm0plus.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,793 @@
+/**************************************************************************//**
+ * @file core_cm0plus.h
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+ @{
+ */
+
+/* CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+ __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0PLUS_REV
+ #define __CM0PLUS_REV 0x0000
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if (__VTOR_PRESENT == 1)
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
+ else {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC4337/core_cm3.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,1627 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC4337/core_cm4.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,1772 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+ @{
+ */
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x04) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+#include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/** \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1)
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
+ NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC4337/core_cm4_simd.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,673 @@
+/**************************************************************************//**
+ * @file core_cm4_simd.h
+ * @brief CMSIS Cortex-M4 SIMD Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32) ) >> 32))
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_iar.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_ccs.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC4337/core_cmFunc.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,636 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief Enable IRQ Interrupts
+
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief Disable IRQ Interrupts
+
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ uint32_t result;
+
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC4337/core_cmInstr.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,688 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V3.20
+ * @date 05. March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/** \brief Breakpoint
+
+ This function causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __rbit
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX __clrex
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb");
+}
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb");
+}
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb");
+}
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (short)__builtin_bswap16(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32 - op2));
+}
+
+
+/** \brief Breakpoint
+
+ This function causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC4337/system_LPC43xx.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,90 @@
+/*
+ * @brief LPC43xx/LPC18xx mcu header
+ *
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products. This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights. NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers. This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SYSTEM_LPC43XX_H
+#define __SYSTEM_LPC43XX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* System initialization options */
+#define PIN_SETUP 1 /* Configure pins during initialization */
+#define CLOCK_SETUP 1 /* Configure clocks during initialization */
+#define MEMORY_SETUP 0 /* Configure external memory during init */
+#define SPIFI_INIT 1 /* Initialize SPIFI */
+
+/* Crystal frequency into device */
+#define CRYSTAL_MAIN_FREQ_IN 12000000
+
+/* Crystal frequency into device for RTC/32K input */
+#define CRYSTAL_32K_FREQ_IN 32768
+
+/* Default CPU clock frequency */
+#if defined(CHIP_LPC43XX)
+#define MAX_CLOCK_FREQ (204000000)
+#else
+#define MAX_CLOCK_FREQ (180000000)
+#endif
+
+#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
+ /* FPU declarations */
+ #define LPC_CPACR 0xE000ED88
+
+ #define SCB_MVFR0 0xE000EF40
+ #define SCB_MVFR0_RESET 0x10110021
+
+ #define SCB_MVFR1 0xE000EF44
+ #define SCB_MVFR1_RESET 0x11000011
+
+ #if defined(__ARMCC_VERSION)
+ void fpuInit(void) __attribute__ ((section("BOOTSTRAP_CODE")));
+ #else
+ extern void fpuInit(void);
+ #endif
+#endif
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC43XX_H */
Binary file TARGET_LPC812/TOOLCHAIN_ARM_MICRO/board.o has changed
Binary file TARGET_LPC812/TOOLCHAIN_ARM_MICRO/cmsis_nvic.o has changed
Binary file TARGET_LPC812/TOOLCHAIN_ARM_MICRO/mbed.ar has changed
Binary file TARGET_LPC812/TOOLCHAIN_ARM_MICRO/retarget.o has changed
Binary file TARGET_LPC812/TOOLCHAIN_ARM_MICRO/sys.o has changed
Binary file TARGET_LPC812/TOOLCHAIN_ARM_MICRO/system_LPC8xx.o has changed
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_button.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,187 @@
+/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup app_button Button Handler
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Buttons handling module.
+ *
+ * @details The button handler uses the @ref app_gpiote to detect that a button has been
+ * pushed. To handle debouncing, it will start a timer in the GPIOTE event handler.
+ * The button will only be reported as pushed if the corresponding pin is still active when
+ * the timer expires. If there is a new GPIOTE event while the timer is running, the timer
+ * is restarted.
+ * Use the USE_SCHEDULER parameter of the APP_BUTTON_INIT() macro to select if the
+ * @ref app_scheduler is to be used or not.
+ *
+ * @note The app_button module uses the app_timer module. The user must ensure that the queue in
+ * app_timer is large enough to hold the app_timer_stop() / app_timer_start() operations
+ * which will be executed on each event from GPIOTE module (2 operations), as well as other
+ * app_timer operations queued simultaneously in the application.
+ *
+ * @note Even if the scheduler is not used, app_button.h will include app_scheduler.h, so when
+ * compiling, app_scheduler.h must be available in one of the compiler include paths.
+ */
+
+#ifndef APP_BUTTON_H__
+#define APP_BUTTON_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "app_error.h"
+#include "app_scheduler.h"
+#include "nrf_gpio.h"
+
+#define APP_BUTTON_SCHED_EVT_SIZE sizeof(app_button_event_t) /**< Size of button events being passed through the scheduler (is to be used for computing the maximum size of scheduler events). */
+#define APP_BUTTON_PUSH 1 /**< Indicates that a button is pushed. */
+#define APP_BUTTON_RELEASE 0 /**< Indicates that a button is released. */
+#define APP_BUTTON_ACTIVE_HIGH 1 /**< Indicates that a button is active high. */
+#define APP_BUTTON_ACTIVE_LOW 0 /**< Indicates that a button is active low. */
+
+/**@brief Button event handler type. */
+typedef void (*app_button_handler_t)(uint8_t pin_no, uint8_t button_action);
+
+/**@brief Type of function for passing events from the Button Handler module to the scheduler. */
+typedef uint32_t (*app_button_evt_schedule_func_t) (app_button_handler_t button_handler,
+ uint8_t pin_no,
+ uint8_t button_action);
+
+/**@brief Button configuration structure. */
+typedef struct
+{
+ uint8_t pin_no; /**< Pin to be used as a button. */
+ uint8_t active_state; /**< APP_BUTTON_ACTIVE_HIGH or APP_BUTTON_ACTIVE_LOW. */
+ nrf_gpio_pin_pull_t pull_cfg; /**< Pull-up or -down configuration. */
+ app_button_handler_t button_handler; /**< Handler to be called when button is pushed. */
+} app_button_cfg_t;
+
+/**@brief Pin transition direction struct. */
+typedef struct
+{
+ uint32_t high_to_low; /**Pin went from high to low */
+ uint32_t low_to_high; /**Pin went from low to high */
+} pin_transition_t;
+
+/**@brief Macro for initializing the Button Handler module.
+ *
+ * @details It will initialize the specified pins as buttons, and configure the Button Handler
+ * module as a GPIOTE user (but it will not enable button detection). It will also connect
+ * the Button Handler module to the scheduler (if specified).
+ *
+ * @param[in] BUTTONS Array of buttons to be used (type app_button_cfg_t, must be
+ * static!).
+ * @param[in] BUTTON_COUNT Number of buttons.
+ * @param[in] DETECTION_DELAY Delay from a GPIOTE event until a button is reported as pushed.
+ * @param[in] USE_SCHEDULER TRUE if the application is using the event scheduler,
+ * FALSE otherwise.
+ */
+/*lint -emacro(506, APP_BUTTON_INIT) */ /* Suppress "Constant value Boolean */
+#define APP_BUTTON_INIT(BUTTONS, BUTTON_COUNT, DETECTION_DELAY, USE_SCHEDULER) \
+ do \
+ { \
+ uint32_t ERR_CODE = app_button_init((BUTTONS), \
+ (BUTTON_COUNT), \
+ (DETECTION_DELAY), \
+ (USE_SCHEDULER) ? app_button_evt_schedule : NULL); \
+ APP_ERROR_CHECK(ERR_CODE); \
+ } while (0)
+
+/**@brief Function for initializing the Buttons.
+ *
+ * @details This function will initialize the specified pins as buttons, and configure the Button
+ * Handler module as a GPIOTE user (but it will not enable button detection).
+ *
+ * @note Normally initialization should be done using the APP_BUTTON_INIT() macro, as that will take
+ * care of connecting the Buttons module to the scheduler (if specified).
+ *
+ * @note app_button_enable() function must be called in order to enable the button detection.
+ *
+ * @param[in] p_buttons Array of buttons to be used (NOTE: Must be static!).
+ * @param[in] button_count Number of buttons.
+ * @param[in] detection_delay Delay from a GPIOTE event until a button is reported as pushed.
+ * @param[in] evt_schedule_func Function for passing button events to the scheduler. Point to
+ * app_button_evt_schedule() to connect to the scheduler. Set to
+ * NULL to make the Buttons module call the event handler directly
+ * from the delayed button push detection timeout handler.
+ *
+ * @return NRF_SUCCESS on success, otherwise an error code.
+ */
+uint32_t app_button_init(app_button_cfg_t * p_buttons,
+ uint8_t button_count,
+ uint32_t detection_delay,
+ app_button_evt_schedule_func_t evt_schedule_func);
+
+/**@brief Function for enabling button detection.
+ *
+ * @retval NRF_ERROR_INVALID_PARAM GPIOTE has to many users.
+ * @retval NRF_ERROR_INVALID_STATE Button or GPIOTE not initialized.
+ * @retval NRF_SUCCESS Button detection successfully enabled.
+ */
+uint32_t app_button_enable(void);
+
+/**@brief Function for disabling button detection.
+ *
+ * @retval NRF_ERROR_INVALID_PARAM GPIOTE has to many users.
+ * @retval NRF_ERROR_INVALID_STATE Button or GPIOTE not initialized.
+ * @retval NRF_SUCCESS Button detection successfully enabled.
+ */
+uint32_t app_button_disable(void);
+
+/**@brief Function for checking if a button is currently being pushed.
+ *
+ * @param[in] pin_no Button pin to be checked.
+ * @param[out] p_is_pushed Button state.
+ *
+ * @retval NRF_SUCCESS State successfully read.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid pin_no.
+ */
+uint32_t app_button_is_pushed(uint8_t pin_no, bool * p_is_pushed);
+
+
+// Type and functions for connecting the Buttons module to the scheduler:
+
+/**@cond NO_DOXYGEN */
+typedef struct
+{
+ app_button_handler_t button_handler;
+ uint8_t pin_no;
+ uint8_t button_action;
+} app_button_event_t;
+
+static __INLINE void app_button_evt_get(void * p_event_data, uint16_t event_size)
+{
+ app_button_event_t * p_buttons_event = (app_button_event_t *)p_event_data;
+
+ APP_ERROR_CHECK_BOOL(event_size == sizeof(app_button_event_t));
+ p_buttons_event->button_handler(p_buttons_event->pin_no, p_buttons_event->button_action);
+}
+
+static __INLINE uint32_t app_button_evt_schedule(app_button_handler_t button_handler,
+ uint8_t pin_no,
+ uint8_t button_action)
+{
+ app_button_event_t buttons_event;
+
+ buttons_event.button_handler = button_handler;
+ buttons_event.pin_no = pin_no;
+ buttons_event.button_action = button_action;
+
+ return app_sched_event_put(&buttons_event, sizeof(buttons_event), app_button_evt_get);
+}
+/**@endcond */
+
+#endif // APP_BUTTON_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_error.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,84 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup app_error Common application error handler
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Common application error handler and macros for utilizing a common error handler.
+ */
+
+#ifndef APP_ERROR_H__
+#define APP_ERROR_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "nrf_error.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@brief Function for error handling, which is called when an error has occurred.
+ *
+ * @param[in] error_code Error code supplied to the handler.
+ * @param[in] line_num Line number where the handler is called.
+ * @param[in] p_file_name Pointer to the file name.
+ */
+void app_error_handler(uint32_t error_code, uint32_t line_num, const uint8_t * p_file_name);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@brief Macro for calling error handler function.
+ *
+ * @param[in] ERR_CODE Error code supplied to the error handler.
+ */
+#define APP_ERROR_HANDLER(ERR_CODE) \
+ do \
+ { \
+ /* app_error_handler((ERR_CODE), __LINE__, (uint8_t*) __FILE__); */ \
+ } while (0)
+
+/**@brief Macro for calling error handler function if supplied error code any other than NRF_SUCCESS.
+ *
+ * @param[in] ERR_CODE Error code supplied to the error handler.
+ */
+#define APP_ERROR_CHECK(ERR_CODE) \
+ do \
+ { \
+ const uint32_t LOCAL_ERR_CODE = (ERR_CODE); \
+ if (LOCAL_ERR_CODE != NRF_SUCCESS) \
+ { \
+ APP_ERROR_HANDLER(LOCAL_ERR_CODE); \
+ } \
+ } while (0)
+
+/**@brief Macro for calling error handler function if supplied boolean value is false.
+ *
+ * @param[in] BOOLEAN_VALUE Boolean value to be evaluated.
+ */
+#define APP_ERROR_CHECK_BOOL(BOOLEAN_VALUE) \
+ do \
+ { \
+ const bool LOCAL_BOOLEAN_VALUE = (BOOLEAN_VALUE); \
+ if (!LOCAL_BOOLEAN_VALUE) \
+ { \
+ APP_ERROR_HANDLER(0); \
+ } \
+ } while (0)
+
+#endif // APP_ERROR_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_fifo.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,83 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/**@file
+ *
+ * @defgroup app_fifo FIFO implementation
+ * @{
+ * @ingroup app_common
+ *
+ * @brief FIFO implementation.
+ */
+
+#ifndef APP_FIFO_H__
+#define APP_FIFO_H__
+
+#include <stdint.h>
+#include <stdlib.h>
+#include "nrf_error.h"
+
+/**@brief A FIFO instance structure. Keeps track of which bytes to read and write next.
+ * Also it keeps the information about which memory is allocated for the buffer
+ * and its size. This needs to be initialized by app_fifo_init() before use.
+ */
+typedef struct
+{
+ uint8_t * p_buf; /**< Pointer to FIFO buffer memory. */
+ uint16_t buf_size_mask; /**< Read/write index mask. Also used for size checking. */
+ volatile uint32_t read_pos; /**< Next read position in the FIFO buffer. */
+ volatile uint32_t write_pos; /**< Next write position in the FIFO buffer. */
+} app_fifo_t;
+
+/**@brief Function for initializing the FIFO.
+ *
+ * @param[out] p_fifo FIFO object.
+ * @param[in] p_buf FIFO buffer for storing data. The buffer size has to be a power of two.
+ * @param[in] buf_size Size of the FIFO buffer provided, has to be a power of 2.
+ *
+ * @retval NRF_SUCCESS If initialization was successful.
+ * @retval NRF_ERROR_NULL If a NULL pointer is provided as buffer.
+ * @retval NRF_ERROR_INVALID_LENGTH If size of buffer provided is not a power of two.
+ */
+uint32_t app_fifo_init(app_fifo_t * p_fifo, uint8_t * p_buf, uint16_t buf_size);
+
+/**@brief Function for adding an element to the FIFO.
+ *
+ * @param[in] p_fifo Pointer to the FIFO.
+ * @param[in] byte Data byte to add to the FIFO.
+ *
+ * @retval NRF_SUCCESS If an element has been successfully added to the FIFO.
+ * @retval NRF_ERROR_NO_MEM If the FIFO is full.
+ */
+uint32_t app_fifo_put(app_fifo_t * p_fifo, uint8_t byte);
+
+/**@brief Function for getting the next element from the FIFO.
+ *
+ * @param[in] p_fifo Pointer to the FIFO.
+ * @param[out] p_byte Byte fetched from the FIFO.
+ *
+ * @retval NRF_SUCCESS If an element was returned.
+ * @retval NRF_ERROR_NOT_FOUND If there is no more elements in the queue.
+ */
+uint32_t app_fifo_get(app_fifo_t * p_fifo, uint8_t * p_byte);
+
+/**@brief Function for flushing the FIFO.
+ *
+ * @param[in] p_fifo Pointer to the FIFO.
+ *
+ * @retval NRF_SUCCESS If the FIFO flushed successfully.
+ */
+uint32_t app_fifo_flush(app_fifo_t * p_fifo);
+
+#endif // APP_FIFO_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_gpiote.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,226 @@
+/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup app_gpiote GPIOTE Handler
+ * @{
+ * @ingroup app_common
+ *
+ * @brief GPIOTE handler module.
+ *
+ * @details The GPIOTE handler allows several modules ("users") to share the GPIOTE interrupt,
+ * each user defining a set of pins able to generate events to the user.
+ * When a GPIOTE interrupt occurs, the GPIOTE interrupt handler will call the event handler
+ * of each user for which at least one of the pins generated an event.
+ *
+ * The GPIOTE users are responsible for configuring all their corresponding pins, except
+ * the SENSE field, which should be initialized to GPIO_PIN_CNF_SENSE_Disabled.
+ * The SENSE field will be updated by the GPIOTE module when it is enabled or disabled,
+ * and also while it is enabled.
+ *
+ * The module specifies on which pins events should be generated if the pin(s) goes
+ * from low->high or high->low or both directions.
+ *
+ * @note Even if the application is using the @ref app_scheduler, the GPIOTE event handlers will
+ * be called directly from the GPIOTE interrupt handler.
+ *
+ * @warning If multiple users registers for the same pins the behavior for those pins are undefined.
+ */
+
+#ifndef APP_GPIOTE_H__
+#define APP_GPIOTE_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+// #include "nrf.h"
+#include "app_error.h"
+#include "app_util.h"
+
+#ifdef __cpluplus
+extern "C" {
+#endif
+
+#define GPIOTE_USER_NODE_SIZE 20 /**< Size of app_gpiote.gpiote_user_t (only for use inside APP_GPIOTE_BUF_SIZE()). */
+#define NO_OF_PINS 32 /**< Number of GPIO pins on the nRF51 chip. */
+
+/**@brief Compute number of bytes required to hold the GPIOTE data structures.
+ *
+ * @param[in] MAX_USERS Maximum number of GPIOTE users.
+ *
+ * @return Required buffer size (in bytes).
+ */
+#define APP_GPIOTE_BUF_SIZE(MAX_USERS) ((MAX_USERS) * GPIOTE_USER_NODE_SIZE)
+
+typedef uint8_t app_gpiote_user_id_t;
+
+/**@brief GPIOTE event handler type. */
+typedef void (*app_gpiote_event_handler_t)(uint32_t event_pins_low_to_high,
+ uint32_t event_pins_high_to_low);
+
+/**@brief GPIOTE input event handler type. */
+typedef void (*app_gpiote_input_event_handler_t)(void);
+
+/**@brief Macro for initializing the GPIOTE module.
+ *
+ * @details It will handle dimensioning and allocation of the memory buffer required by the module,
+ * making sure that the buffer is correctly aligned.
+ *
+ * @param[in] MAX_USERS Maximum number of GPIOTE users.
+ *
+ * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it
+ * several times as long as it is from the same location, e.g. to do a reinitialization).
+ */
+/*lint -emacro(506, APP_GPIOTE_INIT) */ /* Suppress "Constant value Boolean */
+#define APP_GPIOTE_INIT(MAX_USERS) \
+ do \
+ { \
+ static uint32_t app_gpiote_buf[CEIL_DIV(APP_GPIOTE_BUF_SIZE(MAX_USERS), sizeof(uint32_t))];\
+ uint32_t ERR_CODE = app_gpiote_init((MAX_USERS), app_gpiote_buf); \
+ APP_ERROR_CHECK(ERR_CODE); \
+ } while (0)
+
+/**@brief Function for initializing the GPIOTE module.
+ *
+ * @note Normally initialization should be done using the APP_GPIOTE_INIT() macro, as that will
+ * allocate the buffer needed by the GPIOTE module (including aligning the buffer correctly).
+ *
+ * @param[in] max_users Maximum number of GPIOTE users.
+ * @param[in] p_buffer Pointer to memory buffer for internal use in the app_gpiote
+ * module. The size of the buffer can be computed using the
+ * APP_GPIOTE_BUF_SIZE() macro. The buffer must be aligned to
+ * a 4 byte boundary.
+ *
+ * @retval NRF_SUCCESS Successful initialization.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte
+ * boundary).
+ */
+uint32_t app_gpiote_init(uint8_t max_users, void * p_buffer);
+
+/**@brief Function for registering a GPIOTE user.
+ *
+ * @param[out] p_user_id Id for the new GPIOTE user.
+ * @param[in] pins_low_to_high_mask Mask defining which pins will generate events to this user
+ * when state is changed from low->high.
+ * @param[in] pins_high_to_low_mask Mask defining which pins will generate events to this user
+ * when state is changed from high->low.
+ * @param[in] event_handler Pointer to function to be executed when an event occurs.
+ *
+ * @retval NRF_SUCCESS Successful initialization.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte boundary).
+ * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE
+ * module.
+ * @retval NRF_ERROR_NO_MEM Returned if the application tries to register more users
+ * than defined when the GPIOTE module was initialized in
+ * @ref app_gpiote_init.
+ */
+uint32_t app_gpiote_user_register(app_gpiote_user_id_t * p_user_id,
+ uint32_t pins_low_to_high_mask,
+ uint32_t pins_high_to_low_mask,
+ app_gpiote_event_handler_t event_handler);
+
+/**@brief Function for informing the GPIOTE module that the specified user wants to use the GPIOTE module.
+ *
+ * @param[in] user_id Id of user to enable.
+ *
+ * @retval NRF_SUCCESS On success.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid user_id provided, No a valid user.
+ * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE
+ * module.
+ */
+uint32_t app_gpiote_user_enable(app_gpiote_user_id_t user_id);
+
+/**@brief Function for informing the GPIOTE module that the specified user is done using the GPIOTE module.
+ *
+ * @param[in] user_id Id of user to enable.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid user_id provided, No a valid user.
+ * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE
+ * module.
+ */
+uint32_t app_gpiote_user_disable(app_gpiote_user_id_t user_id);
+
+/**@brief Function for getting the state of the pins which are registered for the specified user.
+ *
+ * @param[in] user_id Id of user to check.
+ * @param[out] p_pins Bit mask corresponding to the pins configured to generate events to
+ * the specified user. All bits corresponding to pins in the state
+ * 'high' will have value '1', all others will have value '0'.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid user_id provided, No a valid user.
+ * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE
+ * module.
+ */
+uint32_t app_gpiote_pins_state_get(app_gpiote_user_id_t user_id, uint32_t * p_pins);
+
+/**@brief Function for registering event handlers for GPIOTE IN events.
+ *
+ * @param[in] channel GPIOTE channel [0..3].
+ * @param[in] pin Pins associated with GPIOTE channel. Changes on following pins will generate events.
+ * @param[in] polarity Specify operation on input that shall trigger IN event.
+ * @param[in] event_handler Event handler invoked on the IN event in the GPIOTE interrupt.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid channel or pin number.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events.
+ */
+uint32_t app_gpiote_input_event_handler_register(const uint8_t channel,
+ const uint32_t pin,
+ const uint32_t polarity,
+ app_gpiote_input_event_handler_t event_handler);
+
+/**@brief Function for unregistering event handlers for GPIOTE IN events.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events.
+ */
+uint32_t app_gpiote_input_event_handler_unregister(const uint8_t channel);
+
+/**@brief Function for registering event handler invoked at the end of a GPIOTE interrupt.
+ *
+ * @param[in] event_handler Event handler invoked at the end of the GPIOTE interrupt.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events.
+ */
+uint32_t app_gpiote_end_irq_event_handler_register(app_gpiote_input_event_handler_t event_handler);
+
+/**@brief Function for unregistering event handler invoked at the end of a GPIOTE interrupt.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events.
+ */
+uint32_t app_gpiote_end_irq_event_handler_unregister(void);
+
+/**@brief Function for enabling interrupts in the GPIOTE driver.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support.
+ */
+uint32_t app_gpiote_enable_interrupts(void);
+
+/**@brief Function for disabling interrupts in the GPIOTE driver.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support.
+ */
+uint32_t app_gpiote_disable_interrupts(void);
+
+#ifdef __cpluplus
+}
+#endif
+
+#endif // APP_GPIOTE_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_scheduler.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,134 @@
+/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup app_scheduler Scheduler
+ * @{
+ * @ingroup app_common
+ *
+ * @brief The scheduler is used for transferring execution from the interrupt context to the main
+ * context.
+ *
+ * @details See @ref ble_sdk_apps_seq_diagrams for sequence diagrams illustrating the flow of events
+ * when using the Scheduler.
+ *
+ * @section app_scheduler_req Requirements:
+ *
+ * @subsection main_context_logic Logic in main context:
+ *
+ * - Define an event handler for each type of event expected.
+ * - Initialize the scheduler by calling the APP_SCHED_INIT() macro before entering the
+ * application main loop.
+ * - Call app_sched_execute() from the main loop each time the application wakes up because of an
+ * event (typically when sd_app_evt_wait() returns).
+ *
+ * @subsection int_context_logic Logic in interrupt context:
+ *
+ * - In the interrupt handler, call app_sched_event_put()
+ * with the appropriate data and event handler. This will insert an event into the
+ * scheduler's queue. The app_sched_execute() function will pull this event and call its
+ * handler in the main context.
+ *
+ * For an example usage of the scheduler, please see the implementations of
+ * @ref ble_sdk_app_hids_mouse and @ref ble_sdk_app_hids_keyboard.
+ *
+ * @image html scheduler_working.jpg The high level design of the scheduler
+ */
+
+#ifndef APP_SCHEDULER_H__
+#define APP_SCHEDULER_H__
+
+#include <stdint.h>
+#include "app_error.h"
+
+#define APP_SCHED_EVENT_HEADER_SIZE 8 /**< Size of app_scheduler.event_header_t (only for use inside APP_SCHED_BUF_SIZE()). */
+
+/**@brief Compute number of bytes required to hold the scheduler buffer.
+ *
+ * @param[in] EVENT_SIZE Maximum size of events to be passed through the scheduler.
+ * @param[in] QUEUE_SIZE Number of entries in scheduler queue (i.e. the maximum number of events
+ * that can be scheduled for execution).
+ *
+ * @return Required scheduler buffer size (in bytes).
+ */
+#define APP_SCHED_BUF_SIZE(EVENT_SIZE, QUEUE_SIZE) \
+ (((EVENT_SIZE) + APP_SCHED_EVENT_HEADER_SIZE) * ((QUEUE_SIZE) + 1))
+
+/**@brief Scheduler event handler type. */
+typedef void (*app_sched_event_handler_t)(void * p_event_data, uint16_t event_size);
+
+/**@brief Macro for initializing the event scheduler.
+ *
+ * @details It will also handle dimensioning and allocation of the memory buffer required by the
+ * scheduler, making sure the buffer is correctly aligned.
+ *
+ * @param[in] EVENT_SIZE Maximum size of events to be passed through the scheduler.
+ * @param[in] QUEUE_SIZE Number of entries in scheduler queue (i.e. the maximum number of events
+ * that can be scheduled for execution).
+ *
+ * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it
+ * several times as long as it is from the same location, e.g. to do a reinitialization).
+ */
+#define APP_SCHED_INIT(EVENT_SIZE, QUEUE_SIZE) \
+ do \
+ { \
+ static uint32_t APP_SCHED_BUF[CEIL_DIV(APP_SCHED_BUF_SIZE((EVENT_SIZE), (QUEUE_SIZE)), \
+ sizeof(uint32_t))]; \
+ uint32_t ERR_CODE = app_sched_init((EVENT_SIZE), (QUEUE_SIZE), APP_SCHED_BUF); \
+ APP_ERROR_CHECK(ERR_CODE); \
+ } while (0)
+
+/**@brief Function for initializing the Scheduler.
+ *
+ * @details It must be called before entering the main loop.
+ *
+ * @param[in] max_event_size Maximum size of events to be passed through the scheduler.
+ * @param[in] queue_size Number of entries in scheduler queue (i.e. the maximum number of
+ * events that can be scheduled for execution).
+ * @param[in] p_event_buffer Pointer to memory buffer for holding the scheduler queue. It must
+ * be dimensioned using the APP_SCHED_BUFFER_SIZE() macro. The buffer
+ * must be aligned to a 4 byte boundary.
+ *
+ * @note Normally initialization should be done using the APP_SCHED_INIT() macro, as that will both
+ * allocate the scheduler buffer, and also align the buffer correctly.
+ *
+ * @retval NRF_SUCCESS Successful initialization.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte
+ * boundary).
+ */
+uint32_t app_sched_init(uint16_t max_event_size, uint16_t queue_size, void * p_evt_buffer);
+
+/**@brief Function for executing all scheduled events.
+ *
+ * @details This function must be called from within the main loop. It will execute all events
+ * scheduled since the last time it was called.
+ */
+void app_sched_execute(void);
+
+/**@brief Function for scheduling an event.
+ *
+ * @details Puts an event into the event queue.
+ *
+ * @param[in] p_event_data Pointer to event data to be scheduled.
+ * @param[in] p_event_size Size of event data to be scheduled.
+ * @param[in] handler Event handler to receive the event.
+ *
+ * @return NRF_SUCCESS on success, otherwise an error code.
+ */
+uint32_t app_sched_event_put(void * p_event_data,
+ uint16_t event_size,
+ app_sched_event_handler_t handler);
+
+#endif // APP_SCHEDULER_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_timer.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,313 @@
+/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup app_timer Application Timer
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Application timer functionality.
+ *
+ * @details It enables the application to create multiple timer instances based on the RTC1
+ * peripheral. Checking for timeouts and invokation of user timeout handlers is performed
+ * in the RTC1 interrupt handler. List handling is done using a software interrupt (SWI0).
+ * Both interrupt handlers are running in APP_LOW priority level.
+ *
+ * @note When calling app_timer_start() or app_timer_stop(), the timer operation is just queued,
+ * and the software interrupt is triggered. The actual timer start/stop operation is
+ * executed by the SWI0 interrupt handler. Since the SWI0 interrupt is running in APP_LOW,
+ * if the application code calling the timer function is running in APP_LOW or APP_HIGH,
+ * the timer operation will not be performed until the application handler has returned.
+ * This will be the case e.g. when stopping a timer from a timeout handler when not using
+ * the scheduler.
+ *
+ * @details Use the USE_SCHEDULER parameter of the APP_TIMER_INIT() macro to select if the
+ * @ref app_scheduler is to be used or not.
+ *
+ * @note Even if the scheduler is not used, app_timer.h will include app_scheduler.h, so when
+ * compiling, app_scheduler.h must be available in one of the compiler include paths.
+ */
+
+#ifndef APP_TIMER_H__
+#define APP_TIMER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include "app_error.h"
+#include "app_util.h"
+#include "app_scheduler.h"
+#include "compiler_abstraction.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif // #ifdef __cplusplus
+
+#define APP_TIMER_SCHED_EVT_SIZE sizeof(app_timer_event_t) /**< Size of button events being passed through the scheduler (is to be used for computing the maximum size of scheduler events). */
+#define APP_TIMER_CLOCK_FREQ 32768 /**< Clock frequency of the RTC timer used to implement the app timer module. */
+#define APP_TIMER_MIN_TIMEOUT_TICKS 5 /**< Minimum value of the timeout_ticks parameter of app_timer_start(). */
+
+#define APP_TIMER_NODE_SIZE 40 /**< Size of app_timer.timer_node_t (only for use inside APP_TIMER_BUF_SIZE()). */
+#define APP_TIMER_USER_OP_SIZE 24 /**< Size of app_timer.timer_user_op_t (only for use inside APP_TIMER_BUF_SIZE()). */
+#define APP_TIMER_USER_SIZE 8 /**< Size of app_timer.timer_user_t (only for use inside APP_TIMER_BUF_SIZE()). */
+#define APP_TIMER_INT_LEVELS 3 /**< Number of interrupt levels from where timer operations may be initiated (only for use inside APP_TIMER_BUF_SIZE()). */
+
+#define MAX_RTC_COUNTER_VAL 0x00FFFFFF /**< Maximum value of the RTC counter. */
+
+/**@brief Compute number of bytes required to hold the application timer data structures.
+ *
+ * @param[in] MAX_TIMERS Maximum number of timers that can be created at any given time.
+ * @param[in] OP_QUEUE_SIZE Size of queues holding timer operations that are pending execution.
+ * NOTE: Due to the queue implementation, this size must be one more
+ * than the size that is actually needed.
+ *
+ * @return Required application timer buffer size (in bytes).
+ */
+#define APP_TIMER_BUF_SIZE(MAX_TIMERS, OP_QUEUE_SIZE) \
+ ( \
+ ((MAX_TIMERS) * APP_TIMER_NODE_SIZE) \
+ + \
+ ( \
+ APP_TIMER_INT_LEVELS \
+ * \
+ (APP_TIMER_USER_SIZE + ((OP_QUEUE_SIZE) + 1) * APP_TIMER_USER_OP_SIZE) \
+ ) \
+ )
+
+/**@brief Convert milliseconds to timer ticks.
+ *
+ * @note This macro uses 64 bit integer arithmetic, but as long as the macro parameters are
+ * constants (i.e. defines), the computation will be done by the preprocessor.
+ *
+ * @param[in] MS Milliseconds.
+ * @param[in] PRESCALER Value of the RTC1 PRESCALER register (must be the same value that was
+ * passed to APP_TIMER_INIT()).
+ *
+ * @note When using this macro, it is the responsibility of the developer to ensure that the
+ * values provided as input result in an output value that is supported by the
+ * @ref app_timer_start function. For example, when the ticks for 1 ms is needed, the
+ * maximum possible value of PRESCALER must be 6, when @ref APP_TIMER_CLOCK_FREQ is 32768.
+ * This will result in a ticks value as 5. Any higher value for PRESCALER will result in a
+ * ticks value that is not supported by this module.
+ *
+ * @return Number of timer ticks.
+ */
+#define APP_TIMER_TICKS(MS, PRESCALER)\
+ ((uint32_t)ROUNDED_DIV((MS) * (uint64_t)APP_TIMER_CLOCK_FREQ, ((PRESCALER) + 1) * 1000))
+
+/**@brief Timer id type. */
+typedef uint32_t app_timer_id_t;
+
+#define TIMER_NULL ((app_timer_id_t)(0 - 1)) /**< Invalid timer id. */
+
+/**@brief Application timeout handler type. */
+typedef void (*app_timer_timeout_handler_t)(void * p_context);
+
+/**@brief Type of function for passing events from the timer module to the scheduler. */
+typedef uint32_t (*app_timer_evt_schedule_func_t) (app_timer_timeout_handler_t timeout_handler,
+ void * p_context);
+
+/**@brief Timer modes. */
+typedef enum
+{
+ APP_TIMER_MODE_SINGLE_SHOT, /**< The timer will expire only once. */
+ APP_TIMER_MODE_REPEATED /**< The timer will restart each time it expires. */
+} app_timer_mode_t;
+
+/**@brief Macro for initializing the application timer module.
+ *
+ * @details It will handle dimensioning and allocation of the memory buffer required by the timer,
+ * making sure that the buffer is correctly aligned. It will also connect the timer module
+ * to the scheduler (if specified).
+ *
+ * @note This module assumes that the LFCLK is already running. If it isn't, the module will
+ * be non-functional, since the RTC will not run. If you don't use a softdevice, you'll
+ * have to start the LFCLK manually. See the rtc_example's \ref lfclk_config() function
+ * for an example of how to do this. If you use a softdevice, the LFCLK is started on
+ * softdevice init.
+ *
+ *
+ * @param[in] PRESCALER Value of the RTC1 PRESCALER register. This will decide the
+ * timer tick rate. Set to 0 for no prescaling.
+ * @param[in] MAX_TIMERS Maximum number of timers that can be created at any given time.
+ * @param[in] OP_QUEUES_SIZE Size of queues holding timer operations that are pending execution.
+ * @param[in] USE_SCHEDULER TRUE if the application is using the event scheduler,
+ * FALSE otherwise.
+ *
+ * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it
+ * several times as long as it is from the same location, e.g. to do a reinitialization).
+ */
+/*lint -emacro(506, APP_TIMER_INIT) */ /* Suppress "Constant value Boolean */
+#define APP_TIMER_INIT(PRESCALER, MAX_TIMERS, OP_QUEUES_SIZE, USE_SCHEDULER) \
+ do \
+ { \
+ static uint32_t APP_TIMER_BUF[CEIL_DIV(APP_TIMER_BUF_SIZE((MAX_TIMERS), \
+ (OP_QUEUES_SIZE) + 1), \
+ sizeof(uint32_t))]; \
+ uint32_t ERR_CODE = app_timer_init((PRESCALER), \
+ (MAX_TIMERS), \
+ (OP_QUEUES_SIZE) + 1, \
+ APP_TIMER_BUF, \
+ (USE_SCHEDULER) ? app_timer_evt_schedule : NULL); \
+ APP_ERROR_CHECK(ERR_CODE); \
+ } while (0)
+
+/**@brief Function for initializing the timer module.
+ *
+ * @note Normally initialization should be done using the APP_TIMER_INIT() macro, as that will both
+ * allocate the buffers needed by the timer module (including aligning the buffers correctly,
+ * and also take care of connecting the timer module to the scheduler (if specified).
+ *
+ * @param[in] prescaler Value of the RTC1 PRESCALER register. Set to 0 for no prescaling.
+ * @param[in] max_timers Maximum number of timers that can be created at any given time.
+ * @param[in] op_queues_size Size of queues holding timer operations that are pending
+ * execution. NOTE: Due to the queue implementation, this size must
+ * be one more than the size that is actually needed.
+ * @param[in] p_buffer Pointer to memory buffer for internal use in the app_timer
+ * module. The size of the buffer can be computed using the
+ * APP_TIMER_BUF_SIZE() macro. The buffer must be aligned to a
+ * 4 byte boundary.
+ * @param[in] evt_schedule_func Function for passing timeout events to the scheduler. Point to
+ * app_timer_evt_schedule() to connect to the scheduler. Set to NULL
+ * to make the timer module call the timeout handler directly from
+ * the timer interrupt handler.
+ *
+ * @retval NRF_SUCCESS Successful initialization.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte
+ * boundary or NULL).
+ */
+uint32_t app_timer_init(uint32_t prescaler,
+ uint8_t max_timers,
+ uint8_t op_queues_size,
+ void * p_buffer,
+ app_timer_evt_schedule_func_t evt_schedule_func);
+
+/**@brief Function for creating a timer instance.
+ *
+ * @param[out] p_timer_id Id of the newly created timer.
+ * @param[in] mode Timer mode.
+ * @param[in] timeout_handler Function to be executed when the timer expires.
+ *
+ * @retval NRF_SUCCESS Timer was successfully created.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter.
+ * @retval NRF_ERROR_INVALID_STATE Application timer module has not been initialized.
+ * @retval NRF_ERROR_NO_MEM Maximum number of timers has already been reached.
+ *
+ * @note This function does the timer allocation in the caller's context. It is also not protected
+ * by a critical region. Therefore care must be taken not to call it from several interrupt
+ * levels simultaneously.
+ */
+uint32_t app_timer_create(app_timer_id_t * p_timer_id,
+ app_timer_mode_t mode,
+ app_timer_timeout_handler_t timeout_handler);
+
+/**@brief Function for starting a timer.
+ *
+ * @param[in] timer_id Id of timer to start.
+ * @param[in] timeout_ticks Number of ticks (of RTC1, including prescaling) to timeout event
+ * (minimum 5 ticks).
+ * @param[in] p_context General purpose pointer. Will be passed to the timeout handler when
+ * the timer expires.
+ *
+ * @retval NRF_SUCCESS Timer was successfully started.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter.
+ * @retval NRF_ERROR_INVALID_STATE Application timer module has not been initialized, or timer
+ * has not been created.
+ * @retval NRF_ERROR_NO_MEM Timer operations queue was full.
+ *
+ * @note The minimum timeout_ticks value is 5.
+ * @note For multiple active timers, timeouts occurring in close proximity to each other (in the
+ * range of 1 to 3 ticks) will have a positive jitter of maximum 3 ticks.
+ * @note When calling this method on a timer which is already running, the second start operation
+ * will be ignored.
+ */
+uint32_t app_timer_start(app_timer_id_t timer_id, uint32_t timeout_ticks, void * p_context);
+
+/**@brief Function for stopping the specified timer.
+ *
+ * @param[in] timer_id Id of timer to stop.
+ *
+ * @retval NRF_SUCCESS Timer was successfully stopped.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter.
+ * @retval NRF_ERROR_INVALID_STATE Application timer module has not been initialized, or timer
+ * has not been created.
+ * @retval NRF_ERROR_NO_MEM Timer operations queue was full.
+ */
+uint32_t app_timer_stop(app_timer_id_t timer_id);
+
+/**@brief Function for stopping all running timers.
+ *
+ * @retval NRF_SUCCESS All timers were successfully stopped.
+ * @retval NRF_ERROR_INVALID_STATE Application timer module has not been initialized.
+ * @retval NRF_ERROR_NO_MEM Timer operations queue was full.
+ */
+uint32_t app_timer_stop_all(void);
+
+/**@brief Function for returning the current value of the RTC1 counter. The
+ * value includes overflow bits to extend the range to 64-bits.
+ *
+ * @param[out] p_ticks Current value of the RTC1 counter.
+ *
+ * @retval NRF_SUCCESS Counter was successfully read.
+ */
+uint32_t app_timer_cnt_get(uint64_t * p_ticks);
+
+/**@brief Function for computing the difference between two RTC1 counter values.
+ *
+ * @param[in] ticks_to Value returned by app_timer_cnt_get().
+ * @param[in] ticks_from Value returned by app_timer_cnt_get().
+ * @param[out] p_ticks_diff Number of ticks from ticks_from to ticks_to.
+ *
+ * @retval NRF_SUCCESS Counter difference was successfully computed.
+ */
+uint32_t app_timer_cnt_diff_compute(uint32_t ticks_to,
+ uint32_t ticks_from,
+ uint32_t * p_ticks_diff);
+
+
+// Type and functions for connecting the timer to the scheduler:
+
+/**@cond NO_DOXYGEN */
+typedef struct
+{
+ app_timer_timeout_handler_t timeout_handler;
+ void * p_context;
+} app_timer_event_t;
+
+static __INLINE void app_timer_evt_get(void * p_event_data, uint16_t event_size)
+{
+ app_timer_event_t * p_timer_event = (app_timer_event_t *)p_event_data;
+
+ APP_ERROR_CHECK_BOOL(event_size == sizeof(app_timer_event_t));
+ p_timer_event->timeout_handler(p_timer_event->p_context);
+}
+
+static __INLINE uint32_t app_timer_evt_schedule(app_timer_timeout_handler_t timeout_handler,
+ void * p_context)
+{
+ app_timer_event_t timer_event;
+
+ timer_event.timeout_handler = timeout_handler;
+ timer_event.p_context = p_context;
+
+ return app_sched_event_put(&timer_event, sizeof(timer_event), app_timer_evt_get);
+}
+/**@endcond */
+
+#ifdef __cplusplus
+}
+#endif // #ifdef __cplusplus
+
+#endif // APP_TIMER_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_trace.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,55 @@
+#ifndef __DEBUG_H_
+#define __DEBUG_H_
+
+#include <stdint.h>
+#include <stdio.h>
+
+/**
+ * @defgroup app_trace Debug Logger
+ * @ingroup app_common
+ * @{
+ * @brief Enables debug logs/ trace over UART.
+ * @details Enables debug logs/ trace over UART. Tracing is enabled only if
+ * ENABLE_DEBUG_LOG_SUPPORT is defined in the project.
+ */
+#ifdef ENABLE_DEBUG_LOG_SUPPORT
+/**
+ * @brief Module Initialization.
+ *
+ * @details Initializes the module to use UART as trace output.
+ *
+ * @warning This function will configure UART using default board configuration (described in @ref nrf51_setups).
+ * Do not call this function if UART is configured from a higher level in the application.
+ */
+void app_trace_init(void);
+
+/**
+ * @brief Log debug messages.
+ *
+ * @details This API logs messages over UART. The module must be initialized before using this API.
+ *
+ * @note Though this is currently a macro, it should be used used and treated as function.
+ */
+#define app_trace_log printf
+
+/**
+ * @brief Dump auxiliary byte buffer to the debug trace.
+ *
+ * @details This API logs messages over UART. The module must be initialized before using this API.
+ *
+ * @param[in] p_buffer Buffer to be dumped on the debug trace.
+ * @param[in] len Size of the buffer.
+ */
+void app_trace_dump(uint8_t * p_buffer, uint32_t len);
+
+#else // ENABLE_DEBUG_LOG_SUPPORT
+
+#define app_trace_init(...)
+#define app_trace_log(...)
+#define app_trace_dump(...)
+
+#endif // ENABLE_DEBUG_LOG_SUPPORT
+
+/** @} */
+
+#endif //__DEBUG_H_
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_uart.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,286 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/**@file
+ *
+ * @defgroup app_uart UART module
+ * @{
+ * @ingroup app_common
+ *
+ * @brief UART module interface.
+ */
+
+#ifndef APP_UART_H__
+#define APP_UART_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "app_util_platform.h"
+
+#define UART_PIN_DISCONNECTED 0xFFFFFFFF /**< Value indicating that no pin is connected to this UART register. */
+
+/**@brief UART Flow Control modes for the peripheral.
+ */
+typedef enum
+{
+ APP_UART_FLOW_CONTROL_DISABLED, /**< UART Hw Flow Control is disabled. */
+ APP_UART_FLOW_CONTROL_ENABLED, /**< Standard UART Hw Flow Control is enabled. */
+ APP_UART_FLOW_CONTROL_LOW_POWER /**< Specialized UART Hw Flow Control is used. The Low Power setting allows the nRF51 to Power Off the UART module when CTS is in-active, and re-enabling the UART when the CTS signal becomes active. This allows the nRF51 to safe power by only using the UART module when it is needed by the remote site. */
+} app_uart_flow_control_t;
+
+/**@brief UART communication structure holding configuration settings for the peripheral.
+ */
+typedef struct
+{
+ uint8_t rx_pin_no; /**< RX pin number. */
+ uint8_t tx_pin_no; /**< TX pin number. */
+ uint8_t rts_pin_no; /**< RTS pin number, only used if flow control is enabled. */
+ uint8_t cts_pin_no; /**< CTS pin number, only used if flow control is enabled. */
+ app_uart_flow_control_t flow_control; /**< Flow control setting, if flow control is used, the system will use low power UART mode, based on CTS signal. */
+ bool use_parity; /**< Even parity if TRUE, no parity if FALSE. */
+ uint32_t baud_rate; /**< Baud rate configuration. */
+} app_uart_comm_params_t;
+
+/**@brief UART buffer for transmitting/receiving data.
+ */
+typedef struct
+{
+ uint8_t * rx_buf; /**< Pointer to the RX buffer. */
+ uint32_t rx_buf_size; /**< Size of the RX buffer. */
+ uint8_t * tx_buf; /**< Pointer to the TX buffer. */
+ uint32_t tx_buf_size; /**< Size of the TX buffer. */
+} app_uart_buffers_t;
+
+/**@brief Enumeration describing current state of the UART.
+ *
+ * @details The connection state can be fetched by the application using the function call
+ * @ref app_uart_get_connection_state.
+ * When hardware flow control is used
+ * - APP_UART_CONNECTED: Communication is ongoing.
+ * - APP_UART_DISCONNECTED: No communication is ongoing.
+ *
+ * When no hardware flow control is used
+ * - APP_UART_CONNECTED: Always returned as bytes can always be received/transmitted.
+ */
+typedef enum
+{
+ APP_UART_DISCONNECTED, /**< State indicating that the UART is disconnected and cannot receive or transmit bytes. */
+ APP_UART_CONNECTED /**< State indicating that the UART is connected and ready to receive or transmit bytes. If flow control is disabled, the state will always be connected. */
+} app_uart_connection_state_t;
+
+/**@brief Enumeration which defines events used by the UART module upon data reception or error.
+ *
+ * @details The event type is used to indicate the type of additional information in the event
+ * @ref app_uart_evt_t.
+ */
+typedef enum
+{
+ APP_UART_DATA_READY, /**< An event indicating that UART data has been received. The data is available in the FIFO and can be fetched using @ref app_uart_get. */
+ APP_UART_FIFO_ERROR, /**< An error in the FIFO module used by the app_uart module has occured. The FIFO error code is stored in app_uart_evt_t.data.error_code field. */
+ APP_UART_COMMUNICATION_ERROR, /**< An communication error has occured during reception. The error is stored in app_uart_evt_t.data.error_communication field. */
+ APP_UART_TX_EMPTY, /**< An event indicating that UART has completed transmission of all available data in the TX FIFO. */
+ APP_UART_DATA, /**< An event indicating that UART data has been received, and data is present in data field. This event is only used when no FIFO is configured. */
+} app_uart_evt_type_t;
+
+/**@brief Struct containing events from the UART module.
+ *
+ * @details The app_uart_evt_t is used to notify the application of asynchronous events when data
+ * are received on the UART peripheral or in case an error occured during data reception.
+ */
+typedef struct
+{
+ app_uart_evt_type_t evt_type; /**< Type of event. */
+ union
+ {
+ uint32_t error_communication; /**< Field used if evt_type is: APP_UART_COMMUNICATION_ERROR. This field contains the value in the ERRORSRC register for the UART peripheral. The UART_ERRORSRC_x defines from @ref nrf51_bitfields.h can be used to parse the error code. See also the nRF51 Series Reference Manual for specification. */
+ uint32_t error_code; /**< Field used if evt_type is: NRF_ERROR_x. Additional status/error code if the error event type is APP_UART_FIFO_ERROR. This error code refer to errors defined in nrf_error.h. */
+ uint8_t value; /**< Field used if evt_type is: NRF_ERROR_x. Additional status/error code if the error event type is APP_UART_FIFO_ERROR. This error code refer to errors defined in nrf_error.h. */
+ } data;
+} app_uart_evt_t;
+
+/**@brief Function for handling app_uart event callback.
+ *
+ * @details Upon an event in the app_uart module this callback function will be called to notify
+ * the applicatioon about the event.
+ *
+ * @param[in] p_app_uart_event Pointer to UART event.
+ */
+
+
+typedef void (* app_uart_event_handler_t) (app_uart_evt_t * p_app_uart_event);
+
+/**@brief Macro for safe initialization of the UART module in a single user instance when using
+ * a FIFO together with UART.
+ *
+ * @param[in] P_COMM_PARAMS Pointer to a UART communication structure: app_uart_comm_params_t
+ * @param[in] RX_BUF_SIZE Size of desired RX buffer, must be a power of 2 or ZERO (No FIFO).
+ * @param[in] TX_BUF_SIZE Size of desired TX buffer, must be a power of 2 or ZERO (No FIFO).
+ * @param[in] EVENT_HANDLER Event handler function to be called when an event occurs in the
+ * UART module.
+ * @param[in] IRQ_PRIO IRQ priority, app_irq_priority_t, for the UART module irq handler.
+ * @param[out] ERR_CODE The return value of the UART initialization function will be
+ * written to this parameter.
+ *
+ * @note Since this macro allocates a buffer and registers the module as a GPIOTE user when flow
+ * control is enabled, it must only be called once.
+ */
+#define APP_UART_FIFO_INIT(P_COMM_PARAMS, RX_BUF_SIZE, TX_BUF_SIZE, EVT_HANDLER, IRQ_PRIO, ERR_CODE) \
+ do \
+ { \
+ uint16_t APP_UART_UID = 0; \
+ app_uart_buffers_t buffers; \
+ static uint8_t rx_buf[RX_BUF_SIZE]; \
+ static uint8_t tx_buf[TX_BUF_SIZE]; \
+ \
+ buffers.rx_buf = rx_buf; \
+ buffers.rx_buf_size = sizeof (rx_buf); \
+ buffers.tx_buf = tx_buf; \
+ buffers.tx_buf_size = sizeof (tx_buf); \
+ ERR_CODE = app_uart_init(P_COMM_PARAMS, &buffers, EVT_HANDLER, IRQ_PRIO, &APP_UART_UID); \
+ } while (0)
+
+/**@brief Macro for safe initialization of the UART module in a single user instance.
+ *
+ * @param[in] P_COMM_PARAMS Pointer to a UART communication structure: app_uart_comm_params_t
+ * @param[in] EVENT_HANDLER Event handler function to be called when an event occurs in the
+ * UART module.
+ * @param[in] IRQ_PRIO IRQ priority, app_irq_priority_t, for the UART module irq handler.
+ * @param[out] ERR_CODE The return value of the UART initialization function will be
+ * written to this parameter.
+ *
+ * @note Since this macro allocates registers the module as a GPIOTE user when flow control is
+ * enabled, it must only be called once.
+ */
+#define APP_UART_INIT(P_COMM_PARAMS, EVT_HANDLER, IRQ_PRIO, ERR_CODE) \
+ do \
+ { \
+ uint16_t APP_UART_UID = 0; \
+ ERR_CODE = app_uart_init(P_COMM_PARAMS, NULL, EVT_HANDLER, IRQ_PRIO, &APP_UART_UID); \
+ } while (0)
+
+/**@brief Function for initializing the UART module. Use this initialization when several instances of the UART
+ * module are needed.
+ *
+ * @details This initialization will return a UART user id for the caller. The UART user id must be
+ * used upon re-initialization of the UART or closing of the module for the user.
+ * If single instance usage is needed, the APP_UART_INIT() macro should be used instead.
+ *
+ * @note Normally single instance initialization should be done using the APP_UART_INIT() or
+ * APP_UART_INIT_FIFO() macro depending on whether the FIFO should be used by the UART, as
+ * that will allocate the buffers needed by the UART module (including aligning the buffer
+ * correctly).
+
+ * @param[in] p_comm_params Pin and communication parameters.
+ * @param[in] p_buffers RX and TX buffers, NULL is FIFO is not used.
+ * @param[in] error_handler Function to be called in case of an error.
+ * @param[in] app_irq_priority Interrupt priority level.
+ * @param[in,out] p_uart_uid User id for the UART module. The p_uart_uid must be used if
+ * re-initialization and/or closing of the UART module is needed.
+ * If the value pointed to by p_uart_uid is zero, this is
+ * considdered a first time initialization. Otherwise this is
+ * considered a re-initialization for the user with id *p_uart_uid.
+ *
+ * @retval NRF_SUCCESS If successful initialization.
+ * @retval NRF_ERROR_INVALID_LENGTH If a provided buffer is not a power of two.
+ * @retval NRF_ERROR_NULL If one of the provided buffers is a NULL pointer.
+ *
+ * Those errors are propagated by the UART module to the caller upon registration when Hardware Flow
+ * Control is enabled. When Hardware Flow Control is not used, those errors cannot occur.
+ * @retval NRF_ERROR_INVALID_STATE The GPIOTE module is not in a valid state when registering
+ * the UART module as a user.
+ * @retval NRF_ERROR_INVALID_PARAM The UART module provides an invalid callback function when
+ * registering the UART module as a user.
+ * Or the value pointed to by *p_uart_uid is not a valid
+ * GPIOTE number.
+ * @retval NRF_ERROR_NO_MEM GPIOTE module has reached the maximum number of users.
+ */
+uint32_t app_uart_init(const app_uart_comm_params_t * p_comm_params,
+ app_uart_buffers_t * p_buffers,
+ app_uart_event_handler_t error_handler,
+ app_irq_priority_t irq_priority,
+ uint16_t * p_uart_uid);
+
+/**@brief Function for getting a byte from the UART.
+ *
+ * @details This function will get the next byte from the RX buffer. If the RX buffer is empty
+ * an error code will be returned and the app_uart module will generate an event upon
+ * reception of the first byte which is added to the RX buffer.
+ *
+ * @param[out] p_byte Pointer to an address where next byte received on the UART will be copied.
+ *
+ * @retval NRF_SUCCESS If a byte has been received and pushed to the pointer provided.
+ * @retval NRF_ERROR_NOT_FOUND If no byte is available in the RX buffer of the app_uart module.
+ */
+uint32_t app_uart_get(uint8_t * p_byte);
+
+/**@brief Function for putting a byte on the UART.
+ *
+ * @details This call is non-blocking.
+ *
+ * @param[in] byte Byte to be transmitted on the UART.
+ *
+ * @retval NRF_SUCCESS If the byte was succesfully put on the TX buffer for transmission.
+ * @retval NRF_ERROR_NO_MEM If no more space is available in the TX buffer.
+ * NRF_ERROR_NO_MEM may occur if flow control is enabled and CTS signal
+ * is high for a long period and the buffer fills up.
+ */
+uint32_t app_uart_put(uint8_t byte);
+
+/**@brief Function for getting the current state of the UART.
+ *
+ * @details If flow control is disabled, the state is assumed to always be APP_UART_CONNECTED.
+ *
+ * When using flow control the state will be controlled by the CTS. If CTS is set active
+ * by the remote side, or the app_uart module is in the process of transmitting a byte,
+ * app_uart is in APP_UART_CONNECTED state. If CTS is set inactive by remote side app_uart
+ * will not get into APP_UART_DISCONNECTED state until the last byte in the TXD register
+ * is fully transmitted.
+ *
+ * Internal states in the state machine are mapped to the general connected/disconnected
+ * states in the following ways:
+ *
+ * - UART_ON = CONNECTED
+ * - UART_READY = CONNECTED
+ * - UART_WAIT = CONNECTED
+ * - UART_OFF = DISCONNECTED.
+ *
+ * @param[out] p_connection_state Current connection state of the UART.
+ *
+ * @retval NRF_SUCCESS The connection state was succesfully retrieved.
+ */
+uint32_t app_uart_get_connection_state(app_uart_connection_state_t * p_connection_state);
+
+/**@brief Function for flushing the RX and TX buffers (Only valid if FIFO is used).
+ * This function does nothing if FIFO is not used.
+ *
+ * @retval NRF_SUCCESS Flushing completed (Current implementation will always succeed).
+ */
+uint32_t app_uart_flush(void);
+
+/**@brief Function for closing the UART module.
+ *
+ * @details This function will close any on-going UART transmissions and disable itself in the
+ * GPTIO module.
+ *
+ * @param[in] app_uart_uid User id for the UART module. The app_uart_uid must be identical to the
+ * UART id returned on initialization and which is currently in use.
+
+ * @retval NRF_SUCCESS If successfully closed.
+ * @retval NRF_ERROR_INVALID_PARAM If an invalid user id is provided or the user id differs from
+ * the current active user.
+ */
+uint32_t app_uart_close(uint16_t app_uart_id);
+
+
+#endif //APP_UART_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_util.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,232 @@
+/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup app_util Utility Functions and Definitions
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Various types and definitions available to all applications.
+ */
+
+#ifndef APP_UTIL_H__
+#define APP_UTIL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "compiler_abstraction.h"
+
+enum
+{
+ UNIT_0_625_MS = 625, /**< Number of microseconds in 0.625 milliseconds. */
+ UNIT_1_25_MS = 1250, /**< Number of microseconds in 1.25 milliseconds. */
+ UNIT_10_MS = 10000 /**< Number of microseconds in 10 milliseconds. */
+};
+
+/**@brief Macro for doing static (i.e. compile time) assertion.
+ *
+ * @note If the assertion fails when compiling using Keil, the compiler will report error message
+ * "error: #94: the size of an array must be greater than zero" (while gcc will list the
+ * symbol static_assert_failed, making the error message more readable).
+ * If the supplied expression can not be evaluated at compile time, Keil will report
+ * "error: #28: expression must have a constant value".
+ *
+ * @note The macro is intentionally implemented not using do while(0), allowing it to be used
+ * outside function blocks (e.g. close to global type- and variable declarations).
+ * If used in a code block, it must be used before any executable code in this block.
+ *
+ * @param[in] EXPR Constant expression to be verified.
+ */
+
+#if defined(__GNUC__)
+#define STATIC_ASSERT(EXPR) typedef char __attribute__((unused)) static_assert_failed[(EXPR) ? 1 : -1]
+#else
+#define STATIC_ASSERT(EXPR) typedef char static_assert_failed[(EXPR) ? 1 : -1]
+#endif
+
+
+/**@brief type for holding an encoded (i.e. little endian) 16 bit unsigned integer. */
+typedef uint8_t uint16_le_t[2];
+
+/**@brief type for holding an encoded (i.e. little endian) 32 bit unsigned integer. */
+typedef uint8_t uint32_le_t[4];
+
+/**@brief Byte array type. */
+typedef struct
+{
+ uint16_t size; /**< Number of array entries. */
+ uint8_t * p_data; /**< Pointer to array entries. */
+} uint8_array_t;
+
+/**@brief Perform rounded integer division (as opposed to truncating the result).
+ *
+ * @param[in] A Numerator.
+ * @param[in] B Denominator.
+ *
+ * @return Rounded (integer) result of dividing A by B.
+ */
+#define ROUNDED_DIV(A, B) (((A) + ((B) / 2)) / (B))
+
+/**@brief Check if the integer provided is a power of two.
+ *
+ * @param[in] A Number to be tested.
+ *
+ * @return true if value is power of two.
+ * @return false if value not power of two.
+ */
+#define IS_POWER_OF_TWO(A) ( ((A) != 0) && ((((A) - 1) & (A)) == 0) )
+
+/**@brief To convert ticks to millisecond
+ * @param[in] time Number of millseconds that needs to be converted.
+ * @param[in] resolution Units to be converted.
+ */
+#define MSEC_TO_UNITS(TIME, RESOLUTION) (((TIME) * 1000) / (RESOLUTION))
+
+
+/**@brief Perform integer division, making sure the result is rounded up.
+ *
+ * @details One typical use for this is to compute the number of objects with size B is needed to
+ * hold A number of bytes.
+ *
+ * @param[in] A Numerator.
+ * @param[in] B Denominator.
+ *
+ * @return Integer result of dividing A by B, rounded up.
+ */
+#define CEIL_DIV(A, B) \
+ /*lint -save -e573 */ \
+ ((((A) - 1) / (B)) + 1) \
+ /*lint -restore */
+
+/**@brief Function for encoding a uint16 value.
+ *
+ * @param[in] value Value to be encoded.
+ * @param[out] p_encoded_data Buffer where the encoded data is to be written.
+ *
+ * @return Number of bytes written.
+ */
+static __INLINE uint8_t uint16_encode(uint16_t value, uint8_t * p_encoded_data)
+{
+ p_encoded_data[0] = (uint8_t) ((value & 0x00FF) >> 0);
+ p_encoded_data[1] = (uint8_t) ((value & 0xFF00) >> 8);
+ return sizeof(uint16_t);
+}
+
+/**@brief Function for encoding a uint32 value.
+ *
+ * @param[in] value Value to be encoded.
+ * @param[out] p_encoded_data Buffer where the encoded data is to be written.
+ *
+ * @return Number of bytes written.
+ */
+static __INLINE uint8_t uint32_encode(uint32_t value, uint8_t * p_encoded_data)
+{
+ p_encoded_data[0] = (uint8_t) ((value & 0x000000FF) >> 0);
+ p_encoded_data[1] = (uint8_t) ((value & 0x0000FF00) >> 8);
+ p_encoded_data[2] = (uint8_t) ((value & 0x00FF0000) >> 16);
+ p_encoded_data[3] = (uint8_t) ((value & 0xFF000000) >> 24);
+ return sizeof(uint32_t);
+}
+
+/**@brief Function for decoding a uint16 value.
+ *
+ * @param[in] p_encoded_data Buffer where the encoded data is stored.
+ *
+ * @return Decoded value.
+ */
+static __INLINE uint16_t uint16_decode(const uint8_t * p_encoded_data)
+{
+ return ( (((uint16_t)((uint8_t *)p_encoded_data)[0])) |
+ (((uint16_t)((uint8_t *)p_encoded_data)[1]) << 8 ));
+}
+
+/**@brief Function for decoding a uint32 value.
+ *
+ * @param[in] p_encoded_data Buffer where the encoded data is stored.
+ *
+ * @return Decoded value.
+ */
+static __INLINE uint32_t uint32_decode(const uint8_t * p_encoded_data)
+{
+ return ( (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0) |
+ (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8) |
+ (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16) |
+ (((uint32_t)((uint8_t *)p_encoded_data)[3]) << 24 ));
+}
+
+/** @brief Function for converting the input voltage (in milli volts) into percentage of 3.0 Volts.
+ *
+ * @details The calculation is based on a linearized version of the battery's discharge
+ * curve. 3.0V returns 100% battery level. The limit for power failure is 2.1V and
+ * is considered to be the lower boundary.
+ *
+ * The discharge curve for CR2032 is non-linear. In this model it is split into
+ * 4 linear sections:
+ * - Section 1: 3.0V - 2.9V = 100% - 42% (58% drop on 100 mV)
+ * - Section 2: 2.9V - 2.74V = 42% - 18% (24% drop on 160 mV)
+ * - Section 3: 2.74V - 2.44V = 18% - 6% (12% drop on 300 mV)
+ * - Section 4: 2.44V - 2.1V = 6% - 0% (6% drop on 340 mV)
+ *
+ * These numbers are by no means accurate. Temperature and
+ * load in the actual application is not accounted for!
+ *
+ * @param[in] mvolts The voltage in mV
+ *
+ * @return Battery level in percent.
+*/
+static __INLINE uint8_t battery_level_in_percent(const uint16_t mvolts)
+{
+ uint8_t battery_level;
+
+ if (mvolts >= 3000)
+ {
+ battery_level = 100;
+ }
+ else if (mvolts > 2900)
+ {
+ battery_level = 100 - ((3000 - mvolts) * 58) / 100;
+ }
+ else if (mvolts > 2740)
+ {
+ battery_level = 42 - ((2900 - mvolts) * 24) / 160;
+ }
+ else if (mvolts > 2440)
+ {
+ battery_level = 18 - ((2740 - mvolts) * 12) / 300;
+ }
+ else if (mvolts > 2100)
+ {
+ battery_level = 6 - ((2440 - mvolts) * 6) / 340;
+ }
+ else
+ {
+ battery_level = 0;
+ }
+
+ return battery_level;
+}
+
+/**@brief Function for checking if a pointer value is aligned to a 4 byte boundary.
+ *
+ * @param[in] p Pointer value to be checked.
+ *
+ * @return TRUE if pointer is aligned to a 4 byte boundary, FALSE otherwise.
+ */
+static __INLINE bool is_word_aligned(void * p)
+{
+ return (((uintptr_t)p & 0x03) == 0);
+}
+
+#endif // APP_UTIL_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/crc16.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,52 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup crc_compute CRC compute
+ * @{
+ * @ingroup hci_transport
+ *
+ * @brief This module implements the CRC-16 calculation in the blocks.
+ */
+
+#ifndef CRC16_H__
+#define CRC16_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@brief Function for calculating CRC-16 in blocks.
+ *
+ * Feed each consecutive data block into this function, along with the current value of p_crc as
+ * returned by the previous call of this function. The first call of this function should pass NULL
+ * as the initial value of the crc in p_crc.
+ *
+ * @param[in] p_data The input data block for computation.
+ * @param[in] size The size of the input data block in bytes.
+ * @param[in] p_crc The previous calculated CRC-16 value or NULL if first call.
+ *
+ * @return The updated CRC-16 value, based on the input supplied.
+ */
+uint16_t crc16_compute(const uint8_t * p_data, uint32_t size, const uint16_t * p_crc);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif // CRC16_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hal_transport.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,227 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/**@file
+ *
+ * @defgroup hci_transport HCI Transport
+ * @{
+ * @ingroup app_common
+ *
+ * @brief HCI transport module implementation.
+ *
+ * This module implements certain specific features from the three-wire UART transport layer,
+ * defined by the Bluetooth specification version 4.0 [Vol 4] part D.
+ *
+ * \par Features supported
+ * - Transmission and reception of Vendor Specific HCI packet type application packets.
+ * - Transmission and reception of reliable packets: defined by chapter 6 of the specification.
+ *
+ * \par Features not supported
+ * - Link establishment procedure: defined by chapter 8 of the specification.
+ * - Low power: defined by chapter 9 of the specification.
+ *
+ * \par Implementation specific behaviour
+ * - As Link establishment procedure is not supported following static link configuration parameters
+ * are used:
+ * + TX window size is 1.
+ * + 16 bit CCITT-CRC must be used.
+ * + Out of frame software flow control not supported.
+ * + Parameters specific for resending reliable packets are compile time configurable (clarifed
+ * later in this document).
+ * + Acknowledgement packet transmissions are not timeout driven , meaning they are delivered for
+ * transmission within same context which the corresponding application packet was received.
+ *
+ * \par Implementation specific limitations
+ * Current implementation has the following limitations which will have impact to system wide
+ * behaviour:
+ * - Delayed acknowledgement scheduling not implemented:
+ * There exists a possibility that acknowledgement TX packet and application TX packet will collide
+ * in the TX pipeline having the end result that acknowledgement packet will be excluded from the TX
+ * pipeline which will trigger the retransmission algorithm within the peer protocol entity.
+ * - Delayed retransmission scheduling not implemented:
+ * There exists a possibility that retransmitted application TX packet and acknowledgement TX packet
+ * will collide in the TX pipeline having the end result that retransmitted application TX packet
+ * will be excluded from the TX pipeline.
+ * - Processing of the acknowledgement number from RX application packets:
+ * Acknowledgement number is not processed from the RX application packets having the end result
+ * that unnecessary application packet retransmissions can occur.
+ *
+ * The application TX packet processing flow is illustrated by the statemachine below.
+ *
+ * @image html hci_transport_tx_sm.png "TX - application packet statemachine"
+ *
+ * \par Component specific configuration options
+ *
+ * The following compile time configuration options are available, and used to configure the
+ * application TX packet retransmission interval, in order to suite various application specific
+ * implementations:
+ * - MAC_PACKET_SIZE_IN_BITS Maximum size of a single application packet in bits.
+ * - USED_BAUD_RATE Used uart baudrate.
+ *
+ * The following compile time configuration option is available to configure module specific
+ * behaviour:
+ * - MAX_RETRY_COUNT Max retransmission retry count for applicaton packets.
+ */
+
+#ifndef HCI_TRANSPORT_H__
+#define HCI_TRANSPORT_H__
+
+#include <stdint.h>
+#include "nrf_error.h"
+
+#define HCI_TRANSPORT_PKT_HEADER_SIZE (2) /**< Size of transport packet header */
+
+/**@brief Generic event callback function events. */
+typedef enum
+{
+ HCI_TRANSPORT_RX_RDY, /**< An event indicating that RX packet is ready for read. */
+ HCI_TRANSPORT_EVT_TYPE_MAX /**< Enumeration upper bound. */
+} hci_transport_evt_type_t;
+
+/**@brief Struct containing events from the Transport layer.
+ */
+typedef struct
+{
+ hci_transport_evt_type_t evt_type; /**< Type of event. */
+} hci_transport_evt_t;
+
+/**@brief Transport layer generic event callback function type.
+ *
+ * @param[in] event Transport layer event.
+ */
+typedef void (*hci_transport_event_handler_t)(hci_transport_evt_t event);
+
+/**@brief TX done event callback function result codes. */
+typedef enum
+{
+ HCI_TRANSPORT_TX_DONE_SUCCESS, /**< Transmission success, peer transport entity has acknowledged the transmission. */
+ HCI_TRANSPORT_TX_DONE_FAILURE /**< Transmission failure. */
+} hci_transport_tx_done_result_t;
+
+/**@brief Transport layer TX done event callback function type.
+ *
+ * @param[in] result TX done event result code.
+ */
+typedef void (*hci_transport_tx_done_handler_t)(hci_transport_tx_done_result_t result);
+
+/**@brief Function for registering a generic event handler.
+ *
+ * @note Multiple registration requests will overwrite any possible existing registration.
+ *
+ * @param[in] event_handler The function to be called by the transport layer upon an event.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_evt_handler_reg(hci_transport_event_handler_t event_handler);
+
+/**@brief Function for registering a handler for TX done event.
+ *
+ * @note Multiple registration requests will overwrite any possible existing registration.
+ *
+ * @param[in] event_handler The function to be called by the transport layer upon TX done
+ * event.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_tx_done_register(hci_transport_tx_done_handler_t event_handler);
+
+/**@brief Function for opening the transport channel and initializing the transport layer.
+ *
+ * @warning Must not be called for a channel which has been allready opened.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_INTERNAL Operation failure. Internal error ocurred.
+ */
+uint32_t hci_transport_open(void);
+
+/**@brief Function for closing the transport channel.
+ *
+ * @note Can be called multiple times and also for not opened channel.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_transport_close(void);
+
+/**@brief Function for allocating tx packet memory.
+ *
+ * @param[out] pp_memory Pointer to the packet data.
+ *
+ * @retval NRF_SUCCESS Operation success. Memory was allocated.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No memory available.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_tx_alloc(uint8_t ** pp_memory);
+
+/**@brief Function for freeing tx packet memory.
+ *
+ * @note Memory management works in FIFO principle meaning that free order must match the alloc
+ * order.
+ *
+ * @retval NRF_SUCCESS Operation success. Memory was freed.
+ */
+uint32_t hci_transport_tx_free(void);
+
+/**@brief Function for writing a packet.
+ *
+ * @note Completion of this method does not guarantee that actual peripheral transmission would
+ * have completed.
+ *
+ * @note In case of 0 byte packet length write request, message will consist of only transport
+ * module specific headers.
+ *
+ * @note The buffer provided to this function must be allocated through @ref hci_transport_tx_alloc
+ * function.
+ *
+ * @retval NRF_SUCCESS Operation success. Packet was added to the transmission queue
+ * and an event will be send upon transmission completion.
+ * @retval NRF_ERROR_NO_MEM Operation failure. Transmission queue is full and packet was not
+ * added to the transmission queue. User should wait for
+ * a appropriate event prior issuing this operation again.
+ * @retval NRF_ERROR_DATA_SIZE Operation failure. Packet size exceeds limit.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ * @retval NRF_ERROR_INVALID_STATE Operation failure. Channel is not open.
+ * @retval NRF_ERROR_INVALID_ADDR Operation failure. Buffer provided is not allocated through
+ * hci_transport_tx_alloc function.
+ */
+uint32_t hci_transport_pkt_write(const uint8_t * p_buffer, uint16_t length);
+
+/**@brief Function for extracting received packet.
+ *
+ * @note Extracted memory can't be reused by the underlying transport layer untill freed by call to
+ * hci_transport_rx_pkt_consume().
+ *
+ * @param[out] pp_buffer Pointer to the packet data.
+ * @param[out] p_length Length of packet data in bytes.
+ *
+ * @retval NRF_SUCCESS Operation success. Packet was extracted.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to extract.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_rx_pkt_extract(uint8_t ** pp_buffer, uint16_t * p_length);
+
+/**@brief Function for consuming extracted packet described by p_buffer.
+ *
+ * RX memory pointed to by p_buffer is freed and can be reused by the underlying transport layer.
+ *
+ * @param[in] p_buffer Pointer to the buffer that has been consumed.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to consume.
+ * @retval NRF_ERROR_INVALID_ADDR Operation failure. Not a valid pointer.
+ */
+uint32_t hci_transport_rx_pkt_consume(uint8_t * p_buffer);
+
+#endif // HCI_TRANSPORT_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_mem_pool.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,132 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup memory_pool Memory pool
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Memory pool implementation
+ *
+ * Memory pool implementation, based on circular buffer data structure, which supports asynchronous
+ * processing of RX data. The current default implementation supports 1 TX buffer and 4 RX buffers.
+ * The memory managed by the pool is allocated from static storage instead of heap. The internal
+ * design of the circular buffer implementing the RX memory layout is illustrated in the picture
+ * below.
+ *
+ * @image html memory_pool.png "Circular buffer design"
+ *
+ * The expected call order for the RX APIs is as follows:
+ * - hci_mem_pool_rx_produce
+ * - hci_mem_pool_rx_data_size_set
+ * - hci_mem_pool_rx_extract
+ * - hci_mem_pool_rx_consume
+ *
+ * @warning If the above mentioned expected call order is violated the end result can be undefined.
+ *
+ * \par Component specific configuration options
+ *
+ * The following compile time configuration options are available to suit various implementations:
+ * - TX_BUF_SIZE TX buffer size in bytes.
+ * - RX_BUF_SIZE RX buffer size in bytes.
+ * - RX_BUF_QUEUE_SIZE RX buffer element size.
+ */
+
+#ifndef HCI_MEM_POOL_H__
+#define HCI_MEM_POOL_H__
+
+#include <stdint.h>
+#include "nrf_error.h"
+
+/**@brief Function for opening the module.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_mem_pool_open(void);
+
+/**@brief Function for closing the module.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_mem_pool_close(void);
+
+/**@brief Function for allocating requested amount of TX memory.
+ *
+ * @param[out] pp_buffer Pointer to the allocated memory.
+ *
+ * @retval NRF_SUCCESS Operation success. Memory was allocated.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No memory available for allocation.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_mem_pool_tx_alloc(void ** pp_buffer);
+
+/**@brief Function for freeing previously allocated TX memory.
+ *
+ * @note Memory management follows the FIFO principle meaning that free() order must match the
+ * alloc(...) order, which is the reason for omitting exact memory block identifier as an
+ * input parameter.
+ *
+ * @retval NRF_SUCCESS Operation success. Memory was freed.
+ */
+uint32_t hci_mem_pool_tx_free(void);
+
+/**@brief Function for producing a free RX memory block for usage.
+ *
+ * @note Upon produce request amount being 0, NRF_SUCCESS is returned.
+ *
+ * @param[in] length Amount, in bytes, of free memory to be produced.
+ * @param[out] pp_buffer Pointer to the allocated memory.
+ *
+ * @retval NRF_SUCCESS Operation success. Free RX memory block produced.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No suitable memory available for allocation.
+ * @retval NRF_ERROR_DATA_SIZE Operation failure. Request size exceeds limit.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_mem_pool_rx_produce(uint32_t length, void ** pp_buffer);
+
+/**@brief Function for setting the length of the last produced RX memory block.
+ *
+ * @warning If call to this API is omitted the end result is that the following call to
+ * mem_pool_rx_extract will return incorrect data in the p_length output parameter.
+ *
+ * @param[in] length Amount, in bytes, of actual memory used.
+ *
+ * @retval NRF_SUCCESS Operation success. Length was set.
+ */
+uint32_t hci_mem_pool_rx_data_size_set(uint32_t length);
+
+/**@brief Function for extracting a packet, which has been filled with read data, for further
+ * processing.
+ *
+ * @param[out] pp_buffer Pointer to the packet data.
+ * @param[out] p_length Length of packet data in bytes.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to extract.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_mem_pool_rx_extract(uint8_t ** pp_buffer, uint32_t * p_length);
+
+/**@brief Function for freeing previously extracted packet, which has been filled with read data.
+ *
+ * @param[in] p_buffer Pointer to consumed buffer.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to free.
+ * @retval NRF_ERROR_INVALID_ADDR Operation failure. Not a valid pointer.
+ */
+uint32_t hci_mem_pool_rx_consume(uint8_t * p_buffer);
+
+#endif // HCI_MEM_POOL_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_mem_pool_internal.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,32 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup memory_pool_internal Memory Pool Internal
+ * @{
+ * @ingroup memory_pool
+ *
+ * @brief Memory pool internal definitions
+ */
+
+#ifndef MEM_POOL_INTERNAL_H__
+#define MEM_POOL_INTERNAL_H__
+
+#define TX_BUF_SIZE 600u /**< TX buffer size in bytes. */
+#define RX_BUF_SIZE TX_BUF_SIZE /**< RX buffer size in bytes. */
+
+#define RX_BUF_QUEUE_SIZE 4u /**< RX buffer element size. */
+
+#endif // MEM_POOL_INTERNAL_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_slip.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,129 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup hci_slip SLIP module
+ * @{
+ * @ingroup app_common
+ *
+ * @brief SLIP layer for supporting packet framing in HCI transport.
+ *
+ * @details This module implements SLIP packet framing as described in the Bluetooth Core
+ * Specification 4.0, Volume 4, Part D, Chapter 3 SLIP Layer.
+ *
+ * SLIP framing ensures that all packets sent on the UART are framed as:
+ * <0xC0> SLIP packet 1 <0xC0> <0xC0> SLIP packet 2 <0xC0>.
+ *
+ * The SLIP layer uses events to notify the upper layer when data transmission is complete
+ * and when a SLIP packet is received.
+ */
+
+#ifndef HCI_SLIP_H__
+#define HCI_SLIP_H__
+
+#include <stdint.h>
+
+/**@brief Event types from the SLIP Layer. */
+typedef enum
+{
+ HCI_SLIP_RX_RDY, /**< An event indicating that an RX packet is ready to be read. */
+ HCI_SLIP_TX_DONE, /**< An event indicating write completion of the TX packet provided in the function call \ref hci_slip_write . */
+ HCI_SLIP_RX_OVERFLOW, /**< An event indicating that RX data has been discarded due to lack of free RX memory. */
+ HCI_SLIP_ERROR, /**< An event indicating that an unrecoverable error has occurred. */
+ HCI_SLIP_EVT_TYPE_MAX /**< Enumeration upper bound. */
+} hci_slip_evt_type_t;
+
+/**@brief Structure containing an event from the SLIP layer.
+ */
+typedef struct
+{
+ hci_slip_evt_type_t evt_type; /**< Type of event. */
+ const uint8_t * packet; /**< This field contains a pointer to the packet for which the event relates, i.e. SLIP_TX_DONE: the packet transmitted, SLIP_RX_RDY: the packet received, SLIP_RX_OVERFLOW: The packet which overflow/or NULL if no receive buffer is available. */
+ uint32_t packet_length; /**< Packet length, i.e. SLIP_TX_DONE: Bytes transmitted, SLIP_RX_RDY: Bytes received, SLIP_RX_OVERFLOW: index at which the packet overflowed. */
+} hci_slip_evt_t;
+
+/**@brief Function for the SLIP layer event callback.
+ */
+typedef void (*hci_slip_event_handler_t)(hci_slip_evt_t event);
+
+/**@brief Function for registering the event handler provided as parameter and this event handler
+ * will be used by SLIP layer to send events described in \ref hci_slip_evt_type_t.
+ *
+ * @note Multiple registration requests will overwrite any existing registration.
+ *
+ * @param[in] event_handler This function is called by the SLIP layer upon an event.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_slip_evt_handler_register(hci_slip_event_handler_t event_handler);
+
+/**@brief Function for opening the SLIP layer. This function must be called before
+ * \ref hci_slip_write and before any data can be received.
+ *
+ * @note Can be called multiple times.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ *
+ * The SLIP layer module will propagate errors from underlying sub-modules.
+ * This implementation is using UART module as a physical transmission layer, and hci_slip_open
+ * executes \ref app_uart_init . For an extended error list, please refer to \ref app_uart_init .
+ */
+uint32_t hci_slip_open(void);
+
+/**@brief Function for closing the SLIP layer. After this function is called no data can be
+ * transmitted or received in this layer.
+ *
+ * @note This function can be called multiple times and also for an unopened channel.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_slip_close(void);
+
+/**@brief Function for writing a packet with SLIP encoding. Packet transmission is confirmed when
+ * the HCI_SLIP_TX_DONE event is received by the function caller.
+ *
+ * @param[in] p_buffer Pointer to the packet to transmit.
+ * @param[in] length Packet length, in bytes.
+ *
+ * @retval NRF_SUCCESS Operation success. Packet was encoded and added to the
+ * transmission queue and an event will be sent upon transmission
+ * completion.
+ * @retval NRF_ERROR_NO_MEM Operation failure. Transmission queue is full and packet was not
+ * added to the transmission queue. Application shall wait for
+ * the \ref HCI_SLIP_TX_DONE event. After HCI_SLIP_TX_DONE this
+ * function can be executed for transmission of next packet.
+ * @retval NRF_ERROR_INVALID_ADDR If a NULL pointer is provided.
+ * @retval NRF_ERROR_INVALID_STATE Operation failure. Module is not open.
+ */
+uint32_t hci_slip_write(const uint8_t * p_buffer, uint32_t length);
+
+/**@brief Function for registering a receive buffer. The receive buffer will be used for storage of
+ * received and SLIP decoded data.
+ * No data can be received by the SLIP layer until a receive buffer has been registered.
+ *
+ * @note The lifetime of the buffer must be valid during complete reception of data. A static
+ * buffer is recommended.
+ *
+ * @warning Multiple registration requests will overwrite any existing registration.
+ *
+ * @param[in] p_buffer Pointer to receive buffer. The received and SLIP decoded packet
+ * will be placed in this buffer.
+ * @param[in] length Buffer length, in bytes.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_slip_rx_buffer_register(uint8_t * p_buffer, uint32_t length);
+
+#endif // HCI_SLIP_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_transport.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,220 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/**@file
+ *
+ * @defgroup hci_transport HCI Transport
+ * @{
+ * @ingroup app_common
+ *
+ * @brief HCI transport module implementation.
+ *
+ * This module implements certain specific features from the three-wire UART transport layer,
+ * defined by the Bluetooth specification version 4.0 [Vol 4] part D.
+ *
+ * \par Features supported
+ * - Transmission and reception of Vendor Specific HCI packet type application packets.
+ * - Transmission and reception of reliable packets: defined by chapter 6 of the specification.
+ *
+ * \par Features not supported
+ * - Link establishment procedure: defined by chapter 8 of the specification.
+ * - Low power: defined by chapter 9 of the specification.
+ *
+ * \par Implementation specific behaviour
+ * - As Link establishment procedure is not supported following static link configuration parameters
+ * are used:
+ * + TX window size is 1.
+ * + 16 bit CCITT-CRC must be used.
+ * + Out of frame software flow control not supported.
+ * + Parameters specific for resending reliable packets are compile time configurable (clarifed
+ * later in this document).
+ * + Acknowledgement packet transmissions are not timeout driven , meaning they are delivered for
+ * transmission within same context which the corresponding application packet was received.
+ *
+ * \par Implementation specific limitations
+ * Current implementation has the following limitations which will have impact to system wide
+ * behaviour:
+ * - Delayed acknowledgement scheduling not implemented:
+ * There exists a possibility that acknowledgement TX packet and application TX packet will collide
+ * in the TX pipeline having the end result that acknowledgement packet will be excluded from the TX
+ * pipeline which will trigger the retransmission algorithm within the peer protocol entity.
+ * - Delayed retransmission scheduling not implemented:
+ * There exists a possibility that retransmitted application TX packet and acknowledgement TX packet
+ * will collide in the TX pipeline having the end result that retransmitted application TX packet
+ * will be excluded from the TX pipeline.
+ * - Processing of the acknowledgement number from RX application packets:
+ * Acknowledgement number is not processed from the RX application packets having the end result
+ * that unnecessary application packet retransmissions can occur.
+ *
+ * The application TX packet processing flow is illustrated by the statemachine below.
+ *
+ * @image html hci_transport_tx_sm.png "TX - application packet statemachine"
+ *
+ * \par Component specific configuration options
+ *
+ * The following compile time configuration options are available, and used to configure the
+ * application TX packet retransmission interval, in order to suite various application specific
+ * implementations:
+ * - MAC_PACKET_SIZE_IN_BITS Maximum size of a single application packet in bits.
+ * - USED_BAUD_RATE Used uart baudrate.
+ *
+ * The following compile time configuration option is available to configure module specific
+ * behaviour:
+ * - MAX_RETRY_COUNT Max retransmission retry count for applicaton packets.
+ */
+
+#ifndef HCI_TRANSPORT_H__
+#define HCI_TRANSPORT_H__
+
+#include <stdint.h>
+#include "nrf_error.h"
+
+/**@brief Generic event callback function events. */
+typedef enum
+{
+ HCI_TRANSPORT_RX_RDY, /**< An event indicating that RX packet is ready for read. */
+ HCI_TRANSPORT_EVT_TYPE_MAX /**< Enumeration upper bound. */
+} hci_transport_evt_type_t;
+
+/**@brief Struct containing events from the Transport layer.
+ */
+typedef struct
+{
+ hci_transport_evt_type_t evt_type; /**< Type of event. */
+} hci_transport_evt_t;
+
+/**@brief Transport layer generic event callback function type.
+ *
+ * @param[in] event Transport layer event.
+ */
+typedef void (*hci_transport_event_handler_t)(hci_transport_evt_t event);
+
+/**@brief TX done event callback function result codes. */
+typedef enum
+{
+ HCI_TRANSPORT_TX_DONE_SUCCESS, /**< Transmission success, peer transport entity has acknowledged the transmission. */
+ HCI_TRANSPORT_TX_DONE_FAILURE /**< Transmission failure. */
+} hci_transport_tx_done_result_t;
+
+/**@brief Transport layer TX done event callback function type.
+ *
+ * @param[in] result TX done event result code.
+ */
+typedef void (*hci_transport_tx_done_handler_t)(hci_transport_tx_done_result_t result);
+
+/**@brief Function for registering a generic event handler.
+ *
+ * @note Multiple registration requests will overwrite any possible existing registration.
+ *
+ * @param[in] event_handler The function to be called by the transport layer upon an event.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_evt_handler_reg(hci_transport_event_handler_t event_handler);
+
+/**@brief Function for registering a handler for TX done event.
+ *
+ * @note Multiple registration requests will overwrite any possible existing registration.
+ *
+ * @param[in] event_handler The function to be called by the transport layer upon TX done
+ * event.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_tx_done_register(hci_transport_tx_done_handler_t event_handler);
+
+/**@brief Function for opening the transport channel and initializing the transport layer.
+ *
+ * @warning Must not be called for a channel which has been allready opened.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_INTERNAL Operation failure. Internal error ocurred.
+ */
+uint32_t hci_transport_open(void);
+
+/**@brief Function for closing the transport channel.
+ *
+ * @note Can be called multiple times and also for not opened channel.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_transport_close(void);
+
+/**@brief Function for allocating tx packet memory.
+ *
+ * @param[out] pp_memory Pointer to the packet data.
+ *
+ * @retval NRF_SUCCESS Operation success. Memory was allocated.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No memory available.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_tx_alloc(uint8_t ** pp_memory);
+
+/**@brief Function for freeing tx packet memory.
+ *
+ * @note Memory management works in FIFO principle meaning that free order must match the alloc
+ * order.
+ *
+ * @retval NRF_SUCCESS Operation success. Memory was freed.
+ */
+uint32_t hci_transport_tx_free(void);
+
+/**@brief Function for writing a packet.
+ *
+ * @note Completion of this method does not guarantee that actual peripheral transmission would
+ * have completed.
+ *
+ * @note In case of 0 byte packet length write request, message will consist of only transport
+ * module specific headers.
+ *
+ * @retval NRF_SUCCESS Operation success. Packet was added to the transmission queue
+ * and an event will be send upon transmission completion.
+ * @retval NRF_ERROR_NO_MEM Operation failure. Transmission queue is full and packet was not
+ * added to the transmission queue. User should wait for
+ * a appropriate event prior issuing this operation again.
+ * @retval NRF_ERROR_DATA_SIZE Operation failure. Packet size exceeds limit.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ * @retval NRF_ERROR_INVALID_STATE Operation failure. Channel is not open.
+ */
+uint32_t hci_transport_pkt_write(const uint8_t * p_buffer, uint32_t length);
+
+/**@brief Function for extracting received packet.
+ *
+ * @note Extracted memory can't be reused by the underlying transport layer untill freed by call to
+ * hci_transport_rx_pkt_consume().
+ *
+ * @param[out] pp_buffer Pointer to the packet data.
+ * @param[out] p_length Length of packet data in bytes.
+ *
+ * @retval NRF_SUCCESS Operation success. Packet was extracted.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to extract.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_rx_pkt_extract(uint8_t ** pp_buffer, uint32_t * p_length);
+
+/**@brief Function for consuming extracted packet described by p_buffer.
+ *
+ * RX memory pointed to by p_buffer is freed and can be reused by the underlying transport layer.
+ *
+ * @param[in] p_buffer Pointer to the buffer that has been consumed.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to consume.
+ * @retval NRF_ERROR_INVALID_ADDR Operation failure. Not a valid pointer.
+ */
+uint32_t hci_transport_rx_pkt_consume(uint8_t * p_buffer);
+
+#endif // HCI_TRANSPORT_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/pstorage.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,381 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/**@file
+ *
+ * @defgroup persistent_storage Persistent Storage Interface
+ * @{
+ * @ingroup app_common
+ * @brief Abstracted flash interface.
+ *
+ * @details In order to ensure that the SDK and application be moved to alternate persistent storage
+ * options other than the default provided with NRF solution, an abstracted interface is provided
+ * by the module to ensure SDK modules and application can be ported to alternate option with ease.
+ */
+
+#ifndef PSTORAGE_H__
+#define PSTORAGE_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* #ifdef __cplusplus */
+
+#include "pstorage_platform.h"
+
+
+/**@defgroup ps_opcode Persistent Storage Access Operation Codes
+ * @{
+ * @brief Persistent Storage Access Operation Codes. These are used to report any error during
+ * a persistent storage access operation or any general error that may occur in the
+ * interface.
+ *
+ * @details Persistent Storage Access Operation Codes used in error notification callback
+ * registered with the interface to report any error during an persistent storage access
+ * operation or any general error that may occur in the interface.
+ */
+#define PSTORAGE_ERROR_OP_CODE 0x01 /**< General Error Code */
+#define PSTORAGE_STORE_OP_CODE 0x02 /**< Error when Store Operation was requested */
+#define PSTORAGE_LOAD_OP_CODE 0x03 /**< Error when Load Operation was requested */
+#define PSTORAGE_CLEAR_OP_CODE 0x04 /**< Error when Clear Operation was requested */
+#define PSTORAGE_UPDATE_OP_CODE 0x05 /**< Update an already touched storage block */
+
+/**@} */
+
+/**@defgroup pstorage_data_types Persistent Memory Interface Data Types
+ * @{
+ * @brief Data Types needed for interfacing with persistent memory.
+ *
+ * @details Data Types needed for interfacing with persistent memory.
+ */
+
+/**@brief Persistent Storage Error Reporting Callback
+ *
+ * @details Persistent Storage Error Reporting Callback that is used by the interface to report
+ * success or failure of a flash operation. Therefore, for any operations, application
+ * can know when the procedure was complete. For store operation, since no data copy
+ * is made, receiving a success or failure notification, indicated by the reason
+ * parameter of callback is an indication that the resident memory could now be reused
+ * or freed, as the case may be.
+ *
+ * @param[in] handle Identifies module and block for which callback is received.
+ * @param[in] op_code Identifies the operation for which the event is notified.
+ * @param[in] result Identifies the result of flash access operation.
+ * NRF_SUCCESS implies, operation succeeded.
+ * @param[in] p_data Identifies the application data pointer. In case of store operation, this
+ * points to the resident source of application memory that application can now
+ * free or reuse. In case of clear, this is NULL as no application pointer is
+ * needed for this operation.
+ * @param[in] data_len Length data application had provided for the operation.
+ *
+ */
+typedef void (*pstorage_ntf_cb_t)(pstorage_handle_t * p_handle,
+ uint8_t op_code,
+ uint32_t result,
+ uint8_t * p_data,
+ uint32_t data_len);
+
+
+typedef struct
+{
+ pstorage_ntf_cb_t cb; /**< Callback registered with the module to be notified of any error occurring in persistent memory management */
+ pstorage_size_t block_size; /**< Desired block size for persistent memory storage, for example, if a module has a table with 10 entries, each entry is size 64 bytes,
+ * it can request 10 blocks with block size 64 bytes. On the other hand, the module can also request one block of size 640 based on
+ * how it would like to access or alter memory in persistent memory.
+ * First option is preferred when single entries that need to be updated often when having no impact on the other entries.
+ * While second option is preferred when entries of table are not changed on individually but have common point of loading and storing
+ * data. */
+ pstorage_size_t block_count; /** Number of blocks requested by the module, minimum values is 1. */
+} pstorage_module_param_t;
+
+/**@} */
+
+/**@defgroup pstorage_routines Persistent Storage Access Routines
+ * @{
+ * @brief Functions/Interface SDK modules use to persistently store data.
+ *
+ * @details Interface for Application & SDK module to load/store information persistently.
+ * Note: that while implementation of each of the persistent storage access function
+ * depends on the system and can specific to system/solution, the signature of the
+ * interface routines should not be altered.
+ */
+
+/**@brief Module Initialization Routine.
+ *
+ * @details Initializes module. To be called once before any other APIs of the module are used.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ */
+uint32_t pstorage_init(void);
+
+
+/**@brief Register with persistent storage interface.
+ *
+ * @param[in] p_module_param Module registration param.
+ * @param[out] p_block_id Block identifier to identify persistent memory blocks in case
+ * registration succeeds. Application is expected to use the block ids
+ * for subsequent operations on requested persistent memory. Maximum
+ * registrations permitted is determined by configuration parameter
+ * PSTORAGE_MAX_APPLICATIONS.
+ * In case more than one memory blocks are requested, the identifier provided here is
+ * the base identifier for the first block and to identify subsequent block,
+ * application shall use \@ref pstorage_block_identifier_get with this base identifier
+ * and block number. Therefore if 10 blocks of size 64 are requested and application
+ * wishes to store memory in 6th block, it shall use
+ * \@ref pstorage_block_identifier_get with based id and provide a block number of 5.
+ * This way application is only expected to remember the base block identifier.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_NO_MEM in case no more registrations can be supported.
+ */
+uint32_t pstorage_register(pstorage_module_param_t * p_module_param,
+ pstorage_handle_t * p_block_id);
+
+
+/**
+ * @brief Function to get block id with reference to base block identifier provided at time of
+ * registration.
+ *
+ * @details Function to get block id with reference to base block identifier provided at time of
+ * registration.
+ * In case more than one memory blocks were requested when registering, the identifier
+ * provided here is the base identifier for the first block and to identify subsequent
+ * block, application shall use this routine to get block identifier providing input as
+ * base identifier and block number. Therefore if 10 blocks of size 64 are requested and
+ * application wishes to store memory in 6th block, it shall use
+ * \@ref pstorage_block_identifier_get with based id and provide a block number of 5.
+ * This way application is only expected to remember the base block identifier.
+ *
+ * @param[in] p_base_id Base block id received at the time of registration.
+ * @param[in] block_num Block Number, with first block numbered zero.
+ * @param[out] p_block_id Block identifier for the block number requested in case the API succeeds.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ */
+uint32_t pstorage_block_identifier_get(pstorage_handle_t * p_base_id,
+ pstorage_size_t block_num,
+ pstorage_handle_t * p_block_id);
+
+
+/**@brief Routine to persistently store data of length 'size' contained in 'p_src' address
+ * in storage module at 'p_dest' address; Equivalent to Storage Write.
+ *
+ * @param[in] p_dest Destination address where data is to be stored persistently.
+ * @param[in] p_src Source address containing data to be stored. API assumes this to be resident
+ * memory and no intermediate copy of data is made by the API.
+ * @param[in] size Size of data to be stored expressed in bytes. Should be word aligned.
+ * @param[in] offset Offset in bytes to be applied when writing to the block.
+ * For example, if within a block of 100 bytes, application wishes to
+ * write 20 bytes at offset of 12, then this field should be set to 12.
+ * Should be word aligned.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_src' is not aligned.
+ * @retval NRF_ERROR_NO_MEM in case request cannot be processed.
+ *
+ * @warning No copy of the data is made, and hence memory provided for data source to be written
+ * to flash cannot be freed or reused by the application until this procedure
+ * is complete. End of this procedure is notified to the application using the
+ * notification callback registered by the application.
+ */
+uint32_t pstorage_store(pstorage_handle_t * p_dest,
+ uint8_t * p_src,
+ pstorage_size_t size,
+ pstorage_size_t offset);
+
+/**@brief Routine to update persistently stored data of length 'size' contained in 'p_src' address
+ * in storage module at 'p_dest' address.
+ *
+ * @param[in] p_dest Destination address where data is to be updated.
+ * @param[in] p_src Source address containing data to be stored. API assumes this to be resident
+ * memory and no intermediate copy of data is made by the API.
+ * @param[in] size Size of data to be stored expressed in bytes. Should be word aligned.
+ * @param[in] offset Offset in bytes to be applied when writing to the block.
+ * For example, if within a block of 100 bytes, application wishes to
+ * write 20 bytes at offset of 12, then this field should be set to 12.
+ * Should be word aligned.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_src' is not aligned.
+ * @retval NRF_ERROR_NO_MEM in case request cannot be processed.
+ *
+ * @warning No copy of the data is made, and hence memory provided for data source to be written
+ * to flash cannot be freed or reused by the application until this procedure
+ * is complete. End of this procedure is notified to the application using the
+ * notification callback registered by the application.
+ */
+uint32_t pstorage_update(pstorage_handle_t * p_dest,
+ uint8_t * p_src,
+ pstorage_size_t size,
+ pstorage_size_t offset);
+
+/**@brief Routine to load persistently stored data of length 'size' from 'p_src' address
+ * to 'p_dest' address; Equivalent to Storage Read.
+ *
+ * @param[in] p_dest Destination address where persistently stored data is to be loaded.
+ * @param[in] p_src Source from where data is to be loaded from persistent memory.
+ * @param[in] size Size of data to be loaded from persistent memory expressed in bytes.
+ * Should be word aligned.
+ * @param[in] offset Offset in bytes to be applied when loading from the block.
+ * For example, if within a block of 100 bytes, application wishes to
+ * load 20 bytes from offset of 12, then this field should be set to 12.
+ * Should be word aligned.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_dst' is not aligned.
+ * @retval NRF_ERROR_NO_MEM in case request cannot be processed.
+ */
+uint32_t pstorage_load(uint8_t * p_dest,
+ pstorage_handle_t * p_src,
+ pstorage_size_t size,
+ pstorage_size_t offset);
+
+/**@brief Routine to clear data in persistent memory.
+ *
+ * @param[in] p_base_id Base block identifier in persistent memory that needs to cleared;
+ * Equivalent to an Erase Operation.
+ *
+ * @param[in] size Size of data to be cleared from persistent memory expressed in bytes.
+ * This parameter is to provision for clearing of certain blocks
+ * of memory, or all memory blocks in a registered module. If the total size
+ * of the application module is used (blocks * block size) in combination with
+ * the identifier for the first block in the module, all blocks in the
+ * module will be erased.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_dst' is not aligned.
+ * @retval NRF_ERROR_NO_MEM in case request cannot be processed.
+ *
+ * @note Clear operations may take time. This API however, does not block until the clear
+ * procedure is complete. Application is notified of procedure completion using
+ * notification callback registered by the application. 'result' parameter of the
+ * callback suggests if the procedure was successful or not.
+ */
+uint32_t pstorage_clear(pstorage_handle_t * p_base_id, pstorage_size_t size);
+
+/**
+ * @brief API to get status of number of pending operations with the module.
+ *
+ * @param[out] p_count Number of storage operations pending with the module, if 0,
+ * there are no outstanding requests.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ */
+uint32_t pstorage_access_status_get(uint32_t * p_count);
+
+#ifdef PSTORAGE_RAW_MODE_ENABLE
+
+/**@brief Function for registering with persistent storage interface.
+ *
+ * @param[in] p_module_param Module registration param.
+ * @param[out] p_block_id Block identifier to identify persistent memory blocks in case
+ * registration succeeds. Application is expected to use the block ids
+ * for subsequent operations on requested persistent memory.
+ * In case more than one memory blocks are requested, the identifier provided here is
+ * the base identifier for the first block and to identify subsequent block,
+ * application shall use \@ref pstorage_block_identifier_get with this base identifier
+ * and block number. Therefore if 10 blocks of size 64 are requested and application
+ * wishes to store memory in 6th block, it shall use
+ * \@ref pstorage_block_identifier_get with based id and provide a block number of 5.
+ * This way application is only expected to remember the base block identifier.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_NO_MEM in case no more registrations can be supported.
+ */
+uint32_t pstorage_raw_register(pstorage_module_param_t * p_module_param,
+ pstorage_handle_t * p_block_id);
+
+/**@brief Raw mode function for persistently storing data of length 'size' contained in 'p_src'
+ * address in storage module at 'p_dest' address; Equivalent to Storage Write.
+ *
+ * @param[in] p_dest Destination address where data is to be stored persistently.
+ * @param[in] p_src Source address containing data to be stored. API assumes this to be resident
+ * memory and no intermediate copy of data is made by the API.
+ * @param[in] size Size of data to be stored expressed in bytes. Should be word aligned.
+ * @param[in] offset Offset in bytes to be applied when writing to the block.
+ * For example, if within a block of 100 bytes, application wishes to
+ * write 20 bytes at offset of 12, then this field should be set to 12.
+ * Should be word aligned.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_src' is not aligned.
+ * @retval NRF_ERROR_NO_MEM in case request cannot be processed.
+ *
+ * @warning No copy of the data is made, and hence memory provided for data source to be written
+ * to flash cannot be freed or reused by the application until this procedure
+ * is complete. End of this procedure is notified to the application using the
+ * notification callback registered by the application.
+ */
+uint32_t pstorage_raw_store(pstorage_handle_t * p_dest,
+ uint8_t * p_src,
+ pstorage_size_t size,
+ pstorage_size_t offset);
+
+/**@brief Function for clearing data in persistent memory in raw mode.
+ *
+ * @param[in] p_dest Base block identifier in persistent memory that needs to cleared;
+ * Equivalent to an Erase Operation.
+ * @param[in] size Size of data to be cleared from persistent memory expressed in bytes.
+ * This is currently unused. And a clear would mean clearing all blocks,
+ * however, this parameter is to provision for clearing of certain blocks
+ * of memory only and not all if need be.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_NO_MEM in case request cannot be processed.
+ *
+ * @note Clear operations may take time. This API however, does not block until the clear
+ * procedure is complete. Application is notified of procedure completion using
+ * notification callback registered by the application. 'result' parameter of the
+ * callback suggests if the procedure was successful or not.
+ */
+uint32_t pstorage_raw_clear(pstorage_handle_t * p_dest, pstorage_size_t size);
+
+#endif // PSTORAGE_RAW_MODE_ENABLE
+
+#ifdef __cplusplus
+}
+#endif /* #ifdef __cplusplus */
+
+
+/**@} */
+/**@} */
+
+#endif // PSTORAGE_H__
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/nrf_delay.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,74 @@
+#ifndef _NRF_DELAY_H
+#define _NRF_DELAY_H
+
+// #include "nrf.h"
+
+/*lint --e{438, 522} "Variable not used" "Function lacks side-effects" */
+#if defined ( __CC_ARM )
+static __ASM void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
+{
+loop
+ SUBS R0, R0, #1
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ BNE loop
+ BX LR
+}
+#elif defined ( __ICCARM__ )
+static void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
+{
+__ASM (
+"loop:\n\t"
+ " SUBS R0, R0, #1\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " BNE loop\n\t");
+}
+#elif defined ( __GNUC__ )
+static void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
+{
+ do
+ {
+ __ASM volatile (
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ );
+ } while (--number_of_us);
+}
+#endif
+
+void nrf_delay_ms(uint32_t volatile number_of_ms);
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/sd_common/app_util_platform.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,110 @@
+/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/**@file
+ *
+ * @defgroup app_util_platform Utility Functions and Definitions (Platform)
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Various types and definitions available to all applications when using SoftDevice.
+ */
+
+#ifndef APP_UTIL_PLATFORM_H__
+#define APP_UTIL_PLATFORM_H__
+
+#include <stdint.h>
+#include "compiler_abstraction.h"
+#include "nrf51.h"
+#include "app_error.h"
+
+/**@brief The interrupt priorities available to the application while the SoftDevice is active. */
+typedef enum
+{
+ APP_IRQ_PRIORITY_HIGH = 1,
+ APP_IRQ_PRIORITY_LOW = 3
+} app_irq_priority_t;
+
+#define NRF_APP_PRIORITY_THREAD 4 /**< "Interrupt level" when running in Thread Mode. */
+
+/**@cond NO_DOXYGEN */
+#define EXTERNAL_INT_VECTOR_OFFSET 16
+/**@endcond */
+
+#define PACKED(TYPE) __packed TYPE
+
+/**@brief Macro for entering a critical region.
+ *
+ * @note Due to implementation details, there must exist one and only one call to
+ * CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located
+ * in the same scope.
+ */
+#define CRITICAL_REGION_ENTER() \
+ { \
+ uint8_t IS_NESTED_CRITICAL_REGION = 0; \
+ uint32_t CURRENT_INT_PRI = current_int_priority_get(); \
+ if (CURRENT_INT_PRI != APP_IRQ_PRIORITY_HIGH) \
+ { \
+ uint32_t ERR_CODE = sd_nvic_critical_region_enter(&IS_NESTED_CRITICAL_REGION); \
+ if (ERR_CODE == NRF_ERROR_SOFTDEVICE_NOT_ENABLED) \
+ { \
+ __disable_irq(); \
+ } \
+ else \
+ { \
+ APP_ERROR_CHECK(ERR_CODE); \
+ } \
+ }
+
+/**@brief Macro for leaving a critical region.
+ *
+ * @note Due to implementation details, there must exist one and only one call to
+ * CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located
+ * in the same scope.
+ */
+#define CRITICAL_REGION_EXIT() \
+ if (CURRENT_INT_PRI != APP_IRQ_PRIORITY_HIGH) \
+ { \
+ uint32_t ERR_CODE; \
+ __enable_irq(); \
+ ERR_CODE = sd_nvic_critical_region_exit(IS_NESTED_CRITICAL_REGION); \
+ if (ERR_CODE != NRF_ERROR_SOFTDEVICE_NOT_ENABLED) \
+ { \
+ APP_ERROR_CHECK(ERR_CODE); \
+ } \
+ } \
+ }
+
+/**@brief Function for finding the current interrupt level.
+ *
+ * @return Current interrupt level.
+ * @retval APP_IRQ_PRIORITY_HIGH We are running in Application High interrupt level.
+ * @retval APP_IRQ_PRIORITY_LOW We are running in Application Low interrupt level.
+ * @retval APP_IRQ_PRIORITY_THREAD We are running in Thread Mode.
+ */
+static __INLINE uint8_t current_int_priority_get(void)
+{
+ uint32_t isr_vector_num = (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk);
+ if (isr_vector_num > 0)
+ {
+ int32_t irq_type = ((int32_t)isr_vector_num - EXTERNAL_INT_VECTOR_OFFSET);
+ return (NVIC_GetPriority((IRQn_Type)irq_type) & 0xFF);
+ }
+ else
+ {
+ return NRF_APP_PRIORITY_THREAD;
+ }
+}
+
+#endif // APP_UTIL_PLATFORM_H__
+
+/** @} */
--- a/TARGET_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_0_0/s110_nrf51822_7.0.0_API/include/nrf_svc.h Fri Aug 15 15:28:31 2014 +0100
+++ b/TARGET_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_0_0/s110_nrf51822_7.0.0_API/include/nrf_svc.h Fri Sep 12 16:41:52 2014 +0100
@@ -16,7 +16,7 @@
{ \
__asm( \
"svc %0\n" \
- "bx r14" : : "I" (number) : "r0" \
+ "bx r14" : : "I" ((uint32_t)number) : "r0" \
); \
}
#elif defined (__ICCARM__)
--- a/TARGET_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/objects.h Fri Aug 15 15:28:31 2014 +0100
+++ b/TARGET_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/objects.h Fri Sep 12 16:41:52 2014 +0100
@@ -53,6 +53,7 @@
PinName sda;
PinName scl;
int freq;
+ uint8_t address_set;
};
struct analogin_s {
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Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_crc_ex.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_dac.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_dac_ex.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_dma.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_flash.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_flash_ex.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_gpio.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_i2c.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_i2c_ex.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_i2s.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_irda.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_iwdg.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_pcd.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_pcd_ex.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_pwr.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_pwr_ex.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_rcc.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_rcc_ex.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_rtc.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_rtc_ex.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_smartcard.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_smartcard_ex.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_smbus.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_spi.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_tim.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_tim_ex.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_tsc.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_uart.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_uart_ex.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_usart.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f0xx_hal_wwdg.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/sys.o has changed
Binary file TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/system_stm32f0xx.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/board.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/cmsis_nvic.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/mbed.ar has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/mbed_overrides.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/misc.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/retarget.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/startup_stm32f10x_md.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_adc.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_bkp.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_can.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_cec.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_crc.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_dac.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_dbgmcu.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_dma.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_exti.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_flash.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_fsmc.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_gpio.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_i2c.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_iwdg.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_pwr.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_rcc.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_rtc.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_sdio.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_spi.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_tim.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_usart.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f10x_wwdg.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/sys.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/system_stm32f10x.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/board.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/cmsis_nvic.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/mbed.ar has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/mbed_overrides.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/misc.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/retarget.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_adc.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_bkp.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_can.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_cec.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_crc.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_dac.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_dbgmcu.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_dma.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_exti.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_flash.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_fsmc.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_gpio.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_i2c.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_iwdg.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_pwr.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_rcc.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_rtc.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_sdio.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_spi.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_tim.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_usart.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f10x_wwdg.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/sys.o has changed
Binary file TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/system_stm32f10x.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/board.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/cmsis_nvic.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/mbed.ar has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/mbed_overrides.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/retarget.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/startup_stm32f302x8.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/stm32f30x_adc.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/stm32f30x_can.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/stm32f30x_comp.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/stm32f30x_crc.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/stm32f30x_dac.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/stm32f30x_dbgmcu.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/stm32f30x_dma.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/stm32f30x_exti.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/stm32f30x_flash.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/stm32f30x_gpio.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/stm32f30x_hrtim.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/stm32f30x_i2c.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/stm32f30x_iwdg.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/stm32f30x_misc.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/stm32f30x_opamp.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/stm32f30x_pwr.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/stm32f30x_rcc.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/stm32f30x_rtc.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/stm32f30x_spi.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/stm32f30x_syscfg.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/stm32f30x_tim.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/stm32f30x_usart.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/stm32f30x_wwdg.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/sys.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/system_stm32f30x.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/board.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/cmsis_nvic.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/mbed.ar has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/mbed_overrides.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/retarget.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/stm32f30x_adc.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/stm32f30x_can.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/stm32f30x_comp.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/stm32f30x_crc.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/stm32f30x_dac.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/stm32f30x_dbgmcu.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/stm32f30x_dma.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/stm32f30x_exti.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/stm32f30x_flash.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/stm32f30x_gpio.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/stm32f30x_hrtim.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/stm32f30x_i2c.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/stm32f30x_iwdg.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/stm32f30x_misc.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/stm32f30x_opamp.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/stm32f30x_pwr.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/stm32f30x_rcc.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/stm32f30x_rtc.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/stm32f30x_spi.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/stm32f30x_syscfg.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/stm32f30x_tim.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/stm32f30x_usart.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/stm32f30x_wwdg.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/sys.o has changed
Binary file TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/system_stm32f30x.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/board.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/cmsis_nvic.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/mbed.ar has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/mbed_overrides.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/retarget.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/startup_stm32f334x8.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_adc.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_adc_ex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_can.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_cec.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_comp.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_cortex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_crc.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_crc_ex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_dac.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_dac_ex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_dma.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_flash.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_flash_ex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_gpio.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_hrtim.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_i2c.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_i2c_ex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_i2s.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_i2s_ex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_irda.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_iwdg.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_opamp.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_opamp_ex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_pcd.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_pcd_ex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_pwr.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_pwr_ex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_rcc.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_rcc_ex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_rtc.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_rtc_ex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_sdadc.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_smartcard.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_smartcard_ex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_smbus.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_spi.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_tim.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_tim_ex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_tsc.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_uart.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_uart_ex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_usart.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f3xx_hal_wwdg.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/sys.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/system_stm32f3xx.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/board.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/cmsis_nvic.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/mbed.ar has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/mbed_overrides.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/retarget.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_adc.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_adc_ex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_can.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_cec.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_comp.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_cortex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_crc.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_crc_ex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_dac.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_dac_ex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_dma.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_flash.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_flash_ex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_gpio.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_hrtim.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_i2c.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_i2c_ex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_i2s.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_i2s_ex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_irda.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_iwdg.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_opamp.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_opamp_ex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_pcd.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_pcd_ex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_pwr.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_pwr_ex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_rcc.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_rcc_ex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_rtc.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_rtc_ex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_sdadc.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_smartcard.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_smartcard_ex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_smbus.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_spi.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_tim.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_tim_ex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_tsc.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_uart.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_uart_ex.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_usart.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f3xx_hal_wwdg.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/sys.o has changed
Binary file TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/system_stm32f3xx.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/board.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/cmsis_nvic.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/hal_tick.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/mbed.ar has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/mbed_overrides.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/retarget.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/startup_stm32f401xe.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_adc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_adc_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_can.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_cortex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_crc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_cryp.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_cryp_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_dac.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_dac_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_dcmi.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_dma.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_dma2d.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_dma_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_eth.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_flash.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_flash_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_gpio.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_hash.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_hash_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_hcd.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_i2c.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_i2c_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_i2s.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_i2s_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_irda.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_iwdg.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_ltdc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_nand.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_nor.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_pccard.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_pcd.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_pwr.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_pwr_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_rcc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_rcc_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_rng.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_rtc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_rtc_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_sai.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_sd.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_sdram.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_smartcard.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_spi.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_sram.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_tim.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_tim_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_uart.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_usart.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_wwdg.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_ll_fmc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_ll_fsmc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_ll_sdmmc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_ll_usb.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/sys.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/system_stm32f4xx.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/board.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/cmsis_nvic.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/hal_tick.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/mbed.ar has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/mbed_overrides.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/retarget.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_adc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_adc_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_can.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_cortex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_crc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_cryp.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_cryp_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_dac.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_dac_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_dcmi.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_dma.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_dma2d.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_dma_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_eth.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_flash.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_flash_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_gpio.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_hash.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_hash_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_hcd.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_i2c.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_i2c_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_i2s.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_i2s_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_irda.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_iwdg.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_ltdc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_nand.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_nor.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_pccard.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_pcd.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_pwr.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_pwr_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_rcc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_rcc_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_rng.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_rtc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_rtc_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_sai.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_sd.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_sdram.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_smartcard.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_spi.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_sram.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_tim.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_tim_ex.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_uart.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_usart.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_wwdg.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_ll_fmc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_ll_fsmc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_ll_sdmmc.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f4xx_ll_usb.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/sys.o has changed
Binary file TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/system_stm32f4xx.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/board.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/cmsis_nvic.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/hal_tick.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/mbed.ar has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/mbed_overrides.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/retarget.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_adc.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_adc_ex.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_can.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_cortex.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_crc.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_cryp.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_cryp_ex.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_dac.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_dac_ex.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_dcmi.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_dma.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_dma2d.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_dma_ex.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_eth.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_flash.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_flash_ex.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_flash_ramfunc.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_gpio.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_hash.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_hash_ex.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_hcd.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_i2c.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_i2c_ex.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_i2s.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_i2s_ex.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_irda.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_iwdg.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_ltdc.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_nand.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_nor.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_pccard.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_pcd.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_pcd_ex.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_pwr.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_pwr_ex.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_rcc.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_rcc_ex.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_rng.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_rtc.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_rtc_ex.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_sai.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_sd.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_sdram.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_smartcard.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_spi.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_sram.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_tim.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_tim_ex.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_uart.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_usart.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_wwdg.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_ll_fmc.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_ll_fsmc.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_ll_sdmmc.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f4xx_ll_usb.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/sys.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/system_stm32f4xx.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/board.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/cmsis_nvic.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/hal_tick.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/mbed.ar has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/mbed_overrides.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/retarget.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/startup_stm32f411xe.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_adc.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_adc_ex.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_can.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_cortex.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_crc.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_cryp.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_cryp_ex.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_dac.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_dac_ex.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_dcmi.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_dma.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_dma2d.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_dma_ex.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_eth.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_flash.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_flash_ex.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_flash_ramfunc.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_gpio.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_hash.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_hash_ex.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_hcd.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_i2c.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_i2c_ex.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_i2s.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_i2s_ex.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_irda.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_iwdg.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_ltdc.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_nand.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_nor.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_pccard.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_pcd.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_pcd_ex.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_pwr.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_pwr_ex.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_rcc.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_rcc_ex.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_rng.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_rtc.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_rtc_ex.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_sai.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_sd.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_sdram.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_smartcard.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_spi.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_sram.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_tim.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_tim_ex.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_uart.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_usart.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_hal_wwdg.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_ll_fmc.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_ll_fsmc.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_ll_sdmmc.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_ll_usb.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/sys.o has changed
Binary file TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/system_stm32f4xx.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/board.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/cmsis_nvic.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/mbed.ar has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/mbed_overrides.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/retarget.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/startup_stm32l053xx.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_adc.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_adc_ex.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_comp.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_cortex.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_crc.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_crc_ex.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_cryp.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_dac.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_dac_ex.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_dma.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_flash.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_flash_ex.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_flash_ramfunc.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_gpio.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_i2c.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_i2c_ex.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_i2s.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_irda.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_iwdg.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_lcd.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_lptim.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_pcd.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_pcd_ex.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_pwr.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_pwr_ex.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_rcc.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_rcc_ex.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_rng.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_rtc.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_rtc_ex.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_smartcard.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_smartcard_ex.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_smbus.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_spi.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_tim.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_tim_ex.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_tsc.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_uart.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_uart_ex.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_usart.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l0xx_hal_wwdg.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/sys.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/system_stm32l0xx.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/board.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/cmsis_nvic.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/mbed.ar has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/mbed_overrides.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/retarget.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_adc.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_adc_ex.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_comp.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_cortex.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_crc.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_crc_ex.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_cryp.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_dac.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_dac_ex.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_dma.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_flash.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_flash_ex.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_flash_ramfunc.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_gpio.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_i2c.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_i2c_ex.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_i2s.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_irda.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_iwdg.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_lcd.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_lptim.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_pcd.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_pcd_ex.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_pwr.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_pwr_ex.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_rcc.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_rcc_ex.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_rng.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_rtc.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_rtc_ex.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_smartcard.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_smartcard_ex.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_smbus.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_spi.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_tim.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_tim_ex.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_tsc.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_uart.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_uart_ex.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_usart.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l0xx_hal_wwdg.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/sys.o has changed
Binary file TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/system_stm32l0xx.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/board.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/cmsis_nvic.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/mbed.ar has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/mbed_overrides.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/misc.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/retarget.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/startup_stm32l1xx_hd.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_adc.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_aes.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_aes_util.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_comp.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_crc.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_dac.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_dbgmcu.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_dma.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_exti.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_flash.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_flash_ramfunc.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_fsmc.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_gpio.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_i2c.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_iwdg.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_lcd.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_opamp.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_pwr.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_rcc.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_rtc.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_sdio.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_spi.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_syscfg.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_tim.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_usart.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_wwdg.o has changed
Binary file TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/sys.o has changed
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_OC_MBUINO/LPC11Uxx.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,670 @@
+
+/****************************************************************************************************//**
+ * @file LPC11Uxx.h
+ *
+ *
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
+ * default LPC11Uxx Device Series
+ *
+ * @version V0.1
+ * @date 21. March 2011
+ *
+ * @note Generated with SFDGen V2.6 Build 3j (beta) on Thursday, 17.03.2011 13:19:45
+ *
+ * from CMSIS SVD File 'LPC11U1x_svd.xml' Version 0.1,
+ * created on Wednesday, 16.03.2011 20:30:42, last modified on Thursday, 17.03.2011 20:19:40
+ *
+ *******************************************************************************************************/
+
+// ################################################################################
+// Minor fix 8 April 2011 - changed LPC_CT32B1_BASE from 0x40014000 to 0x40018000
+// ################################################################################
+
+/** @addtogroup NXP
+ * @{
+ */
+
+/** @addtogroup LPC11Uxx
+ * @{
+ */
+
+#ifndef __LPC11UXX_H__
+#define __LPC11UXX_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined ( __CC_ARM )
+ #pragma anon_unions
+#endif
+
+ /* Interrupt Number Definition */
+
+typedef enum {
+// ------------------------- Cortex-M0 Processor Exceptions Numbers -----------------------------
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
+ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
+ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< 15 System Tick Timer */
+// --------------------------- LPC11Uxx Specific Interrupt Numbers ------------------------------
+FLEX_INT0_IRQn = 0, /*!< All I/O pins can be routed to below 8 interrupts. */
+ FLEX_INT1_IRQn = 1,
+ FLEX_INT2_IRQn = 2,
+ FLEX_INT3_IRQn = 3,
+ FLEX_INT4_IRQn = 4,
+ FLEX_INT5_IRQn = 5,
+ FLEX_INT6_IRQn = 6,
+ FLEX_INT7_IRQn = 7,
+ GINT0_IRQn = 8, /*!< Grouped Interrupt 0 */
+ GINT1_IRQn = 9, /*!< Grouped Interrupt 1 */
+ Reserved0_IRQn = 10, /*!< Reserved Interrupt */
+ Reserved1_IRQn = 11,
+ Reserved2_IRQn = 12,
+ Reserved3_IRQn = 13,
+ SSP1_IRQn = 14, /*!< SSP1 Interrupt */
+ I2C_IRQn = 15, /*!< I2C Interrupt */
+ TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */
+ TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */
+ TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */
+ TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */
+ SSP0_IRQn = 20, /*!< SSP0 Interrupt */
+ UART_IRQn = 21, /*!< UART Interrupt */
+ USB_IRQn = 22, /*!< USB IRQ Interrupt */
+ USB_FIQn = 23, /*!< USB FIQ Interrupt */
+ ADC_IRQn = 24, /*!< A/D Converter Interrupt */
+ WDT_IRQn = 25, /*!< Watchdog timer Interrupt */
+ BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */
+ FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */
+ Reserved4_IRQn = 28, /*!< Reserved Interrupt */
+ Reserved5_IRQn = 29, /*!< Reserved Interrupt */
+ USBWakeup_IRQn = 30, /*!< USB wakeup Interrupt */
+ Reserved6_IRQn = 31, /*!< Reserved Interrupt */
+} IRQn_Type;
+
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M0 Processor and Core Peripherals */
+
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
+#include "system_LPC11Uxx.h" /*!< LPC11Uxx System */
+
+/** @addtogroup Device_Peripheral_Registers
+ * @{
+ */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- I2C -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x I2C-bus controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (I2C)
+ */
+
+typedef struct { /*!< (@ 0x40000000) I2C Structure */
+ __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register */
+ __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register */
+ __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. */
+ __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0 */
+ __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word */
+ __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word */
+ __IO uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register*/
+ __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register*/
+ __IO uint32_t ADR1; /*!< (@ 0x40000020) I2C Slave Address Register 1*/
+ __IO uint32_t ADR2; /*!< (@ 0x40000024) I2C Slave Address Register 2*/
+ __IO uint32_t ADR3; /*!< (@ 0x40000028) I2C Slave Address Register 3*/
+ __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register */
+union{
+ __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register */
+ struct{
+ __IO uint32_t MASK0;
+ __IO uint32_t MASK1;
+ __IO uint32_t MASK2;
+ __IO uint32_t MASK3;
+ };
+ };
+} LPC_I2C_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- WWDT -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x Windowed Watchdog Timer (WWDT) Modification date=3/16/2011 Major revision=0 Minor revision=3 (WWDT)
+ */
+
+typedef struct { /*!< (@ 0x40004000) WWDT Structure */
+ __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register*/
+ __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register */
+ __IO uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register */
+ __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register */
+ __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
+ __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
+ __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
+} LPC_WWDT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- USART -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x USART Modification date=3/16/2011 Major revision=0 Minor revision=3 (USART)
+ */
+
+typedef struct { /*!< (@ 0x40008000) USART Structure */
+
+ union {
+ __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
+ __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
+ __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
+ };
+
+ union {
+ __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
+ __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
+ };
+
+ union {
+ __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
+ __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
+ };
+ __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
+ __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
+ __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
+ __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
+ __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
+ __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
+ __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
+ __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
+ __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
+ __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
+ __I uint32_t RESERVED0[3];
+ __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
+ __I uint32_t RESERVED1;
+ __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
+ __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
+ __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
+ __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
+ __IO uint32_t SYNCCTRL;
+} LPC_USART_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- Timer -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x 32-bitcounter/timers CT32B0/1 Modification date=3/16/2011 Major revision=0 Minor revision=3
+ */
+
+typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
+ __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register */
+ __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register */
+ __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter */
+ __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register */
+ __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter */
+ __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register */
+ union {
+ __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register */
+ struct{
+ __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */
+ __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */
+ __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */
+ __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */
+ };
+ };
+ __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register */
+ union{
+ __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register */
+ struct{
+ __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */
+ __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */
+ __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */
+ __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */
+ };
+ };
+__IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register */
+ __I uint32_t RESERVED0[12];
+ __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register */
+ __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register */
+} LPC_CTxxBx_Type;
+
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- ADC -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x ADC Modification date=3/16/2011 Major revision=0 Minor revision=3 (ADC)
+ */
+
+typedef struct { /*!< (@ 0x4001C000) ADC Structure */
+ __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register */
+ __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register */
+ __I uint32_t RESERVED0[1];
+ __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register */
+ union{
+ __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/
+ struct{
+ __IO uint32_t DR0; /*!< (@ 0x40020010) A/D Channel Data Register 0*/
+ __IO uint32_t DR1; /*!< (@ 0x40020014) A/D Channel Data Register 1*/
+ __IO uint32_t DR2; /*!< (@ 0x40020018) A/D Channel Data Register 2*/
+ __IO uint32_t DR3; /*!< (@ 0x4002001C) A/D Channel Data Register 3*/
+ __IO uint32_t DR4; /*!< (@ 0x40020020) A/D Channel Data Register 4*/
+ __IO uint32_t DR5; /*!< (@ 0x40020024) A/D Channel Data Register 5*/
+ __IO uint32_t DR6; /*!< (@ 0x40020028) A/D Channel Data Register 6*/
+ __IO uint32_t DR7; /*!< (@ 0x4002002C) A/D Channel Data Register 7*/
+ };
+ };
+ __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. */
+} LPC_ADC_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- PMU -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x Power Management Unit (PMU) Modification date=3/16/2011 Major revision=0 Minor revision=3 (PMU)
+ */
+
+typedef struct { /*!< (@ 0x40038000) PMU Structure */
+ __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */
+ union{
+ __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */
+ struct{
+ __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */
+ __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */
+ __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */
+ __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */
+ };
+ };
+} LPC_PMU_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- FLASHCTRL -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x Flash programming firmware Modification date=3/17/2011 Major revision=0 Minor revision=3 (FLASHCTRL)
+ */
+
+typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
+ __I uint32_t RESERVED0[4];
+ __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
+ __I uint32_t RESERVED1[3];
+ __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
+ __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
+ __I uint32_t RESERVED2[1];
+ __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
+ __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
+ __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
+ __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
+ __I uint32_t RESERVED3[1001];
+ __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
+ __I uint32_t RESERVED4[1];
+ __IO uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
+} LPC_FLASHCTRL_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SSP0/1 -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x SSP/SPI Modification date=3/16/2011 Major revision=0 Minor revision=3 (SSP0)
+ */
+
+typedef struct { /*!< (@ 0x40040000) SSP0 Structure */
+ __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
+ __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
+ __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
+ __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */
+ __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */
+ __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
+ __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */
+ __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */
+ __IO uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
+} LPC_SSPx_Type;
+
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- IOCONFIG -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG)
+ */
+
+typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */
+ __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
+ __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
+ __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
+ __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
+ __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
+ __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
+ __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
+ __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
+ __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 */
+ __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 */
+ __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
+ __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
+ __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
+ __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
+ __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
+ __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
+ __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
+ __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
+ __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
+ __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
+ __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
+ __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
+ __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
+ __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
+ __IO uint32_t PIO1_0; /*!< Offset: 0x060 */
+ __IO uint32_t PIO1_1;
+ __IO uint32_t PIO1_2;
+ __IO uint32_t PIO1_3;
+ __IO uint32_t PIO1_4; /*!< Offset: 0x070 */
+ __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
+ __IO uint32_t PIO1_6;
+ __IO uint32_t PIO1_7;
+ __IO uint32_t PIO1_8; /*!< Offset: 0x080 */
+ __IO uint32_t PIO1_9;
+ __IO uint32_t PIO1_10;
+ __IO uint32_t PIO1_11;
+ __IO uint32_t PIO1_12; /*!< Offset: 0x090 */
+ __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for pin PIO1_13/DTR/CT16B0_MAT0/TXD */
+ __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for pin PIO1_14/DSR/CT16B0_MAT1/RXD */
+ __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
+ __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
+ __IO uint32_t PIO1_17;
+ __IO uint32_t PIO1_18;
+ __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
+ __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
+ __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
+ __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
+ __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
+ __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
+ __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
+ __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
+ __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
+ __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
+ __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
+ __IO uint32_t PIO1_30;
+ __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
+} LPC_IOCON_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SYSCON -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x System control block Modification date=3/16/2011 Major revision=0 Minor revision=3 (SYSCON)
+ */
+
+typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
+ __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
+ __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
+ __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
+ __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
+ __IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */
+ __I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */
+ __I uint32_t RESERVED0[2];
+ __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
+ __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
+ __I uint32_t RESERVED1[2];
+ __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
+ __I uint32_t RESERVED2[3];
+ __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
+ __IO uint32_t SYSPLLCLKUEN; /*!< (@ 0x40048044) System PLL clock source update enable */
+ __IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */
+ __IO uint32_t USBPLLCLKUEN; /*!< (@ 0x4004804C) USB PLL clock source update enable */
+ __I uint32_t RESERVED3[8];
+ __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
+ __IO uint32_t MAINCLKUEN; /*!< (@ 0x40048074) Main clock source update enable */
+ __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
+ __I uint32_t RESERVED4[1];
+ __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
+ __I uint32_t RESERVED5[4];
+ __IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */
+ __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */
+ __IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */
+ __I uint32_t RESERVED6[8];
+ __IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */
+ __IO uint32_t USBCLKUEN; /*!< (@ 0x400480C4) USB clock source update enable */
+ __IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */
+ __I uint32_t RESERVED7[5];
+ __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
+ __IO uint32_t CLKOUTUEN; /*!< (@ 0x400480E4) CLKOUT clock source update enable */
+ __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
+ __I uint32_t RESERVED8[5];
+ __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
+ __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */
+ __I uint32_t RESERVED9[18];
+ __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
+ __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
+ __I uint32_t RESERVED10[6];
+ __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay */
+ __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
+ __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */
+ __I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */
+ __I uint32_t RESERVED11[25];
+ __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
+ __I uint32_t RESERVED12[3];
+ __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
+ __I uint32_t RESERVED13[6];
+ __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
+ __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
+ __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
+ __I uint32_t RESERVED14[110];
+ __I uint32_t DEVICE_ID; /*!< (@ 0x400483F4) Device ID */
+} LPC_SYSCON_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_PIN_INT -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PIN_INT)
+ */
+
+typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
+ __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */
+ __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
+ __IO uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
+ __IO uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
+ __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
+ __IO uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
+ __IO uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
+ __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
+ __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
+ __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */
+} LPC_GPIO_PIN_INT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_GROUP_INT0/1 -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_GROUP_INT0)
+ */
+
+typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
+ __I uint32_t RESERVED0[7];
+ __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
+ __I uint32_t RESERVED1[6];
+ __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
+} LPC_GPIO_GROUP_INTx_Type;
+
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- USB -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x USB2.0device controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (USB)
+ */
+
+typedef struct { /*!< (@ 0x40080000) USB Structure */
+ __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40080000) USB Device Command/Status register */
+ __IO uint32_t INFO; /*!< (@ 0x40080004) USB Info register */
+ __IO uint32_t EPLISTSTART; /*!< (@ 0x40080008) USB EP Command/Status List start address */
+ __IO uint32_t DATABUFSTART; /*!< (@ 0x4008000C) USB Data buffer start address */
+ __IO uint32_t LPM; /*!< (@ 0x40080010) Link Power Management register */
+ __IO uint32_t EPSKIP; /*!< (@ 0x40080014) USB Endpoint skip */
+ __IO uint32_t EPINUSE; /*!< (@ 0x40080018) USB Endpoint Buffer in use */
+ __IO uint32_t EPBUFCFG; /*!< (@ 0x4008001C) USB Endpoint Buffer Configuration register */
+ __IO uint32_t INTSTAT; /*!< (@ 0x40080020) USB interrupt status register */
+ __IO uint32_t INTEN; /*!< (@ 0x40080024) USB interrupt enable register */
+ __IO uint32_t INTSETSTAT; /*!< (@ 0x40080028) USB set interrupt status register */
+ __IO uint32_t INTROUTING; /*!< (@ 0x4008002C) USB interrupt routing register */
+ __I uint32_t RESERVED0[1];
+ __I uint32_t EPTOGGLE; /*!< (@ 0x40080034) USB Endpoint toggle register */
+} LPC_USB_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_PORT -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT)
+ */
+
+typedef struct {
+ union {
+ struct {
+ __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
+ __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */
+ };
+ __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */
+ };
+ __I uint32_t RESERVED0[1008];
+ union {
+ struct {
+ __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */
+ __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */
+ };
+ __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */
+ };
+ uint32_t RESERVED1[960];
+ __IO uint32_t DIR[2]; /* 0x2000 */
+ uint32_t RESERVED2[30];
+ __IO uint32_t MASK[2]; /* 0x2080 */
+ uint32_t RESERVED3[30];
+ __IO uint32_t PIN[2]; /* 0x2100 */
+ uint32_t RESERVED4[30];
+ __IO uint32_t MPIN[2]; /* 0x2180 */
+ uint32_t RESERVED5[30];
+ __IO uint32_t SET[2]; /* 0x2200 */
+ uint32_t RESERVED6[30];
+ __O uint32_t CLR[2]; /* 0x2280 */
+ uint32_t RESERVED7[30];
+ __O uint32_t NOT[2]; /* 0x2300 */
+} LPC_GPIO_Type;
+
+
+#if defined ( __CC_ARM )
+ #pragma no_anon_unions
+#endif
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- Peripheral memory map -----
+// ------------------------------------------------------------------------------------------------
+
+#define LPC_I2C_BASE (0x40000000)
+#define LPC_WWDT_BASE (0x40004000)
+#define LPC_USART_BASE (0x40008000)
+#define LPC_CT16B0_BASE (0x4000C000)
+#define LPC_CT16B1_BASE (0x40010000)
+#define LPC_CT32B0_BASE (0x40014000)
+#define LPC_CT32B1_BASE (0x40018000)
+#define LPC_ADC_BASE (0x4001C000)
+#define LPC_PMU_BASE (0x40038000)
+#define LPC_FLASHCTRL_BASE (0x4003C000)
+#define LPC_SSP0_BASE (0x40040000)
+#define LPC_SSP1_BASE (0x40058000)
+#define LPC_IOCON_BASE (0x40044000)
+#define LPC_SYSCON_BASE (0x40048000)
+#define LPC_GPIO_PIN_INT_BASE (0x4004C000)
+#define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)
+#define LPC_GPIO_GROUP_INT1_BASE (0x40060000)
+#define LPC_USB_BASE (0x40080000)
+#define LPC_GPIO_BASE (0x50000000)
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- Peripheral declaration -----
+// ------------------------------------------------------------------------------------------------
+
+#define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)
+#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
+#define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)
+#define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE)
+#define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE)
+#define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE)
+#define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE)
+#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
+#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
+#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
+#define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE)
+#define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE)
+#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
+#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
+#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
+#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT0_BASE)
+#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT1_BASE)
+#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
+#define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)
+
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group (null) */
+/** @} */ /* End of group LPC11Uxx */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif // __LPC11UXX_H__
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_OC_MBUINO/TARGET_NXP/TARGET_LPC11UXX/PeripheralPins.h Fri Sep 12 16:41:52 2014 +0100 @@ -0,0 +1,43 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +/************ADC***************/ +extern const PinMap PinMap_ADC[]; + +/************I2C***************/ +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; + +/************UART***************/ +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; + +/************SPI***************/ +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SSEL[]; + +/************PWM***************/ +extern const PinMap PinMap_PWM[]; + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_OC_MBUINO/TARGET_NXP/TARGET_LPC11UXX/PortNames.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ Port0 = 0,
+ Port1 = 1
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_OC_MBUINO/TARGET_NXP/TARGET_LPC11UXX/TARGET_OC_MBUINO/PeripheralNames.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,91 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ UART_0 = (int)LPC_USART_BASE
+} UARTName;
+
+typedef enum {
+ I2C_0 = (int)LPC_I2C_BASE
+} I2CName;
+
+typedef enum {
+ ADC0_0 = 0,
+ ADC0_1,
+ ADC0_2,
+ ADC0_3,
+ ADC0_4,
+ ADC0_5,
+ ADC0_6,
+ ADC0_7
+} ADCName;
+
+typedef enum {
+ SPI_0 = (int)LPC_SSP0_BASE,
+ SPI_1 = (int)LPC_SSP1_BASE
+} SPIName;
+
+typedef enum {
+ PWM_1 = 0,
+ PWM_2,
+ PWM_3,
+ PWM_4,
+ PWM_5,
+ PWM_6,
+ PWM_7,
+ PWM_8,
+ PWM_9,
+ PWM_10,
+ PWM_11,
+ PWM_12,
+ PWM_13
+} PWMName;
+
+#define STDIO_UART_TX USBTX
+#define STDIO_UART_RX USBRX
+#define STDIO_UART UART_0
+
+// Default peripherals
+#define MBED_SPI0 P0_9, P0_8, P0_6, P0_2 // MOSI, MISO, CLK, SEL
+#define MBED_SPI1 P0_21, P0_22, P1_15, P01_19 // MOSI, MISO, CLK, SEL
+
+#define MBED_UART0 USBTX, USBRX
+#define MBED_UARTUSB USBTX, USBRX
+
+#define MBED_I2C0 P0_5, P0_4
+
+#define MBED_ANALOGIN0 P0_11
+#define MBED_ANALOGIN1 P0_12
+#define MBED_ANALOGIN2 P0_13
+#define MBED_ANALOGIN3 P0_14
+#define MBED_ANALOGIN4 P0_15
+#define MBED_ANALOGIN5 P0_16
+#define MBED_ANALOGIN6 P0_22
+#define MBED_ANALOGIN7 P0_23
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_OC_MBUINO/TARGET_NXP/TARGET_LPC11UXX/TARGET_OC_MBUINO/PinNames.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,105 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT 5
+
+typedef enum {
+ // LPC11U24 HVQFN33 Pin Names
+ P0_0 = 0,
+ P0_1 = 1,
+ P0_2 = 2,
+ P0_3 = 3,
+ P0_4 = 4,
+ P0_5 = 5,
+ P0_6 = 6,
+ P0_7 = 7,
+ P0_8 = 8,
+ P0_9 = 9,
+ P0_10 = 10,
+ P0_11 = 11,
+ P0_12 = 12,
+ P0_13 = 13,
+ P0_14 = 14,
+ P0_15 = 15,
+ P0_16 = 16,
+ P0_17 = 17,
+ P0_18 = 18,
+ P0_19 = 19,
+ P0_20 = 20,
+ P0_21 = 21,
+ P0_22 = 22,
+ P0_23 = 23,
+
+ P1_15 = 47,
+ P1_19 = 51,
+
+ // Other mbed Pin Names
+ LED1 = P0_7,
+ LED2 = P0_8,
+ LED3 = P0_2,
+ LED4 = P0_20,
+ LED5 = P1_19,
+ LED6 = P0_17,
+ LED7 = P0_23,
+
+ USBTX = P0_19,
+ USBRX = P0_18,
+
+ I2C_SCL = P0_4,
+ I2C_SDA = P0_5,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF,
+} PinName;
+
+typedef enum {
+ CHANNEL0 = FLEX_INT0_IRQn,
+ CHANNEL1 = FLEX_INT1_IRQn,
+ CHANNEL2 = FLEX_INT2_IRQn,
+ CHANNEL3 = FLEX_INT3_IRQn,
+ CHANNEL4 = FLEX_INT4_IRQn,
+ CHANNEL5 = FLEX_INT5_IRQn,
+ CHANNEL6 = FLEX_INT6_IRQn,
+ CHANNEL7 = FLEX_INT7_IRQn
+} Channel;
+
+typedef enum {
+ PullUp = 2,
+ PullDown = 1,
+ PullNone = 0,
+ Repeater = 3,
+ OpenDrain = 4,
+ PullDefault = PullDown
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_OC_MBUINO/TARGET_NXP/TARGET_LPC11UXX/TARGET_OC_MBUINO/device.h Fri Sep 12 16:41:52 2014 +0100 @@ -0,0 +1,59 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 0 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 32 +#define DEVICE_MAC_OFFSET 20 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_PATTERN 1 + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_OC_MBUINO/TARGET_NXP/TARGET_LPC11UXX/gpio_object.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,52 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "mbed_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ uint32_t mask;
+
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_set;
+ __IO uint32_t *reg_clr;
+ __I uint32_t *reg_in;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ if (value)
+ *obj->reg_set = obj->mask;
+ else
+ *obj->reg_clr = obj->mask;
+}
+
+static inline int gpio_read(gpio_t *obj) {
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_OC_MBUINO/TARGET_NXP/TARGET_LPC11UXX/objects.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,66 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ uint32_t ch;
+};
+
+struct port_s {
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_mpin;
+ PortName port;
+ uint32_t mask;
+};
+
+struct pwmout_s {
+ PWMName pwm;
+};
+
+struct serial_s {
+ LPC_USART_Type *uart;
+ int index;
+};
+
+struct analogin_s {
+ ADCName adc;
+};
+
+struct i2c_s {
+ LPC_I2C_Type *i2c;
+};
+
+struct spi_s {
+ LPC_SSPx_Type *spi;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_OC_MBUINO/TOOLCHAIN_ARM_MICRO/LPC11U24.sct Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,17 @@
+
+LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
+ ER_IROM1 0x00000000 0x8000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 6KB - 0xC0 = 0x1740
+ RW_IRAM1 0x100000C0 0x1740 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
+ .ANY (USBRAM)
+ }
+}
+
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_OC_MBUINO/TOOLCHAIN_ARM_STD/LPC11U24.sct Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,17 @@
+
+LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
+ ER_IROM1 0x00000000 0x8000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 6KB - 0xC0 = 0x1740
+ RW_IRAM1 0x100000C0 0x1740 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
+ .ANY (USBRAM)
+ }
+}
+
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_OC_MBUINO/TOOLCHAIN_GCC_ARM/LPC11U24.ld Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,154 @@
+/* Linker script for mbed LPC1768 */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K
+ RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1740
+ USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text.Reset_Handler)
+ *(.text.SystemInit)
+
+ /* Only vectors and code running at reset are safe to be in first 512
+ bytes since RAM can be mapped into this area for RAM based interrupt
+ vectors. */
+ . = 0x00000200;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_OC_MBUINO/cmsis.h Fri Sep 12 16:41:52 2014 +0100 @@ -0,0 +1,13 @@ +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in LPC11U24 specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "LPC11Uxx.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_OC_MBUINO/cmsis_nvic.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,26 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_OC_MBUINO/core_cm0.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,682 @@
+/**************************************************************************//**
+ * @file core_cm0.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+ @{
+ */
+
+/* CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+ __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0_REV
+ #define __CM0_REV 0x0000
+ #warning "__CM0_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
+ else {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_OC_MBUINO/core_cm0plus.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,793 @@
+/**************************************************************************//**
+ * @file core_cm0plus.h
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+ @{
+ */
+
+/* CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+ __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0PLUS_REV
+ #define __CM0PLUS_REV 0x0000
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if (__VTOR_PRESENT == 1)
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
+ else {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_OC_MBUINO/core_cm3.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,1627 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_OC_MBUINO/core_cm4.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,1772 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+ @{
+ */
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x04) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+#include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/** \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1)
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
+ NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_OC_MBUINO/core_cm4_simd.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,673 @@
+/**************************************************************************//**
+ * @file core_cm4_simd.h
+ * @brief CMSIS Cortex-M4 SIMD Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32) ) >> 32))
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_iar.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_ccs.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_OC_MBUINO/core_cmFunc.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,636 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief Enable IRQ Interrupts
+
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief Disable IRQ Interrupts
+
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ uint32_t result;
+
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_OC_MBUINO/core_cmInstr.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,688 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V3.20
+ * @date 05. March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/** \brief Breakpoint
+
+ This function causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __rbit
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX __clrex
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb");
+}
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb");
+}
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb");
+}
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (short)__builtin_bswap16(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32 - op2));
+}
+
+
+/** \brief Breakpoint
+
+ This function causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_OC_MBUINO/power_api.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,82 @@
+/****************************************************************************
+ * $Id:: power_api.h 6249 2011-01-25 19:23:47Z usb01267 $
+ * Project: NXP LPC11Uxx software example
+ *
+ * Description:
+ * Power API Header File for NXP LPC11Uxx Device Series
+ *
+ ****************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+****************************************************************************/
+#ifndef __LPC11UXX_POWER_API_H__
+#define __LPC11UXX_POWER_API_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define PWRROMD_PRESENT
+
+typedef struct _PWRD {
+ void (*set_pll)(unsigned int cmd[], unsigned int resp[]);
+ void (*set_power)(unsigned int cmd[], unsigned int resp[]);
+} PWRD;
+
+typedef struct _ROM {
+#ifdef USBROMD_PRESENT
+ const USB * pUSBD;
+#else
+ const unsigned p_usbd;
+#endif /* USBROMD_PRESENT */
+ const unsigned p_clib;
+ const unsigned p_cand;
+#ifdef PWRROMD_PRESENT
+ const PWRD * pPWRD;
+#else
+ const unsigned p_pwrd;
+#endif /* PWRROMD_PRESENT */
+ const unsigned p_dev1;
+ const unsigned p_dev2;
+ const unsigned p_dev3;
+ const unsigned p_dev4;
+} ROM;
+
+//PLL setup related definitions
+#define CPU_FREQ_EQU 0 //main PLL freq must be equal to the specified
+#define CPU_FREQ_LTE 1 //main PLL freq must be less than or equal the specified
+#define CPU_FREQ_GTE 2 //main PLL freq must be greater than or equal the specified
+#define CPU_FREQ_APPROX 3 //main PLL freq must be as close as possible the specified
+
+#define PLL_CMD_SUCCESS 0 //PLL setup successfully found
+#define PLL_INVALID_FREQ 1 //specified freq out of range (either input or output)
+#define PLL_INVALID_MODE 2 //invalid mode (see above for valid) specified
+#define PLL_FREQ_NOT_FOUND 3 //specified freq not found under specified conditions
+#define PLL_NOT_LOCKED 4 //PLL not locked => no changes to the PLL setup
+
+//power setup elated definitions
+#define PARAM_DEFAULT 0 //default power settings (voltage regulator, flash interface)
+#define PARAM_CPU_PERFORMANCE 1 //setup for maximum CPU performance (higher current, more computation)
+#define PARAM_EFFICIENCY 2 //balanced setting (power vs CPU performance)
+#define PARAM_LOW_CURRENT 3 //lowest active current, lowest CPU performance
+
+#define PARAM_CMD_SUCCESS 0 //power setting successfully found
+#define PARAM_INVALID_FREQ 1 //specified freq out of range (=0 or > 50 MHz)
+#define PARAM_INVALID_MODE 2 //specified mode not valid (see above for valid)
+
+#define MAX_CLOCK_KHZ_PARAM 50000
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LPC11UXX_POWER_API_H__ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_OC_MBUINO/system_LPC11Uxx.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,64 @@
+/**************************************************************************//**
+ * @file system_LPC11Uxx.h
+ * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File
+ * for the NXP LPC11Uxx Device Series
+ * @version V1.10
+ * @date 24. November 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC11Uxx_H
+#define __SYSTEM_LPC11Uxx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC11Uxx_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_RBLAB_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_button.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,187 @@
+/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup app_button Button Handler
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Buttons handling module.
+ *
+ * @details The button handler uses the @ref app_gpiote to detect that a button has been
+ * pushed. To handle debouncing, it will start a timer in the GPIOTE event handler.
+ * The button will only be reported as pushed if the corresponding pin is still active when
+ * the timer expires. If there is a new GPIOTE event while the timer is running, the timer
+ * is restarted.
+ * Use the USE_SCHEDULER parameter of the APP_BUTTON_INIT() macro to select if the
+ * @ref app_scheduler is to be used or not.
+ *
+ * @note The app_button module uses the app_timer module. The user must ensure that the queue in
+ * app_timer is large enough to hold the app_timer_stop() / app_timer_start() operations
+ * which will be executed on each event from GPIOTE module (2 operations), as well as other
+ * app_timer operations queued simultaneously in the application.
+ *
+ * @note Even if the scheduler is not used, app_button.h will include app_scheduler.h, so when
+ * compiling, app_scheduler.h must be available in one of the compiler include paths.
+ */
+
+#ifndef APP_BUTTON_H__
+#define APP_BUTTON_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "app_error.h"
+#include "app_scheduler.h"
+#include "nrf_gpio.h"
+
+#define APP_BUTTON_SCHED_EVT_SIZE sizeof(app_button_event_t) /**< Size of button events being passed through the scheduler (is to be used for computing the maximum size of scheduler events). */
+#define APP_BUTTON_PUSH 1 /**< Indicates that a button is pushed. */
+#define APP_BUTTON_RELEASE 0 /**< Indicates that a button is released. */
+#define APP_BUTTON_ACTIVE_HIGH 1 /**< Indicates that a button is active high. */
+#define APP_BUTTON_ACTIVE_LOW 0 /**< Indicates that a button is active low. */
+
+/**@brief Button event handler type. */
+typedef void (*app_button_handler_t)(uint8_t pin_no, uint8_t button_action);
+
+/**@brief Type of function for passing events from the Button Handler module to the scheduler. */
+typedef uint32_t (*app_button_evt_schedule_func_t) (app_button_handler_t button_handler,
+ uint8_t pin_no,
+ uint8_t button_action);
+
+/**@brief Button configuration structure. */
+typedef struct
+{
+ uint8_t pin_no; /**< Pin to be used as a button. */
+ uint8_t active_state; /**< APP_BUTTON_ACTIVE_HIGH or APP_BUTTON_ACTIVE_LOW. */
+ nrf_gpio_pin_pull_t pull_cfg; /**< Pull-up or -down configuration. */
+ app_button_handler_t button_handler; /**< Handler to be called when button is pushed. */
+} app_button_cfg_t;
+
+/**@brief Pin transition direction struct. */
+typedef struct
+{
+ uint32_t high_to_low; /**Pin went from high to low */
+ uint32_t low_to_high; /**Pin went from low to high */
+} pin_transition_t;
+
+/**@brief Macro for initializing the Button Handler module.
+ *
+ * @details It will initialize the specified pins as buttons, and configure the Button Handler
+ * module as a GPIOTE user (but it will not enable button detection). It will also connect
+ * the Button Handler module to the scheduler (if specified).
+ *
+ * @param[in] BUTTONS Array of buttons to be used (type app_button_cfg_t, must be
+ * static!).
+ * @param[in] BUTTON_COUNT Number of buttons.
+ * @param[in] DETECTION_DELAY Delay from a GPIOTE event until a button is reported as pushed.
+ * @param[in] USE_SCHEDULER TRUE if the application is using the event scheduler,
+ * FALSE otherwise.
+ */
+/*lint -emacro(506, APP_BUTTON_INIT) */ /* Suppress "Constant value Boolean */
+#define APP_BUTTON_INIT(BUTTONS, BUTTON_COUNT, DETECTION_DELAY, USE_SCHEDULER) \
+ do \
+ { \
+ uint32_t ERR_CODE = app_button_init((BUTTONS), \
+ (BUTTON_COUNT), \
+ (DETECTION_DELAY), \
+ (USE_SCHEDULER) ? app_button_evt_schedule : NULL); \
+ APP_ERROR_CHECK(ERR_CODE); \
+ } while (0)
+
+/**@brief Function for initializing the Buttons.
+ *
+ * @details This function will initialize the specified pins as buttons, and configure the Button
+ * Handler module as a GPIOTE user (but it will not enable button detection).
+ *
+ * @note Normally initialization should be done using the APP_BUTTON_INIT() macro, as that will take
+ * care of connecting the Buttons module to the scheduler (if specified).
+ *
+ * @note app_button_enable() function must be called in order to enable the button detection.
+ *
+ * @param[in] p_buttons Array of buttons to be used (NOTE: Must be static!).
+ * @param[in] button_count Number of buttons.
+ * @param[in] detection_delay Delay from a GPIOTE event until a button is reported as pushed.
+ * @param[in] evt_schedule_func Function for passing button events to the scheduler. Point to
+ * app_button_evt_schedule() to connect to the scheduler. Set to
+ * NULL to make the Buttons module call the event handler directly
+ * from the delayed button push detection timeout handler.
+ *
+ * @return NRF_SUCCESS on success, otherwise an error code.
+ */
+uint32_t app_button_init(app_button_cfg_t * p_buttons,
+ uint8_t button_count,
+ uint32_t detection_delay,
+ app_button_evt_schedule_func_t evt_schedule_func);
+
+/**@brief Function for enabling button detection.
+ *
+ * @retval NRF_ERROR_INVALID_PARAM GPIOTE has to many users.
+ * @retval NRF_ERROR_INVALID_STATE Button or GPIOTE not initialized.
+ * @retval NRF_SUCCESS Button detection successfully enabled.
+ */
+uint32_t app_button_enable(void);
+
+/**@brief Function for disabling button detection.
+ *
+ * @retval NRF_ERROR_INVALID_PARAM GPIOTE has to many users.
+ * @retval NRF_ERROR_INVALID_STATE Button or GPIOTE not initialized.
+ * @retval NRF_SUCCESS Button detection successfully enabled.
+ */
+uint32_t app_button_disable(void);
+
+/**@brief Function for checking if a button is currently being pushed.
+ *
+ * @param[in] pin_no Button pin to be checked.
+ * @param[out] p_is_pushed Button state.
+ *
+ * @retval NRF_SUCCESS State successfully read.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid pin_no.
+ */
+uint32_t app_button_is_pushed(uint8_t pin_no, bool * p_is_pushed);
+
+
+// Type and functions for connecting the Buttons module to the scheduler:
+
+/**@cond NO_DOXYGEN */
+typedef struct
+{
+ app_button_handler_t button_handler;
+ uint8_t pin_no;
+ uint8_t button_action;
+} app_button_event_t;
+
+static __INLINE void app_button_evt_get(void * p_event_data, uint16_t event_size)
+{
+ app_button_event_t * p_buttons_event = (app_button_event_t *)p_event_data;
+
+ APP_ERROR_CHECK_BOOL(event_size == sizeof(app_button_event_t));
+ p_buttons_event->button_handler(p_buttons_event->pin_no, p_buttons_event->button_action);
+}
+
+static __INLINE uint32_t app_button_evt_schedule(app_button_handler_t button_handler,
+ uint8_t pin_no,
+ uint8_t button_action)
+{
+ app_button_event_t buttons_event;
+
+ buttons_event.button_handler = button_handler;
+ buttons_event.pin_no = pin_no;
+ buttons_event.button_action = button_action;
+
+ return app_sched_event_put(&buttons_event, sizeof(buttons_event), app_button_evt_get);
+}
+/**@endcond */
+
+#endif // APP_BUTTON_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_RBLAB_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_error.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,84 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup app_error Common application error handler
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Common application error handler and macros for utilizing a common error handler.
+ */
+
+#ifndef APP_ERROR_H__
+#define APP_ERROR_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "nrf_error.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@brief Function for error handling, which is called when an error has occurred.
+ *
+ * @param[in] error_code Error code supplied to the handler.
+ * @param[in] line_num Line number where the handler is called.
+ * @param[in] p_file_name Pointer to the file name.
+ */
+void app_error_handler(uint32_t error_code, uint32_t line_num, const uint8_t * p_file_name);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@brief Macro for calling error handler function.
+ *
+ * @param[in] ERR_CODE Error code supplied to the error handler.
+ */
+#define APP_ERROR_HANDLER(ERR_CODE) \
+ do \
+ { \
+ /* app_error_handler((ERR_CODE), __LINE__, (uint8_t*) __FILE__); */ \
+ } while (0)
+
+/**@brief Macro for calling error handler function if supplied error code any other than NRF_SUCCESS.
+ *
+ * @param[in] ERR_CODE Error code supplied to the error handler.
+ */
+#define APP_ERROR_CHECK(ERR_CODE) \
+ do \
+ { \
+ const uint32_t LOCAL_ERR_CODE = (ERR_CODE); \
+ if (LOCAL_ERR_CODE != NRF_SUCCESS) \
+ { \
+ APP_ERROR_HANDLER(LOCAL_ERR_CODE); \
+ } \
+ } while (0)
+
+/**@brief Macro for calling error handler function if supplied boolean value is false.
+ *
+ * @param[in] BOOLEAN_VALUE Boolean value to be evaluated.
+ */
+#define APP_ERROR_CHECK_BOOL(BOOLEAN_VALUE) \
+ do \
+ { \
+ const bool LOCAL_BOOLEAN_VALUE = (BOOLEAN_VALUE); \
+ if (!LOCAL_BOOLEAN_VALUE) \
+ { \
+ APP_ERROR_HANDLER(0); \
+ } \
+ } while (0)
+
+#endif // APP_ERROR_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_RBLAB_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_fifo.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,83 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/**@file
+ *
+ * @defgroup app_fifo FIFO implementation
+ * @{
+ * @ingroup app_common
+ *
+ * @brief FIFO implementation.
+ */
+
+#ifndef APP_FIFO_H__
+#define APP_FIFO_H__
+
+#include <stdint.h>
+#include <stdlib.h>
+#include "nrf_error.h"
+
+/**@brief A FIFO instance structure. Keeps track of which bytes to read and write next.
+ * Also it keeps the information about which memory is allocated for the buffer
+ * and its size. This needs to be initialized by app_fifo_init() before use.
+ */
+typedef struct
+{
+ uint8_t * p_buf; /**< Pointer to FIFO buffer memory. */
+ uint16_t buf_size_mask; /**< Read/write index mask. Also used for size checking. */
+ volatile uint32_t read_pos; /**< Next read position in the FIFO buffer. */
+ volatile uint32_t write_pos; /**< Next write position in the FIFO buffer. */
+} app_fifo_t;
+
+/**@brief Function for initializing the FIFO.
+ *
+ * @param[out] p_fifo FIFO object.
+ * @param[in] p_buf FIFO buffer for storing data. The buffer size has to be a power of two.
+ * @param[in] buf_size Size of the FIFO buffer provided, has to be a power of 2.
+ *
+ * @retval NRF_SUCCESS If initialization was successful.
+ * @retval NRF_ERROR_NULL If a NULL pointer is provided as buffer.
+ * @retval NRF_ERROR_INVALID_LENGTH If size of buffer provided is not a power of two.
+ */
+uint32_t app_fifo_init(app_fifo_t * p_fifo, uint8_t * p_buf, uint16_t buf_size);
+
+/**@brief Function for adding an element to the FIFO.
+ *
+ * @param[in] p_fifo Pointer to the FIFO.
+ * @param[in] byte Data byte to add to the FIFO.
+ *
+ * @retval NRF_SUCCESS If an element has been successfully added to the FIFO.
+ * @retval NRF_ERROR_NO_MEM If the FIFO is full.
+ */
+uint32_t app_fifo_put(app_fifo_t * p_fifo, uint8_t byte);
+
+/**@brief Function for getting the next element from the FIFO.
+ *
+ * @param[in] p_fifo Pointer to the FIFO.
+ * @param[out] p_byte Byte fetched from the FIFO.
+ *
+ * @retval NRF_SUCCESS If an element was returned.
+ * @retval NRF_ERROR_NOT_FOUND If there is no more elements in the queue.
+ */
+uint32_t app_fifo_get(app_fifo_t * p_fifo, uint8_t * p_byte);
+
+/**@brief Function for flushing the FIFO.
+ *
+ * @param[in] p_fifo Pointer to the FIFO.
+ *
+ * @retval NRF_SUCCESS If the FIFO flushed successfully.
+ */
+uint32_t app_fifo_flush(app_fifo_t * p_fifo);
+
+#endif // APP_FIFO_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_RBLAB_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_gpiote.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,226 @@
+/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup app_gpiote GPIOTE Handler
+ * @{
+ * @ingroup app_common
+ *
+ * @brief GPIOTE handler module.
+ *
+ * @details The GPIOTE handler allows several modules ("users") to share the GPIOTE interrupt,
+ * each user defining a set of pins able to generate events to the user.
+ * When a GPIOTE interrupt occurs, the GPIOTE interrupt handler will call the event handler
+ * of each user for which at least one of the pins generated an event.
+ *
+ * The GPIOTE users are responsible for configuring all their corresponding pins, except
+ * the SENSE field, which should be initialized to GPIO_PIN_CNF_SENSE_Disabled.
+ * The SENSE field will be updated by the GPIOTE module when it is enabled or disabled,
+ * and also while it is enabled.
+ *
+ * The module specifies on which pins events should be generated if the pin(s) goes
+ * from low->high or high->low or both directions.
+ *
+ * @note Even if the application is using the @ref app_scheduler, the GPIOTE event handlers will
+ * be called directly from the GPIOTE interrupt handler.
+ *
+ * @warning If multiple users registers for the same pins the behavior for those pins are undefined.
+ */
+
+#ifndef APP_GPIOTE_H__
+#define APP_GPIOTE_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+// #include "nrf.h"
+#include "app_error.h"
+#include "app_util.h"
+
+#ifdef __cpluplus
+extern "C" {
+#endif
+
+#define GPIOTE_USER_NODE_SIZE 20 /**< Size of app_gpiote.gpiote_user_t (only for use inside APP_GPIOTE_BUF_SIZE()). */
+#define NO_OF_PINS 32 /**< Number of GPIO pins on the nRF51 chip. */
+
+/**@brief Compute number of bytes required to hold the GPIOTE data structures.
+ *
+ * @param[in] MAX_USERS Maximum number of GPIOTE users.
+ *
+ * @return Required buffer size (in bytes).
+ */
+#define APP_GPIOTE_BUF_SIZE(MAX_USERS) ((MAX_USERS) * GPIOTE_USER_NODE_SIZE)
+
+typedef uint8_t app_gpiote_user_id_t;
+
+/**@brief GPIOTE event handler type. */
+typedef void (*app_gpiote_event_handler_t)(uint32_t event_pins_low_to_high,
+ uint32_t event_pins_high_to_low);
+
+/**@brief GPIOTE input event handler type. */
+typedef void (*app_gpiote_input_event_handler_t)(void);
+
+/**@brief Macro for initializing the GPIOTE module.
+ *
+ * @details It will handle dimensioning and allocation of the memory buffer required by the module,
+ * making sure that the buffer is correctly aligned.
+ *
+ * @param[in] MAX_USERS Maximum number of GPIOTE users.
+ *
+ * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it
+ * several times as long as it is from the same location, e.g. to do a reinitialization).
+ */
+/*lint -emacro(506, APP_GPIOTE_INIT) */ /* Suppress "Constant value Boolean */
+#define APP_GPIOTE_INIT(MAX_USERS) \
+ do \
+ { \
+ static uint32_t app_gpiote_buf[CEIL_DIV(APP_GPIOTE_BUF_SIZE(MAX_USERS), sizeof(uint32_t))];\
+ uint32_t ERR_CODE = app_gpiote_init((MAX_USERS), app_gpiote_buf); \
+ APP_ERROR_CHECK(ERR_CODE); \
+ } while (0)
+
+/**@brief Function for initializing the GPIOTE module.
+ *
+ * @note Normally initialization should be done using the APP_GPIOTE_INIT() macro, as that will
+ * allocate the buffer needed by the GPIOTE module (including aligning the buffer correctly).
+ *
+ * @param[in] max_users Maximum number of GPIOTE users.
+ * @param[in] p_buffer Pointer to memory buffer for internal use in the app_gpiote
+ * module. The size of the buffer can be computed using the
+ * APP_GPIOTE_BUF_SIZE() macro. The buffer must be aligned to
+ * a 4 byte boundary.
+ *
+ * @retval NRF_SUCCESS Successful initialization.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte
+ * boundary).
+ */
+uint32_t app_gpiote_init(uint8_t max_users, void * p_buffer);
+
+/**@brief Function for registering a GPIOTE user.
+ *
+ * @param[out] p_user_id Id for the new GPIOTE user.
+ * @param[in] pins_low_to_high_mask Mask defining which pins will generate events to this user
+ * when state is changed from low->high.
+ * @param[in] pins_high_to_low_mask Mask defining which pins will generate events to this user
+ * when state is changed from high->low.
+ * @param[in] event_handler Pointer to function to be executed when an event occurs.
+ *
+ * @retval NRF_SUCCESS Successful initialization.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte boundary).
+ * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE
+ * module.
+ * @retval NRF_ERROR_NO_MEM Returned if the application tries to register more users
+ * than defined when the GPIOTE module was initialized in
+ * @ref app_gpiote_init.
+ */
+uint32_t app_gpiote_user_register(app_gpiote_user_id_t * p_user_id,
+ uint32_t pins_low_to_high_mask,
+ uint32_t pins_high_to_low_mask,
+ app_gpiote_event_handler_t event_handler);
+
+/**@brief Function for informing the GPIOTE module that the specified user wants to use the GPIOTE module.
+ *
+ * @param[in] user_id Id of user to enable.
+ *
+ * @retval NRF_SUCCESS On success.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid user_id provided, No a valid user.
+ * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE
+ * module.
+ */
+uint32_t app_gpiote_user_enable(app_gpiote_user_id_t user_id);
+
+/**@brief Function for informing the GPIOTE module that the specified user is done using the GPIOTE module.
+ *
+ * @param[in] user_id Id of user to enable.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid user_id provided, No a valid user.
+ * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE
+ * module.
+ */
+uint32_t app_gpiote_user_disable(app_gpiote_user_id_t user_id);
+
+/**@brief Function for getting the state of the pins which are registered for the specified user.
+ *
+ * @param[in] user_id Id of user to check.
+ * @param[out] p_pins Bit mask corresponding to the pins configured to generate events to
+ * the specified user. All bits corresponding to pins in the state
+ * 'high' will have value '1', all others will have value '0'.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid user_id provided, No a valid user.
+ * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE
+ * module.
+ */
+uint32_t app_gpiote_pins_state_get(app_gpiote_user_id_t user_id, uint32_t * p_pins);
+
+/**@brief Function for registering event handlers for GPIOTE IN events.
+ *
+ * @param[in] channel GPIOTE channel [0..3].
+ * @param[in] pin Pins associated with GPIOTE channel. Changes on following pins will generate events.
+ * @param[in] polarity Specify operation on input that shall trigger IN event.
+ * @param[in] event_handler Event handler invoked on the IN event in the GPIOTE interrupt.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid channel or pin number.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events.
+ */
+uint32_t app_gpiote_input_event_handler_register(const uint8_t channel,
+ const uint32_t pin,
+ const uint32_t polarity,
+ app_gpiote_input_event_handler_t event_handler);
+
+/**@brief Function for unregistering event handlers for GPIOTE IN events.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events.
+ */
+uint32_t app_gpiote_input_event_handler_unregister(const uint8_t channel);
+
+/**@brief Function for registering event handler invoked at the end of a GPIOTE interrupt.
+ *
+ * @param[in] event_handler Event handler invoked at the end of the GPIOTE interrupt.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events.
+ */
+uint32_t app_gpiote_end_irq_event_handler_register(app_gpiote_input_event_handler_t event_handler);
+
+/**@brief Function for unregistering event handler invoked at the end of a GPIOTE interrupt.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events.
+ */
+uint32_t app_gpiote_end_irq_event_handler_unregister(void);
+
+/**@brief Function for enabling interrupts in the GPIOTE driver.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support.
+ */
+uint32_t app_gpiote_enable_interrupts(void);
+
+/**@brief Function for disabling interrupts in the GPIOTE driver.
+ *
+ * @return NRF_SUCCESS On success.
+ * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support.
+ */
+uint32_t app_gpiote_disable_interrupts(void);
+
+#ifdef __cpluplus
+}
+#endif
+
+#endif // APP_GPIOTE_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_RBLAB_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_scheduler.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,134 @@
+/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup app_scheduler Scheduler
+ * @{
+ * @ingroup app_common
+ *
+ * @brief The scheduler is used for transferring execution from the interrupt context to the main
+ * context.
+ *
+ * @details See @ref ble_sdk_apps_seq_diagrams for sequence diagrams illustrating the flow of events
+ * when using the Scheduler.
+ *
+ * @section app_scheduler_req Requirements:
+ *
+ * @subsection main_context_logic Logic in main context:
+ *
+ * - Define an event handler for each type of event expected.
+ * - Initialize the scheduler by calling the APP_SCHED_INIT() macro before entering the
+ * application main loop.
+ * - Call app_sched_execute() from the main loop each time the application wakes up because of an
+ * event (typically when sd_app_evt_wait() returns).
+ *
+ * @subsection int_context_logic Logic in interrupt context:
+ *
+ * - In the interrupt handler, call app_sched_event_put()
+ * with the appropriate data and event handler. This will insert an event into the
+ * scheduler's queue. The app_sched_execute() function will pull this event and call its
+ * handler in the main context.
+ *
+ * For an example usage of the scheduler, please see the implementations of
+ * @ref ble_sdk_app_hids_mouse and @ref ble_sdk_app_hids_keyboard.
+ *
+ * @image html scheduler_working.jpg The high level design of the scheduler
+ */
+
+#ifndef APP_SCHEDULER_H__
+#define APP_SCHEDULER_H__
+
+#include <stdint.h>
+#include "app_error.h"
+
+#define APP_SCHED_EVENT_HEADER_SIZE 8 /**< Size of app_scheduler.event_header_t (only for use inside APP_SCHED_BUF_SIZE()). */
+
+/**@brief Compute number of bytes required to hold the scheduler buffer.
+ *
+ * @param[in] EVENT_SIZE Maximum size of events to be passed through the scheduler.
+ * @param[in] QUEUE_SIZE Number of entries in scheduler queue (i.e. the maximum number of events
+ * that can be scheduled for execution).
+ *
+ * @return Required scheduler buffer size (in bytes).
+ */
+#define APP_SCHED_BUF_SIZE(EVENT_SIZE, QUEUE_SIZE) \
+ (((EVENT_SIZE) + APP_SCHED_EVENT_HEADER_SIZE) * ((QUEUE_SIZE) + 1))
+
+/**@brief Scheduler event handler type. */
+typedef void (*app_sched_event_handler_t)(void * p_event_data, uint16_t event_size);
+
+/**@brief Macro for initializing the event scheduler.
+ *
+ * @details It will also handle dimensioning and allocation of the memory buffer required by the
+ * scheduler, making sure the buffer is correctly aligned.
+ *
+ * @param[in] EVENT_SIZE Maximum size of events to be passed through the scheduler.
+ * @param[in] QUEUE_SIZE Number of entries in scheduler queue (i.e. the maximum number of events
+ * that can be scheduled for execution).
+ *
+ * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it
+ * several times as long as it is from the same location, e.g. to do a reinitialization).
+ */
+#define APP_SCHED_INIT(EVENT_SIZE, QUEUE_SIZE) \
+ do \
+ { \
+ static uint32_t APP_SCHED_BUF[CEIL_DIV(APP_SCHED_BUF_SIZE((EVENT_SIZE), (QUEUE_SIZE)), \
+ sizeof(uint32_t))]; \
+ uint32_t ERR_CODE = app_sched_init((EVENT_SIZE), (QUEUE_SIZE), APP_SCHED_BUF); \
+ APP_ERROR_CHECK(ERR_CODE); \
+ } while (0)
+
+/**@brief Function for initializing the Scheduler.
+ *
+ * @details It must be called before entering the main loop.
+ *
+ * @param[in] max_event_size Maximum size of events to be passed through the scheduler.
+ * @param[in] queue_size Number of entries in scheduler queue (i.e. the maximum number of
+ * events that can be scheduled for execution).
+ * @param[in] p_event_buffer Pointer to memory buffer for holding the scheduler queue. It must
+ * be dimensioned using the APP_SCHED_BUFFER_SIZE() macro. The buffer
+ * must be aligned to a 4 byte boundary.
+ *
+ * @note Normally initialization should be done using the APP_SCHED_INIT() macro, as that will both
+ * allocate the scheduler buffer, and also align the buffer correctly.
+ *
+ * @retval NRF_SUCCESS Successful initialization.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte
+ * boundary).
+ */
+uint32_t app_sched_init(uint16_t max_event_size, uint16_t queue_size, void * p_evt_buffer);
+
+/**@brief Function for executing all scheduled events.
+ *
+ * @details This function must be called from within the main loop. It will execute all events
+ * scheduled since the last time it was called.
+ */
+void app_sched_execute(void);
+
+/**@brief Function for scheduling an event.
+ *
+ * @details Puts an event into the event queue.
+ *
+ * @param[in] p_event_data Pointer to event data to be scheduled.
+ * @param[in] p_event_size Size of event data to be scheduled.
+ * @param[in] handler Event handler to receive the event.
+ *
+ * @return NRF_SUCCESS on success, otherwise an error code.
+ */
+uint32_t app_sched_event_put(void * p_event_data,
+ uint16_t event_size,
+ app_sched_event_handler_t handler);
+
+#endif // APP_SCHEDULER_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_RBLAB_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_timer.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,313 @@
+/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup app_timer Application Timer
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Application timer functionality.
+ *
+ * @details It enables the application to create multiple timer instances based on the RTC1
+ * peripheral. Checking for timeouts and invokation of user timeout handlers is performed
+ * in the RTC1 interrupt handler. List handling is done using a software interrupt (SWI0).
+ * Both interrupt handlers are running in APP_LOW priority level.
+ *
+ * @note When calling app_timer_start() or app_timer_stop(), the timer operation is just queued,
+ * and the software interrupt is triggered. The actual timer start/stop operation is
+ * executed by the SWI0 interrupt handler. Since the SWI0 interrupt is running in APP_LOW,
+ * if the application code calling the timer function is running in APP_LOW or APP_HIGH,
+ * the timer operation will not be performed until the application handler has returned.
+ * This will be the case e.g. when stopping a timer from a timeout handler when not using
+ * the scheduler.
+ *
+ * @details Use the USE_SCHEDULER parameter of the APP_TIMER_INIT() macro to select if the
+ * @ref app_scheduler is to be used or not.
+ *
+ * @note Even if the scheduler is not used, app_timer.h will include app_scheduler.h, so when
+ * compiling, app_scheduler.h must be available in one of the compiler include paths.
+ */
+
+#ifndef APP_TIMER_H__
+#define APP_TIMER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include "app_error.h"
+#include "app_util.h"
+#include "app_scheduler.h"
+#include "compiler_abstraction.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif // #ifdef __cplusplus
+
+#define APP_TIMER_SCHED_EVT_SIZE sizeof(app_timer_event_t) /**< Size of button events being passed through the scheduler (is to be used for computing the maximum size of scheduler events). */
+#define APP_TIMER_CLOCK_FREQ 32768 /**< Clock frequency of the RTC timer used to implement the app timer module. */
+#define APP_TIMER_MIN_TIMEOUT_TICKS 5 /**< Minimum value of the timeout_ticks parameter of app_timer_start(). */
+
+#define APP_TIMER_NODE_SIZE 40 /**< Size of app_timer.timer_node_t (only for use inside APP_TIMER_BUF_SIZE()). */
+#define APP_TIMER_USER_OP_SIZE 24 /**< Size of app_timer.timer_user_op_t (only for use inside APP_TIMER_BUF_SIZE()). */
+#define APP_TIMER_USER_SIZE 8 /**< Size of app_timer.timer_user_t (only for use inside APP_TIMER_BUF_SIZE()). */
+#define APP_TIMER_INT_LEVELS 3 /**< Number of interrupt levels from where timer operations may be initiated (only for use inside APP_TIMER_BUF_SIZE()). */
+
+#define MAX_RTC_COUNTER_VAL 0x00FFFFFF /**< Maximum value of the RTC counter. */
+
+/**@brief Compute number of bytes required to hold the application timer data structures.
+ *
+ * @param[in] MAX_TIMERS Maximum number of timers that can be created at any given time.
+ * @param[in] OP_QUEUE_SIZE Size of queues holding timer operations that are pending execution.
+ * NOTE: Due to the queue implementation, this size must be one more
+ * than the size that is actually needed.
+ *
+ * @return Required application timer buffer size (in bytes).
+ */
+#define APP_TIMER_BUF_SIZE(MAX_TIMERS, OP_QUEUE_SIZE) \
+ ( \
+ ((MAX_TIMERS) * APP_TIMER_NODE_SIZE) \
+ + \
+ ( \
+ APP_TIMER_INT_LEVELS \
+ * \
+ (APP_TIMER_USER_SIZE + ((OP_QUEUE_SIZE) + 1) * APP_TIMER_USER_OP_SIZE) \
+ ) \
+ )
+
+/**@brief Convert milliseconds to timer ticks.
+ *
+ * @note This macro uses 64 bit integer arithmetic, but as long as the macro parameters are
+ * constants (i.e. defines), the computation will be done by the preprocessor.
+ *
+ * @param[in] MS Milliseconds.
+ * @param[in] PRESCALER Value of the RTC1 PRESCALER register (must be the same value that was
+ * passed to APP_TIMER_INIT()).
+ *
+ * @note When using this macro, it is the responsibility of the developer to ensure that the
+ * values provided as input result in an output value that is supported by the
+ * @ref app_timer_start function. For example, when the ticks for 1 ms is needed, the
+ * maximum possible value of PRESCALER must be 6, when @ref APP_TIMER_CLOCK_FREQ is 32768.
+ * This will result in a ticks value as 5. Any higher value for PRESCALER will result in a
+ * ticks value that is not supported by this module.
+ *
+ * @return Number of timer ticks.
+ */
+#define APP_TIMER_TICKS(MS, PRESCALER)\
+ ((uint32_t)ROUNDED_DIV((MS) * (uint64_t)APP_TIMER_CLOCK_FREQ, ((PRESCALER) + 1) * 1000))
+
+/**@brief Timer id type. */
+typedef uint32_t app_timer_id_t;
+
+#define TIMER_NULL ((app_timer_id_t)(0 - 1)) /**< Invalid timer id. */
+
+/**@brief Application timeout handler type. */
+typedef void (*app_timer_timeout_handler_t)(void * p_context);
+
+/**@brief Type of function for passing events from the timer module to the scheduler. */
+typedef uint32_t (*app_timer_evt_schedule_func_t) (app_timer_timeout_handler_t timeout_handler,
+ void * p_context);
+
+/**@brief Timer modes. */
+typedef enum
+{
+ APP_TIMER_MODE_SINGLE_SHOT, /**< The timer will expire only once. */
+ APP_TIMER_MODE_REPEATED /**< The timer will restart each time it expires. */
+} app_timer_mode_t;
+
+/**@brief Macro for initializing the application timer module.
+ *
+ * @details It will handle dimensioning and allocation of the memory buffer required by the timer,
+ * making sure that the buffer is correctly aligned. It will also connect the timer module
+ * to the scheduler (if specified).
+ *
+ * @note This module assumes that the LFCLK is already running. If it isn't, the module will
+ * be non-functional, since the RTC will not run. If you don't use a softdevice, you'll
+ * have to start the LFCLK manually. See the rtc_example's \ref lfclk_config() function
+ * for an example of how to do this. If you use a softdevice, the LFCLK is started on
+ * softdevice init.
+ *
+ *
+ * @param[in] PRESCALER Value of the RTC1 PRESCALER register. This will decide the
+ * timer tick rate. Set to 0 for no prescaling.
+ * @param[in] MAX_TIMERS Maximum number of timers that can be created at any given time.
+ * @param[in] OP_QUEUES_SIZE Size of queues holding timer operations that are pending execution.
+ * @param[in] USE_SCHEDULER TRUE if the application is using the event scheduler,
+ * FALSE otherwise.
+ *
+ * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it
+ * several times as long as it is from the same location, e.g. to do a reinitialization).
+ */
+/*lint -emacro(506, APP_TIMER_INIT) */ /* Suppress "Constant value Boolean */
+#define APP_TIMER_INIT(PRESCALER, MAX_TIMERS, OP_QUEUES_SIZE, USE_SCHEDULER) \
+ do \
+ { \
+ static uint32_t APP_TIMER_BUF[CEIL_DIV(APP_TIMER_BUF_SIZE((MAX_TIMERS), \
+ (OP_QUEUES_SIZE) + 1), \
+ sizeof(uint32_t))]; \
+ uint32_t ERR_CODE = app_timer_init((PRESCALER), \
+ (MAX_TIMERS), \
+ (OP_QUEUES_SIZE) + 1, \
+ APP_TIMER_BUF, \
+ (USE_SCHEDULER) ? app_timer_evt_schedule : NULL); \
+ APP_ERROR_CHECK(ERR_CODE); \
+ } while (0)
+
+/**@brief Function for initializing the timer module.
+ *
+ * @note Normally initialization should be done using the APP_TIMER_INIT() macro, as that will both
+ * allocate the buffers needed by the timer module (including aligning the buffers correctly,
+ * and also take care of connecting the timer module to the scheduler (if specified).
+ *
+ * @param[in] prescaler Value of the RTC1 PRESCALER register. Set to 0 for no prescaling.
+ * @param[in] max_timers Maximum number of timers that can be created at any given time.
+ * @param[in] op_queues_size Size of queues holding timer operations that are pending
+ * execution. NOTE: Due to the queue implementation, this size must
+ * be one more than the size that is actually needed.
+ * @param[in] p_buffer Pointer to memory buffer for internal use in the app_timer
+ * module. The size of the buffer can be computed using the
+ * APP_TIMER_BUF_SIZE() macro. The buffer must be aligned to a
+ * 4 byte boundary.
+ * @param[in] evt_schedule_func Function for passing timeout events to the scheduler. Point to
+ * app_timer_evt_schedule() to connect to the scheduler. Set to NULL
+ * to make the timer module call the timeout handler directly from
+ * the timer interrupt handler.
+ *
+ * @retval NRF_SUCCESS Successful initialization.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte
+ * boundary or NULL).
+ */
+uint32_t app_timer_init(uint32_t prescaler,
+ uint8_t max_timers,
+ uint8_t op_queues_size,
+ void * p_buffer,
+ app_timer_evt_schedule_func_t evt_schedule_func);
+
+/**@brief Function for creating a timer instance.
+ *
+ * @param[out] p_timer_id Id of the newly created timer.
+ * @param[in] mode Timer mode.
+ * @param[in] timeout_handler Function to be executed when the timer expires.
+ *
+ * @retval NRF_SUCCESS Timer was successfully created.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter.
+ * @retval NRF_ERROR_INVALID_STATE Application timer module has not been initialized.
+ * @retval NRF_ERROR_NO_MEM Maximum number of timers has already been reached.
+ *
+ * @note This function does the timer allocation in the caller's context. It is also not protected
+ * by a critical region. Therefore care must be taken not to call it from several interrupt
+ * levels simultaneously.
+ */
+uint32_t app_timer_create(app_timer_id_t * p_timer_id,
+ app_timer_mode_t mode,
+ app_timer_timeout_handler_t timeout_handler);
+
+/**@brief Function for starting a timer.
+ *
+ * @param[in] timer_id Id of timer to start.
+ * @param[in] timeout_ticks Number of ticks (of RTC1, including prescaling) to timeout event
+ * (minimum 5 ticks).
+ * @param[in] p_context General purpose pointer. Will be passed to the timeout handler when
+ * the timer expires.
+ *
+ * @retval NRF_SUCCESS Timer was successfully started.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter.
+ * @retval NRF_ERROR_INVALID_STATE Application timer module has not been initialized, or timer
+ * has not been created.
+ * @retval NRF_ERROR_NO_MEM Timer operations queue was full.
+ *
+ * @note The minimum timeout_ticks value is 5.
+ * @note For multiple active timers, timeouts occurring in close proximity to each other (in the
+ * range of 1 to 3 ticks) will have a positive jitter of maximum 3 ticks.
+ * @note When calling this method on a timer which is already running, the second start operation
+ * will be ignored.
+ */
+uint32_t app_timer_start(app_timer_id_t timer_id, uint32_t timeout_ticks, void * p_context);
+
+/**@brief Function for stopping the specified timer.
+ *
+ * @param[in] timer_id Id of timer to stop.
+ *
+ * @retval NRF_SUCCESS Timer was successfully stopped.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid parameter.
+ * @retval NRF_ERROR_INVALID_STATE Application timer module has not been initialized, or timer
+ * has not been created.
+ * @retval NRF_ERROR_NO_MEM Timer operations queue was full.
+ */
+uint32_t app_timer_stop(app_timer_id_t timer_id);
+
+/**@brief Function for stopping all running timers.
+ *
+ * @retval NRF_SUCCESS All timers were successfully stopped.
+ * @retval NRF_ERROR_INVALID_STATE Application timer module has not been initialized.
+ * @retval NRF_ERROR_NO_MEM Timer operations queue was full.
+ */
+uint32_t app_timer_stop_all(void);
+
+/**@brief Function for returning the current value of the RTC1 counter. The
+ * value includes overflow bits to extend the range to 64-bits.
+ *
+ * @param[out] p_ticks Current value of the RTC1 counter.
+ *
+ * @retval NRF_SUCCESS Counter was successfully read.
+ */
+uint32_t app_timer_cnt_get(uint64_t * p_ticks);
+
+/**@brief Function for computing the difference between two RTC1 counter values.
+ *
+ * @param[in] ticks_to Value returned by app_timer_cnt_get().
+ * @param[in] ticks_from Value returned by app_timer_cnt_get().
+ * @param[out] p_ticks_diff Number of ticks from ticks_from to ticks_to.
+ *
+ * @retval NRF_SUCCESS Counter difference was successfully computed.
+ */
+uint32_t app_timer_cnt_diff_compute(uint32_t ticks_to,
+ uint32_t ticks_from,
+ uint32_t * p_ticks_diff);
+
+
+// Type and functions for connecting the timer to the scheduler:
+
+/**@cond NO_DOXYGEN */
+typedef struct
+{
+ app_timer_timeout_handler_t timeout_handler;
+ void * p_context;
+} app_timer_event_t;
+
+static __INLINE void app_timer_evt_get(void * p_event_data, uint16_t event_size)
+{
+ app_timer_event_t * p_timer_event = (app_timer_event_t *)p_event_data;
+
+ APP_ERROR_CHECK_BOOL(event_size == sizeof(app_timer_event_t));
+ p_timer_event->timeout_handler(p_timer_event->p_context);
+}
+
+static __INLINE uint32_t app_timer_evt_schedule(app_timer_timeout_handler_t timeout_handler,
+ void * p_context)
+{
+ app_timer_event_t timer_event;
+
+ timer_event.timeout_handler = timeout_handler;
+ timer_event.p_context = p_context;
+
+ return app_sched_event_put(&timer_event, sizeof(timer_event), app_timer_evt_get);
+}
+/**@endcond */
+
+#ifdef __cplusplus
+}
+#endif // #ifdef __cplusplus
+
+#endif // APP_TIMER_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_RBLAB_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_trace.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,55 @@
+#ifndef __DEBUG_H_
+#define __DEBUG_H_
+
+#include <stdint.h>
+#include <stdio.h>
+
+/**
+ * @defgroup app_trace Debug Logger
+ * @ingroup app_common
+ * @{
+ * @brief Enables debug logs/ trace over UART.
+ * @details Enables debug logs/ trace over UART. Tracing is enabled only if
+ * ENABLE_DEBUG_LOG_SUPPORT is defined in the project.
+ */
+#ifdef ENABLE_DEBUG_LOG_SUPPORT
+/**
+ * @brief Module Initialization.
+ *
+ * @details Initializes the module to use UART as trace output.
+ *
+ * @warning This function will configure UART using default board configuration (described in @ref nrf51_setups).
+ * Do not call this function if UART is configured from a higher level in the application.
+ */
+void app_trace_init(void);
+
+/**
+ * @brief Log debug messages.
+ *
+ * @details This API logs messages over UART. The module must be initialized before using this API.
+ *
+ * @note Though this is currently a macro, it should be used used and treated as function.
+ */
+#define app_trace_log printf
+
+/**
+ * @brief Dump auxiliary byte buffer to the debug trace.
+ *
+ * @details This API logs messages over UART. The module must be initialized before using this API.
+ *
+ * @param[in] p_buffer Buffer to be dumped on the debug trace.
+ * @param[in] len Size of the buffer.
+ */
+void app_trace_dump(uint8_t * p_buffer, uint32_t len);
+
+#else // ENABLE_DEBUG_LOG_SUPPORT
+
+#define app_trace_init(...)
+#define app_trace_log(...)
+#define app_trace_dump(...)
+
+#endif // ENABLE_DEBUG_LOG_SUPPORT
+
+/** @} */
+
+#endif //__DEBUG_H_
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_RBLAB_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_uart.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,286 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/**@file
+ *
+ * @defgroup app_uart UART module
+ * @{
+ * @ingroup app_common
+ *
+ * @brief UART module interface.
+ */
+
+#ifndef APP_UART_H__
+#define APP_UART_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "app_util_platform.h"
+
+#define UART_PIN_DISCONNECTED 0xFFFFFFFF /**< Value indicating that no pin is connected to this UART register. */
+
+/**@brief UART Flow Control modes for the peripheral.
+ */
+typedef enum
+{
+ APP_UART_FLOW_CONTROL_DISABLED, /**< UART Hw Flow Control is disabled. */
+ APP_UART_FLOW_CONTROL_ENABLED, /**< Standard UART Hw Flow Control is enabled. */
+ APP_UART_FLOW_CONTROL_LOW_POWER /**< Specialized UART Hw Flow Control is used. The Low Power setting allows the nRF51 to Power Off the UART module when CTS is in-active, and re-enabling the UART when the CTS signal becomes active. This allows the nRF51 to safe power by only using the UART module when it is needed by the remote site. */
+} app_uart_flow_control_t;
+
+/**@brief UART communication structure holding configuration settings for the peripheral.
+ */
+typedef struct
+{
+ uint8_t rx_pin_no; /**< RX pin number. */
+ uint8_t tx_pin_no; /**< TX pin number. */
+ uint8_t rts_pin_no; /**< RTS pin number, only used if flow control is enabled. */
+ uint8_t cts_pin_no; /**< CTS pin number, only used if flow control is enabled. */
+ app_uart_flow_control_t flow_control; /**< Flow control setting, if flow control is used, the system will use low power UART mode, based on CTS signal. */
+ bool use_parity; /**< Even parity if TRUE, no parity if FALSE. */
+ uint32_t baud_rate; /**< Baud rate configuration. */
+} app_uart_comm_params_t;
+
+/**@brief UART buffer for transmitting/receiving data.
+ */
+typedef struct
+{
+ uint8_t * rx_buf; /**< Pointer to the RX buffer. */
+ uint32_t rx_buf_size; /**< Size of the RX buffer. */
+ uint8_t * tx_buf; /**< Pointer to the TX buffer. */
+ uint32_t tx_buf_size; /**< Size of the TX buffer. */
+} app_uart_buffers_t;
+
+/**@brief Enumeration describing current state of the UART.
+ *
+ * @details The connection state can be fetched by the application using the function call
+ * @ref app_uart_get_connection_state.
+ * When hardware flow control is used
+ * - APP_UART_CONNECTED: Communication is ongoing.
+ * - APP_UART_DISCONNECTED: No communication is ongoing.
+ *
+ * When no hardware flow control is used
+ * - APP_UART_CONNECTED: Always returned as bytes can always be received/transmitted.
+ */
+typedef enum
+{
+ APP_UART_DISCONNECTED, /**< State indicating that the UART is disconnected and cannot receive or transmit bytes. */
+ APP_UART_CONNECTED /**< State indicating that the UART is connected and ready to receive or transmit bytes. If flow control is disabled, the state will always be connected. */
+} app_uart_connection_state_t;
+
+/**@brief Enumeration which defines events used by the UART module upon data reception or error.
+ *
+ * @details The event type is used to indicate the type of additional information in the event
+ * @ref app_uart_evt_t.
+ */
+typedef enum
+{
+ APP_UART_DATA_READY, /**< An event indicating that UART data has been received. The data is available in the FIFO and can be fetched using @ref app_uart_get. */
+ APP_UART_FIFO_ERROR, /**< An error in the FIFO module used by the app_uart module has occured. The FIFO error code is stored in app_uart_evt_t.data.error_code field. */
+ APP_UART_COMMUNICATION_ERROR, /**< An communication error has occured during reception. The error is stored in app_uart_evt_t.data.error_communication field. */
+ APP_UART_TX_EMPTY, /**< An event indicating that UART has completed transmission of all available data in the TX FIFO. */
+ APP_UART_DATA, /**< An event indicating that UART data has been received, and data is present in data field. This event is only used when no FIFO is configured. */
+} app_uart_evt_type_t;
+
+/**@brief Struct containing events from the UART module.
+ *
+ * @details The app_uart_evt_t is used to notify the application of asynchronous events when data
+ * are received on the UART peripheral or in case an error occured during data reception.
+ */
+typedef struct
+{
+ app_uart_evt_type_t evt_type; /**< Type of event. */
+ union
+ {
+ uint32_t error_communication; /**< Field used if evt_type is: APP_UART_COMMUNICATION_ERROR. This field contains the value in the ERRORSRC register for the UART peripheral. The UART_ERRORSRC_x defines from @ref nrf51_bitfields.h can be used to parse the error code. See also the nRF51 Series Reference Manual for specification. */
+ uint32_t error_code; /**< Field used if evt_type is: NRF_ERROR_x. Additional status/error code if the error event type is APP_UART_FIFO_ERROR. This error code refer to errors defined in nrf_error.h. */
+ uint8_t value; /**< Field used if evt_type is: NRF_ERROR_x. Additional status/error code if the error event type is APP_UART_FIFO_ERROR. This error code refer to errors defined in nrf_error.h. */
+ } data;
+} app_uart_evt_t;
+
+/**@brief Function for handling app_uart event callback.
+ *
+ * @details Upon an event in the app_uart module this callback function will be called to notify
+ * the applicatioon about the event.
+ *
+ * @param[in] p_app_uart_event Pointer to UART event.
+ */
+
+
+typedef void (* app_uart_event_handler_t) (app_uart_evt_t * p_app_uart_event);
+
+/**@brief Macro for safe initialization of the UART module in a single user instance when using
+ * a FIFO together with UART.
+ *
+ * @param[in] P_COMM_PARAMS Pointer to a UART communication structure: app_uart_comm_params_t
+ * @param[in] RX_BUF_SIZE Size of desired RX buffer, must be a power of 2 or ZERO (No FIFO).
+ * @param[in] TX_BUF_SIZE Size of desired TX buffer, must be a power of 2 or ZERO (No FIFO).
+ * @param[in] EVENT_HANDLER Event handler function to be called when an event occurs in the
+ * UART module.
+ * @param[in] IRQ_PRIO IRQ priority, app_irq_priority_t, for the UART module irq handler.
+ * @param[out] ERR_CODE The return value of the UART initialization function will be
+ * written to this parameter.
+ *
+ * @note Since this macro allocates a buffer and registers the module as a GPIOTE user when flow
+ * control is enabled, it must only be called once.
+ */
+#define APP_UART_FIFO_INIT(P_COMM_PARAMS, RX_BUF_SIZE, TX_BUF_SIZE, EVT_HANDLER, IRQ_PRIO, ERR_CODE) \
+ do \
+ { \
+ uint16_t APP_UART_UID = 0; \
+ app_uart_buffers_t buffers; \
+ static uint8_t rx_buf[RX_BUF_SIZE]; \
+ static uint8_t tx_buf[TX_BUF_SIZE]; \
+ \
+ buffers.rx_buf = rx_buf; \
+ buffers.rx_buf_size = sizeof (rx_buf); \
+ buffers.tx_buf = tx_buf; \
+ buffers.tx_buf_size = sizeof (tx_buf); \
+ ERR_CODE = app_uart_init(P_COMM_PARAMS, &buffers, EVT_HANDLER, IRQ_PRIO, &APP_UART_UID); \
+ } while (0)
+
+/**@brief Macro for safe initialization of the UART module in a single user instance.
+ *
+ * @param[in] P_COMM_PARAMS Pointer to a UART communication structure: app_uart_comm_params_t
+ * @param[in] EVENT_HANDLER Event handler function to be called when an event occurs in the
+ * UART module.
+ * @param[in] IRQ_PRIO IRQ priority, app_irq_priority_t, for the UART module irq handler.
+ * @param[out] ERR_CODE The return value of the UART initialization function will be
+ * written to this parameter.
+ *
+ * @note Since this macro allocates registers the module as a GPIOTE user when flow control is
+ * enabled, it must only be called once.
+ */
+#define APP_UART_INIT(P_COMM_PARAMS, EVT_HANDLER, IRQ_PRIO, ERR_CODE) \
+ do \
+ { \
+ uint16_t APP_UART_UID = 0; \
+ ERR_CODE = app_uart_init(P_COMM_PARAMS, NULL, EVT_HANDLER, IRQ_PRIO, &APP_UART_UID); \
+ } while (0)
+
+/**@brief Function for initializing the UART module. Use this initialization when several instances of the UART
+ * module are needed.
+ *
+ * @details This initialization will return a UART user id for the caller. The UART user id must be
+ * used upon re-initialization of the UART or closing of the module for the user.
+ * If single instance usage is needed, the APP_UART_INIT() macro should be used instead.
+ *
+ * @note Normally single instance initialization should be done using the APP_UART_INIT() or
+ * APP_UART_INIT_FIFO() macro depending on whether the FIFO should be used by the UART, as
+ * that will allocate the buffers needed by the UART module (including aligning the buffer
+ * correctly).
+
+ * @param[in] p_comm_params Pin and communication parameters.
+ * @param[in] p_buffers RX and TX buffers, NULL is FIFO is not used.
+ * @param[in] error_handler Function to be called in case of an error.
+ * @param[in] app_irq_priority Interrupt priority level.
+ * @param[in,out] p_uart_uid User id for the UART module. The p_uart_uid must be used if
+ * re-initialization and/or closing of the UART module is needed.
+ * If the value pointed to by p_uart_uid is zero, this is
+ * considdered a first time initialization. Otherwise this is
+ * considered a re-initialization for the user with id *p_uart_uid.
+ *
+ * @retval NRF_SUCCESS If successful initialization.
+ * @retval NRF_ERROR_INVALID_LENGTH If a provided buffer is not a power of two.
+ * @retval NRF_ERROR_NULL If one of the provided buffers is a NULL pointer.
+ *
+ * Those errors are propagated by the UART module to the caller upon registration when Hardware Flow
+ * Control is enabled. When Hardware Flow Control is not used, those errors cannot occur.
+ * @retval NRF_ERROR_INVALID_STATE The GPIOTE module is not in a valid state when registering
+ * the UART module as a user.
+ * @retval NRF_ERROR_INVALID_PARAM The UART module provides an invalid callback function when
+ * registering the UART module as a user.
+ * Or the value pointed to by *p_uart_uid is not a valid
+ * GPIOTE number.
+ * @retval NRF_ERROR_NO_MEM GPIOTE module has reached the maximum number of users.
+ */
+uint32_t app_uart_init(const app_uart_comm_params_t * p_comm_params,
+ app_uart_buffers_t * p_buffers,
+ app_uart_event_handler_t error_handler,
+ app_irq_priority_t irq_priority,
+ uint16_t * p_uart_uid);
+
+/**@brief Function for getting a byte from the UART.
+ *
+ * @details This function will get the next byte from the RX buffer. If the RX buffer is empty
+ * an error code will be returned and the app_uart module will generate an event upon
+ * reception of the first byte which is added to the RX buffer.
+ *
+ * @param[out] p_byte Pointer to an address where next byte received on the UART will be copied.
+ *
+ * @retval NRF_SUCCESS If a byte has been received and pushed to the pointer provided.
+ * @retval NRF_ERROR_NOT_FOUND If no byte is available in the RX buffer of the app_uart module.
+ */
+uint32_t app_uart_get(uint8_t * p_byte);
+
+/**@brief Function for putting a byte on the UART.
+ *
+ * @details This call is non-blocking.
+ *
+ * @param[in] byte Byte to be transmitted on the UART.
+ *
+ * @retval NRF_SUCCESS If the byte was succesfully put on the TX buffer for transmission.
+ * @retval NRF_ERROR_NO_MEM If no more space is available in the TX buffer.
+ * NRF_ERROR_NO_MEM may occur if flow control is enabled and CTS signal
+ * is high for a long period and the buffer fills up.
+ */
+uint32_t app_uart_put(uint8_t byte);
+
+/**@brief Function for getting the current state of the UART.
+ *
+ * @details If flow control is disabled, the state is assumed to always be APP_UART_CONNECTED.
+ *
+ * When using flow control the state will be controlled by the CTS. If CTS is set active
+ * by the remote side, or the app_uart module is in the process of transmitting a byte,
+ * app_uart is in APP_UART_CONNECTED state. If CTS is set inactive by remote side app_uart
+ * will not get into APP_UART_DISCONNECTED state until the last byte in the TXD register
+ * is fully transmitted.
+ *
+ * Internal states in the state machine are mapped to the general connected/disconnected
+ * states in the following ways:
+ *
+ * - UART_ON = CONNECTED
+ * - UART_READY = CONNECTED
+ * - UART_WAIT = CONNECTED
+ * - UART_OFF = DISCONNECTED.
+ *
+ * @param[out] p_connection_state Current connection state of the UART.
+ *
+ * @retval NRF_SUCCESS The connection state was succesfully retrieved.
+ */
+uint32_t app_uart_get_connection_state(app_uart_connection_state_t * p_connection_state);
+
+/**@brief Function for flushing the RX and TX buffers (Only valid if FIFO is used).
+ * This function does nothing if FIFO is not used.
+ *
+ * @retval NRF_SUCCESS Flushing completed (Current implementation will always succeed).
+ */
+uint32_t app_uart_flush(void);
+
+/**@brief Function for closing the UART module.
+ *
+ * @details This function will close any on-going UART transmissions and disable itself in the
+ * GPTIO module.
+ *
+ * @param[in] app_uart_uid User id for the UART module. The app_uart_uid must be identical to the
+ * UART id returned on initialization and which is currently in use.
+
+ * @retval NRF_SUCCESS If successfully closed.
+ * @retval NRF_ERROR_INVALID_PARAM If an invalid user id is provided or the user id differs from
+ * the current active user.
+ */
+uint32_t app_uart_close(uint16_t app_uart_id);
+
+
+#endif //APP_UART_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_RBLAB_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_util.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,232 @@
+/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup app_util Utility Functions and Definitions
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Various types and definitions available to all applications.
+ */
+
+#ifndef APP_UTIL_H__
+#define APP_UTIL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "compiler_abstraction.h"
+
+enum
+{
+ UNIT_0_625_MS = 625, /**< Number of microseconds in 0.625 milliseconds. */
+ UNIT_1_25_MS = 1250, /**< Number of microseconds in 1.25 milliseconds. */
+ UNIT_10_MS = 10000 /**< Number of microseconds in 10 milliseconds. */
+};
+
+/**@brief Macro for doing static (i.e. compile time) assertion.
+ *
+ * @note If the assertion fails when compiling using Keil, the compiler will report error message
+ * "error: #94: the size of an array must be greater than zero" (while gcc will list the
+ * symbol static_assert_failed, making the error message more readable).
+ * If the supplied expression can not be evaluated at compile time, Keil will report
+ * "error: #28: expression must have a constant value".
+ *
+ * @note The macro is intentionally implemented not using do while(0), allowing it to be used
+ * outside function blocks (e.g. close to global type- and variable declarations).
+ * If used in a code block, it must be used before any executable code in this block.
+ *
+ * @param[in] EXPR Constant expression to be verified.
+ */
+
+#if defined(__GNUC__)
+#define STATIC_ASSERT(EXPR) typedef char __attribute__((unused)) static_assert_failed[(EXPR) ? 1 : -1]
+#else
+#define STATIC_ASSERT(EXPR) typedef char static_assert_failed[(EXPR) ? 1 : -1]
+#endif
+
+
+/**@brief type for holding an encoded (i.e. little endian) 16 bit unsigned integer. */
+typedef uint8_t uint16_le_t[2];
+
+/**@brief type for holding an encoded (i.e. little endian) 32 bit unsigned integer. */
+typedef uint8_t uint32_le_t[4];
+
+/**@brief Byte array type. */
+typedef struct
+{
+ uint16_t size; /**< Number of array entries. */
+ uint8_t * p_data; /**< Pointer to array entries. */
+} uint8_array_t;
+
+/**@brief Perform rounded integer division (as opposed to truncating the result).
+ *
+ * @param[in] A Numerator.
+ * @param[in] B Denominator.
+ *
+ * @return Rounded (integer) result of dividing A by B.
+ */
+#define ROUNDED_DIV(A, B) (((A) + ((B) / 2)) / (B))
+
+/**@brief Check if the integer provided is a power of two.
+ *
+ * @param[in] A Number to be tested.
+ *
+ * @return true if value is power of two.
+ * @return false if value not power of two.
+ */
+#define IS_POWER_OF_TWO(A) ( ((A) != 0) && ((((A) - 1) & (A)) == 0) )
+
+/**@brief To convert ticks to millisecond
+ * @param[in] time Number of millseconds that needs to be converted.
+ * @param[in] resolution Units to be converted.
+ */
+#define MSEC_TO_UNITS(TIME, RESOLUTION) (((TIME) * 1000) / (RESOLUTION))
+
+
+/**@brief Perform integer division, making sure the result is rounded up.
+ *
+ * @details One typical use for this is to compute the number of objects with size B is needed to
+ * hold A number of bytes.
+ *
+ * @param[in] A Numerator.
+ * @param[in] B Denominator.
+ *
+ * @return Integer result of dividing A by B, rounded up.
+ */
+#define CEIL_DIV(A, B) \
+ /*lint -save -e573 */ \
+ ((((A) - 1) / (B)) + 1) \
+ /*lint -restore */
+
+/**@brief Function for encoding a uint16 value.
+ *
+ * @param[in] value Value to be encoded.
+ * @param[out] p_encoded_data Buffer where the encoded data is to be written.
+ *
+ * @return Number of bytes written.
+ */
+static __INLINE uint8_t uint16_encode(uint16_t value, uint8_t * p_encoded_data)
+{
+ p_encoded_data[0] = (uint8_t) ((value & 0x00FF) >> 0);
+ p_encoded_data[1] = (uint8_t) ((value & 0xFF00) >> 8);
+ return sizeof(uint16_t);
+}
+
+/**@brief Function for encoding a uint32 value.
+ *
+ * @param[in] value Value to be encoded.
+ * @param[out] p_encoded_data Buffer where the encoded data is to be written.
+ *
+ * @return Number of bytes written.
+ */
+static __INLINE uint8_t uint32_encode(uint32_t value, uint8_t * p_encoded_data)
+{
+ p_encoded_data[0] = (uint8_t) ((value & 0x000000FF) >> 0);
+ p_encoded_data[1] = (uint8_t) ((value & 0x0000FF00) >> 8);
+ p_encoded_data[2] = (uint8_t) ((value & 0x00FF0000) >> 16);
+ p_encoded_data[3] = (uint8_t) ((value & 0xFF000000) >> 24);
+ return sizeof(uint32_t);
+}
+
+/**@brief Function for decoding a uint16 value.
+ *
+ * @param[in] p_encoded_data Buffer where the encoded data is stored.
+ *
+ * @return Decoded value.
+ */
+static __INLINE uint16_t uint16_decode(const uint8_t * p_encoded_data)
+{
+ return ( (((uint16_t)((uint8_t *)p_encoded_data)[0])) |
+ (((uint16_t)((uint8_t *)p_encoded_data)[1]) << 8 ));
+}
+
+/**@brief Function for decoding a uint32 value.
+ *
+ * @param[in] p_encoded_data Buffer where the encoded data is stored.
+ *
+ * @return Decoded value.
+ */
+static __INLINE uint32_t uint32_decode(const uint8_t * p_encoded_data)
+{
+ return ( (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0) |
+ (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8) |
+ (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16) |
+ (((uint32_t)((uint8_t *)p_encoded_data)[3]) << 24 ));
+}
+
+/** @brief Function for converting the input voltage (in milli volts) into percentage of 3.0 Volts.
+ *
+ * @details The calculation is based on a linearized version of the battery's discharge
+ * curve. 3.0V returns 100% battery level. The limit for power failure is 2.1V and
+ * is considered to be the lower boundary.
+ *
+ * The discharge curve for CR2032 is non-linear. In this model it is split into
+ * 4 linear sections:
+ * - Section 1: 3.0V - 2.9V = 100% - 42% (58% drop on 100 mV)
+ * - Section 2: 2.9V - 2.74V = 42% - 18% (24% drop on 160 mV)
+ * - Section 3: 2.74V - 2.44V = 18% - 6% (12% drop on 300 mV)
+ * - Section 4: 2.44V - 2.1V = 6% - 0% (6% drop on 340 mV)
+ *
+ * These numbers are by no means accurate. Temperature and
+ * load in the actual application is not accounted for!
+ *
+ * @param[in] mvolts The voltage in mV
+ *
+ * @return Battery level in percent.
+*/
+static __INLINE uint8_t battery_level_in_percent(const uint16_t mvolts)
+{
+ uint8_t battery_level;
+
+ if (mvolts >= 3000)
+ {
+ battery_level = 100;
+ }
+ else if (mvolts > 2900)
+ {
+ battery_level = 100 - ((3000 - mvolts) * 58) / 100;
+ }
+ else if (mvolts > 2740)
+ {
+ battery_level = 42 - ((2900 - mvolts) * 24) / 160;
+ }
+ else if (mvolts > 2440)
+ {
+ battery_level = 18 - ((2740 - mvolts) * 12) / 300;
+ }
+ else if (mvolts > 2100)
+ {
+ battery_level = 6 - ((2440 - mvolts) * 6) / 340;
+ }
+ else
+ {
+ battery_level = 0;
+ }
+
+ return battery_level;
+}
+
+/**@brief Function for checking if a pointer value is aligned to a 4 byte boundary.
+ *
+ * @param[in] p Pointer value to be checked.
+ *
+ * @return TRUE if pointer is aligned to a 4 byte boundary, FALSE otherwise.
+ */
+static __INLINE bool is_word_aligned(void * p)
+{
+ return (((uintptr_t)p & 0x03) == 0);
+}
+
+#endif // APP_UTIL_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_RBLAB_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/crc16.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,52 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup crc_compute CRC compute
+ * @{
+ * @ingroup hci_transport
+ *
+ * @brief This module implements the CRC-16 calculation in the blocks.
+ */
+
+#ifndef CRC16_H__
+#define CRC16_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@brief Function for calculating CRC-16 in blocks.
+ *
+ * Feed each consecutive data block into this function, along with the current value of p_crc as
+ * returned by the previous call of this function. The first call of this function should pass NULL
+ * as the initial value of the crc in p_crc.
+ *
+ * @param[in] p_data The input data block for computation.
+ * @param[in] size The size of the input data block in bytes.
+ * @param[in] p_crc The previous calculated CRC-16 value or NULL if first call.
+ *
+ * @return The updated CRC-16 value, based on the input supplied.
+ */
+uint16_t crc16_compute(const uint8_t * p_data, uint32_t size, const uint16_t * p_crc);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif // CRC16_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_RBLAB_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hal_transport.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,227 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/**@file
+ *
+ * @defgroup hci_transport HCI Transport
+ * @{
+ * @ingroup app_common
+ *
+ * @brief HCI transport module implementation.
+ *
+ * This module implements certain specific features from the three-wire UART transport layer,
+ * defined by the Bluetooth specification version 4.0 [Vol 4] part D.
+ *
+ * \par Features supported
+ * - Transmission and reception of Vendor Specific HCI packet type application packets.
+ * - Transmission and reception of reliable packets: defined by chapter 6 of the specification.
+ *
+ * \par Features not supported
+ * - Link establishment procedure: defined by chapter 8 of the specification.
+ * - Low power: defined by chapter 9 of the specification.
+ *
+ * \par Implementation specific behaviour
+ * - As Link establishment procedure is not supported following static link configuration parameters
+ * are used:
+ * + TX window size is 1.
+ * + 16 bit CCITT-CRC must be used.
+ * + Out of frame software flow control not supported.
+ * + Parameters specific for resending reliable packets are compile time configurable (clarifed
+ * later in this document).
+ * + Acknowledgement packet transmissions are not timeout driven , meaning they are delivered for
+ * transmission within same context which the corresponding application packet was received.
+ *
+ * \par Implementation specific limitations
+ * Current implementation has the following limitations which will have impact to system wide
+ * behaviour:
+ * - Delayed acknowledgement scheduling not implemented:
+ * There exists a possibility that acknowledgement TX packet and application TX packet will collide
+ * in the TX pipeline having the end result that acknowledgement packet will be excluded from the TX
+ * pipeline which will trigger the retransmission algorithm within the peer protocol entity.
+ * - Delayed retransmission scheduling not implemented:
+ * There exists a possibility that retransmitted application TX packet and acknowledgement TX packet
+ * will collide in the TX pipeline having the end result that retransmitted application TX packet
+ * will be excluded from the TX pipeline.
+ * - Processing of the acknowledgement number from RX application packets:
+ * Acknowledgement number is not processed from the RX application packets having the end result
+ * that unnecessary application packet retransmissions can occur.
+ *
+ * The application TX packet processing flow is illustrated by the statemachine below.
+ *
+ * @image html hci_transport_tx_sm.png "TX - application packet statemachine"
+ *
+ * \par Component specific configuration options
+ *
+ * The following compile time configuration options are available, and used to configure the
+ * application TX packet retransmission interval, in order to suite various application specific
+ * implementations:
+ * - MAC_PACKET_SIZE_IN_BITS Maximum size of a single application packet in bits.
+ * - USED_BAUD_RATE Used uart baudrate.
+ *
+ * The following compile time configuration option is available to configure module specific
+ * behaviour:
+ * - MAX_RETRY_COUNT Max retransmission retry count for applicaton packets.
+ */
+
+#ifndef HCI_TRANSPORT_H__
+#define HCI_TRANSPORT_H__
+
+#include <stdint.h>
+#include "nrf_error.h"
+
+#define HCI_TRANSPORT_PKT_HEADER_SIZE (2) /**< Size of transport packet header */
+
+/**@brief Generic event callback function events. */
+typedef enum
+{
+ HCI_TRANSPORT_RX_RDY, /**< An event indicating that RX packet is ready for read. */
+ HCI_TRANSPORT_EVT_TYPE_MAX /**< Enumeration upper bound. */
+} hci_transport_evt_type_t;
+
+/**@brief Struct containing events from the Transport layer.
+ */
+typedef struct
+{
+ hci_transport_evt_type_t evt_type; /**< Type of event. */
+} hci_transport_evt_t;
+
+/**@brief Transport layer generic event callback function type.
+ *
+ * @param[in] event Transport layer event.
+ */
+typedef void (*hci_transport_event_handler_t)(hci_transport_evt_t event);
+
+/**@brief TX done event callback function result codes. */
+typedef enum
+{
+ HCI_TRANSPORT_TX_DONE_SUCCESS, /**< Transmission success, peer transport entity has acknowledged the transmission. */
+ HCI_TRANSPORT_TX_DONE_FAILURE /**< Transmission failure. */
+} hci_transport_tx_done_result_t;
+
+/**@brief Transport layer TX done event callback function type.
+ *
+ * @param[in] result TX done event result code.
+ */
+typedef void (*hci_transport_tx_done_handler_t)(hci_transport_tx_done_result_t result);
+
+/**@brief Function for registering a generic event handler.
+ *
+ * @note Multiple registration requests will overwrite any possible existing registration.
+ *
+ * @param[in] event_handler The function to be called by the transport layer upon an event.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_evt_handler_reg(hci_transport_event_handler_t event_handler);
+
+/**@brief Function for registering a handler for TX done event.
+ *
+ * @note Multiple registration requests will overwrite any possible existing registration.
+ *
+ * @param[in] event_handler The function to be called by the transport layer upon TX done
+ * event.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_tx_done_register(hci_transport_tx_done_handler_t event_handler);
+
+/**@brief Function for opening the transport channel and initializing the transport layer.
+ *
+ * @warning Must not be called for a channel which has been allready opened.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_INTERNAL Operation failure. Internal error ocurred.
+ */
+uint32_t hci_transport_open(void);
+
+/**@brief Function for closing the transport channel.
+ *
+ * @note Can be called multiple times and also for not opened channel.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_transport_close(void);
+
+/**@brief Function for allocating tx packet memory.
+ *
+ * @param[out] pp_memory Pointer to the packet data.
+ *
+ * @retval NRF_SUCCESS Operation success. Memory was allocated.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No memory available.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_tx_alloc(uint8_t ** pp_memory);
+
+/**@brief Function for freeing tx packet memory.
+ *
+ * @note Memory management works in FIFO principle meaning that free order must match the alloc
+ * order.
+ *
+ * @retval NRF_SUCCESS Operation success. Memory was freed.
+ */
+uint32_t hci_transport_tx_free(void);
+
+/**@brief Function for writing a packet.
+ *
+ * @note Completion of this method does not guarantee that actual peripheral transmission would
+ * have completed.
+ *
+ * @note In case of 0 byte packet length write request, message will consist of only transport
+ * module specific headers.
+ *
+ * @note The buffer provided to this function must be allocated through @ref hci_transport_tx_alloc
+ * function.
+ *
+ * @retval NRF_SUCCESS Operation success. Packet was added to the transmission queue
+ * and an event will be send upon transmission completion.
+ * @retval NRF_ERROR_NO_MEM Operation failure. Transmission queue is full and packet was not
+ * added to the transmission queue. User should wait for
+ * a appropriate event prior issuing this operation again.
+ * @retval NRF_ERROR_DATA_SIZE Operation failure. Packet size exceeds limit.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ * @retval NRF_ERROR_INVALID_STATE Operation failure. Channel is not open.
+ * @retval NRF_ERROR_INVALID_ADDR Operation failure. Buffer provided is not allocated through
+ * hci_transport_tx_alloc function.
+ */
+uint32_t hci_transport_pkt_write(const uint8_t * p_buffer, uint16_t length);
+
+/**@brief Function for extracting received packet.
+ *
+ * @note Extracted memory can't be reused by the underlying transport layer untill freed by call to
+ * hci_transport_rx_pkt_consume().
+ *
+ * @param[out] pp_buffer Pointer to the packet data.
+ * @param[out] p_length Length of packet data in bytes.
+ *
+ * @retval NRF_SUCCESS Operation success. Packet was extracted.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to extract.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_rx_pkt_extract(uint8_t ** pp_buffer, uint16_t * p_length);
+
+/**@brief Function for consuming extracted packet described by p_buffer.
+ *
+ * RX memory pointed to by p_buffer is freed and can be reused by the underlying transport layer.
+ *
+ * @param[in] p_buffer Pointer to the buffer that has been consumed.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to consume.
+ * @retval NRF_ERROR_INVALID_ADDR Operation failure. Not a valid pointer.
+ */
+uint32_t hci_transport_rx_pkt_consume(uint8_t * p_buffer);
+
+#endif // HCI_TRANSPORT_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_RBLAB_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_mem_pool.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,132 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup memory_pool Memory pool
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Memory pool implementation
+ *
+ * Memory pool implementation, based on circular buffer data structure, which supports asynchronous
+ * processing of RX data. The current default implementation supports 1 TX buffer and 4 RX buffers.
+ * The memory managed by the pool is allocated from static storage instead of heap. The internal
+ * design of the circular buffer implementing the RX memory layout is illustrated in the picture
+ * below.
+ *
+ * @image html memory_pool.png "Circular buffer design"
+ *
+ * The expected call order for the RX APIs is as follows:
+ * - hci_mem_pool_rx_produce
+ * - hci_mem_pool_rx_data_size_set
+ * - hci_mem_pool_rx_extract
+ * - hci_mem_pool_rx_consume
+ *
+ * @warning If the above mentioned expected call order is violated the end result can be undefined.
+ *
+ * \par Component specific configuration options
+ *
+ * The following compile time configuration options are available to suit various implementations:
+ * - TX_BUF_SIZE TX buffer size in bytes.
+ * - RX_BUF_SIZE RX buffer size in bytes.
+ * - RX_BUF_QUEUE_SIZE RX buffer element size.
+ */
+
+#ifndef HCI_MEM_POOL_H__
+#define HCI_MEM_POOL_H__
+
+#include <stdint.h>
+#include "nrf_error.h"
+
+/**@brief Function for opening the module.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_mem_pool_open(void);
+
+/**@brief Function for closing the module.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_mem_pool_close(void);
+
+/**@brief Function for allocating requested amount of TX memory.
+ *
+ * @param[out] pp_buffer Pointer to the allocated memory.
+ *
+ * @retval NRF_SUCCESS Operation success. Memory was allocated.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No memory available for allocation.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_mem_pool_tx_alloc(void ** pp_buffer);
+
+/**@brief Function for freeing previously allocated TX memory.
+ *
+ * @note Memory management follows the FIFO principle meaning that free() order must match the
+ * alloc(...) order, which is the reason for omitting exact memory block identifier as an
+ * input parameter.
+ *
+ * @retval NRF_SUCCESS Operation success. Memory was freed.
+ */
+uint32_t hci_mem_pool_tx_free(void);
+
+/**@brief Function for producing a free RX memory block for usage.
+ *
+ * @note Upon produce request amount being 0, NRF_SUCCESS is returned.
+ *
+ * @param[in] length Amount, in bytes, of free memory to be produced.
+ * @param[out] pp_buffer Pointer to the allocated memory.
+ *
+ * @retval NRF_SUCCESS Operation success. Free RX memory block produced.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No suitable memory available for allocation.
+ * @retval NRF_ERROR_DATA_SIZE Operation failure. Request size exceeds limit.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_mem_pool_rx_produce(uint32_t length, void ** pp_buffer);
+
+/**@brief Function for setting the length of the last produced RX memory block.
+ *
+ * @warning If call to this API is omitted the end result is that the following call to
+ * mem_pool_rx_extract will return incorrect data in the p_length output parameter.
+ *
+ * @param[in] length Amount, in bytes, of actual memory used.
+ *
+ * @retval NRF_SUCCESS Operation success. Length was set.
+ */
+uint32_t hci_mem_pool_rx_data_size_set(uint32_t length);
+
+/**@brief Function for extracting a packet, which has been filled with read data, for further
+ * processing.
+ *
+ * @param[out] pp_buffer Pointer to the packet data.
+ * @param[out] p_length Length of packet data in bytes.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to extract.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_mem_pool_rx_extract(uint8_t ** pp_buffer, uint32_t * p_length);
+
+/**@brief Function for freeing previously extracted packet, which has been filled with read data.
+ *
+ * @param[in] p_buffer Pointer to consumed buffer.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to free.
+ * @retval NRF_ERROR_INVALID_ADDR Operation failure. Not a valid pointer.
+ */
+uint32_t hci_mem_pool_rx_consume(uint8_t * p_buffer);
+
+#endif // HCI_MEM_POOL_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_RBLAB_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_mem_pool_internal.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,32 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup memory_pool_internal Memory Pool Internal
+ * @{
+ * @ingroup memory_pool
+ *
+ * @brief Memory pool internal definitions
+ */
+
+#ifndef MEM_POOL_INTERNAL_H__
+#define MEM_POOL_INTERNAL_H__
+
+#define TX_BUF_SIZE 600u /**< TX buffer size in bytes. */
+#define RX_BUF_SIZE TX_BUF_SIZE /**< RX buffer size in bytes. */
+
+#define RX_BUF_QUEUE_SIZE 4u /**< RX buffer element size. */
+
+#endif // MEM_POOL_INTERNAL_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_RBLAB_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_slip.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,129 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/** @file
+ *
+ * @defgroup hci_slip SLIP module
+ * @{
+ * @ingroup app_common
+ *
+ * @brief SLIP layer for supporting packet framing in HCI transport.
+ *
+ * @details This module implements SLIP packet framing as described in the Bluetooth Core
+ * Specification 4.0, Volume 4, Part D, Chapter 3 SLIP Layer.
+ *
+ * SLIP framing ensures that all packets sent on the UART are framed as:
+ * <0xC0> SLIP packet 1 <0xC0> <0xC0> SLIP packet 2 <0xC0>.
+ *
+ * The SLIP layer uses events to notify the upper layer when data transmission is complete
+ * and when a SLIP packet is received.
+ */
+
+#ifndef HCI_SLIP_H__
+#define HCI_SLIP_H__
+
+#include <stdint.h>
+
+/**@brief Event types from the SLIP Layer. */
+typedef enum
+{
+ HCI_SLIP_RX_RDY, /**< An event indicating that an RX packet is ready to be read. */
+ HCI_SLIP_TX_DONE, /**< An event indicating write completion of the TX packet provided in the function call \ref hci_slip_write . */
+ HCI_SLIP_RX_OVERFLOW, /**< An event indicating that RX data has been discarded due to lack of free RX memory. */
+ HCI_SLIP_ERROR, /**< An event indicating that an unrecoverable error has occurred. */
+ HCI_SLIP_EVT_TYPE_MAX /**< Enumeration upper bound. */
+} hci_slip_evt_type_t;
+
+/**@brief Structure containing an event from the SLIP layer.
+ */
+typedef struct
+{
+ hci_slip_evt_type_t evt_type; /**< Type of event. */
+ const uint8_t * packet; /**< This field contains a pointer to the packet for which the event relates, i.e. SLIP_TX_DONE: the packet transmitted, SLIP_RX_RDY: the packet received, SLIP_RX_OVERFLOW: The packet which overflow/or NULL if no receive buffer is available. */
+ uint32_t packet_length; /**< Packet length, i.e. SLIP_TX_DONE: Bytes transmitted, SLIP_RX_RDY: Bytes received, SLIP_RX_OVERFLOW: index at which the packet overflowed. */
+} hci_slip_evt_t;
+
+/**@brief Function for the SLIP layer event callback.
+ */
+typedef void (*hci_slip_event_handler_t)(hci_slip_evt_t event);
+
+/**@brief Function for registering the event handler provided as parameter and this event handler
+ * will be used by SLIP layer to send events described in \ref hci_slip_evt_type_t.
+ *
+ * @note Multiple registration requests will overwrite any existing registration.
+ *
+ * @param[in] event_handler This function is called by the SLIP layer upon an event.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_slip_evt_handler_register(hci_slip_event_handler_t event_handler);
+
+/**@brief Function for opening the SLIP layer. This function must be called before
+ * \ref hci_slip_write and before any data can be received.
+ *
+ * @note Can be called multiple times.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ *
+ * The SLIP layer module will propagate errors from underlying sub-modules.
+ * This implementation is using UART module as a physical transmission layer, and hci_slip_open
+ * executes \ref app_uart_init . For an extended error list, please refer to \ref app_uart_init .
+ */
+uint32_t hci_slip_open(void);
+
+/**@brief Function for closing the SLIP layer. After this function is called no data can be
+ * transmitted or received in this layer.
+ *
+ * @note This function can be called multiple times and also for an unopened channel.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_slip_close(void);
+
+/**@brief Function for writing a packet with SLIP encoding. Packet transmission is confirmed when
+ * the HCI_SLIP_TX_DONE event is received by the function caller.
+ *
+ * @param[in] p_buffer Pointer to the packet to transmit.
+ * @param[in] length Packet length, in bytes.
+ *
+ * @retval NRF_SUCCESS Operation success. Packet was encoded and added to the
+ * transmission queue and an event will be sent upon transmission
+ * completion.
+ * @retval NRF_ERROR_NO_MEM Operation failure. Transmission queue is full and packet was not
+ * added to the transmission queue. Application shall wait for
+ * the \ref HCI_SLIP_TX_DONE event. After HCI_SLIP_TX_DONE this
+ * function can be executed for transmission of next packet.
+ * @retval NRF_ERROR_INVALID_ADDR If a NULL pointer is provided.
+ * @retval NRF_ERROR_INVALID_STATE Operation failure. Module is not open.
+ */
+uint32_t hci_slip_write(const uint8_t * p_buffer, uint32_t length);
+
+/**@brief Function for registering a receive buffer. The receive buffer will be used for storage of
+ * received and SLIP decoded data.
+ * No data can be received by the SLIP layer until a receive buffer has been registered.
+ *
+ * @note The lifetime of the buffer must be valid during complete reception of data. A static
+ * buffer is recommended.
+ *
+ * @warning Multiple registration requests will overwrite any existing registration.
+ *
+ * @param[in] p_buffer Pointer to receive buffer. The received and SLIP decoded packet
+ * will be placed in this buffer.
+ * @param[in] length Buffer length, in bytes.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_slip_rx_buffer_register(uint8_t * p_buffer, uint32_t length);
+
+#endif // HCI_SLIP_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_RBLAB_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_transport.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,220 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/**@file
+ *
+ * @defgroup hci_transport HCI Transport
+ * @{
+ * @ingroup app_common
+ *
+ * @brief HCI transport module implementation.
+ *
+ * This module implements certain specific features from the three-wire UART transport layer,
+ * defined by the Bluetooth specification version 4.0 [Vol 4] part D.
+ *
+ * \par Features supported
+ * - Transmission and reception of Vendor Specific HCI packet type application packets.
+ * - Transmission and reception of reliable packets: defined by chapter 6 of the specification.
+ *
+ * \par Features not supported
+ * - Link establishment procedure: defined by chapter 8 of the specification.
+ * - Low power: defined by chapter 9 of the specification.
+ *
+ * \par Implementation specific behaviour
+ * - As Link establishment procedure is not supported following static link configuration parameters
+ * are used:
+ * + TX window size is 1.
+ * + 16 bit CCITT-CRC must be used.
+ * + Out of frame software flow control not supported.
+ * + Parameters specific for resending reliable packets are compile time configurable (clarifed
+ * later in this document).
+ * + Acknowledgement packet transmissions are not timeout driven , meaning they are delivered for
+ * transmission within same context which the corresponding application packet was received.
+ *
+ * \par Implementation specific limitations
+ * Current implementation has the following limitations which will have impact to system wide
+ * behaviour:
+ * - Delayed acknowledgement scheduling not implemented:
+ * There exists a possibility that acknowledgement TX packet and application TX packet will collide
+ * in the TX pipeline having the end result that acknowledgement packet will be excluded from the TX
+ * pipeline which will trigger the retransmission algorithm within the peer protocol entity.
+ * - Delayed retransmission scheduling not implemented:
+ * There exists a possibility that retransmitted application TX packet and acknowledgement TX packet
+ * will collide in the TX pipeline having the end result that retransmitted application TX packet
+ * will be excluded from the TX pipeline.
+ * - Processing of the acknowledgement number from RX application packets:
+ * Acknowledgement number is not processed from the RX application packets having the end result
+ * that unnecessary application packet retransmissions can occur.
+ *
+ * The application TX packet processing flow is illustrated by the statemachine below.
+ *
+ * @image html hci_transport_tx_sm.png "TX - application packet statemachine"
+ *
+ * \par Component specific configuration options
+ *
+ * The following compile time configuration options are available, and used to configure the
+ * application TX packet retransmission interval, in order to suite various application specific
+ * implementations:
+ * - MAC_PACKET_SIZE_IN_BITS Maximum size of a single application packet in bits.
+ * - USED_BAUD_RATE Used uart baudrate.
+ *
+ * The following compile time configuration option is available to configure module specific
+ * behaviour:
+ * - MAX_RETRY_COUNT Max retransmission retry count for applicaton packets.
+ */
+
+#ifndef HCI_TRANSPORT_H__
+#define HCI_TRANSPORT_H__
+
+#include <stdint.h>
+#include "nrf_error.h"
+
+/**@brief Generic event callback function events. */
+typedef enum
+{
+ HCI_TRANSPORT_RX_RDY, /**< An event indicating that RX packet is ready for read. */
+ HCI_TRANSPORT_EVT_TYPE_MAX /**< Enumeration upper bound. */
+} hci_transport_evt_type_t;
+
+/**@brief Struct containing events from the Transport layer.
+ */
+typedef struct
+{
+ hci_transport_evt_type_t evt_type; /**< Type of event. */
+} hci_transport_evt_t;
+
+/**@brief Transport layer generic event callback function type.
+ *
+ * @param[in] event Transport layer event.
+ */
+typedef void (*hci_transport_event_handler_t)(hci_transport_evt_t event);
+
+/**@brief TX done event callback function result codes. */
+typedef enum
+{
+ HCI_TRANSPORT_TX_DONE_SUCCESS, /**< Transmission success, peer transport entity has acknowledged the transmission. */
+ HCI_TRANSPORT_TX_DONE_FAILURE /**< Transmission failure. */
+} hci_transport_tx_done_result_t;
+
+/**@brief Transport layer TX done event callback function type.
+ *
+ * @param[in] result TX done event result code.
+ */
+typedef void (*hci_transport_tx_done_handler_t)(hci_transport_tx_done_result_t result);
+
+/**@brief Function for registering a generic event handler.
+ *
+ * @note Multiple registration requests will overwrite any possible existing registration.
+ *
+ * @param[in] event_handler The function to be called by the transport layer upon an event.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_evt_handler_reg(hci_transport_event_handler_t event_handler);
+
+/**@brief Function for registering a handler for TX done event.
+ *
+ * @note Multiple registration requests will overwrite any possible existing registration.
+ *
+ * @param[in] event_handler The function to be called by the transport layer upon TX done
+ * event.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_tx_done_register(hci_transport_tx_done_handler_t event_handler);
+
+/**@brief Function for opening the transport channel and initializing the transport layer.
+ *
+ * @warning Must not be called for a channel which has been allready opened.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_INTERNAL Operation failure. Internal error ocurred.
+ */
+uint32_t hci_transport_open(void);
+
+/**@brief Function for closing the transport channel.
+ *
+ * @note Can be called multiple times and also for not opened channel.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+uint32_t hci_transport_close(void);
+
+/**@brief Function for allocating tx packet memory.
+ *
+ * @param[out] pp_memory Pointer to the packet data.
+ *
+ * @retval NRF_SUCCESS Operation success. Memory was allocated.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No memory available.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_tx_alloc(uint8_t ** pp_memory);
+
+/**@brief Function for freeing tx packet memory.
+ *
+ * @note Memory management works in FIFO principle meaning that free order must match the alloc
+ * order.
+ *
+ * @retval NRF_SUCCESS Operation success. Memory was freed.
+ */
+uint32_t hci_transport_tx_free(void);
+
+/**@brief Function for writing a packet.
+ *
+ * @note Completion of this method does not guarantee that actual peripheral transmission would
+ * have completed.
+ *
+ * @note In case of 0 byte packet length write request, message will consist of only transport
+ * module specific headers.
+ *
+ * @retval NRF_SUCCESS Operation success. Packet was added to the transmission queue
+ * and an event will be send upon transmission completion.
+ * @retval NRF_ERROR_NO_MEM Operation failure. Transmission queue is full and packet was not
+ * added to the transmission queue. User should wait for
+ * a appropriate event prior issuing this operation again.
+ * @retval NRF_ERROR_DATA_SIZE Operation failure. Packet size exceeds limit.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ * @retval NRF_ERROR_INVALID_STATE Operation failure. Channel is not open.
+ */
+uint32_t hci_transport_pkt_write(const uint8_t * p_buffer, uint32_t length);
+
+/**@brief Function for extracting received packet.
+ *
+ * @note Extracted memory can't be reused by the underlying transport layer untill freed by call to
+ * hci_transport_rx_pkt_consume().
+ *
+ * @param[out] pp_buffer Pointer to the packet data.
+ * @param[out] p_length Length of packet data in bytes.
+ *
+ * @retval NRF_SUCCESS Operation success. Packet was extracted.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to extract.
+ * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_transport_rx_pkt_extract(uint8_t ** pp_buffer, uint32_t * p_length);
+
+/**@brief Function for consuming extracted packet described by p_buffer.
+ *
+ * RX memory pointed to by p_buffer is freed and can be reused by the underlying transport layer.
+ *
+ * @param[in] p_buffer Pointer to the buffer that has been consumed.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to consume.
+ * @retval NRF_ERROR_INVALID_ADDR Operation failure. Not a valid pointer.
+ */
+uint32_t hci_transport_rx_pkt_consume(uint8_t * p_buffer);
+
+#endif // HCI_TRANSPORT_H__
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_RBLAB_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/pstorage.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,381 @@
+/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/**@file
+ *
+ * @defgroup persistent_storage Persistent Storage Interface
+ * @{
+ * @ingroup app_common
+ * @brief Abstracted flash interface.
+ *
+ * @details In order to ensure that the SDK and application be moved to alternate persistent storage
+ * options other than the default provided with NRF solution, an abstracted interface is provided
+ * by the module to ensure SDK modules and application can be ported to alternate option with ease.
+ */
+
+#ifndef PSTORAGE_H__
+#define PSTORAGE_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* #ifdef __cplusplus */
+
+#include "pstorage_platform.h"
+
+
+/**@defgroup ps_opcode Persistent Storage Access Operation Codes
+ * @{
+ * @brief Persistent Storage Access Operation Codes. These are used to report any error during
+ * a persistent storage access operation or any general error that may occur in the
+ * interface.
+ *
+ * @details Persistent Storage Access Operation Codes used in error notification callback
+ * registered with the interface to report any error during an persistent storage access
+ * operation or any general error that may occur in the interface.
+ */
+#define PSTORAGE_ERROR_OP_CODE 0x01 /**< General Error Code */
+#define PSTORAGE_STORE_OP_CODE 0x02 /**< Error when Store Operation was requested */
+#define PSTORAGE_LOAD_OP_CODE 0x03 /**< Error when Load Operation was requested */
+#define PSTORAGE_CLEAR_OP_CODE 0x04 /**< Error when Clear Operation was requested */
+#define PSTORAGE_UPDATE_OP_CODE 0x05 /**< Update an already touched storage block */
+
+/**@} */
+
+/**@defgroup pstorage_data_types Persistent Memory Interface Data Types
+ * @{
+ * @brief Data Types needed for interfacing with persistent memory.
+ *
+ * @details Data Types needed for interfacing with persistent memory.
+ */
+
+/**@brief Persistent Storage Error Reporting Callback
+ *
+ * @details Persistent Storage Error Reporting Callback that is used by the interface to report
+ * success or failure of a flash operation. Therefore, for any operations, application
+ * can know when the procedure was complete. For store operation, since no data copy
+ * is made, receiving a success or failure notification, indicated by the reason
+ * parameter of callback is an indication that the resident memory could now be reused
+ * or freed, as the case may be.
+ *
+ * @param[in] handle Identifies module and block for which callback is received.
+ * @param[in] op_code Identifies the operation for which the event is notified.
+ * @param[in] result Identifies the result of flash access operation.
+ * NRF_SUCCESS implies, operation succeeded.
+ * @param[in] p_data Identifies the application data pointer. In case of store operation, this
+ * points to the resident source of application memory that application can now
+ * free or reuse. In case of clear, this is NULL as no application pointer is
+ * needed for this operation.
+ * @param[in] data_len Length data application had provided for the operation.
+ *
+ */
+typedef void (*pstorage_ntf_cb_t)(pstorage_handle_t * p_handle,
+ uint8_t op_code,
+ uint32_t result,
+ uint8_t * p_data,
+ uint32_t data_len);
+
+
+typedef struct
+{
+ pstorage_ntf_cb_t cb; /**< Callback registered with the module to be notified of any error occurring in persistent memory management */
+ pstorage_size_t block_size; /**< Desired block size for persistent memory storage, for example, if a module has a table with 10 entries, each entry is size 64 bytes,
+ * it can request 10 blocks with block size 64 bytes. On the other hand, the module can also request one block of size 640 based on
+ * how it would like to access or alter memory in persistent memory.
+ * First option is preferred when single entries that need to be updated often when having no impact on the other entries.
+ * While second option is preferred when entries of table are not changed on individually but have common point of loading and storing
+ * data. */
+ pstorage_size_t block_count; /** Number of blocks requested by the module, minimum values is 1. */
+} pstorage_module_param_t;
+
+/**@} */
+
+/**@defgroup pstorage_routines Persistent Storage Access Routines
+ * @{
+ * @brief Functions/Interface SDK modules use to persistently store data.
+ *
+ * @details Interface for Application & SDK module to load/store information persistently.
+ * Note: that while implementation of each of the persistent storage access function
+ * depends on the system and can specific to system/solution, the signature of the
+ * interface routines should not be altered.
+ */
+
+/**@brief Module Initialization Routine.
+ *
+ * @details Initializes module. To be called once before any other APIs of the module are used.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ */
+uint32_t pstorage_init(void);
+
+
+/**@brief Register with persistent storage interface.
+ *
+ * @param[in] p_module_param Module registration param.
+ * @param[out] p_block_id Block identifier to identify persistent memory blocks in case
+ * registration succeeds. Application is expected to use the block ids
+ * for subsequent operations on requested persistent memory. Maximum
+ * registrations permitted is determined by configuration parameter
+ * PSTORAGE_MAX_APPLICATIONS.
+ * In case more than one memory blocks are requested, the identifier provided here is
+ * the base identifier for the first block and to identify subsequent block,
+ * application shall use \@ref pstorage_block_identifier_get with this base identifier
+ * and block number. Therefore if 10 blocks of size 64 are requested and application
+ * wishes to store memory in 6th block, it shall use
+ * \@ref pstorage_block_identifier_get with based id and provide a block number of 5.
+ * This way application is only expected to remember the base block identifier.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_NO_MEM in case no more registrations can be supported.
+ */
+uint32_t pstorage_register(pstorage_module_param_t * p_module_param,
+ pstorage_handle_t * p_block_id);
+
+
+/**
+ * @brief Function to get block id with reference to base block identifier provided at time of
+ * registration.
+ *
+ * @details Function to get block id with reference to base block identifier provided at time of
+ * registration.
+ * In case more than one memory blocks were requested when registering, the identifier
+ * provided here is the base identifier for the first block and to identify subsequent
+ * block, application shall use this routine to get block identifier providing input as
+ * base identifier and block number. Therefore if 10 blocks of size 64 are requested and
+ * application wishes to store memory in 6th block, it shall use
+ * \@ref pstorage_block_identifier_get with based id and provide a block number of 5.
+ * This way application is only expected to remember the base block identifier.
+ *
+ * @param[in] p_base_id Base block id received at the time of registration.
+ * @param[in] block_num Block Number, with first block numbered zero.
+ * @param[out] p_block_id Block identifier for the block number requested in case the API succeeds.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ */
+uint32_t pstorage_block_identifier_get(pstorage_handle_t * p_base_id,
+ pstorage_size_t block_num,
+ pstorage_handle_t * p_block_id);
+
+
+/**@brief Routine to persistently store data of length 'size' contained in 'p_src' address
+ * in storage module at 'p_dest' address; Equivalent to Storage Write.
+ *
+ * @param[in] p_dest Destination address where data is to be stored persistently.
+ * @param[in] p_src Source address containing data to be stored. API assumes this to be resident
+ * memory and no intermediate copy of data is made by the API.
+ * @param[in] size Size of data to be stored expressed in bytes. Should be word aligned.
+ * @param[in] offset Offset in bytes to be applied when writing to the block.
+ * For example, if within a block of 100 bytes, application wishes to
+ * write 20 bytes at offset of 12, then this field should be set to 12.
+ * Should be word aligned.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_src' is not aligned.
+ * @retval NRF_ERROR_NO_MEM in case request cannot be processed.
+ *
+ * @warning No copy of the data is made, and hence memory provided for data source to be written
+ * to flash cannot be freed or reused by the application until this procedure
+ * is complete. End of this procedure is notified to the application using the
+ * notification callback registered by the application.
+ */
+uint32_t pstorage_store(pstorage_handle_t * p_dest,
+ uint8_t * p_src,
+ pstorage_size_t size,
+ pstorage_size_t offset);
+
+/**@brief Routine to update persistently stored data of length 'size' contained in 'p_src' address
+ * in storage module at 'p_dest' address.
+ *
+ * @param[in] p_dest Destination address where data is to be updated.
+ * @param[in] p_src Source address containing data to be stored. API assumes this to be resident
+ * memory and no intermediate copy of data is made by the API.
+ * @param[in] size Size of data to be stored expressed in bytes. Should be word aligned.
+ * @param[in] offset Offset in bytes to be applied when writing to the block.
+ * For example, if within a block of 100 bytes, application wishes to
+ * write 20 bytes at offset of 12, then this field should be set to 12.
+ * Should be word aligned.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_src' is not aligned.
+ * @retval NRF_ERROR_NO_MEM in case request cannot be processed.
+ *
+ * @warning No copy of the data is made, and hence memory provided for data source to be written
+ * to flash cannot be freed or reused by the application until this procedure
+ * is complete. End of this procedure is notified to the application using the
+ * notification callback registered by the application.
+ */
+uint32_t pstorage_update(pstorage_handle_t * p_dest,
+ uint8_t * p_src,
+ pstorage_size_t size,
+ pstorage_size_t offset);
+
+/**@brief Routine to load persistently stored data of length 'size' from 'p_src' address
+ * to 'p_dest' address; Equivalent to Storage Read.
+ *
+ * @param[in] p_dest Destination address where persistently stored data is to be loaded.
+ * @param[in] p_src Source from where data is to be loaded from persistent memory.
+ * @param[in] size Size of data to be loaded from persistent memory expressed in bytes.
+ * Should be word aligned.
+ * @param[in] offset Offset in bytes to be applied when loading from the block.
+ * For example, if within a block of 100 bytes, application wishes to
+ * load 20 bytes from offset of 12, then this field should be set to 12.
+ * Should be word aligned.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_dst' is not aligned.
+ * @retval NRF_ERROR_NO_MEM in case request cannot be processed.
+ */
+uint32_t pstorage_load(uint8_t * p_dest,
+ pstorage_handle_t * p_src,
+ pstorage_size_t size,
+ pstorage_size_t offset);
+
+/**@brief Routine to clear data in persistent memory.
+ *
+ * @param[in] p_base_id Base block identifier in persistent memory that needs to cleared;
+ * Equivalent to an Erase Operation.
+ *
+ * @param[in] size Size of data to be cleared from persistent memory expressed in bytes.
+ * This parameter is to provision for clearing of certain blocks
+ * of memory, or all memory blocks in a registered module. If the total size
+ * of the application module is used (blocks * block size) in combination with
+ * the identifier for the first block in the module, all blocks in the
+ * module will be erased.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_dst' is not aligned.
+ * @retval NRF_ERROR_NO_MEM in case request cannot be processed.
+ *
+ * @note Clear operations may take time. This API however, does not block until the clear
+ * procedure is complete. Application is notified of procedure completion using
+ * notification callback registered by the application. 'result' parameter of the
+ * callback suggests if the procedure was successful or not.
+ */
+uint32_t pstorage_clear(pstorage_handle_t * p_base_id, pstorage_size_t size);
+
+/**
+ * @brief API to get status of number of pending operations with the module.
+ *
+ * @param[out] p_count Number of storage operations pending with the module, if 0,
+ * there are no outstanding requests.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ */
+uint32_t pstorage_access_status_get(uint32_t * p_count);
+
+#ifdef PSTORAGE_RAW_MODE_ENABLE
+
+/**@brief Function for registering with persistent storage interface.
+ *
+ * @param[in] p_module_param Module registration param.
+ * @param[out] p_block_id Block identifier to identify persistent memory blocks in case
+ * registration succeeds. Application is expected to use the block ids
+ * for subsequent operations on requested persistent memory.
+ * In case more than one memory blocks are requested, the identifier provided here is
+ * the base identifier for the first block and to identify subsequent block,
+ * application shall use \@ref pstorage_block_identifier_get with this base identifier
+ * and block number. Therefore if 10 blocks of size 64 are requested and application
+ * wishes to store memory in 6th block, it shall use
+ * \@ref pstorage_block_identifier_get with based id and provide a block number of 5.
+ * This way application is only expected to remember the base block identifier.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_NO_MEM in case no more registrations can be supported.
+ */
+uint32_t pstorage_raw_register(pstorage_module_param_t * p_module_param,
+ pstorage_handle_t * p_block_id);
+
+/**@brief Raw mode function for persistently storing data of length 'size' contained in 'p_src'
+ * address in storage module at 'p_dest' address; Equivalent to Storage Write.
+ *
+ * @param[in] p_dest Destination address where data is to be stored persistently.
+ * @param[in] p_src Source address containing data to be stored. API assumes this to be resident
+ * memory and no intermediate copy of data is made by the API.
+ * @param[in] size Size of data to be stored expressed in bytes. Should be word aligned.
+ * @param[in] offset Offset in bytes to be applied when writing to the block.
+ * For example, if within a block of 100 bytes, application wishes to
+ * write 20 bytes at offset of 12, then this field should be set to 12.
+ * Should be word aligned.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_src' is not aligned.
+ * @retval NRF_ERROR_NO_MEM in case request cannot be processed.
+ *
+ * @warning No copy of the data is made, and hence memory provided for data source to be written
+ * to flash cannot be freed or reused by the application until this procedure
+ * is complete. End of this procedure is notified to the application using the
+ * notification callback registered by the application.
+ */
+uint32_t pstorage_raw_store(pstorage_handle_t * p_dest,
+ uint8_t * p_src,
+ pstorage_size_t size,
+ pstorage_size_t offset);
+
+/**@brief Function for clearing data in persistent memory in raw mode.
+ *
+ * @param[in] p_dest Base block identifier in persistent memory that needs to cleared;
+ * Equivalent to an Erase Operation.
+ * @param[in] size Size of data to be cleared from persistent memory expressed in bytes.
+ * This is currently unused. And a clear would mean clearing all blocks,
+ * however, this parameter is to provision for clearing of certain blocks
+ * of memory only and not all if need be.
+ *
+ * @retval NRF_SUCCESS on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization.
+ * @retval NRF_ERROR_NULL if NULL parameter has been passed.
+ * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API.
+ * @retval NRF_ERROR_NO_MEM in case request cannot be processed.
+ *
+ * @note Clear operations may take time. This API however, does not block until the clear
+ * procedure is complete. Application is notified of procedure completion using
+ * notification callback registered by the application. 'result' parameter of the
+ * callback suggests if the procedure was successful or not.
+ */
+uint32_t pstorage_raw_clear(pstorage_handle_t * p_dest, pstorage_size_t size);
+
+#endif // PSTORAGE_RAW_MODE_ENABLE
+
+#ifdef __cplusplus
+}
+#endif /* #ifdef __cplusplus */
+
+
+/**@} */
+/**@} */
+
+#endif // PSTORAGE_H__
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_RBLAB_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/nrf_delay.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,74 @@
+#ifndef _NRF_DELAY_H
+#define _NRF_DELAY_H
+
+// #include "nrf.h"
+
+/*lint --e{438, 522} "Variable not used" "Function lacks side-effects" */
+#if defined ( __CC_ARM )
+static __ASM void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
+{
+loop
+ SUBS R0, R0, #1
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ BNE loop
+ BX LR
+}
+#elif defined ( __ICCARM__ )
+static void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
+{
+__ASM (
+"loop:\n\t"
+ " SUBS R0, R0, #1\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " NOP\n\t"
+ " BNE loop\n\t");
+}
+#elif defined ( __GNUC__ )
+static void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
+{
+ do
+ {
+ __ASM volatile (
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ "NOP\n\t"
+ );
+ } while (--number_of_us);
+}
+#endif
+
+void nrf_delay_ms(uint32_t volatile number_of_ms);
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_RBLAB_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/sd_common/app_util_platform.h Fri Sep 12 16:41:52 2014 +0100
@@ -0,0 +1,110 @@
+/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/**@file
+ *
+ * @defgroup app_util_platform Utility Functions and Definitions (Platform)
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Various types and definitions available to all applications when using SoftDevice.
+ */
+
+#ifndef APP_UTIL_PLATFORM_H__
+#define APP_UTIL_PLATFORM_H__
+
+#include <stdint.h>
+#include "compiler_abstraction.h"
+#include "nrf51.h"
+#include "app_error.h"
+
+/**@brief The interrupt priorities available to the application while the SoftDevice is active. */
+typedef enum
+{
+ APP_IRQ_PRIORITY_HIGH = 1,
+ APP_IRQ_PRIORITY_LOW = 3
+} app_irq_priority_t;
+
+#define NRF_APP_PRIORITY_THREAD 4 /**< "Interrupt level" when running in Thread Mode. */
+
+/**@cond NO_DOXYGEN */
+#define EXTERNAL_INT_VECTOR_OFFSET 16
+/**@endcond */
+
+#define PACKED(TYPE) __packed TYPE
+
+/**@brief Macro for entering a critical region.
+ *
+ * @note Due to implementation details, there must exist one and only one call to
+ * CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located
+ * in the same scope.
+ */
+#define CRITICAL_REGION_ENTER() \
+ { \
+ uint8_t IS_NESTED_CRITICAL_REGION = 0; \
+ uint32_t CURRENT_INT_PRI = current_int_priority_get(); \
+ if (CURRENT_INT_PRI != APP_IRQ_PRIORITY_HIGH) \
+ { \
+ uint32_t ERR_CODE = sd_nvic_critical_region_enter(&IS_NESTED_CRITICAL_REGION); \
+ if (ERR_CODE == NRF_ERROR_SOFTDEVICE_NOT_ENABLED) \
+ { \
+ __disable_irq(); \
+ } \
+ else \
+ { \
+ APP_ERROR_CHECK(ERR_CODE); \
+ } \
+ }
+
+/**@brief Macro for leaving a critical region.
+ *
+ * @note Due to implementation details, there must exist one and only one call to
+ * CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located
+ * in the same scope.
+ */
+#define CRITICAL_REGION_EXIT() \
+ if (CURRENT_INT_PRI != APP_IRQ_PRIORITY_HIGH) \
+ { \
+ uint32_t ERR_CODE; \
+ __enable_irq(); \
+ ERR_CODE = sd_nvic_critical_region_exit(IS_NESTED_CRITICAL_REGION); \
+ if (ERR_CODE != NRF_ERROR_SOFTDEVICE_NOT_ENABLED) \
+ { \
+ APP_ERROR_CHECK(ERR_CODE); \
+ } \
+ } \
+ }
+
+/**@brief Function for finding the current interrupt level.
+ *
+ * @return Current interrupt level.
+ * @retval APP_IRQ_PRIORITY_HIGH We are running in Application High interrupt level.
+ * @retval APP_IRQ_PRIORITY_LOW We are running in Application Low interrupt level.
+ * @retval APP_IRQ_PRIORITY_THREAD We are running in Thread Mode.
+ */
+static __INLINE uint8_t current_int_priority_get(void)
+{
+ uint32_t isr_vector_num = (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk);
+ if (isr_vector_num > 0)
+ {
+ int32_t irq_type = ((int32_t)isr_vector_num - EXTERNAL_INT_VECTOR_OFFSET);
+ return (NVIC_GetPriority((IRQn_Type)irq_type) & 0xFF);
+ }
+ else
+ {
+ return NRF_APP_PRIORITY_THREAD;
+ }
+}
+
+#endif // APP_UTIL_PLATFORM_H__
+
+/** @} */
--- a/TARGET_RBLAB_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_0_0/s110_nrf51822_7.0.0_API/include/nrf_svc.h Fri Aug 15 15:28:31 2014 +0100
+++ b/TARGET_RBLAB_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_7_0_0/s110_nrf51822_7.0.0_API/include/nrf_svc.h Fri Sep 12 16:41:52 2014 +0100
@@ -16,7 +16,7 @@
{ \
__asm( \
"svc %0\n" \
- "bx r14" : : "I" (number) : "r0" \
+ "bx r14" : : "I" ((uint32_t)number) : "r0" \
); \
}
#elif defined (__ICCARM__)
--- a/TARGET_RBLAB_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_RBLAB_NRF51822/PinNames.h Fri Aug 15 15:28:31 2014 +0100
+++ b/TARGET_RBLAB_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_RBLAB_NRF51822/PinNames.h Fri Sep 12 16:41:52 2014 +0100
@@ -98,10 +98,10 @@
P0_29 = p29,
P0_30 = p30,
- LED1 = p18,
- LED2 = p19,
- LED3 = p18,
- LED4 = p19,
+ LED1 = p15,
+ LED2 = p15,
+ LED3 = p15,
+ LED4 = p15,
BUTTON1 = p16,
BUTTON2 = p17,
@@ -117,43 +117,49 @@
SPI_PSELMOSI0 = p20,
SPI_PSELMISO0 = p22,
- SPI_PSELSS0 = p24,
+ SPI_PSELSS0 = p14,
SPI_PSELSCK0 = p25,
- SPI_PSELMOSI1 = p12,
- SPI_PSELMISO1 = p13,
+ SPI_PSELMOSI1 = p20,
+ SPI_PSELMISO1 = p22,
SPI_PSELSS1 = p14,
- SPI_PSELSCK1 = p15,
-
- SPIS_PSELMOSI = p12,
- SPIS_PSELMISO = p13,
+ SPI_PSELSCK1 = p25,
+
+ SPIS_PSELMOSI = p20,
+ SPIS_PSELMISO = p22,
SPIS_PSELSS = p14,
- SPIS_PSELSCK = p15,
+ SPIS_PSELSCK = p25,
+
+ I2C_SDA0 = p29,
+ I2C_SCL0 = p28,
- I2C_SDA0 = p22,
- I2C_SCL0 = p20,
-
+/*
I2C_SDA1 = p13,
- I2C_SCL1 = p15,
-
- D0 = p7,
- D1 = p8,
- D2 = p9,
- D3 = p10,
- D4 = p11,
- D5 = p12,
- D6 = p13,
+ I2C_SCL1 = p15,
+*/
+
+ D0 = p11,
+ D1 = p9,
+ D2 = p10,
+ D3 = p8,
+ D4 = p21,
+ D5 = p23,
+ D6 = p16,
D7 = p17,
- D8 = p18,
- D9 = p23,
- D10 = p24,
- D11 = p25,
- D12 = p28,
- D13 = p29,
+ D8 = p19,
+ D9 = p18,
+ D10 = p14,
+ D11 = p12,
+ D12 = p13,
+ D13 = p15,
- D14 = p5,
- D15 = p6,
+ D14 = p29, // I2C - SDA
+ D15 = p28, // I2C - SCL
+
+ D16 = p25, // SPI - SCK
+ D17 = p22, // SPI - MISO
+ D18 = p20, // SPI - MOSI
A0 = p1,
A1 = p2,
@@ -162,6 +168,13 @@
A4 = p5,
A5 = p6,
+ D19 = A0,
+ D20 = A1,
+ D21 = A2,
+ D22 = A3,
+ D23 = A4,
+ D24 = A5,
+
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
--- a/TARGET_RBLAB_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/objects.h Fri Aug 15 15:28:31 2014 +0100
+++ b/TARGET_RBLAB_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/objects.h Fri Sep 12 16:41:52 2014 +0100
@@ -53,6 +53,7 @@
PinName sda;
PinName scl;
int freq;
+ uint8_t address_set;
};
struct analogin_s {
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--- a/Ticker.h Fri Aug 15 15:28:31 2014 +0100
+++ b/Ticker.h Fri Sep 12 16:41:52 2014 +0100
@@ -83,7 +83,7 @@
* @param fptr pointer to the function to be called
* @param t the time between calls in micro-seconds
*/
- void attach_us(void (*fptr)(void), unsigned int t) {
+ void attach_us(void (*fptr)(void), timestamp_t t) {
_function.attach(fptr);
setup(t);
}
@@ -95,21 +95,26 @@
* @param t the time between calls in micro-seconds
*/
template<typename T>
- void attach_us(T* tptr, void (T::*mptr)(void), unsigned int t) {
+ void attach_us(T* tptr, void (T::*mptr)(void), timestamp_t t) {
_function.attach(tptr, mptr);
setup(t);
}
+ virtual ~Ticker() {
+ detach();
+ }
+
/** Detach the function
*/
void detach();
protected:
- void setup(unsigned int t);
+ void setup(timestamp_t t);
virtual void handler();
- unsigned int _delay;
- FunctionPointer _function;
+protected:
+ timestamp_t _delay; /**< Time delay (in microseconds) for re-setting the multi-shot callback. */
+ FunctionPointer _function; /**< Callback. */
};
} // namespace mbed
--- a/TimerEvent.h Fri Aug 15 15:28:31 2014 +0100
+++ b/TimerEvent.h Fri Sep 12 16:41:52 2014 +0100
@@ -39,7 +39,7 @@
virtual void handler() = 0;
// insert in to linked list
- void insert(unsigned int timestamp);
+ void insert(timestamp_t timestamp);
// remove from linked list, if in it
void remove();
--- a/mbed.h Fri Aug 15 15:28:31 2014 +0100 +++ b/mbed.h Fri Sep 12 16:41:52 2014 +0100 @@ -16,7 +16,7 @@ #ifndef MBED_H #define MBED_H -#define MBED_LIBRARY_VERSION 88 +#define MBED_LIBRARY_VERSION 89 #include "platform.h"
--- a/us_ticker_api.h Fri Aug 15 15:28:31 2014 +0100
+++ b/us_ticker_api.h Fri Sep 12 16:41:52 2014 +0100
@@ -22,24 +22,26 @@
extern "C" {
#endif
+typedef uint64_t timestamp_t;
+
uint32_t us_ticker_read(void);
typedef void (*ticker_event_handler)(uint32_t id);
void us_ticker_set_handler(ticker_event_handler handler);
typedef struct ticker_event_s {
- uint32_t timestamp;
- uint32_t id;
+ timestamp_t timestamp;
+ uint32_t id;
struct ticker_event_s *next;
} ticker_event_t;
void us_ticker_init(void);
-void us_ticker_set_interrupt(unsigned int timestamp);
+void us_ticker_set_interrupt(timestamp_t timestamp);
void us_ticker_disable_interrupt(void);
void us_ticker_clear_interrupt(void);
void us_ticker_irq_handler(void);
-void us_ticker_insert_event(ticker_event_t *obj, unsigned int timestamp, uint32_t id);
+void us_ticker_insert_event(ticker_event_t *obj, timestamp_t timestamp, uint32_t id);
void us_ticker_remove_event(ticker_event_t *obj);
#ifdef __cplusplus